Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Lanai/LanaiGenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
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|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace Lanai {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
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    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
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    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
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    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
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    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
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    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
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    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
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    G_FCONSTANT = 121,
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    G_VASTART = 122,
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    G_VAARG = 123,
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    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
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    G_ZEXT  = 126,
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    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
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    G_ROTR  = 132,
148
    G_ROTL  = 133,
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    G_ICMP  = 134,
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    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
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    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
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    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
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    G_UMULFIXSAT  = 158,
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    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
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    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
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    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
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    G_FPOWI = 171,
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    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
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    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
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    G_FLDEXP  = 178,
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    G_FFREXP  = 179,
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    G_FNEG  = 180,
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    G_FPEXT = 181,
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    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
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    G_IS_FPCLASS  = 189,
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    G_FCANONICALIZE = 190,
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    G_FMINNUM = 191,
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    G_FMAXNUM = 192,
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    G_FMINNUM_IEEE  = 193,
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    G_FMAXNUM_IEEE  = 194,
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    G_FMINIMUM  = 195,
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    G_FMAXIMUM  = 196,
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    G_GET_FPENV = 197,
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    G_SET_FPENV = 198,
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    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
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    G_SET_FPMODE  = 201,
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    G_RESET_FPMODE  = 202,
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    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
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    G_SMAX  = 206,
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    G_UMIN  = 207,
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    G_UMAX  = 208,
224
    G_ABS = 209,
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    G_LROUND  = 210,
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    G_LLROUND = 211,
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    G_BR  = 212,
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    G_BRJT  = 213,
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    G_INSERT_VECTOR_ELT = 214,
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    G_EXTRACT_VECTOR_ELT  = 215,
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    G_SHUFFLE_VECTOR  = 216,
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    G_CTTZ  = 217,
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    G_CTTZ_ZERO_UNDEF = 218,
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    G_CTLZ  = 219,
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    G_CTLZ_ZERO_UNDEF = 220,
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    G_CTPOP = 221,
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    G_BSWAP = 222,
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    G_BITREVERSE  = 223,
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    G_FCEIL = 224,
240
    G_FCOS  = 225,
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    G_FSIN  = 226,
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    G_FSQRT = 227,
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    G_FFLOOR  = 228,
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    G_FRINT = 229,
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    G_FNEARBYINT  = 230,
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    G_ADDRSPACE_CAST  = 231,
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    G_BLOCK_ADDR  = 232,
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    G_JUMP_TABLE  = 233,
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    G_DYN_STACKALLOC  = 234,
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    G_STACKSAVE = 235,
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    G_STACKRESTORE  = 236,
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    G_STRICT_FADD = 237,
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    G_STRICT_FSUB = 238,
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    G_STRICT_FMUL = 239,
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    G_STRICT_FDIV = 240,
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    G_STRICT_FREM = 241,
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    G_STRICT_FMA  = 242,
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    G_STRICT_FSQRT  = 243,
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    G_STRICT_FLDEXP = 244,
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    G_READ_REGISTER = 245,
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    G_WRITE_REGISTER  = 246,
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    G_MEMCPY  = 247,
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    G_MEMCPY_INLINE = 248,
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    G_MEMMOVE = 249,
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    G_MEMSET  = 250,
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    G_BZERO = 251,
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    G_VECREDUCE_SEQ_FADD  = 252,
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    G_VECREDUCE_SEQ_FMUL  = 253,
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    G_VECREDUCE_FADD  = 254,
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    G_VECREDUCE_FMUL  = 255,
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    G_VECREDUCE_FMAX  = 256,
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    G_VECREDUCE_FMIN  = 257,
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    G_VECREDUCE_FMAXIMUM  = 258,
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    G_VECREDUCE_FMINIMUM  = 259,
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    G_VECREDUCE_ADD = 260,
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    G_VECREDUCE_MUL = 261,
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    G_VECREDUCE_AND = 262,
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    G_VECREDUCE_OR  = 263,
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    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
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    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
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    G_SBFX  = 269,
285
    G_UBFX  = 270,
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    ADJCALLSTACKDOWN  = 271,
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    ADJCALLSTACKUP  = 272,
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    ADJDYNALLOC = 273,
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    CALL  = 274,
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    CALLR = 275,
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    ADDC_F_I_HI = 276,
292
    ADDC_F_I_LO = 277,
293
    ADDC_F_R  = 278,
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    ADDC_I_HI = 279,
295
    ADDC_I_LO = 280,
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    ADDC_R  = 281,
297
    ADD_F_I_HI  = 282,
298
    ADD_F_I_LO  = 283,
299
    ADD_F_R = 284,
300
    ADD_I_HI  = 285,
301
    ADD_I_LO  = 286,
302
    ADD_R = 287,
303
    AND_F_I_HI  = 288,
304
    AND_F_I_LO  = 289,
305
    AND_F_R = 290,
306
    AND_I_HI  = 291,
307
    AND_I_LO  = 292,
308
    AND_R = 293,
309
    BRCC  = 294,
310
    BRIND_CC  = 295,
311
    BRIND_CCA = 296,
312
    BRR = 297,
313
    BT  = 298,
314
    JR  = 299,
315
    LDADDR  = 300,
316
    LDBs_RI = 301,
317
    LDBs_RR = 302,
318
    LDBz_RI = 303,
319
    LDBz_RR = 304,
320
    LDHs_RI = 305,
321
    LDHs_RR = 306,
322
    LDHz_RI = 307,
323
    LDHz_RR = 308,
324
    LDW_RI  = 309,
325
    LDW_RR  = 310,
326
    LDWz_RR = 311,
327
    LEADZ = 312,
328
    LOG0  = 313,
329
    LOG1  = 314,
330
    LOG2  = 315,
331
    LOG3  = 316,
332
    LOG4  = 317,
333
    MOVHI = 318,
334
    NOP = 319,
335
    OR_F_I_HI = 320,
336
    OR_F_I_LO = 321,
337
    OR_F_R  = 322,
338
    OR_I_HI = 323,
339
    OR_I_LO = 324,
340
    OR_R  = 325,
341
    POPC  = 326,
342
    RET = 327,
343
    SA_F_I  = 328,
344
    SA_I  = 329,
345
    SCC = 330,
346
    SELECT  = 331,
347
    SFSUB_F_RI_HI = 332,
348
    SFSUB_F_RI_LO = 333,
349
    SFSUB_F_RR  = 334,
350
    SHL_F_R = 335,
351
    SHL_R = 336,
352
    SLI = 337,
353
    SL_F_I  = 338,
354
    SL_I  = 339,
355
    SRA_F_R = 340,
356
    SRA_R = 341,
357
    SRL_F_R = 342,
358
    SRL_R = 343,
359
    STADDR  = 344,
360
    STB_RI  = 345,
361
    STB_RR  = 346,
362
    STH_RI  = 347,
363
    STH_RR  = 348,
364
    SUBB_F_I_HI = 349,
365
    SUBB_F_I_LO = 350,
366
    SUBB_F_R  = 351,
367
    SUBB_I_HI = 352,
368
    SUBB_I_LO = 353,
369
    SUBB_R  = 354,
370
    SUB_F_I_HI  = 355,
371
    SUB_F_I_LO  = 356,
372
    SUB_F_R = 357,
373
    SUB_I_HI  = 358,
374
    SUB_I_LO  = 359,
375
    SUB_R = 360,
376
    SW_RI = 361,
377
    SW_RR = 362,
378
    TRAILZ  = 363,
379
    XOR_F_I_HI  = 364,
380
    XOR_F_I_LO  = 365,
381
    XOR_F_R = 366,
382
    XOR_I_HI  = 367,
383
    XOR_I_LO  = 368,
384
    XOR_R = 369,
385
    INSTRUCTION_LIST_END = 370
386
  };
387
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} // end namespace Lanai
389
} // end namespace llvm
390
#endif // GET_INSTRINFO_ENUM
391
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#ifdef GET_INSTRINFO_SCHED_ENUM
393
#undef GET_INSTRINFO_SCHED_ENUM
394
namespace llvm {
395
396
namespace Lanai {
397
namespace Sched {
398
  enum {
399
    NoInstrModel  = 0,
400
    IIC_ALU_WriteALU  = 1,
401
    IIC_ALU = 2,
402
    IIC_LD_WriteLD  = 3,
403
    IIC_LDSW_WriteLDSW  = 4,
404
    WriteLD = 5,
405
    IIC_ST_WriteST  = 6,
406
    IIC_STSW_WriteSTSW  = 7,
407
    SCHED_LIST_END = 8
408
  };
409
} // end namespace Sched
410
} // end namespace Lanai
411
} // end namespace llvm
412
#endif // GET_INSTRINFO_SCHED_ENUM
413
414
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
415
namespace llvm {
416
417
struct LanaiInstrTable {
418
  MCInstrDesc Insts[370];
419
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
420
  MCOperandInfo OperandInfo[166];
421
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
422
  MCPhysReg ImplicitOps[8];
423
};
424
425
} // end namespace llvm
426
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
427
428
#ifdef GET_INSTRINFO_MC_DESC
429
#undef GET_INSTRINFO_MC_DESC
430
namespace llvm {
431
432
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
433
static constexpr unsigned LanaiImpOpBase = sizeof LanaiInstrTable::OperandInfo / (sizeof(MCPhysReg));
434
435
extern const LanaiInstrTable LanaiDescs = {
436
  {
437
    { 369,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = XOR_R
438
    { 368,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = XOR_I_LO
439
    { 367,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = XOR_I_HI
440
    { 366,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = XOR_F_R
441
    { 365,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = XOR_F_I_LO
442
    { 364,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = XOR_F_I_HI
443
    { 363,  2,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 140,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = TRAILZ
444
    { 362,  4,  0,  4,  6,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = SW_RR
445
    { 361,  4,  0,  4,  6,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = SW_RI
446
    { 360,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = SUB_R
447
    { 359,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = SUB_I_LO
448
    { 358,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = SUB_I_HI
449
    { 357,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = SUB_F_R
450
    { 356,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = SUB_F_I_LO
451
    { 355,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = SUB_F_I_HI
452
    { 354,  4,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = SUBB_R
453
    { 353,  3,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = SUBB_I_LO
454
    { 352,  3,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = SUBB_I_HI
455
    { 351,  4,  1,  4,  1,  1,  1,  LanaiImpOpBase + 4, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = SUBB_F_R
456
    { 350,  3,  1,  4,  1,  1,  1,  LanaiImpOpBase + 4, 143,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = SUBB_F_I_LO
457
    { 349,  3,  1,  4,  1,  1,  1,  LanaiImpOpBase + 4, 143,  0|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = SUBB_F_I_HI
458
    { 348,  4,  0,  4,  6,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = STH_RR
459
    { 347,  4,  0,  4,  7,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = STH_RI
460
    { 346,  4,  0,  4,  6,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = STB_RR
461
    { 345,  4,  0,  4,  7,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = STB_RI
462
    { 344,  2,  0,  4,  6,  0,  0,  LanaiImpOpBase + 0, 150,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = STADDR
463
    { 343,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = SRL_R
464
    { 342,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = SRL_F_R
465
    { 341,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = SRA_R
466
    { 340,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = SRA_F_R
467
    { 339,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = SL_I
468
    { 338,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = SL_F_I
469
    { 337,  2,  1,  4,  0,  0,  0,  LanaiImpOpBase + 0, 150,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = SLI
470
    { 336,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = SHL_R
471
    { 335,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = SHL_F_R
472
    { 334,  2,  0,  4,  1,  0,  1,  LanaiImpOpBase + 6, 140,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = SFSUB_F_RR
473
    { 333,  2,  0,  4,  1,  0,  1,  LanaiImpOpBase + 6, 150,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = SFSUB_F_RI_LO
474
    { 332,  2,  0,  4,  1,  0,  1,  LanaiImpOpBase + 6, 150,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = SFSUB_F_RI_HI
475
    { 331,  4,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 162,  0|(1ULL<<MCID::Select)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = SELECT
476
    { 330,  2,  1,  4,  2,  1,  0,  LanaiImpOpBase + 6, 150,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = SCC
477
    { 329,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = SA_I
478
    { 328,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = SA_F_I
479
    { 327,  0,  0,  4,  0,  1,  0,  LanaiImpOpBase + 7, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = RET
480
    { 326,  2,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 140,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = POPC
481
    { 325,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = OR_R
482
    { 324,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = OR_I_LO
483
    { 323,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = OR_I_HI
484
    { 322,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = OR_F_R
485
    { 321,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = OR_F_I_LO
486
    { 320,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = OR_F_I_HI
487
    { 319,  0,  0,  4,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = NOP
488
    { 318,  2,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 150,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = MOVHI
489
    { 317,  0,  0,  4,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = LOG4
490
    { 316,  0,  0,  4,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = LOG3
491
    { 315,  0,  0,  4,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = LOG2
492
    { 314,  0,  0,  4,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = LOG1
493
    { 313,  0,  0,  4,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = LOG0
494
    { 312,  2,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 140,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = LEADZ
495
    { 311,  4,  1,  4,  5,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = LDWz_RR
496
    { 310,  4,  1,  4,  5,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = LDW_RR
497
    { 309,  4,  1,  4,  3,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = LDW_RI
498
    { 308,  4,  1,  4,  5,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = LDHz_RR
499
    { 307,  4,  1,  4,  4,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = LDHz_RI
500
    { 306,  4,  1,  4,  5,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = LDHs_RR
501
    { 305,  4,  1,  4,  4,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = LDHs_RI
502
    { 304,  4,  1,  4,  5,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = LDBz_RR
503
    { 303,  4,  1,  4,  4,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = LDBz_RI
504
    { 302,  4,  1,  4,  5,  0,  0,  LanaiImpOpBase + 0, 158,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = LDBs_RR
505
    { 301,  4,  1,  4,  4,  0,  0,  LanaiImpOpBase + 0, 154,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = LDBs_RI
506
    { 300,  2,  1,  4,  3,  0,  0,  LanaiImpOpBase + 0, 150,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = LDADDR
507
    { 299,  1,  0,  4,  1,  0,  0,  LanaiImpOpBase + 0, 142,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = JR
508
    { 298,  1,  0,  4,  2,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = BT
509
    { 297,  2,  0,  4,  0,  1,  0,  LanaiImpOpBase + 6, 152,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = BRR
510
    { 296,  3,  0,  4,  1,  1,  0,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = BRIND_CCA
511
    { 295,  2,  0,  4,  1,  1,  0,  LanaiImpOpBase + 6, 150,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = BRIND_CC
512
    { 294,  2,  0,  4,  2,  1,  0,  LanaiImpOpBase + 6, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = BRCC
513
    { 293,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = AND_R
514
    { 292,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = AND_I_LO
515
    { 291,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = AND_I_HI
516
    { 290,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = AND_F_R
517
    { 289,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = AND_F_I_LO
518
    { 288,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = AND_F_I_HI
519
    { 287,  4,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = ADD_R
520
    { 286,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = ADD_I_LO
521
    { 285,  3,  1,  4,  1,  0,  0,  LanaiImpOpBase + 0, 143,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = ADD_I_HI
522
    { 284,  4,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = ADD_F_R
523
    { 283,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = ADD_F_I_LO
524
    { 282,  3,  1,  4,  1,  0,  1,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = ADD_F_I_HI
525
    { 281,  4,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = ADDC_R
526
    { 280,  3,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = ADDC_I_LO
527
    { 279,  3,  1,  4,  1,  1,  0,  LanaiImpOpBase + 6, 143,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = ADDC_I_HI
528
    { 278,  4,  1,  4,  1,  1,  1,  LanaiImpOpBase + 4, 146,  0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = ADDC_F_R
529
    { 277,  3,  1,  4,  1,  1,  1,  LanaiImpOpBase + 4, 143,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = ADDC_F_I_LO
530
    { 276,  3,  1,  4,  1,  1,  1,  LanaiImpOpBase + 4, 143,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = ADDC_F_I_HI
531
    { 275,  1,  0,  4,  0,  1,  1,  LanaiImpOpBase + 2, 142,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = CALLR
532
    { 274,  1,  0,  4,  0,  1,  1,  LanaiImpOpBase + 2, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = CALL
533
    { 273,  2,  1,  4,  0,  1,  1,  LanaiImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = ADJDYNALLOC
534
    { 272,  2,  0,  4,  0,  1,  1,  LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = ADJCALLSTACKUP
535
    { 271,  2,  0,  4,  0,  1,  1,  LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = ADJCALLSTACKDOWN
536
    { 270,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_UBFX
537
    { 269,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_SBFX
538
    { 268,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
539
    { 267,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
540
    { 266,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
541
    { 265,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
542
    { 264,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
543
    { 263,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
544
    { 262,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
545
    { 261,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
546
    { 260,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
547
    { 259,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
548
    { 258,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
549
    { 257,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
550
    { 256,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
551
    { 255,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
552
    { 254,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
553
    { 253,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
554
    { 252,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
555
    { 251,  3,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_BZERO
556
    { 250,  4,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_MEMSET
557
    { 249,  4,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_MEMMOVE
558
    { 248,  3,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
559
    { 247,  4,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_MEMCPY
560
    { 246,  2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
561
    { 245,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
562
    { 244,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
563
    { 243,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
564
    { 242,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_STRICT_FMA
565
    { 241,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_STRICT_FREM
566
    { 240,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
567
    { 239,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
568
    { 238,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
569
    { 237,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_STRICT_FADD
570
    { 236,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_STACKRESTORE
571
    { 235,  1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_STACKSAVE
572
    { 234,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
573
    { 233,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
574
    { 232,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
575
    { 231,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
576
    { 230,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_FNEARBYINT
577
    { 229,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_FRINT
578
    { 228,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_FFLOOR
579
    { 227,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_FSQRT
580
    { 226,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_FSIN
581
    { 225,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_FCOS
582
    { 224,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_FCEIL
583
    { 223,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BITREVERSE
584
    { 222,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BSWAP
585
    { 221,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_CTPOP
586
    { 220,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
587
    { 219,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_CTLZ
588
    { 218,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
589
    { 217,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_CTTZ
590
    { 216,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
591
    { 215,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
592
    { 214,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
593
    { 213,  3,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_BRJT
594
    { 212,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_BR
595
    { 211,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_LLROUND
596
    { 210,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_LROUND
597
    { 209,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_ABS
598
    { 208,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_UMAX
599
    { 207,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_UMIN
600
    { 206,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_SMAX
601
    { 205,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_SMIN
602
    { 204,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_PTRMASK
603
    { 203,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_PTR_ADD
604
    { 202,  0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
605
    { 201,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_SET_FPMODE
606
    { 200,  1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_GET_FPMODE
607
    { 199,  0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_RESET_FPENV
608
    { 198,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SET_FPENV
609
    { 197,  1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_GET_FPENV
610
    { 196,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FMAXIMUM
611
    { 195,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FMINIMUM
612
    { 194,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
613
    { 193,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
614
    { 192,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FMAXNUM
615
    { 191,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FMINNUM
616
    { 190,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
617
    { 189,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
618
    { 188,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
619
    { 187,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FABS
620
    { 186,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_UITOFP
621
    { 185,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_SITOFP
622
    { 184,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPTOUI
623
    { 183,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPTOSI
624
    { 182,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FPTRUNC
625
    { 181,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPEXT
626
    { 180,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FNEG
627
    { 179,  3,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FFREXP
628
    { 178,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FLDEXP
629
    { 177,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FLOG10
630
    { 176,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FLOG2
631
    { 175,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FLOG
632
    { 174,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FEXP10
633
    { 173,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FEXP2
634
    { 172,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_FEXP
635
    { 171,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_FPOWI
636
    { 170,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_FPOW
637
    { 169,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_FREM
638
    { 168,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_FDIV
639
    { 167,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_FMAD
640
    { 166,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_FMA
641
    { 165,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_FMUL
642
    { 164,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_FSUB
643
    { 163,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_FADD
644
    { 162,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
645
    { 161,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
646
    { 160,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UDIVFIX
647
    { 159,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SDIVFIX
648
    { 158,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
649
    { 157,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
650
    { 156,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_UMULFIX
651
    { 155,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SMULFIX
652
    { 154,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSHLSAT
653
    { 153,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USHLSAT
654
    { 152,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SSUBSAT
655
    { 151,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_USUBSAT
656
    { 150,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_SADDSAT
657
    { 149,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_UADDSAT
658
    { 148,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_SMULH
659
    { 147,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UMULH
660
    { 146,  4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SMULO
661
    { 145,  4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UMULO
662
    { 144,  5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SSUBE
663
    { 143,  4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_SSUBO
664
    { 142,  5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_SADDE
665
    { 141,  4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_SADDO
666
    { 140,  5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_USUBE
667
    { 139,  4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_USUBO
668
    { 138,  5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_UADDE
669
    { 137,  4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_UADDO
670
    { 136,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SELECT
671
    { 135,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_FCMP
672
    { 134,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ICMP
673
    { 133,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_ROTL
674
    { 132,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_ROTR
675
    { 131,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_FSHR
676
    { 130,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_FSHL
677
    { 129,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ASHR
678
    { 128,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_LSHR
679
    { 127,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_SHL
680
    { 126,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ZEXT
681
    { 125,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_SEXT_INREG
682
    { 124,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_SEXT
683
    { 123,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_VAARG
684
    { 122,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_VASTART
685
    { 121,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_FCONSTANT
686
    { 120,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_CONSTANT
687
    { 119,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_TRUNC
688
    { 118,  2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ANYEXT
689
    { 117,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
690
    { 116,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
691
    { 115,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
692
    { 114,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_INTRINSIC
693
    { 113,  0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
694
    { 112,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_BRINDIRECT
695
    { 111,  2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_BRCOND
696
    { 110,  4,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_PREFETCH
697
    { 109,  2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_FENCE
698
    { 108,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
699
    { 107,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
700
    { 106,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
701
    { 105,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
702
    { 104,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
703
    { 103,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
704
    { 102,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
705
    { 101,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
706
    { 100,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
707
    { 99, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
708
    { 98, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
709
    { 97, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
710
    { 96, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
711
    { 95, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
712
    { 94, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
713
    { 93, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
714
    { 92, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
715
    { 91, 4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
716
    { 90, 5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
717
    { 89, 5,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
718
    { 88, 2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_STORE
719
    { 87, 5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
720
    { 86, 5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
721
    { 85, 5,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
722
    { 84, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
723
    { 83, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_SEXTLOAD
724
    { 82, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_LOAD
725
    { 81, 1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
726
    { 80, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
727
    { 79, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
728
    { 78, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
729
    { 77, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
730
    { 76, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
731
    { 75, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
732
    { 74, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_FREEZE
733
    { 73, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_BITCAST
734
    { 72, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INTTOPTR
735
    { 71, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_PTRTOINT
736
    { 70, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
737
    { 69, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
738
    { 68, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
739
    { 67, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
740
    { 66, 4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_INSERT
741
    { 65, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
742
    { 64, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_EXTRACT
743
    { 63, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
744
    { 62, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
745
    { 61, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
746
    { 60, 1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_PHI
747
    { 59, 1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
748
    { 58, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_XOR
749
    { 57, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_OR
750
    { 56, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_AND
751
    { 55, 4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_UDIVREM
752
    { 54, 4,  2,  0,  0,  0,  0,  LanaiImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SDIVREM
753
    { 53, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_UREM
754
    { 52, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_SREM
755
    { 51, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_UDIV
756
    { 50, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_SDIV
757
    { 49, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_MUL
758
    { 48, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #48 = G_SUB
759
    { 47, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #47 = G_ADD
760
    { 46, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
761
    { 45, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
762
    { 44, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
763
    { 43, 1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
764
    { 42, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = MEMBARRIER
765
    { 41, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
766
    { 40, 3,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
767
    { 39, 2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
768
    { 38, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
769
    { 37, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
770
    { 36, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
771
    { 35, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
772
    { 34, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
773
    { 33, 1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
774
    { 32, 2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
775
    { 31, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
776
    { 30, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
777
    { 29, 1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
778
    { 28, 1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
779
    { 27, 6,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
780
    { 26, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
781
    { 25, 2,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
782
    { 24, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
783
    { 23, 4,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
784
    { 22, 1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
785
    { 21, 1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
786
    { 20, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
787
    { 19, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
788
    { 18, 2,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
789
    { 17, 1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
790
    { 16, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
791
    { 15, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
792
    { 14, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
793
    { 13, 0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
794
    { 12, 3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
795
    { 11, 4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
796
    { 10, 1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
797
    { 9,  4,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 5,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
798
    { 8,  3,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
799
    { 7,  0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
800
    { 6,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
801
    { 5,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
802
    { 4,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
803
    { 3,  1,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
804
    { 2,  0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
805
    { 1,  0,  0,  0,  0,  0,  0,  LanaiImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
806
    { 0,  1,  1,  0,  0,  0,  0,  LanaiImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
807
  }, {
808
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
809
    /* 1 */
810
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
811
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
812
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
813
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
814
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
815
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
816
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
817
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
818
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
819
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
820
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
821
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
822
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
823
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
824
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
825
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
826
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
827
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
828
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
829
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
830
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
831
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
832
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
833
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
834
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
835
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
836
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
837
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
838
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
839
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
840
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
841
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
842
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
843
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
844
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
845
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
846
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
847
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
848
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
849
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
850
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
851
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
852
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
853
    /* 140 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
854
    /* 142 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
855
    /* 143 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
856
    /* 146 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI::Predicate), MCOI::OPERAND_UNKNOWN, 0 },
857
    /* 150 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
858
    /* 152 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
859
    /* 154 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
860
    /* 158 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
861
    /* 162 */ { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Lanai::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
862
  }, {
863
    /* 0 */
864
    /* 0 */ Lanai::SP, Lanai::SP,
865
    /* 2 */ Lanai::SP, Lanai::RCA,
866
    /* 4 */ Lanai::SR, Lanai::SR,
867
    /* 6 */ Lanai::SR,
868
    /* 7 */ Lanai::RCA,
869
  }
870
};
871
872
873
#ifdef __GNUC__
874
#pragma GCC diagnostic push
875
#pragma GCC diagnostic ignored "-Woverlength-strings"
876
#endif
877
extern const char LanaiInstrNameData[] = {
878
  /* 0 */ "G_FLOG10\0"
879
  /* 9 */ "G_FEXP10\0"
880
  /* 18 */ "LOG0\0"
881
  /* 23 */ "LOG1\0"
882
  /* 28 */ "G_FLOG2\0"
883
  /* 36 */ "G_FEXP2\0"
884
  /* 44 */ "LOG3\0"
885
  /* 49 */ "LOG4\0"
886
  /* 54 */ "BRIND_CCA\0"
887
  /* 64 */ "G_FMA\0"
888
  /* 70 */ "G_STRICT_FMA\0"
889
  /* 83 */ "G_FSUB\0"
890
  /* 90 */ "G_STRICT_FSUB\0"
891
  /* 104 */ "G_ATOMICRMW_FSUB\0"
892
  /* 121 */ "G_SUB\0"
893
  /* 127 */ "G_ATOMICRMW_SUB\0"
894
  /* 143 */ "BRCC\0"
895
  /* 148 */ "SCC\0"
896
  /* 152 */ "BRIND_CC\0"
897
  /* 161 */ "G_INTRINSIC\0"
898
  /* 173 */ "G_FPTRUNC\0"
899
  /* 183 */ "G_INTRINSIC_TRUNC\0"
900
  /* 201 */ "G_TRUNC\0"
901
  /* 209 */ "G_BUILD_VECTOR_TRUNC\0"
902
  /* 230 */ "G_DYN_STACKALLOC\0"
903
  /* 247 */ "ADJDYNALLOC\0"
904
  /* 259 */ "POPC\0"
905
  /* 264 */ "G_FMAD\0"
906
  /* 271 */ "G_INDEXED_SEXTLOAD\0"
907
  /* 290 */ "G_SEXTLOAD\0"
908
  /* 301 */ "G_INDEXED_ZEXTLOAD\0"
909
  /* 320 */ "G_ZEXTLOAD\0"
910
  /* 331 */ "G_INDEXED_LOAD\0"
911
  /* 346 */ "G_LOAD\0"
912
  /* 353 */ "G_VECREDUCE_FADD\0"
913
  /* 370 */ "G_FADD\0"
914
  /* 377 */ "G_VECREDUCE_SEQ_FADD\0"
915
  /* 398 */ "G_STRICT_FADD\0"
916
  /* 412 */ "G_ATOMICRMW_FADD\0"
917
  /* 429 */ "G_VECREDUCE_ADD\0"
918
  /* 445 */ "G_ADD\0"
919
  /* 451 */ "G_PTR_ADD\0"
920
  /* 461 */ "G_ATOMICRMW_ADD\0"
921
  /* 477 */ "G_ATOMICRMW_NAND\0"
922
  /* 494 */ "G_VECREDUCE_AND\0"
923
  /* 510 */ "G_AND\0"
924
  /* 516 */ "G_ATOMICRMW_AND\0"
925
  /* 532 */ "LIFETIME_END\0"
926
  /* 545 */ "G_BRCOND\0"
927
  /* 554 */ "G_LLROUND\0"
928
  /* 564 */ "G_LROUND\0"
929
  /* 573 */ "G_INTRINSIC_ROUND\0"
930
  /* 591 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
931
  /* 617 */ "LOAD_STACK_GUARD\0"
932
  /* 634 */ "PSEUDO_PROBE\0"
933
  /* 647 */ "G_SSUBE\0"
934
  /* 655 */ "G_USUBE\0"
935
  /* 663 */ "G_FENCE\0"
936
  /* 671 */ "ARITH_FENCE\0"
937
  /* 683 */ "REG_SEQUENCE\0"
938
  /* 696 */ "G_SADDE\0"
939
  /* 704 */ "G_UADDE\0"
940
  /* 712 */ "G_GET_FPMODE\0"
941
  /* 725 */ "G_RESET_FPMODE\0"
942
  /* 740 */ "G_SET_FPMODE\0"
943
  /* 753 */ "G_FMINNUM_IEEE\0"
944
  /* 768 */ "G_FMAXNUM_IEEE\0"
945
  /* 783 */ "G_JUMP_TABLE\0"
946
  /* 796 */ "BUNDLE\0"
947
  /* 803 */ "G_MEMCPY_INLINE\0"
948
  /* 819 */ "LOCAL_ESCAPE\0"
949
  /* 832 */ "G_STACKRESTORE\0"
950
  /* 847 */ "G_INDEXED_STORE\0"
951
  /* 863 */ "G_STORE\0"
952
  /* 871 */ "G_BITREVERSE\0"
953
  /* 884 */ "DBG_VALUE\0"
954
  /* 894 */ "G_GLOBAL_VALUE\0"
955
  /* 909 */ "G_STACKSAVE\0"
956
  /* 921 */ "G_MEMMOVE\0"
957
  /* 931 */ "G_FREEZE\0"
958
  /* 940 */ "G_FCANONICALIZE\0"
959
  /* 956 */ "G_CTLZ_ZERO_UNDEF\0"
960
  /* 974 */ "G_CTTZ_ZERO_UNDEF\0"
961
  /* 992 */ "G_IMPLICIT_DEF\0"
962
  /* 1007 */ "DBG_INSTR_REF\0"
963
  /* 1021 */ "G_FNEG\0"
964
  /* 1028 */ "EXTRACT_SUBREG\0"
965
  /* 1043 */ "INSERT_SUBREG\0"
966
  /* 1057 */ "G_SEXT_INREG\0"
967
  /* 1070 */ "SUBREG_TO_REG\0"
968
  /* 1084 */ "G_ATOMIC_CMPXCHG\0"
969
  /* 1101 */ "G_ATOMICRMW_XCHG\0"
970
  /* 1118 */ "G_FLOG\0"
971
  /* 1125 */ "G_VAARG\0"
972
  /* 1133 */ "PREALLOCATED_ARG\0"
973
  /* 1150 */ "G_PREFETCH\0"
974
  /* 1161 */ "G_SMULH\0"
975
  /* 1169 */ "G_UMULH\0"
976
  /* 1177 */ "DBG_PHI\0"
977
  /* 1185 */ "MOVHI\0"
978
  /* 1191 */ "SFSUB_F_RI_HI\0"
979
  /* 1205 */ "SUBB_I_HI\0"
980
  /* 1215 */ "SUB_I_HI\0"
981
  /* 1224 */ "ADDC_I_HI\0"
982
  /* 1234 */ "ADD_I_HI\0"
983
  /* 1243 */ "AND_I_HI\0"
984
  /* 1252 */ "SUBB_F_I_HI\0"
985
  /* 1264 */ "SUB_F_I_HI\0"
986
  /* 1275 */ "ADDC_F_I_HI\0"
987
  /* 1287 */ "ADD_F_I_HI\0"
988
  /* 1298 */ "AND_F_I_HI\0"
989
  /* 1309 */ "XOR_F_I_HI\0"
990
  /* 1320 */ "XOR_I_HI\0"
991
  /* 1329 */ "SLI\0"
992
  /* 1333 */ "STB_RI\0"
993
  /* 1340 */ "STH_RI\0"
994
  /* 1347 */ "LDW_RI\0"
995
  /* 1354 */ "SW_RI\0"
996
  /* 1360 */ "LDBs_RI\0"
997
  /* 1368 */ "LDHs_RI\0"
998
  /* 1376 */ "LDBz_RI\0"
999
  /* 1384 */ "LDHz_RI\0"
1000
  /* 1392 */ "G_FPTOSI\0"
1001
  /* 1401 */ "G_FPTOUI\0"
1002
  /* 1410 */ "G_FPOWI\0"
1003
  /* 1418 */ "SA_I\0"
1004
  /* 1423 */ "SA_F_I\0"
1005
  /* 1430 */ "SL_F_I\0"
1006
  /* 1437 */ "SL_I\0"
1007
  /* 1442 */ "G_PTRMASK\0"
1008
  /* 1452 */ "GC_LABEL\0"
1009
  /* 1461 */ "DBG_LABEL\0"
1010
  /* 1471 */ "EH_LABEL\0"
1011
  /* 1480 */ "ANNOTATION_LABEL\0"
1012
  /* 1497 */ "ICALL_BRANCH_FUNNEL\0"
1013
  /* 1517 */ "G_FSHL\0"
1014
  /* 1524 */ "G_SHL\0"
1015
  /* 1530 */ "G_FCEIL\0"
1016
  /* 1538 */ "PATCHABLE_TAIL_CALL\0"
1017
  /* 1558 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1018
  /* 1585 */ "PATCHABLE_EVENT_CALL\0"
1019
  /* 1606 */ "FENTRY_CALL\0"
1020
  /* 1618 */ "KILL\0"
1021
  /* 1623 */ "G_CONSTANT_POOL\0"
1022
  /* 1639 */ "G_ROTL\0"
1023
  /* 1646 */ "G_VECREDUCE_FMUL\0"
1024
  /* 1663 */ "G_FMUL\0"
1025
  /* 1670 */ "G_VECREDUCE_SEQ_FMUL\0"
1026
  /* 1691 */ "G_STRICT_FMUL\0"
1027
  /* 1705 */ "G_VECREDUCE_MUL\0"
1028
  /* 1721 */ "G_MUL\0"
1029
  /* 1727 */ "G_FREM\0"
1030
  /* 1734 */ "G_STRICT_FREM\0"
1031
  /* 1748 */ "G_SREM\0"
1032
  /* 1755 */ "G_UREM\0"
1033
  /* 1762 */ "G_SDIVREM\0"
1034
  /* 1772 */ "G_UDIVREM\0"
1035
  /* 1782 */ "INLINEASM\0"
1036
  /* 1792 */ "G_VECREDUCE_FMINIMUM\0"
1037
  /* 1813 */ "G_FMINIMUM\0"
1038
  /* 1824 */ "G_VECREDUCE_FMAXIMUM\0"
1039
  /* 1845 */ "G_FMAXIMUM\0"
1040
  /* 1856 */ "G_FMINNUM\0"
1041
  /* 1866 */ "G_FMAXNUM\0"
1042
  /* 1876 */ "G_INTRINSIC_ROUNDEVEN\0"
1043
  /* 1898 */ "G_ASSERT_ALIGN\0"
1044
  /* 1913 */ "G_FCOPYSIGN\0"
1045
  /* 1925 */ "G_VECREDUCE_FMIN\0"
1046
  /* 1942 */ "G_ATOMICRMW_FMIN\0"
1047
  /* 1959 */ "G_VECREDUCE_SMIN\0"
1048
  /* 1976 */ "G_SMIN\0"
1049
  /* 1983 */ "G_VECREDUCE_UMIN\0"
1050
  /* 2000 */ "G_UMIN\0"
1051
  /* 2007 */ "G_ATOMICRMW_UMIN\0"
1052
  /* 2024 */ "G_ATOMICRMW_MIN\0"
1053
  /* 2040 */ "G_FSIN\0"
1054
  /* 2047 */ "CFI_INSTRUCTION\0"
1055
  /* 2063 */ "ADJCALLSTACKDOWN\0"
1056
  /* 2080 */ "G_SSUBO\0"
1057
  /* 2088 */ "G_USUBO\0"
1058
  /* 2096 */ "G_SADDO\0"
1059
  /* 2104 */ "G_UADDO\0"
1060
  /* 2112 */ "JUMP_TABLE_DEBUG_INFO\0"
1061
  /* 2134 */ "G_SMULO\0"
1062
  /* 2142 */ "G_UMULO\0"
1063
  /* 2150 */ "SFSUB_F_RI_LO\0"
1064
  /* 2164 */ "SUBB_I_LO\0"
1065
  /* 2174 */ "SUB_I_LO\0"
1066
  /* 2183 */ "ADDC_I_LO\0"
1067
  /* 2193 */ "ADD_I_LO\0"
1068
  /* 2202 */ "AND_I_LO\0"
1069
  /* 2211 */ "SUBB_F_I_LO\0"
1070
  /* 2223 */ "SUB_F_I_LO\0"
1071
  /* 2234 */ "ADDC_F_I_LO\0"
1072
  /* 2246 */ "ADD_F_I_LO\0"
1073
  /* 2257 */ "AND_F_I_LO\0"
1074
  /* 2268 */ "XOR_F_I_LO\0"
1075
  /* 2279 */ "XOR_I_LO\0"
1076
  /* 2288 */ "G_BZERO\0"
1077
  /* 2296 */ "STACKMAP\0"
1078
  /* 2305 */ "G_ATOMICRMW_UDEC_WRAP\0"
1079
  /* 2327 */ "G_ATOMICRMW_UINC_WRAP\0"
1080
  /* 2349 */ "G_BSWAP\0"
1081
  /* 2357 */ "G_SITOFP\0"
1082
  /* 2366 */ "G_UITOFP\0"
1083
  /* 2375 */ "G_FCMP\0"
1084
  /* 2382 */ "G_ICMP\0"
1085
  /* 2389 */ "NOP\0"
1086
  /* 2393 */ "G_CTPOP\0"
1087
  /* 2401 */ "PATCHABLE_OP\0"
1088
  /* 2414 */ "FAULTING_OP\0"
1089
  /* 2426 */ "ADJCALLSTACKUP\0"
1090
  /* 2441 */ "PREALLOCATED_SETUP\0"
1091
  /* 2460 */ "G_FLDEXP\0"
1092
  /* 2469 */ "G_STRICT_FLDEXP\0"
1093
  /* 2485 */ "G_FEXP\0"
1094
  /* 2492 */ "G_FFREXP\0"
1095
  /* 2501 */ "G_BR\0"
1096
  /* 2506 */ "INLINEASM_BR\0"
1097
  /* 2519 */ "LDADDR\0"
1098
  /* 2526 */ "STADDR\0"
1099
  /* 2533 */ "G_BLOCK_ADDR\0"
1100
  /* 2546 */ "MEMBARRIER\0"
1101
  /* 2557 */ "G_CONSTANT_FOLD_BARRIER\0"
1102
  /* 2581 */ "PATCHABLE_FUNCTION_ENTER\0"
1103
  /* 2606 */ "G_READCYCLECOUNTER\0"
1104
  /* 2625 */ "G_READ_REGISTER\0"
1105
  /* 2641 */ "G_WRITE_REGISTER\0"
1106
  /* 2658 */ "G_ASHR\0"
1107
  /* 2665 */ "G_FSHR\0"
1108
  /* 2672 */ "G_LSHR\0"
1109
  /* 2679 */ "JR\0"
1110
  /* 2682 */ "CALLR\0"
1111
  /* 2688 */ "G_FFLOOR\0"
1112
  /* 2697 */ "G_BUILD_VECTOR\0"
1113
  /* 2712 */ "G_SHUFFLE_VECTOR\0"
1114
  /* 2729 */ "G_VECREDUCE_XOR\0"
1115
  /* 2745 */ "G_XOR\0"
1116
  /* 2751 */ "G_ATOMICRMW_XOR\0"
1117
  /* 2767 */ "G_VECREDUCE_OR\0"
1118
  /* 2782 */ "G_OR\0"
1119
  /* 2787 */ "G_ATOMICRMW_OR\0"
1120
  /* 2802 */ "BRR\0"
1121
  /* 2806 */ "STB_RR\0"
1122
  /* 2813 */ "SFSUB_F_RR\0"
1123
  /* 2824 */ "STH_RR\0"
1124
  /* 2831 */ "LDW_RR\0"
1125
  /* 2838 */ "SW_RR\0"
1126
  /* 2844 */ "LDBs_RR\0"
1127
  /* 2852 */ "LDHs_RR\0"
1128
  /* 2860 */ "LDBz_RR\0"
1129
  /* 2868 */ "LDHz_RR\0"
1130
  /* 2876 */ "LDWz_RR\0"
1131
  /* 2884 */ "G_ROTR\0"
1132
  /* 2891 */ "G_INTTOPTR\0"
1133
  /* 2902 */ "SRA_R\0"
1134
  /* 2908 */ "SUBB_R\0"
1135
  /* 2915 */ "SUB_R\0"
1136
  /* 2921 */ "ADDC_R\0"
1137
  /* 2928 */ "ADD_R\0"
1138
  /* 2934 */ "AND_R\0"
1139
  /* 2940 */ "SRA_F_R\0"
1140
  /* 2948 */ "SUBB_F_R\0"
1141
  /* 2957 */ "SUB_F_R\0"
1142
  /* 2965 */ "ADDC_F_R\0"
1143
  /* 2974 */ "ADD_F_R\0"
1144
  /* 2982 */ "AND_F_R\0"
1145
  /* 2990 */ "SHL_F_R\0"
1146
  /* 2998 */ "SRL_F_R\0"
1147
  /* 3006 */ "XOR_F_R\0"
1148
  /* 3014 */ "SHL_R\0"
1149
  /* 3020 */ "SRL_R\0"
1150
  /* 3026 */ "XOR_R\0"
1151
  /* 3032 */ "G_FABS\0"
1152
  /* 3039 */ "G_ABS\0"
1153
  /* 3045 */ "G_UNMERGE_VALUES\0"
1154
  /* 3062 */ "G_MERGE_VALUES\0"
1155
  /* 3077 */ "G_FCOS\0"
1156
  /* 3084 */ "G_CONCAT_VECTORS\0"
1157
  /* 3101 */ "COPY_TO_REGCLASS\0"
1158
  /* 3118 */ "G_IS_FPCLASS\0"
1159
  /* 3131 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1160
  /* 3161 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1161
  /* 3188 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1162
  /* 3226 */ "G_SSUBSAT\0"
1163
  /* 3236 */ "G_USUBSAT\0"
1164
  /* 3246 */ "G_SADDSAT\0"
1165
  /* 3256 */ "G_UADDSAT\0"
1166
  /* 3266 */ "G_SSHLSAT\0"
1167
  /* 3276 */ "G_USHLSAT\0"
1168
  /* 3286 */ "G_SMULFIXSAT\0"
1169
  /* 3299 */ "G_UMULFIXSAT\0"
1170
  /* 3312 */ "G_SDIVFIXSAT\0"
1171
  /* 3325 */ "G_UDIVFIXSAT\0"
1172
  /* 3338 */ "BT\0"
1173
  /* 3341 */ "G_EXTRACT\0"
1174
  /* 3351 */ "G_SELECT\0"
1175
  /* 3360 */ "G_BRINDIRECT\0"
1176
  /* 3373 */ "PATCHABLE_RET\0"
1177
  /* 3387 */ "G_MEMSET\0"
1178
  /* 3396 */ "PATCHABLE_FUNCTION_EXIT\0"
1179
  /* 3420 */ "G_BRJT\0"
1180
  /* 3427 */ "G_EXTRACT_VECTOR_ELT\0"
1181
  /* 3448 */ "G_INSERT_VECTOR_ELT\0"
1182
  /* 3468 */ "G_FCONSTANT\0"
1183
  /* 3480 */ "G_CONSTANT\0"
1184
  /* 3491 */ "G_INTRINSIC_CONVERGENT\0"
1185
  /* 3514 */ "STATEPOINT\0"
1186
  /* 3525 */ "PATCHPOINT\0"
1187
  /* 3536 */ "G_PTRTOINT\0"
1188
  /* 3547 */ "G_FRINT\0"
1189
  /* 3555 */ "G_INTRINSIC_LRINT\0"
1190
  /* 3573 */ "G_FNEARBYINT\0"
1191
  /* 3586 */ "G_VASTART\0"
1192
  /* 3596 */ "LIFETIME_START\0"
1193
  /* 3611 */ "G_INVOKE_REGION_START\0"
1194
  /* 3633 */ "G_INSERT\0"
1195
  /* 3642 */ "G_FSQRT\0"
1196
  /* 3650 */ "G_STRICT_FSQRT\0"
1197
  /* 3665 */ "G_BITCAST\0"
1198
  /* 3675 */ "G_ADDRSPACE_CAST\0"
1199
  /* 3692 */ "DBG_VALUE_LIST\0"
1200
  /* 3707 */ "G_FPEXT\0"
1201
  /* 3715 */ "G_SEXT\0"
1202
  /* 3722 */ "G_ASSERT_SEXT\0"
1203
  /* 3736 */ "G_ANYEXT\0"
1204
  /* 3745 */ "G_ZEXT\0"
1205
  /* 3752 */ "G_ASSERT_ZEXT\0"
1206
  /* 3766 */ "G_FDIV\0"
1207
  /* 3773 */ "G_STRICT_FDIV\0"
1208
  /* 3787 */ "G_SDIV\0"
1209
  /* 3794 */ "G_UDIV\0"
1210
  /* 3801 */ "G_GET_FPENV\0"
1211
  /* 3813 */ "G_RESET_FPENV\0"
1212
  /* 3827 */ "G_SET_FPENV\0"
1213
  /* 3839 */ "G_FPOW\0"
1214
  /* 3846 */ "G_VECREDUCE_FMAX\0"
1215
  /* 3863 */ "G_ATOMICRMW_FMAX\0"
1216
  /* 3880 */ "G_VECREDUCE_SMAX\0"
1217
  /* 3897 */ "G_SMAX\0"
1218
  /* 3904 */ "G_VECREDUCE_UMAX\0"
1219
  /* 3921 */ "G_UMAX\0"
1220
  /* 3928 */ "G_ATOMICRMW_UMAX\0"
1221
  /* 3945 */ "G_ATOMICRMW_MAX\0"
1222
  /* 3961 */ "G_FRAME_INDEX\0"
1223
  /* 3975 */ "G_SBFX\0"
1224
  /* 3982 */ "G_UBFX\0"
1225
  /* 3989 */ "G_SMULFIX\0"
1226
  /* 3999 */ "G_UMULFIX\0"
1227
  /* 4009 */ "G_SDIVFIX\0"
1228
  /* 4019 */ "G_UDIVFIX\0"
1229
  /* 4029 */ "G_MEMCPY\0"
1230
  /* 4038 */ "COPY\0"
1231
  /* 4043 */ "LEADZ\0"
1232
  /* 4049 */ "TRAILZ\0"
1233
  /* 4056 */ "G_CTLZ\0"
1234
  /* 4063 */ "G_CTTZ\0"
1235
};
1236
#ifdef __GNUC__
1237
#pragma GCC diagnostic pop
1238
#endif
1239
1240
extern const unsigned LanaiInstrNameIndices[] = {
1241
    1181U, 1782U, 2506U, 2047U, 1471U, 1452U, 1480U, 1618U, 
1242
    1028U, 1043U, 994U, 1070U, 3101U, 884U, 3692U, 1007U, 
1243
    1177U, 1461U, 683U, 4038U, 796U, 3596U, 532U, 634U, 
1244
    671U, 2296U, 1606U, 3525U, 617U, 2441U, 1133U, 3514U, 
1245
    819U, 2414U, 2401U, 2581U, 3373U, 3396U, 1538U, 1585U, 
1246
    1558U, 1497U, 2546U, 2112U, 3722U, 3752U, 1898U, 445U, 
1247
    121U, 1721U, 3787U, 3794U, 1748U, 1755U, 1762U, 1772U, 
1248
    510U, 2782U, 2745U, 992U, 1179U, 3961U, 894U, 1623U, 
1249
    3341U, 3045U, 3633U, 3062U, 2697U, 209U, 3084U, 3536U, 
1250
    2891U, 3665U, 931U, 2557U, 591U, 183U, 573U, 3555U, 
1251
    1876U, 2606U, 346U, 290U, 320U, 331U, 271U, 301U, 
1252
    863U, 847U, 3131U, 1084U, 1101U, 461U, 127U, 516U, 
1253
    477U, 2787U, 2751U, 3945U, 2024U, 3928U, 2007U, 412U, 
1254
    104U, 3863U, 1942U, 2327U, 2305U, 663U, 1150U, 545U, 
1255
    3360U, 3611U, 161U, 3161U, 3491U, 3188U, 3736U, 201U, 
1256
    3480U, 3468U, 3586U, 1125U, 3715U, 1057U, 3745U, 1524U, 
1257
    2672U, 2658U, 1517U, 2665U, 2884U, 1639U, 2382U, 2375U, 
1258
    3351U, 2104U, 704U, 2088U, 655U, 2096U, 696U, 2080U, 
1259
    647U, 2142U, 2134U, 1169U, 1161U, 3256U, 3246U, 3236U, 
1260
    3226U, 3276U, 3266U, 3989U, 3999U, 3286U, 3299U, 4009U, 
1261
    4019U, 3312U, 3325U, 370U, 83U, 1663U, 64U, 264U, 
1262
    3766U, 1727U, 3839U, 1410U, 2485U, 36U, 9U, 1118U, 
1263
    28U, 0U, 2460U, 2492U, 1021U, 3707U, 173U, 1392U, 
1264
    1401U, 2357U, 2366U, 3032U, 1913U, 3118U, 940U, 1856U, 
1265
    1866U, 753U, 768U, 1813U, 1845U, 3801U, 3827U, 3813U, 
1266
    712U, 740U, 725U, 451U, 1442U, 1976U, 3897U, 2000U, 
1267
    3921U, 3039U, 564U, 554U, 2501U, 3420U, 3448U, 3427U, 
1268
    2712U, 4063U, 974U, 4056U, 956U, 2393U, 2349U, 871U, 
1269
    1530U, 3077U, 2040U, 3642U, 2688U, 3547U, 3573U, 3675U, 
1270
    2533U, 783U, 230U, 909U, 832U, 398U, 90U, 1691U, 
1271
    3773U, 1734U, 70U, 3650U, 2469U, 2625U, 2641U, 4029U, 
1272
    803U, 921U, 3387U, 2288U, 377U, 1670U, 353U, 1646U, 
1273
    3846U, 1925U, 1824U, 1792U, 429U, 1705U, 494U, 2767U, 
1274
    2729U, 3880U, 1959U, 3904U, 1983U, 3975U, 3982U, 2063U, 
1275
    2426U, 247U, 1553U, 2682U, 1275U, 2234U, 2965U, 1224U, 
1276
    2183U, 2921U, 1287U, 2246U, 2974U, 1234U, 2193U, 2928U, 
1277
    1298U, 2257U, 2982U, 1243U, 2202U, 2934U, 143U, 152U, 
1278
    54U, 2802U, 3338U, 2679U, 2519U, 1360U, 2844U, 1376U, 
1279
    2860U, 1368U, 2852U, 1384U, 2868U, 1347U, 2831U, 2876U, 
1280
    4043U, 18U, 23U, 31U, 44U, 49U, 1185U, 2389U, 
1281
    1310U, 2269U, 3007U, 1321U, 2280U, 3027U, 259U, 3383U, 
1282
    1423U, 1418U, 148U, 3353U, 1191U, 2150U, 2813U, 2990U, 
1283
    3014U, 1329U, 1430U, 1437U, 2940U, 2902U, 2998U, 3020U, 
1284
    2526U, 1333U, 2806U, 1340U, 2824U, 1252U, 2211U, 2948U, 
1285
    1205U, 2164U, 2908U, 1264U, 2223U, 2957U, 1215U, 2174U, 
1286
    2915U, 1354U, 2838U, 4049U, 1309U, 2268U, 3006U, 1320U, 
1287
    2279U, 3026U, 
1288
};
1289
1290
0
static inline void InitLanaiMCInstrInfo(MCInstrInfo *II) {
1291
0
  II->InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 370);
1292
0
}
1293
1294
} // end namespace llvm
1295
#endif // GET_INSTRINFO_MC_DESC
1296
1297
#ifdef GET_INSTRINFO_HEADER
1298
#undef GET_INSTRINFO_HEADER
1299
namespace llvm {
1300
struct LanaiGenInstrInfo : public TargetInstrInfo {
1301
  explicit LanaiGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
1302
  ~LanaiGenInstrInfo() override = default;
1303
1304
};
1305
} // end namespace llvm
1306
#endif // GET_INSTRINFO_HEADER
1307
1308
#ifdef GET_INSTRINFO_HELPER_DECLS
1309
#undef GET_INSTRINFO_HELPER_DECLS
1310
1311
1312
#endif // GET_INSTRINFO_HELPER_DECLS
1313
1314
#ifdef GET_INSTRINFO_HELPERS
1315
#undef GET_INSTRINFO_HELPERS
1316
1317
#endif // GET_INSTRINFO_HELPERS
1318
1319
#ifdef GET_INSTRINFO_CTOR_DTOR
1320
#undef GET_INSTRINFO_CTOR_DTOR
1321
namespace llvm {
1322
extern const LanaiInstrTable LanaiDescs;
1323
extern const unsigned LanaiInstrNameIndices[];
1324
extern const char LanaiInstrNameData[];
1325
LanaiGenInstrInfo::LanaiGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
1326
0
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
1327
0
  InitMCInstrInfo(LanaiDescs.Insts, LanaiInstrNameIndices, LanaiInstrNameData, nullptr, nullptr, 370);
1328
0
}
1329
} // end namespace llvm
1330
#endif // GET_INSTRINFO_CTOR_DTOR
1331
1332
#ifdef GET_INSTRINFO_OPERAND_ENUM
1333
#undef GET_INSTRINFO_OPERAND_ENUM
1334
namespace llvm {
1335
namespace Lanai {
1336
namespace OpName {
1337
enum {
1338
  OPERAND_LAST
1339
};
1340
} // end namespace OpName
1341
} // end namespace Lanai
1342
} // end namespace llvm
1343
#endif //GET_INSTRINFO_OPERAND_ENUM
1344
1345
#ifdef GET_INSTRINFO_NAMED_OPS
1346
#undef GET_INSTRINFO_NAMED_OPS
1347
namespace llvm {
1348
namespace Lanai {
1349
LLVM_READONLY
1350
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1351
  return -1;
1352
}
1353
} // end namespace Lanai
1354
} // end namespace llvm
1355
#endif //GET_INSTRINFO_NAMED_OPS
1356
1357
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1358
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1359
namespace llvm {
1360
namespace Lanai {
1361
namespace OpTypes {
1362
enum OperandType {
1363
  AluOp = 0,
1364
  BrTarget = 1,
1365
  CCOp = 2,
1366
  CallTarget = 3,
1367
  MEMi = 4,
1368
  MEMri = 5,
1369
  MEMrr = 6,
1370
  MEMspls = 7,
1371
  f32imm = 8,
1372
  f64imm = 9,
1373
  i1imm = 10,
1374
  i8imm = 11,
1375
  i16imm = 12,
1376
  i32hi16 = 13,
1377
  i32hi16and = 14,
1378
  i32imm = 15,
1379
  i32lo16and = 16,
1380
  i32lo16s = 17,
1381
  i32lo16z = 18,
1382
  i32lo21 = 19,
1383
  i32neg16 = 20,
1384
  i64imm = 21,
1385
  imm10 = 22,
1386
  immShift = 23,
1387
  pred = 24,
1388
  ptype0 = 25,
1389
  ptype1 = 26,
1390
  ptype2 = 27,
1391
  ptype3 = 28,
1392
  ptype4 = 29,
1393
  ptype5 = 30,
1394
  type0 = 31,
1395
  type1 = 32,
1396
  type2 = 33,
1397
  type3 = 34,
1398
  type4 = 35,
1399
  type5 = 36,
1400
  untyped_imm_0 = 37,
1401
  CCR = 38,
1402
  GPR = 39,
1403
  OPERAND_TYPE_LIST_END
1404
};
1405
} // end namespace OpTypes
1406
} // end namespace Lanai
1407
} // end namespace llvm
1408
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
1409
1410
#ifdef GET_INSTRINFO_OPERAND_TYPE
1411
#undef GET_INSTRINFO_OPERAND_TYPE
1412
namespace llvm {
1413
namespace Lanai {
1414
LLVM_READONLY
1415
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
1416
  static const uint16_t Offsets[] = {
1417
    /* PHI */
1418
    0,
1419
    /* INLINEASM */
1420
    1,
1421
    /* INLINEASM_BR */
1422
    1,
1423
    /* CFI_INSTRUCTION */
1424
    1,
1425
    /* EH_LABEL */
1426
    2,
1427
    /* GC_LABEL */
1428
    3,
1429
    /* ANNOTATION_LABEL */
1430
    4,
1431
    /* KILL */
1432
    5,
1433
    /* EXTRACT_SUBREG */
1434
    5,
1435
    /* INSERT_SUBREG */
1436
    8,
1437
    /* IMPLICIT_DEF */
1438
    12,
1439
    /* SUBREG_TO_REG */
1440
    13,
1441
    /* COPY_TO_REGCLASS */
1442
    17,
1443
    /* DBG_VALUE */
1444
    20,
1445
    /* DBG_VALUE_LIST */
1446
    20,
1447
    /* DBG_INSTR_REF */
1448
    20,
1449
    /* DBG_PHI */
1450
    20,
1451
    /* DBG_LABEL */
1452
    20,
1453
    /* REG_SEQUENCE */
1454
    21,
1455
    /* COPY */
1456
    23,
1457
    /* BUNDLE */
1458
    25,
1459
    /* LIFETIME_START */
1460
    25,
1461
    /* LIFETIME_END */
1462
    26,
1463
    /* PSEUDO_PROBE */
1464
    27,
1465
    /* ARITH_FENCE */
1466
    31,
1467
    /* STACKMAP */
1468
    33,
1469
    /* FENTRY_CALL */
1470
    35,
1471
    /* PATCHPOINT */
1472
    35,
1473
    /* LOAD_STACK_GUARD */
1474
    41,
1475
    /* PREALLOCATED_SETUP */
1476
    42,
1477
    /* PREALLOCATED_ARG */
1478
    43,
1479
    /* STATEPOINT */
1480
    46,
1481
    /* LOCAL_ESCAPE */
1482
    46,
1483
    /* FAULTING_OP */
1484
    48,
1485
    /* PATCHABLE_OP */
1486
    49,
1487
    /* PATCHABLE_FUNCTION_ENTER */
1488
    49,
1489
    /* PATCHABLE_RET */
1490
    49,
1491
    /* PATCHABLE_FUNCTION_EXIT */
1492
    49,
1493
    /* PATCHABLE_TAIL_CALL */
1494
    49,
1495
    /* PATCHABLE_EVENT_CALL */
1496
    49,
1497
    /* PATCHABLE_TYPED_EVENT_CALL */
1498
    51,
1499
    /* ICALL_BRANCH_FUNNEL */
1500
    54,
1501
    /* MEMBARRIER */
1502
    54,
1503
    /* JUMP_TABLE_DEBUG_INFO */
1504
    54,
1505
    /* G_ASSERT_SEXT */
1506
    55,
1507
    /* G_ASSERT_ZEXT */
1508
    58,
1509
    /* G_ASSERT_ALIGN */
1510
    61,
1511
    /* G_ADD */
1512
    64,
1513
    /* G_SUB */
1514
    67,
1515
    /* G_MUL */
1516
    70,
1517
    /* G_SDIV */
1518
    73,
1519
    /* G_UDIV */
1520
    76,
1521
    /* G_SREM */
1522
    79,
1523
    /* G_UREM */
1524
    82,
1525
    /* G_SDIVREM */
1526
    85,
1527
    /* G_UDIVREM */
1528
    89,
1529
    /* G_AND */
1530
    93,
1531
    /* G_OR */
1532
    96,
1533
    /* G_XOR */
1534
    99,
1535
    /* G_IMPLICIT_DEF */
1536
    102,
1537
    /* G_PHI */
1538
    103,
1539
    /* G_FRAME_INDEX */
1540
    104,
1541
    /* G_GLOBAL_VALUE */
1542
    106,
1543
    /* G_CONSTANT_POOL */
1544
    108,
1545
    /* G_EXTRACT */
1546
    110,
1547
    /* G_UNMERGE_VALUES */
1548
    113,
1549
    /* G_INSERT */
1550
    115,
1551
    /* G_MERGE_VALUES */
1552
    119,
1553
    /* G_BUILD_VECTOR */
1554
    121,
1555
    /* G_BUILD_VECTOR_TRUNC */
1556
    123,
1557
    /* G_CONCAT_VECTORS */
1558
    125,
1559
    /* G_PTRTOINT */
1560
    127,
1561
    /* G_INTTOPTR */
1562
    129,
1563
    /* G_BITCAST */
1564
    131,
1565
    /* G_FREEZE */
1566
    133,
1567
    /* G_CONSTANT_FOLD_BARRIER */
1568
    135,
1569
    /* G_INTRINSIC_FPTRUNC_ROUND */
1570
    137,
1571
    /* G_INTRINSIC_TRUNC */
1572
    140,
1573
    /* G_INTRINSIC_ROUND */
1574
    142,
1575
    /* G_INTRINSIC_LRINT */
1576
    144,
1577
    /* G_INTRINSIC_ROUNDEVEN */
1578
    146,
1579
    /* G_READCYCLECOUNTER */
1580
    148,
1581
    /* G_LOAD */
1582
    149,
1583
    /* G_SEXTLOAD */
1584
    151,
1585
    /* G_ZEXTLOAD */
1586
    153,
1587
    /* G_INDEXED_LOAD */
1588
    155,
1589
    /* G_INDEXED_SEXTLOAD */
1590
    160,
1591
    /* G_INDEXED_ZEXTLOAD */
1592
    165,
1593
    /* G_STORE */
1594
    170,
1595
    /* G_INDEXED_STORE */
1596
    172,
1597
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
1598
    177,
1599
    /* G_ATOMIC_CMPXCHG */
1600
    182,
1601
    /* G_ATOMICRMW_XCHG */
1602
    186,
1603
    /* G_ATOMICRMW_ADD */
1604
    189,
1605
    /* G_ATOMICRMW_SUB */
1606
    192,
1607
    /* G_ATOMICRMW_AND */
1608
    195,
1609
    /* G_ATOMICRMW_NAND */
1610
    198,
1611
    /* G_ATOMICRMW_OR */
1612
    201,
1613
    /* G_ATOMICRMW_XOR */
1614
    204,
1615
    /* G_ATOMICRMW_MAX */
1616
    207,
1617
    /* G_ATOMICRMW_MIN */
1618
    210,
1619
    /* G_ATOMICRMW_UMAX */
1620
    213,
1621
    /* G_ATOMICRMW_UMIN */
1622
    216,
1623
    /* G_ATOMICRMW_FADD */
1624
    219,
1625
    /* G_ATOMICRMW_FSUB */
1626
    222,
1627
    /* G_ATOMICRMW_FMAX */
1628
    225,
1629
    /* G_ATOMICRMW_FMIN */
1630
    228,
1631
    /* G_ATOMICRMW_UINC_WRAP */
1632
    231,
1633
    /* G_ATOMICRMW_UDEC_WRAP */
1634
    234,
1635
    /* G_FENCE */
1636
    237,
1637
    /* G_PREFETCH */
1638
    239,
1639
    /* G_BRCOND */
1640
    243,
1641
    /* G_BRINDIRECT */
1642
    245,
1643
    /* G_INVOKE_REGION_START */
1644
    246,
1645
    /* G_INTRINSIC */
1646
    246,
1647
    /* G_INTRINSIC_W_SIDE_EFFECTS */
1648
    247,
1649
    /* G_INTRINSIC_CONVERGENT */
1650
    248,
1651
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
1652
    249,
1653
    /* G_ANYEXT */
1654
    250,
1655
    /* G_TRUNC */
1656
    252,
1657
    /* G_CONSTANT */
1658
    254,
1659
    /* G_FCONSTANT */
1660
    256,
1661
    /* G_VASTART */
1662
    258,
1663
    /* G_VAARG */
1664
    259,
1665
    /* G_SEXT */
1666
    262,
1667
    /* G_SEXT_INREG */
1668
    264,
1669
    /* G_ZEXT */
1670
    267,
1671
    /* G_SHL */
1672
    269,
1673
    /* G_LSHR */
1674
    272,
1675
    /* G_ASHR */
1676
    275,
1677
    /* G_FSHL */
1678
    278,
1679
    /* G_FSHR */
1680
    282,
1681
    /* G_ROTR */
1682
    286,
1683
    /* G_ROTL */
1684
    289,
1685
    /* G_ICMP */
1686
    292,
1687
    /* G_FCMP */
1688
    296,
1689
    /* G_SELECT */
1690
    300,
1691
    /* G_UADDO */
1692
    304,
1693
    /* G_UADDE */
1694
    308,
1695
    /* G_USUBO */
1696
    313,
1697
    /* G_USUBE */
1698
    317,
1699
    /* G_SADDO */
1700
    322,
1701
    /* G_SADDE */
1702
    326,
1703
    /* G_SSUBO */
1704
    331,
1705
    /* G_SSUBE */
1706
    335,
1707
    /* G_UMULO */
1708
    340,
1709
    /* G_SMULO */
1710
    344,
1711
    /* G_UMULH */
1712
    348,
1713
    /* G_SMULH */
1714
    351,
1715
    /* G_UADDSAT */
1716
    354,
1717
    /* G_SADDSAT */
1718
    357,
1719
    /* G_USUBSAT */
1720
    360,
1721
    /* G_SSUBSAT */
1722
    363,
1723
    /* G_USHLSAT */
1724
    366,
1725
    /* G_SSHLSAT */
1726
    369,
1727
    /* G_SMULFIX */
1728
    372,
1729
    /* G_UMULFIX */
1730
    376,
1731
    /* G_SMULFIXSAT */
1732
    380,
1733
    /* G_UMULFIXSAT */
1734
    384,
1735
    /* G_SDIVFIX */
1736
    388,
1737
    /* G_UDIVFIX */
1738
    392,
1739
    /* G_SDIVFIXSAT */
1740
    396,
1741
    /* G_UDIVFIXSAT */
1742
    400,
1743
    /* G_FADD */
1744
    404,
1745
    /* G_FSUB */
1746
    407,
1747
    /* G_FMUL */
1748
    410,
1749
    /* G_FMA */
1750
    413,
1751
    /* G_FMAD */
1752
    417,
1753
    /* G_FDIV */
1754
    421,
1755
    /* G_FREM */
1756
    424,
1757
    /* G_FPOW */
1758
    427,
1759
    /* G_FPOWI */
1760
    430,
1761
    /* G_FEXP */
1762
    433,
1763
    /* G_FEXP2 */
1764
    435,
1765
    /* G_FEXP10 */
1766
    437,
1767
    /* G_FLOG */
1768
    439,
1769
    /* G_FLOG2 */
1770
    441,
1771
    /* G_FLOG10 */
1772
    443,
1773
    /* G_FLDEXP */
1774
    445,
1775
    /* G_FFREXP */
1776
    448,
1777
    /* G_FNEG */
1778
    451,
1779
    /* G_FPEXT */
1780
    453,
1781
    /* G_FPTRUNC */
1782
    455,
1783
    /* G_FPTOSI */
1784
    457,
1785
    /* G_FPTOUI */
1786
    459,
1787
    /* G_SITOFP */
1788
    461,
1789
    /* G_UITOFP */
1790
    463,
1791
    /* G_FABS */
1792
    465,
1793
    /* G_FCOPYSIGN */
1794
    467,
1795
    /* G_IS_FPCLASS */
1796
    470,
1797
    /* G_FCANONICALIZE */
1798
    473,
1799
    /* G_FMINNUM */
1800
    475,
1801
    /* G_FMAXNUM */
1802
    478,
1803
    /* G_FMINNUM_IEEE */
1804
    481,
1805
    /* G_FMAXNUM_IEEE */
1806
    484,
1807
    /* G_FMINIMUM */
1808
    487,
1809
    /* G_FMAXIMUM */
1810
    490,
1811
    /* G_GET_FPENV */
1812
    493,
1813
    /* G_SET_FPENV */
1814
    494,
1815
    /* G_RESET_FPENV */
1816
    495,
1817
    /* G_GET_FPMODE */
1818
    495,
1819
    /* G_SET_FPMODE */
1820
    496,
1821
    /* G_RESET_FPMODE */
1822
    497,
1823
    /* G_PTR_ADD */
1824
    497,
1825
    /* G_PTRMASK */
1826
    500,
1827
    /* G_SMIN */
1828
    503,
1829
    /* G_SMAX */
1830
    506,
1831
    /* G_UMIN */
1832
    509,
1833
    /* G_UMAX */
1834
    512,
1835
    /* G_ABS */
1836
    515,
1837
    /* G_LROUND */
1838
    517,
1839
    /* G_LLROUND */
1840
    519,
1841
    /* G_BR */
1842
    521,
1843
    /* G_BRJT */
1844
    522,
1845
    /* G_INSERT_VECTOR_ELT */
1846
    525,
1847
    /* G_EXTRACT_VECTOR_ELT */
1848
    529,
1849
    /* G_SHUFFLE_VECTOR */
1850
    532,
1851
    /* G_CTTZ */
1852
    536,
1853
    /* G_CTTZ_ZERO_UNDEF */
1854
    538,
1855
    /* G_CTLZ */
1856
    540,
1857
    /* G_CTLZ_ZERO_UNDEF */
1858
    542,
1859
    /* G_CTPOP */
1860
    544,
1861
    /* G_BSWAP */
1862
    546,
1863
    /* G_BITREVERSE */
1864
    548,
1865
    /* G_FCEIL */
1866
    550,
1867
    /* G_FCOS */
1868
    552,
1869
    /* G_FSIN */
1870
    554,
1871
    /* G_FSQRT */
1872
    556,
1873
    /* G_FFLOOR */
1874
    558,
1875
    /* G_FRINT */
1876
    560,
1877
    /* G_FNEARBYINT */
1878
    562,
1879
    /* G_ADDRSPACE_CAST */
1880
    564,
1881
    /* G_BLOCK_ADDR */
1882
    566,
1883
    /* G_JUMP_TABLE */
1884
    568,
1885
    /* G_DYN_STACKALLOC */
1886
    570,
1887
    /* G_STACKSAVE */
1888
    573,
1889
    /* G_STACKRESTORE */
1890
    574,
1891
    /* G_STRICT_FADD */
1892
    575,
1893
    /* G_STRICT_FSUB */
1894
    578,
1895
    /* G_STRICT_FMUL */
1896
    581,
1897
    /* G_STRICT_FDIV */
1898
    584,
1899
    /* G_STRICT_FREM */
1900
    587,
1901
    /* G_STRICT_FMA */
1902
    590,
1903
    /* G_STRICT_FSQRT */
1904
    594,
1905
    /* G_STRICT_FLDEXP */
1906
    596,
1907
    /* G_READ_REGISTER */
1908
    599,
1909
    /* G_WRITE_REGISTER */
1910
    601,
1911
    /* G_MEMCPY */
1912
    603,
1913
    /* G_MEMCPY_INLINE */
1914
    607,
1915
    /* G_MEMMOVE */
1916
    610,
1917
    /* G_MEMSET */
1918
    614,
1919
    /* G_BZERO */
1920
    618,
1921
    /* G_VECREDUCE_SEQ_FADD */
1922
    621,
1923
    /* G_VECREDUCE_SEQ_FMUL */
1924
    624,
1925
    /* G_VECREDUCE_FADD */
1926
    627,
1927
    /* G_VECREDUCE_FMUL */
1928
    629,
1929
    /* G_VECREDUCE_FMAX */
1930
    631,
1931
    /* G_VECREDUCE_FMIN */
1932
    633,
1933
    /* G_VECREDUCE_FMAXIMUM */
1934
    635,
1935
    /* G_VECREDUCE_FMINIMUM */
1936
    637,
1937
    /* G_VECREDUCE_ADD */
1938
    639,
1939
    /* G_VECREDUCE_MUL */
1940
    641,
1941
    /* G_VECREDUCE_AND */
1942
    643,
1943
    /* G_VECREDUCE_OR */
1944
    645,
1945
    /* G_VECREDUCE_XOR */
1946
    647,
1947
    /* G_VECREDUCE_SMAX */
1948
    649,
1949
    /* G_VECREDUCE_SMIN */
1950
    651,
1951
    /* G_VECREDUCE_UMAX */
1952
    653,
1953
    /* G_VECREDUCE_UMIN */
1954
    655,
1955
    /* G_SBFX */
1956
    657,
1957
    /* G_UBFX */
1958
    661,
1959
    /* ADJCALLSTACKDOWN */
1960
    665,
1961
    /* ADJCALLSTACKUP */
1962
    667,
1963
    /* ADJDYNALLOC */
1964
    669,
1965
    /* CALL */
1966
    671,
1967
    /* CALLR */
1968
    672,
1969
    /* ADDC_F_I_HI */
1970
    673,
1971
    /* ADDC_F_I_LO */
1972
    676,
1973
    /* ADDC_F_R */
1974
    679,
1975
    /* ADDC_I_HI */
1976
    683,
1977
    /* ADDC_I_LO */
1978
    686,
1979
    /* ADDC_R */
1980
    689,
1981
    /* ADD_F_I_HI */
1982
    693,
1983
    /* ADD_F_I_LO */
1984
    696,
1985
    /* ADD_F_R */
1986
    699,
1987
    /* ADD_I_HI */
1988
    703,
1989
    /* ADD_I_LO */
1990
    706,
1991
    /* ADD_R */
1992
    709,
1993
    /* AND_F_I_HI */
1994
    713,
1995
    /* AND_F_I_LO */
1996
    716,
1997
    /* AND_F_R */
1998
    719,
1999
    /* AND_I_HI */
2000
    723,
2001
    /* AND_I_LO */
2002
    726,
2003
    /* AND_R */
2004
    729,
2005
    /* BRCC */
2006
    733,
2007
    /* BRIND_CC */
2008
    735,
2009
    /* BRIND_CCA */
2010
    737,
2011
    /* BRR */
2012
    740,
2013
    /* BT */
2014
    742,
2015
    /* JR */
2016
    743,
2017
    /* LDADDR */
2018
    744,
2019
    /* LDBs_RI */
2020
    746,
2021
    /* LDBs_RR */
2022
    750,
2023
    /* LDBz_RI */
2024
    754,
2025
    /* LDBz_RR */
2026
    758,
2027
    /* LDHs_RI */
2028
    762,
2029
    /* LDHs_RR */
2030
    766,
2031
    /* LDHz_RI */
2032
    770,
2033
    /* LDHz_RR */
2034
    774,
2035
    /* LDW_RI */
2036
    778,
2037
    /* LDW_RR */
2038
    782,
2039
    /* LDWz_RR */
2040
    786,
2041
    /* LEADZ */
2042
    790,
2043
    /* LOG0 */
2044
    792,
2045
    /* LOG1 */
2046
    792,
2047
    /* LOG2 */
2048
    792,
2049
    /* LOG3 */
2050
    792,
2051
    /* LOG4 */
2052
    792,
2053
    /* MOVHI */
2054
    792,
2055
    /* NOP */
2056
    794,
2057
    /* OR_F_I_HI */
2058
    794,
2059
    /* OR_F_I_LO */
2060
    797,
2061
    /* OR_F_R */
2062
    800,
2063
    /* OR_I_HI */
2064
    804,
2065
    /* OR_I_LO */
2066
    807,
2067
    /* OR_R */
2068
    810,
2069
    /* POPC */
2070
    814,
2071
    /* RET */
2072
    816,
2073
    /* SA_F_I */
2074
    816,
2075
    /* SA_I */
2076
    819,
2077
    /* SCC */
2078
    822,
2079
    /* SELECT */
2080
    824,
2081
    /* SFSUB_F_RI_HI */
2082
    828,
2083
    /* SFSUB_F_RI_LO */
2084
    830,
2085
    /* SFSUB_F_RR */
2086
    832,
2087
    /* SHL_F_R */
2088
    834,
2089
    /* SHL_R */
2090
    838,
2091
    /* SLI */
2092
    842,
2093
    /* SL_F_I */
2094
    844,
2095
    /* SL_I */
2096
    847,
2097
    /* SRA_F_R */
2098
    850,
2099
    /* SRA_R */
2100
    854,
2101
    /* SRL_F_R */
2102
    858,
2103
    /* SRL_R */
2104
    862,
2105
    /* STADDR */
2106
    866,
2107
    /* STB_RI */
2108
    868,
2109
    /* STB_RR */
2110
    872,
2111
    /* STH_RI */
2112
    876,
2113
    /* STH_RR */
2114
    880,
2115
    /* SUBB_F_I_HI */
2116
    884,
2117
    /* SUBB_F_I_LO */
2118
    887,
2119
    /* SUBB_F_R */
2120
    890,
2121
    /* SUBB_I_HI */
2122
    894,
2123
    /* SUBB_I_LO */
2124
    897,
2125
    /* SUBB_R */
2126
    900,
2127
    /* SUB_F_I_HI */
2128
    904,
2129
    /* SUB_F_I_LO */
2130
    907,
2131
    /* SUB_F_R */
2132
    910,
2133
    /* SUB_I_HI */
2134
    914,
2135
    /* SUB_I_LO */
2136
    917,
2137
    /* SUB_R */
2138
    920,
2139
    /* SW_RI */
2140
    924,
2141
    /* SW_RR */
2142
    928,
2143
    /* TRAILZ */
2144
    932,
2145
    /* XOR_F_I_HI */
2146
    934,
2147
    /* XOR_F_I_LO */
2148
    937,
2149
    /* XOR_F_R */
2150
    940,
2151
    /* XOR_I_HI */
2152
    944,
2153
    /* XOR_I_LO */
2154
    947,
2155
    /* XOR_R */
2156
    950,
2157
  };
2158
2159
  using namespace OpTypes;
2160
  static const int8_t OpcodeOperandTypes[] = {
2161
    
2162
    /* PHI */
2163
    -1, 
2164
    /* INLINEASM */
2165
    /* INLINEASM_BR */
2166
    /* CFI_INSTRUCTION */
2167
    i32imm, 
2168
    /* EH_LABEL */
2169
    i32imm, 
2170
    /* GC_LABEL */
2171
    i32imm, 
2172
    /* ANNOTATION_LABEL */
2173
    i32imm, 
2174
    /* KILL */
2175
    /* EXTRACT_SUBREG */
2176
    -1, -1, i32imm, 
2177
    /* INSERT_SUBREG */
2178
    -1, -1, -1, i32imm, 
2179
    /* IMPLICIT_DEF */
2180
    -1, 
2181
    /* SUBREG_TO_REG */
2182
    -1, -1, -1, i32imm, 
2183
    /* COPY_TO_REGCLASS */
2184
    -1, -1, i32imm, 
2185
    /* DBG_VALUE */
2186
    /* DBG_VALUE_LIST */
2187
    /* DBG_INSTR_REF */
2188
    /* DBG_PHI */
2189
    /* DBG_LABEL */
2190
    -1, 
2191
    /* REG_SEQUENCE */
2192
    -1, -1, 
2193
    /* COPY */
2194
    -1, -1, 
2195
    /* BUNDLE */
2196
    /* LIFETIME_START */
2197
    i32imm, 
2198
    /* LIFETIME_END */
2199
    i32imm, 
2200
    /* PSEUDO_PROBE */
2201
    i64imm, i64imm, i8imm, i32imm, 
2202
    /* ARITH_FENCE */
2203
    -1, -1, 
2204
    /* STACKMAP */
2205
    i64imm, i32imm, 
2206
    /* FENTRY_CALL */
2207
    /* PATCHPOINT */
2208
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
2209
    /* LOAD_STACK_GUARD */
2210
    -1, 
2211
    /* PREALLOCATED_SETUP */
2212
    i32imm, 
2213
    /* PREALLOCATED_ARG */
2214
    -1, i32imm, i32imm, 
2215
    /* STATEPOINT */
2216
    /* LOCAL_ESCAPE */
2217
    -1, i32imm, 
2218
    /* FAULTING_OP */
2219
    -1, 
2220
    /* PATCHABLE_OP */
2221
    /* PATCHABLE_FUNCTION_ENTER */
2222
    /* PATCHABLE_RET */
2223
    /* PATCHABLE_FUNCTION_EXIT */
2224
    /* PATCHABLE_TAIL_CALL */
2225
    /* PATCHABLE_EVENT_CALL */
2226
    -1, -1, 
2227
    /* PATCHABLE_TYPED_EVENT_CALL */
2228
    -1, -1, -1, 
2229
    /* ICALL_BRANCH_FUNNEL */
2230
    /* MEMBARRIER */
2231
    /* JUMP_TABLE_DEBUG_INFO */
2232
    i64imm, 
2233
    /* G_ASSERT_SEXT */
2234
    type0, type0, untyped_imm_0, 
2235
    /* G_ASSERT_ZEXT */
2236
    type0, type0, untyped_imm_0, 
2237
    /* G_ASSERT_ALIGN */
2238
    type0, type0, untyped_imm_0, 
2239
    /* G_ADD */
2240
    type0, type0, type0, 
2241
    /* G_SUB */
2242
    type0, type0, type0, 
2243
    /* G_MUL */
2244
    type0, type0, type0, 
2245
    /* G_SDIV */
2246
    type0, type0, type0, 
2247
    /* G_UDIV */
2248
    type0, type0, type0, 
2249
    /* G_SREM */
2250
    type0, type0, type0, 
2251
    /* G_UREM */
2252
    type0, type0, type0, 
2253
    /* G_SDIVREM */
2254
    type0, type0, type0, type0, 
2255
    /* G_UDIVREM */
2256
    type0, type0, type0, type0, 
2257
    /* G_AND */
2258
    type0, type0, type0, 
2259
    /* G_OR */
2260
    type0, type0, type0, 
2261
    /* G_XOR */
2262
    type0, type0, type0, 
2263
    /* G_IMPLICIT_DEF */
2264
    type0, 
2265
    /* G_PHI */
2266
    type0, 
2267
    /* G_FRAME_INDEX */
2268
    type0, -1, 
2269
    /* G_GLOBAL_VALUE */
2270
    type0, -1, 
2271
    /* G_CONSTANT_POOL */
2272
    type0, -1, 
2273
    /* G_EXTRACT */
2274
    type0, type1, untyped_imm_0, 
2275
    /* G_UNMERGE_VALUES */
2276
    type0, type1, 
2277
    /* G_INSERT */
2278
    type0, type0, type1, untyped_imm_0, 
2279
    /* G_MERGE_VALUES */
2280
    type0, type1, 
2281
    /* G_BUILD_VECTOR */
2282
    type0, type1, 
2283
    /* G_BUILD_VECTOR_TRUNC */
2284
    type0, type1, 
2285
    /* G_CONCAT_VECTORS */
2286
    type0, type1, 
2287
    /* G_PTRTOINT */
2288
    type0, type1, 
2289
    /* G_INTTOPTR */
2290
    type0, type1, 
2291
    /* G_BITCAST */
2292
    type0, type1, 
2293
    /* G_FREEZE */
2294
    type0, type0, 
2295
    /* G_CONSTANT_FOLD_BARRIER */
2296
    type0, type0, 
2297
    /* G_INTRINSIC_FPTRUNC_ROUND */
2298
    type0, type1, i32imm, 
2299
    /* G_INTRINSIC_TRUNC */
2300
    type0, type0, 
2301
    /* G_INTRINSIC_ROUND */
2302
    type0, type0, 
2303
    /* G_INTRINSIC_LRINT */
2304
    type0, type1, 
2305
    /* G_INTRINSIC_ROUNDEVEN */
2306
    type0, type0, 
2307
    /* G_READCYCLECOUNTER */
2308
    type0, 
2309
    /* G_LOAD */
2310
    type0, ptype1, 
2311
    /* G_SEXTLOAD */
2312
    type0, ptype1, 
2313
    /* G_ZEXTLOAD */
2314
    type0, ptype1, 
2315
    /* G_INDEXED_LOAD */
2316
    type0, ptype1, ptype1, type2, -1, 
2317
    /* G_INDEXED_SEXTLOAD */
2318
    type0, ptype1, ptype1, type2, -1, 
2319
    /* G_INDEXED_ZEXTLOAD */
2320
    type0, ptype1, ptype1, type2, -1, 
2321
    /* G_STORE */
2322
    type0, ptype1, 
2323
    /* G_INDEXED_STORE */
2324
    ptype0, type1, ptype0, ptype2, -1, 
2325
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2326
    type0, type1, type2, type0, type0, 
2327
    /* G_ATOMIC_CMPXCHG */
2328
    type0, ptype1, type0, type0, 
2329
    /* G_ATOMICRMW_XCHG */
2330
    type0, ptype1, type0, 
2331
    /* G_ATOMICRMW_ADD */
2332
    type0, ptype1, type0, 
2333
    /* G_ATOMICRMW_SUB */
2334
    type0, ptype1, type0, 
2335
    /* G_ATOMICRMW_AND */
2336
    type0, ptype1, type0, 
2337
    /* G_ATOMICRMW_NAND */
2338
    type0, ptype1, type0, 
2339
    /* G_ATOMICRMW_OR */
2340
    type0, ptype1, type0, 
2341
    /* G_ATOMICRMW_XOR */
2342
    type0, ptype1, type0, 
2343
    /* G_ATOMICRMW_MAX */
2344
    type0, ptype1, type0, 
2345
    /* G_ATOMICRMW_MIN */
2346
    type0, ptype1, type0, 
2347
    /* G_ATOMICRMW_UMAX */
2348
    type0, ptype1, type0, 
2349
    /* G_ATOMICRMW_UMIN */
2350
    type0, ptype1, type0, 
2351
    /* G_ATOMICRMW_FADD */
2352
    type0, ptype1, type0, 
2353
    /* G_ATOMICRMW_FSUB */
2354
    type0, ptype1, type0, 
2355
    /* G_ATOMICRMW_FMAX */
2356
    type0, ptype1, type0, 
2357
    /* G_ATOMICRMW_FMIN */
2358
    type0, ptype1, type0, 
2359
    /* G_ATOMICRMW_UINC_WRAP */
2360
    type0, ptype1, type0, 
2361
    /* G_ATOMICRMW_UDEC_WRAP */
2362
    type0, ptype1, type0, 
2363
    /* G_FENCE */
2364
    i32imm, i32imm, 
2365
    /* G_PREFETCH */
2366
    ptype0, i32imm, i32imm, i32imm, 
2367
    /* G_BRCOND */
2368
    type0, -1, 
2369
    /* G_BRINDIRECT */
2370
    type0, 
2371
    /* G_INVOKE_REGION_START */
2372
    /* G_INTRINSIC */
2373
    -1, 
2374
    /* G_INTRINSIC_W_SIDE_EFFECTS */
2375
    -1, 
2376
    /* G_INTRINSIC_CONVERGENT */
2377
    -1, 
2378
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2379
    -1, 
2380
    /* G_ANYEXT */
2381
    type0, type1, 
2382
    /* G_TRUNC */
2383
    type0, type1, 
2384
    /* G_CONSTANT */
2385
    type0, -1, 
2386
    /* G_FCONSTANT */
2387
    type0, -1, 
2388
    /* G_VASTART */
2389
    type0, 
2390
    /* G_VAARG */
2391
    type0, type1, -1, 
2392
    /* G_SEXT */
2393
    type0, type1, 
2394
    /* G_SEXT_INREG */
2395
    type0, type0, untyped_imm_0, 
2396
    /* G_ZEXT */
2397
    type0, type1, 
2398
    /* G_SHL */
2399
    type0, type0, type1, 
2400
    /* G_LSHR */
2401
    type0, type0, type1, 
2402
    /* G_ASHR */
2403
    type0, type0, type1, 
2404
    /* G_FSHL */
2405
    type0, type0, type0, type1, 
2406
    /* G_FSHR */
2407
    type0, type0, type0, type1, 
2408
    /* G_ROTR */
2409
    type0, type0, type1, 
2410
    /* G_ROTL */
2411
    type0, type0, type1, 
2412
    /* G_ICMP */
2413
    type0, -1, type1, type1, 
2414
    /* G_FCMP */
2415
    type0, -1, type1, type1, 
2416
    /* G_SELECT */
2417
    type0, type1, type0, type0, 
2418
    /* G_UADDO */
2419
    type0, type1, type0, type0, 
2420
    /* G_UADDE */
2421
    type0, type1, type0, type0, type1, 
2422
    /* G_USUBO */
2423
    type0, type1, type0, type0, 
2424
    /* G_USUBE */
2425
    type0, type1, type0, type0, type1, 
2426
    /* G_SADDO */
2427
    type0, type1, type0, type0, 
2428
    /* G_SADDE */
2429
    type0, type1, type0, type0, type1, 
2430
    /* G_SSUBO */
2431
    type0, type1, type0, type0, 
2432
    /* G_SSUBE */
2433
    type0, type1, type0, type0, type1, 
2434
    /* G_UMULO */
2435
    type0, type1, type0, type0, 
2436
    /* G_SMULO */
2437
    type0, type1, type0, type0, 
2438
    /* G_UMULH */
2439
    type0, type0, type0, 
2440
    /* G_SMULH */
2441
    type0, type0, type0, 
2442
    /* G_UADDSAT */
2443
    type0, type0, type0, 
2444
    /* G_SADDSAT */
2445
    type0, type0, type0, 
2446
    /* G_USUBSAT */
2447
    type0, type0, type0, 
2448
    /* G_SSUBSAT */
2449
    type0, type0, type0, 
2450
    /* G_USHLSAT */
2451
    type0, type0, type1, 
2452
    /* G_SSHLSAT */
2453
    type0, type0, type1, 
2454
    /* G_SMULFIX */
2455
    type0, type0, type0, untyped_imm_0, 
2456
    /* G_UMULFIX */
2457
    type0, type0, type0, untyped_imm_0, 
2458
    /* G_SMULFIXSAT */
2459
    type0, type0, type0, untyped_imm_0, 
2460
    /* G_UMULFIXSAT */
2461
    type0, type0, type0, untyped_imm_0, 
2462
    /* G_SDIVFIX */
2463
    type0, type0, type0, untyped_imm_0, 
2464
    /* G_UDIVFIX */
2465
    type0, type0, type0, untyped_imm_0, 
2466
    /* G_SDIVFIXSAT */
2467
    type0, type0, type0, untyped_imm_0, 
2468
    /* G_UDIVFIXSAT */
2469
    type0, type0, type0, untyped_imm_0, 
2470
    /* G_FADD */
2471
    type0, type0, type0, 
2472
    /* G_FSUB */
2473
    type0, type0, type0, 
2474
    /* G_FMUL */
2475
    type0, type0, type0, 
2476
    /* G_FMA */
2477
    type0, type0, type0, type0, 
2478
    /* G_FMAD */
2479
    type0, type0, type0, type0, 
2480
    /* G_FDIV */
2481
    type0, type0, type0, 
2482
    /* G_FREM */
2483
    type0, type0, type0, 
2484
    /* G_FPOW */
2485
    type0, type0, type0, 
2486
    /* G_FPOWI */
2487
    type0, type0, type1, 
2488
    /* G_FEXP */
2489
    type0, type0, 
2490
    /* G_FEXP2 */
2491
    type0, type0, 
2492
    /* G_FEXP10 */
2493
    type0, type0, 
2494
    /* G_FLOG */
2495
    type0, type0, 
2496
    /* G_FLOG2 */
2497
    type0, type0, 
2498
    /* G_FLOG10 */
2499
    type0, type0, 
2500
    /* G_FLDEXP */
2501
    type0, type0, type1, 
2502
    /* G_FFREXP */
2503
    type0, type1, type0, 
2504
    /* G_FNEG */
2505
    type0, type0, 
2506
    /* G_FPEXT */
2507
    type0, type1, 
2508
    /* G_FPTRUNC */
2509
    type0, type1, 
2510
    /* G_FPTOSI */
2511
    type0, type1, 
2512
    /* G_FPTOUI */
2513
    type0, type1, 
2514
    /* G_SITOFP */
2515
    type0, type1, 
2516
    /* G_UITOFP */
2517
    type0, type1, 
2518
    /* G_FABS */
2519
    type0, type0, 
2520
    /* G_FCOPYSIGN */
2521
    type0, type0, type1, 
2522
    /* G_IS_FPCLASS */
2523
    type0, type1, -1, 
2524
    /* G_FCANONICALIZE */
2525
    type0, type0, 
2526
    /* G_FMINNUM */
2527
    type0, type0, type0, 
2528
    /* G_FMAXNUM */
2529
    type0, type0, type0, 
2530
    /* G_FMINNUM_IEEE */
2531
    type0, type0, type0, 
2532
    /* G_FMAXNUM_IEEE */
2533
    type0, type0, type0, 
2534
    /* G_FMINIMUM */
2535
    type0, type0, type0, 
2536
    /* G_FMAXIMUM */
2537
    type0, type0, type0, 
2538
    /* G_GET_FPENV */
2539
    type0, 
2540
    /* G_SET_FPENV */
2541
    type0, 
2542
    /* G_RESET_FPENV */
2543
    /* G_GET_FPMODE */
2544
    type0, 
2545
    /* G_SET_FPMODE */
2546
    type0, 
2547
    /* G_RESET_FPMODE */
2548
    /* G_PTR_ADD */
2549
    ptype0, ptype0, type1, 
2550
    /* G_PTRMASK */
2551
    ptype0, ptype0, type1, 
2552
    /* G_SMIN */
2553
    type0, type0, type0, 
2554
    /* G_SMAX */
2555
    type0, type0, type0, 
2556
    /* G_UMIN */
2557
    type0, type0, type0, 
2558
    /* G_UMAX */
2559
    type0, type0, type0, 
2560
    /* G_ABS */
2561
    type0, type0, 
2562
    /* G_LROUND */
2563
    type0, type1, 
2564
    /* G_LLROUND */
2565
    type0, type1, 
2566
    /* G_BR */
2567
    -1, 
2568
    /* G_BRJT */
2569
    ptype0, -1, type1, 
2570
    /* G_INSERT_VECTOR_ELT */
2571
    type0, type0, type1, type2, 
2572
    /* G_EXTRACT_VECTOR_ELT */
2573
    type0, type1, type2, 
2574
    /* G_SHUFFLE_VECTOR */
2575
    type0, type1, type1, -1, 
2576
    /* G_CTTZ */
2577
    type0, type1, 
2578
    /* G_CTTZ_ZERO_UNDEF */
2579
    type0, type1, 
2580
    /* G_CTLZ */
2581
    type0, type1, 
2582
    /* G_CTLZ_ZERO_UNDEF */
2583
    type0, type1, 
2584
    /* G_CTPOP */
2585
    type0, type1, 
2586
    /* G_BSWAP */
2587
    type0, type0, 
2588
    /* G_BITREVERSE */
2589
    type0, type0, 
2590
    /* G_FCEIL */
2591
    type0, type0, 
2592
    /* G_FCOS */
2593
    type0, type0, 
2594
    /* G_FSIN */
2595
    type0, type0, 
2596
    /* G_FSQRT */
2597
    type0, type0, 
2598
    /* G_FFLOOR */
2599
    type0, type0, 
2600
    /* G_FRINT */
2601
    type0, type0, 
2602
    /* G_FNEARBYINT */
2603
    type0, type0, 
2604
    /* G_ADDRSPACE_CAST */
2605
    type0, type1, 
2606
    /* G_BLOCK_ADDR */
2607
    type0, -1, 
2608
    /* G_JUMP_TABLE */
2609
    type0, -1, 
2610
    /* G_DYN_STACKALLOC */
2611
    ptype0, type1, i32imm, 
2612
    /* G_STACKSAVE */
2613
    ptype0, 
2614
    /* G_STACKRESTORE */
2615
    ptype0, 
2616
    /* G_STRICT_FADD */
2617
    type0, type0, type0, 
2618
    /* G_STRICT_FSUB */
2619
    type0, type0, type0, 
2620
    /* G_STRICT_FMUL */
2621
    type0, type0, type0, 
2622
    /* G_STRICT_FDIV */
2623
    type0, type0, type0, 
2624
    /* G_STRICT_FREM */
2625
    type0, type0, type0, 
2626
    /* G_STRICT_FMA */
2627
    type0, type0, type0, type0, 
2628
    /* G_STRICT_FSQRT */
2629
    type0, type0, 
2630
    /* G_STRICT_FLDEXP */
2631
    type0, type0, type1, 
2632
    /* G_READ_REGISTER */
2633
    type0, -1, 
2634
    /* G_WRITE_REGISTER */
2635
    -1, type0, 
2636
    /* G_MEMCPY */
2637
    ptype0, ptype1, type2, untyped_imm_0, 
2638
    /* G_MEMCPY_INLINE */
2639
    ptype0, ptype1, type2, 
2640
    /* G_MEMMOVE */
2641
    ptype0, ptype1, type2, untyped_imm_0, 
2642
    /* G_MEMSET */
2643
    ptype0, type1, type2, untyped_imm_0, 
2644
    /* G_BZERO */
2645
    ptype0, type1, untyped_imm_0, 
2646
    /* G_VECREDUCE_SEQ_FADD */
2647
    type0, type1, type2, 
2648
    /* G_VECREDUCE_SEQ_FMUL */
2649
    type0, type1, type2, 
2650
    /* G_VECREDUCE_FADD */
2651
    type0, type1, 
2652
    /* G_VECREDUCE_FMUL */
2653
    type0, type1, 
2654
    /* G_VECREDUCE_FMAX */
2655
    type0, type1, 
2656
    /* G_VECREDUCE_FMIN */
2657
    type0, type1, 
2658
    /* G_VECREDUCE_FMAXIMUM */
2659
    type0, type1, 
2660
    /* G_VECREDUCE_FMINIMUM */
2661
    type0, type1, 
2662
    /* G_VECREDUCE_ADD */
2663
    type0, type1, 
2664
    /* G_VECREDUCE_MUL */
2665
    type0, type1, 
2666
    /* G_VECREDUCE_AND */
2667
    type0, type1, 
2668
    /* G_VECREDUCE_OR */
2669
    type0, type1, 
2670
    /* G_VECREDUCE_XOR */
2671
    type0, type1, 
2672
    /* G_VECREDUCE_SMAX */
2673
    type0, type1, 
2674
    /* G_VECREDUCE_SMIN */
2675
    type0, type1, 
2676
    /* G_VECREDUCE_UMAX */
2677
    type0, type1, 
2678
    /* G_VECREDUCE_UMIN */
2679
    type0, type1, 
2680
    /* G_SBFX */
2681
    type0, type0, type1, type1, 
2682
    /* G_UBFX */
2683
    type0, type0, type1, type1, 
2684
    /* ADJCALLSTACKDOWN */
2685
    i32imm, i32imm, 
2686
    /* ADJCALLSTACKUP */
2687
    i32imm, i32imm, 
2688
    /* ADJDYNALLOC */
2689
    GPR, GPR, 
2690
    /* CALL */
2691
    CallTarget, 
2692
    /* CALLR */
2693
    GPR, 
2694
    /* ADDC_F_I_HI */
2695
    GPR, GPR, i32hi16, 
2696
    /* ADDC_F_I_LO */
2697
    GPR, GPR, i32lo16z, 
2698
    /* ADDC_F_R */
2699
    GPR, GPR, GPR, i32imm, 
2700
    /* ADDC_I_HI */
2701
    GPR, GPR, i32hi16, 
2702
    /* ADDC_I_LO */
2703
    GPR, GPR, i32lo16z, 
2704
    /* ADDC_R */
2705
    GPR, GPR, GPR, i32imm, 
2706
    /* ADD_F_I_HI */
2707
    GPR, GPR, i32hi16, 
2708
    /* ADD_F_I_LO */
2709
    GPR, GPR, i32lo16z, 
2710
    /* ADD_F_R */
2711
    GPR, GPR, GPR, i32imm, 
2712
    /* ADD_I_HI */
2713
    GPR, GPR, i32hi16, 
2714
    /* ADD_I_LO */
2715
    GPR, GPR, i32lo16z, 
2716
    /* ADD_R */
2717
    GPR, GPR, GPR, i32imm, 
2718
    /* AND_F_I_HI */
2719
    GPR, GPR, i32hi16and, 
2720
    /* AND_F_I_LO */
2721
    GPR, GPR, i32lo16and, 
2722
    /* AND_F_R */
2723
    GPR, GPR, GPR, i32imm, 
2724
    /* AND_I_HI */
2725
    GPR, GPR, i32hi16and, 
2726
    /* AND_I_LO */
2727
    GPR, GPR, i32lo16and, 
2728
    /* AND_R */
2729
    GPR, GPR, GPR, i32imm, 
2730
    /* BRCC */
2731
    BrTarget, CCOp, 
2732
    /* BRIND_CC */
2733
    GPR, CCOp, 
2734
    /* BRIND_CCA */
2735
    GPR, GPR, CCOp, 
2736
    /* BRR */
2737
    i16imm, CCOp, 
2738
    /* BT */
2739
    BrTarget, 
2740
    /* JR */
2741
    GPR, 
2742
    /* LDADDR */
2743
    GPR, i32lo21, 
2744
    /* LDBs_RI */
2745
    GPR, GPR, imm10, AluOp, 
2746
    /* LDBs_RR */
2747
    GPR, GPR, GPR, AluOp, 
2748
    /* LDBz_RI */
2749
    GPR, GPR, imm10, AluOp, 
2750
    /* LDBz_RR */
2751
    GPR, GPR, GPR, AluOp, 
2752
    /* LDHs_RI */
2753
    GPR, GPR, imm10, AluOp, 
2754
    /* LDHs_RR */
2755
    GPR, GPR, GPR, AluOp, 
2756
    /* LDHz_RI */
2757
    GPR, GPR, imm10, AluOp, 
2758
    /* LDHz_RR */
2759
    GPR, GPR, GPR, AluOp, 
2760
    /* LDW_RI */
2761
    GPR, GPR, i32lo16s, AluOp, 
2762
    /* LDW_RR */
2763
    GPR, GPR, GPR, AluOp, 
2764
    /* LDWz_RR */
2765
    GPR, GPR, GPR, AluOp, 
2766
    /* LEADZ */
2767
    GPR, GPR, 
2768
    /* LOG0 */
2769
    /* LOG1 */
2770
    /* LOG2 */
2771
    /* LOG3 */
2772
    /* LOG4 */
2773
    /* MOVHI */
2774
    GPR, i32hi16, 
2775
    /* NOP */
2776
    /* OR_F_I_HI */
2777
    GPR, GPR, i32hi16, 
2778
    /* OR_F_I_LO */
2779
    GPR, GPR, i32lo16z, 
2780
    /* OR_F_R */
2781
    GPR, GPR, GPR, i32imm, 
2782
    /* OR_I_HI */
2783
    GPR, GPR, i32hi16, 
2784
    /* OR_I_LO */
2785
    GPR, GPR, i32lo16z, 
2786
    /* OR_R */
2787
    GPR, GPR, GPR, i32imm, 
2788
    /* POPC */
2789
    GPR, GPR, 
2790
    /* RET */
2791
    /* SA_F_I */
2792
    GPR, GPR, immShift, 
2793
    /* SA_I */
2794
    GPR, GPR, immShift, 
2795
    /* SCC */
2796
    GPR, CCOp, 
2797
    /* SELECT */
2798
    GPR, GPR, GPR, CCOp, 
2799
    /* SFSUB_F_RI_HI */
2800
    GPR, i32hi16, 
2801
    /* SFSUB_F_RI_LO */
2802
    GPR, i32lo16z, 
2803
    /* SFSUB_F_RR */
2804
    GPR, GPR, 
2805
    /* SHL_F_R */
2806
    GPR, GPR, GPR, i32imm, 
2807
    /* SHL_R */
2808
    GPR, GPR, GPR, i32imm, 
2809
    /* SLI */
2810
    GPR, i32lo21, 
2811
    /* SL_F_I */
2812
    GPR, GPR, immShift, 
2813
    /* SL_I */
2814
    GPR, GPR, immShift, 
2815
    /* SRA_F_R */
2816
    GPR, GPR, GPR, i32imm, 
2817
    /* SRA_R */
2818
    GPR, GPR, GPR, i32imm, 
2819
    /* SRL_F_R */
2820
    GPR, GPR, GPR, i32imm, 
2821
    /* SRL_R */
2822
    GPR, GPR, GPR, i32imm, 
2823
    /* STADDR */
2824
    GPR, i32lo21, 
2825
    /* STB_RI */
2826
    GPR, GPR, imm10, AluOp, 
2827
    /* STB_RR */
2828
    GPR, GPR, GPR, AluOp, 
2829
    /* STH_RI */
2830
    GPR, GPR, imm10, AluOp, 
2831
    /* STH_RR */
2832
    GPR, GPR, GPR, AluOp, 
2833
    /* SUBB_F_I_HI */
2834
    GPR, GPR, i32hi16, 
2835
    /* SUBB_F_I_LO */
2836
    GPR, GPR, i32lo16z, 
2837
    /* SUBB_F_R */
2838
    GPR, GPR, GPR, i32imm, 
2839
    /* SUBB_I_HI */
2840
    GPR, GPR, i32hi16, 
2841
    /* SUBB_I_LO */
2842
    GPR, GPR, i32lo16z, 
2843
    /* SUBB_R */
2844
    GPR, GPR, GPR, i32imm, 
2845
    /* SUB_F_I_HI */
2846
    GPR, GPR, i32hi16, 
2847
    /* SUB_F_I_LO */
2848
    GPR, GPR, i32lo16z, 
2849
    /* SUB_F_R */
2850
    GPR, GPR, GPR, i32imm, 
2851
    /* SUB_I_HI */
2852
    GPR, GPR, i32hi16, 
2853
    /* SUB_I_LO */
2854
    GPR, GPR, i32lo16z, 
2855
    /* SUB_R */
2856
    GPR, GPR, GPR, i32imm, 
2857
    /* SW_RI */
2858
    GPR, GPR, i32lo16s, AluOp, 
2859
    /* SW_RR */
2860
    GPR, GPR, GPR, AluOp, 
2861
    /* TRAILZ */
2862
    GPR, GPR, 
2863
    /* XOR_F_I_HI */
2864
    GPR, GPR, i32hi16, 
2865
    /* XOR_F_I_LO */
2866
    GPR, GPR, i32lo16z, 
2867
    /* XOR_F_R */
2868
    GPR, GPR, GPR, i32imm, 
2869
    /* XOR_I_HI */
2870
    GPR, GPR, i32hi16, 
2871
    /* XOR_I_LO */
2872
    GPR, GPR, i32lo16z, 
2873
    /* XOR_R */
2874
    GPR, GPR, GPR, i32imm, 
2875
  };
2876
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
2877
}
2878
} // end namespace Lanai
2879
} // end namespace llvm
2880
#endif // GET_INSTRINFO_OPERAND_TYPE
2881
2882
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
2883
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
2884
namespace llvm {
2885
namespace Lanai {
2886
LLVM_READONLY
2887
static int getMemOperandSize(int OpType) {
2888
  switch (OpType) {
2889
  default: return 0;
2890
  }
2891
}
2892
} // end namespace Lanai
2893
} // end namespace llvm
2894
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
2895
2896
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
2897
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
2898
namespace llvm {
2899
namespace Lanai {
2900
LLVM_READONLY static unsigned
2901
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
2902
  return LogicalOpIdx;
2903
}
2904
LLVM_READONLY static inline unsigned
2905
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
2906
  auto S = 0U;
2907
  for (auto i = 0U; i < LogicalOpIdx; ++i)
2908
    S += getLogicalOperandSize(Opcode, i);
2909
  return S;
2910
}
2911
} // end namespace Lanai
2912
} // end namespace llvm
2913
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
2914
2915
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
2916
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
2917
namespace llvm {
2918
namespace Lanai {
2919
LLVM_READONLY static int
2920
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
2921
  return -1;
2922
}
2923
} // end namespace Lanai
2924
} // end namespace llvm
2925
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
2926
2927
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
2928
#undef GET_INSTRINFO_MC_HELPER_DECLS
2929
2930
namespace llvm {
2931
class MCInst;
2932
class FeatureBitset;
2933
2934
namespace Lanai_MC {
2935
2936
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
2937
2938
} // end namespace Lanai_MC
2939
} // end namespace llvm
2940
2941
#endif // GET_INSTRINFO_MC_HELPER_DECLS
2942
2943
#ifdef GET_INSTRINFO_MC_HELPERS
2944
#undef GET_INSTRINFO_MC_HELPERS
2945
2946
namespace llvm {
2947
namespace Lanai_MC {
2948
2949
} // end namespace Lanai_MC
2950
} // end namespace llvm
2951
2952
#endif // GET_GENISTRINFO_MC_HELPERS
2953
2954
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
2955
    defined(GET_AVAILABLE_OPCODE_CHECKER)
2956
#define GET_COMPUTE_FEATURES
2957
#endif
2958
#ifdef GET_COMPUTE_FEATURES
2959
#undef GET_COMPUTE_FEATURES
2960
namespace llvm {
2961
namespace Lanai_MC {
2962
2963
// Bits for subtarget features that participate in instruction matching.
2964
enum SubtargetFeatureBits : uint8_t {
2965
};
2966
2967
0
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
2968
0
  FeatureBitset Features;
2969
0
  return Features;
2970
0
}
2971
2972
0
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
2973
0
  enum : uint8_t {
2974
0
    CEFBS_None,
2975
0
  };
2976
2977
0
  static constexpr FeatureBitset FeatureBitsets[] = {
2978
0
    {}, // CEFBS_None
2979
0
  };
2980
0
  static constexpr uint8_t RequiredFeaturesRefs[] = {
2981
0
    CEFBS_None, // PHI = 0
2982
0
    CEFBS_None, // INLINEASM = 1
2983
0
    CEFBS_None, // INLINEASM_BR = 2
2984
0
    CEFBS_None, // CFI_INSTRUCTION = 3
2985
0
    CEFBS_None, // EH_LABEL = 4
2986
0
    CEFBS_None, // GC_LABEL = 5
2987
0
    CEFBS_None, // ANNOTATION_LABEL = 6
2988
0
    CEFBS_None, // KILL = 7
2989
0
    CEFBS_None, // EXTRACT_SUBREG = 8
2990
0
    CEFBS_None, // INSERT_SUBREG = 9
2991
0
    CEFBS_None, // IMPLICIT_DEF = 10
2992
0
    CEFBS_None, // SUBREG_TO_REG = 11
2993
0
    CEFBS_None, // COPY_TO_REGCLASS = 12
2994
0
    CEFBS_None, // DBG_VALUE = 13
2995
0
    CEFBS_None, // DBG_VALUE_LIST = 14
2996
0
    CEFBS_None, // DBG_INSTR_REF = 15
2997
0
    CEFBS_None, // DBG_PHI = 16
2998
0
    CEFBS_None, // DBG_LABEL = 17
2999
0
    CEFBS_None, // REG_SEQUENCE = 18
3000
0
    CEFBS_None, // COPY = 19
3001
0
    CEFBS_None, // BUNDLE = 20
3002
0
    CEFBS_None, // LIFETIME_START = 21
3003
0
    CEFBS_None, // LIFETIME_END = 22
3004
0
    CEFBS_None, // PSEUDO_PROBE = 23
3005
0
    CEFBS_None, // ARITH_FENCE = 24
3006
0
    CEFBS_None, // STACKMAP = 25
3007
0
    CEFBS_None, // FENTRY_CALL = 26
3008
0
    CEFBS_None, // PATCHPOINT = 27
3009
0
    CEFBS_None, // LOAD_STACK_GUARD = 28
3010
0
    CEFBS_None, // PREALLOCATED_SETUP = 29
3011
0
    CEFBS_None, // PREALLOCATED_ARG = 30
3012
0
    CEFBS_None, // STATEPOINT = 31
3013
0
    CEFBS_None, // LOCAL_ESCAPE = 32
3014
0
    CEFBS_None, // FAULTING_OP = 33
3015
0
    CEFBS_None, // PATCHABLE_OP = 34
3016
0
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
3017
0
    CEFBS_None, // PATCHABLE_RET = 36
3018
0
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
3019
0
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
3020
0
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
3021
0
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
3022
0
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
3023
0
    CEFBS_None, // MEMBARRIER = 42
3024
0
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
3025
0
    CEFBS_None, // G_ASSERT_SEXT = 44
3026
0
    CEFBS_None, // G_ASSERT_ZEXT = 45
3027
0
    CEFBS_None, // G_ASSERT_ALIGN = 46
3028
0
    CEFBS_None, // G_ADD = 47
3029
0
    CEFBS_None, // G_SUB = 48
3030
0
    CEFBS_None, // G_MUL = 49
3031
0
    CEFBS_None, // G_SDIV = 50
3032
0
    CEFBS_None, // G_UDIV = 51
3033
0
    CEFBS_None, // G_SREM = 52
3034
0
    CEFBS_None, // G_UREM = 53
3035
0
    CEFBS_None, // G_SDIVREM = 54
3036
0
    CEFBS_None, // G_UDIVREM = 55
3037
0
    CEFBS_None, // G_AND = 56
3038
0
    CEFBS_None, // G_OR = 57
3039
0
    CEFBS_None, // G_XOR = 58
3040
0
    CEFBS_None, // G_IMPLICIT_DEF = 59
3041
0
    CEFBS_None, // G_PHI = 60
3042
0
    CEFBS_None, // G_FRAME_INDEX = 61
3043
0
    CEFBS_None, // G_GLOBAL_VALUE = 62
3044
0
    CEFBS_None, // G_CONSTANT_POOL = 63
3045
0
    CEFBS_None, // G_EXTRACT = 64
3046
0
    CEFBS_None, // G_UNMERGE_VALUES = 65
3047
0
    CEFBS_None, // G_INSERT = 66
3048
0
    CEFBS_None, // G_MERGE_VALUES = 67
3049
0
    CEFBS_None, // G_BUILD_VECTOR = 68
3050
0
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
3051
0
    CEFBS_None, // G_CONCAT_VECTORS = 70
3052
0
    CEFBS_None, // G_PTRTOINT = 71
3053
0
    CEFBS_None, // G_INTTOPTR = 72
3054
0
    CEFBS_None, // G_BITCAST = 73
3055
0
    CEFBS_None, // G_FREEZE = 74
3056
0
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
3057
0
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
3058
0
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
3059
0
    CEFBS_None, // G_INTRINSIC_ROUND = 78
3060
0
    CEFBS_None, // G_INTRINSIC_LRINT = 79
3061
0
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
3062
0
    CEFBS_None, // G_READCYCLECOUNTER = 81
3063
0
    CEFBS_None, // G_LOAD = 82
3064
0
    CEFBS_None, // G_SEXTLOAD = 83
3065
0
    CEFBS_None, // G_ZEXTLOAD = 84
3066
0
    CEFBS_None, // G_INDEXED_LOAD = 85
3067
0
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
3068
0
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
3069
0
    CEFBS_None, // G_STORE = 88
3070
0
    CEFBS_None, // G_INDEXED_STORE = 89
3071
0
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
3072
0
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
3073
0
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
3074
0
    CEFBS_None, // G_ATOMICRMW_ADD = 93
3075
0
    CEFBS_None, // G_ATOMICRMW_SUB = 94
3076
0
    CEFBS_None, // G_ATOMICRMW_AND = 95
3077
0
    CEFBS_None, // G_ATOMICRMW_NAND = 96
3078
0
    CEFBS_None, // G_ATOMICRMW_OR = 97
3079
0
    CEFBS_None, // G_ATOMICRMW_XOR = 98
3080
0
    CEFBS_None, // G_ATOMICRMW_MAX = 99
3081
0
    CEFBS_None, // G_ATOMICRMW_MIN = 100
3082
0
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
3083
0
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
3084
0
    CEFBS_None, // G_ATOMICRMW_FADD = 103
3085
0
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
3086
0
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
3087
0
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
3088
0
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
3089
0
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
3090
0
    CEFBS_None, // G_FENCE = 109
3091
0
    CEFBS_None, // G_PREFETCH = 110
3092
0
    CEFBS_None, // G_BRCOND = 111
3093
0
    CEFBS_None, // G_BRINDIRECT = 112
3094
0
    CEFBS_None, // G_INVOKE_REGION_START = 113
3095
0
    CEFBS_None, // G_INTRINSIC = 114
3096
0
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
3097
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
3098
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
3099
0
    CEFBS_None, // G_ANYEXT = 118
3100
0
    CEFBS_None, // G_TRUNC = 119
3101
0
    CEFBS_None, // G_CONSTANT = 120
3102
0
    CEFBS_None, // G_FCONSTANT = 121
3103
0
    CEFBS_None, // G_VASTART = 122
3104
0
    CEFBS_None, // G_VAARG = 123
3105
0
    CEFBS_None, // G_SEXT = 124
3106
0
    CEFBS_None, // G_SEXT_INREG = 125
3107
0
    CEFBS_None, // G_ZEXT = 126
3108
0
    CEFBS_None, // G_SHL = 127
3109
0
    CEFBS_None, // G_LSHR = 128
3110
0
    CEFBS_None, // G_ASHR = 129
3111
0
    CEFBS_None, // G_FSHL = 130
3112
0
    CEFBS_None, // G_FSHR = 131
3113
0
    CEFBS_None, // G_ROTR = 132
3114
0
    CEFBS_None, // G_ROTL = 133
3115
0
    CEFBS_None, // G_ICMP = 134
3116
0
    CEFBS_None, // G_FCMP = 135
3117
0
    CEFBS_None, // G_SELECT = 136
3118
0
    CEFBS_None, // G_UADDO = 137
3119
0
    CEFBS_None, // G_UADDE = 138
3120
0
    CEFBS_None, // G_USUBO = 139
3121
0
    CEFBS_None, // G_USUBE = 140
3122
0
    CEFBS_None, // G_SADDO = 141
3123
0
    CEFBS_None, // G_SADDE = 142
3124
0
    CEFBS_None, // G_SSUBO = 143
3125
0
    CEFBS_None, // G_SSUBE = 144
3126
0
    CEFBS_None, // G_UMULO = 145
3127
0
    CEFBS_None, // G_SMULO = 146
3128
0
    CEFBS_None, // G_UMULH = 147
3129
0
    CEFBS_None, // G_SMULH = 148
3130
0
    CEFBS_None, // G_UADDSAT = 149
3131
0
    CEFBS_None, // G_SADDSAT = 150
3132
0
    CEFBS_None, // G_USUBSAT = 151
3133
0
    CEFBS_None, // G_SSUBSAT = 152
3134
0
    CEFBS_None, // G_USHLSAT = 153
3135
0
    CEFBS_None, // G_SSHLSAT = 154
3136
0
    CEFBS_None, // G_SMULFIX = 155
3137
0
    CEFBS_None, // G_UMULFIX = 156
3138
0
    CEFBS_None, // G_SMULFIXSAT = 157
3139
0
    CEFBS_None, // G_UMULFIXSAT = 158
3140
0
    CEFBS_None, // G_SDIVFIX = 159
3141
0
    CEFBS_None, // G_UDIVFIX = 160
3142
0
    CEFBS_None, // G_SDIVFIXSAT = 161
3143
0
    CEFBS_None, // G_UDIVFIXSAT = 162
3144
0
    CEFBS_None, // G_FADD = 163
3145
0
    CEFBS_None, // G_FSUB = 164
3146
0
    CEFBS_None, // G_FMUL = 165
3147
0
    CEFBS_None, // G_FMA = 166
3148
0
    CEFBS_None, // G_FMAD = 167
3149
0
    CEFBS_None, // G_FDIV = 168
3150
0
    CEFBS_None, // G_FREM = 169
3151
0
    CEFBS_None, // G_FPOW = 170
3152
0
    CEFBS_None, // G_FPOWI = 171
3153
0
    CEFBS_None, // G_FEXP = 172
3154
0
    CEFBS_None, // G_FEXP2 = 173
3155
0
    CEFBS_None, // G_FEXP10 = 174
3156
0
    CEFBS_None, // G_FLOG = 175
3157
0
    CEFBS_None, // G_FLOG2 = 176
3158
0
    CEFBS_None, // G_FLOG10 = 177
3159
0
    CEFBS_None, // G_FLDEXP = 178
3160
0
    CEFBS_None, // G_FFREXP = 179
3161
0
    CEFBS_None, // G_FNEG = 180
3162
0
    CEFBS_None, // G_FPEXT = 181
3163
0
    CEFBS_None, // G_FPTRUNC = 182
3164
0
    CEFBS_None, // G_FPTOSI = 183
3165
0
    CEFBS_None, // G_FPTOUI = 184
3166
0
    CEFBS_None, // G_SITOFP = 185
3167
0
    CEFBS_None, // G_UITOFP = 186
3168
0
    CEFBS_None, // G_FABS = 187
3169
0
    CEFBS_None, // G_FCOPYSIGN = 188
3170
0
    CEFBS_None, // G_IS_FPCLASS = 189
3171
0
    CEFBS_None, // G_FCANONICALIZE = 190
3172
0
    CEFBS_None, // G_FMINNUM = 191
3173
0
    CEFBS_None, // G_FMAXNUM = 192
3174
0
    CEFBS_None, // G_FMINNUM_IEEE = 193
3175
0
    CEFBS_None, // G_FMAXNUM_IEEE = 194
3176
0
    CEFBS_None, // G_FMINIMUM = 195
3177
0
    CEFBS_None, // G_FMAXIMUM = 196
3178
0
    CEFBS_None, // G_GET_FPENV = 197
3179
0
    CEFBS_None, // G_SET_FPENV = 198
3180
0
    CEFBS_None, // G_RESET_FPENV = 199
3181
0
    CEFBS_None, // G_GET_FPMODE = 200
3182
0
    CEFBS_None, // G_SET_FPMODE = 201
3183
0
    CEFBS_None, // G_RESET_FPMODE = 202
3184
0
    CEFBS_None, // G_PTR_ADD = 203
3185
0
    CEFBS_None, // G_PTRMASK = 204
3186
0
    CEFBS_None, // G_SMIN = 205
3187
0
    CEFBS_None, // G_SMAX = 206
3188
0
    CEFBS_None, // G_UMIN = 207
3189
0
    CEFBS_None, // G_UMAX = 208
3190
0
    CEFBS_None, // G_ABS = 209
3191
0
    CEFBS_None, // G_LROUND = 210
3192
0
    CEFBS_None, // G_LLROUND = 211
3193
0
    CEFBS_None, // G_BR = 212
3194
0
    CEFBS_None, // G_BRJT = 213
3195
0
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
3196
0
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
3197
0
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
3198
0
    CEFBS_None, // G_CTTZ = 217
3199
0
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
3200
0
    CEFBS_None, // G_CTLZ = 219
3201
0
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
3202
0
    CEFBS_None, // G_CTPOP = 221
3203
0
    CEFBS_None, // G_BSWAP = 222
3204
0
    CEFBS_None, // G_BITREVERSE = 223
3205
0
    CEFBS_None, // G_FCEIL = 224
3206
0
    CEFBS_None, // G_FCOS = 225
3207
0
    CEFBS_None, // G_FSIN = 226
3208
0
    CEFBS_None, // G_FSQRT = 227
3209
0
    CEFBS_None, // G_FFLOOR = 228
3210
0
    CEFBS_None, // G_FRINT = 229
3211
0
    CEFBS_None, // G_FNEARBYINT = 230
3212
0
    CEFBS_None, // G_ADDRSPACE_CAST = 231
3213
0
    CEFBS_None, // G_BLOCK_ADDR = 232
3214
0
    CEFBS_None, // G_JUMP_TABLE = 233
3215
0
    CEFBS_None, // G_DYN_STACKALLOC = 234
3216
0
    CEFBS_None, // G_STACKSAVE = 235
3217
0
    CEFBS_None, // G_STACKRESTORE = 236
3218
0
    CEFBS_None, // G_STRICT_FADD = 237
3219
0
    CEFBS_None, // G_STRICT_FSUB = 238
3220
0
    CEFBS_None, // G_STRICT_FMUL = 239
3221
0
    CEFBS_None, // G_STRICT_FDIV = 240
3222
0
    CEFBS_None, // G_STRICT_FREM = 241
3223
0
    CEFBS_None, // G_STRICT_FMA = 242
3224
0
    CEFBS_None, // G_STRICT_FSQRT = 243
3225
0
    CEFBS_None, // G_STRICT_FLDEXP = 244
3226
0
    CEFBS_None, // G_READ_REGISTER = 245
3227
0
    CEFBS_None, // G_WRITE_REGISTER = 246
3228
0
    CEFBS_None, // G_MEMCPY = 247
3229
0
    CEFBS_None, // G_MEMCPY_INLINE = 248
3230
0
    CEFBS_None, // G_MEMMOVE = 249
3231
0
    CEFBS_None, // G_MEMSET = 250
3232
0
    CEFBS_None, // G_BZERO = 251
3233
0
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
3234
0
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
3235
0
    CEFBS_None, // G_VECREDUCE_FADD = 254
3236
0
    CEFBS_None, // G_VECREDUCE_FMUL = 255
3237
0
    CEFBS_None, // G_VECREDUCE_FMAX = 256
3238
0
    CEFBS_None, // G_VECREDUCE_FMIN = 257
3239
0
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
3240
0
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
3241
0
    CEFBS_None, // G_VECREDUCE_ADD = 260
3242
0
    CEFBS_None, // G_VECREDUCE_MUL = 261
3243
0
    CEFBS_None, // G_VECREDUCE_AND = 262
3244
0
    CEFBS_None, // G_VECREDUCE_OR = 263
3245
0
    CEFBS_None, // G_VECREDUCE_XOR = 264
3246
0
    CEFBS_None, // G_VECREDUCE_SMAX = 265
3247
0
    CEFBS_None, // G_VECREDUCE_SMIN = 266
3248
0
    CEFBS_None, // G_VECREDUCE_UMAX = 267
3249
0
    CEFBS_None, // G_VECREDUCE_UMIN = 268
3250
0
    CEFBS_None, // G_SBFX = 269
3251
0
    CEFBS_None, // G_UBFX = 270
3252
0
    CEFBS_None, // ADJCALLSTACKDOWN = 271
3253
0
    CEFBS_None, // ADJCALLSTACKUP = 272
3254
0
    CEFBS_None, // ADJDYNALLOC = 273
3255
0
    CEFBS_None, // CALL = 274
3256
0
    CEFBS_None, // CALLR = 275
3257
0
    CEFBS_None, // ADDC_F_I_HI = 276
3258
0
    CEFBS_None, // ADDC_F_I_LO = 277
3259
0
    CEFBS_None, // ADDC_F_R = 278
3260
0
    CEFBS_None, // ADDC_I_HI = 279
3261
0
    CEFBS_None, // ADDC_I_LO = 280
3262
0
    CEFBS_None, // ADDC_R = 281
3263
0
    CEFBS_None, // ADD_F_I_HI = 282
3264
0
    CEFBS_None, // ADD_F_I_LO = 283
3265
0
    CEFBS_None, // ADD_F_R = 284
3266
0
    CEFBS_None, // ADD_I_HI = 285
3267
0
    CEFBS_None, // ADD_I_LO = 286
3268
0
    CEFBS_None, // ADD_R = 287
3269
0
    CEFBS_None, // AND_F_I_HI = 288
3270
0
    CEFBS_None, // AND_F_I_LO = 289
3271
0
    CEFBS_None, // AND_F_R = 290
3272
0
    CEFBS_None, // AND_I_HI = 291
3273
0
    CEFBS_None, // AND_I_LO = 292
3274
0
    CEFBS_None, // AND_R = 293
3275
0
    CEFBS_None, // BRCC = 294
3276
0
    CEFBS_None, // BRIND_CC = 295
3277
0
    CEFBS_None, // BRIND_CCA = 296
3278
0
    CEFBS_None, // BRR = 297
3279
0
    CEFBS_None, // BT = 298
3280
0
    CEFBS_None, // JR = 299
3281
0
    CEFBS_None, // LDADDR = 300
3282
0
    CEFBS_None, // LDBs_RI = 301
3283
0
    CEFBS_None, // LDBs_RR = 302
3284
0
    CEFBS_None, // LDBz_RI = 303
3285
0
    CEFBS_None, // LDBz_RR = 304
3286
0
    CEFBS_None, // LDHs_RI = 305
3287
0
    CEFBS_None, // LDHs_RR = 306
3288
0
    CEFBS_None, // LDHz_RI = 307
3289
0
    CEFBS_None, // LDHz_RR = 308
3290
0
    CEFBS_None, // LDW_RI = 309
3291
0
    CEFBS_None, // LDW_RR = 310
3292
0
    CEFBS_None, // LDWz_RR = 311
3293
0
    CEFBS_None, // LEADZ = 312
3294
0
    CEFBS_None, // LOG0 = 313
3295
0
    CEFBS_None, // LOG1 = 314
3296
0
    CEFBS_None, // LOG2 = 315
3297
0
    CEFBS_None, // LOG3 = 316
3298
0
    CEFBS_None, // LOG4 = 317
3299
0
    CEFBS_None, // MOVHI = 318
3300
0
    CEFBS_None, // NOP = 319
3301
0
    CEFBS_None, // OR_F_I_HI = 320
3302
0
    CEFBS_None, // OR_F_I_LO = 321
3303
0
    CEFBS_None, // OR_F_R = 322
3304
0
    CEFBS_None, // OR_I_HI = 323
3305
0
    CEFBS_None, // OR_I_LO = 324
3306
0
    CEFBS_None, // OR_R = 325
3307
0
    CEFBS_None, // POPC = 326
3308
0
    CEFBS_None, // RET = 327
3309
0
    CEFBS_None, // SA_F_I = 328
3310
0
    CEFBS_None, // SA_I = 329
3311
0
    CEFBS_None, // SCC = 330
3312
0
    CEFBS_None, // SELECT = 331
3313
0
    CEFBS_None, // SFSUB_F_RI_HI = 332
3314
0
    CEFBS_None, // SFSUB_F_RI_LO = 333
3315
0
    CEFBS_None, // SFSUB_F_RR = 334
3316
0
    CEFBS_None, // SHL_F_R = 335
3317
0
    CEFBS_None, // SHL_R = 336
3318
0
    CEFBS_None, // SLI = 337
3319
0
    CEFBS_None, // SL_F_I = 338
3320
0
    CEFBS_None, // SL_I = 339
3321
0
    CEFBS_None, // SRA_F_R = 340
3322
0
    CEFBS_None, // SRA_R = 341
3323
0
    CEFBS_None, // SRL_F_R = 342
3324
0
    CEFBS_None, // SRL_R = 343
3325
0
    CEFBS_None, // STADDR = 344
3326
0
    CEFBS_None, // STB_RI = 345
3327
0
    CEFBS_None, // STB_RR = 346
3328
0
    CEFBS_None, // STH_RI = 347
3329
0
    CEFBS_None, // STH_RR = 348
3330
0
    CEFBS_None, // SUBB_F_I_HI = 349
3331
0
    CEFBS_None, // SUBB_F_I_LO = 350
3332
0
    CEFBS_None, // SUBB_F_R = 351
3333
0
    CEFBS_None, // SUBB_I_HI = 352
3334
0
    CEFBS_None, // SUBB_I_LO = 353
3335
0
    CEFBS_None, // SUBB_R = 354
3336
0
    CEFBS_None, // SUB_F_I_HI = 355
3337
0
    CEFBS_None, // SUB_F_I_LO = 356
3338
0
    CEFBS_None, // SUB_F_R = 357
3339
0
    CEFBS_None, // SUB_I_HI = 358
3340
0
    CEFBS_None, // SUB_I_LO = 359
3341
0
    CEFBS_None, // SUB_R = 360
3342
0
    CEFBS_None, // SW_RI = 361
3343
0
    CEFBS_None, // SW_RR = 362
3344
0
    CEFBS_None, // TRAILZ = 363
3345
0
    CEFBS_None, // XOR_F_I_HI = 364
3346
0
    CEFBS_None, // XOR_F_I_LO = 365
3347
0
    CEFBS_None, // XOR_F_R = 366
3348
0
    CEFBS_None, // XOR_I_HI = 367
3349
0
    CEFBS_None, // XOR_I_LO = 368
3350
0
    CEFBS_None, // XOR_R = 369
3351
0
  };
3352
3353
0
  assert(Opcode < 370);
3354
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
3355
0
}
3356
3357
} // end namespace Lanai_MC
3358
} // end namespace llvm
3359
#endif // GET_COMPUTE_FEATURES
3360
3361
#ifdef GET_AVAILABLE_OPCODE_CHECKER
3362
#undef GET_AVAILABLE_OPCODE_CHECKER
3363
namespace llvm {
3364
namespace Lanai_MC {
3365
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
3366
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3367
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3368
  FeatureBitset MissingFeatures =
3369
      (AvailableFeatures & RequiredFeatures) ^
3370
      RequiredFeatures;
3371
  return !MissingFeatures.any();
3372
}
3373
} // end namespace Lanai_MC
3374
} // end namespace llvm
3375
#endif // GET_AVAILABLE_OPCODE_CHECKER
3376
3377
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
3378
#undef ENABLE_INSTR_PREDICATE_VERIFIER
3379
#include <sstream>
3380
3381
namespace llvm {
3382
namespace Lanai_MC {
3383
3384
#ifndef NDEBUG
3385
static const char *SubtargetFeatureNames[] = {
3386
  nullptr
3387
};
3388
3389
#endif // NDEBUG
3390
3391
void verifyInstructionPredicates(
3392
0
    unsigned Opcode, const FeatureBitset &Features) {
3393
0
#ifndef NDEBUG
3394
0
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
3395
0
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
3396
0
  FeatureBitset MissingFeatures =
3397
0
      (AvailableFeatures & RequiredFeatures) ^
3398
0
      RequiredFeatures;
3399
0
  if (MissingFeatures.any()) {
3400
0
    std::ostringstream Msg;
3401
0
    Msg << "Attempting to emit " << &LanaiInstrNameData[LanaiInstrNameIndices[Opcode]]
3402
0
        << " instruction but the ";
3403
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
3404
0
      if (MissingFeatures.test(i))
3405
0
        Msg << SubtargetFeatureNames[i] << " ";
3406
0
    Msg << "predicate(s) are not met";
3407
0
    report_fatal_error(Msg.str().c_str());
3408
0
  }
3409
0
#endif // NDEBUG
3410
0
}
3411
} // end namespace Lanai_MC
3412
} // end namespace llvm
3413
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
3414
3415
#ifdef GET_INSTRMAP_INFO
3416
#undef GET_INSTRMAP_INFO
3417
namespace llvm {
3418
3419
namespace Lanai {
3420
3421
enum PostEncoderMethod {
3422
  PostEncoderMethod_adjustPqBitsSpls
3423
};
3424
3425
// splsIdempotent
3426
LLVM_READONLY
3427
0
int splsIdempotent(uint16_t Opcode) {
3428
0
static const uint16_t splsIdempotentTable[][2] = {
3429
0
  { Lanai::LDBs_RI, Lanai::LDBs_RI },
3430
0
  { Lanai::LDBz_RI, Lanai::LDBz_RI },
3431
0
  { Lanai::LDHs_RI, Lanai::LDHs_RI },
3432
0
  { Lanai::LDHz_RI, Lanai::LDHz_RI },
3433
0
  { Lanai::STB_RI, Lanai::STB_RI },
3434
0
  { Lanai::STH_RI, Lanai::STH_RI },
3435
0
}; // End of splsIdempotentTable
3436
3437
0
  unsigned mid;
3438
0
  unsigned start = 0;
3439
0
  unsigned end = 6;
3440
0
  while (start < end) {
3441
0
    mid = start + (end - start) / 2;
3442
0
    if (Opcode == splsIdempotentTable[mid][0]) {
3443
0
      break;
3444
0
    }
3445
0
    if (Opcode < splsIdempotentTable[mid][0])
3446
0
      end = mid;
3447
0
    else
3448
0
      start = mid + 1;
3449
0
  }
3450
0
  if (start == end)
3451
0
    return -1; // Instruction doesn't exist in this table.
3452
3453
0
  return splsIdempotentTable[mid][1];
3454
0
}
3455
3456
} // end namespace Lanai
3457
} // end namespace llvm
3458
#endif // GET_INSTRMAP_INFO
3459