/src/build/lib/Target/Lanai/LanaiGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t LanaiMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(268632064), // ADDC_F_I_HI |
290 | 0 | UINT64_C(268566528), // ADDC_F_I_LO |
291 | 0 | UINT64_C(3221356800), // ADDC_F_R |
292 | 0 | UINT64_C(268500992), // ADDC_I_HI |
293 | 0 | UINT64_C(268435456), // ADDC_I_LO |
294 | 0 | UINT64_C(3221225728), // ADDC_R |
295 | 0 | UINT64_C(196608), // ADD_F_I_HI |
296 | 0 | UINT64_C(131072), // ADD_F_I_LO |
297 | 0 | UINT64_C(3221356544), // ADD_F_R |
298 | 0 | UINT64_C(65536), // ADD_I_HI |
299 | 0 | UINT64_C(0), // ADD_I_LO |
300 | 0 | UINT64_C(3221225472), // ADD_R |
301 | 0 | UINT64_C(1073938432), // AND_F_I_HI |
302 | 0 | UINT64_C(1073872896), // AND_F_I_LO |
303 | 0 | UINT64_C(3221357568), // AND_F_R |
304 | 0 | UINT64_C(1073807360), // AND_I_HI |
305 | 0 | UINT64_C(1073741824), // AND_I_LO |
306 | 0 | UINT64_C(3221226496), // AND_R |
307 | 0 | UINT64_C(3758096384), // BRCC |
308 | 0 | UINT64_C(3238003968), // BRIND_CC |
309 | 0 | UINT64_C(3238003968), // BRIND_CCA |
310 | 0 | UINT64_C(3774873602), // BRR |
311 | 0 | UINT64_C(3758096384), // BT |
312 | 0 | UINT64_C(3238003968), // JR |
313 | 0 | UINT64_C(4026531840), // LDADDR |
314 | 0 | UINT64_C(4026744832), // LDBs_RI |
315 | 0 | UINT64_C(2684354564), // LDBs_RR |
316 | 0 | UINT64_C(4026748928), // LDBz_RI |
317 | 0 | UINT64_C(2684354565), // LDBz_RR |
318 | 0 | UINT64_C(4026728448), // LDHs_RI |
319 | 0 | UINT64_C(2684354560), // LDHs_RR |
320 | 0 | UINT64_C(4026732544), // LDHz_RI |
321 | 0 | UINT64_C(2684354561), // LDHz_RR |
322 | 0 | UINT64_C(2147483648), // LDW_RI |
323 | 0 | UINT64_C(2684354562), // LDW_RR |
324 | 0 | UINT64_C(2684354563), // LDWz_RR |
325 | 0 | UINT64_C(3489660930), // LEADZ |
326 | 0 | UINT64_C(2), // LOG0 |
327 | 0 | UINT64_C(3), // LOG1 |
328 | 0 | UINT64_C(4), // LOG2 |
329 | 0 | UINT64_C(5), // LOG3 |
330 | 0 | UINT64_C(6), // LOG4 |
331 | 0 | UINT64_C(65536), // MOVHI |
332 | 0 | UINT64_C(1), // NOP |
333 | 0 | UINT64_C(1342373888), // OR_F_I_HI |
334 | 0 | UINT64_C(1342308352), // OR_F_I_LO |
335 | 0 | UINT64_C(3221357824), // OR_F_R |
336 | 0 | UINT64_C(1342242816), // OR_I_HI |
337 | 0 | UINT64_C(1342177280), // OR_I_LO |
338 | 0 | UINT64_C(3221226752), // OR_R |
339 | 0 | UINT64_C(3489660929), // POPC |
340 | 0 | UINT64_C(2165768188), // RET |
341 | 0 | UINT64_C(1879244800), // SA_F_I |
342 | 0 | UINT64_C(1879113728), // SA_I |
343 | 0 | UINT64_C(3758096386), // SCC |
344 | 0 | UINT64_C(3221227264), // SELECT |
345 | 0 | UINT64_C(537067520), // SFSUB_F_RI_HI |
346 | 0 | UINT64_C(537001984), // SFSUB_F_RI_LO |
347 | 0 | UINT64_C(3221357056), // SFSUB_F_RR |
348 | 0 | UINT64_C(3221358464), // SHL_F_R |
349 | 0 | UINT64_C(3221227392), // SHL_R |
350 | 0 | UINT64_C(4026662912), // SLI |
351 | 0 | UINT64_C(1879179264), // SL_F_I |
352 | 0 | UINT64_C(1879048192), // SL_I |
353 | 0 | UINT64_C(3221358528), // SRA_F_R |
354 | 0 | UINT64_C(3221227456), // SRA_R |
355 | 0 | UINT64_C(3221358464), // SRL_F_R |
356 | 0 | UINT64_C(3221227392), // SRL_R |
357 | 0 | UINT64_C(4026597376), // STADDR |
358 | 0 | UINT64_C(4026753024), // STB_RI |
359 | 0 | UINT64_C(2952790020), // STB_RR |
360 | 0 | UINT64_C(4026736640), // STH_RI |
361 | 0 | UINT64_C(2952790016), // STH_RR |
362 | 0 | UINT64_C(805502976), // SUBB_F_I_HI |
363 | 0 | UINT64_C(805437440), // SUBB_F_I_LO |
364 | 0 | UINT64_C(3221357312), // SUBB_F_R |
365 | 0 | UINT64_C(805371904), // SUBB_I_HI |
366 | 0 | UINT64_C(805306368), // SUBB_I_LO |
367 | 0 | UINT64_C(3221226240), // SUBB_R |
368 | 0 | UINT64_C(537067520), // SUB_F_I_HI |
369 | 0 | UINT64_C(537001984), // SUB_F_I_LO |
370 | 0 | UINT64_C(3221357056), // SUB_F_R |
371 | 0 | UINT64_C(536936448), // SUB_I_HI |
372 | 0 | UINT64_C(536870912), // SUB_I_LO |
373 | 0 | UINT64_C(3221225984), // SUB_R |
374 | 0 | UINT64_C(2415919104), // SW_RI |
375 | 0 | UINT64_C(2952790018), // SW_RR |
376 | 0 | UINT64_C(3489660931), // TRAILZ |
377 | 0 | UINT64_C(1610809344), // XOR_F_I_HI |
378 | 0 | UINT64_C(1610743808), // XOR_F_I_LO |
379 | 0 | UINT64_C(3221358080), // XOR_F_R |
380 | 0 | UINT64_C(1610678272), // XOR_I_HI |
381 | 0 | UINT64_C(1610612736), // XOR_I_LO |
382 | 0 | UINT64_C(3221227008), // XOR_R |
383 | 0 | UINT64_C(0) |
384 | 0 | }; |
385 | 0 | const unsigned opcode = MI.getOpcode(); |
386 | 0 | uint64_t Value = InstBits[opcode]; |
387 | 0 | uint64_t op = 0; |
388 | 0 | (void)op; // suppress warning |
389 | 0 | switch (opcode) { |
390 | 0 | case Lanai::LOG0: |
391 | 0 | case Lanai::LOG1: |
392 | 0 | case Lanai::LOG2: |
393 | 0 | case Lanai::LOG3: |
394 | 0 | case Lanai::LOG4: |
395 | 0 | case Lanai::NOP: |
396 | 0 | case Lanai::RET: { |
397 | 0 | break; |
398 | 0 | } |
399 | 0 | case Lanai::BRR: { |
400 | | // op: DDDI |
401 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
402 | 0 | Value |= (op & UINT64_C(14)) << 24; |
403 | 0 | Value |= (op & UINT64_C(1)); |
404 | | // op: imm16 |
405 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
406 | 0 | op &= UINT64_C(65532); |
407 | 0 | Value |= op; |
408 | 0 | break; |
409 | 0 | } |
410 | 0 | case Lanai::LEADZ: |
411 | 0 | case Lanai::POPC: |
412 | 0 | case Lanai::TRAILZ: { |
413 | | // op: Rd |
414 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
415 | 0 | op &= UINT64_C(31); |
416 | 0 | op <<= 23; |
417 | 0 | Value |= op; |
418 | | // op: Rs1 |
419 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
420 | 0 | op &= UINT64_C(31); |
421 | 0 | op <<= 18; |
422 | 0 | Value |= op; |
423 | 0 | break; |
424 | 0 | } |
425 | 0 | case Lanai::ADDC_F_R: |
426 | 0 | case Lanai::ADDC_R: |
427 | 0 | case Lanai::ADD_F_R: |
428 | 0 | case Lanai::ADD_R: |
429 | 0 | case Lanai::AND_F_R: |
430 | 0 | case Lanai::AND_R: |
431 | 0 | case Lanai::OR_F_R: |
432 | 0 | case Lanai::OR_R: |
433 | 0 | case Lanai::SELECT: |
434 | 0 | case Lanai::SHL_F_R: |
435 | 0 | case Lanai::SHL_R: |
436 | 0 | case Lanai::SRA_F_R: |
437 | 0 | case Lanai::SRA_R: |
438 | 0 | case Lanai::SRL_F_R: |
439 | 0 | case Lanai::SRL_R: |
440 | 0 | case Lanai::SUBB_F_R: |
441 | 0 | case Lanai::SUBB_R: |
442 | 0 | case Lanai::SUB_F_R: |
443 | 0 | case Lanai::SUB_R: |
444 | 0 | case Lanai::XOR_F_R: |
445 | 0 | case Lanai::XOR_R: { |
446 | | // op: Rd |
447 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
448 | 0 | op &= UINT64_C(31); |
449 | 0 | op <<= 23; |
450 | 0 | Value |= op; |
451 | | // op: Rs1 |
452 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
453 | 0 | op &= UINT64_C(31); |
454 | 0 | op <<= 18; |
455 | 0 | Value |= op; |
456 | | // op: Rs2 |
457 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
458 | 0 | op &= UINT64_C(31); |
459 | 0 | op <<= 11; |
460 | 0 | Value |= op; |
461 | | // op: DDDI |
462 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
463 | 0 | Value |= (op & UINT64_C(1)) << 16; |
464 | 0 | Value |= (op & UINT64_C(14)) >> 1; |
465 | 0 | break; |
466 | 0 | } |
467 | 0 | case Lanai::ADDC_F_I_HI: |
468 | 0 | case Lanai::ADDC_F_I_LO: |
469 | 0 | case Lanai::ADDC_I_HI: |
470 | 0 | case Lanai::ADDC_I_LO: |
471 | 0 | case Lanai::ADD_F_I_HI: |
472 | 0 | case Lanai::ADD_F_I_LO: |
473 | 0 | case Lanai::ADD_I_HI: |
474 | 0 | case Lanai::ADD_I_LO: |
475 | 0 | case Lanai::AND_F_I_HI: |
476 | 0 | case Lanai::AND_F_I_LO: |
477 | 0 | case Lanai::AND_I_HI: |
478 | 0 | case Lanai::AND_I_LO: |
479 | 0 | case Lanai::OR_F_I_HI: |
480 | 0 | case Lanai::OR_F_I_LO: |
481 | 0 | case Lanai::OR_I_HI: |
482 | 0 | case Lanai::OR_I_LO: |
483 | 0 | case Lanai::SA_F_I: |
484 | 0 | case Lanai::SA_I: |
485 | 0 | case Lanai::SL_F_I: |
486 | 0 | case Lanai::SL_I: |
487 | 0 | case Lanai::SUBB_F_I_HI: |
488 | 0 | case Lanai::SUBB_F_I_LO: |
489 | 0 | case Lanai::SUBB_I_HI: |
490 | 0 | case Lanai::SUBB_I_LO: |
491 | 0 | case Lanai::SUB_F_I_HI: |
492 | 0 | case Lanai::SUB_F_I_LO: |
493 | 0 | case Lanai::SUB_I_HI: |
494 | 0 | case Lanai::SUB_I_LO: |
495 | 0 | case Lanai::XOR_F_I_HI: |
496 | 0 | case Lanai::XOR_F_I_LO: |
497 | 0 | case Lanai::XOR_I_HI: |
498 | 0 | case Lanai::XOR_I_LO: { |
499 | | // op: Rd |
500 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
501 | 0 | op &= UINT64_C(31); |
502 | 0 | op <<= 23; |
503 | 0 | Value |= op; |
504 | | // op: Rs1 |
505 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
506 | 0 | op &= UINT64_C(31); |
507 | 0 | op <<= 18; |
508 | 0 | Value |= op; |
509 | | // op: imm16 |
510 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
511 | 0 | op &= UINT64_C(65535); |
512 | 0 | Value |= op; |
513 | 0 | break; |
514 | 0 | } |
515 | 0 | case Lanai::STADDR: { |
516 | | // op: Rd |
517 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
518 | 0 | op &= UINT64_C(31); |
519 | 0 | op <<= 23; |
520 | 0 | Value |= op; |
521 | | // op: dst |
522 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
523 | 0 | Value |= (op & UINT64_C(2031616)) << 2; |
524 | 0 | Value |= (op & UINT64_C(65535)); |
525 | 0 | break; |
526 | 0 | } |
527 | 0 | case Lanai::SW_RI: { |
528 | | // op: Rd |
529 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
530 | 0 | op &= UINT64_C(31); |
531 | 0 | op <<= 23; |
532 | 0 | Value |= op; |
533 | | // op: dst |
534 | 0 | op = getRiMemoryOpValue(MI, 1, Fixups, STI); |
535 | 0 | op &= UINT64_C(8388607); |
536 | 0 | Value |= op; |
537 | 0 | Value = adjustPqBitsRmAndRrm(MI, Value, STI); |
538 | 0 | break; |
539 | 0 | } |
540 | 0 | case Lanai::STB_RR: |
541 | 0 | case Lanai::STH_RR: |
542 | 0 | case Lanai::SW_RR: { |
543 | | // op: Rd |
544 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
545 | 0 | op &= UINT64_C(31); |
546 | 0 | op <<= 23; |
547 | 0 | Value |= op; |
548 | | // op: dst |
549 | 0 | op = getRrMemoryOpValue(MI, 1, Fixups, STI); |
550 | 0 | Value |= (op & UINT64_C(1015808)) << 3; |
551 | 0 | Value |= (op & UINT64_C(768)) << 8; |
552 | 0 | Value |= (op & UINT64_C(31744)) << 1; |
553 | 0 | Value |= (op & UINT64_C(255)) << 3; |
554 | 0 | Value = adjustPqBitsRmAndRrm(MI, Value, STI); |
555 | 0 | break; |
556 | 0 | } |
557 | 0 | case Lanai::STB_RI: |
558 | 0 | case Lanai::STH_RI: { |
559 | | // op: Rd |
560 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
561 | 0 | op &= UINT64_C(31); |
562 | 0 | op <<= 23; |
563 | 0 | Value |= op; |
564 | | // op: dst |
565 | 0 | op = getSplsOpValue(MI, 1, Fixups, STI); |
566 | 0 | Value |= (op & UINT64_C(126976)) << 6; |
567 | 0 | Value |= (op & UINT64_C(4095)); |
568 | 0 | Value = adjustPqBitsSpls(MI, Value, STI); |
569 | 0 | break; |
570 | 0 | } |
571 | 0 | case Lanai::SLI: { |
572 | | // op: Rd |
573 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
574 | 0 | op &= UINT64_C(31); |
575 | 0 | op <<= 23; |
576 | 0 | Value |= op; |
577 | | // op: imm |
578 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
579 | 0 | Value |= (op & UINT64_C(2031616)) << 2; |
580 | 0 | Value |= (op & UINT64_C(65535)); |
581 | 0 | break; |
582 | 0 | } |
583 | 0 | case Lanai::MOVHI: { |
584 | | // op: Rd |
585 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
586 | 0 | op &= UINT64_C(31); |
587 | 0 | op <<= 23; |
588 | 0 | Value |= op; |
589 | | // op: imm16 |
590 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
591 | 0 | op &= UINT64_C(65535); |
592 | 0 | Value |= op; |
593 | 0 | break; |
594 | 0 | } |
595 | 0 | case Lanai::LDADDR: { |
596 | | // op: Rd |
597 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
598 | 0 | op &= UINT64_C(31); |
599 | 0 | op <<= 23; |
600 | 0 | Value |= op; |
601 | | // op: src |
602 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
603 | 0 | Value |= (op & UINT64_C(2031616)) << 2; |
604 | 0 | Value |= (op & UINT64_C(65535)); |
605 | 0 | break; |
606 | 0 | } |
607 | 0 | case Lanai::LDW_RI: { |
608 | | // op: Rd |
609 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
610 | 0 | op &= UINT64_C(31); |
611 | 0 | op <<= 23; |
612 | 0 | Value |= op; |
613 | | // op: src |
614 | 0 | op = getRiMemoryOpValue(MI, 1, Fixups, STI); |
615 | 0 | op &= UINT64_C(8388607); |
616 | 0 | Value |= op; |
617 | 0 | Value = adjustPqBitsRmAndRrm(MI, Value, STI); |
618 | 0 | break; |
619 | 0 | } |
620 | 0 | case Lanai::LDBs_RR: |
621 | 0 | case Lanai::LDBz_RR: |
622 | 0 | case Lanai::LDHs_RR: |
623 | 0 | case Lanai::LDHz_RR: |
624 | 0 | case Lanai::LDW_RR: |
625 | 0 | case Lanai::LDWz_RR: { |
626 | | // op: Rd |
627 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
628 | 0 | op &= UINT64_C(31); |
629 | 0 | op <<= 23; |
630 | 0 | Value |= op; |
631 | | // op: src |
632 | 0 | op = getRrMemoryOpValue(MI, 1, Fixups, STI); |
633 | 0 | Value |= (op & UINT64_C(1015808)) << 3; |
634 | 0 | Value |= (op & UINT64_C(768)) << 8; |
635 | 0 | Value |= (op & UINT64_C(31744)) << 1; |
636 | 0 | Value |= (op & UINT64_C(255)) << 3; |
637 | 0 | Value = adjustPqBitsRmAndRrm(MI, Value, STI); |
638 | 0 | break; |
639 | 0 | } |
640 | 0 | case Lanai::LDBs_RI: |
641 | 0 | case Lanai::LDBz_RI: |
642 | 0 | case Lanai::LDHs_RI: |
643 | 0 | case Lanai::LDHz_RI: { |
644 | | // op: Rd |
645 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
646 | 0 | op &= UINT64_C(31); |
647 | 0 | op <<= 23; |
648 | 0 | Value |= op; |
649 | | // op: src |
650 | 0 | op = getSplsOpValue(MI, 1, Fixups, STI); |
651 | 0 | Value |= (op & UINT64_C(126976)) << 6; |
652 | 0 | Value |= (op & UINT64_C(4095)); |
653 | 0 | Value = adjustPqBitsSpls(MI, Value, STI); |
654 | 0 | break; |
655 | 0 | } |
656 | 0 | case Lanai::BRIND_CC: { |
657 | | // op: Rs1 |
658 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
659 | 0 | op &= UINT64_C(31); |
660 | 0 | op <<= 18; |
661 | 0 | Value |= op; |
662 | | // op: DDDI |
663 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
664 | 0 | Value |= (op & UINT64_C(1)) << 16; |
665 | 0 | Value |= (op & UINT64_C(14)) >> 1; |
666 | 0 | break; |
667 | 0 | } |
668 | 0 | case Lanai::SCC: { |
669 | | // op: Rs1 |
670 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
671 | 0 | op &= UINT64_C(31); |
672 | 0 | op <<= 18; |
673 | 0 | Value |= op; |
674 | | // op: DDDI |
675 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
676 | 0 | Value |= (op & UINT64_C(14)) << 24; |
677 | 0 | Value |= (op & UINT64_C(1)); |
678 | 0 | break; |
679 | 0 | } |
680 | 0 | case Lanai::SFSUB_F_RR: { |
681 | | // op: Rs1 |
682 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
683 | 0 | op &= UINT64_C(31); |
684 | 0 | op <<= 18; |
685 | 0 | Value |= op; |
686 | | // op: Rs2 |
687 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
688 | 0 | op &= UINT64_C(31); |
689 | 0 | op <<= 11; |
690 | 0 | Value |= op; |
691 | 0 | break; |
692 | 0 | } |
693 | 0 | case Lanai::BRIND_CCA: { |
694 | | // op: Rs1 |
695 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
696 | 0 | op &= UINT64_C(31); |
697 | 0 | op <<= 18; |
698 | 0 | Value |= op; |
699 | | // op: Rs2 |
700 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
701 | 0 | op &= UINT64_C(31); |
702 | 0 | op <<= 11; |
703 | 0 | Value |= op; |
704 | | // op: DDDI |
705 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
706 | 0 | Value |= (op & UINT64_C(1)) << 16; |
707 | 0 | Value |= (op & UINT64_C(14)) >> 1; |
708 | 0 | break; |
709 | 0 | } |
710 | 0 | case Lanai::SFSUB_F_RI_HI: |
711 | 0 | case Lanai::SFSUB_F_RI_LO: { |
712 | | // op: Rs1 |
713 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
714 | 0 | op &= UINT64_C(31); |
715 | 0 | op <<= 18; |
716 | 0 | Value |= op; |
717 | | // op: imm16 |
718 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
719 | 0 | op &= UINT64_C(65535); |
720 | 0 | Value |= op; |
721 | 0 | break; |
722 | 0 | } |
723 | 0 | case Lanai::JR: { |
724 | | // op: Rs2 |
725 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
726 | 0 | op &= UINT64_C(31); |
727 | 0 | op <<= 11; |
728 | 0 | Value |= op; |
729 | 0 | break; |
730 | 0 | } |
731 | 0 | case Lanai::BT: { |
732 | | // op: addr |
733 | 0 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
734 | 0 | op &= UINT64_C(33554428); |
735 | 0 | Value |= op; |
736 | 0 | break; |
737 | 0 | } |
738 | 0 | case Lanai::BRCC: { |
739 | | // op: addr |
740 | 0 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
741 | 0 | op &= UINT64_C(33554428); |
742 | 0 | Value |= op; |
743 | | // op: DDDI |
744 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
745 | 0 | Value |= (op & UINT64_C(14)) << 24; |
746 | 0 | Value |= (op & UINT64_C(1)); |
747 | 0 | break; |
748 | 0 | } |
749 | 0 | default: |
750 | 0 | std::string msg; |
751 | 0 | raw_string_ostream Msg(msg); |
752 | 0 | Msg << "Not supported instr: " << MI; |
753 | 0 | report_fatal_error(Msg.str().c_str()); |
754 | 0 | } |
755 | 0 | return Value; |
756 | 0 | } |
757 | | |
758 | | #ifdef GET_OPERAND_BIT_OFFSET |
759 | | #undef GET_OPERAND_BIT_OFFSET |
760 | | |
761 | | uint32_t LanaiMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
762 | | unsigned OpNum, |
763 | | const MCSubtargetInfo &STI) const { |
764 | | switch (MI.getOpcode()) { |
765 | | case Lanai::LOG0: |
766 | | case Lanai::LOG1: |
767 | | case Lanai::LOG2: |
768 | | case Lanai::LOG3: |
769 | | case Lanai::LOG4: |
770 | | case Lanai::NOP: |
771 | | case Lanai::RET: { |
772 | | break; |
773 | | } |
774 | | case Lanai::ADDC_F_R: |
775 | | case Lanai::ADDC_R: |
776 | | case Lanai::ADD_F_R: |
777 | | case Lanai::ADD_R: |
778 | | case Lanai::AND_F_R: |
779 | | case Lanai::AND_R: |
780 | | case Lanai::OR_F_R: |
781 | | case Lanai::OR_R: |
782 | | case Lanai::SELECT: |
783 | | case Lanai::SHL_F_R: |
784 | | case Lanai::SHL_R: |
785 | | case Lanai::SRA_F_R: |
786 | | case Lanai::SRA_R: |
787 | | case Lanai::SRL_F_R: |
788 | | case Lanai::SRL_R: |
789 | | case Lanai::SUBB_F_R: |
790 | | case Lanai::SUBB_R: |
791 | | case Lanai::SUB_F_R: |
792 | | case Lanai::SUB_R: |
793 | | case Lanai::XOR_F_R: |
794 | | case Lanai::XOR_R: { |
795 | | switch (OpNum) { |
796 | | case 0: |
797 | | // op: Rd |
798 | | return 23; |
799 | | case 1: |
800 | | // op: Rs1 |
801 | | return 18; |
802 | | case 2: |
803 | | // op: Rs2 |
804 | | return 11; |
805 | | case 3: |
806 | | // op: DDDI |
807 | | return 0; |
808 | | } |
809 | | break; |
810 | | } |
811 | | case Lanai::ADDC_F_I_HI: |
812 | | case Lanai::ADDC_F_I_LO: |
813 | | case Lanai::ADDC_I_HI: |
814 | | case Lanai::ADDC_I_LO: |
815 | | case Lanai::ADD_F_I_HI: |
816 | | case Lanai::ADD_F_I_LO: |
817 | | case Lanai::ADD_I_HI: |
818 | | case Lanai::ADD_I_LO: |
819 | | case Lanai::AND_F_I_HI: |
820 | | case Lanai::AND_F_I_LO: |
821 | | case Lanai::AND_I_HI: |
822 | | case Lanai::AND_I_LO: |
823 | | case Lanai::OR_F_I_HI: |
824 | | case Lanai::OR_F_I_LO: |
825 | | case Lanai::OR_I_HI: |
826 | | case Lanai::OR_I_LO: |
827 | | case Lanai::SA_F_I: |
828 | | case Lanai::SA_I: |
829 | | case Lanai::SL_F_I: |
830 | | case Lanai::SL_I: |
831 | | case Lanai::SUBB_F_I_HI: |
832 | | case Lanai::SUBB_F_I_LO: |
833 | | case Lanai::SUBB_I_HI: |
834 | | case Lanai::SUBB_I_LO: |
835 | | case Lanai::SUB_F_I_HI: |
836 | | case Lanai::SUB_F_I_LO: |
837 | | case Lanai::SUB_I_HI: |
838 | | case Lanai::SUB_I_LO: |
839 | | case Lanai::XOR_F_I_HI: |
840 | | case Lanai::XOR_F_I_LO: |
841 | | case Lanai::XOR_I_HI: |
842 | | case Lanai::XOR_I_LO: { |
843 | | switch (OpNum) { |
844 | | case 0: |
845 | | // op: Rd |
846 | | return 23; |
847 | | case 1: |
848 | | // op: Rs1 |
849 | | return 18; |
850 | | case 2: |
851 | | // op: imm16 |
852 | | return 0; |
853 | | } |
854 | | break; |
855 | | } |
856 | | case Lanai::LEADZ: |
857 | | case Lanai::POPC: |
858 | | case Lanai::TRAILZ: { |
859 | | switch (OpNum) { |
860 | | case 0: |
861 | | // op: Rd |
862 | | return 23; |
863 | | case 1: |
864 | | // op: Rs1 |
865 | | return 18; |
866 | | } |
867 | | break; |
868 | | } |
869 | | case Lanai::STADDR: |
870 | | case Lanai::STB_RI: |
871 | | case Lanai::STH_RI: |
872 | | case Lanai::SW_RI: { |
873 | | switch (OpNum) { |
874 | | case 0: |
875 | | // op: Rd |
876 | | return 23; |
877 | | case 1: |
878 | | // op: dst |
879 | | return 0; |
880 | | } |
881 | | break; |
882 | | } |
883 | | case Lanai::STB_RR: |
884 | | case Lanai::STH_RR: |
885 | | case Lanai::SW_RR: { |
886 | | switch (OpNum) { |
887 | | case 0: |
888 | | // op: Rd |
889 | | return 23; |
890 | | case 1: |
891 | | // op: dst |
892 | | return 3; |
893 | | } |
894 | | break; |
895 | | } |
896 | | case Lanai::SLI: { |
897 | | switch (OpNum) { |
898 | | case 0: |
899 | | // op: Rd |
900 | | return 23; |
901 | | case 1: |
902 | | // op: imm |
903 | | return 0; |
904 | | } |
905 | | break; |
906 | | } |
907 | | case Lanai::MOVHI: { |
908 | | switch (OpNum) { |
909 | | case 0: |
910 | | // op: Rd |
911 | | return 23; |
912 | | case 1: |
913 | | // op: imm16 |
914 | | return 0; |
915 | | } |
916 | | break; |
917 | | } |
918 | | case Lanai::LDADDR: |
919 | | case Lanai::LDBs_RI: |
920 | | case Lanai::LDBz_RI: |
921 | | case Lanai::LDHs_RI: |
922 | | case Lanai::LDHz_RI: |
923 | | case Lanai::LDW_RI: { |
924 | | switch (OpNum) { |
925 | | case 0: |
926 | | // op: Rd |
927 | | return 23; |
928 | | case 1: |
929 | | // op: src |
930 | | return 0; |
931 | | } |
932 | | break; |
933 | | } |
934 | | case Lanai::LDBs_RR: |
935 | | case Lanai::LDBz_RR: |
936 | | case Lanai::LDHs_RR: |
937 | | case Lanai::LDHz_RR: |
938 | | case Lanai::LDW_RR: |
939 | | case Lanai::LDWz_RR: { |
940 | | switch (OpNum) { |
941 | | case 0: |
942 | | // op: Rd |
943 | | return 23; |
944 | | case 1: |
945 | | // op: src |
946 | | return 3; |
947 | | } |
948 | | break; |
949 | | } |
950 | | case Lanai::BRIND_CC: |
951 | | case Lanai::SCC: { |
952 | | switch (OpNum) { |
953 | | case 0: |
954 | | // op: Rs1 |
955 | | return 18; |
956 | | case 1: |
957 | | // op: DDDI |
958 | | return 0; |
959 | | } |
960 | | break; |
961 | | } |
962 | | case Lanai::BRIND_CCA: { |
963 | | switch (OpNum) { |
964 | | case 0: |
965 | | // op: Rs1 |
966 | | return 18; |
967 | | case 1: |
968 | | // op: Rs2 |
969 | | return 11; |
970 | | case 2: |
971 | | // op: DDDI |
972 | | return 0; |
973 | | } |
974 | | break; |
975 | | } |
976 | | case Lanai::SFSUB_F_RR: { |
977 | | switch (OpNum) { |
978 | | case 0: |
979 | | // op: Rs1 |
980 | | return 18; |
981 | | case 1: |
982 | | // op: Rs2 |
983 | | return 11; |
984 | | } |
985 | | break; |
986 | | } |
987 | | case Lanai::SFSUB_F_RI_HI: |
988 | | case Lanai::SFSUB_F_RI_LO: { |
989 | | switch (OpNum) { |
990 | | case 0: |
991 | | // op: Rs1 |
992 | | return 18; |
993 | | case 1: |
994 | | // op: imm16 |
995 | | return 0; |
996 | | } |
997 | | break; |
998 | | } |
999 | | case Lanai::JR: { |
1000 | | switch (OpNum) { |
1001 | | case 0: |
1002 | | // op: Rs2 |
1003 | | return 11; |
1004 | | } |
1005 | | break; |
1006 | | } |
1007 | | case Lanai::BRCC: { |
1008 | | switch (OpNum) { |
1009 | | case 0: |
1010 | | // op: addr |
1011 | | return 2; |
1012 | | case 1: |
1013 | | // op: DDDI |
1014 | | return 0; |
1015 | | } |
1016 | | break; |
1017 | | } |
1018 | | case Lanai::BT: { |
1019 | | switch (OpNum) { |
1020 | | case 0: |
1021 | | // op: addr |
1022 | | return 2; |
1023 | | } |
1024 | | break; |
1025 | | } |
1026 | | case Lanai::BRR: { |
1027 | | switch (OpNum) { |
1028 | | case 1: |
1029 | | // op: DDDI |
1030 | | return 0; |
1031 | | case 0: |
1032 | | // op: imm16 |
1033 | | return 2; |
1034 | | } |
1035 | | break; |
1036 | | } |
1037 | | } |
1038 | | std::string msg; |
1039 | | raw_string_ostream Msg(msg); |
1040 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
1041 | | report_fatal_error(Msg.str().c_str()); |
1042 | | } |
1043 | | |
1044 | | #endif // GET_OPERAND_BIT_OFFSET |
1045 | | |