/src/build/lib/Target/Lanai/LanaiGenSubtargetInfo.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Subtarget Enumeration Source Fragment                                      *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM

namespace llvm {
} // end namespace llvm

#endif // GET_SUBTARGETINFO_ENUM


#ifdef GET_SUBTARGETINFO_MACRO
#undef GET_SUBTARGETINFO_MACRO
#endif // GET_SUBTARGETINFO_MACRO


#ifdef GET_SUBTARGETINFO_MC_DESC
#undef GET_SUBTARGETINFO_MC_DESC

namespace llvm {

#ifdef DBGFIELD
#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
#endif
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
#define DBGFIELD(x) x,
#else
#define DBGFIELD(x)
#endif

// Functional units for "LanaiItinerary"
namespace LanaiItineraryFU {
  const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
  const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
} // end namespace LanaiItineraryFU

extern const llvm::InstrStage LanaiStages[] = {
  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
  { 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
  { 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
  { 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
  { 0, 0, 0, llvm::InstrStage::Required } // End stages
};
extern const unsigned LanaiOperandCycles[] = {
  0, // No itinerary
  0 // End operand cycles
};
extern const unsigned LanaiForwardingPaths[] = {
 0, // No itinerary
 0 // End bypass tables
};

static const llvm::InstrItinerary LanaiItinerary[] = {
  { 0, 0, 0, 0, 0 }, // 0 NoInstrModel
  { 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
  { 1, 1, 2, 0, 0 }, // 2 IIC_ALU
  { 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
  { 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
  { 0, 0, 0, 0, 0 }, // 5 WriteLD
  { 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
  { 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
  { 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
};

// ===============================================================
// Data tables for the new per-operand machine model.

// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
  { 0,  0,  0 }, // Invalid
  { 1,  1,   0}, // #1
  { 2,  1,   0} // #2
}; // LanaiWriteProcResTable

// {Cycles, WriteResourceID}
extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
  { 0,  0}, // Invalid
  { 1,  0}, // #1 WriteALU
  { 2,  0}, // #2 WriteLD_WriteLDSW_WriteST
  { 4,  0} // #3 WriteSTSW
}; // LanaiWriteLatencyTable

// {UseIdx, WriteResourceID, Cycles}
extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
  {0,  0,  0}, // Invalid
}; // LanaiReadAdvanceTable

// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
  {DBGFIELD("InvalidSchedClass")  8191, false, false, false, 0, 0,  0, 0,  0, 0},
  {DBGFIELD("IIC_ALU_WriteALU")   1, false, false, false,  1, 1,  1, 1,  0, 0}, // #1
  {DBGFIELD("IIC_ALU")            8191, false, false, false,  0, 0,  0, 0,  0, 0}, // #2
  {DBGFIELD("IIC_LD_WriteLD")     1, false, false, false,  2, 1,  2, 1,  0, 0}, // #3
  {DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false, false,  2, 1,  2, 1,  0, 0}, // #4
  {DBGFIELD("WriteLD")            1, false, false, false,  2, 1,  2, 1,  0, 0}, // #5
  {DBGFIELD("IIC_ST_WriteST")     1, false, false, false,  2, 1,  2, 1,  0, 0}, // #6
  {DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false, false,  2, 1,  3, 1,  0, 0}, // #7
}; // LanaiSchedModelSchedClasses

#undef DBGFIELD

static const llvm::MCSchedModel NoSchedModel = {
  MCSchedModel::DefaultIssueWidth,
  MCSchedModel::DefaultMicroOpBufferSize,
  MCSchedModel::DefaultLoopMicroOpBufferSize,
  MCSchedModel::DefaultLoadLatency,
  MCSchedModel::DefaultHighLatency,
  MCSchedModel::DefaultMispredictPenalty,
  false, // PostRAScheduler
  false, // CompleteModel
  false, // EnableIntervals
  0, // Processor ID
  nullptr, nullptr, 0, 0, // No instruction-level machine model.
  nullptr, // No Itinerary
  nullptr // No extra processor descriptor
};

static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
  0,  // Invalid
};

// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
  {"InvalidUnit", 0, 0, 0, 0},
  {"ALU",             1, 0, 0, nullptr}, // #1
  {"LdSt",            1, 0, 0, nullptr}, // #2
};

static const llvm::MCSchedModel LanaiSchedModel = {
  1, // IssueWidth
  0, // MicroOpBufferSize
  0, // LoopMicroOpBufferSize
  2, // LoadLatency
  MCSchedModel::DefaultHighLatency,
  10, // MispredictPenalty
  false, // PostRAScheduler
  false, // CompleteModel
  false, // EnableIntervals
  1, // Processor ID
  LanaiSchedModelProcResources,
  LanaiSchedModelSchedClasses,
  3,
  8,
  LanaiItinerary,
  nullptr // No extra processor descriptor
};

// Sorted (by key) array of values for CPU subtype.
extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
 { "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
 { "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
};

namespace Lanai_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {
  // Don't know how to resolve this scheduling class.
  return 0;
}
} // end namespace Lanai_MC

struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
  LanaiGenMCSubtargetInfo(const Triple &TT,
    StringRef CPU, StringRef TuneCPU, StringRef FS,
    ArrayRef<SubtargetFeatureKV> PF,
    ArrayRef<SubtargetSubTypeKV> PD,
    const MCWriteProcResEntry *WPR,
    const MCWriteLatencyEntry *WL,
    const MCReadAdvanceEntry *RA, const InstrStage *IS,
    const unsigned *OC, const unsigned *FP) :
      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
                      WPR, WL, RA, IS, OC, FP) { }

  unsigned resolveVariantSchedClass(unsigned SchedClass,
      const MCInst *MI, const MCInstrInfo *MCII,
      unsigned CPUID) const override {
    return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
  }
};

static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
  return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, LanaiSubTypeKV, 
                      LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
                      LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
}

} // end namespace llvm

#endif // GET_SUBTARGETINFO_MC_DESC


#ifdef GET_SUBTARGETINFO_TARGET_DESC
#undef GET_SUBTARGETINFO_TARGET_DESC

#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

// ParseSubtargetFeatures - Parses features string setting specified
// subtarget options.
void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
  LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
}
#endif // GET_SUBTARGETINFO_TARGET_DESC


#ifdef GET_SUBTARGETINFO_HEADER
#undef GET_SUBTARGETINFO_HEADER

namespace llvm {
class DFAPacketizer;
namespace Lanai_MC {
unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);
} // end namespace Lanai_MC

struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
  explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
public:
  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;
  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;
  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;
};
} // end namespace llvm

#endif // GET_SUBTARGETINFO_HEADER


#ifdef GET_SUBTARGETINFO_CTOR
#undef GET_SUBTARGETINFO_CTOR

#include "llvm/CodeGen/TargetSchedule.h"

namespace llvm {
extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
extern const llvm::InstrStage LanaiStages[];
extern const unsigned LanaiOperandCycles[];
extern const unsigned LanaiForwardingPaths[];
LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
  : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, ArrayRef(LanaiSubTypeKV, 2), 
                        LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable, 
                        LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}

unsigned LanaiGenSubtargetInfo
::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {
  report_fatal_error("Expected a variant SchedClass");
} // LanaiGenSubtargetInfo::resolveSchedClass

unsigned LanaiGenSubtargetInfo
::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {
  return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
} // LanaiGenSubtargetInfo::resolveVariantSchedClass

} // end namespace llvm

#endif // GET_SUBTARGETINFO_CTOR


#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS

#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS


#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS

#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS


Coverage Report

Created: 2024-01-17 10:31

Line	Count	Source (jump to first uncovered line)
1		/===- TableGen'erated file -------------------------------------- C++ --===\
2		\|* *\|
3		\|* Subtarget Enumeration Source Fragment *\|
4		\|* *\|
5		\|* Automatically generated file, do not edit! *\|
6		\|* *\|
7		\===----------------------------------------------------------------------===/
8
9
10		#ifdef GET_SUBTARGETINFO_ENUM
11		#undef GET_SUBTARGETINFO_ENUM
12
13		namespace llvm {
14		} // end namespace llvm
15
16		#endif // GET_SUBTARGETINFO_ENUM
17
18
19		#ifdef GET_SUBTARGETINFO_MACRO
20		#undef GET_SUBTARGETINFO_MACRO
21		#endif // GET_SUBTARGETINFO_MACRO
22
23
24		#ifdef GET_SUBTARGETINFO_MC_DESC
25		#undef GET_SUBTARGETINFO_MC_DESC
26
27		namespace llvm {
28
29		#ifdef DBGFIELD
30		#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"
31		#endif
32		#if !defined(NDEBUG) \|\| defined(LLVM_ENABLE_DUMP)
33		#define DBGFIELD(x) x,
34		#else
35		#define DBGFIELD(x)
36		#endif
37
38		// Functional units for "LanaiItinerary"
39		namespace LanaiItineraryFU {
40		const InstrStage::FuncUnits ALU_FU = 1ULL << 0;
41		const InstrStage::FuncUnits LDST_FU = 1ULL << 1;
42		} // end namespace LanaiItineraryFU
43
44		extern const llvm::InstrStage LanaiStages[] = {
45		{ 0, 0, 0, llvm::InstrStage::Required }, // No itinerary
46		{ 1, LanaiItineraryFU::ALU_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 1
47		{ 1, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 2
48		{ 2, LanaiItineraryFU::LDST_FU, -1, (llvm::InstrStage::ReservationKinds)0 }, // 3
49		{ 0, 0, 0, llvm::InstrStage::Required } // End stages
50		};
51		extern const unsigned LanaiOperandCycles[] = {
52		0, // No itinerary
53		0 // End operand cycles
54		};
55		extern const unsigned LanaiForwardingPaths[] = {
56		0, // No itinerary
57		0 // End bypass tables
58		};
59
60		static const llvm::InstrItinerary LanaiItinerary[] = {
61		{ 0, 0, 0, 0, 0 }, // 0 NoInstrModel
62		{ 1, 1, 2, 0, 0 }, // 1 IIC_ALU_WriteALU
63		{ 1, 1, 2, 0, 0 }, // 2 IIC_ALU
64		{ 1, 2, 3, 0, 0 }, // 3 IIC_LD_WriteLD
65		{ 1, 3, 4, 0, 0 }, // 4 IIC_LDSW_WriteLDSW
66		{ 0, 0, 0, 0, 0 }, // 5 WriteLD
67		{ 1, 2, 3, 0, 0 }, // 6 IIC_ST_WriteST
68		{ 1, 3, 4, 0, 0 }, // 7 IIC_STSW_WriteSTSW
69		{ 0, uint16_t(~0U), uint16_t(~0U), uint16_t(~0U), uint16_t(~0U) }// end marker
70		};
71
72		// ===============================================================
73		// Data tables for the new per-operand machine model.
74
75		// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}
76		extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[] = {
77		{ 0, 0, 0 }, // Invalid
78		{ 1, 1, 0}, // #1
79		{ 2, 1, 0} // #2
80		}; // LanaiWriteProcResTable
81
82		// {Cycles, WriteResourceID}
83		extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[] = {
84		{ 0, 0}, // Invalid
85		{ 1, 0}, // #1 WriteALU
86		{ 2, 0}, // #2 WriteLD_WriteLDSW_WriteST
87		{ 4, 0} // #3 WriteSTSW
88		}; // LanaiWriteLatencyTable
89
90		// {UseIdx, WriteResourceID, Cycles}
91		extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[] = {
92		{0, 0, 0}, // Invalid
93		}; // LanaiReadAdvanceTable
94
95		// {Name, NumMicroOps, BeginGroup, EndGroup, RetireOOO, WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}
96		static const llvm::MCSchedClassDesc LanaiSchedModelSchedClasses[] = {
97		{DBGFIELD("InvalidSchedClass") 8191, false, false, false, 0, 0, 0, 0, 0, 0},
98		{DBGFIELD("IIC_ALU_WriteALU") 1, false, false, false, 1, 1, 1, 1, 0, 0}, // #1
99		{DBGFIELD("IIC_ALU") 8191, false, false, false, 0, 0, 0, 0, 0, 0}, // #2
100		{DBGFIELD("IIC_LD_WriteLD") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #3
101		{DBGFIELD("IIC_LDSW_WriteLDSW") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #4
102		{DBGFIELD("WriteLD") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #5
103		{DBGFIELD("IIC_ST_WriteST") 1, false, false, false, 2, 1, 2, 1, 0, 0}, // #6
104		{DBGFIELD("IIC_STSW_WriteSTSW") 1, false, false, false, 2, 1, 3, 1, 0, 0}, // #7
105		}; // LanaiSchedModelSchedClasses
106
107		#undef DBGFIELD
108
109		static const llvm::MCSchedModel NoSchedModel = {
110		MCSchedModel::DefaultIssueWidth,
111		MCSchedModel::DefaultMicroOpBufferSize,
112		MCSchedModel::DefaultLoopMicroOpBufferSize,
113		MCSchedModel::DefaultLoadLatency,
114		MCSchedModel::DefaultHighLatency,
115		MCSchedModel::DefaultMispredictPenalty,
116		false, // PostRAScheduler
117		false, // CompleteModel
118		false, // EnableIntervals
119		0, // Processor ID
120		nullptr, nullptr, 0, 0, // No instruction-level machine model.
121		nullptr, // No Itinerary
122		nullptr // No extra processor descriptor
123		};
124
125		static const unsigned LanaiSchedModelProcResourceSubUnits[] = {
126		0, // Invalid
127		};
128
129		// {Name, NumUnits, SuperIdx, BufferSize, SubUnitsIdxBegin}
130		static const llvm::MCProcResourceDesc LanaiSchedModelProcResources[] = {
131		{"InvalidUnit", 0, 0, 0, 0},
132		{"ALU", 1, 0, 0, nullptr}, // #1
133		{"LdSt", 1, 0, 0, nullptr}, // #2
134		};
135
136		static const llvm::MCSchedModel LanaiSchedModel = {
137		1, // IssueWidth
138		0, // MicroOpBufferSize
139		0, // LoopMicroOpBufferSize
140		2, // LoadLatency
141		MCSchedModel::DefaultHighLatency,
142		10, // MispredictPenalty
143		false, // PostRAScheduler
144		false, // CompleteModel
145		false, // EnableIntervals
146		1, // Processor ID
147		LanaiSchedModelProcResources,
148		LanaiSchedModelSchedClasses,
149		3,
150		8,
151		LanaiItinerary,
152		nullptr // No extra processor descriptor
153		};
154
155		// Sorted (by key) array of values for CPU subtype.
156		extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[] = {
157		{ "generic", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
158		{ "v11", { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &LanaiSchedModel },
159		};
160
161		namespace Lanai_MC {
162		unsigned resolveVariantSchedClassImpl(unsigned SchedClass,
163	0	const MCInst MI, const MCInstrInfo MCII, unsigned CPUID) {
164		// Don't know how to resolve this scheduling class.
165	0	return 0;
166	0	}
167		} // end namespace Lanai_MC
168
169		struct LanaiGenMCSubtargetInfo : public MCSubtargetInfo {
170		LanaiGenMCSubtargetInfo(const Triple &TT,
171		StringRef CPU, StringRef TuneCPU, StringRef FS,
172		ArrayRef<SubtargetFeatureKV> PF,
173		ArrayRef<SubtargetSubTypeKV> PD,
174		const MCWriteProcResEntry *WPR,
175		const MCWriteLatencyEntry *WL,
176		const MCReadAdvanceEntry RA, const InstrStage IS,
177		const unsigned OC, const unsigned FP) :
178		MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,
179	0	WPR, WL, RA, IS, OC, FP) { }
180
181		unsigned resolveVariantSchedClass(unsigned SchedClass,
182		const MCInst MI, const MCInstrInfo MCII,
183	0	unsigned CPUID) const override {
184	0	return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
185	0	}
186		};
187
188	0	static inline MCSubtargetInfo *createLanaiMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {
189	0	return new LanaiGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, LanaiSubTypeKV,
190	0	LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
191	0	LanaiStages, LanaiOperandCycles, LanaiForwardingPaths);
192	0	}
193
194		} // end namespace llvm
195
196		#endif // GET_SUBTARGETINFO_MC_DESC
197
198
199		#ifdef GET_SUBTARGETINFO_TARGET_DESC
200		#undef GET_SUBTARGETINFO_TARGET_DESC
201
202		#include "llvm/Support/Debug.h"
203		#include "llvm/Support/raw_ostream.h"
204
205		// ParseSubtargetFeatures - Parses features string setting specified
206		// subtarget options.
207	0	void llvm::LanaiSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {
208	0	LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);
209	0	LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);
210	0	LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");
211	0	}
212		#endif // GET_SUBTARGETINFO_TARGET_DESC
213
214
215		#ifdef GET_SUBTARGETINFO_HEADER
216		#undef GET_SUBTARGETINFO_HEADER
217
218		namespace llvm {
219		class DFAPacketizer;
220		namespace Lanai_MC {
221		unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst MI, const MCInstrInfo MCII, unsigned CPUID);
222		} // end namespace Lanai_MC
223
224		struct LanaiGenSubtargetInfo : public TargetSubtargetInfo {
225		explicit LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);
226		public:
227		unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr DefMI, const TargetSchedModel SchedModel) const override;
228		unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst MI, const MCInstrInfo MCII, unsigned CPUID) const override;
229		DFAPacketizer createDFAPacketizer(const InstrItineraryData IID) const;
230		};
231		} // end namespace llvm
232
233		#endif // GET_SUBTARGETINFO_HEADER
234
235
236		#ifdef GET_SUBTARGETINFO_CTOR
237		#undef GET_SUBTARGETINFO_CTOR
238
239		#include "llvm/CodeGen/TargetSchedule.h"
240
241		namespace llvm {
242		extern const llvm::SubtargetFeatureKV LanaiFeatureKV[];
243		extern const llvm::SubtargetSubTypeKV LanaiSubTypeKV[];
244		extern const llvm::MCWriteProcResEntry LanaiWriteProcResTable[];
245		extern const llvm::MCWriteLatencyEntry LanaiWriteLatencyTable[];
246		extern const llvm::MCReadAdvanceEntry LanaiReadAdvanceTable[];
247		extern const llvm::InstrStage LanaiStages[];
248		extern const unsigned LanaiOperandCycles[];
249		extern const unsigned LanaiForwardingPaths[];
250		LanaiGenSubtargetInfo::LanaiGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)
251		: TargetSubtargetInfo(TT, CPU, TuneCPU, FS, std::nullopt, ArrayRef(LanaiSubTypeKV, 2),
252		LanaiWriteProcResTable, LanaiWriteLatencyTable, LanaiReadAdvanceTable,
253	0	LanaiStages, LanaiOperandCycles, LanaiForwardingPaths) {}
254
255		unsigned LanaiGenSubtargetInfo
256	0	::resolveSchedClass(unsigned SchedClass, const MachineInstr MI, const TargetSchedModel SchedModel) const {
257	0	report_fatal_error("Expected a variant SchedClass");
258	0	} // LanaiGenSubtargetInfo::resolveSchedClass
259
260		unsigned LanaiGenSubtargetInfo
261	0	::resolveVariantSchedClass(unsigned SchedClass, const MCInst MI, const MCInstrInfo MCII, unsigned CPUID) const {
262	0	return Lanai_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);
263	0	} // LanaiGenSubtargetInfo::resolveVariantSchedClass
264
265		} // end namespace llvm
266
267		#endif // GET_SUBTARGETINFO_CTOR
268
269
270		#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
271		#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
272
273		#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS
274
275
276		#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
277		#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
278
279		#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS
280