Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/LoongArch/LoongArchGenInstrInfo.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace LoongArch {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
56
    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
95
    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
97
    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
124
    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
131
    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
133
    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
136
    G_FCONSTANT = 121,
137
    G_VASTART = 122,
138
    G_VAARG = 123,
139
    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
141
    G_ZEXT  = 126,
142
    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
147
    G_ROTR  = 132,
148
    G_ROTL  = 133,
149
    G_ICMP  = 134,
150
    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
153
    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
170
    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
173
    G_UMULFIXSAT  = 158,
174
    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
176
    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
179
    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
186
    G_FPOWI = 171,
187
    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
190
    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
193
    G_FLDEXP  = 178,
194
    G_FFREXP  = 179,
195
    G_FNEG  = 180,
196
    G_FPEXT = 181,
197
    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
204
    G_IS_FPCLASS  = 189,
205
    G_FCANONICALIZE = 190,
206
    G_FMINNUM = 191,
207
    G_FMAXNUM = 192,
208
    G_FMINNUM_IEEE  = 193,
209
    G_FMAXNUM_IEEE  = 194,
210
    G_FMINIMUM  = 195,
211
    G_FMAXIMUM  = 196,
212
    G_GET_FPENV = 197,
213
    G_SET_FPENV = 198,
214
    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
216
    G_SET_FPMODE  = 201,
217
    G_RESET_FPMODE  = 202,
218
    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
221
    G_SMAX  = 206,
222
    G_UMIN  = 207,
223
    G_UMAX  = 208,
224
    G_ABS = 209,
225
    G_LROUND  = 210,
226
    G_LLROUND = 211,
227
    G_BR  = 212,
228
    G_BRJT  = 213,
229
    G_INSERT_VECTOR_ELT = 214,
230
    G_EXTRACT_VECTOR_ELT  = 215,
231
    G_SHUFFLE_VECTOR  = 216,
232
    G_CTTZ  = 217,
233
    G_CTTZ_ZERO_UNDEF = 218,
234
    G_CTLZ  = 219,
235
    G_CTLZ_ZERO_UNDEF = 220,
236
    G_CTPOP = 221,
237
    G_BSWAP = 222,
238
    G_BITREVERSE  = 223,
239
    G_FCEIL = 224,
240
    G_FCOS  = 225,
241
    G_FSIN  = 226,
242
    G_FSQRT = 227,
243
    G_FFLOOR  = 228,
244
    G_FRINT = 229,
245
    G_FNEARBYINT  = 230,
246
    G_ADDRSPACE_CAST  = 231,
247
    G_BLOCK_ADDR  = 232,
248
    G_JUMP_TABLE  = 233,
249
    G_DYN_STACKALLOC  = 234,
250
    G_STACKSAVE = 235,
251
    G_STACKRESTORE  = 236,
252
    G_STRICT_FADD = 237,
253
    G_STRICT_FSUB = 238,
254
    G_STRICT_FMUL = 239,
255
    G_STRICT_FDIV = 240,
256
    G_STRICT_FREM = 241,
257
    G_STRICT_FMA  = 242,
258
    G_STRICT_FSQRT  = 243,
259
    G_STRICT_FLDEXP = 244,
260
    G_READ_REGISTER = 245,
261
    G_WRITE_REGISTER  = 246,
262
    G_MEMCPY  = 247,
263
    G_MEMCPY_INLINE = 248,
264
    G_MEMMOVE = 249,
265
    G_MEMSET  = 250,
266
    G_BZERO = 251,
267
    G_VECREDUCE_SEQ_FADD  = 252,
268
    G_VECREDUCE_SEQ_FMUL  = 253,
269
    G_VECREDUCE_FADD  = 254,
270
    G_VECREDUCE_FMUL  = 255,
271
    G_VECREDUCE_FMAX  = 256,
272
    G_VECREDUCE_FMIN  = 257,
273
    G_VECREDUCE_FMAXIMUM  = 258,
274
    G_VECREDUCE_FMINIMUM  = 259,
275
    G_VECREDUCE_ADD = 260,
276
    G_VECREDUCE_MUL = 261,
277
    G_VECREDUCE_AND = 262,
278
    G_VECREDUCE_OR  = 263,
279
    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
281
    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
284
    G_SBFX  = 269,
285
    G_UBFX  = 270,
286
    ADJCALLSTACKDOWN  = 271,
287
    ADJCALLSTACKUP  = 272,
288
    PseudoAtomicLoadAdd32 = 273,
289
    PseudoAtomicLoadAnd32 = 274,
290
    PseudoAtomicLoadNand32  = 275,
291
    PseudoAtomicLoadNand64  = 276,
292
    PseudoAtomicLoadOr32  = 277,
293
    PseudoAtomicLoadSub32 = 278,
294
    PseudoAtomicLoadXor32 = 279,
295
    PseudoAtomicStoreD  = 280,
296
    PseudoAtomicStoreW  = 281,
297
    PseudoAtomicSwap32  = 282,
298
    PseudoBR  = 283,
299
    PseudoBRIND = 284,
300
    PseudoB_TAIL  = 285,
301
    PseudoCALL  = 286,
302
    PseudoCALL36  = 287,
303
    PseudoCALLIndirect  = 288,
304
    PseudoCALL_LARGE  = 289,
305
    PseudoCALL_MEDIUM = 290,
306
    PseudoCmpXchg32 = 291,
307
    PseudoCmpXchg64 = 292,
308
    PseudoCopyCFR = 293,
309
    PseudoJIRL_CALL = 294,
310
    PseudoJIRL_TAIL = 295,
311
    PseudoLA_ABS  = 296,
312
    PseudoLA_ABS_LARGE  = 297,
313
    PseudoLA_GOT  = 298,
314
    PseudoLA_GOT_LARGE  = 299,
315
    PseudoLA_PCREL  = 300,
316
    PseudoLA_PCREL_LARGE  = 301,
317
    PseudoLA_TLS_GD = 302,
318
    PseudoLA_TLS_GD_LARGE = 303,
319
    PseudoLA_TLS_IE = 304,
320
    PseudoLA_TLS_IE_LARGE = 305,
321
    PseudoLA_TLS_LD = 306,
322
    PseudoLA_TLS_LD_LARGE = 307,
323
    PseudoLA_TLS_LE = 308,
324
    PseudoLD_CFR  = 309,
325
    PseudoLI_D  = 310,
326
    PseudoLI_W  = 311,
327
    PseudoMaskedAtomicLoadAdd32 = 312,
328
    PseudoMaskedAtomicLoadMax32 = 313,
329
    PseudoMaskedAtomicLoadMin32 = 314,
330
    PseudoMaskedAtomicLoadNand32  = 315,
331
    PseudoMaskedAtomicLoadSub32 = 316,
332
    PseudoMaskedAtomicLoadUMax32  = 317,
333
    PseudoMaskedAtomicLoadUMin32  = 318,
334
    PseudoMaskedAtomicSwap32  = 319,
335
    PseudoMaskedCmpXchg32 = 320,
336
    PseudoRET = 321,
337
    PseudoST_CFR  = 322,
338
    PseudoTAIL  = 323,
339
    PseudoTAIL36  = 324,
340
    PseudoTAILIndirect  = 325,
341
    PseudoTAIL_LARGE  = 326,
342
    PseudoTAIL_MEDIUM = 327,
343
    PseudoUNIMP = 328,
344
    PseudoVBNZ  = 329,
345
    PseudoVBNZ_B  = 330,
346
    PseudoVBNZ_D  = 331,
347
    PseudoVBNZ_H  = 332,
348
    PseudoVBNZ_W  = 333,
349
    PseudoVBZ = 334,
350
    PseudoVBZ_B = 335,
351
    PseudoVBZ_D = 336,
352
    PseudoVBZ_H = 337,
353
    PseudoVBZ_W = 338,
354
    PseudoVREPLI_B  = 339,
355
    PseudoVREPLI_D  = 340,
356
    PseudoVREPLI_H  = 341,
357
    PseudoVREPLI_W  = 342,
358
    PseudoXVBNZ = 343,
359
    PseudoXVBNZ_B = 344,
360
    PseudoXVBNZ_D = 345,
361
    PseudoXVBNZ_H = 346,
362
    PseudoXVBNZ_W = 347,
363
    PseudoXVBZ  = 348,
364
    PseudoXVBZ_B  = 349,
365
    PseudoXVBZ_D  = 350,
366
    PseudoXVBZ_H  = 351,
367
    PseudoXVBZ_W  = 352,
368
    PseudoXVINSGR2VR_B  = 353,
369
    PseudoXVINSGR2VR_H  = 354,
370
    PseudoXVREPLI_B = 355,
371
    PseudoXVREPLI_D = 356,
372
    PseudoXVREPLI_H = 357,
373
    PseudoXVREPLI_W = 358,
374
    RDFCSR  = 359,
375
    WRFCSR  = 360,
376
    ADC_B = 361,
377
    ADC_D = 362,
378
    ADC_H = 363,
379
    ADC_W = 364,
380
    ADDI_D  = 365,
381
    ADDI_W  = 366,
382
    ADDU12I_D = 367,
383
    ADDU12I_W = 368,
384
    ADDU16I_D = 369,
385
    ADD_D = 370,
386
    ADD_W = 371,
387
    ALSL_D  = 372,
388
    ALSL_W  = 373,
389
    ALSL_WU = 374,
390
    AMADD_B = 375,
391
    AMADD_D = 376,
392
    AMADD_H = 377,
393
    AMADD_W = 378,
394
    AMADD__DB_B = 379,
395
    AMADD__DB_D = 380,
396
    AMADD__DB_H = 381,
397
    AMADD__DB_W = 382,
398
    AMAND_D = 383,
399
    AMAND_W = 384,
400
    AMAND__DB_D = 385,
401
    AMAND__DB_W = 386,
402
    AMCAS_B = 387,
403
    AMCAS_D = 388,
404
    AMCAS_H = 389,
405
    AMCAS_W = 390,
406
    AMCAS__DB_B = 391,
407
    AMCAS__DB_D = 392,
408
    AMCAS__DB_H = 393,
409
    AMCAS__DB_W = 394,
410
    AMMAX_D = 395,
411
    AMMAX_DU  = 396,
412
    AMMAX_W = 397,
413
    AMMAX_WU  = 398,
414
    AMMAX__DB_D = 399,
415
    AMMAX__DB_DU  = 400,
416
    AMMAX__DB_W = 401,
417
    AMMAX__DB_WU  = 402,
418
    AMMIN_D = 403,
419
    AMMIN_DU  = 404,
420
    AMMIN_W = 405,
421
    AMMIN_WU  = 406,
422
    AMMIN__DB_D = 407,
423
    AMMIN__DB_DU  = 408,
424
    AMMIN__DB_W = 409,
425
    AMMIN__DB_WU  = 410,
426
    AMOR_D  = 411,
427
    AMOR_W  = 412,
428
    AMOR__DB_D  = 413,
429
    AMOR__DB_W  = 414,
430
    AMSWAP_B  = 415,
431
    AMSWAP_D  = 416,
432
    AMSWAP_H  = 417,
433
    AMSWAP_W  = 418,
434
    AMSWAP__DB_B  = 419,
435
    AMSWAP__DB_D  = 420,
436
    AMSWAP__DB_H  = 421,
437
    AMSWAP__DB_W  = 422,
438
    AMXOR_D = 423,
439
    AMXOR_W = 424,
440
    AMXOR__DB_D = 425,
441
    AMXOR__DB_W = 426,
442
    AND = 427,
443
    ANDI  = 428,
444
    ANDN  = 429,
445
    ARMADC_W  = 430,
446
    ARMADD_W  = 431,
447
    ARMAND_W  = 432,
448
    ARMMFFLAG = 433,
449
    ARMMOVE = 434,
450
    ARMMOV_D  = 435,
451
    ARMMOV_W  = 436,
452
    ARMMTFLAG = 437,
453
    ARMNOT_W  = 438,
454
    ARMOR_W = 439,
455
    ARMROTRI_W  = 440,
456
    ARMROTR_W = 441,
457
    ARMRRX_W  = 442,
458
    ARMSBC_W  = 443,
459
    ARMSLLI_W = 444,
460
    ARMSLL_W  = 445,
461
    ARMSRAI_W = 446,
462
    ARMSRA_W  = 447,
463
    ARMSRLI_W = 448,
464
    ARMSRL_W  = 449,
465
    ARMSUB_W  = 450,
466
    ARMXOR_W  = 451,
467
    ASRTGT_D  = 452,
468
    ASRTLE_D  = 453,
469
    B = 454,
470
    BCEQZ = 455,
471
    BCNEZ = 456,
472
    BEQ = 457,
473
    BEQZ  = 458,
474
    BGE = 459,
475
    BGEU  = 460,
476
    BITREV_4B = 461,
477
    BITREV_8B = 462,
478
    BITREV_D  = 463,
479
    BITREV_W  = 464,
480
    BL  = 465,
481
    BLT = 466,
482
    BLTU  = 467,
483
    BNE = 468,
484
    BNEZ  = 469,
485
    BREAK = 470,
486
    BSTRINS_D = 471,
487
    BSTRINS_W = 472,
488
    BSTRPICK_D  = 473,
489
    BSTRPICK_W  = 474,
490
    BYTEPICK_D  = 475,
491
    BYTEPICK_W  = 476,
492
    CACOP = 477,
493
    CLO_D = 478,
494
    CLO_W = 479,
495
    CLZ_D = 480,
496
    CLZ_W = 481,
497
    CPUCFG  = 482,
498
    CRCC_W_B_W  = 483,
499
    CRCC_W_D_W  = 484,
500
    CRCC_W_H_W  = 485,
501
    CRCC_W_W_W  = 486,
502
    CRC_W_B_W = 487,
503
    CRC_W_D_W = 488,
504
    CRC_W_H_W = 489,
505
    CRC_W_W_W = 490,
506
    CSRRD = 491,
507
    CSRWR = 492,
508
    CSRXCHG = 493,
509
    CTO_D = 494,
510
    CTO_W = 495,
511
    CTZ_D = 496,
512
    CTZ_W = 497,
513
    DBAR  = 498,
514
    DBCL  = 499,
515
    DIV_D = 500,
516
    DIV_DU  = 501,
517
    DIV_W = 502,
518
    DIV_WU  = 503,
519
    ERTN  = 504,
520
    EXT_W_B = 505,
521
    EXT_W_H = 506,
522
    FABS_D  = 507,
523
    FABS_S  = 508,
524
    FADD_D  = 509,
525
    FADD_S  = 510,
526
    FCLASS_D  = 511,
527
    FCLASS_S  = 512,
528
    FCMP_CAF_D  = 513,
529
    FCMP_CAF_S  = 514,
530
    FCMP_CEQ_D  = 515,
531
    FCMP_CEQ_S  = 516,
532
    FCMP_CLE_D  = 517,
533
    FCMP_CLE_S  = 518,
534
    FCMP_CLT_D  = 519,
535
    FCMP_CLT_S  = 520,
536
    FCMP_CNE_D  = 521,
537
    FCMP_CNE_S  = 522,
538
    FCMP_COR_D  = 523,
539
    FCMP_COR_S  = 524,
540
    FCMP_CUEQ_D = 525,
541
    FCMP_CUEQ_S = 526,
542
    FCMP_CULE_D = 527,
543
    FCMP_CULE_S = 528,
544
    FCMP_CULT_D = 529,
545
    FCMP_CULT_S = 530,
546
    FCMP_CUNE_D = 531,
547
    FCMP_CUNE_S = 532,
548
    FCMP_CUN_D  = 533,
549
    FCMP_CUN_S  = 534,
550
    FCMP_SAF_D  = 535,
551
    FCMP_SAF_S  = 536,
552
    FCMP_SEQ_D  = 537,
553
    FCMP_SEQ_S  = 538,
554
    FCMP_SLE_D  = 539,
555
    FCMP_SLE_S  = 540,
556
    FCMP_SLT_D  = 541,
557
    FCMP_SLT_S  = 542,
558
    FCMP_SNE_D  = 543,
559
    FCMP_SNE_S  = 544,
560
    FCMP_SOR_D  = 545,
561
    FCMP_SOR_S  = 546,
562
    FCMP_SUEQ_D = 547,
563
    FCMP_SUEQ_S = 548,
564
    FCMP_SULE_D = 549,
565
    FCMP_SULE_S = 550,
566
    FCMP_SULT_D = 551,
567
    FCMP_SULT_S = 552,
568
    FCMP_SUNE_D = 553,
569
    FCMP_SUNE_S = 554,
570
    FCMP_SUN_D  = 555,
571
    FCMP_SUN_S  = 556,
572
    FCOPYSIGN_D = 557,
573
    FCOPYSIGN_S = 558,
574
    FCVT_D_LD = 559,
575
    FCVT_D_S  = 560,
576
    FCVT_LD_D = 561,
577
    FCVT_S_D  = 562,
578
    FCVT_UD_D = 563,
579
    FDIV_D  = 564,
580
    FDIV_S  = 565,
581
    FFINT_D_L = 566,
582
    FFINT_D_W = 567,
583
    FFINT_S_L = 568,
584
    FFINT_S_W = 569,
585
    FLDGT_D = 570,
586
    FLDGT_S = 571,
587
    FLDLE_D = 572,
588
    FLDLE_S = 573,
589
    FLDX_D  = 574,
590
    FLDX_S  = 575,
591
    FLD_D = 576,
592
    FLD_S = 577,
593
    FLOGB_D = 578,
594
    FLOGB_S = 579,
595
    FMADD_D = 580,
596
    FMADD_S = 581,
597
    FMAXA_D = 582,
598
    FMAXA_S = 583,
599
    FMAX_D  = 584,
600
    FMAX_S  = 585,
601
    FMINA_D = 586,
602
    FMINA_S = 587,
603
    FMIN_D  = 588,
604
    FMIN_S  = 589,
605
    FMOV_D  = 590,
606
    FMOV_S  = 591,
607
    FMSUB_D = 592,
608
    FMSUB_S = 593,
609
    FMUL_D  = 594,
610
    FMUL_S  = 595,
611
    FNEG_D  = 596,
612
    FNEG_S  = 597,
613
    FNMADD_D  = 598,
614
    FNMADD_S  = 599,
615
    FNMSUB_D  = 600,
616
    FNMSUB_S  = 601,
617
    FRECIPE_D = 602,
618
    FRECIPE_S = 603,
619
    FRECIP_D  = 604,
620
    FRECIP_S  = 605,
621
    FRINT_D = 606,
622
    FRINT_S = 607,
623
    FRSQRTE_D = 608,
624
    FRSQRTE_S = 609,
625
    FRSQRT_D  = 610,
626
    FRSQRT_S  = 611,
627
    FSCALEB_D = 612,
628
    FSCALEB_S = 613,
629
    FSEL_xD = 614,
630
    FSEL_xS = 615,
631
    FSQRT_D = 616,
632
    FSQRT_S = 617,
633
    FSTGT_D = 618,
634
    FSTGT_S = 619,
635
    FSTLE_D = 620,
636
    FSTLE_S = 621,
637
    FSTX_D  = 622,
638
    FSTX_S  = 623,
639
    FST_D = 624,
640
    FST_S = 625,
641
    FSUB_D  = 626,
642
    FSUB_S  = 627,
643
    FTINTRM_L_D = 628,
644
    FTINTRM_L_S = 629,
645
    FTINTRM_W_D = 630,
646
    FTINTRM_W_S = 631,
647
    FTINTRNE_L_D  = 632,
648
    FTINTRNE_L_S  = 633,
649
    FTINTRNE_W_D  = 634,
650
    FTINTRNE_W_S  = 635,
651
    FTINTRP_L_D = 636,
652
    FTINTRP_L_S = 637,
653
    FTINTRP_W_D = 638,
654
    FTINTRP_W_S = 639,
655
    FTINTRZ_L_D = 640,
656
    FTINTRZ_L_S = 641,
657
    FTINTRZ_W_D = 642,
658
    FTINTRZ_W_S = 643,
659
    FTINT_L_D = 644,
660
    FTINT_L_S = 645,
661
    FTINT_W_D = 646,
662
    FTINT_W_S = 647,
663
    GCSRRD  = 648,
664
    GCSRWR  = 649,
665
    GCSRXCHG  = 650,
666
    GTLBFLUSH = 651,
667
    HVCL  = 652,
668
    IBAR  = 653,
669
    IDLE  = 654,
670
    INVTLB  = 655,
671
    IOCSRRD_B = 656,
672
    IOCSRRD_D = 657,
673
    IOCSRRD_H = 658,
674
    IOCSRRD_W = 659,
675
    IOCSRWR_B = 660,
676
    IOCSRWR_D = 661,
677
    IOCSRWR_H = 662,
678
    IOCSRWR_W = 663,
679
    JIRL  = 664,
680
    JISCR0  = 665,
681
    JISCR1  = 666,
682
    LDDIR = 667,
683
    LDGT_B  = 668,
684
    LDGT_D  = 669,
685
    LDGT_H  = 670,
686
    LDGT_W  = 671,
687
    LDLE_B  = 672,
688
    LDLE_D  = 673,
689
    LDLE_H  = 674,
690
    LDLE_W  = 675,
691
    LDL_D = 676,
692
    LDL_W = 677,
693
    LDPTE = 678,
694
    LDPTR_D = 679,
695
    LDPTR_W = 680,
696
    LDR_D = 681,
697
    LDR_W = 682,
698
    LDX_B = 683,
699
    LDX_BU  = 684,
700
    LDX_D = 685,
701
    LDX_H = 686,
702
    LDX_HU  = 687,
703
    LDX_W = 688,
704
    LDX_WU  = 689,
705
    LD_B  = 690,
706
    LD_BU = 691,
707
    LD_D  = 692,
708
    LD_H  = 693,
709
    LD_HU = 694,
710
    LD_W  = 695,
711
    LD_WU = 696,
712
    LLACQ_D = 697,
713
    LLACQ_W = 698,
714
    LL_D  = 699,
715
    LL_W  = 700,
716
    LU12I_W = 701,
717
    LU32I_D = 702,
718
    LU52I_D = 703,
719
    MASKEQZ = 704,
720
    MASKNEZ = 705,
721
    MOD_D = 706,
722
    MOD_DU  = 707,
723
    MOD_W = 708,
724
    MOD_WU  = 709,
725
    MOVCF2FR_xS = 710,
726
    MOVCF2GR  = 711,
727
    MOVFCSR2GR  = 712,
728
    MOVFR2CF_xS = 713,
729
    MOVFR2GR_D  = 714,
730
    MOVFR2GR_S  = 715,
731
    MOVFR2GR_S_64 = 716,
732
    MOVFRH2GR_S = 717,
733
    MOVGR2CF  = 718,
734
    MOVGR2FCSR  = 719,
735
    MOVGR2FRH_W = 720,
736
    MOVGR2FR_D  = 721,
737
    MOVGR2FR_W  = 722,
738
    MOVGR2FR_W_64 = 723,
739
    MOVGR2SCR = 724,
740
    MOVSCR2GR = 725,
741
    MULH_D  = 726,
742
    MULH_DU = 727,
743
    MULH_W  = 728,
744
    MULH_WU = 729,
745
    MULW_D_W  = 730,
746
    MULW_D_WU = 731,
747
    MUL_D = 732,
748
    MUL_W = 733,
749
    NOR = 734,
750
    OR  = 735,
751
    ORI = 736,
752
    ORN = 737,
753
    PCADDI  = 738,
754
    PCADDU12I = 739,
755
    PCADDU18I = 740,
756
    PCALAU12I = 741,
757
    PRELD = 742,
758
    PRELDX  = 743,
759
    RCRI_B  = 744,
760
    RCRI_D  = 745,
761
    RCRI_H  = 746,
762
    RCRI_W  = 747,
763
    RCR_B = 748,
764
    RCR_D = 749,
765
    RCR_H = 750,
766
    RCR_W = 751,
767
    RDTIMEH_W = 752,
768
    RDTIMEL_W = 753,
769
    RDTIME_D  = 754,
770
    REVB_2H = 755,
771
    REVB_2W = 756,
772
    REVB_4H = 757,
773
    REVB_D  = 758,
774
    REVH_2W = 759,
775
    REVH_D  = 760,
776
    ROTRI_B = 761,
777
    ROTRI_D = 762,
778
    ROTRI_H = 763,
779
    ROTRI_W = 764,
780
    ROTR_B  = 765,
781
    ROTR_D  = 766,
782
    ROTR_H  = 767,
783
    ROTR_W  = 768,
784
    SBC_B = 769,
785
    SBC_D = 770,
786
    SBC_H = 771,
787
    SBC_W = 772,
788
    SCREL_D = 773,
789
    SCREL_W = 774,
790
    SC_D  = 775,
791
    SC_Q  = 776,
792
    SC_W  = 777,
793
    SETARMJ = 778,
794
    SETX86J = 779,
795
    SETX86LOOPE = 780,
796
    SETX86LOOPNE  = 781,
797
    SET_CFR_FALSE = 782,
798
    SET_CFR_TRUE  = 783,
799
    SLLI_D  = 784,
800
    SLLI_W  = 785,
801
    SLL_D = 786,
802
    SLL_W = 787,
803
    SLT = 788,
804
    SLTI  = 789,
805
    SLTU  = 790,
806
    SLTUI = 791,
807
    SRAI_D  = 792,
808
    SRAI_W  = 793,
809
    SRA_D = 794,
810
    SRA_W = 795,
811
    SRLI_D  = 796,
812
    SRLI_W  = 797,
813
    SRL_D = 798,
814
    SRL_W = 799,
815
    STGT_B  = 800,
816
    STGT_D  = 801,
817
    STGT_H  = 802,
818
    STGT_W  = 803,
819
    STLE_B  = 804,
820
    STLE_D  = 805,
821
    STLE_H  = 806,
822
    STLE_W  = 807,
823
    STL_D = 808,
824
    STL_W = 809,
825
    STPTR_D = 810,
826
    STPTR_W = 811,
827
    STR_D = 812,
828
    STR_W = 813,
829
    STX_B = 814,
830
    STX_D = 815,
831
    STX_H = 816,
832
    STX_W = 817,
833
    ST_B  = 818,
834
    ST_D  = 819,
835
    ST_H  = 820,
836
    ST_W  = 821,
837
    SUB_D = 822,
838
    SUB_W = 823,
839
    SYSCALL = 824,
840
    TLBCLR  = 825,
841
    TLBFILL = 826,
842
    TLBFLUSH  = 827,
843
    TLBRD = 828,
844
    TLBSRCH = 829,
845
    TLBWR = 830,
846
    VABSD_B = 831,
847
    VABSD_BU  = 832,
848
    VABSD_D = 833,
849
    VABSD_DU  = 834,
850
    VABSD_H = 835,
851
    VABSD_HU  = 836,
852
    VABSD_W = 837,
853
    VABSD_WU  = 838,
854
    VADDA_B = 839,
855
    VADDA_D = 840,
856
    VADDA_H = 841,
857
    VADDA_W = 842,
858
    VADDI_BU  = 843,
859
    VADDI_DU  = 844,
860
    VADDI_HU  = 845,
861
    VADDI_WU  = 846,
862
    VADDWEV_D_W = 847,
863
    VADDWEV_D_WU  = 848,
864
    VADDWEV_D_WU_W  = 849,
865
    VADDWEV_H_B = 850,
866
    VADDWEV_H_BU  = 851,
867
    VADDWEV_H_BU_B  = 852,
868
    VADDWEV_Q_D = 853,
869
    VADDWEV_Q_DU  = 854,
870
    VADDWEV_Q_DU_D  = 855,
871
    VADDWEV_W_H = 856,
872
    VADDWEV_W_HU  = 857,
873
    VADDWEV_W_HU_H  = 858,
874
    VADDWOD_D_W = 859,
875
    VADDWOD_D_WU  = 860,
876
    VADDWOD_D_WU_W  = 861,
877
    VADDWOD_H_B = 862,
878
    VADDWOD_H_BU  = 863,
879
    VADDWOD_H_BU_B  = 864,
880
    VADDWOD_Q_D = 865,
881
    VADDWOD_Q_DU  = 866,
882
    VADDWOD_Q_DU_D  = 867,
883
    VADDWOD_W_H = 868,
884
    VADDWOD_W_HU  = 869,
885
    VADDWOD_W_HU_H  = 870,
886
    VADD_B  = 871,
887
    VADD_D  = 872,
888
    VADD_H  = 873,
889
    VADD_Q  = 874,
890
    VADD_W  = 875,
891
    VANDI_B = 876,
892
    VANDN_V = 877,
893
    VAND_V  = 878,
894
    VAVGR_B = 879,
895
    VAVGR_BU  = 880,
896
    VAVGR_D = 881,
897
    VAVGR_DU  = 882,
898
    VAVGR_H = 883,
899
    VAVGR_HU  = 884,
900
    VAVGR_W = 885,
901
    VAVGR_WU  = 886,
902
    VAVG_B  = 887,
903
    VAVG_BU = 888,
904
    VAVG_D  = 889,
905
    VAVG_DU = 890,
906
    VAVG_H  = 891,
907
    VAVG_HU = 892,
908
    VAVG_W  = 893,
909
    VAVG_WU = 894,
910
    VBITCLRI_B  = 895,
911
    VBITCLRI_D  = 896,
912
    VBITCLRI_H  = 897,
913
    VBITCLRI_W  = 898,
914
    VBITCLR_B = 899,
915
    VBITCLR_D = 900,
916
    VBITCLR_H = 901,
917
    VBITCLR_W = 902,
918
    VBITREVI_B  = 903,
919
    VBITREVI_D  = 904,
920
    VBITREVI_H  = 905,
921
    VBITREVI_W  = 906,
922
    VBITREV_B = 907,
923
    VBITREV_D = 908,
924
    VBITREV_H = 909,
925
    VBITREV_W = 910,
926
    VBITSELI_B  = 911,
927
    VBITSEL_V = 912,
928
    VBITSETI_B  = 913,
929
    VBITSETI_D  = 914,
930
    VBITSETI_H  = 915,
931
    VBITSETI_W  = 916,
932
    VBITSET_B = 917,
933
    VBITSET_D = 918,
934
    VBITSET_H = 919,
935
    VBITSET_W = 920,
936
    VBSLL_V = 921,
937
    VBSRL_V = 922,
938
    VCLO_B  = 923,
939
    VCLO_D  = 924,
940
    VCLO_H  = 925,
941
    VCLO_W  = 926,
942
    VCLZ_B  = 927,
943
    VCLZ_D  = 928,
944
    VCLZ_H  = 929,
945
    VCLZ_W  = 930,
946
    VDIV_B  = 931,
947
    VDIV_BU = 932,
948
    VDIV_D  = 933,
949
    VDIV_DU = 934,
950
    VDIV_H  = 935,
951
    VDIV_HU = 936,
952
    VDIV_W  = 937,
953
    VDIV_WU = 938,
954
    VEXT2XV_DU_BU = 939,
955
    VEXT2XV_DU_HU = 940,
956
    VEXT2XV_DU_WU = 941,
957
    VEXT2XV_D_B = 942,
958
    VEXT2XV_D_H = 943,
959
    VEXT2XV_D_W = 944,
960
    VEXT2XV_HU_BU = 945,
961
    VEXT2XV_H_B = 946,
962
    VEXT2XV_WU_BU = 947,
963
    VEXT2XV_WU_HU = 948,
964
    VEXT2XV_W_B = 949,
965
    VEXT2XV_W_H = 950,
966
    VEXTH_DU_WU = 951,
967
    VEXTH_D_W = 952,
968
    VEXTH_HU_BU = 953,
969
    VEXTH_H_B = 954,
970
    VEXTH_QU_DU = 955,
971
    VEXTH_Q_D = 956,
972
    VEXTH_WU_HU = 957,
973
    VEXTH_W_H = 958,
974
    VEXTL_QU_DU = 959,
975
    VEXTL_Q_D = 960,
976
    VEXTRINS_B  = 961,
977
    VEXTRINS_D  = 962,
978
    VEXTRINS_H  = 963,
979
    VEXTRINS_W  = 964,
980
    VFADD_D = 965,
981
    VFADD_S = 966,
982
    VFCLASS_D = 967,
983
    VFCLASS_S = 968,
984
    VFCMP_CAF_D = 969,
985
    VFCMP_CAF_S = 970,
986
    VFCMP_CEQ_D = 971,
987
    VFCMP_CEQ_S = 972,
988
    VFCMP_CLE_D = 973,
989
    VFCMP_CLE_S = 974,
990
    VFCMP_CLT_D = 975,
991
    VFCMP_CLT_S = 976,
992
    VFCMP_CNE_D = 977,
993
    VFCMP_CNE_S = 978,
994
    VFCMP_COR_D = 979,
995
    VFCMP_COR_S = 980,
996
    VFCMP_CUEQ_D  = 981,
997
    VFCMP_CUEQ_S  = 982,
998
    VFCMP_CULE_D  = 983,
999
    VFCMP_CULE_S  = 984,
1000
    VFCMP_CULT_D  = 985,
1001
    VFCMP_CULT_S  = 986,
1002
    VFCMP_CUNE_D  = 987,
1003
    VFCMP_CUNE_S  = 988,
1004
    VFCMP_CUN_D = 989,
1005
    VFCMP_CUN_S = 990,
1006
    VFCMP_SAF_D = 991,
1007
    VFCMP_SAF_S = 992,
1008
    VFCMP_SEQ_D = 993,
1009
    VFCMP_SEQ_S = 994,
1010
    VFCMP_SLE_D = 995,
1011
    VFCMP_SLE_S = 996,
1012
    VFCMP_SLT_D = 997,
1013
    VFCMP_SLT_S = 998,
1014
    VFCMP_SNE_D = 999,
1015
    VFCMP_SNE_S = 1000,
1016
    VFCMP_SOR_D = 1001,
1017
    VFCMP_SOR_S = 1002,
1018
    VFCMP_SUEQ_D  = 1003,
1019
    VFCMP_SUEQ_S  = 1004,
1020
    VFCMP_SULE_D  = 1005,
1021
    VFCMP_SULE_S  = 1006,
1022
    VFCMP_SULT_D  = 1007,
1023
    VFCMP_SULT_S  = 1008,
1024
    VFCMP_SUNE_D  = 1009,
1025
    VFCMP_SUNE_S  = 1010,
1026
    VFCMP_SUN_D = 1011,
1027
    VFCMP_SUN_S = 1012,
1028
    VFCVTH_D_S  = 1013,
1029
    VFCVTH_S_H  = 1014,
1030
    VFCVTL_D_S  = 1015,
1031
    VFCVTL_S_H  = 1016,
1032
    VFCVT_H_S = 1017,
1033
    VFCVT_S_D = 1018,
1034
    VFDIV_D = 1019,
1035
    VFDIV_S = 1020,
1036
    VFFINTH_D_W = 1021,
1037
    VFFINTL_D_W = 1022,
1038
    VFFINT_D_L  = 1023,
1039
    VFFINT_D_LU = 1024,
1040
    VFFINT_S_L  = 1025,
1041
    VFFINT_S_W  = 1026,
1042
    VFFINT_S_WU = 1027,
1043
    VFLOGB_D  = 1028,
1044
    VFLOGB_S  = 1029,
1045
    VFMADD_D  = 1030,
1046
    VFMADD_S  = 1031,
1047
    VFMAXA_D  = 1032,
1048
    VFMAXA_S  = 1033,
1049
    VFMAX_D = 1034,
1050
    VFMAX_S = 1035,
1051
    VFMINA_D  = 1036,
1052
    VFMINA_S  = 1037,
1053
    VFMIN_D = 1038,
1054
    VFMIN_S = 1039,
1055
    VFMSUB_D  = 1040,
1056
    VFMSUB_S  = 1041,
1057
    VFMUL_D = 1042,
1058
    VFMUL_S = 1043,
1059
    VFNMADD_D = 1044,
1060
    VFNMADD_S = 1045,
1061
    VFNMSUB_D = 1046,
1062
    VFNMSUB_S = 1047,
1063
    VFRECIPE_D  = 1048,
1064
    VFRECIPE_S  = 1049,
1065
    VFRECIP_D = 1050,
1066
    VFRECIP_S = 1051,
1067
    VFRINTRM_D  = 1052,
1068
    VFRINTRM_S  = 1053,
1069
    VFRINTRNE_D = 1054,
1070
    VFRINTRNE_S = 1055,
1071
    VFRINTRP_D  = 1056,
1072
    VFRINTRP_S  = 1057,
1073
    VFRINTRZ_D  = 1058,
1074
    VFRINTRZ_S  = 1059,
1075
    VFRINT_D  = 1060,
1076
    VFRINT_S  = 1061,
1077
    VFRSQRTE_D  = 1062,
1078
    VFRSQRTE_S  = 1063,
1079
    VFRSQRT_D = 1064,
1080
    VFRSQRT_S = 1065,
1081
    VFRSTPI_B = 1066,
1082
    VFRSTPI_H = 1067,
1083
    VFRSTP_B  = 1068,
1084
    VFRSTP_H  = 1069,
1085
    VFSQRT_D  = 1070,
1086
    VFSQRT_S  = 1071,
1087
    VFSUB_D = 1072,
1088
    VFSUB_S = 1073,
1089
    VFTINTH_L_S = 1074,
1090
    VFTINTL_L_S = 1075,
1091
    VFTINTRMH_L_S = 1076,
1092
    VFTINTRML_L_S = 1077,
1093
    VFTINTRM_L_D  = 1078,
1094
    VFTINTRM_W_D  = 1079,
1095
    VFTINTRM_W_S  = 1080,
1096
    VFTINTRNEH_L_S  = 1081,
1097
    VFTINTRNEL_L_S  = 1082,
1098
    VFTINTRNE_L_D = 1083,
1099
    VFTINTRNE_W_D = 1084,
1100
    VFTINTRNE_W_S = 1085,
1101
    VFTINTRPH_L_S = 1086,
1102
    VFTINTRPL_L_S = 1087,
1103
    VFTINTRP_L_D  = 1088,
1104
    VFTINTRP_W_D  = 1089,
1105
    VFTINTRP_W_S  = 1090,
1106
    VFTINTRZH_L_S = 1091,
1107
    VFTINTRZL_L_S = 1092,
1108
    VFTINTRZ_LU_D = 1093,
1109
    VFTINTRZ_L_D  = 1094,
1110
    VFTINTRZ_WU_S = 1095,
1111
    VFTINTRZ_W_D  = 1096,
1112
    VFTINTRZ_W_S  = 1097,
1113
    VFTINT_LU_D = 1098,
1114
    VFTINT_L_D  = 1099,
1115
    VFTINT_WU_S = 1100,
1116
    VFTINT_W_D  = 1101,
1117
    VFTINT_W_S  = 1102,
1118
    VHADDW_DU_WU  = 1103,
1119
    VHADDW_D_W  = 1104,
1120
    VHADDW_HU_BU  = 1105,
1121
    VHADDW_H_B  = 1106,
1122
    VHADDW_QU_DU  = 1107,
1123
    VHADDW_Q_D  = 1108,
1124
    VHADDW_WU_HU  = 1109,
1125
    VHADDW_W_H  = 1110,
1126
    VHSUBW_DU_WU  = 1111,
1127
    VHSUBW_D_W  = 1112,
1128
    VHSUBW_HU_BU  = 1113,
1129
    VHSUBW_H_B  = 1114,
1130
    VHSUBW_QU_DU  = 1115,
1131
    VHSUBW_Q_D  = 1116,
1132
    VHSUBW_WU_HU  = 1117,
1133
    VHSUBW_W_H  = 1118,
1134
    VILVH_B = 1119,
1135
    VILVH_D = 1120,
1136
    VILVH_H = 1121,
1137
    VILVH_W = 1122,
1138
    VILVL_B = 1123,
1139
    VILVL_D = 1124,
1140
    VILVL_H = 1125,
1141
    VILVL_W = 1126,
1142
    VINSGR2VR_B = 1127,
1143
    VINSGR2VR_D = 1128,
1144
    VINSGR2VR_H = 1129,
1145
    VINSGR2VR_W = 1130,
1146
    VLD = 1131,
1147
    VLDI  = 1132,
1148
    VLDREPL_B = 1133,
1149
    VLDREPL_D = 1134,
1150
    VLDREPL_H = 1135,
1151
    VLDREPL_W = 1136,
1152
    VLDX  = 1137,
1153
    VMADDWEV_D_W  = 1138,
1154
    VMADDWEV_D_WU = 1139,
1155
    VMADDWEV_D_WU_W = 1140,
1156
    VMADDWEV_H_B  = 1141,
1157
    VMADDWEV_H_BU = 1142,
1158
    VMADDWEV_H_BU_B = 1143,
1159
    VMADDWEV_Q_D  = 1144,
1160
    VMADDWEV_Q_DU = 1145,
1161
    VMADDWEV_Q_DU_D = 1146,
1162
    VMADDWEV_W_H  = 1147,
1163
    VMADDWEV_W_HU = 1148,
1164
    VMADDWEV_W_HU_H = 1149,
1165
    VMADDWOD_D_W  = 1150,
1166
    VMADDWOD_D_WU = 1151,
1167
    VMADDWOD_D_WU_W = 1152,
1168
    VMADDWOD_H_B  = 1153,
1169
    VMADDWOD_H_BU = 1154,
1170
    VMADDWOD_H_BU_B = 1155,
1171
    VMADDWOD_Q_D  = 1156,
1172
    VMADDWOD_Q_DU = 1157,
1173
    VMADDWOD_Q_DU_D = 1158,
1174
    VMADDWOD_W_H  = 1159,
1175
    VMADDWOD_W_HU = 1160,
1176
    VMADDWOD_W_HU_H = 1161,
1177
    VMADD_B = 1162,
1178
    VMADD_D = 1163,
1179
    VMADD_H = 1164,
1180
    VMADD_W = 1165,
1181
    VMAXI_B = 1166,
1182
    VMAXI_BU  = 1167,
1183
    VMAXI_D = 1168,
1184
    VMAXI_DU  = 1169,
1185
    VMAXI_H = 1170,
1186
    VMAXI_HU  = 1171,
1187
    VMAXI_W = 1172,
1188
    VMAXI_WU  = 1173,
1189
    VMAX_B  = 1174,
1190
    VMAX_BU = 1175,
1191
    VMAX_D  = 1176,
1192
    VMAX_DU = 1177,
1193
    VMAX_H  = 1178,
1194
    VMAX_HU = 1179,
1195
    VMAX_W  = 1180,
1196
    VMAX_WU = 1181,
1197
    VMINI_B = 1182,
1198
    VMINI_BU  = 1183,
1199
    VMINI_D = 1184,
1200
    VMINI_DU  = 1185,
1201
    VMINI_H = 1186,
1202
    VMINI_HU  = 1187,
1203
    VMINI_W = 1188,
1204
    VMINI_WU  = 1189,
1205
    VMIN_B  = 1190,
1206
    VMIN_BU = 1191,
1207
    VMIN_D  = 1192,
1208
    VMIN_DU = 1193,
1209
    VMIN_H  = 1194,
1210
    VMIN_HU = 1195,
1211
    VMIN_W  = 1196,
1212
    VMIN_WU = 1197,
1213
    VMOD_B  = 1198,
1214
    VMOD_BU = 1199,
1215
    VMOD_D  = 1200,
1216
    VMOD_DU = 1201,
1217
    VMOD_H  = 1202,
1218
    VMOD_HU = 1203,
1219
    VMOD_W  = 1204,
1220
    VMOD_WU = 1205,
1221
    VMSKGEZ_B = 1206,
1222
    VMSKLTZ_B = 1207,
1223
    VMSKLTZ_D = 1208,
1224
    VMSKLTZ_H = 1209,
1225
    VMSKLTZ_W = 1210,
1226
    VMSKNZ_B  = 1211,
1227
    VMSUB_B = 1212,
1228
    VMSUB_D = 1213,
1229
    VMSUB_H = 1214,
1230
    VMSUB_W = 1215,
1231
    VMUH_B  = 1216,
1232
    VMUH_BU = 1217,
1233
    VMUH_D  = 1218,
1234
    VMUH_DU = 1219,
1235
    VMUH_H  = 1220,
1236
    VMUH_HU = 1221,
1237
    VMUH_W  = 1222,
1238
    VMUH_WU = 1223,
1239
    VMULWEV_D_W = 1224,
1240
    VMULWEV_D_WU  = 1225,
1241
    VMULWEV_D_WU_W  = 1226,
1242
    VMULWEV_H_B = 1227,
1243
    VMULWEV_H_BU  = 1228,
1244
    VMULWEV_H_BU_B  = 1229,
1245
    VMULWEV_Q_D = 1230,
1246
    VMULWEV_Q_DU  = 1231,
1247
    VMULWEV_Q_DU_D  = 1232,
1248
    VMULWEV_W_H = 1233,
1249
    VMULWEV_W_HU  = 1234,
1250
    VMULWEV_W_HU_H  = 1235,
1251
    VMULWOD_D_W = 1236,
1252
    VMULWOD_D_WU  = 1237,
1253
    VMULWOD_D_WU_W  = 1238,
1254
    VMULWOD_H_B = 1239,
1255
    VMULWOD_H_BU  = 1240,
1256
    VMULWOD_H_BU_B  = 1241,
1257
    VMULWOD_Q_D = 1242,
1258
    VMULWOD_Q_DU  = 1243,
1259
    VMULWOD_Q_DU_D  = 1244,
1260
    VMULWOD_W_H = 1245,
1261
    VMULWOD_W_HU  = 1246,
1262
    VMULWOD_W_HU_H  = 1247,
1263
    VMUL_B  = 1248,
1264
    VMUL_D  = 1249,
1265
    VMUL_H  = 1250,
1266
    VMUL_W  = 1251,
1267
    VNEG_B  = 1252,
1268
    VNEG_D  = 1253,
1269
    VNEG_H  = 1254,
1270
    VNEG_W  = 1255,
1271
    VNORI_B = 1256,
1272
    VNOR_V  = 1257,
1273
    VORI_B  = 1258,
1274
    VORN_V  = 1259,
1275
    VOR_V = 1260,
1276
    VPACKEV_B = 1261,
1277
    VPACKEV_D = 1262,
1278
    VPACKEV_H = 1263,
1279
    VPACKEV_W = 1264,
1280
    VPACKOD_B = 1265,
1281
    VPACKOD_D = 1266,
1282
    VPACKOD_H = 1267,
1283
    VPACKOD_W = 1268,
1284
    VPCNT_B = 1269,
1285
    VPCNT_D = 1270,
1286
    VPCNT_H = 1271,
1287
    VPCNT_W = 1272,
1288
    VPERMI_W  = 1273,
1289
    VPICKEV_B = 1274,
1290
    VPICKEV_D = 1275,
1291
    VPICKEV_H = 1276,
1292
    VPICKEV_W = 1277,
1293
    VPICKOD_B = 1278,
1294
    VPICKOD_D = 1279,
1295
    VPICKOD_H = 1280,
1296
    VPICKOD_W = 1281,
1297
    VPICKVE2GR_B  = 1282,
1298
    VPICKVE2GR_BU = 1283,
1299
    VPICKVE2GR_D  = 1284,
1300
    VPICKVE2GR_DU = 1285,
1301
    VPICKVE2GR_H  = 1286,
1302
    VPICKVE2GR_HU = 1287,
1303
    VPICKVE2GR_W  = 1288,
1304
    VPICKVE2GR_WU = 1289,
1305
    VREPLGR2VR_B  = 1290,
1306
    VREPLGR2VR_D  = 1291,
1307
    VREPLGR2VR_H  = 1292,
1308
    VREPLGR2VR_W  = 1293,
1309
    VREPLVEI_B  = 1294,
1310
    VREPLVEI_D  = 1295,
1311
    VREPLVEI_H  = 1296,
1312
    VREPLVEI_W  = 1297,
1313
    VREPLVE_B = 1298,
1314
    VREPLVE_D = 1299,
1315
    VREPLVE_H = 1300,
1316
    VREPLVE_W = 1301,
1317
    VROTRI_B  = 1302,
1318
    VROTRI_D  = 1303,
1319
    VROTRI_H  = 1304,
1320
    VROTRI_W  = 1305,
1321
    VROTR_B = 1306,
1322
    VROTR_D = 1307,
1323
    VROTR_H = 1308,
1324
    VROTR_W = 1309,
1325
    VSADD_B = 1310,
1326
    VSADD_BU  = 1311,
1327
    VSADD_D = 1312,
1328
    VSADD_DU  = 1313,
1329
    VSADD_H = 1314,
1330
    VSADD_HU  = 1315,
1331
    VSADD_W = 1316,
1332
    VSADD_WU  = 1317,
1333
    VSAT_B  = 1318,
1334
    VSAT_BU = 1319,
1335
    VSAT_D  = 1320,
1336
    VSAT_DU = 1321,
1337
    VSAT_H  = 1322,
1338
    VSAT_HU = 1323,
1339
    VSAT_W  = 1324,
1340
    VSAT_WU = 1325,
1341
    VSEQI_B = 1326,
1342
    VSEQI_D = 1327,
1343
    VSEQI_H = 1328,
1344
    VSEQI_W = 1329,
1345
    VSEQ_B  = 1330,
1346
    VSEQ_D  = 1331,
1347
    VSEQ_H  = 1332,
1348
    VSEQ_W  = 1333,
1349
    VSETALLNEZ_B  = 1334,
1350
    VSETALLNEZ_D  = 1335,
1351
    VSETALLNEZ_H  = 1336,
1352
    VSETALLNEZ_W  = 1337,
1353
    VSETANYEQZ_B  = 1338,
1354
    VSETANYEQZ_D  = 1339,
1355
    VSETANYEQZ_H  = 1340,
1356
    VSETANYEQZ_W  = 1341,
1357
    VSETEQZ_V = 1342,
1358
    VSETNEZ_V = 1343,
1359
    VSHUF4I_B = 1344,
1360
    VSHUF4I_D = 1345,
1361
    VSHUF4I_H = 1346,
1362
    VSHUF4I_W = 1347,
1363
    VSHUF_B = 1348,
1364
    VSHUF_D = 1349,
1365
    VSHUF_H = 1350,
1366
    VSHUF_W = 1351,
1367
    VSIGNCOV_B  = 1352,
1368
    VSIGNCOV_D  = 1353,
1369
    VSIGNCOV_H  = 1354,
1370
    VSIGNCOV_W  = 1355,
1371
    VSLEI_B = 1356,
1372
    VSLEI_BU  = 1357,
1373
    VSLEI_D = 1358,
1374
    VSLEI_DU  = 1359,
1375
    VSLEI_H = 1360,
1376
    VSLEI_HU  = 1361,
1377
    VSLEI_W = 1362,
1378
    VSLEI_WU  = 1363,
1379
    VSLE_B  = 1364,
1380
    VSLE_BU = 1365,
1381
    VSLE_D  = 1366,
1382
    VSLE_DU = 1367,
1383
    VSLE_H  = 1368,
1384
    VSLE_HU = 1369,
1385
    VSLE_W  = 1370,
1386
    VSLE_WU = 1371,
1387
    VSLLI_B = 1372,
1388
    VSLLI_D = 1373,
1389
    VSLLI_H = 1374,
1390
    VSLLI_W = 1375,
1391
    VSLLWIL_DU_WU = 1376,
1392
    VSLLWIL_D_W = 1377,
1393
    VSLLWIL_HU_BU = 1378,
1394
    VSLLWIL_H_B = 1379,
1395
    VSLLWIL_WU_HU = 1380,
1396
    VSLLWIL_W_H = 1381,
1397
    VSLL_B  = 1382,
1398
    VSLL_D  = 1383,
1399
    VSLL_H  = 1384,
1400
    VSLL_W  = 1385,
1401
    VSLTI_B = 1386,
1402
    VSLTI_BU  = 1387,
1403
    VSLTI_D = 1388,
1404
    VSLTI_DU  = 1389,
1405
    VSLTI_H = 1390,
1406
    VSLTI_HU  = 1391,
1407
    VSLTI_W = 1392,
1408
    VSLTI_WU  = 1393,
1409
    VSLT_B  = 1394,
1410
    VSLT_BU = 1395,
1411
    VSLT_D  = 1396,
1412
    VSLT_DU = 1397,
1413
    VSLT_H  = 1398,
1414
    VSLT_HU = 1399,
1415
    VSLT_W  = 1400,
1416
    VSLT_WU = 1401,
1417
    VSRAI_B = 1402,
1418
    VSRAI_D = 1403,
1419
    VSRAI_H = 1404,
1420
    VSRAI_W = 1405,
1421
    VSRANI_B_H  = 1406,
1422
    VSRANI_D_Q  = 1407,
1423
    VSRANI_H_W  = 1408,
1424
    VSRANI_W_D  = 1409,
1425
    VSRAN_B_H = 1410,
1426
    VSRAN_H_W = 1411,
1427
    VSRAN_W_D = 1412,
1428
    VSRARI_B  = 1413,
1429
    VSRARI_D  = 1414,
1430
    VSRARI_H  = 1415,
1431
    VSRARI_W  = 1416,
1432
    VSRARNI_B_H = 1417,
1433
    VSRARNI_D_Q = 1418,
1434
    VSRARNI_H_W = 1419,
1435
    VSRARNI_W_D = 1420,
1436
    VSRARN_B_H  = 1421,
1437
    VSRARN_H_W  = 1422,
1438
    VSRARN_W_D  = 1423,
1439
    VSRAR_B = 1424,
1440
    VSRAR_D = 1425,
1441
    VSRAR_H = 1426,
1442
    VSRAR_W = 1427,
1443
    VSRA_B  = 1428,
1444
    VSRA_D  = 1429,
1445
    VSRA_H  = 1430,
1446
    VSRA_W  = 1431,
1447
    VSRLI_B = 1432,
1448
    VSRLI_D = 1433,
1449
    VSRLI_H = 1434,
1450
    VSRLI_W = 1435,
1451
    VSRLNI_B_H  = 1436,
1452
    VSRLNI_D_Q  = 1437,
1453
    VSRLNI_H_W  = 1438,
1454
    VSRLNI_W_D  = 1439,
1455
    VSRLN_B_H = 1440,
1456
    VSRLN_H_W = 1441,
1457
    VSRLN_W_D = 1442,
1458
    VSRLRI_B  = 1443,
1459
    VSRLRI_D  = 1444,
1460
    VSRLRI_H  = 1445,
1461
    VSRLRI_W  = 1446,
1462
    VSRLRNI_B_H = 1447,
1463
    VSRLRNI_D_Q = 1448,
1464
    VSRLRNI_H_W = 1449,
1465
    VSRLRNI_W_D = 1450,
1466
    VSRLRN_B_H  = 1451,
1467
    VSRLRN_H_W  = 1452,
1468
    VSRLRN_W_D  = 1453,
1469
    VSRLR_B = 1454,
1470
    VSRLR_D = 1455,
1471
    VSRLR_H = 1456,
1472
    VSRLR_W = 1457,
1473
    VSRL_B  = 1458,
1474
    VSRL_D  = 1459,
1475
    VSRL_H  = 1460,
1476
    VSRL_W  = 1461,
1477
    VSSRANI_BU_H  = 1462,
1478
    VSSRANI_B_H = 1463,
1479
    VSSRANI_DU_Q  = 1464,
1480
    VSSRANI_D_Q = 1465,
1481
    VSSRANI_HU_W  = 1466,
1482
    VSSRANI_H_W = 1467,
1483
    VSSRANI_WU_D  = 1468,
1484
    VSSRANI_W_D = 1469,
1485
    VSSRAN_BU_H = 1470,
1486
    VSSRAN_B_H  = 1471,
1487
    VSSRAN_HU_W = 1472,
1488
    VSSRAN_H_W  = 1473,
1489
    VSSRAN_WU_D = 1474,
1490
    VSSRAN_W_D  = 1475,
1491
    VSSRARNI_BU_H = 1476,
1492
    VSSRARNI_B_H  = 1477,
1493
    VSSRARNI_DU_Q = 1478,
1494
    VSSRARNI_D_Q  = 1479,
1495
    VSSRARNI_HU_W = 1480,
1496
    VSSRARNI_H_W  = 1481,
1497
    VSSRARNI_WU_D = 1482,
1498
    VSSRARNI_W_D  = 1483,
1499
    VSSRARN_BU_H  = 1484,
1500
    VSSRARN_B_H = 1485,
1501
    VSSRARN_HU_W  = 1486,
1502
    VSSRARN_H_W = 1487,
1503
    VSSRARN_WU_D  = 1488,
1504
    VSSRARN_W_D = 1489,
1505
    VSSRLNI_BU_H  = 1490,
1506
    VSSRLNI_B_H = 1491,
1507
    VSSRLNI_DU_Q  = 1492,
1508
    VSSRLNI_D_Q = 1493,
1509
    VSSRLNI_HU_W  = 1494,
1510
    VSSRLNI_H_W = 1495,
1511
    VSSRLNI_WU_D  = 1496,
1512
    VSSRLNI_W_D = 1497,
1513
    VSSRLN_BU_H = 1498,
1514
    VSSRLN_B_H  = 1499,
1515
    VSSRLN_HU_W = 1500,
1516
    VSSRLN_H_W  = 1501,
1517
    VSSRLN_WU_D = 1502,
1518
    VSSRLN_W_D  = 1503,
1519
    VSSRLRNI_BU_H = 1504,
1520
    VSSRLRNI_B_H  = 1505,
1521
    VSSRLRNI_DU_Q = 1506,
1522
    VSSRLRNI_D_Q  = 1507,
1523
    VSSRLRNI_HU_W = 1508,
1524
    VSSRLRNI_H_W  = 1509,
1525
    VSSRLRNI_WU_D = 1510,
1526
    VSSRLRNI_W_D  = 1511,
1527
    VSSRLRN_BU_H  = 1512,
1528
    VSSRLRN_B_H = 1513,
1529
    VSSRLRN_HU_W  = 1514,
1530
    VSSRLRN_H_W = 1515,
1531
    VSSRLRN_WU_D  = 1516,
1532
    VSSRLRN_W_D = 1517,
1533
    VSSUB_B = 1518,
1534
    VSSUB_BU  = 1519,
1535
    VSSUB_D = 1520,
1536
    VSSUB_DU  = 1521,
1537
    VSSUB_H = 1522,
1538
    VSSUB_HU  = 1523,
1539
    VSSUB_W = 1524,
1540
    VSSUB_WU  = 1525,
1541
    VST = 1526,
1542
    VSTELM_B  = 1527,
1543
    VSTELM_D  = 1528,
1544
    VSTELM_H  = 1529,
1545
    VSTELM_W  = 1530,
1546
    VSTX  = 1531,
1547
    VSUBI_BU  = 1532,
1548
    VSUBI_DU  = 1533,
1549
    VSUBI_HU  = 1534,
1550
    VSUBI_WU  = 1535,
1551
    VSUBWEV_D_W = 1536,
1552
    VSUBWEV_D_WU  = 1537,
1553
    VSUBWEV_H_B = 1538,
1554
    VSUBWEV_H_BU  = 1539,
1555
    VSUBWEV_Q_D = 1540,
1556
    VSUBWEV_Q_DU  = 1541,
1557
    VSUBWEV_W_H = 1542,
1558
    VSUBWEV_W_HU  = 1543,
1559
    VSUBWOD_D_W = 1544,
1560
    VSUBWOD_D_WU  = 1545,
1561
    VSUBWOD_H_B = 1546,
1562
    VSUBWOD_H_BU  = 1547,
1563
    VSUBWOD_Q_D = 1548,
1564
    VSUBWOD_Q_DU  = 1549,
1565
    VSUBWOD_W_H = 1550,
1566
    VSUBWOD_W_HU  = 1551,
1567
    VSUB_B  = 1552,
1568
    VSUB_D  = 1553,
1569
    VSUB_H  = 1554,
1570
    VSUB_Q  = 1555,
1571
    VSUB_W  = 1556,
1572
    VXORI_B = 1557,
1573
    VXOR_V  = 1558,
1574
    X86ADC_B  = 1559,
1575
    X86ADC_D  = 1560,
1576
    X86ADC_H  = 1561,
1577
    X86ADC_W  = 1562,
1578
    X86ADD_B  = 1563,
1579
    X86ADD_D  = 1564,
1580
    X86ADD_DU = 1565,
1581
    X86ADD_H  = 1566,
1582
    X86ADD_W  = 1567,
1583
    X86ADD_WU = 1568,
1584
    X86AND_B  = 1569,
1585
    X86AND_D  = 1570,
1586
    X86AND_H  = 1571,
1587
    X86AND_W  = 1572,
1588
    X86CLRTM  = 1573,
1589
    X86DECTOP = 1574,
1590
    X86DEC_B  = 1575,
1591
    X86DEC_D  = 1576,
1592
    X86DEC_H  = 1577,
1593
    X86DEC_W  = 1578,
1594
    X86INCTOP = 1579,
1595
    X86INC_B  = 1580,
1596
    X86INC_D  = 1581,
1597
    X86INC_H  = 1582,
1598
    X86INC_W  = 1583,
1599
    X86MFFLAG = 1584,
1600
    X86MFTOP  = 1585,
1601
    X86MTFLAG = 1586,
1602
    X86MTTOP  = 1587,
1603
    X86MUL_B  = 1588,
1604
    X86MUL_BU = 1589,
1605
    X86MUL_D  = 1590,
1606
    X86MUL_DU = 1591,
1607
    X86MUL_H  = 1592,
1608
    X86MUL_HU = 1593,
1609
    X86MUL_W  = 1594,
1610
    X86MUL_WU = 1595,
1611
    X86OR_B = 1596,
1612
    X86OR_D = 1597,
1613
    X86OR_H = 1598,
1614
    X86OR_W = 1599,
1615
    X86RCLI_B = 1600,
1616
    X86RCLI_D = 1601,
1617
    X86RCLI_H = 1602,
1618
    X86RCLI_W = 1603,
1619
    X86RCL_B  = 1604,
1620
    X86RCL_D  = 1605,
1621
    X86RCL_H  = 1606,
1622
    X86RCL_W  = 1607,
1623
    X86RCRI_B = 1608,
1624
    X86RCRI_D = 1609,
1625
    X86RCRI_H = 1610,
1626
    X86RCRI_W = 1611,
1627
    X86RCR_B  = 1612,
1628
    X86RCR_D  = 1613,
1629
    X86RCR_H  = 1614,
1630
    X86RCR_W  = 1615,
1631
    X86ROTLI_B  = 1616,
1632
    X86ROTLI_D  = 1617,
1633
    X86ROTLI_H  = 1618,
1634
    X86ROTLI_W  = 1619,
1635
    X86ROTL_B = 1620,
1636
    X86ROTL_D = 1621,
1637
    X86ROTL_H = 1622,
1638
    X86ROTL_W = 1623,
1639
    X86ROTRI_B  = 1624,
1640
    X86ROTRI_D  = 1625,
1641
    X86ROTRI_H  = 1626,
1642
    X86ROTRI_W  = 1627,
1643
    X86ROTR_B = 1628,
1644
    X86ROTR_D = 1629,
1645
    X86ROTR_H = 1630,
1646
    X86ROTR_W = 1631,
1647
    X86SBC_B  = 1632,
1648
    X86SBC_D  = 1633,
1649
    X86SBC_H  = 1634,
1650
    X86SBC_W  = 1635,
1651
    X86SETTAG = 1636,
1652
    X86SETTM  = 1637,
1653
    X86SLLI_B = 1638,
1654
    X86SLLI_D = 1639,
1655
    X86SLLI_H = 1640,
1656
    X86SLLI_W = 1641,
1657
    X86SLL_B  = 1642,
1658
    X86SLL_D  = 1643,
1659
    X86SLL_H  = 1644,
1660
    X86SLL_W  = 1645,
1661
    X86SRAI_B = 1646,
1662
    X86SRAI_D = 1647,
1663
    X86SRAI_H = 1648,
1664
    X86SRAI_W = 1649,
1665
    X86SRA_B  = 1650,
1666
    X86SRA_D  = 1651,
1667
    X86SRA_H  = 1652,
1668
    X86SRA_W  = 1653,
1669
    X86SRLI_B = 1654,
1670
    X86SRLI_D = 1655,
1671
    X86SRLI_H = 1656,
1672
    X86SRLI_W = 1657,
1673
    X86SRL_B  = 1658,
1674
    X86SRL_D  = 1659,
1675
    X86SRL_H  = 1660,
1676
    X86SRL_W  = 1661,
1677
    X86SUB_B  = 1662,
1678
    X86SUB_D  = 1663,
1679
    X86SUB_DU = 1664,
1680
    X86SUB_H  = 1665,
1681
    X86SUB_W  = 1666,
1682
    X86SUB_WU = 1667,
1683
    X86XOR_B  = 1668,
1684
    X86XOR_D  = 1669,
1685
    X86XOR_H  = 1670,
1686
    X86XOR_W  = 1671,
1687
    XOR = 1672,
1688
    XORI  = 1673,
1689
    XVABSD_B  = 1674,
1690
    XVABSD_BU = 1675,
1691
    XVABSD_D  = 1676,
1692
    XVABSD_DU = 1677,
1693
    XVABSD_H  = 1678,
1694
    XVABSD_HU = 1679,
1695
    XVABSD_W  = 1680,
1696
    XVABSD_WU = 1681,
1697
    XVADDA_B  = 1682,
1698
    XVADDA_D  = 1683,
1699
    XVADDA_H  = 1684,
1700
    XVADDA_W  = 1685,
1701
    XVADDI_BU = 1686,
1702
    XVADDI_DU = 1687,
1703
    XVADDI_HU = 1688,
1704
    XVADDI_WU = 1689,
1705
    XVADDWEV_D_W  = 1690,
1706
    XVADDWEV_D_WU = 1691,
1707
    XVADDWEV_D_WU_W = 1692,
1708
    XVADDWEV_H_B  = 1693,
1709
    XVADDWEV_H_BU = 1694,
1710
    XVADDWEV_H_BU_B = 1695,
1711
    XVADDWEV_Q_D  = 1696,
1712
    XVADDWEV_Q_DU = 1697,
1713
    XVADDWEV_Q_DU_D = 1698,
1714
    XVADDWEV_W_H  = 1699,
1715
    XVADDWEV_W_HU = 1700,
1716
    XVADDWEV_W_HU_H = 1701,
1717
    XVADDWOD_D_W  = 1702,
1718
    XVADDWOD_D_WU = 1703,
1719
    XVADDWOD_D_WU_W = 1704,
1720
    XVADDWOD_H_B  = 1705,
1721
    XVADDWOD_H_BU = 1706,
1722
    XVADDWOD_H_BU_B = 1707,
1723
    XVADDWOD_Q_D  = 1708,
1724
    XVADDWOD_Q_DU = 1709,
1725
    XVADDWOD_Q_DU_D = 1710,
1726
    XVADDWOD_W_H  = 1711,
1727
    XVADDWOD_W_HU = 1712,
1728
    XVADDWOD_W_HU_H = 1713,
1729
    XVADD_B = 1714,
1730
    XVADD_D = 1715,
1731
    XVADD_H = 1716,
1732
    XVADD_Q = 1717,
1733
    XVADD_W = 1718,
1734
    XVANDI_B  = 1719,
1735
    XVANDN_V  = 1720,
1736
    XVAND_V = 1721,
1737
    XVAVGR_B  = 1722,
1738
    XVAVGR_BU = 1723,
1739
    XVAVGR_D  = 1724,
1740
    XVAVGR_DU = 1725,
1741
    XVAVGR_H  = 1726,
1742
    XVAVGR_HU = 1727,
1743
    XVAVGR_W  = 1728,
1744
    XVAVGR_WU = 1729,
1745
    XVAVG_B = 1730,
1746
    XVAVG_BU  = 1731,
1747
    XVAVG_D = 1732,
1748
    XVAVG_DU  = 1733,
1749
    XVAVG_H = 1734,
1750
    XVAVG_HU  = 1735,
1751
    XVAVG_W = 1736,
1752
    XVAVG_WU  = 1737,
1753
    XVBITCLRI_B = 1738,
1754
    XVBITCLRI_D = 1739,
1755
    XVBITCLRI_H = 1740,
1756
    XVBITCLRI_W = 1741,
1757
    XVBITCLR_B  = 1742,
1758
    XVBITCLR_D  = 1743,
1759
    XVBITCLR_H  = 1744,
1760
    XVBITCLR_W  = 1745,
1761
    XVBITREVI_B = 1746,
1762
    XVBITREVI_D = 1747,
1763
    XVBITREVI_H = 1748,
1764
    XVBITREVI_W = 1749,
1765
    XVBITREV_B  = 1750,
1766
    XVBITREV_D  = 1751,
1767
    XVBITREV_H  = 1752,
1768
    XVBITREV_W  = 1753,
1769
    XVBITSELI_B = 1754,
1770
    XVBITSEL_V  = 1755,
1771
    XVBITSETI_B = 1756,
1772
    XVBITSETI_D = 1757,
1773
    XVBITSETI_H = 1758,
1774
    XVBITSETI_W = 1759,
1775
    XVBITSET_B  = 1760,
1776
    XVBITSET_D  = 1761,
1777
    XVBITSET_H  = 1762,
1778
    XVBITSET_W  = 1763,
1779
    XVBSLL_V  = 1764,
1780
    XVBSRL_V  = 1765,
1781
    XVCLO_B = 1766,
1782
    XVCLO_D = 1767,
1783
    XVCLO_H = 1768,
1784
    XVCLO_W = 1769,
1785
    XVCLZ_B = 1770,
1786
    XVCLZ_D = 1771,
1787
    XVCLZ_H = 1772,
1788
    XVCLZ_W = 1773,
1789
    XVDIV_B = 1774,
1790
    XVDIV_BU  = 1775,
1791
    XVDIV_D = 1776,
1792
    XVDIV_DU  = 1777,
1793
    XVDIV_H = 1778,
1794
    XVDIV_HU  = 1779,
1795
    XVDIV_W = 1780,
1796
    XVDIV_WU  = 1781,
1797
    XVEXTH_DU_WU  = 1782,
1798
    XVEXTH_D_W  = 1783,
1799
    XVEXTH_HU_BU  = 1784,
1800
    XVEXTH_H_B  = 1785,
1801
    XVEXTH_QU_DU  = 1786,
1802
    XVEXTH_Q_D  = 1787,
1803
    XVEXTH_WU_HU  = 1788,
1804
    XVEXTH_W_H  = 1789,
1805
    XVEXTL_QU_DU  = 1790,
1806
    XVEXTL_Q_D  = 1791,
1807
    XVEXTRINS_B = 1792,
1808
    XVEXTRINS_D = 1793,
1809
    XVEXTRINS_H = 1794,
1810
    XVEXTRINS_W = 1795,
1811
    XVFADD_D  = 1796,
1812
    XVFADD_S  = 1797,
1813
    XVFCLASS_D  = 1798,
1814
    XVFCLASS_S  = 1799,
1815
    XVFCMP_CAF_D  = 1800,
1816
    XVFCMP_CAF_S  = 1801,
1817
    XVFCMP_CEQ_D  = 1802,
1818
    XVFCMP_CEQ_S  = 1803,
1819
    XVFCMP_CLE_D  = 1804,
1820
    XVFCMP_CLE_S  = 1805,
1821
    XVFCMP_CLT_D  = 1806,
1822
    XVFCMP_CLT_S  = 1807,
1823
    XVFCMP_CNE_D  = 1808,
1824
    XVFCMP_CNE_S  = 1809,
1825
    XVFCMP_COR_D  = 1810,
1826
    XVFCMP_COR_S  = 1811,
1827
    XVFCMP_CUEQ_D = 1812,
1828
    XVFCMP_CUEQ_S = 1813,
1829
    XVFCMP_CULE_D = 1814,
1830
    XVFCMP_CULE_S = 1815,
1831
    XVFCMP_CULT_D = 1816,
1832
    XVFCMP_CULT_S = 1817,
1833
    XVFCMP_CUNE_D = 1818,
1834
    XVFCMP_CUNE_S = 1819,
1835
    XVFCMP_CUN_D  = 1820,
1836
    XVFCMP_CUN_S  = 1821,
1837
    XVFCMP_SAF_D  = 1822,
1838
    XVFCMP_SAF_S  = 1823,
1839
    XVFCMP_SEQ_D  = 1824,
1840
    XVFCMP_SEQ_S  = 1825,
1841
    XVFCMP_SLE_D  = 1826,
1842
    XVFCMP_SLE_S  = 1827,
1843
    XVFCMP_SLT_D  = 1828,
1844
    XVFCMP_SLT_S  = 1829,
1845
    XVFCMP_SNE_D  = 1830,
1846
    XVFCMP_SNE_S  = 1831,
1847
    XVFCMP_SOR_D  = 1832,
1848
    XVFCMP_SOR_S  = 1833,
1849
    XVFCMP_SUEQ_D = 1834,
1850
    XVFCMP_SUEQ_S = 1835,
1851
    XVFCMP_SULE_D = 1836,
1852
    XVFCMP_SULE_S = 1837,
1853
    XVFCMP_SULT_D = 1838,
1854
    XVFCMP_SULT_S = 1839,
1855
    XVFCMP_SUNE_D = 1840,
1856
    XVFCMP_SUNE_S = 1841,
1857
    XVFCMP_SUN_D  = 1842,
1858
    XVFCMP_SUN_S  = 1843,
1859
    XVFCVTH_D_S = 1844,
1860
    XVFCVTH_S_H = 1845,
1861
    XVFCVTL_D_S = 1846,
1862
    XVFCVTL_S_H = 1847,
1863
    XVFCVT_H_S  = 1848,
1864
    XVFCVT_S_D  = 1849,
1865
    XVFDIV_D  = 1850,
1866
    XVFDIV_S  = 1851,
1867
    XVFFINTH_D_W  = 1852,
1868
    XVFFINTL_D_W  = 1853,
1869
    XVFFINT_D_L = 1854,
1870
    XVFFINT_D_LU  = 1855,
1871
    XVFFINT_S_L = 1856,
1872
    XVFFINT_S_W = 1857,
1873
    XVFFINT_S_WU  = 1858,
1874
    XVFLOGB_D = 1859,
1875
    XVFLOGB_S = 1860,
1876
    XVFMADD_D = 1861,
1877
    XVFMADD_S = 1862,
1878
    XVFMAXA_D = 1863,
1879
    XVFMAXA_S = 1864,
1880
    XVFMAX_D  = 1865,
1881
    XVFMAX_S  = 1866,
1882
    XVFMINA_D = 1867,
1883
    XVFMINA_S = 1868,
1884
    XVFMIN_D  = 1869,
1885
    XVFMIN_S  = 1870,
1886
    XVFMSUB_D = 1871,
1887
    XVFMSUB_S = 1872,
1888
    XVFMUL_D  = 1873,
1889
    XVFMUL_S  = 1874,
1890
    XVFNMADD_D  = 1875,
1891
    XVFNMADD_S  = 1876,
1892
    XVFNMSUB_D  = 1877,
1893
    XVFNMSUB_S  = 1878,
1894
    XVFRECIPE_D = 1879,
1895
    XVFRECIPE_S = 1880,
1896
    XVFRECIP_D  = 1881,
1897
    XVFRECIP_S  = 1882,
1898
    XVFRINTRM_D = 1883,
1899
    XVFRINTRM_S = 1884,
1900
    XVFRINTRNE_D  = 1885,
1901
    XVFRINTRNE_S  = 1886,
1902
    XVFRINTRP_D = 1887,
1903
    XVFRINTRP_S = 1888,
1904
    XVFRINTRZ_D = 1889,
1905
    XVFRINTRZ_S = 1890,
1906
    XVFRINT_D = 1891,
1907
    XVFRINT_S = 1892,
1908
    XVFRSQRTE_D = 1893,
1909
    XVFRSQRTE_S = 1894,
1910
    XVFRSQRT_D  = 1895,
1911
    XVFRSQRT_S  = 1896,
1912
    XVFRSTPI_B  = 1897,
1913
    XVFRSTPI_H  = 1898,
1914
    XVFRSTP_B = 1899,
1915
    XVFRSTP_H = 1900,
1916
    XVFSQRT_D = 1901,
1917
    XVFSQRT_S = 1902,
1918
    XVFSUB_D  = 1903,
1919
    XVFSUB_S  = 1904,
1920
    XVFTINTH_L_S  = 1905,
1921
    XVFTINTL_L_S  = 1906,
1922
    XVFTINTRMH_L_S  = 1907,
1923
    XVFTINTRML_L_S  = 1908,
1924
    XVFTINTRM_L_D = 1909,
1925
    XVFTINTRM_W_D = 1910,
1926
    XVFTINTRM_W_S = 1911,
1927
    XVFTINTRNEH_L_S = 1912,
1928
    XVFTINTRNEL_L_S = 1913,
1929
    XVFTINTRNE_L_D  = 1914,
1930
    XVFTINTRNE_W_D  = 1915,
1931
    XVFTINTRNE_W_S  = 1916,
1932
    XVFTINTRPH_L_S  = 1917,
1933
    XVFTINTRPL_L_S  = 1918,
1934
    XVFTINTRP_L_D = 1919,
1935
    XVFTINTRP_W_D = 1920,
1936
    XVFTINTRP_W_S = 1921,
1937
    XVFTINTRZH_L_S  = 1922,
1938
    XVFTINTRZL_L_S  = 1923,
1939
    XVFTINTRZ_LU_D  = 1924,
1940
    XVFTINTRZ_L_D = 1925,
1941
    XVFTINTRZ_WU_S  = 1926,
1942
    XVFTINTRZ_W_D = 1927,
1943
    XVFTINTRZ_W_S = 1928,
1944
    XVFTINT_LU_D  = 1929,
1945
    XVFTINT_L_D = 1930,
1946
    XVFTINT_WU_S  = 1931,
1947
    XVFTINT_W_D = 1932,
1948
    XVFTINT_W_S = 1933,
1949
    XVHADDW_DU_WU = 1934,
1950
    XVHADDW_D_W = 1935,
1951
    XVHADDW_HU_BU = 1936,
1952
    XVHADDW_H_B = 1937,
1953
    XVHADDW_QU_DU = 1938,
1954
    XVHADDW_Q_D = 1939,
1955
    XVHADDW_WU_HU = 1940,
1956
    XVHADDW_W_H = 1941,
1957
    XVHSELI_D = 1942,
1958
    XVHSUBW_DU_WU = 1943,
1959
    XVHSUBW_D_W = 1944,
1960
    XVHSUBW_HU_BU = 1945,
1961
    XVHSUBW_H_B = 1946,
1962
    XVHSUBW_QU_DU = 1947,
1963
    XVHSUBW_Q_D = 1948,
1964
    XVHSUBW_WU_HU = 1949,
1965
    XVHSUBW_W_H = 1950,
1966
    XVILVH_B  = 1951,
1967
    XVILVH_D  = 1952,
1968
    XVILVH_H  = 1953,
1969
    XVILVH_W  = 1954,
1970
    XVILVL_B  = 1955,
1971
    XVILVL_D  = 1956,
1972
    XVILVL_H  = 1957,
1973
    XVILVL_W  = 1958,
1974
    XVINSGR2VR_D  = 1959,
1975
    XVINSGR2VR_W  = 1960,
1976
    XVINSVE0_D  = 1961,
1977
    XVINSVE0_W  = 1962,
1978
    XVLD  = 1963,
1979
    XVLDI = 1964,
1980
    XVLDREPL_B  = 1965,
1981
    XVLDREPL_D  = 1966,
1982
    XVLDREPL_H  = 1967,
1983
    XVLDREPL_W  = 1968,
1984
    XVLDX = 1969,
1985
    XVMADDWEV_D_W = 1970,
1986
    XVMADDWEV_D_WU  = 1971,
1987
    XVMADDWEV_D_WU_W  = 1972,
1988
    XVMADDWEV_H_B = 1973,
1989
    XVMADDWEV_H_BU  = 1974,
1990
    XVMADDWEV_H_BU_B  = 1975,
1991
    XVMADDWEV_Q_D = 1976,
1992
    XVMADDWEV_Q_DU  = 1977,
1993
    XVMADDWEV_Q_DU_D  = 1978,
1994
    XVMADDWEV_W_H = 1979,
1995
    XVMADDWEV_W_HU  = 1980,
1996
    XVMADDWEV_W_HU_H  = 1981,
1997
    XVMADDWOD_D_W = 1982,
1998
    XVMADDWOD_D_WU  = 1983,
1999
    XVMADDWOD_D_WU_W  = 1984,
2000
    XVMADDWOD_H_B = 1985,
2001
    XVMADDWOD_H_BU  = 1986,
2002
    XVMADDWOD_H_BU_B  = 1987,
2003
    XVMADDWOD_Q_D = 1988,
2004
    XVMADDWOD_Q_DU  = 1989,
2005
    XVMADDWOD_Q_DU_D  = 1990,
2006
    XVMADDWOD_W_H = 1991,
2007
    XVMADDWOD_W_HU  = 1992,
2008
    XVMADDWOD_W_HU_H  = 1993,
2009
    XVMADD_B  = 1994,
2010
    XVMADD_D  = 1995,
2011
    XVMADD_H  = 1996,
2012
    XVMADD_W  = 1997,
2013
    XVMAXI_B  = 1998,
2014
    XVMAXI_BU = 1999,
2015
    XVMAXI_D  = 2000,
2016
    XVMAXI_DU = 2001,
2017
    XVMAXI_H  = 2002,
2018
    XVMAXI_HU = 2003,
2019
    XVMAXI_W  = 2004,
2020
    XVMAXI_WU = 2005,
2021
    XVMAX_B = 2006,
2022
    XVMAX_BU  = 2007,
2023
    XVMAX_D = 2008,
2024
    XVMAX_DU  = 2009,
2025
    XVMAX_H = 2010,
2026
    XVMAX_HU  = 2011,
2027
    XVMAX_W = 2012,
2028
    XVMAX_WU  = 2013,
2029
    XVMINI_B  = 2014,
2030
    XVMINI_BU = 2015,
2031
    XVMINI_D  = 2016,
2032
    XVMINI_DU = 2017,
2033
    XVMINI_H  = 2018,
2034
    XVMINI_HU = 2019,
2035
    XVMINI_W  = 2020,
2036
    XVMINI_WU = 2021,
2037
    XVMIN_B = 2022,
2038
    XVMIN_BU  = 2023,
2039
    XVMIN_D = 2024,
2040
    XVMIN_DU  = 2025,
2041
    XVMIN_H = 2026,
2042
    XVMIN_HU  = 2027,
2043
    XVMIN_W = 2028,
2044
    XVMIN_WU  = 2029,
2045
    XVMOD_B = 2030,
2046
    XVMOD_BU  = 2031,
2047
    XVMOD_D = 2032,
2048
    XVMOD_DU  = 2033,
2049
    XVMOD_H = 2034,
2050
    XVMOD_HU  = 2035,
2051
    XVMOD_W = 2036,
2052
    XVMOD_WU  = 2037,
2053
    XVMSKGEZ_B  = 2038,
2054
    XVMSKLTZ_B  = 2039,
2055
    XVMSKLTZ_D  = 2040,
2056
    XVMSKLTZ_H  = 2041,
2057
    XVMSKLTZ_W  = 2042,
2058
    XVMSKNZ_B = 2043,
2059
    XVMSUB_B  = 2044,
2060
    XVMSUB_D  = 2045,
2061
    XVMSUB_H  = 2046,
2062
    XVMSUB_W  = 2047,
2063
    XVMUH_B = 2048,
2064
    XVMUH_BU  = 2049,
2065
    XVMUH_D = 2050,
2066
    XVMUH_DU  = 2051,
2067
    XVMUH_H = 2052,
2068
    XVMUH_HU  = 2053,
2069
    XVMUH_W = 2054,
2070
    XVMUH_WU  = 2055,
2071
    XVMULWEV_D_W  = 2056,
2072
    XVMULWEV_D_WU = 2057,
2073
    XVMULWEV_D_WU_W = 2058,
2074
    XVMULWEV_H_B  = 2059,
2075
    XVMULWEV_H_BU = 2060,
2076
    XVMULWEV_H_BU_B = 2061,
2077
    XVMULWEV_Q_D  = 2062,
2078
    XVMULWEV_Q_DU = 2063,
2079
    XVMULWEV_Q_DU_D = 2064,
2080
    XVMULWEV_W_H  = 2065,
2081
    XVMULWEV_W_HU = 2066,
2082
    XVMULWEV_W_HU_H = 2067,
2083
    XVMULWOD_D_W  = 2068,
2084
    XVMULWOD_D_WU = 2069,
2085
    XVMULWOD_D_WU_W = 2070,
2086
    XVMULWOD_H_B  = 2071,
2087
    XVMULWOD_H_BU = 2072,
2088
    XVMULWOD_H_BU_B = 2073,
2089
    XVMULWOD_Q_D  = 2074,
2090
    XVMULWOD_Q_DU = 2075,
2091
    XVMULWOD_Q_DU_D = 2076,
2092
    XVMULWOD_W_H  = 2077,
2093
    XVMULWOD_W_HU = 2078,
2094
    XVMULWOD_W_HU_H = 2079,
2095
    XVMUL_B = 2080,
2096
    XVMUL_D = 2081,
2097
    XVMUL_H = 2082,
2098
    XVMUL_W = 2083,
2099
    XVNEG_B = 2084,
2100
    XVNEG_D = 2085,
2101
    XVNEG_H = 2086,
2102
    XVNEG_W = 2087,
2103
    XVNORI_B  = 2088,
2104
    XVNOR_V = 2089,
2105
    XVORI_B = 2090,
2106
    XVORN_V = 2091,
2107
    XVOR_V  = 2092,
2108
    XVPACKEV_B  = 2093,
2109
    XVPACKEV_D  = 2094,
2110
    XVPACKEV_H  = 2095,
2111
    XVPACKEV_W  = 2096,
2112
    XVPACKOD_B  = 2097,
2113
    XVPACKOD_D  = 2098,
2114
    XVPACKOD_H  = 2099,
2115
    XVPACKOD_W  = 2100,
2116
    XVPCNT_B  = 2101,
2117
    XVPCNT_D  = 2102,
2118
    XVPCNT_H  = 2103,
2119
    XVPCNT_W  = 2104,
2120
    XVPERMI_D = 2105,
2121
    XVPERMI_Q = 2106,
2122
    XVPERMI_W = 2107,
2123
    XVPERM_W  = 2108,
2124
    XVPICKEV_B  = 2109,
2125
    XVPICKEV_D  = 2110,
2126
    XVPICKEV_H  = 2111,
2127
    XVPICKEV_W  = 2112,
2128
    XVPICKOD_B  = 2113,
2129
    XVPICKOD_D  = 2114,
2130
    XVPICKOD_H  = 2115,
2131
    XVPICKOD_W  = 2116,
2132
    XVPICKVE2GR_D = 2117,
2133
    XVPICKVE2GR_DU  = 2118,
2134
    XVPICKVE2GR_W = 2119,
2135
    XVPICKVE2GR_WU  = 2120,
2136
    XVPICKVE_D  = 2121,
2137
    XVPICKVE_W  = 2122,
2138
    XVREPL128VEI_B  = 2123,
2139
    XVREPL128VEI_D  = 2124,
2140
    XVREPL128VEI_H  = 2125,
2141
    XVREPL128VEI_W  = 2126,
2142
    XVREPLGR2VR_B = 2127,
2143
    XVREPLGR2VR_D = 2128,
2144
    XVREPLGR2VR_H = 2129,
2145
    XVREPLGR2VR_W = 2130,
2146
    XVREPLVE0_B = 2131,
2147
    XVREPLVE0_D = 2132,
2148
    XVREPLVE0_H = 2133,
2149
    XVREPLVE0_Q = 2134,
2150
    XVREPLVE0_W = 2135,
2151
    XVREPLVE_B  = 2136,
2152
    XVREPLVE_D  = 2137,
2153
    XVREPLVE_H  = 2138,
2154
    XVREPLVE_W  = 2139,
2155
    XVROTRI_B = 2140,
2156
    XVROTRI_D = 2141,
2157
    XVROTRI_H = 2142,
2158
    XVROTRI_W = 2143,
2159
    XVROTR_B  = 2144,
2160
    XVROTR_D  = 2145,
2161
    XVROTR_H  = 2146,
2162
    XVROTR_W  = 2147,
2163
    XVSADD_B  = 2148,
2164
    XVSADD_BU = 2149,
2165
    XVSADD_D  = 2150,
2166
    XVSADD_DU = 2151,
2167
    XVSADD_H  = 2152,
2168
    XVSADD_HU = 2153,
2169
    XVSADD_W  = 2154,
2170
    XVSADD_WU = 2155,
2171
    XVSAT_B = 2156,
2172
    XVSAT_BU  = 2157,
2173
    XVSAT_D = 2158,
2174
    XVSAT_DU  = 2159,
2175
    XVSAT_H = 2160,
2176
    XVSAT_HU  = 2161,
2177
    XVSAT_W = 2162,
2178
    XVSAT_WU  = 2163,
2179
    XVSEQI_B  = 2164,
2180
    XVSEQI_D  = 2165,
2181
    XVSEQI_H  = 2166,
2182
    XVSEQI_W  = 2167,
2183
    XVSEQ_B = 2168,
2184
    XVSEQ_D = 2169,
2185
    XVSEQ_H = 2170,
2186
    XVSEQ_W = 2171,
2187
    XVSETALLNEZ_B = 2172,
2188
    XVSETALLNEZ_D = 2173,
2189
    XVSETALLNEZ_H = 2174,
2190
    XVSETALLNEZ_W = 2175,
2191
    XVSETANYEQZ_B = 2176,
2192
    XVSETANYEQZ_D = 2177,
2193
    XVSETANYEQZ_H = 2178,
2194
    XVSETANYEQZ_W = 2179,
2195
    XVSETEQZ_V  = 2180,
2196
    XVSETNEZ_V  = 2181,
2197
    XVSHUF4I_B  = 2182,
2198
    XVSHUF4I_D  = 2183,
2199
    XVSHUF4I_H  = 2184,
2200
    XVSHUF4I_W  = 2185,
2201
    XVSHUF_B  = 2186,
2202
    XVSHUF_D  = 2187,
2203
    XVSHUF_H  = 2188,
2204
    XVSHUF_W  = 2189,
2205
    XVSIGNCOV_B = 2190,
2206
    XVSIGNCOV_D = 2191,
2207
    XVSIGNCOV_H = 2192,
2208
    XVSIGNCOV_W = 2193,
2209
    XVSLEI_B  = 2194,
2210
    XVSLEI_BU = 2195,
2211
    XVSLEI_D  = 2196,
2212
    XVSLEI_DU = 2197,
2213
    XVSLEI_H  = 2198,
2214
    XVSLEI_HU = 2199,
2215
    XVSLEI_W  = 2200,
2216
    XVSLEI_WU = 2201,
2217
    XVSLE_B = 2202,
2218
    XVSLE_BU  = 2203,
2219
    XVSLE_D = 2204,
2220
    XVSLE_DU  = 2205,
2221
    XVSLE_H = 2206,
2222
    XVSLE_HU  = 2207,
2223
    XVSLE_W = 2208,
2224
    XVSLE_WU  = 2209,
2225
    XVSLLI_B  = 2210,
2226
    XVSLLI_D  = 2211,
2227
    XVSLLI_H  = 2212,
2228
    XVSLLI_W  = 2213,
2229
    XVSLLWIL_DU_WU  = 2214,
2230
    XVSLLWIL_D_W  = 2215,
2231
    XVSLLWIL_HU_BU  = 2216,
2232
    XVSLLWIL_H_B  = 2217,
2233
    XVSLLWIL_WU_HU  = 2218,
2234
    XVSLLWIL_W_H  = 2219,
2235
    XVSLL_B = 2220,
2236
    XVSLL_D = 2221,
2237
    XVSLL_H = 2222,
2238
    XVSLL_W = 2223,
2239
    XVSLTI_B  = 2224,
2240
    XVSLTI_BU = 2225,
2241
    XVSLTI_D  = 2226,
2242
    XVSLTI_DU = 2227,
2243
    XVSLTI_H  = 2228,
2244
    XVSLTI_HU = 2229,
2245
    XVSLTI_W  = 2230,
2246
    XVSLTI_WU = 2231,
2247
    XVSLT_B = 2232,
2248
    XVSLT_BU  = 2233,
2249
    XVSLT_D = 2234,
2250
    XVSLT_DU  = 2235,
2251
    XVSLT_H = 2236,
2252
    XVSLT_HU  = 2237,
2253
    XVSLT_W = 2238,
2254
    XVSLT_WU  = 2239,
2255
    XVSRAI_B  = 2240,
2256
    XVSRAI_D  = 2241,
2257
    XVSRAI_H  = 2242,
2258
    XVSRAI_W  = 2243,
2259
    XVSRANI_B_H = 2244,
2260
    XVSRANI_D_Q = 2245,
2261
    XVSRANI_H_W = 2246,
2262
    XVSRANI_W_D = 2247,
2263
    XVSRAN_B_H  = 2248,
2264
    XVSRAN_H_W  = 2249,
2265
    XVSRAN_W_D  = 2250,
2266
    XVSRARI_B = 2251,
2267
    XVSRARI_D = 2252,
2268
    XVSRARI_H = 2253,
2269
    XVSRARI_W = 2254,
2270
    XVSRARNI_B_H  = 2255,
2271
    XVSRARNI_D_Q  = 2256,
2272
    XVSRARNI_H_W  = 2257,
2273
    XVSRARNI_W_D  = 2258,
2274
    XVSRARN_B_H = 2259,
2275
    XVSRARN_H_W = 2260,
2276
    XVSRARN_W_D = 2261,
2277
    XVSRAR_B  = 2262,
2278
    XVSRAR_D  = 2263,
2279
    XVSRAR_H  = 2264,
2280
    XVSRAR_W  = 2265,
2281
    XVSRA_B = 2266,
2282
    XVSRA_D = 2267,
2283
    XVSRA_H = 2268,
2284
    XVSRA_W = 2269,
2285
    XVSRLI_B  = 2270,
2286
    XVSRLI_D  = 2271,
2287
    XVSRLI_H  = 2272,
2288
    XVSRLI_W  = 2273,
2289
    XVSRLNI_B_H = 2274,
2290
    XVSRLNI_D_Q = 2275,
2291
    XVSRLNI_H_W = 2276,
2292
    XVSRLNI_W_D = 2277,
2293
    XVSRLN_B_H  = 2278,
2294
    XVSRLN_H_W  = 2279,
2295
    XVSRLN_W_D  = 2280,
2296
    XVSRLRI_B = 2281,
2297
    XVSRLRI_D = 2282,
2298
    XVSRLRI_H = 2283,
2299
    XVSRLRI_W = 2284,
2300
    XVSRLRNI_B_H  = 2285,
2301
    XVSRLRNI_D_Q  = 2286,
2302
    XVSRLRNI_H_W  = 2287,
2303
    XVSRLRNI_W_D  = 2288,
2304
    XVSRLRN_B_H = 2289,
2305
    XVSRLRN_H_W = 2290,
2306
    XVSRLRN_W_D = 2291,
2307
    XVSRLR_B  = 2292,
2308
    XVSRLR_D  = 2293,
2309
    XVSRLR_H  = 2294,
2310
    XVSRLR_W  = 2295,
2311
    XVSRL_B = 2296,
2312
    XVSRL_D = 2297,
2313
    XVSRL_H = 2298,
2314
    XVSRL_W = 2299,
2315
    XVSSRANI_BU_H = 2300,
2316
    XVSSRANI_B_H  = 2301,
2317
    XVSSRANI_DU_Q = 2302,
2318
    XVSSRANI_D_Q  = 2303,
2319
    XVSSRANI_HU_W = 2304,
2320
    XVSSRANI_H_W  = 2305,
2321
    XVSSRANI_WU_D = 2306,
2322
    XVSSRANI_W_D  = 2307,
2323
    XVSSRAN_BU_H  = 2308,
2324
    XVSSRAN_B_H = 2309,
2325
    XVSSRAN_HU_W  = 2310,
2326
    XVSSRAN_H_W = 2311,
2327
    XVSSRAN_WU_D  = 2312,
2328
    XVSSRAN_W_D = 2313,
2329
    XVSSRARNI_BU_H  = 2314,
2330
    XVSSRARNI_B_H = 2315,
2331
    XVSSRARNI_DU_Q  = 2316,
2332
    XVSSRARNI_D_Q = 2317,
2333
    XVSSRARNI_HU_W  = 2318,
2334
    XVSSRARNI_H_W = 2319,
2335
    XVSSRARNI_WU_D  = 2320,
2336
    XVSSRARNI_W_D = 2321,
2337
    XVSSRARN_BU_H = 2322,
2338
    XVSSRARN_B_H  = 2323,
2339
    XVSSRARN_HU_W = 2324,
2340
    XVSSRARN_H_W  = 2325,
2341
    XVSSRARN_WU_D = 2326,
2342
    XVSSRARN_W_D  = 2327,
2343
    XVSSRLNI_BU_H = 2328,
2344
    XVSSRLNI_B_H  = 2329,
2345
    XVSSRLNI_DU_Q = 2330,
2346
    XVSSRLNI_D_Q  = 2331,
2347
    XVSSRLNI_HU_W = 2332,
2348
    XVSSRLNI_H_W  = 2333,
2349
    XVSSRLNI_WU_D = 2334,
2350
    XVSSRLNI_W_D  = 2335,
2351
    XVSSRLN_BU_H  = 2336,
2352
    XVSSRLN_B_H = 2337,
2353
    XVSSRLN_HU_W  = 2338,
2354
    XVSSRLN_H_W = 2339,
2355
    XVSSRLN_WU_D  = 2340,
2356
    XVSSRLN_W_D = 2341,
2357
    XVSSRLRNI_BU_H  = 2342,
2358
    XVSSRLRNI_B_H = 2343,
2359
    XVSSRLRNI_DU_Q  = 2344,
2360
    XVSSRLRNI_D_Q = 2345,
2361
    XVSSRLRNI_HU_W  = 2346,
2362
    XVSSRLRNI_H_W = 2347,
2363
    XVSSRLRNI_WU_D  = 2348,
2364
    XVSSRLRNI_W_D = 2349,
2365
    XVSSRLRN_BU_H = 2350,
2366
    XVSSRLRN_B_H  = 2351,
2367
    XVSSRLRN_HU_W = 2352,
2368
    XVSSRLRN_H_W  = 2353,
2369
    XVSSRLRN_WU_D = 2354,
2370
    XVSSRLRN_W_D  = 2355,
2371
    XVSSUB_B  = 2356,
2372
    XVSSUB_BU = 2357,
2373
    XVSSUB_D  = 2358,
2374
    XVSSUB_DU = 2359,
2375
    XVSSUB_H  = 2360,
2376
    XVSSUB_HU = 2361,
2377
    XVSSUB_W  = 2362,
2378
    XVSSUB_WU = 2363,
2379
    XVST  = 2364,
2380
    XVSTELM_B = 2365,
2381
    XVSTELM_D = 2366,
2382
    XVSTELM_H = 2367,
2383
    XVSTELM_W = 2368,
2384
    XVSTX = 2369,
2385
    XVSUBI_BU = 2370,
2386
    XVSUBI_DU = 2371,
2387
    XVSUBI_HU = 2372,
2388
    XVSUBI_WU = 2373,
2389
    XVSUBWEV_D_W  = 2374,
2390
    XVSUBWEV_D_WU = 2375,
2391
    XVSUBWEV_H_B  = 2376,
2392
    XVSUBWEV_H_BU = 2377,
2393
    XVSUBWEV_Q_D  = 2378,
2394
    XVSUBWEV_Q_DU = 2379,
2395
    XVSUBWEV_W_H  = 2380,
2396
    XVSUBWEV_W_HU = 2381,
2397
    XVSUBWOD_D_W  = 2382,
2398
    XVSUBWOD_D_WU = 2383,
2399
    XVSUBWOD_H_B  = 2384,
2400
    XVSUBWOD_H_BU = 2385,
2401
    XVSUBWOD_Q_D  = 2386,
2402
    XVSUBWOD_Q_DU = 2387,
2403
    XVSUBWOD_W_H  = 2388,
2404
    XVSUBWOD_W_HU = 2389,
2405
    XVSUB_B = 2390,
2406
    XVSUB_D = 2391,
2407
    XVSUB_H = 2392,
2408
    XVSUB_Q = 2393,
2409
    XVSUB_W = 2394,
2410
    XVXORI_B  = 2395,
2411
    XVXOR_V = 2396,
2412
    INSTRUCTION_LIST_END = 2397
2413
  };
2414
2415
} // end namespace LoongArch
2416
} // end namespace llvm
2417
#endif // GET_INSTRINFO_ENUM
2418
2419
#ifdef GET_INSTRINFO_SCHED_ENUM
2420
#undef GET_INSTRINFO_SCHED_ENUM
2421
namespace llvm {
2422
2423
namespace LoongArch {
2424
namespace Sched {
2425
  enum {
2426
    NoInstrModel  = 0,
2427
    SCHED_LIST_END = 1
2428
  };
2429
} // end namespace Sched
2430
} // end namespace LoongArch
2431
} // end namespace llvm
2432
#endif // GET_INSTRINFO_SCHED_ENUM
2433
2434
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2435
namespace llvm {
2436
2437
struct LoongArchInstrTable {
2438
  MCInstrDesc Insts[2397];
2439
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
2440
  MCOperandInfo OperandInfo[405];
2441
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
2442
  MCPhysReg ImplicitOps[12];
2443
};
2444
2445
} // end namespace llvm
2446
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
2447
2448
#ifdef GET_INSTRINFO_MC_DESC
2449
#undef GET_INSTRINFO_MC_DESC
2450
namespace llvm {
2451
2452
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
2453
static constexpr unsigned LoongArchImpOpBase = sizeof LoongArchInstrTable::OperandInfo / (sizeof(MCPhysReg));
2454
2455
extern const LoongArchInstrTable LoongArchDescs = {
2456
  {
2457
    { 2396, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2396 = XVXOR_V
2458
    { 2395, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2395 = XVXORI_B
2459
    { 2394, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2394 = XVSUB_W
2460
    { 2393, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2393 = XVSUB_Q
2461
    { 2392, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2392 = XVSUB_H
2462
    { 2391, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2391 = XVSUB_D
2463
    { 2390, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2390 = XVSUB_B
2464
    { 2389, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2389 = XVSUBWOD_W_HU
2465
    { 2388, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2388 = XVSUBWOD_W_H
2466
    { 2387, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2387 = XVSUBWOD_Q_DU
2467
    { 2386, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2386 = XVSUBWOD_Q_D
2468
    { 2385, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2385 = XVSUBWOD_H_BU
2469
    { 2384, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2384 = XVSUBWOD_H_B
2470
    { 2383, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2383 = XVSUBWOD_D_WU
2471
    { 2382, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2382 = XVSUBWOD_D_W
2472
    { 2381, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2381 = XVSUBWEV_W_HU
2473
    { 2380, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2380 = XVSUBWEV_W_H
2474
    { 2379, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2379 = XVSUBWEV_Q_DU
2475
    { 2378, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2378 = XVSUBWEV_Q_D
2476
    { 2377, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2377 = XVSUBWEV_H_BU
2477
    { 2376, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2376 = XVSUBWEV_H_B
2478
    { 2375, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2375 = XVSUBWEV_D_WU
2479
    { 2374, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2374 = XVSUBWEV_D_W
2480
    { 2373, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2373 = XVSUBI_WU
2481
    { 2372, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2372 = XVSUBI_HU
2482
    { 2371, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2371 = XVSUBI_DU
2483
    { 2370, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2370 = XVSUBI_BU
2484
    { 2369, 3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 388,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #2369 = XVSTX
2485
    { 2368, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 401,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #2368 = XVSTELM_W
2486
    { 2367, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 401,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #2367 = XVSTELM_H
2487
    { 2366, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 401,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #2366 = XVSTELM_D
2488
    { 2365, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 401,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #2365 = XVSTELM_B
2489
    { 2364, 3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 385,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #2364 = XVST
2490
    { 2363, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2363 = XVSSUB_WU
2491
    { 2362, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2362 = XVSSUB_W
2492
    { 2361, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2361 = XVSSUB_HU
2493
    { 2360, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2360 = XVSSUB_H
2494
    { 2359, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2359 = XVSSUB_DU
2495
    { 2358, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2358 = XVSSUB_D
2496
    { 2357, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2357 = XVSSUB_BU
2497
    { 2356, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2356 = XVSSUB_B
2498
    { 2355, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2355 = XVSSRLRN_W_D
2499
    { 2354, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2354 = XVSSRLRN_WU_D
2500
    { 2353, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2353 = XVSSRLRN_H_W
2501
    { 2352, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2352 = XVSSRLRN_HU_W
2502
    { 2351, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2351 = XVSSRLRN_B_H
2503
    { 2350, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2350 = XVSSRLRN_BU_H
2504
    { 2349, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2349 = XVSSRLRNI_W_D
2505
    { 2348, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2348 = XVSSRLRNI_WU_D
2506
    { 2347, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2347 = XVSSRLRNI_H_W
2507
    { 2346, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2346 = XVSSRLRNI_HU_W
2508
    { 2345, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2345 = XVSSRLRNI_D_Q
2509
    { 2344, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2344 = XVSSRLRNI_DU_Q
2510
    { 2343, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2343 = XVSSRLRNI_B_H
2511
    { 2342, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2342 = XVSSRLRNI_BU_H
2512
    { 2341, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2341 = XVSSRLN_W_D
2513
    { 2340, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2340 = XVSSRLN_WU_D
2514
    { 2339, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2339 = XVSSRLN_H_W
2515
    { 2338, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2338 = XVSSRLN_HU_W
2516
    { 2337, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2337 = XVSSRLN_B_H
2517
    { 2336, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2336 = XVSSRLN_BU_H
2518
    { 2335, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2335 = XVSSRLNI_W_D
2519
    { 2334, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2334 = XVSSRLNI_WU_D
2520
    { 2333, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2333 = XVSSRLNI_H_W
2521
    { 2332, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2332 = XVSSRLNI_HU_W
2522
    { 2331, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2331 = XVSSRLNI_D_Q
2523
    { 2330, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2330 = XVSSRLNI_DU_Q
2524
    { 2329, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2329 = XVSSRLNI_B_H
2525
    { 2328, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2328 = XVSSRLNI_BU_H
2526
    { 2327, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2327 = XVSSRARN_W_D
2527
    { 2326, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2326 = XVSSRARN_WU_D
2528
    { 2325, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2325 = XVSSRARN_H_W
2529
    { 2324, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2324 = XVSSRARN_HU_W
2530
    { 2323, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2323 = XVSSRARN_B_H
2531
    { 2322, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2322 = XVSSRARN_BU_H
2532
    { 2321, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2321 = XVSSRARNI_W_D
2533
    { 2320, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2320 = XVSSRARNI_WU_D
2534
    { 2319, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2319 = XVSSRARNI_H_W
2535
    { 2318, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2318 = XVSSRARNI_HU_W
2536
    { 2317, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2317 = XVSSRARNI_D_Q
2537
    { 2316, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2316 = XVSSRARNI_DU_Q
2538
    { 2315, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2315 = XVSSRARNI_B_H
2539
    { 2314, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2314 = XVSSRARNI_BU_H
2540
    { 2313, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2313 = XVSSRAN_W_D
2541
    { 2312, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2312 = XVSSRAN_WU_D
2542
    { 2311, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2311 = XVSSRAN_H_W
2543
    { 2310, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2310 = XVSSRAN_HU_W
2544
    { 2309, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2309 = XVSSRAN_B_H
2545
    { 2308, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2308 = XVSSRAN_BU_H
2546
    { 2307, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2307 = XVSSRANI_W_D
2547
    { 2306, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2306 = XVSSRANI_WU_D
2548
    { 2305, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2305 = XVSSRANI_H_W
2549
    { 2304, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2304 = XVSSRANI_HU_W
2550
    { 2303, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2303 = XVSSRANI_D_Q
2551
    { 2302, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2302 = XVSSRANI_DU_Q
2552
    { 2301, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2301 = XVSSRANI_B_H
2553
    { 2300, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2300 = XVSSRANI_BU_H
2554
    { 2299, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2299 = XVSRL_W
2555
    { 2298, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2298 = XVSRL_H
2556
    { 2297, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2297 = XVSRL_D
2557
    { 2296, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2296 = XVSRL_B
2558
    { 2295, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2295 = XVSRLR_W
2559
    { 2294, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2294 = XVSRLR_H
2560
    { 2293, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2293 = XVSRLR_D
2561
    { 2292, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2292 = XVSRLR_B
2562
    { 2291, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2291 = XVSRLRN_W_D
2563
    { 2290, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2290 = XVSRLRN_H_W
2564
    { 2289, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2289 = XVSRLRN_B_H
2565
    { 2288, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2288 = XVSRLRNI_W_D
2566
    { 2287, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2287 = XVSRLRNI_H_W
2567
    { 2286, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2286 = XVSRLRNI_D_Q
2568
    { 2285, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2285 = XVSRLRNI_B_H
2569
    { 2284, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2284 = XVSRLRI_W
2570
    { 2283, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2283 = XVSRLRI_H
2571
    { 2282, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2282 = XVSRLRI_D
2572
    { 2281, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2281 = XVSRLRI_B
2573
    { 2280, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2280 = XVSRLN_W_D
2574
    { 2279, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2279 = XVSRLN_H_W
2575
    { 2278, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2278 = XVSRLN_B_H
2576
    { 2277, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2277 = XVSRLNI_W_D
2577
    { 2276, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2276 = XVSRLNI_H_W
2578
    { 2275, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2275 = XVSRLNI_D_Q
2579
    { 2274, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2274 = XVSRLNI_B_H
2580
    { 2273, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2273 = XVSRLI_W
2581
    { 2272, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2272 = XVSRLI_H
2582
    { 2271, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2271 = XVSRLI_D
2583
    { 2270, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2270 = XVSRLI_B
2584
    { 2269, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2269 = XVSRA_W
2585
    { 2268, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2268 = XVSRA_H
2586
    { 2267, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2267 = XVSRA_D
2587
    { 2266, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2266 = XVSRA_B
2588
    { 2265, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2265 = XVSRAR_W
2589
    { 2264, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2264 = XVSRAR_H
2590
    { 2263, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2263 = XVSRAR_D
2591
    { 2262, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2262 = XVSRAR_B
2592
    { 2261, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2261 = XVSRARN_W_D
2593
    { 2260, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2260 = XVSRARN_H_W
2594
    { 2259, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2259 = XVSRARN_B_H
2595
    { 2258, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2258 = XVSRARNI_W_D
2596
    { 2257, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2257 = XVSRARNI_H_W
2597
    { 2256, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2256 = XVSRARNI_D_Q
2598
    { 2255, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2255 = XVSRARNI_B_H
2599
    { 2254, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2254 = XVSRARI_W
2600
    { 2253, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2253 = XVSRARI_H
2601
    { 2252, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2252 = XVSRARI_D
2602
    { 2251, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2251 = XVSRARI_B
2603
    { 2250, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2250 = XVSRAN_W_D
2604
    { 2249, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2249 = XVSRAN_H_W
2605
    { 2248, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2248 = XVSRAN_B_H
2606
    { 2247, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2247 = XVSRANI_W_D
2607
    { 2246, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2246 = XVSRANI_H_W
2608
    { 2245, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2245 = XVSRANI_D_Q
2609
    { 2244, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2244 = XVSRANI_B_H
2610
    { 2243, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2243 = XVSRAI_W
2611
    { 2242, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2242 = XVSRAI_H
2612
    { 2241, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2241 = XVSRAI_D
2613
    { 2240, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2240 = XVSRAI_B
2614
    { 2239, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2239 = XVSLT_WU
2615
    { 2238, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2238 = XVSLT_W
2616
    { 2237, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2237 = XVSLT_HU
2617
    { 2236, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2236 = XVSLT_H
2618
    { 2235, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2235 = XVSLT_DU
2619
    { 2234, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2234 = XVSLT_D
2620
    { 2233, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2233 = XVSLT_BU
2621
    { 2232, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2232 = XVSLT_B
2622
    { 2231, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2231 = XVSLTI_WU
2623
    { 2230, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2230 = XVSLTI_W
2624
    { 2229, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2229 = XVSLTI_HU
2625
    { 2228, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2228 = XVSLTI_H
2626
    { 2227, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2227 = XVSLTI_DU
2627
    { 2226, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2226 = XVSLTI_D
2628
    { 2225, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2225 = XVSLTI_BU
2629
    { 2224, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2224 = XVSLTI_B
2630
    { 2223, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2223 = XVSLL_W
2631
    { 2222, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2222 = XVSLL_H
2632
    { 2221, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2221 = XVSLL_D
2633
    { 2220, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2220 = XVSLL_B
2634
    { 2219, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2219 = XVSLLWIL_W_H
2635
    { 2218, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2218 = XVSLLWIL_WU_HU
2636
    { 2217, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2217 = XVSLLWIL_H_B
2637
    { 2216, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2216 = XVSLLWIL_HU_BU
2638
    { 2215, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2215 = XVSLLWIL_D_W
2639
    { 2214, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2214 = XVSLLWIL_DU_WU
2640
    { 2213, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2213 = XVSLLI_W
2641
    { 2212, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2212 = XVSLLI_H
2642
    { 2211, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2211 = XVSLLI_D
2643
    { 2210, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2210 = XVSLLI_B
2644
    { 2209, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2209 = XVSLE_WU
2645
    { 2208, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2208 = XVSLE_W
2646
    { 2207, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2207 = XVSLE_HU
2647
    { 2206, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2206 = XVSLE_H
2648
    { 2205, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2205 = XVSLE_DU
2649
    { 2204, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2204 = XVSLE_D
2650
    { 2203, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2203 = XVSLE_BU
2651
    { 2202, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2202 = XVSLE_B
2652
    { 2201, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2201 = XVSLEI_WU
2653
    { 2200, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2200 = XVSLEI_W
2654
    { 2199, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2199 = XVSLEI_HU
2655
    { 2198, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2198 = XVSLEI_H
2656
    { 2197, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2197 = XVSLEI_DU
2657
    { 2196, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2196 = XVSLEI_D
2658
    { 2195, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2195 = XVSLEI_BU
2659
    { 2194, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2194 = XVSLEI_B
2660
    { 2193, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2193 = XVSIGNCOV_W
2661
    { 2192, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2192 = XVSIGNCOV_H
2662
    { 2191, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2191 = XVSIGNCOV_D
2663
    { 2190, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2190 = XVSIGNCOV_B
2664
    { 2189, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2189 = XVSHUF_W
2665
    { 2188, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2188 = XVSHUF_H
2666
    { 2187, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2187 = XVSHUF_D
2667
    { 2186, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #2186 = XVSHUF_B
2668
    { 2185, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2185 = XVSHUF4I_W
2669
    { 2184, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2184 = XVSHUF4I_H
2670
    { 2183, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2183 = XVSHUF4I_D
2671
    { 2182, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2182 = XVSHUF4I_B
2672
    { 2181, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2181 = XVSETNEZ_V
2673
    { 2180, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2180 = XVSETEQZ_V
2674
    { 2179, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2179 = XVSETANYEQZ_W
2675
    { 2178, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2178 = XVSETANYEQZ_H
2676
    { 2177, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2177 = XVSETANYEQZ_D
2677
    { 2176, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2176 = XVSETANYEQZ_B
2678
    { 2175, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2175 = XVSETALLNEZ_W
2679
    { 2174, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2174 = XVSETALLNEZ_H
2680
    { 2173, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2173 = XVSETALLNEZ_D
2681
    { 2172, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 399,  0, 0x0ULL },  // Inst #2172 = XVSETALLNEZ_B
2682
    { 2171, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2171 = XVSEQ_W
2683
    { 2170, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2170 = XVSEQ_H
2684
    { 2169, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2169 = XVSEQ_D
2685
    { 2168, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2168 = XVSEQ_B
2686
    { 2167, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2167 = XVSEQI_W
2687
    { 2166, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2166 = XVSEQI_H
2688
    { 2165, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2165 = XVSEQI_D
2689
    { 2164, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2164 = XVSEQI_B
2690
    { 2163, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2163 = XVSAT_WU
2691
    { 2162, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2162 = XVSAT_W
2692
    { 2161, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2161 = XVSAT_HU
2693
    { 2160, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2160 = XVSAT_H
2694
    { 2159, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2159 = XVSAT_DU
2695
    { 2158, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2158 = XVSAT_D
2696
    { 2157, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2157 = XVSAT_BU
2697
    { 2156, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2156 = XVSAT_B
2698
    { 2155, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2155 = XVSADD_WU
2699
    { 2154, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2154 = XVSADD_W
2700
    { 2153, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2153 = XVSADD_HU
2701
    { 2152, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2152 = XVSADD_H
2702
    { 2151, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2151 = XVSADD_DU
2703
    { 2150, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2150 = XVSADD_D
2704
    { 2149, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2149 = XVSADD_BU
2705
    { 2148, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2148 = XVSADD_B
2706
    { 2147, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2147 = XVROTR_W
2707
    { 2146, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2146 = XVROTR_H
2708
    { 2145, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2145 = XVROTR_D
2709
    { 2144, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2144 = XVROTR_B
2710
    { 2143, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2143 = XVROTRI_W
2711
    { 2142, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2142 = XVROTRI_H
2712
    { 2141, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2141 = XVROTRI_D
2713
    { 2140, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2140 = XVROTRI_B
2714
    { 2139, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 396,  0, 0x0ULL },  // Inst #2139 = XVREPLVE_W
2715
    { 2138, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 396,  0, 0x0ULL },  // Inst #2138 = XVREPLVE_H
2716
    { 2137, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 396,  0, 0x0ULL },  // Inst #2137 = XVREPLVE_D
2717
    { 2136, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 396,  0, 0x0ULL },  // Inst #2136 = XVREPLVE_B
2718
    { 2135, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2135 = XVREPLVE0_W
2719
    { 2134, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2134 = XVREPLVE0_Q
2720
    { 2133, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2133 = XVREPLVE0_H
2721
    { 2132, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2132 = XVREPLVE0_D
2722
    { 2131, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2131 = XVREPLVE0_B
2723
    { 2130, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 394,  0, 0x0ULL },  // Inst #2130 = XVREPLGR2VR_W
2724
    { 2129, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 394,  0, 0x0ULL },  // Inst #2129 = XVREPLGR2VR_H
2725
    { 2128, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 394,  0, 0x0ULL },  // Inst #2128 = XVREPLGR2VR_D
2726
    { 2127, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 394,  0, 0x0ULL },  // Inst #2127 = XVREPLGR2VR_B
2727
    { 2126, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2126 = XVREPL128VEI_W
2728
    { 2125, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2125 = XVREPL128VEI_H
2729
    { 2124, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2124 = XVREPL128VEI_D
2730
    { 2123, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2123 = XVREPL128VEI_B
2731
    { 2122, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2122 = XVPICKVE_W
2732
    { 2121, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2121 = XVPICKVE_D
2733
    { 2120, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 391,  0, 0x0ULL },  // Inst #2120 = XVPICKVE2GR_WU
2734
    { 2119, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 391,  0, 0x0ULL },  // Inst #2119 = XVPICKVE2GR_W
2735
    { 2118, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 391,  0, 0x0ULL },  // Inst #2118 = XVPICKVE2GR_DU
2736
    { 2117, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 391,  0, 0x0ULL },  // Inst #2117 = XVPICKVE2GR_D
2737
    { 2116, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2116 = XVPICKOD_W
2738
    { 2115, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2115 = XVPICKOD_H
2739
    { 2114, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2114 = XVPICKOD_D
2740
    { 2113, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2113 = XVPICKOD_B
2741
    { 2112, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2112 = XVPICKEV_W
2742
    { 2111, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2111 = XVPICKEV_H
2743
    { 2110, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2110 = XVPICKEV_D
2744
    { 2109, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2109 = XVPICKEV_B
2745
    { 2108, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2108 = XVPERM_W
2746
    { 2107, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2107 = XVPERMI_W
2747
    { 2106, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #2106 = XVPERMI_Q
2748
    { 2105, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2105 = XVPERMI_D
2749
    { 2104, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2104 = XVPCNT_W
2750
    { 2103, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2103 = XVPCNT_H
2751
    { 2102, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2102 = XVPCNT_D
2752
    { 2101, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2101 = XVPCNT_B
2753
    { 2100, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2100 = XVPACKOD_W
2754
    { 2099, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2099 = XVPACKOD_H
2755
    { 2098, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2098 = XVPACKOD_D
2756
    { 2097, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2097 = XVPACKOD_B
2757
    { 2096, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2096 = XVPACKEV_W
2758
    { 2095, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2095 = XVPACKEV_H
2759
    { 2094, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2094 = XVPACKEV_D
2760
    { 2093, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2093 = XVPACKEV_B
2761
    { 2092, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2092 = XVOR_V
2762
    { 2091, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2091 = XVORN_V
2763
    { 2090, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2090 = XVORI_B
2764
    { 2089, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2089 = XVNOR_V
2765
    { 2088, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2088 = XVNORI_B
2766
    { 2087, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2087 = XVNEG_W
2767
    { 2086, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2086 = XVNEG_H
2768
    { 2085, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2085 = XVNEG_D
2769
    { 2084, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2084 = XVNEG_B
2770
    { 2083, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2083 = XVMUL_W
2771
    { 2082, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2082 = XVMUL_H
2772
    { 2081, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2081 = XVMUL_D
2773
    { 2080, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2080 = XVMUL_B
2774
    { 2079, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2079 = XVMULWOD_W_HU_H
2775
    { 2078, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2078 = XVMULWOD_W_HU
2776
    { 2077, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2077 = XVMULWOD_W_H
2777
    { 2076, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2076 = XVMULWOD_Q_DU_D
2778
    { 2075, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2075 = XVMULWOD_Q_DU
2779
    { 2074, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2074 = XVMULWOD_Q_D
2780
    { 2073, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2073 = XVMULWOD_H_BU_B
2781
    { 2072, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2072 = XVMULWOD_H_BU
2782
    { 2071, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2071 = XVMULWOD_H_B
2783
    { 2070, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2070 = XVMULWOD_D_WU_W
2784
    { 2069, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2069 = XVMULWOD_D_WU
2785
    { 2068, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2068 = XVMULWOD_D_W
2786
    { 2067, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2067 = XVMULWEV_W_HU_H
2787
    { 2066, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2066 = XVMULWEV_W_HU
2788
    { 2065, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2065 = XVMULWEV_W_H
2789
    { 2064, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2064 = XVMULWEV_Q_DU_D
2790
    { 2063, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2063 = XVMULWEV_Q_DU
2791
    { 2062, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2062 = XVMULWEV_Q_D
2792
    { 2061, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2061 = XVMULWEV_H_BU_B
2793
    { 2060, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2060 = XVMULWEV_H_BU
2794
    { 2059, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2059 = XVMULWEV_H_B
2795
    { 2058, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2058 = XVMULWEV_D_WU_W
2796
    { 2057, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2057 = XVMULWEV_D_WU
2797
    { 2056, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2056 = XVMULWEV_D_W
2798
    { 2055, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2055 = XVMUH_WU
2799
    { 2054, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2054 = XVMUH_W
2800
    { 2053, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2053 = XVMUH_HU
2801
    { 2052, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2052 = XVMUH_H
2802
    { 2051, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2051 = XVMUH_DU
2803
    { 2050, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2050 = XVMUH_D
2804
    { 2049, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2049 = XVMUH_BU
2805
    { 2048, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2048 = XVMUH_B
2806
    { 2047, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2047 = XVMSUB_W
2807
    { 2046, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2046 = XVMSUB_H
2808
    { 2045, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2045 = XVMSUB_D
2809
    { 2044, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #2044 = XVMSUB_B
2810
    { 2043, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2043 = XVMSKNZ_B
2811
    { 2042, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2042 = XVMSKLTZ_W
2812
    { 2041, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2041 = XVMSKLTZ_H
2813
    { 2040, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2040 = XVMSKLTZ_D
2814
    { 2039, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2039 = XVMSKLTZ_B
2815
    { 2038, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #2038 = XVMSKGEZ_B
2816
    { 2037, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2037 = XVMOD_WU
2817
    { 2036, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2036 = XVMOD_W
2818
    { 2035, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2035 = XVMOD_HU
2819
    { 2034, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2034 = XVMOD_H
2820
    { 2033, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2033 = XVMOD_DU
2821
    { 2032, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2032 = XVMOD_D
2822
    { 2031, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2031 = XVMOD_BU
2823
    { 2030, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2030 = XVMOD_B
2824
    { 2029, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2029 = XVMIN_WU
2825
    { 2028, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2028 = XVMIN_W
2826
    { 2027, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2027 = XVMIN_HU
2827
    { 2026, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2026 = XVMIN_H
2828
    { 2025, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2025 = XVMIN_DU
2829
    { 2024, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2024 = XVMIN_D
2830
    { 2023, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2023 = XVMIN_BU
2831
    { 2022, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2022 = XVMIN_B
2832
    { 2021, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2021 = XVMINI_WU
2833
    { 2020, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2020 = XVMINI_W
2834
    { 2019, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2019 = XVMINI_HU
2835
    { 2018, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2018 = XVMINI_H
2836
    { 2017, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2017 = XVMINI_DU
2837
    { 2016, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2016 = XVMINI_D
2838
    { 2015, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2015 = XVMINI_BU
2839
    { 2014, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2014 = XVMINI_B
2840
    { 2013, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2013 = XVMAX_WU
2841
    { 2012, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2012 = XVMAX_W
2842
    { 2011, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2011 = XVMAX_HU
2843
    { 2010, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2010 = XVMAX_H
2844
    { 2009, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2009 = XVMAX_DU
2845
    { 2008, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2008 = XVMAX_D
2846
    { 2007, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2007 = XVMAX_BU
2847
    { 2006, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #2006 = XVMAX_B
2848
    { 2005, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2005 = XVMAXI_WU
2849
    { 2004, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2004 = XVMAXI_W
2850
    { 2003, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2003 = XVMAXI_HU
2851
    { 2002, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2002 = XVMAXI_H
2852
    { 2001, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2001 = XVMAXI_DU
2853
    { 2000, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #2000 = XVMAXI_D
2854
    { 1999, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1999 = XVMAXI_BU
2855
    { 1998, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1998 = XVMAXI_B
2856
    { 1997, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1997 = XVMADD_W
2857
    { 1996, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1996 = XVMADD_H
2858
    { 1995, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1995 = XVMADD_D
2859
    { 1994, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1994 = XVMADD_B
2860
    { 1993, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1993 = XVMADDWOD_W_HU_H
2861
    { 1992, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1992 = XVMADDWOD_W_HU
2862
    { 1991, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1991 = XVMADDWOD_W_H
2863
    { 1990, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1990 = XVMADDWOD_Q_DU_D
2864
    { 1989, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1989 = XVMADDWOD_Q_DU
2865
    { 1988, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1988 = XVMADDWOD_Q_D
2866
    { 1987, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1987 = XVMADDWOD_H_BU_B
2867
    { 1986, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1986 = XVMADDWOD_H_BU
2868
    { 1985, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1985 = XVMADDWOD_H_B
2869
    { 1984, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1984 = XVMADDWOD_D_WU_W
2870
    { 1983, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1983 = XVMADDWOD_D_WU
2871
    { 1982, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1982 = XVMADDWOD_D_W
2872
    { 1981, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1981 = XVMADDWEV_W_HU_H
2873
    { 1980, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1980 = XVMADDWEV_W_HU
2874
    { 1979, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1979 = XVMADDWEV_W_H
2875
    { 1978, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1978 = XVMADDWEV_Q_DU_D
2876
    { 1977, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1977 = XVMADDWEV_Q_DU
2877
    { 1976, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1976 = XVMADDWEV_Q_D
2878
    { 1975, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1975 = XVMADDWEV_H_BU_B
2879
    { 1974, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1974 = XVMADDWEV_H_BU
2880
    { 1973, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1973 = XVMADDWEV_H_B
2881
    { 1972, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1972 = XVMADDWEV_D_WU_W
2882
    { 1971, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1971 = XVMADDWEV_D_WU
2883
    { 1970, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1970 = XVMADDWEV_D_W
2884
    { 1969, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 388,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1969 = XVLDX
2885
    { 1968, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 385,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1968 = XVLDREPL_W
2886
    { 1967, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 385,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1967 = XVLDREPL_H
2887
    { 1966, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 385,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1966 = XVLDREPL_D
2888
    { 1965, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 385,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1965 = XVLDREPL_B
2889
    { 1964, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 198,  0, 0x0ULL },  // Inst #1964 = XVLDI
2890
    { 1963, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 385,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1963 = XVLD
2891
    { 1962, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1962 = XVINSVE0_W
2892
    { 1961, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1961 = XVINSVE0_D
2893
    { 1960, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 194,  0, 0x0ULL },  // Inst #1960 = XVINSGR2VR_W
2894
    { 1959, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 194,  0, 0x0ULL },  // Inst #1959 = XVINSGR2VR_D
2895
    { 1958, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1958 = XVILVL_W
2896
    { 1957, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1957 = XVILVL_H
2897
    { 1956, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1956 = XVILVL_D
2898
    { 1955, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1955 = XVILVL_B
2899
    { 1954, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1954 = XVILVH_W
2900
    { 1953, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1953 = XVILVH_H
2901
    { 1952, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1952 = XVILVH_D
2902
    { 1951, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1951 = XVILVH_B
2903
    { 1950, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1950 = XVHSUBW_W_H
2904
    { 1949, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1949 = XVHSUBW_WU_HU
2905
    { 1948, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1948 = XVHSUBW_Q_D
2906
    { 1947, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1947 = XVHSUBW_QU_DU
2907
    { 1946, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1946 = XVHSUBW_H_B
2908
    { 1945, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1945 = XVHSUBW_HU_BU
2909
    { 1944, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1944 = XVHSUBW_D_W
2910
    { 1943, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1943 = XVHSUBW_DU_WU
2911
    { 1942, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1942 = XVHSELI_D
2912
    { 1941, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1941 = XVHADDW_W_H
2913
    { 1940, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1940 = XVHADDW_WU_HU
2914
    { 1939, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1939 = XVHADDW_Q_D
2915
    { 1938, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1938 = XVHADDW_QU_DU
2916
    { 1937, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1937 = XVHADDW_H_B
2917
    { 1936, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1936 = XVHADDW_HU_BU
2918
    { 1935, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1935 = XVHADDW_D_W
2919
    { 1934, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1934 = XVHADDW_DU_WU
2920
    { 1933, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1933 = XVFTINT_W_S
2921
    { 1932, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1932 = XVFTINT_W_D
2922
    { 1931, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1931 = XVFTINT_WU_S
2923
    { 1930, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1930 = XVFTINT_L_D
2924
    { 1929, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1929 = XVFTINT_LU_D
2925
    { 1928, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1928 = XVFTINTRZ_W_S
2926
    { 1927, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1927 = XVFTINTRZ_W_D
2927
    { 1926, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1926 = XVFTINTRZ_WU_S
2928
    { 1925, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1925 = XVFTINTRZ_L_D
2929
    { 1924, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1924 = XVFTINTRZ_LU_D
2930
    { 1923, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1923 = XVFTINTRZL_L_S
2931
    { 1922, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1922 = XVFTINTRZH_L_S
2932
    { 1921, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1921 = XVFTINTRP_W_S
2933
    { 1920, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1920 = XVFTINTRP_W_D
2934
    { 1919, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1919 = XVFTINTRP_L_D
2935
    { 1918, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1918 = XVFTINTRPL_L_S
2936
    { 1917, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1917 = XVFTINTRPH_L_S
2937
    { 1916, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1916 = XVFTINTRNE_W_S
2938
    { 1915, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1915 = XVFTINTRNE_W_D
2939
    { 1914, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1914 = XVFTINTRNE_L_D
2940
    { 1913, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1913 = XVFTINTRNEL_L_S
2941
    { 1912, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1912 = XVFTINTRNEH_L_S
2942
    { 1911, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1911 = XVFTINTRM_W_S
2943
    { 1910, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1910 = XVFTINTRM_W_D
2944
    { 1909, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1909 = XVFTINTRM_L_D
2945
    { 1908, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1908 = XVFTINTRML_L_S
2946
    { 1907, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1907 = XVFTINTRMH_L_S
2947
    { 1906, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1906 = XVFTINTL_L_S
2948
    { 1905, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1905 = XVFTINTH_L_S
2949
    { 1904, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1904 = XVFSUB_S
2950
    { 1903, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1903 = XVFSUB_D
2951
    { 1902, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1902 = XVFSQRT_S
2952
    { 1901, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1901 = XVFSQRT_D
2953
    { 1900, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1900 = XVFRSTP_H
2954
    { 1899, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 381,  0, 0x0ULL },  // Inst #1899 = XVFRSTP_B
2955
    { 1898, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1898 = XVFRSTPI_H
2956
    { 1897, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1897 = XVFRSTPI_B
2957
    { 1896, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1896 = XVFRSQRT_S
2958
    { 1895, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1895 = XVFRSQRT_D
2959
    { 1894, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1894 = XVFRSQRTE_S
2960
    { 1893, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1893 = XVFRSQRTE_D
2961
    { 1892, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1892 = XVFRINT_S
2962
    { 1891, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1891 = XVFRINT_D
2963
    { 1890, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1890 = XVFRINTRZ_S
2964
    { 1889, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1889 = XVFRINTRZ_D
2965
    { 1888, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1888 = XVFRINTRP_S
2966
    { 1887, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1887 = XVFRINTRP_D
2967
    { 1886, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1886 = XVFRINTRNE_S
2968
    { 1885, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1885 = XVFRINTRNE_D
2969
    { 1884, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1884 = XVFRINTRM_S
2970
    { 1883, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1883 = XVFRINTRM_D
2971
    { 1882, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1882 = XVFRECIP_S
2972
    { 1881, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1881 = XVFRECIP_D
2973
    { 1880, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1880 = XVFRECIPE_S
2974
    { 1879, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1879 = XVFRECIPE_D
2975
    { 1878, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1878 = XVFNMSUB_S
2976
    { 1877, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1877 = XVFNMSUB_D
2977
    { 1876, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1876 = XVFNMADD_S
2978
    { 1875, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1875 = XVFNMADD_D
2979
    { 1874, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1874 = XVFMUL_S
2980
    { 1873, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1873 = XVFMUL_D
2981
    { 1872, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1872 = XVFMSUB_S
2982
    { 1871, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1871 = XVFMSUB_D
2983
    { 1870, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1870 = XVFMIN_S
2984
    { 1869, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1869 = XVFMIN_D
2985
    { 1868, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1868 = XVFMINA_S
2986
    { 1867, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1867 = XVFMINA_D
2987
    { 1866, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1866 = XVFMAX_S
2988
    { 1865, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1865 = XVFMAX_D
2989
    { 1864, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1864 = XVFMAXA_S
2990
    { 1863, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1863 = XVFMAXA_D
2991
    { 1862, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1862 = XVFMADD_S
2992
    { 1861, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1861 = XVFMADD_D
2993
    { 1860, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1860 = XVFLOGB_S
2994
    { 1859, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1859 = XVFLOGB_D
2995
    { 1858, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1858 = XVFFINT_S_WU
2996
    { 1857, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1857 = XVFFINT_S_W
2997
    { 1856, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1856 = XVFFINT_S_L
2998
    { 1855, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1855 = XVFFINT_D_LU
2999
    { 1854, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1854 = XVFFINT_D_L
3000
    { 1853, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1853 = XVFFINTL_D_W
3001
    { 1852, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1852 = XVFFINTH_D_W
3002
    { 1851, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1851 = XVFDIV_S
3003
    { 1850, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1850 = XVFDIV_D
3004
    { 1849, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1849 = XVFCVT_S_D
3005
    { 1848, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1848 = XVFCVT_H_S
3006
    { 1847, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1847 = XVFCVTL_S_H
3007
    { 1846, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1846 = XVFCVTL_D_S
3008
    { 1845, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1845 = XVFCVTH_S_H
3009
    { 1844, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1844 = XVFCVTH_D_S
3010
    { 1843, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1843 = XVFCMP_SUN_S
3011
    { 1842, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1842 = XVFCMP_SUN_D
3012
    { 1841, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1841 = XVFCMP_SUNE_S
3013
    { 1840, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1840 = XVFCMP_SUNE_D
3014
    { 1839, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1839 = XVFCMP_SULT_S
3015
    { 1838, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1838 = XVFCMP_SULT_D
3016
    { 1837, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1837 = XVFCMP_SULE_S
3017
    { 1836, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1836 = XVFCMP_SULE_D
3018
    { 1835, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1835 = XVFCMP_SUEQ_S
3019
    { 1834, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1834 = XVFCMP_SUEQ_D
3020
    { 1833, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1833 = XVFCMP_SOR_S
3021
    { 1832, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1832 = XVFCMP_SOR_D
3022
    { 1831, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1831 = XVFCMP_SNE_S
3023
    { 1830, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1830 = XVFCMP_SNE_D
3024
    { 1829, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1829 = XVFCMP_SLT_S
3025
    { 1828, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1828 = XVFCMP_SLT_D
3026
    { 1827, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1827 = XVFCMP_SLE_S
3027
    { 1826, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1826 = XVFCMP_SLE_D
3028
    { 1825, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1825 = XVFCMP_SEQ_S
3029
    { 1824, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1824 = XVFCMP_SEQ_D
3030
    { 1823, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1823 = XVFCMP_SAF_S
3031
    { 1822, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1822 = XVFCMP_SAF_D
3032
    { 1821, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1821 = XVFCMP_CUN_S
3033
    { 1820, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1820 = XVFCMP_CUN_D
3034
    { 1819, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1819 = XVFCMP_CUNE_S
3035
    { 1818, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1818 = XVFCMP_CUNE_D
3036
    { 1817, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1817 = XVFCMP_CULT_S
3037
    { 1816, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1816 = XVFCMP_CULT_D
3038
    { 1815, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1815 = XVFCMP_CULE_S
3039
    { 1814, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1814 = XVFCMP_CULE_D
3040
    { 1813, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1813 = XVFCMP_CUEQ_S
3041
    { 1812, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1812 = XVFCMP_CUEQ_D
3042
    { 1811, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1811 = XVFCMP_COR_S
3043
    { 1810, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1810 = XVFCMP_COR_D
3044
    { 1809, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1809 = XVFCMP_CNE_S
3045
    { 1808, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1808 = XVFCMP_CNE_D
3046
    { 1807, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1807 = XVFCMP_CLT_S
3047
    { 1806, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1806 = XVFCMP_CLT_D
3048
    { 1805, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1805 = XVFCMP_CLE_S
3049
    { 1804, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1804 = XVFCMP_CLE_D
3050
    { 1803, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1803 = XVFCMP_CEQ_S
3051
    { 1802, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1802 = XVFCMP_CEQ_D
3052
    { 1801, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1801 = XVFCMP_CAF_S
3053
    { 1800, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1800 = XVFCMP_CAF_D
3054
    { 1799, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1799 = XVFCLASS_S
3055
    { 1798, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1798 = XVFCLASS_D
3056
    { 1797, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1797 = XVFADD_S
3057
    { 1796, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1796 = XVFADD_D
3058
    { 1795, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1795 = XVEXTRINS_W
3059
    { 1794, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1794 = XVEXTRINS_H
3060
    { 1793, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1793 = XVEXTRINS_D
3061
    { 1792, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1792 = XVEXTRINS_B
3062
    { 1791, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1791 = XVEXTL_Q_D
3063
    { 1790, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1790 = XVEXTL_QU_DU
3064
    { 1789, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1789 = XVEXTH_W_H
3065
    { 1788, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1788 = XVEXTH_WU_HU
3066
    { 1787, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1787 = XVEXTH_Q_D
3067
    { 1786, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1786 = XVEXTH_QU_DU
3068
    { 1785, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1785 = XVEXTH_H_B
3069
    { 1784, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1784 = XVEXTH_HU_BU
3070
    { 1783, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1783 = XVEXTH_D_W
3071
    { 1782, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1782 = XVEXTH_DU_WU
3072
    { 1781, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1781 = XVDIV_WU
3073
    { 1780, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1780 = XVDIV_W
3074
    { 1779, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1779 = XVDIV_HU
3075
    { 1778, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1778 = XVDIV_H
3076
    { 1777, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1777 = XVDIV_DU
3077
    { 1776, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1776 = XVDIV_D
3078
    { 1775, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1775 = XVDIV_BU
3079
    { 1774, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1774 = XVDIV_B
3080
    { 1773, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1773 = XVCLZ_W
3081
    { 1772, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1772 = XVCLZ_H
3082
    { 1771, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1771 = XVCLZ_D
3083
    { 1770, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1770 = XVCLZ_B
3084
    { 1769, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1769 = XVCLO_W
3085
    { 1768, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1768 = XVCLO_H
3086
    { 1767, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1767 = XVCLO_D
3087
    { 1766, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #1766 = XVCLO_B
3088
    { 1765, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1765 = XVBSRL_V
3089
    { 1764, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1764 = XVBSLL_V
3090
    { 1763, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1763 = XVBITSET_W
3091
    { 1762, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1762 = XVBITSET_H
3092
    { 1761, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1761 = XVBITSET_D
3093
    { 1760, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1760 = XVBITSET_B
3094
    { 1759, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1759 = XVBITSETI_W
3095
    { 1758, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1758 = XVBITSETI_H
3096
    { 1757, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1757 = XVBITSETI_D
3097
    { 1756, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1756 = XVBITSETI_B
3098
    { 1755, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 377,  0, 0x0ULL },  // Inst #1755 = XVBITSEL_V
3099
    { 1754, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 373,  0, 0x0ULL },  // Inst #1754 = XVBITSELI_B
3100
    { 1753, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1753 = XVBITREV_W
3101
    { 1752, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1752 = XVBITREV_H
3102
    { 1751, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1751 = XVBITREV_D
3103
    { 1750, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1750 = XVBITREV_B
3104
    { 1749, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1749 = XVBITREVI_W
3105
    { 1748, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1748 = XVBITREVI_H
3106
    { 1747, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1747 = XVBITREVI_D
3107
    { 1746, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1746 = XVBITREVI_B
3108
    { 1745, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1745 = XVBITCLR_W
3109
    { 1744, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1744 = XVBITCLR_H
3110
    { 1743, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1743 = XVBITCLR_D
3111
    { 1742, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1742 = XVBITCLR_B
3112
    { 1741, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1741 = XVBITCLRI_W
3113
    { 1740, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1740 = XVBITCLRI_H
3114
    { 1739, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1739 = XVBITCLRI_D
3115
    { 1738, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1738 = XVBITCLRI_B
3116
    { 1737, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1737 = XVAVG_WU
3117
    { 1736, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1736 = XVAVG_W
3118
    { 1735, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1735 = XVAVG_HU
3119
    { 1734, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1734 = XVAVG_H
3120
    { 1733, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1733 = XVAVG_DU
3121
    { 1732, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1732 = XVAVG_D
3122
    { 1731, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1731 = XVAVG_BU
3123
    { 1730, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1730 = XVAVG_B
3124
    { 1729, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1729 = XVAVGR_WU
3125
    { 1728, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1728 = XVAVGR_W
3126
    { 1727, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1727 = XVAVGR_HU
3127
    { 1726, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1726 = XVAVGR_H
3128
    { 1725, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1725 = XVAVGR_DU
3129
    { 1724, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1724 = XVAVGR_D
3130
    { 1723, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1723 = XVAVGR_BU
3131
    { 1722, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1722 = XVAVGR_B
3132
    { 1721, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1721 = XVAND_V
3133
    { 1720, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1720 = XVANDN_V
3134
    { 1719, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1719 = XVANDI_B
3135
    { 1718, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1718 = XVADD_W
3136
    { 1717, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1717 = XVADD_Q
3137
    { 1716, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1716 = XVADD_H
3138
    { 1715, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1715 = XVADD_D
3139
    { 1714, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1714 = XVADD_B
3140
    { 1713, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1713 = XVADDWOD_W_HU_H
3141
    { 1712, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1712 = XVADDWOD_W_HU
3142
    { 1711, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1711 = XVADDWOD_W_H
3143
    { 1710, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1710 = XVADDWOD_Q_DU_D
3144
    { 1709, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1709 = XVADDWOD_Q_DU
3145
    { 1708, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1708 = XVADDWOD_Q_D
3146
    { 1707, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1707 = XVADDWOD_H_BU_B
3147
    { 1706, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1706 = XVADDWOD_H_BU
3148
    { 1705, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1705 = XVADDWOD_H_B
3149
    { 1704, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1704 = XVADDWOD_D_WU_W
3150
    { 1703, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1703 = XVADDWOD_D_WU
3151
    { 1702, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1702 = XVADDWOD_D_W
3152
    { 1701, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1701 = XVADDWEV_W_HU_H
3153
    { 1700, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1700 = XVADDWEV_W_HU
3154
    { 1699, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1699 = XVADDWEV_W_H
3155
    { 1698, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1698 = XVADDWEV_Q_DU_D
3156
    { 1697, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1697 = XVADDWEV_Q_DU
3157
    { 1696, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1696 = XVADDWEV_Q_D
3158
    { 1695, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1695 = XVADDWEV_H_BU_B
3159
    { 1694, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1694 = XVADDWEV_H_BU
3160
    { 1693, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1693 = XVADDWEV_H_B
3161
    { 1692, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1692 = XVADDWEV_D_WU_W
3162
    { 1691, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1691 = XVADDWEV_D_WU
3163
    { 1690, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1690 = XVADDWEV_D_W
3164
    { 1689, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1689 = XVADDI_WU
3165
    { 1688, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1688 = XVADDI_HU
3166
    { 1687, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1687 = XVADDI_DU
3167
    { 1686, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 370,  0, 0x0ULL },  // Inst #1686 = XVADDI_BU
3168
    { 1685, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1685 = XVADDA_W
3169
    { 1684, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1684 = XVADDA_H
3170
    { 1683, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1683 = XVADDA_D
3171
    { 1682, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1682 = XVADDA_B
3172
    { 1681, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1681 = XVABSD_WU
3173
    { 1680, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1680 = XVABSD_W
3174
    { 1679, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1679 = XVABSD_HU
3175
    { 1678, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1678 = XVABSD_H
3176
    { 1677, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1677 = XVABSD_DU
3177
    { 1676, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1676 = XVABSD_D
3178
    { 1675, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1675 = XVABSD_BU
3179
    { 1674, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 367,  0, 0x0ULL },  // Inst #1674 = XVABSD_B
3180
    { 1673, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #1673 = XORI
3181
    { 1672, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #1672 = XOR
3182
    { 1671, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1671 = X86XOR_W
3183
    { 1670, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1670 = X86XOR_H
3184
    { 1669, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1669 = X86XOR_D
3185
    { 1668, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1668 = X86XOR_B
3186
    { 1667, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1667 = X86SUB_WU
3187
    { 1666, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1666 = X86SUB_W
3188
    { 1665, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1665 = X86SUB_H
3189
    { 1664, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1664 = X86SUB_DU
3190
    { 1663, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1663 = X86SUB_D
3191
    { 1662, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1662 = X86SUB_B
3192
    { 1661, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1661 = X86SRL_W
3193
    { 1660, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1660 = X86SRL_H
3194
    { 1659, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1659 = X86SRL_D
3195
    { 1658, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1658 = X86SRL_B
3196
    { 1657, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1657 = X86SRLI_W
3197
    { 1656, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1656 = X86SRLI_H
3198
    { 1655, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1655 = X86SRLI_D
3199
    { 1654, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1654 = X86SRLI_B
3200
    { 1653, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1653 = X86SRA_W
3201
    { 1652, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1652 = X86SRA_H
3202
    { 1651, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1651 = X86SRA_D
3203
    { 1650, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1650 = X86SRA_B
3204
    { 1649, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1649 = X86SRAI_W
3205
    { 1648, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1648 = X86SRAI_H
3206
    { 1647, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1647 = X86SRAI_D
3207
    { 1646, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1646 = X86SRAI_B
3208
    { 1645, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1645 = X86SLL_W
3209
    { 1644, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1644 = X86SLL_H
3210
    { 1643, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1643 = X86SLL_D
3211
    { 1642, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1642 = X86SLL_B
3212
    { 1641, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1641 = X86SLLI_W
3213
    { 1640, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1640 = X86SLLI_H
3214
    { 1639, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1639 = X86SLLI_D
3215
    { 1638, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1638 = X86SLLI_B
3216
    { 1637, 0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0, 0x0ULL },  // Inst #1637 = X86SETTM
3217
    { 1636, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #1636 = X86SETTAG
3218
    { 1635, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1635 = X86SBC_W
3219
    { 1634, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1634 = X86SBC_H
3220
    { 1633, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1633 = X86SBC_D
3221
    { 1632, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1632 = X86SBC_B
3222
    { 1631, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1631 = X86ROTR_W
3223
    { 1630, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1630 = X86ROTR_H
3224
    { 1629, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1629 = X86ROTR_D
3225
    { 1628, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1628 = X86ROTR_B
3226
    { 1627, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1627 = X86ROTRI_W
3227
    { 1626, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1626 = X86ROTRI_H
3228
    { 1625, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1625 = X86ROTRI_D
3229
    { 1624, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1624 = X86ROTRI_B
3230
    { 1623, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1623 = X86ROTL_W
3231
    { 1622, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1622 = X86ROTL_H
3232
    { 1621, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1621 = X86ROTL_D
3233
    { 1620, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1620 = X86ROTL_B
3234
    { 1619, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1619 = X86ROTLI_W
3235
    { 1618, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1618 = X86ROTLI_H
3236
    { 1617, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1617 = X86ROTLI_D
3237
    { 1616, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1616 = X86ROTLI_B
3238
    { 1615, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1615 = X86RCR_W
3239
    { 1614, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1614 = X86RCR_H
3240
    { 1613, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1613 = X86RCR_D
3241
    { 1612, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1612 = X86RCR_B
3242
    { 1611, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1611 = X86RCRI_W
3243
    { 1610, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1610 = X86RCRI_H
3244
    { 1609, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1609 = X86RCRI_D
3245
    { 1608, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1608 = X86RCRI_B
3246
    { 1607, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1607 = X86RCL_W
3247
    { 1606, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1606 = X86RCL_H
3248
    { 1605, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1605 = X86RCL_D
3249
    { 1604, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1604 = X86RCL_B
3250
    { 1603, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1603 = X86RCLI_W
3251
    { 1602, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1602 = X86RCLI_H
3252
    { 1601, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1601 = X86RCLI_D
3253
    { 1600, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1600 = X86RCLI_B
3254
    { 1599, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1599 = X86OR_W
3255
    { 1598, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1598 = X86OR_H
3256
    { 1597, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1597 = X86OR_D
3257
    { 1596, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1596 = X86OR_B
3258
    { 1595, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1595 = X86MUL_WU
3259
    { 1594, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1594 = X86MUL_W
3260
    { 1593, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1593 = X86MUL_HU
3261
    { 1592, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1592 = X86MUL_H
3262
    { 1591, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1591 = X86MUL_DU
3263
    { 1590, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1590 = X86MUL_D
3264
    { 1589, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1589 = X86MUL_BU
3265
    { 1588, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1588 = X86MUL_B
3266
    { 1587, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0, 0x0ULL },  // Inst #1587 = X86MTTOP
3267
    { 1586, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1586 = X86MTFLAG
3268
    { 1585, 1,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1585 = X86MFTOP
3269
    { 1584, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #1584 = X86MFFLAG
3270
    { 1583, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1583 = X86INC_W
3271
    { 1582, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1582 = X86INC_H
3272
    { 1581, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1581 = X86INC_D
3273
    { 1580, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1580 = X86INC_B
3274
    { 1579, 0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0, 0x0ULL },  // Inst #1579 = X86INCTOP
3275
    { 1578, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1578 = X86DEC_W
3276
    { 1577, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1577 = X86DEC_H
3277
    { 1576, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1576 = X86DEC_D
3278
    { 1575, 1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 150,  0, 0x0ULL },  // Inst #1575 = X86DEC_B
3279
    { 1574, 0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0, 0x0ULL },  // Inst #1574 = X86DECTOP
3280
    { 1573, 0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0, 0x0ULL },  // Inst #1573 = X86CLRTM
3281
    { 1572, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1572 = X86AND_W
3282
    { 1571, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1571 = X86AND_H
3283
    { 1570, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1570 = X86AND_D
3284
    { 1569, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1569 = X86AND_B
3285
    { 1568, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1568 = X86ADD_WU
3286
    { 1567, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1567 = X86ADD_W
3287
    { 1566, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1566 = X86ADD_H
3288
    { 1565, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1565 = X86ADD_DU
3289
    { 1564, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1564 = X86ADD_D
3290
    { 1563, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1563 = X86ADD_B
3291
    { 1562, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1562 = X86ADC_W
3292
    { 1561, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1561 = X86ADC_H
3293
    { 1560, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1560 = X86ADC_D
3294
    { 1559, 2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #1559 = X86ADC_B
3295
    { 1558, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1558 = VXOR_V
3296
    { 1557, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1557 = VXORI_B
3297
    { 1556, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1556 = VSUB_W
3298
    { 1555, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1555 = VSUB_Q
3299
    { 1554, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1554 = VSUB_H
3300
    { 1553, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1553 = VSUB_D
3301
    { 1552, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1552 = VSUB_B
3302
    { 1551, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1551 = VSUBWOD_W_HU
3303
    { 1550, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1550 = VSUBWOD_W_H
3304
    { 1549, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1549 = VSUBWOD_Q_DU
3305
    { 1548, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1548 = VSUBWOD_Q_D
3306
    { 1547, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1547 = VSUBWOD_H_BU
3307
    { 1546, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1546 = VSUBWOD_H_B
3308
    { 1545, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1545 = VSUBWOD_D_WU
3309
    { 1544, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1544 = VSUBWOD_D_W
3310
    { 1543, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1543 = VSUBWEV_W_HU
3311
    { 1542, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1542 = VSUBWEV_W_H
3312
    { 1541, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1541 = VSUBWEV_Q_DU
3313
    { 1540, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1540 = VSUBWEV_Q_D
3314
    { 1539, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1539 = VSUBWEV_H_BU
3315
    { 1538, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1538 = VSUBWEV_H_B
3316
    { 1537, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1537 = VSUBWEV_D_WU
3317
    { 1536, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1536 = VSUBWEV_D_W
3318
    { 1535, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1535 = VSUBI_WU
3319
    { 1534, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1534 = VSUBI_HU
3320
    { 1533, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1533 = VSUBI_DU
3321
    { 1532, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1532 = VSUBI_BU
3322
    { 1531, 3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 350,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #1531 = VSTX
3323
    { 1530, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 363,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #1530 = VSTELM_W
3324
    { 1529, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 363,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #1529 = VSTELM_H
3325
    { 1528, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 363,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #1528 = VSTELM_D
3326
    { 1527, 4,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 363,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #1527 = VSTELM_B
3327
    { 1526, 3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 347,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #1526 = VST
3328
    { 1525, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1525 = VSSUB_WU
3329
    { 1524, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1524 = VSSUB_W
3330
    { 1523, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1523 = VSSUB_HU
3331
    { 1522, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1522 = VSSUB_H
3332
    { 1521, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1521 = VSSUB_DU
3333
    { 1520, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1520 = VSSUB_D
3334
    { 1519, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1519 = VSSUB_BU
3335
    { 1518, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1518 = VSSUB_B
3336
    { 1517, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1517 = VSSRLRN_W_D
3337
    { 1516, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1516 = VSSRLRN_WU_D
3338
    { 1515, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1515 = VSSRLRN_H_W
3339
    { 1514, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1514 = VSSRLRN_HU_W
3340
    { 1513, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1513 = VSSRLRN_B_H
3341
    { 1512, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1512 = VSSRLRN_BU_H
3342
    { 1511, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1511 = VSSRLRNI_W_D
3343
    { 1510, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1510 = VSSRLRNI_WU_D
3344
    { 1509, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1509 = VSSRLRNI_H_W
3345
    { 1508, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1508 = VSSRLRNI_HU_W
3346
    { 1507, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1507 = VSSRLRNI_D_Q
3347
    { 1506, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1506 = VSSRLRNI_DU_Q
3348
    { 1505, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1505 = VSSRLRNI_B_H
3349
    { 1504, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1504 = VSSRLRNI_BU_H
3350
    { 1503, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1503 = VSSRLN_W_D
3351
    { 1502, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1502 = VSSRLN_WU_D
3352
    { 1501, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1501 = VSSRLN_H_W
3353
    { 1500, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1500 = VSSRLN_HU_W
3354
    { 1499, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1499 = VSSRLN_B_H
3355
    { 1498, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1498 = VSSRLN_BU_H
3356
    { 1497, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1497 = VSSRLNI_W_D
3357
    { 1496, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1496 = VSSRLNI_WU_D
3358
    { 1495, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1495 = VSSRLNI_H_W
3359
    { 1494, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1494 = VSSRLNI_HU_W
3360
    { 1493, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1493 = VSSRLNI_D_Q
3361
    { 1492, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1492 = VSSRLNI_DU_Q
3362
    { 1491, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1491 = VSSRLNI_B_H
3363
    { 1490, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1490 = VSSRLNI_BU_H
3364
    { 1489, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1489 = VSSRARN_W_D
3365
    { 1488, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1488 = VSSRARN_WU_D
3366
    { 1487, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1487 = VSSRARN_H_W
3367
    { 1486, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1486 = VSSRARN_HU_W
3368
    { 1485, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1485 = VSSRARN_B_H
3369
    { 1484, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1484 = VSSRARN_BU_H
3370
    { 1483, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1483 = VSSRARNI_W_D
3371
    { 1482, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1482 = VSSRARNI_WU_D
3372
    { 1481, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1481 = VSSRARNI_H_W
3373
    { 1480, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1480 = VSSRARNI_HU_W
3374
    { 1479, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1479 = VSSRARNI_D_Q
3375
    { 1478, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1478 = VSSRARNI_DU_Q
3376
    { 1477, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1477 = VSSRARNI_B_H
3377
    { 1476, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1476 = VSSRARNI_BU_H
3378
    { 1475, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1475 = VSSRAN_W_D
3379
    { 1474, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1474 = VSSRAN_WU_D
3380
    { 1473, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1473 = VSSRAN_H_W
3381
    { 1472, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1472 = VSSRAN_HU_W
3382
    { 1471, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1471 = VSSRAN_B_H
3383
    { 1470, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1470 = VSSRAN_BU_H
3384
    { 1469, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1469 = VSSRANI_W_D
3385
    { 1468, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1468 = VSSRANI_WU_D
3386
    { 1467, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1467 = VSSRANI_H_W
3387
    { 1466, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1466 = VSSRANI_HU_W
3388
    { 1465, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1465 = VSSRANI_D_Q
3389
    { 1464, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1464 = VSSRANI_DU_Q
3390
    { 1463, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1463 = VSSRANI_B_H
3391
    { 1462, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1462 = VSSRANI_BU_H
3392
    { 1461, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1461 = VSRL_W
3393
    { 1460, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1460 = VSRL_H
3394
    { 1459, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1459 = VSRL_D
3395
    { 1458, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1458 = VSRL_B
3396
    { 1457, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1457 = VSRLR_W
3397
    { 1456, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1456 = VSRLR_H
3398
    { 1455, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1455 = VSRLR_D
3399
    { 1454, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1454 = VSRLR_B
3400
    { 1453, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1453 = VSRLRN_W_D
3401
    { 1452, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1452 = VSRLRN_H_W
3402
    { 1451, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1451 = VSRLRN_B_H
3403
    { 1450, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1450 = VSRLRNI_W_D
3404
    { 1449, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1449 = VSRLRNI_H_W
3405
    { 1448, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1448 = VSRLRNI_D_Q
3406
    { 1447, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1447 = VSRLRNI_B_H
3407
    { 1446, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1446 = VSRLRI_W
3408
    { 1445, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1445 = VSRLRI_H
3409
    { 1444, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1444 = VSRLRI_D
3410
    { 1443, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1443 = VSRLRI_B
3411
    { 1442, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1442 = VSRLN_W_D
3412
    { 1441, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1441 = VSRLN_H_W
3413
    { 1440, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1440 = VSRLN_B_H
3414
    { 1439, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1439 = VSRLNI_W_D
3415
    { 1438, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1438 = VSRLNI_H_W
3416
    { 1437, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1437 = VSRLNI_D_Q
3417
    { 1436, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1436 = VSRLNI_B_H
3418
    { 1435, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1435 = VSRLI_W
3419
    { 1434, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1434 = VSRLI_H
3420
    { 1433, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1433 = VSRLI_D
3421
    { 1432, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1432 = VSRLI_B
3422
    { 1431, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1431 = VSRA_W
3423
    { 1430, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1430 = VSRA_H
3424
    { 1429, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1429 = VSRA_D
3425
    { 1428, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1428 = VSRA_B
3426
    { 1427, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1427 = VSRAR_W
3427
    { 1426, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1426 = VSRAR_H
3428
    { 1425, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1425 = VSRAR_D
3429
    { 1424, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1424 = VSRAR_B
3430
    { 1423, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1423 = VSRARN_W_D
3431
    { 1422, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1422 = VSRARN_H_W
3432
    { 1421, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1421 = VSRARN_B_H
3433
    { 1420, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1420 = VSRARNI_W_D
3434
    { 1419, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1419 = VSRARNI_H_W
3435
    { 1418, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1418 = VSRARNI_D_Q
3436
    { 1417, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1417 = VSRARNI_B_H
3437
    { 1416, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1416 = VSRARI_W
3438
    { 1415, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1415 = VSRARI_H
3439
    { 1414, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1414 = VSRARI_D
3440
    { 1413, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1413 = VSRARI_B
3441
    { 1412, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1412 = VSRAN_W_D
3442
    { 1411, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1411 = VSRAN_H_W
3443
    { 1410, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1410 = VSRAN_B_H
3444
    { 1409, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1409 = VSRANI_W_D
3445
    { 1408, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1408 = VSRANI_H_W
3446
    { 1407, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1407 = VSRANI_D_Q
3447
    { 1406, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1406 = VSRANI_B_H
3448
    { 1405, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1405 = VSRAI_W
3449
    { 1404, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1404 = VSRAI_H
3450
    { 1403, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1403 = VSRAI_D
3451
    { 1402, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1402 = VSRAI_B
3452
    { 1401, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1401 = VSLT_WU
3453
    { 1400, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1400 = VSLT_W
3454
    { 1399, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1399 = VSLT_HU
3455
    { 1398, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1398 = VSLT_H
3456
    { 1397, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1397 = VSLT_DU
3457
    { 1396, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1396 = VSLT_D
3458
    { 1395, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1395 = VSLT_BU
3459
    { 1394, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1394 = VSLT_B
3460
    { 1393, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1393 = VSLTI_WU
3461
    { 1392, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1392 = VSLTI_W
3462
    { 1391, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1391 = VSLTI_HU
3463
    { 1390, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1390 = VSLTI_H
3464
    { 1389, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1389 = VSLTI_DU
3465
    { 1388, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1388 = VSLTI_D
3466
    { 1387, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1387 = VSLTI_BU
3467
    { 1386, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1386 = VSLTI_B
3468
    { 1385, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1385 = VSLL_W
3469
    { 1384, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1384 = VSLL_H
3470
    { 1383, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1383 = VSLL_D
3471
    { 1382, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1382 = VSLL_B
3472
    { 1381, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1381 = VSLLWIL_W_H
3473
    { 1380, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1380 = VSLLWIL_WU_HU
3474
    { 1379, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1379 = VSLLWIL_H_B
3475
    { 1378, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1378 = VSLLWIL_HU_BU
3476
    { 1377, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1377 = VSLLWIL_D_W
3477
    { 1376, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1376 = VSLLWIL_DU_WU
3478
    { 1375, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1375 = VSLLI_W
3479
    { 1374, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1374 = VSLLI_H
3480
    { 1373, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1373 = VSLLI_D
3481
    { 1372, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1372 = VSLLI_B
3482
    { 1371, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1371 = VSLE_WU
3483
    { 1370, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1370 = VSLE_W
3484
    { 1369, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1369 = VSLE_HU
3485
    { 1368, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1368 = VSLE_H
3486
    { 1367, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1367 = VSLE_DU
3487
    { 1366, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1366 = VSLE_D
3488
    { 1365, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1365 = VSLE_BU
3489
    { 1364, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1364 = VSLE_B
3490
    { 1363, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1363 = VSLEI_WU
3491
    { 1362, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1362 = VSLEI_W
3492
    { 1361, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1361 = VSLEI_HU
3493
    { 1360, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1360 = VSLEI_H
3494
    { 1359, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1359 = VSLEI_DU
3495
    { 1358, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1358 = VSLEI_D
3496
    { 1357, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1357 = VSLEI_BU
3497
    { 1356, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1356 = VSLEI_B
3498
    { 1355, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1355 = VSIGNCOV_W
3499
    { 1354, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1354 = VSIGNCOV_H
3500
    { 1353, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1353 = VSIGNCOV_D
3501
    { 1352, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1352 = VSIGNCOV_B
3502
    { 1351, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1351 = VSHUF_W
3503
    { 1350, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1350 = VSHUF_H
3504
    { 1349, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1349 = VSHUF_D
3505
    { 1348, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1348 = VSHUF_B
3506
    { 1347, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1347 = VSHUF4I_W
3507
    { 1346, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1346 = VSHUF4I_H
3508
    { 1345, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1345 = VSHUF4I_D
3509
    { 1344, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1344 = VSHUF4I_B
3510
    { 1343, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1343 = VSETNEZ_V
3511
    { 1342, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1342 = VSETEQZ_V
3512
    { 1341, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1341 = VSETANYEQZ_W
3513
    { 1340, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1340 = VSETANYEQZ_H
3514
    { 1339, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1339 = VSETANYEQZ_D
3515
    { 1338, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1338 = VSETANYEQZ_B
3516
    { 1337, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1337 = VSETALLNEZ_W
3517
    { 1336, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1336 = VSETALLNEZ_H
3518
    { 1335, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1335 = VSETALLNEZ_D
3519
    { 1334, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 361,  0, 0x0ULL },  // Inst #1334 = VSETALLNEZ_B
3520
    { 1333, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1333 = VSEQ_W
3521
    { 1332, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1332 = VSEQ_H
3522
    { 1331, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1331 = VSEQ_D
3523
    { 1330, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1330 = VSEQ_B
3524
    { 1329, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1329 = VSEQI_W
3525
    { 1328, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1328 = VSEQI_H
3526
    { 1327, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1327 = VSEQI_D
3527
    { 1326, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1326 = VSEQI_B
3528
    { 1325, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1325 = VSAT_WU
3529
    { 1324, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1324 = VSAT_W
3530
    { 1323, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1323 = VSAT_HU
3531
    { 1322, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1322 = VSAT_H
3532
    { 1321, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1321 = VSAT_DU
3533
    { 1320, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1320 = VSAT_D
3534
    { 1319, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1319 = VSAT_BU
3535
    { 1318, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1318 = VSAT_B
3536
    { 1317, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1317 = VSADD_WU
3537
    { 1316, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1316 = VSADD_W
3538
    { 1315, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1315 = VSADD_HU
3539
    { 1314, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1314 = VSADD_H
3540
    { 1313, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1313 = VSADD_DU
3541
    { 1312, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1312 = VSADD_D
3542
    { 1311, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1311 = VSADD_BU
3543
    { 1310, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1310 = VSADD_B
3544
    { 1309, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1309 = VROTR_W
3545
    { 1308, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1308 = VROTR_H
3546
    { 1307, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1307 = VROTR_D
3547
    { 1306, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1306 = VROTR_B
3548
    { 1305, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1305 = VROTRI_W
3549
    { 1304, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1304 = VROTRI_H
3550
    { 1303, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1303 = VROTRI_D
3551
    { 1302, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1302 = VROTRI_B
3552
    { 1301, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 358,  0, 0x0ULL },  // Inst #1301 = VREPLVE_W
3553
    { 1300, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 358,  0, 0x0ULL },  // Inst #1300 = VREPLVE_H
3554
    { 1299, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 358,  0, 0x0ULL },  // Inst #1299 = VREPLVE_D
3555
    { 1298, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 358,  0, 0x0ULL },  // Inst #1298 = VREPLVE_B
3556
    { 1297, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1297 = VREPLVEI_W
3557
    { 1296, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1296 = VREPLVEI_H
3558
    { 1295, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1295 = VREPLVEI_D
3559
    { 1294, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1294 = VREPLVEI_B
3560
    { 1293, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 356,  0, 0x0ULL },  // Inst #1293 = VREPLGR2VR_W
3561
    { 1292, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 356,  0, 0x0ULL },  // Inst #1292 = VREPLGR2VR_H
3562
    { 1291, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 356,  0, 0x0ULL },  // Inst #1291 = VREPLGR2VR_D
3563
    { 1290, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 356,  0, 0x0ULL },  // Inst #1290 = VREPLGR2VR_B
3564
    { 1289, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1289 = VPICKVE2GR_WU
3565
    { 1288, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1288 = VPICKVE2GR_W
3566
    { 1287, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1287 = VPICKVE2GR_HU
3567
    { 1286, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1286 = VPICKVE2GR_H
3568
    { 1285, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1285 = VPICKVE2GR_DU
3569
    { 1284, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1284 = VPICKVE2GR_D
3570
    { 1283, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1283 = VPICKVE2GR_BU
3571
    { 1282, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 353,  0, 0x0ULL },  // Inst #1282 = VPICKVE2GR_B
3572
    { 1281, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1281 = VPICKOD_W
3573
    { 1280, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1280 = VPICKOD_H
3574
    { 1279, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1279 = VPICKOD_D
3575
    { 1278, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1278 = VPICKOD_B
3576
    { 1277, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1277 = VPICKEV_W
3577
    { 1276, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1276 = VPICKEV_H
3578
    { 1275, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1275 = VPICKEV_D
3579
    { 1274, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1274 = VPICKEV_B
3580
    { 1273, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1273 = VPERMI_W
3581
    { 1272, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1272 = VPCNT_W
3582
    { 1271, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1271 = VPCNT_H
3583
    { 1270, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1270 = VPCNT_D
3584
    { 1269, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1269 = VPCNT_B
3585
    { 1268, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1268 = VPACKOD_W
3586
    { 1267, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1267 = VPACKOD_H
3587
    { 1266, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1266 = VPACKOD_D
3588
    { 1265, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1265 = VPACKOD_B
3589
    { 1264, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1264 = VPACKEV_W
3590
    { 1263, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1263 = VPACKEV_H
3591
    { 1262, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1262 = VPACKEV_D
3592
    { 1261, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1261 = VPACKEV_B
3593
    { 1260, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1260 = VOR_V
3594
    { 1259, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1259 = VORN_V
3595
    { 1258, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1258 = VORI_B
3596
    { 1257, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1257 = VNOR_V
3597
    { 1256, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1256 = VNORI_B
3598
    { 1255, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1255 = VNEG_W
3599
    { 1254, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1254 = VNEG_H
3600
    { 1253, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1253 = VNEG_D
3601
    { 1252, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1252 = VNEG_B
3602
    { 1251, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1251 = VMUL_W
3603
    { 1250, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1250 = VMUL_H
3604
    { 1249, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1249 = VMUL_D
3605
    { 1248, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1248 = VMUL_B
3606
    { 1247, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1247 = VMULWOD_W_HU_H
3607
    { 1246, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1246 = VMULWOD_W_HU
3608
    { 1245, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1245 = VMULWOD_W_H
3609
    { 1244, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1244 = VMULWOD_Q_DU_D
3610
    { 1243, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1243 = VMULWOD_Q_DU
3611
    { 1242, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1242 = VMULWOD_Q_D
3612
    { 1241, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1241 = VMULWOD_H_BU_B
3613
    { 1240, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1240 = VMULWOD_H_BU
3614
    { 1239, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1239 = VMULWOD_H_B
3615
    { 1238, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1238 = VMULWOD_D_WU_W
3616
    { 1237, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1237 = VMULWOD_D_WU
3617
    { 1236, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1236 = VMULWOD_D_W
3618
    { 1235, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1235 = VMULWEV_W_HU_H
3619
    { 1234, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1234 = VMULWEV_W_HU
3620
    { 1233, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1233 = VMULWEV_W_H
3621
    { 1232, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1232 = VMULWEV_Q_DU_D
3622
    { 1231, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1231 = VMULWEV_Q_DU
3623
    { 1230, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1230 = VMULWEV_Q_D
3624
    { 1229, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1229 = VMULWEV_H_BU_B
3625
    { 1228, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1228 = VMULWEV_H_BU
3626
    { 1227, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1227 = VMULWEV_H_B
3627
    { 1226, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1226 = VMULWEV_D_WU_W
3628
    { 1225, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1225 = VMULWEV_D_WU
3629
    { 1224, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1224 = VMULWEV_D_W
3630
    { 1223, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1223 = VMUH_WU
3631
    { 1222, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1222 = VMUH_W
3632
    { 1221, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1221 = VMUH_HU
3633
    { 1220, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1220 = VMUH_H
3634
    { 1219, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1219 = VMUH_DU
3635
    { 1218, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1218 = VMUH_D
3636
    { 1217, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1217 = VMUH_BU
3637
    { 1216, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1216 = VMUH_B
3638
    { 1215, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1215 = VMSUB_W
3639
    { 1214, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1214 = VMSUB_H
3640
    { 1213, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1213 = VMSUB_D
3641
    { 1212, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1212 = VMSUB_B
3642
    { 1211, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1211 = VMSKNZ_B
3643
    { 1210, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1210 = VMSKLTZ_W
3644
    { 1209, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1209 = VMSKLTZ_H
3645
    { 1208, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1208 = VMSKLTZ_D
3646
    { 1207, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1207 = VMSKLTZ_B
3647
    { 1206, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1206 = VMSKGEZ_B
3648
    { 1205, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1205 = VMOD_WU
3649
    { 1204, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1204 = VMOD_W
3650
    { 1203, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1203 = VMOD_HU
3651
    { 1202, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1202 = VMOD_H
3652
    { 1201, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1201 = VMOD_DU
3653
    { 1200, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1200 = VMOD_D
3654
    { 1199, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1199 = VMOD_BU
3655
    { 1198, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1198 = VMOD_B
3656
    { 1197, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1197 = VMIN_WU
3657
    { 1196, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1196 = VMIN_W
3658
    { 1195, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1195 = VMIN_HU
3659
    { 1194, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1194 = VMIN_H
3660
    { 1193, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1193 = VMIN_DU
3661
    { 1192, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1192 = VMIN_D
3662
    { 1191, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1191 = VMIN_BU
3663
    { 1190, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1190 = VMIN_B
3664
    { 1189, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1189 = VMINI_WU
3665
    { 1188, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1188 = VMINI_W
3666
    { 1187, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1187 = VMINI_HU
3667
    { 1186, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1186 = VMINI_H
3668
    { 1185, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1185 = VMINI_DU
3669
    { 1184, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1184 = VMINI_D
3670
    { 1183, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1183 = VMINI_BU
3671
    { 1182, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1182 = VMINI_B
3672
    { 1181, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1181 = VMAX_WU
3673
    { 1180, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1180 = VMAX_W
3674
    { 1179, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1179 = VMAX_HU
3675
    { 1178, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1178 = VMAX_H
3676
    { 1177, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1177 = VMAX_DU
3677
    { 1176, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1176 = VMAX_D
3678
    { 1175, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1175 = VMAX_BU
3679
    { 1174, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1174 = VMAX_B
3680
    { 1173, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1173 = VMAXI_WU
3681
    { 1172, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1172 = VMAXI_W
3682
    { 1171, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1171 = VMAXI_HU
3683
    { 1170, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1170 = VMAXI_H
3684
    { 1169, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1169 = VMAXI_DU
3685
    { 1168, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1168 = VMAXI_D
3686
    { 1167, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1167 = VMAXI_BU
3687
    { 1166, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #1166 = VMAXI_B
3688
    { 1165, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1165 = VMADD_W
3689
    { 1164, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1164 = VMADD_H
3690
    { 1163, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1163 = VMADD_D
3691
    { 1162, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1162 = VMADD_B
3692
    { 1161, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1161 = VMADDWOD_W_HU_H
3693
    { 1160, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1160 = VMADDWOD_W_HU
3694
    { 1159, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1159 = VMADDWOD_W_H
3695
    { 1158, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1158 = VMADDWOD_Q_DU_D
3696
    { 1157, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1157 = VMADDWOD_Q_DU
3697
    { 1156, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1156 = VMADDWOD_Q_D
3698
    { 1155, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1155 = VMADDWOD_H_BU_B
3699
    { 1154, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1154 = VMADDWOD_H_BU
3700
    { 1153, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1153 = VMADDWOD_H_B
3701
    { 1152, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1152 = VMADDWOD_D_WU_W
3702
    { 1151, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1151 = VMADDWOD_D_WU
3703
    { 1150, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1150 = VMADDWOD_D_W
3704
    { 1149, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1149 = VMADDWEV_W_HU_H
3705
    { 1148, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1148 = VMADDWEV_W_HU
3706
    { 1147, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1147 = VMADDWEV_W_H
3707
    { 1146, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1146 = VMADDWEV_Q_DU_D
3708
    { 1145, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1145 = VMADDWEV_Q_DU
3709
    { 1144, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1144 = VMADDWEV_Q_D
3710
    { 1143, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1143 = VMADDWEV_H_BU_B
3711
    { 1142, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1142 = VMADDWEV_H_BU
3712
    { 1141, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1141 = VMADDWEV_H_B
3713
    { 1140, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1140 = VMADDWEV_D_WU_W
3714
    { 1139, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1139 = VMADDWEV_D_WU
3715
    { 1138, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1138 = VMADDWEV_D_W
3716
    { 1137, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 350,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1137 = VLDX
3717
    { 1136, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 347,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1136 = VLDREPL_W
3718
    { 1135, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 347,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1135 = VLDREPL_H
3719
    { 1134, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 347,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1134 = VLDREPL_D
3720
    { 1133, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 347,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1133 = VLDREPL_B
3721
    { 1132, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 190,  0, 0x0ULL },  // Inst #1132 = VLDI
3722
    { 1131, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 347,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #1131 = VLD
3723
    { 1130, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 343,  0, 0x0ULL },  // Inst #1130 = VINSGR2VR_W
3724
    { 1129, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 343,  0, 0x0ULL },  // Inst #1129 = VINSGR2VR_H
3725
    { 1128, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 343,  0, 0x0ULL },  // Inst #1128 = VINSGR2VR_D
3726
    { 1127, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 343,  0, 0x0ULL },  // Inst #1127 = VINSGR2VR_B
3727
    { 1126, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1126 = VILVL_W
3728
    { 1125, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1125 = VILVL_H
3729
    { 1124, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1124 = VILVL_D
3730
    { 1123, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1123 = VILVL_B
3731
    { 1122, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1122 = VILVH_W
3732
    { 1121, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1121 = VILVH_H
3733
    { 1120, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1120 = VILVH_D
3734
    { 1119, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1119 = VILVH_B
3735
    { 1118, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1118 = VHSUBW_W_H
3736
    { 1117, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1117 = VHSUBW_WU_HU
3737
    { 1116, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1116 = VHSUBW_Q_D
3738
    { 1115, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1115 = VHSUBW_QU_DU
3739
    { 1114, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1114 = VHSUBW_H_B
3740
    { 1113, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1113 = VHSUBW_HU_BU
3741
    { 1112, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1112 = VHSUBW_D_W
3742
    { 1111, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1111 = VHSUBW_DU_WU
3743
    { 1110, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1110 = VHADDW_W_H
3744
    { 1109, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1109 = VHADDW_WU_HU
3745
    { 1108, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1108 = VHADDW_Q_D
3746
    { 1107, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1107 = VHADDW_QU_DU
3747
    { 1106, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1106 = VHADDW_H_B
3748
    { 1105, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1105 = VHADDW_HU_BU
3749
    { 1104, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1104 = VHADDW_D_W
3750
    { 1103, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1103 = VHADDW_DU_WU
3751
    { 1102, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1102 = VFTINT_W_S
3752
    { 1101, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1101 = VFTINT_W_D
3753
    { 1100, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1100 = VFTINT_WU_S
3754
    { 1099, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1099 = VFTINT_L_D
3755
    { 1098, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1098 = VFTINT_LU_D
3756
    { 1097, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1097 = VFTINTRZ_W_S
3757
    { 1096, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1096 = VFTINTRZ_W_D
3758
    { 1095, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1095 = VFTINTRZ_WU_S
3759
    { 1094, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1094 = VFTINTRZ_L_D
3760
    { 1093, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1093 = VFTINTRZ_LU_D
3761
    { 1092, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1092 = VFTINTRZL_L_S
3762
    { 1091, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1091 = VFTINTRZH_L_S
3763
    { 1090, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1090 = VFTINTRP_W_S
3764
    { 1089, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1089 = VFTINTRP_W_D
3765
    { 1088, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1088 = VFTINTRP_L_D
3766
    { 1087, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1087 = VFTINTRPL_L_S
3767
    { 1086, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1086 = VFTINTRPH_L_S
3768
    { 1085, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1085 = VFTINTRNE_W_S
3769
    { 1084, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1084 = VFTINTRNE_W_D
3770
    { 1083, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1083 = VFTINTRNE_L_D
3771
    { 1082, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1082 = VFTINTRNEL_L_S
3772
    { 1081, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1081 = VFTINTRNEH_L_S
3773
    { 1080, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1080 = VFTINTRM_W_S
3774
    { 1079, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1079 = VFTINTRM_W_D
3775
    { 1078, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1078 = VFTINTRM_L_D
3776
    { 1077, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1077 = VFTINTRML_L_S
3777
    { 1076, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1076 = VFTINTRMH_L_S
3778
    { 1075, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1075 = VFTINTL_L_S
3779
    { 1074, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1074 = VFTINTH_L_S
3780
    { 1073, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1073 = VFSUB_S
3781
    { 1072, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1072 = VFSUB_D
3782
    { 1071, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1071 = VFSQRT_S
3783
    { 1070, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1070 = VFSQRT_D
3784
    { 1069, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1069 = VFRSTP_H
3785
    { 1068, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 339,  0, 0x0ULL },  // Inst #1068 = VFRSTP_B
3786
    { 1067, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1067 = VFRSTPI_H
3787
    { 1066, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #1066 = VFRSTPI_B
3788
    { 1065, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1065 = VFRSQRT_S
3789
    { 1064, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1064 = VFRSQRT_D
3790
    { 1063, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1063 = VFRSQRTE_S
3791
    { 1062, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1062 = VFRSQRTE_D
3792
    { 1061, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1061 = VFRINT_S
3793
    { 1060, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1060 = VFRINT_D
3794
    { 1059, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1059 = VFRINTRZ_S
3795
    { 1058, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1058 = VFRINTRZ_D
3796
    { 1057, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1057 = VFRINTRP_S
3797
    { 1056, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1056 = VFRINTRP_D
3798
    { 1055, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1055 = VFRINTRNE_S
3799
    { 1054, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1054 = VFRINTRNE_D
3800
    { 1053, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1053 = VFRINTRM_S
3801
    { 1052, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1052 = VFRINTRM_D
3802
    { 1051, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1051 = VFRECIP_S
3803
    { 1050, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1050 = VFRECIP_D
3804
    { 1049, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1049 = VFRECIPE_S
3805
    { 1048, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1048 = VFRECIPE_D
3806
    { 1047, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1047 = VFNMSUB_S
3807
    { 1046, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1046 = VFNMSUB_D
3808
    { 1045, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1045 = VFNMADD_S
3809
    { 1044, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1044 = VFNMADD_D
3810
    { 1043, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1043 = VFMUL_S
3811
    { 1042, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1042 = VFMUL_D
3812
    { 1041, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1041 = VFMSUB_S
3813
    { 1040, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1040 = VFMSUB_D
3814
    { 1039, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1039 = VFMIN_S
3815
    { 1038, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1038 = VFMIN_D
3816
    { 1037, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1037 = VFMINA_S
3817
    { 1036, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1036 = VFMINA_D
3818
    { 1035, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1035 = VFMAX_S
3819
    { 1034, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1034 = VFMAX_D
3820
    { 1033, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1033 = VFMAXA_S
3821
    { 1032, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1032 = VFMAXA_D
3822
    { 1031, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1031 = VFMADD_S
3823
    { 1030, 4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #1030 = VFMADD_D
3824
    { 1029, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1029 = VFLOGB_S
3825
    { 1028, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1028 = VFLOGB_D
3826
    { 1027, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1027 = VFFINT_S_WU
3827
    { 1026, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1026 = VFFINT_S_W
3828
    { 1025, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1025 = VFFINT_S_L
3829
    { 1024, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1024 = VFFINT_D_LU
3830
    { 1023, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1023 = VFFINT_D_L
3831
    { 1022, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1022 = VFFINTL_D_W
3832
    { 1021, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1021 = VFFINTH_D_W
3833
    { 1020, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1020 = VFDIV_S
3834
    { 1019, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1019 = VFDIV_D
3835
    { 1018, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1018 = VFCVT_S_D
3836
    { 1017, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1017 = VFCVT_H_S
3837
    { 1016, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1016 = VFCVTL_S_H
3838
    { 1015, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1015 = VFCVTL_D_S
3839
    { 1014, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1014 = VFCVTH_S_H
3840
    { 1013, 2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #1013 = VFCVTH_D_S
3841
    { 1012, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1012 = VFCMP_SUN_S
3842
    { 1011, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1011 = VFCMP_SUN_D
3843
    { 1010, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1010 = VFCMP_SUNE_S
3844
    { 1009, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1009 = VFCMP_SUNE_D
3845
    { 1008, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1008 = VFCMP_SULT_S
3846
    { 1007, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1007 = VFCMP_SULT_D
3847
    { 1006, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1006 = VFCMP_SULE_S
3848
    { 1005, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1005 = VFCMP_SULE_D
3849
    { 1004, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1004 = VFCMP_SUEQ_S
3850
    { 1003, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1003 = VFCMP_SUEQ_D
3851
    { 1002, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1002 = VFCMP_SOR_S
3852
    { 1001, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1001 = VFCMP_SOR_D
3853
    { 1000, 3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #1000 = VFCMP_SNE_S
3854
    { 999,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #999 = VFCMP_SNE_D
3855
    { 998,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #998 = VFCMP_SLT_S
3856
    { 997,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #997 = VFCMP_SLT_D
3857
    { 996,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #996 = VFCMP_SLE_S
3858
    { 995,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #995 = VFCMP_SLE_D
3859
    { 994,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #994 = VFCMP_SEQ_S
3860
    { 993,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #993 = VFCMP_SEQ_D
3861
    { 992,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #992 = VFCMP_SAF_S
3862
    { 991,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #991 = VFCMP_SAF_D
3863
    { 990,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #990 = VFCMP_CUN_S
3864
    { 989,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #989 = VFCMP_CUN_D
3865
    { 988,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #988 = VFCMP_CUNE_S
3866
    { 987,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #987 = VFCMP_CUNE_D
3867
    { 986,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #986 = VFCMP_CULT_S
3868
    { 985,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #985 = VFCMP_CULT_D
3869
    { 984,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #984 = VFCMP_CULE_S
3870
    { 983,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #983 = VFCMP_CULE_D
3871
    { 982,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #982 = VFCMP_CUEQ_S
3872
    { 981,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #981 = VFCMP_CUEQ_D
3873
    { 980,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #980 = VFCMP_COR_S
3874
    { 979,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #979 = VFCMP_COR_D
3875
    { 978,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #978 = VFCMP_CNE_S
3876
    { 977,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #977 = VFCMP_CNE_D
3877
    { 976,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #976 = VFCMP_CLT_S
3878
    { 975,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #975 = VFCMP_CLT_D
3879
    { 974,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #974 = VFCMP_CLE_S
3880
    { 973,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #973 = VFCMP_CLE_D
3881
    { 972,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #972 = VFCMP_CEQ_S
3882
    { 971,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #971 = VFCMP_CEQ_D
3883
    { 970,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #970 = VFCMP_CAF_S
3884
    { 969,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #969 = VFCMP_CAF_D
3885
    { 968,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #968 = VFCLASS_S
3886
    { 967,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #967 = VFCLASS_D
3887
    { 966,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #966 = VFADD_S
3888
    { 965,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #965 = VFADD_D
3889
    { 964,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #964 = VEXTRINS_W
3890
    { 963,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #963 = VEXTRINS_H
3891
    { 962,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #962 = VEXTRINS_D
3892
    { 961,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #961 = VEXTRINS_B
3893
    { 960,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #960 = VEXTL_Q_D
3894
    { 959,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #959 = VEXTL_QU_DU
3895
    { 958,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #958 = VEXTH_W_H
3896
    { 957,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #957 = VEXTH_WU_HU
3897
    { 956,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #956 = VEXTH_Q_D
3898
    { 955,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #955 = VEXTH_QU_DU
3899
    { 954,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #954 = VEXTH_H_B
3900
    { 953,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #953 = VEXTH_HU_BU
3901
    { 952,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #952 = VEXTH_D_W
3902
    { 951,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #951 = VEXTH_DU_WU
3903
    { 950,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #950 = VEXT2XV_W_H
3904
    { 949,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #949 = VEXT2XV_W_B
3905
    { 948,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #948 = VEXT2XV_WU_HU
3906
    { 947,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #947 = VEXT2XV_WU_BU
3907
    { 946,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #946 = VEXT2XV_H_B
3908
    { 945,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #945 = VEXT2XV_HU_BU
3909
    { 944,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #944 = VEXT2XV_D_W
3910
    { 943,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #943 = VEXT2XV_D_H
3911
    { 942,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #942 = VEXT2XV_D_B
3912
    { 941,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #941 = VEXT2XV_DU_WU
3913
    { 940,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #940 = VEXT2XV_DU_HU
3914
    { 939,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 337,  0, 0x0ULL },  // Inst #939 = VEXT2XV_DU_BU
3915
    { 938,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #938 = VDIV_WU
3916
    { 937,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #937 = VDIV_W
3917
    { 936,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #936 = VDIV_HU
3918
    { 935,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #935 = VDIV_H
3919
    { 934,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #934 = VDIV_DU
3920
    { 933,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #933 = VDIV_D
3921
    { 932,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #932 = VDIV_BU
3922
    { 931,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #931 = VDIV_B
3923
    { 930,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #930 = VCLZ_W
3924
    { 929,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #929 = VCLZ_H
3925
    { 928,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #928 = VCLZ_D
3926
    { 927,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #927 = VCLZ_B
3927
    { 926,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #926 = VCLO_W
3928
    { 925,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #925 = VCLO_H
3929
    { 924,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #924 = VCLO_D
3930
    { 923,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 335,  0, 0x0ULL },  // Inst #923 = VCLO_B
3931
    { 922,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #922 = VBSRL_V
3932
    { 921,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #921 = VBSLL_V
3933
    { 920,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #920 = VBITSET_W
3934
    { 919,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #919 = VBITSET_H
3935
    { 918,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #918 = VBITSET_D
3936
    { 917,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #917 = VBITSET_B
3937
    { 916,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #916 = VBITSETI_W
3938
    { 915,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #915 = VBITSETI_H
3939
    { 914,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #914 = VBITSETI_D
3940
    { 913,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #913 = VBITSETI_B
3941
    { 912,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 331,  0, 0x0ULL },  // Inst #912 = VBITSEL_V
3942
    { 911,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 327,  0, 0x0ULL },  // Inst #911 = VBITSELI_B
3943
    { 910,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #910 = VBITREV_W
3944
    { 909,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #909 = VBITREV_H
3945
    { 908,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #908 = VBITREV_D
3946
    { 907,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #907 = VBITREV_B
3947
    { 906,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #906 = VBITREVI_W
3948
    { 905,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #905 = VBITREVI_H
3949
    { 904,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #904 = VBITREVI_D
3950
    { 903,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #903 = VBITREVI_B
3951
    { 902,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #902 = VBITCLR_W
3952
    { 901,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #901 = VBITCLR_H
3953
    { 900,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #900 = VBITCLR_D
3954
    { 899,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #899 = VBITCLR_B
3955
    { 898,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #898 = VBITCLRI_W
3956
    { 897,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #897 = VBITCLRI_H
3957
    { 896,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #896 = VBITCLRI_D
3958
    { 895,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #895 = VBITCLRI_B
3959
    { 894,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #894 = VAVG_WU
3960
    { 893,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #893 = VAVG_W
3961
    { 892,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #892 = VAVG_HU
3962
    { 891,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #891 = VAVG_H
3963
    { 890,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #890 = VAVG_DU
3964
    { 889,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #889 = VAVG_D
3965
    { 888,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #888 = VAVG_BU
3966
    { 887,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #887 = VAVG_B
3967
    { 886,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #886 = VAVGR_WU
3968
    { 885,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #885 = VAVGR_W
3969
    { 884,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #884 = VAVGR_HU
3970
    { 883,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #883 = VAVGR_H
3971
    { 882,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #882 = VAVGR_DU
3972
    { 881,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #881 = VAVGR_D
3973
    { 880,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #880 = VAVGR_BU
3974
    { 879,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #879 = VAVGR_B
3975
    { 878,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #878 = VAND_V
3976
    { 877,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #877 = VANDN_V
3977
    { 876,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #876 = VANDI_B
3978
    { 875,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #875 = VADD_W
3979
    { 874,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #874 = VADD_Q
3980
    { 873,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #873 = VADD_H
3981
    { 872,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #872 = VADD_D
3982
    { 871,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #871 = VADD_B
3983
    { 870,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #870 = VADDWOD_W_HU_H
3984
    { 869,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #869 = VADDWOD_W_HU
3985
    { 868,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #868 = VADDWOD_W_H
3986
    { 867,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #867 = VADDWOD_Q_DU_D
3987
    { 866,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #866 = VADDWOD_Q_DU
3988
    { 865,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #865 = VADDWOD_Q_D
3989
    { 864,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #864 = VADDWOD_H_BU_B
3990
    { 863,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #863 = VADDWOD_H_BU
3991
    { 862,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #862 = VADDWOD_H_B
3992
    { 861,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #861 = VADDWOD_D_WU_W
3993
    { 860,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #860 = VADDWOD_D_WU
3994
    { 859,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #859 = VADDWOD_D_W
3995
    { 858,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #858 = VADDWEV_W_HU_H
3996
    { 857,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #857 = VADDWEV_W_HU
3997
    { 856,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #856 = VADDWEV_W_H
3998
    { 855,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #855 = VADDWEV_Q_DU_D
3999
    { 854,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #854 = VADDWEV_Q_DU
4000
    { 853,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #853 = VADDWEV_Q_D
4001
    { 852,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #852 = VADDWEV_H_BU_B
4002
    { 851,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #851 = VADDWEV_H_BU
4003
    { 850,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #850 = VADDWEV_H_B
4004
    { 849,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #849 = VADDWEV_D_WU_W
4005
    { 848,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #848 = VADDWEV_D_WU
4006
    { 847,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #847 = VADDWEV_D_W
4007
    { 846,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #846 = VADDI_WU
4008
    { 845,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #845 = VADDI_HU
4009
    { 844,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #844 = VADDI_DU
4010
    { 843,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 324,  0, 0x0ULL },  // Inst #843 = VADDI_BU
4011
    { 842,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #842 = VADDA_W
4012
    { 841,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #841 = VADDA_H
4013
    { 840,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #840 = VADDA_D
4014
    { 839,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #839 = VADDA_B
4015
    { 838,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #838 = VABSD_WU
4016
    { 837,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #837 = VABSD_W
4017
    { 836,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #836 = VABSD_HU
4018
    { 835,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #835 = VABSD_H
4019
    { 834,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #834 = VABSD_DU
4020
    { 833,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #833 = VABSD_D
4021
    { 832,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #832 = VABSD_BU
4022
    { 831,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 321,  0, 0x0ULL },  // Inst #831 = VABSD_B
4023
    { 830,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #830 = TLBWR
4024
    { 829,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #829 = TLBSRCH
4025
    { 828,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #828 = TLBRD
4026
    { 827,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #827 = TLBFLUSH
4027
    { 826,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #826 = TLBFILL
4028
    { 825,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #825 = TLBCLR
4029
    { 824,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #824 = SYSCALL
4030
    { 823,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #823 = SUB_W
4031
    { 822,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #822 = SUB_D
4032
    { 821,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #821 = ST_W
4033
    { 820,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #820 = ST_H
4034
    { 819,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #819 = ST_D
4035
    { 818,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #818 = ST_B
4036
    { 817,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #817 = STX_W
4037
    { 816,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #816 = STX_H
4038
    { 815,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #815 = STX_D
4039
    { 814,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #814 = STX_B
4040
    { 813,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #813 = STR_W
4041
    { 812,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #812 = STR_D
4042
    { 811,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #811 = STPTR_W
4043
    { 810,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #810 = STPTR_D
4044
    { 809,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #809 = STL_W
4045
    { 808,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #808 = STL_D
4046
    { 807,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #807 = STLE_W
4047
    { 806,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #806 = STLE_H
4048
    { 805,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #805 = STLE_D
4049
    { 804,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #804 = STLE_B
4050
    { 803,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #803 = STGT_W
4051
    { 802,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #802 = STGT_H
4052
    { 801,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #801 = STGT_D
4053
    { 800,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #800 = STGT_B
4054
    { 799,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #799 = SRL_W
4055
    { 798,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #798 = SRL_D
4056
    { 797,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #797 = SRLI_W
4057
    { 796,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #796 = SRLI_D
4058
    { 795,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #795 = SRA_W
4059
    { 794,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #794 = SRA_D
4060
    { 793,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #793 = SRAI_W
4061
    { 792,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #792 = SRAI_D
4062
    { 791,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #791 = SLTUI
4063
    { 790,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #790 = SLTU
4064
    { 789,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #789 = SLTI
4065
    { 788,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #788 = SLT
4066
    { 787,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #787 = SLL_W
4067
    { 786,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #786 = SLL_D
4068
    { 785,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #785 = SLLI_W
4069
    { 784,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #784 = SLLI_D
4070
    { 783,  1,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 320,  0, 0x0ULL },  // Inst #783 = SET_CFR_TRUE
4071
    { 782,  1,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 320,  0, 0x0ULL },  // Inst #782 = SET_CFR_FALSE
4072
    { 781,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #781 = SETX86LOOPNE
4073
    { 780,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #780 = SETX86LOOPE
4074
    { 779,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #779 = SETX86J
4075
    { 778,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #778 = SETARMJ
4076
    { 777,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 231,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #777 = SC_W
4077
    { 776,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 316,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #776 = SC_Q
4078
    { 775,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 231,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #775 = SC_D
4079
    { 774,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 313,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #774 = SCREL_W
4080
    { 773,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 313,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #773 = SCREL_D
4081
    { 772,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #772 = SBC_W
4082
    { 771,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #771 = SBC_H
4083
    { 770,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #770 = SBC_D
4084
    { 769,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #769 = SBC_B
4085
    { 768,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #768 = ROTR_W
4086
    { 767,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #767 = ROTR_H
4087
    { 766,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #766 = ROTR_D
4088
    { 765,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #765 = ROTR_B
4089
    { 764,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #764 = ROTRI_W
4090
    { 763,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #763 = ROTRI_H
4091
    { 762,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #762 = ROTRI_D
4092
    { 761,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #761 = ROTRI_B
4093
    { 760,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #760 = REVH_D
4094
    { 759,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #759 = REVH_2W
4095
    { 758,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #758 = REVB_D
4096
    { 757,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #757 = REVB_4H
4097
    { 756,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #756 = REVB_2W
4098
    { 755,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #755 = REVB_2H
4099
    { 754,  2,  2,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #754 = RDTIME_D
4100
    { 753,  2,  2,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #753 = RDTIMEL_W
4101
    { 752,  2,  2,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #752 = RDTIMEH_W
4102
    { 751,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #751 = RCR_W
4103
    { 750,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #750 = RCR_H
4104
    { 749,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #749 = RCR_D
4105
    { 748,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #748 = RCR_B
4106
    { 747,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #747 = RCRI_W
4107
    { 746,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #746 = RCRI_H
4108
    { 745,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #745 = RCRI_D
4109
    { 744,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #744 = RCRI_B
4110
    { 743,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 310,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #743 = PRELDX
4111
    { 742,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 225,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #742 = PRELD
4112
    { 741,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #741 = PCALAU12I
4113
    { 740,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #740 = PCADDU18I
4114
    { 739,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #739 = PCADDU12I
4115
    { 738,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #738 = PCADDI
4116
    { 737,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #737 = ORN
4117
    { 736,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #736 = ORI
4118
    { 735,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #735 = OR
4119
    { 734,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #734 = NOR
4120
    { 733,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #733 = MUL_W
4121
    { 732,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #732 = MUL_D
4122
    { 731,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #731 = MULW_D_WU
4123
    { 730,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #730 = MULW_D_W
4124
    { 729,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #729 = MULH_WU
4125
    { 728,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #728 = MULH_W
4126
    { 727,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #727 = MULH_DU
4127
    { 726,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #726 = MULH_D
4128
    { 725,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 308,  0, 0x0ULL },  // Inst #725 = MOVSCR2GR
4129
    { 724,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 306,  0, 0x0ULL },  // Inst #724 = MOVGR2SCR
4130
    { 723,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 302,  0, 0x0ULL },  // Inst #723 = MOVGR2FR_W_64
4131
    { 722,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 304,  0, 0x0ULL },  // Inst #722 = MOVGR2FR_W
4132
    { 721,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 302,  0, 0x0ULL },  // Inst #721 = MOVGR2FR_D
4133
    { 720,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 299,  0, 0x0ULL },  // Inst #720 = MOVGR2FRH_W
4134
    { 719,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 297,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #719 = MOVGR2FCSR
4135
    { 718,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 295,  0, 0x0ULL },  // Inst #718 = MOVGR2CF
4136
    { 717,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 291,  0, 0x0ULL },  // Inst #717 = MOVFRH2GR_S
4137
    { 716,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 291,  0, 0x0ULL },  // Inst #716 = MOVFR2GR_S_64
4138
    { 715,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 293,  0, 0x0ULL },  // Inst #715 = MOVFR2GR_S
4139
    { 714,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 291,  0, 0x0ULL },  // Inst #714 = MOVFR2GR_D
4140
    { 713,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 289,  0, 0x0ULL },  // Inst #713 = MOVFR2CF_xS
4141
    { 712,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 287,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #712 = MOVFCSR2GR
4142
    { 711,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 285,  0, 0x0ULL },  // Inst #711 = MOVCF2GR
4143
    { 710,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 283,  0, 0x0ULL },  // Inst #710 = MOVCF2FR_xS
4144
    { 709,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #709 = MOD_WU
4145
    { 708,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #708 = MOD_W
4146
    { 707,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #707 = MOD_DU
4147
    { 706,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #706 = MOD_D
4148
    { 705,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #705 = MASKNEZ
4149
    { 704,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #704 = MASKEQZ
4150
    { 703,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #703 = LU52I_D
4151
    { 702,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 228,  0, 0x0ULL },  // Inst #702 = LU32I_D
4152
    { 701,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #701 = LU12I_W
4153
    { 700,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #700 = LL_W
4154
    { 699,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #699 = LL_D
4155
    { 698,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #698 = LLACQ_W
4156
    { 697,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #697 = LLACQ_D
4157
    { 696,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #696 = LD_WU
4158
    { 695,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #695 = LD_W
4159
    { 694,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #694 = LD_HU
4160
    { 693,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #693 = LD_H
4161
    { 692,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #692 = LD_D
4162
    { 691,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #691 = LD_BU
4163
    { 690,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #690 = LD_B
4164
    { 689,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #689 = LDX_WU
4165
    { 688,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #688 = LDX_W
4166
    { 687,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #687 = LDX_HU
4167
    { 686,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #686 = LDX_H
4168
    { 685,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #685 = LDX_D
4169
    { 684,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #684 = LDX_BU
4170
    { 683,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #683 = LDX_B
4171
    { 682,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #682 = LDR_W
4172
    { 681,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #681 = LDR_D
4173
    { 680,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #680 = LDPTR_W
4174
    { 679,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #679 = LDPTR_D
4175
    { 678,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #678 = LDPTE
4176
    { 677,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #677 = LDL_W
4177
    { 676,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #676 = LDL_D
4178
    { 675,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #675 = LDLE_W
4179
    { 674,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #674 = LDLE_H
4180
    { 673,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #673 = LDLE_D
4181
    { 672,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #672 = LDLE_B
4182
    { 671,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #671 = LDGT_W
4183
    { 670,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #670 = LDGT_H
4184
    { 669,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #669 = LDGT_D
4185
    { 668,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #668 = LDGT_B
4186
    { 667,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #667 = LDDIR
4187
    { 666,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0, 0x0ULL },  // Inst #666 = JISCR1
4188
    { 665,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0, 0x0ULL },  // Inst #665 = JISCR0
4189
    { 664,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #664 = JIRL
4190
    { 663,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #663 = IOCSRWR_W
4191
    { 662,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #662 = IOCSRWR_H
4192
    { 661,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #661 = IOCSRWR_D
4193
    { 660,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #660 = IOCSRWR_B
4194
    { 659,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #659 = IOCSRRD_W
4195
    { 658,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #658 = IOCSRRD_H
4196
    { 657,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #657 = IOCSRRD_D
4197
    { 656,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #656 = IOCSRRD_B
4198
    { 655,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #655 = INVTLB
4199
    { 654,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #654 = IDLE
4200
    { 653,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #653 = IBAR
4201
    { 652,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #652 = HVCL
4202
    { 651,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #651 = GTLBFLUSH
4203
    { 650,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 231,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #650 = GCSRXCHG
4204
    { 649,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 228,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #649 = GCSRWR
4205
    { 648,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #648 = GCSRRD
4206
    { 647,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #647 = FTINT_W_S
4207
    { 646,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #646 = FTINT_W_D
4208
    { 645,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #645 = FTINT_L_S
4209
    { 644,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #644 = FTINT_L_D
4210
    { 643,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #643 = FTINTRZ_W_S
4211
    { 642,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #642 = FTINTRZ_W_D
4212
    { 641,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #641 = FTINTRZ_L_S
4213
    { 640,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #640 = FTINTRZ_L_D
4214
    { 639,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #639 = FTINTRP_W_S
4215
    { 638,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #638 = FTINTRP_W_D
4216
    { 637,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #637 = FTINTRP_L_S
4217
    { 636,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #636 = FTINTRP_L_D
4218
    { 635,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #635 = FTINTRNE_W_S
4219
    { 634,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #634 = FTINTRNE_W_D
4220
    { 633,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #633 = FTINTRNE_L_S
4221
    { 632,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #632 = FTINTRNE_L_D
4222
    { 631,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #631 = FTINTRM_W_S
4223
    { 630,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #630 = FTINTRM_W_D
4224
    { 629,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #629 = FTINTRM_L_S
4225
    { 628,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #628 = FTINTRM_L_D
4226
    { 627,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #627 = FSUB_S
4227
    { 626,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #626 = FSUB_D
4228
    { 625,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 264,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #625 = FST_S
4229
    { 624,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 261,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #624 = FST_D
4230
    { 623,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 258,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #623 = FSTX_S
4231
    { 622,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 255,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #622 = FSTX_D
4232
    { 621,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 258,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #621 = FSTLE_S
4233
    { 620,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 255,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #620 = FSTLE_D
4234
    { 619,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 258,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #619 = FSTGT_S
4235
    { 618,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 255,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #618 = FSTGT_D
4236
    { 617,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #617 = FSQRT_S
4237
    { 616,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #616 = FSQRT_D
4238
    { 615,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 279,  0, 0x0ULL },  // Inst #615 = FSEL_xS
4239
    { 614,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 275,  0, 0x0ULL },  // Inst #614 = FSEL_xD
4240
    { 613,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #613 = FSCALEB_S
4241
    { 612,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #612 = FSCALEB_D
4242
    { 611,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #611 = FRSQRT_S
4243
    { 610,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #610 = FRSQRT_D
4244
    { 609,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #609 = FRSQRTE_S
4245
    { 608,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #608 = FRSQRTE_D
4246
    { 607,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #607 = FRINT_S
4247
    { 606,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #606 = FRINT_D
4248
    { 605,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #605 = FRECIP_S
4249
    { 604,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #604 = FRECIP_D
4250
    { 603,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #603 = FRECIPE_S
4251
    { 602,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #602 = FRECIPE_D
4252
    { 601,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 271,  0, 0x0ULL },  // Inst #601 = FNMSUB_S
4253
    { 600,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 267,  0, 0x0ULL },  // Inst #600 = FNMSUB_D
4254
    { 599,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 271,  0, 0x0ULL },  // Inst #599 = FNMADD_S
4255
    { 598,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 267,  0, 0x0ULL },  // Inst #598 = FNMADD_D
4256
    { 597,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #597 = FNEG_S
4257
    { 596,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #596 = FNEG_D
4258
    { 595,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #595 = FMUL_S
4259
    { 594,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #594 = FMUL_D
4260
    { 593,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 271,  0, 0x0ULL },  // Inst #593 = FMSUB_S
4261
    { 592,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 267,  0, 0x0ULL },  // Inst #592 = FMSUB_D
4262
    { 591,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #591 = FMOV_S
4263
    { 590,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #590 = FMOV_D
4264
    { 589,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #589 = FMIN_S
4265
    { 588,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #588 = FMIN_D
4266
    { 587,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #587 = FMINA_S
4267
    { 586,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #586 = FMINA_D
4268
    { 585,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #585 = FMAX_S
4269
    { 584,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #584 = FMAX_D
4270
    { 583,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #583 = FMAXA_S
4271
    { 582,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #582 = FMAXA_D
4272
    { 581,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 271,  0, 0x0ULL },  // Inst #581 = FMADD_S
4273
    { 580,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 267,  0, 0x0ULL },  // Inst #580 = FMADD_D
4274
    { 579,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #579 = FLOGB_S
4275
    { 578,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #578 = FLOGB_D
4276
    { 577,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 264,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #577 = FLD_S
4277
    { 576,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 261,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #576 = FLD_D
4278
    { 575,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 258,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #575 = FLDX_S
4279
    { 574,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 255,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #574 = FLDX_D
4280
    { 573,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 258,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #573 = FLDLE_S
4281
    { 572,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 255,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #572 = FLDLE_D
4282
    { 571,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 258,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #571 = FLDGT_S
4283
    { 570,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 255,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #570 = FLDGT_D
4284
    { 569,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #569 = FFINT_S_W
4285
    { 568,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #568 = FFINT_S_L
4286
    { 567,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #567 = FFINT_D_W
4287
    { 566,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #566 = FFINT_D_L
4288
    { 565,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #565 = FDIV_S
4289
    { 564,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #564 = FDIV_D
4290
    { 563,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #563 = FCVT_UD_D
4291
    { 562,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 253,  0, 0x0ULL },  // Inst #562 = FCVT_S_D
4292
    { 561,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #561 = FCVT_LD_D
4293
    { 560,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 251,  0, 0x0ULL },  // Inst #560 = FCVT_D_S
4294
    { 559,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #559 = FCVT_D_LD
4295
    { 558,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #558 = FCOPYSIGN_S
4296
    { 557,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #557 = FCOPYSIGN_D
4297
    { 556,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #556 = FCMP_SUN_S
4298
    { 555,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #555 = FCMP_SUN_D
4299
    { 554,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #554 = FCMP_SUNE_S
4300
    { 553,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #553 = FCMP_SUNE_D
4301
    { 552,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #552 = FCMP_SULT_S
4302
    { 551,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #551 = FCMP_SULT_D
4303
    { 550,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #550 = FCMP_SULE_S
4304
    { 549,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #549 = FCMP_SULE_D
4305
    { 548,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #548 = FCMP_SUEQ_S
4306
    { 547,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #547 = FCMP_SUEQ_D
4307
    { 546,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #546 = FCMP_SOR_S
4308
    { 545,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #545 = FCMP_SOR_D
4309
    { 544,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #544 = FCMP_SNE_S
4310
    { 543,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #543 = FCMP_SNE_D
4311
    { 542,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #542 = FCMP_SLT_S
4312
    { 541,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #541 = FCMP_SLT_D
4313
    { 540,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #540 = FCMP_SLE_S
4314
    { 539,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #539 = FCMP_SLE_D
4315
    { 538,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #538 = FCMP_SEQ_S
4316
    { 537,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #537 = FCMP_SEQ_D
4317
    { 536,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #536 = FCMP_SAF_S
4318
    { 535,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #535 = FCMP_SAF_D
4319
    { 534,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #534 = FCMP_CUN_S
4320
    { 533,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #533 = FCMP_CUN_D
4321
    { 532,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #532 = FCMP_CUNE_S
4322
    { 531,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #531 = FCMP_CUNE_D
4323
    { 530,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #530 = FCMP_CULT_S
4324
    { 529,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #529 = FCMP_CULT_D
4325
    { 528,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #528 = FCMP_CULE_S
4326
    { 527,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #527 = FCMP_CULE_D
4327
    { 526,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #526 = FCMP_CUEQ_S
4328
    { 525,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #525 = FCMP_CUEQ_D
4329
    { 524,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #524 = FCMP_COR_S
4330
    { 523,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #523 = FCMP_COR_D
4331
    { 522,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #522 = FCMP_CNE_S
4332
    { 521,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #521 = FCMP_CNE_D
4333
    { 520,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #520 = FCMP_CLT_S
4334
    { 519,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #519 = FCMP_CLT_D
4335
    { 518,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #518 = FCMP_CLE_S
4336
    { 517,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #517 = FCMP_CLE_D
4337
    { 516,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #516 = FCMP_CEQ_S
4338
    { 515,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #515 = FCMP_CEQ_D
4339
    { 514,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 248,  0, 0x0ULL },  // Inst #514 = FCMP_CAF_S
4340
    { 513,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 245,  0, 0x0ULL },  // Inst #513 = FCMP_CAF_D
4341
    { 512,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #512 = FCLASS_S
4342
    { 511,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #511 = FCLASS_D
4343
    { 510,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #510 = FADD_S
4344
    { 509,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 239,  0, 0x0ULL },  // Inst #509 = FADD_D
4345
    { 508,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #508 = FABS_S
4346
    { 507,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 235,  0, 0x0ULL },  // Inst #507 = FABS_D
4347
    { 506,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #506 = EXT_W_H
4348
    { 505,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #505 = EXT_W_B
4349
    { 504,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #504 = ERTN
4350
    { 503,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #503 = DIV_WU
4351
    { 502,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #502 = DIV_W
4352
    { 501,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #501 = DIV_DU
4353
    { 500,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #500 = DIV_D
4354
    { 499,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #499 = DBCL
4355
    { 498,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #498 = DBAR
4356
    { 497,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #497 = CTZ_W
4357
    { 496,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #496 = CTZ_D
4358
    { 495,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #495 = CTO_W
4359
    { 494,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #494 = CTO_D
4360
    { 493,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 231,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #493 = CSRXCHG
4361
    { 492,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 228,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #492 = CSRWR
4362
    { 491,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #491 = CSRRD
4363
    { 490,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #490 = CRC_W_W_W
4364
    { 489,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #489 = CRC_W_H_W
4365
    { 488,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #488 = CRC_W_D_W
4366
    { 487,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #487 = CRC_W_B_W
4367
    { 486,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #486 = CRCC_W_W_W
4368
    { 485,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #485 = CRCC_W_H_W
4369
    { 484,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #484 = CRCC_W_D_W
4370
    { 483,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #483 = CRCC_W_B_W
4371
    { 482,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #482 = CPUCFG
4372
    { 481,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #481 = CLZ_W
4373
    { 480,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #480 = CLZ_D
4374
    { 479,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #479 = CLO_W
4375
    { 478,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #478 = CLO_D
4376
    { 477,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 225,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #477 = CACOP
4377
    { 476,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #476 = BYTEPICK_W
4378
    { 475,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #475 = BYTEPICK_D
4379
    { 474,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 221,  0, 0x0ULL },  // Inst #474 = BSTRPICK_W
4380
    { 473,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 221,  0, 0x0ULL },  // Inst #473 = BSTRPICK_D
4381
    { 472,  5,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 216,  0, 0x0ULL },  // Inst #472 = BSTRINS_W
4382
    { 471,  5,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 216,  0, 0x0ULL },  // Inst #471 = BSTRINS_D
4383
    { 470,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #470 = BREAK
4384
    { 469,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #469 = BNEZ
4385
    { 468,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #468 = BNE
4386
    { 467,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #467 = BLTU
4387
    { 466,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #466 = BLT
4388
    { 465,  1,  0,  4,  0,  0,  1,  LoongArchImpOpBase + 3, 0,  0|(1ULL<<MCID::Call), 0x0ULL },  // Inst #465 = BL
4389
    { 464,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #464 = BITREV_W
4390
    { 463,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #463 = BITREV_D
4391
    { 462,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #462 = BITREV_8B
4392
    { 461,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0, 0x0ULL },  // Inst #461 = BITREV_4B
4393
    { 460,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #460 = BGEU
4394
    { 459,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #459 = BGE
4395
    { 458,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #458 = BEQZ
4396
    { 457,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #457 = BEQ
4397
    { 456,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 214,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #456 = BCNEZ
4398
    { 455,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 214,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #455 = BCEQZ
4399
    { 454,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #454 = B
4400
    { 453,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #453 = ASRTLE_D
4401
    { 452,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 212,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #452 = ASRTGT_D
4402
    { 451,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #451 = ARMXOR_W
4403
    { 450,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #450 = ARMSUB_W
4404
    { 449,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #449 = ARMSRL_W
4405
    { 448,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #448 = ARMSRLI_W
4406
    { 447,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #447 = ARMSRA_W
4407
    { 446,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #446 = ARMSRAI_W
4408
    { 445,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #445 = ARMSLL_W
4409
    { 444,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #444 = ARMSLLI_W
4410
    { 443,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #443 = ARMSBC_W
4411
    { 442,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #442 = ARMRRX_W
4412
    { 441,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #441 = ARMROTR_W
4413
    { 440,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #440 = ARMROTRI_W
4414
    { 439,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #439 = ARMOR_W
4415
    { 438,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #438 = ARMNOT_W
4416
    { 437,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #437 = ARMMTFLAG
4417
    { 436,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #436 = ARMMOV_W
4418
    { 435,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #435 = ARMMOV_D
4419
    { 434,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #434 = ARMMOVE
4420
    { 433,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0, 0x0ULL },  // Inst #433 = ARMMFFLAG
4421
    { 432,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #432 = ARMAND_W
4422
    { 431,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #431 = ARMADD_W
4423
    { 430,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #430 = ARMADC_W
4424
    { 429,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #429 = ANDN
4425
    { 428,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #428 = ANDI
4426
    { 427,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #427 = AND
4427
    { 426,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #426 = AMXOR__DB_W
4428
    { 425,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #425 = AMXOR__DB_D
4429
    { 424,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #424 = AMXOR_W
4430
    { 423,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #423 = AMXOR_D
4431
    { 422,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #422 = AMSWAP__DB_W
4432
    { 421,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #421 = AMSWAP__DB_H
4433
    { 420,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #420 = AMSWAP__DB_D
4434
    { 419,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #419 = AMSWAP__DB_B
4435
    { 418,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #418 = AMSWAP_W
4436
    { 417,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #417 = AMSWAP_H
4437
    { 416,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #416 = AMSWAP_D
4438
    { 415,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #415 = AMSWAP_B
4439
    { 414,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #414 = AMOR__DB_W
4440
    { 413,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #413 = AMOR__DB_D
4441
    { 412,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #412 = AMOR_W
4442
    { 411,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #411 = AMOR_D
4443
    { 410,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #410 = AMMIN__DB_WU
4444
    { 409,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #409 = AMMIN__DB_W
4445
    { 408,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #408 = AMMIN__DB_DU
4446
    { 407,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #407 = AMMIN__DB_D
4447
    { 406,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #406 = AMMIN_WU
4448
    { 405,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #405 = AMMIN_W
4449
    { 404,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #404 = AMMIN_DU
4450
    { 403,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #403 = AMMIN_D
4451
    { 402,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #402 = AMMAX__DB_WU
4452
    { 401,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #401 = AMMAX__DB_W
4453
    { 400,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #400 = AMMAX__DB_DU
4454
    { 399,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #399 = AMMAX__DB_D
4455
    { 398,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #398 = AMMAX_WU
4456
    { 397,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #397 = AMMAX_W
4457
    { 396,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #396 = AMMAX_DU
4458
    { 395,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #395 = AMMAX_D
4459
    { 394,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #394 = AMCAS__DB_W
4460
    { 393,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #393 = AMCAS__DB_H
4461
    { 392,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #392 = AMCAS__DB_D
4462
    { 391,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #391 = AMCAS__DB_B
4463
    { 390,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #390 = AMCAS_W
4464
    { 389,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #389 = AMCAS_H
4465
    { 388,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #388 = AMCAS_D
4466
    { 387,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #387 = AMCAS_B
4467
    { 386,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #386 = AMAND__DB_W
4468
    { 385,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #385 = AMAND__DB_D
4469
    { 384,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #384 = AMAND_W
4470
    { 383,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #383 = AMAND_D
4471
    { 382,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #382 = AMADD__DB_W
4472
    { 381,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #381 = AMADD__DB_H
4473
    { 380,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #380 = AMADD__DB_D
4474
    { 379,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #379 = AMADD__DB_B
4475
    { 378,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #378 = AMADD_W
4476
    { 377,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #377 = AMADD_H
4477
    { 376,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #376 = AMADD_D
4478
    { 375,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #375 = AMADD_B
4479
    { 374,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #374 = ALSL_WU
4480
    { 373,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #373 = ALSL_W
4481
    { 372,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #372 = ALSL_D
4482
    { 371,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #371 = ADD_W
4483
    { 370,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #370 = ADD_D
4484
    { 369,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #369 = ADDU16I_D
4485
    { 368,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #368 = ADDU12I_W
4486
    { 367,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #367 = ADDU12I_D
4487
    { 366,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #366 = ADDI_W
4488
    { 365,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0, 0x0ULL },  // Inst #365 = ADDI_D
4489
    { 364,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #364 = ADC_W
4490
    { 363,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #363 = ADC_H
4491
    { 362,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #362 = ADC_D
4492
    { 361,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0, 0x0ULL },  // Inst #361 = ADC_B
4493
    { 360,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 200,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #360 = WRFCSR
4494
    { 359,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #359 = RDFCSR
4495
    { 358,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 198,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #358 = PseudoXVREPLI_W
4496
    { 357,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 198,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #357 = PseudoXVREPLI_H
4497
    { 356,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 198,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #356 = PseudoXVREPLI_D
4498
    { 355,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 198,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #355 = PseudoXVREPLI_B
4499
    { 354,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 194,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #354 = PseudoXVINSGR2VR_H
4500
    { 353,  4,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 194,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #353 = PseudoXVINSGR2VR_B
4501
    { 352,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #352 = PseudoXVBZ_W
4502
    { 351,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #351 = PseudoXVBZ_H
4503
    { 350,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #350 = PseudoXVBZ_D
4504
    { 349,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #349 = PseudoXVBZ_B
4505
    { 348,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #348 = PseudoXVBZ
4506
    { 347,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #347 = PseudoXVBNZ_W
4507
    { 346,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #346 = PseudoXVBNZ_H
4508
    { 345,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #345 = PseudoXVBNZ_D
4509
    { 344,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #344 = PseudoXVBNZ_B
4510
    { 343,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 192,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #343 = PseudoXVBNZ
4511
    { 342,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 190,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #342 = PseudoVREPLI_W
4512
    { 341,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 190,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #341 = PseudoVREPLI_H
4513
    { 340,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 190,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #340 = PseudoVREPLI_D
4514
    { 339,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 190,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #339 = PseudoVREPLI_B
4515
    { 338,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #338 = PseudoVBZ_W
4516
    { 337,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #337 = PseudoVBZ_H
4517
    { 336,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #336 = PseudoVBZ_D
4518
    { 335,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #335 = PseudoVBZ_B
4519
    { 334,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #334 = PseudoVBZ
4520
    { 333,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #333 = PseudoVBNZ_W
4521
    { 332,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #332 = PseudoVBNZ_H
4522
    { 331,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #331 = PseudoVBNZ_D
4523
    { 330,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #330 = PseudoVBNZ_B
4524
    { 329,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 188,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #329 = PseudoVBNZ
4525
    { 328,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #328 = PseudoUNIMP
4526
    { 327,  1,  0,  8,  0,  1,  1,  LoongArchImpOpBase + 10,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #327 = PseudoTAIL_MEDIUM
4527
    { 326,  1,  0,  24, 0,  1,  2,  LoongArchImpOpBase + 7, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #326 = PseudoTAIL_LARGE
4528
    { 325,  1,  0,  4,  0,  1,  0,  LoongArchImpOpBase + 2, 187,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #325 = PseudoTAILIndirect
4529
    { 324,  2,  0,  8,  0,  1,  0,  LoongArchImpOpBase + 2, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #324 = PseudoTAIL36
4530
    { 323,  1,  0,  4,  0,  1,  0,  LoongArchImpOpBase + 2, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #323 = PseudoTAIL
4531
    { 322,  3,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #322 = PseudoST_CFR
4532
    { 321,  0,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #321 = PseudoRET
4533
    { 320,  7,  2,  44, 0,  0,  0,  LoongArchImpOpBase + 0, 180,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #320 = PseudoMaskedCmpXchg32
4534
    { 319,  6,  2,  36, 0,  0,  0,  LoongArchImpOpBase + 0, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #319 = PseudoMaskedAtomicSwap32
4535
    { 318,  7,  3,  48, 0,  0,  0,  LoongArchImpOpBase + 0, 173,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #318 = PseudoMaskedAtomicLoadUMin32
4536
    { 317,  7,  3,  48, 0,  0,  0,  LoongArchImpOpBase + 0, 173,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #317 = PseudoMaskedAtomicLoadUMax32
4537
    { 316,  6,  2,  36, 0,  0,  0,  LoongArchImpOpBase + 0, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #316 = PseudoMaskedAtomicLoadSub32
4538
    { 315,  6,  2,  36, 0,  0,  0,  LoongArchImpOpBase + 0, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #315 = PseudoMaskedAtomicLoadNand32
4539
    { 314,  8,  3,  56, 0,  0,  0,  LoongArchImpOpBase + 0, 165,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #314 = PseudoMaskedAtomicLoadMin32
4540
    { 313,  8,  3,  56, 0,  0,  0,  LoongArchImpOpBase + 0, 165,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #313 = PseudoMaskedAtomicLoadMax32
4541
    { 312,  6,  2,  36, 0,  0,  0,  LoongArchImpOpBase + 0, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #312 = PseudoMaskedAtomicLoadAdd32
4542
    { 311,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #311 = PseudoLI_W
4543
    { 310,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #310 = PseudoLI_D
4544
    { 309,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 162,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #309 = PseudoLD_CFR
4545
    { 308,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #308 = PseudoLA_TLS_LE
4546
    { 307,  3,  1,  20, 0,  0,  1,  LoongArchImpOpBase + 6, 159,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #307 = PseudoLA_TLS_LD_LARGE
4547
    { 306,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #306 = PseudoLA_TLS_LD
4548
    { 305,  3,  1,  20, 0,  0,  1,  LoongArchImpOpBase + 6, 159,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #305 = PseudoLA_TLS_IE_LARGE
4549
    { 304,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #304 = PseudoLA_TLS_IE
4550
    { 303,  3,  1,  20, 0,  0,  1,  LoongArchImpOpBase + 6, 159,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #303 = PseudoLA_TLS_GD_LARGE
4551
    { 302,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #302 = PseudoLA_TLS_GD
4552
    { 301,  3,  1,  20, 0,  0,  1,  LoongArchImpOpBase + 6, 159,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #301 = PseudoLA_PCREL_LARGE
4553
    { 300,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #300 = PseudoLA_PCREL
4554
    { 299,  3,  1,  20, 0,  0,  1,  LoongArchImpOpBase + 6, 159,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #299 = PseudoLA_GOT_LARGE
4555
    { 298,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #298 = PseudoLA_GOT
4556
    { 297,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 159,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #297 = PseudoLA_ABS_LARGE
4557
    { 296,  2,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #296 = PseudoLA_ABS
4558
    { 295,  2,  0,  4,  0,  1,  0,  LoongArchImpOpBase + 2, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #295 = PseudoJIRL_TAIL
4559
    { 294,  2,  0,  4,  0,  0,  1,  LoongArchImpOpBase + 3, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL },  // Inst #294 = PseudoJIRL_CALL
4560
    { 293,  2,  1,  12, 0,  0,  0,  LoongArchImpOpBase + 0, 157,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #293 = PseudoCopyCFR
4561
    { 292,  6,  2,  36, 0,  0,  0,  LoongArchImpOpBase + 0, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #292 = PseudoCmpXchg64
4562
    { 291,  6,  2,  36, 0,  0,  0,  LoongArchImpOpBase + 0, 151,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #291 = PseudoCmpXchg32
4563
    { 290,  1,  0,  8,  0,  0,  2,  LoongArchImpOpBase + 4, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL },  // Inst #290 = PseudoCALL_MEDIUM
4564
    { 289,  1,  0,  24, 0,  0,  2,  LoongArchImpOpBase + 4, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL },  // Inst #289 = PseudoCALL_LARGE
4565
    { 288,  1,  0,  4,  0,  0,  1,  LoongArchImpOpBase + 3, 150,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL },  // Inst #288 = PseudoCALLIndirect
4566
    { 287,  1,  0,  8,  0,  0,  1,  LoongArchImpOpBase + 3, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call), 0x0ULL },  // Inst #287 = PseudoCALL36
4567
    { 286,  1,  0,  4,  0,  0,  1,  LoongArchImpOpBase + 3, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x0ULL },  // Inst #286 = PseudoCALL
4568
    { 285,  1,  0,  4,  0,  1,  0,  LoongArchImpOpBase + 2, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #285 = PseudoB_TAIL
4569
    { 284,  2,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #284 = PseudoBRIND
4570
    { 283,  1,  0,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #283 = PseudoBR
4571
    { 282,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #282 = PseudoAtomicSwap32
4572
    { 281,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #281 = PseudoAtomicStoreW
4573
    { 280,  3,  1,  4,  0,  0,  0,  LoongArchImpOpBase + 0, 145,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #280 = PseudoAtomicStoreD
4574
    { 279,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #279 = PseudoAtomicLoadXor32
4575
    { 278,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #278 = PseudoAtomicLoadSub32
4576
    { 277,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #277 = PseudoAtomicLoadOr32
4577
    { 276,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #276 = PseudoAtomicLoadNand64
4578
    { 275,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #275 = PseudoAtomicLoadNand32
4579
    { 274,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #274 = PseudoAtomicLoadAnd32
4580
    { 273,  5,  2,  24, 0,  0,  0,  LoongArchImpOpBase + 0, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #273 = PseudoAtomicLoadAdd32
4581
    { 272,  2,  0,  4,  0,  1,  1,  LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #272 = ADJCALLSTACKUP
4582
    { 271,  2,  0,  4,  0,  1,  1,  LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #271 = ADJCALLSTACKDOWN
4583
    { 270,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #270 = G_UBFX
4584
    { 269,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #269 = G_SBFX
4585
    { 268,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
4586
    { 267,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
4587
    { 266,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
4588
    { 265,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
4589
    { 264,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
4590
    { 263,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
4591
    { 262,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
4592
    { 261,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
4593
    { 260,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
4594
    { 259,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
4595
    { 258,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
4596
    { 257,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
4597
    { 256,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
4598
    { 255,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
4599
    { 254,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
4600
    { 253,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
4601
    { 252,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
4602
    { 251,  3,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #251 = G_BZERO
4603
    { 250,  4,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #250 = G_MEMSET
4604
    { 249,  4,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #249 = G_MEMMOVE
4605
    { 248,  3,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
4606
    { 247,  4,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #247 = G_MEMCPY
4607
    { 246,  2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
4608
    { 245,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
4609
    { 244,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
4610
    { 243,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
4611
    { 242,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #242 = G_STRICT_FMA
4612
    { 241,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #241 = G_STRICT_FREM
4613
    { 240,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
4614
    { 239,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
4615
    { 238,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
4616
    { 237,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #237 = G_STRICT_FADD
4617
    { 236,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #236 = G_STACKRESTORE
4618
    { 235,  1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #235 = G_STACKSAVE
4619
    { 234,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
4620
    { 233,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
4621
    { 232,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
4622
    { 231,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
4623
    { 230,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #230 = G_FNEARBYINT
4624
    { 229,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #229 = G_FRINT
4625
    { 228,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #228 = G_FFLOOR
4626
    { 227,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #227 = G_FSQRT
4627
    { 226,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #226 = G_FSIN
4628
    { 225,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #225 = G_FCOS
4629
    { 224,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #224 = G_FCEIL
4630
    { 223,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #223 = G_BITREVERSE
4631
    { 222,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #222 = G_BSWAP
4632
    { 221,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #221 = G_CTPOP
4633
    { 220,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
4634
    { 219,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #219 = G_CTLZ
4635
    { 218,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
4636
    { 217,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #217 = G_CTTZ
4637
    { 216,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
4638
    { 215,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
4639
    { 214,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
4640
    { 213,  3,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #213 = G_BRJT
4641
    { 212,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #212 = G_BR
4642
    { 211,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #211 = G_LLROUND
4643
    { 210,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #210 = G_LROUND
4644
    { 209,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #209 = G_ABS
4645
    { 208,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #208 = G_UMAX
4646
    { 207,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #207 = G_UMIN
4647
    { 206,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #206 = G_SMAX
4648
    { 205,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #205 = G_SMIN
4649
    { 204,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #204 = G_PTRMASK
4650
    { 203,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #203 = G_PTR_ADD
4651
    { 202,  0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
4652
    { 201,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #201 = G_SET_FPMODE
4653
    { 200,  1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #200 = G_GET_FPMODE
4654
    { 199,  0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #199 = G_RESET_FPENV
4655
    { 198,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #198 = G_SET_FPENV
4656
    { 197,  1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #197 = G_GET_FPENV
4657
    { 196,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #196 = G_FMAXIMUM
4658
    { 195,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #195 = G_FMINIMUM
4659
    { 194,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
4660
    { 193,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
4661
    { 192,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #192 = G_FMAXNUM
4662
    { 191,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #191 = G_FMINNUM
4663
    { 190,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
4664
    { 189,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
4665
    { 188,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
4666
    { 187,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #187 = G_FABS
4667
    { 186,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #186 = G_UITOFP
4668
    { 185,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #185 = G_SITOFP
4669
    { 184,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #184 = G_FPTOUI
4670
    { 183,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #183 = G_FPTOSI
4671
    { 182,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #182 = G_FPTRUNC
4672
    { 181,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #181 = G_FPEXT
4673
    { 180,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #180 = G_FNEG
4674
    { 179,  3,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #179 = G_FFREXP
4675
    { 178,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #178 = G_FLDEXP
4676
    { 177,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #177 = G_FLOG10
4677
    { 176,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #176 = G_FLOG2
4678
    { 175,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #175 = G_FLOG
4679
    { 174,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #174 = G_FEXP10
4680
    { 173,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #173 = G_FEXP2
4681
    { 172,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #172 = G_FEXP
4682
    { 171,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #171 = G_FPOWI
4683
    { 170,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #170 = G_FPOW
4684
    { 169,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #169 = G_FREM
4685
    { 168,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #168 = G_FDIV
4686
    { 167,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #167 = G_FMAD
4687
    { 166,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #166 = G_FMA
4688
    { 165,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #165 = G_FMUL
4689
    { 164,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #164 = G_FSUB
4690
    { 163,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #163 = G_FADD
4691
    { 162,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
4692
    { 161,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
4693
    { 160,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #160 = G_UDIVFIX
4694
    { 159,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #159 = G_SDIVFIX
4695
    { 158,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
4696
    { 157,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
4697
    { 156,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #156 = G_UMULFIX
4698
    { 155,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #155 = G_SMULFIX
4699
    { 154,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #154 = G_SSHLSAT
4700
    { 153,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #153 = G_USHLSAT
4701
    { 152,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #152 = G_SSUBSAT
4702
    { 151,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #151 = G_USUBSAT
4703
    { 150,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #150 = G_SADDSAT
4704
    { 149,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #149 = G_UADDSAT
4705
    { 148,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #148 = G_SMULH
4706
    { 147,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #147 = G_UMULH
4707
    { 146,  4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #146 = G_SMULO
4708
    { 145,  4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #145 = G_UMULO
4709
    { 144,  5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #144 = G_SSUBE
4710
    { 143,  4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #143 = G_SSUBO
4711
    { 142,  5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #142 = G_SADDE
4712
    { 141,  4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #141 = G_SADDO
4713
    { 140,  5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #140 = G_USUBE
4714
    { 139,  4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #139 = G_USUBO
4715
    { 138,  5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #138 = G_UADDE
4716
    { 137,  4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #137 = G_UADDO
4717
    { 136,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #136 = G_SELECT
4718
    { 135,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #135 = G_FCMP
4719
    { 134,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #134 = G_ICMP
4720
    { 133,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #133 = G_ROTL
4721
    { 132,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #132 = G_ROTR
4722
    { 131,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #131 = G_FSHR
4723
    { 130,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #130 = G_FSHL
4724
    { 129,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #129 = G_ASHR
4725
    { 128,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #128 = G_LSHR
4726
    { 127,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #127 = G_SHL
4727
    { 126,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #126 = G_ZEXT
4728
    { 125,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #125 = G_SEXT_INREG
4729
    { 124,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #124 = G_SEXT
4730
    { 123,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #123 = G_VAARG
4731
    { 122,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #122 = G_VASTART
4732
    { 121,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #121 = G_FCONSTANT
4733
    { 120,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #120 = G_CONSTANT
4734
    { 119,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #119 = G_TRUNC
4735
    { 118,  2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #118 = G_ANYEXT
4736
    { 117,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
4737
    { 116,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
4738
    { 115,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
4739
    { 114,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #114 = G_INTRINSIC
4740
    { 113,  0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
4741
    { 112,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #112 = G_BRINDIRECT
4742
    { 111,  2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #111 = G_BRCOND
4743
    { 110,  4,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #110 = G_PREFETCH
4744
    { 109,  2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #109 = G_FENCE
4745
    { 108,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
4746
    { 107,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
4747
    { 106,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
4748
    { 105,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
4749
    { 104,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
4750
    { 103,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
4751
    { 102,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
4752
    { 101,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
4753
    { 100,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
4754
    { 99, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
4755
    { 98, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
4756
    { 97, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
4757
    { 96, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
4758
    { 95, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
4759
    { 94, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
4760
    { 93, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
4761
    { 92, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
4762
    { 91, 4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
4763
    { 90, 5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
4764
    { 89, 5,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
4765
    { 88, 2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #88 = G_STORE
4766
    { 87, 5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
4767
    { 86, 5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
4768
    { 85, 5,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
4769
    { 84, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
4770
    { 83, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #83 = G_SEXTLOAD
4771
    { 82, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #82 = G_LOAD
4772
    { 81, 1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
4773
    { 80, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
4774
    { 79, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
4775
    { 78, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
4776
    { 77, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
4777
    { 76, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
4778
    { 75, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
4779
    { 74, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #74 = G_FREEZE
4780
    { 73, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #73 = G_BITCAST
4781
    { 72, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #72 = G_INTTOPTR
4782
    { 71, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #71 = G_PTRTOINT
4783
    { 70, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
4784
    { 69, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
4785
    { 68, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
4786
    { 67, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
4787
    { 66, 4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #66 = G_INSERT
4788
    { 65, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
4789
    { 64, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #64 = G_EXTRACT
4790
    { 63, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
4791
    { 62, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
4792
    { 61, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
4793
    { 60, 1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #60 = G_PHI
4794
    { 59, 1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
4795
    { 58, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #58 = G_XOR
4796
    { 57, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #57 = G_OR
4797
    { 56, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #56 = G_AND
4798
    { 55, 4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #55 = G_UDIVREM
4799
    { 54, 4,  2,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #54 = G_SDIVREM
4800
    { 53, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #53 = G_UREM
4801
    { 52, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #52 = G_SREM
4802
    { 51, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #51 = G_UDIV
4803
    { 50, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #50 = G_SDIV
4804
    { 49, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #49 = G_MUL
4805
    { 48, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #48 = G_SUB
4806
    { 47, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #47 = G_ADD
4807
    { 46, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
4808
    { 45, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
4809
    { 44, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
4810
    { 43, 1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
4811
    { 42, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #42 = MEMBARRIER
4812
    { 41, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
4813
    { 40, 3,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
4814
    { 39, 2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
4815
    { 38, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
4816
    { 37, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
4817
    { 36, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #36 = PATCHABLE_RET
4818
    { 35, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
4819
    { 34, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #34 = PATCHABLE_OP
4820
    { 33, 1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #33 = FAULTING_OP
4821
    { 32, 2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
4822
    { 31, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #31 = STATEPOINT
4823
    { 30, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
4824
    { 29, 1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
4825
    { 28, 1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
4826
    { 27, 6,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #27 = PATCHPOINT
4827
    { 26, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #26 = FENTRY_CALL
4828
    { 25, 2,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #25 = STACKMAP
4829
    { 24, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #24 = ARITH_FENCE
4830
    { 23, 4,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
4831
    { 22, 1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #22 = LIFETIME_END
4832
    { 21, 1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #21 = LIFETIME_START
4833
    { 20, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #20 = BUNDLE
4834
    { 19, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #19 = COPY
4835
    { 18, 2,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #18 = REG_SEQUENCE
4836
    { 17, 1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #17 = DBG_LABEL
4837
    { 16, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #16 = DBG_PHI
4838
    { 15, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
4839
    { 14, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
4840
    { 13, 0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #13 = DBG_VALUE
4841
    { 12, 3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
4842
    { 11, 4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 9,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
4843
    { 10, 1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
4844
    { 9,  4,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 5,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #9 = INSERT_SUBREG
4845
    { 8,  3,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
4846
    { 7,  0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #7 = KILL
4847
    { 6,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
4848
    { 5,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #5 = GC_LABEL
4849
    { 4,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #4 = EH_LABEL
4850
    { 3,  1,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
4851
    { 2,  0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #2 = INLINEASM_BR
4852
    { 1,  0,  0,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #1 = INLINEASM
4853
    { 0,  1,  1,  0,  0,  0,  0,  LoongArchImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #0 = PHI
4854
  }, {
4855
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4856
    /* 1 */
4857
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4858
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4859
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4860
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4861
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4862
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4863
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
4864
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4865
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4866
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
4867
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4868
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4869
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4870
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4871
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4872
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4873
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4874
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4875
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4876
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4877
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4878
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4879
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4880
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4881
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4882
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4883
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4884
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4885
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4886
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
4887
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4888
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4889
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4890
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4891
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4892
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4893
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4894
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4895
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
4896
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4897
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
4898
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
4899
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
4900
    /* 140 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4901
    /* 145 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4902
    /* 148 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4903
    /* 150 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4904
    /* 151 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4905
    /* 157 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4906
    /* 159 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4907
    /* 162 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4908
    /* 165 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4909
    /* 173 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4910
    /* 180 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4911
    /* 187 */ { LoongArch::GPRTRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4912
    /* 188 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4913
    /* 190 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4914
    /* 192 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4915
    /* 194 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4916
    /* 198 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4917
    /* 200 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4918
    /* 202 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4919
    /* 206 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_EARLY_CLOBBER }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4920
    /* 209 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4921
    /* 212 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4922
    /* 214 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4923
    /* 216 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4924
    /* 221 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4925
    /* 225 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4926
    /* 228 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4927
    /* 231 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4928
    /* 235 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4929
    /* 237 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4930
    /* 239 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4931
    /* 242 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4932
    /* 245 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4933
    /* 248 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4934
    /* 251 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4935
    /* 253 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4936
    /* 255 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4937
    /* 258 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4938
    /* 261 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4939
    /* 264 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4940
    /* 267 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4941
    /* 271 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4942
    /* 275 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4943
    /* 279 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4944
    /* 283 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4945
    /* 285 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4946
    /* 287 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4947
    /* 289 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4948
    /* 291 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4949
    /* 293 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4950
    /* 295 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4951
    /* 297 */ { LoongArch::FCSRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4952
    /* 299 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4953
    /* 302 */ { LoongArch::FPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4954
    /* 304 */ { LoongArch::FPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4955
    /* 306 */ { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4956
    /* 308 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::SCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4957
    /* 310 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4958
    /* 313 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4959
    /* 316 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4960
    /* 320 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4961
    /* 321 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4962
    /* 324 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4963
    /* 327 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4964
    /* 331 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4965
    /* 335 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4966
    /* 337 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4967
    /* 339 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4968
    /* 343 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4969
    /* 347 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4970
    /* 350 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4971
    /* 353 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4972
    /* 356 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4973
    /* 358 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4974
    /* 361 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4975
    /* 363 */ { LoongArch::LSX128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4976
    /* 367 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4977
    /* 370 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4978
    /* 373 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4979
    /* 377 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4980
    /* 381 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4981
    /* 385 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4982
    /* 388 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4983
    /* 391 */ { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4984
    /* 394 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4985
    /* 396 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4986
    /* 399 */ { LoongArch::CFRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
4987
    /* 401 */ { LoongArch::LASX256RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { LoongArch::GPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
4988
  }, {
4989
    /* 0 */
4990
    /* 0 */ LoongArch::R3, LoongArch::R3,
4991
    /* 2 */ LoongArch::R3,
4992
    /* 3 */ LoongArch::R1,
4993
    /* 4 */ LoongArch::R1, LoongArch::R20,
4994
    /* 6 */ LoongArch::R20,
4995
    /* 7 */ LoongArch::R3, LoongArch::R19, LoongArch::R20,
4996
    /* 10 */ LoongArch::R3, LoongArch::R20,
4997
  }
4998
};
4999
5000
5001
#ifdef __GNUC__
5002
#pragma GCC diagnostic push
5003
#pragma GCC diagnostic ignored "-Woverlength-strings"
5004
#endif
5005
extern const char LoongArchInstrNameData[] = {
5006
  /* 0 */ "G_FLOG10\0"
5007
  /* 9 */ "G_FEXP10\0"
5008
  /* 18 */ "JISCR0\0"
5009
  /* 25 */ "JISCR1\0"
5010
  /* 32 */ "PseudoMaskedAtomicLoadSub32\0"
5011
  /* 60 */ "PseudoAtomicLoadSub32\0"
5012
  /* 82 */ "PseudoMaskedAtomicLoadAdd32\0"
5013
  /* 110 */ "PseudoAtomicLoadAdd32\0"
5014
  /* 132 */ "PseudoAtomicLoadAnd32\0"
5015
  /* 154 */ "PseudoMaskedAtomicLoadNand32\0"
5016
  /* 183 */ "PseudoAtomicLoadNand32\0"
5017
  /* 206 */ "PseudoMaskedCmpXchg32\0"
5018
  /* 228 */ "PseudoCmpXchg32\0"
5019
  /* 244 */ "PseudoMaskedAtomicLoadUMin32\0"
5020
  /* 273 */ "PseudoMaskedAtomicLoadMin32\0"
5021
  /* 301 */ "PseudoMaskedAtomicSwap32\0"
5022
  /* 326 */ "PseudoAtomicSwap32\0"
5023
  /* 345 */ "PseudoAtomicLoadOr32\0"
5024
  /* 366 */ "PseudoAtomicLoadXor32\0"
5025
  /* 388 */ "PseudoMaskedAtomicLoadUMax32\0"
5026
  /* 417 */ "PseudoMaskedAtomicLoadMax32\0"
5027
  /* 445 */ "G_FLOG2\0"
5028
  /* 453 */ "G_FEXP2\0"
5029
  /* 461 */ "MOVFR2GR_S_64\0"
5030
  /* 475 */ "MOVGR2FR_W_64\0"
5031
  /* 489 */ "PseudoAtomicLoadNand64\0"
5032
  /* 512 */ "PseudoCmpXchg64\0"
5033
  /* 528 */ "PseudoTAIL36\0"
5034
  /* 541 */ "PseudoCALL36\0"
5035
  /* 554 */ "G_FMA\0"
5036
  /* 560 */ "G_STRICT_FMA\0"
5037
  /* 573 */ "BITREV_4B\0"
5038
  /* 583 */ "BITREV_8B\0"
5039
  /* 593 */ "INVTLB\0"
5040
  /* 600 */ "G_FSUB\0"
5041
  /* 607 */ "G_STRICT_FSUB\0"
5042
  /* 621 */ "G_ATOMICRMW_FSUB\0"
5043
  /* 638 */ "G_SUB\0"
5044
  /* 644 */ "G_ATOMICRMW_SUB\0"
5045
  /* 660 */ "XVREPLVE0_B\0"
5046
  /* 672 */ "XVADDA_B\0"
5047
  /* 681 */ "X86SRA_B\0"
5048
  /* 690 */ "XVSRA_B\0"
5049
  /* 698 */ "AMADD__DB_B\0"
5050
  /* 710 */ "AMSWAP__DB_B\0"
5051
  /* 723 */ "AMCAS__DB_B\0"
5052
  /* 735 */ "X86SUB_B\0"
5053
  /* 744 */ "XVMSUB_B\0"
5054
  /* 753 */ "XVSSUB_B\0"
5055
  /* 762 */ "XVSUB_B\0"
5056
  /* 770 */ "X86SBC_B\0"
5057
  /* 779 */ "X86ADC_B\0"
5058
  /* 788 */ "X86DEC_B\0"
5059
  /* 797 */ "X86INC_B\0"
5060
  /* 806 */ "X86ADD_B\0"
5061
  /* 815 */ "AMADD_B\0"
5062
  /* 823 */ "XVMADD_B\0"
5063
  /* 832 */ "XVSADD_B\0"
5064
  /* 841 */ "XVADD_B\0"
5065
  /* 849 */ "LD_B\0"
5066
  /* 854 */ "X86AND_B\0"
5067
  /* 863 */ "XVPACKOD_B\0"
5068
  /* 874 */ "XVPICKOD_B\0"
5069
  /* 885 */ "XVMOD_B\0"
5070
  /* 893 */ "IOCSRRD_B\0"
5071
  /* 903 */ "XVABSD_B\0"
5072
  /* 912 */ "VEXT2XV_D_B\0"
5073
  /* 924 */ "LDLE_B\0"
5074
  /* 931 */ "XVSLE_B\0"
5075
  /* 939 */ "STLE_B\0"
5076
  /* 946 */ "XVREPLVE_B\0"
5077
  /* 957 */ "XVSHUF_B\0"
5078
  /* 966 */ "XVNEG_B\0"
5079
  /* 974 */ "XVAVG_B\0"
5080
  /* 982 */ "XVMUH_B\0"
5081
  /* 990 */ "XVILVH_B\0"
5082
  /* 999 */ "XVSUBWOD_H_B\0"
5083
  /* 1012 */ "XVMADDWOD_H_B\0"
5084
  /* 1026 */ "XVADDWOD_H_B\0"
5085
  /* 1039 */ "XVMULWOD_H_B\0"
5086
  /* 1052 */ "XVEXTH_H_B\0"
5087
  /* 1063 */ "XVSLLWIL_H_B\0"
5088
  /* 1076 */ "XVSUBWEV_H_B\0"
5089
  /* 1089 */ "XVMADDWEV_H_B\0"
5090
  /* 1103 */ "XVADDWEV_H_B\0"
5091
  /* 1116 */ "XVMULWEV_H_B\0"
5092
  /* 1129 */ "VEXT2XV_H_B\0"
5093
  /* 1141 */ "XVHSUBW_H_B\0"
5094
  /* 1153 */ "XVHADDW_H_B\0"
5095
  /* 1165 */ "XVSHUF4I_B\0"
5096
  /* 1176 */ "X86SRAI_B\0"
5097
  /* 1186 */ "XVSRAI_B\0"
5098
  /* 1195 */ "XVANDI_B\0"
5099
  /* 1204 */ "XVSLEI_B\0"
5100
  /* 1213 */ "XVREPL128VEI_B\0"
5101
  /* 1228 */ "VREPLVEI_B\0"
5102
  /* 1239 */ "X86RCLI_B\0"
5103
  /* 1249 */ "XVBITSELI_B\0"
5104
  /* 1261 */ "X86SLLI_B\0"
5105
  /* 1271 */ "XVSLLI_B\0"
5106
  /* 1280 */ "PseudoXVREPLI_B\0"
5107
  /* 1296 */ "PseudoVREPLI_B\0"
5108
  /* 1311 */ "X86SRLI_B\0"
5109
  /* 1321 */ "XVSRLI_B\0"
5110
  /* 1330 */ "X86ROTLI_B\0"
5111
  /* 1341 */ "XVMINI_B\0"
5112
  /* 1350 */ "XVFRSTPI_B\0"
5113
  /* 1361 */ "XVSEQI_B\0"
5114
  /* 1370 */ "XVSRARI_B\0"
5115
  /* 1380 */ "X86RCRI_B\0"
5116
  /* 1390 */ "XVBITCLRI_B\0"
5117
  /* 1402 */ "XVSRLRI_B\0"
5118
  /* 1412 */ "XVNORI_B\0"
5119
  /* 1421 */ "XVORI_B\0"
5120
  /* 1429 */ "XVXORI_B\0"
5121
  /* 1438 */ "X86ROTRI_B\0"
5122
  /* 1449 */ "XVROTRI_B\0"
5123
  /* 1459 */ "XVBITSETI_B\0"
5124
  /* 1471 */ "XVSLTI_B\0"
5125
  /* 1480 */ "XVBITREVI_B\0"
5126
  /* 1492 */ "XVMAXI_B\0"
5127
  /* 1501 */ "X86RCL_B\0"
5128
  /* 1510 */ "X86SLL_B\0"
5129
  /* 1519 */ "XVSLL_B\0"
5130
  /* 1527 */ "XVLDREPL_B\0"
5131
  /* 1538 */ "X86SRL_B\0"
5132
  /* 1547 */ "XVSRL_B\0"
5133
  /* 1555 */ "X86ROTL_B\0"
5134
  /* 1565 */ "X86MUL_B\0"
5135
  /* 1574 */ "XVMUL_B\0"
5136
  /* 1582 */ "XVILVL_B\0"
5137
  /* 1591 */ "XVSTELM_B\0"
5138
  /* 1601 */ "XVMIN_B\0"
5139
  /* 1609 */ "XVCLO_B\0"
5140
  /* 1617 */ "AMSWAP_B\0"
5141
  /* 1626 */ "XVFRSTP_B\0"
5142
  /* 1636 */ "XVSEQ_B\0"
5143
  /* 1644 */ "XVSRAR_B\0"
5144
  /* 1653 */ "X86RCR_B\0"
5145
  /* 1662 */ "VPICKVE2GR_B\0"
5146
  /* 1675 */ "XVAVGR_B\0"
5147
  /* 1684 */ "XVBITCLR_B\0"
5148
  /* 1695 */ "XVSRLR_B\0"
5149
  /* 1704 */ "X86OR_B\0"
5150
  /* 1712 */ "X86XOR_B\0"
5151
  /* 1721 */ "X86ROTR_B\0"
5152
  /* 1731 */ "XVROTR_B\0"
5153
  /* 1740 */ "XVREPLGR2VR_B\0"
5154
  /* 1754 */ "PseudoXVINSGR2VR_B\0"
5155
  /* 1773 */ "IOCSRWR_B\0"
5156
  /* 1783 */ "AMCAS_B\0"
5157
  /* 1791 */ "XVEXTRINS_B\0"
5158
  /* 1803 */ "XVSAT_B\0"
5159
  /* 1811 */ "XVBITSET_B\0"
5160
  /* 1822 */ "LDGT_B\0"
5161
  /* 1829 */ "STGT_B\0"
5162
  /* 1836 */ "XVSLT_B\0"
5163
  /* 1844 */ "XVPCNT_B\0"
5164
  /* 1853 */ "ST_B\0"
5165
  /* 1858 */ "XVMADDWOD_H_BU_B\0"
5166
  /* 1875 */ "XVADDWOD_H_BU_B\0"
5167
  /* 1891 */ "XVMULWOD_H_BU_B\0"
5168
  /* 1907 */ "XVMADDWEV_H_BU_B\0"
5169
  /* 1924 */ "XVADDWEV_H_BU_B\0"
5170
  /* 1940 */ "XVMULWEV_H_BU_B\0"
5171
  /* 1956 */ "XVPACKEV_B\0"
5172
  /* 1967 */ "XVPICKEV_B\0"
5173
  /* 1978 */ "XVBITREV_B\0"
5174
  /* 1989 */ "XVDIV_B\0"
5175
  /* 1997 */ "XVSIGNCOV_B\0"
5176
  /* 2009 */ "EXT_W_B\0"
5177
  /* 2017 */ "VEXT2XV_W_B\0"
5178
  /* 2029 */ "XVMAX_B\0"
5179
  /* 2037 */ "LDX_B\0"
5180
  /* 2043 */ "STX_B\0"
5181
  /* 2049 */ "PseudoXVBZ_B\0"
5182
  /* 2062 */ "PseudoVBZ_B\0"
5183
  /* 2074 */ "XVMSKGEZ_B\0"
5184
  /* 2085 */ "XVSETALLNEZ_B\0"
5185
  /* 2099 */ "XVCLZ_B\0"
5186
  /* 2107 */ "PseudoXVBNZ_B\0"
5187
  /* 2121 */ "PseudoVBNZ_B\0"
5188
  /* 2134 */ "XVMSKNZ_B\0"
5189
  /* 2144 */ "XVSETANYEQZ_B\0"
5190
  /* 2158 */ "XVMSKLTZ_B\0"
5191
  /* 2169 */ "G_INTRINSIC\0"
5192
  /* 2181 */ "G_FPTRUNC\0"
5193
  /* 2191 */ "G_INTRINSIC_TRUNC\0"
5194
  /* 2209 */ "G_TRUNC\0"
5195
  /* 2217 */ "G_BUILD_VECTOR_TRUNC\0"
5196
  /* 2238 */ "G_DYN_STACKALLOC\0"
5197
  /* 2255 */ "G_FMAD\0"
5198
  /* 2262 */ "G_INDEXED_SEXTLOAD\0"
5199
  /* 2281 */ "G_SEXTLOAD\0"
5200
  /* 2292 */ "G_INDEXED_ZEXTLOAD\0"
5201
  /* 2311 */ "G_ZEXTLOAD\0"
5202
  /* 2322 */ "G_INDEXED_LOAD\0"
5203
  /* 2337 */ "G_LOAD\0"
5204
  /* 2344 */ "G_VECREDUCE_FADD\0"
5205
  /* 2361 */ "G_FADD\0"
5206
  /* 2368 */ "G_VECREDUCE_SEQ_FADD\0"
5207
  /* 2389 */ "G_STRICT_FADD\0"
5208
  /* 2403 */ "G_ATOMICRMW_FADD\0"
5209
  /* 2420 */ "G_VECREDUCE_ADD\0"
5210
  /* 2436 */ "G_ADD\0"
5211
  /* 2442 */ "G_PTR_ADD\0"
5212
  /* 2452 */ "G_ATOMICRMW_ADD\0"
5213
  /* 2468 */ "PseudoLA_TLS_GD\0"
5214
  /* 2484 */ "PRELD\0"
5215
  /* 2490 */ "XVLD\0"
5216
  /* 2495 */ "FCVT_D_LD\0"
5217
  /* 2505 */ "PseudoLA_TLS_LD\0"
5218
  /* 2521 */ "G_ATOMICRMW_NAND\0"
5219
  /* 2538 */ "G_VECREDUCE_AND\0"
5220
  /* 2554 */ "G_AND\0"
5221
  /* 2560 */ "G_ATOMICRMW_AND\0"
5222
  /* 2576 */ "LIFETIME_END\0"
5223
  /* 2589 */ "PseudoBRIND\0"
5224
  /* 2601 */ "G_BRCOND\0"
5225
  /* 2610 */ "G_LLROUND\0"
5226
  /* 2620 */ "G_LROUND\0"
5227
  /* 2629 */ "G_INTRINSIC_ROUND\0"
5228
  /* 2647 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
5229
  /* 2673 */ "LOAD_STACK_GUARD\0"
5230
  /* 2690 */ "TLBRD\0"
5231
  /* 2696 */ "GCSRRD\0"
5232
  /* 2703 */ "XVREPLVE0_D\0"
5233
  /* 2715 */ "XVINSVE0_D\0"
5234
  /* 2726 */ "XVADDA_D\0"
5235
  /* 2735 */ "XVFMINA_D\0"
5236
  /* 2745 */ "X86SRA_D\0"
5237
  /* 2754 */ "XVSRA_D\0"
5238
  /* 2762 */ "XVFMAXA_D\0"
5239
  /* 2772 */ "AMADD__DB_D\0"
5240
  /* 2784 */ "AMAND__DB_D\0"
5241
  /* 2796 */ "AMMIN__DB_D\0"
5242
  /* 2808 */ "AMSWAP__DB_D\0"
5243
  /* 2821 */ "AMOR__DB_D\0"
5244
  /* 2832 */ "AMXOR__DB_D\0"
5245
  /* 2844 */ "AMCAS__DB_D\0"
5246
  /* 2856 */ "AMMAX__DB_D\0"
5247
  /* 2868 */ "FSCALEB_D\0"
5248
  /* 2878 */ "XVFLOGB_D\0"
5249
  /* 2888 */ "X86SUB_D\0"
5250
  /* 2897 */ "XVFSUB_D\0"
5251
  /* 2906 */ "XVFMSUB_D\0"
5252
  /* 2916 */ "XVFNMSUB_D\0"
5253
  /* 2927 */ "XVMSUB_D\0"
5254
  /* 2936 */ "XVSSUB_D\0"
5255
  /* 2945 */ "XVSUB_D\0"
5256
  /* 2953 */ "REVB_D\0"
5257
  /* 2960 */ "X86SBC_D\0"
5258
  /* 2969 */ "X86ADC_D\0"
5259
  /* 2978 */ "X86DEC_D\0"
5260
  /* 2987 */ "X86INC_D\0"
5261
  /* 2996 */ "SC_D\0"
5262
  /* 3001 */ "X86ADD_D\0"
5263
  /* 3010 */ "XVFADD_D\0"
5264
  /* 3019 */ "AMADD_D\0"
5265
  /* 3027 */ "XVFMADD_D\0"
5266
  /* 3037 */ "XVFNMADD_D\0"
5267
  /* 3048 */ "XVMADD_D\0"
5268
  /* 3057 */ "XVSADD_D\0"
5269
  /* 3066 */ "XVADD_D\0"
5270
  /* 3074 */ "FLD_D\0"
5271
  /* 3080 */ "FCVT_LD_D\0"
5272
  /* 3090 */ "X86AND_D\0"
5273
  /* 3099 */ "AMAND_D\0"
5274
  /* 3107 */ "XVPACKOD_D\0"
5275
  /* 3118 */ "XVPICKOD_D\0"
5276
  /* 3129 */ "XVMOD_D\0"
5277
  /* 3137 */ "IOCSRRD_D\0"
5278
  /* 3147 */ "XVABSD_D\0"
5279
  /* 3156 */ "FCVT_UD_D\0"
5280
  /* 3166 */ "XVFCMP_CLE_D\0"
5281
  /* 3179 */ "FLDLE_D\0"
5282
  /* 3187 */ "XVSLE_D\0"
5283
  /* 3195 */ "XVFCMP_SLE_D\0"
5284
  /* 3208 */ "ASRTLE_D\0"
5285
  /* 3217 */ "FSTLE_D\0"
5286
  /* 3225 */ "XVFCMP_CULE_D\0"
5287
  /* 3239 */ "XVFCMP_SULE_D\0"
5288
  /* 3253 */ "RDTIME_D\0"
5289
  /* 3262 */ "XVFCMP_CNE_D\0"
5290
  /* 3275 */ "XVFRINTRNE_D\0"
5291
  /* 3288 */ "XVFCMP_SNE_D\0"
5292
  /* 3301 */ "XVFCMP_CUNE_D\0"
5293
  /* 3315 */ "XVFCMP_SUNE_D\0"
5294
  /* 3329 */ "XVFRECIPE_D\0"
5295
  /* 3341 */ "XVFRSQRTE_D\0"
5296
  /* 3353 */ "XVPICKVE_D\0"
5297
  /* 3364 */ "XVREPLVE_D\0"
5298
  /* 3375 */ "XVFCMP_CAF_D\0"
5299
  /* 3388 */ "XVFCMP_SAF_D\0"
5300
  /* 3401 */ "XVSHUF_D\0"
5301
  /* 3410 */ "FNEG_D\0"
5302
  /* 3417 */ "XVNEG_D\0"
5303
  /* 3425 */ "XVAVG_D\0"
5304
  /* 3433 */ "MULH_D\0"
5305
  /* 3440 */ "XVMUH_D\0"
5306
  /* 3448 */ "REVH_D\0"
5307
  /* 3455 */ "XVILVH_D\0"
5308
  /* 3464 */ "ADDU12I_D\0"
5309
  /* 3474 */ "LU32I_D\0"
5310
  /* 3482 */ "LU52I_D\0"
5311
  /* 3490 */ "XVSHUF4I_D\0"
5312
  /* 3501 */ "ADDU16I_D\0"
5313
  /* 3511 */ "X86SRAI_D\0"
5314
  /* 3521 */ "XVSRAI_D\0"
5315
  /* 3530 */ "ADDI_D\0"
5316
  /* 3537 */ "XVSLEI_D\0"
5317
  /* 3546 */ "XVREPL128VEI_D\0"
5318
  /* 3561 */ "VREPLVEI_D\0"
5319
  /* 3572 */ "X86RCLI_D\0"
5320
  /* 3582 */ "XVHSELI_D\0"
5321
  /* 3592 */ "X86SLLI_D\0"
5322
  /* 3602 */ "XVSLLI_D\0"
5323
  /* 3611 */ "PseudoXVREPLI_D\0"
5324
  /* 3627 */ "PseudoVREPLI_D\0"
5325
  /* 3642 */ "X86SRLI_D\0"
5326
  /* 3652 */ "XVSRLI_D\0"
5327
  /* 3661 */ "X86ROTLI_D\0"
5328
  /* 3672 */ "PseudoLI_D\0"
5329
  /* 3683 */ "XVPERMI_D\0"
5330
  /* 3693 */ "XVMINI_D\0"
5331
  /* 3702 */ "XVSEQI_D\0"
5332
  /* 3711 */ "XVSRARI_D\0"
5333
  /* 3721 */ "X86RCRI_D\0"
5334
  /* 3731 */ "XVBITCLRI_D\0"
5335
  /* 3743 */ "XVSRLRI_D\0"
5336
  /* 3753 */ "X86ROTRI_D\0"
5337
  /* 3764 */ "XVROTRI_D\0"
5338
  /* 3774 */ "XVBITSETI_D\0"
5339
  /* 3786 */ "XVSLTI_D\0"
5340
  /* 3795 */ "XVBITREVI_D\0"
5341
  /* 3807 */ "XVMAXI_D\0"
5342
  /* 3816 */ "BYTEPICK_D\0"
5343
  /* 3827 */ "BSTRPICK_D\0"
5344
  /* 3838 */ "X86RCL_D\0"
5345
  /* 3847 */ "LDL_D\0"
5346
  /* 3853 */ "SCREL_D\0"
5347
  /* 3861 */ "X86SLL_D\0"
5348
  /* 3870 */ "XVSLL_D\0"
5349
  /* 3878 */ "XVLDREPL_D\0"
5350
  /* 3889 */ "X86SRL_D\0"
5351
  /* 3898 */ "XVSRL_D\0"
5352
  /* 3906 */ "ALSL_D\0"
5353
  /* 3913 */ "X86ROTL_D\0"
5354
  /* 3923 */ "STL_D\0"
5355
  /* 3929 */ "X86MUL_D\0"
5356
  /* 3938 */ "XVFMUL_D\0"
5357
  /* 3947 */ "XVMUL_D\0"
5358
  /* 3955 */ "XVILVL_D\0"
5359
  /* 3964 */ "XVFTINTRNE_L_D\0"
5360
  /* 3979 */ "XVFTINTRM_L_D\0"
5361
  /* 3993 */ "XVFTINTRP_L_D\0"
5362
  /* 4007 */ "XVFTINT_L_D\0"
5363
  /* 4019 */ "XVFTINTRZ_L_D\0"
5364
  /* 4033 */ "XVSTELM_D\0"
5365
  /* 4043 */ "XVFRINTRM_D\0"
5366
  /* 4055 */ "FCOPYSIGN_D\0"
5367
  /* 4067 */ "XVFMIN_D\0"
5368
  /* 4076 */ "AMMIN_D\0"
5369
  /* 4084 */ "XVMIN_D\0"
5370
  /* 4092 */ "XVFCMP_CUN_D\0"
5371
  /* 4105 */ "XVFCMP_SUN_D\0"
5372
  /* 4118 */ "XVCLO_D\0"
5373
  /* 4126 */ "CTO_D\0"
5374
  /* 4132 */ "AMSWAP_D\0"
5375
  /* 4141 */ "XVFRECIP_D\0"
5376
  /* 4152 */ "XVFRINTRP_D\0"
5377
  /* 4164 */ "LLACQ_D\0"
5378
  /* 4172 */ "XVFCMP_CEQ_D\0"
5379
  /* 4185 */ "XVSEQ_D\0"
5380
  /* 4193 */ "XVFCMP_SEQ_D\0"
5381
  /* 4206 */ "XVFCMP_CUEQ_D\0"
5382
  /* 4220 */ "XVFCMP_SUEQ_D\0"
5383
  /* 4234 */ "XVSUBWOD_Q_D\0"
5384
  /* 4247 */ "XVMADDWOD_Q_D\0"
5385
  /* 4261 */ "XVADDWOD_Q_D\0"
5386
  /* 4274 */ "XVMULWOD_Q_D\0"
5387
  /* 4287 */ "XVEXTH_Q_D\0"
5388
  /* 4298 */ "XVEXTL_Q_D\0"
5389
  /* 4309 */ "XVSUBWEV_Q_D\0"
5390
  /* 4322 */ "XVMADDWEV_Q_D\0"
5391
  /* 4336 */ "XVADDWEV_Q_D\0"
5392
  /* 4349 */ "XVMULWEV_Q_D\0"
5393
  /* 4362 */ "XVHSUBW_Q_D\0"
5394
  /* 4374 */ "XVHADDW_Q_D\0"
5395
  /* 4386 */ "XVSRAR_D\0"
5396
  /* 4395 */ "X86RCR_D\0"
5397
  /* 4404 */ "LDR_D\0"
5398
  /* 4410 */ "MOVGR2FR_D\0"
5399
  /* 4421 */ "XVPICKVE2GR_D\0"
5400
  /* 4435 */ "MOVFR2GR_D\0"
5401
  /* 4446 */ "XVAVGR_D\0"
5402
  /* 4455 */ "XVBITCLR_D\0"
5403
  /* 4466 */ "XVSRLR_D\0"
5404
  /* 4475 */ "X86OR_D\0"
5405
  /* 4483 */ "XVFCMP_COR_D\0"
5406
  /* 4496 */ "AMOR_D\0"
5407
  /* 4503 */ "XVFCMP_SOR_D\0"
5408
  /* 4516 */ "X86XOR_D\0"
5409
  /* 4525 */ "AMXOR_D\0"
5410
  /* 4533 */ "X86ROTR_D\0"
5411
  /* 4543 */ "XVROTR_D\0"
5412
  /* 4552 */ "LDPTR_D\0"
5413
  /* 4560 */ "STPTR_D\0"
5414
  /* 4568 */ "STR_D\0"
5415
  /* 4574 */ "XVREPLGR2VR_D\0"
5416
  /* 4588 */ "XVINSGR2VR_D\0"
5417
  /* 4601 */ "IOCSRWR_D\0"
5418
  /* 4611 */ "AMCAS_D\0"
5419
  /* 4619 */ "FABS_D\0"
5420
  /* 4626 */ "BSTRINS_D\0"
5421
  /* 4636 */ "XVEXTRINS_D\0"
5422
  /* 4648 */ "XVFCLASS_D\0"
5423
  /* 4659 */ "XVFCVT_S_D\0"
5424
  /* 4670 */ "XVSAT_D\0"
5425
  /* 4678 */ "XVBITSET_D\0"
5426
  /* 4689 */ "FLDGT_D\0"
5427
  /* 4697 */ "ASRTGT_D\0"
5428
  /* 4706 */ "FSTGT_D\0"
5429
  /* 4714 */ "XVFCMP_CLT_D\0"
5430
  /* 4727 */ "XVSLT_D\0"
5431
  /* 4735 */ "XVFCMP_SLT_D\0"
5432
  /* 4748 */ "XVFCMP_CULT_D\0"
5433
  /* 4762 */ "XVFCMP_SULT_D\0"
5434
  /* 4776 */ "XVPCNT_D\0"
5435
  /* 4785 */ "XVFRINT_D\0"
5436
  /* 4795 */ "XVFSQRT_D\0"
5437
  /* 4805 */ "XVFRSQRT_D\0"
5438
  /* 4816 */ "FST_D\0"
5439
  /* 4822 */ "XVMADDWOD_Q_DU_D\0"
5440
  /* 4839 */ "XVADDWOD_Q_DU_D\0"
5441
  /* 4855 */ "XVMULWOD_Q_DU_D\0"
5442
  /* 4871 */ "XVMADDWEV_Q_DU_D\0"
5443
  /* 4888 */ "XVADDWEV_Q_DU_D\0"
5444
  /* 4904 */ "XVMULWEV_Q_DU_D\0"
5445
  /* 4920 */ "XVFTINT_LU_D\0"
5446
  /* 4933 */ "XVFTINTRZ_LU_D\0"
5447
  /* 4948 */ "XVSSRANI_WU_D\0"
5448
  /* 4962 */ "XVSSRLNI_WU_D\0"
5449
  /* 4976 */ "XVSSRARNI_WU_D\0"
5450
  /* 4991 */ "XVSSRLRNI_WU_D\0"
5451
  /* 5006 */ "XVSSRAN_WU_D\0"
5452
  /* 5019 */ "XVSSRLN_WU_D\0"
5453
  /* 5032 */ "XVSSRARN_WU_D\0"
5454
  /* 5046 */ "XVSSRLRN_WU_D\0"
5455
  /* 5060 */ "XVPACKEV_D\0"
5456
  /* 5071 */ "XVPICKEV_D\0"
5457
  /* 5082 */ "XVBITREV_D\0"
5458
  /* 5093 */ "XVFDIV_D\0"
5459
  /* 5102 */ "XVDIV_D\0"
5460
  /* 5110 */ "XVSIGNCOV_D\0"
5461
  /* 5122 */ "FMOV_D\0"
5462
  /* 5129 */ "ARMMOV_D\0"
5463
  /* 5138 */ "XVFTINTRNE_W_D\0"
5464
  /* 5153 */ "XVSSRANI_W_D\0"
5465
  /* 5166 */ "XVSRANI_W_D\0"
5466
  /* 5178 */ "XVSSRLNI_W_D\0"
5467
  /* 5191 */ "XVSRLNI_W_D\0"
5468
  /* 5203 */ "XVSSRARNI_W_D\0"
5469
  /* 5217 */ "XVSRARNI_W_D\0"
5470
  /* 5230 */ "XVSSRLRNI_W_D\0"
5471
  /* 5244 */ "XVSRLRNI_W_D\0"
5472
  /* 5257 */ "XVFTINTRM_W_D\0"
5473
  /* 5271 */ "XVSSRAN_W_D\0"
5474
  /* 5283 */ "XVSRAN_W_D\0"
5475
  /* 5294 */ "XVSSRLN_W_D\0"
5476
  /* 5306 */ "XVSRLN_W_D\0"
5477
  /* 5317 */ "XVSSRARN_W_D\0"
5478
  /* 5330 */ "XVSRARN_W_D\0"
5479
  /* 5342 */ "XVSSRLRN_W_D\0"
5480
  /* 5355 */ "XVSRLRN_W_D\0"
5481
  /* 5367 */ "XVFTINTRP_W_D\0"
5482
  /* 5381 */ "XVFTINT_W_D\0"
5483
  /* 5393 */ "XVFTINTRZ_W_D\0"
5484
  /* 5407 */ "XVFMAX_D\0"
5485
  /* 5416 */ "AMMAX_D\0"
5486
  /* 5424 */ "XVMAX_D\0"
5487
  /* 5432 */ "FLDX_D\0"
5488
  /* 5439 */ "FSTX_D\0"
5489
  /* 5446 */ "PseudoXVBZ_D\0"
5490
  /* 5459 */ "PseudoVBZ_D\0"
5491
  /* 5471 */ "XVSETALLNEZ_D\0"
5492
  /* 5485 */ "XVCLZ_D\0"
5493
  /* 5493 */ "PseudoXVBNZ_D\0"
5494
  /* 5507 */ "PseudoVBNZ_D\0"
5495
  /* 5520 */ "XVSETANYEQZ_D\0"
5496
  /* 5534 */ "XVFRINTRZ_D\0"
5497
  /* 5546 */ "CTZ_D\0"
5498
  /* 5552 */ "XVMSKLTZ_D\0"
5499
  /* 5563 */ "PseudoAtomicStoreD\0"
5500
  /* 5582 */ "FSEL_xD\0"
5501
  /* 5590 */ "PSEUDO_PROBE\0"
5502
  /* 5603 */ "G_SSUBE\0"
5503
  /* 5611 */ "G_USUBE\0"
5504
  /* 5619 */ "G_FENCE\0"
5505
  /* 5627 */ "ARITH_FENCE\0"
5506
  /* 5639 */ "REG_SEQUENCE\0"
5507
  /* 5652 */ "G_SADDE\0"
5508
  /* 5660 */ "G_UADDE\0"
5509
  /* 5668 */ "G_GET_FPMODE\0"
5510
  /* 5681 */ "G_RESET_FPMODE\0"
5511
  /* 5696 */ "G_SET_FPMODE\0"
5512
  /* 5709 */ "G_FMINNUM_IEEE\0"
5513
  /* 5724 */ "G_FMAXNUM_IEEE\0"
5514
  /* 5739 */ "BGE\0"
5515
  /* 5743 */ "PseudoLA_TLS_GD_LARGE\0"
5516
  /* 5765 */ "PseudoLA_TLS_LD_LARGE\0"
5517
  /* 5787 */ "PseudoLA_TLS_IE_LARGE\0"
5518
  /* 5809 */ "PseudoLA_PCREL_LARGE\0"
5519
  /* 5830 */ "PseudoTAIL_LARGE\0"
5520
  /* 5847 */ "PseudoCALL_LARGE\0"
5521
  /* 5864 */ "PseudoLA_ABS_LARGE\0"
5522
  /* 5883 */ "PseudoLA_GOT_LARGE\0"
5523
  /* 5902 */ "PseudoLA_TLS_IE\0"
5524
  /* 5918 */ "G_JUMP_TABLE\0"
5525
  /* 5931 */ "IDLE\0"
5526
  /* 5936 */ "BUNDLE\0"
5527
  /* 5943 */ "PseudoLA_TLS_LE\0"
5528
  /* 5959 */ "BNE\0"
5529
  /* 5963 */ "G_MEMCPY_INLINE\0"
5530
  /* 5979 */ "SETX86LOOPNE\0"
5531
  /* 5992 */ "LOCAL_ESCAPE\0"
5532
  /* 6005 */ "SETX86LOOPE\0"
5533
  /* 6017 */ "G_STACKRESTORE\0"
5534
  /* 6032 */ "G_INDEXED_STORE\0"
5535
  /* 6048 */ "G_STORE\0"
5536
  /* 6056 */ "SET_CFR_FALSE\0"
5537
  /* 6070 */ "G_BITREVERSE\0"
5538
  /* 6083 */ "LDPTE\0"
5539
  /* 6089 */ "DBG_VALUE\0"
5540
  /* 6099 */ "G_GLOBAL_VALUE\0"
5541
  /* 6114 */ "SET_CFR_TRUE\0"
5542
  /* 6127 */ "G_STACKSAVE\0"
5543
  /* 6139 */ "G_MEMMOVE\0"
5544
  /* 6149 */ "ARMMOVE\0"
5545
  /* 6157 */ "G_FREEZE\0"
5546
  /* 6166 */ "G_FCANONICALIZE\0"
5547
  /* 6182 */ "MOVGR2CF\0"
5548
  /* 6191 */ "G_CTLZ_ZERO_UNDEF\0"
5549
  /* 6209 */ "G_CTTZ_ZERO_UNDEF\0"
5550
  /* 6227 */ "G_IMPLICIT_DEF\0"
5551
  /* 6242 */ "DBG_INSTR_REF\0"
5552
  /* 6256 */ "X86MFFLAG\0"
5553
  /* 6266 */ "ARMMFFLAG\0"
5554
  /* 6276 */ "X86MTFLAG\0"
5555
  /* 6286 */ "ARMMTFLAG\0"
5556
  /* 6296 */ "X86SETTAG\0"
5557
  /* 6306 */ "G_FNEG\0"
5558
  /* 6313 */ "EXTRACT_SUBREG\0"
5559
  /* 6328 */ "INSERT_SUBREG\0"
5560
  /* 6342 */ "G_SEXT_INREG\0"
5561
  /* 6355 */ "SUBREG_TO_REG\0"
5562
  /* 6369 */ "CPUCFG\0"
5563
  /* 6376 */ "G_ATOMIC_CMPXCHG\0"
5564
  /* 6393 */ "GCSRXCHG\0"
5565
  /* 6402 */ "G_ATOMICRMW_XCHG\0"
5566
  /* 6419 */ "G_FLOG\0"
5567
  /* 6426 */ "G_VAARG\0"
5568
  /* 6434 */ "PREALLOCATED_ARG\0"
5569
  /* 6451 */ "REVB_2H\0"
5570
  /* 6459 */ "REVB_4H\0"
5571
  /* 6467 */ "TLBSRCH\0"
5572
  /* 6475 */ "G_PREFETCH\0"
5573
  /* 6486 */ "G_SMULH\0"
5574
  /* 6494 */ "G_UMULH\0"
5575
  /* 6502 */ "GTLBFLUSH\0"
5576
  /* 6512 */ "XVREPLVE0_H\0"
5577
  /* 6524 */ "XVADDA_H\0"
5578
  /* 6533 */ "X86SRA_H\0"
5579
  /* 6542 */ "XVSRA_H\0"
5580
  /* 6550 */ "AMADD__DB_H\0"
5581
  /* 6562 */ "AMSWAP__DB_H\0"
5582
  /* 6575 */ "AMCAS__DB_H\0"
5583
  /* 6587 */ "X86SUB_H\0"
5584
  /* 6596 */ "XVMSUB_H\0"
5585
  /* 6605 */ "XVSSUB_H\0"
5586
  /* 6614 */ "XVSUB_H\0"
5587
  /* 6622 */ "XVSSRANI_B_H\0"
5588
  /* 6635 */ "XVSRANI_B_H\0"
5589
  /* 6647 */ "XVSSRLNI_B_H\0"
5590
  /* 6660 */ "XVSRLNI_B_H\0"
5591
  /* 6672 */ "XVSSRARNI_B_H\0"
5592
  /* 6686 */ "XVSRARNI_B_H\0"
5593
  /* 6699 */ "XVSSRLRNI_B_H\0"
5594
  /* 6713 */ "XVSRLRNI_B_H\0"
5595
  /* 6726 */ "XVSSRAN_B_H\0"
5596
  /* 6738 */ "XVSRAN_B_H\0"
5597
  /* 6749 */ "XVSSRLN_B_H\0"
5598
  /* 6761 */ "XVSRLN_B_H\0"
5599
  /* 6772 */ "XVSSRARN_B_H\0"
5600
  /* 6785 */ "XVSRARN_B_H\0"
5601
  /* 6797 */ "XVSSRLRN_B_H\0"
5602
  /* 6810 */ "XVSRLRN_B_H\0"
5603
  /* 6822 */ "X86SBC_H\0"
5604
  /* 6831 */ "X86ADC_H\0"
5605
  /* 6840 */ "X86DEC_H\0"
5606
  /* 6849 */ "X86INC_H\0"
5607
  /* 6858 */ "X86ADD_H\0"
5608
  /* 6867 */ "AMADD_H\0"
5609
  /* 6875 */ "XVMADD_H\0"
5610
  /* 6884 */ "XVSADD_H\0"
5611
  /* 6893 */ "XVADD_H\0"
5612
  /* 6901 */ "LD_H\0"
5613
  /* 6906 */ "X86AND_H\0"
5614
  /* 6915 */ "XVPACKOD_H\0"
5615
  /* 6926 */ "XVPICKOD_H\0"
5616
  /* 6937 */ "XVMOD_H\0"
5617
  /* 6945 */ "IOCSRRD_H\0"
5618
  /* 6955 */ "XVABSD_H\0"
5619
  /* 6964 */ "VEXT2XV_D_H\0"
5620
  /* 6976 */ "LDLE_H\0"
5621
  /* 6983 */ "XVSLE_H\0"
5622
  /* 6991 */ "STLE_H\0"
5623
  /* 6998 */ "XVREPLVE_H\0"
5624
  /* 7009 */ "XVSHUF_H\0"
5625
  /* 7018 */ "XVNEG_H\0"
5626
  /* 7026 */ "XVAVG_H\0"
5627
  /* 7034 */ "XVMUH_H\0"
5628
  /* 7042 */ "XVILVH_H\0"
5629
  /* 7051 */ "XVSHUF4I_H\0"
5630
  /* 7062 */ "X86SRAI_H\0"
5631
  /* 7072 */ "XVSRAI_H\0"
5632
  /* 7081 */ "XVSLEI_H\0"
5633
  /* 7090 */ "XVREPL128VEI_H\0"
5634
  /* 7105 */ "VREPLVEI_H\0"
5635
  /* 7116 */ "X86RCLI_H\0"
5636
  /* 7126 */ "X86SLLI_H\0"
5637
  /* 7136 */ "XVSLLI_H\0"
5638
  /* 7145 */ "PseudoXVREPLI_H\0"
5639
  /* 7161 */ "PseudoVREPLI_H\0"
5640
  /* 7176 */ "X86SRLI_H\0"
5641
  /* 7186 */ "XVSRLI_H\0"
5642
  /* 7195 */ "X86ROTLI_H\0"
5643
  /* 7206 */ "XVMINI_H\0"
5644
  /* 7215 */ "XVFRSTPI_H\0"
5645
  /* 7226 */ "XVSEQI_H\0"
5646
  /* 7235 */ "XVSRARI_H\0"
5647
  /* 7245 */ "X86RCRI_H\0"
5648
  /* 7255 */ "XVBITCLRI_H\0"
5649
  /* 7267 */ "XVSRLRI_H\0"
5650
  /* 7277 */ "X86ROTRI_H\0"
5651
  /* 7288 */ "XVROTRI_H\0"
5652
  /* 7298 */ "XVBITSETI_H\0"
5653
  /* 7310 */ "XVSLTI_H\0"
5654
  /* 7319 */ "XVBITREVI_H\0"
5655
  /* 7331 */ "XVMAXI_H\0"
5656
  /* 7340 */ "X86RCL_H\0"
5657
  /* 7349 */ "X86SLL_H\0"
5658
  /* 7358 */ "XVSLL_H\0"
5659
  /* 7366 */ "XVLDREPL_H\0"
5660
  /* 7377 */ "X86SRL_H\0"
5661
  /* 7386 */ "XVSRL_H\0"
5662
  /* 7394 */ "X86ROTL_H\0"
5663
  /* 7404 */ "X86MUL_H\0"
5664
  /* 7413 */ "XVMUL_H\0"
5665
  /* 7421 */ "XVILVL_H\0"
5666
  /* 7430 */ "XVSTELM_H\0"
5667
  /* 7440 */ "XVMIN_H\0"
5668
  /* 7448 */ "XVCLO_H\0"
5669
  /* 7456 */ "AMSWAP_H\0"
5670
  /* 7465 */ "XVFRSTP_H\0"
5671
  /* 7475 */ "XVSEQ_H\0"
5672
  /* 7483 */ "XVSRAR_H\0"
5673
  /* 7492 */ "X86RCR_H\0"
5674
  /* 7501 */ "VPICKVE2GR_H\0"
5675
  /* 7514 */ "XVAVGR_H\0"
5676
  /* 7523 */ "XVBITCLR_H\0"
5677
  /* 7534 */ "XVSRLR_H\0"
5678
  /* 7543 */ "X86OR_H\0"
5679
  /* 7551 */ "X86XOR_H\0"
5680
  /* 7560 */ "X86ROTR_H\0"
5681
  /* 7570 */ "XVROTR_H\0"
5682
  /* 7579 */ "XVREPLGR2VR_H\0"
5683
  /* 7593 */ "PseudoXVINSGR2VR_H\0"
5684
  /* 7612 */ "IOCSRWR_H\0"
5685
  /* 7622 */ "AMCAS_H\0"
5686
  /* 7630 */ "XVEXTRINS_H\0"
5687
  /* 7642 */ "XVFCVTH_S_H\0"
5688
  /* 7654 */ "XVFCVTL_S_H\0"
5689
  /* 7666 */ "XVSAT_H\0"
5690
  /* 7674 */ "XVBITSET_H\0"
5691
  /* 7685 */ "LDGT_H\0"
5692
  /* 7692 */ "STGT_H\0"
5693
  /* 7699 */ "XVSLT_H\0"
5694
  /* 7707 */ "XVPCNT_H\0"
5695
  /* 7716 */ "ST_H\0"
5696
  /* 7721 */ "XVSSRANI_BU_H\0"
5697
  /* 7735 */ "XVSSRLNI_BU_H\0"
5698
  /* 7749 */ "XVSSRARNI_BU_H\0"
5699
  /* 7764 */ "XVSSRLRNI_BU_H\0"
5700
  /* 7779 */ "XVSSRAN_BU_H\0"
5701
  /* 7792 */ "XVSSRLN_BU_H\0"
5702
  /* 7805 */ "XVSSRARN_BU_H\0"
5703
  /* 7819 */ "XVSSRLRN_BU_H\0"
5704
  /* 7833 */ "XVMADDWOD_W_HU_H\0"
5705
  /* 7850 */ "XVADDWOD_W_HU_H\0"
5706
  /* 7866 */ "XVMULWOD_W_HU_H\0"
5707
  /* 7882 */ "XVMADDWEV_W_HU_H\0"
5708
  /* 7899 */ "XVADDWEV_W_HU_H\0"
5709
  /* 7915 */ "XVMULWEV_W_HU_H\0"
5710
  /* 7931 */ "XVPACKEV_H\0"
5711
  /* 7942 */ "XVPICKEV_H\0"
5712
  /* 7953 */ "XVBITREV_H\0"
5713
  /* 7964 */ "XVDIV_H\0"
5714
  /* 7972 */ "XVSIGNCOV_H\0"
5715
  /* 7984 */ "XVSUBWOD_W_H\0"
5716
  /* 7997 */ "XVMADDWOD_W_H\0"
5717
  /* 8011 */ "XVADDWOD_W_H\0"
5718
  /* 8024 */ "XVMULWOD_W_H\0"
5719
  /* 8037 */ "XVEXTH_W_H\0"
5720
  /* 8048 */ "XVSLLWIL_W_H\0"
5721
  /* 8061 */ "EXT_W_H\0"
5722
  /* 8069 */ "XVSUBWEV_W_H\0"
5723
  /* 8082 */ "XVMADDWEV_W_H\0"
5724
  /* 8096 */ "XVADDWEV_W_H\0"
5725
  /* 8109 */ "XVMULWEV_W_H\0"
5726
  /* 8122 */ "VEXT2XV_W_H\0"
5727
  /* 8134 */ "XVHSUBW_W_H\0"
5728
  /* 8146 */ "XVHADDW_W_H\0"
5729
  /* 8158 */ "XVMAX_H\0"
5730
  /* 8166 */ "LDX_H\0"
5731
  /* 8172 */ "STX_H\0"
5732
  /* 8178 */ "PseudoXVBZ_H\0"
5733
  /* 8191 */ "PseudoVBZ_H\0"
5734
  /* 8203 */ "XVSETALLNEZ_H\0"
5735
  /* 8217 */ "XVCLZ_H\0"
5736
  /* 8225 */ "PseudoXVBNZ_H\0"
5737
  /* 8239 */ "PseudoVBNZ_H\0"
5738
  /* 8252 */ "XVSETANYEQZ_H\0"
5739
  /* 8266 */ "XVMSKLTZ_H\0"
5740
  /* 8277 */ "PCALAU12I\0"
5741
  /* 8287 */ "PCADDU12I\0"
5742
  /* 8297 */ "PCADDU18I\0"
5743
  /* 8307 */ "PCADDI\0"
5744
  /* 8314 */ "XVLDI\0"
5745
  /* 8320 */ "ANDI\0"
5746
  /* 8325 */ "DBG_PHI\0"
5747
  /* 8333 */ "XORI\0"
5748
  /* 8338 */ "G_FPTOSI\0"
5749
  /* 8347 */ "SLTI\0"
5750
  /* 8352 */ "G_FPTOUI\0"
5751
  /* 8361 */ "SLTUI\0"
5752
  /* 8367 */ "G_FPOWI\0"
5753
  /* 8375 */ "SETX86J\0"
5754
  /* 8383 */ "SETARMJ\0"
5755
  /* 8391 */ "BREAK\0"
5756
  /* 8397 */ "G_PTRMASK\0"
5757
  /* 8407 */ "BL\0"
5758
  /* 8410 */ "DBCL\0"
5759
  /* 8415 */ "HVCL\0"
5760
  /* 8420 */ "GC_LABEL\0"
5761
  /* 8429 */ "DBG_LABEL\0"
5762
  /* 8439 */ "EH_LABEL\0"
5763
  /* 8448 */ "ANNOTATION_LABEL\0"
5764
  /* 8465 */ "ICALL_BRANCH_FUNNEL\0"
5765
  /* 8485 */ "PseudoLA_PCREL\0"
5766
  /* 8500 */ "G_FSHL\0"
5767
  /* 8507 */ "G_SHL\0"
5768
  /* 8513 */ "PseudoB_TAIL\0"
5769
  /* 8526 */ "PseudoJIRL_TAIL\0"
5770
  /* 8542 */ "PseudoTAIL\0"
5771
  /* 8553 */ "G_FCEIL\0"
5772
  /* 8561 */ "SYSCALL\0"
5773
  /* 8569 */ "PATCHABLE_TAIL_CALL\0"
5774
  /* 8589 */ "PseudoJIRL_CALL\0"
5775
  /* 8605 */ "PATCHABLE_TYPED_EVENT_CALL\0"
5776
  /* 8632 */ "PATCHABLE_EVENT_CALL\0"
5777
  /* 8653 */ "FENTRY_CALL\0"
5778
  /* 8665 */ "PseudoCALL\0"
5779
  /* 8676 */ "TLBFILL\0"
5780
  /* 8684 */ "KILL\0"
5781
  /* 8689 */ "G_CONSTANT_POOL\0"
5782
  /* 8705 */ "JIRL\0"
5783
  /* 8710 */ "G_ROTL\0"
5784
  /* 8717 */ "G_VECREDUCE_FMUL\0"
5785
  /* 8734 */ "G_FMUL\0"
5786
  /* 8741 */ "G_VECREDUCE_SEQ_FMUL\0"
5787
  /* 8762 */ "G_STRICT_FMUL\0"
5788
  /* 8776 */ "G_VECREDUCE_MUL\0"
5789
  /* 8792 */ "G_MUL\0"
5790
  /* 8798 */ "XVFFINT_D_L\0"
5791
  /* 8810 */ "XVFFINT_S_L\0"
5792
  /* 8822 */ "G_FREM\0"
5793
  /* 8829 */ "G_STRICT_FREM\0"
5794
  /* 8843 */ "G_SREM\0"
5795
  /* 8850 */ "G_UREM\0"
5796
  /* 8857 */ "G_SDIVREM\0"
5797
  /* 8867 */ "G_UDIVREM\0"
5798
  /* 8877 */ "INLINEASM\0"
5799
  /* 8887 */ "X86CLRTM\0"
5800
  /* 8896 */ "X86SETTM\0"
5801
  /* 8905 */ "PseudoTAIL_MEDIUM\0"
5802
  /* 8923 */ "PseudoCALL_MEDIUM\0"
5803
  /* 8941 */ "G_VECREDUCE_FMINIMUM\0"
5804
  /* 8962 */ "G_FMINIMUM\0"
5805
  /* 8973 */ "G_VECREDUCE_FMAXIMUM\0"
5806
  /* 8994 */ "G_FMAXIMUM\0"
5807
  /* 9005 */ "G_FMINNUM\0"
5808
  /* 9015 */ "G_FMAXNUM\0"
5809
  /* 9025 */ "ANDN\0"
5810
  /* 9030 */ "G_INTRINSIC_ROUNDEVEN\0"
5811
  /* 9052 */ "G_ASSERT_ALIGN\0"
5812
  /* 9067 */ "G_FCOPYSIGN\0"
5813
  /* 9079 */ "G_VECREDUCE_FMIN\0"
5814
  /* 9096 */ "G_ATOMICRMW_FMIN\0"
5815
  /* 9113 */ "G_VECREDUCE_SMIN\0"
5816
  /* 9130 */ "G_SMIN\0"
5817
  /* 9137 */ "G_VECREDUCE_UMIN\0"
5818
  /* 9154 */ "G_UMIN\0"
5819
  /* 9161 */ "G_ATOMICRMW_UMIN\0"
5820
  /* 9178 */ "G_ATOMICRMW_MIN\0"
5821
  /* 9194 */ "G_FSIN\0"
5822
  /* 9201 */ "CFI_INSTRUCTION\0"
5823
  /* 9217 */ "ORN\0"
5824
  /* 9221 */ "ERTN\0"
5825
  /* 9226 */ "ADJCALLSTACKDOWN\0"
5826
  /* 9243 */ "G_SSUBO\0"
5827
  /* 9251 */ "G_USUBO\0"
5828
  /* 9259 */ "G_SADDO\0"
5829
  /* 9267 */ "G_UADDO\0"
5830
  /* 9275 */ "JUMP_TABLE_DEBUG_INFO\0"
5831
  /* 9297 */ "G_SMULO\0"
5832
  /* 9305 */ "G_UMULO\0"
5833
  /* 9313 */ "G_BZERO\0"
5834
  /* 9321 */ "STACKMAP\0"
5835
  /* 9330 */ "G_ATOMICRMW_UDEC_WRAP\0"
5836
  /* 9352 */ "G_ATOMICRMW_UINC_WRAP\0"
5837
  /* 9374 */ "G_BSWAP\0"
5838
  /* 9382 */ "G_SITOFP\0"
5839
  /* 9391 */ "G_UITOFP\0"
5840
  /* 9400 */ "G_FCMP\0"
5841
  /* 9407 */ "G_ICMP\0"
5842
  /* 9414 */ "PseudoUNIMP\0"
5843
  /* 9426 */ "CACOP\0"
5844
  /* 9432 */ "G_CTPOP\0"
5845
  /* 9440 */ "X86DECTOP\0"
5846
  /* 9450 */ "X86INCTOP\0"
5847
  /* 9460 */ "X86MFTOP\0"
5848
  /* 9469 */ "X86MTTOP\0"
5849
  /* 9478 */ "PATCHABLE_OP\0"
5850
  /* 9491 */ "FAULTING_OP\0"
5851
  /* 9503 */ "ADJCALLSTACKUP\0"
5852
  /* 9518 */ "PREALLOCATED_SETUP\0"
5853
  /* 9537 */ "G_FLDEXP\0"
5854
  /* 9546 */ "G_STRICT_FLDEXP\0"
5855
  /* 9562 */ "G_FEXP\0"
5856
  /* 9569 */ "G_FFREXP\0"
5857
  /* 9578 */ "BEQ\0"
5858
  /* 9582 */ "XVREPLVE0_Q\0"
5859
  /* 9594 */ "XVSUB_Q\0"
5860
  /* 9602 */ "SC_Q\0"
5861
  /* 9607 */ "XVADD_Q\0"
5862
  /* 9615 */ "XVSSRANI_D_Q\0"
5863
  /* 9628 */ "XVSRANI_D_Q\0"
5864
  /* 9640 */ "XVSSRLNI_D_Q\0"
5865
  /* 9653 */ "XVSRLNI_D_Q\0"
5866
  /* 9665 */ "XVSSRARNI_D_Q\0"
5867
  /* 9679 */ "XVSRARNI_D_Q\0"
5868
  /* 9692 */ "XVSSRLRNI_D_Q\0"
5869
  /* 9706 */ "XVSRLRNI_D_Q\0"
5870
  /* 9719 */ "XVPERMI_Q\0"
5871
  /* 9729 */ "XVSSRANI_DU_Q\0"
5872
  /* 9743 */ "XVSSRLNI_DU_Q\0"
5873
  /* 9757 */ "XVSSRARNI_DU_Q\0"
5874
  /* 9772 */ "XVSSRLRNI_DU_Q\0"
5875
  /* 9787 */ "DBAR\0"
5876
  /* 9792 */ "IBAR\0"
5877
  /* 9797 */ "G_BR\0"
5878
  /* 9802 */ "INLINEASM_BR\0"
5879
  /* 9815 */ "PseudoBR\0"
5880
  /* 9824 */ "MOVGR2SCR\0"
5881
  /* 9834 */ "G_BLOCK_ADDR\0"
5882
  /* 9847 */ "MEMBARRIER\0"
5883
  /* 9858 */ "G_CONSTANT_FOLD_BARRIER\0"
5884
  /* 9882 */ "PATCHABLE_FUNCTION_ENTER\0"
5885
  /* 9907 */ "G_READCYCLECOUNTER\0"
5886
  /* 9926 */ "G_READ_REGISTER\0"
5887
  /* 9942 */ "G_WRITE_REGISTER\0"
5888
  /* 9959 */ "PseudoLD_CFR\0"
5889
  /* 9972 */ "PseudoST_CFR\0"
5890
  /* 9985 */ "PseudoCopyCFR\0"
5891
  /* 9999 */ "MOVCF2GR\0"
5892
  /* 10008 */ "MOVSCR2GR\0"
5893
  /* 10018 */ "MOVFCSR2GR\0"
5894
  /* 10029 */ "G_ASHR\0"
5895
  /* 10036 */ "G_FSHR\0"
5896
  /* 10043 */ "G_LSHR\0"
5897
  /* 10050 */ "LDDIR\0"
5898
  /* 10056 */ "TLBCLR\0"
5899
  /* 10063 */ "NOR\0"
5900
  /* 10067 */ "G_FFLOOR\0"
5901
  /* 10076 */ "G_BUILD_VECTOR\0"
5902
  /* 10091 */ "G_SHUFFLE_VECTOR\0"
5903
  /* 10108 */ "G_VECREDUCE_XOR\0"
5904
  /* 10124 */ "G_XOR\0"
5905
  /* 10130 */ "G_ATOMICRMW_XOR\0"
5906
  /* 10146 */ "G_VECREDUCE_OR\0"
5907
  /* 10161 */ "G_OR\0"
5908
  /* 10166 */ "G_ATOMICRMW_OR\0"
5909
  /* 10181 */ "MOVGR2FCSR\0"
5910
  /* 10192 */ "RDFCSR\0"
5911
  /* 10199 */ "WRFCSR\0"
5912
  /* 10206 */ "G_ROTR\0"
5913
  /* 10213 */ "G_INTTOPTR\0"
5914
  /* 10224 */ "TLBWR\0"
5915
  /* 10230 */ "GCSRWR\0"
5916
  /* 10237 */ "G_FABS\0"
5917
  /* 10244 */ "PseudoLA_ABS\0"
5918
  /* 10257 */ "G_ABS\0"
5919
  /* 10263 */ "G_UNMERGE_VALUES\0"
5920
  /* 10280 */ "G_MERGE_VALUES\0"
5921
  /* 10295 */ "G_FCOS\0"
5922
  /* 10302 */ "G_CONCAT_VECTORS\0"
5923
  /* 10319 */ "COPY_TO_REGCLASS\0"
5924
  /* 10336 */ "G_IS_FPCLASS\0"
5925
  /* 10349 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
5926
  /* 10379 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
5927
  /* 10406 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
5928
  /* 10444 */ "XVFMINA_S\0"
5929
  /* 10454 */ "XVFMAXA_S\0"
5930
  /* 10464 */ "FSCALEB_S\0"
5931
  /* 10474 */ "XVFLOGB_S\0"
5932
  /* 10484 */ "XVFSUB_S\0"
5933
  /* 10493 */ "XVFMSUB_S\0"
5934
  /* 10503 */ "XVFNMSUB_S\0"
5935
  /* 10514 */ "XVFADD_S\0"
5936
  /* 10523 */ "XVFMADD_S\0"
5937
  /* 10533 */ "XVFNMADD_S\0"
5938
  /* 10544 */ "FLD_S\0"
5939
  /* 10550 */ "XVFCVTH_D_S\0"
5940
  /* 10562 */ "XVFCVTL_D_S\0"
5941
  /* 10574 */ "FCVT_D_S\0"
5942
  /* 10583 */ "XVFCMP_CLE_S\0"
5943
  /* 10596 */ "FLDLE_S\0"
5944
  /* 10604 */ "XVFCMP_SLE_S\0"
5945
  /* 10617 */ "FSTLE_S\0"
5946
  /* 10625 */ "XVFCMP_CULE_S\0"
5947
  /* 10639 */ "XVFCMP_SULE_S\0"
5948
  /* 10653 */ "XVFCMP_CNE_S\0"
5949
  /* 10666 */ "XVFRINTRNE_S\0"
5950
  /* 10679 */ "XVFCMP_SNE_S\0"
5951
  /* 10692 */ "XVFCMP_CUNE_S\0"
5952
  /* 10706 */ "XVFCMP_SUNE_S\0"
5953
  /* 10720 */ "XVFRECIPE_S\0"
5954
  /* 10732 */ "XVFRSQRTE_S\0"
5955
  /* 10744 */ "XVFCMP_CAF_S\0"
5956
  /* 10757 */ "XVFCMP_SAF_S\0"
5957
  /* 10770 */ "FNEG_S\0"
5958
  /* 10777 */ "XVFCVT_H_S\0"
5959
  /* 10788 */ "XVFMUL_S\0"
5960
  /* 10797 */ "FTINTRNE_L_S\0"
5961
  /* 10810 */ "XVFTINTRNEH_L_S\0"
5962
  /* 10826 */ "XVFTINTRMH_L_S\0"
5963
  /* 10841 */ "XVFTINTRPH_L_S\0"
5964
  /* 10856 */ "XVFTINTH_L_S\0"
5965
  /* 10869 */ "XVFTINTRZH_L_S\0"
5966
  /* 10884 */ "XVFTINTRNEL_L_S\0"
5967
  /* 10900 */ "XVFTINTRML_L_S\0"
5968
  /* 10915 */ "XVFTINTRPL_L_S\0"
5969
  /* 10930 */ "XVFTINTL_L_S\0"
5970
  /* 10943 */ "XVFTINTRZL_L_S\0"
5971
  /* 10958 */ "FTINTRM_L_S\0"
5972
  /* 10970 */ "FTINTRP_L_S\0"
5973
  /* 10982 */ "FTINT_L_S\0"
5974
  /* 10992 */ "FTINTRZ_L_S\0"
5975
  /* 11004 */ "XVFRINTRM_S\0"
5976
  /* 11016 */ "FCOPYSIGN_S\0"
5977
  /* 11028 */ "XVFMIN_S\0"
5978
  /* 11037 */ "XVFCMP_CUN_S\0"
5979
  /* 11050 */ "XVFCMP_SUN_S\0"
5980
  /* 11063 */ "XVFRECIP_S\0"
5981
  /* 11074 */ "XVFRINTRP_S\0"
5982
  /* 11086 */ "XVFCMP_CEQ_S\0"
5983
  /* 11099 */ "XVFCMP_SEQ_S\0"
5984
  /* 11112 */ "XVFCMP_CUEQ_S\0"
5985
  /* 11126 */ "XVFCMP_SUEQ_S\0"
5986
  /* 11140 */ "MOVFRH2GR_S\0"
5987
  /* 11152 */ "MOVFR2GR_S\0"
5988
  /* 11163 */ "XVFCMP_COR_S\0"
5989
  /* 11176 */ "XVFCMP_SOR_S\0"
5990
  /* 11189 */ "FABS_S\0"
5991
  /* 11196 */ "XVFCLASS_S\0"
5992
  /* 11207 */ "FLDGT_S\0"
5993
  /* 11215 */ "FSTGT_S\0"
5994
  /* 11223 */ "XVFCMP_CLT_S\0"
5995
  /* 11236 */ "XVFCMP_SLT_S\0"
5996
  /* 11249 */ "XVFCMP_CULT_S\0"
5997
  /* 11263 */ "XVFCMP_SULT_S\0"
5998
  /* 11277 */ "XVFRINT_S\0"
5999
  /* 11287 */ "XVFSQRT_S\0"
6000
  /* 11297 */ "XVFRSQRT_S\0"
6001
  /* 11308 */ "FST_S\0"
6002
  /* 11314 */ "XVFTINT_WU_S\0"
6003
  /* 11327 */ "XVFTINTRZ_WU_S\0"
6004
  /* 11342 */ "XVFDIV_S\0"
6005
  /* 11351 */ "FMOV_S\0"
6006
  /* 11358 */ "XVFTINTRNE_W_S\0"
6007
  /* 11373 */ "XVFTINTRM_W_S\0"
6008
  /* 11387 */ "XVFTINTRP_W_S\0"
6009
  /* 11401 */ "XVFTINT_W_S\0"
6010
  /* 11413 */ "XVFTINTRZ_W_S\0"
6011
  /* 11427 */ "XVFMAX_S\0"
6012
  /* 11436 */ "FLDX_S\0"
6013
  /* 11443 */ "FSTX_S\0"
6014
  /* 11450 */ "XVFRINTRZ_S\0"
6015
  /* 11462 */ "MOVFR2CF_xS\0"
6016
  /* 11474 */ "FSEL_xS\0"
6017
  /* 11482 */ "MOVCF2FR_xS\0"
6018
  /* 11494 */ "G_SSUBSAT\0"
6019
  /* 11504 */ "G_USUBSAT\0"
6020
  /* 11514 */ "G_SADDSAT\0"
6021
  /* 11524 */ "G_UADDSAT\0"
6022
  /* 11534 */ "G_SSHLSAT\0"
6023
  /* 11544 */ "G_USHLSAT\0"
6024
  /* 11554 */ "G_SMULFIXSAT\0"
6025
  /* 11567 */ "G_UMULFIXSAT\0"
6026
  /* 11580 */ "G_SDIVFIXSAT\0"
6027
  /* 11593 */ "G_UDIVFIXSAT\0"
6028
  /* 11606 */ "G_EXTRACT\0"
6029
  /* 11616 */ "G_SELECT\0"
6030
  /* 11625 */ "G_BRINDIRECT\0"
6031
  /* 11638 */ "PATCHABLE_RET\0"
6032
  /* 11652 */ "PseudoRET\0"
6033
  /* 11662 */ "G_MEMSET\0"
6034
  /* 11671 */ "PATCHABLE_FUNCTION_EXIT\0"
6035
  /* 11695 */ "G_BRJT\0"
6036
  /* 11702 */ "BLT\0"
6037
  /* 11706 */ "G_EXTRACT_VECTOR_ELT\0"
6038
  /* 11727 */ "G_INSERT_VECTOR_ELT\0"
6039
  /* 11747 */ "SLT\0"
6040
  /* 11751 */ "G_FCONSTANT\0"
6041
  /* 11763 */ "G_CONSTANT\0"
6042
  /* 11774 */ "G_INTRINSIC_CONVERGENT\0"
6043
  /* 11797 */ "STATEPOINT\0"
6044
  /* 11808 */ "PATCHPOINT\0"
6045
  /* 11819 */ "G_PTRTOINT\0"
6046
  /* 11830 */ "G_FRINT\0"
6047
  /* 11838 */ "G_INTRINSIC_LRINT\0"
6048
  /* 11856 */ "G_FNEARBYINT\0"
6049
  /* 11869 */ "PseudoLA_GOT\0"
6050
  /* 11882 */ "G_VASTART\0"
6051
  /* 11892 */ "LIFETIME_START\0"
6052
  /* 11907 */ "G_INVOKE_REGION_START\0"
6053
  /* 11929 */ "G_INSERT\0"
6054
  /* 11938 */ "G_FSQRT\0"
6055
  /* 11946 */ "G_STRICT_FSQRT\0"
6056
  /* 11961 */ "G_BITCAST\0"
6057
  /* 11971 */ "G_ADDRSPACE_CAST\0"
6058
  /* 11988 */ "DBG_VALUE_LIST\0"
6059
  /* 12003 */ "XVST\0"
6060
  /* 12008 */ "G_FPEXT\0"
6061
  /* 12016 */ "G_SEXT\0"
6062
  /* 12023 */ "G_ASSERT_SEXT\0"
6063
  /* 12037 */ "G_ANYEXT\0"
6064
  /* 12046 */ "G_ZEXT\0"
6065
  /* 12053 */ "G_ASSERT_ZEXT\0"
6066
  /* 12067 */ "XVSSUB_BU\0"
6067
  /* 12077 */ "XVSADD_BU\0"
6068
  /* 12087 */ "LD_BU\0"
6069
  /* 12093 */ "XVMOD_BU\0"
6070
  /* 12102 */ "XVABSD_BU\0"
6071
  /* 12112 */ "XVSLE_BU\0"
6072
  /* 12121 */ "XVAVG_BU\0"
6073
  /* 12130 */ "XVMUH_BU\0"
6074
  /* 12139 */ "XVSUBWOD_H_BU\0"
6075
  /* 12153 */ "XVMADDWOD_H_BU\0"
6076
  /* 12168 */ "XVADDWOD_H_BU\0"
6077
  /* 12182 */ "XVMULWOD_H_BU\0"
6078
  /* 12196 */ "XVSUBWEV_H_BU\0"
6079
  /* 12210 */ "XVMADDWEV_H_BU\0"
6080
  /* 12225 */ "XVADDWEV_H_BU\0"
6081
  /* 12239 */ "XVMULWEV_H_BU\0"
6082
  /* 12253 */ "XVSUBI_BU\0"
6083
  /* 12263 */ "XVADDI_BU\0"
6084
  /* 12273 */ "XVSLEI_BU\0"
6085
  /* 12283 */ "XVMINI_BU\0"
6086
  /* 12293 */ "XVSLTI_BU\0"
6087
  /* 12303 */ "XVMAXI_BU\0"
6088
  /* 12313 */ "X86MUL_BU\0"
6089
  /* 12323 */ "XVMIN_BU\0"
6090
  /* 12332 */ "VPICKVE2GR_BU\0"
6091
  /* 12346 */ "XVAVGR_BU\0"
6092
  /* 12356 */ "XVSAT_BU\0"
6093
  /* 12365 */ "XVSLT_BU\0"
6094
  /* 12374 */ "VEXT2XV_DU_BU\0"
6095
  /* 12388 */ "XVEXTH_HU_BU\0"
6096
  /* 12401 */ "XVSLLWIL_HU_BU\0"
6097
  /* 12416 */ "VEXT2XV_HU_BU\0"
6098
  /* 12430 */ "XVHSUBW_HU_BU\0"
6099
  /* 12444 */ "XVHADDW_HU_BU\0"
6100
  /* 12458 */ "VEXT2XV_WU_BU\0"
6101
  /* 12472 */ "XVDIV_BU\0"
6102
  /* 12481 */ "XVMAX_BU\0"
6103
  /* 12490 */ "LDX_BU\0"
6104
  /* 12497 */ "AMMIN__DB_DU\0"
6105
  /* 12510 */ "AMMAX__DB_DU\0"
6106
  /* 12523 */ "X86SUB_DU\0"
6107
  /* 12533 */ "XVSSUB_DU\0"
6108
  /* 12543 */ "X86ADD_DU\0"
6109
  /* 12553 */ "XVSADD_DU\0"
6110
  /* 12563 */ "XVMOD_DU\0"
6111
  /* 12572 */ "XVABSD_DU\0"
6112
  /* 12582 */ "XVSLE_DU\0"
6113
  /* 12591 */ "XVAVG_DU\0"
6114
  /* 12600 */ "MULH_DU\0"
6115
  /* 12608 */ "XVMUH_DU\0"
6116
  /* 12617 */ "XVSUBI_DU\0"
6117
  /* 12627 */ "XVADDI_DU\0"
6118
  /* 12637 */ "XVSLEI_DU\0"
6119
  /* 12647 */ "XVMINI_DU\0"
6120
  /* 12657 */ "XVSLTI_DU\0"
6121
  /* 12667 */ "XVMAXI_DU\0"
6122
  /* 12677 */ "X86MUL_DU\0"
6123
  /* 12687 */ "AMMIN_DU\0"
6124
  /* 12696 */ "XVMIN_DU\0"
6125
  /* 12705 */ "XVSUBWOD_Q_DU\0"
6126
  /* 12719 */ "XVMADDWOD_Q_DU\0"
6127
  /* 12734 */ "XVADDWOD_Q_DU\0"
6128
  /* 12748 */ "XVMULWOD_Q_DU\0"
6129
  /* 12762 */ "XVSUBWEV_Q_DU\0"
6130
  /* 12776 */ "XVMADDWEV_Q_DU\0"
6131
  /* 12791 */ "XVADDWEV_Q_DU\0"
6132
  /* 12805 */ "XVMULWEV_Q_DU\0"
6133
  /* 12819 */ "XVPICKVE2GR_DU\0"
6134
  /* 12834 */ "XVAVGR_DU\0"
6135
  /* 12844 */ "XVSAT_DU\0"
6136
  /* 12853 */ "XVSLT_DU\0"
6137
  /* 12862 */ "XVEXTH_QU_DU\0"
6138
  /* 12875 */ "XVEXTL_QU_DU\0"
6139
  /* 12888 */ "XVHSUBW_QU_DU\0"
6140
  /* 12902 */ "XVHADDW_QU_DU\0"
6141
  /* 12916 */ "XVDIV_DU\0"
6142
  /* 12925 */ "AMMAX_DU\0"
6143
  /* 12934 */ "XVMAX_DU\0"
6144
  /* 12943 */ "BGEU\0"
6145
  /* 12948 */ "XVSSUB_HU\0"
6146
  /* 12958 */ "XVSADD_HU\0"
6147
  /* 12968 */ "LD_HU\0"
6148
  /* 12974 */ "XVMOD_HU\0"
6149
  /* 12983 */ "XVABSD_HU\0"
6150
  /* 12993 */ "XVSLE_HU\0"
6151
  /* 13002 */ "XVAVG_HU\0"
6152
  /* 13011 */ "XVMUH_HU\0"
6153
  /* 13020 */ "XVSUBI_HU\0"
6154
  /* 13030 */ "XVADDI_HU\0"
6155
  /* 13040 */ "XVSLEI_HU\0"
6156
  /* 13050 */ "XVMINI_HU\0"
6157
  /* 13060 */ "XVSLTI_HU\0"
6158
  /* 13070 */ "XVMAXI_HU\0"
6159
  /* 13080 */ "X86MUL_HU\0"
6160
  /* 13090 */ "XVMIN_HU\0"
6161
  /* 13099 */ "VPICKVE2GR_HU\0"
6162
  /* 13113 */ "XVAVGR_HU\0"
6163
  /* 13123 */ "XVSAT_HU\0"
6164
  /* 13132 */ "XVSLT_HU\0"
6165
  /* 13141 */ "VEXT2XV_DU_HU\0"
6166
  /* 13155 */ "XVEXTH_WU_HU\0"
6167
  /* 13168 */ "XVSLLWIL_WU_HU\0"
6168
  /* 13183 */ "VEXT2XV_WU_HU\0"
6169
  /* 13197 */ "XVHSUBW_WU_HU\0"
6170
  /* 13211 */ "XVHADDW_WU_HU\0"
6171
  /* 13225 */ "XVDIV_HU\0"
6172
  /* 13234 */ "XVSUBWOD_W_HU\0"
6173
  /* 13248 */ "XVMADDWOD_W_HU\0"
6174
  /* 13263 */ "XVADDWOD_W_HU\0"
6175
  /* 13277 */ "XVMULWOD_W_HU\0"
6176
  /* 13291 */ "XVSUBWEV_W_HU\0"
6177
  /* 13305 */ "XVMADDWEV_W_HU\0"
6178
  /* 13320 */ "XVADDWEV_W_HU\0"
6179
  /* 13334 */ "XVMULWEV_W_HU\0"
6180
  /* 13348 */ "XVMAX_HU\0"
6181
  /* 13357 */ "LDX_HU\0"
6182
  /* 13364 */ "XVFFINT_D_LU\0"
6183
  /* 13377 */ "BLTU\0"
6184
  /* 13382 */ "SLTU\0"
6185
  /* 13387 */ "AMMIN__DB_WU\0"
6186
  /* 13400 */ "AMMAX__DB_WU\0"
6187
  /* 13413 */ "X86SUB_WU\0"
6188
  /* 13423 */ "XVSSUB_WU\0"
6189
  /* 13433 */ "X86ADD_WU\0"
6190
  /* 13443 */ "XVSADD_WU\0"
6191
  /* 13453 */ "LD_WU\0"
6192
  /* 13459 */ "XVMOD_WU\0"
6193
  /* 13468 */ "XVABSD_WU\0"
6194
  /* 13478 */ "XVSUBWOD_D_WU\0"
6195
  /* 13492 */ "XVMADDWOD_D_WU\0"
6196
  /* 13507 */ "XVADDWOD_D_WU\0"
6197
  /* 13521 */ "XVMULWOD_D_WU\0"
6198
  /* 13535 */ "XVSUBWEV_D_WU\0"
6199
  /* 13549 */ "XVMADDWEV_D_WU\0"
6200
  /* 13564 */ "XVADDWEV_D_WU\0"
6201
  /* 13578 */ "XVMULWEV_D_WU\0"
6202
  /* 13592 */ "MULW_D_WU\0"
6203
  /* 13602 */ "XVSLE_WU\0"
6204
  /* 13611 */ "XVAVG_WU\0"
6205
  /* 13620 */ "MULH_WU\0"
6206
  /* 13628 */ "XVMUH_WU\0"
6207
  /* 13637 */ "XVSUBI_WU\0"
6208
  /* 13647 */ "XVADDI_WU\0"
6209
  /* 13657 */ "XVSLEI_WU\0"
6210
  /* 13667 */ "XVMINI_WU\0"
6211
  /* 13677 */ "XVSLTI_WU\0"
6212
  /* 13687 */ "XVMAXI_WU\0"
6213
  /* 13697 */ "ALSL_WU\0"
6214
  /* 13705 */ "X86MUL_WU\0"
6215
  /* 13715 */ "AMMIN_WU\0"
6216
  /* 13724 */ "XVMIN_WU\0"
6217
  /* 13733 */ "XVPICKVE2GR_WU\0"
6218
  /* 13748 */ "XVAVGR_WU\0"
6219
  /* 13758 */ "XVFFINT_S_WU\0"
6220
  /* 13771 */ "XVSAT_WU\0"
6221
  /* 13780 */ "XVSLT_WU\0"
6222
  /* 13789 */ "XVEXTH_DU_WU\0"
6223
  /* 13802 */ "XVSLLWIL_DU_WU\0"
6224
  /* 13817 */ "VEXT2XV_DU_WU\0"
6225
  /* 13831 */ "XVHSUBW_DU_WU\0"
6226
  /* 13845 */ "XVHADDW_DU_WU\0"
6227
  /* 13859 */ "XVDIV_WU\0"
6228
  /* 13868 */ "AMMAX_WU\0"
6229
  /* 13877 */ "XVMAX_WU\0"
6230
  /* 13886 */ "LDX_WU\0"
6231
  /* 13893 */ "G_FDIV\0"
6232
  /* 13900 */ "G_STRICT_FDIV\0"
6233
  /* 13914 */ "G_SDIV\0"
6234
  /* 13921 */ "G_UDIV\0"
6235
  /* 13928 */ "G_GET_FPENV\0"
6236
  /* 13940 */ "G_RESET_FPENV\0"
6237
  /* 13954 */ "G_SET_FPENV\0"
6238
  /* 13966 */ "XVAND_V\0"
6239
  /* 13974 */ "XVBITSEL_V\0"
6240
  /* 13985 */ "XVBSLL_V\0"
6241
  /* 13994 */ "XVBSRL_V\0"
6242
  /* 14003 */ "XVANDN_V\0"
6243
  /* 14012 */ "XVORN_V\0"
6244
  /* 14020 */ "XVNOR_V\0"
6245
  /* 14028 */ "XVOR_V\0"
6246
  /* 14035 */ "XVXOR_V\0"
6247
  /* 14043 */ "XVSETNEZ_V\0"
6248
  /* 14054 */ "XVSETEQZ_V\0"
6249
  /* 14065 */ "REVB_2W\0"
6250
  /* 14073 */ "REVH_2W\0"
6251
  /* 14081 */ "G_FPOW\0"
6252
  /* 14088 */ "XVREPLVE0_W\0"
6253
  /* 14100 */ "XVINSVE0_W\0"
6254
  /* 14111 */ "XVADDA_W\0"
6255
  /* 14120 */ "X86SRA_W\0"
6256
  /* 14129 */ "ARMSRA_W\0"
6257
  /* 14138 */ "XVSRA_W\0"
6258
  /* 14146 */ "AMADD__DB_W\0"
6259
  /* 14158 */ "AMAND__DB_W\0"
6260
  /* 14170 */ "AMMIN__DB_W\0"
6261
  /* 14182 */ "AMSWAP__DB_W\0"
6262
  /* 14195 */ "AMOR__DB_W\0"
6263
  /* 14206 */ "AMXOR__DB_W\0"
6264
  /* 14218 */ "AMCAS__DB_W\0"
6265
  /* 14230 */ "AMMAX__DB_W\0"
6266
  /* 14242 */ "X86SUB_W\0"
6267
  /* 14251 */ "ARMSUB_W\0"
6268
  /* 14260 */ "XVMSUB_W\0"
6269
  /* 14269 */ "XVSSUB_W\0"
6270
  /* 14278 */ "XVSUB_W\0"
6271
  /* 14286 */ "CRCC_W_B_W\0"
6272
  /* 14297 */ "CRC_W_B_W\0"
6273
  /* 14307 */ "X86SBC_W\0"
6274
  /* 14316 */ "ARMSBC_W\0"
6275
  /* 14325 */ "X86ADC_W\0"
6276
  /* 14334 */ "ARMADC_W\0"
6277
  /* 14343 */ "X86DEC_W\0"
6278
  /* 14352 */ "X86INC_W\0"
6279
  /* 14361 */ "SC_W\0"
6280
  /* 14366 */ "X86ADD_W\0"
6281
  /* 14375 */ "AMADD_W\0"
6282
  /* 14383 */ "ARMADD_W\0"
6283
  /* 14392 */ "XVMADD_W\0"
6284
  /* 14401 */ "XVSADD_W\0"
6285
  /* 14410 */ "XVADD_W\0"
6286
  /* 14418 */ "LD_W\0"
6287
  /* 14423 */ "X86AND_W\0"
6288
  /* 14432 */ "AMAND_W\0"
6289
  /* 14440 */ "ARMAND_W\0"
6290
  /* 14449 */ "XVPACKOD_W\0"
6291
  /* 14460 */ "XVPICKOD_W\0"
6292
  /* 14471 */ "XVMOD_W\0"
6293
  /* 14479 */ "IOCSRRD_W\0"
6294
  /* 14489 */ "XVABSD_W\0"
6295
  /* 14498 */ "XVSUBWOD_D_W\0"
6296
  /* 14511 */ "XVMADDWOD_D_W\0"
6297
  /* 14525 */ "XVADDWOD_D_W\0"
6298
  /* 14538 */ "XVMULWOD_D_W\0"
6299
  /* 14551 */ "XVFFINTH_D_W\0"
6300
  /* 14564 */ "XVEXTH_D_W\0"
6301
  /* 14575 */ "XVSLLWIL_D_W\0"
6302
  /* 14588 */ "XVFFINTL_D_W\0"
6303
  /* 14601 */ "FFINT_D_W\0"
6304
  /* 14611 */ "XVSUBWEV_D_W\0"
6305
  /* 14624 */ "XVMADDWEV_D_W\0"
6306
  /* 14638 */ "XVADDWEV_D_W\0"
6307
  /* 14651 */ "XVMULWEV_D_W\0"
6308
  /* 14664 */ "VEXT2XV_D_W\0"
6309
  /* 14676 */ "XVHSUBW_D_W\0"
6310
  /* 14688 */ "XVHADDW_D_W\0"
6311
  /* 14700 */ "MULW_D_W\0"
6312
  /* 14709 */ "CRCC_W_D_W\0"
6313
  /* 14720 */ "CRC_W_D_W\0"
6314
  /* 14730 */ "LDLE_W\0"
6315
  /* 14737 */ "XVSLE_W\0"
6316
  /* 14745 */ "STLE_W\0"
6317
  /* 14752 */ "XVPICKVE_W\0"
6318
  /* 14763 */ "XVREPLVE_W\0"
6319
  /* 14774 */ "XVSHUF_W\0"
6320
  /* 14783 */ "XVNEG_W\0"
6321
  /* 14791 */ "XVAVG_W\0"
6322
  /* 14799 */ "RDTIMEH_W\0"
6323
  /* 14809 */ "MULH_W\0"
6324
  /* 14816 */ "MOVGR2FRH_W\0"
6325
  /* 14828 */ "XVMUH_W\0"
6326
  /* 14836 */ "XVILVH_W\0"
6327
  /* 14845 */ "XVSSRANI_H_W\0"
6328
  /* 14858 */ "XVSRANI_H_W\0"
6329
  /* 14870 */ "XVSSRLNI_H_W\0"
6330
  /* 14883 */ "XVSRLNI_H_W\0"
6331
  /* 14895 */ "XVSSRARNI_H_W\0"
6332
  /* 14909 */ "XVSRARNI_H_W\0"
6333
  /* 14922 */ "XVSSRLRNI_H_W\0"
6334
  /* 14936 */ "XVSRLRNI_H_W\0"
6335
  /* 14949 */ "XVSSRAN_H_W\0"
6336
  /* 14961 */ "XVSRAN_H_W\0"
6337
  /* 14972 */ "XVSSRLN_H_W\0"
6338
  /* 14984 */ "XVSRLN_H_W\0"
6339
  /* 14995 */ "XVSSRARN_H_W\0"
6340
  /* 15008 */ "XVSRARN_H_W\0"
6341
  /* 15020 */ "XVSSRLRN_H_W\0"
6342
  /* 15033 */ "XVSRLRN_H_W\0"
6343
  /* 15045 */ "CRCC_W_H_W\0"
6344
  /* 15056 */ "CRC_W_H_W\0"
6345
  /* 15066 */ "ADDU12I_W\0"
6346
  /* 15076 */ "LU12I_W\0"
6347
  /* 15084 */ "XVSHUF4I_W\0"
6348
  /* 15095 */ "X86SRAI_W\0"
6349
  /* 15105 */ "ARMSRAI_W\0"
6350
  /* 15115 */ "XVSRAI_W\0"
6351
  /* 15124 */ "ADDI_W\0"
6352
  /* 15131 */ "XVSLEI_W\0"
6353
  /* 15140 */ "XVREPL128VEI_W\0"
6354
  /* 15155 */ "VREPLVEI_W\0"
6355
  /* 15166 */ "X86RCLI_W\0"
6356
  /* 15176 */ "X86SLLI_W\0"
6357
  /* 15186 */ "ARMSLLI_W\0"
6358
  /* 15196 */ "XVSLLI_W\0"
6359
  /* 15205 */ "PseudoXVREPLI_W\0"
6360
  /* 15221 */ "PseudoVREPLI_W\0"
6361
  /* 15236 */ "X86SRLI_W\0"
6362
  /* 15246 */ "ARMSRLI_W\0"
6363
  /* 15256 */ "XVSRLI_W\0"
6364
  /* 15265 */ "X86ROTLI_W\0"
6365
  /* 15276 */ "PseudoLI_W\0"
6366
  /* 15287 */ "XVPERMI_W\0"
6367
  /* 15297 */ "XVMINI_W\0"
6368
  /* 15306 */ "XVSEQI_W\0"
6369
  /* 15315 */ "XVSRARI_W\0"
6370
  /* 15325 */ "X86RCRI_W\0"
6371
  /* 15335 */ "XVBITCLRI_W\0"
6372
  /* 15347 */ "XVSRLRI_W\0"
6373
  /* 15357 */ "X86ROTRI_W\0"
6374
  /* 15368 */ "ARMROTRI_W\0"
6375
  /* 15379 */ "XVROTRI_W\0"
6376
  /* 15389 */ "XVBITSETI_W\0"
6377
  /* 15401 */ "XVSLTI_W\0"
6378
  /* 15410 */ "XVBITREVI_W\0"
6379
  /* 15422 */ "XVMAXI_W\0"
6380
  /* 15431 */ "BYTEPICK_W\0"
6381
  /* 15442 */ "BSTRPICK_W\0"
6382
  /* 15453 */ "X86RCL_W\0"
6383
  /* 15462 */ "LDL_W\0"
6384
  /* 15468 */ "RDTIMEL_W\0"
6385
  /* 15478 */ "SCREL_W\0"
6386
  /* 15486 */ "X86SLL_W\0"
6387
  /* 15495 */ "ARMSLL_W\0"
6388
  /* 15504 */ "XVSLL_W\0"
6389
  /* 15512 */ "XVLDREPL_W\0"
6390
  /* 15523 */ "X86SRL_W\0"
6391
  /* 15532 */ "ARMSRL_W\0"
6392
  /* 15541 */ "XVSRL_W\0"
6393
  /* 15549 */ "ALSL_W\0"
6394
  /* 15556 */ "X86ROTL_W\0"
6395
  /* 15566 */ "STL_W\0"
6396
  /* 15572 */ "X86MUL_W\0"
6397
  /* 15581 */ "XVMUL_W\0"
6398
  /* 15589 */ "XVILVL_W\0"
6399
  /* 15598 */ "XVSTELM_W\0"
6400
  /* 15608 */ "XVPERM_W\0"
6401
  /* 15617 */ "AMMIN_W\0"
6402
  /* 15625 */ "XVMIN_W\0"
6403
  /* 15633 */ "XVCLO_W\0"
6404
  /* 15641 */ "CTO_W\0"
6405
  /* 15647 */ "AMSWAP_W\0"
6406
  /* 15656 */ "LLACQ_W\0"
6407
  /* 15664 */ "XVSEQ_W\0"
6408
  /* 15672 */ "XVSRAR_W\0"
6409
  /* 15681 */ "X86RCR_W\0"
6410
  /* 15690 */ "LDR_W\0"
6411
  /* 15696 */ "MOVGR2FR_W\0"
6412
  /* 15707 */ "XVPICKVE2GR_W\0"
6413
  /* 15721 */ "XVAVGR_W\0"
6414
  /* 15730 */ "XVBITCLR_W\0"
6415
  /* 15741 */ "XVSRLR_W\0"
6416
  /* 15750 */ "X86OR_W\0"
6417
  /* 15758 */ "AMOR_W\0"
6418
  /* 15765 */ "ARMOR_W\0"
6419
  /* 15773 */ "X86XOR_W\0"
6420
  /* 15782 */ "AMXOR_W\0"
6421
  /* 15790 */ "ARMXOR_W\0"
6422
  /* 15799 */ "X86ROTR_W\0"
6423
  /* 15809 */ "ARMROTR_W\0"
6424
  /* 15819 */ "XVROTR_W\0"
6425
  /* 15828 */ "LDPTR_W\0"
6426
  /* 15836 */ "STPTR_W\0"
6427
  /* 15844 */ "STR_W\0"
6428
  /* 15850 */ "XVREPLGR2VR_W\0"
6429
  /* 15864 */ "XVINSGR2VR_W\0"
6430
  /* 15877 */ "IOCSRWR_W\0"
6431
  /* 15887 */ "AMCAS_W\0"
6432
  /* 15895 */ "BSTRINS_W\0"
6433
  /* 15905 */ "XVEXTRINS_W\0"
6434
  /* 15917 */ "XVFFINT_S_W\0"
6435
  /* 15929 */ "XVSAT_W\0"
6436
  /* 15937 */ "XVBITSET_W\0"
6437
  /* 15948 */ "LDGT_W\0"
6438
  /* 15955 */ "STGT_W\0"
6439
  /* 15962 */ "XVSLT_W\0"
6440
  /* 15970 */ "XVPCNT_W\0"
6441
  /* 15979 */ "ARMNOT_W\0"
6442
  /* 15988 */ "ST_W\0"
6443
  /* 15993 */ "XVSSRANI_HU_W\0"
6444
  /* 16007 */ "XVSSRLNI_HU_W\0"
6445
  /* 16021 */ "XVSSRARNI_HU_W\0"
6446
  /* 16036 */ "XVSSRLRNI_HU_W\0"
6447
  /* 16051 */ "XVSSRAN_HU_W\0"
6448
  /* 16064 */ "XVSSRLN_HU_W\0"
6449
  /* 16077 */ "XVSSRARN_HU_W\0"
6450
  /* 16091 */ "XVSSRLRN_HU_W\0"
6451
  /* 16105 */ "XVMADDWOD_D_WU_W\0"
6452
  /* 16122 */ "XVADDWOD_D_WU_W\0"
6453
  /* 16138 */ "XVMULWOD_D_WU_W\0"
6454
  /* 16154 */ "XVMADDWEV_D_WU_W\0"
6455
  /* 16171 */ "XVADDWEV_D_WU_W\0"
6456
  /* 16187 */ "XVMULWEV_D_WU_W\0"
6457
  /* 16203 */ "XVPACKEV_W\0"
6458
  /* 16214 */ "XVPICKEV_W\0"
6459
  /* 16225 */ "XVBITREV_W\0"
6460
  /* 16236 */ "XVDIV_W\0"
6461
  /* 16244 */ "XVSIGNCOV_W\0"
6462
  /* 16256 */ "ARMMOV_W\0"
6463
  /* 16265 */ "CRCC_W_W_W\0"
6464
  /* 16276 */ "CRC_W_W_W\0"
6465
  /* 16286 */ "AMMAX_W\0"
6466
  /* 16294 */ "XVMAX_W\0"
6467
  /* 16302 */ "LDX_W\0"
6468
  /* 16308 */ "ARMRRX_W\0"
6469
  /* 16317 */ "STX_W\0"
6470
  /* 16323 */ "PseudoXVBZ_W\0"
6471
  /* 16336 */ "PseudoVBZ_W\0"
6472
  /* 16348 */ "XVSETALLNEZ_W\0"
6473
  /* 16362 */ "XVCLZ_W\0"
6474
  /* 16370 */ "PseudoXVBNZ_W\0"
6475
  /* 16384 */ "PseudoVBNZ_W\0"
6476
  /* 16397 */ "XVSETANYEQZ_W\0"
6477
  /* 16411 */ "CTZ_W\0"
6478
  /* 16417 */ "XVMSKLTZ_W\0"
6479
  /* 16428 */ "PseudoAtomicStoreW\0"
6480
  /* 16447 */ "G_VECREDUCE_FMAX\0"
6481
  /* 16464 */ "G_ATOMICRMW_FMAX\0"
6482
  /* 16481 */ "G_VECREDUCE_SMAX\0"
6483
  /* 16498 */ "G_SMAX\0"
6484
  /* 16505 */ "G_VECREDUCE_UMAX\0"
6485
  /* 16522 */ "G_UMAX\0"
6486
  /* 16529 */ "G_ATOMICRMW_UMAX\0"
6487
  /* 16546 */ "G_ATOMICRMW_MAX\0"
6488
  /* 16562 */ "PRELDX\0"
6489
  /* 16569 */ "XVLDX\0"
6490
  /* 16575 */ "G_FRAME_INDEX\0"
6491
  /* 16589 */ "G_SBFX\0"
6492
  /* 16596 */ "G_UBFX\0"
6493
  /* 16603 */ "G_SMULFIX\0"
6494
  /* 16613 */ "G_UMULFIX\0"
6495
  /* 16623 */ "G_SDIVFIX\0"
6496
  /* 16633 */ "G_UDIVFIX\0"
6497
  /* 16643 */ "XVSTX\0"
6498
  /* 16649 */ "G_MEMCPY\0"
6499
  /* 16658 */ "COPY\0"
6500
  /* 16663 */ "PseudoXVBZ\0"
6501
  /* 16674 */ "PseudoVBZ\0"
6502
  /* 16684 */ "BNEZ\0"
6503
  /* 16689 */ "BCNEZ\0"
6504
  /* 16695 */ "MASKNEZ\0"
6505
  /* 16703 */ "G_CTLZ\0"
6506
  /* 16710 */ "PseudoXVBNZ\0"
6507
  /* 16722 */ "PseudoVBNZ\0"
6508
  /* 16733 */ "BEQZ\0"
6509
  /* 16738 */ "BCEQZ\0"
6510
  /* 16744 */ "MASKEQZ\0"
6511
  /* 16752 */ "G_CTTZ\0"
6512
  /* 16759 */ "PseudoTAILIndirect\0"
6513
  /* 16778 */ "PseudoCALLIndirect\0"
6514
};
6515
#ifdef __GNUC__
6516
#pragma GCC diagnostic pop
6517
#endif
6518
6519
extern const unsigned LoongArchInstrNameIndices[] = {
6520
    8329U, 8877U, 9802U, 9201U, 8439U, 8420U, 8448U, 8684U, 
6521
    6313U, 6328U, 6229U, 6355U, 10319U, 6089U, 11988U, 6242U, 
6522
    8325U, 8429U, 5639U, 16658U, 5936U, 11892U, 2576U, 5590U, 
6523
    5627U, 9321U, 8653U, 11808U, 2673U, 9518U, 6434U, 11797U, 
6524
    5992U, 9491U, 9478U, 9882U, 11638U, 11671U, 8569U, 8632U, 
6525
    8605U, 8465U, 9847U, 9275U, 12023U, 12053U, 9052U, 2436U, 
6526
    638U, 8792U, 13914U, 13921U, 8843U, 8850U, 8857U, 8867U, 
6527
    2554U, 10161U, 10124U, 6227U, 8327U, 16575U, 6099U, 8689U, 
6528
    11606U, 10263U, 11929U, 10280U, 10076U, 2217U, 10302U, 11819U, 
6529
    10213U, 11961U, 6157U, 9858U, 2647U, 2191U, 2629U, 11838U, 
6530
    9030U, 9907U, 2337U, 2281U, 2311U, 2322U, 2262U, 2292U, 
6531
    6048U, 6032U, 10349U, 6376U, 6402U, 2452U, 644U, 2560U, 
6532
    2521U, 10166U, 10130U, 16546U, 9178U, 16529U, 9161U, 2403U, 
6533
    621U, 16464U, 9096U, 9352U, 9330U, 5619U, 6475U, 2601U, 
6534
    11625U, 11907U, 2169U, 10379U, 11774U, 10406U, 12037U, 2209U, 
6535
    11763U, 11751U, 11882U, 6426U, 12016U, 6342U, 12046U, 8507U, 
6536
    10043U, 10029U, 8500U, 10036U, 10206U, 8710U, 9407U, 9400U, 
6537
    11616U, 9267U, 5660U, 9251U, 5611U, 9259U, 5652U, 9243U, 
6538
    5603U, 9305U, 9297U, 6494U, 6486U, 11524U, 11514U, 11504U, 
6539
    11494U, 11544U, 11534U, 16603U, 16613U, 11554U, 11567U, 16623U, 
6540
    16633U, 11580U, 11593U, 2361U, 600U, 8734U, 554U, 2255U, 
6541
    13893U, 8822U, 14081U, 8367U, 9562U, 453U, 9U, 6419U, 
6542
    445U, 0U, 9537U, 9569U, 6306U, 12008U, 2181U, 8338U, 
6543
    8352U, 9382U, 9391U, 10237U, 9067U, 10336U, 6166U, 9005U, 
6544
    9015U, 5709U, 5724U, 8962U, 8994U, 13928U, 13954U, 13940U, 
6545
    5668U, 5696U, 5681U, 2442U, 8397U, 9130U, 16498U, 9154U, 
6546
    16522U, 10257U, 2620U, 2610U, 9797U, 11695U, 11727U, 11706U, 
6547
    10091U, 16752U, 6209U, 16703U, 6191U, 9432U, 9374U, 6070U, 
6548
    8553U, 10295U, 9194U, 11938U, 10067U, 11830U, 11856U, 11971U, 
6549
    9834U, 5918U, 2238U, 6127U, 6017U, 2389U, 607U, 8762U, 
6550
    13900U, 8829U, 560U, 11946U, 9546U, 9926U, 9942U, 16649U, 
6551
    5963U, 6139U, 11662U, 9313U, 2368U, 8741U, 2344U, 8717U, 
6552
    16447U, 9079U, 8973U, 8941U, 2420U, 8776U, 2538U, 10146U, 
6553
    10108U, 16481U, 9113U, 16505U, 9137U, 16589U, 16596U, 9226U, 
6554
    9503U, 110U, 132U, 183U, 489U, 345U, 60U, 366U, 
6555
    5563U, 16428U, 326U, 9815U, 2589U, 8513U, 8665U, 541U, 
6556
    16778U, 5847U, 8923U, 228U, 512U, 9985U, 8589U, 8526U, 
6557
    10244U, 5864U, 11869U, 5883U, 8485U, 5809U, 2468U, 5743U, 
6558
    5902U, 5787U, 2505U, 5765U, 5943U, 9959U, 3672U, 15276U, 
6559
    82U, 417U, 273U, 154U, 32U, 388U, 244U, 301U, 
6560
    206U, 11652U, 9972U, 8542U, 528U, 16759U, 5830U, 8905U, 
6561
    9414U, 16722U, 2121U, 5507U, 8239U, 16384U, 16674U, 2062U, 
6562
    5459U, 8191U, 16336U, 1296U, 3627U, 7161U, 15221U, 16710U, 
6563
    2107U, 5493U, 8225U, 16370U, 16663U, 2049U, 5446U, 8178U, 
6564
    16323U, 1754U, 7593U, 1280U, 3611U, 7145U, 15205U, 10192U, 
6565
    10199U, 782U, 2972U, 6834U, 14328U, 3530U, 15124U, 3464U, 
6566
    15066U, 3501U, 3004U, 14369U, 3906U, 15549U, 13697U, 815U, 
6567
    3019U, 6867U, 14375U, 698U, 2772U, 6550U, 14146U, 3099U, 
6568
    14432U, 2784U, 14158U, 1783U, 4611U, 7622U, 15887U, 723U, 
6569
    2844U, 6575U, 14218U, 5416U, 12925U, 16286U, 13868U, 2856U, 
6570
    12510U, 14230U, 13400U, 4076U, 12687U, 15617U, 13715U, 2796U, 
6571
    12497U, 14170U, 13387U, 4496U, 15758U, 2821U, 14195U, 1617U, 
6572
    4132U, 7456U, 15647U, 710U, 2808U, 6562U, 14182U, 4525U, 
6573
    15782U, 2832U, 14206U, 2534U, 8320U, 9025U, 14334U, 14383U, 
6574
    14440U, 6266U, 6149U, 5129U, 16256U, 6286U, 15979U, 15765U, 
6575
    15368U, 15809U, 16308U, 14316U, 15186U, 15495U, 15105U, 14129U, 
6576
    15246U, 15532U, 14251U, 15790U, 4697U, 3208U, 581U, 16738U, 
6577
    16689U, 9578U, 16733U, 5739U, 12943U, 573U, 583U, 5084U, 
6578
    16227U, 8407U, 11702U, 13377U, 5959U, 16684U, 8391U, 4626U, 
6579
    15895U, 3827U, 15442U, 3816U, 15431U, 9426U, 4120U, 15635U, 
6580
    5487U, 16364U, 6369U, 14286U, 14709U, 15045U, 16265U, 14297U, 
6581
    14720U, 15056U, 16276U, 2697U, 10231U, 6394U, 4126U, 15641U, 
6582
    5546U, 16411U, 9787U, 8410U, 5096U, 12918U, 16238U, 13861U, 
6583
    9221U, 2009U, 8061U, 4619U, 11189U, 3012U, 10516U, 4650U, 
6584
    11198U, 3377U, 10746U, 4174U, 11088U, 3168U, 10585U, 4716U, 
6585
    11225U, 3264U, 10655U, 4485U, 11165U, 4208U, 11114U, 3227U, 
6586
    10627U, 4750U, 11251U, 3303U, 10694U, 4094U, 11039U, 3390U, 
6587
    10759U, 4195U, 11101U, 3197U, 10606U, 4737U, 11238U, 3290U, 
6588
    10681U, 4505U, 11178U, 4222U, 11128U, 3241U, 10641U, 4764U, 
6589
    11265U, 3317U, 10708U, 4107U, 11052U, 4055U, 11016U, 2495U, 
6590
    10574U, 3080U, 4661U, 3156U, 5095U, 11344U, 8800U, 14601U, 
6591
    8812U, 15919U, 4689U, 11207U, 3179U, 10596U, 5432U, 11436U, 
6592
    3074U, 10544U, 2880U, 10476U, 3029U, 10525U, 2764U, 10456U, 
6593
    5409U, 11429U, 2737U, 10446U, 4069U, 11030U, 5122U, 11351U, 
6594
    2908U, 10495U, 3940U, 10790U, 3410U, 10770U, 3039U, 10535U, 
6595
    2918U, 10505U, 3331U, 10722U, 4143U, 11065U, 4787U, 11279U, 
6596
    3343U, 10734U, 4807U, 11299U, 2868U, 10464U, 5582U, 11474U, 
6597
    4797U, 11289U, 4706U, 11215U, 3217U, 10617U, 5439U, 11443U, 
6598
    4816U, 11308U, 2899U, 10486U, 3981U, 10958U, 5259U, 11375U, 
6599
    3966U, 10797U, 5140U, 11360U, 3995U, 10970U, 5369U, 11389U, 
6600
    4021U, 10992U, 5395U, 11415U, 4009U, 10982U, 5383U, 11403U, 
6601
    2696U, 10230U, 6393U, 6502U, 8415U, 9792U, 5931U, 593U, 
6602
    893U, 3137U, 6945U, 14479U, 1773U, 4601U, 7612U, 15877U, 
6603
    8705U, 18U, 25U, 10050U, 1822U, 4690U, 7685U, 15948U, 
6604
    924U, 3180U, 6976U, 14730U, 3847U, 15462U, 6083U, 4552U, 
6605
    15828U, 4404U, 15690U, 2037U, 12490U, 5433U, 8166U, 13357U, 
6606
    16302U, 13886U, 849U, 12087U, 3075U, 6901U, 12968U, 14418U, 
6607
    13453U, 4164U, 15656U, 3865U, 15490U, 15076U, 3474U, 3482U, 
6608
    16744U, 16695U, 3131U, 12565U, 14473U, 13461U, 11482U, 9999U, 
6609
    10018U, 11462U, 4435U, 11152U, 461U, 11140U, 6182U, 10181U, 
6610
    14816U, 4410U, 15696U, 475U, 9824U, 10008U, 3433U, 12600U, 
6611
    14809U, 13620U, 14700U, 13592U, 3932U, 15575U, 10063U, 10064U, 
6612
    8334U, 9217U, 8307U, 8287U, 8297U, 8277U, 2484U, 16562U, 
6613
    1383U, 3724U, 7248U, 15328U, 1656U, 4398U, 7495U, 15684U, 
6614
    14799U, 15468U, 3253U, 6451U, 14065U, 6459U, 2953U, 14073U, 
6615
    3448U, 1441U, 3756U, 7280U, 15360U, 1724U, 4536U, 7563U, 
6616
    15802U, 773U, 2963U, 6825U, 14310U, 3853U, 15478U, 2996U, 
6617
    9602U, 14361U, 8383U, 8375U, 6005U, 5979U, 6056U, 6114U, 
6618
    3595U, 15179U, 3864U, 15489U, 11747U, 8347U, 13382U, 8361U, 
6619
    3514U, 15098U, 2748U, 14123U, 3645U, 15239U, 3892U, 15526U, 
6620
    1829U, 4707U, 7692U, 15955U, 939U, 3218U, 6991U, 14745U, 
6621
    3923U, 15566U, 4560U, 15836U, 4568U, 15844U, 2043U, 5440U, 
6622
    8172U, 16317U, 1853U, 4817U, 7716U, 15988U, 2891U, 14245U, 
6623
    8561U, 10056U, 8676U, 6503U, 2690U, 6467U, 10224U, 904U, 
6624
    12103U, 3148U, 12573U, 6956U, 12984U, 14490U, 13469U, 673U, 
6625
    2727U, 6525U, 14112U, 12264U, 12628U, 13031U, 13648U, 14639U, 
6626
    13565U, 16172U, 1104U, 12226U, 1925U, 4337U, 12792U, 4889U, 
6627
    8097U, 13321U, 7900U, 14526U, 13508U, 16123U, 1027U, 12169U, 
6628
    1876U, 4262U, 12735U, 4840U, 8012U, 13264U, 7851U, 842U, 
6629
    3067U, 6894U, 9608U, 14411U, 1196U, 14004U, 13967U, 1676U, 
6630
    12347U, 4447U, 12835U, 7515U, 13114U, 15722U, 13749U, 975U, 
6631
    12122U, 3426U, 12592U, 7027U, 13003U, 14792U, 13612U, 1391U, 
6632
    3732U, 7256U, 15336U, 1685U, 4456U, 7524U, 15731U, 1481U, 
6633
    3796U, 7320U, 15411U, 1979U, 5083U, 7954U, 16226U, 1250U, 
6634
    13975U, 1460U, 3775U, 7299U, 15390U, 1812U, 4679U, 7675U, 
6635
    15938U, 13986U, 13995U, 1610U, 4119U, 7449U, 15634U, 2100U, 
6636
    5486U, 8218U, 16363U, 1990U, 12473U, 5103U, 12917U, 7965U, 
6637
    13226U, 16237U, 13860U, 12374U, 13141U, 13817U, 912U, 6964U, 
6638
    14664U, 12416U, 1129U, 12458U, 13183U, 2017U, 8122U, 13790U, 
6639
    14565U, 12389U, 1053U, 12863U, 4288U, 13156U, 8038U, 12876U, 
6640
    4299U, 1792U, 4637U, 7631U, 15906U, 3011U, 10515U, 4649U, 
6641
    11197U, 3376U, 10745U, 4173U, 11087U, 3167U, 10584U, 4715U, 
6642
    11224U, 3263U, 10654U, 4484U, 11164U, 4207U, 11113U, 3226U, 
6643
    10626U, 4749U, 11250U, 3302U, 10693U, 4093U, 11038U, 3389U, 
6644
    10758U, 4194U, 11100U, 3196U, 10605U, 4736U, 11237U, 3289U, 
6645
    10680U, 4504U, 11177U, 4221U, 11127U, 3240U, 10640U, 4763U, 
6646
    11264U, 3316U, 10707U, 4106U, 11051U, 10551U, 7643U, 10563U, 
6647
    7655U, 10778U, 4660U, 5094U, 11343U, 14552U, 14589U, 8799U, 
6648
    13365U, 8811U, 15918U, 13759U, 2879U, 10475U, 3028U, 10524U, 
6649
    2763U, 10455U, 5408U, 11428U, 2736U, 10445U, 4068U, 11029U, 
6650
    2907U, 10494U, 3939U, 10789U, 3038U, 10534U, 2917U, 10504U, 
6651
    3330U, 10721U, 4142U, 11064U, 4044U, 11005U, 3276U, 10667U, 
6652
    4153U, 11075U, 5535U, 11451U, 4786U, 11278U, 3342U, 10733U, 
6653
    4806U, 11298U, 1351U, 7216U, 1627U, 7466U, 4796U, 11288U, 
6654
    2898U, 10485U, 10857U, 10931U, 10827U, 10901U, 3980U, 5258U, 
6655
    11374U, 10811U, 10885U, 3965U, 5139U, 11359U, 10842U, 10916U, 
6656
    3994U, 5368U, 11388U, 10870U, 10944U, 4934U, 4020U, 11328U, 
6657
    5394U, 11414U, 4921U, 4008U, 11315U, 5382U, 11402U, 13846U, 
6658
    14689U, 12445U, 1154U, 12903U, 4375U, 13212U, 8147U, 13832U, 
6659
    14677U, 12431U, 1142U, 12889U, 4363U, 13198U, 8135U, 991U, 
6660
    3456U, 7043U, 14837U, 1583U, 3956U, 7422U, 15590U, 1761U, 
6661
    4589U, 7600U, 15865U, 2491U, 8315U, 1528U, 3879U, 7367U, 
6662
    15513U, 16570U, 14625U, 13550U, 16155U, 1090U, 12211U, 1908U, 
6663
    4323U, 12777U, 4872U, 8083U, 13306U, 7883U, 14512U, 13493U, 
6664
    16106U, 1013U, 12154U, 1859U, 4248U, 12720U, 4823U, 7998U, 
6665
    13249U, 7834U, 824U, 3049U, 6876U, 14393U, 1493U, 12304U, 
6666
    3808U, 12668U, 7332U, 13071U, 15423U, 13688U, 2030U, 12482U, 
6667
    5425U, 12935U, 8159U, 13349U, 16295U, 13878U, 1342U, 12284U, 
6668
    3694U, 12648U, 7207U, 13051U, 15298U, 13668U, 1602U, 12324U, 
6669
    4085U, 12697U, 7441U, 13091U, 15626U, 13725U, 886U, 12094U, 
6670
    3130U, 12564U, 6938U, 12975U, 14472U, 13460U, 2075U, 2159U, 
6671
    5553U, 8267U, 16418U, 2135U, 745U, 2928U, 6597U, 14261U, 
6672
    983U, 12131U, 3441U, 12609U, 7035U, 13012U, 14829U, 13629U, 
6673
    14652U, 13579U, 16188U, 1117U, 12240U, 1941U, 4350U, 12806U, 
6674
    4905U, 8110U, 13335U, 7916U, 14539U, 13522U, 16139U, 1040U, 
6675
    12183U, 1892U, 4275U, 12749U, 4856U, 8025U, 13278U, 7867U, 
6676
    1575U, 3948U, 7414U, 15582U, 967U, 3418U, 7019U, 14784U, 
6677
    1413U, 14021U, 1422U, 14013U, 14029U, 1957U, 5061U, 7932U, 
6678
    16204U, 864U, 3108U, 6916U, 14450U, 1845U, 4777U, 7708U, 
6679
    15971U, 15288U, 1968U, 5072U, 7943U, 16215U, 875U, 3119U, 
6680
    6927U, 14461U, 1662U, 12332U, 4422U, 12820U, 7501U, 13099U, 
6681
    15708U, 13734U, 1741U, 4575U, 7580U, 15851U, 1228U, 3561U, 
6682
    7105U, 15155U, 947U, 3365U, 6999U, 14764U, 1450U, 3765U, 
6683
    7289U, 15380U, 1732U, 4544U, 7571U, 15820U, 833U, 12078U, 
6684
    3058U, 12554U, 6885U, 12959U, 14402U, 13444U, 1804U, 12357U, 
6685
    4671U, 12845U, 7667U, 13124U, 15930U, 13772U, 1362U, 3703U, 
6686
    7227U, 15307U, 1637U, 4186U, 7476U, 15665U, 2086U, 5472U, 
6687
    8204U, 16349U, 2145U, 5521U, 8253U, 16398U, 14055U, 14044U, 
6688
    1166U, 3491U, 7052U, 15085U, 958U, 3402U, 7010U, 14775U, 
6689
    1998U, 5111U, 7973U, 16245U, 1205U, 12274U, 3538U, 12638U, 
6690
    7082U, 13041U, 15132U, 13658U, 932U, 12113U, 3188U, 12583U, 
6691
    6984U, 12994U, 14738U, 13603U, 1272U, 3603U, 7137U, 15197U, 
6692
    13803U, 14576U, 12402U, 1064U, 13169U, 8049U, 1520U, 3871U, 
6693
    7359U, 15505U, 1472U, 12294U, 3787U, 12658U, 7311U, 13061U, 
6694
    15402U, 13678U, 1837U, 12366U, 4728U, 12854U, 7700U, 13133U, 
6695
    15963U, 13781U, 1187U, 3522U, 7073U, 15116U, 6636U, 9629U, 
6696
    14859U, 5167U, 6739U, 14962U, 5284U, 1371U, 3712U, 7236U, 
6697
    15316U, 6687U, 9680U, 14910U, 5218U, 6786U, 15009U, 5331U, 
6698
    1645U, 4387U, 7484U, 15673U, 691U, 2755U, 6543U, 14139U, 
6699
    1322U, 3653U, 7187U, 15257U, 6661U, 9654U, 14884U, 5192U, 
6700
    6762U, 14985U, 5307U, 1403U, 3744U, 7268U, 15348U, 6714U, 
6701
    9707U, 14937U, 5245U, 6811U, 15034U, 5356U, 1696U, 4467U, 
6702
    7535U, 15742U, 1548U, 3899U, 7387U, 15542U, 7722U, 6623U, 
6703
    9730U, 9616U, 15994U, 14846U, 4949U, 5154U, 7780U, 6727U, 
6704
    16052U, 14950U, 5007U, 5272U, 7750U, 6673U, 9758U, 9666U, 
6705
    16022U, 14896U, 4977U, 5204U, 7806U, 6773U, 16078U, 14996U, 
6706
    5033U, 5318U, 7736U, 6648U, 9744U, 9641U, 16008U, 14871U, 
6707
    4963U, 5179U, 7793U, 6750U, 16065U, 14973U, 5020U, 5295U, 
6708
    7765U, 6700U, 9773U, 9693U, 16037U, 14923U, 4992U, 5231U, 
6709
    7820U, 6798U, 16092U, 15021U, 5047U, 5343U, 754U, 12068U, 
6710
    2937U, 12534U, 6606U, 12949U, 14270U, 13424U, 12004U, 1592U, 
6711
    4034U, 7431U, 15599U, 16644U, 12254U, 12618U, 13021U, 13638U, 
6712
    14612U, 13536U, 1077U, 12197U, 4310U, 12763U, 8070U, 13292U, 
6713
    14499U, 13479U, 1000U, 12140U, 4235U, 12706U, 7985U, 13235U, 
6714
    763U, 2946U, 6615U, 9595U, 14279U, 1430U, 14036U, 779U, 
6715
    2969U, 6831U, 14325U, 806U, 3001U, 12543U, 6858U, 14366U, 
6716
    13433U, 854U, 3090U, 6906U, 14423U, 8887U, 9440U, 788U, 
6717
    2978U, 6840U, 14343U, 9450U, 797U, 2987U, 6849U, 14352U, 
6718
    6256U, 9460U, 6276U, 9469U, 1565U, 12313U, 3929U, 12677U, 
6719
    7404U, 13080U, 15572U, 13705U, 1704U, 4475U, 7543U, 15750U, 
6720
    1239U, 3572U, 7116U, 15166U, 1501U, 3838U, 7340U, 15453U, 
6721
    1380U, 3721U, 7245U, 15325U, 1653U, 4395U, 7492U, 15681U, 
6722
    1330U, 3661U, 7195U, 15265U, 1555U, 3913U, 7394U, 15556U, 
6723
    1438U, 3753U, 7277U, 15357U, 1721U, 4533U, 7560U, 15799U, 
6724
    770U, 2960U, 6822U, 14307U, 6296U, 8896U, 1261U, 3592U, 
6725
    7126U, 15176U, 1510U, 3861U, 7349U, 15486U, 1176U, 3511U, 
6726
    7062U, 15095U, 681U, 2745U, 6533U, 14120U, 1311U, 3642U, 
6727
    7176U, 15236U, 1538U, 3889U, 7377U, 15523U, 735U, 2888U, 
6728
    12523U, 6587U, 14242U, 13413U, 1712U, 4516U, 7551U, 15773U, 
6729
    10120U, 8333U, 903U, 12102U, 3147U, 12572U, 6955U, 12983U, 
6730
    14489U, 13468U, 672U, 2726U, 6524U, 14111U, 12263U, 12627U, 
6731
    13030U, 13647U, 14638U, 13564U, 16171U, 1103U, 12225U, 1924U, 
6732
    4336U, 12791U, 4888U, 8096U, 13320U, 7899U, 14525U, 13507U, 
6733
    16122U, 1026U, 12168U, 1875U, 4261U, 12734U, 4839U, 8011U, 
6734
    13263U, 7850U, 841U, 3066U, 6893U, 9607U, 14410U, 1195U, 
6735
    14003U, 13966U, 1675U, 12346U, 4446U, 12834U, 7514U, 13113U, 
6736
    15721U, 13748U, 974U, 12121U, 3425U, 12591U, 7026U, 13002U, 
6737
    14791U, 13611U, 1390U, 3731U, 7255U, 15335U, 1684U, 4455U, 
6738
    7523U, 15730U, 1480U, 3795U, 7319U, 15410U, 1978U, 5082U, 
6739
    7953U, 16225U, 1249U, 13974U, 1459U, 3774U, 7298U, 15389U, 
6740
    1811U, 4678U, 7674U, 15937U, 13985U, 13994U, 1609U, 4118U, 
6741
    7448U, 15633U, 2099U, 5485U, 8217U, 16362U, 1989U, 12472U, 
6742
    5102U, 12916U, 7964U, 13225U, 16236U, 13859U, 13789U, 14564U, 
6743
    12388U, 1052U, 12862U, 4287U, 13155U, 8037U, 12875U, 4298U, 
6744
    1791U, 4636U, 7630U, 15905U, 3010U, 10514U, 4648U, 11196U, 
6745
    3375U, 10744U, 4172U, 11086U, 3166U, 10583U, 4714U, 11223U, 
6746
    3262U, 10653U, 4483U, 11163U, 4206U, 11112U, 3225U, 10625U, 
6747
    4748U, 11249U, 3301U, 10692U, 4092U, 11037U, 3388U, 10757U, 
6748
    4193U, 11099U, 3195U, 10604U, 4735U, 11236U, 3288U, 10679U, 
6749
    4503U, 11176U, 4220U, 11126U, 3239U, 10639U, 4762U, 11263U, 
6750
    3315U, 10706U, 4105U, 11050U, 10550U, 7642U, 10562U, 7654U, 
6751
    10777U, 4659U, 5093U, 11342U, 14551U, 14588U, 8798U, 13364U, 
6752
    8810U, 15917U, 13758U, 2878U, 10474U, 3027U, 10523U, 2762U, 
6753
    10454U, 5407U, 11427U, 2735U, 10444U, 4067U, 11028U, 2906U, 
6754
    10493U, 3938U, 10788U, 3037U, 10533U, 2916U, 10503U, 3329U, 
6755
    10720U, 4141U, 11063U, 4043U, 11004U, 3275U, 10666U, 4152U, 
6756
    11074U, 5534U, 11450U, 4785U, 11277U, 3341U, 10732U, 4805U, 
6757
    11297U, 1350U, 7215U, 1626U, 7465U, 4795U, 11287U, 2897U, 
6758
    10484U, 10856U, 10930U, 10826U, 10900U, 3979U, 5257U, 11373U, 
6759
    10810U, 10884U, 3964U, 5138U, 11358U, 10841U, 10915U, 3993U, 
6760
    5367U, 11387U, 10869U, 10943U, 4933U, 4019U, 11327U, 5393U, 
6761
    11413U, 4920U, 4007U, 11314U, 5381U, 11401U, 13845U, 14688U, 
6762
    12444U, 1153U, 12902U, 4374U, 13211U, 8146U, 3582U, 13831U, 
6763
    14676U, 12430U, 1141U, 12888U, 4362U, 13197U, 8134U, 990U, 
6764
    3455U, 7042U, 14836U, 1582U, 3955U, 7421U, 15589U, 4588U, 
6765
    15864U, 2715U, 14100U, 2490U, 8314U, 1527U, 3878U, 7366U, 
6766
    15512U, 16569U, 14624U, 13549U, 16154U, 1089U, 12210U, 1907U, 
6767
    4322U, 12776U, 4871U, 8082U, 13305U, 7882U, 14511U, 13492U, 
6768
    16105U, 1012U, 12153U, 1858U, 4247U, 12719U, 4822U, 7997U, 
6769
    13248U, 7833U, 823U, 3048U, 6875U, 14392U, 1492U, 12303U, 
6770
    3807U, 12667U, 7331U, 13070U, 15422U, 13687U, 2029U, 12481U, 
6771
    5424U, 12934U, 8158U, 13348U, 16294U, 13877U, 1341U, 12283U, 
6772
    3693U, 12647U, 7206U, 13050U, 15297U, 13667U, 1601U, 12323U, 
6773
    4084U, 12696U, 7440U, 13090U, 15625U, 13724U, 885U, 12093U, 
6774
    3129U, 12563U, 6937U, 12974U, 14471U, 13459U, 2074U, 2158U, 
6775
    5552U, 8266U, 16417U, 2134U, 744U, 2927U, 6596U, 14260U, 
6776
    982U, 12130U, 3440U, 12608U, 7034U, 13011U, 14828U, 13628U, 
6777
    14651U, 13578U, 16187U, 1116U, 12239U, 1940U, 4349U, 12805U, 
6778
    4904U, 8109U, 13334U, 7915U, 14538U, 13521U, 16138U, 1039U, 
6779
    12182U, 1891U, 4274U, 12748U, 4855U, 8024U, 13277U, 7866U, 
6780
    1574U, 3947U, 7413U, 15581U, 966U, 3417U, 7018U, 14783U, 
6781
    1412U, 14020U, 1421U, 14012U, 14028U, 1956U, 5060U, 7931U, 
6782
    16203U, 863U, 3107U, 6915U, 14449U, 1844U, 4776U, 7707U, 
6783
    15970U, 3683U, 9719U, 15287U, 15608U, 1967U, 5071U, 7942U, 
6784
    16214U, 874U, 3118U, 6926U, 14460U, 4421U, 12819U, 15707U, 
6785
    13733U, 3353U, 14752U, 1213U, 3546U, 7090U, 15140U, 1740U, 
6786
    4574U, 7579U, 15850U, 660U, 2703U, 6512U, 9582U, 14088U, 
6787
    946U, 3364U, 6998U, 14763U, 1449U, 3764U, 7288U, 15379U, 
6788
    1731U, 4543U, 7570U, 15819U, 832U, 12077U, 3057U, 12553U, 
6789
    6884U, 12958U, 14401U, 13443U, 1803U, 12356U, 4670U, 12844U, 
6790
    7666U, 13123U, 15929U, 13771U, 1361U, 3702U, 7226U, 15306U, 
6791
    1636U, 4185U, 7475U, 15664U, 2085U, 5471U, 8203U, 16348U, 
6792
    2144U, 5520U, 8252U, 16397U, 14054U, 14043U, 1165U, 3490U, 
6793
    7051U, 15084U, 957U, 3401U, 7009U, 14774U, 1997U, 5110U, 
6794
    7972U, 16244U, 1204U, 12273U, 3537U, 12637U, 7081U, 13040U, 
6795
    15131U, 13657U, 931U, 12112U, 3187U, 12582U, 6983U, 12993U, 
6796
    14737U, 13602U, 1271U, 3602U, 7136U, 15196U, 13802U, 14575U, 
6797
    12401U, 1063U, 13168U, 8048U, 1519U, 3870U, 7358U, 15504U, 
6798
    1471U, 12293U, 3786U, 12657U, 7310U, 13060U, 15401U, 13677U, 
6799
    1836U, 12365U, 4727U, 12853U, 7699U, 13132U, 15962U, 13780U, 
6800
    1186U, 3521U, 7072U, 15115U, 6635U, 9628U, 14858U, 5166U, 
6801
    6738U, 14961U, 5283U, 1370U, 3711U, 7235U, 15315U, 6686U, 
6802
    9679U, 14909U, 5217U, 6785U, 15008U, 5330U, 1644U, 4386U, 
6803
    7483U, 15672U, 690U, 2754U, 6542U, 14138U, 1321U, 3652U, 
6804
    7186U, 15256U, 6660U, 9653U, 14883U, 5191U, 6761U, 14984U, 
6805
    5306U, 1402U, 3743U, 7267U, 15347U, 6713U, 9706U, 14936U, 
6806
    5244U, 6810U, 15033U, 5355U, 1695U, 4466U, 7534U, 15741U, 
6807
    1547U, 3898U, 7386U, 15541U, 7721U, 6622U, 9729U, 9615U, 
6808
    15993U, 14845U, 4948U, 5153U, 7779U, 6726U, 16051U, 14949U, 
6809
    5006U, 5271U, 7749U, 6672U, 9757U, 9665U, 16021U, 14895U, 
6810
    4976U, 5203U, 7805U, 6772U, 16077U, 14995U, 5032U, 5317U, 
6811
    7735U, 6647U, 9743U, 9640U, 16007U, 14870U, 4962U, 5178U, 
6812
    7792U, 6749U, 16064U, 14972U, 5019U, 5294U, 7764U, 6699U, 
6813
    9772U, 9692U, 16036U, 14922U, 4991U, 5230U, 7819U, 6797U, 
6814
    16091U, 15020U, 5046U, 5342U, 753U, 12067U, 2936U, 12533U, 
6815
    6605U, 12948U, 14269U, 13423U, 12003U, 1591U, 4033U, 7430U, 
6816
    15598U, 16643U, 12253U, 12617U, 13020U, 13637U, 14611U, 13535U, 
6817
    1076U, 12196U, 4309U, 12762U, 8069U, 13291U, 14498U, 13478U, 
6818
    999U, 12139U, 4234U, 12705U, 7984U, 13234U, 762U, 2945U, 
6819
    6614U, 9594U, 14278U, 1429U, 14035U, 
6820
};
6821
6822
0
static inline void InitLoongArchMCInstrInfo(MCInstrInfo *II) {
6823
0
  II->InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2397);
6824
0
}
6825
6826
} // end namespace llvm
6827
#endif // GET_INSTRINFO_MC_DESC
6828
6829
#ifdef GET_INSTRINFO_HEADER
6830
#undef GET_INSTRINFO_HEADER
6831
namespace llvm {
6832
struct LoongArchGenInstrInfo : public TargetInstrInfo {
6833
  explicit LoongArchGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
6834
  ~LoongArchGenInstrInfo() override = default;
6835
6836
};
6837
} // end namespace llvm
6838
#endif // GET_INSTRINFO_HEADER
6839
6840
#ifdef GET_INSTRINFO_HELPER_DECLS
6841
#undef GET_INSTRINFO_HELPER_DECLS
6842
6843
6844
#endif // GET_INSTRINFO_HELPER_DECLS
6845
6846
#ifdef GET_INSTRINFO_HELPERS
6847
#undef GET_INSTRINFO_HELPERS
6848
6849
#endif // GET_INSTRINFO_HELPERS
6850
6851
#ifdef GET_INSTRINFO_CTOR_DTOR
6852
#undef GET_INSTRINFO_CTOR_DTOR
6853
namespace llvm {
6854
extern const LoongArchInstrTable LoongArchDescs;
6855
extern const unsigned LoongArchInstrNameIndices[];
6856
extern const char LoongArchInstrNameData[];
6857
LoongArchGenInstrInfo::LoongArchGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
6858
0
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
6859
0
  InitMCInstrInfo(LoongArchDescs.Insts, LoongArchInstrNameIndices, LoongArchInstrNameData, nullptr, nullptr, 2397);
6860
0
}
6861
} // end namespace llvm
6862
#endif // GET_INSTRINFO_CTOR_DTOR
6863
6864
#ifdef GET_INSTRINFO_OPERAND_ENUM
6865
#undef GET_INSTRINFO_OPERAND_ENUM
6866
namespace llvm {
6867
namespace LoongArch {
6868
namespace OpName {
6869
enum {
6870
  OPERAND_LAST
6871
};
6872
} // end namespace OpName
6873
} // end namespace LoongArch
6874
} // end namespace llvm
6875
#endif //GET_INSTRINFO_OPERAND_ENUM
6876
6877
#ifdef GET_INSTRINFO_NAMED_OPS
6878
#undef GET_INSTRINFO_NAMED_OPS
6879
namespace llvm {
6880
namespace LoongArch {
6881
LLVM_READONLY
6882
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
6883
  return -1;
6884
}
6885
} // end namespace LoongArch
6886
} // end namespace llvm
6887
#endif //GET_INSTRINFO_NAMED_OPS
6888
6889
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
6890
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
6891
namespace llvm {
6892
namespace LoongArch {
6893
namespace OpTypes {
6894
enum OperandType {
6895
  bare_symbol = 0,
6896
  f32imm = 1,
6897
  f64imm = 2,
6898
  grlenimm = 3,
6899
  i1imm = 4,
6900
  i8imm = 5,
6901
  i16imm = 6,
6902
  i32imm = 7,
6903
  i64imm = 8,
6904
  imm32 = 9,
6905
  ptype0 = 10,
6906
  ptype1 = 11,
6907
  ptype2 = 12,
6908
  ptype3 = 13,
6909
  ptype4 = 14,
6910
  ptype5 = 15,
6911
  simm5 = 16,
6912
  simm8 = 17,
6913
  simm8_lsl1 = 18,
6914
  simm8_lsl2 = 19,
6915
  simm8_lsl3 = 20,
6916
  simm9_lsl3 = 21,
6917
  simm10 = 22,
6918
  simm10_lsl2 = 23,
6919
  simm11_lsl1 = 24,
6920
  simm12 = 25,
6921
  simm12_addlike = 26,
6922
  simm12_lu52id = 27,
6923
  simm13 = 28,
6924
  simm14_lsl2 = 29,
6925
  simm16 = 30,
6926
  simm16_lsl2 = 31,
6927
  simm16_lsl2_br = 32,
6928
  simm16_lsl16 = 33,
6929
  simm20 = 34,
6930
  simm20_lu12iw = 35,
6931
  simm20_lu32id = 36,
6932
  simm20_pcaddu18i = 37,
6933
  simm20_pcalau12i = 38,
6934
  simm21_lsl2 = 39,
6935
  simm26_b = 40,
6936
  simm26_symbol = 41,
6937
  simm32_hi16_lo12 = 42,
6938
  type0 = 43,
6939
  type1 = 44,
6940
  type2 = 45,
6941
  type3 = 46,
6942
  type4 = 47,
6943
  type5 = 48,
6944
  uimm1 = 49,
6945
  uimm2 = 50,
6946
  uimm2_plus1 = 51,
6947
  uimm3 = 52,
6948
  uimm4 = 53,
6949
  uimm5 = 54,
6950
  uimm6 = 55,
6951
  uimm7 = 56,
6952
  uimm8 = 57,
6953
  uimm12 = 58,
6954
  uimm12_ori = 59,
6955
  uimm14 = 60,
6956
  uimm15 = 61,
6957
  untyped_imm_0 = 62,
6958
  GPRMemAtomic = 63,
6959
  CFR = 64,
6960
  FCSR = 65,
6961
  FPR32 = 66,
6962
  FPR64 = 67,
6963
  GPR = 68,
6964
  GPRT = 69,
6965
  LASX256 = 70,
6966
  LSX128 = 71,
6967
  SCR = 72,
6968
  OPERAND_TYPE_LIST_END
6969
};
6970
} // end namespace OpTypes
6971
} // end namespace LoongArch
6972
} // end namespace llvm
6973
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
6974
6975
#ifdef GET_INSTRINFO_OPERAND_TYPE
6976
#undef GET_INSTRINFO_OPERAND_TYPE
6977
namespace llvm {
6978
namespace LoongArch {
6979
LLVM_READONLY
6980
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
6981
  static const uint16_t Offsets[] = {
6982
    /* PHI */
6983
    0,
6984
    /* INLINEASM */
6985
    1,
6986
    /* INLINEASM_BR */
6987
    1,
6988
    /* CFI_INSTRUCTION */
6989
    1,
6990
    /* EH_LABEL */
6991
    2,
6992
    /* GC_LABEL */
6993
    3,
6994
    /* ANNOTATION_LABEL */
6995
    4,
6996
    /* KILL */
6997
    5,
6998
    /* EXTRACT_SUBREG */
6999
    5,
7000
    /* INSERT_SUBREG */
7001
    8,
7002
    /* IMPLICIT_DEF */
7003
    12,
7004
    /* SUBREG_TO_REG */
7005
    13,
7006
    /* COPY_TO_REGCLASS */
7007
    17,
7008
    /* DBG_VALUE */
7009
    20,
7010
    /* DBG_VALUE_LIST */
7011
    20,
7012
    /* DBG_INSTR_REF */
7013
    20,
7014
    /* DBG_PHI */
7015
    20,
7016
    /* DBG_LABEL */
7017
    20,
7018
    /* REG_SEQUENCE */
7019
    21,
7020
    /* COPY */
7021
    23,
7022
    /* BUNDLE */
7023
    25,
7024
    /* LIFETIME_START */
7025
    25,
7026
    /* LIFETIME_END */
7027
    26,
7028
    /* PSEUDO_PROBE */
7029
    27,
7030
    /* ARITH_FENCE */
7031
    31,
7032
    /* STACKMAP */
7033
    33,
7034
    /* FENTRY_CALL */
7035
    35,
7036
    /* PATCHPOINT */
7037
    35,
7038
    /* LOAD_STACK_GUARD */
7039
    41,
7040
    /* PREALLOCATED_SETUP */
7041
    42,
7042
    /* PREALLOCATED_ARG */
7043
    43,
7044
    /* STATEPOINT */
7045
    46,
7046
    /* LOCAL_ESCAPE */
7047
    46,
7048
    /* FAULTING_OP */
7049
    48,
7050
    /* PATCHABLE_OP */
7051
    49,
7052
    /* PATCHABLE_FUNCTION_ENTER */
7053
    49,
7054
    /* PATCHABLE_RET */
7055
    49,
7056
    /* PATCHABLE_FUNCTION_EXIT */
7057
    49,
7058
    /* PATCHABLE_TAIL_CALL */
7059
    49,
7060
    /* PATCHABLE_EVENT_CALL */
7061
    49,
7062
    /* PATCHABLE_TYPED_EVENT_CALL */
7063
    51,
7064
    /* ICALL_BRANCH_FUNNEL */
7065
    54,
7066
    /* MEMBARRIER */
7067
    54,
7068
    /* JUMP_TABLE_DEBUG_INFO */
7069
    54,
7070
    /* G_ASSERT_SEXT */
7071
    55,
7072
    /* G_ASSERT_ZEXT */
7073
    58,
7074
    /* G_ASSERT_ALIGN */
7075
    61,
7076
    /* G_ADD */
7077
    64,
7078
    /* G_SUB */
7079
    67,
7080
    /* G_MUL */
7081
    70,
7082
    /* G_SDIV */
7083
    73,
7084
    /* G_UDIV */
7085
    76,
7086
    /* G_SREM */
7087
    79,
7088
    /* G_UREM */
7089
    82,
7090
    /* G_SDIVREM */
7091
    85,
7092
    /* G_UDIVREM */
7093
    89,
7094
    /* G_AND */
7095
    93,
7096
    /* G_OR */
7097
    96,
7098
    /* G_XOR */
7099
    99,
7100
    /* G_IMPLICIT_DEF */
7101
    102,
7102
    /* G_PHI */
7103
    103,
7104
    /* G_FRAME_INDEX */
7105
    104,
7106
    /* G_GLOBAL_VALUE */
7107
    106,
7108
    /* G_CONSTANT_POOL */
7109
    108,
7110
    /* G_EXTRACT */
7111
    110,
7112
    /* G_UNMERGE_VALUES */
7113
    113,
7114
    /* G_INSERT */
7115
    115,
7116
    /* G_MERGE_VALUES */
7117
    119,
7118
    /* G_BUILD_VECTOR */
7119
    121,
7120
    /* G_BUILD_VECTOR_TRUNC */
7121
    123,
7122
    /* G_CONCAT_VECTORS */
7123
    125,
7124
    /* G_PTRTOINT */
7125
    127,
7126
    /* G_INTTOPTR */
7127
    129,
7128
    /* G_BITCAST */
7129
    131,
7130
    /* G_FREEZE */
7131
    133,
7132
    /* G_CONSTANT_FOLD_BARRIER */
7133
    135,
7134
    /* G_INTRINSIC_FPTRUNC_ROUND */
7135
    137,
7136
    /* G_INTRINSIC_TRUNC */
7137
    140,
7138
    /* G_INTRINSIC_ROUND */
7139
    142,
7140
    /* G_INTRINSIC_LRINT */
7141
    144,
7142
    /* G_INTRINSIC_ROUNDEVEN */
7143
    146,
7144
    /* G_READCYCLECOUNTER */
7145
    148,
7146
    /* G_LOAD */
7147
    149,
7148
    /* G_SEXTLOAD */
7149
    151,
7150
    /* G_ZEXTLOAD */
7151
    153,
7152
    /* G_INDEXED_LOAD */
7153
    155,
7154
    /* G_INDEXED_SEXTLOAD */
7155
    160,
7156
    /* G_INDEXED_ZEXTLOAD */
7157
    165,
7158
    /* G_STORE */
7159
    170,
7160
    /* G_INDEXED_STORE */
7161
    172,
7162
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
7163
    177,
7164
    /* G_ATOMIC_CMPXCHG */
7165
    182,
7166
    /* G_ATOMICRMW_XCHG */
7167
    186,
7168
    /* G_ATOMICRMW_ADD */
7169
    189,
7170
    /* G_ATOMICRMW_SUB */
7171
    192,
7172
    /* G_ATOMICRMW_AND */
7173
    195,
7174
    /* G_ATOMICRMW_NAND */
7175
    198,
7176
    /* G_ATOMICRMW_OR */
7177
    201,
7178
    /* G_ATOMICRMW_XOR */
7179
    204,
7180
    /* G_ATOMICRMW_MAX */
7181
    207,
7182
    /* G_ATOMICRMW_MIN */
7183
    210,
7184
    /* G_ATOMICRMW_UMAX */
7185
    213,
7186
    /* G_ATOMICRMW_UMIN */
7187
    216,
7188
    /* G_ATOMICRMW_FADD */
7189
    219,
7190
    /* G_ATOMICRMW_FSUB */
7191
    222,
7192
    /* G_ATOMICRMW_FMAX */
7193
    225,
7194
    /* G_ATOMICRMW_FMIN */
7195
    228,
7196
    /* G_ATOMICRMW_UINC_WRAP */
7197
    231,
7198
    /* G_ATOMICRMW_UDEC_WRAP */
7199
    234,
7200
    /* G_FENCE */
7201
    237,
7202
    /* G_PREFETCH */
7203
    239,
7204
    /* G_BRCOND */
7205
    243,
7206
    /* G_BRINDIRECT */
7207
    245,
7208
    /* G_INVOKE_REGION_START */
7209
    246,
7210
    /* G_INTRINSIC */
7211
    246,
7212
    /* G_INTRINSIC_W_SIDE_EFFECTS */
7213
    247,
7214
    /* G_INTRINSIC_CONVERGENT */
7215
    248,
7216
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
7217
    249,
7218
    /* G_ANYEXT */
7219
    250,
7220
    /* G_TRUNC */
7221
    252,
7222
    /* G_CONSTANT */
7223
    254,
7224
    /* G_FCONSTANT */
7225
    256,
7226
    /* G_VASTART */
7227
    258,
7228
    /* G_VAARG */
7229
    259,
7230
    /* G_SEXT */
7231
    262,
7232
    /* G_SEXT_INREG */
7233
    264,
7234
    /* G_ZEXT */
7235
    267,
7236
    /* G_SHL */
7237
    269,
7238
    /* G_LSHR */
7239
    272,
7240
    /* G_ASHR */
7241
    275,
7242
    /* G_FSHL */
7243
    278,
7244
    /* G_FSHR */
7245
    282,
7246
    /* G_ROTR */
7247
    286,
7248
    /* G_ROTL */
7249
    289,
7250
    /* G_ICMP */
7251
    292,
7252
    /* G_FCMP */
7253
    296,
7254
    /* G_SELECT */
7255
    300,
7256
    /* G_UADDO */
7257
    304,
7258
    /* G_UADDE */
7259
    308,
7260
    /* G_USUBO */
7261
    313,
7262
    /* G_USUBE */
7263
    317,
7264
    /* G_SADDO */
7265
    322,
7266
    /* G_SADDE */
7267
    326,
7268
    /* G_SSUBO */
7269
    331,
7270
    /* G_SSUBE */
7271
    335,
7272
    /* G_UMULO */
7273
    340,
7274
    /* G_SMULO */
7275
    344,
7276
    /* G_UMULH */
7277
    348,
7278
    /* G_SMULH */
7279
    351,
7280
    /* G_UADDSAT */
7281
    354,
7282
    /* G_SADDSAT */
7283
    357,
7284
    /* G_USUBSAT */
7285
    360,
7286
    /* G_SSUBSAT */
7287
    363,
7288
    /* G_USHLSAT */
7289
    366,
7290
    /* G_SSHLSAT */
7291
    369,
7292
    /* G_SMULFIX */
7293
    372,
7294
    /* G_UMULFIX */
7295
    376,
7296
    /* G_SMULFIXSAT */
7297
    380,
7298
    /* G_UMULFIXSAT */
7299
    384,
7300
    /* G_SDIVFIX */
7301
    388,
7302
    /* G_UDIVFIX */
7303
    392,
7304
    /* G_SDIVFIXSAT */
7305
    396,
7306
    /* G_UDIVFIXSAT */
7307
    400,
7308
    /* G_FADD */
7309
    404,
7310
    /* G_FSUB */
7311
    407,
7312
    /* G_FMUL */
7313
    410,
7314
    /* G_FMA */
7315
    413,
7316
    /* G_FMAD */
7317
    417,
7318
    /* G_FDIV */
7319
    421,
7320
    /* G_FREM */
7321
    424,
7322
    /* G_FPOW */
7323
    427,
7324
    /* G_FPOWI */
7325
    430,
7326
    /* G_FEXP */
7327
    433,
7328
    /* G_FEXP2 */
7329
    435,
7330
    /* G_FEXP10 */
7331
    437,
7332
    /* G_FLOG */
7333
    439,
7334
    /* G_FLOG2 */
7335
    441,
7336
    /* G_FLOG10 */
7337
    443,
7338
    /* G_FLDEXP */
7339
    445,
7340
    /* G_FFREXP */
7341
    448,
7342
    /* G_FNEG */
7343
    451,
7344
    /* G_FPEXT */
7345
    453,
7346
    /* G_FPTRUNC */
7347
    455,
7348
    /* G_FPTOSI */
7349
    457,
7350
    /* G_FPTOUI */
7351
    459,
7352
    /* G_SITOFP */
7353
    461,
7354
    /* G_UITOFP */
7355
    463,
7356
    /* G_FABS */
7357
    465,
7358
    /* G_FCOPYSIGN */
7359
    467,
7360
    /* G_IS_FPCLASS */
7361
    470,
7362
    /* G_FCANONICALIZE */
7363
    473,
7364
    /* G_FMINNUM */
7365
    475,
7366
    /* G_FMAXNUM */
7367
    478,
7368
    /* G_FMINNUM_IEEE */
7369
    481,
7370
    /* G_FMAXNUM_IEEE */
7371
    484,
7372
    /* G_FMINIMUM */
7373
    487,
7374
    /* G_FMAXIMUM */
7375
    490,
7376
    /* G_GET_FPENV */
7377
    493,
7378
    /* G_SET_FPENV */
7379
    494,
7380
    /* G_RESET_FPENV */
7381
    495,
7382
    /* G_GET_FPMODE */
7383
    495,
7384
    /* G_SET_FPMODE */
7385
    496,
7386
    /* G_RESET_FPMODE */
7387
    497,
7388
    /* G_PTR_ADD */
7389
    497,
7390
    /* G_PTRMASK */
7391
    500,
7392
    /* G_SMIN */
7393
    503,
7394
    /* G_SMAX */
7395
    506,
7396
    /* G_UMIN */
7397
    509,
7398
    /* G_UMAX */
7399
    512,
7400
    /* G_ABS */
7401
    515,
7402
    /* G_LROUND */
7403
    517,
7404
    /* G_LLROUND */
7405
    519,
7406
    /* G_BR */
7407
    521,
7408
    /* G_BRJT */
7409
    522,
7410
    /* G_INSERT_VECTOR_ELT */
7411
    525,
7412
    /* G_EXTRACT_VECTOR_ELT */
7413
    529,
7414
    /* G_SHUFFLE_VECTOR */
7415
    532,
7416
    /* G_CTTZ */
7417
    536,
7418
    /* G_CTTZ_ZERO_UNDEF */
7419
    538,
7420
    /* G_CTLZ */
7421
    540,
7422
    /* G_CTLZ_ZERO_UNDEF */
7423
    542,
7424
    /* G_CTPOP */
7425
    544,
7426
    /* G_BSWAP */
7427
    546,
7428
    /* G_BITREVERSE */
7429
    548,
7430
    /* G_FCEIL */
7431
    550,
7432
    /* G_FCOS */
7433
    552,
7434
    /* G_FSIN */
7435
    554,
7436
    /* G_FSQRT */
7437
    556,
7438
    /* G_FFLOOR */
7439
    558,
7440
    /* G_FRINT */
7441
    560,
7442
    /* G_FNEARBYINT */
7443
    562,
7444
    /* G_ADDRSPACE_CAST */
7445
    564,
7446
    /* G_BLOCK_ADDR */
7447
    566,
7448
    /* G_JUMP_TABLE */
7449
    568,
7450
    /* G_DYN_STACKALLOC */
7451
    570,
7452
    /* G_STACKSAVE */
7453
    573,
7454
    /* G_STACKRESTORE */
7455
    574,
7456
    /* G_STRICT_FADD */
7457
    575,
7458
    /* G_STRICT_FSUB */
7459
    578,
7460
    /* G_STRICT_FMUL */
7461
    581,
7462
    /* G_STRICT_FDIV */
7463
    584,
7464
    /* G_STRICT_FREM */
7465
    587,
7466
    /* G_STRICT_FMA */
7467
    590,
7468
    /* G_STRICT_FSQRT */
7469
    594,
7470
    /* G_STRICT_FLDEXP */
7471
    596,
7472
    /* G_READ_REGISTER */
7473
    599,
7474
    /* G_WRITE_REGISTER */
7475
    601,
7476
    /* G_MEMCPY */
7477
    603,
7478
    /* G_MEMCPY_INLINE */
7479
    607,
7480
    /* G_MEMMOVE */
7481
    610,
7482
    /* G_MEMSET */
7483
    614,
7484
    /* G_BZERO */
7485
    618,
7486
    /* G_VECREDUCE_SEQ_FADD */
7487
    621,
7488
    /* G_VECREDUCE_SEQ_FMUL */
7489
    624,
7490
    /* G_VECREDUCE_FADD */
7491
    627,
7492
    /* G_VECREDUCE_FMUL */
7493
    629,
7494
    /* G_VECREDUCE_FMAX */
7495
    631,
7496
    /* G_VECREDUCE_FMIN */
7497
    633,
7498
    /* G_VECREDUCE_FMAXIMUM */
7499
    635,
7500
    /* G_VECREDUCE_FMINIMUM */
7501
    637,
7502
    /* G_VECREDUCE_ADD */
7503
    639,
7504
    /* G_VECREDUCE_MUL */
7505
    641,
7506
    /* G_VECREDUCE_AND */
7507
    643,
7508
    /* G_VECREDUCE_OR */
7509
    645,
7510
    /* G_VECREDUCE_XOR */
7511
    647,
7512
    /* G_VECREDUCE_SMAX */
7513
    649,
7514
    /* G_VECREDUCE_SMIN */
7515
    651,
7516
    /* G_VECREDUCE_UMAX */
7517
    653,
7518
    /* G_VECREDUCE_UMIN */
7519
    655,
7520
    /* G_SBFX */
7521
    657,
7522
    /* G_UBFX */
7523
    661,
7524
    /* ADJCALLSTACKDOWN */
7525
    665,
7526
    /* ADJCALLSTACKUP */
7527
    667,
7528
    /* PseudoAtomicLoadAdd32 */
7529
    669,
7530
    /* PseudoAtomicLoadAnd32 */
7531
    674,
7532
    /* PseudoAtomicLoadNand32 */
7533
    679,
7534
    /* PseudoAtomicLoadNand64 */
7535
    684,
7536
    /* PseudoAtomicLoadOr32 */
7537
    689,
7538
    /* PseudoAtomicLoadSub32 */
7539
    694,
7540
    /* PseudoAtomicLoadXor32 */
7541
    699,
7542
    /* PseudoAtomicStoreD */
7543
    704,
7544
    /* PseudoAtomicStoreW */
7545
    707,
7546
    /* PseudoAtomicSwap32 */
7547
    710,
7548
    /* PseudoBR */
7549
    715,
7550
    /* PseudoBRIND */
7551
    716,
7552
    /* PseudoB_TAIL */
7553
    718,
7554
    /* PseudoCALL */
7555
    719,
7556
    /* PseudoCALL36 */
7557
    720,
7558
    /* PseudoCALLIndirect */
7559
    721,
7560
    /* PseudoCALL_LARGE */
7561
    722,
7562
    /* PseudoCALL_MEDIUM */
7563
    723,
7564
    /* PseudoCmpXchg32 */
7565
    724,
7566
    /* PseudoCmpXchg64 */
7567
    730,
7568
    /* PseudoCopyCFR */
7569
    736,
7570
    /* PseudoJIRL_CALL */
7571
    738,
7572
    /* PseudoJIRL_TAIL */
7573
    740,
7574
    /* PseudoLA_ABS */
7575
    742,
7576
    /* PseudoLA_ABS_LARGE */
7577
    744,
7578
    /* PseudoLA_GOT */
7579
    747,
7580
    /* PseudoLA_GOT_LARGE */
7581
    749,
7582
    /* PseudoLA_PCREL */
7583
    752,
7584
    /* PseudoLA_PCREL_LARGE */
7585
    754,
7586
    /* PseudoLA_TLS_GD */
7587
    757,
7588
    /* PseudoLA_TLS_GD_LARGE */
7589
    759,
7590
    /* PseudoLA_TLS_IE */
7591
    762,
7592
    /* PseudoLA_TLS_IE_LARGE */
7593
    764,
7594
    /* PseudoLA_TLS_LD */
7595
    767,
7596
    /* PseudoLA_TLS_LD_LARGE */
7597
    769,
7598
    /* PseudoLA_TLS_LE */
7599
    772,
7600
    /* PseudoLD_CFR */
7601
    774,
7602
    /* PseudoLI_D */
7603
    777,
7604
    /* PseudoLI_W */
7605
    779,
7606
    /* PseudoMaskedAtomicLoadAdd32 */
7607
    781,
7608
    /* PseudoMaskedAtomicLoadMax32 */
7609
    787,
7610
    /* PseudoMaskedAtomicLoadMin32 */
7611
    795,
7612
    /* PseudoMaskedAtomicLoadNand32 */
7613
    803,
7614
    /* PseudoMaskedAtomicLoadSub32 */
7615
    809,
7616
    /* PseudoMaskedAtomicLoadUMax32 */
7617
    815,
7618
    /* PseudoMaskedAtomicLoadUMin32 */
7619
    822,
7620
    /* PseudoMaskedAtomicSwap32 */
7621
    829,
7622
    /* PseudoMaskedCmpXchg32 */
7623
    835,
7624
    /* PseudoRET */
7625
    842,
7626
    /* PseudoST_CFR */
7627
    842,
7628
    /* PseudoTAIL */
7629
    845,
7630
    /* PseudoTAIL36 */
7631
    846,
7632
    /* PseudoTAILIndirect */
7633
    848,
7634
    /* PseudoTAIL_LARGE */
7635
    849,
7636
    /* PseudoTAIL_MEDIUM */
7637
    850,
7638
    /* PseudoUNIMP */
7639
    851,
7640
    /* PseudoVBNZ */
7641
    851,
7642
    /* PseudoVBNZ_B */
7643
    853,
7644
    /* PseudoVBNZ_D */
7645
    855,
7646
    /* PseudoVBNZ_H */
7647
    857,
7648
    /* PseudoVBNZ_W */
7649
    859,
7650
    /* PseudoVBZ */
7651
    861,
7652
    /* PseudoVBZ_B */
7653
    863,
7654
    /* PseudoVBZ_D */
7655
    865,
7656
    /* PseudoVBZ_H */
7657
    867,
7658
    /* PseudoVBZ_W */
7659
    869,
7660
    /* PseudoVREPLI_B */
7661
    871,
7662
    /* PseudoVREPLI_D */
7663
    873,
7664
    /* PseudoVREPLI_H */
7665
    875,
7666
    /* PseudoVREPLI_W */
7667
    877,
7668
    /* PseudoXVBNZ */
7669
    879,
7670
    /* PseudoXVBNZ_B */
7671
    881,
7672
    /* PseudoXVBNZ_D */
7673
    883,
7674
    /* PseudoXVBNZ_H */
7675
    885,
7676
    /* PseudoXVBNZ_W */
7677
    887,
7678
    /* PseudoXVBZ */
7679
    889,
7680
    /* PseudoXVBZ_B */
7681
    891,
7682
    /* PseudoXVBZ_D */
7683
    893,
7684
    /* PseudoXVBZ_H */
7685
    895,
7686
    /* PseudoXVBZ_W */
7687
    897,
7688
    /* PseudoXVINSGR2VR_B */
7689
    899,
7690
    /* PseudoXVINSGR2VR_H */
7691
    903,
7692
    /* PseudoXVREPLI_B */
7693
    907,
7694
    /* PseudoXVREPLI_D */
7695
    909,
7696
    /* PseudoXVREPLI_H */
7697
    911,
7698
    /* PseudoXVREPLI_W */
7699
    913,
7700
    /* RDFCSR */
7701
    915,
7702
    /* WRFCSR */
7703
    917,
7704
    /* ADC_B */
7705
    919,
7706
    /* ADC_D */
7707
    922,
7708
    /* ADC_H */
7709
    925,
7710
    /* ADC_W */
7711
    928,
7712
    /* ADDI_D */
7713
    931,
7714
    /* ADDI_W */
7715
    934,
7716
    /* ADDU12I_D */
7717
    937,
7718
    /* ADDU12I_W */
7719
    940,
7720
    /* ADDU16I_D */
7721
    943,
7722
    /* ADD_D */
7723
    946,
7724
    /* ADD_W */
7725
    949,
7726
    /* ALSL_D */
7727
    952,
7728
    /* ALSL_W */
7729
    956,
7730
    /* ALSL_WU */
7731
    960,
7732
    /* AMADD_B */
7733
    964,
7734
    /* AMADD_D */
7735
    967,
7736
    /* AMADD_H */
7737
    970,
7738
    /* AMADD_W */
7739
    973,
7740
    /* AMADD__DB_B */
7741
    976,
7742
    /* AMADD__DB_D */
7743
    979,
7744
    /* AMADD__DB_H */
7745
    982,
7746
    /* AMADD__DB_W */
7747
    985,
7748
    /* AMAND_D */
7749
    988,
7750
    /* AMAND_W */
7751
    991,
7752
    /* AMAND__DB_D */
7753
    994,
7754
    /* AMAND__DB_W */
7755
    997,
7756
    /* AMCAS_B */
7757
    1000,
7758
    /* AMCAS_D */
7759
    1003,
7760
    /* AMCAS_H */
7761
    1006,
7762
    /* AMCAS_W */
7763
    1009,
7764
    /* AMCAS__DB_B */
7765
    1012,
7766
    /* AMCAS__DB_D */
7767
    1015,
7768
    /* AMCAS__DB_H */
7769
    1018,
7770
    /* AMCAS__DB_W */
7771
    1021,
7772
    /* AMMAX_D */
7773
    1024,
7774
    /* AMMAX_DU */
7775
    1027,
7776
    /* AMMAX_W */
7777
    1030,
7778
    /* AMMAX_WU */
7779
    1033,
7780
    /* AMMAX__DB_D */
7781
    1036,
7782
    /* AMMAX__DB_DU */
7783
    1039,
7784
    /* AMMAX__DB_W */
7785
    1042,
7786
    /* AMMAX__DB_WU */
7787
    1045,
7788
    /* AMMIN_D */
7789
    1048,
7790
    /* AMMIN_DU */
7791
    1051,
7792
    /* AMMIN_W */
7793
    1054,
7794
    /* AMMIN_WU */
7795
    1057,
7796
    /* AMMIN__DB_D */
7797
    1060,
7798
    /* AMMIN__DB_DU */
7799
    1063,
7800
    /* AMMIN__DB_W */
7801
    1066,
7802
    /* AMMIN__DB_WU */
7803
    1069,
7804
    /* AMOR_D */
7805
    1072,
7806
    /* AMOR_W */
7807
    1075,
7808
    /* AMOR__DB_D */
7809
    1078,
7810
    /* AMOR__DB_W */
7811
    1081,
7812
    /* AMSWAP_B */
7813
    1084,
7814
    /* AMSWAP_D */
7815
    1087,
7816
    /* AMSWAP_H */
7817
    1090,
7818
    /* AMSWAP_W */
7819
    1093,
7820
    /* AMSWAP__DB_B */
7821
    1096,
7822
    /* AMSWAP__DB_D */
7823
    1099,
7824
    /* AMSWAP__DB_H */
7825
    1102,
7826
    /* AMSWAP__DB_W */
7827
    1105,
7828
    /* AMXOR_D */
7829
    1108,
7830
    /* AMXOR_W */
7831
    1111,
7832
    /* AMXOR__DB_D */
7833
    1114,
7834
    /* AMXOR__DB_W */
7835
    1117,
7836
    /* AND */
7837
    1120,
7838
    /* ANDI */
7839
    1123,
7840
    /* ANDN */
7841
    1126,
7842
    /* ARMADC_W */
7843
    1129,
7844
    /* ARMADD_W */
7845
    1132,
7846
    /* ARMAND_W */
7847
    1135,
7848
    /* ARMMFFLAG */
7849
    1138,
7850
    /* ARMMOVE */
7851
    1140,
7852
    /* ARMMOV_D */
7853
    1143,
7854
    /* ARMMOV_W */
7855
    1145,
7856
    /* ARMMTFLAG */
7857
    1147,
7858
    /* ARMNOT_W */
7859
    1149,
7860
    /* ARMOR_W */
7861
    1151,
7862
    /* ARMROTRI_W */
7863
    1154,
7864
    /* ARMROTR_W */
7865
    1157,
7866
    /* ARMRRX_W */
7867
    1160,
7868
    /* ARMSBC_W */
7869
    1162,
7870
    /* ARMSLLI_W */
7871
    1165,
7872
    /* ARMSLL_W */
7873
    1168,
7874
    /* ARMSRAI_W */
7875
    1171,
7876
    /* ARMSRA_W */
7877
    1174,
7878
    /* ARMSRLI_W */
7879
    1177,
7880
    /* ARMSRL_W */
7881
    1180,
7882
    /* ARMSUB_W */
7883
    1183,
7884
    /* ARMXOR_W */
7885
    1186,
7886
    /* ASRTGT_D */
7887
    1189,
7888
    /* ASRTLE_D */
7889
    1191,
7890
    /* B */
7891
    1193,
7892
    /* BCEQZ */
7893
    1194,
7894
    /* BCNEZ */
7895
    1196,
7896
    /* BEQ */
7897
    1198,
7898
    /* BEQZ */
7899
    1201,
7900
    /* BGE */
7901
    1203,
7902
    /* BGEU */
7903
    1206,
7904
    /* BITREV_4B */
7905
    1209,
7906
    /* BITREV_8B */
7907
    1211,
7908
    /* BITREV_D */
7909
    1213,
7910
    /* BITREV_W */
7911
    1215,
7912
    /* BL */
7913
    1217,
7914
    /* BLT */
7915
    1218,
7916
    /* BLTU */
7917
    1221,
7918
    /* BNE */
7919
    1224,
7920
    /* BNEZ */
7921
    1227,
7922
    /* BREAK */
7923
    1229,
7924
    /* BSTRINS_D */
7925
    1230,
7926
    /* BSTRINS_W */
7927
    1235,
7928
    /* BSTRPICK_D */
7929
    1240,
7930
    /* BSTRPICK_W */
7931
    1244,
7932
    /* BYTEPICK_D */
7933
    1248,
7934
    /* BYTEPICK_W */
7935
    1252,
7936
    /* CACOP */
7937
    1256,
7938
    /* CLO_D */
7939
    1259,
7940
    /* CLO_W */
7941
    1261,
7942
    /* CLZ_D */
7943
    1263,
7944
    /* CLZ_W */
7945
    1265,
7946
    /* CPUCFG */
7947
    1267,
7948
    /* CRCC_W_B_W */
7949
    1269,
7950
    /* CRCC_W_D_W */
7951
    1272,
7952
    /* CRCC_W_H_W */
7953
    1275,
7954
    /* CRCC_W_W_W */
7955
    1278,
7956
    /* CRC_W_B_W */
7957
    1281,
7958
    /* CRC_W_D_W */
7959
    1284,
7960
    /* CRC_W_H_W */
7961
    1287,
7962
    /* CRC_W_W_W */
7963
    1290,
7964
    /* CSRRD */
7965
    1293,
7966
    /* CSRWR */
7967
    1295,
7968
    /* CSRXCHG */
7969
    1298,
7970
    /* CTO_D */
7971
    1302,
7972
    /* CTO_W */
7973
    1304,
7974
    /* CTZ_D */
7975
    1306,
7976
    /* CTZ_W */
7977
    1308,
7978
    /* DBAR */
7979
    1310,
7980
    /* DBCL */
7981
    1311,
7982
    /* DIV_D */
7983
    1312,
7984
    /* DIV_DU */
7985
    1315,
7986
    /* DIV_W */
7987
    1318,
7988
    /* DIV_WU */
7989
    1321,
7990
    /* ERTN */
7991
    1324,
7992
    /* EXT_W_B */
7993
    1324,
7994
    /* EXT_W_H */
7995
    1326,
7996
    /* FABS_D */
7997
    1328,
7998
    /* FABS_S */
7999
    1330,
8000
    /* FADD_D */
8001
    1332,
8002
    /* FADD_S */
8003
    1335,
8004
    /* FCLASS_D */
8005
    1338,
8006
    /* FCLASS_S */
8007
    1340,
8008
    /* FCMP_CAF_D */
8009
    1342,
8010
    /* FCMP_CAF_S */
8011
    1345,
8012
    /* FCMP_CEQ_D */
8013
    1348,
8014
    /* FCMP_CEQ_S */
8015
    1351,
8016
    /* FCMP_CLE_D */
8017
    1354,
8018
    /* FCMP_CLE_S */
8019
    1357,
8020
    /* FCMP_CLT_D */
8021
    1360,
8022
    /* FCMP_CLT_S */
8023
    1363,
8024
    /* FCMP_CNE_D */
8025
    1366,
8026
    /* FCMP_CNE_S */
8027
    1369,
8028
    /* FCMP_COR_D */
8029
    1372,
8030
    /* FCMP_COR_S */
8031
    1375,
8032
    /* FCMP_CUEQ_D */
8033
    1378,
8034
    /* FCMP_CUEQ_S */
8035
    1381,
8036
    /* FCMP_CULE_D */
8037
    1384,
8038
    /* FCMP_CULE_S */
8039
    1387,
8040
    /* FCMP_CULT_D */
8041
    1390,
8042
    /* FCMP_CULT_S */
8043
    1393,
8044
    /* FCMP_CUNE_D */
8045
    1396,
8046
    /* FCMP_CUNE_S */
8047
    1399,
8048
    /* FCMP_CUN_D */
8049
    1402,
8050
    /* FCMP_CUN_S */
8051
    1405,
8052
    /* FCMP_SAF_D */
8053
    1408,
8054
    /* FCMP_SAF_S */
8055
    1411,
8056
    /* FCMP_SEQ_D */
8057
    1414,
8058
    /* FCMP_SEQ_S */
8059
    1417,
8060
    /* FCMP_SLE_D */
8061
    1420,
8062
    /* FCMP_SLE_S */
8063
    1423,
8064
    /* FCMP_SLT_D */
8065
    1426,
8066
    /* FCMP_SLT_S */
8067
    1429,
8068
    /* FCMP_SNE_D */
8069
    1432,
8070
    /* FCMP_SNE_S */
8071
    1435,
8072
    /* FCMP_SOR_D */
8073
    1438,
8074
    /* FCMP_SOR_S */
8075
    1441,
8076
    /* FCMP_SUEQ_D */
8077
    1444,
8078
    /* FCMP_SUEQ_S */
8079
    1447,
8080
    /* FCMP_SULE_D */
8081
    1450,
8082
    /* FCMP_SULE_S */
8083
    1453,
8084
    /* FCMP_SULT_D */
8085
    1456,
8086
    /* FCMP_SULT_S */
8087
    1459,
8088
    /* FCMP_SUNE_D */
8089
    1462,
8090
    /* FCMP_SUNE_S */
8091
    1465,
8092
    /* FCMP_SUN_D */
8093
    1468,
8094
    /* FCMP_SUN_S */
8095
    1471,
8096
    /* FCOPYSIGN_D */
8097
    1474,
8098
    /* FCOPYSIGN_S */
8099
    1477,
8100
    /* FCVT_D_LD */
8101
    1480,
8102
    /* FCVT_D_S */
8103
    1483,
8104
    /* FCVT_LD_D */
8105
    1485,
8106
    /* FCVT_S_D */
8107
    1487,
8108
    /* FCVT_UD_D */
8109
    1489,
8110
    /* FDIV_D */
8111
    1491,
8112
    /* FDIV_S */
8113
    1494,
8114
    /* FFINT_D_L */
8115
    1497,
8116
    /* FFINT_D_W */
8117
    1499,
8118
    /* FFINT_S_L */
8119
    1501,
8120
    /* FFINT_S_W */
8121
    1503,
8122
    /* FLDGT_D */
8123
    1505,
8124
    /* FLDGT_S */
8125
    1508,
8126
    /* FLDLE_D */
8127
    1511,
8128
    /* FLDLE_S */
8129
    1514,
8130
    /* FLDX_D */
8131
    1517,
8132
    /* FLDX_S */
8133
    1520,
8134
    /* FLD_D */
8135
    1523,
8136
    /* FLD_S */
8137
    1526,
8138
    /* FLOGB_D */
8139
    1529,
8140
    /* FLOGB_S */
8141
    1531,
8142
    /* FMADD_D */
8143
    1533,
8144
    /* FMADD_S */
8145
    1537,
8146
    /* FMAXA_D */
8147
    1541,
8148
    /* FMAXA_S */
8149
    1544,
8150
    /* FMAX_D */
8151
    1547,
8152
    /* FMAX_S */
8153
    1550,
8154
    /* FMINA_D */
8155
    1553,
8156
    /* FMINA_S */
8157
    1556,
8158
    /* FMIN_D */
8159
    1559,
8160
    /* FMIN_S */
8161
    1562,
8162
    /* FMOV_D */
8163
    1565,
8164
    /* FMOV_S */
8165
    1567,
8166
    /* FMSUB_D */
8167
    1569,
8168
    /* FMSUB_S */
8169
    1573,
8170
    /* FMUL_D */
8171
    1577,
8172
    /* FMUL_S */
8173
    1580,
8174
    /* FNEG_D */
8175
    1583,
8176
    /* FNEG_S */
8177
    1585,
8178
    /* FNMADD_D */
8179
    1587,
8180
    /* FNMADD_S */
8181
    1591,
8182
    /* FNMSUB_D */
8183
    1595,
8184
    /* FNMSUB_S */
8185
    1599,
8186
    /* FRECIPE_D */
8187
    1603,
8188
    /* FRECIPE_S */
8189
    1605,
8190
    /* FRECIP_D */
8191
    1607,
8192
    /* FRECIP_S */
8193
    1609,
8194
    /* FRINT_D */
8195
    1611,
8196
    /* FRINT_S */
8197
    1613,
8198
    /* FRSQRTE_D */
8199
    1615,
8200
    /* FRSQRTE_S */
8201
    1617,
8202
    /* FRSQRT_D */
8203
    1619,
8204
    /* FRSQRT_S */
8205
    1621,
8206
    /* FSCALEB_D */
8207
    1623,
8208
    /* FSCALEB_S */
8209
    1626,
8210
    /* FSEL_xD */
8211
    1629,
8212
    /* FSEL_xS */
8213
    1633,
8214
    /* FSQRT_D */
8215
    1637,
8216
    /* FSQRT_S */
8217
    1639,
8218
    /* FSTGT_D */
8219
    1641,
8220
    /* FSTGT_S */
8221
    1644,
8222
    /* FSTLE_D */
8223
    1647,
8224
    /* FSTLE_S */
8225
    1650,
8226
    /* FSTX_D */
8227
    1653,
8228
    /* FSTX_S */
8229
    1656,
8230
    /* FST_D */
8231
    1659,
8232
    /* FST_S */
8233
    1662,
8234
    /* FSUB_D */
8235
    1665,
8236
    /* FSUB_S */
8237
    1668,
8238
    /* FTINTRM_L_D */
8239
    1671,
8240
    /* FTINTRM_L_S */
8241
    1673,
8242
    /* FTINTRM_W_D */
8243
    1675,
8244
    /* FTINTRM_W_S */
8245
    1677,
8246
    /* FTINTRNE_L_D */
8247
    1679,
8248
    /* FTINTRNE_L_S */
8249
    1681,
8250
    /* FTINTRNE_W_D */
8251
    1683,
8252
    /* FTINTRNE_W_S */
8253
    1685,
8254
    /* FTINTRP_L_D */
8255
    1687,
8256
    /* FTINTRP_L_S */
8257
    1689,
8258
    /* FTINTRP_W_D */
8259
    1691,
8260
    /* FTINTRP_W_S */
8261
    1693,
8262
    /* FTINTRZ_L_D */
8263
    1695,
8264
    /* FTINTRZ_L_S */
8265
    1697,
8266
    /* FTINTRZ_W_D */
8267
    1699,
8268
    /* FTINTRZ_W_S */
8269
    1701,
8270
    /* FTINT_L_D */
8271
    1703,
8272
    /* FTINT_L_S */
8273
    1705,
8274
    /* FTINT_W_D */
8275
    1707,
8276
    /* FTINT_W_S */
8277
    1709,
8278
    /* GCSRRD */
8279
    1711,
8280
    /* GCSRWR */
8281
    1713,
8282
    /* GCSRXCHG */
8283
    1716,
8284
    /* GTLBFLUSH */
8285
    1720,
8286
    /* HVCL */
8287
    1720,
8288
    /* IBAR */
8289
    1721,
8290
    /* IDLE */
8291
    1722,
8292
    /* INVTLB */
8293
    1723,
8294
    /* IOCSRRD_B */
8295
    1726,
8296
    /* IOCSRRD_D */
8297
    1728,
8298
    /* IOCSRRD_H */
8299
    1730,
8300
    /* IOCSRRD_W */
8301
    1732,
8302
    /* IOCSRWR_B */
8303
    1734,
8304
    /* IOCSRWR_D */
8305
    1736,
8306
    /* IOCSRWR_H */
8307
    1738,
8308
    /* IOCSRWR_W */
8309
    1740,
8310
    /* JIRL */
8311
    1742,
8312
    /* JISCR0 */
8313
    1745,
8314
    /* JISCR1 */
8315
    1746,
8316
    /* LDDIR */
8317
    1747,
8318
    /* LDGT_B */
8319
    1750,
8320
    /* LDGT_D */
8321
    1753,
8322
    /* LDGT_H */
8323
    1756,
8324
    /* LDGT_W */
8325
    1759,
8326
    /* LDLE_B */
8327
    1762,
8328
    /* LDLE_D */
8329
    1765,
8330
    /* LDLE_H */
8331
    1768,
8332
    /* LDLE_W */
8333
    1771,
8334
    /* LDL_D */
8335
    1774,
8336
    /* LDL_W */
8337
    1777,
8338
    /* LDPTE */
8339
    1780,
8340
    /* LDPTR_D */
8341
    1782,
8342
    /* LDPTR_W */
8343
    1785,
8344
    /* LDR_D */
8345
    1788,
8346
    /* LDR_W */
8347
    1791,
8348
    /* LDX_B */
8349
    1794,
8350
    /* LDX_BU */
8351
    1797,
8352
    /* LDX_D */
8353
    1800,
8354
    /* LDX_H */
8355
    1803,
8356
    /* LDX_HU */
8357
    1806,
8358
    /* LDX_W */
8359
    1809,
8360
    /* LDX_WU */
8361
    1812,
8362
    /* LD_B */
8363
    1815,
8364
    /* LD_BU */
8365
    1818,
8366
    /* LD_D */
8367
    1821,
8368
    /* LD_H */
8369
    1824,
8370
    /* LD_HU */
8371
    1827,
8372
    /* LD_W */
8373
    1830,
8374
    /* LD_WU */
8375
    1833,
8376
    /* LLACQ_D */
8377
    1836,
8378
    /* LLACQ_W */
8379
    1838,
8380
    /* LL_D */
8381
    1840,
8382
    /* LL_W */
8383
    1843,
8384
    /* LU12I_W */
8385
    1846,
8386
    /* LU32I_D */
8387
    1848,
8388
    /* LU52I_D */
8389
    1851,
8390
    /* MASKEQZ */
8391
    1854,
8392
    /* MASKNEZ */
8393
    1857,
8394
    /* MOD_D */
8395
    1860,
8396
    /* MOD_DU */
8397
    1863,
8398
    /* MOD_W */
8399
    1866,
8400
    /* MOD_WU */
8401
    1869,
8402
    /* MOVCF2FR_xS */
8403
    1872,
8404
    /* MOVCF2GR */
8405
    1874,
8406
    /* MOVFCSR2GR */
8407
    1876,
8408
    /* MOVFR2CF_xS */
8409
    1878,
8410
    /* MOVFR2GR_D */
8411
    1880,
8412
    /* MOVFR2GR_S */
8413
    1882,
8414
    /* MOVFR2GR_S_64 */
8415
    1884,
8416
    /* MOVFRH2GR_S */
8417
    1886,
8418
    /* MOVGR2CF */
8419
    1888,
8420
    /* MOVGR2FCSR */
8421
    1890,
8422
    /* MOVGR2FRH_W */
8423
    1892,
8424
    /* MOVGR2FR_D */
8425
    1895,
8426
    /* MOVGR2FR_W */
8427
    1897,
8428
    /* MOVGR2FR_W_64 */
8429
    1899,
8430
    /* MOVGR2SCR */
8431
    1901,
8432
    /* MOVSCR2GR */
8433
    1903,
8434
    /* MULH_D */
8435
    1905,
8436
    /* MULH_DU */
8437
    1908,
8438
    /* MULH_W */
8439
    1911,
8440
    /* MULH_WU */
8441
    1914,
8442
    /* MULW_D_W */
8443
    1917,
8444
    /* MULW_D_WU */
8445
    1920,
8446
    /* MUL_D */
8447
    1923,
8448
    /* MUL_W */
8449
    1926,
8450
    /* NOR */
8451
    1929,
8452
    /* OR */
8453
    1932,
8454
    /* ORI */
8455
    1935,
8456
    /* ORN */
8457
    1938,
8458
    /* PCADDI */
8459
    1941,
8460
    /* PCADDU12I */
8461
    1943,
8462
    /* PCADDU18I */
8463
    1945,
8464
    /* PCALAU12I */
8465
    1947,
8466
    /* PRELD */
8467
    1949,
8468
    /* PRELDX */
8469
    1952,
8470
    /* RCRI_B */
8471
    1955,
8472
    /* RCRI_D */
8473
    1958,
8474
    /* RCRI_H */
8475
    1961,
8476
    /* RCRI_W */
8477
    1964,
8478
    /* RCR_B */
8479
    1967,
8480
    /* RCR_D */
8481
    1970,
8482
    /* RCR_H */
8483
    1973,
8484
    /* RCR_W */
8485
    1976,
8486
    /* RDTIMEH_W */
8487
    1979,
8488
    /* RDTIMEL_W */
8489
    1981,
8490
    /* RDTIME_D */
8491
    1983,
8492
    /* REVB_2H */
8493
    1985,
8494
    /* REVB_2W */
8495
    1987,
8496
    /* REVB_4H */
8497
    1989,
8498
    /* REVB_D */
8499
    1991,
8500
    /* REVH_2W */
8501
    1993,
8502
    /* REVH_D */
8503
    1995,
8504
    /* ROTRI_B */
8505
    1997,
8506
    /* ROTRI_D */
8507
    2000,
8508
    /* ROTRI_H */
8509
    2003,
8510
    /* ROTRI_W */
8511
    2006,
8512
    /* ROTR_B */
8513
    2009,
8514
    /* ROTR_D */
8515
    2012,
8516
    /* ROTR_H */
8517
    2015,
8518
    /* ROTR_W */
8519
    2018,
8520
    /* SBC_B */
8521
    2021,
8522
    /* SBC_D */
8523
    2024,
8524
    /* SBC_H */
8525
    2027,
8526
    /* SBC_W */
8527
    2030,
8528
    /* SCREL_D */
8529
    2033,
8530
    /* SCREL_W */
8531
    2036,
8532
    /* SC_D */
8533
    2039,
8534
    /* SC_Q */
8535
    2043,
8536
    /* SC_W */
8537
    2047,
8538
    /* SETARMJ */
8539
    2051,
8540
    /* SETX86J */
8541
    2053,
8542
    /* SETX86LOOPE */
8543
    2055,
8544
    /* SETX86LOOPNE */
8545
    2057,
8546
    /* SET_CFR_FALSE */
8547
    2059,
8548
    /* SET_CFR_TRUE */
8549
    2060,
8550
    /* SLLI_D */
8551
    2061,
8552
    /* SLLI_W */
8553
    2064,
8554
    /* SLL_D */
8555
    2067,
8556
    /* SLL_W */
8557
    2070,
8558
    /* SLT */
8559
    2073,
8560
    /* SLTI */
8561
    2076,
8562
    /* SLTU */
8563
    2079,
8564
    /* SLTUI */
8565
    2082,
8566
    /* SRAI_D */
8567
    2085,
8568
    /* SRAI_W */
8569
    2088,
8570
    /* SRA_D */
8571
    2091,
8572
    /* SRA_W */
8573
    2094,
8574
    /* SRLI_D */
8575
    2097,
8576
    /* SRLI_W */
8577
    2100,
8578
    /* SRL_D */
8579
    2103,
8580
    /* SRL_W */
8581
    2106,
8582
    /* STGT_B */
8583
    2109,
8584
    /* STGT_D */
8585
    2112,
8586
    /* STGT_H */
8587
    2115,
8588
    /* STGT_W */
8589
    2118,
8590
    /* STLE_B */
8591
    2121,
8592
    /* STLE_D */
8593
    2124,
8594
    /* STLE_H */
8595
    2127,
8596
    /* STLE_W */
8597
    2130,
8598
    /* STL_D */
8599
    2133,
8600
    /* STL_W */
8601
    2136,
8602
    /* STPTR_D */
8603
    2139,
8604
    /* STPTR_W */
8605
    2142,
8606
    /* STR_D */
8607
    2145,
8608
    /* STR_W */
8609
    2148,
8610
    /* STX_B */
8611
    2151,
8612
    /* STX_D */
8613
    2154,
8614
    /* STX_H */
8615
    2157,
8616
    /* STX_W */
8617
    2160,
8618
    /* ST_B */
8619
    2163,
8620
    /* ST_D */
8621
    2166,
8622
    /* ST_H */
8623
    2169,
8624
    /* ST_W */
8625
    2172,
8626
    /* SUB_D */
8627
    2175,
8628
    /* SUB_W */
8629
    2178,
8630
    /* SYSCALL */
8631
    2181,
8632
    /* TLBCLR */
8633
    2182,
8634
    /* TLBFILL */
8635
    2182,
8636
    /* TLBFLUSH */
8637
    2182,
8638
    /* TLBRD */
8639
    2182,
8640
    /* TLBSRCH */
8641
    2182,
8642
    /* TLBWR */
8643
    2182,
8644
    /* VABSD_B */
8645
    2182,
8646
    /* VABSD_BU */
8647
    2185,
8648
    /* VABSD_D */
8649
    2188,
8650
    /* VABSD_DU */
8651
    2191,
8652
    /* VABSD_H */
8653
    2194,
8654
    /* VABSD_HU */
8655
    2197,
8656
    /* VABSD_W */
8657
    2200,
8658
    /* VABSD_WU */
8659
    2203,
8660
    /* VADDA_B */
8661
    2206,
8662
    /* VADDA_D */
8663
    2209,
8664
    /* VADDA_H */
8665
    2212,
8666
    /* VADDA_W */
8667
    2215,
8668
    /* VADDI_BU */
8669
    2218,
8670
    /* VADDI_DU */
8671
    2221,
8672
    /* VADDI_HU */
8673
    2224,
8674
    /* VADDI_WU */
8675
    2227,
8676
    /* VADDWEV_D_W */
8677
    2230,
8678
    /* VADDWEV_D_WU */
8679
    2233,
8680
    /* VADDWEV_D_WU_W */
8681
    2236,
8682
    /* VADDWEV_H_B */
8683
    2239,
8684
    /* VADDWEV_H_BU */
8685
    2242,
8686
    /* VADDWEV_H_BU_B */
8687
    2245,
8688
    /* VADDWEV_Q_D */
8689
    2248,
8690
    /* VADDWEV_Q_DU */
8691
    2251,
8692
    /* VADDWEV_Q_DU_D */
8693
    2254,
8694
    /* VADDWEV_W_H */
8695
    2257,
8696
    /* VADDWEV_W_HU */
8697
    2260,
8698
    /* VADDWEV_W_HU_H */
8699
    2263,
8700
    /* VADDWOD_D_W */
8701
    2266,
8702
    /* VADDWOD_D_WU */
8703
    2269,
8704
    /* VADDWOD_D_WU_W */
8705
    2272,
8706
    /* VADDWOD_H_B */
8707
    2275,
8708
    /* VADDWOD_H_BU */
8709
    2278,
8710
    /* VADDWOD_H_BU_B */
8711
    2281,
8712
    /* VADDWOD_Q_D */
8713
    2284,
8714
    /* VADDWOD_Q_DU */
8715
    2287,
8716
    /* VADDWOD_Q_DU_D */
8717
    2290,
8718
    /* VADDWOD_W_H */
8719
    2293,
8720
    /* VADDWOD_W_HU */
8721
    2296,
8722
    /* VADDWOD_W_HU_H */
8723
    2299,
8724
    /* VADD_B */
8725
    2302,
8726
    /* VADD_D */
8727
    2305,
8728
    /* VADD_H */
8729
    2308,
8730
    /* VADD_Q */
8731
    2311,
8732
    /* VADD_W */
8733
    2314,
8734
    /* VANDI_B */
8735
    2317,
8736
    /* VANDN_V */
8737
    2320,
8738
    /* VAND_V */
8739
    2323,
8740
    /* VAVGR_B */
8741
    2326,
8742
    /* VAVGR_BU */
8743
    2329,
8744
    /* VAVGR_D */
8745
    2332,
8746
    /* VAVGR_DU */
8747
    2335,
8748
    /* VAVGR_H */
8749
    2338,
8750
    /* VAVGR_HU */
8751
    2341,
8752
    /* VAVGR_W */
8753
    2344,
8754
    /* VAVGR_WU */
8755
    2347,
8756
    /* VAVG_B */
8757
    2350,
8758
    /* VAVG_BU */
8759
    2353,
8760
    /* VAVG_D */
8761
    2356,
8762
    /* VAVG_DU */
8763
    2359,
8764
    /* VAVG_H */
8765
    2362,
8766
    /* VAVG_HU */
8767
    2365,
8768
    /* VAVG_W */
8769
    2368,
8770
    /* VAVG_WU */
8771
    2371,
8772
    /* VBITCLRI_B */
8773
    2374,
8774
    /* VBITCLRI_D */
8775
    2377,
8776
    /* VBITCLRI_H */
8777
    2380,
8778
    /* VBITCLRI_W */
8779
    2383,
8780
    /* VBITCLR_B */
8781
    2386,
8782
    /* VBITCLR_D */
8783
    2389,
8784
    /* VBITCLR_H */
8785
    2392,
8786
    /* VBITCLR_W */
8787
    2395,
8788
    /* VBITREVI_B */
8789
    2398,
8790
    /* VBITREVI_D */
8791
    2401,
8792
    /* VBITREVI_H */
8793
    2404,
8794
    /* VBITREVI_W */
8795
    2407,
8796
    /* VBITREV_B */
8797
    2410,
8798
    /* VBITREV_D */
8799
    2413,
8800
    /* VBITREV_H */
8801
    2416,
8802
    /* VBITREV_W */
8803
    2419,
8804
    /* VBITSELI_B */
8805
    2422,
8806
    /* VBITSEL_V */
8807
    2426,
8808
    /* VBITSETI_B */
8809
    2430,
8810
    /* VBITSETI_D */
8811
    2433,
8812
    /* VBITSETI_H */
8813
    2436,
8814
    /* VBITSETI_W */
8815
    2439,
8816
    /* VBITSET_B */
8817
    2442,
8818
    /* VBITSET_D */
8819
    2445,
8820
    /* VBITSET_H */
8821
    2448,
8822
    /* VBITSET_W */
8823
    2451,
8824
    /* VBSLL_V */
8825
    2454,
8826
    /* VBSRL_V */
8827
    2457,
8828
    /* VCLO_B */
8829
    2460,
8830
    /* VCLO_D */
8831
    2462,
8832
    /* VCLO_H */
8833
    2464,
8834
    /* VCLO_W */
8835
    2466,
8836
    /* VCLZ_B */
8837
    2468,
8838
    /* VCLZ_D */
8839
    2470,
8840
    /* VCLZ_H */
8841
    2472,
8842
    /* VCLZ_W */
8843
    2474,
8844
    /* VDIV_B */
8845
    2476,
8846
    /* VDIV_BU */
8847
    2479,
8848
    /* VDIV_D */
8849
    2482,
8850
    /* VDIV_DU */
8851
    2485,
8852
    /* VDIV_H */
8853
    2488,
8854
    /* VDIV_HU */
8855
    2491,
8856
    /* VDIV_W */
8857
    2494,
8858
    /* VDIV_WU */
8859
    2497,
8860
    /* VEXT2XV_DU_BU */
8861
    2500,
8862
    /* VEXT2XV_DU_HU */
8863
    2502,
8864
    /* VEXT2XV_DU_WU */
8865
    2504,
8866
    /* VEXT2XV_D_B */
8867
    2506,
8868
    /* VEXT2XV_D_H */
8869
    2508,
8870
    /* VEXT2XV_D_W */
8871
    2510,
8872
    /* VEXT2XV_HU_BU */
8873
    2512,
8874
    /* VEXT2XV_H_B */
8875
    2514,
8876
    /* VEXT2XV_WU_BU */
8877
    2516,
8878
    /* VEXT2XV_WU_HU */
8879
    2518,
8880
    /* VEXT2XV_W_B */
8881
    2520,
8882
    /* VEXT2XV_W_H */
8883
    2522,
8884
    /* VEXTH_DU_WU */
8885
    2524,
8886
    /* VEXTH_D_W */
8887
    2526,
8888
    /* VEXTH_HU_BU */
8889
    2528,
8890
    /* VEXTH_H_B */
8891
    2530,
8892
    /* VEXTH_QU_DU */
8893
    2532,
8894
    /* VEXTH_Q_D */
8895
    2534,
8896
    /* VEXTH_WU_HU */
8897
    2536,
8898
    /* VEXTH_W_H */
8899
    2538,
8900
    /* VEXTL_QU_DU */
8901
    2540,
8902
    /* VEXTL_Q_D */
8903
    2542,
8904
    /* VEXTRINS_B */
8905
    2544,
8906
    /* VEXTRINS_D */
8907
    2548,
8908
    /* VEXTRINS_H */
8909
    2552,
8910
    /* VEXTRINS_W */
8911
    2556,
8912
    /* VFADD_D */
8913
    2560,
8914
    /* VFADD_S */
8915
    2563,
8916
    /* VFCLASS_D */
8917
    2566,
8918
    /* VFCLASS_S */
8919
    2568,
8920
    /* VFCMP_CAF_D */
8921
    2570,
8922
    /* VFCMP_CAF_S */
8923
    2573,
8924
    /* VFCMP_CEQ_D */
8925
    2576,
8926
    /* VFCMP_CEQ_S */
8927
    2579,
8928
    /* VFCMP_CLE_D */
8929
    2582,
8930
    /* VFCMP_CLE_S */
8931
    2585,
8932
    /* VFCMP_CLT_D */
8933
    2588,
8934
    /* VFCMP_CLT_S */
8935
    2591,
8936
    /* VFCMP_CNE_D */
8937
    2594,
8938
    /* VFCMP_CNE_S */
8939
    2597,
8940
    /* VFCMP_COR_D */
8941
    2600,
8942
    /* VFCMP_COR_S */
8943
    2603,
8944
    /* VFCMP_CUEQ_D */
8945
    2606,
8946
    /* VFCMP_CUEQ_S */
8947
    2609,
8948
    /* VFCMP_CULE_D */
8949
    2612,
8950
    /* VFCMP_CULE_S */
8951
    2615,
8952
    /* VFCMP_CULT_D */
8953
    2618,
8954
    /* VFCMP_CULT_S */
8955
    2621,
8956
    /* VFCMP_CUNE_D */
8957
    2624,
8958
    /* VFCMP_CUNE_S */
8959
    2627,
8960
    /* VFCMP_CUN_D */
8961
    2630,
8962
    /* VFCMP_CUN_S */
8963
    2633,
8964
    /* VFCMP_SAF_D */
8965
    2636,
8966
    /* VFCMP_SAF_S */
8967
    2639,
8968
    /* VFCMP_SEQ_D */
8969
    2642,
8970
    /* VFCMP_SEQ_S */
8971
    2645,
8972
    /* VFCMP_SLE_D */
8973
    2648,
8974
    /* VFCMP_SLE_S */
8975
    2651,
8976
    /* VFCMP_SLT_D */
8977
    2654,
8978
    /* VFCMP_SLT_S */
8979
    2657,
8980
    /* VFCMP_SNE_D */
8981
    2660,
8982
    /* VFCMP_SNE_S */
8983
    2663,
8984
    /* VFCMP_SOR_D */
8985
    2666,
8986
    /* VFCMP_SOR_S */
8987
    2669,
8988
    /* VFCMP_SUEQ_D */
8989
    2672,
8990
    /* VFCMP_SUEQ_S */
8991
    2675,
8992
    /* VFCMP_SULE_D */
8993
    2678,
8994
    /* VFCMP_SULE_S */
8995
    2681,
8996
    /* VFCMP_SULT_D */
8997
    2684,
8998
    /* VFCMP_SULT_S */
8999
    2687,
9000
    /* VFCMP_SUNE_D */
9001
    2690,
9002
    /* VFCMP_SUNE_S */
9003
    2693,
9004
    /* VFCMP_SUN_D */
9005
    2696,
9006
    /* VFCMP_SUN_S */
9007
    2699,
9008
    /* VFCVTH_D_S */
9009
    2702,
9010
    /* VFCVTH_S_H */
9011
    2704,
9012
    /* VFCVTL_D_S */
9013
    2706,
9014
    /* VFCVTL_S_H */
9015
    2708,
9016
    /* VFCVT_H_S */
9017
    2710,
9018
    /* VFCVT_S_D */
9019
    2713,
9020
    /* VFDIV_D */
9021
    2716,
9022
    /* VFDIV_S */
9023
    2719,
9024
    /* VFFINTH_D_W */
9025
    2722,
9026
    /* VFFINTL_D_W */
9027
    2724,
9028
    /* VFFINT_D_L */
9029
    2726,
9030
    /* VFFINT_D_LU */
9031
    2728,
9032
    /* VFFINT_S_L */
9033
    2730,
9034
    /* VFFINT_S_W */
9035
    2733,
9036
    /* VFFINT_S_WU */
9037
    2735,
9038
    /* VFLOGB_D */
9039
    2737,
9040
    /* VFLOGB_S */
9041
    2739,
9042
    /* VFMADD_D */
9043
    2741,
9044
    /* VFMADD_S */
9045
    2745,
9046
    /* VFMAXA_D */
9047
    2749,
9048
    /* VFMAXA_S */
9049
    2752,
9050
    /* VFMAX_D */
9051
    2755,
9052
    /* VFMAX_S */
9053
    2758,
9054
    /* VFMINA_D */
9055
    2761,
9056
    /* VFMINA_S */
9057
    2764,
9058
    /* VFMIN_D */
9059
    2767,
9060
    /* VFMIN_S */
9061
    2770,
9062
    /* VFMSUB_D */
9063
    2773,
9064
    /* VFMSUB_S */
9065
    2777,
9066
    /* VFMUL_D */
9067
    2781,
9068
    /* VFMUL_S */
9069
    2784,
9070
    /* VFNMADD_D */
9071
    2787,
9072
    /* VFNMADD_S */
9073
    2791,
9074
    /* VFNMSUB_D */
9075
    2795,
9076
    /* VFNMSUB_S */
9077
    2799,
9078
    /* VFRECIPE_D */
9079
    2803,
9080
    /* VFRECIPE_S */
9081
    2805,
9082
    /* VFRECIP_D */
9083
    2807,
9084
    /* VFRECIP_S */
9085
    2809,
9086
    /* VFRINTRM_D */
9087
    2811,
9088
    /* VFRINTRM_S */
9089
    2813,
9090
    /* VFRINTRNE_D */
9091
    2815,
9092
    /* VFRINTRNE_S */
9093
    2817,
9094
    /* VFRINTRP_D */
9095
    2819,
9096
    /* VFRINTRP_S */
9097
    2821,
9098
    /* VFRINTRZ_D */
9099
    2823,
9100
    /* VFRINTRZ_S */
9101
    2825,
9102
    /* VFRINT_D */
9103
    2827,
9104
    /* VFRINT_S */
9105
    2829,
9106
    /* VFRSQRTE_D */
9107
    2831,
9108
    /* VFRSQRTE_S */
9109
    2833,
9110
    /* VFRSQRT_D */
9111
    2835,
9112
    /* VFRSQRT_S */
9113
    2837,
9114
    /* VFRSTPI_B */
9115
    2839,
9116
    /* VFRSTPI_H */
9117
    2843,
9118
    /* VFRSTP_B */
9119
    2847,
9120
    /* VFRSTP_H */
9121
    2851,
9122
    /* VFSQRT_D */
9123
    2855,
9124
    /* VFSQRT_S */
9125
    2857,
9126
    /* VFSUB_D */
9127
    2859,
9128
    /* VFSUB_S */
9129
    2862,
9130
    /* VFTINTH_L_S */
9131
    2865,
9132
    /* VFTINTL_L_S */
9133
    2867,
9134
    /* VFTINTRMH_L_S */
9135
    2869,
9136
    /* VFTINTRML_L_S */
9137
    2871,
9138
    /* VFTINTRM_L_D */
9139
    2873,
9140
    /* VFTINTRM_W_D */
9141
    2875,
9142
    /* VFTINTRM_W_S */
9143
    2878,
9144
    /* VFTINTRNEH_L_S */
9145
    2880,
9146
    /* VFTINTRNEL_L_S */
9147
    2882,
9148
    /* VFTINTRNE_L_D */
9149
    2884,
9150
    /* VFTINTRNE_W_D */
9151
    2886,
9152
    /* VFTINTRNE_W_S */
9153
    2889,
9154
    /* VFTINTRPH_L_S */
9155
    2891,
9156
    /* VFTINTRPL_L_S */
9157
    2893,
9158
    /* VFTINTRP_L_D */
9159
    2895,
9160
    /* VFTINTRP_W_D */
9161
    2897,
9162
    /* VFTINTRP_W_S */
9163
    2900,
9164
    /* VFTINTRZH_L_S */
9165
    2902,
9166
    /* VFTINTRZL_L_S */
9167
    2904,
9168
    /* VFTINTRZ_LU_D */
9169
    2906,
9170
    /* VFTINTRZ_L_D */
9171
    2908,
9172
    /* VFTINTRZ_WU_S */
9173
    2910,
9174
    /* VFTINTRZ_W_D */
9175
    2912,
9176
    /* VFTINTRZ_W_S */
9177
    2915,
9178
    /* VFTINT_LU_D */
9179
    2917,
9180
    /* VFTINT_L_D */
9181
    2919,
9182
    /* VFTINT_WU_S */
9183
    2921,
9184
    /* VFTINT_W_D */
9185
    2923,
9186
    /* VFTINT_W_S */
9187
    2926,
9188
    /* VHADDW_DU_WU */
9189
    2928,
9190
    /* VHADDW_D_W */
9191
    2931,
9192
    /* VHADDW_HU_BU */
9193
    2934,
9194
    /* VHADDW_H_B */
9195
    2937,
9196
    /* VHADDW_QU_DU */
9197
    2940,
9198
    /* VHADDW_Q_D */
9199
    2943,
9200
    /* VHADDW_WU_HU */
9201
    2946,
9202
    /* VHADDW_W_H */
9203
    2949,
9204
    /* VHSUBW_DU_WU */
9205
    2952,
9206
    /* VHSUBW_D_W */
9207
    2955,
9208
    /* VHSUBW_HU_BU */
9209
    2958,
9210
    /* VHSUBW_H_B */
9211
    2961,
9212
    /* VHSUBW_QU_DU */
9213
    2964,
9214
    /* VHSUBW_Q_D */
9215
    2967,
9216
    /* VHSUBW_WU_HU */
9217
    2970,
9218
    /* VHSUBW_W_H */
9219
    2973,
9220
    /* VILVH_B */
9221
    2976,
9222
    /* VILVH_D */
9223
    2979,
9224
    /* VILVH_H */
9225
    2982,
9226
    /* VILVH_W */
9227
    2985,
9228
    /* VILVL_B */
9229
    2988,
9230
    /* VILVL_D */
9231
    2991,
9232
    /* VILVL_H */
9233
    2994,
9234
    /* VILVL_W */
9235
    2997,
9236
    /* VINSGR2VR_B */
9237
    3000,
9238
    /* VINSGR2VR_D */
9239
    3004,
9240
    /* VINSGR2VR_H */
9241
    3008,
9242
    /* VINSGR2VR_W */
9243
    3012,
9244
    /* VLD */
9245
    3016,
9246
    /* VLDI */
9247
    3019,
9248
    /* VLDREPL_B */
9249
    3021,
9250
    /* VLDREPL_D */
9251
    3024,
9252
    /* VLDREPL_H */
9253
    3027,
9254
    /* VLDREPL_W */
9255
    3030,
9256
    /* VLDX */
9257
    3033,
9258
    /* VMADDWEV_D_W */
9259
    3036,
9260
    /* VMADDWEV_D_WU */
9261
    3040,
9262
    /* VMADDWEV_D_WU_W */
9263
    3044,
9264
    /* VMADDWEV_H_B */
9265
    3048,
9266
    /* VMADDWEV_H_BU */
9267
    3052,
9268
    /* VMADDWEV_H_BU_B */
9269
    3056,
9270
    /* VMADDWEV_Q_D */
9271
    3060,
9272
    /* VMADDWEV_Q_DU */
9273
    3064,
9274
    /* VMADDWEV_Q_DU_D */
9275
    3068,
9276
    /* VMADDWEV_W_H */
9277
    3072,
9278
    /* VMADDWEV_W_HU */
9279
    3076,
9280
    /* VMADDWEV_W_HU_H */
9281
    3080,
9282
    /* VMADDWOD_D_W */
9283
    3084,
9284
    /* VMADDWOD_D_WU */
9285
    3088,
9286
    /* VMADDWOD_D_WU_W */
9287
    3092,
9288
    /* VMADDWOD_H_B */
9289
    3096,
9290
    /* VMADDWOD_H_BU */
9291
    3100,
9292
    /* VMADDWOD_H_BU_B */
9293
    3104,
9294
    /* VMADDWOD_Q_D */
9295
    3108,
9296
    /* VMADDWOD_Q_DU */
9297
    3112,
9298
    /* VMADDWOD_Q_DU_D */
9299
    3116,
9300
    /* VMADDWOD_W_H */
9301
    3120,
9302
    /* VMADDWOD_W_HU */
9303
    3124,
9304
    /* VMADDWOD_W_HU_H */
9305
    3128,
9306
    /* VMADD_B */
9307
    3132,
9308
    /* VMADD_D */
9309
    3136,
9310
    /* VMADD_H */
9311
    3140,
9312
    /* VMADD_W */
9313
    3144,
9314
    /* VMAXI_B */
9315
    3148,
9316
    /* VMAXI_BU */
9317
    3151,
9318
    /* VMAXI_D */
9319
    3154,
9320
    /* VMAXI_DU */
9321
    3157,
9322
    /* VMAXI_H */
9323
    3160,
9324
    /* VMAXI_HU */
9325
    3163,
9326
    /* VMAXI_W */
9327
    3166,
9328
    /* VMAXI_WU */
9329
    3169,
9330
    /* VMAX_B */
9331
    3172,
9332
    /* VMAX_BU */
9333
    3175,
9334
    /* VMAX_D */
9335
    3178,
9336
    /* VMAX_DU */
9337
    3181,
9338
    /* VMAX_H */
9339
    3184,
9340
    /* VMAX_HU */
9341
    3187,
9342
    /* VMAX_W */
9343
    3190,
9344
    /* VMAX_WU */
9345
    3193,
9346
    /* VMINI_B */
9347
    3196,
9348
    /* VMINI_BU */
9349
    3199,
9350
    /* VMINI_D */
9351
    3202,
9352
    /* VMINI_DU */
9353
    3205,
9354
    /* VMINI_H */
9355
    3208,
9356
    /* VMINI_HU */
9357
    3211,
9358
    /* VMINI_W */
9359
    3214,
9360
    /* VMINI_WU */
9361
    3217,
9362
    /* VMIN_B */
9363
    3220,
9364
    /* VMIN_BU */
9365
    3223,
9366
    /* VMIN_D */
9367
    3226,
9368
    /* VMIN_DU */
9369
    3229,
9370
    /* VMIN_H */
9371
    3232,
9372
    /* VMIN_HU */
9373
    3235,
9374
    /* VMIN_W */
9375
    3238,
9376
    /* VMIN_WU */
9377
    3241,
9378
    /* VMOD_B */
9379
    3244,
9380
    /* VMOD_BU */
9381
    3247,
9382
    /* VMOD_D */
9383
    3250,
9384
    /* VMOD_DU */
9385
    3253,
9386
    /* VMOD_H */
9387
    3256,
9388
    /* VMOD_HU */
9389
    3259,
9390
    /* VMOD_W */
9391
    3262,
9392
    /* VMOD_WU */
9393
    3265,
9394
    /* VMSKGEZ_B */
9395
    3268,
9396
    /* VMSKLTZ_B */
9397
    3270,
9398
    /* VMSKLTZ_D */
9399
    3272,
9400
    /* VMSKLTZ_H */
9401
    3274,
9402
    /* VMSKLTZ_W */
9403
    3276,
9404
    /* VMSKNZ_B */
9405
    3278,
9406
    /* VMSUB_B */
9407
    3280,
9408
    /* VMSUB_D */
9409
    3284,
9410
    /* VMSUB_H */
9411
    3288,
9412
    /* VMSUB_W */
9413
    3292,
9414
    /* VMUH_B */
9415
    3296,
9416
    /* VMUH_BU */
9417
    3299,
9418
    /* VMUH_D */
9419
    3302,
9420
    /* VMUH_DU */
9421
    3305,
9422
    /* VMUH_H */
9423
    3308,
9424
    /* VMUH_HU */
9425
    3311,
9426
    /* VMUH_W */
9427
    3314,
9428
    /* VMUH_WU */
9429
    3317,
9430
    /* VMULWEV_D_W */
9431
    3320,
9432
    /* VMULWEV_D_WU */
9433
    3323,
9434
    /* VMULWEV_D_WU_W */
9435
    3326,
9436
    /* VMULWEV_H_B */
9437
    3329,
9438
    /* VMULWEV_H_BU */
9439
    3332,
9440
    /* VMULWEV_H_BU_B */
9441
    3335,
9442
    /* VMULWEV_Q_D */
9443
    3338,
9444
    /* VMULWEV_Q_DU */
9445
    3341,
9446
    /* VMULWEV_Q_DU_D */
9447
    3344,
9448
    /* VMULWEV_W_H */
9449
    3347,
9450
    /* VMULWEV_W_HU */
9451
    3350,
9452
    /* VMULWEV_W_HU_H */
9453
    3353,
9454
    /* VMULWOD_D_W */
9455
    3356,
9456
    /* VMULWOD_D_WU */
9457
    3359,
9458
    /* VMULWOD_D_WU_W */
9459
    3362,
9460
    /* VMULWOD_H_B */
9461
    3365,
9462
    /* VMULWOD_H_BU */
9463
    3368,
9464
    /* VMULWOD_H_BU_B */
9465
    3371,
9466
    /* VMULWOD_Q_D */
9467
    3374,
9468
    /* VMULWOD_Q_DU */
9469
    3377,
9470
    /* VMULWOD_Q_DU_D */
9471
    3380,
9472
    /* VMULWOD_W_H */
9473
    3383,
9474
    /* VMULWOD_W_HU */
9475
    3386,
9476
    /* VMULWOD_W_HU_H */
9477
    3389,
9478
    /* VMUL_B */
9479
    3392,
9480
    /* VMUL_D */
9481
    3395,
9482
    /* VMUL_H */
9483
    3398,
9484
    /* VMUL_W */
9485
    3401,
9486
    /* VNEG_B */
9487
    3404,
9488
    /* VNEG_D */
9489
    3406,
9490
    /* VNEG_H */
9491
    3408,
9492
    /* VNEG_W */
9493
    3410,
9494
    /* VNORI_B */
9495
    3412,
9496
    /* VNOR_V */
9497
    3415,
9498
    /* VORI_B */
9499
    3418,
9500
    /* VORN_V */
9501
    3421,
9502
    /* VOR_V */
9503
    3424,
9504
    /* VPACKEV_B */
9505
    3427,
9506
    /* VPACKEV_D */
9507
    3430,
9508
    /* VPACKEV_H */
9509
    3433,
9510
    /* VPACKEV_W */
9511
    3436,
9512
    /* VPACKOD_B */
9513
    3439,
9514
    /* VPACKOD_D */
9515
    3442,
9516
    /* VPACKOD_H */
9517
    3445,
9518
    /* VPACKOD_W */
9519
    3448,
9520
    /* VPCNT_B */
9521
    3451,
9522
    /* VPCNT_D */
9523
    3453,
9524
    /* VPCNT_H */
9525
    3455,
9526
    /* VPCNT_W */
9527
    3457,
9528
    /* VPERMI_W */
9529
    3459,
9530
    /* VPICKEV_B */
9531
    3463,
9532
    /* VPICKEV_D */
9533
    3466,
9534
    /* VPICKEV_H */
9535
    3469,
9536
    /* VPICKEV_W */
9537
    3472,
9538
    /* VPICKOD_B */
9539
    3475,
9540
    /* VPICKOD_D */
9541
    3478,
9542
    /* VPICKOD_H */
9543
    3481,
9544
    /* VPICKOD_W */
9545
    3484,
9546
    /* VPICKVE2GR_B */
9547
    3487,
9548
    /* VPICKVE2GR_BU */
9549
    3490,
9550
    /* VPICKVE2GR_D */
9551
    3493,
9552
    /* VPICKVE2GR_DU */
9553
    3496,
9554
    /* VPICKVE2GR_H */
9555
    3499,
9556
    /* VPICKVE2GR_HU */
9557
    3502,
9558
    /* VPICKVE2GR_W */
9559
    3505,
9560
    /* VPICKVE2GR_WU */
9561
    3508,
9562
    /* VREPLGR2VR_B */
9563
    3511,
9564
    /* VREPLGR2VR_D */
9565
    3513,
9566
    /* VREPLGR2VR_H */
9567
    3515,
9568
    /* VREPLGR2VR_W */
9569
    3517,
9570
    /* VREPLVEI_B */
9571
    3519,
9572
    /* VREPLVEI_D */
9573
    3522,
9574
    /* VREPLVEI_H */
9575
    3525,
9576
    /* VREPLVEI_W */
9577
    3528,
9578
    /* VREPLVE_B */
9579
    3531,
9580
    /* VREPLVE_D */
9581
    3534,
9582
    /* VREPLVE_H */
9583
    3537,
9584
    /* VREPLVE_W */
9585
    3540,
9586
    /* VROTRI_B */
9587
    3543,
9588
    /* VROTRI_D */
9589
    3546,
9590
    /* VROTRI_H */
9591
    3549,
9592
    /* VROTRI_W */
9593
    3552,
9594
    /* VROTR_B */
9595
    3555,
9596
    /* VROTR_D */
9597
    3558,
9598
    /* VROTR_H */
9599
    3561,
9600
    /* VROTR_W */
9601
    3564,
9602
    /* VSADD_B */
9603
    3567,
9604
    /* VSADD_BU */
9605
    3570,
9606
    /* VSADD_D */
9607
    3573,
9608
    /* VSADD_DU */
9609
    3576,
9610
    /* VSADD_H */
9611
    3579,
9612
    /* VSADD_HU */
9613
    3582,
9614
    /* VSADD_W */
9615
    3585,
9616
    /* VSADD_WU */
9617
    3588,
9618
    /* VSAT_B */
9619
    3591,
9620
    /* VSAT_BU */
9621
    3594,
9622
    /* VSAT_D */
9623
    3597,
9624
    /* VSAT_DU */
9625
    3600,
9626
    /* VSAT_H */
9627
    3603,
9628
    /* VSAT_HU */
9629
    3606,
9630
    /* VSAT_W */
9631
    3609,
9632
    /* VSAT_WU */
9633
    3612,
9634
    /* VSEQI_B */
9635
    3615,
9636
    /* VSEQI_D */
9637
    3618,
9638
    /* VSEQI_H */
9639
    3621,
9640
    /* VSEQI_W */
9641
    3624,
9642
    /* VSEQ_B */
9643
    3627,
9644
    /* VSEQ_D */
9645
    3630,
9646
    /* VSEQ_H */
9647
    3633,
9648
    /* VSEQ_W */
9649
    3636,
9650
    /* VSETALLNEZ_B */
9651
    3639,
9652
    /* VSETALLNEZ_D */
9653
    3641,
9654
    /* VSETALLNEZ_H */
9655
    3643,
9656
    /* VSETALLNEZ_W */
9657
    3645,
9658
    /* VSETANYEQZ_B */
9659
    3647,
9660
    /* VSETANYEQZ_D */
9661
    3649,
9662
    /* VSETANYEQZ_H */
9663
    3651,
9664
    /* VSETANYEQZ_W */
9665
    3653,
9666
    /* VSETEQZ_V */
9667
    3655,
9668
    /* VSETNEZ_V */
9669
    3657,
9670
    /* VSHUF4I_B */
9671
    3659,
9672
    /* VSHUF4I_D */
9673
    3662,
9674
    /* VSHUF4I_H */
9675
    3666,
9676
    /* VSHUF4I_W */
9677
    3669,
9678
    /* VSHUF_B */
9679
    3672,
9680
    /* VSHUF_D */
9681
    3676,
9682
    /* VSHUF_H */
9683
    3680,
9684
    /* VSHUF_W */
9685
    3684,
9686
    /* VSIGNCOV_B */
9687
    3688,
9688
    /* VSIGNCOV_D */
9689
    3691,
9690
    /* VSIGNCOV_H */
9691
    3694,
9692
    /* VSIGNCOV_W */
9693
    3697,
9694
    /* VSLEI_B */
9695
    3700,
9696
    /* VSLEI_BU */
9697
    3703,
9698
    /* VSLEI_D */
9699
    3706,
9700
    /* VSLEI_DU */
9701
    3709,
9702
    /* VSLEI_H */
9703
    3712,
9704
    /* VSLEI_HU */
9705
    3715,
9706
    /* VSLEI_W */
9707
    3718,
9708
    /* VSLEI_WU */
9709
    3721,
9710
    /* VSLE_B */
9711
    3724,
9712
    /* VSLE_BU */
9713
    3727,
9714
    /* VSLE_D */
9715
    3730,
9716
    /* VSLE_DU */
9717
    3733,
9718
    /* VSLE_H */
9719
    3736,
9720
    /* VSLE_HU */
9721
    3739,
9722
    /* VSLE_W */
9723
    3742,
9724
    /* VSLE_WU */
9725
    3745,
9726
    /* VSLLI_B */
9727
    3748,
9728
    /* VSLLI_D */
9729
    3751,
9730
    /* VSLLI_H */
9731
    3754,
9732
    /* VSLLI_W */
9733
    3757,
9734
    /* VSLLWIL_DU_WU */
9735
    3760,
9736
    /* VSLLWIL_D_W */
9737
    3763,
9738
    /* VSLLWIL_HU_BU */
9739
    3766,
9740
    /* VSLLWIL_H_B */
9741
    3769,
9742
    /* VSLLWIL_WU_HU */
9743
    3772,
9744
    /* VSLLWIL_W_H */
9745
    3775,
9746
    /* VSLL_B */
9747
    3778,
9748
    /* VSLL_D */
9749
    3781,
9750
    /* VSLL_H */
9751
    3784,
9752
    /* VSLL_W */
9753
    3787,
9754
    /* VSLTI_B */
9755
    3790,
9756
    /* VSLTI_BU */
9757
    3793,
9758
    /* VSLTI_D */
9759
    3796,
9760
    /* VSLTI_DU */
9761
    3799,
9762
    /* VSLTI_H */
9763
    3802,
9764
    /* VSLTI_HU */
9765
    3805,
9766
    /* VSLTI_W */
9767
    3808,
9768
    /* VSLTI_WU */
9769
    3811,
9770
    /* VSLT_B */
9771
    3814,
9772
    /* VSLT_BU */
9773
    3817,
9774
    /* VSLT_D */
9775
    3820,
9776
    /* VSLT_DU */
9777
    3823,
9778
    /* VSLT_H */
9779
    3826,
9780
    /* VSLT_HU */
9781
    3829,
9782
    /* VSLT_W */
9783
    3832,
9784
    /* VSLT_WU */
9785
    3835,
9786
    /* VSRAI_B */
9787
    3838,
9788
    /* VSRAI_D */
9789
    3841,
9790
    /* VSRAI_H */
9791
    3844,
9792
    /* VSRAI_W */
9793
    3847,
9794
    /* VSRANI_B_H */
9795
    3850,
9796
    /* VSRANI_D_Q */
9797
    3854,
9798
    /* VSRANI_H_W */
9799
    3858,
9800
    /* VSRANI_W_D */
9801
    3862,
9802
    /* VSRAN_B_H */
9803
    3866,
9804
    /* VSRAN_H_W */
9805
    3869,
9806
    /* VSRAN_W_D */
9807
    3872,
9808
    /* VSRARI_B */
9809
    3875,
9810
    /* VSRARI_D */
9811
    3878,
9812
    /* VSRARI_H */
9813
    3881,
9814
    /* VSRARI_W */
9815
    3884,
9816
    /* VSRARNI_B_H */
9817
    3887,
9818
    /* VSRARNI_D_Q */
9819
    3891,
9820
    /* VSRARNI_H_W */
9821
    3895,
9822
    /* VSRARNI_W_D */
9823
    3899,
9824
    /* VSRARN_B_H */
9825
    3903,
9826
    /* VSRARN_H_W */
9827
    3906,
9828
    /* VSRARN_W_D */
9829
    3909,
9830
    /* VSRAR_B */
9831
    3912,
9832
    /* VSRAR_D */
9833
    3915,
9834
    /* VSRAR_H */
9835
    3918,
9836
    /* VSRAR_W */
9837
    3921,
9838
    /* VSRA_B */
9839
    3924,
9840
    /* VSRA_D */
9841
    3927,
9842
    /* VSRA_H */
9843
    3930,
9844
    /* VSRA_W */
9845
    3933,
9846
    /* VSRLI_B */
9847
    3936,
9848
    /* VSRLI_D */
9849
    3939,
9850
    /* VSRLI_H */
9851
    3942,
9852
    /* VSRLI_W */
9853
    3945,
9854
    /* VSRLNI_B_H */
9855
    3948,
9856
    /* VSRLNI_D_Q */
9857
    3952,
9858
    /* VSRLNI_H_W */
9859
    3956,
9860
    /* VSRLNI_W_D */
9861
    3960,
9862
    /* VSRLN_B_H */
9863
    3964,
9864
    /* VSRLN_H_W */
9865
    3967,
9866
    /* VSRLN_W_D */
9867
    3970,
9868
    /* VSRLRI_B */
9869
    3973,
9870
    /* VSRLRI_D */
9871
    3976,
9872
    /* VSRLRI_H */
9873
    3979,
9874
    /* VSRLRI_W */
9875
    3982,
9876
    /* VSRLRNI_B_H */
9877
    3985,
9878
    /* VSRLRNI_D_Q */
9879
    3989,
9880
    /* VSRLRNI_H_W */
9881
    3993,
9882
    /* VSRLRNI_W_D */
9883
    3997,
9884
    /* VSRLRN_B_H */
9885
    4001,
9886
    /* VSRLRN_H_W */
9887
    4004,
9888
    /* VSRLRN_W_D */
9889
    4007,
9890
    /* VSRLR_B */
9891
    4010,
9892
    /* VSRLR_D */
9893
    4013,
9894
    /* VSRLR_H */
9895
    4016,
9896
    /* VSRLR_W */
9897
    4019,
9898
    /* VSRL_B */
9899
    4022,
9900
    /* VSRL_D */
9901
    4025,
9902
    /* VSRL_H */
9903
    4028,
9904
    /* VSRL_W */
9905
    4031,
9906
    /* VSSRANI_BU_H */
9907
    4034,
9908
    /* VSSRANI_B_H */
9909
    4038,
9910
    /* VSSRANI_DU_Q */
9911
    4042,
9912
    /* VSSRANI_D_Q */
9913
    4046,
9914
    /* VSSRANI_HU_W */
9915
    4050,
9916
    /* VSSRANI_H_W */
9917
    4054,
9918
    /* VSSRANI_WU_D */
9919
    4058,
9920
    /* VSSRANI_W_D */
9921
    4062,
9922
    /* VSSRAN_BU_H */
9923
    4066,
9924
    /* VSSRAN_B_H */
9925
    4069,
9926
    /* VSSRAN_HU_W */
9927
    4072,
9928
    /* VSSRAN_H_W */
9929
    4075,
9930
    /* VSSRAN_WU_D */
9931
    4078,
9932
    /* VSSRAN_W_D */
9933
    4081,
9934
    /* VSSRARNI_BU_H */
9935
    4084,
9936
    /* VSSRARNI_B_H */
9937
    4088,
9938
    /* VSSRARNI_DU_Q */
9939
    4092,
9940
    /* VSSRARNI_D_Q */
9941
    4096,
9942
    /* VSSRARNI_HU_W */
9943
    4100,
9944
    /* VSSRARNI_H_W */
9945
    4104,
9946
    /* VSSRARNI_WU_D */
9947
    4108,
9948
    /* VSSRARNI_W_D */
9949
    4112,
9950
    /* VSSRARN_BU_H */
9951
    4116,
9952
    /* VSSRARN_B_H */
9953
    4119,
9954
    /* VSSRARN_HU_W */
9955
    4122,
9956
    /* VSSRARN_H_W */
9957
    4125,
9958
    /* VSSRARN_WU_D */
9959
    4128,
9960
    /* VSSRARN_W_D */
9961
    4131,
9962
    /* VSSRLNI_BU_H */
9963
    4134,
9964
    /* VSSRLNI_B_H */
9965
    4138,
9966
    /* VSSRLNI_DU_Q */
9967
    4142,
9968
    /* VSSRLNI_D_Q */
9969
    4146,
9970
    /* VSSRLNI_HU_W */
9971
    4150,
9972
    /* VSSRLNI_H_W */
9973
    4154,
9974
    /* VSSRLNI_WU_D */
9975
    4158,
9976
    /* VSSRLNI_W_D */
9977
    4162,
9978
    /* VSSRLN_BU_H */
9979
    4166,
9980
    /* VSSRLN_B_H */
9981
    4169,
9982
    /* VSSRLN_HU_W */
9983
    4172,
9984
    /* VSSRLN_H_W */
9985
    4175,
9986
    /* VSSRLN_WU_D */
9987
    4178,
9988
    /* VSSRLN_W_D */
9989
    4181,
9990
    /* VSSRLRNI_BU_H */
9991
    4184,
9992
    /* VSSRLRNI_B_H */
9993
    4188,
9994
    /* VSSRLRNI_DU_Q */
9995
    4192,
9996
    /* VSSRLRNI_D_Q */
9997
    4196,
9998
    /* VSSRLRNI_HU_W */
9999
    4200,
10000
    /* VSSRLRNI_H_W */
10001
    4204,
10002
    /* VSSRLRNI_WU_D */
10003
    4208,
10004
    /* VSSRLRNI_W_D */
10005
    4212,
10006
    /* VSSRLRN_BU_H */
10007
    4216,
10008
    /* VSSRLRN_B_H */
10009
    4219,
10010
    /* VSSRLRN_HU_W */
10011
    4222,
10012
    /* VSSRLRN_H_W */
10013
    4225,
10014
    /* VSSRLRN_WU_D */
10015
    4228,
10016
    /* VSSRLRN_W_D */
10017
    4231,
10018
    /* VSSUB_B */
10019
    4234,
10020
    /* VSSUB_BU */
10021
    4237,
10022
    /* VSSUB_D */
10023
    4240,
10024
    /* VSSUB_DU */
10025
    4243,
10026
    /* VSSUB_H */
10027
    4246,
10028
    /* VSSUB_HU */
10029
    4249,
10030
    /* VSSUB_W */
10031
    4252,
10032
    /* VSSUB_WU */
10033
    4255,
10034
    /* VST */
10035
    4258,
10036
    /* VSTELM_B */
10037
    4261,
10038
    /* VSTELM_D */
10039
    4265,
10040
    /* VSTELM_H */
10041
    4269,
10042
    /* VSTELM_W */
10043
    4273,
10044
    /* VSTX */
10045
    4277,
10046
    /* VSUBI_BU */
10047
    4280,
10048
    /* VSUBI_DU */
10049
    4283,
10050
    /* VSUBI_HU */
10051
    4286,
10052
    /* VSUBI_WU */
10053
    4289,
10054
    /* VSUBWEV_D_W */
10055
    4292,
10056
    /* VSUBWEV_D_WU */
10057
    4295,
10058
    /* VSUBWEV_H_B */
10059
    4298,
10060
    /* VSUBWEV_H_BU */
10061
    4301,
10062
    /* VSUBWEV_Q_D */
10063
    4304,
10064
    /* VSUBWEV_Q_DU */
10065
    4307,
10066
    /* VSUBWEV_W_H */
10067
    4310,
10068
    /* VSUBWEV_W_HU */
10069
    4313,
10070
    /* VSUBWOD_D_W */
10071
    4316,
10072
    /* VSUBWOD_D_WU */
10073
    4319,
10074
    /* VSUBWOD_H_B */
10075
    4322,
10076
    /* VSUBWOD_H_BU */
10077
    4325,
10078
    /* VSUBWOD_Q_D */
10079
    4328,
10080
    /* VSUBWOD_Q_DU */
10081
    4331,
10082
    /* VSUBWOD_W_H */
10083
    4334,
10084
    /* VSUBWOD_W_HU */
10085
    4337,
10086
    /* VSUB_B */
10087
    4340,
10088
    /* VSUB_D */
10089
    4343,
10090
    /* VSUB_H */
10091
    4346,
10092
    /* VSUB_Q */
10093
    4349,
10094
    /* VSUB_W */
10095
    4352,
10096
    /* VXORI_B */
10097
    4355,
10098
    /* VXOR_V */
10099
    4358,
10100
    /* X86ADC_B */
10101
    4361,
10102
    /* X86ADC_D */
10103
    4363,
10104
    /* X86ADC_H */
10105
    4365,
10106
    /* X86ADC_W */
10107
    4367,
10108
    /* X86ADD_B */
10109
    4369,
10110
    /* X86ADD_D */
10111
    4371,
10112
    /* X86ADD_DU */
10113
    4373,
10114
    /* X86ADD_H */
10115
    4375,
10116
    /* X86ADD_W */
10117
    4377,
10118
    /* X86ADD_WU */
10119
    4379,
10120
    /* X86AND_B */
10121
    4381,
10122
    /* X86AND_D */
10123
    4383,
10124
    /* X86AND_H */
10125
    4385,
10126
    /* X86AND_W */
10127
    4387,
10128
    /* X86CLRTM */
10129
    4389,
10130
    /* X86DECTOP */
10131
    4389,
10132
    /* X86DEC_B */
10133
    4389,
10134
    /* X86DEC_D */
10135
    4390,
10136
    /* X86DEC_H */
10137
    4391,
10138
    /* X86DEC_W */
10139
    4392,
10140
    /* X86INCTOP */
10141
    4393,
10142
    /* X86INC_B */
10143
    4393,
10144
    /* X86INC_D */
10145
    4394,
10146
    /* X86INC_H */
10147
    4395,
10148
    /* X86INC_W */
10149
    4396,
10150
    /* X86MFFLAG */
10151
    4397,
10152
    /* X86MFTOP */
10153
    4399,
10154
    /* X86MTFLAG */
10155
    4400,
10156
    /* X86MTTOP */
10157
    4402,
10158
    /* X86MUL_B */
10159
    4403,
10160
    /* X86MUL_BU */
10161
    4405,
10162
    /* X86MUL_D */
10163
    4407,
10164
    /* X86MUL_DU */
10165
    4409,
10166
    /* X86MUL_H */
10167
    4411,
10168
    /* X86MUL_HU */
10169
    4413,
10170
    /* X86MUL_W */
10171
    4415,
10172
    /* X86MUL_WU */
10173
    4417,
10174
    /* X86OR_B */
10175
    4419,
10176
    /* X86OR_D */
10177
    4421,
10178
    /* X86OR_H */
10179
    4423,
10180
    /* X86OR_W */
10181
    4425,
10182
    /* X86RCLI_B */
10183
    4427,
10184
    /* X86RCLI_D */
10185
    4429,
10186
    /* X86RCLI_H */
10187
    4431,
10188
    /* X86RCLI_W */
10189
    4433,
10190
    /* X86RCL_B */
10191
    4435,
10192
    /* X86RCL_D */
10193
    4437,
10194
    /* X86RCL_H */
10195
    4439,
10196
    /* X86RCL_W */
10197
    4441,
10198
    /* X86RCRI_B */
10199
    4443,
10200
    /* X86RCRI_D */
10201
    4445,
10202
    /* X86RCRI_H */
10203
    4447,
10204
    /* X86RCRI_W */
10205
    4449,
10206
    /* X86RCR_B */
10207
    4451,
10208
    /* X86RCR_D */
10209
    4453,
10210
    /* X86RCR_H */
10211
    4455,
10212
    /* X86RCR_W */
10213
    4457,
10214
    /* X86ROTLI_B */
10215
    4459,
10216
    /* X86ROTLI_D */
10217
    4461,
10218
    /* X86ROTLI_H */
10219
    4463,
10220
    /* X86ROTLI_W */
10221
    4465,
10222
    /* X86ROTL_B */
10223
    4467,
10224
    /* X86ROTL_D */
10225
    4469,
10226
    /* X86ROTL_H */
10227
    4471,
10228
    /* X86ROTL_W */
10229
    4473,
10230
    /* X86ROTRI_B */
10231
    4475,
10232
    /* X86ROTRI_D */
10233
    4477,
10234
    /* X86ROTRI_H */
10235
    4479,
10236
    /* X86ROTRI_W */
10237
    4481,
10238
    /* X86ROTR_B */
10239
    4483,
10240
    /* X86ROTR_D */
10241
    4485,
10242
    /* X86ROTR_H */
10243
    4487,
10244
    /* X86ROTR_W */
10245
    4489,
10246
    /* X86SBC_B */
10247
    4491,
10248
    /* X86SBC_D */
10249
    4493,
10250
    /* X86SBC_H */
10251
    4495,
10252
    /* X86SBC_W */
10253
    4497,
10254
    /* X86SETTAG */
10255
    4499,
10256
    /* X86SETTM */
10257
    4502,
10258
    /* X86SLLI_B */
10259
    4502,
10260
    /* X86SLLI_D */
10261
    4504,
10262
    /* X86SLLI_H */
10263
    4506,
10264
    /* X86SLLI_W */
10265
    4508,
10266
    /* X86SLL_B */
10267
    4510,
10268
    /* X86SLL_D */
10269
    4512,
10270
    /* X86SLL_H */
10271
    4514,
10272
    /* X86SLL_W */
10273
    4516,
10274
    /* X86SRAI_B */
10275
    4518,
10276
    /* X86SRAI_D */
10277
    4520,
10278
    /* X86SRAI_H */
10279
    4522,
10280
    /* X86SRAI_W */
10281
    4524,
10282
    /* X86SRA_B */
10283
    4526,
10284
    /* X86SRA_D */
10285
    4528,
10286
    /* X86SRA_H */
10287
    4530,
10288
    /* X86SRA_W */
10289
    4532,
10290
    /* X86SRLI_B */
10291
    4534,
10292
    /* X86SRLI_D */
10293
    4536,
10294
    /* X86SRLI_H */
10295
    4538,
10296
    /* X86SRLI_W */
10297
    4540,
10298
    /* X86SRL_B */
10299
    4542,
10300
    /* X86SRL_D */
10301
    4544,
10302
    /* X86SRL_H */
10303
    4546,
10304
    /* X86SRL_W */
10305
    4548,
10306
    /* X86SUB_B */
10307
    4550,
10308
    /* X86SUB_D */
10309
    4552,
10310
    /* X86SUB_DU */
10311
    4554,
10312
    /* X86SUB_H */
10313
    4556,
10314
    /* X86SUB_W */
10315
    4558,
10316
    /* X86SUB_WU */
10317
    4560,
10318
    /* X86XOR_B */
10319
    4562,
10320
    /* X86XOR_D */
10321
    4564,
10322
    /* X86XOR_H */
10323
    4566,
10324
    /* X86XOR_W */
10325
    4568,
10326
    /* XOR */
10327
    4570,
10328
    /* XORI */
10329
    4573,
10330
    /* XVABSD_B */
10331
    4576,
10332
    /* XVABSD_BU */
10333
    4579,
10334
    /* XVABSD_D */
10335
    4582,
10336
    /* XVABSD_DU */
10337
    4585,
10338
    /* XVABSD_H */
10339
    4588,
10340
    /* XVABSD_HU */
10341
    4591,
10342
    /* XVABSD_W */
10343
    4594,
10344
    /* XVABSD_WU */
10345
    4597,
10346
    /* XVADDA_B */
10347
    4600,
10348
    /* XVADDA_D */
10349
    4603,
10350
    /* XVADDA_H */
10351
    4606,
10352
    /* XVADDA_W */
10353
    4609,
10354
    /* XVADDI_BU */
10355
    4612,
10356
    /* XVADDI_DU */
10357
    4615,
10358
    /* XVADDI_HU */
10359
    4618,
10360
    /* XVADDI_WU */
10361
    4621,
10362
    /* XVADDWEV_D_W */
10363
    4624,
10364
    /* XVADDWEV_D_WU */
10365
    4627,
10366
    /* XVADDWEV_D_WU_W */
10367
    4630,
10368
    /* XVADDWEV_H_B */
10369
    4633,
10370
    /* XVADDWEV_H_BU */
10371
    4636,
10372
    /* XVADDWEV_H_BU_B */
10373
    4639,
10374
    /* XVADDWEV_Q_D */
10375
    4642,
10376
    /* XVADDWEV_Q_DU */
10377
    4645,
10378
    /* XVADDWEV_Q_DU_D */
10379
    4648,
10380
    /* XVADDWEV_W_H */
10381
    4651,
10382
    /* XVADDWEV_W_HU */
10383
    4654,
10384
    /* XVADDWEV_W_HU_H */
10385
    4657,
10386
    /* XVADDWOD_D_W */
10387
    4660,
10388
    /* XVADDWOD_D_WU */
10389
    4663,
10390
    /* XVADDWOD_D_WU_W */
10391
    4666,
10392
    /* XVADDWOD_H_B */
10393
    4669,
10394
    /* XVADDWOD_H_BU */
10395
    4672,
10396
    /* XVADDWOD_H_BU_B */
10397
    4675,
10398
    /* XVADDWOD_Q_D */
10399
    4678,
10400
    /* XVADDWOD_Q_DU */
10401
    4681,
10402
    /* XVADDWOD_Q_DU_D */
10403
    4684,
10404
    /* XVADDWOD_W_H */
10405
    4687,
10406
    /* XVADDWOD_W_HU */
10407
    4690,
10408
    /* XVADDWOD_W_HU_H */
10409
    4693,
10410
    /* XVADD_B */
10411
    4696,
10412
    /* XVADD_D */
10413
    4699,
10414
    /* XVADD_H */
10415
    4702,
10416
    /* XVADD_Q */
10417
    4705,
10418
    /* XVADD_W */
10419
    4708,
10420
    /* XVANDI_B */
10421
    4711,
10422
    /* XVANDN_V */
10423
    4714,
10424
    /* XVAND_V */
10425
    4717,
10426
    /* XVAVGR_B */
10427
    4720,
10428
    /* XVAVGR_BU */
10429
    4723,
10430
    /* XVAVGR_D */
10431
    4726,
10432
    /* XVAVGR_DU */
10433
    4729,
10434
    /* XVAVGR_H */
10435
    4732,
10436
    /* XVAVGR_HU */
10437
    4735,
10438
    /* XVAVGR_W */
10439
    4738,
10440
    /* XVAVGR_WU */
10441
    4741,
10442
    /* XVAVG_B */
10443
    4744,
10444
    /* XVAVG_BU */
10445
    4747,
10446
    /* XVAVG_D */
10447
    4750,
10448
    /* XVAVG_DU */
10449
    4753,
10450
    /* XVAVG_H */
10451
    4756,
10452
    /* XVAVG_HU */
10453
    4759,
10454
    /* XVAVG_W */
10455
    4762,
10456
    /* XVAVG_WU */
10457
    4765,
10458
    /* XVBITCLRI_B */
10459
    4768,
10460
    /* XVBITCLRI_D */
10461
    4771,
10462
    /* XVBITCLRI_H */
10463
    4774,
10464
    /* XVBITCLRI_W */
10465
    4777,
10466
    /* XVBITCLR_B */
10467
    4780,
10468
    /* XVBITCLR_D */
10469
    4783,
10470
    /* XVBITCLR_H */
10471
    4786,
10472
    /* XVBITCLR_W */
10473
    4789,
10474
    /* XVBITREVI_B */
10475
    4792,
10476
    /* XVBITREVI_D */
10477
    4795,
10478
    /* XVBITREVI_H */
10479
    4798,
10480
    /* XVBITREVI_W */
10481
    4801,
10482
    /* XVBITREV_B */
10483
    4804,
10484
    /* XVBITREV_D */
10485
    4807,
10486
    /* XVBITREV_H */
10487
    4810,
10488
    /* XVBITREV_W */
10489
    4813,
10490
    /* XVBITSELI_B */
10491
    4816,
10492
    /* XVBITSEL_V */
10493
    4820,
10494
    /* XVBITSETI_B */
10495
    4824,
10496
    /* XVBITSETI_D */
10497
    4827,
10498
    /* XVBITSETI_H */
10499
    4830,
10500
    /* XVBITSETI_W */
10501
    4833,
10502
    /* XVBITSET_B */
10503
    4836,
10504
    /* XVBITSET_D */
10505
    4839,
10506
    /* XVBITSET_H */
10507
    4842,
10508
    /* XVBITSET_W */
10509
    4845,
10510
    /* XVBSLL_V */
10511
    4848,
10512
    /* XVBSRL_V */
10513
    4851,
10514
    /* XVCLO_B */
10515
    4854,
10516
    /* XVCLO_D */
10517
    4856,
10518
    /* XVCLO_H */
10519
    4858,
10520
    /* XVCLO_W */
10521
    4860,
10522
    /* XVCLZ_B */
10523
    4862,
10524
    /* XVCLZ_D */
10525
    4864,
10526
    /* XVCLZ_H */
10527
    4866,
10528
    /* XVCLZ_W */
10529
    4868,
10530
    /* XVDIV_B */
10531
    4870,
10532
    /* XVDIV_BU */
10533
    4873,
10534
    /* XVDIV_D */
10535
    4876,
10536
    /* XVDIV_DU */
10537
    4879,
10538
    /* XVDIV_H */
10539
    4882,
10540
    /* XVDIV_HU */
10541
    4885,
10542
    /* XVDIV_W */
10543
    4888,
10544
    /* XVDIV_WU */
10545
    4891,
10546
    /* XVEXTH_DU_WU */
10547
    4894,
10548
    /* XVEXTH_D_W */
10549
    4896,
10550
    /* XVEXTH_HU_BU */
10551
    4898,
10552
    /* XVEXTH_H_B */
10553
    4900,
10554
    /* XVEXTH_QU_DU */
10555
    4902,
10556
    /* XVEXTH_Q_D */
10557
    4904,
10558
    /* XVEXTH_WU_HU */
10559
    4906,
10560
    /* XVEXTH_W_H */
10561
    4908,
10562
    /* XVEXTL_QU_DU */
10563
    4910,
10564
    /* XVEXTL_Q_D */
10565
    4912,
10566
    /* XVEXTRINS_B */
10567
    4914,
10568
    /* XVEXTRINS_D */
10569
    4918,
10570
    /* XVEXTRINS_H */
10571
    4922,
10572
    /* XVEXTRINS_W */
10573
    4926,
10574
    /* XVFADD_D */
10575
    4930,
10576
    /* XVFADD_S */
10577
    4933,
10578
    /* XVFCLASS_D */
10579
    4936,
10580
    /* XVFCLASS_S */
10581
    4938,
10582
    /* XVFCMP_CAF_D */
10583
    4940,
10584
    /* XVFCMP_CAF_S */
10585
    4943,
10586
    /* XVFCMP_CEQ_D */
10587
    4946,
10588
    /* XVFCMP_CEQ_S */
10589
    4949,
10590
    /* XVFCMP_CLE_D */
10591
    4952,
10592
    /* XVFCMP_CLE_S */
10593
    4955,
10594
    /* XVFCMP_CLT_D */
10595
    4958,
10596
    /* XVFCMP_CLT_S */
10597
    4961,
10598
    /* XVFCMP_CNE_D */
10599
    4964,
10600
    /* XVFCMP_CNE_S */
10601
    4967,
10602
    /* XVFCMP_COR_D */
10603
    4970,
10604
    /* XVFCMP_COR_S */
10605
    4973,
10606
    /* XVFCMP_CUEQ_D */
10607
    4976,
10608
    /* XVFCMP_CUEQ_S */
10609
    4979,
10610
    /* XVFCMP_CULE_D */
10611
    4982,
10612
    /* XVFCMP_CULE_S */
10613
    4985,
10614
    /* XVFCMP_CULT_D */
10615
    4988,
10616
    /* XVFCMP_CULT_S */
10617
    4991,
10618
    /* XVFCMP_CUNE_D */
10619
    4994,
10620
    /* XVFCMP_CUNE_S */
10621
    4997,
10622
    /* XVFCMP_CUN_D */
10623
    5000,
10624
    /* XVFCMP_CUN_S */
10625
    5003,
10626
    /* XVFCMP_SAF_D */
10627
    5006,
10628
    /* XVFCMP_SAF_S */
10629
    5009,
10630
    /* XVFCMP_SEQ_D */
10631
    5012,
10632
    /* XVFCMP_SEQ_S */
10633
    5015,
10634
    /* XVFCMP_SLE_D */
10635
    5018,
10636
    /* XVFCMP_SLE_S */
10637
    5021,
10638
    /* XVFCMP_SLT_D */
10639
    5024,
10640
    /* XVFCMP_SLT_S */
10641
    5027,
10642
    /* XVFCMP_SNE_D */
10643
    5030,
10644
    /* XVFCMP_SNE_S */
10645
    5033,
10646
    /* XVFCMP_SOR_D */
10647
    5036,
10648
    /* XVFCMP_SOR_S */
10649
    5039,
10650
    /* XVFCMP_SUEQ_D */
10651
    5042,
10652
    /* XVFCMP_SUEQ_S */
10653
    5045,
10654
    /* XVFCMP_SULE_D */
10655
    5048,
10656
    /* XVFCMP_SULE_S */
10657
    5051,
10658
    /* XVFCMP_SULT_D */
10659
    5054,
10660
    /* XVFCMP_SULT_S */
10661
    5057,
10662
    /* XVFCMP_SUNE_D */
10663
    5060,
10664
    /* XVFCMP_SUNE_S */
10665
    5063,
10666
    /* XVFCMP_SUN_D */
10667
    5066,
10668
    /* XVFCMP_SUN_S */
10669
    5069,
10670
    /* XVFCVTH_D_S */
10671
    5072,
10672
    /* XVFCVTH_S_H */
10673
    5074,
10674
    /* XVFCVTL_D_S */
10675
    5076,
10676
    /* XVFCVTL_S_H */
10677
    5078,
10678
    /* XVFCVT_H_S */
10679
    5080,
10680
    /* XVFCVT_S_D */
10681
    5083,
10682
    /* XVFDIV_D */
10683
    5086,
10684
    /* XVFDIV_S */
10685
    5089,
10686
    /* XVFFINTH_D_W */
10687
    5092,
10688
    /* XVFFINTL_D_W */
10689
    5094,
10690
    /* XVFFINT_D_L */
10691
    5096,
10692
    /* XVFFINT_D_LU */
10693
    5098,
10694
    /* XVFFINT_S_L */
10695
    5100,
10696
    /* XVFFINT_S_W */
10697
    5103,
10698
    /* XVFFINT_S_WU */
10699
    5105,
10700
    /* XVFLOGB_D */
10701
    5107,
10702
    /* XVFLOGB_S */
10703
    5109,
10704
    /* XVFMADD_D */
10705
    5111,
10706
    /* XVFMADD_S */
10707
    5115,
10708
    /* XVFMAXA_D */
10709
    5119,
10710
    /* XVFMAXA_S */
10711
    5122,
10712
    /* XVFMAX_D */
10713
    5125,
10714
    /* XVFMAX_S */
10715
    5128,
10716
    /* XVFMINA_D */
10717
    5131,
10718
    /* XVFMINA_S */
10719
    5134,
10720
    /* XVFMIN_D */
10721
    5137,
10722
    /* XVFMIN_S */
10723
    5140,
10724
    /* XVFMSUB_D */
10725
    5143,
10726
    /* XVFMSUB_S */
10727
    5147,
10728
    /* XVFMUL_D */
10729
    5151,
10730
    /* XVFMUL_S */
10731
    5154,
10732
    /* XVFNMADD_D */
10733
    5157,
10734
    /* XVFNMADD_S */
10735
    5161,
10736
    /* XVFNMSUB_D */
10737
    5165,
10738
    /* XVFNMSUB_S */
10739
    5169,
10740
    /* XVFRECIPE_D */
10741
    5173,
10742
    /* XVFRECIPE_S */
10743
    5175,
10744
    /* XVFRECIP_D */
10745
    5177,
10746
    /* XVFRECIP_S */
10747
    5179,
10748
    /* XVFRINTRM_D */
10749
    5181,
10750
    /* XVFRINTRM_S */
10751
    5183,
10752
    /* XVFRINTRNE_D */
10753
    5185,
10754
    /* XVFRINTRNE_S */
10755
    5187,
10756
    /* XVFRINTRP_D */
10757
    5189,
10758
    /* XVFRINTRP_S */
10759
    5191,
10760
    /* XVFRINTRZ_D */
10761
    5193,
10762
    /* XVFRINTRZ_S */
10763
    5195,
10764
    /* XVFRINT_D */
10765
    5197,
10766
    /* XVFRINT_S */
10767
    5199,
10768
    /* XVFRSQRTE_D */
10769
    5201,
10770
    /* XVFRSQRTE_S */
10771
    5203,
10772
    /* XVFRSQRT_D */
10773
    5205,
10774
    /* XVFRSQRT_S */
10775
    5207,
10776
    /* XVFRSTPI_B */
10777
    5209,
10778
    /* XVFRSTPI_H */
10779
    5213,
10780
    /* XVFRSTP_B */
10781
    5217,
10782
    /* XVFRSTP_H */
10783
    5221,
10784
    /* XVFSQRT_D */
10785
    5225,
10786
    /* XVFSQRT_S */
10787
    5227,
10788
    /* XVFSUB_D */
10789
    5229,
10790
    /* XVFSUB_S */
10791
    5232,
10792
    /* XVFTINTH_L_S */
10793
    5235,
10794
    /* XVFTINTL_L_S */
10795
    5237,
10796
    /* XVFTINTRMH_L_S */
10797
    5239,
10798
    /* XVFTINTRML_L_S */
10799
    5241,
10800
    /* XVFTINTRM_L_D */
10801
    5243,
10802
    /* XVFTINTRM_W_D */
10803
    5245,
10804
    /* XVFTINTRM_W_S */
10805
    5248,
10806
    /* XVFTINTRNEH_L_S */
10807
    5250,
10808
    /* XVFTINTRNEL_L_S */
10809
    5252,
10810
    /* XVFTINTRNE_L_D */
10811
    5254,
10812
    /* XVFTINTRNE_W_D */
10813
    5256,
10814
    /* XVFTINTRNE_W_S */
10815
    5259,
10816
    /* XVFTINTRPH_L_S */
10817
    5261,
10818
    /* XVFTINTRPL_L_S */
10819
    5263,
10820
    /* XVFTINTRP_L_D */
10821
    5265,
10822
    /* XVFTINTRP_W_D */
10823
    5267,
10824
    /* XVFTINTRP_W_S */
10825
    5270,
10826
    /* XVFTINTRZH_L_S */
10827
    5272,
10828
    /* XVFTINTRZL_L_S */
10829
    5274,
10830
    /* XVFTINTRZ_LU_D */
10831
    5276,
10832
    /* XVFTINTRZ_L_D */
10833
    5278,
10834
    /* XVFTINTRZ_WU_S */
10835
    5280,
10836
    /* XVFTINTRZ_W_D */
10837
    5282,
10838
    /* XVFTINTRZ_W_S */
10839
    5285,
10840
    /* XVFTINT_LU_D */
10841
    5287,
10842
    /* XVFTINT_L_D */
10843
    5289,
10844
    /* XVFTINT_WU_S */
10845
    5291,
10846
    /* XVFTINT_W_D */
10847
    5293,
10848
    /* XVFTINT_W_S */
10849
    5296,
10850
    /* XVHADDW_DU_WU */
10851
    5298,
10852
    /* XVHADDW_D_W */
10853
    5301,
10854
    /* XVHADDW_HU_BU */
10855
    5304,
10856
    /* XVHADDW_H_B */
10857
    5307,
10858
    /* XVHADDW_QU_DU */
10859
    5310,
10860
    /* XVHADDW_Q_D */
10861
    5313,
10862
    /* XVHADDW_WU_HU */
10863
    5316,
10864
    /* XVHADDW_W_H */
10865
    5319,
10866
    /* XVHSELI_D */
10867
    5322,
10868
    /* XVHSUBW_DU_WU */
10869
    5325,
10870
    /* XVHSUBW_D_W */
10871
    5328,
10872
    /* XVHSUBW_HU_BU */
10873
    5331,
10874
    /* XVHSUBW_H_B */
10875
    5334,
10876
    /* XVHSUBW_QU_DU */
10877
    5337,
10878
    /* XVHSUBW_Q_D */
10879
    5340,
10880
    /* XVHSUBW_WU_HU */
10881
    5343,
10882
    /* XVHSUBW_W_H */
10883
    5346,
10884
    /* XVILVH_B */
10885
    5349,
10886
    /* XVILVH_D */
10887
    5352,
10888
    /* XVILVH_H */
10889
    5355,
10890
    /* XVILVH_W */
10891
    5358,
10892
    /* XVILVL_B */
10893
    5361,
10894
    /* XVILVL_D */
10895
    5364,
10896
    /* XVILVL_H */
10897
    5367,
10898
    /* XVILVL_W */
10899
    5370,
10900
    /* XVINSGR2VR_D */
10901
    5373,
10902
    /* XVINSGR2VR_W */
10903
    5377,
10904
    /* XVINSVE0_D */
10905
    5381,
10906
    /* XVINSVE0_W */
10907
    5385,
10908
    /* XVLD */
10909
    5389,
10910
    /* XVLDI */
10911
    5392,
10912
    /* XVLDREPL_B */
10913
    5394,
10914
    /* XVLDREPL_D */
10915
    5397,
10916
    /* XVLDREPL_H */
10917
    5400,
10918
    /* XVLDREPL_W */
10919
    5403,
10920
    /* XVLDX */
10921
    5406,
10922
    /* XVMADDWEV_D_W */
10923
    5409,
10924
    /* XVMADDWEV_D_WU */
10925
    5413,
10926
    /* XVMADDWEV_D_WU_W */
10927
    5417,
10928
    /* XVMADDWEV_H_B */
10929
    5421,
10930
    /* XVMADDWEV_H_BU */
10931
    5425,
10932
    /* XVMADDWEV_H_BU_B */
10933
    5429,
10934
    /* XVMADDWEV_Q_D */
10935
    5433,
10936
    /* XVMADDWEV_Q_DU */
10937
    5437,
10938
    /* XVMADDWEV_Q_DU_D */
10939
    5441,
10940
    /* XVMADDWEV_W_H */
10941
    5445,
10942
    /* XVMADDWEV_W_HU */
10943
    5449,
10944
    /* XVMADDWEV_W_HU_H */
10945
    5453,
10946
    /* XVMADDWOD_D_W */
10947
    5457,
10948
    /* XVMADDWOD_D_WU */
10949
    5461,
10950
    /* XVMADDWOD_D_WU_W */
10951
    5465,
10952
    /* XVMADDWOD_H_B */
10953
    5469,
10954
    /* XVMADDWOD_H_BU */
10955
    5473,
10956
    /* XVMADDWOD_H_BU_B */
10957
    5477,
10958
    /* XVMADDWOD_Q_D */
10959
    5481,
10960
    /* XVMADDWOD_Q_DU */
10961
    5485,
10962
    /* XVMADDWOD_Q_DU_D */
10963
    5489,
10964
    /* XVMADDWOD_W_H */
10965
    5493,
10966
    /* XVMADDWOD_W_HU */
10967
    5497,
10968
    /* XVMADDWOD_W_HU_H */
10969
    5501,
10970
    /* XVMADD_B */
10971
    5505,
10972
    /* XVMADD_D */
10973
    5509,
10974
    /* XVMADD_H */
10975
    5513,
10976
    /* XVMADD_W */
10977
    5517,
10978
    /* XVMAXI_B */
10979
    5521,
10980
    /* XVMAXI_BU */
10981
    5524,
10982
    /* XVMAXI_D */
10983
    5527,
10984
    /* XVMAXI_DU */
10985
    5530,
10986
    /* XVMAXI_H */
10987
    5533,
10988
    /* XVMAXI_HU */
10989
    5536,
10990
    /* XVMAXI_W */
10991
    5539,
10992
    /* XVMAXI_WU */
10993
    5542,
10994
    /* XVMAX_B */
10995
    5545,
10996
    /* XVMAX_BU */
10997
    5548,
10998
    /* XVMAX_D */
10999
    5551,
11000
    /* XVMAX_DU */
11001
    5554,
11002
    /* XVMAX_H */
11003
    5557,
11004
    /* XVMAX_HU */
11005
    5560,
11006
    /* XVMAX_W */
11007
    5563,
11008
    /* XVMAX_WU */
11009
    5566,
11010
    /* XVMINI_B */
11011
    5569,
11012
    /* XVMINI_BU */
11013
    5572,
11014
    /* XVMINI_D */
11015
    5575,
11016
    /* XVMINI_DU */
11017
    5578,
11018
    /* XVMINI_H */
11019
    5581,
11020
    /* XVMINI_HU */
11021
    5584,
11022
    /* XVMINI_W */
11023
    5587,
11024
    /* XVMINI_WU */
11025
    5590,
11026
    /* XVMIN_B */
11027
    5593,
11028
    /* XVMIN_BU */
11029
    5596,
11030
    /* XVMIN_D */
11031
    5599,
11032
    /* XVMIN_DU */
11033
    5602,
11034
    /* XVMIN_H */
11035
    5605,
11036
    /* XVMIN_HU */
11037
    5608,
11038
    /* XVMIN_W */
11039
    5611,
11040
    /* XVMIN_WU */
11041
    5614,
11042
    /* XVMOD_B */
11043
    5617,
11044
    /* XVMOD_BU */
11045
    5620,
11046
    /* XVMOD_D */
11047
    5623,
11048
    /* XVMOD_DU */
11049
    5626,
11050
    /* XVMOD_H */
11051
    5629,
11052
    /* XVMOD_HU */
11053
    5632,
11054
    /* XVMOD_W */
11055
    5635,
11056
    /* XVMOD_WU */
11057
    5638,
11058
    /* XVMSKGEZ_B */
11059
    5641,
11060
    /* XVMSKLTZ_B */
11061
    5643,
11062
    /* XVMSKLTZ_D */
11063
    5645,
11064
    /* XVMSKLTZ_H */
11065
    5647,
11066
    /* XVMSKLTZ_W */
11067
    5649,
11068
    /* XVMSKNZ_B */
11069
    5651,
11070
    /* XVMSUB_B */
11071
    5653,
11072
    /* XVMSUB_D */
11073
    5657,
11074
    /* XVMSUB_H */
11075
    5661,
11076
    /* XVMSUB_W */
11077
    5665,
11078
    /* XVMUH_B */
11079
    5669,
11080
    /* XVMUH_BU */
11081
    5672,
11082
    /* XVMUH_D */
11083
    5675,
11084
    /* XVMUH_DU */
11085
    5678,
11086
    /* XVMUH_H */
11087
    5681,
11088
    /* XVMUH_HU */
11089
    5684,
11090
    /* XVMUH_W */
11091
    5687,
11092
    /* XVMUH_WU */
11093
    5690,
11094
    /* XVMULWEV_D_W */
11095
    5693,
11096
    /* XVMULWEV_D_WU */
11097
    5696,
11098
    /* XVMULWEV_D_WU_W */
11099
    5699,
11100
    /* XVMULWEV_H_B */
11101
    5702,
11102
    /* XVMULWEV_H_BU */
11103
    5705,
11104
    /* XVMULWEV_H_BU_B */
11105
    5708,
11106
    /* XVMULWEV_Q_D */
11107
    5711,
11108
    /* XVMULWEV_Q_DU */
11109
    5714,
11110
    /* XVMULWEV_Q_DU_D */
11111
    5717,
11112
    /* XVMULWEV_W_H */
11113
    5720,
11114
    /* XVMULWEV_W_HU */
11115
    5723,
11116
    /* XVMULWEV_W_HU_H */
11117
    5726,
11118
    /* XVMULWOD_D_W */
11119
    5729,
11120
    /* XVMULWOD_D_WU */
11121
    5732,
11122
    /* XVMULWOD_D_WU_W */
11123
    5735,
11124
    /* XVMULWOD_H_B */
11125
    5738,
11126
    /* XVMULWOD_H_BU */
11127
    5741,
11128
    /* XVMULWOD_H_BU_B */
11129
    5744,
11130
    /* XVMULWOD_Q_D */
11131
    5747,
11132
    /* XVMULWOD_Q_DU */
11133
    5750,
11134
    /* XVMULWOD_Q_DU_D */
11135
    5753,
11136
    /* XVMULWOD_W_H */
11137
    5756,
11138
    /* XVMULWOD_W_HU */
11139
    5759,
11140
    /* XVMULWOD_W_HU_H */
11141
    5762,
11142
    /* XVMUL_B */
11143
    5765,
11144
    /* XVMUL_D */
11145
    5768,
11146
    /* XVMUL_H */
11147
    5771,
11148
    /* XVMUL_W */
11149
    5774,
11150
    /* XVNEG_B */
11151
    5777,
11152
    /* XVNEG_D */
11153
    5779,
11154
    /* XVNEG_H */
11155
    5781,
11156
    /* XVNEG_W */
11157
    5783,
11158
    /* XVNORI_B */
11159
    5785,
11160
    /* XVNOR_V */
11161
    5788,
11162
    /* XVORI_B */
11163
    5791,
11164
    /* XVORN_V */
11165
    5794,
11166
    /* XVOR_V */
11167
    5797,
11168
    /* XVPACKEV_B */
11169
    5800,
11170
    /* XVPACKEV_D */
11171
    5803,
11172
    /* XVPACKEV_H */
11173
    5806,
11174
    /* XVPACKEV_W */
11175
    5809,
11176
    /* XVPACKOD_B */
11177
    5812,
11178
    /* XVPACKOD_D */
11179
    5815,
11180
    /* XVPACKOD_H */
11181
    5818,
11182
    /* XVPACKOD_W */
11183
    5821,
11184
    /* XVPCNT_B */
11185
    5824,
11186
    /* XVPCNT_D */
11187
    5826,
11188
    /* XVPCNT_H */
11189
    5828,
11190
    /* XVPCNT_W */
11191
    5830,
11192
    /* XVPERMI_D */
11193
    5832,
11194
    /* XVPERMI_Q */
11195
    5835,
11196
    /* XVPERMI_W */
11197
    5839,
11198
    /* XVPERM_W */
11199
    5843,
11200
    /* XVPICKEV_B */
11201
    5846,
11202
    /* XVPICKEV_D */
11203
    5849,
11204
    /* XVPICKEV_H */
11205
    5852,
11206
    /* XVPICKEV_W */
11207
    5855,
11208
    /* XVPICKOD_B */
11209
    5858,
11210
    /* XVPICKOD_D */
11211
    5861,
11212
    /* XVPICKOD_H */
11213
    5864,
11214
    /* XVPICKOD_W */
11215
    5867,
11216
    /* XVPICKVE2GR_D */
11217
    5870,
11218
    /* XVPICKVE2GR_DU */
11219
    5873,
11220
    /* XVPICKVE2GR_W */
11221
    5876,
11222
    /* XVPICKVE2GR_WU */
11223
    5879,
11224
    /* XVPICKVE_D */
11225
    5882,
11226
    /* XVPICKVE_W */
11227
    5885,
11228
    /* XVREPL128VEI_B */
11229
    5888,
11230
    /* XVREPL128VEI_D */
11231
    5891,
11232
    /* XVREPL128VEI_H */
11233
    5894,
11234
    /* XVREPL128VEI_W */
11235
    5897,
11236
    /* XVREPLGR2VR_B */
11237
    5900,
11238
    /* XVREPLGR2VR_D */
11239
    5902,
11240
    /* XVREPLGR2VR_H */
11241
    5904,
11242
    /* XVREPLGR2VR_W */
11243
    5906,
11244
    /* XVREPLVE0_B */
11245
    5908,
11246
    /* XVREPLVE0_D */
11247
    5910,
11248
    /* XVREPLVE0_H */
11249
    5912,
11250
    /* XVREPLVE0_Q */
11251
    5914,
11252
    /* XVREPLVE0_W */
11253
    5916,
11254
    /* XVREPLVE_B */
11255
    5918,
11256
    /* XVREPLVE_D */
11257
    5921,
11258
    /* XVREPLVE_H */
11259
    5924,
11260
    /* XVREPLVE_W */
11261
    5927,
11262
    /* XVROTRI_B */
11263
    5930,
11264
    /* XVROTRI_D */
11265
    5933,
11266
    /* XVROTRI_H */
11267
    5936,
11268
    /* XVROTRI_W */
11269
    5939,
11270
    /* XVROTR_B */
11271
    5942,
11272
    /* XVROTR_D */
11273
    5945,
11274
    /* XVROTR_H */
11275
    5948,
11276
    /* XVROTR_W */
11277
    5951,
11278
    /* XVSADD_B */
11279
    5954,
11280
    /* XVSADD_BU */
11281
    5957,
11282
    /* XVSADD_D */
11283
    5960,
11284
    /* XVSADD_DU */
11285
    5963,
11286
    /* XVSADD_H */
11287
    5966,
11288
    /* XVSADD_HU */
11289
    5969,
11290
    /* XVSADD_W */
11291
    5972,
11292
    /* XVSADD_WU */
11293
    5975,
11294
    /* XVSAT_B */
11295
    5978,
11296
    /* XVSAT_BU */
11297
    5981,
11298
    /* XVSAT_D */
11299
    5984,
11300
    /* XVSAT_DU */
11301
    5987,
11302
    /* XVSAT_H */
11303
    5990,
11304
    /* XVSAT_HU */
11305
    5993,
11306
    /* XVSAT_W */
11307
    5996,
11308
    /* XVSAT_WU */
11309
    5999,
11310
    /* XVSEQI_B */
11311
    6002,
11312
    /* XVSEQI_D */
11313
    6005,
11314
    /* XVSEQI_H */
11315
    6008,
11316
    /* XVSEQI_W */
11317
    6011,
11318
    /* XVSEQ_B */
11319
    6014,
11320
    /* XVSEQ_D */
11321
    6017,
11322
    /* XVSEQ_H */
11323
    6020,
11324
    /* XVSEQ_W */
11325
    6023,
11326
    /* XVSETALLNEZ_B */
11327
    6026,
11328
    /* XVSETALLNEZ_D */
11329
    6028,
11330
    /* XVSETALLNEZ_H */
11331
    6030,
11332
    /* XVSETALLNEZ_W */
11333
    6032,
11334
    /* XVSETANYEQZ_B */
11335
    6034,
11336
    /* XVSETANYEQZ_D */
11337
    6036,
11338
    /* XVSETANYEQZ_H */
11339
    6038,
11340
    /* XVSETANYEQZ_W */
11341
    6040,
11342
    /* XVSETEQZ_V */
11343
    6042,
11344
    /* XVSETNEZ_V */
11345
    6044,
11346
    /* XVSHUF4I_B */
11347
    6046,
11348
    /* XVSHUF4I_D */
11349
    6049,
11350
    /* XVSHUF4I_H */
11351
    6053,
11352
    /* XVSHUF4I_W */
11353
    6056,
11354
    /* XVSHUF_B */
11355
    6059,
11356
    /* XVSHUF_D */
11357
    6063,
11358
    /* XVSHUF_H */
11359
    6067,
11360
    /* XVSHUF_W */
11361
    6071,
11362
    /* XVSIGNCOV_B */
11363
    6075,
11364
    /* XVSIGNCOV_D */
11365
    6078,
11366
    /* XVSIGNCOV_H */
11367
    6081,
11368
    /* XVSIGNCOV_W */
11369
    6084,
11370
    /* XVSLEI_B */
11371
    6087,
11372
    /* XVSLEI_BU */
11373
    6090,
11374
    /* XVSLEI_D */
11375
    6093,
11376
    /* XVSLEI_DU */
11377
    6096,
11378
    /* XVSLEI_H */
11379
    6099,
11380
    /* XVSLEI_HU */
11381
    6102,
11382
    /* XVSLEI_W */
11383
    6105,
11384
    /* XVSLEI_WU */
11385
    6108,
11386
    /* XVSLE_B */
11387
    6111,
11388
    /* XVSLE_BU */
11389
    6114,
11390
    /* XVSLE_D */
11391
    6117,
11392
    /* XVSLE_DU */
11393
    6120,
11394
    /* XVSLE_H */
11395
    6123,
11396
    /* XVSLE_HU */
11397
    6126,
11398
    /* XVSLE_W */
11399
    6129,
11400
    /* XVSLE_WU */
11401
    6132,
11402
    /* XVSLLI_B */
11403
    6135,
11404
    /* XVSLLI_D */
11405
    6138,
11406
    /* XVSLLI_H */
11407
    6141,
11408
    /* XVSLLI_W */
11409
    6144,
11410
    /* XVSLLWIL_DU_WU */
11411
    6147,
11412
    /* XVSLLWIL_D_W */
11413
    6150,
11414
    /* XVSLLWIL_HU_BU */
11415
    6153,
11416
    /* XVSLLWIL_H_B */
11417
    6156,
11418
    /* XVSLLWIL_WU_HU */
11419
    6159,
11420
    /* XVSLLWIL_W_H */
11421
    6162,
11422
    /* XVSLL_B */
11423
    6165,
11424
    /* XVSLL_D */
11425
    6168,
11426
    /* XVSLL_H */
11427
    6171,
11428
    /* XVSLL_W */
11429
    6174,
11430
    /* XVSLTI_B */
11431
    6177,
11432
    /* XVSLTI_BU */
11433
    6180,
11434
    /* XVSLTI_D */
11435
    6183,
11436
    /* XVSLTI_DU */
11437
    6186,
11438
    /* XVSLTI_H */
11439
    6189,
11440
    /* XVSLTI_HU */
11441
    6192,
11442
    /* XVSLTI_W */
11443
    6195,
11444
    /* XVSLTI_WU */
11445
    6198,
11446
    /* XVSLT_B */
11447
    6201,
11448
    /* XVSLT_BU */
11449
    6204,
11450
    /* XVSLT_D */
11451
    6207,
11452
    /* XVSLT_DU */
11453
    6210,
11454
    /* XVSLT_H */
11455
    6213,
11456
    /* XVSLT_HU */
11457
    6216,
11458
    /* XVSLT_W */
11459
    6219,
11460
    /* XVSLT_WU */
11461
    6222,
11462
    /* XVSRAI_B */
11463
    6225,
11464
    /* XVSRAI_D */
11465
    6228,
11466
    /* XVSRAI_H */
11467
    6231,
11468
    /* XVSRAI_W */
11469
    6234,
11470
    /* XVSRANI_B_H */
11471
    6237,
11472
    /* XVSRANI_D_Q */
11473
    6241,
11474
    /* XVSRANI_H_W */
11475
    6245,
11476
    /* XVSRANI_W_D */
11477
    6249,
11478
    /* XVSRAN_B_H */
11479
    6253,
11480
    /* XVSRAN_H_W */
11481
    6256,
11482
    /* XVSRAN_W_D */
11483
    6259,
11484
    /* XVSRARI_B */
11485
    6262,
11486
    /* XVSRARI_D */
11487
    6265,
11488
    /* XVSRARI_H */
11489
    6268,
11490
    /* XVSRARI_W */
11491
    6271,
11492
    /* XVSRARNI_B_H */
11493
    6274,
11494
    /* XVSRARNI_D_Q */
11495
    6278,
11496
    /* XVSRARNI_H_W */
11497
    6282,
11498
    /* XVSRARNI_W_D */
11499
    6286,
11500
    /* XVSRARN_B_H */
11501
    6290,
11502
    /* XVSRARN_H_W */
11503
    6293,
11504
    /* XVSRARN_W_D */
11505
    6296,
11506
    /* XVSRAR_B */
11507
    6299,
11508
    /* XVSRAR_D */
11509
    6302,
11510
    /* XVSRAR_H */
11511
    6305,
11512
    /* XVSRAR_W */
11513
    6308,
11514
    /* XVSRA_B */
11515
    6311,
11516
    /* XVSRA_D */
11517
    6314,
11518
    /* XVSRA_H */
11519
    6317,
11520
    /* XVSRA_W */
11521
    6320,
11522
    /* XVSRLI_B */
11523
    6323,
11524
    /* XVSRLI_D */
11525
    6326,
11526
    /* XVSRLI_H */
11527
    6329,
11528
    /* XVSRLI_W */
11529
    6332,
11530
    /* XVSRLNI_B_H */
11531
    6335,
11532
    /* XVSRLNI_D_Q */
11533
    6339,
11534
    /* XVSRLNI_H_W */
11535
    6343,
11536
    /* XVSRLNI_W_D */
11537
    6347,
11538
    /* XVSRLN_B_H */
11539
    6351,
11540
    /* XVSRLN_H_W */
11541
    6354,
11542
    /* XVSRLN_W_D */
11543
    6357,
11544
    /* XVSRLRI_B */
11545
    6360,
11546
    /* XVSRLRI_D */
11547
    6363,
11548
    /* XVSRLRI_H */
11549
    6366,
11550
    /* XVSRLRI_W */
11551
    6369,
11552
    /* XVSRLRNI_B_H */
11553
    6372,
11554
    /* XVSRLRNI_D_Q */
11555
    6376,
11556
    /* XVSRLRNI_H_W */
11557
    6380,
11558
    /* XVSRLRNI_W_D */
11559
    6384,
11560
    /* XVSRLRN_B_H */
11561
    6388,
11562
    /* XVSRLRN_H_W */
11563
    6391,
11564
    /* XVSRLRN_W_D */
11565
    6394,
11566
    /* XVSRLR_B */
11567
    6397,
11568
    /* XVSRLR_D */
11569
    6400,
11570
    /* XVSRLR_H */
11571
    6403,
11572
    /* XVSRLR_W */
11573
    6406,
11574
    /* XVSRL_B */
11575
    6409,
11576
    /* XVSRL_D */
11577
    6412,
11578
    /* XVSRL_H */
11579
    6415,
11580
    /* XVSRL_W */
11581
    6418,
11582
    /* XVSSRANI_BU_H */
11583
    6421,
11584
    /* XVSSRANI_B_H */
11585
    6425,
11586
    /* XVSSRANI_DU_Q */
11587
    6429,
11588
    /* XVSSRANI_D_Q */
11589
    6433,
11590
    /* XVSSRANI_HU_W */
11591
    6437,
11592
    /* XVSSRANI_H_W */
11593
    6441,
11594
    /* XVSSRANI_WU_D */
11595
    6445,
11596
    /* XVSSRANI_W_D */
11597
    6449,
11598
    /* XVSSRAN_BU_H */
11599
    6453,
11600
    /* XVSSRAN_B_H */
11601
    6456,
11602
    /* XVSSRAN_HU_W */
11603
    6459,
11604
    /* XVSSRAN_H_W */
11605
    6462,
11606
    /* XVSSRAN_WU_D */
11607
    6465,
11608
    /* XVSSRAN_W_D */
11609
    6468,
11610
    /* XVSSRARNI_BU_H */
11611
    6471,
11612
    /* XVSSRARNI_B_H */
11613
    6475,
11614
    /* XVSSRARNI_DU_Q */
11615
    6479,
11616
    /* XVSSRARNI_D_Q */
11617
    6483,
11618
    /* XVSSRARNI_HU_W */
11619
    6487,
11620
    /* XVSSRARNI_H_W */
11621
    6491,
11622
    /* XVSSRARNI_WU_D */
11623
    6495,
11624
    /* XVSSRARNI_W_D */
11625
    6499,
11626
    /* XVSSRARN_BU_H */
11627
    6503,
11628
    /* XVSSRARN_B_H */
11629
    6506,
11630
    /* XVSSRARN_HU_W */
11631
    6509,
11632
    /* XVSSRARN_H_W */
11633
    6512,
11634
    /* XVSSRARN_WU_D */
11635
    6515,
11636
    /* XVSSRARN_W_D */
11637
    6518,
11638
    /* XVSSRLNI_BU_H */
11639
    6521,
11640
    /* XVSSRLNI_B_H */
11641
    6525,
11642
    /* XVSSRLNI_DU_Q */
11643
    6529,
11644
    /* XVSSRLNI_D_Q */
11645
    6533,
11646
    /* XVSSRLNI_HU_W */
11647
    6537,
11648
    /* XVSSRLNI_H_W */
11649
    6541,
11650
    /* XVSSRLNI_WU_D */
11651
    6545,
11652
    /* XVSSRLNI_W_D */
11653
    6549,
11654
    /* XVSSRLN_BU_H */
11655
    6553,
11656
    /* XVSSRLN_B_H */
11657
    6556,
11658
    /* XVSSRLN_HU_W */
11659
    6559,
11660
    /* XVSSRLN_H_W */
11661
    6562,
11662
    /* XVSSRLN_WU_D */
11663
    6565,
11664
    /* XVSSRLN_W_D */
11665
    6568,
11666
    /* XVSSRLRNI_BU_H */
11667
    6571,
11668
    /* XVSSRLRNI_B_H */
11669
    6575,
11670
    /* XVSSRLRNI_DU_Q */
11671
    6579,
11672
    /* XVSSRLRNI_D_Q */
11673
    6583,
11674
    /* XVSSRLRNI_HU_W */
11675
    6587,
11676
    /* XVSSRLRNI_H_W */
11677
    6591,
11678
    /* XVSSRLRNI_WU_D */
11679
    6595,
11680
    /* XVSSRLRNI_W_D */
11681
    6599,
11682
    /* XVSSRLRN_BU_H */
11683
    6603,
11684
    /* XVSSRLRN_B_H */
11685
    6606,
11686
    /* XVSSRLRN_HU_W */
11687
    6609,
11688
    /* XVSSRLRN_H_W */
11689
    6612,
11690
    /* XVSSRLRN_WU_D */
11691
    6615,
11692
    /* XVSSRLRN_W_D */
11693
    6618,
11694
    /* XVSSUB_B */
11695
    6621,
11696
    /* XVSSUB_BU */
11697
    6624,
11698
    /* XVSSUB_D */
11699
    6627,
11700
    /* XVSSUB_DU */
11701
    6630,
11702
    /* XVSSUB_H */
11703
    6633,
11704
    /* XVSSUB_HU */
11705
    6636,
11706
    /* XVSSUB_W */
11707
    6639,
11708
    /* XVSSUB_WU */
11709
    6642,
11710
    /* XVST */
11711
    6645,
11712
    /* XVSTELM_B */
11713
    6648,
11714
    /* XVSTELM_D */
11715
    6652,
11716
    /* XVSTELM_H */
11717
    6656,
11718
    /* XVSTELM_W */
11719
    6660,
11720
    /* XVSTX */
11721
    6664,
11722
    /* XVSUBI_BU */
11723
    6667,
11724
    /* XVSUBI_DU */
11725
    6670,
11726
    /* XVSUBI_HU */
11727
    6673,
11728
    /* XVSUBI_WU */
11729
    6676,
11730
    /* XVSUBWEV_D_W */
11731
    6679,
11732
    /* XVSUBWEV_D_WU */
11733
    6682,
11734
    /* XVSUBWEV_H_B */
11735
    6685,
11736
    /* XVSUBWEV_H_BU */
11737
    6688,
11738
    /* XVSUBWEV_Q_D */
11739
    6691,
11740
    /* XVSUBWEV_Q_DU */
11741
    6694,
11742
    /* XVSUBWEV_W_H */
11743
    6697,
11744
    /* XVSUBWEV_W_HU */
11745
    6700,
11746
    /* XVSUBWOD_D_W */
11747
    6703,
11748
    /* XVSUBWOD_D_WU */
11749
    6706,
11750
    /* XVSUBWOD_H_B */
11751
    6709,
11752
    /* XVSUBWOD_H_BU */
11753
    6712,
11754
    /* XVSUBWOD_Q_D */
11755
    6715,
11756
    /* XVSUBWOD_Q_DU */
11757
    6718,
11758
    /* XVSUBWOD_W_H */
11759
    6721,
11760
    /* XVSUBWOD_W_HU */
11761
    6724,
11762
    /* XVSUB_B */
11763
    6727,
11764
    /* XVSUB_D */
11765
    6730,
11766
    /* XVSUB_H */
11767
    6733,
11768
    /* XVSUB_Q */
11769
    6736,
11770
    /* XVSUB_W */
11771
    6739,
11772
    /* XVXORI_B */
11773
    6742,
11774
    /* XVXOR_V */
11775
    6745,
11776
  };
11777
11778
  using namespace OpTypes;
11779
  static const int8_t OpcodeOperandTypes[] = {
11780
    
11781
    /* PHI */
11782
    -1, 
11783
    /* INLINEASM */
11784
    /* INLINEASM_BR */
11785
    /* CFI_INSTRUCTION */
11786
    i32imm, 
11787
    /* EH_LABEL */
11788
    i32imm, 
11789
    /* GC_LABEL */
11790
    i32imm, 
11791
    /* ANNOTATION_LABEL */
11792
    i32imm, 
11793
    /* KILL */
11794
    /* EXTRACT_SUBREG */
11795
    -1, -1, i32imm, 
11796
    /* INSERT_SUBREG */
11797
    -1, -1, -1, i32imm, 
11798
    /* IMPLICIT_DEF */
11799
    -1, 
11800
    /* SUBREG_TO_REG */
11801
    -1, -1, -1, i32imm, 
11802
    /* COPY_TO_REGCLASS */
11803
    -1, -1, i32imm, 
11804
    /* DBG_VALUE */
11805
    /* DBG_VALUE_LIST */
11806
    /* DBG_INSTR_REF */
11807
    /* DBG_PHI */
11808
    /* DBG_LABEL */
11809
    -1, 
11810
    /* REG_SEQUENCE */
11811
    -1, -1, 
11812
    /* COPY */
11813
    -1, -1, 
11814
    /* BUNDLE */
11815
    /* LIFETIME_START */
11816
    i32imm, 
11817
    /* LIFETIME_END */
11818
    i32imm, 
11819
    /* PSEUDO_PROBE */
11820
    i64imm, i64imm, i8imm, i32imm, 
11821
    /* ARITH_FENCE */
11822
    -1, -1, 
11823
    /* STACKMAP */
11824
    i64imm, i32imm, 
11825
    /* FENTRY_CALL */
11826
    /* PATCHPOINT */
11827
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
11828
    /* LOAD_STACK_GUARD */
11829
    -1, 
11830
    /* PREALLOCATED_SETUP */
11831
    i32imm, 
11832
    /* PREALLOCATED_ARG */
11833
    -1, i32imm, i32imm, 
11834
    /* STATEPOINT */
11835
    /* LOCAL_ESCAPE */
11836
    -1, i32imm, 
11837
    /* FAULTING_OP */
11838
    -1, 
11839
    /* PATCHABLE_OP */
11840
    /* PATCHABLE_FUNCTION_ENTER */
11841
    /* PATCHABLE_RET */
11842
    /* PATCHABLE_FUNCTION_EXIT */
11843
    /* PATCHABLE_TAIL_CALL */
11844
    /* PATCHABLE_EVENT_CALL */
11845
    -1, -1, 
11846
    /* PATCHABLE_TYPED_EVENT_CALL */
11847
    -1, -1, -1, 
11848
    /* ICALL_BRANCH_FUNNEL */
11849
    /* MEMBARRIER */
11850
    /* JUMP_TABLE_DEBUG_INFO */
11851
    i64imm, 
11852
    /* G_ASSERT_SEXT */
11853
    type0, type0, untyped_imm_0, 
11854
    /* G_ASSERT_ZEXT */
11855
    type0, type0, untyped_imm_0, 
11856
    /* G_ASSERT_ALIGN */
11857
    type0, type0, untyped_imm_0, 
11858
    /* G_ADD */
11859
    type0, type0, type0, 
11860
    /* G_SUB */
11861
    type0, type0, type0, 
11862
    /* G_MUL */
11863
    type0, type0, type0, 
11864
    /* G_SDIV */
11865
    type0, type0, type0, 
11866
    /* G_UDIV */
11867
    type0, type0, type0, 
11868
    /* G_SREM */
11869
    type0, type0, type0, 
11870
    /* G_UREM */
11871
    type0, type0, type0, 
11872
    /* G_SDIVREM */
11873
    type0, type0, type0, type0, 
11874
    /* G_UDIVREM */
11875
    type0, type0, type0, type0, 
11876
    /* G_AND */
11877
    type0, type0, type0, 
11878
    /* G_OR */
11879
    type0, type0, type0, 
11880
    /* G_XOR */
11881
    type0, type0, type0, 
11882
    /* G_IMPLICIT_DEF */
11883
    type0, 
11884
    /* G_PHI */
11885
    type0, 
11886
    /* G_FRAME_INDEX */
11887
    type0, -1, 
11888
    /* G_GLOBAL_VALUE */
11889
    type0, -1, 
11890
    /* G_CONSTANT_POOL */
11891
    type0, -1, 
11892
    /* G_EXTRACT */
11893
    type0, type1, untyped_imm_0, 
11894
    /* G_UNMERGE_VALUES */
11895
    type0, type1, 
11896
    /* G_INSERT */
11897
    type0, type0, type1, untyped_imm_0, 
11898
    /* G_MERGE_VALUES */
11899
    type0, type1, 
11900
    /* G_BUILD_VECTOR */
11901
    type0, type1, 
11902
    /* G_BUILD_VECTOR_TRUNC */
11903
    type0, type1, 
11904
    /* G_CONCAT_VECTORS */
11905
    type0, type1, 
11906
    /* G_PTRTOINT */
11907
    type0, type1, 
11908
    /* G_INTTOPTR */
11909
    type0, type1, 
11910
    /* G_BITCAST */
11911
    type0, type1, 
11912
    /* G_FREEZE */
11913
    type0, type0, 
11914
    /* G_CONSTANT_FOLD_BARRIER */
11915
    type0, type0, 
11916
    /* G_INTRINSIC_FPTRUNC_ROUND */
11917
    type0, type1, i32imm, 
11918
    /* G_INTRINSIC_TRUNC */
11919
    type0, type0, 
11920
    /* G_INTRINSIC_ROUND */
11921
    type0, type0, 
11922
    /* G_INTRINSIC_LRINT */
11923
    type0, type1, 
11924
    /* G_INTRINSIC_ROUNDEVEN */
11925
    type0, type0, 
11926
    /* G_READCYCLECOUNTER */
11927
    type0, 
11928
    /* G_LOAD */
11929
    type0, ptype1, 
11930
    /* G_SEXTLOAD */
11931
    type0, ptype1, 
11932
    /* G_ZEXTLOAD */
11933
    type0, ptype1, 
11934
    /* G_INDEXED_LOAD */
11935
    type0, ptype1, ptype1, type2, -1, 
11936
    /* G_INDEXED_SEXTLOAD */
11937
    type0, ptype1, ptype1, type2, -1, 
11938
    /* G_INDEXED_ZEXTLOAD */
11939
    type0, ptype1, ptype1, type2, -1, 
11940
    /* G_STORE */
11941
    type0, ptype1, 
11942
    /* G_INDEXED_STORE */
11943
    ptype0, type1, ptype0, ptype2, -1, 
11944
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
11945
    type0, type1, type2, type0, type0, 
11946
    /* G_ATOMIC_CMPXCHG */
11947
    type0, ptype1, type0, type0, 
11948
    /* G_ATOMICRMW_XCHG */
11949
    type0, ptype1, type0, 
11950
    /* G_ATOMICRMW_ADD */
11951
    type0, ptype1, type0, 
11952
    /* G_ATOMICRMW_SUB */
11953
    type0, ptype1, type0, 
11954
    /* G_ATOMICRMW_AND */
11955
    type0, ptype1, type0, 
11956
    /* G_ATOMICRMW_NAND */
11957
    type0, ptype1, type0, 
11958
    /* G_ATOMICRMW_OR */
11959
    type0, ptype1, type0, 
11960
    /* G_ATOMICRMW_XOR */
11961
    type0, ptype1, type0, 
11962
    /* G_ATOMICRMW_MAX */
11963
    type0, ptype1, type0, 
11964
    /* G_ATOMICRMW_MIN */
11965
    type0, ptype1, type0, 
11966
    /* G_ATOMICRMW_UMAX */
11967
    type0, ptype1, type0, 
11968
    /* G_ATOMICRMW_UMIN */
11969
    type0, ptype1, type0, 
11970
    /* G_ATOMICRMW_FADD */
11971
    type0, ptype1, type0, 
11972
    /* G_ATOMICRMW_FSUB */
11973
    type0, ptype1, type0, 
11974
    /* G_ATOMICRMW_FMAX */
11975
    type0, ptype1, type0, 
11976
    /* G_ATOMICRMW_FMIN */
11977
    type0, ptype1, type0, 
11978
    /* G_ATOMICRMW_UINC_WRAP */
11979
    type0, ptype1, type0, 
11980
    /* G_ATOMICRMW_UDEC_WRAP */
11981
    type0, ptype1, type0, 
11982
    /* G_FENCE */
11983
    i32imm, i32imm, 
11984
    /* G_PREFETCH */
11985
    ptype0, i32imm, i32imm, i32imm, 
11986
    /* G_BRCOND */
11987
    type0, -1, 
11988
    /* G_BRINDIRECT */
11989
    type0, 
11990
    /* G_INVOKE_REGION_START */
11991
    /* G_INTRINSIC */
11992
    -1, 
11993
    /* G_INTRINSIC_W_SIDE_EFFECTS */
11994
    -1, 
11995
    /* G_INTRINSIC_CONVERGENT */
11996
    -1, 
11997
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
11998
    -1, 
11999
    /* G_ANYEXT */
12000
    type0, type1, 
12001
    /* G_TRUNC */
12002
    type0, type1, 
12003
    /* G_CONSTANT */
12004
    type0, -1, 
12005
    /* G_FCONSTANT */
12006
    type0, -1, 
12007
    /* G_VASTART */
12008
    type0, 
12009
    /* G_VAARG */
12010
    type0, type1, -1, 
12011
    /* G_SEXT */
12012
    type0, type1, 
12013
    /* G_SEXT_INREG */
12014
    type0, type0, untyped_imm_0, 
12015
    /* G_ZEXT */
12016
    type0, type1, 
12017
    /* G_SHL */
12018
    type0, type0, type1, 
12019
    /* G_LSHR */
12020
    type0, type0, type1, 
12021
    /* G_ASHR */
12022
    type0, type0, type1, 
12023
    /* G_FSHL */
12024
    type0, type0, type0, type1, 
12025
    /* G_FSHR */
12026
    type0, type0, type0, type1, 
12027
    /* G_ROTR */
12028
    type0, type0, type1, 
12029
    /* G_ROTL */
12030
    type0, type0, type1, 
12031
    /* G_ICMP */
12032
    type0, -1, type1, type1, 
12033
    /* G_FCMP */
12034
    type0, -1, type1, type1, 
12035
    /* G_SELECT */
12036
    type0, type1, type0, type0, 
12037
    /* G_UADDO */
12038
    type0, type1, type0, type0, 
12039
    /* G_UADDE */
12040
    type0, type1, type0, type0, type1, 
12041
    /* G_USUBO */
12042
    type0, type1, type0, type0, 
12043
    /* G_USUBE */
12044
    type0, type1, type0, type0, type1, 
12045
    /* G_SADDO */
12046
    type0, type1, type0, type0, 
12047
    /* G_SADDE */
12048
    type0, type1, type0, type0, type1, 
12049
    /* G_SSUBO */
12050
    type0, type1, type0, type0, 
12051
    /* G_SSUBE */
12052
    type0, type1, type0, type0, type1, 
12053
    /* G_UMULO */
12054
    type0, type1, type0, type0, 
12055
    /* G_SMULO */
12056
    type0, type1, type0, type0, 
12057
    /* G_UMULH */
12058
    type0, type0, type0, 
12059
    /* G_SMULH */
12060
    type0, type0, type0, 
12061
    /* G_UADDSAT */
12062
    type0, type0, type0, 
12063
    /* G_SADDSAT */
12064
    type0, type0, type0, 
12065
    /* G_USUBSAT */
12066
    type0, type0, type0, 
12067
    /* G_SSUBSAT */
12068
    type0, type0, type0, 
12069
    /* G_USHLSAT */
12070
    type0, type0, type1, 
12071
    /* G_SSHLSAT */
12072
    type0, type0, type1, 
12073
    /* G_SMULFIX */
12074
    type0, type0, type0, untyped_imm_0, 
12075
    /* G_UMULFIX */
12076
    type0, type0, type0, untyped_imm_0, 
12077
    /* G_SMULFIXSAT */
12078
    type0, type0, type0, untyped_imm_0, 
12079
    /* G_UMULFIXSAT */
12080
    type0, type0, type0, untyped_imm_0, 
12081
    /* G_SDIVFIX */
12082
    type0, type0, type0, untyped_imm_0, 
12083
    /* G_UDIVFIX */
12084
    type0, type0, type0, untyped_imm_0, 
12085
    /* G_SDIVFIXSAT */
12086
    type0, type0, type0, untyped_imm_0, 
12087
    /* G_UDIVFIXSAT */
12088
    type0, type0, type0, untyped_imm_0, 
12089
    /* G_FADD */
12090
    type0, type0, type0, 
12091
    /* G_FSUB */
12092
    type0, type0, type0, 
12093
    /* G_FMUL */
12094
    type0, type0, type0, 
12095
    /* G_FMA */
12096
    type0, type0, type0, type0, 
12097
    /* G_FMAD */
12098
    type0, type0, type0, type0, 
12099
    /* G_FDIV */
12100
    type0, type0, type0, 
12101
    /* G_FREM */
12102
    type0, type0, type0, 
12103
    /* G_FPOW */
12104
    type0, type0, type0, 
12105
    /* G_FPOWI */
12106
    type0, type0, type1, 
12107
    /* G_FEXP */
12108
    type0, type0, 
12109
    /* G_FEXP2 */
12110
    type0, type0, 
12111
    /* G_FEXP10 */
12112
    type0, type0, 
12113
    /* G_FLOG */
12114
    type0, type0, 
12115
    /* G_FLOG2 */
12116
    type0, type0, 
12117
    /* G_FLOG10 */
12118
    type0, type0, 
12119
    /* G_FLDEXP */
12120
    type0, type0, type1, 
12121
    /* G_FFREXP */
12122
    type0, type1, type0, 
12123
    /* G_FNEG */
12124
    type0, type0, 
12125
    /* G_FPEXT */
12126
    type0, type1, 
12127
    /* G_FPTRUNC */
12128
    type0, type1, 
12129
    /* G_FPTOSI */
12130
    type0, type1, 
12131
    /* G_FPTOUI */
12132
    type0, type1, 
12133
    /* G_SITOFP */
12134
    type0, type1, 
12135
    /* G_UITOFP */
12136
    type0, type1, 
12137
    /* G_FABS */
12138
    type0, type0, 
12139
    /* G_FCOPYSIGN */
12140
    type0, type0, type1, 
12141
    /* G_IS_FPCLASS */
12142
    type0, type1, -1, 
12143
    /* G_FCANONICALIZE */
12144
    type0, type0, 
12145
    /* G_FMINNUM */
12146
    type0, type0, type0, 
12147
    /* G_FMAXNUM */
12148
    type0, type0, type0, 
12149
    /* G_FMINNUM_IEEE */
12150
    type0, type0, type0, 
12151
    /* G_FMAXNUM_IEEE */
12152
    type0, type0, type0, 
12153
    /* G_FMINIMUM */
12154
    type0, type0, type0, 
12155
    /* G_FMAXIMUM */
12156
    type0, type0, type0, 
12157
    /* G_GET_FPENV */
12158
    type0, 
12159
    /* G_SET_FPENV */
12160
    type0, 
12161
    /* G_RESET_FPENV */
12162
    /* G_GET_FPMODE */
12163
    type0, 
12164
    /* G_SET_FPMODE */
12165
    type0, 
12166
    /* G_RESET_FPMODE */
12167
    /* G_PTR_ADD */
12168
    ptype0, ptype0, type1, 
12169
    /* G_PTRMASK */
12170
    ptype0, ptype0, type1, 
12171
    /* G_SMIN */
12172
    type0, type0, type0, 
12173
    /* G_SMAX */
12174
    type0, type0, type0, 
12175
    /* G_UMIN */
12176
    type0, type0, type0, 
12177
    /* G_UMAX */
12178
    type0, type0, type0, 
12179
    /* G_ABS */
12180
    type0, type0, 
12181
    /* G_LROUND */
12182
    type0, type1, 
12183
    /* G_LLROUND */
12184
    type0, type1, 
12185
    /* G_BR */
12186
    -1, 
12187
    /* G_BRJT */
12188
    ptype0, -1, type1, 
12189
    /* G_INSERT_VECTOR_ELT */
12190
    type0, type0, type1, type2, 
12191
    /* G_EXTRACT_VECTOR_ELT */
12192
    type0, type1, type2, 
12193
    /* G_SHUFFLE_VECTOR */
12194
    type0, type1, type1, -1, 
12195
    /* G_CTTZ */
12196
    type0, type1, 
12197
    /* G_CTTZ_ZERO_UNDEF */
12198
    type0, type1, 
12199
    /* G_CTLZ */
12200
    type0, type1, 
12201
    /* G_CTLZ_ZERO_UNDEF */
12202
    type0, type1, 
12203
    /* G_CTPOP */
12204
    type0, type1, 
12205
    /* G_BSWAP */
12206
    type0, type0, 
12207
    /* G_BITREVERSE */
12208
    type0, type0, 
12209
    /* G_FCEIL */
12210
    type0, type0, 
12211
    /* G_FCOS */
12212
    type0, type0, 
12213
    /* G_FSIN */
12214
    type0, type0, 
12215
    /* G_FSQRT */
12216
    type0, type0, 
12217
    /* G_FFLOOR */
12218
    type0, type0, 
12219
    /* G_FRINT */
12220
    type0, type0, 
12221
    /* G_FNEARBYINT */
12222
    type0, type0, 
12223
    /* G_ADDRSPACE_CAST */
12224
    type0, type1, 
12225
    /* G_BLOCK_ADDR */
12226
    type0, -1, 
12227
    /* G_JUMP_TABLE */
12228
    type0, -1, 
12229
    /* G_DYN_STACKALLOC */
12230
    ptype0, type1, i32imm, 
12231
    /* G_STACKSAVE */
12232
    ptype0, 
12233
    /* G_STACKRESTORE */
12234
    ptype0, 
12235
    /* G_STRICT_FADD */
12236
    type0, type0, type0, 
12237
    /* G_STRICT_FSUB */
12238
    type0, type0, type0, 
12239
    /* G_STRICT_FMUL */
12240
    type0, type0, type0, 
12241
    /* G_STRICT_FDIV */
12242
    type0, type0, type0, 
12243
    /* G_STRICT_FREM */
12244
    type0, type0, type0, 
12245
    /* G_STRICT_FMA */
12246
    type0, type0, type0, type0, 
12247
    /* G_STRICT_FSQRT */
12248
    type0, type0, 
12249
    /* G_STRICT_FLDEXP */
12250
    type0, type0, type1, 
12251
    /* G_READ_REGISTER */
12252
    type0, -1, 
12253
    /* G_WRITE_REGISTER */
12254
    -1, type0, 
12255
    /* G_MEMCPY */
12256
    ptype0, ptype1, type2, untyped_imm_0, 
12257
    /* G_MEMCPY_INLINE */
12258
    ptype0, ptype1, type2, 
12259
    /* G_MEMMOVE */
12260
    ptype0, ptype1, type2, untyped_imm_0, 
12261
    /* G_MEMSET */
12262
    ptype0, type1, type2, untyped_imm_0, 
12263
    /* G_BZERO */
12264
    ptype0, type1, untyped_imm_0, 
12265
    /* G_VECREDUCE_SEQ_FADD */
12266
    type0, type1, type2, 
12267
    /* G_VECREDUCE_SEQ_FMUL */
12268
    type0, type1, type2, 
12269
    /* G_VECREDUCE_FADD */
12270
    type0, type1, 
12271
    /* G_VECREDUCE_FMUL */
12272
    type0, type1, 
12273
    /* G_VECREDUCE_FMAX */
12274
    type0, type1, 
12275
    /* G_VECREDUCE_FMIN */
12276
    type0, type1, 
12277
    /* G_VECREDUCE_FMAXIMUM */
12278
    type0, type1, 
12279
    /* G_VECREDUCE_FMINIMUM */
12280
    type0, type1, 
12281
    /* G_VECREDUCE_ADD */
12282
    type0, type1, 
12283
    /* G_VECREDUCE_MUL */
12284
    type0, type1, 
12285
    /* G_VECREDUCE_AND */
12286
    type0, type1, 
12287
    /* G_VECREDUCE_OR */
12288
    type0, type1, 
12289
    /* G_VECREDUCE_XOR */
12290
    type0, type1, 
12291
    /* G_VECREDUCE_SMAX */
12292
    type0, type1, 
12293
    /* G_VECREDUCE_SMIN */
12294
    type0, type1, 
12295
    /* G_VECREDUCE_UMAX */
12296
    type0, type1, 
12297
    /* G_VECREDUCE_UMIN */
12298
    type0, type1, 
12299
    /* G_SBFX */
12300
    type0, type0, type1, type1, 
12301
    /* G_UBFX */
12302
    type0, type0, type1, type1, 
12303
    /* ADJCALLSTACKDOWN */
12304
    i32imm, i32imm, 
12305
    /* ADJCALLSTACKUP */
12306
    i32imm, i32imm, 
12307
    /* PseudoAtomicLoadAdd32 */
12308
    GPR, GPR, GPR, GPR, grlenimm, 
12309
    /* PseudoAtomicLoadAnd32 */
12310
    GPR, GPR, GPR, GPR, grlenimm, 
12311
    /* PseudoAtomicLoadNand32 */
12312
    GPR, GPR, GPR, GPR, grlenimm, 
12313
    /* PseudoAtomicLoadNand64 */
12314
    GPR, GPR, GPR, GPR, grlenimm, 
12315
    /* PseudoAtomicLoadOr32 */
12316
    GPR, GPR, GPR, GPR, grlenimm, 
12317
    /* PseudoAtomicLoadSub32 */
12318
    GPR, GPR, GPR, GPR, grlenimm, 
12319
    /* PseudoAtomicLoadXor32 */
12320
    GPR, GPR, GPR, GPR, grlenimm, 
12321
    /* PseudoAtomicStoreD */
12322
    GPR, GPR, GPR, 
12323
    /* PseudoAtomicStoreW */
12324
    GPR, GPR, GPR, 
12325
    /* PseudoAtomicSwap32 */
12326
    GPR, GPR, GPR, GPR, grlenimm, 
12327
    /* PseudoBR */
12328
    simm26_b, 
12329
    /* PseudoBRIND */
12330
    GPR, simm16_lsl2, 
12331
    /* PseudoB_TAIL */
12332
    simm26_b, 
12333
    /* PseudoCALL */
12334
    bare_symbol, 
12335
    /* PseudoCALL36 */
12336
    bare_symbol, 
12337
    /* PseudoCALLIndirect */
12338
    GPR, 
12339
    /* PseudoCALL_LARGE */
12340
    bare_symbol, 
12341
    /* PseudoCALL_MEDIUM */
12342
    bare_symbol, 
12343
    /* PseudoCmpXchg32 */
12344
    GPR, GPR, GPR, GPR, GPR, grlenimm, 
12345
    /* PseudoCmpXchg64 */
12346
    GPR, GPR, GPR, GPR, GPR, grlenimm, 
12347
    /* PseudoCopyCFR */
12348
    CFR, CFR, 
12349
    /* PseudoJIRL_CALL */
12350
    GPR, simm16_lsl2, 
12351
    /* PseudoJIRL_TAIL */
12352
    GPR, simm16_lsl2, 
12353
    /* PseudoLA_ABS */
12354
    GPR, bare_symbol, 
12355
    /* PseudoLA_ABS_LARGE */
12356
    GPR, GPR, bare_symbol, 
12357
    /* PseudoLA_GOT */
12358
    GPR, bare_symbol, 
12359
    /* PseudoLA_GOT_LARGE */
12360
    GPR, GPR, bare_symbol, 
12361
    /* PseudoLA_PCREL */
12362
    GPR, bare_symbol, 
12363
    /* PseudoLA_PCREL_LARGE */
12364
    GPR, GPR, bare_symbol, 
12365
    /* PseudoLA_TLS_GD */
12366
    GPR, bare_symbol, 
12367
    /* PseudoLA_TLS_GD_LARGE */
12368
    GPR, GPR, bare_symbol, 
12369
    /* PseudoLA_TLS_IE */
12370
    GPR, bare_symbol, 
12371
    /* PseudoLA_TLS_IE_LARGE */
12372
    GPR, GPR, bare_symbol, 
12373
    /* PseudoLA_TLS_LD */
12374
    GPR, bare_symbol, 
12375
    /* PseudoLA_TLS_LD_LARGE */
12376
    GPR, GPR, bare_symbol, 
12377
    /* PseudoLA_TLS_LE */
12378
    GPR, bare_symbol, 
12379
    /* PseudoLD_CFR */
12380
    CFR, GPR, grlenimm, 
12381
    /* PseudoLI_D */
12382
    GPR, grlenimm, 
12383
    /* PseudoLI_W */
12384
    GPR, imm32, 
12385
    /* PseudoMaskedAtomicLoadAdd32 */
12386
    GPR, GPR, GPR, GPR, GPR, grlenimm, 
12387
    /* PseudoMaskedAtomicLoadMax32 */
12388
    GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, 
12389
    /* PseudoMaskedAtomicLoadMin32 */
12390
    GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, grlenimm, 
12391
    /* PseudoMaskedAtomicLoadNand32 */
12392
    GPR, GPR, GPR, GPR, GPR, grlenimm, 
12393
    /* PseudoMaskedAtomicLoadSub32 */
12394
    GPR, GPR, GPR, GPR, GPR, grlenimm, 
12395
    /* PseudoMaskedAtomicLoadUMax32 */
12396
    GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, 
12397
    /* PseudoMaskedAtomicLoadUMin32 */
12398
    GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, 
12399
    /* PseudoMaskedAtomicSwap32 */
12400
    GPR, GPR, GPR, GPR, GPR, grlenimm, 
12401
    /* PseudoMaskedCmpXchg32 */
12402
    GPR, GPR, GPR, GPR, GPR, GPR, grlenimm, 
12403
    /* PseudoRET */
12404
    /* PseudoST_CFR */
12405
    CFR, GPR, grlenimm, 
12406
    /* PseudoTAIL */
12407
    bare_symbol, 
12408
    /* PseudoTAIL36 */
12409
    GPR, bare_symbol, 
12410
    /* PseudoTAILIndirect */
12411
    GPRT, 
12412
    /* PseudoTAIL_LARGE */
12413
    bare_symbol, 
12414
    /* PseudoTAIL_MEDIUM */
12415
    bare_symbol, 
12416
    /* PseudoUNIMP */
12417
    /* PseudoVBNZ */
12418
    GPR, LSX128, 
12419
    /* PseudoVBNZ_B */
12420
    GPR, LSX128, 
12421
    /* PseudoVBNZ_D */
12422
    GPR, LSX128, 
12423
    /* PseudoVBNZ_H */
12424
    GPR, LSX128, 
12425
    /* PseudoVBNZ_W */
12426
    GPR, LSX128, 
12427
    /* PseudoVBZ */
12428
    GPR, LSX128, 
12429
    /* PseudoVBZ_B */
12430
    GPR, LSX128, 
12431
    /* PseudoVBZ_D */
12432
    GPR, LSX128, 
12433
    /* PseudoVBZ_H */
12434
    GPR, LSX128, 
12435
    /* PseudoVBZ_W */
12436
    GPR, LSX128, 
12437
    /* PseudoVREPLI_B */
12438
    LSX128, simm10, 
12439
    /* PseudoVREPLI_D */
12440
    LSX128, simm10, 
12441
    /* PseudoVREPLI_H */
12442
    LSX128, simm10, 
12443
    /* PseudoVREPLI_W */
12444
    LSX128, simm10, 
12445
    /* PseudoXVBNZ */
12446
    GPR, LASX256, 
12447
    /* PseudoXVBNZ_B */
12448
    GPR, LASX256, 
12449
    /* PseudoXVBNZ_D */
12450
    GPR, LASX256, 
12451
    /* PseudoXVBNZ_H */
12452
    GPR, LASX256, 
12453
    /* PseudoXVBNZ_W */
12454
    GPR, LASX256, 
12455
    /* PseudoXVBZ */
12456
    GPR, LASX256, 
12457
    /* PseudoXVBZ_B */
12458
    GPR, LASX256, 
12459
    /* PseudoXVBZ_D */
12460
    GPR, LASX256, 
12461
    /* PseudoXVBZ_H */
12462
    GPR, LASX256, 
12463
    /* PseudoXVBZ_W */
12464
    GPR, LASX256, 
12465
    /* PseudoXVINSGR2VR_B */
12466
    LASX256, LASX256, GPR, uimm5, 
12467
    /* PseudoXVINSGR2VR_H */
12468
    LASX256, LASX256, GPR, uimm4, 
12469
    /* PseudoXVREPLI_B */
12470
    LASX256, simm10, 
12471
    /* PseudoXVREPLI_D */
12472
    LASX256, simm10, 
12473
    /* PseudoXVREPLI_H */
12474
    LASX256, simm10, 
12475
    /* PseudoXVREPLI_W */
12476
    LASX256, simm10, 
12477
    /* RDFCSR */
12478
    GPR, uimm2, 
12479
    /* WRFCSR */
12480
    uimm2, GPR, 
12481
    /* ADC_B */
12482
    GPR, GPR, GPR, 
12483
    /* ADC_D */
12484
    GPR, GPR, GPR, 
12485
    /* ADC_H */
12486
    GPR, GPR, GPR, 
12487
    /* ADC_W */
12488
    GPR, GPR, GPR, 
12489
    /* ADDI_D */
12490
    GPR, GPR, simm12_addlike, 
12491
    /* ADDI_W */
12492
    GPR, GPR, simm12_addlike, 
12493
    /* ADDU12I_D */
12494
    GPR, GPR, simm5, 
12495
    /* ADDU12I_W */
12496
    GPR, GPR, simm5, 
12497
    /* ADDU16I_D */
12498
    GPR, GPR, simm16, 
12499
    /* ADD_D */
12500
    GPR, GPR, GPR, 
12501
    /* ADD_W */
12502
    GPR, GPR, GPR, 
12503
    /* ALSL_D */
12504
    GPR, GPR, GPR, uimm2_plus1, 
12505
    /* ALSL_W */
12506
    GPR, GPR, GPR, uimm2_plus1, 
12507
    /* ALSL_WU */
12508
    GPR, GPR, GPR, uimm2_plus1, 
12509
    /* AMADD_B */
12510
    GPR, GPR, GPRMemAtomic, 
12511
    /* AMADD_D */
12512
    GPR, GPR, GPRMemAtomic, 
12513
    /* AMADD_H */
12514
    GPR, GPR, GPRMemAtomic, 
12515
    /* AMADD_W */
12516
    GPR, GPR, GPRMemAtomic, 
12517
    /* AMADD__DB_B */
12518
    GPR, GPR, GPRMemAtomic, 
12519
    /* AMADD__DB_D */
12520
    GPR, GPR, GPRMemAtomic, 
12521
    /* AMADD__DB_H */
12522
    GPR, GPR, GPRMemAtomic, 
12523
    /* AMADD__DB_W */
12524
    GPR, GPR, GPRMemAtomic, 
12525
    /* AMAND_D */
12526
    GPR, GPR, GPRMemAtomic, 
12527
    /* AMAND_W */
12528
    GPR, GPR, GPRMemAtomic, 
12529
    /* AMAND__DB_D */
12530
    GPR, GPR, GPRMemAtomic, 
12531
    /* AMAND__DB_W */
12532
    GPR, GPR, GPRMemAtomic, 
12533
    /* AMCAS_B */
12534
    GPR, GPR, GPRMemAtomic, 
12535
    /* AMCAS_D */
12536
    GPR, GPR, GPRMemAtomic, 
12537
    /* AMCAS_H */
12538
    GPR, GPR, GPRMemAtomic, 
12539
    /* AMCAS_W */
12540
    GPR, GPR, GPRMemAtomic, 
12541
    /* AMCAS__DB_B */
12542
    GPR, GPR, GPRMemAtomic, 
12543
    /* AMCAS__DB_D */
12544
    GPR, GPR, GPRMemAtomic, 
12545
    /* AMCAS__DB_H */
12546
    GPR, GPR, GPRMemAtomic, 
12547
    /* AMCAS__DB_W */
12548
    GPR, GPR, GPRMemAtomic, 
12549
    /* AMMAX_D */
12550
    GPR, GPR, GPRMemAtomic, 
12551
    /* AMMAX_DU */
12552
    GPR, GPR, GPRMemAtomic, 
12553
    /* AMMAX_W */
12554
    GPR, GPR, GPRMemAtomic, 
12555
    /* AMMAX_WU */
12556
    GPR, GPR, GPRMemAtomic, 
12557
    /* AMMAX__DB_D */
12558
    GPR, GPR, GPRMemAtomic, 
12559
    /* AMMAX__DB_DU */
12560
    GPR, GPR, GPRMemAtomic, 
12561
    /* AMMAX__DB_W */
12562
    GPR, GPR, GPRMemAtomic, 
12563
    /* AMMAX__DB_WU */
12564
    GPR, GPR, GPRMemAtomic, 
12565
    /* AMMIN_D */
12566
    GPR, GPR, GPRMemAtomic, 
12567
    /* AMMIN_DU */
12568
    GPR, GPR, GPRMemAtomic, 
12569
    /* AMMIN_W */
12570
    GPR, GPR, GPRMemAtomic, 
12571
    /* AMMIN_WU */
12572
    GPR, GPR, GPRMemAtomic, 
12573
    /* AMMIN__DB_D */
12574
    GPR, GPR, GPRMemAtomic, 
12575
    /* AMMIN__DB_DU */
12576
    GPR, GPR, GPRMemAtomic, 
12577
    /* AMMIN__DB_W */
12578
    GPR, GPR, GPRMemAtomic, 
12579
    /* AMMIN__DB_WU */
12580
    GPR, GPR, GPRMemAtomic, 
12581
    /* AMOR_D */
12582
    GPR, GPR, GPRMemAtomic, 
12583
    /* AMOR_W */
12584
    GPR, GPR, GPRMemAtomic, 
12585
    /* AMOR__DB_D */
12586
    GPR, GPR, GPRMemAtomic, 
12587
    /* AMOR__DB_W */
12588
    GPR, GPR, GPRMemAtomic, 
12589
    /* AMSWAP_B */
12590
    GPR, GPR, GPRMemAtomic, 
12591
    /* AMSWAP_D */
12592
    GPR, GPR, GPRMemAtomic, 
12593
    /* AMSWAP_H */
12594
    GPR, GPR, GPRMemAtomic, 
12595
    /* AMSWAP_W */
12596
    GPR, GPR, GPRMemAtomic, 
12597
    /* AMSWAP__DB_B */
12598
    GPR, GPR, GPRMemAtomic, 
12599
    /* AMSWAP__DB_D */
12600
    GPR, GPR, GPRMemAtomic, 
12601
    /* AMSWAP__DB_H */
12602
    GPR, GPR, GPRMemAtomic, 
12603
    /* AMSWAP__DB_W */
12604
    GPR, GPR, GPRMemAtomic, 
12605
    /* AMXOR_D */
12606
    GPR, GPR, GPRMemAtomic, 
12607
    /* AMXOR_W */
12608
    GPR, GPR, GPRMemAtomic, 
12609
    /* AMXOR__DB_D */
12610
    GPR, GPR, GPRMemAtomic, 
12611
    /* AMXOR__DB_W */
12612
    GPR, GPR, GPRMemAtomic, 
12613
    /* AND */
12614
    GPR, GPR, GPR, 
12615
    /* ANDI */
12616
    GPR, GPR, uimm12, 
12617
    /* ANDN */
12618
    GPR, GPR, GPR, 
12619
    /* ARMADC_W */
12620
    GPR, GPR, uimm4, 
12621
    /* ARMADD_W */
12622
    GPR, GPR, uimm4, 
12623
    /* ARMAND_W */
12624
    GPR, GPR, uimm4, 
12625
    /* ARMMFFLAG */
12626
    GPR, uimm8, 
12627
    /* ARMMOVE */
12628
    GPR, GPR, uimm4, 
12629
    /* ARMMOV_D */
12630
    GPR, uimm4, 
12631
    /* ARMMOV_W */
12632
    GPR, uimm4, 
12633
    /* ARMMTFLAG */
12634
    GPR, uimm8, 
12635
    /* ARMNOT_W */
12636
    GPR, uimm4, 
12637
    /* ARMOR_W */
12638
    GPR, GPR, uimm4, 
12639
    /* ARMROTRI_W */
12640
    GPR, uimm5, uimm4, 
12641
    /* ARMROTR_W */
12642
    GPR, GPR, uimm4, 
12643
    /* ARMRRX_W */
12644
    GPR, uimm4, 
12645
    /* ARMSBC_W */
12646
    GPR, GPR, uimm4, 
12647
    /* ARMSLLI_W */
12648
    GPR, uimm5, uimm4, 
12649
    /* ARMSLL_W */
12650
    GPR, GPR, uimm4, 
12651
    /* ARMSRAI_W */
12652
    GPR, uimm5, uimm4, 
12653
    /* ARMSRA_W */
12654
    GPR, GPR, uimm4, 
12655
    /* ARMSRLI_W */
12656
    GPR, uimm5, uimm4, 
12657
    /* ARMSRL_W */
12658
    GPR, GPR, uimm4, 
12659
    /* ARMSUB_W */
12660
    GPR, GPR, uimm4, 
12661
    /* ARMXOR_W */
12662
    GPR, GPR, uimm4, 
12663
    /* ASRTGT_D */
12664
    GPR, GPR, 
12665
    /* ASRTLE_D */
12666
    GPR, GPR, 
12667
    /* B */
12668
    simm26_b, 
12669
    /* BCEQZ */
12670
    CFR, simm21_lsl2, 
12671
    /* BCNEZ */
12672
    CFR, simm21_lsl2, 
12673
    /* BEQ */
12674
    GPR, GPR, simm16_lsl2_br, 
12675
    /* BEQZ */
12676
    GPR, simm21_lsl2, 
12677
    /* BGE */
12678
    GPR, GPR, simm16_lsl2_br, 
12679
    /* BGEU */
12680
    GPR, GPR, simm16_lsl2_br, 
12681
    /* BITREV_4B */
12682
    GPR, GPR, 
12683
    /* BITREV_8B */
12684
    GPR, GPR, 
12685
    /* BITREV_D */
12686
    GPR, GPR, 
12687
    /* BITREV_W */
12688
    GPR, GPR, 
12689
    /* BL */
12690
    simm26_symbol, 
12691
    /* BLT */
12692
    GPR, GPR, simm16_lsl2_br, 
12693
    /* BLTU */
12694
    GPR, GPR, simm16_lsl2_br, 
12695
    /* BNE */
12696
    GPR, GPR, simm16_lsl2_br, 
12697
    /* BNEZ */
12698
    GPR, simm21_lsl2, 
12699
    /* BREAK */
12700
    uimm15, 
12701
    /* BSTRINS_D */
12702
    GPR, GPR, GPR, uimm6, uimm6, 
12703
    /* BSTRINS_W */
12704
    GPR, GPR, GPR, uimm5, uimm5, 
12705
    /* BSTRPICK_D */
12706
    GPR, GPR, uimm6, uimm6, 
12707
    /* BSTRPICK_W */
12708
    GPR, GPR, uimm5, uimm5, 
12709
    /* BYTEPICK_D */
12710
    GPR, GPR, GPR, uimm3, 
12711
    /* BYTEPICK_W */
12712
    GPR, GPR, GPR, uimm2, 
12713
    /* CACOP */
12714
    uimm5, GPR, simm12, 
12715
    /* CLO_D */
12716
    GPR, GPR, 
12717
    /* CLO_W */
12718
    GPR, GPR, 
12719
    /* CLZ_D */
12720
    GPR, GPR, 
12721
    /* CLZ_W */
12722
    GPR, GPR, 
12723
    /* CPUCFG */
12724
    GPR, GPR, 
12725
    /* CRCC_W_B_W */
12726
    GPR, GPR, GPR, 
12727
    /* CRCC_W_D_W */
12728
    GPR, GPR, GPR, 
12729
    /* CRCC_W_H_W */
12730
    GPR, GPR, GPR, 
12731
    /* CRCC_W_W_W */
12732
    GPR, GPR, GPR, 
12733
    /* CRC_W_B_W */
12734
    GPR, GPR, GPR, 
12735
    /* CRC_W_D_W */
12736
    GPR, GPR, GPR, 
12737
    /* CRC_W_H_W */
12738
    GPR, GPR, GPR, 
12739
    /* CRC_W_W_W */
12740
    GPR, GPR, GPR, 
12741
    /* CSRRD */
12742
    GPR, uimm14, 
12743
    /* CSRWR */
12744
    GPR, GPR, uimm14, 
12745
    /* CSRXCHG */
12746
    GPR, GPR, GPR, uimm14, 
12747
    /* CTO_D */
12748
    GPR, GPR, 
12749
    /* CTO_W */
12750
    GPR, GPR, 
12751
    /* CTZ_D */
12752
    GPR, GPR, 
12753
    /* CTZ_W */
12754
    GPR, GPR, 
12755
    /* DBAR */
12756
    uimm15, 
12757
    /* DBCL */
12758
    uimm15, 
12759
    /* DIV_D */
12760
    GPR, GPR, GPR, 
12761
    /* DIV_DU */
12762
    GPR, GPR, GPR, 
12763
    /* DIV_W */
12764
    GPR, GPR, GPR, 
12765
    /* DIV_WU */
12766
    GPR, GPR, GPR, 
12767
    /* ERTN */
12768
    /* EXT_W_B */
12769
    GPR, GPR, 
12770
    /* EXT_W_H */
12771
    GPR, GPR, 
12772
    /* FABS_D */
12773
    FPR64, FPR64, 
12774
    /* FABS_S */
12775
    FPR32, FPR32, 
12776
    /* FADD_D */
12777
    FPR64, FPR64, FPR64, 
12778
    /* FADD_S */
12779
    FPR32, FPR32, FPR32, 
12780
    /* FCLASS_D */
12781
    FPR64, FPR64, 
12782
    /* FCLASS_S */
12783
    FPR32, FPR32, 
12784
    /* FCMP_CAF_D */
12785
    CFR, FPR64, FPR64, 
12786
    /* FCMP_CAF_S */
12787
    CFR, FPR32, FPR32, 
12788
    /* FCMP_CEQ_D */
12789
    CFR, FPR64, FPR64, 
12790
    /* FCMP_CEQ_S */
12791
    CFR, FPR32, FPR32, 
12792
    /* FCMP_CLE_D */
12793
    CFR, FPR64, FPR64, 
12794
    /* FCMP_CLE_S */
12795
    CFR, FPR32, FPR32, 
12796
    /* FCMP_CLT_D */
12797
    CFR, FPR64, FPR64, 
12798
    /* FCMP_CLT_S */
12799
    CFR, FPR32, FPR32, 
12800
    /* FCMP_CNE_D */
12801
    CFR, FPR64, FPR64, 
12802
    /* FCMP_CNE_S */
12803
    CFR, FPR32, FPR32, 
12804
    /* FCMP_COR_D */
12805
    CFR, FPR64, FPR64, 
12806
    /* FCMP_COR_S */
12807
    CFR, FPR32, FPR32, 
12808
    /* FCMP_CUEQ_D */
12809
    CFR, FPR64, FPR64, 
12810
    /* FCMP_CUEQ_S */
12811
    CFR, FPR32, FPR32, 
12812
    /* FCMP_CULE_D */
12813
    CFR, FPR64, FPR64, 
12814
    /* FCMP_CULE_S */
12815
    CFR, FPR32, FPR32, 
12816
    /* FCMP_CULT_D */
12817
    CFR, FPR64, FPR64, 
12818
    /* FCMP_CULT_S */
12819
    CFR, FPR32, FPR32, 
12820
    /* FCMP_CUNE_D */
12821
    CFR, FPR64, FPR64, 
12822
    /* FCMP_CUNE_S */
12823
    CFR, FPR32, FPR32, 
12824
    /* FCMP_CUN_D */
12825
    CFR, FPR64, FPR64, 
12826
    /* FCMP_CUN_S */
12827
    CFR, FPR32, FPR32, 
12828
    /* FCMP_SAF_D */
12829
    CFR, FPR64, FPR64, 
12830
    /* FCMP_SAF_S */
12831
    CFR, FPR32, FPR32, 
12832
    /* FCMP_SEQ_D */
12833
    CFR, FPR64, FPR64, 
12834
    /* FCMP_SEQ_S */
12835
    CFR, FPR32, FPR32, 
12836
    /* FCMP_SLE_D */
12837
    CFR, FPR64, FPR64, 
12838
    /* FCMP_SLE_S */
12839
    CFR, FPR32, FPR32, 
12840
    /* FCMP_SLT_D */
12841
    CFR, FPR64, FPR64, 
12842
    /* FCMP_SLT_S */
12843
    CFR, FPR32, FPR32, 
12844
    /* FCMP_SNE_D */
12845
    CFR, FPR64, FPR64, 
12846
    /* FCMP_SNE_S */
12847
    CFR, FPR32, FPR32, 
12848
    /* FCMP_SOR_D */
12849
    CFR, FPR64, FPR64, 
12850
    /* FCMP_SOR_S */
12851
    CFR, FPR32, FPR32, 
12852
    /* FCMP_SUEQ_D */
12853
    CFR, FPR64, FPR64, 
12854
    /* FCMP_SUEQ_S */
12855
    CFR, FPR32, FPR32, 
12856
    /* FCMP_SULE_D */
12857
    CFR, FPR64, FPR64, 
12858
    /* FCMP_SULE_S */
12859
    CFR, FPR32, FPR32, 
12860
    /* FCMP_SULT_D */
12861
    CFR, FPR64, FPR64, 
12862
    /* FCMP_SULT_S */
12863
    CFR, FPR32, FPR32, 
12864
    /* FCMP_SUNE_D */
12865
    CFR, FPR64, FPR64, 
12866
    /* FCMP_SUNE_S */
12867
    CFR, FPR32, FPR32, 
12868
    /* FCMP_SUN_D */
12869
    CFR, FPR64, FPR64, 
12870
    /* FCMP_SUN_S */
12871
    CFR, FPR32, FPR32, 
12872
    /* FCOPYSIGN_D */
12873
    FPR64, FPR64, FPR64, 
12874
    /* FCOPYSIGN_S */
12875
    FPR32, FPR32, FPR32, 
12876
    /* FCVT_D_LD */
12877
    FPR32, FPR32, FPR32, 
12878
    /* FCVT_D_S */
12879
    FPR64, FPR32, 
12880
    /* FCVT_LD_D */
12881
    FPR32, FPR32, 
12882
    /* FCVT_S_D */
12883
    FPR32, FPR64, 
12884
    /* FCVT_UD_D */
12885
    FPR32, FPR32, 
12886
    /* FDIV_D */
12887
    FPR64, FPR64, FPR64, 
12888
    /* FDIV_S */
12889
    FPR32, FPR32, FPR32, 
12890
    /* FFINT_D_L */
12891
    FPR64, FPR64, 
12892
    /* FFINT_D_W */
12893
    FPR64, FPR32, 
12894
    /* FFINT_S_L */
12895
    FPR32, FPR64, 
12896
    /* FFINT_S_W */
12897
    FPR32, FPR32, 
12898
    /* FLDGT_D */
12899
    FPR64, GPR, GPR, 
12900
    /* FLDGT_S */
12901
    FPR32, GPR, GPR, 
12902
    /* FLDLE_D */
12903
    FPR64, GPR, GPR, 
12904
    /* FLDLE_S */
12905
    FPR32, GPR, GPR, 
12906
    /* FLDX_D */
12907
    FPR64, GPR, GPR, 
12908
    /* FLDX_S */
12909
    FPR32, GPR, GPR, 
12910
    /* FLD_D */
12911
    FPR64, GPR, simm12, 
12912
    /* FLD_S */
12913
    FPR32, GPR, simm12, 
12914
    /* FLOGB_D */
12915
    FPR64, FPR64, 
12916
    /* FLOGB_S */
12917
    FPR32, FPR32, 
12918
    /* FMADD_D */
12919
    FPR64, FPR64, FPR64, FPR64, 
12920
    /* FMADD_S */
12921
    FPR32, FPR32, FPR32, FPR32, 
12922
    /* FMAXA_D */
12923
    FPR64, FPR64, FPR64, 
12924
    /* FMAXA_S */
12925
    FPR32, FPR32, FPR32, 
12926
    /* FMAX_D */
12927
    FPR64, FPR64, FPR64, 
12928
    /* FMAX_S */
12929
    FPR32, FPR32, FPR32, 
12930
    /* FMINA_D */
12931
    FPR64, FPR64, FPR64, 
12932
    /* FMINA_S */
12933
    FPR32, FPR32, FPR32, 
12934
    /* FMIN_D */
12935
    FPR64, FPR64, FPR64, 
12936
    /* FMIN_S */
12937
    FPR32, FPR32, FPR32, 
12938
    /* FMOV_D */
12939
    FPR64, FPR64, 
12940
    /* FMOV_S */
12941
    FPR32, FPR32, 
12942
    /* FMSUB_D */
12943
    FPR64, FPR64, FPR64, FPR64, 
12944
    /* FMSUB_S */
12945
    FPR32, FPR32, FPR32, FPR32, 
12946
    /* FMUL_D */
12947
    FPR64, FPR64, FPR64, 
12948
    /* FMUL_S */
12949
    FPR32, FPR32, FPR32, 
12950
    /* FNEG_D */
12951
    FPR64, FPR64, 
12952
    /* FNEG_S */
12953
    FPR32, FPR32, 
12954
    /* FNMADD_D */
12955
    FPR64, FPR64, FPR64, FPR64, 
12956
    /* FNMADD_S */
12957
    FPR32, FPR32, FPR32, FPR32, 
12958
    /* FNMSUB_D */
12959
    FPR64, FPR64, FPR64, FPR64, 
12960
    /* FNMSUB_S */
12961
    FPR32, FPR32, FPR32, FPR32, 
12962
    /* FRECIPE_D */
12963
    FPR64, FPR64, 
12964
    /* FRECIPE_S */
12965
    FPR32, FPR32, 
12966
    /* FRECIP_D */
12967
    FPR64, FPR64, 
12968
    /* FRECIP_S */
12969
    FPR32, FPR32, 
12970
    /* FRINT_D */
12971
    FPR64, FPR64, 
12972
    /* FRINT_S */
12973
    FPR32, FPR32, 
12974
    /* FRSQRTE_D */
12975
    FPR64, FPR64, 
12976
    /* FRSQRTE_S */
12977
    FPR32, FPR32, 
12978
    /* FRSQRT_D */
12979
    FPR64, FPR64, 
12980
    /* FRSQRT_S */
12981
    FPR32, FPR32, 
12982
    /* FSCALEB_D */
12983
    FPR64, FPR64, FPR64, 
12984
    /* FSCALEB_S */
12985
    FPR32, FPR32, FPR32, 
12986
    /* FSEL_xD */
12987
    FPR64, FPR64, FPR64, CFR, 
12988
    /* FSEL_xS */
12989
    FPR32, FPR32, FPR32, CFR, 
12990
    /* FSQRT_D */
12991
    FPR64, FPR64, 
12992
    /* FSQRT_S */
12993
    FPR32, FPR32, 
12994
    /* FSTGT_D */
12995
    FPR64, GPR, GPR, 
12996
    /* FSTGT_S */
12997
    FPR32, GPR, GPR, 
12998
    /* FSTLE_D */
12999
    FPR64, GPR, GPR, 
13000
    /* FSTLE_S */
13001
    FPR32, GPR, GPR, 
13002
    /* FSTX_D */
13003
    FPR64, GPR, GPR, 
13004
    /* FSTX_S */
13005
    FPR32, GPR, GPR, 
13006
    /* FST_D */
13007
    FPR64, GPR, simm12, 
13008
    /* FST_S */
13009
    FPR32, GPR, simm12, 
13010
    /* FSUB_D */
13011
    FPR64, FPR64, FPR64, 
13012
    /* FSUB_S */
13013
    FPR32, FPR32, FPR32, 
13014
    /* FTINTRM_L_D */
13015
    FPR64, FPR64, 
13016
    /* FTINTRM_L_S */
13017
    FPR64, FPR32, 
13018
    /* FTINTRM_W_D */
13019
    FPR32, FPR64, 
13020
    /* FTINTRM_W_S */
13021
    FPR32, FPR32, 
13022
    /* FTINTRNE_L_D */
13023
    FPR64, FPR64, 
13024
    /* FTINTRNE_L_S */
13025
    FPR64, FPR32, 
13026
    /* FTINTRNE_W_D */
13027
    FPR32, FPR64, 
13028
    /* FTINTRNE_W_S */
13029
    FPR32, FPR32, 
13030
    /* FTINTRP_L_D */
13031
    FPR64, FPR64, 
13032
    /* FTINTRP_L_S */
13033
    FPR64, FPR32, 
13034
    /* FTINTRP_W_D */
13035
    FPR32, FPR64, 
13036
    /* FTINTRP_W_S */
13037
    FPR32, FPR32, 
13038
    /* FTINTRZ_L_D */
13039
    FPR64, FPR64, 
13040
    /* FTINTRZ_L_S */
13041
    FPR64, FPR32, 
13042
    /* FTINTRZ_W_D */
13043
    FPR32, FPR64, 
13044
    /* FTINTRZ_W_S */
13045
    FPR32, FPR32, 
13046
    /* FTINT_L_D */
13047
    FPR64, FPR64, 
13048
    /* FTINT_L_S */
13049
    FPR64, FPR32, 
13050
    /* FTINT_W_D */
13051
    FPR32, FPR64, 
13052
    /* FTINT_W_S */
13053
    FPR32, FPR32, 
13054
    /* GCSRRD */
13055
    GPR, uimm14, 
13056
    /* GCSRWR */
13057
    GPR, GPR, uimm14, 
13058
    /* GCSRXCHG */
13059
    GPR, GPR, GPR, uimm14, 
13060
    /* GTLBFLUSH */
13061
    /* HVCL */
13062
    uimm15, 
13063
    /* IBAR */
13064
    uimm15, 
13065
    /* IDLE */
13066
    uimm15, 
13067
    /* INVTLB */
13068
    GPR, GPR, uimm5, 
13069
    /* IOCSRRD_B */
13070
    GPR, GPR, 
13071
    /* IOCSRRD_D */
13072
    GPR, GPR, 
13073
    /* IOCSRRD_H */
13074
    GPR, GPR, 
13075
    /* IOCSRRD_W */
13076
    GPR, GPR, 
13077
    /* IOCSRWR_B */
13078
    GPR, GPR, 
13079
    /* IOCSRWR_D */
13080
    GPR, GPR, 
13081
    /* IOCSRWR_H */
13082
    GPR, GPR, 
13083
    /* IOCSRWR_W */
13084
    GPR, GPR, 
13085
    /* JIRL */
13086
    GPR, GPR, simm16_lsl2, 
13087
    /* JISCR0 */
13088
    simm21_lsl2, 
13089
    /* JISCR1 */
13090
    simm21_lsl2, 
13091
    /* LDDIR */
13092
    GPR, GPR, uimm8, 
13093
    /* LDGT_B */
13094
    GPR, GPR, GPR, 
13095
    /* LDGT_D */
13096
    GPR, GPR, GPR, 
13097
    /* LDGT_H */
13098
    GPR, GPR, GPR, 
13099
    /* LDGT_W */
13100
    GPR, GPR, GPR, 
13101
    /* LDLE_B */
13102
    GPR, GPR, GPR, 
13103
    /* LDLE_D */
13104
    GPR, GPR, GPR, 
13105
    /* LDLE_H */
13106
    GPR, GPR, GPR, 
13107
    /* LDLE_W */
13108
    GPR, GPR, GPR, 
13109
    /* LDL_D */
13110
    GPR, GPR, simm12_addlike, 
13111
    /* LDL_W */
13112
    GPR, GPR, simm12_addlike, 
13113
    /* LDPTE */
13114
    GPR, uimm8, 
13115
    /* LDPTR_D */
13116
    GPR, GPR, simm14_lsl2, 
13117
    /* LDPTR_W */
13118
    GPR, GPR, simm14_lsl2, 
13119
    /* LDR_D */
13120
    GPR, GPR, simm12_addlike, 
13121
    /* LDR_W */
13122
    GPR, GPR, simm12_addlike, 
13123
    /* LDX_B */
13124
    GPR, GPR, GPR, 
13125
    /* LDX_BU */
13126
    GPR, GPR, GPR, 
13127
    /* LDX_D */
13128
    GPR, GPR, GPR, 
13129
    /* LDX_H */
13130
    GPR, GPR, GPR, 
13131
    /* LDX_HU */
13132
    GPR, GPR, GPR, 
13133
    /* LDX_W */
13134
    GPR, GPR, GPR, 
13135
    /* LDX_WU */
13136
    GPR, GPR, GPR, 
13137
    /* LD_B */
13138
    GPR, GPR, simm12_addlike, 
13139
    /* LD_BU */
13140
    GPR, GPR, simm12_addlike, 
13141
    /* LD_D */
13142
    GPR, GPR, simm12_addlike, 
13143
    /* LD_H */
13144
    GPR, GPR, simm12_addlike, 
13145
    /* LD_HU */
13146
    GPR, GPR, simm12_addlike, 
13147
    /* LD_W */
13148
    GPR, GPR, simm12_addlike, 
13149
    /* LD_WU */
13150
    GPR, GPR, simm12_addlike, 
13151
    /* LLACQ_D */
13152
    GPR, GPR, 
13153
    /* LLACQ_W */
13154
    GPR, GPR, 
13155
    /* LL_D */
13156
    GPR, GPR, simm14_lsl2, 
13157
    /* LL_W */
13158
    GPR, GPR, simm14_lsl2, 
13159
    /* LU12I_W */
13160
    GPR, simm20_lu12iw, 
13161
    /* LU32I_D */
13162
    GPR, GPR, simm20_lu32id, 
13163
    /* LU52I_D */
13164
    GPR, GPR, simm12_lu52id, 
13165
    /* MASKEQZ */
13166
    GPR, GPR, GPR, 
13167
    /* MASKNEZ */
13168
    GPR, GPR, GPR, 
13169
    /* MOD_D */
13170
    GPR, GPR, GPR, 
13171
    /* MOD_DU */
13172
    GPR, GPR, GPR, 
13173
    /* MOD_W */
13174
    GPR, GPR, GPR, 
13175
    /* MOD_WU */
13176
    GPR, GPR, GPR, 
13177
    /* MOVCF2FR_xS */
13178
    FPR32, CFR, 
13179
    /* MOVCF2GR */
13180
    GPR, CFR, 
13181
    /* MOVFCSR2GR */
13182
    GPR, FCSR, 
13183
    /* MOVFR2CF_xS */
13184
    CFR, FPR32, 
13185
    /* MOVFR2GR_D */
13186
    GPR, FPR64, 
13187
    /* MOVFR2GR_S */
13188
    GPR, FPR32, 
13189
    /* MOVFR2GR_S_64 */
13190
    GPR, FPR64, 
13191
    /* MOVFRH2GR_S */
13192
    GPR, FPR64, 
13193
    /* MOVGR2CF */
13194
    CFR, GPR, 
13195
    /* MOVGR2FCSR */
13196
    FCSR, GPR, 
13197
    /* MOVGR2FRH_W */
13198
    FPR64, FPR64, GPR, 
13199
    /* MOVGR2FR_D */
13200
    FPR64, GPR, 
13201
    /* MOVGR2FR_W */
13202
    FPR32, GPR, 
13203
    /* MOVGR2FR_W_64 */
13204
    FPR64, GPR, 
13205
    /* MOVGR2SCR */
13206
    SCR, GPR, 
13207
    /* MOVSCR2GR */
13208
    GPR, SCR, 
13209
    /* MULH_D */
13210
    GPR, GPR, GPR, 
13211
    /* MULH_DU */
13212
    GPR, GPR, GPR, 
13213
    /* MULH_W */
13214
    GPR, GPR, GPR, 
13215
    /* MULH_WU */
13216
    GPR, GPR, GPR, 
13217
    /* MULW_D_W */
13218
    GPR, GPR, GPR, 
13219
    /* MULW_D_WU */
13220
    GPR, GPR, GPR, 
13221
    /* MUL_D */
13222
    GPR, GPR, GPR, 
13223
    /* MUL_W */
13224
    GPR, GPR, GPR, 
13225
    /* NOR */
13226
    GPR, GPR, GPR, 
13227
    /* OR */
13228
    GPR, GPR, GPR, 
13229
    /* ORI */
13230
    GPR, GPR, uimm12_ori, 
13231
    /* ORN */
13232
    GPR, GPR, GPR, 
13233
    /* PCADDI */
13234
    GPR, simm20, 
13235
    /* PCADDU12I */
13236
    GPR, simm20, 
13237
    /* PCADDU18I */
13238
    GPR, simm20_pcaddu18i, 
13239
    /* PCALAU12I */
13240
    GPR, simm20_pcalau12i, 
13241
    /* PRELD */
13242
    uimm5, GPR, simm12, 
13243
    /* PRELDX */
13244
    uimm5, GPR, GPR, 
13245
    /* RCRI_B */
13246
    GPR, GPR, uimm3, 
13247
    /* RCRI_D */
13248
    GPR, GPR, uimm6, 
13249
    /* RCRI_H */
13250
    GPR, GPR, uimm4, 
13251
    /* RCRI_W */
13252
    GPR, GPR, uimm5, 
13253
    /* RCR_B */
13254
    GPR, GPR, GPR, 
13255
    /* RCR_D */
13256
    GPR, GPR, GPR, 
13257
    /* RCR_H */
13258
    GPR, GPR, GPR, 
13259
    /* RCR_W */
13260
    GPR, GPR, GPR, 
13261
    /* RDTIMEH_W */
13262
    GPR, GPR, 
13263
    /* RDTIMEL_W */
13264
    GPR, GPR, 
13265
    /* RDTIME_D */
13266
    GPR, GPR, 
13267
    /* REVB_2H */
13268
    GPR, GPR, 
13269
    /* REVB_2W */
13270
    GPR, GPR, 
13271
    /* REVB_4H */
13272
    GPR, GPR, 
13273
    /* REVB_D */
13274
    GPR, GPR, 
13275
    /* REVH_2W */
13276
    GPR, GPR, 
13277
    /* REVH_D */
13278
    GPR, GPR, 
13279
    /* ROTRI_B */
13280
    GPR, GPR, uimm3, 
13281
    /* ROTRI_D */
13282
    GPR, GPR, uimm6, 
13283
    /* ROTRI_H */
13284
    GPR, GPR, uimm4, 
13285
    /* ROTRI_W */
13286
    GPR, GPR, uimm5, 
13287
    /* ROTR_B */
13288
    GPR, GPR, GPR, 
13289
    /* ROTR_D */
13290
    GPR, GPR, GPR, 
13291
    /* ROTR_H */
13292
    GPR, GPR, GPR, 
13293
    /* ROTR_W */
13294
    GPR, GPR, GPR, 
13295
    /* SBC_B */
13296
    GPR, GPR, GPR, 
13297
    /* SBC_D */
13298
    GPR, GPR, GPR, 
13299
    /* SBC_H */
13300
    GPR, GPR, GPR, 
13301
    /* SBC_W */
13302
    GPR, GPR, GPR, 
13303
    /* SCREL_D */
13304
    GPR, GPR, GPR, 
13305
    /* SCREL_W */
13306
    GPR, GPR, GPR, 
13307
    /* SC_D */
13308
    GPR, GPR, GPR, simm14_lsl2, 
13309
    /* SC_Q */
13310
    GPR, GPR, GPR, GPR, 
13311
    /* SC_W */
13312
    GPR, GPR, GPR, simm14_lsl2, 
13313
    /* SETARMJ */
13314
    GPR, uimm4, 
13315
    /* SETX86J */
13316
    GPR, uimm4, 
13317
    /* SETX86LOOPE */
13318
    GPR, GPR, 
13319
    /* SETX86LOOPNE */
13320
    GPR, GPR, 
13321
    /* SET_CFR_FALSE */
13322
    CFR, 
13323
    /* SET_CFR_TRUE */
13324
    CFR, 
13325
    /* SLLI_D */
13326
    GPR, GPR, uimm6, 
13327
    /* SLLI_W */
13328
    GPR, GPR, uimm5, 
13329
    /* SLL_D */
13330
    GPR, GPR, GPR, 
13331
    /* SLL_W */
13332
    GPR, GPR, GPR, 
13333
    /* SLT */
13334
    GPR, GPR, GPR, 
13335
    /* SLTI */
13336
    GPR, GPR, simm12, 
13337
    /* SLTU */
13338
    GPR, GPR, GPR, 
13339
    /* SLTUI */
13340
    GPR, GPR, simm12, 
13341
    /* SRAI_D */
13342
    GPR, GPR, uimm6, 
13343
    /* SRAI_W */
13344
    GPR, GPR, uimm5, 
13345
    /* SRA_D */
13346
    GPR, GPR, GPR, 
13347
    /* SRA_W */
13348
    GPR, GPR, GPR, 
13349
    /* SRLI_D */
13350
    GPR, GPR, uimm6, 
13351
    /* SRLI_W */
13352
    GPR, GPR, uimm5, 
13353
    /* SRL_D */
13354
    GPR, GPR, GPR, 
13355
    /* SRL_W */
13356
    GPR, GPR, GPR, 
13357
    /* STGT_B */
13358
    GPR, GPR, GPR, 
13359
    /* STGT_D */
13360
    GPR, GPR, GPR, 
13361
    /* STGT_H */
13362
    GPR, GPR, GPR, 
13363
    /* STGT_W */
13364
    GPR, GPR, GPR, 
13365
    /* STLE_B */
13366
    GPR, GPR, GPR, 
13367
    /* STLE_D */
13368
    GPR, GPR, GPR, 
13369
    /* STLE_H */
13370
    GPR, GPR, GPR, 
13371
    /* STLE_W */
13372
    GPR, GPR, GPR, 
13373
    /* STL_D */
13374
    GPR, GPR, simm12_addlike, 
13375
    /* STL_W */
13376
    GPR, GPR, simm12_addlike, 
13377
    /* STPTR_D */
13378
    GPR, GPR, simm14_lsl2, 
13379
    /* STPTR_W */
13380
    GPR, GPR, simm14_lsl2, 
13381
    /* STR_D */
13382
    GPR, GPR, simm12_addlike, 
13383
    /* STR_W */
13384
    GPR, GPR, simm12_addlike, 
13385
    /* STX_B */
13386
    GPR, GPR, GPR, 
13387
    /* STX_D */
13388
    GPR, GPR, GPR, 
13389
    /* STX_H */
13390
    GPR, GPR, GPR, 
13391
    /* STX_W */
13392
    GPR, GPR, GPR, 
13393
    /* ST_B */
13394
    GPR, GPR, simm12_addlike, 
13395
    /* ST_D */
13396
    GPR, GPR, simm12_addlike, 
13397
    /* ST_H */
13398
    GPR, GPR, simm12_addlike, 
13399
    /* ST_W */
13400
    GPR, GPR, simm12_addlike, 
13401
    /* SUB_D */
13402
    GPR, GPR, GPR, 
13403
    /* SUB_W */
13404
    GPR, GPR, GPR, 
13405
    /* SYSCALL */
13406
    uimm15, 
13407
    /* TLBCLR */
13408
    /* TLBFILL */
13409
    /* TLBFLUSH */
13410
    /* TLBRD */
13411
    /* TLBSRCH */
13412
    /* TLBWR */
13413
    /* VABSD_B */
13414
    LSX128, LSX128, LSX128, 
13415
    /* VABSD_BU */
13416
    LSX128, LSX128, LSX128, 
13417
    /* VABSD_D */
13418
    LSX128, LSX128, LSX128, 
13419
    /* VABSD_DU */
13420
    LSX128, LSX128, LSX128, 
13421
    /* VABSD_H */
13422
    LSX128, LSX128, LSX128, 
13423
    /* VABSD_HU */
13424
    LSX128, LSX128, LSX128, 
13425
    /* VABSD_W */
13426
    LSX128, LSX128, LSX128, 
13427
    /* VABSD_WU */
13428
    LSX128, LSX128, LSX128, 
13429
    /* VADDA_B */
13430
    LSX128, LSX128, LSX128, 
13431
    /* VADDA_D */
13432
    LSX128, LSX128, LSX128, 
13433
    /* VADDA_H */
13434
    LSX128, LSX128, LSX128, 
13435
    /* VADDA_W */
13436
    LSX128, LSX128, LSX128, 
13437
    /* VADDI_BU */
13438
    LSX128, LSX128, uimm5, 
13439
    /* VADDI_DU */
13440
    LSX128, LSX128, uimm5, 
13441
    /* VADDI_HU */
13442
    LSX128, LSX128, uimm5, 
13443
    /* VADDI_WU */
13444
    LSX128, LSX128, uimm5, 
13445
    /* VADDWEV_D_W */
13446
    LSX128, LSX128, LSX128, 
13447
    /* VADDWEV_D_WU */
13448
    LSX128, LSX128, LSX128, 
13449
    /* VADDWEV_D_WU_W */
13450
    LSX128, LSX128, LSX128, 
13451
    /* VADDWEV_H_B */
13452
    LSX128, LSX128, LSX128, 
13453
    /* VADDWEV_H_BU */
13454
    LSX128, LSX128, LSX128, 
13455
    /* VADDWEV_H_BU_B */
13456
    LSX128, LSX128, LSX128, 
13457
    /* VADDWEV_Q_D */
13458
    LSX128, LSX128, LSX128, 
13459
    /* VADDWEV_Q_DU */
13460
    LSX128, LSX128, LSX128, 
13461
    /* VADDWEV_Q_DU_D */
13462
    LSX128, LSX128, LSX128, 
13463
    /* VADDWEV_W_H */
13464
    LSX128, LSX128, LSX128, 
13465
    /* VADDWEV_W_HU */
13466
    LSX128, LSX128, LSX128, 
13467
    /* VADDWEV_W_HU_H */
13468
    LSX128, LSX128, LSX128, 
13469
    /* VADDWOD_D_W */
13470
    LSX128, LSX128, LSX128, 
13471
    /* VADDWOD_D_WU */
13472
    LSX128, LSX128, LSX128, 
13473
    /* VADDWOD_D_WU_W */
13474
    LSX128, LSX128, LSX128, 
13475
    /* VADDWOD_H_B */
13476
    LSX128, LSX128, LSX128, 
13477
    /* VADDWOD_H_BU */
13478
    LSX128, LSX128, LSX128, 
13479
    /* VADDWOD_H_BU_B */
13480
    LSX128, LSX128, LSX128, 
13481
    /* VADDWOD_Q_D */
13482
    LSX128, LSX128, LSX128, 
13483
    /* VADDWOD_Q_DU */
13484
    LSX128, LSX128, LSX128, 
13485
    /* VADDWOD_Q_DU_D */
13486
    LSX128, LSX128, LSX128, 
13487
    /* VADDWOD_W_H */
13488
    LSX128, LSX128, LSX128, 
13489
    /* VADDWOD_W_HU */
13490
    LSX128, LSX128, LSX128, 
13491
    /* VADDWOD_W_HU_H */
13492
    LSX128, LSX128, LSX128, 
13493
    /* VADD_B */
13494
    LSX128, LSX128, LSX128, 
13495
    /* VADD_D */
13496
    LSX128, LSX128, LSX128, 
13497
    /* VADD_H */
13498
    LSX128, LSX128, LSX128, 
13499
    /* VADD_Q */
13500
    LSX128, LSX128, LSX128, 
13501
    /* VADD_W */
13502
    LSX128, LSX128, LSX128, 
13503
    /* VANDI_B */
13504
    LSX128, LSX128, uimm8, 
13505
    /* VANDN_V */
13506
    LSX128, LSX128, LSX128, 
13507
    /* VAND_V */
13508
    LSX128, LSX128, LSX128, 
13509
    /* VAVGR_B */
13510
    LSX128, LSX128, LSX128, 
13511
    /* VAVGR_BU */
13512
    LSX128, LSX128, LSX128, 
13513
    /* VAVGR_D */
13514
    LSX128, LSX128, LSX128, 
13515
    /* VAVGR_DU */
13516
    LSX128, LSX128, LSX128, 
13517
    /* VAVGR_H */
13518
    LSX128, LSX128, LSX128, 
13519
    /* VAVGR_HU */
13520
    LSX128, LSX128, LSX128, 
13521
    /* VAVGR_W */
13522
    LSX128, LSX128, LSX128, 
13523
    /* VAVGR_WU */
13524
    LSX128, LSX128, LSX128, 
13525
    /* VAVG_B */
13526
    LSX128, LSX128, LSX128, 
13527
    /* VAVG_BU */
13528
    LSX128, LSX128, LSX128, 
13529
    /* VAVG_D */
13530
    LSX128, LSX128, LSX128, 
13531
    /* VAVG_DU */
13532
    LSX128, LSX128, LSX128, 
13533
    /* VAVG_H */
13534
    LSX128, LSX128, LSX128, 
13535
    /* VAVG_HU */
13536
    LSX128, LSX128, LSX128, 
13537
    /* VAVG_W */
13538
    LSX128, LSX128, LSX128, 
13539
    /* VAVG_WU */
13540
    LSX128, LSX128, LSX128, 
13541
    /* VBITCLRI_B */
13542
    LSX128, LSX128, uimm3, 
13543
    /* VBITCLRI_D */
13544
    LSX128, LSX128, uimm6, 
13545
    /* VBITCLRI_H */
13546
    LSX128, LSX128, uimm4, 
13547
    /* VBITCLRI_W */
13548
    LSX128, LSX128, uimm5, 
13549
    /* VBITCLR_B */
13550
    LSX128, LSX128, LSX128, 
13551
    /* VBITCLR_D */
13552
    LSX128, LSX128, LSX128, 
13553
    /* VBITCLR_H */
13554
    LSX128, LSX128, LSX128, 
13555
    /* VBITCLR_W */
13556
    LSX128, LSX128, LSX128, 
13557
    /* VBITREVI_B */
13558
    LSX128, LSX128, uimm3, 
13559
    /* VBITREVI_D */
13560
    LSX128, LSX128, uimm6, 
13561
    /* VBITREVI_H */
13562
    LSX128, LSX128, uimm4, 
13563
    /* VBITREVI_W */
13564
    LSX128, LSX128, uimm5, 
13565
    /* VBITREV_B */
13566
    LSX128, LSX128, LSX128, 
13567
    /* VBITREV_D */
13568
    LSX128, LSX128, LSX128, 
13569
    /* VBITREV_H */
13570
    LSX128, LSX128, LSX128, 
13571
    /* VBITREV_W */
13572
    LSX128, LSX128, LSX128, 
13573
    /* VBITSELI_B */
13574
    LSX128, LSX128, LSX128, uimm8, 
13575
    /* VBITSEL_V */
13576
    LSX128, LSX128, LSX128, LSX128, 
13577
    /* VBITSETI_B */
13578
    LSX128, LSX128, uimm3, 
13579
    /* VBITSETI_D */
13580
    LSX128, LSX128, uimm6, 
13581
    /* VBITSETI_H */
13582
    LSX128, LSX128, uimm4, 
13583
    /* VBITSETI_W */
13584
    LSX128, LSX128, uimm5, 
13585
    /* VBITSET_B */
13586
    LSX128, LSX128, LSX128, 
13587
    /* VBITSET_D */
13588
    LSX128, LSX128, LSX128, 
13589
    /* VBITSET_H */
13590
    LSX128, LSX128, LSX128, 
13591
    /* VBITSET_W */
13592
    LSX128, LSX128, LSX128, 
13593
    /* VBSLL_V */
13594
    LSX128, LSX128, uimm5, 
13595
    /* VBSRL_V */
13596
    LSX128, LSX128, uimm5, 
13597
    /* VCLO_B */
13598
    LSX128, LSX128, 
13599
    /* VCLO_D */
13600
    LSX128, LSX128, 
13601
    /* VCLO_H */
13602
    LSX128, LSX128, 
13603
    /* VCLO_W */
13604
    LSX128, LSX128, 
13605
    /* VCLZ_B */
13606
    LSX128, LSX128, 
13607
    /* VCLZ_D */
13608
    LSX128, LSX128, 
13609
    /* VCLZ_H */
13610
    LSX128, LSX128, 
13611
    /* VCLZ_W */
13612
    LSX128, LSX128, 
13613
    /* VDIV_B */
13614
    LSX128, LSX128, LSX128, 
13615
    /* VDIV_BU */
13616
    LSX128, LSX128, LSX128, 
13617
    /* VDIV_D */
13618
    LSX128, LSX128, LSX128, 
13619
    /* VDIV_DU */
13620
    LSX128, LSX128, LSX128, 
13621
    /* VDIV_H */
13622
    LSX128, LSX128, LSX128, 
13623
    /* VDIV_HU */
13624
    LSX128, LSX128, LSX128, 
13625
    /* VDIV_W */
13626
    LSX128, LSX128, LSX128, 
13627
    /* VDIV_WU */
13628
    LSX128, LSX128, LSX128, 
13629
    /* VEXT2XV_DU_BU */
13630
    LASX256, LASX256, 
13631
    /* VEXT2XV_DU_HU */
13632
    LASX256, LASX256, 
13633
    /* VEXT2XV_DU_WU */
13634
    LASX256, LASX256, 
13635
    /* VEXT2XV_D_B */
13636
    LASX256, LASX256, 
13637
    /* VEXT2XV_D_H */
13638
    LASX256, LASX256, 
13639
    /* VEXT2XV_D_W */
13640
    LASX256, LASX256, 
13641
    /* VEXT2XV_HU_BU */
13642
    LASX256, LASX256, 
13643
    /* VEXT2XV_H_B */
13644
    LASX256, LASX256, 
13645
    /* VEXT2XV_WU_BU */
13646
    LASX256, LASX256, 
13647
    /* VEXT2XV_WU_HU */
13648
    LASX256, LASX256, 
13649
    /* VEXT2XV_W_B */
13650
    LASX256, LASX256, 
13651
    /* VEXT2XV_W_H */
13652
    LASX256, LASX256, 
13653
    /* VEXTH_DU_WU */
13654
    LSX128, LSX128, 
13655
    /* VEXTH_D_W */
13656
    LSX128, LSX128, 
13657
    /* VEXTH_HU_BU */
13658
    LSX128, LSX128, 
13659
    /* VEXTH_H_B */
13660
    LSX128, LSX128, 
13661
    /* VEXTH_QU_DU */
13662
    LSX128, LSX128, 
13663
    /* VEXTH_Q_D */
13664
    LSX128, LSX128, 
13665
    /* VEXTH_WU_HU */
13666
    LSX128, LSX128, 
13667
    /* VEXTH_W_H */
13668
    LSX128, LSX128, 
13669
    /* VEXTL_QU_DU */
13670
    LSX128, LSX128, 
13671
    /* VEXTL_Q_D */
13672
    LSX128, LSX128, 
13673
    /* VEXTRINS_B */
13674
    LSX128, LSX128, LSX128, uimm8, 
13675
    /* VEXTRINS_D */
13676
    LSX128, LSX128, LSX128, uimm8, 
13677
    /* VEXTRINS_H */
13678
    LSX128, LSX128, LSX128, uimm8, 
13679
    /* VEXTRINS_W */
13680
    LSX128, LSX128, LSX128, uimm8, 
13681
    /* VFADD_D */
13682
    LSX128, LSX128, LSX128, 
13683
    /* VFADD_S */
13684
    LSX128, LSX128, LSX128, 
13685
    /* VFCLASS_D */
13686
    LSX128, LSX128, 
13687
    /* VFCLASS_S */
13688
    LSX128, LSX128, 
13689
    /* VFCMP_CAF_D */
13690
    LSX128, LSX128, LSX128, 
13691
    /* VFCMP_CAF_S */
13692
    LSX128, LSX128, LSX128, 
13693
    /* VFCMP_CEQ_D */
13694
    LSX128, LSX128, LSX128, 
13695
    /* VFCMP_CEQ_S */
13696
    LSX128, LSX128, LSX128, 
13697
    /* VFCMP_CLE_D */
13698
    LSX128, LSX128, LSX128, 
13699
    /* VFCMP_CLE_S */
13700
    LSX128, LSX128, LSX128, 
13701
    /* VFCMP_CLT_D */
13702
    LSX128, LSX128, LSX128, 
13703
    /* VFCMP_CLT_S */
13704
    LSX128, LSX128, LSX128, 
13705
    /* VFCMP_CNE_D */
13706
    LSX128, LSX128, LSX128, 
13707
    /* VFCMP_CNE_S */
13708
    LSX128, LSX128, LSX128, 
13709
    /* VFCMP_COR_D */
13710
    LSX128, LSX128, LSX128, 
13711
    /* VFCMP_COR_S */
13712
    LSX128, LSX128, LSX128, 
13713
    /* VFCMP_CUEQ_D */
13714
    LSX128, LSX128, LSX128, 
13715
    /* VFCMP_CUEQ_S */
13716
    LSX128, LSX128, LSX128, 
13717
    /* VFCMP_CULE_D */
13718
    LSX128, LSX128, LSX128, 
13719
    /* VFCMP_CULE_S */
13720
    LSX128, LSX128, LSX128, 
13721
    /* VFCMP_CULT_D */
13722
    LSX128, LSX128, LSX128, 
13723
    /* VFCMP_CULT_S */
13724
    LSX128, LSX128, LSX128, 
13725
    /* VFCMP_CUNE_D */
13726
    LSX128, LSX128, LSX128, 
13727
    /* VFCMP_CUNE_S */
13728
    LSX128, LSX128, LSX128, 
13729
    /* VFCMP_CUN_D */
13730
    LSX128, LSX128, LSX128, 
13731
    /* VFCMP_CUN_S */
13732
    LSX128, LSX128, LSX128, 
13733
    /* VFCMP_SAF_D */
13734
    LSX128, LSX128, LSX128, 
13735
    /* VFCMP_SAF_S */
13736
    LSX128, LSX128, LSX128, 
13737
    /* VFCMP_SEQ_D */
13738
    LSX128, LSX128, LSX128, 
13739
    /* VFCMP_SEQ_S */
13740
    LSX128, LSX128, LSX128, 
13741
    /* VFCMP_SLE_D */
13742
    LSX128, LSX128, LSX128, 
13743
    /* VFCMP_SLE_S */
13744
    LSX128, LSX128, LSX128, 
13745
    /* VFCMP_SLT_D */
13746
    LSX128, LSX128, LSX128, 
13747
    /* VFCMP_SLT_S */
13748
    LSX128, LSX128, LSX128, 
13749
    /* VFCMP_SNE_D */
13750
    LSX128, LSX128, LSX128, 
13751
    /* VFCMP_SNE_S */
13752
    LSX128, LSX128, LSX128, 
13753
    /* VFCMP_SOR_D */
13754
    LSX128, LSX128, LSX128, 
13755
    /* VFCMP_SOR_S */
13756
    LSX128, LSX128, LSX128, 
13757
    /* VFCMP_SUEQ_D */
13758
    LSX128, LSX128, LSX128, 
13759
    /* VFCMP_SUEQ_S */
13760
    LSX128, LSX128, LSX128, 
13761
    /* VFCMP_SULE_D */
13762
    LSX128, LSX128, LSX128, 
13763
    /* VFCMP_SULE_S */
13764
    LSX128, LSX128, LSX128, 
13765
    /* VFCMP_SULT_D */
13766
    LSX128, LSX128, LSX128, 
13767
    /* VFCMP_SULT_S */
13768
    LSX128, LSX128, LSX128, 
13769
    /* VFCMP_SUNE_D */
13770
    LSX128, LSX128, LSX128, 
13771
    /* VFCMP_SUNE_S */
13772
    LSX128, LSX128, LSX128, 
13773
    /* VFCMP_SUN_D */
13774
    LSX128, LSX128, LSX128, 
13775
    /* VFCMP_SUN_S */
13776
    LSX128, LSX128, LSX128, 
13777
    /* VFCVTH_D_S */
13778
    LSX128, LSX128, 
13779
    /* VFCVTH_S_H */
13780
    LSX128, LSX128, 
13781
    /* VFCVTL_D_S */
13782
    LSX128, LSX128, 
13783
    /* VFCVTL_S_H */
13784
    LSX128, LSX128, 
13785
    /* VFCVT_H_S */
13786
    LSX128, LSX128, LSX128, 
13787
    /* VFCVT_S_D */
13788
    LSX128, LSX128, LSX128, 
13789
    /* VFDIV_D */
13790
    LSX128, LSX128, LSX128, 
13791
    /* VFDIV_S */
13792
    LSX128, LSX128, LSX128, 
13793
    /* VFFINTH_D_W */
13794
    LSX128, LSX128, 
13795
    /* VFFINTL_D_W */
13796
    LSX128, LSX128, 
13797
    /* VFFINT_D_L */
13798
    LSX128, LSX128, 
13799
    /* VFFINT_D_LU */
13800
    LSX128, LSX128, 
13801
    /* VFFINT_S_L */
13802
    LSX128, LSX128, LSX128, 
13803
    /* VFFINT_S_W */
13804
    LSX128, LSX128, 
13805
    /* VFFINT_S_WU */
13806
    LSX128, LSX128, 
13807
    /* VFLOGB_D */
13808
    LSX128, LSX128, 
13809
    /* VFLOGB_S */
13810
    LSX128, LSX128, 
13811
    /* VFMADD_D */
13812
    LSX128, LSX128, LSX128, LSX128, 
13813
    /* VFMADD_S */
13814
    LSX128, LSX128, LSX128, LSX128, 
13815
    /* VFMAXA_D */
13816
    LSX128, LSX128, LSX128, 
13817
    /* VFMAXA_S */
13818
    LSX128, LSX128, LSX128, 
13819
    /* VFMAX_D */
13820
    LSX128, LSX128, LSX128, 
13821
    /* VFMAX_S */
13822
    LSX128, LSX128, LSX128, 
13823
    /* VFMINA_D */
13824
    LSX128, LSX128, LSX128, 
13825
    /* VFMINA_S */
13826
    LSX128, LSX128, LSX128, 
13827
    /* VFMIN_D */
13828
    LSX128, LSX128, LSX128, 
13829
    /* VFMIN_S */
13830
    LSX128, LSX128, LSX128, 
13831
    /* VFMSUB_D */
13832
    LSX128, LSX128, LSX128, LSX128, 
13833
    /* VFMSUB_S */
13834
    LSX128, LSX128, LSX128, LSX128, 
13835
    /* VFMUL_D */
13836
    LSX128, LSX128, LSX128, 
13837
    /* VFMUL_S */
13838
    LSX128, LSX128, LSX128, 
13839
    /* VFNMADD_D */
13840
    LSX128, LSX128, LSX128, LSX128, 
13841
    /* VFNMADD_S */
13842
    LSX128, LSX128, LSX128, LSX128, 
13843
    /* VFNMSUB_D */
13844
    LSX128, LSX128, LSX128, LSX128, 
13845
    /* VFNMSUB_S */
13846
    LSX128, LSX128, LSX128, LSX128, 
13847
    /* VFRECIPE_D */
13848
    LSX128, LSX128, 
13849
    /* VFRECIPE_S */
13850
    LSX128, LSX128, 
13851
    /* VFRECIP_D */
13852
    LSX128, LSX128, 
13853
    /* VFRECIP_S */
13854
    LSX128, LSX128, 
13855
    /* VFRINTRM_D */
13856
    LSX128, LSX128, 
13857
    /* VFRINTRM_S */
13858
    LSX128, LSX128, 
13859
    /* VFRINTRNE_D */
13860
    LSX128, LSX128, 
13861
    /* VFRINTRNE_S */
13862
    LSX128, LSX128, 
13863
    /* VFRINTRP_D */
13864
    LSX128, LSX128, 
13865
    /* VFRINTRP_S */
13866
    LSX128, LSX128, 
13867
    /* VFRINTRZ_D */
13868
    LSX128, LSX128, 
13869
    /* VFRINTRZ_S */
13870
    LSX128, LSX128, 
13871
    /* VFRINT_D */
13872
    LSX128, LSX128, 
13873
    /* VFRINT_S */
13874
    LSX128, LSX128, 
13875
    /* VFRSQRTE_D */
13876
    LSX128, LSX128, 
13877
    /* VFRSQRTE_S */
13878
    LSX128, LSX128, 
13879
    /* VFRSQRT_D */
13880
    LSX128, LSX128, 
13881
    /* VFRSQRT_S */
13882
    LSX128, LSX128, 
13883
    /* VFRSTPI_B */
13884
    LSX128, LSX128, LSX128, uimm5, 
13885
    /* VFRSTPI_H */
13886
    LSX128, LSX128, LSX128, uimm5, 
13887
    /* VFRSTP_B */
13888
    LSX128, LSX128, LSX128, LSX128, 
13889
    /* VFRSTP_H */
13890
    LSX128, LSX128, LSX128, LSX128, 
13891
    /* VFSQRT_D */
13892
    LSX128, LSX128, 
13893
    /* VFSQRT_S */
13894
    LSX128, LSX128, 
13895
    /* VFSUB_D */
13896
    LSX128, LSX128, LSX128, 
13897
    /* VFSUB_S */
13898
    LSX128, LSX128, LSX128, 
13899
    /* VFTINTH_L_S */
13900
    LSX128, LSX128, 
13901
    /* VFTINTL_L_S */
13902
    LSX128, LSX128, 
13903
    /* VFTINTRMH_L_S */
13904
    LSX128, LSX128, 
13905
    /* VFTINTRML_L_S */
13906
    LSX128, LSX128, 
13907
    /* VFTINTRM_L_D */
13908
    LSX128, LSX128, 
13909
    /* VFTINTRM_W_D */
13910
    LSX128, LSX128, LSX128, 
13911
    /* VFTINTRM_W_S */
13912
    LSX128, LSX128, 
13913
    /* VFTINTRNEH_L_S */
13914
    LSX128, LSX128, 
13915
    /* VFTINTRNEL_L_S */
13916
    LSX128, LSX128, 
13917
    /* VFTINTRNE_L_D */
13918
    LSX128, LSX128, 
13919
    /* VFTINTRNE_W_D */
13920
    LSX128, LSX128, LSX128, 
13921
    /* VFTINTRNE_W_S */
13922
    LSX128, LSX128, 
13923
    /* VFTINTRPH_L_S */
13924
    LSX128, LSX128, 
13925
    /* VFTINTRPL_L_S */
13926
    LSX128, LSX128, 
13927
    /* VFTINTRP_L_D */
13928
    LSX128, LSX128, 
13929
    /* VFTINTRP_W_D */
13930
    LSX128, LSX128, LSX128, 
13931
    /* VFTINTRP_W_S */
13932
    LSX128, LSX128, 
13933
    /* VFTINTRZH_L_S */
13934
    LSX128, LSX128, 
13935
    /* VFTINTRZL_L_S */
13936
    LSX128, LSX128, 
13937
    /* VFTINTRZ_LU_D */
13938
    LSX128, LSX128, 
13939
    /* VFTINTRZ_L_D */
13940
    LSX128, LSX128, 
13941
    /* VFTINTRZ_WU_S */
13942
    LSX128, LSX128, 
13943
    /* VFTINTRZ_W_D */
13944
    LSX128, LSX128, LSX128, 
13945
    /* VFTINTRZ_W_S */
13946
    LSX128, LSX128, 
13947
    /* VFTINT_LU_D */
13948
    LSX128, LSX128, 
13949
    /* VFTINT_L_D */
13950
    LSX128, LSX128, 
13951
    /* VFTINT_WU_S */
13952
    LSX128, LSX128, 
13953
    /* VFTINT_W_D */
13954
    LSX128, LSX128, LSX128, 
13955
    /* VFTINT_W_S */
13956
    LSX128, LSX128, 
13957
    /* VHADDW_DU_WU */
13958
    LSX128, LSX128, LSX128, 
13959
    /* VHADDW_D_W */
13960
    LSX128, LSX128, LSX128, 
13961
    /* VHADDW_HU_BU */
13962
    LSX128, LSX128, LSX128, 
13963
    /* VHADDW_H_B */
13964
    LSX128, LSX128, LSX128, 
13965
    /* VHADDW_QU_DU */
13966
    LSX128, LSX128, LSX128, 
13967
    /* VHADDW_Q_D */
13968
    LSX128, LSX128, LSX128, 
13969
    /* VHADDW_WU_HU */
13970
    LSX128, LSX128, LSX128, 
13971
    /* VHADDW_W_H */
13972
    LSX128, LSX128, LSX128, 
13973
    /* VHSUBW_DU_WU */
13974
    LSX128, LSX128, LSX128, 
13975
    /* VHSUBW_D_W */
13976
    LSX128, LSX128, LSX128, 
13977
    /* VHSUBW_HU_BU */
13978
    LSX128, LSX128, LSX128, 
13979
    /* VHSUBW_H_B */
13980
    LSX128, LSX128, LSX128, 
13981
    /* VHSUBW_QU_DU */
13982
    LSX128, LSX128, LSX128, 
13983
    /* VHSUBW_Q_D */
13984
    LSX128, LSX128, LSX128, 
13985
    /* VHSUBW_WU_HU */
13986
    LSX128, LSX128, LSX128, 
13987
    /* VHSUBW_W_H */
13988
    LSX128, LSX128, LSX128, 
13989
    /* VILVH_B */
13990
    LSX128, LSX128, LSX128, 
13991
    /* VILVH_D */
13992
    LSX128, LSX128, LSX128, 
13993
    /* VILVH_H */
13994
    LSX128, LSX128, LSX128, 
13995
    /* VILVH_W */
13996
    LSX128, LSX128, LSX128, 
13997
    /* VILVL_B */
13998
    LSX128, LSX128, LSX128, 
13999
    /* VILVL_D */
14000
    LSX128, LSX128, LSX128, 
14001
    /* VILVL_H */
14002
    LSX128, LSX128, LSX128, 
14003
    /* VILVL_W */
14004
    LSX128, LSX128, LSX128, 
14005
    /* VINSGR2VR_B */
14006
    LSX128, LSX128, GPR, uimm4, 
14007
    /* VINSGR2VR_D */
14008
    LSX128, LSX128, GPR, uimm1, 
14009
    /* VINSGR2VR_H */
14010
    LSX128, LSX128, GPR, uimm3, 
14011
    /* VINSGR2VR_W */
14012
    LSX128, LSX128, GPR, uimm2, 
14013
    /* VLD */
14014
    LSX128, GPR, simm12, 
14015
    /* VLDI */
14016
    LSX128, simm13, 
14017
    /* VLDREPL_B */
14018
    LSX128, GPR, simm12, 
14019
    /* VLDREPL_D */
14020
    LSX128, GPR, simm9_lsl3, 
14021
    /* VLDREPL_H */
14022
    LSX128, GPR, simm11_lsl1, 
14023
    /* VLDREPL_W */
14024
    LSX128, GPR, simm10_lsl2, 
14025
    /* VLDX */
14026
    LSX128, GPR, GPR, 
14027
    /* VMADDWEV_D_W */
14028
    LSX128, LSX128, LSX128, LSX128, 
14029
    /* VMADDWEV_D_WU */
14030
    LSX128, LSX128, LSX128, LSX128, 
14031
    /* VMADDWEV_D_WU_W */
14032
    LSX128, LSX128, LSX128, LSX128, 
14033
    /* VMADDWEV_H_B */
14034
    LSX128, LSX128, LSX128, LSX128, 
14035
    /* VMADDWEV_H_BU */
14036
    LSX128, LSX128, LSX128, LSX128, 
14037
    /* VMADDWEV_H_BU_B */
14038
    LSX128, LSX128, LSX128, LSX128, 
14039
    /* VMADDWEV_Q_D */
14040
    LSX128, LSX128, LSX128, LSX128, 
14041
    /* VMADDWEV_Q_DU */
14042
    LSX128, LSX128, LSX128, LSX128, 
14043
    /* VMADDWEV_Q_DU_D */
14044
    LSX128, LSX128, LSX128, LSX128, 
14045
    /* VMADDWEV_W_H */
14046
    LSX128, LSX128, LSX128, LSX128, 
14047
    /* VMADDWEV_W_HU */
14048
    LSX128, LSX128, LSX128, LSX128, 
14049
    /* VMADDWEV_W_HU_H */
14050
    LSX128, LSX128, LSX128, LSX128, 
14051
    /* VMADDWOD_D_W */
14052
    LSX128, LSX128, LSX128, LSX128, 
14053
    /* VMADDWOD_D_WU */
14054
    LSX128, LSX128, LSX128, LSX128, 
14055
    /* VMADDWOD_D_WU_W */
14056
    LSX128, LSX128, LSX128, LSX128, 
14057
    /* VMADDWOD_H_B */
14058
    LSX128, LSX128, LSX128, LSX128, 
14059
    /* VMADDWOD_H_BU */
14060
    LSX128, LSX128, LSX128, LSX128, 
14061
    /* VMADDWOD_H_BU_B */
14062
    LSX128, LSX128, LSX128, LSX128, 
14063
    /* VMADDWOD_Q_D */
14064
    LSX128, LSX128, LSX128, LSX128, 
14065
    /* VMADDWOD_Q_DU */
14066
    LSX128, LSX128, LSX128, LSX128, 
14067
    /* VMADDWOD_Q_DU_D */
14068
    LSX128, LSX128, LSX128, LSX128, 
14069
    /* VMADDWOD_W_H */
14070
    LSX128, LSX128, LSX128, LSX128, 
14071
    /* VMADDWOD_W_HU */
14072
    LSX128, LSX128, LSX128, LSX128, 
14073
    /* VMADDWOD_W_HU_H */
14074
    LSX128, LSX128, LSX128, LSX128, 
14075
    /* VMADD_B */
14076
    LSX128, LSX128, LSX128, LSX128, 
14077
    /* VMADD_D */
14078
    LSX128, LSX128, LSX128, LSX128, 
14079
    /* VMADD_H */
14080
    LSX128, LSX128, LSX128, LSX128, 
14081
    /* VMADD_W */
14082
    LSX128, LSX128, LSX128, LSX128, 
14083
    /* VMAXI_B */
14084
    LSX128, LSX128, simm5, 
14085
    /* VMAXI_BU */
14086
    LSX128, LSX128, uimm5, 
14087
    /* VMAXI_D */
14088
    LSX128, LSX128, simm5, 
14089
    /* VMAXI_DU */
14090
    LSX128, LSX128, uimm5, 
14091
    /* VMAXI_H */
14092
    LSX128, LSX128, simm5, 
14093
    /* VMAXI_HU */
14094
    LSX128, LSX128, uimm5, 
14095
    /* VMAXI_W */
14096
    LSX128, LSX128, simm5, 
14097
    /* VMAXI_WU */
14098
    LSX128, LSX128, uimm5, 
14099
    /* VMAX_B */
14100
    LSX128, LSX128, LSX128, 
14101
    /* VMAX_BU */
14102
    LSX128, LSX128, LSX128, 
14103
    /* VMAX_D */
14104
    LSX128, LSX128, LSX128, 
14105
    /* VMAX_DU */
14106
    LSX128, LSX128, LSX128, 
14107
    /* VMAX_H */
14108
    LSX128, LSX128, LSX128, 
14109
    /* VMAX_HU */
14110
    LSX128, LSX128, LSX128, 
14111
    /* VMAX_W */
14112
    LSX128, LSX128, LSX128, 
14113
    /* VMAX_WU */
14114
    LSX128, LSX128, LSX128, 
14115
    /* VMINI_B */
14116
    LSX128, LSX128, simm5, 
14117
    /* VMINI_BU */
14118
    LSX128, LSX128, uimm5, 
14119
    /* VMINI_D */
14120
    LSX128, LSX128, simm5, 
14121
    /* VMINI_DU */
14122
    LSX128, LSX128, uimm5, 
14123
    /* VMINI_H */
14124
    LSX128, LSX128, simm5, 
14125
    /* VMINI_HU */
14126
    LSX128, LSX128, uimm5, 
14127
    /* VMINI_W */
14128
    LSX128, LSX128, simm5, 
14129
    /* VMINI_WU */
14130
    LSX128, LSX128, uimm5, 
14131
    /* VMIN_B */
14132
    LSX128, LSX128, LSX128, 
14133
    /* VMIN_BU */
14134
    LSX128, LSX128, LSX128, 
14135
    /* VMIN_D */
14136
    LSX128, LSX128, LSX128, 
14137
    /* VMIN_DU */
14138
    LSX128, LSX128, LSX128, 
14139
    /* VMIN_H */
14140
    LSX128, LSX128, LSX128, 
14141
    /* VMIN_HU */
14142
    LSX128, LSX128, LSX128, 
14143
    /* VMIN_W */
14144
    LSX128, LSX128, LSX128, 
14145
    /* VMIN_WU */
14146
    LSX128, LSX128, LSX128, 
14147
    /* VMOD_B */
14148
    LSX128, LSX128, LSX128, 
14149
    /* VMOD_BU */
14150
    LSX128, LSX128, LSX128, 
14151
    /* VMOD_D */
14152
    LSX128, LSX128, LSX128, 
14153
    /* VMOD_DU */
14154
    LSX128, LSX128, LSX128, 
14155
    /* VMOD_H */
14156
    LSX128, LSX128, LSX128, 
14157
    /* VMOD_HU */
14158
    LSX128, LSX128, LSX128, 
14159
    /* VMOD_W */
14160
    LSX128, LSX128, LSX128, 
14161
    /* VMOD_WU */
14162
    LSX128, LSX128, LSX128, 
14163
    /* VMSKGEZ_B */
14164
    LSX128, LSX128, 
14165
    /* VMSKLTZ_B */
14166
    LSX128, LSX128, 
14167
    /* VMSKLTZ_D */
14168
    LSX128, LSX128, 
14169
    /* VMSKLTZ_H */
14170
    LSX128, LSX128, 
14171
    /* VMSKLTZ_W */
14172
    LSX128, LSX128, 
14173
    /* VMSKNZ_B */
14174
    LSX128, LSX128, 
14175
    /* VMSUB_B */
14176
    LSX128, LSX128, LSX128, LSX128, 
14177
    /* VMSUB_D */
14178
    LSX128, LSX128, LSX128, LSX128, 
14179
    /* VMSUB_H */
14180
    LSX128, LSX128, LSX128, LSX128, 
14181
    /* VMSUB_W */
14182
    LSX128, LSX128, LSX128, LSX128, 
14183
    /* VMUH_B */
14184
    LSX128, LSX128, LSX128, 
14185
    /* VMUH_BU */
14186
    LSX128, LSX128, LSX128, 
14187
    /* VMUH_D */
14188
    LSX128, LSX128, LSX128, 
14189
    /* VMUH_DU */
14190
    LSX128, LSX128, LSX128, 
14191
    /* VMUH_H */
14192
    LSX128, LSX128, LSX128, 
14193
    /* VMUH_HU */
14194
    LSX128, LSX128, LSX128, 
14195
    /* VMUH_W */
14196
    LSX128, LSX128, LSX128, 
14197
    /* VMUH_WU */
14198
    LSX128, LSX128, LSX128, 
14199
    /* VMULWEV_D_W */
14200
    LSX128, LSX128, LSX128, 
14201
    /* VMULWEV_D_WU */
14202
    LSX128, LSX128, LSX128, 
14203
    /* VMULWEV_D_WU_W */
14204
    LSX128, LSX128, LSX128, 
14205
    /* VMULWEV_H_B */
14206
    LSX128, LSX128, LSX128, 
14207
    /* VMULWEV_H_BU */
14208
    LSX128, LSX128, LSX128, 
14209
    /* VMULWEV_H_BU_B */
14210
    LSX128, LSX128, LSX128, 
14211
    /* VMULWEV_Q_D */
14212
    LSX128, LSX128, LSX128, 
14213
    /* VMULWEV_Q_DU */
14214
    LSX128, LSX128, LSX128, 
14215
    /* VMULWEV_Q_DU_D */
14216
    LSX128, LSX128, LSX128, 
14217
    /* VMULWEV_W_H */
14218
    LSX128, LSX128, LSX128, 
14219
    /* VMULWEV_W_HU */
14220
    LSX128, LSX128, LSX128, 
14221
    /* VMULWEV_W_HU_H */
14222
    LSX128, LSX128, LSX128, 
14223
    /* VMULWOD_D_W */
14224
    LSX128, LSX128, LSX128, 
14225
    /* VMULWOD_D_WU */
14226
    LSX128, LSX128, LSX128, 
14227
    /* VMULWOD_D_WU_W */
14228
    LSX128, LSX128, LSX128, 
14229
    /* VMULWOD_H_B */
14230
    LSX128, LSX128, LSX128, 
14231
    /* VMULWOD_H_BU */
14232
    LSX128, LSX128, LSX128, 
14233
    /* VMULWOD_H_BU_B */
14234
    LSX128, LSX128, LSX128, 
14235
    /* VMULWOD_Q_D */
14236
    LSX128, LSX128, LSX128, 
14237
    /* VMULWOD_Q_DU */
14238
    LSX128, LSX128, LSX128, 
14239
    /* VMULWOD_Q_DU_D */
14240
    LSX128, LSX128, LSX128, 
14241
    /* VMULWOD_W_H */
14242
    LSX128, LSX128, LSX128, 
14243
    /* VMULWOD_W_HU */
14244
    LSX128, LSX128, LSX128, 
14245
    /* VMULWOD_W_HU_H */
14246
    LSX128, LSX128, LSX128, 
14247
    /* VMUL_B */
14248
    LSX128, LSX128, LSX128, 
14249
    /* VMUL_D */
14250
    LSX128, LSX128, LSX128, 
14251
    /* VMUL_H */
14252
    LSX128, LSX128, LSX128, 
14253
    /* VMUL_W */
14254
    LSX128, LSX128, LSX128, 
14255
    /* VNEG_B */
14256
    LSX128, LSX128, 
14257
    /* VNEG_D */
14258
    LSX128, LSX128, 
14259
    /* VNEG_H */
14260
    LSX128, LSX128, 
14261
    /* VNEG_W */
14262
    LSX128, LSX128, 
14263
    /* VNORI_B */
14264
    LSX128, LSX128, uimm8, 
14265
    /* VNOR_V */
14266
    LSX128, LSX128, LSX128, 
14267
    /* VORI_B */
14268
    LSX128, LSX128, uimm8, 
14269
    /* VORN_V */
14270
    LSX128, LSX128, LSX128, 
14271
    /* VOR_V */
14272
    LSX128, LSX128, LSX128, 
14273
    /* VPACKEV_B */
14274
    LSX128, LSX128, LSX128, 
14275
    /* VPACKEV_D */
14276
    LSX128, LSX128, LSX128, 
14277
    /* VPACKEV_H */
14278
    LSX128, LSX128, LSX128, 
14279
    /* VPACKEV_W */
14280
    LSX128, LSX128, LSX128, 
14281
    /* VPACKOD_B */
14282
    LSX128, LSX128, LSX128, 
14283
    /* VPACKOD_D */
14284
    LSX128, LSX128, LSX128, 
14285
    /* VPACKOD_H */
14286
    LSX128, LSX128, LSX128, 
14287
    /* VPACKOD_W */
14288
    LSX128, LSX128, LSX128, 
14289
    /* VPCNT_B */
14290
    LSX128, LSX128, 
14291
    /* VPCNT_D */
14292
    LSX128, LSX128, 
14293
    /* VPCNT_H */
14294
    LSX128, LSX128, 
14295
    /* VPCNT_W */
14296
    LSX128, LSX128, 
14297
    /* VPERMI_W */
14298
    LSX128, LSX128, LSX128, uimm8, 
14299
    /* VPICKEV_B */
14300
    LSX128, LSX128, LSX128, 
14301
    /* VPICKEV_D */
14302
    LSX128, LSX128, LSX128, 
14303
    /* VPICKEV_H */
14304
    LSX128, LSX128, LSX128, 
14305
    /* VPICKEV_W */
14306
    LSX128, LSX128, LSX128, 
14307
    /* VPICKOD_B */
14308
    LSX128, LSX128, LSX128, 
14309
    /* VPICKOD_D */
14310
    LSX128, LSX128, LSX128, 
14311
    /* VPICKOD_H */
14312
    LSX128, LSX128, LSX128, 
14313
    /* VPICKOD_W */
14314
    LSX128, LSX128, LSX128, 
14315
    /* VPICKVE2GR_B */
14316
    GPR, LSX128, uimm4, 
14317
    /* VPICKVE2GR_BU */
14318
    GPR, LSX128, uimm4, 
14319
    /* VPICKVE2GR_D */
14320
    GPR, LSX128, uimm1, 
14321
    /* VPICKVE2GR_DU */
14322
    GPR, LSX128, uimm1, 
14323
    /* VPICKVE2GR_H */
14324
    GPR, LSX128, uimm3, 
14325
    /* VPICKVE2GR_HU */
14326
    GPR, LSX128, uimm3, 
14327
    /* VPICKVE2GR_W */
14328
    GPR, LSX128, uimm2, 
14329
    /* VPICKVE2GR_WU */
14330
    GPR, LSX128, uimm2, 
14331
    /* VREPLGR2VR_B */
14332
    LSX128, GPR, 
14333
    /* VREPLGR2VR_D */
14334
    LSX128, GPR, 
14335
    /* VREPLGR2VR_H */
14336
    LSX128, GPR, 
14337
    /* VREPLGR2VR_W */
14338
    LSX128, GPR, 
14339
    /* VREPLVEI_B */
14340
    LSX128, LSX128, uimm4, 
14341
    /* VREPLVEI_D */
14342
    LSX128, LSX128, uimm1, 
14343
    /* VREPLVEI_H */
14344
    LSX128, LSX128, uimm3, 
14345
    /* VREPLVEI_W */
14346
    LSX128, LSX128, uimm2, 
14347
    /* VREPLVE_B */
14348
    LSX128, LSX128, GPR, 
14349
    /* VREPLVE_D */
14350
    LSX128, LSX128, GPR, 
14351
    /* VREPLVE_H */
14352
    LSX128, LSX128, GPR, 
14353
    /* VREPLVE_W */
14354
    LSX128, LSX128, GPR, 
14355
    /* VROTRI_B */
14356
    LSX128, LSX128, uimm3, 
14357
    /* VROTRI_D */
14358
    LSX128, LSX128, uimm6, 
14359
    /* VROTRI_H */
14360
    LSX128, LSX128, uimm4, 
14361
    /* VROTRI_W */
14362
    LSX128, LSX128, uimm5, 
14363
    /* VROTR_B */
14364
    LSX128, LSX128, LSX128, 
14365
    /* VROTR_D */
14366
    LSX128, LSX128, LSX128, 
14367
    /* VROTR_H */
14368
    LSX128, LSX128, LSX128, 
14369
    /* VROTR_W */
14370
    LSX128, LSX128, LSX128, 
14371
    /* VSADD_B */
14372
    LSX128, LSX128, LSX128, 
14373
    /* VSADD_BU */
14374
    LSX128, LSX128, LSX128, 
14375
    /* VSADD_D */
14376
    LSX128, LSX128, LSX128, 
14377
    /* VSADD_DU */
14378
    LSX128, LSX128, LSX128, 
14379
    /* VSADD_H */
14380
    LSX128, LSX128, LSX128, 
14381
    /* VSADD_HU */
14382
    LSX128, LSX128, LSX128, 
14383
    /* VSADD_W */
14384
    LSX128, LSX128, LSX128, 
14385
    /* VSADD_WU */
14386
    LSX128, LSX128, LSX128, 
14387
    /* VSAT_B */
14388
    LSX128, LSX128, uimm3, 
14389
    /* VSAT_BU */
14390
    LSX128, LSX128, uimm3, 
14391
    /* VSAT_D */
14392
    LSX128, LSX128, uimm6, 
14393
    /* VSAT_DU */
14394
    LSX128, LSX128, uimm6, 
14395
    /* VSAT_H */
14396
    LSX128, LSX128, uimm4, 
14397
    /* VSAT_HU */
14398
    LSX128, LSX128, uimm4, 
14399
    /* VSAT_W */
14400
    LSX128, LSX128, uimm5, 
14401
    /* VSAT_WU */
14402
    LSX128, LSX128, uimm5, 
14403
    /* VSEQI_B */
14404
    LSX128, LSX128, simm5, 
14405
    /* VSEQI_D */
14406
    LSX128, LSX128, simm5, 
14407
    /* VSEQI_H */
14408
    LSX128, LSX128, simm5, 
14409
    /* VSEQI_W */
14410
    LSX128, LSX128, simm5, 
14411
    /* VSEQ_B */
14412
    LSX128, LSX128, LSX128, 
14413
    /* VSEQ_D */
14414
    LSX128, LSX128, LSX128, 
14415
    /* VSEQ_H */
14416
    LSX128, LSX128, LSX128, 
14417
    /* VSEQ_W */
14418
    LSX128, LSX128, LSX128, 
14419
    /* VSETALLNEZ_B */
14420
    CFR, LSX128, 
14421
    /* VSETALLNEZ_D */
14422
    CFR, LSX128, 
14423
    /* VSETALLNEZ_H */
14424
    CFR, LSX128, 
14425
    /* VSETALLNEZ_W */
14426
    CFR, LSX128, 
14427
    /* VSETANYEQZ_B */
14428
    CFR, LSX128, 
14429
    /* VSETANYEQZ_D */
14430
    CFR, LSX128, 
14431
    /* VSETANYEQZ_H */
14432
    CFR, LSX128, 
14433
    /* VSETANYEQZ_W */
14434
    CFR, LSX128, 
14435
    /* VSETEQZ_V */
14436
    CFR, LSX128, 
14437
    /* VSETNEZ_V */
14438
    CFR, LSX128, 
14439
    /* VSHUF4I_B */
14440
    LSX128, LSX128, uimm8, 
14441
    /* VSHUF4I_D */
14442
    LSX128, LSX128, LSX128, uimm8, 
14443
    /* VSHUF4I_H */
14444
    LSX128, LSX128, uimm8, 
14445
    /* VSHUF4I_W */
14446
    LSX128, LSX128, uimm8, 
14447
    /* VSHUF_B */
14448
    LSX128, LSX128, LSX128, LSX128, 
14449
    /* VSHUF_D */
14450
    LSX128, LSX128, LSX128, LSX128, 
14451
    /* VSHUF_H */
14452
    LSX128, LSX128, LSX128, LSX128, 
14453
    /* VSHUF_W */
14454
    LSX128, LSX128, LSX128, LSX128, 
14455
    /* VSIGNCOV_B */
14456
    LSX128, LSX128, LSX128, 
14457
    /* VSIGNCOV_D */
14458
    LSX128, LSX128, LSX128, 
14459
    /* VSIGNCOV_H */
14460
    LSX128, LSX128, LSX128, 
14461
    /* VSIGNCOV_W */
14462
    LSX128, LSX128, LSX128, 
14463
    /* VSLEI_B */
14464
    LSX128, LSX128, simm5, 
14465
    /* VSLEI_BU */
14466
    LSX128, LSX128, uimm5, 
14467
    /* VSLEI_D */
14468
    LSX128, LSX128, simm5, 
14469
    /* VSLEI_DU */
14470
    LSX128, LSX128, uimm5, 
14471
    /* VSLEI_H */
14472
    LSX128, LSX128, simm5, 
14473
    /* VSLEI_HU */
14474
    LSX128, LSX128, uimm5, 
14475
    /* VSLEI_W */
14476
    LSX128, LSX128, simm5, 
14477
    /* VSLEI_WU */
14478
    LSX128, LSX128, uimm5, 
14479
    /* VSLE_B */
14480
    LSX128, LSX128, LSX128, 
14481
    /* VSLE_BU */
14482
    LSX128, LSX128, LSX128, 
14483
    /* VSLE_D */
14484
    LSX128, LSX128, LSX128, 
14485
    /* VSLE_DU */
14486
    LSX128, LSX128, LSX128, 
14487
    /* VSLE_H */
14488
    LSX128, LSX128, LSX128, 
14489
    /* VSLE_HU */
14490
    LSX128, LSX128, LSX128, 
14491
    /* VSLE_W */
14492
    LSX128, LSX128, LSX128, 
14493
    /* VSLE_WU */
14494
    LSX128, LSX128, LSX128, 
14495
    /* VSLLI_B */
14496
    LSX128, LSX128, uimm3, 
14497
    /* VSLLI_D */
14498
    LSX128, LSX128, uimm6, 
14499
    /* VSLLI_H */
14500
    LSX128, LSX128, uimm4, 
14501
    /* VSLLI_W */
14502
    LSX128, LSX128, uimm5, 
14503
    /* VSLLWIL_DU_WU */
14504
    LSX128, LSX128, uimm5, 
14505
    /* VSLLWIL_D_W */
14506
    LSX128, LSX128, uimm5, 
14507
    /* VSLLWIL_HU_BU */
14508
    LSX128, LSX128, uimm3, 
14509
    /* VSLLWIL_H_B */
14510
    LSX128, LSX128, uimm3, 
14511
    /* VSLLWIL_WU_HU */
14512
    LSX128, LSX128, uimm4, 
14513
    /* VSLLWIL_W_H */
14514
    LSX128, LSX128, uimm4, 
14515
    /* VSLL_B */
14516
    LSX128, LSX128, LSX128, 
14517
    /* VSLL_D */
14518
    LSX128, LSX128, LSX128, 
14519
    /* VSLL_H */
14520
    LSX128, LSX128, LSX128, 
14521
    /* VSLL_W */
14522
    LSX128, LSX128, LSX128, 
14523
    /* VSLTI_B */
14524
    LSX128, LSX128, simm5, 
14525
    /* VSLTI_BU */
14526
    LSX128, LSX128, uimm5, 
14527
    /* VSLTI_D */
14528
    LSX128, LSX128, simm5, 
14529
    /* VSLTI_DU */
14530
    LSX128, LSX128, uimm5, 
14531
    /* VSLTI_H */
14532
    LSX128, LSX128, simm5, 
14533
    /* VSLTI_HU */
14534
    LSX128, LSX128, uimm5, 
14535
    /* VSLTI_W */
14536
    LSX128, LSX128, simm5, 
14537
    /* VSLTI_WU */
14538
    LSX128, LSX128, uimm5, 
14539
    /* VSLT_B */
14540
    LSX128, LSX128, LSX128, 
14541
    /* VSLT_BU */
14542
    LSX128, LSX128, LSX128, 
14543
    /* VSLT_D */
14544
    LSX128, LSX128, LSX128, 
14545
    /* VSLT_DU */
14546
    LSX128, LSX128, LSX128, 
14547
    /* VSLT_H */
14548
    LSX128, LSX128, LSX128, 
14549
    /* VSLT_HU */
14550
    LSX128, LSX128, LSX128, 
14551
    /* VSLT_W */
14552
    LSX128, LSX128, LSX128, 
14553
    /* VSLT_WU */
14554
    LSX128, LSX128, LSX128, 
14555
    /* VSRAI_B */
14556
    LSX128, LSX128, uimm3, 
14557
    /* VSRAI_D */
14558
    LSX128, LSX128, uimm6, 
14559
    /* VSRAI_H */
14560
    LSX128, LSX128, uimm4, 
14561
    /* VSRAI_W */
14562
    LSX128, LSX128, uimm5, 
14563
    /* VSRANI_B_H */
14564
    LSX128, LSX128, LSX128, uimm4, 
14565
    /* VSRANI_D_Q */
14566
    LSX128, LSX128, LSX128, uimm7, 
14567
    /* VSRANI_H_W */
14568
    LSX128, LSX128, LSX128, uimm5, 
14569
    /* VSRANI_W_D */
14570
    LSX128, LSX128, LSX128, uimm6, 
14571
    /* VSRAN_B_H */
14572
    LSX128, LSX128, LSX128, 
14573
    /* VSRAN_H_W */
14574
    LSX128, LSX128, LSX128, 
14575
    /* VSRAN_W_D */
14576
    LSX128, LSX128, LSX128, 
14577
    /* VSRARI_B */
14578
    LSX128, LSX128, uimm3, 
14579
    /* VSRARI_D */
14580
    LSX128, LSX128, uimm6, 
14581
    /* VSRARI_H */
14582
    LSX128, LSX128, uimm4, 
14583
    /* VSRARI_W */
14584
    LSX128, LSX128, uimm5, 
14585
    /* VSRARNI_B_H */
14586
    LSX128, LSX128, LSX128, uimm4, 
14587
    /* VSRARNI_D_Q */
14588
    LSX128, LSX128, LSX128, uimm7, 
14589
    /* VSRARNI_H_W */
14590
    LSX128, LSX128, LSX128, uimm5, 
14591
    /* VSRARNI_W_D */
14592
    LSX128, LSX128, LSX128, uimm6, 
14593
    /* VSRARN_B_H */
14594
    LSX128, LSX128, LSX128, 
14595
    /* VSRARN_H_W */
14596
    LSX128, LSX128, LSX128, 
14597
    /* VSRARN_W_D */
14598
    LSX128, LSX128, LSX128, 
14599
    /* VSRAR_B */
14600
    LSX128, LSX128, LSX128, 
14601
    /* VSRAR_D */
14602
    LSX128, LSX128, LSX128, 
14603
    /* VSRAR_H */
14604
    LSX128, LSX128, LSX128, 
14605
    /* VSRAR_W */
14606
    LSX128, LSX128, LSX128, 
14607
    /* VSRA_B */
14608
    LSX128, LSX128, LSX128, 
14609
    /* VSRA_D */
14610
    LSX128, LSX128, LSX128, 
14611
    /* VSRA_H */
14612
    LSX128, LSX128, LSX128, 
14613
    /* VSRA_W */
14614
    LSX128, LSX128, LSX128, 
14615
    /* VSRLI_B */
14616
    LSX128, LSX128, uimm3, 
14617
    /* VSRLI_D */
14618
    LSX128, LSX128, uimm6, 
14619
    /* VSRLI_H */
14620
    LSX128, LSX128, uimm4, 
14621
    /* VSRLI_W */
14622
    LSX128, LSX128, uimm5, 
14623
    /* VSRLNI_B_H */
14624
    LSX128, LSX128, LSX128, uimm4, 
14625
    /* VSRLNI_D_Q */
14626
    LSX128, LSX128, LSX128, uimm7, 
14627
    /* VSRLNI_H_W */
14628
    LSX128, LSX128, LSX128, uimm5, 
14629
    /* VSRLNI_W_D */
14630
    LSX128, LSX128, LSX128, uimm6, 
14631
    /* VSRLN_B_H */
14632
    LSX128, LSX128, LSX128, 
14633
    /* VSRLN_H_W */
14634
    LSX128, LSX128, LSX128, 
14635
    /* VSRLN_W_D */
14636
    LSX128, LSX128, LSX128, 
14637
    /* VSRLRI_B */
14638
    LSX128, LSX128, uimm3, 
14639
    /* VSRLRI_D */
14640
    LSX128, LSX128, uimm6, 
14641
    /* VSRLRI_H */
14642
    LSX128, LSX128, uimm4, 
14643
    /* VSRLRI_W */
14644
    LSX128, LSX128, uimm5, 
14645
    /* VSRLRNI_B_H */
14646
    LSX128, LSX128, LSX128, uimm4, 
14647
    /* VSRLRNI_D_Q */
14648
    LSX128, LSX128, LSX128, uimm7, 
14649
    /* VSRLRNI_H_W */
14650
    LSX128, LSX128, LSX128, uimm5, 
14651
    /* VSRLRNI_W_D */
14652
    LSX128, LSX128, LSX128, uimm6, 
14653
    /* VSRLRN_B_H */
14654
    LSX128, LSX128, LSX128, 
14655
    /* VSRLRN_H_W */
14656
    LSX128, LSX128, LSX128, 
14657
    /* VSRLRN_W_D */
14658
    LSX128, LSX128, LSX128, 
14659
    /* VSRLR_B */
14660
    LSX128, LSX128, LSX128, 
14661
    /* VSRLR_D */
14662
    LSX128, LSX128, LSX128, 
14663
    /* VSRLR_H */
14664
    LSX128, LSX128, LSX128, 
14665
    /* VSRLR_W */
14666
    LSX128, LSX128, LSX128, 
14667
    /* VSRL_B */
14668
    LSX128, LSX128, LSX128, 
14669
    /* VSRL_D */
14670
    LSX128, LSX128, LSX128, 
14671
    /* VSRL_H */
14672
    LSX128, LSX128, LSX128, 
14673
    /* VSRL_W */
14674
    LSX128, LSX128, LSX128, 
14675
    /* VSSRANI_BU_H */
14676
    LSX128, LSX128, LSX128, uimm4, 
14677
    /* VSSRANI_B_H */
14678
    LSX128, LSX128, LSX128, uimm4, 
14679
    /* VSSRANI_DU_Q */
14680
    LSX128, LSX128, LSX128, uimm7, 
14681
    /* VSSRANI_D_Q */
14682
    LSX128, LSX128, LSX128, uimm7, 
14683
    /* VSSRANI_HU_W */
14684
    LSX128, LSX128, LSX128, uimm5, 
14685
    /* VSSRANI_H_W */
14686
    LSX128, LSX128, LSX128, uimm5, 
14687
    /* VSSRANI_WU_D */
14688
    LSX128, LSX128, LSX128, uimm6, 
14689
    /* VSSRANI_W_D */
14690
    LSX128, LSX128, LSX128, uimm6, 
14691
    /* VSSRAN_BU_H */
14692
    LSX128, LSX128, LSX128, 
14693
    /* VSSRAN_B_H */
14694
    LSX128, LSX128, LSX128, 
14695
    /* VSSRAN_HU_W */
14696
    LSX128, LSX128, LSX128, 
14697
    /* VSSRAN_H_W */
14698
    LSX128, LSX128, LSX128, 
14699
    /* VSSRAN_WU_D */
14700
    LSX128, LSX128, LSX128, 
14701
    /* VSSRAN_W_D */
14702
    LSX128, LSX128, LSX128, 
14703
    /* VSSRARNI_BU_H */
14704
    LSX128, LSX128, LSX128, uimm4, 
14705
    /* VSSRARNI_B_H */
14706
    LSX128, LSX128, LSX128, uimm4, 
14707
    /* VSSRARNI_DU_Q */
14708
    LSX128, LSX128, LSX128, uimm7, 
14709
    /* VSSRARNI_D_Q */
14710
    LSX128, LSX128, LSX128, uimm7, 
14711
    /* VSSRARNI_HU_W */
14712
    LSX128, LSX128, LSX128, uimm5, 
14713
    /* VSSRARNI_H_W */
14714
    LSX128, LSX128, LSX128, uimm5, 
14715
    /* VSSRARNI_WU_D */
14716
    LSX128, LSX128, LSX128, uimm6, 
14717
    /* VSSRARNI_W_D */
14718
    LSX128, LSX128, LSX128, uimm6, 
14719
    /* VSSRARN_BU_H */
14720
    LSX128, LSX128, LSX128, 
14721
    /* VSSRARN_B_H */
14722
    LSX128, LSX128, LSX128, 
14723
    /* VSSRARN_HU_W */
14724
    LSX128, LSX128, LSX128, 
14725
    /* VSSRARN_H_W */
14726
    LSX128, LSX128, LSX128, 
14727
    /* VSSRARN_WU_D */
14728
    LSX128, LSX128, LSX128, 
14729
    /* VSSRARN_W_D */
14730
    LSX128, LSX128, LSX128, 
14731
    /* VSSRLNI_BU_H */
14732
    LSX128, LSX128, LSX128, uimm4, 
14733
    /* VSSRLNI_B_H */
14734
    LSX128, LSX128, LSX128, uimm4, 
14735
    /* VSSRLNI_DU_Q */
14736
    LSX128, LSX128, LSX128, uimm7, 
14737
    /* VSSRLNI_D_Q */
14738
    LSX128, LSX128, LSX128, uimm7, 
14739
    /* VSSRLNI_HU_W */
14740
    LSX128, LSX128, LSX128, uimm5, 
14741
    /* VSSRLNI_H_W */
14742
    LSX128, LSX128, LSX128, uimm5, 
14743
    /* VSSRLNI_WU_D */
14744
    LSX128, LSX128, LSX128, uimm6, 
14745
    /* VSSRLNI_W_D */
14746
    LSX128, LSX128, LSX128, uimm6, 
14747
    /* VSSRLN_BU_H */
14748
    LSX128, LSX128, LSX128, 
14749
    /* VSSRLN_B_H */
14750
    LSX128, LSX128, LSX128, 
14751
    /* VSSRLN_HU_W */
14752
    LSX128, LSX128, LSX128, 
14753
    /* VSSRLN_H_W */
14754
    LSX128, LSX128, LSX128, 
14755
    /* VSSRLN_WU_D */
14756
    LSX128, LSX128, LSX128, 
14757
    /* VSSRLN_W_D */
14758
    LSX128, LSX128, LSX128, 
14759
    /* VSSRLRNI_BU_H */
14760
    LSX128, LSX128, LSX128, uimm4, 
14761
    /* VSSRLRNI_B_H */
14762
    LSX128, LSX128, LSX128, uimm4, 
14763
    /* VSSRLRNI_DU_Q */
14764
    LSX128, LSX128, LSX128, uimm7, 
14765
    /* VSSRLRNI_D_Q */
14766
    LSX128, LSX128, LSX128, uimm7, 
14767
    /* VSSRLRNI_HU_W */
14768
    LSX128, LSX128, LSX128, uimm5, 
14769
    /* VSSRLRNI_H_W */
14770
    LSX128, LSX128, LSX128, uimm5, 
14771
    /* VSSRLRNI_WU_D */
14772
    LSX128, LSX128, LSX128, uimm6, 
14773
    /* VSSRLRNI_W_D */
14774
    LSX128, LSX128, LSX128, uimm6, 
14775
    /* VSSRLRN_BU_H */
14776
    LSX128, LSX128, LSX128, 
14777
    /* VSSRLRN_B_H */
14778
    LSX128, LSX128, LSX128, 
14779
    /* VSSRLRN_HU_W */
14780
    LSX128, LSX128, LSX128, 
14781
    /* VSSRLRN_H_W */
14782
    LSX128, LSX128, LSX128, 
14783
    /* VSSRLRN_WU_D */
14784
    LSX128, LSX128, LSX128, 
14785
    /* VSSRLRN_W_D */
14786
    LSX128, LSX128, LSX128, 
14787
    /* VSSUB_B */
14788
    LSX128, LSX128, LSX128, 
14789
    /* VSSUB_BU */
14790
    LSX128, LSX128, LSX128, 
14791
    /* VSSUB_D */
14792
    LSX128, LSX128, LSX128, 
14793
    /* VSSUB_DU */
14794
    LSX128, LSX128, LSX128, 
14795
    /* VSSUB_H */
14796
    LSX128, LSX128, LSX128, 
14797
    /* VSSUB_HU */
14798
    LSX128, LSX128, LSX128, 
14799
    /* VSSUB_W */
14800
    LSX128, LSX128, LSX128, 
14801
    /* VSSUB_WU */
14802
    LSX128, LSX128, LSX128, 
14803
    /* VST */
14804
    LSX128, GPR, simm12, 
14805
    /* VSTELM_B */
14806
    LSX128, GPR, simm8, uimm4, 
14807
    /* VSTELM_D */
14808
    LSX128, GPR, simm8_lsl3, uimm1, 
14809
    /* VSTELM_H */
14810
    LSX128, GPR, simm8_lsl1, uimm3, 
14811
    /* VSTELM_W */
14812
    LSX128, GPR, simm8_lsl2, uimm2, 
14813
    /* VSTX */
14814
    LSX128, GPR, GPR, 
14815
    /* VSUBI_BU */
14816
    LSX128, LSX128, uimm5, 
14817
    /* VSUBI_DU */
14818
    LSX128, LSX128, uimm5, 
14819
    /* VSUBI_HU */
14820
    LSX128, LSX128, uimm5, 
14821
    /* VSUBI_WU */
14822
    LSX128, LSX128, uimm5, 
14823
    /* VSUBWEV_D_W */
14824
    LSX128, LSX128, LSX128, 
14825
    /* VSUBWEV_D_WU */
14826
    LSX128, LSX128, LSX128, 
14827
    /* VSUBWEV_H_B */
14828
    LSX128, LSX128, LSX128, 
14829
    /* VSUBWEV_H_BU */
14830
    LSX128, LSX128, LSX128, 
14831
    /* VSUBWEV_Q_D */
14832
    LSX128, LSX128, LSX128, 
14833
    /* VSUBWEV_Q_DU */
14834
    LSX128, LSX128, LSX128, 
14835
    /* VSUBWEV_W_H */
14836
    LSX128, LSX128, LSX128, 
14837
    /* VSUBWEV_W_HU */
14838
    LSX128, LSX128, LSX128, 
14839
    /* VSUBWOD_D_W */
14840
    LSX128, LSX128, LSX128, 
14841
    /* VSUBWOD_D_WU */
14842
    LSX128, LSX128, LSX128, 
14843
    /* VSUBWOD_H_B */
14844
    LSX128, LSX128, LSX128, 
14845
    /* VSUBWOD_H_BU */
14846
    LSX128, LSX128, LSX128, 
14847
    /* VSUBWOD_Q_D */
14848
    LSX128, LSX128, LSX128, 
14849
    /* VSUBWOD_Q_DU */
14850
    LSX128, LSX128, LSX128, 
14851
    /* VSUBWOD_W_H */
14852
    LSX128, LSX128, LSX128, 
14853
    /* VSUBWOD_W_HU */
14854
    LSX128, LSX128, LSX128, 
14855
    /* VSUB_B */
14856
    LSX128, LSX128, LSX128, 
14857
    /* VSUB_D */
14858
    LSX128, LSX128, LSX128, 
14859
    /* VSUB_H */
14860
    LSX128, LSX128, LSX128, 
14861
    /* VSUB_Q */
14862
    LSX128, LSX128, LSX128, 
14863
    /* VSUB_W */
14864
    LSX128, LSX128, LSX128, 
14865
    /* VXORI_B */
14866
    LSX128, LSX128, uimm8, 
14867
    /* VXOR_V */
14868
    LSX128, LSX128, LSX128, 
14869
    /* X86ADC_B */
14870
    GPR, GPR, 
14871
    /* X86ADC_D */
14872
    GPR, GPR, 
14873
    /* X86ADC_H */
14874
    GPR, GPR, 
14875
    /* X86ADC_W */
14876
    GPR, GPR, 
14877
    /* X86ADD_B */
14878
    GPR, GPR, 
14879
    /* X86ADD_D */
14880
    GPR, GPR, 
14881
    /* X86ADD_DU */
14882
    GPR, GPR, 
14883
    /* X86ADD_H */
14884
    GPR, GPR, 
14885
    /* X86ADD_W */
14886
    GPR, GPR, 
14887
    /* X86ADD_WU */
14888
    GPR, GPR, 
14889
    /* X86AND_B */
14890
    GPR, GPR, 
14891
    /* X86AND_D */
14892
    GPR, GPR, 
14893
    /* X86AND_H */
14894
    GPR, GPR, 
14895
    /* X86AND_W */
14896
    GPR, GPR, 
14897
    /* X86CLRTM */
14898
    /* X86DECTOP */
14899
    /* X86DEC_B */
14900
    GPR, 
14901
    /* X86DEC_D */
14902
    GPR, 
14903
    /* X86DEC_H */
14904
    GPR, 
14905
    /* X86DEC_W */
14906
    GPR, 
14907
    /* X86INCTOP */
14908
    /* X86INC_B */
14909
    GPR, 
14910
    /* X86INC_D */
14911
    GPR, 
14912
    /* X86INC_H */
14913
    GPR, 
14914
    /* X86INC_W */
14915
    GPR, 
14916
    /* X86MFFLAG */
14917
    GPR, uimm8, 
14918
    /* X86MFTOP */
14919
    GPR, 
14920
    /* X86MTFLAG */
14921
    GPR, uimm8, 
14922
    /* X86MTTOP */
14923
    uimm3, 
14924
    /* X86MUL_B */
14925
    GPR, GPR, 
14926
    /* X86MUL_BU */
14927
    GPR, GPR, 
14928
    /* X86MUL_D */
14929
    GPR, GPR, 
14930
    /* X86MUL_DU */
14931
    GPR, GPR, 
14932
    /* X86MUL_H */
14933
    GPR, GPR, 
14934
    /* X86MUL_HU */
14935
    GPR, GPR, 
14936
    /* X86MUL_W */
14937
    GPR, GPR, 
14938
    /* X86MUL_WU */
14939
    GPR, GPR, 
14940
    /* X86OR_B */
14941
    GPR, GPR, 
14942
    /* X86OR_D */
14943
    GPR, GPR, 
14944
    /* X86OR_H */
14945
    GPR, GPR, 
14946
    /* X86OR_W */
14947
    GPR, GPR, 
14948
    /* X86RCLI_B */
14949
    GPR, uimm3, 
14950
    /* X86RCLI_D */
14951
    GPR, uimm6, 
14952
    /* X86RCLI_H */
14953
    GPR, uimm4, 
14954
    /* X86RCLI_W */
14955
    GPR, uimm5, 
14956
    /* X86RCL_B */
14957
    GPR, GPR, 
14958
    /* X86RCL_D */
14959
    GPR, GPR, 
14960
    /* X86RCL_H */
14961
    GPR, GPR, 
14962
    /* X86RCL_W */
14963
    GPR, GPR, 
14964
    /* X86RCRI_B */
14965
    GPR, uimm3, 
14966
    /* X86RCRI_D */
14967
    GPR, uimm6, 
14968
    /* X86RCRI_H */
14969
    GPR, uimm4, 
14970
    /* X86RCRI_W */
14971
    GPR, uimm5, 
14972
    /* X86RCR_B */
14973
    GPR, GPR, 
14974
    /* X86RCR_D */
14975
    GPR, GPR, 
14976
    /* X86RCR_H */
14977
    GPR, GPR, 
14978
    /* X86RCR_W */
14979
    GPR, GPR, 
14980
    /* X86ROTLI_B */
14981
    GPR, uimm3, 
14982
    /* X86ROTLI_D */
14983
    GPR, uimm6, 
14984
    /* X86ROTLI_H */
14985
    GPR, uimm4, 
14986
    /* X86ROTLI_W */
14987
    GPR, uimm5, 
14988
    /* X86ROTL_B */
14989
    GPR, GPR, 
14990
    /* X86ROTL_D */
14991
    GPR, GPR, 
14992
    /* X86ROTL_H */
14993
    GPR, GPR, 
14994
    /* X86ROTL_W */
14995
    GPR, GPR, 
14996
    /* X86ROTRI_B */
14997
    GPR, uimm3, 
14998
    /* X86ROTRI_D */
14999
    GPR, uimm6, 
15000
    /* X86ROTRI_H */
15001
    GPR, uimm4, 
15002
    /* X86ROTRI_W */
15003
    GPR, uimm5, 
15004
    /* X86ROTR_B */
15005
    GPR, GPR, 
15006
    /* X86ROTR_D */
15007
    GPR, GPR, 
15008
    /* X86ROTR_H */
15009
    GPR, GPR, 
15010
    /* X86ROTR_W */
15011
    GPR, GPR, 
15012
    /* X86SBC_B */
15013
    GPR, GPR, 
15014
    /* X86SBC_D */
15015
    GPR, GPR, 
15016
    /* X86SBC_H */
15017
    GPR, GPR, 
15018
    /* X86SBC_W */
15019
    GPR, GPR, 
15020
    /* X86SETTAG */
15021
    GPR, uimm5, uimm8, 
15022
    /* X86SETTM */
15023
    /* X86SLLI_B */
15024
    GPR, uimm3, 
15025
    /* X86SLLI_D */
15026
    GPR, uimm6, 
15027
    /* X86SLLI_H */
15028
    GPR, uimm4, 
15029
    /* X86SLLI_W */
15030
    GPR, uimm5, 
15031
    /* X86SLL_B */
15032
    GPR, GPR, 
15033
    /* X86SLL_D */
15034
    GPR, GPR, 
15035
    /* X86SLL_H */
15036
    GPR, GPR, 
15037
    /* X86SLL_W */
15038
    GPR, GPR, 
15039
    /* X86SRAI_B */
15040
    GPR, uimm3, 
15041
    /* X86SRAI_D */
15042
    GPR, uimm6, 
15043
    /* X86SRAI_H */
15044
    GPR, uimm4, 
15045
    /* X86SRAI_W */
15046
    GPR, uimm5, 
15047
    /* X86SRA_B */
15048
    GPR, GPR, 
15049
    /* X86SRA_D */
15050
    GPR, GPR, 
15051
    /* X86SRA_H */
15052
    GPR, GPR, 
15053
    /* X86SRA_W */
15054
    GPR, GPR, 
15055
    /* X86SRLI_B */
15056
    GPR, uimm3, 
15057
    /* X86SRLI_D */
15058
    GPR, uimm6, 
15059
    /* X86SRLI_H */
15060
    GPR, uimm4, 
15061
    /* X86SRLI_W */
15062
    GPR, uimm5, 
15063
    /* X86SRL_B */
15064
    GPR, GPR, 
15065
    /* X86SRL_D */
15066
    GPR, GPR, 
15067
    /* X86SRL_H */
15068
    GPR, GPR, 
15069
    /* X86SRL_W */
15070
    GPR, GPR, 
15071
    /* X86SUB_B */
15072
    GPR, GPR, 
15073
    /* X86SUB_D */
15074
    GPR, GPR, 
15075
    /* X86SUB_DU */
15076
    GPR, GPR, 
15077
    /* X86SUB_H */
15078
    GPR, GPR, 
15079
    /* X86SUB_W */
15080
    GPR, GPR, 
15081
    /* X86SUB_WU */
15082
    GPR, GPR, 
15083
    /* X86XOR_B */
15084
    GPR, GPR, 
15085
    /* X86XOR_D */
15086
    GPR, GPR, 
15087
    /* X86XOR_H */
15088
    GPR, GPR, 
15089
    /* X86XOR_W */
15090
    GPR, GPR, 
15091
    /* XOR */
15092
    GPR, GPR, GPR, 
15093
    /* XORI */
15094
    GPR, GPR, uimm12, 
15095
    /* XVABSD_B */
15096
    LASX256, LASX256, LASX256, 
15097
    /* XVABSD_BU */
15098
    LASX256, LASX256, LASX256, 
15099
    /* XVABSD_D */
15100
    LASX256, LASX256, LASX256, 
15101
    /* XVABSD_DU */
15102
    LASX256, LASX256, LASX256, 
15103
    /* XVABSD_H */
15104
    LASX256, LASX256, LASX256, 
15105
    /* XVABSD_HU */
15106
    LASX256, LASX256, LASX256, 
15107
    /* XVABSD_W */
15108
    LASX256, LASX256, LASX256, 
15109
    /* XVABSD_WU */
15110
    LASX256, LASX256, LASX256, 
15111
    /* XVADDA_B */
15112
    LASX256, LASX256, LASX256, 
15113
    /* XVADDA_D */
15114
    LASX256, LASX256, LASX256, 
15115
    /* XVADDA_H */
15116
    LASX256, LASX256, LASX256, 
15117
    /* XVADDA_W */
15118
    LASX256, LASX256, LASX256, 
15119
    /* XVADDI_BU */
15120
    LASX256, LASX256, uimm5, 
15121
    /* XVADDI_DU */
15122
    LASX256, LASX256, uimm5, 
15123
    /* XVADDI_HU */
15124
    LASX256, LASX256, uimm5, 
15125
    /* XVADDI_WU */
15126
    LASX256, LASX256, uimm5, 
15127
    /* XVADDWEV_D_W */
15128
    LASX256, LASX256, LASX256, 
15129
    /* XVADDWEV_D_WU */
15130
    LASX256, LASX256, LASX256, 
15131
    /* XVADDWEV_D_WU_W */
15132
    LASX256, LASX256, LASX256, 
15133
    /* XVADDWEV_H_B */
15134
    LASX256, LASX256, LASX256, 
15135
    /* XVADDWEV_H_BU */
15136
    LASX256, LASX256, LASX256, 
15137
    /* XVADDWEV_H_BU_B */
15138
    LASX256, LASX256, LASX256, 
15139
    /* XVADDWEV_Q_D */
15140
    LASX256, LASX256, LASX256, 
15141
    /* XVADDWEV_Q_DU */
15142
    LASX256, LASX256, LASX256, 
15143
    /* XVADDWEV_Q_DU_D */
15144
    LASX256, LASX256, LASX256, 
15145
    /* XVADDWEV_W_H */
15146
    LASX256, LASX256, LASX256, 
15147
    /* XVADDWEV_W_HU */
15148
    LASX256, LASX256, LASX256, 
15149
    /* XVADDWEV_W_HU_H */
15150
    LASX256, LASX256, LASX256, 
15151
    /* XVADDWOD_D_W */
15152
    LASX256, LASX256, LASX256, 
15153
    /* XVADDWOD_D_WU */
15154
    LASX256, LASX256, LASX256, 
15155
    /* XVADDWOD_D_WU_W */
15156
    LASX256, LASX256, LASX256, 
15157
    /* XVADDWOD_H_B */
15158
    LASX256, LASX256, LASX256, 
15159
    /* XVADDWOD_H_BU */
15160
    LASX256, LASX256, LASX256, 
15161
    /* XVADDWOD_H_BU_B */
15162
    LASX256, LASX256, LASX256, 
15163
    /* XVADDWOD_Q_D */
15164
    LASX256, LASX256, LASX256, 
15165
    /* XVADDWOD_Q_DU */
15166
    LASX256, LASX256, LASX256, 
15167
    /* XVADDWOD_Q_DU_D */
15168
    LASX256, LASX256, LASX256, 
15169
    /* XVADDWOD_W_H */
15170
    LASX256, LASX256, LASX256, 
15171
    /* XVADDWOD_W_HU */
15172
    LASX256, LASX256, LASX256, 
15173
    /* XVADDWOD_W_HU_H */
15174
    LASX256, LASX256, LASX256, 
15175
    /* XVADD_B */
15176
    LASX256, LASX256, LASX256, 
15177
    /* XVADD_D */
15178
    LASX256, LASX256, LASX256, 
15179
    /* XVADD_H */
15180
    LASX256, LASX256, LASX256, 
15181
    /* XVADD_Q */
15182
    LASX256, LASX256, LASX256, 
15183
    /* XVADD_W */
15184
    LASX256, LASX256, LASX256, 
15185
    /* XVANDI_B */
15186
    LASX256, LASX256, uimm8, 
15187
    /* XVANDN_V */
15188
    LASX256, LASX256, LASX256, 
15189
    /* XVAND_V */
15190
    LASX256, LASX256, LASX256, 
15191
    /* XVAVGR_B */
15192
    LASX256, LASX256, LASX256, 
15193
    /* XVAVGR_BU */
15194
    LASX256, LASX256, LASX256, 
15195
    /* XVAVGR_D */
15196
    LASX256, LASX256, LASX256, 
15197
    /* XVAVGR_DU */
15198
    LASX256, LASX256, LASX256, 
15199
    /* XVAVGR_H */
15200
    LASX256, LASX256, LASX256, 
15201
    /* XVAVGR_HU */
15202
    LASX256, LASX256, LASX256, 
15203
    /* XVAVGR_W */
15204
    LASX256, LASX256, LASX256, 
15205
    /* XVAVGR_WU */
15206
    LASX256, LASX256, LASX256, 
15207
    /* XVAVG_B */
15208
    LASX256, LASX256, LASX256, 
15209
    /* XVAVG_BU */
15210
    LASX256, LASX256, LASX256, 
15211
    /* XVAVG_D */
15212
    LASX256, LASX256, LASX256, 
15213
    /* XVAVG_DU */
15214
    LASX256, LASX256, LASX256, 
15215
    /* XVAVG_H */
15216
    LASX256, LASX256, LASX256, 
15217
    /* XVAVG_HU */
15218
    LASX256, LASX256, LASX256, 
15219
    /* XVAVG_W */
15220
    LASX256, LASX256, LASX256, 
15221
    /* XVAVG_WU */
15222
    LASX256, LASX256, LASX256, 
15223
    /* XVBITCLRI_B */
15224
    LASX256, LASX256, uimm3, 
15225
    /* XVBITCLRI_D */
15226
    LASX256, LASX256, uimm6, 
15227
    /* XVBITCLRI_H */
15228
    LASX256, LASX256, uimm4, 
15229
    /* XVBITCLRI_W */
15230
    LASX256, LASX256, uimm5, 
15231
    /* XVBITCLR_B */
15232
    LASX256, LASX256, LASX256, 
15233
    /* XVBITCLR_D */
15234
    LASX256, LASX256, LASX256, 
15235
    /* XVBITCLR_H */
15236
    LASX256, LASX256, LASX256, 
15237
    /* XVBITCLR_W */
15238
    LASX256, LASX256, LASX256, 
15239
    /* XVBITREVI_B */
15240
    LASX256, LASX256, uimm3, 
15241
    /* XVBITREVI_D */
15242
    LASX256, LASX256, uimm6, 
15243
    /* XVBITREVI_H */
15244
    LASX256, LASX256, uimm4, 
15245
    /* XVBITREVI_W */
15246
    LASX256, LASX256, uimm5, 
15247
    /* XVBITREV_B */
15248
    LASX256, LASX256, LASX256, 
15249
    /* XVBITREV_D */
15250
    LASX256, LASX256, LASX256, 
15251
    /* XVBITREV_H */
15252
    LASX256, LASX256, LASX256, 
15253
    /* XVBITREV_W */
15254
    LASX256, LASX256, LASX256, 
15255
    /* XVBITSELI_B */
15256
    LASX256, LASX256, LASX256, uimm8, 
15257
    /* XVBITSEL_V */
15258
    LASX256, LASX256, LASX256, LASX256, 
15259
    /* XVBITSETI_B */
15260
    LASX256, LASX256, uimm3, 
15261
    /* XVBITSETI_D */
15262
    LASX256, LASX256, uimm6, 
15263
    /* XVBITSETI_H */
15264
    LASX256, LASX256, uimm4, 
15265
    /* XVBITSETI_W */
15266
    LASX256, LASX256, uimm5, 
15267
    /* XVBITSET_B */
15268
    LASX256, LASX256, LASX256, 
15269
    /* XVBITSET_D */
15270
    LASX256, LASX256, LASX256, 
15271
    /* XVBITSET_H */
15272
    LASX256, LASX256, LASX256, 
15273
    /* XVBITSET_W */
15274
    LASX256, LASX256, LASX256, 
15275
    /* XVBSLL_V */
15276
    LASX256, LASX256, uimm5, 
15277
    /* XVBSRL_V */
15278
    LASX256, LASX256, uimm5, 
15279
    /* XVCLO_B */
15280
    LASX256, LASX256, 
15281
    /* XVCLO_D */
15282
    LASX256, LASX256, 
15283
    /* XVCLO_H */
15284
    LASX256, LASX256, 
15285
    /* XVCLO_W */
15286
    LASX256, LASX256, 
15287
    /* XVCLZ_B */
15288
    LASX256, LASX256, 
15289
    /* XVCLZ_D */
15290
    LASX256, LASX256, 
15291
    /* XVCLZ_H */
15292
    LASX256, LASX256, 
15293
    /* XVCLZ_W */
15294
    LASX256, LASX256, 
15295
    /* XVDIV_B */
15296
    LASX256, LASX256, LASX256, 
15297
    /* XVDIV_BU */
15298
    LASX256, LASX256, LASX256, 
15299
    /* XVDIV_D */
15300
    LASX256, LASX256, LASX256, 
15301
    /* XVDIV_DU */
15302
    LASX256, LASX256, LASX256, 
15303
    /* XVDIV_H */
15304
    LASX256, LASX256, LASX256, 
15305
    /* XVDIV_HU */
15306
    LASX256, LASX256, LASX256, 
15307
    /* XVDIV_W */
15308
    LASX256, LASX256, LASX256, 
15309
    /* XVDIV_WU */
15310
    LASX256, LASX256, LASX256, 
15311
    /* XVEXTH_DU_WU */
15312
    LASX256, LASX256, 
15313
    /* XVEXTH_D_W */
15314
    LASX256, LASX256, 
15315
    /* XVEXTH_HU_BU */
15316
    LASX256, LASX256, 
15317
    /* XVEXTH_H_B */
15318
    LASX256, LASX256, 
15319
    /* XVEXTH_QU_DU */
15320
    LASX256, LASX256, 
15321
    /* XVEXTH_Q_D */
15322
    LASX256, LASX256, 
15323
    /* XVEXTH_WU_HU */
15324
    LASX256, LASX256, 
15325
    /* XVEXTH_W_H */
15326
    LASX256, LASX256, 
15327
    /* XVEXTL_QU_DU */
15328
    LASX256, LASX256, 
15329
    /* XVEXTL_Q_D */
15330
    LASX256, LASX256, 
15331
    /* XVEXTRINS_B */
15332
    LASX256, LASX256, LASX256, uimm8, 
15333
    /* XVEXTRINS_D */
15334
    LASX256, LASX256, LASX256, uimm8, 
15335
    /* XVEXTRINS_H */
15336
    LASX256, LASX256, LASX256, uimm8, 
15337
    /* XVEXTRINS_W */
15338
    LASX256, LASX256, LASX256, uimm8, 
15339
    /* XVFADD_D */
15340
    LASX256, LASX256, LASX256, 
15341
    /* XVFADD_S */
15342
    LASX256, LASX256, LASX256, 
15343
    /* XVFCLASS_D */
15344
    LASX256, LASX256, 
15345
    /* XVFCLASS_S */
15346
    LASX256, LASX256, 
15347
    /* XVFCMP_CAF_D */
15348
    LASX256, LASX256, LASX256, 
15349
    /* XVFCMP_CAF_S */
15350
    LASX256, LASX256, LASX256, 
15351
    /* XVFCMP_CEQ_D */
15352
    LASX256, LASX256, LASX256, 
15353
    /* XVFCMP_CEQ_S */
15354
    LASX256, LASX256, LASX256, 
15355
    /* XVFCMP_CLE_D */
15356
    LASX256, LASX256, LASX256, 
15357
    /* XVFCMP_CLE_S */
15358
    LASX256, LASX256, LASX256, 
15359
    /* XVFCMP_CLT_D */
15360
    LASX256, LASX256, LASX256, 
15361
    /* XVFCMP_CLT_S */
15362
    LASX256, LASX256, LASX256, 
15363
    /* XVFCMP_CNE_D */
15364
    LASX256, LASX256, LASX256, 
15365
    /* XVFCMP_CNE_S */
15366
    LASX256, LASX256, LASX256, 
15367
    /* XVFCMP_COR_D */
15368
    LASX256, LASX256, LASX256, 
15369
    /* XVFCMP_COR_S */
15370
    LASX256, LASX256, LASX256, 
15371
    /* XVFCMP_CUEQ_D */
15372
    LASX256, LASX256, LASX256, 
15373
    /* XVFCMP_CUEQ_S */
15374
    LASX256, LASX256, LASX256, 
15375
    /* XVFCMP_CULE_D */
15376
    LASX256, LASX256, LASX256, 
15377
    /* XVFCMP_CULE_S */
15378
    LASX256, LASX256, LASX256, 
15379
    /* XVFCMP_CULT_D */
15380
    LASX256, LASX256, LASX256, 
15381
    /* XVFCMP_CULT_S */
15382
    LASX256, LASX256, LASX256, 
15383
    /* XVFCMP_CUNE_D */
15384
    LASX256, LASX256, LASX256, 
15385
    /* XVFCMP_CUNE_S */
15386
    LASX256, LASX256, LASX256, 
15387
    /* XVFCMP_CUN_D */
15388
    LASX256, LASX256, LASX256, 
15389
    /* XVFCMP_CUN_S */
15390
    LASX256, LASX256, LASX256, 
15391
    /* XVFCMP_SAF_D */
15392
    LASX256, LASX256, LASX256, 
15393
    /* XVFCMP_SAF_S */
15394
    LASX256, LASX256, LASX256, 
15395
    /* XVFCMP_SEQ_D */
15396
    LASX256, LASX256, LASX256, 
15397
    /* XVFCMP_SEQ_S */
15398
    LASX256, LASX256, LASX256, 
15399
    /* XVFCMP_SLE_D */
15400
    LASX256, LASX256, LASX256, 
15401
    /* XVFCMP_SLE_S */
15402
    LASX256, LASX256, LASX256, 
15403
    /* XVFCMP_SLT_D */
15404
    LASX256, LASX256, LASX256, 
15405
    /* XVFCMP_SLT_S */
15406
    LASX256, LASX256, LASX256, 
15407
    /* XVFCMP_SNE_D */
15408
    LASX256, LASX256, LASX256, 
15409
    /* XVFCMP_SNE_S */
15410
    LASX256, LASX256, LASX256, 
15411
    /* XVFCMP_SOR_D */
15412
    LASX256, LASX256, LASX256, 
15413
    /* XVFCMP_SOR_S */
15414
    LASX256, LASX256, LASX256, 
15415
    /* XVFCMP_SUEQ_D */
15416
    LASX256, LASX256, LASX256, 
15417
    /* XVFCMP_SUEQ_S */
15418
    LASX256, LASX256, LASX256, 
15419
    /* XVFCMP_SULE_D */
15420
    LASX256, LASX256, LASX256, 
15421
    /* XVFCMP_SULE_S */
15422
    LASX256, LASX256, LASX256, 
15423
    /* XVFCMP_SULT_D */
15424
    LASX256, LASX256, LASX256, 
15425
    /* XVFCMP_SULT_S */
15426
    LASX256, LASX256, LASX256, 
15427
    /* XVFCMP_SUNE_D */
15428
    LASX256, LASX256, LASX256, 
15429
    /* XVFCMP_SUNE_S */
15430
    LASX256, LASX256, LASX256, 
15431
    /* XVFCMP_SUN_D */
15432
    LASX256, LASX256, LASX256, 
15433
    /* XVFCMP_SUN_S */
15434
    LASX256, LASX256, LASX256, 
15435
    /* XVFCVTH_D_S */
15436
    LASX256, LASX256, 
15437
    /* XVFCVTH_S_H */
15438
    LASX256, LASX256, 
15439
    /* XVFCVTL_D_S */
15440
    LASX256, LASX256, 
15441
    /* XVFCVTL_S_H */
15442
    LASX256, LASX256, 
15443
    /* XVFCVT_H_S */
15444
    LASX256, LASX256, LASX256, 
15445
    /* XVFCVT_S_D */
15446
    LASX256, LASX256, LASX256, 
15447
    /* XVFDIV_D */
15448
    LASX256, LASX256, LASX256, 
15449
    /* XVFDIV_S */
15450
    LASX256, LASX256, LASX256, 
15451
    /* XVFFINTH_D_W */
15452
    LASX256, LASX256, 
15453
    /* XVFFINTL_D_W */
15454
    LASX256, LASX256, 
15455
    /* XVFFINT_D_L */
15456
    LASX256, LASX256, 
15457
    /* XVFFINT_D_LU */
15458
    LASX256, LASX256, 
15459
    /* XVFFINT_S_L */
15460
    LASX256, LASX256, LASX256, 
15461
    /* XVFFINT_S_W */
15462
    LASX256, LASX256, 
15463
    /* XVFFINT_S_WU */
15464
    LASX256, LASX256, 
15465
    /* XVFLOGB_D */
15466
    LASX256, LASX256, 
15467
    /* XVFLOGB_S */
15468
    LASX256, LASX256, 
15469
    /* XVFMADD_D */
15470
    LASX256, LASX256, LASX256, LASX256, 
15471
    /* XVFMADD_S */
15472
    LASX256, LASX256, LASX256, LASX256, 
15473
    /* XVFMAXA_D */
15474
    LASX256, LASX256, LASX256, 
15475
    /* XVFMAXA_S */
15476
    LASX256, LASX256, LASX256, 
15477
    /* XVFMAX_D */
15478
    LASX256, LASX256, LASX256, 
15479
    /* XVFMAX_S */
15480
    LASX256, LASX256, LASX256, 
15481
    /* XVFMINA_D */
15482
    LASX256, LASX256, LASX256, 
15483
    /* XVFMINA_S */
15484
    LASX256, LASX256, LASX256, 
15485
    /* XVFMIN_D */
15486
    LASX256, LASX256, LASX256, 
15487
    /* XVFMIN_S */
15488
    LASX256, LASX256, LASX256, 
15489
    /* XVFMSUB_D */
15490
    LASX256, LASX256, LASX256, LASX256, 
15491
    /* XVFMSUB_S */
15492
    LASX256, LASX256, LASX256, LASX256, 
15493
    /* XVFMUL_D */
15494
    LASX256, LASX256, LASX256, 
15495
    /* XVFMUL_S */
15496
    LASX256, LASX256, LASX256, 
15497
    /* XVFNMADD_D */
15498
    LASX256, LASX256, LASX256, LASX256, 
15499
    /* XVFNMADD_S */
15500
    LASX256, LASX256, LASX256, LASX256, 
15501
    /* XVFNMSUB_D */
15502
    LASX256, LASX256, LASX256, LASX256, 
15503
    /* XVFNMSUB_S */
15504
    LASX256, LASX256, LASX256, LASX256, 
15505
    /* XVFRECIPE_D */
15506
    LASX256, LASX256, 
15507
    /* XVFRECIPE_S */
15508
    LASX256, LASX256, 
15509
    /* XVFRECIP_D */
15510
    LASX256, LASX256, 
15511
    /* XVFRECIP_S */
15512
    LASX256, LASX256, 
15513
    /* XVFRINTRM_D */
15514
    LASX256, LASX256, 
15515
    /* XVFRINTRM_S */
15516
    LASX256, LASX256, 
15517
    /* XVFRINTRNE_D */
15518
    LASX256, LASX256, 
15519
    /* XVFRINTRNE_S */
15520
    LASX256, LASX256, 
15521
    /* XVFRINTRP_D */
15522
    LASX256, LASX256, 
15523
    /* XVFRINTRP_S */
15524
    LASX256, LASX256, 
15525
    /* XVFRINTRZ_D */
15526
    LASX256, LASX256, 
15527
    /* XVFRINTRZ_S */
15528
    LASX256, LASX256, 
15529
    /* XVFRINT_D */
15530
    LASX256, LASX256, 
15531
    /* XVFRINT_S */
15532
    LASX256, LASX256, 
15533
    /* XVFRSQRTE_D */
15534
    LASX256, LASX256, 
15535
    /* XVFRSQRTE_S */
15536
    LASX256, LASX256, 
15537
    /* XVFRSQRT_D */
15538
    LASX256, LASX256, 
15539
    /* XVFRSQRT_S */
15540
    LASX256, LASX256, 
15541
    /* XVFRSTPI_B */
15542
    LASX256, LASX256, LASX256, uimm5, 
15543
    /* XVFRSTPI_H */
15544
    LASX256, LASX256, LASX256, uimm5, 
15545
    /* XVFRSTP_B */
15546
    LASX256, LASX256, LASX256, LASX256, 
15547
    /* XVFRSTP_H */
15548
    LASX256, LASX256, LASX256, LASX256, 
15549
    /* XVFSQRT_D */
15550
    LASX256, LASX256, 
15551
    /* XVFSQRT_S */
15552
    LASX256, LASX256, 
15553
    /* XVFSUB_D */
15554
    LASX256, LASX256, LASX256, 
15555
    /* XVFSUB_S */
15556
    LASX256, LASX256, LASX256, 
15557
    /* XVFTINTH_L_S */
15558
    LASX256, LASX256, 
15559
    /* XVFTINTL_L_S */
15560
    LASX256, LASX256, 
15561
    /* XVFTINTRMH_L_S */
15562
    LASX256, LASX256, 
15563
    /* XVFTINTRML_L_S */
15564
    LASX256, LASX256, 
15565
    /* XVFTINTRM_L_D */
15566
    LASX256, LASX256, 
15567
    /* XVFTINTRM_W_D */
15568
    LASX256, LASX256, LASX256, 
15569
    /* XVFTINTRM_W_S */
15570
    LASX256, LASX256, 
15571
    /* XVFTINTRNEH_L_S */
15572
    LASX256, LASX256, 
15573
    /* XVFTINTRNEL_L_S */
15574
    LASX256, LASX256, 
15575
    /* XVFTINTRNE_L_D */
15576
    LASX256, LASX256, 
15577
    /* XVFTINTRNE_W_D */
15578
    LASX256, LASX256, LASX256, 
15579
    /* XVFTINTRNE_W_S */
15580
    LASX256, LASX256, 
15581
    /* XVFTINTRPH_L_S */
15582
    LASX256, LASX256, 
15583
    /* XVFTINTRPL_L_S */
15584
    LASX256, LASX256, 
15585
    /* XVFTINTRP_L_D */
15586
    LASX256, LASX256, 
15587
    /* XVFTINTRP_W_D */
15588
    LASX256, LASX256, LASX256, 
15589
    /* XVFTINTRP_W_S */
15590
    LASX256, LASX256, 
15591
    /* XVFTINTRZH_L_S */
15592
    LASX256, LASX256, 
15593
    /* XVFTINTRZL_L_S */
15594
    LASX256, LASX256, 
15595
    /* XVFTINTRZ_LU_D */
15596
    LASX256, LASX256, 
15597
    /* XVFTINTRZ_L_D */
15598
    LASX256, LASX256, 
15599
    /* XVFTINTRZ_WU_S */
15600
    LASX256, LASX256, 
15601
    /* XVFTINTRZ_W_D */
15602
    LASX256, LASX256, LASX256, 
15603
    /* XVFTINTRZ_W_S */
15604
    LASX256, LASX256, 
15605
    /* XVFTINT_LU_D */
15606
    LASX256, LASX256, 
15607
    /* XVFTINT_L_D */
15608
    LASX256, LASX256, 
15609
    /* XVFTINT_WU_S */
15610
    LASX256, LASX256, 
15611
    /* XVFTINT_W_D */
15612
    LASX256, LASX256, LASX256, 
15613
    /* XVFTINT_W_S */
15614
    LASX256, LASX256, 
15615
    /* XVHADDW_DU_WU */
15616
    LASX256, LASX256, LASX256, 
15617
    /* XVHADDW_D_W */
15618
    LASX256, LASX256, LASX256, 
15619
    /* XVHADDW_HU_BU */
15620
    LASX256, LASX256, LASX256, 
15621
    /* XVHADDW_H_B */
15622
    LASX256, LASX256, LASX256, 
15623
    /* XVHADDW_QU_DU */
15624
    LASX256, LASX256, LASX256, 
15625
    /* XVHADDW_Q_D */
15626
    LASX256, LASX256, LASX256, 
15627
    /* XVHADDW_WU_HU */
15628
    LASX256, LASX256, LASX256, 
15629
    /* XVHADDW_W_H */
15630
    LASX256, LASX256, LASX256, 
15631
    /* XVHSELI_D */
15632
    LASX256, LASX256, uimm5, 
15633
    /* XVHSUBW_DU_WU */
15634
    LASX256, LASX256, LASX256, 
15635
    /* XVHSUBW_D_W */
15636
    LASX256, LASX256, LASX256, 
15637
    /* XVHSUBW_HU_BU */
15638
    LASX256, LASX256, LASX256, 
15639
    /* XVHSUBW_H_B */
15640
    LASX256, LASX256, LASX256, 
15641
    /* XVHSUBW_QU_DU */
15642
    LASX256, LASX256, LASX256, 
15643
    /* XVHSUBW_Q_D */
15644
    LASX256, LASX256, LASX256, 
15645
    /* XVHSUBW_WU_HU */
15646
    LASX256, LASX256, LASX256, 
15647
    /* XVHSUBW_W_H */
15648
    LASX256, LASX256, LASX256, 
15649
    /* XVILVH_B */
15650
    LASX256, LASX256, LASX256, 
15651
    /* XVILVH_D */
15652
    LASX256, LASX256, LASX256, 
15653
    /* XVILVH_H */
15654
    LASX256, LASX256, LASX256, 
15655
    /* XVILVH_W */
15656
    LASX256, LASX256, LASX256, 
15657
    /* XVILVL_B */
15658
    LASX256, LASX256, LASX256, 
15659
    /* XVILVL_D */
15660
    LASX256, LASX256, LASX256, 
15661
    /* XVILVL_H */
15662
    LASX256, LASX256, LASX256, 
15663
    /* XVILVL_W */
15664
    LASX256, LASX256, LASX256, 
15665
    /* XVINSGR2VR_D */
15666
    LASX256, LASX256, GPR, uimm2, 
15667
    /* XVINSGR2VR_W */
15668
    LASX256, LASX256, GPR, uimm3, 
15669
    /* XVINSVE0_D */
15670
    LASX256, LASX256, LASX256, uimm2, 
15671
    /* XVINSVE0_W */
15672
    LASX256, LASX256, LASX256, uimm3, 
15673
    /* XVLD */
15674
    LASX256, GPR, simm12, 
15675
    /* XVLDI */
15676
    LASX256, simm13, 
15677
    /* XVLDREPL_B */
15678
    LASX256, GPR, simm12, 
15679
    /* XVLDREPL_D */
15680
    LASX256, GPR, simm9_lsl3, 
15681
    /* XVLDREPL_H */
15682
    LASX256, GPR, simm11_lsl1, 
15683
    /* XVLDREPL_W */
15684
    LASX256, GPR, simm10_lsl2, 
15685
    /* XVLDX */
15686
    LASX256, GPR, GPR, 
15687
    /* XVMADDWEV_D_W */
15688
    LASX256, LASX256, LASX256, LASX256, 
15689
    /* XVMADDWEV_D_WU */
15690
    LASX256, LASX256, LASX256, LASX256, 
15691
    /* XVMADDWEV_D_WU_W */
15692
    LASX256, LASX256, LASX256, LASX256, 
15693
    /* XVMADDWEV_H_B */
15694
    LASX256, LASX256, LASX256, LASX256, 
15695
    /* XVMADDWEV_H_BU */
15696
    LASX256, LASX256, LASX256, LASX256, 
15697
    /* XVMADDWEV_H_BU_B */
15698
    LASX256, LASX256, LASX256, LASX256, 
15699
    /* XVMADDWEV_Q_D */
15700
    LASX256, LASX256, LASX256, LASX256, 
15701
    /* XVMADDWEV_Q_DU */
15702
    LASX256, LASX256, LASX256, LASX256, 
15703
    /* XVMADDWEV_Q_DU_D */
15704
    LASX256, LASX256, LASX256, LASX256, 
15705
    /* XVMADDWEV_W_H */
15706
    LASX256, LASX256, LASX256, LASX256, 
15707
    /* XVMADDWEV_W_HU */
15708
    LASX256, LASX256, LASX256, LASX256, 
15709
    /* XVMADDWEV_W_HU_H */
15710
    LASX256, LASX256, LASX256, LASX256, 
15711
    /* XVMADDWOD_D_W */
15712
    LASX256, LASX256, LASX256, LASX256, 
15713
    /* XVMADDWOD_D_WU */
15714
    LASX256, LASX256, LASX256, LASX256, 
15715
    /* XVMADDWOD_D_WU_W */
15716
    LASX256, LASX256, LASX256, LASX256, 
15717
    /* XVMADDWOD_H_B */
15718
    LASX256, LASX256, LASX256, LASX256, 
15719
    /* XVMADDWOD_H_BU */
15720
    LASX256, LASX256, LASX256, LASX256, 
15721
    /* XVMADDWOD_H_BU_B */
15722
    LASX256, LASX256, LASX256, LASX256, 
15723
    /* XVMADDWOD_Q_D */
15724
    LASX256, LASX256, LASX256, LASX256, 
15725
    /* XVMADDWOD_Q_DU */
15726
    LASX256, LASX256, LASX256, LASX256, 
15727
    /* XVMADDWOD_Q_DU_D */
15728
    LASX256, LASX256, LASX256, LASX256, 
15729
    /* XVMADDWOD_W_H */
15730
    LASX256, LASX256, LASX256, LASX256, 
15731
    /* XVMADDWOD_W_HU */
15732
    LASX256, LASX256, LASX256, LASX256, 
15733
    /* XVMADDWOD_W_HU_H */
15734
    LASX256, LASX256, LASX256, LASX256, 
15735
    /* XVMADD_B */
15736
    LASX256, LASX256, LASX256, LASX256, 
15737
    /* XVMADD_D */
15738
    LASX256, LASX256, LASX256, LASX256, 
15739
    /* XVMADD_H */
15740
    LASX256, LASX256, LASX256, LASX256, 
15741
    /* XVMADD_W */
15742
    LASX256, LASX256, LASX256, LASX256, 
15743
    /* XVMAXI_B */
15744
    LASX256, LASX256, simm5, 
15745
    /* XVMAXI_BU */
15746
    LASX256, LASX256, uimm5, 
15747
    /* XVMAXI_D */
15748
    LASX256, LASX256, simm5, 
15749
    /* XVMAXI_DU */
15750
    LASX256, LASX256, uimm5, 
15751
    /* XVMAXI_H */
15752
    LASX256, LASX256, simm5, 
15753
    /* XVMAXI_HU */
15754
    LASX256, LASX256, uimm5, 
15755
    /* XVMAXI_W */
15756
    LASX256, LASX256, simm5, 
15757
    /* XVMAXI_WU */
15758
    LASX256, LASX256, uimm5, 
15759
    /* XVMAX_B */
15760
    LASX256, LASX256, LASX256, 
15761
    /* XVMAX_BU */
15762
    LASX256, LASX256, LASX256, 
15763
    /* XVMAX_D */
15764
    LASX256, LASX256, LASX256, 
15765
    /* XVMAX_DU */
15766
    LASX256, LASX256, LASX256, 
15767
    /* XVMAX_H */
15768
    LASX256, LASX256, LASX256, 
15769
    /* XVMAX_HU */
15770
    LASX256, LASX256, LASX256, 
15771
    /* XVMAX_W */
15772
    LASX256, LASX256, LASX256, 
15773
    /* XVMAX_WU */
15774
    LASX256, LASX256, LASX256, 
15775
    /* XVMINI_B */
15776
    LASX256, LASX256, simm5, 
15777
    /* XVMINI_BU */
15778
    LASX256, LASX256, uimm5, 
15779
    /* XVMINI_D */
15780
    LASX256, LASX256, simm5, 
15781
    /* XVMINI_DU */
15782
    LASX256, LASX256, uimm5, 
15783
    /* XVMINI_H */
15784
    LASX256, LASX256, simm5, 
15785
    /* XVMINI_HU */
15786
    LASX256, LASX256, uimm5, 
15787
    /* XVMINI_W */
15788
    LASX256, LASX256, simm5, 
15789
    /* XVMINI_WU */
15790
    LASX256, LASX256, uimm5, 
15791
    /* XVMIN_B */
15792
    LASX256, LASX256, LASX256, 
15793
    /* XVMIN_BU */
15794
    LASX256, LASX256, LASX256, 
15795
    /* XVMIN_D */
15796
    LASX256, LASX256, LASX256, 
15797
    /* XVMIN_DU */
15798
    LASX256, LASX256, LASX256, 
15799
    /* XVMIN_H */
15800
    LASX256, LASX256, LASX256, 
15801
    /* XVMIN_HU */
15802
    LASX256, LASX256, LASX256, 
15803
    /* XVMIN_W */
15804
    LASX256, LASX256, LASX256, 
15805
    /* XVMIN_WU */
15806
    LASX256, LASX256, LASX256, 
15807
    /* XVMOD_B */
15808
    LASX256, LASX256, LASX256, 
15809
    /* XVMOD_BU */
15810
    LASX256, LASX256, LASX256, 
15811
    /* XVMOD_D */
15812
    LASX256, LASX256, LASX256, 
15813
    /* XVMOD_DU */
15814
    LASX256, LASX256, LASX256, 
15815
    /* XVMOD_H */
15816
    LASX256, LASX256, LASX256, 
15817
    /* XVMOD_HU */
15818
    LASX256, LASX256, LASX256, 
15819
    /* XVMOD_W */
15820
    LASX256, LASX256, LASX256, 
15821
    /* XVMOD_WU */
15822
    LASX256, LASX256, LASX256, 
15823
    /* XVMSKGEZ_B */
15824
    LASX256, LASX256, 
15825
    /* XVMSKLTZ_B */
15826
    LASX256, LASX256, 
15827
    /* XVMSKLTZ_D */
15828
    LASX256, LASX256, 
15829
    /* XVMSKLTZ_H */
15830
    LASX256, LASX256, 
15831
    /* XVMSKLTZ_W */
15832
    LASX256, LASX256, 
15833
    /* XVMSKNZ_B */
15834
    LASX256, LASX256, 
15835
    /* XVMSUB_B */
15836
    LASX256, LASX256, LASX256, LASX256, 
15837
    /* XVMSUB_D */
15838
    LASX256, LASX256, LASX256, LASX256, 
15839
    /* XVMSUB_H */
15840
    LASX256, LASX256, LASX256, LASX256, 
15841
    /* XVMSUB_W */
15842
    LASX256, LASX256, LASX256, LASX256, 
15843
    /* XVMUH_B */
15844
    LASX256, LASX256, LASX256, 
15845
    /* XVMUH_BU */
15846
    LASX256, LASX256, LASX256, 
15847
    /* XVMUH_D */
15848
    LASX256, LASX256, LASX256, 
15849
    /* XVMUH_DU */
15850
    LASX256, LASX256, LASX256, 
15851
    /* XVMUH_H */
15852
    LASX256, LASX256, LASX256, 
15853
    /* XVMUH_HU */
15854
    LASX256, LASX256, LASX256, 
15855
    /* XVMUH_W */
15856
    LASX256, LASX256, LASX256, 
15857
    /* XVMUH_WU */
15858
    LASX256, LASX256, LASX256, 
15859
    /* XVMULWEV_D_W */
15860
    LASX256, LASX256, LASX256, 
15861
    /* XVMULWEV_D_WU */
15862
    LASX256, LASX256, LASX256, 
15863
    /* XVMULWEV_D_WU_W */
15864
    LASX256, LASX256, LASX256, 
15865
    /* XVMULWEV_H_B */
15866
    LASX256, LASX256, LASX256, 
15867
    /* XVMULWEV_H_BU */
15868
    LASX256, LASX256, LASX256, 
15869
    /* XVMULWEV_H_BU_B */
15870
    LASX256, LASX256, LASX256, 
15871
    /* XVMULWEV_Q_D */
15872
    LASX256, LASX256, LASX256, 
15873
    /* XVMULWEV_Q_DU */
15874
    LASX256, LASX256, LASX256, 
15875
    /* XVMULWEV_Q_DU_D */
15876
    LASX256, LASX256, LASX256, 
15877
    /* XVMULWEV_W_H */
15878
    LASX256, LASX256, LASX256, 
15879
    /* XVMULWEV_W_HU */
15880
    LASX256, LASX256, LASX256, 
15881
    /* XVMULWEV_W_HU_H */
15882
    LASX256, LASX256, LASX256, 
15883
    /* XVMULWOD_D_W */
15884
    LASX256, LASX256, LASX256, 
15885
    /* XVMULWOD_D_WU */
15886
    LASX256, LASX256, LASX256, 
15887
    /* XVMULWOD_D_WU_W */
15888
    LASX256, LASX256, LASX256, 
15889
    /* XVMULWOD_H_B */
15890
    LASX256, LASX256, LASX256, 
15891
    /* XVMULWOD_H_BU */
15892
    LASX256, LASX256, LASX256, 
15893
    /* XVMULWOD_H_BU_B */
15894
    LASX256, LASX256, LASX256, 
15895
    /* XVMULWOD_Q_D */
15896
    LASX256, LASX256, LASX256, 
15897
    /* XVMULWOD_Q_DU */
15898
    LASX256, LASX256, LASX256, 
15899
    /* XVMULWOD_Q_DU_D */
15900
    LASX256, LASX256, LASX256, 
15901
    /* XVMULWOD_W_H */
15902
    LASX256, LASX256, LASX256, 
15903
    /* XVMULWOD_W_HU */
15904
    LASX256, LASX256, LASX256, 
15905
    /* XVMULWOD_W_HU_H */
15906
    LASX256, LASX256, LASX256, 
15907
    /* XVMUL_B */
15908
    LASX256, LASX256, LASX256, 
15909
    /* XVMUL_D */
15910
    LASX256, LASX256, LASX256, 
15911
    /* XVMUL_H */
15912
    LASX256, LASX256, LASX256, 
15913
    /* XVMUL_W */
15914
    LASX256, LASX256, LASX256, 
15915
    /* XVNEG_B */
15916
    LASX256, LASX256, 
15917
    /* XVNEG_D */
15918
    LASX256, LASX256, 
15919
    /* XVNEG_H */
15920
    LASX256, LASX256, 
15921
    /* XVNEG_W */
15922
    LASX256, LASX256, 
15923
    /* XVNORI_B */
15924
    LASX256, LASX256, uimm8, 
15925
    /* XVNOR_V */
15926
    LASX256, LASX256, LASX256, 
15927
    /* XVORI_B */
15928
    LASX256, LASX256, uimm8, 
15929
    /* XVORN_V */
15930
    LASX256, LASX256, LASX256, 
15931
    /* XVOR_V */
15932
    LASX256, LASX256, LASX256, 
15933
    /* XVPACKEV_B */
15934
    LASX256, LASX256, LASX256, 
15935
    /* XVPACKEV_D */
15936
    LASX256, LASX256, LASX256, 
15937
    /* XVPACKEV_H */
15938
    LASX256, LASX256, LASX256, 
15939
    /* XVPACKEV_W */
15940
    LASX256, LASX256, LASX256, 
15941
    /* XVPACKOD_B */
15942
    LASX256, LASX256, LASX256, 
15943
    /* XVPACKOD_D */
15944
    LASX256, LASX256, LASX256, 
15945
    /* XVPACKOD_H */
15946
    LASX256, LASX256, LASX256, 
15947
    /* XVPACKOD_W */
15948
    LASX256, LASX256, LASX256, 
15949
    /* XVPCNT_B */
15950
    LASX256, LASX256, 
15951
    /* XVPCNT_D */
15952
    LASX256, LASX256, 
15953
    /* XVPCNT_H */
15954
    LASX256, LASX256, 
15955
    /* XVPCNT_W */
15956
    LASX256, LASX256, 
15957
    /* XVPERMI_D */
15958
    LASX256, LASX256, uimm8, 
15959
    /* XVPERMI_Q */
15960
    LASX256, LASX256, LASX256, uimm8, 
15961
    /* XVPERMI_W */
15962
    LASX256, LASX256, LASX256, uimm8, 
15963
    /* XVPERM_W */
15964
    LASX256, LASX256, LASX256, 
15965
    /* XVPICKEV_B */
15966
    LASX256, LASX256, LASX256, 
15967
    /* XVPICKEV_D */
15968
    LASX256, LASX256, LASX256, 
15969
    /* XVPICKEV_H */
15970
    LASX256, LASX256, LASX256, 
15971
    /* XVPICKEV_W */
15972
    LASX256, LASX256, LASX256, 
15973
    /* XVPICKOD_B */
15974
    LASX256, LASX256, LASX256, 
15975
    /* XVPICKOD_D */
15976
    LASX256, LASX256, LASX256, 
15977
    /* XVPICKOD_H */
15978
    LASX256, LASX256, LASX256, 
15979
    /* XVPICKOD_W */
15980
    LASX256, LASX256, LASX256, 
15981
    /* XVPICKVE2GR_D */
15982
    GPR, LASX256, uimm2, 
15983
    /* XVPICKVE2GR_DU */
15984
    GPR, LASX256, uimm2, 
15985
    /* XVPICKVE2GR_W */
15986
    GPR, LASX256, uimm3, 
15987
    /* XVPICKVE2GR_WU */
15988
    GPR, LASX256, uimm3, 
15989
    /* XVPICKVE_D */
15990
    LASX256, LASX256, uimm2, 
15991
    /* XVPICKVE_W */
15992
    LASX256, LASX256, uimm3, 
15993
    /* XVREPL128VEI_B */
15994
    LASX256, LASX256, uimm4, 
15995
    /* XVREPL128VEI_D */
15996
    LASX256, LASX256, uimm1, 
15997
    /* XVREPL128VEI_H */
15998
    LASX256, LASX256, uimm3, 
15999
    /* XVREPL128VEI_W */
16000
    LASX256, LASX256, uimm2, 
16001
    /* XVREPLGR2VR_B */
16002
    LASX256, GPR, 
16003
    /* XVREPLGR2VR_D */
16004
    LASX256, GPR, 
16005
    /* XVREPLGR2VR_H */
16006
    LASX256, GPR, 
16007
    /* XVREPLGR2VR_W */
16008
    LASX256, GPR, 
16009
    /* XVREPLVE0_B */
16010
    LASX256, LASX256, 
16011
    /* XVREPLVE0_D */
16012
    LASX256, LASX256, 
16013
    /* XVREPLVE0_H */
16014
    LASX256, LASX256, 
16015
    /* XVREPLVE0_Q */
16016
    LASX256, LASX256, 
16017
    /* XVREPLVE0_W */
16018
    LASX256, LASX256, 
16019
    /* XVREPLVE_B */
16020
    LASX256, LASX256, GPR, 
16021
    /* XVREPLVE_D */
16022
    LASX256, LASX256, GPR, 
16023
    /* XVREPLVE_H */
16024
    LASX256, LASX256, GPR, 
16025
    /* XVREPLVE_W */
16026
    LASX256, LASX256, GPR, 
16027
    /* XVROTRI_B */
16028
    LASX256, LASX256, uimm3, 
16029
    /* XVROTRI_D */
16030
    LASX256, LASX256, uimm6, 
16031
    /* XVROTRI_H */
16032
    LASX256, LASX256, uimm4, 
16033
    /* XVROTRI_W */
16034
    LASX256, LASX256, uimm5, 
16035
    /* XVROTR_B */
16036
    LASX256, LASX256, LASX256, 
16037
    /* XVROTR_D */
16038
    LASX256, LASX256, LASX256, 
16039
    /* XVROTR_H */
16040
    LASX256, LASX256, LASX256, 
16041
    /* XVROTR_W */
16042
    LASX256, LASX256, LASX256, 
16043
    /* XVSADD_B */
16044
    LASX256, LASX256, LASX256, 
16045
    /* XVSADD_BU */
16046
    LASX256, LASX256, LASX256, 
16047
    /* XVSADD_D */
16048
    LASX256, LASX256, LASX256, 
16049
    /* XVSADD_DU */
16050
    LASX256, LASX256, LASX256, 
16051
    /* XVSADD_H */
16052
    LASX256, LASX256, LASX256, 
16053
    /* XVSADD_HU */
16054
    LASX256, LASX256, LASX256, 
16055
    /* XVSADD_W */
16056
    LASX256, LASX256, LASX256, 
16057
    /* XVSADD_WU */
16058
    LASX256, LASX256, LASX256, 
16059
    /* XVSAT_B */
16060
    LASX256, LASX256, uimm3, 
16061
    /* XVSAT_BU */
16062
    LASX256, LASX256, uimm3, 
16063
    /* XVSAT_D */
16064
    LASX256, LASX256, uimm6, 
16065
    /* XVSAT_DU */
16066
    LASX256, LASX256, uimm6, 
16067
    /* XVSAT_H */
16068
    LASX256, LASX256, uimm4, 
16069
    /* XVSAT_HU */
16070
    LASX256, LASX256, uimm4, 
16071
    /* XVSAT_W */
16072
    LASX256, LASX256, uimm5, 
16073
    /* XVSAT_WU */
16074
    LASX256, LASX256, uimm5, 
16075
    /* XVSEQI_B */
16076
    LASX256, LASX256, simm5, 
16077
    /* XVSEQI_D */
16078
    LASX256, LASX256, simm5, 
16079
    /* XVSEQI_H */
16080
    LASX256, LASX256, simm5, 
16081
    /* XVSEQI_W */
16082
    LASX256, LASX256, simm5, 
16083
    /* XVSEQ_B */
16084
    LASX256, LASX256, LASX256, 
16085
    /* XVSEQ_D */
16086
    LASX256, LASX256, LASX256, 
16087
    /* XVSEQ_H */
16088
    LASX256, LASX256, LASX256, 
16089
    /* XVSEQ_W */
16090
    LASX256, LASX256, LASX256, 
16091
    /* XVSETALLNEZ_B */
16092
    CFR, LASX256, 
16093
    /* XVSETALLNEZ_D */
16094
    CFR, LASX256, 
16095
    /* XVSETALLNEZ_H */
16096
    CFR, LASX256, 
16097
    /* XVSETALLNEZ_W */
16098
    CFR, LASX256, 
16099
    /* XVSETANYEQZ_B */
16100
    CFR, LASX256, 
16101
    /* XVSETANYEQZ_D */
16102
    CFR, LASX256, 
16103
    /* XVSETANYEQZ_H */
16104
    CFR, LASX256, 
16105
    /* XVSETANYEQZ_W */
16106
    CFR, LASX256, 
16107
    /* XVSETEQZ_V */
16108
    CFR, LASX256, 
16109
    /* XVSETNEZ_V */
16110
    CFR, LASX256, 
16111
    /* XVSHUF4I_B */
16112
    LASX256, LASX256, uimm8, 
16113
    /* XVSHUF4I_D */
16114
    LASX256, LASX256, LASX256, uimm8, 
16115
    /* XVSHUF4I_H */
16116
    LASX256, LASX256, uimm8, 
16117
    /* XVSHUF4I_W */
16118
    LASX256, LASX256, uimm8, 
16119
    /* XVSHUF_B */
16120
    LASX256, LASX256, LASX256, LASX256, 
16121
    /* XVSHUF_D */
16122
    LASX256, LASX256, LASX256, LASX256, 
16123
    /* XVSHUF_H */
16124
    LASX256, LASX256, LASX256, LASX256, 
16125
    /* XVSHUF_W */
16126
    LASX256, LASX256, LASX256, LASX256, 
16127
    /* XVSIGNCOV_B */
16128
    LASX256, LASX256, LASX256, 
16129
    /* XVSIGNCOV_D */
16130
    LASX256, LASX256, LASX256, 
16131
    /* XVSIGNCOV_H */
16132
    LASX256, LASX256, LASX256, 
16133
    /* XVSIGNCOV_W */
16134
    LASX256, LASX256, LASX256, 
16135
    /* XVSLEI_B */
16136
    LASX256, LASX256, simm5, 
16137
    /* XVSLEI_BU */
16138
    LASX256, LASX256, uimm5, 
16139
    /* XVSLEI_D */
16140
    LASX256, LASX256, simm5, 
16141
    /* XVSLEI_DU */
16142
    LASX256, LASX256, uimm5, 
16143
    /* XVSLEI_H */
16144
    LASX256, LASX256, simm5, 
16145
    /* XVSLEI_HU */
16146
    LASX256, LASX256, uimm5, 
16147
    /* XVSLEI_W */
16148
    LASX256, LASX256, simm5, 
16149
    /* XVSLEI_WU */
16150
    LASX256, LASX256, uimm5, 
16151
    /* XVSLE_B */
16152
    LASX256, LASX256, LASX256, 
16153
    /* XVSLE_BU */
16154
    LASX256, LASX256, LASX256, 
16155
    /* XVSLE_D */
16156
    LASX256, LASX256, LASX256, 
16157
    /* XVSLE_DU */
16158
    LASX256, LASX256, LASX256, 
16159
    /* XVSLE_H */
16160
    LASX256, LASX256, LASX256, 
16161
    /* XVSLE_HU */
16162
    LASX256, LASX256, LASX256, 
16163
    /* XVSLE_W */
16164
    LASX256, LASX256, LASX256, 
16165
    /* XVSLE_WU */
16166
    LASX256, LASX256, LASX256, 
16167
    /* XVSLLI_B */
16168
    LASX256, LASX256, uimm3, 
16169
    /* XVSLLI_D */
16170
    LASX256, LASX256, uimm6, 
16171
    /* XVSLLI_H */
16172
    LASX256, LASX256, uimm4, 
16173
    /* XVSLLI_W */
16174
    LASX256, LASX256, uimm5, 
16175
    /* XVSLLWIL_DU_WU */
16176
    LASX256, LASX256, uimm5, 
16177
    /* XVSLLWIL_D_W */
16178
    LASX256, LASX256, uimm5, 
16179
    /* XVSLLWIL_HU_BU */
16180
    LASX256, LASX256, uimm3, 
16181
    /* XVSLLWIL_H_B */
16182
    LASX256, LASX256, uimm3, 
16183
    /* XVSLLWIL_WU_HU */
16184
    LASX256, LASX256, uimm4, 
16185
    /* XVSLLWIL_W_H */
16186
    LASX256, LASX256, uimm4, 
16187
    /* XVSLL_B */
16188
    LASX256, LASX256, LASX256, 
16189
    /* XVSLL_D */
16190
    LASX256, LASX256, LASX256, 
16191
    /* XVSLL_H */
16192
    LASX256, LASX256, LASX256, 
16193
    /* XVSLL_W */
16194
    LASX256, LASX256, LASX256, 
16195
    /* XVSLTI_B */
16196
    LASX256, LASX256, simm5, 
16197
    /* XVSLTI_BU */
16198
    LASX256, LASX256, uimm5, 
16199
    /* XVSLTI_D */
16200
    LASX256, LASX256, simm5, 
16201
    /* XVSLTI_DU */
16202
    LASX256, LASX256, uimm5, 
16203
    /* XVSLTI_H */
16204
    LASX256, LASX256, simm5, 
16205
    /* XVSLTI_HU */
16206
    LASX256, LASX256, uimm5, 
16207
    /* XVSLTI_W */
16208
    LASX256, LASX256, simm5, 
16209
    /* XVSLTI_WU */
16210
    LASX256, LASX256, uimm5, 
16211
    /* XVSLT_B */
16212
    LASX256, LASX256, LASX256, 
16213
    /* XVSLT_BU */
16214
    LASX256, LASX256, LASX256, 
16215
    /* XVSLT_D */
16216
    LASX256, LASX256, LASX256, 
16217
    /* XVSLT_DU */
16218
    LASX256, LASX256, LASX256, 
16219
    /* XVSLT_H */
16220
    LASX256, LASX256, LASX256, 
16221
    /* XVSLT_HU */
16222
    LASX256, LASX256, LASX256, 
16223
    /* XVSLT_W */
16224
    LASX256, LASX256, LASX256, 
16225
    /* XVSLT_WU */
16226
    LASX256, LASX256, LASX256, 
16227
    /* XVSRAI_B */
16228
    LASX256, LASX256, uimm3, 
16229
    /* XVSRAI_D */
16230
    LASX256, LASX256, uimm6, 
16231
    /* XVSRAI_H */
16232
    LASX256, LASX256, uimm4, 
16233
    /* XVSRAI_W */
16234
    LASX256, LASX256, uimm5, 
16235
    /* XVSRANI_B_H */
16236
    LASX256, LASX256, LASX256, uimm4, 
16237
    /* XVSRANI_D_Q */
16238
    LASX256, LASX256, LASX256, uimm7, 
16239
    /* XVSRANI_H_W */
16240
    LASX256, LASX256, LASX256, uimm5, 
16241
    /* XVSRANI_W_D */
16242
    LASX256, LASX256, LASX256, uimm6, 
16243
    /* XVSRAN_B_H */
16244
    LASX256, LASX256, LASX256, 
16245
    /* XVSRAN_H_W */
16246
    LASX256, LASX256, LASX256, 
16247
    /* XVSRAN_W_D */
16248
    LASX256, LASX256, LASX256, 
16249
    /* XVSRARI_B */
16250
    LASX256, LASX256, uimm3, 
16251
    /* XVSRARI_D */
16252
    LASX256, LASX256, uimm6, 
16253
    /* XVSRARI_H */
16254
    LASX256, LASX256, uimm4, 
16255
    /* XVSRARI_W */
16256
    LASX256, LASX256, uimm5, 
16257
    /* XVSRARNI_B_H */
16258
    LASX256, LASX256, LASX256, uimm4, 
16259
    /* XVSRARNI_D_Q */
16260
    LASX256, LASX256, LASX256, uimm7, 
16261
    /* XVSRARNI_H_W */
16262
    LASX256, LASX256, LASX256, uimm5, 
16263
    /* XVSRARNI_W_D */
16264
    LASX256, LASX256, LASX256, uimm6, 
16265
    /* XVSRARN_B_H */
16266
    LASX256, LASX256, LASX256, 
16267
    /* XVSRARN_H_W */
16268
    LASX256, LASX256, LASX256, 
16269
    /* XVSRARN_W_D */
16270
    LASX256, LASX256, LASX256, 
16271
    /* XVSRAR_B */
16272
    LASX256, LASX256, LASX256, 
16273
    /* XVSRAR_D */
16274
    LASX256, LASX256, LASX256, 
16275
    /* XVSRAR_H */
16276
    LASX256, LASX256, LASX256, 
16277
    /* XVSRAR_W */
16278
    LASX256, LASX256, LASX256, 
16279
    /* XVSRA_B */
16280
    LASX256, LASX256, LASX256, 
16281
    /* XVSRA_D */
16282
    LASX256, LASX256, LASX256, 
16283
    /* XVSRA_H */
16284
    LASX256, LASX256, LASX256, 
16285
    /* XVSRA_W */
16286
    LASX256, LASX256, LASX256, 
16287
    /* XVSRLI_B */
16288
    LASX256, LASX256, uimm3, 
16289
    /* XVSRLI_D */
16290
    LASX256, LASX256, uimm6, 
16291
    /* XVSRLI_H */
16292
    LASX256, LASX256, uimm4, 
16293
    /* XVSRLI_W */
16294
    LASX256, LASX256, uimm5, 
16295
    /* XVSRLNI_B_H */
16296
    LASX256, LASX256, LASX256, uimm4, 
16297
    /* XVSRLNI_D_Q */
16298
    LASX256, LASX256, LASX256, uimm7, 
16299
    /* XVSRLNI_H_W */
16300
    LASX256, LASX256, LASX256, uimm5, 
16301
    /* XVSRLNI_W_D */
16302
    LASX256, LASX256, LASX256, uimm6, 
16303
    /* XVSRLN_B_H */
16304
    LASX256, LASX256, LASX256, 
16305
    /* XVSRLN_H_W */
16306
    LASX256, LASX256, LASX256, 
16307
    /* XVSRLN_W_D */
16308
    LASX256, LASX256, LASX256, 
16309
    /* XVSRLRI_B */
16310
    LASX256, LASX256, uimm3, 
16311
    /* XVSRLRI_D */
16312
    LASX256, LASX256, uimm6, 
16313
    /* XVSRLRI_H */
16314
    LASX256, LASX256, uimm4, 
16315
    /* XVSRLRI_W */
16316
    LASX256, LASX256, uimm5, 
16317
    /* XVSRLRNI_B_H */
16318
    LASX256, LASX256, LASX256, uimm4, 
16319
    /* XVSRLRNI_D_Q */
16320
    LASX256, LASX256, LASX256, uimm7, 
16321
    /* XVSRLRNI_H_W */
16322
    LASX256, LASX256, LASX256, uimm5, 
16323
    /* XVSRLRNI_W_D */
16324
    LASX256, LASX256, LASX256, uimm6, 
16325
    /* XVSRLRN_B_H */
16326
    LASX256, LASX256, LASX256, 
16327
    /* XVSRLRN_H_W */
16328
    LASX256, LASX256, LASX256, 
16329
    /* XVSRLRN_W_D */
16330
    LASX256, LASX256, LASX256, 
16331
    /* XVSRLR_B */
16332
    LASX256, LASX256, LASX256, 
16333
    /* XVSRLR_D */
16334
    LASX256, LASX256, LASX256, 
16335
    /* XVSRLR_H */
16336
    LASX256, LASX256, LASX256, 
16337
    /* XVSRLR_W */
16338
    LASX256, LASX256, LASX256, 
16339
    /* XVSRL_B */
16340
    LASX256, LASX256, LASX256, 
16341
    /* XVSRL_D */
16342
    LASX256, LASX256, LASX256, 
16343
    /* XVSRL_H */
16344
    LASX256, LASX256, LASX256, 
16345
    /* XVSRL_W */
16346
    LASX256, LASX256, LASX256, 
16347
    /* XVSSRANI_BU_H */
16348
    LASX256, LASX256, LASX256, uimm4, 
16349
    /* XVSSRANI_B_H */
16350
    LASX256, LASX256, LASX256, uimm4, 
16351
    /* XVSSRANI_DU_Q */
16352
    LASX256, LASX256, LASX256, uimm7, 
16353
    /* XVSSRANI_D_Q */
16354
    LASX256, LASX256, LASX256, uimm7, 
16355
    /* XVSSRANI_HU_W */
16356
    LASX256, LASX256, LASX256, uimm5, 
16357
    /* XVSSRANI_H_W */
16358
    LASX256, LASX256, LASX256, uimm5, 
16359
    /* XVSSRANI_WU_D */
16360
    LASX256, LASX256, LASX256, uimm6, 
16361
    /* XVSSRANI_W_D */
16362
    LASX256, LASX256, LASX256, uimm6, 
16363
    /* XVSSRAN_BU_H */
16364
    LASX256, LASX256, LASX256, 
16365
    /* XVSSRAN_B_H */
16366
    LASX256, LASX256, LASX256, 
16367
    /* XVSSRAN_HU_W */
16368
    LASX256, LASX256, LASX256, 
16369
    /* XVSSRAN_H_W */
16370
    LASX256, LASX256, LASX256, 
16371
    /* XVSSRAN_WU_D */
16372
    LASX256, LASX256, LASX256, 
16373
    /* XVSSRAN_W_D */
16374
    LASX256, LASX256, LASX256, 
16375
    /* XVSSRARNI_BU_H */
16376
    LASX256, LASX256, LASX256, uimm4, 
16377
    /* XVSSRARNI_B_H */
16378
    LASX256, LASX256, LASX256, uimm4, 
16379
    /* XVSSRARNI_DU_Q */
16380
    LASX256, LASX256, LASX256, uimm7, 
16381
    /* XVSSRARNI_D_Q */
16382
    LASX256, LASX256, LASX256, uimm7, 
16383
    /* XVSSRARNI_HU_W */
16384
    LASX256, LASX256, LASX256, uimm5, 
16385
    /* XVSSRARNI_H_W */
16386
    LASX256, LASX256, LASX256, uimm5, 
16387
    /* XVSSRARNI_WU_D */
16388
    LASX256, LASX256, LASX256, uimm6, 
16389
    /* XVSSRARNI_W_D */
16390
    LASX256, LASX256, LASX256, uimm6, 
16391
    /* XVSSRARN_BU_H */
16392
    LASX256, LASX256, LASX256, 
16393
    /* XVSSRARN_B_H */
16394
    LASX256, LASX256, LASX256, 
16395
    /* XVSSRARN_HU_W */
16396
    LASX256, LASX256, LASX256, 
16397
    /* XVSSRARN_H_W */
16398
    LASX256, LASX256, LASX256, 
16399
    /* XVSSRARN_WU_D */
16400
    LASX256, LASX256, LASX256, 
16401
    /* XVSSRARN_W_D */
16402
    LASX256, LASX256, LASX256, 
16403
    /* XVSSRLNI_BU_H */
16404
    LASX256, LASX256, LASX256, uimm4, 
16405
    /* XVSSRLNI_B_H */
16406
    LASX256, LASX256, LASX256, uimm4, 
16407
    /* XVSSRLNI_DU_Q */
16408
    LASX256, LASX256, LASX256, uimm7, 
16409
    /* XVSSRLNI_D_Q */
16410
    LASX256, LASX256, LASX256, uimm7, 
16411
    /* XVSSRLNI_HU_W */
16412
    LASX256, LASX256, LASX256, uimm5, 
16413
    /* XVSSRLNI_H_W */
16414
    LASX256, LASX256, LASX256, uimm5, 
16415
    /* XVSSRLNI_WU_D */
16416
    LASX256, LASX256, LASX256, uimm6, 
16417
    /* XVSSRLNI_W_D */
16418
    LASX256, LASX256, LASX256, uimm6, 
16419
    /* XVSSRLN_BU_H */
16420
    LASX256, LASX256, LASX256, 
16421
    /* XVSSRLN_B_H */
16422
    LASX256, LASX256, LASX256, 
16423
    /* XVSSRLN_HU_W */
16424
    LASX256, LASX256, LASX256, 
16425
    /* XVSSRLN_H_W */
16426
    LASX256, LASX256, LASX256, 
16427
    /* XVSSRLN_WU_D */
16428
    LASX256, LASX256, LASX256, 
16429
    /* XVSSRLN_W_D */
16430
    LASX256, LASX256, LASX256, 
16431
    /* XVSSRLRNI_BU_H */
16432
    LASX256, LASX256, LASX256, uimm4, 
16433
    /* XVSSRLRNI_B_H */
16434
    LASX256, LASX256, LASX256, uimm4, 
16435
    /* XVSSRLRNI_DU_Q */
16436
    LASX256, LASX256, LASX256, uimm7, 
16437
    /* XVSSRLRNI_D_Q */
16438
    LASX256, LASX256, LASX256, uimm7, 
16439
    /* XVSSRLRNI_HU_W */
16440
    LASX256, LASX256, LASX256, uimm5, 
16441
    /* XVSSRLRNI_H_W */
16442
    LASX256, LASX256, LASX256, uimm5, 
16443
    /* XVSSRLRNI_WU_D */
16444
    LASX256, LASX256, LASX256, uimm6, 
16445
    /* XVSSRLRNI_W_D */
16446
    LASX256, LASX256, LASX256, uimm6, 
16447
    /* XVSSRLRN_BU_H */
16448
    LASX256, LASX256, LASX256, 
16449
    /* XVSSRLRN_B_H */
16450
    LASX256, LASX256, LASX256, 
16451
    /* XVSSRLRN_HU_W */
16452
    LASX256, LASX256, LASX256, 
16453
    /* XVSSRLRN_H_W */
16454
    LASX256, LASX256, LASX256, 
16455
    /* XVSSRLRN_WU_D */
16456
    LASX256, LASX256, LASX256, 
16457
    /* XVSSRLRN_W_D */
16458
    LASX256, LASX256, LASX256, 
16459
    /* XVSSUB_B */
16460
    LASX256, LASX256, LASX256, 
16461
    /* XVSSUB_BU */
16462
    LASX256, LASX256, LASX256, 
16463
    /* XVSSUB_D */
16464
    LASX256, LASX256, LASX256, 
16465
    /* XVSSUB_DU */
16466
    LASX256, LASX256, LASX256, 
16467
    /* XVSSUB_H */
16468
    LASX256, LASX256, LASX256, 
16469
    /* XVSSUB_HU */
16470
    LASX256, LASX256, LASX256, 
16471
    /* XVSSUB_W */
16472
    LASX256, LASX256, LASX256, 
16473
    /* XVSSUB_WU */
16474
    LASX256, LASX256, LASX256, 
16475
    /* XVST */
16476
    LASX256, GPR, simm12, 
16477
    /* XVSTELM_B */
16478
    LASX256, GPR, simm8, uimm5, 
16479
    /* XVSTELM_D */
16480
    LASX256, GPR, simm8_lsl3, uimm2, 
16481
    /* XVSTELM_H */
16482
    LASX256, GPR, simm8_lsl1, uimm4, 
16483
    /* XVSTELM_W */
16484
    LASX256, GPR, simm8_lsl2, uimm3, 
16485
    /* XVSTX */
16486
    LASX256, GPR, GPR, 
16487
    /* XVSUBI_BU */
16488
    LASX256, LASX256, uimm5, 
16489
    /* XVSUBI_DU */
16490
    LASX256, LASX256, uimm5, 
16491
    /* XVSUBI_HU */
16492
    LASX256, LASX256, uimm5, 
16493
    /* XVSUBI_WU */
16494
    LASX256, LASX256, uimm5, 
16495
    /* XVSUBWEV_D_W */
16496
    LASX256, LASX256, LASX256, 
16497
    /* XVSUBWEV_D_WU */
16498
    LASX256, LASX256, LASX256, 
16499
    /* XVSUBWEV_H_B */
16500
    LASX256, LASX256, LASX256, 
16501
    /* XVSUBWEV_H_BU */
16502
    LASX256, LASX256, LASX256, 
16503
    /* XVSUBWEV_Q_D */
16504
    LASX256, LASX256, LASX256, 
16505
    /* XVSUBWEV_Q_DU */
16506
    LASX256, LASX256, LASX256, 
16507
    /* XVSUBWEV_W_H */
16508
    LASX256, LASX256, LASX256, 
16509
    /* XVSUBWEV_W_HU */
16510
    LASX256, LASX256, LASX256, 
16511
    /* XVSUBWOD_D_W */
16512
    LASX256, LASX256, LASX256, 
16513
    /* XVSUBWOD_D_WU */
16514
    LASX256, LASX256, LASX256, 
16515
    /* XVSUBWOD_H_B */
16516
    LASX256, LASX256, LASX256, 
16517
    /* XVSUBWOD_H_BU */
16518
    LASX256, LASX256, LASX256, 
16519
    /* XVSUBWOD_Q_D */
16520
    LASX256, LASX256, LASX256, 
16521
    /* XVSUBWOD_Q_DU */
16522
    LASX256, LASX256, LASX256, 
16523
    /* XVSUBWOD_W_H */
16524
    LASX256, LASX256, LASX256, 
16525
    /* XVSUBWOD_W_HU */
16526
    LASX256, LASX256, LASX256, 
16527
    /* XVSUB_B */
16528
    LASX256, LASX256, LASX256, 
16529
    /* XVSUB_D */
16530
    LASX256, LASX256, LASX256, 
16531
    /* XVSUB_H */
16532
    LASX256, LASX256, LASX256, 
16533
    /* XVSUB_Q */
16534
    LASX256, LASX256, LASX256, 
16535
    /* XVSUB_W */
16536
    LASX256, LASX256, LASX256, 
16537
    /* XVXORI_B */
16538
    LASX256, LASX256, uimm8, 
16539
    /* XVXOR_V */
16540
    LASX256, LASX256, LASX256, 
16541
  };
16542
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
16543
}
16544
} // end namespace LoongArch
16545
} // end namespace llvm
16546
#endif // GET_INSTRINFO_OPERAND_TYPE
16547
16548
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
16549
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
16550
namespace llvm {
16551
namespace LoongArch {
16552
LLVM_READONLY
16553
static int getMemOperandSize(int OpType) {
16554
  switch (OpType) {
16555
  default: return 0;
16556
  }
16557
}
16558
} // end namespace LoongArch
16559
} // end namespace llvm
16560
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
16561
16562
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
16563
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
16564
namespace llvm {
16565
namespace LoongArch {
16566
LLVM_READONLY static unsigned
16567
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
16568
  return LogicalOpIdx;
16569
}
16570
LLVM_READONLY static inline unsigned
16571
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
16572
  auto S = 0U;
16573
  for (auto i = 0U; i < LogicalOpIdx; ++i)
16574
    S += getLogicalOperandSize(Opcode, i);
16575
  return S;
16576
}
16577
} // end namespace LoongArch
16578
} // end namespace llvm
16579
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
16580
16581
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
16582
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
16583
namespace llvm {
16584
namespace LoongArch {
16585
LLVM_READONLY static int
16586
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
16587
  return -1;
16588
}
16589
} // end namespace LoongArch
16590
} // end namespace llvm
16591
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
16592
16593
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
16594
#undef GET_INSTRINFO_MC_HELPER_DECLS
16595
16596
namespace llvm {
16597
class MCInst;
16598
class FeatureBitset;
16599
16600
namespace LoongArch_MC {
16601
16602
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
16603
16604
} // end namespace LoongArch_MC
16605
} // end namespace llvm
16606
16607
#endif // GET_INSTRINFO_MC_HELPER_DECLS
16608
16609
#ifdef GET_INSTRINFO_MC_HELPERS
16610
#undef GET_INSTRINFO_MC_HELPERS
16611
16612
namespace llvm {
16613
namespace LoongArch_MC {
16614
16615
} // end namespace LoongArch_MC
16616
} // end namespace llvm
16617
16618
#endif // GET_GENISTRINFO_MC_HELPERS
16619
16620
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
16621
    defined(GET_AVAILABLE_OPCODE_CHECKER)
16622
#define GET_COMPUTE_FEATURES
16623
#endif
16624
#ifdef GET_COMPUTE_FEATURES
16625
#undef GET_COMPUTE_FEATURES
16626
namespace llvm {
16627
namespace LoongArch_MC {
16628
16629
// Bits for subtarget features that participate in instruction matching.
16630
enum SubtargetFeatureBits : uint8_t {
16631
  Feature_IsLA64Bit = 4,
16632
  Feature_IsLA32Bit = 3,
16633
  Feature_HasLaGlobalWithPcrelBit = 1,
16634
  Feature_HasLaGlobalWithAbsBit = 0,
16635
  Feature_HasLaLocalWithAbsBit = 2,
16636
};
16637
16638
0
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
16639
0
  FeatureBitset Features;
16640
0
  if (FB[LoongArch::Feature64Bit])
16641
0
    Features.set(Feature_IsLA64Bit);
16642
0
  if (!FB[LoongArch::Feature64Bit])
16643
0
    Features.set(Feature_IsLA32Bit);
16644
0
  if (FB[LoongArch::LaGlobalWithPcrel])
16645
0
    Features.set(Feature_HasLaGlobalWithPcrelBit);
16646
0
  if (FB[LoongArch::LaGlobalWithAbs])
16647
0
    Features.set(Feature_HasLaGlobalWithAbsBit);
16648
0
  if (FB[LoongArch::LaLocalWithAbs])
16649
0
    Features.set(Feature_HasLaLocalWithAbsBit);
16650
0
  return Features;
16651
0
}
16652
16653
0
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
16654
0
  enum : uint8_t {
16655
0
    CEFBS_None,
16656
0
    CEFBS_IsLA32,
16657
0
    CEFBS_IsLA64,
16658
0
  };
16659
16660
0
  static constexpr FeatureBitset FeatureBitsets[] = {
16661
0
    {}, // CEFBS_None
16662
0
    {Feature_IsLA32Bit, },
16663
0
    {Feature_IsLA64Bit, },
16664
0
  };
16665
0
  static constexpr uint8_t RequiredFeaturesRefs[] = {
16666
0
    CEFBS_None, // PHI = 0
16667
0
    CEFBS_None, // INLINEASM = 1
16668
0
    CEFBS_None, // INLINEASM_BR = 2
16669
0
    CEFBS_None, // CFI_INSTRUCTION = 3
16670
0
    CEFBS_None, // EH_LABEL = 4
16671
0
    CEFBS_None, // GC_LABEL = 5
16672
0
    CEFBS_None, // ANNOTATION_LABEL = 6
16673
0
    CEFBS_None, // KILL = 7
16674
0
    CEFBS_None, // EXTRACT_SUBREG = 8
16675
0
    CEFBS_None, // INSERT_SUBREG = 9
16676
0
    CEFBS_None, // IMPLICIT_DEF = 10
16677
0
    CEFBS_None, // SUBREG_TO_REG = 11
16678
0
    CEFBS_None, // COPY_TO_REGCLASS = 12
16679
0
    CEFBS_None, // DBG_VALUE = 13
16680
0
    CEFBS_None, // DBG_VALUE_LIST = 14
16681
0
    CEFBS_None, // DBG_INSTR_REF = 15
16682
0
    CEFBS_None, // DBG_PHI = 16
16683
0
    CEFBS_None, // DBG_LABEL = 17
16684
0
    CEFBS_None, // REG_SEQUENCE = 18
16685
0
    CEFBS_None, // COPY = 19
16686
0
    CEFBS_None, // BUNDLE = 20
16687
0
    CEFBS_None, // LIFETIME_START = 21
16688
0
    CEFBS_None, // LIFETIME_END = 22
16689
0
    CEFBS_None, // PSEUDO_PROBE = 23
16690
0
    CEFBS_None, // ARITH_FENCE = 24
16691
0
    CEFBS_None, // STACKMAP = 25
16692
0
    CEFBS_None, // FENTRY_CALL = 26
16693
0
    CEFBS_None, // PATCHPOINT = 27
16694
0
    CEFBS_None, // LOAD_STACK_GUARD = 28
16695
0
    CEFBS_None, // PREALLOCATED_SETUP = 29
16696
0
    CEFBS_None, // PREALLOCATED_ARG = 30
16697
0
    CEFBS_None, // STATEPOINT = 31
16698
0
    CEFBS_None, // LOCAL_ESCAPE = 32
16699
0
    CEFBS_None, // FAULTING_OP = 33
16700
0
    CEFBS_None, // PATCHABLE_OP = 34
16701
0
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
16702
0
    CEFBS_None, // PATCHABLE_RET = 36
16703
0
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
16704
0
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
16705
0
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
16706
0
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
16707
0
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
16708
0
    CEFBS_None, // MEMBARRIER = 42
16709
0
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
16710
0
    CEFBS_None, // G_ASSERT_SEXT = 44
16711
0
    CEFBS_None, // G_ASSERT_ZEXT = 45
16712
0
    CEFBS_None, // G_ASSERT_ALIGN = 46
16713
0
    CEFBS_None, // G_ADD = 47
16714
0
    CEFBS_None, // G_SUB = 48
16715
0
    CEFBS_None, // G_MUL = 49
16716
0
    CEFBS_None, // G_SDIV = 50
16717
0
    CEFBS_None, // G_UDIV = 51
16718
0
    CEFBS_None, // G_SREM = 52
16719
0
    CEFBS_None, // G_UREM = 53
16720
0
    CEFBS_None, // G_SDIVREM = 54
16721
0
    CEFBS_None, // G_UDIVREM = 55
16722
0
    CEFBS_None, // G_AND = 56
16723
0
    CEFBS_None, // G_OR = 57
16724
0
    CEFBS_None, // G_XOR = 58
16725
0
    CEFBS_None, // G_IMPLICIT_DEF = 59
16726
0
    CEFBS_None, // G_PHI = 60
16727
0
    CEFBS_None, // G_FRAME_INDEX = 61
16728
0
    CEFBS_None, // G_GLOBAL_VALUE = 62
16729
0
    CEFBS_None, // G_CONSTANT_POOL = 63
16730
0
    CEFBS_None, // G_EXTRACT = 64
16731
0
    CEFBS_None, // G_UNMERGE_VALUES = 65
16732
0
    CEFBS_None, // G_INSERT = 66
16733
0
    CEFBS_None, // G_MERGE_VALUES = 67
16734
0
    CEFBS_None, // G_BUILD_VECTOR = 68
16735
0
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
16736
0
    CEFBS_None, // G_CONCAT_VECTORS = 70
16737
0
    CEFBS_None, // G_PTRTOINT = 71
16738
0
    CEFBS_None, // G_INTTOPTR = 72
16739
0
    CEFBS_None, // G_BITCAST = 73
16740
0
    CEFBS_None, // G_FREEZE = 74
16741
0
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
16742
0
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
16743
0
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
16744
0
    CEFBS_None, // G_INTRINSIC_ROUND = 78
16745
0
    CEFBS_None, // G_INTRINSIC_LRINT = 79
16746
0
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
16747
0
    CEFBS_None, // G_READCYCLECOUNTER = 81
16748
0
    CEFBS_None, // G_LOAD = 82
16749
0
    CEFBS_None, // G_SEXTLOAD = 83
16750
0
    CEFBS_None, // G_ZEXTLOAD = 84
16751
0
    CEFBS_None, // G_INDEXED_LOAD = 85
16752
0
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
16753
0
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
16754
0
    CEFBS_None, // G_STORE = 88
16755
0
    CEFBS_None, // G_INDEXED_STORE = 89
16756
0
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
16757
0
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
16758
0
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
16759
0
    CEFBS_None, // G_ATOMICRMW_ADD = 93
16760
0
    CEFBS_None, // G_ATOMICRMW_SUB = 94
16761
0
    CEFBS_None, // G_ATOMICRMW_AND = 95
16762
0
    CEFBS_None, // G_ATOMICRMW_NAND = 96
16763
0
    CEFBS_None, // G_ATOMICRMW_OR = 97
16764
0
    CEFBS_None, // G_ATOMICRMW_XOR = 98
16765
0
    CEFBS_None, // G_ATOMICRMW_MAX = 99
16766
0
    CEFBS_None, // G_ATOMICRMW_MIN = 100
16767
0
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
16768
0
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
16769
0
    CEFBS_None, // G_ATOMICRMW_FADD = 103
16770
0
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
16771
0
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
16772
0
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
16773
0
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
16774
0
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
16775
0
    CEFBS_None, // G_FENCE = 109
16776
0
    CEFBS_None, // G_PREFETCH = 110
16777
0
    CEFBS_None, // G_BRCOND = 111
16778
0
    CEFBS_None, // G_BRINDIRECT = 112
16779
0
    CEFBS_None, // G_INVOKE_REGION_START = 113
16780
0
    CEFBS_None, // G_INTRINSIC = 114
16781
0
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
16782
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
16783
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
16784
0
    CEFBS_None, // G_ANYEXT = 118
16785
0
    CEFBS_None, // G_TRUNC = 119
16786
0
    CEFBS_None, // G_CONSTANT = 120
16787
0
    CEFBS_None, // G_FCONSTANT = 121
16788
0
    CEFBS_None, // G_VASTART = 122
16789
0
    CEFBS_None, // G_VAARG = 123
16790
0
    CEFBS_None, // G_SEXT = 124
16791
0
    CEFBS_None, // G_SEXT_INREG = 125
16792
0
    CEFBS_None, // G_ZEXT = 126
16793
0
    CEFBS_None, // G_SHL = 127
16794
0
    CEFBS_None, // G_LSHR = 128
16795
0
    CEFBS_None, // G_ASHR = 129
16796
0
    CEFBS_None, // G_FSHL = 130
16797
0
    CEFBS_None, // G_FSHR = 131
16798
0
    CEFBS_None, // G_ROTR = 132
16799
0
    CEFBS_None, // G_ROTL = 133
16800
0
    CEFBS_None, // G_ICMP = 134
16801
0
    CEFBS_None, // G_FCMP = 135
16802
0
    CEFBS_None, // G_SELECT = 136
16803
0
    CEFBS_None, // G_UADDO = 137
16804
0
    CEFBS_None, // G_UADDE = 138
16805
0
    CEFBS_None, // G_USUBO = 139
16806
0
    CEFBS_None, // G_USUBE = 140
16807
0
    CEFBS_None, // G_SADDO = 141
16808
0
    CEFBS_None, // G_SADDE = 142
16809
0
    CEFBS_None, // G_SSUBO = 143
16810
0
    CEFBS_None, // G_SSUBE = 144
16811
0
    CEFBS_None, // G_UMULO = 145
16812
0
    CEFBS_None, // G_SMULO = 146
16813
0
    CEFBS_None, // G_UMULH = 147
16814
0
    CEFBS_None, // G_SMULH = 148
16815
0
    CEFBS_None, // G_UADDSAT = 149
16816
0
    CEFBS_None, // G_SADDSAT = 150
16817
0
    CEFBS_None, // G_USUBSAT = 151
16818
0
    CEFBS_None, // G_SSUBSAT = 152
16819
0
    CEFBS_None, // G_USHLSAT = 153
16820
0
    CEFBS_None, // G_SSHLSAT = 154
16821
0
    CEFBS_None, // G_SMULFIX = 155
16822
0
    CEFBS_None, // G_UMULFIX = 156
16823
0
    CEFBS_None, // G_SMULFIXSAT = 157
16824
0
    CEFBS_None, // G_UMULFIXSAT = 158
16825
0
    CEFBS_None, // G_SDIVFIX = 159
16826
0
    CEFBS_None, // G_UDIVFIX = 160
16827
0
    CEFBS_None, // G_SDIVFIXSAT = 161
16828
0
    CEFBS_None, // G_UDIVFIXSAT = 162
16829
0
    CEFBS_None, // G_FADD = 163
16830
0
    CEFBS_None, // G_FSUB = 164
16831
0
    CEFBS_None, // G_FMUL = 165
16832
0
    CEFBS_None, // G_FMA = 166
16833
0
    CEFBS_None, // G_FMAD = 167
16834
0
    CEFBS_None, // G_FDIV = 168
16835
0
    CEFBS_None, // G_FREM = 169
16836
0
    CEFBS_None, // G_FPOW = 170
16837
0
    CEFBS_None, // G_FPOWI = 171
16838
0
    CEFBS_None, // G_FEXP = 172
16839
0
    CEFBS_None, // G_FEXP2 = 173
16840
0
    CEFBS_None, // G_FEXP10 = 174
16841
0
    CEFBS_None, // G_FLOG = 175
16842
0
    CEFBS_None, // G_FLOG2 = 176
16843
0
    CEFBS_None, // G_FLOG10 = 177
16844
0
    CEFBS_None, // G_FLDEXP = 178
16845
0
    CEFBS_None, // G_FFREXP = 179
16846
0
    CEFBS_None, // G_FNEG = 180
16847
0
    CEFBS_None, // G_FPEXT = 181
16848
0
    CEFBS_None, // G_FPTRUNC = 182
16849
0
    CEFBS_None, // G_FPTOSI = 183
16850
0
    CEFBS_None, // G_FPTOUI = 184
16851
0
    CEFBS_None, // G_SITOFP = 185
16852
0
    CEFBS_None, // G_UITOFP = 186
16853
0
    CEFBS_None, // G_FABS = 187
16854
0
    CEFBS_None, // G_FCOPYSIGN = 188
16855
0
    CEFBS_None, // G_IS_FPCLASS = 189
16856
0
    CEFBS_None, // G_FCANONICALIZE = 190
16857
0
    CEFBS_None, // G_FMINNUM = 191
16858
0
    CEFBS_None, // G_FMAXNUM = 192
16859
0
    CEFBS_None, // G_FMINNUM_IEEE = 193
16860
0
    CEFBS_None, // G_FMAXNUM_IEEE = 194
16861
0
    CEFBS_None, // G_FMINIMUM = 195
16862
0
    CEFBS_None, // G_FMAXIMUM = 196
16863
0
    CEFBS_None, // G_GET_FPENV = 197
16864
0
    CEFBS_None, // G_SET_FPENV = 198
16865
0
    CEFBS_None, // G_RESET_FPENV = 199
16866
0
    CEFBS_None, // G_GET_FPMODE = 200
16867
0
    CEFBS_None, // G_SET_FPMODE = 201
16868
0
    CEFBS_None, // G_RESET_FPMODE = 202
16869
0
    CEFBS_None, // G_PTR_ADD = 203
16870
0
    CEFBS_None, // G_PTRMASK = 204
16871
0
    CEFBS_None, // G_SMIN = 205
16872
0
    CEFBS_None, // G_SMAX = 206
16873
0
    CEFBS_None, // G_UMIN = 207
16874
0
    CEFBS_None, // G_UMAX = 208
16875
0
    CEFBS_None, // G_ABS = 209
16876
0
    CEFBS_None, // G_LROUND = 210
16877
0
    CEFBS_None, // G_LLROUND = 211
16878
0
    CEFBS_None, // G_BR = 212
16879
0
    CEFBS_None, // G_BRJT = 213
16880
0
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
16881
0
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
16882
0
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
16883
0
    CEFBS_None, // G_CTTZ = 217
16884
0
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
16885
0
    CEFBS_None, // G_CTLZ = 219
16886
0
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
16887
0
    CEFBS_None, // G_CTPOP = 221
16888
0
    CEFBS_None, // G_BSWAP = 222
16889
0
    CEFBS_None, // G_BITREVERSE = 223
16890
0
    CEFBS_None, // G_FCEIL = 224
16891
0
    CEFBS_None, // G_FCOS = 225
16892
0
    CEFBS_None, // G_FSIN = 226
16893
0
    CEFBS_None, // G_FSQRT = 227
16894
0
    CEFBS_None, // G_FFLOOR = 228
16895
0
    CEFBS_None, // G_FRINT = 229
16896
0
    CEFBS_None, // G_FNEARBYINT = 230
16897
0
    CEFBS_None, // G_ADDRSPACE_CAST = 231
16898
0
    CEFBS_None, // G_BLOCK_ADDR = 232
16899
0
    CEFBS_None, // G_JUMP_TABLE = 233
16900
0
    CEFBS_None, // G_DYN_STACKALLOC = 234
16901
0
    CEFBS_None, // G_STACKSAVE = 235
16902
0
    CEFBS_None, // G_STACKRESTORE = 236
16903
0
    CEFBS_None, // G_STRICT_FADD = 237
16904
0
    CEFBS_None, // G_STRICT_FSUB = 238
16905
0
    CEFBS_None, // G_STRICT_FMUL = 239
16906
0
    CEFBS_None, // G_STRICT_FDIV = 240
16907
0
    CEFBS_None, // G_STRICT_FREM = 241
16908
0
    CEFBS_None, // G_STRICT_FMA = 242
16909
0
    CEFBS_None, // G_STRICT_FSQRT = 243
16910
0
    CEFBS_None, // G_STRICT_FLDEXP = 244
16911
0
    CEFBS_None, // G_READ_REGISTER = 245
16912
0
    CEFBS_None, // G_WRITE_REGISTER = 246
16913
0
    CEFBS_None, // G_MEMCPY = 247
16914
0
    CEFBS_None, // G_MEMCPY_INLINE = 248
16915
0
    CEFBS_None, // G_MEMMOVE = 249
16916
0
    CEFBS_None, // G_MEMSET = 250
16917
0
    CEFBS_None, // G_BZERO = 251
16918
0
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
16919
0
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
16920
0
    CEFBS_None, // G_VECREDUCE_FADD = 254
16921
0
    CEFBS_None, // G_VECREDUCE_FMUL = 255
16922
0
    CEFBS_None, // G_VECREDUCE_FMAX = 256
16923
0
    CEFBS_None, // G_VECREDUCE_FMIN = 257
16924
0
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
16925
0
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
16926
0
    CEFBS_None, // G_VECREDUCE_ADD = 260
16927
0
    CEFBS_None, // G_VECREDUCE_MUL = 261
16928
0
    CEFBS_None, // G_VECREDUCE_AND = 262
16929
0
    CEFBS_None, // G_VECREDUCE_OR = 263
16930
0
    CEFBS_None, // G_VECREDUCE_XOR = 264
16931
0
    CEFBS_None, // G_VECREDUCE_SMAX = 265
16932
0
    CEFBS_None, // G_VECREDUCE_SMIN = 266
16933
0
    CEFBS_None, // G_VECREDUCE_UMAX = 267
16934
0
    CEFBS_None, // G_VECREDUCE_UMIN = 268
16935
0
    CEFBS_None, // G_SBFX = 269
16936
0
    CEFBS_None, // G_UBFX = 270
16937
0
    CEFBS_None, // ADJCALLSTACKDOWN = 271
16938
0
    CEFBS_None, // ADJCALLSTACKUP = 272
16939
0
    CEFBS_None, // PseudoAtomicLoadAdd32 = 273
16940
0
    CEFBS_None, // PseudoAtomicLoadAnd32 = 274
16941
0
    CEFBS_None, // PseudoAtomicLoadNand32 = 275
16942
0
    CEFBS_None, // PseudoAtomicLoadNand64 = 276
16943
0
    CEFBS_None, // PseudoAtomicLoadOr32 = 277
16944
0
    CEFBS_None, // PseudoAtomicLoadSub32 = 278
16945
0
    CEFBS_None, // PseudoAtomicLoadXor32 = 279
16946
0
    CEFBS_IsLA64, // PseudoAtomicStoreD = 280
16947
0
    CEFBS_None, // PseudoAtomicStoreW = 281
16948
0
    CEFBS_None, // PseudoAtomicSwap32 = 282
16949
0
    CEFBS_None, // PseudoBR = 283
16950
0
    CEFBS_None, // PseudoBRIND = 284
16951
0
    CEFBS_None, // PseudoB_TAIL = 285
16952
0
    CEFBS_None, // PseudoCALL = 286
16953
0
    CEFBS_IsLA64, // PseudoCALL36 = 287
16954
0
    CEFBS_None, // PseudoCALLIndirect = 288
16955
0
    CEFBS_None, // PseudoCALL_LARGE = 289
16956
0
    CEFBS_None, // PseudoCALL_MEDIUM = 290
16957
0
    CEFBS_None, // PseudoCmpXchg32 = 291
16958
0
    CEFBS_None, // PseudoCmpXchg64 = 292
16959
0
    CEFBS_None, // PseudoCopyCFR = 293
16960
0
    CEFBS_None, // PseudoJIRL_CALL = 294
16961
0
    CEFBS_None, // PseudoJIRL_TAIL = 295
16962
0
    CEFBS_None, // PseudoLA_ABS = 296
16963
0
    CEFBS_None, // PseudoLA_ABS_LARGE = 297
16964
0
    CEFBS_None, // PseudoLA_GOT = 298
16965
0
    CEFBS_IsLA64, // PseudoLA_GOT_LARGE = 299
16966
0
    CEFBS_None, // PseudoLA_PCREL = 300
16967
0
    CEFBS_IsLA64, // PseudoLA_PCREL_LARGE = 301
16968
0
    CEFBS_None, // PseudoLA_TLS_GD = 302
16969
0
    CEFBS_IsLA64, // PseudoLA_TLS_GD_LARGE = 303
16970
0
    CEFBS_None, // PseudoLA_TLS_IE = 304
16971
0
    CEFBS_IsLA64, // PseudoLA_TLS_IE_LARGE = 305
16972
0
    CEFBS_None, // PseudoLA_TLS_LD = 306
16973
0
    CEFBS_IsLA64, // PseudoLA_TLS_LD_LARGE = 307
16974
0
    CEFBS_None, // PseudoLA_TLS_LE = 308
16975
0
    CEFBS_None, // PseudoLD_CFR = 309
16976
0
    CEFBS_IsLA64, // PseudoLI_D = 310
16977
0
    CEFBS_None, // PseudoLI_W = 311
16978
0
    CEFBS_None, // PseudoMaskedAtomicLoadAdd32 = 312
16979
0
    CEFBS_None, // PseudoMaskedAtomicLoadMax32 = 313
16980
0
    CEFBS_None, // PseudoMaskedAtomicLoadMin32 = 314
16981
0
    CEFBS_None, // PseudoMaskedAtomicLoadNand32 = 315
16982
0
    CEFBS_None, // PseudoMaskedAtomicLoadSub32 = 316
16983
0
    CEFBS_None, // PseudoMaskedAtomicLoadUMax32 = 317
16984
0
    CEFBS_None, // PseudoMaskedAtomicLoadUMin32 = 318
16985
0
    CEFBS_None, // PseudoMaskedAtomicSwap32 = 319
16986
0
    CEFBS_None, // PseudoMaskedCmpXchg32 = 320
16987
0
    CEFBS_None, // PseudoRET = 321
16988
0
    CEFBS_None, // PseudoST_CFR = 322
16989
0
    CEFBS_None, // PseudoTAIL = 323
16990
0
    CEFBS_IsLA64, // PseudoTAIL36 = 324
16991
0
    CEFBS_None, // PseudoTAILIndirect = 325
16992
0
    CEFBS_None, // PseudoTAIL_LARGE = 326
16993
0
    CEFBS_None, // PseudoTAIL_MEDIUM = 327
16994
0
    CEFBS_None, // PseudoUNIMP = 328
16995
0
    CEFBS_None, // PseudoVBNZ = 329
16996
0
    CEFBS_None, // PseudoVBNZ_B = 330
16997
0
    CEFBS_None, // PseudoVBNZ_D = 331
16998
0
    CEFBS_None, // PseudoVBNZ_H = 332
16999
0
    CEFBS_None, // PseudoVBNZ_W = 333
17000
0
    CEFBS_None, // PseudoVBZ = 334
17001
0
    CEFBS_None, // PseudoVBZ_B = 335
17002
0
    CEFBS_None, // PseudoVBZ_D = 336
17003
0
    CEFBS_None, // PseudoVBZ_H = 337
17004
0
    CEFBS_None, // PseudoVBZ_W = 338
17005
0
    CEFBS_None, // PseudoVREPLI_B = 339
17006
0
    CEFBS_None, // PseudoVREPLI_D = 340
17007
0
    CEFBS_None, // PseudoVREPLI_H = 341
17008
0
    CEFBS_None, // PseudoVREPLI_W = 342
17009
0
    CEFBS_None, // PseudoXVBNZ = 343
17010
0
    CEFBS_None, // PseudoXVBNZ_B = 344
17011
0
    CEFBS_None, // PseudoXVBNZ_D = 345
17012
0
    CEFBS_None, // PseudoXVBNZ_H = 346
17013
0
    CEFBS_None, // PseudoXVBNZ_W = 347
17014
0
    CEFBS_None, // PseudoXVBZ = 348
17015
0
    CEFBS_None, // PseudoXVBZ_B = 349
17016
0
    CEFBS_None, // PseudoXVBZ_D = 350
17017
0
    CEFBS_None, // PseudoXVBZ_H = 351
17018
0
    CEFBS_None, // PseudoXVBZ_W = 352
17019
0
    CEFBS_None, // PseudoXVINSGR2VR_B = 353
17020
0
    CEFBS_None, // PseudoXVINSGR2VR_H = 354
17021
0
    CEFBS_None, // PseudoXVREPLI_B = 355
17022
0
    CEFBS_None, // PseudoXVREPLI_D = 356
17023
0
    CEFBS_None, // PseudoXVREPLI_H = 357
17024
0
    CEFBS_None, // PseudoXVREPLI_W = 358
17025
0
    CEFBS_None, // RDFCSR = 359
17026
0
    CEFBS_None, // WRFCSR = 360
17027
0
    CEFBS_None, // ADC_B = 361
17028
0
    CEFBS_IsLA64, // ADC_D = 362
17029
0
    CEFBS_None, // ADC_H = 363
17030
0
    CEFBS_None, // ADC_W = 364
17031
0
    CEFBS_IsLA64, // ADDI_D = 365
17032
0
    CEFBS_None, // ADDI_W = 366
17033
0
    CEFBS_IsLA64, // ADDU12I_D = 367
17034
0
    CEFBS_None, // ADDU12I_W = 368
17035
0
    CEFBS_IsLA64, // ADDU16I_D = 369
17036
0
    CEFBS_IsLA64, // ADD_D = 370
17037
0
    CEFBS_None, // ADD_W = 371
17038
0
    CEFBS_IsLA64, // ALSL_D = 372
17039
0
    CEFBS_None, // ALSL_W = 373
17040
0
    CEFBS_IsLA64, // ALSL_WU = 374
17041
0
    CEFBS_IsLA64, // AMADD_B = 375
17042
0
    CEFBS_IsLA64, // AMADD_D = 376
17043
0
    CEFBS_IsLA64, // AMADD_H = 377
17044
0
    CEFBS_IsLA64, // AMADD_W = 378
17045
0
    CEFBS_IsLA64, // AMADD__DB_B = 379
17046
0
    CEFBS_IsLA64, // AMADD__DB_D = 380
17047
0
    CEFBS_IsLA64, // AMADD__DB_H = 381
17048
0
    CEFBS_IsLA64, // AMADD__DB_W = 382
17049
0
    CEFBS_IsLA64, // AMAND_D = 383
17050
0
    CEFBS_IsLA64, // AMAND_W = 384
17051
0
    CEFBS_IsLA64, // AMAND__DB_D = 385
17052
0
    CEFBS_IsLA64, // AMAND__DB_W = 386
17053
0
    CEFBS_IsLA64, // AMCAS_B = 387
17054
0
    CEFBS_IsLA64, // AMCAS_D = 388
17055
0
    CEFBS_IsLA64, // AMCAS_H = 389
17056
0
    CEFBS_IsLA64, // AMCAS_W = 390
17057
0
    CEFBS_IsLA64, // AMCAS__DB_B = 391
17058
0
    CEFBS_IsLA64, // AMCAS__DB_D = 392
17059
0
    CEFBS_IsLA64, // AMCAS__DB_H = 393
17060
0
    CEFBS_IsLA64, // AMCAS__DB_W = 394
17061
0
    CEFBS_IsLA64, // AMMAX_D = 395
17062
0
    CEFBS_IsLA64, // AMMAX_DU = 396
17063
0
    CEFBS_IsLA64, // AMMAX_W = 397
17064
0
    CEFBS_IsLA64, // AMMAX_WU = 398
17065
0
    CEFBS_IsLA64, // AMMAX__DB_D = 399
17066
0
    CEFBS_IsLA64, // AMMAX__DB_DU = 400
17067
0
    CEFBS_IsLA64, // AMMAX__DB_W = 401
17068
0
    CEFBS_IsLA64, // AMMAX__DB_WU = 402
17069
0
    CEFBS_IsLA64, // AMMIN_D = 403
17070
0
    CEFBS_IsLA64, // AMMIN_DU = 404
17071
0
    CEFBS_IsLA64, // AMMIN_W = 405
17072
0
    CEFBS_IsLA64, // AMMIN_WU = 406
17073
0
    CEFBS_IsLA64, // AMMIN__DB_D = 407
17074
0
    CEFBS_IsLA64, // AMMIN__DB_DU = 408
17075
0
    CEFBS_IsLA64, // AMMIN__DB_W = 409
17076
0
    CEFBS_IsLA64, // AMMIN__DB_WU = 410
17077
0
    CEFBS_IsLA64, // AMOR_D = 411
17078
0
    CEFBS_IsLA64, // AMOR_W = 412
17079
0
    CEFBS_IsLA64, // AMOR__DB_D = 413
17080
0
    CEFBS_IsLA64, // AMOR__DB_W = 414
17081
0
    CEFBS_IsLA64, // AMSWAP_B = 415
17082
0
    CEFBS_IsLA64, // AMSWAP_D = 416
17083
0
    CEFBS_IsLA64, // AMSWAP_H = 417
17084
0
    CEFBS_IsLA64, // AMSWAP_W = 418
17085
0
    CEFBS_IsLA64, // AMSWAP__DB_B = 419
17086
0
    CEFBS_IsLA64, // AMSWAP__DB_D = 420
17087
0
    CEFBS_IsLA64, // AMSWAP__DB_H = 421
17088
0
    CEFBS_IsLA64, // AMSWAP__DB_W = 422
17089
0
    CEFBS_IsLA64, // AMXOR_D = 423
17090
0
    CEFBS_IsLA64, // AMXOR_W = 424
17091
0
    CEFBS_IsLA64, // AMXOR__DB_D = 425
17092
0
    CEFBS_IsLA64, // AMXOR__DB_W = 426
17093
0
    CEFBS_None, // AND = 427
17094
0
    CEFBS_None, // ANDI = 428
17095
0
    CEFBS_None, // ANDN = 429
17096
0
    CEFBS_None, // ARMADC_W = 430
17097
0
    CEFBS_None, // ARMADD_W = 431
17098
0
    CEFBS_None, // ARMAND_W = 432
17099
0
    CEFBS_None, // ARMMFFLAG = 433
17100
0
    CEFBS_None, // ARMMOVE = 434
17101
0
    CEFBS_IsLA64, // ARMMOV_D = 435
17102
0
    CEFBS_None, // ARMMOV_W = 436
17103
0
    CEFBS_None, // ARMMTFLAG = 437
17104
0
    CEFBS_None, // ARMNOT_W = 438
17105
0
    CEFBS_None, // ARMOR_W = 439
17106
0
    CEFBS_None, // ARMROTRI_W = 440
17107
0
    CEFBS_None, // ARMROTR_W = 441
17108
0
    CEFBS_None, // ARMRRX_W = 442
17109
0
    CEFBS_None, // ARMSBC_W = 443
17110
0
    CEFBS_None, // ARMSLLI_W = 444
17111
0
    CEFBS_None, // ARMSLL_W = 445
17112
0
    CEFBS_None, // ARMSRAI_W = 446
17113
0
    CEFBS_None, // ARMSRA_W = 447
17114
0
    CEFBS_None, // ARMSRLI_W = 448
17115
0
    CEFBS_None, // ARMSRL_W = 449
17116
0
    CEFBS_None, // ARMSUB_W = 450
17117
0
    CEFBS_None, // ARMXOR_W = 451
17118
0
    CEFBS_IsLA64, // ASRTGT_D = 452
17119
0
    CEFBS_IsLA64, // ASRTLE_D = 453
17120
0
    CEFBS_None, // B = 454
17121
0
    CEFBS_None, // BCEQZ = 455
17122
0
    CEFBS_None, // BCNEZ = 456
17123
0
    CEFBS_None, // BEQ = 457
17124
0
    CEFBS_None, // BEQZ = 458
17125
0
    CEFBS_None, // BGE = 459
17126
0
    CEFBS_None, // BGEU = 460
17127
0
    CEFBS_None, // BITREV_4B = 461
17128
0
    CEFBS_IsLA64, // BITREV_8B = 462
17129
0
    CEFBS_IsLA64, // BITREV_D = 463
17130
0
    CEFBS_None, // BITREV_W = 464
17131
0
    CEFBS_None, // BL = 465
17132
0
    CEFBS_None, // BLT = 466
17133
0
    CEFBS_None, // BLTU = 467
17134
0
    CEFBS_None, // BNE = 468
17135
0
    CEFBS_None, // BNEZ = 469
17136
0
    CEFBS_None, // BREAK = 470
17137
0
    CEFBS_IsLA64, // BSTRINS_D = 471
17138
0
    CEFBS_None, // BSTRINS_W = 472
17139
0
    CEFBS_IsLA64, // BSTRPICK_D = 473
17140
0
    CEFBS_None, // BSTRPICK_W = 474
17141
0
    CEFBS_IsLA64, // BYTEPICK_D = 475
17142
0
    CEFBS_None, // BYTEPICK_W = 476
17143
0
    CEFBS_None, // CACOP = 477
17144
0
    CEFBS_IsLA64, // CLO_D = 478
17145
0
    CEFBS_None, // CLO_W = 479
17146
0
    CEFBS_IsLA64, // CLZ_D = 480
17147
0
    CEFBS_None, // CLZ_W = 481
17148
0
    CEFBS_None, // CPUCFG = 482
17149
0
    CEFBS_IsLA64, // CRCC_W_B_W = 483
17150
0
    CEFBS_IsLA64, // CRCC_W_D_W = 484
17151
0
    CEFBS_IsLA64, // CRCC_W_H_W = 485
17152
0
    CEFBS_IsLA64, // CRCC_W_W_W = 486
17153
0
    CEFBS_IsLA64, // CRC_W_B_W = 487
17154
0
    CEFBS_IsLA64, // CRC_W_D_W = 488
17155
0
    CEFBS_IsLA64, // CRC_W_H_W = 489
17156
0
    CEFBS_IsLA64, // CRC_W_W_W = 490
17157
0
    CEFBS_None, // CSRRD = 491
17158
0
    CEFBS_None, // CSRWR = 492
17159
0
    CEFBS_None, // CSRXCHG = 493
17160
0
    CEFBS_IsLA64, // CTO_D = 494
17161
0
    CEFBS_None, // CTO_W = 495
17162
0
    CEFBS_IsLA64, // CTZ_D = 496
17163
0
    CEFBS_None, // CTZ_W = 497
17164
0
    CEFBS_None, // DBAR = 498
17165
0
    CEFBS_None, // DBCL = 499
17166
0
    CEFBS_IsLA64, // DIV_D = 500
17167
0
    CEFBS_IsLA64, // DIV_DU = 501
17168
0
    CEFBS_None, // DIV_W = 502
17169
0
    CEFBS_None, // DIV_WU = 503
17170
0
    CEFBS_None, // ERTN = 504
17171
0
    CEFBS_None, // EXT_W_B = 505
17172
0
    CEFBS_None, // EXT_W_H = 506
17173
0
    CEFBS_None, // FABS_D = 507
17174
0
    CEFBS_None, // FABS_S = 508
17175
0
    CEFBS_None, // FADD_D = 509
17176
0
    CEFBS_None, // FADD_S = 510
17177
0
    CEFBS_None, // FCLASS_D = 511
17178
0
    CEFBS_None, // FCLASS_S = 512
17179
0
    CEFBS_None, // FCMP_CAF_D = 513
17180
0
    CEFBS_None, // FCMP_CAF_S = 514
17181
0
    CEFBS_None, // FCMP_CEQ_D = 515
17182
0
    CEFBS_None, // FCMP_CEQ_S = 516
17183
0
    CEFBS_None, // FCMP_CLE_D = 517
17184
0
    CEFBS_None, // FCMP_CLE_S = 518
17185
0
    CEFBS_None, // FCMP_CLT_D = 519
17186
0
    CEFBS_None, // FCMP_CLT_S = 520
17187
0
    CEFBS_None, // FCMP_CNE_D = 521
17188
0
    CEFBS_None, // FCMP_CNE_S = 522
17189
0
    CEFBS_None, // FCMP_COR_D = 523
17190
0
    CEFBS_None, // FCMP_COR_S = 524
17191
0
    CEFBS_None, // FCMP_CUEQ_D = 525
17192
0
    CEFBS_None, // FCMP_CUEQ_S = 526
17193
0
    CEFBS_None, // FCMP_CULE_D = 527
17194
0
    CEFBS_None, // FCMP_CULE_S = 528
17195
0
    CEFBS_None, // FCMP_CULT_D = 529
17196
0
    CEFBS_None, // FCMP_CULT_S = 530
17197
0
    CEFBS_None, // FCMP_CUNE_D = 531
17198
0
    CEFBS_None, // FCMP_CUNE_S = 532
17199
0
    CEFBS_None, // FCMP_CUN_D = 533
17200
0
    CEFBS_None, // FCMP_CUN_S = 534
17201
0
    CEFBS_None, // FCMP_SAF_D = 535
17202
0
    CEFBS_None, // FCMP_SAF_S = 536
17203
0
    CEFBS_None, // FCMP_SEQ_D = 537
17204
0
    CEFBS_None, // FCMP_SEQ_S = 538
17205
0
    CEFBS_None, // FCMP_SLE_D = 539
17206
0
    CEFBS_None, // FCMP_SLE_S = 540
17207
0
    CEFBS_None, // FCMP_SLT_D = 541
17208
0
    CEFBS_None, // FCMP_SLT_S = 542
17209
0
    CEFBS_None, // FCMP_SNE_D = 543
17210
0
    CEFBS_None, // FCMP_SNE_S = 544
17211
0
    CEFBS_None, // FCMP_SOR_D = 545
17212
0
    CEFBS_None, // FCMP_SOR_S = 546
17213
0
    CEFBS_None, // FCMP_SUEQ_D = 547
17214
0
    CEFBS_None, // FCMP_SUEQ_S = 548
17215
0
    CEFBS_None, // FCMP_SULE_D = 549
17216
0
    CEFBS_None, // FCMP_SULE_S = 550
17217
0
    CEFBS_None, // FCMP_SULT_D = 551
17218
0
    CEFBS_None, // FCMP_SULT_S = 552
17219
0
    CEFBS_None, // FCMP_SUNE_D = 553
17220
0
    CEFBS_None, // FCMP_SUNE_S = 554
17221
0
    CEFBS_None, // FCMP_SUN_D = 555
17222
0
    CEFBS_None, // FCMP_SUN_S = 556
17223
0
    CEFBS_None, // FCOPYSIGN_D = 557
17224
0
    CEFBS_None, // FCOPYSIGN_S = 558
17225
0
    CEFBS_None, // FCVT_D_LD = 559
17226
0
    CEFBS_None, // FCVT_D_S = 560
17227
0
    CEFBS_None, // FCVT_LD_D = 561
17228
0
    CEFBS_None, // FCVT_S_D = 562
17229
0
    CEFBS_None, // FCVT_UD_D = 563
17230
0
    CEFBS_None, // FDIV_D = 564
17231
0
    CEFBS_None, // FDIV_S = 565
17232
0
    CEFBS_None, // FFINT_D_L = 566
17233
0
    CEFBS_None, // FFINT_D_W = 567
17234
0
    CEFBS_None, // FFINT_S_L = 568
17235
0
    CEFBS_None, // FFINT_S_W = 569
17236
0
    CEFBS_None, // FLDGT_D = 570
17237
0
    CEFBS_None, // FLDGT_S = 571
17238
0
    CEFBS_None, // FLDLE_D = 572
17239
0
    CEFBS_None, // FLDLE_S = 573
17240
0
    CEFBS_None, // FLDX_D = 574
17241
0
    CEFBS_None, // FLDX_S = 575
17242
0
    CEFBS_None, // FLD_D = 576
17243
0
    CEFBS_None, // FLD_S = 577
17244
0
    CEFBS_None, // FLOGB_D = 578
17245
0
    CEFBS_None, // FLOGB_S = 579
17246
0
    CEFBS_None, // FMADD_D = 580
17247
0
    CEFBS_None, // FMADD_S = 581
17248
0
    CEFBS_None, // FMAXA_D = 582
17249
0
    CEFBS_None, // FMAXA_S = 583
17250
0
    CEFBS_None, // FMAX_D = 584
17251
0
    CEFBS_None, // FMAX_S = 585
17252
0
    CEFBS_None, // FMINA_D = 586
17253
0
    CEFBS_None, // FMINA_S = 587
17254
0
    CEFBS_None, // FMIN_D = 588
17255
0
    CEFBS_None, // FMIN_S = 589
17256
0
    CEFBS_None, // FMOV_D = 590
17257
0
    CEFBS_None, // FMOV_S = 591
17258
0
    CEFBS_None, // FMSUB_D = 592
17259
0
    CEFBS_None, // FMSUB_S = 593
17260
0
    CEFBS_None, // FMUL_D = 594
17261
0
    CEFBS_None, // FMUL_S = 595
17262
0
    CEFBS_None, // FNEG_D = 596
17263
0
    CEFBS_None, // FNEG_S = 597
17264
0
    CEFBS_None, // FNMADD_D = 598
17265
0
    CEFBS_None, // FNMADD_S = 599
17266
0
    CEFBS_None, // FNMSUB_D = 600
17267
0
    CEFBS_None, // FNMSUB_S = 601
17268
0
    CEFBS_None, // FRECIPE_D = 602
17269
0
    CEFBS_None, // FRECIPE_S = 603
17270
0
    CEFBS_None, // FRECIP_D = 604
17271
0
    CEFBS_None, // FRECIP_S = 605
17272
0
    CEFBS_None, // FRINT_D = 606
17273
0
    CEFBS_None, // FRINT_S = 607
17274
0
    CEFBS_None, // FRSQRTE_D = 608
17275
0
    CEFBS_None, // FRSQRTE_S = 609
17276
0
    CEFBS_None, // FRSQRT_D = 610
17277
0
    CEFBS_None, // FRSQRT_S = 611
17278
0
    CEFBS_None, // FSCALEB_D = 612
17279
0
    CEFBS_None, // FSCALEB_S = 613
17280
0
    CEFBS_None, // FSEL_xD = 614
17281
0
    CEFBS_None, // FSEL_xS = 615
17282
0
    CEFBS_None, // FSQRT_D = 616
17283
0
    CEFBS_None, // FSQRT_S = 617
17284
0
    CEFBS_None, // FSTGT_D = 618
17285
0
    CEFBS_None, // FSTGT_S = 619
17286
0
    CEFBS_None, // FSTLE_D = 620
17287
0
    CEFBS_None, // FSTLE_S = 621
17288
0
    CEFBS_None, // FSTX_D = 622
17289
0
    CEFBS_None, // FSTX_S = 623
17290
0
    CEFBS_None, // FST_D = 624
17291
0
    CEFBS_None, // FST_S = 625
17292
0
    CEFBS_None, // FSUB_D = 626
17293
0
    CEFBS_None, // FSUB_S = 627
17294
0
    CEFBS_None, // FTINTRM_L_D = 628
17295
0
    CEFBS_None, // FTINTRM_L_S = 629
17296
0
    CEFBS_None, // FTINTRM_W_D = 630
17297
0
    CEFBS_None, // FTINTRM_W_S = 631
17298
0
    CEFBS_None, // FTINTRNE_L_D = 632
17299
0
    CEFBS_None, // FTINTRNE_L_S = 633
17300
0
    CEFBS_None, // FTINTRNE_W_D = 634
17301
0
    CEFBS_None, // FTINTRNE_W_S = 635
17302
0
    CEFBS_None, // FTINTRP_L_D = 636
17303
0
    CEFBS_None, // FTINTRP_L_S = 637
17304
0
    CEFBS_None, // FTINTRP_W_D = 638
17305
0
    CEFBS_None, // FTINTRP_W_S = 639
17306
0
    CEFBS_None, // FTINTRZ_L_D = 640
17307
0
    CEFBS_None, // FTINTRZ_L_S = 641
17308
0
    CEFBS_None, // FTINTRZ_W_D = 642
17309
0
    CEFBS_None, // FTINTRZ_W_S = 643
17310
0
    CEFBS_None, // FTINT_L_D = 644
17311
0
    CEFBS_None, // FTINT_L_S = 645
17312
0
    CEFBS_None, // FTINT_W_D = 646
17313
0
    CEFBS_None, // FTINT_W_S = 647
17314
0
    CEFBS_None, // GCSRRD = 648
17315
0
    CEFBS_None, // GCSRWR = 649
17316
0
    CEFBS_None, // GCSRXCHG = 650
17317
0
    CEFBS_None, // GTLBFLUSH = 651
17318
0
    CEFBS_None, // HVCL = 652
17319
0
    CEFBS_None, // IBAR = 653
17320
0
    CEFBS_None, // IDLE = 654
17321
0
    CEFBS_None, // INVTLB = 655
17322
0
    CEFBS_None, // IOCSRRD_B = 656
17323
0
    CEFBS_IsLA64, // IOCSRRD_D = 657
17324
0
    CEFBS_None, // IOCSRRD_H = 658
17325
0
    CEFBS_None, // IOCSRRD_W = 659
17326
0
    CEFBS_None, // IOCSRWR_B = 660
17327
0
    CEFBS_IsLA64, // IOCSRWR_D = 661
17328
0
    CEFBS_None, // IOCSRWR_H = 662
17329
0
    CEFBS_None, // IOCSRWR_W = 663
17330
0
    CEFBS_None, // JIRL = 664
17331
0
    CEFBS_None, // JISCR0 = 665
17332
0
    CEFBS_None, // JISCR1 = 666
17333
0
    CEFBS_None, // LDDIR = 667
17334
0
    CEFBS_IsLA64, // LDGT_B = 668
17335
0
    CEFBS_IsLA64, // LDGT_D = 669
17336
0
    CEFBS_IsLA64, // LDGT_H = 670
17337
0
    CEFBS_IsLA64, // LDGT_W = 671
17338
0
    CEFBS_IsLA64, // LDLE_B = 672
17339
0
    CEFBS_IsLA64, // LDLE_D = 673
17340
0
    CEFBS_IsLA64, // LDLE_H = 674
17341
0
    CEFBS_IsLA64, // LDLE_W = 675
17342
0
    CEFBS_IsLA64, // LDL_D = 676
17343
0
    CEFBS_None, // LDL_W = 677
17344
0
    CEFBS_None, // LDPTE = 678
17345
0
    CEFBS_IsLA64, // LDPTR_D = 679
17346
0
    CEFBS_IsLA64, // LDPTR_W = 680
17347
0
    CEFBS_IsLA64, // LDR_D = 681
17348
0
    CEFBS_None, // LDR_W = 682
17349
0
    CEFBS_IsLA64, // LDX_B = 683
17350
0
    CEFBS_IsLA64, // LDX_BU = 684
17351
0
    CEFBS_IsLA64, // LDX_D = 685
17352
0
    CEFBS_IsLA64, // LDX_H = 686
17353
0
    CEFBS_IsLA64, // LDX_HU = 687
17354
0
    CEFBS_IsLA64, // LDX_W = 688
17355
0
    CEFBS_IsLA64, // LDX_WU = 689
17356
0
    CEFBS_None, // LD_B = 690
17357
0
    CEFBS_None, // LD_BU = 691
17358
0
    CEFBS_IsLA64, // LD_D = 692
17359
0
    CEFBS_None, // LD_H = 693
17360
0
    CEFBS_None, // LD_HU = 694
17361
0
    CEFBS_None, // LD_W = 695
17362
0
    CEFBS_IsLA64, // LD_WU = 696
17363
0
    CEFBS_IsLA64, // LLACQ_D = 697
17364
0
    CEFBS_None, // LLACQ_W = 698
17365
0
    CEFBS_IsLA64, // LL_D = 699
17366
0
    CEFBS_None, // LL_W = 700
17367
0
    CEFBS_None, // LU12I_W = 701
17368
0
    CEFBS_IsLA64, // LU32I_D = 702
17369
0
    CEFBS_IsLA64, // LU52I_D = 703
17370
0
    CEFBS_None, // MASKEQZ = 704
17371
0
    CEFBS_None, // MASKNEZ = 705
17372
0
    CEFBS_IsLA64, // MOD_D = 706
17373
0
    CEFBS_IsLA64, // MOD_DU = 707
17374
0
    CEFBS_None, // MOD_W = 708
17375
0
    CEFBS_None, // MOD_WU = 709
17376
0
    CEFBS_None, // MOVCF2FR_xS = 710
17377
0
    CEFBS_None, // MOVCF2GR = 711
17378
0
    CEFBS_None, // MOVFCSR2GR = 712
17379
0
    CEFBS_None, // MOVFR2CF_xS = 713
17380
0
    CEFBS_IsLA64, // MOVFR2GR_D = 714
17381
0
    CEFBS_None, // MOVFR2GR_S = 715
17382
0
    CEFBS_None, // MOVFR2GR_S_64 = 716
17383
0
    CEFBS_None, // MOVFRH2GR_S = 717
17384
0
    CEFBS_None, // MOVGR2CF = 718
17385
0
    CEFBS_None, // MOVGR2FCSR = 719
17386
0
    CEFBS_None, // MOVGR2FRH_W = 720
17387
0
    CEFBS_IsLA64, // MOVGR2FR_D = 721
17388
0
    CEFBS_None, // MOVGR2FR_W = 722
17389
0
    CEFBS_IsLA32, // MOVGR2FR_W_64 = 723
17390
0
    CEFBS_None, // MOVGR2SCR = 724
17391
0
    CEFBS_None, // MOVSCR2GR = 725
17392
0
    CEFBS_IsLA64, // MULH_D = 726
17393
0
    CEFBS_IsLA64, // MULH_DU = 727
17394
0
    CEFBS_None, // MULH_W = 728
17395
0
    CEFBS_None, // MULH_WU = 729
17396
0
    CEFBS_IsLA64, // MULW_D_W = 730
17397
0
    CEFBS_IsLA64, // MULW_D_WU = 731
17398
0
    CEFBS_IsLA64, // MUL_D = 732
17399
0
    CEFBS_None, // MUL_W = 733
17400
0
    CEFBS_None, // NOR = 734
17401
0
    CEFBS_None, // OR = 735
17402
0
    CEFBS_None, // ORI = 736
17403
0
    CEFBS_None, // ORN = 737
17404
0
    CEFBS_None, // PCADDI = 738
17405
0
    CEFBS_None, // PCADDU12I = 739
17406
0
    CEFBS_IsLA64, // PCADDU18I = 740
17407
0
    CEFBS_None, // PCALAU12I = 741
17408
0
    CEFBS_None, // PRELD = 742
17409
0
    CEFBS_IsLA64, // PRELDX = 743
17410
0
    CEFBS_None, // RCRI_B = 744
17411
0
    CEFBS_IsLA64, // RCRI_D = 745
17412
0
    CEFBS_None, // RCRI_H = 746
17413
0
    CEFBS_None, // RCRI_W = 747
17414
0
    CEFBS_None, // RCR_B = 748
17415
0
    CEFBS_IsLA64, // RCR_D = 749
17416
0
    CEFBS_None, // RCR_H = 750
17417
0
    CEFBS_None, // RCR_W = 751
17418
0
    CEFBS_None, // RDTIMEH_W = 752
17419
0
    CEFBS_None, // RDTIMEL_W = 753
17420
0
    CEFBS_IsLA64, // RDTIME_D = 754
17421
0
    CEFBS_None, // REVB_2H = 755
17422
0
    CEFBS_IsLA64, // REVB_2W = 756
17423
0
    CEFBS_IsLA64, // REVB_4H = 757
17424
0
    CEFBS_IsLA64, // REVB_D = 758
17425
0
    CEFBS_IsLA64, // REVH_2W = 759
17426
0
    CEFBS_IsLA64, // REVH_D = 760
17427
0
    CEFBS_None, // ROTRI_B = 761
17428
0
    CEFBS_IsLA64, // ROTRI_D = 762
17429
0
    CEFBS_None, // ROTRI_H = 763
17430
0
    CEFBS_None, // ROTRI_W = 764
17431
0
    CEFBS_None, // ROTR_B = 765
17432
0
    CEFBS_IsLA64, // ROTR_D = 766
17433
0
    CEFBS_None, // ROTR_H = 767
17434
0
    CEFBS_None, // ROTR_W = 768
17435
0
    CEFBS_None, // SBC_B = 769
17436
0
    CEFBS_IsLA64, // SBC_D = 770
17437
0
    CEFBS_None, // SBC_H = 771
17438
0
    CEFBS_None, // SBC_W = 772
17439
0
    CEFBS_IsLA64, // SCREL_D = 773
17440
0
    CEFBS_None, // SCREL_W = 774
17441
0
    CEFBS_IsLA64, // SC_D = 775
17442
0
    CEFBS_IsLA64, // SC_Q = 776
17443
0
    CEFBS_None, // SC_W = 777
17444
0
    CEFBS_None, // SETARMJ = 778
17445
0
    CEFBS_None, // SETX86J = 779
17446
0
    CEFBS_None, // SETX86LOOPE = 780
17447
0
    CEFBS_None, // SETX86LOOPNE = 781
17448
0
    CEFBS_None, // SET_CFR_FALSE = 782
17449
0
    CEFBS_None, // SET_CFR_TRUE = 783
17450
0
    CEFBS_IsLA64, // SLLI_D = 784
17451
0
    CEFBS_None, // SLLI_W = 785
17452
0
    CEFBS_IsLA64, // SLL_D = 786
17453
0
    CEFBS_None, // SLL_W = 787
17454
0
    CEFBS_None, // SLT = 788
17455
0
    CEFBS_None, // SLTI = 789
17456
0
    CEFBS_None, // SLTU = 790
17457
0
    CEFBS_None, // SLTUI = 791
17458
0
    CEFBS_IsLA64, // SRAI_D = 792
17459
0
    CEFBS_None, // SRAI_W = 793
17460
0
    CEFBS_IsLA64, // SRA_D = 794
17461
0
    CEFBS_None, // SRA_W = 795
17462
0
    CEFBS_IsLA64, // SRLI_D = 796
17463
0
    CEFBS_None, // SRLI_W = 797
17464
0
    CEFBS_IsLA64, // SRL_D = 798
17465
0
    CEFBS_None, // SRL_W = 799
17466
0
    CEFBS_IsLA64, // STGT_B = 800
17467
0
    CEFBS_IsLA64, // STGT_D = 801
17468
0
    CEFBS_IsLA64, // STGT_H = 802
17469
0
    CEFBS_IsLA64, // STGT_W = 803
17470
0
    CEFBS_IsLA64, // STLE_B = 804
17471
0
    CEFBS_IsLA64, // STLE_D = 805
17472
0
    CEFBS_IsLA64, // STLE_H = 806
17473
0
    CEFBS_IsLA64, // STLE_W = 807
17474
0
    CEFBS_IsLA64, // STL_D = 808
17475
0
    CEFBS_None, // STL_W = 809
17476
0
    CEFBS_IsLA64, // STPTR_D = 810
17477
0
    CEFBS_IsLA64, // STPTR_W = 811
17478
0
    CEFBS_IsLA64, // STR_D = 812
17479
0
    CEFBS_None, // STR_W = 813
17480
0
    CEFBS_IsLA64, // STX_B = 814
17481
0
    CEFBS_IsLA64, // STX_D = 815
17482
0
    CEFBS_IsLA64, // STX_H = 816
17483
0
    CEFBS_IsLA64, // STX_W = 817
17484
0
    CEFBS_None, // ST_B = 818
17485
0
    CEFBS_IsLA64, // ST_D = 819
17486
0
    CEFBS_None, // ST_H = 820
17487
0
    CEFBS_None, // ST_W = 821
17488
0
    CEFBS_IsLA64, // SUB_D = 822
17489
0
    CEFBS_None, // SUB_W = 823
17490
0
    CEFBS_None, // SYSCALL = 824
17491
0
    CEFBS_None, // TLBCLR = 825
17492
0
    CEFBS_None, // TLBFILL = 826
17493
0
    CEFBS_None, // TLBFLUSH = 827
17494
0
    CEFBS_None, // TLBRD = 828
17495
0
    CEFBS_None, // TLBSRCH = 829
17496
0
    CEFBS_None, // TLBWR = 830
17497
0
    CEFBS_None, // VABSD_B = 831
17498
0
    CEFBS_None, // VABSD_BU = 832
17499
0
    CEFBS_None, // VABSD_D = 833
17500
0
    CEFBS_None, // VABSD_DU = 834
17501
0
    CEFBS_None, // VABSD_H = 835
17502
0
    CEFBS_None, // VABSD_HU = 836
17503
0
    CEFBS_None, // VABSD_W = 837
17504
0
    CEFBS_None, // VABSD_WU = 838
17505
0
    CEFBS_None, // VADDA_B = 839
17506
0
    CEFBS_None, // VADDA_D = 840
17507
0
    CEFBS_None, // VADDA_H = 841
17508
0
    CEFBS_None, // VADDA_W = 842
17509
0
    CEFBS_None, // VADDI_BU = 843
17510
0
    CEFBS_None, // VADDI_DU = 844
17511
0
    CEFBS_None, // VADDI_HU = 845
17512
0
    CEFBS_None, // VADDI_WU = 846
17513
0
    CEFBS_None, // VADDWEV_D_W = 847
17514
0
    CEFBS_None, // VADDWEV_D_WU = 848
17515
0
    CEFBS_None, // VADDWEV_D_WU_W = 849
17516
0
    CEFBS_None, // VADDWEV_H_B = 850
17517
0
    CEFBS_None, // VADDWEV_H_BU = 851
17518
0
    CEFBS_None, // VADDWEV_H_BU_B = 852
17519
0
    CEFBS_None, // VADDWEV_Q_D = 853
17520
0
    CEFBS_None, // VADDWEV_Q_DU = 854
17521
0
    CEFBS_None, // VADDWEV_Q_DU_D = 855
17522
0
    CEFBS_None, // VADDWEV_W_H = 856
17523
0
    CEFBS_None, // VADDWEV_W_HU = 857
17524
0
    CEFBS_None, // VADDWEV_W_HU_H = 858
17525
0
    CEFBS_None, // VADDWOD_D_W = 859
17526
0
    CEFBS_None, // VADDWOD_D_WU = 860
17527
0
    CEFBS_None, // VADDWOD_D_WU_W = 861
17528
0
    CEFBS_None, // VADDWOD_H_B = 862
17529
0
    CEFBS_None, // VADDWOD_H_BU = 863
17530
0
    CEFBS_None, // VADDWOD_H_BU_B = 864
17531
0
    CEFBS_None, // VADDWOD_Q_D = 865
17532
0
    CEFBS_None, // VADDWOD_Q_DU = 866
17533
0
    CEFBS_None, // VADDWOD_Q_DU_D = 867
17534
0
    CEFBS_None, // VADDWOD_W_H = 868
17535
0
    CEFBS_None, // VADDWOD_W_HU = 869
17536
0
    CEFBS_None, // VADDWOD_W_HU_H = 870
17537
0
    CEFBS_None, // VADD_B = 871
17538
0
    CEFBS_None, // VADD_D = 872
17539
0
    CEFBS_None, // VADD_H = 873
17540
0
    CEFBS_None, // VADD_Q = 874
17541
0
    CEFBS_None, // VADD_W = 875
17542
0
    CEFBS_None, // VANDI_B = 876
17543
0
    CEFBS_None, // VANDN_V = 877
17544
0
    CEFBS_None, // VAND_V = 878
17545
0
    CEFBS_None, // VAVGR_B = 879
17546
0
    CEFBS_None, // VAVGR_BU = 880
17547
0
    CEFBS_None, // VAVGR_D = 881
17548
0
    CEFBS_None, // VAVGR_DU = 882
17549
0
    CEFBS_None, // VAVGR_H = 883
17550
0
    CEFBS_None, // VAVGR_HU = 884
17551
0
    CEFBS_None, // VAVGR_W = 885
17552
0
    CEFBS_None, // VAVGR_WU = 886
17553
0
    CEFBS_None, // VAVG_B = 887
17554
0
    CEFBS_None, // VAVG_BU = 888
17555
0
    CEFBS_None, // VAVG_D = 889
17556
0
    CEFBS_None, // VAVG_DU = 890
17557
0
    CEFBS_None, // VAVG_H = 891
17558
0
    CEFBS_None, // VAVG_HU = 892
17559
0
    CEFBS_None, // VAVG_W = 893
17560
0
    CEFBS_None, // VAVG_WU = 894
17561
0
    CEFBS_None, // VBITCLRI_B = 895
17562
0
    CEFBS_None, // VBITCLRI_D = 896
17563
0
    CEFBS_None, // VBITCLRI_H = 897
17564
0
    CEFBS_None, // VBITCLRI_W = 898
17565
0
    CEFBS_None, // VBITCLR_B = 899
17566
0
    CEFBS_None, // VBITCLR_D = 900
17567
0
    CEFBS_None, // VBITCLR_H = 901
17568
0
    CEFBS_None, // VBITCLR_W = 902
17569
0
    CEFBS_None, // VBITREVI_B = 903
17570
0
    CEFBS_None, // VBITREVI_D = 904
17571
0
    CEFBS_None, // VBITREVI_H = 905
17572
0
    CEFBS_None, // VBITREVI_W = 906
17573
0
    CEFBS_None, // VBITREV_B = 907
17574
0
    CEFBS_None, // VBITREV_D = 908
17575
0
    CEFBS_None, // VBITREV_H = 909
17576
0
    CEFBS_None, // VBITREV_W = 910
17577
0
    CEFBS_None, // VBITSELI_B = 911
17578
0
    CEFBS_None, // VBITSEL_V = 912
17579
0
    CEFBS_None, // VBITSETI_B = 913
17580
0
    CEFBS_None, // VBITSETI_D = 914
17581
0
    CEFBS_None, // VBITSETI_H = 915
17582
0
    CEFBS_None, // VBITSETI_W = 916
17583
0
    CEFBS_None, // VBITSET_B = 917
17584
0
    CEFBS_None, // VBITSET_D = 918
17585
0
    CEFBS_None, // VBITSET_H = 919
17586
0
    CEFBS_None, // VBITSET_W = 920
17587
0
    CEFBS_None, // VBSLL_V = 921
17588
0
    CEFBS_None, // VBSRL_V = 922
17589
0
    CEFBS_None, // VCLO_B = 923
17590
0
    CEFBS_None, // VCLO_D = 924
17591
0
    CEFBS_None, // VCLO_H = 925
17592
0
    CEFBS_None, // VCLO_W = 926
17593
0
    CEFBS_None, // VCLZ_B = 927
17594
0
    CEFBS_None, // VCLZ_D = 928
17595
0
    CEFBS_None, // VCLZ_H = 929
17596
0
    CEFBS_None, // VCLZ_W = 930
17597
0
    CEFBS_None, // VDIV_B = 931
17598
0
    CEFBS_None, // VDIV_BU = 932
17599
0
    CEFBS_None, // VDIV_D = 933
17600
0
    CEFBS_None, // VDIV_DU = 934
17601
0
    CEFBS_None, // VDIV_H = 935
17602
0
    CEFBS_None, // VDIV_HU = 936
17603
0
    CEFBS_None, // VDIV_W = 937
17604
0
    CEFBS_None, // VDIV_WU = 938
17605
0
    CEFBS_None, // VEXT2XV_DU_BU = 939
17606
0
    CEFBS_None, // VEXT2XV_DU_HU = 940
17607
0
    CEFBS_None, // VEXT2XV_DU_WU = 941
17608
0
    CEFBS_None, // VEXT2XV_D_B = 942
17609
0
    CEFBS_None, // VEXT2XV_D_H = 943
17610
0
    CEFBS_None, // VEXT2XV_D_W = 944
17611
0
    CEFBS_None, // VEXT2XV_HU_BU = 945
17612
0
    CEFBS_None, // VEXT2XV_H_B = 946
17613
0
    CEFBS_None, // VEXT2XV_WU_BU = 947
17614
0
    CEFBS_None, // VEXT2XV_WU_HU = 948
17615
0
    CEFBS_None, // VEXT2XV_W_B = 949
17616
0
    CEFBS_None, // VEXT2XV_W_H = 950
17617
0
    CEFBS_None, // VEXTH_DU_WU = 951
17618
0
    CEFBS_None, // VEXTH_D_W = 952
17619
0
    CEFBS_None, // VEXTH_HU_BU = 953
17620
0
    CEFBS_None, // VEXTH_H_B = 954
17621
0
    CEFBS_None, // VEXTH_QU_DU = 955
17622
0
    CEFBS_None, // VEXTH_Q_D = 956
17623
0
    CEFBS_None, // VEXTH_WU_HU = 957
17624
0
    CEFBS_None, // VEXTH_W_H = 958
17625
0
    CEFBS_None, // VEXTL_QU_DU = 959
17626
0
    CEFBS_None, // VEXTL_Q_D = 960
17627
0
    CEFBS_None, // VEXTRINS_B = 961
17628
0
    CEFBS_None, // VEXTRINS_D = 962
17629
0
    CEFBS_None, // VEXTRINS_H = 963
17630
0
    CEFBS_None, // VEXTRINS_W = 964
17631
0
    CEFBS_None, // VFADD_D = 965
17632
0
    CEFBS_None, // VFADD_S = 966
17633
0
    CEFBS_None, // VFCLASS_D = 967
17634
0
    CEFBS_None, // VFCLASS_S = 968
17635
0
    CEFBS_None, // VFCMP_CAF_D = 969
17636
0
    CEFBS_None, // VFCMP_CAF_S = 970
17637
0
    CEFBS_None, // VFCMP_CEQ_D = 971
17638
0
    CEFBS_None, // VFCMP_CEQ_S = 972
17639
0
    CEFBS_None, // VFCMP_CLE_D = 973
17640
0
    CEFBS_None, // VFCMP_CLE_S = 974
17641
0
    CEFBS_None, // VFCMP_CLT_D = 975
17642
0
    CEFBS_None, // VFCMP_CLT_S = 976
17643
0
    CEFBS_None, // VFCMP_CNE_D = 977
17644
0
    CEFBS_None, // VFCMP_CNE_S = 978
17645
0
    CEFBS_None, // VFCMP_COR_D = 979
17646
0
    CEFBS_None, // VFCMP_COR_S = 980
17647
0
    CEFBS_None, // VFCMP_CUEQ_D = 981
17648
0
    CEFBS_None, // VFCMP_CUEQ_S = 982
17649
0
    CEFBS_None, // VFCMP_CULE_D = 983
17650
0
    CEFBS_None, // VFCMP_CULE_S = 984
17651
0
    CEFBS_None, // VFCMP_CULT_D = 985
17652
0
    CEFBS_None, // VFCMP_CULT_S = 986
17653
0
    CEFBS_None, // VFCMP_CUNE_D = 987
17654
0
    CEFBS_None, // VFCMP_CUNE_S = 988
17655
0
    CEFBS_None, // VFCMP_CUN_D = 989
17656
0
    CEFBS_None, // VFCMP_CUN_S = 990
17657
0
    CEFBS_None, // VFCMP_SAF_D = 991
17658
0
    CEFBS_None, // VFCMP_SAF_S = 992
17659
0
    CEFBS_None, // VFCMP_SEQ_D = 993
17660
0
    CEFBS_None, // VFCMP_SEQ_S = 994
17661
0
    CEFBS_None, // VFCMP_SLE_D = 995
17662
0
    CEFBS_None, // VFCMP_SLE_S = 996
17663
0
    CEFBS_None, // VFCMP_SLT_D = 997
17664
0
    CEFBS_None, // VFCMP_SLT_S = 998
17665
0
    CEFBS_None, // VFCMP_SNE_D = 999
17666
0
    CEFBS_None, // VFCMP_SNE_S = 1000
17667
0
    CEFBS_None, // VFCMP_SOR_D = 1001
17668
0
    CEFBS_None, // VFCMP_SOR_S = 1002
17669
0
    CEFBS_None, // VFCMP_SUEQ_D = 1003
17670
0
    CEFBS_None, // VFCMP_SUEQ_S = 1004
17671
0
    CEFBS_None, // VFCMP_SULE_D = 1005
17672
0
    CEFBS_None, // VFCMP_SULE_S = 1006
17673
0
    CEFBS_None, // VFCMP_SULT_D = 1007
17674
0
    CEFBS_None, // VFCMP_SULT_S = 1008
17675
0
    CEFBS_None, // VFCMP_SUNE_D = 1009
17676
0
    CEFBS_None, // VFCMP_SUNE_S = 1010
17677
0
    CEFBS_None, // VFCMP_SUN_D = 1011
17678
0
    CEFBS_None, // VFCMP_SUN_S = 1012
17679
0
    CEFBS_None, // VFCVTH_D_S = 1013
17680
0
    CEFBS_None, // VFCVTH_S_H = 1014
17681
0
    CEFBS_None, // VFCVTL_D_S = 1015
17682
0
    CEFBS_None, // VFCVTL_S_H = 1016
17683
0
    CEFBS_None, // VFCVT_H_S = 1017
17684
0
    CEFBS_None, // VFCVT_S_D = 1018
17685
0
    CEFBS_None, // VFDIV_D = 1019
17686
0
    CEFBS_None, // VFDIV_S = 1020
17687
0
    CEFBS_None, // VFFINTH_D_W = 1021
17688
0
    CEFBS_None, // VFFINTL_D_W = 1022
17689
0
    CEFBS_None, // VFFINT_D_L = 1023
17690
0
    CEFBS_None, // VFFINT_D_LU = 1024
17691
0
    CEFBS_None, // VFFINT_S_L = 1025
17692
0
    CEFBS_None, // VFFINT_S_W = 1026
17693
0
    CEFBS_None, // VFFINT_S_WU = 1027
17694
0
    CEFBS_None, // VFLOGB_D = 1028
17695
0
    CEFBS_None, // VFLOGB_S = 1029
17696
0
    CEFBS_None, // VFMADD_D = 1030
17697
0
    CEFBS_None, // VFMADD_S = 1031
17698
0
    CEFBS_None, // VFMAXA_D = 1032
17699
0
    CEFBS_None, // VFMAXA_S = 1033
17700
0
    CEFBS_None, // VFMAX_D = 1034
17701
0
    CEFBS_None, // VFMAX_S = 1035
17702
0
    CEFBS_None, // VFMINA_D = 1036
17703
0
    CEFBS_None, // VFMINA_S = 1037
17704
0
    CEFBS_None, // VFMIN_D = 1038
17705
0
    CEFBS_None, // VFMIN_S = 1039
17706
0
    CEFBS_None, // VFMSUB_D = 1040
17707
0
    CEFBS_None, // VFMSUB_S = 1041
17708
0
    CEFBS_None, // VFMUL_D = 1042
17709
0
    CEFBS_None, // VFMUL_S = 1043
17710
0
    CEFBS_None, // VFNMADD_D = 1044
17711
0
    CEFBS_None, // VFNMADD_S = 1045
17712
0
    CEFBS_None, // VFNMSUB_D = 1046
17713
0
    CEFBS_None, // VFNMSUB_S = 1047
17714
0
    CEFBS_None, // VFRECIPE_D = 1048
17715
0
    CEFBS_None, // VFRECIPE_S = 1049
17716
0
    CEFBS_None, // VFRECIP_D = 1050
17717
0
    CEFBS_None, // VFRECIP_S = 1051
17718
0
    CEFBS_None, // VFRINTRM_D = 1052
17719
0
    CEFBS_None, // VFRINTRM_S = 1053
17720
0
    CEFBS_None, // VFRINTRNE_D = 1054
17721
0
    CEFBS_None, // VFRINTRNE_S = 1055
17722
0
    CEFBS_None, // VFRINTRP_D = 1056
17723
0
    CEFBS_None, // VFRINTRP_S = 1057
17724
0
    CEFBS_None, // VFRINTRZ_D = 1058
17725
0
    CEFBS_None, // VFRINTRZ_S = 1059
17726
0
    CEFBS_None, // VFRINT_D = 1060
17727
0
    CEFBS_None, // VFRINT_S = 1061
17728
0
    CEFBS_None, // VFRSQRTE_D = 1062
17729
0
    CEFBS_None, // VFRSQRTE_S = 1063
17730
0
    CEFBS_None, // VFRSQRT_D = 1064
17731
0
    CEFBS_None, // VFRSQRT_S = 1065
17732
0
    CEFBS_None, // VFRSTPI_B = 1066
17733
0
    CEFBS_None, // VFRSTPI_H = 1067
17734
0
    CEFBS_None, // VFRSTP_B = 1068
17735
0
    CEFBS_None, // VFRSTP_H = 1069
17736
0
    CEFBS_None, // VFSQRT_D = 1070
17737
0
    CEFBS_None, // VFSQRT_S = 1071
17738
0
    CEFBS_None, // VFSUB_D = 1072
17739
0
    CEFBS_None, // VFSUB_S = 1073
17740
0
    CEFBS_None, // VFTINTH_L_S = 1074
17741
0
    CEFBS_None, // VFTINTL_L_S = 1075
17742
0
    CEFBS_None, // VFTINTRMH_L_S = 1076
17743
0
    CEFBS_None, // VFTINTRML_L_S = 1077
17744
0
    CEFBS_None, // VFTINTRM_L_D = 1078
17745
0
    CEFBS_None, // VFTINTRM_W_D = 1079
17746
0
    CEFBS_None, // VFTINTRM_W_S = 1080
17747
0
    CEFBS_None, // VFTINTRNEH_L_S = 1081
17748
0
    CEFBS_None, // VFTINTRNEL_L_S = 1082
17749
0
    CEFBS_None, // VFTINTRNE_L_D = 1083
17750
0
    CEFBS_None, // VFTINTRNE_W_D = 1084
17751
0
    CEFBS_None, // VFTINTRNE_W_S = 1085
17752
0
    CEFBS_None, // VFTINTRPH_L_S = 1086
17753
0
    CEFBS_None, // VFTINTRPL_L_S = 1087
17754
0
    CEFBS_None, // VFTINTRP_L_D = 1088
17755
0
    CEFBS_None, // VFTINTRP_W_D = 1089
17756
0
    CEFBS_None, // VFTINTRP_W_S = 1090
17757
0
    CEFBS_None, // VFTINTRZH_L_S = 1091
17758
0
    CEFBS_None, // VFTINTRZL_L_S = 1092
17759
0
    CEFBS_None, // VFTINTRZ_LU_D = 1093
17760
0
    CEFBS_None, // VFTINTRZ_L_D = 1094
17761
0
    CEFBS_None, // VFTINTRZ_WU_S = 1095
17762
0
    CEFBS_None, // VFTINTRZ_W_D = 1096
17763
0
    CEFBS_None, // VFTINTRZ_W_S = 1097
17764
0
    CEFBS_None, // VFTINT_LU_D = 1098
17765
0
    CEFBS_None, // VFTINT_L_D = 1099
17766
0
    CEFBS_None, // VFTINT_WU_S = 1100
17767
0
    CEFBS_None, // VFTINT_W_D = 1101
17768
0
    CEFBS_None, // VFTINT_W_S = 1102
17769
0
    CEFBS_None, // VHADDW_DU_WU = 1103
17770
0
    CEFBS_None, // VHADDW_D_W = 1104
17771
0
    CEFBS_None, // VHADDW_HU_BU = 1105
17772
0
    CEFBS_None, // VHADDW_H_B = 1106
17773
0
    CEFBS_None, // VHADDW_QU_DU = 1107
17774
0
    CEFBS_None, // VHADDW_Q_D = 1108
17775
0
    CEFBS_None, // VHADDW_WU_HU = 1109
17776
0
    CEFBS_None, // VHADDW_W_H = 1110
17777
0
    CEFBS_None, // VHSUBW_DU_WU = 1111
17778
0
    CEFBS_None, // VHSUBW_D_W = 1112
17779
0
    CEFBS_None, // VHSUBW_HU_BU = 1113
17780
0
    CEFBS_None, // VHSUBW_H_B = 1114
17781
0
    CEFBS_None, // VHSUBW_QU_DU = 1115
17782
0
    CEFBS_None, // VHSUBW_Q_D = 1116
17783
0
    CEFBS_None, // VHSUBW_WU_HU = 1117
17784
0
    CEFBS_None, // VHSUBW_W_H = 1118
17785
0
    CEFBS_None, // VILVH_B = 1119
17786
0
    CEFBS_None, // VILVH_D = 1120
17787
0
    CEFBS_None, // VILVH_H = 1121
17788
0
    CEFBS_None, // VILVH_W = 1122
17789
0
    CEFBS_None, // VILVL_B = 1123
17790
0
    CEFBS_None, // VILVL_D = 1124
17791
0
    CEFBS_None, // VILVL_H = 1125
17792
0
    CEFBS_None, // VILVL_W = 1126
17793
0
    CEFBS_None, // VINSGR2VR_B = 1127
17794
0
    CEFBS_None, // VINSGR2VR_D = 1128
17795
0
    CEFBS_None, // VINSGR2VR_H = 1129
17796
0
    CEFBS_None, // VINSGR2VR_W = 1130
17797
0
    CEFBS_None, // VLD = 1131
17798
0
    CEFBS_None, // VLDI = 1132
17799
0
    CEFBS_None, // VLDREPL_B = 1133
17800
0
    CEFBS_None, // VLDREPL_D = 1134
17801
0
    CEFBS_None, // VLDREPL_H = 1135
17802
0
    CEFBS_None, // VLDREPL_W = 1136
17803
0
    CEFBS_None, // VLDX = 1137
17804
0
    CEFBS_None, // VMADDWEV_D_W = 1138
17805
0
    CEFBS_None, // VMADDWEV_D_WU = 1139
17806
0
    CEFBS_None, // VMADDWEV_D_WU_W = 1140
17807
0
    CEFBS_None, // VMADDWEV_H_B = 1141
17808
0
    CEFBS_None, // VMADDWEV_H_BU = 1142
17809
0
    CEFBS_None, // VMADDWEV_H_BU_B = 1143
17810
0
    CEFBS_None, // VMADDWEV_Q_D = 1144
17811
0
    CEFBS_None, // VMADDWEV_Q_DU = 1145
17812
0
    CEFBS_None, // VMADDWEV_Q_DU_D = 1146
17813
0
    CEFBS_None, // VMADDWEV_W_H = 1147
17814
0
    CEFBS_None, // VMADDWEV_W_HU = 1148
17815
0
    CEFBS_None, // VMADDWEV_W_HU_H = 1149
17816
0
    CEFBS_None, // VMADDWOD_D_W = 1150
17817
0
    CEFBS_None, // VMADDWOD_D_WU = 1151
17818
0
    CEFBS_None, // VMADDWOD_D_WU_W = 1152
17819
0
    CEFBS_None, // VMADDWOD_H_B = 1153
17820
0
    CEFBS_None, // VMADDWOD_H_BU = 1154
17821
0
    CEFBS_None, // VMADDWOD_H_BU_B = 1155
17822
0
    CEFBS_None, // VMADDWOD_Q_D = 1156
17823
0
    CEFBS_None, // VMADDWOD_Q_DU = 1157
17824
0
    CEFBS_None, // VMADDWOD_Q_DU_D = 1158
17825
0
    CEFBS_None, // VMADDWOD_W_H = 1159
17826
0
    CEFBS_None, // VMADDWOD_W_HU = 1160
17827
0
    CEFBS_None, // VMADDWOD_W_HU_H = 1161
17828
0
    CEFBS_None, // VMADD_B = 1162
17829
0
    CEFBS_None, // VMADD_D = 1163
17830
0
    CEFBS_None, // VMADD_H = 1164
17831
0
    CEFBS_None, // VMADD_W = 1165
17832
0
    CEFBS_None, // VMAXI_B = 1166
17833
0
    CEFBS_None, // VMAXI_BU = 1167
17834
0
    CEFBS_None, // VMAXI_D = 1168
17835
0
    CEFBS_None, // VMAXI_DU = 1169
17836
0
    CEFBS_None, // VMAXI_H = 1170
17837
0
    CEFBS_None, // VMAXI_HU = 1171
17838
0
    CEFBS_None, // VMAXI_W = 1172
17839
0
    CEFBS_None, // VMAXI_WU = 1173
17840
0
    CEFBS_None, // VMAX_B = 1174
17841
0
    CEFBS_None, // VMAX_BU = 1175
17842
0
    CEFBS_None, // VMAX_D = 1176
17843
0
    CEFBS_None, // VMAX_DU = 1177
17844
0
    CEFBS_None, // VMAX_H = 1178
17845
0
    CEFBS_None, // VMAX_HU = 1179
17846
0
    CEFBS_None, // VMAX_W = 1180
17847
0
    CEFBS_None, // VMAX_WU = 1181
17848
0
    CEFBS_None, // VMINI_B = 1182
17849
0
    CEFBS_None, // VMINI_BU = 1183
17850
0
    CEFBS_None, // VMINI_D = 1184
17851
0
    CEFBS_None, // VMINI_DU = 1185
17852
0
    CEFBS_None, // VMINI_H = 1186
17853
0
    CEFBS_None, // VMINI_HU = 1187
17854
0
    CEFBS_None, // VMINI_W = 1188
17855
0
    CEFBS_None, // VMINI_WU = 1189
17856
0
    CEFBS_None, // VMIN_B = 1190
17857
0
    CEFBS_None, // VMIN_BU = 1191
17858
0
    CEFBS_None, // VMIN_D = 1192
17859
0
    CEFBS_None, // VMIN_DU = 1193
17860
0
    CEFBS_None, // VMIN_H = 1194
17861
0
    CEFBS_None, // VMIN_HU = 1195
17862
0
    CEFBS_None, // VMIN_W = 1196
17863
0
    CEFBS_None, // VMIN_WU = 1197
17864
0
    CEFBS_None, // VMOD_B = 1198
17865
0
    CEFBS_None, // VMOD_BU = 1199
17866
0
    CEFBS_None, // VMOD_D = 1200
17867
0
    CEFBS_None, // VMOD_DU = 1201
17868
0
    CEFBS_None, // VMOD_H = 1202
17869
0
    CEFBS_None, // VMOD_HU = 1203
17870
0
    CEFBS_None, // VMOD_W = 1204
17871
0
    CEFBS_None, // VMOD_WU = 1205
17872
0
    CEFBS_None, // VMSKGEZ_B = 1206
17873
0
    CEFBS_None, // VMSKLTZ_B = 1207
17874
0
    CEFBS_None, // VMSKLTZ_D = 1208
17875
0
    CEFBS_None, // VMSKLTZ_H = 1209
17876
0
    CEFBS_None, // VMSKLTZ_W = 1210
17877
0
    CEFBS_None, // VMSKNZ_B = 1211
17878
0
    CEFBS_None, // VMSUB_B = 1212
17879
0
    CEFBS_None, // VMSUB_D = 1213
17880
0
    CEFBS_None, // VMSUB_H = 1214
17881
0
    CEFBS_None, // VMSUB_W = 1215
17882
0
    CEFBS_None, // VMUH_B = 1216
17883
0
    CEFBS_None, // VMUH_BU = 1217
17884
0
    CEFBS_None, // VMUH_D = 1218
17885
0
    CEFBS_None, // VMUH_DU = 1219
17886
0
    CEFBS_None, // VMUH_H = 1220
17887
0
    CEFBS_None, // VMUH_HU = 1221
17888
0
    CEFBS_None, // VMUH_W = 1222
17889
0
    CEFBS_None, // VMUH_WU = 1223
17890
0
    CEFBS_None, // VMULWEV_D_W = 1224
17891
0
    CEFBS_None, // VMULWEV_D_WU = 1225
17892
0
    CEFBS_None, // VMULWEV_D_WU_W = 1226
17893
0
    CEFBS_None, // VMULWEV_H_B = 1227
17894
0
    CEFBS_None, // VMULWEV_H_BU = 1228
17895
0
    CEFBS_None, // VMULWEV_H_BU_B = 1229
17896
0
    CEFBS_None, // VMULWEV_Q_D = 1230
17897
0
    CEFBS_None, // VMULWEV_Q_DU = 1231
17898
0
    CEFBS_None, // VMULWEV_Q_DU_D = 1232
17899
0
    CEFBS_None, // VMULWEV_W_H = 1233
17900
0
    CEFBS_None, // VMULWEV_W_HU = 1234
17901
0
    CEFBS_None, // VMULWEV_W_HU_H = 1235
17902
0
    CEFBS_None, // VMULWOD_D_W = 1236
17903
0
    CEFBS_None, // VMULWOD_D_WU = 1237
17904
0
    CEFBS_None, // VMULWOD_D_WU_W = 1238
17905
0
    CEFBS_None, // VMULWOD_H_B = 1239
17906
0
    CEFBS_None, // VMULWOD_H_BU = 1240
17907
0
    CEFBS_None, // VMULWOD_H_BU_B = 1241
17908
0
    CEFBS_None, // VMULWOD_Q_D = 1242
17909
0
    CEFBS_None, // VMULWOD_Q_DU = 1243
17910
0
    CEFBS_None, // VMULWOD_Q_DU_D = 1244
17911
0
    CEFBS_None, // VMULWOD_W_H = 1245
17912
0
    CEFBS_None, // VMULWOD_W_HU = 1246
17913
0
    CEFBS_None, // VMULWOD_W_HU_H = 1247
17914
0
    CEFBS_None, // VMUL_B = 1248
17915
0
    CEFBS_None, // VMUL_D = 1249
17916
0
    CEFBS_None, // VMUL_H = 1250
17917
0
    CEFBS_None, // VMUL_W = 1251
17918
0
    CEFBS_None, // VNEG_B = 1252
17919
0
    CEFBS_None, // VNEG_D = 1253
17920
0
    CEFBS_None, // VNEG_H = 1254
17921
0
    CEFBS_None, // VNEG_W = 1255
17922
0
    CEFBS_None, // VNORI_B = 1256
17923
0
    CEFBS_None, // VNOR_V = 1257
17924
0
    CEFBS_None, // VORI_B = 1258
17925
0
    CEFBS_None, // VORN_V = 1259
17926
0
    CEFBS_None, // VOR_V = 1260
17927
0
    CEFBS_None, // VPACKEV_B = 1261
17928
0
    CEFBS_None, // VPACKEV_D = 1262
17929
0
    CEFBS_None, // VPACKEV_H = 1263
17930
0
    CEFBS_None, // VPACKEV_W = 1264
17931
0
    CEFBS_None, // VPACKOD_B = 1265
17932
0
    CEFBS_None, // VPACKOD_D = 1266
17933
0
    CEFBS_None, // VPACKOD_H = 1267
17934
0
    CEFBS_None, // VPACKOD_W = 1268
17935
0
    CEFBS_None, // VPCNT_B = 1269
17936
0
    CEFBS_None, // VPCNT_D = 1270
17937
0
    CEFBS_None, // VPCNT_H = 1271
17938
0
    CEFBS_None, // VPCNT_W = 1272
17939
0
    CEFBS_None, // VPERMI_W = 1273
17940
0
    CEFBS_None, // VPICKEV_B = 1274
17941
0
    CEFBS_None, // VPICKEV_D = 1275
17942
0
    CEFBS_None, // VPICKEV_H = 1276
17943
0
    CEFBS_None, // VPICKEV_W = 1277
17944
0
    CEFBS_None, // VPICKOD_B = 1278
17945
0
    CEFBS_None, // VPICKOD_D = 1279
17946
0
    CEFBS_None, // VPICKOD_H = 1280
17947
0
    CEFBS_None, // VPICKOD_W = 1281
17948
0
    CEFBS_None, // VPICKVE2GR_B = 1282
17949
0
    CEFBS_None, // VPICKVE2GR_BU = 1283
17950
0
    CEFBS_None, // VPICKVE2GR_D = 1284
17951
0
    CEFBS_None, // VPICKVE2GR_DU = 1285
17952
0
    CEFBS_None, // VPICKVE2GR_H = 1286
17953
0
    CEFBS_None, // VPICKVE2GR_HU = 1287
17954
0
    CEFBS_None, // VPICKVE2GR_W = 1288
17955
0
    CEFBS_None, // VPICKVE2GR_WU = 1289
17956
0
    CEFBS_None, // VREPLGR2VR_B = 1290
17957
0
    CEFBS_None, // VREPLGR2VR_D = 1291
17958
0
    CEFBS_None, // VREPLGR2VR_H = 1292
17959
0
    CEFBS_None, // VREPLGR2VR_W = 1293
17960
0
    CEFBS_None, // VREPLVEI_B = 1294
17961
0
    CEFBS_None, // VREPLVEI_D = 1295
17962
0
    CEFBS_None, // VREPLVEI_H = 1296
17963
0
    CEFBS_None, // VREPLVEI_W = 1297
17964
0
    CEFBS_None, // VREPLVE_B = 1298
17965
0
    CEFBS_None, // VREPLVE_D = 1299
17966
0
    CEFBS_None, // VREPLVE_H = 1300
17967
0
    CEFBS_None, // VREPLVE_W = 1301
17968
0
    CEFBS_None, // VROTRI_B = 1302
17969
0
    CEFBS_None, // VROTRI_D = 1303
17970
0
    CEFBS_None, // VROTRI_H = 1304
17971
0
    CEFBS_None, // VROTRI_W = 1305
17972
0
    CEFBS_None, // VROTR_B = 1306
17973
0
    CEFBS_None, // VROTR_D = 1307
17974
0
    CEFBS_None, // VROTR_H = 1308
17975
0
    CEFBS_None, // VROTR_W = 1309
17976
0
    CEFBS_None, // VSADD_B = 1310
17977
0
    CEFBS_None, // VSADD_BU = 1311
17978
0
    CEFBS_None, // VSADD_D = 1312
17979
0
    CEFBS_None, // VSADD_DU = 1313
17980
0
    CEFBS_None, // VSADD_H = 1314
17981
0
    CEFBS_None, // VSADD_HU = 1315
17982
0
    CEFBS_None, // VSADD_W = 1316
17983
0
    CEFBS_None, // VSADD_WU = 1317
17984
0
    CEFBS_None, // VSAT_B = 1318
17985
0
    CEFBS_None, // VSAT_BU = 1319
17986
0
    CEFBS_None, // VSAT_D = 1320
17987
0
    CEFBS_None, // VSAT_DU = 1321
17988
0
    CEFBS_None, // VSAT_H = 1322
17989
0
    CEFBS_None, // VSAT_HU = 1323
17990
0
    CEFBS_None, // VSAT_W = 1324
17991
0
    CEFBS_None, // VSAT_WU = 1325
17992
0
    CEFBS_None, // VSEQI_B = 1326
17993
0
    CEFBS_None, // VSEQI_D = 1327
17994
0
    CEFBS_None, // VSEQI_H = 1328
17995
0
    CEFBS_None, // VSEQI_W = 1329
17996
0
    CEFBS_None, // VSEQ_B = 1330
17997
0
    CEFBS_None, // VSEQ_D = 1331
17998
0
    CEFBS_None, // VSEQ_H = 1332
17999
0
    CEFBS_None, // VSEQ_W = 1333
18000
0
    CEFBS_None, // VSETALLNEZ_B = 1334
18001
0
    CEFBS_None, // VSETALLNEZ_D = 1335
18002
0
    CEFBS_None, // VSETALLNEZ_H = 1336
18003
0
    CEFBS_None, // VSETALLNEZ_W = 1337
18004
0
    CEFBS_None, // VSETANYEQZ_B = 1338
18005
0
    CEFBS_None, // VSETANYEQZ_D = 1339
18006
0
    CEFBS_None, // VSETANYEQZ_H = 1340
18007
0
    CEFBS_None, // VSETANYEQZ_W = 1341
18008
0
    CEFBS_None, // VSETEQZ_V = 1342
18009
0
    CEFBS_None, // VSETNEZ_V = 1343
18010
0
    CEFBS_None, // VSHUF4I_B = 1344
18011
0
    CEFBS_None, // VSHUF4I_D = 1345
18012
0
    CEFBS_None, // VSHUF4I_H = 1346
18013
0
    CEFBS_None, // VSHUF4I_W = 1347
18014
0
    CEFBS_None, // VSHUF_B = 1348
18015
0
    CEFBS_None, // VSHUF_D = 1349
18016
0
    CEFBS_None, // VSHUF_H = 1350
18017
0
    CEFBS_None, // VSHUF_W = 1351
18018
0
    CEFBS_None, // VSIGNCOV_B = 1352
18019
0
    CEFBS_None, // VSIGNCOV_D = 1353
18020
0
    CEFBS_None, // VSIGNCOV_H = 1354
18021
0
    CEFBS_None, // VSIGNCOV_W = 1355
18022
0
    CEFBS_None, // VSLEI_B = 1356
18023
0
    CEFBS_None, // VSLEI_BU = 1357
18024
0
    CEFBS_None, // VSLEI_D = 1358
18025
0
    CEFBS_None, // VSLEI_DU = 1359
18026
0
    CEFBS_None, // VSLEI_H = 1360
18027
0
    CEFBS_None, // VSLEI_HU = 1361
18028
0
    CEFBS_None, // VSLEI_W = 1362
18029
0
    CEFBS_None, // VSLEI_WU = 1363
18030
0
    CEFBS_None, // VSLE_B = 1364
18031
0
    CEFBS_None, // VSLE_BU = 1365
18032
0
    CEFBS_None, // VSLE_D = 1366
18033
0
    CEFBS_None, // VSLE_DU = 1367
18034
0
    CEFBS_None, // VSLE_H = 1368
18035
0
    CEFBS_None, // VSLE_HU = 1369
18036
0
    CEFBS_None, // VSLE_W = 1370
18037
0
    CEFBS_None, // VSLE_WU = 1371
18038
0
    CEFBS_None, // VSLLI_B = 1372
18039
0
    CEFBS_None, // VSLLI_D = 1373
18040
0
    CEFBS_None, // VSLLI_H = 1374
18041
0
    CEFBS_None, // VSLLI_W = 1375
18042
0
    CEFBS_None, // VSLLWIL_DU_WU = 1376
18043
0
    CEFBS_None, // VSLLWIL_D_W = 1377
18044
0
    CEFBS_None, // VSLLWIL_HU_BU = 1378
18045
0
    CEFBS_None, // VSLLWIL_H_B = 1379
18046
0
    CEFBS_None, // VSLLWIL_WU_HU = 1380
18047
0
    CEFBS_None, // VSLLWIL_W_H = 1381
18048
0
    CEFBS_None, // VSLL_B = 1382
18049
0
    CEFBS_None, // VSLL_D = 1383
18050
0
    CEFBS_None, // VSLL_H = 1384
18051
0
    CEFBS_None, // VSLL_W = 1385
18052
0
    CEFBS_None, // VSLTI_B = 1386
18053
0
    CEFBS_None, // VSLTI_BU = 1387
18054
0
    CEFBS_None, // VSLTI_D = 1388
18055
0
    CEFBS_None, // VSLTI_DU = 1389
18056
0
    CEFBS_None, // VSLTI_H = 1390
18057
0
    CEFBS_None, // VSLTI_HU = 1391
18058
0
    CEFBS_None, // VSLTI_W = 1392
18059
0
    CEFBS_None, // VSLTI_WU = 1393
18060
0
    CEFBS_None, // VSLT_B = 1394
18061
0
    CEFBS_None, // VSLT_BU = 1395
18062
0
    CEFBS_None, // VSLT_D = 1396
18063
0
    CEFBS_None, // VSLT_DU = 1397
18064
0
    CEFBS_None, // VSLT_H = 1398
18065
0
    CEFBS_None, // VSLT_HU = 1399
18066
0
    CEFBS_None, // VSLT_W = 1400
18067
0
    CEFBS_None, // VSLT_WU = 1401
18068
0
    CEFBS_None, // VSRAI_B = 1402
18069
0
    CEFBS_None, // VSRAI_D = 1403
18070
0
    CEFBS_None, // VSRAI_H = 1404
18071
0
    CEFBS_None, // VSRAI_W = 1405
18072
0
    CEFBS_None, // VSRANI_B_H = 1406
18073
0
    CEFBS_None, // VSRANI_D_Q = 1407
18074
0
    CEFBS_None, // VSRANI_H_W = 1408
18075
0
    CEFBS_None, // VSRANI_W_D = 1409
18076
0
    CEFBS_None, // VSRAN_B_H = 1410
18077
0
    CEFBS_None, // VSRAN_H_W = 1411
18078
0
    CEFBS_None, // VSRAN_W_D = 1412
18079
0
    CEFBS_None, // VSRARI_B = 1413
18080
0
    CEFBS_None, // VSRARI_D = 1414
18081
0
    CEFBS_None, // VSRARI_H = 1415
18082
0
    CEFBS_None, // VSRARI_W = 1416
18083
0
    CEFBS_None, // VSRARNI_B_H = 1417
18084
0
    CEFBS_None, // VSRARNI_D_Q = 1418
18085
0
    CEFBS_None, // VSRARNI_H_W = 1419
18086
0
    CEFBS_None, // VSRARNI_W_D = 1420
18087
0
    CEFBS_None, // VSRARN_B_H = 1421
18088
0
    CEFBS_None, // VSRARN_H_W = 1422
18089
0
    CEFBS_None, // VSRARN_W_D = 1423
18090
0
    CEFBS_None, // VSRAR_B = 1424
18091
0
    CEFBS_None, // VSRAR_D = 1425
18092
0
    CEFBS_None, // VSRAR_H = 1426
18093
0
    CEFBS_None, // VSRAR_W = 1427
18094
0
    CEFBS_None, // VSRA_B = 1428
18095
0
    CEFBS_None, // VSRA_D = 1429
18096
0
    CEFBS_None, // VSRA_H = 1430
18097
0
    CEFBS_None, // VSRA_W = 1431
18098
0
    CEFBS_None, // VSRLI_B = 1432
18099
0
    CEFBS_None, // VSRLI_D = 1433
18100
0
    CEFBS_None, // VSRLI_H = 1434
18101
0
    CEFBS_None, // VSRLI_W = 1435
18102
0
    CEFBS_None, // VSRLNI_B_H = 1436
18103
0
    CEFBS_None, // VSRLNI_D_Q = 1437
18104
0
    CEFBS_None, // VSRLNI_H_W = 1438
18105
0
    CEFBS_None, // VSRLNI_W_D = 1439
18106
0
    CEFBS_None, // VSRLN_B_H = 1440
18107
0
    CEFBS_None, // VSRLN_H_W = 1441
18108
0
    CEFBS_None, // VSRLN_W_D = 1442
18109
0
    CEFBS_None, // VSRLRI_B = 1443
18110
0
    CEFBS_None, // VSRLRI_D = 1444
18111
0
    CEFBS_None, // VSRLRI_H = 1445
18112
0
    CEFBS_None, // VSRLRI_W = 1446
18113
0
    CEFBS_None, // VSRLRNI_B_H = 1447
18114
0
    CEFBS_None, // VSRLRNI_D_Q = 1448
18115
0
    CEFBS_None, // VSRLRNI_H_W = 1449
18116
0
    CEFBS_None, // VSRLRNI_W_D = 1450
18117
0
    CEFBS_None, // VSRLRN_B_H = 1451
18118
0
    CEFBS_None, // VSRLRN_H_W = 1452
18119
0
    CEFBS_None, // VSRLRN_W_D = 1453
18120
0
    CEFBS_None, // VSRLR_B = 1454
18121
0
    CEFBS_None, // VSRLR_D = 1455
18122
0
    CEFBS_None, // VSRLR_H = 1456
18123
0
    CEFBS_None, // VSRLR_W = 1457
18124
0
    CEFBS_None, // VSRL_B = 1458
18125
0
    CEFBS_None, // VSRL_D = 1459
18126
0
    CEFBS_None, // VSRL_H = 1460
18127
0
    CEFBS_None, // VSRL_W = 1461
18128
0
    CEFBS_None, // VSSRANI_BU_H = 1462
18129
0
    CEFBS_None, // VSSRANI_B_H = 1463
18130
0
    CEFBS_None, // VSSRANI_DU_Q = 1464
18131
0
    CEFBS_None, // VSSRANI_D_Q = 1465
18132
0
    CEFBS_None, // VSSRANI_HU_W = 1466
18133
0
    CEFBS_None, // VSSRANI_H_W = 1467
18134
0
    CEFBS_None, // VSSRANI_WU_D = 1468
18135
0
    CEFBS_None, // VSSRANI_W_D = 1469
18136
0
    CEFBS_None, // VSSRAN_BU_H = 1470
18137
0
    CEFBS_None, // VSSRAN_B_H = 1471
18138
0
    CEFBS_None, // VSSRAN_HU_W = 1472
18139
0
    CEFBS_None, // VSSRAN_H_W = 1473
18140
0
    CEFBS_None, // VSSRAN_WU_D = 1474
18141
0
    CEFBS_None, // VSSRAN_W_D = 1475
18142
0
    CEFBS_None, // VSSRARNI_BU_H = 1476
18143
0
    CEFBS_None, // VSSRARNI_B_H = 1477
18144
0
    CEFBS_None, // VSSRARNI_DU_Q = 1478
18145
0
    CEFBS_None, // VSSRARNI_D_Q = 1479
18146
0
    CEFBS_None, // VSSRARNI_HU_W = 1480
18147
0
    CEFBS_None, // VSSRARNI_H_W = 1481
18148
0
    CEFBS_None, // VSSRARNI_WU_D = 1482
18149
0
    CEFBS_None, // VSSRARNI_W_D = 1483
18150
0
    CEFBS_None, // VSSRARN_BU_H = 1484
18151
0
    CEFBS_None, // VSSRARN_B_H = 1485
18152
0
    CEFBS_None, // VSSRARN_HU_W = 1486
18153
0
    CEFBS_None, // VSSRARN_H_W = 1487
18154
0
    CEFBS_None, // VSSRARN_WU_D = 1488
18155
0
    CEFBS_None, // VSSRARN_W_D = 1489
18156
0
    CEFBS_None, // VSSRLNI_BU_H = 1490
18157
0
    CEFBS_None, // VSSRLNI_B_H = 1491
18158
0
    CEFBS_None, // VSSRLNI_DU_Q = 1492
18159
0
    CEFBS_None, // VSSRLNI_D_Q = 1493
18160
0
    CEFBS_None, // VSSRLNI_HU_W = 1494
18161
0
    CEFBS_None, // VSSRLNI_H_W = 1495
18162
0
    CEFBS_None, // VSSRLNI_WU_D = 1496
18163
0
    CEFBS_None, // VSSRLNI_W_D = 1497
18164
0
    CEFBS_None, // VSSRLN_BU_H = 1498
18165
0
    CEFBS_None, // VSSRLN_B_H = 1499
18166
0
    CEFBS_None, // VSSRLN_HU_W = 1500
18167
0
    CEFBS_None, // VSSRLN_H_W = 1501
18168
0
    CEFBS_None, // VSSRLN_WU_D = 1502
18169
0
    CEFBS_None, // VSSRLN_W_D = 1503
18170
0
    CEFBS_None, // VSSRLRNI_BU_H = 1504
18171
0
    CEFBS_None, // VSSRLRNI_B_H = 1505
18172
0
    CEFBS_None, // VSSRLRNI_DU_Q = 1506
18173
0
    CEFBS_None, // VSSRLRNI_D_Q = 1507
18174
0
    CEFBS_None, // VSSRLRNI_HU_W = 1508
18175
0
    CEFBS_None, // VSSRLRNI_H_W = 1509
18176
0
    CEFBS_None, // VSSRLRNI_WU_D = 1510
18177
0
    CEFBS_None, // VSSRLRNI_W_D = 1511
18178
0
    CEFBS_None, // VSSRLRN_BU_H = 1512
18179
0
    CEFBS_None, // VSSRLRN_B_H = 1513
18180
0
    CEFBS_None, // VSSRLRN_HU_W = 1514
18181
0
    CEFBS_None, // VSSRLRN_H_W = 1515
18182
0
    CEFBS_None, // VSSRLRN_WU_D = 1516
18183
0
    CEFBS_None, // VSSRLRN_W_D = 1517
18184
0
    CEFBS_None, // VSSUB_B = 1518
18185
0
    CEFBS_None, // VSSUB_BU = 1519
18186
0
    CEFBS_None, // VSSUB_D = 1520
18187
0
    CEFBS_None, // VSSUB_DU = 1521
18188
0
    CEFBS_None, // VSSUB_H = 1522
18189
0
    CEFBS_None, // VSSUB_HU = 1523
18190
0
    CEFBS_None, // VSSUB_W = 1524
18191
0
    CEFBS_None, // VSSUB_WU = 1525
18192
0
    CEFBS_None, // VST = 1526
18193
0
    CEFBS_None, // VSTELM_B = 1527
18194
0
    CEFBS_None, // VSTELM_D = 1528
18195
0
    CEFBS_None, // VSTELM_H = 1529
18196
0
    CEFBS_None, // VSTELM_W = 1530
18197
0
    CEFBS_None, // VSTX = 1531
18198
0
    CEFBS_None, // VSUBI_BU = 1532
18199
0
    CEFBS_None, // VSUBI_DU = 1533
18200
0
    CEFBS_None, // VSUBI_HU = 1534
18201
0
    CEFBS_None, // VSUBI_WU = 1535
18202
0
    CEFBS_None, // VSUBWEV_D_W = 1536
18203
0
    CEFBS_None, // VSUBWEV_D_WU = 1537
18204
0
    CEFBS_None, // VSUBWEV_H_B = 1538
18205
0
    CEFBS_None, // VSUBWEV_H_BU = 1539
18206
0
    CEFBS_None, // VSUBWEV_Q_D = 1540
18207
0
    CEFBS_None, // VSUBWEV_Q_DU = 1541
18208
0
    CEFBS_None, // VSUBWEV_W_H = 1542
18209
0
    CEFBS_None, // VSUBWEV_W_HU = 1543
18210
0
    CEFBS_None, // VSUBWOD_D_W = 1544
18211
0
    CEFBS_None, // VSUBWOD_D_WU = 1545
18212
0
    CEFBS_None, // VSUBWOD_H_B = 1546
18213
0
    CEFBS_None, // VSUBWOD_H_BU = 1547
18214
0
    CEFBS_None, // VSUBWOD_Q_D = 1548
18215
0
    CEFBS_None, // VSUBWOD_Q_DU = 1549
18216
0
    CEFBS_None, // VSUBWOD_W_H = 1550
18217
0
    CEFBS_None, // VSUBWOD_W_HU = 1551
18218
0
    CEFBS_None, // VSUB_B = 1552
18219
0
    CEFBS_None, // VSUB_D = 1553
18220
0
    CEFBS_None, // VSUB_H = 1554
18221
0
    CEFBS_None, // VSUB_Q = 1555
18222
0
    CEFBS_None, // VSUB_W = 1556
18223
0
    CEFBS_None, // VXORI_B = 1557
18224
0
    CEFBS_None, // VXOR_V = 1558
18225
0
    CEFBS_None, // X86ADC_B = 1559
18226
0
    CEFBS_IsLA64, // X86ADC_D = 1560
18227
0
    CEFBS_None, // X86ADC_H = 1561
18228
0
    CEFBS_None, // X86ADC_W = 1562
18229
0
    CEFBS_None, // X86ADD_B = 1563
18230
0
    CEFBS_IsLA64, // X86ADD_D = 1564
18231
0
    CEFBS_IsLA64, // X86ADD_DU = 1565
18232
0
    CEFBS_None, // X86ADD_H = 1566
18233
0
    CEFBS_None, // X86ADD_W = 1567
18234
0
    CEFBS_IsLA64, // X86ADD_WU = 1568
18235
0
    CEFBS_None, // X86AND_B = 1569
18236
0
    CEFBS_IsLA64, // X86AND_D = 1570
18237
0
    CEFBS_None, // X86AND_H = 1571
18238
0
    CEFBS_None, // X86AND_W = 1572
18239
0
    CEFBS_None, // X86CLRTM = 1573
18240
0
    CEFBS_None, // X86DECTOP = 1574
18241
0
    CEFBS_None, // X86DEC_B = 1575
18242
0
    CEFBS_IsLA64, // X86DEC_D = 1576
18243
0
    CEFBS_None, // X86DEC_H = 1577
18244
0
    CEFBS_None, // X86DEC_W = 1578
18245
0
    CEFBS_None, // X86INCTOP = 1579
18246
0
    CEFBS_None, // X86INC_B = 1580
18247
0
    CEFBS_IsLA64, // X86INC_D = 1581
18248
0
    CEFBS_None, // X86INC_H = 1582
18249
0
    CEFBS_None, // X86INC_W = 1583
18250
0
    CEFBS_None, // X86MFFLAG = 1584
18251
0
    CEFBS_None, // X86MFTOP = 1585
18252
0
    CEFBS_None, // X86MTFLAG = 1586
18253
0
    CEFBS_None, // X86MTTOP = 1587
18254
0
    CEFBS_None, // X86MUL_B = 1588
18255
0
    CEFBS_None, // X86MUL_BU = 1589
18256
0
    CEFBS_IsLA64, // X86MUL_D = 1590
18257
0
    CEFBS_IsLA64, // X86MUL_DU = 1591
18258
0
    CEFBS_None, // X86MUL_H = 1592
18259
0
    CEFBS_None, // X86MUL_HU = 1593
18260
0
    CEFBS_None, // X86MUL_W = 1594
18261
0
    CEFBS_IsLA64, // X86MUL_WU = 1595
18262
0
    CEFBS_None, // X86OR_B = 1596
18263
0
    CEFBS_IsLA64, // X86OR_D = 1597
18264
0
    CEFBS_None, // X86OR_H = 1598
18265
0
    CEFBS_None, // X86OR_W = 1599
18266
0
    CEFBS_None, // X86RCLI_B = 1600
18267
0
    CEFBS_IsLA64, // X86RCLI_D = 1601
18268
0
    CEFBS_None, // X86RCLI_H = 1602
18269
0
    CEFBS_None, // X86RCLI_W = 1603
18270
0
    CEFBS_None, // X86RCL_B = 1604
18271
0
    CEFBS_IsLA64, // X86RCL_D = 1605
18272
0
    CEFBS_None, // X86RCL_H = 1606
18273
0
    CEFBS_None, // X86RCL_W = 1607
18274
0
    CEFBS_None, // X86RCRI_B = 1608
18275
0
    CEFBS_IsLA64, // X86RCRI_D = 1609
18276
0
    CEFBS_None, // X86RCRI_H = 1610
18277
0
    CEFBS_None, // X86RCRI_W = 1611
18278
0
    CEFBS_None, // X86RCR_B = 1612
18279
0
    CEFBS_IsLA64, // X86RCR_D = 1613
18280
0
    CEFBS_None, // X86RCR_H = 1614
18281
0
    CEFBS_None, // X86RCR_W = 1615
18282
0
    CEFBS_None, // X86ROTLI_B = 1616
18283
0
    CEFBS_IsLA64, // X86ROTLI_D = 1617
18284
0
    CEFBS_None, // X86ROTLI_H = 1618
18285
0
    CEFBS_None, // X86ROTLI_W = 1619
18286
0
    CEFBS_None, // X86ROTL_B = 1620
18287
0
    CEFBS_IsLA64, // X86ROTL_D = 1621
18288
0
    CEFBS_None, // X86ROTL_H = 1622
18289
0
    CEFBS_None, // X86ROTL_W = 1623
18290
0
    CEFBS_None, // X86ROTRI_B = 1624
18291
0
    CEFBS_IsLA64, // X86ROTRI_D = 1625
18292
0
    CEFBS_None, // X86ROTRI_H = 1626
18293
0
    CEFBS_None, // X86ROTRI_W = 1627
18294
0
    CEFBS_None, // X86ROTR_B = 1628
18295
0
    CEFBS_IsLA64, // X86ROTR_D = 1629
18296
0
    CEFBS_None, // X86ROTR_H = 1630
18297
0
    CEFBS_None, // X86ROTR_W = 1631
18298
0
    CEFBS_None, // X86SBC_B = 1632
18299
0
    CEFBS_IsLA64, // X86SBC_D = 1633
18300
0
    CEFBS_None, // X86SBC_H = 1634
18301
0
    CEFBS_None, // X86SBC_W = 1635
18302
0
    CEFBS_None, // X86SETTAG = 1636
18303
0
    CEFBS_None, // X86SETTM = 1637
18304
0
    CEFBS_None, // X86SLLI_B = 1638
18305
0
    CEFBS_IsLA64, // X86SLLI_D = 1639
18306
0
    CEFBS_None, // X86SLLI_H = 1640
18307
0
    CEFBS_None, // X86SLLI_W = 1641
18308
0
    CEFBS_None, // X86SLL_B = 1642
18309
0
    CEFBS_IsLA64, // X86SLL_D = 1643
18310
0
    CEFBS_None, // X86SLL_H = 1644
18311
0
    CEFBS_None, // X86SLL_W = 1645
18312
0
    CEFBS_None, // X86SRAI_B = 1646
18313
0
    CEFBS_IsLA64, // X86SRAI_D = 1647
18314
0
    CEFBS_None, // X86SRAI_H = 1648
18315
0
    CEFBS_None, // X86SRAI_W = 1649
18316
0
    CEFBS_None, // X86SRA_B = 1650
18317
0
    CEFBS_IsLA64, // X86SRA_D = 1651
18318
0
    CEFBS_None, // X86SRA_H = 1652
18319
0
    CEFBS_None, // X86SRA_W = 1653
18320
0
    CEFBS_None, // X86SRLI_B = 1654
18321
0
    CEFBS_IsLA64, // X86SRLI_D = 1655
18322
0
    CEFBS_None, // X86SRLI_H = 1656
18323
0
    CEFBS_None, // X86SRLI_W = 1657
18324
0
    CEFBS_None, // X86SRL_B = 1658
18325
0
    CEFBS_IsLA64, // X86SRL_D = 1659
18326
0
    CEFBS_None, // X86SRL_H = 1660
18327
0
    CEFBS_None, // X86SRL_W = 1661
18328
0
    CEFBS_None, // X86SUB_B = 1662
18329
0
    CEFBS_IsLA64, // X86SUB_D = 1663
18330
0
    CEFBS_IsLA64, // X86SUB_DU = 1664
18331
0
    CEFBS_None, // X86SUB_H = 1665
18332
0
    CEFBS_None, // X86SUB_W = 1666
18333
0
    CEFBS_IsLA64, // X86SUB_WU = 1667
18334
0
    CEFBS_None, // X86XOR_B = 1668
18335
0
    CEFBS_IsLA64, // X86XOR_D = 1669
18336
0
    CEFBS_None, // X86XOR_H = 1670
18337
0
    CEFBS_None, // X86XOR_W = 1671
18338
0
    CEFBS_None, // XOR = 1672
18339
0
    CEFBS_None, // XORI = 1673
18340
0
    CEFBS_None, // XVABSD_B = 1674
18341
0
    CEFBS_None, // XVABSD_BU = 1675
18342
0
    CEFBS_None, // XVABSD_D = 1676
18343
0
    CEFBS_None, // XVABSD_DU = 1677
18344
0
    CEFBS_None, // XVABSD_H = 1678
18345
0
    CEFBS_None, // XVABSD_HU = 1679
18346
0
    CEFBS_None, // XVABSD_W = 1680
18347
0
    CEFBS_None, // XVABSD_WU = 1681
18348
0
    CEFBS_None, // XVADDA_B = 1682
18349
0
    CEFBS_None, // XVADDA_D = 1683
18350
0
    CEFBS_None, // XVADDA_H = 1684
18351
0
    CEFBS_None, // XVADDA_W = 1685
18352
0
    CEFBS_None, // XVADDI_BU = 1686
18353
0
    CEFBS_None, // XVADDI_DU = 1687
18354
0
    CEFBS_None, // XVADDI_HU = 1688
18355
0
    CEFBS_None, // XVADDI_WU = 1689
18356
0
    CEFBS_None, // XVADDWEV_D_W = 1690
18357
0
    CEFBS_None, // XVADDWEV_D_WU = 1691
18358
0
    CEFBS_None, // XVADDWEV_D_WU_W = 1692
18359
0
    CEFBS_None, // XVADDWEV_H_B = 1693
18360
0
    CEFBS_None, // XVADDWEV_H_BU = 1694
18361
0
    CEFBS_None, // XVADDWEV_H_BU_B = 1695
18362
0
    CEFBS_None, // XVADDWEV_Q_D = 1696
18363
0
    CEFBS_None, // XVADDWEV_Q_DU = 1697
18364
0
    CEFBS_None, // XVADDWEV_Q_DU_D = 1698
18365
0
    CEFBS_None, // XVADDWEV_W_H = 1699
18366
0
    CEFBS_None, // XVADDWEV_W_HU = 1700
18367
0
    CEFBS_None, // XVADDWEV_W_HU_H = 1701
18368
0
    CEFBS_None, // XVADDWOD_D_W = 1702
18369
0
    CEFBS_None, // XVADDWOD_D_WU = 1703
18370
0
    CEFBS_None, // XVADDWOD_D_WU_W = 1704
18371
0
    CEFBS_None, // XVADDWOD_H_B = 1705
18372
0
    CEFBS_None, // XVADDWOD_H_BU = 1706
18373
0
    CEFBS_None, // XVADDWOD_H_BU_B = 1707
18374
0
    CEFBS_None, // XVADDWOD_Q_D = 1708
18375
0
    CEFBS_None, // XVADDWOD_Q_DU = 1709
18376
0
    CEFBS_None, // XVADDWOD_Q_DU_D = 1710
18377
0
    CEFBS_None, // XVADDWOD_W_H = 1711
18378
0
    CEFBS_None, // XVADDWOD_W_HU = 1712
18379
0
    CEFBS_None, // XVADDWOD_W_HU_H = 1713
18380
0
    CEFBS_None, // XVADD_B = 1714
18381
0
    CEFBS_None, // XVADD_D = 1715
18382
0
    CEFBS_None, // XVADD_H = 1716
18383
0
    CEFBS_None, // XVADD_Q = 1717
18384
0
    CEFBS_None, // XVADD_W = 1718
18385
0
    CEFBS_None, // XVANDI_B = 1719
18386
0
    CEFBS_None, // XVANDN_V = 1720
18387
0
    CEFBS_None, // XVAND_V = 1721
18388
0
    CEFBS_None, // XVAVGR_B = 1722
18389
0
    CEFBS_None, // XVAVGR_BU = 1723
18390
0
    CEFBS_None, // XVAVGR_D = 1724
18391
0
    CEFBS_None, // XVAVGR_DU = 1725
18392
0
    CEFBS_None, // XVAVGR_H = 1726
18393
0
    CEFBS_None, // XVAVGR_HU = 1727
18394
0
    CEFBS_None, // XVAVGR_W = 1728
18395
0
    CEFBS_None, // XVAVGR_WU = 1729
18396
0
    CEFBS_None, // XVAVG_B = 1730
18397
0
    CEFBS_None, // XVAVG_BU = 1731
18398
0
    CEFBS_None, // XVAVG_D = 1732
18399
0
    CEFBS_None, // XVAVG_DU = 1733
18400
0
    CEFBS_None, // XVAVG_H = 1734
18401
0
    CEFBS_None, // XVAVG_HU = 1735
18402
0
    CEFBS_None, // XVAVG_W = 1736
18403
0
    CEFBS_None, // XVAVG_WU = 1737
18404
0
    CEFBS_None, // XVBITCLRI_B = 1738
18405
0
    CEFBS_None, // XVBITCLRI_D = 1739
18406
0
    CEFBS_None, // XVBITCLRI_H = 1740
18407
0
    CEFBS_None, // XVBITCLRI_W = 1741
18408
0
    CEFBS_None, // XVBITCLR_B = 1742
18409
0
    CEFBS_None, // XVBITCLR_D = 1743
18410
0
    CEFBS_None, // XVBITCLR_H = 1744
18411
0
    CEFBS_None, // XVBITCLR_W = 1745
18412
0
    CEFBS_None, // XVBITREVI_B = 1746
18413
0
    CEFBS_None, // XVBITREVI_D = 1747
18414
0
    CEFBS_None, // XVBITREVI_H = 1748
18415
0
    CEFBS_None, // XVBITREVI_W = 1749
18416
0
    CEFBS_None, // XVBITREV_B = 1750
18417
0
    CEFBS_None, // XVBITREV_D = 1751
18418
0
    CEFBS_None, // XVBITREV_H = 1752
18419
0
    CEFBS_None, // XVBITREV_W = 1753
18420
0
    CEFBS_None, // XVBITSELI_B = 1754
18421
0
    CEFBS_None, // XVBITSEL_V = 1755
18422
0
    CEFBS_None, // XVBITSETI_B = 1756
18423
0
    CEFBS_None, // XVBITSETI_D = 1757
18424
0
    CEFBS_None, // XVBITSETI_H = 1758
18425
0
    CEFBS_None, // XVBITSETI_W = 1759
18426
0
    CEFBS_None, // XVBITSET_B = 1760
18427
0
    CEFBS_None, // XVBITSET_D = 1761
18428
0
    CEFBS_None, // XVBITSET_H = 1762
18429
0
    CEFBS_None, // XVBITSET_W = 1763
18430
0
    CEFBS_None, // XVBSLL_V = 1764
18431
0
    CEFBS_None, // XVBSRL_V = 1765
18432
0
    CEFBS_None, // XVCLO_B = 1766
18433
0
    CEFBS_None, // XVCLO_D = 1767
18434
0
    CEFBS_None, // XVCLO_H = 1768
18435
0
    CEFBS_None, // XVCLO_W = 1769
18436
0
    CEFBS_None, // XVCLZ_B = 1770
18437
0
    CEFBS_None, // XVCLZ_D = 1771
18438
0
    CEFBS_None, // XVCLZ_H = 1772
18439
0
    CEFBS_None, // XVCLZ_W = 1773
18440
0
    CEFBS_None, // XVDIV_B = 1774
18441
0
    CEFBS_None, // XVDIV_BU = 1775
18442
0
    CEFBS_None, // XVDIV_D = 1776
18443
0
    CEFBS_None, // XVDIV_DU = 1777
18444
0
    CEFBS_None, // XVDIV_H = 1778
18445
0
    CEFBS_None, // XVDIV_HU = 1779
18446
0
    CEFBS_None, // XVDIV_W = 1780
18447
0
    CEFBS_None, // XVDIV_WU = 1781
18448
0
    CEFBS_None, // XVEXTH_DU_WU = 1782
18449
0
    CEFBS_None, // XVEXTH_D_W = 1783
18450
0
    CEFBS_None, // XVEXTH_HU_BU = 1784
18451
0
    CEFBS_None, // XVEXTH_H_B = 1785
18452
0
    CEFBS_None, // XVEXTH_QU_DU = 1786
18453
0
    CEFBS_None, // XVEXTH_Q_D = 1787
18454
0
    CEFBS_None, // XVEXTH_WU_HU = 1788
18455
0
    CEFBS_None, // XVEXTH_W_H = 1789
18456
0
    CEFBS_None, // XVEXTL_QU_DU = 1790
18457
0
    CEFBS_None, // XVEXTL_Q_D = 1791
18458
0
    CEFBS_None, // XVEXTRINS_B = 1792
18459
0
    CEFBS_None, // XVEXTRINS_D = 1793
18460
0
    CEFBS_None, // XVEXTRINS_H = 1794
18461
0
    CEFBS_None, // XVEXTRINS_W = 1795
18462
0
    CEFBS_None, // XVFADD_D = 1796
18463
0
    CEFBS_None, // XVFADD_S = 1797
18464
0
    CEFBS_None, // XVFCLASS_D = 1798
18465
0
    CEFBS_None, // XVFCLASS_S = 1799
18466
0
    CEFBS_None, // XVFCMP_CAF_D = 1800
18467
0
    CEFBS_None, // XVFCMP_CAF_S = 1801
18468
0
    CEFBS_None, // XVFCMP_CEQ_D = 1802
18469
0
    CEFBS_None, // XVFCMP_CEQ_S = 1803
18470
0
    CEFBS_None, // XVFCMP_CLE_D = 1804
18471
0
    CEFBS_None, // XVFCMP_CLE_S = 1805
18472
0
    CEFBS_None, // XVFCMP_CLT_D = 1806
18473
0
    CEFBS_None, // XVFCMP_CLT_S = 1807
18474
0
    CEFBS_None, // XVFCMP_CNE_D = 1808
18475
0
    CEFBS_None, // XVFCMP_CNE_S = 1809
18476
0
    CEFBS_None, // XVFCMP_COR_D = 1810
18477
0
    CEFBS_None, // XVFCMP_COR_S = 1811
18478
0
    CEFBS_None, // XVFCMP_CUEQ_D = 1812
18479
0
    CEFBS_None, // XVFCMP_CUEQ_S = 1813
18480
0
    CEFBS_None, // XVFCMP_CULE_D = 1814
18481
0
    CEFBS_None, // XVFCMP_CULE_S = 1815
18482
0
    CEFBS_None, // XVFCMP_CULT_D = 1816
18483
0
    CEFBS_None, // XVFCMP_CULT_S = 1817
18484
0
    CEFBS_None, // XVFCMP_CUNE_D = 1818
18485
0
    CEFBS_None, // XVFCMP_CUNE_S = 1819
18486
0
    CEFBS_None, // XVFCMP_CUN_D = 1820
18487
0
    CEFBS_None, // XVFCMP_CUN_S = 1821
18488
0
    CEFBS_None, // XVFCMP_SAF_D = 1822
18489
0
    CEFBS_None, // XVFCMP_SAF_S = 1823
18490
0
    CEFBS_None, // XVFCMP_SEQ_D = 1824
18491
0
    CEFBS_None, // XVFCMP_SEQ_S = 1825
18492
0
    CEFBS_None, // XVFCMP_SLE_D = 1826
18493
0
    CEFBS_None, // XVFCMP_SLE_S = 1827
18494
0
    CEFBS_None, // XVFCMP_SLT_D = 1828
18495
0
    CEFBS_None, // XVFCMP_SLT_S = 1829
18496
0
    CEFBS_None, // XVFCMP_SNE_D = 1830
18497
0
    CEFBS_None, // XVFCMP_SNE_S = 1831
18498
0
    CEFBS_None, // XVFCMP_SOR_D = 1832
18499
0
    CEFBS_None, // XVFCMP_SOR_S = 1833
18500
0
    CEFBS_None, // XVFCMP_SUEQ_D = 1834
18501
0
    CEFBS_None, // XVFCMP_SUEQ_S = 1835
18502
0
    CEFBS_None, // XVFCMP_SULE_D = 1836
18503
0
    CEFBS_None, // XVFCMP_SULE_S = 1837
18504
0
    CEFBS_None, // XVFCMP_SULT_D = 1838
18505
0
    CEFBS_None, // XVFCMP_SULT_S = 1839
18506
0
    CEFBS_None, // XVFCMP_SUNE_D = 1840
18507
0
    CEFBS_None, // XVFCMP_SUNE_S = 1841
18508
0
    CEFBS_None, // XVFCMP_SUN_D = 1842
18509
0
    CEFBS_None, // XVFCMP_SUN_S = 1843
18510
0
    CEFBS_None, // XVFCVTH_D_S = 1844
18511
0
    CEFBS_None, // XVFCVTH_S_H = 1845
18512
0
    CEFBS_None, // XVFCVTL_D_S = 1846
18513
0
    CEFBS_None, // XVFCVTL_S_H = 1847
18514
0
    CEFBS_None, // XVFCVT_H_S = 1848
18515
0
    CEFBS_None, // XVFCVT_S_D = 1849
18516
0
    CEFBS_None, // XVFDIV_D = 1850
18517
0
    CEFBS_None, // XVFDIV_S = 1851
18518
0
    CEFBS_None, // XVFFINTH_D_W = 1852
18519
0
    CEFBS_None, // XVFFINTL_D_W = 1853
18520
0
    CEFBS_None, // XVFFINT_D_L = 1854
18521
0
    CEFBS_None, // XVFFINT_D_LU = 1855
18522
0
    CEFBS_None, // XVFFINT_S_L = 1856
18523
0
    CEFBS_None, // XVFFINT_S_W = 1857
18524
0
    CEFBS_None, // XVFFINT_S_WU = 1858
18525
0
    CEFBS_None, // XVFLOGB_D = 1859
18526
0
    CEFBS_None, // XVFLOGB_S = 1860
18527
0
    CEFBS_None, // XVFMADD_D = 1861
18528
0
    CEFBS_None, // XVFMADD_S = 1862
18529
0
    CEFBS_None, // XVFMAXA_D = 1863
18530
0
    CEFBS_None, // XVFMAXA_S = 1864
18531
0
    CEFBS_None, // XVFMAX_D = 1865
18532
0
    CEFBS_None, // XVFMAX_S = 1866
18533
0
    CEFBS_None, // XVFMINA_D = 1867
18534
0
    CEFBS_None, // XVFMINA_S = 1868
18535
0
    CEFBS_None, // XVFMIN_D = 1869
18536
0
    CEFBS_None, // XVFMIN_S = 1870
18537
0
    CEFBS_None, // XVFMSUB_D = 1871
18538
0
    CEFBS_None, // XVFMSUB_S = 1872
18539
0
    CEFBS_None, // XVFMUL_D = 1873
18540
0
    CEFBS_None, // XVFMUL_S = 1874
18541
0
    CEFBS_None, // XVFNMADD_D = 1875
18542
0
    CEFBS_None, // XVFNMADD_S = 1876
18543
0
    CEFBS_None, // XVFNMSUB_D = 1877
18544
0
    CEFBS_None, // XVFNMSUB_S = 1878
18545
0
    CEFBS_None, // XVFRECIPE_D = 1879
18546
0
    CEFBS_None, // XVFRECIPE_S = 1880
18547
0
    CEFBS_None, // XVFRECIP_D = 1881
18548
0
    CEFBS_None, // XVFRECIP_S = 1882
18549
0
    CEFBS_None, // XVFRINTRM_D = 1883
18550
0
    CEFBS_None, // XVFRINTRM_S = 1884
18551
0
    CEFBS_None, // XVFRINTRNE_D = 1885
18552
0
    CEFBS_None, // XVFRINTRNE_S = 1886
18553
0
    CEFBS_None, // XVFRINTRP_D = 1887
18554
0
    CEFBS_None, // XVFRINTRP_S = 1888
18555
0
    CEFBS_None, // XVFRINTRZ_D = 1889
18556
0
    CEFBS_None, // XVFRINTRZ_S = 1890
18557
0
    CEFBS_None, // XVFRINT_D = 1891
18558
0
    CEFBS_None, // XVFRINT_S = 1892
18559
0
    CEFBS_None, // XVFRSQRTE_D = 1893
18560
0
    CEFBS_None, // XVFRSQRTE_S = 1894
18561
0
    CEFBS_None, // XVFRSQRT_D = 1895
18562
0
    CEFBS_None, // XVFRSQRT_S = 1896
18563
0
    CEFBS_None, // XVFRSTPI_B = 1897
18564
0
    CEFBS_None, // XVFRSTPI_H = 1898
18565
0
    CEFBS_None, // XVFRSTP_B = 1899
18566
0
    CEFBS_None, // XVFRSTP_H = 1900
18567
0
    CEFBS_None, // XVFSQRT_D = 1901
18568
0
    CEFBS_None, // XVFSQRT_S = 1902
18569
0
    CEFBS_None, // XVFSUB_D = 1903
18570
0
    CEFBS_None, // XVFSUB_S = 1904
18571
0
    CEFBS_None, // XVFTINTH_L_S = 1905
18572
0
    CEFBS_None, // XVFTINTL_L_S = 1906
18573
0
    CEFBS_None, // XVFTINTRMH_L_S = 1907
18574
0
    CEFBS_None, // XVFTINTRML_L_S = 1908
18575
0
    CEFBS_None, // XVFTINTRM_L_D = 1909
18576
0
    CEFBS_None, // XVFTINTRM_W_D = 1910
18577
0
    CEFBS_None, // XVFTINTRM_W_S = 1911
18578
0
    CEFBS_None, // XVFTINTRNEH_L_S = 1912
18579
0
    CEFBS_None, // XVFTINTRNEL_L_S = 1913
18580
0
    CEFBS_None, // XVFTINTRNE_L_D = 1914
18581
0
    CEFBS_None, // XVFTINTRNE_W_D = 1915
18582
0
    CEFBS_None, // XVFTINTRNE_W_S = 1916
18583
0
    CEFBS_None, // XVFTINTRPH_L_S = 1917
18584
0
    CEFBS_None, // XVFTINTRPL_L_S = 1918
18585
0
    CEFBS_None, // XVFTINTRP_L_D = 1919
18586
0
    CEFBS_None, // XVFTINTRP_W_D = 1920
18587
0
    CEFBS_None, // XVFTINTRP_W_S = 1921
18588
0
    CEFBS_None, // XVFTINTRZH_L_S = 1922
18589
0
    CEFBS_None, // XVFTINTRZL_L_S = 1923
18590
0
    CEFBS_None, // XVFTINTRZ_LU_D = 1924
18591
0
    CEFBS_None, // XVFTINTRZ_L_D = 1925
18592
0
    CEFBS_None, // XVFTINTRZ_WU_S = 1926
18593
0
    CEFBS_None, // XVFTINTRZ_W_D = 1927
18594
0
    CEFBS_None, // XVFTINTRZ_W_S = 1928
18595
0
    CEFBS_None, // XVFTINT_LU_D = 1929
18596
0
    CEFBS_None, // XVFTINT_L_D = 1930
18597
0
    CEFBS_None, // XVFTINT_WU_S = 1931
18598
0
    CEFBS_None, // XVFTINT_W_D = 1932
18599
0
    CEFBS_None, // XVFTINT_W_S = 1933
18600
0
    CEFBS_None, // XVHADDW_DU_WU = 1934
18601
0
    CEFBS_None, // XVHADDW_D_W = 1935
18602
0
    CEFBS_None, // XVHADDW_HU_BU = 1936
18603
0
    CEFBS_None, // XVHADDW_H_B = 1937
18604
0
    CEFBS_None, // XVHADDW_QU_DU = 1938
18605
0
    CEFBS_None, // XVHADDW_Q_D = 1939
18606
0
    CEFBS_None, // XVHADDW_WU_HU = 1940
18607
0
    CEFBS_None, // XVHADDW_W_H = 1941
18608
0
    CEFBS_None, // XVHSELI_D = 1942
18609
0
    CEFBS_None, // XVHSUBW_DU_WU = 1943
18610
0
    CEFBS_None, // XVHSUBW_D_W = 1944
18611
0
    CEFBS_None, // XVHSUBW_HU_BU = 1945
18612
0
    CEFBS_None, // XVHSUBW_H_B = 1946
18613
0
    CEFBS_None, // XVHSUBW_QU_DU = 1947
18614
0
    CEFBS_None, // XVHSUBW_Q_D = 1948
18615
0
    CEFBS_None, // XVHSUBW_WU_HU = 1949
18616
0
    CEFBS_None, // XVHSUBW_W_H = 1950
18617
0
    CEFBS_None, // XVILVH_B = 1951
18618
0
    CEFBS_None, // XVILVH_D = 1952
18619
0
    CEFBS_None, // XVILVH_H = 1953
18620
0
    CEFBS_None, // XVILVH_W = 1954
18621
0
    CEFBS_None, // XVILVL_B = 1955
18622
0
    CEFBS_None, // XVILVL_D = 1956
18623
0
    CEFBS_None, // XVILVL_H = 1957
18624
0
    CEFBS_None, // XVILVL_W = 1958
18625
0
    CEFBS_None, // XVINSGR2VR_D = 1959
18626
0
    CEFBS_None, // XVINSGR2VR_W = 1960
18627
0
    CEFBS_None, // XVINSVE0_D = 1961
18628
0
    CEFBS_None, // XVINSVE0_W = 1962
18629
0
    CEFBS_None, // XVLD = 1963
18630
0
    CEFBS_None, // XVLDI = 1964
18631
0
    CEFBS_None, // XVLDREPL_B = 1965
18632
0
    CEFBS_None, // XVLDREPL_D = 1966
18633
0
    CEFBS_None, // XVLDREPL_H = 1967
18634
0
    CEFBS_None, // XVLDREPL_W = 1968
18635
0
    CEFBS_None, // XVLDX = 1969
18636
0
    CEFBS_None, // XVMADDWEV_D_W = 1970
18637
0
    CEFBS_None, // XVMADDWEV_D_WU = 1971
18638
0
    CEFBS_None, // XVMADDWEV_D_WU_W = 1972
18639
0
    CEFBS_None, // XVMADDWEV_H_B = 1973
18640
0
    CEFBS_None, // XVMADDWEV_H_BU = 1974
18641
0
    CEFBS_None, // XVMADDWEV_H_BU_B = 1975
18642
0
    CEFBS_None, // XVMADDWEV_Q_D = 1976
18643
0
    CEFBS_None, // XVMADDWEV_Q_DU = 1977
18644
0
    CEFBS_None, // XVMADDWEV_Q_DU_D = 1978
18645
0
    CEFBS_None, // XVMADDWEV_W_H = 1979
18646
0
    CEFBS_None, // XVMADDWEV_W_HU = 1980
18647
0
    CEFBS_None, // XVMADDWEV_W_HU_H = 1981
18648
0
    CEFBS_None, // XVMADDWOD_D_W = 1982
18649
0
    CEFBS_None, // XVMADDWOD_D_WU = 1983
18650
0
    CEFBS_None, // XVMADDWOD_D_WU_W = 1984
18651
0
    CEFBS_None, // XVMADDWOD_H_B = 1985
18652
0
    CEFBS_None, // XVMADDWOD_H_BU = 1986
18653
0
    CEFBS_None, // XVMADDWOD_H_BU_B = 1987
18654
0
    CEFBS_None, // XVMADDWOD_Q_D = 1988
18655
0
    CEFBS_None, // XVMADDWOD_Q_DU = 1989
18656
0
    CEFBS_None, // XVMADDWOD_Q_DU_D = 1990
18657
0
    CEFBS_None, // XVMADDWOD_W_H = 1991
18658
0
    CEFBS_None, // XVMADDWOD_W_HU = 1992
18659
0
    CEFBS_None, // XVMADDWOD_W_HU_H = 1993
18660
0
    CEFBS_None, // XVMADD_B = 1994
18661
0
    CEFBS_None, // XVMADD_D = 1995
18662
0
    CEFBS_None, // XVMADD_H = 1996
18663
0
    CEFBS_None, // XVMADD_W = 1997
18664
0
    CEFBS_None, // XVMAXI_B = 1998
18665
0
    CEFBS_None, // XVMAXI_BU = 1999
18666
0
    CEFBS_None, // XVMAXI_D = 2000
18667
0
    CEFBS_None, // XVMAXI_DU = 2001
18668
0
    CEFBS_None, // XVMAXI_H = 2002
18669
0
    CEFBS_None, // XVMAXI_HU = 2003
18670
0
    CEFBS_None, // XVMAXI_W = 2004
18671
0
    CEFBS_None, // XVMAXI_WU = 2005
18672
0
    CEFBS_None, // XVMAX_B = 2006
18673
0
    CEFBS_None, // XVMAX_BU = 2007
18674
0
    CEFBS_None, // XVMAX_D = 2008
18675
0
    CEFBS_None, // XVMAX_DU = 2009
18676
0
    CEFBS_None, // XVMAX_H = 2010
18677
0
    CEFBS_None, // XVMAX_HU = 2011
18678
0
    CEFBS_None, // XVMAX_W = 2012
18679
0
    CEFBS_None, // XVMAX_WU = 2013
18680
0
    CEFBS_None, // XVMINI_B = 2014
18681
0
    CEFBS_None, // XVMINI_BU = 2015
18682
0
    CEFBS_None, // XVMINI_D = 2016
18683
0
    CEFBS_None, // XVMINI_DU = 2017
18684
0
    CEFBS_None, // XVMINI_H = 2018
18685
0
    CEFBS_None, // XVMINI_HU = 2019
18686
0
    CEFBS_None, // XVMINI_W = 2020
18687
0
    CEFBS_None, // XVMINI_WU = 2021
18688
0
    CEFBS_None, // XVMIN_B = 2022
18689
0
    CEFBS_None, // XVMIN_BU = 2023
18690
0
    CEFBS_None, // XVMIN_D = 2024
18691
0
    CEFBS_None, // XVMIN_DU = 2025
18692
0
    CEFBS_None, // XVMIN_H = 2026
18693
0
    CEFBS_None, // XVMIN_HU = 2027
18694
0
    CEFBS_None, // XVMIN_W = 2028
18695
0
    CEFBS_None, // XVMIN_WU = 2029
18696
0
    CEFBS_None, // XVMOD_B = 2030
18697
0
    CEFBS_None, // XVMOD_BU = 2031
18698
0
    CEFBS_None, // XVMOD_D = 2032
18699
0
    CEFBS_None, // XVMOD_DU = 2033
18700
0
    CEFBS_None, // XVMOD_H = 2034
18701
0
    CEFBS_None, // XVMOD_HU = 2035
18702
0
    CEFBS_None, // XVMOD_W = 2036
18703
0
    CEFBS_None, // XVMOD_WU = 2037
18704
0
    CEFBS_None, // XVMSKGEZ_B = 2038
18705
0
    CEFBS_None, // XVMSKLTZ_B = 2039
18706
0
    CEFBS_None, // XVMSKLTZ_D = 2040
18707
0
    CEFBS_None, // XVMSKLTZ_H = 2041
18708
0
    CEFBS_None, // XVMSKLTZ_W = 2042
18709
0
    CEFBS_None, // XVMSKNZ_B = 2043
18710
0
    CEFBS_None, // XVMSUB_B = 2044
18711
0
    CEFBS_None, // XVMSUB_D = 2045
18712
0
    CEFBS_None, // XVMSUB_H = 2046
18713
0
    CEFBS_None, // XVMSUB_W = 2047
18714
0
    CEFBS_None, // XVMUH_B = 2048
18715
0
    CEFBS_None, // XVMUH_BU = 2049
18716
0
    CEFBS_None, // XVMUH_D = 2050
18717
0
    CEFBS_None, // XVMUH_DU = 2051
18718
0
    CEFBS_None, // XVMUH_H = 2052
18719
0
    CEFBS_None, // XVMUH_HU = 2053
18720
0
    CEFBS_None, // XVMUH_W = 2054
18721
0
    CEFBS_None, // XVMUH_WU = 2055
18722
0
    CEFBS_None, // XVMULWEV_D_W = 2056
18723
0
    CEFBS_None, // XVMULWEV_D_WU = 2057
18724
0
    CEFBS_None, // XVMULWEV_D_WU_W = 2058
18725
0
    CEFBS_None, // XVMULWEV_H_B = 2059
18726
0
    CEFBS_None, // XVMULWEV_H_BU = 2060
18727
0
    CEFBS_None, // XVMULWEV_H_BU_B = 2061
18728
0
    CEFBS_None, // XVMULWEV_Q_D = 2062
18729
0
    CEFBS_None, // XVMULWEV_Q_DU = 2063
18730
0
    CEFBS_None, // XVMULWEV_Q_DU_D = 2064
18731
0
    CEFBS_None, // XVMULWEV_W_H = 2065
18732
0
    CEFBS_None, // XVMULWEV_W_HU = 2066
18733
0
    CEFBS_None, // XVMULWEV_W_HU_H = 2067
18734
0
    CEFBS_None, // XVMULWOD_D_W = 2068
18735
0
    CEFBS_None, // XVMULWOD_D_WU = 2069
18736
0
    CEFBS_None, // XVMULWOD_D_WU_W = 2070
18737
0
    CEFBS_None, // XVMULWOD_H_B = 2071
18738
0
    CEFBS_None, // XVMULWOD_H_BU = 2072
18739
0
    CEFBS_None, // XVMULWOD_H_BU_B = 2073
18740
0
    CEFBS_None, // XVMULWOD_Q_D = 2074
18741
0
    CEFBS_None, // XVMULWOD_Q_DU = 2075
18742
0
    CEFBS_None, // XVMULWOD_Q_DU_D = 2076
18743
0
    CEFBS_None, // XVMULWOD_W_H = 2077
18744
0
    CEFBS_None, // XVMULWOD_W_HU = 2078
18745
0
    CEFBS_None, // XVMULWOD_W_HU_H = 2079
18746
0
    CEFBS_None, // XVMUL_B = 2080
18747
0
    CEFBS_None, // XVMUL_D = 2081
18748
0
    CEFBS_None, // XVMUL_H = 2082
18749
0
    CEFBS_None, // XVMUL_W = 2083
18750
0
    CEFBS_None, // XVNEG_B = 2084
18751
0
    CEFBS_None, // XVNEG_D = 2085
18752
0
    CEFBS_None, // XVNEG_H = 2086
18753
0
    CEFBS_None, // XVNEG_W = 2087
18754
0
    CEFBS_None, // XVNORI_B = 2088
18755
0
    CEFBS_None, // XVNOR_V = 2089
18756
0
    CEFBS_None, // XVORI_B = 2090
18757
0
    CEFBS_None, // XVORN_V = 2091
18758
0
    CEFBS_None, // XVOR_V = 2092
18759
0
    CEFBS_None, // XVPACKEV_B = 2093
18760
0
    CEFBS_None, // XVPACKEV_D = 2094
18761
0
    CEFBS_None, // XVPACKEV_H = 2095
18762
0
    CEFBS_None, // XVPACKEV_W = 2096
18763
0
    CEFBS_None, // XVPACKOD_B = 2097
18764
0
    CEFBS_None, // XVPACKOD_D = 2098
18765
0
    CEFBS_None, // XVPACKOD_H = 2099
18766
0
    CEFBS_None, // XVPACKOD_W = 2100
18767
0
    CEFBS_None, // XVPCNT_B = 2101
18768
0
    CEFBS_None, // XVPCNT_D = 2102
18769
0
    CEFBS_None, // XVPCNT_H = 2103
18770
0
    CEFBS_None, // XVPCNT_W = 2104
18771
0
    CEFBS_None, // XVPERMI_D = 2105
18772
0
    CEFBS_None, // XVPERMI_Q = 2106
18773
0
    CEFBS_None, // XVPERMI_W = 2107
18774
0
    CEFBS_None, // XVPERM_W = 2108
18775
0
    CEFBS_None, // XVPICKEV_B = 2109
18776
0
    CEFBS_None, // XVPICKEV_D = 2110
18777
0
    CEFBS_None, // XVPICKEV_H = 2111
18778
0
    CEFBS_None, // XVPICKEV_W = 2112
18779
0
    CEFBS_None, // XVPICKOD_B = 2113
18780
0
    CEFBS_None, // XVPICKOD_D = 2114
18781
0
    CEFBS_None, // XVPICKOD_H = 2115
18782
0
    CEFBS_None, // XVPICKOD_W = 2116
18783
0
    CEFBS_None, // XVPICKVE2GR_D = 2117
18784
0
    CEFBS_None, // XVPICKVE2GR_DU = 2118
18785
0
    CEFBS_None, // XVPICKVE2GR_W = 2119
18786
0
    CEFBS_None, // XVPICKVE2GR_WU = 2120
18787
0
    CEFBS_None, // XVPICKVE_D = 2121
18788
0
    CEFBS_None, // XVPICKVE_W = 2122
18789
0
    CEFBS_None, // XVREPL128VEI_B = 2123
18790
0
    CEFBS_None, // XVREPL128VEI_D = 2124
18791
0
    CEFBS_None, // XVREPL128VEI_H = 2125
18792
0
    CEFBS_None, // XVREPL128VEI_W = 2126
18793
0
    CEFBS_None, // XVREPLGR2VR_B = 2127
18794
0
    CEFBS_None, // XVREPLGR2VR_D = 2128
18795
0
    CEFBS_None, // XVREPLGR2VR_H = 2129
18796
0
    CEFBS_None, // XVREPLGR2VR_W = 2130
18797
0
    CEFBS_None, // XVREPLVE0_B = 2131
18798
0
    CEFBS_None, // XVREPLVE0_D = 2132
18799
0
    CEFBS_None, // XVREPLVE0_H = 2133
18800
0
    CEFBS_None, // XVREPLVE0_Q = 2134
18801
0
    CEFBS_None, // XVREPLVE0_W = 2135
18802
0
    CEFBS_None, // XVREPLVE_B = 2136
18803
0
    CEFBS_None, // XVREPLVE_D = 2137
18804
0
    CEFBS_None, // XVREPLVE_H = 2138
18805
0
    CEFBS_None, // XVREPLVE_W = 2139
18806
0
    CEFBS_None, // XVROTRI_B = 2140
18807
0
    CEFBS_None, // XVROTRI_D = 2141
18808
0
    CEFBS_None, // XVROTRI_H = 2142
18809
0
    CEFBS_None, // XVROTRI_W = 2143
18810
0
    CEFBS_None, // XVROTR_B = 2144
18811
0
    CEFBS_None, // XVROTR_D = 2145
18812
0
    CEFBS_None, // XVROTR_H = 2146
18813
0
    CEFBS_None, // XVROTR_W = 2147
18814
0
    CEFBS_None, // XVSADD_B = 2148
18815
0
    CEFBS_None, // XVSADD_BU = 2149
18816
0
    CEFBS_None, // XVSADD_D = 2150
18817
0
    CEFBS_None, // XVSADD_DU = 2151
18818
0
    CEFBS_None, // XVSADD_H = 2152
18819
0
    CEFBS_None, // XVSADD_HU = 2153
18820
0
    CEFBS_None, // XVSADD_W = 2154
18821
0
    CEFBS_None, // XVSADD_WU = 2155
18822
0
    CEFBS_None, // XVSAT_B = 2156
18823
0
    CEFBS_None, // XVSAT_BU = 2157
18824
0
    CEFBS_None, // XVSAT_D = 2158
18825
0
    CEFBS_None, // XVSAT_DU = 2159
18826
0
    CEFBS_None, // XVSAT_H = 2160
18827
0
    CEFBS_None, // XVSAT_HU = 2161
18828
0
    CEFBS_None, // XVSAT_W = 2162
18829
0
    CEFBS_None, // XVSAT_WU = 2163
18830
0
    CEFBS_None, // XVSEQI_B = 2164
18831
0
    CEFBS_None, // XVSEQI_D = 2165
18832
0
    CEFBS_None, // XVSEQI_H = 2166
18833
0
    CEFBS_None, // XVSEQI_W = 2167
18834
0
    CEFBS_None, // XVSEQ_B = 2168
18835
0
    CEFBS_None, // XVSEQ_D = 2169
18836
0
    CEFBS_None, // XVSEQ_H = 2170
18837
0
    CEFBS_None, // XVSEQ_W = 2171
18838
0
    CEFBS_None, // XVSETALLNEZ_B = 2172
18839
0
    CEFBS_None, // XVSETALLNEZ_D = 2173
18840
0
    CEFBS_None, // XVSETALLNEZ_H = 2174
18841
0
    CEFBS_None, // XVSETALLNEZ_W = 2175
18842
0
    CEFBS_None, // XVSETANYEQZ_B = 2176
18843
0
    CEFBS_None, // XVSETANYEQZ_D = 2177
18844
0
    CEFBS_None, // XVSETANYEQZ_H = 2178
18845
0
    CEFBS_None, // XVSETANYEQZ_W = 2179
18846
0
    CEFBS_None, // XVSETEQZ_V = 2180
18847
0
    CEFBS_None, // XVSETNEZ_V = 2181
18848
0
    CEFBS_None, // XVSHUF4I_B = 2182
18849
0
    CEFBS_None, // XVSHUF4I_D = 2183
18850
0
    CEFBS_None, // XVSHUF4I_H = 2184
18851
0
    CEFBS_None, // XVSHUF4I_W = 2185
18852
0
    CEFBS_None, // XVSHUF_B = 2186
18853
0
    CEFBS_None, // XVSHUF_D = 2187
18854
0
    CEFBS_None, // XVSHUF_H = 2188
18855
0
    CEFBS_None, // XVSHUF_W = 2189
18856
0
    CEFBS_None, // XVSIGNCOV_B = 2190
18857
0
    CEFBS_None, // XVSIGNCOV_D = 2191
18858
0
    CEFBS_None, // XVSIGNCOV_H = 2192
18859
0
    CEFBS_None, // XVSIGNCOV_W = 2193
18860
0
    CEFBS_None, // XVSLEI_B = 2194
18861
0
    CEFBS_None, // XVSLEI_BU = 2195
18862
0
    CEFBS_None, // XVSLEI_D = 2196
18863
0
    CEFBS_None, // XVSLEI_DU = 2197
18864
0
    CEFBS_None, // XVSLEI_H = 2198
18865
0
    CEFBS_None, // XVSLEI_HU = 2199
18866
0
    CEFBS_None, // XVSLEI_W = 2200
18867
0
    CEFBS_None, // XVSLEI_WU = 2201
18868
0
    CEFBS_None, // XVSLE_B = 2202
18869
0
    CEFBS_None, // XVSLE_BU = 2203
18870
0
    CEFBS_None, // XVSLE_D = 2204
18871
0
    CEFBS_None, // XVSLE_DU = 2205
18872
0
    CEFBS_None, // XVSLE_H = 2206
18873
0
    CEFBS_None, // XVSLE_HU = 2207
18874
0
    CEFBS_None, // XVSLE_W = 2208
18875
0
    CEFBS_None, // XVSLE_WU = 2209
18876
0
    CEFBS_None, // XVSLLI_B = 2210
18877
0
    CEFBS_None, // XVSLLI_D = 2211
18878
0
    CEFBS_None, // XVSLLI_H = 2212
18879
0
    CEFBS_None, // XVSLLI_W = 2213
18880
0
    CEFBS_None, // XVSLLWIL_DU_WU = 2214
18881
0
    CEFBS_None, // XVSLLWIL_D_W = 2215
18882
0
    CEFBS_None, // XVSLLWIL_HU_BU = 2216
18883
0
    CEFBS_None, // XVSLLWIL_H_B = 2217
18884
0
    CEFBS_None, // XVSLLWIL_WU_HU = 2218
18885
0
    CEFBS_None, // XVSLLWIL_W_H = 2219
18886
0
    CEFBS_None, // XVSLL_B = 2220
18887
0
    CEFBS_None, // XVSLL_D = 2221
18888
0
    CEFBS_None, // XVSLL_H = 2222
18889
0
    CEFBS_None, // XVSLL_W = 2223
18890
0
    CEFBS_None, // XVSLTI_B = 2224
18891
0
    CEFBS_None, // XVSLTI_BU = 2225
18892
0
    CEFBS_None, // XVSLTI_D = 2226
18893
0
    CEFBS_None, // XVSLTI_DU = 2227
18894
0
    CEFBS_None, // XVSLTI_H = 2228
18895
0
    CEFBS_None, // XVSLTI_HU = 2229
18896
0
    CEFBS_None, // XVSLTI_W = 2230
18897
0
    CEFBS_None, // XVSLTI_WU = 2231
18898
0
    CEFBS_None, // XVSLT_B = 2232
18899
0
    CEFBS_None, // XVSLT_BU = 2233
18900
0
    CEFBS_None, // XVSLT_D = 2234
18901
0
    CEFBS_None, // XVSLT_DU = 2235
18902
0
    CEFBS_None, // XVSLT_H = 2236
18903
0
    CEFBS_None, // XVSLT_HU = 2237
18904
0
    CEFBS_None, // XVSLT_W = 2238
18905
0
    CEFBS_None, // XVSLT_WU = 2239
18906
0
    CEFBS_None, // XVSRAI_B = 2240
18907
0
    CEFBS_None, // XVSRAI_D = 2241
18908
0
    CEFBS_None, // XVSRAI_H = 2242
18909
0
    CEFBS_None, // XVSRAI_W = 2243
18910
0
    CEFBS_None, // XVSRANI_B_H = 2244
18911
0
    CEFBS_None, // XVSRANI_D_Q = 2245
18912
0
    CEFBS_None, // XVSRANI_H_W = 2246
18913
0
    CEFBS_None, // XVSRANI_W_D = 2247
18914
0
    CEFBS_None, // XVSRAN_B_H = 2248
18915
0
    CEFBS_None, // XVSRAN_H_W = 2249
18916
0
    CEFBS_None, // XVSRAN_W_D = 2250
18917
0
    CEFBS_None, // XVSRARI_B = 2251
18918
0
    CEFBS_None, // XVSRARI_D = 2252
18919
0
    CEFBS_None, // XVSRARI_H = 2253
18920
0
    CEFBS_None, // XVSRARI_W = 2254
18921
0
    CEFBS_None, // XVSRARNI_B_H = 2255
18922
0
    CEFBS_None, // XVSRARNI_D_Q = 2256
18923
0
    CEFBS_None, // XVSRARNI_H_W = 2257
18924
0
    CEFBS_None, // XVSRARNI_W_D = 2258
18925
0
    CEFBS_None, // XVSRARN_B_H = 2259
18926
0
    CEFBS_None, // XVSRARN_H_W = 2260
18927
0
    CEFBS_None, // XVSRARN_W_D = 2261
18928
0
    CEFBS_None, // XVSRAR_B = 2262
18929
0
    CEFBS_None, // XVSRAR_D = 2263
18930
0
    CEFBS_None, // XVSRAR_H = 2264
18931
0
    CEFBS_None, // XVSRAR_W = 2265
18932
0
    CEFBS_None, // XVSRA_B = 2266
18933
0
    CEFBS_None, // XVSRA_D = 2267
18934
0
    CEFBS_None, // XVSRA_H = 2268
18935
0
    CEFBS_None, // XVSRA_W = 2269
18936
0
    CEFBS_None, // XVSRLI_B = 2270
18937
0
    CEFBS_None, // XVSRLI_D = 2271
18938
0
    CEFBS_None, // XVSRLI_H = 2272
18939
0
    CEFBS_None, // XVSRLI_W = 2273
18940
0
    CEFBS_None, // XVSRLNI_B_H = 2274
18941
0
    CEFBS_None, // XVSRLNI_D_Q = 2275
18942
0
    CEFBS_None, // XVSRLNI_H_W = 2276
18943
0
    CEFBS_None, // XVSRLNI_W_D = 2277
18944
0
    CEFBS_None, // XVSRLN_B_H = 2278
18945
0
    CEFBS_None, // XVSRLN_H_W = 2279
18946
0
    CEFBS_None, // XVSRLN_W_D = 2280
18947
0
    CEFBS_None, // XVSRLRI_B = 2281
18948
0
    CEFBS_None, // XVSRLRI_D = 2282
18949
0
    CEFBS_None, // XVSRLRI_H = 2283
18950
0
    CEFBS_None, // XVSRLRI_W = 2284
18951
0
    CEFBS_None, // XVSRLRNI_B_H = 2285
18952
0
    CEFBS_None, // XVSRLRNI_D_Q = 2286
18953
0
    CEFBS_None, // XVSRLRNI_H_W = 2287
18954
0
    CEFBS_None, // XVSRLRNI_W_D = 2288
18955
0
    CEFBS_None, // XVSRLRN_B_H = 2289
18956
0
    CEFBS_None, // XVSRLRN_H_W = 2290
18957
0
    CEFBS_None, // XVSRLRN_W_D = 2291
18958
0
    CEFBS_None, // XVSRLR_B = 2292
18959
0
    CEFBS_None, // XVSRLR_D = 2293
18960
0
    CEFBS_None, // XVSRLR_H = 2294
18961
0
    CEFBS_None, // XVSRLR_W = 2295
18962
0
    CEFBS_None, // XVSRL_B = 2296
18963
0
    CEFBS_None, // XVSRL_D = 2297
18964
0
    CEFBS_None, // XVSRL_H = 2298
18965
0
    CEFBS_None, // XVSRL_W = 2299
18966
0
    CEFBS_None, // XVSSRANI_BU_H = 2300
18967
0
    CEFBS_None, // XVSSRANI_B_H = 2301
18968
0
    CEFBS_None, // XVSSRANI_DU_Q = 2302
18969
0
    CEFBS_None, // XVSSRANI_D_Q = 2303
18970
0
    CEFBS_None, // XVSSRANI_HU_W = 2304
18971
0
    CEFBS_None, // XVSSRANI_H_W = 2305
18972
0
    CEFBS_None, // XVSSRANI_WU_D = 2306
18973
0
    CEFBS_None, // XVSSRANI_W_D = 2307
18974
0
    CEFBS_None, // XVSSRAN_BU_H = 2308
18975
0
    CEFBS_None, // XVSSRAN_B_H = 2309
18976
0
    CEFBS_None, // XVSSRAN_HU_W = 2310
18977
0
    CEFBS_None, // XVSSRAN_H_W = 2311
18978
0
    CEFBS_None, // XVSSRAN_WU_D = 2312
18979
0
    CEFBS_None, // XVSSRAN_W_D = 2313
18980
0
    CEFBS_None, // XVSSRARNI_BU_H = 2314
18981
0
    CEFBS_None, // XVSSRARNI_B_H = 2315
18982
0
    CEFBS_None, // XVSSRARNI_DU_Q = 2316
18983
0
    CEFBS_None, // XVSSRARNI_D_Q = 2317
18984
0
    CEFBS_None, // XVSSRARNI_HU_W = 2318
18985
0
    CEFBS_None, // XVSSRARNI_H_W = 2319
18986
0
    CEFBS_None, // XVSSRARNI_WU_D = 2320
18987
0
    CEFBS_None, // XVSSRARNI_W_D = 2321
18988
0
    CEFBS_None, // XVSSRARN_BU_H = 2322
18989
0
    CEFBS_None, // XVSSRARN_B_H = 2323
18990
0
    CEFBS_None, // XVSSRARN_HU_W = 2324
18991
0
    CEFBS_None, // XVSSRARN_H_W = 2325
18992
0
    CEFBS_None, // XVSSRARN_WU_D = 2326
18993
0
    CEFBS_None, // XVSSRARN_W_D = 2327
18994
0
    CEFBS_None, // XVSSRLNI_BU_H = 2328
18995
0
    CEFBS_None, // XVSSRLNI_B_H = 2329
18996
0
    CEFBS_None, // XVSSRLNI_DU_Q = 2330
18997
0
    CEFBS_None, // XVSSRLNI_D_Q = 2331
18998
0
    CEFBS_None, // XVSSRLNI_HU_W = 2332
18999
0
    CEFBS_None, // XVSSRLNI_H_W = 2333
19000
0
    CEFBS_None, // XVSSRLNI_WU_D = 2334
19001
0
    CEFBS_None, // XVSSRLNI_W_D = 2335
19002
0
    CEFBS_None, // XVSSRLN_BU_H = 2336
19003
0
    CEFBS_None, // XVSSRLN_B_H = 2337
19004
0
    CEFBS_None, // XVSSRLN_HU_W = 2338
19005
0
    CEFBS_None, // XVSSRLN_H_W = 2339
19006
0
    CEFBS_None, // XVSSRLN_WU_D = 2340
19007
0
    CEFBS_None, // XVSSRLN_W_D = 2341
19008
0
    CEFBS_None, // XVSSRLRNI_BU_H = 2342
19009
0
    CEFBS_None, // XVSSRLRNI_B_H = 2343
19010
0
    CEFBS_None, // XVSSRLRNI_DU_Q = 2344
19011
0
    CEFBS_None, // XVSSRLRNI_D_Q = 2345
19012
0
    CEFBS_None, // XVSSRLRNI_HU_W = 2346
19013
0
    CEFBS_None, // XVSSRLRNI_H_W = 2347
19014
0
    CEFBS_None, // XVSSRLRNI_WU_D = 2348
19015
0
    CEFBS_None, // XVSSRLRNI_W_D = 2349
19016
0
    CEFBS_None, // XVSSRLRN_BU_H = 2350
19017
0
    CEFBS_None, // XVSSRLRN_B_H = 2351
19018
0
    CEFBS_None, // XVSSRLRN_HU_W = 2352
19019
0
    CEFBS_None, // XVSSRLRN_H_W = 2353
19020
0
    CEFBS_None, // XVSSRLRN_WU_D = 2354
19021
0
    CEFBS_None, // XVSSRLRN_W_D = 2355
19022
0
    CEFBS_None, // XVSSUB_B = 2356
19023
0
    CEFBS_None, // XVSSUB_BU = 2357
19024
0
    CEFBS_None, // XVSSUB_D = 2358
19025
0
    CEFBS_None, // XVSSUB_DU = 2359
19026
0
    CEFBS_None, // XVSSUB_H = 2360
19027
0
    CEFBS_None, // XVSSUB_HU = 2361
19028
0
    CEFBS_None, // XVSSUB_W = 2362
19029
0
    CEFBS_None, // XVSSUB_WU = 2363
19030
0
    CEFBS_None, // XVST = 2364
19031
0
    CEFBS_None, // XVSTELM_B = 2365
19032
0
    CEFBS_None, // XVSTELM_D = 2366
19033
0
    CEFBS_None, // XVSTELM_H = 2367
19034
0
    CEFBS_None, // XVSTELM_W = 2368
19035
0
    CEFBS_None, // XVSTX = 2369
19036
0
    CEFBS_None, // XVSUBI_BU = 2370
19037
0
    CEFBS_None, // XVSUBI_DU = 2371
19038
0
    CEFBS_None, // XVSUBI_HU = 2372
19039
0
    CEFBS_None, // XVSUBI_WU = 2373
19040
0
    CEFBS_None, // XVSUBWEV_D_W = 2374
19041
0
    CEFBS_None, // XVSUBWEV_D_WU = 2375
19042
0
    CEFBS_None, // XVSUBWEV_H_B = 2376
19043
0
    CEFBS_None, // XVSUBWEV_H_BU = 2377
19044
0
    CEFBS_None, // XVSUBWEV_Q_D = 2378
19045
0
    CEFBS_None, // XVSUBWEV_Q_DU = 2379
19046
0
    CEFBS_None, // XVSUBWEV_W_H = 2380
19047
0
    CEFBS_None, // XVSUBWEV_W_HU = 2381
19048
0
    CEFBS_None, // XVSUBWOD_D_W = 2382
19049
0
    CEFBS_None, // XVSUBWOD_D_WU = 2383
19050
0
    CEFBS_None, // XVSUBWOD_H_B = 2384
19051
0
    CEFBS_None, // XVSUBWOD_H_BU = 2385
19052
0
    CEFBS_None, // XVSUBWOD_Q_D = 2386
19053
0
    CEFBS_None, // XVSUBWOD_Q_DU = 2387
19054
0
    CEFBS_None, // XVSUBWOD_W_H = 2388
19055
0
    CEFBS_None, // XVSUBWOD_W_HU = 2389
19056
0
    CEFBS_None, // XVSUB_B = 2390
19057
0
    CEFBS_None, // XVSUB_D = 2391
19058
0
    CEFBS_None, // XVSUB_H = 2392
19059
0
    CEFBS_None, // XVSUB_Q = 2393
19060
0
    CEFBS_None, // XVSUB_W = 2394
19061
0
    CEFBS_None, // XVXORI_B = 2395
19062
0
    CEFBS_None, // XVXOR_V = 2396
19063
0
  };
19064
19065
0
  assert(Opcode < 2397);
19066
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
19067
0
}
19068
19069
} // end namespace LoongArch_MC
19070
} // end namespace llvm
19071
#endif // GET_COMPUTE_FEATURES
19072
19073
#ifdef GET_AVAILABLE_OPCODE_CHECKER
19074
#undef GET_AVAILABLE_OPCODE_CHECKER
19075
namespace llvm {
19076
namespace LoongArch_MC {
19077
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
19078
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
19079
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
19080
  FeatureBitset MissingFeatures =
19081
      (AvailableFeatures & RequiredFeatures) ^
19082
      RequiredFeatures;
19083
  return !MissingFeatures.any();
19084
}
19085
} // end namespace LoongArch_MC
19086
} // end namespace llvm
19087
#endif // GET_AVAILABLE_OPCODE_CHECKER
19088
19089
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
19090
#undef ENABLE_INSTR_PREDICATE_VERIFIER
19091
#include <sstream>
19092
19093
namespace llvm {
19094
namespace LoongArch_MC {
19095
19096
#ifndef NDEBUG
19097
static const char *SubtargetFeatureNames[] = {
19098
  "Feature_HasLaGlobalWithAbs",
19099
  "Feature_HasLaGlobalWithPcrel",
19100
  "Feature_HasLaLocalWithAbs",
19101
  "Feature_IsLA32",
19102
  "Feature_IsLA64",
19103
  nullptr
19104
};
19105
19106
#endif // NDEBUG
19107
19108
void verifyInstructionPredicates(
19109
0
    unsigned Opcode, const FeatureBitset &Features) {
19110
0
#ifndef NDEBUG
19111
0
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
19112
0
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
19113
0
  FeatureBitset MissingFeatures =
19114
0
      (AvailableFeatures & RequiredFeatures) ^
19115
0
      RequiredFeatures;
19116
0
  if (MissingFeatures.any()) {
19117
0
    std::ostringstream Msg;
19118
0
    Msg << "Attempting to emit " << &LoongArchInstrNameData[LoongArchInstrNameIndices[Opcode]]
19119
0
        << " instruction but the ";
19120
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
19121
0
      if (MissingFeatures.test(i))
19122
0
        Msg << SubtargetFeatureNames[i] << " ";
19123
0
    Msg << "predicate(s) are not met";
19124
0
    report_fatal_error(Msg.str().c_str());
19125
0
  }
19126
0
#endif // NDEBUG
19127
0
}
19128
} // end namespace LoongArch_MC
19129
} // end namespace llvm
19130
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
19131