/src/build/lib/Target/LoongArch/LoongArchGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t LoongArchMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(0), |
297 | 0 | UINT64_C(0), |
298 | 0 | UINT64_C(0), |
299 | 0 | UINT64_C(0), |
300 | 0 | UINT64_C(0), |
301 | 0 | UINT64_C(0), |
302 | 0 | UINT64_C(0), |
303 | 0 | UINT64_C(0), |
304 | 0 | UINT64_C(0), |
305 | 0 | UINT64_C(0), |
306 | 0 | UINT64_C(0), |
307 | 0 | UINT64_C(0), |
308 | 0 | UINT64_C(0), |
309 | 0 | UINT64_C(0), |
310 | 0 | UINT64_C(0), |
311 | 0 | UINT64_C(0), |
312 | 0 | UINT64_C(0), |
313 | 0 | UINT64_C(0), |
314 | 0 | UINT64_C(0), |
315 | 0 | UINT64_C(0), |
316 | 0 | UINT64_C(0), |
317 | 0 | UINT64_C(0), |
318 | 0 | UINT64_C(0), |
319 | 0 | UINT64_C(0), |
320 | 0 | UINT64_C(0), |
321 | 0 | UINT64_C(0), |
322 | 0 | UINT64_C(0), |
323 | 0 | UINT64_C(0), |
324 | 0 | UINT64_C(0), |
325 | 0 | UINT64_C(0), |
326 | 0 | UINT64_C(0), |
327 | 0 | UINT64_C(0), |
328 | 0 | UINT64_C(0), |
329 | 0 | UINT64_C(0), |
330 | 0 | UINT64_C(0), |
331 | 0 | UINT64_C(0), |
332 | 0 | UINT64_C(0), |
333 | 0 | UINT64_C(0), |
334 | 0 | UINT64_C(0), |
335 | 0 | UINT64_C(0), |
336 | 0 | UINT64_C(0), |
337 | 0 | UINT64_C(0), |
338 | 0 | UINT64_C(0), |
339 | 0 | UINT64_C(0), |
340 | 0 | UINT64_C(0), |
341 | 0 | UINT64_C(0), |
342 | 0 | UINT64_C(0), |
343 | 0 | UINT64_C(0), |
344 | 0 | UINT64_C(0), |
345 | 0 | UINT64_C(0), |
346 | 0 | UINT64_C(0), |
347 | 0 | UINT64_C(0), |
348 | 0 | UINT64_C(0), |
349 | 0 | UINT64_C(0), |
350 | 0 | UINT64_C(0), |
351 | 0 | UINT64_C(0), |
352 | 0 | UINT64_C(0), |
353 | 0 | UINT64_C(0), |
354 | 0 | UINT64_C(0), |
355 | 0 | UINT64_C(0), |
356 | 0 | UINT64_C(0), |
357 | 0 | UINT64_C(0), |
358 | 0 | UINT64_C(0), |
359 | 0 | UINT64_C(0), |
360 | 0 | UINT64_C(0), |
361 | 0 | UINT64_C(0), |
362 | 0 | UINT64_C(0), |
363 | 0 | UINT64_C(0), |
364 | 0 | UINT64_C(0), |
365 | 0 | UINT64_C(0), |
366 | 0 | UINT64_C(0), |
367 | 0 | UINT64_C(0), |
368 | 0 | UINT64_C(0), |
369 | 0 | UINT64_C(0), |
370 | 0 | UINT64_C(0), |
371 | 0 | UINT64_C(0), |
372 | 0 | UINT64_C(0), |
373 | 0 | UINT64_C(0), |
374 | 0 | UINT64_C(3145728), // ADC_B |
375 | 0 | UINT64_C(3244032), // ADC_D |
376 | 0 | UINT64_C(3178496), // ADC_H |
377 | 0 | UINT64_C(3211264), // ADC_W |
378 | 0 | UINT64_C(46137344), // ADDI_D |
379 | 0 | UINT64_C(41943040), // ADDI_W |
380 | 0 | UINT64_C(2719744), // ADDU12I_D |
381 | 0 | UINT64_C(2686976), // ADDU12I_W |
382 | 0 | UINT64_C(268435456), // ADDU16I_D |
383 | 0 | UINT64_C(1081344), // ADD_D |
384 | 0 | UINT64_C(1048576), // ADD_W |
385 | 0 | UINT64_C(2883584), // ALSL_D |
386 | 0 | UINT64_C(262144), // ALSL_W |
387 | 0 | UINT64_C(393216), // ALSL_WU |
388 | 0 | UINT64_C(945618944), // AMADD_B |
389 | 0 | UINT64_C(945913856), // AMADD_D |
390 | 0 | UINT64_C(945651712), // AMADD_H |
391 | 0 | UINT64_C(945881088), // AMADD_W |
392 | 0 | UINT64_C(945750016), // AMADD__DB_B |
393 | 0 | UINT64_C(946503680), // AMADD__DB_D |
394 | 0 | UINT64_C(945782784), // AMADD__DB_H |
395 | 0 | UINT64_C(946470912), // AMADD__DB_W |
396 | 0 | UINT64_C(945979392), // AMAND_D |
397 | 0 | UINT64_C(945946624), // AMAND_W |
398 | 0 | UINT64_C(946569216), // AMAND__DB_D |
399 | 0 | UINT64_C(946536448), // AMAND__DB_W |
400 | 0 | UINT64_C(945291264), // AMCAS_B |
401 | 0 | UINT64_C(945389568), // AMCAS_D |
402 | 0 | UINT64_C(945324032), // AMCAS_H |
403 | 0 | UINT64_C(945356800), // AMCAS_W |
404 | 0 | UINT64_C(945422336), // AMCAS__DB_B |
405 | 0 | UINT64_C(945520640), // AMCAS__DB_D |
406 | 0 | UINT64_C(945455104), // AMCAS__DB_H |
407 | 0 | UINT64_C(945487872), // AMCAS__DB_W |
408 | 0 | UINT64_C(946176000), // AMMAX_D |
409 | 0 | UINT64_C(946307072), // AMMAX_DU |
410 | 0 | UINT64_C(946143232), // AMMAX_W |
411 | 0 | UINT64_C(946274304), // AMMAX_WU |
412 | 0 | UINT64_C(946765824), // AMMAX__DB_D |
413 | 0 | UINT64_C(946896896), // AMMAX__DB_DU |
414 | 0 | UINT64_C(946733056), // AMMAX__DB_W |
415 | 0 | UINT64_C(946864128), // AMMAX__DB_WU |
416 | 0 | UINT64_C(946241536), // AMMIN_D |
417 | 0 | UINT64_C(946372608), // AMMIN_DU |
418 | 0 | UINT64_C(946208768), // AMMIN_W |
419 | 0 | UINT64_C(946339840), // AMMIN_WU |
420 | 0 | UINT64_C(946831360), // AMMIN__DB_D |
421 | 0 | UINT64_C(946962432), // AMMIN__DB_DU |
422 | 0 | UINT64_C(946798592), // AMMIN__DB_W |
423 | 0 | UINT64_C(946929664), // AMMIN__DB_WU |
424 | 0 | UINT64_C(946044928), // AMOR_D |
425 | 0 | UINT64_C(946012160), // AMOR_W |
426 | 0 | UINT64_C(946634752), // AMOR__DB_D |
427 | 0 | UINT64_C(946601984), // AMOR__DB_W |
428 | 0 | UINT64_C(945553408), // AMSWAP_B |
429 | 0 | UINT64_C(945848320), // AMSWAP_D |
430 | 0 | UINT64_C(945586176), // AMSWAP_H |
431 | 0 | UINT64_C(945815552), // AMSWAP_W |
432 | 0 | UINT64_C(945684480), // AMSWAP__DB_B |
433 | 0 | UINT64_C(946438144), // AMSWAP__DB_D |
434 | 0 | UINT64_C(945717248), // AMSWAP__DB_H |
435 | 0 | UINT64_C(946405376), // AMSWAP__DB_W |
436 | 0 | UINT64_C(946110464), // AMXOR_D |
437 | 0 | UINT64_C(946077696), // AMXOR_W |
438 | 0 | UINT64_C(946700288), // AMXOR__DB_D |
439 | 0 | UINT64_C(946667520), // AMXOR__DB_W |
440 | 0 | UINT64_C(1343488), // AND |
441 | 0 | UINT64_C(54525952), // ANDI |
442 | 0 | UINT64_C(1474560), // ANDN |
443 | 0 | UINT64_C(3670032), // ARMADC_W |
444 | 0 | UINT64_C(3604496), // ARMADD_W |
445 | 0 | UINT64_C(3735568), // ARMAND_W |
446 | 0 | UINT64_C(6029376), // ARMMFFLAG |
447 | 0 | UINT64_C(3555328), // ARMMOVE |
448 | 0 | UINT64_C(4177950), // ARMMOV_D |
449 | 0 | UINT64_C(4177949), // ARMMOV_W |
450 | 0 | UINT64_C(6029408), // ARMMTFLAG |
451 | 0 | UINT64_C(4177948), // ARMNOT_W |
452 | 0 | UINT64_C(3768336), // ARMOR_W |
453 | 0 | UINT64_C(4063248), // ARMROTRI_W |
454 | 0 | UINT64_C(3932176), // ARMROTR_W |
455 | 0 | UINT64_C(4177951), // ARMRRX_W |
456 | 0 | UINT64_C(3702800), // ARMSBC_W |
457 | 0 | UINT64_C(3964944), // ARMSLLI_W |
458 | 0 | UINT64_C(3833872), // ARMSLL_W |
459 | 0 | UINT64_C(4030480), // ARMSRAI_W |
460 | 0 | UINT64_C(3899408), // ARMSRA_W |
461 | 0 | UINT64_C(3997712), // ARMSRLI_W |
462 | 0 | UINT64_C(3866640), // ARMSRL_W |
463 | 0 | UINT64_C(3637264), // ARMSUB_W |
464 | 0 | UINT64_C(3801104), // ARMXOR_W |
465 | 0 | UINT64_C(98304), // ASRTGT_D |
466 | 0 | UINT64_C(65536), // ASRTLE_D |
467 | 0 | UINT64_C(1342177280), // B |
468 | 0 | UINT64_C(1207959552), // BCEQZ |
469 | 0 | UINT64_C(1207959808), // BCNEZ |
470 | 0 | UINT64_C(1476395008), // BEQ |
471 | 0 | UINT64_C(1073741824), // BEQZ |
472 | 0 | UINT64_C(1677721600), // BGE |
473 | 0 | UINT64_C(1811939328), // BGEU |
474 | 0 | UINT64_C(18432), // BITREV_4B |
475 | 0 | UINT64_C(19456), // BITREV_8B |
476 | 0 | UINT64_C(21504), // BITREV_D |
477 | 0 | UINT64_C(20480), // BITREV_W |
478 | 0 | UINT64_C(1409286144), // BL |
479 | 0 | UINT64_C(1610612736), // BLT |
480 | 0 | UINT64_C(1744830464), // BLTU |
481 | 0 | UINT64_C(1543503872), // BNE |
482 | 0 | UINT64_C(1140850688), // BNEZ |
483 | 0 | UINT64_C(2752512), // BREAK |
484 | 0 | UINT64_C(8388608), // BSTRINS_D |
485 | 0 | UINT64_C(6291456), // BSTRINS_W |
486 | 0 | UINT64_C(12582912), // BSTRPICK_D |
487 | 0 | UINT64_C(6324224), // BSTRPICK_W |
488 | 0 | UINT64_C(786432), // BYTEPICK_D |
489 | 0 | UINT64_C(524288), // BYTEPICK_W |
490 | 0 | UINT64_C(100663296), // CACOP |
491 | 0 | UINT64_C(8192), // CLO_D |
492 | 0 | UINT64_C(4096), // CLO_W |
493 | 0 | UINT64_C(9216), // CLZ_D |
494 | 0 | UINT64_C(5120), // CLZ_W |
495 | 0 | UINT64_C(27648), // CPUCFG |
496 | 0 | UINT64_C(2490368), // CRCC_W_B_W |
497 | 0 | UINT64_C(2588672), // CRCC_W_D_W |
498 | 0 | UINT64_C(2523136), // CRCC_W_H_W |
499 | 0 | UINT64_C(2555904), // CRCC_W_W_W |
500 | 0 | UINT64_C(2359296), // CRC_W_B_W |
501 | 0 | UINT64_C(2457600), // CRC_W_D_W |
502 | 0 | UINT64_C(2392064), // CRC_W_H_W |
503 | 0 | UINT64_C(2424832), // CRC_W_W_W |
504 | 0 | UINT64_C(67108864), // CSRRD |
505 | 0 | UINT64_C(67108896), // CSRWR |
506 | 0 | UINT64_C(67108864), // CSRXCHG |
507 | 0 | UINT64_C(10240), // CTO_D |
508 | 0 | UINT64_C(6144), // CTO_W |
509 | 0 | UINT64_C(11264), // CTZ_D |
510 | 0 | UINT64_C(7168), // CTZ_W |
511 | 0 | UINT64_C(946995200), // DBAR |
512 | 0 | UINT64_C(2785280), // DBCL |
513 | 0 | UINT64_C(2228224), // DIV_D |
514 | 0 | UINT64_C(2293760), // DIV_DU |
515 | 0 | UINT64_C(2097152), // DIV_W |
516 | 0 | UINT64_C(2162688), // DIV_WU |
517 | 0 | UINT64_C(105396224), // ERTN |
518 | 0 | UINT64_C(23552), // EXT_W_B |
519 | 0 | UINT64_C(22528), // EXT_W_H |
520 | 0 | UINT64_C(18089984), // FABS_D |
521 | 0 | UINT64_C(18088960), // FABS_S |
522 | 0 | UINT64_C(16842752), // FADD_D |
523 | 0 | UINT64_C(16809984), // FADD_S |
524 | 0 | UINT64_C(18102272), // FCLASS_D |
525 | 0 | UINT64_C(18101248), // FCLASS_S |
526 | 0 | UINT64_C(203423744), // FCMP_CAF_D |
527 | 0 | UINT64_C(202375168), // FCMP_CAF_S |
528 | 0 | UINT64_C(203554816), // FCMP_CEQ_D |
529 | 0 | UINT64_C(202506240), // FCMP_CEQ_S |
530 | 0 | UINT64_C(203620352), // FCMP_CLE_D |
531 | 0 | UINT64_C(202571776), // FCMP_CLE_S |
532 | 0 | UINT64_C(203489280), // FCMP_CLT_D |
533 | 0 | UINT64_C(202440704), // FCMP_CLT_S |
534 | 0 | UINT64_C(203948032), // FCMP_CNE_D |
535 | 0 | UINT64_C(202899456), // FCMP_CNE_S |
536 | 0 | UINT64_C(204079104), // FCMP_COR_D |
537 | 0 | UINT64_C(203030528), // FCMP_COR_S |
538 | 0 | UINT64_C(203816960), // FCMP_CUEQ_D |
539 | 0 | UINT64_C(202768384), // FCMP_CUEQ_S |
540 | 0 | UINT64_C(203882496), // FCMP_CULE_D |
541 | 0 | UINT64_C(202833920), // FCMP_CULE_S |
542 | 0 | UINT64_C(203751424), // FCMP_CULT_D |
543 | 0 | UINT64_C(202702848), // FCMP_CULT_S |
544 | 0 | UINT64_C(204210176), // FCMP_CUNE_D |
545 | 0 | UINT64_C(203161600), // FCMP_CUNE_S |
546 | 0 | UINT64_C(203685888), // FCMP_CUN_D |
547 | 0 | UINT64_C(202637312), // FCMP_CUN_S |
548 | 0 | UINT64_C(203456512), // FCMP_SAF_D |
549 | 0 | UINT64_C(202407936), // FCMP_SAF_S |
550 | 0 | UINT64_C(203587584), // FCMP_SEQ_D |
551 | 0 | UINT64_C(202539008), // FCMP_SEQ_S |
552 | 0 | UINT64_C(203653120), // FCMP_SLE_D |
553 | 0 | UINT64_C(202604544), // FCMP_SLE_S |
554 | 0 | UINT64_C(203522048), // FCMP_SLT_D |
555 | 0 | UINT64_C(202473472), // FCMP_SLT_S |
556 | 0 | UINT64_C(203980800), // FCMP_SNE_D |
557 | 0 | UINT64_C(202932224), // FCMP_SNE_S |
558 | 0 | UINT64_C(204111872), // FCMP_SOR_D |
559 | 0 | UINT64_C(203063296), // FCMP_SOR_S |
560 | 0 | UINT64_C(203849728), // FCMP_SUEQ_D |
561 | 0 | UINT64_C(202801152), // FCMP_SUEQ_S |
562 | 0 | UINT64_C(203915264), // FCMP_SULE_D |
563 | 0 | UINT64_C(202866688), // FCMP_SULE_S |
564 | 0 | UINT64_C(203784192), // FCMP_SULT_D |
565 | 0 | UINT64_C(202735616), // FCMP_SULT_S |
566 | 0 | UINT64_C(204242944), // FCMP_SUNE_D |
567 | 0 | UINT64_C(203194368), // FCMP_SUNE_S |
568 | 0 | UINT64_C(203718656), // FCMP_SUN_D |
569 | 0 | UINT64_C(202670080), // FCMP_SUN_S |
570 | 0 | UINT64_C(18022400), // FCOPYSIGN_D |
571 | 0 | UINT64_C(17989632), // FCOPYSIGN_S |
572 | 0 | UINT64_C(18153472), // FCVT_D_LD |
573 | 0 | UINT64_C(18424832), // FCVT_D_S |
574 | 0 | UINT64_C(18145280), // FCVT_LD_D |
575 | 0 | UINT64_C(18421760), // FCVT_S_D |
576 | 0 | UINT64_C(18146304), // FCVT_UD_D |
577 | 0 | UINT64_C(17235968), // FDIV_D |
578 | 0 | UINT64_C(17203200), // FDIV_S |
579 | 0 | UINT64_C(18688000), // FFINT_D_L |
580 | 0 | UINT64_C(18685952), // FFINT_D_W |
581 | 0 | UINT64_C(18683904), // FFINT_S_L |
582 | 0 | UINT64_C(18681856), // FFINT_S_W |
583 | 0 | UINT64_C(947159040), // FLDGT_D |
584 | 0 | UINT64_C(947126272), // FLDGT_S |
585 | 0 | UINT64_C(947224576), // FLDLE_D |
586 | 0 | UINT64_C(947191808), // FLDLE_S |
587 | 0 | UINT64_C(942931968), // FLDX_D |
588 | 0 | UINT64_C(942669824), // FLDX_S |
589 | 0 | UINT64_C(729808896), // FLD_D |
590 | 0 | UINT64_C(721420288), // FLD_S |
591 | 0 | UINT64_C(18098176), // FLOGB_D |
592 | 0 | UINT64_C(18097152), // FLOGB_S |
593 | 0 | UINT64_C(136314880), // FMADD_D |
594 | 0 | UINT64_C(135266304), // FMADD_S |
595 | 0 | UINT64_C(17629184), // FMAXA_D |
596 | 0 | UINT64_C(17596416), // FMAXA_S |
597 | 0 | UINT64_C(17367040), // FMAX_D |
598 | 0 | UINT64_C(17334272), // FMAX_S |
599 | 0 | UINT64_C(17760256), // FMINA_D |
600 | 0 | UINT64_C(17727488), // FMINA_S |
601 | 0 | UINT64_C(17498112), // FMIN_D |
602 | 0 | UINT64_C(17465344), // FMIN_S |
603 | 0 | UINT64_C(18126848), // FMOV_D |
604 | 0 | UINT64_C(18125824), // FMOV_S |
605 | 0 | UINT64_C(140509184), // FMSUB_D |
606 | 0 | UINT64_C(139460608), // FMSUB_S |
607 | 0 | UINT64_C(17104896), // FMUL_D |
608 | 0 | UINT64_C(17072128), // FMUL_S |
609 | 0 | UINT64_C(18094080), // FNEG_D |
610 | 0 | UINT64_C(18093056), // FNEG_S |
611 | 0 | UINT64_C(144703488), // FNMADD_D |
612 | 0 | UINT64_C(143654912), // FNMADD_S |
613 | 0 | UINT64_C(148897792), // FNMSUB_D |
614 | 0 | UINT64_C(147849216), // FNMSUB_S |
615 | 0 | UINT64_C(18118656), // FRECIPE_D |
616 | 0 | UINT64_C(18117632), // FRECIPE_S |
617 | 0 | UINT64_C(18110464), // FRECIP_D |
618 | 0 | UINT64_C(18109440), // FRECIP_S |
619 | 0 | UINT64_C(18761728), // FRINT_D |
620 | 0 | UINT64_C(18760704), // FRINT_S |
621 | 0 | UINT64_C(18122752), // FRSQRTE_D |
622 | 0 | UINT64_C(18121728), // FRSQRTE_S |
623 | 0 | UINT64_C(18114560), // FRSQRT_D |
624 | 0 | UINT64_C(18113536), // FRSQRT_S |
625 | 0 | UINT64_C(17891328), // FSCALEB_D |
626 | 0 | UINT64_C(17858560), // FSCALEB_S |
627 | 0 | UINT64_C(218103808), // FSEL_xD |
628 | 0 | UINT64_C(218103808), // FSEL_xS |
629 | 0 | UINT64_C(18106368), // FSQRT_D |
630 | 0 | UINT64_C(18105344), // FSQRT_S |
631 | 0 | UINT64_C(947290112), // FSTGT_D |
632 | 0 | UINT64_C(947257344), // FSTGT_S |
633 | 0 | UINT64_C(947355648), // FSTLE_D |
634 | 0 | UINT64_C(947322880), // FSTLE_S |
635 | 0 | UINT64_C(943456256), // FSTX_D |
636 | 0 | UINT64_C(943194112), // FSTX_S |
637 | 0 | UINT64_C(734003200), // FST_D |
638 | 0 | UINT64_C(725614592), // FST_S |
639 | 0 | UINT64_C(16973824), // FSUB_D |
640 | 0 | UINT64_C(16941056), // FSUB_S |
641 | 0 | UINT64_C(18491392), // FTINTRM_L_D |
642 | 0 | UINT64_C(18490368), // FTINTRM_L_S |
643 | 0 | UINT64_C(18483200), // FTINTRM_W_D |
644 | 0 | UINT64_C(18482176), // FTINTRM_W_S |
645 | 0 | UINT64_C(18540544), // FTINTRNE_L_D |
646 | 0 | UINT64_C(18539520), // FTINTRNE_L_S |
647 | 0 | UINT64_C(18532352), // FTINTRNE_W_D |
648 | 0 | UINT64_C(18531328), // FTINTRNE_W_S |
649 | 0 | UINT64_C(18507776), // FTINTRP_L_D |
650 | 0 | UINT64_C(18506752), // FTINTRP_L_S |
651 | 0 | UINT64_C(18499584), // FTINTRP_W_D |
652 | 0 | UINT64_C(18498560), // FTINTRP_W_S |
653 | 0 | UINT64_C(18524160), // FTINTRZ_L_D |
654 | 0 | UINT64_C(18523136), // FTINTRZ_L_S |
655 | 0 | UINT64_C(18515968), // FTINTRZ_W_D |
656 | 0 | UINT64_C(18514944), // FTINTRZ_W_S |
657 | 0 | UINT64_C(18556928), // FTINT_L_D |
658 | 0 | UINT64_C(18555904), // FTINT_L_S |
659 | 0 | UINT64_C(18548736), // FTINT_W_D |
660 | 0 | UINT64_C(18547712), // FTINT_W_S |
661 | 0 | UINT64_C(83886080), // GCSRRD |
662 | 0 | UINT64_C(83886112), // GCSRWR |
663 | 0 | UINT64_C(83886080), // GCSRXCHG |
664 | 0 | UINT64_C(105391105), // GTLBFLUSH |
665 | 0 | UINT64_C(2850816), // HVCL |
666 | 0 | UINT64_C(947027968), // IBAR |
667 | 0 | UINT64_C(105414656), // IDLE |
668 | 0 | UINT64_C(105480192), // INVTLB |
669 | 0 | UINT64_C(105381888), // IOCSRRD_B |
670 | 0 | UINT64_C(105384960), // IOCSRRD_D |
671 | 0 | UINT64_C(105382912), // IOCSRRD_H |
672 | 0 | UINT64_C(105383936), // IOCSRRD_W |
673 | 0 | UINT64_C(105385984), // IOCSRWR_B |
674 | 0 | UINT64_C(105389056), // IOCSRWR_D |
675 | 0 | UINT64_C(105387008), // IOCSRWR_H |
676 | 0 | UINT64_C(105388032), // IOCSRWR_W |
677 | 0 | UINT64_C(1275068416), // JIRL |
678 | 0 | UINT64_C(1207960064), // JISCR0 |
679 | 0 | UINT64_C(1207960320), // JISCR1 |
680 | 0 | UINT64_C(104857600), // LDDIR |
681 | 0 | UINT64_C(947388416), // LDGT_B |
682 | 0 | UINT64_C(947486720), // LDGT_D |
683 | 0 | UINT64_C(947421184), // LDGT_H |
684 | 0 | UINT64_C(947453952), // LDGT_W |
685 | 0 | UINT64_C(947519488), // LDLE_B |
686 | 0 | UINT64_C(947617792), // LDLE_D |
687 | 0 | UINT64_C(947552256), // LDLE_H |
688 | 0 | UINT64_C(947585024), // LDLE_W |
689 | 0 | UINT64_C(780140544), // LDL_D |
690 | 0 | UINT64_C(771751936), // LDL_W |
691 | 0 | UINT64_C(105119744), // LDPTE |
692 | 0 | UINT64_C(637534208), // LDPTR_D |
693 | 0 | UINT64_C(603979776), // LDPTR_W |
694 | 0 | UINT64_C(784334848), // LDR_D |
695 | 0 | UINT64_C(775946240), // LDR_W |
696 | 0 | UINT64_C(939524096), // LDX_B |
697 | 0 | UINT64_C(941621248), // LDX_BU |
698 | 0 | UINT64_C(940310528), // LDX_D |
699 | 0 | UINT64_C(939786240), // LDX_H |
700 | 0 | UINT64_C(941883392), // LDX_HU |
701 | 0 | UINT64_C(940048384), // LDX_W |
702 | 0 | UINT64_C(942145536), // LDX_WU |
703 | 0 | UINT64_C(671088640), // LD_B |
704 | 0 | UINT64_C(704643072), // LD_BU |
705 | 0 | UINT64_C(683671552), // LD_D |
706 | 0 | UINT64_C(675282944), // LD_H |
707 | 0 | UINT64_C(708837376), // LD_HU |
708 | 0 | UINT64_C(679477248), // LD_W |
709 | 0 | UINT64_C(713031680), // LD_WU |
710 | 0 | UINT64_C(945260544), // LLACQ_D |
711 | 0 | UINT64_C(945258496), // LLACQ_W |
712 | 0 | UINT64_C(570425344), // LL_D |
713 | 0 | UINT64_C(536870912), // LL_W |
714 | 0 | UINT64_C(335544320), // LU12I_W |
715 | 0 | UINT64_C(369098752), // LU32I_D |
716 | 0 | UINT64_C(50331648), // LU52I_D |
717 | 0 | UINT64_C(1245184), // MASKEQZ |
718 | 0 | UINT64_C(1277952), // MASKNEZ |
719 | 0 | UINT64_C(2260992), // MOD_D |
720 | 0 | UINT64_C(2326528), // MOD_DU |
721 | 0 | UINT64_C(2129920), // MOD_W |
722 | 0 | UINT64_C(2195456), // MOD_WU |
723 | 0 | UINT64_C(18142208), // MOVCF2FR_xS |
724 | 0 | UINT64_C(18144256), // MOVCF2GR |
725 | 0 | UINT64_C(18139136), // MOVFCSR2GR |
726 | 0 | UINT64_C(18141184), // MOVFR2CF_xS |
727 | 0 | UINT64_C(18135040), // MOVFR2GR_D |
728 | 0 | UINT64_C(18134016), // MOVFR2GR_S |
729 | 0 | UINT64_C(18134016), // MOVFR2GR_S_64 |
730 | 0 | UINT64_C(18136064), // MOVFRH2GR_S |
731 | 0 | UINT64_C(18143232), // MOVGR2CF |
732 | 0 | UINT64_C(18137088), // MOVGR2FCSR |
733 | 0 | UINT64_C(18131968), // MOVGR2FRH_W |
734 | 0 | UINT64_C(18130944), // MOVGR2FR_D |
735 | 0 | UINT64_C(18129920), // MOVGR2FR_W |
736 | 0 | UINT64_C(18129920), // MOVGR2FR_W_64 |
737 | 0 | UINT64_C(2048), // MOVGR2SCR |
738 | 0 | UINT64_C(3072), // MOVSCR2GR |
739 | 0 | UINT64_C(1966080), // MULH_D |
740 | 0 | UINT64_C(1998848), // MULH_DU |
741 | 0 | UINT64_C(1867776), // MULH_W |
742 | 0 | UINT64_C(1900544), // MULH_WU |
743 | 0 | UINT64_C(2031616), // MULW_D_W |
744 | 0 | UINT64_C(2064384), // MULW_D_WU |
745 | 0 | UINT64_C(1933312), // MUL_D |
746 | 0 | UINT64_C(1835008), // MUL_W |
747 | 0 | UINT64_C(1310720), // NOR |
748 | 0 | UINT64_C(1376256), // OR |
749 | 0 | UINT64_C(58720256), // ORI |
750 | 0 | UINT64_C(1441792), // ORN |
751 | 0 | UINT64_C(402653184), // PCADDI |
752 | 0 | UINT64_C(469762048), // PCADDU12I |
753 | 0 | UINT64_C(503316480), // PCADDU18I |
754 | 0 | UINT64_C(436207616), // PCALAU12I |
755 | 0 | UINT64_C(717225984), // PRELD |
756 | 0 | UINT64_C(942407680), // PRELDX |
757 | 0 | UINT64_C(5251072), // RCRI_B |
758 | 0 | UINT64_C(5308416), // RCRI_D |
759 | 0 | UINT64_C(5259264), // RCRI_H |
760 | 0 | UINT64_C(5275648), // RCRI_W |
761 | 0 | UINT64_C(3407872), // RCR_B |
762 | 0 | UINT64_C(3506176), // RCR_D |
763 | 0 | UINT64_C(3440640), // RCR_H |
764 | 0 | UINT64_C(3473408), // RCR_W |
765 | 0 | UINT64_C(25600), // RDTIMEH_W |
766 | 0 | UINT64_C(24576), // RDTIMEL_W |
767 | 0 | UINT64_C(26624), // RDTIME_D |
768 | 0 | UINT64_C(12288), // REVB_2H |
769 | 0 | UINT64_C(14336), // REVB_2W |
770 | 0 | UINT64_C(13312), // REVB_4H |
771 | 0 | UINT64_C(15360), // REVB_D |
772 | 0 | UINT64_C(16384), // REVH_2W |
773 | 0 | UINT64_C(17408), // REVH_D |
774 | 0 | UINT64_C(4988928), // ROTRI_B |
775 | 0 | UINT64_C(5046272), // ROTRI_D |
776 | 0 | UINT64_C(4997120), // ROTRI_H |
777 | 0 | UINT64_C(5013504), // ROTRI_W |
778 | 0 | UINT64_C(1703936), // ROTR_B |
779 | 0 | UINT64_C(1802240), // ROTR_D |
780 | 0 | UINT64_C(1736704), // ROTR_H |
781 | 0 | UINT64_C(1769472), // ROTR_W |
782 | 0 | UINT64_C(3276800), // SBC_B |
783 | 0 | UINT64_C(3375104), // SBC_D |
784 | 0 | UINT64_C(3309568), // SBC_H |
785 | 0 | UINT64_C(3342336), // SBC_W |
786 | 0 | UINT64_C(945261568), // SCREL_D |
787 | 0 | UINT64_C(945259520), // SCREL_W |
788 | 0 | UINT64_C(587202560), // SC_D |
789 | 0 | UINT64_C(945225728), // SC_Q |
790 | 0 | UINT64_C(553648128), // SC_W |
791 | 0 | UINT64_C(3588096), // SETARMJ |
792 | 0 | UINT64_C(3571712), // SETX86J |
793 | 0 | UINT64_C(30720), // SETX86LOOPE |
794 | 0 | UINT64_C(31744), // SETX86LOOPNE |
795 | 0 | UINT64_C(202375168), // SET_CFR_FALSE |
796 | 0 | UINT64_C(202768384), // SET_CFR_TRUE |
797 | 0 | UINT64_C(4259840), // SLLI_D |
798 | 0 | UINT64_C(4227072), // SLLI_W |
799 | 0 | UINT64_C(1605632), // SLL_D |
800 | 0 | UINT64_C(1507328), // SLL_W |
801 | 0 | UINT64_C(1179648), // SLT |
802 | 0 | UINT64_C(33554432), // SLTI |
803 | 0 | UINT64_C(1212416), // SLTU |
804 | 0 | UINT64_C(37748736), // SLTUI |
805 | 0 | UINT64_C(4784128), // SRAI_D |
806 | 0 | UINT64_C(4751360), // SRAI_W |
807 | 0 | UINT64_C(1671168), // SRA_D |
808 | 0 | UINT64_C(1572864), // SRA_W |
809 | 0 | UINT64_C(4521984), // SRLI_D |
810 | 0 | UINT64_C(4489216), // SRLI_W |
811 | 0 | UINT64_C(1638400), // SRL_D |
812 | 0 | UINT64_C(1540096), // SRL_W |
813 | 0 | UINT64_C(947650560), // STGT_B |
814 | 0 | UINT64_C(947748864), // STGT_D |
815 | 0 | UINT64_C(947683328), // STGT_H |
816 | 0 | UINT64_C(947716096), // STGT_W |
817 | 0 | UINT64_C(947781632), // STLE_B |
818 | 0 | UINT64_C(947879936), // STLE_D |
819 | 0 | UINT64_C(947814400), // STLE_H |
820 | 0 | UINT64_C(947847168), // STLE_W |
821 | 0 | UINT64_C(796917760), // STL_D |
822 | 0 | UINT64_C(788529152), // STL_W |
823 | 0 | UINT64_C(654311424), // STPTR_D |
824 | 0 | UINT64_C(620756992), // STPTR_W |
825 | 0 | UINT64_C(801112064), // STR_D |
826 | 0 | UINT64_C(792723456), // STR_W |
827 | 0 | UINT64_C(940572672), // STX_B |
828 | 0 | UINT64_C(941359104), // STX_D |
829 | 0 | UINT64_C(940834816), // STX_H |
830 | 0 | UINT64_C(941096960), // STX_W |
831 | 0 | UINT64_C(687865856), // ST_B |
832 | 0 | UINT64_C(700448768), // ST_D |
833 | 0 | UINT64_C(692060160), // ST_H |
834 | 0 | UINT64_C(696254464), // ST_W |
835 | 0 | UINT64_C(1146880), // SUB_D |
836 | 0 | UINT64_C(1114112), // SUB_W |
837 | 0 | UINT64_C(2818048), // SYSCALL |
838 | 0 | UINT64_C(105390080), // TLBCLR |
839 | 0 | UINT64_C(105395200), // TLBFILL |
840 | 0 | UINT64_C(105391104), // TLBFLUSH |
841 | 0 | UINT64_C(105393152), // TLBRD |
842 | 0 | UINT64_C(105392128), // TLBSRCH |
843 | 0 | UINT64_C(105394176), // TLBWR |
844 | 0 | UINT64_C(1885339648), // VABSD_B |
845 | 0 | UINT64_C(1885470720), // VABSD_BU |
846 | 0 | UINT64_C(1885437952), // VABSD_D |
847 | 0 | UINT64_C(1885569024), // VABSD_DU |
848 | 0 | UINT64_C(1885372416), // VABSD_H |
849 | 0 | UINT64_C(1885503488), // VABSD_HU |
850 | 0 | UINT64_C(1885405184), // VABSD_W |
851 | 0 | UINT64_C(1885536256), // VABSD_WU |
852 | 0 | UINT64_C(1885077504), // VADDA_B |
853 | 0 | UINT64_C(1885175808), // VADDA_D |
854 | 0 | UINT64_C(1885110272), // VADDA_H |
855 | 0 | UINT64_C(1885143040), // VADDA_W |
856 | 0 | UINT64_C(1921646592), // VADDI_BU |
857 | 0 | UINT64_C(1921744896), // VADDI_DU |
858 | 0 | UINT64_C(1921679360), // VADDI_HU |
859 | 0 | UINT64_C(1921712128), // VADDI_WU |
860 | 0 | UINT64_C(1881079808), // VADDWEV_D_W |
861 | 0 | UINT64_C(1882128384), // VADDWEV_D_WU |
862 | 0 | UINT64_C(1883176960), // VADDWEV_D_WU_W |
863 | 0 | UINT64_C(1881014272), // VADDWEV_H_B |
864 | 0 | UINT64_C(1882062848), // VADDWEV_H_BU |
865 | 0 | UINT64_C(1883111424), // VADDWEV_H_BU_B |
866 | 0 | UINT64_C(1881112576), // VADDWEV_Q_D |
867 | 0 | UINT64_C(1882161152), // VADDWEV_Q_DU |
868 | 0 | UINT64_C(1883209728), // VADDWEV_Q_DU_D |
869 | 0 | UINT64_C(1881047040), // VADDWEV_W_H |
870 | 0 | UINT64_C(1882095616), // VADDWEV_W_HU |
871 | 0 | UINT64_C(1883144192), // VADDWEV_W_HU_H |
872 | 0 | UINT64_C(1881341952), // VADDWOD_D_W |
873 | 0 | UINT64_C(1882390528), // VADDWOD_D_WU |
874 | 0 | UINT64_C(1883308032), // VADDWOD_D_WU_W |
875 | 0 | UINT64_C(1881276416), // VADDWOD_H_B |
876 | 0 | UINT64_C(1882324992), // VADDWOD_H_BU |
877 | 0 | UINT64_C(1883242496), // VADDWOD_H_BU_B |
878 | 0 | UINT64_C(1881374720), // VADDWOD_Q_D |
879 | 0 | UINT64_C(1882423296), // VADDWOD_Q_DU |
880 | 0 | UINT64_C(1883340800), // VADDWOD_Q_DU_D |
881 | 0 | UINT64_C(1881309184), // VADDWOD_W_H |
882 | 0 | UINT64_C(1882357760), // VADDWOD_W_HU |
883 | 0 | UINT64_C(1883275264), // VADDWOD_W_HU_H |
884 | 0 | UINT64_C(1879703552), // VADD_B |
885 | 0 | UINT64_C(1879801856), // VADD_D |
886 | 0 | UINT64_C(1879736320), // VADD_H |
887 | 0 | UINT64_C(1898774528), // VADD_Q |
888 | 0 | UINT64_C(1879769088), // VADD_W |
889 | 0 | UINT64_C(1943011328), // VANDI_B |
890 | 0 | UINT64_C(1898446848), // VANDN_V |
891 | 0 | UINT64_C(1898315776), // VAND_V |
892 | 0 | UINT64_C(1885863936), // VAVGR_B |
893 | 0 | UINT64_C(1885995008), // VAVGR_BU |
894 | 0 | UINT64_C(1885962240), // VAVGR_D |
895 | 0 | UINT64_C(1886093312), // VAVGR_DU |
896 | 0 | UINT64_C(1885896704), // VAVGR_H |
897 | 0 | UINT64_C(1886027776), // VAVGR_HU |
898 | 0 | UINT64_C(1885929472), // VAVGR_W |
899 | 0 | UINT64_C(1886060544), // VAVGR_WU |
900 | 0 | UINT64_C(1885601792), // VAVG_B |
901 | 0 | UINT64_C(1885732864), // VAVG_BU |
902 | 0 | UINT64_C(1885700096), // VAVG_D |
903 | 0 | UINT64_C(1885831168), // VAVG_DU |
904 | 0 | UINT64_C(1885634560), // VAVG_H |
905 | 0 | UINT64_C(1885765632), // VAVG_HU |
906 | 0 | UINT64_C(1885667328), // VAVG_W |
907 | 0 | UINT64_C(1885798400), // VAVG_WU |
908 | 0 | UINT64_C(1930436608), // VBITCLRI_B |
909 | 0 | UINT64_C(1930493952), // VBITCLRI_D |
910 | 0 | UINT64_C(1930444800), // VBITCLRI_H |
911 | 0 | UINT64_C(1930461184), // VBITCLRI_W |
912 | 0 | UINT64_C(1896611840), // VBITCLR_B |
913 | 0 | UINT64_C(1896710144), // VBITCLR_D |
914 | 0 | UINT64_C(1896644608), // VBITCLR_H |
915 | 0 | UINT64_C(1896677376), // VBITCLR_W |
916 | 0 | UINT64_C(1930960896), // VBITREVI_B |
917 | 0 | UINT64_C(1931018240), // VBITREVI_D |
918 | 0 | UINT64_C(1930969088), // VBITREVI_H |
919 | 0 | UINT64_C(1930985472), // VBITREVI_W |
920 | 0 | UINT64_C(1896873984), // VBITREV_B |
921 | 0 | UINT64_C(1896972288), // VBITREV_D |
922 | 0 | UINT64_C(1896906752), // VBITREV_H |
923 | 0 | UINT64_C(1896939520), // VBITREV_W |
924 | 0 | UINT64_C(1942224896), // VBITSELI_B |
925 | 0 | UINT64_C(219152384), // VBITSEL_V |
926 | 0 | UINT64_C(1930698752), // VBITSETI_B |
927 | 0 | UINT64_C(1930756096), // VBITSETI_D |
928 | 0 | UINT64_C(1930706944), // VBITSETI_H |
929 | 0 | UINT64_C(1930723328), // VBITSETI_W |
930 | 0 | UINT64_C(1896742912), // VBITSET_B |
931 | 0 | UINT64_C(1896841216), // VBITSET_D |
932 | 0 | UINT64_C(1896775680), // VBITSET_H |
933 | 0 | UINT64_C(1896808448), // VBITSET_W |
934 | 0 | UINT64_C(1921908736), // VBSLL_V |
935 | 0 | UINT64_C(1921941504), // VBSRL_V |
936 | 0 | UINT64_C(1922826240), // VCLO_B |
937 | 0 | UINT64_C(1922829312), // VCLO_D |
938 | 0 | UINT64_C(1922827264), // VCLO_H |
939 | 0 | UINT64_C(1922828288), // VCLO_W |
940 | 0 | UINT64_C(1922830336), // VCLZ_B |
941 | 0 | UINT64_C(1922833408), // VCLZ_D |
942 | 0 | UINT64_C(1922831360), // VCLZ_H |
943 | 0 | UINT64_C(1922832384), // VCLZ_W |
944 | 0 | UINT64_C(1893728256), // VDIV_B |
945 | 0 | UINT64_C(1893990400), // VDIV_BU |
946 | 0 | UINT64_C(1893826560), // VDIV_D |
947 | 0 | UINT64_C(1894088704), // VDIV_DU |
948 | 0 | UINT64_C(1893761024), // VDIV_H |
949 | 0 | UINT64_C(1894023168), // VDIV_HU |
950 | 0 | UINT64_C(1893793792), // VDIV_W |
951 | 0 | UINT64_C(1894055936), // VDIV_WU |
952 | 0 | UINT64_C(1990144000), // VEXT2XV_DU_BU |
953 | 0 | UINT64_C(1990146048), // VEXT2XV_DU_HU |
954 | 0 | UINT64_C(1990147072), // VEXT2XV_DU_WU |
955 | 0 | UINT64_C(1990137856), // VEXT2XV_D_B |
956 | 0 | UINT64_C(1990139904), // VEXT2XV_D_H |
957 | 0 | UINT64_C(1990140928), // VEXT2XV_D_W |
958 | 0 | UINT64_C(1990141952), // VEXT2XV_HU_BU |
959 | 0 | UINT64_C(1990135808), // VEXT2XV_H_B |
960 | 0 | UINT64_C(1990142976), // VEXT2XV_WU_BU |
961 | 0 | UINT64_C(1990145024), // VEXT2XV_WU_HU |
962 | 0 | UINT64_C(1990136832), // VEXT2XV_W_B |
963 | 0 | UINT64_C(1990138880), // VEXT2XV_W_H |
964 | 0 | UINT64_C(1923020800), // VEXTH_DU_WU |
965 | 0 | UINT64_C(1923016704), // VEXTH_D_W |
966 | 0 | UINT64_C(1923018752), // VEXTH_HU_BU |
967 | 0 | UINT64_C(1923014656), // VEXTH_H_B |
968 | 0 | UINT64_C(1923021824), // VEXTH_QU_DU |
969 | 0 | UINT64_C(1923017728), // VEXTH_Q_D |
970 | 0 | UINT64_C(1923019776), // VEXTH_WU_HU |
971 | 0 | UINT64_C(1923015680), // VEXTH_W_H |
972 | 0 | UINT64_C(1930231808), // VEXTL_QU_DU |
973 | 0 | UINT64_C(1929969664), // VEXTL_Q_D |
974 | 0 | UINT64_C(1938554880), // VEXTRINS_B |
975 | 0 | UINT64_C(1937768448), // VEXTRINS_D |
976 | 0 | UINT64_C(1938292736), // VEXTRINS_H |
977 | 0 | UINT64_C(1938030592), // VEXTRINS_W |
978 | 0 | UINT64_C(1899036672), // VFADD_D |
979 | 0 | UINT64_C(1899003904), // VFADD_S |
980 | 0 | UINT64_C(1922881536), // VFCLASS_D |
981 | 0 | UINT64_C(1922880512), // VFCLASS_S |
982 | 0 | UINT64_C(207618048), // VFCMP_CAF_D |
983 | 0 | UINT64_C(206569472), // VFCMP_CAF_S |
984 | 0 | UINT64_C(207749120), // VFCMP_CEQ_D |
985 | 0 | UINT64_C(206700544), // VFCMP_CEQ_S |
986 | 0 | UINT64_C(207814656), // VFCMP_CLE_D |
987 | 0 | UINT64_C(206766080), // VFCMP_CLE_S |
988 | 0 | UINT64_C(207683584), // VFCMP_CLT_D |
989 | 0 | UINT64_C(206635008), // VFCMP_CLT_S |
990 | 0 | UINT64_C(208142336), // VFCMP_CNE_D |
991 | 0 | UINT64_C(207093760), // VFCMP_CNE_S |
992 | 0 | UINT64_C(208273408), // VFCMP_COR_D |
993 | 0 | UINT64_C(207224832), // VFCMP_COR_S |
994 | 0 | UINT64_C(208011264), // VFCMP_CUEQ_D |
995 | 0 | UINT64_C(206962688), // VFCMP_CUEQ_S |
996 | 0 | UINT64_C(208076800), // VFCMP_CULE_D |
997 | 0 | UINT64_C(207028224), // VFCMP_CULE_S |
998 | 0 | UINT64_C(207945728), // VFCMP_CULT_D |
999 | 0 | UINT64_C(206897152), // VFCMP_CULT_S |
1000 | 0 | UINT64_C(208404480), // VFCMP_CUNE_D |
1001 | 0 | UINT64_C(207355904), // VFCMP_CUNE_S |
1002 | 0 | UINT64_C(207880192), // VFCMP_CUN_D |
1003 | 0 | UINT64_C(206831616), // VFCMP_CUN_S |
1004 | 0 | UINT64_C(207650816), // VFCMP_SAF_D |
1005 | 0 | UINT64_C(206602240), // VFCMP_SAF_S |
1006 | 0 | UINT64_C(207781888), // VFCMP_SEQ_D |
1007 | 0 | UINT64_C(206733312), // VFCMP_SEQ_S |
1008 | 0 | UINT64_C(207847424), // VFCMP_SLE_D |
1009 | 0 | UINT64_C(206798848), // VFCMP_SLE_S |
1010 | 0 | UINT64_C(207716352), // VFCMP_SLT_D |
1011 | 0 | UINT64_C(206667776), // VFCMP_SLT_S |
1012 | 0 | UINT64_C(208175104), // VFCMP_SNE_D |
1013 | 0 | UINT64_C(207126528), // VFCMP_SNE_S |
1014 | 0 | UINT64_C(208306176), // VFCMP_SOR_D |
1015 | 0 | UINT64_C(207257600), // VFCMP_SOR_S |
1016 | 0 | UINT64_C(208044032), // VFCMP_SUEQ_D |
1017 | 0 | UINT64_C(206995456), // VFCMP_SUEQ_S |
1018 | 0 | UINT64_C(208109568), // VFCMP_SULE_D |
1019 | 0 | UINT64_C(207060992), // VFCMP_SULE_S |
1020 | 0 | UINT64_C(207978496), // VFCMP_SULT_D |
1021 | 0 | UINT64_C(206929920), // VFCMP_SULT_S |
1022 | 0 | UINT64_C(208437248), // VFCMP_SUNE_D |
1023 | 0 | UINT64_C(207388672), // VFCMP_SUNE_S |
1024 | 0 | UINT64_C(207912960), // VFCMP_SUN_D |
1025 | 0 | UINT64_C(206864384), // VFCMP_SUN_S |
1026 | 0 | UINT64_C(1922954240), // VFCVTH_D_S |
1027 | 0 | UINT64_C(1922952192), // VFCVTH_S_H |
1028 | 0 | UINT64_C(1922953216), // VFCVTL_D_S |
1029 | 0 | UINT64_C(1922951168), // VFCVTL_S_H |
1030 | 0 | UINT64_C(1900412928), // VFCVT_H_S |
1031 | 0 | UINT64_C(1900445696), // VFCVT_S_D |
1032 | 0 | UINT64_C(1899692032), // VFDIV_D |
1033 | 0 | UINT64_C(1899659264), // VFDIV_S |
1034 | 0 | UINT64_C(1922962432), // VFFINTH_D_W |
1035 | 0 | UINT64_C(1922961408), // VFFINTL_D_W |
1036 | 0 | UINT64_C(1922959360), // VFFINT_D_L |
1037 | 0 | UINT64_C(1922960384), // VFFINT_D_LU |
1038 | 0 | UINT64_C(1900544000), // VFFINT_S_L |
1039 | 0 | UINT64_C(1922957312), // VFFINT_S_W |
1040 | 0 | UINT64_C(1922958336), // VFFINT_S_WU |
1041 | 0 | UINT64_C(1922877440), // VFLOGB_D |
1042 | 0 | UINT64_C(1922876416), // VFLOGB_S |
1043 | 0 | UINT64_C(153092096), // VFMADD_D |
1044 | 0 | UINT64_C(152043520), // VFMADD_S |
1045 | 0 | UINT64_C(1900085248), // VFMAXA_D |
1046 | 0 | UINT64_C(1900052480), // VFMAXA_S |
1047 | 0 | UINT64_C(1899823104), // VFMAX_D |
1048 | 0 | UINT64_C(1899790336), // VFMAX_S |
1049 | 0 | UINT64_C(1900216320), // VFMINA_D |
1050 | 0 | UINT64_C(1900183552), // VFMINA_S |
1051 | 0 | UINT64_C(1899954176), // VFMIN_D |
1052 | 0 | UINT64_C(1899921408), // VFMIN_S |
1053 | 0 | UINT64_C(157286400), // VFMSUB_D |
1054 | 0 | UINT64_C(156237824), // VFMSUB_S |
1055 | 0 | UINT64_C(1899560960), // VFMUL_D |
1056 | 0 | UINT64_C(1899528192), // VFMUL_S |
1057 | 0 | UINT64_C(161480704), // VFNMADD_D |
1058 | 0 | UINT64_C(160432128), // VFNMADD_S |
1059 | 0 | UINT64_C(165675008), // VFNMSUB_D |
1060 | 0 | UINT64_C(164626432), // VFNMSUB_S |
1061 | 0 | UINT64_C(1922897920), // VFRECIPE_D |
1062 | 0 | UINT64_C(1922896896), // VFRECIPE_S |
1063 | 0 | UINT64_C(1922889728), // VFRECIP_D |
1064 | 0 | UINT64_C(1922888704), // VFRECIP_S |
1065 | 0 | UINT64_C(1922910208), // VFRINTRM_D |
1066 | 0 | UINT64_C(1922909184), // VFRINTRM_S |
1067 | 0 | UINT64_C(1922922496), // VFRINTRNE_D |
1068 | 0 | UINT64_C(1922921472), // VFRINTRNE_S |
1069 | 0 | UINT64_C(1922914304), // VFRINTRP_D |
1070 | 0 | UINT64_C(1922913280), // VFRINTRP_S |
1071 | 0 | UINT64_C(1922918400), // VFRINTRZ_D |
1072 | 0 | UINT64_C(1922917376), // VFRINTRZ_S |
1073 | 0 | UINT64_C(1922906112), // VFRINT_D |
1074 | 0 | UINT64_C(1922905088), // VFRINT_S |
1075 | 0 | UINT64_C(1922902016), // VFRSQRTE_D |
1076 | 0 | UINT64_C(1922900992), // VFRSQRTE_S |
1077 | 0 | UINT64_C(1922893824), // VFRSQRT_D |
1078 | 0 | UINT64_C(1922892800), // VFRSQRT_S |
1079 | 0 | UINT64_C(1922695168), // VFRSTPI_B |
1080 | 0 | UINT64_C(1922727936), // VFRSTPI_H |
1081 | 0 | UINT64_C(1898643456), // VFRSTP_B |
1082 | 0 | UINT64_C(1898676224), // VFRSTP_H |
1083 | 0 | UINT64_C(1922885632), // VFSQRT_D |
1084 | 0 | UINT64_C(1922884608), // VFSQRT_S |
1085 | 0 | UINT64_C(1899167744), // VFSUB_D |
1086 | 0 | UINT64_C(1899134976), // VFSUB_S |
1087 | 0 | UINT64_C(1922991104), // VFTINTH_L_S |
1088 | 0 | UINT64_C(1922990080), // VFTINTL_L_S |
1089 | 0 | UINT64_C(1922993152), // VFTINTRMH_L_S |
1090 | 0 | UINT64_C(1922992128), // VFTINTRML_L_S |
1091 | 0 | UINT64_C(1922972672), // VFTINTRM_L_D |
1092 | 0 | UINT64_C(1900675072), // VFTINTRM_W_D |
1093 | 0 | UINT64_C(1922971648), // VFTINTRM_W_S |
1094 | 0 | UINT64_C(1922999296), // VFTINTRNEH_L_S |
1095 | 0 | UINT64_C(1922998272), // VFTINTRNEL_L_S |
1096 | 0 | UINT64_C(1922978816), // VFTINTRNE_L_D |
1097 | 0 | UINT64_C(1900773376), // VFTINTRNE_W_D |
1098 | 0 | UINT64_C(1922977792), // VFTINTRNE_W_S |
1099 | 0 | UINT64_C(1922995200), // VFTINTRPH_L_S |
1100 | 0 | UINT64_C(1922994176), // VFTINTRPL_L_S |
1101 | 0 | UINT64_C(1922974720), // VFTINTRP_L_D |
1102 | 0 | UINT64_C(1900707840), // VFTINTRP_W_D |
1103 | 0 | UINT64_C(1922973696), // VFTINTRP_W_S |
1104 | 0 | UINT64_C(1922997248), // VFTINTRZH_L_S |
1105 | 0 | UINT64_C(1922996224), // VFTINTRZL_L_S |
1106 | 0 | UINT64_C(1922987008), // VFTINTRZ_LU_D |
1107 | 0 | UINT64_C(1922976768), // VFTINTRZ_L_D |
1108 | 0 | UINT64_C(1922985984), // VFTINTRZ_WU_S |
1109 | 0 | UINT64_C(1900740608), // VFTINTRZ_W_D |
1110 | 0 | UINT64_C(1922975744), // VFTINTRZ_W_S |
1111 | 0 | UINT64_C(1922980864), // VFTINT_LU_D |
1112 | 0 | UINT64_C(1922970624), // VFTINT_L_D |
1113 | 0 | UINT64_C(1922979840), // VFTINT_WU_S |
1114 | 0 | UINT64_C(1900642304), // VFTINT_W_D |
1115 | 0 | UINT64_C(1922969600), // VFTINT_W_S |
1116 | 0 | UINT64_C(1884880896), // VHADDW_DU_WU |
1117 | 0 | UINT64_C(1884618752), // VHADDW_D_W |
1118 | 0 | UINT64_C(1884815360), // VHADDW_HU_BU |
1119 | 0 | UINT64_C(1884553216), // VHADDW_H_B |
1120 | 0 | UINT64_C(1884913664), // VHADDW_QU_DU |
1121 | 0 | UINT64_C(1884651520), // VHADDW_Q_D |
1122 | 0 | UINT64_C(1884848128), // VHADDW_WU_HU |
1123 | 0 | UINT64_C(1884585984), // VHADDW_W_H |
1124 | 0 | UINT64_C(1885011968), // VHSUBW_DU_WU |
1125 | 0 | UINT64_C(1884749824), // VHSUBW_D_W |
1126 | 0 | UINT64_C(1884946432), // VHSUBW_HU_BU |
1127 | 0 | UINT64_C(1884684288), // VHSUBW_H_B |
1128 | 0 | UINT64_C(1885044736), // VHSUBW_QU_DU |
1129 | 0 | UINT64_C(1884782592), // VHSUBW_Q_D |
1130 | 0 | UINT64_C(1884979200), // VHSUBW_WU_HU |
1131 | 0 | UINT64_C(1884717056), // VHSUBW_W_H |
1132 | 0 | UINT64_C(1897660416), // VILVH_B |
1133 | 0 | UINT64_C(1897758720), // VILVH_D |
1134 | 0 | UINT64_C(1897693184), // VILVH_H |
1135 | 0 | UINT64_C(1897725952), // VILVH_W |
1136 | 0 | UINT64_C(1897529344), // VILVL_B |
1137 | 0 | UINT64_C(1897627648), // VILVL_D |
1138 | 0 | UINT64_C(1897562112), // VILVL_H |
1139 | 0 | UINT64_C(1897594880), // VILVL_W |
1140 | 0 | UINT64_C(1928036352), // VINSGR2VR_B |
1141 | 0 | UINT64_C(1928065024), // VINSGR2VR_D |
1142 | 0 | UINT64_C(1928052736), // VINSGR2VR_H |
1143 | 0 | UINT64_C(1928060928), // VINSGR2VR_W |
1144 | 0 | UINT64_C(738197504), // VLD |
1145 | 0 | UINT64_C(1944059904), // VLDI |
1146 | 0 | UINT64_C(813694976), // VLDREPL_B |
1147 | 0 | UINT64_C(806354944), // VLDREPL_D |
1148 | 0 | UINT64_C(809500672), // VLDREPL_H |
1149 | 0 | UINT64_C(807403520), // VLDREPL_W |
1150 | 0 | UINT64_C(943718400), // VLDX |
1151 | 0 | UINT64_C(1890385920), // VMADDWEV_D_W |
1152 | 0 | UINT64_C(1890910208), // VMADDWEV_D_WU |
1153 | 0 | UINT64_C(1891434496), // VMADDWEV_D_WU_W |
1154 | 0 | UINT64_C(1890320384), // VMADDWEV_H_B |
1155 | 0 | UINT64_C(1890844672), // VMADDWEV_H_BU |
1156 | 0 | UINT64_C(1891368960), // VMADDWEV_H_BU_B |
1157 | 0 | UINT64_C(1890418688), // VMADDWEV_Q_D |
1158 | 0 | UINT64_C(1890942976), // VMADDWEV_Q_DU |
1159 | 0 | UINT64_C(1891467264), // VMADDWEV_Q_DU_D |
1160 | 0 | UINT64_C(1890353152), // VMADDWEV_W_H |
1161 | 0 | UINT64_C(1890877440), // VMADDWEV_W_HU |
1162 | 0 | UINT64_C(1891401728), // VMADDWEV_W_HU_H |
1163 | 0 | UINT64_C(1890516992), // VMADDWOD_D_W |
1164 | 0 | UINT64_C(1891041280), // VMADDWOD_D_WU |
1165 | 0 | UINT64_C(1891565568), // VMADDWOD_D_WU_W |
1166 | 0 | UINT64_C(1890451456), // VMADDWOD_H_B |
1167 | 0 | UINT64_C(1890975744), // VMADDWOD_H_BU |
1168 | 0 | UINT64_C(1891500032), // VMADDWOD_H_BU_B |
1169 | 0 | UINT64_C(1890549760), // VMADDWOD_Q_D |
1170 | 0 | UINT64_C(1891074048), // VMADDWOD_Q_DU |
1171 | 0 | UINT64_C(1891598336), // VMADDWOD_Q_DU_D |
1172 | 0 | UINT64_C(1890484224), // VMADDWOD_W_H |
1173 | 0 | UINT64_C(1891008512), // VMADDWOD_W_HU |
1174 | 0 | UINT64_C(1891532800), // VMADDWOD_W_HU_H |
1175 | 0 | UINT64_C(1890058240), // VMADD_B |
1176 | 0 | UINT64_C(1890156544), // VMADD_D |
1177 | 0 | UINT64_C(1890091008), // VMADD_H |
1178 | 0 | UINT64_C(1890123776), // VMADD_W |
1179 | 0 | UINT64_C(1922039808), // VMAXI_B |
1180 | 0 | UINT64_C(1922301952), // VMAXI_BU |
1181 | 0 | UINT64_C(1922138112), // VMAXI_D |
1182 | 0 | UINT64_C(1922400256), // VMAXI_DU |
1183 | 0 | UINT64_C(1922072576), // VMAXI_H |
1184 | 0 | UINT64_C(1922334720), // VMAXI_HU |
1185 | 0 | UINT64_C(1922105344), // VMAXI_W |
1186 | 0 | UINT64_C(1922367488), // VMAXI_WU |
1187 | 0 | UINT64_C(1886388224), // VMAX_B |
1188 | 0 | UINT64_C(1886650368), // VMAX_BU |
1189 | 0 | UINT64_C(1886486528), // VMAX_D |
1190 | 0 | UINT64_C(1886748672), // VMAX_DU |
1191 | 0 | UINT64_C(1886420992), // VMAX_H |
1192 | 0 | UINT64_C(1886683136), // VMAX_HU |
1193 | 0 | UINT64_C(1886453760), // VMAX_W |
1194 | 0 | UINT64_C(1886715904), // VMAX_WU |
1195 | 0 | UINT64_C(1922170880), // VMINI_B |
1196 | 0 | UINT64_C(1922433024), // VMINI_BU |
1197 | 0 | UINT64_C(1922269184), // VMINI_D |
1198 | 0 | UINT64_C(1922531328), // VMINI_DU |
1199 | 0 | UINT64_C(1922203648), // VMINI_H |
1200 | 0 | UINT64_C(1922465792), // VMINI_HU |
1201 | 0 | UINT64_C(1922236416), // VMINI_W |
1202 | 0 | UINT64_C(1922498560), // VMINI_WU |
1203 | 0 | UINT64_C(1886519296), // VMIN_B |
1204 | 0 | UINT64_C(1886781440), // VMIN_BU |
1205 | 0 | UINT64_C(1886617600), // VMIN_D |
1206 | 0 | UINT64_C(1886879744), // VMIN_DU |
1207 | 0 | UINT64_C(1886552064), // VMIN_H |
1208 | 0 | UINT64_C(1886814208), // VMIN_HU |
1209 | 0 | UINT64_C(1886584832), // VMIN_W |
1210 | 0 | UINT64_C(1886846976), // VMIN_WU |
1211 | 0 | UINT64_C(1893859328), // VMOD_B |
1212 | 0 | UINT64_C(1894121472), // VMOD_BU |
1213 | 0 | UINT64_C(1893957632), // VMOD_D |
1214 | 0 | UINT64_C(1894219776), // VMOD_DU |
1215 | 0 | UINT64_C(1893892096), // VMOD_H |
1216 | 0 | UINT64_C(1894154240), // VMOD_HU |
1217 | 0 | UINT64_C(1893924864), // VMOD_W |
1218 | 0 | UINT64_C(1894187008), // VMOD_WU |
1219 | 0 | UINT64_C(1922846720), // VMSKGEZ_B |
1220 | 0 | UINT64_C(1922842624), // VMSKLTZ_B |
1221 | 0 | UINT64_C(1922845696), // VMSKLTZ_D |
1222 | 0 | UINT64_C(1922843648), // VMSKLTZ_H |
1223 | 0 | UINT64_C(1922844672), // VMSKLTZ_W |
1224 | 0 | UINT64_C(1922850816), // VMSKNZ_B |
1225 | 0 | UINT64_C(1890189312), // VMSUB_B |
1226 | 0 | UINT64_C(1890287616), // VMSUB_D |
1227 | 0 | UINT64_C(1890222080), // VMSUB_H |
1228 | 0 | UINT64_C(1890254848), // VMSUB_W |
1229 | 0 | UINT64_C(1887830016), // VMUH_B |
1230 | 0 | UINT64_C(1887961088), // VMUH_BU |
1231 | 0 | UINT64_C(1887928320), // VMUH_D |
1232 | 0 | UINT64_C(1888059392), // VMUH_DU |
1233 | 0 | UINT64_C(1887862784), // VMUH_H |
1234 | 0 | UINT64_C(1887993856), // VMUH_HU |
1235 | 0 | UINT64_C(1887895552), // VMUH_W |
1236 | 0 | UINT64_C(1888026624), // VMUH_WU |
1237 | 0 | UINT64_C(1888550912), // VMULWEV_D_W |
1238 | 0 | UINT64_C(1889075200), // VMULWEV_D_WU |
1239 | 0 | UINT64_C(1889599488), // VMULWEV_D_WU_W |
1240 | 0 | UINT64_C(1888485376), // VMULWEV_H_B |
1241 | 0 | UINT64_C(1889009664), // VMULWEV_H_BU |
1242 | 0 | UINT64_C(1889533952), // VMULWEV_H_BU_B |
1243 | 0 | UINT64_C(1888583680), // VMULWEV_Q_D |
1244 | 0 | UINT64_C(1889107968), // VMULWEV_Q_DU |
1245 | 0 | UINT64_C(1889632256), // VMULWEV_Q_DU_D |
1246 | 0 | UINT64_C(1888518144), // VMULWEV_W_H |
1247 | 0 | UINT64_C(1889042432), // VMULWEV_W_HU |
1248 | 0 | UINT64_C(1889566720), // VMULWEV_W_HU_H |
1249 | 0 | UINT64_C(1888681984), // VMULWOD_D_W |
1250 | 0 | UINT64_C(1889206272), // VMULWOD_D_WU |
1251 | 0 | UINT64_C(1889730560), // VMULWOD_D_WU_W |
1252 | 0 | UINT64_C(1888616448), // VMULWOD_H_B |
1253 | 0 | UINT64_C(1889140736), // VMULWOD_H_BU |
1254 | 0 | UINT64_C(1889665024), // VMULWOD_H_BU_B |
1255 | 0 | UINT64_C(1888714752), // VMULWOD_Q_D |
1256 | 0 | UINT64_C(1889239040), // VMULWOD_Q_DU |
1257 | 0 | UINT64_C(1889763328), // VMULWOD_Q_DU_D |
1258 | 0 | UINT64_C(1888649216), // VMULWOD_W_H |
1259 | 0 | UINT64_C(1889173504), // VMULWOD_W_HU |
1260 | 0 | UINT64_C(1889697792), // VMULWOD_W_HU_H |
1261 | 0 | UINT64_C(1887698944), // VMUL_B |
1262 | 0 | UINT64_C(1887797248), // VMUL_D |
1263 | 0 | UINT64_C(1887731712), // VMUL_H |
1264 | 0 | UINT64_C(1887764480), // VMUL_W |
1265 | 0 | UINT64_C(1922838528), // VNEG_B |
1266 | 0 | UINT64_C(1922841600), // VNEG_D |
1267 | 0 | UINT64_C(1922839552), // VNEG_H |
1268 | 0 | UINT64_C(1922840576), // VNEG_W |
1269 | 0 | UINT64_C(1943797760), // VNORI_B |
1270 | 0 | UINT64_C(1898414080), // VNOR_V |
1271 | 0 | UINT64_C(1943273472), // VORI_B |
1272 | 0 | UINT64_C(1898479616), // VORN_V |
1273 | 0 | UINT64_C(1898348544), // VOR_V |
1274 | 0 | UINT64_C(1897267200), // VPACKEV_B |
1275 | 0 | UINT64_C(1897365504), // VPACKEV_D |
1276 | 0 | UINT64_C(1897299968), // VPACKEV_H |
1277 | 0 | UINT64_C(1897332736), // VPACKEV_W |
1278 | 0 | UINT64_C(1897398272), // VPACKOD_B |
1279 | 0 | UINT64_C(1897496576), // VPACKOD_D |
1280 | 0 | UINT64_C(1897431040), // VPACKOD_H |
1281 | 0 | UINT64_C(1897463808), // VPACKOD_W |
1282 | 0 | UINT64_C(1922834432), // VPCNT_B |
1283 | 0 | UINT64_C(1922837504), // VPCNT_D |
1284 | 0 | UINT64_C(1922835456), // VPCNT_H |
1285 | 0 | UINT64_C(1922836480), // VPCNT_W |
1286 | 0 | UINT64_C(1944322048), // VPERMI_W |
1287 | 0 | UINT64_C(1897791488), // VPICKEV_B |
1288 | 0 | UINT64_C(1897889792), // VPICKEV_D |
1289 | 0 | UINT64_C(1897824256), // VPICKEV_H |
1290 | 0 | UINT64_C(1897857024), // VPICKEV_W |
1291 | 0 | UINT64_C(1897922560), // VPICKOD_B |
1292 | 0 | UINT64_C(1898020864), // VPICKOD_D |
1293 | 0 | UINT64_C(1897955328), // VPICKOD_H |
1294 | 0 | UINT64_C(1897988096), // VPICKOD_W |
1295 | 0 | UINT64_C(1928298496), // VPICKVE2GR_B |
1296 | 0 | UINT64_C(1928560640), // VPICKVE2GR_BU |
1297 | 0 | UINT64_C(1928327168), // VPICKVE2GR_D |
1298 | 0 | UINT64_C(1928589312), // VPICKVE2GR_DU |
1299 | 0 | UINT64_C(1928314880), // VPICKVE2GR_H |
1300 | 0 | UINT64_C(1928577024), // VPICKVE2GR_HU |
1301 | 0 | UINT64_C(1928323072), // VPICKVE2GR_W |
1302 | 0 | UINT64_C(1928585216), // VPICKVE2GR_WU |
1303 | 0 | UINT64_C(1923022848), // VREPLGR2VR_B |
1304 | 0 | UINT64_C(1923025920), // VREPLGR2VR_D |
1305 | 0 | UINT64_C(1923023872), // VREPLGR2VR_H |
1306 | 0 | UINT64_C(1923024896), // VREPLGR2VR_W |
1307 | 0 | UINT64_C(1928822784), // VREPLVEI_B |
1308 | 0 | UINT64_C(1928851456), // VREPLVEI_D |
1309 | 0 | UINT64_C(1928839168), // VREPLVEI_H |
1310 | 0 | UINT64_C(1928847360), // VREPLVEI_W |
1311 | 0 | UINT64_C(1898053632), // VREPLVE_B |
1312 | 0 | UINT64_C(1898151936), // VREPLVE_D |
1313 | 0 | UINT64_C(1898086400), // VREPLVE_H |
1314 | 0 | UINT64_C(1898119168), // VREPLVE_W |
1315 | 0 | UINT64_C(1923096576), // VROTRI_B |
1316 | 0 | UINT64_C(1923153920), // VROTRI_D |
1317 | 0 | UINT64_C(1923104768), // VROTRI_H |
1318 | 0 | UINT64_C(1923121152), // VROTRI_W |
1319 | 0 | UINT64_C(1894645760), // VROTR_B |
1320 | 0 | UINT64_C(1894744064), // VROTR_D |
1321 | 0 | UINT64_C(1894678528), // VROTR_H |
1322 | 0 | UINT64_C(1894711296), // VROTR_W |
1323 | 0 | UINT64_C(1883635712), // VSADD_B |
1324 | 0 | UINT64_C(1883897856), // VSADD_BU |
1325 | 0 | UINT64_C(1883734016), // VSADD_D |
1326 | 0 | UINT64_C(1883996160), // VSADD_DU |
1327 | 0 | UINT64_C(1883668480), // VSADD_H |
1328 | 0 | UINT64_C(1883930624), // VSADD_HU |
1329 | 0 | UINT64_C(1883701248), // VSADD_W |
1330 | 0 | UINT64_C(1883963392), // VSADD_WU |
1331 | 0 | UINT64_C(1931747328), // VSAT_B |
1332 | 0 | UINT64_C(1932009472), // VSAT_BU |
1333 | 0 | UINT64_C(1931804672), // VSAT_D |
1334 | 0 | UINT64_C(1932066816), // VSAT_DU |
1335 | 0 | UINT64_C(1931755520), // VSAT_H |
1336 | 0 | UINT64_C(1932017664), // VSAT_HU |
1337 | 0 | UINT64_C(1931771904), // VSAT_W |
1338 | 0 | UINT64_C(1932034048), // VSAT_WU |
1339 | 0 | UINT64_C(1920991232), // VSEQI_B |
1340 | 0 | UINT64_C(1921089536), // VSEQI_D |
1341 | 0 | UINT64_C(1921024000), // VSEQI_H |
1342 | 0 | UINT64_C(1921056768), // VSEQI_W |
1343 | 0 | UINT64_C(1879048192), // VSEQ_B |
1344 | 0 | UINT64_C(1879146496), // VSEQ_D |
1345 | 0 | UINT64_C(1879080960), // VSEQ_H |
1346 | 0 | UINT64_C(1879113728), // VSEQ_W |
1347 | 0 | UINT64_C(1922871296), // VSETALLNEZ_B |
1348 | 0 | UINT64_C(1922874368), // VSETALLNEZ_D |
1349 | 0 | UINT64_C(1922872320), // VSETALLNEZ_H |
1350 | 0 | UINT64_C(1922873344), // VSETALLNEZ_W |
1351 | 0 | UINT64_C(1922867200), // VSETANYEQZ_B |
1352 | 0 | UINT64_C(1922870272), // VSETANYEQZ_D |
1353 | 0 | UINT64_C(1922868224), // VSETANYEQZ_H |
1354 | 0 | UINT64_C(1922869248), // VSETANYEQZ_W |
1355 | 0 | UINT64_C(1922865152), // VSETEQZ_V |
1356 | 0 | UINT64_C(1922866176), // VSETNEZ_V |
1357 | 0 | UINT64_C(1938817024), // VSHUF4I_B |
1358 | 0 | UINT64_C(1939603456), // VSHUF4I_D |
1359 | 0 | UINT64_C(1939079168), // VSHUF4I_H |
1360 | 0 | UINT64_C(1939341312), // VSHUF4I_W |
1361 | 0 | UINT64_C(223346688), // VSHUF_B |
1362 | 0 | UINT64_C(1903919104), // VSHUF_D |
1363 | 0 | UINT64_C(1903853568), // VSHUF_H |
1364 | 0 | UINT64_C(1903886336), // VSHUF_W |
1365 | 0 | UINT64_C(1898840064), // VSIGNCOV_B |
1366 | 0 | UINT64_C(1898938368), // VSIGNCOV_D |
1367 | 0 | UINT64_C(1898872832), // VSIGNCOV_H |
1368 | 0 | UINT64_C(1898905600), // VSIGNCOV_W |
1369 | 0 | UINT64_C(1921122304), // VSLEI_B |
1370 | 0 | UINT64_C(1921253376), // VSLEI_BU |
1371 | 0 | UINT64_C(1921220608), // VSLEI_D |
1372 | 0 | UINT64_C(1921351680), // VSLEI_DU |
1373 | 0 | UINT64_C(1921155072), // VSLEI_H |
1374 | 0 | UINT64_C(1921286144), // VSLEI_HU |
1375 | 0 | UINT64_C(1921187840), // VSLEI_W |
1376 | 0 | UINT64_C(1921318912), // VSLEI_WU |
1377 | 0 | UINT64_C(1879179264), // VSLE_B |
1378 | 0 | UINT64_C(1879310336), // VSLE_BU |
1379 | 0 | UINT64_C(1879277568), // VSLE_D |
1380 | 0 | UINT64_C(1879408640), // VSLE_DU |
1381 | 0 | UINT64_C(1879212032), // VSLE_H |
1382 | 0 | UINT64_C(1879343104), // VSLE_HU |
1383 | 0 | UINT64_C(1879244800), // VSLE_W |
1384 | 0 | UINT64_C(1879375872), // VSLE_WU |
1385 | 0 | UINT64_C(1932271616), // VSLLI_B |
1386 | 0 | UINT64_C(1932328960), // VSLLI_D |
1387 | 0 | UINT64_C(1932279808), // VSLLI_H |
1388 | 0 | UINT64_C(1932296192), // VSLLI_W |
1389 | 0 | UINT64_C(1930199040), // VSLLWIL_DU_WU |
1390 | 0 | UINT64_C(1929936896), // VSLLWIL_D_W |
1391 | 0 | UINT64_C(1930174464), // VSLLWIL_HU_BU |
1392 | 0 | UINT64_C(1929912320), // VSLLWIL_H_B |
1393 | 0 | UINT64_C(1930182656), // VSLLWIL_WU_HU |
1394 | 0 | UINT64_C(1929920512), // VSLLWIL_W_H |
1395 | 0 | UINT64_C(1894252544), // VSLL_B |
1396 | 0 | UINT64_C(1894350848), // VSLL_D |
1397 | 0 | UINT64_C(1894285312), // VSLL_H |
1398 | 0 | UINT64_C(1894318080), // VSLL_W |
1399 | 0 | UINT64_C(1921384448), // VSLTI_B |
1400 | 0 | UINT64_C(1921515520), // VSLTI_BU |
1401 | 0 | UINT64_C(1921482752), // VSLTI_D |
1402 | 0 | UINT64_C(1921613824), // VSLTI_DU |
1403 | 0 | UINT64_C(1921417216), // VSLTI_H |
1404 | 0 | UINT64_C(1921548288), // VSLTI_HU |
1405 | 0 | UINT64_C(1921449984), // VSLTI_W |
1406 | 0 | UINT64_C(1921581056), // VSLTI_WU |
1407 | 0 | UINT64_C(1879441408), // VSLT_B |
1408 | 0 | UINT64_C(1879572480), // VSLT_BU |
1409 | 0 | UINT64_C(1879539712), // VSLT_D |
1410 | 0 | UINT64_C(1879670784), // VSLT_DU |
1411 | 0 | UINT64_C(1879474176), // VSLT_H |
1412 | 0 | UINT64_C(1879605248), // VSLT_HU |
1413 | 0 | UINT64_C(1879506944), // VSLT_W |
1414 | 0 | UINT64_C(1879638016), // VSLT_WU |
1415 | 0 | UINT64_C(1932795904), // VSRAI_B |
1416 | 0 | UINT64_C(1932853248), // VSRAI_D |
1417 | 0 | UINT64_C(1932804096), // VSRAI_H |
1418 | 0 | UINT64_C(1932820480), // VSRAI_W |
1419 | 0 | UINT64_C(1935163392), // VSRANI_B_H |
1420 | 0 | UINT64_C(1935278080), // VSRANI_D_Q |
1421 | 0 | UINT64_C(1935179776), // VSRANI_H_W |
1422 | 0 | UINT64_C(1935212544), // VSRANI_W_D |
1423 | 0 | UINT64_C(1895202816), // VSRAN_B_H |
1424 | 0 | UINT64_C(1895235584), // VSRAN_H_W |
1425 | 0 | UINT64_C(1895268352), // VSRAN_W_D |
1426 | 0 | UINT64_C(1923620864), // VSRARI_B |
1427 | 0 | UINT64_C(1923678208), // VSRARI_D |
1428 | 0 | UINT64_C(1923629056), // VSRARI_H |
1429 | 0 | UINT64_C(1923645440), // VSRARI_W |
1430 | 0 | UINT64_C(1935425536), // VSRARNI_B_H |
1431 | 0 | UINT64_C(1935540224), // VSRARNI_D_Q |
1432 | 0 | UINT64_C(1935441920), // VSRARNI_H_W |
1433 | 0 | UINT64_C(1935474688), // VSRARNI_W_D |
1434 | 0 | UINT64_C(1895464960), // VSRARN_B_H |
1435 | 0 | UINT64_C(1895497728), // VSRARN_H_W |
1436 | 0 | UINT64_C(1895530496), // VSRARN_W_D |
1437 | 0 | UINT64_C(1894907904), // VSRAR_B |
1438 | 0 | UINT64_C(1895006208), // VSRAR_D |
1439 | 0 | UINT64_C(1894940672), // VSRAR_H |
1440 | 0 | UINT64_C(1894973440), // VSRAR_W |
1441 | 0 | UINT64_C(1894514688), // VSRA_B |
1442 | 0 | UINT64_C(1894612992), // VSRA_D |
1443 | 0 | UINT64_C(1894547456), // VSRA_H |
1444 | 0 | UINT64_C(1894580224), // VSRA_W |
1445 | 0 | UINT64_C(1932533760), // VSRLI_B |
1446 | 0 | UINT64_C(1932591104), // VSRLI_D |
1447 | 0 | UINT64_C(1932541952), // VSRLI_H |
1448 | 0 | UINT64_C(1932558336), // VSRLI_W |
1449 | 0 | UINT64_C(1933590528), // VSRLNI_B_H |
1450 | 0 | UINT64_C(1933705216), // VSRLNI_D_Q |
1451 | 0 | UINT64_C(1933606912), // VSRLNI_H_W |
1452 | 0 | UINT64_C(1933639680), // VSRLNI_W_D |
1453 | 0 | UINT64_C(1895071744), // VSRLN_B_H |
1454 | 0 | UINT64_C(1895104512), // VSRLN_H_W |
1455 | 0 | UINT64_C(1895137280), // VSRLN_W_D |
1456 | 0 | UINT64_C(1923358720), // VSRLRI_B |
1457 | 0 | UINT64_C(1923416064), // VSRLRI_D |
1458 | 0 | UINT64_C(1923366912), // VSRLRI_H |
1459 | 0 | UINT64_C(1923383296), // VSRLRI_W |
1460 | 0 | UINT64_C(1933852672), // VSRLRNI_B_H |
1461 | 0 | UINT64_C(1933967360), // VSRLRNI_D_Q |
1462 | 0 | UINT64_C(1933869056), // VSRLRNI_H_W |
1463 | 0 | UINT64_C(1933901824), // VSRLRNI_W_D |
1464 | 0 | UINT64_C(1895333888), // VSRLRN_B_H |
1465 | 0 | UINT64_C(1895366656), // VSRLRN_H_W |
1466 | 0 | UINT64_C(1895399424), // VSRLRN_W_D |
1467 | 0 | UINT64_C(1894776832), // VSRLR_B |
1468 | 0 | UINT64_C(1894875136), // VSRLR_D |
1469 | 0 | UINT64_C(1894809600), // VSRLR_H |
1470 | 0 | UINT64_C(1894842368), // VSRLR_W |
1471 | 0 | UINT64_C(1894383616), // VSRL_B |
1472 | 0 | UINT64_C(1894481920), // VSRL_D |
1473 | 0 | UINT64_C(1894416384), // VSRL_H |
1474 | 0 | UINT64_C(1894449152), // VSRL_W |
1475 | 0 | UINT64_C(1935949824), // VSSRANI_BU_H |
1476 | 0 | UINT64_C(1935687680), // VSSRANI_B_H |
1477 | 0 | UINT64_C(1936064512), // VSSRANI_DU_Q |
1478 | 0 | UINT64_C(1935802368), // VSSRANI_D_Q |
1479 | 0 | UINT64_C(1935966208), // VSSRANI_HU_W |
1480 | 0 | UINT64_C(1935704064), // VSSRANI_H_W |
1481 | 0 | UINT64_C(1935998976), // VSSRANI_WU_D |
1482 | 0 | UINT64_C(1935736832), // VSSRANI_W_D |
1483 | 0 | UINT64_C(1896251392), // VSSRAN_BU_H |
1484 | 0 | UINT64_C(1895727104), // VSSRAN_B_H |
1485 | 0 | UINT64_C(1896284160), // VSSRAN_HU_W |
1486 | 0 | UINT64_C(1895759872), // VSSRAN_H_W |
1487 | 0 | UINT64_C(1896316928), // VSSRAN_WU_D |
1488 | 0 | UINT64_C(1895792640), // VSSRAN_W_D |
1489 | 0 | UINT64_C(1936474112), // VSSRARNI_BU_H |
1490 | 0 | UINT64_C(1936211968), // VSSRARNI_B_H |
1491 | 0 | UINT64_C(1936588800), // VSSRARNI_DU_Q |
1492 | 0 | UINT64_C(1936326656), // VSSRARNI_D_Q |
1493 | 0 | UINT64_C(1936490496), // VSSRARNI_HU_W |
1494 | 0 | UINT64_C(1936228352), // VSSRARNI_H_W |
1495 | 0 | UINT64_C(1936523264), // VSSRARNI_WU_D |
1496 | 0 | UINT64_C(1936261120), // VSSRARNI_W_D |
1497 | 0 | UINT64_C(1896513536), // VSSRARN_BU_H |
1498 | 0 | UINT64_C(1895989248), // VSSRARN_B_H |
1499 | 0 | UINT64_C(1896546304), // VSSRARN_HU_W |
1500 | 0 | UINT64_C(1896022016), // VSSRARN_H_W |
1501 | 0 | UINT64_C(1896579072), // VSSRARN_WU_D |
1502 | 0 | UINT64_C(1896054784), // VSSRARN_W_D |
1503 | 0 | UINT64_C(1934376960), // VSSRLNI_BU_H |
1504 | 0 | UINT64_C(1934114816), // VSSRLNI_B_H |
1505 | 0 | UINT64_C(1934491648), // VSSRLNI_DU_Q |
1506 | 0 | UINT64_C(1934229504), // VSSRLNI_D_Q |
1507 | 0 | UINT64_C(1934393344), // VSSRLNI_HU_W |
1508 | 0 | UINT64_C(1934131200), // VSSRLNI_H_W |
1509 | 0 | UINT64_C(1934426112), // VSSRLNI_WU_D |
1510 | 0 | UINT64_C(1934163968), // VSSRLNI_W_D |
1511 | 0 | UINT64_C(1896120320), // VSSRLN_BU_H |
1512 | 0 | UINT64_C(1895596032), // VSSRLN_B_H |
1513 | 0 | UINT64_C(1896153088), // VSSRLN_HU_W |
1514 | 0 | UINT64_C(1895628800), // VSSRLN_H_W |
1515 | 0 | UINT64_C(1896185856), // VSSRLN_WU_D |
1516 | 0 | UINT64_C(1895661568), // VSSRLN_W_D |
1517 | 0 | UINT64_C(1934901248), // VSSRLRNI_BU_H |
1518 | 0 | UINT64_C(1934639104), // VSSRLRNI_B_H |
1519 | 0 | UINT64_C(1935015936), // VSSRLRNI_DU_Q |
1520 | 0 | UINT64_C(1934753792), // VSSRLRNI_D_Q |
1521 | 0 | UINT64_C(1934917632), // VSSRLRNI_HU_W |
1522 | 0 | UINT64_C(1934655488), // VSSRLRNI_H_W |
1523 | 0 | UINT64_C(1934950400), // VSSRLRNI_WU_D |
1524 | 0 | UINT64_C(1934688256), // VSSRLRNI_W_D |
1525 | 0 | UINT64_C(1896382464), // VSSRLRN_BU_H |
1526 | 0 | UINT64_C(1895858176), // VSSRLRN_B_H |
1527 | 0 | UINT64_C(1896415232), // VSSRLRN_HU_W |
1528 | 0 | UINT64_C(1895890944), // VSSRLRN_H_W |
1529 | 0 | UINT64_C(1896448000), // VSSRLRN_WU_D |
1530 | 0 | UINT64_C(1895923712), // VSSRLRN_W_D |
1531 | 0 | UINT64_C(1883766784), // VSSUB_B |
1532 | 0 | UINT64_C(1884028928), // VSSUB_BU |
1533 | 0 | UINT64_C(1883865088), // VSSUB_D |
1534 | 0 | UINT64_C(1884127232), // VSSUB_DU |
1535 | 0 | UINT64_C(1883799552), // VSSUB_H |
1536 | 0 | UINT64_C(1884061696), // VSSUB_HU |
1537 | 0 | UINT64_C(1883832320), // VSSUB_W |
1538 | 0 | UINT64_C(1884094464), // VSSUB_WU |
1539 | 0 | UINT64_C(742391808), // VST |
1540 | 0 | UINT64_C(830472192), // VSTELM_B |
1541 | 0 | UINT64_C(823132160), // VSTELM_D |
1542 | 0 | UINT64_C(826277888), // VSTELM_H |
1543 | 0 | UINT64_C(824180736), // VSTELM_W |
1544 | 0 | UINT64_C(943980544), // VSTX |
1545 | 0 | UINT64_C(1921777664), // VSUBI_BU |
1546 | 0 | UINT64_C(1921875968), // VSUBI_DU |
1547 | 0 | UINT64_C(1921810432), // VSUBI_HU |
1548 | 0 | UINT64_C(1921843200), // VSUBI_WU |
1549 | 0 | UINT64_C(1881210880), // VSUBWEV_D_W |
1550 | 0 | UINT64_C(1882259456), // VSUBWEV_D_WU |
1551 | 0 | UINT64_C(1881145344), // VSUBWEV_H_B |
1552 | 0 | UINT64_C(1882193920), // VSUBWEV_H_BU |
1553 | 0 | UINT64_C(1881243648), // VSUBWEV_Q_D |
1554 | 0 | UINT64_C(1882292224), // VSUBWEV_Q_DU |
1555 | 0 | UINT64_C(1881178112), // VSUBWEV_W_H |
1556 | 0 | UINT64_C(1882226688), // VSUBWEV_W_HU |
1557 | 0 | UINT64_C(1881473024), // VSUBWOD_D_W |
1558 | 0 | UINT64_C(1882521600), // VSUBWOD_D_WU |
1559 | 0 | UINT64_C(1881407488), // VSUBWOD_H_B |
1560 | 0 | UINT64_C(1882456064), // VSUBWOD_H_BU |
1561 | 0 | UINT64_C(1881505792), // VSUBWOD_Q_D |
1562 | 0 | UINT64_C(1882554368), // VSUBWOD_Q_DU |
1563 | 0 | UINT64_C(1881440256), // VSUBWOD_W_H |
1564 | 0 | UINT64_C(1882488832), // VSUBWOD_W_HU |
1565 | 0 | UINT64_C(1879834624), // VSUB_B |
1566 | 0 | UINT64_C(1879932928), // VSUB_D |
1567 | 0 | UINT64_C(1879867392), // VSUB_H |
1568 | 0 | UINT64_C(1898807296), // VSUB_Q |
1569 | 0 | UINT64_C(1879900160), // VSUB_W |
1570 | 0 | UINT64_C(1943535616), // VXORI_B |
1571 | 0 | UINT64_C(1898381312), // VXOR_V |
1572 | 0 | UINT64_C(4128780), // X86ADC_B |
1573 | 0 | UINT64_C(4128783), // X86ADC_D |
1574 | 0 | UINT64_C(4128781), // X86ADC_H |
1575 | 0 | UINT64_C(4128782), // X86ADC_W |
1576 | 0 | UINT64_C(4128772), // X86ADD_B |
1577 | 0 | UINT64_C(4128775), // X86ADD_D |
1578 | 0 | UINT64_C(4128769), // X86ADD_DU |
1579 | 0 | UINT64_C(4128773), // X86ADD_H |
1580 | 0 | UINT64_C(4128774), // X86ADD_W |
1581 | 0 | UINT64_C(4128768), // X86ADD_WU |
1582 | 0 | UINT64_C(4161552), // X86AND_B |
1583 | 0 | UINT64_C(4161555), // X86AND_D |
1584 | 0 | UINT64_C(4161553), // X86AND_H |
1585 | 0 | UINT64_C(4161554), // X86AND_W |
1586 | 0 | UINT64_C(32808), // X86CLRTM |
1587 | 0 | UINT64_C(32809), // X86DECTOP |
1588 | 0 | UINT64_C(32772), // X86DEC_B |
1589 | 0 | UINT64_C(32775), // X86DEC_D |
1590 | 0 | UINT64_C(32773), // X86DEC_H |
1591 | 0 | UINT64_C(32774), // X86DEC_W |
1592 | 0 | UINT64_C(32777), // X86INCTOP |
1593 | 0 | UINT64_C(32768), // X86INC_B |
1594 | 0 | UINT64_C(32771), // X86INC_D |
1595 | 0 | UINT64_C(32769), // X86INC_H |
1596 | 0 | UINT64_C(32770), // X86INC_W |
1597 | 0 | UINT64_C(6029312), // X86MFFLAG |
1598 | 0 | UINT64_C(29696), // X86MFTOP |
1599 | 0 | UINT64_C(6029344), // X86MTFLAG |
1600 | 0 | UINT64_C(28672), // X86MTTOP |
1601 | 0 | UINT64_C(4096000), // X86MUL_B |
1602 | 0 | UINT64_C(4096004), // X86MUL_BU |
1603 | 0 | UINT64_C(4096003), // X86MUL_D |
1604 | 0 | UINT64_C(4096007), // X86MUL_DU |
1605 | 0 | UINT64_C(4096001), // X86MUL_H |
1606 | 0 | UINT64_C(4096005), // X86MUL_HU |
1607 | 0 | UINT64_C(4096002), // X86MUL_W |
1608 | 0 | UINT64_C(4096006), // X86MUL_WU |
1609 | 0 | UINT64_C(4161556), // X86OR_B |
1610 | 0 | UINT64_C(4161559), // X86OR_D |
1611 | 0 | UINT64_C(4161557), // X86OR_H |
1612 | 0 | UINT64_C(4161558), // X86OR_W |
1613 | 0 | UINT64_C(5513240), // X86RCLI_B |
1614 | 0 | UINT64_C(5570587), // X86RCLI_D |
1615 | 0 | UINT64_C(5521433), // X86RCLI_H |
1616 | 0 | UINT64_C(5537818), // X86RCLI_W |
1617 | 0 | UINT64_C(4161548), // X86RCL_B |
1618 | 0 | UINT64_C(4161551), // X86RCL_D |
1619 | 0 | UINT64_C(4161549), // X86RCL_H |
1620 | 0 | UINT64_C(4161550), // X86RCL_W |
1621 | 0 | UINT64_C(5513232), // X86RCRI_B |
1622 | 0 | UINT64_C(5570579), // X86RCRI_D |
1623 | 0 | UINT64_C(5521425), // X86RCRI_H |
1624 | 0 | UINT64_C(5537810), // X86RCRI_W |
1625 | 0 | UINT64_C(4161544), // X86RCR_B |
1626 | 0 | UINT64_C(4161547), // X86RCR_D |
1627 | 0 | UINT64_C(4161545), // X86RCR_H |
1628 | 0 | UINT64_C(4161546), // X86RCR_W |
1629 | 0 | UINT64_C(5513236), // X86ROTLI_B |
1630 | 0 | UINT64_C(5570583), // X86ROTLI_D |
1631 | 0 | UINT64_C(5521429), // X86ROTLI_H |
1632 | 0 | UINT64_C(5537814), // X86ROTLI_W |
1633 | 0 | UINT64_C(4161540), // X86ROTL_B |
1634 | 0 | UINT64_C(4161543), // X86ROTL_D |
1635 | 0 | UINT64_C(4161541), // X86ROTL_H |
1636 | 0 | UINT64_C(4161542), // X86ROTL_W |
1637 | 0 | UINT64_C(5513228), // X86ROTRI_B |
1638 | 0 | UINT64_C(5570575), // X86ROTRI_D |
1639 | 0 | UINT64_C(5521421), // X86ROTRI_H |
1640 | 0 | UINT64_C(5537806), // X86ROTRI_W |
1641 | 0 | UINT64_C(4161536), // X86ROTR_B |
1642 | 0 | UINT64_C(4161538), // X86ROTR_D |
1643 | 0 | UINT64_C(4161537), // X86ROTR_H |
1644 | 0 | UINT64_C(4161539), // X86ROTR_W |
1645 | 0 | UINT64_C(4128784), // X86SBC_B |
1646 | 0 | UINT64_C(4128787), // X86SBC_D |
1647 | 0 | UINT64_C(4128785), // X86SBC_H |
1648 | 0 | UINT64_C(4128786), // X86SBC_W |
1649 | 0 | UINT64_C(5767168), // X86SETTAG |
1650 | 0 | UINT64_C(32776), // X86SETTM |
1651 | 0 | UINT64_C(5513216), // X86SLLI_B |
1652 | 0 | UINT64_C(5570563), // X86SLLI_D |
1653 | 0 | UINT64_C(5521409), // X86SLLI_H |
1654 | 0 | UINT64_C(5537794), // X86SLLI_W |
1655 | 0 | UINT64_C(4128788), // X86SLL_B |
1656 | 0 | UINT64_C(4128791), // X86SLL_D |
1657 | 0 | UINT64_C(4128789), // X86SLL_H |
1658 | 0 | UINT64_C(4128790), // X86SLL_W |
1659 | 0 | UINT64_C(5513224), // X86SRAI_B |
1660 | 0 | UINT64_C(5570571), // X86SRAI_D |
1661 | 0 | UINT64_C(5521417), // X86SRAI_H |
1662 | 0 | UINT64_C(5537802), // X86SRAI_W |
1663 | 0 | UINT64_C(4128796), // X86SRA_B |
1664 | 0 | UINT64_C(4128799), // X86SRA_D |
1665 | 0 | UINT64_C(4128797), // X86SRA_H |
1666 | 0 | UINT64_C(4128798), // X86SRA_W |
1667 | 0 | UINT64_C(5513220), // X86SRLI_B |
1668 | 0 | UINT64_C(5570567), // X86SRLI_D |
1669 | 0 | UINT64_C(5521413), // X86SRLI_H |
1670 | 0 | UINT64_C(5537798), // X86SRLI_W |
1671 | 0 | UINT64_C(4128792), // X86SRL_B |
1672 | 0 | UINT64_C(4128795), // X86SRL_D |
1673 | 0 | UINT64_C(4128793), // X86SRL_H |
1674 | 0 | UINT64_C(4128794), // X86SRL_W |
1675 | 0 | UINT64_C(4128776), // X86SUB_B |
1676 | 0 | UINT64_C(4128779), // X86SUB_D |
1677 | 0 | UINT64_C(4128771), // X86SUB_DU |
1678 | 0 | UINT64_C(4128777), // X86SUB_H |
1679 | 0 | UINT64_C(4128778), // X86SUB_W |
1680 | 0 | UINT64_C(4128770), // X86SUB_WU |
1681 | 0 | UINT64_C(4161560), // X86XOR_B |
1682 | 0 | UINT64_C(4161563), // X86XOR_D |
1683 | 0 | UINT64_C(4161561), // X86XOR_H |
1684 | 0 | UINT64_C(4161562), // X86XOR_W |
1685 | 0 | UINT64_C(1409024), // XOR |
1686 | 0 | UINT64_C(62914560), // XORI |
1687 | 0 | UINT64_C(1952448512), // XVABSD_B |
1688 | 0 | UINT64_C(1952579584), // XVABSD_BU |
1689 | 0 | UINT64_C(1952546816), // XVABSD_D |
1690 | 0 | UINT64_C(1952677888), // XVABSD_DU |
1691 | 0 | UINT64_C(1952481280), // XVABSD_H |
1692 | 0 | UINT64_C(1952612352), // XVABSD_HU |
1693 | 0 | UINT64_C(1952514048), // XVABSD_W |
1694 | 0 | UINT64_C(1952645120), // XVABSD_WU |
1695 | 0 | UINT64_C(1952186368), // XVADDA_B |
1696 | 0 | UINT64_C(1952284672), // XVADDA_D |
1697 | 0 | UINT64_C(1952219136), // XVADDA_H |
1698 | 0 | UINT64_C(1952251904), // XVADDA_W |
1699 | 0 | UINT64_C(1988755456), // XVADDI_BU |
1700 | 0 | UINT64_C(1988853760), // XVADDI_DU |
1701 | 0 | UINT64_C(1988788224), // XVADDI_HU |
1702 | 0 | UINT64_C(1988820992), // XVADDI_WU |
1703 | 0 | UINT64_C(1948188672), // XVADDWEV_D_W |
1704 | 0 | UINT64_C(1949237248), // XVADDWEV_D_WU |
1705 | 0 | UINT64_C(1950285824), // XVADDWEV_D_WU_W |
1706 | 0 | UINT64_C(1948123136), // XVADDWEV_H_B |
1707 | 0 | UINT64_C(1949171712), // XVADDWEV_H_BU |
1708 | 0 | UINT64_C(1950220288), // XVADDWEV_H_BU_B |
1709 | 0 | UINT64_C(1948221440), // XVADDWEV_Q_D |
1710 | 0 | UINT64_C(1949270016), // XVADDWEV_Q_DU |
1711 | 0 | UINT64_C(1950318592), // XVADDWEV_Q_DU_D |
1712 | 0 | UINT64_C(1948155904), // XVADDWEV_W_H |
1713 | 0 | UINT64_C(1949204480), // XVADDWEV_W_HU |
1714 | 0 | UINT64_C(1950253056), // XVADDWEV_W_HU_H |
1715 | 0 | UINT64_C(1948450816), // XVADDWOD_D_W |
1716 | 0 | UINT64_C(1949499392), // XVADDWOD_D_WU |
1717 | 0 | UINT64_C(1950416896), // XVADDWOD_D_WU_W |
1718 | 0 | UINT64_C(1948385280), // XVADDWOD_H_B |
1719 | 0 | UINT64_C(1949433856), // XVADDWOD_H_BU |
1720 | 0 | UINT64_C(1950351360), // XVADDWOD_H_BU_B |
1721 | 0 | UINT64_C(1948483584), // XVADDWOD_Q_D |
1722 | 0 | UINT64_C(1949532160), // XVADDWOD_Q_DU |
1723 | 0 | UINT64_C(1950449664), // XVADDWOD_Q_DU_D |
1724 | 0 | UINT64_C(1948418048), // XVADDWOD_W_H |
1725 | 0 | UINT64_C(1949466624), // XVADDWOD_W_HU |
1726 | 0 | UINT64_C(1950384128), // XVADDWOD_W_HU_H |
1727 | 0 | UINT64_C(1946812416), // XVADD_B |
1728 | 0 | UINT64_C(1946910720), // XVADD_D |
1729 | 0 | UINT64_C(1946845184), // XVADD_H |
1730 | 0 | UINT64_C(1965883392), // XVADD_Q |
1731 | 0 | UINT64_C(1946877952), // XVADD_W |
1732 | 0 | UINT64_C(2010120192), // XVANDI_B |
1733 | 0 | UINT64_C(1965555712), // XVANDN_V |
1734 | 0 | UINT64_C(1965424640), // XVAND_V |
1735 | 0 | UINT64_C(1952972800), // XVAVGR_B |
1736 | 0 | UINT64_C(1953103872), // XVAVGR_BU |
1737 | 0 | UINT64_C(1953071104), // XVAVGR_D |
1738 | 0 | UINT64_C(1953202176), // XVAVGR_DU |
1739 | 0 | UINT64_C(1953005568), // XVAVGR_H |
1740 | 0 | UINT64_C(1953136640), // XVAVGR_HU |
1741 | 0 | UINT64_C(1953038336), // XVAVGR_W |
1742 | 0 | UINT64_C(1953169408), // XVAVGR_WU |
1743 | 0 | UINT64_C(1952710656), // XVAVG_B |
1744 | 0 | UINT64_C(1952841728), // XVAVG_BU |
1745 | 0 | UINT64_C(1952808960), // XVAVG_D |
1746 | 0 | UINT64_C(1952940032), // XVAVG_DU |
1747 | 0 | UINT64_C(1952743424), // XVAVG_H |
1748 | 0 | UINT64_C(1952874496), // XVAVG_HU |
1749 | 0 | UINT64_C(1952776192), // XVAVG_W |
1750 | 0 | UINT64_C(1952907264), // XVAVG_WU |
1751 | 0 | UINT64_C(1997545472), // XVBITCLRI_B |
1752 | 0 | UINT64_C(1997602816), // XVBITCLRI_D |
1753 | 0 | UINT64_C(1997553664), // XVBITCLRI_H |
1754 | 0 | UINT64_C(1997570048), // XVBITCLRI_W |
1755 | 0 | UINT64_C(1963720704), // XVBITCLR_B |
1756 | 0 | UINT64_C(1963819008), // XVBITCLR_D |
1757 | 0 | UINT64_C(1963753472), // XVBITCLR_H |
1758 | 0 | UINT64_C(1963786240), // XVBITCLR_W |
1759 | 0 | UINT64_C(1998069760), // XVBITREVI_B |
1760 | 0 | UINT64_C(1998127104), // XVBITREVI_D |
1761 | 0 | UINT64_C(1998077952), // XVBITREVI_H |
1762 | 0 | UINT64_C(1998094336), // XVBITREVI_W |
1763 | 0 | UINT64_C(1963982848), // XVBITREV_B |
1764 | 0 | UINT64_C(1964081152), // XVBITREV_D |
1765 | 0 | UINT64_C(1964015616), // XVBITREV_H |
1766 | 0 | UINT64_C(1964048384), // XVBITREV_W |
1767 | 0 | UINT64_C(2009333760), // XVBITSELI_B |
1768 | 0 | UINT64_C(220200960), // XVBITSEL_V |
1769 | 0 | UINT64_C(1997807616), // XVBITSETI_B |
1770 | 0 | UINT64_C(1997864960), // XVBITSETI_D |
1771 | 0 | UINT64_C(1997815808), // XVBITSETI_H |
1772 | 0 | UINT64_C(1997832192), // XVBITSETI_W |
1773 | 0 | UINT64_C(1963851776), // XVBITSET_B |
1774 | 0 | UINT64_C(1963950080), // XVBITSET_D |
1775 | 0 | UINT64_C(1963884544), // XVBITSET_H |
1776 | 0 | UINT64_C(1963917312), // XVBITSET_W |
1777 | 0 | UINT64_C(1989017600), // XVBSLL_V |
1778 | 0 | UINT64_C(1989050368), // XVBSRL_V |
1779 | 0 | UINT64_C(1989935104), // XVCLO_B |
1780 | 0 | UINT64_C(1989938176), // XVCLO_D |
1781 | 0 | UINT64_C(1989936128), // XVCLO_H |
1782 | 0 | UINT64_C(1989937152), // XVCLO_W |
1783 | 0 | UINT64_C(1989939200), // XVCLZ_B |
1784 | 0 | UINT64_C(1989942272), // XVCLZ_D |
1785 | 0 | UINT64_C(1989940224), // XVCLZ_H |
1786 | 0 | UINT64_C(1989941248), // XVCLZ_W |
1787 | 0 | UINT64_C(1960837120), // XVDIV_B |
1788 | 0 | UINT64_C(1961099264), // XVDIV_BU |
1789 | 0 | UINT64_C(1960935424), // XVDIV_D |
1790 | 0 | UINT64_C(1961197568), // XVDIV_DU |
1791 | 0 | UINT64_C(1960869888), // XVDIV_H |
1792 | 0 | UINT64_C(1961132032), // XVDIV_HU |
1793 | 0 | UINT64_C(1960902656), // XVDIV_W |
1794 | 0 | UINT64_C(1961164800), // XVDIV_WU |
1795 | 0 | UINT64_C(1990129664), // XVEXTH_DU_WU |
1796 | 0 | UINT64_C(1990125568), // XVEXTH_D_W |
1797 | 0 | UINT64_C(1990127616), // XVEXTH_HU_BU |
1798 | 0 | UINT64_C(1990123520), // XVEXTH_H_B |
1799 | 0 | UINT64_C(1990130688), // XVEXTH_QU_DU |
1800 | 0 | UINT64_C(1990126592), // XVEXTH_Q_D |
1801 | 0 | UINT64_C(1990128640), // XVEXTH_WU_HU |
1802 | 0 | UINT64_C(1990124544), // XVEXTH_W_H |
1803 | 0 | UINT64_C(1997340672), // XVEXTL_QU_DU |
1804 | 0 | UINT64_C(1997078528), // XVEXTL_Q_D |
1805 | 0 | UINT64_C(2005663744), // XVEXTRINS_B |
1806 | 0 | UINT64_C(2004877312), // XVEXTRINS_D |
1807 | 0 | UINT64_C(2005401600), // XVEXTRINS_H |
1808 | 0 | UINT64_C(2005139456), // XVEXTRINS_W |
1809 | 0 | UINT64_C(1966145536), // XVFADD_D |
1810 | 0 | UINT64_C(1966112768), // XVFADD_S |
1811 | 0 | UINT64_C(1989990400), // XVFCLASS_D |
1812 | 0 | UINT64_C(1989989376), // XVFCLASS_S |
1813 | 0 | UINT64_C(211812352), // XVFCMP_CAF_D |
1814 | 0 | UINT64_C(210763776), // XVFCMP_CAF_S |
1815 | 0 | UINT64_C(211943424), // XVFCMP_CEQ_D |
1816 | 0 | UINT64_C(210894848), // XVFCMP_CEQ_S |
1817 | 0 | UINT64_C(212008960), // XVFCMP_CLE_D |
1818 | 0 | UINT64_C(210960384), // XVFCMP_CLE_S |
1819 | 0 | UINT64_C(211877888), // XVFCMP_CLT_D |
1820 | 0 | UINT64_C(210829312), // XVFCMP_CLT_S |
1821 | 0 | UINT64_C(212336640), // XVFCMP_CNE_D |
1822 | 0 | UINT64_C(211288064), // XVFCMP_CNE_S |
1823 | 0 | UINT64_C(212467712), // XVFCMP_COR_D |
1824 | 0 | UINT64_C(211419136), // XVFCMP_COR_S |
1825 | 0 | UINT64_C(212205568), // XVFCMP_CUEQ_D |
1826 | 0 | UINT64_C(211156992), // XVFCMP_CUEQ_S |
1827 | 0 | UINT64_C(212271104), // XVFCMP_CULE_D |
1828 | 0 | UINT64_C(211222528), // XVFCMP_CULE_S |
1829 | 0 | UINT64_C(212140032), // XVFCMP_CULT_D |
1830 | 0 | UINT64_C(211091456), // XVFCMP_CULT_S |
1831 | 0 | UINT64_C(212598784), // XVFCMP_CUNE_D |
1832 | 0 | UINT64_C(211550208), // XVFCMP_CUNE_S |
1833 | 0 | UINT64_C(212074496), // XVFCMP_CUN_D |
1834 | 0 | UINT64_C(211025920), // XVFCMP_CUN_S |
1835 | 0 | UINT64_C(211845120), // XVFCMP_SAF_D |
1836 | 0 | UINT64_C(210796544), // XVFCMP_SAF_S |
1837 | 0 | UINT64_C(211976192), // XVFCMP_SEQ_D |
1838 | 0 | UINT64_C(210927616), // XVFCMP_SEQ_S |
1839 | 0 | UINT64_C(212041728), // XVFCMP_SLE_D |
1840 | 0 | UINT64_C(210993152), // XVFCMP_SLE_S |
1841 | 0 | UINT64_C(211910656), // XVFCMP_SLT_D |
1842 | 0 | UINT64_C(210862080), // XVFCMP_SLT_S |
1843 | 0 | UINT64_C(212369408), // XVFCMP_SNE_D |
1844 | 0 | UINT64_C(211320832), // XVFCMP_SNE_S |
1845 | 0 | UINT64_C(212500480), // XVFCMP_SOR_D |
1846 | 0 | UINT64_C(211451904), // XVFCMP_SOR_S |
1847 | 0 | UINT64_C(212238336), // XVFCMP_SUEQ_D |
1848 | 0 | UINT64_C(211189760), // XVFCMP_SUEQ_S |
1849 | 0 | UINT64_C(212303872), // XVFCMP_SULE_D |
1850 | 0 | UINT64_C(211255296), // XVFCMP_SULE_S |
1851 | 0 | UINT64_C(212172800), // XVFCMP_SULT_D |
1852 | 0 | UINT64_C(211124224), // XVFCMP_SULT_S |
1853 | 0 | UINT64_C(212631552), // XVFCMP_SUNE_D |
1854 | 0 | UINT64_C(211582976), // XVFCMP_SUNE_S |
1855 | 0 | UINT64_C(212107264), // XVFCMP_SUN_D |
1856 | 0 | UINT64_C(211058688), // XVFCMP_SUN_S |
1857 | 0 | UINT64_C(1990063104), // XVFCVTH_D_S |
1858 | 0 | UINT64_C(1990061056), // XVFCVTH_S_H |
1859 | 0 | UINT64_C(1990062080), // XVFCVTL_D_S |
1860 | 0 | UINT64_C(1990060032), // XVFCVTL_S_H |
1861 | 0 | UINT64_C(1967521792), // XVFCVT_H_S |
1862 | 0 | UINT64_C(1967554560), // XVFCVT_S_D |
1863 | 0 | UINT64_C(1966800896), // XVFDIV_D |
1864 | 0 | UINT64_C(1966768128), // XVFDIV_S |
1865 | 0 | UINT64_C(1990071296), // XVFFINTH_D_W |
1866 | 0 | UINT64_C(1990070272), // XVFFINTL_D_W |
1867 | 0 | UINT64_C(1990068224), // XVFFINT_D_L |
1868 | 0 | UINT64_C(1990069248), // XVFFINT_D_LU |
1869 | 0 | UINT64_C(1967652864), // XVFFINT_S_L |
1870 | 0 | UINT64_C(1990066176), // XVFFINT_S_W |
1871 | 0 | UINT64_C(1990067200), // XVFFINT_S_WU |
1872 | 0 | UINT64_C(1989986304), // XVFLOGB_D |
1873 | 0 | UINT64_C(1989985280), // XVFLOGB_S |
1874 | 0 | UINT64_C(169869312), // XVFMADD_D |
1875 | 0 | UINT64_C(168820736), // XVFMADD_S |
1876 | 0 | UINT64_C(1967194112), // XVFMAXA_D |
1877 | 0 | UINT64_C(1967161344), // XVFMAXA_S |
1878 | 0 | UINT64_C(1966931968), // XVFMAX_D |
1879 | 0 | UINT64_C(1966899200), // XVFMAX_S |
1880 | 0 | UINT64_C(1967325184), // XVFMINA_D |
1881 | 0 | UINT64_C(1967292416), // XVFMINA_S |
1882 | 0 | UINT64_C(1967063040), // XVFMIN_D |
1883 | 0 | UINT64_C(1967030272), // XVFMIN_S |
1884 | 0 | UINT64_C(174063616), // XVFMSUB_D |
1885 | 0 | UINT64_C(173015040), // XVFMSUB_S |
1886 | 0 | UINT64_C(1966669824), // XVFMUL_D |
1887 | 0 | UINT64_C(1966637056), // XVFMUL_S |
1888 | 0 | UINT64_C(178257920), // XVFNMADD_D |
1889 | 0 | UINT64_C(177209344), // XVFNMADD_S |
1890 | 0 | UINT64_C(182452224), // XVFNMSUB_D |
1891 | 0 | UINT64_C(181403648), // XVFNMSUB_S |
1892 | 0 | UINT64_C(1990006784), // XVFRECIPE_D |
1893 | 0 | UINT64_C(1990005760), // XVFRECIPE_S |
1894 | 0 | UINT64_C(1989998592), // XVFRECIP_D |
1895 | 0 | UINT64_C(1989997568), // XVFRECIP_S |
1896 | 0 | UINT64_C(1990019072), // XVFRINTRM_D |
1897 | 0 | UINT64_C(1990018048), // XVFRINTRM_S |
1898 | 0 | UINT64_C(1990031360), // XVFRINTRNE_D |
1899 | 0 | UINT64_C(1990030336), // XVFRINTRNE_S |
1900 | 0 | UINT64_C(1990023168), // XVFRINTRP_D |
1901 | 0 | UINT64_C(1990022144), // XVFRINTRP_S |
1902 | 0 | UINT64_C(1990027264), // XVFRINTRZ_D |
1903 | 0 | UINT64_C(1990026240), // XVFRINTRZ_S |
1904 | 0 | UINT64_C(1990014976), // XVFRINT_D |
1905 | 0 | UINT64_C(1990013952), // XVFRINT_S |
1906 | 0 | UINT64_C(1990010880), // XVFRSQRTE_D |
1907 | 0 | UINT64_C(1990009856), // XVFRSQRTE_S |
1908 | 0 | UINT64_C(1990002688), // XVFRSQRT_D |
1909 | 0 | UINT64_C(1990001664), // XVFRSQRT_S |
1910 | 0 | UINT64_C(1989804032), // XVFRSTPI_B |
1911 | 0 | UINT64_C(1989836800), // XVFRSTPI_H |
1912 | 0 | UINT64_C(1965752320), // XVFRSTP_B |
1913 | 0 | UINT64_C(1965785088), // XVFRSTP_H |
1914 | 0 | UINT64_C(1989994496), // XVFSQRT_D |
1915 | 0 | UINT64_C(1989993472), // XVFSQRT_S |
1916 | 0 | UINT64_C(1966276608), // XVFSUB_D |
1917 | 0 | UINT64_C(1966243840), // XVFSUB_S |
1918 | 0 | UINT64_C(1990099968), // XVFTINTH_L_S |
1919 | 0 | UINT64_C(1990098944), // XVFTINTL_L_S |
1920 | 0 | UINT64_C(1990102016), // XVFTINTRMH_L_S |
1921 | 0 | UINT64_C(1990100992), // XVFTINTRML_L_S |
1922 | 0 | UINT64_C(1990081536), // XVFTINTRM_L_D |
1923 | 0 | UINT64_C(1967783936), // XVFTINTRM_W_D |
1924 | 0 | UINT64_C(1990080512), // XVFTINTRM_W_S |
1925 | 0 | UINT64_C(1990108160), // XVFTINTRNEH_L_S |
1926 | 0 | UINT64_C(1990107136), // XVFTINTRNEL_L_S |
1927 | 0 | UINT64_C(1990087680), // XVFTINTRNE_L_D |
1928 | 0 | UINT64_C(1967882240), // XVFTINTRNE_W_D |
1929 | 0 | UINT64_C(1990086656), // XVFTINTRNE_W_S |
1930 | 0 | UINT64_C(1990104064), // XVFTINTRPH_L_S |
1931 | 0 | UINT64_C(1990103040), // XVFTINTRPL_L_S |
1932 | 0 | UINT64_C(1990083584), // XVFTINTRP_L_D |
1933 | 0 | UINT64_C(1967816704), // XVFTINTRP_W_D |
1934 | 0 | UINT64_C(1990082560), // XVFTINTRP_W_S |
1935 | 0 | UINT64_C(1990106112), // XVFTINTRZH_L_S |
1936 | 0 | UINT64_C(1990105088), // XVFTINTRZL_L_S |
1937 | 0 | UINT64_C(1990095872), // XVFTINTRZ_LU_D |
1938 | 0 | UINT64_C(1990085632), // XVFTINTRZ_L_D |
1939 | 0 | UINT64_C(1990094848), // XVFTINTRZ_WU_S |
1940 | 0 | UINT64_C(1967849472), // XVFTINTRZ_W_D |
1941 | 0 | UINT64_C(1990084608), // XVFTINTRZ_W_S |
1942 | 0 | UINT64_C(1990089728), // XVFTINT_LU_D |
1943 | 0 | UINT64_C(1990079488), // XVFTINT_L_D |
1944 | 0 | UINT64_C(1990088704), // XVFTINT_WU_S |
1945 | 0 | UINT64_C(1967751168), // XVFTINT_W_D |
1946 | 0 | UINT64_C(1990078464), // XVFTINT_W_S |
1947 | 0 | UINT64_C(1951989760), // XVHADDW_DU_WU |
1948 | 0 | UINT64_C(1951727616), // XVHADDW_D_W |
1949 | 0 | UINT64_C(1951924224), // XVHADDW_HU_BU |
1950 | 0 | UINT64_C(1951662080), // XVHADDW_H_B |
1951 | 0 | UINT64_C(1952022528), // XVHADDW_QU_DU |
1952 | 0 | UINT64_C(1951760384), // XVHADDW_Q_D |
1953 | 0 | UINT64_C(1951956992), // XVHADDW_WU_HU |
1954 | 0 | UINT64_C(1951694848), // XVHADDW_W_H |
1955 | 0 | UINT64_C(1990164480), // XVHSELI_D |
1956 | 0 | UINT64_C(1952120832), // XVHSUBW_DU_WU |
1957 | 0 | UINT64_C(1951858688), // XVHSUBW_D_W |
1958 | 0 | UINT64_C(1952055296), // XVHSUBW_HU_BU |
1959 | 0 | UINT64_C(1951793152), // XVHSUBW_H_B |
1960 | 0 | UINT64_C(1952153600), // XVHSUBW_QU_DU |
1961 | 0 | UINT64_C(1951891456), // XVHSUBW_Q_D |
1962 | 0 | UINT64_C(1952088064), // XVHSUBW_WU_HU |
1963 | 0 | UINT64_C(1951825920), // XVHSUBW_W_H |
1964 | 0 | UINT64_C(1964769280), // XVILVH_B |
1965 | 0 | UINT64_C(1964867584), // XVILVH_D |
1966 | 0 | UINT64_C(1964802048), // XVILVH_H |
1967 | 0 | UINT64_C(1964834816), // XVILVH_W |
1968 | 0 | UINT64_C(1964638208), // XVILVL_B |
1969 | 0 | UINT64_C(1964736512), // XVILVL_D |
1970 | 0 | UINT64_C(1964670976), // XVILVL_H |
1971 | 0 | UINT64_C(1964703744), // XVILVL_W |
1972 | 0 | UINT64_C(1995169792), // XVINSGR2VR_D |
1973 | 0 | UINT64_C(1995161600), // XVINSGR2VR_W |
1974 | 0 | UINT64_C(1996480512), // XVINSVE0_D |
1975 | 0 | UINT64_C(1996472320), // XVINSVE0_W |
1976 | 0 | UINT64_C(746586112), // XVLD |
1977 | 0 | UINT64_C(2011168768), // XVLDI |
1978 | 0 | UINT64_C(847249408), // XVLDREPL_B |
1979 | 0 | UINT64_C(839909376), // XVLDREPL_D |
1980 | 0 | UINT64_C(843055104), // XVLDREPL_H |
1981 | 0 | UINT64_C(840957952), // XVLDREPL_W |
1982 | 0 | UINT64_C(944242688), // XVLDX |
1983 | 0 | UINT64_C(1957494784), // XVMADDWEV_D_W |
1984 | 0 | UINT64_C(1958019072), // XVMADDWEV_D_WU |
1985 | 0 | UINT64_C(1958543360), // XVMADDWEV_D_WU_W |
1986 | 0 | UINT64_C(1957429248), // XVMADDWEV_H_B |
1987 | 0 | UINT64_C(1957953536), // XVMADDWEV_H_BU |
1988 | 0 | UINT64_C(1958477824), // XVMADDWEV_H_BU_B |
1989 | 0 | UINT64_C(1957527552), // XVMADDWEV_Q_D |
1990 | 0 | UINT64_C(1958051840), // XVMADDWEV_Q_DU |
1991 | 0 | UINT64_C(1958576128), // XVMADDWEV_Q_DU_D |
1992 | 0 | UINT64_C(1957462016), // XVMADDWEV_W_H |
1993 | 0 | UINT64_C(1957986304), // XVMADDWEV_W_HU |
1994 | 0 | UINT64_C(1958510592), // XVMADDWEV_W_HU_H |
1995 | 0 | UINT64_C(1957625856), // XVMADDWOD_D_W |
1996 | 0 | UINT64_C(1958150144), // XVMADDWOD_D_WU |
1997 | 0 | UINT64_C(1958674432), // XVMADDWOD_D_WU_W |
1998 | 0 | UINT64_C(1957560320), // XVMADDWOD_H_B |
1999 | 0 | UINT64_C(1958084608), // XVMADDWOD_H_BU |
2000 | 0 | UINT64_C(1958608896), // XVMADDWOD_H_BU_B |
2001 | 0 | UINT64_C(1957658624), // XVMADDWOD_Q_D |
2002 | 0 | UINT64_C(1958182912), // XVMADDWOD_Q_DU |
2003 | 0 | UINT64_C(1958707200), // XVMADDWOD_Q_DU_D |
2004 | 0 | UINT64_C(1957593088), // XVMADDWOD_W_H |
2005 | 0 | UINT64_C(1958117376), // XVMADDWOD_W_HU |
2006 | 0 | UINT64_C(1958641664), // XVMADDWOD_W_HU_H |
2007 | 0 | UINT64_C(1957167104), // XVMADD_B |
2008 | 0 | UINT64_C(1957265408), // XVMADD_D |
2009 | 0 | UINT64_C(1957199872), // XVMADD_H |
2010 | 0 | UINT64_C(1957232640), // XVMADD_W |
2011 | 0 | UINT64_C(1989148672), // XVMAXI_B |
2012 | 0 | UINT64_C(1989410816), // XVMAXI_BU |
2013 | 0 | UINT64_C(1989246976), // XVMAXI_D |
2014 | 0 | UINT64_C(1989509120), // XVMAXI_DU |
2015 | 0 | UINT64_C(1989181440), // XVMAXI_H |
2016 | 0 | UINT64_C(1989443584), // XVMAXI_HU |
2017 | 0 | UINT64_C(1989214208), // XVMAXI_W |
2018 | 0 | UINT64_C(1989476352), // XVMAXI_WU |
2019 | 0 | UINT64_C(1953497088), // XVMAX_B |
2020 | 0 | UINT64_C(1953759232), // XVMAX_BU |
2021 | 0 | UINT64_C(1953595392), // XVMAX_D |
2022 | 0 | UINT64_C(1953857536), // XVMAX_DU |
2023 | 0 | UINT64_C(1953529856), // XVMAX_H |
2024 | 0 | UINT64_C(1953792000), // XVMAX_HU |
2025 | 0 | UINT64_C(1953562624), // XVMAX_W |
2026 | 0 | UINT64_C(1953824768), // XVMAX_WU |
2027 | 0 | UINT64_C(1989279744), // XVMINI_B |
2028 | 0 | UINT64_C(1989541888), // XVMINI_BU |
2029 | 0 | UINT64_C(1989378048), // XVMINI_D |
2030 | 0 | UINT64_C(1989640192), // XVMINI_DU |
2031 | 0 | UINT64_C(1989312512), // XVMINI_H |
2032 | 0 | UINT64_C(1989574656), // XVMINI_HU |
2033 | 0 | UINT64_C(1989345280), // XVMINI_W |
2034 | 0 | UINT64_C(1989607424), // XVMINI_WU |
2035 | 0 | UINT64_C(1953628160), // XVMIN_B |
2036 | 0 | UINT64_C(1953890304), // XVMIN_BU |
2037 | 0 | UINT64_C(1953726464), // XVMIN_D |
2038 | 0 | UINT64_C(1953988608), // XVMIN_DU |
2039 | 0 | UINT64_C(1953660928), // XVMIN_H |
2040 | 0 | UINT64_C(1953923072), // XVMIN_HU |
2041 | 0 | UINT64_C(1953693696), // XVMIN_W |
2042 | 0 | UINT64_C(1953955840), // XVMIN_WU |
2043 | 0 | UINT64_C(1960968192), // XVMOD_B |
2044 | 0 | UINT64_C(1961230336), // XVMOD_BU |
2045 | 0 | UINT64_C(1961066496), // XVMOD_D |
2046 | 0 | UINT64_C(1961328640), // XVMOD_DU |
2047 | 0 | UINT64_C(1961000960), // XVMOD_H |
2048 | 0 | UINT64_C(1961263104), // XVMOD_HU |
2049 | 0 | UINT64_C(1961033728), // XVMOD_W |
2050 | 0 | UINT64_C(1961295872), // XVMOD_WU |
2051 | 0 | UINT64_C(1989955584), // XVMSKGEZ_B |
2052 | 0 | UINT64_C(1989951488), // XVMSKLTZ_B |
2053 | 0 | UINT64_C(1989954560), // XVMSKLTZ_D |
2054 | 0 | UINT64_C(1989952512), // XVMSKLTZ_H |
2055 | 0 | UINT64_C(1989953536), // XVMSKLTZ_W |
2056 | 0 | UINT64_C(1989959680), // XVMSKNZ_B |
2057 | 0 | UINT64_C(1957298176), // XVMSUB_B |
2058 | 0 | UINT64_C(1957396480), // XVMSUB_D |
2059 | 0 | UINT64_C(1957330944), // XVMSUB_H |
2060 | 0 | UINT64_C(1957363712), // XVMSUB_W |
2061 | 0 | UINT64_C(1954938880), // XVMUH_B |
2062 | 0 | UINT64_C(1955069952), // XVMUH_BU |
2063 | 0 | UINT64_C(1955037184), // XVMUH_D |
2064 | 0 | UINT64_C(1955168256), // XVMUH_DU |
2065 | 0 | UINT64_C(1954971648), // XVMUH_H |
2066 | 0 | UINT64_C(1955102720), // XVMUH_HU |
2067 | 0 | UINT64_C(1955004416), // XVMUH_W |
2068 | 0 | UINT64_C(1955135488), // XVMUH_WU |
2069 | 0 | UINT64_C(1955659776), // XVMULWEV_D_W |
2070 | 0 | UINT64_C(1956184064), // XVMULWEV_D_WU |
2071 | 0 | UINT64_C(1956708352), // XVMULWEV_D_WU_W |
2072 | 0 | UINT64_C(1955594240), // XVMULWEV_H_B |
2073 | 0 | UINT64_C(1956118528), // XVMULWEV_H_BU |
2074 | 0 | UINT64_C(1956642816), // XVMULWEV_H_BU_B |
2075 | 0 | UINT64_C(1955692544), // XVMULWEV_Q_D |
2076 | 0 | UINT64_C(1956216832), // XVMULWEV_Q_DU |
2077 | 0 | UINT64_C(1956741120), // XVMULWEV_Q_DU_D |
2078 | 0 | UINT64_C(1955627008), // XVMULWEV_W_H |
2079 | 0 | UINT64_C(1956151296), // XVMULWEV_W_HU |
2080 | 0 | UINT64_C(1956675584), // XVMULWEV_W_HU_H |
2081 | 0 | UINT64_C(1955790848), // XVMULWOD_D_W |
2082 | 0 | UINT64_C(1956315136), // XVMULWOD_D_WU |
2083 | 0 | UINT64_C(1956839424), // XVMULWOD_D_WU_W |
2084 | 0 | UINT64_C(1955725312), // XVMULWOD_H_B |
2085 | 0 | UINT64_C(1956249600), // XVMULWOD_H_BU |
2086 | 0 | UINT64_C(1956773888), // XVMULWOD_H_BU_B |
2087 | 0 | UINT64_C(1955823616), // XVMULWOD_Q_D |
2088 | 0 | UINT64_C(1956347904), // XVMULWOD_Q_DU |
2089 | 0 | UINT64_C(1956872192), // XVMULWOD_Q_DU_D |
2090 | 0 | UINT64_C(1955758080), // XVMULWOD_W_H |
2091 | 0 | UINT64_C(1956282368), // XVMULWOD_W_HU |
2092 | 0 | UINT64_C(1956806656), // XVMULWOD_W_HU_H |
2093 | 0 | UINT64_C(1954807808), // XVMUL_B |
2094 | 0 | UINT64_C(1954906112), // XVMUL_D |
2095 | 0 | UINT64_C(1954840576), // XVMUL_H |
2096 | 0 | UINT64_C(1954873344), // XVMUL_W |
2097 | 0 | UINT64_C(1989947392), // XVNEG_B |
2098 | 0 | UINT64_C(1989950464), // XVNEG_D |
2099 | 0 | UINT64_C(1989948416), // XVNEG_H |
2100 | 0 | UINT64_C(1989949440), // XVNEG_W |
2101 | 0 | UINT64_C(2010906624), // XVNORI_B |
2102 | 0 | UINT64_C(1965522944), // XVNOR_V |
2103 | 0 | UINT64_C(2010382336), // XVORI_B |
2104 | 0 | UINT64_C(1965588480), // XVORN_V |
2105 | 0 | UINT64_C(1965457408), // XVOR_V |
2106 | 0 | UINT64_C(1964376064), // XVPACKEV_B |
2107 | 0 | UINT64_C(1964474368), // XVPACKEV_D |
2108 | 0 | UINT64_C(1964408832), // XVPACKEV_H |
2109 | 0 | UINT64_C(1964441600), // XVPACKEV_W |
2110 | 0 | UINT64_C(1964507136), // XVPACKOD_B |
2111 | 0 | UINT64_C(1964605440), // XVPACKOD_D |
2112 | 0 | UINT64_C(1964539904), // XVPACKOD_H |
2113 | 0 | UINT64_C(1964572672), // XVPACKOD_W |
2114 | 0 | UINT64_C(1989943296), // XVPCNT_B |
2115 | 0 | UINT64_C(1989946368), // XVPCNT_D |
2116 | 0 | UINT64_C(1989944320), // XVPCNT_H |
2117 | 0 | UINT64_C(1989945344), // XVPCNT_W |
2118 | 0 | UINT64_C(2011693056), // XVPERMI_D |
2119 | 0 | UINT64_C(2011955200), // XVPERMI_Q |
2120 | 0 | UINT64_C(2011430912), // XVPERMI_W |
2121 | 0 | UINT64_C(1971126272), // XVPERM_W |
2122 | 0 | UINT64_C(1964900352), // XVPICKEV_B |
2123 | 0 | UINT64_C(1964998656), // XVPICKEV_D |
2124 | 0 | UINT64_C(1964933120), // XVPICKEV_H |
2125 | 0 | UINT64_C(1964965888), // XVPICKEV_W |
2126 | 0 | UINT64_C(1965031424), // XVPICKOD_B |
2127 | 0 | UINT64_C(1965129728), // XVPICKOD_D |
2128 | 0 | UINT64_C(1965064192), // XVPICKOD_H |
2129 | 0 | UINT64_C(1965096960), // XVPICKOD_W |
2130 | 0 | UINT64_C(1995431936), // XVPICKVE2GR_D |
2131 | 0 | UINT64_C(1995694080), // XVPICKVE2GR_DU |
2132 | 0 | UINT64_C(1995423744), // XVPICKVE2GR_W |
2133 | 0 | UINT64_C(1995685888), // XVPICKVE2GR_WU |
2134 | 0 | UINT64_C(1996742656), // XVPICKVE_D |
2135 | 0 | UINT64_C(1996734464), // XVPICKVE_W |
2136 | 0 | UINT64_C(1995931648), // XVREPL128VEI_B |
2137 | 0 | UINT64_C(1995960320), // XVREPL128VEI_D |
2138 | 0 | UINT64_C(1995948032), // XVREPL128VEI_H |
2139 | 0 | UINT64_C(1995956224), // XVREPL128VEI_W |
2140 | 0 | UINT64_C(1990131712), // XVREPLGR2VR_B |
2141 | 0 | UINT64_C(1990134784), // XVREPLGR2VR_D |
2142 | 0 | UINT64_C(1990132736), // XVREPLGR2VR_H |
2143 | 0 | UINT64_C(1990133760), // XVREPLGR2VR_W |
2144 | 0 | UINT64_C(1996947456), // XVREPLVE0_B |
2145 | 0 | UINT64_C(1997004800), // XVREPLVE0_D |
2146 | 0 | UINT64_C(1996980224), // XVREPLVE0_H |
2147 | 0 | UINT64_C(1997008896), // XVREPLVE0_Q |
2148 | 0 | UINT64_C(1996996608), // XVREPLVE0_W |
2149 | 0 | UINT64_C(1965162496), // XVREPLVE_B |
2150 | 0 | UINT64_C(1965260800), // XVREPLVE_D |
2151 | 0 | UINT64_C(1965195264), // XVREPLVE_H |
2152 | 0 | UINT64_C(1965228032), // XVREPLVE_W |
2153 | 0 | UINT64_C(1990205440), // XVROTRI_B |
2154 | 0 | UINT64_C(1990262784), // XVROTRI_D |
2155 | 0 | UINT64_C(1990213632), // XVROTRI_H |
2156 | 0 | UINT64_C(1990230016), // XVROTRI_W |
2157 | 0 | UINT64_C(1961754624), // XVROTR_B |
2158 | 0 | UINT64_C(1961852928), // XVROTR_D |
2159 | 0 | UINT64_C(1961787392), // XVROTR_H |
2160 | 0 | UINT64_C(1961820160), // XVROTR_W |
2161 | 0 | UINT64_C(1950744576), // XVSADD_B |
2162 | 0 | UINT64_C(1951006720), // XVSADD_BU |
2163 | 0 | UINT64_C(1950842880), // XVSADD_D |
2164 | 0 | UINT64_C(1951105024), // XVSADD_DU |
2165 | 0 | UINT64_C(1950777344), // XVSADD_H |
2166 | 0 | UINT64_C(1951039488), // XVSADD_HU |
2167 | 0 | UINT64_C(1950810112), // XVSADD_W |
2168 | 0 | UINT64_C(1951072256), // XVSADD_WU |
2169 | 0 | UINT64_C(1998856192), // XVSAT_B |
2170 | 0 | UINT64_C(1999118336), // XVSAT_BU |
2171 | 0 | UINT64_C(1998913536), // XVSAT_D |
2172 | 0 | UINT64_C(1999175680), // XVSAT_DU |
2173 | 0 | UINT64_C(1998864384), // XVSAT_H |
2174 | 0 | UINT64_C(1999126528), // XVSAT_HU |
2175 | 0 | UINT64_C(1998880768), // XVSAT_W |
2176 | 0 | UINT64_C(1999142912), // XVSAT_WU |
2177 | 0 | UINT64_C(1988100096), // XVSEQI_B |
2178 | 0 | UINT64_C(1988198400), // XVSEQI_D |
2179 | 0 | UINT64_C(1988132864), // XVSEQI_H |
2180 | 0 | UINT64_C(1988165632), // XVSEQI_W |
2181 | 0 | UINT64_C(1946157056), // XVSEQ_B |
2182 | 0 | UINT64_C(1946255360), // XVSEQ_D |
2183 | 0 | UINT64_C(1946189824), // XVSEQ_H |
2184 | 0 | UINT64_C(1946222592), // XVSEQ_W |
2185 | 0 | UINT64_C(1989980160), // XVSETALLNEZ_B |
2186 | 0 | UINT64_C(1989983232), // XVSETALLNEZ_D |
2187 | 0 | UINT64_C(1989981184), // XVSETALLNEZ_H |
2188 | 0 | UINT64_C(1989982208), // XVSETALLNEZ_W |
2189 | 0 | UINT64_C(1989976064), // XVSETANYEQZ_B |
2190 | 0 | UINT64_C(1989979136), // XVSETANYEQZ_D |
2191 | 0 | UINT64_C(1989977088), // XVSETANYEQZ_H |
2192 | 0 | UINT64_C(1989978112), // XVSETANYEQZ_W |
2193 | 0 | UINT64_C(1989974016), // XVSETEQZ_V |
2194 | 0 | UINT64_C(1989975040), // XVSETNEZ_V |
2195 | 0 | UINT64_C(2005925888), // XVSHUF4I_B |
2196 | 0 | UINT64_C(2006712320), // XVSHUF4I_D |
2197 | 0 | UINT64_C(2006188032), // XVSHUF4I_H |
2198 | 0 | UINT64_C(2006450176), // XVSHUF4I_W |
2199 | 0 | UINT64_C(224395264), // XVSHUF_B |
2200 | 0 | UINT64_C(1971027968), // XVSHUF_D |
2201 | 0 | UINT64_C(1970962432), // XVSHUF_H |
2202 | 0 | UINT64_C(1970995200), // XVSHUF_W |
2203 | 0 | UINT64_C(1965948928), // XVSIGNCOV_B |
2204 | 0 | UINT64_C(1966047232), // XVSIGNCOV_D |
2205 | 0 | UINT64_C(1965981696), // XVSIGNCOV_H |
2206 | 0 | UINT64_C(1966014464), // XVSIGNCOV_W |
2207 | 0 | UINT64_C(1988231168), // XVSLEI_B |
2208 | 0 | UINT64_C(1988362240), // XVSLEI_BU |
2209 | 0 | UINT64_C(1988329472), // XVSLEI_D |
2210 | 0 | UINT64_C(1988460544), // XVSLEI_DU |
2211 | 0 | UINT64_C(1988263936), // XVSLEI_H |
2212 | 0 | UINT64_C(1988395008), // XVSLEI_HU |
2213 | 0 | UINT64_C(1988296704), // XVSLEI_W |
2214 | 0 | UINT64_C(1988427776), // XVSLEI_WU |
2215 | 0 | UINT64_C(1946288128), // XVSLE_B |
2216 | 0 | UINT64_C(1946419200), // XVSLE_BU |
2217 | 0 | UINT64_C(1946386432), // XVSLE_D |
2218 | 0 | UINT64_C(1946517504), // XVSLE_DU |
2219 | 0 | UINT64_C(1946320896), // XVSLE_H |
2220 | 0 | UINT64_C(1946451968), // XVSLE_HU |
2221 | 0 | UINT64_C(1946353664), // XVSLE_W |
2222 | 0 | UINT64_C(1946484736), // XVSLE_WU |
2223 | 0 | UINT64_C(1999380480), // XVSLLI_B |
2224 | 0 | UINT64_C(1999437824), // XVSLLI_D |
2225 | 0 | UINT64_C(1999388672), // XVSLLI_H |
2226 | 0 | UINT64_C(1999405056), // XVSLLI_W |
2227 | 0 | UINT64_C(1997307904), // XVSLLWIL_DU_WU |
2228 | 0 | UINT64_C(1997045760), // XVSLLWIL_D_W |
2229 | 0 | UINT64_C(1997283328), // XVSLLWIL_HU_BU |
2230 | 0 | UINT64_C(1997021184), // XVSLLWIL_H_B |
2231 | 0 | UINT64_C(1997291520), // XVSLLWIL_WU_HU |
2232 | 0 | UINT64_C(1997029376), // XVSLLWIL_W_H |
2233 | 0 | UINT64_C(1961361408), // XVSLL_B |
2234 | 0 | UINT64_C(1961459712), // XVSLL_D |
2235 | 0 | UINT64_C(1961394176), // XVSLL_H |
2236 | 0 | UINT64_C(1961426944), // XVSLL_W |
2237 | 0 | UINT64_C(1988493312), // XVSLTI_B |
2238 | 0 | UINT64_C(1988624384), // XVSLTI_BU |
2239 | 0 | UINT64_C(1988591616), // XVSLTI_D |
2240 | 0 | UINT64_C(1988722688), // XVSLTI_DU |
2241 | 0 | UINT64_C(1988526080), // XVSLTI_H |
2242 | 0 | UINT64_C(1988657152), // XVSLTI_HU |
2243 | 0 | UINT64_C(1988558848), // XVSLTI_W |
2244 | 0 | UINT64_C(1988689920), // XVSLTI_WU |
2245 | 0 | UINT64_C(1946550272), // XVSLT_B |
2246 | 0 | UINT64_C(1946681344), // XVSLT_BU |
2247 | 0 | UINT64_C(1946648576), // XVSLT_D |
2248 | 0 | UINT64_C(1946779648), // XVSLT_DU |
2249 | 0 | UINT64_C(1946583040), // XVSLT_H |
2250 | 0 | UINT64_C(1946714112), // XVSLT_HU |
2251 | 0 | UINT64_C(1946615808), // XVSLT_W |
2252 | 0 | UINT64_C(1946746880), // XVSLT_WU |
2253 | 0 | UINT64_C(1999904768), // XVSRAI_B |
2254 | 0 | UINT64_C(1999962112), // XVSRAI_D |
2255 | 0 | UINT64_C(1999912960), // XVSRAI_H |
2256 | 0 | UINT64_C(1999929344), // XVSRAI_W |
2257 | 0 | UINT64_C(2002272256), // XVSRANI_B_H |
2258 | 0 | UINT64_C(2002386944), // XVSRANI_D_Q |
2259 | 0 | UINT64_C(2002288640), // XVSRANI_H_W |
2260 | 0 | UINT64_C(2002321408), // XVSRANI_W_D |
2261 | 0 | UINT64_C(1962311680), // XVSRAN_B_H |
2262 | 0 | UINT64_C(1962344448), // XVSRAN_H_W |
2263 | 0 | UINT64_C(1962377216), // XVSRAN_W_D |
2264 | 0 | UINT64_C(1990729728), // XVSRARI_B |
2265 | 0 | UINT64_C(1990787072), // XVSRARI_D |
2266 | 0 | UINT64_C(1990737920), // XVSRARI_H |
2267 | 0 | UINT64_C(1990754304), // XVSRARI_W |
2268 | 0 | UINT64_C(2002534400), // XVSRARNI_B_H |
2269 | 0 | UINT64_C(2002649088), // XVSRARNI_D_Q |
2270 | 0 | UINT64_C(2002550784), // XVSRARNI_H_W |
2271 | 0 | UINT64_C(2002583552), // XVSRARNI_W_D |
2272 | 0 | UINT64_C(1962573824), // XVSRARN_B_H |
2273 | 0 | UINT64_C(1962606592), // XVSRARN_H_W |
2274 | 0 | UINT64_C(1962639360), // XVSRARN_W_D |
2275 | 0 | UINT64_C(1962016768), // XVSRAR_B |
2276 | 0 | UINT64_C(1962115072), // XVSRAR_D |
2277 | 0 | UINT64_C(1962049536), // XVSRAR_H |
2278 | 0 | UINT64_C(1962082304), // XVSRAR_W |
2279 | 0 | UINT64_C(1961623552), // XVSRA_B |
2280 | 0 | UINT64_C(1961721856), // XVSRA_D |
2281 | 0 | UINT64_C(1961656320), // XVSRA_H |
2282 | 0 | UINT64_C(1961689088), // XVSRA_W |
2283 | 0 | UINT64_C(1999642624), // XVSRLI_B |
2284 | 0 | UINT64_C(1999699968), // XVSRLI_D |
2285 | 0 | UINT64_C(1999650816), // XVSRLI_H |
2286 | 0 | UINT64_C(1999667200), // XVSRLI_W |
2287 | 0 | UINT64_C(2000699392), // XVSRLNI_B_H |
2288 | 0 | UINT64_C(2000814080), // XVSRLNI_D_Q |
2289 | 0 | UINT64_C(2000715776), // XVSRLNI_H_W |
2290 | 0 | UINT64_C(2000748544), // XVSRLNI_W_D |
2291 | 0 | UINT64_C(1962180608), // XVSRLN_B_H |
2292 | 0 | UINT64_C(1962213376), // XVSRLN_H_W |
2293 | 0 | UINT64_C(1962246144), // XVSRLN_W_D |
2294 | 0 | UINT64_C(1990467584), // XVSRLRI_B |
2295 | 0 | UINT64_C(1990524928), // XVSRLRI_D |
2296 | 0 | UINT64_C(1990475776), // XVSRLRI_H |
2297 | 0 | UINT64_C(1990492160), // XVSRLRI_W |
2298 | 0 | UINT64_C(2000961536), // XVSRLRNI_B_H |
2299 | 0 | UINT64_C(2001076224), // XVSRLRNI_D_Q |
2300 | 0 | UINT64_C(2000977920), // XVSRLRNI_H_W |
2301 | 0 | UINT64_C(2001010688), // XVSRLRNI_W_D |
2302 | 0 | UINT64_C(1962442752), // XVSRLRN_B_H |
2303 | 0 | UINT64_C(1962475520), // XVSRLRN_H_W |
2304 | 0 | UINT64_C(1962508288), // XVSRLRN_W_D |
2305 | 0 | UINT64_C(1961885696), // XVSRLR_B |
2306 | 0 | UINT64_C(1961984000), // XVSRLR_D |
2307 | 0 | UINT64_C(1961918464), // XVSRLR_H |
2308 | 0 | UINT64_C(1961951232), // XVSRLR_W |
2309 | 0 | UINT64_C(1961492480), // XVSRL_B |
2310 | 0 | UINT64_C(1961590784), // XVSRL_D |
2311 | 0 | UINT64_C(1961525248), // XVSRL_H |
2312 | 0 | UINT64_C(1961558016), // XVSRL_W |
2313 | 0 | UINT64_C(2003058688), // XVSSRANI_BU_H |
2314 | 0 | UINT64_C(2002796544), // XVSSRANI_B_H |
2315 | 0 | UINT64_C(2003173376), // XVSSRANI_DU_Q |
2316 | 0 | UINT64_C(2002911232), // XVSSRANI_D_Q |
2317 | 0 | UINT64_C(2003075072), // XVSSRANI_HU_W |
2318 | 0 | UINT64_C(2002812928), // XVSSRANI_H_W |
2319 | 0 | UINT64_C(2003107840), // XVSSRANI_WU_D |
2320 | 0 | UINT64_C(2002845696), // XVSSRANI_W_D |
2321 | 0 | UINT64_C(1963360256), // XVSSRAN_BU_H |
2322 | 0 | UINT64_C(1962835968), // XVSSRAN_B_H |
2323 | 0 | UINT64_C(1963393024), // XVSSRAN_HU_W |
2324 | 0 | UINT64_C(1962868736), // XVSSRAN_H_W |
2325 | 0 | UINT64_C(1963425792), // XVSSRAN_WU_D |
2326 | 0 | UINT64_C(1962901504), // XVSSRAN_W_D |
2327 | 0 | UINT64_C(2003582976), // XVSSRARNI_BU_H |
2328 | 0 | UINT64_C(2003320832), // XVSSRARNI_B_H |
2329 | 0 | UINT64_C(2003697664), // XVSSRARNI_DU_Q |
2330 | 0 | UINT64_C(2003435520), // XVSSRARNI_D_Q |
2331 | 0 | UINT64_C(2003599360), // XVSSRARNI_HU_W |
2332 | 0 | UINT64_C(2003337216), // XVSSRARNI_H_W |
2333 | 0 | UINT64_C(2003632128), // XVSSRARNI_WU_D |
2334 | 0 | UINT64_C(2003369984), // XVSSRARNI_W_D |
2335 | 0 | UINT64_C(1963622400), // XVSSRARN_BU_H |
2336 | 0 | UINT64_C(1963098112), // XVSSRARN_B_H |
2337 | 0 | UINT64_C(1963655168), // XVSSRARN_HU_W |
2338 | 0 | UINT64_C(1963130880), // XVSSRARN_H_W |
2339 | 0 | UINT64_C(1963687936), // XVSSRARN_WU_D |
2340 | 0 | UINT64_C(1963163648), // XVSSRARN_W_D |
2341 | 0 | UINT64_C(2001485824), // XVSSRLNI_BU_H |
2342 | 0 | UINT64_C(2001223680), // XVSSRLNI_B_H |
2343 | 0 | UINT64_C(2001600512), // XVSSRLNI_DU_Q |
2344 | 0 | UINT64_C(2001338368), // XVSSRLNI_D_Q |
2345 | 0 | UINT64_C(2001502208), // XVSSRLNI_HU_W |
2346 | 0 | UINT64_C(2001240064), // XVSSRLNI_H_W |
2347 | 0 | UINT64_C(2001534976), // XVSSRLNI_WU_D |
2348 | 0 | UINT64_C(2001272832), // XVSSRLNI_W_D |
2349 | 0 | UINT64_C(1963229184), // XVSSRLN_BU_H |
2350 | 0 | UINT64_C(1962704896), // XVSSRLN_B_H |
2351 | 0 | UINT64_C(1963261952), // XVSSRLN_HU_W |
2352 | 0 | UINT64_C(1962737664), // XVSSRLN_H_W |
2353 | 0 | UINT64_C(1963294720), // XVSSRLN_WU_D |
2354 | 0 | UINT64_C(1962770432), // XVSSRLN_W_D |
2355 | 0 | UINT64_C(2002010112), // XVSSRLRNI_BU_H |
2356 | 0 | UINT64_C(2001747968), // XVSSRLRNI_B_H |
2357 | 0 | UINT64_C(2002124800), // XVSSRLRNI_DU_Q |
2358 | 0 | UINT64_C(2001862656), // XVSSRLRNI_D_Q |
2359 | 0 | UINT64_C(2002026496), // XVSSRLRNI_HU_W |
2360 | 0 | UINT64_C(2001764352), // XVSSRLRNI_H_W |
2361 | 0 | UINT64_C(2002059264), // XVSSRLRNI_WU_D |
2362 | 0 | UINT64_C(2001797120), // XVSSRLRNI_W_D |
2363 | 0 | UINT64_C(1963491328), // XVSSRLRN_BU_H |
2364 | 0 | UINT64_C(1962967040), // XVSSRLRN_B_H |
2365 | 0 | UINT64_C(1963524096), // XVSSRLRN_HU_W |
2366 | 0 | UINT64_C(1962999808), // XVSSRLRN_H_W |
2367 | 0 | UINT64_C(1963556864), // XVSSRLRN_WU_D |
2368 | 0 | UINT64_C(1963032576), // XVSSRLRN_W_D |
2369 | 0 | UINT64_C(1950875648), // XVSSUB_B |
2370 | 0 | UINT64_C(1951137792), // XVSSUB_BU |
2371 | 0 | UINT64_C(1950973952), // XVSSUB_D |
2372 | 0 | UINT64_C(1951236096), // XVSSUB_DU |
2373 | 0 | UINT64_C(1950908416), // XVSSUB_H |
2374 | 0 | UINT64_C(1951170560), // XVSSUB_HU |
2375 | 0 | UINT64_C(1950941184), // XVSSUB_W |
2376 | 0 | UINT64_C(1951203328), // XVSSUB_WU |
2377 | 0 | UINT64_C(750780416), // XVST |
2378 | 0 | UINT64_C(864026624), // XVSTELM_B |
2379 | 0 | UINT64_C(856686592), // XVSTELM_D |
2380 | 0 | UINT64_C(859832320), // XVSTELM_H |
2381 | 0 | UINT64_C(857735168), // XVSTELM_W |
2382 | 0 | UINT64_C(944504832), // XVSTX |
2383 | 0 | UINT64_C(1988886528), // XVSUBI_BU |
2384 | 0 | UINT64_C(1988984832), // XVSUBI_DU |
2385 | 0 | UINT64_C(1988919296), // XVSUBI_HU |
2386 | 0 | UINT64_C(1988952064), // XVSUBI_WU |
2387 | 0 | UINT64_C(1948319744), // XVSUBWEV_D_W |
2388 | 0 | UINT64_C(1949368320), // XVSUBWEV_D_WU |
2389 | 0 | UINT64_C(1948254208), // XVSUBWEV_H_B |
2390 | 0 | UINT64_C(1949302784), // XVSUBWEV_H_BU |
2391 | 0 | UINT64_C(1948352512), // XVSUBWEV_Q_D |
2392 | 0 | UINT64_C(1949401088), // XVSUBWEV_Q_DU |
2393 | 0 | UINT64_C(1948286976), // XVSUBWEV_W_H |
2394 | 0 | UINT64_C(1949335552), // XVSUBWEV_W_HU |
2395 | 0 | UINT64_C(1948581888), // XVSUBWOD_D_W |
2396 | 0 | UINT64_C(1949630464), // XVSUBWOD_D_WU |
2397 | 0 | UINT64_C(1948516352), // XVSUBWOD_H_B |
2398 | 0 | UINT64_C(1949564928), // XVSUBWOD_H_BU |
2399 | 0 | UINT64_C(1948614656), // XVSUBWOD_Q_D |
2400 | 0 | UINT64_C(1949663232), // XVSUBWOD_Q_DU |
2401 | 0 | UINT64_C(1948549120), // XVSUBWOD_W_H |
2402 | 0 | UINT64_C(1949597696), // XVSUBWOD_W_HU |
2403 | 0 | UINT64_C(1946943488), // XVSUB_B |
2404 | 0 | UINT64_C(1947041792), // XVSUB_D |
2405 | 0 | UINT64_C(1946976256), // XVSUB_H |
2406 | 0 | UINT64_C(1965916160), // XVSUB_Q |
2407 | 0 | UINT64_C(1947009024), // XVSUB_W |
2408 | 0 | UINT64_C(2010644480), // XVXORI_B |
2409 | 0 | UINT64_C(1965490176), // XVXOR_V |
2410 | 0 | UINT64_C(0) |
2411 | 0 | }; |
2412 | 0 | const unsigned opcode = MI.getOpcode(); |
2413 | 0 | uint64_t Value = InstBits[opcode]; |
2414 | 0 | uint64_t op = 0; |
2415 | 0 | (void)op; // suppress warning |
2416 | 0 | switch (opcode) { |
2417 | 0 | case LoongArch::ERTN: |
2418 | 0 | case LoongArch::GTLBFLUSH: |
2419 | 0 | case LoongArch::TLBCLR: |
2420 | 0 | case LoongArch::TLBFILL: |
2421 | 0 | case LoongArch::TLBFLUSH: |
2422 | 0 | case LoongArch::TLBRD: |
2423 | 0 | case LoongArch::TLBSRCH: |
2424 | 0 | case LoongArch::TLBWR: |
2425 | 0 | case LoongArch::X86CLRTM: |
2426 | 0 | case LoongArch::X86DECTOP: |
2427 | 0 | case LoongArch::X86INCTOP: |
2428 | 0 | case LoongArch::X86SETTM: { |
2429 | 0 | break; |
2430 | 0 | } |
2431 | 0 | case LoongArch::FSEL_xD: |
2432 | 0 | case LoongArch::FSEL_xS: { |
2433 | | // op: ca |
2434 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
2435 | 0 | op &= UINT64_C(7); |
2436 | 0 | op <<= 15; |
2437 | 0 | Value |= op; |
2438 | | // op: fk |
2439 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2440 | 0 | op &= UINT64_C(31); |
2441 | 0 | op <<= 10; |
2442 | 0 | Value |= op; |
2443 | | // op: fj |
2444 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2445 | 0 | op &= UINT64_C(31); |
2446 | 0 | op <<= 5; |
2447 | 0 | Value |= op; |
2448 | | // op: fd |
2449 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2450 | 0 | op &= UINT64_C(31); |
2451 | 0 | Value |= op; |
2452 | 0 | break; |
2453 | 0 | } |
2454 | 0 | case LoongArch::SET_CFR_FALSE: |
2455 | 0 | case LoongArch::SET_CFR_TRUE: { |
2456 | | // op: cd |
2457 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2458 | 0 | op &= UINT64_C(7); |
2459 | 0 | Value |= op; |
2460 | 0 | break; |
2461 | 0 | } |
2462 | 0 | case LoongArch::CSRRD: |
2463 | 0 | case LoongArch::GCSRRD: { |
2464 | | // op: csr_num |
2465 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2466 | 0 | op &= UINT64_C(16383); |
2467 | 0 | op <<= 10; |
2468 | 0 | Value |= op; |
2469 | | // op: rd |
2470 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2471 | 0 | op &= UINT64_C(31); |
2472 | 0 | Value |= op; |
2473 | 0 | break; |
2474 | 0 | } |
2475 | 0 | case LoongArch::CSRWR: |
2476 | 0 | case LoongArch::GCSRWR: { |
2477 | | // op: csr_num |
2478 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2479 | 0 | op &= UINT64_C(16383); |
2480 | 0 | op <<= 10; |
2481 | 0 | Value |= op; |
2482 | | // op: rd |
2483 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2484 | 0 | op &= UINT64_C(31); |
2485 | 0 | Value |= op; |
2486 | 0 | break; |
2487 | 0 | } |
2488 | 0 | case LoongArch::CSRXCHG: |
2489 | 0 | case LoongArch::GCSRXCHG: { |
2490 | | // op: csr_num |
2491 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
2492 | 0 | op &= UINT64_C(16383); |
2493 | 0 | op <<= 10; |
2494 | 0 | Value |= op; |
2495 | | // op: rj |
2496 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2497 | 0 | op &= UINT64_C(31); |
2498 | 0 | op <<= 5; |
2499 | 0 | Value |= op; |
2500 | | // op: rd |
2501 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2502 | 0 | op &= UINT64_C(31); |
2503 | 0 | Value |= op; |
2504 | 0 | break; |
2505 | 0 | } |
2506 | 0 | case LoongArch::FMADD_D: |
2507 | 0 | case LoongArch::FMADD_S: |
2508 | 0 | case LoongArch::FMSUB_D: |
2509 | 0 | case LoongArch::FMSUB_S: |
2510 | 0 | case LoongArch::FNMADD_D: |
2511 | 0 | case LoongArch::FNMADD_S: |
2512 | 0 | case LoongArch::FNMSUB_D: |
2513 | 0 | case LoongArch::FNMSUB_S: { |
2514 | | // op: fa |
2515 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
2516 | 0 | op &= UINT64_C(31); |
2517 | 0 | op <<= 15; |
2518 | 0 | Value |= op; |
2519 | | // op: fk |
2520 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2521 | 0 | op &= UINT64_C(31); |
2522 | 0 | op <<= 10; |
2523 | 0 | Value |= op; |
2524 | | // op: fj |
2525 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2526 | 0 | op &= UINT64_C(31); |
2527 | 0 | op <<= 5; |
2528 | 0 | Value |= op; |
2529 | | // op: fd |
2530 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2531 | 0 | op &= UINT64_C(31); |
2532 | 0 | Value |= op; |
2533 | 0 | break; |
2534 | 0 | } |
2535 | 0 | case LoongArch::FABS_D: |
2536 | 0 | case LoongArch::FABS_S: |
2537 | 0 | case LoongArch::FCLASS_D: |
2538 | 0 | case LoongArch::FCLASS_S: |
2539 | 0 | case LoongArch::FCVT_D_S: |
2540 | 0 | case LoongArch::FCVT_LD_D: |
2541 | 0 | case LoongArch::FCVT_S_D: |
2542 | 0 | case LoongArch::FCVT_UD_D: |
2543 | 0 | case LoongArch::FFINT_D_L: |
2544 | 0 | case LoongArch::FFINT_D_W: |
2545 | 0 | case LoongArch::FFINT_S_L: |
2546 | 0 | case LoongArch::FFINT_S_W: |
2547 | 0 | case LoongArch::FLOGB_D: |
2548 | 0 | case LoongArch::FLOGB_S: |
2549 | 0 | case LoongArch::FNEG_D: |
2550 | 0 | case LoongArch::FNEG_S: |
2551 | 0 | case LoongArch::FRECIPE_D: |
2552 | 0 | case LoongArch::FRECIPE_S: |
2553 | 0 | case LoongArch::FRECIP_D: |
2554 | 0 | case LoongArch::FRECIP_S: |
2555 | 0 | case LoongArch::FRINT_D: |
2556 | 0 | case LoongArch::FRINT_S: |
2557 | 0 | case LoongArch::FRSQRTE_D: |
2558 | 0 | case LoongArch::FRSQRTE_S: |
2559 | 0 | case LoongArch::FRSQRT_D: |
2560 | 0 | case LoongArch::FRSQRT_S: |
2561 | 0 | case LoongArch::FSQRT_D: |
2562 | 0 | case LoongArch::FSQRT_S: |
2563 | 0 | case LoongArch::FTINTRM_L_D: |
2564 | 0 | case LoongArch::FTINTRM_L_S: |
2565 | 0 | case LoongArch::FTINTRM_W_D: |
2566 | 0 | case LoongArch::FTINTRM_W_S: |
2567 | 0 | case LoongArch::FTINTRNE_L_D: |
2568 | 0 | case LoongArch::FTINTRNE_L_S: |
2569 | 0 | case LoongArch::FTINTRNE_W_D: |
2570 | 0 | case LoongArch::FTINTRNE_W_S: |
2571 | 0 | case LoongArch::FTINTRP_L_D: |
2572 | 0 | case LoongArch::FTINTRP_L_S: |
2573 | 0 | case LoongArch::FTINTRP_W_D: |
2574 | 0 | case LoongArch::FTINTRP_W_S: |
2575 | 0 | case LoongArch::FTINTRZ_L_D: |
2576 | 0 | case LoongArch::FTINTRZ_L_S: |
2577 | 0 | case LoongArch::FTINTRZ_W_D: |
2578 | 0 | case LoongArch::FTINTRZ_W_S: |
2579 | 0 | case LoongArch::FTINT_L_D: |
2580 | 0 | case LoongArch::FTINT_L_S: |
2581 | 0 | case LoongArch::FTINT_W_D: |
2582 | 0 | case LoongArch::FTINT_W_S: { |
2583 | | // op: fj |
2584 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2585 | 0 | op &= UINT64_C(31); |
2586 | 0 | op <<= 5; |
2587 | 0 | Value |= op; |
2588 | | // op: fd |
2589 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2590 | 0 | op &= UINT64_C(31); |
2591 | 0 | Value |= op; |
2592 | 0 | break; |
2593 | 0 | } |
2594 | 0 | case LoongArch::FCMP_CAF_D: |
2595 | 0 | case LoongArch::FCMP_CAF_S: |
2596 | 0 | case LoongArch::FCMP_CEQ_D: |
2597 | 0 | case LoongArch::FCMP_CEQ_S: |
2598 | 0 | case LoongArch::FCMP_CLE_D: |
2599 | 0 | case LoongArch::FCMP_CLE_S: |
2600 | 0 | case LoongArch::FCMP_CLT_D: |
2601 | 0 | case LoongArch::FCMP_CLT_S: |
2602 | 0 | case LoongArch::FCMP_CNE_D: |
2603 | 0 | case LoongArch::FCMP_CNE_S: |
2604 | 0 | case LoongArch::FCMP_COR_D: |
2605 | 0 | case LoongArch::FCMP_COR_S: |
2606 | 0 | case LoongArch::FCMP_CUEQ_D: |
2607 | 0 | case LoongArch::FCMP_CUEQ_S: |
2608 | 0 | case LoongArch::FCMP_CULE_D: |
2609 | 0 | case LoongArch::FCMP_CULE_S: |
2610 | 0 | case LoongArch::FCMP_CULT_D: |
2611 | 0 | case LoongArch::FCMP_CULT_S: |
2612 | 0 | case LoongArch::FCMP_CUNE_D: |
2613 | 0 | case LoongArch::FCMP_CUNE_S: |
2614 | 0 | case LoongArch::FCMP_CUN_D: |
2615 | 0 | case LoongArch::FCMP_CUN_S: |
2616 | 0 | case LoongArch::FCMP_SAF_D: |
2617 | 0 | case LoongArch::FCMP_SAF_S: |
2618 | 0 | case LoongArch::FCMP_SEQ_D: |
2619 | 0 | case LoongArch::FCMP_SEQ_S: |
2620 | 0 | case LoongArch::FCMP_SLE_D: |
2621 | 0 | case LoongArch::FCMP_SLE_S: |
2622 | 0 | case LoongArch::FCMP_SLT_D: |
2623 | 0 | case LoongArch::FCMP_SLT_S: |
2624 | 0 | case LoongArch::FCMP_SNE_D: |
2625 | 0 | case LoongArch::FCMP_SNE_S: |
2626 | 0 | case LoongArch::FCMP_SOR_D: |
2627 | 0 | case LoongArch::FCMP_SOR_S: |
2628 | 0 | case LoongArch::FCMP_SUEQ_D: |
2629 | 0 | case LoongArch::FCMP_SUEQ_S: |
2630 | 0 | case LoongArch::FCMP_SULE_D: |
2631 | 0 | case LoongArch::FCMP_SULE_S: |
2632 | 0 | case LoongArch::FCMP_SULT_D: |
2633 | 0 | case LoongArch::FCMP_SULT_S: |
2634 | 0 | case LoongArch::FCMP_SUNE_D: |
2635 | 0 | case LoongArch::FCMP_SUNE_S: |
2636 | 0 | case LoongArch::FCMP_SUN_D: |
2637 | 0 | case LoongArch::FCMP_SUN_S: { |
2638 | | // op: fk |
2639 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2640 | 0 | op &= UINT64_C(31); |
2641 | 0 | op <<= 10; |
2642 | 0 | Value |= op; |
2643 | | // op: fj |
2644 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2645 | 0 | op &= UINT64_C(31); |
2646 | 0 | op <<= 5; |
2647 | 0 | Value |= op; |
2648 | | // op: cd |
2649 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2650 | 0 | op &= UINT64_C(7); |
2651 | 0 | Value |= op; |
2652 | 0 | break; |
2653 | 0 | } |
2654 | 0 | case LoongArch::FADD_D: |
2655 | 0 | case LoongArch::FADD_S: |
2656 | 0 | case LoongArch::FCOPYSIGN_D: |
2657 | 0 | case LoongArch::FCOPYSIGN_S: |
2658 | 0 | case LoongArch::FCVT_D_LD: |
2659 | 0 | case LoongArch::FDIV_D: |
2660 | 0 | case LoongArch::FDIV_S: |
2661 | 0 | case LoongArch::FMAXA_D: |
2662 | 0 | case LoongArch::FMAXA_S: |
2663 | 0 | case LoongArch::FMAX_D: |
2664 | 0 | case LoongArch::FMAX_S: |
2665 | 0 | case LoongArch::FMINA_D: |
2666 | 0 | case LoongArch::FMINA_S: |
2667 | 0 | case LoongArch::FMIN_D: |
2668 | 0 | case LoongArch::FMIN_S: |
2669 | 0 | case LoongArch::FMUL_D: |
2670 | 0 | case LoongArch::FMUL_S: |
2671 | 0 | case LoongArch::FSCALEB_D: |
2672 | 0 | case LoongArch::FSCALEB_S: |
2673 | 0 | case LoongArch::FSUB_D: |
2674 | 0 | case LoongArch::FSUB_S: { |
2675 | | // op: fk |
2676 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2677 | 0 | op &= UINT64_C(31); |
2678 | 0 | op <<= 10; |
2679 | 0 | Value |= op; |
2680 | | // op: fj |
2681 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2682 | 0 | op &= UINT64_C(31); |
2683 | 0 | op <<= 5; |
2684 | 0 | Value |= op; |
2685 | | // op: fd |
2686 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2687 | 0 | op &= UINT64_C(31); |
2688 | 0 | Value |= op; |
2689 | 0 | break; |
2690 | 0 | } |
2691 | 0 | case LoongArch::VPICKVE2GR_D: |
2692 | 0 | case LoongArch::VPICKVE2GR_DU: { |
2693 | | // op: imm1 |
2694 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2695 | 0 | op &= UINT64_C(1); |
2696 | 0 | op <<= 10; |
2697 | 0 | Value |= op; |
2698 | | // op: vj |
2699 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2700 | 0 | op &= UINT64_C(31); |
2701 | 0 | op <<= 5; |
2702 | 0 | Value |= op; |
2703 | | // op: rd |
2704 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2705 | 0 | op &= UINT64_C(31); |
2706 | 0 | Value |= op; |
2707 | 0 | break; |
2708 | 0 | } |
2709 | 0 | case LoongArch::VREPLVEI_D: { |
2710 | | // op: imm1 |
2711 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2712 | 0 | op &= UINT64_C(1); |
2713 | 0 | op <<= 10; |
2714 | 0 | Value |= op; |
2715 | | // op: vj |
2716 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2717 | 0 | op &= UINT64_C(31); |
2718 | 0 | op <<= 5; |
2719 | 0 | Value |= op; |
2720 | | // op: vd |
2721 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2722 | 0 | op &= UINT64_C(31); |
2723 | 0 | Value |= op; |
2724 | 0 | break; |
2725 | 0 | } |
2726 | 0 | case LoongArch::XVREPL128VEI_D: { |
2727 | | // op: imm1 |
2728 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2729 | 0 | op &= UINT64_C(1); |
2730 | 0 | op <<= 10; |
2731 | 0 | Value |= op; |
2732 | | // op: xj |
2733 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2734 | 0 | op &= UINT64_C(31); |
2735 | 0 | op <<= 5; |
2736 | 0 | Value |= op; |
2737 | | // op: xd |
2738 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2739 | 0 | op &= UINT64_C(31); |
2740 | 0 | Value |= op; |
2741 | 0 | break; |
2742 | 0 | } |
2743 | 0 | case LoongArch::VINSGR2VR_D: { |
2744 | | // op: imm1 |
2745 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
2746 | 0 | op &= UINT64_C(1); |
2747 | 0 | op <<= 10; |
2748 | 0 | Value |= op; |
2749 | | // op: rj |
2750 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2751 | 0 | op &= UINT64_C(31); |
2752 | 0 | op <<= 5; |
2753 | 0 | Value |= op; |
2754 | | // op: vd |
2755 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2756 | 0 | op &= UINT64_C(31); |
2757 | 0 | Value |= op; |
2758 | 0 | break; |
2759 | 0 | } |
2760 | 0 | case LoongArch::VSTELM_D: { |
2761 | | // op: imm1 |
2762 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
2763 | 0 | op &= UINT64_C(1); |
2764 | 0 | op <<= 18; |
2765 | 0 | Value |= op; |
2766 | | // op: imm8 |
2767 | 0 | op = getImmOpValueAsr<3>(MI, 2, Fixups, STI); |
2768 | 0 | op &= UINT64_C(255); |
2769 | 0 | op <<= 10; |
2770 | 0 | Value |= op; |
2771 | | // op: rj |
2772 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2773 | 0 | op &= UINT64_C(31); |
2774 | 0 | op <<= 5; |
2775 | 0 | Value |= op; |
2776 | | // op: vd |
2777 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2778 | 0 | op &= UINT64_C(31); |
2779 | 0 | Value |= op; |
2780 | 0 | break; |
2781 | 0 | } |
2782 | 0 | case LoongArch::VLDREPL_W: { |
2783 | | // op: imm10 |
2784 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
2785 | 0 | op &= UINT64_C(1023); |
2786 | 0 | op <<= 10; |
2787 | 0 | Value |= op; |
2788 | | // op: rj |
2789 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2790 | 0 | op &= UINT64_C(31); |
2791 | 0 | op <<= 5; |
2792 | 0 | Value |= op; |
2793 | | // op: vd |
2794 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2795 | 0 | op &= UINT64_C(31); |
2796 | 0 | Value |= op; |
2797 | 0 | break; |
2798 | 0 | } |
2799 | 0 | case LoongArch::XVLDREPL_W: { |
2800 | | // op: imm10 |
2801 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
2802 | 0 | op &= UINT64_C(1023); |
2803 | 0 | op <<= 10; |
2804 | 0 | Value |= op; |
2805 | | // op: rj |
2806 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2807 | 0 | op &= UINT64_C(31); |
2808 | 0 | op <<= 5; |
2809 | 0 | Value |= op; |
2810 | | // op: xd |
2811 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2812 | 0 | op &= UINT64_C(31); |
2813 | 0 | Value |= op; |
2814 | 0 | break; |
2815 | 0 | } |
2816 | 0 | case LoongArch::VLDREPL_H: { |
2817 | | // op: imm11 |
2818 | 0 | op = getImmOpValueAsr<1>(MI, 2, Fixups, STI); |
2819 | 0 | op &= UINT64_C(2047); |
2820 | 0 | op <<= 10; |
2821 | 0 | Value |= op; |
2822 | | // op: rj |
2823 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2824 | 0 | op &= UINT64_C(31); |
2825 | 0 | op <<= 5; |
2826 | 0 | Value |= op; |
2827 | | // op: vd |
2828 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2829 | 0 | op &= UINT64_C(31); |
2830 | 0 | Value |= op; |
2831 | 0 | break; |
2832 | 0 | } |
2833 | 0 | case LoongArch::XVLDREPL_H: { |
2834 | | // op: imm11 |
2835 | 0 | op = getImmOpValueAsr<1>(MI, 2, Fixups, STI); |
2836 | 0 | op &= UINT64_C(2047); |
2837 | 0 | op <<= 10; |
2838 | 0 | Value |= op; |
2839 | | // op: rj |
2840 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2841 | 0 | op &= UINT64_C(31); |
2842 | 0 | op <<= 5; |
2843 | 0 | Value |= op; |
2844 | | // op: xd |
2845 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2846 | 0 | op &= UINT64_C(31); |
2847 | 0 | Value |= op; |
2848 | 0 | break; |
2849 | 0 | } |
2850 | 0 | case LoongArch::FLD_D: |
2851 | 0 | case LoongArch::FLD_S: |
2852 | 0 | case LoongArch::FST_D: |
2853 | 0 | case LoongArch::FST_S: { |
2854 | | // op: imm12 |
2855 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2856 | 0 | op &= UINT64_C(4095); |
2857 | 0 | op <<= 10; |
2858 | 0 | Value |= op; |
2859 | | // op: rj |
2860 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2861 | 0 | op &= UINT64_C(31); |
2862 | 0 | op <<= 5; |
2863 | 0 | Value |= op; |
2864 | | // op: fd |
2865 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2866 | 0 | op &= UINT64_C(31); |
2867 | 0 | Value |= op; |
2868 | 0 | break; |
2869 | 0 | } |
2870 | 0 | case LoongArch::PRELD: { |
2871 | | // op: imm12 |
2872 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2873 | 0 | op &= UINT64_C(4095); |
2874 | 0 | op <<= 10; |
2875 | 0 | Value |= op; |
2876 | | // op: rj |
2877 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2878 | 0 | op &= UINT64_C(31); |
2879 | 0 | op <<= 5; |
2880 | 0 | Value |= op; |
2881 | | // op: imm5 |
2882 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2883 | 0 | op &= UINT64_C(31); |
2884 | 0 | Value |= op; |
2885 | 0 | break; |
2886 | 0 | } |
2887 | 0 | case LoongArch::CACOP: { |
2888 | | // op: imm12 |
2889 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2890 | 0 | op &= UINT64_C(4095); |
2891 | 0 | op <<= 10; |
2892 | 0 | Value |= op; |
2893 | | // op: rj |
2894 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2895 | 0 | op &= UINT64_C(31); |
2896 | 0 | op <<= 5; |
2897 | 0 | Value |= op; |
2898 | | // op: op |
2899 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2900 | 0 | op &= UINT64_C(31); |
2901 | 0 | Value |= op; |
2902 | 0 | break; |
2903 | 0 | } |
2904 | 0 | case LoongArch::ADDI_D: |
2905 | 0 | case LoongArch::ADDI_W: |
2906 | 0 | case LoongArch::ANDI: |
2907 | 0 | case LoongArch::LDL_D: |
2908 | 0 | case LoongArch::LDL_W: |
2909 | 0 | case LoongArch::LDR_D: |
2910 | 0 | case LoongArch::LDR_W: |
2911 | 0 | case LoongArch::LD_B: |
2912 | 0 | case LoongArch::LD_BU: |
2913 | 0 | case LoongArch::LD_D: |
2914 | 0 | case LoongArch::LD_H: |
2915 | 0 | case LoongArch::LD_HU: |
2916 | 0 | case LoongArch::LD_W: |
2917 | 0 | case LoongArch::LD_WU: |
2918 | 0 | case LoongArch::LU52I_D: |
2919 | 0 | case LoongArch::ORI: |
2920 | 0 | case LoongArch::SLTI: |
2921 | 0 | case LoongArch::SLTUI: |
2922 | 0 | case LoongArch::STL_D: |
2923 | 0 | case LoongArch::STL_W: |
2924 | 0 | case LoongArch::STR_D: |
2925 | 0 | case LoongArch::STR_W: |
2926 | 0 | case LoongArch::ST_B: |
2927 | 0 | case LoongArch::ST_D: |
2928 | 0 | case LoongArch::ST_H: |
2929 | 0 | case LoongArch::ST_W: |
2930 | 0 | case LoongArch::XORI: { |
2931 | | // op: imm12 |
2932 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2933 | 0 | op &= UINT64_C(4095); |
2934 | 0 | op <<= 10; |
2935 | 0 | Value |= op; |
2936 | | // op: rj |
2937 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2938 | 0 | op &= UINT64_C(31); |
2939 | 0 | op <<= 5; |
2940 | 0 | Value |= op; |
2941 | | // op: rd |
2942 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2943 | 0 | op &= UINT64_C(31); |
2944 | 0 | Value |= op; |
2945 | 0 | break; |
2946 | 0 | } |
2947 | 0 | case LoongArch::VLD: |
2948 | 0 | case LoongArch::VLDREPL_B: |
2949 | 0 | case LoongArch::VST: { |
2950 | | // op: imm12 |
2951 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2952 | 0 | op &= UINT64_C(4095); |
2953 | 0 | op <<= 10; |
2954 | 0 | Value |= op; |
2955 | | // op: rj |
2956 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2957 | 0 | op &= UINT64_C(31); |
2958 | 0 | op <<= 5; |
2959 | 0 | Value |= op; |
2960 | | // op: vd |
2961 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2962 | 0 | op &= UINT64_C(31); |
2963 | 0 | Value |= op; |
2964 | 0 | break; |
2965 | 0 | } |
2966 | 0 | case LoongArch::XVLD: |
2967 | 0 | case LoongArch::XVLDREPL_B: |
2968 | 0 | case LoongArch::XVST: { |
2969 | | // op: imm12 |
2970 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
2971 | 0 | op &= UINT64_C(4095); |
2972 | 0 | op <<= 10; |
2973 | 0 | Value |= op; |
2974 | | // op: rj |
2975 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2976 | 0 | op &= UINT64_C(31); |
2977 | 0 | op <<= 5; |
2978 | 0 | Value |= op; |
2979 | | // op: xd |
2980 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2981 | 0 | op &= UINT64_C(31); |
2982 | 0 | Value |= op; |
2983 | 0 | break; |
2984 | 0 | } |
2985 | 0 | case LoongArch::VLDI: { |
2986 | | // op: imm13 |
2987 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
2988 | 0 | op &= UINT64_C(8191); |
2989 | 0 | op <<= 5; |
2990 | 0 | Value |= op; |
2991 | | // op: vd |
2992 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2993 | 0 | op &= UINT64_C(31); |
2994 | 0 | Value |= op; |
2995 | 0 | break; |
2996 | 0 | } |
2997 | 0 | case LoongArch::XVLDI: { |
2998 | | // op: imm13 |
2999 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3000 | 0 | op &= UINT64_C(8191); |
3001 | 0 | op <<= 5; |
3002 | 0 | Value |= op; |
3003 | | // op: xd |
3004 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3005 | 0 | op &= UINT64_C(31); |
3006 | 0 | Value |= op; |
3007 | 0 | break; |
3008 | 0 | } |
3009 | 0 | case LoongArch::LDPTR_D: |
3010 | 0 | case LoongArch::LDPTR_W: |
3011 | 0 | case LoongArch::LL_D: |
3012 | 0 | case LoongArch::LL_W: |
3013 | 0 | case LoongArch::STPTR_D: |
3014 | 0 | case LoongArch::STPTR_W: { |
3015 | | // op: imm14 |
3016 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
3017 | 0 | op &= UINT64_C(16383); |
3018 | 0 | op <<= 10; |
3019 | 0 | Value |= op; |
3020 | | // op: rj |
3021 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3022 | 0 | op &= UINT64_C(31); |
3023 | 0 | op <<= 5; |
3024 | 0 | Value |= op; |
3025 | | // op: rd |
3026 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3027 | 0 | op &= UINT64_C(31); |
3028 | 0 | Value |= op; |
3029 | 0 | break; |
3030 | 0 | } |
3031 | 0 | case LoongArch::SC_D: |
3032 | 0 | case LoongArch::SC_W: { |
3033 | | // op: imm14 |
3034 | 0 | op = getImmOpValueAsr<2>(MI, 3, Fixups, STI); |
3035 | 0 | op &= UINT64_C(16383); |
3036 | 0 | op <<= 10; |
3037 | 0 | Value |= op; |
3038 | | // op: rj |
3039 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3040 | 0 | op &= UINT64_C(31); |
3041 | 0 | op <<= 5; |
3042 | 0 | Value |= op; |
3043 | | // op: rd |
3044 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3045 | 0 | op &= UINT64_C(31); |
3046 | 0 | Value |= op; |
3047 | 0 | break; |
3048 | 0 | } |
3049 | 0 | case LoongArch::BREAK: |
3050 | 0 | case LoongArch::DBAR: |
3051 | 0 | case LoongArch::DBCL: |
3052 | 0 | case LoongArch::HVCL: |
3053 | 0 | case LoongArch::IBAR: |
3054 | 0 | case LoongArch::IDLE: |
3055 | 0 | case LoongArch::SYSCALL: { |
3056 | | // op: imm15 |
3057 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3058 | 0 | op &= UINT64_C(32767); |
3059 | 0 | Value |= op; |
3060 | 0 | break; |
3061 | 0 | } |
3062 | 0 | case LoongArch::BEQ: |
3063 | 0 | case LoongArch::BGE: |
3064 | 0 | case LoongArch::BGEU: |
3065 | 0 | case LoongArch::BLT: |
3066 | 0 | case LoongArch::BLTU: |
3067 | 0 | case LoongArch::BNE: { |
3068 | | // op: imm16 |
3069 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
3070 | 0 | op &= UINT64_C(65535); |
3071 | 0 | op <<= 10; |
3072 | 0 | Value |= op; |
3073 | | // op: rj |
3074 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3075 | 0 | op &= UINT64_C(31); |
3076 | 0 | op <<= 5; |
3077 | 0 | Value |= op; |
3078 | | // op: rd |
3079 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3080 | 0 | op &= UINT64_C(31); |
3081 | 0 | Value |= op; |
3082 | 0 | break; |
3083 | 0 | } |
3084 | 0 | case LoongArch::JIRL: { |
3085 | | // op: imm16 |
3086 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
3087 | 0 | op &= UINT64_C(65535); |
3088 | 0 | op <<= 10; |
3089 | 0 | Value |= op; |
3090 | | // op: rj |
3091 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3092 | 0 | op &= UINT64_C(31); |
3093 | 0 | op <<= 5; |
3094 | 0 | Value |= op; |
3095 | | // op: rd |
3096 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3097 | 0 | op &= UINT64_C(31); |
3098 | 0 | Value |= op; |
3099 | 0 | break; |
3100 | 0 | } |
3101 | 0 | case LoongArch::ADDU16I_D: { |
3102 | | // op: imm16 |
3103 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3104 | 0 | op &= UINT64_C(65535); |
3105 | 0 | op <<= 10; |
3106 | 0 | Value |= op; |
3107 | | // op: rj |
3108 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3109 | 0 | op &= UINT64_C(31); |
3110 | 0 | op <<= 5; |
3111 | 0 | Value |= op; |
3112 | | // op: rd |
3113 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3114 | 0 | op &= UINT64_C(31); |
3115 | 0 | Value |= op; |
3116 | 0 | break; |
3117 | 0 | } |
3118 | 0 | case LoongArch::ALSL_D: |
3119 | 0 | case LoongArch::ALSL_W: |
3120 | 0 | case LoongArch::ALSL_WU: { |
3121 | | // op: imm2 |
3122 | 0 | op = getImmOpValueSub1(MI, 3, Fixups, STI); |
3123 | 0 | op &= UINT64_C(3); |
3124 | 0 | op <<= 15; |
3125 | 0 | Value |= op; |
3126 | | // op: rk |
3127 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3128 | 0 | op &= UINT64_C(31); |
3129 | 0 | op <<= 10; |
3130 | 0 | Value |= op; |
3131 | | // op: rj |
3132 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3133 | 0 | op &= UINT64_C(31); |
3134 | 0 | op <<= 5; |
3135 | 0 | Value |= op; |
3136 | | // op: rd |
3137 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3138 | 0 | op &= UINT64_C(31); |
3139 | 0 | Value |= op; |
3140 | 0 | break; |
3141 | 0 | } |
3142 | 0 | case LoongArch::VPICKVE2GR_W: |
3143 | 0 | case LoongArch::VPICKVE2GR_WU: { |
3144 | | // op: imm2 |
3145 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3146 | 0 | op &= UINT64_C(3); |
3147 | 0 | op <<= 10; |
3148 | 0 | Value |= op; |
3149 | | // op: vj |
3150 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3151 | 0 | op &= UINT64_C(31); |
3152 | 0 | op <<= 5; |
3153 | 0 | Value |= op; |
3154 | | // op: rd |
3155 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3156 | 0 | op &= UINT64_C(31); |
3157 | 0 | Value |= op; |
3158 | 0 | break; |
3159 | 0 | } |
3160 | 0 | case LoongArch::VREPLVEI_W: { |
3161 | | // op: imm2 |
3162 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3163 | 0 | op &= UINT64_C(3); |
3164 | 0 | op <<= 10; |
3165 | 0 | Value |= op; |
3166 | | // op: vj |
3167 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3168 | 0 | op &= UINT64_C(31); |
3169 | 0 | op <<= 5; |
3170 | 0 | Value |= op; |
3171 | | // op: vd |
3172 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3173 | 0 | op &= UINT64_C(31); |
3174 | 0 | Value |= op; |
3175 | 0 | break; |
3176 | 0 | } |
3177 | 0 | case LoongArch::XVPICKVE2GR_D: |
3178 | 0 | case LoongArch::XVPICKVE2GR_DU: { |
3179 | | // op: imm2 |
3180 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3181 | 0 | op &= UINT64_C(3); |
3182 | 0 | op <<= 10; |
3183 | 0 | Value |= op; |
3184 | | // op: xj |
3185 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3186 | 0 | op &= UINT64_C(31); |
3187 | 0 | op <<= 5; |
3188 | 0 | Value |= op; |
3189 | | // op: rd |
3190 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3191 | 0 | op &= UINT64_C(31); |
3192 | 0 | Value |= op; |
3193 | 0 | break; |
3194 | 0 | } |
3195 | 0 | case LoongArch::XVPICKVE_D: |
3196 | 0 | case LoongArch::XVREPL128VEI_W: { |
3197 | | // op: imm2 |
3198 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3199 | 0 | op &= UINT64_C(3); |
3200 | 0 | op <<= 10; |
3201 | 0 | Value |= op; |
3202 | | // op: xj |
3203 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3204 | 0 | op &= UINT64_C(31); |
3205 | 0 | op <<= 5; |
3206 | 0 | Value |= op; |
3207 | | // op: xd |
3208 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3209 | 0 | op &= UINT64_C(31); |
3210 | 0 | Value |= op; |
3211 | 0 | break; |
3212 | 0 | } |
3213 | 0 | case LoongArch::VINSGR2VR_W: { |
3214 | | // op: imm2 |
3215 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3216 | 0 | op &= UINT64_C(3); |
3217 | 0 | op <<= 10; |
3218 | 0 | Value |= op; |
3219 | | // op: rj |
3220 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3221 | 0 | op &= UINT64_C(31); |
3222 | 0 | op <<= 5; |
3223 | 0 | Value |= op; |
3224 | | // op: vd |
3225 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3226 | 0 | op &= UINT64_C(31); |
3227 | 0 | Value |= op; |
3228 | 0 | break; |
3229 | 0 | } |
3230 | 0 | case LoongArch::XVINSGR2VR_D: { |
3231 | | // op: imm2 |
3232 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3233 | 0 | op &= UINT64_C(3); |
3234 | 0 | op <<= 10; |
3235 | 0 | Value |= op; |
3236 | | // op: rj |
3237 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3238 | 0 | op &= UINT64_C(31); |
3239 | 0 | op <<= 5; |
3240 | 0 | Value |= op; |
3241 | | // op: xd |
3242 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3243 | 0 | op &= UINT64_C(31); |
3244 | 0 | Value |= op; |
3245 | 0 | break; |
3246 | 0 | } |
3247 | 0 | case LoongArch::XVINSVE0_D: { |
3248 | | // op: imm2 |
3249 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3250 | 0 | op &= UINT64_C(3); |
3251 | 0 | op <<= 10; |
3252 | 0 | Value |= op; |
3253 | | // op: xj |
3254 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3255 | 0 | op &= UINT64_C(31); |
3256 | 0 | op <<= 5; |
3257 | 0 | Value |= op; |
3258 | | // op: xd |
3259 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3260 | 0 | op &= UINT64_C(31); |
3261 | 0 | Value |= op; |
3262 | 0 | break; |
3263 | 0 | } |
3264 | 0 | case LoongArch::BYTEPICK_W: { |
3265 | | // op: imm2 |
3266 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3267 | 0 | op &= UINT64_C(3); |
3268 | 0 | op <<= 15; |
3269 | 0 | Value |= op; |
3270 | | // op: rk |
3271 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3272 | 0 | op &= UINT64_C(31); |
3273 | 0 | op <<= 10; |
3274 | 0 | Value |= op; |
3275 | | // op: rj |
3276 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3277 | 0 | op &= UINT64_C(31); |
3278 | 0 | op <<= 5; |
3279 | 0 | Value |= op; |
3280 | | // op: rd |
3281 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3282 | 0 | op &= UINT64_C(31); |
3283 | 0 | Value |= op; |
3284 | 0 | break; |
3285 | 0 | } |
3286 | 0 | case LoongArch::VSTELM_W: { |
3287 | | // op: imm2 |
3288 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3289 | 0 | op &= UINT64_C(3); |
3290 | 0 | op <<= 18; |
3291 | 0 | Value |= op; |
3292 | | // op: imm8 |
3293 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
3294 | 0 | op &= UINT64_C(255); |
3295 | 0 | op <<= 10; |
3296 | 0 | Value |= op; |
3297 | | // op: rj |
3298 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3299 | 0 | op &= UINT64_C(31); |
3300 | 0 | op <<= 5; |
3301 | 0 | Value |= op; |
3302 | | // op: vd |
3303 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3304 | 0 | op &= UINT64_C(31); |
3305 | 0 | Value |= op; |
3306 | 0 | break; |
3307 | 0 | } |
3308 | 0 | case LoongArch::XVSTELM_D: { |
3309 | | // op: imm2 |
3310 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3311 | 0 | op &= UINT64_C(3); |
3312 | 0 | op <<= 18; |
3313 | 0 | Value |= op; |
3314 | | // op: imm8 |
3315 | 0 | op = getImmOpValueAsr<3>(MI, 2, Fixups, STI); |
3316 | 0 | op &= UINT64_C(255); |
3317 | 0 | op <<= 10; |
3318 | 0 | Value |= op; |
3319 | | // op: rj |
3320 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3321 | 0 | op &= UINT64_C(31); |
3322 | 0 | op <<= 5; |
3323 | 0 | Value |= op; |
3324 | | // op: xd |
3325 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3326 | 0 | op &= UINT64_C(31); |
3327 | 0 | Value |= op; |
3328 | 0 | break; |
3329 | 0 | } |
3330 | 0 | case LoongArch::LU12I_W: |
3331 | 0 | case LoongArch::PCADDI: |
3332 | 0 | case LoongArch::PCADDU12I: |
3333 | 0 | case LoongArch::PCADDU18I: |
3334 | 0 | case LoongArch::PCALAU12I: { |
3335 | | // op: imm20 |
3336 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3337 | 0 | op &= UINT64_C(1048575); |
3338 | 0 | op <<= 5; |
3339 | 0 | Value |= op; |
3340 | | // op: rd |
3341 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3342 | 0 | op &= UINT64_C(31); |
3343 | 0 | Value |= op; |
3344 | 0 | break; |
3345 | 0 | } |
3346 | 0 | case LoongArch::LU32I_D: { |
3347 | | // op: imm20 |
3348 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3349 | 0 | op &= UINT64_C(1048575); |
3350 | 0 | op <<= 5; |
3351 | 0 | Value |= op; |
3352 | | // op: rd |
3353 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3354 | 0 | op &= UINT64_C(31); |
3355 | 0 | Value |= op; |
3356 | 0 | break; |
3357 | 0 | } |
3358 | 0 | case LoongArch::JISCR0: |
3359 | 0 | case LoongArch::JISCR1: { |
3360 | | // op: imm21 |
3361 | 0 | op = getImmOpValueAsr<2>(MI, 0, Fixups, STI); |
3362 | 0 | Value |= (op & UINT64_C(65535)) << 10; |
3363 | 0 | Value |= (op & UINT64_C(2031616)) >> 16; |
3364 | 0 | break; |
3365 | 0 | } |
3366 | 0 | case LoongArch::BCEQZ: |
3367 | 0 | case LoongArch::BCNEZ: { |
3368 | | // op: imm21 |
3369 | 0 | op = getImmOpValueAsr<2>(MI, 1, Fixups, STI); |
3370 | 0 | Value |= (op & UINT64_C(65535)) << 10; |
3371 | 0 | Value |= (op & UINT64_C(2031616)) >> 16; |
3372 | | // op: cj |
3373 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3374 | 0 | op &= UINT64_C(7); |
3375 | 0 | op <<= 5; |
3376 | 0 | Value |= op; |
3377 | 0 | break; |
3378 | 0 | } |
3379 | 0 | case LoongArch::BEQZ: |
3380 | 0 | case LoongArch::BNEZ: { |
3381 | | // op: imm21 |
3382 | 0 | op = getImmOpValueAsr<2>(MI, 1, Fixups, STI); |
3383 | 0 | Value |= (op & UINT64_C(65535)) << 10; |
3384 | 0 | Value |= (op & UINT64_C(2031616)) >> 16; |
3385 | | // op: rj |
3386 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3387 | 0 | op &= UINT64_C(31); |
3388 | 0 | op <<= 5; |
3389 | 0 | Value |= op; |
3390 | 0 | break; |
3391 | 0 | } |
3392 | 0 | case LoongArch::B: |
3393 | 0 | case LoongArch::BL: { |
3394 | | // op: imm26 |
3395 | 0 | op = getImmOpValueAsr<2>(MI, 0, Fixups, STI); |
3396 | 0 | Value |= (op & UINT64_C(65535)) << 10; |
3397 | 0 | Value |= (op & UINT64_C(67043328)) >> 16; |
3398 | 0 | break; |
3399 | 0 | } |
3400 | 0 | case LoongArch::X86RCLI_B: |
3401 | 0 | case LoongArch::X86RCRI_B: |
3402 | 0 | case LoongArch::X86ROTLI_B: |
3403 | 0 | case LoongArch::X86ROTRI_B: |
3404 | 0 | case LoongArch::X86SLLI_B: |
3405 | 0 | case LoongArch::X86SRAI_B: |
3406 | 0 | case LoongArch::X86SRLI_B: { |
3407 | | // op: imm3 |
3408 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3409 | 0 | op &= UINT64_C(7); |
3410 | 0 | op <<= 10; |
3411 | 0 | Value |= op; |
3412 | | // op: rj |
3413 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3414 | 0 | op &= UINT64_C(31); |
3415 | 0 | op <<= 5; |
3416 | 0 | Value |= op; |
3417 | 0 | break; |
3418 | 0 | } |
3419 | 0 | case LoongArch::RCRI_B: |
3420 | 0 | case LoongArch::ROTRI_B: { |
3421 | | // op: imm3 |
3422 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3423 | 0 | op &= UINT64_C(7); |
3424 | 0 | op <<= 10; |
3425 | 0 | Value |= op; |
3426 | | // op: rj |
3427 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3428 | 0 | op &= UINT64_C(31); |
3429 | 0 | op <<= 5; |
3430 | 0 | Value |= op; |
3431 | | // op: rd |
3432 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3433 | 0 | op &= UINT64_C(31); |
3434 | 0 | Value |= op; |
3435 | 0 | break; |
3436 | 0 | } |
3437 | 0 | case LoongArch::VPICKVE2GR_H: |
3438 | 0 | case LoongArch::VPICKVE2GR_HU: { |
3439 | | // op: imm3 |
3440 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3441 | 0 | op &= UINT64_C(7); |
3442 | 0 | op <<= 10; |
3443 | 0 | Value |= op; |
3444 | | // op: vj |
3445 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3446 | 0 | op &= UINT64_C(31); |
3447 | 0 | op <<= 5; |
3448 | 0 | Value |= op; |
3449 | | // op: rd |
3450 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3451 | 0 | op &= UINT64_C(31); |
3452 | 0 | Value |= op; |
3453 | 0 | break; |
3454 | 0 | } |
3455 | 0 | case LoongArch::VBITCLRI_B: |
3456 | 0 | case LoongArch::VBITREVI_B: |
3457 | 0 | case LoongArch::VBITSETI_B: |
3458 | 0 | case LoongArch::VREPLVEI_H: |
3459 | 0 | case LoongArch::VROTRI_B: |
3460 | 0 | case LoongArch::VSAT_B: |
3461 | 0 | case LoongArch::VSAT_BU: |
3462 | 0 | case LoongArch::VSLLI_B: |
3463 | 0 | case LoongArch::VSLLWIL_HU_BU: |
3464 | 0 | case LoongArch::VSLLWIL_H_B: |
3465 | 0 | case LoongArch::VSRAI_B: |
3466 | 0 | case LoongArch::VSRARI_B: |
3467 | 0 | case LoongArch::VSRLI_B: |
3468 | 0 | case LoongArch::VSRLRI_B: { |
3469 | | // op: imm3 |
3470 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3471 | 0 | op &= UINT64_C(7); |
3472 | 0 | op <<= 10; |
3473 | 0 | Value |= op; |
3474 | | // op: vj |
3475 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3476 | 0 | op &= UINT64_C(31); |
3477 | 0 | op <<= 5; |
3478 | 0 | Value |= op; |
3479 | | // op: vd |
3480 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3481 | 0 | op &= UINT64_C(31); |
3482 | 0 | Value |= op; |
3483 | 0 | break; |
3484 | 0 | } |
3485 | 0 | case LoongArch::XVPICKVE2GR_W: |
3486 | 0 | case LoongArch::XVPICKVE2GR_WU: { |
3487 | | // op: imm3 |
3488 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3489 | 0 | op &= UINT64_C(7); |
3490 | 0 | op <<= 10; |
3491 | 0 | Value |= op; |
3492 | | // op: xj |
3493 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3494 | 0 | op &= UINT64_C(31); |
3495 | 0 | op <<= 5; |
3496 | 0 | Value |= op; |
3497 | | // op: rd |
3498 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3499 | 0 | op &= UINT64_C(31); |
3500 | 0 | Value |= op; |
3501 | 0 | break; |
3502 | 0 | } |
3503 | 0 | case LoongArch::XVBITCLRI_B: |
3504 | 0 | case LoongArch::XVBITREVI_B: |
3505 | 0 | case LoongArch::XVBITSETI_B: |
3506 | 0 | case LoongArch::XVPICKVE_W: |
3507 | 0 | case LoongArch::XVREPL128VEI_H: |
3508 | 0 | case LoongArch::XVROTRI_B: |
3509 | 0 | case LoongArch::XVSAT_B: |
3510 | 0 | case LoongArch::XVSAT_BU: |
3511 | 0 | case LoongArch::XVSLLI_B: |
3512 | 0 | case LoongArch::XVSLLWIL_HU_BU: |
3513 | 0 | case LoongArch::XVSLLWIL_H_B: |
3514 | 0 | case LoongArch::XVSRAI_B: |
3515 | 0 | case LoongArch::XVSRARI_B: |
3516 | 0 | case LoongArch::XVSRLI_B: |
3517 | 0 | case LoongArch::XVSRLRI_B: { |
3518 | | // op: imm3 |
3519 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3520 | 0 | op &= UINT64_C(7); |
3521 | 0 | op <<= 10; |
3522 | 0 | Value |= op; |
3523 | | // op: xj |
3524 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3525 | 0 | op &= UINT64_C(31); |
3526 | 0 | op <<= 5; |
3527 | 0 | Value |= op; |
3528 | | // op: xd |
3529 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3530 | 0 | op &= UINT64_C(31); |
3531 | 0 | Value |= op; |
3532 | 0 | break; |
3533 | 0 | } |
3534 | 0 | case LoongArch::VINSGR2VR_H: { |
3535 | | // op: imm3 |
3536 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3537 | 0 | op &= UINT64_C(7); |
3538 | 0 | op <<= 10; |
3539 | 0 | Value |= op; |
3540 | | // op: rj |
3541 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3542 | 0 | op &= UINT64_C(31); |
3543 | 0 | op <<= 5; |
3544 | 0 | Value |= op; |
3545 | | // op: vd |
3546 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3547 | 0 | op &= UINT64_C(31); |
3548 | 0 | Value |= op; |
3549 | 0 | break; |
3550 | 0 | } |
3551 | 0 | case LoongArch::XVINSGR2VR_W: { |
3552 | | // op: imm3 |
3553 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3554 | 0 | op &= UINT64_C(7); |
3555 | 0 | op <<= 10; |
3556 | 0 | Value |= op; |
3557 | | // op: rj |
3558 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3559 | 0 | op &= UINT64_C(31); |
3560 | 0 | op <<= 5; |
3561 | 0 | Value |= op; |
3562 | | // op: xd |
3563 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3564 | 0 | op &= UINT64_C(31); |
3565 | 0 | Value |= op; |
3566 | 0 | break; |
3567 | 0 | } |
3568 | 0 | case LoongArch::XVINSVE0_W: { |
3569 | | // op: imm3 |
3570 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3571 | 0 | op &= UINT64_C(7); |
3572 | 0 | op <<= 10; |
3573 | 0 | Value |= op; |
3574 | | // op: xj |
3575 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3576 | 0 | op &= UINT64_C(31); |
3577 | 0 | op <<= 5; |
3578 | 0 | Value |= op; |
3579 | | // op: xd |
3580 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3581 | 0 | op &= UINT64_C(31); |
3582 | 0 | Value |= op; |
3583 | 0 | break; |
3584 | 0 | } |
3585 | 0 | case LoongArch::BYTEPICK_D: { |
3586 | | // op: imm3 |
3587 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3588 | 0 | op &= UINT64_C(7); |
3589 | 0 | op <<= 15; |
3590 | 0 | Value |= op; |
3591 | | // op: rk |
3592 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3593 | 0 | op &= UINT64_C(31); |
3594 | 0 | op <<= 10; |
3595 | 0 | Value |= op; |
3596 | | // op: rj |
3597 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3598 | 0 | op &= UINT64_C(31); |
3599 | 0 | op <<= 5; |
3600 | 0 | Value |= op; |
3601 | | // op: rd |
3602 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3603 | 0 | op &= UINT64_C(31); |
3604 | 0 | Value |= op; |
3605 | 0 | break; |
3606 | 0 | } |
3607 | 0 | case LoongArch::VSTELM_H: { |
3608 | | // op: imm3 |
3609 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3610 | 0 | op &= UINT64_C(7); |
3611 | 0 | op <<= 18; |
3612 | 0 | Value |= op; |
3613 | | // op: imm8 |
3614 | 0 | op = getImmOpValueAsr<1>(MI, 2, Fixups, STI); |
3615 | 0 | op &= UINT64_C(255); |
3616 | 0 | op <<= 10; |
3617 | 0 | Value |= op; |
3618 | | // op: rj |
3619 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3620 | 0 | op &= UINT64_C(31); |
3621 | 0 | op <<= 5; |
3622 | 0 | Value |= op; |
3623 | | // op: vd |
3624 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3625 | 0 | op &= UINT64_C(31); |
3626 | 0 | Value |= op; |
3627 | 0 | break; |
3628 | 0 | } |
3629 | 0 | case LoongArch::XVSTELM_W: { |
3630 | | // op: imm3 |
3631 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3632 | 0 | op &= UINT64_C(7); |
3633 | 0 | op <<= 18; |
3634 | 0 | Value |= op; |
3635 | | // op: imm8 |
3636 | 0 | op = getImmOpValueAsr<2>(MI, 2, Fixups, STI); |
3637 | 0 | op &= UINT64_C(255); |
3638 | 0 | op <<= 10; |
3639 | 0 | Value |= op; |
3640 | | // op: rj |
3641 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3642 | 0 | op &= UINT64_C(31); |
3643 | 0 | op <<= 5; |
3644 | 0 | Value |= op; |
3645 | | // op: xd |
3646 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3647 | 0 | op &= UINT64_C(31); |
3648 | 0 | Value |= op; |
3649 | 0 | break; |
3650 | 0 | } |
3651 | 0 | case LoongArch::SETARMJ: |
3652 | 0 | case LoongArch::SETX86J: { |
3653 | | // op: imm4 |
3654 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3655 | 0 | op &= UINT64_C(15); |
3656 | 0 | op <<= 10; |
3657 | 0 | Value |= op; |
3658 | | // op: rd |
3659 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3660 | 0 | op &= UINT64_C(31); |
3661 | 0 | Value |= op; |
3662 | 0 | break; |
3663 | 0 | } |
3664 | 0 | case LoongArch::ARMMOV_D: |
3665 | 0 | case LoongArch::ARMMOV_W: |
3666 | 0 | case LoongArch::ARMNOT_W: |
3667 | 0 | case LoongArch::ARMRRX_W: |
3668 | 0 | case LoongArch::X86RCLI_H: |
3669 | 0 | case LoongArch::X86RCRI_H: |
3670 | 0 | case LoongArch::X86ROTLI_H: |
3671 | 0 | case LoongArch::X86ROTRI_H: |
3672 | 0 | case LoongArch::X86SLLI_H: |
3673 | 0 | case LoongArch::X86SRAI_H: |
3674 | 0 | case LoongArch::X86SRLI_H: { |
3675 | | // op: imm4 |
3676 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3677 | 0 | op &= UINT64_C(15); |
3678 | 0 | op <<= 10; |
3679 | 0 | Value |= op; |
3680 | | // op: rj |
3681 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3682 | 0 | op &= UINT64_C(31); |
3683 | 0 | op <<= 5; |
3684 | 0 | Value |= op; |
3685 | 0 | break; |
3686 | 0 | } |
3687 | 0 | case LoongArch::ARMADC_W: |
3688 | 0 | case LoongArch::ARMADD_W: |
3689 | 0 | case LoongArch::ARMAND_W: |
3690 | 0 | case LoongArch::ARMOR_W: |
3691 | 0 | case LoongArch::ARMROTR_W: |
3692 | 0 | case LoongArch::ARMSBC_W: |
3693 | 0 | case LoongArch::ARMSLL_W: |
3694 | 0 | case LoongArch::ARMSRA_W: |
3695 | 0 | case LoongArch::ARMSRL_W: |
3696 | 0 | case LoongArch::ARMSUB_W: |
3697 | 0 | case LoongArch::ARMXOR_W: { |
3698 | | // op: imm4 |
3699 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3700 | 0 | op &= UINT64_C(15); |
3701 | 0 | Value |= op; |
3702 | | // op: rk |
3703 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3704 | 0 | op &= UINT64_C(31); |
3705 | 0 | op <<= 10; |
3706 | 0 | Value |= op; |
3707 | | // op: rj |
3708 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3709 | 0 | op &= UINT64_C(31); |
3710 | 0 | op <<= 5; |
3711 | 0 | Value |= op; |
3712 | 0 | break; |
3713 | 0 | } |
3714 | 0 | case LoongArch::ARMMOVE: |
3715 | 0 | case LoongArch::RCRI_H: |
3716 | 0 | case LoongArch::ROTRI_H: { |
3717 | | // op: imm4 |
3718 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3719 | 0 | op &= UINT64_C(15); |
3720 | 0 | op <<= 10; |
3721 | 0 | Value |= op; |
3722 | | // op: rj |
3723 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3724 | 0 | op &= UINT64_C(31); |
3725 | 0 | op <<= 5; |
3726 | 0 | Value |= op; |
3727 | | // op: rd |
3728 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3729 | 0 | op &= UINT64_C(31); |
3730 | 0 | Value |= op; |
3731 | 0 | break; |
3732 | 0 | } |
3733 | 0 | case LoongArch::VPICKVE2GR_B: |
3734 | 0 | case LoongArch::VPICKVE2GR_BU: { |
3735 | | // op: imm4 |
3736 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3737 | 0 | op &= UINT64_C(15); |
3738 | 0 | op <<= 10; |
3739 | 0 | Value |= op; |
3740 | | // op: vj |
3741 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3742 | 0 | op &= UINT64_C(31); |
3743 | 0 | op <<= 5; |
3744 | 0 | Value |= op; |
3745 | | // op: rd |
3746 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3747 | 0 | op &= UINT64_C(31); |
3748 | 0 | Value |= op; |
3749 | 0 | break; |
3750 | 0 | } |
3751 | 0 | case LoongArch::VBITCLRI_H: |
3752 | 0 | case LoongArch::VBITREVI_H: |
3753 | 0 | case LoongArch::VBITSETI_H: |
3754 | 0 | case LoongArch::VREPLVEI_B: |
3755 | 0 | case LoongArch::VROTRI_H: |
3756 | 0 | case LoongArch::VSAT_H: |
3757 | 0 | case LoongArch::VSAT_HU: |
3758 | 0 | case LoongArch::VSLLI_H: |
3759 | 0 | case LoongArch::VSLLWIL_WU_HU: |
3760 | 0 | case LoongArch::VSLLWIL_W_H: |
3761 | 0 | case LoongArch::VSRAI_H: |
3762 | 0 | case LoongArch::VSRARI_H: |
3763 | 0 | case LoongArch::VSRLI_H: |
3764 | 0 | case LoongArch::VSRLRI_H: { |
3765 | | // op: imm4 |
3766 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3767 | 0 | op &= UINT64_C(15); |
3768 | 0 | op <<= 10; |
3769 | 0 | Value |= op; |
3770 | | // op: vj |
3771 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3772 | 0 | op &= UINT64_C(31); |
3773 | 0 | op <<= 5; |
3774 | 0 | Value |= op; |
3775 | | // op: vd |
3776 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3777 | 0 | op &= UINT64_C(31); |
3778 | 0 | Value |= op; |
3779 | 0 | break; |
3780 | 0 | } |
3781 | 0 | case LoongArch::XVBITCLRI_H: |
3782 | 0 | case LoongArch::XVBITREVI_H: |
3783 | 0 | case LoongArch::XVBITSETI_H: |
3784 | 0 | case LoongArch::XVREPL128VEI_B: |
3785 | 0 | case LoongArch::XVROTRI_H: |
3786 | 0 | case LoongArch::XVSAT_H: |
3787 | 0 | case LoongArch::XVSAT_HU: |
3788 | 0 | case LoongArch::XVSLLI_H: |
3789 | 0 | case LoongArch::XVSLLWIL_WU_HU: |
3790 | 0 | case LoongArch::XVSLLWIL_W_H: |
3791 | 0 | case LoongArch::XVSRAI_H: |
3792 | 0 | case LoongArch::XVSRARI_H: |
3793 | 0 | case LoongArch::XVSRLI_H: |
3794 | 0 | case LoongArch::XVSRLRI_H: { |
3795 | | // op: imm4 |
3796 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3797 | 0 | op &= UINT64_C(15); |
3798 | 0 | op <<= 10; |
3799 | 0 | Value |= op; |
3800 | | // op: xj |
3801 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3802 | 0 | op &= UINT64_C(31); |
3803 | 0 | op <<= 5; |
3804 | 0 | Value |= op; |
3805 | | // op: xd |
3806 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3807 | 0 | op &= UINT64_C(31); |
3808 | 0 | Value |= op; |
3809 | 0 | break; |
3810 | 0 | } |
3811 | 0 | case LoongArch::VINSGR2VR_B: { |
3812 | | // op: imm4 |
3813 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3814 | 0 | op &= UINT64_C(15); |
3815 | 0 | op <<= 10; |
3816 | 0 | Value |= op; |
3817 | | // op: rj |
3818 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3819 | 0 | op &= UINT64_C(31); |
3820 | 0 | op <<= 5; |
3821 | 0 | Value |= op; |
3822 | | // op: vd |
3823 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3824 | 0 | op &= UINT64_C(31); |
3825 | 0 | Value |= op; |
3826 | 0 | break; |
3827 | 0 | } |
3828 | 0 | case LoongArch::VSRANI_B_H: |
3829 | 0 | case LoongArch::VSRARNI_B_H: |
3830 | 0 | case LoongArch::VSRLNI_B_H: |
3831 | 0 | case LoongArch::VSRLRNI_B_H: |
3832 | 0 | case LoongArch::VSSRANI_BU_H: |
3833 | 0 | case LoongArch::VSSRANI_B_H: |
3834 | 0 | case LoongArch::VSSRARNI_BU_H: |
3835 | 0 | case LoongArch::VSSRARNI_B_H: |
3836 | 0 | case LoongArch::VSSRLNI_BU_H: |
3837 | 0 | case LoongArch::VSSRLNI_B_H: |
3838 | 0 | case LoongArch::VSSRLRNI_BU_H: |
3839 | 0 | case LoongArch::VSSRLRNI_B_H: { |
3840 | | // op: imm4 |
3841 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3842 | 0 | op &= UINT64_C(15); |
3843 | 0 | op <<= 10; |
3844 | 0 | Value |= op; |
3845 | | // op: vj |
3846 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3847 | 0 | op &= UINT64_C(31); |
3848 | 0 | op <<= 5; |
3849 | 0 | Value |= op; |
3850 | | // op: vd |
3851 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3852 | 0 | op &= UINT64_C(31); |
3853 | 0 | Value |= op; |
3854 | 0 | break; |
3855 | 0 | } |
3856 | 0 | case LoongArch::XVSRANI_B_H: |
3857 | 0 | case LoongArch::XVSRARNI_B_H: |
3858 | 0 | case LoongArch::XVSRLNI_B_H: |
3859 | 0 | case LoongArch::XVSRLRNI_B_H: |
3860 | 0 | case LoongArch::XVSSRANI_BU_H: |
3861 | 0 | case LoongArch::XVSSRANI_B_H: |
3862 | 0 | case LoongArch::XVSSRARNI_BU_H: |
3863 | 0 | case LoongArch::XVSSRARNI_B_H: |
3864 | 0 | case LoongArch::XVSSRLNI_BU_H: |
3865 | 0 | case LoongArch::XVSSRLNI_B_H: |
3866 | 0 | case LoongArch::XVSSRLRNI_BU_H: |
3867 | 0 | case LoongArch::XVSSRLRNI_B_H: { |
3868 | | // op: imm4 |
3869 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3870 | 0 | op &= UINT64_C(15); |
3871 | 0 | op <<= 10; |
3872 | 0 | Value |= op; |
3873 | | // op: xj |
3874 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3875 | 0 | op &= UINT64_C(31); |
3876 | 0 | op <<= 5; |
3877 | 0 | Value |= op; |
3878 | | // op: xd |
3879 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3880 | 0 | op &= UINT64_C(31); |
3881 | 0 | Value |= op; |
3882 | 0 | break; |
3883 | 0 | } |
3884 | 0 | case LoongArch::XVSTELM_H: { |
3885 | | // op: imm4 |
3886 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3887 | 0 | op &= UINT64_C(15); |
3888 | 0 | op <<= 18; |
3889 | 0 | Value |= op; |
3890 | | // op: imm8 |
3891 | 0 | op = getImmOpValueAsr<1>(MI, 2, Fixups, STI); |
3892 | 0 | op &= UINT64_C(255); |
3893 | 0 | op <<= 10; |
3894 | 0 | Value |= op; |
3895 | | // op: rj |
3896 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3897 | 0 | op &= UINT64_C(31); |
3898 | 0 | op <<= 5; |
3899 | 0 | Value |= op; |
3900 | | // op: xd |
3901 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3902 | 0 | op &= UINT64_C(31); |
3903 | 0 | Value |= op; |
3904 | 0 | break; |
3905 | 0 | } |
3906 | 0 | case LoongArch::VSTELM_B: { |
3907 | | // op: imm4 |
3908 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3909 | 0 | op &= UINT64_C(15); |
3910 | 0 | op <<= 18; |
3911 | 0 | Value |= op; |
3912 | | // op: imm8 |
3913 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3914 | 0 | op &= UINT64_C(255); |
3915 | 0 | op <<= 10; |
3916 | 0 | Value |= op; |
3917 | | // op: rj |
3918 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3919 | 0 | op &= UINT64_C(31); |
3920 | 0 | op <<= 5; |
3921 | 0 | Value |= op; |
3922 | | // op: vd |
3923 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3924 | 0 | op &= UINT64_C(31); |
3925 | 0 | Value |= op; |
3926 | 0 | break; |
3927 | 0 | } |
3928 | 0 | case LoongArch::X86RCLI_W: |
3929 | 0 | case LoongArch::X86RCRI_W: |
3930 | 0 | case LoongArch::X86ROTLI_W: |
3931 | 0 | case LoongArch::X86ROTRI_W: |
3932 | 0 | case LoongArch::X86SLLI_W: |
3933 | 0 | case LoongArch::X86SRAI_W: |
3934 | 0 | case LoongArch::X86SRLI_W: { |
3935 | | // op: imm5 |
3936 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3937 | 0 | op &= UINT64_C(31); |
3938 | 0 | op <<= 10; |
3939 | 0 | Value |= op; |
3940 | | // op: rj |
3941 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3942 | 0 | op &= UINT64_C(31); |
3943 | 0 | op <<= 5; |
3944 | 0 | Value |= op; |
3945 | 0 | break; |
3946 | 0 | } |
3947 | 0 | case LoongArch::ARMROTRI_W: |
3948 | 0 | case LoongArch::ARMSLLI_W: |
3949 | 0 | case LoongArch::ARMSRAI_W: |
3950 | 0 | case LoongArch::ARMSRLI_W: { |
3951 | | // op: imm5 |
3952 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3953 | 0 | op &= UINT64_C(31); |
3954 | 0 | op <<= 10; |
3955 | 0 | Value |= op; |
3956 | | // op: rj |
3957 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3958 | 0 | op &= UINT64_C(31); |
3959 | 0 | op <<= 5; |
3960 | 0 | Value |= op; |
3961 | | // op: imm4 |
3962 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3963 | 0 | op &= UINT64_C(15); |
3964 | 0 | Value |= op; |
3965 | 0 | break; |
3966 | 0 | } |
3967 | 0 | case LoongArch::ADDU12I_D: |
3968 | 0 | case LoongArch::ADDU12I_W: |
3969 | 0 | case LoongArch::RCRI_W: |
3970 | 0 | case LoongArch::ROTRI_W: |
3971 | 0 | case LoongArch::SLLI_W: |
3972 | 0 | case LoongArch::SRAI_W: |
3973 | 0 | case LoongArch::SRLI_W: { |
3974 | | // op: imm5 |
3975 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3976 | 0 | op &= UINT64_C(31); |
3977 | 0 | op <<= 10; |
3978 | 0 | Value |= op; |
3979 | | // op: rj |
3980 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3981 | 0 | op &= UINT64_C(31); |
3982 | 0 | op <<= 5; |
3983 | 0 | Value |= op; |
3984 | | // op: rd |
3985 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3986 | 0 | op &= UINT64_C(31); |
3987 | 0 | Value |= op; |
3988 | 0 | break; |
3989 | 0 | } |
3990 | 0 | case LoongArch::VADDI_BU: |
3991 | 0 | case LoongArch::VADDI_DU: |
3992 | 0 | case LoongArch::VADDI_HU: |
3993 | 0 | case LoongArch::VADDI_WU: |
3994 | 0 | case LoongArch::VBITCLRI_W: |
3995 | 0 | case LoongArch::VBITREVI_W: |
3996 | 0 | case LoongArch::VBITSETI_W: |
3997 | 0 | case LoongArch::VBSLL_V: |
3998 | 0 | case LoongArch::VBSRL_V: |
3999 | 0 | case LoongArch::VMAXI_B: |
4000 | 0 | case LoongArch::VMAXI_BU: |
4001 | 0 | case LoongArch::VMAXI_D: |
4002 | 0 | case LoongArch::VMAXI_DU: |
4003 | 0 | case LoongArch::VMAXI_H: |
4004 | 0 | case LoongArch::VMAXI_HU: |
4005 | 0 | case LoongArch::VMAXI_W: |
4006 | 0 | case LoongArch::VMAXI_WU: |
4007 | 0 | case LoongArch::VMINI_B: |
4008 | 0 | case LoongArch::VMINI_BU: |
4009 | 0 | case LoongArch::VMINI_D: |
4010 | 0 | case LoongArch::VMINI_DU: |
4011 | 0 | case LoongArch::VMINI_H: |
4012 | 0 | case LoongArch::VMINI_HU: |
4013 | 0 | case LoongArch::VMINI_W: |
4014 | 0 | case LoongArch::VMINI_WU: |
4015 | 0 | case LoongArch::VROTRI_W: |
4016 | 0 | case LoongArch::VSAT_W: |
4017 | 0 | case LoongArch::VSAT_WU: |
4018 | 0 | case LoongArch::VSEQI_B: |
4019 | 0 | case LoongArch::VSEQI_D: |
4020 | 0 | case LoongArch::VSEQI_H: |
4021 | 0 | case LoongArch::VSEQI_W: |
4022 | 0 | case LoongArch::VSLEI_B: |
4023 | 0 | case LoongArch::VSLEI_BU: |
4024 | 0 | case LoongArch::VSLEI_D: |
4025 | 0 | case LoongArch::VSLEI_DU: |
4026 | 0 | case LoongArch::VSLEI_H: |
4027 | 0 | case LoongArch::VSLEI_HU: |
4028 | 0 | case LoongArch::VSLEI_W: |
4029 | 0 | case LoongArch::VSLEI_WU: |
4030 | 0 | case LoongArch::VSLLI_W: |
4031 | 0 | case LoongArch::VSLLWIL_DU_WU: |
4032 | 0 | case LoongArch::VSLLWIL_D_W: |
4033 | 0 | case LoongArch::VSLTI_B: |
4034 | 0 | case LoongArch::VSLTI_BU: |
4035 | 0 | case LoongArch::VSLTI_D: |
4036 | 0 | case LoongArch::VSLTI_DU: |
4037 | 0 | case LoongArch::VSLTI_H: |
4038 | 0 | case LoongArch::VSLTI_HU: |
4039 | 0 | case LoongArch::VSLTI_W: |
4040 | 0 | case LoongArch::VSLTI_WU: |
4041 | 0 | case LoongArch::VSRAI_W: |
4042 | 0 | case LoongArch::VSRARI_W: |
4043 | 0 | case LoongArch::VSRLI_W: |
4044 | 0 | case LoongArch::VSRLRI_W: |
4045 | 0 | case LoongArch::VSUBI_BU: |
4046 | 0 | case LoongArch::VSUBI_DU: |
4047 | 0 | case LoongArch::VSUBI_HU: |
4048 | 0 | case LoongArch::VSUBI_WU: { |
4049 | | // op: imm5 |
4050 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4051 | 0 | op &= UINT64_C(31); |
4052 | 0 | op <<= 10; |
4053 | 0 | Value |= op; |
4054 | | // op: vj |
4055 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4056 | 0 | op &= UINT64_C(31); |
4057 | 0 | op <<= 5; |
4058 | 0 | Value |= op; |
4059 | | // op: vd |
4060 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4061 | 0 | op &= UINT64_C(31); |
4062 | 0 | Value |= op; |
4063 | 0 | break; |
4064 | 0 | } |
4065 | 0 | case LoongArch::XVADDI_BU: |
4066 | 0 | case LoongArch::XVADDI_DU: |
4067 | 0 | case LoongArch::XVADDI_HU: |
4068 | 0 | case LoongArch::XVADDI_WU: |
4069 | 0 | case LoongArch::XVBITCLRI_W: |
4070 | 0 | case LoongArch::XVBITREVI_W: |
4071 | 0 | case LoongArch::XVBITSETI_W: |
4072 | 0 | case LoongArch::XVBSLL_V: |
4073 | 0 | case LoongArch::XVBSRL_V: |
4074 | 0 | case LoongArch::XVHSELI_D: |
4075 | 0 | case LoongArch::XVMAXI_B: |
4076 | 0 | case LoongArch::XVMAXI_BU: |
4077 | 0 | case LoongArch::XVMAXI_D: |
4078 | 0 | case LoongArch::XVMAXI_DU: |
4079 | 0 | case LoongArch::XVMAXI_H: |
4080 | 0 | case LoongArch::XVMAXI_HU: |
4081 | 0 | case LoongArch::XVMAXI_W: |
4082 | 0 | case LoongArch::XVMAXI_WU: |
4083 | 0 | case LoongArch::XVMINI_B: |
4084 | 0 | case LoongArch::XVMINI_BU: |
4085 | 0 | case LoongArch::XVMINI_D: |
4086 | 0 | case LoongArch::XVMINI_DU: |
4087 | 0 | case LoongArch::XVMINI_H: |
4088 | 0 | case LoongArch::XVMINI_HU: |
4089 | 0 | case LoongArch::XVMINI_W: |
4090 | 0 | case LoongArch::XVMINI_WU: |
4091 | 0 | case LoongArch::XVROTRI_W: |
4092 | 0 | case LoongArch::XVSAT_W: |
4093 | 0 | case LoongArch::XVSAT_WU: |
4094 | 0 | case LoongArch::XVSEQI_B: |
4095 | 0 | case LoongArch::XVSEQI_D: |
4096 | 0 | case LoongArch::XVSEQI_H: |
4097 | 0 | case LoongArch::XVSEQI_W: |
4098 | 0 | case LoongArch::XVSLEI_B: |
4099 | 0 | case LoongArch::XVSLEI_BU: |
4100 | 0 | case LoongArch::XVSLEI_D: |
4101 | 0 | case LoongArch::XVSLEI_DU: |
4102 | 0 | case LoongArch::XVSLEI_H: |
4103 | 0 | case LoongArch::XVSLEI_HU: |
4104 | 0 | case LoongArch::XVSLEI_W: |
4105 | 0 | case LoongArch::XVSLEI_WU: |
4106 | 0 | case LoongArch::XVSLLI_W: |
4107 | 0 | case LoongArch::XVSLLWIL_DU_WU: |
4108 | 0 | case LoongArch::XVSLLWIL_D_W: |
4109 | 0 | case LoongArch::XVSLTI_B: |
4110 | 0 | case LoongArch::XVSLTI_BU: |
4111 | 0 | case LoongArch::XVSLTI_D: |
4112 | 0 | case LoongArch::XVSLTI_DU: |
4113 | 0 | case LoongArch::XVSLTI_H: |
4114 | 0 | case LoongArch::XVSLTI_HU: |
4115 | 0 | case LoongArch::XVSLTI_W: |
4116 | 0 | case LoongArch::XVSLTI_WU: |
4117 | 0 | case LoongArch::XVSRAI_W: |
4118 | 0 | case LoongArch::XVSRARI_W: |
4119 | 0 | case LoongArch::XVSRLI_W: |
4120 | 0 | case LoongArch::XVSRLRI_W: |
4121 | 0 | case LoongArch::XVSUBI_BU: |
4122 | 0 | case LoongArch::XVSUBI_DU: |
4123 | 0 | case LoongArch::XVSUBI_HU: |
4124 | 0 | case LoongArch::XVSUBI_WU: { |
4125 | | // op: imm5 |
4126 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4127 | 0 | op &= UINT64_C(31); |
4128 | 0 | op <<= 10; |
4129 | 0 | Value |= op; |
4130 | | // op: xj |
4131 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4132 | 0 | op &= UINT64_C(31); |
4133 | 0 | op <<= 5; |
4134 | 0 | Value |= op; |
4135 | | // op: xd |
4136 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4137 | 0 | op &= UINT64_C(31); |
4138 | 0 | Value |= op; |
4139 | 0 | break; |
4140 | 0 | } |
4141 | 0 | case LoongArch::VFRSTPI_B: |
4142 | 0 | case LoongArch::VFRSTPI_H: |
4143 | 0 | case LoongArch::VSRANI_H_W: |
4144 | 0 | case LoongArch::VSRARNI_H_W: |
4145 | 0 | case LoongArch::VSRLNI_H_W: |
4146 | 0 | case LoongArch::VSRLRNI_H_W: |
4147 | 0 | case LoongArch::VSSRANI_HU_W: |
4148 | 0 | case LoongArch::VSSRANI_H_W: |
4149 | 0 | case LoongArch::VSSRARNI_HU_W: |
4150 | 0 | case LoongArch::VSSRARNI_H_W: |
4151 | 0 | case LoongArch::VSSRLNI_HU_W: |
4152 | 0 | case LoongArch::VSSRLNI_H_W: |
4153 | 0 | case LoongArch::VSSRLRNI_HU_W: |
4154 | 0 | case LoongArch::VSSRLRNI_H_W: { |
4155 | | // op: imm5 |
4156 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4157 | 0 | op &= UINT64_C(31); |
4158 | 0 | op <<= 10; |
4159 | 0 | Value |= op; |
4160 | | // op: vj |
4161 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4162 | 0 | op &= UINT64_C(31); |
4163 | 0 | op <<= 5; |
4164 | 0 | Value |= op; |
4165 | | // op: vd |
4166 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4167 | 0 | op &= UINT64_C(31); |
4168 | 0 | Value |= op; |
4169 | 0 | break; |
4170 | 0 | } |
4171 | 0 | case LoongArch::XVFRSTPI_B: |
4172 | 0 | case LoongArch::XVFRSTPI_H: |
4173 | 0 | case LoongArch::XVSRANI_H_W: |
4174 | 0 | case LoongArch::XVSRARNI_H_W: |
4175 | 0 | case LoongArch::XVSRLNI_H_W: |
4176 | 0 | case LoongArch::XVSRLRNI_H_W: |
4177 | 0 | case LoongArch::XVSSRANI_HU_W: |
4178 | 0 | case LoongArch::XVSSRANI_H_W: |
4179 | 0 | case LoongArch::XVSSRARNI_HU_W: |
4180 | 0 | case LoongArch::XVSSRARNI_H_W: |
4181 | 0 | case LoongArch::XVSSRLNI_HU_W: |
4182 | 0 | case LoongArch::XVSSRLNI_H_W: |
4183 | 0 | case LoongArch::XVSSRLRNI_HU_W: |
4184 | 0 | case LoongArch::XVSSRLRNI_H_W: { |
4185 | | // op: imm5 |
4186 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4187 | 0 | op &= UINT64_C(31); |
4188 | 0 | op <<= 10; |
4189 | 0 | Value |= op; |
4190 | | // op: xj |
4191 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4192 | 0 | op &= UINT64_C(31); |
4193 | 0 | op <<= 5; |
4194 | 0 | Value |= op; |
4195 | | // op: xd |
4196 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4197 | 0 | op &= UINT64_C(31); |
4198 | 0 | Value |= op; |
4199 | 0 | break; |
4200 | 0 | } |
4201 | 0 | case LoongArch::XVSTELM_B: { |
4202 | | // op: imm5 |
4203 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4204 | 0 | op &= UINT64_C(31); |
4205 | 0 | op <<= 18; |
4206 | 0 | Value |= op; |
4207 | | // op: imm8 |
4208 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4209 | 0 | op &= UINT64_C(255); |
4210 | 0 | op <<= 10; |
4211 | 0 | Value |= op; |
4212 | | // op: rj |
4213 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4214 | 0 | op &= UINT64_C(31); |
4215 | 0 | op <<= 5; |
4216 | 0 | Value |= op; |
4217 | | // op: xd |
4218 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4219 | 0 | op &= UINT64_C(31); |
4220 | 0 | Value |= op; |
4221 | 0 | break; |
4222 | 0 | } |
4223 | 0 | case LoongArch::X86RCLI_D: |
4224 | 0 | case LoongArch::X86RCRI_D: |
4225 | 0 | case LoongArch::X86ROTLI_D: |
4226 | 0 | case LoongArch::X86ROTRI_D: |
4227 | 0 | case LoongArch::X86SLLI_D: |
4228 | 0 | case LoongArch::X86SRAI_D: |
4229 | 0 | case LoongArch::X86SRLI_D: { |
4230 | | // op: imm6 |
4231 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4232 | 0 | op &= UINT64_C(63); |
4233 | 0 | op <<= 10; |
4234 | 0 | Value |= op; |
4235 | | // op: rj |
4236 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4237 | 0 | op &= UINT64_C(31); |
4238 | 0 | op <<= 5; |
4239 | 0 | Value |= op; |
4240 | 0 | break; |
4241 | 0 | } |
4242 | 0 | case LoongArch::RCRI_D: |
4243 | 0 | case LoongArch::ROTRI_D: |
4244 | 0 | case LoongArch::SLLI_D: |
4245 | 0 | case LoongArch::SRAI_D: |
4246 | 0 | case LoongArch::SRLI_D: { |
4247 | | // op: imm6 |
4248 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4249 | 0 | op &= UINT64_C(63); |
4250 | 0 | op <<= 10; |
4251 | 0 | Value |= op; |
4252 | | // op: rj |
4253 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4254 | 0 | op &= UINT64_C(31); |
4255 | 0 | op <<= 5; |
4256 | 0 | Value |= op; |
4257 | | // op: rd |
4258 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4259 | 0 | op &= UINT64_C(31); |
4260 | 0 | Value |= op; |
4261 | 0 | break; |
4262 | 0 | } |
4263 | 0 | case LoongArch::VBITCLRI_D: |
4264 | 0 | case LoongArch::VBITREVI_D: |
4265 | 0 | case LoongArch::VBITSETI_D: |
4266 | 0 | case LoongArch::VROTRI_D: |
4267 | 0 | case LoongArch::VSAT_D: |
4268 | 0 | case LoongArch::VSAT_DU: |
4269 | 0 | case LoongArch::VSLLI_D: |
4270 | 0 | case LoongArch::VSRAI_D: |
4271 | 0 | case LoongArch::VSRARI_D: |
4272 | 0 | case LoongArch::VSRLI_D: |
4273 | 0 | case LoongArch::VSRLRI_D: { |
4274 | | // op: imm6 |
4275 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4276 | 0 | op &= UINT64_C(63); |
4277 | 0 | op <<= 10; |
4278 | 0 | Value |= op; |
4279 | | // op: vj |
4280 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4281 | 0 | op &= UINT64_C(31); |
4282 | 0 | op <<= 5; |
4283 | 0 | Value |= op; |
4284 | | // op: vd |
4285 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4286 | 0 | op &= UINT64_C(31); |
4287 | 0 | Value |= op; |
4288 | 0 | break; |
4289 | 0 | } |
4290 | 0 | case LoongArch::XVBITCLRI_D: |
4291 | 0 | case LoongArch::XVBITREVI_D: |
4292 | 0 | case LoongArch::XVBITSETI_D: |
4293 | 0 | case LoongArch::XVROTRI_D: |
4294 | 0 | case LoongArch::XVSAT_D: |
4295 | 0 | case LoongArch::XVSAT_DU: |
4296 | 0 | case LoongArch::XVSLLI_D: |
4297 | 0 | case LoongArch::XVSRAI_D: |
4298 | 0 | case LoongArch::XVSRARI_D: |
4299 | 0 | case LoongArch::XVSRLI_D: |
4300 | 0 | case LoongArch::XVSRLRI_D: { |
4301 | | // op: imm6 |
4302 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4303 | 0 | op &= UINT64_C(63); |
4304 | 0 | op <<= 10; |
4305 | 0 | Value |= op; |
4306 | | // op: xj |
4307 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4308 | 0 | op &= UINT64_C(31); |
4309 | 0 | op <<= 5; |
4310 | 0 | Value |= op; |
4311 | | // op: xd |
4312 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4313 | 0 | op &= UINT64_C(31); |
4314 | 0 | Value |= op; |
4315 | 0 | break; |
4316 | 0 | } |
4317 | 0 | case LoongArch::VSRANI_W_D: |
4318 | 0 | case LoongArch::VSRARNI_W_D: |
4319 | 0 | case LoongArch::VSRLNI_W_D: |
4320 | 0 | case LoongArch::VSRLRNI_W_D: |
4321 | 0 | case LoongArch::VSSRANI_WU_D: |
4322 | 0 | case LoongArch::VSSRANI_W_D: |
4323 | 0 | case LoongArch::VSSRARNI_WU_D: |
4324 | 0 | case LoongArch::VSSRARNI_W_D: |
4325 | 0 | case LoongArch::VSSRLNI_WU_D: |
4326 | 0 | case LoongArch::VSSRLNI_W_D: |
4327 | 0 | case LoongArch::VSSRLRNI_WU_D: |
4328 | 0 | case LoongArch::VSSRLRNI_W_D: { |
4329 | | // op: imm6 |
4330 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4331 | 0 | op &= UINT64_C(63); |
4332 | 0 | op <<= 10; |
4333 | 0 | Value |= op; |
4334 | | // op: vj |
4335 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4336 | 0 | op &= UINT64_C(31); |
4337 | 0 | op <<= 5; |
4338 | 0 | Value |= op; |
4339 | | // op: vd |
4340 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4341 | 0 | op &= UINT64_C(31); |
4342 | 0 | Value |= op; |
4343 | 0 | break; |
4344 | 0 | } |
4345 | 0 | case LoongArch::XVSRANI_W_D: |
4346 | 0 | case LoongArch::XVSRARNI_W_D: |
4347 | 0 | case LoongArch::XVSRLNI_W_D: |
4348 | 0 | case LoongArch::XVSRLRNI_W_D: |
4349 | 0 | case LoongArch::XVSSRANI_WU_D: |
4350 | 0 | case LoongArch::XVSSRANI_W_D: |
4351 | 0 | case LoongArch::XVSSRARNI_WU_D: |
4352 | 0 | case LoongArch::XVSSRARNI_W_D: |
4353 | 0 | case LoongArch::XVSSRLNI_WU_D: |
4354 | 0 | case LoongArch::XVSSRLNI_W_D: |
4355 | 0 | case LoongArch::XVSSRLRNI_WU_D: |
4356 | 0 | case LoongArch::XVSSRLRNI_W_D: { |
4357 | | // op: imm6 |
4358 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4359 | 0 | op &= UINT64_C(63); |
4360 | 0 | op <<= 10; |
4361 | 0 | Value |= op; |
4362 | | // op: xj |
4363 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4364 | 0 | op &= UINT64_C(31); |
4365 | 0 | op <<= 5; |
4366 | 0 | Value |= op; |
4367 | | // op: xd |
4368 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4369 | 0 | op &= UINT64_C(31); |
4370 | 0 | Value |= op; |
4371 | 0 | break; |
4372 | 0 | } |
4373 | 0 | case LoongArch::VSRANI_D_Q: |
4374 | 0 | case LoongArch::VSRARNI_D_Q: |
4375 | 0 | case LoongArch::VSRLNI_D_Q: |
4376 | 0 | case LoongArch::VSRLRNI_D_Q: |
4377 | 0 | case LoongArch::VSSRANI_DU_Q: |
4378 | 0 | case LoongArch::VSSRANI_D_Q: |
4379 | 0 | case LoongArch::VSSRARNI_DU_Q: |
4380 | 0 | case LoongArch::VSSRARNI_D_Q: |
4381 | 0 | case LoongArch::VSSRLNI_DU_Q: |
4382 | 0 | case LoongArch::VSSRLNI_D_Q: |
4383 | 0 | case LoongArch::VSSRLRNI_DU_Q: |
4384 | 0 | case LoongArch::VSSRLRNI_D_Q: { |
4385 | | // op: imm7 |
4386 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4387 | 0 | op &= UINT64_C(127); |
4388 | 0 | op <<= 10; |
4389 | 0 | Value |= op; |
4390 | | // op: vj |
4391 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4392 | 0 | op &= UINT64_C(31); |
4393 | 0 | op <<= 5; |
4394 | 0 | Value |= op; |
4395 | | // op: vd |
4396 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4397 | 0 | op &= UINT64_C(31); |
4398 | 0 | Value |= op; |
4399 | 0 | break; |
4400 | 0 | } |
4401 | 0 | case LoongArch::XVSRANI_D_Q: |
4402 | 0 | case LoongArch::XVSRARNI_D_Q: |
4403 | 0 | case LoongArch::XVSRLNI_D_Q: |
4404 | 0 | case LoongArch::XVSRLRNI_D_Q: |
4405 | 0 | case LoongArch::XVSSRANI_DU_Q: |
4406 | 0 | case LoongArch::XVSSRANI_D_Q: |
4407 | 0 | case LoongArch::XVSSRARNI_DU_Q: |
4408 | 0 | case LoongArch::XVSSRARNI_D_Q: |
4409 | 0 | case LoongArch::XVSSRLNI_DU_Q: |
4410 | 0 | case LoongArch::XVSSRLNI_D_Q: |
4411 | 0 | case LoongArch::XVSSRLRNI_DU_Q: |
4412 | 0 | case LoongArch::XVSSRLRNI_D_Q: { |
4413 | | // op: imm7 |
4414 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4415 | 0 | op &= UINT64_C(127); |
4416 | 0 | op <<= 10; |
4417 | 0 | Value |= op; |
4418 | | // op: xj |
4419 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4420 | 0 | op &= UINT64_C(31); |
4421 | 0 | op <<= 5; |
4422 | 0 | Value |= op; |
4423 | | // op: xd |
4424 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4425 | 0 | op &= UINT64_C(31); |
4426 | 0 | Value |= op; |
4427 | 0 | break; |
4428 | 0 | } |
4429 | 0 | case LoongArch::ARMMFFLAG: |
4430 | 0 | case LoongArch::ARMMTFLAG: |
4431 | 0 | case LoongArch::X86MFFLAG: |
4432 | 0 | case LoongArch::X86MTFLAG: { |
4433 | | // op: imm8 |
4434 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4435 | 0 | op &= UINT64_C(255); |
4436 | 0 | op <<= 10; |
4437 | 0 | Value |= op; |
4438 | | // op: rd |
4439 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4440 | 0 | op &= UINT64_C(31); |
4441 | 0 | Value |= op; |
4442 | 0 | break; |
4443 | 0 | } |
4444 | 0 | case LoongArch::X86SETTAG: { |
4445 | | // op: imm8 |
4446 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4447 | 0 | op &= UINT64_C(255); |
4448 | 0 | op <<= 10; |
4449 | 0 | Value |= op; |
4450 | | // op: imm5 |
4451 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4452 | 0 | op &= UINT64_C(31); |
4453 | 0 | op <<= 5; |
4454 | 0 | Value |= op; |
4455 | | // op: rd |
4456 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4457 | 0 | op &= UINT64_C(31); |
4458 | 0 | Value |= op; |
4459 | 0 | break; |
4460 | 0 | } |
4461 | 0 | case LoongArch::LDDIR: { |
4462 | | // op: imm8 |
4463 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4464 | 0 | op &= UINT64_C(255); |
4465 | 0 | op <<= 10; |
4466 | 0 | Value |= op; |
4467 | | // op: rj |
4468 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4469 | 0 | op &= UINT64_C(31); |
4470 | 0 | op <<= 5; |
4471 | 0 | Value |= op; |
4472 | | // op: rd |
4473 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4474 | 0 | op &= UINT64_C(31); |
4475 | 0 | Value |= op; |
4476 | 0 | break; |
4477 | 0 | } |
4478 | 0 | case LoongArch::VANDI_B: |
4479 | 0 | case LoongArch::VNORI_B: |
4480 | 0 | case LoongArch::VORI_B: |
4481 | 0 | case LoongArch::VSHUF4I_B: |
4482 | 0 | case LoongArch::VSHUF4I_H: |
4483 | 0 | case LoongArch::VSHUF4I_W: |
4484 | 0 | case LoongArch::VXORI_B: { |
4485 | | // op: imm8 |
4486 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4487 | 0 | op &= UINT64_C(255); |
4488 | 0 | op <<= 10; |
4489 | 0 | Value |= op; |
4490 | | // op: vj |
4491 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4492 | 0 | op &= UINT64_C(31); |
4493 | 0 | op <<= 5; |
4494 | 0 | Value |= op; |
4495 | | // op: vd |
4496 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4497 | 0 | op &= UINT64_C(31); |
4498 | 0 | Value |= op; |
4499 | 0 | break; |
4500 | 0 | } |
4501 | 0 | case LoongArch::XVANDI_B: |
4502 | 0 | case LoongArch::XVNORI_B: |
4503 | 0 | case LoongArch::XVORI_B: |
4504 | 0 | case LoongArch::XVPERMI_D: |
4505 | 0 | case LoongArch::XVSHUF4I_B: |
4506 | 0 | case LoongArch::XVSHUF4I_H: |
4507 | 0 | case LoongArch::XVSHUF4I_W: |
4508 | 0 | case LoongArch::XVXORI_B: { |
4509 | | // op: imm8 |
4510 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4511 | 0 | op &= UINT64_C(255); |
4512 | 0 | op <<= 10; |
4513 | 0 | Value |= op; |
4514 | | // op: xj |
4515 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4516 | 0 | op &= UINT64_C(31); |
4517 | 0 | op <<= 5; |
4518 | 0 | Value |= op; |
4519 | | // op: xd |
4520 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4521 | 0 | op &= UINT64_C(31); |
4522 | 0 | Value |= op; |
4523 | 0 | break; |
4524 | 0 | } |
4525 | 0 | case LoongArch::VBITSELI_B: |
4526 | 0 | case LoongArch::VEXTRINS_B: |
4527 | 0 | case LoongArch::VEXTRINS_D: |
4528 | 0 | case LoongArch::VEXTRINS_H: |
4529 | 0 | case LoongArch::VEXTRINS_W: |
4530 | 0 | case LoongArch::VPERMI_W: |
4531 | 0 | case LoongArch::VSHUF4I_D: { |
4532 | | // op: imm8 |
4533 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4534 | 0 | op &= UINT64_C(255); |
4535 | 0 | op <<= 10; |
4536 | 0 | Value |= op; |
4537 | | // op: vj |
4538 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4539 | 0 | op &= UINT64_C(31); |
4540 | 0 | op <<= 5; |
4541 | 0 | Value |= op; |
4542 | | // op: vd |
4543 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4544 | 0 | op &= UINT64_C(31); |
4545 | 0 | Value |= op; |
4546 | 0 | break; |
4547 | 0 | } |
4548 | 0 | case LoongArch::XVBITSELI_B: |
4549 | 0 | case LoongArch::XVEXTRINS_B: |
4550 | 0 | case LoongArch::XVEXTRINS_D: |
4551 | 0 | case LoongArch::XVEXTRINS_H: |
4552 | 0 | case LoongArch::XVEXTRINS_W: |
4553 | 0 | case LoongArch::XVPERMI_Q: |
4554 | 0 | case LoongArch::XVPERMI_W: |
4555 | 0 | case LoongArch::XVSHUF4I_D: { |
4556 | | // op: imm8 |
4557 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4558 | 0 | op &= UINT64_C(255); |
4559 | 0 | op <<= 10; |
4560 | 0 | Value |= op; |
4561 | | // op: xj |
4562 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4563 | 0 | op &= UINT64_C(31); |
4564 | 0 | op <<= 5; |
4565 | 0 | Value |= op; |
4566 | | // op: xd |
4567 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4568 | 0 | op &= UINT64_C(31); |
4569 | 0 | Value |= op; |
4570 | 0 | break; |
4571 | 0 | } |
4572 | 0 | case LoongArch::VLDREPL_D: { |
4573 | | // op: imm9 |
4574 | 0 | op = getImmOpValueAsr<3>(MI, 2, Fixups, STI); |
4575 | 0 | op &= UINT64_C(511); |
4576 | 0 | op <<= 10; |
4577 | 0 | Value |= op; |
4578 | | // op: rj |
4579 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4580 | 0 | op &= UINT64_C(31); |
4581 | 0 | op <<= 5; |
4582 | 0 | Value |= op; |
4583 | | // op: vd |
4584 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4585 | 0 | op &= UINT64_C(31); |
4586 | 0 | Value |= op; |
4587 | 0 | break; |
4588 | 0 | } |
4589 | 0 | case LoongArch::XVLDREPL_D: { |
4590 | | // op: imm9 |
4591 | 0 | op = getImmOpValueAsr<3>(MI, 2, Fixups, STI); |
4592 | 0 | op &= UINT64_C(511); |
4593 | 0 | op <<= 10; |
4594 | 0 | Value |= op; |
4595 | | // op: rj |
4596 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4597 | 0 | op &= UINT64_C(31); |
4598 | 0 | op <<= 5; |
4599 | 0 | Value |= op; |
4600 | | // op: xd |
4601 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4602 | 0 | op &= UINT64_C(31); |
4603 | 0 | Value |= op; |
4604 | 0 | break; |
4605 | 0 | } |
4606 | 0 | case LoongArch::BSTRPICK_D: { |
4607 | | // op: msbd |
4608 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4609 | 0 | op &= UINT64_C(63); |
4610 | 0 | op <<= 16; |
4611 | 0 | Value |= op; |
4612 | | // op: lsbd |
4613 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4614 | 0 | op &= UINT64_C(63); |
4615 | 0 | op <<= 10; |
4616 | 0 | Value |= op; |
4617 | | // op: rj |
4618 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4619 | 0 | op &= UINT64_C(31); |
4620 | 0 | op <<= 5; |
4621 | 0 | Value |= op; |
4622 | | // op: rd |
4623 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4624 | 0 | op &= UINT64_C(31); |
4625 | 0 | Value |= op; |
4626 | 0 | break; |
4627 | 0 | } |
4628 | 0 | case LoongArch::BSTRINS_D: { |
4629 | | // op: msbd |
4630 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4631 | 0 | op &= UINT64_C(63); |
4632 | 0 | op <<= 16; |
4633 | 0 | Value |= op; |
4634 | | // op: lsbd |
4635 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4636 | 0 | op &= UINT64_C(63); |
4637 | 0 | op <<= 10; |
4638 | 0 | Value |= op; |
4639 | | // op: rj |
4640 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4641 | 0 | op &= UINT64_C(31); |
4642 | 0 | op <<= 5; |
4643 | 0 | Value |= op; |
4644 | | // op: rd |
4645 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4646 | 0 | op &= UINT64_C(31); |
4647 | 0 | Value |= op; |
4648 | 0 | break; |
4649 | 0 | } |
4650 | 0 | case LoongArch::BSTRPICK_W: { |
4651 | | // op: msbw |
4652 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4653 | 0 | op &= UINT64_C(31); |
4654 | 0 | op <<= 16; |
4655 | 0 | Value |= op; |
4656 | | // op: lsbw |
4657 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4658 | 0 | op &= UINT64_C(31); |
4659 | 0 | op <<= 10; |
4660 | 0 | Value |= op; |
4661 | | // op: rj |
4662 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4663 | 0 | op &= UINT64_C(31); |
4664 | 0 | op <<= 5; |
4665 | 0 | Value |= op; |
4666 | | // op: rd |
4667 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4668 | 0 | op &= UINT64_C(31); |
4669 | 0 | Value |= op; |
4670 | 0 | break; |
4671 | 0 | } |
4672 | 0 | case LoongArch::BSTRINS_W: { |
4673 | | // op: msbw |
4674 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4675 | 0 | op &= UINT64_C(31); |
4676 | 0 | op <<= 16; |
4677 | 0 | Value |= op; |
4678 | | // op: lsbw |
4679 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4680 | 0 | op &= UINT64_C(31); |
4681 | 0 | op <<= 10; |
4682 | 0 | Value |= op; |
4683 | | // op: rj |
4684 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4685 | 0 | op &= UINT64_C(31); |
4686 | 0 | op <<= 5; |
4687 | 0 | Value |= op; |
4688 | | // op: rd |
4689 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4690 | 0 | op &= UINT64_C(31); |
4691 | 0 | Value |= op; |
4692 | 0 | break; |
4693 | 0 | } |
4694 | 0 | case LoongArch::X86MTTOP: { |
4695 | | // op: ptr |
4696 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4697 | 0 | op &= UINT64_C(7); |
4698 | 0 | op <<= 5; |
4699 | 0 | Value |= op; |
4700 | 0 | break; |
4701 | 0 | } |
4702 | 0 | case LoongArch::X86MFTOP: { |
4703 | | // op: rd |
4704 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4705 | 0 | op &= UINT64_C(31); |
4706 | 0 | Value |= op; |
4707 | 0 | break; |
4708 | 0 | } |
4709 | 0 | case LoongArch::X86DEC_B: |
4710 | 0 | case LoongArch::X86DEC_D: |
4711 | 0 | case LoongArch::X86DEC_H: |
4712 | 0 | case LoongArch::X86DEC_W: |
4713 | 0 | case LoongArch::X86INC_B: |
4714 | 0 | case LoongArch::X86INC_D: |
4715 | 0 | case LoongArch::X86INC_H: |
4716 | 0 | case LoongArch::X86INC_W: { |
4717 | | // op: rj |
4718 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4719 | 0 | op &= UINT64_C(31); |
4720 | 0 | op <<= 5; |
4721 | 0 | Value |= op; |
4722 | 0 | break; |
4723 | 0 | } |
4724 | 0 | case LoongArch::BITREV_4B: |
4725 | 0 | case LoongArch::BITREV_8B: |
4726 | 0 | case LoongArch::BITREV_D: |
4727 | 0 | case LoongArch::BITREV_W: |
4728 | 0 | case LoongArch::CLO_D: |
4729 | 0 | case LoongArch::CLO_W: |
4730 | 0 | case LoongArch::CLZ_D: |
4731 | 0 | case LoongArch::CLZ_W: |
4732 | 0 | case LoongArch::CPUCFG: |
4733 | 0 | case LoongArch::CTO_D: |
4734 | 0 | case LoongArch::CTO_W: |
4735 | 0 | case LoongArch::CTZ_D: |
4736 | 0 | case LoongArch::CTZ_W: |
4737 | 0 | case LoongArch::EXT_W_B: |
4738 | 0 | case LoongArch::EXT_W_H: |
4739 | 0 | case LoongArch::IOCSRRD_B: |
4740 | 0 | case LoongArch::IOCSRRD_D: |
4741 | 0 | case LoongArch::IOCSRRD_H: |
4742 | 0 | case LoongArch::IOCSRRD_W: |
4743 | 0 | case LoongArch::IOCSRWR_B: |
4744 | 0 | case LoongArch::IOCSRWR_D: |
4745 | 0 | case LoongArch::IOCSRWR_H: |
4746 | 0 | case LoongArch::IOCSRWR_W: |
4747 | 0 | case LoongArch::LLACQ_D: |
4748 | 0 | case LoongArch::LLACQ_W: |
4749 | 0 | case LoongArch::RDTIMEH_W: |
4750 | 0 | case LoongArch::RDTIMEL_W: |
4751 | 0 | case LoongArch::RDTIME_D: |
4752 | 0 | case LoongArch::REVB_2H: |
4753 | 0 | case LoongArch::REVB_2W: |
4754 | 0 | case LoongArch::REVB_4H: |
4755 | 0 | case LoongArch::REVB_D: |
4756 | 0 | case LoongArch::REVH_2W: |
4757 | 0 | case LoongArch::REVH_D: |
4758 | 0 | case LoongArch::SETX86LOOPE: |
4759 | 0 | case LoongArch::SETX86LOOPNE: { |
4760 | | // op: rj |
4761 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4762 | 0 | op &= UINT64_C(31); |
4763 | 0 | op <<= 5; |
4764 | 0 | Value |= op; |
4765 | | // op: rd |
4766 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4767 | 0 | op &= UINT64_C(31); |
4768 | 0 | Value |= op; |
4769 | 0 | break; |
4770 | 0 | } |
4771 | 0 | case LoongArch::MOVGR2SCR: { |
4772 | | // op: rj |
4773 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4774 | 0 | op &= UINT64_C(31); |
4775 | 0 | op <<= 5; |
4776 | 0 | Value |= op; |
4777 | | // op: sd |
4778 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4779 | 0 | op &= UINT64_C(3); |
4780 | 0 | Value |= op; |
4781 | 0 | break; |
4782 | 0 | } |
4783 | 0 | case LoongArch::VREPLGR2VR_B: |
4784 | 0 | case LoongArch::VREPLGR2VR_D: |
4785 | 0 | case LoongArch::VREPLGR2VR_H: |
4786 | 0 | case LoongArch::VREPLGR2VR_W: { |
4787 | | // op: rj |
4788 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4789 | 0 | op &= UINT64_C(31); |
4790 | 0 | op <<= 5; |
4791 | 0 | Value |= op; |
4792 | | // op: vd |
4793 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4794 | 0 | op &= UINT64_C(31); |
4795 | 0 | Value |= op; |
4796 | 0 | break; |
4797 | 0 | } |
4798 | 0 | case LoongArch::XVREPLGR2VR_B: |
4799 | 0 | case LoongArch::XVREPLGR2VR_D: |
4800 | 0 | case LoongArch::XVREPLGR2VR_H: |
4801 | 0 | case LoongArch::XVREPLGR2VR_W: { |
4802 | | // op: rj |
4803 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4804 | 0 | op &= UINT64_C(31); |
4805 | 0 | op <<= 5; |
4806 | 0 | Value |= op; |
4807 | | // op: xd |
4808 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4809 | 0 | op &= UINT64_C(31); |
4810 | 0 | Value |= op; |
4811 | 0 | break; |
4812 | 0 | } |
4813 | 0 | case LoongArch::SCREL_D: |
4814 | 0 | case LoongArch::SCREL_W: { |
4815 | | // op: rj |
4816 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4817 | 0 | op &= UINT64_C(31); |
4818 | 0 | op <<= 5; |
4819 | 0 | Value |= op; |
4820 | | // op: rd |
4821 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4822 | 0 | op &= UINT64_C(31); |
4823 | 0 | Value |= op; |
4824 | 0 | break; |
4825 | 0 | } |
4826 | 0 | case LoongArch::INVTLB: { |
4827 | | // op: rk |
4828 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4829 | 0 | op &= UINT64_C(31); |
4830 | 0 | op <<= 10; |
4831 | 0 | Value |= op; |
4832 | | // op: rj |
4833 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4834 | 0 | op &= UINT64_C(31); |
4835 | 0 | op <<= 5; |
4836 | 0 | Value |= op; |
4837 | | // op: op |
4838 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4839 | 0 | op &= UINT64_C(31); |
4840 | 0 | Value |= op; |
4841 | 0 | break; |
4842 | 0 | } |
4843 | 0 | case LoongArch::ASRTGT_D: |
4844 | 0 | case LoongArch::ASRTLE_D: |
4845 | 0 | case LoongArch::X86ADC_B: |
4846 | 0 | case LoongArch::X86ADC_D: |
4847 | 0 | case LoongArch::X86ADC_H: |
4848 | 0 | case LoongArch::X86ADC_W: |
4849 | 0 | case LoongArch::X86ADD_B: |
4850 | 0 | case LoongArch::X86ADD_D: |
4851 | 0 | case LoongArch::X86ADD_DU: |
4852 | 0 | case LoongArch::X86ADD_H: |
4853 | 0 | case LoongArch::X86ADD_W: |
4854 | 0 | case LoongArch::X86ADD_WU: |
4855 | 0 | case LoongArch::X86AND_B: |
4856 | 0 | case LoongArch::X86AND_D: |
4857 | 0 | case LoongArch::X86AND_H: |
4858 | 0 | case LoongArch::X86AND_W: |
4859 | 0 | case LoongArch::X86MUL_B: |
4860 | 0 | case LoongArch::X86MUL_BU: |
4861 | 0 | case LoongArch::X86MUL_D: |
4862 | 0 | case LoongArch::X86MUL_DU: |
4863 | 0 | case LoongArch::X86MUL_H: |
4864 | 0 | case LoongArch::X86MUL_HU: |
4865 | 0 | case LoongArch::X86MUL_W: |
4866 | 0 | case LoongArch::X86MUL_WU: |
4867 | 0 | case LoongArch::X86OR_B: |
4868 | 0 | case LoongArch::X86OR_D: |
4869 | 0 | case LoongArch::X86OR_H: |
4870 | 0 | case LoongArch::X86OR_W: |
4871 | 0 | case LoongArch::X86RCL_B: |
4872 | 0 | case LoongArch::X86RCL_D: |
4873 | 0 | case LoongArch::X86RCL_H: |
4874 | 0 | case LoongArch::X86RCL_W: |
4875 | 0 | case LoongArch::X86RCR_B: |
4876 | 0 | case LoongArch::X86RCR_D: |
4877 | 0 | case LoongArch::X86RCR_H: |
4878 | 0 | case LoongArch::X86RCR_W: |
4879 | 0 | case LoongArch::X86ROTL_B: |
4880 | 0 | case LoongArch::X86ROTL_D: |
4881 | 0 | case LoongArch::X86ROTL_H: |
4882 | 0 | case LoongArch::X86ROTL_W: |
4883 | 0 | case LoongArch::X86ROTR_B: |
4884 | 0 | case LoongArch::X86ROTR_D: |
4885 | 0 | case LoongArch::X86ROTR_H: |
4886 | 0 | case LoongArch::X86ROTR_W: |
4887 | 0 | case LoongArch::X86SBC_B: |
4888 | 0 | case LoongArch::X86SBC_D: |
4889 | 0 | case LoongArch::X86SBC_H: |
4890 | 0 | case LoongArch::X86SBC_W: |
4891 | 0 | case LoongArch::X86SLL_B: |
4892 | 0 | case LoongArch::X86SLL_D: |
4893 | 0 | case LoongArch::X86SLL_H: |
4894 | 0 | case LoongArch::X86SLL_W: |
4895 | 0 | case LoongArch::X86SRA_B: |
4896 | 0 | case LoongArch::X86SRA_D: |
4897 | 0 | case LoongArch::X86SRA_H: |
4898 | 0 | case LoongArch::X86SRA_W: |
4899 | 0 | case LoongArch::X86SRL_B: |
4900 | 0 | case LoongArch::X86SRL_D: |
4901 | 0 | case LoongArch::X86SRL_H: |
4902 | 0 | case LoongArch::X86SRL_W: |
4903 | 0 | case LoongArch::X86SUB_B: |
4904 | 0 | case LoongArch::X86SUB_D: |
4905 | 0 | case LoongArch::X86SUB_DU: |
4906 | 0 | case LoongArch::X86SUB_H: |
4907 | 0 | case LoongArch::X86SUB_W: |
4908 | 0 | case LoongArch::X86SUB_WU: |
4909 | 0 | case LoongArch::X86XOR_B: |
4910 | 0 | case LoongArch::X86XOR_D: |
4911 | 0 | case LoongArch::X86XOR_H: |
4912 | 0 | case LoongArch::X86XOR_W: { |
4913 | | // op: rk |
4914 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4915 | 0 | op &= UINT64_C(31); |
4916 | 0 | op <<= 10; |
4917 | 0 | Value |= op; |
4918 | | // op: rj |
4919 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4920 | 0 | op &= UINT64_C(31); |
4921 | 0 | op <<= 5; |
4922 | 0 | Value |= op; |
4923 | 0 | break; |
4924 | 0 | } |
4925 | 0 | case LoongArch::AMADD_B: |
4926 | 0 | case LoongArch::AMADD_D: |
4927 | 0 | case LoongArch::AMADD_H: |
4928 | 0 | case LoongArch::AMADD_W: |
4929 | 0 | case LoongArch::AMADD__DB_B: |
4930 | 0 | case LoongArch::AMADD__DB_D: |
4931 | 0 | case LoongArch::AMADD__DB_H: |
4932 | 0 | case LoongArch::AMADD__DB_W: |
4933 | 0 | case LoongArch::AMAND_D: |
4934 | 0 | case LoongArch::AMAND_W: |
4935 | 0 | case LoongArch::AMAND__DB_D: |
4936 | 0 | case LoongArch::AMAND__DB_W: |
4937 | 0 | case LoongArch::AMCAS_B: |
4938 | 0 | case LoongArch::AMCAS_D: |
4939 | 0 | case LoongArch::AMCAS_H: |
4940 | 0 | case LoongArch::AMCAS_W: |
4941 | 0 | case LoongArch::AMCAS__DB_B: |
4942 | 0 | case LoongArch::AMCAS__DB_D: |
4943 | 0 | case LoongArch::AMCAS__DB_H: |
4944 | 0 | case LoongArch::AMCAS__DB_W: |
4945 | 0 | case LoongArch::AMMAX_D: |
4946 | 0 | case LoongArch::AMMAX_DU: |
4947 | 0 | case LoongArch::AMMAX_W: |
4948 | 0 | case LoongArch::AMMAX_WU: |
4949 | 0 | case LoongArch::AMMAX__DB_D: |
4950 | 0 | case LoongArch::AMMAX__DB_DU: |
4951 | 0 | case LoongArch::AMMAX__DB_W: |
4952 | 0 | case LoongArch::AMMAX__DB_WU: |
4953 | 0 | case LoongArch::AMMIN_D: |
4954 | 0 | case LoongArch::AMMIN_DU: |
4955 | 0 | case LoongArch::AMMIN_W: |
4956 | 0 | case LoongArch::AMMIN_WU: |
4957 | 0 | case LoongArch::AMMIN__DB_D: |
4958 | 0 | case LoongArch::AMMIN__DB_DU: |
4959 | 0 | case LoongArch::AMMIN__DB_W: |
4960 | 0 | case LoongArch::AMMIN__DB_WU: |
4961 | 0 | case LoongArch::AMOR_D: |
4962 | 0 | case LoongArch::AMOR_W: |
4963 | 0 | case LoongArch::AMOR__DB_D: |
4964 | 0 | case LoongArch::AMOR__DB_W: |
4965 | 0 | case LoongArch::AMSWAP_B: |
4966 | 0 | case LoongArch::AMSWAP_D: |
4967 | 0 | case LoongArch::AMSWAP_H: |
4968 | 0 | case LoongArch::AMSWAP_W: |
4969 | 0 | case LoongArch::AMSWAP__DB_B: |
4970 | 0 | case LoongArch::AMSWAP__DB_D: |
4971 | 0 | case LoongArch::AMSWAP__DB_H: |
4972 | 0 | case LoongArch::AMSWAP__DB_W: |
4973 | 0 | case LoongArch::AMXOR_D: |
4974 | 0 | case LoongArch::AMXOR_W: |
4975 | 0 | case LoongArch::AMXOR__DB_D: |
4976 | 0 | case LoongArch::AMXOR__DB_W: { |
4977 | | // op: rk |
4978 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4979 | 0 | op &= UINT64_C(31); |
4980 | 0 | op <<= 10; |
4981 | 0 | Value |= op; |
4982 | | // op: rj |
4983 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4984 | 0 | op &= UINT64_C(31); |
4985 | 0 | op <<= 5; |
4986 | 0 | Value |= op; |
4987 | | // op: rd |
4988 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4989 | 0 | op &= UINT64_C(31); |
4990 | 0 | Value |= op; |
4991 | 0 | break; |
4992 | 0 | } |
4993 | 0 | case LoongArch::FLDGT_D: |
4994 | 0 | case LoongArch::FLDGT_S: |
4995 | 0 | case LoongArch::FLDLE_D: |
4996 | 0 | case LoongArch::FLDLE_S: |
4997 | 0 | case LoongArch::FLDX_D: |
4998 | 0 | case LoongArch::FLDX_S: |
4999 | 0 | case LoongArch::FSTGT_D: |
5000 | 0 | case LoongArch::FSTGT_S: |
5001 | 0 | case LoongArch::FSTLE_D: |
5002 | 0 | case LoongArch::FSTLE_S: |
5003 | 0 | case LoongArch::FSTX_D: |
5004 | 0 | case LoongArch::FSTX_S: { |
5005 | | // op: rk |
5006 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5007 | 0 | op &= UINT64_C(31); |
5008 | 0 | op <<= 10; |
5009 | 0 | Value |= op; |
5010 | | // op: rj |
5011 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5012 | 0 | op &= UINT64_C(31); |
5013 | 0 | op <<= 5; |
5014 | 0 | Value |= op; |
5015 | | // op: fd |
5016 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5017 | 0 | op &= UINT64_C(31); |
5018 | 0 | Value |= op; |
5019 | 0 | break; |
5020 | 0 | } |
5021 | 0 | case LoongArch::PRELDX: { |
5022 | | // op: rk |
5023 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5024 | 0 | op &= UINT64_C(31); |
5025 | 0 | op <<= 10; |
5026 | 0 | Value |= op; |
5027 | | // op: rj |
5028 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5029 | 0 | op &= UINT64_C(31); |
5030 | 0 | op <<= 5; |
5031 | 0 | Value |= op; |
5032 | | // op: imm5 |
5033 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5034 | 0 | op &= UINT64_C(31); |
5035 | 0 | Value |= op; |
5036 | 0 | break; |
5037 | 0 | } |
5038 | 0 | case LoongArch::ADC_B: |
5039 | 0 | case LoongArch::ADC_D: |
5040 | 0 | case LoongArch::ADC_H: |
5041 | 0 | case LoongArch::ADC_W: |
5042 | 0 | case LoongArch::ADD_D: |
5043 | 0 | case LoongArch::ADD_W: |
5044 | 0 | case LoongArch::AND: |
5045 | 0 | case LoongArch::ANDN: |
5046 | 0 | case LoongArch::CRCC_W_B_W: |
5047 | 0 | case LoongArch::CRCC_W_D_W: |
5048 | 0 | case LoongArch::CRCC_W_H_W: |
5049 | 0 | case LoongArch::CRCC_W_W_W: |
5050 | 0 | case LoongArch::CRC_W_B_W: |
5051 | 0 | case LoongArch::CRC_W_D_W: |
5052 | 0 | case LoongArch::CRC_W_H_W: |
5053 | 0 | case LoongArch::CRC_W_W_W: |
5054 | 0 | case LoongArch::DIV_D: |
5055 | 0 | case LoongArch::DIV_DU: |
5056 | 0 | case LoongArch::DIV_W: |
5057 | 0 | case LoongArch::DIV_WU: |
5058 | 0 | case LoongArch::LDGT_B: |
5059 | 0 | case LoongArch::LDGT_D: |
5060 | 0 | case LoongArch::LDGT_H: |
5061 | 0 | case LoongArch::LDGT_W: |
5062 | 0 | case LoongArch::LDLE_B: |
5063 | 0 | case LoongArch::LDLE_D: |
5064 | 0 | case LoongArch::LDLE_H: |
5065 | 0 | case LoongArch::LDLE_W: |
5066 | 0 | case LoongArch::LDX_B: |
5067 | 0 | case LoongArch::LDX_BU: |
5068 | 0 | case LoongArch::LDX_D: |
5069 | 0 | case LoongArch::LDX_H: |
5070 | 0 | case LoongArch::LDX_HU: |
5071 | 0 | case LoongArch::LDX_W: |
5072 | 0 | case LoongArch::LDX_WU: |
5073 | 0 | case LoongArch::MASKEQZ: |
5074 | 0 | case LoongArch::MASKNEZ: |
5075 | 0 | case LoongArch::MOD_D: |
5076 | 0 | case LoongArch::MOD_DU: |
5077 | 0 | case LoongArch::MOD_W: |
5078 | 0 | case LoongArch::MOD_WU: |
5079 | 0 | case LoongArch::MULH_D: |
5080 | 0 | case LoongArch::MULH_DU: |
5081 | 0 | case LoongArch::MULH_W: |
5082 | 0 | case LoongArch::MULH_WU: |
5083 | 0 | case LoongArch::MULW_D_W: |
5084 | 0 | case LoongArch::MULW_D_WU: |
5085 | 0 | case LoongArch::MUL_D: |
5086 | 0 | case LoongArch::MUL_W: |
5087 | 0 | case LoongArch::NOR: |
5088 | 0 | case LoongArch::OR: |
5089 | 0 | case LoongArch::ORN: |
5090 | 0 | case LoongArch::RCR_B: |
5091 | 0 | case LoongArch::RCR_D: |
5092 | 0 | case LoongArch::RCR_H: |
5093 | 0 | case LoongArch::RCR_W: |
5094 | 0 | case LoongArch::ROTR_B: |
5095 | 0 | case LoongArch::ROTR_D: |
5096 | 0 | case LoongArch::ROTR_H: |
5097 | 0 | case LoongArch::ROTR_W: |
5098 | 0 | case LoongArch::SBC_B: |
5099 | 0 | case LoongArch::SBC_D: |
5100 | 0 | case LoongArch::SBC_H: |
5101 | 0 | case LoongArch::SBC_W: |
5102 | 0 | case LoongArch::SLL_D: |
5103 | 0 | case LoongArch::SLL_W: |
5104 | 0 | case LoongArch::SLT: |
5105 | 0 | case LoongArch::SLTU: |
5106 | 0 | case LoongArch::SRA_D: |
5107 | 0 | case LoongArch::SRA_W: |
5108 | 0 | case LoongArch::SRL_D: |
5109 | 0 | case LoongArch::SRL_W: |
5110 | 0 | case LoongArch::STGT_B: |
5111 | 0 | case LoongArch::STGT_D: |
5112 | 0 | case LoongArch::STGT_H: |
5113 | 0 | case LoongArch::STGT_W: |
5114 | 0 | case LoongArch::STLE_B: |
5115 | 0 | case LoongArch::STLE_D: |
5116 | 0 | case LoongArch::STLE_H: |
5117 | 0 | case LoongArch::STLE_W: |
5118 | 0 | case LoongArch::STX_B: |
5119 | 0 | case LoongArch::STX_D: |
5120 | 0 | case LoongArch::STX_H: |
5121 | 0 | case LoongArch::STX_W: |
5122 | 0 | case LoongArch::SUB_D: |
5123 | 0 | case LoongArch::SUB_W: |
5124 | 0 | case LoongArch::XOR: { |
5125 | | // op: rk |
5126 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5127 | 0 | op &= UINT64_C(31); |
5128 | 0 | op <<= 10; |
5129 | 0 | Value |= op; |
5130 | | // op: rj |
5131 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5132 | 0 | op &= UINT64_C(31); |
5133 | 0 | op <<= 5; |
5134 | 0 | Value |= op; |
5135 | | // op: rd |
5136 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5137 | 0 | op &= UINT64_C(31); |
5138 | 0 | Value |= op; |
5139 | 0 | break; |
5140 | 0 | } |
5141 | 0 | case LoongArch::VLDX: |
5142 | 0 | case LoongArch::VSTX: { |
5143 | | // op: rk |
5144 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5145 | 0 | op &= UINT64_C(31); |
5146 | 0 | op <<= 10; |
5147 | 0 | Value |= op; |
5148 | | // op: rj |
5149 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5150 | 0 | op &= UINT64_C(31); |
5151 | 0 | op <<= 5; |
5152 | 0 | Value |= op; |
5153 | | // op: vd |
5154 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5155 | 0 | op &= UINT64_C(31); |
5156 | 0 | Value |= op; |
5157 | 0 | break; |
5158 | 0 | } |
5159 | 0 | case LoongArch::XVLDX: |
5160 | 0 | case LoongArch::XVSTX: { |
5161 | | // op: rk |
5162 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5163 | 0 | op &= UINT64_C(31); |
5164 | 0 | op <<= 10; |
5165 | 0 | Value |= op; |
5166 | | // op: rj |
5167 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5168 | 0 | op &= UINT64_C(31); |
5169 | 0 | op <<= 5; |
5170 | 0 | Value |= op; |
5171 | | // op: xd |
5172 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5173 | 0 | op &= UINT64_C(31); |
5174 | 0 | Value |= op; |
5175 | 0 | break; |
5176 | 0 | } |
5177 | 0 | case LoongArch::SC_Q: { |
5178 | | // op: rk |
5179 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5180 | 0 | op &= UINT64_C(31); |
5181 | 0 | op <<= 10; |
5182 | 0 | Value |= op; |
5183 | | // op: rj |
5184 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5185 | 0 | op &= UINT64_C(31); |
5186 | 0 | op <<= 5; |
5187 | 0 | Value |= op; |
5188 | | // op: rd |
5189 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5190 | 0 | op &= UINT64_C(31); |
5191 | 0 | Value |= op; |
5192 | 0 | break; |
5193 | 0 | } |
5194 | 0 | case LoongArch::VREPLVE_B: |
5195 | 0 | case LoongArch::VREPLVE_D: |
5196 | 0 | case LoongArch::VREPLVE_H: |
5197 | 0 | case LoongArch::VREPLVE_W: { |
5198 | | // op: rk |
5199 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5200 | 0 | op &= UINT64_C(31); |
5201 | 0 | op <<= 10; |
5202 | 0 | Value |= op; |
5203 | | // op: vj |
5204 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5205 | 0 | op &= UINT64_C(31); |
5206 | 0 | op <<= 5; |
5207 | 0 | Value |= op; |
5208 | | // op: vd |
5209 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5210 | 0 | op &= UINT64_C(31); |
5211 | 0 | Value |= op; |
5212 | 0 | break; |
5213 | 0 | } |
5214 | 0 | case LoongArch::XVREPLVE_B: |
5215 | 0 | case LoongArch::XVREPLVE_D: |
5216 | 0 | case LoongArch::XVREPLVE_H: |
5217 | 0 | case LoongArch::XVREPLVE_W: { |
5218 | | // op: rk |
5219 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5220 | 0 | op &= UINT64_C(31); |
5221 | 0 | op <<= 10; |
5222 | 0 | Value |= op; |
5223 | | // op: xj |
5224 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5225 | 0 | op &= UINT64_C(31); |
5226 | 0 | op <<= 5; |
5227 | 0 | Value |= op; |
5228 | | // op: xd |
5229 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5230 | 0 | op &= UINT64_C(31); |
5231 | 0 | Value |= op; |
5232 | 0 | break; |
5233 | 0 | } |
5234 | 0 | case LoongArch::LDPTE: { |
5235 | | // op: seq |
5236 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5237 | 0 | op &= UINT64_C(255); |
5238 | 0 | op <<= 10; |
5239 | 0 | Value |= op; |
5240 | | // op: rj |
5241 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5242 | 0 | op &= UINT64_C(31); |
5243 | 0 | op <<= 5; |
5244 | 0 | Value |= op; |
5245 | 0 | break; |
5246 | 0 | } |
5247 | 0 | case LoongArch::MOVSCR2GR: { |
5248 | | // op: sj |
5249 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5250 | 0 | op &= UINT64_C(3); |
5251 | 0 | op <<= 5; |
5252 | 0 | Value |= op; |
5253 | | // op: rd |
5254 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5255 | 0 | op &= UINT64_C(31); |
5256 | 0 | Value |= op; |
5257 | 0 | break; |
5258 | 0 | } |
5259 | 0 | case LoongArch::FMOV_D: |
5260 | 0 | case LoongArch::FMOV_S: |
5261 | 0 | case LoongArch::MOVCF2FR_xS: |
5262 | 0 | case LoongArch::MOVCF2GR: |
5263 | 0 | case LoongArch::MOVFCSR2GR: |
5264 | 0 | case LoongArch::MOVFR2CF_xS: |
5265 | 0 | case LoongArch::MOVFR2GR_D: |
5266 | 0 | case LoongArch::MOVFR2GR_S: |
5267 | 0 | case LoongArch::MOVFR2GR_S_64: |
5268 | 0 | case LoongArch::MOVFRH2GR_S: |
5269 | 0 | case LoongArch::MOVGR2CF: |
5270 | 0 | case LoongArch::MOVGR2FCSR: |
5271 | 0 | case LoongArch::MOVGR2FR_D: |
5272 | 0 | case LoongArch::MOVGR2FR_W: |
5273 | 0 | case LoongArch::MOVGR2FR_W_64: { |
5274 | | // op: src |
5275 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5276 | 0 | op &= UINT64_C(31); |
5277 | 0 | op <<= 5; |
5278 | 0 | Value |= op; |
5279 | | // op: dst |
5280 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5281 | 0 | op &= UINT64_C(31); |
5282 | 0 | Value |= op; |
5283 | 0 | break; |
5284 | 0 | } |
5285 | 0 | case LoongArch::MOVGR2FRH_W: { |
5286 | | // op: src |
5287 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5288 | 0 | op &= UINT64_C(31); |
5289 | 0 | op <<= 5; |
5290 | 0 | Value |= op; |
5291 | | // op: dst |
5292 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5293 | 0 | op &= UINT64_C(31); |
5294 | 0 | Value |= op; |
5295 | 0 | break; |
5296 | 0 | } |
5297 | 0 | case LoongArch::VBITSEL_V: |
5298 | 0 | case LoongArch::VFMADD_D: |
5299 | 0 | case LoongArch::VFMADD_S: |
5300 | 0 | case LoongArch::VFMSUB_D: |
5301 | 0 | case LoongArch::VFMSUB_S: |
5302 | 0 | case LoongArch::VFNMADD_D: |
5303 | 0 | case LoongArch::VFNMADD_S: |
5304 | 0 | case LoongArch::VFNMSUB_D: |
5305 | 0 | case LoongArch::VFNMSUB_S: |
5306 | 0 | case LoongArch::VSHUF_B: { |
5307 | | // op: va |
5308 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5309 | 0 | op &= UINT64_C(31); |
5310 | 0 | op <<= 15; |
5311 | 0 | Value |= op; |
5312 | | // op: vk |
5313 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5314 | 0 | op &= UINT64_C(31); |
5315 | 0 | op <<= 10; |
5316 | 0 | Value |= op; |
5317 | | // op: vj |
5318 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5319 | 0 | op &= UINT64_C(31); |
5320 | 0 | op <<= 5; |
5321 | 0 | Value |= op; |
5322 | | // op: vd |
5323 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5324 | 0 | op &= UINT64_C(31); |
5325 | 0 | Value |= op; |
5326 | 0 | break; |
5327 | 0 | } |
5328 | 0 | case LoongArch::VSETALLNEZ_B: |
5329 | 0 | case LoongArch::VSETALLNEZ_D: |
5330 | 0 | case LoongArch::VSETALLNEZ_H: |
5331 | 0 | case LoongArch::VSETALLNEZ_W: |
5332 | 0 | case LoongArch::VSETANYEQZ_B: |
5333 | 0 | case LoongArch::VSETANYEQZ_D: |
5334 | 0 | case LoongArch::VSETANYEQZ_H: |
5335 | 0 | case LoongArch::VSETANYEQZ_W: |
5336 | 0 | case LoongArch::VSETEQZ_V: |
5337 | 0 | case LoongArch::VSETNEZ_V: { |
5338 | | // op: vj |
5339 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5340 | 0 | op &= UINT64_C(31); |
5341 | 0 | op <<= 5; |
5342 | 0 | Value |= op; |
5343 | | // op: cd |
5344 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5345 | 0 | op &= UINT64_C(7); |
5346 | 0 | Value |= op; |
5347 | 0 | break; |
5348 | 0 | } |
5349 | 0 | case LoongArch::VCLO_B: |
5350 | 0 | case LoongArch::VCLO_D: |
5351 | 0 | case LoongArch::VCLO_H: |
5352 | 0 | case LoongArch::VCLO_W: |
5353 | 0 | case LoongArch::VCLZ_B: |
5354 | 0 | case LoongArch::VCLZ_D: |
5355 | 0 | case LoongArch::VCLZ_H: |
5356 | 0 | case LoongArch::VCLZ_W: |
5357 | 0 | case LoongArch::VEXTH_DU_WU: |
5358 | 0 | case LoongArch::VEXTH_D_W: |
5359 | 0 | case LoongArch::VEXTH_HU_BU: |
5360 | 0 | case LoongArch::VEXTH_H_B: |
5361 | 0 | case LoongArch::VEXTH_QU_DU: |
5362 | 0 | case LoongArch::VEXTH_Q_D: |
5363 | 0 | case LoongArch::VEXTH_WU_HU: |
5364 | 0 | case LoongArch::VEXTH_W_H: |
5365 | 0 | case LoongArch::VEXTL_QU_DU: |
5366 | 0 | case LoongArch::VEXTL_Q_D: |
5367 | 0 | case LoongArch::VFCLASS_D: |
5368 | 0 | case LoongArch::VFCLASS_S: |
5369 | 0 | case LoongArch::VFCVTH_D_S: |
5370 | 0 | case LoongArch::VFCVTH_S_H: |
5371 | 0 | case LoongArch::VFCVTL_D_S: |
5372 | 0 | case LoongArch::VFCVTL_S_H: |
5373 | 0 | case LoongArch::VFFINTH_D_W: |
5374 | 0 | case LoongArch::VFFINTL_D_W: |
5375 | 0 | case LoongArch::VFFINT_D_L: |
5376 | 0 | case LoongArch::VFFINT_D_LU: |
5377 | 0 | case LoongArch::VFFINT_S_W: |
5378 | 0 | case LoongArch::VFFINT_S_WU: |
5379 | 0 | case LoongArch::VFLOGB_D: |
5380 | 0 | case LoongArch::VFLOGB_S: |
5381 | 0 | case LoongArch::VFRECIPE_D: |
5382 | 0 | case LoongArch::VFRECIPE_S: |
5383 | 0 | case LoongArch::VFRECIP_D: |
5384 | 0 | case LoongArch::VFRECIP_S: |
5385 | 0 | case LoongArch::VFRINTRM_D: |
5386 | 0 | case LoongArch::VFRINTRM_S: |
5387 | 0 | case LoongArch::VFRINTRNE_D: |
5388 | 0 | case LoongArch::VFRINTRNE_S: |
5389 | 0 | case LoongArch::VFRINTRP_D: |
5390 | 0 | case LoongArch::VFRINTRP_S: |
5391 | 0 | case LoongArch::VFRINTRZ_D: |
5392 | 0 | case LoongArch::VFRINTRZ_S: |
5393 | 0 | case LoongArch::VFRINT_D: |
5394 | 0 | case LoongArch::VFRINT_S: |
5395 | 0 | case LoongArch::VFRSQRTE_D: |
5396 | 0 | case LoongArch::VFRSQRTE_S: |
5397 | 0 | case LoongArch::VFRSQRT_D: |
5398 | 0 | case LoongArch::VFRSQRT_S: |
5399 | 0 | case LoongArch::VFSQRT_D: |
5400 | 0 | case LoongArch::VFSQRT_S: |
5401 | 0 | case LoongArch::VFTINTH_L_S: |
5402 | 0 | case LoongArch::VFTINTL_L_S: |
5403 | 0 | case LoongArch::VFTINTRMH_L_S: |
5404 | 0 | case LoongArch::VFTINTRML_L_S: |
5405 | 0 | case LoongArch::VFTINTRM_L_D: |
5406 | 0 | case LoongArch::VFTINTRM_W_S: |
5407 | 0 | case LoongArch::VFTINTRNEH_L_S: |
5408 | 0 | case LoongArch::VFTINTRNEL_L_S: |
5409 | 0 | case LoongArch::VFTINTRNE_L_D: |
5410 | 0 | case LoongArch::VFTINTRNE_W_S: |
5411 | 0 | case LoongArch::VFTINTRPH_L_S: |
5412 | 0 | case LoongArch::VFTINTRPL_L_S: |
5413 | 0 | case LoongArch::VFTINTRP_L_D: |
5414 | 0 | case LoongArch::VFTINTRP_W_S: |
5415 | 0 | case LoongArch::VFTINTRZH_L_S: |
5416 | 0 | case LoongArch::VFTINTRZL_L_S: |
5417 | 0 | case LoongArch::VFTINTRZ_LU_D: |
5418 | 0 | case LoongArch::VFTINTRZ_L_D: |
5419 | 0 | case LoongArch::VFTINTRZ_WU_S: |
5420 | 0 | case LoongArch::VFTINTRZ_W_S: |
5421 | 0 | case LoongArch::VFTINT_LU_D: |
5422 | 0 | case LoongArch::VFTINT_L_D: |
5423 | 0 | case LoongArch::VFTINT_WU_S: |
5424 | 0 | case LoongArch::VFTINT_W_S: |
5425 | 0 | case LoongArch::VMSKGEZ_B: |
5426 | 0 | case LoongArch::VMSKLTZ_B: |
5427 | 0 | case LoongArch::VMSKLTZ_D: |
5428 | 0 | case LoongArch::VMSKLTZ_H: |
5429 | 0 | case LoongArch::VMSKLTZ_W: |
5430 | 0 | case LoongArch::VMSKNZ_B: |
5431 | 0 | case LoongArch::VNEG_B: |
5432 | 0 | case LoongArch::VNEG_D: |
5433 | 0 | case LoongArch::VNEG_H: |
5434 | 0 | case LoongArch::VNEG_W: |
5435 | 0 | case LoongArch::VPCNT_B: |
5436 | 0 | case LoongArch::VPCNT_D: |
5437 | 0 | case LoongArch::VPCNT_H: |
5438 | 0 | case LoongArch::VPCNT_W: { |
5439 | | // op: vj |
5440 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5441 | 0 | op &= UINT64_C(31); |
5442 | 0 | op <<= 5; |
5443 | 0 | Value |= op; |
5444 | | // op: vd |
5445 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5446 | 0 | op &= UINT64_C(31); |
5447 | 0 | Value |= op; |
5448 | 0 | break; |
5449 | 0 | } |
5450 | 0 | case LoongArch::VABSD_B: |
5451 | 0 | case LoongArch::VABSD_BU: |
5452 | 0 | case LoongArch::VABSD_D: |
5453 | 0 | case LoongArch::VABSD_DU: |
5454 | 0 | case LoongArch::VABSD_H: |
5455 | 0 | case LoongArch::VABSD_HU: |
5456 | 0 | case LoongArch::VABSD_W: |
5457 | 0 | case LoongArch::VABSD_WU: |
5458 | 0 | case LoongArch::VADDA_B: |
5459 | 0 | case LoongArch::VADDA_D: |
5460 | 0 | case LoongArch::VADDA_H: |
5461 | 0 | case LoongArch::VADDA_W: |
5462 | 0 | case LoongArch::VADDWEV_D_W: |
5463 | 0 | case LoongArch::VADDWEV_D_WU: |
5464 | 0 | case LoongArch::VADDWEV_D_WU_W: |
5465 | 0 | case LoongArch::VADDWEV_H_B: |
5466 | 0 | case LoongArch::VADDWEV_H_BU: |
5467 | 0 | case LoongArch::VADDWEV_H_BU_B: |
5468 | 0 | case LoongArch::VADDWEV_Q_D: |
5469 | 0 | case LoongArch::VADDWEV_Q_DU: |
5470 | 0 | case LoongArch::VADDWEV_Q_DU_D: |
5471 | 0 | case LoongArch::VADDWEV_W_H: |
5472 | 0 | case LoongArch::VADDWEV_W_HU: |
5473 | 0 | case LoongArch::VADDWEV_W_HU_H: |
5474 | 0 | case LoongArch::VADDWOD_D_W: |
5475 | 0 | case LoongArch::VADDWOD_D_WU: |
5476 | 0 | case LoongArch::VADDWOD_D_WU_W: |
5477 | 0 | case LoongArch::VADDWOD_H_B: |
5478 | 0 | case LoongArch::VADDWOD_H_BU: |
5479 | 0 | case LoongArch::VADDWOD_H_BU_B: |
5480 | 0 | case LoongArch::VADDWOD_Q_D: |
5481 | 0 | case LoongArch::VADDWOD_Q_DU: |
5482 | 0 | case LoongArch::VADDWOD_Q_DU_D: |
5483 | 0 | case LoongArch::VADDWOD_W_H: |
5484 | 0 | case LoongArch::VADDWOD_W_HU: |
5485 | 0 | case LoongArch::VADDWOD_W_HU_H: |
5486 | 0 | case LoongArch::VADD_B: |
5487 | 0 | case LoongArch::VADD_D: |
5488 | 0 | case LoongArch::VADD_H: |
5489 | 0 | case LoongArch::VADD_Q: |
5490 | 0 | case LoongArch::VADD_W: |
5491 | 0 | case LoongArch::VANDN_V: |
5492 | 0 | case LoongArch::VAND_V: |
5493 | 0 | case LoongArch::VAVGR_B: |
5494 | 0 | case LoongArch::VAVGR_BU: |
5495 | 0 | case LoongArch::VAVGR_D: |
5496 | 0 | case LoongArch::VAVGR_DU: |
5497 | 0 | case LoongArch::VAVGR_H: |
5498 | 0 | case LoongArch::VAVGR_HU: |
5499 | 0 | case LoongArch::VAVGR_W: |
5500 | 0 | case LoongArch::VAVGR_WU: |
5501 | 0 | case LoongArch::VAVG_B: |
5502 | 0 | case LoongArch::VAVG_BU: |
5503 | 0 | case LoongArch::VAVG_D: |
5504 | 0 | case LoongArch::VAVG_DU: |
5505 | 0 | case LoongArch::VAVG_H: |
5506 | 0 | case LoongArch::VAVG_HU: |
5507 | 0 | case LoongArch::VAVG_W: |
5508 | 0 | case LoongArch::VAVG_WU: |
5509 | 0 | case LoongArch::VBITCLR_B: |
5510 | 0 | case LoongArch::VBITCLR_D: |
5511 | 0 | case LoongArch::VBITCLR_H: |
5512 | 0 | case LoongArch::VBITCLR_W: |
5513 | 0 | case LoongArch::VBITREV_B: |
5514 | 0 | case LoongArch::VBITREV_D: |
5515 | 0 | case LoongArch::VBITREV_H: |
5516 | 0 | case LoongArch::VBITREV_W: |
5517 | 0 | case LoongArch::VBITSET_B: |
5518 | 0 | case LoongArch::VBITSET_D: |
5519 | 0 | case LoongArch::VBITSET_H: |
5520 | 0 | case LoongArch::VBITSET_W: |
5521 | 0 | case LoongArch::VDIV_B: |
5522 | 0 | case LoongArch::VDIV_BU: |
5523 | 0 | case LoongArch::VDIV_D: |
5524 | 0 | case LoongArch::VDIV_DU: |
5525 | 0 | case LoongArch::VDIV_H: |
5526 | 0 | case LoongArch::VDIV_HU: |
5527 | 0 | case LoongArch::VDIV_W: |
5528 | 0 | case LoongArch::VDIV_WU: |
5529 | 0 | case LoongArch::VFADD_D: |
5530 | 0 | case LoongArch::VFADD_S: |
5531 | 0 | case LoongArch::VFCMP_CAF_D: |
5532 | 0 | case LoongArch::VFCMP_CAF_S: |
5533 | 0 | case LoongArch::VFCMP_CEQ_D: |
5534 | 0 | case LoongArch::VFCMP_CEQ_S: |
5535 | 0 | case LoongArch::VFCMP_CLE_D: |
5536 | 0 | case LoongArch::VFCMP_CLE_S: |
5537 | 0 | case LoongArch::VFCMP_CLT_D: |
5538 | 0 | case LoongArch::VFCMP_CLT_S: |
5539 | 0 | case LoongArch::VFCMP_CNE_D: |
5540 | 0 | case LoongArch::VFCMP_CNE_S: |
5541 | 0 | case LoongArch::VFCMP_COR_D: |
5542 | 0 | case LoongArch::VFCMP_COR_S: |
5543 | 0 | case LoongArch::VFCMP_CUEQ_D: |
5544 | 0 | case LoongArch::VFCMP_CUEQ_S: |
5545 | 0 | case LoongArch::VFCMP_CULE_D: |
5546 | 0 | case LoongArch::VFCMP_CULE_S: |
5547 | 0 | case LoongArch::VFCMP_CULT_D: |
5548 | 0 | case LoongArch::VFCMP_CULT_S: |
5549 | 0 | case LoongArch::VFCMP_CUNE_D: |
5550 | 0 | case LoongArch::VFCMP_CUNE_S: |
5551 | 0 | case LoongArch::VFCMP_CUN_D: |
5552 | 0 | case LoongArch::VFCMP_CUN_S: |
5553 | 0 | case LoongArch::VFCMP_SAF_D: |
5554 | 0 | case LoongArch::VFCMP_SAF_S: |
5555 | 0 | case LoongArch::VFCMP_SEQ_D: |
5556 | 0 | case LoongArch::VFCMP_SEQ_S: |
5557 | 0 | case LoongArch::VFCMP_SLE_D: |
5558 | 0 | case LoongArch::VFCMP_SLE_S: |
5559 | 0 | case LoongArch::VFCMP_SLT_D: |
5560 | 0 | case LoongArch::VFCMP_SLT_S: |
5561 | 0 | case LoongArch::VFCMP_SNE_D: |
5562 | 0 | case LoongArch::VFCMP_SNE_S: |
5563 | 0 | case LoongArch::VFCMP_SOR_D: |
5564 | 0 | case LoongArch::VFCMP_SOR_S: |
5565 | 0 | case LoongArch::VFCMP_SUEQ_D: |
5566 | 0 | case LoongArch::VFCMP_SUEQ_S: |
5567 | 0 | case LoongArch::VFCMP_SULE_D: |
5568 | 0 | case LoongArch::VFCMP_SULE_S: |
5569 | 0 | case LoongArch::VFCMP_SULT_D: |
5570 | 0 | case LoongArch::VFCMP_SULT_S: |
5571 | 0 | case LoongArch::VFCMP_SUNE_D: |
5572 | 0 | case LoongArch::VFCMP_SUNE_S: |
5573 | 0 | case LoongArch::VFCMP_SUN_D: |
5574 | 0 | case LoongArch::VFCMP_SUN_S: |
5575 | 0 | case LoongArch::VFCVT_H_S: |
5576 | 0 | case LoongArch::VFCVT_S_D: |
5577 | 0 | case LoongArch::VFDIV_D: |
5578 | 0 | case LoongArch::VFDIV_S: |
5579 | 0 | case LoongArch::VFFINT_S_L: |
5580 | 0 | case LoongArch::VFMAXA_D: |
5581 | 0 | case LoongArch::VFMAXA_S: |
5582 | 0 | case LoongArch::VFMAX_D: |
5583 | 0 | case LoongArch::VFMAX_S: |
5584 | 0 | case LoongArch::VFMINA_D: |
5585 | 0 | case LoongArch::VFMINA_S: |
5586 | 0 | case LoongArch::VFMIN_D: |
5587 | 0 | case LoongArch::VFMIN_S: |
5588 | 0 | case LoongArch::VFMUL_D: |
5589 | 0 | case LoongArch::VFMUL_S: |
5590 | 0 | case LoongArch::VFSUB_D: |
5591 | 0 | case LoongArch::VFSUB_S: |
5592 | 0 | case LoongArch::VFTINTRM_W_D: |
5593 | 0 | case LoongArch::VFTINTRNE_W_D: |
5594 | 0 | case LoongArch::VFTINTRP_W_D: |
5595 | 0 | case LoongArch::VFTINTRZ_W_D: |
5596 | 0 | case LoongArch::VFTINT_W_D: |
5597 | 0 | case LoongArch::VHADDW_DU_WU: |
5598 | 0 | case LoongArch::VHADDW_D_W: |
5599 | 0 | case LoongArch::VHADDW_HU_BU: |
5600 | 0 | case LoongArch::VHADDW_H_B: |
5601 | 0 | case LoongArch::VHADDW_QU_DU: |
5602 | 0 | case LoongArch::VHADDW_Q_D: |
5603 | 0 | case LoongArch::VHADDW_WU_HU: |
5604 | 0 | case LoongArch::VHADDW_W_H: |
5605 | 0 | case LoongArch::VHSUBW_DU_WU: |
5606 | 0 | case LoongArch::VHSUBW_D_W: |
5607 | 0 | case LoongArch::VHSUBW_HU_BU: |
5608 | 0 | case LoongArch::VHSUBW_H_B: |
5609 | 0 | case LoongArch::VHSUBW_QU_DU: |
5610 | 0 | case LoongArch::VHSUBW_Q_D: |
5611 | 0 | case LoongArch::VHSUBW_WU_HU: |
5612 | 0 | case LoongArch::VHSUBW_W_H: |
5613 | 0 | case LoongArch::VILVH_B: |
5614 | 0 | case LoongArch::VILVH_D: |
5615 | 0 | case LoongArch::VILVH_H: |
5616 | 0 | case LoongArch::VILVH_W: |
5617 | 0 | case LoongArch::VILVL_B: |
5618 | 0 | case LoongArch::VILVL_D: |
5619 | 0 | case LoongArch::VILVL_H: |
5620 | 0 | case LoongArch::VILVL_W: |
5621 | 0 | case LoongArch::VMAX_B: |
5622 | 0 | case LoongArch::VMAX_BU: |
5623 | 0 | case LoongArch::VMAX_D: |
5624 | 0 | case LoongArch::VMAX_DU: |
5625 | 0 | case LoongArch::VMAX_H: |
5626 | 0 | case LoongArch::VMAX_HU: |
5627 | 0 | case LoongArch::VMAX_W: |
5628 | 0 | case LoongArch::VMAX_WU: |
5629 | 0 | case LoongArch::VMIN_B: |
5630 | 0 | case LoongArch::VMIN_BU: |
5631 | 0 | case LoongArch::VMIN_D: |
5632 | 0 | case LoongArch::VMIN_DU: |
5633 | 0 | case LoongArch::VMIN_H: |
5634 | 0 | case LoongArch::VMIN_HU: |
5635 | 0 | case LoongArch::VMIN_W: |
5636 | 0 | case LoongArch::VMIN_WU: |
5637 | 0 | case LoongArch::VMOD_B: |
5638 | 0 | case LoongArch::VMOD_BU: |
5639 | 0 | case LoongArch::VMOD_D: |
5640 | 0 | case LoongArch::VMOD_DU: |
5641 | 0 | case LoongArch::VMOD_H: |
5642 | 0 | case LoongArch::VMOD_HU: |
5643 | 0 | case LoongArch::VMOD_W: |
5644 | 0 | case LoongArch::VMOD_WU: |
5645 | 0 | case LoongArch::VMUH_B: |
5646 | 0 | case LoongArch::VMUH_BU: |
5647 | 0 | case LoongArch::VMUH_D: |
5648 | 0 | case LoongArch::VMUH_DU: |
5649 | 0 | case LoongArch::VMUH_H: |
5650 | 0 | case LoongArch::VMUH_HU: |
5651 | 0 | case LoongArch::VMUH_W: |
5652 | 0 | case LoongArch::VMUH_WU: |
5653 | 0 | case LoongArch::VMULWEV_D_W: |
5654 | 0 | case LoongArch::VMULWEV_D_WU: |
5655 | 0 | case LoongArch::VMULWEV_D_WU_W: |
5656 | 0 | case LoongArch::VMULWEV_H_B: |
5657 | 0 | case LoongArch::VMULWEV_H_BU: |
5658 | 0 | case LoongArch::VMULWEV_H_BU_B: |
5659 | 0 | case LoongArch::VMULWEV_Q_D: |
5660 | 0 | case LoongArch::VMULWEV_Q_DU: |
5661 | 0 | case LoongArch::VMULWEV_Q_DU_D: |
5662 | 0 | case LoongArch::VMULWEV_W_H: |
5663 | 0 | case LoongArch::VMULWEV_W_HU: |
5664 | 0 | case LoongArch::VMULWEV_W_HU_H: |
5665 | 0 | case LoongArch::VMULWOD_D_W: |
5666 | 0 | case LoongArch::VMULWOD_D_WU: |
5667 | 0 | case LoongArch::VMULWOD_D_WU_W: |
5668 | 0 | case LoongArch::VMULWOD_H_B: |
5669 | 0 | case LoongArch::VMULWOD_H_BU: |
5670 | 0 | case LoongArch::VMULWOD_H_BU_B: |
5671 | 0 | case LoongArch::VMULWOD_Q_D: |
5672 | 0 | case LoongArch::VMULWOD_Q_DU: |
5673 | 0 | case LoongArch::VMULWOD_Q_DU_D: |
5674 | 0 | case LoongArch::VMULWOD_W_H: |
5675 | 0 | case LoongArch::VMULWOD_W_HU: |
5676 | 0 | case LoongArch::VMULWOD_W_HU_H: |
5677 | 0 | case LoongArch::VMUL_B: |
5678 | 0 | case LoongArch::VMUL_D: |
5679 | 0 | case LoongArch::VMUL_H: |
5680 | 0 | case LoongArch::VMUL_W: |
5681 | 0 | case LoongArch::VNOR_V: |
5682 | 0 | case LoongArch::VORN_V: |
5683 | 0 | case LoongArch::VOR_V: |
5684 | 0 | case LoongArch::VPACKEV_B: |
5685 | 0 | case LoongArch::VPACKEV_D: |
5686 | 0 | case LoongArch::VPACKEV_H: |
5687 | 0 | case LoongArch::VPACKEV_W: |
5688 | 0 | case LoongArch::VPACKOD_B: |
5689 | 0 | case LoongArch::VPACKOD_D: |
5690 | 0 | case LoongArch::VPACKOD_H: |
5691 | 0 | case LoongArch::VPACKOD_W: |
5692 | 0 | case LoongArch::VPICKEV_B: |
5693 | 0 | case LoongArch::VPICKEV_D: |
5694 | 0 | case LoongArch::VPICKEV_H: |
5695 | 0 | case LoongArch::VPICKEV_W: |
5696 | 0 | case LoongArch::VPICKOD_B: |
5697 | 0 | case LoongArch::VPICKOD_D: |
5698 | 0 | case LoongArch::VPICKOD_H: |
5699 | 0 | case LoongArch::VPICKOD_W: |
5700 | 0 | case LoongArch::VROTR_B: |
5701 | 0 | case LoongArch::VROTR_D: |
5702 | 0 | case LoongArch::VROTR_H: |
5703 | 0 | case LoongArch::VROTR_W: |
5704 | 0 | case LoongArch::VSADD_B: |
5705 | 0 | case LoongArch::VSADD_BU: |
5706 | 0 | case LoongArch::VSADD_D: |
5707 | 0 | case LoongArch::VSADD_DU: |
5708 | 0 | case LoongArch::VSADD_H: |
5709 | 0 | case LoongArch::VSADD_HU: |
5710 | 0 | case LoongArch::VSADD_W: |
5711 | 0 | case LoongArch::VSADD_WU: |
5712 | 0 | case LoongArch::VSEQ_B: |
5713 | 0 | case LoongArch::VSEQ_D: |
5714 | 0 | case LoongArch::VSEQ_H: |
5715 | 0 | case LoongArch::VSEQ_W: |
5716 | 0 | case LoongArch::VSIGNCOV_B: |
5717 | 0 | case LoongArch::VSIGNCOV_D: |
5718 | 0 | case LoongArch::VSIGNCOV_H: |
5719 | 0 | case LoongArch::VSIGNCOV_W: |
5720 | 0 | case LoongArch::VSLE_B: |
5721 | 0 | case LoongArch::VSLE_BU: |
5722 | 0 | case LoongArch::VSLE_D: |
5723 | 0 | case LoongArch::VSLE_DU: |
5724 | 0 | case LoongArch::VSLE_H: |
5725 | 0 | case LoongArch::VSLE_HU: |
5726 | 0 | case LoongArch::VSLE_W: |
5727 | 0 | case LoongArch::VSLE_WU: |
5728 | 0 | case LoongArch::VSLL_B: |
5729 | 0 | case LoongArch::VSLL_D: |
5730 | 0 | case LoongArch::VSLL_H: |
5731 | 0 | case LoongArch::VSLL_W: |
5732 | 0 | case LoongArch::VSLT_B: |
5733 | 0 | case LoongArch::VSLT_BU: |
5734 | 0 | case LoongArch::VSLT_D: |
5735 | 0 | case LoongArch::VSLT_DU: |
5736 | 0 | case LoongArch::VSLT_H: |
5737 | 0 | case LoongArch::VSLT_HU: |
5738 | 0 | case LoongArch::VSLT_W: |
5739 | 0 | case LoongArch::VSLT_WU: |
5740 | 0 | case LoongArch::VSRAN_B_H: |
5741 | 0 | case LoongArch::VSRAN_H_W: |
5742 | 0 | case LoongArch::VSRAN_W_D: |
5743 | 0 | case LoongArch::VSRARN_B_H: |
5744 | 0 | case LoongArch::VSRARN_H_W: |
5745 | 0 | case LoongArch::VSRARN_W_D: |
5746 | 0 | case LoongArch::VSRAR_B: |
5747 | 0 | case LoongArch::VSRAR_D: |
5748 | 0 | case LoongArch::VSRAR_H: |
5749 | 0 | case LoongArch::VSRAR_W: |
5750 | 0 | case LoongArch::VSRA_B: |
5751 | 0 | case LoongArch::VSRA_D: |
5752 | 0 | case LoongArch::VSRA_H: |
5753 | 0 | case LoongArch::VSRA_W: |
5754 | 0 | case LoongArch::VSRLN_B_H: |
5755 | 0 | case LoongArch::VSRLN_H_W: |
5756 | 0 | case LoongArch::VSRLN_W_D: |
5757 | 0 | case LoongArch::VSRLRN_B_H: |
5758 | 0 | case LoongArch::VSRLRN_H_W: |
5759 | 0 | case LoongArch::VSRLRN_W_D: |
5760 | 0 | case LoongArch::VSRLR_B: |
5761 | 0 | case LoongArch::VSRLR_D: |
5762 | 0 | case LoongArch::VSRLR_H: |
5763 | 0 | case LoongArch::VSRLR_W: |
5764 | 0 | case LoongArch::VSRL_B: |
5765 | 0 | case LoongArch::VSRL_D: |
5766 | 0 | case LoongArch::VSRL_H: |
5767 | 0 | case LoongArch::VSRL_W: |
5768 | 0 | case LoongArch::VSSRAN_BU_H: |
5769 | 0 | case LoongArch::VSSRAN_B_H: |
5770 | 0 | case LoongArch::VSSRAN_HU_W: |
5771 | 0 | case LoongArch::VSSRAN_H_W: |
5772 | 0 | case LoongArch::VSSRAN_WU_D: |
5773 | 0 | case LoongArch::VSSRAN_W_D: |
5774 | 0 | case LoongArch::VSSRARN_BU_H: |
5775 | 0 | case LoongArch::VSSRARN_B_H: |
5776 | 0 | case LoongArch::VSSRARN_HU_W: |
5777 | 0 | case LoongArch::VSSRARN_H_W: |
5778 | 0 | case LoongArch::VSSRARN_WU_D: |
5779 | 0 | case LoongArch::VSSRARN_W_D: |
5780 | 0 | case LoongArch::VSSRLN_BU_H: |
5781 | 0 | case LoongArch::VSSRLN_B_H: |
5782 | 0 | case LoongArch::VSSRLN_HU_W: |
5783 | 0 | case LoongArch::VSSRLN_H_W: |
5784 | 0 | case LoongArch::VSSRLN_WU_D: |
5785 | 0 | case LoongArch::VSSRLN_W_D: |
5786 | 0 | case LoongArch::VSSRLRN_BU_H: |
5787 | 0 | case LoongArch::VSSRLRN_B_H: |
5788 | 0 | case LoongArch::VSSRLRN_HU_W: |
5789 | 0 | case LoongArch::VSSRLRN_H_W: |
5790 | 0 | case LoongArch::VSSRLRN_WU_D: |
5791 | 0 | case LoongArch::VSSRLRN_W_D: |
5792 | 0 | case LoongArch::VSSUB_B: |
5793 | 0 | case LoongArch::VSSUB_BU: |
5794 | 0 | case LoongArch::VSSUB_D: |
5795 | 0 | case LoongArch::VSSUB_DU: |
5796 | 0 | case LoongArch::VSSUB_H: |
5797 | 0 | case LoongArch::VSSUB_HU: |
5798 | 0 | case LoongArch::VSSUB_W: |
5799 | 0 | case LoongArch::VSSUB_WU: |
5800 | 0 | case LoongArch::VSUBWEV_D_W: |
5801 | 0 | case LoongArch::VSUBWEV_D_WU: |
5802 | 0 | case LoongArch::VSUBWEV_H_B: |
5803 | 0 | case LoongArch::VSUBWEV_H_BU: |
5804 | 0 | case LoongArch::VSUBWEV_Q_D: |
5805 | 0 | case LoongArch::VSUBWEV_Q_DU: |
5806 | 0 | case LoongArch::VSUBWEV_W_H: |
5807 | 0 | case LoongArch::VSUBWEV_W_HU: |
5808 | 0 | case LoongArch::VSUBWOD_D_W: |
5809 | 0 | case LoongArch::VSUBWOD_D_WU: |
5810 | 0 | case LoongArch::VSUBWOD_H_B: |
5811 | 0 | case LoongArch::VSUBWOD_H_BU: |
5812 | 0 | case LoongArch::VSUBWOD_Q_D: |
5813 | 0 | case LoongArch::VSUBWOD_Q_DU: |
5814 | 0 | case LoongArch::VSUBWOD_W_H: |
5815 | 0 | case LoongArch::VSUBWOD_W_HU: |
5816 | 0 | case LoongArch::VSUB_B: |
5817 | 0 | case LoongArch::VSUB_D: |
5818 | 0 | case LoongArch::VSUB_H: |
5819 | 0 | case LoongArch::VSUB_Q: |
5820 | 0 | case LoongArch::VSUB_W: |
5821 | 0 | case LoongArch::VXOR_V: { |
5822 | | // op: vk |
5823 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5824 | 0 | op &= UINT64_C(31); |
5825 | 0 | op <<= 10; |
5826 | 0 | Value |= op; |
5827 | | // op: vj |
5828 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5829 | 0 | op &= UINT64_C(31); |
5830 | 0 | op <<= 5; |
5831 | 0 | Value |= op; |
5832 | | // op: vd |
5833 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5834 | 0 | op &= UINT64_C(31); |
5835 | 0 | Value |= op; |
5836 | 0 | break; |
5837 | 0 | } |
5838 | 0 | case LoongArch::VFRSTP_B: |
5839 | 0 | case LoongArch::VFRSTP_H: |
5840 | 0 | case LoongArch::VMADDWEV_D_W: |
5841 | 0 | case LoongArch::VMADDWEV_D_WU: |
5842 | 0 | case LoongArch::VMADDWEV_D_WU_W: |
5843 | 0 | case LoongArch::VMADDWEV_H_B: |
5844 | 0 | case LoongArch::VMADDWEV_H_BU: |
5845 | 0 | case LoongArch::VMADDWEV_H_BU_B: |
5846 | 0 | case LoongArch::VMADDWEV_Q_D: |
5847 | 0 | case LoongArch::VMADDWEV_Q_DU: |
5848 | 0 | case LoongArch::VMADDWEV_Q_DU_D: |
5849 | 0 | case LoongArch::VMADDWEV_W_H: |
5850 | 0 | case LoongArch::VMADDWEV_W_HU: |
5851 | 0 | case LoongArch::VMADDWEV_W_HU_H: |
5852 | 0 | case LoongArch::VMADDWOD_D_W: |
5853 | 0 | case LoongArch::VMADDWOD_D_WU: |
5854 | 0 | case LoongArch::VMADDWOD_D_WU_W: |
5855 | 0 | case LoongArch::VMADDWOD_H_B: |
5856 | 0 | case LoongArch::VMADDWOD_H_BU: |
5857 | 0 | case LoongArch::VMADDWOD_H_BU_B: |
5858 | 0 | case LoongArch::VMADDWOD_Q_D: |
5859 | 0 | case LoongArch::VMADDWOD_Q_DU: |
5860 | 0 | case LoongArch::VMADDWOD_Q_DU_D: |
5861 | 0 | case LoongArch::VMADDWOD_W_H: |
5862 | 0 | case LoongArch::VMADDWOD_W_HU: |
5863 | 0 | case LoongArch::VMADDWOD_W_HU_H: |
5864 | 0 | case LoongArch::VMADD_B: |
5865 | 0 | case LoongArch::VMADD_D: |
5866 | 0 | case LoongArch::VMADD_H: |
5867 | 0 | case LoongArch::VMADD_W: |
5868 | 0 | case LoongArch::VMSUB_B: |
5869 | 0 | case LoongArch::VMSUB_D: |
5870 | 0 | case LoongArch::VMSUB_H: |
5871 | 0 | case LoongArch::VMSUB_W: |
5872 | 0 | case LoongArch::VSHUF_D: |
5873 | 0 | case LoongArch::VSHUF_H: |
5874 | 0 | case LoongArch::VSHUF_W: { |
5875 | | // op: vk |
5876 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5877 | 0 | op &= UINT64_C(31); |
5878 | 0 | op <<= 10; |
5879 | 0 | Value |= op; |
5880 | | // op: vj |
5881 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5882 | 0 | op &= UINT64_C(31); |
5883 | 0 | op <<= 5; |
5884 | 0 | Value |= op; |
5885 | | // op: vd |
5886 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5887 | 0 | op &= UINT64_C(31); |
5888 | 0 | Value |= op; |
5889 | 0 | break; |
5890 | 0 | } |
5891 | 0 | case LoongArch::XVBITSEL_V: |
5892 | 0 | case LoongArch::XVFMADD_D: |
5893 | 0 | case LoongArch::XVFMADD_S: |
5894 | 0 | case LoongArch::XVFMSUB_D: |
5895 | 0 | case LoongArch::XVFMSUB_S: |
5896 | 0 | case LoongArch::XVFNMADD_D: |
5897 | 0 | case LoongArch::XVFNMADD_S: |
5898 | 0 | case LoongArch::XVFNMSUB_D: |
5899 | 0 | case LoongArch::XVFNMSUB_S: |
5900 | 0 | case LoongArch::XVSHUF_B: { |
5901 | | // op: xa |
5902 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5903 | 0 | op &= UINT64_C(31); |
5904 | 0 | op <<= 15; |
5905 | 0 | Value |= op; |
5906 | | // op: xk |
5907 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5908 | 0 | op &= UINT64_C(31); |
5909 | 0 | op <<= 10; |
5910 | 0 | Value |= op; |
5911 | | // op: xj |
5912 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5913 | 0 | op &= UINT64_C(31); |
5914 | 0 | op <<= 5; |
5915 | 0 | Value |= op; |
5916 | | // op: xd |
5917 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5918 | 0 | op &= UINT64_C(31); |
5919 | 0 | Value |= op; |
5920 | 0 | break; |
5921 | 0 | } |
5922 | 0 | case LoongArch::XVSETALLNEZ_B: |
5923 | 0 | case LoongArch::XVSETALLNEZ_D: |
5924 | 0 | case LoongArch::XVSETALLNEZ_H: |
5925 | 0 | case LoongArch::XVSETALLNEZ_W: |
5926 | 0 | case LoongArch::XVSETANYEQZ_B: |
5927 | 0 | case LoongArch::XVSETANYEQZ_D: |
5928 | 0 | case LoongArch::XVSETANYEQZ_H: |
5929 | 0 | case LoongArch::XVSETANYEQZ_W: |
5930 | 0 | case LoongArch::XVSETEQZ_V: |
5931 | 0 | case LoongArch::XVSETNEZ_V: { |
5932 | | // op: xj |
5933 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5934 | 0 | op &= UINT64_C(31); |
5935 | 0 | op <<= 5; |
5936 | 0 | Value |= op; |
5937 | | // op: cd |
5938 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5939 | 0 | op &= UINT64_C(7); |
5940 | 0 | Value |= op; |
5941 | 0 | break; |
5942 | 0 | } |
5943 | 0 | case LoongArch::VEXT2XV_DU_BU: |
5944 | 0 | case LoongArch::VEXT2XV_DU_HU: |
5945 | 0 | case LoongArch::VEXT2XV_DU_WU: |
5946 | 0 | case LoongArch::VEXT2XV_D_B: |
5947 | 0 | case LoongArch::VEXT2XV_D_H: |
5948 | 0 | case LoongArch::VEXT2XV_D_W: |
5949 | 0 | case LoongArch::VEXT2XV_HU_BU: |
5950 | 0 | case LoongArch::VEXT2XV_H_B: |
5951 | 0 | case LoongArch::VEXT2XV_WU_BU: |
5952 | 0 | case LoongArch::VEXT2XV_WU_HU: |
5953 | 0 | case LoongArch::VEXT2XV_W_B: |
5954 | 0 | case LoongArch::VEXT2XV_W_H: |
5955 | 0 | case LoongArch::XVCLO_B: |
5956 | 0 | case LoongArch::XVCLO_D: |
5957 | 0 | case LoongArch::XVCLO_H: |
5958 | 0 | case LoongArch::XVCLO_W: |
5959 | 0 | case LoongArch::XVCLZ_B: |
5960 | 0 | case LoongArch::XVCLZ_D: |
5961 | 0 | case LoongArch::XVCLZ_H: |
5962 | 0 | case LoongArch::XVCLZ_W: |
5963 | 0 | case LoongArch::XVEXTH_DU_WU: |
5964 | 0 | case LoongArch::XVEXTH_D_W: |
5965 | 0 | case LoongArch::XVEXTH_HU_BU: |
5966 | 0 | case LoongArch::XVEXTH_H_B: |
5967 | 0 | case LoongArch::XVEXTH_QU_DU: |
5968 | 0 | case LoongArch::XVEXTH_Q_D: |
5969 | 0 | case LoongArch::XVEXTH_WU_HU: |
5970 | 0 | case LoongArch::XVEXTH_W_H: |
5971 | 0 | case LoongArch::XVEXTL_QU_DU: |
5972 | 0 | case LoongArch::XVEXTL_Q_D: |
5973 | 0 | case LoongArch::XVFCLASS_D: |
5974 | 0 | case LoongArch::XVFCLASS_S: |
5975 | 0 | case LoongArch::XVFCVTH_D_S: |
5976 | 0 | case LoongArch::XVFCVTH_S_H: |
5977 | 0 | case LoongArch::XVFCVTL_D_S: |
5978 | 0 | case LoongArch::XVFCVTL_S_H: |
5979 | 0 | case LoongArch::XVFFINTH_D_W: |
5980 | 0 | case LoongArch::XVFFINTL_D_W: |
5981 | 0 | case LoongArch::XVFFINT_D_L: |
5982 | 0 | case LoongArch::XVFFINT_D_LU: |
5983 | 0 | case LoongArch::XVFFINT_S_W: |
5984 | 0 | case LoongArch::XVFFINT_S_WU: |
5985 | 0 | case LoongArch::XVFLOGB_D: |
5986 | 0 | case LoongArch::XVFLOGB_S: |
5987 | 0 | case LoongArch::XVFRECIPE_D: |
5988 | 0 | case LoongArch::XVFRECIPE_S: |
5989 | 0 | case LoongArch::XVFRECIP_D: |
5990 | 0 | case LoongArch::XVFRECIP_S: |
5991 | 0 | case LoongArch::XVFRINTRM_D: |
5992 | 0 | case LoongArch::XVFRINTRM_S: |
5993 | 0 | case LoongArch::XVFRINTRNE_D: |
5994 | 0 | case LoongArch::XVFRINTRNE_S: |
5995 | 0 | case LoongArch::XVFRINTRP_D: |
5996 | 0 | case LoongArch::XVFRINTRP_S: |
5997 | 0 | case LoongArch::XVFRINTRZ_D: |
5998 | 0 | case LoongArch::XVFRINTRZ_S: |
5999 | 0 | case LoongArch::XVFRINT_D: |
6000 | 0 | case LoongArch::XVFRINT_S: |
6001 | 0 | case LoongArch::XVFRSQRTE_D: |
6002 | 0 | case LoongArch::XVFRSQRTE_S: |
6003 | 0 | case LoongArch::XVFRSQRT_D: |
6004 | 0 | case LoongArch::XVFRSQRT_S: |
6005 | 0 | case LoongArch::XVFSQRT_D: |
6006 | 0 | case LoongArch::XVFSQRT_S: |
6007 | 0 | case LoongArch::XVFTINTH_L_S: |
6008 | 0 | case LoongArch::XVFTINTL_L_S: |
6009 | 0 | case LoongArch::XVFTINTRMH_L_S: |
6010 | 0 | case LoongArch::XVFTINTRML_L_S: |
6011 | 0 | case LoongArch::XVFTINTRM_L_D: |
6012 | 0 | case LoongArch::XVFTINTRM_W_S: |
6013 | 0 | case LoongArch::XVFTINTRNEH_L_S: |
6014 | 0 | case LoongArch::XVFTINTRNEL_L_S: |
6015 | 0 | case LoongArch::XVFTINTRNE_L_D: |
6016 | 0 | case LoongArch::XVFTINTRNE_W_S: |
6017 | 0 | case LoongArch::XVFTINTRPH_L_S: |
6018 | 0 | case LoongArch::XVFTINTRPL_L_S: |
6019 | 0 | case LoongArch::XVFTINTRP_L_D: |
6020 | 0 | case LoongArch::XVFTINTRP_W_S: |
6021 | 0 | case LoongArch::XVFTINTRZH_L_S: |
6022 | 0 | case LoongArch::XVFTINTRZL_L_S: |
6023 | 0 | case LoongArch::XVFTINTRZ_LU_D: |
6024 | 0 | case LoongArch::XVFTINTRZ_L_D: |
6025 | 0 | case LoongArch::XVFTINTRZ_WU_S: |
6026 | 0 | case LoongArch::XVFTINTRZ_W_S: |
6027 | 0 | case LoongArch::XVFTINT_LU_D: |
6028 | 0 | case LoongArch::XVFTINT_L_D: |
6029 | 0 | case LoongArch::XVFTINT_WU_S: |
6030 | 0 | case LoongArch::XVFTINT_W_S: |
6031 | 0 | case LoongArch::XVMSKGEZ_B: |
6032 | 0 | case LoongArch::XVMSKLTZ_B: |
6033 | 0 | case LoongArch::XVMSKLTZ_D: |
6034 | 0 | case LoongArch::XVMSKLTZ_H: |
6035 | 0 | case LoongArch::XVMSKLTZ_W: |
6036 | 0 | case LoongArch::XVMSKNZ_B: |
6037 | 0 | case LoongArch::XVNEG_B: |
6038 | 0 | case LoongArch::XVNEG_D: |
6039 | 0 | case LoongArch::XVNEG_H: |
6040 | 0 | case LoongArch::XVNEG_W: |
6041 | 0 | case LoongArch::XVPCNT_B: |
6042 | 0 | case LoongArch::XVPCNT_D: |
6043 | 0 | case LoongArch::XVPCNT_H: |
6044 | 0 | case LoongArch::XVPCNT_W: |
6045 | 0 | case LoongArch::XVREPLVE0_B: |
6046 | 0 | case LoongArch::XVREPLVE0_D: |
6047 | 0 | case LoongArch::XVREPLVE0_H: |
6048 | 0 | case LoongArch::XVREPLVE0_Q: |
6049 | 0 | case LoongArch::XVREPLVE0_W: { |
6050 | | // op: xj |
6051 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6052 | 0 | op &= UINT64_C(31); |
6053 | 0 | op <<= 5; |
6054 | 0 | Value |= op; |
6055 | | // op: xd |
6056 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6057 | 0 | op &= UINT64_C(31); |
6058 | 0 | Value |= op; |
6059 | 0 | break; |
6060 | 0 | } |
6061 | 0 | case LoongArch::XVABSD_B: |
6062 | 0 | case LoongArch::XVABSD_BU: |
6063 | 0 | case LoongArch::XVABSD_D: |
6064 | 0 | case LoongArch::XVABSD_DU: |
6065 | 0 | case LoongArch::XVABSD_H: |
6066 | 0 | case LoongArch::XVABSD_HU: |
6067 | 0 | case LoongArch::XVABSD_W: |
6068 | 0 | case LoongArch::XVABSD_WU: |
6069 | 0 | case LoongArch::XVADDA_B: |
6070 | 0 | case LoongArch::XVADDA_D: |
6071 | 0 | case LoongArch::XVADDA_H: |
6072 | 0 | case LoongArch::XVADDA_W: |
6073 | 0 | case LoongArch::XVADDWEV_D_W: |
6074 | 0 | case LoongArch::XVADDWEV_D_WU: |
6075 | 0 | case LoongArch::XVADDWEV_D_WU_W: |
6076 | 0 | case LoongArch::XVADDWEV_H_B: |
6077 | 0 | case LoongArch::XVADDWEV_H_BU: |
6078 | 0 | case LoongArch::XVADDWEV_H_BU_B: |
6079 | 0 | case LoongArch::XVADDWEV_Q_D: |
6080 | 0 | case LoongArch::XVADDWEV_Q_DU: |
6081 | 0 | case LoongArch::XVADDWEV_Q_DU_D: |
6082 | 0 | case LoongArch::XVADDWEV_W_H: |
6083 | 0 | case LoongArch::XVADDWEV_W_HU: |
6084 | 0 | case LoongArch::XVADDWEV_W_HU_H: |
6085 | 0 | case LoongArch::XVADDWOD_D_W: |
6086 | 0 | case LoongArch::XVADDWOD_D_WU: |
6087 | 0 | case LoongArch::XVADDWOD_D_WU_W: |
6088 | 0 | case LoongArch::XVADDWOD_H_B: |
6089 | 0 | case LoongArch::XVADDWOD_H_BU: |
6090 | 0 | case LoongArch::XVADDWOD_H_BU_B: |
6091 | 0 | case LoongArch::XVADDWOD_Q_D: |
6092 | 0 | case LoongArch::XVADDWOD_Q_DU: |
6093 | 0 | case LoongArch::XVADDWOD_Q_DU_D: |
6094 | 0 | case LoongArch::XVADDWOD_W_H: |
6095 | 0 | case LoongArch::XVADDWOD_W_HU: |
6096 | 0 | case LoongArch::XVADDWOD_W_HU_H: |
6097 | 0 | case LoongArch::XVADD_B: |
6098 | 0 | case LoongArch::XVADD_D: |
6099 | 0 | case LoongArch::XVADD_H: |
6100 | 0 | case LoongArch::XVADD_Q: |
6101 | 0 | case LoongArch::XVADD_W: |
6102 | 0 | case LoongArch::XVANDN_V: |
6103 | 0 | case LoongArch::XVAND_V: |
6104 | 0 | case LoongArch::XVAVGR_B: |
6105 | 0 | case LoongArch::XVAVGR_BU: |
6106 | 0 | case LoongArch::XVAVGR_D: |
6107 | 0 | case LoongArch::XVAVGR_DU: |
6108 | 0 | case LoongArch::XVAVGR_H: |
6109 | 0 | case LoongArch::XVAVGR_HU: |
6110 | 0 | case LoongArch::XVAVGR_W: |
6111 | 0 | case LoongArch::XVAVGR_WU: |
6112 | 0 | case LoongArch::XVAVG_B: |
6113 | 0 | case LoongArch::XVAVG_BU: |
6114 | 0 | case LoongArch::XVAVG_D: |
6115 | 0 | case LoongArch::XVAVG_DU: |
6116 | 0 | case LoongArch::XVAVG_H: |
6117 | 0 | case LoongArch::XVAVG_HU: |
6118 | 0 | case LoongArch::XVAVG_W: |
6119 | 0 | case LoongArch::XVAVG_WU: |
6120 | 0 | case LoongArch::XVBITCLR_B: |
6121 | 0 | case LoongArch::XVBITCLR_D: |
6122 | 0 | case LoongArch::XVBITCLR_H: |
6123 | 0 | case LoongArch::XVBITCLR_W: |
6124 | 0 | case LoongArch::XVBITREV_B: |
6125 | 0 | case LoongArch::XVBITREV_D: |
6126 | 0 | case LoongArch::XVBITREV_H: |
6127 | 0 | case LoongArch::XVBITREV_W: |
6128 | 0 | case LoongArch::XVBITSET_B: |
6129 | 0 | case LoongArch::XVBITSET_D: |
6130 | 0 | case LoongArch::XVBITSET_H: |
6131 | 0 | case LoongArch::XVBITSET_W: |
6132 | 0 | case LoongArch::XVDIV_B: |
6133 | 0 | case LoongArch::XVDIV_BU: |
6134 | 0 | case LoongArch::XVDIV_D: |
6135 | 0 | case LoongArch::XVDIV_DU: |
6136 | 0 | case LoongArch::XVDIV_H: |
6137 | 0 | case LoongArch::XVDIV_HU: |
6138 | 0 | case LoongArch::XVDIV_W: |
6139 | 0 | case LoongArch::XVDIV_WU: |
6140 | 0 | case LoongArch::XVFADD_D: |
6141 | 0 | case LoongArch::XVFADD_S: |
6142 | 0 | case LoongArch::XVFCMP_CAF_D: |
6143 | 0 | case LoongArch::XVFCMP_CAF_S: |
6144 | 0 | case LoongArch::XVFCMP_CEQ_D: |
6145 | 0 | case LoongArch::XVFCMP_CEQ_S: |
6146 | 0 | case LoongArch::XVFCMP_CLE_D: |
6147 | 0 | case LoongArch::XVFCMP_CLE_S: |
6148 | 0 | case LoongArch::XVFCMP_CLT_D: |
6149 | 0 | case LoongArch::XVFCMP_CLT_S: |
6150 | 0 | case LoongArch::XVFCMP_CNE_D: |
6151 | 0 | case LoongArch::XVFCMP_CNE_S: |
6152 | 0 | case LoongArch::XVFCMP_COR_D: |
6153 | 0 | case LoongArch::XVFCMP_COR_S: |
6154 | 0 | case LoongArch::XVFCMP_CUEQ_D: |
6155 | 0 | case LoongArch::XVFCMP_CUEQ_S: |
6156 | 0 | case LoongArch::XVFCMP_CULE_D: |
6157 | 0 | case LoongArch::XVFCMP_CULE_S: |
6158 | 0 | case LoongArch::XVFCMP_CULT_D: |
6159 | 0 | case LoongArch::XVFCMP_CULT_S: |
6160 | 0 | case LoongArch::XVFCMP_CUNE_D: |
6161 | 0 | case LoongArch::XVFCMP_CUNE_S: |
6162 | 0 | case LoongArch::XVFCMP_CUN_D: |
6163 | 0 | case LoongArch::XVFCMP_CUN_S: |
6164 | 0 | case LoongArch::XVFCMP_SAF_D: |
6165 | 0 | case LoongArch::XVFCMP_SAF_S: |
6166 | 0 | case LoongArch::XVFCMP_SEQ_D: |
6167 | 0 | case LoongArch::XVFCMP_SEQ_S: |
6168 | 0 | case LoongArch::XVFCMP_SLE_D: |
6169 | 0 | case LoongArch::XVFCMP_SLE_S: |
6170 | 0 | case LoongArch::XVFCMP_SLT_D: |
6171 | 0 | case LoongArch::XVFCMP_SLT_S: |
6172 | 0 | case LoongArch::XVFCMP_SNE_D: |
6173 | 0 | case LoongArch::XVFCMP_SNE_S: |
6174 | 0 | case LoongArch::XVFCMP_SOR_D: |
6175 | 0 | case LoongArch::XVFCMP_SOR_S: |
6176 | 0 | case LoongArch::XVFCMP_SUEQ_D: |
6177 | 0 | case LoongArch::XVFCMP_SUEQ_S: |
6178 | 0 | case LoongArch::XVFCMP_SULE_D: |
6179 | 0 | case LoongArch::XVFCMP_SULE_S: |
6180 | 0 | case LoongArch::XVFCMP_SULT_D: |
6181 | 0 | case LoongArch::XVFCMP_SULT_S: |
6182 | 0 | case LoongArch::XVFCMP_SUNE_D: |
6183 | 0 | case LoongArch::XVFCMP_SUNE_S: |
6184 | 0 | case LoongArch::XVFCMP_SUN_D: |
6185 | 0 | case LoongArch::XVFCMP_SUN_S: |
6186 | 0 | case LoongArch::XVFCVT_H_S: |
6187 | 0 | case LoongArch::XVFCVT_S_D: |
6188 | 0 | case LoongArch::XVFDIV_D: |
6189 | 0 | case LoongArch::XVFDIV_S: |
6190 | 0 | case LoongArch::XVFFINT_S_L: |
6191 | 0 | case LoongArch::XVFMAXA_D: |
6192 | 0 | case LoongArch::XVFMAXA_S: |
6193 | 0 | case LoongArch::XVFMAX_D: |
6194 | 0 | case LoongArch::XVFMAX_S: |
6195 | 0 | case LoongArch::XVFMINA_D: |
6196 | 0 | case LoongArch::XVFMINA_S: |
6197 | 0 | case LoongArch::XVFMIN_D: |
6198 | 0 | case LoongArch::XVFMIN_S: |
6199 | 0 | case LoongArch::XVFMUL_D: |
6200 | 0 | case LoongArch::XVFMUL_S: |
6201 | 0 | case LoongArch::XVFSUB_D: |
6202 | 0 | case LoongArch::XVFSUB_S: |
6203 | 0 | case LoongArch::XVFTINTRM_W_D: |
6204 | 0 | case LoongArch::XVFTINTRNE_W_D: |
6205 | 0 | case LoongArch::XVFTINTRP_W_D: |
6206 | 0 | case LoongArch::XVFTINTRZ_W_D: |
6207 | 0 | case LoongArch::XVFTINT_W_D: |
6208 | 0 | case LoongArch::XVHADDW_DU_WU: |
6209 | 0 | case LoongArch::XVHADDW_D_W: |
6210 | 0 | case LoongArch::XVHADDW_HU_BU: |
6211 | 0 | case LoongArch::XVHADDW_H_B: |
6212 | 0 | case LoongArch::XVHADDW_QU_DU: |
6213 | 0 | case LoongArch::XVHADDW_Q_D: |
6214 | 0 | case LoongArch::XVHADDW_WU_HU: |
6215 | 0 | case LoongArch::XVHADDW_W_H: |
6216 | 0 | case LoongArch::XVHSUBW_DU_WU: |
6217 | 0 | case LoongArch::XVHSUBW_D_W: |
6218 | 0 | case LoongArch::XVHSUBW_HU_BU: |
6219 | 0 | case LoongArch::XVHSUBW_H_B: |
6220 | 0 | case LoongArch::XVHSUBW_QU_DU: |
6221 | 0 | case LoongArch::XVHSUBW_Q_D: |
6222 | 0 | case LoongArch::XVHSUBW_WU_HU: |
6223 | 0 | case LoongArch::XVHSUBW_W_H: |
6224 | 0 | case LoongArch::XVILVH_B: |
6225 | 0 | case LoongArch::XVILVH_D: |
6226 | 0 | case LoongArch::XVILVH_H: |
6227 | 0 | case LoongArch::XVILVH_W: |
6228 | 0 | case LoongArch::XVILVL_B: |
6229 | 0 | case LoongArch::XVILVL_D: |
6230 | 0 | case LoongArch::XVILVL_H: |
6231 | 0 | case LoongArch::XVILVL_W: |
6232 | 0 | case LoongArch::XVMAX_B: |
6233 | 0 | case LoongArch::XVMAX_BU: |
6234 | 0 | case LoongArch::XVMAX_D: |
6235 | 0 | case LoongArch::XVMAX_DU: |
6236 | 0 | case LoongArch::XVMAX_H: |
6237 | 0 | case LoongArch::XVMAX_HU: |
6238 | 0 | case LoongArch::XVMAX_W: |
6239 | 0 | case LoongArch::XVMAX_WU: |
6240 | 0 | case LoongArch::XVMIN_B: |
6241 | 0 | case LoongArch::XVMIN_BU: |
6242 | 0 | case LoongArch::XVMIN_D: |
6243 | 0 | case LoongArch::XVMIN_DU: |
6244 | 0 | case LoongArch::XVMIN_H: |
6245 | 0 | case LoongArch::XVMIN_HU: |
6246 | 0 | case LoongArch::XVMIN_W: |
6247 | 0 | case LoongArch::XVMIN_WU: |
6248 | 0 | case LoongArch::XVMOD_B: |
6249 | 0 | case LoongArch::XVMOD_BU: |
6250 | 0 | case LoongArch::XVMOD_D: |
6251 | 0 | case LoongArch::XVMOD_DU: |
6252 | 0 | case LoongArch::XVMOD_H: |
6253 | 0 | case LoongArch::XVMOD_HU: |
6254 | 0 | case LoongArch::XVMOD_W: |
6255 | 0 | case LoongArch::XVMOD_WU: |
6256 | 0 | case LoongArch::XVMUH_B: |
6257 | 0 | case LoongArch::XVMUH_BU: |
6258 | 0 | case LoongArch::XVMUH_D: |
6259 | 0 | case LoongArch::XVMUH_DU: |
6260 | 0 | case LoongArch::XVMUH_H: |
6261 | 0 | case LoongArch::XVMUH_HU: |
6262 | 0 | case LoongArch::XVMUH_W: |
6263 | 0 | case LoongArch::XVMUH_WU: |
6264 | 0 | case LoongArch::XVMULWEV_D_W: |
6265 | 0 | case LoongArch::XVMULWEV_D_WU: |
6266 | 0 | case LoongArch::XVMULWEV_D_WU_W: |
6267 | 0 | case LoongArch::XVMULWEV_H_B: |
6268 | 0 | case LoongArch::XVMULWEV_H_BU: |
6269 | 0 | case LoongArch::XVMULWEV_H_BU_B: |
6270 | 0 | case LoongArch::XVMULWEV_Q_D: |
6271 | 0 | case LoongArch::XVMULWEV_Q_DU: |
6272 | 0 | case LoongArch::XVMULWEV_Q_DU_D: |
6273 | 0 | case LoongArch::XVMULWEV_W_H: |
6274 | 0 | case LoongArch::XVMULWEV_W_HU: |
6275 | 0 | case LoongArch::XVMULWEV_W_HU_H: |
6276 | 0 | case LoongArch::XVMULWOD_D_W: |
6277 | 0 | case LoongArch::XVMULWOD_D_WU: |
6278 | 0 | case LoongArch::XVMULWOD_D_WU_W: |
6279 | 0 | case LoongArch::XVMULWOD_H_B: |
6280 | 0 | case LoongArch::XVMULWOD_H_BU: |
6281 | 0 | case LoongArch::XVMULWOD_H_BU_B: |
6282 | 0 | case LoongArch::XVMULWOD_Q_D: |
6283 | 0 | case LoongArch::XVMULWOD_Q_DU: |
6284 | 0 | case LoongArch::XVMULWOD_Q_DU_D: |
6285 | 0 | case LoongArch::XVMULWOD_W_H: |
6286 | 0 | case LoongArch::XVMULWOD_W_HU: |
6287 | 0 | case LoongArch::XVMULWOD_W_HU_H: |
6288 | 0 | case LoongArch::XVMUL_B: |
6289 | 0 | case LoongArch::XVMUL_D: |
6290 | 0 | case LoongArch::XVMUL_H: |
6291 | 0 | case LoongArch::XVMUL_W: |
6292 | 0 | case LoongArch::XVNOR_V: |
6293 | 0 | case LoongArch::XVORN_V: |
6294 | 0 | case LoongArch::XVOR_V: |
6295 | 0 | case LoongArch::XVPACKEV_B: |
6296 | 0 | case LoongArch::XVPACKEV_D: |
6297 | 0 | case LoongArch::XVPACKEV_H: |
6298 | 0 | case LoongArch::XVPACKEV_W: |
6299 | 0 | case LoongArch::XVPACKOD_B: |
6300 | 0 | case LoongArch::XVPACKOD_D: |
6301 | 0 | case LoongArch::XVPACKOD_H: |
6302 | 0 | case LoongArch::XVPACKOD_W: |
6303 | 0 | case LoongArch::XVPERM_W: |
6304 | 0 | case LoongArch::XVPICKEV_B: |
6305 | 0 | case LoongArch::XVPICKEV_D: |
6306 | 0 | case LoongArch::XVPICKEV_H: |
6307 | 0 | case LoongArch::XVPICKEV_W: |
6308 | 0 | case LoongArch::XVPICKOD_B: |
6309 | 0 | case LoongArch::XVPICKOD_D: |
6310 | 0 | case LoongArch::XVPICKOD_H: |
6311 | 0 | case LoongArch::XVPICKOD_W: |
6312 | 0 | case LoongArch::XVROTR_B: |
6313 | 0 | case LoongArch::XVROTR_D: |
6314 | 0 | case LoongArch::XVROTR_H: |
6315 | 0 | case LoongArch::XVROTR_W: |
6316 | 0 | case LoongArch::XVSADD_B: |
6317 | 0 | case LoongArch::XVSADD_BU: |
6318 | 0 | case LoongArch::XVSADD_D: |
6319 | 0 | case LoongArch::XVSADD_DU: |
6320 | 0 | case LoongArch::XVSADD_H: |
6321 | 0 | case LoongArch::XVSADD_HU: |
6322 | 0 | case LoongArch::XVSADD_W: |
6323 | 0 | case LoongArch::XVSADD_WU: |
6324 | 0 | case LoongArch::XVSEQ_B: |
6325 | 0 | case LoongArch::XVSEQ_D: |
6326 | 0 | case LoongArch::XVSEQ_H: |
6327 | 0 | case LoongArch::XVSEQ_W: |
6328 | 0 | case LoongArch::XVSIGNCOV_B: |
6329 | 0 | case LoongArch::XVSIGNCOV_D: |
6330 | 0 | case LoongArch::XVSIGNCOV_H: |
6331 | 0 | case LoongArch::XVSIGNCOV_W: |
6332 | 0 | case LoongArch::XVSLE_B: |
6333 | 0 | case LoongArch::XVSLE_BU: |
6334 | 0 | case LoongArch::XVSLE_D: |
6335 | 0 | case LoongArch::XVSLE_DU: |
6336 | 0 | case LoongArch::XVSLE_H: |
6337 | 0 | case LoongArch::XVSLE_HU: |
6338 | 0 | case LoongArch::XVSLE_W: |
6339 | 0 | case LoongArch::XVSLE_WU: |
6340 | 0 | case LoongArch::XVSLL_B: |
6341 | 0 | case LoongArch::XVSLL_D: |
6342 | 0 | case LoongArch::XVSLL_H: |
6343 | 0 | case LoongArch::XVSLL_W: |
6344 | 0 | case LoongArch::XVSLT_B: |
6345 | 0 | case LoongArch::XVSLT_BU: |
6346 | 0 | case LoongArch::XVSLT_D: |
6347 | 0 | case LoongArch::XVSLT_DU: |
6348 | 0 | case LoongArch::XVSLT_H: |
6349 | 0 | case LoongArch::XVSLT_HU: |
6350 | 0 | case LoongArch::XVSLT_W: |
6351 | 0 | case LoongArch::XVSLT_WU: |
6352 | 0 | case LoongArch::XVSRAN_B_H: |
6353 | 0 | case LoongArch::XVSRAN_H_W: |
6354 | 0 | case LoongArch::XVSRAN_W_D: |
6355 | 0 | case LoongArch::XVSRARN_B_H: |
6356 | 0 | case LoongArch::XVSRARN_H_W: |
6357 | 0 | case LoongArch::XVSRARN_W_D: |
6358 | 0 | case LoongArch::XVSRAR_B: |
6359 | 0 | case LoongArch::XVSRAR_D: |
6360 | 0 | case LoongArch::XVSRAR_H: |
6361 | 0 | case LoongArch::XVSRAR_W: |
6362 | 0 | case LoongArch::XVSRA_B: |
6363 | 0 | case LoongArch::XVSRA_D: |
6364 | 0 | case LoongArch::XVSRA_H: |
6365 | 0 | case LoongArch::XVSRA_W: |
6366 | 0 | case LoongArch::XVSRLN_B_H: |
6367 | 0 | case LoongArch::XVSRLN_H_W: |
6368 | 0 | case LoongArch::XVSRLN_W_D: |
6369 | 0 | case LoongArch::XVSRLRN_B_H: |
6370 | 0 | case LoongArch::XVSRLRN_H_W: |
6371 | 0 | case LoongArch::XVSRLRN_W_D: |
6372 | 0 | case LoongArch::XVSRLR_B: |
6373 | 0 | case LoongArch::XVSRLR_D: |
6374 | 0 | case LoongArch::XVSRLR_H: |
6375 | 0 | case LoongArch::XVSRLR_W: |
6376 | 0 | case LoongArch::XVSRL_B: |
6377 | 0 | case LoongArch::XVSRL_D: |
6378 | 0 | case LoongArch::XVSRL_H: |
6379 | 0 | case LoongArch::XVSRL_W: |
6380 | 0 | case LoongArch::XVSSRAN_BU_H: |
6381 | 0 | case LoongArch::XVSSRAN_B_H: |
6382 | 0 | case LoongArch::XVSSRAN_HU_W: |
6383 | 0 | case LoongArch::XVSSRAN_H_W: |
6384 | 0 | case LoongArch::XVSSRAN_WU_D: |
6385 | 0 | case LoongArch::XVSSRAN_W_D: |
6386 | 0 | case LoongArch::XVSSRARN_BU_H: |
6387 | 0 | case LoongArch::XVSSRARN_B_H: |
6388 | 0 | case LoongArch::XVSSRARN_HU_W: |
6389 | 0 | case LoongArch::XVSSRARN_H_W: |
6390 | 0 | case LoongArch::XVSSRARN_WU_D: |
6391 | 0 | case LoongArch::XVSSRARN_W_D: |
6392 | 0 | case LoongArch::XVSSRLN_BU_H: |
6393 | 0 | case LoongArch::XVSSRLN_B_H: |
6394 | 0 | case LoongArch::XVSSRLN_HU_W: |
6395 | 0 | case LoongArch::XVSSRLN_H_W: |
6396 | 0 | case LoongArch::XVSSRLN_WU_D: |
6397 | 0 | case LoongArch::XVSSRLN_W_D: |
6398 | 0 | case LoongArch::XVSSRLRN_BU_H: |
6399 | 0 | case LoongArch::XVSSRLRN_B_H: |
6400 | 0 | case LoongArch::XVSSRLRN_HU_W: |
6401 | 0 | case LoongArch::XVSSRLRN_H_W: |
6402 | 0 | case LoongArch::XVSSRLRN_WU_D: |
6403 | 0 | case LoongArch::XVSSRLRN_W_D: |
6404 | 0 | case LoongArch::XVSSUB_B: |
6405 | 0 | case LoongArch::XVSSUB_BU: |
6406 | 0 | case LoongArch::XVSSUB_D: |
6407 | 0 | case LoongArch::XVSSUB_DU: |
6408 | 0 | case LoongArch::XVSSUB_H: |
6409 | 0 | case LoongArch::XVSSUB_HU: |
6410 | 0 | case LoongArch::XVSSUB_W: |
6411 | 0 | case LoongArch::XVSSUB_WU: |
6412 | 0 | case LoongArch::XVSUBWEV_D_W: |
6413 | 0 | case LoongArch::XVSUBWEV_D_WU: |
6414 | 0 | case LoongArch::XVSUBWEV_H_B: |
6415 | 0 | case LoongArch::XVSUBWEV_H_BU: |
6416 | 0 | case LoongArch::XVSUBWEV_Q_D: |
6417 | 0 | case LoongArch::XVSUBWEV_Q_DU: |
6418 | 0 | case LoongArch::XVSUBWEV_W_H: |
6419 | 0 | case LoongArch::XVSUBWEV_W_HU: |
6420 | 0 | case LoongArch::XVSUBWOD_D_W: |
6421 | 0 | case LoongArch::XVSUBWOD_D_WU: |
6422 | 0 | case LoongArch::XVSUBWOD_H_B: |
6423 | 0 | case LoongArch::XVSUBWOD_H_BU: |
6424 | 0 | case LoongArch::XVSUBWOD_Q_D: |
6425 | 0 | case LoongArch::XVSUBWOD_Q_DU: |
6426 | 0 | case LoongArch::XVSUBWOD_W_H: |
6427 | 0 | case LoongArch::XVSUBWOD_W_HU: |
6428 | 0 | case LoongArch::XVSUB_B: |
6429 | 0 | case LoongArch::XVSUB_D: |
6430 | 0 | case LoongArch::XVSUB_H: |
6431 | 0 | case LoongArch::XVSUB_Q: |
6432 | 0 | case LoongArch::XVSUB_W: |
6433 | 0 | case LoongArch::XVXOR_V: { |
6434 | | // op: xk |
6435 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6436 | 0 | op &= UINT64_C(31); |
6437 | 0 | op <<= 10; |
6438 | 0 | Value |= op; |
6439 | | // op: xj |
6440 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6441 | 0 | op &= UINT64_C(31); |
6442 | 0 | op <<= 5; |
6443 | 0 | Value |= op; |
6444 | | // op: xd |
6445 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6446 | 0 | op &= UINT64_C(31); |
6447 | 0 | Value |= op; |
6448 | 0 | break; |
6449 | 0 | } |
6450 | 0 | case LoongArch::XVFRSTP_B: |
6451 | 0 | case LoongArch::XVFRSTP_H: |
6452 | 0 | case LoongArch::XVMADDWEV_D_W: |
6453 | 0 | case LoongArch::XVMADDWEV_D_WU: |
6454 | 0 | case LoongArch::XVMADDWEV_D_WU_W: |
6455 | 0 | case LoongArch::XVMADDWEV_H_B: |
6456 | 0 | case LoongArch::XVMADDWEV_H_BU: |
6457 | 0 | case LoongArch::XVMADDWEV_H_BU_B: |
6458 | 0 | case LoongArch::XVMADDWEV_Q_D: |
6459 | 0 | case LoongArch::XVMADDWEV_Q_DU: |
6460 | 0 | case LoongArch::XVMADDWEV_Q_DU_D: |
6461 | 0 | case LoongArch::XVMADDWEV_W_H: |
6462 | 0 | case LoongArch::XVMADDWEV_W_HU: |
6463 | 0 | case LoongArch::XVMADDWEV_W_HU_H: |
6464 | 0 | case LoongArch::XVMADDWOD_D_W: |
6465 | 0 | case LoongArch::XVMADDWOD_D_WU: |
6466 | 0 | case LoongArch::XVMADDWOD_D_WU_W: |
6467 | 0 | case LoongArch::XVMADDWOD_H_B: |
6468 | 0 | case LoongArch::XVMADDWOD_H_BU: |
6469 | 0 | case LoongArch::XVMADDWOD_H_BU_B: |
6470 | 0 | case LoongArch::XVMADDWOD_Q_D: |
6471 | 0 | case LoongArch::XVMADDWOD_Q_DU: |
6472 | 0 | case LoongArch::XVMADDWOD_Q_DU_D: |
6473 | 0 | case LoongArch::XVMADDWOD_W_H: |
6474 | 0 | case LoongArch::XVMADDWOD_W_HU: |
6475 | 0 | case LoongArch::XVMADDWOD_W_HU_H: |
6476 | 0 | case LoongArch::XVMADD_B: |
6477 | 0 | case LoongArch::XVMADD_D: |
6478 | 0 | case LoongArch::XVMADD_H: |
6479 | 0 | case LoongArch::XVMADD_W: |
6480 | 0 | case LoongArch::XVMSUB_B: |
6481 | 0 | case LoongArch::XVMSUB_D: |
6482 | 0 | case LoongArch::XVMSUB_H: |
6483 | 0 | case LoongArch::XVMSUB_W: |
6484 | 0 | case LoongArch::XVSHUF_D: |
6485 | 0 | case LoongArch::XVSHUF_H: |
6486 | 0 | case LoongArch::XVSHUF_W: { |
6487 | | // op: xk |
6488 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6489 | 0 | op &= UINT64_C(31); |
6490 | 0 | op <<= 10; |
6491 | 0 | Value |= op; |
6492 | | // op: xj |
6493 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6494 | 0 | op &= UINT64_C(31); |
6495 | 0 | op <<= 5; |
6496 | 0 | Value |= op; |
6497 | | // op: xd |
6498 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6499 | 0 | op &= UINT64_C(31); |
6500 | 0 | Value |= op; |
6501 | 0 | break; |
6502 | 0 | } |
6503 | 0 | default: |
6504 | 0 | std::string msg; |
6505 | 0 | raw_string_ostream Msg(msg); |
6506 | 0 | Msg << "Not supported instr: " << MI; |
6507 | 0 | report_fatal_error(Msg.str().c_str()); |
6508 | 0 | } |
6509 | 0 | return Value; |
6510 | 0 | } |
6511 | | |
6512 | | #ifdef GET_OPERAND_BIT_OFFSET |
6513 | | #undef GET_OPERAND_BIT_OFFSET |
6514 | | |
6515 | | uint32_t LoongArchMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
6516 | | unsigned OpNum, |
6517 | | const MCSubtargetInfo &STI) const { |
6518 | | switch (MI.getOpcode()) { |
6519 | | case LoongArch::ERTN: |
6520 | | case LoongArch::GTLBFLUSH: |
6521 | | case LoongArch::TLBCLR: |
6522 | | case LoongArch::TLBFILL: |
6523 | | case LoongArch::TLBFLUSH: |
6524 | | case LoongArch::TLBRD: |
6525 | | case LoongArch::TLBSRCH: |
6526 | | case LoongArch::TLBWR: |
6527 | | case LoongArch::X86CLRTM: |
6528 | | case LoongArch::X86DECTOP: |
6529 | | case LoongArch::X86INCTOP: |
6530 | | case LoongArch::X86SETTM: { |
6531 | | break; |
6532 | | } |
6533 | | case LoongArch::SET_CFR_FALSE: |
6534 | | case LoongArch::SET_CFR_TRUE: { |
6535 | | switch (OpNum) { |
6536 | | case 0: |
6537 | | // op: cd |
6538 | | return 0; |
6539 | | } |
6540 | | break; |
6541 | | } |
6542 | | case LoongArch::BREAK: |
6543 | | case LoongArch::DBAR: |
6544 | | case LoongArch::DBCL: |
6545 | | case LoongArch::HVCL: |
6546 | | case LoongArch::IBAR: |
6547 | | case LoongArch::IDLE: |
6548 | | case LoongArch::SYSCALL: { |
6549 | | switch (OpNum) { |
6550 | | case 0: |
6551 | | // op: imm15 |
6552 | | return 0; |
6553 | | } |
6554 | | break; |
6555 | | } |
6556 | | case LoongArch::JISCR0: |
6557 | | case LoongArch::JISCR1: { |
6558 | | switch (OpNum) { |
6559 | | case 0: |
6560 | | // op: imm21 |
6561 | | return 0; |
6562 | | } |
6563 | | break; |
6564 | | } |
6565 | | case LoongArch::B: |
6566 | | case LoongArch::BL: { |
6567 | | switch (OpNum) { |
6568 | | case 0: |
6569 | | // op: imm26 |
6570 | | return 0; |
6571 | | } |
6572 | | break; |
6573 | | } |
6574 | | case LoongArch::X86MTTOP: { |
6575 | | switch (OpNum) { |
6576 | | case 0: |
6577 | | // op: ptr |
6578 | | return 5; |
6579 | | } |
6580 | | break; |
6581 | | } |
6582 | | case LoongArch::X86MFTOP: { |
6583 | | switch (OpNum) { |
6584 | | case 0: |
6585 | | // op: rd |
6586 | | return 0; |
6587 | | } |
6588 | | break; |
6589 | | } |
6590 | | case LoongArch::X86DEC_B: |
6591 | | case LoongArch::X86DEC_D: |
6592 | | case LoongArch::X86DEC_H: |
6593 | | case LoongArch::X86DEC_W: |
6594 | | case LoongArch::X86INC_B: |
6595 | | case LoongArch::X86INC_D: |
6596 | | case LoongArch::X86INC_H: |
6597 | | case LoongArch::X86INC_W: { |
6598 | | switch (OpNum) { |
6599 | | case 0: |
6600 | | // op: rj |
6601 | | return 5; |
6602 | | } |
6603 | | break; |
6604 | | } |
6605 | | case LoongArch::INVTLB: { |
6606 | | switch (OpNum) { |
6607 | | case 0: |
6608 | | // op: rk |
6609 | | return 10; |
6610 | | case 1: |
6611 | | // op: rj |
6612 | | return 5; |
6613 | | case 2: |
6614 | | // op: op |
6615 | | return 0; |
6616 | | } |
6617 | | break; |
6618 | | } |
6619 | | case LoongArch::CSRRD: |
6620 | | case LoongArch::GCSRRD: { |
6621 | | switch (OpNum) { |
6622 | | case 1: |
6623 | | // op: csr_num |
6624 | | return 10; |
6625 | | case 0: |
6626 | | // op: rd |
6627 | | return 0; |
6628 | | } |
6629 | | break; |
6630 | | } |
6631 | | case LoongArch::FABS_D: |
6632 | | case LoongArch::FABS_S: |
6633 | | case LoongArch::FCLASS_D: |
6634 | | case LoongArch::FCLASS_S: |
6635 | | case LoongArch::FCVT_D_S: |
6636 | | case LoongArch::FCVT_LD_D: |
6637 | | case LoongArch::FCVT_S_D: |
6638 | | case LoongArch::FCVT_UD_D: |
6639 | | case LoongArch::FFINT_D_L: |
6640 | | case LoongArch::FFINT_D_W: |
6641 | | case LoongArch::FFINT_S_L: |
6642 | | case LoongArch::FFINT_S_W: |
6643 | | case LoongArch::FLOGB_D: |
6644 | | case LoongArch::FLOGB_S: |
6645 | | case LoongArch::FNEG_D: |
6646 | | case LoongArch::FNEG_S: |
6647 | | case LoongArch::FRECIPE_D: |
6648 | | case LoongArch::FRECIPE_S: |
6649 | | case LoongArch::FRECIP_D: |
6650 | | case LoongArch::FRECIP_S: |
6651 | | case LoongArch::FRINT_D: |
6652 | | case LoongArch::FRINT_S: |
6653 | | case LoongArch::FRSQRTE_D: |
6654 | | case LoongArch::FRSQRTE_S: |
6655 | | case LoongArch::FRSQRT_D: |
6656 | | case LoongArch::FRSQRT_S: |
6657 | | case LoongArch::FSQRT_D: |
6658 | | case LoongArch::FSQRT_S: |
6659 | | case LoongArch::FTINTRM_L_D: |
6660 | | case LoongArch::FTINTRM_L_S: |
6661 | | case LoongArch::FTINTRM_W_D: |
6662 | | case LoongArch::FTINTRM_W_S: |
6663 | | case LoongArch::FTINTRNE_L_D: |
6664 | | case LoongArch::FTINTRNE_L_S: |
6665 | | case LoongArch::FTINTRNE_W_D: |
6666 | | case LoongArch::FTINTRNE_W_S: |
6667 | | case LoongArch::FTINTRP_L_D: |
6668 | | case LoongArch::FTINTRP_L_S: |
6669 | | case LoongArch::FTINTRP_W_D: |
6670 | | case LoongArch::FTINTRP_W_S: |
6671 | | case LoongArch::FTINTRZ_L_D: |
6672 | | case LoongArch::FTINTRZ_L_S: |
6673 | | case LoongArch::FTINTRZ_W_D: |
6674 | | case LoongArch::FTINTRZ_W_S: |
6675 | | case LoongArch::FTINT_L_D: |
6676 | | case LoongArch::FTINT_L_S: |
6677 | | case LoongArch::FTINT_W_D: |
6678 | | case LoongArch::FTINT_W_S: { |
6679 | | switch (OpNum) { |
6680 | | case 1: |
6681 | | // op: fj |
6682 | | return 5; |
6683 | | case 0: |
6684 | | // op: fd |
6685 | | return 0; |
6686 | | } |
6687 | | break; |
6688 | | } |
6689 | | case LoongArch::VLDI: { |
6690 | | switch (OpNum) { |
6691 | | case 1: |
6692 | | // op: imm13 |
6693 | | return 5; |
6694 | | case 0: |
6695 | | // op: vd |
6696 | | return 0; |
6697 | | } |
6698 | | break; |
6699 | | } |
6700 | | case LoongArch::XVLDI: { |
6701 | | switch (OpNum) { |
6702 | | case 1: |
6703 | | // op: imm13 |
6704 | | return 5; |
6705 | | case 0: |
6706 | | // op: xd |
6707 | | return 0; |
6708 | | } |
6709 | | break; |
6710 | | } |
6711 | | case LoongArch::LU12I_W: |
6712 | | case LoongArch::PCADDI: |
6713 | | case LoongArch::PCADDU12I: |
6714 | | case LoongArch::PCADDU18I: |
6715 | | case LoongArch::PCALAU12I: { |
6716 | | switch (OpNum) { |
6717 | | case 1: |
6718 | | // op: imm20 |
6719 | | return 5; |
6720 | | case 0: |
6721 | | // op: rd |
6722 | | return 0; |
6723 | | } |
6724 | | break; |
6725 | | } |
6726 | | case LoongArch::BCEQZ: |
6727 | | case LoongArch::BCNEZ: { |
6728 | | switch (OpNum) { |
6729 | | case 1: |
6730 | | // op: imm21 |
6731 | | return 0; |
6732 | | case 0: |
6733 | | // op: cj |
6734 | | return 5; |
6735 | | } |
6736 | | break; |
6737 | | } |
6738 | | case LoongArch::BEQZ: |
6739 | | case LoongArch::BNEZ: { |
6740 | | switch (OpNum) { |
6741 | | case 1: |
6742 | | // op: imm21 |
6743 | | return 0; |
6744 | | case 0: |
6745 | | // op: rj |
6746 | | return 5; |
6747 | | } |
6748 | | break; |
6749 | | } |
6750 | | case LoongArch::X86RCLI_B: |
6751 | | case LoongArch::X86RCRI_B: |
6752 | | case LoongArch::X86ROTLI_B: |
6753 | | case LoongArch::X86ROTRI_B: |
6754 | | case LoongArch::X86SLLI_B: |
6755 | | case LoongArch::X86SRAI_B: |
6756 | | case LoongArch::X86SRLI_B: { |
6757 | | switch (OpNum) { |
6758 | | case 1: |
6759 | | // op: imm3 |
6760 | | return 10; |
6761 | | case 0: |
6762 | | // op: rj |
6763 | | return 5; |
6764 | | } |
6765 | | break; |
6766 | | } |
6767 | | case LoongArch::SETARMJ: |
6768 | | case LoongArch::SETX86J: { |
6769 | | switch (OpNum) { |
6770 | | case 1: |
6771 | | // op: imm4 |
6772 | | return 10; |
6773 | | case 0: |
6774 | | // op: rd |
6775 | | return 0; |
6776 | | } |
6777 | | break; |
6778 | | } |
6779 | | case LoongArch::ARMMOV_D: |
6780 | | case LoongArch::ARMMOV_W: |
6781 | | case LoongArch::ARMNOT_W: |
6782 | | case LoongArch::ARMRRX_W: |
6783 | | case LoongArch::X86RCLI_H: |
6784 | | case LoongArch::X86RCRI_H: |
6785 | | case LoongArch::X86ROTLI_H: |
6786 | | case LoongArch::X86ROTRI_H: |
6787 | | case LoongArch::X86SLLI_H: |
6788 | | case LoongArch::X86SRAI_H: |
6789 | | case LoongArch::X86SRLI_H: { |
6790 | | switch (OpNum) { |
6791 | | case 1: |
6792 | | // op: imm4 |
6793 | | return 10; |
6794 | | case 0: |
6795 | | // op: rj |
6796 | | return 5; |
6797 | | } |
6798 | | break; |
6799 | | } |
6800 | | case LoongArch::ARMROTRI_W: |
6801 | | case LoongArch::ARMSLLI_W: |
6802 | | case LoongArch::ARMSRAI_W: |
6803 | | case LoongArch::ARMSRLI_W: { |
6804 | | switch (OpNum) { |
6805 | | case 1: |
6806 | | // op: imm5 |
6807 | | return 10; |
6808 | | case 0: |
6809 | | // op: rj |
6810 | | return 5; |
6811 | | case 2: |
6812 | | // op: imm4 |
6813 | | return 0; |
6814 | | } |
6815 | | break; |
6816 | | } |
6817 | | case LoongArch::X86RCLI_W: |
6818 | | case LoongArch::X86RCRI_W: |
6819 | | case LoongArch::X86ROTLI_W: |
6820 | | case LoongArch::X86ROTRI_W: |
6821 | | case LoongArch::X86SLLI_W: |
6822 | | case LoongArch::X86SRAI_W: |
6823 | | case LoongArch::X86SRLI_W: { |
6824 | | switch (OpNum) { |
6825 | | case 1: |
6826 | | // op: imm5 |
6827 | | return 10; |
6828 | | case 0: |
6829 | | // op: rj |
6830 | | return 5; |
6831 | | } |
6832 | | break; |
6833 | | } |
6834 | | case LoongArch::X86RCLI_D: |
6835 | | case LoongArch::X86RCRI_D: |
6836 | | case LoongArch::X86ROTLI_D: |
6837 | | case LoongArch::X86ROTRI_D: |
6838 | | case LoongArch::X86SLLI_D: |
6839 | | case LoongArch::X86SRAI_D: |
6840 | | case LoongArch::X86SRLI_D: { |
6841 | | switch (OpNum) { |
6842 | | case 1: |
6843 | | // op: imm6 |
6844 | | return 10; |
6845 | | case 0: |
6846 | | // op: rj |
6847 | | return 5; |
6848 | | } |
6849 | | break; |
6850 | | } |
6851 | | case LoongArch::ARMMFFLAG: |
6852 | | case LoongArch::ARMMTFLAG: |
6853 | | case LoongArch::X86MFFLAG: |
6854 | | case LoongArch::X86MTFLAG: { |
6855 | | switch (OpNum) { |
6856 | | case 1: |
6857 | | // op: imm8 |
6858 | | return 10; |
6859 | | case 0: |
6860 | | // op: rd |
6861 | | return 0; |
6862 | | } |
6863 | | break; |
6864 | | } |
6865 | | case LoongArch::BITREV_4B: |
6866 | | case LoongArch::BITREV_8B: |
6867 | | case LoongArch::BITREV_D: |
6868 | | case LoongArch::BITREV_W: |
6869 | | case LoongArch::CLO_D: |
6870 | | case LoongArch::CLO_W: |
6871 | | case LoongArch::CLZ_D: |
6872 | | case LoongArch::CLZ_W: |
6873 | | case LoongArch::CPUCFG: |
6874 | | case LoongArch::CTO_D: |
6875 | | case LoongArch::CTO_W: |
6876 | | case LoongArch::CTZ_D: |
6877 | | case LoongArch::CTZ_W: |
6878 | | case LoongArch::EXT_W_B: |
6879 | | case LoongArch::EXT_W_H: |
6880 | | case LoongArch::IOCSRRD_B: |
6881 | | case LoongArch::IOCSRRD_D: |
6882 | | case LoongArch::IOCSRRD_H: |
6883 | | case LoongArch::IOCSRRD_W: |
6884 | | case LoongArch::IOCSRWR_B: |
6885 | | case LoongArch::IOCSRWR_D: |
6886 | | case LoongArch::IOCSRWR_H: |
6887 | | case LoongArch::IOCSRWR_W: |
6888 | | case LoongArch::LLACQ_D: |
6889 | | case LoongArch::LLACQ_W: |
6890 | | case LoongArch::RDTIMEH_W: |
6891 | | case LoongArch::RDTIMEL_W: |
6892 | | case LoongArch::RDTIME_D: |
6893 | | case LoongArch::REVB_2H: |
6894 | | case LoongArch::REVB_2W: |
6895 | | case LoongArch::REVB_4H: |
6896 | | case LoongArch::REVB_D: |
6897 | | case LoongArch::REVH_2W: |
6898 | | case LoongArch::REVH_D: |
6899 | | case LoongArch::SETX86LOOPE: |
6900 | | case LoongArch::SETX86LOOPNE: { |
6901 | | switch (OpNum) { |
6902 | | case 1: |
6903 | | // op: rj |
6904 | | return 5; |
6905 | | case 0: |
6906 | | // op: rd |
6907 | | return 0; |
6908 | | } |
6909 | | break; |
6910 | | } |
6911 | | case LoongArch::MOVGR2SCR: { |
6912 | | switch (OpNum) { |
6913 | | case 1: |
6914 | | // op: rj |
6915 | | return 5; |
6916 | | case 0: |
6917 | | // op: sd |
6918 | | return 0; |
6919 | | } |
6920 | | break; |
6921 | | } |
6922 | | case LoongArch::VREPLGR2VR_B: |
6923 | | case LoongArch::VREPLGR2VR_D: |
6924 | | case LoongArch::VREPLGR2VR_H: |
6925 | | case LoongArch::VREPLGR2VR_W: { |
6926 | | switch (OpNum) { |
6927 | | case 1: |
6928 | | // op: rj |
6929 | | return 5; |
6930 | | case 0: |
6931 | | // op: vd |
6932 | | return 0; |
6933 | | } |
6934 | | break; |
6935 | | } |
6936 | | case LoongArch::XVREPLGR2VR_B: |
6937 | | case LoongArch::XVREPLGR2VR_D: |
6938 | | case LoongArch::XVREPLGR2VR_H: |
6939 | | case LoongArch::XVREPLGR2VR_W: { |
6940 | | switch (OpNum) { |
6941 | | case 1: |
6942 | | // op: rj |
6943 | | return 5; |
6944 | | case 0: |
6945 | | // op: xd |
6946 | | return 0; |
6947 | | } |
6948 | | break; |
6949 | | } |
6950 | | case LoongArch::ASRTGT_D: |
6951 | | case LoongArch::ASRTLE_D: |
6952 | | case LoongArch::X86ADC_B: |
6953 | | case LoongArch::X86ADC_D: |
6954 | | case LoongArch::X86ADC_H: |
6955 | | case LoongArch::X86ADC_W: |
6956 | | case LoongArch::X86ADD_B: |
6957 | | case LoongArch::X86ADD_D: |
6958 | | case LoongArch::X86ADD_DU: |
6959 | | case LoongArch::X86ADD_H: |
6960 | | case LoongArch::X86ADD_W: |
6961 | | case LoongArch::X86ADD_WU: |
6962 | | case LoongArch::X86AND_B: |
6963 | | case LoongArch::X86AND_D: |
6964 | | case LoongArch::X86AND_H: |
6965 | | case LoongArch::X86AND_W: |
6966 | | case LoongArch::X86MUL_B: |
6967 | | case LoongArch::X86MUL_BU: |
6968 | | case LoongArch::X86MUL_D: |
6969 | | case LoongArch::X86MUL_DU: |
6970 | | case LoongArch::X86MUL_H: |
6971 | | case LoongArch::X86MUL_HU: |
6972 | | case LoongArch::X86MUL_W: |
6973 | | case LoongArch::X86MUL_WU: |
6974 | | case LoongArch::X86OR_B: |
6975 | | case LoongArch::X86OR_D: |
6976 | | case LoongArch::X86OR_H: |
6977 | | case LoongArch::X86OR_W: |
6978 | | case LoongArch::X86RCL_B: |
6979 | | case LoongArch::X86RCL_D: |
6980 | | case LoongArch::X86RCL_H: |
6981 | | case LoongArch::X86RCL_W: |
6982 | | case LoongArch::X86RCR_B: |
6983 | | case LoongArch::X86RCR_D: |
6984 | | case LoongArch::X86RCR_H: |
6985 | | case LoongArch::X86RCR_W: |
6986 | | case LoongArch::X86ROTL_B: |
6987 | | case LoongArch::X86ROTL_D: |
6988 | | case LoongArch::X86ROTL_H: |
6989 | | case LoongArch::X86ROTL_W: |
6990 | | case LoongArch::X86ROTR_B: |
6991 | | case LoongArch::X86ROTR_D: |
6992 | | case LoongArch::X86ROTR_H: |
6993 | | case LoongArch::X86ROTR_W: |
6994 | | case LoongArch::X86SBC_B: |
6995 | | case LoongArch::X86SBC_D: |
6996 | | case LoongArch::X86SBC_H: |
6997 | | case LoongArch::X86SBC_W: |
6998 | | case LoongArch::X86SLL_B: |
6999 | | case LoongArch::X86SLL_D: |
7000 | | case LoongArch::X86SLL_H: |
7001 | | case LoongArch::X86SLL_W: |
7002 | | case LoongArch::X86SRA_B: |
7003 | | case LoongArch::X86SRA_D: |
7004 | | case LoongArch::X86SRA_H: |
7005 | | case LoongArch::X86SRA_W: |
7006 | | case LoongArch::X86SRL_B: |
7007 | | case LoongArch::X86SRL_D: |
7008 | | case LoongArch::X86SRL_H: |
7009 | | case LoongArch::X86SRL_W: |
7010 | | case LoongArch::X86SUB_B: |
7011 | | case LoongArch::X86SUB_D: |
7012 | | case LoongArch::X86SUB_DU: |
7013 | | case LoongArch::X86SUB_H: |
7014 | | case LoongArch::X86SUB_W: |
7015 | | case LoongArch::X86SUB_WU: |
7016 | | case LoongArch::X86XOR_B: |
7017 | | case LoongArch::X86XOR_D: |
7018 | | case LoongArch::X86XOR_H: |
7019 | | case LoongArch::X86XOR_W: { |
7020 | | switch (OpNum) { |
7021 | | case 1: |
7022 | | // op: rk |
7023 | | return 10; |
7024 | | case 0: |
7025 | | // op: rj |
7026 | | return 5; |
7027 | | } |
7028 | | break; |
7029 | | } |
7030 | | case LoongArch::AMADD_B: |
7031 | | case LoongArch::AMADD_D: |
7032 | | case LoongArch::AMADD_H: |
7033 | | case LoongArch::AMADD_W: |
7034 | | case LoongArch::AMADD__DB_B: |
7035 | | case LoongArch::AMADD__DB_D: |
7036 | | case LoongArch::AMADD__DB_H: |
7037 | | case LoongArch::AMADD__DB_W: |
7038 | | case LoongArch::AMAND_D: |
7039 | | case LoongArch::AMAND_W: |
7040 | | case LoongArch::AMAND__DB_D: |
7041 | | case LoongArch::AMAND__DB_W: |
7042 | | case LoongArch::AMCAS_B: |
7043 | | case LoongArch::AMCAS_D: |
7044 | | case LoongArch::AMCAS_H: |
7045 | | case LoongArch::AMCAS_W: |
7046 | | case LoongArch::AMCAS__DB_B: |
7047 | | case LoongArch::AMCAS__DB_D: |
7048 | | case LoongArch::AMCAS__DB_H: |
7049 | | case LoongArch::AMCAS__DB_W: |
7050 | | case LoongArch::AMMAX_D: |
7051 | | case LoongArch::AMMAX_DU: |
7052 | | case LoongArch::AMMAX_W: |
7053 | | case LoongArch::AMMAX_WU: |
7054 | | case LoongArch::AMMAX__DB_D: |
7055 | | case LoongArch::AMMAX__DB_DU: |
7056 | | case LoongArch::AMMAX__DB_W: |
7057 | | case LoongArch::AMMAX__DB_WU: |
7058 | | case LoongArch::AMMIN_D: |
7059 | | case LoongArch::AMMIN_DU: |
7060 | | case LoongArch::AMMIN_W: |
7061 | | case LoongArch::AMMIN_WU: |
7062 | | case LoongArch::AMMIN__DB_D: |
7063 | | case LoongArch::AMMIN__DB_DU: |
7064 | | case LoongArch::AMMIN__DB_W: |
7065 | | case LoongArch::AMMIN__DB_WU: |
7066 | | case LoongArch::AMOR_D: |
7067 | | case LoongArch::AMOR_W: |
7068 | | case LoongArch::AMOR__DB_D: |
7069 | | case LoongArch::AMOR__DB_W: |
7070 | | case LoongArch::AMSWAP_B: |
7071 | | case LoongArch::AMSWAP_D: |
7072 | | case LoongArch::AMSWAP_H: |
7073 | | case LoongArch::AMSWAP_W: |
7074 | | case LoongArch::AMSWAP__DB_B: |
7075 | | case LoongArch::AMSWAP__DB_D: |
7076 | | case LoongArch::AMSWAP__DB_H: |
7077 | | case LoongArch::AMSWAP__DB_W: |
7078 | | case LoongArch::AMXOR_D: |
7079 | | case LoongArch::AMXOR_W: |
7080 | | case LoongArch::AMXOR__DB_D: |
7081 | | case LoongArch::AMXOR__DB_W: { |
7082 | | switch (OpNum) { |
7083 | | case 1: |
7084 | | // op: rk |
7085 | | return 10; |
7086 | | case 2: |
7087 | | // op: rj |
7088 | | return 5; |
7089 | | case 0: |
7090 | | // op: rd |
7091 | | return 0; |
7092 | | } |
7093 | | break; |
7094 | | } |
7095 | | case LoongArch::LDPTE: { |
7096 | | switch (OpNum) { |
7097 | | case 1: |
7098 | | // op: seq |
7099 | | return 10; |
7100 | | case 0: |
7101 | | // op: rj |
7102 | | return 5; |
7103 | | } |
7104 | | break; |
7105 | | } |
7106 | | case LoongArch::MOVSCR2GR: { |
7107 | | switch (OpNum) { |
7108 | | case 1: |
7109 | | // op: sj |
7110 | | return 5; |
7111 | | case 0: |
7112 | | // op: rd |
7113 | | return 0; |
7114 | | } |
7115 | | break; |
7116 | | } |
7117 | | case LoongArch::FMOV_D: |
7118 | | case LoongArch::FMOV_S: |
7119 | | case LoongArch::MOVCF2FR_xS: |
7120 | | case LoongArch::MOVCF2GR: |
7121 | | case LoongArch::MOVFCSR2GR: |
7122 | | case LoongArch::MOVFR2CF_xS: |
7123 | | case LoongArch::MOVFR2GR_D: |
7124 | | case LoongArch::MOVFR2GR_S: |
7125 | | case LoongArch::MOVFR2GR_S_64: |
7126 | | case LoongArch::MOVFRH2GR_S: |
7127 | | case LoongArch::MOVGR2CF: |
7128 | | case LoongArch::MOVGR2FCSR: |
7129 | | case LoongArch::MOVGR2FR_D: |
7130 | | case LoongArch::MOVGR2FR_W: |
7131 | | case LoongArch::MOVGR2FR_W_64: { |
7132 | | switch (OpNum) { |
7133 | | case 1: |
7134 | | // op: src |
7135 | | return 5; |
7136 | | case 0: |
7137 | | // op: dst |
7138 | | return 0; |
7139 | | } |
7140 | | break; |
7141 | | } |
7142 | | case LoongArch::VSETALLNEZ_B: |
7143 | | case LoongArch::VSETALLNEZ_D: |
7144 | | case LoongArch::VSETALLNEZ_H: |
7145 | | case LoongArch::VSETALLNEZ_W: |
7146 | | case LoongArch::VSETANYEQZ_B: |
7147 | | case LoongArch::VSETANYEQZ_D: |
7148 | | case LoongArch::VSETANYEQZ_H: |
7149 | | case LoongArch::VSETANYEQZ_W: |
7150 | | case LoongArch::VSETEQZ_V: |
7151 | | case LoongArch::VSETNEZ_V: { |
7152 | | switch (OpNum) { |
7153 | | case 1: |
7154 | | // op: vj |
7155 | | return 5; |
7156 | | case 0: |
7157 | | // op: cd |
7158 | | return 0; |
7159 | | } |
7160 | | break; |
7161 | | } |
7162 | | case LoongArch::VCLO_B: |
7163 | | case LoongArch::VCLO_D: |
7164 | | case LoongArch::VCLO_H: |
7165 | | case LoongArch::VCLO_W: |
7166 | | case LoongArch::VCLZ_B: |
7167 | | case LoongArch::VCLZ_D: |
7168 | | case LoongArch::VCLZ_H: |
7169 | | case LoongArch::VCLZ_W: |
7170 | | case LoongArch::VEXTH_DU_WU: |
7171 | | case LoongArch::VEXTH_D_W: |
7172 | | case LoongArch::VEXTH_HU_BU: |
7173 | | case LoongArch::VEXTH_H_B: |
7174 | | case LoongArch::VEXTH_QU_DU: |
7175 | | case LoongArch::VEXTH_Q_D: |
7176 | | case LoongArch::VEXTH_WU_HU: |
7177 | | case LoongArch::VEXTH_W_H: |
7178 | | case LoongArch::VEXTL_QU_DU: |
7179 | | case LoongArch::VEXTL_Q_D: |
7180 | | case LoongArch::VFCLASS_D: |
7181 | | case LoongArch::VFCLASS_S: |
7182 | | case LoongArch::VFCVTH_D_S: |
7183 | | case LoongArch::VFCVTH_S_H: |
7184 | | case LoongArch::VFCVTL_D_S: |
7185 | | case LoongArch::VFCVTL_S_H: |
7186 | | case LoongArch::VFFINTH_D_W: |
7187 | | case LoongArch::VFFINTL_D_W: |
7188 | | case LoongArch::VFFINT_D_L: |
7189 | | case LoongArch::VFFINT_D_LU: |
7190 | | case LoongArch::VFFINT_S_W: |
7191 | | case LoongArch::VFFINT_S_WU: |
7192 | | case LoongArch::VFLOGB_D: |
7193 | | case LoongArch::VFLOGB_S: |
7194 | | case LoongArch::VFRECIPE_D: |
7195 | | case LoongArch::VFRECIPE_S: |
7196 | | case LoongArch::VFRECIP_D: |
7197 | | case LoongArch::VFRECIP_S: |
7198 | | case LoongArch::VFRINTRM_D: |
7199 | | case LoongArch::VFRINTRM_S: |
7200 | | case LoongArch::VFRINTRNE_D: |
7201 | | case LoongArch::VFRINTRNE_S: |
7202 | | case LoongArch::VFRINTRP_D: |
7203 | | case LoongArch::VFRINTRP_S: |
7204 | | case LoongArch::VFRINTRZ_D: |
7205 | | case LoongArch::VFRINTRZ_S: |
7206 | | case LoongArch::VFRINT_D: |
7207 | | case LoongArch::VFRINT_S: |
7208 | | case LoongArch::VFRSQRTE_D: |
7209 | | case LoongArch::VFRSQRTE_S: |
7210 | | case LoongArch::VFRSQRT_D: |
7211 | | case LoongArch::VFRSQRT_S: |
7212 | | case LoongArch::VFSQRT_D: |
7213 | | case LoongArch::VFSQRT_S: |
7214 | | case LoongArch::VFTINTH_L_S: |
7215 | | case LoongArch::VFTINTL_L_S: |
7216 | | case LoongArch::VFTINTRMH_L_S: |
7217 | | case LoongArch::VFTINTRML_L_S: |
7218 | | case LoongArch::VFTINTRM_L_D: |
7219 | | case LoongArch::VFTINTRM_W_S: |
7220 | | case LoongArch::VFTINTRNEH_L_S: |
7221 | | case LoongArch::VFTINTRNEL_L_S: |
7222 | | case LoongArch::VFTINTRNE_L_D: |
7223 | | case LoongArch::VFTINTRNE_W_S: |
7224 | | case LoongArch::VFTINTRPH_L_S: |
7225 | | case LoongArch::VFTINTRPL_L_S: |
7226 | | case LoongArch::VFTINTRP_L_D: |
7227 | | case LoongArch::VFTINTRP_W_S: |
7228 | | case LoongArch::VFTINTRZH_L_S: |
7229 | | case LoongArch::VFTINTRZL_L_S: |
7230 | | case LoongArch::VFTINTRZ_LU_D: |
7231 | | case LoongArch::VFTINTRZ_L_D: |
7232 | | case LoongArch::VFTINTRZ_WU_S: |
7233 | | case LoongArch::VFTINTRZ_W_S: |
7234 | | case LoongArch::VFTINT_LU_D: |
7235 | | case LoongArch::VFTINT_L_D: |
7236 | | case LoongArch::VFTINT_WU_S: |
7237 | | case LoongArch::VFTINT_W_S: |
7238 | | case LoongArch::VMSKGEZ_B: |
7239 | | case LoongArch::VMSKLTZ_B: |
7240 | | case LoongArch::VMSKLTZ_D: |
7241 | | case LoongArch::VMSKLTZ_H: |
7242 | | case LoongArch::VMSKLTZ_W: |
7243 | | case LoongArch::VMSKNZ_B: |
7244 | | case LoongArch::VNEG_B: |
7245 | | case LoongArch::VNEG_D: |
7246 | | case LoongArch::VNEG_H: |
7247 | | case LoongArch::VNEG_W: |
7248 | | case LoongArch::VPCNT_B: |
7249 | | case LoongArch::VPCNT_D: |
7250 | | case LoongArch::VPCNT_H: |
7251 | | case LoongArch::VPCNT_W: { |
7252 | | switch (OpNum) { |
7253 | | case 1: |
7254 | | // op: vj |
7255 | | return 5; |
7256 | | case 0: |
7257 | | // op: vd |
7258 | | return 0; |
7259 | | } |
7260 | | break; |
7261 | | } |
7262 | | case LoongArch::XVSETALLNEZ_B: |
7263 | | case LoongArch::XVSETALLNEZ_D: |
7264 | | case LoongArch::XVSETALLNEZ_H: |
7265 | | case LoongArch::XVSETALLNEZ_W: |
7266 | | case LoongArch::XVSETANYEQZ_B: |
7267 | | case LoongArch::XVSETANYEQZ_D: |
7268 | | case LoongArch::XVSETANYEQZ_H: |
7269 | | case LoongArch::XVSETANYEQZ_W: |
7270 | | case LoongArch::XVSETEQZ_V: |
7271 | | case LoongArch::XVSETNEZ_V: { |
7272 | | switch (OpNum) { |
7273 | | case 1: |
7274 | | // op: xj |
7275 | | return 5; |
7276 | | case 0: |
7277 | | // op: cd |
7278 | | return 0; |
7279 | | } |
7280 | | break; |
7281 | | } |
7282 | | case LoongArch::VEXT2XV_DU_BU: |
7283 | | case LoongArch::VEXT2XV_DU_HU: |
7284 | | case LoongArch::VEXT2XV_DU_WU: |
7285 | | case LoongArch::VEXT2XV_D_B: |
7286 | | case LoongArch::VEXT2XV_D_H: |
7287 | | case LoongArch::VEXT2XV_D_W: |
7288 | | case LoongArch::VEXT2XV_HU_BU: |
7289 | | case LoongArch::VEXT2XV_H_B: |
7290 | | case LoongArch::VEXT2XV_WU_BU: |
7291 | | case LoongArch::VEXT2XV_WU_HU: |
7292 | | case LoongArch::VEXT2XV_W_B: |
7293 | | case LoongArch::VEXT2XV_W_H: |
7294 | | case LoongArch::XVCLO_B: |
7295 | | case LoongArch::XVCLO_D: |
7296 | | case LoongArch::XVCLO_H: |
7297 | | case LoongArch::XVCLO_W: |
7298 | | case LoongArch::XVCLZ_B: |
7299 | | case LoongArch::XVCLZ_D: |
7300 | | case LoongArch::XVCLZ_H: |
7301 | | case LoongArch::XVCLZ_W: |
7302 | | case LoongArch::XVEXTH_DU_WU: |
7303 | | case LoongArch::XVEXTH_D_W: |
7304 | | case LoongArch::XVEXTH_HU_BU: |
7305 | | case LoongArch::XVEXTH_H_B: |
7306 | | case LoongArch::XVEXTH_QU_DU: |
7307 | | case LoongArch::XVEXTH_Q_D: |
7308 | | case LoongArch::XVEXTH_WU_HU: |
7309 | | case LoongArch::XVEXTH_W_H: |
7310 | | case LoongArch::XVEXTL_QU_DU: |
7311 | | case LoongArch::XVEXTL_Q_D: |
7312 | | case LoongArch::XVFCLASS_D: |
7313 | | case LoongArch::XVFCLASS_S: |
7314 | | case LoongArch::XVFCVTH_D_S: |
7315 | | case LoongArch::XVFCVTH_S_H: |
7316 | | case LoongArch::XVFCVTL_D_S: |
7317 | | case LoongArch::XVFCVTL_S_H: |
7318 | | case LoongArch::XVFFINTH_D_W: |
7319 | | case LoongArch::XVFFINTL_D_W: |
7320 | | case LoongArch::XVFFINT_D_L: |
7321 | | case LoongArch::XVFFINT_D_LU: |
7322 | | case LoongArch::XVFFINT_S_W: |
7323 | | case LoongArch::XVFFINT_S_WU: |
7324 | | case LoongArch::XVFLOGB_D: |
7325 | | case LoongArch::XVFLOGB_S: |
7326 | | case LoongArch::XVFRECIPE_D: |
7327 | | case LoongArch::XVFRECIPE_S: |
7328 | | case LoongArch::XVFRECIP_D: |
7329 | | case LoongArch::XVFRECIP_S: |
7330 | | case LoongArch::XVFRINTRM_D: |
7331 | | case LoongArch::XVFRINTRM_S: |
7332 | | case LoongArch::XVFRINTRNE_D: |
7333 | | case LoongArch::XVFRINTRNE_S: |
7334 | | case LoongArch::XVFRINTRP_D: |
7335 | | case LoongArch::XVFRINTRP_S: |
7336 | | case LoongArch::XVFRINTRZ_D: |
7337 | | case LoongArch::XVFRINTRZ_S: |
7338 | | case LoongArch::XVFRINT_D: |
7339 | | case LoongArch::XVFRINT_S: |
7340 | | case LoongArch::XVFRSQRTE_D: |
7341 | | case LoongArch::XVFRSQRTE_S: |
7342 | | case LoongArch::XVFRSQRT_D: |
7343 | | case LoongArch::XVFRSQRT_S: |
7344 | | case LoongArch::XVFSQRT_D: |
7345 | | case LoongArch::XVFSQRT_S: |
7346 | | case LoongArch::XVFTINTH_L_S: |
7347 | | case LoongArch::XVFTINTL_L_S: |
7348 | | case LoongArch::XVFTINTRMH_L_S: |
7349 | | case LoongArch::XVFTINTRML_L_S: |
7350 | | case LoongArch::XVFTINTRM_L_D: |
7351 | | case LoongArch::XVFTINTRM_W_S: |
7352 | | case LoongArch::XVFTINTRNEH_L_S: |
7353 | | case LoongArch::XVFTINTRNEL_L_S: |
7354 | | case LoongArch::XVFTINTRNE_L_D: |
7355 | | case LoongArch::XVFTINTRNE_W_S: |
7356 | | case LoongArch::XVFTINTRPH_L_S: |
7357 | | case LoongArch::XVFTINTRPL_L_S: |
7358 | | case LoongArch::XVFTINTRP_L_D: |
7359 | | case LoongArch::XVFTINTRP_W_S: |
7360 | | case LoongArch::XVFTINTRZH_L_S: |
7361 | | case LoongArch::XVFTINTRZL_L_S: |
7362 | | case LoongArch::XVFTINTRZ_LU_D: |
7363 | | case LoongArch::XVFTINTRZ_L_D: |
7364 | | case LoongArch::XVFTINTRZ_WU_S: |
7365 | | case LoongArch::XVFTINTRZ_W_S: |
7366 | | case LoongArch::XVFTINT_LU_D: |
7367 | | case LoongArch::XVFTINT_L_D: |
7368 | | case LoongArch::XVFTINT_WU_S: |
7369 | | case LoongArch::XVFTINT_W_S: |
7370 | | case LoongArch::XVMSKGEZ_B: |
7371 | | case LoongArch::XVMSKLTZ_B: |
7372 | | case LoongArch::XVMSKLTZ_D: |
7373 | | case LoongArch::XVMSKLTZ_H: |
7374 | | case LoongArch::XVMSKLTZ_W: |
7375 | | case LoongArch::XVMSKNZ_B: |
7376 | | case LoongArch::XVNEG_B: |
7377 | | case LoongArch::XVNEG_D: |
7378 | | case LoongArch::XVNEG_H: |
7379 | | case LoongArch::XVNEG_W: |
7380 | | case LoongArch::XVPCNT_B: |
7381 | | case LoongArch::XVPCNT_D: |
7382 | | case LoongArch::XVPCNT_H: |
7383 | | case LoongArch::XVPCNT_W: |
7384 | | case LoongArch::XVREPLVE0_B: |
7385 | | case LoongArch::XVREPLVE0_D: |
7386 | | case LoongArch::XVREPLVE0_H: |
7387 | | case LoongArch::XVREPLVE0_Q: |
7388 | | case LoongArch::XVREPLVE0_W: { |
7389 | | switch (OpNum) { |
7390 | | case 1: |
7391 | | // op: xj |
7392 | | return 5; |
7393 | | case 0: |
7394 | | // op: xd |
7395 | | return 0; |
7396 | | } |
7397 | | break; |
7398 | | } |
7399 | | case LoongArch::CSRWR: |
7400 | | case LoongArch::GCSRWR: { |
7401 | | switch (OpNum) { |
7402 | | case 2: |
7403 | | // op: csr_num |
7404 | | return 10; |
7405 | | case 1: |
7406 | | // op: rd |
7407 | | return 0; |
7408 | | } |
7409 | | break; |
7410 | | } |
7411 | | case LoongArch::FCMP_CAF_D: |
7412 | | case LoongArch::FCMP_CAF_S: |
7413 | | case LoongArch::FCMP_CEQ_D: |
7414 | | case LoongArch::FCMP_CEQ_S: |
7415 | | case LoongArch::FCMP_CLE_D: |
7416 | | case LoongArch::FCMP_CLE_S: |
7417 | | case LoongArch::FCMP_CLT_D: |
7418 | | case LoongArch::FCMP_CLT_S: |
7419 | | case LoongArch::FCMP_CNE_D: |
7420 | | case LoongArch::FCMP_CNE_S: |
7421 | | case LoongArch::FCMP_COR_D: |
7422 | | case LoongArch::FCMP_COR_S: |
7423 | | case LoongArch::FCMP_CUEQ_D: |
7424 | | case LoongArch::FCMP_CUEQ_S: |
7425 | | case LoongArch::FCMP_CULE_D: |
7426 | | case LoongArch::FCMP_CULE_S: |
7427 | | case LoongArch::FCMP_CULT_D: |
7428 | | case LoongArch::FCMP_CULT_S: |
7429 | | case LoongArch::FCMP_CUNE_D: |
7430 | | case LoongArch::FCMP_CUNE_S: |
7431 | | case LoongArch::FCMP_CUN_D: |
7432 | | case LoongArch::FCMP_CUN_S: |
7433 | | case LoongArch::FCMP_SAF_D: |
7434 | | case LoongArch::FCMP_SAF_S: |
7435 | | case LoongArch::FCMP_SEQ_D: |
7436 | | case LoongArch::FCMP_SEQ_S: |
7437 | | case LoongArch::FCMP_SLE_D: |
7438 | | case LoongArch::FCMP_SLE_S: |
7439 | | case LoongArch::FCMP_SLT_D: |
7440 | | case LoongArch::FCMP_SLT_S: |
7441 | | case LoongArch::FCMP_SNE_D: |
7442 | | case LoongArch::FCMP_SNE_S: |
7443 | | case LoongArch::FCMP_SOR_D: |
7444 | | case LoongArch::FCMP_SOR_S: |
7445 | | case LoongArch::FCMP_SUEQ_D: |
7446 | | case LoongArch::FCMP_SUEQ_S: |
7447 | | case LoongArch::FCMP_SULE_D: |
7448 | | case LoongArch::FCMP_SULE_S: |
7449 | | case LoongArch::FCMP_SULT_D: |
7450 | | case LoongArch::FCMP_SULT_S: |
7451 | | case LoongArch::FCMP_SUNE_D: |
7452 | | case LoongArch::FCMP_SUNE_S: |
7453 | | case LoongArch::FCMP_SUN_D: |
7454 | | case LoongArch::FCMP_SUN_S: { |
7455 | | switch (OpNum) { |
7456 | | case 2: |
7457 | | // op: fk |
7458 | | return 10; |
7459 | | case 1: |
7460 | | // op: fj |
7461 | | return 5; |
7462 | | case 0: |
7463 | | // op: cd |
7464 | | return 0; |
7465 | | } |
7466 | | break; |
7467 | | } |
7468 | | case LoongArch::FADD_D: |
7469 | | case LoongArch::FADD_S: |
7470 | | case LoongArch::FCOPYSIGN_D: |
7471 | | case LoongArch::FCOPYSIGN_S: |
7472 | | case LoongArch::FCVT_D_LD: |
7473 | | case LoongArch::FDIV_D: |
7474 | | case LoongArch::FDIV_S: |
7475 | | case LoongArch::FMAXA_D: |
7476 | | case LoongArch::FMAXA_S: |
7477 | | case LoongArch::FMAX_D: |
7478 | | case LoongArch::FMAX_S: |
7479 | | case LoongArch::FMINA_D: |
7480 | | case LoongArch::FMINA_S: |
7481 | | case LoongArch::FMIN_D: |
7482 | | case LoongArch::FMIN_S: |
7483 | | case LoongArch::FMUL_D: |
7484 | | case LoongArch::FMUL_S: |
7485 | | case LoongArch::FSCALEB_D: |
7486 | | case LoongArch::FSCALEB_S: |
7487 | | case LoongArch::FSUB_D: |
7488 | | case LoongArch::FSUB_S: { |
7489 | | switch (OpNum) { |
7490 | | case 2: |
7491 | | // op: fk |
7492 | | return 10; |
7493 | | case 1: |
7494 | | // op: fj |
7495 | | return 5; |
7496 | | case 0: |
7497 | | // op: fd |
7498 | | return 0; |
7499 | | } |
7500 | | break; |
7501 | | } |
7502 | | case LoongArch::VPICKVE2GR_D: |
7503 | | case LoongArch::VPICKVE2GR_DU: { |
7504 | | switch (OpNum) { |
7505 | | case 2: |
7506 | | // op: imm1 |
7507 | | return 10; |
7508 | | case 1: |
7509 | | // op: vj |
7510 | | return 5; |
7511 | | case 0: |
7512 | | // op: rd |
7513 | | return 0; |
7514 | | } |
7515 | | break; |
7516 | | } |
7517 | | case LoongArch::VREPLVEI_D: { |
7518 | | switch (OpNum) { |
7519 | | case 2: |
7520 | | // op: imm1 |
7521 | | return 10; |
7522 | | case 1: |
7523 | | // op: vj |
7524 | | return 5; |
7525 | | case 0: |
7526 | | // op: vd |
7527 | | return 0; |
7528 | | } |
7529 | | break; |
7530 | | } |
7531 | | case LoongArch::XVREPL128VEI_D: { |
7532 | | switch (OpNum) { |
7533 | | case 2: |
7534 | | // op: imm1 |
7535 | | return 10; |
7536 | | case 1: |
7537 | | // op: xj |
7538 | | return 5; |
7539 | | case 0: |
7540 | | // op: xd |
7541 | | return 0; |
7542 | | } |
7543 | | break; |
7544 | | } |
7545 | | case LoongArch::VLDREPL_W: { |
7546 | | switch (OpNum) { |
7547 | | case 2: |
7548 | | // op: imm10 |
7549 | | return 10; |
7550 | | case 1: |
7551 | | // op: rj |
7552 | | return 5; |
7553 | | case 0: |
7554 | | // op: vd |
7555 | | return 0; |
7556 | | } |
7557 | | break; |
7558 | | } |
7559 | | case LoongArch::XVLDREPL_W: { |
7560 | | switch (OpNum) { |
7561 | | case 2: |
7562 | | // op: imm10 |
7563 | | return 10; |
7564 | | case 1: |
7565 | | // op: rj |
7566 | | return 5; |
7567 | | case 0: |
7568 | | // op: xd |
7569 | | return 0; |
7570 | | } |
7571 | | break; |
7572 | | } |
7573 | | case LoongArch::VLDREPL_H: { |
7574 | | switch (OpNum) { |
7575 | | case 2: |
7576 | | // op: imm11 |
7577 | | return 10; |
7578 | | case 1: |
7579 | | // op: rj |
7580 | | return 5; |
7581 | | case 0: |
7582 | | // op: vd |
7583 | | return 0; |
7584 | | } |
7585 | | break; |
7586 | | } |
7587 | | case LoongArch::XVLDREPL_H: { |
7588 | | switch (OpNum) { |
7589 | | case 2: |
7590 | | // op: imm11 |
7591 | | return 10; |
7592 | | case 1: |
7593 | | // op: rj |
7594 | | return 5; |
7595 | | case 0: |
7596 | | // op: xd |
7597 | | return 0; |
7598 | | } |
7599 | | break; |
7600 | | } |
7601 | | case LoongArch::FLD_D: |
7602 | | case LoongArch::FLD_S: |
7603 | | case LoongArch::FST_D: |
7604 | | case LoongArch::FST_S: { |
7605 | | switch (OpNum) { |
7606 | | case 2: |
7607 | | // op: imm12 |
7608 | | return 10; |
7609 | | case 1: |
7610 | | // op: rj |
7611 | | return 5; |
7612 | | case 0: |
7613 | | // op: fd |
7614 | | return 0; |
7615 | | } |
7616 | | break; |
7617 | | } |
7618 | | case LoongArch::PRELD: { |
7619 | | switch (OpNum) { |
7620 | | case 2: |
7621 | | // op: imm12 |
7622 | | return 10; |
7623 | | case 1: |
7624 | | // op: rj |
7625 | | return 5; |
7626 | | case 0: |
7627 | | // op: imm5 |
7628 | | return 0; |
7629 | | } |
7630 | | break; |
7631 | | } |
7632 | | case LoongArch::CACOP: { |
7633 | | switch (OpNum) { |
7634 | | case 2: |
7635 | | // op: imm12 |
7636 | | return 10; |
7637 | | case 1: |
7638 | | // op: rj |
7639 | | return 5; |
7640 | | case 0: |
7641 | | // op: op |
7642 | | return 0; |
7643 | | } |
7644 | | break; |
7645 | | } |
7646 | | case LoongArch::ADDI_D: |
7647 | | case LoongArch::ADDI_W: |
7648 | | case LoongArch::ANDI: |
7649 | | case LoongArch::LDL_D: |
7650 | | case LoongArch::LDL_W: |
7651 | | case LoongArch::LDR_D: |
7652 | | case LoongArch::LDR_W: |
7653 | | case LoongArch::LD_B: |
7654 | | case LoongArch::LD_BU: |
7655 | | case LoongArch::LD_D: |
7656 | | case LoongArch::LD_H: |
7657 | | case LoongArch::LD_HU: |
7658 | | case LoongArch::LD_W: |
7659 | | case LoongArch::LD_WU: |
7660 | | case LoongArch::LU52I_D: |
7661 | | case LoongArch::ORI: |
7662 | | case LoongArch::SLTI: |
7663 | | case LoongArch::SLTUI: |
7664 | | case LoongArch::STL_D: |
7665 | | case LoongArch::STL_W: |
7666 | | case LoongArch::STR_D: |
7667 | | case LoongArch::STR_W: |
7668 | | case LoongArch::ST_B: |
7669 | | case LoongArch::ST_D: |
7670 | | case LoongArch::ST_H: |
7671 | | case LoongArch::ST_W: |
7672 | | case LoongArch::XORI: { |
7673 | | switch (OpNum) { |
7674 | | case 2: |
7675 | | // op: imm12 |
7676 | | return 10; |
7677 | | case 1: |
7678 | | // op: rj |
7679 | | return 5; |
7680 | | case 0: |
7681 | | // op: rd |
7682 | | return 0; |
7683 | | } |
7684 | | break; |
7685 | | } |
7686 | | case LoongArch::VLD: |
7687 | | case LoongArch::VLDREPL_B: |
7688 | | case LoongArch::VST: { |
7689 | | switch (OpNum) { |
7690 | | case 2: |
7691 | | // op: imm12 |
7692 | | return 10; |
7693 | | case 1: |
7694 | | // op: rj |
7695 | | return 5; |
7696 | | case 0: |
7697 | | // op: vd |
7698 | | return 0; |
7699 | | } |
7700 | | break; |
7701 | | } |
7702 | | case LoongArch::XVLD: |
7703 | | case LoongArch::XVLDREPL_B: |
7704 | | case LoongArch::XVST: { |
7705 | | switch (OpNum) { |
7706 | | case 2: |
7707 | | // op: imm12 |
7708 | | return 10; |
7709 | | case 1: |
7710 | | // op: rj |
7711 | | return 5; |
7712 | | case 0: |
7713 | | // op: xd |
7714 | | return 0; |
7715 | | } |
7716 | | break; |
7717 | | } |
7718 | | case LoongArch::LDPTR_D: |
7719 | | case LoongArch::LDPTR_W: |
7720 | | case LoongArch::LL_D: |
7721 | | case LoongArch::LL_W: |
7722 | | case LoongArch::STPTR_D: |
7723 | | case LoongArch::STPTR_W: { |
7724 | | switch (OpNum) { |
7725 | | case 2: |
7726 | | // op: imm14 |
7727 | | return 10; |
7728 | | case 1: |
7729 | | // op: rj |
7730 | | return 5; |
7731 | | case 0: |
7732 | | // op: rd |
7733 | | return 0; |
7734 | | } |
7735 | | break; |
7736 | | } |
7737 | | case LoongArch::BEQ: |
7738 | | case LoongArch::BGE: |
7739 | | case LoongArch::BGEU: |
7740 | | case LoongArch::BLT: |
7741 | | case LoongArch::BLTU: |
7742 | | case LoongArch::BNE: { |
7743 | | switch (OpNum) { |
7744 | | case 2: |
7745 | | // op: imm16 |
7746 | | return 10; |
7747 | | case 0: |
7748 | | // op: rj |
7749 | | return 5; |
7750 | | case 1: |
7751 | | // op: rd |
7752 | | return 0; |
7753 | | } |
7754 | | break; |
7755 | | } |
7756 | | case LoongArch::ADDU16I_D: |
7757 | | case LoongArch::JIRL: { |
7758 | | switch (OpNum) { |
7759 | | case 2: |
7760 | | // op: imm16 |
7761 | | return 10; |
7762 | | case 1: |
7763 | | // op: rj |
7764 | | return 5; |
7765 | | case 0: |
7766 | | // op: rd |
7767 | | return 0; |
7768 | | } |
7769 | | break; |
7770 | | } |
7771 | | case LoongArch::VPICKVE2GR_W: |
7772 | | case LoongArch::VPICKVE2GR_WU: { |
7773 | | switch (OpNum) { |
7774 | | case 2: |
7775 | | // op: imm2 |
7776 | | return 10; |
7777 | | case 1: |
7778 | | // op: vj |
7779 | | return 5; |
7780 | | case 0: |
7781 | | // op: rd |
7782 | | return 0; |
7783 | | } |
7784 | | break; |
7785 | | } |
7786 | | case LoongArch::VREPLVEI_W: { |
7787 | | switch (OpNum) { |
7788 | | case 2: |
7789 | | // op: imm2 |
7790 | | return 10; |
7791 | | case 1: |
7792 | | // op: vj |
7793 | | return 5; |
7794 | | case 0: |
7795 | | // op: vd |
7796 | | return 0; |
7797 | | } |
7798 | | break; |
7799 | | } |
7800 | | case LoongArch::XVPICKVE2GR_D: |
7801 | | case LoongArch::XVPICKVE2GR_DU: { |
7802 | | switch (OpNum) { |
7803 | | case 2: |
7804 | | // op: imm2 |
7805 | | return 10; |
7806 | | case 1: |
7807 | | // op: xj |
7808 | | return 5; |
7809 | | case 0: |
7810 | | // op: rd |
7811 | | return 0; |
7812 | | } |
7813 | | break; |
7814 | | } |
7815 | | case LoongArch::XVPICKVE_D: |
7816 | | case LoongArch::XVREPL128VEI_W: { |
7817 | | switch (OpNum) { |
7818 | | case 2: |
7819 | | // op: imm2 |
7820 | | return 10; |
7821 | | case 1: |
7822 | | // op: xj |
7823 | | return 5; |
7824 | | case 0: |
7825 | | // op: xd |
7826 | | return 0; |
7827 | | } |
7828 | | break; |
7829 | | } |
7830 | | case LoongArch::LU32I_D: { |
7831 | | switch (OpNum) { |
7832 | | case 2: |
7833 | | // op: imm20 |
7834 | | return 5; |
7835 | | case 1: |
7836 | | // op: rd |
7837 | | return 0; |
7838 | | } |
7839 | | break; |
7840 | | } |
7841 | | case LoongArch::RCRI_B: |
7842 | | case LoongArch::ROTRI_B: { |
7843 | | switch (OpNum) { |
7844 | | case 2: |
7845 | | // op: imm3 |
7846 | | return 10; |
7847 | | case 1: |
7848 | | // op: rj |
7849 | | return 5; |
7850 | | case 0: |
7851 | | // op: rd |
7852 | | return 0; |
7853 | | } |
7854 | | break; |
7855 | | } |
7856 | | case LoongArch::VPICKVE2GR_H: |
7857 | | case LoongArch::VPICKVE2GR_HU: { |
7858 | | switch (OpNum) { |
7859 | | case 2: |
7860 | | // op: imm3 |
7861 | | return 10; |
7862 | | case 1: |
7863 | | // op: vj |
7864 | | return 5; |
7865 | | case 0: |
7866 | | // op: rd |
7867 | | return 0; |
7868 | | } |
7869 | | break; |
7870 | | } |
7871 | | case LoongArch::VBITCLRI_B: |
7872 | | case LoongArch::VBITREVI_B: |
7873 | | case LoongArch::VBITSETI_B: |
7874 | | case LoongArch::VREPLVEI_H: |
7875 | | case LoongArch::VROTRI_B: |
7876 | | case LoongArch::VSAT_B: |
7877 | | case LoongArch::VSAT_BU: |
7878 | | case LoongArch::VSLLI_B: |
7879 | | case LoongArch::VSLLWIL_HU_BU: |
7880 | | case LoongArch::VSLLWIL_H_B: |
7881 | | case LoongArch::VSRAI_B: |
7882 | | case LoongArch::VSRARI_B: |
7883 | | case LoongArch::VSRLI_B: |
7884 | | case LoongArch::VSRLRI_B: { |
7885 | | switch (OpNum) { |
7886 | | case 2: |
7887 | | // op: imm3 |
7888 | | return 10; |
7889 | | case 1: |
7890 | | // op: vj |
7891 | | return 5; |
7892 | | case 0: |
7893 | | // op: vd |
7894 | | return 0; |
7895 | | } |
7896 | | break; |
7897 | | } |
7898 | | case LoongArch::XVPICKVE2GR_W: |
7899 | | case LoongArch::XVPICKVE2GR_WU: { |
7900 | | switch (OpNum) { |
7901 | | case 2: |
7902 | | // op: imm3 |
7903 | | return 10; |
7904 | | case 1: |
7905 | | // op: xj |
7906 | | return 5; |
7907 | | case 0: |
7908 | | // op: rd |
7909 | | return 0; |
7910 | | } |
7911 | | break; |
7912 | | } |
7913 | | case LoongArch::XVBITCLRI_B: |
7914 | | case LoongArch::XVBITREVI_B: |
7915 | | case LoongArch::XVBITSETI_B: |
7916 | | case LoongArch::XVPICKVE_W: |
7917 | | case LoongArch::XVREPL128VEI_H: |
7918 | | case LoongArch::XVROTRI_B: |
7919 | | case LoongArch::XVSAT_B: |
7920 | | case LoongArch::XVSAT_BU: |
7921 | | case LoongArch::XVSLLI_B: |
7922 | | case LoongArch::XVSLLWIL_HU_BU: |
7923 | | case LoongArch::XVSLLWIL_H_B: |
7924 | | case LoongArch::XVSRAI_B: |
7925 | | case LoongArch::XVSRARI_B: |
7926 | | case LoongArch::XVSRLI_B: |
7927 | | case LoongArch::XVSRLRI_B: { |
7928 | | switch (OpNum) { |
7929 | | case 2: |
7930 | | // op: imm3 |
7931 | | return 10; |
7932 | | case 1: |
7933 | | // op: xj |
7934 | | return 5; |
7935 | | case 0: |
7936 | | // op: xd |
7937 | | return 0; |
7938 | | } |
7939 | | break; |
7940 | | } |
7941 | | case LoongArch::ARMADC_W: |
7942 | | case LoongArch::ARMADD_W: |
7943 | | case LoongArch::ARMAND_W: |
7944 | | case LoongArch::ARMOR_W: |
7945 | | case LoongArch::ARMROTR_W: |
7946 | | case LoongArch::ARMSBC_W: |
7947 | | case LoongArch::ARMSLL_W: |
7948 | | case LoongArch::ARMSRA_W: |
7949 | | case LoongArch::ARMSRL_W: |
7950 | | case LoongArch::ARMSUB_W: |
7951 | | case LoongArch::ARMXOR_W: { |
7952 | | switch (OpNum) { |
7953 | | case 2: |
7954 | | // op: imm4 |
7955 | | return 0; |
7956 | | case 1: |
7957 | | // op: rk |
7958 | | return 10; |
7959 | | case 0: |
7960 | | // op: rj |
7961 | | return 5; |
7962 | | } |
7963 | | break; |
7964 | | } |
7965 | | case LoongArch::ARMMOVE: |
7966 | | case LoongArch::RCRI_H: |
7967 | | case LoongArch::ROTRI_H: { |
7968 | | switch (OpNum) { |
7969 | | case 2: |
7970 | | // op: imm4 |
7971 | | return 10; |
7972 | | case 1: |
7973 | | // op: rj |
7974 | | return 5; |
7975 | | case 0: |
7976 | | // op: rd |
7977 | | return 0; |
7978 | | } |
7979 | | break; |
7980 | | } |
7981 | | case LoongArch::VPICKVE2GR_B: |
7982 | | case LoongArch::VPICKVE2GR_BU: { |
7983 | | switch (OpNum) { |
7984 | | case 2: |
7985 | | // op: imm4 |
7986 | | return 10; |
7987 | | case 1: |
7988 | | // op: vj |
7989 | | return 5; |
7990 | | case 0: |
7991 | | // op: rd |
7992 | | return 0; |
7993 | | } |
7994 | | break; |
7995 | | } |
7996 | | case LoongArch::VBITCLRI_H: |
7997 | | case LoongArch::VBITREVI_H: |
7998 | | case LoongArch::VBITSETI_H: |
7999 | | case LoongArch::VREPLVEI_B: |
8000 | | case LoongArch::VROTRI_H: |
8001 | | case LoongArch::VSAT_H: |
8002 | | case LoongArch::VSAT_HU: |
8003 | | case LoongArch::VSLLI_H: |
8004 | | case LoongArch::VSLLWIL_WU_HU: |
8005 | | case LoongArch::VSLLWIL_W_H: |
8006 | | case LoongArch::VSRAI_H: |
8007 | | case LoongArch::VSRARI_H: |
8008 | | case LoongArch::VSRLI_H: |
8009 | | case LoongArch::VSRLRI_H: { |
8010 | | switch (OpNum) { |
8011 | | case 2: |
8012 | | // op: imm4 |
8013 | | return 10; |
8014 | | case 1: |
8015 | | // op: vj |
8016 | | return 5; |
8017 | | case 0: |
8018 | | // op: vd |
8019 | | return 0; |
8020 | | } |
8021 | | break; |
8022 | | } |
8023 | | case LoongArch::XVBITCLRI_H: |
8024 | | case LoongArch::XVBITREVI_H: |
8025 | | case LoongArch::XVBITSETI_H: |
8026 | | case LoongArch::XVREPL128VEI_B: |
8027 | | case LoongArch::XVROTRI_H: |
8028 | | case LoongArch::XVSAT_H: |
8029 | | case LoongArch::XVSAT_HU: |
8030 | | case LoongArch::XVSLLI_H: |
8031 | | case LoongArch::XVSLLWIL_WU_HU: |
8032 | | case LoongArch::XVSLLWIL_W_H: |
8033 | | case LoongArch::XVSRAI_H: |
8034 | | case LoongArch::XVSRARI_H: |
8035 | | case LoongArch::XVSRLI_H: |
8036 | | case LoongArch::XVSRLRI_H: { |
8037 | | switch (OpNum) { |
8038 | | case 2: |
8039 | | // op: imm4 |
8040 | | return 10; |
8041 | | case 1: |
8042 | | // op: xj |
8043 | | return 5; |
8044 | | case 0: |
8045 | | // op: xd |
8046 | | return 0; |
8047 | | } |
8048 | | break; |
8049 | | } |
8050 | | case LoongArch::ADDU12I_D: |
8051 | | case LoongArch::ADDU12I_W: |
8052 | | case LoongArch::RCRI_W: |
8053 | | case LoongArch::ROTRI_W: |
8054 | | case LoongArch::SLLI_W: |
8055 | | case LoongArch::SRAI_W: |
8056 | | case LoongArch::SRLI_W: { |
8057 | | switch (OpNum) { |
8058 | | case 2: |
8059 | | // op: imm5 |
8060 | | return 10; |
8061 | | case 1: |
8062 | | // op: rj |
8063 | | return 5; |
8064 | | case 0: |
8065 | | // op: rd |
8066 | | return 0; |
8067 | | } |
8068 | | break; |
8069 | | } |
8070 | | case LoongArch::VADDI_BU: |
8071 | | case LoongArch::VADDI_DU: |
8072 | | case LoongArch::VADDI_HU: |
8073 | | case LoongArch::VADDI_WU: |
8074 | | case LoongArch::VBITCLRI_W: |
8075 | | case LoongArch::VBITREVI_W: |
8076 | | case LoongArch::VBITSETI_W: |
8077 | | case LoongArch::VBSLL_V: |
8078 | | case LoongArch::VBSRL_V: |
8079 | | case LoongArch::VMAXI_B: |
8080 | | case LoongArch::VMAXI_BU: |
8081 | | case LoongArch::VMAXI_D: |
8082 | | case LoongArch::VMAXI_DU: |
8083 | | case LoongArch::VMAXI_H: |
8084 | | case LoongArch::VMAXI_HU: |
8085 | | case LoongArch::VMAXI_W: |
8086 | | case LoongArch::VMAXI_WU: |
8087 | | case LoongArch::VMINI_B: |
8088 | | case LoongArch::VMINI_BU: |
8089 | | case LoongArch::VMINI_D: |
8090 | | case LoongArch::VMINI_DU: |
8091 | | case LoongArch::VMINI_H: |
8092 | | case LoongArch::VMINI_HU: |
8093 | | case LoongArch::VMINI_W: |
8094 | | case LoongArch::VMINI_WU: |
8095 | | case LoongArch::VROTRI_W: |
8096 | | case LoongArch::VSAT_W: |
8097 | | case LoongArch::VSAT_WU: |
8098 | | case LoongArch::VSEQI_B: |
8099 | | case LoongArch::VSEQI_D: |
8100 | | case LoongArch::VSEQI_H: |
8101 | | case LoongArch::VSEQI_W: |
8102 | | case LoongArch::VSLEI_B: |
8103 | | case LoongArch::VSLEI_BU: |
8104 | | case LoongArch::VSLEI_D: |
8105 | | case LoongArch::VSLEI_DU: |
8106 | | case LoongArch::VSLEI_H: |
8107 | | case LoongArch::VSLEI_HU: |
8108 | | case LoongArch::VSLEI_W: |
8109 | | case LoongArch::VSLEI_WU: |
8110 | | case LoongArch::VSLLI_W: |
8111 | | case LoongArch::VSLLWIL_DU_WU: |
8112 | | case LoongArch::VSLLWIL_D_W: |
8113 | | case LoongArch::VSLTI_B: |
8114 | | case LoongArch::VSLTI_BU: |
8115 | | case LoongArch::VSLTI_D: |
8116 | | case LoongArch::VSLTI_DU: |
8117 | | case LoongArch::VSLTI_H: |
8118 | | case LoongArch::VSLTI_HU: |
8119 | | case LoongArch::VSLTI_W: |
8120 | | case LoongArch::VSLTI_WU: |
8121 | | case LoongArch::VSRAI_W: |
8122 | | case LoongArch::VSRARI_W: |
8123 | | case LoongArch::VSRLI_W: |
8124 | | case LoongArch::VSRLRI_W: |
8125 | | case LoongArch::VSUBI_BU: |
8126 | | case LoongArch::VSUBI_DU: |
8127 | | case LoongArch::VSUBI_HU: |
8128 | | case LoongArch::VSUBI_WU: { |
8129 | | switch (OpNum) { |
8130 | | case 2: |
8131 | | // op: imm5 |
8132 | | return 10; |
8133 | | case 1: |
8134 | | // op: vj |
8135 | | return 5; |
8136 | | case 0: |
8137 | | // op: vd |
8138 | | return 0; |
8139 | | } |
8140 | | break; |
8141 | | } |
8142 | | case LoongArch::XVADDI_BU: |
8143 | | case LoongArch::XVADDI_DU: |
8144 | | case LoongArch::XVADDI_HU: |
8145 | | case LoongArch::XVADDI_WU: |
8146 | | case LoongArch::XVBITCLRI_W: |
8147 | | case LoongArch::XVBITREVI_W: |
8148 | | case LoongArch::XVBITSETI_W: |
8149 | | case LoongArch::XVBSLL_V: |
8150 | | case LoongArch::XVBSRL_V: |
8151 | | case LoongArch::XVHSELI_D: |
8152 | | case LoongArch::XVMAXI_B: |
8153 | | case LoongArch::XVMAXI_BU: |
8154 | | case LoongArch::XVMAXI_D: |
8155 | | case LoongArch::XVMAXI_DU: |
8156 | | case LoongArch::XVMAXI_H: |
8157 | | case LoongArch::XVMAXI_HU: |
8158 | | case LoongArch::XVMAXI_W: |
8159 | | case LoongArch::XVMAXI_WU: |
8160 | | case LoongArch::XVMINI_B: |
8161 | | case LoongArch::XVMINI_BU: |
8162 | | case LoongArch::XVMINI_D: |
8163 | | case LoongArch::XVMINI_DU: |
8164 | | case LoongArch::XVMINI_H: |
8165 | | case LoongArch::XVMINI_HU: |
8166 | | case LoongArch::XVMINI_W: |
8167 | | case LoongArch::XVMINI_WU: |
8168 | | case LoongArch::XVROTRI_W: |
8169 | | case LoongArch::XVSAT_W: |
8170 | | case LoongArch::XVSAT_WU: |
8171 | | case LoongArch::XVSEQI_B: |
8172 | | case LoongArch::XVSEQI_D: |
8173 | | case LoongArch::XVSEQI_H: |
8174 | | case LoongArch::XVSEQI_W: |
8175 | | case LoongArch::XVSLEI_B: |
8176 | | case LoongArch::XVSLEI_BU: |
8177 | | case LoongArch::XVSLEI_D: |
8178 | | case LoongArch::XVSLEI_DU: |
8179 | | case LoongArch::XVSLEI_H: |
8180 | | case LoongArch::XVSLEI_HU: |
8181 | | case LoongArch::XVSLEI_W: |
8182 | | case LoongArch::XVSLEI_WU: |
8183 | | case LoongArch::XVSLLI_W: |
8184 | | case LoongArch::XVSLLWIL_DU_WU: |
8185 | | case LoongArch::XVSLLWIL_D_W: |
8186 | | case LoongArch::XVSLTI_B: |
8187 | | case LoongArch::XVSLTI_BU: |
8188 | | case LoongArch::XVSLTI_D: |
8189 | | case LoongArch::XVSLTI_DU: |
8190 | | case LoongArch::XVSLTI_H: |
8191 | | case LoongArch::XVSLTI_HU: |
8192 | | case LoongArch::XVSLTI_W: |
8193 | | case LoongArch::XVSLTI_WU: |
8194 | | case LoongArch::XVSRAI_W: |
8195 | | case LoongArch::XVSRARI_W: |
8196 | | case LoongArch::XVSRLI_W: |
8197 | | case LoongArch::XVSRLRI_W: |
8198 | | case LoongArch::XVSUBI_BU: |
8199 | | case LoongArch::XVSUBI_DU: |
8200 | | case LoongArch::XVSUBI_HU: |
8201 | | case LoongArch::XVSUBI_WU: { |
8202 | | switch (OpNum) { |
8203 | | case 2: |
8204 | | // op: imm5 |
8205 | | return 10; |
8206 | | case 1: |
8207 | | // op: xj |
8208 | | return 5; |
8209 | | case 0: |
8210 | | // op: xd |
8211 | | return 0; |
8212 | | } |
8213 | | break; |
8214 | | } |
8215 | | case LoongArch::RCRI_D: |
8216 | | case LoongArch::ROTRI_D: |
8217 | | case LoongArch::SLLI_D: |
8218 | | case LoongArch::SRAI_D: |
8219 | | case LoongArch::SRLI_D: { |
8220 | | switch (OpNum) { |
8221 | | case 2: |
8222 | | // op: imm6 |
8223 | | return 10; |
8224 | | case 1: |
8225 | | // op: rj |
8226 | | return 5; |
8227 | | case 0: |
8228 | | // op: rd |
8229 | | return 0; |
8230 | | } |
8231 | | break; |
8232 | | } |
8233 | | case LoongArch::VBITCLRI_D: |
8234 | | case LoongArch::VBITREVI_D: |
8235 | | case LoongArch::VBITSETI_D: |
8236 | | case LoongArch::VROTRI_D: |
8237 | | case LoongArch::VSAT_D: |
8238 | | case LoongArch::VSAT_DU: |
8239 | | case LoongArch::VSLLI_D: |
8240 | | case LoongArch::VSRAI_D: |
8241 | | case LoongArch::VSRARI_D: |
8242 | | case LoongArch::VSRLI_D: |
8243 | | case LoongArch::VSRLRI_D: { |
8244 | | switch (OpNum) { |
8245 | | case 2: |
8246 | | // op: imm6 |
8247 | | return 10; |
8248 | | case 1: |
8249 | | // op: vj |
8250 | | return 5; |
8251 | | case 0: |
8252 | | // op: vd |
8253 | | return 0; |
8254 | | } |
8255 | | break; |
8256 | | } |
8257 | | case LoongArch::XVBITCLRI_D: |
8258 | | case LoongArch::XVBITREVI_D: |
8259 | | case LoongArch::XVBITSETI_D: |
8260 | | case LoongArch::XVROTRI_D: |
8261 | | case LoongArch::XVSAT_D: |
8262 | | case LoongArch::XVSAT_DU: |
8263 | | case LoongArch::XVSLLI_D: |
8264 | | case LoongArch::XVSRAI_D: |
8265 | | case LoongArch::XVSRARI_D: |
8266 | | case LoongArch::XVSRLI_D: |
8267 | | case LoongArch::XVSRLRI_D: { |
8268 | | switch (OpNum) { |
8269 | | case 2: |
8270 | | // op: imm6 |
8271 | | return 10; |
8272 | | case 1: |
8273 | | // op: xj |
8274 | | return 5; |
8275 | | case 0: |
8276 | | // op: xd |
8277 | | return 0; |
8278 | | } |
8279 | | break; |
8280 | | } |
8281 | | case LoongArch::X86SETTAG: { |
8282 | | switch (OpNum) { |
8283 | | case 2: |
8284 | | // op: imm8 |
8285 | | return 10; |
8286 | | case 1: |
8287 | | // op: imm5 |
8288 | | return 5; |
8289 | | case 0: |
8290 | | // op: rd |
8291 | | return 0; |
8292 | | } |
8293 | | break; |
8294 | | } |
8295 | | case LoongArch::LDDIR: { |
8296 | | switch (OpNum) { |
8297 | | case 2: |
8298 | | // op: imm8 |
8299 | | return 10; |
8300 | | case 1: |
8301 | | // op: rj |
8302 | | return 5; |
8303 | | case 0: |
8304 | | // op: rd |
8305 | | return 0; |
8306 | | } |
8307 | | break; |
8308 | | } |
8309 | | case LoongArch::VANDI_B: |
8310 | | case LoongArch::VNORI_B: |
8311 | | case LoongArch::VORI_B: |
8312 | | case LoongArch::VSHUF4I_B: |
8313 | | case LoongArch::VSHUF4I_H: |
8314 | | case LoongArch::VSHUF4I_W: |
8315 | | case LoongArch::VXORI_B: { |
8316 | | switch (OpNum) { |
8317 | | case 2: |
8318 | | // op: imm8 |
8319 | | return 10; |
8320 | | case 1: |
8321 | | // op: vj |
8322 | | return 5; |
8323 | | case 0: |
8324 | | // op: vd |
8325 | | return 0; |
8326 | | } |
8327 | | break; |
8328 | | } |
8329 | | case LoongArch::XVANDI_B: |
8330 | | case LoongArch::XVNORI_B: |
8331 | | case LoongArch::XVORI_B: |
8332 | | case LoongArch::XVPERMI_D: |
8333 | | case LoongArch::XVSHUF4I_B: |
8334 | | case LoongArch::XVSHUF4I_H: |
8335 | | case LoongArch::XVSHUF4I_W: |
8336 | | case LoongArch::XVXORI_B: { |
8337 | | switch (OpNum) { |
8338 | | case 2: |
8339 | | // op: imm8 |
8340 | | return 10; |
8341 | | case 1: |
8342 | | // op: xj |
8343 | | return 5; |
8344 | | case 0: |
8345 | | // op: xd |
8346 | | return 0; |
8347 | | } |
8348 | | break; |
8349 | | } |
8350 | | case LoongArch::VLDREPL_D: { |
8351 | | switch (OpNum) { |
8352 | | case 2: |
8353 | | // op: imm9 |
8354 | | return 10; |
8355 | | case 1: |
8356 | | // op: rj |
8357 | | return 5; |
8358 | | case 0: |
8359 | | // op: vd |
8360 | | return 0; |
8361 | | } |
8362 | | break; |
8363 | | } |
8364 | | case LoongArch::XVLDREPL_D: { |
8365 | | switch (OpNum) { |
8366 | | case 2: |
8367 | | // op: imm9 |
8368 | | return 10; |
8369 | | case 1: |
8370 | | // op: rj |
8371 | | return 5; |
8372 | | case 0: |
8373 | | // op: xd |
8374 | | return 0; |
8375 | | } |
8376 | | break; |
8377 | | } |
8378 | | case LoongArch::BSTRPICK_D: { |
8379 | | switch (OpNum) { |
8380 | | case 2: |
8381 | | // op: msbd |
8382 | | return 16; |
8383 | | case 3: |
8384 | | // op: lsbd |
8385 | | return 10; |
8386 | | case 1: |
8387 | | // op: rj |
8388 | | return 5; |
8389 | | case 0: |
8390 | | // op: rd |
8391 | | return 0; |
8392 | | } |
8393 | | break; |
8394 | | } |
8395 | | case LoongArch::BSTRPICK_W: { |
8396 | | switch (OpNum) { |
8397 | | case 2: |
8398 | | // op: msbw |
8399 | | return 16; |
8400 | | case 3: |
8401 | | // op: lsbw |
8402 | | return 10; |
8403 | | case 1: |
8404 | | // op: rj |
8405 | | return 5; |
8406 | | case 0: |
8407 | | // op: rd |
8408 | | return 0; |
8409 | | } |
8410 | | break; |
8411 | | } |
8412 | | case LoongArch::SCREL_D: |
8413 | | case LoongArch::SCREL_W: { |
8414 | | switch (OpNum) { |
8415 | | case 2: |
8416 | | // op: rj |
8417 | | return 5; |
8418 | | case 1: |
8419 | | // op: rd |
8420 | | return 0; |
8421 | | } |
8422 | | break; |
8423 | | } |
8424 | | case LoongArch::FLDGT_D: |
8425 | | case LoongArch::FLDGT_S: |
8426 | | case LoongArch::FLDLE_D: |
8427 | | case LoongArch::FLDLE_S: |
8428 | | case LoongArch::FLDX_D: |
8429 | | case LoongArch::FLDX_S: |
8430 | | case LoongArch::FSTGT_D: |
8431 | | case LoongArch::FSTGT_S: |
8432 | | case LoongArch::FSTLE_D: |
8433 | | case LoongArch::FSTLE_S: |
8434 | | case LoongArch::FSTX_D: |
8435 | | case LoongArch::FSTX_S: { |
8436 | | switch (OpNum) { |
8437 | | case 2: |
8438 | | // op: rk |
8439 | | return 10; |
8440 | | case 1: |
8441 | | // op: rj |
8442 | | return 5; |
8443 | | case 0: |
8444 | | // op: fd |
8445 | | return 0; |
8446 | | } |
8447 | | break; |
8448 | | } |
8449 | | case LoongArch::PRELDX: { |
8450 | | switch (OpNum) { |
8451 | | case 2: |
8452 | | // op: rk |
8453 | | return 10; |
8454 | | case 1: |
8455 | | // op: rj |
8456 | | return 5; |
8457 | | case 0: |
8458 | | // op: imm5 |
8459 | | return 0; |
8460 | | } |
8461 | | break; |
8462 | | } |
8463 | | case LoongArch::ADC_B: |
8464 | | case LoongArch::ADC_D: |
8465 | | case LoongArch::ADC_H: |
8466 | | case LoongArch::ADC_W: |
8467 | | case LoongArch::ADD_D: |
8468 | | case LoongArch::ADD_W: |
8469 | | case LoongArch::AND: |
8470 | | case LoongArch::ANDN: |
8471 | | case LoongArch::CRCC_W_B_W: |
8472 | | case LoongArch::CRCC_W_D_W: |
8473 | | case LoongArch::CRCC_W_H_W: |
8474 | | case LoongArch::CRCC_W_W_W: |
8475 | | case LoongArch::CRC_W_B_W: |
8476 | | case LoongArch::CRC_W_D_W: |
8477 | | case LoongArch::CRC_W_H_W: |
8478 | | case LoongArch::CRC_W_W_W: |
8479 | | case LoongArch::DIV_D: |
8480 | | case LoongArch::DIV_DU: |
8481 | | case LoongArch::DIV_W: |
8482 | | case LoongArch::DIV_WU: |
8483 | | case LoongArch::LDGT_B: |
8484 | | case LoongArch::LDGT_D: |
8485 | | case LoongArch::LDGT_H: |
8486 | | case LoongArch::LDGT_W: |
8487 | | case LoongArch::LDLE_B: |
8488 | | case LoongArch::LDLE_D: |
8489 | | case LoongArch::LDLE_H: |
8490 | | case LoongArch::LDLE_W: |
8491 | | case LoongArch::LDX_B: |
8492 | | case LoongArch::LDX_BU: |
8493 | | case LoongArch::LDX_D: |
8494 | | case LoongArch::LDX_H: |
8495 | | case LoongArch::LDX_HU: |
8496 | | case LoongArch::LDX_W: |
8497 | | case LoongArch::LDX_WU: |
8498 | | case LoongArch::MASKEQZ: |
8499 | | case LoongArch::MASKNEZ: |
8500 | | case LoongArch::MOD_D: |
8501 | | case LoongArch::MOD_DU: |
8502 | | case LoongArch::MOD_W: |
8503 | | case LoongArch::MOD_WU: |
8504 | | case LoongArch::MULH_D: |
8505 | | case LoongArch::MULH_DU: |
8506 | | case LoongArch::MULH_W: |
8507 | | case LoongArch::MULH_WU: |
8508 | | case LoongArch::MULW_D_W: |
8509 | | case LoongArch::MULW_D_WU: |
8510 | | case LoongArch::MUL_D: |
8511 | | case LoongArch::MUL_W: |
8512 | | case LoongArch::NOR: |
8513 | | case LoongArch::OR: |
8514 | | case LoongArch::ORN: |
8515 | | case LoongArch::RCR_B: |
8516 | | case LoongArch::RCR_D: |
8517 | | case LoongArch::RCR_H: |
8518 | | case LoongArch::RCR_W: |
8519 | | case LoongArch::ROTR_B: |
8520 | | case LoongArch::ROTR_D: |
8521 | | case LoongArch::ROTR_H: |
8522 | | case LoongArch::ROTR_W: |
8523 | | case LoongArch::SBC_B: |
8524 | | case LoongArch::SBC_D: |
8525 | | case LoongArch::SBC_H: |
8526 | | case LoongArch::SBC_W: |
8527 | | case LoongArch::SLL_D: |
8528 | | case LoongArch::SLL_W: |
8529 | | case LoongArch::SLT: |
8530 | | case LoongArch::SLTU: |
8531 | | case LoongArch::SRA_D: |
8532 | | case LoongArch::SRA_W: |
8533 | | case LoongArch::SRL_D: |
8534 | | case LoongArch::SRL_W: |
8535 | | case LoongArch::STGT_B: |
8536 | | case LoongArch::STGT_D: |
8537 | | case LoongArch::STGT_H: |
8538 | | case LoongArch::STGT_W: |
8539 | | case LoongArch::STLE_B: |
8540 | | case LoongArch::STLE_D: |
8541 | | case LoongArch::STLE_H: |
8542 | | case LoongArch::STLE_W: |
8543 | | case LoongArch::STX_B: |
8544 | | case LoongArch::STX_D: |
8545 | | case LoongArch::STX_H: |
8546 | | case LoongArch::STX_W: |
8547 | | case LoongArch::SUB_D: |
8548 | | case LoongArch::SUB_W: |
8549 | | case LoongArch::XOR: { |
8550 | | switch (OpNum) { |
8551 | | case 2: |
8552 | | // op: rk |
8553 | | return 10; |
8554 | | case 1: |
8555 | | // op: rj |
8556 | | return 5; |
8557 | | case 0: |
8558 | | // op: rd |
8559 | | return 0; |
8560 | | } |
8561 | | break; |
8562 | | } |
8563 | | case LoongArch::VLDX: |
8564 | | case LoongArch::VSTX: { |
8565 | | switch (OpNum) { |
8566 | | case 2: |
8567 | | // op: rk |
8568 | | return 10; |
8569 | | case 1: |
8570 | | // op: rj |
8571 | | return 5; |
8572 | | case 0: |
8573 | | // op: vd |
8574 | | return 0; |
8575 | | } |
8576 | | break; |
8577 | | } |
8578 | | case LoongArch::XVLDX: |
8579 | | case LoongArch::XVSTX: { |
8580 | | switch (OpNum) { |
8581 | | case 2: |
8582 | | // op: rk |
8583 | | return 10; |
8584 | | case 1: |
8585 | | // op: rj |
8586 | | return 5; |
8587 | | case 0: |
8588 | | // op: xd |
8589 | | return 0; |
8590 | | } |
8591 | | break; |
8592 | | } |
8593 | | case LoongArch::VREPLVE_B: |
8594 | | case LoongArch::VREPLVE_D: |
8595 | | case LoongArch::VREPLVE_H: |
8596 | | case LoongArch::VREPLVE_W: { |
8597 | | switch (OpNum) { |
8598 | | case 2: |
8599 | | // op: rk |
8600 | | return 10; |
8601 | | case 1: |
8602 | | // op: vj |
8603 | | return 5; |
8604 | | case 0: |
8605 | | // op: vd |
8606 | | return 0; |
8607 | | } |
8608 | | break; |
8609 | | } |
8610 | | case LoongArch::XVREPLVE_B: |
8611 | | case LoongArch::XVREPLVE_D: |
8612 | | case LoongArch::XVREPLVE_H: |
8613 | | case LoongArch::XVREPLVE_W: { |
8614 | | switch (OpNum) { |
8615 | | case 2: |
8616 | | // op: rk |
8617 | | return 10; |
8618 | | case 1: |
8619 | | // op: xj |
8620 | | return 5; |
8621 | | case 0: |
8622 | | // op: xd |
8623 | | return 0; |
8624 | | } |
8625 | | break; |
8626 | | } |
8627 | | case LoongArch::SC_Q: { |
8628 | | switch (OpNum) { |
8629 | | case 2: |
8630 | | // op: rk |
8631 | | return 10; |
8632 | | case 3: |
8633 | | // op: rj |
8634 | | return 5; |
8635 | | case 1: |
8636 | | // op: rd |
8637 | | return 0; |
8638 | | } |
8639 | | break; |
8640 | | } |
8641 | | case LoongArch::MOVGR2FRH_W: { |
8642 | | switch (OpNum) { |
8643 | | case 2: |
8644 | | // op: src |
8645 | | return 5; |
8646 | | case 1: |
8647 | | // op: dst |
8648 | | return 0; |
8649 | | } |
8650 | | break; |
8651 | | } |
8652 | | case LoongArch::VABSD_B: |
8653 | | case LoongArch::VABSD_BU: |
8654 | | case LoongArch::VABSD_D: |
8655 | | case LoongArch::VABSD_DU: |
8656 | | case LoongArch::VABSD_H: |
8657 | | case LoongArch::VABSD_HU: |
8658 | | case LoongArch::VABSD_W: |
8659 | | case LoongArch::VABSD_WU: |
8660 | | case LoongArch::VADDA_B: |
8661 | | case LoongArch::VADDA_D: |
8662 | | case LoongArch::VADDA_H: |
8663 | | case LoongArch::VADDA_W: |
8664 | | case LoongArch::VADDWEV_D_W: |
8665 | | case LoongArch::VADDWEV_D_WU: |
8666 | | case LoongArch::VADDWEV_D_WU_W: |
8667 | | case LoongArch::VADDWEV_H_B: |
8668 | | case LoongArch::VADDWEV_H_BU: |
8669 | | case LoongArch::VADDWEV_H_BU_B: |
8670 | | case LoongArch::VADDWEV_Q_D: |
8671 | | case LoongArch::VADDWEV_Q_DU: |
8672 | | case LoongArch::VADDWEV_Q_DU_D: |
8673 | | case LoongArch::VADDWEV_W_H: |
8674 | | case LoongArch::VADDWEV_W_HU: |
8675 | | case LoongArch::VADDWEV_W_HU_H: |
8676 | | case LoongArch::VADDWOD_D_W: |
8677 | | case LoongArch::VADDWOD_D_WU: |
8678 | | case LoongArch::VADDWOD_D_WU_W: |
8679 | | case LoongArch::VADDWOD_H_B: |
8680 | | case LoongArch::VADDWOD_H_BU: |
8681 | | case LoongArch::VADDWOD_H_BU_B: |
8682 | | case LoongArch::VADDWOD_Q_D: |
8683 | | case LoongArch::VADDWOD_Q_DU: |
8684 | | case LoongArch::VADDWOD_Q_DU_D: |
8685 | | case LoongArch::VADDWOD_W_H: |
8686 | | case LoongArch::VADDWOD_W_HU: |
8687 | | case LoongArch::VADDWOD_W_HU_H: |
8688 | | case LoongArch::VADD_B: |
8689 | | case LoongArch::VADD_D: |
8690 | | case LoongArch::VADD_H: |
8691 | | case LoongArch::VADD_Q: |
8692 | | case LoongArch::VADD_W: |
8693 | | case LoongArch::VANDN_V: |
8694 | | case LoongArch::VAND_V: |
8695 | | case LoongArch::VAVGR_B: |
8696 | | case LoongArch::VAVGR_BU: |
8697 | | case LoongArch::VAVGR_D: |
8698 | | case LoongArch::VAVGR_DU: |
8699 | | case LoongArch::VAVGR_H: |
8700 | | case LoongArch::VAVGR_HU: |
8701 | | case LoongArch::VAVGR_W: |
8702 | | case LoongArch::VAVGR_WU: |
8703 | | case LoongArch::VAVG_B: |
8704 | | case LoongArch::VAVG_BU: |
8705 | | case LoongArch::VAVG_D: |
8706 | | case LoongArch::VAVG_DU: |
8707 | | case LoongArch::VAVG_H: |
8708 | | case LoongArch::VAVG_HU: |
8709 | | case LoongArch::VAVG_W: |
8710 | | case LoongArch::VAVG_WU: |
8711 | | case LoongArch::VBITCLR_B: |
8712 | | case LoongArch::VBITCLR_D: |
8713 | | case LoongArch::VBITCLR_H: |
8714 | | case LoongArch::VBITCLR_W: |
8715 | | case LoongArch::VBITREV_B: |
8716 | | case LoongArch::VBITREV_D: |
8717 | | case LoongArch::VBITREV_H: |
8718 | | case LoongArch::VBITREV_W: |
8719 | | case LoongArch::VBITSET_B: |
8720 | | case LoongArch::VBITSET_D: |
8721 | | case LoongArch::VBITSET_H: |
8722 | | case LoongArch::VBITSET_W: |
8723 | | case LoongArch::VDIV_B: |
8724 | | case LoongArch::VDIV_BU: |
8725 | | case LoongArch::VDIV_D: |
8726 | | case LoongArch::VDIV_DU: |
8727 | | case LoongArch::VDIV_H: |
8728 | | case LoongArch::VDIV_HU: |
8729 | | case LoongArch::VDIV_W: |
8730 | | case LoongArch::VDIV_WU: |
8731 | | case LoongArch::VFADD_D: |
8732 | | case LoongArch::VFADD_S: |
8733 | | case LoongArch::VFCMP_CAF_D: |
8734 | | case LoongArch::VFCMP_CAF_S: |
8735 | | case LoongArch::VFCMP_CEQ_D: |
8736 | | case LoongArch::VFCMP_CEQ_S: |
8737 | | case LoongArch::VFCMP_CLE_D: |
8738 | | case LoongArch::VFCMP_CLE_S: |
8739 | | case LoongArch::VFCMP_CLT_D: |
8740 | | case LoongArch::VFCMP_CLT_S: |
8741 | | case LoongArch::VFCMP_CNE_D: |
8742 | | case LoongArch::VFCMP_CNE_S: |
8743 | | case LoongArch::VFCMP_COR_D: |
8744 | | case LoongArch::VFCMP_COR_S: |
8745 | | case LoongArch::VFCMP_CUEQ_D: |
8746 | | case LoongArch::VFCMP_CUEQ_S: |
8747 | | case LoongArch::VFCMP_CULE_D: |
8748 | | case LoongArch::VFCMP_CULE_S: |
8749 | | case LoongArch::VFCMP_CULT_D: |
8750 | | case LoongArch::VFCMP_CULT_S: |
8751 | | case LoongArch::VFCMP_CUNE_D: |
8752 | | case LoongArch::VFCMP_CUNE_S: |
8753 | | case LoongArch::VFCMP_CUN_D: |
8754 | | case LoongArch::VFCMP_CUN_S: |
8755 | | case LoongArch::VFCMP_SAF_D: |
8756 | | case LoongArch::VFCMP_SAF_S: |
8757 | | case LoongArch::VFCMP_SEQ_D: |
8758 | | case LoongArch::VFCMP_SEQ_S: |
8759 | | case LoongArch::VFCMP_SLE_D: |
8760 | | case LoongArch::VFCMP_SLE_S: |
8761 | | case LoongArch::VFCMP_SLT_D: |
8762 | | case LoongArch::VFCMP_SLT_S: |
8763 | | case LoongArch::VFCMP_SNE_D: |
8764 | | case LoongArch::VFCMP_SNE_S: |
8765 | | case LoongArch::VFCMP_SOR_D: |
8766 | | case LoongArch::VFCMP_SOR_S: |
8767 | | case LoongArch::VFCMP_SUEQ_D: |
8768 | | case LoongArch::VFCMP_SUEQ_S: |
8769 | | case LoongArch::VFCMP_SULE_D: |
8770 | | case LoongArch::VFCMP_SULE_S: |
8771 | | case LoongArch::VFCMP_SULT_D: |
8772 | | case LoongArch::VFCMP_SULT_S: |
8773 | | case LoongArch::VFCMP_SUNE_D: |
8774 | | case LoongArch::VFCMP_SUNE_S: |
8775 | | case LoongArch::VFCMP_SUN_D: |
8776 | | case LoongArch::VFCMP_SUN_S: |
8777 | | case LoongArch::VFCVT_H_S: |
8778 | | case LoongArch::VFCVT_S_D: |
8779 | | case LoongArch::VFDIV_D: |
8780 | | case LoongArch::VFDIV_S: |
8781 | | case LoongArch::VFFINT_S_L: |
8782 | | case LoongArch::VFMAXA_D: |
8783 | | case LoongArch::VFMAXA_S: |
8784 | | case LoongArch::VFMAX_D: |
8785 | | case LoongArch::VFMAX_S: |
8786 | | case LoongArch::VFMINA_D: |
8787 | | case LoongArch::VFMINA_S: |
8788 | | case LoongArch::VFMIN_D: |
8789 | | case LoongArch::VFMIN_S: |
8790 | | case LoongArch::VFMUL_D: |
8791 | | case LoongArch::VFMUL_S: |
8792 | | case LoongArch::VFSUB_D: |
8793 | | case LoongArch::VFSUB_S: |
8794 | | case LoongArch::VFTINTRM_W_D: |
8795 | | case LoongArch::VFTINTRNE_W_D: |
8796 | | case LoongArch::VFTINTRP_W_D: |
8797 | | case LoongArch::VFTINTRZ_W_D: |
8798 | | case LoongArch::VFTINT_W_D: |
8799 | | case LoongArch::VHADDW_DU_WU: |
8800 | | case LoongArch::VHADDW_D_W: |
8801 | | case LoongArch::VHADDW_HU_BU: |
8802 | | case LoongArch::VHADDW_H_B: |
8803 | | case LoongArch::VHADDW_QU_DU: |
8804 | | case LoongArch::VHADDW_Q_D: |
8805 | | case LoongArch::VHADDW_WU_HU: |
8806 | | case LoongArch::VHADDW_W_H: |
8807 | | case LoongArch::VHSUBW_DU_WU: |
8808 | | case LoongArch::VHSUBW_D_W: |
8809 | | case LoongArch::VHSUBW_HU_BU: |
8810 | | case LoongArch::VHSUBW_H_B: |
8811 | | case LoongArch::VHSUBW_QU_DU: |
8812 | | case LoongArch::VHSUBW_Q_D: |
8813 | | case LoongArch::VHSUBW_WU_HU: |
8814 | | case LoongArch::VHSUBW_W_H: |
8815 | | case LoongArch::VILVH_B: |
8816 | | case LoongArch::VILVH_D: |
8817 | | case LoongArch::VILVH_H: |
8818 | | case LoongArch::VILVH_W: |
8819 | | case LoongArch::VILVL_B: |
8820 | | case LoongArch::VILVL_D: |
8821 | | case LoongArch::VILVL_H: |
8822 | | case LoongArch::VILVL_W: |
8823 | | case LoongArch::VMAX_B: |
8824 | | case LoongArch::VMAX_BU: |
8825 | | case LoongArch::VMAX_D: |
8826 | | case LoongArch::VMAX_DU: |
8827 | | case LoongArch::VMAX_H: |
8828 | | case LoongArch::VMAX_HU: |
8829 | | case LoongArch::VMAX_W: |
8830 | | case LoongArch::VMAX_WU: |
8831 | | case LoongArch::VMIN_B: |
8832 | | case LoongArch::VMIN_BU: |
8833 | | case LoongArch::VMIN_D: |
8834 | | case LoongArch::VMIN_DU: |
8835 | | case LoongArch::VMIN_H: |
8836 | | case LoongArch::VMIN_HU: |
8837 | | case LoongArch::VMIN_W: |
8838 | | case LoongArch::VMIN_WU: |
8839 | | case LoongArch::VMOD_B: |
8840 | | case LoongArch::VMOD_BU: |
8841 | | case LoongArch::VMOD_D: |
8842 | | case LoongArch::VMOD_DU: |
8843 | | case LoongArch::VMOD_H: |
8844 | | case LoongArch::VMOD_HU: |
8845 | | case LoongArch::VMOD_W: |
8846 | | case LoongArch::VMOD_WU: |
8847 | | case LoongArch::VMUH_B: |
8848 | | case LoongArch::VMUH_BU: |
8849 | | case LoongArch::VMUH_D: |
8850 | | case LoongArch::VMUH_DU: |
8851 | | case LoongArch::VMUH_H: |
8852 | | case LoongArch::VMUH_HU: |
8853 | | case LoongArch::VMUH_W: |
8854 | | case LoongArch::VMUH_WU: |
8855 | | case LoongArch::VMULWEV_D_W: |
8856 | | case LoongArch::VMULWEV_D_WU: |
8857 | | case LoongArch::VMULWEV_D_WU_W: |
8858 | | case LoongArch::VMULWEV_H_B: |
8859 | | case LoongArch::VMULWEV_H_BU: |
8860 | | case LoongArch::VMULWEV_H_BU_B: |
8861 | | case LoongArch::VMULWEV_Q_D: |
8862 | | case LoongArch::VMULWEV_Q_DU: |
8863 | | case LoongArch::VMULWEV_Q_DU_D: |
8864 | | case LoongArch::VMULWEV_W_H: |
8865 | | case LoongArch::VMULWEV_W_HU: |
8866 | | case LoongArch::VMULWEV_W_HU_H: |
8867 | | case LoongArch::VMULWOD_D_W: |
8868 | | case LoongArch::VMULWOD_D_WU: |
8869 | | case LoongArch::VMULWOD_D_WU_W: |
8870 | | case LoongArch::VMULWOD_H_B: |
8871 | | case LoongArch::VMULWOD_H_BU: |
8872 | | case LoongArch::VMULWOD_H_BU_B: |
8873 | | case LoongArch::VMULWOD_Q_D: |
8874 | | case LoongArch::VMULWOD_Q_DU: |
8875 | | case LoongArch::VMULWOD_Q_DU_D: |
8876 | | case LoongArch::VMULWOD_W_H: |
8877 | | case LoongArch::VMULWOD_W_HU: |
8878 | | case LoongArch::VMULWOD_W_HU_H: |
8879 | | case LoongArch::VMUL_B: |
8880 | | case LoongArch::VMUL_D: |
8881 | | case LoongArch::VMUL_H: |
8882 | | case LoongArch::VMUL_W: |
8883 | | case LoongArch::VNOR_V: |
8884 | | case LoongArch::VORN_V: |
8885 | | case LoongArch::VOR_V: |
8886 | | case LoongArch::VPACKEV_B: |
8887 | | case LoongArch::VPACKEV_D: |
8888 | | case LoongArch::VPACKEV_H: |
8889 | | case LoongArch::VPACKEV_W: |
8890 | | case LoongArch::VPACKOD_B: |
8891 | | case LoongArch::VPACKOD_D: |
8892 | | case LoongArch::VPACKOD_H: |
8893 | | case LoongArch::VPACKOD_W: |
8894 | | case LoongArch::VPICKEV_B: |
8895 | | case LoongArch::VPICKEV_D: |
8896 | | case LoongArch::VPICKEV_H: |
8897 | | case LoongArch::VPICKEV_W: |
8898 | | case LoongArch::VPICKOD_B: |
8899 | | case LoongArch::VPICKOD_D: |
8900 | | case LoongArch::VPICKOD_H: |
8901 | | case LoongArch::VPICKOD_W: |
8902 | | case LoongArch::VROTR_B: |
8903 | | case LoongArch::VROTR_D: |
8904 | | case LoongArch::VROTR_H: |
8905 | | case LoongArch::VROTR_W: |
8906 | | case LoongArch::VSADD_B: |
8907 | | case LoongArch::VSADD_BU: |
8908 | | case LoongArch::VSADD_D: |
8909 | | case LoongArch::VSADD_DU: |
8910 | | case LoongArch::VSADD_H: |
8911 | | case LoongArch::VSADD_HU: |
8912 | | case LoongArch::VSADD_W: |
8913 | | case LoongArch::VSADD_WU: |
8914 | | case LoongArch::VSEQ_B: |
8915 | | case LoongArch::VSEQ_D: |
8916 | | case LoongArch::VSEQ_H: |
8917 | | case LoongArch::VSEQ_W: |
8918 | | case LoongArch::VSIGNCOV_B: |
8919 | | case LoongArch::VSIGNCOV_D: |
8920 | | case LoongArch::VSIGNCOV_H: |
8921 | | case LoongArch::VSIGNCOV_W: |
8922 | | case LoongArch::VSLE_B: |
8923 | | case LoongArch::VSLE_BU: |
8924 | | case LoongArch::VSLE_D: |
8925 | | case LoongArch::VSLE_DU: |
8926 | | case LoongArch::VSLE_H: |
8927 | | case LoongArch::VSLE_HU: |
8928 | | case LoongArch::VSLE_W: |
8929 | | case LoongArch::VSLE_WU: |
8930 | | case LoongArch::VSLL_B: |
8931 | | case LoongArch::VSLL_D: |
8932 | | case LoongArch::VSLL_H: |
8933 | | case LoongArch::VSLL_W: |
8934 | | case LoongArch::VSLT_B: |
8935 | | case LoongArch::VSLT_BU: |
8936 | | case LoongArch::VSLT_D: |
8937 | | case LoongArch::VSLT_DU: |
8938 | | case LoongArch::VSLT_H: |
8939 | | case LoongArch::VSLT_HU: |
8940 | | case LoongArch::VSLT_W: |
8941 | | case LoongArch::VSLT_WU: |
8942 | | case LoongArch::VSRAN_B_H: |
8943 | | case LoongArch::VSRAN_H_W: |
8944 | | case LoongArch::VSRAN_W_D: |
8945 | | case LoongArch::VSRARN_B_H: |
8946 | | case LoongArch::VSRARN_H_W: |
8947 | | case LoongArch::VSRARN_W_D: |
8948 | | case LoongArch::VSRAR_B: |
8949 | | case LoongArch::VSRAR_D: |
8950 | | case LoongArch::VSRAR_H: |
8951 | | case LoongArch::VSRAR_W: |
8952 | | case LoongArch::VSRA_B: |
8953 | | case LoongArch::VSRA_D: |
8954 | | case LoongArch::VSRA_H: |
8955 | | case LoongArch::VSRA_W: |
8956 | | case LoongArch::VSRLN_B_H: |
8957 | | case LoongArch::VSRLN_H_W: |
8958 | | case LoongArch::VSRLN_W_D: |
8959 | | case LoongArch::VSRLRN_B_H: |
8960 | | case LoongArch::VSRLRN_H_W: |
8961 | | case LoongArch::VSRLRN_W_D: |
8962 | | case LoongArch::VSRLR_B: |
8963 | | case LoongArch::VSRLR_D: |
8964 | | case LoongArch::VSRLR_H: |
8965 | | case LoongArch::VSRLR_W: |
8966 | | case LoongArch::VSRL_B: |
8967 | | case LoongArch::VSRL_D: |
8968 | | case LoongArch::VSRL_H: |
8969 | | case LoongArch::VSRL_W: |
8970 | | case LoongArch::VSSRAN_BU_H: |
8971 | | case LoongArch::VSSRAN_B_H: |
8972 | | case LoongArch::VSSRAN_HU_W: |
8973 | | case LoongArch::VSSRAN_H_W: |
8974 | | case LoongArch::VSSRAN_WU_D: |
8975 | | case LoongArch::VSSRAN_W_D: |
8976 | | case LoongArch::VSSRARN_BU_H: |
8977 | | case LoongArch::VSSRARN_B_H: |
8978 | | case LoongArch::VSSRARN_HU_W: |
8979 | | case LoongArch::VSSRARN_H_W: |
8980 | | case LoongArch::VSSRARN_WU_D: |
8981 | | case LoongArch::VSSRARN_W_D: |
8982 | | case LoongArch::VSSRLN_BU_H: |
8983 | | case LoongArch::VSSRLN_B_H: |
8984 | | case LoongArch::VSSRLN_HU_W: |
8985 | | case LoongArch::VSSRLN_H_W: |
8986 | | case LoongArch::VSSRLN_WU_D: |
8987 | | case LoongArch::VSSRLN_W_D: |
8988 | | case LoongArch::VSSRLRN_BU_H: |
8989 | | case LoongArch::VSSRLRN_B_H: |
8990 | | case LoongArch::VSSRLRN_HU_W: |
8991 | | case LoongArch::VSSRLRN_H_W: |
8992 | | case LoongArch::VSSRLRN_WU_D: |
8993 | | case LoongArch::VSSRLRN_W_D: |
8994 | | case LoongArch::VSSUB_B: |
8995 | | case LoongArch::VSSUB_BU: |
8996 | | case LoongArch::VSSUB_D: |
8997 | | case LoongArch::VSSUB_DU: |
8998 | | case LoongArch::VSSUB_H: |
8999 | | case LoongArch::VSSUB_HU: |
9000 | | case LoongArch::VSSUB_W: |
9001 | | case LoongArch::VSSUB_WU: |
9002 | | case LoongArch::VSUBWEV_D_W: |
9003 | | case LoongArch::VSUBWEV_D_WU: |
9004 | | case LoongArch::VSUBWEV_H_B: |
9005 | | case LoongArch::VSUBWEV_H_BU: |
9006 | | case LoongArch::VSUBWEV_Q_D: |
9007 | | case LoongArch::VSUBWEV_Q_DU: |
9008 | | case LoongArch::VSUBWEV_W_H: |
9009 | | case LoongArch::VSUBWEV_W_HU: |
9010 | | case LoongArch::VSUBWOD_D_W: |
9011 | | case LoongArch::VSUBWOD_D_WU: |
9012 | | case LoongArch::VSUBWOD_H_B: |
9013 | | case LoongArch::VSUBWOD_H_BU: |
9014 | | case LoongArch::VSUBWOD_Q_D: |
9015 | | case LoongArch::VSUBWOD_Q_DU: |
9016 | | case LoongArch::VSUBWOD_W_H: |
9017 | | case LoongArch::VSUBWOD_W_HU: |
9018 | | case LoongArch::VSUB_B: |
9019 | | case LoongArch::VSUB_D: |
9020 | | case LoongArch::VSUB_H: |
9021 | | case LoongArch::VSUB_Q: |
9022 | | case LoongArch::VSUB_W: |
9023 | | case LoongArch::VXOR_V: { |
9024 | | switch (OpNum) { |
9025 | | case 2: |
9026 | | // op: vk |
9027 | | return 10; |
9028 | | case 1: |
9029 | | // op: vj |
9030 | | return 5; |
9031 | | case 0: |
9032 | | // op: vd |
9033 | | return 0; |
9034 | | } |
9035 | | break; |
9036 | | } |
9037 | | case LoongArch::XVABSD_B: |
9038 | | case LoongArch::XVABSD_BU: |
9039 | | case LoongArch::XVABSD_D: |
9040 | | case LoongArch::XVABSD_DU: |
9041 | | case LoongArch::XVABSD_H: |
9042 | | case LoongArch::XVABSD_HU: |
9043 | | case LoongArch::XVABSD_W: |
9044 | | case LoongArch::XVABSD_WU: |
9045 | | case LoongArch::XVADDA_B: |
9046 | | case LoongArch::XVADDA_D: |
9047 | | case LoongArch::XVADDA_H: |
9048 | | case LoongArch::XVADDA_W: |
9049 | | case LoongArch::XVADDWEV_D_W: |
9050 | | case LoongArch::XVADDWEV_D_WU: |
9051 | | case LoongArch::XVADDWEV_D_WU_W: |
9052 | | case LoongArch::XVADDWEV_H_B: |
9053 | | case LoongArch::XVADDWEV_H_BU: |
9054 | | case LoongArch::XVADDWEV_H_BU_B: |
9055 | | case LoongArch::XVADDWEV_Q_D: |
9056 | | case LoongArch::XVADDWEV_Q_DU: |
9057 | | case LoongArch::XVADDWEV_Q_DU_D: |
9058 | | case LoongArch::XVADDWEV_W_H: |
9059 | | case LoongArch::XVADDWEV_W_HU: |
9060 | | case LoongArch::XVADDWEV_W_HU_H: |
9061 | | case LoongArch::XVADDWOD_D_W: |
9062 | | case LoongArch::XVADDWOD_D_WU: |
9063 | | case LoongArch::XVADDWOD_D_WU_W: |
9064 | | case LoongArch::XVADDWOD_H_B: |
9065 | | case LoongArch::XVADDWOD_H_BU: |
9066 | | case LoongArch::XVADDWOD_H_BU_B: |
9067 | | case LoongArch::XVADDWOD_Q_D: |
9068 | | case LoongArch::XVADDWOD_Q_DU: |
9069 | | case LoongArch::XVADDWOD_Q_DU_D: |
9070 | | case LoongArch::XVADDWOD_W_H: |
9071 | | case LoongArch::XVADDWOD_W_HU: |
9072 | | case LoongArch::XVADDWOD_W_HU_H: |
9073 | | case LoongArch::XVADD_B: |
9074 | | case LoongArch::XVADD_D: |
9075 | | case LoongArch::XVADD_H: |
9076 | | case LoongArch::XVADD_Q: |
9077 | | case LoongArch::XVADD_W: |
9078 | | case LoongArch::XVANDN_V: |
9079 | | case LoongArch::XVAND_V: |
9080 | | case LoongArch::XVAVGR_B: |
9081 | | case LoongArch::XVAVGR_BU: |
9082 | | case LoongArch::XVAVGR_D: |
9083 | | case LoongArch::XVAVGR_DU: |
9084 | | case LoongArch::XVAVGR_H: |
9085 | | case LoongArch::XVAVGR_HU: |
9086 | | case LoongArch::XVAVGR_W: |
9087 | | case LoongArch::XVAVGR_WU: |
9088 | | case LoongArch::XVAVG_B: |
9089 | | case LoongArch::XVAVG_BU: |
9090 | | case LoongArch::XVAVG_D: |
9091 | | case LoongArch::XVAVG_DU: |
9092 | | case LoongArch::XVAVG_H: |
9093 | | case LoongArch::XVAVG_HU: |
9094 | | case LoongArch::XVAVG_W: |
9095 | | case LoongArch::XVAVG_WU: |
9096 | | case LoongArch::XVBITCLR_B: |
9097 | | case LoongArch::XVBITCLR_D: |
9098 | | case LoongArch::XVBITCLR_H: |
9099 | | case LoongArch::XVBITCLR_W: |
9100 | | case LoongArch::XVBITREV_B: |
9101 | | case LoongArch::XVBITREV_D: |
9102 | | case LoongArch::XVBITREV_H: |
9103 | | case LoongArch::XVBITREV_W: |
9104 | | case LoongArch::XVBITSET_B: |
9105 | | case LoongArch::XVBITSET_D: |
9106 | | case LoongArch::XVBITSET_H: |
9107 | | case LoongArch::XVBITSET_W: |
9108 | | case LoongArch::XVDIV_B: |
9109 | | case LoongArch::XVDIV_BU: |
9110 | | case LoongArch::XVDIV_D: |
9111 | | case LoongArch::XVDIV_DU: |
9112 | | case LoongArch::XVDIV_H: |
9113 | | case LoongArch::XVDIV_HU: |
9114 | | case LoongArch::XVDIV_W: |
9115 | | case LoongArch::XVDIV_WU: |
9116 | | case LoongArch::XVFADD_D: |
9117 | | case LoongArch::XVFADD_S: |
9118 | | case LoongArch::XVFCMP_CAF_D: |
9119 | | case LoongArch::XVFCMP_CAF_S: |
9120 | | case LoongArch::XVFCMP_CEQ_D: |
9121 | | case LoongArch::XVFCMP_CEQ_S: |
9122 | | case LoongArch::XVFCMP_CLE_D: |
9123 | | case LoongArch::XVFCMP_CLE_S: |
9124 | | case LoongArch::XVFCMP_CLT_D: |
9125 | | case LoongArch::XVFCMP_CLT_S: |
9126 | | case LoongArch::XVFCMP_CNE_D: |
9127 | | case LoongArch::XVFCMP_CNE_S: |
9128 | | case LoongArch::XVFCMP_COR_D: |
9129 | | case LoongArch::XVFCMP_COR_S: |
9130 | | case LoongArch::XVFCMP_CUEQ_D: |
9131 | | case LoongArch::XVFCMP_CUEQ_S: |
9132 | | case LoongArch::XVFCMP_CULE_D: |
9133 | | case LoongArch::XVFCMP_CULE_S: |
9134 | | case LoongArch::XVFCMP_CULT_D: |
9135 | | case LoongArch::XVFCMP_CULT_S: |
9136 | | case LoongArch::XVFCMP_CUNE_D: |
9137 | | case LoongArch::XVFCMP_CUNE_S: |
9138 | | case LoongArch::XVFCMP_CUN_D: |
9139 | | case LoongArch::XVFCMP_CUN_S: |
9140 | | case LoongArch::XVFCMP_SAF_D: |
9141 | | case LoongArch::XVFCMP_SAF_S: |
9142 | | case LoongArch::XVFCMP_SEQ_D: |
9143 | | case LoongArch::XVFCMP_SEQ_S: |
9144 | | case LoongArch::XVFCMP_SLE_D: |
9145 | | case LoongArch::XVFCMP_SLE_S: |
9146 | | case LoongArch::XVFCMP_SLT_D: |
9147 | | case LoongArch::XVFCMP_SLT_S: |
9148 | | case LoongArch::XVFCMP_SNE_D: |
9149 | | case LoongArch::XVFCMP_SNE_S: |
9150 | | case LoongArch::XVFCMP_SOR_D: |
9151 | | case LoongArch::XVFCMP_SOR_S: |
9152 | | case LoongArch::XVFCMP_SUEQ_D: |
9153 | | case LoongArch::XVFCMP_SUEQ_S: |
9154 | | case LoongArch::XVFCMP_SULE_D: |
9155 | | case LoongArch::XVFCMP_SULE_S: |
9156 | | case LoongArch::XVFCMP_SULT_D: |
9157 | | case LoongArch::XVFCMP_SULT_S: |
9158 | | case LoongArch::XVFCMP_SUNE_D: |
9159 | | case LoongArch::XVFCMP_SUNE_S: |
9160 | | case LoongArch::XVFCMP_SUN_D: |
9161 | | case LoongArch::XVFCMP_SUN_S: |
9162 | | case LoongArch::XVFCVT_H_S: |
9163 | | case LoongArch::XVFCVT_S_D: |
9164 | | case LoongArch::XVFDIV_D: |
9165 | | case LoongArch::XVFDIV_S: |
9166 | | case LoongArch::XVFFINT_S_L: |
9167 | | case LoongArch::XVFMAXA_D: |
9168 | | case LoongArch::XVFMAXA_S: |
9169 | | case LoongArch::XVFMAX_D: |
9170 | | case LoongArch::XVFMAX_S: |
9171 | | case LoongArch::XVFMINA_D: |
9172 | | case LoongArch::XVFMINA_S: |
9173 | | case LoongArch::XVFMIN_D: |
9174 | | case LoongArch::XVFMIN_S: |
9175 | | case LoongArch::XVFMUL_D: |
9176 | | case LoongArch::XVFMUL_S: |
9177 | | case LoongArch::XVFSUB_D: |
9178 | | case LoongArch::XVFSUB_S: |
9179 | | case LoongArch::XVFTINTRM_W_D: |
9180 | | case LoongArch::XVFTINTRNE_W_D: |
9181 | | case LoongArch::XVFTINTRP_W_D: |
9182 | | case LoongArch::XVFTINTRZ_W_D: |
9183 | | case LoongArch::XVFTINT_W_D: |
9184 | | case LoongArch::XVHADDW_DU_WU: |
9185 | | case LoongArch::XVHADDW_D_W: |
9186 | | case LoongArch::XVHADDW_HU_BU: |
9187 | | case LoongArch::XVHADDW_H_B: |
9188 | | case LoongArch::XVHADDW_QU_DU: |
9189 | | case LoongArch::XVHADDW_Q_D: |
9190 | | case LoongArch::XVHADDW_WU_HU: |
9191 | | case LoongArch::XVHADDW_W_H: |
9192 | | case LoongArch::XVHSUBW_DU_WU: |
9193 | | case LoongArch::XVHSUBW_D_W: |
9194 | | case LoongArch::XVHSUBW_HU_BU: |
9195 | | case LoongArch::XVHSUBW_H_B: |
9196 | | case LoongArch::XVHSUBW_QU_DU: |
9197 | | case LoongArch::XVHSUBW_Q_D: |
9198 | | case LoongArch::XVHSUBW_WU_HU: |
9199 | | case LoongArch::XVHSUBW_W_H: |
9200 | | case LoongArch::XVILVH_B: |
9201 | | case LoongArch::XVILVH_D: |
9202 | | case LoongArch::XVILVH_H: |
9203 | | case LoongArch::XVILVH_W: |
9204 | | case LoongArch::XVILVL_B: |
9205 | | case LoongArch::XVILVL_D: |
9206 | | case LoongArch::XVILVL_H: |
9207 | | case LoongArch::XVILVL_W: |
9208 | | case LoongArch::XVMAX_B: |
9209 | | case LoongArch::XVMAX_BU: |
9210 | | case LoongArch::XVMAX_D: |
9211 | | case LoongArch::XVMAX_DU: |
9212 | | case LoongArch::XVMAX_H: |
9213 | | case LoongArch::XVMAX_HU: |
9214 | | case LoongArch::XVMAX_W: |
9215 | | case LoongArch::XVMAX_WU: |
9216 | | case LoongArch::XVMIN_B: |
9217 | | case LoongArch::XVMIN_BU: |
9218 | | case LoongArch::XVMIN_D: |
9219 | | case LoongArch::XVMIN_DU: |
9220 | | case LoongArch::XVMIN_H: |
9221 | | case LoongArch::XVMIN_HU: |
9222 | | case LoongArch::XVMIN_W: |
9223 | | case LoongArch::XVMIN_WU: |
9224 | | case LoongArch::XVMOD_B: |
9225 | | case LoongArch::XVMOD_BU: |
9226 | | case LoongArch::XVMOD_D: |
9227 | | case LoongArch::XVMOD_DU: |
9228 | | case LoongArch::XVMOD_H: |
9229 | | case LoongArch::XVMOD_HU: |
9230 | | case LoongArch::XVMOD_W: |
9231 | | case LoongArch::XVMOD_WU: |
9232 | | case LoongArch::XVMUH_B: |
9233 | | case LoongArch::XVMUH_BU: |
9234 | | case LoongArch::XVMUH_D: |
9235 | | case LoongArch::XVMUH_DU: |
9236 | | case LoongArch::XVMUH_H: |
9237 | | case LoongArch::XVMUH_HU: |
9238 | | case LoongArch::XVMUH_W: |
9239 | | case LoongArch::XVMUH_WU: |
9240 | | case LoongArch::XVMULWEV_D_W: |
9241 | | case LoongArch::XVMULWEV_D_WU: |
9242 | | case LoongArch::XVMULWEV_D_WU_W: |
9243 | | case LoongArch::XVMULWEV_H_B: |
9244 | | case LoongArch::XVMULWEV_H_BU: |
9245 | | case LoongArch::XVMULWEV_H_BU_B: |
9246 | | case LoongArch::XVMULWEV_Q_D: |
9247 | | case LoongArch::XVMULWEV_Q_DU: |
9248 | | case LoongArch::XVMULWEV_Q_DU_D: |
9249 | | case LoongArch::XVMULWEV_W_H: |
9250 | | case LoongArch::XVMULWEV_W_HU: |
9251 | | case LoongArch::XVMULWEV_W_HU_H: |
9252 | | case LoongArch::XVMULWOD_D_W: |
9253 | | case LoongArch::XVMULWOD_D_WU: |
9254 | | case LoongArch::XVMULWOD_D_WU_W: |
9255 | | case LoongArch::XVMULWOD_H_B: |
9256 | | case LoongArch::XVMULWOD_H_BU: |
9257 | | case LoongArch::XVMULWOD_H_BU_B: |
9258 | | case LoongArch::XVMULWOD_Q_D: |
9259 | | case LoongArch::XVMULWOD_Q_DU: |
9260 | | case LoongArch::XVMULWOD_Q_DU_D: |
9261 | | case LoongArch::XVMULWOD_W_H: |
9262 | | case LoongArch::XVMULWOD_W_HU: |
9263 | | case LoongArch::XVMULWOD_W_HU_H: |
9264 | | case LoongArch::XVMUL_B: |
9265 | | case LoongArch::XVMUL_D: |
9266 | | case LoongArch::XVMUL_H: |
9267 | | case LoongArch::XVMUL_W: |
9268 | | case LoongArch::XVNOR_V: |
9269 | | case LoongArch::XVORN_V: |
9270 | | case LoongArch::XVOR_V: |
9271 | | case LoongArch::XVPACKEV_B: |
9272 | | case LoongArch::XVPACKEV_D: |
9273 | | case LoongArch::XVPACKEV_H: |
9274 | | case LoongArch::XVPACKEV_W: |
9275 | | case LoongArch::XVPACKOD_B: |
9276 | | case LoongArch::XVPACKOD_D: |
9277 | | case LoongArch::XVPACKOD_H: |
9278 | | case LoongArch::XVPACKOD_W: |
9279 | | case LoongArch::XVPERM_W: |
9280 | | case LoongArch::XVPICKEV_B: |
9281 | | case LoongArch::XVPICKEV_D: |
9282 | | case LoongArch::XVPICKEV_H: |
9283 | | case LoongArch::XVPICKEV_W: |
9284 | | case LoongArch::XVPICKOD_B: |
9285 | | case LoongArch::XVPICKOD_D: |
9286 | | case LoongArch::XVPICKOD_H: |
9287 | | case LoongArch::XVPICKOD_W: |
9288 | | case LoongArch::XVROTR_B: |
9289 | | case LoongArch::XVROTR_D: |
9290 | | case LoongArch::XVROTR_H: |
9291 | | case LoongArch::XVROTR_W: |
9292 | | case LoongArch::XVSADD_B: |
9293 | | case LoongArch::XVSADD_BU: |
9294 | | case LoongArch::XVSADD_D: |
9295 | | case LoongArch::XVSADD_DU: |
9296 | | case LoongArch::XVSADD_H: |
9297 | | case LoongArch::XVSADD_HU: |
9298 | | case LoongArch::XVSADD_W: |
9299 | | case LoongArch::XVSADD_WU: |
9300 | | case LoongArch::XVSEQ_B: |
9301 | | case LoongArch::XVSEQ_D: |
9302 | | case LoongArch::XVSEQ_H: |
9303 | | case LoongArch::XVSEQ_W: |
9304 | | case LoongArch::XVSIGNCOV_B: |
9305 | | case LoongArch::XVSIGNCOV_D: |
9306 | | case LoongArch::XVSIGNCOV_H: |
9307 | | case LoongArch::XVSIGNCOV_W: |
9308 | | case LoongArch::XVSLE_B: |
9309 | | case LoongArch::XVSLE_BU: |
9310 | | case LoongArch::XVSLE_D: |
9311 | | case LoongArch::XVSLE_DU: |
9312 | | case LoongArch::XVSLE_H: |
9313 | | case LoongArch::XVSLE_HU: |
9314 | | case LoongArch::XVSLE_W: |
9315 | | case LoongArch::XVSLE_WU: |
9316 | | case LoongArch::XVSLL_B: |
9317 | | case LoongArch::XVSLL_D: |
9318 | | case LoongArch::XVSLL_H: |
9319 | | case LoongArch::XVSLL_W: |
9320 | | case LoongArch::XVSLT_B: |
9321 | | case LoongArch::XVSLT_BU: |
9322 | | case LoongArch::XVSLT_D: |
9323 | | case LoongArch::XVSLT_DU: |
9324 | | case LoongArch::XVSLT_H: |
9325 | | case LoongArch::XVSLT_HU: |
9326 | | case LoongArch::XVSLT_W: |
9327 | | case LoongArch::XVSLT_WU: |
9328 | | case LoongArch::XVSRAN_B_H: |
9329 | | case LoongArch::XVSRAN_H_W: |
9330 | | case LoongArch::XVSRAN_W_D: |
9331 | | case LoongArch::XVSRARN_B_H: |
9332 | | case LoongArch::XVSRARN_H_W: |
9333 | | case LoongArch::XVSRARN_W_D: |
9334 | | case LoongArch::XVSRAR_B: |
9335 | | case LoongArch::XVSRAR_D: |
9336 | | case LoongArch::XVSRAR_H: |
9337 | | case LoongArch::XVSRAR_W: |
9338 | | case LoongArch::XVSRA_B: |
9339 | | case LoongArch::XVSRA_D: |
9340 | | case LoongArch::XVSRA_H: |
9341 | | case LoongArch::XVSRA_W: |
9342 | | case LoongArch::XVSRLN_B_H: |
9343 | | case LoongArch::XVSRLN_H_W: |
9344 | | case LoongArch::XVSRLN_W_D: |
9345 | | case LoongArch::XVSRLRN_B_H: |
9346 | | case LoongArch::XVSRLRN_H_W: |
9347 | | case LoongArch::XVSRLRN_W_D: |
9348 | | case LoongArch::XVSRLR_B: |
9349 | | case LoongArch::XVSRLR_D: |
9350 | | case LoongArch::XVSRLR_H: |
9351 | | case LoongArch::XVSRLR_W: |
9352 | | case LoongArch::XVSRL_B: |
9353 | | case LoongArch::XVSRL_D: |
9354 | | case LoongArch::XVSRL_H: |
9355 | | case LoongArch::XVSRL_W: |
9356 | | case LoongArch::XVSSRAN_BU_H: |
9357 | | case LoongArch::XVSSRAN_B_H: |
9358 | | case LoongArch::XVSSRAN_HU_W: |
9359 | | case LoongArch::XVSSRAN_H_W: |
9360 | | case LoongArch::XVSSRAN_WU_D: |
9361 | | case LoongArch::XVSSRAN_W_D: |
9362 | | case LoongArch::XVSSRARN_BU_H: |
9363 | | case LoongArch::XVSSRARN_B_H: |
9364 | | case LoongArch::XVSSRARN_HU_W: |
9365 | | case LoongArch::XVSSRARN_H_W: |
9366 | | case LoongArch::XVSSRARN_WU_D: |
9367 | | case LoongArch::XVSSRARN_W_D: |
9368 | | case LoongArch::XVSSRLN_BU_H: |
9369 | | case LoongArch::XVSSRLN_B_H: |
9370 | | case LoongArch::XVSSRLN_HU_W: |
9371 | | case LoongArch::XVSSRLN_H_W: |
9372 | | case LoongArch::XVSSRLN_WU_D: |
9373 | | case LoongArch::XVSSRLN_W_D: |
9374 | | case LoongArch::XVSSRLRN_BU_H: |
9375 | | case LoongArch::XVSSRLRN_B_H: |
9376 | | case LoongArch::XVSSRLRN_HU_W: |
9377 | | case LoongArch::XVSSRLRN_H_W: |
9378 | | case LoongArch::XVSSRLRN_WU_D: |
9379 | | case LoongArch::XVSSRLRN_W_D: |
9380 | | case LoongArch::XVSSUB_B: |
9381 | | case LoongArch::XVSSUB_BU: |
9382 | | case LoongArch::XVSSUB_D: |
9383 | | case LoongArch::XVSSUB_DU: |
9384 | | case LoongArch::XVSSUB_H: |
9385 | | case LoongArch::XVSSUB_HU: |
9386 | | case LoongArch::XVSSUB_W: |
9387 | | case LoongArch::XVSSUB_WU: |
9388 | | case LoongArch::XVSUBWEV_D_W: |
9389 | | case LoongArch::XVSUBWEV_D_WU: |
9390 | | case LoongArch::XVSUBWEV_H_B: |
9391 | | case LoongArch::XVSUBWEV_H_BU: |
9392 | | case LoongArch::XVSUBWEV_Q_D: |
9393 | | case LoongArch::XVSUBWEV_Q_DU: |
9394 | | case LoongArch::XVSUBWEV_W_H: |
9395 | | case LoongArch::XVSUBWEV_W_HU: |
9396 | | case LoongArch::XVSUBWOD_D_W: |
9397 | | case LoongArch::XVSUBWOD_D_WU: |
9398 | | case LoongArch::XVSUBWOD_H_B: |
9399 | | case LoongArch::XVSUBWOD_H_BU: |
9400 | | case LoongArch::XVSUBWOD_Q_D: |
9401 | | case LoongArch::XVSUBWOD_Q_DU: |
9402 | | case LoongArch::XVSUBWOD_W_H: |
9403 | | case LoongArch::XVSUBWOD_W_HU: |
9404 | | case LoongArch::XVSUB_B: |
9405 | | case LoongArch::XVSUB_D: |
9406 | | case LoongArch::XVSUB_H: |
9407 | | case LoongArch::XVSUB_Q: |
9408 | | case LoongArch::XVSUB_W: |
9409 | | case LoongArch::XVXOR_V: { |
9410 | | switch (OpNum) { |
9411 | | case 2: |
9412 | | // op: xk |
9413 | | return 10; |
9414 | | case 1: |
9415 | | // op: xj |
9416 | | return 5; |
9417 | | case 0: |
9418 | | // op: xd |
9419 | | return 0; |
9420 | | } |
9421 | | break; |
9422 | | } |
9423 | | case LoongArch::FSEL_xD: |
9424 | | case LoongArch::FSEL_xS: { |
9425 | | switch (OpNum) { |
9426 | | case 3: |
9427 | | // op: ca |
9428 | | return 15; |
9429 | | case 2: |
9430 | | // op: fk |
9431 | | return 10; |
9432 | | case 1: |
9433 | | // op: fj |
9434 | | return 5; |
9435 | | case 0: |
9436 | | // op: fd |
9437 | | return 0; |
9438 | | } |
9439 | | break; |
9440 | | } |
9441 | | case LoongArch::CSRXCHG: |
9442 | | case LoongArch::GCSRXCHG: { |
9443 | | switch (OpNum) { |
9444 | | case 3: |
9445 | | // op: csr_num |
9446 | | return 10; |
9447 | | case 2: |
9448 | | // op: rj |
9449 | | return 5; |
9450 | | case 1: |
9451 | | // op: rd |
9452 | | return 0; |
9453 | | } |
9454 | | break; |
9455 | | } |
9456 | | case LoongArch::FMADD_D: |
9457 | | case LoongArch::FMADD_S: |
9458 | | case LoongArch::FMSUB_D: |
9459 | | case LoongArch::FMSUB_S: |
9460 | | case LoongArch::FNMADD_D: |
9461 | | case LoongArch::FNMADD_S: |
9462 | | case LoongArch::FNMSUB_D: |
9463 | | case LoongArch::FNMSUB_S: { |
9464 | | switch (OpNum) { |
9465 | | case 3: |
9466 | | // op: fa |
9467 | | return 15; |
9468 | | case 2: |
9469 | | // op: fk |
9470 | | return 10; |
9471 | | case 1: |
9472 | | // op: fj |
9473 | | return 5; |
9474 | | case 0: |
9475 | | // op: fd |
9476 | | return 0; |
9477 | | } |
9478 | | break; |
9479 | | } |
9480 | | case LoongArch::VINSGR2VR_D: { |
9481 | | switch (OpNum) { |
9482 | | case 3: |
9483 | | // op: imm1 |
9484 | | return 10; |
9485 | | case 2: |
9486 | | // op: rj |
9487 | | return 5; |
9488 | | case 1: |
9489 | | // op: vd |
9490 | | return 0; |
9491 | | } |
9492 | | break; |
9493 | | } |
9494 | | case LoongArch::VSTELM_D: { |
9495 | | switch (OpNum) { |
9496 | | case 3: |
9497 | | // op: imm1 |
9498 | | return 18; |
9499 | | case 2: |
9500 | | // op: imm8 |
9501 | | return 10; |
9502 | | case 1: |
9503 | | // op: rj |
9504 | | return 5; |
9505 | | case 0: |
9506 | | // op: vd |
9507 | | return 0; |
9508 | | } |
9509 | | break; |
9510 | | } |
9511 | | case LoongArch::SC_D: |
9512 | | case LoongArch::SC_W: { |
9513 | | switch (OpNum) { |
9514 | | case 3: |
9515 | | // op: imm14 |
9516 | | return 10; |
9517 | | case 2: |
9518 | | // op: rj |
9519 | | return 5; |
9520 | | case 1: |
9521 | | // op: rd |
9522 | | return 0; |
9523 | | } |
9524 | | break; |
9525 | | } |
9526 | | case LoongArch::VINSGR2VR_W: { |
9527 | | switch (OpNum) { |
9528 | | case 3: |
9529 | | // op: imm2 |
9530 | | return 10; |
9531 | | case 2: |
9532 | | // op: rj |
9533 | | return 5; |
9534 | | case 1: |
9535 | | // op: vd |
9536 | | return 0; |
9537 | | } |
9538 | | break; |
9539 | | } |
9540 | | case LoongArch::XVINSGR2VR_D: { |
9541 | | switch (OpNum) { |
9542 | | case 3: |
9543 | | // op: imm2 |
9544 | | return 10; |
9545 | | case 2: |
9546 | | // op: rj |
9547 | | return 5; |
9548 | | case 1: |
9549 | | // op: xd |
9550 | | return 0; |
9551 | | } |
9552 | | break; |
9553 | | } |
9554 | | case LoongArch::XVINSVE0_D: { |
9555 | | switch (OpNum) { |
9556 | | case 3: |
9557 | | // op: imm2 |
9558 | | return 10; |
9559 | | case 2: |
9560 | | // op: xj |
9561 | | return 5; |
9562 | | case 1: |
9563 | | // op: xd |
9564 | | return 0; |
9565 | | } |
9566 | | break; |
9567 | | } |
9568 | | case LoongArch::ALSL_D: |
9569 | | case LoongArch::ALSL_W: |
9570 | | case LoongArch::ALSL_WU: |
9571 | | case LoongArch::BYTEPICK_W: { |
9572 | | switch (OpNum) { |
9573 | | case 3: |
9574 | | // op: imm2 |
9575 | | return 15; |
9576 | | case 2: |
9577 | | // op: rk |
9578 | | return 10; |
9579 | | case 1: |
9580 | | // op: rj |
9581 | | return 5; |
9582 | | case 0: |
9583 | | // op: rd |
9584 | | return 0; |
9585 | | } |
9586 | | break; |
9587 | | } |
9588 | | case LoongArch::VSTELM_W: { |
9589 | | switch (OpNum) { |
9590 | | case 3: |
9591 | | // op: imm2 |
9592 | | return 18; |
9593 | | case 2: |
9594 | | // op: imm8 |
9595 | | return 10; |
9596 | | case 1: |
9597 | | // op: rj |
9598 | | return 5; |
9599 | | case 0: |
9600 | | // op: vd |
9601 | | return 0; |
9602 | | } |
9603 | | break; |
9604 | | } |
9605 | | case LoongArch::XVSTELM_D: { |
9606 | | switch (OpNum) { |
9607 | | case 3: |
9608 | | // op: imm2 |
9609 | | return 18; |
9610 | | case 2: |
9611 | | // op: imm8 |
9612 | | return 10; |
9613 | | case 1: |
9614 | | // op: rj |
9615 | | return 5; |
9616 | | case 0: |
9617 | | // op: xd |
9618 | | return 0; |
9619 | | } |
9620 | | break; |
9621 | | } |
9622 | | case LoongArch::VINSGR2VR_H: { |
9623 | | switch (OpNum) { |
9624 | | case 3: |
9625 | | // op: imm3 |
9626 | | return 10; |
9627 | | case 2: |
9628 | | // op: rj |
9629 | | return 5; |
9630 | | case 1: |
9631 | | // op: vd |
9632 | | return 0; |
9633 | | } |
9634 | | break; |
9635 | | } |
9636 | | case LoongArch::XVINSGR2VR_W: { |
9637 | | switch (OpNum) { |
9638 | | case 3: |
9639 | | // op: imm3 |
9640 | | return 10; |
9641 | | case 2: |
9642 | | // op: rj |
9643 | | return 5; |
9644 | | case 1: |
9645 | | // op: xd |
9646 | | return 0; |
9647 | | } |
9648 | | break; |
9649 | | } |
9650 | | case LoongArch::XVINSVE0_W: { |
9651 | | switch (OpNum) { |
9652 | | case 3: |
9653 | | // op: imm3 |
9654 | | return 10; |
9655 | | case 2: |
9656 | | // op: xj |
9657 | | return 5; |
9658 | | case 1: |
9659 | | // op: xd |
9660 | | return 0; |
9661 | | } |
9662 | | break; |
9663 | | } |
9664 | | case LoongArch::BYTEPICK_D: { |
9665 | | switch (OpNum) { |
9666 | | case 3: |
9667 | | // op: imm3 |
9668 | | return 15; |
9669 | | case 2: |
9670 | | // op: rk |
9671 | | return 10; |
9672 | | case 1: |
9673 | | // op: rj |
9674 | | return 5; |
9675 | | case 0: |
9676 | | // op: rd |
9677 | | return 0; |
9678 | | } |
9679 | | break; |
9680 | | } |
9681 | | case LoongArch::VSTELM_H: { |
9682 | | switch (OpNum) { |
9683 | | case 3: |
9684 | | // op: imm3 |
9685 | | return 18; |
9686 | | case 2: |
9687 | | // op: imm8 |
9688 | | return 10; |
9689 | | case 1: |
9690 | | // op: rj |
9691 | | return 5; |
9692 | | case 0: |
9693 | | // op: vd |
9694 | | return 0; |
9695 | | } |
9696 | | break; |
9697 | | } |
9698 | | case LoongArch::XVSTELM_W: { |
9699 | | switch (OpNum) { |
9700 | | case 3: |
9701 | | // op: imm3 |
9702 | | return 18; |
9703 | | case 2: |
9704 | | // op: imm8 |
9705 | | return 10; |
9706 | | case 1: |
9707 | | // op: rj |
9708 | | return 5; |
9709 | | case 0: |
9710 | | // op: xd |
9711 | | return 0; |
9712 | | } |
9713 | | break; |
9714 | | } |
9715 | | case LoongArch::VINSGR2VR_B: { |
9716 | | switch (OpNum) { |
9717 | | case 3: |
9718 | | // op: imm4 |
9719 | | return 10; |
9720 | | case 2: |
9721 | | // op: rj |
9722 | | return 5; |
9723 | | case 1: |
9724 | | // op: vd |
9725 | | return 0; |
9726 | | } |
9727 | | break; |
9728 | | } |
9729 | | case LoongArch::VSRANI_B_H: |
9730 | | case LoongArch::VSRARNI_B_H: |
9731 | | case LoongArch::VSRLNI_B_H: |
9732 | | case LoongArch::VSRLRNI_B_H: |
9733 | | case LoongArch::VSSRANI_BU_H: |
9734 | | case LoongArch::VSSRANI_B_H: |
9735 | | case LoongArch::VSSRARNI_BU_H: |
9736 | | case LoongArch::VSSRARNI_B_H: |
9737 | | case LoongArch::VSSRLNI_BU_H: |
9738 | | case LoongArch::VSSRLNI_B_H: |
9739 | | case LoongArch::VSSRLRNI_BU_H: |
9740 | | case LoongArch::VSSRLRNI_B_H: { |
9741 | | switch (OpNum) { |
9742 | | case 3: |
9743 | | // op: imm4 |
9744 | | return 10; |
9745 | | case 2: |
9746 | | // op: vj |
9747 | | return 5; |
9748 | | case 1: |
9749 | | // op: vd |
9750 | | return 0; |
9751 | | } |
9752 | | break; |
9753 | | } |
9754 | | case LoongArch::XVSRANI_B_H: |
9755 | | case LoongArch::XVSRARNI_B_H: |
9756 | | case LoongArch::XVSRLNI_B_H: |
9757 | | case LoongArch::XVSRLRNI_B_H: |
9758 | | case LoongArch::XVSSRANI_BU_H: |
9759 | | case LoongArch::XVSSRANI_B_H: |
9760 | | case LoongArch::XVSSRARNI_BU_H: |
9761 | | case LoongArch::XVSSRARNI_B_H: |
9762 | | case LoongArch::XVSSRLNI_BU_H: |
9763 | | case LoongArch::XVSSRLNI_B_H: |
9764 | | case LoongArch::XVSSRLRNI_BU_H: |
9765 | | case LoongArch::XVSSRLRNI_B_H: { |
9766 | | switch (OpNum) { |
9767 | | case 3: |
9768 | | // op: imm4 |
9769 | | return 10; |
9770 | | case 2: |
9771 | | // op: xj |
9772 | | return 5; |
9773 | | case 1: |
9774 | | // op: xd |
9775 | | return 0; |
9776 | | } |
9777 | | break; |
9778 | | } |
9779 | | case LoongArch::VSTELM_B: { |
9780 | | switch (OpNum) { |
9781 | | case 3: |
9782 | | // op: imm4 |
9783 | | return 18; |
9784 | | case 2: |
9785 | | // op: imm8 |
9786 | | return 10; |
9787 | | case 1: |
9788 | | // op: rj |
9789 | | return 5; |
9790 | | case 0: |
9791 | | // op: vd |
9792 | | return 0; |
9793 | | } |
9794 | | break; |
9795 | | } |
9796 | | case LoongArch::XVSTELM_H: { |
9797 | | switch (OpNum) { |
9798 | | case 3: |
9799 | | // op: imm4 |
9800 | | return 18; |
9801 | | case 2: |
9802 | | // op: imm8 |
9803 | | return 10; |
9804 | | case 1: |
9805 | | // op: rj |
9806 | | return 5; |
9807 | | case 0: |
9808 | | // op: xd |
9809 | | return 0; |
9810 | | } |
9811 | | break; |
9812 | | } |
9813 | | case LoongArch::VFRSTPI_B: |
9814 | | case LoongArch::VFRSTPI_H: |
9815 | | case LoongArch::VSRANI_H_W: |
9816 | | case LoongArch::VSRARNI_H_W: |
9817 | | case LoongArch::VSRLNI_H_W: |
9818 | | case LoongArch::VSRLRNI_H_W: |
9819 | | case LoongArch::VSSRANI_HU_W: |
9820 | | case LoongArch::VSSRANI_H_W: |
9821 | | case LoongArch::VSSRARNI_HU_W: |
9822 | | case LoongArch::VSSRARNI_H_W: |
9823 | | case LoongArch::VSSRLNI_HU_W: |
9824 | | case LoongArch::VSSRLNI_H_W: |
9825 | | case LoongArch::VSSRLRNI_HU_W: |
9826 | | case LoongArch::VSSRLRNI_H_W: { |
9827 | | switch (OpNum) { |
9828 | | case 3: |
9829 | | // op: imm5 |
9830 | | return 10; |
9831 | | case 2: |
9832 | | // op: vj |
9833 | | return 5; |
9834 | | case 1: |
9835 | | // op: vd |
9836 | | return 0; |
9837 | | } |
9838 | | break; |
9839 | | } |
9840 | | case LoongArch::XVFRSTPI_B: |
9841 | | case LoongArch::XVFRSTPI_H: |
9842 | | case LoongArch::XVSRANI_H_W: |
9843 | | case LoongArch::XVSRARNI_H_W: |
9844 | | case LoongArch::XVSRLNI_H_W: |
9845 | | case LoongArch::XVSRLRNI_H_W: |
9846 | | case LoongArch::XVSSRANI_HU_W: |
9847 | | case LoongArch::XVSSRANI_H_W: |
9848 | | case LoongArch::XVSSRARNI_HU_W: |
9849 | | case LoongArch::XVSSRARNI_H_W: |
9850 | | case LoongArch::XVSSRLNI_HU_W: |
9851 | | case LoongArch::XVSSRLNI_H_W: |
9852 | | case LoongArch::XVSSRLRNI_HU_W: |
9853 | | case LoongArch::XVSSRLRNI_H_W: { |
9854 | | switch (OpNum) { |
9855 | | case 3: |
9856 | | // op: imm5 |
9857 | | return 10; |
9858 | | case 2: |
9859 | | // op: xj |
9860 | | return 5; |
9861 | | case 1: |
9862 | | // op: xd |
9863 | | return 0; |
9864 | | } |
9865 | | break; |
9866 | | } |
9867 | | case LoongArch::XVSTELM_B: { |
9868 | | switch (OpNum) { |
9869 | | case 3: |
9870 | | // op: imm5 |
9871 | | return 18; |
9872 | | case 2: |
9873 | | // op: imm8 |
9874 | | return 10; |
9875 | | case 1: |
9876 | | // op: rj |
9877 | | return 5; |
9878 | | case 0: |
9879 | | // op: xd |
9880 | | return 0; |
9881 | | } |
9882 | | break; |
9883 | | } |
9884 | | case LoongArch::VSRANI_W_D: |
9885 | | case LoongArch::VSRARNI_W_D: |
9886 | | case LoongArch::VSRLNI_W_D: |
9887 | | case LoongArch::VSRLRNI_W_D: |
9888 | | case LoongArch::VSSRANI_WU_D: |
9889 | | case LoongArch::VSSRANI_W_D: |
9890 | | case LoongArch::VSSRARNI_WU_D: |
9891 | | case LoongArch::VSSRARNI_W_D: |
9892 | | case LoongArch::VSSRLNI_WU_D: |
9893 | | case LoongArch::VSSRLNI_W_D: |
9894 | | case LoongArch::VSSRLRNI_WU_D: |
9895 | | case LoongArch::VSSRLRNI_W_D: { |
9896 | | switch (OpNum) { |
9897 | | case 3: |
9898 | | // op: imm6 |
9899 | | return 10; |
9900 | | case 2: |
9901 | | // op: vj |
9902 | | return 5; |
9903 | | case 1: |
9904 | | // op: vd |
9905 | | return 0; |
9906 | | } |
9907 | | break; |
9908 | | } |
9909 | | case LoongArch::XVSRANI_W_D: |
9910 | | case LoongArch::XVSRARNI_W_D: |
9911 | | case LoongArch::XVSRLNI_W_D: |
9912 | | case LoongArch::XVSRLRNI_W_D: |
9913 | | case LoongArch::XVSSRANI_WU_D: |
9914 | | case LoongArch::XVSSRANI_W_D: |
9915 | | case LoongArch::XVSSRARNI_WU_D: |
9916 | | case LoongArch::XVSSRARNI_W_D: |
9917 | | case LoongArch::XVSSRLNI_WU_D: |
9918 | | case LoongArch::XVSSRLNI_W_D: |
9919 | | case LoongArch::XVSSRLRNI_WU_D: |
9920 | | case LoongArch::XVSSRLRNI_W_D: { |
9921 | | switch (OpNum) { |
9922 | | case 3: |
9923 | | // op: imm6 |
9924 | | return 10; |
9925 | | case 2: |
9926 | | // op: xj |
9927 | | return 5; |
9928 | | case 1: |
9929 | | // op: xd |
9930 | | return 0; |
9931 | | } |
9932 | | break; |
9933 | | } |
9934 | | case LoongArch::VSRANI_D_Q: |
9935 | | case LoongArch::VSRARNI_D_Q: |
9936 | | case LoongArch::VSRLNI_D_Q: |
9937 | | case LoongArch::VSRLRNI_D_Q: |
9938 | | case LoongArch::VSSRANI_DU_Q: |
9939 | | case LoongArch::VSSRANI_D_Q: |
9940 | | case LoongArch::VSSRARNI_DU_Q: |
9941 | | case LoongArch::VSSRARNI_D_Q: |
9942 | | case LoongArch::VSSRLNI_DU_Q: |
9943 | | case LoongArch::VSSRLNI_D_Q: |
9944 | | case LoongArch::VSSRLRNI_DU_Q: |
9945 | | case LoongArch::VSSRLRNI_D_Q: { |
9946 | | switch (OpNum) { |
9947 | | case 3: |
9948 | | // op: imm7 |
9949 | | return 10; |
9950 | | case 2: |
9951 | | // op: vj |
9952 | | return 5; |
9953 | | case 1: |
9954 | | // op: vd |
9955 | | return 0; |
9956 | | } |
9957 | | break; |
9958 | | } |
9959 | | case LoongArch::XVSRANI_D_Q: |
9960 | | case LoongArch::XVSRARNI_D_Q: |
9961 | | case LoongArch::XVSRLNI_D_Q: |
9962 | | case LoongArch::XVSRLRNI_D_Q: |
9963 | | case LoongArch::XVSSRANI_DU_Q: |
9964 | | case LoongArch::XVSSRANI_D_Q: |
9965 | | case LoongArch::XVSSRARNI_DU_Q: |
9966 | | case LoongArch::XVSSRARNI_D_Q: |
9967 | | case LoongArch::XVSSRLNI_DU_Q: |
9968 | | case LoongArch::XVSSRLNI_D_Q: |
9969 | | case LoongArch::XVSSRLRNI_DU_Q: |
9970 | | case LoongArch::XVSSRLRNI_D_Q: { |
9971 | | switch (OpNum) { |
9972 | | case 3: |
9973 | | // op: imm7 |
9974 | | return 10; |
9975 | | case 2: |
9976 | | // op: xj |
9977 | | return 5; |
9978 | | case 1: |
9979 | | // op: xd |
9980 | | return 0; |
9981 | | } |
9982 | | break; |
9983 | | } |
9984 | | case LoongArch::VBITSELI_B: |
9985 | | case LoongArch::VEXTRINS_B: |
9986 | | case LoongArch::VEXTRINS_D: |
9987 | | case LoongArch::VEXTRINS_H: |
9988 | | case LoongArch::VEXTRINS_W: |
9989 | | case LoongArch::VPERMI_W: |
9990 | | case LoongArch::VSHUF4I_D: { |
9991 | | switch (OpNum) { |
9992 | | case 3: |
9993 | | // op: imm8 |
9994 | | return 10; |
9995 | | case 2: |
9996 | | // op: vj |
9997 | | return 5; |
9998 | | case 1: |
9999 | | // op: vd |
10000 | | return 0; |
10001 | | } |
10002 | | break; |
10003 | | } |
10004 | | case LoongArch::XVBITSELI_B: |
10005 | | case LoongArch::XVEXTRINS_B: |
10006 | | case LoongArch::XVEXTRINS_D: |
10007 | | case LoongArch::XVEXTRINS_H: |
10008 | | case LoongArch::XVEXTRINS_W: |
10009 | | case LoongArch::XVPERMI_Q: |
10010 | | case LoongArch::XVPERMI_W: |
10011 | | case LoongArch::XVSHUF4I_D: { |
10012 | | switch (OpNum) { |
10013 | | case 3: |
10014 | | // op: imm8 |
10015 | | return 10; |
10016 | | case 2: |
10017 | | // op: xj |
10018 | | return 5; |
10019 | | case 1: |
10020 | | // op: xd |
10021 | | return 0; |
10022 | | } |
10023 | | break; |
10024 | | } |
10025 | | case LoongArch::BSTRINS_D: { |
10026 | | switch (OpNum) { |
10027 | | case 3: |
10028 | | // op: msbd |
10029 | | return 16; |
10030 | | case 4: |
10031 | | // op: lsbd |
10032 | | return 10; |
10033 | | case 2: |
10034 | | // op: rj |
10035 | | return 5; |
10036 | | case 1: |
10037 | | // op: rd |
10038 | | return 0; |
10039 | | } |
10040 | | break; |
10041 | | } |
10042 | | case LoongArch::BSTRINS_W: { |
10043 | | switch (OpNum) { |
10044 | | case 3: |
10045 | | // op: msbw |
10046 | | return 16; |
10047 | | case 4: |
10048 | | // op: lsbw |
10049 | | return 10; |
10050 | | case 2: |
10051 | | // op: rj |
10052 | | return 5; |
10053 | | case 1: |
10054 | | // op: rd |
10055 | | return 0; |
10056 | | } |
10057 | | break; |
10058 | | } |
10059 | | case LoongArch::VBITSEL_V: |
10060 | | case LoongArch::VFMADD_D: |
10061 | | case LoongArch::VFMADD_S: |
10062 | | case LoongArch::VFMSUB_D: |
10063 | | case LoongArch::VFMSUB_S: |
10064 | | case LoongArch::VFNMADD_D: |
10065 | | case LoongArch::VFNMADD_S: |
10066 | | case LoongArch::VFNMSUB_D: |
10067 | | case LoongArch::VFNMSUB_S: |
10068 | | case LoongArch::VSHUF_B: { |
10069 | | switch (OpNum) { |
10070 | | case 3: |
10071 | | // op: va |
10072 | | return 15; |
10073 | | case 2: |
10074 | | // op: vk |
10075 | | return 10; |
10076 | | case 1: |
10077 | | // op: vj |
10078 | | return 5; |
10079 | | case 0: |
10080 | | // op: vd |
10081 | | return 0; |
10082 | | } |
10083 | | break; |
10084 | | } |
10085 | | case LoongArch::VFRSTP_B: |
10086 | | case LoongArch::VFRSTP_H: |
10087 | | case LoongArch::VMADDWEV_D_W: |
10088 | | case LoongArch::VMADDWEV_D_WU: |
10089 | | case LoongArch::VMADDWEV_D_WU_W: |
10090 | | case LoongArch::VMADDWEV_H_B: |
10091 | | case LoongArch::VMADDWEV_H_BU: |
10092 | | case LoongArch::VMADDWEV_H_BU_B: |
10093 | | case LoongArch::VMADDWEV_Q_D: |
10094 | | case LoongArch::VMADDWEV_Q_DU: |
10095 | | case LoongArch::VMADDWEV_Q_DU_D: |
10096 | | case LoongArch::VMADDWEV_W_H: |
10097 | | case LoongArch::VMADDWEV_W_HU: |
10098 | | case LoongArch::VMADDWEV_W_HU_H: |
10099 | | case LoongArch::VMADDWOD_D_W: |
10100 | | case LoongArch::VMADDWOD_D_WU: |
10101 | | case LoongArch::VMADDWOD_D_WU_W: |
10102 | | case LoongArch::VMADDWOD_H_B: |
10103 | | case LoongArch::VMADDWOD_H_BU: |
10104 | | case LoongArch::VMADDWOD_H_BU_B: |
10105 | | case LoongArch::VMADDWOD_Q_D: |
10106 | | case LoongArch::VMADDWOD_Q_DU: |
10107 | | case LoongArch::VMADDWOD_Q_DU_D: |
10108 | | case LoongArch::VMADDWOD_W_H: |
10109 | | case LoongArch::VMADDWOD_W_HU: |
10110 | | case LoongArch::VMADDWOD_W_HU_H: |
10111 | | case LoongArch::VMADD_B: |
10112 | | case LoongArch::VMADD_D: |
10113 | | case LoongArch::VMADD_H: |
10114 | | case LoongArch::VMADD_W: |
10115 | | case LoongArch::VMSUB_B: |
10116 | | case LoongArch::VMSUB_D: |
10117 | | case LoongArch::VMSUB_H: |
10118 | | case LoongArch::VMSUB_W: |
10119 | | case LoongArch::VSHUF_D: |
10120 | | case LoongArch::VSHUF_H: |
10121 | | case LoongArch::VSHUF_W: { |
10122 | | switch (OpNum) { |
10123 | | case 3: |
10124 | | // op: vk |
10125 | | return 10; |
10126 | | case 2: |
10127 | | // op: vj |
10128 | | return 5; |
10129 | | case 1: |
10130 | | // op: vd |
10131 | | return 0; |
10132 | | } |
10133 | | break; |
10134 | | } |
10135 | | case LoongArch::XVBITSEL_V: |
10136 | | case LoongArch::XVFMADD_D: |
10137 | | case LoongArch::XVFMADD_S: |
10138 | | case LoongArch::XVFMSUB_D: |
10139 | | case LoongArch::XVFMSUB_S: |
10140 | | case LoongArch::XVFNMADD_D: |
10141 | | case LoongArch::XVFNMADD_S: |
10142 | | case LoongArch::XVFNMSUB_D: |
10143 | | case LoongArch::XVFNMSUB_S: |
10144 | | case LoongArch::XVSHUF_B: { |
10145 | | switch (OpNum) { |
10146 | | case 3: |
10147 | | // op: xa |
10148 | | return 15; |
10149 | | case 2: |
10150 | | // op: xk |
10151 | | return 10; |
10152 | | case 1: |
10153 | | // op: xj |
10154 | | return 5; |
10155 | | case 0: |
10156 | | // op: xd |
10157 | | return 0; |
10158 | | } |
10159 | | break; |
10160 | | } |
10161 | | case LoongArch::XVFRSTP_B: |
10162 | | case LoongArch::XVFRSTP_H: |
10163 | | case LoongArch::XVMADDWEV_D_W: |
10164 | | case LoongArch::XVMADDWEV_D_WU: |
10165 | | case LoongArch::XVMADDWEV_D_WU_W: |
10166 | | case LoongArch::XVMADDWEV_H_B: |
10167 | | case LoongArch::XVMADDWEV_H_BU: |
10168 | | case LoongArch::XVMADDWEV_H_BU_B: |
10169 | | case LoongArch::XVMADDWEV_Q_D: |
10170 | | case LoongArch::XVMADDWEV_Q_DU: |
10171 | | case LoongArch::XVMADDWEV_Q_DU_D: |
10172 | | case LoongArch::XVMADDWEV_W_H: |
10173 | | case LoongArch::XVMADDWEV_W_HU: |
10174 | | case LoongArch::XVMADDWEV_W_HU_H: |
10175 | | case LoongArch::XVMADDWOD_D_W: |
10176 | | case LoongArch::XVMADDWOD_D_WU: |
10177 | | case LoongArch::XVMADDWOD_D_WU_W: |
10178 | | case LoongArch::XVMADDWOD_H_B: |
10179 | | case LoongArch::XVMADDWOD_H_BU: |
10180 | | case LoongArch::XVMADDWOD_H_BU_B: |
10181 | | case LoongArch::XVMADDWOD_Q_D: |
10182 | | case LoongArch::XVMADDWOD_Q_DU: |
10183 | | case LoongArch::XVMADDWOD_Q_DU_D: |
10184 | | case LoongArch::XVMADDWOD_W_H: |
10185 | | case LoongArch::XVMADDWOD_W_HU: |
10186 | | case LoongArch::XVMADDWOD_W_HU_H: |
10187 | | case LoongArch::XVMADD_B: |
10188 | | case LoongArch::XVMADD_D: |
10189 | | case LoongArch::XVMADD_H: |
10190 | | case LoongArch::XVMADD_W: |
10191 | | case LoongArch::XVMSUB_B: |
10192 | | case LoongArch::XVMSUB_D: |
10193 | | case LoongArch::XVMSUB_H: |
10194 | | case LoongArch::XVMSUB_W: |
10195 | | case LoongArch::XVSHUF_D: |
10196 | | case LoongArch::XVSHUF_H: |
10197 | | case LoongArch::XVSHUF_W: { |
10198 | | switch (OpNum) { |
10199 | | case 3: |
10200 | | // op: xk |
10201 | | return 10; |
10202 | | case 2: |
10203 | | // op: xj |
10204 | | return 5; |
10205 | | case 1: |
10206 | | // op: xd |
10207 | | return 0; |
10208 | | } |
10209 | | break; |
10210 | | } |
10211 | | } |
10212 | | std::string msg; |
10213 | | raw_string_ostream Msg(msg); |
10214 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
10215 | | report_fatal_error(Msg.str().c_str()); |
10216 | | } |
10217 | | |
10218 | | #endif // GET_OPERAND_BIT_OFFSET |
10219 | | |