/src/build/lib/Target/LoongArch/LoongArchGenMCPseudoLowering.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | bool LoongArchAsmPrinter:: |
10 | | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | 0 | const MachineInstr *MI) { |
12 | 0 | switch (MI->getOpcode()) { |
13 | 0 | default: return false; |
14 | 0 | case LoongArch::PseudoAtomicStoreD: { |
15 | 0 | MCInst TmpInst; |
16 | 0 | MCOperand MCOp; |
17 | 0 | TmpInst.setOpcode(LoongArch::AMSWAP__DB_D); |
18 | | // Operand: rd |
19 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
20 | | // Operand: rk |
21 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
22 | 0 | TmpInst.addOperand(MCOp); |
23 | | // Operand: rj |
24 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
25 | 0 | TmpInst.addOperand(MCOp); |
26 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
27 | 0 | break; |
28 | 0 | } |
29 | 0 | case LoongArch::PseudoAtomicStoreW: { |
30 | 0 | MCInst TmpInst; |
31 | 0 | MCOperand MCOp; |
32 | 0 | TmpInst.setOpcode(LoongArch::AMSWAP__DB_W); |
33 | | // Operand: rd |
34 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
35 | | // Operand: rk |
36 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
37 | 0 | TmpInst.addOperand(MCOp); |
38 | | // Operand: rj |
39 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
40 | 0 | TmpInst.addOperand(MCOp); |
41 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
42 | 0 | break; |
43 | 0 | } |
44 | 0 | case LoongArch::PseudoBR: { |
45 | 0 | MCInst TmpInst; |
46 | 0 | MCOperand MCOp; |
47 | 0 | TmpInst.setOpcode(LoongArch::B); |
48 | | // Operand: imm26 |
49 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
50 | 0 | TmpInst.addOperand(MCOp); |
51 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
52 | 0 | break; |
53 | 0 | } |
54 | 0 | case LoongArch::PseudoBRIND: { |
55 | 0 | MCInst TmpInst; |
56 | 0 | MCOperand MCOp; |
57 | 0 | TmpInst.setOpcode(LoongArch::JIRL); |
58 | | // Operand: rd |
59 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
60 | | // Operand: rj |
61 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
62 | 0 | TmpInst.addOperand(MCOp); |
63 | | // Operand: imm16 |
64 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
65 | 0 | TmpInst.addOperand(MCOp); |
66 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
67 | 0 | break; |
68 | 0 | } |
69 | 0 | case LoongArch::PseudoB_TAIL: { |
70 | 0 | MCInst TmpInst; |
71 | 0 | MCOperand MCOp; |
72 | 0 | TmpInst.setOpcode(LoongArch::B); |
73 | | // Operand: imm26 |
74 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
75 | 0 | TmpInst.addOperand(MCOp); |
76 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
77 | 0 | break; |
78 | 0 | } |
79 | 0 | case LoongArch::PseudoCALLIndirect: { |
80 | 0 | MCInst TmpInst; |
81 | 0 | MCOperand MCOp; |
82 | 0 | TmpInst.setOpcode(LoongArch::JIRL); |
83 | | // Operand: rd |
84 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); |
85 | | // Operand: rj |
86 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
87 | 0 | TmpInst.addOperand(MCOp); |
88 | | // Operand: imm16 |
89 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
90 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
91 | 0 | break; |
92 | 0 | } |
93 | 0 | case LoongArch::PseudoJIRL_CALL: { |
94 | 0 | MCInst TmpInst; |
95 | 0 | MCOperand MCOp; |
96 | 0 | TmpInst.setOpcode(LoongArch::JIRL); |
97 | | // Operand: rd |
98 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); |
99 | | // Operand: rj |
100 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
101 | 0 | TmpInst.addOperand(MCOp); |
102 | | // Operand: imm16 |
103 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
104 | 0 | TmpInst.addOperand(MCOp); |
105 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
106 | 0 | break; |
107 | 0 | } |
108 | 0 | case LoongArch::PseudoJIRL_TAIL: { |
109 | 0 | MCInst TmpInst; |
110 | 0 | MCOperand MCOp; |
111 | 0 | TmpInst.setOpcode(LoongArch::JIRL); |
112 | | // Operand: rd |
113 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
114 | | // Operand: rj |
115 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
116 | 0 | TmpInst.addOperand(MCOp); |
117 | | // Operand: imm16 |
118 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
119 | 0 | TmpInst.addOperand(MCOp); |
120 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
121 | 0 | break; |
122 | 0 | } |
123 | 0 | case LoongArch::PseudoRET: { |
124 | 0 | MCInst TmpInst; |
125 | 0 | MCOperand MCOp; |
126 | 0 | TmpInst.setOpcode(LoongArch::JIRL); |
127 | | // Operand: rd |
128 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
129 | | // Operand: rj |
130 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); |
131 | | // Operand: imm16 |
132 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
133 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
134 | 0 | break; |
135 | 0 | } |
136 | 0 | case LoongArch::PseudoTAILIndirect: { |
137 | 0 | MCInst TmpInst; |
138 | 0 | MCOperand MCOp; |
139 | 0 | TmpInst.setOpcode(LoongArch::JIRL); |
140 | | // Operand: rd |
141 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
142 | | // Operand: rj |
143 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
144 | 0 | TmpInst.addOperand(MCOp); |
145 | | // Operand: imm16 |
146 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
147 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
148 | 0 | break; |
149 | 0 | } |
150 | 0 | case LoongArch::PseudoUNIMP: { |
151 | 0 | MCInst TmpInst; |
152 | 0 | MCOperand MCOp; |
153 | 0 | TmpInst.setOpcode(LoongArch::AMSWAP_W); |
154 | | // Operand: rd |
155 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
156 | | // Operand: rk |
157 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R1)); |
158 | | // Operand: rj |
159 | 0 | TmpInst.addOperand(MCOperand::createReg(LoongArch::R0)); |
160 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
161 | 0 | break; |
162 | 0 | } |
163 | 0 | } |
164 | 0 | return true; |
165 | 0 | } |
166 | | |