/src/build/lib/Target/LoongArch/LoongArchGenRegisterInfo.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass LoongArchMCRegisterClasses[];

namespace LoongArch {
enum {
  NoRegister,
  F0 = 1,
  F1 = 2,
  F2 = 3,
  F3 = 4,
  F4 = 5,
  F5 = 6,
  F6 = 7,
  F7 = 8,
  F8 = 9,
  F9 = 10,
  F10 = 11,
  F11 = 12,
  F12 = 13,
  F13 = 14,
  F14 = 15,
  F15 = 16,
  F16 = 17,
  F17 = 18,
  F18 = 19,
  F19 = 20,
  F20 = 21,
  F21 = 22,
  F22 = 23,
  F23 = 24,
  F24 = 25,
  F25 = 26,
  F26 = 27,
  F27 = 28,
  F28 = 29,
  F29 = 30,
  F30 = 31,
  F31 = 32,
  FCC0 = 33,
  FCC1 = 34,
  FCC2 = 35,
  FCC3 = 36,
  FCC4 = 37,
  FCC5 = 38,
  FCC6 = 39,
  FCC7 = 40,
  FCSR0 = 41,
  FCSR1 = 42,
  FCSR2 = 43,
  FCSR3 = 44,
  R0 = 45,
  R1 = 46,
  R2 = 47,
  R3 = 48,
  R4 = 49,
  R5 = 50,
  R6 = 51,
  R7 = 52,
  R8 = 53,
  R9 = 54,
  R10 = 55,
  R11 = 56,
  R12 = 57,
  R13 = 58,
  R14 = 59,
  R15 = 60,
  R16 = 61,
  R17 = 62,
  R18 = 63,
  R19 = 64,
  R20 = 65,
  R21 = 66,
  R22 = 67,
  R23 = 68,
  R24 = 69,
  R25 = 70,
  R26 = 71,
  R27 = 72,
  R28 = 73,
  R29 = 74,
  R30 = 75,
  R31 = 76,
  SCR0 = 77,
  SCR1 = 78,
  SCR2 = 79,
  SCR3 = 80,
  VR0 = 81,
  VR1 = 82,
  VR2 = 83,
  VR3 = 84,
  VR4 = 85,
  VR5 = 86,
  VR6 = 87,
  VR7 = 88,
  VR8 = 89,
  VR9 = 90,
  VR10 = 91,
  VR11 = 92,
  VR12 = 93,
  VR13 = 94,
  VR14 = 95,
  VR15 = 96,
  VR16 = 97,
  VR17 = 98,
  VR18 = 99,
  VR19 = 100,
  VR20 = 101,
  VR21 = 102,
  VR22 = 103,
  VR23 = 104,
  VR24 = 105,
  VR25 = 106,
  VR26 = 107,
  VR27 = 108,
  VR28 = 109,
  VR29 = 110,
  VR30 = 111,
  VR31 = 112,
  XR0 = 113,
  XR1 = 114,
  XR2 = 115,
  XR3 = 116,
  XR4 = 117,
  XR5 = 118,
  XR6 = 119,
  XR7 = 120,
  XR8 = 121,
  XR9 = 122,
  XR10 = 123,
  XR11 = 124,
  XR12 = 125,
  XR13 = 126,
  XR14 = 127,
  XR15 = 128,
  XR16 = 129,
  XR17 = 130,
  XR18 = 131,
  XR19 = 132,
  XR20 = 133,
  XR21 = 134,
  XR22 = 135,
  XR23 = 136,
  XR24 = 137,
  XR25 = 138,
  XR26 = 139,
  XR27 = 140,
  XR28 = 141,
  XR29 = 142,
  XR30 = 143,
  XR31 = 144,
  F0_64 = 145,
  F1_64 = 146,
  F2_64 = 147,
  F3_64 = 148,
  F4_64 = 149,
  F5_64 = 150,
  F6_64 = 151,
  F7_64 = 152,
  F8_64 = 153,
  F9_64 = 154,
  F10_64 = 155,
  F11_64 = 156,
  F12_64 = 157,
  F13_64 = 158,
  F14_64 = 159,
  F15_64 = 160,
  F16_64 = 161,
  F17_64 = 162,
  F18_64 = 163,
  F19_64 = 164,
  F20_64 = 165,
  F21_64 = 166,
  F22_64 = 167,
  F23_64 = 168,
  F24_64 = 169,
  F25_64 = 170,
  F26_64 = 171,
  F27_64 = 172,
  F28_64 = 173,
  F29_64 = 174,
  F30_64 = 175,
  F31_64 = 176,
  NUM_TARGET_REGS // 177
};
} // end namespace LoongArch

// Register classes

namespace LoongArch {
enum {
  FPR32RegClassID = 0,
  GPRRegClassID = 1,
  GPRTRegClassID = 2,
  CFRRegClassID = 3,
  FCSRRegClassID = 4,
  SCRRegClassID = 5,
  FPR64RegClassID = 6,
  LSX128RegClassID = 7,
  LASX256RegClassID = 8,

};
} // end namespace LoongArch


// Register alternate name indices

namespace LoongArch {
enum {
  NoRegAltName, // 0
  RegAliasName, // 1
  NUM_TARGET_REG_ALT_NAMES = 2
};
} // end namespace LoongArch


// Subregister indices

namespace LoongArch {
enum : uint16_t {
  NoSubRegister,
  sub_32, // 1
  sub_64, // 2
  sub_128,  // 3
  NUM_TARGET_SUBREGS
};
} // end namespace LoongArch

// Register pressure sets enum.
namespace LoongArch {
enum RegisterPressureSets {
  CFR = 0,
  GPRT = 1,
  FPR32 = 2,
  GPR = 3,
};
} // end namespace LoongArch

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t LoongArchRegDiffLists[] = {
  /* 0 */ -32, 64, -144, 0,
  /* 4 */ 144, -64, 32, 0,
};

extern const LaneBitmask LoongArchLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t LoongArchSubRegIdxLists[] = {
  /* 0 */ 3, 2, 1, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 32 },  // sub_32
  { 0, 64 },  // sub_64
  { 0, 128 }, // sub_128
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char LoongArchRegStrings[] = {
  /* 0 */ "F10\0"
  /* 4 */ "VR10\0"
  /* 9 */ "XR10\0"
  /* 14 */ "F20\0"
  /* 18 */ "VR20\0"
  /* 23 */ "XR20\0"
  /* 28 */ "F30\0"
  /* 32 */ "VR30\0"
  /* 37 */ "XR30\0"
  /* 42 */ "FCC0\0"
  /* 47 */ "F0\0"
  /* 50 */ "SCR0\0"
  /* 55 */ "FCSR0\0"
  /* 61 */ "VR0\0"
  /* 65 */ "XR0\0"
  /* 69 */ "F11\0"
  /* 73 */ "VR11\0"
  /* 78 */ "XR11\0"
  /* 83 */ "F21\0"
  /* 87 */ "VR21\0"
  /* 92 */ "XR21\0"
  /* 97 */ "F31\0"
  /* 101 */ "VR31\0"
  /* 106 */ "XR31\0"
  /* 111 */ "FCC1\0"
  /* 116 */ "F1\0"
  /* 119 */ "SCR1\0"
  /* 124 */ "FCSR1\0"
  /* 130 */ "VR1\0"
  /* 134 */ "XR1\0"
  /* 138 */ "F12\0"
  /* 142 */ "VR12\0"
  /* 147 */ "XR12\0"
  /* 152 */ "F22\0"
  /* 156 */ "VR22\0"
  /* 161 */ "XR22\0"
  /* 166 */ "FCC2\0"
  /* 171 */ "F2\0"
  /* 174 */ "SCR2\0"
  /* 179 */ "FCSR2\0"
  /* 185 */ "VR2\0"
  /* 189 */ "XR2\0"
  /* 193 */ "F13\0"
  /* 197 */ "VR13\0"
  /* 202 */ "XR13\0"
  /* 207 */ "F23\0"
  /* 211 */ "VR23\0"
  /* 216 */ "XR23\0"
  /* 221 */ "FCC3\0"
  /* 226 */ "F3\0"
  /* 229 */ "SCR3\0"
  /* 234 */ "FCSR3\0"
  /* 240 */ "VR3\0"
  /* 244 */ "XR3\0"
  /* 248 */ "F14\0"
  /* 252 */ "VR14\0"
  /* 257 */ "XR14\0"
  /* 262 */ "F24\0"
  /* 266 */ "VR24\0"
  /* 271 */ "XR24\0"
  /* 276 */ "F10_64\0"
  /* 283 */ "F20_64\0"
  /* 290 */ "F30_64\0"
  /* 297 */ "F0_64\0"
  /* 303 */ "F11_64\0"
  /* 310 */ "F21_64\0"
  /* 317 */ "F31_64\0"
  /* 324 */ "F1_64\0"
  /* 330 */ "F12_64\0"
  /* 337 */ "F22_64\0"
  /* 344 */ "F2_64\0"
  /* 350 */ "F13_64\0"
  /* 357 */ "F23_64\0"
  /* 364 */ "F3_64\0"
  /* 370 */ "F14_64\0"
  /* 377 */ "F24_64\0"
  /* 384 */ "F4_64\0"
  /* 390 */ "F15_64\0"
  /* 397 */ "F25_64\0"
  /* 404 */ "F5_64\0"
  /* 410 */ "F16_64\0"
  /* 417 */ "F26_64\0"
  /* 424 */ "F6_64\0"
  /* 430 */ "F17_64\0"
  /* 437 */ "F27_64\0"
  /* 444 */ "F7_64\0"
  /* 450 */ "F18_64\0"
  /* 457 */ "F28_64\0"
  /* 464 */ "F8_64\0"
  /* 470 */ "F19_64\0"
  /* 477 */ "F29_64\0"
  /* 484 */ "F9_64\0"
  /* 490 */ "FCC4\0"
  /* 495 */ "F4\0"
  /* 498 */ "VR4\0"
  /* 502 */ "XR4\0"
  /* 506 */ "F15\0"
  /* 510 */ "VR15\0"
  /* 515 */ "XR15\0"
  /* 520 */ "F25\0"
  /* 524 */ "VR25\0"
  /* 529 */ "XR25\0"
  /* 534 */ "FCC5\0"
  /* 539 */ "F5\0"
  /* 542 */ "VR5\0"
  /* 546 */ "XR5\0"
  /* 550 */ "F16\0"
  /* 554 */ "VR16\0"
  /* 559 */ "XR16\0"
  /* 564 */ "F26\0"
  /* 568 */ "VR26\0"
  /* 573 */ "XR26\0"
  /* 578 */ "FCC6\0"
  /* 583 */ "F6\0"
  /* 586 */ "VR6\0"
  /* 590 */ "XR6\0"
  /* 594 */ "F17\0"
  /* 598 */ "VR17\0"
  /* 603 */ "XR17\0"
  /* 608 */ "F27\0"
  /* 612 */ "VR27\0"
  /* 617 */ "XR27\0"
  /* 622 */ "FCC7\0"
  /* 627 */ "F7\0"
  /* 630 */ "VR7\0"
  /* 634 */ "XR7\0"
  /* 638 */ "F18\0"
  /* 642 */ "VR18\0"
  /* 647 */ "XR18\0"
  /* 652 */ "F28\0"
  /* 656 */ "VR28\0"
  /* 661 */ "XR28\0"
  /* 666 */ "F8\0"
  /* 669 */ "VR8\0"
  /* 673 */ "XR8\0"
  /* 677 */ "F19\0"
  /* 681 */ "VR19\0"
  /* 686 */ "XR19\0"
  /* 691 */ "F29\0"
  /* 695 */ "VR29\0"
  /* 700 */ "XR29\0"
  /* 705 */ "F9\0"
  /* 708 */ "VR9\0"
  /* 712 */ "XR9\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc LoongArchRegDesc[] = { // Descriptors
  { 3, 0, 0, 0, 0, 0 },
  { 47, 3, 4, 3, 12288, 2 },
  { 116, 3, 4, 3, 12289, 2 },
  { 171, 3, 4, 3, 12290, 2 },
  { 226, 3, 4, 3, 12291, 2 },
  { 495, 3, 4, 3, 12292, 2 },
  { 539, 3, 4, 3, 12293, 2 },
  { 583, 3, 4, 3, 12294, 2 },
  { 627, 3, 4, 3, 12295, 2 },
  { 666, 3, 4, 3, 12296, 2 },
  { 705, 3, 4, 3, 12297, 2 },
  { 0, 3, 4, 3, 12298, 2 },
  { 69, 3, 4, 3, 12299, 2 },
  { 138, 3, 4, 3, 12300, 2 },
  { 193, 3, 4, 3, 12301, 2 },
  { 248, 3, 4, 3, 12302, 2 },
  { 506, 3, 4, 3, 12303, 2 },
  { 550, 3, 4, 3, 12304, 2 },
  { 594, 3, 4, 3, 12305, 2 },
  { 638, 3, 4, 3, 12306, 2 },
  { 677, 3, 4, 3, 12307, 2 },
  { 14, 3, 4, 3, 12308, 2 },
  { 83, 3, 4, 3, 12309, 2 },
  { 152, 3, 4, 3, 12310, 2 },
  { 207, 3, 4, 3, 12311, 2 },
  { 262, 3, 4, 3, 12312, 2 },
  { 520, 3, 4, 3, 12313, 2 },
  { 564, 3, 4, 3, 12314, 2 },
  { 608, 3, 4, 3, 12315, 2 },
  { 652, 3, 4, 3, 12316, 2 },
  { 691, 3, 4, 3, 12317, 2 },
  { 28, 3, 4, 3, 12318, 2 },
  { 97, 3, 4, 3, 12319, 2 },
  { 42, 3, 3, 3, 12320, 2 },
  { 111, 3, 3, 3, 12321, 2 },
  { 166, 3, 3, 3, 12322, 2 },
  { 221, 3, 3, 3, 12323, 2 },
  { 490, 3, 3, 3, 12324, 2 },
  { 534, 3, 3, 3, 12325, 2 },
  { 578, 3, 3, 3, 12326, 2 },
  { 622, 3, 3, 3, 12327, 2 },
  { 55, 3, 3, 3, 12328, 2 },
  { 124, 3, 3, 3, 12329, 2 },
  { 179, 3, 3, 3, 12330, 2 },
  { 234, 3, 3, 3, 12331, 2 },
  { 52, 3, 3, 3, 12332, 2 },
  { 121, 3, 3, 3, 12333, 2 },
  { 176, 3, 3, 3, 12334, 2 },
  { 231, 3, 3, 3, 12335, 2 },
  { 499, 3, 3, 3, 12336, 2 },
  { 543, 3, 3, 3, 12337, 2 },
  { 587, 3, 3, 3, 12338, 2 },
  { 631, 3, 3, 3, 12339, 2 },
  { 670, 3, 3, 3, 12340, 2 },
  { 709, 3, 3, 3, 12341, 2 },
  { 5, 3, 3, 3, 12342, 2 },
  { 74, 3, 3, 3, 12343, 2 },
  { 143, 3, 3, 3, 12344, 2 },
  { 198, 3, 3, 3, 12345, 2 },
  { 253, 3, 3, 3, 12346, 2 },
  { 511, 3, 3, 3, 12347, 2 },
  { 555, 3, 3, 3, 12348, 2 },
  { 599, 3, 3, 3, 12349, 2 },
  { 643, 3, 3, 3, 12350, 2 },
  { 682, 3, 3, 3, 12351, 2 },
  { 19, 3, 3, 3, 12352, 2 },
  { 88, 3, 3, 3, 12353, 2 },
  { 157, 3, 3, 3, 12354, 2 },
  { 212, 3, 3, 3, 12355, 2 },
  { 267, 3, 3, 3, 12356, 2 },
  { 525, 3, 3, 3, 12357, 2 },
  { 569, 3, 3, 3, 12358, 2 },
  { 613, 3, 3, 3, 12359, 2 },
  { 657, 3, 3, 3, 12360, 2 },
  { 696, 3, 3, 3, 12361, 2 },
  { 33, 3, 3, 3, 12362, 2 },
  { 102, 3, 3, 3, 12363, 2 },
  { 50, 3, 3, 3, 12364, 2 },
  { 119, 3, 3, 3, 12365, 2 },
  { 174, 3, 3, 3, 12366, 2 },
  { 229, 3, 3, 3, 12367, 2 },
  { 61, 1, 6, 1, 12288, 0 },
  { 130, 1, 6, 1, 12289, 0 },
  { 185, 1, 6, 1, 12290, 0 },
  { 240, 1, 6, 1, 12291, 0 },
  { 498, 1, 6, 1, 12292, 0 },
  { 542, 1, 6, 1, 12293, 0 },
  { 586, 1, 6, 1, 12294, 0 },
  { 630, 1, 6, 1, 12295, 0 },
  { 669, 1, 6, 1, 12296, 0 },
  { 708, 1, 6, 1, 12297, 0 },
  { 4, 1, 6, 1, 12298, 0 },
  { 73, 1, 6, 1, 12299, 0 },
  { 142, 1, 6, 1, 12300, 0 },
  { 197, 1, 6, 1, 12301, 0 },
  { 252, 1, 6, 1, 12302, 0 },
  { 510, 1, 6, 1, 12303, 0 },
  { 554, 1, 6, 1, 12304, 0 },
  { 598, 1, 6, 1, 12305, 0 },
  { 642, 1, 6, 1, 12306, 0 },
  { 681, 1, 6, 1, 12307, 0 },
  { 18, 1, 6, 1, 12308, 0 },
  { 87, 1, 6, 1, 12309, 0 },
  { 156, 1, 6, 1, 12310, 0 },
  { 211, 1, 6, 1, 12311, 0 },
  { 266, 1, 6, 1, 12312, 0 },
  { 524, 1, 6, 1, 12313, 0 },
  { 568, 1, 6, 1, 12314, 0 },
  { 612, 1, 6, 1, 12315, 0 },
  { 656, 1, 6, 1, 12316, 0 },
  { 695, 1, 6, 1, 12317, 0 },
  { 32, 1, 6, 1, 12318, 0 },
  { 101, 1, 6, 1, 12319, 0 },
  { 65, 0, 3, 0, 12288, 0 },
  { 134, 0, 3, 0, 12289, 0 },
  { 189, 0, 3, 0, 12290, 0 },
  { 244, 0, 3, 0, 12291, 0 },
  { 502, 0, 3, 0, 12292, 0 },
  { 546, 0, 3, 0, 12293, 0 },
  { 590, 0, 3, 0, 12294, 0 },
  { 634, 0, 3, 0, 12295, 0 },
  { 673, 0, 3, 0, 12296, 0 },
  { 712, 0, 3, 0, 12297, 0 },
  { 9, 0, 3, 0, 12298, 0 },
  { 78, 0, 3, 0, 12299, 0 },
  { 147, 0, 3, 0, 12300, 0 },
  { 202, 0, 3, 0, 12301, 0 },
  { 257, 0, 3, 0, 12302, 0 },
  { 515, 0, 3, 0, 12303, 0 },
  { 559, 0, 3, 0, 12304, 0 },
  { 603, 0, 3, 0, 12305, 0 },
  { 647, 0, 3, 0, 12306, 0 },
  { 686, 0, 3, 0, 12307, 0 },
  { 23, 0, 3, 0, 12308, 0 },
  { 92, 0, 3, 0, 12309, 0 },
  { 161, 0, 3, 0, 12310, 0 },
  { 216, 0, 3, 0, 12311, 0 },
  { 271, 0, 3, 0, 12312, 0 },
  { 529, 0, 3, 0, 12313, 0 },
  { 573, 0, 3, 0, 12314, 0 },
  { 617, 0, 3, 0, 12315, 0 },
  { 661, 0, 3, 0, 12316, 0 },
  { 700, 0, 3, 0, 12317, 0 },
  { 37, 0, 3, 0, 12318, 0 },
  { 106, 0, 3, 0, 12319, 0 },
  { 297, 2, 5, 2, 12288, 0 },
  { 324, 2, 5, 2, 12289, 0 },
  { 344, 2, 5, 2, 12290, 0 },
  { 364, 2, 5, 2, 12291, 0 },
  { 384, 2, 5, 2, 12292, 0 },
  { 404, 2, 5, 2, 12293, 0 },
  { 424, 2, 5, 2, 12294, 0 },
  { 444, 2, 5, 2, 12295, 0 },
  { 464, 2, 5, 2, 12296, 0 },
  { 484, 2, 5, 2, 12297, 0 },
  { 276, 2, 5, 2, 12298, 0 },
  { 303, 2, 5, 2, 12299, 0 },
  { 330, 2, 5, 2, 12300, 0 },
  { 350, 2, 5, 2, 12301, 0 },
  { 370, 2, 5, 2, 12302, 0 },
  { 390, 2, 5, 2, 12303, 0 },
  { 410, 2, 5, 2, 12304, 0 },
  { 430, 2, 5, 2, 12305, 0 },
  { 450, 2, 5, 2, 12306, 0 },
  { 470, 2, 5, 2, 12307, 0 },
  { 283, 2, 5, 2, 12308, 0 },
  { 310, 2, 5, 2, 12309, 0 },
  { 337, 2, 5, 2, 12310, 0 },
  { 357, 2, 5, 2, 12311, 0 },
  { 377, 2, 5, 2, 12312, 0 },
  { 397, 2, 5, 2, 12313, 0 },
  { 417, 2, 5, 2, 12314, 0 },
  { 437, 2, 5, 2, 12315, 0 },
  { 457, 2, 5, 2, 12316, 0 },
  { 477, 2, 5, 2, 12317, 0 },
  { 290, 2, 5, 2, 12318, 0 },
  { 317, 2, 5, 2, 12319, 0 },
};

extern const MCPhysReg LoongArchRegUnitRoots[][2] = {
  { LoongArch::F0 },
  { LoongArch::F1 },
  { LoongArch::F2 },
  { LoongArch::F3 },
  { LoongArch::F4 },
  { LoongArch::F5 },
  { LoongArch::F6 },
  { LoongArch::F7 },
  { LoongArch::F8 },
  { LoongArch::F9 },
  { LoongArch::F10 },
  { LoongArch::F11 },
  { LoongArch::F12 },
  { LoongArch::F13 },
  { LoongArch::F14 },
  { LoongArch::F15 },
  { LoongArch::F16 },
  { LoongArch::F17 },
  { LoongArch::F18 },
  { LoongArch::F19 },
  { LoongArch::F20 },
  { LoongArch::F21 },
  { LoongArch::F22 },
  { LoongArch::F23 },
  { LoongArch::F24 },
  { LoongArch::F25 },
  { LoongArch::F26 },
  { LoongArch::F27 },
  { LoongArch::F28 },
  { LoongArch::F29 },
  { LoongArch::F30 },
  { LoongArch::F31 },
  { LoongArch::FCC0 },
  { LoongArch::FCC1 },
  { LoongArch::FCC2 },
  { LoongArch::FCC3 },
  { LoongArch::FCC4 },
  { LoongArch::FCC5 },
  { LoongArch::FCC6 },
  { LoongArch::FCC7 },
  { LoongArch::FCSR0 },
  { LoongArch::FCSR1 },
  { LoongArch::FCSR2 },
  { LoongArch::FCSR3 },
  { LoongArch::R0 },
  { LoongArch::R1 },
  { LoongArch::R2 },
  { LoongArch::R3 },
  { LoongArch::R4 },
  { LoongArch::R5 },
  { LoongArch::R6 },
  { LoongArch::R7 },
  { LoongArch::R8 },
  { LoongArch::R9 },
  { LoongArch::R10 },
  { LoongArch::R11 },
  { LoongArch::R12 },
  { LoongArch::R13 },
  { LoongArch::R14 },
  { LoongArch::R15 },
  { LoongArch::R16 },
  { LoongArch::R17 },
  { LoongArch::R18 },
  { LoongArch::R19 },
  { LoongArch::R20 },
  { LoongArch::R21 },
  { LoongArch::R22 },
  { LoongArch::R23 },
  { LoongArch::R24 },
  { LoongArch::R25 },
  { LoongArch::R26 },
  { LoongArch::R27 },
  { LoongArch::R28 },
  { LoongArch::R29 },
  { LoongArch::R30 },
  { LoongArch::R31 },
  { LoongArch::SCR0 },
  { LoongArch::SCR1 },
  { LoongArch::SCR2 },
  { LoongArch::SCR3 },
};

namespace {     // Register classes...
  // FPR32 Register Class...
  const MCPhysReg FPR32[] = {
    LoongArch::F0, LoongArch::F1, LoongArch::F2, LoongArch::F3, LoongArch::F4, LoongArch::F5, LoongArch::F6, LoongArch::F7, LoongArch::F8, LoongArch::F9, LoongArch::F10, LoongArch::F11, LoongArch::F12, LoongArch::F13, LoongArch::F14, LoongArch::F15, LoongArch::F16, LoongArch::F17, LoongArch::F18, LoongArch::F19, LoongArch::F20, LoongArch::F21, LoongArch::F22, LoongArch::F23, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 
  };

  // FPR32 Bit set.
  const uint8_t FPR32Bits[] = {
    0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // GPR Register Class...
  const MCPhysReg GPR[] = {
    LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::R0, LoongArch::R1, LoongArch::R2, LoongArch::R3, LoongArch::R21, 
  };

  // GPR Bit set.
  const uint8_t GPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
  };

  // GPRT Register Class...
  const MCPhysReg GPRT[] = {
    LoongArch::R4, LoongArch::R5, LoongArch::R6, LoongArch::R7, LoongArch::R8, LoongArch::R9, LoongArch::R10, LoongArch::R11, LoongArch::R12, LoongArch::R13, LoongArch::R14, LoongArch::R15, LoongArch::R16, LoongArch::R17, LoongArch::R18, LoongArch::R19, LoongArch::R20, 
  };

  // GPRT Bit set.
  const uint8_t GPRTBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x03, 
  };

  // CFR Register Class...
  const MCPhysReg CFR[] = {
    LoongArch::FCC0, LoongArch::FCC1, LoongArch::FCC2, LoongArch::FCC3, LoongArch::FCC4, LoongArch::FCC5, LoongArch::FCC6, LoongArch::FCC7, 
  };

  // CFR Bit set.
  const uint8_t CFRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 
  };

  // FCSR Register Class...
  const MCPhysReg FCSR[] = {
    LoongArch::FCSR0, LoongArch::FCSR1, LoongArch::FCSR2, LoongArch::FCSR3, 
  };

  // FCSR Bit set.
  const uint8_t FCSRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 
  };

  // SCR Register Class...
  const MCPhysReg SCR[] = {
    LoongArch::SCR0, LoongArch::SCR1, LoongArch::SCR2, LoongArch::SCR3, 
  };

  // SCR Bit set.
  const uint8_t SCRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
  };

  // FPR64 Register Class...
  const MCPhysReg FPR64[] = {
    LoongArch::F0_64, LoongArch::F1_64, LoongArch::F2_64, LoongArch::F3_64, LoongArch::F4_64, LoongArch::F5_64, LoongArch::F6_64, LoongArch::F7_64, LoongArch::F8_64, LoongArch::F9_64, LoongArch::F10_64, LoongArch::F11_64, LoongArch::F12_64, LoongArch::F13_64, LoongArch::F14_64, LoongArch::F15_64, LoongArch::F16_64, LoongArch::F17_64, LoongArch::F18_64, LoongArch::F19_64, LoongArch::F20_64, LoongArch::F21_64, LoongArch::F22_64, LoongArch::F23_64, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 
  };

  // FPR64 Bit set.
  const uint8_t FPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // LSX128 Register Class...
  const MCPhysReg LSX128[] = {
    LoongArch::VR0, LoongArch::VR1, LoongArch::VR2, LoongArch::VR3, LoongArch::VR4, LoongArch::VR5, LoongArch::VR6, LoongArch::VR7, LoongArch::VR8, LoongArch::VR9, LoongArch::VR10, LoongArch::VR11, LoongArch::VR12, LoongArch::VR13, LoongArch::VR14, LoongArch::VR15, LoongArch::VR16, LoongArch::VR17, LoongArch::VR18, LoongArch::VR19, LoongArch::VR20, LoongArch::VR21, LoongArch::VR22, LoongArch::VR23, LoongArch::VR24, LoongArch::VR25, LoongArch::VR26, LoongArch::VR27, LoongArch::VR28, LoongArch::VR29, LoongArch::VR30, LoongArch::VR31, 
  };

  // LSX128 Bit set.
  const uint8_t LSX128Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // LASX256 Register Class...
  const MCPhysReg LASX256[] = {
    LoongArch::XR0, LoongArch::XR1, LoongArch::XR2, LoongArch::XR3, LoongArch::XR4, LoongArch::XR5, LoongArch::XR6, LoongArch::XR7, LoongArch::XR8, LoongArch::XR9, LoongArch::XR10, LoongArch::XR11, LoongArch::XR12, LoongArch::XR13, LoongArch::XR14, LoongArch::XR15, LoongArch::XR16, LoongArch::XR17, LoongArch::XR18, LoongArch::XR19, LoongArch::XR20, LoongArch::XR21, LoongArch::XR22, LoongArch::XR23, LoongArch::XR24, LoongArch::XR25, LoongArch::XR26, LoongArch::XR27, LoongArch::XR28, LoongArch::XR29, LoongArch::XR30, LoongArch::XR31, 
  };

  // LASX256 Bit set.
  const uint8_t LASX256Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char LoongArchRegClassStrings[] = {
  /* 0 */ "FPR32\0"
  /* 6 */ "FPR64\0"
  /* 12 */ "LASX256\0"
  /* 20 */ "LSX128\0"
  /* 27 */ "SCR\0"
  /* 31 */ "CFR\0"
  /* 35 */ "GPR\0"
  /* 39 */ "FCSR\0"
  /* 44 */ "GPRT\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass LoongArchMCRegisterClasses[] = {
  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), LoongArch::FPR32RegClassID, 32, 1, true },
  { GPR, GPRBits, 35, 32, sizeof(GPRBits), LoongArch::GPRRegClassID, 0, 1, true },
  { GPRT, GPRTBits, 44, 17, sizeof(GPRTBits), LoongArch::GPRTRegClassID, 0, 1, true },
  { CFR, CFRBits, 31, 8, sizeof(CFRBits), LoongArch::CFRRegClassID, 0, 1, true },
  { FCSR, FCSRBits, 39, 4, sizeof(FCSRBits), LoongArch::FCSRRegClassID, 32, 1, false },
  { SCR, SCRBits, 27, 4, sizeof(SCRBits), LoongArch::SCRRegClassID, 0, 1, false },
  { FPR64, FPR64Bits, 6, 32, sizeof(FPR64Bits), LoongArch::FPR64RegClassID, 64, 1, true },
  { LSX128, LSX128Bits, 20, 32, sizeof(LSX128Bits), LoongArch::LSX128RegClassID, 128, 1, true },
  { LASX256, LASX256Bits, 12, 32, sizeof(LASX256Bits), LoongArch::LASX256RegClassID, 256, 1, true },
};

// LoongArch Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[] = {
  { 0U, LoongArch::R0 },
  { 1U, LoongArch::R1 },
  { 2U, LoongArch::R2 },
  { 3U, LoongArch::R3 },
  { 4U, LoongArch::R4 },
  { 5U, LoongArch::R5 },
  { 6U, LoongArch::R6 },
  { 7U, LoongArch::R7 },
  { 8U, LoongArch::R8 },
  { 9U, LoongArch::R9 },
  { 10U, LoongArch::R10 },
  { 11U, LoongArch::R11 },
  { 12U, LoongArch::R12 },
  { 13U, LoongArch::R13 },
  { 14U, LoongArch::R14 },
  { 15U, LoongArch::R15 },
  { 16U, LoongArch::R16 },
  { 17U, LoongArch::R17 },
  { 18U, LoongArch::R18 },
  { 19U, LoongArch::R19 },
  { 20U, LoongArch::R20 },
  { 21U, LoongArch::R21 },
  { 22U, LoongArch::R22 },
  { 23U, LoongArch::R23 },
  { 24U, LoongArch::R24 },
  { 25U, LoongArch::R25 },
  { 26U, LoongArch::R26 },
  { 27U, LoongArch::R27 },
  { 28U, LoongArch::R28 },
  { 29U, LoongArch::R29 },
  { 30U, LoongArch::R30 },
  { 31U, LoongArch::R31 },
  { 32U, LoongArch::F0_64 },
  { 33U, LoongArch::F1_64 },
  { 34U, LoongArch::F2_64 },
  { 35U, LoongArch::F3_64 },
  { 36U, LoongArch::F4_64 },
  { 37U, LoongArch::F5_64 },
  { 38U, LoongArch::F6_64 },
  { 39U, LoongArch::F7_64 },
  { 40U, LoongArch::F8_64 },
  { 41U, LoongArch::F9_64 },
  { 42U, LoongArch::F10_64 },
  { 43U, LoongArch::F11_64 },
  { 44U, LoongArch::F12_64 },
  { 45U, LoongArch::F13_64 },
  { 46U, LoongArch::F14_64 },
  { 47U, LoongArch::F15_64 },
  { 48U, LoongArch::F16_64 },
  { 49U, LoongArch::F17_64 },
  { 50U, LoongArch::F18_64 },
  { 51U, LoongArch::F19_64 },
  { 52U, LoongArch::F20_64 },
  { 53U, LoongArch::F21_64 },
  { 54U, LoongArch::F22_64 },
  { 55U, LoongArch::F23_64 },
  { 56U, LoongArch::F24_64 },
  { 57U, LoongArch::F25_64 },
  { 58U, LoongArch::F26_64 },
  { 59U, LoongArch::F27_64 },
  { 60U, LoongArch::F28_64 },
  { 61U, LoongArch::F29_64 },
  { 62U, LoongArch::F30_64 },
  { 63U, LoongArch::F31_64 },
};
extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize = std::size(LoongArchDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[] = {
  { 0U, LoongArch::R0 },
  { 1U, LoongArch::R1 },
  { 2U, LoongArch::R2 },
  { 3U, LoongArch::R3 },
  { 4U, LoongArch::R4 },
  { 5U, LoongArch::R5 },
  { 6U, LoongArch::R6 },
  { 7U, LoongArch::R7 },
  { 8U, LoongArch::R8 },
  { 9U, LoongArch::R9 },
  { 10U, LoongArch::R10 },
  { 11U, LoongArch::R11 },
  { 12U, LoongArch::R12 },
  { 13U, LoongArch::R13 },
  { 14U, LoongArch::R14 },
  { 15U, LoongArch::R15 },
  { 16U, LoongArch::R16 },
  { 17U, LoongArch::R17 },
  { 18U, LoongArch::R18 },
  { 19U, LoongArch::R19 },
  { 20U, LoongArch::R20 },
  { 21U, LoongArch::R21 },
  { 22U, LoongArch::R22 },
  { 23U, LoongArch::R23 },
  { 24U, LoongArch::R24 },
  { 25U, LoongArch::R25 },
  { 26U, LoongArch::R26 },
  { 27U, LoongArch::R27 },
  { 28U, LoongArch::R28 },
  { 29U, LoongArch::R29 },
  { 30U, LoongArch::R30 },
  { 31U, LoongArch::R31 },
  { 32U, LoongArch::F0_64 },
  { 33U, LoongArch::F1_64 },
  { 34U, LoongArch::F2_64 },
  { 35U, LoongArch::F3_64 },
  { 36U, LoongArch::F4_64 },
  { 37U, LoongArch::F5_64 },
  { 38U, LoongArch::F6_64 },
  { 39U, LoongArch::F7_64 },
  { 40U, LoongArch::F8_64 },
  { 41U, LoongArch::F9_64 },
  { 42U, LoongArch::F10_64 },
  { 43U, LoongArch::F11_64 },
  { 44U, LoongArch::F12_64 },
  { 45U, LoongArch::F13_64 },
  { 46U, LoongArch::F14_64 },
  { 47U, LoongArch::F15_64 },
  { 48U, LoongArch::F16_64 },
  { 49U, LoongArch::F17_64 },
  { 50U, LoongArch::F18_64 },
  { 51U, LoongArch::F19_64 },
  { 52U, LoongArch::F20_64 },
  { 53U, LoongArch::F21_64 },
  { 54U, LoongArch::F22_64 },
  { 55U, LoongArch::F23_64 },
  { 56U, LoongArch::F24_64 },
  { 57U, LoongArch::F25_64 },
  { 58U, LoongArch::F26_64 },
  { 59U, LoongArch::F27_64 },
  { 60U, LoongArch::F28_64 },
  { 61U, LoongArch::F29_64 },
  { 62U, LoongArch::F30_64 },
  { 63U, LoongArch::F31_64 },
};
extern const unsigned LoongArchEHFlavour0Dwarf2LSize = std::size(LoongArchEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[] = {
  { LoongArch::F0, 32U },
  { LoongArch::F1, 33U },
  { LoongArch::F2, 34U },
  { LoongArch::F3, 35U },
  { LoongArch::F4, 36U },
  { LoongArch::F5, 37U },
  { LoongArch::F6, 38U },
  { LoongArch::F7, 39U },
  { LoongArch::F8, 40U },
  { LoongArch::F9, 41U },
  { LoongArch::F10, 42U },
  { LoongArch::F11, 43U },
  { LoongArch::F12, 44U },
  { LoongArch::F13, 45U },
  { LoongArch::F14, 46U },
  { LoongArch::F15, 47U },
  { LoongArch::F16, 48U },
  { LoongArch::F17, 49U },
  { LoongArch::F18, 50U },
  { LoongArch::F19, 51U },
  { LoongArch::F20, 52U },
  { LoongArch::F21, 53U },
  { LoongArch::F22, 54U },
  { LoongArch::F23, 55U },
  { LoongArch::F24, 56U },
  { LoongArch::F25, 57U },
  { LoongArch::F26, 58U },
  { LoongArch::F27, 59U },
  { LoongArch::F28, 60U },
  { LoongArch::F29, 61U },
  { LoongArch::F30, 62U },
  { LoongArch::F31, 63U },
  { LoongArch::R0, 0U },
  { LoongArch::R1, 1U },
  { LoongArch::R2, 2U },
  { LoongArch::R3, 3U },
  { LoongArch::R4, 4U },
  { LoongArch::R5, 5U },
  { LoongArch::R6, 6U },
  { LoongArch::R7, 7U },
  { LoongArch::R8, 8U },
  { LoongArch::R9, 9U },
  { LoongArch::R10, 10U },
  { LoongArch::R11, 11U },
  { LoongArch::R12, 12U },
  { LoongArch::R13, 13U },
  { LoongArch::R14, 14U },
  { LoongArch::R15, 15U },
  { LoongArch::R16, 16U },
  { LoongArch::R17, 17U },
  { LoongArch::R18, 18U },
  { LoongArch::R19, 19U },
  { LoongArch::R20, 20U },
  { LoongArch::R21, 21U },
  { LoongArch::R22, 22U },
  { LoongArch::R23, 23U },
  { LoongArch::R24, 24U },
  { LoongArch::R25, 25U },
  { LoongArch::R26, 26U },
  { LoongArch::R27, 27U },
  { LoongArch::R28, 28U },
  { LoongArch::R29, 29U },
  { LoongArch::R30, 30U },
  { LoongArch::R31, 31U },
  { LoongArch::VR0, 32U },
  { LoongArch::VR1, 33U },
  { LoongArch::VR2, 34U },
  { LoongArch::VR3, 35U },
  { LoongArch::VR4, 36U },
  { LoongArch::VR5, 37U },
  { LoongArch::VR6, 38U },
  { LoongArch::VR7, 39U },
  { LoongArch::VR8, 40U },
  { LoongArch::VR9, 41U },
  { LoongArch::VR10, 42U },
  { LoongArch::VR11, 43U },
  { LoongArch::VR12, 44U },
  { LoongArch::VR13, 45U },
  { LoongArch::VR14, 46U },
  { LoongArch::VR15, 47U },
  { LoongArch::VR16, 48U },
  { LoongArch::VR17, 49U },
  { LoongArch::VR18, 50U },
  { LoongArch::VR19, 51U },
  { LoongArch::VR20, 52U },
  { LoongArch::VR21, 53U },
  { LoongArch::VR22, 54U },
  { LoongArch::VR23, 55U },
  { LoongArch::VR24, 56U },
  { LoongArch::VR25, 57U },
  { LoongArch::VR26, 58U },
  { LoongArch::VR27, 59U },
  { LoongArch::VR28, 60U },
  { LoongArch::VR29, 61U },
  { LoongArch::VR30, 62U },
  { LoongArch::VR31, 63U },
  { LoongArch::XR0, 32U },
  { LoongArch::XR1, 33U },
  { LoongArch::XR2, 34U },
  { LoongArch::XR3, 35U },
  { LoongArch::XR4, 36U },
  { LoongArch::XR5, 37U },
  { LoongArch::XR6, 38U },
  { LoongArch::XR7, 39U },
  { LoongArch::XR8, 40U },
  { LoongArch::XR9, 41U },
  { LoongArch::XR10, 42U },
  { LoongArch::XR11, 43U },
  { LoongArch::XR12, 44U },
  { LoongArch::XR13, 45U },
  { LoongArch::XR14, 46U },
  { LoongArch::XR15, 47U },
  { LoongArch::XR16, 48U },
  { LoongArch::XR17, 49U },
  { LoongArch::XR18, 50U },
  { LoongArch::XR19, 51U },
  { LoongArch::XR20, 52U },
  { LoongArch::XR21, 53U },
  { LoongArch::XR22, 54U },
  { LoongArch::XR23, 55U },
  { LoongArch::XR24, 56U },
  { LoongArch::XR25, 57U },
  { LoongArch::XR26, 58U },
  { LoongArch::XR27, 59U },
  { LoongArch::XR28, 60U },
  { LoongArch::XR29, 61U },
  { LoongArch::XR30, 62U },
  { LoongArch::XR31, 63U },
  { LoongArch::F0_64, 32U },
  { LoongArch::F1_64, 33U },
  { LoongArch::F2_64, 34U },
  { LoongArch::F3_64, 35U },
  { LoongArch::F4_64, 36U },
  { LoongArch::F5_64, 37U },
  { LoongArch::F6_64, 38U },
  { LoongArch::F7_64, 39U },
  { LoongArch::F8_64, 40U },
  { LoongArch::F9_64, 41U },
  { LoongArch::F10_64, 42U },
  { LoongArch::F11_64, 43U },
  { LoongArch::F12_64, 44U },
  { LoongArch::F13_64, 45U },
  { LoongArch::F14_64, 46U },
  { LoongArch::F15_64, 47U },
  { LoongArch::F16_64, 48U },
  { LoongArch::F17_64, 49U },
  { LoongArch::F18_64, 50U },
  { LoongArch::F19_64, 51U },
  { LoongArch::F20_64, 52U },
  { LoongArch::F21_64, 53U },
  { LoongArch::F22_64, 54U },
  { LoongArch::F23_64, 55U },
  { LoongArch::F24_64, 56U },
  { LoongArch::F25_64, 57U },
  { LoongArch::F26_64, 58U },
  { LoongArch::F27_64, 59U },
  { LoongArch::F28_64, 60U },
  { LoongArch::F29_64, 61U },
  { LoongArch::F30_64, 62U },
  { LoongArch::F31_64, 63U },
};
extern const unsigned LoongArchDwarfFlavour0L2DwarfSize = std::size(LoongArchDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[] = {
  { LoongArch::F0, 32U },
  { LoongArch::F1, 33U },
  { LoongArch::F2, 34U },
  { LoongArch::F3, 35U },
  { LoongArch::F4, 36U },
  { LoongArch::F5, 37U },
  { LoongArch::F6, 38U },
  { LoongArch::F7, 39U },
  { LoongArch::F8, 40U },
  { LoongArch::F9, 41U },
  { LoongArch::F10, 42U },
  { LoongArch::F11, 43U },
  { LoongArch::F12, 44U },
  { LoongArch::F13, 45U },
  { LoongArch::F14, 46U },
  { LoongArch::F15, 47U },
  { LoongArch::F16, 48U },
  { LoongArch::F17, 49U },
  { LoongArch::F18, 50U },
  { LoongArch::F19, 51U },
  { LoongArch::F20, 52U },
  { LoongArch::F21, 53U },
  { LoongArch::F22, 54U },
  { LoongArch::F23, 55U },
  { LoongArch::F24, 56U },
  { LoongArch::F25, 57U },
  { LoongArch::F26, 58U },
  { LoongArch::F27, 59U },
  { LoongArch::F28, 60U },
  { LoongArch::F29, 61U },
  { LoongArch::F30, 62U },
  { LoongArch::F31, 63U },
  { LoongArch::R0, 0U },
  { LoongArch::R1, 1U },
  { LoongArch::R2, 2U },
  { LoongArch::R3, 3U },
  { LoongArch::R4, 4U },
  { LoongArch::R5, 5U },
  { LoongArch::R6, 6U },
  { LoongArch::R7, 7U },
  { LoongArch::R8, 8U },
  { LoongArch::R9, 9U },
  { LoongArch::R10, 10U },
  { LoongArch::R11, 11U },
  { LoongArch::R12, 12U },
  { LoongArch::R13, 13U },
  { LoongArch::R14, 14U },
  { LoongArch::R15, 15U },
  { LoongArch::R16, 16U },
  { LoongArch::R17, 17U },
  { LoongArch::R18, 18U },
  { LoongArch::R19, 19U },
  { LoongArch::R20, 20U },
  { LoongArch::R21, 21U },
  { LoongArch::R22, 22U },
  { LoongArch::R23, 23U },
  { LoongArch::R24, 24U },
  { LoongArch::R25, 25U },
  { LoongArch::R26, 26U },
  { LoongArch::R27, 27U },
  { LoongArch::R28, 28U },
  { LoongArch::R29, 29U },
  { LoongArch::R30, 30U },
  { LoongArch::R31, 31U },
  { LoongArch::VR0, 32U },
  { LoongArch::VR1, 33U },
  { LoongArch::VR2, 34U },
  { LoongArch::VR3, 35U },
  { LoongArch::VR4, 36U },
  { LoongArch::VR5, 37U },
  { LoongArch::VR6, 38U },
  { LoongArch::VR7, 39U },
  { LoongArch::VR8, 40U },
  { LoongArch::VR9, 41U },
  { LoongArch::VR10, 42U },
  { LoongArch::VR11, 43U },
  { LoongArch::VR12, 44U },
  { LoongArch::VR13, 45U },
  { LoongArch::VR14, 46U },
  { LoongArch::VR15, 47U },
  { LoongArch::VR16, 48U },
  { LoongArch::VR17, 49U },
  { LoongArch::VR18, 50U },
  { LoongArch::VR19, 51U },
  { LoongArch::VR20, 52U },
  { LoongArch::VR21, 53U },
  { LoongArch::VR22, 54U },
  { LoongArch::VR23, 55U },
  { LoongArch::VR24, 56U },
  { LoongArch::VR25, 57U },
  { LoongArch::VR26, 58U },
  { LoongArch::VR27, 59U },
  { LoongArch::VR28, 60U },
  { LoongArch::VR29, 61U },
  { LoongArch::VR30, 62U },
  { LoongArch::VR31, 63U },
  { LoongArch::XR0, 32U },
  { LoongArch::XR1, 33U },
  { LoongArch::XR2, 34U },
  { LoongArch::XR3, 35U },
  { LoongArch::XR4, 36U },
  { LoongArch::XR5, 37U },
  { LoongArch::XR6, 38U },
  { LoongArch::XR7, 39U },
  { LoongArch::XR8, 40U },
  { LoongArch::XR9, 41U },
  { LoongArch::XR10, 42U },
  { LoongArch::XR11, 43U },
  { LoongArch::XR12, 44U },
  { LoongArch::XR13, 45U },
  { LoongArch::XR14, 46U },
  { LoongArch::XR15, 47U },
  { LoongArch::XR16, 48U },
  { LoongArch::XR17, 49U },
  { LoongArch::XR18, 50U },
  { LoongArch::XR19, 51U },
  { LoongArch::XR20, 52U },
  { LoongArch::XR21, 53U },
  { LoongArch::XR22, 54U },
  { LoongArch::XR23, 55U },
  { LoongArch::XR24, 56U },
  { LoongArch::XR25, 57U },
  { LoongArch::XR26, 58U },
  { LoongArch::XR27, 59U },
  { LoongArch::XR28, 60U },
  { LoongArch::XR29, 61U },
  { LoongArch::XR30, 62U },
  { LoongArch::XR31, 63U },
  { LoongArch::F0_64, 32U },
  { LoongArch::F1_64, 33U },
  { LoongArch::F2_64, 34U },
  { LoongArch::F3_64, 35U },
  { LoongArch::F4_64, 36U },
  { LoongArch::F5_64, 37U },
  { LoongArch::F6_64, 38U },
  { LoongArch::F7_64, 39U },
  { LoongArch::F8_64, 40U },
  { LoongArch::F9_64, 41U },
  { LoongArch::F10_64, 42U },
  { LoongArch::F11_64, 43U },
  { LoongArch::F12_64, 44U },
  { LoongArch::F13_64, 45U },
  { LoongArch::F14_64, 46U },
  { LoongArch::F15_64, 47U },
  { LoongArch::F16_64, 48U },
  { LoongArch::F17_64, 49U },
  { LoongArch::F18_64, 50U },
  { LoongArch::F19_64, 51U },
  { LoongArch::F20_64, 52U },
  { LoongArch::F21_64, 53U },
  { LoongArch::F22_64, 54U },
  { LoongArch::F23_64, 55U },
  { LoongArch::F24_64, 56U },
  { LoongArch::F25_64, 57U },
  { LoongArch::F26_64, 58U },
  { LoongArch::F27_64, 59U },
  { LoongArch::F28_64, 60U },
  { LoongArch::F29_64, 61U },
  { LoongArch::F30_64, 62U },
  { LoongArch::F31_64, 63U },
};
extern const unsigned LoongArchEHFlavour0L2DwarfSize = std::size(LoongArchEHFlavour0L2Dwarf);

extern const uint16_t LoongArchRegEncodingTable[] = {
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
};
static inline void InitLoongArchMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(LoongArchRegDesc, 177, RA, PC, LoongArchMCRegisterClasses, 9, LoongArchRegUnitRoots, 80, LoongArchRegDiffLists, LoongArchLaneMaskLists, LoongArchRegStrings, LoongArchRegClassStrings, LoongArchSubRegIdxLists, 4,
LoongArchSubRegIdxRanges, LoongArchRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class LoongArchFrameLowering;

struct LoongArchGenRegisterInfo : public TargetRegisterInfo {
  explicit LoongArchGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const LoongArchFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace LoongArch { // Register classes
  extern const TargetRegisterClass FPR32RegClass;
  extern const TargetRegisterClass GPRRegClass;
  extern const TargetRegisterClass GPRTRegClass;
  extern const TargetRegisterClass CFRRegClass;
  extern const TargetRegisterClass FCSRRegClass;
  extern const TargetRegisterClass SCRRegClass;
  extern const TargetRegisterClass FPR64RegClass;
  extern const TargetRegisterClass LSX128RegClass;
  extern const TargetRegisterClass LASX256RegClass;
} // end namespace LoongArch

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass LoongArchMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i32, MVT::Other,
  /* 2 */ MVT::i64, MVT::Other,
  /* 4 */ MVT::f32, MVT::Other,
  /* 6 */ MVT::f64, MVT::Other,
  /* 8 */ MVT::v4f32, MVT::v2f64, MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::Other,
  /* 15 */ MVT::v8f32, MVT::v4f64, MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_128", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_32
  LaneBitmask(0x0000000000000001), // sub_64
  LaneBitmask(0x0000000000000001), // sub_128
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 32, 32, 32, /*VTLists+*/4 },    // FPR32
  { 32, 32, 32, /*VTLists+*/0 },    // GPR
  { 32, 32, 32, /*VTLists+*/0 },    // GPRT
  { 32, 32, 32, /*VTLists+*/0 },    // CFR
  { 32, 32, 32, /*VTLists+*/0 },    // FCSR
  { 32, 32, 32, /*VTLists+*/0 },    // SCR
  { 64, 64, 64, /*VTLists+*/6 },    // FPR64
  { 128, 128, 128, /*VTLists+*/8 },    // LSX128
  { 256, 256, 256, /*VTLists+*/15 },    // LASX256
  // Mode = 1 (LA64)
  { 32, 32, 32, /*VTLists+*/4 },    // FPR32
  { 64, 64, 64, /*VTLists+*/2 },    // GPR
  { 64, 64, 64, /*VTLists+*/2 },    // GPRT
  { 64, 64, 64, /*VTLists+*/2 },    // CFR
  { 32, 32, 32, /*VTLists+*/0 },    // FCSR
  { 64, 64, 64, /*VTLists+*/2 },    // SCR
  { 64, 64, 64, /*VTLists+*/6 },    // FPR64
  { 128, 128, 128, /*VTLists+*/8 },    // LSX128
  { 256, 256, 256, /*VTLists+*/15 },    // LASX256
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t FPR32SubClassMask[] = {
  0x00000001, 
  0x000001c0, // sub_32
};

static const uint32_t GPRSubClassMask[] = {
  0x00000006, 
};

static const uint32_t GPRTSubClassMask[] = {
  0x00000004, 
};

static const uint32_t CFRSubClassMask[] = {
  0x00000008, 
};

static const uint32_t FCSRSubClassMask[] = {
  0x00000010, 
};

static const uint32_t SCRSubClassMask[] = {
  0x00000020, 
};

static const uint32_t FPR64SubClassMask[] = {
  0x00000040, 
  0x00000180, // sub_64
};

static const uint32_t LSX128SubClassMask[] = {
  0x00000080, 
  0x00000100, // sub_128
};

static const uint32_t LASX256SubClassMask[] = {
  0x00000100, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 0,
  /* 2 */ 2, 0,
  /* 4 */ 3, 0,
};

static const TargetRegisterClass *const GPRTSuperclasses[] = {
  &LoongArch::GPRRegClass,
  nullptr
};


namespace LoongArch {   // Register class instances
  extern const TargetRegisterClass FPR32RegClass = {
    &LoongArchMCRegisterClasses[FPR32RegClassID],
    FPR32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRRegClass = {
    &LoongArchMCRegisterClasses[GPRRegClassID],
    GPRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRTRegClass = {
    &LoongArchMCRegisterClasses[GPRTRegClassID],
    GPRTSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRTSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CFRRegClass = {
    &LoongArchMCRegisterClasses[CFRRegClassID],
    CFRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FCSRRegClass = {
    &LoongArchMCRegisterClasses[FCSRRegClassID],
    FCSRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass SCRRegClass = {
    &LoongArchMCRegisterClasses[SCRRegClassID],
    SCRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FPR64RegClass = {
    &LoongArchMCRegisterClasses[FPR64RegClassID],
    FPR64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LSX128RegClass = {
    &LoongArchMCRegisterClasses[LSX128RegClassID],
    LSX128SubClassMask,
    SuperRegIdxSeqs + 4,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LASX256RegClass = {
    &LoongArchMCRegisterClasses[LASX256RegClassID],
    LASX256SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

} // end namespace LoongArch

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &LoongArch::FPR32RegClass,
    &LoongArch::GPRRegClass,
    &LoongArch::GPRTRegClass,
    &LoongArch::CFRRegClass,
    &LoongArch::FCSRRegClass,
    &LoongArch::SCRRegClass,
    &LoongArch::FPR64RegClass,
    &LoongArch::LSX128RegClass,
    &LoongArch::LASX256RegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc LoongArchRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned LoongArchGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t Rows[1][3] = {
    { LoongArch::sub_32, LoongArch::sub_64, 0, },
  };

  --IdxA; assert(IdxA < 3); (void) IdxA;
  --IdxB; assert(IdxB < 3);
  return Rows[0][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 }  // Sequence 0
  };
  static const uint8_t CompositeSequences[] = {
    0, // to sub_32
    0, // to sub_64
    0 // to sub_128
  };

LaneBitmask LoongArchGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask LoongArchGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 3 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *LoongArchGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[9][3] = {
    { // FPR32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_128
    },
    { // GPR
      0,  // sub_32
      0,  // sub_64
      0,  // sub_128
    },
    { // GPRT
      0,  // sub_32
      0,  // sub_64
      0,  // sub_128
    },
    { // CFR
      0,  // sub_32
      0,  // sub_64
      0,  // sub_128
    },
    { // FCSR
      0,  // sub_32
      0,  // sub_64
      0,  // sub_128
    },
    { // SCR
      0,  // sub_32
      0,  // sub_64
      0,  // sub_128
    },
    { // FPR64
      7,  // sub_32 -> FPR64
      0,  // sub_64
      0,  // sub_128
    },
    { // LSX128
      8,  // sub_32 -> LSX128
      8,  // sub_64 -> LSX128
      0,  // sub_128
    },
    { // LASX256
      9,  // sub_32 -> LASX256
      9,  // sub_64 -> LASX256
      9,  // sub_128 -> LASX256
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 3 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *LoongArchGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[9][3] = {
    { // FPR32
      0,  // FPR32:sub_32
      0,  // FPR32:sub_64
      0,  // FPR32:sub_128
    },
    { // GPR
      0,  // GPR:sub_32
      0,  // GPR:sub_64
      0,  // GPR:sub_128
    },
    { // GPRT
      0,  // GPRT:sub_32
      0,  // GPRT:sub_64
      0,  // GPRT:sub_128
    },
    { // CFR
      0,  // CFR:sub_32
      0,  // CFR:sub_64
      0,  // CFR:sub_128
    },
    { // FCSR
      0,  // FCSR:sub_32
      0,  // FCSR:sub_64
      0,  // FCSR:sub_128
    },
    { // SCR
      0,  // SCR:sub_32
      0,  // SCR:sub_64
      0,  // SCR:sub_128
    },
    { // FPR64
      1,  // FPR64:sub_32 -> FPR32
      0,  // FPR64:sub_64
      0,  // FPR64:sub_128
    },
    { // LSX128
      1,  // LSX128:sub_32 -> FPR32
      7,  // LSX128:sub_64 -> FPR64
      0,  // LSX128:sub_128
    },
    { // LASX256
      1,  // LASX256:sub_32 -> FPR32
      7,  // LASX256:sub_64 -> FPR64
      8,  // LASX256:sub_128 -> LSX128
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 3 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &LoongArchGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 32},    // FPR32
    {1, 32},    // GPR
    {1, 17},    // GPRT
    {1, 8},   // CFR
    {0, 0},   // FCSR
    {0, 0},   // SCR
    {1, 32},    // FPR64
    {1, 32},    // LSX128
    {1, 32},    // LASX256
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned LoongArchGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 80 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned LoongArchGenRegisterInfo::getNumRegPressureSets() const {
  return 4;
}

// Get the name of this register unit pressure set.
const char *LoongArchGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "CFR",
    "GPRT",
    "FPR32",
    "GPR",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned LoongArchGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    8,    // 0: CFR
    17,   // 1: GPRT
    32,   // 2: FPR32
    32,   // 3: GPR
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 2, -1,
  /* 4 */ 1, 3, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *LoongArchGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    2,5,4,0,1,1,2,2,2,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *LoongArchGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 80 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,1,1,1,1,5,5,5,5,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,1,1,1,1,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc LoongArchRegDesc[];
extern const int16_t LoongArchRegDiffLists[];
extern const LaneBitmask LoongArchLaneMaskLists[];
extern const char LoongArchRegStrings[];
extern const char LoongArchRegClassStrings[];
extern const MCPhysReg LoongArchRegUnitRoots[][2];
extern const uint16_t LoongArchSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits LoongArchSubRegIdxRanges[];
extern const uint16_t LoongArchRegEncodingTable[];
// LoongArch Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0Dwarf2L[];
extern const unsigned LoongArchDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0Dwarf2L[];
extern const unsigned LoongArchEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchDwarfFlavour0L2Dwarf[];
extern const unsigned LoongArchDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair LoongArchEHFlavour0L2Dwarf[];
extern const unsigned LoongArchEHFlavour0L2DwarfSize;

LoongArchGenRegisterInfo::
LoongArchGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&LoongArchRegInfoDesc, RegisterClasses, RegisterClasses+9,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFE), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(LoongArchRegDesc, 177, RA, PC,
                     LoongArchMCRegisterClasses, 9,
                     LoongArchRegUnitRoots,
                     80,
                     LoongArchRegDiffLists,
                     LoongArchLaneMaskLists,
                     LoongArchRegStrings,
                     LoongArchRegClassStrings,
                     LoongArchSubRegIdxLists,
                     4,
                     LoongArchSubRegIdxRanges,
                     LoongArchRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(LoongArchDwarfFlavour0Dwarf2L, LoongArchDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(LoongArchEHFlavour0Dwarf2L, LoongArchEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(LoongArchDwarfFlavour0L2Dwarf, LoongArchDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(LoongArchEHFlavour0L2Dwarf, LoongArchEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24_64, LoongArch::F25_64, LoongArch::F26_64, LoongArch::F27_64, LoongArch::F28_64, LoongArch::F29_64, LoongArch::F30_64, LoongArch::F31_64, 0 };
static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x0001fe00, };
static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, LoongArch::F24, LoongArch::F25, LoongArch::F26, LoongArch::F27, LoongArch::F28, LoongArch::F29, LoongArch::F30, LoongArch::F31, 0 };
static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0xfe000000, 0x00006001, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_ILP32S_LP64S_SaveList[] = { LoongArch::R1, LoongArch::R22, LoongArch::R23, LoongArch::R24, LoongArch::R25, LoongArch::R26, LoongArch::R27, LoongArch::R28, LoongArch::R29, LoongArch::R30, LoongArch::R31, 0 };
static const uint32_t CSR_ILP32S_LP64S_RegMask[] = { 0x00000000, 0x00006000, 0x00001ff8, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000000, 0x00002000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> LoongArchGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_ILP32D_LP64D_RegMask,
    CSR_ILP32F_LP64F_RegMask,
    CSR_ILP32S_LP64S_RegMask,
    CSR_NoRegs_RegMask,
  };
  return ArrayRef(Masks);
}

bool LoongArchGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool LoongArchGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool LoongArchGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool LoongArchGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      PhysReg == LoongArch::R0 ||
      false;
}

ArrayRef<const char *> LoongArchGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR_ILP32D_LP64D",
    "CSR_ILP32F_LP64F",
    "CSR_ILP32S_LP64S",
    "CSR_NoRegs",
  };
  return ArrayRef(Names);
}

const LoongArchFrameLowering *
LoongArchGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const LoongArchFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31