Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/MSP430/MSP430GenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
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|* From: MSP430.td                                                            *|
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|*                                                                            *|
8
\*===----------------------------------------------------------------------===*/
9
10
11
#ifdef GET_ASSEMBLER_HEADER
12
#undef GET_ASSEMBLER_HEADER
13
  // This should be included into the middle of the declaration of
14
  // your subclasses implementation of MCTargetAsmParser.
15
  FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
16
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
17
                       const OperandVector &Operands);
18
  void convertToMapAndConstraints(unsigned Kind,
19
                           const OperandVector &Operands) override;
20
  unsigned MatchInstructionImpl(const OperandVector &Operands,
21
                                MCInst &Inst,
22
                                uint64_t &ErrorInfo,
23
                                FeatureBitset &MissingFeatures,
24
                                bool matchingInlineAsm,
25
                                unsigned VariantID = 0);
26
  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
28
                                uint64_t &ErrorInfo,
29
                                bool matchingInlineAsm,
30
0
                                unsigned VariantID = 0) {
31
0
    FeatureBitset MissingFeatures;
32
0
    return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
33
0
                                matchingInlineAsm, VariantID);
34
0
  }
35
36
#endif // GET_ASSEMBLER_HEADER
37
38
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#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
40
#undef GET_OPERAND_DIAGNOSTIC_TYPES
41
42
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
43
44
45
#ifdef GET_REGISTER_MATCHER
46
#undef GET_REGISTER_MATCHER
47
48
// Bits for subtarget features that participate in instruction matching.
49
enum SubtargetFeatureBits : uint8_t {
50
};
51
52
0
static unsigned MatchRegisterName(StringRef Name) {
53
0
  switch (Name.size()) {
54
0
  default: break;
55
0
  case 2:  // 20 strings to match.
56
0
    if (Name[0] != 'r')
57
0
      break;
58
0
    switch (Name[1]) {
59
0
    default: break;
60
0
    case '0':  // 2 strings to match.
61
0
      return 3;  // "r0"
62
0
    case '1':  // 2 strings to match.
63
0
      return 5;  // "r1"
64
0
    case '2':  // 2 strings to match.
65
0
      return 7;  // "r2"
66
0
    case '3':  // 2 strings to match.
67
0
      return 1;  // "r3"
68
0
    case '4':  // 2 strings to match.
69
0
      return 9;  // "r4"
70
0
    case '5':  // 2 strings to match.
71
0
      return 10;  // "r5"
72
0
    case '6':  // 2 strings to match.
73
0
      return 11;  // "r6"
74
0
    case '7':  // 2 strings to match.
75
0
      return 12;  // "r7"
76
0
    case '8':  // 2 strings to match.
77
0
      return 13;  // "r8"
78
0
    case '9':  // 2 strings to match.
79
0
      return 14;  // "r9"
80
0
    }
81
0
    break;
82
0
  case 3:  // 12 strings to match.
83
0
    if (memcmp(Name.data()+0, "r1", 2) != 0)
84
0
      break;
85
0
    switch (Name[2]) {
86
0
    default: break;
87
0
    case '0':  // 2 strings to match.
88
0
      return 15;  // "r10"
89
0
    case '1':  // 2 strings to match.
90
0
      return 16;  // "r11"
91
0
    case '2':  // 2 strings to match.
92
0
      return 17;  // "r12"
93
0
    case '3':  // 2 strings to match.
94
0
      return 18;  // "r13"
95
0
    case '4':  // 2 strings to match.
96
0
      return 19;  // "r14"
97
0
    case '5':  // 2 strings to match.
98
0
      return 20;  // "r15"
99
0
    }
100
0
    break;
101
0
  }
102
0
  return 0;
103
0
}
104
105
0
static unsigned MatchRegisterAltName(StringRef Name) {
106
0
  switch (Name.size()) {
107
0
  default: break;
108
0
  case 2:  // 10 strings to match.
109
0
    switch (Name[0]) {
110
0
    default: break;
111
0
    case 'c':  // 2 strings to match.
112
0
      if (Name[1] != 'g')
113
0
        break;
114
0
      return 1;  // "cg"
115
0
    case 'f':  // 2 strings to match.
116
0
      if (Name[1] != 'p')
117
0
        break;
118
0
      return 9;  // "fp"
119
0
    case 'p':  // 2 strings to match.
120
0
      if (Name[1] != 'c')
121
0
        break;
122
0
      return 3;  // "pc"
123
0
    case 's':  // 4 strings to match.
124
0
      switch (Name[1]) {
125
0
      default: break;
126
0
      case 'p':  // 2 strings to match.
127
0
        return 5;  // "sp"
128
0
      case 'r':  // 2 strings to match.
129
0
        return 7;  // "sr"
130
0
      }
131
0
      break;
132
0
    }
133
0
    break;
134
0
  }
135
0
  return 0;
136
0
}
137
138
#endif // GET_REGISTER_MATCHER
139
140
141
#ifdef GET_SUBTARGET_FEATURE_NAME
142
#undef GET_SUBTARGET_FEATURE_NAME
143
144
// User-level names for subtarget features that participate in
145
// instruction matching.
146
static const char *getSubtargetFeatureName(uint64_t Val) {
147
  return "(unknown)";
148
}
149
150
#endif // GET_SUBTARGET_FEATURE_NAME
151
152
153
#ifdef GET_MATCHER_IMPLEMENTATION
154
#undef GET_MATCHER_IMPLEMENTATION
155
156
enum {
157
  Tie0_1_1,
158
  Tie1_1_1,
159
};
160
161
static const uint8_t TiedAsmOperandTable[][3] = {
162
  /* Tie0_1_1 */ { 0, 1, 1 },
163
  /* Tie1_1_1 */ { 1, 1, 1 },
164
};
165
166
namespace {
167
enum OperatorConversionKind {
168
  CVT_Done,
169
  CVT_Reg,
170
  CVT_Tied,
171
  CVT_95_Reg,
172
  CVT_imm_95_0,
173
  CVT_95_addMemOperands,
174
  CVT_95_addImmOperands,
175
  CVT_95_addRegOperands,
176
  CVT_regSR,
177
  CVT_imm_95_1,
178
  CVT_imm_95_4,
179
  CVT_imm_95_2,
180
  CVT_imm_95_8,
181
  CVT_imm_95__MINUS_1,
182
  CVT_regCG,
183
  CVT_NUM_CONVERTERS
184
};
185
186
enum InstructionConversionKind {
187
  Convert__Reg1_0__Tie0_1_1__imm_95_0,
188
  Convert__Mem2_0__imm_95_0,
189
  Convert__Reg1_1__Tie0_1_1__Reg1_0,
190
  Convert__Mem2_1__Reg1_0,
191
  Convert__Reg1_1__Tie0_1_1__CGImm1_0,
192
  Convert__Mem2_1__CGImm1_0,
193
  Convert__Reg1_1__Tie0_1_1__Imm1_0,
194
  Convert__Mem2_1__Imm1_0,
195
  Convert__Reg1_1__Tie0_1_1__IndReg1_0,
196
  Convert__Mem2_1__IndReg1_0,
197
  Convert__Reg1_1__Tie0_1_1__Mem2_0,
198
  Convert__Mem2_1__Mem2_0,
199
  Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1,
200
  Convert__Mem2_1__PostIndReg1_0,
201
  Convert__Reg1_1__Reg1_0,
202
  Convert__Reg1_1__CGImm1_0,
203
  Convert__Reg1_1__Imm1_0,
204
  Convert__Reg1_1__IndReg1_0,
205
  Convert__Reg1_1__Mem2_0,
206
  Convert__Reg1_1__PostIndReg1_0,
207
  Convert__Reg1_0,
208
  Convert__Imm1_0,
209
  Convert__Mem2_0,
210
  Convert__IndReg1_0,
211
  Convert__PostIndReg1_0,
212
  Convert__Reg1_0__imm_95_0,
213
  Convert__regSR__Tie0_1_1__imm_95_1,
214
  Convert__regSR__Tie0_1_1__imm_95_4,
215
  Convert__regSR__Tie0_1_1__imm_95_2,
216
  Convert__Reg1_0__Tie0_1_1__imm_95_1,
217
  Convert__Mem2_0__imm_95_1,
218
  Convert__Reg1_0__Tie0_1_1__imm_95_2,
219
  Convert__Mem2_0__imm_95_2,
220
  Convert__regSR__Tie0_1_1__imm_95_8,
221
  Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1,
222
  Convert__Mem2_0__imm_95__MINUS_1,
223
  Convert__Imm1_1__Imm1_0,
224
  Convert__Reg1_1__PostIndReg1_0__Tie1_1_1,
225
  Convert__regCG__imm_95_0,
226
  Convert__CGImm1_0,
227
  Convert_NoOperands,
228
  Convert__Reg1_0__Tie0_1_1__Reg1_0,
229
  Convert__Mem2_0__Mem2_0,
230
  Convert__Reg1_0__Tie0_1_1,
231
  CVT_NUM_SIGNATURES
232
};
233
234
} // end anonymous namespace
235
236
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][9] = {
237
  // Convert__Reg1_0__Tie0_1_1__imm_95_0
238
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_0, 0, CVT_Done },
239
  // Convert__Mem2_0__imm_95_0
240
  { CVT_95_addMemOperands, 1, CVT_imm_95_0, 0, CVT_Done },
241
  // Convert__Reg1_1__Tie0_1_1__Reg1_0
242
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
243
  // Convert__Mem2_1__Reg1_0
244
  { CVT_95_addMemOperands, 2, CVT_95_Reg, 1, CVT_Done },
245
  // Convert__Reg1_1__Tie0_1_1__CGImm1_0
246
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
247
  // Convert__Mem2_1__CGImm1_0
248
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
249
  // Convert__Reg1_1__Tie0_1_1__Imm1_0
250
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addImmOperands, 1, CVT_Done },
251
  // Convert__Mem2_1__Imm1_0
252
  { CVT_95_addMemOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
253
  // Convert__Reg1_1__Tie0_1_1__IndReg1_0
254
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addRegOperands, 1, CVT_Done },
255
  // Convert__Mem2_1__IndReg1_0
256
  { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done },
257
  // Convert__Reg1_1__Tie0_1_1__Mem2_0
258
  { CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 1, CVT_Done },
259
  // Convert__Mem2_1__Mem2_0
260
  { CVT_95_addMemOperands, 2, CVT_95_addMemOperands, 1, CVT_Done },
261
  // Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1
262
  { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Tied, Tie1_1_1, CVT_Done },
263
  // Convert__Mem2_1__PostIndReg1_0
264
  { CVT_95_addMemOperands, 2, CVT_95_addRegOperands, 1, CVT_Done },
265
  // Convert__Reg1_1__Reg1_0
266
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
267
  // Convert__Reg1_1__CGImm1_0
268
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
269
  // Convert__Reg1_1__Imm1_0
270
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
271
  // Convert__Reg1_1__IndReg1_0
272
  { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done },
273
  // Convert__Reg1_1__Mem2_0
274
  { CVT_95_Reg, 2, CVT_95_addMemOperands, 1, CVT_Done },
275
  // Convert__Reg1_1__PostIndReg1_0
276
  { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Done },
277
  // Convert__Reg1_0
278
  { CVT_95_Reg, 1, CVT_Done },
279
  // Convert__Imm1_0
280
  { CVT_95_addImmOperands, 1, CVT_Done },
281
  // Convert__Mem2_0
282
  { CVT_95_addMemOperands, 1, CVT_Done },
283
  // Convert__IndReg1_0
284
  { CVT_95_addRegOperands, 1, CVT_Done },
285
  // Convert__PostIndReg1_0
286
  { CVT_95_addRegOperands, 1, CVT_Done },
287
  // Convert__Reg1_0__imm_95_0
288
  { CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
289
  // Convert__regSR__Tie0_1_1__imm_95_1
290
  { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_1, 0, CVT_Done },
291
  // Convert__regSR__Tie0_1_1__imm_95_4
292
  { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_4, 0, CVT_Done },
293
  // Convert__regSR__Tie0_1_1__imm_95_2
294
  { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_2, 0, CVT_Done },
295
  // Convert__Reg1_0__Tie0_1_1__imm_95_1
296
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_1, 0, CVT_Done },
297
  // Convert__Mem2_0__imm_95_1
298
  { CVT_95_addMemOperands, 1, CVT_imm_95_1, 0, CVT_Done },
299
  // Convert__Reg1_0__Tie0_1_1__imm_95_2
300
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95_2, 0, CVT_Done },
301
  // Convert__Mem2_0__imm_95_2
302
  { CVT_95_addMemOperands, 1, CVT_imm_95_2, 0, CVT_Done },
303
  // Convert__regSR__Tie0_1_1__imm_95_8
304
  { CVT_regSR, 0, CVT_Tied, Tie0_1_1, CVT_imm_95_8, 0, CVT_Done },
305
  // Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1
306
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_imm_95__MINUS_1, 0, CVT_Done },
307
  // Convert__Mem2_0__imm_95__MINUS_1
308
  { CVT_95_addMemOperands, 1, CVT_imm_95__MINUS_1, 0, CVT_Done },
309
  // Convert__Imm1_1__Imm1_0
310
  { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
311
  // Convert__Reg1_1__PostIndReg1_0__Tie1_1_1
312
  { CVT_95_Reg, 2, CVT_95_addRegOperands, 1, CVT_Tied, Tie1_1_1, CVT_Done },
313
  // Convert__regCG__imm_95_0
314
  { CVT_regCG, 0, CVT_imm_95_0, 0, CVT_Done },
315
  // Convert__CGImm1_0
316
  { CVT_95_addImmOperands, 1, CVT_Done },
317
  // Convert_NoOperands
318
  { CVT_Done },
319
  // Convert__Reg1_0__Tie0_1_1__Reg1_0
320
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 1, CVT_Done },
321
  // Convert__Mem2_0__Mem2_0
322
  { CVT_95_addMemOperands, 1, CVT_95_addMemOperands, 1, CVT_Done },
323
  // Convert__Reg1_0__Tie0_1_1
324
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
325
};
326
327
void MSP430AsmParser::
328
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
329
0
                const OperandVector &Operands) {
330
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
331
0
  const uint8_t *Converter = ConversionTable[Kind];
332
0
  unsigned OpIdx;
333
0
  Inst.setOpcode(Opcode);
334
0
  for (const uint8_t *p = Converter; *p; p += 2) {
335
0
    OpIdx = *(p + 1);
336
0
    switch (*p) {
337
0
    default: llvm_unreachable("invalid conversion entry!");
338
0
    case CVT_Reg:
339
0
      static_cast<MSP430Operand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
340
0
      break;
341
0
    case CVT_Tied: {
342
0
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
343
0
                              std::begin(TiedAsmOperandTable)) &&
344
0
             "Tied operand not found");
345
0
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
346
0
      if (TiedResOpnd != (uint8_t)-1)
347
0
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
348
0
      break;
349
0
    }
350
0
    case CVT_95_Reg:
351
0
      static_cast<MSP430Operand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
352
0
      break;
353
0
    case CVT_imm_95_0:
354
0
      Inst.addOperand(MCOperand::createImm(0));
355
0
      break;
356
0
    case CVT_95_addMemOperands:
357
0
      static_cast<MSP430Operand &>(*Operands[OpIdx]).addMemOperands(Inst, 2);
358
0
      break;
359
0
    case CVT_95_addImmOperands:
360
0
      static_cast<MSP430Operand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
361
0
      break;
362
0
    case CVT_95_addRegOperands:
363
0
      static_cast<MSP430Operand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
364
0
      break;
365
0
    case CVT_regSR:
366
0
      Inst.addOperand(MCOperand::createReg(MSP430::SR));
367
0
      break;
368
0
    case CVT_imm_95_1:
369
0
      Inst.addOperand(MCOperand::createImm(1));
370
0
      break;
371
0
    case CVT_imm_95_4:
372
0
      Inst.addOperand(MCOperand::createImm(4));
373
0
      break;
374
0
    case CVT_imm_95_2:
375
0
      Inst.addOperand(MCOperand::createImm(2));
376
0
      break;
377
0
    case CVT_imm_95_8:
378
0
      Inst.addOperand(MCOperand::createImm(8));
379
0
      break;
380
0
    case CVT_imm_95__MINUS_1:
381
0
      Inst.addOperand(MCOperand::createImm(-1));
382
0
      break;
383
0
    case CVT_regCG:
384
0
      Inst.addOperand(MCOperand::createReg(MSP430::CG));
385
0
      break;
386
0
    }
387
0
  }
388
0
}
389
390
void MSP430AsmParser::
391
convertToMapAndConstraints(unsigned Kind,
392
0
                           const OperandVector &Operands) {
393
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
394
0
  unsigned NumMCOperands = 0;
395
0
  const uint8_t *Converter = ConversionTable[Kind];
396
0
  for (const uint8_t *p = Converter; *p; p += 2) {
397
0
    switch (*p) {
398
0
    default: llvm_unreachable("invalid conversion entry!");
399
0
    case CVT_Reg:
400
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
401
0
      Operands[*(p + 1)]->setConstraint("r");
402
0
      ++NumMCOperands;
403
0
      break;
404
0
    case CVT_Tied:
405
0
      ++NumMCOperands;
406
0
      break;
407
0
    case CVT_95_Reg:
408
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
409
0
      Operands[*(p + 1)]->setConstraint("r");
410
0
      NumMCOperands += 1;
411
0
      break;
412
0
    case CVT_imm_95_0:
413
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
414
0
      Operands[*(p + 1)]->setConstraint("");
415
0
      ++NumMCOperands;
416
0
      break;
417
0
    case CVT_95_addMemOperands:
418
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
419
0
      Operands[*(p + 1)]->setConstraint("m");
420
0
      NumMCOperands += 2;
421
0
      break;
422
0
    case CVT_95_addImmOperands:
423
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
424
0
      Operands[*(p + 1)]->setConstraint("m");
425
0
      NumMCOperands += 1;
426
0
      break;
427
0
    case CVT_95_addRegOperands:
428
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
429
0
      Operands[*(p + 1)]->setConstraint("m");
430
0
      NumMCOperands += 1;
431
0
      break;
432
0
    case CVT_regSR:
433
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
434
0
      Operands[*(p + 1)]->setConstraint("m");
435
0
      ++NumMCOperands;
436
0
      break;
437
0
    case CVT_imm_95_1:
438
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
439
0
      Operands[*(p + 1)]->setConstraint("");
440
0
      ++NumMCOperands;
441
0
      break;
442
0
    case CVT_imm_95_4:
443
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
444
0
      Operands[*(p + 1)]->setConstraint("");
445
0
      ++NumMCOperands;
446
0
      break;
447
0
    case CVT_imm_95_2:
448
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
449
0
      Operands[*(p + 1)]->setConstraint("");
450
0
      ++NumMCOperands;
451
0
      break;
452
0
    case CVT_imm_95_8:
453
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
454
0
      Operands[*(p + 1)]->setConstraint("");
455
0
      ++NumMCOperands;
456
0
      break;
457
0
    case CVT_imm_95__MINUS_1:
458
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
459
0
      Operands[*(p + 1)]->setConstraint("");
460
0
      ++NumMCOperands;
461
0
      break;
462
0
    case CVT_regCG:
463
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
464
0
      Operands[*(p + 1)]->setConstraint("m");
465
0
      ++NumMCOperands;
466
0
      break;
467
0
    }
468
0
  }
469
0
}
470
471
namespace {
472
473
/// MatchClassKind - The kinds of classes which participate in
474
/// instruction matching.
475
enum MatchClassKind {
476
  InvalidMatchClass = 0,
477
  OptionalMatchClass = 1,
478
  MCK_LAST_TOKEN = OptionalMatchClass,
479
  MCK_GR16, // register class 'GR16'
480
  MCK_GR8, // register class 'GR8'
481
  MCK_LAST_REGISTER = MCK_GR8,
482
  MCK_CGImm, // user defined class 'CGImmAsmOperand'
483
  MCK_Imm, // user defined class 'ImmAsmOperand'
484
  MCK_IndReg, // user defined class 'IndRegAsmOperand'
485
  MCK_Mem, // user defined class 'MemAsmOperand'
486
  MCK_PostIndReg, // user defined class 'PostIndRegAsmOperand'
487
  NumMatchClassKinds
488
};
489
490
} // end anonymous namespace
491
492
0
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
493
0
  return MCTargetAsmParser::Match_InvalidOperand;
494
0
}
495
496
0
static MatchClassKind matchTokenString(StringRef Name) {
497
0
  return InvalidMatchClass;
498
0
}
499
500
/// isSubclass - Compute whether \p A is a subclass of \p B.
501
0
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
502
0
  if (A == B)
503
0
    return true;
504
505
0
  return false;
506
0
}
507
508
0
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
509
0
  MSP430Operand &Operand = (MSP430Operand &)GOp;
510
0
  if (Kind == InvalidMatchClass)
511
0
    return MCTargetAsmParser::Match_InvalidOperand;
512
513
0
  if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
514
0
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
515
0
             MCTargetAsmParser::Match_Success :
516
0
             MCTargetAsmParser::Match_InvalidOperand;
517
518
0
  switch (Kind) {
519
0
  default: break;
520
  // 'CGImm' class
521
0
  case MCK_CGImm: {
522
0
    DiagnosticPredicate DP(Operand.isCGImm());
523
0
    if (DP.isMatch())
524
0
      return MCTargetAsmParser::Match_Success;
525
0
    break;
526
0
    }
527
  // 'Imm' class
528
0
  case MCK_Imm: {
529
0
    DiagnosticPredicate DP(Operand.isImm());
530
0
    if (DP.isMatch())
531
0
      return MCTargetAsmParser::Match_Success;
532
0
    break;
533
0
    }
534
  // 'IndReg' class
535
0
  case MCK_IndReg: {
536
0
    DiagnosticPredicate DP(Operand.isIndReg());
537
0
    if (DP.isMatch())
538
0
      return MCTargetAsmParser::Match_Success;
539
0
    break;
540
0
    }
541
  // 'Mem' class
542
0
  case MCK_Mem: {
543
0
    DiagnosticPredicate DP(Operand.isMem());
544
0
    if (DP.isMatch())
545
0
      return MCTargetAsmParser::Match_Success;
546
0
    break;
547
0
    }
548
  // 'PostIndReg' class
549
0
  case MCK_PostIndReg: {
550
0
    DiagnosticPredicate DP(Operand.isPostIndReg());
551
0
    if (DP.isMatch())
552
0
      return MCTargetAsmParser::Match_Success;
553
0
    break;
554
0
    }
555
0
  } // end switch (Kind)
556
557
0
  if (Operand.isReg()) {
558
0
    MatchClassKind OpKind;
559
0
    switch (Operand.getReg()) {
560
0
    default: OpKind = InvalidMatchClass; break;
561
0
    case MSP430::PCB: OpKind = MCK_GR8; break;
562
0
    case MSP430::SPB: OpKind = MCK_GR8; break;
563
0
    case MSP430::SRB: OpKind = MCK_GR8; break;
564
0
    case MSP430::CGB: OpKind = MCK_GR8; break;
565
0
    case MSP430::R4B: OpKind = MCK_GR8; break;
566
0
    case MSP430::R5B: OpKind = MCK_GR8; break;
567
0
    case MSP430::R6B: OpKind = MCK_GR8; break;
568
0
    case MSP430::R7B: OpKind = MCK_GR8; break;
569
0
    case MSP430::R8B: OpKind = MCK_GR8; break;
570
0
    case MSP430::R9B: OpKind = MCK_GR8; break;
571
0
    case MSP430::R10B: OpKind = MCK_GR8; break;
572
0
    case MSP430::R11B: OpKind = MCK_GR8; break;
573
0
    case MSP430::R12B: OpKind = MCK_GR8; break;
574
0
    case MSP430::R13B: OpKind = MCK_GR8; break;
575
0
    case MSP430::R14B: OpKind = MCK_GR8; break;
576
0
    case MSP430::R15B: OpKind = MCK_GR8; break;
577
0
    case MSP430::PC: OpKind = MCK_GR16; break;
578
0
    case MSP430::SP: OpKind = MCK_GR16; break;
579
0
    case MSP430::SR: OpKind = MCK_GR16; break;
580
0
    case MSP430::CG: OpKind = MCK_GR16; break;
581
0
    case MSP430::R4: OpKind = MCK_GR16; break;
582
0
    case MSP430::R5: OpKind = MCK_GR16; break;
583
0
    case MSP430::R6: OpKind = MCK_GR16; break;
584
0
    case MSP430::R7: OpKind = MCK_GR16; break;
585
0
    case MSP430::R8: OpKind = MCK_GR16; break;
586
0
    case MSP430::R9: OpKind = MCK_GR16; break;
587
0
    case MSP430::R10: OpKind = MCK_GR16; break;
588
0
    case MSP430::R11: OpKind = MCK_GR16; break;
589
0
    case MSP430::R12: OpKind = MCK_GR16; break;
590
0
    case MSP430::R13: OpKind = MCK_GR16; break;
591
0
    case MSP430::R14: OpKind = MCK_GR16; break;
592
0
    case MSP430::R15: OpKind = MCK_GR16; break;
593
0
    }
594
0
    return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
595
0
                                      getDiagKindFromRegisterClass(Kind);
596
0
  }
597
598
0
  if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
599
0
    return getDiagKindFromRegisterClass(Kind);
600
601
0
  return MCTargetAsmParser::Match_InvalidOperand;
602
0
}
603
604
#ifndef NDEBUG
605
0
const char *getMatchClassName(MatchClassKind Kind) {
606
0
  switch (Kind) {
607
0
  case InvalidMatchClass: return "InvalidMatchClass";
608
0
  case OptionalMatchClass: return "OptionalMatchClass";
609
0
  case MCK_GR16: return "MCK_GR16";
610
0
  case MCK_GR8: return "MCK_GR8";
611
0
  case MCK_CGImm: return "MCK_CGImm";
612
0
  case MCK_Imm: return "MCK_Imm";
613
0
  case MCK_IndReg: return "MCK_IndReg";
614
0
  case MCK_Mem: return "MCK_Mem";
615
0
  case MCK_PostIndReg: return "MCK_PostIndReg";
616
0
  case NumMatchClassKinds: return "NumMatchClassKinds";
617
0
  }
618
0
  llvm_unreachable("unhandled MatchClassKind!");
619
0
}
620
621
#endif // NDEBUG
622
FeatureBitset MSP430AsmParser::
623
0
ComputeAvailableFeatures(const FeatureBitset &FB) const {
624
0
  FeatureBitset Features;
625
0
  return Features;
626
0
}
627
628
static bool checkAsmTiedOperandConstraints(const MSP430AsmParser&AsmParser,
629
                               unsigned Kind,
630
                               const OperandVector &Operands,
631
0
                               uint64_t &ErrorInfo) {
632
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
633
0
  const uint8_t *Converter = ConversionTable[Kind];
634
0
  for (const uint8_t *p = Converter; *p; p += 2) {
635
0
    switch (*p) {
636
0
    case CVT_Tied: {
637
0
      unsigned OpIdx = *(p + 1);
638
0
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
639
0
                              std::begin(TiedAsmOperandTable)) &&
640
0
             "Tied operand not found");
641
0
      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
642
0
      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
643
0
      if (OpndNum1 != OpndNum2) {
644
0
        auto &SrcOp1 = Operands[OpndNum1];
645
0
        auto &SrcOp2 = Operands[OpndNum2];
646
0
        if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
647
0
          ErrorInfo = OpndNum2;
648
0
          return false;
649
0
        }
650
0
      }
651
0
      break;
652
0
    }
653
0
    default:
654
0
      break;
655
0
    }
656
0
  }
657
0
  return true;
658
0
}
659
660
static const char MnemonicTable[] =
661
    "\003adc\005adc.b\003add\005add.b\004addc\006addc.b\003and\005and.b\003b"
662
    "ic\005bic.b\003bis\005bis.b\003bit\005bit.b\002br\004call\003clr\005clr"
663
    ".b\004clrc\004clrn\004clrz\003cmp\005cmp.b\004dadc\006dadc.b\004dadd\006"
664
    "dadd.b\003dec\005dec.b\004decd\006decd.b\004dint\004eint\003inc\005inc."
665
    "b\004incd\006incd.b\003inv\005inv.b\001j\003jmp\003mov\005mov.b\003nop\003"
666
    "pop\004push\006push.b\003ret\004reti\003rla\005rla.b\003rlc\005rlc.b\003"
667
    "rra\005rra.b\003rrc\005rrc.b\003sbc\005sbc.b\004setc\004setn\004setz\003"
668
    "sub\005sub.b\004subc\006subc.b\004swpb\003sxt\003tst\005tst.b\003xor\005"
669
    "xor.b";
670
671
// Feature bitsets.
672
enum : uint8_t {
673
  AMFBS_None,
674
};
675
676
static constexpr FeatureBitset FeatureBitsets[] = {
677
  {}, // AMFBS_None
678
};
679
680
namespace {
681
  struct MatchEntry {
682
    uint16_t Mnemonic;
683
    uint16_t Opcode;
684
    uint8_t ConvertFn;
685
    uint8_t RequiredFeaturesIdx;
686
    uint8_t Classes[2];
687
0
    StringRef getMnemonic() const {
688
0
      return StringRef(MnemonicTable + Mnemonic + 1,
689
0
                       MnemonicTable[Mnemonic]);
690
0
    }
691
  };
692
693
  // Predicate for searching for an opcode.
694
  struct LessOpcode {
695
0
    bool operator()(const MatchEntry &LHS, StringRef RHS) {
696
0
      return LHS.getMnemonic() < RHS;
697
0
    }
698
0
    bool operator()(StringRef LHS, const MatchEntry &RHS) {
699
0
      return LHS < RHS.getMnemonic();
700
0
    }
701
0
    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
702
0
      return LHS.getMnemonic() < RHS.getMnemonic();
703
0
    }
704
  };
705
} // end anonymous namespace
706
707
static const MatchEntry MatchTable0[] = {
708
  { 0 /* adc */, MSP430::ADDC16rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR16 }, },
709
  { 0 /* adc */, MSP430::ADDC16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
710
  { 4 /* adc.b */, MSP430::ADDC8rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR8 }, },
711
  { 4 /* adc.b */, MSP430::ADDC8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
712
  { 10 /* add */, MSP430::ADD16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
713
  { 10 /* add */, MSP430::ADD16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
714
  { 10 /* add */, MSP430::ADD16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
715
  { 10 /* add */, MSP430::ADD16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
716
  { 10 /* add */, MSP430::ADD16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
717
  { 10 /* add */, MSP430::ADD16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
718
  { 10 /* add */, MSP430::ADD16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
719
  { 10 /* add */, MSP430::ADD16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
720
  { 10 /* add */, MSP430::ADD16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
721
  { 10 /* add */, MSP430::ADD16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
722
  { 10 /* add */, MSP430::ADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
723
  { 10 /* add */, MSP430::ADD16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
724
  { 14 /* add.b */, MSP430::ADD8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
725
  { 14 /* add.b */, MSP430::ADD8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
726
  { 14 /* add.b */, MSP430::ADD8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
727
  { 14 /* add.b */, MSP430::ADD8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
728
  { 14 /* add.b */, MSP430::ADD8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
729
  { 14 /* add.b */, MSP430::ADD8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
730
  { 14 /* add.b */, MSP430::ADD8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
731
  { 14 /* add.b */, MSP430::ADD8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
732
  { 14 /* add.b */, MSP430::ADD8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
733
  { 14 /* add.b */, MSP430::ADD8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
734
  { 14 /* add.b */, MSP430::ADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
735
  { 14 /* add.b */, MSP430::ADD8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
736
  { 20 /* addc */, MSP430::ADDC16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
737
  { 20 /* addc */, MSP430::ADDC16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
738
  { 20 /* addc */, MSP430::ADDC16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
739
  { 20 /* addc */, MSP430::ADDC16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
740
  { 20 /* addc */, MSP430::ADDC16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
741
  { 20 /* addc */, MSP430::ADDC16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
742
  { 20 /* addc */, MSP430::ADDC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
743
  { 20 /* addc */, MSP430::ADDC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
744
  { 20 /* addc */, MSP430::ADDC16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
745
  { 20 /* addc */, MSP430::ADDC16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
746
  { 20 /* addc */, MSP430::ADDC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
747
  { 20 /* addc */, MSP430::ADDC16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
748
  { 25 /* addc.b */, MSP430::ADDC8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
749
  { 25 /* addc.b */, MSP430::ADDC8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
750
  { 25 /* addc.b */, MSP430::ADDC8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
751
  { 25 /* addc.b */, MSP430::ADDC8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
752
  { 25 /* addc.b */, MSP430::ADDC8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
753
  { 25 /* addc.b */, MSP430::ADDC8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
754
  { 25 /* addc.b */, MSP430::ADDC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
755
  { 25 /* addc.b */, MSP430::ADDC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
756
  { 25 /* addc.b */, MSP430::ADDC8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
757
  { 25 /* addc.b */, MSP430::ADDC8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
758
  { 25 /* addc.b */, MSP430::ADDC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
759
  { 25 /* addc.b */, MSP430::ADDC8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
760
  { 32 /* and */, MSP430::AND16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
761
  { 32 /* and */, MSP430::AND16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
762
  { 32 /* and */, MSP430::AND16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
763
  { 32 /* and */, MSP430::AND16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
764
  { 32 /* and */, MSP430::AND16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
765
  { 32 /* and */, MSP430::AND16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
766
  { 32 /* and */, MSP430::AND16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
767
  { 32 /* and */, MSP430::AND16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
768
  { 32 /* and */, MSP430::AND16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
769
  { 32 /* and */, MSP430::AND16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
770
  { 32 /* and */, MSP430::AND16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
771
  { 32 /* and */, MSP430::AND16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
772
  { 36 /* and.b */, MSP430::AND8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
773
  { 36 /* and.b */, MSP430::AND8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
774
  { 36 /* and.b */, MSP430::AND8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
775
  { 36 /* and.b */, MSP430::AND8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
776
  { 36 /* and.b */, MSP430::AND8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
777
  { 36 /* and.b */, MSP430::AND8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
778
  { 36 /* and.b */, MSP430::AND8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
779
  { 36 /* and.b */, MSP430::AND8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
780
  { 36 /* and.b */, MSP430::AND8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
781
  { 36 /* and.b */, MSP430::AND8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
782
  { 36 /* and.b */, MSP430::AND8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
783
  { 36 /* and.b */, MSP430::AND8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
784
  { 42 /* bic */, MSP430::BIC16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
785
  { 42 /* bic */, MSP430::BIC16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
786
  { 42 /* bic */, MSP430::BIC16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
787
  { 42 /* bic */, MSP430::BIC16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
788
  { 42 /* bic */, MSP430::BIC16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
789
  { 42 /* bic */, MSP430::BIC16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
790
  { 42 /* bic */, MSP430::BIC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
791
  { 42 /* bic */, MSP430::BIC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
792
  { 42 /* bic */, MSP430::BIC16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
793
  { 42 /* bic */, MSP430::BIC16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
794
  { 42 /* bic */, MSP430::BIC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
795
  { 42 /* bic */, MSP430::BIC16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
796
  { 46 /* bic.b */, MSP430::BIC8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
797
  { 46 /* bic.b */, MSP430::BIC8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
798
  { 46 /* bic.b */, MSP430::BIC8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
799
  { 46 /* bic.b */, MSP430::BIC8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
800
  { 46 /* bic.b */, MSP430::BIC8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
801
  { 46 /* bic.b */, MSP430::BIC8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
802
  { 46 /* bic.b */, MSP430::BIC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
803
  { 46 /* bic.b */, MSP430::BIC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
804
  { 46 /* bic.b */, MSP430::BIC8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
805
  { 46 /* bic.b */, MSP430::BIC8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
806
  { 46 /* bic.b */, MSP430::BIC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
807
  { 46 /* bic.b */, MSP430::BIC8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
808
  { 52 /* bis */, MSP430::BIS16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
809
  { 52 /* bis */, MSP430::BIS16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
810
  { 52 /* bis */, MSP430::BIS16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
811
  { 52 /* bis */, MSP430::BIS16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
812
  { 52 /* bis */, MSP430::BIS16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
813
  { 52 /* bis */, MSP430::BIS16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
814
  { 52 /* bis */, MSP430::BIS16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
815
  { 52 /* bis */, MSP430::BIS16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
816
  { 52 /* bis */, MSP430::BIS16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
817
  { 52 /* bis */, MSP430::BIS16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
818
  { 52 /* bis */, MSP430::BIS16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
819
  { 52 /* bis */, MSP430::BIS16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
820
  { 56 /* bis.b */, MSP430::BIS8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
821
  { 56 /* bis.b */, MSP430::BIS8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
822
  { 56 /* bis.b */, MSP430::BIS8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
823
  { 56 /* bis.b */, MSP430::BIS8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
824
  { 56 /* bis.b */, MSP430::BIS8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
825
  { 56 /* bis.b */, MSP430::BIS8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
826
  { 56 /* bis.b */, MSP430::BIS8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
827
  { 56 /* bis.b */, MSP430::BIS8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
828
  { 56 /* bis.b */, MSP430::BIS8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
829
  { 56 /* bis.b */, MSP430::BIS8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
830
  { 56 /* bis.b */, MSP430::BIS8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
831
  { 56 /* bis.b */, MSP430::BIS8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
832
  { 62 /* bit */, MSP430::BIT16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
833
  { 62 /* bit */, MSP430::BIT16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
834
  { 62 /* bit */, MSP430::BIT16rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
835
  { 62 /* bit */, MSP430::BIT16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
836
  { 62 /* bit */, MSP430::BIT16ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
837
  { 62 /* bit */, MSP430::BIT16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
838
  { 62 /* bit */, MSP430::BIT16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
839
  { 62 /* bit */, MSP430::BIT16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
840
  { 62 /* bit */, MSP430::BIT16rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
841
  { 62 /* bit */, MSP430::BIT16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
842
  { 62 /* bit */, MSP430::BIT16rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
843
  { 62 /* bit */, MSP430::BIT16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
844
  { 66 /* bit.b */, MSP430::BIT8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
845
  { 66 /* bit.b */, MSP430::BIT8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
846
  { 66 /* bit.b */, MSP430::BIT8rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
847
  { 66 /* bit.b */, MSP430::BIT8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
848
  { 66 /* bit.b */, MSP430::BIT8ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
849
  { 66 /* bit.b */, MSP430::BIT8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
850
  { 66 /* bit.b */, MSP430::BIT8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
851
  { 66 /* bit.b */, MSP430::BIT8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
852
  { 66 /* bit.b */, MSP430::BIT8rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
853
  { 66 /* bit.b */, MSP430::BIT8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
854
  { 66 /* bit.b */, MSP430::BIT8rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
855
  { 66 /* bit.b */, MSP430::BIT8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
856
  { 72 /* br */, MSP430::Br, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
857
  { 72 /* br */, MSP430::Bi, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
858
  { 72 /* br */, MSP430::Bm, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
859
  { 75 /* call */, MSP430::CALLr, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
860
  { 75 /* call */, MSP430::CALLi, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
861
  { 75 /* call */, MSP430::CALLn, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
862
  { 75 /* call */, MSP430::CALLm, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
863
  { 75 /* call */, MSP430::CALLp, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
864
  { 80 /* clr */, MSP430::MOV16rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR16 }, },
865
  { 80 /* clr */, MSP430::MOV16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
866
  { 84 /* clr.b */, MSP430::MOV8rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR8 }, },
867
  { 84 /* clr.b */, MSP430::MOV8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
868
  { 90 /* clrc */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_1, AMFBS_None, {  }, },
869
  { 95 /* clrn */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_4, AMFBS_None, {  }, },
870
  { 100 /* clrz */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_2, AMFBS_None, {  }, },
871
  { 105 /* cmp */, MSP430::CMP16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
872
  { 105 /* cmp */, MSP430::CMP16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
873
  { 105 /* cmp */, MSP430::CMP16rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
874
  { 105 /* cmp */, MSP430::CMP16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
875
  { 105 /* cmp */, MSP430::CMP16ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
876
  { 105 /* cmp */, MSP430::CMP16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
877
  { 105 /* cmp */, MSP430::CMP16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
878
  { 105 /* cmp */, MSP430::CMP16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
879
  { 105 /* cmp */, MSP430::CMP16rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
880
  { 105 /* cmp */, MSP430::CMP16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
881
  { 105 /* cmp */, MSP430::CMP16rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
882
  { 105 /* cmp */, MSP430::CMP16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
883
  { 109 /* cmp.b */, MSP430::CMP8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
884
  { 109 /* cmp.b */, MSP430::CMP8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
885
  { 109 /* cmp.b */, MSP430::CMP8rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
886
  { 109 /* cmp.b */, MSP430::CMP8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
887
  { 109 /* cmp.b */, MSP430::CMP8ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
888
  { 109 /* cmp.b */, MSP430::CMP8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
889
  { 109 /* cmp.b */, MSP430::CMP8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
890
  { 109 /* cmp.b */, MSP430::CMP8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
891
  { 109 /* cmp.b */, MSP430::CMP8rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
892
  { 109 /* cmp.b */, MSP430::CMP8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
893
  { 109 /* cmp.b */, MSP430::CMP8rp, Convert__Reg1_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
894
  { 109 /* cmp.b */, MSP430::CMP8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
895
  { 115 /* dadc */, MSP430::DADD16rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR16 }, },
896
  { 115 /* dadc */, MSP430::DADD16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
897
  { 120 /* dadc.b */, MSP430::DADD8rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR8 }, },
898
  { 120 /* dadc.b */, MSP430::DADD8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
899
  { 127 /* dadd */, MSP430::DADD16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
900
  { 127 /* dadd */, MSP430::DADD16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
901
  { 127 /* dadd */, MSP430::DADD16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
902
  { 127 /* dadd */, MSP430::DADD16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
903
  { 127 /* dadd */, MSP430::DADD16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
904
  { 127 /* dadd */, MSP430::DADD16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
905
  { 127 /* dadd */, MSP430::DADD16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
906
  { 127 /* dadd */, MSP430::DADD16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
907
  { 127 /* dadd */, MSP430::DADD16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
908
  { 127 /* dadd */, MSP430::DADD16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
909
  { 127 /* dadd */, MSP430::DADD16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
910
  { 127 /* dadd */, MSP430::DADD16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
911
  { 132 /* dadd.b */, MSP430::DADD8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
912
  { 132 /* dadd.b */, MSP430::DADD8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
913
  { 132 /* dadd.b */, MSP430::DADD8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
914
  { 132 /* dadd.b */, MSP430::DADD8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
915
  { 132 /* dadd.b */, MSP430::DADD8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
916
  { 132 /* dadd.b */, MSP430::DADD8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
917
  { 132 /* dadd.b */, MSP430::DADD8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
918
  { 132 /* dadd.b */, MSP430::DADD8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
919
  { 132 /* dadd.b */, MSP430::DADD8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
920
  { 132 /* dadd.b */, MSP430::DADD8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
921
  { 132 /* dadd.b */, MSP430::DADD8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
922
  { 132 /* dadd.b */, MSP430::DADD8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
923
  { 139 /* dec */, MSP430::SUB16rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR16 }, },
924
  { 139 /* dec */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
925
  { 143 /* dec.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR8 }, },
926
  { 143 /* dec.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
927
  { 149 /* decd */, MSP430::SUB16rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR16 }, },
928
  { 149 /* decd */, MSP430::SUB16mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
929
  { 154 /* decd.b */, MSP430::SUB8rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR8 }, },
930
  { 154 /* decd.b */, MSP430::SUB8mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
931
  { 161 /* dint */, MSP430::BIC16rc, Convert__regSR__Tie0_1_1__imm_95_8, AMFBS_None, {  }, },
932
  { 166 /* eint */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_8, AMFBS_None, {  }, },
933
  { 171 /* inc */, MSP430::ADD16rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR16 }, },
934
  { 171 /* inc */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
935
  { 175 /* inc.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0_1_1__imm_95_1, AMFBS_None, { MCK_GR8 }, },
936
  { 175 /* inc.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_1, AMFBS_None, { MCK_Mem }, },
937
  { 181 /* incd */, MSP430::ADD16rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR16 }, },
938
  { 181 /* incd */, MSP430::ADD16mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
939
  { 186 /* incd.b */, MSP430::ADD8rc, Convert__Reg1_0__Tie0_1_1__imm_95_2, AMFBS_None, { MCK_GR8 }, },
940
  { 186 /* incd.b */, MSP430::ADD8mc, Convert__Mem2_0__imm_95_2, AMFBS_None, { MCK_Mem }, },
941
  { 193 /* inv */, MSP430::XOR16rc, Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GR16 }, },
942
  { 193 /* inv */, MSP430::XOR16mc, Convert__Mem2_0__imm_95__MINUS_1, AMFBS_None, { MCK_Mem }, },
943
  { 197 /* inv.b */, MSP430::XOR8rc, Convert__Reg1_0__Tie0_1_1__imm_95__MINUS_1, AMFBS_None, { MCK_GR8 }, },
944
  { 197 /* inv.b */, MSP430::XOR8mc, Convert__Mem2_0__imm_95__MINUS_1, AMFBS_None, { MCK_Mem }, },
945
  { 203 /* j */, MSP430::JCC, Convert__Imm1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Imm }, },
946
  { 205 /* jmp */, MSP430::JMP, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
947
  { 209 /* mov */, MSP430::MOV16rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
948
  { 209 /* mov */, MSP430::MOV16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
949
  { 209 /* mov */, MSP430::MOV16rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
950
  { 209 /* mov */, MSP430::MOV16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
951
  { 209 /* mov */, MSP430::MOV16ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
952
  { 209 /* mov */, MSP430::MOV16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
953
  { 209 /* mov */, MSP430::MOV16rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
954
  { 209 /* mov */, MSP430::MOV16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
955
  { 209 /* mov */, MSP430::MOV16rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
956
  { 209 /* mov */, MSP430::MOV16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
957
  { 209 /* mov */, MSP430::MOV16rp, Convert__Reg1_1__PostIndReg1_0__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
958
  { 213 /* mov.b */, MSP430::MOV8rr, Convert__Reg1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
959
  { 213 /* mov.b */, MSP430::MOV8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
960
  { 213 /* mov.b */, MSP430::MOV8rc, Convert__Reg1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
961
  { 213 /* mov.b */, MSP430::MOV8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
962
  { 213 /* mov.b */, MSP430::MOV8ri, Convert__Reg1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
963
  { 213 /* mov.b */, MSP430::MOV8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
964
  { 213 /* mov.b */, MSP430::MOV8rn, Convert__Reg1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
965
  { 213 /* mov.b */, MSP430::MOV8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
966
  { 213 /* mov.b */, MSP430::MOV8rm, Convert__Reg1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
967
  { 213 /* mov.b */, MSP430::MOV8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
968
  { 213 /* mov.b */, MSP430::MOV8rp, Convert__Reg1_1__PostIndReg1_0__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
969
  { 219 /* nop */, MSP430::MOV16rc, Convert__regCG__imm_95_0, AMFBS_None, {  }, },
970
  { 223 /* pop */, MSP430::POP16r, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
971
  { 227 /* push */, MSP430::PUSH16r, Convert__Reg1_0, AMFBS_None, { MCK_GR16 }, },
972
  { 227 /* push */, MSP430::PUSH16c, Convert__CGImm1_0, AMFBS_None, { MCK_CGImm }, },
973
  { 227 /* push */, MSP430::PUSH16i, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, },
974
  { 232 /* push.b */, MSP430::PUSH8r, Convert__Reg1_0, AMFBS_None, { MCK_GR8 }, },
975
  { 239 /* ret */, MSP430::RET, Convert_NoOperands, AMFBS_None, {  }, },
976
  { 243 /* reti */, MSP430::RETI, Convert_NoOperands, AMFBS_None, {  }, },
977
  { 248 /* rla */, MSP430::ADD16rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16 }, },
978
  { 248 /* rla */, MSP430::ADD16mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
979
  { 252 /* rla.b */, MSP430::ADD8rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8 }, },
980
  { 252 /* rla.b */, MSP430::ADD8mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
981
  { 258 /* rlc */, MSP430::ADDC16rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16 }, },
982
  { 258 /* rlc */, MSP430::ADDC16mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
983
  { 262 /* rlc.b */, MSP430::ADDC8rr, Convert__Reg1_0__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8 }, },
984
  { 262 /* rlc.b */, MSP430::ADDC8mm, Convert__Mem2_0__Mem2_0, AMFBS_None, { MCK_Mem }, },
985
  { 268 /* rra */, MSP430::RRA16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
986
  { 268 /* rra */, MSP430::RRA16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
987
  { 268 /* rra */, MSP430::RRA16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
988
  { 268 /* rra */, MSP430::RRA16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
989
  { 272 /* rra.b */, MSP430::RRA8r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR8 }, },
990
  { 272 /* rra.b */, MSP430::RRA8n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
991
  { 272 /* rra.b */, MSP430::RRA8m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
992
  { 272 /* rra.b */, MSP430::RRA8p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
993
  { 278 /* rrc */, MSP430::RRC16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
994
  { 278 /* rrc */, MSP430::RRC16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
995
  { 278 /* rrc */, MSP430::RRC16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
996
  { 278 /* rrc */, MSP430::RRC16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
997
  { 282 /* rrc.b */, MSP430::RRC8r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR8 }, },
998
  { 282 /* rrc.b */, MSP430::RRC8n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
999
  { 282 /* rrc.b */, MSP430::RRC8m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1000
  { 282 /* rrc.b */, MSP430::RRC8p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1001
  { 288 /* sbc */, MSP430::SUBC16rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR16 }, },
1002
  { 288 /* sbc */, MSP430::SUBC16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1003
  { 292 /* sbc.b */, MSP430::SUBC8rc, Convert__Reg1_0__Tie0_1_1__imm_95_0, AMFBS_None, { MCK_GR8 }, },
1004
  { 292 /* sbc.b */, MSP430::SUBC8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1005
  { 298 /* setc */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_1, AMFBS_None, {  }, },
1006
  { 303 /* setn */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_4, AMFBS_None, {  }, },
1007
  { 308 /* setz */, MSP430::BIS16rc, Convert__regSR__Tie0_1_1__imm_95_2, AMFBS_None, {  }, },
1008
  { 313 /* sub */, MSP430::SUB16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
1009
  { 313 /* sub */, MSP430::SUB16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
1010
  { 313 /* sub */, MSP430::SUB16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
1011
  { 313 /* sub */, MSP430::SUB16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1012
  { 313 /* sub */, MSP430::SUB16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
1013
  { 313 /* sub */, MSP430::SUB16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1014
  { 313 /* sub */, MSP430::SUB16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1015
  { 313 /* sub */, MSP430::SUB16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1016
  { 313 /* sub */, MSP430::SUB16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
1017
  { 313 /* sub */, MSP430::SUB16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1018
  { 313 /* sub */, MSP430::SUB16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
1019
  { 313 /* sub */, MSP430::SUB16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1020
  { 317 /* sub.b */, MSP430::SUB8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
1021
  { 317 /* sub.b */, MSP430::SUB8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
1022
  { 317 /* sub.b */, MSP430::SUB8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
1023
  { 317 /* sub.b */, MSP430::SUB8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1024
  { 317 /* sub.b */, MSP430::SUB8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
1025
  { 317 /* sub.b */, MSP430::SUB8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1026
  { 317 /* sub.b */, MSP430::SUB8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1027
  { 317 /* sub.b */, MSP430::SUB8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1028
  { 317 /* sub.b */, MSP430::SUB8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
1029
  { 317 /* sub.b */, MSP430::SUB8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1030
  { 317 /* sub.b */, MSP430::SUB8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
1031
  { 317 /* sub.b */, MSP430::SUB8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1032
  { 323 /* subc */, MSP430::SUBC16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
1033
  { 323 /* subc */, MSP430::SUBC16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
1034
  { 323 /* subc */, MSP430::SUBC16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
1035
  { 323 /* subc */, MSP430::SUBC16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1036
  { 323 /* subc */, MSP430::SUBC16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
1037
  { 323 /* subc */, MSP430::SUBC16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1038
  { 323 /* subc */, MSP430::SUBC16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1039
  { 323 /* subc */, MSP430::SUBC16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1040
  { 323 /* subc */, MSP430::SUBC16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
1041
  { 323 /* subc */, MSP430::SUBC16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1042
  { 323 /* subc */, MSP430::SUBC16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
1043
  { 323 /* subc */, MSP430::SUBC16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1044
  { 328 /* subc.b */, MSP430::SUBC8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
1045
  { 328 /* subc.b */, MSP430::SUBC8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
1046
  { 328 /* subc.b */, MSP430::SUBC8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
1047
  { 328 /* subc.b */, MSP430::SUBC8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1048
  { 328 /* subc.b */, MSP430::SUBC8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
1049
  { 328 /* subc.b */, MSP430::SUBC8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1050
  { 328 /* subc.b */, MSP430::SUBC8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1051
  { 328 /* subc.b */, MSP430::SUBC8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1052
  { 328 /* subc.b */, MSP430::SUBC8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
1053
  { 328 /* subc.b */, MSP430::SUBC8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1054
  { 328 /* subc.b */, MSP430::SUBC8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
1055
  { 328 /* subc.b */, MSP430::SUBC8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1056
  { 335 /* swpb */, MSP430::SWPB16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
1057
  { 335 /* swpb */, MSP430::SWPB16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1058
  { 335 /* swpb */, MSP430::SWPB16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1059
  { 335 /* swpb */, MSP430::SWPB16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1060
  { 340 /* sxt */, MSP430::SEXT16r, Convert__Reg1_0__Tie0_1_1, AMFBS_None, { MCK_GR16 }, },
1061
  { 340 /* sxt */, MSP430::SEXT16n, Convert__IndReg1_0, AMFBS_None, { MCK_IndReg }, },
1062
  { 340 /* sxt */, MSP430::SEXT16m, Convert__Mem2_0, AMFBS_None, { MCK_Mem }, },
1063
  { 340 /* sxt */, MSP430::SEXT16p, Convert__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg }, },
1064
  { 344 /* tst */, MSP430::CMP16rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR16 }, },
1065
  { 344 /* tst */, MSP430::CMP16mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1066
  { 348 /* tst.b */, MSP430::CMP8rc, Convert__Reg1_0__imm_95_0, AMFBS_None, { MCK_GR8 }, },
1067
  { 348 /* tst.b */, MSP430::CMP8mc, Convert__Mem2_0__imm_95_0, AMFBS_None, { MCK_Mem }, },
1068
  { 354 /* xor */, MSP430::XOR16rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_GR16 }, },
1069
  { 354 /* xor */, MSP430::XOR16mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR16, MCK_Mem }, },
1070
  { 354 /* xor */, MSP430::XOR16rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR16 }, },
1071
  { 354 /* xor */, MSP430::XOR16mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1072
  { 354 /* xor */, MSP430::XOR16ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR16 }, },
1073
  { 354 /* xor */, MSP430::XOR16mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1074
  { 354 /* xor */, MSP430::XOR16rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR16 }, },
1075
  { 354 /* xor */, MSP430::XOR16mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1076
  { 354 /* xor */, MSP430::XOR16rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR16 }, },
1077
  { 354 /* xor */, MSP430::XOR16mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1078
  { 354 /* xor */, MSP430::XOR16rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR16 }, },
1079
  { 354 /* xor */, MSP430::XOR16mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1080
  { 358 /* xor.b */, MSP430::XOR8rr, Convert__Reg1_1__Tie0_1_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_GR8 }, },
1081
  { 358 /* xor.b */, MSP430::XOR8mr, Convert__Mem2_1__Reg1_0, AMFBS_None, { MCK_GR8, MCK_Mem }, },
1082
  { 358 /* xor.b */, MSP430::XOR8rc, Convert__Reg1_1__Tie0_1_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_GR8 }, },
1083
  { 358 /* xor.b */, MSP430::XOR8mc, Convert__Mem2_1__CGImm1_0, AMFBS_None, { MCK_CGImm, MCK_Mem }, },
1084
  { 358 /* xor.b */, MSP430::XOR8ri, Convert__Reg1_1__Tie0_1_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_GR8 }, },
1085
  { 358 /* xor.b */, MSP430::XOR8mi, Convert__Mem2_1__Imm1_0, AMFBS_None, { MCK_Imm, MCK_Mem }, },
1086
  { 358 /* xor.b */, MSP430::XOR8rn, Convert__Reg1_1__Tie0_1_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_GR8 }, },
1087
  { 358 /* xor.b */, MSP430::XOR8mn, Convert__Mem2_1__IndReg1_0, AMFBS_None, { MCK_IndReg, MCK_Mem }, },
1088
  { 358 /* xor.b */, MSP430::XOR8rm, Convert__Reg1_1__Tie0_1_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_GR8 }, },
1089
  { 358 /* xor.b */, MSP430::XOR8mm, Convert__Mem2_1__Mem2_0, AMFBS_None, { MCK_Mem, MCK_Mem }, },
1090
  { 358 /* xor.b */, MSP430::XOR8rp, Convert__Reg1_1__PostIndReg1_0__Tie0_1_1__Tie1_1_1, AMFBS_None, { MCK_PostIndReg, MCK_GR8 }, },
1091
  { 358 /* xor.b */, MSP430::XOR8mp, Convert__Mem2_1__PostIndReg1_0, AMFBS_None, { MCK_PostIndReg, MCK_Mem }, },
1092
};
1093
1094
#include "llvm/Support/Debug.h"
1095
#include "llvm/Support/Format.h"
1096
1097
unsigned MSP430AsmParser::
1098
MatchInstructionImpl(const OperandVector &Operands,
1099
                     MCInst &Inst,
1100
                     uint64_t &ErrorInfo,
1101
                     FeatureBitset &MissingFeatures,
1102
0
                     bool matchingInlineAsm, unsigned VariantID) {
1103
  // Eliminate obvious mismatches.
1104
0
  if (Operands.size() > 3) {
1105
0
    ErrorInfo = 3;
1106
0
    return Match_InvalidOperand;
1107
0
  }
1108
1109
  // Get the current feature set.
1110
0
  const FeatureBitset &AvailableFeatures = getAvailableFeatures();
1111
1112
  // Get the instruction mnemonic, which is the first token.
1113
0
  StringRef Mnemonic = ((MSP430Operand &)*Operands[0]).getToken();
1114
1115
  // Some state to try to produce better error messages.
1116
0
  bool HadMatchOtherThanFeatures = false;
1117
0
  bool HadMatchOtherThanPredicate = false;
1118
0
  unsigned RetCode = Match_InvalidOperand;
1119
0
  MissingFeatures.set();
1120
  // Set ErrorInfo to the operand that mismatches if it is
1121
  // wrong for all instances of the instruction.
1122
0
  ErrorInfo = ~0ULL;
1123
  // Find the appropriate table for this asm variant.
1124
0
  const MatchEntry *Start, *End;
1125
0
  switch (VariantID) {
1126
0
  default: llvm_unreachable("invalid variant!");
1127
0
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1128
0
  }
1129
  // Search the table.
1130
0
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1131
1132
0
  DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
1133
0
  std::distance(MnemonicRange.first, MnemonicRange.second) <<
1134
0
  " encodings with mnemonic '" << Mnemonic << "'\n");
1135
1136
  // Return a more specific error code if no mnemonics match.
1137
0
  if (MnemonicRange.first == MnemonicRange.second)
1138
0
    return Match_MnemonicFail;
1139
1140
0
  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1141
0
       it != ie; ++it) {
1142
0
    const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
1143
0
    bool HasRequiredFeatures =
1144
0
      (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
1145
0
    DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
1146
0
                                          << MII.getName(it->Opcode) << "\n");
1147
    // equal_range guarantees that instruction mnemonic matches.
1148
0
    assert(Mnemonic == it->getMnemonic());
1149
0
    bool OperandsValid = true;
1150
0
    for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 2; ++FormalIdx) {
1151
0
      auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
1152
0
      DEBUG_WITH_TYPE("asm-matcher",
1153
0
                      dbgs() << "  Matching formal operand class " << getMatchClassName(Formal)
1154
0
                             << " against actual operand at index " << ActualIdx);
1155
0
      if (ActualIdx < Operands.size())
1156
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
1157
0
                        Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
1158
0
      else
1159
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
1160
0
      if (ActualIdx >= Operands.size()) {
1161
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
1162
0
        if (Formal == InvalidMatchClass) {
1163
0
          break;
1164
0
        }
1165
0
        if (isSubclass(Formal, OptionalMatchClass)) {
1166
0
          continue;
1167
0
        }
1168
0
        OperandsValid = false;
1169
0
        ErrorInfo = ActualIdx;
1170
0
        break;
1171
0
      }
1172
0
      MCParsedAsmOperand &Actual = *Operands[ActualIdx];
1173
0
      unsigned Diag = validateOperandClass(Actual, Formal);
1174
0
      if (Diag == Match_Success) {
1175
0
        DEBUG_WITH_TYPE("asm-matcher",
1176
0
                        dbgs() << "match success using generic matcher\n");
1177
0
        ++ActualIdx;
1178
0
        continue;
1179
0
      }
1180
      // If the generic handler indicates an invalid operand
1181
      // failure, check for a special case.
1182
0
      if (Diag != Match_Success) {
1183
0
        unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
1184
0
        if (TargetDiag == Match_Success) {
1185
0
          DEBUG_WITH_TYPE("asm-matcher",
1186
0
                          dbgs() << "match success using target matcher\n");
1187
0
          ++ActualIdx;
1188
0
          continue;
1189
0
        }
1190
        // If the target matcher returned a specific error code use
1191
        // that, else use the one from the generic matcher.
1192
0
        if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
1193
0
          Diag = TargetDiag;
1194
0
      }
1195
      // If current formal operand wasn't matched and it is optional
1196
      // then try to match next formal operand
1197
0
      if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
1198
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
1199
0
        continue;
1200
0
      }
1201
      // If this operand is broken for all of the instances of this
1202
      // mnemonic, keep track of it so we can report loc info.
1203
      // If we already had a match that only failed due to a
1204
      // target predicate, that diagnostic is preferred.
1205
0
      if (!HadMatchOtherThanPredicate &&
1206
0
          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
1207
0
        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
1208
0
          RetCode = Diag;
1209
0
        ErrorInfo = ActualIdx;
1210
0
      }
1211
      // Otherwise, just reject this instance of the mnemonic.
1212
0
      OperandsValid = false;
1213
0
      break;
1214
0
    }
1215
1216
0
    if (!OperandsValid) {
1217
0
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
1218
0
                                               "operand mismatches, ignoring "
1219
0
                                               "this opcode\n");
1220
0
      continue;
1221
0
    }
1222
0
    if (!HasRequiredFeatures) {
1223
0
      HadMatchOtherThanFeatures = true;
1224
0
      FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
1225
0
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
1226
0
                      for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
1227
0
                        if (NewMissingFeatures[I])
1228
0
                          dbgs() << ' ' << I;
1229
0
                      dbgs() << "\n");
1230
0
      if (NewMissingFeatures.count() <=
1231
0
          MissingFeatures.count())
1232
0
        MissingFeatures = NewMissingFeatures;
1233
0
      continue;
1234
0
    }
1235
1236
0
    Inst.clear();
1237
1238
0
    Inst.setOpcode(it->Opcode);
1239
    // We have a potential match but have not rendered the operands.
1240
    // Check the target predicate to handle any context sensitive
1241
    // constraints.
1242
    // For example, Ties that are referenced multiple times must be
1243
    // checked here to ensure the input is the same for each match
1244
    // constraints. If we leave it any later the ties will have been
1245
    // canonicalized
1246
0
    unsigned MatchResult;
1247
0
    if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
1248
0
      Inst.clear();
1249
0
      DEBUG_WITH_TYPE(
1250
0
          "asm-matcher",
1251
0
          dbgs() << "Early target match predicate failed with diag code "
1252
0
                 << MatchResult << "\n");
1253
0
      RetCode = MatchResult;
1254
0
      HadMatchOtherThanPredicate = true;
1255
0
      continue;
1256
0
    }
1257
1258
0
    if (matchingInlineAsm) {
1259
0
      convertToMapAndConstraints(it->ConvertFn, Operands);
1260
0
      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
1261
0
        return Match_InvalidTiedOperand;
1262
1263
0
      return Match_Success;
1264
0
    }
1265
1266
    // We have selected a definite instruction, convert the parsed
1267
    // operands into the appropriate MCInst.
1268
0
    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
1269
1270
    // We have a potential match. Check the target predicate to
1271
    // handle any context sensitive constraints.
1272
0
    if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
1273
0
      DEBUG_WITH_TYPE("asm-matcher",
1274
0
                      dbgs() << "Target match predicate failed with diag code "
1275
0
                             << MatchResult << "\n");
1276
0
      Inst.clear();
1277
0
      RetCode = MatchResult;
1278
0
      HadMatchOtherThanPredicate = true;
1279
0
      continue;
1280
0
    }
1281
1282
0
    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
1283
0
      return Match_InvalidTiedOperand;
1284
1285
0
    DEBUG_WITH_TYPE(
1286
0
        "asm-matcher",
1287
0
        dbgs() << "Opcode result: complete match, selecting this opcode\n");
1288
0
    return Match_Success;
1289
0
  }
1290
1291
  // Okay, we had no match.  Try to return a useful error code.
1292
0
  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
1293
0
    return RetCode;
1294
1295
0
  ErrorInfo = 0;
1296
0
  return Match_MissingFeature;
1297
0
}
1298
1299
#endif // GET_MATCHER_IMPLEMENTATION
1300
1301
1302
#ifdef GET_MNEMONIC_SPELL_CHECKER
1303
#undef GET_MNEMONIC_SPELL_CHECKER
1304
1305
static std::string MSP430MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
1306
  const unsigned MaxEditDist = 2;
1307
  std::vector<StringRef> Candidates;
1308
  StringRef Prev = "";
1309
1310
  // Find the appropriate table for this asm variant.
1311
  const MatchEntry *Start, *End;
1312
  switch (VariantID) {
1313
  default: llvm_unreachable("invalid variant!");
1314
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1315
  }
1316
1317
  for (auto I = Start; I < End; I++) {
1318
    // Ignore unsupported instructions.
1319
    const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
1320
    if ((FBS & RequiredFeatures) != RequiredFeatures)
1321
      continue;
1322
1323
    StringRef T = I->getMnemonic();
1324
    // Avoid recomputing the edit distance for the same string.
1325
    if (T.equals(Prev))
1326
      continue;
1327
1328
    Prev = T;
1329
    unsigned Dist = S.edit_distance(T, false, MaxEditDist);
1330
    if (Dist <= MaxEditDist)
1331
      Candidates.push_back(T);
1332
  }
1333
1334
  if (Candidates.empty())
1335
    return "";
1336
1337
  std::string Res = ", did you mean: ";
1338
  unsigned i = 0;
1339
  for (; i < Candidates.size() - 1; i++)
1340
    Res += Candidates[i].str() + ", ";
1341
  return Res + Candidates[i].str() + "?";
1342
}
1343
1344
#endif // GET_MNEMONIC_SPELL_CHECKER
1345
1346
1347
#ifdef GET_MNEMONIC_CHECKER
1348
#undef GET_MNEMONIC_CHECKER
1349
1350
static bool MSP430CheckMnemonic(StringRef Mnemonic,
1351
                                const FeatureBitset &AvailableFeatures,
1352
                                unsigned VariantID) {
1353
  // Find the appropriate table for this asm variant.
1354
  const MatchEntry *Start, *End;
1355
  switch (VariantID) {
1356
  default: llvm_unreachable("invalid variant!");
1357
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
1358
  }
1359
1360
  // Search the table.
1361
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
1362
1363
  if (MnemonicRange.first == MnemonicRange.second)
1364
    return false;
1365
1366
  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
1367
       it != ie; ++it) {
1368
    const FeatureBitset &RequiredFeatures =
1369
      FeatureBitsets[it->RequiredFeaturesIdx];
1370
    if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
1371
      return true;
1372
  }
1373
  return false;
1374
}
1375
1376
#endif // GET_MNEMONIC_CHECKER
1377