Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/MSP430/MSP430GenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace MSP430 {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
56
    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
95
    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
97
    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
124
    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
131
    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
133
    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
136
    G_FCONSTANT = 121,
137
    G_VASTART = 122,
138
    G_VAARG = 123,
139
    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
141
    G_ZEXT  = 126,
142
    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
147
    G_ROTR  = 132,
148
    G_ROTL  = 133,
149
    G_ICMP  = 134,
150
    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
153
    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
170
    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
173
    G_UMULFIXSAT  = 158,
174
    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
176
    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
179
    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
186
    G_FPOWI = 171,
187
    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
190
    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
193
    G_FLDEXP  = 178,
194
    G_FFREXP  = 179,
195
    G_FNEG  = 180,
196
    G_FPEXT = 181,
197
    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
204
    G_IS_FPCLASS  = 189,
205
    G_FCANONICALIZE = 190,
206
    G_FMINNUM = 191,
207
    G_FMAXNUM = 192,
208
    G_FMINNUM_IEEE  = 193,
209
    G_FMAXNUM_IEEE  = 194,
210
    G_FMINIMUM  = 195,
211
    G_FMAXIMUM  = 196,
212
    G_GET_FPENV = 197,
213
    G_SET_FPENV = 198,
214
    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
216
    G_SET_FPMODE  = 201,
217
    G_RESET_FPMODE  = 202,
218
    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
221
    G_SMAX  = 206,
222
    G_UMIN  = 207,
223
    G_UMAX  = 208,
224
    G_ABS = 209,
225
    G_LROUND  = 210,
226
    G_LLROUND = 211,
227
    G_BR  = 212,
228
    G_BRJT  = 213,
229
    G_INSERT_VECTOR_ELT = 214,
230
    G_EXTRACT_VECTOR_ELT  = 215,
231
    G_SHUFFLE_VECTOR  = 216,
232
    G_CTTZ  = 217,
233
    G_CTTZ_ZERO_UNDEF = 218,
234
    G_CTLZ  = 219,
235
    G_CTLZ_ZERO_UNDEF = 220,
236
    G_CTPOP = 221,
237
    G_BSWAP = 222,
238
    G_BITREVERSE  = 223,
239
    G_FCEIL = 224,
240
    G_FCOS  = 225,
241
    G_FSIN  = 226,
242
    G_FSQRT = 227,
243
    G_FFLOOR  = 228,
244
    G_FRINT = 229,
245
    G_FNEARBYINT  = 230,
246
    G_ADDRSPACE_CAST  = 231,
247
    G_BLOCK_ADDR  = 232,
248
    G_JUMP_TABLE  = 233,
249
    G_DYN_STACKALLOC  = 234,
250
    G_STACKSAVE = 235,
251
    G_STACKRESTORE  = 236,
252
    G_STRICT_FADD = 237,
253
    G_STRICT_FSUB = 238,
254
    G_STRICT_FMUL = 239,
255
    G_STRICT_FDIV = 240,
256
    G_STRICT_FREM = 241,
257
    G_STRICT_FMA  = 242,
258
    G_STRICT_FSQRT  = 243,
259
    G_STRICT_FLDEXP = 244,
260
    G_READ_REGISTER = 245,
261
    G_WRITE_REGISTER  = 246,
262
    G_MEMCPY  = 247,
263
    G_MEMCPY_INLINE = 248,
264
    G_MEMMOVE = 249,
265
    G_MEMSET  = 250,
266
    G_BZERO = 251,
267
    G_VECREDUCE_SEQ_FADD  = 252,
268
    G_VECREDUCE_SEQ_FMUL  = 253,
269
    G_VECREDUCE_FADD  = 254,
270
    G_VECREDUCE_FMUL  = 255,
271
    G_VECREDUCE_FMAX  = 256,
272
    G_VECREDUCE_FMIN  = 257,
273
    G_VECREDUCE_FMAXIMUM  = 258,
274
    G_VECREDUCE_FMINIMUM  = 259,
275
    G_VECREDUCE_ADD = 260,
276
    G_VECREDUCE_MUL = 261,
277
    G_VECREDUCE_AND = 262,
278
    G_VECREDUCE_OR  = 263,
279
    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
281
    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
284
    G_SBFX  = 269,
285
    G_UBFX  = 270,
286
    ADD16mc = 271,
287
    ADD16mi = 272,
288
    ADD16mm = 273,
289
    ADD16mn = 274,
290
    ADD16mp = 275,
291
    ADD16mr = 276,
292
    ADD16rc = 277,
293
    ADD16ri = 278,
294
    ADD16rm = 279,
295
    ADD16rn = 280,
296
    ADD16rp = 281,
297
    ADD16rr = 282,
298
    ADD8mc  = 283,
299
    ADD8mi  = 284,
300
    ADD8mm  = 285,
301
    ADD8mn  = 286,
302
    ADD8mp  = 287,
303
    ADD8mr  = 288,
304
    ADD8rc  = 289,
305
    ADD8ri  = 290,
306
    ADD8rm  = 291,
307
    ADD8rn  = 292,
308
    ADD8rp  = 293,
309
    ADD8rr  = 294,
310
    ADDC16mc  = 295,
311
    ADDC16mi  = 296,
312
    ADDC16mm  = 297,
313
    ADDC16mn  = 298,
314
    ADDC16mp  = 299,
315
    ADDC16mr  = 300,
316
    ADDC16rc  = 301,
317
    ADDC16ri  = 302,
318
    ADDC16rm  = 303,
319
    ADDC16rn  = 304,
320
    ADDC16rp  = 305,
321
    ADDC16rr  = 306,
322
    ADDC8mc = 307,
323
    ADDC8mi = 308,
324
    ADDC8mm = 309,
325
    ADDC8mn = 310,
326
    ADDC8mp = 311,
327
    ADDC8mr = 312,
328
    ADDC8rc = 313,
329
    ADDC8ri = 314,
330
    ADDC8rm = 315,
331
    ADDC8rn = 316,
332
    ADDC8rp = 317,
333
    ADDC8rr = 318,
334
    ADDframe  = 319,
335
    ADJCALLSTACKDOWN  = 320,
336
    ADJCALLSTACKUP  = 321,
337
    AND16mc = 322,
338
    AND16mi = 323,
339
    AND16mm = 324,
340
    AND16mn = 325,
341
    AND16mp = 326,
342
    AND16mr = 327,
343
    AND16rc = 328,
344
    AND16ri = 329,
345
    AND16rm = 330,
346
    AND16rn = 331,
347
    AND16rp = 332,
348
    AND16rr = 333,
349
    AND8mc  = 334,
350
    AND8mi  = 335,
351
    AND8mm  = 336,
352
    AND8mn  = 337,
353
    AND8mp  = 338,
354
    AND8mr  = 339,
355
    AND8rc  = 340,
356
    AND8ri  = 341,
357
    AND8rm  = 342,
358
    AND8rn  = 343,
359
    AND8rp  = 344,
360
    AND8rr  = 345,
361
    BIC16mc = 346,
362
    BIC16mi = 347,
363
    BIC16mm = 348,
364
    BIC16mn = 349,
365
    BIC16mp = 350,
366
    BIC16mr = 351,
367
    BIC16rc = 352,
368
    BIC16ri = 353,
369
    BIC16rm = 354,
370
    BIC16rn = 355,
371
    BIC16rp = 356,
372
    BIC16rr = 357,
373
    BIC8mc  = 358,
374
    BIC8mi  = 359,
375
    BIC8mm  = 360,
376
    BIC8mn  = 361,
377
    BIC8mp  = 362,
378
    BIC8mr  = 363,
379
    BIC8rc  = 364,
380
    BIC8ri  = 365,
381
    BIC8rm  = 366,
382
    BIC8rn  = 367,
383
    BIC8rp  = 368,
384
    BIC8rr  = 369,
385
    BIS16mc = 370,
386
    BIS16mi = 371,
387
    BIS16mm = 372,
388
    BIS16mn = 373,
389
    BIS16mp = 374,
390
    BIS16mr = 375,
391
    BIS16rc = 376,
392
    BIS16ri = 377,
393
    BIS16rm = 378,
394
    BIS16rn = 379,
395
    BIS16rp = 380,
396
    BIS16rr = 381,
397
    BIS8mc  = 382,
398
    BIS8mi  = 383,
399
    BIS8mm  = 384,
400
    BIS8mn  = 385,
401
    BIS8mp  = 386,
402
    BIS8mr  = 387,
403
    BIS8rc  = 388,
404
    BIS8ri  = 389,
405
    BIS8rm  = 390,
406
    BIS8rn  = 391,
407
    BIS8rp  = 392,
408
    BIS8rr  = 393,
409
    BIT16mc = 394,
410
    BIT16mi = 395,
411
    BIT16mm = 396,
412
    BIT16mn = 397,
413
    BIT16mp = 398,
414
    BIT16mr = 399,
415
    BIT16rc = 400,
416
    BIT16ri = 401,
417
    BIT16rm = 402,
418
    BIT16rn = 403,
419
    BIT16rp = 404,
420
    BIT16rr = 405,
421
    BIT8mc  = 406,
422
    BIT8mi  = 407,
423
    BIT8mm  = 408,
424
    BIT8mn  = 409,
425
    BIT8mp  = 410,
426
    BIT8mr  = 411,
427
    BIT8rc  = 412,
428
    BIT8ri  = 413,
429
    BIT8rm  = 414,
430
    BIT8rn  = 415,
431
    BIT8rp  = 416,
432
    BIT8rr  = 417,
433
    Bi  = 418,
434
    Bm  = 419,
435
    Br  = 420,
436
    CALLi = 421,
437
    CALLm = 422,
438
    CALLn = 423,
439
    CALLp = 424,
440
    CALLr = 425,
441
    CMP16mc = 426,
442
    CMP16mi = 427,
443
    CMP16mm = 428,
444
    CMP16mn = 429,
445
    CMP16mp = 430,
446
    CMP16mr = 431,
447
    CMP16rc = 432,
448
    CMP16ri = 433,
449
    CMP16rm = 434,
450
    CMP16rn = 435,
451
    CMP16rp = 436,
452
    CMP16rr = 437,
453
    CMP8mc  = 438,
454
    CMP8mi  = 439,
455
    CMP8mm  = 440,
456
    CMP8mn  = 441,
457
    CMP8mp  = 442,
458
    CMP8mr  = 443,
459
    CMP8rc  = 444,
460
    CMP8ri  = 445,
461
    CMP8rm  = 446,
462
    CMP8rn  = 447,
463
    CMP8rp  = 448,
464
    CMP8rr  = 449,
465
    DADD16mc  = 450,
466
    DADD16mi  = 451,
467
    DADD16mm  = 452,
468
    DADD16mn  = 453,
469
    DADD16mp  = 454,
470
    DADD16mr  = 455,
471
    DADD16rc  = 456,
472
    DADD16ri  = 457,
473
    DADD16rm  = 458,
474
    DADD16rn  = 459,
475
    DADD16rp  = 460,
476
    DADD16rr  = 461,
477
    DADD8mc = 462,
478
    DADD8mi = 463,
479
    DADD8mm = 464,
480
    DADD8mn = 465,
481
    DADD8mp = 466,
482
    DADD8mr = 467,
483
    DADD8rc = 468,
484
    DADD8ri = 469,
485
    DADD8rm = 470,
486
    DADD8rn = 471,
487
    DADD8rp = 472,
488
    DADD8rr = 473,
489
    JCC = 474,
490
    JMP = 475,
491
    MOV16mc = 476,
492
    MOV16mi = 477,
493
    MOV16mm = 478,
494
    MOV16mn = 479,
495
    MOV16mr = 480,
496
    MOV16rc = 481,
497
    MOV16ri = 482,
498
    MOV16rm = 483,
499
    MOV16rn = 484,
500
    MOV16rp = 485,
501
    MOV16rr = 486,
502
    MOV8mc  = 487,
503
    MOV8mi  = 488,
504
    MOV8mm  = 489,
505
    MOV8mn  = 490,
506
    MOV8mr  = 491,
507
    MOV8rc  = 492,
508
    MOV8ri  = 493,
509
    MOV8rm  = 494,
510
    MOV8rn  = 495,
511
    MOV8rp  = 496,
512
    MOV8rr  = 497,
513
    MOVZX16rm8  = 498,
514
    MOVZX16rr8  = 499,
515
    POP16r  = 500,
516
    PUSH16c = 501,
517
    PUSH16i = 502,
518
    PUSH16r = 503,
519
    PUSH8r  = 504,
520
    RET = 505,
521
    RETI  = 506,
522
    RRA16m  = 507,
523
    RRA16n  = 508,
524
    RRA16p  = 509,
525
    RRA16r  = 510,
526
    RRA8m = 511,
527
    RRA8n = 512,
528
    RRA8p = 513,
529
    RRA8r = 514,
530
    RRC16m  = 515,
531
    RRC16n  = 516,
532
    RRC16p  = 517,
533
    RRC16r  = 518,
534
    RRC8m = 519,
535
    RRC8n = 520,
536
    RRC8p = 521,
537
    RRC8r = 522,
538
    Rrcl16  = 523,
539
    Rrcl8 = 524,
540
    SEXT16m = 525,
541
    SEXT16n = 526,
542
    SEXT16p = 527,
543
    SEXT16r = 528,
544
    SUB16mc = 529,
545
    SUB16mi = 530,
546
    SUB16mm = 531,
547
    SUB16mn = 532,
548
    SUB16mp = 533,
549
    SUB16mr = 534,
550
    SUB16rc = 535,
551
    SUB16ri = 536,
552
    SUB16rm = 537,
553
    SUB16rn = 538,
554
    SUB16rp = 539,
555
    SUB16rr = 540,
556
    SUB8mc  = 541,
557
    SUB8mi  = 542,
558
    SUB8mm  = 543,
559
    SUB8mn  = 544,
560
    SUB8mp  = 545,
561
    SUB8mr  = 546,
562
    SUB8rc  = 547,
563
    SUB8ri  = 548,
564
    SUB8rm  = 549,
565
    SUB8rn  = 550,
566
    SUB8rp  = 551,
567
    SUB8rr  = 552,
568
    SUBC16mc  = 553,
569
    SUBC16mi  = 554,
570
    SUBC16mm  = 555,
571
    SUBC16mn  = 556,
572
    SUBC16mp  = 557,
573
    SUBC16mr  = 558,
574
    SUBC16rc  = 559,
575
    SUBC16ri  = 560,
576
    SUBC16rm  = 561,
577
    SUBC16rn  = 562,
578
    SUBC16rp  = 563,
579
    SUBC16rr  = 564,
580
    SUBC8mc = 565,
581
    SUBC8mi = 566,
582
    SUBC8mm = 567,
583
    SUBC8mn = 568,
584
    SUBC8mp = 569,
585
    SUBC8mr = 570,
586
    SUBC8rc = 571,
587
    SUBC8ri = 572,
588
    SUBC8rm = 573,
589
    SUBC8rn = 574,
590
    SUBC8rp = 575,
591
    SUBC8rr = 576,
592
    SWPB16m = 577,
593
    SWPB16n = 578,
594
    SWPB16p = 579,
595
    SWPB16r = 580,
596
    Select16  = 581,
597
    Select8 = 582,
598
    Shl16 = 583,
599
    Shl8  = 584,
600
    Sra16 = 585,
601
    Sra8  = 586,
602
    Srl16 = 587,
603
    Srl8  = 588,
604
    XOR16mc = 589,
605
    XOR16mi = 590,
606
    XOR16mm = 591,
607
    XOR16mn = 592,
608
    XOR16mp = 593,
609
    XOR16mr = 594,
610
    XOR16rc = 595,
611
    XOR16ri = 596,
612
    XOR16rm = 597,
613
    XOR16rn = 598,
614
    XOR16rp = 599,
615
    XOR16rr = 600,
616
    XOR8mc  = 601,
617
    XOR8mi  = 602,
618
    XOR8mm  = 603,
619
    XOR8mn  = 604,
620
    XOR8mp  = 605,
621
    XOR8mr  = 606,
622
    XOR8rc  = 607,
623
    XOR8ri  = 608,
624
    XOR8rm  = 609,
625
    XOR8rn  = 610,
626
    XOR8rp  = 611,
627
    XOR8rr  = 612,
628
    ZEXT16r = 613,
629
    INSTRUCTION_LIST_END = 614
630
  };
631
632
} // end namespace MSP430
633
} // end namespace llvm
634
#endif // GET_INSTRINFO_ENUM
635
636
#ifdef GET_INSTRINFO_SCHED_ENUM
637
#undef GET_INSTRINFO_SCHED_ENUM
638
namespace llvm {
639
640
namespace MSP430 {
641
namespace Sched {
642
  enum {
643
    NoInstrModel  = 0,
644
    SCHED_LIST_END = 1
645
  };
646
} // end namespace Sched
647
} // end namespace MSP430
648
} // end namespace llvm
649
#endif // GET_INSTRINFO_SCHED_ENUM
650
651
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
652
namespace llvm {
653
654
struct MSP430InstrTable {
655
  MCInstrDesc Insts[614];
656
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
657
  MCOperandInfo OperandInfo[255];
658
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
659
  MCPhysReg ImplicitOps[17];
660
};
661
662
} // end namespace llvm
663
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
664
665
#ifdef GET_INSTRINFO_MC_DESC
666
#undef GET_INSTRINFO_MC_DESC
667
namespace llvm {
668
669
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
670
static constexpr unsigned MSP430ImpOpBase = sizeof MSP430InstrTable::OperandInfo / (sizeof(MCPhysReg));
671
672
extern const MSP430InstrTable MSP430Descs = {
673
  {
674
    { 613,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  237,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #613 = ZEXT16r
675
    { 612,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  196,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #612 = XOR8rr
676
    { 611,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #611 = XOR8rp
677
    { 610,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #610 = XOR8rn
678
    { 609,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #609 = XOR8rm
679
    { 608,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #608 = XOR8ri
680
    { 607,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #607 = XOR8rc
681
    { 606,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #606 = XOR8mr
682
    { 605,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #605 = XOR8mp
683
    { 604,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #604 = XOR8mn
684
    { 603,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #603 = XOR8mm
685
    { 602,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #602 = XOR8mi
686
    { 601,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #601 = XOR8mc
687
    { 600,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  173,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #600 = XOR16rr
688
    { 599,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #599 = XOR16rp
689
    { 598,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #598 = XOR16rn
690
    { 597,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #597 = XOR16rm
691
    { 596,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #596 = XOR16ri
692
    { 595,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #595 = XOR16rc
693
    { 594,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #594 = XOR16mr
694
    { 593,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #593 = XOR16mp
695
    { 592,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #592 = XOR16mn
696
    { 591,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #591 = XOR16mm
697
    { 590,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #590 = XOR16mi
698
    { 589,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #589 = XOR16mc
699
    { 588,  3,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  252,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #588 = Srl8
700
    { 587,  3,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  249,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #587 = Srl16
701
    { 586,  3,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  252,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #586 = Sra8
702
    { 585,  3,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  249,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #585 = Sra16
703
    { 584,  3,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  252,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #584 = Shl8
704
    { 583,  3,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  249,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #583 = Shl16
705
    { 582,  4,  1,  0,  0,  1,  0,  MSP430ImpOpBase + 0,  245,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #582 = Select8
706
    { 581,  4,  1,  0,  0,  1,  0,  MSP430ImpOpBase + 0,  241,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #581 = Select16
707
    { 580,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  237,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #580 = SWPB16r
708
    { 579,  1,  0,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #579 = SWPB16p
709
    { 578,  1,  0,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #578 = SWPB16n
710
    { 577,  2,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  224,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #577 = SWPB16m
711
    { 576,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  196,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #576 = SUBC8rr
712
    { 575,  4,  2,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #575 = SUBC8rp
713
    { 574,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #574 = SUBC8rn
714
    { 573,  4,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #573 = SUBC8rm
715
    { 572,  3,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #572 = SUBC8ri
716
    { 571,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #571 = SUBC8rc
717
    { 570,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #570 = SUBC8mr
718
    { 569,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #569 = SUBC8mp
719
    { 568,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #568 = SUBC8mn
720
    { 567,  4,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #567 = SUBC8mm
721
    { 566,  3,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #566 = SUBC8mi
722
    { 565,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #565 = SUBC8mc
723
    { 564,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  173,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #564 = SUBC16rr
724
    { 563,  4,  2,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #563 = SUBC16rp
725
    { 562,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #562 = SUBC16rn
726
    { 561,  4,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #561 = SUBC16rm
727
    { 560,  3,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #560 = SUBC16ri
728
    { 559,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #559 = SUBC16rc
729
    { 558,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #558 = SUBC16mr
730
    { 557,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #557 = SUBC16mp
731
    { 556,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #556 = SUBC16mn
732
    { 555,  4,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #555 = SUBC16mm
733
    { 554,  3,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #554 = SUBC16mi
734
    { 553,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #553 = SUBC16mc
735
    { 552,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  196,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #552 = SUB8rr
736
    { 551,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #551 = SUB8rp
737
    { 550,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #550 = SUB8rn
738
    { 549,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #549 = SUB8rm
739
    { 548,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #548 = SUB8ri
740
    { 547,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #547 = SUB8rc
741
    { 546,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #546 = SUB8mr
742
    { 545,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #545 = SUB8mp
743
    { 544,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #544 = SUB8mn
744
    { 543,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #543 = SUB8mm
745
    { 542,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #542 = SUB8mi
746
    { 541,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #541 = SUB8mc
747
    { 540,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  173,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #540 = SUB16rr
748
    { 539,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #539 = SUB16rp
749
    { 538,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #538 = SUB16rn
750
    { 537,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #537 = SUB16rm
751
    { 536,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #536 = SUB16ri
752
    { 535,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #535 = SUB16rc
753
    { 534,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #534 = SUB16mr
754
    { 533,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #533 = SUB16mp
755
    { 532,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #532 = SUB16mn
756
    { 531,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #531 = SUB16mm
757
    { 530,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #530 = SUB16mi
758
    { 529,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #529 = SUB16mc
759
    { 528,  2,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  237,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #528 = SEXT16r
760
    { 527,  1,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #527 = SEXT16p
761
    { 526,  1,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #526 = SEXT16n
762
    { 525,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  224,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #525 = SEXT16m
763
    { 524,  2,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  222,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #524 = Rrcl8
764
    { 523,  2,  1,  0,  0,  0,  1,  MSP430ImpOpBase + 0,  211,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #523 = Rrcl16
765
    { 522,  2,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  239,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #522 = RRC8r
766
    { 521,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #521 = RRC8p
767
    { 520,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #520 = RRC8n
768
    { 519,  2,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  224,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #519 = RRC8m
769
    { 518,  2,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  237,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #518 = RRC16r
770
    { 517,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #517 = RRC16p
771
    { 516,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #516 = RRC16n
772
    { 515,  2,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  224,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #515 = RRC16m
773
    { 514,  2,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  239,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #514 = RRA8r
774
    { 513,  1,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #513 = RRA8p
775
    { 512,  1,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #512 = RRA8n
776
    { 511,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  224,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #511 = RRA8m
777
    { 510,  2,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  237,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #510 = RRA16r
778
    { 509,  1,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #509 = RRA16p
779
    { 508,  1,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  227,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #508 = RRA16n
780
    { 507,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  224,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #507 = RRA16m
781
    { 506,  0,  0,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #506 = RETI
782
    { 505,  0,  0,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #505 = RET
783
    { 504,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 15, 236,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #504 = PUSH8r
784
    { 503,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 15, 226,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #503 = PUSH16r
785
    { 502,  1,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 15, 1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #502 = PUSH16i
786
    { 501,  1,  0,  2,  0,  1,  1,  MSP430ImpOpBase + 15, 0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #501 = PUSH16c
787
    { 500,  1,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 15, 226,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #500 = POP16r
788
    { 499,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  234,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #499 = MOVZX16rr8
789
    { 498,  3,  1,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #498 = MOVZX16rm8
790
    { 497,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  222,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #497 = MOV8rr
791
    { 496,  3,  2,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  231,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #496 = MOV8rp
792
    { 495,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  220,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #495 = MOV8rn
793
    { 494,  3,  1,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  217,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #494 = MOV8rm
794
    { 493,  2,  1,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  215,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #493 = MOV8ri
795
    { 492,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  213,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #492 = MOV8rc
796
    { 491,  3,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #491 = MOV8mr
797
    { 490,  3,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #490 = MOV8mn
798
    { 489,  4,  0,  6,  0,  0,  0,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #489 = MOV8mm
799
    { 488,  3,  0,  6,  0,  0,  0,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #488 = MOV8mi
800
    { 487,  3,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #487 = MOV8mc
801
    { 486,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  211,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #486 = MOV16rr
802
    { 485,  3,  2,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  228,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #485 = MOV16rp
803
    { 484,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  209,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #484 = MOV16rn
804
    { 483,  3,  1,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  206,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #483 = MOV16rm
805
    { 482,  2,  1,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  204,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #482 = MOV16ri
806
    { 481,  2,  1,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  202,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #481 = MOV16rc
807
    { 480,  3,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #480 = MOV16mr
808
    { 479,  3,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #479 = MOV16mn
809
    { 478,  4,  0,  6,  0,  0,  0,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #478 = MOV16mm
810
    { 477,  3,  0,  6,  0,  0,  0,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #477 = MOV16mi
811
    { 476,  3,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #476 = MOV16mc
812
    { 475,  1,  0,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #475 = JMP
813
    { 474,  2,  0,  2,  0,  1,  0,  MSP430ImpOpBase + 0,  13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #474 = JCC
814
    { 473,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  196,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #473 = DADD8rr
815
    { 472,  4,  2,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #472 = DADD8rp
816
    { 471,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #471 = DADD8rn
817
    { 470,  4,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #470 = DADD8rm
818
    { 469,  3,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #469 = DADD8ri
819
    { 468,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #468 = DADD8rc
820
    { 467,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #467 = DADD8mr
821
    { 466,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #466 = DADD8mp
822
    { 465,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #465 = DADD8mn
823
    { 464,  4,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #464 = DADD8mm
824
    { 463,  3,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #463 = DADD8mi
825
    { 462,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #462 = DADD8mc
826
    { 461,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  173,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #461 = DADD16rr
827
    { 460,  4,  2,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #460 = DADD16rp
828
    { 459,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #459 = DADD16rn
829
    { 458,  4,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #458 = DADD16rm
830
    { 457,  3,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #457 = DADD16ri
831
    { 456,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #456 = DADD16rc
832
    { 455,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #455 = DADD16mr
833
    { 454,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #454 = DADD16mp
834
    { 453,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #453 = DADD16mn
835
    { 452,  4,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #452 = DADD16mm
836
    { 451,  3,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #451 = DADD16mi
837
    { 450,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #450 = DADD16mc
838
    { 449,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  222,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #449 = CMP8rr
839
    { 448,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  220,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #448 = CMP8rp
840
    { 447,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  220,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #447 = CMP8rn
841
    { 446,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  217,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #446 = CMP8rm
842
    { 445,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  215,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #445 = CMP8ri
843
    { 444,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  213,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #444 = CMP8rc
844
    { 443,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #443 = CMP8mr
845
    { 442,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #442 = CMP8mp
846
    { 441,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #441 = CMP8mn
847
    { 440,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #440 = CMP8mm
848
    { 439,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #439 = CMP8mi
849
    { 438,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #438 = CMP8mc
850
    { 437,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  211,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #437 = CMP16rr
851
    { 436,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  209,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #436 = CMP16rp
852
    { 435,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  209,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #435 = CMP16rn
853
    { 434,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #434 = CMP16rm
854
    { 433,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #433 = CMP16ri
855
    { 432,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  202,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #432 = CMP16rc
856
    { 431,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #431 = CMP16mr
857
    { 430,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #430 = CMP16mp
858
    { 429,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #429 = CMP16mn
859
    { 428,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #428 = CMP16mm
860
    { 427,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #427 = CMP16mi
861
    { 426,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #426 = CMP16mc
862
    { 425,  1,  0,  2,  0,  1,  6,  MSP430ImpOpBase + 8,  226,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #425 = CALLr
863
    { 424,  1,  0,  2,  0,  1,  6,  MSP430ImpOpBase + 8,  227,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #424 = CALLp
864
    { 423,  1,  0,  2,  0,  1,  6,  MSP430ImpOpBase + 8,  227,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #423 = CALLn
865
    { 422,  2,  0,  4,  0,  1,  6,  MSP430ImpOpBase + 8,  224,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #422 = CALLm
866
    { 421,  1,  0,  4,  0,  1,  6,  MSP430ImpOpBase + 8,  1,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #421 = CALLi
867
    { 420,  1,  0,  2,  0,  0,  0,  MSP430ImpOpBase + 0,  226,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #420 = Br
868
    { 419,  2,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  224,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #419 = Bm
869
    { 418,  1,  0,  4,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #418 = Bi
870
    { 417,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  222,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #417 = BIT8rr
871
    { 416,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  220,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #416 = BIT8rp
872
    { 415,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  220,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #415 = BIT8rn
873
    { 414,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  217,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #414 = BIT8rm
874
    { 413,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  215,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #413 = BIT8ri
875
    { 412,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  213,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #412 = BIT8rc
876
    { 411,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #411 = BIT8mr
877
    { 410,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #410 = BIT8mp
878
    { 409,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #409 = BIT8mn
879
    { 408,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #408 = BIT8mm
880
    { 407,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #407 = BIT8mi
881
    { 406,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #406 = BIT8mc
882
    { 405,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  211,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #405 = BIT16rr
883
    { 404,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  209,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #404 = BIT16rp
884
    { 403,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  209,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #403 = BIT16rn
885
    { 402,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  206,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #402 = BIT16rm
886
    { 401,  2,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  204,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #401 = BIT16ri
887
    { 400,  2,  0,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  202,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #400 = BIT16rc
888
    { 399,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #399 = BIT16mr
889
    { 398,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #398 = BIT16mp
890
    { 397,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #397 = BIT16mn
891
    { 396,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #396 = BIT16mm
892
    { 395,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #395 = BIT16mi
893
    { 394,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #394 = BIT16mc
894
    { 393,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  196,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #393 = BIS8rr
895
    { 392,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #392 = BIS8rp
896
    { 391,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #391 = BIS8rn
897
    { 390,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #390 = BIS8rm
898
    { 389,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #389 = BIS8ri
899
    { 388,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #388 = BIS8rc
900
    { 387,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #387 = BIS8mr
901
    { 386,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #386 = BIS8mp
902
    { 385,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #385 = BIS8mn
903
    { 384,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #384 = BIS8mm
904
    { 383,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #383 = BIS8mi
905
    { 382,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #382 = BIS8mc
906
    { 381,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  173,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #381 = BIS16rr
907
    { 380,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #380 = BIS16rp
908
    { 379,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #379 = BIS16rn
909
    { 378,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #378 = BIS16rm
910
    { 377,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #377 = BIS16ri
911
    { 376,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #376 = BIS16rc
912
    { 375,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #375 = BIS16mr
913
    { 374,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #374 = BIS16mp
914
    { 373,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #373 = BIS16mn
915
    { 372,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #372 = BIS16mm
916
    { 371,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #371 = BIS16mi
917
    { 370,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #370 = BIS16mc
918
    { 369,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  196,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #369 = BIC8rr
919
    { 368,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #368 = BIC8rp
920
    { 367,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #367 = BIC8rn
921
    { 366,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #366 = BIC8rm
922
    { 365,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #365 = BIC8ri
923
    { 364,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #364 = BIC8rc
924
    { 363,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #363 = BIC8mr
925
    { 362,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #362 = BIC8mp
926
    { 361,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #361 = BIC8mn
927
    { 360,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #360 = BIC8mm
928
    { 359,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #359 = BIC8mi
929
    { 358,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #358 = BIC8mc
930
    { 357,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  173,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #357 = BIC16rr
931
    { 356,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #356 = BIC16rp
932
    { 355,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #355 = BIC16rn
933
    { 354,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #354 = BIC16rm
934
    { 353,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #353 = BIC16ri
935
    { 352,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #352 = BIC16rc
936
    { 351,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #351 = BIC16mr
937
    { 350,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #350 = BIC16mp
938
    { 349,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #349 = BIC16mn
939
    { 348,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #348 = BIC16mm
940
    { 347,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #347 = BIC16mi
941
    { 346,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #346 = BIC16mc
942
    { 345,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  196,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #345 = AND8rr
943
    { 344,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #344 = AND8rp
944
    { 343,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #343 = AND8rn
945
    { 342,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #342 = AND8rm
946
    { 341,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #341 = AND8ri
947
    { 340,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #340 = AND8rc
948
    { 339,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #339 = AND8mr
949
    { 338,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #338 = AND8mp
950
    { 337,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #337 = AND8mn
951
    { 336,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #336 = AND8mm
952
    { 335,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #335 = AND8mi
953
    { 334,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #334 = AND8mc
954
    { 333,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  173,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #333 = AND16rr
955
    { 332,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #332 = AND16rp
956
    { 331,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #331 = AND16rn
957
    { 330,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #330 = AND16rm
958
    { 329,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #329 = AND16ri
959
    { 328,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #328 = AND16rc
960
    { 327,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #327 = AND16mr
961
    { 326,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #326 = AND16mp
962
    { 325,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #325 = AND16mn
963
    { 324,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #324 = AND16mm
964
    { 323,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #323 = AND16mi
965
    { 322,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #322 = AND16mc
966
    { 321,  2,  0,  0,  0,  1,  2,  MSP430ImpOpBase + 5,  21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #321 = ADJCALLSTACKUP
967
    { 320,  2,  0,  0,  0,  1,  2,  MSP430ImpOpBase + 5,  21, 0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #320 = ADJCALLSTACKDOWN
968
    { 319,  3,  1,  0,  0,  1,  1,  MSP430ImpOpBase + 3,  199,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #319 = ADDframe
969
    { 318,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  196,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #318 = ADDC8rr
970
    { 317,  4,  2,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #317 = ADDC8rp
971
    { 316,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #316 = ADDC8rn
972
    { 315,  4,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #315 = ADDC8rm
973
    { 314,  3,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #314 = ADDC8ri
974
    { 313,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #313 = ADDC8rc
975
    { 312,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #312 = ADDC8mr
976
    { 311,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #311 = ADDC8mp
977
    { 310,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #310 = ADDC8mn
978
    { 309,  4,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #309 = ADDC8mm
979
    { 308,  3,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #308 = ADDC8mi
980
    { 307,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #307 = ADDC8mc
981
    { 306,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  173,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #306 = ADDC16rr
982
    { 305,  4,  2,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #305 = ADDC16rp
983
    { 304,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #304 = ADDC16rn
984
    { 303,  4,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #303 = ADDC16rm
985
    { 302,  3,  1,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #302 = ADDC16ri
986
    { 301,  3,  1,  2,  0,  1,  1,  MSP430ImpOpBase + 1,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #301 = ADDC16rc
987
    { 300,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #300 = ADDC16mr
988
    { 299,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #299 = ADDC16mp
989
    { 298,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #298 = ADDC16mn
990
    { 297,  4,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #297 = ADDC16mm
991
    { 296,  3,  0,  6,  0,  1,  1,  MSP430ImpOpBase + 1,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #296 = ADDC16mi
992
    { 295,  3,  0,  4,  0,  1,  1,  MSP430ImpOpBase + 1,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #295 = ADDC16mc
993
    { 294,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  196,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #294 = ADD8rr
994
    { 293,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  192,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #293 = ADD8rp
995
    { 292,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  189,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #292 = ADD8rn
996
    { 291,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #291 = ADD8rm
997
    { 290,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  182,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #290 = ADD8ri
998
    { 289,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  179,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #289 = ADD8rc
999
    { 288,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  176,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #288 = ADD8mr
1000
    { 287,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #287 = ADD8mp
1001
    { 286,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #286 = ADD8mn
1002
    { 285,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #285 = ADD8mm
1003
    { 284,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #284 = ADD8mi
1004
    { 283,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #283 = ADD8mc
1005
    { 282,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  173,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #282 = ADD16rr
1006
    { 281,  4,  2,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  169,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #281 = ADD16rp
1007
    { 280,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  166,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #280 = ADD16rn
1008
    { 279,  4,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  162,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #279 = ADD16rm
1009
    { 278,  3,  1,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  159,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #278 = ADD16ri
1010
    { 277,  3,  1,  2,  0,  0,  1,  MSP430ImpOpBase + 0,  156,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #277 = ADD16rc
1011
    { 276,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  153,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #276 = ADD16mr
1012
    { 275,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #275 = ADD16mp
1013
    { 274,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  150,  0|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #274 = ADD16mn
1014
    { 273,  4,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  146,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #273 = ADD16mm
1015
    { 272,  3,  0,  6,  0,  0,  1,  MSP430ImpOpBase + 0,  143,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #272 = ADD16mi
1016
    { 271,  3,  0,  4,  0,  0,  1,  MSP430ImpOpBase + 0,  140,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #271 = ADD16mc
1017
    { 270,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #270 = G_UBFX
1018
    { 269,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #269 = G_SBFX
1019
    { 268,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
1020
    { 267,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
1021
    { 266,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
1022
    { 265,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
1023
    { 264,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
1024
    { 263,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
1025
    { 262,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
1026
    { 261,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
1027
    { 260,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
1028
    { 259,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
1029
    { 258,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
1030
    { 257,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
1031
    { 256,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
1032
    { 255,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
1033
    { 254,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
1034
    { 253,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
1035
    { 252,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
1036
    { 251,  3,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #251 = G_BZERO
1037
    { 250,  4,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #250 = G_MEMSET
1038
    { 249,  4,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #249 = G_MEMMOVE
1039
    { 248,  3,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
1040
    { 247,  4,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #247 = G_MEMCPY
1041
    { 246,  2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
1042
    { 245,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
1043
    { 244,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
1044
    { 243,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
1045
    { 242,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #242 = G_STRICT_FMA
1046
    { 241,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #241 = G_STRICT_FREM
1047
    { 240,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
1048
    { 239,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
1049
    { 238,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
1050
    { 237,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #237 = G_STRICT_FADD
1051
    { 236,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #236 = G_STACKRESTORE
1052
    { 235,  1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #235 = G_STACKSAVE
1053
    { 234,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
1054
    { 233,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
1055
    { 232,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
1056
    { 231,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
1057
    { 230,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #230 = G_FNEARBYINT
1058
    { 229,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #229 = G_FRINT
1059
    { 228,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #228 = G_FFLOOR
1060
    { 227,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #227 = G_FSQRT
1061
    { 226,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #226 = G_FSIN
1062
    { 225,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #225 = G_FCOS
1063
    { 224,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #224 = G_FCEIL
1064
    { 223,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #223 = G_BITREVERSE
1065
    { 222,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #222 = G_BSWAP
1066
    { 221,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #221 = G_CTPOP
1067
    { 220,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
1068
    { 219,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #219 = G_CTLZ
1069
    { 218,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
1070
    { 217,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #217 = G_CTTZ
1071
    { 216,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
1072
    { 215,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
1073
    { 214,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
1074
    { 213,  3,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #213 = G_BRJT
1075
    { 212,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #212 = G_BR
1076
    { 211,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #211 = G_LLROUND
1077
    { 210,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #210 = G_LROUND
1078
    { 209,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #209 = G_ABS
1079
    { 208,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #208 = G_UMAX
1080
    { 207,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #207 = G_UMIN
1081
    { 206,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #206 = G_SMAX
1082
    { 205,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #205 = G_SMIN
1083
    { 204,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #204 = G_PTRMASK
1084
    { 203,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #203 = G_PTR_ADD
1085
    { 202,  0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
1086
    { 201,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #201 = G_SET_FPMODE
1087
    { 200,  1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #200 = G_GET_FPMODE
1088
    { 199,  0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #199 = G_RESET_FPENV
1089
    { 198,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #198 = G_SET_FPENV
1090
    { 197,  1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #197 = G_GET_FPENV
1091
    { 196,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #196 = G_FMAXIMUM
1092
    { 195,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #195 = G_FMINIMUM
1093
    { 194,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
1094
    { 193,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
1095
    { 192,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #192 = G_FMAXNUM
1096
    { 191,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #191 = G_FMINNUM
1097
    { 190,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
1098
    { 189,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
1099
    { 188,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
1100
    { 187,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #187 = G_FABS
1101
    { 186,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #186 = G_UITOFP
1102
    { 185,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #185 = G_SITOFP
1103
    { 184,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #184 = G_FPTOUI
1104
    { 183,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #183 = G_FPTOSI
1105
    { 182,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #182 = G_FPTRUNC
1106
    { 181,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #181 = G_FPEXT
1107
    { 180,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #180 = G_FNEG
1108
    { 179,  3,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #179 = G_FFREXP
1109
    { 178,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #178 = G_FLDEXP
1110
    { 177,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #177 = G_FLOG10
1111
    { 176,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #176 = G_FLOG2
1112
    { 175,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #175 = G_FLOG
1113
    { 174,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #174 = G_FEXP10
1114
    { 173,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #173 = G_FEXP2
1115
    { 172,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #172 = G_FEXP
1116
    { 171,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #171 = G_FPOWI
1117
    { 170,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #170 = G_FPOW
1118
    { 169,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #169 = G_FREM
1119
    { 168,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #168 = G_FDIV
1120
    { 167,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #167 = G_FMAD
1121
    { 166,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #166 = G_FMA
1122
    { 165,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #165 = G_FMUL
1123
    { 164,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #164 = G_FSUB
1124
    { 163,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #163 = G_FADD
1125
    { 162,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
1126
    { 161,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
1127
    { 160,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #160 = G_UDIVFIX
1128
    { 159,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #159 = G_SDIVFIX
1129
    { 158,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
1130
    { 157,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
1131
    { 156,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #156 = G_UMULFIX
1132
    { 155,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #155 = G_SMULFIX
1133
    { 154,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #154 = G_SSHLSAT
1134
    { 153,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #153 = G_USHLSAT
1135
    { 152,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #152 = G_SSUBSAT
1136
    { 151,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #151 = G_USUBSAT
1137
    { 150,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #150 = G_SADDSAT
1138
    { 149,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #149 = G_UADDSAT
1139
    { 148,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #148 = G_SMULH
1140
    { 147,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #147 = G_UMULH
1141
    { 146,  4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #146 = G_SMULO
1142
    { 145,  4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #145 = G_UMULO
1143
    { 144,  5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #144 = G_SSUBE
1144
    { 143,  4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #143 = G_SSUBO
1145
    { 142,  5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #142 = G_SADDE
1146
    { 141,  4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #141 = G_SADDO
1147
    { 140,  5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #140 = G_USUBE
1148
    { 139,  4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #139 = G_USUBO
1149
    { 138,  5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #138 = G_UADDE
1150
    { 137,  4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #137 = G_UADDO
1151
    { 136,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #136 = G_SELECT
1152
    { 135,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #135 = G_FCMP
1153
    { 134,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #134 = G_ICMP
1154
    { 133,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #133 = G_ROTL
1155
    { 132,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #132 = G_ROTR
1156
    { 131,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #131 = G_FSHR
1157
    { 130,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #130 = G_FSHL
1158
    { 129,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #129 = G_ASHR
1159
    { 128,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #128 = G_LSHR
1160
    { 127,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #127 = G_SHL
1161
    { 126,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #126 = G_ZEXT
1162
    { 125,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #125 = G_SEXT_INREG
1163
    { 124,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #124 = G_SEXT
1164
    { 123,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #123 = G_VAARG
1165
    { 122,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #122 = G_VASTART
1166
    { 121,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #121 = G_FCONSTANT
1167
    { 120,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #120 = G_CONSTANT
1168
    { 119,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #119 = G_TRUNC
1169
    { 118,  2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #118 = G_ANYEXT
1170
    { 117,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1171
    { 116,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
1172
    { 115,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
1173
    { 114,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #114 = G_INTRINSIC
1174
    { 113,  0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
1175
    { 112,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #112 = G_BRINDIRECT
1176
    { 111,  2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #111 = G_BRCOND
1177
    { 110,  4,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #110 = G_PREFETCH
1178
    { 109,  2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #109 = G_FENCE
1179
    { 108,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
1180
    { 107,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
1181
    { 106,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
1182
    { 105,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
1183
    { 104,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
1184
    { 103,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
1185
    { 102,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
1186
    { 101,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
1187
    { 100,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
1188
    { 99, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
1189
    { 98, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
1190
    { 97, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
1191
    { 96, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
1192
    { 95, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
1193
    { 94, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
1194
    { 93, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
1195
    { 92, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
1196
    { 91, 4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
1197
    { 90, 5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1198
    { 89, 5,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
1199
    { 88, 2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #88 = G_STORE
1200
    { 87, 5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
1201
    { 86, 5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
1202
    { 85, 5,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
1203
    { 84, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
1204
    { 83, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #83 = G_SEXTLOAD
1205
    { 82, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #82 = G_LOAD
1206
    { 81, 1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
1207
    { 80, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
1208
    { 79, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
1209
    { 78, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
1210
    { 77, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
1211
    { 76, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
1212
    { 75, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
1213
    { 74, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #74 = G_FREEZE
1214
    { 73, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #73 = G_BITCAST
1215
    { 72, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #72 = G_INTTOPTR
1216
    { 71, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #71 = G_PTRTOINT
1217
    { 70, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
1218
    { 69, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
1219
    { 68, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
1220
    { 67, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
1221
    { 66, 4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #66 = G_INSERT
1222
    { 65, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
1223
    { 64, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #64 = G_EXTRACT
1224
    { 63, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
1225
    { 62, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
1226
    { 61, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
1227
    { 60, 1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #60 = G_PHI
1228
    { 59, 1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
1229
    { 58, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #58 = G_XOR
1230
    { 57, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #57 = G_OR
1231
    { 56, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #56 = G_AND
1232
    { 55, 4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #55 = G_UDIVREM
1233
    { 54, 4,  2,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #54 = G_SDIVREM
1234
    { 53, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #53 = G_UREM
1235
    { 52, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #52 = G_SREM
1236
    { 51, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #51 = G_UDIV
1237
    { 50, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #50 = G_SDIV
1238
    { 49, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #49 = G_MUL
1239
    { 48, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #48 = G_SUB
1240
    { 47, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #47 = G_ADD
1241
    { 46, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
1242
    { 45, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
1243
    { 44, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
1244
    { 43, 1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
1245
    { 42, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #42 = MEMBARRIER
1246
    { 41, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
1247
    { 40, 3,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1248
    { 39, 2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
1249
    { 38, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
1250
    { 37, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
1251
    { 36, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #36 = PATCHABLE_RET
1252
    { 35, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
1253
    { 34, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #34 = PATCHABLE_OP
1254
    { 33, 1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #33 = FAULTING_OP
1255
    { 32, 2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
1256
    { 31, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #31 = STATEPOINT
1257
    { 30, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
1258
    { 29, 1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
1259
    { 28, 1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
1260
    { 27, 6,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #27 = PATCHPOINT
1261
    { 26, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #26 = FENTRY_CALL
1262
    { 25, 2,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #25 = STACKMAP
1263
    { 24, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #24 = ARITH_FENCE
1264
    { 23, 4,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
1265
    { 22, 1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #22 = LIFETIME_END
1266
    { 21, 1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #21 = LIFETIME_START
1267
    { 20, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #20 = BUNDLE
1268
    { 19, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #19 = COPY
1269
    { 18, 2,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #18 = REG_SEQUENCE
1270
    { 17, 1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #17 = DBG_LABEL
1271
    { 16, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #16 = DBG_PHI
1272
    { 15, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
1273
    { 14, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
1274
    { 13, 0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #13 = DBG_VALUE
1275
    { 12, 3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
1276
    { 11, 4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  9,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
1277
    { 10, 1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
1278
    { 9,  4,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  5,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #9 = INSERT_SUBREG
1279
    { 8,  3,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
1280
    { 7,  0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #7 = KILL
1281
    { 6,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
1282
    { 5,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #5 = GC_LABEL
1283
    { 4,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #4 = EH_LABEL
1284
    { 3,  1,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
1285
    { 2,  0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #2 = INLINEASM_BR
1286
    { 1,  0,  0,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #1 = INLINEASM
1287
    { 0,  1,  1,  0,  0,  0,  0,  MSP430ImpOpBase + 0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL },  // Inst #0 = PHI
1288
  }, {
1289
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1290
    /* 1 */
1291
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1292
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1293
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1294
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1295
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1296
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1297
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1298
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1299
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1300
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1301
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1302
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1303
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1304
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1305
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1306
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1307
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1308
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1309
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1310
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1311
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1312
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1313
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1314
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1315
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1316
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1317
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1318
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1319
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1320
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1321
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1322
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1323
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1324
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1325
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1326
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1327
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1328
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1329
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1330
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1331
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1332
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1333
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1334
    /* 140 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1335
    /* 143 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1336
    /* 146 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1337
    /* 150 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1338
    /* 153 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1339
    /* 156 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1340
    /* 159 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1341
    /* 162 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1342
    /* 166 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1343
    /* 169 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1344
    /* 173 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1345
    /* 176 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1346
    /* 179 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1347
    /* 182 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1348
    /* 185 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1349
    /* 189 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1350
    /* 192 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1351
    /* 196 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1352
    /* 199 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1353
    /* 202 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1354
    /* 204 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1355
    /* 206 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1356
    /* 209 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1357
    /* 211 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1358
    /* 213 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1359
    /* 215 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1360
    /* 217 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1361
    /* 220 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1362
    /* 222 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1363
    /* 224 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1364
    /* 226 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1365
    /* 227 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 },
1366
    /* 228 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1367
    /* 231 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(1) },
1368
    /* 234 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1369
    /* 236 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1370
    /* 237 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1371
    /* 239 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1372
    /* 241 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1373
    /* 245 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1374
    /* 249 */ { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1375
    /* 252 */ { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { MSP430::GR8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1376
  }, {
1377
    /* 0 */
1378
    /* 0 */ MSP430::SR,
1379
    /* 1 */ MSP430::SR, MSP430::SR,
1380
    /* 3 */ MSP430::SP, MSP430::SR,
1381
    /* 5 */ MSP430::SP, MSP430::SP, MSP430::SR,
1382
    /* 8 */ MSP430::SP, MSP430::R11, MSP430::R12, MSP430::R13, MSP430::R14, MSP430::R15, MSP430::SR,
1383
    /* 15 */ MSP430::SP, MSP430::SP,
1384
  }
1385
};
1386
1387
1388
#ifdef __GNUC__
1389
#pragma GCC diagnostic push
1390
#pragma GCC diagnostic ignored "-Woverlength-strings"
1391
#endif
1392
extern const char MSP430InstrNameData[] = {
1393
  /* 0 */ "G_FLOG10\0"
1394
  /* 9 */ "G_FEXP10\0"
1395
  /* 18 */ "G_FLOG2\0"
1396
  /* 26 */ "G_FEXP2\0"
1397
  /* 34 */ "Sra16\0"
1398
  /* 40 */ "Rrcl16\0"
1399
  /* 47 */ "Shl16\0"
1400
  /* 53 */ "Srl16\0"
1401
  /* 59 */ "Select16\0"
1402
  /* 68 */ "Sra8\0"
1403
  /* 73 */ "Rrcl8\0"
1404
  /* 79 */ "Shl8\0"
1405
  /* 84 */ "Srl8\0"
1406
  /* 89 */ "MOVZX16rm8\0"
1407
  /* 100 */ "MOVZX16rr8\0"
1408
  /* 111 */ "Select8\0"
1409
  /* 119 */ "G_FMA\0"
1410
  /* 125 */ "G_STRICT_FMA\0"
1411
  /* 138 */ "G_FSUB\0"
1412
  /* 145 */ "G_STRICT_FSUB\0"
1413
  /* 159 */ "G_ATOMICRMW_FSUB\0"
1414
  /* 176 */ "G_SUB\0"
1415
  /* 182 */ "G_ATOMICRMW_SUB\0"
1416
  /* 198 */ "JCC\0"
1417
  /* 202 */ "G_INTRINSIC\0"
1418
  /* 214 */ "G_FPTRUNC\0"
1419
  /* 224 */ "G_INTRINSIC_TRUNC\0"
1420
  /* 242 */ "G_TRUNC\0"
1421
  /* 250 */ "G_BUILD_VECTOR_TRUNC\0"
1422
  /* 271 */ "G_DYN_STACKALLOC\0"
1423
  /* 288 */ "G_FMAD\0"
1424
  /* 295 */ "G_INDEXED_SEXTLOAD\0"
1425
  /* 314 */ "G_SEXTLOAD\0"
1426
  /* 325 */ "G_INDEXED_ZEXTLOAD\0"
1427
  /* 344 */ "G_ZEXTLOAD\0"
1428
  /* 355 */ "G_INDEXED_LOAD\0"
1429
  /* 370 */ "G_LOAD\0"
1430
  /* 377 */ "G_VECREDUCE_FADD\0"
1431
  /* 394 */ "G_FADD\0"
1432
  /* 401 */ "G_VECREDUCE_SEQ_FADD\0"
1433
  /* 422 */ "G_STRICT_FADD\0"
1434
  /* 436 */ "G_ATOMICRMW_FADD\0"
1435
  /* 453 */ "G_VECREDUCE_ADD\0"
1436
  /* 469 */ "G_ADD\0"
1437
  /* 475 */ "G_PTR_ADD\0"
1438
  /* 485 */ "G_ATOMICRMW_ADD\0"
1439
  /* 501 */ "G_ATOMICRMW_NAND\0"
1440
  /* 518 */ "G_VECREDUCE_AND\0"
1441
  /* 534 */ "G_AND\0"
1442
  /* 540 */ "G_ATOMICRMW_AND\0"
1443
  /* 556 */ "LIFETIME_END\0"
1444
  /* 569 */ "G_BRCOND\0"
1445
  /* 578 */ "G_LLROUND\0"
1446
  /* 588 */ "G_LROUND\0"
1447
  /* 597 */ "G_INTRINSIC_ROUND\0"
1448
  /* 615 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1449
  /* 641 */ "LOAD_STACK_GUARD\0"
1450
  /* 658 */ "PSEUDO_PROBE\0"
1451
  /* 671 */ "G_SSUBE\0"
1452
  /* 679 */ "G_USUBE\0"
1453
  /* 687 */ "G_FENCE\0"
1454
  /* 695 */ "ARITH_FENCE\0"
1455
  /* 707 */ "REG_SEQUENCE\0"
1456
  /* 720 */ "G_SADDE\0"
1457
  /* 728 */ "G_UADDE\0"
1458
  /* 736 */ "G_GET_FPMODE\0"
1459
  /* 749 */ "G_RESET_FPMODE\0"
1460
  /* 764 */ "G_SET_FPMODE\0"
1461
  /* 777 */ "G_FMINNUM_IEEE\0"
1462
  /* 792 */ "G_FMAXNUM_IEEE\0"
1463
  /* 807 */ "G_JUMP_TABLE\0"
1464
  /* 820 */ "BUNDLE\0"
1465
  /* 827 */ "G_MEMCPY_INLINE\0"
1466
  /* 843 */ "LOCAL_ESCAPE\0"
1467
  /* 856 */ "G_STACKRESTORE\0"
1468
  /* 871 */ "G_INDEXED_STORE\0"
1469
  /* 887 */ "G_STORE\0"
1470
  /* 895 */ "G_BITREVERSE\0"
1471
  /* 908 */ "DBG_VALUE\0"
1472
  /* 918 */ "G_GLOBAL_VALUE\0"
1473
  /* 933 */ "G_STACKSAVE\0"
1474
  /* 945 */ "G_MEMMOVE\0"
1475
  /* 955 */ "G_FREEZE\0"
1476
  /* 964 */ "G_FCANONICALIZE\0"
1477
  /* 980 */ "G_CTLZ_ZERO_UNDEF\0"
1478
  /* 998 */ "G_CTTZ_ZERO_UNDEF\0"
1479
  /* 1016 */ "G_IMPLICIT_DEF\0"
1480
  /* 1031 */ "DBG_INSTR_REF\0"
1481
  /* 1045 */ "G_FNEG\0"
1482
  /* 1052 */ "EXTRACT_SUBREG\0"
1483
  /* 1067 */ "INSERT_SUBREG\0"
1484
  /* 1081 */ "G_SEXT_INREG\0"
1485
  /* 1094 */ "SUBREG_TO_REG\0"
1486
  /* 1108 */ "G_ATOMIC_CMPXCHG\0"
1487
  /* 1125 */ "G_ATOMICRMW_XCHG\0"
1488
  /* 1142 */ "G_FLOG\0"
1489
  /* 1149 */ "G_VAARG\0"
1490
  /* 1157 */ "PREALLOCATED_ARG\0"
1491
  /* 1174 */ "G_PREFETCH\0"
1492
  /* 1185 */ "G_SMULH\0"
1493
  /* 1193 */ "G_UMULH\0"
1494
  /* 1201 */ "DBG_PHI\0"
1495
  /* 1209 */ "G_FPTOSI\0"
1496
  /* 1218 */ "RETI\0"
1497
  /* 1223 */ "G_FPTOUI\0"
1498
  /* 1232 */ "G_FPOWI\0"
1499
  /* 1240 */ "G_PTRMASK\0"
1500
  /* 1250 */ "GC_LABEL\0"
1501
  /* 1259 */ "DBG_LABEL\0"
1502
  /* 1269 */ "EH_LABEL\0"
1503
  /* 1278 */ "ANNOTATION_LABEL\0"
1504
  /* 1295 */ "ICALL_BRANCH_FUNNEL\0"
1505
  /* 1315 */ "G_FSHL\0"
1506
  /* 1322 */ "G_SHL\0"
1507
  /* 1328 */ "G_FCEIL\0"
1508
  /* 1336 */ "PATCHABLE_TAIL_CALL\0"
1509
  /* 1356 */ "PATCHABLE_TYPED_EVENT_CALL\0"
1510
  /* 1383 */ "PATCHABLE_EVENT_CALL\0"
1511
  /* 1404 */ "FENTRY_CALL\0"
1512
  /* 1416 */ "KILL\0"
1513
  /* 1421 */ "G_CONSTANT_POOL\0"
1514
  /* 1437 */ "G_ROTL\0"
1515
  /* 1444 */ "G_VECREDUCE_FMUL\0"
1516
  /* 1461 */ "G_FMUL\0"
1517
  /* 1468 */ "G_VECREDUCE_SEQ_FMUL\0"
1518
  /* 1489 */ "G_STRICT_FMUL\0"
1519
  /* 1503 */ "G_VECREDUCE_MUL\0"
1520
  /* 1519 */ "G_MUL\0"
1521
  /* 1525 */ "G_FREM\0"
1522
  /* 1532 */ "G_STRICT_FREM\0"
1523
  /* 1546 */ "G_SREM\0"
1524
  /* 1553 */ "G_UREM\0"
1525
  /* 1560 */ "G_SDIVREM\0"
1526
  /* 1570 */ "G_UDIVREM\0"
1527
  /* 1580 */ "INLINEASM\0"
1528
  /* 1590 */ "G_VECREDUCE_FMINIMUM\0"
1529
  /* 1611 */ "G_FMINIMUM\0"
1530
  /* 1622 */ "G_VECREDUCE_FMAXIMUM\0"
1531
  /* 1643 */ "G_FMAXIMUM\0"
1532
  /* 1654 */ "G_FMINNUM\0"
1533
  /* 1664 */ "G_FMAXNUM\0"
1534
  /* 1674 */ "G_INTRINSIC_ROUNDEVEN\0"
1535
  /* 1696 */ "G_ASSERT_ALIGN\0"
1536
  /* 1711 */ "G_FCOPYSIGN\0"
1537
  /* 1723 */ "G_VECREDUCE_FMIN\0"
1538
  /* 1740 */ "G_ATOMICRMW_FMIN\0"
1539
  /* 1757 */ "G_VECREDUCE_SMIN\0"
1540
  /* 1774 */ "G_SMIN\0"
1541
  /* 1781 */ "G_VECREDUCE_UMIN\0"
1542
  /* 1798 */ "G_UMIN\0"
1543
  /* 1805 */ "G_ATOMICRMW_UMIN\0"
1544
  /* 1822 */ "G_ATOMICRMW_MIN\0"
1545
  /* 1838 */ "G_FSIN\0"
1546
  /* 1845 */ "CFI_INSTRUCTION\0"
1547
  /* 1861 */ "ADJCALLSTACKDOWN\0"
1548
  /* 1878 */ "G_SSUBO\0"
1549
  /* 1886 */ "G_USUBO\0"
1550
  /* 1894 */ "G_SADDO\0"
1551
  /* 1902 */ "G_UADDO\0"
1552
  /* 1910 */ "JUMP_TABLE_DEBUG_INFO\0"
1553
  /* 1932 */ "G_SMULO\0"
1554
  /* 1940 */ "G_UMULO\0"
1555
  /* 1948 */ "G_BZERO\0"
1556
  /* 1956 */ "STACKMAP\0"
1557
  /* 1965 */ "G_ATOMICRMW_UDEC_WRAP\0"
1558
  /* 1987 */ "G_ATOMICRMW_UINC_WRAP\0"
1559
  /* 2009 */ "G_BSWAP\0"
1560
  /* 2017 */ "G_SITOFP\0"
1561
  /* 2026 */ "G_UITOFP\0"
1562
  /* 2035 */ "G_FCMP\0"
1563
  /* 2042 */ "G_ICMP\0"
1564
  /* 2049 */ "JMP\0"
1565
  /* 2053 */ "G_CTPOP\0"
1566
  /* 2061 */ "PATCHABLE_OP\0"
1567
  /* 2074 */ "FAULTING_OP\0"
1568
  /* 2086 */ "ADJCALLSTACKUP\0"
1569
  /* 2101 */ "PREALLOCATED_SETUP\0"
1570
  /* 2120 */ "G_FLDEXP\0"
1571
  /* 2129 */ "G_STRICT_FLDEXP\0"
1572
  /* 2145 */ "G_FEXP\0"
1573
  /* 2152 */ "G_FFREXP\0"
1574
  /* 2161 */ "G_BR\0"
1575
  /* 2166 */ "INLINEASM_BR\0"
1576
  /* 2179 */ "G_BLOCK_ADDR\0"
1577
  /* 2192 */ "MEMBARRIER\0"
1578
  /* 2203 */ "G_CONSTANT_FOLD_BARRIER\0"
1579
  /* 2227 */ "PATCHABLE_FUNCTION_ENTER\0"
1580
  /* 2252 */ "G_READCYCLECOUNTER\0"
1581
  /* 2271 */ "G_READ_REGISTER\0"
1582
  /* 2287 */ "G_WRITE_REGISTER\0"
1583
  /* 2304 */ "G_ASHR\0"
1584
  /* 2311 */ "G_FSHR\0"
1585
  /* 2318 */ "G_LSHR\0"
1586
  /* 2325 */ "G_FFLOOR\0"
1587
  /* 2334 */ "G_BUILD_VECTOR\0"
1588
  /* 2349 */ "G_SHUFFLE_VECTOR\0"
1589
  /* 2366 */ "G_VECREDUCE_XOR\0"
1590
  /* 2382 */ "G_XOR\0"
1591
  /* 2388 */ "G_ATOMICRMW_XOR\0"
1592
  /* 2404 */ "G_VECREDUCE_OR\0"
1593
  /* 2419 */ "G_OR\0"
1594
  /* 2424 */ "G_ATOMICRMW_OR\0"
1595
  /* 2439 */ "G_ROTR\0"
1596
  /* 2446 */ "G_INTTOPTR\0"
1597
  /* 2457 */ "G_FABS\0"
1598
  /* 2464 */ "G_ABS\0"
1599
  /* 2470 */ "G_UNMERGE_VALUES\0"
1600
  /* 2487 */ "G_MERGE_VALUES\0"
1601
  /* 2502 */ "G_FCOS\0"
1602
  /* 2509 */ "G_CONCAT_VECTORS\0"
1603
  /* 2526 */ "COPY_TO_REGCLASS\0"
1604
  /* 2543 */ "G_IS_FPCLASS\0"
1605
  /* 2556 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
1606
  /* 2586 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
1607
  /* 2613 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
1608
  /* 2651 */ "G_SSUBSAT\0"
1609
  /* 2661 */ "G_USUBSAT\0"
1610
  /* 2671 */ "G_SADDSAT\0"
1611
  /* 2681 */ "G_UADDSAT\0"
1612
  /* 2691 */ "G_SSHLSAT\0"
1613
  /* 2701 */ "G_USHLSAT\0"
1614
  /* 2711 */ "G_SMULFIXSAT\0"
1615
  /* 2724 */ "G_UMULFIXSAT\0"
1616
  /* 2737 */ "G_SDIVFIXSAT\0"
1617
  /* 2750 */ "G_UDIVFIXSAT\0"
1618
  /* 2763 */ "G_EXTRACT\0"
1619
  /* 2773 */ "G_SELECT\0"
1620
  /* 2782 */ "G_BRINDIRECT\0"
1621
  /* 2795 */ "PATCHABLE_RET\0"
1622
  /* 2809 */ "G_MEMSET\0"
1623
  /* 2818 */ "PATCHABLE_FUNCTION_EXIT\0"
1624
  /* 2842 */ "G_BRJT\0"
1625
  /* 2849 */ "G_EXTRACT_VECTOR_ELT\0"
1626
  /* 2870 */ "G_INSERT_VECTOR_ELT\0"
1627
  /* 2890 */ "G_FCONSTANT\0"
1628
  /* 2902 */ "G_CONSTANT\0"
1629
  /* 2913 */ "G_INTRINSIC_CONVERGENT\0"
1630
  /* 2936 */ "STATEPOINT\0"
1631
  /* 2947 */ "PATCHPOINT\0"
1632
  /* 2958 */ "G_PTRTOINT\0"
1633
  /* 2969 */ "G_FRINT\0"
1634
  /* 2977 */ "G_INTRINSIC_LRINT\0"
1635
  /* 2995 */ "G_FNEARBYINT\0"
1636
  /* 3008 */ "G_VASTART\0"
1637
  /* 3018 */ "LIFETIME_START\0"
1638
  /* 3033 */ "G_INVOKE_REGION_START\0"
1639
  /* 3055 */ "G_INSERT\0"
1640
  /* 3064 */ "G_FSQRT\0"
1641
  /* 3072 */ "G_STRICT_FSQRT\0"
1642
  /* 3087 */ "G_BITCAST\0"
1643
  /* 3097 */ "G_ADDRSPACE_CAST\0"
1644
  /* 3114 */ "DBG_VALUE_LIST\0"
1645
  /* 3129 */ "G_FPEXT\0"
1646
  /* 3137 */ "G_SEXT\0"
1647
  /* 3144 */ "G_ASSERT_SEXT\0"
1648
  /* 3158 */ "G_ANYEXT\0"
1649
  /* 3167 */ "G_ZEXT\0"
1650
  /* 3174 */ "G_ASSERT_ZEXT\0"
1651
  /* 3188 */ "G_FDIV\0"
1652
  /* 3195 */ "G_STRICT_FDIV\0"
1653
  /* 3209 */ "G_SDIV\0"
1654
  /* 3216 */ "G_UDIV\0"
1655
  /* 3223 */ "G_GET_FPENV\0"
1656
  /* 3235 */ "G_RESET_FPENV\0"
1657
  /* 3249 */ "G_SET_FPENV\0"
1658
  /* 3261 */ "G_FPOW\0"
1659
  /* 3268 */ "G_VECREDUCE_FMAX\0"
1660
  /* 3285 */ "G_ATOMICRMW_FMAX\0"
1661
  /* 3302 */ "G_VECREDUCE_SMAX\0"
1662
  /* 3319 */ "G_SMAX\0"
1663
  /* 3326 */ "G_VECREDUCE_UMAX\0"
1664
  /* 3343 */ "G_UMAX\0"
1665
  /* 3350 */ "G_ATOMICRMW_UMAX\0"
1666
  /* 3367 */ "G_ATOMICRMW_MAX\0"
1667
  /* 3383 */ "G_FRAME_INDEX\0"
1668
  /* 3397 */ "G_SBFX\0"
1669
  /* 3404 */ "G_UBFX\0"
1670
  /* 3411 */ "G_SMULFIX\0"
1671
  /* 3421 */ "G_UMULFIX\0"
1672
  /* 3431 */ "G_SDIVFIX\0"
1673
  /* 3441 */ "G_UDIVFIX\0"
1674
  /* 3451 */ "G_MEMCPY\0"
1675
  /* 3460 */ "COPY\0"
1676
  /* 3465 */ "G_CTLZ\0"
1677
  /* 3472 */ "G_CTTZ\0"
1678
  /* 3479 */ "PUSH16c\0"
1679
  /* 3487 */ "SUB16mc\0"
1680
  /* 3495 */ "SUBC16mc\0"
1681
  /* 3504 */ "ADDC16mc\0"
1682
  /* 3513 */ "BIC16mc\0"
1683
  /* 3521 */ "DADD16mc\0"
1684
  /* 3530 */ "AND16mc\0"
1685
  /* 3538 */ "CMP16mc\0"
1686
  /* 3546 */ "XOR16mc\0"
1687
  /* 3554 */ "BIS16mc\0"
1688
  /* 3562 */ "BIT16mc\0"
1689
  /* 3570 */ "MOV16mc\0"
1690
  /* 3578 */ "SUB8mc\0"
1691
  /* 3585 */ "SUBC8mc\0"
1692
  /* 3593 */ "ADDC8mc\0"
1693
  /* 3601 */ "BIC8mc\0"
1694
  /* 3608 */ "DADD8mc\0"
1695
  /* 3616 */ "AND8mc\0"
1696
  /* 3623 */ "CMP8mc\0"
1697
  /* 3630 */ "XOR8mc\0"
1698
  /* 3637 */ "BIS8mc\0"
1699
  /* 3644 */ "BIT8mc\0"
1700
  /* 3651 */ "MOV8mc\0"
1701
  /* 3658 */ "SUB16rc\0"
1702
  /* 3666 */ "SUBC16rc\0"
1703
  /* 3675 */ "ADDC16rc\0"
1704
  /* 3684 */ "BIC16rc\0"
1705
  /* 3692 */ "DADD16rc\0"
1706
  /* 3701 */ "AND16rc\0"
1707
  /* 3709 */ "CMP16rc\0"
1708
  /* 3717 */ "XOR16rc\0"
1709
  /* 3725 */ "BIS16rc\0"
1710
  /* 3733 */ "BIT16rc\0"
1711
  /* 3741 */ "MOV16rc\0"
1712
  /* 3749 */ "SUB8rc\0"
1713
  /* 3756 */ "SUBC8rc\0"
1714
  /* 3764 */ "ADDC8rc\0"
1715
  /* 3772 */ "BIC8rc\0"
1716
  /* 3779 */ "DADD8rc\0"
1717
  /* 3787 */ "AND8rc\0"
1718
  /* 3794 */ "CMP8rc\0"
1719
  /* 3801 */ "XOR8rc\0"
1720
  /* 3808 */ "BIS8rc\0"
1721
  /* 3815 */ "BIT8rc\0"
1722
  /* 3822 */ "MOV8rc\0"
1723
  /* 3829 */ "ADDframe\0"
1724
  /* 3838 */ "PUSH16i\0"
1725
  /* 3846 */ "Bi\0"
1726
  /* 3849 */ "CALLi\0"
1727
  /* 3855 */ "SUB16mi\0"
1728
  /* 3863 */ "SUBC16mi\0"
1729
  /* 3872 */ "ADDC16mi\0"
1730
  /* 3881 */ "BIC16mi\0"
1731
  /* 3889 */ "DADD16mi\0"
1732
  /* 3898 */ "AND16mi\0"
1733
  /* 3906 */ "CMP16mi\0"
1734
  /* 3914 */ "XOR16mi\0"
1735
  /* 3922 */ "BIS16mi\0"
1736
  /* 3930 */ "BIT16mi\0"
1737
  /* 3938 */ "MOV16mi\0"
1738
  /* 3946 */ "SUB8mi\0"
1739
  /* 3953 */ "SUBC8mi\0"
1740
  /* 3961 */ "ADDC8mi\0"
1741
  /* 3969 */ "BIC8mi\0"
1742
  /* 3976 */ "DADD8mi\0"
1743
  /* 3984 */ "AND8mi\0"
1744
  /* 3991 */ "CMP8mi\0"
1745
  /* 3998 */ "XOR8mi\0"
1746
  /* 4005 */ "BIS8mi\0"
1747
  /* 4012 */ "BIT8mi\0"
1748
  /* 4019 */ "MOV8mi\0"
1749
  /* 4026 */ "SUB16ri\0"
1750
  /* 4034 */ "SUBC16ri\0"
1751
  /* 4043 */ "ADDC16ri\0"
1752
  /* 4052 */ "BIC16ri\0"
1753
  /* 4060 */ "DADD16ri\0"
1754
  /* 4069 */ "AND16ri\0"
1755
  /* 4077 */ "CMP16ri\0"
1756
  /* 4085 */ "XOR16ri\0"
1757
  /* 4093 */ "BIS16ri\0"
1758
  /* 4101 */ "BIT16ri\0"
1759
  /* 4109 */ "MOV16ri\0"
1760
  /* 4117 */ "SUB8ri\0"
1761
  /* 4124 */ "SUBC8ri\0"
1762
  /* 4132 */ "ADDC8ri\0"
1763
  /* 4140 */ "BIC8ri\0"
1764
  /* 4147 */ "DADD8ri\0"
1765
  /* 4155 */ "AND8ri\0"
1766
  /* 4162 */ "CMP8ri\0"
1767
  /* 4169 */ "XOR8ri\0"
1768
  /* 4176 */ "BIS8ri\0"
1769
  /* 4183 */ "BIT8ri\0"
1770
  /* 4190 */ "MOV8ri\0"
1771
  /* 4197 */ "RRA16m\0"
1772
  /* 4204 */ "SWPB16m\0"
1773
  /* 4212 */ "RRC16m\0"
1774
  /* 4219 */ "SEXT16m\0"
1775
  /* 4227 */ "RRA8m\0"
1776
  /* 4233 */ "RRC8m\0"
1777
  /* 4239 */ "Bm\0"
1778
  /* 4242 */ "CALLm\0"
1779
  /* 4248 */ "SUB16mm\0"
1780
  /* 4256 */ "SUBC16mm\0"
1781
  /* 4265 */ "ADDC16mm\0"
1782
  /* 4274 */ "BIC16mm\0"
1783
  /* 4282 */ "DADD16mm\0"
1784
  /* 4291 */ "AND16mm\0"
1785
  /* 4299 */ "CMP16mm\0"
1786
  /* 4307 */ "XOR16mm\0"
1787
  /* 4315 */ "BIS16mm\0"
1788
  /* 4323 */ "BIT16mm\0"
1789
  /* 4331 */ "MOV16mm\0"
1790
  /* 4339 */ "SUB8mm\0"
1791
  /* 4346 */ "SUBC8mm\0"
1792
  /* 4354 */ "ADDC8mm\0"
1793
  /* 4362 */ "BIC8mm\0"
1794
  /* 4369 */ "DADD8mm\0"
1795
  /* 4377 */ "AND8mm\0"
1796
  /* 4384 */ "CMP8mm\0"
1797
  /* 4391 */ "XOR8mm\0"
1798
  /* 4398 */ "BIS8mm\0"
1799
  /* 4405 */ "BIT8mm\0"
1800
  /* 4412 */ "MOV8mm\0"
1801
  /* 4419 */ "SUB16rm\0"
1802
  /* 4427 */ "SUBC16rm\0"
1803
  /* 4436 */ "ADDC16rm\0"
1804
  /* 4445 */ "BIC16rm\0"
1805
  /* 4453 */ "DADD16rm\0"
1806
  /* 4462 */ "AND16rm\0"
1807
  /* 4470 */ "CMP16rm\0"
1808
  /* 4478 */ "XOR16rm\0"
1809
  /* 4486 */ "BIS16rm\0"
1810
  /* 4494 */ "BIT16rm\0"
1811
  /* 4502 */ "MOV16rm\0"
1812
  /* 4510 */ "SUB8rm\0"
1813
  /* 4517 */ "SUBC8rm\0"
1814
  /* 4525 */ "ADDC8rm\0"
1815
  /* 4533 */ "BIC8rm\0"
1816
  /* 4540 */ "DADD8rm\0"
1817
  /* 4548 */ "AND8rm\0"
1818
  /* 4555 */ "CMP8rm\0"
1819
  /* 4562 */ "XOR8rm\0"
1820
  /* 4569 */ "BIS8rm\0"
1821
  /* 4576 */ "BIT8rm\0"
1822
  /* 4583 */ "MOV8rm\0"
1823
  /* 4590 */ "RRA16n\0"
1824
  /* 4597 */ "SWPB16n\0"
1825
  /* 4605 */ "RRC16n\0"
1826
  /* 4612 */ "SEXT16n\0"
1827
  /* 4620 */ "RRA8n\0"
1828
  /* 4626 */ "RRC8n\0"
1829
  /* 4632 */ "CALLn\0"
1830
  /* 4638 */ "SUB16mn\0"
1831
  /* 4646 */ "SUBC16mn\0"
1832
  /* 4655 */ "ADDC16mn\0"
1833
  /* 4664 */ "BIC16mn\0"
1834
  /* 4672 */ "DADD16mn\0"
1835
  /* 4681 */ "AND16mn\0"
1836
  /* 4689 */ "CMP16mn\0"
1837
  /* 4697 */ "XOR16mn\0"
1838
  /* 4705 */ "BIS16mn\0"
1839
  /* 4713 */ "BIT16mn\0"
1840
  /* 4721 */ "MOV16mn\0"
1841
  /* 4729 */ "SUB8mn\0"
1842
  /* 4736 */ "SUBC8mn\0"
1843
  /* 4744 */ "ADDC8mn\0"
1844
  /* 4752 */ "BIC8mn\0"
1845
  /* 4759 */ "DADD8mn\0"
1846
  /* 4767 */ "AND8mn\0"
1847
  /* 4774 */ "CMP8mn\0"
1848
  /* 4781 */ "XOR8mn\0"
1849
  /* 4788 */ "BIS8mn\0"
1850
  /* 4795 */ "BIT8mn\0"
1851
  /* 4802 */ "MOV8mn\0"
1852
  /* 4809 */ "SUB16rn\0"
1853
  /* 4817 */ "SUBC16rn\0"
1854
  /* 4826 */ "ADDC16rn\0"
1855
  /* 4835 */ "BIC16rn\0"
1856
  /* 4843 */ "DADD16rn\0"
1857
  /* 4852 */ "AND16rn\0"
1858
  /* 4860 */ "CMP16rn\0"
1859
  /* 4868 */ "XOR16rn\0"
1860
  /* 4876 */ "BIS16rn\0"
1861
  /* 4884 */ "BIT16rn\0"
1862
  /* 4892 */ "MOV16rn\0"
1863
  /* 4900 */ "SUB8rn\0"
1864
  /* 4907 */ "SUBC8rn\0"
1865
  /* 4915 */ "ADDC8rn\0"
1866
  /* 4923 */ "BIC8rn\0"
1867
  /* 4930 */ "DADD8rn\0"
1868
  /* 4938 */ "AND8rn\0"
1869
  /* 4945 */ "CMP8rn\0"
1870
  /* 4952 */ "XOR8rn\0"
1871
  /* 4959 */ "BIS8rn\0"
1872
  /* 4966 */ "BIT8rn\0"
1873
  /* 4973 */ "MOV8rn\0"
1874
  /* 4980 */ "RRA16p\0"
1875
  /* 4987 */ "SWPB16p\0"
1876
  /* 4995 */ "RRC16p\0"
1877
  /* 5002 */ "SEXT16p\0"
1878
  /* 5010 */ "RRA8p\0"
1879
  /* 5016 */ "RRC8p\0"
1880
  /* 5022 */ "CALLp\0"
1881
  /* 5028 */ "SUB16mp\0"
1882
  /* 5036 */ "SUBC16mp\0"
1883
  /* 5045 */ "ADDC16mp\0"
1884
  /* 5054 */ "BIC16mp\0"
1885
  /* 5062 */ "DADD16mp\0"
1886
  /* 5071 */ "AND16mp\0"
1887
  /* 5079 */ "CMP16mp\0"
1888
  /* 5087 */ "XOR16mp\0"
1889
  /* 5095 */ "BIS16mp\0"
1890
  /* 5103 */ "BIT16mp\0"
1891
  /* 5111 */ "SUB8mp\0"
1892
  /* 5118 */ "SUBC8mp\0"
1893
  /* 5126 */ "ADDC8mp\0"
1894
  /* 5134 */ "BIC8mp\0"
1895
  /* 5141 */ "DADD8mp\0"
1896
  /* 5149 */ "AND8mp\0"
1897
  /* 5156 */ "CMP8mp\0"
1898
  /* 5163 */ "XOR8mp\0"
1899
  /* 5170 */ "BIS8mp\0"
1900
  /* 5177 */ "BIT8mp\0"
1901
  /* 5184 */ "SUB16rp\0"
1902
  /* 5192 */ "SUBC16rp\0"
1903
  /* 5201 */ "ADDC16rp\0"
1904
  /* 5210 */ "BIC16rp\0"
1905
  /* 5218 */ "DADD16rp\0"
1906
  /* 5227 */ "AND16rp\0"
1907
  /* 5235 */ "CMP16rp\0"
1908
  /* 5243 */ "XOR16rp\0"
1909
  /* 5251 */ "BIS16rp\0"
1910
  /* 5259 */ "BIT16rp\0"
1911
  /* 5267 */ "MOV16rp\0"
1912
  /* 5275 */ "SUB8rp\0"
1913
  /* 5282 */ "SUBC8rp\0"
1914
  /* 5290 */ "ADDC8rp\0"
1915
  /* 5298 */ "BIC8rp\0"
1916
  /* 5305 */ "DADD8rp\0"
1917
  /* 5313 */ "AND8rp\0"
1918
  /* 5320 */ "CMP8rp\0"
1919
  /* 5327 */ "XOR8rp\0"
1920
  /* 5334 */ "BIS8rp\0"
1921
  /* 5341 */ "BIT8rp\0"
1922
  /* 5348 */ "MOV8rp\0"
1923
  /* 5355 */ "RRA16r\0"
1924
  /* 5362 */ "SWPB16r\0"
1925
  /* 5370 */ "RRC16r\0"
1926
  /* 5377 */ "PUSH16r\0"
1927
  /* 5385 */ "POP16r\0"
1928
  /* 5392 */ "SEXT16r\0"
1929
  /* 5400 */ "ZEXT16r\0"
1930
  /* 5408 */ "RRA8r\0"
1931
  /* 5414 */ "RRC8r\0"
1932
  /* 5420 */ "PUSH8r\0"
1933
  /* 5427 */ "Br\0"
1934
  /* 5430 */ "CALLr\0"
1935
  /* 5436 */ "SUB16mr\0"
1936
  /* 5444 */ "SUBC16mr\0"
1937
  /* 5453 */ "ADDC16mr\0"
1938
  /* 5462 */ "BIC16mr\0"
1939
  /* 5470 */ "DADD16mr\0"
1940
  /* 5479 */ "AND16mr\0"
1941
  /* 5487 */ "CMP16mr\0"
1942
  /* 5495 */ "XOR16mr\0"
1943
  /* 5503 */ "BIS16mr\0"
1944
  /* 5511 */ "BIT16mr\0"
1945
  /* 5519 */ "MOV16mr\0"
1946
  /* 5527 */ "SUB8mr\0"
1947
  /* 5534 */ "SUBC8mr\0"
1948
  /* 5542 */ "ADDC8mr\0"
1949
  /* 5550 */ "BIC8mr\0"
1950
  /* 5557 */ "DADD8mr\0"
1951
  /* 5565 */ "AND8mr\0"
1952
  /* 5572 */ "CMP8mr\0"
1953
  /* 5579 */ "XOR8mr\0"
1954
  /* 5586 */ "BIS8mr\0"
1955
  /* 5593 */ "BIT8mr\0"
1956
  /* 5600 */ "MOV8mr\0"
1957
  /* 5607 */ "SUB16rr\0"
1958
  /* 5615 */ "SUBC16rr\0"
1959
  /* 5624 */ "ADDC16rr\0"
1960
  /* 5633 */ "BIC16rr\0"
1961
  /* 5641 */ "DADD16rr\0"
1962
  /* 5650 */ "AND16rr\0"
1963
  /* 5658 */ "CMP16rr\0"
1964
  /* 5666 */ "XOR16rr\0"
1965
  /* 5674 */ "BIS16rr\0"
1966
  /* 5682 */ "BIT16rr\0"
1967
  /* 5690 */ "MOV16rr\0"
1968
  /* 5698 */ "SUB8rr\0"
1969
  /* 5705 */ "SUBC8rr\0"
1970
  /* 5713 */ "ADDC8rr\0"
1971
  /* 5721 */ "BIC8rr\0"
1972
  /* 5728 */ "DADD8rr\0"
1973
  /* 5736 */ "AND8rr\0"
1974
  /* 5743 */ "CMP8rr\0"
1975
  /* 5750 */ "XOR8rr\0"
1976
  /* 5757 */ "BIS8rr\0"
1977
  /* 5764 */ "BIT8rr\0"
1978
  /* 5771 */ "MOV8rr\0"
1979
};
1980
#ifdef __GNUC__
1981
#pragma GCC diagnostic pop
1982
#endif
1983
1984
extern const unsigned MSP430InstrNameIndices[] = {
1985
    1205U, 1580U, 2166U, 1845U, 1269U, 1250U, 1278U, 1416U, 
1986
    1052U, 1067U, 1018U, 1094U, 2526U, 908U, 3114U, 1031U, 
1987
    1201U, 1259U, 707U, 3460U, 820U, 3018U, 556U, 658U, 
1988
    695U, 1956U, 1404U, 2947U, 641U, 2101U, 1157U, 2936U, 
1989
    843U, 2074U, 2061U, 2227U, 2795U, 2818U, 1336U, 1383U, 
1990
    1356U, 1295U, 2192U, 1910U, 3144U, 3174U, 1696U, 469U, 
1991
    176U, 1519U, 3209U, 3216U, 1546U, 1553U, 1560U, 1570U, 
1992
    534U, 2419U, 2382U, 1016U, 1203U, 3383U, 918U, 1421U, 
1993
    2763U, 2470U, 3055U, 2487U, 2334U, 250U, 2509U, 2958U, 
1994
    2446U, 3087U, 955U, 2203U, 615U, 224U, 597U, 2977U, 
1995
    1674U, 2252U, 370U, 314U, 344U, 355U, 295U, 325U, 
1996
    887U, 871U, 2556U, 1108U, 1125U, 485U, 182U, 540U, 
1997
    501U, 2424U, 2388U, 3367U, 1822U, 3350U, 1805U, 436U, 
1998
    159U, 3285U, 1740U, 1987U, 1965U, 687U, 1174U, 569U, 
1999
    2782U, 3033U, 202U, 2586U, 2913U, 2613U, 3158U, 242U, 
2000
    2902U, 2890U, 3008U, 1149U, 3137U, 1081U, 3167U, 1322U, 
2001
    2318U, 2304U, 1315U, 2311U, 2439U, 1437U, 2042U, 2035U, 
2002
    2773U, 1902U, 728U, 1886U, 679U, 1894U, 720U, 1878U, 
2003
    671U, 1940U, 1932U, 1193U, 1185U, 2681U, 2671U, 2661U, 
2004
    2651U, 2701U, 2691U, 3411U, 3421U, 2711U, 2724U, 3431U, 
2005
    3441U, 2737U, 2750U, 394U, 138U, 1461U, 119U, 288U, 
2006
    3188U, 1525U, 3261U, 1232U, 2145U, 26U, 9U, 1142U, 
2007
    18U, 0U, 2120U, 2152U, 1045U, 3129U, 214U, 1209U, 
2008
    1223U, 2017U, 2026U, 2457U, 1711U, 2543U, 964U, 1654U, 
2009
    1664U, 777U, 792U, 1611U, 1643U, 3223U, 3249U, 3235U, 
2010
    736U, 764U, 749U, 475U, 1240U, 1774U, 3319U, 1798U, 
2011
    3343U, 2464U, 588U, 578U, 2161U, 2842U, 2870U, 2849U, 
2012
    2349U, 3472U, 998U, 3465U, 980U, 2053U, 2009U, 895U, 
2013
    1328U, 2502U, 1838U, 3064U, 2325U, 2969U, 2995U, 3097U, 
2014
    2179U, 807U, 271U, 933U, 856U, 422U, 145U, 1489U, 
2015
    3195U, 1532U, 125U, 3072U, 2129U, 2271U, 2287U, 3451U, 
2016
    827U, 945U, 2809U, 1948U, 401U, 1468U, 377U, 1444U, 
2017
    3268U, 1723U, 1622U, 1590U, 453U, 1503U, 518U, 2404U, 
2018
    2366U, 3302U, 1757U, 3326U, 1781U, 3397U, 3404U, 3522U, 
2019
    3890U, 4283U, 4673U, 5063U, 5471U, 3693U, 4061U, 4454U, 
2020
    4844U, 5219U, 5642U, 3609U, 3977U, 4370U, 4760U, 5142U, 
2021
    5558U, 3780U, 4148U, 4541U, 4931U, 5306U, 5729U, 3504U, 
2022
    3872U, 4265U, 4655U, 5045U, 5453U, 3675U, 4043U, 4436U, 
2023
    4826U, 5201U, 5624U, 3593U, 3961U, 4354U, 4744U, 5126U, 
2024
    5542U, 3764U, 4132U, 4525U, 4915U, 5290U, 5713U, 3829U, 
2025
    1861U, 2086U, 3530U, 3898U, 4291U, 4681U, 5071U, 5479U, 
2026
    3701U, 4069U, 4462U, 4852U, 5227U, 5650U, 3616U, 3984U, 
2027
    4377U, 4767U, 5149U, 5565U, 3787U, 4155U, 4548U, 4938U, 
2028
    5313U, 5736U, 3513U, 3881U, 4274U, 4664U, 5054U, 5462U, 
2029
    3684U, 4052U, 4445U, 4835U, 5210U, 5633U, 3601U, 3969U, 
2030
    4362U, 4752U, 5134U, 5550U, 3772U, 4140U, 4533U, 4923U, 
2031
    5298U, 5721U, 3554U, 3922U, 4315U, 4705U, 5095U, 5503U, 
2032
    3725U, 4093U, 4486U, 4876U, 5251U, 5674U, 3637U, 4005U, 
2033
    4398U, 4788U, 5170U, 5586U, 3808U, 4176U, 4569U, 4959U, 
2034
    5334U, 5757U, 3562U, 3930U, 4323U, 4713U, 5103U, 5511U, 
2035
    3733U, 4101U, 4494U, 4884U, 5259U, 5682U, 3644U, 4012U, 
2036
    4405U, 4795U, 5177U, 5593U, 3815U, 4183U, 4576U, 4966U, 
2037
    5341U, 5764U, 3846U, 4239U, 5427U, 3849U, 4242U, 4632U, 
2038
    5022U, 5430U, 3538U, 3906U, 4299U, 4689U, 5079U, 5487U, 
2039
    3709U, 4077U, 4470U, 4860U, 5235U, 5658U, 3623U, 3991U, 
2040
    4384U, 4774U, 5156U, 5572U, 3794U, 4162U, 4555U, 4945U, 
2041
    5320U, 5743U, 3521U, 3889U, 4282U, 4672U, 5062U, 5470U, 
2042
    3692U, 4060U, 4453U, 4843U, 5218U, 5641U, 3608U, 3976U, 
2043
    4369U, 4759U, 5141U, 5557U, 3779U, 4147U, 4540U, 4930U, 
2044
    5305U, 5728U, 198U, 2049U, 3570U, 3938U, 4331U, 4721U, 
2045
    5519U, 3741U, 4109U, 4502U, 4892U, 5267U, 5690U, 3651U, 
2046
    4019U, 4412U, 4802U, 5600U, 3822U, 4190U, 4583U, 4973U, 
2047
    5348U, 5771U, 89U, 100U, 5385U, 3479U, 3838U, 5377U, 
2048
    5420U, 2805U, 1218U, 4197U, 4590U, 4980U, 5355U, 4227U, 
2049
    4620U, 5010U, 5408U, 4212U, 4605U, 4995U, 5370U, 4233U, 
2050
    4626U, 5016U, 5414U, 40U, 73U, 4219U, 4612U, 5002U, 
2051
    5392U, 3487U, 3855U, 4248U, 4638U, 5028U, 5436U, 3658U, 
2052
    4026U, 4419U, 4809U, 5184U, 5607U, 3578U, 3946U, 4339U, 
2053
    4729U, 5111U, 5527U, 3749U, 4117U, 4510U, 4900U, 5275U, 
2054
    5698U, 3495U, 3863U, 4256U, 4646U, 5036U, 5444U, 3666U, 
2055
    4034U, 4427U, 4817U, 5192U, 5615U, 3585U, 3953U, 4346U, 
2056
    4736U, 5118U, 5534U, 3756U, 4124U, 4517U, 4907U, 5282U, 
2057
    5705U, 4204U, 4597U, 4987U, 5362U, 59U, 111U, 47U, 
2058
    79U, 34U, 68U, 53U, 84U, 3546U, 3914U, 4307U, 
2059
    4697U, 5087U, 5495U, 3717U, 4085U, 4478U, 4868U, 5243U, 
2060
    5666U, 3630U, 3998U, 4391U, 4781U, 5163U, 5579U, 3801U, 
2061
    4169U, 4562U, 4952U, 5327U, 5750U, 5400U, 
2062
};
2063
2064
0
static inline void InitMSP430MCInstrInfo(MCInstrInfo *II) {
2065
0
  II->InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 614);
2066
0
}
2067
2068
} // end namespace llvm
2069
#endif // GET_INSTRINFO_MC_DESC
2070
2071
#ifdef GET_INSTRINFO_HEADER
2072
#undef GET_INSTRINFO_HEADER
2073
namespace llvm {
2074
struct MSP430GenInstrInfo : public TargetInstrInfo {
2075
  explicit MSP430GenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2076
  ~MSP430GenInstrInfo() override = default;
2077
2078
};
2079
} // end namespace llvm
2080
#endif // GET_INSTRINFO_HEADER
2081
2082
#ifdef GET_INSTRINFO_HELPER_DECLS
2083
#undef GET_INSTRINFO_HELPER_DECLS
2084
2085
2086
#endif // GET_INSTRINFO_HELPER_DECLS
2087
2088
#ifdef GET_INSTRINFO_HELPERS
2089
#undef GET_INSTRINFO_HELPERS
2090
2091
#endif // GET_INSTRINFO_HELPERS
2092
2093
#ifdef GET_INSTRINFO_CTOR_DTOR
2094
#undef GET_INSTRINFO_CTOR_DTOR
2095
namespace llvm {
2096
extern const MSP430InstrTable MSP430Descs;
2097
extern const unsigned MSP430InstrNameIndices[];
2098
extern const char MSP430InstrNameData[];
2099
MSP430GenInstrInfo::MSP430GenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2100
0
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2101
0
  InitMCInstrInfo(MSP430Descs.Insts, MSP430InstrNameIndices, MSP430InstrNameData, nullptr, nullptr, 614);
2102
0
}
2103
} // end namespace llvm
2104
#endif // GET_INSTRINFO_CTOR_DTOR
2105
2106
#ifdef GET_INSTRINFO_OPERAND_ENUM
2107
#undef GET_INSTRINFO_OPERAND_ENUM
2108
namespace llvm {
2109
namespace MSP430 {
2110
namespace OpName {
2111
enum {
2112
  OPERAND_LAST
2113
};
2114
} // end namespace OpName
2115
} // end namespace MSP430
2116
} // end namespace llvm
2117
#endif //GET_INSTRINFO_OPERAND_ENUM
2118
2119
#ifdef GET_INSTRINFO_NAMED_OPS
2120
#undef GET_INSTRINFO_NAMED_OPS
2121
namespace llvm {
2122
namespace MSP430 {
2123
LLVM_READONLY
2124
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
2125
  return -1;
2126
}
2127
} // end namespace MSP430
2128
} // end namespace llvm
2129
#endif //GET_INSTRINFO_NAMED_OPS
2130
2131
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
2132
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
2133
namespace llvm {
2134
namespace MSP430 {
2135
namespace OpTypes {
2136
enum OperandType {
2137
  cc = 0,
2138
  cg8imm = 1,
2139
  cg16imm = 2,
2140
  f32imm = 3,
2141
  f64imm = 4,
2142
  i1imm = 5,
2143
  i8imm = 6,
2144
  i16imm = 7,
2145
  i32imm = 8,
2146
  i64imm = 9,
2147
  indreg = 10,
2148
  jmptarget = 11,
2149
  memdst = 12,
2150
  memsrc = 13,
2151
  postreg = 14,
2152
  ptype0 = 15,
2153
  ptype1 = 16,
2154
  ptype2 = 17,
2155
  ptype3 = 18,
2156
  ptype4 = 19,
2157
  ptype5 = 20,
2158
  type0 = 21,
2159
  type1 = 22,
2160
  type2 = 23,
2161
  type3 = 24,
2162
  type4 = 25,
2163
  type5 = 26,
2164
  untyped_imm_0 = 27,
2165
  GR8 = 28,
2166
  GR16 = 29,
2167
  OPERAND_TYPE_LIST_END
2168
};
2169
} // end namespace OpTypes
2170
} // end namespace MSP430
2171
} // end namespace llvm
2172
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2173
2174
#ifdef GET_INSTRINFO_OPERAND_TYPE
2175
#undef GET_INSTRINFO_OPERAND_TYPE
2176
namespace llvm {
2177
namespace MSP430 {
2178
LLVM_READONLY
2179
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
2180
  static const uint16_t Offsets[] = {
2181
    /* PHI */
2182
    0,
2183
    /* INLINEASM */
2184
    1,
2185
    /* INLINEASM_BR */
2186
    1,
2187
    /* CFI_INSTRUCTION */
2188
    1,
2189
    /* EH_LABEL */
2190
    2,
2191
    /* GC_LABEL */
2192
    3,
2193
    /* ANNOTATION_LABEL */
2194
    4,
2195
    /* KILL */
2196
    5,
2197
    /* EXTRACT_SUBREG */
2198
    5,
2199
    /* INSERT_SUBREG */
2200
    8,
2201
    /* IMPLICIT_DEF */
2202
    12,
2203
    /* SUBREG_TO_REG */
2204
    13,
2205
    /* COPY_TO_REGCLASS */
2206
    17,
2207
    /* DBG_VALUE */
2208
    20,
2209
    /* DBG_VALUE_LIST */
2210
    20,
2211
    /* DBG_INSTR_REF */
2212
    20,
2213
    /* DBG_PHI */
2214
    20,
2215
    /* DBG_LABEL */
2216
    20,
2217
    /* REG_SEQUENCE */
2218
    21,
2219
    /* COPY */
2220
    23,
2221
    /* BUNDLE */
2222
    25,
2223
    /* LIFETIME_START */
2224
    25,
2225
    /* LIFETIME_END */
2226
    26,
2227
    /* PSEUDO_PROBE */
2228
    27,
2229
    /* ARITH_FENCE */
2230
    31,
2231
    /* STACKMAP */
2232
    33,
2233
    /* FENTRY_CALL */
2234
    35,
2235
    /* PATCHPOINT */
2236
    35,
2237
    /* LOAD_STACK_GUARD */
2238
    41,
2239
    /* PREALLOCATED_SETUP */
2240
    42,
2241
    /* PREALLOCATED_ARG */
2242
    43,
2243
    /* STATEPOINT */
2244
    46,
2245
    /* LOCAL_ESCAPE */
2246
    46,
2247
    /* FAULTING_OP */
2248
    48,
2249
    /* PATCHABLE_OP */
2250
    49,
2251
    /* PATCHABLE_FUNCTION_ENTER */
2252
    49,
2253
    /* PATCHABLE_RET */
2254
    49,
2255
    /* PATCHABLE_FUNCTION_EXIT */
2256
    49,
2257
    /* PATCHABLE_TAIL_CALL */
2258
    49,
2259
    /* PATCHABLE_EVENT_CALL */
2260
    49,
2261
    /* PATCHABLE_TYPED_EVENT_CALL */
2262
    51,
2263
    /* ICALL_BRANCH_FUNNEL */
2264
    54,
2265
    /* MEMBARRIER */
2266
    54,
2267
    /* JUMP_TABLE_DEBUG_INFO */
2268
    54,
2269
    /* G_ASSERT_SEXT */
2270
    55,
2271
    /* G_ASSERT_ZEXT */
2272
    58,
2273
    /* G_ASSERT_ALIGN */
2274
    61,
2275
    /* G_ADD */
2276
    64,
2277
    /* G_SUB */
2278
    67,
2279
    /* G_MUL */
2280
    70,
2281
    /* G_SDIV */
2282
    73,
2283
    /* G_UDIV */
2284
    76,
2285
    /* G_SREM */
2286
    79,
2287
    /* G_UREM */
2288
    82,
2289
    /* G_SDIVREM */
2290
    85,
2291
    /* G_UDIVREM */
2292
    89,
2293
    /* G_AND */
2294
    93,
2295
    /* G_OR */
2296
    96,
2297
    /* G_XOR */
2298
    99,
2299
    /* G_IMPLICIT_DEF */
2300
    102,
2301
    /* G_PHI */
2302
    103,
2303
    /* G_FRAME_INDEX */
2304
    104,
2305
    /* G_GLOBAL_VALUE */
2306
    106,
2307
    /* G_CONSTANT_POOL */
2308
    108,
2309
    /* G_EXTRACT */
2310
    110,
2311
    /* G_UNMERGE_VALUES */
2312
    113,
2313
    /* G_INSERT */
2314
    115,
2315
    /* G_MERGE_VALUES */
2316
    119,
2317
    /* G_BUILD_VECTOR */
2318
    121,
2319
    /* G_BUILD_VECTOR_TRUNC */
2320
    123,
2321
    /* G_CONCAT_VECTORS */
2322
    125,
2323
    /* G_PTRTOINT */
2324
    127,
2325
    /* G_INTTOPTR */
2326
    129,
2327
    /* G_BITCAST */
2328
    131,
2329
    /* G_FREEZE */
2330
    133,
2331
    /* G_CONSTANT_FOLD_BARRIER */
2332
    135,
2333
    /* G_INTRINSIC_FPTRUNC_ROUND */
2334
    137,
2335
    /* G_INTRINSIC_TRUNC */
2336
    140,
2337
    /* G_INTRINSIC_ROUND */
2338
    142,
2339
    /* G_INTRINSIC_LRINT */
2340
    144,
2341
    /* G_INTRINSIC_ROUNDEVEN */
2342
    146,
2343
    /* G_READCYCLECOUNTER */
2344
    148,
2345
    /* G_LOAD */
2346
    149,
2347
    /* G_SEXTLOAD */
2348
    151,
2349
    /* G_ZEXTLOAD */
2350
    153,
2351
    /* G_INDEXED_LOAD */
2352
    155,
2353
    /* G_INDEXED_SEXTLOAD */
2354
    160,
2355
    /* G_INDEXED_ZEXTLOAD */
2356
    165,
2357
    /* G_STORE */
2358
    170,
2359
    /* G_INDEXED_STORE */
2360
    172,
2361
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
2362
    177,
2363
    /* G_ATOMIC_CMPXCHG */
2364
    182,
2365
    /* G_ATOMICRMW_XCHG */
2366
    186,
2367
    /* G_ATOMICRMW_ADD */
2368
    189,
2369
    /* G_ATOMICRMW_SUB */
2370
    192,
2371
    /* G_ATOMICRMW_AND */
2372
    195,
2373
    /* G_ATOMICRMW_NAND */
2374
    198,
2375
    /* G_ATOMICRMW_OR */
2376
    201,
2377
    /* G_ATOMICRMW_XOR */
2378
    204,
2379
    /* G_ATOMICRMW_MAX */
2380
    207,
2381
    /* G_ATOMICRMW_MIN */
2382
    210,
2383
    /* G_ATOMICRMW_UMAX */
2384
    213,
2385
    /* G_ATOMICRMW_UMIN */
2386
    216,
2387
    /* G_ATOMICRMW_FADD */
2388
    219,
2389
    /* G_ATOMICRMW_FSUB */
2390
    222,
2391
    /* G_ATOMICRMW_FMAX */
2392
    225,
2393
    /* G_ATOMICRMW_FMIN */
2394
    228,
2395
    /* G_ATOMICRMW_UINC_WRAP */
2396
    231,
2397
    /* G_ATOMICRMW_UDEC_WRAP */
2398
    234,
2399
    /* G_FENCE */
2400
    237,
2401
    /* G_PREFETCH */
2402
    239,
2403
    /* G_BRCOND */
2404
    243,
2405
    /* G_BRINDIRECT */
2406
    245,
2407
    /* G_INVOKE_REGION_START */
2408
    246,
2409
    /* G_INTRINSIC */
2410
    246,
2411
    /* G_INTRINSIC_W_SIDE_EFFECTS */
2412
    247,
2413
    /* G_INTRINSIC_CONVERGENT */
2414
    248,
2415
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
2416
    249,
2417
    /* G_ANYEXT */
2418
    250,
2419
    /* G_TRUNC */
2420
    252,
2421
    /* G_CONSTANT */
2422
    254,
2423
    /* G_FCONSTANT */
2424
    256,
2425
    /* G_VASTART */
2426
    258,
2427
    /* G_VAARG */
2428
    259,
2429
    /* G_SEXT */
2430
    262,
2431
    /* G_SEXT_INREG */
2432
    264,
2433
    /* G_ZEXT */
2434
    267,
2435
    /* G_SHL */
2436
    269,
2437
    /* G_LSHR */
2438
    272,
2439
    /* G_ASHR */
2440
    275,
2441
    /* G_FSHL */
2442
    278,
2443
    /* G_FSHR */
2444
    282,
2445
    /* G_ROTR */
2446
    286,
2447
    /* G_ROTL */
2448
    289,
2449
    /* G_ICMP */
2450
    292,
2451
    /* G_FCMP */
2452
    296,
2453
    /* G_SELECT */
2454
    300,
2455
    /* G_UADDO */
2456
    304,
2457
    /* G_UADDE */
2458
    308,
2459
    /* G_USUBO */
2460
    313,
2461
    /* G_USUBE */
2462
    317,
2463
    /* G_SADDO */
2464
    322,
2465
    /* G_SADDE */
2466
    326,
2467
    /* G_SSUBO */
2468
    331,
2469
    /* G_SSUBE */
2470
    335,
2471
    /* G_UMULO */
2472
    340,
2473
    /* G_SMULO */
2474
    344,
2475
    /* G_UMULH */
2476
    348,
2477
    /* G_SMULH */
2478
    351,
2479
    /* G_UADDSAT */
2480
    354,
2481
    /* G_SADDSAT */
2482
    357,
2483
    /* G_USUBSAT */
2484
    360,
2485
    /* G_SSUBSAT */
2486
    363,
2487
    /* G_USHLSAT */
2488
    366,
2489
    /* G_SSHLSAT */
2490
    369,
2491
    /* G_SMULFIX */
2492
    372,
2493
    /* G_UMULFIX */
2494
    376,
2495
    /* G_SMULFIXSAT */
2496
    380,
2497
    /* G_UMULFIXSAT */
2498
    384,
2499
    /* G_SDIVFIX */
2500
    388,
2501
    /* G_UDIVFIX */
2502
    392,
2503
    /* G_SDIVFIXSAT */
2504
    396,
2505
    /* G_UDIVFIXSAT */
2506
    400,
2507
    /* G_FADD */
2508
    404,
2509
    /* G_FSUB */
2510
    407,
2511
    /* G_FMUL */
2512
    410,
2513
    /* G_FMA */
2514
    413,
2515
    /* G_FMAD */
2516
    417,
2517
    /* G_FDIV */
2518
    421,
2519
    /* G_FREM */
2520
    424,
2521
    /* G_FPOW */
2522
    427,
2523
    /* G_FPOWI */
2524
    430,
2525
    /* G_FEXP */
2526
    433,
2527
    /* G_FEXP2 */
2528
    435,
2529
    /* G_FEXP10 */
2530
    437,
2531
    /* G_FLOG */
2532
    439,
2533
    /* G_FLOG2 */
2534
    441,
2535
    /* G_FLOG10 */
2536
    443,
2537
    /* G_FLDEXP */
2538
    445,
2539
    /* G_FFREXP */
2540
    448,
2541
    /* G_FNEG */
2542
    451,
2543
    /* G_FPEXT */
2544
    453,
2545
    /* G_FPTRUNC */
2546
    455,
2547
    /* G_FPTOSI */
2548
    457,
2549
    /* G_FPTOUI */
2550
    459,
2551
    /* G_SITOFP */
2552
    461,
2553
    /* G_UITOFP */
2554
    463,
2555
    /* G_FABS */
2556
    465,
2557
    /* G_FCOPYSIGN */
2558
    467,
2559
    /* G_IS_FPCLASS */
2560
    470,
2561
    /* G_FCANONICALIZE */
2562
    473,
2563
    /* G_FMINNUM */
2564
    475,
2565
    /* G_FMAXNUM */
2566
    478,
2567
    /* G_FMINNUM_IEEE */
2568
    481,
2569
    /* G_FMAXNUM_IEEE */
2570
    484,
2571
    /* G_FMINIMUM */
2572
    487,
2573
    /* G_FMAXIMUM */
2574
    490,
2575
    /* G_GET_FPENV */
2576
    493,
2577
    /* G_SET_FPENV */
2578
    494,
2579
    /* G_RESET_FPENV */
2580
    495,
2581
    /* G_GET_FPMODE */
2582
    495,
2583
    /* G_SET_FPMODE */
2584
    496,
2585
    /* G_RESET_FPMODE */
2586
    497,
2587
    /* G_PTR_ADD */
2588
    497,
2589
    /* G_PTRMASK */
2590
    500,
2591
    /* G_SMIN */
2592
    503,
2593
    /* G_SMAX */
2594
    506,
2595
    /* G_UMIN */
2596
    509,
2597
    /* G_UMAX */
2598
    512,
2599
    /* G_ABS */
2600
    515,
2601
    /* G_LROUND */
2602
    517,
2603
    /* G_LLROUND */
2604
    519,
2605
    /* G_BR */
2606
    521,
2607
    /* G_BRJT */
2608
    522,
2609
    /* G_INSERT_VECTOR_ELT */
2610
    525,
2611
    /* G_EXTRACT_VECTOR_ELT */
2612
    529,
2613
    /* G_SHUFFLE_VECTOR */
2614
    532,
2615
    /* G_CTTZ */
2616
    536,
2617
    /* G_CTTZ_ZERO_UNDEF */
2618
    538,
2619
    /* G_CTLZ */
2620
    540,
2621
    /* G_CTLZ_ZERO_UNDEF */
2622
    542,
2623
    /* G_CTPOP */
2624
    544,
2625
    /* G_BSWAP */
2626
    546,
2627
    /* G_BITREVERSE */
2628
    548,
2629
    /* G_FCEIL */
2630
    550,
2631
    /* G_FCOS */
2632
    552,
2633
    /* G_FSIN */
2634
    554,
2635
    /* G_FSQRT */
2636
    556,
2637
    /* G_FFLOOR */
2638
    558,
2639
    /* G_FRINT */
2640
    560,
2641
    /* G_FNEARBYINT */
2642
    562,
2643
    /* G_ADDRSPACE_CAST */
2644
    564,
2645
    /* G_BLOCK_ADDR */
2646
    566,
2647
    /* G_JUMP_TABLE */
2648
    568,
2649
    /* G_DYN_STACKALLOC */
2650
    570,
2651
    /* G_STACKSAVE */
2652
    573,
2653
    /* G_STACKRESTORE */
2654
    574,
2655
    /* G_STRICT_FADD */
2656
    575,
2657
    /* G_STRICT_FSUB */
2658
    578,
2659
    /* G_STRICT_FMUL */
2660
    581,
2661
    /* G_STRICT_FDIV */
2662
    584,
2663
    /* G_STRICT_FREM */
2664
    587,
2665
    /* G_STRICT_FMA */
2666
    590,
2667
    /* G_STRICT_FSQRT */
2668
    594,
2669
    /* G_STRICT_FLDEXP */
2670
    596,
2671
    /* G_READ_REGISTER */
2672
    599,
2673
    /* G_WRITE_REGISTER */
2674
    601,
2675
    /* G_MEMCPY */
2676
    603,
2677
    /* G_MEMCPY_INLINE */
2678
    607,
2679
    /* G_MEMMOVE */
2680
    610,
2681
    /* G_MEMSET */
2682
    614,
2683
    /* G_BZERO */
2684
    618,
2685
    /* G_VECREDUCE_SEQ_FADD */
2686
    621,
2687
    /* G_VECREDUCE_SEQ_FMUL */
2688
    624,
2689
    /* G_VECREDUCE_FADD */
2690
    627,
2691
    /* G_VECREDUCE_FMUL */
2692
    629,
2693
    /* G_VECREDUCE_FMAX */
2694
    631,
2695
    /* G_VECREDUCE_FMIN */
2696
    633,
2697
    /* G_VECREDUCE_FMAXIMUM */
2698
    635,
2699
    /* G_VECREDUCE_FMINIMUM */
2700
    637,
2701
    /* G_VECREDUCE_ADD */
2702
    639,
2703
    /* G_VECREDUCE_MUL */
2704
    641,
2705
    /* G_VECREDUCE_AND */
2706
    643,
2707
    /* G_VECREDUCE_OR */
2708
    645,
2709
    /* G_VECREDUCE_XOR */
2710
    647,
2711
    /* G_VECREDUCE_SMAX */
2712
    649,
2713
    /* G_VECREDUCE_SMIN */
2714
    651,
2715
    /* G_VECREDUCE_UMAX */
2716
    653,
2717
    /* G_VECREDUCE_UMIN */
2718
    655,
2719
    /* G_SBFX */
2720
    657,
2721
    /* G_UBFX */
2722
    661,
2723
    /* ADD16mc */
2724
    665,
2725
    /* ADD16mi */
2726
    668,
2727
    /* ADD16mm */
2728
    671,
2729
    /* ADD16mn */
2730
    675,
2731
    /* ADD16mp */
2732
    678,
2733
    /* ADD16mr */
2734
    681,
2735
    /* ADD16rc */
2736
    684,
2737
    /* ADD16ri */
2738
    687,
2739
    /* ADD16rm */
2740
    690,
2741
    /* ADD16rn */
2742
    694,
2743
    /* ADD16rp */
2744
    697,
2745
    /* ADD16rr */
2746
    701,
2747
    /* ADD8mc */
2748
    704,
2749
    /* ADD8mi */
2750
    707,
2751
    /* ADD8mm */
2752
    710,
2753
    /* ADD8mn */
2754
    714,
2755
    /* ADD8mp */
2756
    717,
2757
    /* ADD8mr */
2758
    720,
2759
    /* ADD8rc */
2760
    723,
2761
    /* ADD8ri */
2762
    726,
2763
    /* ADD8rm */
2764
    729,
2765
    /* ADD8rn */
2766
    733,
2767
    /* ADD8rp */
2768
    736,
2769
    /* ADD8rr */
2770
    740,
2771
    /* ADDC16mc */
2772
    743,
2773
    /* ADDC16mi */
2774
    746,
2775
    /* ADDC16mm */
2776
    749,
2777
    /* ADDC16mn */
2778
    753,
2779
    /* ADDC16mp */
2780
    756,
2781
    /* ADDC16mr */
2782
    759,
2783
    /* ADDC16rc */
2784
    762,
2785
    /* ADDC16ri */
2786
    765,
2787
    /* ADDC16rm */
2788
    768,
2789
    /* ADDC16rn */
2790
    772,
2791
    /* ADDC16rp */
2792
    775,
2793
    /* ADDC16rr */
2794
    779,
2795
    /* ADDC8mc */
2796
    782,
2797
    /* ADDC8mi */
2798
    785,
2799
    /* ADDC8mm */
2800
    788,
2801
    /* ADDC8mn */
2802
    792,
2803
    /* ADDC8mp */
2804
    795,
2805
    /* ADDC8mr */
2806
    798,
2807
    /* ADDC8rc */
2808
    801,
2809
    /* ADDC8ri */
2810
    804,
2811
    /* ADDC8rm */
2812
    807,
2813
    /* ADDC8rn */
2814
    811,
2815
    /* ADDC8rp */
2816
    814,
2817
    /* ADDC8rr */
2818
    818,
2819
    /* ADDframe */
2820
    821,
2821
    /* ADJCALLSTACKDOWN */
2822
    824,
2823
    /* ADJCALLSTACKUP */
2824
    826,
2825
    /* AND16mc */
2826
    828,
2827
    /* AND16mi */
2828
    831,
2829
    /* AND16mm */
2830
    834,
2831
    /* AND16mn */
2832
    838,
2833
    /* AND16mp */
2834
    841,
2835
    /* AND16mr */
2836
    844,
2837
    /* AND16rc */
2838
    847,
2839
    /* AND16ri */
2840
    850,
2841
    /* AND16rm */
2842
    853,
2843
    /* AND16rn */
2844
    857,
2845
    /* AND16rp */
2846
    860,
2847
    /* AND16rr */
2848
    864,
2849
    /* AND8mc */
2850
    867,
2851
    /* AND8mi */
2852
    870,
2853
    /* AND8mm */
2854
    873,
2855
    /* AND8mn */
2856
    877,
2857
    /* AND8mp */
2858
    880,
2859
    /* AND8mr */
2860
    883,
2861
    /* AND8rc */
2862
    886,
2863
    /* AND8ri */
2864
    889,
2865
    /* AND8rm */
2866
    892,
2867
    /* AND8rn */
2868
    896,
2869
    /* AND8rp */
2870
    899,
2871
    /* AND8rr */
2872
    903,
2873
    /* BIC16mc */
2874
    906,
2875
    /* BIC16mi */
2876
    909,
2877
    /* BIC16mm */
2878
    912,
2879
    /* BIC16mn */
2880
    916,
2881
    /* BIC16mp */
2882
    919,
2883
    /* BIC16mr */
2884
    922,
2885
    /* BIC16rc */
2886
    925,
2887
    /* BIC16ri */
2888
    928,
2889
    /* BIC16rm */
2890
    931,
2891
    /* BIC16rn */
2892
    935,
2893
    /* BIC16rp */
2894
    938,
2895
    /* BIC16rr */
2896
    942,
2897
    /* BIC8mc */
2898
    945,
2899
    /* BIC8mi */
2900
    948,
2901
    /* BIC8mm */
2902
    951,
2903
    /* BIC8mn */
2904
    955,
2905
    /* BIC8mp */
2906
    958,
2907
    /* BIC8mr */
2908
    961,
2909
    /* BIC8rc */
2910
    964,
2911
    /* BIC8ri */
2912
    967,
2913
    /* BIC8rm */
2914
    970,
2915
    /* BIC8rn */
2916
    974,
2917
    /* BIC8rp */
2918
    977,
2919
    /* BIC8rr */
2920
    981,
2921
    /* BIS16mc */
2922
    984,
2923
    /* BIS16mi */
2924
    987,
2925
    /* BIS16mm */
2926
    990,
2927
    /* BIS16mn */
2928
    994,
2929
    /* BIS16mp */
2930
    997,
2931
    /* BIS16mr */
2932
    1000,
2933
    /* BIS16rc */
2934
    1003,
2935
    /* BIS16ri */
2936
    1006,
2937
    /* BIS16rm */
2938
    1009,
2939
    /* BIS16rn */
2940
    1013,
2941
    /* BIS16rp */
2942
    1016,
2943
    /* BIS16rr */
2944
    1020,
2945
    /* BIS8mc */
2946
    1023,
2947
    /* BIS8mi */
2948
    1026,
2949
    /* BIS8mm */
2950
    1029,
2951
    /* BIS8mn */
2952
    1033,
2953
    /* BIS8mp */
2954
    1036,
2955
    /* BIS8mr */
2956
    1039,
2957
    /* BIS8rc */
2958
    1042,
2959
    /* BIS8ri */
2960
    1045,
2961
    /* BIS8rm */
2962
    1048,
2963
    /* BIS8rn */
2964
    1052,
2965
    /* BIS8rp */
2966
    1055,
2967
    /* BIS8rr */
2968
    1059,
2969
    /* BIT16mc */
2970
    1062,
2971
    /* BIT16mi */
2972
    1065,
2973
    /* BIT16mm */
2974
    1068,
2975
    /* BIT16mn */
2976
    1072,
2977
    /* BIT16mp */
2978
    1075,
2979
    /* BIT16mr */
2980
    1078,
2981
    /* BIT16rc */
2982
    1081,
2983
    /* BIT16ri */
2984
    1083,
2985
    /* BIT16rm */
2986
    1085,
2987
    /* BIT16rn */
2988
    1088,
2989
    /* BIT16rp */
2990
    1090,
2991
    /* BIT16rr */
2992
    1092,
2993
    /* BIT8mc */
2994
    1094,
2995
    /* BIT8mi */
2996
    1097,
2997
    /* BIT8mm */
2998
    1100,
2999
    /* BIT8mn */
3000
    1104,
3001
    /* BIT8mp */
3002
    1107,
3003
    /* BIT8mr */
3004
    1110,
3005
    /* BIT8rc */
3006
    1113,
3007
    /* BIT8ri */
3008
    1115,
3009
    /* BIT8rm */
3010
    1117,
3011
    /* BIT8rn */
3012
    1120,
3013
    /* BIT8rp */
3014
    1122,
3015
    /* BIT8rr */
3016
    1124,
3017
    /* Bi */
3018
    1126,
3019
    /* Bm */
3020
    1127,
3021
    /* Br */
3022
    1129,
3023
    /* CALLi */
3024
    1130,
3025
    /* CALLm */
3026
    1131,
3027
    /* CALLn */
3028
    1133,
3029
    /* CALLp */
3030
    1134,
3031
    /* CALLr */
3032
    1135,
3033
    /* CMP16mc */
3034
    1136,
3035
    /* CMP16mi */
3036
    1139,
3037
    /* CMP16mm */
3038
    1142,
3039
    /* CMP16mn */
3040
    1146,
3041
    /* CMP16mp */
3042
    1149,
3043
    /* CMP16mr */
3044
    1152,
3045
    /* CMP16rc */
3046
    1155,
3047
    /* CMP16ri */
3048
    1157,
3049
    /* CMP16rm */
3050
    1159,
3051
    /* CMP16rn */
3052
    1162,
3053
    /* CMP16rp */
3054
    1164,
3055
    /* CMP16rr */
3056
    1166,
3057
    /* CMP8mc */
3058
    1168,
3059
    /* CMP8mi */
3060
    1171,
3061
    /* CMP8mm */
3062
    1174,
3063
    /* CMP8mn */
3064
    1178,
3065
    /* CMP8mp */
3066
    1181,
3067
    /* CMP8mr */
3068
    1184,
3069
    /* CMP8rc */
3070
    1187,
3071
    /* CMP8ri */
3072
    1189,
3073
    /* CMP8rm */
3074
    1191,
3075
    /* CMP8rn */
3076
    1194,
3077
    /* CMP8rp */
3078
    1196,
3079
    /* CMP8rr */
3080
    1198,
3081
    /* DADD16mc */
3082
    1200,
3083
    /* DADD16mi */
3084
    1203,
3085
    /* DADD16mm */
3086
    1206,
3087
    /* DADD16mn */
3088
    1210,
3089
    /* DADD16mp */
3090
    1213,
3091
    /* DADD16mr */
3092
    1216,
3093
    /* DADD16rc */
3094
    1219,
3095
    /* DADD16ri */
3096
    1222,
3097
    /* DADD16rm */
3098
    1225,
3099
    /* DADD16rn */
3100
    1229,
3101
    /* DADD16rp */
3102
    1232,
3103
    /* DADD16rr */
3104
    1236,
3105
    /* DADD8mc */
3106
    1239,
3107
    /* DADD8mi */
3108
    1242,
3109
    /* DADD8mm */
3110
    1245,
3111
    /* DADD8mn */
3112
    1249,
3113
    /* DADD8mp */
3114
    1252,
3115
    /* DADD8mr */
3116
    1255,
3117
    /* DADD8rc */
3118
    1258,
3119
    /* DADD8ri */
3120
    1261,
3121
    /* DADD8rm */
3122
    1264,
3123
    /* DADD8rn */
3124
    1268,
3125
    /* DADD8rp */
3126
    1271,
3127
    /* DADD8rr */
3128
    1275,
3129
    /* JCC */
3130
    1278,
3131
    /* JMP */
3132
    1280,
3133
    /* MOV16mc */
3134
    1281,
3135
    /* MOV16mi */
3136
    1284,
3137
    /* MOV16mm */
3138
    1287,
3139
    /* MOV16mn */
3140
    1291,
3141
    /* MOV16mr */
3142
    1294,
3143
    /* MOV16rc */
3144
    1297,
3145
    /* MOV16ri */
3146
    1299,
3147
    /* MOV16rm */
3148
    1301,
3149
    /* MOV16rn */
3150
    1304,
3151
    /* MOV16rp */
3152
    1306,
3153
    /* MOV16rr */
3154
    1309,
3155
    /* MOV8mc */
3156
    1311,
3157
    /* MOV8mi */
3158
    1314,
3159
    /* MOV8mm */
3160
    1317,
3161
    /* MOV8mn */
3162
    1321,
3163
    /* MOV8mr */
3164
    1324,
3165
    /* MOV8rc */
3166
    1327,
3167
    /* MOV8ri */
3168
    1329,
3169
    /* MOV8rm */
3170
    1331,
3171
    /* MOV8rn */
3172
    1334,
3173
    /* MOV8rp */
3174
    1336,
3175
    /* MOV8rr */
3176
    1339,
3177
    /* MOVZX16rm8 */
3178
    1341,
3179
    /* MOVZX16rr8 */
3180
    1344,
3181
    /* POP16r */
3182
    1346,
3183
    /* PUSH16c */
3184
    1347,
3185
    /* PUSH16i */
3186
    1348,
3187
    /* PUSH16r */
3188
    1349,
3189
    /* PUSH8r */
3190
    1350,
3191
    /* RET */
3192
    1351,
3193
    /* RETI */
3194
    1351,
3195
    /* RRA16m */
3196
    1351,
3197
    /* RRA16n */
3198
    1353,
3199
    /* RRA16p */
3200
    1354,
3201
    /* RRA16r */
3202
    1355,
3203
    /* RRA8m */
3204
    1357,
3205
    /* RRA8n */
3206
    1359,
3207
    /* RRA8p */
3208
    1360,
3209
    /* RRA8r */
3210
    1361,
3211
    /* RRC16m */
3212
    1363,
3213
    /* RRC16n */
3214
    1365,
3215
    /* RRC16p */
3216
    1366,
3217
    /* RRC16r */
3218
    1367,
3219
    /* RRC8m */
3220
    1369,
3221
    /* RRC8n */
3222
    1371,
3223
    /* RRC8p */
3224
    1372,
3225
    /* RRC8r */
3226
    1373,
3227
    /* Rrcl16 */
3228
    1375,
3229
    /* Rrcl8 */
3230
    1377,
3231
    /* SEXT16m */
3232
    1379,
3233
    /* SEXT16n */
3234
    1381,
3235
    /* SEXT16p */
3236
    1382,
3237
    /* SEXT16r */
3238
    1383,
3239
    /* SUB16mc */
3240
    1385,
3241
    /* SUB16mi */
3242
    1388,
3243
    /* SUB16mm */
3244
    1391,
3245
    /* SUB16mn */
3246
    1395,
3247
    /* SUB16mp */
3248
    1398,
3249
    /* SUB16mr */
3250
    1401,
3251
    /* SUB16rc */
3252
    1404,
3253
    /* SUB16ri */
3254
    1407,
3255
    /* SUB16rm */
3256
    1410,
3257
    /* SUB16rn */
3258
    1414,
3259
    /* SUB16rp */
3260
    1417,
3261
    /* SUB16rr */
3262
    1421,
3263
    /* SUB8mc */
3264
    1424,
3265
    /* SUB8mi */
3266
    1427,
3267
    /* SUB8mm */
3268
    1430,
3269
    /* SUB8mn */
3270
    1434,
3271
    /* SUB8mp */
3272
    1437,
3273
    /* SUB8mr */
3274
    1440,
3275
    /* SUB8rc */
3276
    1443,
3277
    /* SUB8ri */
3278
    1446,
3279
    /* SUB8rm */
3280
    1449,
3281
    /* SUB8rn */
3282
    1453,
3283
    /* SUB8rp */
3284
    1456,
3285
    /* SUB8rr */
3286
    1460,
3287
    /* SUBC16mc */
3288
    1463,
3289
    /* SUBC16mi */
3290
    1466,
3291
    /* SUBC16mm */
3292
    1469,
3293
    /* SUBC16mn */
3294
    1473,
3295
    /* SUBC16mp */
3296
    1476,
3297
    /* SUBC16mr */
3298
    1479,
3299
    /* SUBC16rc */
3300
    1482,
3301
    /* SUBC16ri */
3302
    1485,
3303
    /* SUBC16rm */
3304
    1488,
3305
    /* SUBC16rn */
3306
    1492,
3307
    /* SUBC16rp */
3308
    1495,
3309
    /* SUBC16rr */
3310
    1499,
3311
    /* SUBC8mc */
3312
    1502,
3313
    /* SUBC8mi */
3314
    1505,
3315
    /* SUBC8mm */
3316
    1508,
3317
    /* SUBC8mn */
3318
    1512,
3319
    /* SUBC8mp */
3320
    1515,
3321
    /* SUBC8mr */
3322
    1518,
3323
    /* SUBC8rc */
3324
    1521,
3325
    /* SUBC8ri */
3326
    1524,
3327
    /* SUBC8rm */
3328
    1527,
3329
    /* SUBC8rn */
3330
    1531,
3331
    /* SUBC8rp */
3332
    1534,
3333
    /* SUBC8rr */
3334
    1538,
3335
    /* SWPB16m */
3336
    1541,
3337
    /* SWPB16n */
3338
    1543,
3339
    /* SWPB16p */
3340
    1544,
3341
    /* SWPB16r */
3342
    1545,
3343
    /* Select16 */
3344
    1547,
3345
    /* Select8 */
3346
    1551,
3347
    /* Shl16 */
3348
    1555,
3349
    /* Shl8 */
3350
    1558,
3351
    /* Sra16 */
3352
    1561,
3353
    /* Sra8 */
3354
    1564,
3355
    /* Srl16 */
3356
    1567,
3357
    /* Srl8 */
3358
    1570,
3359
    /* XOR16mc */
3360
    1573,
3361
    /* XOR16mi */
3362
    1576,
3363
    /* XOR16mm */
3364
    1579,
3365
    /* XOR16mn */
3366
    1583,
3367
    /* XOR16mp */
3368
    1586,
3369
    /* XOR16mr */
3370
    1589,
3371
    /* XOR16rc */
3372
    1592,
3373
    /* XOR16ri */
3374
    1595,
3375
    /* XOR16rm */
3376
    1598,
3377
    /* XOR16rn */
3378
    1602,
3379
    /* XOR16rp */
3380
    1605,
3381
    /* XOR16rr */
3382
    1609,
3383
    /* XOR8mc */
3384
    1612,
3385
    /* XOR8mi */
3386
    1615,
3387
    /* XOR8mm */
3388
    1618,
3389
    /* XOR8mn */
3390
    1622,
3391
    /* XOR8mp */
3392
    1625,
3393
    /* XOR8mr */
3394
    1628,
3395
    /* XOR8rc */
3396
    1631,
3397
    /* XOR8ri */
3398
    1634,
3399
    /* XOR8rm */
3400
    1637,
3401
    /* XOR8rn */
3402
    1641,
3403
    /* XOR8rp */
3404
    1644,
3405
    /* XOR8rr */
3406
    1648,
3407
    /* ZEXT16r */
3408
    1651,
3409
  };
3410
3411
  using namespace OpTypes;
3412
  static const int8_t OpcodeOperandTypes[] = {
3413
    
3414
    /* PHI */
3415
    -1, 
3416
    /* INLINEASM */
3417
    /* INLINEASM_BR */
3418
    /* CFI_INSTRUCTION */
3419
    i32imm, 
3420
    /* EH_LABEL */
3421
    i32imm, 
3422
    /* GC_LABEL */
3423
    i32imm, 
3424
    /* ANNOTATION_LABEL */
3425
    i32imm, 
3426
    /* KILL */
3427
    /* EXTRACT_SUBREG */
3428
    -1, -1, i32imm, 
3429
    /* INSERT_SUBREG */
3430
    -1, -1, -1, i32imm, 
3431
    /* IMPLICIT_DEF */
3432
    -1, 
3433
    /* SUBREG_TO_REG */
3434
    -1, -1, -1, i32imm, 
3435
    /* COPY_TO_REGCLASS */
3436
    -1, -1, i32imm, 
3437
    /* DBG_VALUE */
3438
    /* DBG_VALUE_LIST */
3439
    /* DBG_INSTR_REF */
3440
    /* DBG_PHI */
3441
    /* DBG_LABEL */
3442
    -1, 
3443
    /* REG_SEQUENCE */
3444
    -1, -1, 
3445
    /* COPY */
3446
    -1, -1, 
3447
    /* BUNDLE */
3448
    /* LIFETIME_START */
3449
    i32imm, 
3450
    /* LIFETIME_END */
3451
    i32imm, 
3452
    /* PSEUDO_PROBE */
3453
    i64imm, i64imm, i8imm, i32imm, 
3454
    /* ARITH_FENCE */
3455
    -1, -1, 
3456
    /* STACKMAP */
3457
    i64imm, i32imm, 
3458
    /* FENTRY_CALL */
3459
    /* PATCHPOINT */
3460
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
3461
    /* LOAD_STACK_GUARD */
3462
    -1, 
3463
    /* PREALLOCATED_SETUP */
3464
    i32imm, 
3465
    /* PREALLOCATED_ARG */
3466
    -1, i32imm, i32imm, 
3467
    /* STATEPOINT */
3468
    /* LOCAL_ESCAPE */
3469
    -1, i32imm, 
3470
    /* FAULTING_OP */
3471
    -1, 
3472
    /* PATCHABLE_OP */
3473
    /* PATCHABLE_FUNCTION_ENTER */
3474
    /* PATCHABLE_RET */
3475
    /* PATCHABLE_FUNCTION_EXIT */
3476
    /* PATCHABLE_TAIL_CALL */
3477
    /* PATCHABLE_EVENT_CALL */
3478
    -1, -1, 
3479
    /* PATCHABLE_TYPED_EVENT_CALL */
3480
    -1, -1, -1, 
3481
    /* ICALL_BRANCH_FUNNEL */
3482
    /* MEMBARRIER */
3483
    /* JUMP_TABLE_DEBUG_INFO */
3484
    i64imm, 
3485
    /* G_ASSERT_SEXT */
3486
    type0, type0, untyped_imm_0, 
3487
    /* G_ASSERT_ZEXT */
3488
    type0, type0, untyped_imm_0, 
3489
    /* G_ASSERT_ALIGN */
3490
    type0, type0, untyped_imm_0, 
3491
    /* G_ADD */
3492
    type0, type0, type0, 
3493
    /* G_SUB */
3494
    type0, type0, type0, 
3495
    /* G_MUL */
3496
    type0, type0, type0, 
3497
    /* G_SDIV */
3498
    type0, type0, type0, 
3499
    /* G_UDIV */
3500
    type0, type0, type0, 
3501
    /* G_SREM */
3502
    type0, type0, type0, 
3503
    /* G_UREM */
3504
    type0, type0, type0, 
3505
    /* G_SDIVREM */
3506
    type0, type0, type0, type0, 
3507
    /* G_UDIVREM */
3508
    type0, type0, type0, type0, 
3509
    /* G_AND */
3510
    type0, type0, type0, 
3511
    /* G_OR */
3512
    type0, type0, type0, 
3513
    /* G_XOR */
3514
    type0, type0, type0, 
3515
    /* G_IMPLICIT_DEF */
3516
    type0, 
3517
    /* G_PHI */
3518
    type0, 
3519
    /* G_FRAME_INDEX */
3520
    type0, -1, 
3521
    /* G_GLOBAL_VALUE */
3522
    type0, -1, 
3523
    /* G_CONSTANT_POOL */
3524
    type0, -1, 
3525
    /* G_EXTRACT */
3526
    type0, type1, untyped_imm_0, 
3527
    /* G_UNMERGE_VALUES */
3528
    type0, type1, 
3529
    /* G_INSERT */
3530
    type0, type0, type1, untyped_imm_0, 
3531
    /* G_MERGE_VALUES */
3532
    type0, type1, 
3533
    /* G_BUILD_VECTOR */
3534
    type0, type1, 
3535
    /* G_BUILD_VECTOR_TRUNC */
3536
    type0, type1, 
3537
    /* G_CONCAT_VECTORS */
3538
    type0, type1, 
3539
    /* G_PTRTOINT */
3540
    type0, type1, 
3541
    /* G_INTTOPTR */
3542
    type0, type1, 
3543
    /* G_BITCAST */
3544
    type0, type1, 
3545
    /* G_FREEZE */
3546
    type0, type0, 
3547
    /* G_CONSTANT_FOLD_BARRIER */
3548
    type0, type0, 
3549
    /* G_INTRINSIC_FPTRUNC_ROUND */
3550
    type0, type1, i32imm, 
3551
    /* G_INTRINSIC_TRUNC */
3552
    type0, type0, 
3553
    /* G_INTRINSIC_ROUND */
3554
    type0, type0, 
3555
    /* G_INTRINSIC_LRINT */
3556
    type0, type1, 
3557
    /* G_INTRINSIC_ROUNDEVEN */
3558
    type0, type0, 
3559
    /* G_READCYCLECOUNTER */
3560
    type0, 
3561
    /* G_LOAD */
3562
    type0, ptype1, 
3563
    /* G_SEXTLOAD */
3564
    type0, ptype1, 
3565
    /* G_ZEXTLOAD */
3566
    type0, ptype1, 
3567
    /* G_INDEXED_LOAD */
3568
    type0, ptype1, ptype1, type2, -1, 
3569
    /* G_INDEXED_SEXTLOAD */
3570
    type0, ptype1, ptype1, type2, -1, 
3571
    /* G_INDEXED_ZEXTLOAD */
3572
    type0, ptype1, ptype1, type2, -1, 
3573
    /* G_STORE */
3574
    type0, ptype1, 
3575
    /* G_INDEXED_STORE */
3576
    ptype0, type1, ptype0, ptype2, -1, 
3577
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
3578
    type0, type1, type2, type0, type0, 
3579
    /* G_ATOMIC_CMPXCHG */
3580
    type0, ptype1, type0, type0, 
3581
    /* G_ATOMICRMW_XCHG */
3582
    type0, ptype1, type0, 
3583
    /* G_ATOMICRMW_ADD */
3584
    type0, ptype1, type0, 
3585
    /* G_ATOMICRMW_SUB */
3586
    type0, ptype1, type0, 
3587
    /* G_ATOMICRMW_AND */
3588
    type0, ptype1, type0, 
3589
    /* G_ATOMICRMW_NAND */
3590
    type0, ptype1, type0, 
3591
    /* G_ATOMICRMW_OR */
3592
    type0, ptype1, type0, 
3593
    /* G_ATOMICRMW_XOR */
3594
    type0, ptype1, type0, 
3595
    /* G_ATOMICRMW_MAX */
3596
    type0, ptype1, type0, 
3597
    /* G_ATOMICRMW_MIN */
3598
    type0, ptype1, type0, 
3599
    /* G_ATOMICRMW_UMAX */
3600
    type0, ptype1, type0, 
3601
    /* G_ATOMICRMW_UMIN */
3602
    type0, ptype1, type0, 
3603
    /* G_ATOMICRMW_FADD */
3604
    type0, ptype1, type0, 
3605
    /* G_ATOMICRMW_FSUB */
3606
    type0, ptype1, type0, 
3607
    /* G_ATOMICRMW_FMAX */
3608
    type0, ptype1, type0, 
3609
    /* G_ATOMICRMW_FMIN */
3610
    type0, ptype1, type0, 
3611
    /* G_ATOMICRMW_UINC_WRAP */
3612
    type0, ptype1, type0, 
3613
    /* G_ATOMICRMW_UDEC_WRAP */
3614
    type0, ptype1, type0, 
3615
    /* G_FENCE */
3616
    i32imm, i32imm, 
3617
    /* G_PREFETCH */
3618
    ptype0, i32imm, i32imm, i32imm, 
3619
    /* G_BRCOND */
3620
    type0, -1, 
3621
    /* G_BRINDIRECT */
3622
    type0, 
3623
    /* G_INVOKE_REGION_START */
3624
    /* G_INTRINSIC */
3625
    -1, 
3626
    /* G_INTRINSIC_W_SIDE_EFFECTS */
3627
    -1, 
3628
    /* G_INTRINSIC_CONVERGENT */
3629
    -1, 
3630
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
3631
    -1, 
3632
    /* G_ANYEXT */
3633
    type0, type1, 
3634
    /* G_TRUNC */
3635
    type0, type1, 
3636
    /* G_CONSTANT */
3637
    type0, -1, 
3638
    /* G_FCONSTANT */
3639
    type0, -1, 
3640
    /* G_VASTART */
3641
    type0, 
3642
    /* G_VAARG */
3643
    type0, type1, -1, 
3644
    /* G_SEXT */
3645
    type0, type1, 
3646
    /* G_SEXT_INREG */
3647
    type0, type0, untyped_imm_0, 
3648
    /* G_ZEXT */
3649
    type0, type1, 
3650
    /* G_SHL */
3651
    type0, type0, type1, 
3652
    /* G_LSHR */
3653
    type0, type0, type1, 
3654
    /* G_ASHR */
3655
    type0, type0, type1, 
3656
    /* G_FSHL */
3657
    type0, type0, type0, type1, 
3658
    /* G_FSHR */
3659
    type0, type0, type0, type1, 
3660
    /* G_ROTR */
3661
    type0, type0, type1, 
3662
    /* G_ROTL */
3663
    type0, type0, type1, 
3664
    /* G_ICMP */
3665
    type0, -1, type1, type1, 
3666
    /* G_FCMP */
3667
    type0, -1, type1, type1, 
3668
    /* G_SELECT */
3669
    type0, type1, type0, type0, 
3670
    /* G_UADDO */
3671
    type0, type1, type0, type0, 
3672
    /* G_UADDE */
3673
    type0, type1, type0, type0, type1, 
3674
    /* G_USUBO */
3675
    type0, type1, type0, type0, 
3676
    /* G_USUBE */
3677
    type0, type1, type0, type0, type1, 
3678
    /* G_SADDO */
3679
    type0, type1, type0, type0, 
3680
    /* G_SADDE */
3681
    type0, type1, type0, type0, type1, 
3682
    /* G_SSUBO */
3683
    type0, type1, type0, type0, 
3684
    /* G_SSUBE */
3685
    type0, type1, type0, type0, type1, 
3686
    /* G_UMULO */
3687
    type0, type1, type0, type0, 
3688
    /* G_SMULO */
3689
    type0, type1, type0, type0, 
3690
    /* G_UMULH */
3691
    type0, type0, type0, 
3692
    /* G_SMULH */
3693
    type0, type0, type0, 
3694
    /* G_UADDSAT */
3695
    type0, type0, type0, 
3696
    /* G_SADDSAT */
3697
    type0, type0, type0, 
3698
    /* G_USUBSAT */
3699
    type0, type0, type0, 
3700
    /* G_SSUBSAT */
3701
    type0, type0, type0, 
3702
    /* G_USHLSAT */
3703
    type0, type0, type1, 
3704
    /* G_SSHLSAT */
3705
    type0, type0, type1, 
3706
    /* G_SMULFIX */
3707
    type0, type0, type0, untyped_imm_0, 
3708
    /* G_UMULFIX */
3709
    type0, type0, type0, untyped_imm_0, 
3710
    /* G_SMULFIXSAT */
3711
    type0, type0, type0, untyped_imm_0, 
3712
    /* G_UMULFIXSAT */
3713
    type0, type0, type0, untyped_imm_0, 
3714
    /* G_SDIVFIX */
3715
    type0, type0, type0, untyped_imm_0, 
3716
    /* G_UDIVFIX */
3717
    type0, type0, type0, untyped_imm_0, 
3718
    /* G_SDIVFIXSAT */
3719
    type0, type0, type0, untyped_imm_0, 
3720
    /* G_UDIVFIXSAT */
3721
    type0, type0, type0, untyped_imm_0, 
3722
    /* G_FADD */
3723
    type0, type0, type0, 
3724
    /* G_FSUB */
3725
    type0, type0, type0, 
3726
    /* G_FMUL */
3727
    type0, type0, type0, 
3728
    /* G_FMA */
3729
    type0, type0, type0, type0, 
3730
    /* G_FMAD */
3731
    type0, type0, type0, type0, 
3732
    /* G_FDIV */
3733
    type0, type0, type0, 
3734
    /* G_FREM */
3735
    type0, type0, type0, 
3736
    /* G_FPOW */
3737
    type0, type0, type0, 
3738
    /* G_FPOWI */
3739
    type0, type0, type1, 
3740
    /* G_FEXP */
3741
    type0, type0, 
3742
    /* G_FEXP2 */
3743
    type0, type0, 
3744
    /* G_FEXP10 */
3745
    type0, type0, 
3746
    /* G_FLOG */
3747
    type0, type0, 
3748
    /* G_FLOG2 */
3749
    type0, type0, 
3750
    /* G_FLOG10 */
3751
    type0, type0, 
3752
    /* G_FLDEXP */
3753
    type0, type0, type1, 
3754
    /* G_FFREXP */
3755
    type0, type1, type0, 
3756
    /* G_FNEG */
3757
    type0, type0, 
3758
    /* G_FPEXT */
3759
    type0, type1, 
3760
    /* G_FPTRUNC */
3761
    type0, type1, 
3762
    /* G_FPTOSI */
3763
    type0, type1, 
3764
    /* G_FPTOUI */
3765
    type0, type1, 
3766
    /* G_SITOFP */
3767
    type0, type1, 
3768
    /* G_UITOFP */
3769
    type0, type1, 
3770
    /* G_FABS */
3771
    type0, type0, 
3772
    /* G_FCOPYSIGN */
3773
    type0, type0, type1, 
3774
    /* G_IS_FPCLASS */
3775
    type0, type1, -1, 
3776
    /* G_FCANONICALIZE */
3777
    type0, type0, 
3778
    /* G_FMINNUM */
3779
    type0, type0, type0, 
3780
    /* G_FMAXNUM */
3781
    type0, type0, type0, 
3782
    /* G_FMINNUM_IEEE */
3783
    type0, type0, type0, 
3784
    /* G_FMAXNUM_IEEE */
3785
    type0, type0, type0, 
3786
    /* G_FMINIMUM */
3787
    type0, type0, type0, 
3788
    /* G_FMAXIMUM */
3789
    type0, type0, type0, 
3790
    /* G_GET_FPENV */
3791
    type0, 
3792
    /* G_SET_FPENV */
3793
    type0, 
3794
    /* G_RESET_FPENV */
3795
    /* G_GET_FPMODE */
3796
    type0, 
3797
    /* G_SET_FPMODE */
3798
    type0, 
3799
    /* G_RESET_FPMODE */
3800
    /* G_PTR_ADD */
3801
    ptype0, ptype0, type1, 
3802
    /* G_PTRMASK */
3803
    ptype0, ptype0, type1, 
3804
    /* G_SMIN */
3805
    type0, type0, type0, 
3806
    /* G_SMAX */
3807
    type0, type0, type0, 
3808
    /* G_UMIN */
3809
    type0, type0, type0, 
3810
    /* G_UMAX */
3811
    type0, type0, type0, 
3812
    /* G_ABS */
3813
    type0, type0, 
3814
    /* G_LROUND */
3815
    type0, type1, 
3816
    /* G_LLROUND */
3817
    type0, type1, 
3818
    /* G_BR */
3819
    -1, 
3820
    /* G_BRJT */
3821
    ptype0, -1, type1, 
3822
    /* G_INSERT_VECTOR_ELT */
3823
    type0, type0, type1, type2, 
3824
    /* G_EXTRACT_VECTOR_ELT */
3825
    type0, type1, type2, 
3826
    /* G_SHUFFLE_VECTOR */
3827
    type0, type1, type1, -1, 
3828
    /* G_CTTZ */
3829
    type0, type1, 
3830
    /* G_CTTZ_ZERO_UNDEF */
3831
    type0, type1, 
3832
    /* G_CTLZ */
3833
    type0, type1, 
3834
    /* G_CTLZ_ZERO_UNDEF */
3835
    type0, type1, 
3836
    /* G_CTPOP */
3837
    type0, type1, 
3838
    /* G_BSWAP */
3839
    type0, type0, 
3840
    /* G_BITREVERSE */
3841
    type0, type0, 
3842
    /* G_FCEIL */
3843
    type0, type0, 
3844
    /* G_FCOS */
3845
    type0, type0, 
3846
    /* G_FSIN */
3847
    type0, type0, 
3848
    /* G_FSQRT */
3849
    type0, type0, 
3850
    /* G_FFLOOR */
3851
    type0, type0, 
3852
    /* G_FRINT */
3853
    type0, type0, 
3854
    /* G_FNEARBYINT */
3855
    type0, type0, 
3856
    /* G_ADDRSPACE_CAST */
3857
    type0, type1, 
3858
    /* G_BLOCK_ADDR */
3859
    type0, -1, 
3860
    /* G_JUMP_TABLE */
3861
    type0, -1, 
3862
    /* G_DYN_STACKALLOC */
3863
    ptype0, type1, i32imm, 
3864
    /* G_STACKSAVE */
3865
    ptype0, 
3866
    /* G_STACKRESTORE */
3867
    ptype0, 
3868
    /* G_STRICT_FADD */
3869
    type0, type0, type0, 
3870
    /* G_STRICT_FSUB */
3871
    type0, type0, type0, 
3872
    /* G_STRICT_FMUL */
3873
    type0, type0, type0, 
3874
    /* G_STRICT_FDIV */
3875
    type0, type0, type0, 
3876
    /* G_STRICT_FREM */
3877
    type0, type0, type0, 
3878
    /* G_STRICT_FMA */
3879
    type0, type0, type0, type0, 
3880
    /* G_STRICT_FSQRT */
3881
    type0, type0, 
3882
    /* G_STRICT_FLDEXP */
3883
    type0, type0, type1, 
3884
    /* G_READ_REGISTER */
3885
    type0, -1, 
3886
    /* G_WRITE_REGISTER */
3887
    -1, type0, 
3888
    /* G_MEMCPY */
3889
    ptype0, ptype1, type2, untyped_imm_0, 
3890
    /* G_MEMCPY_INLINE */
3891
    ptype0, ptype1, type2, 
3892
    /* G_MEMMOVE */
3893
    ptype0, ptype1, type2, untyped_imm_0, 
3894
    /* G_MEMSET */
3895
    ptype0, type1, type2, untyped_imm_0, 
3896
    /* G_BZERO */
3897
    ptype0, type1, untyped_imm_0, 
3898
    /* G_VECREDUCE_SEQ_FADD */
3899
    type0, type1, type2, 
3900
    /* G_VECREDUCE_SEQ_FMUL */
3901
    type0, type1, type2, 
3902
    /* G_VECREDUCE_FADD */
3903
    type0, type1, 
3904
    /* G_VECREDUCE_FMUL */
3905
    type0, type1, 
3906
    /* G_VECREDUCE_FMAX */
3907
    type0, type1, 
3908
    /* G_VECREDUCE_FMIN */
3909
    type0, type1, 
3910
    /* G_VECREDUCE_FMAXIMUM */
3911
    type0, type1, 
3912
    /* G_VECREDUCE_FMINIMUM */
3913
    type0, type1, 
3914
    /* G_VECREDUCE_ADD */
3915
    type0, type1, 
3916
    /* G_VECREDUCE_MUL */
3917
    type0, type1, 
3918
    /* G_VECREDUCE_AND */
3919
    type0, type1, 
3920
    /* G_VECREDUCE_OR */
3921
    type0, type1, 
3922
    /* G_VECREDUCE_XOR */
3923
    type0, type1, 
3924
    /* G_VECREDUCE_SMAX */
3925
    type0, type1, 
3926
    /* G_VECREDUCE_SMIN */
3927
    type0, type1, 
3928
    /* G_VECREDUCE_UMAX */
3929
    type0, type1, 
3930
    /* G_VECREDUCE_UMIN */
3931
    type0, type1, 
3932
    /* G_SBFX */
3933
    type0, type0, type1, type1, 
3934
    /* G_UBFX */
3935
    type0, type0, type1, type1, 
3936
    /* ADD16mc */
3937
    GR16, i16imm, cg16imm, 
3938
    /* ADD16mi */
3939
    GR16, i16imm, i16imm, 
3940
    /* ADD16mm */
3941
    GR16, i16imm, GR16, i16imm, 
3942
    /* ADD16mn */
3943
    GR16, i16imm, GR16, 
3944
    /* ADD16mp */
3945
    GR16, i16imm, GR16, 
3946
    /* ADD16mr */
3947
    GR16, i16imm, GR16, 
3948
    /* ADD16rc */
3949
    GR16, GR16, cg16imm, 
3950
    /* ADD16ri */
3951
    GR16, GR16, i16imm, 
3952
    /* ADD16rm */
3953
    GR16, GR16, GR16, i16imm, 
3954
    /* ADD16rn */
3955
    GR16, GR16, GR16, 
3956
    /* ADD16rp */
3957
    GR16, GR16, GR16, GR16, 
3958
    /* ADD16rr */
3959
    GR16, GR16, GR16, 
3960
    /* ADD8mc */
3961
    GR16, i16imm, cg8imm, 
3962
    /* ADD8mi */
3963
    GR16, i16imm, i8imm, 
3964
    /* ADD8mm */
3965
    GR16, i16imm, GR16, i16imm, 
3966
    /* ADD8mn */
3967
    GR16, i16imm, GR16, 
3968
    /* ADD8mp */
3969
    GR16, i16imm, GR16, 
3970
    /* ADD8mr */
3971
    GR16, i16imm, GR8, 
3972
    /* ADD8rc */
3973
    GR8, GR8, cg8imm, 
3974
    /* ADD8ri */
3975
    GR8, GR8, i8imm, 
3976
    /* ADD8rm */
3977
    GR8, GR8, GR16, i16imm, 
3978
    /* ADD8rn */
3979
    GR8, GR8, GR16, 
3980
    /* ADD8rp */
3981
    GR8, GR16, GR8, GR16, 
3982
    /* ADD8rr */
3983
    GR8, GR8, GR8, 
3984
    /* ADDC16mc */
3985
    GR16, i16imm, cg16imm, 
3986
    /* ADDC16mi */
3987
    GR16, i16imm, i16imm, 
3988
    /* ADDC16mm */
3989
    GR16, i16imm, GR16, i16imm, 
3990
    /* ADDC16mn */
3991
    GR16, i16imm, GR16, 
3992
    /* ADDC16mp */
3993
    GR16, i16imm, GR16, 
3994
    /* ADDC16mr */
3995
    GR16, i16imm, GR16, 
3996
    /* ADDC16rc */
3997
    GR16, GR16, cg16imm, 
3998
    /* ADDC16ri */
3999
    GR16, GR16, i16imm, 
4000
    /* ADDC16rm */
4001
    GR16, GR16, GR16, i16imm, 
4002
    /* ADDC16rn */
4003
    GR16, GR16, GR16, 
4004
    /* ADDC16rp */
4005
    GR16, GR16, GR16, GR16, 
4006
    /* ADDC16rr */
4007
    GR16, GR16, GR16, 
4008
    /* ADDC8mc */
4009
    GR16, i16imm, cg8imm, 
4010
    /* ADDC8mi */
4011
    GR16, i16imm, i8imm, 
4012
    /* ADDC8mm */
4013
    GR16, i16imm, GR16, i16imm, 
4014
    /* ADDC8mn */
4015
    GR16, i16imm, GR16, 
4016
    /* ADDC8mp */
4017
    GR16, i16imm, GR16, 
4018
    /* ADDC8mr */
4019
    GR16, i16imm, GR8, 
4020
    /* ADDC8rc */
4021
    GR8, GR8, cg8imm, 
4022
    /* ADDC8ri */
4023
    GR8, GR8, i8imm, 
4024
    /* ADDC8rm */
4025
    GR8, GR8, GR16, i16imm, 
4026
    /* ADDC8rn */
4027
    GR8, GR8, GR16, 
4028
    /* ADDC8rp */
4029
    GR8, GR16, GR8, GR16, 
4030
    /* ADDC8rr */
4031
    GR8, GR8, GR8, 
4032
    /* ADDframe */
4033
    GR16, i16imm, i16imm, 
4034
    /* ADJCALLSTACKDOWN */
4035
    i16imm, i16imm, 
4036
    /* ADJCALLSTACKUP */
4037
    i16imm, i16imm, 
4038
    /* AND16mc */
4039
    GR16, i16imm, cg16imm, 
4040
    /* AND16mi */
4041
    GR16, i16imm, i16imm, 
4042
    /* AND16mm */
4043
    GR16, i16imm, GR16, i16imm, 
4044
    /* AND16mn */
4045
    GR16, i16imm, GR16, 
4046
    /* AND16mp */
4047
    GR16, i16imm, GR16, 
4048
    /* AND16mr */
4049
    GR16, i16imm, GR16, 
4050
    /* AND16rc */
4051
    GR16, GR16, cg16imm, 
4052
    /* AND16ri */
4053
    GR16, GR16, i16imm, 
4054
    /* AND16rm */
4055
    GR16, GR16, GR16, i16imm, 
4056
    /* AND16rn */
4057
    GR16, GR16, GR16, 
4058
    /* AND16rp */
4059
    GR16, GR16, GR16, GR16, 
4060
    /* AND16rr */
4061
    GR16, GR16, GR16, 
4062
    /* AND8mc */
4063
    GR16, i16imm, cg8imm, 
4064
    /* AND8mi */
4065
    GR16, i16imm, i8imm, 
4066
    /* AND8mm */
4067
    GR16, i16imm, GR16, i16imm, 
4068
    /* AND8mn */
4069
    GR16, i16imm, GR16, 
4070
    /* AND8mp */
4071
    GR16, i16imm, GR16, 
4072
    /* AND8mr */
4073
    GR16, i16imm, GR8, 
4074
    /* AND8rc */
4075
    GR8, GR8, cg8imm, 
4076
    /* AND8ri */
4077
    GR8, GR8, i8imm, 
4078
    /* AND8rm */
4079
    GR8, GR8, GR16, i16imm, 
4080
    /* AND8rn */
4081
    GR8, GR8, GR16, 
4082
    /* AND8rp */
4083
    GR8, GR16, GR8, GR16, 
4084
    /* AND8rr */
4085
    GR8, GR8, GR8, 
4086
    /* BIC16mc */
4087
    GR16, i16imm, cg16imm, 
4088
    /* BIC16mi */
4089
    GR16, i16imm, i16imm, 
4090
    /* BIC16mm */
4091
    GR16, i16imm, GR16, i16imm, 
4092
    /* BIC16mn */
4093
    GR16, i16imm, GR16, 
4094
    /* BIC16mp */
4095
    GR16, i16imm, GR16, 
4096
    /* BIC16mr */
4097
    GR16, i16imm, GR16, 
4098
    /* BIC16rc */
4099
    GR16, GR16, cg16imm, 
4100
    /* BIC16ri */
4101
    GR16, GR16, i16imm, 
4102
    /* BIC16rm */
4103
    GR16, GR16, GR16, i16imm, 
4104
    /* BIC16rn */
4105
    GR16, GR16, GR16, 
4106
    /* BIC16rp */
4107
    GR16, GR16, GR16, GR16, 
4108
    /* BIC16rr */
4109
    GR16, GR16, GR16, 
4110
    /* BIC8mc */
4111
    GR16, i16imm, cg8imm, 
4112
    /* BIC8mi */
4113
    GR16, i16imm, i8imm, 
4114
    /* BIC8mm */
4115
    GR16, i16imm, GR16, i16imm, 
4116
    /* BIC8mn */
4117
    GR16, i16imm, GR16, 
4118
    /* BIC8mp */
4119
    GR16, i16imm, GR16, 
4120
    /* BIC8mr */
4121
    GR16, i16imm, GR8, 
4122
    /* BIC8rc */
4123
    GR8, GR8, cg8imm, 
4124
    /* BIC8ri */
4125
    GR8, GR8, i8imm, 
4126
    /* BIC8rm */
4127
    GR8, GR8, GR16, i16imm, 
4128
    /* BIC8rn */
4129
    GR8, GR8, GR16, 
4130
    /* BIC8rp */
4131
    GR8, GR16, GR8, GR16, 
4132
    /* BIC8rr */
4133
    GR8, GR8, GR8, 
4134
    /* BIS16mc */
4135
    GR16, i16imm, cg16imm, 
4136
    /* BIS16mi */
4137
    GR16, i16imm, i16imm, 
4138
    /* BIS16mm */
4139
    GR16, i16imm, GR16, i16imm, 
4140
    /* BIS16mn */
4141
    GR16, i16imm, GR16, 
4142
    /* BIS16mp */
4143
    GR16, i16imm, GR16, 
4144
    /* BIS16mr */
4145
    GR16, i16imm, GR16, 
4146
    /* BIS16rc */
4147
    GR16, GR16, cg16imm, 
4148
    /* BIS16ri */
4149
    GR16, GR16, i16imm, 
4150
    /* BIS16rm */
4151
    GR16, GR16, GR16, i16imm, 
4152
    /* BIS16rn */
4153
    GR16, GR16, GR16, 
4154
    /* BIS16rp */
4155
    GR16, GR16, GR16, GR16, 
4156
    /* BIS16rr */
4157
    GR16, GR16, GR16, 
4158
    /* BIS8mc */
4159
    GR16, i16imm, cg8imm, 
4160
    /* BIS8mi */
4161
    GR16, i16imm, i8imm, 
4162
    /* BIS8mm */
4163
    GR16, i16imm, GR16, i16imm, 
4164
    /* BIS8mn */
4165
    GR16, i16imm, GR16, 
4166
    /* BIS8mp */
4167
    GR16, i16imm, GR16, 
4168
    /* BIS8mr */
4169
    GR16, i16imm, GR8, 
4170
    /* BIS8rc */
4171
    GR8, GR8, cg8imm, 
4172
    /* BIS8ri */
4173
    GR8, GR8, i8imm, 
4174
    /* BIS8rm */
4175
    GR8, GR8, GR16, i16imm, 
4176
    /* BIS8rn */
4177
    GR8, GR8, GR16, 
4178
    /* BIS8rp */
4179
    GR8, GR16, GR8, GR16, 
4180
    /* BIS8rr */
4181
    GR8, GR8, GR8, 
4182
    /* BIT16mc */
4183
    GR16, i16imm, cg16imm, 
4184
    /* BIT16mi */
4185
    GR16, i16imm, i16imm, 
4186
    /* BIT16mm */
4187
    GR16, i16imm, GR16, i16imm, 
4188
    /* BIT16mn */
4189
    GR16, i16imm, GR16, 
4190
    /* BIT16mp */
4191
    GR16, i16imm, GR16, 
4192
    /* BIT16mr */
4193
    GR16, i16imm, GR16, 
4194
    /* BIT16rc */
4195
    GR16, cg16imm, 
4196
    /* BIT16ri */
4197
    GR16, i16imm, 
4198
    /* BIT16rm */
4199
    GR16, GR16, i16imm, 
4200
    /* BIT16rn */
4201
    GR16, GR16, 
4202
    /* BIT16rp */
4203
    GR16, GR16, 
4204
    /* BIT16rr */
4205
    GR16, GR16, 
4206
    /* BIT8mc */
4207
    GR16, i16imm, cg8imm, 
4208
    /* BIT8mi */
4209
    GR16, i16imm, i8imm, 
4210
    /* BIT8mm */
4211
    GR16, i16imm, GR16, i16imm, 
4212
    /* BIT8mn */
4213
    GR16, i16imm, GR16, 
4214
    /* BIT8mp */
4215
    GR16, i16imm, GR16, 
4216
    /* BIT8mr */
4217
    GR16, i16imm, GR8, 
4218
    /* BIT8rc */
4219
    GR8, cg8imm, 
4220
    /* BIT8ri */
4221
    GR8, i8imm, 
4222
    /* BIT8rm */
4223
    GR8, GR16, i16imm, 
4224
    /* BIT8rn */
4225
    GR8, GR16, 
4226
    /* BIT8rp */
4227
    GR8, GR16, 
4228
    /* BIT8rr */
4229
    GR8, GR8, 
4230
    /* Bi */
4231
    i16imm, 
4232
    /* Bm */
4233
    GR16, i16imm, 
4234
    /* Br */
4235
    GR16, 
4236
    /* CALLi */
4237
    i16imm, 
4238
    /* CALLm */
4239
    GR16, i16imm, 
4240
    /* CALLn */
4241
    GR16, 
4242
    /* CALLp */
4243
    GR16, 
4244
    /* CALLr */
4245
    GR16, 
4246
    /* CMP16mc */
4247
    GR16, i16imm, cg16imm, 
4248
    /* CMP16mi */
4249
    GR16, i16imm, i16imm, 
4250
    /* CMP16mm */
4251
    GR16, i16imm, GR16, i16imm, 
4252
    /* CMP16mn */
4253
    GR16, i16imm, GR16, 
4254
    /* CMP16mp */
4255
    GR16, i16imm, GR16, 
4256
    /* CMP16mr */
4257
    GR16, i16imm, GR16, 
4258
    /* CMP16rc */
4259
    GR16, cg16imm, 
4260
    /* CMP16ri */
4261
    GR16, i16imm, 
4262
    /* CMP16rm */
4263
    GR16, GR16, i16imm, 
4264
    /* CMP16rn */
4265
    GR16, GR16, 
4266
    /* CMP16rp */
4267
    GR16, GR16, 
4268
    /* CMP16rr */
4269
    GR16, GR16, 
4270
    /* CMP8mc */
4271
    GR16, i16imm, cg8imm, 
4272
    /* CMP8mi */
4273
    GR16, i16imm, i8imm, 
4274
    /* CMP8mm */
4275
    GR16, i16imm, GR16, i16imm, 
4276
    /* CMP8mn */
4277
    GR16, i16imm, GR16, 
4278
    /* CMP8mp */
4279
    GR16, i16imm, GR16, 
4280
    /* CMP8mr */
4281
    GR16, i16imm, GR8, 
4282
    /* CMP8rc */
4283
    GR8, cg8imm, 
4284
    /* CMP8ri */
4285
    GR8, i8imm, 
4286
    /* CMP8rm */
4287
    GR8, GR16, i16imm, 
4288
    /* CMP8rn */
4289
    GR8, GR16, 
4290
    /* CMP8rp */
4291
    GR8, GR16, 
4292
    /* CMP8rr */
4293
    GR8, GR8, 
4294
    /* DADD16mc */
4295
    GR16, i16imm, cg16imm, 
4296
    /* DADD16mi */
4297
    GR16, i16imm, i16imm, 
4298
    /* DADD16mm */
4299
    GR16, i16imm, GR16, i16imm, 
4300
    /* DADD16mn */
4301
    GR16, i16imm, GR16, 
4302
    /* DADD16mp */
4303
    GR16, i16imm, GR16, 
4304
    /* DADD16mr */
4305
    GR16, i16imm, GR16, 
4306
    /* DADD16rc */
4307
    GR16, GR16, cg16imm, 
4308
    /* DADD16ri */
4309
    GR16, GR16, i16imm, 
4310
    /* DADD16rm */
4311
    GR16, GR16, GR16, i16imm, 
4312
    /* DADD16rn */
4313
    GR16, GR16, GR16, 
4314
    /* DADD16rp */
4315
    GR16, GR16, GR16, GR16, 
4316
    /* DADD16rr */
4317
    GR16, GR16, GR16, 
4318
    /* DADD8mc */
4319
    GR16, i16imm, cg8imm, 
4320
    /* DADD8mi */
4321
    GR16, i16imm, i8imm, 
4322
    /* DADD8mm */
4323
    GR16, i16imm, GR16, i16imm, 
4324
    /* DADD8mn */
4325
    GR16, i16imm, GR16, 
4326
    /* DADD8mp */
4327
    GR16, i16imm, GR16, 
4328
    /* DADD8mr */
4329
    GR16, i16imm, GR8, 
4330
    /* DADD8rc */
4331
    GR8, GR8, cg8imm, 
4332
    /* DADD8ri */
4333
    GR8, GR8, i8imm, 
4334
    /* DADD8rm */
4335
    GR8, GR8, GR16, i16imm, 
4336
    /* DADD8rn */
4337
    GR8, GR8, GR16, 
4338
    /* DADD8rp */
4339
    GR8, GR16, GR8, GR16, 
4340
    /* DADD8rr */
4341
    GR8, GR8, GR8, 
4342
    /* JCC */
4343
    jmptarget, cc, 
4344
    /* JMP */
4345
    jmptarget, 
4346
    /* MOV16mc */
4347
    GR16, i16imm, cg16imm, 
4348
    /* MOV16mi */
4349
    GR16, i16imm, i16imm, 
4350
    /* MOV16mm */
4351
    GR16, i16imm, GR16, i16imm, 
4352
    /* MOV16mn */
4353
    GR16, i16imm, GR16, 
4354
    /* MOV16mr */
4355
    GR16, i16imm, GR16, 
4356
    /* MOV16rc */
4357
    GR16, cg16imm, 
4358
    /* MOV16ri */
4359
    GR16, i16imm, 
4360
    /* MOV16rm */
4361
    GR16, GR16, i16imm, 
4362
    /* MOV16rn */
4363
    GR16, GR16, 
4364
    /* MOV16rp */
4365
    GR16, GR16, GR16, 
4366
    /* MOV16rr */
4367
    GR16, GR16, 
4368
    /* MOV8mc */
4369
    GR16, i16imm, cg8imm, 
4370
    /* MOV8mi */
4371
    GR16, i16imm, i8imm, 
4372
    /* MOV8mm */
4373
    GR16, i16imm, GR16, i16imm, 
4374
    /* MOV8mn */
4375
    GR16, i16imm, GR16, 
4376
    /* MOV8mr */
4377
    GR16, i16imm, GR8, 
4378
    /* MOV8rc */
4379
    GR8, cg8imm, 
4380
    /* MOV8ri */
4381
    GR8, i8imm, 
4382
    /* MOV8rm */
4383
    GR8, GR16, i16imm, 
4384
    /* MOV8rn */
4385
    GR8, GR16, 
4386
    /* MOV8rp */
4387
    GR8, GR16, GR16, 
4388
    /* MOV8rr */
4389
    GR8, GR8, 
4390
    /* MOVZX16rm8 */
4391
    GR16, GR16, i16imm, 
4392
    /* MOVZX16rr8 */
4393
    GR16, GR8, 
4394
    /* POP16r */
4395
    GR16, 
4396
    /* PUSH16c */
4397
    cg16imm, 
4398
    /* PUSH16i */
4399
    i16imm, 
4400
    /* PUSH16r */
4401
    GR16, 
4402
    /* PUSH8r */
4403
    GR8, 
4404
    /* RET */
4405
    /* RETI */
4406
    /* RRA16m */
4407
    GR16, i16imm, 
4408
    /* RRA16n */
4409
    GR16, 
4410
    /* RRA16p */
4411
    GR16, 
4412
    /* RRA16r */
4413
    GR16, GR16, 
4414
    /* RRA8m */
4415
    GR16, i16imm, 
4416
    /* RRA8n */
4417
    GR16, 
4418
    /* RRA8p */
4419
    GR16, 
4420
    /* RRA8r */
4421
    GR8, GR8, 
4422
    /* RRC16m */
4423
    GR16, i16imm, 
4424
    /* RRC16n */
4425
    GR16, 
4426
    /* RRC16p */
4427
    GR16, 
4428
    /* RRC16r */
4429
    GR16, GR16, 
4430
    /* RRC8m */
4431
    GR16, i16imm, 
4432
    /* RRC8n */
4433
    GR16, 
4434
    /* RRC8p */
4435
    GR16, 
4436
    /* RRC8r */
4437
    GR8, GR8, 
4438
    /* Rrcl16 */
4439
    GR16, GR16, 
4440
    /* Rrcl8 */
4441
    GR8, GR8, 
4442
    /* SEXT16m */
4443
    GR16, i16imm, 
4444
    /* SEXT16n */
4445
    GR16, 
4446
    /* SEXT16p */
4447
    GR16, 
4448
    /* SEXT16r */
4449
    GR16, GR16, 
4450
    /* SUB16mc */
4451
    GR16, i16imm, cg16imm, 
4452
    /* SUB16mi */
4453
    GR16, i16imm, i16imm, 
4454
    /* SUB16mm */
4455
    GR16, i16imm, GR16, i16imm, 
4456
    /* SUB16mn */
4457
    GR16, i16imm, GR16, 
4458
    /* SUB16mp */
4459
    GR16, i16imm, GR16, 
4460
    /* SUB16mr */
4461
    GR16, i16imm, GR16, 
4462
    /* SUB16rc */
4463
    GR16, GR16, cg16imm, 
4464
    /* SUB16ri */
4465
    GR16, GR16, i16imm, 
4466
    /* SUB16rm */
4467
    GR16, GR16, GR16, i16imm, 
4468
    /* SUB16rn */
4469
    GR16, GR16, GR16, 
4470
    /* SUB16rp */
4471
    GR16, GR16, GR16, GR16, 
4472
    /* SUB16rr */
4473
    GR16, GR16, GR16, 
4474
    /* SUB8mc */
4475
    GR16, i16imm, cg8imm, 
4476
    /* SUB8mi */
4477
    GR16, i16imm, i8imm, 
4478
    /* SUB8mm */
4479
    GR16, i16imm, GR16, i16imm, 
4480
    /* SUB8mn */
4481
    GR16, i16imm, GR16, 
4482
    /* SUB8mp */
4483
    GR16, i16imm, GR16, 
4484
    /* SUB8mr */
4485
    GR16, i16imm, GR8, 
4486
    /* SUB8rc */
4487
    GR8, GR8, cg8imm, 
4488
    /* SUB8ri */
4489
    GR8, GR8, i8imm, 
4490
    /* SUB8rm */
4491
    GR8, GR8, GR16, i16imm, 
4492
    /* SUB8rn */
4493
    GR8, GR8, GR16, 
4494
    /* SUB8rp */
4495
    GR8, GR16, GR8, GR16, 
4496
    /* SUB8rr */
4497
    GR8, GR8, GR8, 
4498
    /* SUBC16mc */
4499
    GR16, i16imm, cg16imm, 
4500
    /* SUBC16mi */
4501
    GR16, i16imm, i16imm, 
4502
    /* SUBC16mm */
4503
    GR16, i16imm, GR16, i16imm, 
4504
    /* SUBC16mn */
4505
    GR16, i16imm, GR16, 
4506
    /* SUBC16mp */
4507
    GR16, i16imm, GR16, 
4508
    /* SUBC16mr */
4509
    GR16, i16imm, GR16, 
4510
    /* SUBC16rc */
4511
    GR16, GR16, cg16imm, 
4512
    /* SUBC16ri */
4513
    GR16, GR16, i16imm, 
4514
    /* SUBC16rm */
4515
    GR16, GR16, GR16, i16imm, 
4516
    /* SUBC16rn */
4517
    GR16, GR16, GR16, 
4518
    /* SUBC16rp */
4519
    GR16, GR16, GR16, GR16, 
4520
    /* SUBC16rr */
4521
    GR16, GR16, GR16, 
4522
    /* SUBC8mc */
4523
    GR16, i16imm, cg8imm, 
4524
    /* SUBC8mi */
4525
    GR16, i16imm, i8imm, 
4526
    /* SUBC8mm */
4527
    GR16, i16imm, GR16, i16imm, 
4528
    /* SUBC8mn */
4529
    GR16, i16imm, GR16, 
4530
    /* SUBC8mp */
4531
    GR16, i16imm, GR16, 
4532
    /* SUBC8mr */
4533
    GR16, i16imm, GR8, 
4534
    /* SUBC8rc */
4535
    GR8, GR8, cg8imm, 
4536
    /* SUBC8ri */
4537
    GR8, GR8, i8imm, 
4538
    /* SUBC8rm */
4539
    GR8, GR8, GR16, i16imm, 
4540
    /* SUBC8rn */
4541
    GR8, GR8, GR16, 
4542
    /* SUBC8rp */
4543
    GR8, GR16, GR8, GR16, 
4544
    /* SUBC8rr */
4545
    GR8, GR8, GR8, 
4546
    /* SWPB16m */
4547
    GR16, i16imm, 
4548
    /* SWPB16n */
4549
    GR16, 
4550
    /* SWPB16p */
4551
    GR16, 
4552
    /* SWPB16r */
4553
    GR16, GR16, 
4554
    /* Select16 */
4555
    GR16, GR16, GR16, i8imm, 
4556
    /* Select8 */
4557
    GR8, GR8, GR8, i8imm, 
4558
    /* Shl16 */
4559
    GR16, GR16, GR8, 
4560
    /* Shl8 */
4561
    GR8, GR8, GR8, 
4562
    /* Sra16 */
4563
    GR16, GR16, GR8, 
4564
    /* Sra8 */
4565
    GR8, GR8, GR8, 
4566
    /* Srl16 */
4567
    GR16, GR16, GR8, 
4568
    /* Srl8 */
4569
    GR8, GR8, GR8, 
4570
    /* XOR16mc */
4571
    GR16, i16imm, cg16imm, 
4572
    /* XOR16mi */
4573
    GR16, i16imm, i16imm, 
4574
    /* XOR16mm */
4575
    GR16, i16imm, GR16, i16imm, 
4576
    /* XOR16mn */
4577
    GR16, i16imm, GR16, 
4578
    /* XOR16mp */
4579
    GR16, i16imm, GR16, 
4580
    /* XOR16mr */
4581
    GR16, i16imm, GR16, 
4582
    /* XOR16rc */
4583
    GR16, GR16, cg16imm, 
4584
    /* XOR16ri */
4585
    GR16, GR16, i16imm, 
4586
    /* XOR16rm */
4587
    GR16, GR16, GR16, i16imm, 
4588
    /* XOR16rn */
4589
    GR16, GR16, GR16, 
4590
    /* XOR16rp */
4591
    GR16, GR16, GR16, GR16, 
4592
    /* XOR16rr */
4593
    GR16, GR16, GR16, 
4594
    /* XOR8mc */
4595
    GR16, i16imm, cg8imm, 
4596
    /* XOR8mi */
4597
    GR16, i16imm, i8imm, 
4598
    /* XOR8mm */
4599
    GR16, i16imm, GR16, i16imm, 
4600
    /* XOR8mn */
4601
    GR16, i16imm, GR16, 
4602
    /* XOR8mp */
4603
    GR16, i16imm, GR16, 
4604
    /* XOR8mr */
4605
    GR16, i16imm, GR8, 
4606
    /* XOR8rc */
4607
    GR8, GR8, cg8imm, 
4608
    /* XOR8ri */
4609
    GR8, GR8, i8imm, 
4610
    /* XOR8rm */
4611
    GR8, GR8, GR16, i16imm, 
4612
    /* XOR8rn */
4613
    GR8, GR8, GR16, 
4614
    /* XOR8rp */
4615
    GR8, GR16, GR8, GR16, 
4616
    /* XOR8rr */
4617
    GR8, GR8, GR8, 
4618
    /* ZEXT16r */
4619
    GR16, GR16, 
4620
  };
4621
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
4622
}
4623
} // end namespace MSP430
4624
} // end namespace llvm
4625
#endif // GET_INSTRINFO_OPERAND_TYPE
4626
4627
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
4628
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
4629
namespace llvm {
4630
namespace MSP430 {
4631
LLVM_READONLY
4632
static int getMemOperandSize(int OpType) {
4633
  switch (OpType) {
4634
  default: return 0;
4635
  }
4636
}
4637
} // end namespace MSP430
4638
} // end namespace llvm
4639
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
4640
4641
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
4642
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
4643
namespace llvm {
4644
namespace MSP430 {
4645
LLVM_READONLY static unsigned
4646
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
4647
  return LogicalOpIdx;
4648
}
4649
LLVM_READONLY static inline unsigned
4650
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
4651
  auto S = 0U;
4652
  for (auto i = 0U; i < LogicalOpIdx; ++i)
4653
    S += getLogicalOperandSize(Opcode, i);
4654
  return S;
4655
}
4656
} // end namespace MSP430
4657
} // end namespace llvm
4658
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
4659
4660
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
4661
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
4662
namespace llvm {
4663
namespace MSP430 {
4664
LLVM_READONLY static int
4665
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
4666
  return -1;
4667
}
4668
} // end namespace MSP430
4669
} // end namespace llvm
4670
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
4671
4672
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
4673
#undef GET_INSTRINFO_MC_HELPER_DECLS
4674
4675
namespace llvm {
4676
class MCInst;
4677
class FeatureBitset;
4678
4679
namespace MSP430_MC {
4680
4681
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
4682
4683
} // end namespace MSP430_MC
4684
} // end namespace llvm
4685
4686
#endif // GET_INSTRINFO_MC_HELPER_DECLS
4687
4688
#ifdef GET_INSTRINFO_MC_HELPERS
4689
#undef GET_INSTRINFO_MC_HELPERS
4690
4691
namespace llvm {
4692
namespace MSP430_MC {
4693
4694
} // end namespace MSP430_MC
4695
} // end namespace llvm
4696
4697
#endif // GET_GENISTRINFO_MC_HELPERS
4698
4699
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
4700
    defined(GET_AVAILABLE_OPCODE_CHECKER)
4701
#define GET_COMPUTE_FEATURES
4702
#endif
4703
#ifdef GET_COMPUTE_FEATURES
4704
#undef GET_COMPUTE_FEATURES
4705
namespace llvm {
4706
namespace MSP430_MC {
4707
4708
// Bits for subtarget features that participate in instruction matching.
4709
enum SubtargetFeatureBits : uint8_t {
4710
};
4711
4712
0
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
4713
0
  FeatureBitset Features;
4714
0
  return Features;
4715
0
}
4716
4717
0
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
4718
0
  enum : uint8_t {
4719
0
    CEFBS_None,
4720
0
  };
4721
4722
0
  static constexpr FeatureBitset FeatureBitsets[] = {
4723
0
    {}, // CEFBS_None
4724
0
  };
4725
0
  static constexpr uint8_t RequiredFeaturesRefs[] = {
4726
0
    CEFBS_None, // PHI = 0
4727
0
    CEFBS_None, // INLINEASM = 1
4728
0
    CEFBS_None, // INLINEASM_BR = 2
4729
0
    CEFBS_None, // CFI_INSTRUCTION = 3
4730
0
    CEFBS_None, // EH_LABEL = 4
4731
0
    CEFBS_None, // GC_LABEL = 5
4732
0
    CEFBS_None, // ANNOTATION_LABEL = 6
4733
0
    CEFBS_None, // KILL = 7
4734
0
    CEFBS_None, // EXTRACT_SUBREG = 8
4735
0
    CEFBS_None, // INSERT_SUBREG = 9
4736
0
    CEFBS_None, // IMPLICIT_DEF = 10
4737
0
    CEFBS_None, // SUBREG_TO_REG = 11
4738
0
    CEFBS_None, // COPY_TO_REGCLASS = 12
4739
0
    CEFBS_None, // DBG_VALUE = 13
4740
0
    CEFBS_None, // DBG_VALUE_LIST = 14
4741
0
    CEFBS_None, // DBG_INSTR_REF = 15
4742
0
    CEFBS_None, // DBG_PHI = 16
4743
0
    CEFBS_None, // DBG_LABEL = 17
4744
0
    CEFBS_None, // REG_SEQUENCE = 18
4745
0
    CEFBS_None, // COPY = 19
4746
0
    CEFBS_None, // BUNDLE = 20
4747
0
    CEFBS_None, // LIFETIME_START = 21
4748
0
    CEFBS_None, // LIFETIME_END = 22
4749
0
    CEFBS_None, // PSEUDO_PROBE = 23
4750
0
    CEFBS_None, // ARITH_FENCE = 24
4751
0
    CEFBS_None, // STACKMAP = 25
4752
0
    CEFBS_None, // FENTRY_CALL = 26
4753
0
    CEFBS_None, // PATCHPOINT = 27
4754
0
    CEFBS_None, // LOAD_STACK_GUARD = 28
4755
0
    CEFBS_None, // PREALLOCATED_SETUP = 29
4756
0
    CEFBS_None, // PREALLOCATED_ARG = 30
4757
0
    CEFBS_None, // STATEPOINT = 31
4758
0
    CEFBS_None, // LOCAL_ESCAPE = 32
4759
0
    CEFBS_None, // FAULTING_OP = 33
4760
0
    CEFBS_None, // PATCHABLE_OP = 34
4761
0
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
4762
0
    CEFBS_None, // PATCHABLE_RET = 36
4763
0
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
4764
0
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
4765
0
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
4766
0
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
4767
0
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
4768
0
    CEFBS_None, // MEMBARRIER = 42
4769
0
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
4770
0
    CEFBS_None, // G_ASSERT_SEXT = 44
4771
0
    CEFBS_None, // G_ASSERT_ZEXT = 45
4772
0
    CEFBS_None, // G_ASSERT_ALIGN = 46
4773
0
    CEFBS_None, // G_ADD = 47
4774
0
    CEFBS_None, // G_SUB = 48
4775
0
    CEFBS_None, // G_MUL = 49
4776
0
    CEFBS_None, // G_SDIV = 50
4777
0
    CEFBS_None, // G_UDIV = 51
4778
0
    CEFBS_None, // G_SREM = 52
4779
0
    CEFBS_None, // G_UREM = 53
4780
0
    CEFBS_None, // G_SDIVREM = 54
4781
0
    CEFBS_None, // G_UDIVREM = 55
4782
0
    CEFBS_None, // G_AND = 56
4783
0
    CEFBS_None, // G_OR = 57
4784
0
    CEFBS_None, // G_XOR = 58
4785
0
    CEFBS_None, // G_IMPLICIT_DEF = 59
4786
0
    CEFBS_None, // G_PHI = 60
4787
0
    CEFBS_None, // G_FRAME_INDEX = 61
4788
0
    CEFBS_None, // G_GLOBAL_VALUE = 62
4789
0
    CEFBS_None, // G_CONSTANT_POOL = 63
4790
0
    CEFBS_None, // G_EXTRACT = 64
4791
0
    CEFBS_None, // G_UNMERGE_VALUES = 65
4792
0
    CEFBS_None, // G_INSERT = 66
4793
0
    CEFBS_None, // G_MERGE_VALUES = 67
4794
0
    CEFBS_None, // G_BUILD_VECTOR = 68
4795
0
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
4796
0
    CEFBS_None, // G_CONCAT_VECTORS = 70
4797
0
    CEFBS_None, // G_PTRTOINT = 71
4798
0
    CEFBS_None, // G_INTTOPTR = 72
4799
0
    CEFBS_None, // G_BITCAST = 73
4800
0
    CEFBS_None, // G_FREEZE = 74
4801
0
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
4802
0
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
4803
0
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
4804
0
    CEFBS_None, // G_INTRINSIC_ROUND = 78
4805
0
    CEFBS_None, // G_INTRINSIC_LRINT = 79
4806
0
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
4807
0
    CEFBS_None, // G_READCYCLECOUNTER = 81
4808
0
    CEFBS_None, // G_LOAD = 82
4809
0
    CEFBS_None, // G_SEXTLOAD = 83
4810
0
    CEFBS_None, // G_ZEXTLOAD = 84
4811
0
    CEFBS_None, // G_INDEXED_LOAD = 85
4812
0
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
4813
0
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
4814
0
    CEFBS_None, // G_STORE = 88
4815
0
    CEFBS_None, // G_INDEXED_STORE = 89
4816
0
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
4817
0
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
4818
0
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
4819
0
    CEFBS_None, // G_ATOMICRMW_ADD = 93
4820
0
    CEFBS_None, // G_ATOMICRMW_SUB = 94
4821
0
    CEFBS_None, // G_ATOMICRMW_AND = 95
4822
0
    CEFBS_None, // G_ATOMICRMW_NAND = 96
4823
0
    CEFBS_None, // G_ATOMICRMW_OR = 97
4824
0
    CEFBS_None, // G_ATOMICRMW_XOR = 98
4825
0
    CEFBS_None, // G_ATOMICRMW_MAX = 99
4826
0
    CEFBS_None, // G_ATOMICRMW_MIN = 100
4827
0
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
4828
0
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
4829
0
    CEFBS_None, // G_ATOMICRMW_FADD = 103
4830
0
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
4831
0
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
4832
0
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
4833
0
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
4834
0
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
4835
0
    CEFBS_None, // G_FENCE = 109
4836
0
    CEFBS_None, // G_PREFETCH = 110
4837
0
    CEFBS_None, // G_BRCOND = 111
4838
0
    CEFBS_None, // G_BRINDIRECT = 112
4839
0
    CEFBS_None, // G_INVOKE_REGION_START = 113
4840
0
    CEFBS_None, // G_INTRINSIC = 114
4841
0
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
4842
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
4843
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
4844
0
    CEFBS_None, // G_ANYEXT = 118
4845
0
    CEFBS_None, // G_TRUNC = 119
4846
0
    CEFBS_None, // G_CONSTANT = 120
4847
0
    CEFBS_None, // G_FCONSTANT = 121
4848
0
    CEFBS_None, // G_VASTART = 122
4849
0
    CEFBS_None, // G_VAARG = 123
4850
0
    CEFBS_None, // G_SEXT = 124
4851
0
    CEFBS_None, // G_SEXT_INREG = 125
4852
0
    CEFBS_None, // G_ZEXT = 126
4853
0
    CEFBS_None, // G_SHL = 127
4854
0
    CEFBS_None, // G_LSHR = 128
4855
0
    CEFBS_None, // G_ASHR = 129
4856
0
    CEFBS_None, // G_FSHL = 130
4857
0
    CEFBS_None, // G_FSHR = 131
4858
0
    CEFBS_None, // G_ROTR = 132
4859
0
    CEFBS_None, // G_ROTL = 133
4860
0
    CEFBS_None, // G_ICMP = 134
4861
0
    CEFBS_None, // G_FCMP = 135
4862
0
    CEFBS_None, // G_SELECT = 136
4863
0
    CEFBS_None, // G_UADDO = 137
4864
0
    CEFBS_None, // G_UADDE = 138
4865
0
    CEFBS_None, // G_USUBO = 139
4866
0
    CEFBS_None, // G_USUBE = 140
4867
0
    CEFBS_None, // G_SADDO = 141
4868
0
    CEFBS_None, // G_SADDE = 142
4869
0
    CEFBS_None, // G_SSUBO = 143
4870
0
    CEFBS_None, // G_SSUBE = 144
4871
0
    CEFBS_None, // G_UMULO = 145
4872
0
    CEFBS_None, // G_SMULO = 146
4873
0
    CEFBS_None, // G_UMULH = 147
4874
0
    CEFBS_None, // G_SMULH = 148
4875
0
    CEFBS_None, // G_UADDSAT = 149
4876
0
    CEFBS_None, // G_SADDSAT = 150
4877
0
    CEFBS_None, // G_USUBSAT = 151
4878
0
    CEFBS_None, // G_SSUBSAT = 152
4879
0
    CEFBS_None, // G_USHLSAT = 153
4880
0
    CEFBS_None, // G_SSHLSAT = 154
4881
0
    CEFBS_None, // G_SMULFIX = 155
4882
0
    CEFBS_None, // G_UMULFIX = 156
4883
0
    CEFBS_None, // G_SMULFIXSAT = 157
4884
0
    CEFBS_None, // G_UMULFIXSAT = 158
4885
0
    CEFBS_None, // G_SDIVFIX = 159
4886
0
    CEFBS_None, // G_UDIVFIX = 160
4887
0
    CEFBS_None, // G_SDIVFIXSAT = 161
4888
0
    CEFBS_None, // G_UDIVFIXSAT = 162
4889
0
    CEFBS_None, // G_FADD = 163
4890
0
    CEFBS_None, // G_FSUB = 164
4891
0
    CEFBS_None, // G_FMUL = 165
4892
0
    CEFBS_None, // G_FMA = 166
4893
0
    CEFBS_None, // G_FMAD = 167
4894
0
    CEFBS_None, // G_FDIV = 168
4895
0
    CEFBS_None, // G_FREM = 169
4896
0
    CEFBS_None, // G_FPOW = 170
4897
0
    CEFBS_None, // G_FPOWI = 171
4898
0
    CEFBS_None, // G_FEXP = 172
4899
0
    CEFBS_None, // G_FEXP2 = 173
4900
0
    CEFBS_None, // G_FEXP10 = 174
4901
0
    CEFBS_None, // G_FLOG = 175
4902
0
    CEFBS_None, // G_FLOG2 = 176
4903
0
    CEFBS_None, // G_FLOG10 = 177
4904
0
    CEFBS_None, // G_FLDEXP = 178
4905
0
    CEFBS_None, // G_FFREXP = 179
4906
0
    CEFBS_None, // G_FNEG = 180
4907
0
    CEFBS_None, // G_FPEXT = 181
4908
0
    CEFBS_None, // G_FPTRUNC = 182
4909
0
    CEFBS_None, // G_FPTOSI = 183
4910
0
    CEFBS_None, // G_FPTOUI = 184
4911
0
    CEFBS_None, // G_SITOFP = 185
4912
0
    CEFBS_None, // G_UITOFP = 186
4913
0
    CEFBS_None, // G_FABS = 187
4914
0
    CEFBS_None, // G_FCOPYSIGN = 188
4915
0
    CEFBS_None, // G_IS_FPCLASS = 189
4916
0
    CEFBS_None, // G_FCANONICALIZE = 190
4917
0
    CEFBS_None, // G_FMINNUM = 191
4918
0
    CEFBS_None, // G_FMAXNUM = 192
4919
0
    CEFBS_None, // G_FMINNUM_IEEE = 193
4920
0
    CEFBS_None, // G_FMAXNUM_IEEE = 194
4921
0
    CEFBS_None, // G_FMINIMUM = 195
4922
0
    CEFBS_None, // G_FMAXIMUM = 196
4923
0
    CEFBS_None, // G_GET_FPENV = 197
4924
0
    CEFBS_None, // G_SET_FPENV = 198
4925
0
    CEFBS_None, // G_RESET_FPENV = 199
4926
0
    CEFBS_None, // G_GET_FPMODE = 200
4927
0
    CEFBS_None, // G_SET_FPMODE = 201
4928
0
    CEFBS_None, // G_RESET_FPMODE = 202
4929
0
    CEFBS_None, // G_PTR_ADD = 203
4930
0
    CEFBS_None, // G_PTRMASK = 204
4931
0
    CEFBS_None, // G_SMIN = 205
4932
0
    CEFBS_None, // G_SMAX = 206
4933
0
    CEFBS_None, // G_UMIN = 207
4934
0
    CEFBS_None, // G_UMAX = 208
4935
0
    CEFBS_None, // G_ABS = 209
4936
0
    CEFBS_None, // G_LROUND = 210
4937
0
    CEFBS_None, // G_LLROUND = 211
4938
0
    CEFBS_None, // G_BR = 212
4939
0
    CEFBS_None, // G_BRJT = 213
4940
0
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
4941
0
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
4942
0
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
4943
0
    CEFBS_None, // G_CTTZ = 217
4944
0
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
4945
0
    CEFBS_None, // G_CTLZ = 219
4946
0
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
4947
0
    CEFBS_None, // G_CTPOP = 221
4948
0
    CEFBS_None, // G_BSWAP = 222
4949
0
    CEFBS_None, // G_BITREVERSE = 223
4950
0
    CEFBS_None, // G_FCEIL = 224
4951
0
    CEFBS_None, // G_FCOS = 225
4952
0
    CEFBS_None, // G_FSIN = 226
4953
0
    CEFBS_None, // G_FSQRT = 227
4954
0
    CEFBS_None, // G_FFLOOR = 228
4955
0
    CEFBS_None, // G_FRINT = 229
4956
0
    CEFBS_None, // G_FNEARBYINT = 230
4957
0
    CEFBS_None, // G_ADDRSPACE_CAST = 231
4958
0
    CEFBS_None, // G_BLOCK_ADDR = 232
4959
0
    CEFBS_None, // G_JUMP_TABLE = 233
4960
0
    CEFBS_None, // G_DYN_STACKALLOC = 234
4961
0
    CEFBS_None, // G_STACKSAVE = 235
4962
0
    CEFBS_None, // G_STACKRESTORE = 236
4963
0
    CEFBS_None, // G_STRICT_FADD = 237
4964
0
    CEFBS_None, // G_STRICT_FSUB = 238
4965
0
    CEFBS_None, // G_STRICT_FMUL = 239
4966
0
    CEFBS_None, // G_STRICT_FDIV = 240
4967
0
    CEFBS_None, // G_STRICT_FREM = 241
4968
0
    CEFBS_None, // G_STRICT_FMA = 242
4969
0
    CEFBS_None, // G_STRICT_FSQRT = 243
4970
0
    CEFBS_None, // G_STRICT_FLDEXP = 244
4971
0
    CEFBS_None, // G_READ_REGISTER = 245
4972
0
    CEFBS_None, // G_WRITE_REGISTER = 246
4973
0
    CEFBS_None, // G_MEMCPY = 247
4974
0
    CEFBS_None, // G_MEMCPY_INLINE = 248
4975
0
    CEFBS_None, // G_MEMMOVE = 249
4976
0
    CEFBS_None, // G_MEMSET = 250
4977
0
    CEFBS_None, // G_BZERO = 251
4978
0
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
4979
0
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
4980
0
    CEFBS_None, // G_VECREDUCE_FADD = 254
4981
0
    CEFBS_None, // G_VECREDUCE_FMUL = 255
4982
0
    CEFBS_None, // G_VECREDUCE_FMAX = 256
4983
0
    CEFBS_None, // G_VECREDUCE_FMIN = 257
4984
0
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
4985
0
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
4986
0
    CEFBS_None, // G_VECREDUCE_ADD = 260
4987
0
    CEFBS_None, // G_VECREDUCE_MUL = 261
4988
0
    CEFBS_None, // G_VECREDUCE_AND = 262
4989
0
    CEFBS_None, // G_VECREDUCE_OR = 263
4990
0
    CEFBS_None, // G_VECREDUCE_XOR = 264
4991
0
    CEFBS_None, // G_VECREDUCE_SMAX = 265
4992
0
    CEFBS_None, // G_VECREDUCE_SMIN = 266
4993
0
    CEFBS_None, // G_VECREDUCE_UMAX = 267
4994
0
    CEFBS_None, // G_VECREDUCE_UMIN = 268
4995
0
    CEFBS_None, // G_SBFX = 269
4996
0
    CEFBS_None, // G_UBFX = 270
4997
0
    CEFBS_None, // ADD16mc = 271
4998
0
    CEFBS_None, // ADD16mi = 272
4999
0
    CEFBS_None, // ADD16mm = 273
5000
0
    CEFBS_None, // ADD16mn = 274
5001
0
    CEFBS_None, // ADD16mp = 275
5002
0
    CEFBS_None, // ADD16mr = 276
5003
0
    CEFBS_None, // ADD16rc = 277
5004
0
    CEFBS_None, // ADD16ri = 278
5005
0
    CEFBS_None, // ADD16rm = 279
5006
0
    CEFBS_None, // ADD16rn = 280
5007
0
    CEFBS_None, // ADD16rp = 281
5008
0
    CEFBS_None, // ADD16rr = 282
5009
0
    CEFBS_None, // ADD8mc = 283
5010
0
    CEFBS_None, // ADD8mi = 284
5011
0
    CEFBS_None, // ADD8mm = 285
5012
0
    CEFBS_None, // ADD8mn = 286
5013
0
    CEFBS_None, // ADD8mp = 287
5014
0
    CEFBS_None, // ADD8mr = 288
5015
0
    CEFBS_None, // ADD8rc = 289
5016
0
    CEFBS_None, // ADD8ri = 290
5017
0
    CEFBS_None, // ADD8rm = 291
5018
0
    CEFBS_None, // ADD8rn = 292
5019
0
    CEFBS_None, // ADD8rp = 293
5020
0
    CEFBS_None, // ADD8rr = 294
5021
0
    CEFBS_None, // ADDC16mc = 295
5022
0
    CEFBS_None, // ADDC16mi = 296
5023
0
    CEFBS_None, // ADDC16mm = 297
5024
0
    CEFBS_None, // ADDC16mn = 298
5025
0
    CEFBS_None, // ADDC16mp = 299
5026
0
    CEFBS_None, // ADDC16mr = 300
5027
0
    CEFBS_None, // ADDC16rc = 301
5028
0
    CEFBS_None, // ADDC16ri = 302
5029
0
    CEFBS_None, // ADDC16rm = 303
5030
0
    CEFBS_None, // ADDC16rn = 304
5031
0
    CEFBS_None, // ADDC16rp = 305
5032
0
    CEFBS_None, // ADDC16rr = 306
5033
0
    CEFBS_None, // ADDC8mc = 307
5034
0
    CEFBS_None, // ADDC8mi = 308
5035
0
    CEFBS_None, // ADDC8mm = 309
5036
0
    CEFBS_None, // ADDC8mn = 310
5037
0
    CEFBS_None, // ADDC8mp = 311
5038
0
    CEFBS_None, // ADDC8mr = 312
5039
0
    CEFBS_None, // ADDC8rc = 313
5040
0
    CEFBS_None, // ADDC8ri = 314
5041
0
    CEFBS_None, // ADDC8rm = 315
5042
0
    CEFBS_None, // ADDC8rn = 316
5043
0
    CEFBS_None, // ADDC8rp = 317
5044
0
    CEFBS_None, // ADDC8rr = 318
5045
0
    CEFBS_None, // ADDframe = 319
5046
0
    CEFBS_None, // ADJCALLSTACKDOWN = 320
5047
0
    CEFBS_None, // ADJCALLSTACKUP = 321
5048
0
    CEFBS_None, // AND16mc = 322
5049
0
    CEFBS_None, // AND16mi = 323
5050
0
    CEFBS_None, // AND16mm = 324
5051
0
    CEFBS_None, // AND16mn = 325
5052
0
    CEFBS_None, // AND16mp = 326
5053
0
    CEFBS_None, // AND16mr = 327
5054
0
    CEFBS_None, // AND16rc = 328
5055
0
    CEFBS_None, // AND16ri = 329
5056
0
    CEFBS_None, // AND16rm = 330
5057
0
    CEFBS_None, // AND16rn = 331
5058
0
    CEFBS_None, // AND16rp = 332
5059
0
    CEFBS_None, // AND16rr = 333
5060
0
    CEFBS_None, // AND8mc = 334
5061
0
    CEFBS_None, // AND8mi = 335
5062
0
    CEFBS_None, // AND8mm = 336
5063
0
    CEFBS_None, // AND8mn = 337
5064
0
    CEFBS_None, // AND8mp = 338
5065
0
    CEFBS_None, // AND8mr = 339
5066
0
    CEFBS_None, // AND8rc = 340
5067
0
    CEFBS_None, // AND8ri = 341
5068
0
    CEFBS_None, // AND8rm = 342
5069
0
    CEFBS_None, // AND8rn = 343
5070
0
    CEFBS_None, // AND8rp = 344
5071
0
    CEFBS_None, // AND8rr = 345
5072
0
    CEFBS_None, // BIC16mc = 346
5073
0
    CEFBS_None, // BIC16mi = 347
5074
0
    CEFBS_None, // BIC16mm = 348
5075
0
    CEFBS_None, // BIC16mn = 349
5076
0
    CEFBS_None, // BIC16mp = 350
5077
0
    CEFBS_None, // BIC16mr = 351
5078
0
    CEFBS_None, // BIC16rc = 352
5079
0
    CEFBS_None, // BIC16ri = 353
5080
0
    CEFBS_None, // BIC16rm = 354
5081
0
    CEFBS_None, // BIC16rn = 355
5082
0
    CEFBS_None, // BIC16rp = 356
5083
0
    CEFBS_None, // BIC16rr = 357
5084
0
    CEFBS_None, // BIC8mc = 358
5085
0
    CEFBS_None, // BIC8mi = 359
5086
0
    CEFBS_None, // BIC8mm = 360
5087
0
    CEFBS_None, // BIC8mn = 361
5088
0
    CEFBS_None, // BIC8mp = 362
5089
0
    CEFBS_None, // BIC8mr = 363
5090
0
    CEFBS_None, // BIC8rc = 364
5091
0
    CEFBS_None, // BIC8ri = 365
5092
0
    CEFBS_None, // BIC8rm = 366
5093
0
    CEFBS_None, // BIC8rn = 367
5094
0
    CEFBS_None, // BIC8rp = 368
5095
0
    CEFBS_None, // BIC8rr = 369
5096
0
    CEFBS_None, // BIS16mc = 370
5097
0
    CEFBS_None, // BIS16mi = 371
5098
0
    CEFBS_None, // BIS16mm = 372
5099
0
    CEFBS_None, // BIS16mn = 373
5100
0
    CEFBS_None, // BIS16mp = 374
5101
0
    CEFBS_None, // BIS16mr = 375
5102
0
    CEFBS_None, // BIS16rc = 376
5103
0
    CEFBS_None, // BIS16ri = 377
5104
0
    CEFBS_None, // BIS16rm = 378
5105
0
    CEFBS_None, // BIS16rn = 379
5106
0
    CEFBS_None, // BIS16rp = 380
5107
0
    CEFBS_None, // BIS16rr = 381
5108
0
    CEFBS_None, // BIS8mc = 382
5109
0
    CEFBS_None, // BIS8mi = 383
5110
0
    CEFBS_None, // BIS8mm = 384
5111
0
    CEFBS_None, // BIS8mn = 385
5112
0
    CEFBS_None, // BIS8mp = 386
5113
0
    CEFBS_None, // BIS8mr = 387
5114
0
    CEFBS_None, // BIS8rc = 388
5115
0
    CEFBS_None, // BIS8ri = 389
5116
0
    CEFBS_None, // BIS8rm = 390
5117
0
    CEFBS_None, // BIS8rn = 391
5118
0
    CEFBS_None, // BIS8rp = 392
5119
0
    CEFBS_None, // BIS8rr = 393
5120
0
    CEFBS_None, // BIT16mc = 394
5121
0
    CEFBS_None, // BIT16mi = 395
5122
0
    CEFBS_None, // BIT16mm = 396
5123
0
    CEFBS_None, // BIT16mn = 397
5124
0
    CEFBS_None, // BIT16mp = 398
5125
0
    CEFBS_None, // BIT16mr = 399
5126
0
    CEFBS_None, // BIT16rc = 400
5127
0
    CEFBS_None, // BIT16ri = 401
5128
0
    CEFBS_None, // BIT16rm = 402
5129
0
    CEFBS_None, // BIT16rn = 403
5130
0
    CEFBS_None, // BIT16rp = 404
5131
0
    CEFBS_None, // BIT16rr = 405
5132
0
    CEFBS_None, // BIT8mc = 406
5133
0
    CEFBS_None, // BIT8mi = 407
5134
0
    CEFBS_None, // BIT8mm = 408
5135
0
    CEFBS_None, // BIT8mn = 409
5136
0
    CEFBS_None, // BIT8mp = 410
5137
0
    CEFBS_None, // BIT8mr = 411
5138
0
    CEFBS_None, // BIT8rc = 412
5139
0
    CEFBS_None, // BIT8ri = 413
5140
0
    CEFBS_None, // BIT8rm = 414
5141
0
    CEFBS_None, // BIT8rn = 415
5142
0
    CEFBS_None, // BIT8rp = 416
5143
0
    CEFBS_None, // BIT8rr = 417
5144
0
    CEFBS_None, // Bi = 418
5145
0
    CEFBS_None, // Bm = 419
5146
0
    CEFBS_None, // Br = 420
5147
0
    CEFBS_None, // CALLi = 421
5148
0
    CEFBS_None, // CALLm = 422
5149
0
    CEFBS_None, // CALLn = 423
5150
0
    CEFBS_None, // CALLp = 424
5151
0
    CEFBS_None, // CALLr = 425
5152
0
    CEFBS_None, // CMP16mc = 426
5153
0
    CEFBS_None, // CMP16mi = 427
5154
0
    CEFBS_None, // CMP16mm = 428
5155
0
    CEFBS_None, // CMP16mn = 429
5156
0
    CEFBS_None, // CMP16mp = 430
5157
0
    CEFBS_None, // CMP16mr = 431
5158
0
    CEFBS_None, // CMP16rc = 432
5159
0
    CEFBS_None, // CMP16ri = 433
5160
0
    CEFBS_None, // CMP16rm = 434
5161
0
    CEFBS_None, // CMP16rn = 435
5162
0
    CEFBS_None, // CMP16rp = 436
5163
0
    CEFBS_None, // CMP16rr = 437
5164
0
    CEFBS_None, // CMP8mc = 438
5165
0
    CEFBS_None, // CMP8mi = 439
5166
0
    CEFBS_None, // CMP8mm = 440
5167
0
    CEFBS_None, // CMP8mn = 441
5168
0
    CEFBS_None, // CMP8mp = 442
5169
0
    CEFBS_None, // CMP8mr = 443
5170
0
    CEFBS_None, // CMP8rc = 444
5171
0
    CEFBS_None, // CMP8ri = 445
5172
0
    CEFBS_None, // CMP8rm = 446
5173
0
    CEFBS_None, // CMP8rn = 447
5174
0
    CEFBS_None, // CMP8rp = 448
5175
0
    CEFBS_None, // CMP8rr = 449
5176
0
    CEFBS_None, // DADD16mc = 450
5177
0
    CEFBS_None, // DADD16mi = 451
5178
0
    CEFBS_None, // DADD16mm = 452
5179
0
    CEFBS_None, // DADD16mn = 453
5180
0
    CEFBS_None, // DADD16mp = 454
5181
0
    CEFBS_None, // DADD16mr = 455
5182
0
    CEFBS_None, // DADD16rc = 456
5183
0
    CEFBS_None, // DADD16ri = 457
5184
0
    CEFBS_None, // DADD16rm = 458
5185
0
    CEFBS_None, // DADD16rn = 459
5186
0
    CEFBS_None, // DADD16rp = 460
5187
0
    CEFBS_None, // DADD16rr = 461
5188
0
    CEFBS_None, // DADD8mc = 462
5189
0
    CEFBS_None, // DADD8mi = 463
5190
0
    CEFBS_None, // DADD8mm = 464
5191
0
    CEFBS_None, // DADD8mn = 465
5192
0
    CEFBS_None, // DADD8mp = 466
5193
0
    CEFBS_None, // DADD8mr = 467
5194
0
    CEFBS_None, // DADD8rc = 468
5195
0
    CEFBS_None, // DADD8ri = 469
5196
0
    CEFBS_None, // DADD8rm = 470
5197
0
    CEFBS_None, // DADD8rn = 471
5198
0
    CEFBS_None, // DADD8rp = 472
5199
0
    CEFBS_None, // DADD8rr = 473
5200
0
    CEFBS_None, // JCC = 474
5201
0
    CEFBS_None, // JMP = 475
5202
0
    CEFBS_None, // MOV16mc = 476
5203
0
    CEFBS_None, // MOV16mi = 477
5204
0
    CEFBS_None, // MOV16mm = 478
5205
0
    CEFBS_None, // MOV16mn = 479
5206
0
    CEFBS_None, // MOV16mr = 480
5207
0
    CEFBS_None, // MOV16rc = 481
5208
0
    CEFBS_None, // MOV16ri = 482
5209
0
    CEFBS_None, // MOV16rm = 483
5210
0
    CEFBS_None, // MOV16rn = 484
5211
0
    CEFBS_None, // MOV16rp = 485
5212
0
    CEFBS_None, // MOV16rr = 486
5213
0
    CEFBS_None, // MOV8mc = 487
5214
0
    CEFBS_None, // MOV8mi = 488
5215
0
    CEFBS_None, // MOV8mm = 489
5216
0
    CEFBS_None, // MOV8mn = 490
5217
0
    CEFBS_None, // MOV8mr = 491
5218
0
    CEFBS_None, // MOV8rc = 492
5219
0
    CEFBS_None, // MOV8ri = 493
5220
0
    CEFBS_None, // MOV8rm = 494
5221
0
    CEFBS_None, // MOV8rn = 495
5222
0
    CEFBS_None, // MOV8rp = 496
5223
0
    CEFBS_None, // MOV8rr = 497
5224
0
    CEFBS_None, // MOVZX16rm8 = 498
5225
0
    CEFBS_None, // MOVZX16rr8 = 499
5226
0
    CEFBS_None, // POP16r = 500
5227
0
    CEFBS_None, // PUSH16c = 501
5228
0
    CEFBS_None, // PUSH16i = 502
5229
0
    CEFBS_None, // PUSH16r = 503
5230
0
    CEFBS_None, // PUSH8r = 504
5231
0
    CEFBS_None, // RET = 505
5232
0
    CEFBS_None, // RETI = 506
5233
0
    CEFBS_None, // RRA16m = 507
5234
0
    CEFBS_None, // RRA16n = 508
5235
0
    CEFBS_None, // RRA16p = 509
5236
0
    CEFBS_None, // RRA16r = 510
5237
0
    CEFBS_None, // RRA8m = 511
5238
0
    CEFBS_None, // RRA8n = 512
5239
0
    CEFBS_None, // RRA8p = 513
5240
0
    CEFBS_None, // RRA8r = 514
5241
0
    CEFBS_None, // RRC16m = 515
5242
0
    CEFBS_None, // RRC16n = 516
5243
0
    CEFBS_None, // RRC16p = 517
5244
0
    CEFBS_None, // RRC16r = 518
5245
0
    CEFBS_None, // RRC8m = 519
5246
0
    CEFBS_None, // RRC8n = 520
5247
0
    CEFBS_None, // RRC8p = 521
5248
0
    CEFBS_None, // RRC8r = 522
5249
0
    CEFBS_None, // Rrcl16 = 523
5250
0
    CEFBS_None, // Rrcl8 = 524
5251
0
    CEFBS_None, // SEXT16m = 525
5252
0
    CEFBS_None, // SEXT16n = 526
5253
0
    CEFBS_None, // SEXT16p = 527
5254
0
    CEFBS_None, // SEXT16r = 528
5255
0
    CEFBS_None, // SUB16mc = 529
5256
0
    CEFBS_None, // SUB16mi = 530
5257
0
    CEFBS_None, // SUB16mm = 531
5258
0
    CEFBS_None, // SUB16mn = 532
5259
0
    CEFBS_None, // SUB16mp = 533
5260
0
    CEFBS_None, // SUB16mr = 534
5261
0
    CEFBS_None, // SUB16rc = 535
5262
0
    CEFBS_None, // SUB16ri = 536
5263
0
    CEFBS_None, // SUB16rm = 537
5264
0
    CEFBS_None, // SUB16rn = 538
5265
0
    CEFBS_None, // SUB16rp = 539
5266
0
    CEFBS_None, // SUB16rr = 540
5267
0
    CEFBS_None, // SUB8mc = 541
5268
0
    CEFBS_None, // SUB8mi = 542
5269
0
    CEFBS_None, // SUB8mm = 543
5270
0
    CEFBS_None, // SUB8mn = 544
5271
0
    CEFBS_None, // SUB8mp = 545
5272
0
    CEFBS_None, // SUB8mr = 546
5273
0
    CEFBS_None, // SUB8rc = 547
5274
0
    CEFBS_None, // SUB8ri = 548
5275
0
    CEFBS_None, // SUB8rm = 549
5276
0
    CEFBS_None, // SUB8rn = 550
5277
0
    CEFBS_None, // SUB8rp = 551
5278
0
    CEFBS_None, // SUB8rr = 552
5279
0
    CEFBS_None, // SUBC16mc = 553
5280
0
    CEFBS_None, // SUBC16mi = 554
5281
0
    CEFBS_None, // SUBC16mm = 555
5282
0
    CEFBS_None, // SUBC16mn = 556
5283
0
    CEFBS_None, // SUBC16mp = 557
5284
0
    CEFBS_None, // SUBC16mr = 558
5285
0
    CEFBS_None, // SUBC16rc = 559
5286
0
    CEFBS_None, // SUBC16ri = 560
5287
0
    CEFBS_None, // SUBC16rm = 561
5288
0
    CEFBS_None, // SUBC16rn = 562
5289
0
    CEFBS_None, // SUBC16rp = 563
5290
0
    CEFBS_None, // SUBC16rr = 564
5291
0
    CEFBS_None, // SUBC8mc = 565
5292
0
    CEFBS_None, // SUBC8mi = 566
5293
0
    CEFBS_None, // SUBC8mm = 567
5294
0
    CEFBS_None, // SUBC8mn = 568
5295
0
    CEFBS_None, // SUBC8mp = 569
5296
0
    CEFBS_None, // SUBC8mr = 570
5297
0
    CEFBS_None, // SUBC8rc = 571
5298
0
    CEFBS_None, // SUBC8ri = 572
5299
0
    CEFBS_None, // SUBC8rm = 573
5300
0
    CEFBS_None, // SUBC8rn = 574
5301
0
    CEFBS_None, // SUBC8rp = 575
5302
0
    CEFBS_None, // SUBC8rr = 576
5303
0
    CEFBS_None, // SWPB16m = 577
5304
0
    CEFBS_None, // SWPB16n = 578
5305
0
    CEFBS_None, // SWPB16p = 579
5306
0
    CEFBS_None, // SWPB16r = 580
5307
0
    CEFBS_None, // Select16 = 581
5308
0
    CEFBS_None, // Select8 = 582
5309
0
    CEFBS_None, // Shl16 = 583
5310
0
    CEFBS_None, // Shl8 = 584
5311
0
    CEFBS_None, // Sra16 = 585
5312
0
    CEFBS_None, // Sra8 = 586
5313
0
    CEFBS_None, // Srl16 = 587
5314
0
    CEFBS_None, // Srl8 = 588
5315
0
    CEFBS_None, // XOR16mc = 589
5316
0
    CEFBS_None, // XOR16mi = 590
5317
0
    CEFBS_None, // XOR16mm = 591
5318
0
    CEFBS_None, // XOR16mn = 592
5319
0
    CEFBS_None, // XOR16mp = 593
5320
0
    CEFBS_None, // XOR16mr = 594
5321
0
    CEFBS_None, // XOR16rc = 595
5322
0
    CEFBS_None, // XOR16ri = 596
5323
0
    CEFBS_None, // XOR16rm = 597
5324
0
    CEFBS_None, // XOR16rn = 598
5325
0
    CEFBS_None, // XOR16rp = 599
5326
0
    CEFBS_None, // XOR16rr = 600
5327
0
    CEFBS_None, // XOR8mc = 601
5328
0
    CEFBS_None, // XOR8mi = 602
5329
0
    CEFBS_None, // XOR8mm = 603
5330
0
    CEFBS_None, // XOR8mn = 604
5331
0
    CEFBS_None, // XOR8mp = 605
5332
0
    CEFBS_None, // XOR8mr = 606
5333
0
    CEFBS_None, // XOR8rc = 607
5334
0
    CEFBS_None, // XOR8ri = 608
5335
0
    CEFBS_None, // XOR8rm = 609
5336
0
    CEFBS_None, // XOR8rn = 610
5337
0
    CEFBS_None, // XOR8rp = 611
5338
0
    CEFBS_None, // XOR8rr = 612
5339
0
    CEFBS_None, // ZEXT16r = 613
5340
0
  };
5341
5342
0
  assert(Opcode < 614);
5343
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
5344
0
}
5345
5346
} // end namespace MSP430_MC
5347
} // end namespace llvm
5348
#endif // GET_COMPUTE_FEATURES
5349
5350
#ifdef GET_AVAILABLE_OPCODE_CHECKER
5351
#undef GET_AVAILABLE_OPCODE_CHECKER
5352
namespace llvm {
5353
namespace MSP430_MC {
5354
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
5355
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
5356
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
5357
  FeatureBitset MissingFeatures =
5358
      (AvailableFeatures & RequiredFeatures) ^
5359
      RequiredFeatures;
5360
  return !MissingFeatures.any();
5361
}
5362
} // end namespace MSP430_MC
5363
} // end namespace llvm
5364
#endif // GET_AVAILABLE_OPCODE_CHECKER
5365
5366
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
5367
#undef ENABLE_INSTR_PREDICATE_VERIFIER
5368
#include <sstream>
5369
5370
namespace llvm {
5371
namespace MSP430_MC {
5372
5373
#ifndef NDEBUG
5374
static const char *SubtargetFeatureNames[] = {
5375
  nullptr
5376
};
5377
5378
#endif // NDEBUG
5379
5380
void verifyInstructionPredicates(
5381
0
    unsigned Opcode, const FeatureBitset &Features) {
5382
0
#ifndef NDEBUG
5383
0
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
5384
0
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
5385
0
  FeatureBitset MissingFeatures =
5386
0
      (AvailableFeatures & RequiredFeatures) ^
5387
0
      RequiredFeatures;
5388
0
  if (MissingFeatures.any()) {
5389
0
    std::ostringstream Msg;
5390
0
    Msg << "Attempting to emit " << &MSP430InstrNameData[MSP430InstrNameIndices[Opcode]]
5391
0
        << " instruction but the ";
5392
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
5393
0
      if (MissingFeatures.test(i))
5394
0
        Msg << SubtargetFeatureNames[i] << " ";
5395
0
    Msg << "predicate(s) are not met";
5396
0
    report_fatal_error(Msg.str().c_str());
5397
0
  }
5398
0
#endif // NDEBUG
5399
0
}
5400
} // end namespace MSP430_MC
5401
} // end namespace llvm
5402
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
5403