/src/build/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t MSP430MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(20608), // ADD16mc |
285 | 0 | UINT64_C(20656), // ADD16mi |
286 | 0 | UINT64_C(20624), // ADD16mm |
287 | 0 | UINT64_C(20640), // ADD16mn |
288 | 0 | UINT64_C(20656), // ADD16mp |
289 | 0 | UINT64_C(20608), // ADD16mr |
290 | 0 | UINT64_C(20480), // ADD16rc |
291 | 0 | UINT64_C(20528), // ADD16ri |
292 | 0 | UINT64_C(20496), // ADD16rm |
293 | 0 | UINT64_C(20512), // ADD16rn |
294 | 0 | UINT64_C(20528), // ADD16rp |
295 | 0 | UINT64_C(20480), // ADD16rr |
296 | 0 | UINT64_C(20672), // ADD8mc |
297 | 0 | UINT64_C(20720), // ADD8mi |
298 | 0 | UINT64_C(20688), // ADD8mm |
299 | 0 | UINT64_C(20704), // ADD8mn |
300 | 0 | UINT64_C(20720), // ADD8mp |
301 | 0 | UINT64_C(20672), // ADD8mr |
302 | 0 | UINT64_C(20544), // ADD8rc |
303 | 0 | UINT64_C(20592), // ADD8ri |
304 | 0 | UINT64_C(20560), // ADD8rm |
305 | 0 | UINT64_C(20576), // ADD8rn |
306 | 0 | UINT64_C(20592), // ADD8rp |
307 | 0 | UINT64_C(20544), // ADD8rr |
308 | 0 | UINT64_C(24704), // ADDC16mc |
309 | 0 | UINT64_C(24752), // ADDC16mi |
310 | 0 | UINT64_C(24720), // ADDC16mm |
311 | 0 | UINT64_C(24736), // ADDC16mn |
312 | 0 | UINT64_C(24752), // ADDC16mp |
313 | 0 | UINT64_C(24704), // ADDC16mr |
314 | 0 | UINT64_C(24576), // ADDC16rc |
315 | 0 | UINT64_C(24624), // ADDC16ri |
316 | 0 | UINT64_C(24592), // ADDC16rm |
317 | 0 | UINT64_C(24608), // ADDC16rn |
318 | 0 | UINT64_C(24624), // ADDC16rp |
319 | 0 | UINT64_C(24576), // ADDC16rr |
320 | 0 | UINT64_C(24768), // ADDC8mc |
321 | 0 | UINT64_C(24816), // ADDC8mi |
322 | 0 | UINT64_C(24784), // ADDC8mm |
323 | 0 | UINT64_C(24800), // ADDC8mn |
324 | 0 | UINT64_C(24816), // ADDC8mp |
325 | 0 | UINT64_C(24768), // ADDC8mr |
326 | 0 | UINT64_C(24640), // ADDC8rc |
327 | 0 | UINT64_C(24688), // ADDC8ri |
328 | 0 | UINT64_C(24656), // ADDC8rm |
329 | 0 | UINT64_C(24672), // ADDC8rn |
330 | 0 | UINT64_C(24688), // ADDC8rp |
331 | 0 | UINT64_C(24640), // ADDC8rr |
332 | 0 | UINT64_C(0), // ADDframe |
333 | 0 | UINT64_C(0), // ADJCALLSTACKDOWN |
334 | 0 | UINT64_C(0), // ADJCALLSTACKUP |
335 | 0 | UINT64_C(61568), // AND16mc |
336 | 0 | UINT64_C(61616), // AND16mi |
337 | 0 | UINT64_C(61584), // AND16mm |
338 | 0 | UINT64_C(61600), // AND16mn |
339 | 0 | UINT64_C(61616), // AND16mp |
340 | 0 | UINT64_C(61568), // AND16mr |
341 | 0 | UINT64_C(61440), // AND16rc |
342 | 0 | UINT64_C(61488), // AND16ri |
343 | 0 | UINT64_C(61456), // AND16rm |
344 | 0 | UINT64_C(61472), // AND16rn |
345 | 0 | UINT64_C(61488), // AND16rp |
346 | 0 | UINT64_C(61440), // AND16rr |
347 | 0 | UINT64_C(61632), // AND8mc |
348 | 0 | UINT64_C(61680), // AND8mi |
349 | 0 | UINT64_C(61648), // AND8mm |
350 | 0 | UINT64_C(61664), // AND8mn |
351 | 0 | UINT64_C(61680), // AND8mp |
352 | 0 | UINT64_C(61632), // AND8mr |
353 | 0 | UINT64_C(61504), // AND8rc |
354 | 0 | UINT64_C(61552), // AND8ri |
355 | 0 | UINT64_C(61520), // AND8rm |
356 | 0 | UINT64_C(61536), // AND8rn |
357 | 0 | UINT64_C(61552), // AND8rp |
358 | 0 | UINT64_C(61504), // AND8rr |
359 | 0 | UINT64_C(49280), // BIC16mc |
360 | 0 | UINT64_C(49328), // BIC16mi |
361 | 0 | UINT64_C(49296), // BIC16mm |
362 | 0 | UINT64_C(49312), // BIC16mn |
363 | 0 | UINT64_C(49328), // BIC16mp |
364 | 0 | UINT64_C(49280), // BIC16mr |
365 | 0 | UINT64_C(49152), // BIC16rc |
366 | 0 | UINT64_C(49200), // BIC16ri |
367 | 0 | UINT64_C(49168), // BIC16rm |
368 | 0 | UINT64_C(49184), // BIC16rn |
369 | 0 | UINT64_C(49200), // BIC16rp |
370 | 0 | UINT64_C(49152), // BIC16rr |
371 | 0 | UINT64_C(49344), // BIC8mc |
372 | 0 | UINT64_C(49392), // BIC8mi |
373 | 0 | UINT64_C(49360), // BIC8mm |
374 | 0 | UINT64_C(49376), // BIC8mn |
375 | 0 | UINT64_C(49392), // BIC8mp |
376 | 0 | UINT64_C(49344), // BIC8mr |
377 | 0 | UINT64_C(49216), // BIC8rc |
378 | 0 | UINT64_C(49264), // BIC8ri |
379 | 0 | UINT64_C(49232), // BIC8rm |
380 | 0 | UINT64_C(49248), // BIC8rn |
381 | 0 | UINT64_C(49264), // BIC8rp |
382 | 0 | UINT64_C(49216), // BIC8rr |
383 | 0 | UINT64_C(53376), // BIS16mc |
384 | 0 | UINT64_C(53424), // BIS16mi |
385 | 0 | UINT64_C(53392), // BIS16mm |
386 | 0 | UINT64_C(53408), // BIS16mn |
387 | 0 | UINT64_C(53424), // BIS16mp |
388 | 0 | UINT64_C(53376), // BIS16mr |
389 | 0 | UINT64_C(53248), // BIS16rc |
390 | 0 | UINT64_C(53296), // BIS16ri |
391 | 0 | UINT64_C(53264), // BIS16rm |
392 | 0 | UINT64_C(53280), // BIS16rn |
393 | 0 | UINT64_C(53296), // BIS16rp |
394 | 0 | UINT64_C(53248), // BIS16rr |
395 | 0 | UINT64_C(53440), // BIS8mc |
396 | 0 | UINT64_C(53488), // BIS8mi |
397 | 0 | UINT64_C(53456), // BIS8mm |
398 | 0 | UINT64_C(53472), // BIS8mn |
399 | 0 | UINT64_C(53488), // BIS8mp |
400 | 0 | UINT64_C(53440), // BIS8mr |
401 | 0 | UINT64_C(53312), // BIS8rc |
402 | 0 | UINT64_C(53360), // BIS8ri |
403 | 0 | UINT64_C(53328), // BIS8rm |
404 | 0 | UINT64_C(53344), // BIS8rn |
405 | 0 | UINT64_C(53360), // BIS8rp |
406 | 0 | UINT64_C(53312), // BIS8rr |
407 | 0 | UINT64_C(45184), // BIT16mc |
408 | 0 | UINT64_C(45232), // BIT16mi |
409 | 0 | UINT64_C(45200), // BIT16mm |
410 | 0 | UINT64_C(45216), // BIT16mn |
411 | 0 | UINT64_C(45232), // BIT16mp |
412 | 0 | UINT64_C(45184), // BIT16mr |
413 | 0 | UINT64_C(45056), // BIT16rc |
414 | 0 | UINT64_C(45104), // BIT16ri |
415 | 0 | UINT64_C(45072), // BIT16rm |
416 | 0 | UINT64_C(45088), // BIT16rn |
417 | 0 | UINT64_C(45104), // BIT16rp |
418 | 0 | UINT64_C(45056), // BIT16rr |
419 | 0 | UINT64_C(45248), // BIT8mc |
420 | 0 | UINT64_C(45296), // BIT8mi |
421 | 0 | UINT64_C(45264), // BIT8mm |
422 | 0 | UINT64_C(45280), // BIT8mn |
423 | 0 | UINT64_C(45296), // BIT8mp |
424 | 0 | UINT64_C(45248), // BIT8mr |
425 | 0 | UINT64_C(45120), // BIT8rc |
426 | 0 | UINT64_C(45168), // BIT8ri |
427 | 0 | UINT64_C(45136), // BIT8rm |
428 | 0 | UINT64_C(45152), // BIT8rn |
429 | 0 | UINT64_C(45168), // BIT8rp |
430 | 0 | UINT64_C(45120), // BIT8rr |
431 | 0 | UINT64_C(16432), // Bi |
432 | 0 | UINT64_C(16400), // Bm |
433 | 0 | UINT64_C(16384), // Br |
434 | 0 | UINT64_C(4784), // CALLi |
435 | 0 | UINT64_C(4752), // CALLm |
436 | 0 | UINT64_C(4768), // CALLn |
437 | 0 | UINT64_C(4784), // CALLp |
438 | 0 | UINT64_C(4736), // CALLr |
439 | 0 | UINT64_C(36992), // CMP16mc |
440 | 0 | UINT64_C(37040), // CMP16mi |
441 | 0 | UINT64_C(37008), // CMP16mm |
442 | 0 | UINT64_C(37024), // CMP16mn |
443 | 0 | UINT64_C(37040), // CMP16mp |
444 | 0 | UINT64_C(36992), // CMP16mr |
445 | 0 | UINT64_C(36864), // CMP16rc |
446 | 0 | UINT64_C(36912), // CMP16ri |
447 | 0 | UINT64_C(36880), // CMP16rm |
448 | 0 | UINT64_C(36896), // CMP16rn |
449 | 0 | UINT64_C(36912), // CMP16rp |
450 | 0 | UINT64_C(36864), // CMP16rr |
451 | 0 | UINT64_C(37056), // CMP8mc |
452 | 0 | UINT64_C(37104), // CMP8mi |
453 | 0 | UINT64_C(37072), // CMP8mm |
454 | 0 | UINT64_C(37088), // CMP8mn |
455 | 0 | UINT64_C(37104), // CMP8mp |
456 | 0 | UINT64_C(37056), // CMP8mr |
457 | 0 | UINT64_C(36928), // CMP8rc |
458 | 0 | UINT64_C(36976), // CMP8ri |
459 | 0 | UINT64_C(36944), // CMP8rm |
460 | 0 | UINT64_C(36960), // CMP8rn |
461 | 0 | UINT64_C(36976), // CMP8rp |
462 | 0 | UINT64_C(36928), // CMP8rr |
463 | 0 | UINT64_C(41088), // DADD16mc |
464 | 0 | UINT64_C(41136), // DADD16mi |
465 | 0 | UINT64_C(41104), // DADD16mm |
466 | 0 | UINT64_C(41120), // DADD16mn |
467 | 0 | UINT64_C(41136), // DADD16mp |
468 | 0 | UINT64_C(41088), // DADD16mr |
469 | 0 | UINT64_C(40960), // DADD16rc |
470 | 0 | UINT64_C(41008), // DADD16ri |
471 | 0 | UINT64_C(40976), // DADD16rm |
472 | 0 | UINT64_C(40992), // DADD16rn |
473 | 0 | UINT64_C(41008), // DADD16rp |
474 | 0 | UINT64_C(40960), // DADD16rr |
475 | 0 | UINT64_C(41152), // DADD8mc |
476 | 0 | UINT64_C(41200), // DADD8mi |
477 | 0 | UINT64_C(41168), // DADD8mm |
478 | 0 | UINT64_C(41184), // DADD8mn |
479 | 0 | UINT64_C(41200), // DADD8mp |
480 | 0 | UINT64_C(41152), // DADD8mr |
481 | 0 | UINT64_C(41024), // DADD8rc |
482 | 0 | UINT64_C(41072), // DADD8ri |
483 | 0 | UINT64_C(41040), // DADD8rm |
484 | 0 | UINT64_C(41056), // DADD8rn |
485 | 0 | UINT64_C(41072), // DADD8rp |
486 | 0 | UINT64_C(41024), // DADD8rr |
487 | 0 | UINT64_C(8192), // JCC |
488 | 0 | UINT64_C(15360), // JMP |
489 | 0 | UINT64_C(16512), // MOV16mc |
490 | 0 | UINT64_C(16560), // MOV16mi |
491 | 0 | UINT64_C(16528), // MOV16mm |
492 | 0 | UINT64_C(16544), // MOV16mn |
493 | 0 | UINT64_C(16512), // MOV16mr |
494 | 0 | UINT64_C(16384), // MOV16rc |
495 | 0 | UINT64_C(16432), // MOV16ri |
496 | 0 | UINT64_C(16400), // MOV16rm |
497 | 0 | UINT64_C(16416), // MOV16rn |
498 | 0 | UINT64_C(16432), // MOV16rp |
499 | 0 | UINT64_C(16384), // MOV16rr |
500 | 0 | UINT64_C(16576), // MOV8mc |
501 | 0 | UINT64_C(16624), // MOV8mi |
502 | 0 | UINT64_C(16592), // MOV8mm |
503 | 0 | UINT64_C(16608), // MOV8mn |
504 | 0 | UINT64_C(16576), // MOV8mr |
505 | 0 | UINT64_C(16448), // MOV8rc |
506 | 0 | UINT64_C(16496), // MOV8ri |
507 | 0 | UINT64_C(16464), // MOV8rm |
508 | 0 | UINT64_C(16480), // MOV8rn |
509 | 0 | UINT64_C(16496), // MOV8rp |
510 | 0 | UINT64_C(16448), // MOV8rr |
511 | 0 | UINT64_C(16464), // MOVZX16rm8 |
512 | 0 | UINT64_C(16448), // MOVZX16rr8 |
513 | 0 | UINT64_C(16688), // POP16r |
514 | 0 | UINT64_C(4608), // PUSH16c |
515 | 0 | UINT64_C(4656), // PUSH16i |
516 | 0 | UINT64_C(4608), // PUSH16r |
517 | 0 | UINT64_C(4672), // PUSH8r |
518 | 0 | UINT64_C(16688), // RET |
519 | 0 | UINT64_C(4864), // RETI |
520 | 0 | UINT64_C(4368), // RRA16m |
521 | 0 | UINT64_C(4384), // RRA16n |
522 | 0 | UINT64_C(4400), // RRA16p |
523 | 0 | UINT64_C(4352), // RRA16r |
524 | 0 | UINT64_C(4432), // RRA8m |
525 | 0 | UINT64_C(4448), // RRA8n |
526 | 0 | UINT64_C(4464), // RRA8p |
527 | 0 | UINT64_C(4416), // RRA8r |
528 | 0 | UINT64_C(4112), // RRC16m |
529 | 0 | UINT64_C(4128), // RRC16n |
530 | 0 | UINT64_C(4144), // RRC16p |
531 | 0 | UINT64_C(4096), // RRC16r |
532 | 0 | UINT64_C(4176), // RRC8m |
533 | 0 | UINT64_C(4192), // RRC8n |
534 | 0 | UINT64_C(4208), // RRC8p |
535 | 0 | UINT64_C(4160), // RRC8r |
536 | 0 | UINT64_C(0), // Rrcl16 |
537 | 0 | UINT64_C(0), // Rrcl8 |
538 | 0 | UINT64_C(4496), // SEXT16m |
539 | 0 | UINT64_C(4512), // SEXT16n |
540 | 0 | UINT64_C(4528), // SEXT16p |
541 | 0 | UINT64_C(4480), // SEXT16r |
542 | 0 | UINT64_C(32896), // SUB16mc |
543 | 0 | UINT64_C(32944), // SUB16mi |
544 | 0 | UINT64_C(32912), // SUB16mm |
545 | 0 | UINT64_C(32928), // SUB16mn |
546 | 0 | UINT64_C(32944), // SUB16mp |
547 | 0 | UINT64_C(32896), // SUB16mr |
548 | 0 | UINT64_C(32768), // SUB16rc |
549 | 0 | UINT64_C(32816), // SUB16ri |
550 | 0 | UINT64_C(32784), // SUB16rm |
551 | 0 | UINT64_C(32800), // SUB16rn |
552 | 0 | UINT64_C(32816), // SUB16rp |
553 | 0 | UINT64_C(32768), // SUB16rr |
554 | 0 | UINT64_C(32960), // SUB8mc |
555 | 0 | UINT64_C(33008), // SUB8mi |
556 | 0 | UINT64_C(32976), // SUB8mm |
557 | 0 | UINT64_C(32992), // SUB8mn |
558 | 0 | UINT64_C(33008), // SUB8mp |
559 | 0 | UINT64_C(32960), // SUB8mr |
560 | 0 | UINT64_C(32832), // SUB8rc |
561 | 0 | UINT64_C(32880), // SUB8ri |
562 | 0 | UINT64_C(32848), // SUB8rm |
563 | 0 | UINT64_C(32864), // SUB8rn |
564 | 0 | UINT64_C(32880), // SUB8rp |
565 | 0 | UINT64_C(32832), // SUB8rr |
566 | 0 | UINT64_C(28800), // SUBC16mc |
567 | 0 | UINT64_C(28848), // SUBC16mi |
568 | 0 | UINT64_C(28816), // SUBC16mm |
569 | 0 | UINT64_C(28832), // SUBC16mn |
570 | 0 | UINT64_C(28848), // SUBC16mp |
571 | 0 | UINT64_C(28800), // SUBC16mr |
572 | 0 | UINT64_C(28672), // SUBC16rc |
573 | 0 | UINT64_C(28720), // SUBC16ri |
574 | 0 | UINT64_C(28688), // SUBC16rm |
575 | 0 | UINT64_C(28704), // SUBC16rn |
576 | 0 | UINT64_C(28720), // SUBC16rp |
577 | 0 | UINT64_C(28672), // SUBC16rr |
578 | 0 | UINT64_C(28864), // SUBC8mc |
579 | 0 | UINT64_C(28912), // SUBC8mi |
580 | 0 | UINT64_C(28880), // SUBC8mm |
581 | 0 | UINT64_C(28896), // SUBC8mn |
582 | 0 | UINT64_C(28912), // SUBC8mp |
583 | 0 | UINT64_C(28864), // SUBC8mr |
584 | 0 | UINT64_C(28736), // SUBC8rc |
585 | 0 | UINT64_C(28784), // SUBC8ri |
586 | 0 | UINT64_C(28752), // SUBC8rm |
587 | 0 | UINT64_C(28768), // SUBC8rn |
588 | 0 | UINT64_C(28784), // SUBC8rp |
589 | 0 | UINT64_C(28736), // SUBC8rr |
590 | 0 | UINT64_C(4240), // SWPB16m |
591 | 0 | UINT64_C(4256), // SWPB16n |
592 | 0 | UINT64_C(4272), // SWPB16p |
593 | 0 | UINT64_C(4224), // SWPB16r |
594 | 0 | UINT64_C(0), // Select16 |
595 | 0 | UINT64_C(0), // Select8 |
596 | 0 | UINT64_C(0), // Shl16 |
597 | 0 | UINT64_C(0), // Shl8 |
598 | 0 | UINT64_C(0), // Sra16 |
599 | 0 | UINT64_C(0), // Sra8 |
600 | 0 | UINT64_C(0), // Srl16 |
601 | 0 | UINT64_C(0), // Srl8 |
602 | 0 | UINT64_C(57472), // XOR16mc |
603 | 0 | UINT64_C(57520), // XOR16mi |
604 | 0 | UINT64_C(57488), // XOR16mm |
605 | 0 | UINT64_C(57504), // XOR16mn |
606 | 0 | UINT64_C(57520), // XOR16mp |
607 | 0 | UINT64_C(57472), // XOR16mr |
608 | 0 | UINT64_C(57344), // XOR16rc |
609 | 0 | UINT64_C(57392), // XOR16ri |
610 | 0 | UINT64_C(57360), // XOR16rm |
611 | 0 | UINT64_C(57376), // XOR16rn |
612 | 0 | UINT64_C(57392), // XOR16rp |
613 | 0 | UINT64_C(57344), // XOR16rr |
614 | 0 | UINT64_C(57536), // XOR8mc |
615 | 0 | UINT64_C(57584), // XOR8mi |
616 | 0 | UINT64_C(57552), // XOR8mm |
617 | 0 | UINT64_C(57568), // XOR8mn |
618 | 0 | UINT64_C(57584), // XOR8mp |
619 | 0 | UINT64_C(57536), // XOR8mr |
620 | 0 | UINT64_C(57408), // XOR8rc |
621 | 0 | UINT64_C(57456), // XOR8ri |
622 | 0 | UINT64_C(57424), // XOR8rm |
623 | 0 | UINT64_C(57440), // XOR8rn |
624 | 0 | UINT64_C(57456), // XOR8rp |
625 | 0 | UINT64_C(57408), // XOR8rr |
626 | 0 | UINT64_C(16448), // ZEXT16r |
627 | 0 | UINT64_C(0) |
628 | 0 | }; |
629 | 0 | const unsigned opcode = MI.getOpcode(); |
630 | 0 | uint64_t Value = InstBits[opcode]; |
631 | 0 | uint64_t op = 0; |
632 | 0 | (void)op; // suppress warning |
633 | 0 | switch (opcode) { |
634 | 0 | case MSP430::ADDframe: |
635 | 0 | case MSP430::ADJCALLSTACKDOWN: |
636 | 0 | case MSP430::ADJCALLSTACKUP: |
637 | 0 | case MSP430::RET: |
638 | 0 | case MSP430::RETI: |
639 | 0 | case MSP430::Rrcl8: |
640 | 0 | case MSP430::Rrcl16: |
641 | 0 | case MSP430::Select8: |
642 | 0 | case MSP430::Select16: |
643 | 0 | case MSP430::Shl8: |
644 | 0 | case MSP430::Shl16: |
645 | 0 | case MSP430::Sra8: |
646 | 0 | case MSP430::Sra16: |
647 | 0 | case MSP430::Srl8: |
648 | 0 | case MSP430::Srl16: { |
649 | 0 | break; |
650 | 0 | } |
651 | 0 | case MSP430::JCC: { |
652 | | // op: cond |
653 | 0 | op = getCCOpValue(MI, 1, Fixups, STI); |
654 | 0 | op &= UINT64_C(7); |
655 | 0 | op <<= 10; |
656 | 0 | Value |= op; |
657 | | // op: dst |
658 | 0 | op = getPCRelImmOpValue(MI, 0, Fixups, STI); |
659 | 0 | op &= UINT64_C(1023); |
660 | 0 | Value |= op; |
661 | 0 | break; |
662 | 0 | } |
663 | 0 | case MSP430::JMP: { |
664 | | // op: dst |
665 | 0 | op = getPCRelImmOpValue(MI, 0, Fixups, STI); |
666 | 0 | op &= UINT64_C(1023); |
667 | 0 | Value |= op; |
668 | 0 | break; |
669 | 0 | } |
670 | 0 | case MSP430::PUSH16c: { |
671 | | // op: imm |
672 | 0 | op = getCGImmOpValue(MI, 0, Fixups, STI); |
673 | 0 | op &= UINT64_C(63); |
674 | 0 | Value |= op; |
675 | 0 | break; |
676 | 0 | } |
677 | 0 | case MSP430::BIT8rc: |
678 | 0 | case MSP430::BIT16rc: |
679 | 0 | case MSP430::CMP8rc: |
680 | 0 | case MSP430::CMP16rc: |
681 | 0 | case MSP430::MOV8rc: |
682 | 0 | case MSP430::MOV16rc: { |
683 | | // op: imm |
684 | 0 | op = getCGImmOpValue(MI, 1, Fixups, STI); |
685 | 0 | Value |= (op & UINT64_C(15)) << 8; |
686 | 0 | Value |= (op & UINT64_C(48)); |
687 | | // op: rd |
688 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
689 | 0 | op &= UINT64_C(15); |
690 | 0 | Value |= op; |
691 | 0 | break; |
692 | 0 | } |
693 | 0 | case MSP430::ADD8mc: |
694 | 0 | case MSP430::ADD16mc: |
695 | 0 | case MSP430::ADDC8mc: |
696 | 0 | case MSP430::ADDC16mc: |
697 | 0 | case MSP430::AND8mc: |
698 | 0 | case MSP430::AND16mc: |
699 | 0 | case MSP430::BIC8mc: |
700 | 0 | case MSP430::BIC16mc: |
701 | 0 | case MSP430::BIS8mc: |
702 | 0 | case MSP430::BIS16mc: |
703 | 0 | case MSP430::BIT8mc: |
704 | 0 | case MSP430::BIT16mc: |
705 | 0 | case MSP430::CMP8mc: |
706 | 0 | case MSP430::CMP16mc: |
707 | 0 | case MSP430::DADD8mc: |
708 | 0 | case MSP430::DADD16mc: |
709 | 0 | case MSP430::MOV8mc: |
710 | 0 | case MSP430::MOV16mc: |
711 | 0 | case MSP430::SUB8mc: |
712 | 0 | case MSP430::SUB16mc: |
713 | 0 | case MSP430::SUBC8mc: |
714 | 0 | case MSP430::SUBC16mc: |
715 | 0 | case MSP430::XOR8mc: |
716 | 0 | case MSP430::XOR16mc: { |
717 | | // op: imm |
718 | 0 | op = getCGImmOpValue(MI, 2, Fixups, STI); |
719 | 0 | Value |= (op & UINT64_C(15)) << 8; |
720 | 0 | Value |= (op & UINT64_C(48)); |
721 | | // op: dst |
722 | 0 | op = getMemOpValue(MI, 0, Fixups, STI); |
723 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
724 | 0 | Value |= (op & UINT64_C(15)); |
725 | 0 | break; |
726 | 0 | } |
727 | 0 | case MSP430::ADD8rc: |
728 | 0 | case MSP430::ADD16rc: |
729 | 0 | case MSP430::ADDC8rc: |
730 | 0 | case MSP430::ADDC16rc: |
731 | 0 | case MSP430::AND8rc: |
732 | 0 | case MSP430::AND16rc: |
733 | 0 | case MSP430::BIC8rc: |
734 | 0 | case MSP430::BIC16rc: |
735 | 0 | case MSP430::BIS8rc: |
736 | 0 | case MSP430::BIS16rc: |
737 | 0 | case MSP430::DADD8rc: |
738 | 0 | case MSP430::DADD16rc: |
739 | 0 | case MSP430::SUB8rc: |
740 | 0 | case MSP430::SUB16rc: |
741 | 0 | case MSP430::SUBC8rc: |
742 | 0 | case MSP430::SUBC16rc: |
743 | 0 | case MSP430::XOR8rc: |
744 | 0 | case MSP430::XOR16rc: { |
745 | | // op: imm |
746 | 0 | op = getCGImmOpValue(MI, 2, Fixups, STI); |
747 | 0 | Value |= (op & UINT64_C(15)) << 8; |
748 | 0 | Value |= (op & UINT64_C(48)); |
749 | | // op: rd |
750 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
751 | 0 | op &= UINT64_C(15); |
752 | 0 | Value |= op; |
753 | 0 | break; |
754 | 0 | } |
755 | 0 | case MSP430::Bi: |
756 | 0 | case MSP430::CALLi: |
757 | 0 | case MSP430::PUSH16i: { |
758 | | // op: imm |
759 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
760 | 0 | op &= UINT64_C(65535); |
761 | 0 | op <<= 16; |
762 | 0 | Value |= op; |
763 | 0 | break; |
764 | 0 | } |
765 | 0 | case MSP430::ADD8mi: |
766 | 0 | case MSP430::ADD16mi: |
767 | 0 | case MSP430::ADDC8mi: |
768 | 0 | case MSP430::ADDC16mi: |
769 | 0 | case MSP430::AND8mi: |
770 | 0 | case MSP430::AND16mi: |
771 | 0 | case MSP430::BIC8mi: |
772 | 0 | case MSP430::BIC16mi: |
773 | 0 | case MSP430::BIS8mi: |
774 | 0 | case MSP430::BIS16mi: |
775 | 0 | case MSP430::BIT8mi: |
776 | 0 | case MSP430::BIT16mi: |
777 | 0 | case MSP430::CMP8mi: |
778 | 0 | case MSP430::CMP16mi: |
779 | 0 | case MSP430::DADD8mi: |
780 | 0 | case MSP430::DADD16mi: |
781 | 0 | case MSP430::MOV8mi: |
782 | 0 | case MSP430::MOV16mi: |
783 | 0 | case MSP430::SUB8mi: |
784 | 0 | case MSP430::SUB16mi: |
785 | 0 | case MSP430::SUBC8mi: |
786 | 0 | case MSP430::SUBC16mi: |
787 | 0 | case MSP430::XOR8mi: |
788 | 0 | case MSP430::XOR16mi: { |
789 | | // op: imm |
790 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
791 | 0 | op &= UINT64_C(65535); |
792 | 0 | op <<= 16; |
793 | 0 | Value |= op; |
794 | | // op: dst |
795 | 0 | op = getMemOpValue(MI, 0, Fixups, STI); |
796 | 0 | Value |= (op & UINT64_C(1048560)) << 28; |
797 | 0 | Value |= (op & UINT64_C(15)); |
798 | 0 | break; |
799 | 0 | } |
800 | 0 | case MSP430::POP16r: { |
801 | | // op: rd |
802 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
803 | 0 | op &= UINT64_C(15); |
804 | 0 | Value |= op; |
805 | 0 | break; |
806 | 0 | } |
807 | 0 | case MSP430::BIT8ri: |
808 | 0 | case MSP430::BIT16ri: |
809 | 0 | case MSP430::CMP8ri: |
810 | 0 | case MSP430::CMP16ri: |
811 | 0 | case MSP430::MOV8ri: |
812 | 0 | case MSP430::MOV16ri: { |
813 | | // op: rd |
814 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
815 | 0 | op &= UINT64_C(15); |
816 | 0 | Value |= op; |
817 | | // op: imm |
818 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
819 | 0 | op &= UINT64_C(65535); |
820 | 0 | op <<= 16; |
821 | 0 | Value |= op; |
822 | 0 | break; |
823 | 0 | } |
824 | 0 | case MSP430::ADD8ri: |
825 | 0 | case MSP430::ADD16ri: |
826 | 0 | case MSP430::ADDC8ri: |
827 | 0 | case MSP430::ADDC16ri: |
828 | 0 | case MSP430::AND8ri: |
829 | 0 | case MSP430::AND16ri: |
830 | 0 | case MSP430::BIC8ri: |
831 | 0 | case MSP430::BIC16ri: |
832 | 0 | case MSP430::BIS8ri: |
833 | 0 | case MSP430::BIS16ri: |
834 | 0 | case MSP430::DADD8ri: |
835 | 0 | case MSP430::DADD16ri: |
836 | 0 | case MSP430::SUB8ri: |
837 | 0 | case MSP430::SUB16ri: |
838 | 0 | case MSP430::SUBC8ri: |
839 | 0 | case MSP430::SUBC16ri: |
840 | 0 | case MSP430::XOR8ri: |
841 | 0 | case MSP430::XOR16ri: { |
842 | | // op: rd |
843 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
844 | 0 | op &= UINT64_C(15); |
845 | 0 | Value |= op; |
846 | | // op: imm |
847 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
848 | 0 | op &= UINT64_C(65535); |
849 | 0 | op <<= 16; |
850 | 0 | Value |= op; |
851 | 0 | break; |
852 | 0 | } |
853 | 0 | case MSP430::BIT8rm: |
854 | 0 | case MSP430::BIT16rm: |
855 | 0 | case MSP430::CMP8rm: |
856 | 0 | case MSP430::CMP16rm: |
857 | 0 | case MSP430::MOV8rm: |
858 | 0 | case MSP430::MOV16rm: |
859 | 0 | case MSP430::MOVZX16rm8: { |
860 | | // op: rd |
861 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
862 | 0 | op &= UINT64_C(15); |
863 | 0 | Value |= op; |
864 | | // op: src |
865 | 0 | op = getMemOpValue(MI, 1, Fixups, STI); |
866 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
867 | 0 | Value |= (op & UINT64_C(15)) << 8; |
868 | 0 | break; |
869 | 0 | } |
870 | 0 | case MSP430::ADD8rm: |
871 | 0 | case MSP430::ADD16rm: |
872 | 0 | case MSP430::ADDC8rm: |
873 | 0 | case MSP430::ADDC16rm: |
874 | 0 | case MSP430::AND8rm: |
875 | 0 | case MSP430::AND16rm: |
876 | 0 | case MSP430::BIC8rm: |
877 | 0 | case MSP430::BIC16rm: |
878 | 0 | case MSP430::BIS8rm: |
879 | 0 | case MSP430::BIS16rm: |
880 | 0 | case MSP430::DADD8rm: |
881 | 0 | case MSP430::DADD16rm: |
882 | 0 | case MSP430::SUB8rm: |
883 | 0 | case MSP430::SUB16rm: |
884 | 0 | case MSP430::SUBC8rm: |
885 | 0 | case MSP430::SUBC16rm: |
886 | 0 | case MSP430::XOR8rm: |
887 | 0 | case MSP430::XOR16rm: { |
888 | | // op: rd |
889 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
890 | 0 | op &= UINT64_C(15); |
891 | 0 | Value |= op; |
892 | | // op: src |
893 | 0 | op = getMemOpValue(MI, 2, Fixups, STI); |
894 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
895 | 0 | Value |= (op & UINT64_C(15)) << 8; |
896 | 0 | break; |
897 | 0 | } |
898 | 0 | case MSP430::CALLn: |
899 | 0 | case MSP430::CALLp: |
900 | 0 | case MSP430::CALLr: |
901 | 0 | case MSP430::PUSH8r: |
902 | 0 | case MSP430::PUSH16r: |
903 | 0 | case MSP430::RRA8n: |
904 | 0 | case MSP430::RRA8p: |
905 | 0 | case MSP430::RRA16n: |
906 | 0 | case MSP430::RRA16p: |
907 | 0 | case MSP430::RRC8n: |
908 | 0 | case MSP430::RRC8p: |
909 | 0 | case MSP430::RRC16n: |
910 | 0 | case MSP430::RRC16p: |
911 | 0 | case MSP430::SEXT16n: |
912 | 0 | case MSP430::SEXT16p: |
913 | 0 | case MSP430::SWPB16n: |
914 | 0 | case MSP430::SWPB16p: { |
915 | | // op: rs |
916 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
917 | 0 | op &= UINT64_C(15); |
918 | 0 | Value |= op; |
919 | 0 | break; |
920 | 0 | } |
921 | 0 | case MSP430::Br: { |
922 | | // op: rs |
923 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
924 | 0 | op &= UINT64_C(15); |
925 | 0 | op <<= 8; |
926 | 0 | Value |= op; |
927 | 0 | break; |
928 | 0 | } |
929 | 0 | case MSP430::RRA8r: |
930 | 0 | case MSP430::RRA16r: |
931 | 0 | case MSP430::RRC8r: |
932 | 0 | case MSP430::RRC16r: |
933 | 0 | case MSP430::SEXT16r: |
934 | 0 | case MSP430::SWPB16r: { |
935 | | // op: rs |
936 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
937 | 0 | op &= UINT64_C(15); |
938 | 0 | Value |= op; |
939 | 0 | break; |
940 | 0 | } |
941 | 0 | case MSP430::BIT8rn: |
942 | 0 | case MSP430::BIT8rp: |
943 | 0 | case MSP430::BIT8rr: |
944 | 0 | case MSP430::BIT16rn: |
945 | 0 | case MSP430::BIT16rp: |
946 | 0 | case MSP430::BIT16rr: |
947 | 0 | case MSP430::CMP8rn: |
948 | 0 | case MSP430::CMP8rp: |
949 | 0 | case MSP430::CMP8rr: |
950 | 0 | case MSP430::CMP16rn: |
951 | 0 | case MSP430::CMP16rp: |
952 | 0 | case MSP430::CMP16rr: |
953 | 0 | case MSP430::MOV8rn: |
954 | 0 | case MSP430::MOV8rr: |
955 | 0 | case MSP430::MOV16rn: |
956 | 0 | case MSP430::MOV16rr: |
957 | 0 | case MSP430::MOVZX16rr8: |
958 | 0 | case MSP430::ZEXT16r: { |
959 | | // op: rs |
960 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
961 | 0 | op &= UINT64_C(15); |
962 | 0 | op <<= 8; |
963 | 0 | Value |= op; |
964 | | // op: rd |
965 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
966 | 0 | op &= UINT64_C(15); |
967 | 0 | Value |= op; |
968 | 0 | break; |
969 | 0 | } |
970 | 0 | case MSP430::ADD8mn: |
971 | 0 | case MSP430::ADD8mp: |
972 | 0 | case MSP430::ADD8mr: |
973 | 0 | case MSP430::ADD16mn: |
974 | 0 | case MSP430::ADD16mp: |
975 | 0 | case MSP430::ADD16mr: |
976 | 0 | case MSP430::ADDC8mn: |
977 | 0 | case MSP430::ADDC8mp: |
978 | 0 | case MSP430::ADDC8mr: |
979 | 0 | case MSP430::ADDC16mn: |
980 | 0 | case MSP430::ADDC16mp: |
981 | 0 | case MSP430::ADDC16mr: |
982 | 0 | case MSP430::AND8mn: |
983 | 0 | case MSP430::AND8mp: |
984 | 0 | case MSP430::AND8mr: |
985 | 0 | case MSP430::AND16mn: |
986 | 0 | case MSP430::AND16mp: |
987 | 0 | case MSP430::AND16mr: |
988 | 0 | case MSP430::BIC8mn: |
989 | 0 | case MSP430::BIC8mp: |
990 | 0 | case MSP430::BIC8mr: |
991 | 0 | case MSP430::BIC16mn: |
992 | 0 | case MSP430::BIC16mp: |
993 | 0 | case MSP430::BIC16mr: |
994 | 0 | case MSP430::BIS8mn: |
995 | 0 | case MSP430::BIS8mp: |
996 | 0 | case MSP430::BIS8mr: |
997 | 0 | case MSP430::BIS16mn: |
998 | 0 | case MSP430::BIS16mp: |
999 | 0 | case MSP430::BIS16mr: |
1000 | 0 | case MSP430::BIT8mn: |
1001 | 0 | case MSP430::BIT8mp: |
1002 | 0 | case MSP430::BIT8mr: |
1003 | 0 | case MSP430::BIT16mn: |
1004 | 0 | case MSP430::BIT16mp: |
1005 | 0 | case MSP430::BIT16mr: |
1006 | 0 | case MSP430::CMP8mn: |
1007 | 0 | case MSP430::CMP8mp: |
1008 | 0 | case MSP430::CMP8mr: |
1009 | 0 | case MSP430::CMP16mn: |
1010 | 0 | case MSP430::CMP16mp: |
1011 | 0 | case MSP430::CMP16mr: |
1012 | 0 | case MSP430::DADD8mn: |
1013 | 0 | case MSP430::DADD8mp: |
1014 | 0 | case MSP430::DADD8mr: |
1015 | 0 | case MSP430::DADD16mn: |
1016 | 0 | case MSP430::DADD16mp: |
1017 | 0 | case MSP430::DADD16mr: |
1018 | 0 | case MSP430::MOV8mn: |
1019 | 0 | case MSP430::MOV8mr: |
1020 | 0 | case MSP430::MOV16mn: |
1021 | 0 | case MSP430::MOV16mr: |
1022 | 0 | case MSP430::SUB8mn: |
1023 | 0 | case MSP430::SUB8mp: |
1024 | 0 | case MSP430::SUB8mr: |
1025 | 0 | case MSP430::SUB16mn: |
1026 | 0 | case MSP430::SUB16mp: |
1027 | 0 | case MSP430::SUB16mr: |
1028 | 0 | case MSP430::SUBC8mn: |
1029 | 0 | case MSP430::SUBC8mp: |
1030 | 0 | case MSP430::SUBC8mr: |
1031 | 0 | case MSP430::SUBC16mn: |
1032 | 0 | case MSP430::SUBC16mp: |
1033 | 0 | case MSP430::SUBC16mr: |
1034 | 0 | case MSP430::XOR8mn: |
1035 | 0 | case MSP430::XOR8mp: |
1036 | 0 | case MSP430::XOR8mr: |
1037 | 0 | case MSP430::XOR16mn: |
1038 | 0 | case MSP430::XOR16mp: |
1039 | 0 | case MSP430::XOR16mr: { |
1040 | | // op: rs |
1041 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1042 | 0 | op &= UINT64_C(15); |
1043 | 0 | op <<= 8; |
1044 | 0 | Value |= op; |
1045 | | // op: dst |
1046 | 0 | op = getMemOpValue(MI, 0, Fixups, STI); |
1047 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
1048 | 0 | Value |= (op & UINT64_C(15)); |
1049 | 0 | break; |
1050 | 0 | } |
1051 | 0 | case MSP430::ADD8rn: |
1052 | 0 | case MSP430::ADD8rr: |
1053 | 0 | case MSP430::ADD16rn: |
1054 | 0 | case MSP430::ADD16rr: |
1055 | 0 | case MSP430::ADDC8rn: |
1056 | 0 | case MSP430::ADDC8rr: |
1057 | 0 | case MSP430::ADDC16rn: |
1058 | 0 | case MSP430::ADDC16rr: |
1059 | 0 | case MSP430::AND8rn: |
1060 | 0 | case MSP430::AND8rr: |
1061 | 0 | case MSP430::AND16rn: |
1062 | 0 | case MSP430::AND16rr: |
1063 | 0 | case MSP430::BIC8rn: |
1064 | 0 | case MSP430::BIC8rr: |
1065 | 0 | case MSP430::BIC16rn: |
1066 | 0 | case MSP430::BIC16rr: |
1067 | 0 | case MSP430::BIS8rn: |
1068 | 0 | case MSP430::BIS8rr: |
1069 | 0 | case MSP430::BIS16rn: |
1070 | 0 | case MSP430::BIS16rr: |
1071 | 0 | case MSP430::DADD8rn: |
1072 | 0 | case MSP430::DADD8rr: |
1073 | 0 | case MSP430::DADD16rn: |
1074 | 0 | case MSP430::DADD16rr: |
1075 | 0 | case MSP430::MOV8rp: |
1076 | 0 | case MSP430::MOV16rp: |
1077 | 0 | case MSP430::SUB8rn: |
1078 | 0 | case MSP430::SUB8rr: |
1079 | 0 | case MSP430::SUB16rn: |
1080 | 0 | case MSP430::SUB16rr: |
1081 | 0 | case MSP430::SUBC8rn: |
1082 | 0 | case MSP430::SUBC8rr: |
1083 | 0 | case MSP430::SUBC16rn: |
1084 | 0 | case MSP430::SUBC16rr: |
1085 | 0 | case MSP430::XOR8rn: |
1086 | 0 | case MSP430::XOR8rr: |
1087 | 0 | case MSP430::XOR16rn: |
1088 | 0 | case MSP430::XOR16rr: { |
1089 | | // op: rs |
1090 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1091 | 0 | op &= UINT64_C(15); |
1092 | 0 | op <<= 8; |
1093 | 0 | Value |= op; |
1094 | | // op: rd |
1095 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1096 | 0 | op &= UINT64_C(15); |
1097 | 0 | Value |= op; |
1098 | 0 | break; |
1099 | 0 | } |
1100 | 0 | case MSP430::ADD8rp: |
1101 | 0 | case MSP430::ADD16rp: |
1102 | 0 | case MSP430::ADDC8rp: |
1103 | 0 | case MSP430::ADDC16rp: |
1104 | 0 | case MSP430::AND8rp: |
1105 | 0 | case MSP430::AND16rp: |
1106 | 0 | case MSP430::BIC8rp: |
1107 | 0 | case MSP430::BIC16rp: |
1108 | 0 | case MSP430::BIS8rp: |
1109 | 0 | case MSP430::BIS16rp: |
1110 | 0 | case MSP430::DADD8rp: |
1111 | 0 | case MSP430::DADD16rp: |
1112 | 0 | case MSP430::SUB8rp: |
1113 | 0 | case MSP430::SUB16rp: |
1114 | 0 | case MSP430::SUBC8rp: |
1115 | 0 | case MSP430::SUBC16rp: |
1116 | 0 | case MSP430::XOR8rp: |
1117 | 0 | case MSP430::XOR16rp: { |
1118 | | // op: rs |
1119 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1120 | 0 | op &= UINT64_C(15); |
1121 | 0 | op <<= 8; |
1122 | 0 | Value |= op; |
1123 | | // op: rd |
1124 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1125 | 0 | op &= UINT64_C(15); |
1126 | 0 | Value |= op; |
1127 | 0 | break; |
1128 | 0 | } |
1129 | 0 | case MSP430::Bm: { |
1130 | | // op: src |
1131 | 0 | op = getMemOpValue(MI, 0, Fixups, STI); |
1132 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
1133 | 0 | Value |= (op & UINT64_C(15)) << 8; |
1134 | 0 | break; |
1135 | 0 | } |
1136 | 0 | case MSP430::CALLm: |
1137 | 0 | case MSP430::RRA8m: |
1138 | 0 | case MSP430::RRA16m: |
1139 | 0 | case MSP430::RRC8m: |
1140 | 0 | case MSP430::RRC16m: |
1141 | 0 | case MSP430::SEXT16m: |
1142 | 0 | case MSP430::SWPB16m: { |
1143 | | // op: src |
1144 | 0 | op = getMemOpValue(MI, 0, Fixups, STI); |
1145 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
1146 | 0 | Value |= (op & UINT64_C(15)); |
1147 | 0 | break; |
1148 | 0 | } |
1149 | 0 | case MSP430::ADD8mm: |
1150 | 0 | case MSP430::ADD16mm: |
1151 | 0 | case MSP430::ADDC8mm: |
1152 | 0 | case MSP430::ADDC16mm: |
1153 | 0 | case MSP430::AND8mm: |
1154 | 0 | case MSP430::AND16mm: |
1155 | 0 | case MSP430::BIC8mm: |
1156 | 0 | case MSP430::BIC16mm: |
1157 | 0 | case MSP430::BIS8mm: |
1158 | 0 | case MSP430::BIS16mm: |
1159 | 0 | case MSP430::BIT8mm: |
1160 | 0 | case MSP430::BIT16mm: |
1161 | 0 | case MSP430::CMP8mm: |
1162 | 0 | case MSP430::CMP16mm: |
1163 | 0 | case MSP430::DADD8mm: |
1164 | 0 | case MSP430::DADD16mm: |
1165 | 0 | case MSP430::MOV8mm: |
1166 | 0 | case MSP430::MOV16mm: |
1167 | 0 | case MSP430::SUB8mm: |
1168 | 0 | case MSP430::SUB16mm: |
1169 | 0 | case MSP430::SUBC8mm: |
1170 | 0 | case MSP430::SUBC16mm: |
1171 | 0 | case MSP430::XOR8mm: |
1172 | 0 | case MSP430::XOR16mm: { |
1173 | | // op: src |
1174 | 0 | op = getMemOpValue(MI, 2, Fixups, STI); |
1175 | 0 | Value |= (op & UINT64_C(1048560)) << 12; |
1176 | 0 | Value |= (op & UINT64_C(15)) << 8; |
1177 | | // op: dst |
1178 | 0 | op = getMemOpValue(MI, 0, Fixups, STI); |
1179 | 0 | Value |= (op & UINT64_C(1048560)) << 28; |
1180 | 0 | Value |= (op & UINT64_C(15)); |
1181 | 0 | break; |
1182 | 0 | } |
1183 | 0 | default: |
1184 | 0 | std::string msg; |
1185 | 0 | raw_string_ostream Msg(msg); |
1186 | 0 | Msg << "Not supported instr: " << MI; |
1187 | 0 | report_fatal_error(Msg.str().c_str()); |
1188 | 0 | } |
1189 | 0 | return Value; |
1190 | 0 | } |
1191 | | |
1192 | | #ifdef GET_OPERAND_BIT_OFFSET |
1193 | | #undef GET_OPERAND_BIT_OFFSET |
1194 | | |
1195 | | uint32_t MSP430MCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
1196 | | unsigned OpNum, |
1197 | | const MCSubtargetInfo &STI) const { |
1198 | | switch (MI.getOpcode()) { |
1199 | | case MSP430::ADDframe: |
1200 | | case MSP430::ADJCALLSTACKDOWN: |
1201 | | case MSP430::ADJCALLSTACKUP: |
1202 | | case MSP430::RET: |
1203 | | case MSP430::RETI: |
1204 | | case MSP430::Rrcl8: |
1205 | | case MSP430::Rrcl16: |
1206 | | case MSP430::Select8: |
1207 | | case MSP430::Select16: |
1208 | | case MSP430::Shl8: |
1209 | | case MSP430::Shl16: |
1210 | | case MSP430::Sra8: |
1211 | | case MSP430::Sra16: |
1212 | | case MSP430::Srl8: |
1213 | | case MSP430::Srl16: { |
1214 | | break; |
1215 | | } |
1216 | | case MSP430::JMP: { |
1217 | | switch (OpNum) { |
1218 | | case 0: |
1219 | | // op: dst |
1220 | | return 0; |
1221 | | } |
1222 | | break; |
1223 | | } |
1224 | | case MSP430::PUSH16c: { |
1225 | | switch (OpNum) { |
1226 | | case 0: |
1227 | | // op: imm |
1228 | | return 0; |
1229 | | } |
1230 | | break; |
1231 | | } |
1232 | | case MSP430::Bi: |
1233 | | case MSP430::CALLi: |
1234 | | case MSP430::PUSH16i: { |
1235 | | switch (OpNum) { |
1236 | | case 0: |
1237 | | // op: imm |
1238 | | return 16; |
1239 | | } |
1240 | | break; |
1241 | | } |
1242 | | case MSP430::BIT8ri: |
1243 | | case MSP430::BIT16ri: |
1244 | | case MSP430::CMP8ri: |
1245 | | case MSP430::CMP16ri: |
1246 | | case MSP430::MOV8ri: |
1247 | | case MSP430::MOV16ri: { |
1248 | | switch (OpNum) { |
1249 | | case 0: |
1250 | | // op: rd |
1251 | | return 0; |
1252 | | case 1: |
1253 | | // op: imm |
1254 | | return 16; |
1255 | | } |
1256 | | break; |
1257 | | } |
1258 | | case MSP430::BIT8rm: |
1259 | | case MSP430::BIT16rm: |
1260 | | case MSP430::CMP8rm: |
1261 | | case MSP430::CMP16rm: |
1262 | | case MSP430::MOV8rm: |
1263 | | case MSP430::MOV16rm: |
1264 | | case MSP430::MOVZX16rm8: { |
1265 | | switch (OpNum) { |
1266 | | case 0: |
1267 | | // op: rd |
1268 | | return 0; |
1269 | | case 1: |
1270 | | // op: src |
1271 | | return 8; |
1272 | | } |
1273 | | break; |
1274 | | } |
1275 | | case MSP430::ADD8ri: |
1276 | | case MSP430::ADD16ri: |
1277 | | case MSP430::ADDC8ri: |
1278 | | case MSP430::ADDC16ri: |
1279 | | case MSP430::AND8ri: |
1280 | | case MSP430::AND16ri: |
1281 | | case MSP430::BIC8ri: |
1282 | | case MSP430::BIC16ri: |
1283 | | case MSP430::BIS8ri: |
1284 | | case MSP430::BIS16ri: |
1285 | | case MSP430::DADD8ri: |
1286 | | case MSP430::DADD16ri: |
1287 | | case MSP430::SUB8ri: |
1288 | | case MSP430::SUB16ri: |
1289 | | case MSP430::SUBC8ri: |
1290 | | case MSP430::SUBC16ri: |
1291 | | case MSP430::XOR8ri: |
1292 | | case MSP430::XOR16ri: { |
1293 | | switch (OpNum) { |
1294 | | case 0: |
1295 | | // op: rd |
1296 | | return 0; |
1297 | | case 2: |
1298 | | // op: imm |
1299 | | return 16; |
1300 | | } |
1301 | | break; |
1302 | | } |
1303 | | case MSP430::ADD8rm: |
1304 | | case MSP430::ADD16rm: |
1305 | | case MSP430::ADDC8rm: |
1306 | | case MSP430::ADDC16rm: |
1307 | | case MSP430::AND8rm: |
1308 | | case MSP430::AND16rm: |
1309 | | case MSP430::BIC8rm: |
1310 | | case MSP430::BIC16rm: |
1311 | | case MSP430::BIS8rm: |
1312 | | case MSP430::BIS16rm: |
1313 | | case MSP430::DADD8rm: |
1314 | | case MSP430::DADD16rm: |
1315 | | case MSP430::SUB8rm: |
1316 | | case MSP430::SUB16rm: |
1317 | | case MSP430::SUBC8rm: |
1318 | | case MSP430::SUBC16rm: |
1319 | | case MSP430::XOR8rm: |
1320 | | case MSP430::XOR16rm: { |
1321 | | switch (OpNum) { |
1322 | | case 0: |
1323 | | // op: rd |
1324 | | return 0; |
1325 | | case 2: |
1326 | | // op: src |
1327 | | return 8; |
1328 | | } |
1329 | | break; |
1330 | | } |
1331 | | case MSP430::POP16r: { |
1332 | | switch (OpNum) { |
1333 | | case 0: |
1334 | | // op: rd |
1335 | | return 0; |
1336 | | } |
1337 | | break; |
1338 | | } |
1339 | | case MSP430::CALLn: |
1340 | | case MSP430::CALLp: |
1341 | | case MSP430::CALLr: |
1342 | | case MSP430::PUSH8r: |
1343 | | case MSP430::PUSH16r: |
1344 | | case MSP430::RRA8n: |
1345 | | case MSP430::RRA8p: |
1346 | | case MSP430::RRA16n: |
1347 | | case MSP430::RRA16p: |
1348 | | case MSP430::RRC8n: |
1349 | | case MSP430::RRC8p: |
1350 | | case MSP430::RRC16n: |
1351 | | case MSP430::RRC16p: |
1352 | | case MSP430::SEXT16n: |
1353 | | case MSP430::SEXT16p: |
1354 | | case MSP430::SWPB16n: |
1355 | | case MSP430::SWPB16p: { |
1356 | | switch (OpNum) { |
1357 | | case 0: |
1358 | | // op: rs |
1359 | | return 0; |
1360 | | } |
1361 | | break; |
1362 | | } |
1363 | | case MSP430::Br: { |
1364 | | switch (OpNum) { |
1365 | | case 0: |
1366 | | // op: rs |
1367 | | return 8; |
1368 | | } |
1369 | | break; |
1370 | | } |
1371 | | case MSP430::CALLm: |
1372 | | case MSP430::RRA8m: |
1373 | | case MSP430::RRA16m: |
1374 | | case MSP430::RRC8m: |
1375 | | case MSP430::RRC16m: |
1376 | | case MSP430::SEXT16m: |
1377 | | case MSP430::SWPB16m: { |
1378 | | switch (OpNum) { |
1379 | | case 0: |
1380 | | // op: src |
1381 | | return 0; |
1382 | | } |
1383 | | break; |
1384 | | } |
1385 | | case MSP430::Bm: { |
1386 | | switch (OpNum) { |
1387 | | case 0: |
1388 | | // op: src |
1389 | | return 8; |
1390 | | } |
1391 | | break; |
1392 | | } |
1393 | | case MSP430::JCC: { |
1394 | | switch (OpNum) { |
1395 | | case 1: |
1396 | | // op: cond |
1397 | | return 10; |
1398 | | case 0: |
1399 | | // op: dst |
1400 | | return 0; |
1401 | | } |
1402 | | break; |
1403 | | } |
1404 | | case MSP430::BIT8rc: |
1405 | | case MSP430::BIT16rc: |
1406 | | case MSP430::CMP8rc: |
1407 | | case MSP430::CMP16rc: |
1408 | | case MSP430::MOV8rc: |
1409 | | case MSP430::MOV16rc: { |
1410 | | switch (OpNum) { |
1411 | | case 1: |
1412 | | // op: imm |
1413 | | return 4; |
1414 | | case 0: |
1415 | | // op: rd |
1416 | | return 0; |
1417 | | } |
1418 | | break; |
1419 | | } |
1420 | | case MSP430::RRA8r: |
1421 | | case MSP430::RRA16r: |
1422 | | case MSP430::RRC8r: |
1423 | | case MSP430::RRC16r: |
1424 | | case MSP430::SEXT16r: |
1425 | | case MSP430::SWPB16r: { |
1426 | | switch (OpNum) { |
1427 | | case 1: |
1428 | | // op: rs |
1429 | | return 0; |
1430 | | } |
1431 | | break; |
1432 | | } |
1433 | | case MSP430::BIT8rn: |
1434 | | case MSP430::BIT8rp: |
1435 | | case MSP430::BIT8rr: |
1436 | | case MSP430::BIT16rn: |
1437 | | case MSP430::BIT16rp: |
1438 | | case MSP430::BIT16rr: |
1439 | | case MSP430::CMP8rn: |
1440 | | case MSP430::CMP8rp: |
1441 | | case MSP430::CMP8rr: |
1442 | | case MSP430::CMP16rn: |
1443 | | case MSP430::CMP16rp: |
1444 | | case MSP430::CMP16rr: |
1445 | | case MSP430::MOV8rn: |
1446 | | case MSP430::MOV8rr: |
1447 | | case MSP430::MOV16rn: |
1448 | | case MSP430::MOV16rr: |
1449 | | case MSP430::MOVZX16rr8: |
1450 | | case MSP430::ZEXT16r: { |
1451 | | switch (OpNum) { |
1452 | | case 1: |
1453 | | // op: rs |
1454 | | return 8; |
1455 | | case 0: |
1456 | | // op: rd |
1457 | | return 0; |
1458 | | } |
1459 | | break; |
1460 | | } |
1461 | | case MSP430::ADD8mi: |
1462 | | case MSP430::ADD16mi: |
1463 | | case MSP430::ADDC8mi: |
1464 | | case MSP430::ADDC16mi: |
1465 | | case MSP430::AND8mi: |
1466 | | case MSP430::AND16mi: |
1467 | | case MSP430::BIC8mi: |
1468 | | case MSP430::BIC16mi: |
1469 | | case MSP430::BIS8mi: |
1470 | | case MSP430::BIS16mi: |
1471 | | case MSP430::BIT8mi: |
1472 | | case MSP430::BIT16mi: |
1473 | | case MSP430::CMP8mi: |
1474 | | case MSP430::CMP16mi: |
1475 | | case MSP430::DADD8mi: |
1476 | | case MSP430::DADD16mi: |
1477 | | case MSP430::MOV8mi: |
1478 | | case MSP430::MOV16mi: |
1479 | | case MSP430::SUB8mi: |
1480 | | case MSP430::SUB16mi: |
1481 | | case MSP430::SUBC8mi: |
1482 | | case MSP430::SUBC16mi: |
1483 | | case MSP430::XOR8mi: |
1484 | | case MSP430::XOR16mi: { |
1485 | | switch (OpNum) { |
1486 | | case 2: |
1487 | | // op: imm |
1488 | | return 16; |
1489 | | case 0: |
1490 | | // op: dst |
1491 | | return 0; |
1492 | | } |
1493 | | break; |
1494 | | } |
1495 | | case MSP430::ADD8mc: |
1496 | | case MSP430::ADD16mc: |
1497 | | case MSP430::ADDC8mc: |
1498 | | case MSP430::ADDC16mc: |
1499 | | case MSP430::AND8mc: |
1500 | | case MSP430::AND16mc: |
1501 | | case MSP430::BIC8mc: |
1502 | | case MSP430::BIC16mc: |
1503 | | case MSP430::BIS8mc: |
1504 | | case MSP430::BIS16mc: |
1505 | | case MSP430::BIT8mc: |
1506 | | case MSP430::BIT16mc: |
1507 | | case MSP430::CMP8mc: |
1508 | | case MSP430::CMP16mc: |
1509 | | case MSP430::DADD8mc: |
1510 | | case MSP430::DADD16mc: |
1511 | | case MSP430::MOV8mc: |
1512 | | case MSP430::MOV16mc: |
1513 | | case MSP430::SUB8mc: |
1514 | | case MSP430::SUB16mc: |
1515 | | case MSP430::SUBC8mc: |
1516 | | case MSP430::SUBC16mc: |
1517 | | case MSP430::XOR8mc: |
1518 | | case MSP430::XOR16mc: { |
1519 | | switch (OpNum) { |
1520 | | case 2: |
1521 | | // op: imm |
1522 | | return 4; |
1523 | | case 0: |
1524 | | // op: dst |
1525 | | return 0; |
1526 | | } |
1527 | | break; |
1528 | | } |
1529 | | case MSP430::ADD8rc: |
1530 | | case MSP430::ADD16rc: |
1531 | | case MSP430::ADDC8rc: |
1532 | | case MSP430::ADDC16rc: |
1533 | | case MSP430::AND8rc: |
1534 | | case MSP430::AND16rc: |
1535 | | case MSP430::BIC8rc: |
1536 | | case MSP430::BIC16rc: |
1537 | | case MSP430::BIS8rc: |
1538 | | case MSP430::BIS16rc: |
1539 | | case MSP430::DADD8rc: |
1540 | | case MSP430::DADD16rc: |
1541 | | case MSP430::SUB8rc: |
1542 | | case MSP430::SUB16rc: |
1543 | | case MSP430::SUBC8rc: |
1544 | | case MSP430::SUBC16rc: |
1545 | | case MSP430::XOR8rc: |
1546 | | case MSP430::XOR16rc: { |
1547 | | switch (OpNum) { |
1548 | | case 2: |
1549 | | // op: imm |
1550 | | return 4; |
1551 | | case 0: |
1552 | | // op: rd |
1553 | | return 0; |
1554 | | } |
1555 | | break; |
1556 | | } |
1557 | | case MSP430::ADD8mn: |
1558 | | case MSP430::ADD8mp: |
1559 | | case MSP430::ADD8mr: |
1560 | | case MSP430::ADD16mn: |
1561 | | case MSP430::ADD16mp: |
1562 | | case MSP430::ADD16mr: |
1563 | | case MSP430::ADDC8mn: |
1564 | | case MSP430::ADDC8mp: |
1565 | | case MSP430::ADDC8mr: |
1566 | | case MSP430::ADDC16mn: |
1567 | | case MSP430::ADDC16mp: |
1568 | | case MSP430::ADDC16mr: |
1569 | | case MSP430::AND8mn: |
1570 | | case MSP430::AND8mp: |
1571 | | case MSP430::AND8mr: |
1572 | | case MSP430::AND16mn: |
1573 | | case MSP430::AND16mp: |
1574 | | case MSP430::AND16mr: |
1575 | | case MSP430::BIC8mn: |
1576 | | case MSP430::BIC8mp: |
1577 | | case MSP430::BIC8mr: |
1578 | | case MSP430::BIC16mn: |
1579 | | case MSP430::BIC16mp: |
1580 | | case MSP430::BIC16mr: |
1581 | | case MSP430::BIS8mn: |
1582 | | case MSP430::BIS8mp: |
1583 | | case MSP430::BIS8mr: |
1584 | | case MSP430::BIS16mn: |
1585 | | case MSP430::BIS16mp: |
1586 | | case MSP430::BIS16mr: |
1587 | | case MSP430::BIT8mn: |
1588 | | case MSP430::BIT8mp: |
1589 | | case MSP430::BIT8mr: |
1590 | | case MSP430::BIT16mn: |
1591 | | case MSP430::BIT16mp: |
1592 | | case MSP430::BIT16mr: |
1593 | | case MSP430::CMP8mn: |
1594 | | case MSP430::CMP8mp: |
1595 | | case MSP430::CMP8mr: |
1596 | | case MSP430::CMP16mn: |
1597 | | case MSP430::CMP16mp: |
1598 | | case MSP430::CMP16mr: |
1599 | | case MSP430::DADD8mn: |
1600 | | case MSP430::DADD8mp: |
1601 | | case MSP430::DADD8mr: |
1602 | | case MSP430::DADD16mn: |
1603 | | case MSP430::DADD16mp: |
1604 | | case MSP430::DADD16mr: |
1605 | | case MSP430::MOV8mn: |
1606 | | case MSP430::MOV8mr: |
1607 | | case MSP430::MOV16mn: |
1608 | | case MSP430::MOV16mr: |
1609 | | case MSP430::SUB8mn: |
1610 | | case MSP430::SUB8mp: |
1611 | | case MSP430::SUB8mr: |
1612 | | case MSP430::SUB16mn: |
1613 | | case MSP430::SUB16mp: |
1614 | | case MSP430::SUB16mr: |
1615 | | case MSP430::SUBC8mn: |
1616 | | case MSP430::SUBC8mp: |
1617 | | case MSP430::SUBC8mr: |
1618 | | case MSP430::SUBC16mn: |
1619 | | case MSP430::SUBC16mp: |
1620 | | case MSP430::SUBC16mr: |
1621 | | case MSP430::XOR8mn: |
1622 | | case MSP430::XOR8mp: |
1623 | | case MSP430::XOR8mr: |
1624 | | case MSP430::XOR16mn: |
1625 | | case MSP430::XOR16mp: |
1626 | | case MSP430::XOR16mr: { |
1627 | | switch (OpNum) { |
1628 | | case 2: |
1629 | | // op: rs |
1630 | | return 8; |
1631 | | case 0: |
1632 | | // op: dst |
1633 | | return 0; |
1634 | | } |
1635 | | break; |
1636 | | } |
1637 | | case MSP430::ADD8rn: |
1638 | | case MSP430::ADD8rr: |
1639 | | case MSP430::ADD16rn: |
1640 | | case MSP430::ADD16rr: |
1641 | | case MSP430::ADDC8rn: |
1642 | | case MSP430::ADDC8rr: |
1643 | | case MSP430::ADDC16rn: |
1644 | | case MSP430::ADDC16rr: |
1645 | | case MSP430::AND8rn: |
1646 | | case MSP430::AND8rr: |
1647 | | case MSP430::AND16rn: |
1648 | | case MSP430::AND16rr: |
1649 | | case MSP430::BIC8rn: |
1650 | | case MSP430::BIC8rr: |
1651 | | case MSP430::BIC16rn: |
1652 | | case MSP430::BIC16rr: |
1653 | | case MSP430::BIS8rn: |
1654 | | case MSP430::BIS8rr: |
1655 | | case MSP430::BIS16rn: |
1656 | | case MSP430::BIS16rr: |
1657 | | case MSP430::DADD8rn: |
1658 | | case MSP430::DADD8rr: |
1659 | | case MSP430::DADD16rn: |
1660 | | case MSP430::DADD16rr: |
1661 | | case MSP430::MOV8rp: |
1662 | | case MSP430::MOV16rp: |
1663 | | case MSP430::SUB8rn: |
1664 | | case MSP430::SUB8rr: |
1665 | | case MSP430::SUB16rn: |
1666 | | case MSP430::SUB16rr: |
1667 | | case MSP430::SUBC8rn: |
1668 | | case MSP430::SUBC8rr: |
1669 | | case MSP430::SUBC16rn: |
1670 | | case MSP430::SUBC16rr: |
1671 | | case MSP430::XOR8rn: |
1672 | | case MSP430::XOR8rr: |
1673 | | case MSP430::XOR16rn: |
1674 | | case MSP430::XOR16rr: { |
1675 | | switch (OpNum) { |
1676 | | case 2: |
1677 | | // op: rs |
1678 | | return 8; |
1679 | | case 0: |
1680 | | // op: rd |
1681 | | return 0; |
1682 | | } |
1683 | | break; |
1684 | | } |
1685 | | case MSP430::ADD8mm: |
1686 | | case MSP430::ADD16mm: |
1687 | | case MSP430::ADDC8mm: |
1688 | | case MSP430::ADDC16mm: |
1689 | | case MSP430::AND8mm: |
1690 | | case MSP430::AND16mm: |
1691 | | case MSP430::BIC8mm: |
1692 | | case MSP430::BIC16mm: |
1693 | | case MSP430::BIS8mm: |
1694 | | case MSP430::BIS16mm: |
1695 | | case MSP430::BIT8mm: |
1696 | | case MSP430::BIT16mm: |
1697 | | case MSP430::CMP8mm: |
1698 | | case MSP430::CMP16mm: |
1699 | | case MSP430::DADD8mm: |
1700 | | case MSP430::DADD16mm: |
1701 | | case MSP430::MOV8mm: |
1702 | | case MSP430::MOV16mm: |
1703 | | case MSP430::SUB8mm: |
1704 | | case MSP430::SUB16mm: |
1705 | | case MSP430::SUBC8mm: |
1706 | | case MSP430::SUBC16mm: |
1707 | | case MSP430::XOR8mm: |
1708 | | case MSP430::XOR16mm: { |
1709 | | switch (OpNum) { |
1710 | | case 2: |
1711 | | // op: src |
1712 | | return 8; |
1713 | | case 0: |
1714 | | // op: dst |
1715 | | return 0; |
1716 | | } |
1717 | | break; |
1718 | | } |
1719 | | case MSP430::ADD8rp: |
1720 | | case MSP430::ADD16rp: |
1721 | | case MSP430::ADDC8rp: |
1722 | | case MSP430::ADDC16rp: |
1723 | | case MSP430::AND8rp: |
1724 | | case MSP430::AND16rp: |
1725 | | case MSP430::BIC8rp: |
1726 | | case MSP430::BIC16rp: |
1727 | | case MSP430::BIS8rp: |
1728 | | case MSP430::BIS16rp: |
1729 | | case MSP430::DADD8rp: |
1730 | | case MSP430::DADD16rp: |
1731 | | case MSP430::SUB8rp: |
1732 | | case MSP430::SUB16rp: |
1733 | | case MSP430::SUBC8rp: |
1734 | | case MSP430::SUBC16rp: |
1735 | | case MSP430::XOR8rp: |
1736 | | case MSP430::XOR16rp: { |
1737 | | switch (OpNum) { |
1738 | | case 3: |
1739 | | // op: rs |
1740 | | return 8; |
1741 | | case 0: |
1742 | | // op: rd |
1743 | | return 0; |
1744 | | } |
1745 | | break; |
1746 | | } |
1747 | | } |
1748 | | std::string msg; |
1749 | | raw_string_ostream Msg(msg); |
1750 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
1751 | | report_fatal_error(Msg.str().c_str()); |
1752 | | } |
1753 | | |
1754 | | #endif // GET_OPERAND_BIT_OFFSET |
1755 | | |