Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Mips/MipsGenAsmMatcher.inc
Line
Count
Source (jump to first uncovered line)
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Assembly Matcher Source Fragment                                           *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|* From: Mips.td                                                              *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_ASSEMBLER_HEADER
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#undef GET_ASSEMBLER_HEADER
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  // This should be included into the middle of the declaration of
14
  // your subclasses implementation of MCTargetAsmParser.
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  FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const;
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  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
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                       const OperandVector &Operands);
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  void convertToMapAndConstraints(unsigned Kind,
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                           const OperandVector &Operands) override;
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
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                                uint64_t &ErrorInfo,
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                                FeatureBitset &MissingFeatures,
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                                bool matchingInlineAsm,
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                                unsigned VariantID = 0);
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  unsigned MatchInstructionImpl(const OperandVector &Operands,
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                                MCInst &Inst,
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                                uint64_t &ErrorInfo,
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                                bool matchingInlineAsm,
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0
                                unsigned VariantID = 0) {
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0
    FeatureBitset MissingFeatures;
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0
    return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
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0
                                matchingInlineAsm, VariantID);
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0
  }
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  ParseStatus MatchOperandParserImpl(
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    OperandVector &Operands,
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    StringRef Mnemonic,
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    bool ParseForAllFeatures = false);
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  ParseStatus tryCustomParseOperand(
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    OperandVector &Operands,
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    unsigned MCK);
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#endif // GET_ASSEMBLER_HEADER
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46
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#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
48
#undef GET_OPERAND_DIAGNOSTIC_TYPES
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50
  Match_Immz,
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  Match_MemSImm10,
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  Match_MemSImm10Lsl1,
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  Match_MemSImm10Lsl2,
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  Match_MemSImm10Lsl3,
55
  Match_MemSImm11,
56
  Match_MemSImm12,
57
  Match_MemSImm16,
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  Match_MemSImm9,
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  Match_MemSImmPtr,
60
  Match_SImm10_0,
61
  Match_SImm10_Lsl1,
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  Match_SImm10_Lsl2,
63
  Match_SImm10_Lsl3,
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  Match_SImm11_0,
65
  Match_SImm16,
66
  Match_SImm16_Relaxed,
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  Match_SImm19_Lsl2,
68
  Match_SImm32,
69
  Match_SImm32_Relaxed,
70
  Match_SImm4_0,
71
  Match_SImm5_0,
72
  Match_SImm6_0,
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  Match_SImm7_Lsl2,
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  Match_SImm9_0,
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  Match_UImm10_0,
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  Match_UImm16,
77
  Match_UImm16_AltRelaxed,
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  Match_UImm16_Relaxed,
79
  Match_UImm1_0,
80
  Match_UImm20_0,
81
  Match_UImm26_0,
82
  Match_UImm2_0,
83
  Match_UImm2_1,
84
  Match_UImm32_Coerced,
85
  Match_UImm3_0,
86
  Match_UImm4_0,
87
  Match_UImm5_0,
88
  Match_UImm5_0_Report_UImm6,
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  Match_UImm5_1,
90
  Match_UImm5_32,
91
  Match_UImm5_33,
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  Match_UImm5_Lsl2,
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  Match_UImm6_0,
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  Match_UImm6_Lsl2,
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  Match_UImm7_0,
96
  Match_UImm7_N1,
97
  Match_UImm8_0,
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  Match_UImmRange2_64,
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  END_OPERAND_DIAGNOSTIC_TYPES
100
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
101
102
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#ifdef GET_REGISTER_MATCHER
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#undef GET_REGISTER_MATCHER
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106
// Bits for subtarget features that participate in instruction matching.
107
enum SubtargetFeatureBits : uint8_t {
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  Feature_HasMips2Bit = 11,
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  Feature_HasMips3_32Bit = 14,
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  Feature_HasMips3_32r2Bit = 15,
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  Feature_HasMips3Bit = 12,
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  Feature_NotMips3Bit = 47,
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  Feature_HasMips4_32Bit = 16,
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  Feature_NotMips4_32Bit = 48,
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  Feature_HasMips4_32r2Bit = 17,
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  Feature_HasMips5_32r2Bit = 18,
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  Feature_HasMips32Bit = 19,
118
  Feature_HasMips32r2Bit = 20,
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  Feature_HasMips32r5Bit = 21,
120
  Feature_HasMips32r6Bit = 22,
121
  Feature_NotMips32r6Bit = 49,
122
  Feature_IsGP64bitBit = 33,
123
  Feature_IsGP32bitBit = 32,
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  Feature_IsPTR64bitBit = 37,
125
  Feature_IsPTR32bitBit = 36,
126
  Feature_HasMips64Bit = 23,
127
  Feature_NotMips64Bit = 50,
128
  Feature_HasMips64r2Bit = 24,
129
  Feature_HasMips64r5Bit = 25,
130
  Feature_HasMips64r6Bit = 26,
131
  Feature_NotMips64r6Bit = 51,
132
  Feature_InMips16ModeBit = 30,
133
  Feature_NotInMips16ModeBit = 46,
134
  Feature_HasCnMipsBit = 1,
135
  Feature_NotCnMipsBit = 42,
136
  Feature_HasCnMipsPBit = 2,
137
  Feature_NotCnMipsPBit = 43,
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  Feature_IsSym32Bit = 39,
139
  Feature_IsSym64Bit = 40,
140
  Feature_HasStdEncBit = 27,
141
  Feature_InMicroMipsBit = 29,
142
  Feature_NotInMicroMipsBit = 45,
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  Feature_HasEVABit = 6,
144
  Feature_HasMSABit = 8,
145
  Feature_HasMadd4Bit = 10,
146
  Feature_HasMTBit = 9,
147
  Feature_UseIndirectJumpsHazardBit = 52,
148
  Feature_NoIndirectJumpGuardsBit = 41,
149
  Feature_HasCRCBit = 0,
150
  Feature_HasVirtBit = 28,
151
  Feature_HasGINVBit = 7,
152
  Feature_IsFP64bitBit = 31,
153
  Feature_NotFP64bitBit = 44,
154
  Feature_IsSingleFloatBit = 38,
155
  Feature_IsNotSingleFloatBit = 34,
156
  Feature_IsNotSoftFloatBit = 35,
157
  Feature_HasMips3DBit = 13,
158
  Feature_HasDSPBit = 3,
159
  Feature_HasDSPR2Bit = 4,
160
  Feature_HasDSPR3Bit = 5,
161
};
162
163
#endif // GET_REGISTER_MATCHER
164
165
166
#ifdef GET_SUBTARGET_FEATURE_NAME
167
#undef GET_SUBTARGET_FEATURE_NAME
168
169
// User-level names for subtarget features that participate in
170
// instruction matching.
171
static const char *getSubtargetFeatureName(uint64_t Val) {
172
  switch(Val) {
173
  case Feature_HasMips2Bit: return "";
174
  case Feature_HasMips3_32Bit: return "";
175
  case Feature_HasMips3_32r2Bit: return "";
176
  case Feature_HasMips3Bit: return "";
177
  case Feature_NotMips3Bit: return "";
178
  case Feature_HasMips4_32Bit: return "";
179
  case Feature_NotMips4_32Bit: return "";
180
  case Feature_HasMips4_32r2Bit: return "";
181
  case Feature_HasMips5_32r2Bit: return "";
182
  case Feature_HasMips32Bit: return "";
183
  case Feature_HasMips32r2Bit: return "";
184
  case Feature_HasMips32r5Bit: return "";
185
  case Feature_HasMips32r6Bit: return "";
186
  case Feature_NotMips32r6Bit: return "";
187
  case Feature_IsGP64bitBit: return "";
188
  case Feature_IsGP32bitBit: return "";
189
  case Feature_IsPTR64bitBit: return "";
190
  case Feature_IsPTR32bitBit: return "";
191
  case Feature_HasMips64Bit: return "";
192
  case Feature_NotMips64Bit: return "";
193
  case Feature_HasMips64r2Bit: return "";
194
  case Feature_HasMips64r5Bit: return "";
195
  case Feature_HasMips64r6Bit: return "";
196
  case Feature_NotMips64r6Bit: return "";
197
  case Feature_InMips16ModeBit: return "";
198
  case Feature_NotInMips16ModeBit: return "";
199
  case Feature_HasCnMipsBit: return "";
200
  case Feature_NotCnMipsBit: return "";
201
  case Feature_HasCnMipsPBit: return "";
202
  case Feature_NotCnMipsPBit: return "";
203
  case Feature_IsSym32Bit: return "";
204
  case Feature_IsSym64Bit: return "";
205
  case Feature_HasStdEncBit: return "";
206
  case Feature_InMicroMipsBit: return "";
207
  case Feature_NotInMicroMipsBit: return "";
208
  case Feature_HasEVABit: return "";
209
  case Feature_HasMSABit: return "";
210
  case Feature_HasMadd4Bit: return "";
211
  case Feature_HasMTBit: return "";
212
  case Feature_UseIndirectJumpsHazardBit: return "";
213
  case Feature_NoIndirectJumpGuardsBit: return "";
214
  case Feature_HasCRCBit: return "";
215
  case Feature_HasVirtBit: return "";
216
  case Feature_HasGINVBit: return "";
217
  case Feature_IsFP64bitBit: return "";
218
  case Feature_NotFP64bitBit: return "";
219
  case Feature_IsSingleFloatBit: return "";
220
  case Feature_IsNotSingleFloatBit: return "";
221
  case Feature_IsNotSoftFloatBit: return "";
222
  case Feature_HasMips3DBit: return "";
223
  case Feature_HasDSPBit: return "";
224
  case Feature_HasDSPR2Bit: return "";
225
  case Feature_HasDSPR3Bit: return "";
226
  default: return "(unknown)";
227
  }
228
}
229
230
#endif // GET_SUBTARGET_FEATURE_NAME
231
232
233
#ifdef GET_MATCHER_IMPLEMENTATION
234
#undef GET_MATCHER_IMPLEMENTATION
235
236
enum {
237
  Tie0_1_1,
238
  Tie0_1_2,
239
};
240
241
static const uint8_t TiedAsmOperandTable[][3] = {
242
  /* Tie0_1_1 */ { 0, 1, 1 },
243
  /* Tie0_1_2 */ { 0, 1, 2 },
244
};
245
246
namespace {
247
enum OperatorConversionKind {
248
  CVT_Done,
249
  CVT_Reg,
250
  CVT_Tied,
251
  CVT_95_addGPR32AsmRegOperands,
252
  CVT_95_addAFGR64AsmRegOperands,
253
  CVT_95_addFGR64AsmRegOperands,
254
  CVT_95_addFGR32AsmRegOperands,
255
  CVT_95_addSImmOperands_LT_32_GT_,
256
  CVT_95_addMSA128AsmRegOperands,
257
  CVT_95_addSImmOperands_LT_16_GT_,
258
  CVT_95_Reg,
259
  CVT_95_addImmOperands,
260
  CVT_95_addGPRMM16AsmRegOperands,
261
  CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_,
262
  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,
263
  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,
264
  CVT_95_addUImmOperands_LT_16_GT_,
265
  CVT_95_addGPR64AsmRegOperands,
266
  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,
267
  CVT_regZERO,
268
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,
269
  CVT_regFCC0,
270
  CVT_95_addFCCAsmRegOperands,
271
  CVT_95_addCOP2AsmRegOperands,
272
  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,
273
  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,
274
  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,
275
  CVT_imm_95_0,
276
  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,
277
  CVT_95_addMemOperands,
278
  CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_,
279
  CVT_95_addCCRAsmRegOperands,
280
  CVT_95_addMSACtrlAsmRegOperands,
281
  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,
282
  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,
283
  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,
284
  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,
285
  CVT_95_addGPR32NonZeroAsmRegOperands,
286
  CVT_95_addGPR32ZeroAsmRegOperands,
287
  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,
288
  CVT_95_addCOP0AsmRegOperands,
289
  CVT_regZERO_64,
290
  CVT_95_addACC64DSPAsmRegOperands,
291
  CVT_95_addConstantUImmOperands_LT_1_GT_,
292
  CVT_regRA,
293
  CVT_regRA_64,
294
  CVT_95_addMicroMipsMemOperands,
295
  CVT_95_addCOP3AsmRegOperands,
296
  CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_,
297
  CVT_95_addConstantUImmOperands_LT_32_GT_,
298
  CVT_95_addStrictlyAFGR64AsmRegOperands,
299
  CVT_95_addStrictlyFGR64AsmRegOperands,
300
  CVT_95_addStrictlyFGR32AsmRegOperands,
301
  CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_,
302
  CVT_95_addRegListOperands,
303
  CVT_ConvertXWPOperands,
304
  CVT_regAC0,
305
  CVT_95_addGPRMM16AsmRegMovePPairFirstOperands,
306
  CVT_95_addGPRMM16AsmRegMovePPairSecondOperands,
307
  CVT_95_addGPRMM16AsmRegMovePOperands,
308
  CVT_95_addHI32DSPAsmRegOperands,
309
  CVT_95_addLO32DSPAsmRegOperands,
310
  CVT_regS0,
311
  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,
312
  CVT_95_addHWRegsAsmRegOperands,
313
  CVT_95_addGPRMM16AsmRegZeroOperands,
314
  CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_,
315
  CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_,
316
  CVT_imm_95_2,
317
  CVT_imm_95_6,
318
  CVT_imm_95_4,
319
  CVT_imm_95_5,
320
  CVT_imm_95_31,
321
  CVT_NUM_CONVERTERS
322
};
323
324
enum InstructionConversionKind {
325
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,
326
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
327
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,
328
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,
329
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,
330
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1,
331
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
332
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2,
333
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
334
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
335
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
336
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,
337
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,
338
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1,
339
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1,
340
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2,
341
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2,
342
  Convert__SImm161_1,
343
  Convert__Reg1_0__SImm161_1,
344
  Convert__Reg1_0__SImm161_2,
345
  Convert__Reg1_0__Reg1_1__SImm161_2,
346
  Convert__Reg1_0__Tie0_1_1__SImm161_1,
347
  Convert__GPR32AsmReg1_0__Simm19_Lsl21_1,
348
  Convert__GPRMM16AsmReg1_0__Imm1_1,
349
  Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1,
350
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,
351
  Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1,
352
  Convert__Imm1_0,
353
  Convert__Reg1_0__Reg1_1__Reg1_2,
354
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,
355
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,
356
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,
357
  Convert__GPR32AsmReg1_0__SImm161_1,
358
  Convert__Reg1_0__Tie0_1_1__Reg1_1,
359
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,
360
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,
361
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,
362
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,
363
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1,
364
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,
365
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1,
366
  Convert__regZERO__regZERO__JumpTarget1_0,
367
  Convert__JumpTarget1_0,
368
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,
369
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,
370
  Convert__regZERO__JumpTarget1_0,
371
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1,
372
  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,
373
  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,
374
  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,
375
  Convert__FGR64AsmReg1_0__JumpTarget1_1,
376
  Convert__regFCC0__JumpTarget1_0,
377
  Convert__FCCAsmReg1_0__JumpTarget1_1,
378
  Convert__COP2AsmReg1_0__JumpTarget1_1,
379
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,
380
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,
381
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,
382
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,
383
  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,
384
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2,
385
  Convert__Reg1_0__JumpTarget1_1,
386
  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,
387
  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,
388
  Convert__GPR32AsmReg1_0__JumpTarget1_1,
389
  Convert__GPR64AsmReg1_0__JumpTarget1_1,
390
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2,
391
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2,
392
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2,
393
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2,
394
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2,
395
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2,
396
  Convert__MSA128AsmReg1_0__JumpTarget1_1,
397
  Convert__imm_95_0__imm_95_0,
398
  Convert_NoOperands,
399
  Convert__ConstantUImm10_01_0__imm_95_0,
400
  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,
401
  Convert__ConstantUImm4_01_0,
402
  Convert__SImm161_0,
403
  Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1,
404
  Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1,
405
  Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,
406
  Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
407
  Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1,
408
  Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
409
  Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0,
410
  Convert__Mem2_1__ConstantUImm5_01_0,
411
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,
412
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,
413
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,
414
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2,
415
  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,
416
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1,
417
  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,
418
  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,
419
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,
420
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,
421
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,
422
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,
423
  Convert__Reg1_0__Reg1_1,
424
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,
425
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
426
  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
427
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
428
  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
429
  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,
430
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0,
431
  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,
432
  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,
433
  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,
434
  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,
435
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1,
436
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2,
437
  Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2,
438
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,
439
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2,
440
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,
441
  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,
442
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,
443
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,
444
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3,
445
  Convert__regZERO,
446
  Convert__GPR32AsmReg1_0,
447
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1,
448
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1,
449
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1,
450
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1,
451
  Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1,
452
  Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1,
453
  Convert__Reg1_1__Reg1_2,
454
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,
455
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2,
456
  Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
457
  Convert__GPR64AsmReg1_0__Imm1_1,
458
  Convert__GPR64AsmReg1_0__Mem2_1,
459
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,
460
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,
461
  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
462
  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,
463
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,
464
  Convert__GPR64AsmReg1_0__UImm161_1,
465
  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
466
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
467
  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
468
  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,
469
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,
470
  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2,
471
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2,
472
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,
473
  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,
474
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
475
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,
476
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1,
477
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,
478
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,
479
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,
480
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,
481
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,
482
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1,
483
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,
484
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,
485
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,
486
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,
487
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,
488
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,
489
  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,
490
  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,
491
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2,
492
  Convert__GPR32AsmReg1_0__ConstantUImm2_01_1,
493
  Convert__imm_95_0,
494
  Convert__ConstantUImm10_01_0,
495
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1,
496
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2,
497
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2,
498
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2,
499
  Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2,
500
  Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1,
501
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
502
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
503
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
504
  Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,
505
  Convert__regRA__GPR32AsmReg1_0,
506
  Convert__regRA_64__GPR64AsmReg1_0,
507
  Convert__Reg1_0,
508
  Convert__GPR32AsmReg1_0__imm_95_0,
509
  Convert__GPR64AsmReg1_0__imm_95_0,
510
  Convert__regZERO__GPR32AsmReg1_0,
511
  Convert__GPR64AsmReg1_0,
512
  Convert__regZERO_64__GPR64AsmReg1_0,
513
  Convert__UImm5Lsl21_0,
514
  Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1,
515
  Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1,
516
  Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1,
517
  Convert__GPR32AsmReg1_0__Imm1_1,
518
  Convert__GPR32AsmReg1_0__Mem2_1,
519
  Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1,
520
  Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1,
521
  Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1,
522
  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,
523
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
524
  Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1,
525
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1,
526
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1,
527
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1,
528
  Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1,
529
  Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1,
530
  Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1,
531
  Convert__COP3AsmReg1_0__Mem2_1,
532
  Convert__MSA128AsmReg1_0__ConstantSImm10_01_1,
533
  Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1,
534
  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
535
  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
536
  Convert__GPR32AsmReg1_0__UImm32_Coerced1_1,
537
  Convert__StrictlyAFGR64AsmReg1_0__Imm1_1,
538
  Convert__StrictlyFGR64AsmReg1_0__Imm1_1,
539
  Convert__StrictlyFGR32AsmReg1_0__Imm1_1,
540
  Convert__GPRMM16AsmReg1_0__UImm7_N11_1,
541
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,
542
  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,
543
  Convert__GPR32AsmReg1_0__UImm161_1,
544
  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,
545
  Convert__Reg1_0__Imm1_1__imm_95_0,
546
  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,
547
  Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1,
548
  Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1,
549
  Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1,
550
  Convert__RegList1_0__Mem2_1,
551
  Convert__RegList161_0__MemOffsetUimm42_1,
552
  ConvertCustom_ConvertXWPOperands,
553
  Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1,
554
  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,
555
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,
556
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,
557
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,
558
  Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2,
559
  Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2,
560
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,
561
  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2,
562
  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,
563
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,
564
  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2,
565
  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,
566
  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,
567
  Convert__GPR32AsmReg1_0__regAC0,
568
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,
569
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
570
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,
571
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,
572
  Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3,
573
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
574
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
575
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
576
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1,
577
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
578
  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
579
  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
580
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1,
581
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
582
  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
583
  Convert__FGR64AsmReg1_1__GPR32AsmReg1_0,
584
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,
585
  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2,
586
  Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
587
  Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0,
588
  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,
589
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1,
590
  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,
591
  Convert__regAC0__GPR32AsmReg1_0,
592
  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0,
593
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0,
594
  Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4,
595
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,
596
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,
597
  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,
598
  Convert__regZERO__regZERO__imm_95_0,
599
  Convert__regZERO__regS0,
600
  Convert__regZERO__regZERO,
601
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO,
602
  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,
603
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,
604
  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,
605
  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,
606
  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,
607
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
608
  Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,
609
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,
610
  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2,
611
  Convert__GPR32AsmReg1_0__ConstantSImm10_01_1,
612
  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,
613
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,
614
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,
615
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_2,
616
  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,
617
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1,
618
  Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1,
619
  Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1,
620
  Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1,
621
  Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1,
622
  Convert__ConstantUImm20_01_0,
623
  Convert__Reg1_0__Tie0_1_1,
624
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1,
625
  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2,
626
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1,
627
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2,
628
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0,
629
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1,
630
  Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1,
631
  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1,
632
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,
633
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,
634
  Convert__UImm161_0,
635
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3,
636
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3,
637
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3,
638
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3,
639
  Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3,
640
  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,
641
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,
642
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3,
643
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3,
644
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3,
645
  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3,
646
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,
647
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,
648
  Convert__ConstantUImm5_01_0,
649
  Convert__MemOffsetSimm16_02_0,
650
  Convert__imm_95_2,
651
  Convert__imm_95_6,
652
  Convert__imm_95_4,
653
  Convert__imm_95_5,
654
  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,
655
  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2,
656
  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2,
657
  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2,
658
  Convert__GPR32AsmReg1_0__imm_95_31,
659
  CVT_NUM_SIGNATURES
660
};
661
662
} // end anonymous namespace
663
664
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
665
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1
666
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
667
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1
668
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
669
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1
670
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
671
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1
672
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
673
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1
674
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
675
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1
676
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
677
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
678
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
679
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2
680
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
681
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
682
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
683
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
684
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
685
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
686
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
687
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1
688
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
689
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2
690
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
691
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1
692
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
693
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1
694
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
695
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2
696
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
697
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2
698
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
699
  // Convert__SImm161_1
700
  { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
701
  // Convert__Reg1_0__SImm161_1
702
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
703
  // Convert__Reg1_0__SImm161_2
704
  { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
705
  // Convert__Reg1_0__Reg1_1__SImm161_2
706
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
707
  // Convert__Reg1_0__Tie0_1_1__SImm161_1
708
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
709
  // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1
710
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
711
  // Convert__GPRMM16AsmReg1_0__Imm1_1
712
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
713
  // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1
714
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
715
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2
716
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
717
  // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1
718
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done },
719
  // Convert__Imm1_0
720
  { CVT_95_addImmOperands, 1, CVT_Done },
721
  // Convert__Reg1_0__Reg1_1__Reg1_2
722
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
723
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2
724
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },
725
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2
726
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
727
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3
728
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
729
  // Convert__GPR32AsmReg1_0__SImm161_1
730
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
731
  // Convert__Reg1_0__Tie0_1_1__Reg1_1
732
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done },
733
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1
734
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
735
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1
736
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
737
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2
738
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
739
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2
740
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
741
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1
742
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
743
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2
744
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
745
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1
746
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
747
  // Convert__regZERO__regZERO__JumpTarget1_0
748
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
749
  // Convert__JumpTarget1_0
750
  { CVT_95_addImmOperands, 1, CVT_Done },
751
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1
752
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
753
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2
754
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
755
  // Convert__regZERO__JumpTarget1_0
756
  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },
757
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1
758
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done },
759
  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2
760
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
761
  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2
762
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
763
  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2
764
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },
765
  // Convert__FGR64AsmReg1_0__JumpTarget1_1
766
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
767
  // Convert__regFCC0__JumpTarget1_0
768
  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },
769
  // Convert__FCCAsmReg1_0__JumpTarget1_1
770
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
771
  // Convert__COP2AsmReg1_0__JumpTarget1_1
772
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
773
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2
774
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
775
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2
776
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
777
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2
778
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
779
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2
780
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
781
  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2
782
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
783
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2
784
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
785
  // Convert__Reg1_0__JumpTarget1_1
786
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
787
  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1
788
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },
789
  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1
790
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
791
  // Convert__GPR32AsmReg1_0__JumpTarget1_1
792
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
793
  // Convert__GPR64AsmReg1_0__JumpTarget1_1
794
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
795
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2
796
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },
797
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2
798
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
799
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2
800
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
801
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2
802
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
803
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2
804
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
805
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2
806
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
807
  // Convert__MSA128AsmReg1_0__JumpTarget1_1
808
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
809
  // Convert__imm_95_0__imm_95_0
810
  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },
811
  // Convert_NoOperands
812
  { CVT_Done },
813
  // Convert__ConstantUImm10_01_0__imm_95_0
814
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },
815
  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1
816
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
817
  // Convert__ConstantUImm4_01_0
818
  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },
819
  // Convert__SImm161_0
820
  { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done },
821
  // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1
822
  { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
823
  // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1
824
  { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
825
  // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2
826
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },
827
  // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
828
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
829
  // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1
830
  { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
831
  // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
832
  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
833
  // Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0
834
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
835
  // Convert__Mem2_1__ConstantUImm5_01_0
836
  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
837
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1
838
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
839
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1
840
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
841
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1
842
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
843
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2
844
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
845
  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1
846
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },
847
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1
848
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done },
849
  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1
850
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },
851
  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1
852
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
853
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2
854
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
855
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2
856
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
857
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3
858
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
859
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3
860
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },
861
  // Convert__Reg1_0__Reg1_1
862
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
863
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2
864
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
865
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
866
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
867
  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
868
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
869
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
870
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
871
  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
872
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
873
  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0
874
  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
875
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0
876
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
877
  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1
878
  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
879
  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0
880
  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
881
  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1
882
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },
883
  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2
884
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
885
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1
886
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done },
887
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2
888
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
889
  // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2
890
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done },
891
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3
892
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
893
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2
894
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },
895
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1
896
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
897
  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2
898
  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
899
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3
900
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },
901
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3
902
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
903
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3
904
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
905
  // Convert__regZERO
906
  { CVT_regZERO, 0, CVT_Done },
907
  // Convert__GPR32AsmReg1_0
908
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
909
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1
910
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done },
911
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1
912
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
913
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1
914
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
915
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1
916
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
917
  // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1
918
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
919
  // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1
920
  { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
921
  // Convert__Reg1_1__Reg1_2
922
  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
923
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2
924
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
925
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2
926
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
927
  // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
928
  { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
929
  // Convert__GPR64AsmReg1_0__Imm1_1
930
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
931
  // Convert__GPR64AsmReg1_0__Mem2_1
932
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
933
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3
934
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
935
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0
936
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
937
  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
938
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
939
  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1
940
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
941
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0
942
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
943
  // Convert__GPR64AsmReg1_0__UImm161_1
944
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
945
  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
946
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
947
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0
948
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
949
  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
950
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
951
  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0
952
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
953
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0
954
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
955
  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2
956
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
957
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2
958
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done },
959
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0
960
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
961
  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1
962
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
963
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
964
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
965
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0
966
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
967
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1
968
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done },
969
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1
970
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },
971
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2
972
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },
973
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1
974
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
975
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2
976
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
977
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2
978
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
979
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1
980
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
981
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1
982
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
983
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2
984
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
985
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3
986
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },
987
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2
988
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
989
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2
990
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
991
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1
992
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },
993
  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1
994
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
995
  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1
996
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },
997
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2
998
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
999
  // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1
1000
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done },
1001
  // Convert__imm_95_0
1002
  { CVT_imm_95_0, 0, CVT_Done },
1003
  // Convert__ConstantUImm10_01_0
1004
  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },
1005
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1
1006
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done },
1007
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2
1008
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1009
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2
1010
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done },
1011
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2
1012
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1013
  // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2
1014
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done },
1015
  // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1
1016
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1017
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1018
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1019
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1020
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1021
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1022
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1023
  // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6
1024
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },
1025
  // Convert__regRA__GPR32AsmReg1_0
1026
  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1027
  // Convert__regRA_64__GPR64AsmReg1_0
1028
  { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1029
  // Convert__Reg1_0
1030
  { CVT_95_Reg, 1, CVT_Done },
1031
  // Convert__GPR32AsmReg1_0__imm_95_0
1032
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1033
  // Convert__GPR64AsmReg1_0__imm_95_0
1034
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1035
  // Convert__regZERO__GPR32AsmReg1_0
1036
  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1037
  // Convert__GPR64AsmReg1_0
1038
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1039
  // Convert__regZERO_64__GPR64AsmReg1_0
1040
  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },
1041
  // Convert__UImm5Lsl21_0
1042
  { CVT_95_addImmOperands, 1, CVT_Done },
1043
  // Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1
1044
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1045
  // Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1
1046
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1047
  // Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1
1048
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1049
  // Convert__GPR32AsmReg1_0__Imm1_1
1050
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1051
  // Convert__GPR32AsmReg1_0__Mem2_1
1052
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1053
  // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1
1054
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1055
  // Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1
1056
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1057
  // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1
1058
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1059
  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1
1060
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1061
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1062
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1063
  // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1
1064
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1065
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1
1066
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1067
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1
1068
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1069
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1
1070
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1071
  // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1
1072
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1073
  // Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1
1074
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1075
  // Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1
1076
  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1077
  // Convert__COP3AsmReg1_0__Mem2_1
1078
  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1079
  // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1
1080
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1081
  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1
1082
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1083
  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1084
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1085
  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1086
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1087
  // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1
1088
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1089
  // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1
1090
  { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1091
  // Convert__StrictlyFGR64AsmReg1_0__Imm1_1
1092
  { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1093
  // Convert__StrictlyFGR32AsmReg1_0__Imm1_1
1094
  { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1095
  // Convert__GPRMM16AsmReg1_0__UImm7_N11_1
1096
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done },
1097
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3
1098
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1099
  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3
1100
  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },
1101
  // Convert__GPR32AsmReg1_0__UImm161_1
1102
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1103
  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1
1104
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },
1105
  // Convert__Reg1_0__Imm1_1__imm_95_0
1106
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1107
  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1
1108
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1109
  // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1
1110
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1111
  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1
1112
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1113
  // Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1
1114
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1115
  // Convert__RegList1_0__Mem2_1
1116
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1117
  // Convert__RegList161_0__MemOffsetUimm42_1
1118
  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1119
  // ConvertCustom_ConvertXWPOperands
1120
  { CVT_ConvertXWPOperands, 0, CVT_Done },
1121
  // Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1
1122
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },
1123
  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1
1124
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1125
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3
1126
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },
1127
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3
1128
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },
1129
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3
1130
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },
1131
  // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2
1132
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },
1133
  // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2
1134
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },
1135
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0
1136
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1137
  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2
1138
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1139
  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1
1140
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },
1141
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0
1142
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1143
  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2
1144
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1145
  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1
1146
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },
1147
  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1
1148
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },
1149
  // Convert__GPR32AsmReg1_0__regAC0
1150
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done },
1151
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0
1152
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1153
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1154
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1155
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO
1156
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },
1157
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64
1158
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },
1159
  // Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3
1160
  { CVT_95_addGPRMM16AsmRegMovePPairFirstOperands, 1, CVT_95_addGPRMM16AsmRegMovePPairSecondOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_95_addGPRMM16AsmRegMovePOperands, 4, CVT_Done },
1161
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1162
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1163
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1164
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1165
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1166
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1167
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1
1168
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1169
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1170
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1171
  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1172
  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1173
  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1174
  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1175
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1
1176
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done },
1177
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1178
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1179
  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1180
  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1181
  // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0
1182
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1183
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0
1184
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1185
  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2
1186
  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1187
  // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1188
  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1189
  // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0
1190
  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1191
  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0
1192
  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1193
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1
1194
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1195
  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0
1196
  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1197
  // Convert__regAC0__GPR32AsmReg1_0
1198
  { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1199
  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0
1200
  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1201
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0
1202
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1203
  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4
1204
  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done },
1205
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2
1206
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1207
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0
1208
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1209
  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1
1210
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1211
  // Convert__regZERO__regZERO__imm_95_0
1212
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },
1213
  // Convert__regZERO__regS0
1214
  { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done },
1215
  // Convert__regZERO__regZERO
1216
  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },
1217
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO
1218
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done },
1219
  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1
1220
  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },
1221
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0
1222
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1223
  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0
1224
  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1225
  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1
1226
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },
1227
  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1
1228
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1229
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1230
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1231
  // Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0
1232
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1233
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2
1234
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1235
  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2
1236
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },
1237
  // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1
1238
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1239
  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1
1240
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },
1241
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1
1242
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },
1243
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2
1244
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1245
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_2
1246
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },
1247
  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1
1248
  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },
1249
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1
1250
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1251
  // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1
1252
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1253
  // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1
1254
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1255
  // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1
1256
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1257
  // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1
1258
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done },
1259
  // Convert__ConstantUImm20_01_0
1260
  { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done },
1261
  // Convert__Reg1_0__Tie0_1_1
1262
  { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done },
1263
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1
1264
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },
1265
  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2
1266
  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1267
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1
1268
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done },
1269
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2
1270
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_32_GT_, 3, CVT_Done },
1271
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0
1272
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },
1273
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1
1274
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },
1275
  // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1
1276
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1277
  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1
1278
  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done },
1279
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2
1280
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },
1281
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2
1282
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },
1283
  // Convert__UImm161_0
1284
  { CVT_95_addUImmOperands_LT_16_GT_, 1, CVT_Done },
1285
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3
1286
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1287
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3
1288
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1289
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3
1290
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1291
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3
1292
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1293
  // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3
1294
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1295
  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2
1296
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },
1297
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3
1298
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },
1299
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3
1300
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },
1301
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3
1302
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },
1303
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3
1304
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },
1305
  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3
1306
  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },
1307
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1
1308
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },
1309
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2
1310
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },
1311
  // Convert__ConstantUImm5_01_0
1312
  { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },
1313
  // Convert__MemOffsetSimm16_02_0
1314
  { CVT_95_addMemOperands, 1, CVT_Done },
1315
  // Convert__imm_95_2
1316
  { CVT_imm_95_2, 0, CVT_Done },
1317
  // Convert__imm_95_6
1318
  { CVT_imm_95_6, 0, CVT_Done },
1319
  // Convert__imm_95_4
1320
  { CVT_imm_95_4, 0, CVT_Done },
1321
  // Convert__imm_95_5
1322
  { CVT_imm_95_5, 0, CVT_Done },
1323
  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2
1324
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },
1325
  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2
1326
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1327
  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2
1328
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1329
  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2
1330
  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },
1331
  // Convert__GPR32AsmReg1_0__imm_95_31
1332
  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },
1333
};
1334
1335
void MipsAsmParser::
1336
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1337
0
                const OperandVector &Operands) {
1338
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1339
0
  const uint8_t *Converter = ConversionTable[Kind];
1340
0
  unsigned OpIdx;
1341
0
  Inst.setOpcode(Opcode);
1342
0
  for (const uint8_t *p = Converter; *p; p += 2) {
1343
0
    OpIdx = *(p + 1);
1344
0
    switch (*p) {
1345
0
    default: llvm_unreachable("invalid conversion entry!");
1346
0
    case CVT_Reg:
1347
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1348
0
      break;
1349
0
    case CVT_Tied: {
1350
0
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
1351
0
                              std::begin(TiedAsmOperandTable)) &&
1352
0
             "Tied operand not found");
1353
0
      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];
1354
0
      if (TiedResOpnd != (uint8_t)-1)
1355
0
        Inst.addOperand(Inst.getOperand(TiedResOpnd));
1356
0
      break;
1357
0
    }
1358
0
    case CVT_95_addGPR32AsmRegOperands:
1359
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1);
1360
0
      break;
1361
0
    case CVT_95_addAFGR64AsmRegOperands:
1362
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1);
1363
0
      break;
1364
0
    case CVT_95_addFGR64AsmRegOperands:
1365
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1);
1366
0
      break;
1367
0
    case CVT_95_addFGR32AsmRegOperands:
1368
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1);
1369
0
      break;
1370
0
    case CVT_95_addSImmOperands_LT_32_GT_:
1371
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1);
1372
0
      break;
1373
0
    case CVT_95_addMSA128AsmRegOperands:
1374
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1);
1375
0
      break;
1376
0
    case CVT_95_addSImmOperands_LT_16_GT_:
1377
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1);
1378
0
      break;
1379
0
    case CVT_95_Reg:
1380
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1);
1381
0
      break;
1382
0
    case CVT_95_addImmOperands:
1383
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1);
1384
0
      break;
1385
0
    case CVT_95_addGPRMM16AsmRegOperands:
1386
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1);
1387
0
      break;
1388
0
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1389
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1);
1390
0
      break;
1391
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1392
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1);
1393
0
      break;
1394
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1395
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1);
1396
0
      break;
1397
0
    case CVT_95_addUImmOperands_LT_16_GT_:
1398
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1);
1399
0
      break;
1400
0
    case CVT_95_addGPR64AsmRegOperands:
1401
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1);
1402
0
      break;
1403
0
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1404
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1);
1405
0
      break;
1406
0
    case CVT_regZERO:
1407
0
      Inst.addOperand(MCOperand::createReg(Mips::ZERO));
1408
0
      break;
1409
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1410
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1);
1411
0
      break;
1412
0
    case CVT_regFCC0:
1413
0
      Inst.addOperand(MCOperand::createReg(Mips::FCC0));
1414
0
      break;
1415
0
    case CVT_95_addFCCAsmRegOperands:
1416
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1);
1417
0
      break;
1418
0
    case CVT_95_addCOP2AsmRegOperands:
1419
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1);
1420
0
      break;
1421
0
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1422
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1);
1423
0
      break;
1424
0
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1425
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1);
1426
0
      break;
1427
0
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1428
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1);
1429
0
      break;
1430
0
    case CVT_imm_95_0:
1431
0
      Inst.addOperand(MCOperand::createImm(0));
1432
0
      break;
1433
0
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1434
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1);
1435
0
      break;
1436
0
    case CVT_95_addMemOperands:
1437
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addMemOperands(Inst, 2);
1438
0
      break;
1439
0
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1440
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1);
1441
0
      break;
1442
0
    case CVT_95_addCCRAsmRegOperands:
1443
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1);
1444
0
      break;
1445
0
    case CVT_95_addMSACtrlAsmRegOperands:
1446
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1);
1447
0
      break;
1448
0
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1449
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1);
1450
0
      break;
1451
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1452
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1);
1453
0
      break;
1454
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1455
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1);
1456
0
      break;
1457
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1458
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1);
1459
0
      break;
1460
0
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1461
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1);
1462
0
      break;
1463
0
    case CVT_95_addGPR32ZeroAsmRegOperands:
1464
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1);
1465
0
      break;
1466
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1467
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1);
1468
0
      break;
1469
0
    case CVT_95_addCOP0AsmRegOperands:
1470
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1);
1471
0
      break;
1472
0
    case CVT_regZERO_64:
1473
0
      Inst.addOperand(MCOperand::createReg(Mips::ZERO_64));
1474
0
      break;
1475
0
    case CVT_95_addACC64DSPAsmRegOperands:
1476
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1);
1477
0
      break;
1478
0
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1479
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1);
1480
0
      break;
1481
0
    case CVT_regRA:
1482
0
      Inst.addOperand(MCOperand::createReg(Mips::RA));
1483
0
      break;
1484
0
    case CVT_regRA_64:
1485
0
      Inst.addOperand(MCOperand::createReg(Mips::RA_64));
1486
0
      break;
1487
0
    case CVT_95_addMicroMipsMemOperands:
1488
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2);
1489
0
      break;
1490
0
    case CVT_95_addCOP3AsmRegOperands:
1491
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1);
1492
0
      break;
1493
0
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1494
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1);
1495
0
      break;
1496
0
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1497
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1);
1498
0
      break;
1499
0
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1500
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1);
1501
0
      break;
1502
0
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1503
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1);
1504
0
      break;
1505
0
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1506
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1);
1507
0
      break;
1508
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1509
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1);
1510
0
      break;
1511
0
    case CVT_95_addRegListOperands:
1512
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addRegListOperands(Inst, 1);
1513
0
      break;
1514
0
    case CVT_ConvertXWPOperands:
1515
0
      ConvertXWPOperands(Inst, Operands);
1516
0
      break;
1517
0
    case CVT_regAC0:
1518
0
      Inst.addOperand(MCOperand::createReg(Mips::AC0));
1519
0
      break;
1520
0
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1521
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairFirstOperands(Inst, 1);
1522
0
      break;
1523
0
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1524
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePPairSecondOperands(Inst, 1);
1525
0
      break;
1526
0
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1527
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1);
1528
0
      break;
1529
0
    case CVT_95_addHI32DSPAsmRegOperands:
1530
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1);
1531
0
      break;
1532
0
    case CVT_95_addLO32DSPAsmRegOperands:
1533
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1);
1534
0
      break;
1535
0
    case CVT_regS0:
1536
0
      Inst.addOperand(MCOperand::createReg(Mips::S0));
1537
0
      break;
1538
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1539
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1);
1540
0
      break;
1541
0
    case CVT_95_addHWRegsAsmRegOperands:
1542
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1);
1543
0
      break;
1544
0
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1545
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1);
1546
0
      break;
1547
0
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1548
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1);
1549
0
      break;
1550
0
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1551
0
      static_cast<MipsOperand &>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1);
1552
0
      break;
1553
0
    case CVT_imm_95_2:
1554
0
      Inst.addOperand(MCOperand::createImm(2));
1555
0
      break;
1556
0
    case CVT_imm_95_6:
1557
0
      Inst.addOperand(MCOperand::createImm(6));
1558
0
      break;
1559
0
    case CVT_imm_95_4:
1560
0
      Inst.addOperand(MCOperand::createImm(4));
1561
0
      break;
1562
0
    case CVT_imm_95_5:
1563
0
      Inst.addOperand(MCOperand::createImm(5));
1564
0
      break;
1565
0
    case CVT_imm_95_31:
1566
0
      Inst.addOperand(MCOperand::createImm(31));
1567
0
      break;
1568
0
    }
1569
0
  }
1570
0
}
1571
1572
void MipsAsmParser::
1573
convertToMapAndConstraints(unsigned Kind,
1574
0
                           const OperandVector &Operands) {
1575
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1576
0
  unsigned NumMCOperands = 0;
1577
0
  const uint8_t *Converter = ConversionTable[Kind];
1578
0
  for (const uint8_t *p = Converter; *p; p += 2) {
1579
0
    switch (*p) {
1580
0
    default: llvm_unreachable("invalid conversion entry!");
1581
0
    case CVT_Reg:
1582
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1583
0
      Operands[*(p + 1)]->setConstraint("r");
1584
0
      ++NumMCOperands;
1585
0
      break;
1586
0
    case CVT_Tied:
1587
0
      ++NumMCOperands;
1588
0
      break;
1589
0
    case CVT_95_addGPR32AsmRegOperands:
1590
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1591
0
      Operands[*(p + 1)]->setConstraint("m");
1592
0
      NumMCOperands += 1;
1593
0
      break;
1594
0
    case CVT_95_addAFGR64AsmRegOperands:
1595
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1596
0
      Operands[*(p + 1)]->setConstraint("m");
1597
0
      NumMCOperands += 1;
1598
0
      break;
1599
0
    case CVT_95_addFGR64AsmRegOperands:
1600
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1601
0
      Operands[*(p + 1)]->setConstraint("m");
1602
0
      NumMCOperands += 1;
1603
0
      break;
1604
0
    case CVT_95_addFGR32AsmRegOperands:
1605
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1606
0
      Operands[*(p + 1)]->setConstraint("m");
1607
0
      NumMCOperands += 1;
1608
0
      break;
1609
0
    case CVT_95_addSImmOperands_LT_32_GT_:
1610
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1611
0
      Operands[*(p + 1)]->setConstraint("m");
1612
0
      NumMCOperands += 1;
1613
0
      break;
1614
0
    case CVT_95_addMSA128AsmRegOperands:
1615
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1616
0
      Operands[*(p + 1)]->setConstraint("m");
1617
0
      NumMCOperands += 1;
1618
0
      break;
1619
0
    case CVT_95_addSImmOperands_LT_16_GT_:
1620
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1621
0
      Operands[*(p + 1)]->setConstraint("m");
1622
0
      NumMCOperands += 1;
1623
0
      break;
1624
0
    case CVT_95_Reg:
1625
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1626
0
      Operands[*(p + 1)]->setConstraint("r");
1627
0
      NumMCOperands += 1;
1628
0
      break;
1629
0
    case CVT_95_addImmOperands:
1630
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1631
0
      Operands[*(p + 1)]->setConstraint("m");
1632
0
      NumMCOperands += 1;
1633
0
      break;
1634
0
    case CVT_95_addGPRMM16AsmRegOperands:
1635
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1636
0
      Operands[*(p + 1)]->setConstraint("m");
1637
0
      NumMCOperands += 1;
1638
0
      break;
1639
0
    case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_:
1640
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1641
0
      Operands[*(p + 1)]->setConstraint("m");
1642
0
      NumMCOperands += 1;
1643
0
      break;
1644
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:
1645
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1646
0
      Operands[*(p + 1)]->setConstraint("m");
1647
0
      NumMCOperands += 1;
1648
0
      break;
1649
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:
1650
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1651
0
      Operands[*(p + 1)]->setConstraint("m");
1652
0
      NumMCOperands += 1;
1653
0
      break;
1654
0
    case CVT_95_addUImmOperands_LT_16_GT_:
1655
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1656
0
      Operands[*(p + 1)]->setConstraint("m");
1657
0
      NumMCOperands += 1;
1658
0
      break;
1659
0
    case CVT_95_addGPR64AsmRegOperands:
1660
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1661
0
      Operands[*(p + 1)]->setConstraint("m");
1662
0
      NumMCOperands += 1;
1663
0
      break;
1664
0
    case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_:
1665
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1666
0
      Operands[*(p + 1)]->setConstraint("m");
1667
0
      NumMCOperands += 1;
1668
0
      break;
1669
0
    case CVT_regZERO:
1670
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1671
0
      Operands[*(p + 1)]->setConstraint("m");
1672
0
      ++NumMCOperands;
1673
0
      break;
1674
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:
1675
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1676
0
      Operands[*(p + 1)]->setConstraint("m");
1677
0
      NumMCOperands += 1;
1678
0
      break;
1679
0
    case CVT_regFCC0:
1680
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1681
0
      Operands[*(p + 1)]->setConstraint("m");
1682
0
      ++NumMCOperands;
1683
0
      break;
1684
0
    case CVT_95_addFCCAsmRegOperands:
1685
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1686
0
      Operands[*(p + 1)]->setConstraint("m");
1687
0
      NumMCOperands += 1;
1688
0
      break;
1689
0
    case CVT_95_addCOP2AsmRegOperands:
1690
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1691
0
      Operands[*(p + 1)]->setConstraint("m");
1692
0
      NumMCOperands += 1;
1693
0
      break;
1694
0
    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:
1695
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1696
0
      Operands[*(p + 1)]->setConstraint("m");
1697
0
      NumMCOperands += 1;
1698
0
      break;
1699
0
    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:
1700
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1701
0
      Operands[*(p + 1)]->setConstraint("m");
1702
0
      NumMCOperands += 1;
1703
0
      break;
1704
0
    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:
1705
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1706
0
      Operands[*(p + 1)]->setConstraint("m");
1707
0
      NumMCOperands += 1;
1708
0
      break;
1709
0
    case CVT_imm_95_0:
1710
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1711
0
      Operands[*(p + 1)]->setConstraint("");
1712
0
      ++NumMCOperands;
1713
0
      break;
1714
0
    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:
1715
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1716
0
      Operands[*(p + 1)]->setConstraint("m");
1717
0
      NumMCOperands += 1;
1718
0
      break;
1719
0
    case CVT_95_addMemOperands:
1720
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1721
0
      Operands[*(p + 1)]->setConstraint("m");
1722
0
      NumMCOperands += 2;
1723
0
      break;
1724
0
    case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_:
1725
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1726
0
      Operands[*(p + 1)]->setConstraint("m");
1727
0
      NumMCOperands += 1;
1728
0
      break;
1729
0
    case CVT_95_addCCRAsmRegOperands:
1730
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1731
0
      Operands[*(p + 1)]->setConstraint("m");
1732
0
      NumMCOperands += 1;
1733
0
      break;
1734
0
    case CVT_95_addMSACtrlAsmRegOperands:
1735
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1736
0
      Operands[*(p + 1)]->setConstraint("m");
1737
0
      NumMCOperands += 1;
1738
0
      break;
1739
0
    case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_:
1740
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1741
0
      Operands[*(p + 1)]->setConstraint("m");
1742
0
      NumMCOperands += 1;
1743
0
      break;
1744
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:
1745
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1746
0
      Operands[*(p + 1)]->setConstraint("m");
1747
0
      NumMCOperands += 1;
1748
0
      break;
1749
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:
1750
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1751
0
      Operands[*(p + 1)]->setConstraint("m");
1752
0
      NumMCOperands += 1;
1753
0
      break;
1754
0
    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:
1755
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1756
0
      Operands[*(p + 1)]->setConstraint("m");
1757
0
      NumMCOperands += 1;
1758
0
      break;
1759
0
    case CVT_95_addGPR32NonZeroAsmRegOperands:
1760
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1761
0
      Operands[*(p + 1)]->setConstraint("m");
1762
0
      NumMCOperands += 1;
1763
0
      break;
1764
0
    case CVT_95_addGPR32ZeroAsmRegOperands:
1765
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1766
0
      Operands[*(p + 1)]->setConstraint("m");
1767
0
      NumMCOperands += 1;
1768
0
      break;
1769
0
    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:
1770
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1771
0
      Operands[*(p + 1)]->setConstraint("m");
1772
0
      NumMCOperands += 1;
1773
0
      break;
1774
0
    case CVT_95_addCOP0AsmRegOperands:
1775
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1776
0
      Operands[*(p + 1)]->setConstraint("m");
1777
0
      NumMCOperands += 1;
1778
0
      break;
1779
0
    case CVT_regZERO_64:
1780
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1781
0
      Operands[*(p + 1)]->setConstraint("m");
1782
0
      ++NumMCOperands;
1783
0
      break;
1784
0
    case CVT_95_addACC64DSPAsmRegOperands:
1785
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1786
0
      Operands[*(p + 1)]->setConstraint("m");
1787
0
      NumMCOperands += 1;
1788
0
      break;
1789
0
    case CVT_95_addConstantUImmOperands_LT_1_GT_:
1790
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1791
0
      Operands[*(p + 1)]->setConstraint("m");
1792
0
      NumMCOperands += 1;
1793
0
      break;
1794
0
    case CVT_regRA:
1795
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1796
0
      Operands[*(p + 1)]->setConstraint("m");
1797
0
      ++NumMCOperands;
1798
0
      break;
1799
0
    case CVT_regRA_64:
1800
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1801
0
      Operands[*(p + 1)]->setConstraint("m");
1802
0
      ++NumMCOperands;
1803
0
      break;
1804
0
    case CVT_95_addMicroMipsMemOperands:
1805
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1806
0
      Operands[*(p + 1)]->setConstraint("m");
1807
0
      NumMCOperands += 2;
1808
0
      break;
1809
0
    case CVT_95_addCOP3AsmRegOperands:
1810
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1811
0
      Operands[*(p + 1)]->setConstraint("m");
1812
0
      NumMCOperands += 1;
1813
0
      break;
1814
0
    case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_:
1815
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1816
0
      Operands[*(p + 1)]->setConstraint("m");
1817
0
      NumMCOperands += 1;
1818
0
      break;
1819
0
    case CVT_95_addConstantUImmOperands_LT_32_GT_:
1820
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1821
0
      Operands[*(p + 1)]->setConstraint("m");
1822
0
      NumMCOperands += 1;
1823
0
      break;
1824
0
    case CVT_95_addStrictlyAFGR64AsmRegOperands:
1825
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1826
0
      Operands[*(p + 1)]->setConstraint("m");
1827
0
      NumMCOperands += 1;
1828
0
      break;
1829
0
    case CVT_95_addStrictlyFGR64AsmRegOperands:
1830
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1831
0
      Operands[*(p + 1)]->setConstraint("m");
1832
0
      NumMCOperands += 1;
1833
0
      break;
1834
0
    case CVT_95_addStrictlyFGR32AsmRegOperands:
1835
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1836
0
      Operands[*(p + 1)]->setConstraint("m");
1837
0
      NumMCOperands += 1;
1838
0
      break;
1839
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_:
1840
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1841
0
      Operands[*(p + 1)]->setConstraint("m");
1842
0
      NumMCOperands += 1;
1843
0
      break;
1844
0
    case CVT_95_addRegListOperands:
1845
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1846
0
      Operands[*(p + 1)]->setConstraint("m");
1847
0
      NumMCOperands += 1;
1848
0
      break;
1849
0
    case CVT_regAC0:
1850
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1851
0
      Operands[*(p + 1)]->setConstraint("m");
1852
0
      ++NumMCOperands;
1853
0
      break;
1854
0
    case CVT_95_addGPRMM16AsmRegMovePPairFirstOperands:
1855
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1856
0
      Operands[*(p + 1)]->setConstraint("m");
1857
0
      NumMCOperands += 1;
1858
0
      break;
1859
0
    case CVT_95_addGPRMM16AsmRegMovePPairSecondOperands:
1860
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1861
0
      Operands[*(p + 1)]->setConstraint("m");
1862
0
      NumMCOperands += 1;
1863
0
      break;
1864
0
    case CVT_95_addGPRMM16AsmRegMovePOperands:
1865
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1866
0
      Operands[*(p + 1)]->setConstraint("m");
1867
0
      NumMCOperands += 1;
1868
0
      break;
1869
0
    case CVT_95_addHI32DSPAsmRegOperands:
1870
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1871
0
      Operands[*(p + 1)]->setConstraint("m");
1872
0
      NumMCOperands += 1;
1873
0
      break;
1874
0
    case CVT_95_addLO32DSPAsmRegOperands:
1875
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1876
0
      Operands[*(p + 1)]->setConstraint("m");
1877
0
      NumMCOperands += 1;
1878
0
      break;
1879
0
    case CVT_regS0:
1880
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1881
0
      Operands[*(p + 1)]->setConstraint("m");
1882
0
      ++NumMCOperands;
1883
0
      break;
1884
0
    case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_:
1885
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1886
0
      Operands[*(p + 1)]->setConstraint("m");
1887
0
      NumMCOperands += 1;
1888
0
      break;
1889
0
    case CVT_95_addHWRegsAsmRegOperands:
1890
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1891
0
      Operands[*(p + 1)]->setConstraint("m");
1892
0
      NumMCOperands += 1;
1893
0
      break;
1894
0
    case CVT_95_addGPRMM16AsmRegZeroOperands:
1895
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1896
0
      Operands[*(p + 1)]->setConstraint("m");
1897
0
      NumMCOperands += 1;
1898
0
      break;
1899
0
    case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_:
1900
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1901
0
      Operands[*(p + 1)]->setConstraint("m");
1902
0
      NumMCOperands += 1;
1903
0
      break;
1904
0
    case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_:
1905
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1906
0
      Operands[*(p + 1)]->setConstraint("m");
1907
0
      NumMCOperands += 1;
1908
0
      break;
1909
0
    case CVT_imm_95_2:
1910
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1911
0
      Operands[*(p + 1)]->setConstraint("");
1912
0
      ++NumMCOperands;
1913
0
      break;
1914
0
    case CVT_imm_95_6:
1915
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1916
0
      Operands[*(p + 1)]->setConstraint("");
1917
0
      ++NumMCOperands;
1918
0
      break;
1919
0
    case CVT_imm_95_4:
1920
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1921
0
      Operands[*(p + 1)]->setConstraint("");
1922
0
      ++NumMCOperands;
1923
0
      break;
1924
0
    case CVT_imm_95_5:
1925
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1926
0
      Operands[*(p + 1)]->setConstraint("");
1927
0
      ++NumMCOperands;
1928
0
      break;
1929
0
    case CVT_imm_95_31:
1930
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1931
0
      Operands[*(p + 1)]->setConstraint("");
1932
0
      ++NumMCOperands;
1933
0
      break;
1934
0
    }
1935
0
  }
1936
0
}
1937
1938
namespace {
1939
1940
/// MatchClassKind - The kinds of classes which participate in
1941
/// instruction matching.
1942
enum MatchClassKind {
1943
  InvalidMatchClass = 0,
1944
  OptionalMatchClass = 1,
1945
  MCK__HASH_, // '#'
1946
  MCK__40_, // '('
1947
  MCK__41_, // ')'
1948
  MCK_0, // '0'
1949
  MCK_16, // '16'
1950
  MCK__91_, // '['
1951
  MCK__93_, // ']'
1952
  MCK_bit, // 'bit'
1953
  MCK_inst, // 'inst'
1954
  MCK_LAST_TOKEN = MCK_inst,
1955
  MCK_Reg37, // derived register class
1956
  MCK_Reg19, // derived register class
1957
  MCK_ACC128, // register class 'ACC128'
1958
  MCK_ACC64, // register class 'ACC64'
1959
  MCK_CPURAReg, // register class 'CPURAReg,RA'
1960
  MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP'
1961
  MCK_DSPCC, // register class 'DSPCC'
1962
  MCK_GP32, // register class 'GP32'
1963
  MCK_GP64, // register class 'GP64'
1964
  MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO'
1965
  MCK_HI32, // register class 'HI32'
1966
  MCK_HI64, // register class 'HI64'
1967
  MCK_LO32, // register class 'LO32'
1968
  MCK_LO64, // register class 'LO64'
1969
  MCK_PC, // register class 'PC'
1970
  MCK_SP64, // register class 'SP64'
1971
  MCK_Reg32, // derived register class
1972
  MCK_Reg13, // derived register class
1973
  MCK_Reg33, // derived register class
1974
  MCK_Reg31, // derived register class
1975
  MCK_Reg30, // derived register class
1976
  MCK_Reg14, // derived register class
1977
  MCK_Reg11, // derived register class
1978
  MCK_GPRMM16MovePPairFirst, // register class 'GPRMM16MovePPairFirst'
1979
  MCK_OCTEON_MPL, // register class 'OCTEON_MPL'
1980
  MCK_OCTEON_P, // register class 'OCTEON_P'
1981
  MCK_Reg28, // derived register class
1982
  MCK_Reg23, // derived register class
1983
  MCK_Reg9, // derived register class
1984
  MCK_Reg4, // derived register class
1985
  MCK_ACC64DSP, // register class 'ACC64DSP'
1986
  MCK_HI32DSP, // register class 'HI32DSP'
1987
  MCK_LO32DSP, // register class 'LO32DSP'
1988
  MCK_Reg34, // derived register class
1989
  MCK_GPRMM16MovePPairSecond, // register class 'GPRMM16MovePPairSecond'
1990
  MCK_Reg29, // derived register class
1991
  MCK_Reg27, // derived register class
1992
  MCK_Reg10, // derived register class
1993
  MCK_Reg8, // derived register class
1994
  MCK_Reg25, // derived register class
1995
  MCK_Reg22, // derived register class
1996
  MCK_Reg21, // derived register class
1997
  MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16'
1998
  MCK_FCC, // register class 'FCC'
1999
  MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP'
2000
  MCK_GPRMM16Zero, // register class 'GPRMM16Zero'
2001
  MCK_Reg26, // derived register class
2002
  MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP'
2003
  MCK_AFGR64, // register class 'AFGR64'
2004
  MCK_MSA128WEvens, // register class 'MSA128WEvens'
2005
  MCK_Reg24, // derived register class
2006
  MCK_GPR32NONZERO, // register class 'GPR32NONZERO'
2007
  MCK_CCR, // register class 'CCR'
2008
  MCK_COP0, // register class 'COP0'
2009
  MCK_COP2, // register class 'COP2'
2010
  MCK_COP3, // register class 'COP3'
2011
  MCK_DSPR, // register class 'DSPR,GPR32'
2012
  MCK_FGR32, // register class 'FGR32,FGRCC'
2013
  MCK_FGR64, // register class 'FGR64'
2014
  MCK_GPR64, // register class 'GPR64'
2015
  MCK_HWRegs, // register class 'HWRegs'
2016
  MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W'
2017
  MCK_MSACtrl, // register class 'MSACtrl'
2018
  MCK_LAST_REGISTER = MCK_MSACtrl,
2019
  MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand'
2020
  MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand'
2021
  MCK_CCRAsmReg, // user defined class 'CCRAsmOperand'
2022
  MCK_COP0AsmReg, // user defined class 'COP0AsmOperand'
2023
  MCK_COP2AsmReg, // user defined class 'COP2AsmOperand'
2024
  MCK_COP3AsmReg, // user defined class 'COP3AsmOperand'
2025
  MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand'
2026
  MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand'
2027
  MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand'
2028
  MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand'
2029
  MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand'
2030
  MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand'
2031
  MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand'
2032
  MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand'
2033
  MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP'
2034
  MCK_GPRMM16AsmRegMovePPairFirst, // user defined class 'GPRMM16AsmOperandMovePPairFirst'
2035
  MCK_GPRMM16AsmRegMovePPairSecond, // user defined class 'GPRMM16AsmOperandMovePPairSecond'
2036
  MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero'
2037
  MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand'
2038
  MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand'
2039
  MCK_Imm, // user defined class 'ImmAsmOperand'
2040
  MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand'
2041
  MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand'
2042
  MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand'
2043
  MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand'
2044
  MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand'
2045
  MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand'
2046
  MCK_InvNum, // user defined class 'MipsInvertedImmoperand'
2047
  MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand'
2048
  MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand'
2049
  MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand'
2050
  MCK_MemOffsetSimm9_0, // user defined class 'anonymous_7497'
2051
  MCK_MemOffsetSimm10_0, // user defined class 'anonymous_7498'
2052
  MCK_MemOffsetSimm11_0, // user defined class 'anonymous_7499'
2053
  MCK_MemOffsetSimm12_0, // user defined class 'anonymous_7500'
2054
  MCK_MemOffsetSimm16_0, // user defined class 'anonymous_7501'
2055
  MCK_MemOffsetSimm10_1, // user defined class 'anonymous_7502'
2056
  MCK_MemOffsetSimm10_2, // user defined class 'anonymous_7503'
2057
  MCK_MemOffsetSimm10_3, // user defined class 'anonymous_7504'
2058
  MCK_Mem, // user defined class 'MipsMemAsmOperand'
2059
  MCK_RegList16, // user defined class 'RegList16AsmOperand'
2060
  MCK_RegList, // user defined class 'RegListAsmOperand'
2061
  MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand'
2062
  MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand'
2063
  MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand'
2064
  MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand'
2065
  MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass'
2066
  MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass'
2067
  MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass'
2068
  MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass'
2069
  MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass'
2070
  MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass'
2071
  MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass'
2072
  MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass'
2073
  MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass'
2074
  MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass'
2075
  MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass'
2076
  MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass'
2077
  MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass'
2078
  MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass'
2079
  MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass'
2080
  MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass'
2081
  MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass'
2082
  MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass'
2083
  MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass'
2084
  MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass'
2085
  MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass'
2086
  MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass'
2087
  MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass'
2088
  MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass'
2089
  MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass'
2090
  MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass'
2091
  MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass'
2092
  MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass'
2093
  MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass'
2094
  MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass'
2095
  MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass'
2096
  MCK_SImm16, // user defined class 'SImm16AsmOperandClass'
2097
  MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass'
2098
  MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass'
2099
  MCK_UImm16, // user defined class 'UImm16AsmOperandClass'
2100
  MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass'
2101
  MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass'
2102
  MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass'
2103
  MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass'
2104
  MCK_SImm32, // user defined class 'SImm32AsmOperandClass'
2105
  MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass'
2106
  MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass'
2107
  NumMatchClassKinds
2108
};
2109
2110
} // end anonymous namespace
2111
2112
0
static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) {
2113
0
  return MCTargetAsmParser::Match_InvalidOperand;
2114
0
}
2115
2116
0
static MatchClassKind matchTokenString(StringRef Name) {
2117
0
  switch (Name.size()) {
2118
0
  default: break;
2119
0
  case 1:  // 6 strings to match.
2120
0
    switch (Name[0]) {
2121
0
    default: break;
2122
0
    case '#':  // 1 string to match.
2123
0
      return MCK__HASH_;  // "#"
2124
0
    case '(':  // 1 string to match.
2125
0
      return MCK__40_;  // "("
2126
0
    case ')':  // 1 string to match.
2127
0
      return MCK__41_;  // ")"
2128
0
    case '0':  // 1 string to match.
2129
0
      return MCK_0;  // "0"
2130
0
    case '[':  // 1 string to match.
2131
0
      return MCK__91_;  // "["
2132
0
    case ']':  // 1 string to match.
2133
0
      return MCK__93_;  // "]"
2134
0
    }
2135
0
    break;
2136
0
  case 2:  // 1 string to match.
2137
0
    if (memcmp(Name.data()+0, "16", 2) != 0)
2138
0
      break;
2139
0
    return MCK_16;  // "16"
2140
0
  case 3:  // 1 string to match.
2141
0
    if (memcmp(Name.data()+0, "bit", 3) != 0)
2142
0
      break;
2143
0
    return MCK_bit;  // "bit"
2144
0
  case 4:  // 1 string to match.
2145
0
    if (memcmp(Name.data()+0, "inst", 4) != 0)
2146
0
      break;
2147
0
    return MCK_inst;  // "inst"
2148
0
  }
2149
0
  return InvalidMatchClass;
2150
0
}
2151
2152
/// isSubclass - Compute whether \p A is a subclass of \p B.
2153
0
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
2154
0
  if (A == B)
2155
0
    return true;
2156
2157
0
  switch (A) {
2158
0
  default:
2159
0
    return false;
2160
2161
0
  case MCK_Reg37:
2162
0
    switch (B) {
2163
0
    default: return false;
2164
0
    case MCK_Reg24: return true;
2165
0
    case MCK_GPR64: return true;
2166
0
    }
2167
2168
0
  case MCK_Reg19:
2169
0
    switch (B) {
2170
0
    default: return false;
2171
0
    case MCK_Reg23: return true;
2172
0
    case MCK_Reg22: return true;
2173
0
    case MCK_Reg21: return true;
2174
0
    case MCK_GPR64: return true;
2175
0
    }
2176
2177
0
  case MCK_ACC64:
2178
0
    return B == MCK_ACC64DSP;
2179
2180
0
  case MCK_CPURAReg:
2181
0
    switch (B) {
2182
0
    default: return false;
2183
0
    case MCK_GPR32NONZERO: return true;
2184
0
    case MCK_DSPR: return true;
2185
0
    }
2186
2187
0
  case MCK_CPUSPReg:
2188
0
    switch (B) {
2189
0
    default: return false;
2190
0
    case MCK_CPU16RegsPlusSP: return true;
2191
0
    case MCK_GPR32NONZERO: return true;
2192
0
    case MCK_DSPR: return true;
2193
0
    }
2194
2195
0
  case MCK_GP32:
2196
0
    switch (B) {
2197
0
    default: return false;
2198
0
    case MCK_GPR32NONZERO: return true;
2199
0
    case MCK_DSPR: return true;
2200
0
    }
2201
2202
0
  case MCK_GP64:
2203
0
    switch (B) {
2204
0
    default: return false;
2205
0
    case MCK_Reg24: return true;
2206
0
    case MCK_GPR64: return true;
2207
0
    }
2208
2209
0
  case MCK_GPR32ZERO:
2210
0
    switch (B) {
2211
0
    default: return false;
2212
0
    case MCK_Reg4: return true;
2213
0
    case MCK_GPRMM16MoveP: return true;
2214
0
    case MCK_GPRMM16Zero: return true;
2215
0
    case MCK_DSPR: return true;
2216
0
    }
2217
2218
0
  case MCK_HI32:
2219
0
    return B == MCK_HI32DSP;
2220
2221
0
  case MCK_LO32:
2222
0
    return B == MCK_LO32DSP;
2223
2224
0
  case MCK_SP64:
2225
0
    switch (B) {
2226
0
    default: return false;
2227
0
    case MCK_Reg26: return true;
2228
0
    case MCK_Reg24: return true;
2229
0
    case MCK_GPR64: return true;
2230
0
    }
2231
2232
0
  case MCK_Reg32:
2233
0
    switch (B) {
2234
0
    default: return false;
2235
0
    case MCK_Reg33: return true;
2236
0
    case MCK_Reg31: return true;
2237
0
    case MCK_Reg34: return true;
2238
0
    case MCK_Reg27: return true;
2239
0
    case MCK_Reg25: return true;
2240
0
    case MCK_Reg21: return true;
2241
0
    case MCK_Reg26: return true;
2242
0
    case MCK_Reg24: return true;
2243
0
    case MCK_GPR64: return true;
2244
0
    }
2245
2246
0
  case MCK_Reg13:
2247
0
    switch (B) {
2248
0
    default: return false;
2249
0
    case MCK_Reg14: return true;
2250
0
    case MCK_GPRMM16MovePPairFirst: return true;
2251
0
    case MCK_GPRMM16MovePPairSecond: return true;
2252
0
    case MCK_Reg8: return true;
2253
0
    case MCK_CPU16Regs: return true;
2254
0
    case MCK_GPRMM16Zero: return true;
2255
0
    case MCK_CPU16RegsPlusSP: return true;
2256
0
    case MCK_GPR32NONZERO: return true;
2257
0
    case MCK_DSPR: return true;
2258
0
    }
2259
2260
0
  case MCK_Reg33:
2261
0
    switch (B) {
2262
0
    default: return false;
2263
0
    case MCK_Reg34: return true;
2264
0
    case MCK_Reg27: return true;
2265
0
    case MCK_Reg25: return true;
2266
0
    case MCK_Reg21: return true;
2267
0
    case MCK_Reg26: return true;
2268
0
    case MCK_Reg24: return true;
2269
0
    case MCK_GPR64: return true;
2270
0
    }
2271
2272
0
  case MCK_Reg31:
2273
0
    switch (B) {
2274
0
    default: return false;
2275
0
    case MCK_Reg27: return true;
2276
0
    case MCK_Reg25: return true;
2277
0
    case MCK_Reg21: return true;
2278
0
    case MCK_Reg26: return true;
2279
0
    case MCK_Reg24: return true;
2280
0
    case MCK_GPR64: return true;
2281
0
    }
2282
2283
0
  case MCK_Reg30:
2284
0
    switch (B) {
2285
0
    default: return false;
2286
0
    case MCK_Reg28: return true;
2287
0
    case MCK_Reg23: return true;
2288
0
    case MCK_Reg29: return true;
2289
0
    case MCK_Reg27: return true;
2290
0
    case MCK_Reg25: return true;
2291
0
    case MCK_Reg22: return true;
2292
0
    case MCK_Reg21: return true;
2293
0
    case MCK_Reg26: return true;
2294
0
    case MCK_Reg24: return true;
2295
0
    case MCK_GPR64: return true;
2296
0
    }
2297
2298
0
  case MCK_Reg14:
2299
0
    switch (B) {
2300
0
    default: return false;
2301
0
    case MCK_GPRMM16MovePPairSecond: return true;
2302
0
    case MCK_Reg8: return true;
2303
0
    case MCK_CPU16Regs: return true;
2304
0
    case MCK_GPRMM16Zero: return true;
2305
0
    case MCK_CPU16RegsPlusSP: return true;
2306
0
    case MCK_GPR32NONZERO: return true;
2307
0
    case MCK_DSPR: return true;
2308
0
    }
2309
2310
0
  case MCK_Reg11:
2311
0
    switch (B) {
2312
0
    default: return false;
2313
0
    case MCK_Reg9: return true;
2314
0
    case MCK_Reg4: return true;
2315
0
    case MCK_Reg10: return true;
2316
0
    case MCK_Reg8: return true;
2317
0
    case MCK_CPU16Regs: return true;
2318
0
    case MCK_GPRMM16MoveP: return true;
2319
0
    case MCK_GPRMM16Zero: return true;
2320
0
    case MCK_CPU16RegsPlusSP: return true;
2321
0
    case MCK_GPR32NONZERO: return true;
2322
0
    case MCK_DSPR: return true;
2323
0
    }
2324
2325
0
  case MCK_GPRMM16MovePPairFirst:
2326
0
    switch (B) {
2327
0
    default: return false;
2328
0
    case MCK_Reg8: return true;
2329
0
    case MCK_CPU16Regs: return true;
2330
0
    case MCK_GPRMM16Zero: return true;
2331
0
    case MCK_CPU16RegsPlusSP: return true;
2332
0
    case MCK_GPR32NONZERO: return true;
2333
0
    case MCK_DSPR: return true;
2334
0
    }
2335
2336
0
  case MCK_Reg28:
2337
0
    switch (B) {
2338
0
    default: return false;
2339
0
    case MCK_Reg29: return true;
2340
0
    case MCK_Reg25: return true;
2341
0
    case MCK_Reg22: return true;
2342
0
    case MCK_Reg26: return true;
2343
0
    case MCK_Reg24: return true;
2344
0
    case MCK_GPR64: return true;
2345
0
    }
2346
2347
0
  case MCK_Reg23:
2348
0
    switch (B) {
2349
0
    default: return false;
2350
0
    case MCK_Reg22: return true;
2351
0
    case MCK_Reg21: return true;
2352
0
    case MCK_GPR64: return true;
2353
0
    }
2354
2355
0
  case MCK_Reg9:
2356
0
    switch (B) {
2357
0
    default: return false;
2358
0
    case MCK_Reg10: return true;
2359
0
    case MCK_CPU16Regs: return true;
2360
0
    case MCK_GPRMM16MoveP: return true;
2361
0
    case MCK_CPU16RegsPlusSP: return true;
2362
0
    case MCK_GPR32NONZERO: return true;
2363
0
    case MCK_DSPR: return true;
2364
0
    }
2365
2366
0
  case MCK_Reg4:
2367
0
    switch (B) {
2368
0
    default: return false;
2369
0
    case MCK_GPRMM16MoveP: return true;
2370
0
    case MCK_GPRMM16Zero: return true;
2371
0
    case MCK_DSPR: return true;
2372
0
    }
2373
2374
0
  case MCK_Reg34:
2375
0
    switch (B) {
2376
0
    default: return false;
2377
0
    case MCK_Reg24: return true;
2378
0
    case MCK_GPR64: return true;
2379
0
    }
2380
2381
0
  case MCK_GPRMM16MovePPairSecond:
2382
0
    switch (B) {
2383
0
    default: return false;
2384
0
    case MCK_GPR32NONZERO: return true;
2385
0
    case MCK_DSPR: return true;
2386
0
    }
2387
2388
0
  case MCK_Reg29:
2389
0
    switch (B) {
2390
0
    default: return false;
2391
0
    case MCK_Reg22: return true;
2392
0
    case MCK_Reg24: return true;
2393
0
    case MCK_GPR64: return true;
2394
0
    }
2395
2396
0
  case MCK_Reg27:
2397
0
    switch (B) {
2398
0
    default: return false;
2399
0
    case MCK_Reg25: return true;
2400
0
    case MCK_Reg21: return true;
2401
0
    case MCK_Reg26: return true;
2402
0
    case MCK_Reg24: return true;
2403
0
    case MCK_GPR64: return true;
2404
0
    }
2405
2406
0
  case MCK_Reg10:
2407
0
    switch (B) {
2408
0
    default: return false;
2409
0
    case MCK_GPRMM16MoveP: return true;
2410
0
    case MCK_GPR32NONZERO: return true;
2411
0
    case MCK_DSPR: return true;
2412
0
    }
2413
2414
0
  case MCK_Reg8:
2415
0
    switch (B) {
2416
0
    default: return false;
2417
0
    case MCK_CPU16Regs: return true;
2418
0
    case MCK_GPRMM16Zero: return true;
2419
0
    case MCK_CPU16RegsPlusSP: return true;
2420
0
    case MCK_GPR32NONZERO: return true;
2421
0
    case MCK_DSPR: return true;
2422
0
    }
2423
2424
0
  case MCK_Reg25:
2425
0
    switch (B) {
2426
0
    default: return false;
2427
0
    case MCK_Reg26: return true;
2428
0
    case MCK_Reg24: return true;
2429
0
    case MCK_GPR64: return true;
2430
0
    }
2431
2432
0
  case MCK_Reg22:
2433
0
    return B == MCK_GPR64;
2434
2435
0
  case MCK_Reg21:
2436
0
    return B == MCK_GPR64;
2437
2438
0
  case MCK_CPU16Regs:
2439
0
    switch (B) {
2440
0
    default: return false;
2441
0
    case MCK_CPU16RegsPlusSP: return true;
2442
0
    case MCK_GPR32NONZERO: return true;
2443
0
    case MCK_DSPR: return true;
2444
0
    }
2445
2446
0
  case MCK_GPRMM16MoveP:
2447
0
    return B == MCK_DSPR;
2448
2449
0
  case MCK_GPRMM16Zero:
2450
0
    return B == MCK_DSPR;
2451
2452
0
  case MCK_Reg26:
2453
0
    switch (B) {
2454
0
    default: return false;
2455
0
    case MCK_Reg24: return true;
2456
0
    case MCK_GPR64: return true;
2457
0
    }
2458
2459
0
  case MCK_CPU16RegsPlusSP:
2460
0
    switch (B) {
2461
0
    default: return false;
2462
0
    case MCK_GPR32NONZERO: return true;
2463
0
    case MCK_DSPR: return true;
2464
0
    }
2465
2466
0
  case MCK_MSA128WEvens:
2467
0
    return B == MCK_MSA128F16;
2468
2469
0
  case MCK_Reg24:
2470
0
    return B == MCK_GPR64;
2471
2472
0
  case MCK_GPR32NONZERO:
2473
0
    return B == MCK_DSPR;
2474
2475
0
  case MCK_MemOffsetSimmPtr:
2476
0
    return B == MCK_Mem;
2477
2478
0
  case MCK_MemOffsetUimm4:
2479
0
    return B == MCK_Mem;
2480
2481
0
  case MCK_MemOffsetSimm9_0:
2482
0
    return B == MCK_Mem;
2483
2484
0
  case MCK_MemOffsetSimm10_0:
2485
0
    return B == MCK_Mem;
2486
2487
0
  case MCK_MemOffsetSimm11_0:
2488
0
    return B == MCK_Mem;
2489
2490
0
  case MCK_MemOffsetSimm12_0:
2491
0
    return B == MCK_Mem;
2492
2493
0
  case MCK_MemOffsetSimm16_0:
2494
0
    return B == MCK_Mem;
2495
2496
0
  case MCK_MemOffsetSimm10_1:
2497
0
    return B == MCK_Mem;
2498
2499
0
  case MCK_MemOffsetSimm10_2:
2500
0
    return B == MCK_Mem;
2501
2502
0
  case MCK_MemOffsetSimm10_3:
2503
0
    return B == MCK_Mem;
2504
2505
0
  case MCK_ConstantImmz:
2506
0
    switch (B) {
2507
0
    default: return false;
2508
0
    case MCK_ConstantUImm1_0: return true;
2509
0
    case MCK_ConstantUImm2_0: return true;
2510
0
    case MCK_ConstantUImm3_0: return true;
2511
0
    case MCK_ConstantSImm4_0: return true;
2512
0
    case MCK_ConstantUImm4_0: return true;
2513
0
    case MCK_ConstantSImm5_0: return true;
2514
0
    case MCK_ConstantUImm5_0: return true;
2515
0
    case MCK_ConstantUImm5_1: return true;
2516
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2517
0
    case MCK_ConstantUImm5_32_Norm: return true;
2518
0
    case MCK_ConstantUImm5_32: return true;
2519
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2520
0
    case MCK_ConstantUImm5_33: return true;
2521
0
    case MCK_ConstantUImmRange2_64: return true;
2522
0
    case MCK_UImm5Lsl2: return true;
2523
0
    case MCK_ConstantSImm6_0: return true;
2524
0
    case MCK_ConstantUImm6_0: return true;
2525
0
    case MCK_UImm6Lsl2: return true;
2526
0
    case MCK_ConstantUImm7_0: return true;
2527
0
    case MCK_UImm7_N1: return true;
2528
0
    case MCK_ConstantUImm8_0: return true;
2529
0
    case MCK_SImm7Lsl2: return true;
2530
0
    case MCK_ConstantSImm9_0: return true;
2531
0
    case MCK_ConstantSImm10_0: return true;
2532
0
    case MCK_ConstantUImm10_0: return true;
2533
0
    case MCK_SImm10Lsl1: return true;
2534
0
    case MCK_ConstantSImm11_0: return true;
2535
0
    case MCK_SImm10Lsl2: return true;
2536
0
    case MCK_SImm10Lsl3: return true;
2537
0
    case MCK_SImm16: return true;
2538
0
    case MCK_SImm16_Relaxed: return true;
2539
0
    case MCK_UImm16_Relaxed: return true;
2540
0
    case MCK_ConstantUImm20_0: return true;
2541
0
    case MCK_ConstantUImm26_0: return true;
2542
0
    case MCK_SImm32: return true;
2543
0
    case MCK_SImm32_Relaxed: return true;
2544
0
    case MCK_UImm32_Coerced: return true;
2545
0
    }
2546
2547
0
  case MCK_ConstantUImm1_0:
2548
0
    switch (B) {
2549
0
    default: return false;
2550
0
    case MCK_ConstantUImm2_0: return true;
2551
0
    case MCK_ConstantUImm3_0: return true;
2552
0
    case MCK_ConstantSImm4_0: return true;
2553
0
    case MCK_ConstantUImm4_0: return true;
2554
0
    case MCK_ConstantSImm5_0: return true;
2555
0
    case MCK_ConstantUImm5_0: return true;
2556
0
    case MCK_ConstantUImm5_1: return true;
2557
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2558
0
    case MCK_ConstantUImm5_32_Norm: return true;
2559
0
    case MCK_ConstantUImm5_32: return true;
2560
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2561
0
    case MCK_ConstantUImm5_33: return true;
2562
0
    case MCK_ConstantUImmRange2_64: return true;
2563
0
    case MCK_UImm5Lsl2: return true;
2564
0
    case MCK_ConstantSImm6_0: return true;
2565
0
    case MCK_ConstantUImm6_0: return true;
2566
0
    case MCK_UImm6Lsl2: return true;
2567
0
    case MCK_ConstantUImm7_0: return true;
2568
0
    case MCK_UImm7_N1: return true;
2569
0
    case MCK_ConstantUImm8_0: return true;
2570
0
    case MCK_SImm7Lsl2: return true;
2571
0
    case MCK_ConstantSImm9_0: return true;
2572
0
    case MCK_ConstantSImm10_0: return true;
2573
0
    case MCK_ConstantUImm10_0: return true;
2574
0
    case MCK_SImm10Lsl1: return true;
2575
0
    case MCK_ConstantSImm11_0: return true;
2576
0
    case MCK_SImm10Lsl2: return true;
2577
0
    case MCK_SImm10Lsl3: return true;
2578
0
    case MCK_SImm16: return true;
2579
0
    case MCK_SImm16_Relaxed: return true;
2580
0
    case MCK_UImm16_Relaxed: return true;
2581
0
    case MCK_ConstantUImm20_0: return true;
2582
0
    case MCK_ConstantUImm26_0: return true;
2583
0
    case MCK_SImm32: return true;
2584
0
    case MCK_SImm32_Relaxed: return true;
2585
0
    case MCK_UImm32_Coerced: return true;
2586
0
    }
2587
2588
0
  case MCK_ConstantUImm2_0:
2589
0
    switch (B) {
2590
0
    default: return false;
2591
0
    case MCK_ConstantUImm3_0: return true;
2592
0
    case MCK_ConstantSImm4_0: return true;
2593
0
    case MCK_ConstantUImm4_0: return true;
2594
0
    case MCK_ConstantSImm5_0: return true;
2595
0
    case MCK_ConstantUImm5_0: return true;
2596
0
    case MCK_ConstantUImm5_1: return true;
2597
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2598
0
    case MCK_ConstantUImm5_32_Norm: return true;
2599
0
    case MCK_ConstantUImm5_32: return true;
2600
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2601
0
    case MCK_ConstantUImm5_33: return true;
2602
0
    case MCK_ConstantUImmRange2_64: return true;
2603
0
    case MCK_UImm5Lsl2: return true;
2604
0
    case MCK_ConstantSImm6_0: return true;
2605
0
    case MCK_ConstantUImm6_0: return true;
2606
0
    case MCK_UImm6Lsl2: return true;
2607
0
    case MCK_ConstantUImm7_0: return true;
2608
0
    case MCK_UImm7_N1: return true;
2609
0
    case MCK_ConstantUImm8_0: return true;
2610
0
    case MCK_SImm7Lsl2: return true;
2611
0
    case MCK_ConstantSImm9_0: return true;
2612
0
    case MCK_ConstantSImm10_0: return true;
2613
0
    case MCK_ConstantUImm10_0: return true;
2614
0
    case MCK_SImm10Lsl1: return true;
2615
0
    case MCK_ConstantSImm11_0: return true;
2616
0
    case MCK_SImm10Lsl2: return true;
2617
0
    case MCK_SImm10Lsl3: return true;
2618
0
    case MCK_SImm16: return true;
2619
0
    case MCK_SImm16_Relaxed: return true;
2620
0
    case MCK_UImm16_Relaxed: return true;
2621
0
    case MCK_ConstantUImm20_0: return true;
2622
0
    case MCK_ConstantUImm26_0: return true;
2623
0
    case MCK_SImm32: return true;
2624
0
    case MCK_SImm32_Relaxed: return true;
2625
0
    case MCK_UImm32_Coerced: return true;
2626
0
    }
2627
2628
0
  case MCK_ConstantUImm2_1:
2629
0
    switch (B) {
2630
0
    default: return false;
2631
0
    case MCK_ConstantUImm3_0: return true;
2632
0
    case MCK_ConstantSImm4_0: return true;
2633
0
    case MCK_ConstantUImm4_0: return true;
2634
0
    case MCK_ConstantSImm5_0: return true;
2635
0
    case MCK_ConstantUImm5_0: return true;
2636
0
    case MCK_ConstantUImm5_1: return true;
2637
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2638
0
    case MCK_ConstantUImm5_32_Norm: return true;
2639
0
    case MCK_ConstantUImm5_32: return true;
2640
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2641
0
    case MCK_ConstantUImm5_33: return true;
2642
0
    case MCK_ConstantUImmRange2_64: return true;
2643
0
    case MCK_UImm5Lsl2: return true;
2644
0
    case MCK_ConstantSImm6_0: return true;
2645
0
    case MCK_ConstantUImm6_0: return true;
2646
0
    case MCK_UImm6Lsl2: return true;
2647
0
    case MCK_ConstantUImm7_0: return true;
2648
0
    case MCK_UImm7_N1: return true;
2649
0
    case MCK_ConstantUImm8_0: return true;
2650
0
    case MCK_SImm7Lsl2: return true;
2651
0
    case MCK_ConstantSImm9_0: return true;
2652
0
    case MCK_ConstantSImm10_0: return true;
2653
0
    case MCK_ConstantUImm10_0: return true;
2654
0
    case MCK_SImm10Lsl1: return true;
2655
0
    case MCK_ConstantSImm11_0: return true;
2656
0
    case MCK_SImm10Lsl2: return true;
2657
0
    case MCK_SImm10Lsl3: return true;
2658
0
    case MCK_SImm16: return true;
2659
0
    case MCK_SImm16_Relaxed: return true;
2660
0
    case MCK_UImm16_Relaxed: return true;
2661
0
    case MCK_ConstantUImm20_0: return true;
2662
0
    case MCK_ConstantUImm26_0: return true;
2663
0
    case MCK_SImm32: return true;
2664
0
    case MCK_SImm32_Relaxed: return true;
2665
0
    case MCK_UImm32_Coerced: return true;
2666
0
    }
2667
2668
0
  case MCK_ConstantUImm3_0:
2669
0
    switch (B) {
2670
0
    default: return false;
2671
0
    case MCK_ConstantSImm4_0: return true;
2672
0
    case MCK_ConstantUImm4_0: return true;
2673
0
    case MCK_ConstantSImm5_0: return true;
2674
0
    case MCK_ConstantUImm5_0: return true;
2675
0
    case MCK_ConstantUImm5_1: return true;
2676
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2677
0
    case MCK_ConstantUImm5_32_Norm: return true;
2678
0
    case MCK_ConstantUImm5_32: return true;
2679
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2680
0
    case MCK_ConstantUImm5_33: return true;
2681
0
    case MCK_ConstantUImmRange2_64: return true;
2682
0
    case MCK_UImm5Lsl2: return true;
2683
0
    case MCK_ConstantSImm6_0: return true;
2684
0
    case MCK_ConstantUImm6_0: return true;
2685
0
    case MCK_UImm6Lsl2: return true;
2686
0
    case MCK_ConstantUImm7_0: return true;
2687
0
    case MCK_UImm7_N1: return true;
2688
0
    case MCK_ConstantUImm8_0: return true;
2689
0
    case MCK_SImm7Lsl2: return true;
2690
0
    case MCK_ConstantSImm9_0: return true;
2691
0
    case MCK_ConstantSImm10_0: return true;
2692
0
    case MCK_ConstantUImm10_0: return true;
2693
0
    case MCK_SImm10Lsl1: return true;
2694
0
    case MCK_ConstantSImm11_0: return true;
2695
0
    case MCK_SImm10Lsl2: return true;
2696
0
    case MCK_SImm10Lsl3: return true;
2697
0
    case MCK_SImm16: return true;
2698
0
    case MCK_SImm16_Relaxed: return true;
2699
0
    case MCK_UImm16_Relaxed: return true;
2700
0
    case MCK_ConstantUImm20_0: return true;
2701
0
    case MCK_ConstantUImm26_0: return true;
2702
0
    case MCK_SImm32: return true;
2703
0
    case MCK_SImm32_Relaxed: return true;
2704
0
    case MCK_UImm32_Coerced: return true;
2705
0
    }
2706
2707
0
  case MCK_ConstantSImm4_0:
2708
0
    switch (B) {
2709
0
    default: return false;
2710
0
    case MCK_ConstantUImm4_0: return true;
2711
0
    case MCK_ConstantSImm5_0: return true;
2712
0
    case MCK_ConstantUImm5_0: return true;
2713
0
    case MCK_ConstantUImm5_1: return true;
2714
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2715
0
    case MCK_ConstantUImm5_32_Norm: return true;
2716
0
    case MCK_ConstantUImm5_32: return true;
2717
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2718
0
    case MCK_ConstantUImm5_33: return true;
2719
0
    case MCK_ConstantUImmRange2_64: return true;
2720
0
    case MCK_UImm5Lsl2: return true;
2721
0
    case MCK_ConstantSImm6_0: return true;
2722
0
    case MCK_ConstantUImm6_0: return true;
2723
0
    case MCK_UImm6Lsl2: return true;
2724
0
    case MCK_ConstantUImm7_0: return true;
2725
0
    case MCK_UImm7_N1: return true;
2726
0
    case MCK_ConstantUImm8_0: return true;
2727
0
    case MCK_SImm7Lsl2: return true;
2728
0
    case MCK_ConstantSImm9_0: return true;
2729
0
    case MCK_ConstantSImm10_0: return true;
2730
0
    case MCK_ConstantUImm10_0: return true;
2731
0
    case MCK_SImm10Lsl1: return true;
2732
0
    case MCK_ConstantSImm11_0: return true;
2733
0
    case MCK_SImm10Lsl2: return true;
2734
0
    case MCK_SImm10Lsl3: return true;
2735
0
    case MCK_SImm16: return true;
2736
0
    case MCK_SImm16_Relaxed: return true;
2737
0
    case MCK_UImm16_Relaxed: return true;
2738
0
    case MCK_ConstantUImm20_0: return true;
2739
0
    case MCK_ConstantUImm26_0: return true;
2740
0
    case MCK_SImm32: return true;
2741
0
    case MCK_SImm32_Relaxed: return true;
2742
0
    case MCK_UImm32_Coerced: return true;
2743
0
    }
2744
2745
0
  case MCK_ConstantUImm4_0:
2746
0
    switch (B) {
2747
0
    default: return false;
2748
0
    case MCK_ConstantSImm5_0: return true;
2749
0
    case MCK_ConstantUImm5_0: return true;
2750
0
    case MCK_ConstantUImm5_1: return true;
2751
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2752
0
    case MCK_ConstantUImm5_32_Norm: return true;
2753
0
    case MCK_ConstantUImm5_32: return true;
2754
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2755
0
    case MCK_ConstantUImm5_33: return true;
2756
0
    case MCK_ConstantUImmRange2_64: return true;
2757
0
    case MCK_UImm5Lsl2: return true;
2758
0
    case MCK_ConstantSImm6_0: return true;
2759
0
    case MCK_ConstantUImm6_0: return true;
2760
0
    case MCK_UImm6Lsl2: return true;
2761
0
    case MCK_ConstantUImm7_0: return true;
2762
0
    case MCK_UImm7_N1: return true;
2763
0
    case MCK_ConstantUImm8_0: return true;
2764
0
    case MCK_SImm7Lsl2: return true;
2765
0
    case MCK_ConstantSImm9_0: return true;
2766
0
    case MCK_ConstantSImm10_0: return true;
2767
0
    case MCK_ConstantUImm10_0: return true;
2768
0
    case MCK_SImm10Lsl1: return true;
2769
0
    case MCK_ConstantSImm11_0: return true;
2770
0
    case MCK_SImm10Lsl2: return true;
2771
0
    case MCK_SImm10Lsl3: return true;
2772
0
    case MCK_SImm16: return true;
2773
0
    case MCK_SImm16_Relaxed: return true;
2774
0
    case MCK_UImm16_Relaxed: return true;
2775
0
    case MCK_ConstantUImm20_0: return true;
2776
0
    case MCK_ConstantUImm26_0: return true;
2777
0
    case MCK_SImm32: return true;
2778
0
    case MCK_SImm32_Relaxed: return true;
2779
0
    case MCK_UImm32_Coerced: return true;
2780
0
    }
2781
2782
0
  case MCK_ConstantSImm5_0:
2783
0
    switch (B) {
2784
0
    default: return false;
2785
0
    case MCK_ConstantUImm5_0: return true;
2786
0
    case MCK_ConstantUImm5_1: return true;
2787
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2788
0
    case MCK_ConstantUImm5_32_Norm: return true;
2789
0
    case MCK_ConstantUImm5_32: return true;
2790
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2791
0
    case MCK_ConstantUImm5_33: return true;
2792
0
    case MCK_ConstantUImmRange2_64: return true;
2793
0
    case MCK_UImm5Lsl2: return true;
2794
0
    case MCK_ConstantSImm6_0: return true;
2795
0
    case MCK_ConstantUImm6_0: return true;
2796
0
    case MCK_UImm6Lsl2: return true;
2797
0
    case MCK_ConstantUImm7_0: return true;
2798
0
    case MCK_UImm7_N1: return true;
2799
0
    case MCK_ConstantUImm8_0: return true;
2800
0
    case MCK_SImm7Lsl2: return true;
2801
0
    case MCK_ConstantSImm9_0: return true;
2802
0
    case MCK_ConstantSImm10_0: return true;
2803
0
    case MCK_ConstantUImm10_0: return true;
2804
0
    case MCK_SImm10Lsl1: return true;
2805
0
    case MCK_ConstantSImm11_0: return true;
2806
0
    case MCK_SImm10Lsl2: return true;
2807
0
    case MCK_SImm10Lsl3: return true;
2808
0
    case MCK_SImm16: return true;
2809
0
    case MCK_SImm16_Relaxed: return true;
2810
0
    case MCK_UImm16_Relaxed: return true;
2811
0
    case MCK_ConstantUImm20_0: return true;
2812
0
    case MCK_ConstantUImm26_0: return true;
2813
0
    case MCK_SImm32: return true;
2814
0
    case MCK_SImm32_Relaxed: return true;
2815
0
    case MCK_UImm32_Coerced: return true;
2816
0
    }
2817
2818
0
  case MCK_ConstantUImm5_0:
2819
0
    switch (B) {
2820
0
    default: return false;
2821
0
    case MCK_ConstantUImm5_1: return true;
2822
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2823
0
    case MCK_ConstantUImm5_32_Norm: return true;
2824
0
    case MCK_ConstantUImm5_32: return true;
2825
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2826
0
    case MCK_ConstantUImm5_33: return true;
2827
0
    case MCK_ConstantUImmRange2_64: return true;
2828
0
    case MCK_UImm5Lsl2: return true;
2829
0
    case MCK_ConstantSImm6_0: return true;
2830
0
    case MCK_ConstantUImm6_0: return true;
2831
0
    case MCK_UImm6Lsl2: return true;
2832
0
    case MCK_ConstantUImm7_0: return true;
2833
0
    case MCK_UImm7_N1: return true;
2834
0
    case MCK_ConstantUImm8_0: return true;
2835
0
    case MCK_SImm7Lsl2: return true;
2836
0
    case MCK_ConstantSImm9_0: return true;
2837
0
    case MCK_ConstantSImm10_0: return true;
2838
0
    case MCK_ConstantUImm10_0: return true;
2839
0
    case MCK_SImm10Lsl1: return true;
2840
0
    case MCK_ConstantSImm11_0: return true;
2841
0
    case MCK_SImm10Lsl2: return true;
2842
0
    case MCK_SImm10Lsl3: return true;
2843
0
    case MCK_SImm16: return true;
2844
0
    case MCK_SImm16_Relaxed: return true;
2845
0
    case MCK_UImm16_Relaxed: return true;
2846
0
    case MCK_ConstantUImm20_0: return true;
2847
0
    case MCK_ConstantUImm26_0: return true;
2848
0
    case MCK_SImm32: return true;
2849
0
    case MCK_SImm32_Relaxed: return true;
2850
0
    case MCK_UImm32_Coerced: return true;
2851
0
    }
2852
2853
0
  case MCK_ConstantUImm5_1:
2854
0
    switch (B) {
2855
0
    default: return false;
2856
0
    case MCK_ConstantUImm5_Plus1_Report_UImm6: return true;
2857
0
    case MCK_ConstantUImm5_32_Norm: return true;
2858
0
    case MCK_ConstantUImm5_32: return true;
2859
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2860
0
    case MCK_ConstantUImm5_33: return true;
2861
0
    case MCK_ConstantUImmRange2_64: return true;
2862
0
    case MCK_UImm5Lsl2: return true;
2863
0
    case MCK_ConstantSImm6_0: return true;
2864
0
    case MCK_ConstantUImm6_0: return true;
2865
0
    case MCK_UImm6Lsl2: return true;
2866
0
    case MCK_ConstantUImm7_0: return true;
2867
0
    case MCK_UImm7_N1: return true;
2868
0
    case MCK_ConstantUImm8_0: return true;
2869
0
    case MCK_SImm7Lsl2: return true;
2870
0
    case MCK_ConstantSImm9_0: return true;
2871
0
    case MCK_ConstantSImm10_0: return true;
2872
0
    case MCK_ConstantUImm10_0: return true;
2873
0
    case MCK_SImm10Lsl1: return true;
2874
0
    case MCK_ConstantSImm11_0: return true;
2875
0
    case MCK_SImm10Lsl2: return true;
2876
0
    case MCK_SImm10Lsl3: return true;
2877
0
    case MCK_SImm16: return true;
2878
0
    case MCK_SImm16_Relaxed: return true;
2879
0
    case MCK_UImm16_Relaxed: return true;
2880
0
    case MCK_ConstantUImm20_0: return true;
2881
0
    case MCK_ConstantUImm26_0: return true;
2882
0
    case MCK_SImm32: return true;
2883
0
    case MCK_SImm32_Relaxed: return true;
2884
0
    case MCK_UImm32_Coerced: return true;
2885
0
    }
2886
2887
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6:
2888
0
    switch (B) {
2889
0
    default: return false;
2890
0
    case MCK_ConstantUImm5_32_Norm: return true;
2891
0
    case MCK_ConstantUImm5_32: return true;
2892
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2893
0
    case MCK_ConstantUImm5_33: return true;
2894
0
    case MCK_ConstantUImmRange2_64: return true;
2895
0
    case MCK_UImm5Lsl2: return true;
2896
0
    case MCK_ConstantSImm6_0: return true;
2897
0
    case MCK_ConstantUImm6_0: return true;
2898
0
    case MCK_UImm6Lsl2: return true;
2899
0
    case MCK_ConstantUImm7_0: return true;
2900
0
    case MCK_UImm7_N1: return true;
2901
0
    case MCK_ConstantUImm8_0: return true;
2902
0
    case MCK_SImm7Lsl2: return true;
2903
0
    case MCK_ConstantSImm9_0: return true;
2904
0
    case MCK_ConstantSImm10_0: return true;
2905
0
    case MCK_ConstantUImm10_0: return true;
2906
0
    case MCK_SImm10Lsl1: return true;
2907
0
    case MCK_ConstantSImm11_0: return true;
2908
0
    case MCK_SImm10Lsl2: return true;
2909
0
    case MCK_SImm10Lsl3: return true;
2910
0
    case MCK_SImm16: return true;
2911
0
    case MCK_SImm16_Relaxed: return true;
2912
0
    case MCK_UImm16_Relaxed: return true;
2913
0
    case MCK_ConstantUImm20_0: return true;
2914
0
    case MCK_ConstantUImm26_0: return true;
2915
0
    case MCK_SImm32: return true;
2916
0
    case MCK_SImm32_Relaxed: return true;
2917
0
    case MCK_UImm32_Coerced: return true;
2918
0
    }
2919
2920
0
  case MCK_ConstantUImm5_32_Norm:
2921
0
    switch (B) {
2922
0
    default: return false;
2923
0
    case MCK_ConstantUImm5_32: return true;
2924
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2925
0
    case MCK_ConstantUImm5_33: return true;
2926
0
    case MCK_ConstantUImmRange2_64: return true;
2927
0
    case MCK_UImm5Lsl2: return true;
2928
0
    case MCK_ConstantSImm6_0: return true;
2929
0
    case MCK_ConstantUImm6_0: return true;
2930
0
    case MCK_UImm6Lsl2: return true;
2931
0
    case MCK_ConstantUImm7_0: return true;
2932
0
    case MCK_UImm7_N1: return true;
2933
0
    case MCK_ConstantUImm8_0: return true;
2934
0
    case MCK_SImm7Lsl2: return true;
2935
0
    case MCK_ConstantSImm9_0: return true;
2936
0
    case MCK_ConstantSImm10_0: return true;
2937
0
    case MCK_ConstantUImm10_0: return true;
2938
0
    case MCK_SImm10Lsl1: return true;
2939
0
    case MCK_ConstantSImm11_0: return true;
2940
0
    case MCK_SImm10Lsl2: return true;
2941
0
    case MCK_SImm10Lsl3: return true;
2942
0
    case MCK_SImm16: return true;
2943
0
    case MCK_SImm16_Relaxed: return true;
2944
0
    case MCK_UImm16_Relaxed: return true;
2945
0
    case MCK_ConstantUImm20_0: return true;
2946
0
    case MCK_ConstantUImm26_0: return true;
2947
0
    case MCK_SImm32: return true;
2948
0
    case MCK_SImm32_Relaxed: return true;
2949
0
    case MCK_UImm32_Coerced: return true;
2950
0
    }
2951
2952
0
  case MCK_ConstantUImm5_32:
2953
0
    switch (B) {
2954
0
    default: return false;
2955
0
    case MCK_ConstantUImm5_0_Report_UImm6: return true;
2956
0
    case MCK_ConstantUImm5_33: return true;
2957
0
    case MCK_ConstantUImmRange2_64: return true;
2958
0
    case MCK_UImm5Lsl2: return true;
2959
0
    case MCK_ConstantSImm6_0: return true;
2960
0
    case MCK_ConstantUImm6_0: return true;
2961
0
    case MCK_UImm6Lsl2: return true;
2962
0
    case MCK_ConstantUImm7_0: return true;
2963
0
    case MCK_UImm7_N1: return true;
2964
0
    case MCK_ConstantUImm8_0: return true;
2965
0
    case MCK_SImm7Lsl2: return true;
2966
0
    case MCK_ConstantSImm9_0: return true;
2967
0
    case MCK_ConstantSImm10_0: return true;
2968
0
    case MCK_ConstantUImm10_0: return true;
2969
0
    case MCK_SImm10Lsl1: return true;
2970
0
    case MCK_ConstantSImm11_0: return true;
2971
0
    case MCK_SImm10Lsl2: return true;
2972
0
    case MCK_SImm10Lsl3: return true;
2973
0
    case MCK_SImm16: return true;
2974
0
    case MCK_SImm16_Relaxed: return true;
2975
0
    case MCK_UImm16_Relaxed: return true;
2976
0
    case MCK_ConstantUImm20_0: return true;
2977
0
    case MCK_ConstantUImm26_0: return true;
2978
0
    case MCK_SImm32: return true;
2979
0
    case MCK_SImm32_Relaxed: return true;
2980
0
    case MCK_UImm32_Coerced: return true;
2981
0
    }
2982
2983
0
  case MCK_ConstantUImm5_0_Report_UImm6:
2984
0
    switch (B) {
2985
0
    default: return false;
2986
0
    case MCK_ConstantUImm5_33: return true;
2987
0
    case MCK_ConstantUImmRange2_64: return true;
2988
0
    case MCK_UImm5Lsl2: return true;
2989
0
    case MCK_ConstantSImm6_0: return true;
2990
0
    case MCK_ConstantUImm6_0: return true;
2991
0
    case MCK_UImm6Lsl2: return true;
2992
0
    case MCK_ConstantUImm7_0: return true;
2993
0
    case MCK_UImm7_N1: return true;
2994
0
    case MCK_ConstantUImm8_0: return true;
2995
0
    case MCK_SImm7Lsl2: return true;
2996
0
    case MCK_ConstantSImm9_0: return true;
2997
0
    case MCK_ConstantSImm10_0: return true;
2998
0
    case MCK_ConstantUImm10_0: return true;
2999
0
    case MCK_SImm10Lsl1: return true;
3000
0
    case MCK_ConstantSImm11_0: return true;
3001
0
    case MCK_SImm10Lsl2: return true;
3002
0
    case MCK_SImm10Lsl3: return true;
3003
0
    case MCK_SImm16: return true;
3004
0
    case MCK_SImm16_Relaxed: return true;
3005
0
    case MCK_UImm16_Relaxed: return true;
3006
0
    case MCK_ConstantUImm20_0: return true;
3007
0
    case MCK_ConstantUImm26_0: return true;
3008
0
    case MCK_SImm32: return true;
3009
0
    case MCK_SImm32_Relaxed: return true;
3010
0
    case MCK_UImm32_Coerced: return true;
3011
0
    }
3012
3013
0
  case MCK_ConstantUImm5_33:
3014
0
    switch (B) {
3015
0
    default: return false;
3016
0
    case MCK_ConstantUImmRange2_64: return true;
3017
0
    case MCK_UImm5Lsl2: return true;
3018
0
    case MCK_ConstantSImm6_0: return true;
3019
0
    case MCK_ConstantUImm6_0: return true;
3020
0
    case MCK_UImm6Lsl2: return true;
3021
0
    case MCK_ConstantUImm7_0: return true;
3022
0
    case MCK_UImm7_N1: return true;
3023
0
    case MCK_ConstantUImm8_0: return true;
3024
0
    case MCK_SImm7Lsl2: return true;
3025
0
    case MCK_ConstantSImm9_0: return true;
3026
0
    case MCK_ConstantSImm10_0: return true;
3027
0
    case MCK_ConstantUImm10_0: return true;
3028
0
    case MCK_SImm10Lsl1: return true;
3029
0
    case MCK_ConstantSImm11_0: return true;
3030
0
    case MCK_SImm10Lsl2: return true;
3031
0
    case MCK_SImm10Lsl3: return true;
3032
0
    case MCK_SImm16: return true;
3033
0
    case MCK_SImm16_Relaxed: return true;
3034
0
    case MCK_UImm16_Relaxed: return true;
3035
0
    case MCK_ConstantUImm20_0: return true;
3036
0
    case MCK_ConstantUImm26_0: return true;
3037
0
    case MCK_SImm32: return true;
3038
0
    case MCK_SImm32_Relaxed: return true;
3039
0
    case MCK_UImm32_Coerced: return true;
3040
0
    }
3041
3042
0
  case MCK_ConstantUImmRange2_64:
3043
0
    switch (B) {
3044
0
    default: return false;
3045
0
    case MCK_UImm5Lsl2: return true;
3046
0
    case MCK_ConstantSImm6_0: return true;
3047
0
    case MCK_ConstantUImm6_0: return true;
3048
0
    case MCK_UImm6Lsl2: return true;
3049
0
    case MCK_ConstantUImm7_0: return true;
3050
0
    case MCK_UImm7_N1: return true;
3051
0
    case MCK_ConstantUImm8_0: return true;
3052
0
    case MCK_SImm7Lsl2: return true;
3053
0
    case MCK_ConstantSImm9_0: return true;
3054
0
    case MCK_ConstantSImm10_0: return true;
3055
0
    case MCK_ConstantUImm10_0: return true;
3056
0
    case MCK_SImm10Lsl1: return true;
3057
0
    case MCK_ConstantSImm11_0: return true;
3058
0
    case MCK_SImm10Lsl2: return true;
3059
0
    case MCK_SImm10Lsl3: return true;
3060
0
    case MCK_SImm16: return true;
3061
0
    case MCK_SImm16_Relaxed: return true;
3062
0
    case MCK_UImm16_Relaxed: return true;
3063
0
    case MCK_ConstantUImm20_0: return true;
3064
0
    case MCK_ConstantUImm26_0: return true;
3065
0
    case MCK_SImm32: return true;
3066
0
    case MCK_SImm32_Relaxed: return true;
3067
0
    case MCK_UImm32_Coerced: return true;
3068
0
    }
3069
3070
0
  case MCK_UImm5Lsl2:
3071
0
    switch (B) {
3072
0
    default: return false;
3073
0
    case MCK_ConstantSImm6_0: return true;
3074
0
    case MCK_ConstantUImm6_0: return true;
3075
0
    case MCK_UImm6Lsl2: return true;
3076
0
    case MCK_ConstantUImm7_0: return true;
3077
0
    case MCK_UImm7_N1: return true;
3078
0
    case MCK_ConstantUImm8_0: return true;
3079
0
    case MCK_SImm7Lsl2: return true;
3080
0
    case MCK_ConstantSImm9_0: return true;
3081
0
    case MCK_ConstantSImm10_0: return true;
3082
0
    case MCK_ConstantUImm10_0: return true;
3083
0
    case MCK_SImm10Lsl1: return true;
3084
0
    case MCK_ConstantSImm11_0: return true;
3085
0
    case MCK_SImm10Lsl2: return true;
3086
0
    case MCK_SImm10Lsl3: return true;
3087
0
    case MCK_SImm16: return true;
3088
0
    case MCK_SImm16_Relaxed: return true;
3089
0
    case MCK_UImm16_Relaxed: return true;
3090
0
    case MCK_ConstantUImm20_0: return true;
3091
0
    case MCK_ConstantUImm26_0: return true;
3092
0
    case MCK_SImm32: return true;
3093
0
    case MCK_SImm32_Relaxed: return true;
3094
0
    case MCK_UImm32_Coerced: return true;
3095
0
    }
3096
3097
0
  case MCK_ConstantSImm6_0:
3098
0
    switch (B) {
3099
0
    default: return false;
3100
0
    case MCK_ConstantUImm6_0: return true;
3101
0
    case MCK_UImm6Lsl2: return true;
3102
0
    case MCK_ConstantUImm7_0: return true;
3103
0
    case MCK_UImm7_N1: return true;
3104
0
    case MCK_ConstantUImm8_0: return true;
3105
0
    case MCK_SImm7Lsl2: return true;
3106
0
    case MCK_ConstantSImm9_0: return true;
3107
0
    case MCK_ConstantSImm10_0: return true;
3108
0
    case MCK_ConstantUImm10_0: return true;
3109
0
    case MCK_SImm10Lsl1: return true;
3110
0
    case MCK_ConstantSImm11_0: return true;
3111
0
    case MCK_SImm10Lsl2: return true;
3112
0
    case MCK_SImm10Lsl3: return true;
3113
0
    case MCK_SImm16: return true;
3114
0
    case MCK_SImm16_Relaxed: return true;
3115
0
    case MCK_UImm16_Relaxed: return true;
3116
0
    case MCK_ConstantUImm20_0: return true;
3117
0
    case MCK_ConstantUImm26_0: return true;
3118
0
    case MCK_SImm32: return true;
3119
0
    case MCK_SImm32_Relaxed: return true;
3120
0
    case MCK_UImm32_Coerced: return true;
3121
0
    }
3122
3123
0
  case MCK_ConstantUImm6_0:
3124
0
    switch (B) {
3125
0
    default: return false;
3126
0
    case MCK_UImm6Lsl2: return true;
3127
0
    case MCK_ConstantUImm7_0: return true;
3128
0
    case MCK_UImm7_N1: return true;
3129
0
    case MCK_ConstantUImm8_0: return true;
3130
0
    case MCK_SImm7Lsl2: return true;
3131
0
    case MCK_ConstantSImm9_0: return true;
3132
0
    case MCK_ConstantSImm10_0: return true;
3133
0
    case MCK_ConstantUImm10_0: return true;
3134
0
    case MCK_SImm10Lsl1: return true;
3135
0
    case MCK_ConstantSImm11_0: return true;
3136
0
    case MCK_SImm10Lsl2: return true;
3137
0
    case MCK_SImm10Lsl3: return true;
3138
0
    case MCK_SImm16: return true;
3139
0
    case MCK_SImm16_Relaxed: return true;
3140
0
    case MCK_UImm16_Relaxed: return true;
3141
0
    case MCK_ConstantUImm20_0: return true;
3142
0
    case MCK_ConstantUImm26_0: return true;
3143
0
    case MCK_SImm32: return true;
3144
0
    case MCK_SImm32_Relaxed: return true;
3145
0
    case MCK_UImm32_Coerced: return true;
3146
0
    }
3147
3148
0
  case MCK_UImm6Lsl2:
3149
0
    switch (B) {
3150
0
    default: return false;
3151
0
    case MCK_ConstantUImm7_0: return true;
3152
0
    case MCK_UImm7_N1: return true;
3153
0
    case MCK_ConstantUImm8_0: return true;
3154
0
    case MCK_SImm7Lsl2: return true;
3155
0
    case MCK_ConstantSImm9_0: return true;
3156
0
    case MCK_ConstantSImm10_0: return true;
3157
0
    case MCK_ConstantUImm10_0: return true;
3158
0
    case MCK_SImm10Lsl1: return true;
3159
0
    case MCK_ConstantSImm11_0: return true;
3160
0
    case MCK_SImm10Lsl2: return true;
3161
0
    case MCK_SImm10Lsl3: return true;
3162
0
    case MCK_SImm16: return true;
3163
0
    case MCK_SImm16_Relaxed: return true;
3164
0
    case MCK_UImm16_Relaxed: return true;
3165
0
    case MCK_ConstantUImm20_0: return true;
3166
0
    case MCK_ConstantUImm26_0: return true;
3167
0
    case MCK_SImm32: return true;
3168
0
    case MCK_SImm32_Relaxed: return true;
3169
0
    case MCK_UImm32_Coerced: return true;
3170
0
    }
3171
3172
0
  case MCK_ConstantUImm7_0:
3173
0
    switch (B) {
3174
0
    default: return false;
3175
0
    case MCK_UImm7_N1: return true;
3176
0
    case MCK_ConstantUImm8_0: return true;
3177
0
    case MCK_SImm7Lsl2: return true;
3178
0
    case MCK_ConstantSImm9_0: return true;
3179
0
    case MCK_ConstantSImm10_0: return true;
3180
0
    case MCK_ConstantUImm10_0: return true;
3181
0
    case MCK_SImm10Lsl1: return true;
3182
0
    case MCK_ConstantSImm11_0: return true;
3183
0
    case MCK_SImm10Lsl2: return true;
3184
0
    case MCK_SImm10Lsl3: return true;
3185
0
    case MCK_SImm16: return true;
3186
0
    case MCK_SImm16_Relaxed: return true;
3187
0
    case MCK_UImm16_Relaxed: return true;
3188
0
    case MCK_ConstantUImm20_0: return true;
3189
0
    case MCK_ConstantUImm26_0: return true;
3190
0
    case MCK_SImm32: return true;
3191
0
    case MCK_SImm32_Relaxed: return true;
3192
0
    case MCK_UImm32_Coerced: return true;
3193
0
    }
3194
3195
0
  case MCK_UImm7_N1:
3196
0
    switch (B) {
3197
0
    default: return false;
3198
0
    case MCK_ConstantUImm8_0: return true;
3199
0
    case MCK_SImm7Lsl2: return true;
3200
0
    case MCK_ConstantSImm9_0: return true;
3201
0
    case MCK_ConstantSImm10_0: return true;
3202
0
    case MCK_ConstantUImm10_0: return true;
3203
0
    case MCK_SImm10Lsl1: return true;
3204
0
    case MCK_ConstantSImm11_0: return true;
3205
0
    case MCK_SImm10Lsl2: return true;
3206
0
    case MCK_SImm10Lsl3: return true;
3207
0
    case MCK_SImm16: return true;
3208
0
    case MCK_SImm16_Relaxed: return true;
3209
0
    case MCK_UImm16_Relaxed: return true;
3210
0
    case MCK_ConstantUImm20_0: return true;
3211
0
    case MCK_ConstantUImm26_0: return true;
3212
0
    case MCK_SImm32: return true;
3213
0
    case MCK_SImm32_Relaxed: return true;
3214
0
    case MCK_UImm32_Coerced: return true;
3215
0
    }
3216
3217
0
  case MCK_ConstantUImm8_0:
3218
0
    switch (B) {
3219
0
    default: return false;
3220
0
    case MCK_SImm7Lsl2: return true;
3221
0
    case MCK_ConstantSImm9_0: return true;
3222
0
    case MCK_ConstantSImm10_0: return true;
3223
0
    case MCK_ConstantUImm10_0: return true;
3224
0
    case MCK_SImm10Lsl1: return true;
3225
0
    case MCK_ConstantSImm11_0: return true;
3226
0
    case MCK_SImm10Lsl2: return true;
3227
0
    case MCK_SImm10Lsl3: return true;
3228
0
    case MCK_SImm16: return true;
3229
0
    case MCK_SImm16_Relaxed: return true;
3230
0
    case MCK_UImm16_Relaxed: return true;
3231
0
    case MCK_ConstantUImm20_0: return true;
3232
0
    case MCK_ConstantUImm26_0: return true;
3233
0
    case MCK_SImm32: return true;
3234
0
    case MCK_SImm32_Relaxed: return true;
3235
0
    case MCK_UImm32_Coerced: return true;
3236
0
    }
3237
3238
0
  case MCK_SImm7Lsl2:
3239
0
    switch (B) {
3240
0
    default: return false;
3241
0
    case MCK_ConstantSImm9_0: return true;
3242
0
    case MCK_ConstantSImm10_0: return true;
3243
0
    case MCK_ConstantUImm10_0: return true;
3244
0
    case MCK_SImm10Lsl1: return true;
3245
0
    case MCK_ConstantSImm11_0: return true;
3246
0
    case MCK_SImm10Lsl2: return true;
3247
0
    case MCK_SImm10Lsl3: return true;
3248
0
    case MCK_SImm16: return true;
3249
0
    case MCK_SImm16_Relaxed: return true;
3250
0
    case MCK_UImm16_Relaxed: return true;
3251
0
    case MCK_ConstantUImm20_0: return true;
3252
0
    case MCK_ConstantUImm26_0: return true;
3253
0
    case MCK_SImm32: return true;
3254
0
    case MCK_SImm32_Relaxed: return true;
3255
0
    case MCK_UImm32_Coerced: return true;
3256
0
    }
3257
3258
0
  case MCK_ConstantSImm9_0:
3259
0
    switch (B) {
3260
0
    default: return false;
3261
0
    case MCK_ConstantSImm10_0: return true;
3262
0
    case MCK_ConstantUImm10_0: return true;
3263
0
    case MCK_SImm10Lsl1: return true;
3264
0
    case MCK_ConstantSImm11_0: return true;
3265
0
    case MCK_SImm10Lsl2: return true;
3266
0
    case MCK_SImm10Lsl3: return true;
3267
0
    case MCK_SImm16: return true;
3268
0
    case MCK_SImm16_Relaxed: return true;
3269
0
    case MCK_UImm16_Relaxed: return true;
3270
0
    case MCK_ConstantUImm20_0: return true;
3271
0
    case MCK_ConstantUImm26_0: return true;
3272
0
    case MCK_SImm32: return true;
3273
0
    case MCK_SImm32_Relaxed: return true;
3274
0
    case MCK_UImm32_Coerced: return true;
3275
0
    }
3276
3277
0
  case MCK_ConstantSImm10_0:
3278
0
    switch (B) {
3279
0
    default: return false;
3280
0
    case MCK_ConstantUImm10_0: return true;
3281
0
    case MCK_SImm10Lsl1: return true;
3282
0
    case MCK_ConstantSImm11_0: return true;
3283
0
    case MCK_SImm10Lsl2: return true;
3284
0
    case MCK_SImm10Lsl3: return true;
3285
0
    case MCK_SImm16: return true;
3286
0
    case MCK_SImm16_Relaxed: return true;
3287
0
    case MCK_UImm16_Relaxed: return true;
3288
0
    case MCK_ConstantUImm20_0: return true;
3289
0
    case MCK_ConstantUImm26_0: return true;
3290
0
    case MCK_SImm32: return true;
3291
0
    case MCK_SImm32_Relaxed: return true;
3292
0
    case MCK_UImm32_Coerced: return true;
3293
0
    }
3294
3295
0
  case MCK_ConstantUImm10_0:
3296
0
    switch (B) {
3297
0
    default: return false;
3298
0
    case MCK_SImm10Lsl1: return true;
3299
0
    case MCK_ConstantSImm11_0: return true;
3300
0
    case MCK_SImm10Lsl2: return true;
3301
0
    case MCK_SImm10Lsl3: return true;
3302
0
    case MCK_SImm16: return true;
3303
0
    case MCK_SImm16_Relaxed: return true;
3304
0
    case MCK_UImm16_Relaxed: return true;
3305
0
    case MCK_ConstantUImm20_0: return true;
3306
0
    case MCK_ConstantUImm26_0: return true;
3307
0
    case MCK_SImm32: return true;
3308
0
    case MCK_SImm32_Relaxed: return true;
3309
0
    case MCK_UImm32_Coerced: return true;
3310
0
    }
3311
3312
0
  case MCK_SImm10Lsl1:
3313
0
    switch (B) {
3314
0
    default: return false;
3315
0
    case MCK_ConstantSImm11_0: return true;
3316
0
    case MCK_SImm10Lsl2: return true;
3317
0
    case MCK_SImm10Lsl3: return true;
3318
0
    case MCK_SImm16: return true;
3319
0
    case MCK_SImm16_Relaxed: return true;
3320
0
    case MCK_UImm16_Relaxed: return true;
3321
0
    case MCK_ConstantUImm20_0: return true;
3322
0
    case MCK_ConstantUImm26_0: return true;
3323
0
    case MCK_SImm32: return true;
3324
0
    case MCK_SImm32_Relaxed: return true;
3325
0
    case MCK_UImm32_Coerced: return true;
3326
0
    }
3327
3328
0
  case MCK_ConstantSImm11_0:
3329
0
    switch (B) {
3330
0
    default: return false;
3331
0
    case MCK_SImm10Lsl2: return true;
3332
0
    case MCK_SImm10Lsl3: return true;
3333
0
    case MCK_SImm16: return true;
3334
0
    case MCK_SImm16_Relaxed: return true;
3335
0
    case MCK_UImm16_Relaxed: return true;
3336
0
    case MCK_ConstantUImm20_0: return true;
3337
0
    case MCK_ConstantUImm26_0: return true;
3338
0
    case MCK_SImm32: return true;
3339
0
    case MCK_SImm32_Relaxed: return true;
3340
0
    case MCK_UImm32_Coerced: return true;
3341
0
    }
3342
3343
0
  case MCK_SImm10Lsl2:
3344
0
    switch (B) {
3345
0
    default: return false;
3346
0
    case MCK_SImm10Lsl3: return true;
3347
0
    case MCK_SImm16: return true;
3348
0
    case MCK_SImm16_Relaxed: return true;
3349
0
    case MCK_UImm16_Relaxed: return true;
3350
0
    case MCK_ConstantUImm20_0: return true;
3351
0
    case MCK_ConstantUImm26_0: return true;
3352
0
    case MCK_SImm32: return true;
3353
0
    case MCK_SImm32_Relaxed: return true;
3354
0
    case MCK_UImm32_Coerced: return true;
3355
0
    }
3356
3357
0
  case MCK_SImm10Lsl3:
3358
0
    switch (B) {
3359
0
    default: return false;
3360
0
    case MCK_SImm16: return true;
3361
0
    case MCK_SImm16_Relaxed: return true;
3362
0
    case MCK_UImm16_Relaxed: return true;
3363
0
    case MCK_ConstantUImm20_0: return true;
3364
0
    case MCK_ConstantUImm26_0: return true;
3365
0
    case MCK_SImm32: return true;
3366
0
    case MCK_SImm32_Relaxed: return true;
3367
0
    case MCK_UImm32_Coerced: return true;
3368
0
    }
3369
3370
0
  case MCK_SImm16:
3371
0
    switch (B) {
3372
0
    default: return false;
3373
0
    case MCK_SImm16_Relaxed: return true;
3374
0
    case MCK_UImm16_Relaxed: return true;
3375
0
    case MCK_ConstantUImm20_0: return true;
3376
0
    case MCK_ConstantUImm26_0: return true;
3377
0
    case MCK_SImm32: return true;
3378
0
    case MCK_SImm32_Relaxed: return true;
3379
0
    case MCK_UImm32_Coerced: return true;
3380
0
    }
3381
3382
0
  case MCK_SImm16_Relaxed:
3383
0
    switch (B) {
3384
0
    default: return false;
3385
0
    case MCK_UImm16_Relaxed: return true;
3386
0
    case MCK_ConstantUImm20_0: return true;
3387
0
    case MCK_ConstantUImm26_0: return true;
3388
0
    case MCK_SImm32: return true;
3389
0
    case MCK_SImm32_Relaxed: return true;
3390
0
    case MCK_UImm32_Coerced: return true;
3391
0
    }
3392
3393
0
  case MCK_UImm16_AltRelaxed:
3394
0
    switch (B) {
3395
0
    default: return false;
3396
0
    case MCK_UImm16_Relaxed: return true;
3397
0
    case MCK_ConstantUImm20_0: return true;
3398
0
    case MCK_ConstantUImm26_0: return true;
3399
0
    case MCK_SImm32: return true;
3400
0
    case MCK_SImm32_Relaxed: return true;
3401
0
    case MCK_UImm32_Coerced: return true;
3402
0
    }
3403
3404
0
  case MCK_UImm16:
3405
0
    switch (B) {
3406
0
    default: return false;
3407
0
    case MCK_UImm16_Relaxed: return true;
3408
0
    case MCK_ConstantUImm20_0: return true;
3409
0
    case MCK_ConstantUImm26_0: return true;
3410
0
    case MCK_SImm32: return true;
3411
0
    case MCK_SImm32_Relaxed: return true;
3412
0
    case MCK_UImm32_Coerced: return true;
3413
0
    }
3414
3415
0
  case MCK_SImm19Lsl2:
3416
0
    switch (B) {
3417
0
    default: return false;
3418
0
    case MCK_ConstantUImm20_0: return true;
3419
0
    case MCK_ConstantUImm26_0: return true;
3420
0
    case MCK_SImm32: return true;
3421
0
    case MCK_SImm32_Relaxed: return true;
3422
0
    case MCK_UImm32_Coerced: return true;
3423
0
    }
3424
3425
0
  case MCK_UImm16_Relaxed:
3426
0
    switch (B) {
3427
0
    default: return false;
3428
0
    case MCK_ConstantUImm20_0: return true;
3429
0
    case MCK_ConstantUImm26_0: return true;
3430
0
    case MCK_SImm32: return true;
3431
0
    case MCK_SImm32_Relaxed: return true;
3432
0
    case MCK_UImm32_Coerced: return true;
3433
0
    }
3434
3435
0
  case MCK_ConstantUImm20_0:
3436
0
    switch (B) {
3437
0
    default: return false;
3438
0
    case MCK_ConstantUImm26_0: return true;
3439
0
    case MCK_SImm32: return true;
3440
0
    case MCK_SImm32_Relaxed: return true;
3441
0
    case MCK_UImm32_Coerced: return true;
3442
0
    }
3443
3444
0
  case MCK_ConstantUImm26_0:
3445
0
    switch (B) {
3446
0
    default: return false;
3447
0
    case MCK_SImm32: return true;
3448
0
    case MCK_SImm32_Relaxed: return true;
3449
0
    case MCK_UImm32_Coerced: return true;
3450
0
    }
3451
3452
0
  case MCK_SImm32:
3453
0
    switch (B) {
3454
0
    default: return false;
3455
0
    case MCK_SImm32_Relaxed: return true;
3456
0
    case MCK_UImm32_Coerced: return true;
3457
0
    }
3458
3459
0
  case MCK_SImm32_Relaxed:
3460
0
    return B == MCK_UImm32_Coerced;
3461
0
  }
3462
0
}
3463
3464
0
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
3465
0
  MipsOperand &Operand = (MipsOperand &)GOp;
3466
0
  if (Kind == InvalidMatchClass)
3467
0
    return MCTargetAsmParser::Match_InvalidOperand;
3468
3469
0
  if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)
3470
0
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
3471
0
             MCTargetAsmParser::Match_Success :
3472
0
             MCTargetAsmParser::Match_InvalidOperand;
3473
3474
0
  switch (Kind) {
3475
0
  default: break;
3476
  // 'ACC64DSPAsmReg' class
3477
0
  case MCK_ACC64DSPAsmReg: {
3478
0
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3479
0
    if (DP.isMatch())
3480
0
      return MCTargetAsmParser::Match_Success;
3481
0
    break;
3482
0
    }
3483
  // 'AFGR64AsmReg' class
3484
0
  case MCK_AFGR64AsmReg: {
3485
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3486
0
    if (DP.isMatch())
3487
0
      return MCTargetAsmParser::Match_Success;
3488
0
    break;
3489
0
    }
3490
  // 'CCRAsmReg' class
3491
0
  case MCK_CCRAsmReg: {
3492
0
    DiagnosticPredicate DP(Operand.isCCRAsmReg());
3493
0
    if (DP.isMatch())
3494
0
      return MCTargetAsmParser::Match_Success;
3495
0
    break;
3496
0
    }
3497
  // 'COP0AsmReg' class
3498
0
  case MCK_COP0AsmReg: {
3499
0
    DiagnosticPredicate DP(Operand.isCOP0AsmReg());
3500
0
    if (DP.isMatch())
3501
0
      return MCTargetAsmParser::Match_Success;
3502
0
    break;
3503
0
    }
3504
  // 'COP2AsmReg' class
3505
0
  case MCK_COP2AsmReg: {
3506
0
    DiagnosticPredicate DP(Operand.isCOP2AsmReg());
3507
0
    if (DP.isMatch())
3508
0
      return MCTargetAsmParser::Match_Success;
3509
0
    break;
3510
0
    }
3511
  // 'COP3AsmReg' class
3512
0
  case MCK_COP3AsmReg: {
3513
0
    DiagnosticPredicate DP(Operand.isCOP3AsmReg());
3514
0
    if (DP.isMatch())
3515
0
      return MCTargetAsmParser::Match_Success;
3516
0
    break;
3517
0
    }
3518
  // 'FCCAsmReg' class
3519
0
  case MCK_FCCAsmReg: {
3520
0
    DiagnosticPredicate DP(Operand.isFCCAsmReg());
3521
0
    if (DP.isMatch())
3522
0
      return MCTargetAsmParser::Match_Success;
3523
0
    break;
3524
0
    }
3525
  // 'FGR32AsmReg' class
3526
0
  case MCK_FGR32AsmReg: {
3527
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3528
0
    if (DP.isMatch())
3529
0
      return MCTargetAsmParser::Match_Success;
3530
0
    break;
3531
0
    }
3532
  // 'FGR64AsmReg' class
3533
0
  case MCK_FGR64AsmReg: {
3534
0
    DiagnosticPredicate DP(Operand.isFGRAsmReg());
3535
0
    if (DP.isMatch())
3536
0
      return MCTargetAsmParser::Match_Success;
3537
0
    break;
3538
0
    }
3539
  // 'GPR32AsmReg' class
3540
0
  case MCK_GPR32AsmReg: {
3541
0
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3542
0
    if (DP.isMatch())
3543
0
      return MCTargetAsmParser::Match_Success;
3544
0
    break;
3545
0
    }
3546
  // 'GPR32NonZeroAsmReg' class
3547
0
  case MCK_GPR32NonZeroAsmReg: {
3548
0
    DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg());
3549
0
    if (DP.isMatch())
3550
0
      return MCTargetAsmParser::Match_Success;
3551
0
    break;
3552
0
    }
3553
  // 'GPR32ZeroAsmReg' class
3554
0
  case MCK_GPR32ZeroAsmReg: {
3555
0
    DiagnosticPredicate DP(Operand.isGPRZeroAsmReg());
3556
0
    if (DP.isMatch())
3557
0
      return MCTargetAsmParser::Match_Success;
3558
0
    break;
3559
0
    }
3560
  // 'GPR64AsmReg' class
3561
0
  case MCK_GPR64AsmReg: {
3562
0
    DiagnosticPredicate DP(Operand.isGPRAsmReg());
3563
0
    if (DP.isMatch())
3564
0
      return MCTargetAsmParser::Match_Success;
3565
0
    break;
3566
0
    }
3567
  // 'GPRMM16AsmReg' class
3568
0
  case MCK_GPRMM16AsmReg: {
3569
0
    DiagnosticPredicate DP(Operand.isMM16AsmReg());
3570
0
    if (DP.isMatch())
3571
0
      return MCTargetAsmParser::Match_Success;
3572
0
    break;
3573
0
    }
3574
  // 'GPRMM16AsmRegMoveP' class
3575
0
  case MCK_GPRMM16AsmRegMoveP: {
3576
0
    DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP());
3577
0
    if (DP.isMatch())
3578
0
      return MCTargetAsmParser::Match_Success;
3579
0
    break;
3580
0
    }
3581
  // 'GPRMM16AsmRegMovePPairFirst' class
3582
0
  case MCK_GPRMM16AsmRegMovePPairFirst: {
3583
0
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairFirst());
3584
0
    if (DP.isMatch())
3585
0
      return MCTargetAsmParser::Match_Success;
3586
0
    break;
3587
0
    }
3588
  // 'GPRMM16AsmRegMovePPairSecond' class
3589
0
  case MCK_GPRMM16AsmRegMovePPairSecond: {
3590
0
    DiagnosticPredicate DP(Operand.isMM16AsmRegMovePPairSecond());
3591
0
    if (DP.isMatch())
3592
0
      return MCTargetAsmParser::Match_Success;
3593
0
    break;
3594
0
    }
3595
  // 'GPRMM16AsmRegZero' class
3596
0
  case MCK_GPRMM16AsmRegZero: {
3597
0
    DiagnosticPredicate DP(Operand.isMM16AsmRegZero());
3598
0
    if (DP.isMatch())
3599
0
      return MCTargetAsmParser::Match_Success;
3600
0
    break;
3601
0
    }
3602
  // 'HI32DSPAsmReg' class
3603
0
  case MCK_HI32DSPAsmReg: {
3604
0
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3605
0
    if (DP.isMatch())
3606
0
      return MCTargetAsmParser::Match_Success;
3607
0
    break;
3608
0
    }
3609
  // 'HWRegsAsmReg' class
3610
0
  case MCK_HWRegsAsmReg: {
3611
0
    DiagnosticPredicate DP(Operand.isHWRegsAsmReg());
3612
0
    if (DP.isMatch())
3613
0
      return MCTargetAsmParser::Match_Success;
3614
0
    break;
3615
0
    }
3616
  // 'Imm' class
3617
0
  case MCK_Imm: {
3618
0
    DiagnosticPredicate DP(Operand.isImm());
3619
0
    if (DP.isMatch())
3620
0
      return MCTargetAsmParser::Match_Success;
3621
0
    break;
3622
0
    }
3623
  // 'LO32DSPAsmReg' class
3624
0
  case MCK_LO32DSPAsmReg: {
3625
0
    DiagnosticPredicate DP(Operand.isACCAsmReg());
3626
0
    if (DP.isMatch())
3627
0
      return MCTargetAsmParser::Match_Success;
3628
0
    break;
3629
0
    }
3630
  // 'MSA128AsmReg' class
3631
0
  case MCK_MSA128AsmReg: {
3632
0
    DiagnosticPredicate DP(Operand.isMSA128AsmReg());
3633
0
    if (DP.isMatch())
3634
0
      return MCTargetAsmParser::Match_Success;
3635
0
    break;
3636
0
    }
3637
  // 'MSACtrlAsmReg' class
3638
0
  case MCK_MSACtrlAsmReg: {
3639
0
    DiagnosticPredicate DP(Operand.isMSACtrlAsmReg());
3640
0
    if (DP.isMatch())
3641
0
      return MCTargetAsmParser::Match_Success;
3642
0
    break;
3643
0
    }
3644
  // 'MicroMipsMemGP' class
3645
0
  case MCK_MicroMipsMemGP: {
3646
0
    DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>());
3647
0
    if (DP.isMatch())
3648
0
      return MCTargetAsmParser::Match_Success;
3649
0
    break;
3650
0
    }
3651
  // 'MicroMipsMem' class
3652
0
  case MCK_MicroMipsMem: {
3653
0
    DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base());
3654
0
    if (DP.isMatch())
3655
0
      return MCTargetAsmParser::Match_Success;
3656
0
    break;
3657
0
    }
3658
  // 'MicroMipsMemSP' class
3659
0
  case MCK_MicroMipsMemSP: {
3660
0
    DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>());
3661
0
    if (DP.isMatch())
3662
0
      return MCTargetAsmParser::Match_Success;
3663
0
    break;
3664
0
    }
3665
  // 'InvNum' class
3666
0
  case MCK_InvNum: {
3667
0
    DiagnosticPredicate DP(Operand.isInvNum());
3668
0
    if (DP.isMatch())
3669
0
      return MCTargetAsmParser::Match_Success;
3670
0
    break;
3671
0
    }
3672
  // 'JumpTarget' class
3673
0
  case MCK_JumpTarget: {
3674
0
    DiagnosticPredicate DP(Operand.isImm());
3675
0
    if (DP.isMatch())
3676
0
      return MCTargetAsmParser::Match_Success;
3677
0
    break;
3678
0
    }
3679
  // 'MemOffsetSimmPtr' class
3680
0
  case MCK_MemOffsetSimmPtr: {
3681
0
    DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset());
3682
0
    if (DP.isMatch())
3683
0
      return MCTargetAsmParser::Match_Success;
3684
0
    if (DP.isNearMatch())
3685
0
      return MipsAsmParser::Match_MemSImmPtr;
3686
0
    break;
3687
0
    }
3688
  // 'MemOffsetUimm4' class
3689
0
  case MCK_MemOffsetUimm4: {
3690
0
    DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>());
3691
0
    if (DP.isMatch())
3692
0
      return MCTargetAsmParser::Match_Success;
3693
0
    break;
3694
0
    }
3695
  // 'MemOffsetSimm9_0' class
3696
0
  case MCK_MemOffsetSimm9_0: {
3697
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9, 0>());
3698
0
    if (DP.isMatch())
3699
0
      return MCTargetAsmParser::Match_Success;
3700
0
    if (DP.isNearMatch())
3701
0
      return MipsAsmParser::Match_MemSImm9;
3702
0
    break;
3703
0
    }
3704
  // 'MemOffsetSimm10_0' class
3705
0
  case MCK_MemOffsetSimm10_0: {
3706
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 0>());
3707
0
    if (DP.isMatch())
3708
0
      return MCTargetAsmParser::Match_Success;
3709
0
    if (DP.isNearMatch())
3710
0
      return MipsAsmParser::Match_MemSImm10;
3711
0
    break;
3712
0
    }
3713
  // 'MemOffsetSimm11_0' class
3714
0
  case MCK_MemOffsetSimm11_0: {
3715
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11, 0>());
3716
0
    if (DP.isMatch())
3717
0
      return MCTargetAsmParser::Match_Success;
3718
0
    if (DP.isNearMatch())
3719
0
      return MipsAsmParser::Match_MemSImm11;
3720
0
    break;
3721
0
    }
3722
  // 'MemOffsetSimm12_0' class
3723
0
  case MCK_MemOffsetSimm12_0: {
3724
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12, 0>());
3725
0
    if (DP.isMatch())
3726
0
      return MCTargetAsmParser::Match_Success;
3727
0
    if (DP.isNearMatch())
3728
0
      return MipsAsmParser::Match_MemSImm12;
3729
0
    break;
3730
0
    }
3731
  // 'MemOffsetSimm16_0' class
3732
0
  case MCK_MemOffsetSimm16_0: {
3733
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16, 0>());
3734
0
    if (DP.isMatch())
3735
0
      return MCTargetAsmParser::Match_Success;
3736
0
    if (DP.isNearMatch())
3737
0
      return MipsAsmParser::Match_MemSImm16;
3738
0
    break;
3739
0
    }
3740
  // 'MemOffsetSimm10_1' class
3741
0
  case MCK_MemOffsetSimm10_1: {
3742
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>());
3743
0
    if (DP.isMatch())
3744
0
      return MCTargetAsmParser::Match_Success;
3745
0
    if (DP.isNearMatch())
3746
0
      return MipsAsmParser::Match_MemSImm10Lsl1;
3747
0
    break;
3748
0
    }
3749
  // 'MemOffsetSimm10_2' class
3750
0
  case MCK_MemOffsetSimm10_2: {
3751
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>());
3752
0
    if (DP.isMatch())
3753
0
      return MCTargetAsmParser::Match_Success;
3754
0
    if (DP.isNearMatch())
3755
0
      return MipsAsmParser::Match_MemSImm10Lsl2;
3756
0
    break;
3757
0
    }
3758
  // 'MemOffsetSimm10_3' class
3759
0
  case MCK_MemOffsetSimm10_3: {
3760
0
    DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>());
3761
0
    if (DP.isMatch())
3762
0
      return MCTargetAsmParser::Match_Success;
3763
0
    if (DP.isNearMatch())
3764
0
      return MipsAsmParser::Match_MemSImm10Lsl3;
3765
0
    break;
3766
0
    }
3767
  // 'Mem' class
3768
0
  case MCK_Mem: {
3769
0
    DiagnosticPredicate DP(Operand.isMem());
3770
0
    if (DP.isMatch())
3771
0
      return MCTargetAsmParser::Match_Success;
3772
0
    break;
3773
0
    }
3774
  // 'RegList16' class
3775
0
  case MCK_RegList16: {
3776
0
    DiagnosticPredicate DP(Operand.isRegList16());
3777
0
    if (DP.isMatch())
3778
0
      return MCTargetAsmParser::Match_Success;
3779
0
    break;
3780
0
    }
3781
  // 'RegList' class
3782
0
  case MCK_RegList: {
3783
0
    DiagnosticPredicate DP(Operand.isRegList());
3784
0
    if (DP.isMatch())
3785
0
      return MCTargetAsmParser::Match_Success;
3786
0
    break;
3787
0
    }
3788
  // 'Simm19_Lsl2' class
3789
0
  case MCK_Simm19_Lsl2: {
3790
0
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
3791
0
    if (DP.isMatch())
3792
0
      return MCTargetAsmParser::Match_Success;
3793
0
    if (DP.isNearMatch())
3794
0
      return MipsAsmParser::Match_SImm19_Lsl2;
3795
0
    break;
3796
0
    }
3797
  // 'StrictlyAFGR64AsmReg' class
3798
0
  case MCK_StrictlyAFGR64AsmReg: {
3799
0
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3800
0
    if (DP.isMatch())
3801
0
      return MCTargetAsmParser::Match_Success;
3802
0
    break;
3803
0
    }
3804
  // 'StrictlyFGR32AsmReg' class
3805
0
  case MCK_StrictlyFGR32AsmReg: {
3806
0
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3807
0
    if (DP.isMatch())
3808
0
      return MCTargetAsmParser::Match_Success;
3809
0
    break;
3810
0
    }
3811
  // 'StrictlyFGR64AsmReg' class
3812
0
  case MCK_StrictlyFGR64AsmReg: {
3813
0
    DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg());
3814
0
    if (DP.isMatch())
3815
0
      return MCTargetAsmParser::Match_Success;
3816
0
    break;
3817
0
    }
3818
  // 'ConstantImmz' class
3819
0
  case MCK_ConstantImmz: {
3820
0
    DiagnosticPredicate DP(Operand.isConstantImmz());
3821
0
    if (DP.isMatch())
3822
0
      return MCTargetAsmParser::Match_Success;
3823
0
    if (DP.isNearMatch())
3824
0
      return MipsAsmParser::Match_Immz;
3825
0
    break;
3826
0
    }
3827
  // 'ConstantUImm1_0' class
3828
0
  case MCK_ConstantUImm1_0: {
3829
0
    DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>());
3830
0
    if (DP.isMatch())
3831
0
      return MCTargetAsmParser::Match_Success;
3832
0
    if (DP.isNearMatch())
3833
0
      return MipsAsmParser::Match_UImm1_0;
3834
0
    break;
3835
0
    }
3836
  // 'ConstantUImm2_0' class
3837
0
  case MCK_ConstantUImm2_0: {
3838
0
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>());
3839
0
    if (DP.isMatch())
3840
0
      return MCTargetAsmParser::Match_Success;
3841
0
    if (DP.isNearMatch())
3842
0
      return MipsAsmParser::Match_UImm2_0;
3843
0
    break;
3844
0
    }
3845
  // 'ConstantUImm2_1' class
3846
0
  case MCK_ConstantUImm2_1: {
3847
0
    DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>());
3848
0
    if (DP.isMatch())
3849
0
      return MCTargetAsmParser::Match_Success;
3850
0
    if (DP.isNearMatch())
3851
0
      return MipsAsmParser::Match_UImm2_1;
3852
0
    break;
3853
0
    }
3854
  // 'ConstantUImm3_0' class
3855
0
  case MCK_ConstantUImm3_0: {
3856
0
    DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>());
3857
0
    if (DP.isMatch())
3858
0
      return MCTargetAsmParser::Match_Success;
3859
0
    if (DP.isNearMatch())
3860
0
      return MipsAsmParser::Match_UImm3_0;
3861
0
    break;
3862
0
    }
3863
  // 'ConstantSImm4_0' class
3864
0
  case MCK_ConstantSImm4_0: {
3865
0
    DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>());
3866
0
    if (DP.isMatch())
3867
0
      return MCTargetAsmParser::Match_Success;
3868
0
    if (DP.isNearMatch())
3869
0
      return MipsAsmParser::Match_SImm4_0;
3870
0
    break;
3871
0
    }
3872
  // 'ConstantUImm4_0' class
3873
0
  case MCK_ConstantUImm4_0: {
3874
0
    DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>());
3875
0
    if (DP.isMatch())
3876
0
      return MCTargetAsmParser::Match_Success;
3877
0
    if (DP.isNearMatch())
3878
0
      return MipsAsmParser::Match_UImm4_0;
3879
0
    break;
3880
0
    }
3881
  // 'ConstantSImm5_0' class
3882
0
  case MCK_ConstantSImm5_0: {
3883
0
    DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>());
3884
0
    if (DP.isMatch())
3885
0
      return MCTargetAsmParser::Match_Success;
3886
0
    if (DP.isNearMatch())
3887
0
      return MipsAsmParser::Match_SImm5_0;
3888
0
    break;
3889
0
    }
3890
  // 'ConstantUImm5_0' class
3891
0
  case MCK_ConstantUImm5_0: {
3892
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3893
0
    if (DP.isMatch())
3894
0
      return MCTargetAsmParser::Match_Success;
3895
0
    if (DP.isNearMatch())
3896
0
      return MipsAsmParser::Match_UImm5_0;
3897
0
    break;
3898
0
    }
3899
  // 'ConstantUImm5_1' class
3900
0
  case MCK_ConstantUImm5_1: {
3901
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3902
0
    if (DP.isMatch())
3903
0
      return MCTargetAsmParser::Match_Success;
3904
0
    if (DP.isNearMatch())
3905
0
      return MipsAsmParser::Match_UImm5_1;
3906
0
    break;
3907
0
    }
3908
  // 'ConstantUImm5_Plus1_Report_UImm6' class
3909
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6: {
3910
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>());
3911
0
    if (DP.isMatch())
3912
0
      return MCTargetAsmParser::Match_Success;
3913
0
    if (DP.isNearMatch())
3914
0
      return MipsAsmParser::Match_UImm5_1;
3915
0
    break;
3916
0
    }
3917
  // 'ConstantUImm5_32_Norm' class
3918
0
  case MCK_ConstantUImm5_32_Norm: {
3919
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3920
0
    if (DP.isMatch())
3921
0
      return MCTargetAsmParser::Match_Success;
3922
0
    if (DP.isNearMatch())
3923
0
      return MipsAsmParser::Match_UImm5_32;
3924
0
    break;
3925
0
    }
3926
  // 'ConstantUImm5_32' class
3927
0
  case MCK_ConstantUImm5_32: {
3928
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>());
3929
0
    if (DP.isMatch())
3930
0
      return MCTargetAsmParser::Match_Success;
3931
0
    if (DP.isNearMatch())
3932
0
      return MipsAsmParser::Match_UImm5_32;
3933
0
    break;
3934
0
    }
3935
  // 'ConstantUImm5_0_Report_UImm6' class
3936
0
  case MCK_ConstantUImm5_0_Report_UImm6: {
3937
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>());
3938
0
    if (DP.isMatch())
3939
0
      return MCTargetAsmParser::Match_Success;
3940
0
    if (DP.isNearMatch())
3941
0
      return MipsAsmParser::Match_UImm5_0_Report_UImm6;
3942
0
    break;
3943
0
    }
3944
  // 'ConstantUImm5_33' class
3945
0
  case MCK_ConstantUImm5_33: {
3946
0
    DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>());
3947
0
    if (DP.isMatch())
3948
0
      return MCTargetAsmParser::Match_Success;
3949
0
    if (DP.isNearMatch())
3950
0
      return MipsAsmParser::Match_UImm5_33;
3951
0
    break;
3952
0
    }
3953
  // 'ConstantUImmRange2_64' class
3954
0
  case MCK_ConstantUImmRange2_64: {
3955
0
    DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>());
3956
0
    if (DP.isMatch())
3957
0
      return MCTargetAsmParser::Match_Success;
3958
0
    if (DP.isNearMatch())
3959
0
      return MipsAsmParser::Match_UImmRange2_64;
3960
0
    break;
3961
0
    }
3962
  // 'UImm5Lsl2' class
3963
0
  case MCK_UImm5Lsl2: {
3964
0
    DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>());
3965
0
    if (DP.isMatch())
3966
0
      return MCTargetAsmParser::Match_Success;
3967
0
    if (DP.isNearMatch())
3968
0
      return MipsAsmParser::Match_UImm5_Lsl2;
3969
0
    break;
3970
0
    }
3971
  // 'ConstantSImm6_0' class
3972
0
  case MCK_ConstantSImm6_0: {
3973
0
    DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>());
3974
0
    if (DP.isMatch())
3975
0
      return MCTargetAsmParser::Match_Success;
3976
0
    if (DP.isNearMatch())
3977
0
      return MipsAsmParser::Match_SImm6_0;
3978
0
    break;
3979
0
    }
3980
  // 'ConstantUImm6_0' class
3981
0
  case MCK_ConstantUImm6_0: {
3982
0
    DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>());
3983
0
    if (DP.isMatch())
3984
0
      return MCTargetAsmParser::Match_Success;
3985
0
    if (DP.isNearMatch())
3986
0
      return MipsAsmParser::Match_UImm6_0;
3987
0
    break;
3988
0
    }
3989
  // 'UImm6Lsl2' class
3990
0
  case MCK_UImm6Lsl2: {
3991
0
    DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>());
3992
0
    if (DP.isMatch())
3993
0
      return MCTargetAsmParser::Match_Success;
3994
0
    if (DP.isNearMatch())
3995
0
      return MipsAsmParser::Match_UImm6_Lsl2;
3996
0
    break;
3997
0
    }
3998
  // 'ConstantUImm7_0' class
3999
0
  case MCK_ConstantUImm7_0: {
4000
0
    DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>());
4001
0
    if (DP.isMatch())
4002
0
      return MCTargetAsmParser::Match_Success;
4003
0
    if (DP.isNearMatch())
4004
0
      return MipsAsmParser::Match_UImm7_0;
4005
0
    break;
4006
0
    }
4007
  // 'UImm7_N1' class
4008
0
  case MCK_UImm7_N1: {
4009
0
    DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>());
4010
0
    if (DP.isMatch())
4011
0
      return MCTargetAsmParser::Match_Success;
4012
0
    if (DP.isNearMatch())
4013
0
      return MipsAsmParser::Match_UImm7_N1;
4014
0
    break;
4015
0
    }
4016
  // 'ConstantUImm8_0' class
4017
0
  case MCK_ConstantUImm8_0: {
4018
0
    DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>());
4019
0
    if (DP.isMatch())
4020
0
      return MCTargetAsmParser::Match_Success;
4021
0
    if (DP.isNearMatch())
4022
0
      return MipsAsmParser::Match_UImm8_0;
4023
0
    break;
4024
0
    }
4025
  // 'SImm7Lsl2' class
4026
0
  case MCK_SImm7Lsl2: {
4027
0
    DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>());
4028
0
    if (DP.isMatch())
4029
0
      return MCTargetAsmParser::Match_Success;
4030
0
    if (DP.isNearMatch())
4031
0
      return MipsAsmParser::Match_SImm7_Lsl2;
4032
0
    break;
4033
0
    }
4034
  // 'ConstantSImm9_0' class
4035
0
  case MCK_ConstantSImm9_0: {
4036
0
    DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>());
4037
0
    if (DP.isMatch())
4038
0
      return MCTargetAsmParser::Match_Success;
4039
0
    if (DP.isNearMatch())
4040
0
      return MipsAsmParser::Match_SImm9_0;
4041
0
    break;
4042
0
    }
4043
  // 'ConstantSImm10_0' class
4044
0
  case MCK_ConstantSImm10_0: {
4045
0
    DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>());
4046
0
    if (DP.isMatch())
4047
0
      return MCTargetAsmParser::Match_Success;
4048
0
    if (DP.isNearMatch())
4049
0
      return MipsAsmParser::Match_SImm10_0;
4050
0
    break;
4051
0
    }
4052
  // 'ConstantUImm10_0' class
4053
0
  case MCK_ConstantUImm10_0: {
4054
0
    DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>());
4055
0
    if (DP.isMatch())
4056
0
      return MCTargetAsmParser::Match_Success;
4057
0
    if (DP.isNearMatch())
4058
0
      return MipsAsmParser::Match_UImm10_0;
4059
0
    break;
4060
0
    }
4061
  // 'SImm10Lsl1' class
4062
0
  case MCK_SImm10Lsl1: {
4063
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>());
4064
0
    if (DP.isMatch())
4065
0
      return MCTargetAsmParser::Match_Success;
4066
0
    if (DP.isNearMatch())
4067
0
      return MipsAsmParser::Match_SImm10_Lsl1;
4068
0
    break;
4069
0
    }
4070
  // 'ConstantSImm11_0' class
4071
0
  case MCK_ConstantSImm11_0: {
4072
0
    DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>());
4073
0
    if (DP.isMatch())
4074
0
      return MCTargetAsmParser::Match_Success;
4075
0
    if (DP.isNearMatch())
4076
0
      return MipsAsmParser::Match_SImm11_0;
4077
0
    break;
4078
0
    }
4079
  // 'SImm10Lsl2' class
4080
0
  case MCK_SImm10Lsl2: {
4081
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>());
4082
0
    if (DP.isMatch())
4083
0
      return MCTargetAsmParser::Match_Success;
4084
0
    if (DP.isNearMatch())
4085
0
      return MipsAsmParser::Match_SImm10_Lsl2;
4086
0
    break;
4087
0
    }
4088
  // 'SImm10Lsl3' class
4089
0
  case MCK_SImm10Lsl3: {
4090
0
    DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>());
4091
0
    if (DP.isMatch())
4092
0
      return MCTargetAsmParser::Match_Success;
4093
0
    if (DP.isNearMatch())
4094
0
      return MipsAsmParser::Match_SImm10_Lsl3;
4095
0
    break;
4096
0
    }
4097
  // 'SImm16' class
4098
0
  case MCK_SImm16: {
4099
0
    DiagnosticPredicate DP(Operand.isSImm<16>());
4100
0
    if (DP.isMatch())
4101
0
      return MCTargetAsmParser::Match_Success;
4102
0
    if (DP.isNearMatch())
4103
0
      return MipsAsmParser::Match_SImm16;
4104
0
    break;
4105
0
    }
4106
  // 'SImm16_Relaxed' class
4107
0
  case MCK_SImm16_Relaxed: {
4108
0
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4109
0
    if (DP.isMatch())
4110
0
      return MCTargetAsmParser::Match_Success;
4111
0
    if (DP.isNearMatch())
4112
0
      return MipsAsmParser::Match_SImm16_Relaxed;
4113
0
    break;
4114
0
    }
4115
  // 'UImm16_AltRelaxed' class
4116
0
  case MCK_UImm16_AltRelaxed: {
4117
0
    DiagnosticPredicate DP(Operand.isUImm<16>());
4118
0
    if (DP.isMatch())
4119
0
      return MCTargetAsmParser::Match_Success;
4120
0
    if (DP.isNearMatch())
4121
0
      return MipsAsmParser::Match_UImm16_AltRelaxed;
4122
0
    break;
4123
0
    }
4124
  // 'UImm16' class
4125
0
  case MCK_UImm16: {
4126
0
    DiagnosticPredicate DP(Operand.isUImm<16>());
4127
0
    if (DP.isMatch())
4128
0
      return MCTargetAsmParser::Match_Success;
4129
0
    if (DP.isNearMatch())
4130
0
      return MipsAsmParser::Match_UImm16;
4131
0
    break;
4132
0
    }
4133
  // 'SImm19Lsl2' class
4134
0
  case MCK_SImm19Lsl2: {
4135
0
    DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>());
4136
0
    if (DP.isMatch())
4137
0
      return MCTargetAsmParser::Match_Success;
4138
0
    if (DP.isNearMatch())
4139
0
      return MipsAsmParser::Match_SImm19_Lsl2;
4140
0
    break;
4141
0
    }
4142
  // 'UImm16_Relaxed' class
4143
0
  case MCK_UImm16_Relaxed: {
4144
0
    DiagnosticPredicate DP(Operand.isAnyImm<16>());
4145
0
    if (DP.isMatch())
4146
0
      return MCTargetAsmParser::Match_Success;
4147
0
    if (DP.isNearMatch())
4148
0
      return MipsAsmParser::Match_UImm16_Relaxed;
4149
0
    break;
4150
0
    }
4151
  // 'ConstantUImm20_0' class
4152
0
  case MCK_ConstantUImm20_0: {
4153
0
    DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>());
4154
0
    if (DP.isMatch())
4155
0
      return MCTargetAsmParser::Match_Success;
4156
0
    if (DP.isNearMatch())
4157
0
      return MipsAsmParser::Match_UImm20_0;
4158
0
    break;
4159
0
    }
4160
  // 'ConstantUImm26_0' class
4161
0
  case MCK_ConstantUImm26_0: {
4162
0
    DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>());
4163
0
    if (DP.isMatch())
4164
0
      return MCTargetAsmParser::Match_Success;
4165
0
    if (DP.isNearMatch())
4166
0
      return MipsAsmParser::Match_UImm26_0;
4167
0
    break;
4168
0
    }
4169
  // 'SImm32' class
4170
0
  case MCK_SImm32: {
4171
0
    DiagnosticPredicate DP(Operand.isSImm<32>());
4172
0
    if (DP.isMatch())
4173
0
      return MCTargetAsmParser::Match_Success;
4174
0
    if (DP.isNearMatch())
4175
0
      return MipsAsmParser::Match_SImm32;
4176
0
    break;
4177
0
    }
4178
  // 'SImm32_Relaxed' class
4179
0
  case MCK_SImm32_Relaxed: {
4180
0
    DiagnosticPredicate DP(Operand.isAnyImm<33>());
4181
0
    if (DP.isMatch())
4182
0
      return MCTargetAsmParser::Match_Success;
4183
0
    if (DP.isNearMatch())
4184
0
      return MipsAsmParser::Match_SImm32_Relaxed;
4185
0
    break;
4186
0
    }
4187
  // 'UImm32_Coerced' class
4188
0
  case MCK_UImm32_Coerced: {
4189
0
    DiagnosticPredicate DP(Operand.isSImm<33>());
4190
0
    if (DP.isMatch())
4191
0
      return MCTargetAsmParser::Match_Success;
4192
0
    if (DP.isNearMatch())
4193
0
      return MipsAsmParser::Match_UImm32_Coerced;
4194
0
    break;
4195
0
    }
4196
0
  } // end switch (Kind)
4197
4198
0
  if (Operand.isReg()) {
4199
0
    MatchClassKind OpKind;
4200
0
    switch (Operand.getReg()) {
4201
0
    default: OpKind = InvalidMatchClass; break;
4202
0
    case Mips::ZERO: OpKind = MCK_GPR32ZERO; break;
4203
0
    case Mips::AT: OpKind = MCK_GPR32NONZERO; break;
4204
0
    case Mips::V0: OpKind = MCK_Reg11; break;
4205
0
    case Mips::V1: OpKind = MCK_Reg11; break;
4206
0
    case Mips::A0: OpKind = MCK_GPRMM16MovePPairFirst; break;
4207
0
    case Mips::A1: OpKind = MCK_Reg13; break;
4208
0
    case Mips::A2: OpKind = MCK_Reg13; break;
4209
0
    case Mips::A3: OpKind = MCK_Reg14; break;
4210
0
    case Mips::T0: OpKind = MCK_GPR32NONZERO; break;
4211
0
    case Mips::T1: OpKind = MCK_GPR32NONZERO; break;
4212
0
    case Mips::T2: OpKind = MCK_GPR32NONZERO; break;
4213
0
    case Mips::T3: OpKind = MCK_GPR32NONZERO; break;
4214
0
    case Mips::T4: OpKind = MCK_GPR32NONZERO; break;
4215
0
    case Mips::T5: OpKind = MCK_GPR32NONZERO; break;
4216
0
    case Mips::T6: OpKind = MCK_GPR32NONZERO; break;
4217
0
    case Mips::T7: OpKind = MCK_GPR32NONZERO; break;
4218
0
    case Mips::S0: OpKind = MCK_Reg9; break;
4219
0
    case Mips::S1: OpKind = MCK_Reg11; break;
4220
0
    case Mips::S2: OpKind = MCK_Reg10; break;
4221
0
    case Mips::S3: OpKind = MCK_Reg10; break;
4222
0
    case Mips::S4: OpKind = MCK_Reg10; break;
4223
0
    case Mips::S5: OpKind = MCK_GPRMM16MovePPairSecond; break;
4224
0
    case Mips::S6: OpKind = MCK_GPRMM16MovePPairSecond; break;
4225
0
    case Mips::S7: OpKind = MCK_GPR32NONZERO; break;
4226
0
    case Mips::T8: OpKind = MCK_GPR32NONZERO; break;
4227
0
    case Mips::T9: OpKind = MCK_GPR32NONZERO; break;
4228
0
    case Mips::K0: OpKind = MCK_GPR32NONZERO; break;
4229
0
    case Mips::K1: OpKind = MCK_GPR32NONZERO; break;
4230
0
    case Mips::GP: OpKind = MCK_GP32; break;
4231
0
    case Mips::SP: OpKind = MCK_CPUSPReg; break;
4232
0
    case Mips::FP: OpKind = MCK_GPR32NONZERO; break;
4233
0
    case Mips::RA: OpKind = MCK_CPURAReg; break;
4234
0
    case Mips::ZERO_64: OpKind = MCK_Reg19; break;
4235
0
    case Mips::AT_64: OpKind = MCK_Reg24; break;
4236
0
    case Mips::V0_64: OpKind = MCK_Reg30; break;
4237
0
    case Mips::V1_64: OpKind = MCK_Reg30; break;
4238
0
    case Mips::A0_64: OpKind = MCK_Reg31; break;
4239
0
    case Mips::A1_64: OpKind = MCK_Reg32; break;
4240
0
    case Mips::A2_64: OpKind = MCK_Reg32; break;
4241
0
    case Mips::A3_64: OpKind = MCK_Reg33; break;
4242
0
    case Mips::T0_64: OpKind = MCK_Reg24; break;
4243
0
    case Mips::T1_64: OpKind = MCK_Reg24; break;
4244
0
    case Mips::T2_64: OpKind = MCK_Reg24; break;
4245
0
    case Mips::T3_64: OpKind = MCK_Reg24; break;
4246
0
    case Mips::T4_64: OpKind = MCK_Reg24; break;
4247
0
    case Mips::T5_64: OpKind = MCK_Reg24; break;
4248
0
    case Mips::T6_64: OpKind = MCK_Reg24; break;
4249
0
    case Mips::T7_64: OpKind = MCK_Reg24; break;
4250
0
    case Mips::S0_64: OpKind = MCK_Reg28; break;
4251
0
    case Mips::S1_64: OpKind = MCK_Reg30; break;
4252
0
    case Mips::S2_64: OpKind = MCK_Reg29; break;
4253
0
    case Mips::S3_64: OpKind = MCK_Reg29; break;
4254
0
    case Mips::S4_64: OpKind = MCK_Reg29; break;
4255
0
    case Mips::S5_64: OpKind = MCK_Reg34; break;
4256
0
    case Mips::S6_64: OpKind = MCK_Reg34; break;
4257
0
    case Mips::S7_64: OpKind = MCK_Reg24; break;
4258
0
    case Mips::T8_64: OpKind = MCK_Reg24; break;
4259
0
    case Mips::T9_64: OpKind = MCK_Reg24; break;
4260
0
    case Mips::K0_64: OpKind = MCK_Reg24; break;
4261
0
    case Mips::K1_64: OpKind = MCK_Reg24; break;
4262
0
    case Mips::GP_64: OpKind = MCK_GP64; break;
4263
0
    case Mips::SP_64: OpKind = MCK_SP64; break;
4264
0
    case Mips::FP_64: OpKind = MCK_Reg24; break;
4265
0
    case Mips::RA_64: OpKind = MCK_Reg37; break;
4266
0
    case Mips::F0: OpKind = MCK_FGR32; break;
4267
0
    case Mips::F1: OpKind = MCK_FGR32; break;
4268
0
    case Mips::F2: OpKind = MCK_FGR32; break;
4269
0
    case Mips::F3: OpKind = MCK_FGR32; break;
4270
0
    case Mips::F4: OpKind = MCK_FGR32; break;
4271
0
    case Mips::F5: OpKind = MCK_FGR32; break;
4272
0
    case Mips::F6: OpKind = MCK_FGR32; break;
4273
0
    case Mips::F7: OpKind = MCK_FGR32; break;
4274
0
    case Mips::F8: OpKind = MCK_FGR32; break;
4275
0
    case Mips::F9: OpKind = MCK_FGR32; break;
4276
0
    case Mips::F10: OpKind = MCK_FGR32; break;
4277
0
    case Mips::F11: OpKind = MCK_FGR32; break;
4278
0
    case Mips::F12: OpKind = MCK_FGR32; break;
4279
0
    case Mips::F13: OpKind = MCK_FGR32; break;
4280
0
    case Mips::F14: OpKind = MCK_FGR32; break;
4281
0
    case Mips::F15: OpKind = MCK_FGR32; break;
4282
0
    case Mips::F16: OpKind = MCK_FGR32; break;
4283
0
    case Mips::F17: OpKind = MCK_FGR32; break;
4284
0
    case Mips::F18: OpKind = MCK_FGR32; break;
4285
0
    case Mips::F19: OpKind = MCK_FGR32; break;
4286
0
    case Mips::F20: OpKind = MCK_FGR32; break;
4287
0
    case Mips::F21: OpKind = MCK_FGR32; break;
4288
0
    case Mips::F22: OpKind = MCK_FGR32; break;
4289
0
    case Mips::F23: OpKind = MCK_FGR32; break;
4290
0
    case Mips::F24: OpKind = MCK_FGR32; break;
4291
0
    case Mips::F25: OpKind = MCK_FGR32; break;
4292
0
    case Mips::F26: OpKind = MCK_FGR32; break;
4293
0
    case Mips::F27: OpKind = MCK_FGR32; break;
4294
0
    case Mips::F28: OpKind = MCK_FGR32; break;
4295
0
    case Mips::F29: OpKind = MCK_FGR32; break;
4296
0
    case Mips::F30: OpKind = MCK_FGR32; break;
4297
0
    case Mips::F31: OpKind = MCK_FGR32; break;
4298
0
    case Mips::D0: OpKind = MCK_AFGR64; break;
4299
0
    case Mips::D1: OpKind = MCK_AFGR64; break;
4300
0
    case Mips::D2: OpKind = MCK_AFGR64; break;
4301
0
    case Mips::D3: OpKind = MCK_AFGR64; break;
4302
0
    case Mips::D4: OpKind = MCK_AFGR64; break;
4303
0
    case Mips::D5: OpKind = MCK_AFGR64; break;
4304
0
    case Mips::D6: OpKind = MCK_AFGR64; break;
4305
0
    case Mips::D7: OpKind = MCK_AFGR64; break;
4306
0
    case Mips::D8: OpKind = MCK_AFGR64; break;
4307
0
    case Mips::D9: OpKind = MCK_AFGR64; break;
4308
0
    case Mips::D10: OpKind = MCK_AFGR64; break;
4309
0
    case Mips::D11: OpKind = MCK_AFGR64; break;
4310
0
    case Mips::D12: OpKind = MCK_AFGR64; break;
4311
0
    case Mips::D13: OpKind = MCK_AFGR64; break;
4312
0
    case Mips::D14: OpKind = MCK_AFGR64; break;
4313
0
    case Mips::D15: OpKind = MCK_AFGR64; break;
4314
0
    case Mips::D0_64: OpKind = MCK_FGR64; break;
4315
0
    case Mips::D1_64: OpKind = MCK_FGR64; break;
4316
0
    case Mips::D2_64: OpKind = MCK_FGR64; break;
4317
0
    case Mips::D3_64: OpKind = MCK_FGR64; break;
4318
0
    case Mips::D4_64: OpKind = MCK_FGR64; break;
4319
0
    case Mips::D5_64: OpKind = MCK_FGR64; break;
4320
0
    case Mips::D6_64: OpKind = MCK_FGR64; break;
4321
0
    case Mips::D7_64: OpKind = MCK_FGR64; break;
4322
0
    case Mips::D8_64: OpKind = MCK_FGR64; break;
4323
0
    case Mips::D9_64: OpKind = MCK_FGR64; break;
4324
0
    case Mips::D10_64: OpKind = MCK_FGR64; break;
4325
0
    case Mips::D11_64: OpKind = MCK_FGR64; break;
4326
0
    case Mips::D12_64: OpKind = MCK_FGR64; break;
4327
0
    case Mips::D13_64: OpKind = MCK_FGR64; break;
4328
0
    case Mips::D14_64: OpKind = MCK_FGR64; break;
4329
0
    case Mips::D15_64: OpKind = MCK_FGR64; break;
4330
0
    case Mips::D16_64: OpKind = MCK_FGR64; break;
4331
0
    case Mips::D17_64: OpKind = MCK_FGR64; break;
4332
0
    case Mips::D18_64: OpKind = MCK_FGR64; break;
4333
0
    case Mips::D19_64: OpKind = MCK_FGR64; break;
4334
0
    case Mips::D20_64: OpKind = MCK_FGR64; break;
4335
0
    case Mips::D21_64: OpKind = MCK_FGR64; break;
4336
0
    case Mips::D22_64: OpKind = MCK_FGR64; break;
4337
0
    case Mips::D23_64: OpKind = MCK_FGR64; break;
4338
0
    case Mips::D24_64: OpKind = MCK_FGR64; break;
4339
0
    case Mips::D25_64: OpKind = MCK_FGR64; break;
4340
0
    case Mips::D26_64: OpKind = MCK_FGR64; break;
4341
0
    case Mips::D27_64: OpKind = MCK_FGR64; break;
4342
0
    case Mips::D28_64: OpKind = MCK_FGR64; break;
4343
0
    case Mips::D29_64: OpKind = MCK_FGR64; break;
4344
0
    case Mips::D30_64: OpKind = MCK_FGR64; break;
4345
0
    case Mips::D31_64: OpKind = MCK_FGR64; break;
4346
0
    case Mips::W0: OpKind = MCK_MSA128WEvens; break;
4347
0
    case Mips::W1: OpKind = MCK_MSA128F16; break;
4348
0
    case Mips::W2: OpKind = MCK_MSA128WEvens; break;
4349
0
    case Mips::W3: OpKind = MCK_MSA128F16; break;
4350
0
    case Mips::W4: OpKind = MCK_MSA128WEvens; break;
4351
0
    case Mips::W5: OpKind = MCK_MSA128F16; break;
4352
0
    case Mips::W6: OpKind = MCK_MSA128WEvens; break;
4353
0
    case Mips::W7: OpKind = MCK_MSA128F16; break;
4354
0
    case Mips::W8: OpKind = MCK_MSA128WEvens; break;
4355
0
    case Mips::W9: OpKind = MCK_MSA128F16; break;
4356
0
    case Mips::W10: OpKind = MCK_MSA128WEvens; break;
4357
0
    case Mips::W11: OpKind = MCK_MSA128F16; break;
4358
0
    case Mips::W12: OpKind = MCK_MSA128WEvens; break;
4359
0
    case Mips::W13: OpKind = MCK_MSA128F16; break;
4360
0
    case Mips::W14: OpKind = MCK_MSA128WEvens; break;
4361
0
    case Mips::W15: OpKind = MCK_MSA128F16; break;
4362
0
    case Mips::W16: OpKind = MCK_MSA128WEvens; break;
4363
0
    case Mips::W17: OpKind = MCK_MSA128F16; break;
4364
0
    case Mips::W18: OpKind = MCK_MSA128WEvens; break;
4365
0
    case Mips::W19: OpKind = MCK_MSA128F16; break;
4366
0
    case Mips::W20: OpKind = MCK_MSA128WEvens; break;
4367
0
    case Mips::W21: OpKind = MCK_MSA128F16; break;
4368
0
    case Mips::W22: OpKind = MCK_MSA128WEvens; break;
4369
0
    case Mips::W23: OpKind = MCK_MSA128F16; break;
4370
0
    case Mips::W24: OpKind = MCK_MSA128WEvens; break;
4371
0
    case Mips::W25: OpKind = MCK_MSA128F16; break;
4372
0
    case Mips::W26: OpKind = MCK_MSA128WEvens; break;
4373
0
    case Mips::W27: OpKind = MCK_MSA128F16; break;
4374
0
    case Mips::W28: OpKind = MCK_MSA128WEvens; break;
4375
0
    case Mips::W29: OpKind = MCK_MSA128F16; break;
4376
0
    case Mips::W30: OpKind = MCK_MSA128WEvens; break;
4377
0
    case Mips::W31: OpKind = MCK_MSA128F16; break;
4378
0
    case Mips::HI0: OpKind = MCK_HI32; break;
4379
0
    case Mips::HI1: OpKind = MCK_HI32DSP; break;
4380
0
    case Mips::HI2: OpKind = MCK_HI32DSP; break;
4381
0
    case Mips::HI3: OpKind = MCK_HI32DSP; break;
4382
0
    case Mips::LO0: OpKind = MCK_LO32; break;
4383
0
    case Mips::LO1: OpKind = MCK_LO32DSP; break;
4384
0
    case Mips::LO2: OpKind = MCK_LO32DSP; break;
4385
0
    case Mips::LO3: OpKind = MCK_LO32DSP; break;
4386
0
    case Mips::HI0_64: OpKind = MCK_HI64; break;
4387
0
    case Mips::LO0_64: OpKind = MCK_LO64; break;
4388
0
    case Mips::FCR0: OpKind = MCK_CCR; break;
4389
0
    case Mips::FCR1: OpKind = MCK_CCR; break;
4390
0
    case Mips::FCR2: OpKind = MCK_CCR; break;
4391
0
    case Mips::FCR3: OpKind = MCK_CCR; break;
4392
0
    case Mips::FCR4: OpKind = MCK_CCR; break;
4393
0
    case Mips::FCR5: OpKind = MCK_CCR; break;
4394
0
    case Mips::FCR6: OpKind = MCK_CCR; break;
4395
0
    case Mips::FCR7: OpKind = MCK_CCR; break;
4396
0
    case Mips::FCR8: OpKind = MCK_CCR; break;
4397
0
    case Mips::FCR9: OpKind = MCK_CCR; break;
4398
0
    case Mips::FCR10: OpKind = MCK_CCR; break;
4399
0
    case Mips::FCR11: OpKind = MCK_CCR; break;
4400
0
    case Mips::FCR12: OpKind = MCK_CCR; break;
4401
0
    case Mips::FCR13: OpKind = MCK_CCR; break;
4402
0
    case Mips::FCR14: OpKind = MCK_CCR; break;
4403
0
    case Mips::FCR15: OpKind = MCK_CCR; break;
4404
0
    case Mips::FCR16: OpKind = MCK_CCR; break;
4405
0
    case Mips::FCR17: OpKind = MCK_CCR; break;
4406
0
    case Mips::FCR18: OpKind = MCK_CCR; break;
4407
0
    case Mips::FCR19: OpKind = MCK_CCR; break;
4408
0
    case Mips::FCR20: OpKind = MCK_CCR; break;
4409
0
    case Mips::FCR21: OpKind = MCK_CCR; break;
4410
0
    case Mips::FCR22: OpKind = MCK_CCR; break;
4411
0
    case Mips::FCR23: OpKind = MCK_CCR; break;
4412
0
    case Mips::FCR24: OpKind = MCK_CCR; break;
4413
0
    case Mips::FCR25: OpKind = MCK_CCR; break;
4414
0
    case Mips::FCR26: OpKind = MCK_CCR; break;
4415
0
    case Mips::FCR27: OpKind = MCK_CCR; break;
4416
0
    case Mips::FCR28: OpKind = MCK_CCR; break;
4417
0
    case Mips::FCR29: OpKind = MCK_CCR; break;
4418
0
    case Mips::FCR30: OpKind = MCK_CCR; break;
4419
0
    case Mips::FCR31: OpKind = MCK_CCR; break;
4420
0
    case Mips::FCC0: OpKind = MCK_FCC; break;
4421
0
    case Mips::FCC1: OpKind = MCK_FCC; break;
4422
0
    case Mips::FCC2: OpKind = MCK_FCC; break;
4423
0
    case Mips::FCC3: OpKind = MCK_FCC; break;
4424
0
    case Mips::FCC4: OpKind = MCK_FCC; break;
4425
0
    case Mips::FCC5: OpKind = MCK_FCC; break;
4426
0
    case Mips::FCC6: OpKind = MCK_FCC; break;
4427
0
    case Mips::FCC7: OpKind = MCK_FCC; break;
4428
0
    case Mips::COP00: OpKind = MCK_COP0; break;
4429
0
    case Mips::COP01: OpKind = MCK_COP0; break;
4430
0
    case Mips::COP02: OpKind = MCK_COP0; break;
4431
0
    case Mips::COP03: OpKind = MCK_COP0; break;
4432
0
    case Mips::COP04: OpKind = MCK_COP0; break;
4433
0
    case Mips::COP05: OpKind = MCK_COP0; break;
4434
0
    case Mips::COP06: OpKind = MCK_COP0; break;
4435
0
    case Mips::COP07: OpKind = MCK_COP0; break;
4436
0
    case Mips::COP08: OpKind = MCK_COP0; break;
4437
0
    case Mips::COP09: OpKind = MCK_COP0; break;
4438
0
    case Mips::COP010: OpKind = MCK_COP0; break;
4439
0
    case Mips::COP011: OpKind = MCK_COP0; break;
4440
0
    case Mips::COP012: OpKind = MCK_COP0; break;
4441
0
    case Mips::COP013: OpKind = MCK_COP0; break;
4442
0
    case Mips::COP014: OpKind = MCK_COP0; break;
4443
0
    case Mips::COP015: OpKind = MCK_COP0; break;
4444
0
    case Mips::COP016: OpKind = MCK_COP0; break;
4445
0
    case Mips::COP017: OpKind = MCK_COP0; break;
4446
0
    case Mips::COP018: OpKind = MCK_COP0; break;
4447
0
    case Mips::COP019: OpKind = MCK_COP0; break;
4448
0
    case Mips::COP020: OpKind = MCK_COP0; break;
4449
0
    case Mips::COP021: OpKind = MCK_COP0; break;
4450
0
    case Mips::COP022: OpKind = MCK_COP0; break;
4451
0
    case Mips::COP023: OpKind = MCK_COP0; break;
4452
0
    case Mips::COP024: OpKind = MCK_COP0; break;
4453
0
    case Mips::COP025: OpKind = MCK_COP0; break;
4454
0
    case Mips::COP026: OpKind = MCK_COP0; break;
4455
0
    case Mips::COP027: OpKind = MCK_COP0; break;
4456
0
    case Mips::COP028: OpKind = MCK_COP0; break;
4457
0
    case Mips::COP029: OpKind = MCK_COP0; break;
4458
0
    case Mips::COP030: OpKind = MCK_COP0; break;
4459
0
    case Mips::COP031: OpKind = MCK_COP0; break;
4460
0
    case Mips::COP20: OpKind = MCK_COP2; break;
4461
0
    case Mips::COP21: OpKind = MCK_COP2; break;
4462
0
    case Mips::COP22: OpKind = MCK_COP2; break;
4463
0
    case Mips::COP23: OpKind = MCK_COP2; break;
4464
0
    case Mips::COP24: OpKind = MCK_COP2; break;
4465
0
    case Mips::COP25: OpKind = MCK_COP2; break;
4466
0
    case Mips::COP26: OpKind = MCK_COP2; break;
4467
0
    case Mips::COP27: OpKind = MCK_COP2; break;
4468
0
    case Mips::COP28: OpKind = MCK_COP2; break;
4469
0
    case Mips::COP29: OpKind = MCK_COP2; break;
4470
0
    case Mips::COP210: OpKind = MCK_COP2; break;
4471
0
    case Mips::COP211: OpKind = MCK_COP2; break;
4472
0
    case Mips::COP212: OpKind = MCK_COP2; break;
4473
0
    case Mips::COP213: OpKind = MCK_COP2; break;
4474
0
    case Mips::COP214: OpKind = MCK_COP2; break;
4475
0
    case Mips::COP215: OpKind = MCK_COP2; break;
4476
0
    case Mips::COP216: OpKind = MCK_COP2; break;
4477
0
    case Mips::COP217: OpKind = MCK_COP2; break;
4478
0
    case Mips::COP218: OpKind = MCK_COP2; break;
4479
0
    case Mips::COP219: OpKind = MCK_COP2; break;
4480
0
    case Mips::COP220: OpKind = MCK_COP2; break;
4481
0
    case Mips::COP221: OpKind = MCK_COP2; break;
4482
0
    case Mips::COP222: OpKind = MCK_COP2; break;
4483
0
    case Mips::COP223: OpKind = MCK_COP2; break;
4484
0
    case Mips::COP224: OpKind = MCK_COP2; break;
4485
0
    case Mips::COP225: OpKind = MCK_COP2; break;
4486
0
    case Mips::COP226: OpKind = MCK_COP2; break;
4487
0
    case Mips::COP227: OpKind = MCK_COP2; break;
4488
0
    case Mips::COP228: OpKind = MCK_COP2; break;
4489
0
    case Mips::COP229: OpKind = MCK_COP2; break;
4490
0
    case Mips::COP230: OpKind = MCK_COP2; break;
4491
0
    case Mips::COP231: OpKind = MCK_COP2; break;
4492
0
    case Mips::COP30: OpKind = MCK_COP3; break;
4493
0
    case Mips::COP31: OpKind = MCK_COP3; break;
4494
0
    case Mips::COP32: OpKind = MCK_COP3; break;
4495
0
    case Mips::COP33: OpKind = MCK_COP3; break;
4496
0
    case Mips::COP34: OpKind = MCK_COP3; break;
4497
0
    case Mips::COP35: OpKind = MCK_COP3; break;
4498
0
    case Mips::COP36: OpKind = MCK_COP3; break;
4499
0
    case Mips::COP37: OpKind = MCK_COP3; break;
4500
0
    case Mips::COP38: OpKind = MCK_COP3; break;
4501
0
    case Mips::COP39: OpKind = MCK_COP3; break;
4502
0
    case Mips::COP310: OpKind = MCK_COP3; break;
4503
0
    case Mips::COP311: OpKind = MCK_COP3; break;
4504
0
    case Mips::COP312: OpKind = MCK_COP3; break;
4505
0
    case Mips::COP313: OpKind = MCK_COP3; break;
4506
0
    case Mips::COP314: OpKind = MCK_COP3; break;
4507
0
    case Mips::COP315: OpKind = MCK_COP3; break;
4508
0
    case Mips::COP316: OpKind = MCK_COP3; break;
4509
0
    case Mips::COP317: OpKind = MCK_COP3; break;
4510
0
    case Mips::COP318: OpKind = MCK_COP3; break;
4511
0
    case Mips::COP319: OpKind = MCK_COP3; break;
4512
0
    case Mips::COP320: OpKind = MCK_COP3; break;
4513
0
    case Mips::COP321: OpKind = MCK_COP3; break;
4514
0
    case Mips::COP322: OpKind = MCK_COP3; break;
4515
0
    case Mips::COP323: OpKind = MCK_COP3; break;
4516
0
    case Mips::COP324: OpKind = MCK_COP3; break;
4517
0
    case Mips::COP325: OpKind = MCK_COP3; break;
4518
0
    case Mips::COP326: OpKind = MCK_COP3; break;
4519
0
    case Mips::COP327: OpKind = MCK_COP3; break;
4520
0
    case Mips::COP328: OpKind = MCK_COP3; break;
4521
0
    case Mips::COP329: OpKind = MCK_COP3; break;
4522
0
    case Mips::COP330: OpKind = MCK_COP3; break;
4523
0
    case Mips::COP331: OpKind = MCK_COP3; break;
4524
0
    case Mips::PC: OpKind = MCK_PC; break;
4525
0
    case Mips::HWR0: OpKind = MCK_HWRegs; break;
4526
0
    case Mips::HWR1: OpKind = MCK_HWRegs; break;
4527
0
    case Mips::HWR2: OpKind = MCK_HWRegs; break;
4528
0
    case Mips::HWR3: OpKind = MCK_HWRegs; break;
4529
0
    case Mips::HWR4: OpKind = MCK_HWRegs; break;
4530
0
    case Mips::HWR5: OpKind = MCK_HWRegs; break;
4531
0
    case Mips::HWR6: OpKind = MCK_HWRegs; break;
4532
0
    case Mips::HWR7: OpKind = MCK_HWRegs; break;
4533
0
    case Mips::HWR8: OpKind = MCK_HWRegs; break;
4534
0
    case Mips::HWR9: OpKind = MCK_HWRegs; break;
4535
0
    case Mips::HWR10: OpKind = MCK_HWRegs; break;
4536
0
    case Mips::HWR11: OpKind = MCK_HWRegs; break;
4537
0
    case Mips::HWR12: OpKind = MCK_HWRegs; break;
4538
0
    case Mips::HWR13: OpKind = MCK_HWRegs; break;
4539
0
    case Mips::HWR14: OpKind = MCK_HWRegs; break;
4540
0
    case Mips::HWR15: OpKind = MCK_HWRegs; break;
4541
0
    case Mips::HWR16: OpKind = MCK_HWRegs; break;
4542
0
    case Mips::HWR17: OpKind = MCK_HWRegs; break;
4543
0
    case Mips::HWR18: OpKind = MCK_HWRegs; break;
4544
0
    case Mips::HWR19: OpKind = MCK_HWRegs; break;
4545
0
    case Mips::HWR20: OpKind = MCK_HWRegs; break;
4546
0
    case Mips::HWR21: OpKind = MCK_HWRegs; break;
4547
0
    case Mips::HWR22: OpKind = MCK_HWRegs; break;
4548
0
    case Mips::HWR23: OpKind = MCK_HWRegs; break;
4549
0
    case Mips::HWR24: OpKind = MCK_HWRegs; break;
4550
0
    case Mips::HWR25: OpKind = MCK_HWRegs; break;
4551
0
    case Mips::HWR26: OpKind = MCK_HWRegs; break;
4552
0
    case Mips::HWR27: OpKind = MCK_HWRegs; break;
4553
0
    case Mips::HWR28: OpKind = MCK_HWRegs; break;
4554
0
    case Mips::HWR29: OpKind = MCK_HWRegs; break;
4555
0
    case Mips::HWR30: OpKind = MCK_HWRegs; break;
4556
0
    case Mips::HWR31: OpKind = MCK_HWRegs; break;
4557
0
    case Mips::AC0: OpKind = MCK_ACC64; break;
4558
0
    case Mips::AC1: OpKind = MCK_ACC64DSP; break;
4559
0
    case Mips::AC2: OpKind = MCK_ACC64DSP; break;
4560
0
    case Mips::AC3: OpKind = MCK_ACC64DSP; break;
4561
0
    case Mips::AC0_64: OpKind = MCK_ACC128; break;
4562
0
    case Mips::DSPCCond: OpKind = MCK_DSPCC; break;
4563
0
    case Mips::MSAIR: OpKind = MCK_MSACtrl; break;
4564
0
    case Mips::MSACSR: OpKind = MCK_MSACtrl; break;
4565
0
    case Mips::MSAAccess: OpKind = MCK_MSACtrl; break;
4566
0
    case Mips::MSASave: OpKind = MCK_MSACtrl; break;
4567
0
    case Mips::MSAModify: OpKind = MCK_MSACtrl; break;
4568
0
    case Mips::MSARequest: OpKind = MCK_MSACtrl; break;
4569
0
    case Mips::MSAMap: OpKind = MCK_MSACtrl; break;
4570
0
    case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break;
4571
0
    case Mips::MSA8: OpKind = MCK_MSACtrl; break;
4572
0
    case Mips::MSA9: OpKind = MCK_MSACtrl; break;
4573
0
    case Mips::MSA10: OpKind = MCK_MSACtrl; break;
4574
0
    case Mips::MSA11: OpKind = MCK_MSACtrl; break;
4575
0
    case Mips::MSA12: OpKind = MCK_MSACtrl; break;
4576
0
    case Mips::MSA13: OpKind = MCK_MSACtrl; break;
4577
0
    case Mips::MSA14: OpKind = MCK_MSACtrl; break;
4578
0
    case Mips::MSA15: OpKind = MCK_MSACtrl; break;
4579
0
    case Mips::MSA16: OpKind = MCK_MSACtrl; break;
4580
0
    case Mips::MSA17: OpKind = MCK_MSACtrl; break;
4581
0
    case Mips::MSA18: OpKind = MCK_MSACtrl; break;
4582
0
    case Mips::MSA19: OpKind = MCK_MSACtrl; break;
4583
0
    case Mips::MSA20: OpKind = MCK_MSACtrl; break;
4584
0
    case Mips::MSA21: OpKind = MCK_MSACtrl; break;
4585
0
    case Mips::MSA22: OpKind = MCK_MSACtrl; break;
4586
0
    case Mips::MSA23: OpKind = MCK_MSACtrl; break;
4587
0
    case Mips::MSA24: OpKind = MCK_MSACtrl; break;
4588
0
    case Mips::MSA25: OpKind = MCK_MSACtrl; break;
4589
0
    case Mips::MSA26: OpKind = MCK_MSACtrl; break;
4590
0
    case Mips::MSA27: OpKind = MCK_MSACtrl; break;
4591
0
    case Mips::MSA28: OpKind = MCK_MSACtrl; break;
4592
0
    case Mips::MSA29: OpKind = MCK_MSACtrl; break;
4593
0
    case Mips::MSA30: OpKind = MCK_MSACtrl; break;
4594
0
    case Mips::MSA31: OpKind = MCK_MSACtrl; break;
4595
0
    case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break;
4596
0
    case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break;
4597
0
    case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break;
4598
0
    case Mips::P0: OpKind = MCK_OCTEON_P; break;
4599
0
    case Mips::P1: OpKind = MCK_OCTEON_P; break;
4600
0
    case Mips::P2: OpKind = MCK_OCTEON_P; break;
4601
0
    }
4602
0
    return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success :
4603
0
                                      getDiagKindFromRegisterClass(Kind);
4604
0
  }
4605
4606
0
  if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)
4607
0
    return getDiagKindFromRegisterClass(Kind);
4608
4609
0
  return MCTargetAsmParser::Match_InvalidOperand;
4610
0
}
4611
4612
#ifndef NDEBUG
4613
0
const char *getMatchClassName(MatchClassKind Kind) {
4614
0
  switch (Kind) {
4615
0
  case InvalidMatchClass: return "InvalidMatchClass";
4616
0
  case OptionalMatchClass: return "OptionalMatchClass";
4617
0
  case MCK__HASH_: return "MCK__HASH_";
4618
0
  case MCK__40_: return "MCK__40_";
4619
0
  case MCK__41_: return "MCK__41_";
4620
0
  case MCK_0: return "MCK_0";
4621
0
  case MCK_16: return "MCK_16";
4622
0
  case MCK__91_: return "MCK__91_";
4623
0
  case MCK__93_: return "MCK__93_";
4624
0
  case MCK_bit: return "MCK_bit";
4625
0
  case MCK_inst: return "MCK_inst";
4626
0
  case MCK_Reg37: return "MCK_Reg37";
4627
0
  case MCK_Reg19: return "MCK_Reg19";
4628
0
  case MCK_ACC128: return "MCK_ACC128";
4629
0
  case MCK_ACC64: return "MCK_ACC64";
4630
0
  case MCK_CPURAReg: return "MCK_CPURAReg";
4631
0
  case MCK_CPUSPReg: return "MCK_CPUSPReg";
4632
0
  case MCK_DSPCC: return "MCK_DSPCC";
4633
0
  case MCK_GP32: return "MCK_GP32";
4634
0
  case MCK_GP64: return "MCK_GP64";
4635
0
  case MCK_GPR32ZERO: return "MCK_GPR32ZERO";
4636
0
  case MCK_HI32: return "MCK_HI32";
4637
0
  case MCK_HI64: return "MCK_HI64";
4638
0
  case MCK_LO32: return "MCK_LO32";
4639
0
  case MCK_LO64: return "MCK_LO64";
4640
0
  case MCK_PC: return "MCK_PC";
4641
0
  case MCK_SP64: return "MCK_SP64";
4642
0
  case MCK_Reg32: return "MCK_Reg32";
4643
0
  case MCK_Reg13: return "MCK_Reg13";
4644
0
  case MCK_Reg33: return "MCK_Reg33";
4645
0
  case MCK_Reg31: return "MCK_Reg31";
4646
0
  case MCK_Reg30: return "MCK_Reg30";
4647
0
  case MCK_Reg14: return "MCK_Reg14";
4648
0
  case MCK_Reg11: return "MCK_Reg11";
4649
0
  case MCK_GPRMM16MovePPairFirst: return "MCK_GPRMM16MovePPairFirst";
4650
0
  case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL";
4651
0
  case MCK_OCTEON_P: return "MCK_OCTEON_P";
4652
0
  case MCK_Reg28: return "MCK_Reg28";
4653
0
  case MCK_Reg23: return "MCK_Reg23";
4654
0
  case MCK_Reg9: return "MCK_Reg9";
4655
0
  case MCK_Reg4: return "MCK_Reg4";
4656
0
  case MCK_ACC64DSP: return "MCK_ACC64DSP";
4657
0
  case MCK_HI32DSP: return "MCK_HI32DSP";
4658
0
  case MCK_LO32DSP: return "MCK_LO32DSP";
4659
0
  case MCK_Reg34: return "MCK_Reg34";
4660
0
  case MCK_GPRMM16MovePPairSecond: return "MCK_GPRMM16MovePPairSecond";
4661
0
  case MCK_Reg29: return "MCK_Reg29";
4662
0
  case MCK_Reg27: return "MCK_Reg27";
4663
0
  case MCK_Reg10: return "MCK_Reg10";
4664
0
  case MCK_Reg8: return "MCK_Reg8";
4665
0
  case MCK_Reg25: return "MCK_Reg25";
4666
0
  case MCK_Reg22: return "MCK_Reg22";
4667
0
  case MCK_Reg21: return "MCK_Reg21";
4668
0
  case MCK_CPU16Regs: return "MCK_CPU16Regs";
4669
0
  case MCK_FCC: return "MCK_FCC";
4670
0
  case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP";
4671
0
  case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero";
4672
0
  case MCK_Reg26: return "MCK_Reg26";
4673
0
  case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP";
4674
0
  case MCK_AFGR64: return "MCK_AFGR64";
4675
0
  case MCK_MSA128WEvens: return "MCK_MSA128WEvens";
4676
0
  case MCK_Reg24: return "MCK_Reg24";
4677
0
  case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO";
4678
0
  case MCK_CCR: return "MCK_CCR";
4679
0
  case MCK_COP0: return "MCK_COP0";
4680
0
  case MCK_COP2: return "MCK_COP2";
4681
0
  case MCK_COP3: return "MCK_COP3";
4682
0
  case MCK_DSPR: return "MCK_DSPR";
4683
0
  case MCK_FGR32: return "MCK_FGR32";
4684
0
  case MCK_FGR64: return "MCK_FGR64";
4685
0
  case MCK_GPR64: return "MCK_GPR64";
4686
0
  case MCK_HWRegs: return "MCK_HWRegs";
4687
0
  case MCK_MSA128F16: return "MCK_MSA128F16";
4688
0
  case MCK_MSACtrl: return "MCK_MSACtrl";
4689
0
  case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg";
4690
0
  case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg";
4691
0
  case MCK_CCRAsmReg: return "MCK_CCRAsmReg";
4692
0
  case MCK_COP0AsmReg: return "MCK_COP0AsmReg";
4693
0
  case MCK_COP2AsmReg: return "MCK_COP2AsmReg";
4694
0
  case MCK_COP3AsmReg: return "MCK_COP3AsmReg";
4695
0
  case MCK_FCCAsmReg: return "MCK_FCCAsmReg";
4696
0
  case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg";
4697
0
  case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg";
4698
0
  case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg";
4699
0
  case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg";
4700
0
  case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg";
4701
0
  case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg";
4702
0
  case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg";
4703
0
  case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP";
4704
0
  case MCK_GPRMM16AsmRegMovePPairFirst: return "MCK_GPRMM16AsmRegMovePPairFirst";
4705
0
  case MCK_GPRMM16AsmRegMovePPairSecond: return "MCK_GPRMM16AsmRegMovePPairSecond";
4706
0
  case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero";
4707
0
  case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg";
4708
0
  case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg";
4709
0
  case MCK_Imm: return "MCK_Imm";
4710
0
  case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg";
4711
0
  case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg";
4712
0
  case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg";
4713
0
  case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP";
4714
0
  case MCK_MicroMipsMem: return "MCK_MicroMipsMem";
4715
0
  case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP";
4716
0
  case MCK_InvNum: return "MCK_InvNum";
4717
0
  case MCK_JumpTarget: return "MCK_JumpTarget";
4718
0
  case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr";
4719
0
  case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4";
4720
0
  case MCK_MemOffsetSimm9_0: return "MCK_MemOffsetSimm9_0";
4721
0
  case MCK_MemOffsetSimm10_0: return "MCK_MemOffsetSimm10_0";
4722
0
  case MCK_MemOffsetSimm11_0: return "MCK_MemOffsetSimm11_0";
4723
0
  case MCK_MemOffsetSimm12_0: return "MCK_MemOffsetSimm12_0";
4724
0
  case MCK_MemOffsetSimm16_0: return "MCK_MemOffsetSimm16_0";
4725
0
  case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1";
4726
0
  case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2";
4727
0
  case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3";
4728
0
  case MCK_Mem: return "MCK_Mem";
4729
0
  case MCK_RegList16: return "MCK_RegList16";
4730
0
  case MCK_RegList: return "MCK_RegList";
4731
0
  case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2";
4732
0
  case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg";
4733
0
  case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg";
4734
0
  case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg";
4735
0
  case MCK_ConstantImmz: return "MCK_ConstantImmz";
4736
0
  case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0";
4737
0
  case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0";
4738
0
  case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1";
4739
0
  case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0";
4740
0
  case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0";
4741
0
  case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0";
4742
0
  case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0";
4743
0
  case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0";
4744
0
  case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1";
4745
0
  case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6";
4746
0
  case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm";
4747
0
  case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32";
4748
0
  case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6";
4749
0
  case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33";
4750
0
  case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64";
4751
0
  case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2";
4752
0
  case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0";
4753
0
  case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0";
4754
0
  case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2";
4755
0
  case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0";
4756
0
  case MCK_UImm7_N1: return "MCK_UImm7_N1";
4757
0
  case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0";
4758
0
  case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2";
4759
0
  case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0";
4760
0
  case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0";
4761
0
  case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0";
4762
0
  case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1";
4763
0
  case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0";
4764
0
  case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2";
4765
0
  case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3";
4766
0
  case MCK_SImm16: return "MCK_SImm16";
4767
0
  case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed";
4768
0
  case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed";
4769
0
  case MCK_UImm16: return "MCK_UImm16";
4770
0
  case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2";
4771
0
  case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed";
4772
0
  case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0";
4773
0
  case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0";
4774
0
  case MCK_SImm32: return "MCK_SImm32";
4775
0
  case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed";
4776
0
  case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced";
4777
0
  case NumMatchClassKinds: return "NumMatchClassKinds";
4778
0
  }
4779
0
  llvm_unreachable("unhandled MatchClassKind!");
4780
0
}
4781
4782
#endif // NDEBUG
4783
FeatureBitset MipsAsmParser::
4784
3
ComputeAvailableFeatures(const FeatureBitset &FB) const {
4785
3
  FeatureBitset Features;
4786
3
  if (FB[Mips::FeatureMips2])
4787
3
    Features.set(Feature_HasMips2Bit);
4788
3
  if (FB[Mips::FeatureMips3_32])
4789
3
    Features.set(Feature_HasMips3_32Bit);
4790
3
  if (FB[Mips::FeatureMips3_32r2])
4791
3
    Features.set(Feature_HasMips3_32r2Bit);
4792
3
  if (FB[Mips::FeatureMips3])
4793
3
    Features.set(Feature_HasMips3Bit);
4794
3
  if (!FB[Mips::FeatureMips3])
4795
0
    Features.set(Feature_NotMips3Bit);
4796
3
  if (FB[Mips::FeatureMips4_32])
4797
3
    Features.set(Feature_HasMips4_32Bit);
4798
3
  if (!FB[Mips::FeatureMips4_32])
4799
0
    Features.set(Feature_NotMips4_32Bit);
4800
3
  if (FB[Mips::FeatureMips4_32r2])
4801
3
    Features.set(Feature_HasMips4_32r2Bit);
4802
3
  if (FB[Mips::FeatureMips5_32r2])
4803
3
    Features.set(Feature_HasMips5_32r2Bit);
4804
3
  if (FB[Mips::FeatureMips32])
4805
3
    Features.set(Feature_HasMips32Bit);
4806
3
  if (FB[Mips::FeatureMips32r2])
4807
0
    Features.set(Feature_HasMips32r2Bit);
4808
3
  if (FB[Mips::FeatureMips32r5])
4809
0
    Features.set(Feature_HasMips32r5Bit);
4810
3
  if (FB[Mips::FeatureMips32r6])
4811
0
    Features.set(Feature_HasMips32r6Bit);
4812
3
  if (!FB[Mips::FeatureMips32r6])
4813
3
    Features.set(Feature_NotMips32r6Bit);
4814
3
  if (FB[Mips::FeatureGP64Bit])
4815
3
    Features.set(Feature_IsGP64bitBit);
4816
3
  if (!FB[Mips::FeatureGP64Bit])
4817
0
    Features.set(Feature_IsGP32bitBit);
4818
3
  if (FB[Mips::FeaturePTR64Bit])
4819
0
    Features.set(Feature_IsPTR64bitBit);
4820
3
  if (!FB[Mips::FeaturePTR64Bit])
4821
3
    Features.set(Feature_IsPTR32bitBit);
4822
3
  if (FB[Mips::FeatureMips64])
4823
3
    Features.set(Feature_HasMips64Bit);
4824
3
  if (!FB[Mips::FeatureMips64])
4825
0
    Features.set(Feature_NotMips64Bit);
4826
3
  if (FB[Mips::FeatureMips64r2])
4827
0
    Features.set(Feature_HasMips64r2Bit);
4828
3
  if (FB[Mips::FeatureMips64r5])
4829
0
    Features.set(Feature_HasMips64r5Bit);
4830
3
  if (FB[Mips::FeatureMips64r6])
4831
0
    Features.set(Feature_HasMips64r6Bit);
4832
3
  if (!FB[Mips::FeatureMips64r6])
4833
3
    Features.set(Feature_NotMips64r6Bit);
4834
3
  if (FB[Mips::FeatureMips16])
4835
0
    Features.set(Feature_InMips16ModeBit);
4836
3
  if (!FB[Mips::FeatureMips16])
4837
3
    Features.set(Feature_NotInMips16ModeBit);
4838
3
  if (FB[Mips::FeatureCnMips])
4839
0
    Features.set(Feature_HasCnMipsBit);
4840
3
  if (!FB[Mips::FeatureCnMips])
4841
3
    Features.set(Feature_NotCnMipsBit);
4842
3
  if (FB[Mips::FeatureCnMipsP])
4843
0
    Features.set(Feature_HasCnMipsPBit);
4844
3
  if (!FB[Mips::FeatureCnMipsP])
4845
3
    Features.set(Feature_NotCnMipsPBit);
4846
3
  if (FB[Mips::FeatureSym32])
4847
0
    Features.set(Feature_IsSym32Bit);
4848
3
  if (!FB[Mips::FeatureSym32])
4849
3
    Features.set(Feature_IsSym64Bit);
4850
3
  if (!FB[Mips::FeatureMips16])
4851
3
    Features.set(Feature_HasStdEncBit);
4852
3
  if (FB[Mips::FeatureMicroMips])
4853
0
    Features.set(Feature_InMicroMipsBit);
4854
3
  if (!FB[Mips::FeatureMicroMips])
4855
3
    Features.set(Feature_NotInMicroMipsBit);
4856
3
  if (FB[Mips::FeatureEVA])
4857
0
    Features.set(Feature_HasEVABit);
4858
3
  if (FB[Mips::FeatureMSA])
4859
0
    Features.set(Feature_HasMSABit);
4860
3
  if (!FB[Mips::FeatureNoMadd4])
4861
3
    Features.set(Feature_HasMadd4Bit);
4862
3
  if (FB[Mips::FeatureMT])
4863
0
    Features.set(Feature_HasMTBit);
4864
3
  if (FB[Mips::FeatureUseIndirectJumpsHazard])
4865
0
    Features.set(Feature_UseIndirectJumpsHazardBit);
4866
3
  if (!FB[Mips::FeatureUseIndirectJumpsHazard])
4867
3
    Features.set(Feature_NoIndirectJumpGuardsBit);
4868
3
  if (FB[Mips::FeatureCRC])
4869
0
    Features.set(Feature_HasCRCBit);
4870
3
  if (FB[Mips::FeatureVirt])
4871
0
    Features.set(Feature_HasVirtBit);
4872
3
  if (FB[Mips::FeatureGINV])
4873
0
    Features.set(Feature_HasGINVBit);
4874
3
  if (FB[Mips::FeatureFP64Bit])
4875
3
    Features.set(Feature_IsFP64bitBit);
4876
3
  if (!FB[Mips::FeatureFP64Bit])
4877
0
    Features.set(Feature_NotFP64bitBit);
4878
3
  if (FB[Mips::FeatureSingleFloat])
4879
0
    Features.set(Feature_IsSingleFloatBit);
4880
3
  if (!FB[Mips::FeatureSingleFloat])
4881
3
    Features.set(Feature_IsNotSingleFloatBit);
4882
3
  if (!FB[Mips::FeatureSoftFloat])
4883
3
    Features.set(Feature_IsNotSoftFloatBit);
4884
3
  if (FB[Mips::FeatureMips3D])
4885
0
    Features.set(Feature_HasMips3DBit);
4886
3
  if (FB[Mips::FeatureDSP])
4887
0
    Features.set(Feature_HasDSPBit);
4888
3
  if (FB[Mips::FeatureDSPR2])
4889
0
    Features.set(Feature_HasDSPR2Bit);
4890
3
  if (FB[Mips::FeatureDSPR3])
4891
0
    Features.set(Feature_HasDSPR3Bit);
4892
3
  return Features;
4893
3
}
4894
4895
static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser,
4896
                               unsigned Kind,
4897
                               const OperandVector &Operands,
4898
0
                               uint64_t &ErrorInfo) {
4899
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
4900
0
  const uint8_t *Converter = ConversionTable[Kind];
4901
0
  for (const uint8_t *p = Converter; *p; p += 2) {
4902
0
    switch (*p) {
4903
0
    case CVT_Tied: {
4904
0
      unsigned OpIdx = *(p + 1);
4905
0
      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -
4906
0
                              std::begin(TiedAsmOperandTable)) &&
4907
0
             "Tied operand not found");
4908
0
      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];
4909
0
      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];
4910
0
      if (OpndNum1 != OpndNum2) {
4911
0
        auto &SrcOp1 = Operands[OpndNum1];
4912
0
        auto &SrcOp2 = Operands[OpndNum2];
4913
0
        if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {
4914
0
          ErrorInfo = OpndNum2;
4915
0
          return false;
4916
0
        }
4917
0
      }
4918
0
      break;
4919
0
    }
4920
0
    default:
4921
0
      break;
4922
0
    }
4923
0
  }
4924
0
  return true;
4925
0
}
4926
4927
static const char MnemonicTable[] =
4928
    "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a"
4929
    "dd.d\006add.ps\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004"
4930
    "addi\005addiu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007"
4931
    "addq.ph\taddq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddq"
4932
    "h_r.w\007addr.ps\010adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010add"
4933
    "s_s.b\010adds_s.d\010adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010ad"
4934
    "ds_u.h\010adds_u.w\005addsc\004addu\007addu.ph\007addu.qb\006addu16\tad"
4935
    "du_s.ph\taddu_s.qb\010adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv."
4936
    "h\006addv.w\007addvi.b\007addvi.d\007addvi.h\007addvi.w\005addwc\005ali"
4937
    "gn\006aluipc\003and\005and.v\005and16\004andi\006andi.b\006andi16\006ap"
4938
    "pend\010asub_s.b\010asub_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asu"
4939
    "b_u.d\010asub_u.h\010asub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007"
4940
    "ave_s.h\007ave_s.w\007ave_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_"
4941
    "s.b\010aver_s.d\010aver_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver"
4942
    "_u.h\010aver_u.w\001b\003b16\005baddu\003bal\004balc\006balign\005bbit0"
4943
    "\007bbit032\005bbit1\007bbit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004b"
4944
    "c1f\005bc1fl\006bc1nez\007bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc"
4945
    "\006bc2nez\007bc2nezc\006bclr.b\006bclr.d\006bclr.h\006bclr.w\007bclri."
4946
    "b\007bclri.d\007bclri.h\007bclri.w\003beq\004beqc\004beql\004beqz\006be"
4947
    "qz16\007beqzalc\005beqzc\007beqzc16\005beqzl\003bge\004bgec\004bgel\004"
4948
    "bgeu\005bgeuc\005bgeul\004bgez\006bgezal\007bgezalc\007bgezall\007bgeza"
4949
    "ls\005bgezc\005bgezl\003bgt\004bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc"
4950
    "\005bgtzc\005bgtzl\007binsl.b\007binsl.d\007binsl.h\007binsl.w\010binsl"
4951
    "i.b\010binsli.d\010binsli.h\010binsli.w\007binsr.b\007binsr.d\007binsr."
4952
    "h\007binsr.w\010binsri.b\010binsri.d\010binsri.h\010binsri.w\006bitrev\007"
4953
    "bitswap\003ble\004blel\004bleu\005bleul\004blez\007blezalc\005blezc\005"
4954
    "blezl\003blt\004bltc\004bltl\004bltu\005bltuc\005bltul\004bltz\006bltza"
4955
    "l\007bltzalc\007bltzall\007bltzals\005bltzc\005bltzl\006bmnz.v\007bmnzi"
4956
    ".b\005bmz.v\006bmzi.b\003bne\004bnec\006bneg.b\006bneg.d\006bneg.h\006b"
4957
    "neg.w\007bnegi.b\007bnegi.d\007bnegi.h\007bnegi.w\004bnel\004bnez\006bn"
4958
    "ez16\007bnezalc\005bnezc\007bnezc16\005bnezl\004bnvc\005bnz.b\005bnz.d\005"
4959
    "bnz.h\005bnz.v\005bnz.w\004bovc\010bposge32\tbposge32c\005break\007brea"
4960
    "k16\006bsel.v\007bseli.b\006bset.b\006bset.d\006bset.h\006bset.w\007bse"
4961
    "ti.b\007bseti.d\007bseti.h\007bseti.w\005bteqz\005btnez\004bz.b\004bz.d"
4962
    "\004bz.h\004bz.v\004bz.w\006c.eq.d\006c.eq.s\005c.f.d\005c.f.s\006c.le."
4963
    "d\006c.le.s\006c.lt.d\006c.lt.s\007c.nge.d\007c.nge.s\007c.ngl.d\007c.n"
4964
    "gl.s\010c.ngle.d\010c.ngle.s\007c.ngt.d\007c.ngt.s\007c.ole.d\007c.ole."
4965
    "s\007c.olt.d\007c.olt.s\007c.seq.d\007c.seq.s\006c.sf.d\006c.sf.s\007c."
4966
    "ueq.d\007c.ueq.s\007c.ule.d\007c.ule.s\007c.ult.d\007c.ult.s\006c.un.d\006"
4967
    "c.un.s\005cache\006cachee\010ceil.l.d\010ceil.l.s\010ceil.w.d\010ceil.w"
4968
    ".s\005ceq.b\005ceq.d\005ceq.h\005ceq.w\006ceqi.b\006ceqi.d\006ceqi.h\006"
4969
    "ceqi.w\004cfc1\004cfc2\006cfcmsa\005cftc1\004cins\006cins32\007class.d\007"
4970
    "class.s\007cle_s.b\007cle_s.d\007cle_s.h\007cle_s.w\007cle_u.b\007cle_u"
4971
    ".d\007cle_u.h\007cle_u.w\010clei_s.b\010clei_s.d\010clei_s.h\010clei_s."
4972
    "w\010clei_u.b\010clei_u.d\010clei_u.h\010clei_u.w\003clo\007clt_s.b\007"
4973
    "clt_s.d\007clt_s.h\007clt_s.w\007clt_u.b\007clt_u.d\007clt_u.h\007clt_u"
4974
    ".w\010clti_s.b\010clti_s.d\010clti_s.h\010clti_s.w\010clti_u.b\010clti_"
4975
    "u.d\010clti_u.h\010clti_u.w\003clz\003cmp\010cmp.af.d\010cmp.af.s\010cm"
4976
    "p.eq.d\tcmp.eq.ph\010cmp.eq.s\010cmp.le.d\tcmp.le.ph\010cmp.le.s\010cmp"
4977
    ".lt.d\tcmp.lt.ph\010cmp.lt.s\tcmp.saf.d\tcmp.saf.s\tcmp.seq.d\tcmp.seq."
4978
    "s\tcmp.sle.d\tcmp.sle.s\tcmp.slt.d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\n"
4979
    "cmp.sule.d\ncmp.sule.s\ncmp.sult.d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tc"
4980
    "mp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tcmp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp."
4981
    "un.d\010cmp.un.s\014cmpgdu.eq.qb\014cmpgdu.le.qb\014cmpgdu.lt.qb\013cmp"
4982
    "gu.eq.qb\013cmpgu.le.qb\013cmpgu.lt.qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\n"
4983
    "cmpu.lt.qb\010copy_s.b\010copy_s.d\010copy_s.h\010copy_s.w\010copy_u.b\010"
4984
    "copy_u.h\010copy_u.w\006crc32b\007crc32cb\007crc32cd\007crc32ch\007crc3"
4985
    "2cw\006crc32d\006crc32h\006crc32w\004ctc1\004ctc2\006ctcmsa\005cttc1\007"
4986
    "cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.l.s\tcvt.ps.pw\010cvt.p"
4987
    "s.s\tcvt.pw.ps\007cvt.s.d\007cvt.s.l\010cvt.s.pl\010cvt.s.pu\007cvt.s.w"
4988
    "\007cvt.w.d\007cvt.w.s\004dadd\005daddi\006daddiu\005daddu\004dahi\006d"
4989
    "align\004dati\004daui\010dbitswap\004dclo\004dclz\004ddiv\005ddivu\005d"
4990
    "eret\004dext\005dextm\005dextu\002di\004dins\005dinsm\005dinsu\003div\005"
4991
    "div.d\005div.s\007div_s.b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007"
4992
    "div_u.d\007div_u.h\007div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005"
4993
    "dmfc1\005dmfc2\006dmfgc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005d"
4994
    "mtc2\006dmtgc0\004dmuh\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006"
4995
    "dmultu\005dmulu\004dneg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010"
4996
    "dotp_u.d\010dotp_u.h\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpa"
4997
    "dd_s.w\tdpadd_u.d\tdpadd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014"
4998
    "dpaqx_s.w.ph\015dpaqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpo"
4999
    "p\010dps.w.ph\013dpsq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa"
5000
    ".w.ph\ndpsu.h.qbl\ndpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u"
5001
    ".d\tdpsub_u.h\tdpsub_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005"
5002
    "drotr\007drotr32\006drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004"
5003
    "dsra\006dsra32\005dsrav\004dsrl\006dsrl32\005dsrlv\004dsub\005dsubi\005"
5004
    "dsubu\003dvp\004dvpe\003ehb\002ei\003emt\004eret\006eretnc\003evp\004ev"
5005
    "pe\003ext\004extp\006extpdp\007extpdpv\005extpv\006extr.w\010extr_r.w\t"
5006
    "extr_rs.w\010extr_s.h\007extrv.w\textrv_r.w\nextrv_rs.w\textrv_s.h\004e"
5007
    "xts\006exts32\006fadd.d\006fadd.w\006fcaf.d\006fcaf.w\006fceq.d\006fceq"
5008
    ".w\010fclass.d\010fclass.w\006fcle.d\006fcle.w\006fclt.d\006fclt.w\006f"
5009
    "cne.d\006fcne.w\006fcor.d\006fcor.w\007fcueq.d\007fcueq.w\007fcule.d\007"
5010
    "fcule.w\007fcult.d\007fcult.w\006fcun.d\006fcun.w\007fcune.d\007fcune.w"
5011
    "\006fdiv.d\006fdiv.w\007fexdo.h\007fexdo.w\007fexp2.d\007fexp2.w\010fex"
5012
    "upl.d\010fexupl.w\010fexupr.d\010fexupr.w\tffint_s.d\tffint_s.w\tffint_"
5013
    "u.d\tffint_u.w\006ffql.d\006ffql.w\006ffqr.d\006ffqr.w\006fill.b\006fil"
5014
    "l.d\006fill.h\006fill.w\007flog2.d\007flog2.w\tfloor.l.d\tfloor.l.s\tfl"
5015
    "oor.w.d\tfloor.w.s\007fmadd.d\007fmadd.w\006fmax.d\006fmax.w\010fmax_a."
5016
    "d\010fmax_a.w\006fmin.d\006fmin.w\010fmin_a.d\010fmin_a.w\007fmsub.d\007"
5017
    "fmsub.w\006fmul.d\006fmul.w\004fork\006frcp.d\006frcp.w\007frint.d\007f"
5018
    "rint.w\010frsqrt.d\010frsqrt.w\006fsaf.d\006fsaf.w\006fseq.d\006fseq.w\006"
5019
    "fsle.d\006fsle.w\006fslt.d\006fslt.w\006fsne.d\006fsne.w\006fsor.d\006f"
5020
    "sor.w\007fsqrt.d\007fsqrt.w\006fsub.d\006fsub.w\007fsueq.d\007fsueq.w\007"
5021
    "fsule.d\007fsule.w\007fsult.d\007fsult.w\006fsun.d\006fsun.w\007fsune.d"
5022
    "\007fsune.w\tftint_s.d\tftint_s.w\tftint_u.d\tftint_u.w\005ftq.h\005ftq"
5023
    ".w\nftrunc_s.d\nftrunc_s.w\nftrunc_u.d\nftrunc_u.w\005ginvi\005ginvt\010"
5024
    "hadd_s.d\010hadd_s.h\010hadd_s.w\010hadd_u.d\010hadd_u.h\010hadd_u.w\010"
5025
    "hsub_s.d\010hsub_s.h\010hsub_s.w\010hsub_u.d\010hsub_u.h\010hsub_u.w\007"
5026
    "hypcall\007ilvev.b\007ilvev.d\007ilvev.h\007ilvev.w\006ilvl.b\006ilvl.d"
5027
    "\006ilvl.h\006ilvl.w\007ilvod.b\007ilvod.d\007ilvod.h\007ilvod.w\006ilv"
5028
    "r.b\006ilvr.d\006ilvr.h\006ilvr.w\003ins\010insert.b\010insert.d\010ins"
5029
    "ert.h\010insert.w\004insv\007insve.b\007insve.d\007insve.h\007insve.w\001"
5030
    "j\003jal\004jalr\007jalr.hb\005jalrc\010jalrc.hb\005jalrs\007jalrs16\004"
5031
    "jals\004jalx\005jialc\003jic\002jr\005jr.hb\004jr16\tjraddiusp\003jrc\005"
5032
    "jrc16\njrcaddiusp\003l.d\003l.s\002la\004lapc\002lb\003lbe\003lbu\005lb"
5033
    "u16\004lbue\004lbux\002ld\004ld.b\004ld.d\004ld.h\004ld.w\004ldc1\004ld"
5034
    "c2\004ldc3\005ldi.b\005ldi.d\005ldi.h\005ldi.w\003ldl\004ldpc\003ldr\005"
5035
    "ldxc1\002lh\003lhe\003lhu\005lhu16\004lhue\003lhx\002li\004li.d\004li.s"
5036
    "\004li16\002ll\003lld\003lle\003lsa\003lui\005luxc1\002lw\004lw16\004lw"
5037
    "c1\004lwc2\004lwc3\003lwe\003lwl\004lwle\003lwm\005lwm16\005lwm32\003lw"
5038
    "p\004lwpc\003lwr\004lwre\003lwu\005lwupc\003lwx\005lwxc1\004lwxs\004mad"
5039
    "d\006madd.d\006madd.s\010madd_q.h\010madd_q.w\007maddf.d\007maddf.s\tma"
5040
    "ddr_q.h\tmaddr_q.w\005maddu\007maddv.b\007maddv.d\007maddv.h\007maddv.w"
5041
    "\013maq_s.w.phl\013maq_s.w.phr\014maq_sa.w.phl\014maq_sa.w.phr\005max.d"
5042
    "\005max.s\007max_a.b\007max_a.d\007max_a.h\007max_a.w\007max_s.b\007max"
5043
    "_s.d\007max_s.h\007max_s.w\007max_u.b\007max_u.d\007max_u.h\007max_u.w\006"
5044
    "maxa.d\006maxa.s\010maxi_s.b\010maxi_s.d\010maxi_s.h\010maxi_s.w\010max"
5045
    "i_u.b\010maxi_u.d\010maxi_u.h\010maxi_u.w\004mfc0\004mfc1\004mfc2\005mf"
5046
    "gc0\005mfhc0\005mfhc1\005mfhc2\006mfhgc0\004mfhi\006mfhi16\004mflo\006m"
5047
    "flo16\006mftacx\005mftc0\005mftc1\006mftdsp\006mftgpr\006mfthc1\005mfth"
5048
    "i\005mftlo\004mftr\005min.d\005min.s\007min_a.b\007min_a.d\007min_a.h\007"
5049
    "min_a.w\007min_s.b\007min_s.d\007min_s.h\007min_s.w\007min_u.b\007min_u"
5050
    ".d\007min_u.h\007min_u.w\006mina.d\006mina.s\010mini_s.b\010mini_s.d\010"
5051
    "mini_s.h\010mini_s.w\010mini_u.b\010mini_u.d\010mini_u.h\010mini_u.w\003"
5052
    "mod\007mod_s.b\007mod_s.d\007mod_s.h\007mod_s.w\007mod_u.b\007mod_u.d\007"
5053
    "mod_u.h\007mod_u.w\006modsub\004modu\005mov.d\005mov.s\004move\006move."
5054
    "v\006move16\005movep\004movf\006movf.d\006movf.s\004movn\006movn.d\006m"
5055
    "ovn.s\004movt\006movt.d\006movt.s\004movz\006movz.d\006movz.s\004msub\006"
5056
    "msub.d\006msub.s\010msub_q.h\010msub_q.w\007msubf.d\007msubf.s\tmsubr_q"
5057
    ".h\tmsubr_q.w\005msubu\007msubv.b\007msubv.d\007msubv.h\007msubv.w\004m"
5058
    "tc0\004mtc1\004mtc2\005mtgc0\005mthc0\005mthc1\005mthc2\006mthgc0\004mt"
5059
    "hi\006mthlip\004mtlo\004mtm0\004mtm1\004mtm2\004mtp0\004mtp1\004mtp2\006"
5060
    "mttacx\005mttc0\005mttc1\006mttdsp\006mttgpr\006mtthc1\005mtthi\005mttl"
5061
    "o\004mttr\003muh\004muhu\003mul\005mul.d\006mul.ph\006mul.ps\005mul.s\007"
5062
    "mul_q.h\007mul_q.w\010mul_s.ph\015muleq_s.w.phl\015muleq_s.w.phr\016mul"
5063
    "eu_s.ph.qbl\016muleu_s.ph.qbr\004mulo\005mulou\nmulq_rs.ph\tmulq_rs.w\t"
5064
    "mulq_s.ph\010mulq_s.w\007mulr.ps\010mulr_q.h\010mulr_q.w\nmulsa.w.ph\015"
5065
    "mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d\006mulv.h\006"
5066
    "mulv.w\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc.d\006nloc.h\006"
5067
    "nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd.d\007nmadd.s\007"
5068
    "nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003not\005not16\002"
5069
    "or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007pckev.b\007pc"
5070
    "kev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod.h\007pckod.w"
5071
    "\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pick.qb\006pll.p"
5072
    "s\006plu.ps\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017"
5073
    "precequ.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016"
5074
    "preceu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016pre"
5075
    "cr_sra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precr"
5076
    "q_rs.ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\006pu"
5077
    "l.ps\006puu.ps\nraddu.w.qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007re"
5078
    "cip.s\003rem\004remu\007repl.ph\007repl.qb\010replv.ph\010replv.qb\006r"
5079
    "int.d\006rint.s\003rol\003ror\004rotr\005rotrv\tround.l.d\tround.l.s\tr"
5080
    "ound.w.d\tround.w.s\007rsqrt.d\007rsqrt.s\003s.d\003s.s\003saa\004saad\007"
5081
    "sat_s.b\007sat_s.d\007sat_s.h\007sat_s.w\007sat_u.b\007sat_u.d\007sat_u"
5082
    ".h\007sat_u.w\002sb\004sb16\003sbe\002sc\003scd\003sce\002sd\005sdbbp\007"
5083
    "sdbbp16\004sdc1\004sdc2\004sdc3\003sdl\003sdr\005sdxc1\003seb\003seh\005"
5084
    "sel.d\005sel.s\006seleqz\010seleqz.d\010seleqz.s\006selnez\010selnez.d\010"
5085
    "selnez.s\003seq\004seqi\003sge\004sgeu\003sgt\004sgtu\002sh\004sh16\003"
5086
    "she\005shf.b\005shf.h\005shf.w\005shilo\006shilov\007shll.ph\007shll.qb"
5087
    "\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\nshllv_s.ph\tshllv_s.w\007"
5088
    "shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010shra_r.w\010shrav.ph\010shr"
5089
    "av.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007shrl.ph\007shrl.qb\010shrlv"
5090
    ".ph\010shrlv.qb\006sigrie\005sld.b\005sld.d\005sld.h\005sld.w\006sldi.b"
5091
    "\006sldi.d\006sldi.h\006sldi.w\003sle\004sleu\003sll\005sll.b\005sll.d\005"
5092
    "sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006slli.w\004sllv"
5093
    "\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b\007splat.d\007"
5094
    "splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010splati.w\006s"
5095
    "qrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w\006srai.b\006"
5096
    "srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006srar.w\007s"
5097
    "rari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005srl.b\005srl."
5098
    "d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006srli.w\006"
5099
    "srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007srlri.h\007"
5100
    "srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003sub\005sub."
5101
    "d\006sub.ps\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010subqh.ph\007s"
5102
    "ubqh.w\nsubqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010subs_s.h\010su"
5103
    "bs_s.w\010subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubsus_u.b\nsub"
5104
    "sus_u.d\nsubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsubsuu_s.h\nsu"
5105
    "bsuu_s.w\004subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\tsubu_s.qb\010"
5106
    "subuh.qb\nsubuh_r.qb\006subv.b\006subv.d\006subv.h\006subv.w\007subvi.b"
5107
    "\007subvi.d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004swc1\004swc"
5108
    "2\004swc3\003swe\003swl\004swle\003swm\005swm16\005swm32\003swp\003swr\004"
5109
    "swre\004swsp\005swxc1\004sync\005synci\nsynciobdma\005syncs\005syncw\006"
5110
    "syncws\007syscall\003teq\004teqi\003tge\004tgei\005tgeiu\004tgeu\007tlb"
5111
    "ginv\010tlbginvf\005tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbinv\007tlb"
5112
    "invf\004tlbp\004tlbr\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004tltu\003"
5113
    "tne\004tnei\ttrunc.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004ulhu\003"
5114
    "ulw\003ush\003usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf.d\006vsh"
5115
    "f.h\006vshf.w\004wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor.v\005xor"
5116
    "16\004xori\006xori.b\005yield";
5117
5118
// Feature bitsets.
5119
enum : uint8_t {
5120
  AMFBS_None,
5121
  AMFBS_HasCnMips,
5122
  AMFBS_HasCnMipsP,
5123
  AMFBS_HasDSP,
5124
  AMFBS_HasDSPR2,
5125
  AMFBS_HasMT,
5126
  AMFBS_InMicroMips,
5127
  AMFBS_InMips16Mode,
5128
  AMFBS_IsGP32bit,
5129
  AMFBS_IsGP64bit,
5130
  AMFBS_IsNotSoftFloat,
5131
  AMFBS_NotCnMips,
5132
  AMFBS_NotInMicroMips,
5133
  AMFBS_HasDSP_InMicroMips,
5134
  AMFBS_HasDSP_NotInMicroMips,
5135
  AMFBS_HasMT_NotInMicroMips,
5136
  AMFBS_HasMips64_HasCnMips,
5137
  AMFBS_HasStdEnc_HasMSA,
5138
  AMFBS_HasStdEnc_HasMips3,
5139
  AMFBS_HasStdEnc_HasMips32,
5140
  AMFBS_HasStdEnc_HasMips32r6,
5141
  AMFBS_HasStdEnc_HasMips64,
5142
  AMFBS_HasStdEnc_HasMips64r6,
5143
  AMFBS_HasStdEnc_IsNotSoftFloat,
5144
  AMFBS_HasStdEnc_NotInMicroMips,
5145
  AMFBS_HasStdEnc_NotMips3,
5146
  AMFBS_InMicroMips_HasDSP,
5147
  AMFBS_InMicroMips_HasDSPR2,
5148
  AMFBS_InMicroMips_HasDSPR3,
5149
  AMFBS_InMicroMips_HasEVA,
5150
  AMFBS_InMicroMips_HasMips32r6,
5151
  AMFBS_InMicroMips_IsNotSoftFloat,
5152
  AMFBS_InMicroMips_NotMips32r6,
5153
  AMFBS_IsFP64bit_IsNotSoftFloat,
5154
  AMFBS_IsGP32bit_NotInMicroMips,
5155
  AMFBS_IsGP64bit_NotInMicroMips,
5156
  AMFBS_NotFP64bit_IsNotSoftFloat,
5157
  AMFBS_NotInMips16Mode_HasDSP,
5158
  AMFBS_NotInMips16Mode_IsPTR64bit,
5159
  AMFBS_HasMips3_NotMips64r6_NotCnMips,
5160
  AMFBS_HasMips64_HasCnMips_NotInMicroMips,
5161
  AMFBS_HasStdEnc_HasMSA_HasMips64,
5162
  AMFBS_HasStdEnc_HasMT_NotInMicroMips,
5163
  AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat,
5164
  AMFBS_HasStdEnc_HasMips2_NotInMicroMips,
5165
  AMFBS_HasStdEnc_HasMips3_NotInMicroMips,
5166
  AMFBS_HasStdEnc_HasMips32_NotInMicroMips,
5167
  AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips,
5168
  AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips,
5169
  AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips,
5170
  AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips,
5171
  AMFBS_HasStdEnc_HasMips64_NotInMicroMips,
5172
  AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips,
5173
  AMFBS_HasStdEnc_HasMips64r5_HasVirt,
5174
  AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips,
5175
  AMFBS_HasStdEnc_IsGP32bit_HasMips32r6,
5176
  AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips,
5177
  AMFBS_HasStdEnc_IsGP64bit_HasMips3,
5178
  AMFBS_HasStdEnc_IsGP64bit_HasMips32r6,
5179
  AMFBS_HasStdEnc_IsGP64bit_HasMips64r6,
5180
  AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips,
5181
  AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat,
5182
  AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards,
5183
  AMFBS_HasStdEnc_NotMips32r6_NotMips64r6,
5184
  AMFBS_InMicroMips_HasMips32r5_HasVirt,
5185
  AMFBS_InMicroMips_HasMips32r6_HasGINV,
5186
  AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat,
5187
  AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat,
5188
  AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat,
5189
  AMFBS_InMicroMips_NotMips32r6_HasDSP,
5190
  AMFBS_InMicroMips_NotMips32r6_HasEVA,
5191
  AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat,
5192
  AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips,
5193
  AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips,
5194
  AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips,
5195
  AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6,
5196
  AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips,
5197
  AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6,
5198
  AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6,
5199
  AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips,
5200
  AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6,
5201
  AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips,
5202
  AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips,
5203
  AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips,
5204
  AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips,
5205
  AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
5206
  AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5207
  AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips,
5208
  AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips,
5209
  AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips,
5210
  AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat,
5211
  AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips,
5212
  AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips,
5213
  AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips,
5214
  AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips,
5215
  AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips,
5216
  AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat,
5217
  AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips,
5218
  AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips,
5219
  AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat,
5220
  AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat,
5221
  AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat,
5222
  AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4,
5223
  AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
5224
  AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips,
5225
  AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips,
5226
  AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips,
5227
  AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips,
5228
  AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
5229
  AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
5230
  AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
5231
  AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips,
5232
  AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips,
5233
  AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5234
  AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips,
5235
  AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips,
5236
  AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips,
5237
  AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips,
5238
  AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5239
  AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips,
5240
  AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4,
5241
  AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5242
  AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips,
5243
  AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5244
  AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat,
5245
  AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5246
  AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
5247
  AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips,
5248
  AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5249
  AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5250
  AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5251
  AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D,
5252
  AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5253
  AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5254
  AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5255
  AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5256
  AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5257
  AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips,
5258
  AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5259
  AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5260
  AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips,
5261
  AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4,
5262
};
5263
5264
static constexpr FeatureBitset FeatureBitsets[] = {
5265
  {}, // AMFBS_None
5266
  {Feature_HasCnMipsBit, },
5267
  {Feature_HasCnMipsPBit, },
5268
  {Feature_HasDSPBit, },
5269
  {Feature_HasDSPR2Bit, },
5270
  {Feature_HasMTBit, },
5271
  {Feature_InMicroMipsBit, },
5272
  {Feature_InMips16ModeBit, },
5273
  {Feature_IsGP32bitBit, },
5274
  {Feature_IsGP64bitBit, },
5275
  {Feature_IsNotSoftFloatBit, },
5276
  {Feature_NotCnMipsBit, },
5277
  {Feature_NotInMicroMipsBit, },
5278
  {Feature_HasDSPBit, Feature_InMicroMipsBit, },
5279
  {Feature_HasDSPBit, Feature_NotInMicroMipsBit, },
5280
  {Feature_HasMTBit, Feature_NotInMicroMipsBit, },
5281
  {Feature_HasMips64Bit, Feature_HasCnMipsBit, },
5282
  {Feature_HasStdEncBit, Feature_HasMSABit, },
5283
  {Feature_HasStdEncBit, Feature_HasMips3Bit, },
5284
  {Feature_HasStdEncBit, Feature_HasMips32Bit, },
5285
  {Feature_HasStdEncBit, Feature_HasMips32r6Bit, },
5286
  {Feature_HasStdEncBit, Feature_HasMips64Bit, },
5287
  {Feature_HasStdEncBit, Feature_HasMips64r6Bit, },
5288
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, },
5289
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, },
5290
  {Feature_HasStdEncBit, Feature_NotMips3Bit, },
5291
  {Feature_InMicroMipsBit, Feature_HasDSPBit, },
5292
  {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, },
5293
  {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, },
5294
  {Feature_InMicroMipsBit, Feature_HasEVABit, },
5295
  {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, },
5296
  {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, },
5297
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, },
5298
  {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
5299
  {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },
5300
  {Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, },
5301
  {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
5302
  {Feature_NotInMips16ModeBit, Feature_HasDSPBit, },
5303
  {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, },
5304
  {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, },
5305
  {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, },
5306
  {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, },
5307
  {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, },
5308
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, },
5309
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, },
5310
  {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },
5311
  {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, },
5312
  {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, },
5313
  {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, },
5314
  {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
5315
  {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, },
5316
  {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotInMicroMipsBit, },
5317
  {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, },
5318
  {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, },
5319
  {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
5320
  {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, },
5321
  {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, },
5322
  {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, },
5323
  {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, },
5324
  {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, },
5325
  {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5326
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
5327
  {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, },
5328
  {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
5329
  {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, },
5330
  {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, },
5331
  {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
5332
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, },
5333
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, },
5334
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, },
5335
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, },
5336
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
5337
  {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, },
5338
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5339
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
5340
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
5341
  {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5342
  {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
5343
  {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
5344
  {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
5345
  {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, },
5346
  {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },
5347
  {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
5348
  {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, },
5349
  {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5350
  {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5351
  {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5352
  {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5353
  {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, },
5354
  {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, },
5355
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, },
5356
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5357
  {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
5358
  {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, },
5359
  {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, },
5360
  {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, },
5361
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, },
5362
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5363
  {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5364
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, },
5365
  {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
5366
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, },
5367
  {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
5368
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5369
  {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5370
  {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5371
  {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5372
  {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5373
  {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
5374
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5375
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5376
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5377
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5378
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5379
  {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5380
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5381
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5382
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5383
  {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5384
  {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, },
5385
  {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, },
5386
  {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5387
  {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, },
5388
  {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5389
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, },
5390
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5391
  {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5392
  {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, },
5393
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5394
  {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
5395
  {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
5396
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, },
5397
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5398
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5399
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5400
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5401
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5402
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, },
5403
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
5404
  {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
5405
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, },
5406
  {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, },
5407
};
5408
5409
namespace {
5410
  struct MatchEntry {
5411
    uint16_t Mnemonic;
5412
    uint16_t Opcode;
5413
    uint16_t ConvertFn;
5414
    uint8_t RequiredFeaturesIdx;
5415
    uint8_t Classes[8];
5416
0
    StringRef getMnemonic() const {
5417
0
      return StringRef(MnemonicTable + Mnemonic + 1,
5418
0
                       MnemonicTable[Mnemonic]);
5419
0
    }
5420
  };
5421
5422
  // Predicate for searching for an opcode.
5423
  struct LessOpcode {
5424
0
    bool operator()(const MatchEntry &LHS, StringRef RHS) {
5425
0
      return LHS.getMnemonic() < RHS;
5426
0
    }
5427
0
    bool operator()(StringRef LHS, const MatchEntry &RHS) {
5428
0
      return LHS < RHS.getMnemonic();
5429
0
    }
5430
0
    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
5431
0
      return LHS.getMnemonic() < RHS.getMnemonic();
5432
0
    }
5433
  };
5434
} // end anonymous namespace
5435
5436
static const MatchEntry MatchTable0[] = {
5437
  { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5438
  { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5439
  { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5440
  { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5441
  { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5442
  { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5443
  { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5444
  { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5445
  { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5446
  { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5447
  { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5448
  { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5449
  { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5450
  { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5451
  { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5452
  { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5453
  { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5454
  { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5455
  { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5456
  { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5457
  { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5458
  { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5459
  { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5460
  { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5461
  { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5462
  { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5463
  { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5464
  { 55 /* add.ps */, Mips::FADD_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5465
  { 62 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5466
  { 62 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5467
  { 62 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5468
  { 68 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5469
  { 76 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5470
  { 84 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5471
  { 92 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5472
  { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5473
  { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5474
  { 100 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5475
  { 100 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5476
  { 105 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, },
5477
  { 105 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
5478
  { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5479
  { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5480
  { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5481
  { 105 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, },
5482
  { 105 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
5483
  { 105 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5484
  { 105 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
5485
  { 105 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, },
5486
  { 105 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, AMFBS_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5487
  { 105 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5488
  { 111 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5489
  { 111 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
5490
  { 111 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, },
5491
  { 119 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, },
5492
  { 129 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5493
  { 137 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, },
5494
  { 145 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, AMFBS_InMicroMips, { MCK_Imm }, },
5495
  { 153 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5496
  { 153 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5497
  { 161 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5498
  { 161 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5499
  { 171 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5500
  { 171 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5501
  { 180 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5502
  { 180 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5503
  { 189 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5504
  { 189 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5505
  { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5506
  { 197 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5507
  { 208 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5508
  { 208 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5509
  { 218 /* addr.ps */, Mips::ADDR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5510
  { 226 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5511
  { 235 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5512
  { 244 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5513
  { 253 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5514
  { 262 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5515
  { 271 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5516
  { 280 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5517
  { 289 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5518
  { 298 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5519
  { 307 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5520
  { 316 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5521
  { 325 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5522
  { 334 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5523
  { 334 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5524
  { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5525
  { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5526
  { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5527
  { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5528
  { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5529
  { 340 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
5530
  { 340 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5531
  { 340 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5532
  { 340 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5533
  { 340 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5534
  { 340 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5535
  { 345 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5536
  { 345 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5537
  { 353 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5538
  { 353 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5539
  { 361 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5540
  { 361 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5541
  { 368 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5542
  { 368 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5543
  { 378 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5544
  { 378 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5545
  { 388 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5546
  { 388 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5547
  { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5548
  { 397 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5549
  { 408 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5550
  { 415 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5551
  { 422 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5552
  { 429 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5553
  { 436 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5554
  { 444 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5555
  { 452 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5556
  { 460 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5557
  { 468 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5558
  { 468 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5559
  { 474 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5560
  { 474 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5561
  { 480 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5562
  { 480 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5563
  { 487 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
5564
  { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5565
  { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5566
  { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5567
  { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5568
  { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5569
  { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5570
  { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
5571
  { 487 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5572
  { 487 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5573
  { 487 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5574
  { 487 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5575
  { 487 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5576
  { 487 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
5577
  { 487 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
5578
  { 491 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5579
  { 497 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5580
  { 497 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
5581
  { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5582
  { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5583
  { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
5584
  { 503 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5585
  { 503 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5586
  { 503 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5587
  { 508 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5588
  { 515 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5589
  { 515 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
5590
  { 522 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5591
  { 522 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
5592
  { 529 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5593
  { 538 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5594
  { 547 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5595
  { 556 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5596
  { 565 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5597
  { 574 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5598
  { 583 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5599
  { 592 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5600
  { 601 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5601
  { 601 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
5602
  { 605 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5603
  { 605 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
5604
  { 611 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5605
  { 619 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5606
  { 627 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5607
  { 635 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5608
  { 643 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5609
  { 651 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5610
  { 659 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5611
  { 667 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5612
  { 675 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5613
  { 684 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5614
  { 693 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5615
  { 702 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5616
  { 711 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5617
  { 720 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5618
  { 729 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5619
  { 738 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5620
  { 747 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
5621
  { 747 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5622
  { 747 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget }, },
5623
  { 747 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, AMFBS_None, { MCK_JumpTarget }, },
5624
  { 747 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, AMFBS_InMips16Mode, { MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5625
  { 749 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5626
  { 749 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips, { MCK_JumpTarget }, },
5627
  { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5628
  { 753 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
5629
  { 759 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, },
5630
  { 759 /* bal */, Mips::BAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5631
  { 759 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, },
5632
  { 763 /* balc */, Mips::BALC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_JumpTarget }, },
5633
  { 763 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5634
  { 768 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5635
  { 768 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
5636
  { 775 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5637
  { 775 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5638
  { 781 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5639
  { 789 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, },
5640
  { 789 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, },
5641
  { 795 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, },
5642
  { 803 /* bc */, Mips::BC, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_JumpTarget }, },
5643
  { 803 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5644
  { 806 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
5645
  { 811 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5646
  { 818 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5647
  { 826 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5648
  { 826 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, },
5649
  { 826 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5650
  { 826 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5651
  { 831 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5652
  { 831 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5653
  { 837 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5654
  { 844 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, },
5655
  { 852 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5656
  { 852 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_JumpTarget }, },
5657
  { 852 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5658
  { 852 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5659
  { 857 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_JumpTarget }, },
5660
  { 857 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, },
5661
  { 863 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5662
  { 870 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5663
  { 878 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5664
  { 885 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, },
5665
  { 893 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5666
  { 900 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5667
  { 907 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5668
  { 914 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5669
  { 921 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5670
  { 929 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5671
  { 937 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5672
  { 945 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5673
  { 953 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5674
  { 953 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5675
  { 953 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5676
  { 957 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5677
  { 957 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5678
  { 957 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5679
  { 962 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5680
  { 962 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5681
  { 967 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5682
  { 967 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5683
  { 967 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5684
  { 967 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5685
  { 972 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5686
  { 972 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5687
  { 979 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5688
  { 979 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5689
  { 987 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5690
  { 987 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5691
  { 987 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5692
  { 987 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5693
  { 993 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5694
  { 1001 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5695
  { 1007 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5696
  { 1007 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5697
  { 1011 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5698
  { 1011 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5699
  { 1011 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5700
  { 1016 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5701
  { 1016 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5702
  { 1021 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5703
  { 1021 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5704
  { 1026 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5705
  { 1026 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5706
  { 1026 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5707
  { 1032 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5708
  { 1032 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5709
  { 1038 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5710
  { 1038 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5711
  { 1043 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5712
  { 1043 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5713
  { 1050 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5714
  { 1050 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5715
  { 1058 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5716
  { 1066 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5717
  { 1074 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5718
  { 1074 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5719
  { 1074 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5720
  { 1080 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5721
  { 1086 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5722
  { 1086 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5723
  { 1090 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5724
  { 1090 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5725
  { 1095 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5726
  { 1095 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5727
  { 1100 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5728
  { 1100 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5729
  { 1106 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5730
  { 1106 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5731
  { 1111 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5732
  { 1111 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5733
  { 1119 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5734
  { 1119 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5735
  { 1119 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5736
  { 1125 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5737
  { 1131 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5738
  { 1139 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5739
  { 1147 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5740
  { 1155 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5741
  { 1163 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5742
  { 1172 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5743
  { 1181 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5744
  { 1190 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5745
  { 1199 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5746
  { 1207 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5747
  { 1215 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5748
  { 1223 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5749
  { 1231 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5750
  { 1240 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5751
  { 1249 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5752
  { 1258 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5753
  { 1267 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5754
  { 1267 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5755
  { 1274 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5756
  { 1274 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
5757
  { 1282 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5758
  { 1282 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5759
  { 1286 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5760
  { 1286 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5761
  { 1291 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5762
  { 1291 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5763
  { 1296 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5764
  { 1296 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5765
  { 1302 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5766
  { 1302 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5767
  { 1307 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5768
  { 1307 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5769
  { 1315 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5770
  { 1315 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5771
  { 1315 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5772
  { 1321 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5773
  { 1327 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5774
  { 1327 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5775
  { 1331 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5776
  { 1331 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5777
  { 1331 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5778
  { 1336 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5779
  { 1336 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5780
  { 1341 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5781
  { 1341 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5782
  { 1346 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5783
  { 1346 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5784
  { 1346 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5785
  { 1352 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5786
  { 1352 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5787
  { 1358 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5788
  { 1358 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5789
  { 1363 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5790
  { 1363 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5791
  { 1370 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5792
  { 1370 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5793
  { 1378 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5794
  { 1386 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5795
  { 1394 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5796
  { 1394 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5797
  { 1394 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5798
  { 1400 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5799
  { 1406 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5800
  { 1413 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5801
  { 1421 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5802
  { 1427 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5803
  { 1434 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5804
  { 1434 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5805
  { 1434 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5806
  { 1438 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5807
  { 1438 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5808
  { 1438 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, },
5809
  { 1443 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5810
  { 1450 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5811
  { 1457 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5812
  { 1464 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5813
  { 1471 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5814
  { 1479 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5815
  { 1487 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5816
  { 1495 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5817
  { 1503 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5818
  { 1503 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, },
5819
  { 1508 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, },
5820
  { 1508 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5821
  { 1508 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5822
  { 1508 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5823
  { 1513 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5824
  { 1513 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5825
  { 1520 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5826
  { 1520 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5827
  { 1528 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5828
  { 1528 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5829
  { 1528 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5830
  { 1528 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
5831
  { 1534 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, },
5832
  { 1542 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
5833
  { 1548 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5834
  { 1548 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5835
  { 1553 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5836
  { 1559 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5837
  { 1565 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5838
  { 1571 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5839
  { 1577 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5840
  { 1583 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5841
  { 1583 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, },
5842
  { 1588 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6_HasDSP, { MCK_JumpTarget }, },
5843
  { 1588 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, AMFBS_HasDSP_NotInMicroMips, { MCK_JumpTarget }, },
5844
  { 1597 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasDSPR3, { MCK_JumpTarget }, },
5845
  { 1607 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
5846
  { 1607 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, AMFBS_InMicroMips, {  }, },
5847
  { 1607 /* break */, Mips::Break16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_0 }, },
5848
  { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
5849
  { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
5850
  { 1607 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5851
  { 1607 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5852
  { 1607 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, AMFBS_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, },
5853
  { 1613 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, },
5854
  { 1613 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
5855
  { 1621 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5856
  { 1628 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
5857
  { 1636 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5858
  { 1643 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5859
  { 1650 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5860
  { 1657 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
5861
  { 1664 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
5862
  { 1672 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
5863
  { 1680 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
5864
  { 1688 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
5865
  { 1696 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, },
5866
  { 1696 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5867
  { 1702 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16 }, },
5868
  { 1702 /* btnez */, Mips::Btnez16, Convert__SImm161_0, AMFBS_InMips16Mode, { MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
5869
  { 1708 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5870
  { 1713 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5871
  { 1718 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5872
  { 1723 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5873
  { 1728 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, },
5874
  { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5875
  { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5876
  { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5877
  { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5878
  { 1733 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5879
  { 1733 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5880
  { 1733 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5881
  { 1733 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5882
  { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5883
  { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5884
  { 1740 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5885
  { 1740 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5886
  { 1747 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5887
  { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5888
  { 1747 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5889
  { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5890
  { 1747 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5891
  { 1747 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5892
  { 1747 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5893
  { 1747 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5894
  { 1753 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5895
  { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5896
  { 1753 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5897
  { 1753 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5898
  { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5899
  { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5900
  { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5901
  { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5902
  { 1759 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5903
  { 1759 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5904
  { 1759 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5905
  { 1759 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5906
  { 1766 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5907
  { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5908
  { 1766 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5909
  { 1766 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5910
  { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5911
  { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5912
  { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5913
  { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5914
  { 1773 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5915
  { 1773 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5916
  { 1773 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5917
  { 1773 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5918
  { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5919
  { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5920
  { 1780 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5921
  { 1780 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5922
  { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5923
  { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5924
  { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5925
  { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5926
  { 1787 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5927
  { 1787 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5928
  { 1787 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5929
  { 1787 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5930
  { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5931
  { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5932
  { 1795 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5933
  { 1795 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5934
  { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5935
  { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5936
  { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5937
  { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5938
  { 1803 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5939
  { 1803 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5940
  { 1803 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5941
  { 1803 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5942
  { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5943
  { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5944
  { 1811 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5945
  { 1811 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5946
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5947
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5948
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5949
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5950
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5951
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5952
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5953
  { 1819 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5954
  { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5955
  { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5956
  { 1828 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5957
  { 1828 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5958
  { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5959
  { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5960
  { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5961
  { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5962
  { 1837 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5963
  { 1837 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5964
  { 1837 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5965
  { 1837 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5966
  { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5967
  { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5968
  { 1845 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5969
  { 1845 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5970
  { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5971
  { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5972
  { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5973
  { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5974
  { 1853 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5975
  { 1853 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5976
  { 1853 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5977
  { 1853 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5978
  { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5979
  { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5980
  { 1861 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5981
  { 1861 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5982
  { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5983
  { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5984
  { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5985
  { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5986
  { 1869 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5987
  { 1869 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5988
  { 1869 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5989
  { 1869 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5990
  { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5991
  { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5992
  { 1877 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5993
  { 1877 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
5994
  { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5995
  { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5996
  { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5997
  { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
5998
  { 1885 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
5999
  { 1885 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6000
  { 1885 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6001
  { 1885 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6002
  { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6003
  { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6004
  { 1893 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6005
  { 1893 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6006
  { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6007
  { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6008
  { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6009
  { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6010
  { 1901 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6011
  { 1901 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6012
  { 1901 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6013
  { 1901 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6014
  { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6015
  { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6016
  { 1908 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6017
  { 1908 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6018
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6019
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6020
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6021
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6022
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6023
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6024
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6025
  { 1915 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6026
  { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6027
  { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6028
  { 1923 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6029
  { 1923 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6030
  { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6031
  { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6032
  { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6033
  { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6034
  { 1931 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6035
  { 1931 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6036
  { 1931 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6037
  { 1931 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6038
  { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6039
  { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6040
  { 1939 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6041
  { 1939 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6042
  { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6043
  { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6044
  { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6045
  { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6046
  { 1947 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6047
  { 1947 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6048
  { 1947 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6049
  { 1947 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6050
  { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6051
  { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6052
  { 1955 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6053
  { 1955 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6054
  { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6055
  { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6056
  { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6057
  { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6058
  { 1963 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6059
  { 1963 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6060
  { 1963 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6061
  { 1963 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6062
  { 1970 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6063
  { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6064
  { 1970 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6065
  { 1970 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6066
  { 1977 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
6067
  { 1977 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
6068
  { 1977 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
6069
  { 1977 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
6070
  { 1983 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
6071
  { 1983 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
6072
  { 1990 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6073
  { 1990 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6074
  { 1999 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6075
  { 1999 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6076
  { 2008 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6077
  { 2008 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6078
  { 2008 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6079
  { 2008 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6080
  { 2017 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6081
  { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6082
  { 2017 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6083
  { 2026 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6084
  { 2032 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6085
  { 2038 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6086
  { 2044 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6087
  { 2050 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6088
  { 2057 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6089
  { 2064 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6090
  { 2071 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6091
  { 2078 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6092
  { 2078 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6093
  { 2083 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6094
  { 2088 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, },
6095
  { 2095 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6096
  { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6097
  { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6098
  { 2101 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6099
  { 2101 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6100
  { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6101
  { 2106 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6102
  { 2113 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6103
  { 2113 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6104
  { 2121 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6105
  { 2121 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6106
  { 2129 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6107
  { 2137 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6108
  { 2145 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6109
  { 2153 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6110
  { 2161 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6111
  { 2169 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6112
  { 2177 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6113
  { 2185 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6114
  { 2193 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6115
  { 2202 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6116
  { 2211 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6117
  { 2220 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6118
  { 2229 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6119
  { 2238 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6120
  { 2247 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6121
  { 2256 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6122
  { 2265 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6123
  { 2265 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6124
  { 2265 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6125
  { 2265 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6126
  { 2269 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6127
  { 2277 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6128
  { 2285 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6129
  { 2293 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6130
  { 2301 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6131
  { 2309 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6132
  { 2317 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6133
  { 2325 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6134
  { 2333 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6135
  { 2342 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6136
  { 2351 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6137
  { 2360 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6138
  { 2369 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6139
  { 2378 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6140
  { 2387 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6141
  { 2396 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6142
  { 2405 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6143
  { 2405 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6144
  { 2405 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6145
  { 2405 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6146
  { 2409 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
6147
  { 2413 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6148
  { 2413 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6149
  { 2422 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6150
  { 2422 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6151
  { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6152
  { 2431 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6153
  { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6154
  { 2440 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6155
  { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6156
  { 2450 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6157
  { 2459 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6158
  { 2459 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6159
  { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6160
  { 2468 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6161
  { 2478 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6162
  { 2478 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6163
  { 2487 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6164
  { 2487 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6165
  { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6166
  { 2496 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6167
  { 2506 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6168
  { 2506 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6169
  { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6170
  { 2515 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6171
  { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6172
  { 2525 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6173
  { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6174
  { 2535 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6175
  { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6176
  { 2545 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6177
  { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6178
  { 2555 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6179
  { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6180
  { 2565 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6181
  { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6182
  { 2575 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6183
  { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6184
  { 2585 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6185
  { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6186
  { 2595 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6187
  { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6188
  { 2606 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6189
  { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6190
  { 2617 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6191
  { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6192
  { 2628 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6193
  { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6194
  { 2639 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6195
  { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6196
  { 2650 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6197
  { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6198
  { 2661 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6199
  { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6200
  { 2671 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6201
  { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6202
  { 2681 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6203
  { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6204
  { 2691 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6205
  { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6206
  { 2701 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6207
  { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6208
  { 2711 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6209
  { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6210
  { 2721 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6211
  { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6212
  { 2731 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6213
  { 2741 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6214
  { 2741 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6215
  { 2750 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6216
  { 2750 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6217
  { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6218
  { 2759 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6219
  { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6220
  { 2772 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6221
  { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6222
  { 2785 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6223
  { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6224
  { 2798 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6225
  { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6226
  { 2810 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6227
  { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6228
  { 2822 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6229
  { 2834 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
6230
  { 2834 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6231
  { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6232
  { 2839 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6233
  { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6234
  { 2850 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6235
  { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6236
  { 2861 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6237
  { 2872 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
6238
  { 2881 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
6239
  { 2890 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
6240
  { 2899 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
6241
  { 2908 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
6242
  { 2917 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
6243
  { 2926 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
6244
  { 2935 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6245
  { 2942 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6246
  { 2950 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6247
  { 2958 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6248
  { 2966 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6249
  { 2974 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6250
  { 2981 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6251
  { 2988 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6252
  { 2995 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6253
  { 2995 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, },
6254
  { 3000 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
6255
  { 3005 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, },
6256
  { 3012 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
6257
  { 3018 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6258
  { 3018 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6259
  { 3026 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6260
  { 3026 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6261
  { 3026 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6262
  { 3026 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6263
  { 3034 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6264
  { 3034 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, },
6265
  { 3034 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6266
  { 3034 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6267
  { 3042 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6268
  { 3042 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6269
  { 3042 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6270
  { 3050 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6271
  { 3050 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6272
  { 3050 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6273
  { 3058 /* cvt.ps.pw */, Mips::CVT_PS_PW64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6274
  { 3068 /* cvt.ps.s */, Mips::CVT_PS_S64, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6275
  { 3077 /* cvt.pw.ps */, Mips::CVT_PW_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6276
  { 3087 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6277
  { 3087 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6278
  { 3087 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6279
  { 3087 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6280
  { 3095 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6281
  { 3095 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6282
  { 3103 /* cvt.s.pl */, Mips::CVT_S_PL64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6283
  { 3112 /* cvt.s.pu */, Mips::CVT_S_PU64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6284
  { 3121 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6285
  { 3121 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6286
  { 3121 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6287
  { 3129 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6288
  { 3129 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6289
  { 3129 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6290
  { 3129 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6291
  { 3137 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6292
  { 3137 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6293
  { 3137 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6294
  { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6295
  { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6296
  { 3145 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6297
  { 3145 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6298
  { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6299
  { 3150 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6300
  { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6301
  { 3156 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6302
  { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6303
  { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, },
6304
  { 3163 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6305
  { 3163 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, },
6306
  { 3169 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6307
  { 3174 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, },
6308
  { 3181 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, },
6309
  { 3186 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, },
6310
  { 3191 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6311
  { 3200 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6312
  { 3200 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6313
  { 3205 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6314
  { 3205 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6315
  { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6316
  { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6317
  { 3210 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6318
  { 3210 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6319
  { 3210 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6320
  { 3210 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6321
  { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6322
  { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
6323
  { 3215 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6324
  { 3215 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6325
  { 3215 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6326
  { 3215 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
6327
  { 3221 /* deret */, Mips::DERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, {  }, },
6328
  { 3221 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
6329
  { 3221 /* deret */, Mips::DERET_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
6330
  { 3227 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6331
  { 3227 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6332
  { 3227 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, },
6333
  { 3232 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, },
6334
  { 3238 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6335
  { 3244 /* di */, Mips::DI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, {  }, },
6336
  { 3244 /* di */, Mips::DI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, {  }, },
6337
  { 3244 /* di */, Mips::DI_MM, Convert__regZERO, AMFBS_InMicroMips, {  }, },
6338
  { 3244 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
6339
  { 3244 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6340
  { 3244 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6341
  { 3247 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6342
  { 3247 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6343
  { 3247 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, },
6344
  { 3252 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, },
6345
  { 3258 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, },
6346
  { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6347
  { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6348
  { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6349
  { 3264 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6350
  { 3264 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6351
  { 3264 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6352
  { 3264 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6353
  { 3264 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6354
  { 3264 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6355
  { 3264 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6356
  { 3264 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6357
  { 3268 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6358
  { 3268 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6359
  { 3268 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6360
  { 3268 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6361
  { 3274 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6362
  { 3274 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6363
  { 3274 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6364
  { 3280 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6365
  { 3288 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6366
  { 3296 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6367
  { 3304 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6368
  { 3312 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6369
  { 3320 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6370
  { 3328 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6371
  { 3336 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6372
  { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6373
  { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, },
6374
  { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, },
6375
  { 3344 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, },
6376
  { 3344 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, },
6377
  { 3344 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6378
  { 3344 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6379
  { 3344 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6380
  { 3344 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6381
  { 3344 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6382
  { 3344 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
6383
  { 3349 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6384
  { 3349 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Mem }, },
6385
  { 3353 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR64AsmReg, MCK_Imm }, },
6386
  { 3357 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6387
  { 3357 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, },
6388
  { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6389
  { 3362 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6390
  { 3368 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6391
  { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6392
  { 3374 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6393
  { 3374 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6394
  { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6395
  { 3380 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6396
  { 3387 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6397
  { 3392 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6398
  { 3398 /* dmt */, Mips::DMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, {  }, },
6399
  { 3398 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6400
  { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6401
  { 3402 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6402
  { 3408 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, },
6403
  { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_None, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, },
6404
  { 3414 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, },
6405
  { 3414 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
6406
  { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, },
6407
  { 3420 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips64r5_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
6408
  { 3427 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6409
  { 3432 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6410
  { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6411
  { 3438 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasMips3_NotMips64r6_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6412
  { 3438 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6413
  { 3438 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6414
  { 3438 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6415
  { 3443 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6416
  { 3449 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6417
  { 3456 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6418
  { 3462 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6419
  { 3469 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6420
  { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6421
  { 3475 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6422
  { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg }, },
6423
  { 3480 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6424
  { 3486 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6425
  { 3495 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6426
  { 3504 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6427
  { 3513 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6428
  { 3522 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6429
  { 3531 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6430
  { 3540 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6431
  { 3540 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6432
  { 3549 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6433
  { 3559 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6434
  { 3569 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6435
  { 3579 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6436
  { 3589 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6437
  { 3599 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6438
  { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6439
  { 3609 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6440
  { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6441
  { 3621 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6442
  { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6443
  { 3633 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6444
  { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6445
  { 3646 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6446
  { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6447
  { 3660 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6448
  { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6449
  { 3671 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6450
  { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6451
  { 3682 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6452
  { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
6453
  { 3692 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6454
  { 3697 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6455
  { 3697 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6456
  { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6457
  { 3706 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6458
  { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6459
  { 3718 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6460
  { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6461
  { 3730 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6462
  { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6463
  { 3743 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6464
  { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6465
  { 3757 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6466
  { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6467
  { 3768 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6468
  { 3779 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6469
  { 3789 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6470
  { 3799 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6471
  { 3809 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6472
  { 3819 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6473
  { 3829 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6474
  { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6475
  { 3839 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6476
  { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6477
  { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6478
  { 3849 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6479
  { 3849 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6480
  { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6481
  { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6482
  { 3854 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6483
  { 3854 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, },
6484
  { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6485
  { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6486
  { 3860 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6487
  { 3860 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6488
  { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6489
  { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, },
6490
  { 3865 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6491
  { 3865 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
6492
  { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6493
  { 3870 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6494
  { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6495
  { 3876 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6496
  { 3884 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6497
  { 3891 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6498
  { 3896 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6499
  { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6500
  { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6501
  { 3901 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6502
  { 3901 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6503
  { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6504
  { 3906 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6505
  { 3913 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6506
  { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6507
  { 3919 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6508
  { 3919 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6509
  { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6510
  { 3924 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6511
  { 3931 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6512
  { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6513
  { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6514
  { 3937 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6515
  { 3937 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, },
6516
  { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6517
  { 3942 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, },
6518
  { 3949 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, },
6519
  { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6520
  { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6521
  { 3955 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6522
  { 3955 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6523
  { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, },
6524
  { 3960 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6525
  { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6526
  { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, },
6527
  { 3966 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6528
  { 3966 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, },
6529
  { 3972 /* dvp */, Mips::DVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, {  }, },
6530
  { 3972 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, {  }, },
6531
  { 3972 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6532
  { 3972 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6533
  { 3976 /* dvpe */, Mips::DVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, {  }, },
6534
  { 3976 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6535
  { 3981 /* ehb */, Mips::EHB, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
6536
  { 3981 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
6537
  { 3981 /* ehb */, Mips::EHB_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
6538
  { 3985 /* ei */, Mips::EI, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, {  }, },
6539
  { 3985 /* ei */, Mips::EI_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, {  }, },
6540
  { 3985 /* ei */, Mips::EI_MM, Convert__regZERO, AMFBS_InMicroMips, {  }, },
6541
  { 3985 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
6542
  { 3985 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6543
  { 3985 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
6544
  { 3988 /* emt */, Mips::EMT, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, {  }, },
6545
  { 3988 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6546
  { 3992 /* eret */, Mips::ERET, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, {  }, },
6547
  { 3992 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
6548
  { 3992 /* eret */, Mips::ERET_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
6549
  { 3997 /* eretnc */, Mips::ERETNC, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_NotInMicroMips, {  }, },
6550
  { 3997 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
6551
  { 4004 /* evp */, Mips::EVP, Convert__regZERO, AMFBS_HasStdEnc_HasMips32r6, {  }, },
6552
  { 4004 /* evp */, Mips::EVP_MMR6, Convert__regZERO, AMFBS_InMicroMips_HasMips32r6, {  }, },
6553
  { 4004 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6554
  { 4004 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6555
  { 4008 /* evpe */, Mips::EVPE, Convert__regZERO, AMFBS_HasMT_NotInMicroMips, {  }, },
6556
  { 4008 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
6557
  { 4013 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6558
  { 4013 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6559
  { 4013 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6560
  { 4017 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6561
  { 4017 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6562
  { 4022 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6563
  { 4022 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6564
  { 4029 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6565
  { 4029 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6566
  { 4037 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6567
  { 4037 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6568
  { 4043 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6569
  { 4043 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6570
  { 4050 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6571
  { 4050 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6572
  { 4059 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6573
  { 4059 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6574
  { 4069 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6575
  { 4069 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, },
6576
  { 4078 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6577
  { 4078 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6578
  { 4086 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6579
  { 4086 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6580
  { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6581
  { 4096 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6582
  { 4107 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6583
  { 4107 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
6584
  { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6585
  { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6586
  { 4117 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6587
  { 4117 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, },
6588
  { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6589
  { 4122 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, AMFBS_HasMips64_HasCnMips_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, },
6590
  { 4129 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6591
  { 4136 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6592
  { 4143 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6593
  { 4150 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6594
  { 4157 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6595
  { 4164 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6596
  { 4171 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6597
  { 4180 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6598
  { 4189 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6599
  { 4196 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6600
  { 4203 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6601
  { 4210 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6602
  { 4217 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6603
  { 4224 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6604
  { 4231 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6605
  { 4238 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6606
  { 4245 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6607
  { 4253 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6608
  { 4261 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6609
  { 4269 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6610
  { 4277 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6611
  { 4285 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6612
  { 4293 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6613
  { 4300 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6614
  { 4307 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6615
  { 4315 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6616
  { 4323 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6617
  { 4330 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6618
  { 4337 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6619
  { 4345 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6620
  { 4353 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6621
  { 4361 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6622
  { 4369 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6623
  { 4378 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6624
  { 4387 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6625
  { 4396 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6626
  { 4405 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6627
  { 4415 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6628
  { 4425 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6629
  { 4435 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6630
  { 4445 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6631
  { 4452 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6632
  { 4459 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6633
  { 4466 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6634
  { 4473 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6635
  { 4480 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, },
6636
  { 4487 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6637
  { 4494 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, },
6638
  { 4501 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6639
  { 4509 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6640
  { 4517 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6641
  { 4517 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6642
  { 4527 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6643
  { 4527 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
6644
  { 4537 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6645
  { 4537 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6646
  { 4537 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
6647
  { 4537 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
6648
  { 4547 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6649
  { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6650
  { 4547 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6651
  { 4557 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6652
  { 4565 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6653
  { 4573 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6654
  { 4580 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6655
  { 4587 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6656
  { 4596 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6657
  { 4605 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6658
  { 4612 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6659
  { 4619 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6660
  { 4628 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6661
  { 4637 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6662
  { 4645 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6663
  { 4653 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6664
  { 4660 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6665
  { 4667 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6666
  { 4672 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6667
  { 4679 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6668
  { 4686 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6669
  { 4694 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6670
  { 4702 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6671
  { 4711 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6672
  { 4720 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6673
  { 4727 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6674
  { 4734 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6675
  { 4741 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6676
  { 4748 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6677
  { 4755 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6678
  { 4762 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6679
  { 4769 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6680
  { 4776 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6681
  { 4783 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6682
  { 4790 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6683
  { 4797 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6684
  { 4804 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6685
  { 4812 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6686
  { 4820 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6687
  { 4827 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6688
  { 4834 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6689
  { 4842 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6690
  { 4850 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6691
  { 4858 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6692
  { 4866 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6693
  { 4874 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6694
  { 4882 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6695
  { 4889 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6696
  { 4896 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6697
  { 4904 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6698
  { 4912 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6699
  { 4922 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6700
  { 4932 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6701
  { 4942 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6702
  { 4952 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6703
  { 4958 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6704
  { 4964 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6705
  { 4975 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6706
  { 4986 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6707
  { 4997 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6708
  { 5008 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg }, },
6709
  { 5008 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg }, },
6710
  { 5014 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6711
  { 5014 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, AMFBS_InMicroMips_HasMips32r6_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, },
6712
  { 5020 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6713
  { 5029 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6714
  { 5038 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6715
  { 5047 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6716
  { 5056 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6717
  { 5065 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6718
  { 5074 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6719
  { 5083 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6720
  { 5092 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6721
  { 5101 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6722
  { 5110 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6723
  { 5119 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6724
  { 5128 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
6725
  { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
6726
  { 5128 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_ConstantUImm10_0 }, },
6727
  { 5128 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_ConstantUImm10_0 }, },
6728
  { 5136 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6729
  { 5144 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6730
  { 5152 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6731
  { 5160 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6732
  { 5168 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6733
  { 5175 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6734
  { 5182 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6735
  { 5189 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6736
  { 5196 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6737
  { 5204 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6738
  { 5212 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6739
  { 5220 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6740
  { 5228 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6741
  { 5235 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6742
  { 5242 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6743
  { 5249 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6744
  { 5256 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6745
  { 5256 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6746
  { 5256 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, },
6747
  { 5260 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, },
6748
  { 5269 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, AMFBS_HasStdEnc_HasMSA_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, },
6749
  { 5278 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, },
6750
  { 5287 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, },
6751
  { 5296 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6752
  { 5296 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6753
  { 5301 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6754
  { 5309 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6755
  { 5317 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6756
  { 5325 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, },
6757
  { 5333 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
6758
  { 5333 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6759
  { 5333 /* j */, Mips::J_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6760
  { 5333 /* j */, Mips::J, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
6761
  { 5335 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, AMFBS_None, { MCK_GPR32AsmReg }, },
6762
  { 5335 /* jal */, Mips::JAL_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6763
  { 5335 /* jal */, Mips::JAL, Convert__JumpTarget1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_JumpTarget }, },
6764
  { 5335 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_JumpTarget }, },
6765
  { 5335 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6766
  { 5339 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6767
  { 5339 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6768
  { 5339 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg }, },
6769
  { 5339 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6770
  { 5339 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6771
  { 5339 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_NotInMips16Mode_IsPTR64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6772
  { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32_NotInMicroMips, { MCK_GPR32AsmReg }, },
6773
  { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotInMicroMips, { MCK_GPR64AsmReg }, },
6774
  { 5344 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6775
  { 5344 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
6776
  { 5352 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
6777
  { 5352 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6778
  { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6779
  { 5352 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6780
  { 5352 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6781
  { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6782
  { 5358 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6783
  { 5367 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6784
  { 5373 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6785
  { 5381 /* jals */, Mips::JALS_MM, Convert__Imm1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_Imm }, },
6786
  { 5386 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_JumpTarget }, },
6787
  { 5386 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_JumpTarget }, },
6788
  { 5391 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6789
  { 5391 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6790
  { 5391 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6791
  { 5397 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6792
  { 5397 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, },
6793
  { 5397 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6794
  { 5401 /* jr */, Mips::JrRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, },
6795
  { 5401 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6796
  { 5401 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
6797
  { 5401 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6798
  { 5401 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, { MCK_GPR64AsmReg }, },
6799
  { 5401 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6800
  { 5404 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg }, },
6801
  { 5404 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg }, },
6802
  { 5404 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg }, },
6803
  { 5404 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg }, },
6804
  { 5410 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6805
  { 5415 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_NotMips32r6, { MCK_UImm5Lsl2 }, },
6806
  { 5425 /* jrc */, Mips::JrcRa16, Convert_NoOperands, AMFBS_InMips16Mode, { MCK_CPURAReg }, },
6807
  { 5425 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
6808
  { 5425 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6, { MCK_GPR32AsmReg }, },
6809
  { 5425 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
6810
  { 5425 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg }, },
6811
  { 5429 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
6812
  { 5435 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm5Lsl2 }, },
6813
  { 5446 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6814
  { 5446 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6815
  { 5450 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6816
  { 5454 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6817
  { 5454 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
6818
  { 5457 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6819
  { 5457 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6820
  { 5462 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6821
  { 5462 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6822
  { 5462 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6823
  { 5465 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6824
  { 5465 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6825
  { 5469 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6826
  { 5469 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6827
  { 5469 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6828
  { 5473 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6829
  { 5479 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6830
  { 5479 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, },
6831
  { 5484 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6832
  { 5484 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6833
  { 5489 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6834
  { 5489 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6835
  { 5492 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, },
6836
  { 5497 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
6837
  { 5502 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
6838
  { 5507 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
6839
  { 5512 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6840
  { 5512 /* ldc1 */, Mips::LDC1_MM_D32, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6841
  { 5512 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6842
  { 5512 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6843
  { 5512 /* ldc1 */, Mips::LDC1_MM_D64, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
6844
  { 5517 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6845
  { 5517 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6846
  { 5517 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
6847
  { 5522 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
6848
  { 5527 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6849
  { 5533 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6850
  { 5539 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6851
  { 5545 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, },
6852
  { 5551 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
6853
  { 5555 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, },
6854
  { 5560 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
6855
  { 5564 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6856
  { 5564 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6857
  { 5570 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6858
  { 5570 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6859
  { 5573 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6860
  { 5573 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6861
  { 5577 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6862
  { 5577 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6863
  { 5581 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6864
  { 5587 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6865
  { 5587 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6866
  { 5592 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6867
  { 5592 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6868
  { 5596 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
6869
  { 5596 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
6870
  { 5596 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6871
  { 5599 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6872
  { 5599 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, },
6873
  { 5599 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, },
6874
  { 5604 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Imm }, },
6875
  { 5604 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, AMFBS_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, },
6876
  { 5609 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6877
  { 5609 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, },
6878
  { 5614 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6879
  { 5614 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
6880
  { 5614 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6881
  { 5614 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6882
  { 5614 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6883
  { 5614 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6884
  { 5617 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6885
  { 5617 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
6886
  { 5621 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6887
  { 5621 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6888
  { 5625 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6889
  { 5625 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6890
  { 5625 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, },
6891
  { 5629 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
6892
  { 5629 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
6893
  { 5629 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, },
6894
  { 5633 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6895
  { 5633 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6896
  { 5633 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6897
  { 5639 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, },
6898
  { 5639 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
6899
  { 5639 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6900
  { 5639 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6901
  { 5639 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
6902
  { 5639 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6903
  { 5639 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6904
  { 5639 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, },
6905
  { 5639 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
6906
  { 5639 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
6907
  { 5642 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, AMFBS_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, },
6908
  { 5647 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6909
  { 5647 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
6910
  { 5652 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6911
  { 5652 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
6912
  { 5652 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
6913
  { 5657 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
6914
  { 5662 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6915
  { 5662 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6916
  { 5666 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6917
  { 5666 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6918
  { 5670 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6919
  { 5670 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6920
  { 5675 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
6921
  { 5679 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6922
  { 5679 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
6923
  { 5685 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
6924
  { 5691 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, },
6925
  { 5695 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6926
  { 5695 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6927
  { 5700 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
6928
  { 5700 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
6929
  { 5704 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6930
  { 5704 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
6931
  { 5709 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm12_02_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, },
6932
  { 5709 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, },
6933
  { 5713 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, AMFBS_HasStdEnc_HasMips64r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, },
6934
  { 5719 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6935
  { 5719 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6936
  { 5723 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6937
  { 5723 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6938
  { 5729 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
6939
  { 5734 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6940
  { 5734 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6941
  { 5734 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6942
  { 5734 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6943
  { 5739 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6944
  { 5739 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
6945
  { 5739 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6946
  { 5746 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6947
  { 5746 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6948
  { 5753 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6949
  { 5762 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6950
  { 5771 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6951
  { 5771 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6952
  { 5779 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6953
  { 5779 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6954
  { 5787 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6955
  { 5797 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6956
  { 5807 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6957
  { 5807 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6958
  { 5807 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6959
  { 5807 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6960
  { 5813 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6961
  { 5821 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6962
  { 5829 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6963
  { 5837 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6964
  { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6965
  { 5845 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6966
  { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6967
  { 5857 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6968
  { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6969
  { 5869 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6970
  { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6971
  { 5882 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
6972
  { 5895 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6973
  { 5895 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6974
  { 5901 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6975
  { 5901 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6976
  { 5907 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6977
  { 5915 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6978
  { 5923 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6979
  { 5931 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6980
  { 5939 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6981
  { 5947 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6982
  { 5955 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6983
  { 5963 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6984
  { 5971 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6985
  { 5979 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6986
  { 5987 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6987
  { 5995 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
6988
  { 6003 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6989
  { 6003 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
6990
  { 6010 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6991
  { 6010 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
6992
  { 6017 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6993
  { 6026 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6994
  { 6035 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6995
  { 6044 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
6996
  { 6053 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6997
  { 6062 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6998
  { 6071 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
6999
  { 6080 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7000
  { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7001
  { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7002
  { 6089 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7003
  { 6089 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7004
  { 6094 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7005
  { 6094 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7006
  { 6094 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7007
  { 6094 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7008
  { 6099 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7009
  { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7010
  { 6099 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
7011
  { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7012
  { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7013
  { 6104 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7014
  { 6104 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7015
  { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7016
  { 6110 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7017
  { 6116 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7018
  { 6116 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7019
  { 6116 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7020
  { 6116 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7021
  { 6122 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7022
  { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7023
  { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7024
  { 6128 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7025
  { 6128 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7026
  { 6135 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7027
  { 6135 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7028
  { 6135 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7029
  { 6135 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7030
  { 6135 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7031
  { 6140 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7032
  { 6147 /* mflo */, Mips::Mflo16, Convert__Reg1_0, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7033
  { 6147 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7034
  { 6147 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7035
  { 6147 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7036
  { 6147 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7037
  { 6152 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7038
  { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7039
  { 6159 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7040
  { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7041
  { 6166 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7042
  { 6172 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7043
  { 6178 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7044
  { 6185 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7045
  { 6192 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7046
  { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7047
  { 6199 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7048
  { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7049
  { 6205 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7050
  { 6211 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
7051
  { 6216 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7052
  { 6216 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7053
  { 6222 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7054
  { 6222 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7055
  { 6228 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7056
  { 6236 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7057
  { 6244 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7058
  { 6252 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7059
  { 6260 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7060
  { 6268 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7061
  { 6276 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7062
  { 6284 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7063
  { 6292 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7064
  { 6300 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7065
  { 6308 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7066
  { 6316 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7067
  { 6324 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7068
  { 6324 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7069
  { 6331 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7070
  { 6331 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7071
  { 6338 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7072
  { 6347 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7073
  { 6356 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7074
  { 6365 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, },
7075
  { 6374 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7076
  { 6383 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7077
  { 6392 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7078
  { 6401 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7079
  { 6410 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7080
  { 6410 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7081
  { 6414 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7082
  { 6422 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7083
  { 6430 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7084
  { 6438 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7085
  { 6446 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7086
  { 6454 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7087
  { 6462 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7088
  { 6470 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7089
  { 6478 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7090
  { 6478 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7091
  { 6485 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7092
  { 6485 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7093
  { 6490 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7094
  { 6490 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7095
  { 6490 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7096
  { 6490 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7097
  { 6490 /* mov.d */, Mips::FMOV_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7098
  { 6496 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7099
  { 6496 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7100
  { 6496 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7101
  { 6502 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, },
7102
  { 6502 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, },
7103
  { 6502 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7104
  { 6502 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7105
  { 6502 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7106
  { 6502 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7107
  { 6502 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, AMFBS_IsGP64bit_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7108
  { 6507 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7109
  { 6514 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7110
  { 6521 /* movep */, Mips::MOVEP_MM, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7111
  { 6521 /* movep */, Mips::MOVEP_MMR6, Convert__GPRMM16AsmRegMovePPairFirst1_0__GPRMM16AsmRegMovePPairSecond1_1__GPRMM16AsmRegMoveP1_2__GPRMM16AsmRegMoveP1_3, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegMovePPairFirst, MCK_GPRMM16AsmRegMovePPairSecond, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, },
7112
  { 6527 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7113
  { 6527 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7114
  { 6532 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7115
  { 6532 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7116
  { 6532 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
7117
  { 6539 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7118
  { 6539 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7119
  { 6546 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7120
  { 6546 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7121
  { 6551 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7122
  { 6551 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7123
  { 6551 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7124
  { 6558 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7125
  { 6558 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7126
  { 6565 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7127
  { 6565 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, },
7128
  { 6570 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7129
  { 6570 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, },
7130
  { 6570 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, },
7131
  { 6577 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7132
  { 6577 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, },
7133
  { 6584 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7134
  { 6584 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7135
  { 6589 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7136
  { 6589 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
7137
  { 6589 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
7138
  { 6596 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7139
  { 6596 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
7140
  { 6603 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7141
  { 6603 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7142
  { 6603 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7143
  { 6603 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7144
  { 6608 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7145
  { 6608 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7146
  { 6608 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7147
  { 6615 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7148
  { 6615 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7149
  { 6622 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7150
  { 6631 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7151
  { 6640 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7152
  { 6640 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7153
  { 6648 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7154
  { 6648 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7155
  { 6656 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7156
  { 6666 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7157
  { 6676 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7158
  { 6676 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7159
  { 6676 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7160
  { 6676 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7161
  { 6682 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7162
  { 6690 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7163
  { 6698 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7164
  { 6706 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7165
  { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7166
  { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7167
  { 6714 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7168
  { 6714 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7169
  { 6719 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7170
  { 6719 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7171
  { 6719 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7172
  { 6719 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7173
  { 6719 /* mtc1 */, Mips::MTC1_D64_MM, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7174
  { 6724 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7175
  { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7176
  { 6724 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, },
7177
  { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7178
  { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7179
  { 6729 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7180
  { 6729 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7181
  { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7182
  { 6735 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7183
  { 6741 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7184
  { 6741 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, },
7185
  { 6741 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7186
  { 6741 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, },
7187
  { 6747 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, },
7188
  { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7189
  { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7190
  { 6753 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7191
  { 6753 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r5_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7192
  { 6760 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7193
  { 6760 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7194
  { 6760 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7195
  { 6760 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, },
7196
  { 6765 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7197
  { 6765 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7198
  { 6772 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg }, },
7199
  { 6772 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7200
  { 6772 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7201
  { 6772 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, },
7202
  { 6777 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7203
  { 6782 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7204
  { 6787 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7205
  { 6792 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7206
  { 6797 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7207
  { 6802 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR64AsmReg }, },
7208
  { 6807 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7209
  { 6807 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7210
  { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, },
7211
  { 6814 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, },
7212
  { 6820 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7213
  { 6826 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg }, },
7214
  { 6833 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7215
  { 6840 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, },
7216
  { 6847 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7217
  { 6847 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7218
  { 6853 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
7219
  { 6853 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, AMFBS_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, },
7220
  { 6859 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, },
7221
  { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7222
  { 6864 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7223
  { 6864 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7224
  { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7225
  { 6868 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7226
  { 6868 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7227
  { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7228
  { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7229
  { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7230
  { 6873 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7231
  { 6873 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7232
  { 6873 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7233
  { 6873 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7234
  { 6873 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7235
  { 6877 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7236
  { 6877 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7237
  { 6877 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7238
  { 6877 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7239
  { 6883 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7240
  { 6883 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7241
  { 6890 /* mul.ps */, Mips::FMUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7242
  { 6897 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7243
  { 6897 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7244
  { 6897 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7245
  { 6903 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7246
  { 6911 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7247
  { 6919 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7248
  { 6919 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7249
  { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7250
  { 6928 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7251
  { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7252
  { 6942 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7253
  { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7254
  { 6956 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7255
  { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7256
  { 6971 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7257
  { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7258
  { 6986 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7259
  { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7260
  { 6991 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7261
  { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7262
  { 6997 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7263
  { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7264
  { 7008 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7265
  { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7266
  { 7018 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7267
  { 7028 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7268
  { 7028 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7269
  { 7037 /* mulr.ps */, Mips::MULR_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7270
  { 7045 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7271
  { 7054 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7272
  { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7273
  { 7063 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7274
  { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7275
  { 7074 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7276
  { 7088 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7277
  { 7088 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7278
  { 7088 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7279
  { 7088 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7280
  { 7093 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7281
  { 7093 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7282
  { 7093 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7283
  { 7093 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7284
  { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7285
  { 7099 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7286
  { 7099 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7287
  { 7104 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7288
  { 7111 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7289
  { 7118 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7290
  { 7125 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7291
  { 7132 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7292
  { 7132 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7293
  { 7132 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7294
  { 7132 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7295
  { 7132 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7296
  { 7132 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7297
  { 7132 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7298
  { 7136 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7299
  { 7136 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7300
  { 7136 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7301
  { 7136 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7302
  { 7142 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7303
  { 7142 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7304
  { 7142 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7305
  { 7148 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7306
  { 7148 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7307
  { 7148 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7308
  { 7148 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7309
  { 7148 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7310
  { 7148 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7311
  { 7153 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7312
  { 7160 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7313
  { 7167 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7314
  { 7174 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7315
  { 7181 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7316
  { 7188 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7317
  { 7195 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7318
  { 7202 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7319
  { 7209 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7320
  { 7209 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7321
  { 7209 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7322
  { 7217 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7323
  { 7217 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7324
  { 7225 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7325
  { 7225 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7326
  { 7225 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7327
  { 7233 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7328
  { 7233 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7329
  { 7241 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
7330
  { 7241 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips_HasMips32r6, {  }, },
7331
  { 7241 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, AMFBS_InMips16Mode, {  }, },
7332
  { 7241 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, AMFBS_InMicroMips, {  }, },
7333
  { 7241 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, AMFBS_InMicroMips, {  }, },
7334
  { 7245 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7335
  { 7245 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7336
  { 7245 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7337
  { 7245 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7338
  { 7245 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7339
  { 7245 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7340
  { 7245 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7341
  { 7249 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7342
  { 7255 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7343
  { 7262 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg }, },
7344
  { 7262 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg }, },
7345
  { 7262 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg }, },
7346
  { 7262 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7347
  { 7262 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7348
  { 7262 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7349
  { 7262 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7350
  { 7266 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7351
  { 7266 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7352
  { 7272 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7353
  { 7272 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7354
  { 7272 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7355
  { 7272 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7356
  { 7272 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7357
  { 7272 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7358
  { 7272 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7359
  { 7272 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
7360
  { 7272 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7361
  { 7272 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7362
  { 7272 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7363
  { 7272 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7364
  { 7272 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7365
  { 7272 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7366
  { 7272 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7367
  { 7275 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7368
  { 7280 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7369
  { 7280 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7370
  { 7285 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7371
  { 7285 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7372
  { 7285 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
7373
  { 7285 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7374
  { 7285 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7375
  { 7285 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
7376
  { 7289 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7377
  { 7295 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7378
  { 7295 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7379
  { 7305 /* pause */, Mips::PAUSE, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, {  }, },
7380
  { 7305 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
7381
  { 7305 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
7382
  { 7311 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7383
  { 7319 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7384
  { 7327 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7385
  { 7335 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7386
  { 7343 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7387
  { 7351 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7388
  { 7359 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7389
  { 7367 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7390
  { 7375 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7391
  { 7382 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7392
  { 7389 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7393
  { 7396 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7394
  { 7403 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7395
  { 7403 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7396
  { 7411 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7397
  { 7411 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7398
  { 7419 /* pll.ps */, Mips::PLL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7399
  { 7426 /* plu.ps */, Mips::PLU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7400
  { 7433 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasCnMips, { MCK_GPR32AsmReg }, },
7401
  { 7433 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7402
  { 7437 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7403
  { 7437 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7404
  { 7450 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7405
  { 7450 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7406
  { 7463 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7407
  { 7463 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7408
  { 7478 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7409
  { 7478 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7410
  { 7494 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7411
  { 7494 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7412
  { 7509 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7413
  { 7509 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7414
  { 7525 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7415
  { 7525 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7416
  { 7539 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7417
  { 7539 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7418
  { 7554 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7419
  { 7554 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7420
  { 7568 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7421
  { 7568 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7422
  { 7583 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7423
  { 7583 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7424
  { 7595 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7425
  { 7595 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7426
  { 7610 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7427
  { 7610 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7428
  { 7627 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7429
  { 7627 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7430
  { 7639 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7431
  { 7639 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7432
  { 7652 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7433
  { 7652 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7434
  { 7667 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7435
  { 7667 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7436
  { 7683 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
7437
  { 7683 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, },
7438
  { 7683 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7439
  { 7683 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, },
7440
  { 7688 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
7441
  { 7688 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm9_02_1__ConstantUImm5_01_0, AMFBS_InMicroMips_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9_0 }, },
7442
  { 7694 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7443
  { 7700 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7444
  { 7700 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7445
  { 7708 /* pul.ps */, Mips::PUL_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7446
  { 7715 /* puu.ps */, Mips::PUU_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7447
  { 7722 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7448
  { 7722 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7449
  { 7733 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
7450
  { 7733 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7451
  { 7739 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7452
  { 7739 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7453
  { 7739 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, },
7454
  { 7739 /* rdhwr */, Mips::RDHWR64, Convert__GPR64AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_HWRegsAsmReg }, },
7455
  { 7739 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, },
7456
  { 7739 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7457
  { 7739 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, },
7458
  { 7745 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7459
  { 7752 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7460
  { 7752 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7461
  { 7752 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7462
  { 7752 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7463
  { 7760 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7464
  { 7760 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7465
  { 7768 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7466
  { 7768 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7467
  { 7768 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7468
  { 7768 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7469
  { 7772 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7470
  { 7772 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7471
  { 7772 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7472
  { 7772 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7473
  { 7777 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7474
  { 7777 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, },
7475
  { 7785 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7476
  { 7785 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, },
7477
  { 7793 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7478
  { 7793 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7479
  { 7802 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7480
  { 7802 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7481
  { 7811 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7482
  { 7811 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7483
  { 7818 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7484
  { 7818 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7485
  { 7825 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7486
  { 7825 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7487
  { 7825 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7488
  { 7825 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7489
  { 7829 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7490
  { 7829 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_SImm16 }, },
7491
  { 7829 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7492
  { 7829 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7493
  { 7833 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7494
  { 7833 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7495
  { 7833 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7496
  { 7833 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7497
  { 7833 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7498
  { 7838 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7499
  { 7838 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7500
  { 7844 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7501
  { 7844 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7502
  { 7854 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7503
  { 7854 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
7504
  { 7864 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7505
  { 7864 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
7506
  { 7864 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
7507
  { 7864 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7508
  { 7874 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7509
  { 7874 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7510
  { 7874 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7511
  { 7884 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7512
  { 7884 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7513
  { 7884 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7514
  { 7884 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7515
  { 7892 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7516
  { 7892 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7517
  { 7900 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7518
  { 7900 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7519
  { 7900 /* s.d */, Mips::SDC1_M1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7520
  { 7900 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7521
  { 7904 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
7522
  { 7908 /* saa */, Mips::SaaAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, },
7523
  { 7908 /* saa */, Mips::SAA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, },
7524
  { 7912 /* saad */, Mips::SaadAddr, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK_Mem }, },
7525
  { 7912 /* saad */, Mips::SAAD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_2, AMFBS_HasCnMipsP, { MCK_GPR64AsmReg, MCK__40_, MCK_GPR64AsmReg, MCK__41_ }, },
7526
  { 7917 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7527
  { 7925 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7528
  { 7933 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7529
  { 7941 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7530
  { 7949 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7531
  { 7957 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7532
  { 7965 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7533
  { 7973 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7534
  { 7981 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7535
  { 7981 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7536
  { 7981 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7537
  { 7981 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7538
  { 7984 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7539
  { 7984 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7540
  { 7989 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7541
  { 7989 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7542
  { 7993 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
7543
  { 7993 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, },
7544
  { 7993 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7545
  { 7993 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7546
  { 7993 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7547
  { 7993 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7548
  { 7996 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
7549
  { 7996 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7550
  { 8000 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7551
  { 8000 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7552
  { 8004 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16_0 }, },
7553
  { 8004 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, AMFBS_HasStdEnc_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, },
7554
  { 8007 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, {  }, },
7555
  { 8007 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, {  }, },
7556
  { 8007 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, {  }, },
7557
  { 8007 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
7558
  { 8007 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7559
  { 8007 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7560
  { 8007 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm20_0 }, },
7561
  { 8013 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_NotMips32r6, { MCK_ConstantUImm4_0 }, },
7562
  { 8013 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm4_0 }, },
7563
  { 8021 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7564
  { 8021 /* sdc1 */, Mips::SDC1_MM_D32, Convert__AFGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7565
  { 8021 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7566
  { 8021 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7567
  { 8021 /* sdc1 */, Mips::SDC1_MM_D64, Convert__FGR64AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16_0 }, },
7568
  { 8026 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
7569
  { 8026 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
7570
  { 8026 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
7571
  { 8031 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
7572
  { 8036 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7573
  { 8040 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, },
7574
  { 8044 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7575
  { 8044 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7576
  { 8050 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7577
  { 8050 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
7578
  { 8050 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7579
  { 8050 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7580
  { 8050 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7581
  { 8054 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs }, },
7582
  { 8054 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg }, },
7583
  { 8054 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg }, },
7584
  { 8054 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7585
  { 8054 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7586
  { 8058 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7587
  { 8058 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7588
  { 8064 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7589
  { 8064 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7590
  { 8070 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7591
  { 8070 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7592
  { 8070 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7593
  { 8077 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7594
  { 8077 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7595
  { 8086 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7596
  { 8086 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7597
  { 8095 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7598
  { 8095 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7599
  { 8095 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7600
  { 8102 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7601
  { 8102 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7602
  { 8111 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7603
  { 8111 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7604
  { 8120 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7605
  { 8120 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7606
  { 8120 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7607
  { 8120 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7608
  { 8120 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7609
  { 8120 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7610
  { 8124 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7611
  { 8124 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7612
  { 8129 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7613
  { 8129 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7614
  { 8129 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7615
  { 8129 /* sge */, Mips::SGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7616
  { 8129 /* sge */, Mips::SGEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7617
  { 8129 /* sge */, Mips::SGEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7618
  { 8133 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7619
  { 8133 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7620
  { 8133 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7621
  { 8133 /* sgeu */, Mips::SGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7622
  { 8133 /* sgeu */, Mips::SGEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7623
  { 8133 /* sgeu */, Mips::SGEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7624
  { 8138 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7625
  { 8138 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7626
  { 8138 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7627
  { 8138 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7628
  { 8138 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7629
  { 8138 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7630
  { 8138 /* sgt */, Mips::SGTImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7631
  { 8138 /* sgt */, Mips::SGTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7632
  { 8142 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7633
  { 8142 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7634
  { 8142 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7635
  { 8142 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7636
  { 8142 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7637
  { 8142 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7638
  { 8142 /* sgtu */, Mips::SGTUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7639
  { 8142 /* sgtu */, Mips::SGTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7640
  { 8147 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7641
  { 8147 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7642
  { 8147 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7643
  { 8147 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7644
  { 8150 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7645
  { 8150 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7646
  { 8155 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7647
  { 8155 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7648
  { 8159 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7649
  { 8165 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7650
  { 8171 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
7651
  { 8177 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7652
  { 8177 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, },
7653
  { 8183 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7654
  { 8183 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, AMFBS_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, },
7655
  { 8190 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7656
  { 8190 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7657
  { 8198 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7658
  { 8198 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7659
  { 8206 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7660
  { 8206 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7661
  { 8216 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7662
  { 8216 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7663
  { 8225 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7664
  { 8225 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7665
  { 8234 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7666
  { 8234 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7667
  { 8243 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7668
  { 8243 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7669
  { 8254 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7670
  { 8254 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7671
  { 8264 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7672
  { 8264 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7673
  { 8272 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7674
  { 8272 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7675
  { 8280 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7676
  { 8280 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7677
  { 8290 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7678
  { 8290 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7679
  { 8300 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7680
  { 8300 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7681
  { 8309 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7682
  { 8309 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7683
  { 8318 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7684
  { 8318 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7685
  { 8327 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7686
  { 8327 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7687
  { 8338 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7688
  { 8338 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7689
  { 8349 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7690
  { 8349 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7691
  { 8359 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7692
  { 8359 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7693
  { 8367 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7694
  { 8367 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, },
7695
  { 8375 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7696
  { 8375 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7697
  { 8384 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7698
  { 8384 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7699
  { 8393 /* sigrie */, Mips::SIGRIE, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, {  }, },
7700
  { 8393 /* sigrie */, Mips::SIGRIE_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, {  }, },
7701
  { 8393 /* sigrie */, Mips::SIGRIE, Convert__UImm161_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_UImm16 }, },
7702
  { 8393 /* sigrie */, Mips::SIGRIE_MMR6, Convert__UImm161_0, AMFBS_InMicroMips_HasMips32r6, { MCK_UImm16 }, },
7703
  { 8400 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7704
  { 8406 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7705
  { 8412 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7706
  { 8418 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7707
  { 8424 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7708
  { 8431 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7709
  { 8438 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7710
  { 8445 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7711
  { 8452 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7712
  { 8452 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7713
  { 8452 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7714
  { 8452 /* sle */, Mips::SLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7715
  { 8452 /* sle */, Mips::SLEImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, },
7716
  { 8452 /* sle */, Mips::SLEImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7717
  { 8456 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7718
  { 8456 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm32_Coerced1_1, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7719
  { 8456 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7720
  { 8456 /* sleu */, Mips::SLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7721
  { 8456 /* sleu */, Mips::SLEUImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm32_Coerced1_2, AMFBS_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm32_Coerced }, },
7722
  { 8456 /* sleu */, Mips::SLEUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7723
  { 8461 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7724
  { 8461 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7725
  { 8461 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7726
  { 8461 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7727
  { 8461 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7728
  { 8461 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7729
  { 8461 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7730
  { 8461 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7731
  { 8461 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7732
  { 8461 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7733
  { 8461 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7734
  { 8461 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7735
  { 8465 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7736
  { 8471 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7737
  { 8477 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7738
  { 8483 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7739
  { 8489 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7740
  { 8489 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7741
  { 8495 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7742
  { 8502 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7743
  { 8509 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7744
  { 8516 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7745
  { 8523 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7746
  { 8523 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7747
  { 8523 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7748
  { 8528 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7749
  { 8528 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7750
  { 8528 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7751
  { 8528 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7752
  { 8528 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7753
  { 8528 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7754
  { 8528 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7755
  { 8528 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7756
  { 8528 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7757
  { 8532 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7758
  { 8532 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7759
  { 8532 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7760
  { 8532 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7761
  { 8537 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, },
7762
  { 8537 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7763
  { 8537 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, },
7764
  { 8537 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__HASH_, MCK_16, MCK_bit, MCK_inst }, },
7765
  { 8543 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7766
  { 8543 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7767
  { 8543 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7768
  { 8543 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, },
7769
  { 8543 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7770
  { 8543 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7771
  { 8543 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7772
  { 8543 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7773
  { 8543 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
7774
  { 8548 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7775
  { 8548 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, },
7776
  { 8548 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7777
  { 8548 /* sne */, Mips::SNEMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7778
  { 8548 /* sne */, Mips::SNEIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
7779
  { 8548 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
7780
  { 8552 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7781
  { 8552 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, },
7782
  { 8557 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7783
  { 8565 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7784
  { 8573 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7785
  { 8581 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, },
7786
  { 8589 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, },
7787
  { 8598 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, },
7788
  { 8607 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, },
7789
  { 8616 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, },
7790
  { 8625 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7791
  { 8625 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7792
  { 8625 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7793
  { 8625 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7794
  { 8632 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7795
  { 8632 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7796
  { 8639 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7797
  { 8639 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7798
  { 8639 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7799
  { 8639 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7800
  { 8639 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7801
  { 8639 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7802
  { 8639 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7803
  { 8639 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7804
  { 8639 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7805
  { 8639 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7806
  { 8643 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7807
  { 8649 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7808
  { 8655 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7809
  { 8661 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7810
  { 8667 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7811
  { 8674 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7812
  { 8681 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7813
  { 8688 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7814
  { 8695 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7815
  { 8702 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7816
  { 8709 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7817
  { 8716 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7818
  { 8723 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7819
  { 8731 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7820
  { 8739 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7821
  { 8747 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7822
  { 8755 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7823
  { 8755 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7824
  { 8755 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7825
  { 8760 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7826
  { 8760 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7827
  { 8760 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7828
  { 8760 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7829
  { 8760 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7830
  { 8760 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, },
7831
  { 8760 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7832
  { 8760 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7833
  { 8760 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7834
  { 8760 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, },
7835
  { 8764 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7836
  { 8770 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7837
  { 8776 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7838
  { 8782 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7839
  { 8788 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7840
  { 8788 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, },
7841
  { 8794 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7842
  { 8801 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7843
  { 8808 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7844
  { 8815 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7845
  { 8822 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7846
  { 8829 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7847
  { 8836 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7848
  { 8843 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7849
  { 8850 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, },
7850
  { 8858 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, },
7851
  { 8866 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, },
7852
  { 8874 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7853
  { 8882 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
7854
  { 8882 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7855
  { 8882 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7856
  { 8887 /* ssnop */, Mips::SSNOP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
7857
  { 8887 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
7858
  { 8887 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
7859
  { 8893 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm10_02_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_0 }, },
7860
  { 8898 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, },
7861
  { 8903 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, },
7862
  { 8908 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, },
7863
  { 8913 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7864
  { 8913 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7865
  { 8913 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7866
  { 8913 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, },
7867
  { 8913 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7868
  { 8913 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7869
  { 8913 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7870
  { 8913 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
7871
  { 8917 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7872
  { 8917 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, },
7873
  { 8917 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7874
  { 8917 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7875
  { 8923 /* sub.ps */, Mips::FSUB_PS64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
7876
  { 8930 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7877
  { 8930 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7878
  { 8930 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
7879
  { 8936 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7880
  { 8936 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7881
  { 8944 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7882
  { 8944 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7883
  { 8954 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7884
  { 8954 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7885
  { 8963 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7886
  { 8963 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7887
  { 8972 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7888
  { 8972 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7889
  { 8980 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7890
  { 8980 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7891
  { 8991 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7892
  { 8991 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7893
  { 9001 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7894
  { 9010 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7895
  { 9019 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7896
  { 9028 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7897
  { 9037 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7898
  { 9046 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7899
  { 9055 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7900
  { 9064 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7901
  { 9073 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7902
  { 9084 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7903
  { 9095 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7904
  { 9106 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7905
  { 9117 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7906
  { 9128 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7907
  { 9139 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7908
  { 9150 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7909
  { 9161 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7910
  { 9161 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7911
  { 9161 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7912
  { 9161 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_InvNum }, },
7913
  { 9161 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, },
7914
  { 9161 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7915
  { 9161 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7916
  { 9161 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7917
  { 9161 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, AMFBS_None, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, },
7918
  { 9166 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7919
  { 9166 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7920
  { 9174 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7921
  { 9174 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7922
  { 9182 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7923
  { 9182 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
7924
  { 9189 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7925
  { 9189 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7926
  { 9199 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7927
  { 9199 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7928
  { 9209 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7929
  { 9209 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7930
  { 9218 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7931
  { 9218 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7932
  { 9229 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7933
  { 9236 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7934
  { 9243 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7935
  { 9250 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
7936
  { 9257 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7937
  { 9265 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7938
  { 9273 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7939
  { 9281 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, },
7940
  { 9289 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7941
  { 9289 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7942
  { 9289 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7943
  { 9295 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7944
  { 9295 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7945
  { 9295 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7946
  { 9295 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_NotInMips16Mode_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
7947
  { 9295 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, },
7948
  { 9295 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7949
  { 9295 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7950
  { 9295 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, },
7951
  { 9295 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, },
7952
  { 9298 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7953
  { 9298 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, },
7954
  { 9303 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
7955
  { 9303 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16_0 }, },
7956
  { 9308 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
7957
  { 9308 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm11_02_1, AMFBS_InMicroMips_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11_0 }, },
7958
  { 9308 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm16_02_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16_0 }, },
7959
  { 9313 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, },
7960
  { 9318 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7961
  { 9318 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7962
  { 9322 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7963
  { 9322 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7964
  { 9326 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7965
  { 9326 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7966
  { 9331 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
7967
  { 9335 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
7968
  { 9335 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, AMFBS_InMicroMips_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, },
7969
  { 9341 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, AMFBS_InMicroMips, { MCK_RegList, MCK_Mem }, },
7970
  { 9347 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12_0 }, },
7971
  { 9351 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, },
7972
  { 9351 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, },
7973
  { 9355 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7974
  { 9355 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm9_02_1, AMFBS_InMicroMips_NotMips32r6_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9_0 }, },
7975
  { 9360 /* swsp */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, },
7976
  { 9365 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7977
  { 9365 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, },
7978
  { 9371 /* sync */, Mips::SYNC, Convert__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, {  }, },
7979
  { 9371 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, AMFBS_InMicroMips_HasMips32r6, {  }, },
7980
  { 9371 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, AMFBS_InMicroMips, {  }, },
7981
  { 9371 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_ConstantUImm5_0 }, },
7982
  { 9371 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm5_0 }, },
7983
  { 9371 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm5_0 }, },
7984
  { 9376 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm16_02_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_MemOffsetSimm16_0 }, },
7985
  { 9376 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_NotMips32r6, { MCK_MemOffsetSimm16_0 }, },
7986
  { 9376 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm16_02_0, AMFBS_InMicroMips_HasMips32r6, { MCK_MemOffsetSimm16_0 }, },
7987
  { 9382 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, AMFBS_HasMips64_HasCnMips, {  }, },
7988
  { 9393 /* syncs */, Mips::SYNC, Convert__imm_95_6, AMFBS_HasMips64_HasCnMips, {  }, },
7989
  { 9399 /* syncw */, Mips::SYNC, Convert__imm_95_4, AMFBS_HasMips64_HasCnMips, {  }, },
7990
  { 9405 /* syncws */, Mips::SYNC, Convert__imm_95_5, AMFBS_HasMips64_HasCnMips, {  }, },
7991
  { 9412 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
7992
  { 9412 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, AMFBS_InMicroMips, {  }, },
7993
  { 9412 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
7994
  { 9412 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, AMFBS_HasStdEnc_NotInMicroMips, { MCK_ConstantUImm20_0 }, },
7995
  { 9420 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7996
  { 9420 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
7997
  { 9420 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
7998
  { 9420 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
7999
  { 9424 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8000
  { 9424 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8001
  { 9429 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8002
  { 9429 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8003
  { 9429 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8004
  { 9429 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8005
  { 9433 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8006
  { 9433 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8007
  { 9438 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8008
  { 9438 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8009
  { 9444 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8010
  { 9444 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8011
  { 9444 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8012
  { 9444 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8013
  { 9449 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
8014
  { 9449 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
8015
  { 9457 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
8016
  { 9457 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
8017
  { 9466 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
8018
  { 9466 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
8019
  { 9472 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
8020
  { 9472 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
8021
  { 9478 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
8022
  { 9478 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
8023
  { 9485 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, {  }, },
8024
  { 9485 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r5_HasVirt, {  }, },
8025
  { 9492 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, {  }, },
8026
  { 9492 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
8027
  { 9499 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, {  }, },
8028
  { 9499 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, AMFBS_InMicroMips_HasMips32r6, {  }, },
8029
  { 9507 /* tlbp */, Mips::TLBP, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
8030
  { 9507 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
8031
  { 9512 /* tlbr */, Mips::TLBR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
8032
  { 9512 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
8033
  { 9517 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
8034
  { 9517 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
8035
  { 9523 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, AMFBS_HasStdEnc_NotInMicroMips, {  }, },
8036
  { 9523 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, AMFBS_InMicroMips, {  }, },
8037
  { 9529 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8038
  { 9529 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8039
  { 9529 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8040
  { 9529 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8041
  { 9533 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8042
  { 9533 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8043
  { 9538 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8044
  { 9538 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8045
  { 9544 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8046
  { 9544 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8047
  { 9544 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8048
  { 9544 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8049
  { 9549 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8050
  { 9549 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8051
  { 9549 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, },
8052
  { 9549 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, AMFBS_HasStdEnc_HasMips2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8053
  { 9553 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8054
  { 9553 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, },
8055
  { 9558 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8056
  { 9558 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, },
8057
  { 9568 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
8058
  { 9568 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, },
8059
  { 9578 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
8060
  { 9578 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, },
8061
  { 9578 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
8062
  { 9578 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, },
8063
  { 9578 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_NotFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, },
8064
  { 9578 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, AMFBS_IsFP64bit_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, },
8065
  { 9588 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8066
  { 9588 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8067
  { 9588 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, AMFBS_InMicroMips_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, },
8068
  { 9588 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_None, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, },
8069
  { 9598 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8070
  { 9602 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8071
  { 9607 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8072
  { 9611 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8073
  { 9615 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, AMFBS_None, { MCK_GPR32AsmReg, MCK_Mem }, },
8074
  { 9619 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8075
  { 9619 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8076
  { 9626 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8077
  { 9626 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8078
  { 9631 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8079
  { 9631 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, AMFBS_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, },
8080
  { 9637 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8081
  { 9644 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8082
  { 9651 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8083
  { 9658 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8084
  { 9665 /* wait */, Mips::WAIT, Convert_NoOperands, AMFBS_HasStdEnc_HasMips3_32_NotInMicroMips, {  }, },
8085
  { 9665 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, AMFBS_InMicroMips, {  }, },
8086
  { 9665 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips_HasMips32r6, { MCK_ConstantUImm10_0 }, },
8087
  { 9665 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, AMFBS_InMicroMips, { MCK_ConstantUImm10_0 }, },
8088
  { 9670 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg }, },
8089
  { 9670 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, AMFBS_HasDSP_InMicroMips, { MCK_GPR32AsmReg }, },
8090
  { 9670 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, AMFBS_InMicroMips_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, },
8091
  { 9670 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, AMFBS_HasDSP_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, },
8092
  { 9676 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8093
  { 9683 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8094
  { 9683 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8095
  { 9683 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8096
  { 9688 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, AMFBS_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, },
8097
  { 9688 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8098
  { 9688 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8099
  { 9688 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8100
  { 9688 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8101
  { 9688 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8102
  { 9688 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8103
  { 9688 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, },
8104
  { 9688 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8105
  { 9688 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8106
  { 9688 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8107
  { 9688 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8108
  { 9688 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8109
  { 9688 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, AMFBS_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, },
8110
  { 9688 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, },
8111
  { 9692 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, },
8112
  { 9698 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8113
  { 9698 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, },
8114
  { 9704 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8115
  { 9704 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8116
  { 9704 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, },
8117
  { 9704 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8118
  { 9704 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_HasStdEnc_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8119
  { 9704 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, AMFBS_InMicroMips_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, },
8120
  { 9709 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, AMFBS_HasStdEnc_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, },
8121
  { 9716 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, AMFBS_HasMT_NotInMicroMips, { MCK_GPR32AsmReg }, },
8122
  { 9716 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, AMFBS_HasStdEnc_HasMT_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, },
8123
};
8124
8125
#include "llvm/Support/Debug.h"
8126
#include "llvm/Support/Format.h"
8127
8128
unsigned MipsAsmParser::
8129
MatchInstructionImpl(const OperandVector &Operands,
8130
                     MCInst &Inst,
8131
                     uint64_t &ErrorInfo,
8132
                     FeatureBitset &MissingFeatures,
8133
0
                     bool matchingInlineAsm, unsigned VariantID) {
8134
  // Eliminate obvious mismatches.
8135
0
  if (Operands.size() > 9) {
8136
0
    ErrorInfo = 9;
8137
0
    return Match_InvalidOperand;
8138
0
  }
8139
8140
  // Get the current feature set.
8141
0
  const FeatureBitset &AvailableFeatures = getAvailableFeatures();
8142
8143
  // Get the instruction mnemonic, which is the first token.
8144
0
  StringRef Mnemonic = ((MipsOperand &)*Operands[0]).getToken();
8145
8146
  // Some state to try to produce better error messages.
8147
0
  bool HadMatchOtherThanFeatures = false;
8148
0
  bool HadMatchOtherThanPredicate = false;
8149
0
  unsigned RetCode = Match_InvalidOperand;
8150
0
  MissingFeatures.set();
8151
  // Set ErrorInfo to the operand that mismatches if it is
8152
  // wrong for all instances of the instruction.
8153
0
  ErrorInfo = ~0ULL;
8154
  // Find the appropriate table for this asm variant.
8155
0
  const MatchEntry *Start, *End;
8156
0
  switch (VariantID) {
8157
0
  default: llvm_unreachable("invalid variant!");
8158
0
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
8159
0
  }
8160
  // Search the table.
8161
0
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
8162
8163
0
  DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " <<
8164
0
  std::distance(MnemonicRange.first, MnemonicRange.second) <<
8165
0
  " encodings with mnemonic '" << Mnemonic << "'\n");
8166
8167
  // Return a more specific error code if no mnemonics match.
8168
0
  if (MnemonicRange.first == MnemonicRange.second)
8169
0
    return Match_MnemonicFail;
8170
8171
0
  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
8172
0
       it != ie; ++it) {
8173
0
    const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
8174
0
    bool HasRequiredFeatures =
8175
0
      (AvailableFeatures & RequiredFeatures) == RequiredFeatures;
8176
0
    DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode "
8177
0
                                          << MII.getName(it->Opcode) << "\n");
8178
    // equal_range guarantees that instruction mnemonic matches.
8179
0
    assert(Mnemonic == it->getMnemonic());
8180
0
    bool OperandsValid = true;
8181
0
    for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) {
8182
0
      auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]);
8183
0
      DEBUG_WITH_TYPE("asm-matcher",
8184
0
                      dbgs() << "  Matching formal operand class " << getMatchClassName(Formal)
8185
0
                             << " against actual operand at index " << ActualIdx);
8186
0
      if (ActualIdx < Operands.size())
8187
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << " (";
8188
0
                        Operands[ActualIdx]->print(dbgs()); dbgs() << "): ");
8189
0
      else
8190
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": ");
8191
0
      if (ActualIdx >= Operands.size()) {
8192
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n");
8193
0
        if (Formal == InvalidMatchClass) {
8194
0
          break;
8195
0
        }
8196
0
        if (isSubclass(Formal, OptionalMatchClass)) {
8197
0
          continue;
8198
0
        }
8199
0
        OperandsValid = false;
8200
0
        ErrorInfo = ActualIdx;
8201
0
        break;
8202
0
      }
8203
0
      MCParsedAsmOperand &Actual = *Operands[ActualIdx];
8204
0
      unsigned Diag = validateOperandClass(Actual, Formal);
8205
0
      if (Diag == Match_Success) {
8206
0
        DEBUG_WITH_TYPE("asm-matcher",
8207
0
                        dbgs() << "match success using generic matcher\n");
8208
0
        ++ActualIdx;
8209
0
        continue;
8210
0
      }
8211
      // If the generic handler indicates an invalid operand
8212
      // failure, check for a special case.
8213
0
      if (Diag != Match_Success) {
8214
0
        unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);
8215
0
        if (TargetDiag == Match_Success) {
8216
0
          DEBUG_WITH_TYPE("asm-matcher",
8217
0
                          dbgs() << "match success using target matcher\n");
8218
0
          ++ActualIdx;
8219
0
          continue;
8220
0
        }
8221
        // If the target matcher returned a specific error code use
8222
        // that, else use the one from the generic matcher.
8223
0
        if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures)
8224
0
          Diag = TargetDiag;
8225
0
      }
8226
      // If current formal operand wasn't matched and it is optional
8227
      // then try to match next formal operand
8228
0
      if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) {
8229
0
        DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n");
8230
0
        continue;
8231
0
      }
8232
      // If this operand is broken for all of the instances of this
8233
      // mnemonic, keep track of it so we can report loc info.
8234
      // If we already had a match that only failed due to a
8235
      // target predicate, that diagnostic is preferred.
8236
0
      if (!HadMatchOtherThanPredicate &&
8237
0
          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {
8238
0
        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand))
8239
0
          RetCode = Diag;
8240
0
        ErrorInfo = ActualIdx;
8241
0
      }
8242
      // Otherwise, just reject this instance of the mnemonic.
8243
0
      OperandsValid = false;
8244
0
      break;
8245
0
    }
8246
8247
0
    if (!OperandsValid) {
8248
0
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple "
8249
0
                                               "operand mismatches, ignoring "
8250
0
                                               "this opcode\n");
8251
0
      continue;
8252
0
    }
8253
0
    if (!HasRequiredFeatures) {
8254
0
      HadMatchOtherThanFeatures = true;
8255
0
      FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures;
8256
0
      DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:";
8257
0
                      for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)
8258
0
                        if (NewMissingFeatures[I])
8259
0
                          dbgs() << ' ' << I;
8260
0
                      dbgs() << "\n");
8261
0
      if (NewMissingFeatures.count() <=
8262
0
          MissingFeatures.count())
8263
0
        MissingFeatures = NewMissingFeatures;
8264
0
      continue;
8265
0
    }
8266
8267
0
    Inst.clear();
8268
8269
0
    Inst.setOpcode(it->Opcode);
8270
    // We have a potential match but have not rendered the operands.
8271
    // Check the target predicate to handle any context sensitive
8272
    // constraints.
8273
    // For example, Ties that are referenced multiple times must be
8274
    // checked here to ensure the input is the same for each match
8275
    // constraints. If we leave it any later the ties will have been
8276
    // canonicalized
8277
0
    unsigned MatchResult;
8278
0
    if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) {
8279
0
      Inst.clear();
8280
0
      DEBUG_WITH_TYPE(
8281
0
          "asm-matcher",
8282
0
          dbgs() << "Early target match predicate failed with diag code "
8283
0
                 << MatchResult << "\n");
8284
0
      RetCode = MatchResult;
8285
0
      HadMatchOtherThanPredicate = true;
8286
0
      continue;
8287
0
    }
8288
8289
0
    if (matchingInlineAsm) {
8290
0
      convertToMapAndConstraints(it->ConvertFn, Operands);
8291
0
      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
8292
0
        return Match_InvalidTiedOperand;
8293
8294
0
      return Match_Success;
8295
0
    }
8296
8297
    // We have selected a definite instruction, convert the parsed
8298
    // operands into the appropriate MCInst.
8299
0
    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
8300
8301
    // We have a potential match. Check the target predicate to
8302
    // handle any context sensitive constraints.
8303
0
    if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
8304
0
      DEBUG_WITH_TYPE("asm-matcher",
8305
0
                      dbgs() << "Target match predicate failed with diag code "
8306
0
                             << MatchResult << "\n");
8307
0
      Inst.clear();
8308
0
      RetCode = MatchResult;
8309
0
      HadMatchOtherThanPredicate = true;
8310
0
      continue;
8311
0
    }
8312
8313
0
    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo))
8314
0
      return Match_InvalidTiedOperand;
8315
8316
0
    DEBUG_WITH_TYPE(
8317
0
        "asm-matcher",
8318
0
        dbgs() << "Opcode result: complete match, selecting this opcode\n");
8319
0
    return Match_Success;
8320
0
  }
8321
8322
  // Okay, we had no match.  Try to return a useful error code.
8323
0
  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
8324
0
    return RetCode;
8325
8326
0
  ErrorInfo = 0;
8327
0
  return Match_MissingFeature;
8328
0
}
8329
8330
namespace {
8331
  struct OperandMatchEntry {
8332
    uint16_t Mnemonic;
8333
    uint8_t OperandMask;
8334
    uint8_t Class;
8335
    uint8_t RequiredFeaturesIdx;
8336
8337
0
    StringRef getMnemonic() const {
8338
0
      return StringRef(MnemonicTable + Mnemonic + 1,
8339
0
                       MnemonicTable[Mnemonic]);
8340
0
    }
8341
  };
8342
8343
  // Predicate for searching for an opcode.
8344
  struct LessOpcodeOperand {
8345
0
    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
8346
0
      return LHS.getMnemonic()  < RHS;
8347
0
    }
8348
0
    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
8349
0
      return LHS < RHS.getMnemonic();
8350
0
    }
8351
0
    bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
8352
0
      return LHS.getMnemonic() < RHS.getMnemonic();
8353
0
    }
8354
  };
8355
} // end anonymous namespace
8356
8357
static const OperandMatchEntry OperandMatchTable[3313] = {
8358
  /* Operand List Mnemonic, Mask, Operand Class, Features */
8359
  { 0 /* abs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8360
  { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
8361
  { 4 /* abs.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
8362
  { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
8363
  { 4 /* abs.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
8364
  { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
8365
  { 10 /* abs.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
8366
  { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8367
  { 16 /* absq_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8368
  { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8369
  { 26 /* absq_s.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8370
  { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8371
  { 36 /* absq_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8372
  { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8373
  { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8374
  { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8375
  { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8376
  { 45 /* add */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8377
  { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8378
  { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8379
  { 45 /* add */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8380
  { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8381
  { 45 /* add */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8382
  { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
8383
  { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
8384
  { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
8385
  { 49 /* add.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
8386
  { 55 /* add.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8387
  { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
8388
  { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8389
  { 62 /* add.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
8390
  { 68 /* add_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8391
  { 76 /* add_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8392
  { 84 /* add_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8393
  { 92 /* add_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8394
  { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8395
  { 100 /* addi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8396
  { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8397
  { 100 /* addi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8398
  { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8399
  { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8400
  { 105 /* addiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8401
  { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8402
  { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8403
  { 105 /* addiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8404
  { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8405
  { 111 /* addiupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8406
  { 111 /* addiupc */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8407
  { 119 /* addiur1sp */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8408
  { 129 /* addiur2 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
8409
  { 137 /* addius5 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8410
  { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8411
  { 153 /* addq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8412
  { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8413
  { 161 /* addq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8414
  { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8415
  { 171 /* addq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8416
  { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8417
  { 180 /* addqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8418
  { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8419
  { 189 /* addqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8420
  { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8421
  { 197 /* addqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8422
  { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8423
  { 208 /* addqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8424
  { 218 /* addr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
8425
  { 226 /* adds_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8426
  { 235 /* adds_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8427
  { 244 /* adds_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8428
  { 253 /* adds_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8429
  { 262 /* adds_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8430
  { 271 /* adds_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8431
  { 280 /* adds_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8432
  { 289 /* adds_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8433
  { 298 /* adds_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8434
  { 307 /* adds_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8435
  { 316 /* adds_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8436
  { 325 /* adds_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8437
  { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8438
  { 334 /* addsc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8439
  { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8440
  { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8441
  { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8442
  { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8443
  { 340 /* addu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8444
  { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8445
  { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8446
  { 340 /* addu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8447
  { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8448
  { 340 /* addu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8449
  { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8450
  { 345 /* addu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8451
  { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8452
  { 353 /* addu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8453
  { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8454
  { 361 /* addu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8455
  { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8456
  { 368 /* addu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8457
  { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8458
  { 378 /* addu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8459
  { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8460
  { 388 /* adduh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8461
  { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8462
  { 397 /* adduh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8463
  { 408 /* addv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8464
  { 415 /* addv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8465
  { 422 /* addv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8466
  { 429 /* addv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8467
  { 436 /* addvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8468
  { 444 /* addvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8469
  { 452 /* addvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8470
  { 460 /* addvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8471
  { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8472
  { 468 /* addwc */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8473
  { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8474
  { 474 /* align */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8475
  { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8476
  { 480 /* aluipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8477
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8478
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8479
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8480
  { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8481
  { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
8482
  { 487 /* and */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8483
  { 487 /* and */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
8484
  { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8485
  { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8486
  { 487 /* and */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8487
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8488
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
8489
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8490
  { 487 /* and */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
8491
  { 491 /* and.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8492
  { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8493
  { 497 /* and16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8494
  { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8495
  { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8496
  { 503 /* andi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8497
  { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8498
  { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8499
  { 503 /* andi */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8500
  { 508 /* andi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8501
  { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8502
  { 515 /* andi16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8503
  { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8504
  { 522 /* append */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8505
  { 529 /* asub_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8506
  { 538 /* asub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8507
  { 547 /* asub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8508
  { 556 /* asub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8509
  { 565 /* asub_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8510
  { 574 /* asub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8511
  { 583 /* asub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8512
  { 592 /* asub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8513
  { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8514
  { 601 /* aui */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8515
  { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8516
  { 605 /* auipc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8517
  { 611 /* ave_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8518
  { 619 /* ave_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8519
  { 627 /* ave_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8520
  { 635 /* ave_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8521
  { 643 /* ave_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8522
  { 651 /* ave_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8523
  { 659 /* ave_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8524
  { 667 /* ave_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8525
  { 675 /* aver_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8526
  { 684 /* aver_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8527
  { 693 /* aver_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8528
  { 702 /* aver_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8529
  { 711 /* aver_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8530
  { 720 /* aver_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8531
  { 729 /* aver_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8532
  { 738 /* aver_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8533
  { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8534
  { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8535
  { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8536
  { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_None },
8537
  { 747 /* b */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8538
  { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8539
  { 749 /* b16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips },
8540
  { 753 /* baddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8541
  { 753 /* baddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8542
  { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8543
  { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8544
  { 759 /* bal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8545
  { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
8546
  { 763 /* balc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8547
  { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
8548
  { 768 /* balign */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
8549
  { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8550
  { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8551
  { 775 /* bbit0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8552
  { 775 /* bbit0 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8553
  { 781 /* bbit032 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8554
  { 781 /* bbit032 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8555
  { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8556
  { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8557
  { 789 /* bbit1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8558
  { 789 /* bbit1 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8559
  { 795 /* bbit132 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
8560
  { 795 /* bbit132 */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasCnMips },
8561
  { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8562
  { 803 /* bc */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8563
  { 806 /* bc16 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8564
  { 811 /* bc1eqz */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8565
  { 811 /* bc1eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8566
  { 818 /* bc1eqzc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8567
  { 818 /* bc1eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8568
  { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8569
  { 826 /* bc1f */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8570
  { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8571
  { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8572
  { 826 /* bc1f */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8573
  { 826 /* bc1f */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8574
  { 831 /* bc1fl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8575
  { 831 /* bc1fl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8576
  { 831 /* bc1fl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8577
  { 837 /* bc1nez */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8578
  { 837 /* bc1nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
8579
  { 844 /* bc1nezc */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8580
  { 844 /* bc1nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
8581
  { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8582
  { 852 /* bc1t */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8583
  { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8584
  { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8585
  { 852 /* bc1t */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8586
  { 852 /* bc1t */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8587
  { 857 /* bc1tl */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8588
  { 857 /* bc1tl */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8589
  { 857 /* bc1tl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8590
  { 863 /* bc2eqz */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8591
  { 863 /* bc2eqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8592
  { 870 /* bc2eqzc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8593
  { 870 /* bc2eqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8594
  { 878 /* bc2nez */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8595
  { 878 /* bc2nez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8596
  { 885 /* bc2nezc */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8597
  { 885 /* bc2nezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8598
  { 893 /* bclr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8599
  { 900 /* bclr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8600
  { 907 /* bclr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8601
  { 914 /* bclr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8602
  { 921 /* bclri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8603
  { 929 /* bclri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8604
  { 937 /* bclri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8605
  { 945 /* bclri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8606
  { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8607
  { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8608
  { 953 /* beq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8609
  { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8610
  { 953 /* beq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8611
  { 953 /* beq */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8612
  { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8613
  { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8614
  { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8615
  { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8616
  { 957 /* beqc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8617
  { 957 /* beqc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8618
  { 962 /* beql */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8619
  { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8620
  { 962 /* beql */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8621
  { 962 /* beql */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8622
  { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8623
  { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8624
  { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8625
  { 967 /* beqz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8626
  { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
8627
  { 967 /* beqz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8628
  { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8629
  { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8630
  { 972 /* beqz16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8631
  { 972 /* beqz16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8632
  { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8633
  { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8634
  { 979 /* beqzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8635
  { 979 /* beqzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8636
  { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8637
  { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8638
  { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8639
  { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8640
  { 987 /* beqzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8641
  { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8642
  { 987 /* beqzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8643
  { 987 /* beqzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8644
  { 993 /* beqzc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8645
  { 993 /* beqzc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8646
  { 1001 /* beqzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8647
  { 1001 /* beqzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8648
  { 1007 /* bge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8649
  { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8650
  { 1007 /* bge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8651
  { 1007 /* bge */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8652
  { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8653
  { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8654
  { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8655
  { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8656
  { 1011 /* bgec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8657
  { 1011 /* bgec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8658
  { 1016 /* bgel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8659
  { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8660
  { 1016 /* bgel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8661
  { 1016 /* bgel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8662
  { 1021 /* bgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8663
  { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8664
  { 1021 /* bgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8665
  { 1021 /* bgeu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8666
  { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8667
  { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8668
  { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8669
  { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8670
  { 1026 /* bgeuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8671
  { 1026 /* bgeuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8672
  { 1032 /* bgeul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8673
  { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8674
  { 1032 /* bgeul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8675
  { 1032 /* bgeul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8676
  { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8677
  { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8678
  { 1038 /* bgez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8679
  { 1038 /* bgez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8680
  { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8681
  { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8682
  { 1043 /* bgezal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8683
  { 1043 /* bgezal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8684
  { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8685
  { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8686
  { 1050 /* bgezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8687
  { 1050 /* bgezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8688
  { 1058 /* bgezall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8689
  { 1058 /* bgezall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8690
  { 1066 /* bgezals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8691
  { 1066 /* bgezals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8692
  { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8693
  { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8694
  { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8695
  { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8696
  { 1074 /* bgezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8697
  { 1074 /* bgezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8698
  { 1080 /* bgezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8699
  { 1080 /* bgezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8700
  { 1086 /* bgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8701
  { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8702
  { 1086 /* bgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8703
  { 1086 /* bgt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8704
  { 1090 /* bgtl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8705
  { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8706
  { 1090 /* bgtl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8707
  { 1090 /* bgtl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8708
  { 1095 /* bgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8709
  { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8710
  { 1095 /* bgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8711
  { 1095 /* bgtu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8712
  { 1100 /* bgtul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8713
  { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8714
  { 1100 /* bgtul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8715
  { 1100 /* bgtul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8716
  { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8717
  { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8718
  { 1106 /* bgtz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8719
  { 1106 /* bgtz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8720
  { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8721
  { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8722
  { 1111 /* bgtzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8723
  { 1111 /* bgtzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8724
  { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8725
  { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8726
  { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8727
  { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8728
  { 1119 /* bgtzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8729
  { 1119 /* bgtzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8730
  { 1125 /* bgtzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8731
  { 1125 /* bgtzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8732
  { 1131 /* binsl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8733
  { 1139 /* binsl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8734
  { 1147 /* binsl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8735
  { 1155 /* binsl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8736
  { 1163 /* binsli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8737
  { 1172 /* binsli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8738
  { 1181 /* binsli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8739
  { 1190 /* binsli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8740
  { 1199 /* binsr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8741
  { 1207 /* binsr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8742
  { 1215 /* binsr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8743
  { 1223 /* binsr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8744
  { 1231 /* binsri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8745
  { 1240 /* binsri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8746
  { 1249 /* binsri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8747
  { 1258 /* binsri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8748
  { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
8749
  { 1267 /* bitrev */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
8750
  { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
8751
  { 1274 /* bitswap */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8752
  { 1282 /* ble */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8753
  { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8754
  { 1282 /* ble */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8755
  { 1282 /* ble */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8756
  { 1286 /* blel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8757
  { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8758
  { 1286 /* blel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8759
  { 1286 /* blel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8760
  { 1291 /* bleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8761
  { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8762
  { 1291 /* bleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8763
  { 1291 /* bleu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8764
  { 1296 /* bleul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8765
  { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8766
  { 1296 /* bleul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8767
  { 1296 /* bleul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8768
  { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8769
  { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8770
  { 1302 /* blez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8771
  { 1302 /* blez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8772
  { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8773
  { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8774
  { 1307 /* blezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8775
  { 1307 /* blezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8776
  { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8777
  { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8778
  { 1315 /* blezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8779
  { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8780
  { 1315 /* blezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8781
  { 1315 /* blezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8782
  { 1321 /* blezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8783
  { 1321 /* blezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8784
  { 1327 /* blt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8785
  { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8786
  { 1327 /* blt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8787
  { 1327 /* blt */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8788
  { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8789
  { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8790
  { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8791
  { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8792
  { 1331 /* bltc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8793
  { 1331 /* bltc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8794
  { 1336 /* bltl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8795
  { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8796
  { 1336 /* bltl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8797
  { 1336 /* bltl */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8798
  { 1341 /* bltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
8799
  { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8800
  { 1341 /* bltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8801
  { 1341 /* bltu */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8802
  { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8803
  { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8804
  { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8805
  { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8806
  { 1346 /* bltuc */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8807
  { 1346 /* bltuc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8808
  { 1352 /* bltul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8809
  { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8810
  { 1352 /* bltul */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8811
  { 1352 /* bltul */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8812
  { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8813
  { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8814
  { 1358 /* bltz */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8815
  { 1358 /* bltz */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8816
  { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8817
  { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
8818
  { 1363 /* bltzal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8819
  { 1363 /* bltzal */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8820
  { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8821
  { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8822
  { 1370 /* bltzalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8823
  { 1370 /* bltzalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8824
  { 1378 /* bltzall */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8825
  { 1378 /* bltzall */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8826
  { 1386 /* bltzals */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8827
  { 1386 /* bltzals */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8828
  { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8829
  { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8830
  { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8831
  { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8832
  { 1394 /* bltzc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8833
  { 1394 /* bltzc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8834
  { 1400 /* bltzl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8835
  { 1400 /* bltzl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8836
  { 1406 /* bmnz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8837
  { 1413 /* bmnzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8838
  { 1421 /* bmz.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8839
  { 1427 /* bmzi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8840
  { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8841
  { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8842
  { 1434 /* bne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8843
  { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8844
  { 1434 /* bne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
8845
  { 1434 /* bne */, 4 /* 2 */, MCK_JumpTarget, AMFBS_None },
8846
  { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8847
  { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8848
  { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8849
  { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8850
  { 1438 /* bnec */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8851
  { 1438 /* bnec */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8852
  { 1443 /* bneg.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8853
  { 1450 /* bneg.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8854
  { 1457 /* bneg.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8855
  { 1464 /* bneg.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8856
  { 1471 /* bnegi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8857
  { 1479 /* bnegi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8858
  { 1487 /* bnegi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8859
  { 1495 /* bnegi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8860
  { 1503 /* bnel */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8861
  { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
8862
  { 1503 /* bnel */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8863
  { 1503 /* bnel */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6 },
8864
  { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8865
  { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
8866
  { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
8867
  { 1508 /* bnez */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
8868
  { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips },
8869
  { 1508 /* bnez */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMips16Mode },
8870
  { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8871
  { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8872
  { 1513 /* bnez16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8873
  { 1513 /* bnez16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8874
  { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8875
  { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8876
  { 1520 /* bnezalc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8877
  { 1520 /* bnezalc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8878
  { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8879
  { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8880
  { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
8881
  { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
8882
  { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8883
  { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8884
  { 1528 /* bnezc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8885
  { 1528 /* bnezc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
8886
  { 1534 /* bnezc16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8887
  { 1534 /* bnezc16 */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8888
  { 1542 /* bnezl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8889
  { 1542 /* bnezl */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
8890
  { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8891
  { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8892
  { 1548 /* bnvc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8893
  { 1548 /* bnvc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8894
  { 1553 /* bnz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8895
  { 1553 /* bnz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8896
  { 1559 /* bnz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8897
  { 1559 /* bnz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8898
  { 1565 /* bnz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8899
  { 1565 /* bnz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8900
  { 1571 /* bnz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8901
  { 1571 /* bnz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8902
  { 1577 /* bnz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8903
  { 1577 /* bnz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8904
  { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8905
  { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
8906
  { 1583 /* bovc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
8907
  { 1583 /* bovc */, 4 /* 2 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
8908
  { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6_HasDSP },
8909
  { 1588 /* bposge32 */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasDSP_NotInMicroMips },
8910
  { 1597 /* bposge32c */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasDSPR3 },
8911
  { 1621 /* bsel.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8912
  { 1628 /* bseli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8913
  { 1636 /* bset.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8914
  { 1643 /* bset.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8915
  { 1650 /* bset.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8916
  { 1657 /* bset.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8917
  { 1664 /* bseti.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8918
  { 1672 /* bseti.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8919
  { 1680 /* bseti.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8920
  { 1688 /* bseti.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8921
  { 1708 /* bz.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8922
  { 1708 /* bz.b */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8923
  { 1713 /* bz.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8924
  { 1713 /* bz.d */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8925
  { 1718 /* bz.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8926
  { 1718 /* bz.h */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8927
  { 1723 /* bz.v */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8928
  { 1723 /* bz.v */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8929
  { 1728 /* bz.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
8930
  { 1728 /* bz.w */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMSA },
8931
  { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8932
  { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8933
  { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8934
  { 1733 /* c.eq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8935
  { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8936
  { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8937
  { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8938
  { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8939
  { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8940
  { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8941
  { 1733 /* c.eq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8942
  { 1733 /* c.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8943
  { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8944
  { 1740 /* c.eq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8945
  { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8946
  { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8947
  { 1740 /* c.eq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8948
  { 1740 /* c.eq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8949
  { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8950
  { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8951
  { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8952
  { 1747 /* c.f.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8953
  { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8954
  { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8955
  { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8956
  { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8957
  { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8958
  { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8959
  { 1747 /* c.f.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8960
  { 1747 /* c.f.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8961
  { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8962
  { 1753 /* c.f.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8963
  { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8964
  { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8965
  { 1753 /* c.f.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8966
  { 1753 /* c.f.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8967
  { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8968
  { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8969
  { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8970
  { 1759 /* c.le.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8971
  { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8972
  { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8973
  { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8974
  { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8975
  { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8976
  { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8977
  { 1759 /* c.le.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8978
  { 1759 /* c.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8979
  { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8980
  { 1766 /* c.le.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8981
  { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8982
  { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8983
  { 1766 /* c.le.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8984
  { 1766 /* c.le.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8985
  { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8986
  { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8987
  { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8988
  { 1773 /* c.lt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8989
  { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8990
  { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8991
  { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8992
  { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
8993
  { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8994
  { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8995
  { 1773 /* c.lt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8996
  { 1773 /* c.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
8997
  { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
8998
  { 1780 /* c.lt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
8999
  { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9000
  { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9001
  { 1780 /* c.lt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9002
  { 1780 /* c.lt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9003
  { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9004
  { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9005
  { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9006
  { 1787 /* c.nge.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9007
  { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9008
  { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9009
  { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9010
  { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9011
  { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9012
  { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9013
  { 1787 /* c.nge.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9014
  { 1787 /* c.nge.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9015
  { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9016
  { 1795 /* c.nge.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9017
  { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9018
  { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9019
  { 1795 /* c.nge.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9020
  { 1795 /* c.nge.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9021
  { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9022
  { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9023
  { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9024
  { 1803 /* c.ngl.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9025
  { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9026
  { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9027
  { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9028
  { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9029
  { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9030
  { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9031
  { 1803 /* c.ngl.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9032
  { 1803 /* c.ngl.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9033
  { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9034
  { 1811 /* c.ngl.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9035
  { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9036
  { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9037
  { 1811 /* c.ngl.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9038
  { 1811 /* c.ngl.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9039
  { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9040
  { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9041
  { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9042
  { 1819 /* c.ngle.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9043
  { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9044
  { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9045
  { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9046
  { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9047
  { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9048
  { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9049
  { 1819 /* c.ngle.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9050
  { 1819 /* c.ngle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9051
  { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9052
  { 1828 /* c.ngle.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9053
  { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9054
  { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9055
  { 1828 /* c.ngle.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9056
  { 1828 /* c.ngle.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9057
  { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9058
  { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9059
  { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9060
  { 1837 /* c.ngt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9061
  { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9062
  { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9063
  { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9064
  { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9065
  { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9066
  { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9067
  { 1837 /* c.ngt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9068
  { 1837 /* c.ngt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9069
  { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9070
  { 1845 /* c.ngt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9071
  { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9072
  { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9073
  { 1845 /* c.ngt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9074
  { 1845 /* c.ngt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9075
  { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9076
  { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9077
  { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9078
  { 1853 /* c.ole.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9079
  { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9080
  { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9081
  { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9082
  { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9083
  { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9084
  { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9085
  { 1853 /* c.ole.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9086
  { 1853 /* c.ole.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9087
  { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9088
  { 1861 /* c.ole.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9089
  { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9090
  { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9091
  { 1861 /* c.ole.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9092
  { 1861 /* c.ole.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9093
  { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9094
  { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9095
  { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9096
  { 1869 /* c.olt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9097
  { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9098
  { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9099
  { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9100
  { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9101
  { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9102
  { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9103
  { 1869 /* c.olt.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9104
  { 1869 /* c.olt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9105
  { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9106
  { 1877 /* c.olt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9107
  { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9108
  { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9109
  { 1877 /* c.olt.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9110
  { 1877 /* c.olt.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9111
  { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9112
  { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9113
  { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9114
  { 1885 /* c.seq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9115
  { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9116
  { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9117
  { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9118
  { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9119
  { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9120
  { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9121
  { 1885 /* c.seq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9122
  { 1885 /* c.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9123
  { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9124
  { 1893 /* c.seq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9125
  { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9126
  { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9127
  { 1893 /* c.seq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9128
  { 1893 /* c.seq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9129
  { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9130
  { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9131
  { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9132
  { 1901 /* c.sf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9133
  { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9134
  { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9135
  { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9136
  { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9137
  { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9138
  { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9139
  { 1901 /* c.sf.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9140
  { 1901 /* c.sf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9141
  { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9142
  { 1908 /* c.sf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9143
  { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9144
  { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9145
  { 1908 /* c.sf.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9146
  { 1908 /* c.sf.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9147
  { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9148
  { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9149
  { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9150
  { 1915 /* c.ueq.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9151
  { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9152
  { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9153
  { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9154
  { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9155
  { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9156
  { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9157
  { 1915 /* c.ueq.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9158
  { 1915 /* c.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9159
  { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9160
  { 1923 /* c.ueq.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9161
  { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9162
  { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9163
  { 1923 /* c.ueq.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9164
  { 1923 /* c.ueq.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9165
  { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9166
  { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9167
  { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9168
  { 1931 /* c.ule.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9169
  { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9170
  { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9171
  { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9172
  { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9173
  { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9174
  { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9175
  { 1931 /* c.ule.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9176
  { 1931 /* c.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9177
  { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9178
  { 1939 /* c.ule.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9179
  { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9180
  { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9181
  { 1939 /* c.ule.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9182
  { 1939 /* c.ule.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9183
  { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9184
  { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9185
  { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9186
  { 1947 /* c.ult.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9187
  { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9188
  { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9189
  { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9190
  { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9191
  { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9192
  { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9193
  { 1947 /* c.ult.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9194
  { 1947 /* c.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9195
  { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9196
  { 1955 /* c.ult.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9197
  { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9198
  { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9199
  { 1955 /* c.ult.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9200
  { 1955 /* c.ult.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9201
  { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9202
  { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9203
  { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9204
  { 1963 /* c.un.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9205
  { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9206
  { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9207
  { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9208
  { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
9209
  { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9210
  { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9211
  { 1963 /* c.un.d */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9212
  { 1963 /* c.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
9213
  { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9214
  { 1970 /* c.un.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9215
  { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9216
  { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9217
  { 1970 /* c.un.s */, 1 /* 0 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9218
  { 1970 /* c.un.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
9219
  { 1977 /* cache */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9220
  { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
9221
  { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
9222
  { 1977 /* cache */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
9223
  { 1983 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
9224
  { 1983 /* cachee */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
9225
  { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
9226
  { 1990 /* ceil.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9227
  { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9228
  { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9229
  { 1999 /* ceil.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9230
  { 1999 /* ceil.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9231
  { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9232
  { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9233
  { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9234
  { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9235
  { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9236
  { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9237
  { 2008 /* ceil.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9238
  { 2008 /* ceil.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9239
  { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
9240
  { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9241
  { 2017 /* ceil.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9242
  { 2026 /* ceq.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9243
  { 2032 /* ceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9244
  { 2038 /* ceq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9245
  { 2044 /* ceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9246
  { 2050 /* ceqi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9247
  { 2057 /* ceqi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9248
  { 2064 /* ceqi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9249
  { 2071 /* ceqi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9250
  { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9251
  { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9252
  { 2078 /* cfc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9253
  { 2078 /* cfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9254
  { 2083 /* cfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9255
  { 2083 /* cfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9256
  { 2088 /* cfcmsa */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9257
  { 2088 /* cfcmsa */, 2 /* 1 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA },
9258
  { 2095 /* cftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9259
  { 2095 /* cftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9260
  { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9261
  { 2101 /* cins */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9262
  { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9263
  { 2101 /* cins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9264
  { 2106 /* cins32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9265
  { 2106 /* cins32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9266
  { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9267
  { 2113 /* class.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9268
  { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9269
  { 2121 /* class.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9270
  { 2129 /* cle_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9271
  { 2137 /* cle_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9272
  { 2145 /* cle_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9273
  { 2153 /* cle_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9274
  { 2161 /* cle_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9275
  { 2169 /* cle_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9276
  { 2177 /* cle_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9277
  { 2185 /* cle_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9278
  { 2193 /* clei_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9279
  { 2202 /* clei_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9280
  { 2211 /* clei_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9281
  { 2220 /* clei_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9282
  { 2229 /* clei_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9283
  { 2238 /* clei_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9284
  { 2247 /* clei_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9285
  { 2256 /* clei_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9286
  { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
9287
  { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9288
  { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9289
  { 2265 /* clo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9290
  { 2269 /* clt_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9291
  { 2277 /* clt_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9292
  { 2285 /* clt_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9293
  { 2293 /* clt_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9294
  { 2301 /* clt_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9295
  { 2309 /* clt_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9296
  { 2317 /* clt_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9297
  { 2325 /* clt_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9298
  { 2333 /* clti_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9299
  { 2342 /* clti_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9300
  { 2351 /* clti_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9301
  { 2360 /* clti_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9302
  { 2369 /* clti_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9303
  { 2378 /* clti_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9304
  { 2387 /* clti_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9305
  { 2396 /* clti_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9306
  { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
9307
  { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9308
  { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9309
  { 2405 /* clz */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9310
  { 2413 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9311
  { 2413 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9312
  { 2413 /* cmp.af.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9313
  { 2413 /* cmp.af.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9314
  { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9315
  { 2422 /* cmp.af.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9316
  { 2431 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9317
  { 2431 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9318
  { 2431 /* cmp.eq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9319
  { 2431 /* cmp.eq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9320
  { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9321
  { 2440 /* cmp.eq.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9322
  { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9323
  { 2450 /* cmp.eq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9324
  { 2459 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9325
  { 2459 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9326
  { 2459 /* cmp.le.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9327
  { 2459 /* cmp.le.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9328
  { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9329
  { 2468 /* cmp.le.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9330
  { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9331
  { 2478 /* cmp.le.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9332
  { 2487 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9333
  { 2487 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9334
  { 2487 /* cmp.lt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9335
  { 2487 /* cmp.lt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9336
  { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9337
  { 2496 /* cmp.lt.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9338
  { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9339
  { 2506 /* cmp.lt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9340
  { 2515 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9341
  { 2515 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9342
  { 2515 /* cmp.saf.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9343
  { 2515 /* cmp.saf.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9344
  { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9345
  { 2525 /* cmp.saf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9346
  { 2535 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9347
  { 2535 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9348
  { 2535 /* cmp.seq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9349
  { 2535 /* cmp.seq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9350
  { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9351
  { 2545 /* cmp.seq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9352
  { 2555 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9353
  { 2555 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9354
  { 2555 /* cmp.sle.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9355
  { 2555 /* cmp.sle.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9356
  { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9357
  { 2565 /* cmp.sle.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9358
  { 2575 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9359
  { 2575 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9360
  { 2575 /* cmp.slt.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9361
  { 2575 /* cmp.slt.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9362
  { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9363
  { 2585 /* cmp.slt.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9364
  { 2595 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9365
  { 2595 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9366
  { 2595 /* cmp.sueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9367
  { 2595 /* cmp.sueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9368
  { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9369
  { 2606 /* cmp.sueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9370
  { 2617 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9371
  { 2617 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9372
  { 2617 /* cmp.sule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9373
  { 2617 /* cmp.sule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9374
  { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9375
  { 2628 /* cmp.sule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9376
  { 2639 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9377
  { 2639 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9378
  { 2639 /* cmp.sult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9379
  { 2639 /* cmp.sult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9380
  { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9381
  { 2650 /* cmp.sult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9382
  { 2661 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9383
  { 2661 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9384
  { 2661 /* cmp.sun.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9385
  { 2661 /* cmp.sun.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9386
  { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9387
  { 2671 /* cmp.sun.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9388
  { 2681 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9389
  { 2681 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9390
  { 2681 /* cmp.ueq.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9391
  { 2681 /* cmp.ueq.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9392
  { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9393
  { 2691 /* cmp.ueq.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9394
  { 2701 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9395
  { 2701 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9396
  { 2701 /* cmp.ule.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9397
  { 2701 /* cmp.ule.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9398
  { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9399
  { 2711 /* cmp.ule.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9400
  { 2721 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9401
  { 2721 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9402
  { 2721 /* cmp.ult.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9403
  { 2721 /* cmp.ult.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9404
  { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9405
  { 2731 /* cmp.ult.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9406
  { 2741 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9407
  { 2741 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9408
  { 2741 /* cmp.un.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9409
  { 2741 /* cmp.un.d */, 6 /* 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9410
  { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
9411
  { 2750 /* cmp.un.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9412
  { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9413
  { 2759 /* cmpgdu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9414
  { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9415
  { 2772 /* cmpgdu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9416
  { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9417
  { 2785 /* cmpgdu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9418
  { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9419
  { 2798 /* cmpgu.eq.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9420
  { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9421
  { 2810 /* cmpgu.le.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9422
  { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9423
  { 2822 /* cmpgu.lt.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9424
  { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9425
  { 2839 /* cmpu.eq.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9426
  { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9427
  { 2850 /* cmpu.le.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9428
  { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9429
  { 2861 /* cmpu.lt.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9430
  { 2872 /* copy_s.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9431
  { 2872 /* copy_s.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9432
  { 2881 /* copy_s.d */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9433
  { 2881 /* copy_s.d */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9434
  { 2890 /* copy_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9435
  { 2890 /* copy_s.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9436
  { 2899 /* copy_s.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9437
  { 2899 /* copy_s.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9438
  { 2908 /* copy_u.b */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9439
  { 2908 /* copy_u.b */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9440
  { 2917 /* copy_u.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9441
  { 2917 /* copy_u.h */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9442
  { 2926 /* copy_u.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9443
  { 2926 /* copy_u.w */, 2 /* 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9444
  { 2935 /* crc32b */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9445
  { 2942 /* crc32cb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9446
  { 2950 /* crc32cd */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips },
9447
  { 2958 /* crc32ch */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9448
  { 2966 /* crc32cw */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9449
  { 2974 /* crc32d */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips },
9450
  { 2981 /* crc32h */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9451
  { 2988 /* crc32w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips },
9452
  { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9453
  { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9454
  { 2995 /* ctc1 */, 2 /* 1 */, MCK_CCRAsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9455
  { 2995 /* ctc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9456
  { 3000 /* ctc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips },
9457
  { 3000 /* ctc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9458
  { 3005 /* ctcmsa */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9459
  { 3005 /* ctcmsa */, 1 /* 0 */, MCK_MSACtrlAsmReg, AMFBS_HasStdEnc_HasMSA },
9460
  { 3012 /* cttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
9461
  { 3012 /* cttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
9462
  { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9463
  { 3018 /* cvt.d.l */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
9464
  { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9465
  { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9466
  { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9467
  { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9468
  { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9469
  { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9470
  { 3026 /* cvt.d.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9471
  { 3026 /* cvt.d.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9472
  { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9473
  { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9474
  { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9475
  { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9476
  { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9477
  { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9478
  { 3034 /* cvt.d.w */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9479
  { 3034 /* cvt.d.w */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9480
  { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9481
  { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9482
  { 3042 /* cvt.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9483
  { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9484
  { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9485
  { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9486
  { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9487
  { 3050 /* cvt.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9488
  { 3050 /* cvt.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9489
  { 3058 /* cvt.ps.pw */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
9490
  { 3068 /* cvt.ps.s */, 6 /* 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9491
  { 3068 /* cvt.ps.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9492
  { 3077 /* cvt.pw.ps */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
9493
  { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9494
  { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9495
  { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9496
  { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9497
  { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9498
  { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9499
  { 3087 /* cvt.s.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9500
  { 3087 /* cvt.s.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9501
  { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9502
  { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips },
9503
  { 3095 /* cvt.s.l */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
9504
  { 3095 /* cvt.s.l */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
9505
  { 3103 /* cvt.s.pl */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9506
  { 3103 /* cvt.s.pl */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9507
  { 3112 /* cvt.s.pu */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9508
  { 3112 /* cvt.s.pu */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
9509
  { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9510
  { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9511
  { 3121 /* cvt.s.w */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9512
  { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9513
  { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9514
  { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9515
  { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9516
  { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9517
  { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9518
  { 3129 /* cvt.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9519
  { 3129 /* cvt.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9520
  { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9521
  { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9522
  { 3137 /* cvt.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9523
  { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9524
  { 3145 /* dadd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9525
  { 3145 /* dadd */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9526
  { 3145 /* dadd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9527
  { 3150 /* daddi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9528
  { 3150 /* daddi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9529
  { 3156 /* daddiu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9530
  { 3156 /* daddiu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9531
  { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9532
  { 3163 /* daddu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9533
  { 3163 /* daddu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9534
  { 3163 /* daddu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9535
  { 3169 /* dahi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9536
  { 3174 /* dalign */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9537
  { 3181 /* dati */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9538
  { 3186 /* daui */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9539
  { 3191 /* dbitswap */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9540
  { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips },
9541
  { 3200 /* dclo */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9542
  { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips },
9543
  { 3205 /* dclz */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9544
  { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9545
  { 3210 /* ddiv */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9546
  { 3210 /* ddiv */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9547
  { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9548
  { 3210 /* ddiv */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9549
  { 3210 /* ddiv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9550
  { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9551
  { 3215 /* ddivu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9552
  { 3215 /* ddivu */, 6 /* 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9553
  { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9554
  { 3215 /* ddivu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9555
  { 3215 /* ddivu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9556
  { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9557
  { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9558
  { 3227 /* dext */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9559
  { 3232 /* dextm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9560
  { 3238 /* dextu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9561
  { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9562
  { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9563
  { 3244 /* di */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9564
  { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9565
  { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9566
  { 3247 /* dins */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9567
  { 3252 /* dinsm */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9568
  { 3258 /* dinsu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9569
  { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9570
  { 3264 /* div */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9571
  { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9572
  { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9573
  { 3264 /* div */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9574
  { 3264 /* div */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9575
  { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9576
  { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9577
  { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9578
  { 3264 /* div */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9579
  { 3264 /* div */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9580
  { 3264 /* div */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9581
  { 3264 /* div */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9582
  { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
9583
  { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9584
  { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
9585
  { 3268 /* div.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
9586
  { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
9587
  { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9588
  { 3274 /* div.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9589
  { 3280 /* div_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9590
  { 3288 /* div_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9591
  { 3296 /* div_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9592
  { 3304 /* div_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9593
  { 3312 /* div_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9594
  { 3320 /* div_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9595
  { 3328 /* div_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9596
  { 3336 /* div_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9597
  { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9598
  { 3344 /* divu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9599
  { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9600
  { 3344 /* divu */, 1 /* 0 */, MCK_GPR32NonZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9601
  { 3344 /* divu */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9602
  { 3344 /* divu */, 1 /* 0 */, MCK_GPR32ZeroAsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9603
  { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
9604
  { 3344 /* divu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9605
  { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9606
  { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
9607
  { 3344 /* divu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9608
  { 3344 /* divu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
9609
  { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9610
  { 3349 /* dla */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9611
  { 3349 /* dla */, 2 /* 1 */, MCK_Mem, AMFBS_None },
9612
  { 3353 /* dli */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9613
  { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9614
  { 3357 /* dlsa */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9615
  { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9616
  { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips },
9617
  { 3362 /* dmfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9618
  { 3362 /* dmfc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9619
  { 3368 /* dmfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips },
9620
  { 3368 /* dmfc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips },
9621
  { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9622
  { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9623
  { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9624
  { 3374 /* dmfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9625
  { 3374 /* dmfc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9626
  { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9627
  { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9628
  { 3380 /* dmfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9629
  { 3380 /* dmfgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9630
  { 3387 /* dmod */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9631
  { 3392 /* dmodu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9632
  { 3398 /* dmt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9633
  { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_NotInMicroMips },
9634
  { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMicroMips },
9635
  { 3402 /* dmtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9636
  { 3402 /* dmtc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9637
  { 3408 /* dmtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips },
9638
  { 3408 /* dmtc1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips },
9639
  { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_None },
9640
  { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_None },
9641
  { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9642
  { 3414 /* dmtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9643
  { 3414 /* dmtc2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3 },
9644
  { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9645
  { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt_NotInMicroMips },
9646
  { 3420 /* dmtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9647
  { 3420 /* dmtgc0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r5_HasVirt },
9648
  { 3427 /* dmuh */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9649
  { 3432 /* dmuhu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9650
  { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9651
  { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasMips3_NotMips64r6_NotCnMips },
9652
  { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9653
  { 3438 /* dmul */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9654
  { 3438 /* dmul */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9655
  { 3443 /* dmulo */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9656
  { 3449 /* dmulou */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9657
  { 3456 /* dmult */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9658
  { 3462 /* dmultu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9659
  { 3469 /* dmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
9660
  { 3475 /* dneg */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9661
  { 3475 /* dneg */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9662
  { 3480 /* dnegu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9663
  { 3480 /* dnegu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9664
  { 3486 /* dotp_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9665
  { 3495 /* dotp_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9666
  { 3504 /* dotp_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9667
  { 3513 /* dotp_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9668
  { 3522 /* dotp_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9669
  { 3531 /* dotp_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9670
  { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9671
  { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9672
  { 3540 /* dpa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9673
  { 3540 /* dpa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9674
  { 3549 /* dpadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9675
  { 3559 /* dpadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9676
  { 3569 /* dpadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9677
  { 3579 /* dpadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9678
  { 3589 /* dpadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9679
  { 3599 /* dpadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9680
  { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9681
  { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9682
  { 3609 /* dpaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9683
  { 3609 /* dpaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9684
  { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9685
  { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9686
  { 3621 /* dpaq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9687
  { 3621 /* dpaq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9688
  { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9689
  { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9690
  { 3633 /* dpaqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9691
  { 3633 /* dpaqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9692
  { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9693
  { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9694
  { 3646 /* dpaqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9695
  { 3646 /* dpaqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9696
  { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9697
  { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9698
  { 3660 /* dpau.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9699
  { 3660 /* dpau.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9700
  { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9701
  { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9702
  { 3671 /* dpau.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9703
  { 3671 /* dpau.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9704
  { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9705
  { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9706
  { 3682 /* dpax.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9707
  { 3682 /* dpax.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9708
  { 3692 /* dpop */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9709
  { 3692 /* dpop */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
9710
  { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9711
  { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9712
  { 3697 /* dps.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9713
  { 3697 /* dps.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9714
  { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9715
  { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9716
  { 3706 /* dpsq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9717
  { 3706 /* dpsq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9718
  { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9719
  { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9720
  { 3718 /* dpsq_sa.l.w */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9721
  { 3718 /* dpsq_sa.l.w */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9722
  { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9723
  { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9724
  { 3730 /* dpsqx_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9725
  { 3730 /* dpsqx_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9726
  { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9727
  { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9728
  { 3743 /* dpsqx_sa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9729
  { 3743 /* dpsqx_sa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9730
  { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9731
  { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9732
  { 3757 /* dpsu.h.qbl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9733
  { 3757 /* dpsu.h.qbl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9734
  { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9735
  { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9736
  { 3768 /* dpsu.h.qbr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9737
  { 3768 /* dpsu.h.qbr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9738
  { 3779 /* dpsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9739
  { 3789 /* dpsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9740
  { 3799 /* dpsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9741
  { 3809 /* dpsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9742
  { 3819 /* dpsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9743
  { 3829 /* dpsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9744
  { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
9745
  { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
9746
  { 3839 /* dpsx.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
9747
  { 3839 /* dpsx.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
9748
  { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9749
  { 3849 /* drem */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9750
  { 3849 /* drem */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9751
  { 3849 /* drem */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9752
  { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9753
  { 3854 /* dremu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9754
  { 3854 /* dremu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9755
  { 3854 /* dremu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
9756
  { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9757
  { 3860 /* drol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9758
  { 3860 /* drol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9759
  { 3860 /* drol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9760
  { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9761
  { 3865 /* dror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9762
  { 3865 /* dror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9763
  { 3865 /* dror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64 },
9764
  { 3870 /* drotr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9765
  { 3870 /* drotr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9766
  { 3876 /* drotr32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9767
  { 3876 /* drotr32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9768
  { 3884 /* drotrv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9769
  { 3884 /* drotrv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9770
  { 3891 /* dsbh */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9771
  { 3896 /* dshd */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
9772
  { 3901 /* dsll */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9773
  { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9774
  { 3901 /* dsll */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9775
  { 3901 /* dsll */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9776
  { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9777
  { 3901 /* dsll */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9778
  { 3906 /* dsll32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9779
  { 3906 /* dsll32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9780
  { 3913 /* dsllv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9781
  { 3913 /* dsllv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9782
  { 3919 /* dsra */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9783
  { 3919 /* dsra */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3 },
9784
  { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3 },
9785
  { 3919 /* dsra */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9786
  { 3924 /* dsra32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9787
  { 3924 /* dsra32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9788
  { 3931 /* dsrav */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9789
  { 3931 /* dsrav */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9790
  { 3937 /* dsrl */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9791
  { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9792
  { 3937 /* dsrl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9793
  { 3937 /* dsrl */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9794
  { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9795
  { 3937 /* dsrl */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9796
  { 3942 /* dsrl32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9797
  { 3942 /* dsrl32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9798
  { 3949 /* dsrlv */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9799
  { 3949 /* dsrlv */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9800
  { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9801
  { 3955 /* dsub */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9802
  { 3955 /* dsub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9803
  { 3955 /* dsub */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9804
  { 3955 /* dsub */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9805
  { 3955 /* dsub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9806
  { 3960 /* dsubi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9807
  { 3960 /* dsubi */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9808
  { 3960 /* dsubi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9809
  { 3960 /* dsubi */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
9810
  { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9811
  { 3966 /* dsubu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9812
  { 3966 /* dsubu */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9813
  { 3966 /* dsubu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9814
  { 3966 /* dsubu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9815
  { 3966 /* dsubu */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
9816
  { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9817
  { 3972 /* dvp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9818
  { 3976 /* dvpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9819
  { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9820
  { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9821
  { 3985 /* ei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
9822
  { 3988 /* emt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9823
  { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
9824
  { 4004 /* evp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9825
  { 4008 /* evpe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9826
  { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
9827
  { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
9828
  { 4013 /* ext */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
9829
  { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9830
  { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9831
  { 4017 /* extp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9832
  { 4017 /* extp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9833
  { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9834
  { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9835
  { 4022 /* extpdp */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9836
  { 4022 /* extpdp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9837
  { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9838
  { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9839
  { 4029 /* extpdpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9840
  { 4029 /* extpdpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9841
  { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9842
  { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9843
  { 4037 /* extpv */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9844
  { 4037 /* extpv */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9845
  { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9846
  { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9847
  { 4043 /* extr.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9848
  { 4043 /* extr.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9849
  { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9850
  { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9851
  { 4050 /* extr_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9852
  { 4050 /* extr_r.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9853
  { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9854
  { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9855
  { 4059 /* extr_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9856
  { 4059 /* extr_rs.w */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9857
  { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9858
  { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9859
  { 4069 /* extr_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9860
  { 4069 /* extr_s.h */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9861
  { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9862
  { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9863
  { 4078 /* extrv.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9864
  { 4078 /* extrv.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9865
  { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9866
  { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9867
  { 4086 /* extrv_r.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9868
  { 4086 /* extrv_r.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9869
  { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9870
  { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9871
  { 4096 /* extrv_rs.w */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9872
  { 4096 /* extrv_rs.w */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9873
  { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
9874
  { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
9875
  { 4107 /* extrv_s.h */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
9876
  { 4107 /* extrv_s.h */, 5 /* 0, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
9877
  { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9878
  { 4117 /* exts */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9879
  { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9880
  { 4117 /* exts */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips },
9881
  { 4122 /* exts32 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9882
  { 4122 /* exts32 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasMips64_HasCnMips_NotInMicroMips },
9883
  { 4129 /* fadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9884
  { 4136 /* fadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9885
  { 4143 /* fcaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9886
  { 4150 /* fcaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9887
  { 4157 /* fceq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9888
  { 4164 /* fceq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9889
  { 4171 /* fclass.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9890
  { 4180 /* fclass.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9891
  { 4189 /* fcle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9892
  { 4196 /* fcle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9893
  { 4203 /* fclt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9894
  { 4210 /* fclt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9895
  { 4217 /* fcne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9896
  { 4224 /* fcne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9897
  { 4231 /* fcor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9898
  { 4238 /* fcor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9899
  { 4245 /* fcueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9900
  { 4253 /* fcueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9901
  { 4261 /* fcule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9902
  { 4269 /* fcule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9903
  { 4277 /* fcult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9904
  { 4285 /* fcult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9905
  { 4293 /* fcun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9906
  { 4300 /* fcun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9907
  { 4307 /* fcune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9908
  { 4315 /* fcune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9909
  { 4323 /* fdiv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9910
  { 4330 /* fdiv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9911
  { 4337 /* fexdo.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9912
  { 4345 /* fexdo.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9913
  { 4353 /* fexp2.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9914
  { 4361 /* fexp2.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9915
  { 4369 /* fexupl.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9916
  { 4378 /* fexupl.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9917
  { 4387 /* fexupr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9918
  { 4396 /* fexupr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9919
  { 4405 /* ffint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9920
  { 4415 /* ffint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9921
  { 4425 /* ffint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9922
  { 4435 /* ffint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9923
  { 4445 /* ffql.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9924
  { 4452 /* ffql.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9925
  { 4459 /* ffqr.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9926
  { 4466 /* ffqr.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9927
  { 4473 /* fill.b */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9928
  { 4473 /* fill.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9929
  { 4480 /* fill.d */, 2 /* 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9930
  { 4480 /* fill.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
9931
  { 4487 /* fill.h */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9932
  { 4487 /* fill.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9933
  { 4494 /* fill.w */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
9934
  { 4494 /* fill.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9935
  { 4501 /* flog2.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9936
  { 4509 /* flog2.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9937
  { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
9938
  { 4517 /* floor.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9939
  { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9940
  { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9941
  { 4527 /* floor.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9942
  { 4527 /* floor.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9943
  { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9944
  { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9945
  { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9946
  { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9947
  { 4537 /* floor.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9948
  { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
9949
  { 4537 /* floor.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9950
  { 4537 /* floor.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
9951
  { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
9952
  { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
9953
  { 4547 /* floor.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
9954
  { 4557 /* fmadd.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9955
  { 4565 /* fmadd.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9956
  { 4573 /* fmax.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9957
  { 4580 /* fmax.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9958
  { 4587 /* fmax_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9959
  { 4596 /* fmax_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9960
  { 4605 /* fmin.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9961
  { 4612 /* fmin.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9962
  { 4619 /* fmin_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9963
  { 4628 /* fmin_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9964
  { 4637 /* fmsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9965
  { 4645 /* fmsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9966
  { 4653 /* fmul.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9967
  { 4660 /* fmul.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9968
  { 4667 /* fork */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
9969
  { 4672 /* frcp.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9970
  { 4679 /* frcp.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9971
  { 4686 /* frint.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9972
  { 4694 /* frint.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9973
  { 4702 /* frsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9974
  { 4711 /* frsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9975
  { 4720 /* fsaf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9976
  { 4727 /* fsaf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9977
  { 4734 /* fseq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9978
  { 4741 /* fseq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9979
  { 4748 /* fsle.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9980
  { 4755 /* fsle.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9981
  { 4762 /* fslt.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9982
  { 4769 /* fslt.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9983
  { 4776 /* fsne.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9984
  { 4783 /* fsne.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9985
  { 4790 /* fsor.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9986
  { 4797 /* fsor.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9987
  { 4804 /* fsqrt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9988
  { 4812 /* fsqrt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9989
  { 4820 /* fsub.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9990
  { 4827 /* fsub.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9991
  { 4834 /* fsueq.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9992
  { 4842 /* fsueq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9993
  { 4850 /* fsule.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9994
  { 4858 /* fsule.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9995
  { 4866 /* fsult.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9996
  { 4874 /* fsult.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9997
  { 4882 /* fsun.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9998
  { 4889 /* fsun.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
9999
  { 4896 /* fsune.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10000
  { 4904 /* fsune.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10001
  { 4912 /* ftint_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10002
  { 4922 /* ftint_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10003
  { 4932 /* ftint_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10004
  { 4942 /* ftint_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10005
  { 4952 /* ftq.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10006
  { 4958 /* ftq.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10007
  { 4964 /* ftrunc_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10008
  { 4975 /* ftrunc_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10009
  { 4986 /* ftrunc_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10010
  { 4997 /* ftrunc_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10011
  { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips },
10012
  { 5008 /* ginvi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV },
10013
  { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips },
10014
  { 5014 /* ginvt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_HasGINV },
10015
  { 5020 /* hadd_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10016
  { 5029 /* hadd_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10017
  { 5038 /* hadd_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10018
  { 5047 /* hadd_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10019
  { 5056 /* hadd_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10020
  { 5065 /* hadd_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10021
  { 5074 /* hsub_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10022
  { 5083 /* hsub_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10023
  { 5092 /* hsub_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10024
  { 5101 /* hsub_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10025
  { 5110 /* hsub_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10026
  { 5119 /* hsub_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10027
  { 5136 /* ilvev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10028
  { 5144 /* ilvev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10029
  { 5152 /* ilvev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10030
  { 5160 /* ilvev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10031
  { 5168 /* ilvl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10032
  { 5175 /* ilvl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10033
  { 5182 /* ilvl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10034
  { 5189 /* ilvl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10035
  { 5196 /* ilvod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10036
  { 5204 /* ilvod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10037
  { 5212 /* ilvod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10038
  { 5220 /* ilvod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10039
  { 5228 /* ilvr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10040
  { 5235 /* ilvr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10041
  { 5242 /* ilvr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10042
  { 5249 /* ilvr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10043
  { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
10044
  { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10045
  { 5256 /* ins */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10046
  { 5260 /* insert.b */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10047
  { 5260 /* insert.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10048
  { 5269 /* insert.d */, 16 /* 4 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10049
  { 5269 /* insert.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA_HasMips64 },
10050
  { 5278 /* insert.h */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10051
  { 5278 /* insert.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10052
  { 5287 /* insert.w */, 16 /* 4 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10053
  { 5287 /* insert.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10054
  { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10055
  { 5296 /* insv */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10056
  { 5301 /* insve.b */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10057
  { 5309 /* insve.d */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10058
  { 5317 /* insve.h */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10059
  { 5325 /* insve.w */, 17 /* 0, 4 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10060
  { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10061
  { 5333 /* j */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10062
  { 5333 /* j */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
10063
  { 5335 /* jal */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10064
  { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_NotInMicroMips },
10065
  { 5335 /* jal */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10066
  { 5335 /* jal */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10067
  { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10068
  { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10069
  { 5339 /* jalr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
10070
  { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards },
10071
  { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10072
  { 5339 /* jalr */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit },
10073
  { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotInMicroMips },
10074
  { 5344 /* jalr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotInMicroMips },
10075
  { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32 },
10076
  { 5344 /* jalr.hb */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r2_NotInMicroMips },
10077
  { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
10078
  { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10079
  { 5352 /* jalrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10080
  { 5352 /* jalrc */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10081
  { 5358 /* jalrc.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10082
  { 5358 /* jalrc.hb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10083
  { 5367 /* jalrs */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10084
  { 5373 /* jalrs16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10085
  { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10086
  { 5386 /* jalx */, 1 /* 0 */, MCK_JumpTarget, AMFBS_InMicroMips_NotMips32r6 },
10087
  { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10088
  { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10089
  { 5391 /* jialc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10090
  { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10091
  { 5391 /* jialc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10092
  { 5391 /* jialc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10093
  { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10094
  { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips32r6 },
10095
  { 5397 /* jic */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10096
  { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_InMicroMips_HasMips32r6 },
10097
  { 5397 /* jic */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10098
  { 5397 /* jic */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_IsGP64bit_HasMips64r6 },
10099
  { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10100
  { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
10101
  { 5401 /* jr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10102
  { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips },
10103
  { 5401 /* jr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10104
  { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6 },
10105
  { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10106
  { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips },
10107
  { 5404 /* jr.hb */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10108
  { 5410 /* jr16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10109
  { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6 },
10110
  { 5425 /* jrc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10111
  { 5425 /* jrc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10112
  { 5429 /* jrc16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10113
  { 5446 /* l.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat },
10114
  { 5446 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat },
10115
  { 5446 /* l.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat },
10116
  { 5446 /* l.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat },
10117
  { 5450 /* l.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10118
  { 5450 /* l.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
10119
  { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10120
  { 5454 /* la */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10121
  { 5454 /* la */, 2 /* 1 */, MCK_Mem, AMFBS_None },
10122
  { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10123
  { 5457 /* lapc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10124
  { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10125
  { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10126
  { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10127
  { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 },
10128
  { 5462 /* lb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10129
  { 5462 /* lb */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips },
10130
  { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10131
  { 5465 /* lbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10132
  { 5465 /* lbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10133
  { 5465 /* lbe */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10134
  { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10135
  { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10136
  { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10137
  { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 },
10138
  { 5469 /* lbu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10139
  { 5469 /* lbu */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips },
10140
  { 5473 /* lbu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10141
  { 5473 /* lbu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10142
  { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10143
  { 5479 /* lbue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10144
  { 5479 /* lbue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10145
  { 5479 /* lbue */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasEVA },
10146
  { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10147
  { 5484 /* lbux */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10148
  { 5489 /* ld */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 },
10149
  { 5489 /* ld */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 },
10150
  { 5489 /* ld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10151
  { 5489 /* ld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10152
  { 5492 /* ld.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10153
  { 5492 /* ld.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA },
10154
  { 5497 /* ld.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10155
  { 5497 /* ld.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA },
10156
  { 5502 /* ld.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10157
  { 5502 /* ld.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA },
10158
  { 5507 /* ld.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10159
  { 5507 /* ld.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA },
10160
  { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
10161
  { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
10162
  { 5512 /* ldc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10163
  { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10164
  { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
10165
  { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
10166
  { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
10167
  { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
10168
  { 5512 /* ldc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10169
  { 5512 /* ldc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10170
  { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10171
  { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10172
  { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10173
  { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
10174
  { 5517 /* ldc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10175
  { 5517 /* ldc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10176
  { 5522 /* ldc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips },
10177
  { 5522 /* ldc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips },
10178
  { 5527 /* ldi.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10179
  { 5533 /* ldi.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10180
  { 5539 /* ldi.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10181
  { 5545 /* ldi.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10182
  { 5551 /* ldl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10183
  { 5551 /* ldl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10184
  { 5555 /* ldpc */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10185
  { 5555 /* ldpc */, 2 /* 1 */, MCK_JumpTarget, AMFBS_HasStdEnc_HasMips64r6 },
10186
  { 5560 /* ldr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10187
  { 5560 /* ldr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
10188
  { 5564 /* ldxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10189
  { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10190
  { 5564 /* ldxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10191
  { 5564 /* ldxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10192
  { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10193
  { 5570 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10194
  { 5570 /* lh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10195
  { 5570 /* lh */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips },
10196
  { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10197
  { 5573 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10198
  { 5573 /* lhe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10199
  { 5573 /* lhe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10200
  { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10201
  { 5577 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_NotInMicroMips },
10202
  { 5577 /* lhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10203
  { 5577 /* lhu */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_InMicroMips },
10204
  { 5581 /* lhu16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10205
  { 5581 /* lhu16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10206
  { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10207
  { 5587 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10208
  { 5587 /* lhue */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10209
  { 5587 /* lhue */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10210
  { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10211
  { 5592 /* lhx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10212
  { 5596 /* li */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10213
  { 5599 /* li.d */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10214
  { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyAFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat },
10215
  { 5599 /* li.d */, 1 /* 0 */, MCK_StrictlyFGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat },
10216
  { 5604 /* li.s */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10217
  { 5604 /* li.s */, 1 /* 0 */, MCK_StrictlyFGR32AsmReg, AMFBS_IsNotSoftFloat },
10218
  { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10219
  { 5609 /* li16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10220
  { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10221
  { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
10222
  { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10223
  { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
10224
  { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10225
  { 5614 /* ll */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 },
10226
  { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10227
  { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10228
  { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10229
  { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
10230
  { 5614 /* ll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10231
  { 5614 /* ll */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10232
  { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
10233
  { 5617 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips },
10234
  { 5617 /* lld */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10235
  { 5617 /* lld */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips64r6_NotInMicroMips },
10236
  { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10237
  { 5621 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10238
  { 5621 /* lle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10239
  { 5621 /* lle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10240
  { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
10241
  { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10242
  { 5625 /* lsa */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10243
  { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10244
  { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10245
  { 5629 /* lui */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10246
  { 5633 /* luxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10247
  { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10248
  { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10249
  { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10250
  { 5633 /* luxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
10251
  { 5633 /* luxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
10252
  { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10253
  { 5639 /* lw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips },
10254
  { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10255
  { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
10256
  { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP },
10257
  { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP },
10258
  { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10259
  { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
10260
  { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10261
  { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10262
  { 5639 /* lw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10263
  { 5639 /* lw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10264
  { 5639 /* lw */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10265
  { 5639 /* lw */, 2 /* 1 */, MCK_MicroMipsMemGP, AMFBS_InMicroMips },
10266
  { 5642 /* lw16 */, 1 /* 0 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips },
10267
  { 5642 /* lw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips },
10268
  { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10269
  { 5647 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10270
  { 5647 /* lwc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10271
  { 5647 /* lwc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat },
10272
  { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10273
  { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10274
  { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10275
  { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
10276
  { 5652 /* lwc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10277
  { 5652 /* lwc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10278
  { 5657 /* lwc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips },
10279
  { 5657 /* lwc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips },
10280
  { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10281
  { 5662 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10282
  { 5662 /* lwe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
10283
  { 5662 /* lwe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10284
  { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10285
  { 5666 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10286
  { 5666 /* lwl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10287
  { 5666 /* lwl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10288
  { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10289
  { 5670 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10290
  { 5670 /* lwle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10291
  { 5670 /* lwle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10292
  { 5675 /* lwm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10293
  { 5675 /* lwm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10294
  { 5679 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 },
10295
  { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
10296
  { 5679 /* lwm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
10297
  { 5679 /* lwm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
10298
  { 5685 /* lwm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
10299
  { 5685 /* lwm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
10300
  { 5691 /* lwp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10301
  { 5691 /* lwp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips },
10302
  { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
10303
  { 5695 /* lwpc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10304
  { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10305
  { 5700 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10306
  { 5700 /* lwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10307
  { 5700 /* lwr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10308
  { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10309
  { 5704 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
10310
  { 5704 /* lwre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10311
  { 5704 /* lwre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
10312
  { 5709 /* lwu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10313
  { 5709 /* lwu */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips_NotMips32r6 },
10314
  { 5709 /* lwu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10315
  { 5709 /* lwu */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
10316
  { 5713 /* lwupc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips64r6 },
10317
  { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10318
  { 5719 /* lwx */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10319
  { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10320
  { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
10321
  { 5723 /* lwxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10322
  { 5723 /* lwxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10323
  { 5729 /* lwxs */, 11 /* 0, 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10324
  { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10325
  { 5734 /* madd */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10326
  { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10327
  { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10328
  { 5734 /* madd */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10329
  { 5734 /* madd */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10330
  { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10331
  { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10332
  { 5739 /* madd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10333
  { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10334
  { 5746 /* madd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10335
  { 5753 /* madd_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10336
  { 5762 /* madd_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10337
  { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10338
  { 5771 /* maddf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10339
  { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10340
  { 5779 /* maddf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10341
  { 5787 /* maddr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10342
  { 5797 /* maddr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10343
  { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10344
  { 5807 /* maddu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10345
  { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10346
  { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10347
  { 5807 /* maddu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10348
  { 5807 /* maddu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10349
  { 5813 /* maddv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10350
  { 5821 /* maddv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10351
  { 5829 /* maddv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10352
  { 5837 /* maddv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10353
  { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10354
  { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10355
  { 5845 /* maq_s.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10356
  { 5845 /* maq_s.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10357
  { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10358
  { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10359
  { 5857 /* maq_s.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10360
  { 5857 /* maq_s.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10361
  { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10362
  { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10363
  { 5869 /* maq_sa.w.phl */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10364
  { 5869 /* maq_sa.w.phl */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10365
  { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10366
  { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10367
  { 5882 /* maq_sa.w.phr */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10368
  { 5882 /* maq_sa.w.phr */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10369
  { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10370
  { 5895 /* max.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10371
  { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10372
  { 5901 /* max.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10373
  { 5907 /* max_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10374
  { 5915 /* max_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10375
  { 5923 /* max_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10376
  { 5931 /* max_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10377
  { 5939 /* max_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10378
  { 5947 /* max_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10379
  { 5955 /* max_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10380
  { 5963 /* max_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10381
  { 5971 /* max_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10382
  { 5979 /* max_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10383
  { 5987 /* max_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10384
  { 5995 /* max_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10385
  { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10386
  { 6003 /* maxa.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10387
  { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10388
  { 6010 /* maxa.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10389
  { 6017 /* maxi_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10390
  { 6026 /* maxi_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10391
  { 6035 /* maxi_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10392
  { 6044 /* maxi_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10393
  { 6053 /* maxi_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10394
  { 6062 /* maxi_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10395
  { 6071 /* maxi_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10396
  { 6080 /* maxi_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10397
  { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10398
  { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10399
  { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10400
  { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10401
  { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10402
  { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10403
  { 6089 /* mfc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10404
  { 6089 /* mfc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10405
  { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10406
  { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10407
  { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10408
  { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10409
  { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10410
  { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10411
  { 6094 /* mfc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10412
  { 6094 /* mfc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10413
  { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10414
  { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10415
  { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10416
  { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10417
  { 6099 /* mfc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10418
  { 6099 /* mfc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10419
  { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10420
  { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10421
  { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10422
  { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10423
  { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10424
  { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10425
  { 6104 /* mfgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10426
  { 6104 /* mfgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10427
  { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10428
  { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10429
  { 6110 /* mfhc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10430
  { 6110 /* mfhc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10431
  { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10432
  { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10433
  { 6116 /* mfhc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10434
  { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10435
  { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10436
  { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10437
  { 6116 /* mfhc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10438
  { 6116 /* mfhc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10439
  { 6122 /* mfhc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10440
  { 6122 /* mfhc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10441
  { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10442
  { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10443
  { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10444
  { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10445
  { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10446
  { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10447
  { 6128 /* mfhgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10448
  { 6128 /* mfhgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10449
  { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10450
  { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10451
  { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10452
  { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10453
  { 6135 /* mfhi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10454
  { 6135 /* mfhi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10455
  { 6140 /* mfhi16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10456
  { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10457
  { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10458
  { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10459
  { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10460
  { 6147 /* mflo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10461
  { 6147 /* mflo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10462
  { 6152 /* mflo16 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10463
  { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10464
  { 6159 /* mftacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10465
  { 6159 /* mftacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10466
  { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10467
  { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10468
  { 6166 /* mftc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10469
  { 6166 /* mftc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10470
  { 6172 /* mftc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10471
  { 6172 /* mftc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10472
  { 6178 /* mftdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10473
  { 6185 /* mftgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10474
  { 6192 /* mfthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10475
  { 6192 /* mfthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10476
  { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10477
  { 6199 /* mfthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10478
  { 6199 /* mfthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10479
  { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10480
  { 6205 /* mftlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10481
  { 6205 /* mftlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10482
  { 6211 /* mftr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10483
  { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10484
  { 6216 /* min.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10485
  { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10486
  { 6222 /* min.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10487
  { 6228 /* min_a.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10488
  { 6236 /* min_a.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10489
  { 6244 /* min_a.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10490
  { 6252 /* min_a.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10491
  { 6260 /* min_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10492
  { 6268 /* min_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10493
  { 6276 /* min_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10494
  { 6284 /* min_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10495
  { 6292 /* min_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10496
  { 6300 /* min_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10497
  { 6308 /* min_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10498
  { 6316 /* min_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10499
  { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10500
  { 6324 /* mina.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10501
  { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10502
  { 6331 /* mina.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10503
  { 6338 /* mini_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10504
  { 6347 /* mini_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10505
  { 6356 /* mini_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10506
  { 6365 /* mini_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10507
  { 6374 /* mini_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10508
  { 6383 /* mini_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10509
  { 6392 /* mini_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10510
  { 6401 /* mini_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10511
  { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10512
  { 6410 /* mod */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10513
  { 6414 /* mod_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10514
  { 6422 /* mod_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10515
  { 6430 /* mod_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10516
  { 6438 /* mod_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10517
  { 6446 /* mod_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10518
  { 6454 /* mod_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10519
  { 6462 /* mod_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10520
  { 6470 /* mod_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10521
  { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10522
  { 6478 /* modsub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10523
  { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10524
  { 6485 /* modu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10525
  { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
10526
  { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10527
  { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10528
  { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10529
  { 6490 /* mov.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10530
  { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10531
  { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10532
  { 6496 /* mov.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10533
  { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10534
  { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10535
  { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10536
  { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips },
10537
  { 6502 /* move */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit_NotInMicroMips },
10538
  { 6507 /* move.v */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10539
  { 6514 /* move16 */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10540
  { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_NotMips32r6 },
10541
  { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_NotMips32r6 },
10542
  { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_NotMips32r6 },
10543
  { 6521 /* movep */, 12 /* 2, 3 */, MCK_GPRMM16AsmRegMoveP, AMFBS_InMicroMips_HasMips32r6 },
10544
  { 6521 /* movep */, 1 /* 0 */, MCK_GPRMM16AsmRegMovePPairFirst, AMFBS_InMicroMips_HasMips32r6 },
10545
  { 6521 /* movep */, 2 /* 1 */, MCK_GPRMM16AsmRegMovePPairSecond, AMFBS_InMicroMips_HasMips32r6 },
10546
  { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10547
  { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10548
  { 6527 /* movf */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10549
  { 6527 /* movf */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10550
  { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10551
  { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10552
  { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10553
  { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10554
  { 6532 /* movf.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10555
  { 6532 /* movf.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10556
  { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10557
  { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10558
  { 6539 /* movf.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10559
  { 6539 /* movf.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10560
  { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10561
  { 6546 /* movn */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10562
  { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10563
  { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10564
  { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10565
  { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10566
  { 6551 /* movn.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10567
  { 6551 /* movn.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10568
  { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10569
  { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10570
  { 6558 /* movn.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10571
  { 6558 /* movn.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10572
  { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10573
  { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10574
  { 6565 /* movt */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10575
  { 6565 /* movt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10576
  { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10577
  { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10578
  { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10579
  { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10580
  { 6570 /* movt.d */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10581
  { 6570 /* movt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10582
  { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10583
  { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10584
  { 6577 /* movt.s */, 4 /* 2 */, MCK_FCCAsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10585
  { 6577 /* movt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10586
  { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10587
  { 6584 /* movz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10588
  { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10589
  { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10590
  { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10591
  { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat },
10592
  { 6589 /* movz.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10593
  { 6589 /* movz.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10594
  { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10595
  { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10596
  { 6596 /* movz.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10597
  { 6596 /* movz.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
10598
  { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10599
  { 6603 /* msub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10600
  { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10601
  { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10602
  { 6603 /* msub */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10603
  { 6603 /* msub */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10604
  { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10605
  { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10606
  { 6608 /* msub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10607
  { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4 },
10608
  { 6615 /* msub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10609
  { 6622 /* msub_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10610
  { 6631 /* msub_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10611
  { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10612
  { 6640 /* msubf.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10613
  { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10614
  { 6648 /* msubf.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10615
  { 6656 /* msubr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10616
  { 6666 /* msubr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10617
  { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10618
  { 6676 /* msubu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10619
  { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10620
  { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10621
  { 6676 /* msubu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10622
  { 6676 /* msubu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10623
  { 6682 /* msubv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10624
  { 6690 /* msubv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10625
  { 6698 /* msubv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10626
  { 6706 /* msubv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10627
  { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10628
  { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10629
  { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10630
  { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10631
  { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10632
  { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10633
  { 6714 /* mtc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10634
  { 6714 /* mtc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10635
  { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10636
  { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10637
  { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10638
  { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10639
  { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10640
  { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10641
  { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10642
  { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10643
  { 6719 /* mtc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10644
  { 6719 /* mtc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10645
  { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10646
  { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10647
  { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10648
  { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10649
  { 6724 /* mtc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10650
  { 6724 /* mtc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10651
  { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10652
  { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10653
  { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10654
  { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10655
  { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10656
  { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10657
  { 6729 /* mtgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10658
  { 6729 /* mtgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10659
  { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10660
  { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10661
  { 6735 /* mthc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10662
  { 6735 /* mthc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10663
  { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10664
  { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10665
  { 6741 /* mthc1 */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10666
  { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10667
  { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10668
  { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips },
10669
  { 6741 /* mthc1 */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10670
  { 6741 /* mthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10671
  { 6747 /* mthc2 */, 2 /* 1 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10672
  { 6747 /* mthc2 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10673
  { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10674
  { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10675
  { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10676
  { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10677
  { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10678
  { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips },
10679
  { 6753 /* mthgc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10680
  { 6753 /* mthgc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r5_HasVirt },
10681
  { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10682
  { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10683
  { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10684
  { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10685
  { 6760 /* mthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10686
  { 6760 /* mthi */, 2 /* 1 */, MCK_HI32DSPAsmReg, AMFBS_HasDSP },
10687
  { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10688
  { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10689
  { 6765 /* mthlip */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10690
  { 6765 /* mthlip */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10691
  { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10692
  { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10693
  { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10694
  { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10695
  { 6772 /* mtlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10696
  { 6772 /* mtlo */, 2 /* 1 */, MCK_LO32DSPAsmReg, AMFBS_HasDSP },
10697
  { 6777 /* mtm0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10698
  { 6782 /* mtm1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10699
  { 6787 /* mtm2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10700
  { 6792 /* mtp0 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10701
  { 6797 /* mtp1 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10702
  { 6802 /* mtp2 */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
10703
  { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10704
  { 6807 /* mttacx */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10705
  { 6807 /* mttacx */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10706
  { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT_NotInMicroMips },
10707
  { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10708
  { 6814 /* mttc0 */, 2 /* 1 */, MCK_COP0AsmReg, AMFBS_HasMT },
10709
  { 6814 /* mttc0 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10710
  { 6820 /* mttc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10711
  { 6820 /* mttc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10712
  { 6826 /* mttdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10713
  { 6833 /* mttgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10714
  { 6840 /* mtthc1 */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasMT },
10715
  { 6840 /* mtthc1 */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10716
  { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10717
  { 6847 /* mtthi */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10718
  { 6847 /* mtthi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10719
  { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
10720
  { 6853 /* mttlo */, 2 /* 1 */, MCK_ACC64DSPAsmReg, AMFBS_HasMT },
10721
  { 6853 /* mttlo */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT },
10722
  { 6859 /* mttr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
10723
  { 6864 /* muh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10724
  { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10725
  { 6864 /* muh */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10726
  { 6868 /* muhu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10727
  { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10728
  { 6868 /* muhu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10729
  { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10730
  { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10731
  { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10732
  { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips },
10733
  { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10734
  { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10735
  { 6873 /* mul */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10736
  { 6873 /* mul */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10737
  { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
10738
  { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10739
  { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10740
  { 6877 /* mul.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10741
  { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10742
  { 6883 /* mul.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10743
  { 6890 /* mul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10744
  { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
10745
  { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10746
  { 6897 /* mul.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10747
  { 6903 /* mul_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10748
  { 6911 /* mul_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10749
  { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10750
  { 6919 /* mul_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10751
  { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10752
  { 6928 /* muleq_s.w.phl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10753
  { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10754
  { 6942 /* muleq_s.w.phr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10755
  { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10756
  { 6956 /* muleu_s.ph.qbl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10757
  { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10758
  { 6971 /* muleu_s.ph.qbr */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10759
  { 6986 /* mulo */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10760
  { 6986 /* mulo */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10761
  { 6991 /* mulou */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10762
  { 6991 /* mulou */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10763
  { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10764
  { 6997 /* mulq_rs.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10765
  { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10766
  { 7008 /* mulq_rs.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10767
  { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10768
  { 7018 /* mulq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10769
  { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10770
  { 7028 /* mulq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10771
  { 7037 /* mulr.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D },
10772
  { 7045 /* mulr_q.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10773
  { 7054 /* mulr_q.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10774
  { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSPR2 },
10775
  { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10776
  { 7063 /* mulsa.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSPR2 },
10777
  { 7063 /* mulsa.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10778
  { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10779
  { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10780
  { 7074 /* mulsaq_s.w.ph */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10781
  { 7074 /* mulsaq_s.w.ph */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10782
  { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10783
  { 7088 /* mult */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10784
  { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10785
  { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10786
  { 7088 /* mult */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10787
  { 7088 /* mult */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10788
  { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
10789
  { 7093 /* multu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10790
  { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
10791
  { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10792
  { 7093 /* multu */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
10793
  { 7093 /* multu */, 6 /* 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10794
  { 7099 /* mulu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10795
  { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10796
  { 7099 /* mulu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10797
  { 7104 /* mulv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10798
  { 7111 /* mulv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10799
  { 7118 /* mulv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10800
  { 7125 /* mulv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10801
  { 7132 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10802
  { 7132 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10803
  { 7132 /* neg */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10804
  { 7132 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10805
  { 7132 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10806
  { 7132 /* neg */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10807
  { 7136 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
10808
  { 7136 /* neg.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10809
  { 7136 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
10810
  { 7136 /* neg.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10811
  { 7142 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
10812
  { 7142 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat },
10813
  { 7142 /* neg.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10814
  { 7148 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10815
  { 7148 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10816
  { 7148 /* negu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10817
  { 7148 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10818
  { 7148 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10819
  { 7148 /* negu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10820
  { 7153 /* nloc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10821
  { 7160 /* nloc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10822
  { 7167 /* nloc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10823
  { 7174 /* nloc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10824
  { 7181 /* nlzc.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10825
  { 7188 /* nlzc.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10826
  { 7195 /* nlzc.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10827
  { 7202 /* nlzc.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10828
  { 7209 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10829
  { 7209 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10830
  { 7209 /* nmadd.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10831
  { 7217 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10832
  { 7217 /* nmadd.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10833
  { 7225 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10834
  { 7225 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10835
  { 7225 /* nmsub.d */, 15 /* 0, 1, 2, 3 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10836
  { 7233 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips },
10837
  { 7233 /* nmsub.s */, 15 /* 0, 1, 2, 3 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4 },
10838
  { 7245 /* nor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit },
10839
  { 7245 /* nor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
10840
  { 7245 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10841
  { 7245 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10842
  { 7245 /* nor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10843
  { 7245 /* nor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit },
10844
  { 7245 /* nor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
10845
  { 7249 /* nor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10846
  { 7255 /* nori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10847
  { 7262 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10848
  { 7262 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10849
  { 7262 /* not */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10850
  { 7262 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10851
  { 7262 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10852
  { 7262 /* not */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10853
  { 7266 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10854
  { 7266 /* not16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10855
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10856
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10857
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10858
  { 7272 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10859
  { 7272 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10860
  { 7272 /* or */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10861
  { 7272 /* or */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
10862
  { 7272 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10863
  { 7272 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10864
  { 7272 /* or */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10865
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10866
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
10867
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
10868
  { 7272 /* or */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
10869
  { 7275 /* or.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10870
  { 7280 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10871
  { 7280 /* or16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10872
  { 7285 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10873
  { 7285 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10874
  { 7285 /* ori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10875
  { 7285 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10876
  { 7285 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10877
  { 7285 /* ori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10878
  { 7289 /* ori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10879
  { 7295 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10880
  { 7295 /* packrl.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10881
  { 7311 /* pckev.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10882
  { 7319 /* pckev.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10883
  { 7327 /* pckev.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10884
  { 7335 /* pckev.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10885
  { 7343 /* pckod.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10886
  { 7351 /* pckod.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10887
  { 7359 /* pckod.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10888
  { 7367 /* pckod.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10889
  { 7375 /* pcnt.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10890
  { 7382 /* pcnt.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10891
  { 7389 /* pcnt.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10892
  { 7396 /* pcnt.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
10893
  { 7403 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10894
  { 7403 /* pick.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10895
  { 7411 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10896
  { 7411 /* pick.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10897
  { 7419 /* pll.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10898
  { 7426 /* plu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10899
  { 7433 /* pop */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasCnMips },
10900
  { 7433 /* pop */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasCnMips },
10901
  { 7437 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10902
  { 7437 /* preceq.w.phl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10903
  { 7450 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10904
  { 7450 /* preceq.w.phr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10905
  { 7463 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10906
  { 7463 /* precequ.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10907
  { 7478 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10908
  { 7478 /* precequ.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10909
  { 7494 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10910
  { 7494 /* precequ.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10911
  { 7509 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10912
  { 7509 /* precequ.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10913
  { 7525 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10914
  { 7525 /* preceu.ph.qbl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10915
  { 7539 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10916
  { 7539 /* preceu.ph.qbla */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10917
  { 7554 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10918
  { 7554 /* preceu.ph.qbr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10919
  { 7568 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10920
  { 7568 /* preceu.ph.qbra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10921
  { 7583 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10922
  { 7583 /* precr.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10923
  { 7595 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10924
  { 7595 /* precr_sra.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10925
  { 7610 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10926
  { 7610 /* precr_sra_r.ph.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10927
  { 7627 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10928
  { 7627 /* precrq.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10929
  { 7639 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10930
  { 7639 /* precrq.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10931
  { 7652 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10932
  { 7652 /* precrq_rs.ph.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10933
  { 7667 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10934
  { 7667 /* precrqu_s.qb.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10935
  { 7683 /* pref */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
10936
  { 7683 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips },
10937
  { 7683 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
10938
  { 7683 /* pref */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
10939
  { 7688 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
10940
  { 7688 /* prefe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
10941
  { 7694 /* prefx */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10942
  { 7700 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
10943
  { 7700 /* prepend */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
10944
  { 7708 /* pul.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10945
  { 7715 /* puu.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
10946
  { 7722 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10947
  { 7722 /* raddu.w.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10948
  { 7733 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10949
  { 7733 /* rddsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10950
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10951
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10952
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10953
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 },
10954
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10955
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
10956
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
10957
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_IsGP64bit },
10958
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10959
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_HasMips32r6 },
10960
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10961
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_HasStdEnc_NotInMicroMips },
10962
  { 7739 /* rdhwr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
10963
  { 7739 /* rdhwr */, 2 /* 1 */, MCK_HWRegsAsmReg, AMFBS_InMicroMips_NotMips32r6 },
10964
  { 7745 /* rdpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10965
  { 7752 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
10966
  { 7752 /* recip.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
10967
  { 7752 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
10968
  { 7752 /* recip.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
10969
  { 7760 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
10970
  { 7760 /* recip.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
10971
  { 7768 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10972
  { 7768 /* rem */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10973
  { 7768 /* rem */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10974
  { 7768 /* rem */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10975
  { 7772 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10976
  { 7772 /* remu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10977
  { 7772 /* remu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10978
  { 7772 /* remu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
10979
  { 7777 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10980
  { 7777 /* repl.ph */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10981
  { 7785 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10982
  { 7785 /* repl.qb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10983
  { 7793 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10984
  { 7793 /* replv.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10985
  { 7802 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
10986
  { 7802 /* replv.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
10987
  { 7811 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10988
  { 7811 /* rint.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10989
  { 7818 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
10990
  { 7818 /* rint.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
10991
  { 7825 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10992
  { 7825 /* rol */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10993
  { 7825 /* rol */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
10994
  { 7825 /* rol */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10995
  { 7829 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10996
  { 7829 /* ror */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
10997
  { 7829 /* ror */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_None },
10998
  { 7829 /* ror */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
10999
  { 7833 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11000
  { 7833 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11001
  { 7833 /* rotr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11002
  { 7833 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11003
  { 7833 /* rotr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11004
  { 7838 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11005
  { 7838 /* rotrv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11006
  { 7844 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
11007
  { 7844 /* round.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11008
  { 7854 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11009
  { 7854 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11010
  { 7854 /* round.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11011
  { 7854 /* round.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11012
  { 7864 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11013
  { 7864 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11014
  { 7864 /* round.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11015
  { 7864 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11016
  { 7864 /* round.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11017
  { 7864 /* round.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11018
  { 7864 /* round.w.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11019
  { 7874 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
11020
  { 7874 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11021
  { 7874 /* round.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11022
  { 7884 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11023
  { 7884 /* rsqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11024
  { 7884 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11025
  { 7884 /* rsqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
11026
  { 7892 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips },
11027
  { 7892 /* rsqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11028
  { 7900 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat },
11029
  { 7900 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat },
11030
  { 7900 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat },
11031
  { 7900 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat },
11032
  { 7900 /* s.d */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat },
11033
  { 7900 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat },
11034
  { 7900 /* s.d */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat },
11035
  { 7900 /* s.d */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat },
11036
  { 7904 /* s.s */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11037
  { 7904 /* s.s */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat },
11038
  { 7908 /* saa */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11039
  { 7908 /* saa */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP },
11040
  { 7908 /* saa */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11041
  { 7912 /* saad */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11042
  { 7912 /* saad */, 2 /* 1 */, MCK_Mem, AMFBS_HasCnMipsP },
11043
  { 7912 /* saad */, 5 /* 0, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMipsP },
11044
  { 7917 /* sat_s.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11045
  { 7925 /* sat_s.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11046
  { 7933 /* sat_s.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11047
  { 7941 /* sat_s.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11048
  { 7949 /* sat_u.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11049
  { 7957 /* sat_u.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11050
  { 7965 /* sat_u.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11051
  { 7973 /* sat_u.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11052
  { 7981 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11053
  { 7981 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11054
  { 7981 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11055
  { 7981 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11056
  { 7981 /* sb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11057
  { 7981 /* sb */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11058
  { 7984 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11059
  { 7984 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 },
11060
  { 7984 /* sb16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11061
  { 7984 /* sb16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11062
  { 7989 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11063
  { 7989 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11064
  { 7989 /* sbe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11065
  { 7989 /* sbe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11066
  { 7993 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11067
  { 7993 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips },
11068
  { 7993 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11069
  { 7993 /* sc */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips },
11070
  { 7993 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11071
  { 7993 /* sc */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasMips32r6 },
11072
  { 7993 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11073
  { 7993 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11074
  { 7993 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11075
  { 7993 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11076
  { 7993 /* sc */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11077
  { 7993 /* sc */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11078
  { 7996 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips32r6 },
11079
  { 7996 /* scd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips32r6 },
11080
  { 7996 /* scd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11081
  { 7996 /* scd */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11082
  { 8000 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11083
  { 8000 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11084
  { 8000 /* sce */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11085
  { 8000 /* sce */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11086
  { 8004 /* sd */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips3 },
11087
  { 8004 /* sd */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips3 },
11088
  { 8004 /* sd */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11089
  { 8004 /* sd */, 2 /* 1 */, MCK_MemOffsetSimmPtr, AMFBS_HasStdEnc_HasMips3_NotInMicroMips },
11090
  { 8021 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11091
  { 8021 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11092
  { 8021 /* sdc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11093
  { 8021 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11094
  { 8021 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11095
  { 8021 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11096
  { 8021 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
11097
  { 8021 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat },
11098
  { 8021 /* sdc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
11099
  { 8021 /* sdc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
11100
  { 8026 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11101
  { 8026 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11102
  { 8026 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11103
  { 8026 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
11104
  { 8026 /* sdc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11105
  { 8026 /* sdc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11106
  { 8031 /* sdc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips },
11107
  { 8031 /* sdc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips },
11108
  { 8036 /* sdl */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11109
  { 8036 /* sdl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11110
  { 8040 /* sdr */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11111
  { 8040 /* sdr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6 },
11112
  { 8044 /* sdxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11113
  { 8044 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11114
  { 8044 /* sdxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11115
  { 8044 /* sdxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11116
  { 8050 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11117
  { 8050 /* seb */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11118
  { 8050 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11119
  { 8050 /* seb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11120
  { 8054 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11121
  { 8054 /* seh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11122
  { 8054 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11123
  { 8054 /* seh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11124
  { 8058 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11125
  { 8058 /* sel.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11126
  { 8064 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11127
  { 8064 /* sel.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11128
  { 8070 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
11129
  { 8070 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11130
  { 8070 /* seleqz */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 },
11131
  { 8077 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11132
  { 8077 /* seleqz.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11133
  { 8086 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11134
  { 8086 /* seleqz.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11135
  { 8095 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips },
11136
  { 8095 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11137
  { 8095 /* selnez */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips32r6 },
11138
  { 8102 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11139
  { 8102 /* selnez.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11140
  { 8111 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips },
11141
  { 8111 /* selnez.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11142
  { 8120 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11143
  { 8120 /* seq */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11144
  { 8120 /* seq */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11145
  { 8120 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11146
  { 8120 /* seq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11147
  { 8120 /* seq */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11148
  { 8124 /* seqi */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11149
  { 8124 /* seqi */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11150
  { 8129 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11151
  { 8129 /* sge */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11152
  { 8129 /* sge */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11153
  { 8129 /* sge */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11154
  { 8129 /* sge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11155
  { 8129 /* sge */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11156
  { 8133 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11157
  { 8133 /* sgeu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11158
  { 8133 /* sgeu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11159
  { 8133 /* sgeu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11160
  { 8133 /* sgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11161
  { 8133 /* sgeu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11162
  { 8138 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11163
  { 8138 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11164
  { 8138 /* sgt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11165
  { 8138 /* sgt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11166
  { 8138 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11167
  { 8138 /* sgt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11168
  { 8138 /* sgt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11169
  { 8138 /* sgt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11170
  { 8142 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11171
  { 8142 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11172
  { 8142 /* sgtu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11173
  { 8142 /* sgtu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11174
  { 8142 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11175
  { 8142 /* sgtu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11176
  { 8142 /* sgtu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11177
  { 8142 /* sgtu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11178
  { 8147 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11179
  { 8147 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11180
  { 8147 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11181
  { 8147 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11182
  { 8147 /* sh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11183
  { 8147 /* sh */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11184
  { 8150 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11185
  { 8150 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 },
11186
  { 8150 /* sh16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11187
  { 8150 /* sh16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11188
  { 8155 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11189
  { 8155 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11190
  { 8155 /* she */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11191
  { 8155 /* she */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11192
  { 8159 /* shf.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11193
  { 8165 /* shf.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11194
  { 8171 /* shf.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11195
  { 8177 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11196
  { 8177 /* shilo */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11197
  { 8183 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_InMicroMips_HasDSP },
11198
  { 8183 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11199
  { 8183 /* shilov */, 1 /* 0 */, MCK_ACC64DSPAsmReg, AMFBS_HasDSP },
11200
  { 8183 /* shilov */, 2 /* 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11201
  { 8190 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11202
  { 8190 /* shll.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11203
  { 8198 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11204
  { 8198 /* shll.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11205
  { 8206 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11206
  { 8206 /* shll_s.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11207
  { 8216 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11208
  { 8216 /* shll_s.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11209
  { 8225 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11210
  { 8225 /* shllv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11211
  { 8234 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11212
  { 8234 /* shllv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11213
  { 8243 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11214
  { 8243 /* shllv_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11215
  { 8254 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11216
  { 8254 /* shllv_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11217
  { 8264 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11218
  { 8264 /* shra.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11219
  { 8272 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11220
  { 8272 /* shra.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11221
  { 8280 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11222
  { 8280 /* shra_r.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11223
  { 8290 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11224
  { 8290 /* shra_r.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11225
  { 8300 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11226
  { 8300 /* shra_r.w */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11227
  { 8309 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11228
  { 8309 /* shrav.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11229
  { 8318 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11230
  { 8318 /* shrav.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11231
  { 8327 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11232
  { 8327 /* shrav_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11233
  { 8338 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11234
  { 8338 /* shrav_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11235
  { 8349 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11236
  { 8349 /* shrav_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11237
  { 8359 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11238
  { 8359 /* shrl.ph */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11239
  { 8367 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11240
  { 8367 /* shrl.qb */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11241
  { 8375 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11242
  { 8375 /* shrlv.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11243
  { 8384 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11244
  { 8384 /* shrlv.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11245
  { 8400 /* sld.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11246
  { 8400 /* sld.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11247
  { 8406 /* sld.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11248
  { 8406 /* sld.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11249
  { 8412 /* sld.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11250
  { 8412 /* sld.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11251
  { 8418 /* sld.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11252
  { 8418 /* sld.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11253
  { 8424 /* sldi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11254
  { 8431 /* sldi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11255
  { 8438 /* sldi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11256
  { 8445 /* sldi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11257
  { 8452 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11258
  { 8452 /* sle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11259
  { 8452 /* sle */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11260
  { 8452 /* sle */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11261
  { 8452 /* sle */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11262
  { 8452 /* sle */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11263
  { 8456 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11264
  { 8456 /* sleu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11265
  { 8456 /* sleu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11266
  { 8456 /* sleu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11267
  { 8456 /* sleu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_IsGP32bit_NotInMicroMips },
11268
  { 8456 /* sleu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11269
  { 8461 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11270
  { 8461 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11271
  { 8461 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11272
  { 8461 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11273
  { 8461 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11274
  { 8461 /* sll */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11275
  { 8461 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11276
  { 8461 /* sll */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11277
  { 8461 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11278
  { 8461 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11279
  { 8461 /* sll */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11280
  { 8465 /* sll.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11281
  { 8471 /* sll.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11282
  { 8477 /* sll.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11283
  { 8483 /* sll.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11284
  { 8489 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11285
  { 8489 /* sll16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11286
  { 8495 /* slli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11287
  { 8502 /* slli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11288
  { 8509 /* slli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11289
  { 8516 /* slli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11290
  { 8523 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11291
  { 8523 /* sllv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11292
  { 8528 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11293
  { 8528 /* slt */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11294
  { 8528 /* slt */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11295
  { 8528 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11296
  { 8528 /* slt */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11297
  { 8528 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11298
  { 8528 /* slt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11299
  { 8528 /* slt */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11300
  { 8532 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11301
  { 8532 /* slti */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11302
  { 8537 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11303
  { 8537 /* sltiu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11304
  { 8543 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11305
  { 8543 /* sltu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11306
  { 8543 /* sltu */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11307
  { 8543 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11308
  { 8543 /* sltu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11309
  { 8543 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11310
  { 8543 /* sltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11311
  { 8543 /* sltu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_IsGP64bit },
11312
  { 8548 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11313
  { 8548 /* sne */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11314
  { 8548 /* sne */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11315
  { 8548 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11316
  { 8548 /* sne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotCnMips },
11317
  { 8548 /* sne */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11318
  { 8552 /* snei */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11319
  { 8552 /* snei */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11320
  { 8557 /* splat.b */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11321
  { 8557 /* splat.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11322
  { 8565 /* splat.d */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11323
  { 8565 /* splat.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11324
  { 8573 /* splat.h */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11325
  { 8573 /* splat.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11326
  { 8581 /* splat.w */, 8 /* 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMSA },
11327
  { 8581 /* splat.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11328
  { 8589 /* splati.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11329
  { 8598 /* splati.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11330
  { 8607 /* splati.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11331
  { 8616 /* splati.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11332
  { 8625 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11333
  { 8625 /* sqrt.d */, 3 /* 0, 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11334
  { 8625 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11335
  { 8625 /* sqrt.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
11336
  { 8632 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
11337
  { 8632 /* sqrt.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11338
  { 8639 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11339
  { 8639 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11340
  { 8639 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11341
  { 8639 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11342
  { 8639 /* sra */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11343
  { 8639 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11344
  { 8639 /* sra */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11345
  { 8639 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11346
  { 8639 /* sra */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11347
  { 8643 /* sra.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11348
  { 8649 /* sra.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11349
  { 8655 /* sra.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11350
  { 8661 /* sra.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11351
  { 8667 /* srai.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11352
  { 8674 /* srai.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11353
  { 8681 /* srai.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11354
  { 8688 /* srai.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11355
  { 8695 /* srar.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11356
  { 8702 /* srar.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11357
  { 8709 /* srar.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11358
  { 8716 /* srar.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11359
  { 8723 /* srari.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11360
  { 8731 /* srari.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11361
  { 8739 /* srari.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11362
  { 8747 /* srari.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11363
  { 8755 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11364
  { 8755 /* srav */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11365
  { 8760 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11366
  { 8760 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11367
  { 8760 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11368
  { 8760 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11369
  { 8760 /* srl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11370
  { 8760 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_NotInMicroMips },
11371
  { 8760 /* srl */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11372
  { 8760 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11373
  { 8760 /* srl */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11374
  { 8764 /* srl.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11375
  { 8770 /* srl.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11376
  { 8776 /* srl.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11377
  { 8782 /* srl.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11378
  { 8788 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11379
  { 8788 /* srl16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11380
  { 8794 /* srli.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11381
  { 8801 /* srli.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11382
  { 8808 /* srli.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11383
  { 8815 /* srli.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11384
  { 8822 /* srlr.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11385
  { 8829 /* srlr.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11386
  { 8836 /* srlr.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11387
  { 8843 /* srlr.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11388
  { 8850 /* srlri.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11389
  { 8858 /* srlri.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11390
  { 8866 /* srlri.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11391
  { 8874 /* srlri.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11392
  { 8882 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11393
  { 8882 /* srlv */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11394
  { 8893 /* st.b */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11395
  { 8893 /* st.b */, 2 /* 1 */, MCK_MemOffsetSimm10_0, AMFBS_HasStdEnc_HasMSA },
11396
  { 8898 /* st.d */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11397
  { 8898 /* st.d */, 2 /* 1 */, MCK_MemOffsetSimm10_3, AMFBS_HasStdEnc_HasMSA },
11398
  { 8903 /* st.h */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11399
  { 8903 /* st.h */, 2 /* 1 */, MCK_MemOffsetSimm10_1, AMFBS_HasStdEnc_HasMSA },
11400
  { 8908 /* st.w */, 1 /* 0 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11401
  { 8908 /* st.w */, 2 /* 1 */, MCK_MemOffsetSimm10_2, AMFBS_HasStdEnc_HasMSA },
11402
  { 8913 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11403
  { 8913 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11404
  { 8913 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11405
  { 8913 /* sub */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11406
  { 8913 /* sub */, 2 /* 1 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11407
  { 8913 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11408
  { 8913 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11409
  { 8913 /* sub */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11410
  { 8913 /* sub */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11411
  { 8913 /* sub */, 4 /* 2 */, MCK_InvNum, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6 },
11412
  { 8917 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips },
11413
  { 8917 /* sub.d */, 7 /* 0, 1, 2 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11414
  { 8917 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips },
11415
  { 8917 /* sub.d */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_IsNotSoftFloat },
11416
  { 8923 /* sub.ps */, 7 /* 0, 1, 2 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11417
  { 8930 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11418
  { 8930 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11419
  { 8930 /* sub.s */, 7 /* 0, 1, 2 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11420
  { 8936 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11421
  { 8936 /* subq.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11422
  { 8944 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11423
  { 8944 /* subq_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11424
  { 8954 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11425
  { 8954 /* subq_s.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11426
  { 8963 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11427
  { 8963 /* subqh.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11428
  { 8972 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11429
  { 8972 /* subqh.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11430
  { 8980 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11431
  { 8980 /* subqh_r.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11432
  { 8991 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11433
  { 8991 /* subqh_r.w */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11434
  { 9001 /* subs_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11435
  { 9010 /* subs_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11436
  { 9019 /* subs_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11437
  { 9028 /* subs_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11438
  { 9037 /* subs_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11439
  { 9046 /* subs_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11440
  { 9055 /* subs_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11441
  { 9064 /* subs_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11442
  { 9073 /* subsus_u.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11443
  { 9084 /* subsus_u.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11444
  { 9095 /* subsus_u.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11445
  { 9106 /* subsus_u.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11446
  { 9117 /* subsuu_s.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11447
  { 9128 /* subsuu_s.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11448
  { 9139 /* subsuu_s.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11449
  { 9150 /* subsuu_s.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11450
  { 9161 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11451
  { 9161 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11452
  { 9161 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11453
  { 9161 /* subu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11454
  { 9161 /* subu */, 2 /* 1 */, MCK_InvNum, AMFBS_None },
11455
  { 9161 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11456
  { 9161 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11457
  { 9161 /* subu */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11458
  { 9161 /* subu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_None },
11459
  { 9161 /* subu */, 4 /* 2 */, MCK_InvNum, AMFBS_None },
11460
  { 9166 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11461
  { 9166 /* subu.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11462
  { 9174 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11463
  { 9174 /* subu.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11464
  { 9182 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11465
  { 9182 /* subu16 */, 7 /* 0, 1, 2 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11466
  { 9189 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11467
  { 9189 /* subu_s.ph */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11468
  { 9199 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11469
  { 9199 /* subu_s.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSP },
11470
  { 9209 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11471
  { 9209 /* subuh.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11472
  { 9218 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSPR2 },
11473
  { 9218 /* subuh_r.qb */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasDSPR2 },
11474
  { 9229 /* subv.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11475
  { 9236 /* subv.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11476
  { 9243 /* subv.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11477
  { 9250 /* subv.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11478
  { 9257 /* subvi.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11479
  { 9265 /* subvi.d */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11480
  { 9273 /* subvi.h */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11481
  { 9281 /* subvi.w */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11482
  { 9289 /* suxc1 */, 1 /* 0 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11483
  { 9289 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11484
  { 9289 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11485
  { 9289 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips },
11486
  { 9289 /* suxc1 */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
11487
  { 9289 /* suxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat },
11488
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11489
  { 9295 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_HasMips32r6 },
11490
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11491
  { 9295 /* sw */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips },
11492
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11493
  { 9295 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotInMicroMips },
11494
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_NotInMips16Mode_HasDSP },
11495
  { 9295 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_NotInMips16Mode_HasDSP },
11496
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11497
  { 9295 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasDSP },
11498
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11499
  { 9295 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_HasMips32r6 },
11500
  { 9295 /* sw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11501
  { 9295 /* sw */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11502
  { 9298 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_NotMips32r6 },
11503
  { 9298 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_NotMips32r6 },
11504
  { 9298 /* sw16 */, 1 /* 0 */, MCK_GPRMM16AsmRegZero, AMFBS_InMicroMips_HasMips32r6 },
11505
  { 9298 /* sw16 */, 2 /* 1 */, MCK_MicroMipsMem, AMFBS_InMicroMips_HasMips32r6 },
11506
  { 9303 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11507
  { 9303 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips },
11508
  { 9303 /* swc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11509
  { 9303 /* swc1 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_IsNotSoftFloat },
11510
  { 9308 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11511
  { 9308 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_HasStdEnc_HasMips32r6_NotInMicroMips },
11512
  { 9308 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11513
  { 9308 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm11_0, AMFBS_InMicroMips_HasMips32r6 },
11514
  { 9308 /* swc2 */, 1 /* 0 */, MCK_COP2AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11515
  { 9308 /* swc2 */, 2 /* 1 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11516
  { 9313 /* swc3 */, 1 /* 0 */, MCK_COP3AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips },
11517
  { 9313 /* swc3 */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips },
11518
  { 9318 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11519
  { 9318 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips },
11520
  { 9318 /* swe */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasEVA },
11521
  { 9318 /* swe */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_HasEVA },
11522
  { 9322 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11523
  { 9322 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11524
  { 9322 /* swl */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11525
  { 9322 /* swl */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11526
  { 9326 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11527
  { 9326 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11528
  { 9326 /* swle */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11529
  { 9326 /* swle */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11530
  { 9331 /* swm */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11531
  { 9331 /* swm */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11532
  { 9335 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_NotMips32r6 },
11533
  { 9335 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_NotMips32r6 },
11534
  { 9335 /* swm16 */, 2 /* 1 */, MCK_MemOffsetUimm4, AMFBS_InMicroMips_HasMips32r6 },
11535
  { 9335 /* swm16 */, 1 /* 0 */, MCK_RegList16, AMFBS_InMicroMips_HasMips32r6 },
11536
  { 9341 /* swm32 */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips },
11537
  { 9341 /* swm32 */, 1 /* 0 */, MCK_RegList, AMFBS_InMicroMips },
11538
  { 9347 /* swp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11539
  { 9347 /* swp */, 2 /* 1 */, MCK_MemOffsetSimm12_0, AMFBS_InMicroMips },
11540
  { 9351 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11541
  { 9351 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips },
11542
  { 9351 /* swr */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11543
  { 9351 /* swr */, 2 /* 1 */, MCK_Mem, AMFBS_InMicroMips_NotMips32r6 },
11544
  { 9355 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11545
  { 9355 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips },
11546
  { 9355 /* swre */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11547
  { 9355 /* swre */, 2 /* 1 */, MCK_MemOffsetSimm9_0, AMFBS_InMicroMips_NotMips32r6_HasEVA },
11548
  { 9360 /* swsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11549
  { 9360 /* swsp */, 2 /* 1 */, MCK_MicroMipsMemSP, AMFBS_InMicroMips_NotMips32r6 },
11550
  { 9365 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11551
  { 9365 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat },
11552
  { 9365 /* swxc1 */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
11553
  { 9365 /* swxc1 */, 10 /* 1, 3 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6_IsNotSoftFloat },
11554
  { 9376 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11555
  { 9376 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_NotMips32r6 },
11556
  { 9376 /* synci */, 1 /* 0 */, MCK_MemOffsetSimm16_0, AMFBS_InMicroMips_HasMips32r6 },
11557
  { 9420 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11558
  { 9420 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11559
  { 9420 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11560
  { 9420 /* teq */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11561
  { 9424 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11562
  { 9424 /* teqi */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11563
  { 9429 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11564
  { 9429 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11565
  { 9429 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11566
  { 9429 /* tge */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11567
  { 9433 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11568
  { 9433 /* tgei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11569
  { 9438 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11570
  { 9438 /* tgeiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11571
  { 9444 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11572
  { 9444 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11573
  { 9444 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11574
  { 9444 /* tgeu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11575
  { 9529 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11576
  { 9529 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11577
  { 9529 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11578
  { 9529 /* tlt */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11579
  { 9533 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11580
  { 9533 /* tlti */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11581
  { 9538 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11582
  { 9538 /* tltiu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11583
  { 9544 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11584
  { 9544 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11585
  { 9544 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11586
  { 9544 /* tltu */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11587
  { 9549 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11588
  { 9549 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11589
  { 9549 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11590
  { 9549 /* tne */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotInMicroMips },
11591
  { 9553 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips },
11592
  { 9553 /* tnei */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11593
  { 9558 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips },
11594
  { 9558 /* trunc.l.d */, 3 /* 0, 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11595
  { 9568 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11596
  { 9568 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11597
  { 9568 /* trunc.l.s */, 2 /* 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11598
  { 9568 /* trunc.l.s */, 1 /* 0 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11599
  { 9578 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11600
  { 9578 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11601
  { 9578 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11602
  { 9578 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_NotFP64bit_IsNotSoftFloat },
11603
  { 9578 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11604
  { 9578 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips },
11605
  { 9578 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11606
  { 9578 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11607
  { 9578 /* trunc.w.d */, 2 /* 1 */, MCK_AFGR64AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat },
11608
  { 9578 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat },
11609
  { 9578 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_NotFP64bit_IsNotSoftFloat },
11610
  { 9578 /* trunc.w.d */, 1 /* 0 */, MCK_FGR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat },
11611
  { 9578 /* trunc.w.d */, 2 /* 1 */, MCK_FGR64AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat },
11612
  { 9578 /* trunc.w.d */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_IsFP64bit_IsNotSoftFloat },
11613
  { 9588 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips },
11614
  { 9588 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_HasMips32r6_IsNotSoftFloat },
11615
  { 9588 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_InMicroMips_IsNotSoftFloat },
11616
  { 9588 /* trunc.w.s */, 3 /* 0, 1 */, MCK_FGR32AsmReg, AMFBS_None },
11617
  { 9588 /* trunc.w.s */, 4 /* 2 */, MCK_GPR32AsmReg, AMFBS_None },
11618
  { 9598 /* ulh */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11619
  { 9598 /* ulh */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11620
  { 9602 /* ulhu */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11621
  { 9602 /* ulhu */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11622
  { 9607 /* ulw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11623
  { 9607 /* ulw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11624
  { 9611 /* ush */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11625
  { 9611 /* ush */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11626
  { 9615 /* usw */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_None },
11627
  { 9615 /* usw */, 2 /* 1 */, MCK_Mem, AMFBS_None },
11628
  { 9619 /* v3mulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11629
  { 9619 /* v3mulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11630
  { 9626 /* vmm0 */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11631
  { 9626 /* vmm0 */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11632
  { 9631 /* vmulu */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11633
  { 9631 /* vmulu */, 7 /* 0, 1, 2 */, MCK_GPR64AsmReg, AMFBS_HasCnMips },
11634
  { 9637 /* vshf.b */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11635
  { 9644 /* vshf.d */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11636
  { 9651 /* vshf.h */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11637
  { 9658 /* vshf.w */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11638
  { 9670 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips },
11639
  { 9670 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_InMicroMips },
11640
  { 9670 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasDSP },
11641
  { 9670 /* wrdsp */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasDSP_NotInMicroMips },
11642
  { 9676 /* wrpgpr */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11643
  { 9683 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMips32r2_NotInMicroMips },
11644
  { 9683 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11645
  { 9683 /* wsbh */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11646
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11647
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11648
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11649
  { 9688 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11650
  { 9688 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11651
  { 9688 /* xor */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11652
  { 9688 /* xor */, 1 /* 0 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
11653
  { 9688 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11654
  { 9688 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11655
  { 9688 /* xor */, 7 /* 0, 1, 2 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11656
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11657
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_IsGP32bit_NotInMicroMips },
11658
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips },
11659
  { 9688 /* xor */, 3 /* 0, 1 */, MCK_GPR64AsmReg, AMFBS_HasStdEnc_IsGP64bit_HasMips3_NotInMicroMips },
11660
  { 9692 /* xor.v */, 7 /* 0, 1, 2 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11661
  { 9698 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11662
  { 9698 /* xor16 */, 3 /* 0, 1 */, MCK_GPRMM16AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11663
  { 9704 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11664
  { 9704 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11665
  { 9704 /* xori */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11666
  { 9704 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_HasMips32r6 },
11667
  { 9704 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_NotInMicroMips },
11668
  { 9704 /* xori */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_InMicroMips_NotMips32r6 },
11669
  { 9709 /* xori.b */, 3 /* 0, 1 */, MCK_MSA128AsmReg, AMFBS_HasStdEnc_HasMSA },
11670
  { 9716 /* yield */, 1 /* 0 */, MCK_GPR32AsmReg, AMFBS_HasMT_NotInMicroMips },
11671
  { 9716 /* yield */, 3 /* 0, 1 */, MCK_GPR32AsmReg, AMFBS_HasStdEnc_HasMT_NotInMicroMips },
11672
};
11673
11674
ParseStatus MipsAsmParser::
11675
tryCustomParseOperand(OperandVector &Operands,
11676
0
                      unsigned MCK) {
11677
11678
0
  switch(MCK) {
11679
0
  case MCK_ACC64DSPAsmReg:
11680
0
    return parseAnyRegister(Operands);
11681
0
  case MCK_AFGR64AsmReg:
11682
0
    return parseAnyRegister(Operands);
11683
0
  case MCK_CCRAsmReg:
11684
0
    return parseAnyRegister(Operands);
11685
0
  case MCK_COP0AsmReg:
11686
0
    return parseAnyRegister(Operands);
11687
0
  case MCK_COP2AsmReg:
11688
0
    return parseAnyRegister(Operands);
11689
0
  case MCK_COP3AsmReg:
11690
0
    return parseAnyRegister(Operands);
11691
0
  case MCK_FCCAsmReg:
11692
0
    return parseAnyRegister(Operands);
11693
0
  case MCK_FGR32AsmReg:
11694
0
    return parseAnyRegister(Operands);
11695
0
  case MCK_FGR64AsmReg:
11696
0
    return parseAnyRegister(Operands);
11697
0
  case MCK_GPR32AsmReg:
11698
0
    return parseAnyRegister(Operands);
11699
0
  case MCK_GPR32NonZeroAsmReg:
11700
0
    return parseAnyRegister(Operands);
11701
0
  case MCK_GPR32ZeroAsmReg:
11702
0
    return parseAnyRegister(Operands);
11703
0
  case MCK_GPR64AsmReg:
11704
0
    return parseAnyRegister(Operands);
11705
0
  case MCK_GPRMM16AsmReg:
11706
0
    return parseAnyRegister(Operands);
11707
0
  case MCK_GPRMM16AsmRegMoveP:
11708
0
    return parseAnyRegister(Operands);
11709
0
  case MCK_GPRMM16AsmRegMovePPairFirst:
11710
0
    return parseAnyRegister(Operands);
11711
0
  case MCK_GPRMM16AsmRegMovePPairSecond:
11712
0
    return parseAnyRegister(Operands);
11713
0
  case MCK_GPRMM16AsmRegZero:
11714
0
    return parseAnyRegister(Operands);
11715
0
  case MCK_HI32DSPAsmReg:
11716
0
    return parseAnyRegister(Operands);
11717
0
  case MCK_HWRegsAsmReg:
11718
0
    return parseAnyRegister(Operands);
11719
0
  case MCK_LO32DSPAsmReg:
11720
0
    return parseAnyRegister(Operands);
11721
0
  case MCK_MSA128AsmReg:
11722
0
    return parseAnyRegister(Operands);
11723
0
  case MCK_MSACtrlAsmReg:
11724
0
    return parseAnyRegister(Operands);
11725
0
  case MCK_MicroMipsMemGP:
11726
0
    return parseMemOperand(Operands);
11727
0
  case MCK_MicroMipsMem:
11728
0
    return parseMemOperand(Operands);
11729
0
  case MCK_MicroMipsMemSP:
11730
0
    return parseMemOperand(Operands);
11731
0
  case MCK_InvNum:
11732
0
    return parseInvNum(Operands);
11733
0
  case MCK_JumpTarget:
11734
0
    return parseJumpTarget(Operands);
11735
0
  case MCK_MemOffsetSimmPtr:
11736
0
    return parseMemOperand(Operands);
11737
0
  case MCK_MemOffsetUimm4:
11738
0
    return parseMemOperand(Operands);
11739
0
  case MCK_MemOffsetSimm9_0:
11740
0
    return parseMemOperand(Operands);
11741
0
  case MCK_MemOffsetSimm10_0:
11742
0
    return parseMemOperand(Operands);
11743
0
  case MCK_MemOffsetSimm11_0:
11744
0
    return parseMemOperand(Operands);
11745
0
  case MCK_MemOffsetSimm12_0:
11746
0
    return parseMemOperand(Operands);
11747
0
  case MCK_MemOffsetSimm16_0:
11748
0
    return parseMemOperand(Operands);
11749
0
  case MCK_MemOffsetSimm10_1:
11750
0
    return parseMemOperand(Operands);
11751
0
  case MCK_MemOffsetSimm10_2:
11752
0
    return parseMemOperand(Operands);
11753
0
  case MCK_MemOffsetSimm10_3:
11754
0
    return parseMemOperand(Operands);
11755
0
  case MCK_Mem:
11756
0
    return parseMemOperand(Operands);
11757
0
  case MCK_RegList16:
11758
0
    return parseRegisterList(Operands);
11759
0
  case MCK_RegList:
11760
0
    return parseRegisterList(Operands);
11761
0
  case MCK_StrictlyAFGR64AsmReg:
11762
0
    return parseAnyRegister(Operands);
11763
0
  case MCK_StrictlyFGR32AsmReg:
11764
0
    return parseAnyRegister(Operands);
11765
0
  case MCK_StrictlyFGR64AsmReg:
11766
0
    return parseAnyRegister(Operands);
11767
0
  default:
11768
0
    return ParseStatus::NoMatch;
11769
0
  }
11770
0
  return ParseStatus::NoMatch;
11771
0
}
11772
11773
ParseStatus MipsAsmParser::
11774
MatchOperandParserImpl(OperandVector &Operands,
11775
                       StringRef Mnemonic,
11776
0
                       bool ParseForAllFeatures) {
11777
  // Get the current feature set.
11778
0
  const FeatureBitset &AvailableFeatures = getAvailableFeatures();
11779
11780
  // Get the next operand index.
11781
0
  unsigned NextOpNum = Operands.size() - 1;
11782
  // Search the table.
11783
0
  auto MnemonicRange =
11784
0
    std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
11785
0
                     Mnemonic, LessOpcodeOperand());
11786
11787
0
  if (MnemonicRange.first == MnemonicRange.second)
11788
0
    return ParseStatus::NoMatch;
11789
11790
0
  for (const OperandMatchEntry *it = MnemonicRange.first,
11791
0
       *ie = MnemonicRange.second; it != ie; ++it) {
11792
    // equal_range guarantees that instruction mnemonic matches.
11793
0
    assert(Mnemonic == it->getMnemonic());
11794
11795
    // check if the available features match
11796
0
    const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx];
11797
0
    if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures)
11798
0
      continue;
11799
11800
    // check if the operand in question has a custom parser.
11801
0
    if (!(it->OperandMask & (1 << NextOpNum)))
11802
0
      continue;
11803
11804
    // call custom parse method to handle the operand
11805
0
    ParseStatus Result = tryCustomParseOperand(Operands, it->Class);
11806
0
    if (!Result.isNoMatch())
11807
0
      return Result;
11808
0
  }
11809
11810
  // Okay, we had no match.
11811
0
  return ParseStatus::NoMatch;
11812
0
}
11813
11814
#endif // GET_MATCHER_IMPLEMENTATION
11815
11816
11817
#ifdef GET_MNEMONIC_SPELL_CHECKER
11818
#undef GET_MNEMONIC_SPELL_CHECKER
11819
11820
0
static std::string MipsMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) {
11821
0
  const unsigned MaxEditDist = 2;
11822
0
  std::vector<StringRef> Candidates;
11823
0
  StringRef Prev = "";
11824
11825
  // Find the appropriate table for this asm variant.
11826
0
  const MatchEntry *Start, *End;
11827
0
  switch (VariantID) {
11828
0
  default: llvm_unreachable("invalid variant!");
11829
0
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11830
0
  }
11831
11832
0
  for (auto I = Start; I < End; I++) {
11833
    // Ignore unsupported instructions.
11834
0
    const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx];
11835
0
    if ((FBS & RequiredFeatures) != RequiredFeatures)
11836
0
      continue;
11837
11838
0
    StringRef T = I->getMnemonic();
11839
    // Avoid recomputing the edit distance for the same string.
11840
0
    if (T.equals(Prev))
11841
0
      continue;
11842
11843
0
    Prev = T;
11844
0
    unsigned Dist = S.edit_distance(T, false, MaxEditDist);
11845
0
    if (Dist <= MaxEditDist)
11846
0
      Candidates.push_back(T);
11847
0
  }
11848
11849
0
  if (Candidates.empty())
11850
0
    return "";
11851
11852
0
  std::string Res = ", did you mean: ";
11853
0
  unsigned i = 0;
11854
0
  for (; i < Candidates.size() - 1; i++)
11855
0
    Res += Candidates[i].str() + ", ";
11856
0
  return Res + Candidates[i].str() + "?";
11857
0
}
11858
11859
#endif // GET_MNEMONIC_SPELL_CHECKER
11860
11861
11862
#ifdef GET_MNEMONIC_CHECKER
11863
#undef GET_MNEMONIC_CHECKER
11864
11865
static bool MipsCheckMnemonic(StringRef Mnemonic,
11866
                                const FeatureBitset &AvailableFeatures,
11867
                                unsigned VariantID) {
11868
  // Find the appropriate table for this asm variant.
11869
  const MatchEntry *Start, *End;
11870
  switch (VariantID) {
11871
  default: llvm_unreachable("invalid variant!");
11872
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
11873
  }
11874
11875
  // Search the table.
11876
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
11877
11878
  if (MnemonicRange.first == MnemonicRange.second)
11879
    return false;
11880
11881
  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
11882
       it != ie; ++it) {
11883
    const FeatureBitset &RequiredFeatures =
11884
      FeatureBitsets[it->RequiredFeaturesIdx];
11885
    if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures)
11886
      return true;
11887
  }
11888
  return false;
11889
}
11890
11891
#endif // GET_MNEMONIC_CHECKER
11892