Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Mips/MipsGenAsmWriter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Writer Source Fragment                                            *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|* From: Mips.td                                                              *|
7
|*                                                                            *|
8
\*===----------------------------------------------------------------------===*/
9
10
/// getMnemonic - This method is automatically generated by tablegen
11
/// from the instruction set description.
12
0
std::pair<const char *, uint64_t> MipsInstPrinter::getMnemonic(const MCInst *MI) {
13
14
0
#ifdef __GNUC__
15
0
#pragma GCC diagnostic push
16
0
#pragma GCC diagnostic ignored "-Woverlength-strings"
17
0
#endif
18
0
  static const char AsmStrs[] = {
19
0
  /* 0 */ "dmfc0\t\0"
20
0
  /* 7 */ "dmfgc0\t\0"
21
0
  /* 15 */ "mfhgc0\t\0"
22
0
  /* 23 */ "mthgc0\t\0"
23
0
  /* 31 */ "dmtgc0\t\0"
24
0
  /* 39 */ "mfhc0\t\0"
25
0
  /* 46 */ "mthc0\t\0"
26
0
  /* 53 */ "dmtc0\t\0"
27
0
  /* 60 */ "vmm0\t\0"
28
0
  /* 66 */ "mtm0\t\0"
29
0
  /* 72 */ "mtp0\t\0"
30
0
  /* 78 */ "bbit0\t\0"
31
0
  /* 85 */ "ldc1\t\0"
32
0
  /* 91 */ "sdc1\t\0"
33
0
  /* 97 */ "cfc1\t\0"
34
0
  /* 103 */ "dmfc1\t\0"
35
0
  /* 110 */ "mfhc1\t\0"
36
0
  /* 117 */ "mthc1\t\0"
37
0
  /* 124 */ "ctc1\t\0"
38
0
  /* 130 */ "dmtc1\t\0"
39
0
  /* 137 */ "lwc1\t\0"
40
0
  /* 143 */ "swc1\t\0"
41
0
  /* 149 */ "ldxc1\t\0"
42
0
  /* 156 */ "sdxc1\t\0"
43
0
  /* 163 */ "luxc1\t\0"
44
0
  /* 170 */ "suxc1\t\0"
45
0
  /* 177 */ "lwxc1\t\0"
46
0
  /* 184 */ "swxc1\t\0"
47
0
  /* 191 */ "mtm1\t\0"
48
0
  /* 197 */ "mtp1\t\0"
49
0
  /* 203 */ "bbit1\t\0"
50
0
  /* 210 */ "bbit032\t\0"
51
0
  /* 219 */ "bbit132\t\0"
52
0
  /* 228 */ "dsra32\t\0"
53
0
  /* 236 */ "bposge32\t\0"
54
0
  /* 246 */ "dsll32\t\0"
55
0
  /* 254 */ "dsrl32\t\0"
56
0
  /* 262 */ "lwm32\t\0"
57
0
  /* 269 */ "swm32\t\0"
58
0
  /* 276 */ "drotr32\t\0"
59
0
  /* 285 */ "cins32\t\0"
60
0
  /* 293 */ "exts32\t\0"
61
0
  /* 301 */ "ldc2\t\0"
62
0
  /* 307 */ "sdc2\t\0"
63
0
  /* 313 */ "cfc2\t\0"
64
0
  /* 319 */ "dmfc2\t\0"
65
0
  /* 326 */ "mfhc2\t\0"
66
0
  /* 333 */ "mthc2\t\0"
67
0
  /* 340 */ "ctc2\t\0"
68
0
  /* 346 */ "dmtc2\t\0"
69
0
  /* 353 */ "lwc2\t\0"
70
0
  /* 359 */ "swc2\t\0"
71
0
  /* 365 */ "mtm2\t\0"
72
0
  /* 371 */ "mtp2\t\0"
73
0
  /* 377 */ "addiur2\t\0"
74
0
  /* 386 */ "ldc3\t\0"
75
0
  /* 392 */ "sdc3\t\0"
76
0
  /* 398 */ "lwc3\t\0"
77
0
  /* 404 */ "swc3\t\0"
78
0
  /* 410 */ "addius5\t\0"
79
0
  /* 419 */ "sb16\t\0"
80
0
  /* 425 */ "bc16\t\0"
81
0
  /* 431 */ "jrc16\t\0"
82
0
  /* 438 */ "bnezc16\t\0"
83
0
  /* 447 */ "beqzc16\t\0"
84
0
  /* 456 */ "and16\t\0"
85
0
  /* 463 */ "move16\t\0"
86
0
  /* 471 */ "sh16\t\0"
87
0
  /* 477 */ "andi16\t\0"
88
0
  /* 485 */ "mfhi16\t\0"
89
0
  /* 493 */ "li16\t\0"
90
0
  /* 499 */ "break16\t\0"
91
0
  /* 508 */ "sll16\t\0"
92
0
  /* 515 */ "srl16\t\0"
93
0
  /* 522 */ "lwm16\t\0"
94
0
  /* 529 */ "swm16\t\0"
95
0
  /* 536 */ "mflo16\t\0"
96
0
  /* 544 */ "sdbbp16\t\0"
97
0
  /* 553 */ "jr16\t\0"
98
0
  /* 559 */ "xor16\t\0"
99
0
  /* 566 */ "jalrs16\t\0"
100
0
  /* 575 */ "not16\t\0"
101
0
  /* 582 */ "lbu16\t\0"
102
0
  /* 589 */ "subu16\t\0"
103
0
  /* 597 */ "addu16\t\0"
104
0
  /* 605 */ "lhu16\t\0"
105
0
  /* 612 */ "lw16\t\0"
106
0
  /* 618 */ "sw16\t\0"
107
0
  /* 624 */ "bnez16\t\0"
108
0
  /* 632 */ "beqz16\t\0"
109
0
  /* 640 */ "saa\t\0"
110
0
  /* 645 */ "preceu.ph.qbla\t\0"
111
0
  /* 661 */ "precequ.ph.qbla\t\0"
112
0
  /* 678 */ "dla\t\0"
113
0
  /* 683 */ "preceu.ph.qbra\t\0"
114
0
  /* 699 */ "precequ.ph.qbra\t\0"
115
0
  /* 716 */ "dsra\t\0"
116
0
  /* 722 */ "dlsa\t\0"
117
0
  /* 728 */ "cfcmsa\t\0"
118
0
  /* 736 */ "ctcmsa\t\0"
119
0
  /* 744 */ "add_a.b\t\0"
120
0
  /* 753 */ "min_a.b\t\0"
121
0
  /* 762 */ "adds_a.b\t\0"
122
0
  /* 772 */ "max_a.b\t\0"
123
0
  /* 781 */ "sra.b\t\0"
124
0
  /* 788 */ "nloc.b\t\0"
125
0
  /* 796 */ "nlzc.b\t\0"
126
0
  /* 804 */ "sld.b\t\0"
127
0
  /* 811 */ "pckod.b\t\0"
128
0
  /* 820 */ "ilvod.b\t\0"
129
0
  /* 829 */ "insve.b\t\0"
130
0
  /* 838 */ "vshf.b\t\0"
131
0
  /* 846 */ "bneg.b\t\0"
132
0
  /* 854 */ "srai.b\t\0"
133
0
  /* 862 */ "sldi.b\t\0"
134
0
  /* 870 */ "andi.b\t\0"
135
0
  /* 878 */ "bnegi.b\t\0"
136
0
  /* 887 */ "bseli.b\t\0"
137
0
  /* 896 */ "slli.b\t\0"
138
0
  /* 904 */ "srli.b\t\0"
139
0
  /* 912 */ "binsli.b\t\0"
140
0
  /* 922 */ "ceqi.b\t\0"
141
0
  /* 930 */ "srari.b\t\0"
142
0
  /* 939 */ "bclri.b\t\0"
143
0
  /* 948 */ "srlri.b\t\0"
144
0
  /* 957 */ "nori.b\t\0"
145
0
  /* 965 */ "xori.b\t\0"
146
0
  /* 973 */ "binsri.b\t\0"
147
0
  /* 983 */ "splati.b\t\0"
148
0
  /* 993 */ "bseti.b\t\0"
149
0
  /* 1002 */ "subvi.b\t\0"
150
0
  /* 1011 */ "addvi.b\t\0"
151
0
  /* 1020 */ "bmzi.b\t\0"
152
0
  /* 1028 */ "bmnzi.b\t\0"
153
0
  /* 1037 */ "fill.b\t\0"
154
0
  /* 1045 */ "sll.b\t\0"
155
0
  /* 1052 */ "srl.b\t\0"
156
0
  /* 1059 */ "binsl.b\t\0"
157
0
  /* 1068 */ "ilvl.b\t\0"
158
0
  /* 1076 */ "ceq.b\t\0"
159
0
  /* 1083 */ "srar.b\t\0"
160
0
  /* 1091 */ "bclr.b\t\0"
161
0
  /* 1099 */ "srlr.b\t\0"
162
0
  /* 1107 */ "binsr.b\t\0"
163
0
  /* 1116 */ "ilvr.b\t\0"
164
0
  /* 1124 */ "asub_s.b\t\0"
165
0
  /* 1134 */ "mod_s.b\t\0"
166
0
  /* 1143 */ "cle_s.b\t\0"
167
0
  /* 1152 */ "ave_s.b\t\0"
168
0
  /* 1161 */ "clei_s.b\t\0"
169
0
  /* 1171 */ "mini_s.b\t\0"
170
0
  /* 1181 */ "clti_s.b\t\0"
171
0
  /* 1191 */ "maxi_s.b\t\0"
172
0
  /* 1201 */ "min_s.b\t\0"
173
0
  /* 1210 */ "aver_s.b\t\0"
174
0
  /* 1220 */ "subs_s.b\t\0"
175
0
  /* 1230 */ "adds_s.b\t\0"
176
0
  /* 1240 */ "sat_s.b\t\0"
177
0
  /* 1249 */ "clt_s.b\t\0"
178
0
  /* 1258 */ "subsuu_s.b\t\0"
179
0
  /* 1270 */ "div_s.b\t\0"
180
0
  /* 1279 */ "max_s.b\t\0"
181
0
  /* 1288 */ "copy_s.b\t\0"
182
0
  /* 1298 */ "splat.b\t\0"
183
0
  /* 1307 */ "bset.b\t\0"
184
0
  /* 1315 */ "pcnt.b\t\0"
185
0
  /* 1323 */ "insert.b\t\0"
186
0
  /* 1333 */ "st.b\t\0"
187
0
  /* 1339 */ "asub_u.b\t\0"
188
0
  /* 1349 */ "mod_u.b\t\0"
189
0
  /* 1358 */ "cle_u.b\t\0"
190
0
  /* 1367 */ "ave_u.b\t\0"
191
0
  /* 1376 */ "clei_u.b\t\0"
192
0
  /* 1386 */ "mini_u.b\t\0"
193
0
  /* 1396 */ "clti_u.b\t\0"
194
0
  /* 1406 */ "maxi_u.b\t\0"
195
0
  /* 1416 */ "min_u.b\t\0"
196
0
  /* 1425 */ "aver_u.b\t\0"
197
0
  /* 1435 */ "subs_u.b\t\0"
198
0
  /* 1445 */ "adds_u.b\t\0"
199
0
  /* 1455 */ "subsus_u.b\t\0"
200
0
  /* 1467 */ "sat_u.b\t\0"
201
0
  /* 1476 */ "clt_u.b\t\0"
202
0
  /* 1485 */ "div_u.b\t\0"
203
0
  /* 1494 */ "max_u.b\t\0"
204
0
  /* 1503 */ "copy_u.b\t\0"
205
0
  /* 1513 */ "msubv.b\t\0"
206
0
  /* 1522 */ "maddv.b\t\0"
207
0
  /* 1531 */ "pckev.b\t\0"
208
0
  /* 1540 */ "ilvev.b\t\0"
209
0
  /* 1549 */ "mulv.b\t\0"
210
0
  /* 1557 */ "bz.b\t\0"
211
0
  /* 1563 */ "bnz.b\t\0"
212
0
  /* 1570 */ "crc32b\t\0"
213
0
  /* 1578 */ "crc32cb\t\0"
214
0
  /* 1587 */ "seb\t\0"
215
0
  /* 1592 */ "jalrc.hb\t\0"
216
0
  /* 1602 */ "jr.hb\t\0"
217
0
  /* 1609 */ "jalr.hb\t\0"
218
0
  /* 1618 */ "lb\t\0"
219
0
  /* 1622 */ "shra.qb\t\0"
220
0
  /* 1631 */ "cmpgdu.le.qb\t\0"
221
0
  /* 1645 */ "cmpgu.le.qb\t\0"
222
0
  /* 1658 */ "cmpu.le.qb\t\0"
223
0
  /* 1670 */ "subuh.qb\t\0"
224
0
  /* 1680 */ "adduh.qb\t\0"
225
0
  /* 1690 */ "pick.qb\t\0"
226
0
  /* 1699 */ "shll.qb\t\0"
227
0
  /* 1708 */ "repl.qb\t\0"
228
0
  /* 1717 */ "shrl.qb\t\0"
229
0
  /* 1726 */ "cmpgdu.eq.qb\t\0"
230
0
  /* 1740 */ "cmpgu.eq.qb\t\0"
231
0
  /* 1753 */ "cmpu.eq.qb\t\0"
232
0
  /* 1765 */ "shra_r.qb\t\0"
233
0
  /* 1776 */ "subuh_r.qb\t\0"
234
0
  /* 1788 */ "adduh_r.qb\t\0"
235
0
  /* 1800 */ "shrav_r.qb\t\0"
236
0
  /* 1812 */ "absq_s.qb\t\0"
237
0
  /* 1823 */ "subu_s.qb\t\0"
238
0
  /* 1834 */ "addu_s.qb\t\0"
239
0
  /* 1845 */ "cmpgdu.lt.qb\t\0"
240
0
  /* 1859 */ "cmpgu.lt.qb\t\0"
241
0
  /* 1872 */ "cmpu.lt.qb\t\0"
242
0
  /* 1884 */ "subu.qb\t\0"
243
0
  /* 1893 */ "addu.qb\t\0"
244
0
  /* 1902 */ "shrav.qb\t\0"
245
0
  /* 1912 */ "shllv.qb\t\0"
246
0
  /* 1922 */ "replv.qb\t\0"
247
0
  /* 1932 */ "shrlv.qb\t\0"
248
0
  /* 1942 */ "raddu.w.qb\t\0"
249
0
  /* 1954 */ "sb\t\0"
250
0
  /* 1958 */ "modsub\t\0"
251
0
  /* 1966 */ "msub\t\0"
252
0
  /* 1972 */ "bposge32c\t\0"
253
0
  /* 1983 */ "bc\t\0"
254
0
  /* 1987 */ "bgec\t\0"
255
0
  /* 1993 */ "bnec\t\0"
256
0
  /* 1999 */ "jic\t\0"
257
0
  /* 2004 */ "balc\t\0"
258
0
  /* 2010 */ "jialc\t\0"
259
0
  /* 2017 */ "bgezalc\t\0"
260
0
  /* 2026 */ "blezalc\t\0"
261
0
  /* 2035 */ "bnezalc\t\0"
262
0
  /* 2044 */ "beqzalc\t\0"
263
0
  /* 2053 */ "bgtzalc\t\0"
264
0
  /* 2062 */ "bltzalc\t\0"
265
0
  /* 2071 */ "sync\t\0"
266
0
  /* 2077 */ "ldpc\t\0"
267
0
  /* 2083 */ "auipc\t\0"
268
0
  /* 2090 */ "aluipc\t\0"
269
0
  /* 2098 */ "addiupc\t\0"
270
0
  /* 2107 */ "lwupc\t\0"
271
0
  /* 2114 */ "lwpc\t\0"
272
0
  /* 2120 */ "beqc\t\0"
273
0
  /* 2126 */ "jrc\t\0"
274
0
  /* 2131 */ "jalrc\t\0"
275
0
  /* 2138 */ "addsc\t\0"
276
0
  /* 2145 */ "bltc\t\0"
277
0
  /* 2151 */ "bgeuc\t\0"
278
0
  /* 2158 */ "bltuc\t\0"
279
0
  /* 2165 */ "bnvc\t\0"
280
0
  /* 2171 */ "bovc\t\0"
281
0
  /* 2177 */ "addwc\t\0"
282
0
  /* 2184 */ "bgezc\t\0"
283
0
  /* 2191 */ "blezc\t\0"
284
0
  /* 2198 */ "bc1nezc\t\0"
285
0
  /* 2207 */ "bc2nezc\t\0"
286
0
  /* 2216 */ "bnezc\t\0"
287
0
  /* 2223 */ "bc1eqzc\t\0"
288
0
  /* 2232 */ "bc2eqzc\t\0"
289
0
  /* 2241 */ "beqzc\t\0"
290
0
  /* 2248 */ "bgtzc\t\0"
291
0
  /* 2255 */ "bltzc\t\0"
292
0
  /* 2262 */ "flog2.d\t\0"
293
0
  /* 2271 */ "fexp2.d\t\0"
294
0
  /* 2280 */ "add_a.d\t\0"
295
0
  /* 2289 */ "fmin_a.d\t\0"
296
0
  /* 2299 */ "adds_a.d\t\0"
297
0
  /* 2309 */ "fmax_a.d\t\0"
298
0
  /* 2319 */ "mina.d\t\0"
299
0
  /* 2327 */ "sra.d\t\0"
300
0
  /* 2334 */ "maxa.d\t\0"
301
0
  /* 2342 */ "fsub.d\t\0"
302
0
  /* 2350 */ "fmsub.d\t\0"
303
0
  /* 2359 */ "nmsub.d\t\0"
304
0
  /* 2368 */ "nloc.d\t\0"
305
0
  /* 2376 */ "nlzc.d\t\0"
306
0
  /* 2384 */ "fadd.d\t\0"
307
0
  /* 2392 */ "fmadd.d\t\0"
308
0
  /* 2401 */ "nmadd.d\t\0"
309
0
  /* 2410 */ "sld.d\t\0"
310
0
  /* 2417 */ "pckod.d\t\0"
311
0
  /* 2426 */ "ilvod.d\t\0"
312
0
  /* 2435 */ "c.nge.d\t\0"
313
0
  /* 2444 */ "c.le.d\t\0"
314
0
  /* 2452 */ "cmp.le.d\t\0"
315
0
  /* 2462 */ "fcle.d\t\0"
316
0
  /* 2470 */ "c.ngle.d\t\0"
317
0
  /* 2480 */ "c.ole.d\t\0"
318
0
  /* 2489 */ "cmp.sle.d\t\0"
319
0
  /* 2500 */ "fsle.d\t\0"
320
0
  /* 2508 */ "c.ule.d\t\0"
321
0
  /* 2517 */ "cmp.ule.d\t\0"
322
0
  /* 2528 */ "fcule.d\t\0"
323
0
  /* 2537 */ "cmp.sule.d\t\0"
324
0
  /* 2549 */ "fsule.d\t\0"
325
0
  /* 2558 */ "fcne.d\t\0"
326
0
  /* 2566 */ "fsne.d\t\0"
327
0
  /* 2574 */ "fcune.d\t\0"
328
0
  /* 2583 */ "fsune.d\t\0"
329
0
  /* 2592 */ "insve.d\t\0"
330
0
  /* 2601 */ "c.f.d\t\0"
331
0
  /* 2608 */ "cmp.af.d\t\0"
332
0
  /* 2618 */ "fcaf.d\t\0"
333
0
  /* 2626 */ "cmp.saf.d\t\0"
334
0
  /* 2637 */ "fsaf.d\t\0"
335
0
  /* 2645 */ "msubf.d\t\0"
336
0
  /* 2654 */ "maddf.d\t\0"
337
0
  /* 2663 */ "vshf.d\t\0"
338
0
  /* 2671 */ "c.sf.d\t\0"
339
0
  /* 2679 */ "movf.d\t\0"
340
0
  /* 2687 */ "bneg.d\t\0"
341
0
  /* 2695 */ "srai.d\t\0"
342
0
  /* 2703 */ "sldi.d\t\0"
343
0
  /* 2711 */ "bnegi.d\t\0"
344
0
  /* 2720 */ "slli.d\t\0"
345
0
  /* 2728 */ "srli.d\t\0"
346
0
  /* 2736 */ "binsli.d\t\0"
347
0
  /* 2746 */ "ceqi.d\t\0"
348
0
  /* 2754 */ "srari.d\t\0"
349
0
  /* 2763 */ "bclri.d\t\0"
350
0
  /* 2772 */ "srlri.d\t\0"
351
0
  /* 2781 */ "binsri.d\t\0"
352
0
  /* 2791 */ "splati.d\t\0"
353
0
  /* 2801 */ "bseti.d\t\0"
354
0
  /* 2810 */ "subvi.d\t\0"
355
0
  /* 2819 */ "addvi.d\t\0"
356
0
  /* 2828 */ "trunc.l.d\t\0"
357
0
  /* 2839 */ "round.l.d\t\0"
358
0
  /* 2850 */ "ceil.l.d\t\0"
359
0
  /* 2860 */ "floor.l.d\t\0"
360
0
  /* 2871 */ "cvt.l.d\t\0"
361
0
  /* 2880 */ "sel.d\t\0"
362
0
  /* 2887 */ "c.ngl.d\t\0"
363
0
  /* 2896 */ "fill.d\t\0"
364
0
  /* 2904 */ "sll.d\t\0"
365
0
  /* 2911 */ "fexupl.d\t\0"
366
0
  /* 2921 */ "ffql.d\t\0"
367
0
  /* 2929 */ "srl.d\t\0"
368
0
  /* 2936 */ "binsl.d\t\0"
369
0
  /* 2945 */ "fmul.d\t\0"
370
0
  /* 2953 */ "ilvl.d\t\0"
371
0
  /* 2961 */ "fmin.d\t\0"
372
0
  /* 2969 */ "c.un.d\t\0"
373
0
  /* 2977 */ "cmp.un.d\t\0"
374
0
  /* 2987 */ "fcun.d\t\0"
375
0
  /* 2995 */ "cmp.sun.d\t\0"
376
0
  /* 3006 */ "fsun.d\t\0"
377
0
  /* 3014 */ "movn.d\t\0"
378
0
  /* 3022 */ "frcp.d\t\0"
379
0
  /* 3030 */ "recip.d\t\0"
380
0
  /* 3039 */ "c.eq.d\t\0"
381
0
  /* 3047 */ "cmp.eq.d\t\0"
382
0
  /* 3057 */ "fceq.d\t\0"
383
0
  /* 3065 */ "c.seq.d\t\0"
384
0
  /* 3074 */ "cmp.seq.d\t\0"
385
0
  /* 3085 */ "fseq.d\t\0"
386
0
  /* 3093 */ "c.ueq.d\t\0"
387
0
  /* 3102 */ "cmp.ueq.d\t\0"
388
0
  /* 3113 */ "fcueq.d\t\0"
389
0
  /* 3122 */ "cmp.sueq.d\t\0"
390
0
  /* 3134 */ "fsueq.d\t\0"
391
0
  /* 3143 */ "srar.d\t\0"
392
0
  /* 3151 */ "bclr.d\t\0"
393
0
  /* 3159 */ "srlr.d\t\0"
394
0
  /* 3167 */ "fcor.d\t\0"
395
0
  /* 3175 */ "fsor.d\t\0"
396
0
  /* 3183 */ "fexupr.d\t\0"
397
0
  /* 3193 */ "ffqr.d\t\0"
398
0
  /* 3201 */ "binsr.d\t\0"
399
0
  /* 3210 */ "ilvr.d\t\0"
400
0
  /* 3218 */ "cvt.s.d\t\0"
401
0
  /* 3227 */ "asub_s.d\t\0"
402
0
  /* 3237 */ "hsub_s.d\t\0"
403
0
  /* 3247 */ "dpsub_s.d\t\0"
404
0
  /* 3258 */ "ftrunc_s.d\t\0"
405
0
  /* 3270 */ "hadd_s.d\t\0"
406
0
  /* 3280 */ "dpadd_s.d\t\0"
407
0
  /* 3291 */ "mod_s.d\t\0"
408
0
  /* 3300 */ "cle_s.d\t\0"
409
0
  /* 3309 */ "ave_s.d\t\0"
410
0
  /* 3318 */ "clei_s.d\t\0"
411
0
  /* 3328 */ "mini_s.d\t\0"
412
0
  /* 3338 */ "clti_s.d\t\0"
413
0
  /* 3348 */ "maxi_s.d\t\0"
414
0
  /* 3358 */ "min_s.d\t\0"
415
0
  /* 3367 */ "dotp_s.d\t\0"
416
0
  /* 3377 */ "aver_s.d\t\0"
417
0
  /* 3387 */ "subs_s.d\t\0"
418
0
  /* 3397 */ "adds_s.d\t\0"
419
0
  /* 3407 */ "sat_s.d\t\0"
420
0
  /* 3416 */ "clt_s.d\t\0"
421
0
  /* 3425 */ "ffint_s.d\t\0"
422
0
  /* 3436 */ "ftint_s.d\t\0"
423
0
  /* 3447 */ "subsuu_s.d\t\0"
424
0
  /* 3459 */ "div_s.d\t\0"
425
0
  /* 3468 */ "max_s.d\t\0"
426
0
  /* 3477 */ "copy_s.d\t\0"
427
0
  /* 3487 */ "abs.d\t\0"
428
0
  /* 3494 */ "fclass.d\t\0"
429
0
  /* 3504 */ "splat.d\t\0"
430
0
  /* 3513 */ "bset.d\t\0"
431
0
  /* 3521 */ "c.ngt.d\t\0"
432
0
  /* 3530 */ "c.lt.d\t\0"
433
0
  /* 3538 */ "cmp.lt.d\t\0"
434
0
  /* 3548 */ "fclt.d\t\0"
435
0
  /* 3556 */ "c.olt.d\t\0"
436
0
  /* 3565 */ "cmp.slt.d\t\0"
437
0
  /* 3576 */ "fslt.d\t\0"
438
0
  /* 3584 */ "c.ult.d\t\0"
439
0
  /* 3593 */ "cmp.ult.d\t\0"
440
0
  /* 3604 */ "fcult.d\t\0"
441
0
  /* 3613 */ "cmp.sult.d\t\0"
442
0
  /* 3625 */ "fsult.d\t\0"
443
0
  /* 3634 */ "pcnt.d\t\0"
444
0
  /* 3642 */ "frint.d\t\0"
445
0
  /* 3651 */ "insert.d\t\0"
446
0
  /* 3661 */ "fsqrt.d\t\0"
447
0
  /* 3670 */ "frsqrt.d\t\0"
448
0
  /* 3680 */ "st.d\t\0"
449
0
  /* 3686 */ "movt.d\t\0"
450
0
  /* 3694 */ "asub_u.d\t\0"
451
0
  /* 3704 */ "hsub_u.d\t\0"
452
0
  /* 3714 */ "dpsub_u.d\t\0"
453
0
  /* 3725 */ "ftrunc_u.d\t\0"
454
0
  /* 3737 */ "hadd_u.d\t\0"
455
0
  /* 3747 */ "dpadd_u.d\t\0"
456
0
  /* 3758 */ "mod_u.d\t\0"
457
0
  /* 3767 */ "cle_u.d\t\0"
458
0
  /* 3776 */ "ave_u.d\t\0"
459
0
  /* 3785 */ "clei_u.d\t\0"
460
0
  /* 3795 */ "mini_u.d\t\0"
461
0
  /* 3805 */ "clti_u.d\t\0"
462
0
  /* 3815 */ "maxi_u.d\t\0"
463
0
  /* 3825 */ "min_u.d\t\0"
464
0
  /* 3834 */ "dotp_u.d\t\0"
465
0
  /* 3844 */ "aver_u.d\t\0"
466
0
  /* 3854 */ "subs_u.d\t\0"
467
0
  /* 3864 */ "adds_u.d\t\0"
468
0
  /* 3874 */ "subsus_u.d\t\0"
469
0
  /* 3886 */ "sat_u.d\t\0"
470
0
  /* 3895 */ "clt_u.d\t\0"
471
0
  /* 3904 */ "ffint_u.d\t\0"
472
0
  /* 3915 */ "ftint_u.d\t\0"
473
0
  /* 3926 */ "div_u.d\t\0"
474
0
  /* 3935 */ "max_u.d\t\0"
475
0
  /* 3944 */ "msubv.d\t\0"
476
0
  /* 3953 */ "maddv.d\t\0"
477
0
  /* 3962 */ "pckev.d\t\0"
478
0
  /* 3971 */ "ilvev.d\t\0"
479
0
  /* 3980 */ "fdiv.d\t\0"
480
0
  /* 3988 */ "mulv.d\t\0"
481
0
  /* 3996 */ "mov.d\t\0"
482
0
  /* 4003 */ "trunc.w.d\t\0"
483
0
  /* 4014 */ "round.w.d\t\0"
484
0
  /* 4025 */ "ceil.w.d\t\0"
485
0
  /* 4035 */ "floor.w.d\t\0"
486
0
  /* 4046 */ "cvt.w.d\t\0"
487
0
  /* 4055 */ "fmax.d\t\0"
488
0
  /* 4063 */ "bz.d\t\0"
489
0
  /* 4069 */ "selnez.d\t\0"
490
0
  /* 4079 */ "bnz.d\t\0"
491
0
  /* 4086 */ "seleqz.d\t\0"
492
0
  /* 4096 */ "movz.d\t\0"
493
0
  /* 4104 */ "crc32d\t\0"
494
0
  /* 4112 */ "saad\t\0"
495
0
  /* 4118 */ "crc32cd\t\0"
496
0
  /* 4127 */ "scd\t\0"
497
0
  /* 4132 */ "dadd\t\0"
498
0
  /* 4138 */ "madd\t\0"
499
0
  /* 4144 */ "dshd\t\0"
500
0
  /* 4150 */ "yield\t\0"
501
0
  /* 4157 */ "lld\t\0"
502
0
  /* 4162 */ "and\t\0"
503
0
  /* 4167 */ "prepend\t\0"
504
0
  /* 4176 */ "append\t\0"
505
0
  /* 4184 */ "dmod\t\0"
506
0
  /* 4190 */ "sd\t\0"
507
0
  /* 4194 */ "lbe\t\0"
508
0
  /* 4199 */ "sbe\t\0"
509
0
  /* 4204 */ "sce\t\0"
510
0
  /* 4209 */ "cachee\t\0"
511
0
  /* 4217 */ "prefe\t\0"
512
0
  /* 4224 */ "bge\t\0"
513
0
  /* 4229 */ "sge\t\0"
514
0
  /* 4234 */ "tge\t\0"
515
0
  /* 4239 */ "cache\t\0"
516
0
  /* 4246 */ "lhe\t\0"
517
0
  /* 4251 */ "she\t\0"
518
0
  /* 4256 */ "sigrie\t\0"
519
0
  /* 4264 */ "ble\t\0"
520
0
  /* 4269 */ "lle\t\0"
521
0
  /* 4274 */ "sle\t\0"
522
0
  /* 4279 */ "lwle\t\0"
523
0
  /* 4285 */ "swle\t\0"
524
0
  /* 4291 */ "bne\t\0"
525
0
  /* 4296 */ "sne\t\0"
526
0
  /* 4301 */ "tne\t\0"
527
0
  /* 4306 */ "dvpe\t\0"
528
0
  /* 4312 */ "evpe\t\0"
529
0
  /* 4318 */ "lwre\t\0"
530
0
  /* 4324 */ "swre\t\0"
531
0
  /* 4330 */ "lbue\t\0"
532
0
  /* 4336 */ "lhue\t\0"
533
0
  /* 4342 */ "move\t\0"
534
0
  /* 4348 */ "lwe\t\0"
535
0
  /* 4353 */ "swe\t\0"
536
0
  /* 4358 */ "bc1f\t\0"
537
0
  /* 4364 */ "pref\t\0"
538
0
  /* 4370 */ "movf\t\0"
539
0
  /* 4376 */ "neg\t\0"
540
0
  /* 4381 */ "add_a.h\t\0"
541
0
  /* 4390 */ "min_a.h\t\0"
542
0
  /* 4399 */ "adds_a.h\t\0"
543
0
  /* 4409 */ "max_a.h\t\0"
544
0
  /* 4418 */ "sra.h\t\0"
545
0
  /* 4425 */ "nloc.h\t\0"
546
0
  /* 4433 */ "nlzc.h\t\0"
547
0
  /* 4441 */ "sld.h\t\0"
548
0
  /* 4448 */ "pckod.h\t\0"
549
0
  /* 4457 */ "ilvod.h\t\0"
550
0
  /* 4466 */ "insve.h\t\0"
551
0
  /* 4475 */ "vshf.h\t\0"
552
0
  /* 4483 */ "bneg.h\t\0"
553
0
  /* 4491 */ "srai.h\t\0"
554
0
  /* 4499 */ "sldi.h\t\0"
555
0
  /* 4507 */ "bnegi.h\t\0"
556
0
  /* 4516 */ "slli.h\t\0"
557
0
  /* 4524 */ "srli.h\t\0"
558
0
  /* 4532 */ "binsli.h\t\0"
559
0
  /* 4542 */ "ceqi.h\t\0"
560
0
  /* 4550 */ "srari.h\t\0"
561
0
  /* 4559 */ "bclri.h\t\0"
562
0
  /* 4568 */ "srlri.h\t\0"
563
0
  /* 4577 */ "binsri.h\t\0"
564
0
  /* 4587 */ "splati.h\t\0"
565
0
  /* 4597 */ "bseti.h\t\0"
566
0
  /* 4606 */ "subvi.h\t\0"
567
0
  /* 4615 */ "addvi.h\t\0"
568
0
  /* 4624 */ "fill.h\t\0"
569
0
  /* 4632 */ "sll.h\t\0"
570
0
  /* 4639 */ "srl.h\t\0"
571
0
  /* 4646 */ "binsl.h\t\0"
572
0
  /* 4655 */ "ilvl.h\t\0"
573
0
  /* 4663 */ "fexdo.h\t\0"
574
0
  /* 4672 */ "msub_q.h\t\0"
575
0
  /* 4682 */ "madd_q.h\t\0"
576
0
  /* 4692 */ "mul_q.h\t\0"
577
0
  /* 4701 */ "msubr_q.h\t\0"
578
0
  /* 4712 */ "maddr_q.h\t\0"
579
0
  /* 4723 */ "mulr_q.h\t\0"
580
0
  /* 4733 */ "ceq.h\t\0"
581
0
  /* 4740 */ "ftq.h\t\0"
582
0
  /* 4747 */ "srar.h\t\0"
583
0
  /* 4755 */ "bclr.h\t\0"
584
0
  /* 4763 */ "srlr.h\t\0"
585
0
  /* 4771 */ "binsr.h\t\0"
586
0
  /* 4780 */ "ilvr.h\t\0"
587
0
  /* 4788 */ "asub_s.h\t\0"
588
0
  /* 4798 */ "hsub_s.h\t\0"
589
0
  /* 4808 */ "dpsub_s.h\t\0"
590
0
  /* 4819 */ "hadd_s.h\t\0"
591
0
  /* 4829 */ "dpadd_s.h\t\0"
592
0
  /* 4840 */ "mod_s.h\t\0"
593
0
  /* 4849 */ "cle_s.h\t\0"
594
0
  /* 4858 */ "ave_s.h\t\0"
595
0
  /* 4867 */ "clei_s.h\t\0"
596
0
  /* 4877 */ "mini_s.h\t\0"
597
0
  /* 4887 */ "clti_s.h\t\0"
598
0
  /* 4897 */ "maxi_s.h\t\0"
599
0
  /* 4907 */ "min_s.h\t\0"
600
0
  /* 4916 */ "dotp_s.h\t\0"
601
0
  /* 4926 */ "aver_s.h\t\0"
602
0
  /* 4936 */ "extr_s.h\t\0"
603
0
  /* 4946 */ "subs_s.h\t\0"
604
0
  /* 4956 */ "adds_s.h\t\0"
605
0
  /* 4966 */ "sat_s.h\t\0"
606
0
  /* 4975 */ "clt_s.h\t\0"
607
0
  /* 4984 */ "subsuu_s.h\t\0"
608
0
  /* 4996 */ "div_s.h\t\0"
609
0
  /* 5005 */ "extrv_s.h\t\0"
610
0
  /* 5016 */ "max_s.h\t\0"
611
0
  /* 5025 */ "copy_s.h\t\0"
612
0
  /* 5035 */ "splat.h\t\0"
613
0
  /* 5044 */ "bset.h\t\0"
614
0
  /* 5052 */ "pcnt.h\t\0"
615
0
  /* 5060 */ "insert.h\t\0"
616
0
  /* 5070 */ "st.h\t\0"
617
0
  /* 5076 */ "asub_u.h\t\0"
618
0
  /* 5086 */ "hsub_u.h\t\0"
619
0
  /* 5096 */ "dpsub_u.h\t\0"
620
0
  /* 5107 */ "hadd_u.h\t\0"
621
0
  /* 5117 */ "dpadd_u.h\t\0"
622
0
  /* 5128 */ "mod_u.h\t\0"
623
0
  /* 5137 */ "cle_u.h\t\0"
624
0
  /* 5146 */ "ave_u.h\t\0"
625
0
  /* 5155 */ "clei_u.h\t\0"
626
0
  /* 5165 */ "mini_u.h\t\0"
627
0
  /* 5175 */ "clti_u.h\t\0"
628
0
  /* 5185 */ "maxi_u.h\t\0"
629
0
  /* 5195 */ "min_u.h\t\0"
630
0
  /* 5204 */ "dotp_u.h\t\0"
631
0
  /* 5214 */ "aver_u.h\t\0"
632
0
  /* 5224 */ "subs_u.h\t\0"
633
0
  /* 5234 */ "adds_u.h\t\0"
634
0
  /* 5244 */ "subsus_u.h\t\0"
635
0
  /* 5256 */ "sat_u.h\t\0"
636
0
  /* 5265 */ "clt_u.h\t\0"
637
0
  /* 5274 */ "div_u.h\t\0"
638
0
  /* 5283 */ "max_u.h\t\0"
639
0
  /* 5292 */ "copy_u.h\t\0"
640
0
  /* 5302 */ "msubv.h\t\0"
641
0
  /* 5311 */ "maddv.h\t\0"
642
0
  /* 5320 */ "pckev.h\t\0"
643
0
  /* 5329 */ "ilvev.h\t\0"
644
0
  /* 5338 */ "mulv.h\t\0"
645
0
  /* 5346 */ "bz.h\t\0"
646
0
  /* 5352 */ "bnz.h\t\0"
647
0
  /* 5359 */ "crc32h\t\0"
648
0
  /* 5367 */ "dsbh\t\0"
649
0
  /* 5373 */ "wsbh\t\0"
650
0
  /* 5379 */ "crc32ch\t\0"
651
0
  /* 5388 */ "seh\t\0"
652
0
  /* 5393 */ "ulh\t\0"
653
0
  /* 5398 */ "shra.ph\t\0"
654
0
  /* 5407 */ "precrq.qb.ph\t\0"
655
0
  /* 5421 */ "precr.qb.ph\t\0"
656
0
  /* 5434 */ "precrqu_s.qb.ph\t\0"
657
0
  /* 5451 */ "cmp.le.ph\t\0"
658
0
  /* 5462 */ "subqh.ph\t\0"
659
0
  /* 5472 */ "addqh.ph\t\0"
660
0
  /* 5482 */ "pick.ph\t\0"
661
0
  /* 5491 */ "shll.ph\t\0"
662
0
  /* 5500 */ "repl.ph\t\0"
663
0
  /* 5509 */ "shrl.ph\t\0"
664
0
  /* 5518 */ "packrl.ph\t\0"
665
0
  /* 5529 */ "mul.ph\t\0"
666
0
  /* 5537 */ "subq.ph\t\0"
667
0
  /* 5546 */ "addq.ph\t\0"
668
0
  /* 5555 */ "cmp.eq.ph\t\0"
669
0
  /* 5566 */ "shra_r.ph\t\0"
670
0
  /* 5577 */ "subqh_r.ph\t\0"
671
0
  /* 5589 */ "addqh_r.ph\t\0"
672
0
  /* 5601 */ "shrav_r.ph\t\0"
673
0
  /* 5613 */ "shll_s.ph\t\0"
674
0
  /* 5624 */ "mul_s.ph\t\0"
675
0
  /* 5634 */ "subq_s.ph\t\0"
676
0
  /* 5645 */ "addq_s.ph\t\0"
677
0
  /* 5656 */ "mulq_s.ph\t\0"
678
0
  /* 5667 */ "absq_s.ph\t\0"
679
0
  /* 5678 */ "subu_s.ph\t\0"
680
0
  /* 5689 */ "addu_s.ph\t\0"
681
0
  /* 5700 */ "shllv_s.ph\t\0"
682
0
  /* 5712 */ "mulq_rs.ph\t\0"
683
0
  /* 5724 */ "cmp.lt.ph\t\0"
684
0
  /* 5735 */ "subu.ph\t\0"
685
0
  /* 5744 */ "addu.ph\t\0"
686
0
  /* 5753 */ "shrav.ph\t\0"
687
0
  /* 5763 */ "shllv.ph\t\0"
688
0
  /* 5773 */ "replv.ph\t\0"
689
0
  /* 5783 */ "shrlv.ph\t\0"
690
0
  /* 5793 */ "dpa.w.ph\t\0"
691
0
  /* 5803 */ "dpaqx_sa.w.ph\t\0"
692
0
  /* 5818 */ "dpsqx_sa.w.ph\t\0"
693
0
  /* 5833 */ "mulsa.w.ph\t\0"
694
0
  /* 5845 */ "dpaq_s.w.ph\t\0"
695
0
  /* 5858 */ "mulsaq_s.w.ph\t\0"
696
0
  /* 5873 */ "dpsq_s.w.ph\t\0"
697
0
  /* 5886 */ "dpaqx_s.w.ph\t\0"
698
0
  /* 5900 */ "dpsqx_s.w.ph\t\0"
699
0
  /* 5914 */ "dps.w.ph\t\0"
700
0
  /* 5924 */ "dpax.w.ph\t\0"
701
0
  /* 5935 */ "dpsx.w.ph\t\0"
702
0
  /* 5946 */ "ush\t\0"
703
0
  /* 5951 */ "dmuh\t\0"
704
0
  /* 5957 */ "synci\t\0"
705
0
  /* 5964 */ "daddi\t\0"
706
0
  /* 5971 */ "andi\t\0"
707
0
  /* 5977 */ "tgei\t\0"
708
0
  /* 5983 */ "snei\t\0"
709
0
  /* 5989 */ "tnei\t\0"
710
0
  /* 5995 */ "dahi\t\0"
711
0
  /* 6001 */ "mfhi\t\0"
712
0
  /* 6007 */ "mthi\t\0"
713
0
  /* 6013 */ ".align 2\n\tli\t\0"
714
0
  /* 6027 */ "dli\t\0"
715
0
  /* 6032 */ "cmpi\t\0"
716
0
  /* 6038 */ "seqi\t\0"
717
0
  /* 6044 */ "teqi\t\0"
718
0
  /* 6050 */ "xori\t\0"
719
0
  /* 6056 */ "dati\t\0"
720
0
  /* 6062 */ "slti\t\0"
721
0
  /* 6068 */ "tlti\t\0"
722
0
  /* 6074 */ "daui\t\0"
723
0
  /* 6080 */ "lui\t\0"
724
0
  /* 6085 */ "ginvi\t\0"
725
0
  /* 6092 */ "j\t\0"
726
0
  /* 6095 */ "break\t\0"
727
0
  /* 6102 */ "fork\t\0"
728
0
  /* 6108 */ "cvt.d.l\t\0"
729
0
  /* 6117 */ "cvt.s.l\t\0"
730
0
  /* 6126 */ "bal\t\0"
731
0
  /* 6131 */ "jal\t\0"
732
0
  /* 6136 */ "bgezal\t\0"
733
0
  /* 6144 */ "bltzal\t\0"
734
0
  /* 6152 */ "dpau.h.qbl\t\0"
735
0
  /* 6164 */ "dpsu.h.qbl\t\0"
736
0
  /* 6176 */ "muleu_s.ph.qbl\t\0"
737
0
  /* 6192 */ "preceu.ph.qbl\t\0"
738
0
  /* 6207 */ "precequ.ph.qbl\t\0"
739
0
  /* 6223 */ "ldl\t\0"
740
0
  /* 6228 */ "sdl\t\0"
741
0
  /* 6233 */ "bgel\t\0"
742
0
  /* 6239 */ "blel\t\0"
743
0
  /* 6245 */ "bnel\t\0"
744
0
  /* 6251 */ "bc1fl\t\0"
745
0
  /* 6258 */ "maq_sa.w.phl\t\0"
746
0
  /* 6272 */ "preceq.w.phl\t\0"
747
0
  /* 6286 */ "maq_s.w.phl\t\0"
748
0
  /* 6299 */ "muleq_s.w.phl\t\0"
749
0
  /* 6314 */ "hypcall\t\0"
750
0
  /* 6323 */ "syscall\t\0"
751
0
  /* 6332 */ "bgezall\t\0"
752
0
  /* 6341 */ "bltzall\t\0"
753
0
  /* 6350 */ "dsll\t\0"
754
0
  /* 6356 */ "drol\t\0"
755
0
  /* 6362 */ "cvt.s.pl\t\0"
756
0
  /* 6372 */ "beql\t\0"
757
0
  /* 6378 */ "dsrl\t\0"
758
0
  /* 6384 */ "bc1tl\t\0"
759
0
  /* 6391 */ "bgtl\t\0"
760
0
  /* 6397 */ "bltl\t\0"
761
0
  /* 6403 */ "bgeul\t\0"
762
0
  /* 6410 */ "bleul\t\0"
763
0
  /* 6417 */ "dmul\t\0"
764
0
  /* 6423 */ "bgtul\t\0"
765
0
  /* 6430 */ "bltul\t\0"
766
0
  /* 6437 */ "lwl\t\0"
767
0
  /* 6442 */ "swl\t\0"
768
0
  /* 6447 */ "bgezl\t\0"
769
0
  /* 6454 */ "blezl\t\0"
770
0
  /* 6461 */ "bgtzl\t\0"
771
0
  /* 6468 */ "bltzl\t\0"
772
0
  /* 6475 */ "drem\t\0"
773
0
  /* 6481 */ "dinsm\t\0"
774
0
  /* 6488 */ "dextm\t\0"
775
0
  /* 6495 */ "lwm\t\0"
776
0
  /* 6500 */ "swm\t\0"
777
0
  /* 6505 */ "balign\t\0"
778
0
  /* 6513 */ "dalign\t\0"
779
0
  /* 6521 */ "movn\t\0"
780
0
  /* 6527 */ "dclo\t\0"
781
0
  /* 6533 */ "mflo\t\0"
782
0
  /* 6539 */ "shilo\t\0"
783
0
  /* 6546 */ "mtlo\t\0"
784
0
  /* 6552 */ "dmulo\t\0"
785
0
  /* 6559 */ "dbitswap\t\0"
786
0
  /* 6569 */ "sdbbp\t\0"
787
0
  /* 6576 */ "extpdp\t\0"
788
0
  /* 6584 */ "movep\t\0"
789
0
  /* 6591 */ "mthlip\t\0"
790
0
  /* 6599 */ "cmp\t\0"
791
0
  /* 6604 */ "dpop\t\0"
792
0
  /* 6610 */ "addiur1sp\t\0"
793
0
  /* 6621 */ "load_ccond_dsp\t\0"
794
0
  /* 6637 */ "store_ccond_dsp\t\0"
795
0
  /* 6654 */ "rddsp\t\0"
796
0
  /* 6661 */ "wrdsp\t\0"
797
0
  /* 6668 */ "jrcaddiusp\t\0"
798
0
  /* 6680 */ "jraddiusp\t\0"
799
0
  /* 6691 */ "swsp\t\0"
800
0
  /* 6697 */ "extp\t\0"
801
0
  /* 6703 */ "dvp\t\0"
802
0
  /* 6708 */ "evp\t\0"
803
0
  /* 6713 */ "lwp\t\0"
804
0
  /* 6718 */ "swp\t\0"
805
0
  /* 6723 */ "beq\t\0"
806
0
  /* 6728 */ "seq\t\0"
807
0
  /* 6733 */ "teq\t\0"
808
0
  /* 6738 */ "dpau.h.qbr\t\0"
809
0
  /* 6750 */ "dpsu.h.qbr\t\0"
810
0
  /* 6762 */ "muleu_s.ph.qbr\t\0"
811
0
  /* 6778 */ "preceu.ph.qbr\t\0"
812
0
  /* 6793 */ "precequ.ph.qbr\t\0"
813
0
  /* 6809 */ "ldr\t\0"
814
0
  /* 6814 */ "sdr\t\0"
815
0
  /* 6819 */ "maq_sa.w.phr\t\0"
816
0
  /* 6833 */ "preceq.w.phr\t\0"
817
0
  /* 6847 */ "maq_s.w.phr\t\0"
818
0
  /* 6860 */ "muleq_s.w.phr\t\0"
819
0
  /* 6875 */ "jr\t\0"
820
0
  /* 6879 */ "jalr\t\0"
821
0
  /* 6885 */ "nor\t\0"
822
0
  /* 6890 */ "dror\t\0"
823
0
  /* 6896 */ "xor\t\0"
824
0
  /* 6901 */ "rdpgpr\t\0"
825
0
  /* 6909 */ "wrpgpr\t\0"
826
0
  /* 6917 */ "mftr\t\0"
827
0
  /* 6923 */ "drotr\t\0"
828
0
  /* 6930 */ "mttr\t\0"
829
0
  /* 6936 */ "rdhwr\t\0"
830
0
  /* 6943 */ "lwr\t\0"
831
0
  /* 6948 */ "swr\t\0"
832
0
  /* 6953 */ "mina.s\t\0"
833
0
  /* 6961 */ "maxa.s\t\0"
834
0
  /* 6969 */ "nmsub.s\t\0"
835
0
  /* 6978 */ "cvt.d.s\t\0"
836
0
  /* 6987 */ "nmadd.s\t\0"
837
0
  /* 6996 */ "c.nge.s\t\0"
838
0
  /* 7005 */ "c.le.s\t\0"
839
0
  /* 7013 */ "cmp.le.s\t\0"
840
0
  /* 7023 */ "c.ngle.s\t\0"
841
0
  /* 7033 */ "c.ole.s\t\0"
842
0
  /* 7042 */ "cmp.sle.s\t\0"
843
0
  /* 7053 */ "c.ule.s\t\0"
844
0
  /* 7062 */ "cmp.ule.s\t\0"
845
0
  /* 7073 */ "cmp.sule.s\t\0"
846
0
  /* 7085 */ "c.f.s\t\0"
847
0
  /* 7092 */ "cmp.af.s\t\0"
848
0
  /* 7102 */ "cmp.saf.s\t\0"
849
0
  /* 7113 */ "msubf.s\t\0"
850
0
  /* 7122 */ "maddf.s\t\0"
851
0
  /* 7131 */ "c.sf.s\t\0"
852
0
  /* 7139 */ "movf.s\t\0"
853
0
  /* 7147 */ "neg.s\t\0"
854
0
  /* 7154 */ "li.s\t\0"
855
0
  /* 7160 */ "trunc.l.s\t\0"
856
0
  /* 7171 */ "round.l.s\t\0"
857
0
  /* 7182 */ "ceil.l.s\t\0"
858
0
  /* 7192 */ "floor.l.s\t\0"
859
0
  /* 7203 */ "cvt.l.s\t\0"
860
0
  /* 7212 */ "sel.s\t\0"
861
0
  /* 7219 */ "c.ngl.s\t\0"
862
0
  /* 7228 */ "mul.s\t\0"
863
0
  /* 7235 */ "min.s\t\0"
864
0
  /* 7242 */ "c.un.s\t\0"
865
0
  /* 7250 */ "cmp.un.s\t\0"
866
0
  /* 7260 */ "cmp.sun.s\t\0"
867
0
  /* 7271 */ "movn.s\t\0"
868
0
  /* 7279 */ "recip.s\t\0"
869
0
  /* 7288 */ "c.eq.s\t\0"
870
0
  /* 7296 */ "cmp.eq.s\t\0"
871
0
  /* 7306 */ "c.seq.s\t\0"
872
0
  /* 7315 */ "cmp.seq.s\t\0"
873
0
  /* 7326 */ "c.ueq.s\t\0"
874
0
  /* 7335 */ "cmp.ueq.s\t\0"
875
0
  /* 7346 */ "cmp.sueq.s\t\0"
876
0
  /* 7358 */ "abs.s\t\0"
877
0
  /* 7365 */ "cvt.ps.s\t\0"
878
0
  /* 7375 */ "class.s\t\0"
879
0
  /* 7384 */ "c.ngt.s\t\0"
880
0
  /* 7393 */ "c.lt.s\t\0"
881
0
  /* 7401 */ "cmp.lt.s\t\0"
882
0
  /* 7411 */ "c.olt.s\t\0"
883
0
  /* 7420 */ "cmp.slt.s\t\0"
884
0
  /* 7431 */ "c.ult.s\t\0"
885
0
  /* 7440 */ "cmp.ult.s\t\0"
886
0
  /* 7451 */ "cmp.sult.s\t\0"
887
0
  /* 7463 */ "rint.s\t\0"
888
0
  /* 7471 */ "rsqrt.s\t\0"
889
0
  /* 7480 */ "movt.s\t\0"
890
0
  /* 7488 */ "div.s\t\0"
891
0
  /* 7495 */ "mov.s\t\0"
892
0
  /* 7502 */ "trunc.w.s\t\0"
893
0
  /* 7513 */ "round.w.s\t\0"
894
0
  /* 7524 */ "ceil.w.s\t\0"
895
0
  /* 7534 */ "floor.w.s\t\0"
896
0
  /* 7545 */ "cvt.w.s\t\0"
897
0
  /* 7554 */ "max.s\t\0"
898
0
  /* 7561 */ "selnez.s\t\0"
899
0
  /* 7571 */ "seleqz.s\t\0"
900
0
  /* 7581 */ "movz.s\t\0"
901
0
  /* 7589 */ "abs\t\0"
902
0
  /* 7594 */ "jals\t\0"
903
0
  /* 7600 */ "bgezals\t\0"
904
0
  /* 7609 */ "bltzals\t\0"
905
0
  /* 7618 */ "cins\t\0"
906
0
  /* 7624 */ "dins\t\0"
907
0
  /* 7630 */ "sub.ps\t\0"
908
0
  /* 7638 */ "add.ps\t\0"
909
0
  /* 7646 */ "pll.ps\t\0"
910
0
  /* 7654 */ "mul.ps\t\0"
911
0
  /* 7662 */ "pul.ps\t\0"
912
0
  /* 7670 */ "addr.ps\t\0"
913
0
  /* 7679 */ "mulr.ps\t\0"
914
0
  /* 7688 */ "plu.ps\t\0"
915
0
  /* 7696 */ "puu.ps\t\0"
916
0
  /* 7704 */ "cvt.pw.ps\t\0"
917
0
  /* 7715 */ "jalrs\t\0"
918
0
  /* 7722 */ "exts\t\0"
919
0
  /* 7728 */ "lwxs\t\0"
920
0
  /* 7734 */ "bc1t\t\0"
921
0
  /* 7740 */ "bgt\t\0"
922
0
  /* 7745 */ "sgt\t\0"
923
0
  /* 7750 */ "wait\t\0"
924
0
  /* 7756 */ "blt\t\0"
925
0
  /* 7761 */ "slt\t\0"
926
0
  /* 7766 */ "tlt\t\0"
927
0
  /* 7771 */ "dmult\t\0"
928
0
  /* 7778 */ "dmt\t\0"
929
0
  /* 7783 */ "emt\t\0"
930
0
  /* 7788 */ "not\t\0"
931
0
  /* 7793 */ "ginvt\t\0"
932
0
  /* 7800 */ "movt\t\0"
933
0
  /* 7806 */ "dext\t\0"
934
0
  /* 7812 */ "lbu\t\0"
935
0
  /* 7817 */ "dsubu\t\0"
936
0
  /* 7824 */ "msubu\t\0"
937
0
  /* 7831 */ "baddu\t\0"
938
0
  /* 7838 */ "daddu\t\0"
939
0
  /* 7845 */ "maddu\t\0"
940
0
  /* 7852 */ "dmodu\t\0"
941
0
  /* 7859 */ "bgeu\t\0"
942
0
  /* 7865 */ "sgeu\t\0"
943
0
  /* 7871 */ "tgeu\t\0"
944
0
  /* 7877 */ "bleu\t\0"
945
0
  /* 7883 */ "sleu\t\0"
946
0
  /* 7889 */ "ulhu\t\0"
947
0
  /* 7895 */ "dmuhu\t\0"
948
0
  /* 7902 */ "daddiu\t\0"
949
0
  /* 7910 */ "tgeiu\t\0"
950
0
  /* 7917 */ "sltiu\t\0"
951
0
  /* 7924 */ "tltiu\t\0"
952
0
  /* 7931 */ "v3mulu\t\0"
953
0
  /* 7939 */ "dmulu\t\0"
954
0
  /* 7946 */ "vmulu\t\0"
955
0
  /* 7953 */ "dremu\t\0"
956
0
  /* 7960 */ "dmulou\t\0"
957
0
  /* 7968 */ "cvt.s.pu\t\0"
958
0
  /* 7978 */ "dinsu\t\0"
959
0
  /* 7985 */ "bgtu\t\0"
960
0
  /* 7991 */ "sgtu\t\0"
961
0
  /* 7997 */ "bltu\t\0"
962
0
  /* 8003 */ "sltu\t\0"
963
0
  /* 8009 */ "tltu\t\0"
964
0
  /* 8015 */ "dmultu\t\0"
965
0
  /* 8023 */ "dextu\t\0"
966
0
  /* 8030 */ "ddivu\t\0"
967
0
  /* 8037 */ "lwu\t\0"
968
0
  /* 8042 */ "and.v\t\0"
969
0
  /* 8049 */ "move.v\t\0"
970
0
  /* 8057 */ "bsel.v\t\0"
971
0
  /* 8065 */ "nor.v\t\0"
972
0
  /* 8072 */ "xor.v\t\0"
973
0
  /* 8079 */ "bz.v\t\0"
974
0
  /* 8085 */ "bmz.v\t\0"
975
0
  /* 8092 */ "bnz.v\t\0"
976
0
  /* 8099 */ "bmnz.v\t\0"
977
0
  /* 8107 */ "dsrav\t\0"
978
0
  /* 8114 */ "bitrev\t\0"
979
0
  /* 8122 */ "ddiv\t\0"
980
0
  /* 8128 */ "dsllv\t\0"
981
0
  /* 8135 */ "dsrlv\t\0"
982
0
  /* 8142 */ "shilov\t\0"
983
0
  /* 8150 */ "extpdpv\t\0"
984
0
  /* 8159 */ "extpv\t\0"
985
0
  /* 8166 */ "drotrv\t\0"
986
0
  /* 8174 */ "insv\t\0"
987
0
  /* 8180 */ "flog2.w\t\0"
988
0
  /* 8189 */ "fexp2.w\t\0"
989
0
  /* 8198 */ "add_a.w\t\0"
990
0
  /* 8207 */ "fmin_a.w\t\0"
991
0
  /* 8217 */ "adds_a.w\t\0"
992
0
  /* 8227 */ "fmax_a.w\t\0"
993
0
  /* 8237 */ "sra.w\t\0"
994
0
  /* 8244 */ "fsub.w\t\0"
995
0
  /* 8252 */ "fmsub.w\t\0"
996
0
  /* 8261 */ "nloc.w\t\0"
997
0
  /* 8269 */ "nlzc.w\t\0"
998
0
  /* 8277 */ "cvt.d.w\t\0"
999
0
  /* 8286 */ "fadd.w\t\0"
1000
0
  /* 8294 */ "fmadd.w\t\0"
1001
0
  /* 8303 */ "sld.w\t\0"
1002
0
  /* 8310 */ "pckod.w\t\0"
1003
0
  /* 8319 */ "ilvod.w\t\0"
1004
0
  /* 8328 */ "fcle.w\t\0"
1005
0
  /* 8336 */ "fsle.w\t\0"
1006
0
  /* 8344 */ "fcule.w\t\0"
1007
0
  /* 8353 */ "fsule.w\t\0"
1008
0
  /* 8362 */ "fcne.w\t\0"
1009
0
  /* 8370 */ "fsne.w\t\0"
1010
0
  /* 8378 */ "fcune.w\t\0"
1011
0
  /* 8387 */ "fsune.w\t\0"
1012
0
  /* 8396 */ "insve.w\t\0"
1013
0
  /* 8405 */ "fcaf.w\t\0"
1014
0
  /* 8413 */ "fsaf.w\t\0"
1015
0
  /* 8421 */ "vshf.w\t\0"
1016
0
  /* 8429 */ "bneg.w\t\0"
1017
0
  /* 8437 */ "precr_sra.ph.w\t\0"
1018
0
  /* 8453 */ "precrq.ph.w\t\0"
1019
0
  /* 8466 */ "precr_sra_r.ph.w\t\0"
1020
0
  /* 8484 */ "precrq_rs.ph.w\t\0"
1021
0
  /* 8500 */ "subqh.w\t\0"
1022
0
  /* 8509 */ "addqh.w\t\0"
1023
0
  /* 8518 */ "srai.w\t\0"
1024
0
  /* 8526 */ "sldi.w\t\0"
1025
0
  /* 8534 */ "bnegi.w\t\0"
1026
0
  /* 8543 */ "slli.w\t\0"
1027
0
  /* 8551 */ "srli.w\t\0"
1028
0
  /* 8559 */ "binsli.w\t\0"
1029
0
  /* 8569 */ "ceqi.w\t\0"
1030
0
  /* 8577 */ "srari.w\t\0"
1031
0
  /* 8586 */ "bclri.w\t\0"
1032
0
  /* 8595 */ "srlri.w\t\0"
1033
0
  /* 8604 */ "binsri.w\t\0"
1034
0
  /* 8614 */ "splati.w\t\0"
1035
0
  /* 8624 */ "bseti.w\t\0"
1036
0
  /* 8633 */ "subvi.w\t\0"
1037
0
  /* 8642 */ "addvi.w\t\0"
1038
0
  /* 8651 */ "dpaq_sa.l.w\t\0"
1039
0
  /* 8664 */ "dpsq_sa.l.w\t\0"
1040
0
  /* 8677 */ "fill.w\t\0"
1041
0
  /* 8685 */ "sll.w\t\0"
1042
0
  /* 8692 */ "fexupl.w\t\0"
1043
0
  /* 8702 */ "ffql.w\t\0"
1044
0
  /* 8710 */ "srl.w\t\0"
1045
0
  /* 8717 */ "binsl.w\t\0"
1046
0
  /* 8726 */ "fmul.w\t\0"
1047
0
  /* 8734 */ "ilvl.w\t\0"
1048
0
  /* 8742 */ "fmin.w\t\0"
1049
0
  /* 8750 */ "fcun.w\t\0"
1050
0
  /* 8758 */ "fsun.w\t\0"
1051
0
  /* 8766 */ "fexdo.w\t\0"
1052
0
  /* 8775 */ "frcp.w\t\0"
1053
0
  /* 8783 */ "msub_q.w\t\0"
1054
0
  /* 8793 */ "madd_q.w\t\0"
1055
0
  /* 8803 */ "mul_q.w\t\0"
1056
0
  /* 8812 */ "msubr_q.w\t\0"
1057
0
  /* 8823 */ "maddr_q.w\t\0"
1058
0
  /* 8834 */ "mulr_q.w\t\0"
1059
0
  /* 8844 */ "fceq.w\t\0"
1060
0
  /* 8852 */ "fseq.w\t\0"
1061
0
  /* 8860 */ "fcueq.w\t\0"
1062
0
  /* 8869 */ "fsueq.w\t\0"
1063
0
  /* 8878 */ "ftq.w\t\0"
1064
0
  /* 8885 */ "shra_r.w\t\0"
1065
0
  /* 8895 */ "subqh_r.w\t\0"
1066
0
  /* 8906 */ "addqh_r.w\t\0"
1067
0
  /* 8917 */ "extr_r.w\t\0"
1068
0
  /* 8927 */ "shrav_r.w\t\0"
1069
0
  /* 8938 */ "extrv_r.w\t\0"
1070
0
  /* 8949 */ "srar.w\t\0"
1071
0
  /* 8957 */ "bclr.w\t\0"
1072
0
  /* 8965 */ "srlr.w\t\0"
1073
0
  /* 8973 */ "fcor.w\t\0"
1074
0
  /* 8981 */ "fsor.w\t\0"
1075
0
  /* 8989 */ "fexupr.w\t\0"
1076
0
  /* 8999 */ "ffqr.w\t\0"
1077
0
  /* 9007 */ "binsr.w\t\0"
1078
0
  /* 9016 */ "extr.w\t\0"
1079
0
  /* 9024 */ "ilvr.w\t\0"
1080
0
  /* 9032 */ "cvt.s.w\t\0"
1081
0
  /* 9041 */ "asub_s.w\t\0"
1082
0
  /* 9051 */ "hsub_s.w\t\0"
1083
0
  /* 9061 */ "dpsub_s.w\t\0"
1084
0
  /* 9072 */ "ftrunc_s.w\t\0"
1085
0
  /* 9084 */ "hadd_s.w\t\0"
1086
0
  /* 9094 */ "dpadd_s.w\t\0"
1087
0
  /* 9105 */ "mod_s.w\t\0"
1088
0
  /* 9114 */ "cle_s.w\t\0"
1089
0
  /* 9123 */ "ave_s.w\t\0"
1090
0
  /* 9132 */ "clei_s.w\t\0"
1091
0
  /* 9142 */ "mini_s.w\t\0"
1092
0
  /* 9152 */ "clti_s.w\t\0"
1093
0
  /* 9162 */ "maxi_s.w\t\0"
1094
0
  /* 9172 */ "shll_s.w\t\0"
1095
0
  /* 9182 */ "min_s.w\t\0"
1096
0
  /* 9191 */ "dotp_s.w\t\0"
1097
0
  /* 9201 */ "subq_s.w\t\0"
1098
0
  /* 9211 */ "addq_s.w\t\0"
1099
0
  /* 9221 */ "mulq_s.w\t\0"
1100
0
  /* 9231 */ "absq_s.w\t\0"
1101
0
  /* 9241 */ "aver_s.w\t\0"
1102
0
  /* 9251 */ "subs_s.w\t\0"
1103
0
  /* 9261 */ "adds_s.w\t\0"
1104
0
  /* 9271 */ "sat_s.w\t\0"
1105
0
  /* 9280 */ "clt_s.w\t\0"
1106
0
  /* 9289 */ "ffint_s.w\t\0"
1107
0
  /* 9300 */ "ftint_s.w\t\0"
1108
0
  /* 9311 */ "subsuu_s.w\t\0"
1109
0
  /* 9323 */ "div_s.w\t\0"
1110
0
  /* 9332 */ "shllv_s.w\t\0"
1111
0
  /* 9343 */ "max_s.w\t\0"
1112
0
  /* 9352 */ "copy_s.w\t\0"
1113
0
  /* 9362 */ "mulq_rs.w\t\0"
1114
0
  /* 9373 */ "extr_rs.w\t\0"
1115
0
  /* 9384 */ "extrv_rs.w\t\0"
1116
0
  /* 9396 */ "fclass.w\t\0"
1117
0
  /* 9406 */ "splat.w\t\0"
1118
0
  /* 9415 */ "bset.w\t\0"
1119
0
  /* 9423 */ "fclt.w\t\0"
1120
0
  /* 9431 */ "fslt.w\t\0"
1121
0
  /* 9439 */ "fcult.w\t\0"
1122
0
  /* 9448 */ "fsult.w\t\0"
1123
0
  /* 9457 */ "pcnt.w\t\0"
1124
0
  /* 9465 */ "frint.w\t\0"
1125
0
  /* 9474 */ "insert.w\t\0"
1126
0
  /* 9484 */ "fsqrt.w\t\0"
1127
0
  /* 9493 */ "frsqrt.w\t\0"
1128
0
  /* 9503 */ "st.w\t\0"
1129
0
  /* 9509 */ "asub_u.w\t\0"
1130
0
  /* 9519 */ "hsub_u.w\t\0"
1131
0
  /* 9529 */ "dpsub_u.w\t\0"
1132
0
  /* 9540 */ "ftrunc_u.w\t\0"
1133
0
  /* 9552 */ "hadd_u.w\t\0"
1134
0
  /* 9562 */ "dpadd_u.w\t\0"
1135
0
  /* 9573 */ "mod_u.w\t\0"
1136
0
  /* 9582 */ "cle_u.w\t\0"
1137
0
  /* 9591 */ "ave_u.w\t\0"
1138
0
  /* 9600 */ "clei_u.w\t\0"
1139
0
  /* 9610 */ "mini_u.w\t\0"
1140
0
  /* 9620 */ "clti_u.w\t\0"
1141
0
  /* 9630 */ "maxi_u.w\t\0"
1142
0
  /* 9640 */ "min_u.w\t\0"
1143
0
  /* 9649 */ "dotp_u.w\t\0"
1144
0
  /* 9659 */ "aver_u.w\t\0"
1145
0
  /* 9669 */ "subs_u.w\t\0"
1146
0
  /* 9679 */ "adds_u.w\t\0"
1147
0
  /* 9689 */ "subsus_u.w\t\0"
1148
0
  /* 9701 */ "sat_u.w\t\0"
1149
0
  /* 9710 */ "clt_u.w\t\0"
1150
0
  /* 9719 */ "ffint_u.w\t\0"
1151
0
  /* 9730 */ "ftint_u.w\t\0"
1152
0
  /* 9741 */ "div_u.w\t\0"
1153
0
  /* 9750 */ "max_u.w\t\0"
1154
0
  /* 9759 */ "copy_u.w\t\0"
1155
0
  /* 9769 */ "msubv.w\t\0"
1156
0
  /* 9778 */ "maddv.w\t\0"
1157
0
  /* 9787 */ "pckev.w\t\0"
1158
0
  /* 9796 */ "ilvev.w\t\0"
1159
0
  /* 9805 */ "fdiv.w\t\0"
1160
0
  /* 9813 */ "mulv.w\t\0"
1161
0
  /* 9821 */ "extrv.w\t\0"
1162
0
  /* 9830 */ "fmax.w\t\0"
1163
0
  /* 9838 */ "bz.w\t\0"
1164
0
  /* 9844 */ "bnz.w\t\0"
1165
0
  /* 9851 */ "crc32w\t\0"
1166
0
  /* 9859 */ "crc32cw\t\0"
1167
0
  /* 9868 */ "ulw\t\0"
1168
0
  /* 9873 */ "cvt.ps.pw\t\0"
1169
0
  /* 9884 */ "usw\t\0"
1170
0
  /* 9889 */ "prefx\t\0"
1171
0
  /* 9896 */ "lhx\t\0"
1172
0
  /* 9901 */ "jalx\t\0"
1173
0
  /* 9907 */ "lbux\t\0"
1174
0
  /* 9913 */ "lwx\t\0"
1175
0
  /* 9918 */ "bgez\t\0"
1176
0
  /* 9924 */ "blez\t\0"
1177
0
  /* 9930 */ "bnez\t\0"
1178
0
  /* 9936 */ "selnez\t\0"
1179
0
  /* 9944 */ "btnez\t\0"
1180
0
  /* 9951 */ "dclz\t\0"
1181
0
  /* 9957 */ "beqz\t\0"
1182
0
  /* 9963 */ "seleqz\t\0"
1183
0
  /* 9971 */ "bteqz\t\0"
1184
0
  /* 9978 */ "bgtz\t\0"
1185
0
  /* 9984 */ "bltz\t\0"
1186
0
  /* 9990 */ "movz\t\0"
1187
0
  /* 9996 */ "seb\t \0"
1188
0
  /* 10002 */ "seh\t \0"
1189
0
  /* 10008 */ "ddivu\t$zero, \0"
1190
0
  /* 10022 */ "ddiv\t$zero, \0"
1191
0
  /* 10035 */ "addiu\t$sp, \0"
1192
0
  /* 10047 */ "mftc0 \0"
1193
0
  /* 10054 */ "mttc0 \0"
1194
0
  /* 10061 */ "mfthc1 \0"
1195
0
  /* 10069 */ "mtthc1 \0"
1196
0
  /* 10077 */ "cftc1 \0"
1197
0
  /* 10084 */ "mftc1 \0"
1198
0
  /* 10091 */ "cttc1 \0"
1199
0
  /* 10098 */ "mttc1 \0"
1200
0
  /* 10105 */ "sync \0"
1201
0
  /* 10111 */ "ld \0"
1202
0
  /* 10115 */ "\t.word \0"
1203
0
  /* 10123 */ "sd \0"
1204
0
  /* 10127 */ "sne \0"
1205
0
  /* 10132 */ "mfthi \0"
1206
0
  /* 10139 */ "mtthi \0"
1207
0
  /* 10146 */ "mftlo \0"
1208
0
  /* 10153 */ "mttlo \0"
1209
0
  /* 10160 */ "mftdsp \0"
1210
0
  /* 10168 */ "mttdsp \0"
1211
0
  /* 10176 */ "seq \0"
1212
0
  /* 10181 */ "mftgpr \0"
1213
0
  /* 10189 */ "mttgpr \0"
1214
0
  /* 10197 */ "dext \0"
1215
0
  /* 10203 */ "mftacx \0"
1216
0
  /* 10211 */ "mttacx \0"
1217
0
  /* 10219 */ "bc1nez \0"
1218
0
  /* 10227 */ "bc2nez \0"
1219
0
  /* 10235 */ "bc1eqz \0"
1220
0
  /* 10243 */ "bc2eqz \0"
1221
0
  /* 10251 */ "# XRay Function Patchable RET.\0"
1222
0
  /* 10282 */ "c.\0"
1223
0
  /* 10285 */ "# XRay Typed Event Log.\0"
1224
0
  /* 10309 */ "# XRay Custom Event Log.\0"
1225
0
  /* 10334 */ "# XRay Function Enter.\0"
1226
0
  /* 10357 */ "# XRay Tail Call Exit.\0"
1227
0
  /* 10380 */ "# XRay Function Exit.\0"
1228
0
  /* 10402 */ "break 0\0"
1229
0
  /* 10410 */ "LIFETIME_END\0"
1230
0
  /* 10423 */ "PSEUDO_PROBE\0"
1231
0
  /* 10436 */ "BUNDLE\0"
1232
0
  /* 10443 */ "DBG_VALUE\0"
1233
0
  /* 10453 */ "DBG_INSTR_REF\0"
1234
0
  /* 10467 */ "DBG_PHI\0"
1235
0
  /* 10475 */ "DBG_LABEL\0"
1236
0
  /* 10485 */ "LIFETIME_START\0"
1237
0
  /* 10500 */ "DBG_VALUE_LIST\0"
1238
0
  /* 10515 */ "jrc\t$ra\0"
1239
0
  /* 10523 */ "jr\t$ra\0"
1240
0
  /* 10530 */ "ehb\0"
1241
0
  /* 10534 */ "eretnc\0"
1242
0
  /* 10541 */ "pause\0"
1243
0
  /* 10547 */ "tlbinvf\0"
1244
0
  /* 10555 */ "tlbginvf\0"
1245
0
  /* 10564 */ "tlbwi\0"
1246
0
  /* 10570 */ "tlbgwi\0"
1247
0
  /* 10577 */ "# FEntry call\0"
1248
0
  /* 10591 */ "foo\0"
1249
0
  /* 10595 */ "tlbp\0"
1250
0
  /* 10600 */ "tlbgp\0"
1251
0
  /* 10606 */ "ssnop\0"
1252
0
  /* 10612 */ "tlbr\0"
1253
0
  /* 10617 */ "tlbgr\0"
1254
0
  /* 10623 */ "tlbwr\0"
1255
0
  /* 10629 */ "tlbgwr\0"
1256
0
  /* 10636 */ "deret\0"
1257
0
  /* 10642 */ "wait\0"
1258
0
  /* 10647 */ "tlbinv\0"
1259
0
  /* 10654 */ "tlbginv\0"
1260
0
};
1261
0
#ifdef __GNUC__
1262
0
#pragma GCC diagnostic pop
1263
0
#endif
1264
1265
0
  static const uint32_t OpInfo0[] = {
1266
0
    0U, // PHI
1267
0
    0U, // INLINEASM
1268
0
    0U, // INLINEASM_BR
1269
0
    0U, // CFI_INSTRUCTION
1270
0
    0U, // EH_LABEL
1271
0
    0U, // GC_LABEL
1272
0
    0U, // ANNOTATION_LABEL
1273
0
    0U, // KILL
1274
0
    0U, // EXTRACT_SUBREG
1275
0
    0U, // INSERT_SUBREG
1276
0
    0U, // IMPLICIT_DEF
1277
0
    0U, // SUBREG_TO_REG
1278
0
    0U, // COPY_TO_REGCLASS
1279
0
    10444U, // DBG_VALUE
1280
0
    10501U, // DBG_VALUE_LIST
1281
0
    10454U, // DBG_INSTR_REF
1282
0
    10468U, // DBG_PHI
1283
0
    10476U, // DBG_LABEL
1284
0
    0U, // REG_SEQUENCE
1285
0
    0U, // COPY
1286
0
    10437U, // BUNDLE
1287
0
    10486U, // LIFETIME_START
1288
0
    10411U, // LIFETIME_END
1289
0
    10424U, // PSEUDO_PROBE
1290
0
    0U, // ARITH_FENCE
1291
0
    0U, // STACKMAP
1292
0
    10578U, // FENTRY_CALL
1293
0
    0U, // PATCHPOINT
1294
0
    0U, // LOAD_STACK_GUARD
1295
0
    0U, // PREALLOCATED_SETUP
1296
0
    0U, // PREALLOCATED_ARG
1297
0
    0U, // STATEPOINT
1298
0
    0U, // LOCAL_ESCAPE
1299
0
    0U, // FAULTING_OP
1300
0
    0U, // PATCHABLE_OP
1301
0
    10335U, // PATCHABLE_FUNCTION_ENTER
1302
0
    10252U, // PATCHABLE_RET
1303
0
    10381U, // PATCHABLE_FUNCTION_EXIT
1304
0
    10358U, // PATCHABLE_TAIL_CALL
1305
0
    10310U, // PATCHABLE_EVENT_CALL
1306
0
    10286U, // PATCHABLE_TYPED_EVENT_CALL
1307
0
    0U, // ICALL_BRANCH_FUNNEL
1308
0
    0U, // MEMBARRIER
1309
0
    0U, // JUMP_TABLE_DEBUG_INFO
1310
0
    0U, // G_ASSERT_SEXT
1311
0
    0U, // G_ASSERT_ZEXT
1312
0
    0U, // G_ASSERT_ALIGN
1313
0
    0U, // G_ADD
1314
0
    0U, // G_SUB
1315
0
    0U, // G_MUL
1316
0
    0U, // G_SDIV
1317
0
    0U, // G_UDIV
1318
0
    0U, // G_SREM
1319
0
    0U, // G_UREM
1320
0
    0U, // G_SDIVREM
1321
0
    0U, // G_UDIVREM
1322
0
    0U, // G_AND
1323
0
    0U, // G_OR
1324
0
    0U, // G_XOR
1325
0
    0U, // G_IMPLICIT_DEF
1326
0
    0U, // G_PHI
1327
0
    0U, // G_FRAME_INDEX
1328
0
    0U, // G_GLOBAL_VALUE
1329
0
    0U, // G_CONSTANT_POOL
1330
0
    0U, // G_EXTRACT
1331
0
    0U, // G_UNMERGE_VALUES
1332
0
    0U, // G_INSERT
1333
0
    0U, // G_MERGE_VALUES
1334
0
    0U, // G_BUILD_VECTOR
1335
0
    0U, // G_BUILD_VECTOR_TRUNC
1336
0
    0U, // G_CONCAT_VECTORS
1337
0
    0U, // G_PTRTOINT
1338
0
    0U, // G_INTTOPTR
1339
0
    0U, // G_BITCAST
1340
0
    0U, // G_FREEZE
1341
0
    0U, // G_CONSTANT_FOLD_BARRIER
1342
0
    0U, // G_INTRINSIC_FPTRUNC_ROUND
1343
0
    0U, // G_INTRINSIC_TRUNC
1344
0
    0U, // G_INTRINSIC_ROUND
1345
0
    0U, // G_INTRINSIC_LRINT
1346
0
    0U, // G_INTRINSIC_ROUNDEVEN
1347
0
    0U, // G_READCYCLECOUNTER
1348
0
    0U, // G_LOAD
1349
0
    0U, // G_SEXTLOAD
1350
0
    0U, // G_ZEXTLOAD
1351
0
    0U, // G_INDEXED_LOAD
1352
0
    0U, // G_INDEXED_SEXTLOAD
1353
0
    0U, // G_INDEXED_ZEXTLOAD
1354
0
    0U, // G_STORE
1355
0
    0U, // G_INDEXED_STORE
1356
0
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
1357
0
    0U, // G_ATOMIC_CMPXCHG
1358
0
    0U, // G_ATOMICRMW_XCHG
1359
0
    0U, // G_ATOMICRMW_ADD
1360
0
    0U, // G_ATOMICRMW_SUB
1361
0
    0U, // G_ATOMICRMW_AND
1362
0
    0U, // G_ATOMICRMW_NAND
1363
0
    0U, // G_ATOMICRMW_OR
1364
0
    0U, // G_ATOMICRMW_XOR
1365
0
    0U, // G_ATOMICRMW_MAX
1366
0
    0U, // G_ATOMICRMW_MIN
1367
0
    0U, // G_ATOMICRMW_UMAX
1368
0
    0U, // G_ATOMICRMW_UMIN
1369
0
    0U, // G_ATOMICRMW_FADD
1370
0
    0U, // G_ATOMICRMW_FSUB
1371
0
    0U, // G_ATOMICRMW_FMAX
1372
0
    0U, // G_ATOMICRMW_FMIN
1373
0
    0U, // G_ATOMICRMW_UINC_WRAP
1374
0
    0U, // G_ATOMICRMW_UDEC_WRAP
1375
0
    0U, // G_FENCE
1376
0
    0U, // G_PREFETCH
1377
0
    0U, // G_BRCOND
1378
0
    0U, // G_BRINDIRECT
1379
0
    0U, // G_INVOKE_REGION_START
1380
0
    0U, // G_INTRINSIC
1381
0
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
1382
0
    0U, // G_INTRINSIC_CONVERGENT
1383
0
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1384
0
    0U, // G_ANYEXT
1385
0
    0U, // G_TRUNC
1386
0
    0U, // G_CONSTANT
1387
0
    0U, // G_FCONSTANT
1388
0
    0U, // G_VASTART
1389
0
    0U, // G_VAARG
1390
0
    0U, // G_SEXT
1391
0
    0U, // G_SEXT_INREG
1392
0
    0U, // G_ZEXT
1393
0
    0U, // G_SHL
1394
0
    0U, // G_LSHR
1395
0
    0U, // G_ASHR
1396
0
    0U, // G_FSHL
1397
0
    0U, // G_FSHR
1398
0
    0U, // G_ROTR
1399
0
    0U, // G_ROTL
1400
0
    0U, // G_ICMP
1401
0
    0U, // G_FCMP
1402
0
    0U, // G_SELECT
1403
0
    0U, // G_UADDO
1404
0
    0U, // G_UADDE
1405
0
    0U, // G_USUBO
1406
0
    0U, // G_USUBE
1407
0
    0U, // G_SADDO
1408
0
    0U, // G_SADDE
1409
0
    0U, // G_SSUBO
1410
0
    0U, // G_SSUBE
1411
0
    0U, // G_UMULO
1412
0
    0U, // G_SMULO
1413
0
    0U, // G_UMULH
1414
0
    0U, // G_SMULH
1415
0
    0U, // G_UADDSAT
1416
0
    0U, // G_SADDSAT
1417
0
    0U, // G_USUBSAT
1418
0
    0U, // G_SSUBSAT
1419
0
    0U, // G_USHLSAT
1420
0
    0U, // G_SSHLSAT
1421
0
    0U, // G_SMULFIX
1422
0
    0U, // G_UMULFIX
1423
0
    0U, // G_SMULFIXSAT
1424
0
    0U, // G_UMULFIXSAT
1425
0
    0U, // G_SDIVFIX
1426
0
    0U, // G_UDIVFIX
1427
0
    0U, // G_SDIVFIXSAT
1428
0
    0U, // G_UDIVFIXSAT
1429
0
    0U, // G_FADD
1430
0
    0U, // G_FSUB
1431
0
    0U, // G_FMUL
1432
0
    0U, // G_FMA
1433
0
    0U, // G_FMAD
1434
0
    0U, // G_FDIV
1435
0
    0U, // G_FREM
1436
0
    0U, // G_FPOW
1437
0
    0U, // G_FPOWI
1438
0
    0U, // G_FEXP
1439
0
    0U, // G_FEXP2
1440
0
    0U, // G_FEXP10
1441
0
    0U, // G_FLOG
1442
0
    0U, // G_FLOG2
1443
0
    0U, // G_FLOG10
1444
0
    0U, // G_FLDEXP
1445
0
    0U, // G_FFREXP
1446
0
    0U, // G_FNEG
1447
0
    0U, // G_FPEXT
1448
0
    0U, // G_FPTRUNC
1449
0
    0U, // G_FPTOSI
1450
0
    0U, // G_FPTOUI
1451
0
    0U, // G_SITOFP
1452
0
    0U, // G_UITOFP
1453
0
    0U, // G_FABS
1454
0
    0U, // G_FCOPYSIGN
1455
0
    0U, // G_IS_FPCLASS
1456
0
    0U, // G_FCANONICALIZE
1457
0
    0U, // G_FMINNUM
1458
0
    0U, // G_FMAXNUM
1459
0
    0U, // G_FMINNUM_IEEE
1460
0
    0U, // G_FMAXNUM_IEEE
1461
0
    0U, // G_FMINIMUM
1462
0
    0U, // G_FMAXIMUM
1463
0
    0U, // G_GET_FPENV
1464
0
    0U, // G_SET_FPENV
1465
0
    0U, // G_RESET_FPENV
1466
0
    0U, // G_GET_FPMODE
1467
0
    0U, // G_SET_FPMODE
1468
0
    0U, // G_RESET_FPMODE
1469
0
    0U, // G_PTR_ADD
1470
0
    0U, // G_PTRMASK
1471
0
    0U, // G_SMIN
1472
0
    0U, // G_SMAX
1473
0
    0U, // G_UMIN
1474
0
    0U, // G_UMAX
1475
0
    0U, // G_ABS
1476
0
    0U, // G_LROUND
1477
0
    0U, // G_LLROUND
1478
0
    0U, // G_BR
1479
0
    0U, // G_BRJT
1480
0
    0U, // G_INSERT_VECTOR_ELT
1481
0
    0U, // G_EXTRACT_VECTOR_ELT
1482
0
    0U, // G_SHUFFLE_VECTOR
1483
0
    0U, // G_CTTZ
1484
0
    0U, // G_CTTZ_ZERO_UNDEF
1485
0
    0U, // G_CTLZ
1486
0
    0U, // G_CTLZ_ZERO_UNDEF
1487
0
    0U, // G_CTPOP
1488
0
    0U, // G_BSWAP
1489
0
    0U, // G_BITREVERSE
1490
0
    0U, // G_FCEIL
1491
0
    0U, // G_FCOS
1492
0
    0U, // G_FSIN
1493
0
    0U, // G_FSQRT
1494
0
    0U, // G_FFLOOR
1495
0
    0U, // G_FRINT
1496
0
    0U, // G_FNEARBYINT
1497
0
    0U, // G_ADDRSPACE_CAST
1498
0
    0U, // G_BLOCK_ADDR
1499
0
    0U, // G_JUMP_TABLE
1500
0
    0U, // G_DYN_STACKALLOC
1501
0
    0U, // G_STACKSAVE
1502
0
    0U, // G_STACKRESTORE
1503
0
    0U, // G_STRICT_FADD
1504
0
    0U, // G_STRICT_FSUB
1505
0
    0U, // G_STRICT_FMUL
1506
0
    0U, // G_STRICT_FDIV
1507
0
    0U, // G_STRICT_FREM
1508
0
    0U, // G_STRICT_FMA
1509
0
    0U, // G_STRICT_FSQRT
1510
0
    0U, // G_STRICT_FLDEXP
1511
0
    0U, // G_READ_REGISTER
1512
0
    0U, // G_WRITE_REGISTER
1513
0
    0U, // G_MEMCPY
1514
0
    0U, // G_MEMCPY_INLINE
1515
0
    0U, // G_MEMMOVE
1516
0
    0U, // G_MEMSET
1517
0
    0U, // G_BZERO
1518
0
    0U, // G_VECREDUCE_SEQ_FADD
1519
0
    0U, // G_VECREDUCE_SEQ_FMUL
1520
0
    0U, // G_VECREDUCE_FADD
1521
0
    0U, // G_VECREDUCE_FMUL
1522
0
    0U, // G_VECREDUCE_FMAX
1523
0
    0U, // G_VECREDUCE_FMIN
1524
0
    0U, // G_VECREDUCE_FMAXIMUM
1525
0
    0U, // G_VECREDUCE_FMINIMUM
1526
0
    0U, // G_VECREDUCE_ADD
1527
0
    0U, // G_VECREDUCE_MUL
1528
0
    0U, // G_VECREDUCE_AND
1529
0
    0U, // G_VECREDUCE_OR
1530
0
    0U, // G_VECREDUCE_XOR
1531
0
    0U, // G_VECREDUCE_SMAX
1532
0
    0U, // G_VECREDUCE_SMIN
1533
0
    0U, // G_VECREDUCE_UMAX
1534
0
    0U, // G_VECREDUCE_UMIN
1535
0
    0U, // G_SBFX
1536
0
    0U, // G_UBFX
1537
0
    23974U, // ABSMacro
1538
0
    0U, // ADJCALLSTACKDOWN
1539
0
    0U, // ADJCALLSTACKUP
1540
0
    0U, // AND_V_D_PSEUDO
1541
0
    0U, // AND_V_H_PSEUDO
1542
0
    0U, // AND_V_W_PSEUDO
1543
0
    0U, // ATOMIC_CMP_SWAP_I16
1544
0
    0U, // ATOMIC_CMP_SWAP_I16_POSTRA
1545
0
    0U, // ATOMIC_CMP_SWAP_I32
1546
0
    0U, // ATOMIC_CMP_SWAP_I32_POSTRA
1547
0
    0U, // ATOMIC_CMP_SWAP_I64
1548
0
    0U, // ATOMIC_CMP_SWAP_I64_POSTRA
1549
0
    0U, // ATOMIC_CMP_SWAP_I8
1550
0
    0U, // ATOMIC_CMP_SWAP_I8_POSTRA
1551
0
    0U, // ATOMIC_LOAD_ADD_I16
1552
0
    0U, // ATOMIC_LOAD_ADD_I16_POSTRA
1553
0
    0U, // ATOMIC_LOAD_ADD_I32
1554
0
    0U, // ATOMIC_LOAD_ADD_I32_POSTRA
1555
0
    0U, // ATOMIC_LOAD_ADD_I64
1556
0
    0U, // ATOMIC_LOAD_ADD_I64_POSTRA
1557
0
    0U, // ATOMIC_LOAD_ADD_I8
1558
0
    0U, // ATOMIC_LOAD_ADD_I8_POSTRA
1559
0
    0U, // ATOMIC_LOAD_AND_I16
1560
0
    0U, // ATOMIC_LOAD_AND_I16_POSTRA
1561
0
    0U, // ATOMIC_LOAD_AND_I32
1562
0
    0U, // ATOMIC_LOAD_AND_I32_POSTRA
1563
0
    0U, // ATOMIC_LOAD_AND_I64
1564
0
    0U, // ATOMIC_LOAD_AND_I64_POSTRA
1565
0
    0U, // ATOMIC_LOAD_AND_I8
1566
0
    0U, // ATOMIC_LOAD_AND_I8_POSTRA
1567
0
    0U, // ATOMIC_LOAD_MAX_I16
1568
0
    0U, // ATOMIC_LOAD_MAX_I16_POSTRA
1569
0
    0U, // ATOMIC_LOAD_MAX_I32
1570
0
    0U, // ATOMIC_LOAD_MAX_I32_POSTRA
1571
0
    0U, // ATOMIC_LOAD_MAX_I64
1572
0
    0U, // ATOMIC_LOAD_MAX_I64_POSTRA
1573
0
    0U, // ATOMIC_LOAD_MAX_I8
1574
0
    0U, // ATOMIC_LOAD_MAX_I8_POSTRA
1575
0
    0U, // ATOMIC_LOAD_MIN_I16
1576
0
    0U, // ATOMIC_LOAD_MIN_I16_POSTRA
1577
0
    0U, // ATOMIC_LOAD_MIN_I32
1578
0
    0U, // ATOMIC_LOAD_MIN_I32_POSTRA
1579
0
    0U, // ATOMIC_LOAD_MIN_I64
1580
0
    0U, // ATOMIC_LOAD_MIN_I64_POSTRA
1581
0
    0U, // ATOMIC_LOAD_MIN_I8
1582
0
    0U, // ATOMIC_LOAD_MIN_I8_POSTRA
1583
0
    0U, // ATOMIC_LOAD_NAND_I16
1584
0
    0U, // ATOMIC_LOAD_NAND_I16_POSTRA
1585
0
    0U, // ATOMIC_LOAD_NAND_I32
1586
0
    0U, // ATOMIC_LOAD_NAND_I32_POSTRA
1587
0
    0U, // ATOMIC_LOAD_NAND_I64
1588
0
    0U, // ATOMIC_LOAD_NAND_I64_POSTRA
1589
0
    0U, // ATOMIC_LOAD_NAND_I8
1590
0
    0U, // ATOMIC_LOAD_NAND_I8_POSTRA
1591
0
    0U, // ATOMIC_LOAD_OR_I16
1592
0
    0U, // ATOMIC_LOAD_OR_I16_POSTRA
1593
0
    0U, // ATOMIC_LOAD_OR_I32
1594
0
    0U, // ATOMIC_LOAD_OR_I32_POSTRA
1595
0
    0U, // ATOMIC_LOAD_OR_I64
1596
0
    0U, // ATOMIC_LOAD_OR_I64_POSTRA
1597
0
    0U, // ATOMIC_LOAD_OR_I8
1598
0
    0U, // ATOMIC_LOAD_OR_I8_POSTRA
1599
0
    0U, // ATOMIC_LOAD_SUB_I16
1600
0
    0U, // ATOMIC_LOAD_SUB_I16_POSTRA
1601
0
    0U, // ATOMIC_LOAD_SUB_I32
1602
0
    0U, // ATOMIC_LOAD_SUB_I32_POSTRA
1603
0
    0U, // ATOMIC_LOAD_SUB_I64
1604
0
    0U, // ATOMIC_LOAD_SUB_I64_POSTRA
1605
0
    0U, // ATOMIC_LOAD_SUB_I8
1606
0
    0U, // ATOMIC_LOAD_SUB_I8_POSTRA
1607
0
    0U, // ATOMIC_LOAD_UMAX_I16
1608
0
    0U, // ATOMIC_LOAD_UMAX_I16_POSTRA
1609
0
    0U, // ATOMIC_LOAD_UMAX_I32
1610
0
    0U, // ATOMIC_LOAD_UMAX_I32_POSTRA
1611
0
    0U, // ATOMIC_LOAD_UMAX_I64
1612
0
    0U, // ATOMIC_LOAD_UMAX_I64_POSTRA
1613
0
    0U, // ATOMIC_LOAD_UMAX_I8
1614
0
    0U, // ATOMIC_LOAD_UMAX_I8_POSTRA
1615
0
    0U, // ATOMIC_LOAD_UMIN_I16
1616
0
    0U, // ATOMIC_LOAD_UMIN_I16_POSTRA
1617
0
    0U, // ATOMIC_LOAD_UMIN_I32
1618
0
    0U, // ATOMIC_LOAD_UMIN_I32_POSTRA
1619
0
    0U, // ATOMIC_LOAD_UMIN_I64
1620
0
    0U, // ATOMIC_LOAD_UMIN_I64_POSTRA
1621
0
    0U, // ATOMIC_LOAD_UMIN_I8
1622
0
    0U, // ATOMIC_LOAD_UMIN_I8_POSTRA
1623
0
    0U, // ATOMIC_LOAD_XOR_I16
1624
0
    0U, // ATOMIC_LOAD_XOR_I16_POSTRA
1625
0
    0U, // ATOMIC_LOAD_XOR_I32
1626
0
    0U, // ATOMIC_LOAD_XOR_I32_POSTRA
1627
0
    0U, // ATOMIC_LOAD_XOR_I64
1628
0
    0U, // ATOMIC_LOAD_XOR_I64_POSTRA
1629
0
    0U, // ATOMIC_LOAD_XOR_I8
1630
0
    0U, // ATOMIC_LOAD_XOR_I8_POSTRA
1631
0
    0U, // ATOMIC_SWAP_I16
1632
0
    0U, // ATOMIC_SWAP_I16_POSTRA
1633
0
    0U, // ATOMIC_SWAP_I32
1634
0
    0U, // ATOMIC_SWAP_I32_POSTRA
1635
0
    0U, // ATOMIC_SWAP_I64
1636
0
    0U, // ATOMIC_SWAP_I64_POSTRA
1637
0
    0U, // ATOMIC_SWAP_I8
1638
0
    0U, // ATOMIC_SWAP_I8_POSTRA
1639
0
    0U, // B
1640
0
    0U, // BAL_BR
1641
0
    0U, // BAL_BR_MM
1642
0
    536893669U, // BEQLImmMacro
1643
0
    536891521U, // BGE
1644
0
    536891521U, // BGEImmMacro
1645
0
    536893530U, // BGEL
1646
0
    536893530U, // BGELImmMacro
1647
0
    536895156U, // BGEU
1648
0
    536895156U, // BGEUImmMacro
1649
0
    536893700U, // BGEUL
1650
0
    536893700U, // BGEULImmMacro
1651
0
    536895037U, // BGT
1652
0
    536895037U, // BGTImmMacro
1653
0
    536893688U, // BGTL
1654
0
    536893688U, // BGTLImmMacro
1655
0
    536895282U, // BGTU
1656
0
    536895282U, // BGTUImmMacro
1657
0
    536893720U, // BGTUL
1658
0
    536893720U, // BGTULImmMacro
1659
0
    536891561U, // BLE
1660
0
    536891561U, // BLEImmMacro
1661
0
    536893536U, // BLEL
1662
0
    536893536U, // BLELImmMacro
1663
0
    536895174U, // BLEU
1664
0
    536895174U, // BLEUImmMacro
1665
0
    536893707U, // BLEUL
1666
0
    536893707U, // BLEULImmMacro
1667
0
    536895053U, // BLT
1668
0
    536895053U, // BLTImmMacro
1669
0
    536893694U, // BLTL
1670
0
    536893694U, // BLTLImmMacro
1671
0
    536895294U, // BLTU
1672
0
    536895294U, // BLTUImmMacro
1673
0
    536893727U, // BLTUL
1674
0
    536893727U, // BLTULImmMacro
1675
0
    536893542U, // BNELImmMacro
1676
0
    0U, // BPOSGE32_PSEUDO
1677
0
    0U, // BSEL_D_PSEUDO
1678
0
    0U, // BSEL_FD_PSEUDO
1679
0
    0U, // BSEL_FW_PSEUDO
1680
0
    0U, // BSEL_H_PSEUDO
1681
0
    0U, // BSEL_W_PSEUDO
1682
0
    0U, // B_MM
1683
0
    557807U,  // B_MMR6_Pseudo
1684
0
    557807U,  // B_MM_Pseudo
1685
0
    536894020U, // BeqImm
1686
0
    536891588U, // BneImm
1687
0
    1073764808U,  // BteqzT8CmpX16
1688
0
    1073764241U,  // BteqzT8CmpiX16
1689
0
    1073765970U,  // BteqzT8SltX16
1690
0
    1073764271U,  // BteqzT8SltiX16
1691
0
    1073766126U,  // BteqzT8SltiuX16
1692
0
    1073766212U,  // BteqzT8SltuX16
1693
0
    1610635720U,  // BtnezT8CmpX16
1694
0
    1610635153U,  // BtnezT8CmpiX16
1695
0
    1610636882U,  // BtnezT8SltX16
1696
0
    1610635183U,  // BtnezT8SltiX16
1697
0
    1610637038U,  // BtnezT8SltiuX16
1698
0
    1610637124U,  // BtnezT8SltuX16
1699
0
    0U, // BuildPairF64
1700
0
    0U, // BuildPairF64_64
1701
0
    26462U, // CFTC1
1702
0
    10592U, // CONSTPOOL_ENTRY
1703
0
    0U, // COPY_FD_PSEUDO
1704
0
    0U, // COPY_FW_PSEUDO
1705
0
    17885036U,  // CTTC1
1706
0
    550788U,  // Constant32
1707
0
    536893714U, // DMULImmMacro
1708
0
    536893714U, // DMULMacro
1709
0
    536893849U, // DMULOMacro
1710
0
    536895257U, // DMULOUMacro
1711
0
    536893653U, // DROL
1712
0
    536893653U, // DROLImm
1713
0
    536894187U, // DROR
1714
0
    536894187U, // DRORImm
1715
0
    536895419U, // DSDivIMacro
1716
0
    536895419U, // DSDivMacro
1717
0
    536893772U, // DSRemIMacro
1718
0
    536893772U, // DSRemMacro
1719
0
    536895327U, // DUDivIMacro
1720
0
    536895327U, // DUDivMacro
1721
0
    536895250U, // DURemIMacro
1722
0
    536895250U, // DURemMacro
1723
0
    0U, // ERet
1724
0
    0U, // ExtractElementF64
1725
0
    0U, // ExtractElementF64_64
1726
0
    0U, // FABS_D
1727
0
    0U, // FABS_W
1728
0
    0U, // FEXP2_D_1_PSEUDO
1729
0
    0U, // FEXP2_W_1_PSEUDO
1730
0
    0U, // FILL_FD_PSEUDO
1731
0
    0U, // FILL_FW_PSEUDO
1732
0
    2181060488U,  // GotPrologue16
1733
0
    0U, // INSERT_B_VIDX64_PSEUDO
1734
0
    0U, // INSERT_B_VIDX_PSEUDO
1735
0
    0U, // INSERT_D_VIDX64_PSEUDO
1736
0
    0U, // INSERT_D_VIDX_PSEUDO
1737
0
    0U, // INSERT_FD_PSEUDO
1738
0
    0U, // INSERT_FD_VIDX64_PSEUDO
1739
0
    0U, // INSERT_FD_VIDX_PSEUDO
1740
0
    0U, // INSERT_FW_PSEUDO
1741
0
    0U, // INSERT_FW_VIDX64_PSEUDO
1742
0
    0U, // INSERT_FW_VIDX_PSEUDO
1743
0
    0U, // INSERT_H_VIDX64_PSEUDO
1744
0
    0U, // INSERT_H_VIDX_PSEUDO
1745
0
    0U, // INSERT_W_VIDX64_PSEUDO
1746
0
    0U, // INSERT_W_VIDX_PSEUDO
1747
0
    0U, // JALR64Pseudo
1748
0
    0U, // JALRHB64Pseudo
1749
0
    0U, // JALRHBPseudo
1750
0
    0U, // JALRPseudo
1751
0
    0U, // JAL_MMR6
1752
0
    546804U,  // JalOneReg
1753
0
    22516U, // JalTwoReg
1754
0
    50358144U,  // LDMacro
1755
0
    0U, // LDR_D
1756
0
    0U, // LDR_W
1757
0
    0U, // LD_F16
1758
0
    50348038U,  // LOAD_ACC128
1759
0
    50348038U,  // LOAD_ACC64
1760
0
    50348038U,  // LOAD_ACC64DSP
1761
0
    50354654U,  // LOAD_CCOND_DSP
1762
0
    0U, // LONG_BRANCH_ADDiu
1763
0
    0U, // LONG_BRANCH_ADDiu2Op
1764
0
    0U, // LONG_BRANCH_DADDiu
1765
0
    0U, // LONG_BRANCH_DADDiu2Op
1766
0
    0U, // LONG_BRANCH_LUi
1767
0
    0U, // LONG_BRANCH_LUi2Op
1768
0
    0U, // LONG_BRANCH_LUi2Op_64
1769
0
    72032U, // LWM_MM
1770
0
    17042U, // LoadAddrImm32
1771
0
    17063U, // LoadAddrImm64
1772
0
    50348690U,  // LoadAddrReg32
1773
0
    50348711U,  // LoadAddrReg64
1774
0
    22408U, // LoadImm32
1775
0
    22412U, // LoadImm64
1776
0
    19107U, // LoadImmDoubleFGR
1777
0
    19107U, // LoadImmDoubleFGR_32
1778
0
    19107U, // LoadImmDoubleGPR
1779
0
    23539U, // LoadImmSingleFGR
1780
0
    23539U, // LoadImmSingleGPR
1781
0
    1599118U, // LwConstant32
1782
0
    26588U, // MFTACX
1783
0
    536897344U, // MFTC0
1784
0
    26469U, // MFTC1
1785
0
    550833U,  // MFTDSP
1786
0
    26566U, // MFTGPR
1787
0
    26446U, // MFTHC1
1788
0
    26517U, // MFTHI
1789
0
    26531U, // MFTLO
1790
0
    0U, // MIPSeh_return32
1791
0
    0U, // MIPSeh_return64
1792
0
    0U, // MSA_FP_EXTEND_D_PSEUDO
1793
0
    0U, // MSA_FP_EXTEND_W_PSEUDO
1794
0
    0U, // MSA_FP_ROUND_D_PSEUDO
1795
0
    0U, // MSA_FP_ROUND_W_PSEUDO
1796
0
    17885156U,  // MTTACX
1797
0
    2752571207U,  // MTTC0
1798
0
    17885043U,  // MTTC1
1799
0
    550841U,  // MTTDSP
1800
0
    17885134U,  // MTTGPR
1801
0
    17885014U,  // MTTHC1
1802
0
    17885084U,  // MTTHI
1803
0
    17885098U,  // MTTLO
1804
0
    536893715U, // MULImmMacro
1805
0
    536893850U, // MULOMacro
1806
0
    536895258U, // MULOUMacro
1807
0
    24157U, // MultRxRy16
1808
0
    86040157U,  // MultRxRyRz16
1809
0
    24401U, // MultuRxRy16
1810
0
    86040401U,  // MultuRxRyRz16
1811
0
    0U, // NOP
1812
0
    536894182U, // NORImm
1813
0
    536894182U, // NORImm64
1814
0
    0U, // NOR_V_D_PSEUDO
1815
0
    0U, // NOR_V_H_PSEUDO
1816
0
    0U, // NOR_V_W_PSEUDO
1817
0
    0U, // OR_V_D_PSEUDO
1818
0
    0U, // OR_V_H_PSEUDO
1819
0
    0U, // OR_V_W_PSEUDO
1820
0
    0U, // PseudoCMPU_EQ_QB
1821
0
    0U, // PseudoCMPU_LE_QB
1822
0
    0U, // PseudoCMPU_LT_QB
1823
0
    0U, // PseudoCMP_EQ_PH
1824
0
    0U, // PseudoCMP_LE_PH
1825
0
    0U, // PseudoCMP_LT_PH
1826
0
    16390U, // PseudoCVT_D32_W
1827
0
    16390U, // PseudoCVT_D64_L
1828
0
    16390U, // PseudoCVT_D64_W
1829
0
    16390U, // PseudoCVT_S_L
1830
0
    16390U, // PseudoCVT_S_W
1831
0
    0U, // PseudoDMULT
1832
0
    0U, // PseudoDMULTu
1833
0
    0U, // PseudoDSDIV
1834
0
    0U, // PseudoDUDIV
1835
0
    0U, // PseudoD_SELECT_I
1836
0
    0U, // PseudoD_SELECT_I64
1837
0
    0U, // PseudoIndirectBranch
1838
0
    0U, // PseudoIndirectBranch64
1839
0
    0U, // PseudoIndirectBranch64R6
1840
0
    0U, // PseudoIndirectBranchR6
1841
0
    0U, // PseudoIndirectBranch_MM
1842
0
    0U, // PseudoIndirectBranch_MMR6
1843
0
    0U, // PseudoIndirectHazardBranch
1844
0
    0U, // PseudoIndirectHazardBranch64
1845
0
    0U, // PseudoIndrectHazardBranch64R6
1846
0
    0U, // PseudoIndrectHazardBranchR6
1847
0
    0U, // PseudoMADD
1848
0
    0U, // PseudoMADDU
1849
0
    0U, // PseudoMADDU_MM
1850
0
    0U, // PseudoMADD_MM
1851
0
    0U, // PseudoMFHI
1852
0
    0U, // PseudoMFHI64
1853
0
    0U, // PseudoMFHI_MM
1854
0
    0U, // PseudoMFLO
1855
0
    0U, // PseudoMFLO64
1856
0
    0U, // PseudoMFLO_MM
1857
0
    0U, // PseudoMSUB
1858
0
    0U, // PseudoMSUBU
1859
0
    0U, // PseudoMSUBU_MM
1860
0
    0U, // PseudoMSUB_MM
1861
0
    0U, // PseudoMTLOHI
1862
0
    0U, // PseudoMTLOHI64
1863
0
    0U, // PseudoMTLOHI_DSP
1864
0
    0U, // PseudoMTLOHI_MM
1865
0
    0U, // PseudoMULT
1866
0
    0U, // PseudoMULT_MM
1867
0
    0U, // PseudoMULTu
1868
0
    0U, // PseudoMULTu_MM
1869
0
    0U, // PseudoPICK_PH
1870
0
    0U, // PseudoPICK_QB
1871
0
    0U, // PseudoReturn
1872
0
    0U, // PseudoReturn64
1873
0
    0U, // PseudoSDIV
1874
0
    0U, // PseudoSELECTFP_F_D32
1875
0
    0U, // PseudoSELECTFP_F_D64
1876
0
    0U, // PseudoSELECTFP_F_I
1877
0
    0U, // PseudoSELECTFP_F_I64
1878
0
    0U, // PseudoSELECTFP_F_S
1879
0
    0U, // PseudoSELECTFP_T_D32
1880
0
    0U, // PseudoSELECTFP_T_D64
1881
0
    0U, // PseudoSELECTFP_T_I
1882
0
    0U, // PseudoSELECTFP_T_I64
1883
0
    0U, // PseudoSELECTFP_T_S
1884
0
    0U, // PseudoSELECT_D32
1885
0
    0U, // PseudoSELECT_D64
1886
0
    0U, // PseudoSELECT_I
1887
0
    0U, // PseudoSELECT_I64
1888
0
    0U, // PseudoSELECT_S
1889
0
    536891300U, // PseudoTRUNC_W_D
1890
0
    536891300U, // PseudoTRUNC_W_D32
1891
0
    536894799U, // PseudoTRUNC_W_S
1892
0
    0U, // PseudoUDIV
1893
0
    536893654U, // ROL
1894
0
    536893654U, // ROLImm
1895
0
    536894188U, // ROR
1896
0
    536894188U, // RORImm
1897
0
    0U, // RetRA
1898
0
    0U, // RetRA16
1899
0
    50351255U,  // SDC1_M1
1900
0
    0U, // SDIV_MM_Pseudo
1901
0
    50358156U,  // SDMacro
1902
0
    536895420U, // SDivIMacro
1903
0
    536895420U, // SDivMacro
1904
0
    536897473U, // SEQIMacro
1905
0
    536897473U, // SEQMacro
1906
0
    536891526U, // SGE
1907
0
    536891526U, // SGEImm
1908
0
    536891526U, // SGEImm64
1909
0
    536895162U, // SGEU
1910
0
    536895162U, // SGEUImm
1911
0
    536895162U, // SGEUImm64
1912
0
    536895042U, // SGTImm
1913
0
    536895042U, // SGTImm64
1914
0
    536895288U, // SGTUImm
1915
0
    536895288U, // SGTUImm64
1916
0
    536891571U, // SLE
1917
0
    536891571U, // SLEImm
1918
0
    536891571U, // SLEImm64
1919
0
    536895180U, // SLEU
1920
0
    536895180U, // SLEUImm
1921
0
    536895180U, // SLEUImm64
1922
0
    536895058U, // SLTImm64
1923
0
    536895300U, // SLTUImm64
1924
0
    536897424U, // SNEIMacro
1925
0
    536897424U, // SNEMacro
1926
0
    0U, // SNZ_B_PSEUDO
1927
0
    0U, // SNZ_D_PSEUDO
1928
0
    0U, // SNZ_H_PSEUDO
1929
0
    0U, // SNZ_V_PSEUDO
1930
0
    0U, // SNZ_W_PSEUDO
1931
0
    536893773U, // SRemIMacro
1932
0
    536893773U, // SRemMacro
1933
0
    50348038U,  // STORE_ACC128
1934
0
    50348038U,  // STORE_ACC64
1935
0
    50348038U,  // STORE_ACC64DSP
1936
0
    50354670U,  // STORE_CCOND_DSP
1937
0
    0U, // STR_D
1938
0
    0U, // STR_W
1939
0
    0U, // ST_F16
1940
0
    72037U, // SWM_MM
1941
0
    0U, // SZ_B_PSEUDO
1942
0
    0U, // SZ_D_PSEUDO
1943
0
    0U, // SZ_H_PSEUDO
1944
0
    0U, // SZ_V_PSEUDO
1945
0
    0U, // SZ_W_PSEUDO
1946
0
    50348673U,  // SaaAddr
1947
0
    50352145U,  // SaadAddr
1948
0
    2713318U, // SelBeqZ
1949
0
    2713291U, // SelBneZ
1950
0
    3321977288U,  // SelTBteqZCmp
1951
0
    3321976721U,  // SelTBteqZCmpi
1952
0
    3321978450U,  // SelTBteqZSlt
1953
0
    3321976751U,  // SelTBteqZSlti
1954
0
    3321978606U,  // SelTBteqZSltiu
1955
0
    3321978692U,  // SelTBteqZSltu
1956
0
    3858848200U,  // SelTBtneZCmp
1957
0
    3858847633U,  // SelTBtneZCmpi
1958
0
    3858849362U,  // SelTBtneZSlt
1959
0
    3858847663U,  // SelTBtneZSlti
1960
0
    3858849518U,  // SelTBtneZSltiu
1961
0
    3858849604U,  // SelTBtneZSltu
1962
0
    119594578U, // SltCCRxRy16
1963
0
    119592879U, // SltiCCRxImmX16
1964
0
    119594734U, // SltiuCCRxImmX16
1965
0
    119594820U, // SltuCCRxRy16
1966
0
    119594820U, // SltuRxRyRz16
1967
0
    0U, // TAILCALL
1968
0
    0U, // TAILCALL64R6REG
1969
0
    0U, // TAILCALLHB64R6REG
1970
0
    0U, // TAILCALLHBR6REG
1971
0
    0U, // TAILCALLR6REG
1972
0
    0U, // TAILCALLREG
1973
0
    0U, // TAILCALLREG64
1974
0
    0U, // TAILCALLREGHB
1975
0
    0U, // TAILCALLREGHB64
1976
0
    0U, // TAILCALLREG_MM
1977
0
    0U, // TAILCALLREG_MMR6
1978
0
    0U, // TAILCALL_MM
1979
0
    0U, // TAILCALL_MMR6
1980
0
    0U, // TRAP
1981
0
    0U, // TRAP_MM
1982
0
    0U, // UDIV_MM_Pseudo
1983
0
    536895328U, // UDivIMacro
1984
0
    536895328U, // UDivMacro
1985
0
    536895251U, // URemIMacro
1986
0
    536895251U, // URemMacro
1987
0
    50353426U,  // Ulh
1988
0
    50355922U,  // Ulhu
1989
0
    50357901U,  // Ulw
1990
0
    50353979U,  // Ush
1991
0
    50357917U,  // Usw
1992
0
    0U, // XOR_V_D_PSEUDO
1993
0
    0U, // XOR_V_H_PSEUDO
1994
0
    0U, // XOR_V_W_PSEUDO
1995
0
    22052U, // ABSQ_S_PH
1996
0
    22052U, // ABSQ_S_PH_MM
1997
0
    18197U, // ABSQ_S_QB
1998
0
    18197U, // ABSQ_S_QB_MMR2
1999
0
    25616U, // ABSQ_S_W
2000
0
    25616U, // ABSQ_S_W_MM
2001
0
    536891430U, // ADD
2002
0
    18483U, // ADDIUPC
2003
0
    18483U, // ADDIUPC_MM
2004
0
    18483U, // ADDIUPC_MMR6
2005
0
    22995U, // ADDIUR1SP_MM
2006
0
    536887674U, // ADDIUR2_MM
2007
0
    18923931U,  // ADDIUS5_MM
2008
0
    547344U,  // ADDIUSP_MM
2009
0
    536895200U, // ADDIU_MMR6
2010
0
    536892769U, // ADDQH_PH
2011
0
    536892769U, // ADDQH_PH_MMR2
2012
0
    536892886U, // ADDQH_R_PH
2013
0
    536892886U, // ADDQH_R_PH_MMR2
2014
0
    536896203U, // ADDQH_R_W
2015
0
    536896203U, // ADDQH_R_W_MMR2
2016
0
    536895806U, // ADDQH_W
2017
0
    536895806U, // ADDQH_W_MMR2
2018
0
    536892843U, // ADDQ_PH
2019
0
    536892843U, // ADDQ_PH_MM
2020
0
    536892942U, // ADDQ_S_PH
2021
0
    536892942U, // ADDQ_S_PH_MM
2022
0
    536896508U, // ADDQ_S_W
2023
0
    536896508U, // ADDQ_S_W_MM
2024
0
    536894967U, // ADDR_PS64
2025
0
    536889435U, // ADDSC
2026
0
    536889435U, // ADDSC_MM
2027
0
    536888059U, // ADDS_A_B
2028
0
    536889596U, // ADDS_A_D
2029
0
    536891696U, // ADDS_A_H
2030
0
    536895514U, // ADDS_A_W
2031
0
    536888527U, // ADDS_S_B
2032
0
    536890694U, // ADDS_S_D
2033
0
    536892253U, // ADDS_S_H
2034
0
    536896558U, // ADDS_S_W
2035
0
    536888742U, // ADDS_U_B
2036
0
    536891161U, // ADDS_U_D
2037
0
    536892531U, // ADDS_U_H
2038
0
    536896976U, // ADDS_U_W
2039
0
    536887894U, // ADDU16_MM
2040
0
    536887894U, // ADDU16_MMR6
2041
0
    536888977U, // ADDUH_QB
2042
0
    536888977U, // ADDUH_QB_MMR2
2043
0
    536889085U, // ADDUH_R_QB
2044
0
    536889085U, // ADDUH_R_QB_MMR2
2045
0
    536895129U, // ADDU_MMR6
2046
0
    536893041U, // ADDU_PH
2047
0
    536893041U, // ADDU_PH_MMR2
2048
0
    536889190U, // ADDU_QB
2049
0
    536889190U, // ADDU_QB_MM
2050
0
    536892986U, // ADDU_S_PH
2051
0
    536892986U, // ADDU_S_PH_MMR2
2052
0
    536889131U, // ADDU_S_QB
2053
0
    536889131U, // ADDU_S_QB_MM
2054
0
    536888308U, // ADDVI_B
2055
0
    536890116U, // ADDVI_D
2056
0
    536891912U, // ADDVI_H
2057
0
    536895939U, // ADDVI_W
2058
0
    536888820U, // ADDV_B
2059
0
    536891251U, // ADDV_D
2060
0
    536892609U, // ADDV_H
2061
0
    536897076U, // ADDV_W
2062
0
    536889474U, // ADDWC
2063
0
    536889474U, // ADDWC_MM
2064
0
    536888041U, // ADD_A_B
2065
0
    536889577U, // ADD_A_D
2066
0
    536891678U, // ADD_A_H
2067
0
    536895495U, // ADD_A_W
2068
0
    536891430U, // ADD_MM
2069
0
    536891430U, // ADD_MMR6
2070
0
    536893262U, // ADDi
2071
0
    536893262U, // ADDi_MM
2072
0
    536895200U, // ADDiu
2073
0
    536895200U, // ADDiu_MM
2074
0
    536895129U, // ADDu
2075
0
    536895129U, // ADDu_MM
2076
0
    536893803U, // ALIGN
2077
0
    536893803U, // ALIGN_MMR6
2078
0
    18475U, // ALUIPC
2079
0
    18475U, // ALUIPC_MMR6
2080
0
    536891459U, // AND
2081
0
    20021705U,  // AND16_MM
2082
0
    20021705U,  // AND16_MMR6
2083
0
    536891459U, // AND64
2084
0
    536887774U, // ANDI16_MM
2085
0
    536887774U, // ANDI16_MMR6
2086
0
    536888167U, // ANDI_B
2087
0
    536893268U, // ANDI_MMR6
2088
0
    536891459U, // AND_MM
2089
0
    536891459U, // AND_MMR6
2090
0
    536895339U, // AND_V
2091
0
    536893268U, // ANDi
2092
0
    536893268U, // ANDi64
2093
0
    536893268U, // ANDi_MM
2094
0
    536891473U, // APPEND
2095
0
    536891473U, // APPEND_MMR2
2096
0
    536888421U, // ASUB_S_B
2097
0
    536890524U, // ASUB_S_D
2098
0
    536892085U, // ASUB_S_H
2099
0
    536896338U, // ASUB_S_W
2100
0
    536888636U, // ASUB_U_B
2101
0
    536890991U, // ASUB_U_D
2102
0
    536892373U, // ASUB_U_H
2103
0
    536896806U, // ASUB_U_W
2104
0
    536893372U, // AUI
2105
0
    18468U, // AUIPC
2106
0
    18468U, // AUIPC_MMR6
2107
0
    536893372U, // AUI_MMR6
2108
0
    536888507U, // AVER_S_B
2109
0
    536890674U, // AVER_S_D
2110
0
    536892223U, // AVER_S_H
2111
0
    536896538U, // AVER_S_W
2112
0
    536888722U, // AVER_U_B
2113
0
    536891141U, // AVER_U_D
2114
0
    536892511U, // AVER_U_H
2115
0
    536896956U, // AVER_U_W
2116
0
    536888449U, // AVE_S_B
2117
0
    536890606U, // AVE_S_D
2118
0
    536892155U, // AVE_S_H
2119
0
    536896420U, // AVE_S_W
2120
0
    536888664U, // AVE_U_B
2121
0
    536891073U, // AVE_U_D
2122
0
    536892443U, // AVE_U_H
2123
0
    536896888U, // AVE_U_W
2124
0
    24288U, // AddiuRxImmX16
2125
0
    3694304U, // AddiuRxPcImmX16
2126
0
    33578720U,  // AddiuRxRxImm16
2127
0
    33578720U,  // AddiuRxRxImmX16
2128
0
    134242016U, // AddiuRxRyOffMemX16
2129
0
    4220724U, // AddiuSpImm16
2130
0
    550708U,  // AddiuSpImmX16
2131
0
    536895129U, // AdduRxRyRz16
2132
0
    33574979U,  // AndRxRxRy16
2133
0
    557477U,  // B16_MM
2134
0
    536895128U, // BADDu
2135
0
    563183U,  // BAL
2136
0
    559061U,  // BALC
2137
0
    559061U,  // BALC_MMR6
2138
0
    536893802U, // BALIGN
2139
0
    536893802U, // BALIGN_MMR2
2140
0
    151011407U, // BBIT0
2141
0
    151011539U, // BBIT032
2142
0
    151011532U, // BBIT1
2143
0
    151011548U, // BBIT132
2144
0
    559040U,  // BC
2145
0
    557482U,  // BC16_MMR6
2146
0
    167798780U, // BC1EQZ
2147
0
    167790768U, // BC1EQZC_MMR6
2148
0
    167792903U, // BC1F
2149
0
    167794796U, // BC1FL
2150
0
    167792903U, // BC1F_MM
2151
0
    167798764U, // BC1NEZ
2152
0
    167790743U, // BC1NEZC_MMR6
2153
0
    167796279U, // BC1T
2154
0
    167794929U, // BC1TL
2155
0
    167796279U, // BC1T_MM
2156
0
    167798788U, // BC2EQZ
2157
0
    167790777U, // BC2EQZC_MMR6
2158
0
    167798772U, // BC2NEZ
2159
0
    167790752U, // BC2NEZC_MMR6
2160
0
    536888236U, // BCLRI_B
2161
0
    536890060U, // BCLRI_D
2162
0
    536891856U, // BCLRI_H
2163
0
    536895883U, // BCLRI_W
2164
0
    536888388U, // BCLR_B
2165
0
    536890448U, // BCLR_D
2166
0
    536892052U, // BCLR_H
2167
0
    536896254U, // BCLR_W
2168
0
    559040U,  // BC_MMR6
2169
0
    536894020U, // BEQ
2170
0
    536894020U, // BEQ64
2171
0
    536889417U, // BEQC
2172
0
    536889417U, // BEQC64
2173
0
    536889417U, // BEQC_MMR6
2174
0
    536893669U, // BEQL
2175
0
    167789177U, // BEQZ16_MM
2176
0
    167790589U, // BEQZALC
2177
0
    167790589U, // BEQZALC_MMR6
2178
0
    167790786U, // BEQZC
2179
0
    167788992U, // BEQZC16_MMR6
2180
0
    167790786U, // BEQZC64
2181
0
    167790786U, // BEQZC_MM
2182
0
    167790786U, // BEQZC_MMR6
2183
0
    536894020U, // BEQ_MM
2184
0
    536889284U, // BGEC
2185
0
    536889284U, // BGEC64
2186
0
    536889284U, // BGEC_MMR6
2187
0
    536889448U, // BGEUC
2188
0
    536889448U, // BGEUC64
2189
0
    536889448U, // BGEUC_MMR6
2190
0
    167798463U, // BGEZ
2191
0
    167798463U, // BGEZ64
2192
0
    167794681U, // BGEZAL
2193
0
    167790562U, // BGEZALC
2194
0
    167790562U, // BGEZALC_MMR6
2195
0
    167794877U, // BGEZALL
2196
0
    167796145U, // BGEZALS_MM
2197
0
    167794681U, // BGEZAL_MM
2198
0
    167790729U, // BGEZC
2199
0
    167790729U, // BGEZC64
2200
0
    167790729U, // BGEZC_MMR6
2201
0
    167794992U, // BGEZL
2202
0
    167798463U, // BGEZ_MM
2203
0
    167798523U, // BGTZ
2204
0
    167798523U, // BGTZ64
2205
0
    167790598U, // BGTZALC
2206
0
    167790598U, // BGTZALC_MMR6
2207
0
    167790793U, // BGTZC
2208
0
    167790793U, // BGTZC64
2209
0
    167790793U, // BGTZC_MMR6
2210
0
    167795006U, // BGTZL
2211
0
    167798523U, // BGTZ_MM
2212
0
    570442641U, // BINSLI_B
2213
0
    570444465U, // BINSLI_D
2214
0
    570446261U, // BINSLI_H
2215
0
    570450288U, // BINSLI_W
2216
0
    570442788U, // BINSL_B
2217
0
    570444665U, // BINSL_D
2218
0
    570446375U, // BINSL_H
2219
0
    570450446U, // BINSL_W
2220
0
    570442702U, // BINSRI_B
2221
0
    570444510U, // BINSRI_D
2222
0
    570446306U, // BINSRI_H
2223
0
    570450333U, // BINSRI_W
2224
0
    570442836U, // BINSR_B
2225
0
    570444930U, // BINSR_D
2226
0
    570446500U, // BINSR_H
2227
0
    570450736U, // BINSR_W
2228
0
    24499U, // BITREV
2229
0
    24499U, // BITREV_MM
2230
0
    22945U, // BITSWAP
2231
0
    22945U, // BITSWAP_MMR6
2232
0
    167798469U, // BLEZ
2233
0
    167798469U, // BLEZ64
2234
0
    167790571U, // BLEZALC
2235
0
    167790571U, // BLEZALC_MMR6
2236
0
    167790736U, // BLEZC
2237
0
    167790736U, // BLEZC64
2238
0
    167790736U, // BLEZC_MMR6
2239
0
    167794999U, // BLEZL
2240
0
    167798469U, // BLEZ_MM
2241
0
    536889442U, // BLTC
2242
0
    536889442U, // BLTC64
2243
0
    536889442U, // BLTC_MMR6
2244
0
    536889455U, // BLTUC
2245
0
    536889455U, // BLTUC64
2246
0
    536889455U, // BLTUC_MMR6
2247
0
    167798529U, // BLTZ
2248
0
    167798529U, // BLTZ64
2249
0
    167794689U, // BLTZAL
2250
0
    167790607U, // BLTZALC
2251
0
    167790607U, // BLTZALC_MMR6
2252
0
    167794886U, // BLTZALL
2253
0
    167796154U, // BLTZALS_MM
2254
0
    167794689U, // BLTZAL_MM
2255
0
    167790800U, // BLTZC
2256
0
    167790800U, // BLTZC64
2257
0
    167790800U, // BLTZC_MMR6
2258
0
    167795013U, // BLTZL
2259
0
    167798529U, // BLTZ_MM
2260
0
    570442757U, // BMNZI_B
2261
0
    570449828U, // BMNZ_V
2262
0
    570442749U, // BMZI_B
2263
0
    570449814U, // BMZ_V
2264
0
    536891588U, // BNE
2265
0
    536891588U, // BNE64
2266
0
    536889290U, // BNEC
2267
0
    536889290U, // BNEC64
2268
0
    536889290U, // BNEC_MMR6
2269
0
    536888175U, // BNEGI_B
2270
0
    536890008U, // BNEGI_D
2271
0
    536891804U, // BNEGI_H
2272
0
    536895831U, // BNEGI_W
2273
0
    536888143U, // BNEG_B
2274
0
    536889984U, // BNEG_D
2275
0
    536891780U, // BNEG_H
2276
0
    536895726U, // BNEG_W
2277
0
    536893542U, // BNEL
2278
0
    167789169U, // BNEZ16_MM
2279
0
    167790580U, // BNEZALC
2280
0
    167790580U, // BNEZALC_MMR6
2281
0
    167790761U, // BNEZC
2282
0
    167788983U, // BNEZC16_MMR6
2283
0
    167790761U, // BNEZC64
2284
0
    167790761U, // BNEZC_MM
2285
0
    167790761U, // BNEZC_MMR6
2286
0
    536891588U, // BNE_MM
2287
0
    536889462U, // BNVC
2288
0
    536889462U, // BNVC_MMR6
2289
0
    167790108U, // BNZ_B
2290
0
    167792624U, // BNZ_D
2291
0
    167793897U, // BNZ_H
2292
0
    167796637U, // BNZ_V
2293
0
    167798389U, // BNZ_W
2294
0
    536889468U, // BOVC
2295
0
    536889468U, // BOVC_MMR6
2296
0
    557293U,  // BPOSGE32
2297
0
    559029U,  // BPOSGE32C_MMR3
2298
0
    557293U,  // BPOSGE32_MM
2299
0
    184670160U, // BREAK
2300
0
    131572U,  // BREAK16_MM
2301
0
    131572U,  // BREAK16_MMR6
2302
0
    184670160U, // BREAK_MM
2303
0
    184670160U, // BREAK_MMR6
2304
0
    570442616U, // BSELI_B
2305
0
    570449786U, // BSEL_V
2306
0
    536888290U, // BSETI_B
2307
0
    536890098U, // BSETI_D
2308
0
    536891894U, // BSETI_H
2309
0
    536895921U, // BSETI_W
2310
0
    536888604U, // BSET_B
2311
0
    536890810U, // BSET_D
2312
0
    536892341U, // BSET_H
2313
0
    536896712U, // BSET_W
2314
0
    167790102U, // BZ_B
2315
0
    167792608U, // BZ_D
2316
0
    167793891U, // BZ_H
2317
0
    167796624U, // BZ_V
2318
0
    167798383U, // BZ_W
2319
0
    704669414U, // BeqzRxImm16
2320
0
    167798502U, // BeqzRxImmX16
2321
0
    4227823U, // Bimm16
2322
0
    557807U,  // BimmX16
2323
0
    704669387U, // BnezRxImm16
2324
0
    167798475U, // BnezRxImmX16
2325
0
    10403U, // Break16
2326
0
    4744948U, // Bteqz16
2327
0
    550644U,  // BteqzX16
2328
0
    4744921U, // Btnez16
2329
0
    550617U,  // BtnezX16
2330
0
    5394576U, // CACHE
2331
0
    5394546U, // CACHEE
2332
0
    5394546U, // CACHEE_MM
2333
0
    5394576U, // CACHE_MM
2334
0
    5394576U, // CACHE_MMR6
2335
0
    5394576U, // CACHE_R6
2336
0
    19235U, // CEIL_L_D64
2337
0
    19235U, // CEIL_L_D_MMR6
2338
0
    23567U, // CEIL_L_S
2339
0
    23567U, // CEIL_L_S_MMR6
2340
0
    20410U, // CEIL_W_D32
2341
0
    20410U, // CEIL_W_D64
2342
0
    20410U, // CEIL_W_D_MMR6
2343
0
    20410U, // CEIL_W_MM
2344
0
    23909U, // CEIL_W_S
2345
0
    23909U, // CEIL_W_S_MM
2346
0
    23909U, // CEIL_W_S_MMR6
2347
0
    536888219U, // CEQI_B
2348
0
    536890043U, // CEQI_D
2349
0
    536891839U, // CEQI_H
2350
0
    536895866U, // CEQI_W
2351
0
    536888373U, // CEQ_B
2352
0
    536890355U, // CEQ_D
2353
0
    536892030U, // CEQ_H
2354
0
    536896142U, // CEQ_W
2355
0
    16482U, // CFC1
2356
0
    16482U, // CFC1_MM
2357
0
    16698U, // CFC2_MM
2358
0
    17113U, // CFCMSA
2359
0
    536894915U, // CINS
2360
0
    536887582U, // CINS32
2361
0
    536894915U, // CINS64_32
2362
0
    536894915U, // CINS_i32
2363
0
    19880U, // CLASS_D
2364
0
    19880U, // CLASS_D_MMR6
2365
0
    23760U, // CLASS_S
2366
0
    23760U, // CLASS_S_MMR6
2367
0
    536888458U, // CLEI_S_B
2368
0
    536890615U, // CLEI_S_D
2369
0
    536892164U, // CLEI_S_H
2370
0
    536896429U, // CLEI_S_W
2371
0
    536888673U, // CLEI_U_B
2372
0
    536891082U, // CLEI_U_D
2373
0
    536892452U, // CLEI_U_H
2374
0
    536896897U, // CLEI_U_W
2375
0
    536888440U, // CLE_S_B
2376
0
    536890597U, // CLE_S_D
2377
0
    536892146U, // CLE_S_H
2378
0
    536896411U, // CLE_S_W
2379
0
    536888655U, // CLE_U_B
2380
0
    536891064U, // CLE_U_D
2381
0
    536892434U, // CLE_U_H
2382
0
    536896879U, // CLE_U_W
2383
0
    22913U, // CLO
2384
0
    22913U, // CLO_MM
2385
0
    22913U, // CLO_MMR6
2386
0
    22913U, // CLO_R6
2387
0
    536888478U, // CLTI_S_B
2388
0
    536890635U, // CLTI_S_D
2389
0
    536892184U, // CLTI_S_H
2390
0
    536896449U, // CLTI_S_W
2391
0
    536888693U, // CLTI_U_B
2392
0
    536891102U, // CLTI_U_D
2393
0
    536892472U, // CLTI_U_H
2394
0
    536896917U, // CLTI_U_W
2395
0
    536888546U, // CLT_S_B
2396
0
    536890713U, // CLT_S_D
2397
0
    536892272U, // CLT_S_H
2398
0
    536896577U, // CLT_S_W
2399
0
    536888773U, // CLT_U_B
2400
0
    536891192U, // CLT_U_D
2401
0
    536892562U, // CLT_U_H
2402
0
    536897007U, // CLT_U_W
2403
0
    26337U, // CLZ
2404
0
    26337U, // CLZ_MM
2405
0
    26337U, // CLZ_MMR6
2406
0
    26337U, // CLZ_R6
2407
0
    536889023U, // CMPGDU_EQ_QB
2408
0
    536889023U, // CMPGDU_EQ_QB_MMR2
2409
0
    536888928U, // CMPGDU_LE_QB
2410
0
    536888928U, // CMPGDU_LE_QB_MMR2
2411
0
    536889142U, // CMPGDU_LT_QB
2412
0
    536889142U, // CMPGDU_LT_QB_MMR2
2413
0
    536889037U, // CMPGU_EQ_QB
2414
0
    536889037U, // CMPGU_EQ_QB_MM
2415
0
    536888942U, // CMPGU_LE_QB
2416
0
    536888942U, // CMPGU_LE_QB_MM
2417
0
    536889156U, // CMPGU_LT_QB
2418
0
    536889156U, // CMPGU_LT_QB_MM
2419
0
    18138U, // CMPU_EQ_QB
2420
0
    18138U, // CMPU_EQ_QB_MM
2421
0
    18043U, // CMPU_LE_QB
2422
0
    18043U, // CMPU_LE_QB_MM
2423
0
    18257U, // CMPU_LT_QB
2424
0
    18257U, // CMPU_LT_QB_MM
2425
0
    536889905U, // CMP_AF_D_MMR6
2426
0
    536894389U, // CMP_AF_S_MMR6
2427
0
    536890344U, // CMP_EQ_D
2428
0
    536890344U, // CMP_EQ_D_MMR6
2429
0
    21940U, // CMP_EQ_PH
2430
0
    21940U, // CMP_EQ_PH_MM
2431
0
    536894593U, // CMP_EQ_S
2432
0
    536894593U, // CMP_EQ_S_MMR6
2433
0
    536889905U, // CMP_F_D
2434
0
    536894389U, // CMP_F_S
2435
0
    536889749U, // CMP_LE_D
2436
0
    536889749U, // CMP_LE_D_MMR6
2437
0
    21836U, // CMP_LE_PH
2438
0
    21836U, // CMP_LE_PH_MM
2439
0
    536894310U, // CMP_LE_S
2440
0
    536894310U, // CMP_LE_S_MMR6
2441
0
    536890835U, // CMP_LT_D
2442
0
    536890835U, // CMP_LT_D_MMR6
2443
0
    22109U, // CMP_LT_PH
2444
0
    22109U, // CMP_LT_PH_MM
2445
0
    536894698U, // CMP_LT_S
2446
0
    536894698U, // CMP_LT_S_MMR6
2447
0
    536889923U, // CMP_SAF_D
2448
0
    536889923U, // CMP_SAF_D_MMR6
2449
0
    536894399U, // CMP_SAF_S
2450
0
    536894399U, // CMP_SAF_S_MMR6
2451
0
    536890371U, // CMP_SEQ_D
2452
0
    536890371U, // CMP_SEQ_D_MMR6
2453
0
    536894612U, // CMP_SEQ_S
2454
0
    536894612U, // CMP_SEQ_S_MMR6
2455
0
    536889786U, // CMP_SLE_D
2456
0
    536889786U, // CMP_SLE_D_MMR6
2457
0
    536894339U, // CMP_SLE_S
2458
0
    536894339U, // CMP_SLE_S_MMR6
2459
0
    536890862U, // CMP_SLT_D
2460
0
    536890862U, // CMP_SLT_D_MMR6
2461
0
    536894717U, // CMP_SLT_S
2462
0
    536894717U, // CMP_SLT_S_MMR6
2463
0
    536890419U, // CMP_SUEQ_D
2464
0
    536890419U, // CMP_SUEQ_D_MMR6
2465
0
    536894643U, // CMP_SUEQ_S
2466
0
    536894643U, // CMP_SUEQ_S_MMR6
2467
0
    536889834U, // CMP_SULE_D
2468
0
    536889834U, // CMP_SULE_D_MMR6
2469
0
    536894370U, // CMP_SULE_S
2470
0
    536894370U, // CMP_SULE_S_MMR6
2471
0
    536890910U, // CMP_SULT_D
2472
0
    536890910U, // CMP_SULT_D_MMR6
2473
0
    536894748U, // CMP_SULT_S
2474
0
    536894748U, // CMP_SULT_S_MMR6
2475
0
    536890292U, // CMP_SUN_D
2476
0
    536890292U, // CMP_SUN_D_MMR6
2477
0
    536894557U, // CMP_SUN_S
2478
0
    536894557U, // CMP_SUN_S_MMR6
2479
0
    536890399U, // CMP_UEQ_D
2480
0
    536890399U, // CMP_UEQ_D_MMR6
2481
0
    536894632U, // CMP_UEQ_S
2482
0
    536894632U, // CMP_UEQ_S_MMR6
2483
0
    536889814U, // CMP_ULE_D
2484
0
    536889814U, // CMP_ULE_D_MMR6
2485
0
    536894359U, // CMP_ULE_S
2486
0
    536894359U, // CMP_ULE_S_MMR6
2487
0
    536890890U, // CMP_ULT_D
2488
0
    536890890U, // CMP_ULT_D_MMR6
2489
0
    536894737U, // CMP_ULT_S
2490
0
    536894737U, // CMP_ULT_S_MMR6
2491
0
    536890274U, // CMP_UN_D
2492
0
    536890274U, // CMP_UN_D_MMR6
2493
0
    536894547U, // CMP_UN_S
2494
0
    536894547U, // CMP_UN_S_MMR6
2495
0
    1073759497U,  // COPY_S_B
2496
0
    1073761686U,  // COPY_S_D
2497
0
    1073763234U,  // COPY_S_H
2498
0
    1073767561U,  // COPY_S_W
2499
0
    1073759712U,  // COPY_U_B
2500
0
    1073763501U,  // COPY_U_H
2501
0
    1073767968U,  // COPY_U_W
2502
0
    536888867U, // CRC32B
2503
0
    536888875U, // CRC32CB
2504
0
    536891415U, // CRC32CD
2505
0
    536892676U, // CRC32CH
2506
0
    536897156U, // CRC32CW
2507
0
    536891401U, // CRC32D
2508
0
    536892656U, // CRC32H
2509
0
    536897148U, // CRC32W
2510
0
    17875069U,  // CTC1
2511
0
    17875069U,  // CTC1_MM
2512
0
    17875285U,  // CTC2_MM
2513
0
    17121U, // CTCMSA
2514
0
    23363U, // CVT_D32_S
2515
0
    23363U, // CVT_D32_S_MM
2516
0
    24662U, // CVT_D32_W
2517
0
    24662U, // CVT_D32_W_MM
2518
0
    22493U, // CVT_D64_L
2519
0
    23363U, // CVT_D64_S
2520
0
    23363U, // CVT_D64_S_MM
2521
0
    24662U, // CVT_D64_W
2522
0
    24662U, // CVT_D64_W_MM
2523
0
    22493U, // CVT_D_L_MMR6
2524
0
    19256U, // CVT_L_D64
2525
0
    19256U, // CVT_L_D64_MM
2526
0
    19256U, // CVT_L_D_MMR6
2527
0
    23588U, // CVT_L_S
2528
0
    23588U, // CVT_L_S_MM
2529
0
    23588U, // CVT_L_S_MMR6
2530
0
    26258U, // CVT_PS_PW64
2531
0
    536894662U, // CVT_PS_S64
2532
0
    24089U, // CVT_PW_PS64
2533
0
    19603U, // CVT_S_D32
2534
0
    19603U, // CVT_S_D32_MM
2535
0
    19603U, // CVT_S_D64
2536
0
    19603U, // CVT_S_D64_MM
2537
0
    22502U, // CVT_S_L
2538
0
    22502U, // CVT_S_L_MMR6
2539
0
    22747U, // CVT_S_PL64
2540
0
    24353U, // CVT_S_PU64
2541
0
    25417U, // CVT_S_W
2542
0
    25417U, // CVT_S_W_MM
2543
0
    25417U, // CVT_S_W_MMR6
2544
0
    20431U, // CVT_W_D32
2545
0
    20431U, // CVT_W_D32_MM
2546
0
    20431U, // CVT_W_D64
2547
0
    20431U, // CVT_W_D64_MM
2548
0
    23930U, // CVT_W_S
2549
0
    23930U, // CVT_W_S_MM
2550
0
    23930U, // CVT_W_S_MMR6
2551
0
    536890336U, // C_EQ_D32
2552
0
    536890336U, // C_EQ_D32_MM
2553
0
    536890336U, // C_EQ_D64
2554
0
    536890336U, // C_EQ_D64_MM
2555
0
    536894585U, // C_EQ_S
2556
0
    536894585U, // C_EQ_S_MM
2557
0
    536889898U, // C_F_D32
2558
0
    536889898U, // C_F_D32_MM
2559
0
    536889898U, // C_F_D64
2560
0
    536889898U, // C_F_D64_MM
2561
0
    536894382U, // C_F_S
2562
0
    536894382U, // C_F_S_MM
2563
0
    536889741U, // C_LE_D32
2564
0
    536889741U, // C_LE_D32_MM
2565
0
    536889741U, // C_LE_D64
2566
0
    536889741U, // C_LE_D64_MM
2567
0
    536894302U, // C_LE_S
2568
0
    536894302U, // C_LE_S_MM
2569
0
    536890827U, // C_LT_D32
2570
0
    536890827U, // C_LT_D32_MM
2571
0
    536890827U, // C_LT_D64
2572
0
    536890827U, // C_LT_D64_MM
2573
0
    536894690U, // C_LT_S
2574
0
    536894690U, // C_LT_S_MM
2575
0
    536889732U, // C_NGE_D32
2576
0
    536889732U, // C_NGE_D32_MM
2577
0
    536889732U, // C_NGE_D64
2578
0
    536889732U, // C_NGE_D64_MM
2579
0
    536894293U, // C_NGE_S
2580
0
    536894293U, // C_NGE_S_MM
2581
0
    536889767U, // C_NGLE_D32
2582
0
    536889767U, // C_NGLE_D32_MM
2583
0
    536889767U, // C_NGLE_D64
2584
0
    536889767U, // C_NGLE_D64_MM
2585
0
    536894320U, // C_NGLE_S
2586
0
    536894320U, // C_NGLE_S_MM
2587
0
    536890184U, // C_NGL_D32
2588
0
    536890184U, // C_NGL_D32_MM
2589
0
    536890184U, // C_NGL_D64
2590
0
    536890184U, // C_NGL_D64_MM
2591
0
    536894516U, // C_NGL_S
2592
0
    536894516U, // C_NGL_S_MM
2593
0
    536890818U, // C_NGT_D32
2594
0
    536890818U, // C_NGT_D32_MM
2595
0
    536890818U, // C_NGT_D64
2596
0
    536890818U, // C_NGT_D64_MM
2597
0
    536894681U, // C_NGT_S
2598
0
    536894681U, // C_NGT_S_MM
2599
0
    536889777U, // C_OLE_D32
2600
0
    536889777U, // C_OLE_D32_MM
2601
0
    536889777U, // C_OLE_D64
2602
0
    536889777U, // C_OLE_D64_MM
2603
0
    536894330U, // C_OLE_S
2604
0
    536894330U, // C_OLE_S_MM
2605
0
    536890853U, // C_OLT_D32
2606
0
    536890853U, // C_OLT_D32_MM
2607
0
    536890853U, // C_OLT_D64
2608
0
    536890853U, // C_OLT_D64_MM
2609
0
    536894708U, // C_OLT_S
2610
0
    536894708U, // C_OLT_S_MM
2611
0
    536890362U, // C_SEQ_D32
2612
0
    536890362U, // C_SEQ_D32_MM
2613
0
    536890362U, // C_SEQ_D64
2614
0
    536890362U, // C_SEQ_D64_MM
2615
0
    536894603U, // C_SEQ_S
2616
0
    536894603U, // C_SEQ_S_MM
2617
0
    536889968U, // C_SF_D32
2618
0
    536889968U, // C_SF_D32_MM
2619
0
    536889968U, // C_SF_D64
2620
0
    536889968U, // C_SF_D64_MM
2621
0
    536894428U, // C_SF_S
2622
0
    536894428U, // C_SF_S_MM
2623
0
    536890390U, // C_UEQ_D32
2624
0
    536890390U, // C_UEQ_D32_MM
2625
0
    536890390U, // C_UEQ_D64
2626
0
    536890390U, // C_UEQ_D64_MM
2627
0
    536894623U, // C_UEQ_S
2628
0
    536894623U, // C_UEQ_S_MM
2629
0
    536889805U, // C_ULE_D32
2630
0
    536889805U, // C_ULE_D32_MM
2631
0
    536889805U, // C_ULE_D64
2632
0
    536889805U, // C_ULE_D64_MM
2633
0
    536894350U, // C_ULE_S
2634
0
    536894350U, // C_ULE_S_MM
2635
0
    536890881U, // C_ULT_D32
2636
0
    536890881U, // C_ULT_D32_MM
2637
0
    536890881U, // C_ULT_D64
2638
0
    536890881U, // C_ULT_D64_MM
2639
0
    536894728U, // C_ULT_S
2640
0
    536894728U, // C_ULT_S_MM
2641
0
    536890266U, // C_UN_D32
2642
0
    536890266U, // C_UN_D32_MM
2643
0
    536890266U, // C_UN_D64
2644
0
    536890266U, // C_UN_D64_MM
2645
0
    536894539U, // C_UN_S
2646
0
    536894539U, // C_UN_S_MM
2647
0
    22984U, // CmpRxRy16
2648
0
    1610635153U,  // CmpiRxImm16
2649
0
    22417U, // CmpiRxImmX16
2650
0
    536891429U, // DADD
2651
0
    536893261U, // DADDi
2652
0
    536895199U, // DADDiu
2653
0
    536895135U, // DADDu
2654
0
    536893292U, // DAHI
2655
0
    536893810U, // DALIGN
2656
0
    536893353U, // DATI
2657
0
    536893371U, // DAUI
2658
0
    22944U, // DBITSWAP
2659
0
    22912U, // DCLO
2660
0
    22912U, // DCLO_R6
2661
0
    26336U, // DCLZ
2662
0
    26336U, // DCLZ_R6
2663
0
    536895419U, // DDIV
2664
0
    536895327U, // DDIVU
2665
0
    10637U, // DERET
2666
0
    10637U, // DERET_MM
2667
0
    10637U, // DERET_MMR6
2668
0
    536895103U, // DEXT
2669
0
    536897494U, // DEXT64_32
2670
0
    536893785U, // DEXTM
2671
0
    536895320U, // DEXTU
2672
0
    546640U,  // DI
2673
0
    536894921U, // DINS
2674
0
    536893778U, // DINSM
2675
0
    536895275U, // DINSU
2676
0
    536895420U, // DIV
2677
0
    536895328U, // DIVU
2678
0
    536895328U, // DIVU_MMR6
2679
0
    536895420U, // DIV_MMR6
2680
0
    536888567U, // DIV_S_B
2681
0
    536890756U, // DIV_S_D
2682
0
    536892293U, // DIV_S_H
2683
0
    536896620U, // DIV_S_W
2684
0
    536888782U, // DIV_U_B
2685
0
    536891223U, // DIV_U_D
2686
0
    536892571U, // DIV_U_H
2687
0
    536897038U, // DIV_U_W
2688
0
    546640U,  // DI_MM
2689
0
    546640U,  // DI_MMR6
2690
0
    536888019U, // DLSA
2691
0
    536888019U, // DLSA_R6
2692
0
    536887297U, // DMFC0
2693
0
    16488U, // DMFC1
2694
0
    536887616U, // DMFC2
2695
0
    201343296U, // DMFC2_OCTEON
2696
0
    536887304U, // DMFGC0
2697
0
    536891481U, // DMOD
2698
0
    536895149U, // DMODU
2699
0
    548451U,  // DMT
2700
0
    2752561206U,  // DMTC0
2701
0
    17875075U,  // DMTC1
2702
0
    2752561499U,  // DMTC2
2703
0
    201343323U, // DMTC2_OCTEON
2704
0
    2752561184U,  // DMTGC0
2705
0
    536893248U, // DMUH
2706
0
    536895192U, // DMUHU
2707
0
    536893714U, // DMUL
2708
0
    24156U, // DMULT
2709
0
    24400U, // DMULTu
2710
0
    536895236U, // DMULU
2711
0
    536893714U, // DMUL_R6
2712
0
    536890664U, // DOTP_S_D
2713
0
    536892213U, // DOTP_S_H
2714
0
    536896488U, // DOTP_S_W
2715
0
    536891131U, // DOTP_U_D
2716
0
    536892501U, // DOTP_U_H
2717
0
    536896946U, // DOTP_U_W
2718
0
    570445009U, // DPADD_S_D
2719
0
    570446558U, // DPADD_S_H
2720
0
    570450823U, // DPADD_S_W
2721
0
    570445476U, // DPADD_U_D
2722
0
    570446846U, // DPADD_U_H
2723
0
    570451291U, // DPADD_U_W
2724
0
    536893100U, // DPAQX_SA_W_PH
2725
0
    536893100U, // DPAQX_SA_W_PH_MMR2
2726
0
    536893183U, // DPAQX_S_W_PH
2727
0
    536893183U, // DPAQX_S_W_PH_MMR2
2728
0
    536895948U, // DPAQ_SA_L_W
2729
0
    536895948U, // DPAQ_SA_L_W_MM
2730
0
    536893142U, // DPAQ_S_W_PH
2731
0
    536893142U, // DPAQ_S_W_PH_MM
2732
0
    536893449U, // DPAU_H_QBL
2733
0
    536893449U, // DPAU_H_QBL_MM
2734
0
    536894035U, // DPAU_H_QBR
2735
0
    536894035U, // DPAU_H_QBR_MM
2736
0
    536893221U, // DPAX_W_PH
2737
0
    536893221U, // DPAX_W_PH_MMR2
2738
0
    536893090U, // DPA_W_PH
2739
0
    536893090U, // DPA_W_PH_MMR2
2740
0
    22989U, // DPOP
2741
0
    536893115U, // DPSQX_SA_W_PH
2742
0
    536893115U, // DPSQX_SA_W_PH_MMR2
2743
0
    536893197U, // DPSQX_S_W_PH
2744
0
    536893197U, // DPSQX_S_W_PH_MMR2
2745
0
    536895961U, // DPSQ_SA_L_W
2746
0
    536895961U, // DPSQ_SA_L_W_MM
2747
0
    536893170U, // DPSQ_S_W_PH
2748
0
    536893170U, // DPSQ_S_W_PH_MM
2749
0
    570444976U, // DPSUB_S_D
2750
0
    570446537U, // DPSUB_S_H
2751
0
    570450790U, // DPSUB_S_W
2752
0
    570445443U, // DPSUB_U_D
2753
0
    570446825U, // DPSUB_U_H
2754
0
    570451258U, // DPSUB_U_W
2755
0
    536893461U, // DPSU_H_QBL
2756
0
    536893461U, // DPSU_H_QBL_MM
2757
0
    536894047U, // DPSU_H_QBR
2758
0
    536894047U, // DPSU_H_QBR_MM
2759
0
    536893232U, // DPSX_W_PH
2760
0
    536893232U, // DPSX_W_PH_MMR2
2761
0
    536893211U, // DPS_W_PH
2762
0
    536893211U, // DPS_W_PH_MMR2
2763
0
    536894220U, // DROTR
2764
0
    536887573U, // DROTR32
2765
0
    536895463U, // DROTRV
2766
0
    21752U, // DSBH
2767
0
    26407U, // DSDIV
2768
0
    20529U, // DSHD
2769
0
    536893647U, // DSLL
2770
0
    536887543U, // DSLL32
2771
0
    2147506383U,  // DSLL64_32
2772
0
    536895425U, // DSLLV
2773
0
    536888013U, // DSRA
2774
0
    536887525U, // DSRA32
2775
0
    536895404U, // DSRAV
2776
0
    536893675U, // DSRL
2777
0
    536887551U, // DSRL32
2778
0
    536895432U, // DSRLV
2779
0
    536889257U, // DSUB
2780
0
    536895114U, // DSUBu
2781
0
    26393U, // DUDIV
2782
0
    547376U,  // DVP
2783
0
    544979U,  // DVPE
2784
0
    547376U,  // DVP_MMR6
2785
0
    26408U, // DivRxRy16
2786
0
    26394U, // DivuRxRy16
2787
0
    10531U, // EHB
2788
0
    10531U, // EHB_MM
2789
0
    10531U, // EHB_MMR6
2790
0
    546652U,  // EI
2791
0
    546652U,  // EI_MM
2792
0
    546652U,  // EI_MMR6
2793
0
    548456U,  // EMT
2794
0
    10638U, // ERET
2795
0
    10535U, // ERETNC
2796
0
    10535U, // ERETNC_MMR6
2797
0
    10638U, // ERET_MM
2798
0
    10638U, // ERET_MMR6
2799
0
    547381U,  // EVP
2800
0
    544985U,  // EVPE
2801
0
    547381U,  // EVP_MMR6
2802
0
    536895104U, // EXT
2803
0
    536893994U, // EXTP
2804
0
    536893873U, // EXTPDP
2805
0
    536895447U, // EXTPDPV
2806
0
    536895447U, // EXTPDPV_MM
2807
0
    536893873U, // EXTPDP_MM
2808
0
    536895456U, // EXTPV
2809
0
    536895456U, // EXTPV_MM
2810
0
    536893994U, // EXTP_MM
2811
0
    536896681U, // EXTRV_RS_W
2812
0
    536896681U, // EXTRV_RS_W_MM
2813
0
    536896235U, // EXTRV_R_W
2814
0
    536896235U, // EXTRV_R_W_MM
2815
0
    536892302U, // EXTRV_S_H
2816
0
    536892302U, // EXTRV_S_H_MM
2817
0
    536897118U, // EXTRV_W
2818
0
    536897118U, // EXTRV_W_MM
2819
0
    536896670U, // EXTR_RS_W
2820
0
    536896670U, // EXTR_RS_W_MM
2821
0
    536896214U, // EXTR_R_W
2822
0
    536896214U, // EXTR_R_W_MM
2823
0
    536892233U, // EXTR_S_H
2824
0
    536892233U, // EXTR_S_H_MM
2825
0
    536896313U, // EXTR_W
2826
0
    536896313U, // EXTR_W_MM
2827
0
    536895019U, // EXTS
2828
0
    536887590U, // EXTS32
2829
0
    536895104U, // EXT_MM
2830
0
    536895104U, // EXT_MMR6
2831
0
    19872U, // FABS_D32
2832
0
    19872U, // FABS_D32_MM
2833
0
    19872U, // FABS_D64
2834
0
    19872U, // FABS_D64_MM
2835
0
    23743U, // FABS_S
2836
0
    23743U, // FABS_S_MM
2837
0
    536889681U, // FADD_D
2838
0
    536889682U, // FADD_D32
2839
0
    536889682U, // FADD_D32_MM
2840
0
    536889682U, // FADD_D64
2841
0
    536889682U, // FADD_D64_MM
2842
0
    536894935U, // FADD_PS64
2843
0
    536894286U, // FADD_S
2844
0
    536894286U, // FADD_S_MM
2845
0
    570448718U, // FADD_S_MMR6
2846
0
    536895583U, // FADD_W
2847
0
    536889915U, // FCAF_D
2848
0
    536895702U, // FCAF_W
2849
0
    536890354U, // FCEQ_D
2850
0
    536896141U, // FCEQ_W
2851
0
    19879U, // FCLASS_D
2852
0
    25781U, // FCLASS_W
2853
0
    536889759U, // FCLE_D
2854
0
    536895625U, // FCLE_W
2855
0
    536890845U, // FCLT_D
2856
0
    536896720U, // FCLT_W
2857
0
    5941291U, // FCMP_D32
2858
0
    5941291U, // FCMP_D32_MM
2859
0
    5941291U, // FCMP_D64
2860
0
    6465579U, // FCMP_S32
2861
0
    6465579U, // FCMP_S32_MM
2862
0
    536889855U, // FCNE_D
2863
0
    536895659U, // FCNE_W
2864
0
    536890464U, // FCOR_D
2865
0
    536896270U, // FCOR_W
2866
0
    536890410U, // FCUEQ_D
2867
0
    536896157U, // FCUEQ_W
2868
0
    536889825U, // FCULE_D
2869
0
    536895641U, // FCULE_W
2870
0
    536890901U, // FCULT_D
2871
0
    536896736U, // FCULT_W
2872
0
    536889871U, // FCUNE_D
2873
0
    536895675U, // FCUNE_W
2874
0
    536890284U, // FCUN_D
2875
0
    536896047U, // FCUN_W
2876
0
    536891277U, // FDIV_D
2877
0
    536891278U, // FDIV_D32
2878
0
    536891278U, // FDIV_D32_MM
2879
0
    536891278U, // FDIV_D64
2880
0
    536891278U, // FDIV_D64_MM
2881
0
    536894785U, // FDIV_S
2882
0
    536894785U, // FDIV_S_MM
2883
0
    570449217U, // FDIV_S_MMR6
2884
0
    536897102U, // FDIV_W
2885
0
    536891960U, // FEXDO_H
2886
0
    536896063U, // FEXDO_W
2887
0
    536889568U, // FEXP2_D
2888
0
    536895486U, // FEXP2_W
2889
0
    19296U, // FEXUPL_D
2890
0
    25077U, // FEXUPL_W
2891
0
    19568U, // FEXUPR_D
2892
0
    25374U, // FEXUPR_W
2893
0
    19810U, // FFINT_S_D
2894
0
    25674U, // FFINT_S_W
2895
0
    20289U, // FFINT_U_D
2896
0
    26104U, // FFINT_U_W
2897
0
    19306U, // FFQL_D
2898
0
    25087U, // FFQL_W
2899
0
    19578U, // FFQR_D
2900
0
    25384U, // FFQR_W
2901
0
    17422U, // FILL_B
2902
0
    19281U, // FILL_D
2903
0
    21009U, // FILL_H
2904
0
    25062U, // FILL_W
2905
0
    18647U, // FLOG2_D
2906
0
    24565U, // FLOG2_W
2907
0
    19245U, // FLOOR_L_D64
2908
0
    19245U, // FLOOR_L_D_MMR6
2909
0
    23577U, // FLOOR_L_S
2910
0
    23577U, // FLOOR_L_S_MMR6
2911
0
    20420U, // FLOOR_W_D32
2912
0
    20420U, // FLOOR_W_D64
2913
0
    20420U, // FLOOR_W_D_MMR6
2914
0
    20420U, // FLOOR_W_MM
2915
0
    23919U, // FLOOR_W_S
2916
0
    23919U, // FLOOR_W_S_MM
2917
0
    23919U, // FLOOR_W_S_MMR6
2918
0
    570444121U, // FMADD_D
2919
0
    570450023U, // FMADD_W
2920
0
    536889606U, // FMAX_A_D
2921
0
    536895524U, // FMAX_A_W
2922
0
    536891352U, // FMAX_D
2923
0
    536897127U, // FMAX_W
2924
0
    536889586U, // FMIN_A_D
2925
0
    536895504U, // FMIN_A_W
2926
0
    536890258U, // FMIN_D
2927
0
    536896039U, // FMIN_W
2928
0
    20381U, // FMOV_D32
2929
0
    20381U, // FMOV_D32_MM
2930
0
    20381U, // FMOV_D64
2931
0
    20381U, // FMOV_D64_MM
2932
0
    20381U, // FMOV_D_MMR6
2933
0
    23880U, // FMOV_S
2934
0
    23880U, // FMOV_S_MM
2935
0
    23880U, // FMOV_S_MMR6
2936
0
    570444079U, // FMSUB_D
2937
0
    570449981U, // FMSUB_W
2938
0
    536890242U, // FMUL_D
2939
0
    536890243U, // FMUL_D32
2940
0
    536890243U, // FMUL_D32_MM
2941
0
    536890243U, // FMUL_D64
2942
0
    536890243U, // FMUL_D64_MM
2943
0
    536894951U, // FMUL_PS64
2944
0
    536894525U, // FMUL_S
2945
0
    536894525U, // FMUL_S_MM
2946
0
    570448957U, // FMUL_S_MMR6
2947
0
    536896023U, // FMUL_W
2948
0
    19073U, // FNEG_D32
2949
0
    19073U, // FNEG_D32_MM
2950
0
    19073U, // FNEG_D64
2951
0
    19073U, // FNEG_D64_MM
2952
0
    23532U, // FNEG_S
2953
0
    23532U, // FNEG_S_MM
2954
0
    23532U, // FNEG_S_MMR6
2955
0
    2752567255U,  // FORK
2956
0
    19407U, // FRCP_D
2957
0
    25160U, // FRCP_W
2958
0
    20027U, // FRINT_D
2959
0
    25850U, // FRINT_W
2960
0
    20055U, // FRSQRT_D
2961
0
    25878U, // FRSQRT_W
2962
0
    536889934U, // FSAF_D
2963
0
    536895710U, // FSAF_W
2964
0
    536890382U, // FSEQ_D
2965
0
    536896149U, // FSEQ_W
2966
0
    536889797U, // FSLE_D
2967
0
    536895633U, // FSLE_W
2968
0
    536890873U, // FSLT_D
2969
0
    536896728U, // FSLT_W
2970
0
    536889863U, // FSNE_D
2971
0
    536895667U, // FSNE_W
2972
0
    536890472U, // FSOR_D
2973
0
    536896278U, // FSOR_W
2974
0
    20046U, // FSQRT_D
2975
0
    20047U, // FSQRT_D32
2976
0
    20047U, // FSQRT_D32_MM
2977
0
    20047U, // FSQRT_D64
2978
0
    20047U, // FSQRT_D64_MM
2979
0
    23857U, // FSQRT_S
2980
0
    23857U, // FSQRT_S_MM
2981
0
    25869U, // FSQRT_W
2982
0
    536889639U, // FSUB_D
2983
0
    536889640U, // FSUB_D32
2984
0
    536889640U, // FSUB_D32_MM
2985
0
    536889640U, // FSUB_D64
2986
0
    536889640U, // FSUB_D64_MM
2987
0
    536894927U, // FSUB_PS64
2988
0
    536894268U, // FSUB_S
2989
0
    536894268U, // FSUB_S_MM
2990
0
    570448700U, // FSUB_S_MMR6
2991
0
    536895541U, // FSUB_W
2992
0
    536890431U, // FSUEQ_D
2993
0
    536896166U, // FSUEQ_W
2994
0
    536889846U, // FSULE_D
2995
0
    536895650U, // FSULE_W
2996
0
    536890922U, // FSULT_D
2997
0
    536896745U, // FSULT_W
2998
0
    536889880U, // FSUNE_D
2999
0
    536895684U, // FSUNE_W
3000
0
    536890303U, // FSUN_D
3001
0
    536896055U, // FSUN_W
3002
0
    19821U, // FTINT_S_D
3003
0
    25685U, // FTINT_S_W
3004
0
    20300U, // FTINT_U_D
3005
0
    26115U, // FTINT_U_W
3006
0
    536892037U, // FTQ_H
3007
0
    536896175U, // FTQ_W
3008
0
    19643U, // FTRUNC_S_D
3009
0
    25457U, // FTRUNC_S_W
3010
0
    20110U, // FTRUNC_U_D
3011
0
    25925U, // FTRUNC_U_W
3012
0
    546758U,  // GINVI
3013
0
    546758U,  // GINVI_MMR6
3014
0
    218127986U, // GINVT
3015
0
    218127986U, // GINVT_MMR6
3016
0
    536890567U, // HADD_S_D
3017
0
    536892116U, // HADD_S_H
3018
0
    536896381U, // HADD_S_W
3019
0
    536891034U, // HADD_U_D
3020
0
    536892404U, // HADD_U_H
3021
0
    536896849U, // HADD_U_W
3022
0
    536890534U, // HSUB_S_D
3023
0
    536892095U, // HSUB_S_H
3024
0
    536896348U, // HSUB_S_W
3025
0
    536891001U, // HSUB_U_D
3026
0
    536892383U, // HSUB_U_H
3027
0
    536896816U, // HSUB_U_W
3028
0
    645291U,  // HYPCALL
3029
0
    645291U,  // HYPCALL_MM
3030
0
    536888837U, // ILVEV_B
3031
0
    536891268U, // ILVEV_D
3032
0
    536892626U, // ILVEV_H
3033
0
    536897093U, // ILVEV_W
3034
0
    536888365U, // ILVL_B
3035
0
    536890250U, // ILVL_D
3036
0
    536891952U, // ILVL_H
3037
0
    536896031U, // ILVL_W
3038
0
    536888117U, // ILVOD_B
3039
0
    536889723U, // ILVOD_D
3040
0
    536891754U, // ILVOD_H
3041
0
    536895616U, // ILVOD_W
3042
0
    536888413U, // ILVR_B
3043
0
    536890507U, // ILVR_D
3044
0
    536892077U, // ILVR_H
3045
0
    536896321U, // ILVR_W
3046
0
    536894916U, // INS
3047
0
    241714476U, // INSERT_B
3048
0
    258494020U, // INSERT_D
3049
0
    275272645U, // INSERT_H
3050
0
    292054275U, // INSERT_W
3051
0
    33578991U,  // INSV
3052
0
    308822846U, // INSVE_B
3053
0
    325601825U, // INSVE_D
3054
0
    342380915U, // INSVE_H
3055
0
    359162061U, // INSVE_W
3056
0
    33578991U,  // INSV_MM
3057
0
    536894916U, // INS_MM
3058
0
    536894916U, // INS_MMR6
3059
0
    186317U,  // J
3060
0
    186356U,  // JAL
3061
0
    23264U, // JALR
3062
0
    547552U,  // JALR16_MM
3063
0
    23264U, // JALR64
3064
0
    547552U,  // JALRC16_MMR6
3065
0
    17977U, // JALRC_HB_MMR6
3066
0
    18516U, // JALRC_MMR6
3067
0
    541239U,  // JALRS16_MM
3068
0
    24100U, // JALRS_MM
3069
0
    17994U, // JALR_HB
3070
0
    17994U, // JALR_HB64
3071
0
    23264U, // JALR_MM
3072
0
    187819U,  // JALS_MM
3073
0
    190126U,  // JALX
3074
0
    190126U,  // JALX_MM
3075
0
    186356U,  // JAL_MM
3076
0
    18395U, // JIALC
3077
0
    18395U, // JIALC64
3078
0
    18395U, // JIALC_MMR6
3079
0
    18384U, // JIC
3080
0
    18384U, // JIC64
3081
0
    18384U, // JIC_MMR6
3082
0
    547548U,  // JR
3083
0
    541226U,  // JR16_MM
3084
0
    547548U,  // JR64
3085
0
    547353U,  // JRADDIUSP
3086
0
    542799U,  // JRC16_MM
3087
0
    541104U,  // JRC16_MMR6
3088
0
    547341U,  // JRCADDIUSP_MMR6
3089
0
    542275U,  // JR_HB
3090
0
    542275U,  // JR_HB64
3091
0
    542275U,  // JR_HB64_R6
3092
0
    542275U,  // JR_HB_R6
3093
0
    547548U,  // JR_MM
3094
0
    186317U,  // J_MM
3095
0
    7542772U, // Jal16
3096
0
    8067060U, // JalB16
3097
0
    10524U, // JrRa16
3098
0
    10516U, // JrcRa16
3099
0
    542799U,  // JrcRx16
3100
0
    542804U,  // JumpLinkReg16
3101
0
    50349651U,  // LB
3102
0
    50349651U,  // LB64
3103
0
    50352227U,  // LBE
3104
0
    50352227U,  // LBE_MM
3105
0
    50348615U,  // LBU16_MM
3106
0
    3254806196U,  // LBUX
3107
0
    3254806196U,  // LBUX_MM
3108
0
    50355845U,  // LBU_MMR6
3109
0
    50349651U,  // LB_MM
3110
0
    50349651U,  // LB_MMR6
3111
0
    50355845U,  // LBu
3112
0
    50355845U,  // LBu64
3113
0
    50352363U,  // LBuE
3114
0
    50352363U,  // LBuE_MM
3115
0
    50355845U,  // LBu_MM
3116
0
    50352186U,  // LD
3117
0
    50348118U,  // LDC1
3118
0
    50348118U,  // LDC164
3119
0
    50348118U,  // LDC1_D64_MMR6
3120
0
    50348118U,  // LDC1_MM_D32
3121
0
    50348118U,  // LDC1_MM_D64
3122
0
    50348334U,  // LDC2
3123
0
    50348334U,  // LDC2_MMR6
3124
0
    50348334U,  // LDC2_R6
3125
0
    50348419U,  // LDC3
3126
0
    17248U, // LDI_B
3127
0
    19089U, // LDI_D
3128
0
    20885U, // LDI_H
3129
0
    24912U, // LDI_W
3130
0
    50354256U,  // LDL
3131
0
    18462U, // LDPC
3132
0
    50354842U,  // LDR
3133
0
    3254796438U,  // LDXC1
3134
0
    3254796438U,  // LDXC164
3135
0
    50348838U,  // LD_B
3136
0
    50350444U,  // LD_D
3137
0
    50352475U,  // LD_H
3138
0
    50356337U,  // LD_W
3139
0
    134242016U, // LEA_ADDiu
3140
0
    134242015U, // LEA_ADDiu64
3141
0
    134242016U, // LEA_ADDiu_MM
3142
0
    50353427U,  // LH
3143
0
    50353427U,  // LH64
3144
0
    50352279U,  // LHE
3145
0
    50352279U,  // LHE_MM
3146
0
    50348638U,  // LHU16_MM
3147
0
    3254806185U,  // LHX
3148
0
    3254806185U,  // LHX_MM
3149
0
    50353427U,  // LH_MM
3150
0
    50355923U,  // LHu
3151
0
    50355923U,  // LHu64
3152
0
    50352369U,  // LHuE
3153
0
    50352369U,  // LHuE_MM
3154
0
    50355923U,  // LHu_MM
3155
0
    16878U, // LI16_MM
3156
0
    16878U, // LI16_MMR6
3157
0
    50354352U,  // LL
3158
0
    50354352U,  // LL64
3159
0
    50354352U,  // LL64_R6
3160
0
    50352190U,  // LLD
3161
0
    50352190U,  // LLD_R6
3162
0
    50352302U,  // LLE
3163
0
    50352302U,  // LLE_MM
3164
0
    50354352U,  // LL_MM
3165
0
    50354352U,  // LL_MMR6
3166
0
    50354352U,  // LL_R6
3167
0
    536888020U, // LSA
3168
0
    3828450004U,  // LSA_MMR6
3169
0
    536888020U, // LSA_R6
3170
0
    201349057U, // LUI_MMR6
3171
0
    3254796452U,  // LUXC1
3172
0
    3254796452U,  // LUXC164
3173
0
    3254796452U,  // LUXC1_MM
3174
0
    201349057U, // LUi
3175
0
    201349057U, // LUi64
3176
0
    201349057U, // LUi_MM
3177
0
    50357902U,  // LW
3178
0
    50348645U,  // LW16_MM
3179
0
    50357902U,  // LW64
3180
0
    50348170U,  // LWC1
3181
0
    50348170U,  // LWC1_MM
3182
0
    50348386U,  // LWC2
3183
0
    50348386U,  // LWC2_MMR6
3184
0
    50348386U,  // LWC2_R6
3185
0
    50348431U,  // LWC3
3186
0
    50357902U,  // LWDSP
3187
0
    50357902U,  // LWDSP_MM
3188
0
    50352381U,  // LWE
3189
0
    50352381U,  // LWE_MM
3190
0
    50357902U,  // LWGP_MM
3191
0
    50354470U,  // LWL
3192
0
    50354470U,  // LWL64
3193
0
    50352312U,  // LWLE
3194
0
    50352312U,  // LWLE_MM
3195
0
    50354470U,  // LWL_MM
3196
0
    66059U, // LWM16_MM
3197
0
    66059U, // LWM16_MMR6
3198
0
    65799U, // LWM32_MM
3199
0
    18499U, // LWPC
3200
0
    18499U, // LWPC_MMR6
3201
0
    369121850U, // LWP_MM
3202
0
    50354976U,  // LWR
3203
0
    50354976U,  // LWR64
3204
0
    50352351U,  // LWRE
3205
0
    50352351U,  // LWRE_MM
3206
0
    50354976U,  // LWR_MM
3207
0
    50357902U,  // LWSP_MM
3208
0
    18492U, // LWUPC
3209
0
    50356070U,  // LWU_MM
3210
0
    3254806202U,  // LWX
3211
0
    3254796466U,  // LWXC1
3212
0
    3254796466U,  // LWXC1_MM
3213
0
    3254804017U,  // LWXS_MM
3214
0
    3254806202U,  // LWX_MM
3215
0
    50357902U,  // LW_MM
3216
0
    50357902U,  // LW_MMR6
3217
0
    50356070U,  // LWu
3218
0
    50349651U,  // LbRxRyOffMemX16
3219
0
    50355845U,  // LbuRxRyOffMemX16
3220
0
    50353427U,  // LhRxRyOffMemX16
3221
0
    50355923U,  // LhuRxRyOffMemX16
3222
0
    1610635144U,  // LiRxImm16
3223
0
    22398U, // LiRxImmAlignX16
3224
0
    22408U, // LiRxImmX16
3225
0
    26254U, // LwRxPcTcp16
3226
0
    26254U, // LwRxPcTcpX16
3227
0
    50357902U,  // LwRxRyOffMemX16
3228
0
    50357902U,  // LwRxSpImmX16
3229
0
    20523U, // MADD
3230
0
    570444383U, // MADDF_D
3231
0
    570444383U, // MADDF_D_MMR6
3232
0
    570448851U, // MADDF_S
3233
0
    570448851U, // MADDF_S_MMR6
3234
0
    570446441U, // MADDR_Q_H
3235
0
    570450552U, // MADDR_Q_W
3236
0
    24230U, // MADDU
3237
0
    536895142U, // MADDU_DSP
3238
0
    536895142U, // MADDU_DSP_MM
3239
0
    24230U, // MADDU_MM
3240
0
    570443251U, // MADDV_B
3241
0
    570445682U, // MADDV_D
3242
0
    570447040U, // MADDV_H
3243
0
    570451507U, // MADDV_W
3244
0
    536889690U, // MADD_D32
3245
0
    536889690U, // MADD_D32_MM
3246
0
    536889690U, // MADD_D64
3247
0
    536891435U, // MADD_DSP
3248
0
    536891435U, // MADD_DSP_MM
3249
0
    20523U, // MADD_MM
3250
0
    570446411U, // MADD_Q_H
3251
0
    570450522U, // MADD_Q_W
3252
0
    536894285U, // MADD_S
3253
0
    536894285U, // MADD_S_MM
3254
0
    536893555U, // MAQ_SA_W_PHL
3255
0
    536893555U, // MAQ_SA_W_PHL_MM
3256
0
    536894116U, // MAQ_SA_W_PHR
3257
0
    536894116U, // MAQ_SA_W_PHR_MM
3258
0
    536893583U, // MAQ_S_W_PHL
3259
0
    536893583U, // MAQ_S_W_PHL_MM
3260
0
    536894144U, // MAQ_S_W_PHR
3261
0
    536894144U, // MAQ_S_W_PHR_MM
3262
0
    536889631U, // MAXA_D
3263
0
    536889631U, // MAXA_D_MMR6
3264
0
    536894258U, // MAXA_S
3265
0
    536894258U, // MAXA_S_MMR6
3266
0
    536888488U, // MAXI_S_B
3267
0
    536890645U, // MAXI_S_D
3268
0
    536892194U, // MAXI_S_H
3269
0
    536896459U, // MAXI_S_W
3270
0
    536888703U, // MAXI_U_B
3271
0
    536891112U, // MAXI_U_D
3272
0
    536892482U, // MAXI_U_H
3273
0
    536896927U, // MAXI_U_W
3274
0
    536888069U, // MAX_A_B
3275
0
    536889607U, // MAX_A_D
3276
0
    536891706U, // MAX_A_H
3277
0
    536895525U, // MAX_A_W
3278
0
    536891353U, // MAX_D
3279
0
    536891353U, // MAX_D_MMR6
3280
0
    536894851U, // MAX_S
3281
0
    536888576U, // MAX_S_B
3282
0
    536890765U, // MAX_S_D
3283
0
    536892313U, // MAX_S_H
3284
0
    536894851U, // MAX_S_MMR6
3285
0
    536896640U, // MAX_S_W
3286
0
    536888791U, // MAX_U_B
3287
0
    536891232U, // MAX_U_D
3288
0
    536892580U, // MAX_U_H
3289
0
    536897047U, // MAX_U_W
3290
0
    536887298U, // MFC0
3291
0
    536887298U, // MFC0_MMR6
3292
0
    16489U, // MFC1
3293
0
    16489U, // MFC1_D64
3294
0
    16489U, // MFC1_MM
3295
0
    16489U, // MFC1_MMR6
3296
0
    536887617U, // MFC2
3297
0
    16705U, // MFC2_MMR6
3298
0
    536887305U, // MFGC0
3299
0
    536887305U, // MFGC0_MM
3300
0
    536887336U, // MFHC0_MMR6
3301
0
    16495U, // MFHC1_D32
3302
0
    16495U, // MFHC1_D32_MM
3303
0
    16495U, // MFHC1_D64
3304
0
    16495U, // MFHC1_D64_MM
3305
0
    16711U, // MFHC2_MMR6
3306
0
    536887312U, // MFHGC0
3307
0
    536887312U, // MFHGC0_MM
3308
0
    546674U,  // MFHI
3309
0
    541158U,  // MFHI16_MM
3310
0
    546674U,  // MFHI64
3311
0
    22386U, // MFHI_DSP
3312
0
    22386U, // MFHI_DSP_MM
3313
0
    546674U,  // MFHI_MM
3314
0
    547206U,  // MFLO
3315
0
    541209U,  // MFLO16_MM
3316
0
    547206U,  // MFLO64
3317
0
    22918U, // MFLO_DSP
3318
0
    22918U, // MFLO_DSP_MM
3319
0
    547206U,  // MFLO_MM
3320
0
    536894214U, // MFTR
3321
0
    536889616U, // MINA_D
3322
0
    536889616U, // MINA_D_MMR6
3323
0
    536894250U, // MINA_S
3324
0
    536894250U, // MINA_S_MMR6
3325
0
    536888468U, // MINI_S_B
3326
0
    536890625U, // MINI_S_D
3327
0
    536892174U, // MINI_S_H
3328
0
    536896439U, // MINI_S_W
3329
0
    536888683U, // MINI_U_B
3330
0
    536891092U, // MINI_U_D
3331
0
    536892462U, // MINI_U_H
3332
0
    536896907U, // MINI_U_W
3333
0
    536888050U, // MIN_A_B
3334
0
    536889587U, // MIN_A_D
3335
0
    536891687U, // MIN_A_H
3336
0
    536895505U, // MIN_A_W
3337
0
    536890259U, // MIN_D
3338
0
    536890259U, // MIN_D_MMR6
3339
0
    536894532U, // MIN_S
3340
0
    536888498U, // MIN_S_B
3341
0
    536890655U, // MIN_S_D
3342
0
    536892204U, // MIN_S_H
3343
0
    536894532U, // MIN_S_MMR6
3344
0
    536896479U, // MIN_S_W
3345
0
    536888713U, // MIN_U_B
3346
0
    536891122U, // MIN_U_D
3347
0
    536892492U, // MIN_U_H
3348
0
    536896937U, // MIN_U_W
3349
0
    536891482U, // MOD
3350
0
    536889255U, // MODSUB
3351
0
    536889255U, // MODSUB_MM
3352
0
    536895150U, // MODU
3353
0
    536895150U, // MODU_MMR6
3354
0
    536891482U, // MOD_MMR6
3355
0
    536888431U, // MOD_S_B
3356
0
    536890588U, // MOD_S_D
3357
0
    536892137U, // MOD_S_H
3358
0
    536896402U, // MOD_S_W
3359
0
    536888646U, // MOD_U_B
3360
0
    536891055U, // MOD_U_D
3361
0
    536892425U, // MOD_U_H
3362
0
    536896870U, // MOD_U_W
3363
0
    20727U, // MOVE16_MM
3364
0
    16848U, // MOVE16_MMR6
3365
0
    536893881U, // MOVEP_MM
3366
0
    536893881U, // MOVEP_MMR6
3367
0
    24434U, // MOVE_V
3368
0
    536889976U, // MOVF_D32
3369
0
    536889976U, // MOVF_D32_MM
3370
0
    536889976U, // MOVF_D64
3371
0
    536891667U, // MOVF_I
3372
0
    536891667U, // MOVF_I64
3373
0
    536891667U, // MOVF_I_MM
3374
0
    536894436U, // MOVF_S
3375
0
    536894436U, // MOVF_S_MM
3376
0
    536890311U, // MOVN_I64_D64
3377
0
    536893818U, // MOVN_I64_I
3378
0
    536893818U, // MOVN_I64_I64
3379
0
    536894568U, // MOVN_I64_S
3380
0
    536890311U, // MOVN_I_D32
3381
0
    536890311U, // MOVN_I_D32_MM
3382
0
    536890311U, // MOVN_I_D64
3383
0
    536893818U, // MOVN_I_I
3384
0
    536893818U, // MOVN_I_I64
3385
0
    536893818U, // MOVN_I_MM
3386
0
    536894568U, // MOVN_I_S
3387
0
    536894568U, // MOVN_I_S_MM
3388
0
    536890983U, // MOVT_D32
3389
0
    536890983U, // MOVT_D32_MM
3390
0
    536890983U, // MOVT_D64
3391
0
    536895097U, // MOVT_I
3392
0
    536895097U, // MOVT_I64
3393
0
    536895097U, // MOVT_I_MM
3394
0
    536894777U, // MOVT_S
3395
0
    536894777U, // MOVT_S_MM
3396
0
    536891393U, // MOVZ_I64_D64
3397
0
    536897287U, // MOVZ_I64_I
3398
0
    536897287U, // MOVZ_I64_I64
3399
0
    536894878U, // MOVZ_I64_S
3400
0
    536891393U, // MOVZ_I_D32
3401
0
    536891393U, // MOVZ_I_D32_MM
3402
0
    536891393U, // MOVZ_I_D64
3403
0
    536897287U, // MOVZ_I_I
3404
0
    536897287U, // MOVZ_I_I64
3405
0
    536897287U, // MOVZ_I_MM
3406
0
    536894878U, // MOVZ_I_S
3407
0
    536894878U, // MOVZ_I_S_MM
3408
0
    18351U, // MSUB
3409
0
    570444374U, // MSUBF_D
3410
0
    570444374U, // MSUBF_D_MMR6
3411
0
    570448842U, // MSUBF_S
3412
0
    570448842U, // MSUBF_S_MMR6
3413
0
    570446430U, // MSUBR_Q_H
3414
0
    570450541U, // MSUBR_Q_W
3415
0
    24209U, // MSUBU
3416
0
    536895121U, // MSUBU_DSP
3417
0
    536895121U, // MSUBU_DSP_MM
3418
0
    24209U, // MSUBU_MM
3419
0
    570443242U, // MSUBV_B
3420
0
    570445673U, // MSUBV_D
3421
0
    570447031U, // MSUBV_H
3422
0
    570451498U, // MSUBV_W
3423
0
    536889648U, // MSUB_D32
3424
0
    536889648U, // MSUB_D32_MM
3425
0
    536889648U, // MSUB_D64
3426
0
    536889263U, // MSUB_DSP
3427
0
    536889263U, // MSUB_DSP_MM
3428
0
    18351U, // MSUB_MM
3429
0
    570446401U, // MSUB_Q_H
3430
0
    570450512U, // MSUB_Q_W
3431
0
    536894267U, // MSUB_S
3432
0
    536894267U, // MSUB_S_MM
3433
0
    2752561207U,  // MTC0
3434
0
    2752561207U,  // MTC0_MMR6
3435
0
    17875076U,  // MTC1
3436
0
    17875076U,  // MTC1_D64
3437
0
    17875076U,  // MTC1_D64_MM
3438
0
    17875076U,  // MTC1_MM
3439
0
    17875076U,  // MTC1_MMR6
3440
0
    2752561500U,  // MTC2
3441
0
    17875292U,  // MTC2_MMR6
3442
0
    2752561185U,  // MTGC0
3443
0
    2752561185U,  // MTGC0_MM
3444
0
    2752561199U,  // MTHC0_MMR6
3445
0
    17924214U,  // MTHC1_D32
3446
0
    17924214U,  // MTHC1_D32_MM
3447
0
    17924214U,  // MTHC1_D64
3448
0
    17924214U,  // MTHC1_D64_MM
3449
0
    17875278U,  // MTHC2_MMR6
3450
0
    2752561176U,  // MTHGC0
3451
0
    2752561176U,  // MTHGC0_MM
3452
0
    546680U,  // MTHI
3453
0
    546680U,  // MTHI64
3454
0
    17880952U,  // MTHI_DSP
3455
0
    17880952U,  // MTHI_DSP_MM
3456
0
    546680U,  // MTHI_MM
3457
0
    17881536U,  // MTHLIP
3458
0
    17881536U,  // MTHLIP_MM
3459
0
    547219U,  // MTLO
3460
0
    547219U,  // MTLO64
3461
0
    17881491U,  // MTLO_DSP
3462
0
    17881491U,  // MTLO_DSP_MM
3463
0
    547219U,  // MTLO_MM
3464
0
    540739U,  // MTM0
3465
0
    540864U,  // MTM1
3466
0
    541038U,  // MTM2
3467
0
    540745U,  // MTP0
3468
0
    540870U,  // MTP1
3469
0
    541044U,  // MTP2
3470
0
    68213523U,  // MTTR
3471
0
    536893249U, // MUH
3472
0
    536895193U, // MUHU
3473
0
    536895193U, // MUHU_MMR6
3474
0
    536893249U, // MUH_MMR6
3475
0
    536893715U, // MUL
3476
0
    536893596U, // MULEQ_S_W_PHL
3477
0
    536893596U, // MULEQ_S_W_PHL_MM
3478
0
    536894157U, // MULEQ_S_W_PHR
3479
0
    536894157U, // MULEQ_S_W_PHR_MM
3480
0
    536893473U, // MULEU_S_PH_QBL
3481
0
    536893473U, // MULEU_S_PH_QBL_MM
3482
0
    536894059U, // MULEU_S_PH_QBR
3483
0
    536894059U, // MULEU_S_PH_QBR_MM
3484
0
    536893009U, // MULQ_RS_PH
3485
0
    536893009U, // MULQ_RS_PH_MM
3486
0
    536896659U, // MULQ_RS_W
3487
0
    536896659U, // MULQ_RS_W_MMR2
3488
0
    536892953U, // MULQ_S_PH
3489
0
    536892953U, // MULQ_S_PH_MMR2
3490
0
    536896518U, // MULQ_S_W
3491
0
    536896518U, // MULQ_S_W_MMR2
3492
0
    536894976U, // MULR_PS64
3493
0
    536892020U, // MULR_Q_H
3494
0
    536896131U, // MULR_Q_W
3495
0
    536893155U, // MULSAQ_S_W_PH
3496
0
    536893155U, // MULSAQ_S_W_PH_MM
3497
0
    536893130U, // MULSA_W_PH
3498
0
    536893130U, // MULSA_W_PH_MMR2
3499
0
    24157U, // MULT
3500
0
    536895313U, // MULTU_DSP
3501
0
    536895313U, // MULTU_DSP_MM
3502
0
    536895069U, // MULT_DSP
3503
0
    536895069U, // MULT_DSP_MM
3504
0
    24157U, // MULT_MM
3505
0
    24401U, // MULTu
3506
0
    24401U, // MULTu_MM
3507
0
    536895230U, // MULU
3508
0
    536895230U, // MULU_MMR6
3509
0
    536888846U, // MULV_B
3510
0
    536891285U, // MULV_D
3511
0
    536892635U, // MULV_H
3512
0
    536897110U, // MULV_W
3513
0
    536893715U, // MUL_MM
3514
0
    536893715U, // MUL_MMR6
3515
0
    536892826U, // MUL_PH
3516
0
    536892826U, // MUL_PH_MMR2
3517
0
    536891989U, // MUL_Q_H
3518
0
    536896100U, // MUL_Q_W
3519
0
    536893715U, // MUL_R6
3520
0
    536892921U, // MUL_S_PH
3521
0
    536892921U, // MUL_S_PH_MMR2
3522
0
    546674U,  // Mfhi16
3523
0
    547206U,  // Mflo16
3524
0
    20727U, // Move32R16
3525
0
    20727U, // MoveR3216
3526
0
    17173U, // NLOC_B
3527
0
    18753U, // NLOC_D
3528
0
    20810U, // NLOC_H
3529
0
    24646U, // NLOC_W
3530
0
    17181U, // NLZC_B
3531
0
    18761U, // NLZC_D
3532
0
    20818U, // NLZC_H
3533
0
    24654U, // NLZC_W
3534
0
    536889698U, // NMADD_D32
3535
0
    536889698U, // NMADD_D32_MM
3536
0
    536889698U, // NMADD_D64
3537
0
    536894284U, // NMADD_S
3538
0
    536894284U, // NMADD_S_MM
3539
0
    536889656U, // NMSUB_D32
3540
0
    536889656U, // NMSUB_D32_MM
3541
0
    536889656U, // NMSUB_D64
3542
0
    536894266U, // NMSUB_S
3543
0
    536894266U, // NMSUB_S_MM
3544
0
    536894182U, // NOR
3545
0
    536894182U, // NOR64
3546
0
    536888254U, // NORI_B
3547
0
    536894182U, // NOR_MM
3548
0
    536894182U, // NOR_MMR6
3549
0
    536895362U, // NOR_V
3550
0
    16960U, // NOT16_MM
3551
0
    16960U, // NOT16_MMR6
3552
0
    20761U, // NegRxRy16
3553
0
    24173U, // NotRxRy16
3554
0
    536894183U, // OR
3555
0
    20021809U,  // OR16_MM
3556
0
    20021809U,  // OR16_MMR6
3557
0
    536894183U, // OR64
3558
0
    536888255U, // ORI_B
3559
0
    536893348U, // ORI_MMR6
3560
0
    536894183U, // OR_MM
3561
0
    536894183U, // OR_MMR6
3562
0
    536895363U, // OR_V
3563
0
    536893348U, // ORi
3564
0
    536893348U, // ORi64
3565
0
    536893348U, // ORi_MM
3566
0
    33577703U,  // OrRxRxRy16
3567
0
    536892815U, // PACKRL_PH
3568
0
    536892815U, // PACKRL_PH_MM
3569
0
    10542U, // PAUSE
3570
0
    10542U, // PAUSE_MM
3571
0
    10542U, // PAUSE_MMR6
3572
0
    536888828U, // PCKEV_B
3573
0
    536891259U, // PCKEV_D
3574
0
    536892617U, // PCKEV_H
3575
0
    536897084U, // PCKEV_W
3576
0
    536888108U, // PCKOD_B
3577
0
    536889714U, // PCKOD_D
3578
0
    536891745U, // PCKOD_H
3579
0
    536895607U, // PCKOD_W
3580
0
    17700U, // PCNT_B
3581
0
    20019U, // PCNT_D
3582
0
    21437U, // PCNT_H
3583
0
    25842U, // PCNT_W
3584
0
    536892779U, // PICK_PH
3585
0
    536892779U, // PICK_PH_MM
3586
0
    536888987U, // PICK_QB
3587
0
    536888987U, // PICK_QB_MM
3588
0
    536894943U, // PLL_PS64
3589
0
    536894985U, // PLU_PS64
3590
0
    22990U, // POP
3591
0
    22592U, // PRECEQU_PH_QBL
3592
0
    17046U, // PRECEQU_PH_QBLA
3593
0
    17046U, // PRECEQU_PH_QBLA_MM
3594
0
    22592U, // PRECEQU_PH_QBL_MM
3595
0
    23178U, // PRECEQU_PH_QBR
3596
0
    17084U, // PRECEQU_PH_QBRA
3597
0
    17084U, // PRECEQU_PH_QBRA_MM
3598
0
    23178U, // PRECEQU_PH_QBR_MM
3599
0
    22657U, // PRECEQ_W_PHL
3600
0
    22657U, // PRECEQ_W_PHL_MM
3601
0
    23218U, // PRECEQ_W_PHR
3602
0
    23218U, // PRECEQ_W_PHR_MM
3603
0
    22577U, // PRECEU_PH_QBL
3604
0
    17030U, // PRECEU_PH_QBLA
3605
0
    17030U, // PRECEU_PH_QBLA_MM
3606
0
    22577U, // PRECEU_PH_QBL_MM
3607
0
    23163U, // PRECEU_PH_QBR
3608
0
    17068U, // PRECEU_PH_QBRA
3609
0
    17068U, // PRECEU_PH_QBRA_MM
3610
0
    23163U, // PRECEU_PH_QBR_MM
3611
0
    536892731U, // PRECRQU_S_QB_PH
3612
0
    536892731U, // PRECRQU_S_QB_PH_MM
3613
0
    536895750U, // PRECRQ_PH_W
3614
0
    536895750U, // PRECRQ_PH_W_MM
3615
0
    536892704U, // PRECRQ_QB_PH
3616
0
    536892704U, // PRECRQ_QB_PH_MM
3617
0
    536895781U, // PRECRQ_RS_PH_W
3618
0
    536895781U, // PRECRQ_RS_PH_W_MM
3619
0
    536892718U, // PRECR_QB_PH
3620
0
    536892718U, // PRECR_QB_PH_MMR2
3621
0
    536895734U, // PRECR_SRA_PH_W
3622
0
    536895734U, // PRECR_SRA_PH_W_MMR2
3623
0
    536895763U, // PRECR_SRA_R_PH_W
3624
0
    536895763U, // PRECR_SRA_R_PH_W_MMR2
3625
0
    5394701U, // PREF
3626
0
    5394554U, // PREFE
3627
0
    5394554U, // PREFE_MM
3628
0
    389179042U, // PREFX_MM
3629
0
    5394701U, // PREF_MM
3630
0
    5394701U, // PREF_MMR6
3631
0
    5394701U, // PREF_R6
3632
0
    536891464U, // PREPEND
3633
0
    536891464U, // PREPEND_MMR2
3634
0
    536894959U, // PUL_PS64
3635
0
    536894993U, // PUU_PS64
3636
0
    18327U, // RADDU_W_QB
3637
0
    18327U, // RADDU_W_QB_MM
3638
0
    184572415U, // RDDSP
3639
0
    402676223U, // RDDSP_MM
3640
0
    536894233U, // RDHWR
3641
0
    536894233U, // RDHWR64
3642
0
    536894233U, // RDHWR_MM
3643
0
    536894233U, // RDHWR_MMR6
3644
0
    23286U, // RDPGPR_MMR6
3645
0
    19415U, // RECIP_D32
3646
0
    19415U, // RECIP_D32_MM
3647
0
    19415U, // RECIP_D64
3648
0
    19415U, // RECIP_D64_MM
3649
0
    23664U, // RECIP_S
3650
0
    23664U, // RECIP_S_MM
3651
0
    22158U, // REPLV_PH
3652
0
    22158U, // REPLV_PH_MM
3653
0
    18307U, // REPLV_QB
3654
0
    18307U, // REPLV_QB_MM
3655
0
    21885U, // REPL_PH
3656
0
    21885U, // REPL_PH_MM
3657
0
    419448493U, // REPL_QB
3658
0
    419448493U, // REPL_QB_MM
3659
0
    20028U, // RINT_D
3660
0
    20028U, // RINT_D_MMR6
3661
0
    23848U, // RINT_S
3662
0
    23848U, // RINT_S_MMR6
3663
0
    536894221U, // ROTR
3664
0
    536895464U, // ROTRV
3665
0
    536895464U, // ROTRV_MM
3666
0
    536894221U, // ROTR_MM
3667
0
    19224U, // ROUND_L_D64
3668
0
    19224U, // ROUND_L_D_MMR6
3669
0
    23556U, // ROUND_L_S
3670
0
    23556U, // ROUND_L_S_MMR6
3671
0
    20399U, // ROUND_W_D32
3672
0
    20399U, // ROUND_W_D64
3673
0
    20399U, // ROUND_W_D_MMR6
3674
0
    20399U, // ROUND_W_MM
3675
0
    23898U, // ROUND_W_S
3676
0
    23898U, // ROUND_W_S_MM
3677
0
    23898U, // ROUND_W_S_MMR6
3678
0
    20056U, // RSQRT_D32
3679
0
    20056U, // RSQRT_D32_MM
3680
0
    20056U, // RSQRT_D64
3681
0
    20056U, // RSQRT_D64_MM
3682
0
    23856U, // RSQRT_S
3683
0
    23856U, // RSQRT_S_MM
3684
0
    0U, // Restore16
3685
0
    0U, // RestoreX16
3686
0
    8405633U, // SAA
3687
0
    8409105U, // SAAD
3688
0
    536888537U, // SAT_S_B
3689
0
    536890704U, // SAT_S_D
3690
0
    536892263U, // SAT_S_H
3691
0
    536896568U, // SAT_S_W
3692
0
    536888764U, // SAT_U_B
3693
0
    536891183U, // SAT_U_D
3694
0
    536892553U, // SAT_U_H
3695
0
    536896998U, // SAT_U_W
3696
0
    50349987U,  // SB
3697
0
    50348452U,  // SB16_MM
3698
0
    50348452U,  // SB16_MMR6
3699
0
    50349987U,  // SB64
3700
0
    50352232U,  // SBE
3701
0
    50352232U,  // SBE_MM
3702
0
    50349987U,  // SB_MM
3703
0
    50349987U,  // SB_MMR6
3704
0
    8964190U, // SC
3705
0
    8964190U, // SC64
3706
0
    8964190U, // SC64_R6
3707
0
    8966176U, // SCD
3708
0
    8966176U, // SCD_R6
3709
0
    8966253U, // SCE
3710
0
    8966253U, // SCE_MM
3711
0
    8964190U, // SC_MM
3712
0
    8964190U, // SC_MMR6
3713
0
    8964190U, // SC_R6
3714
0
    50352223U,  // SD
3715
0
    219562U,  // SDBBP
3716
0
    131617U,  // SDBBP16_MM
3717
0
    131617U,  // SDBBP16_MMR6
3718
0
    645546U,  // SDBBP_MM
3719
0
    219562U,  // SDBBP_MMR6
3720
0
    219562U,  // SDBBP_R6
3721
0
    50348124U,  // SDC1
3722
0
    50348124U,  // SDC164
3723
0
    50348124U,  // SDC1_D64_MMR6
3724
0
    50348124U,  // SDC1_MM_D32
3725
0
    50348124U,  // SDC1_MM_D64
3726
0
    50348340U,  // SDC2
3727
0
    50348340U,  // SDC2_MMR6
3728
0
    50348340U,  // SDC2_R6
3729
0
    50348425U,  // SDC3
3730
0
    26408U, // SDIV
3731
0
    26408U, // SDIV_MM
3732
0
    50354261U,  // SDL
3733
0
    50354847U,  // SDR
3734
0
    3254796445U,  // SDXC1
3735
0
    3254796445U,  // SDXC164
3736
0
    17972U, // SEB
3737
0
    17972U, // SEB64
3738
0
    17972U, // SEB_MM
3739
0
    21773U, // SEH
3740
0
    21773U, // SEH64
3741
0
    21773U, // SEH_MM
3742
0
    536897260U, // SELEQZ
3743
0
    536897260U, // SELEQZ64
3744
0
    536891383U, // SELEQZ_D
3745
0
    536891383U, // SELEQZ_D_MMR6
3746
0
    536897260U, // SELEQZ_MMR6
3747
0
    536894868U, // SELEQZ_S
3748
0
    536894868U, // SELEQZ_S_MMR6
3749
0
    536897233U, // SELNEZ
3750
0
    536897233U, // SELNEZ64
3751
0
    536891366U, // SELNEZ_D
3752
0
    536891366U, // SELNEZ_D_MMR6
3753
0
    536897233U, // SELNEZ_MMR6
3754
0
    536894858U, // SELNEZ_S
3755
0
    536894858U, // SELNEZ_S_MMR6
3756
0
    570444609U, // SEL_D
3757
0
    570444609U, // SEL_D_MMR6
3758
0
    570448941U, // SEL_S
3759
0
    570448941U, // SEL_S_MMR6
3760
0
    536894025U, // SEQ
3761
0
    536893335U, // SEQi
3762
0
    50353980U,  // SH
3763
0
    50348504U,  // SH16_MM
3764
0
    50348504U,  // SH16_MMR6
3765
0
    50353980U,  // SH64
3766
0
    50352284U,  // SHE
3767
0
    50352284U,  // SHE_MM
3768
0
    536888136U, // SHF_B
3769
0
    536891773U, // SHF_H
3770
0
    536895719U, // SHF_W
3771
0
    22924U, // SHILO
3772
0
    24527U, // SHILOV
3773
0
    24527U, // SHILOV_MM
3774
0
    22924U, // SHILO_MM
3775
0
    536893060U, // SHLLV_PH
3776
0
    536893060U, // SHLLV_PH_MM
3777
0
    536889209U, // SHLLV_QB
3778
0
    536889209U, // SHLLV_QB_MM
3779
0
    536892997U, // SHLLV_S_PH
3780
0
    536892997U, // SHLLV_S_PH_MM
3781
0
    536896629U, // SHLLV_S_W
3782
0
    536896629U, // SHLLV_S_W_MM
3783
0
    536892788U, // SHLL_PH
3784
0
    536892788U, // SHLL_PH_MM
3785
0
    536888996U, // SHLL_QB
3786
0
    536888996U, // SHLL_QB_MM
3787
0
    536892910U, // SHLL_S_PH
3788
0
    536892910U, // SHLL_S_PH_MM
3789
0
    536896469U, // SHLL_S_W
3790
0
    536896469U, // SHLL_S_W_MM
3791
0
    536893050U, // SHRAV_PH
3792
0
    536893050U, // SHRAV_PH_MM
3793
0
    536889199U, // SHRAV_QB
3794
0
    536889199U, // SHRAV_QB_MMR2
3795
0
    536892898U, // SHRAV_R_PH
3796
0
    536892898U, // SHRAV_R_PH_MM
3797
0
    536889097U, // SHRAV_R_QB
3798
0
    536889097U, // SHRAV_R_QB_MMR2
3799
0
    536896224U, // SHRAV_R_W
3800
0
    536896224U, // SHRAV_R_W_MM
3801
0
    536892695U, // SHRA_PH
3802
0
    536892695U, // SHRA_PH_MM
3803
0
    536888919U, // SHRA_QB
3804
0
    536888919U, // SHRA_QB_MMR2
3805
0
    536892863U, // SHRA_R_PH
3806
0
    536892863U, // SHRA_R_PH_MM
3807
0
    536889062U, // SHRA_R_QB
3808
0
    536889062U, // SHRA_R_QB_MMR2
3809
0
    536896182U, // SHRA_R_W
3810
0
    536896182U, // SHRA_R_W_MM
3811
0
    536893080U, // SHRLV_PH
3812
0
    536893080U, // SHRLV_PH_MMR2
3813
0
    536889229U, // SHRLV_QB
3814
0
    536889229U, // SHRLV_QB_MM
3815
0
    536892806U, // SHRL_PH
3816
0
    536892806U, // SHRL_PH_MMR2
3817
0
    536889014U, // SHRL_QB
3818
0
    536889014U, // SHRL_QB_MM
3819
0
    50353980U,  // SH_MM
3820
0
    50353980U,  // SH_MMR6
3821
0
    233633U,  // SIGRIE
3822
0
    233633U,  // SIGRIE_MMR6
3823
0
    1107313503U,  // SLDI_B
3824
0
    1107315344U,  // SLDI_D
3825
0
    1107317140U,  // SLDI_H
3826
0
    1107321167U,  // SLDI_W
3827
0
    1107313445U,  // SLD_B
3828
0
    1107315051U,  // SLD_D
3829
0
    1107317082U,  // SLD_H
3830
0
    1107320944U,  // SLD_W
3831
0
    536893648U, // SLL
3832
0
    536887805U, // SLL16_MM
3833
0
    536887805U, // SLL16_MMR6
3834
0
    536893648U, // SLL64_32
3835
0
    536893648U, // SLL64_64
3836
0
    536888193U, // SLLI_B
3837
0
    536890017U, // SLLI_D
3838
0
    536891813U, // SLLI_H
3839
0
    536895840U, // SLLI_W
3840
0
    536895426U, // SLLV
3841
0
    536895426U, // SLLV_MM
3842
0
    536888342U, // SLL_B
3843
0
    536890201U, // SLL_D
3844
0
    536891929U, // SLL_H
3845
0
    536893648U, // SLL_MM
3846
0
    536893648U, // SLL_MMR6
3847
0
    536895982U, // SLL_W
3848
0
    536895058U, // SLT
3849
0
    536895058U, // SLT64
3850
0
    536895058U, // SLT_MM
3851
0
    536893359U, // SLTi
3852
0
    536893359U, // SLTi64
3853
0
    536893359U, // SLTi_MM
3854
0
    536895214U, // SLTiu
3855
0
    536895214U, // SLTiu64
3856
0
    536895214U, // SLTiu_MM
3857
0
    536895300U, // SLTu
3858
0
    536895300U, // SLTu64
3859
0
    536895300U, // SLTu_MM
3860
0
    536891593U, // SNE
3861
0
    536893280U, // SNEi
3862
0
    1073759192U,  // SPLATI_B
3863
0
    1073761000U,  // SPLATI_D
3864
0
    1073762796U,  // SPLATI_H
3865
0
    1073766823U,  // SPLATI_W
3866
0
    1073759507U,  // SPLAT_B
3867
0
    1073761713U,  // SPLAT_D
3868
0
    1073763244U,  // SPLAT_H
3869
0
    1073767615U,  // SPLAT_W
3870
0
    536888014U, // SRA
3871
0
    536888151U, // SRAI_B
3872
0
    536889992U, // SRAI_D
3873
0
    536891788U, // SRAI_H
3874
0
    536895815U, // SRAI_W
3875
0
    536888227U, // SRARI_B
3876
0
    536890051U, // SRARI_D
3877
0
    536891847U, // SRARI_H
3878
0
    536895874U, // SRARI_W
3879
0
    536888380U, // SRAR_B
3880
0
    536890440U, // SRAR_D
3881
0
    536892044U, // SRAR_H
3882
0
    536896246U, // SRAR_W
3883
0
    536895405U, // SRAV
3884
0
    536895405U, // SRAV_MM
3885
0
    536888078U, // SRA_B
3886
0
    536889624U, // SRA_D
3887
0
    536891715U, // SRA_H
3888
0
    536888014U, // SRA_MM
3889
0
    536895534U, // SRA_W
3890
0
    536893676U, // SRL
3891
0
    536887812U, // SRL16_MM
3892
0
    536887812U, // SRL16_MMR6
3893
0
    536888201U, // SRLI_B
3894
0
    536890025U, // SRLI_D
3895
0
    536891821U, // SRLI_H
3896
0
    536895848U, // SRLI_W
3897
0
    536888245U, // SRLRI_B
3898
0
    536890069U, // SRLRI_D
3899
0
    536891865U, // SRLRI_H
3900
0
    536895892U, // SRLRI_W
3901
0
    536888396U, // SRLR_B
3902
0
    536890456U, // SRLR_D
3903
0
    536892060U, // SRLR_H
3904
0
    536896262U, // SRLR_W
3905
0
    536895433U, // SRLV
3906
0
    536895433U, // SRLV_MM
3907
0
    536888349U, // SRL_B
3908
0
    536890226U, // SRL_D
3909
0
    536891936U, // SRL_H
3910
0
    536893676U, // SRL_MM
3911
0
    536896007U, // SRL_W
3912
0
    10607U, // SSNOP
3913
0
    10607U, // SSNOP_MM
3914
0
    10607U, // SSNOP_MMR6
3915
0
    50349366U,  // ST_B
3916
0
    50351713U,  // ST_D
3917
0
    50353103U,  // ST_H
3918
0
    50357536U,  // ST_W
3919
0
    536889258U, // SUB
3920
0
    536892759U, // SUBQH_PH
3921
0
    536892759U, // SUBQH_PH_MMR2
3922
0
    536892874U, // SUBQH_R_PH
3923
0
    536892874U, // SUBQH_R_PH_MMR2
3924
0
    536896192U, // SUBQH_R_W
3925
0
    536896192U, // SUBQH_R_W_MMR2
3926
0
    536895797U, // SUBQH_W
3927
0
    536895797U, // SUBQH_W_MMR2
3928
0
    536892834U, // SUBQ_PH
3929
0
    536892834U, // SUBQ_PH_MM
3930
0
    536892931U, // SUBQ_S_PH
3931
0
    536892931U, // SUBQ_S_PH_MM
3932
0
    536896498U, // SUBQ_S_W
3933
0
    536896498U, // SUBQ_S_W_MM
3934
0
    536888752U, // SUBSUS_U_B
3935
0
    536891171U, // SUBSUS_U_D
3936
0
    536892541U, // SUBSUS_U_H
3937
0
    536896986U, // SUBSUS_U_W
3938
0
    536888555U, // SUBSUU_S_B
3939
0
    536890744U, // SUBSUU_S_D
3940
0
    536892281U, // SUBSUU_S_H
3941
0
    536896608U, // SUBSUU_S_W
3942
0
    536888517U, // SUBS_S_B
3943
0
    536890684U, // SUBS_S_D
3944
0
    536892243U, // SUBS_S_H
3945
0
    536896548U, // SUBS_S_W
3946
0
    536888732U, // SUBS_U_B
3947
0
    536891151U, // SUBS_U_D
3948
0
    536892521U, // SUBS_U_H
3949
0
    536896966U, // SUBS_U_W
3950
0
    536887886U, // SUBU16_MM
3951
0
    536887886U, // SUBU16_MMR6
3952
0
    536888967U, // SUBUH_QB
3953
0
    536888967U, // SUBUH_QB_MMR2
3954
0
    536889073U, // SUBUH_R_QB
3955
0
    536889073U, // SUBUH_R_QB_MMR2
3956
0
    536895115U, // SUBU_MMR6
3957
0
    536893032U, // SUBU_PH
3958
0
    536893032U, // SUBU_PH_MMR2
3959
0
    536889181U, // SUBU_QB
3960
0
    536889181U, // SUBU_QB_MM
3961
0
    536892975U, // SUBU_S_PH
3962
0
    536892975U, // SUBU_S_PH_MMR2
3963
0
    536889120U, // SUBU_S_QB
3964
0
    536889120U, // SUBU_S_QB_MM
3965
0
    536888299U, // SUBVI_B
3966
0
    536890107U, // SUBVI_D
3967
0
    536891903U, // SUBVI_H
3968
0
    536895930U, // SUBVI_W
3969
0
    536888811U, // SUBV_B
3970
0
    536891242U, // SUBV_D
3971
0
    536892600U, // SUBV_H
3972
0
    536897067U, // SUBV_W
3973
0
    536889258U, // SUB_MM
3974
0
    536889258U, // SUB_MMR6
3975
0
    536895115U, // SUBu
3976
0
    536895115U, // SUBu_MM
3977
0
    3254796459U,  // SUXC1
3978
0
    3254796459U,  // SUXC164
3979
0
    3254796459U,  // SUXC1_MM
3980
0
    50357918U,  // SW
3981
0
    50348651U,  // SW16_MM
3982
0
    50348651U,  // SW16_MMR6
3983
0
    50357918U,  // SW64
3984
0
    50348176U,  // SWC1
3985
0
    50348176U,  // SWC1_MM
3986
0
    50348392U,  // SWC2
3987
0
    50348392U,  // SWC2_MMR6
3988
0
    50348392U,  // SWC2_R6
3989
0
    50348437U,  // SWC3
3990
0
    50357918U,  // SWDSP
3991
0
    50357918U,  // SWDSP_MM
3992
0
    50352386U,  // SWE
3993
0
    50352386U,  // SWE_MM
3994
0
    50354475U,  // SWL
3995
0
    50354475U,  // SWL64
3996
0
    50352318U,  // SWLE
3997
0
    50352318U,  // SWLE_MM
3998
0
    50354475U,  // SWL_MM
3999
0
    66066U, // SWM16_MM
4000
0
    66066U, // SWM16_MMR6
4001
0
    65806U, // SWM32_MM
4002
0
    369121855U, // SWP_MM
4003
0
    50354981U,  // SWR
4004
0
    50354981U,  // SWR64
4005
0
    50352357U,  // SWRE
4006
0
    50352357U,  // SWRE_MM
4007
0
    50354981U,  // SWR_MM
4008
0
    50354724U,  // SWSP_MM
4009
0
    50357918U,  // SWSP_MMR6
4010
0
    3254796473U,  // SWXC1
4011
0
    3254796473U,  // SWXC1_MM
4012
0
    50357918U,  // SW_MM
4013
0
    50357918U,  // SW_MMR6
4014
0
    255866U,  // SYNC
4015
0
    268102U,  // SYNCI
4016
0
    268102U,  // SYNCI_MM
4017
0
    268102U,  // SYNCI_MMR6
4018
0
    255866U,  // SYNC_MM
4019
0
    247832U,  // SYNC_MMR6
4020
0
    219316U,  // SYSCALL
4021
0
    645300U,  // SYSCALL_MM
4022
0
    0U, // Save16
4023
0
    0U, // SaveX16
4024
0
    50349987U,  // SbRxRyOffMemX16
4025
0
    550669U,  // SebRx16
4026
0
    550675U,  // SehRx16
4027
0
    50353980U,  // ShRxRyOffMemX16
4028
0
    536893648U, // SllX16
4029
0
    33578946U,  // SllvRxRy16
4030
0
    24146U, // SltRxRy16
4031
0
    1610635183U,  // SltiRxImm16
4032
0
    22447U, // SltiRxImmX16
4033
0
    1610637038U,  // SltiuRxImm16
4034
0
    24302U, // SltiuRxImmX16
4035
0
    24388U, // SltuRxRy16
4036
0
    536888014U, // SraX16
4037
0
    33578925U,  // SravRxRy16
4038
0
    536893676U, // SrlX16
4039
0
    33578953U,  // SrlvRxRy16
4040
0
    536895115U, // SubuRxRyRz16
4041
0
    50357918U,  // SwRxRyOffMemX16
4042
0
    50357918U,  // SwRxSpImmX16
4043
0
    536894030U, // TEQ
4044
0
    22429U, // TEQI
4045
0
    22429U, // TEQI_MM
4046
0
    536894030U, // TEQ_MM
4047
0
    536891531U, // TGE
4048
0
    22362U, // TGEI
4049
0
    24295U, // TGEIU
4050
0
    24295U, // TGEIU_MM
4051
0
    22362U, // TGEI_MM
4052
0
    536895168U, // TGEU
4053
0
    536895168U, // TGEU_MM
4054
0
    536891531U, // TGE_MM
4055
0
    10655U, // TLBGINV
4056
0
    10556U, // TLBGINVF
4057
0
    10556U, // TLBGINVF_MM
4058
0
    10655U, // TLBGINV_MM
4059
0
    10601U, // TLBGP
4060
0
    10601U, // TLBGP_MM
4061
0
    10618U, // TLBGR
4062
0
    10618U, // TLBGR_MM
4063
0
    10571U, // TLBGWI
4064
0
    10571U, // TLBGWI_MM
4065
0
    10630U, // TLBGWR
4066
0
    10630U, // TLBGWR_MM
4067
0
    10648U, // TLBINV
4068
0
    10548U, // TLBINVF
4069
0
    10548U, // TLBINVF_MMR6
4070
0
    10648U, // TLBINV_MMR6
4071
0
    10596U, // TLBP
4072
0
    10596U, // TLBP_MM
4073
0
    10613U, // TLBR
4074
0
    10613U, // TLBR_MM
4075
0
    10565U, // TLBWI
4076
0
    10565U, // TLBWI_MM
4077
0
    10624U, // TLBWR
4078
0
    10624U, // TLBWR_MM
4079
0
    536895063U, // TLT
4080
0
    22453U, // TLTI
4081
0
    24309U, // TLTIU_MM
4082
0
    22453U, // TLTI_MM
4083
0
    536895306U, // TLTU
4084
0
    536895306U, // TLTU_MM
4085
0
    536895063U, // TLT_MM
4086
0
    536891598U, // TNE
4087
0
    22374U, // TNEI
4088
0
    22374U, // TNEI_MM
4089
0
    536891598U, // TNE_MM
4090
0
    19213U, // TRUNC_L_D64
4091
0
    19213U, // TRUNC_L_D_MMR6
4092
0
    23545U, // TRUNC_L_S
4093
0
    23545U, // TRUNC_L_S_MMR6
4094
0
    20388U, // TRUNC_W_D32
4095
0
    20388U, // TRUNC_W_D64
4096
0
    20388U, // TRUNC_W_D_MMR6
4097
0
    20388U, // TRUNC_W_MM
4098
0
    23887U, // TRUNC_W_S
4099
0
    23887U, // TRUNC_W_S_MM
4100
0
    23887U, // TRUNC_W_S_MMR6
4101
0
    24309U, // TTLTIU
4102
0
    26394U, // UDIV
4103
0
    26394U, // UDIV_MM
4104
0
    536895228U, // V3MULU
4105
0
    536887357U, // VMM0
4106
0
    536895243U, // VMULU
4107
0
    570442567U, // VSHF_B
4108
0
    570444392U, // VSHF_D
4109
0
    570446204U, // VSHF_H
4110
0
    570450150U, // VSHF_W
4111
0
    10643U, // WAIT
4112
0
    646727U,  // WAIT_MM
4113
0
    646727U,  // WAIT_MMR6
4114
0
    184572422U, // WRDSP
4115
0
    402676230U, // WRDSP_MM
4116
0
    23294U, // WRPGPR_MMR6
4117
0
    21758U, // WSBH
4118
0
    21758U, // WSBH_MM
4119
0
    21758U, // WSBH_MMR6
4120
0
    536894193U, // XOR
4121
0
    20021808U,  // XOR16_MM
4122
0
    20021808U,  // XOR16_MMR6
4123
0
    536894193U, // XOR64
4124
0
    536888262U, // XORI_B
4125
0
    536893347U, // XORI_MMR6
4126
0
    536894193U, // XOR_MM
4127
0
    536894193U, // XOR_MMR6
4128
0
    536895369U, // XOR_V
4129
0
    536893347U, // XORi
4130
0
    536893347U, // XORi64
4131
0
    536893347U, // XORi_MM
4132
0
    33577713U,  // XorRxRxRy16
4133
0
    20535U, // YIELD
4134
0
  };
4135
4136
0
  static const uint16_t OpInfo1[] = {
4137
0
    0U, // PHI
4138
0
    0U, // INLINEASM
4139
0
    0U, // INLINEASM_BR
4140
0
    0U, // CFI_INSTRUCTION
4141
0
    0U, // EH_LABEL
4142
0
    0U, // GC_LABEL
4143
0
    0U, // ANNOTATION_LABEL
4144
0
    0U, // KILL
4145
0
    0U, // EXTRACT_SUBREG
4146
0
    0U, // INSERT_SUBREG
4147
0
    0U, // IMPLICIT_DEF
4148
0
    0U, // SUBREG_TO_REG
4149
0
    0U, // COPY_TO_REGCLASS
4150
0
    0U, // DBG_VALUE
4151
0
    0U, // DBG_VALUE_LIST
4152
0
    0U, // DBG_INSTR_REF
4153
0
    0U, // DBG_PHI
4154
0
    0U, // DBG_LABEL
4155
0
    0U, // REG_SEQUENCE
4156
0
    0U, // COPY
4157
0
    0U, // BUNDLE
4158
0
    0U, // LIFETIME_START
4159
0
    0U, // LIFETIME_END
4160
0
    0U, // PSEUDO_PROBE
4161
0
    0U, // ARITH_FENCE
4162
0
    0U, // STACKMAP
4163
0
    0U, // FENTRY_CALL
4164
0
    0U, // PATCHPOINT
4165
0
    0U, // LOAD_STACK_GUARD
4166
0
    0U, // PREALLOCATED_SETUP
4167
0
    0U, // PREALLOCATED_ARG
4168
0
    0U, // STATEPOINT
4169
0
    0U, // LOCAL_ESCAPE
4170
0
    0U, // FAULTING_OP
4171
0
    0U, // PATCHABLE_OP
4172
0
    0U, // PATCHABLE_FUNCTION_ENTER
4173
0
    0U, // PATCHABLE_RET
4174
0
    0U, // PATCHABLE_FUNCTION_EXIT
4175
0
    0U, // PATCHABLE_TAIL_CALL
4176
0
    0U, // PATCHABLE_EVENT_CALL
4177
0
    0U, // PATCHABLE_TYPED_EVENT_CALL
4178
0
    0U, // ICALL_BRANCH_FUNNEL
4179
0
    0U, // MEMBARRIER
4180
0
    0U, // JUMP_TABLE_DEBUG_INFO
4181
0
    0U, // G_ASSERT_SEXT
4182
0
    0U, // G_ASSERT_ZEXT
4183
0
    0U, // G_ASSERT_ALIGN
4184
0
    0U, // G_ADD
4185
0
    0U, // G_SUB
4186
0
    0U, // G_MUL
4187
0
    0U, // G_SDIV
4188
0
    0U, // G_UDIV
4189
0
    0U, // G_SREM
4190
0
    0U, // G_UREM
4191
0
    0U, // G_SDIVREM
4192
0
    0U, // G_UDIVREM
4193
0
    0U, // G_AND
4194
0
    0U, // G_OR
4195
0
    0U, // G_XOR
4196
0
    0U, // G_IMPLICIT_DEF
4197
0
    0U, // G_PHI
4198
0
    0U, // G_FRAME_INDEX
4199
0
    0U, // G_GLOBAL_VALUE
4200
0
    0U, // G_CONSTANT_POOL
4201
0
    0U, // G_EXTRACT
4202
0
    0U, // G_UNMERGE_VALUES
4203
0
    0U, // G_INSERT
4204
0
    0U, // G_MERGE_VALUES
4205
0
    0U, // G_BUILD_VECTOR
4206
0
    0U, // G_BUILD_VECTOR_TRUNC
4207
0
    0U, // G_CONCAT_VECTORS
4208
0
    0U, // G_PTRTOINT
4209
0
    0U, // G_INTTOPTR
4210
0
    0U, // G_BITCAST
4211
0
    0U, // G_FREEZE
4212
0
    0U, // G_CONSTANT_FOLD_BARRIER
4213
0
    0U, // G_INTRINSIC_FPTRUNC_ROUND
4214
0
    0U, // G_INTRINSIC_TRUNC
4215
0
    0U, // G_INTRINSIC_ROUND
4216
0
    0U, // G_INTRINSIC_LRINT
4217
0
    0U, // G_INTRINSIC_ROUNDEVEN
4218
0
    0U, // G_READCYCLECOUNTER
4219
0
    0U, // G_LOAD
4220
0
    0U, // G_SEXTLOAD
4221
0
    0U, // G_ZEXTLOAD
4222
0
    0U, // G_INDEXED_LOAD
4223
0
    0U, // G_INDEXED_SEXTLOAD
4224
0
    0U, // G_INDEXED_ZEXTLOAD
4225
0
    0U, // G_STORE
4226
0
    0U, // G_INDEXED_STORE
4227
0
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
4228
0
    0U, // G_ATOMIC_CMPXCHG
4229
0
    0U, // G_ATOMICRMW_XCHG
4230
0
    0U, // G_ATOMICRMW_ADD
4231
0
    0U, // G_ATOMICRMW_SUB
4232
0
    0U, // G_ATOMICRMW_AND
4233
0
    0U, // G_ATOMICRMW_NAND
4234
0
    0U, // G_ATOMICRMW_OR
4235
0
    0U, // G_ATOMICRMW_XOR
4236
0
    0U, // G_ATOMICRMW_MAX
4237
0
    0U, // G_ATOMICRMW_MIN
4238
0
    0U, // G_ATOMICRMW_UMAX
4239
0
    0U, // G_ATOMICRMW_UMIN
4240
0
    0U, // G_ATOMICRMW_FADD
4241
0
    0U, // G_ATOMICRMW_FSUB
4242
0
    0U, // G_ATOMICRMW_FMAX
4243
0
    0U, // G_ATOMICRMW_FMIN
4244
0
    0U, // G_ATOMICRMW_UINC_WRAP
4245
0
    0U, // G_ATOMICRMW_UDEC_WRAP
4246
0
    0U, // G_FENCE
4247
0
    0U, // G_PREFETCH
4248
0
    0U, // G_BRCOND
4249
0
    0U, // G_BRINDIRECT
4250
0
    0U, // G_INVOKE_REGION_START
4251
0
    0U, // G_INTRINSIC
4252
0
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
4253
0
    0U, // G_INTRINSIC_CONVERGENT
4254
0
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
4255
0
    0U, // G_ANYEXT
4256
0
    0U, // G_TRUNC
4257
0
    0U, // G_CONSTANT
4258
0
    0U, // G_FCONSTANT
4259
0
    0U, // G_VASTART
4260
0
    0U, // G_VAARG
4261
0
    0U, // G_SEXT
4262
0
    0U, // G_SEXT_INREG
4263
0
    0U, // G_ZEXT
4264
0
    0U, // G_SHL
4265
0
    0U, // G_LSHR
4266
0
    0U, // G_ASHR
4267
0
    0U, // G_FSHL
4268
0
    0U, // G_FSHR
4269
0
    0U, // G_ROTR
4270
0
    0U, // G_ROTL
4271
0
    0U, // G_ICMP
4272
0
    0U, // G_FCMP
4273
0
    0U, // G_SELECT
4274
0
    0U, // G_UADDO
4275
0
    0U, // G_UADDE
4276
0
    0U, // G_USUBO
4277
0
    0U, // G_USUBE
4278
0
    0U, // G_SADDO
4279
0
    0U, // G_SADDE
4280
0
    0U, // G_SSUBO
4281
0
    0U, // G_SSUBE
4282
0
    0U, // G_UMULO
4283
0
    0U, // G_SMULO
4284
0
    0U, // G_UMULH
4285
0
    0U, // G_SMULH
4286
0
    0U, // G_UADDSAT
4287
0
    0U, // G_SADDSAT
4288
0
    0U, // G_USUBSAT
4289
0
    0U, // G_SSUBSAT
4290
0
    0U, // G_USHLSAT
4291
0
    0U, // G_SSHLSAT
4292
0
    0U, // G_SMULFIX
4293
0
    0U, // G_UMULFIX
4294
0
    0U, // G_SMULFIXSAT
4295
0
    0U, // G_UMULFIXSAT
4296
0
    0U, // G_SDIVFIX
4297
0
    0U, // G_UDIVFIX
4298
0
    0U, // G_SDIVFIXSAT
4299
0
    0U, // G_UDIVFIXSAT
4300
0
    0U, // G_FADD
4301
0
    0U, // G_FSUB
4302
0
    0U, // G_FMUL
4303
0
    0U, // G_FMA
4304
0
    0U, // G_FMAD
4305
0
    0U, // G_FDIV
4306
0
    0U, // G_FREM
4307
0
    0U, // G_FPOW
4308
0
    0U, // G_FPOWI
4309
0
    0U, // G_FEXP
4310
0
    0U, // G_FEXP2
4311
0
    0U, // G_FEXP10
4312
0
    0U, // G_FLOG
4313
0
    0U, // G_FLOG2
4314
0
    0U, // G_FLOG10
4315
0
    0U, // G_FLDEXP
4316
0
    0U, // G_FFREXP
4317
0
    0U, // G_FNEG
4318
0
    0U, // G_FPEXT
4319
0
    0U, // G_FPTRUNC
4320
0
    0U, // G_FPTOSI
4321
0
    0U, // G_FPTOUI
4322
0
    0U, // G_SITOFP
4323
0
    0U, // G_UITOFP
4324
0
    0U, // G_FABS
4325
0
    0U, // G_FCOPYSIGN
4326
0
    0U, // G_IS_FPCLASS
4327
0
    0U, // G_FCANONICALIZE
4328
0
    0U, // G_FMINNUM
4329
0
    0U, // G_FMAXNUM
4330
0
    0U, // G_FMINNUM_IEEE
4331
0
    0U, // G_FMAXNUM_IEEE
4332
0
    0U, // G_FMINIMUM
4333
0
    0U, // G_FMAXIMUM
4334
0
    0U, // G_GET_FPENV
4335
0
    0U, // G_SET_FPENV
4336
0
    0U, // G_RESET_FPENV
4337
0
    0U, // G_GET_FPMODE
4338
0
    0U, // G_SET_FPMODE
4339
0
    0U, // G_RESET_FPMODE
4340
0
    0U, // G_PTR_ADD
4341
0
    0U, // G_PTRMASK
4342
0
    0U, // G_SMIN
4343
0
    0U, // G_SMAX
4344
0
    0U, // G_UMIN
4345
0
    0U, // G_UMAX
4346
0
    0U, // G_ABS
4347
0
    0U, // G_LROUND
4348
0
    0U, // G_LLROUND
4349
0
    0U, // G_BR
4350
0
    0U, // G_BRJT
4351
0
    0U, // G_INSERT_VECTOR_ELT
4352
0
    0U, // G_EXTRACT_VECTOR_ELT
4353
0
    0U, // G_SHUFFLE_VECTOR
4354
0
    0U, // G_CTTZ
4355
0
    0U, // G_CTTZ_ZERO_UNDEF
4356
0
    0U, // G_CTLZ
4357
0
    0U, // G_CTLZ_ZERO_UNDEF
4358
0
    0U, // G_CTPOP
4359
0
    0U, // G_BSWAP
4360
0
    0U, // G_BITREVERSE
4361
0
    0U, // G_FCEIL
4362
0
    0U, // G_FCOS
4363
0
    0U, // G_FSIN
4364
0
    0U, // G_FSQRT
4365
0
    0U, // G_FFLOOR
4366
0
    0U, // G_FRINT
4367
0
    0U, // G_FNEARBYINT
4368
0
    0U, // G_ADDRSPACE_CAST
4369
0
    0U, // G_BLOCK_ADDR
4370
0
    0U, // G_JUMP_TABLE
4371
0
    0U, // G_DYN_STACKALLOC
4372
0
    0U, // G_STACKSAVE
4373
0
    0U, // G_STACKRESTORE
4374
0
    0U, // G_STRICT_FADD
4375
0
    0U, // G_STRICT_FSUB
4376
0
    0U, // G_STRICT_FMUL
4377
0
    0U, // G_STRICT_FDIV
4378
0
    0U, // G_STRICT_FREM
4379
0
    0U, // G_STRICT_FMA
4380
0
    0U, // G_STRICT_FSQRT
4381
0
    0U, // G_STRICT_FLDEXP
4382
0
    0U, // G_READ_REGISTER
4383
0
    0U, // G_WRITE_REGISTER
4384
0
    0U, // G_MEMCPY
4385
0
    0U, // G_MEMCPY_INLINE
4386
0
    0U, // G_MEMMOVE
4387
0
    0U, // G_MEMSET
4388
0
    0U, // G_BZERO
4389
0
    0U, // G_VECREDUCE_SEQ_FADD
4390
0
    0U, // G_VECREDUCE_SEQ_FMUL
4391
0
    0U, // G_VECREDUCE_FADD
4392
0
    0U, // G_VECREDUCE_FMUL
4393
0
    0U, // G_VECREDUCE_FMAX
4394
0
    0U, // G_VECREDUCE_FMIN
4395
0
    0U, // G_VECREDUCE_FMAXIMUM
4396
0
    0U, // G_VECREDUCE_FMINIMUM
4397
0
    0U, // G_VECREDUCE_ADD
4398
0
    0U, // G_VECREDUCE_MUL
4399
0
    0U, // G_VECREDUCE_AND
4400
0
    0U, // G_VECREDUCE_OR
4401
0
    0U, // G_VECREDUCE_XOR
4402
0
    0U, // G_VECREDUCE_SMAX
4403
0
    0U, // G_VECREDUCE_SMIN
4404
0
    0U, // G_VECREDUCE_UMAX
4405
0
    0U, // G_VECREDUCE_UMIN
4406
0
    0U, // G_SBFX
4407
0
    0U, // G_UBFX
4408
0
    0U, // ABSMacro
4409
0
    0U, // ADJCALLSTACKDOWN
4410
0
    0U, // ADJCALLSTACKUP
4411
0
    0U, // AND_V_D_PSEUDO
4412
0
    0U, // AND_V_H_PSEUDO
4413
0
    0U, // AND_V_W_PSEUDO
4414
0
    0U, // ATOMIC_CMP_SWAP_I16
4415
0
    0U, // ATOMIC_CMP_SWAP_I16_POSTRA
4416
0
    0U, // ATOMIC_CMP_SWAP_I32
4417
0
    0U, // ATOMIC_CMP_SWAP_I32_POSTRA
4418
0
    0U, // ATOMIC_CMP_SWAP_I64
4419
0
    0U, // ATOMIC_CMP_SWAP_I64_POSTRA
4420
0
    0U, // ATOMIC_CMP_SWAP_I8
4421
0
    0U, // ATOMIC_CMP_SWAP_I8_POSTRA
4422
0
    0U, // ATOMIC_LOAD_ADD_I16
4423
0
    0U, // ATOMIC_LOAD_ADD_I16_POSTRA
4424
0
    0U, // ATOMIC_LOAD_ADD_I32
4425
0
    0U, // ATOMIC_LOAD_ADD_I32_POSTRA
4426
0
    0U, // ATOMIC_LOAD_ADD_I64
4427
0
    0U, // ATOMIC_LOAD_ADD_I64_POSTRA
4428
0
    0U, // ATOMIC_LOAD_ADD_I8
4429
0
    0U, // ATOMIC_LOAD_ADD_I8_POSTRA
4430
0
    0U, // ATOMIC_LOAD_AND_I16
4431
0
    0U, // ATOMIC_LOAD_AND_I16_POSTRA
4432
0
    0U, // ATOMIC_LOAD_AND_I32
4433
0
    0U, // ATOMIC_LOAD_AND_I32_POSTRA
4434
0
    0U, // ATOMIC_LOAD_AND_I64
4435
0
    0U, // ATOMIC_LOAD_AND_I64_POSTRA
4436
0
    0U, // ATOMIC_LOAD_AND_I8
4437
0
    0U, // ATOMIC_LOAD_AND_I8_POSTRA
4438
0
    0U, // ATOMIC_LOAD_MAX_I16
4439
0
    0U, // ATOMIC_LOAD_MAX_I16_POSTRA
4440
0
    0U, // ATOMIC_LOAD_MAX_I32
4441
0
    0U, // ATOMIC_LOAD_MAX_I32_POSTRA
4442
0
    0U, // ATOMIC_LOAD_MAX_I64
4443
0
    0U, // ATOMIC_LOAD_MAX_I64_POSTRA
4444
0
    0U, // ATOMIC_LOAD_MAX_I8
4445
0
    0U, // ATOMIC_LOAD_MAX_I8_POSTRA
4446
0
    0U, // ATOMIC_LOAD_MIN_I16
4447
0
    0U, // ATOMIC_LOAD_MIN_I16_POSTRA
4448
0
    0U, // ATOMIC_LOAD_MIN_I32
4449
0
    0U, // ATOMIC_LOAD_MIN_I32_POSTRA
4450
0
    0U, // ATOMIC_LOAD_MIN_I64
4451
0
    0U, // ATOMIC_LOAD_MIN_I64_POSTRA
4452
0
    0U, // ATOMIC_LOAD_MIN_I8
4453
0
    0U, // ATOMIC_LOAD_MIN_I8_POSTRA
4454
0
    0U, // ATOMIC_LOAD_NAND_I16
4455
0
    0U, // ATOMIC_LOAD_NAND_I16_POSTRA
4456
0
    0U, // ATOMIC_LOAD_NAND_I32
4457
0
    0U, // ATOMIC_LOAD_NAND_I32_POSTRA
4458
0
    0U, // ATOMIC_LOAD_NAND_I64
4459
0
    0U, // ATOMIC_LOAD_NAND_I64_POSTRA
4460
0
    0U, // ATOMIC_LOAD_NAND_I8
4461
0
    0U, // ATOMIC_LOAD_NAND_I8_POSTRA
4462
0
    0U, // ATOMIC_LOAD_OR_I16
4463
0
    0U, // ATOMIC_LOAD_OR_I16_POSTRA
4464
0
    0U, // ATOMIC_LOAD_OR_I32
4465
0
    0U, // ATOMIC_LOAD_OR_I32_POSTRA
4466
0
    0U, // ATOMIC_LOAD_OR_I64
4467
0
    0U, // ATOMIC_LOAD_OR_I64_POSTRA
4468
0
    0U, // ATOMIC_LOAD_OR_I8
4469
0
    0U, // ATOMIC_LOAD_OR_I8_POSTRA
4470
0
    0U, // ATOMIC_LOAD_SUB_I16
4471
0
    0U, // ATOMIC_LOAD_SUB_I16_POSTRA
4472
0
    0U, // ATOMIC_LOAD_SUB_I32
4473
0
    0U, // ATOMIC_LOAD_SUB_I32_POSTRA
4474
0
    0U, // ATOMIC_LOAD_SUB_I64
4475
0
    0U, // ATOMIC_LOAD_SUB_I64_POSTRA
4476
0
    0U, // ATOMIC_LOAD_SUB_I8
4477
0
    0U, // ATOMIC_LOAD_SUB_I8_POSTRA
4478
0
    0U, // ATOMIC_LOAD_UMAX_I16
4479
0
    0U, // ATOMIC_LOAD_UMAX_I16_POSTRA
4480
0
    0U, // ATOMIC_LOAD_UMAX_I32
4481
0
    0U, // ATOMIC_LOAD_UMAX_I32_POSTRA
4482
0
    0U, // ATOMIC_LOAD_UMAX_I64
4483
0
    0U, // ATOMIC_LOAD_UMAX_I64_POSTRA
4484
0
    0U, // ATOMIC_LOAD_UMAX_I8
4485
0
    0U, // ATOMIC_LOAD_UMAX_I8_POSTRA
4486
0
    0U, // ATOMIC_LOAD_UMIN_I16
4487
0
    0U, // ATOMIC_LOAD_UMIN_I16_POSTRA
4488
0
    0U, // ATOMIC_LOAD_UMIN_I32
4489
0
    0U, // ATOMIC_LOAD_UMIN_I32_POSTRA
4490
0
    0U, // ATOMIC_LOAD_UMIN_I64
4491
0
    0U, // ATOMIC_LOAD_UMIN_I64_POSTRA
4492
0
    0U, // ATOMIC_LOAD_UMIN_I8
4493
0
    0U, // ATOMIC_LOAD_UMIN_I8_POSTRA
4494
0
    0U, // ATOMIC_LOAD_XOR_I16
4495
0
    0U, // ATOMIC_LOAD_XOR_I16_POSTRA
4496
0
    0U, // ATOMIC_LOAD_XOR_I32
4497
0
    0U, // ATOMIC_LOAD_XOR_I32_POSTRA
4498
0
    0U, // ATOMIC_LOAD_XOR_I64
4499
0
    0U, // ATOMIC_LOAD_XOR_I64_POSTRA
4500
0
    0U, // ATOMIC_LOAD_XOR_I8
4501
0
    0U, // ATOMIC_LOAD_XOR_I8_POSTRA
4502
0
    0U, // ATOMIC_SWAP_I16
4503
0
    0U, // ATOMIC_SWAP_I16_POSTRA
4504
0
    0U, // ATOMIC_SWAP_I32
4505
0
    0U, // ATOMIC_SWAP_I32_POSTRA
4506
0
    0U, // ATOMIC_SWAP_I64
4507
0
    0U, // ATOMIC_SWAP_I64_POSTRA
4508
0
    0U, // ATOMIC_SWAP_I8
4509
0
    0U, // ATOMIC_SWAP_I8_POSTRA
4510
0
    0U, // B
4511
0
    0U, // BAL_BR
4512
0
    0U, // BAL_BR_MM
4513
0
    0U, // BEQLImmMacro
4514
0
    0U, // BGE
4515
0
    0U, // BGEImmMacro
4516
0
    0U, // BGEL
4517
0
    0U, // BGELImmMacro
4518
0
    0U, // BGEU
4519
0
    0U, // BGEUImmMacro
4520
0
    0U, // BGEUL
4521
0
    0U, // BGEULImmMacro
4522
0
    0U, // BGT
4523
0
    0U, // BGTImmMacro
4524
0
    0U, // BGTL
4525
0
    0U, // BGTLImmMacro
4526
0
    0U, // BGTU
4527
0
    0U, // BGTUImmMacro
4528
0
    0U, // BGTUL
4529
0
    0U, // BGTULImmMacro
4530
0
    0U, // BLE
4531
0
    0U, // BLEImmMacro
4532
0
    0U, // BLEL
4533
0
    0U, // BLELImmMacro
4534
0
    0U, // BLEU
4535
0
    0U, // BLEUImmMacro
4536
0
    0U, // BLEUL
4537
0
    0U, // BLEULImmMacro
4538
0
    0U, // BLT
4539
0
    0U, // BLTImmMacro
4540
0
    0U, // BLTL
4541
0
    0U, // BLTLImmMacro
4542
0
    0U, // BLTU
4543
0
    0U, // BLTUImmMacro
4544
0
    0U, // BLTUL
4545
0
    0U, // BLTULImmMacro
4546
0
    0U, // BNELImmMacro
4547
0
    0U, // BPOSGE32_PSEUDO
4548
0
    0U, // BSEL_D_PSEUDO
4549
0
    0U, // BSEL_FD_PSEUDO
4550
0
    0U, // BSEL_FW_PSEUDO
4551
0
    0U, // BSEL_H_PSEUDO
4552
0
    0U, // BSEL_W_PSEUDO
4553
0
    0U, // B_MM
4554
0
    0U, // B_MMR6_Pseudo
4555
0
    0U, // B_MM_Pseudo
4556
0
    0U, // BeqImm
4557
0
    0U, // BneImm
4558
0
    0U, // BteqzT8CmpX16
4559
0
    0U, // BteqzT8CmpiX16
4560
0
    0U, // BteqzT8SltX16
4561
0
    0U, // BteqzT8SltiX16
4562
0
    0U, // BteqzT8SltiuX16
4563
0
    0U, // BteqzT8SltuX16
4564
0
    0U, // BtnezT8CmpX16
4565
0
    0U, // BtnezT8CmpiX16
4566
0
    0U, // BtnezT8SltX16
4567
0
    0U, // BtnezT8SltiX16
4568
0
    0U, // BtnezT8SltiuX16
4569
0
    0U, // BtnezT8SltuX16
4570
0
    0U, // BuildPairF64
4571
0
    0U, // BuildPairF64_64
4572
0
    0U, // CFTC1
4573
0
    0U, // CONSTPOOL_ENTRY
4574
0
    0U, // COPY_FD_PSEUDO
4575
0
    0U, // COPY_FW_PSEUDO
4576
0
    0U, // CTTC1
4577
0
    0U, // Constant32
4578
0
    4U, // DMULImmMacro
4579
0
    4U, // DMULMacro
4580
0
    4U, // DMULOMacro
4581
0
    4U, // DMULOUMacro
4582
0
    4U, // DROL
4583
0
    4U, // DROLImm
4584
0
    4U, // DROR
4585
0
    4U, // DRORImm
4586
0
    4U, // DSDivIMacro
4587
0
    4U, // DSDivMacro
4588
0
    4U, // DSRemIMacro
4589
0
    4U, // DSRemMacro
4590
0
    4U, // DUDivIMacro
4591
0
    4U, // DUDivMacro
4592
0
    4U, // DURemIMacro
4593
0
    4U, // DURemMacro
4594
0
    0U, // ERet
4595
0
    0U, // ExtractElementF64
4596
0
    0U, // ExtractElementF64_64
4597
0
    0U, // FABS_D
4598
0
    0U, // FABS_W
4599
0
    0U, // FEXP2_D_1_PSEUDO
4600
0
    0U, // FEXP2_W_1_PSEUDO
4601
0
    0U, // FILL_FD_PSEUDO
4602
0
    0U, // FILL_FW_PSEUDO
4603
0
    0U, // GotPrologue16
4604
0
    0U, // INSERT_B_VIDX64_PSEUDO
4605
0
    0U, // INSERT_B_VIDX_PSEUDO
4606
0
    0U, // INSERT_D_VIDX64_PSEUDO
4607
0
    0U, // INSERT_D_VIDX_PSEUDO
4608
0
    0U, // INSERT_FD_PSEUDO
4609
0
    0U, // INSERT_FD_VIDX64_PSEUDO
4610
0
    0U, // INSERT_FD_VIDX_PSEUDO
4611
0
    0U, // INSERT_FW_PSEUDO
4612
0
    0U, // INSERT_FW_VIDX64_PSEUDO
4613
0
    0U, // INSERT_FW_VIDX_PSEUDO
4614
0
    0U, // INSERT_H_VIDX64_PSEUDO
4615
0
    0U, // INSERT_H_VIDX_PSEUDO
4616
0
    0U, // INSERT_W_VIDX64_PSEUDO
4617
0
    0U, // INSERT_W_VIDX_PSEUDO
4618
0
    0U, // JALR64Pseudo
4619
0
    0U, // JALRHB64Pseudo
4620
0
    0U, // JALRHBPseudo
4621
0
    0U, // JALRPseudo
4622
0
    0U, // JAL_MMR6
4623
0
    0U, // JalOneReg
4624
0
    0U, // JalTwoReg
4625
0
    0U, // LDMacro
4626
0
    0U, // LDR_D
4627
0
    0U, // LDR_W
4628
0
    0U, // LD_F16
4629
0
    0U, // LOAD_ACC128
4630
0
    0U, // LOAD_ACC64
4631
0
    0U, // LOAD_ACC64DSP
4632
0
    0U, // LOAD_CCOND_DSP
4633
0
    0U, // LONG_BRANCH_ADDiu
4634
0
    0U, // LONG_BRANCH_ADDiu2Op
4635
0
    0U, // LONG_BRANCH_DADDiu
4636
0
    0U, // LONG_BRANCH_DADDiu2Op
4637
0
    0U, // LONG_BRANCH_LUi
4638
0
    0U, // LONG_BRANCH_LUi2Op
4639
0
    0U, // LONG_BRANCH_LUi2Op_64
4640
0
    0U, // LWM_MM
4641
0
    0U, // LoadAddrImm32
4642
0
    0U, // LoadAddrImm64
4643
0
    0U, // LoadAddrReg32
4644
0
    0U, // LoadAddrReg64
4645
0
    0U, // LoadImm32
4646
0
    0U, // LoadImm64
4647
0
    0U, // LoadImmDoubleFGR
4648
0
    0U, // LoadImmDoubleFGR_32
4649
0
    0U, // LoadImmDoubleGPR
4650
0
    0U, // LoadImmSingleFGR
4651
0
    0U, // LoadImmSingleGPR
4652
0
    0U, // LwConstant32
4653
0
    0U, // MFTACX
4654
0
    8U, // MFTC0
4655
0
    0U, // MFTC1
4656
0
    0U, // MFTDSP
4657
0
    0U, // MFTGPR
4658
0
    0U, // MFTHC1
4659
0
    0U, // MFTHI
4660
0
    0U, // MFTLO
4661
0
    0U, // MIPSeh_return32
4662
0
    0U, // MIPSeh_return64
4663
0
    0U, // MSA_FP_EXTEND_D_PSEUDO
4664
0
    0U, // MSA_FP_EXTEND_W_PSEUDO
4665
0
    0U, // MSA_FP_ROUND_D_PSEUDO
4666
0
    0U, // MSA_FP_ROUND_W_PSEUDO
4667
0
    0U, // MTTACX
4668
0
    0U, // MTTC0
4669
0
    0U, // MTTC1
4670
0
    0U, // MTTDSP
4671
0
    0U, // MTTGPR
4672
0
    0U, // MTTHC1
4673
0
    0U, // MTTHI
4674
0
    0U, // MTTLO
4675
0
    4U, // MULImmMacro
4676
0
    4U, // MULOMacro
4677
0
    4U, // MULOUMacro
4678
0
    0U, // MultRxRy16
4679
0
    0U, // MultRxRyRz16
4680
0
    0U, // MultuRxRy16
4681
0
    0U, // MultuRxRyRz16
4682
0
    0U, // NOP
4683
0
    4U, // NORImm
4684
0
    4U, // NORImm64
4685
0
    0U, // NOR_V_D_PSEUDO
4686
0
    0U, // NOR_V_H_PSEUDO
4687
0
    0U, // NOR_V_W_PSEUDO
4688
0
    0U, // OR_V_D_PSEUDO
4689
0
    0U, // OR_V_H_PSEUDO
4690
0
    0U, // OR_V_W_PSEUDO
4691
0
    0U, // PseudoCMPU_EQ_QB
4692
0
    0U, // PseudoCMPU_LE_QB
4693
0
    0U, // PseudoCMPU_LT_QB
4694
0
    0U, // PseudoCMP_EQ_PH
4695
0
    0U, // PseudoCMP_LE_PH
4696
0
    0U, // PseudoCMP_LT_PH
4697
0
    0U, // PseudoCVT_D32_W
4698
0
    0U, // PseudoCVT_D64_L
4699
0
    0U, // PseudoCVT_D64_W
4700
0
    0U, // PseudoCVT_S_L
4701
0
    0U, // PseudoCVT_S_W
4702
0
    0U, // PseudoDMULT
4703
0
    0U, // PseudoDMULTu
4704
0
    0U, // PseudoDSDIV
4705
0
    0U, // PseudoDUDIV
4706
0
    0U, // PseudoD_SELECT_I
4707
0
    0U, // PseudoD_SELECT_I64
4708
0
    0U, // PseudoIndirectBranch
4709
0
    0U, // PseudoIndirectBranch64
4710
0
    0U, // PseudoIndirectBranch64R6
4711
0
    0U, // PseudoIndirectBranchR6
4712
0
    0U, // PseudoIndirectBranch_MM
4713
0
    0U, // PseudoIndirectBranch_MMR6
4714
0
    0U, // PseudoIndirectHazardBranch
4715
0
    0U, // PseudoIndirectHazardBranch64
4716
0
    0U, // PseudoIndrectHazardBranch64R6
4717
0
    0U, // PseudoIndrectHazardBranchR6
4718
0
    0U, // PseudoMADD
4719
0
    0U, // PseudoMADDU
4720
0
    0U, // PseudoMADDU_MM
4721
0
    0U, // PseudoMADD_MM
4722
0
    0U, // PseudoMFHI
4723
0
    0U, // PseudoMFHI64
4724
0
    0U, // PseudoMFHI_MM
4725
0
    0U, // PseudoMFLO
4726
0
    0U, // PseudoMFLO64
4727
0
    0U, // PseudoMFLO_MM
4728
0
    0U, // PseudoMSUB
4729
0
    0U, // PseudoMSUBU
4730
0
    0U, // PseudoMSUBU_MM
4731
0
    0U, // PseudoMSUB_MM
4732
0
    0U, // PseudoMTLOHI
4733
0
    0U, // PseudoMTLOHI64
4734
0
    0U, // PseudoMTLOHI_DSP
4735
0
    0U, // PseudoMTLOHI_MM
4736
0
    0U, // PseudoMULT
4737
0
    0U, // PseudoMULT_MM
4738
0
    0U, // PseudoMULTu
4739
0
    0U, // PseudoMULTu_MM
4740
0
    0U, // PseudoPICK_PH
4741
0
    0U, // PseudoPICK_QB
4742
0
    0U, // PseudoReturn
4743
0
    0U, // PseudoReturn64
4744
0
    0U, // PseudoSDIV
4745
0
    0U, // PseudoSELECTFP_F_D32
4746
0
    0U, // PseudoSELECTFP_F_D64
4747
0
    0U, // PseudoSELECTFP_F_I
4748
0
    0U, // PseudoSELECTFP_F_I64
4749
0
    0U, // PseudoSELECTFP_F_S
4750
0
    0U, // PseudoSELECTFP_T_D32
4751
0
    0U, // PseudoSELECTFP_T_D64
4752
0
    0U, // PseudoSELECTFP_T_I
4753
0
    0U, // PseudoSELECTFP_T_I64
4754
0
    0U, // PseudoSELECTFP_T_S
4755
0
    0U, // PseudoSELECT_D32
4756
0
    0U, // PseudoSELECT_D64
4757
0
    0U, // PseudoSELECT_I
4758
0
    0U, // PseudoSELECT_I64
4759
0
    0U, // PseudoSELECT_S
4760
0
    4U, // PseudoTRUNC_W_D
4761
0
    4U, // PseudoTRUNC_W_D32
4762
0
    4U, // PseudoTRUNC_W_S
4763
0
    0U, // PseudoUDIV
4764
0
    4U, // ROL
4765
0
    4U, // ROLImm
4766
0
    4U, // ROR
4767
0
    4U, // RORImm
4768
0
    0U, // RetRA
4769
0
    0U, // RetRA16
4770
0
    0U, // SDC1_M1
4771
0
    0U, // SDIV_MM_Pseudo
4772
0
    0U, // SDMacro
4773
0
    4U, // SDivIMacro
4774
0
    4U, // SDivMacro
4775
0
    4U, // SEQIMacro
4776
0
    4U, // SEQMacro
4777
0
    4U, // SGE
4778
0
    4U, // SGEImm
4779
0
    4U, // SGEImm64
4780
0
    4U, // SGEU
4781
0
    4U, // SGEUImm
4782
0
    4U, // SGEUImm64
4783
0
    4U, // SGTImm
4784
0
    4U, // SGTImm64
4785
0
    4U, // SGTUImm
4786
0
    4U, // SGTUImm64
4787
0
    4U, // SLE
4788
0
    4U, // SLEImm
4789
0
    4U, // SLEImm64
4790
0
    4U, // SLEU
4791
0
    4U, // SLEUImm
4792
0
    4U, // SLEUImm64
4793
0
    4U, // SLTImm64
4794
0
    4U, // SLTUImm64
4795
0
    4U, // SNEIMacro
4796
0
    4U, // SNEMacro
4797
0
    0U, // SNZ_B_PSEUDO
4798
0
    0U, // SNZ_D_PSEUDO
4799
0
    0U, // SNZ_H_PSEUDO
4800
0
    0U, // SNZ_V_PSEUDO
4801
0
    0U, // SNZ_W_PSEUDO
4802
0
    4U, // SRemIMacro
4803
0
    4U, // SRemMacro
4804
0
    0U, // STORE_ACC128
4805
0
    0U, // STORE_ACC64
4806
0
    0U, // STORE_ACC64DSP
4807
0
    0U, // STORE_CCOND_DSP
4808
0
    0U, // STR_D
4809
0
    0U, // STR_W
4810
0
    0U, // ST_F16
4811
0
    0U, // SWM_MM
4812
0
    0U, // SZ_B_PSEUDO
4813
0
    0U, // SZ_D_PSEUDO
4814
0
    0U, // SZ_H_PSEUDO
4815
0
    0U, // SZ_V_PSEUDO
4816
0
    0U, // SZ_W_PSEUDO
4817
0
    0U, // SaaAddr
4818
0
    0U, // SaadAddr
4819
0
    0U, // SelBeqZ
4820
0
    0U, // SelBneZ
4821
0
    0U, // SelTBteqZCmp
4822
0
    0U, // SelTBteqZCmpi
4823
0
    0U, // SelTBteqZSlt
4824
0
    0U, // SelTBteqZSlti
4825
0
    0U, // SelTBteqZSltiu
4826
0
    0U, // SelTBteqZSltu
4827
0
    0U, // SelTBtneZCmp
4828
0
    0U, // SelTBtneZCmpi
4829
0
    0U, // SelTBtneZSlt
4830
0
    0U, // SelTBtneZSlti
4831
0
    0U, // SelTBtneZSltiu
4832
0
    0U, // SelTBtneZSltu
4833
0
    0U, // SltCCRxRy16
4834
0
    0U, // SltiCCRxImmX16
4835
0
    0U, // SltiuCCRxImmX16
4836
0
    0U, // SltuCCRxRy16
4837
0
    0U, // SltuRxRyRz16
4838
0
    0U, // TAILCALL
4839
0
    0U, // TAILCALL64R6REG
4840
0
    0U, // TAILCALLHB64R6REG
4841
0
    0U, // TAILCALLHBR6REG
4842
0
    0U, // TAILCALLR6REG
4843
0
    0U, // TAILCALLREG
4844
0
    0U, // TAILCALLREG64
4845
0
    0U, // TAILCALLREGHB
4846
0
    0U, // TAILCALLREGHB64
4847
0
    0U, // TAILCALLREG_MM
4848
0
    0U, // TAILCALLREG_MMR6
4849
0
    0U, // TAILCALL_MM
4850
0
    0U, // TAILCALL_MMR6
4851
0
    0U, // TRAP
4852
0
    0U, // TRAP_MM
4853
0
    0U, // UDIV_MM_Pseudo
4854
0
    4U, // UDivIMacro
4855
0
    4U, // UDivMacro
4856
0
    4U, // URemIMacro
4857
0
    4U, // URemMacro
4858
0
    0U, // Ulh
4859
0
    0U, // Ulhu
4860
0
    0U, // Ulw
4861
0
    0U, // Ush
4862
0
    0U, // Usw
4863
0
    0U, // XOR_V_D_PSEUDO
4864
0
    0U, // XOR_V_H_PSEUDO
4865
0
    0U, // XOR_V_W_PSEUDO
4866
0
    0U, // ABSQ_S_PH
4867
0
    0U, // ABSQ_S_PH_MM
4868
0
    0U, // ABSQ_S_QB
4869
0
    0U, // ABSQ_S_QB_MMR2
4870
0
    0U, // ABSQ_S_W
4871
0
    0U, // ABSQ_S_W_MM
4872
0
    4U, // ADD
4873
0
    0U, // ADDIUPC
4874
0
    0U, // ADDIUPC_MM
4875
0
    0U, // ADDIUPC_MMR6
4876
0
    0U, // ADDIUR1SP_MM
4877
0
    4U, // ADDIUR2_MM
4878
0
    0U, // ADDIUS5_MM
4879
0
    0U, // ADDIUSP_MM
4880
0
    4U, // ADDIU_MMR6
4881
0
    4U, // ADDQH_PH
4882
0
    4U, // ADDQH_PH_MMR2
4883
0
    4U, // ADDQH_R_PH
4884
0
    4U, // ADDQH_R_PH_MMR2
4885
0
    4U, // ADDQH_R_W
4886
0
    4U, // ADDQH_R_W_MMR2
4887
0
    4U, // ADDQH_W
4888
0
    4U, // ADDQH_W_MMR2
4889
0
    4U, // ADDQ_PH
4890
0
    4U, // ADDQ_PH_MM
4891
0
    4U, // ADDQ_S_PH
4892
0
    4U, // ADDQ_S_PH_MM
4893
0
    4U, // ADDQ_S_W
4894
0
    4U, // ADDQ_S_W_MM
4895
0
    4U, // ADDR_PS64
4896
0
    4U, // ADDSC
4897
0
    4U, // ADDSC_MM
4898
0
    4U, // ADDS_A_B
4899
0
    4U, // ADDS_A_D
4900
0
    4U, // ADDS_A_H
4901
0
    4U, // ADDS_A_W
4902
0
    4U, // ADDS_S_B
4903
0
    4U, // ADDS_S_D
4904
0
    4U, // ADDS_S_H
4905
0
    4U, // ADDS_S_W
4906
0
    4U, // ADDS_U_B
4907
0
    4U, // ADDS_U_D
4908
0
    4U, // ADDS_U_H
4909
0
    4U, // ADDS_U_W
4910
0
    4U, // ADDU16_MM
4911
0
    4U, // ADDU16_MMR6
4912
0
    4U, // ADDUH_QB
4913
0
    4U, // ADDUH_QB_MMR2
4914
0
    4U, // ADDUH_R_QB
4915
0
    4U, // ADDUH_R_QB_MMR2
4916
0
    4U, // ADDU_MMR6
4917
0
    4U, // ADDU_PH
4918
0
    4U, // ADDU_PH_MMR2
4919
0
    4U, // ADDU_QB
4920
0
    4U, // ADDU_QB_MM
4921
0
    4U, // ADDU_S_PH
4922
0
    4U, // ADDU_S_PH_MMR2
4923
0
    4U, // ADDU_S_QB
4924
0
    4U, // ADDU_S_QB_MM
4925
0
    12U,  // ADDVI_B
4926
0
    12U,  // ADDVI_D
4927
0
    12U,  // ADDVI_H
4928
0
    12U,  // ADDVI_W
4929
0
    4U, // ADDV_B
4930
0
    4U, // ADDV_D
4931
0
    4U, // ADDV_H
4932
0
    4U, // ADDV_W
4933
0
    4U, // ADDWC
4934
0
    4U, // ADDWC_MM
4935
0
    4U, // ADD_A_B
4936
0
    4U, // ADD_A_D
4937
0
    4U, // ADD_A_H
4938
0
    4U, // ADD_A_W
4939
0
    4U, // ADD_MM
4940
0
    4U, // ADD_MMR6
4941
0
    4U, // ADDi
4942
0
    4U, // ADDi_MM
4943
0
    4U, // ADDiu
4944
0
    4U, // ADDiu_MM
4945
0
    4U, // ADDu
4946
0
    4U, // ADDu_MM
4947
0
    132U, // ALIGN
4948
0
    132U, // ALIGN_MMR6
4949
0
    0U, // ALUIPC
4950
0
    0U, // ALUIPC_MMR6
4951
0
    4U, // AND
4952
0
    0U, // AND16_MM
4953
0
    0U, // AND16_MMR6
4954
0
    4U, // AND64
4955
0
    4U, // ANDI16_MM
4956
0
    4U, // ANDI16_MMR6
4957
0
    16U,  // ANDI_B
4958
0
    20U,  // ANDI_MMR6
4959
0
    4U, // AND_MM
4960
0
    4U, // AND_MMR6
4961
0
    4U, // AND_V
4962
0
    20U,  // ANDi
4963
0
    20U,  // ANDi64
4964
0
    20U,  // ANDi_MM
4965
0
    12U,  // APPEND
4966
0
    12U,  // APPEND_MMR2
4967
0
    4U, // ASUB_S_B
4968
0
    4U, // ASUB_S_D
4969
0
    4U, // ASUB_S_H
4970
0
    4U, // ASUB_S_W
4971
0
    4U, // ASUB_U_B
4972
0
    4U, // ASUB_U_D
4973
0
    4U, // ASUB_U_H
4974
0
    4U, // ASUB_U_W
4975
0
    20U,  // AUI
4976
0
    0U, // AUIPC
4977
0
    0U, // AUIPC_MMR6
4978
0
    20U,  // AUI_MMR6
4979
0
    4U, // AVER_S_B
4980
0
    4U, // AVER_S_D
4981
0
    4U, // AVER_S_H
4982
0
    4U, // AVER_S_W
4983
0
    4U, // AVER_U_B
4984
0
    4U, // AVER_U_D
4985
0
    4U, // AVER_U_H
4986
0
    4U, // AVER_U_W
4987
0
    4U, // AVE_S_B
4988
0
    4U, // AVE_S_D
4989
0
    4U, // AVE_S_H
4990
0
    4U, // AVE_S_W
4991
0
    4U, // AVE_U_B
4992
0
    4U, // AVE_U_D
4993
0
    4U, // AVE_U_H
4994
0
    4U, // AVE_U_W
4995
0
    0U, // AddiuRxImmX16
4996
0
    0U, // AddiuRxPcImmX16
4997
0
    1U, // AddiuRxRxImm16
4998
0
    0U, // AddiuRxRxImmX16
4999
0
    0U, // AddiuRxRyOffMemX16
5000
0
    0U, // AddiuSpImm16
5001
0
    0U, // AddiuSpImmX16
5002
0
    4U, // AdduRxRyRz16
5003
0
    0U, // AndRxRxRy16
5004
0
    0U, // B16_MM
5005
0
    4U, // BADDu
5006
0
    0U, // BAL
5007
0
    0U, // BALC
5008
0
    0U, // BALC_MMR6
5009
0
    24U,  // BALIGN
5010
0
    24U,  // BALIGN_MMR2
5011
0
    0U, // BBIT0
5012
0
    0U, // BBIT032
5013
0
    0U, // BBIT1
5014
0
    0U, // BBIT132
5015
0
    0U, // BC
5016
0
    0U, // BC16_MMR6
5017
0
    0U, // BC1EQZ
5018
0
    0U, // BC1EQZC_MMR6
5019
0
    0U, // BC1F
5020
0
    0U, // BC1FL
5021
0
    0U, // BC1F_MM
5022
0
    0U, // BC1NEZ
5023
0
    0U, // BC1NEZC_MMR6
5024
0
    0U, // BC1T
5025
0
    0U, // BC1TL
5026
0
    0U, // BC1T_MM
5027
0
    0U, // BC2EQZ
5028
0
    0U, // BC2EQZC_MMR6
5029
0
    0U, // BC2NEZ
5030
0
    0U, // BC2NEZC_MMR6
5031
0
    8U, // BCLRI_B
5032
0
    28U,  // BCLRI_D
5033
0
    32U,  // BCLRI_H
5034
0
    12U,  // BCLRI_W
5035
0
    4U, // BCLR_B
5036
0
    4U, // BCLR_D
5037
0
    4U, // BCLR_H
5038
0
    4U, // BCLR_W
5039
0
    0U, // BC_MMR6
5040
0
    0U, // BEQ
5041
0
    0U, // BEQ64
5042
0
    0U, // BEQC
5043
0
    0U, // BEQC64
5044
0
    0U, // BEQC_MMR6
5045
0
    0U, // BEQL
5046
0
    0U, // BEQZ16_MM
5047
0
    0U, // BEQZALC
5048
0
    0U, // BEQZALC_MMR6
5049
0
    0U, // BEQZC
5050
0
    0U, // BEQZC16_MMR6
5051
0
    0U, // BEQZC64
5052
0
    0U, // BEQZC_MM
5053
0
    0U, // BEQZC_MMR6
5054
0
    0U, // BEQ_MM
5055
0
    0U, // BGEC
5056
0
    0U, // BGEC64
5057
0
    0U, // BGEC_MMR6
5058
0
    0U, // BGEUC
5059
0
    0U, // BGEUC64
5060
0
    0U, // BGEUC_MMR6
5061
0
    0U, // BGEZ
5062
0
    0U, // BGEZ64
5063
0
    0U, // BGEZAL
5064
0
    0U, // BGEZALC
5065
0
    0U, // BGEZALC_MMR6
5066
0
    0U, // BGEZALL
5067
0
    0U, // BGEZALS_MM
5068
0
    0U, // BGEZAL_MM
5069
0
    0U, // BGEZC
5070
0
    0U, // BGEZC64
5071
0
    0U, // BGEZC_MMR6
5072
0
    0U, // BGEZL
5073
0
    0U, // BGEZ_MM
5074
0
    0U, // BGTZ
5075
0
    0U, // BGTZ64
5076
0
    0U, // BGTZALC
5077
0
    0U, // BGTZALC_MMR6
5078
0
    0U, // BGTZC
5079
0
    0U, // BGTZC64
5080
0
    0U, // BGTZC_MMR6
5081
0
    0U, // BGTZL
5082
0
    0U, // BGTZ_MM
5083
0
    36U,  // BINSLI_B
5084
0
    40U,  // BINSLI_D
5085
0
    44U,  // BINSLI_H
5086
0
    48U,  // BINSLI_W
5087
0
    52U,  // BINSL_B
5088
0
    52U,  // BINSL_D
5089
0
    52U,  // BINSL_H
5090
0
    52U,  // BINSL_W
5091
0
    36U,  // BINSRI_B
5092
0
    40U,  // BINSRI_D
5093
0
    44U,  // BINSRI_H
5094
0
    48U,  // BINSRI_W
5095
0
    52U,  // BINSR_B
5096
0
    52U,  // BINSR_D
5097
0
    52U,  // BINSR_H
5098
0
    52U,  // BINSR_W
5099
0
    0U, // BITREV
5100
0
    0U, // BITREV_MM
5101
0
    0U, // BITSWAP
5102
0
    0U, // BITSWAP_MMR6
5103
0
    0U, // BLEZ
5104
0
    0U, // BLEZ64
5105
0
    0U, // BLEZALC
5106
0
    0U, // BLEZALC_MMR6
5107
0
    0U, // BLEZC
5108
0
    0U, // BLEZC64
5109
0
    0U, // BLEZC_MMR6
5110
0
    0U, // BLEZL
5111
0
    0U, // BLEZ_MM
5112
0
    0U, // BLTC
5113
0
    0U, // BLTC64
5114
0
    0U, // BLTC_MMR6
5115
0
    0U, // BLTUC
5116
0
    0U, // BLTUC64
5117
0
    0U, // BLTUC_MMR6
5118
0
    0U, // BLTZ
5119
0
    0U, // BLTZ64
5120
0
    0U, // BLTZAL
5121
0
    0U, // BLTZALC
5122
0
    0U, // BLTZALC_MMR6
5123
0
    0U, // BLTZALL
5124
0
    0U, // BLTZALS_MM
5125
0
    0U, // BLTZAL_MM
5126
0
    0U, // BLTZC
5127
0
    0U, // BLTZC64
5128
0
    0U, // BLTZC_MMR6
5129
0
    0U, // BLTZL
5130
0
    0U, // BLTZ_MM
5131
0
    56U,  // BMNZI_B
5132
0
    52U,  // BMNZ_V
5133
0
    56U,  // BMZI_B
5134
0
    52U,  // BMZ_V
5135
0
    0U, // BNE
5136
0
    0U, // BNE64
5137
0
    0U, // BNEC
5138
0
    0U, // BNEC64
5139
0
    0U, // BNEC_MMR6
5140
0
    8U, // BNEGI_B
5141
0
    28U,  // BNEGI_D
5142
0
    32U,  // BNEGI_H
5143
0
    12U,  // BNEGI_W
5144
0
    4U, // BNEG_B
5145
0
    4U, // BNEG_D
5146
0
    4U, // BNEG_H
5147
0
    4U, // BNEG_W
5148
0
    0U, // BNEL
5149
0
    0U, // BNEZ16_MM
5150
0
    0U, // BNEZALC
5151
0
    0U, // BNEZALC_MMR6
5152
0
    0U, // BNEZC
5153
0
    0U, // BNEZC16_MMR6
5154
0
    0U, // BNEZC64
5155
0
    0U, // BNEZC_MM
5156
0
    0U, // BNEZC_MMR6
5157
0
    0U, // BNE_MM
5158
0
    0U, // BNVC
5159
0
    0U, // BNVC_MMR6
5160
0
    0U, // BNZ_B
5161
0
    0U, // BNZ_D
5162
0
    0U, // BNZ_H
5163
0
    0U, // BNZ_V
5164
0
    0U, // BNZ_W
5165
0
    0U, // BOVC
5166
0
    0U, // BOVC_MMR6
5167
0
    0U, // BPOSGE32
5168
0
    0U, // BPOSGE32C_MMR3
5169
0
    0U, // BPOSGE32_MM
5170
0
    0U, // BREAK
5171
0
    0U, // BREAK16_MM
5172
0
    0U, // BREAK16_MMR6
5173
0
    0U, // BREAK_MM
5174
0
    0U, // BREAK_MMR6
5175
0
    56U,  // BSELI_B
5176
0
    52U,  // BSEL_V
5177
0
    8U, // BSETI_B
5178
0
    28U,  // BSETI_D
5179
0
    32U,  // BSETI_H
5180
0
    12U,  // BSETI_W
5181
0
    4U, // BSET_B
5182
0
    4U, // BSET_D
5183
0
    4U, // BSET_H
5184
0
    4U, // BSET_W
5185
0
    0U, // BZ_B
5186
0
    0U, // BZ_D
5187
0
    0U, // BZ_H
5188
0
    0U, // BZ_V
5189
0
    0U, // BZ_W
5190
0
    1U, // BeqzRxImm16
5191
0
    0U, // BeqzRxImmX16
5192
0
    0U, // Bimm16
5193
0
    0U, // BimmX16
5194
0
    1U, // BnezRxImm16
5195
0
    0U, // BnezRxImmX16
5196
0
    0U, // Break16
5197
0
    0U, // Bteqz16
5198
0
    0U, // BteqzX16
5199
0
    0U, // Btnez16
5200
0
    0U, // BtnezX16
5201
0
    0U, // CACHE
5202
0
    0U, // CACHEE
5203
0
    0U, // CACHEE_MM
5204
0
    0U, // CACHE_MM
5205
0
    0U, // CACHE_MMR6
5206
0
    0U, // CACHE_R6
5207
0
    0U, // CEIL_L_D64
5208
0
    0U, // CEIL_L_D_MMR6
5209
0
    0U, // CEIL_L_S
5210
0
    0U, // CEIL_L_S_MMR6
5211
0
    0U, // CEIL_W_D32
5212
0
    0U, // CEIL_W_D64
5213
0
    0U, // CEIL_W_D_MMR6
5214
0
    0U, // CEIL_W_MM
5215
0
    0U, // CEIL_W_S
5216
0
    0U, // CEIL_W_S_MM
5217
0
    0U, // CEIL_W_S_MMR6
5218
0
    4U, // CEQI_B
5219
0
    4U, // CEQI_D
5220
0
    4U, // CEQI_H
5221
0
    4U, // CEQI_W
5222
0
    4U, // CEQ_B
5223
0
    4U, // CEQ_D
5224
0
    4U, // CEQ_H
5225
0
    4U, // CEQ_W
5226
0
    0U, // CFC1
5227
0
    0U, // CFC1_MM
5228
0
    0U, // CFC2_MM
5229
0
    0U, // CFCMSA
5230
0
    1164U,  // CINS
5231
0
    1164U,  // CINS32
5232
0
    1164U,  // CINS64_32
5233
0
    1164U,  // CINS_i32
5234
0
    0U, // CLASS_D
5235
0
    0U, // CLASS_D_MMR6
5236
0
    0U, // CLASS_S
5237
0
    0U, // CLASS_S_MMR6
5238
0
    4U, // CLEI_S_B
5239
0
    4U, // CLEI_S_D
5240
0
    4U, // CLEI_S_H
5241
0
    4U, // CLEI_S_W
5242
0
    12U,  // CLEI_U_B
5243
0
    12U,  // CLEI_U_D
5244
0
    12U,  // CLEI_U_H
5245
0
    12U,  // CLEI_U_W
5246
0
    4U, // CLE_S_B
5247
0
    4U, // CLE_S_D
5248
0
    4U, // CLE_S_H
5249
0
    4U, // CLE_S_W
5250
0
    4U, // CLE_U_B
5251
0
    4U, // CLE_U_D
5252
0
    4U, // CLE_U_H
5253
0
    4U, // CLE_U_W
5254
0
    0U, // CLO
5255
0
    0U, // CLO_MM
5256
0
    0U, // CLO_MMR6
5257
0
    0U, // CLO_R6
5258
0
    4U, // CLTI_S_B
5259
0
    4U, // CLTI_S_D
5260
0
    4U, // CLTI_S_H
5261
0
    4U, // CLTI_S_W
5262
0
    12U,  // CLTI_U_B
5263
0
    12U,  // CLTI_U_D
5264
0
    12U,  // CLTI_U_H
5265
0
    12U,  // CLTI_U_W
5266
0
    4U, // CLT_S_B
5267
0
    4U, // CLT_S_D
5268
0
    4U, // CLT_S_H
5269
0
    4U, // CLT_S_W
5270
0
    4U, // CLT_U_B
5271
0
    4U, // CLT_U_D
5272
0
    4U, // CLT_U_H
5273
0
    4U, // CLT_U_W
5274
0
    0U, // CLZ
5275
0
    0U, // CLZ_MM
5276
0
    0U, // CLZ_MMR6
5277
0
    0U, // CLZ_R6
5278
0
    4U, // CMPGDU_EQ_QB
5279
0
    4U, // CMPGDU_EQ_QB_MMR2
5280
0
    4U, // CMPGDU_LE_QB
5281
0
    4U, // CMPGDU_LE_QB_MMR2
5282
0
    4U, // CMPGDU_LT_QB
5283
0
    4U, // CMPGDU_LT_QB_MMR2
5284
0
    4U, // CMPGU_EQ_QB
5285
0
    4U, // CMPGU_EQ_QB_MM
5286
0
    4U, // CMPGU_LE_QB
5287
0
    4U, // CMPGU_LE_QB_MM
5288
0
    4U, // CMPGU_LT_QB
5289
0
    4U, // CMPGU_LT_QB_MM
5290
0
    0U, // CMPU_EQ_QB
5291
0
    0U, // CMPU_EQ_QB_MM
5292
0
    0U, // CMPU_LE_QB
5293
0
    0U, // CMPU_LE_QB_MM
5294
0
    0U, // CMPU_LT_QB
5295
0
    0U, // CMPU_LT_QB_MM
5296
0
    4U, // CMP_AF_D_MMR6
5297
0
    4U, // CMP_AF_S_MMR6
5298
0
    4U, // CMP_EQ_D
5299
0
    4U, // CMP_EQ_D_MMR6
5300
0
    0U, // CMP_EQ_PH
5301
0
    0U, // CMP_EQ_PH_MM
5302
0
    4U, // CMP_EQ_S
5303
0
    4U, // CMP_EQ_S_MMR6
5304
0
    4U, // CMP_F_D
5305
0
    4U, // CMP_F_S
5306
0
    4U, // CMP_LE_D
5307
0
    4U, // CMP_LE_D_MMR6
5308
0
    0U, // CMP_LE_PH
5309
0
    0U, // CMP_LE_PH_MM
5310
0
    4U, // CMP_LE_S
5311
0
    4U, // CMP_LE_S_MMR6
5312
0
    4U, // CMP_LT_D
5313
0
    4U, // CMP_LT_D_MMR6
5314
0
    0U, // CMP_LT_PH
5315
0
    0U, // CMP_LT_PH_MM
5316
0
    4U, // CMP_LT_S
5317
0
    4U, // CMP_LT_S_MMR6
5318
0
    4U, // CMP_SAF_D
5319
0
    4U, // CMP_SAF_D_MMR6
5320
0
    4U, // CMP_SAF_S
5321
0
    4U, // CMP_SAF_S_MMR6
5322
0
    4U, // CMP_SEQ_D
5323
0
    4U, // CMP_SEQ_D_MMR6
5324
0
    4U, // CMP_SEQ_S
5325
0
    4U, // CMP_SEQ_S_MMR6
5326
0
    4U, // CMP_SLE_D
5327
0
    4U, // CMP_SLE_D_MMR6
5328
0
    4U, // CMP_SLE_S
5329
0
    4U, // CMP_SLE_S_MMR6
5330
0
    4U, // CMP_SLT_D
5331
0
    4U, // CMP_SLT_D_MMR6
5332
0
    4U, // CMP_SLT_S
5333
0
    4U, // CMP_SLT_S_MMR6
5334
0
    4U, // CMP_SUEQ_D
5335
0
    4U, // CMP_SUEQ_D_MMR6
5336
0
    4U, // CMP_SUEQ_S
5337
0
    4U, // CMP_SUEQ_S_MMR6
5338
0
    4U, // CMP_SULE_D
5339
0
    4U, // CMP_SULE_D_MMR6
5340
0
    4U, // CMP_SULE_S
5341
0
    4U, // CMP_SULE_S_MMR6
5342
0
    4U, // CMP_SULT_D
5343
0
    4U, // CMP_SULT_D_MMR6
5344
0
    4U, // CMP_SULT_S
5345
0
    4U, // CMP_SULT_S_MMR6
5346
0
    4U, // CMP_SUN_D
5347
0
    4U, // CMP_SUN_D_MMR6
5348
0
    4U, // CMP_SUN_S
5349
0
    4U, // CMP_SUN_S_MMR6
5350
0
    4U, // CMP_UEQ_D
5351
0
    4U, // CMP_UEQ_D_MMR6
5352
0
    4U, // CMP_UEQ_S
5353
0
    4U, // CMP_UEQ_S_MMR6
5354
0
    4U, // CMP_ULE_D
5355
0
    4U, // CMP_ULE_D_MMR6
5356
0
    4U, // CMP_ULE_S
5357
0
    4U, // CMP_ULE_S_MMR6
5358
0
    4U, // CMP_ULT_D
5359
0
    4U, // CMP_ULT_D_MMR6
5360
0
    4U, // CMP_ULT_S
5361
0
    4U, // CMP_ULT_S_MMR6
5362
0
    4U, // CMP_UN_D
5363
0
    4U, // CMP_UN_D_MMR6
5364
0
    4U, // CMP_UN_S
5365
0
    4U, // CMP_UN_S_MMR6
5366
0
    289U, // COPY_S_B
5367
0
    317U, // COPY_S_D
5368
0
    265U, // COPY_S_H
5369
0
    281U, // COPY_S_W
5370
0
    289U, // COPY_U_B
5371
0
    265U, // COPY_U_H
5372
0
    281U, // COPY_U_W
5373
0
    4U, // CRC32B
5374
0
    4U, // CRC32CB
5375
0
    4U, // CRC32CD
5376
0
    4U, // CRC32CH
5377
0
    4U, // CRC32CW
5378
0
    4U, // CRC32D
5379
0
    4U, // CRC32H
5380
0
    4U, // CRC32W
5381
0
    0U, // CTC1
5382
0
    0U, // CTC1_MM
5383
0
    0U, // CTC2_MM
5384
0
    0U, // CTCMSA
5385
0
    0U, // CVT_D32_S
5386
0
    0U, // CVT_D32_S_MM
5387
0
    0U, // CVT_D32_W
5388
0
    0U, // CVT_D32_W_MM
5389
0
    0U, // CVT_D64_L
5390
0
    0U, // CVT_D64_S
5391
0
    0U, // CVT_D64_S_MM
5392
0
    0U, // CVT_D64_W
5393
0
    0U, // CVT_D64_W_MM
5394
0
    0U, // CVT_D_L_MMR6
5395
0
    0U, // CVT_L_D64
5396
0
    0U, // CVT_L_D64_MM
5397
0
    0U, // CVT_L_D_MMR6
5398
0
    0U, // CVT_L_S
5399
0
    0U, // CVT_L_S_MM
5400
0
    0U, // CVT_L_S_MMR6
5401
0
    0U, // CVT_PS_PW64
5402
0
    4U, // CVT_PS_S64
5403
0
    0U, // CVT_PW_PS64
5404
0
    0U, // CVT_S_D32
5405
0
    0U, // CVT_S_D32_MM
5406
0
    0U, // CVT_S_D64
5407
0
    0U, // CVT_S_D64_MM
5408
0
    0U, // CVT_S_L
5409
0
    0U, // CVT_S_L_MMR6
5410
0
    0U, // CVT_S_PL64
5411
0
    0U, // CVT_S_PU64
5412
0
    0U, // CVT_S_W
5413
0
    0U, // CVT_S_W_MM
5414
0
    0U, // CVT_S_W_MMR6
5415
0
    0U, // CVT_W_D32
5416
0
    0U, // CVT_W_D32_MM
5417
0
    0U, // CVT_W_D64
5418
0
    0U, // CVT_W_D64_MM
5419
0
    0U, // CVT_W_S
5420
0
    0U, // CVT_W_S_MM
5421
0
    0U, // CVT_W_S_MMR6
5422
0
    4U, // C_EQ_D32
5423
0
    4U, // C_EQ_D32_MM
5424
0
    4U, // C_EQ_D64
5425
0
    4U, // C_EQ_D64_MM
5426
0
    4U, // C_EQ_S
5427
0
    4U, // C_EQ_S_MM
5428
0
    4U, // C_F_D32
5429
0
    4U, // C_F_D32_MM
5430
0
    4U, // C_F_D64
5431
0
    4U, // C_F_D64_MM
5432
0
    4U, // C_F_S
5433
0
    4U, // C_F_S_MM
5434
0
    4U, // C_LE_D32
5435
0
    4U, // C_LE_D32_MM
5436
0
    4U, // C_LE_D64
5437
0
    4U, // C_LE_D64_MM
5438
0
    4U, // C_LE_S
5439
0
    4U, // C_LE_S_MM
5440
0
    4U, // C_LT_D32
5441
0
    4U, // C_LT_D32_MM
5442
0
    4U, // C_LT_D64
5443
0
    4U, // C_LT_D64_MM
5444
0
    4U, // C_LT_S
5445
0
    4U, // C_LT_S_MM
5446
0
    4U, // C_NGE_D32
5447
0
    4U, // C_NGE_D32_MM
5448
0
    4U, // C_NGE_D64
5449
0
    4U, // C_NGE_D64_MM
5450
0
    4U, // C_NGE_S
5451
0
    4U, // C_NGE_S_MM
5452
0
    4U, // C_NGLE_D32
5453
0
    4U, // C_NGLE_D32_MM
5454
0
    4U, // C_NGLE_D64
5455
0
    4U, // C_NGLE_D64_MM
5456
0
    4U, // C_NGLE_S
5457
0
    4U, // C_NGLE_S_MM
5458
0
    4U, // C_NGL_D32
5459
0
    4U, // C_NGL_D32_MM
5460
0
    4U, // C_NGL_D64
5461
0
    4U, // C_NGL_D64_MM
5462
0
    4U, // C_NGL_S
5463
0
    4U, // C_NGL_S_MM
5464
0
    4U, // C_NGT_D32
5465
0
    4U, // C_NGT_D32_MM
5466
0
    4U, // C_NGT_D64
5467
0
    4U, // C_NGT_D64_MM
5468
0
    4U, // C_NGT_S
5469
0
    4U, // C_NGT_S_MM
5470
0
    4U, // C_OLE_D32
5471
0
    4U, // C_OLE_D32_MM
5472
0
    4U, // C_OLE_D64
5473
0
    4U, // C_OLE_D64_MM
5474
0
    4U, // C_OLE_S
5475
0
    4U, // C_OLE_S_MM
5476
0
    4U, // C_OLT_D32
5477
0
    4U, // C_OLT_D32_MM
5478
0
    4U, // C_OLT_D64
5479
0
    4U, // C_OLT_D64_MM
5480
0
    4U, // C_OLT_S
5481
0
    4U, // C_OLT_S_MM
5482
0
    4U, // C_SEQ_D32
5483
0
    4U, // C_SEQ_D32_MM
5484
0
    4U, // C_SEQ_D64
5485
0
    4U, // C_SEQ_D64_MM
5486
0
    4U, // C_SEQ_S
5487
0
    4U, // C_SEQ_S_MM
5488
0
    4U, // C_SF_D32
5489
0
    4U, // C_SF_D32_MM
5490
0
    4U, // C_SF_D64
5491
0
    4U, // C_SF_D64_MM
5492
0
    4U, // C_SF_S
5493
0
    4U, // C_SF_S_MM
5494
0
    4U, // C_UEQ_D32
5495
0
    4U, // C_UEQ_D32_MM
5496
0
    4U, // C_UEQ_D64
5497
0
    4U, // C_UEQ_D64_MM
5498
0
    4U, // C_UEQ_S
5499
0
    4U, // C_UEQ_S_MM
5500
0
    4U, // C_ULE_D32
5501
0
    4U, // C_ULE_D32_MM
5502
0
    4U, // C_ULE_D64
5503
0
    4U, // C_ULE_D64_MM
5504
0
    4U, // C_ULE_S
5505
0
    4U, // C_ULE_S_MM
5506
0
    4U, // C_ULT_D32
5507
0
    4U, // C_ULT_D32_MM
5508
0
    4U, // C_ULT_D64
5509
0
    4U, // C_ULT_D64_MM
5510
0
    4U, // C_ULT_S
5511
0
    4U, // C_ULT_S_MM
5512
0
    4U, // C_UN_D32
5513
0
    4U, // C_UN_D32_MM
5514
0
    4U, // C_UN_D64
5515
0
    4U, // C_UN_D64_MM
5516
0
    4U, // C_UN_S
5517
0
    4U, // C_UN_S_MM
5518
0
    0U, // CmpRxRy16
5519
0
    1U, // CmpiRxImm16
5520
0
    0U, // CmpiRxImmX16
5521
0
    4U, // DADD
5522
0
    4U, // DADDi
5523
0
    4U, // DADDiu
5524
0
    4U, // DADDu
5525
0
    20U,  // DAHI
5526
0
    2180U,  // DALIGN
5527
0
    20U,  // DATI
5528
0
    20U,  // DAUI
5529
0
    0U, // DBITSWAP
5530
0
    0U, // DCLO
5531
0
    0U, // DCLO_R6
5532
0
    0U, // DCLZ
5533
0
    0U, // DCLZ_R6
5534
0
    4U, // DDIV
5535
0
    4U, // DDIVU
5536
0
    0U, // DERET
5537
0
    0U, // DERET_MM
5538
0
    0U, // DERET_MMR6
5539
0
    3228U,  // DEXT
5540
0
    4252U,  // DEXT64_32
5541
0
    5260U,  // DEXTM
5542
0
    448U, // DEXTU
5543
0
    0U, // DI
5544
0
    6300U,  // DINS
5545
0
    7308U,  // DINSM
5546
0
    576U, // DINSU
5547
0
    4U, // DIV
5548
0
    4U, // DIVU
5549
0
    4U, // DIVU_MMR6
5550
0
    4U, // DIV_MMR6
5551
0
    4U, // DIV_S_B
5552
0
    4U, // DIV_S_D
5553
0
    4U, // DIV_S_H
5554
0
    4U, // DIV_S_W
5555
0
    4U, // DIV_U_B
5556
0
    4U, // DIV_U_D
5557
0
    4U, // DIV_U_H
5558
0
    4U, // DIV_U_W
5559
0
    0U, // DI_MM
5560
0
    0U, // DI_MMR6
5561
0
    8324U,  // DLSA
5562
0
    8324U,  // DLSA_R6
5563
0
    8U, // DMFC0
5564
0
    0U, // DMFC1
5565
0
    8U, // DMFC2
5566
0
    0U, // DMFC2_OCTEON
5567
0
    8U, // DMFGC0
5568
0
    4U, // DMOD
5569
0
    4U, // DMODU
5570
0
    0U, // DMT
5571
0
    0U, // DMTC0
5572
0
    0U, // DMTC1
5573
0
    0U, // DMTC2
5574
0
    0U, // DMTC2_OCTEON
5575
0
    0U, // DMTGC0
5576
0
    4U, // DMUH
5577
0
    4U, // DMUHU
5578
0
    4U, // DMUL
5579
0
    0U, // DMULT
5580
0
    0U, // DMULTu
5581
0
    4U, // DMULU
5582
0
    4U, // DMUL_R6
5583
0
    4U, // DOTP_S_D
5584
0
    4U, // DOTP_S_H
5585
0
    4U, // DOTP_S_W
5586
0
    4U, // DOTP_U_D
5587
0
    4U, // DOTP_U_H
5588
0
    4U, // DOTP_U_W
5589
0
    52U,  // DPADD_S_D
5590
0
    52U,  // DPADD_S_H
5591
0
    52U,  // DPADD_S_W
5592
0
    52U,  // DPADD_U_D
5593
0
    52U,  // DPADD_U_H
5594
0
    52U,  // DPADD_U_W
5595
0
    4U, // DPAQX_SA_W_PH
5596
0
    4U, // DPAQX_SA_W_PH_MMR2
5597
0
    4U, // DPAQX_S_W_PH
5598
0
    4U, // DPAQX_S_W_PH_MMR2
5599
0
    4U, // DPAQ_SA_L_W
5600
0
    4U, // DPAQ_SA_L_W_MM
5601
0
    4U, // DPAQ_S_W_PH
5602
0
    4U, // DPAQ_S_W_PH_MM
5603
0
    4U, // DPAU_H_QBL
5604
0
    4U, // DPAU_H_QBL_MM
5605
0
    4U, // DPAU_H_QBR
5606
0
    4U, // DPAU_H_QBR_MM
5607
0
    4U, // DPAX_W_PH
5608
0
    4U, // DPAX_W_PH_MMR2
5609
0
    4U, // DPA_W_PH
5610
0
    4U, // DPA_W_PH_MMR2
5611
0
    0U, // DPOP
5612
0
    4U, // DPSQX_SA_W_PH
5613
0
    4U, // DPSQX_SA_W_PH_MMR2
5614
0
    4U, // DPSQX_S_W_PH
5615
0
    4U, // DPSQX_S_W_PH_MMR2
5616
0
    4U, // DPSQ_SA_L_W
5617
0
    4U, // DPSQ_SA_L_W_MM
5618
0
    4U, // DPSQ_S_W_PH
5619
0
    4U, // DPSQ_S_W_PH_MM
5620
0
    52U,  // DPSUB_S_D
5621
0
    52U,  // DPSUB_S_H
5622
0
    52U,  // DPSUB_S_W
5623
0
    52U,  // DPSUB_U_D
5624
0
    52U,  // DPSUB_U_H
5625
0
    52U,  // DPSUB_U_W
5626
0
    4U, // DPSU_H_QBL
5627
0
    4U, // DPSU_H_QBL_MM
5628
0
    4U, // DPSU_H_QBR
5629
0
    4U, // DPSU_H_QBR_MM
5630
0
    4U, // DPSX_W_PH
5631
0
    4U, // DPSX_W_PH_MMR2
5632
0
    4U, // DPS_W_PH
5633
0
    4U, // DPS_W_PH_MMR2
5634
0
    28U,  // DROTR
5635
0
    12U,  // DROTR32
5636
0
    4U, // DROTRV
5637
0
    0U, // DSBH
5638
0
    0U, // DSDIV
5639
0
    0U, // DSHD
5640
0
    28U,  // DSLL
5641
0
    12U,  // DSLL32
5642
0
    1U, // DSLL64_32
5643
0
    4U, // DSLLV
5644
0
    28U,  // DSRA
5645
0
    12U,  // DSRA32
5646
0
    4U, // DSRAV
5647
0
    28U,  // DSRL
5648
0
    12U,  // DSRL32
5649
0
    4U, // DSRLV
5650
0
    4U, // DSUB
5651
0
    4U, // DSUBu
5652
0
    0U, // DUDIV
5653
0
    0U, // DVP
5654
0
    0U, // DVPE
5655
0
    0U, // DVP_MMR6
5656
0
    0U, // DivRxRy16
5657
0
    0U, // DivuRxRy16
5658
0
    0U, // EHB
5659
0
    0U, // EHB_MM
5660
0
    0U, // EHB_MMR6
5661
0
    0U, // EI
5662
0
    0U, // EI_MM
5663
0
    0U, // EI_MMR6
5664
0
    0U, // EMT
5665
0
    0U, // ERET
5666
0
    0U, // ERETNC
5667
0
    0U, // ERETNC_MMR6
5668
0
    0U, // ERET_MM
5669
0
    0U, // ERET_MMR6
5670
0
    0U, // EVP
5671
0
    0U, // EVPE
5672
0
    0U, // EVP_MMR6
5673
0
    4236U,  // EXT
5674
0
    12U,  // EXTP
5675
0
    12U,  // EXTPDP
5676
0
    4U, // EXTPDPV
5677
0
    4U, // EXTPDPV_MM
5678
0
    12U,  // EXTPDP_MM
5679
0
    4U, // EXTPV
5680
0
    4U, // EXTPV_MM
5681
0
    12U,  // EXTP_MM
5682
0
    4U, // EXTRV_RS_W
5683
0
    4U, // EXTRV_RS_W_MM
5684
0
    4U, // EXTRV_R_W
5685
0
    4U, // EXTRV_R_W_MM
5686
0
    4U, // EXTRV_S_H
5687
0
    4U, // EXTRV_S_H_MM
5688
0
    4U, // EXTRV_W
5689
0
    4U, // EXTRV_W_MM
5690
0
    12U,  // EXTR_RS_W
5691
0
    12U,  // EXTR_RS_W_MM
5692
0
    12U,  // EXTR_R_W
5693
0
    12U,  // EXTR_R_W_MM
5694
0
    12U,  // EXTR_S_H
5695
0
    12U,  // EXTR_S_H_MM
5696
0
    12U,  // EXTR_W
5697
0
    12U,  // EXTR_W_MM
5698
0
    1164U,  // EXTS
5699
0
    1164U,  // EXTS32
5700
0
    4236U,  // EXT_MM
5701
0
    4236U,  // EXT_MMR6
5702
0
    0U, // FABS_D32
5703
0
    0U, // FABS_D32_MM
5704
0
    0U, // FABS_D64
5705
0
    0U, // FABS_D64_MM
5706
0
    0U, // FABS_S
5707
0
    0U, // FABS_S_MM
5708
0
    4U, // FADD_D
5709
0
    4U, // FADD_D32
5710
0
    4U, // FADD_D32_MM
5711
0
    4U, // FADD_D64
5712
0
    4U, // FADD_D64_MM
5713
0
    4U, // FADD_PS64
5714
0
    4U, // FADD_S
5715
0
    4U, // FADD_S_MM
5716
0
    68U,  // FADD_S_MMR6
5717
0
    4U, // FADD_W
5718
0
    4U, // FCAF_D
5719
0
    4U, // FCAF_W
5720
0
    4U, // FCEQ_D
5721
0
    4U, // FCEQ_W
5722
0
    0U, // FCLASS_D
5723
0
    0U, // FCLASS_W
5724
0
    4U, // FCLE_D
5725
0
    4U, // FCLE_W
5726
0
    4U, // FCLT_D
5727
0
    4U, // FCLT_W
5728
0
    0U, // FCMP_D32
5729
0
    0U, // FCMP_D32_MM
5730
0
    0U, // FCMP_D64
5731
0
    0U, // FCMP_S32
5732
0
    0U, // FCMP_S32_MM
5733
0
    4U, // FCNE_D
5734
0
    4U, // FCNE_W
5735
0
    4U, // FCOR_D
5736
0
    4U, // FCOR_W
5737
0
    4U, // FCUEQ_D
5738
0
    4U, // FCUEQ_W
5739
0
    4U, // FCULE_D
5740
0
    4U, // FCULE_W
5741
0
    4U, // FCULT_D
5742
0
    4U, // FCULT_W
5743
0
    4U, // FCUNE_D
5744
0
    4U, // FCUNE_W
5745
0
    4U, // FCUN_D
5746
0
    4U, // FCUN_W
5747
0
    4U, // FDIV_D
5748
0
    4U, // FDIV_D32
5749
0
    4U, // FDIV_D32_MM
5750
0
    4U, // FDIV_D64
5751
0
    4U, // FDIV_D64_MM
5752
0
    4U, // FDIV_S
5753
0
    4U, // FDIV_S_MM
5754
0
    68U,  // FDIV_S_MMR6
5755
0
    4U, // FDIV_W
5756
0
    4U, // FEXDO_H
5757
0
    4U, // FEXDO_W
5758
0
    4U, // FEXP2_D
5759
0
    4U, // FEXP2_W
5760
0
    0U, // FEXUPL_D
5761
0
    0U, // FEXUPL_W
5762
0
    0U, // FEXUPR_D
5763
0
    0U, // FEXUPR_W
5764
0
    0U, // FFINT_S_D
5765
0
    0U, // FFINT_S_W
5766
0
    0U, // FFINT_U_D
5767
0
    0U, // FFINT_U_W
5768
0
    0U, // FFQL_D
5769
0
    0U, // FFQL_W
5770
0
    0U, // FFQR_D
5771
0
    0U, // FFQR_W
5772
0
    0U, // FILL_B
5773
0
    0U, // FILL_D
5774
0
    0U, // FILL_H
5775
0
    0U, // FILL_W
5776
0
    0U, // FLOG2_D
5777
0
    0U, // FLOG2_W
5778
0
    0U, // FLOOR_L_D64
5779
0
    0U, // FLOOR_L_D_MMR6
5780
0
    0U, // FLOOR_L_S
5781
0
    0U, // FLOOR_L_S_MMR6
5782
0
    0U, // FLOOR_W_D32
5783
0
    0U, // FLOOR_W_D64
5784
0
    0U, // FLOOR_W_D_MMR6
5785
0
    0U, // FLOOR_W_MM
5786
0
    0U, // FLOOR_W_S
5787
0
    0U, // FLOOR_W_S_MM
5788
0
    0U, // FLOOR_W_S_MMR6
5789
0
    52U,  // FMADD_D
5790
0
    52U,  // FMADD_W
5791
0
    4U, // FMAX_A_D
5792
0
    4U, // FMAX_A_W
5793
0
    4U, // FMAX_D
5794
0
    4U, // FMAX_W
5795
0
    4U, // FMIN_A_D
5796
0
    4U, // FMIN_A_W
5797
0
    4U, // FMIN_D
5798
0
    4U, // FMIN_W
5799
0
    0U, // FMOV_D32
5800
0
    0U, // FMOV_D32_MM
5801
0
    0U, // FMOV_D64
5802
0
    0U, // FMOV_D64_MM
5803
0
    0U, // FMOV_D_MMR6
5804
0
    0U, // FMOV_S
5805
0
    0U, // FMOV_S_MM
5806
0
    0U, // FMOV_S_MMR6
5807
0
    52U,  // FMSUB_D
5808
0
    52U,  // FMSUB_W
5809
0
    4U, // FMUL_D
5810
0
    4U, // FMUL_D32
5811
0
    4U, // FMUL_D32_MM
5812
0
    4U, // FMUL_D64
5813
0
    4U, // FMUL_D64_MM
5814
0
    4U, // FMUL_PS64
5815
0
    4U, // FMUL_S
5816
0
    4U, // FMUL_S_MM
5817
0
    68U,  // FMUL_S_MMR6
5818
0
    4U, // FMUL_W
5819
0
    0U, // FNEG_D32
5820
0
    0U, // FNEG_D32_MM
5821
0
    0U, // FNEG_D64
5822
0
    0U, // FNEG_D64_MM
5823
0
    0U, // FNEG_S
5824
0
    0U, // FNEG_S_MM
5825
0
    0U, // FNEG_S_MMR6
5826
0
    1U, // FORK
5827
0
    0U, // FRCP_D
5828
0
    0U, // FRCP_W
5829
0
    0U, // FRINT_D
5830
0
    0U, // FRINT_W
5831
0
    0U, // FRSQRT_D
5832
0
    0U, // FRSQRT_W
5833
0
    4U, // FSAF_D
5834
0
    4U, // FSAF_W
5835
0
    4U, // FSEQ_D
5836
0
    4U, // FSEQ_W
5837
0
    4U, // FSLE_D
5838
0
    4U, // FSLE_W
5839
0
    4U, // FSLT_D
5840
0
    4U, // FSLT_W
5841
0
    4U, // FSNE_D
5842
0
    4U, // FSNE_W
5843
0
    4U, // FSOR_D
5844
0
    4U, // FSOR_W
5845
0
    0U, // FSQRT_D
5846
0
    0U, // FSQRT_D32
5847
0
    0U, // FSQRT_D32_MM
5848
0
    0U, // FSQRT_D64
5849
0
    0U, // FSQRT_D64_MM
5850
0
    0U, // FSQRT_S
5851
0
    0U, // FSQRT_S_MM
5852
0
    0U, // FSQRT_W
5853
0
    4U, // FSUB_D
5854
0
    4U, // FSUB_D32
5855
0
    4U, // FSUB_D32_MM
5856
0
    4U, // FSUB_D64
5857
0
    4U, // FSUB_D64_MM
5858
0
    4U, // FSUB_PS64
5859
0
    4U, // FSUB_S
5860
0
    4U, // FSUB_S_MM
5861
0
    68U,  // FSUB_S_MMR6
5862
0
    4U, // FSUB_W
5863
0
    4U, // FSUEQ_D
5864
0
    4U, // FSUEQ_W
5865
0
    4U, // FSULE_D
5866
0
    4U, // FSULE_W
5867
0
    4U, // FSULT_D
5868
0
    4U, // FSULT_W
5869
0
    4U, // FSUNE_D
5870
0
    4U, // FSUNE_W
5871
0
    4U, // FSUN_D
5872
0
    4U, // FSUN_W
5873
0
    0U, // FTINT_S_D
5874
0
    0U, // FTINT_S_W
5875
0
    0U, // FTINT_U_D
5876
0
    0U, // FTINT_U_W
5877
0
    4U, // FTQ_H
5878
0
    4U, // FTQ_W
5879
0
    0U, // FTRUNC_S_D
5880
0
    0U, // FTRUNC_S_W
5881
0
    0U, // FTRUNC_U_D
5882
0
    0U, // FTRUNC_U_W
5883
0
    0U, // GINVI
5884
0
    0U, // GINVI_MMR6
5885
0
    0U, // GINVT
5886
0
    0U, // GINVT_MMR6
5887
0
    4U, // HADD_S_D
5888
0
    4U, // HADD_S_H
5889
0
    4U, // HADD_S_W
5890
0
    4U, // HADD_U_D
5891
0
    4U, // HADD_U_H
5892
0
    4U, // HADD_U_W
5893
0
    4U, // HSUB_S_D
5894
0
    4U, // HSUB_S_H
5895
0
    4U, // HSUB_S_W
5896
0
    4U, // HSUB_U_D
5897
0
    4U, // HSUB_U_H
5898
0
    4U, // HSUB_U_W
5899
0
    0U, // HYPCALL
5900
0
    0U, // HYPCALL_MM
5901
0
    4U, // ILVEV_B
5902
0
    4U, // ILVEV_D
5903
0
    4U, // ILVEV_H
5904
0
    4U, // ILVEV_W
5905
0
    4U, // ILVL_B
5906
0
    4U, // ILVL_D
5907
0
    4U, // ILVL_H
5908
0
    4U, // ILVL_W
5909
0
    4U, // ILVOD_B
5910
0
    4U, // ILVOD_D
5911
0
    4U, // ILVOD_H
5912
0
    4U, // ILVOD_W
5913
0
    4U, // ILVR_B
5914
0
    4U, // ILVR_D
5915
0
    4U, // ILVR_H
5916
0
    4U, // ILVR_W
5917
0
    6284U,  // INS
5918
0
    0U, // INSERT_B
5919
0
    0U, // INSERT_D
5920
0
    0U, // INSERT_H
5921
0
    0U, // INSERT_W
5922
0
    0U, // INSV
5923
0
    0U, // INSVE_B
5924
0
    0U, // INSVE_D
5925
0
    0U, // INSVE_H
5926
0
    0U, // INSVE_W
5927
0
    0U, // INSV_MM
5928
0
    6284U,  // INS_MM
5929
0
    6284U,  // INS_MMR6
5930
0
    0U, // J
5931
0
    0U, // JAL
5932
0
    0U, // JALR
5933
0
    0U, // JALR16_MM
5934
0
    0U, // JALR64
5935
0
    0U, // JALRC16_MMR6
5936
0
    0U, // JALRC_HB_MMR6
5937
0
    0U, // JALRC_MMR6
5938
0
    0U, // JALRS16_MM
5939
0
    0U, // JALRS_MM
5940
0
    0U, // JALR_HB
5941
0
    0U, // JALR_HB64
5942
0
    0U, // JALR_MM
5943
0
    0U, // JALS_MM
5944
0
    0U, // JALX
5945
0
    0U, // JALX_MM
5946
0
    0U, // JAL_MM
5947
0
    0U, // JIALC
5948
0
    0U, // JIALC64
5949
0
    0U, // JIALC_MMR6
5950
0
    0U, // JIC
5951
0
    0U, // JIC64
5952
0
    0U, // JIC_MMR6
5953
0
    0U, // JR
5954
0
    0U, // JR16_MM
5955
0
    0U, // JR64
5956
0
    0U, // JRADDIUSP
5957
0
    0U, // JRC16_MM
5958
0
    0U, // JRC16_MMR6
5959
0
    0U, // JRCADDIUSP_MMR6
5960
0
    0U, // JR_HB
5961
0
    0U, // JR_HB64
5962
0
    0U, // JR_HB64_R6
5963
0
    0U, // JR_HB_R6
5964
0
    0U, // JR_MM
5965
0
    0U, // J_MM
5966
0
    0U, // Jal16
5967
0
    0U, // JalB16
5968
0
    0U, // JrRa16
5969
0
    0U, // JrcRa16
5970
0
    0U, // JrcRx16
5971
0
    0U, // JumpLinkReg16
5972
0
    0U, // LB
5973
0
    0U, // LB64
5974
0
    0U, // LBE
5975
0
    0U, // LBE_MM
5976
0
    0U, // LBU16_MM
5977
0
    1U, // LBUX
5978
0
    1U, // LBUX_MM
5979
0
    0U, // LBU_MMR6
5980
0
    0U, // LB_MM
5981
0
    0U, // LB_MMR6
5982
0
    0U, // LBu
5983
0
    0U, // LBu64
5984
0
    0U, // LBuE
5985
0
    0U, // LBuE_MM
5986
0
    0U, // LBu_MM
5987
0
    0U, // LD
5988
0
    0U, // LDC1
5989
0
    0U, // LDC164
5990
0
    0U, // LDC1_D64_MMR6
5991
0
    0U, // LDC1_MM_D32
5992
0
    0U, // LDC1_MM_D64
5993
0
    0U, // LDC2
5994
0
    0U, // LDC2_MMR6
5995
0
    0U, // LDC2_R6
5996
0
    0U, // LDC3
5997
0
    0U, // LDI_B
5998
0
    0U, // LDI_D
5999
0
    0U, // LDI_H
6000
0
    0U, // LDI_W
6001
0
    0U, // LDL
6002
0
    0U, // LDPC
6003
0
    0U, // LDR
6004
0
    1U, // LDXC1
6005
0
    1U, // LDXC164
6006
0
    0U, // LD_B
6007
0
    0U, // LD_D
6008
0
    0U, // LD_H
6009
0
    0U, // LD_W
6010
0
    0U, // LEA_ADDiu
6011
0
    0U, // LEA_ADDiu64
6012
0
    0U, // LEA_ADDiu_MM
6013
0
    0U, // LH
6014
0
    0U, // LH64
6015
0
    0U, // LHE
6016
0
    0U, // LHE_MM
6017
0
    0U, // LHU16_MM
6018
0
    1U, // LHX
6019
0
    1U, // LHX_MM
6020
0
    0U, // LH_MM
6021
0
    0U, // LHu
6022
0
    0U, // LHu64
6023
0
    0U, // LHuE
6024
0
    0U, // LHuE_MM
6025
0
    0U, // LHu_MM
6026
0
    0U, // LI16_MM
6027
0
    0U, // LI16_MMR6
6028
0
    0U, // LL
6029
0
    0U, // LL64
6030
0
    0U, // LL64_R6
6031
0
    0U, // LLD
6032
0
    0U, // LLD_R6
6033
0
    0U, // LLE
6034
0
    0U, // LLE_MM
6035
0
    0U, // LL_MM
6036
0
    0U, // LL_MMR6
6037
0
    0U, // LL_R6
6038
0
    8324U,  // LSA
6039
0
    1U, // LSA_MMR6
6040
0
    8324U,  // LSA_R6
6041
0
    0U, // LUI_MMR6
6042
0
    1U, // LUXC1
6043
0
    1U, // LUXC164
6044
0
    1U, // LUXC1_MM
6045
0
    0U, // LUi
6046
0
    0U, // LUi64
6047
0
    0U, // LUi_MM
6048
0
    0U, // LW
6049
0
    0U, // LW16_MM
6050
0
    0U, // LW64
6051
0
    0U, // LWC1
6052
0
    0U, // LWC1_MM
6053
0
    0U, // LWC2
6054
0
    0U, // LWC2_MMR6
6055
0
    0U, // LWC2_R6
6056
0
    0U, // LWC3
6057
0
    0U, // LWDSP
6058
0
    0U, // LWDSP_MM
6059
0
    0U, // LWE
6060
0
    0U, // LWE_MM
6061
0
    0U, // LWGP_MM
6062
0
    0U, // LWL
6063
0
    0U, // LWL64
6064
0
    0U, // LWLE
6065
0
    0U, // LWLE_MM
6066
0
    0U, // LWL_MM
6067
0
    0U, // LWM16_MM
6068
0
    0U, // LWM16_MMR6
6069
0
    0U, // LWM32_MM
6070
0
    0U, // LWPC
6071
0
    0U, // LWPC_MMR6
6072
0
    0U, // LWP_MM
6073
0
    0U, // LWR
6074
0
    0U, // LWR64
6075
0
    0U, // LWRE
6076
0
    0U, // LWRE_MM
6077
0
    0U, // LWR_MM
6078
0
    0U, // LWSP_MM
6079
0
    0U, // LWUPC
6080
0
    0U, // LWU_MM
6081
0
    1U, // LWX
6082
0
    1U, // LWXC1
6083
0
    1U, // LWXC1_MM
6084
0
    1U, // LWXS_MM
6085
0
    1U, // LWX_MM
6086
0
    0U, // LW_MM
6087
0
    0U, // LW_MMR6
6088
0
    0U, // LWu
6089
0
    0U, // LbRxRyOffMemX16
6090
0
    0U, // LbuRxRyOffMemX16
6091
0
    0U, // LhRxRyOffMemX16
6092
0
    0U, // LhuRxRyOffMemX16
6093
0
    1U, // LiRxImm16
6094
0
    0U, // LiRxImmAlignX16
6095
0
    0U, // LiRxImmX16
6096
0
    1U, // LwRxPcTcp16
6097
0
    0U, // LwRxPcTcpX16
6098
0
    0U, // LwRxRyOffMemX16
6099
0
    0U, // LwRxSpImmX16
6100
0
    0U, // MADD
6101
0
    52U,  // MADDF_D
6102
0
    52U,  // MADDF_D_MMR6
6103
0
    52U,  // MADDF_S
6104
0
    52U,  // MADDF_S_MMR6
6105
0
    52U,  // MADDR_Q_H
6106
0
    52U,  // MADDR_Q_W
6107
0
    0U, // MADDU
6108
0
    4U, // MADDU_DSP
6109
0
    4U, // MADDU_DSP_MM
6110
0
    0U, // MADDU_MM
6111
0
    52U,  // MADDV_B
6112
0
    52U,  // MADDV_D
6113
0
    52U,  // MADDV_H
6114
0
    52U,  // MADDV_W
6115
0
    9348U,  // MADD_D32
6116
0
    9348U,  // MADD_D32_MM
6117
0
    9348U,  // MADD_D64
6118
0
    4U, // MADD_DSP
6119
0
    4U, // MADD_DSP_MM
6120
0
    0U, // MADD_MM
6121
0
    52U,  // MADD_Q_H
6122
0
    52U,  // MADD_Q_W
6123
0
    9348U,  // MADD_S
6124
0
    9348U,  // MADD_S_MM
6125
0
    4U, // MAQ_SA_W_PHL
6126
0
    4U, // MAQ_SA_W_PHL_MM
6127
0
    4U, // MAQ_SA_W_PHR
6128
0
    4U, // MAQ_SA_W_PHR_MM
6129
0
    4U, // MAQ_S_W_PHL
6130
0
    4U, // MAQ_S_W_PHL_MM
6131
0
    4U, // MAQ_S_W_PHR
6132
0
    4U, // MAQ_S_W_PHR_MM
6133
0
    4U, // MAXA_D
6134
0
    4U, // MAXA_D_MMR6
6135
0
    4U, // MAXA_S
6136
0
    4U, // MAXA_S_MMR6
6137
0
    4U, // MAXI_S_B
6138
0
    4U, // MAXI_S_D
6139
0
    4U, // MAXI_S_H
6140
0
    4U, // MAXI_S_W
6141
0
    12U,  // MAXI_U_B
6142
0
    12U,  // MAXI_U_D
6143
0
    12U,  // MAXI_U_H
6144
0
    12U,  // MAXI_U_W
6145
0
    4U, // MAX_A_B
6146
0
    4U, // MAX_A_D
6147
0
    4U, // MAX_A_H
6148
0
    4U, // MAX_A_W
6149
0
    4U, // MAX_D
6150
0
    4U, // MAX_D_MMR6
6151
0
    4U, // MAX_S
6152
0
    4U, // MAX_S_B
6153
0
    4U, // MAX_S_D
6154
0
    4U, // MAX_S_H
6155
0
    4U, // MAX_S_MMR6
6156
0
    4U, // MAX_S_W
6157
0
    4U, // MAX_U_B
6158
0
    4U, // MAX_U_D
6159
0
    4U, // MAX_U_H
6160
0
    4U, // MAX_U_W
6161
0
    8U, // MFC0
6162
0
    8U, // MFC0_MMR6
6163
0
    0U, // MFC1
6164
0
    0U, // MFC1_D64
6165
0
    0U, // MFC1_MM
6166
0
    0U, // MFC1_MMR6
6167
0
    8U, // MFC2
6168
0
    0U, // MFC2_MMR6
6169
0
    8U, // MFGC0
6170
0
    8U, // MFGC0_MM
6171
0
    8U, // MFHC0_MMR6
6172
0
    0U, // MFHC1_D32
6173
0
    0U, // MFHC1_D32_MM
6174
0
    0U, // MFHC1_D64
6175
0
    0U, // MFHC1_D64_MM
6176
0
    0U, // MFHC2_MMR6
6177
0
    8U, // MFHGC0
6178
0
    8U, // MFHGC0_MM
6179
0
    0U, // MFHI
6180
0
    0U, // MFHI16_MM
6181
0
    0U, // MFHI64
6182
0
    0U, // MFHI_DSP
6183
0
    0U, // MFHI_DSP_MM
6184
0
    0U, // MFHI_MM
6185
0
    0U, // MFLO
6186
0
    0U, // MFLO16_MM
6187
0
    0U, // MFLO64
6188
0
    0U, // MFLO_DSP
6189
0
    0U, // MFLO_DSP_MM
6190
0
    0U, // MFLO_MM
6191
0
    18620U, // MFTR
6192
0
    4U, // MINA_D
6193
0
    4U, // MINA_D_MMR6
6194
0
    4U, // MINA_S
6195
0
    4U, // MINA_S_MMR6
6196
0
    4U, // MINI_S_B
6197
0
    4U, // MINI_S_D
6198
0
    4U, // MINI_S_H
6199
0
    4U, // MINI_S_W
6200
0
    12U,  // MINI_U_B
6201
0
    12U,  // MINI_U_D
6202
0
    12U,  // MINI_U_H
6203
0
    12U,  // MINI_U_W
6204
0
    4U, // MIN_A_B
6205
0
    4U, // MIN_A_D
6206
0
    4U, // MIN_A_H
6207
0
    4U, // MIN_A_W
6208
0
    4U, // MIN_D
6209
0
    4U, // MIN_D_MMR6
6210
0
    4U, // MIN_S
6211
0
    4U, // MIN_S_B
6212
0
    4U, // MIN_S_D
6213
0
    4U, // MIN_S_H
6214
0
    4U, // MIN_S_MMR6
6215
0
    4U, // MIN_S_W
6216
0
    4U, // MIN_U_B
6217
0
    4U, // MIN_U_D
6218
0
    4U, // MIN_U_H
6219
0
    4U, // MIN_U_W
6220
0
    4U, // MOD
6221
0
    4U, // MODSUB
6222
0
    4U, // MODSUB_MM
6223
0
    4U, // MODU
6224
0
    4U, // MODU_MMR6
6225
0
    4U, // MOD_MMR6
6226
0
    4U, // MOD_S_B
6227
0
    4U, // MOD_S_D
6228
0
    4U, // MOD_S_H
6229
0
    4U, // MOD_S_W
6230
0
    4U, // MOD_U_B
6231
0
    4U, // MOD_U_D
6232
0
    4U, // MOD_U_H
6233
0
    4U, // MOD_U_W
6234
0
    0U, // MOVE16_MM
6235
0
    0U, // MOVE16_MMR6
6236
0
    9348U,  // MOVEP_MM
6237
0
    9348U,  // MOVEP_MMR6
6238
0
    0U, // MOVE_V
6239
0
    4U, // MOVF_D32
6240
0
    4U, // MOVF_D32_MM
6241
0
    4U, // MOVF_D64
6242
0
    4U, // MOVF_I
6243
0
    4U, // MOVF_I64
6244
0
    4U, // MOVF_I_MM
6245
0
    4U, // MOVF_S
6246
0
    4U, // MOVF_S_MM
6247
0
    4U, // MOVN_I64_D64
6248
0
    4U, // MOVN_I64_I
6249
0
    4U, // MOVN_I64_I64
6250
0
    4U, // MOVN_I64_S
6251
0
    4U, // MOVN_I_D32
6252
0
    4U, // MOVN_I_D32_MM
6253
0
    4U, // MOVN_I_D64
6254
0
    4U, // MOVN_I_I
6255
0
    4U, // MOVN_I_I64
6256
0
    4U, // MOVN_I_MM
6257
0
    4U, // MOVN_I_S
6258
0
    4U, // MOVN_I_S_MM
6259
0
    4U, // MOVT_D32
6260
0
    4U, // MOVT_D32_MM
6261
0
    4U, // MOVT_D64
6262
0
    4U, // MOVT_I
6263
0
    4U, // MOVT_I64
6264
0
    4U, // MOVT_I_MM
6265
0
    4U, // MOVT_S
6266
0
    4U, // MOVT_S_MM
6267
0
    4U, // MOVZ_I64_D64
6268
0
    4U, // MOVZ_I64_I
6269
0
    4U, // MOVZ_I64_I64
6270
0
    4U, // MOVZ_I64_S
6271
0
    4U, // MOVZ_I_D32
6272
0
    4U, // MOVZ_I_D32_MM
6273
0
    4U, // MOVZ_I_D64
6274
0
    4U, // MOVZ_I_I
6275
0
    4U, // MOVZ_I_I64
6276
0
    4U, // MOVZ_I_MM
6277
0
    4U, // MOVZ_I_S
6278
0
    4U, // MOVZ_I_S_MM
6279
0
    0U, // MSUB
6280
0
    52U,  // MSUBF_D
6281
0
    52U,  // MSUBF_D_MMR6
6282
0
    52U,  // MSUBF_S
6283
0
    52U,  // MSUBF_S_MMR6
6284
0
    52U,  // MSUBR_Q_H
6285
0
    52U,  // MSUBR_Q_W
6286
0
    0U, // MSUBU
6287
0
    4U, // MSUBU_DSP
6288
0
    4U, // MSUBU_DSP_MM
6289
0
    0U, // MSUBU_MM
6290
0
    52U,  // MSUBV_B
6291
0
    52U,  // MSUBV_D
6292
0
    52U,  // MSUBV_H
6293
0
    52U,  // MSUBV_W
6294
0
    9348U,  // MSUB_D32
6295
0
    9348U,  // MSUB_D32_MM
6296
0
    9348U,  // MSUB_D64
6297
0
    4U, // MSUB_DSP
6298
0
    4U, // MSUB_DSP_MM
6299
0
    0U, // MSUB_MM
6300
0
    52U,  // MSUB_Q_H
6301
0
    52U,  // MSUB_Q_W
6302
0
    9348U,  // MSUB_S
6303
0
    9348U,  // MSUB_S_MM
6304
0
    0U, // MTC0
6305
0
    0U, // MTC0_MMR6
6306
0
    0U, // MTC1
6307
0
    0U, // MTC1_D64
6308
0
    0U, // MTC1_D64_MM
6309
0
    0U, // MTC1_MM
6310
0
    0U, // MTC1_MMR6
6311
0
    0U, // MTC2
6312
0
    0U, // MTC2_MMR6
6313
0
    0U, // MTGC0
6314
0
    0U, // MTGC0_MM
6315
0
    0U, // MTHC0_MMR6
6316
0
    0U, // MTHC1_D32
6317
0
    0U, // MTHC1_D32_MM
6318
0
    0U, // MTHC1_D64
6319
0
    0U, // MTHC1_D64_MM
6320
0
    0U, // MTHC2_MMR6
6321
0
    0U, // MTHGC0
6322
0
    0U, // MTHGC0_MM
6323
0
    0U, // MTHI
6324
0
    0U, // MTHI64
6325
0
    0U, // MTHI_DSP
6326
0
    0U, // MTHI_DSP_MM
6327
0
    0U, // MTHI_MM
6328
0
    0U, // MTHLIP
6329
0
    0U, // MTHLIP_MM
6330
0
    0U, // MTLO
6331
0
    0U, // MTLO64
6332
0
    0U, // MTLO_DSP
6333
0
    0U, // MTLO_DSP_MM
6334
0
    0U, // MTLO_MM
6335
0
    0U, // MTM0
6336
0
    0U, // MTM1
6337
0
    0U, // MTM2
6338
0
    0U, // MTP0
6339
0
    0U, // MTP1
6340
0
    0U, // MTP2
6341
0
    2U, // MTTR
6342
0
    4U, // MUH
6343
0
    4U, // MUHU
6344
0
    4U, // MUHU_MMR6
6345
0
    4U, // MUH_MMR6
6346
0
    4U, // MUL
6347
0
    4U, // MULEQ_S_W_PHL
6348
0
    4U, // MULEQ_S_W_PHL_MM
6349
0
    4U, // MULEQ_S_W_PHR
6350
0
    4U, // MULEQ_S_W_PHR_MM
6351
0
    4U, // MULEU_S_PH_QBL
6352
0
    4U, // MULEU_S_PH_QBL_MM
6353
0
    4U, // MULEU_S_PH_QBR
6354
0
    4U, // MULEU_S_PH_QBR_MM
6355
0
    4U, // MULQ_RS_PH
6356
0
    4U, // MULQ_RS_PH_MM
6357
0
    4U, // MULQ_RS_W
6358
0
    4U, // MULQ_RS_W_MMR2
6359
0
    4U, // MULQ_S_PH
6360
0
    4U, // MULQ_S_PH_MMR2
6361
0
    4U, // MULQ_S_W
6362
0
    4U, // MULQ_S_W_MMR2
6363
0
    4U, // MULR_PS64
6364
0
    4U, // MULR_Q_H
6365
0
    4U, // MULR_Q_W
6366
0
    4U, // MULSAQ_S_W_PH
6367
0
    4U, // MULSAQ_S_W_PH_MM
6368
0
    4U, // MULSA_W_PH
6369
0
    4U, // MULSA_W_PH_MMR2
6370
0
    0U, // MULT
6371
0
    4U, // MULTU_DSP
6372
0
    4U, // MULTU_DSP_MM
6373
0
    4U, // MULT_DSP
6374
0
    4U, // MULT_DSP_MM
6375
0
    0U, // MULT_MM
6376
0
    0U, // MULTu
6377
0
    0U, // MULTu_MM
6378
0
    4U, // MULU
6379
0
    4U, // MULU_MMR6
6380
0
    4U, // MULV_B
6381
0
    4U, // MULV_D
6382
0
    4U, // MULV_H
6383
0
    4U, // MULV_W
6384
0
    4U, // MUL_MM
6385
0
    4U, // MUL_MMR6
6386
0
    4U, // MUL_PH
6387
0
    4U, // MUL_PH_MMR2
6388
0
    4U, // MUL_Q_H
6389
0
    4U, // MUL_Q_W
6390
0
    4U, // MUL_R6
6391
0
    4U, // MUL_S_PH
6392
0
    4U, // MUL_S_PH_MMR2
6393
0
    0U, // Mfhi16
6394
0
    0U, // Mflo16
6395
0
    0U, // Move32R16
6396
0
    0U, // MoveR3216
6397
0
    0U, // NLOC_B
6398
0
    0U, // NLOC_D
6399
0
    0U, // NLOC_H
6400
0
    0U, // NLOC_W
6401
0
    0U, // NLZC_B
6402
0
    0U, // NLZC_D
6403
0
    0U, // NLZC_H
6404
0
    0U, // NLZC_W
6405
0
    9348U,  // NMADD_D32
6406
0
    9348U,  // NMADD_D32_MM
6407
0
    9348U,  // NMADD_D64
6408
0
    9348U,  // NMADD_S
6409
0
    9348U,  // NMADD_S_MM
6410
0
    9348U,  // NMSUB_D32
6411
0
    9348U,  // NMSUB_D32_MM
6412
0
    9348U,  // NMSUB_D64
6413
0
    9348U,  // NMSUB_S
6414
0
    9348U,  // NMSUB_S_MM
6415
0
    4U, // NOR
6416
0
    4U, // NOR64
6417
0
    16U,  // NORI_B
6418
0
    4U, // NOR_MM
6419
0
    4U, // NOR_MMR6
6420
0
    4U, // NOR_V
6421
0
    0U, // NOT16_MM
6422
0
    0U, // NOT16_MMR6
6423
0
    0U, // NegRxRy16
6424
0
    0U, // NotRxRy16
6425
0
    4U, // OR
6426
0
    0U, // OR16_MM
6427
0
    0U, // OR16_MMR6
6428
0
    4U, // OR64
6429
0
    16U,  // ORI_B
6430
0
    20U,  // ORI_MMR6
6431
0
    4U, // OR_MM
6432
0
    4U, // OR_MMR6
6433
0
    4U, // OR_V
6434
0
    20U,  // ORi
6435
0
    20U,  // ORi64
6436
0
    20U,  // ORi_MM
6437
0
    0U, // OrRxRxRy16
6438
0
    4U, // PACKRL_PH
6439
0
    4U, // PACKRL_PH_MM
6440
0
    0U, // PAUSE
6441
0
    0U, // PAUSE_MM
6442
0
    0U, // PAUSE_MMR6
6443
0
    4U, // PCKEV_B
6444
0
    4U, // PCKEV_D
6445
0
    4U, // PCKEV_H
6446
0
    4U, // PCKEV_W
6447
0
    4U, // PCKOD_B
6448
0
    4U, // PCKOD_D
6449
0
    4U, // PCKOD_H
6450
0
    4U, // PCKOD_W
6451
0
    0U, // PCNT_B
6452
0
    0U, // PCNT_D
6453
0
    0U, // PCNT_H
6454
0
    0U, // PCNT_W
6455
0
    4U, // PICK_PH
6456
0
    4U, // PICK_PH_MM
6457
0
    4U, // PICK_QB
6458
0
    4U, // PICK_QB_MM
6459
0
    4U, // PLL_PS64
6460
0
    4U, // PLU_PS64
6461
0
    0U, // POP
6462
0
    0U, // PRECEQU_PH_QBL
6463
0
    0U, // PRECEQU_PH_QBLA
6464
0
    0U, // PRECEQU_PH_QBLA_MM
6465
0
    0U, // PRECEQU_PH_QBL_MM
6466
0
    0U, // PRECEQU_PH_QBR
6467
0
    0U, // PRECEQU_PH_QBRA
6468
0
    0U, // PRECEQU_PH_QBRA_MM
6469
0
    0U, // PRECEQU_PH_QBR_MM
6470
0
    0U, // PRECEQ_W_PHL
6471
0
    0U, // PRECEQ_W_PHL_MM
6472
0
    0U, // PRECEQ_W_PHR
6473
0
    0U, // PRECEQ_W_PHR_MM
6474
0
    0U, // PRECEU_PH_QBL
6475
0
    0U, // PRECEU_PH_QBLA
6476
0
    0U, // PRECEU_PH_QBLA_MM
6477
0
    0U, // PRECEU_PH_QBL_MM
6478
0
    0U, // PRECEU_PH_QBR
6479
0
    0U, // PRECEU_PH_QBRA
6480
0
    0U, // PRECEU_PH_QBRA_MM
6481
0
    0U, // PRECEU_PH_QBR_MM
6482
0
    4U, // PRECRQU_S_QB_PH
6483
0
    4U, // PRECRQU_S_QB_PH_MM
6484
0
    4U, // PRECRQ_PH_W
6485
0
    4U, // PRECRQ_PH_W_MM
6486
0
    4U, // PRECRQ_QB_PH
6487
0
    4U, // PRECRQ_QB_PH_MM
6488
0
    4U, // PRECRQ_RS_PH_W
6489
0
    4U, // PRECRQ_RS_PH_W_MM
6490
0
    4U, // PRECR_QB_PH
6491
0
    4U, // PRECR_QB_PH_MMR2
6492
0
    12U,  // PRECR_SRA_PH_W
6493
0
    12U,  // PRECR_SRA_PH_W_MMR2
6494
0
    12U,  // PRECR_SRA_R_PH_W
6495
0
    12U,  // PRECR_SRA_R_PH_W_MMR2
6496
0
    0U, // PREF
6497
0
    0U, // PREFE
6498
0
    0U, // PREFE_MM
6499
0
    0U, // PREFX_MM
6500
0
    0U, // PREF_MM
6501
0
    0U, // PREF_MMR6
6502
0
    0U, // PREF_R6
6503
0
    12U,  // PREPEND
6504
0
    12U,  // PREPEND_MMR2
6505
0
    4U, // PUL_PS64
6506
0
    4U, // PUU_PS64
6507
0
    0U, // RADDU_W_QB
6508
0
    0U, // RADDU_W_QB_MM
6509
0
    0U, // RDDSP
6510
0
    0U, // RDDSP_MM
6511
0
    16U,  // RDHWR
6512
0
    16U,  // RDHWR64
6513
0
    16U,  // RDHWR_MM
6514
0
    8U, // RDHWR_MMR6
6515
0
    0U, // RDPGPR_MMR6
6516
0
    0U, // RECIP_D32
6517
0
    0U, // RECIP_D32_MM
6518
0
    0U, // RECIP_D64
6519
0
    0U, // RECIP_D64_MM
6520
0
    0U, // RECIP_S
6521
0
    0U, // RECIP_S_MM
6522
0
    0U, // REPLV_PH
6523
0
    0U, // REPLV_PH_MM
6524
0
    0U, // REPLV_QB
6525
0
    0U, // REPLV_QB_MM
6526
0
    0U, // REPL_PH
6527
0
    0U, // REPL_PH_MM
6528
0
    0U, // REPL_QB
6529
0
    0U, // REPL_QB_MM
6530
0
    0U, // RINT_D
6531
0
    0U, // RINT_D_MMR6
6532
0
    0U, // RINT_S
6533
0
    0U, // RINT_S_MMR6
6534
0
    12U,  // ROTR
6535
0
    4U, // ROTRV
6536
0
    4U, // ROTRV_MM
6537
0
    12U,  // ROTR_MM
6538
0
    0U, // ROUND_L_D64
6539
0
    0U, // ROUND_L_D_MMR6
6540
0
    0U, // ROUND_L_S
6541
0
    0U, // ROUND_L_S_MMR6
6542
0
    0U, // ROUND_W_D32
6543
0
    0U, // ROUND_W_D64
6544
0
    0U, // ROUND_W_D_MMR6
6545
0
    0U, // ROUND_W_MM
6546
0
    0U, // ROUND_W_S
6547
0
    0U, // ROUND_W_S_MM
6548
0
    0U, // ROUND_W_S_MMR6
6549
0
    0U, // RSQRT_D32
6550
0
    0U, // RSQRT_D32_MM
6551
0
    0U, // RSQRT_D64
6552
0
    0U, // RSQRT_D64_MM
6553
0
    0U, // RSQRT_S
6554
0
    0U, // RSQRT_S_MM
6555
0
    0U, // Restore16
6556
0
    0U, // RestoreX16
6557
0
    0U, // SAA
6558
0
    0U, // SAAD
6559
0
    8U, // SAT_S_B
6560
0
    28U,  // SAT_S_D
6561
0
    32U,  // SAT_S_H
6562
0
    12U,  // SAT_S_W
6563
0
    8U, // SAT_U_B
6564
0
    28U,  // SAT_U_D
6565
0
    32U,  // SAT_U_H
6566
0
    12U,  // SAT_U_W
6567
0
    0U, // SB
6568
0
    0U, // SB16_MM
6569
0
    0U, // SB16_MMR6
6570
0
    0U, // SB64
6571
0
    0U, // SBE
6572
0
    0U, // SBE_MM
6573
0
    0U, // SB_MM
6574
0
    0U, // SB_MMR6
6575
0
    0U, // SC
6576
0
    0U, // SC64
6577
0
    0U, // SC64_R6
6578
0
    0U, // SCD
6579
0
    0U, // SCD_R6
6580
0
    0U, // SCE
6581
0
    0U, // SCE_MM
6582
0
    0U, // SC_MM
6583
0
    0U, // SC_MMR6
6584
0
    0U, // SC_R6
6585
0
    0U, // SD
6586
0
    0U, // SDBBP
6587
0
    0U, // SDBBP16_MM
6588
0
    0U, // SDBBP16_MMR6
6589
0
    0U, // SDBBP_MM
6590
0
    0U, // SDBBP_MMR6
6591
0
    0U, // SDBBP_R6
6592
0
    0U, // SDC1
6593
0
    0U, // SDC164
6594
0
    0U, // SDC1_D64_MMR6
6595
0
    0U, // SDC1_MM_D32
6596
0
    0U, // SDC1_MM_D64
6597
0
    0U, // SDC2
6598
0
    0U, // SDC2_MMR6
6599
0
    0U, // SDC2_R6
6600
0
    0U, // SDC3
6601
0
    0U, // SDIV
6602
0
    0U, // SDIV_MM
6603
0
    0U, // SDL
6604
0
    0U, // SDR
6605
0
    1U, // SDXC1
6606
0
    1U, // SDXC164
6607
0
    0U, // SEB
6608
0
    0U, // SEB64
6609
0
    0U, // SEB_MM
6610
0
    0U, // SEH
6611
0
    0U, // SEH64
6612
0
    0U, // SEH_MM
6613
0
    4U, // SELEQZ
6614
0
    4U, // SELEQZ64
6615
0
    4U, // SELEQZ_D
6616
0
    4U, // SELEQZ_D_MMR6
6617
0
    4U, // SELEQZ_MMR6
6618
0
    4U, // SELEQZ_S
6619
0
    4U, // SELEQZ_S_MMR6
6620
0
    4U, // SELNEZ
6621
0
    4U, // SELNEZ64
6622
0
    4U, // SELNEZ_D
6623
0
    4U, // SELNEZ_D_MMR6
6624
0
    4U, // SELNEZ_MMR6
6625
0
    4U, // SELNEZ_S
6626
0
    4U, // SELNEZ_S_MMR6
6627
0
    52U,  // SEL_D
6628
0
    52U,  // SEL_D_MMR6
6629
0
    52U,  // SEL_S
6630
0
    52U,  // SEL_S_MMR6
6631
0
    4U, // SEQ
6632
0
    4U, // SEQi
6633
0
    0U, // SH
6634
0
    0U, // SH16_MM
6635
0
    0U, // SH16_MMR6
6636
0
    0U, // SH64
6637
0
    0U, // SHE
6638
0
    0U, // SHE_MM
6639
0
    16U,  // SHF_B
6640
0
    16U,  // SHF_H
6641
0
    16U,  // SHF_W
6642
0
    0U, // SHILO
6643
0
    0U, // SHILOV
6644
0
    0U, // SHILOV_MM
6645
0
    0U, // SHILO_MM
6646
0
    4U, // SHLLV_PH
6647
0
    4U, // SHLLV_PH_MM
6648
0
    4U, // SHLLV_QB
6649
0
    4U, // SHLLV_QB_MM
6650
0
    4U, // SHLLV_S_PH
6651
0
    4U, // SHLLV_S_PH_MM
6652
0
    4U, // SHLLV_S_W
6653
0
    4U, // SHLLV_S_W_MM
6654
0
    32U,  // SHLL_PH
6655
0
    32U,  // SHLL_PH_MM
6656
0
    8U, // SHLL_QB
6657
0
    8U, // SHLL_QB_MM
6658
0
    32U,  // SHLL_S_PH
6659
0
    32U,  // SHLL_S_PH_MM
6660
0
    12U,  // SHLL_S_W
6661
0
    12U,  // SHLL_S_W_MM
6662
0
    4U, // SHRAV_PH
6663
0
    4U, // SHRAV_PH_MM
6664
0
    4U, // SHRAV_QB
6665
0
    4U, // SHRAV_QB_MMR2
6666
0
    4U, // SHRAV_R_PH
6667
0
    4U, // SHRAV_R_PH_MM
6668
0
    4U, // SHRAV_R_QB
6669
0
    4U, // SHRAV_R_QB_MMR2
6670
0
    4U, // SHRAV_R_W
6671
0
    4U, // SHRAV_R_W_MM
6672
0
    32U,  // SHRA_PH
6673
0
    32U,  // SHRA_PH_MM
6674
0
    8U, // SHRA_QB
6675
0
    8U, // SHRA_QB_MMR2
6676
0
    32U,  // SHRA_R_PH
6677
0
    32U,  // SHRA_R_PH_MM
6678
0
    8U, // SHRA_R_QB
6679
0
    8U, // SHRA_R_QB_MMR2
6680
0
    12U,  // SHRA_R_W
6681
0
    12U,  // SHRA_R_W_MM
6682
0
    4U, // SHRLV_PH
6683
0
    4U, // SHRLV_PH_MMR2
6684
0
    4U, // SHRLV_QB
6685
0
    4U, // SHRLV_QB_MM
6686
0
    32U,  // SHRL_PH
6687
0
    32U,  // SHRL_PH_MMR2
6688
0
    8U, // SHRL_QB
6689
0
    8U, // SHRL_QB_MM
6690
0
    0U, // SH_MM
6691
0
    0U, // SH_MMR6
6692
0
    0U, // SIGRIE
6693
0
    0U, // SIGRIE_MMR6
6694
0
    301U, // SLDI_B
6695
0
    73U,  // SLDI_D
6696
0
    293U, // SLDI_H
6697
0
    77U,  // SLDI_W
6698
0
    309U, // SLD_B
6699
0
    309U, // SLD_D
6700
0
    309U, // SLD_H
6701
0
    309U, // SLD_W
6702
0
    12U,  // SLL
6703
0
    4U, // SLL16_MM
6704
0
    4U, // SLL16_MMR6
6705
0
    2U, // SLL64_32
6706
0
    2U, // SLL64_64
6707
0
    8U, // SLLI_B
6708
0
    28U,  // SLLI_D
6709
0
    32U,  // SLLI_H
6710
0
    12U,  // SLLI_W
6711
0
    4U, // SLLV
6712
0
    4U, // SLLV_MM
6713
0
    4U, // SLL_B
6714
0
    4U, // SLL_D
6715
0
    4U, // SLL_H
6716
0
    12U,  // SLL_MM
6717
0
    12U,  // SLL_MMR6
6718
0
    4U, // SLL_W
6719
0
    4U, // SLT
6720
0
    4U, // SLT64
6721
0
    4U, // SLT_MM
6722
0
    4U, // SLTi
6723
0
    4U, // SLTi64
6724
0
    4U, // SLTi_MM
6725
0
    4U, // SLTiu
6726
0
    4U, // SLTiu64
6727
0
    4U, // SLTiu_MM
6728
0
    4U, // SLTu
6729
0
    4U, // SLTu64
6730
0
    4U, // SLTu_MM
6731
0
    4U, // SNE
6732
0
    4U, // SNEi
6733
0
    289U, // SPLATI_B
6734
0
    317U, // SPLATI_D
6735
0
    265U, // SPLATI_H
6736
0
    281U, // SPLATI_W
6737
0
    261U, // SPLAT_B
6738
0
    261U, // SPLAT_D
6739
0
    261U, // SPLAT_H
6740
0
    261U, // SPLAT_W
6741
0
    12U,  // SRA
6742
0
    8U, // SRAI_B
6743
0
    28U,  // SRAI_D
6744
0
    32U,  // SRAI_H
6745
0
    12U,  // SRAI_W
6746
0
    8U, // SRARI_B
6747
0
    28U,  // SRARI_D
6748
0
    32U,  // SRARI_H
6749
0
    12U,  // SRARI_W
6750
0
    4U, // SRAR_B
6751
0
    4U, // SRAR_D
6752
0
    4U, // SRAR_H
6753
0
    4U, // SRAR_W
6754
0
    4U, // SRAV
6755
0
    4U, // SRAV_MM
6756
0
    4U, // SRA_B
6757
0
    4U, // SRA_D
6758
0
    4U, // SRA_H
6759
0
    12U,  // SRA_MM
6760
0
    4U, // SRA_W
6761
0
    12U,  // SRL
6762
0
    4U, // SRL16_MM
6763
0
    4U, // SRL16_MMR6
6764
0
    8U, // SRLI_B
6765
0
    28U,  // SRLI_D
6766
0
    32U,  // SRLI_H
6767
0
    12U,  // SRLI_W
6768
0
    8U, // SRLRI_B
6769
0
    28U,  // SRLRI_D
6770
0
    32U,  // SRLRI_H
6771
0
    12U,  // SRLRI_W
6772
0
    4U, // SRLR_B
6773
0
    4U, // SRLR_D
6774
0
    4U, // SRLR_H
6775
0
    4U, // SRLR_W
6776
0
    4U, // SRLV
6777
0
    4U, // SRLV_MM
6778
0
    4U, // SRL_B
6779
0
    4U, // SRL_D
6780
0
    4U, // SRL_H
6781
0
    12U,  // SRL_MM
6782
0
    4U, // SRL_W
6783
0
    0U, // SSNOP
6784
0
    0U, // SSNOP_MM
6785
0
    0U, // SSNOP_MMR6
6786
0
    0U, // ST_B
6787
0
    0U, // ST_D
6788
0
    0U, // ST_H
6789
0
    0U, // ST_W
6790
0
    4U, // SUB
6791
0
    4U, // SUBQH_PH
6792
0
    4U, // SUBQH_PH_MMR2
6793
0
    4U, // SUBQH_R_PH
6794
0
    4U, // SUBQH_R_PH_MMR2
6795
0
    4U, // SUBQH_R_W
6796
0
    4U, // SUBQH_R_W_MMR2
6797
0
    4U, // SUBQH_W
6798
0
    4U, // SUBQH_W_MMR2
6799
0
    4U, // SUBQ_PH
6800
0
    4U, // SUBQ_PH_MM
6801
0
    4U, // SUBQ_S_PH
6802
0
    4U, // SUBQ_S_PH_MM
6803
0
    4U, // SUBQ_S_W
6804
0
    4U, // SUBQ_S_W_MM
6805
0
    4U, // SUBSUS_U_B
6806
0
    4U, // SUBSUS_U_D
6807
0
    4U, // SUBSUS_U_H
6808
0
    4U, // SUBSUS_U_W
6809
0
    4U, // SUBSUU_S_B
6810
0
    4U, // SUBSUU_S_D
6811
0
    4U, // SUBSUU_S_H
6812
0
    4U, // SUBSUU_S_W
6813
0
    4U, // SUBS_S_B
6814
0
    4U, // SUBS_S_D
6815
0
    4U, // SUBS_S_H
6816
0
    4U, // SUBS_S_W
6817
0
    4U, // SUBS_U_B
6818
0
    4U, // SUBS_U_D
6819
0
    4U, // SUBS_U_H
6820
0
    4U, // SUBS_U_W
6821
0
    4U, // SUBU16_MM
6822
0
    4U, // SUBU16_MMR6
6823
0
    4U, // SUBUH_QB
6824
0
    4U, // SUBUH_QB_MMR2
6825
0
    4U, // SUBUH_R_QB
6826
0
    4U, // SUBUH_R_QB_MMR2
6827
0
    4U, // SUBU_MMR6
6828
0
    4U, // SUBU_PH
6829
0
    4U, // SUBU_PH_MMR2
6830
0
    4U, // SUBU_QB
6831
0
    4U, // SUBU_QB_MM
6832
0
    4U, // SUBU_S_PH
6833
0
    4U, // SUBU_S_PH_MMR2
6834
0
    4U, // SUBU_S_QB
6835
0
    4U, // SUBU_S_QB_MM
6836
0
    12U,  // SUBVI_B
6837
0
    12U,  // SUBVI_D
6838
0
    12U,  // SUBVI_H
6839
0
    12U,  // SUBVI_W
6840
0
    4U, // SUBV_B
6841
0
    4U, // SUBV_D
6842
0
    4U, // SUBV_H
6843
0
    4U, // SUBV_W
6844
0
    4U, // SUB_MM
6845
0
    4U, // SUB_MMR6
6846
0
    4U, // SUBu
6847
0
    4U, // SUBu_MM
6848
0
    1U, // SUXC1
6849
0
    1U, // SUXC164
6850
0
    1U, // SUXC1_MM
6851
0
    0U, // SW
6852
0
    0U, // SW16_MM
6853
0
    0U, // SW16_MMR6
6854
0
    0U, // SW64
6855
0
    0U, // SWC1
6856
0
    0U, // SWC1_MM
6857
0
    0U, // SWC2
6858
0
    0U, // SWC2_MMR6
6859
0
    0U, // SWC2_R6
6860
0
    0U, // SWC3
6861
0
    0U, // SWDSP
6862
0
    0U, // SWDSP_MM
6863
0
    0U, // SWE
6864
0
    0U, // SWE_MM
6865
0
    0U, // SWL
6866
0
    0U, // SWL64
6867
0
    0U, // SWLE
6868
0
    0U, // SWLE_MM
6869
0
    0U, // SWL_MM
6870
0
    0U, // SWM16_MM
6871
0
    0U, // SWM16_MMR6
6872
0
    0U, // SWM32_MM
6873
0
    0U, // SWP_MM
6874
0
    0U, // SWR
6875
0
    0U, // SWR64
6876
0
    0U, // SWRE
6877
0
    0U, // SWRE_MM
6878
0
    0U, // SWR_MM
6879
0
    0U, // SWSP_MM
6880
0
    0U, // SWSP_MMR6
6881
0
    1U, // SWXC1
6882
0
    1U, // SWXC1_MM
6883
0
    0U, // SW_MM
6884
0
    0U, // SW_MMR6
6885
0
    0U, // SYNC
6886
0
    0U, // SYNCI
6887
0
    0U, // SYNCI_MM
6888
0
    0U, // SYNCI_MMR6
6889
0
    0U, // SYNC_MM
6890
0
    0U, // SYNC_MMR6
6891
0
    0U, // SYSCALL
6892
0
    0U, // SYSCALL_MM
6893
0
    0U, // Save16
6894
0
    0U, // SaveX16
6895
0
    0U, // SbRxRyOffMemX16
6896
0
    0U, // SebRx16
6897
0
    0U, // SehRx16
6898
0
    0U, // ShRxRyOffMemX16
6899
0
    12U,  // SllX16
6900
0
    0U, // SllvRxRy16
6901
0
    0U, // SltRxRy16
6902
0
    1U, // SltiRxImm16
6903
0
    0U, // SltiRxImmX16
6904
0
    1U, // SltiuRxImm16
6905
0
    0U, // SltiuRxImmX16
6906
0
    0U, // SltuRxRy16
6907
0
    12U,  // SraX16
6908
0
    0U, // SravRxRy16
6909
0
    12U,  // SrlX16
6910
0
    0U, // SrlvRxRy16
6911
0
    4U, // SubuRxRyRz16
6912
0
    0U, // SwRxRyOffMemX16
6913
0
    0U, // SwRxSpImmX16
6914
0
    80U,  // TEQ
6915
0
    0U, // TEQI
6916
0
    0U, // TEQI_MM
6917
0
    32U,  // TEQ_MM
6918
0
    80U,  // TGE
6919
0
    0U, // TGEI
6920
0
    0U, // TGEIU
6921
0
    0U, // TGEIU_MM
6922
0
    0U, // TGEI_MM
6923
0
    80U,  // TGEU
6924
0
    32U,  // TGEU_MM
6925
0
    32U,  // TGE_MM
6926
0
    0U, // TLBGINV
6927
0
    0U, // TLBGINVF
6928
0
    0U, // TLBGINVF_MM
6929
0
    0U, // TLBGINV_MM
6930
0
    0U, // TLBGP
6931
0
    0U, // TLBGP_MM
6932
0
    0U, // TLBGR
6933
0
    0U, // TLBGR_MM
6934
0
    0U, // TLBGWI
6935
0
    0U, // TLBGWI_MM
6936
0
    0U, // TLBGWR
6937
0
    0U, // TLBGWR_MM
6938
0
    0U, // TLBINV
6939
0
    0U, // TLBINVF
6940
0
    0U, // TLBINVF_MMR6
6941
0
    0U, // TLBINV_MMR6
6942
0
    0U, // TLBP
6943
0
    0U, // TLBP_MM
6944
0
    0U, // TLBR
6945
0
    0U, // TLBR_MM
6946
0
    0U, // TLBWI
6947
0
    0U, // TLBWI_MM
6948
0
    0U, // TLBWR
6949
0
    0U, // TLBWR_MM
6950
0
    80U,  // TLT
6951
0
    0U, // TLTI
6952
0
    0U, // TLTIU_MM
6953
0
    0U, // TLTI_MM
6954
0
    80U,  // TLTU
6955
0
    32U,  // TLTU_MM
6956
0
    32U,  // TLT_MM
6957
0
    80U,  // TNE
6958
0
    0U, // TNEI
6959
0
    0U, // TNEI_MM
6960
0
    32U,  // TNE_MM
6961
0
    0U, // TRUNC_L_D64
6962
0
    0U, // TRUNC_L_D_MMR6
6963
0
    0U, // TRUNC_L_S
6964
0
    0U, // TRUNC_L_S_MMR6
6965
0
    0U, // TRUNC_W_D32
6966
0
    0U, // TRUNC_W_D64
6967
0
    0U, // TRUNC_W_D_MMR6
6968
0
    0U, // TRUNC_W_MM
6969
0
    0U, // TRUNC_W_S
6970
0
    0U, // TRUNC_W_S_MM
6971
0
    0U, // TRUNC_W_S_MMR6
6972
0
    0U, // TTLTIU
6973
0
    0U, // UDIV
6974
0
    0U, // UDIV_MM
6975
0
    4U, // V3MULU
6976
0
    4U, // VMM0
6977
0
    4U, // VMULU
6978
0
    52U,  // VSHF_B
6979
0
    52U,  // VSHF_D
6980
0
    52U,  // VSHF_H
6981
0
    52U,  // VSHF_W
6982
0
    0U, // WAIT
6983
0
    0U, // WAIT_MM
6984
0
    0U, // WAIT_MMR6
6985
0
    0U, // WRDSP
6986
0
    0U, // WRDSP_MM
6987
0
    0U, // WRPGPR_MMR6
6988
0
    0U, // WSBH
6989
0
    0U, // WSBH_MM
6990
0
    0U, // WSBH_MMR6
6991
0
    4U, // XOR
6992
0
    0U, // XOR16_MM
6993
0
    0U, // XOR16_MMR6
6994
0
    4U, // XOR64
6995
0
    16U,  // XORI_B
6996
0
    20U,  // XORI_MMR6
6997
0
    4U, // XOR_MM
6998
0
    4U, // XOR_MMR6
6999
0
    4U, // XOR_V
7000
0
    20U,  // XORi
7001
0
    20U,  // XORi64
7002
0
    20U,  // XORi_MM
7003
0
    0U, // XorRxRxRy16
7004
0
    0U, // YIELD
7005
0
  };
7006
7007
  // Emit the opcode for the instruction.
7008
0
  uint64_t Bits = 0;
7009
0
  Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
7010
0
  Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
7011
0
  if (Bits == 0)
7012
0
    return {nullptr, Bits};
7013
0
  return {AsmStrs+(Bits & 16383)-1, Bits};
7014
7015
0
}
7016
/// printInstruction - This method is automatically generated by tablegen
7017
/// from the instruction set description.
7018
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
7019
void MipsInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
7020
  O << "\t";
7021
7022
  auto MnemonicInfo = getMnemonic(MI);
7023
7024
  O << MnemonicInfo.first;
7025
7026
  uint64_t Bits = MnemonicInfo.second;
7027
  assert(Bits != 0 && "Cannot print this instruction.");
7028
7029
  // Fragment 0 encoded into 5 bits for 17 unique commands.
7030
  switch ((Bits >> 14) & 31) {
7031
  default: llvm_unreachable("Invalid command number.");
7032
  case 0:
7033
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
7034
    return;
7035
    break;
7036
  case 1:
7037
    // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
7038
    printOperand(MI, 0, STI, O);
7039
    break;
7040
  case 2:
7041
    // B_MMR6_Pseudo, B_MM_Pseudo, B16_MM, BAL, BALC, BALC_MMR6, BC, BC16_MMR...
7042
    printBranchOperand(MI, Address, 0, STI, O);
7043
    break;
7044
  case 3:
7045
    // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, MultRxRyRz1...
7046
    printOperand(MI, 1, STI, O);
7047
    O << ", ";
7048
    break;
7049
  case 4:
7050
    // LWM_MM, SWM_MM, LWM16_MM, LWM16_MMR6, LWM32_MM, SWM16_MM, SWM16_MMR6, ...
7051
    printRegisterList(MI, 0, STI, O);
7052
    O << ", ";
7053
    printMemOperand(MI, 1, STI, O);
7054
    return;
7055
    break;
7056
  case 5:
7057
    // SelBeqZ, SelBneZ, SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZ...
7058
    printOperand(MI, 3, STI, O);
7059
    break;
7060
  case 6:
7061
    // AND16_MM, AND16_MMR6, LSA_MMR6, MTHC1_D32, MTHC1_D32_MM, MTHC1_D64, MT...
7062
    printOperand(MI, 2, STI, O);
7063
    O << ", ";
7064
    break;
7065
  case 7:
7066
    // BREAK, BREAK_MM, BREAK_MMR6, HYPCALL, HYPCALL_MM, SDBBP_MM, SYSCALL_MM...
7067
    printUImm<10>(MI, 0, STI, O);
7068
    break;
7069
  case 8:
7070
    // BREAK16_MM, BREAK16_MMR6, SDBBP16_MM, SDBBP16_MMR6
7071
    printUImm<4>(MI, 0, STI, O);
7072
    return;
7073
    break;
7074
  case 9:
7075
    // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,...
7076
    printUImm<5>(MI, 2, STI, O);
7077
    O << ", ";
7078
    break;
7079
  case 10:
7080
    // FCMP_D32, FCMP_D32_MM, FCMP_D64, FCMP_S32, FCMP_S32_MM
7081
    printFCCOperand(MI, 2, STI, O);
7082
    break;
7083
  case 11:
7084
    // J, JAL, JALS_MM, JALX, JALX_MM, JAL_MM, J_MM
7085
    printJumpOperand(MI, 0, STI, O);
7086
    return;
7087
    break;
7088
  case 12:
7089
    // Jal16, JalB16
7090
    printUImm<26>(MI, 0, STI, O);
7091
    break;
7092
  case 13:
7093
    // SDBBP, SDBBP_MMR6, SDBBP_R6, SYSCALL
7094
    printUImm<20>(MI, 0, STI, O);
7095
    return;
7096
    break;
7097
  case 14:
7098
    // SIGRIE, SIGRIE_MMR6
7099
    printUImm<16>(MI, 0, STI, O);
7100
    return;
7101
    break;
7102
  case 15:
7103
    // SYNC, SYNC_MM, SYNC_MMR6
7104
    printUImm<5>(MI, 0, STI, O);
7105
    return;
7106
    break;
7107
  case 16:
7108
    // SYNCI, SYNCI_MM, SYNCI_MMR6
7109
    printMemOperand(MI, 0, STI, O);
7110
    return;
7111
    break;
7112
  }
7113
7114
7115
  // Fragment 1 encoded into 5 bits for 18 unique commands.
7116
  switch ((Bits >> 19) & 31) {
7117
  default: llvm_unreachable("Invalid command number.");
7118
  case 0:
7119
    // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
7120
    O << ", ";
7121
    break;
7122
  case 1:
7123
    // B_MMR6_Pseudo, B_MM_Pseudo, Constant32, JalOneReg, MFTDSP, MTTDSP, ADD...
7124
    return;
7125
    break;
7126
  case 2:
7127
    // CTTC1, MTTACX, MTTC0, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, CTC1, CTC1_...
7128
    printOperand(MI, 0, STI, O);
7129
    break;
7130
  case 3:
7131
    // LwConstant32
7132
    O << ", 1f\n\tb\t2f\n\t.align\t2\n1: \t.word\t";
7133
    printOperand(MI, 1, STI, O);
7134
    O << "\n2:";
7135
    return;
7136
    break;
7137
  case 4:
7138
    // MultRxRyRz16, MultuRxRyRz16, SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImm...
7139
    printOperand(MI, 2, STI, O);
7140
    break;
7141
  case 5:
7142
    // SelBeqZ, SelBneZ
7143
    O << ", .+4\n\t\n\tmove ";
7144
    printOperand(MI, 1, STI, O);
7145
    O << ", ";
7146
    printOperand(MI, 2, STI, O);
7147
    return;
7148
    break;
7149
  case 6:
7150
    // AND16_MM, AND16_MMR6, LSA_MMR6, OR16_MM, OR16_MMR6, PREFX_MM, XOR16_MM...
7151
    printOperand(MI, 1, STI, O);
7152
    break;
7153
  case 7:
7154
    // AddiuRxPcImmX16
7155
    O << ", $pc, ";
7156
    printOperand(MI, 1, STI, O);
7157
    return;
7158
    break;
7159
  case 8:
7160
    // AddiuSpImm16, Bimm16
7161
    O << " # 16 bit inst";
7162
    return;
7163
    break;
7164
  case 9:
7165
    // Bteqz16, Btnez16
7166
    O << "  # 16 bit inst";
7167
    return;
7168
    break;
7169
  case 10:
7170
    // CACHE, CACHEE, CACHEE_MM, CACHE_MM, CACHE_MMR6, CACHE_R6, PREF, PREFE,...
7171
    printMemOperand(MI, 0, STI, O);
7172
    return;
7173
    break;
7174
  case 11:
7175
    // FCMP_D32, FCMP_D32_MM, FCMP_D64
7176
    O << ".d\t";
7177
    printOperand(MI, 0, STI, O);
7178
    O << ", ";
7179
    printOperand(MI, 1, STI, O);
7180
    return;
7181
    break;
7182
  case 12:
7183
    // FCMP_S32, FCMP_S32_MM
7184
    O << ".s\t";
7185
    printOperand(MI, 0, STI, O);
7186
    O << ", ";
7187
    printOperand(MI, 1, STI, O);
7188
    return;
7189
    break;
7190
  case 13:
7191
    // INSERT_B, INSERT_D, INSERT_H, INSERT_W, INSVE_B, INSVE_D, INSVE_H, INS...
7192
    O << '[';
7193
    break;
7194
  case 14:
7195
    // Jal16
7196
    O << "\n\tnop";
7197
    return;
7198
    break;
7199
  case 15:
7200
    // JalB16
7201
    O << "\t# branch\n\tnop";
7202
    return;
7203
    break;
7204
  case 16:
7205
    // SAA, SAAD
7206
    O << ", (";
7207
    printOperand(MI, 1, STI, O);
7208
    O << ')';
7209
    return;
7210
    break;
7211
  case 17:
7212
    // SC, SC64, SC64_R6, SCD, SCD_R6, SCE, SCE_MM, SC_MM, SC_MMR6, SC_R6
7213
    printMemOperand(MI, 2, STI, O);
7214
    return;
7215
    break;
7216
  }
7217
7218
7219
  // Fragment 2 encoded into 5 bits for 26 unique commands.
7220
  switch ((Bits >> 24) & 31) {
7221
  default: llvm_unreachable("Invalid command number.");
7222
  case 0:
7223
    // ABSMacro, BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BG...
7224
    printOperand(MI, 1, STI, O);
7225
    break;
7226
  case 1:
7227
    // CTTC1, MTTACX, MTTC1, MTTGPR, MTTHC1, MTTHI, MTTLO, ADDIUS5_MM, AND16_...
7228
    return;
7229
    break;
7230
  case 2:
7231
    // GotPrologue16, AddiuRxRxImm16, AddiuRxRxImmX16, AndRxRxRy16, BINSLI_B,...
7232
    printOperand(MI, 2, STI, O);
7233
    break;
7234
  case 3:
7235
    // LDMacro, LOAD_ACC128, LOAD_ACC64, LOAD_ACC64DSP, LOAD_CCOND_DSP, LoadA...
7236
    printMemOperand(MI, 1, STI, O);
7237
    return;
7238
    break;
7239
  case 4:
7240
    // MTTC0, DMTC0, DMTC2, DMTGC0, FORK, LSA_MMR6, MTC0, MTC0_MMR6, MTC2, MT...
7241
    O << ", ";
7242
    break;
7243
  case 5:
7244
    // MultRxRyRz16, MultuRxRyRz16
7245
    O << "\n\tmflo\t";
7246
    printOperand(MI, 0, STI, O);
7247
    return;
7248
    break;
7249
  case 6:
7250
    // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
7251
    printOperand(MI, 4, STI, O);
7252
    break;
7253
  case 7:
7254
    // SltCCRxRy16, SltiCCRxImmX16, SltiuCCRxImmX16, SltuCCRxRy16, SltuRxRyRz...
7255
    O << "\n\tmove\t";
7256
    printOperand(MI, 0, STI, O);
7257
    O << ", $t8";
7258
    return;
7259
    break;
7260
  case 8:
7261
    // AddiuRxRyOffMemX16, LEA_ADDiu, LEA_ADDiu64, LEA_ADDiu_MM
7262
    printMemOperandEA(MI, 1, STI, O);
7263
    return;
7264
    break;
7265
  case 9:
7266
    // BBIT0, BBIT032, BBIT1, BBIT132
7267
    printUImm<5>(MI, 1, STI, O);
7268
    O << ", ";
7269
    printBranchOperand(MI, Address, 2, STI, O);
7270
    return;
7271
    break;
7272
  case 10:
7273
    // BC1EQZ, BC1EQZC_MMR6, BC1F, BC1FL, BC1F_MM, BC1NEZ, BC1NEZC_MMR6, BC1T...
7274
    printBranchOperand(MI, Address, 1, STI, O);
7275
    break;
7276
  case 11:
7277
    // BREAK, BREAK_MM, BREAK_MMR6, RDDSP, WRDSP
7278
    printUImm<10>(MI, 1, STI, O);
7279
    return;
7280
    break;
7281
  case 12:
7282
    // DMFC2_OCTEON, DMTC2_OCTEON, LUI_MMR6, LUi, LUi64, LUi_MM
7283
    printUImm<16>(MI, 1, STI, O);
7284
    return;
7285
    break;
7286
  case 13:
7287
    // GINVT, GINVT_MMR6
7288
    printUImm<2>(MI, 1, STI, O);
7289
    return;
7290
    break;
7291
  case 14:
7292
    // INSERT_B
7293
    printUImm<4>(MI, 3, STI, O);
7294
    O << "], ";
7295
    printOperand(MI, 2, STI, O);
7296
    return;
7297
    break;
7298
  case 15:
7299
    // INSERT_D
7300
    printUImm<1>(MI, 3, STI, O);
7301
    O << "], ";
7302
    printOperand(MI, 2, STI, O);
7303
    return;
7304
    break;
7305
  case 16:
7306
    // INSERT_H
7307
    printUImm<3>(MI, 3, STI, O);
7308
    O << "], ";
7309
    printOperand(MI, 2, STI, O);
7310
    return;
7311
    break;
7312
  case 17:
7313
    // INSERT_W
7314
    printUImm<2>(MI, 3, STI, O);
7315
    O << "], ";
7316
    printOperand(MI, 2, STI, O);
7317
    return;
7318
    break;
7319
  case 18:
7320
    // INSVE_B
7321
    printUImm<4>(MI, 2, STI, O);
7322
    O << "], ";
7323
    printOperand(MI, 3, STI, O);
7324
    O << '[';
7325
    printUImm<0>(MI, 4, STI, O);
7326
    O << ']';
7327
    return;
7328
    break;
7329
  case 19:
7330
    // INSVE_D
7331
    printUImm<1>(MI, 2, STI, O);
7332
    O << "], ";
7333
    printOperand(MI, 3, STI, O);
7334
    O << '[';
7335
    printUImm<0>(MI, 4, STI, O);
7336
    O << ']';
7337
    return;
7338
    break;
7339
  case 20:
7340
    // INSVE_H
7341
    printUImm<3>(MI, 2, STI, O);
7342
    O << "], ";
7343
    printOperand(MI, 3, STI, O);
7344
    O << '[';
7345
    printUImm<0>(MI, 4, STI, O);
7346
    O << ']';
7347
    return;
7348
    break;
7349
  case 21:
7350
    // INSVE_W
7351
    printUImm<2>(MI, 2, STI, O);
7352
    O << "], ";
7353
    printOperand(MI, 3, STI, O);
7354
    O << '[';
7355
    printUImm<0>(MI, 4, STI, O);
7356
    O << ']';
7357
    return;
7358
    break;
7359
  case 22:
7360
    // LWP_MM, SWP_MM
7361
    printMemOperand(MI, 2, STI, O);
7362
    return;
7363
    break;
7364
  case 23:
7365
    // PREFX_MM
7366
    O << '(';
7367
    printOperand(MI, 0, STI, O);
7368
    O << ')';
7369
    return;
7370
    break;
7371
  case 24:
7372
    // RDDSP_MM, WRDSP_MM
7373
    printUImm<7>(MI, 1, STI, O);
7374
    return;
7375
    break;
7376
  case 25:
7377
    // REPL_QB, REPL_QB_MM
7378
    printUImm<8>(MI, 1, STI, O);
7379
    return;
7380
    break;
7381
  }
7382
7383
7384
  // Fragment 3 encoded into 5 bits for 18 unique commands.
7385
  switch ((Bits >> 29) & 31) {
7386
  default: llvm_unreachable("Invalid command number.");
7387
  case 0:
7388
    // ABSMacro, CFTC1, JalTwoReg, LoadAddrImm32, LoadAddrImm64, LoadImm32, L...
7389
    return;
7390
    break;
7391
  case 1:
7392
    // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
7393
    O << ", ";
7394
    break;
7395
  case 2:
7396
    // BteqzT8CmpX16, BteqzT8CmpiX16, BteqzT8SltX16, BteqzT8SltiX16, BteqzT8S...
7397
    O << "\n\tbteqz\t";
7398
    printBranchOperand(MI, Address, 2, STI, O);
7399
    return;
7400
    break;
7401
  case 3:
7402
    // BtnezT8CmpX16, BtnezT8CmpiX16, BtnezT8SltX16, BtnezT8SltiX16, BtnezT8S...
7403
    O << "\n\tbtnez\t";
7404
    printBranchOperand(MI, Address, 2, STI, O);
7405
    return;
7406
    break;
7407
  case 4:
7408
    // GotPrologue16
7409
    O << "\n\taddiu\t";
7410
    printOperand(MI, 1, STI, O);
7411
    O << ", $pc, ";
7412
    printOperand(MI, 3, STI, O);
7413
    O << "\n ";
7414
    return;
7415
    break;
7416
  case 5:
7417
    // MTTC0, DMTC0, DMTC2, DMTGC0, MTC0, MTC0_MMR6, MTC2, MTGC0, MTGC0_MM, M...
7418
    printUImm<3>(MI, 2, STI, O);
7419
    return;
7420
    break;
7421
  case 6:
7422
    // SelTBteqZCmp, SelTBteqZCmpi, SelTBteqZSlt, SelTBteqZSlti, SelTBteqZSlt...
7423
    O << "\n\tbteqz\t.+4\n\tmove ";
7424
    printOperand(MI, 1, STI, O);
7425
    O << ", ";
7426
    printOperand(MI, 2, STI, O);
7427
    return;
7428
    break;
7429
  case 7:
7430
    // SelTBtneZCmp, SelTBtneZCmpi, SelTBtneZSlt, SelTBtneZSlti, SelTBtneZSlt...
7431
    O << "\n\tbtnez\t.+4\n\tmove ";
7432
    printOperand(MI, 1, STI, O);
7433
    O << ", ";
7434
    printOperand(MI, 2, STI, O);
7435
    return;
7436
    break;
7437
  case 8:
7438
    // AddiuRxRxImm16, LwRxPcTcp16
7439
    O << "\t# 16 bit inst";
7440
    return;
7441
    break;
7442
  case 9:
7443
    // BeqzRxImm16, BnezRxImm16
7444
    O << "  # 16 bit inst";
7445
    return;
7446
    break;
7447
  case 10:
7448
    // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ...
7449
    O << '[';
7450
    break;
7451
  case 11:
7452
    // CmpiRxImm16, LiRxImm16, SltiRxImm16, SltiuRxImm16
7453
    O << " \t# 16 bit inst";
7454
    return;
7455
    break;
7456
  case 12:
7457
    // DSLL64_32
7458
    O << ", 32";
7459
    return;
7460
    break;
7461
  case 13:
7462
    // FORK
7463
    printOperand(MI, 2, STI, O);
7464
    return;
7465
    break;
7466
  case 14:
7467
    // LBUX, LBUX_MM, LDXC1, LDXC164, LHX, LHX_MM, LUXC1, LUXC164, LUXC1_MM, ...
7468
    O << '(';
7469
    printOperand(MI, 1, STI, O);
7470
    O << ')';
7471
    return;
7472
    break;
7473
  case 15:
7474
    // LSA_MMR6
7475
    printOperand(MI, 0, STI, O);
7476
    O << ", ";
7477
    printUImm<2, 1>(MI, 3, STI, O);
7478
    return;
7479
    break;
7480
  case 16:
7481
    // MTTR
7482
    printUImm<1>(MI, 2, STI, O);
7483
    O << ", ";
7484
    printUImm<3>(MI, 3, STI, O);
7485
    O << ", ";
7486
    printUImm<1>(MI, 4, STI, O);
7487
    return;
7488
    break;
7489
  case 17:
7490
    // SLL64_32, SLL64_64
7491
    O << ", 0";
7492
    return;
7493
    break;
7494
  }
7495
7496
7497
  // Fragment 4 encoded into 5 bits for 21 unique commands.
7498
  switch ((Bits >> 34) & 31) {
7499
  default: llvm_unreachable("Invalid command number.");
7500
  case 0:
7501
    // BEQLImmMacro, BGE, BGEImmMacro, BGEL, BGELImmMacro, BGEU, BGEUImmMacro...
7502
    printBranchOperand(MI, Address, 2, STI, O);
7503
    return;
7504
    break;
7505
  case 1:
7506
    // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,...
7507
    printOperand(MI, 2, STI, O);
7508
    break;
7509
  case 2:
7510
    // MFTC0, BCLRI_B, BNEGI_B, BSETI_B, COPY_S_H, COPY_U_H, DMFC0, DMFC2, DM...
7511
    printUImm<3>(MI, 2, STI, O);
7512
    break;
7513
  case 3:
7514
    // ADDVI_B, ADDVI_D, ADDVI_H, ADDVI_W, APPEND, APPEND_MMR2, BCLRI_W, BNEG...
7515
    printUImm<5>(MI, 2, STI, O);
7516
    break;
7517
  case 4:
7518
    // ANDI_B, NORI_B, ORI_B, RDHWR, RDHWR64, RDHWR_MM, SHF_B, SHF_H, SHF_W, ...
7519
    printUImm<8>(MI, 2, STI, O);
7520
    return;
7521
    break;
7522
  case 5:
7523
    // ANDI_MMR6, ANDi, ANDi64, ANDi_MM, AUI, AUI_MMR6, DAHI, DATI, DAUI, ORI...
7524
    printUImm<16>(MI, 2, STI, O);
7525
    return;
7526
    break;
7527
  case 6:
7528
    // BALIGN, BALIGN_MMR2, COPY_S_W, COPY_U_W, SPLATI_W
7529
    printUImm<2>(MI, 2, STI, O);
7530
    break;
7531
  case 7:
7532
    // BCLRI_D, BNEGI_D, BSETI_D, DEXT, DEXT64_32, DINS, DROTR, DSLL, DSRA, D...
7533
    printUImm<6>(MI, 2, STI, O);
7534
    break;
7535
  case 8:
7536
    // BCLRI_H, BNEGI_H, BSETI_H, COPY_S_B, COPY_U_B, SAT_S_H, SAT_U_H, SHLL_...
7537
    printUImm<4>(MI, 2, STI, O);
7538
    break;
7539
  case 9:
7540
    // BINSLI_B, BINSRI_B, SLDI_H
7541
    printUImm<3>(MI, 3, STI, O);
7542
    break;
7543
  case 10:
7544
    // BINSLI_D, BINSRI_D
7545
    printUImm<6>(MI, 3, STI, O);
7546
    return;
7547
    break;
7548
  case 11:
7549
    // BINSLI_H, BINSRI_H, SLDI_B
7550
    printUImm<4>(MI, 3, STI, O);
7551
    break;
7552
  case 12:
7553
    // BINSLI_W, BINSRI_W
7554
    printUImm<5>(MI, 3, STI, O);
7555
    return;
7556
    break;
7557
  case 13:
7558
    // BINSL_B, BINSL_D, BINSL_H, BINSL_W, BINSR_B, BINSR_D, BINSR_H, BINSR_W...
7559
    printOperand(MI, 3, STI, O);
7560
    break;
7561
  case 14:
7562
    // BMNZI_B, BMZI_B, BSELI_B
7563
    printUImm<8>(MI, 3, STI, O);
7564
    return;
7565
    break;
7566
  case 15:
7567
    // COPY_S_D, MFTR, SPLATI_D
7568
    printUImm<1>(MI, 2, STI, O);
7569
    break;
7570
  case 16:
7571
    // DEXTU, DINSU
7572
    printUImm<5, 32>(MI, 2, STI, O);
7573
    O << ", ";
7574
    break;
7575
  case 17:
7576
    // FADD_S_MMR6, FDIV_S_MMR6, FMUL_S_MMR6, FSUB_S_MMR6
7577
    printOperand(MI, 1, STI, O);
7578
    return;
7579
    break;
7580
  case 18:
7581
    // SLDI_D
7582
    printUImm<1>(MI, 3, STI, O);
7583
    O << ']';
7584
    return;
7585
    break;
7586
  case 19:
7587
    // SLDI_W
7588
    printUImm<2>(MI, 3, STI, O);
7589
    O << ']';
7590
    return;
7591
    break;
7592
  case 20:
7593
    // TEQ, TGE, TGEU, TLT, TLTU, TNE
7594
    printUImm<10>(MI, 2, STI, O);
7595
    return;
7596
    break;
7597
  }
7598
7599
7600
  // Fragment 5 encoded into 3 bits for 5 unique commands.
7601
  switch ((Bits >> 39) & 7) {
7602
  default: llvm_unreachable("Invalid command number.");
7603
  case 0:
7604
    // DMULImmMacro, DMULMacro, DMULOMacro, DMULOUMacro, DROL, DROLImm, DROR,...
7605
    return;
7606
    break;
7607
  case 1:
7608
    // ALIGN, ALIGN_MMR6, CINS, CINS32, CINS64_32, CINS_i32, DALIGN, DEXT, DE...
7609
    O << ", ";
7610
    break;
7611
  case 2:
7612
    // COPY_S_B, COPY_S_D, COPY_S_H, COPY_S_W, COPY_U_B, COPY_U_H, COPY_U_W, ...
7613
    O << ']';
7614
    return;
7615
    break;
7616
  case 3:
7617
    // DEXTU
7618
    printUImm<5, 1>(MI, 3, STI, O);
7619
    return;
7620
    break;
7621
  case 4:
7622
    // DINSU
7623
    printUImm<6>(MI, 3, STI, O);
7624
    return;
7625
    break;
7626
  }
7627
7628
7629
  // Fragment 6 encoded into 4 bits for 10 unique commands.
7630
  switch ((Bits >> 42) & 15) {
7631
  default: llvm_unreachable("Invalid command number.");
7632
  case 0:
7633
    // ALIGN, ALIGN_MMR6
7634
    printUImm<2>(MI, 3, STI, O);
7635
    return;
7636
    break;
7637
  case 1:
7638
    // CINS, CINS32, CINS64_32, CINS_i32, EXTS, EXTS32
7639
    printUImm<5>(MI, 3, STI, O);
7640
    return;
7641
    break;
7642
  case 2:
7643
    // DALIGN, MFTR
7644
    printUImm<3>(MI, 3, STI, O);
7645
    break;
7646
  case 3:
7647
    // DEXT
7648
    printUImm<6, 1>(MI, 3, STI, O);
7649
    return;
7650
    break;
7651
  case 4:
7652
    // DEXT64_32, EXT, EXT_MM, EXT_MMR6
7653
    printUImm<5, 1>(MI, 3, STI, O);
7654
    return;
7655
    break;
7656
  case 5:
7657
    // DEXTM
7658
    printUImm<5, 33>(MI, 3, STI, O);
7659
    return;
7660
    break;
7661
  case 6:
7662
    // DINS, INS, INS_MM, INS_MMR6
7663
    printUImm<6>(MI, 3, STI, O);
7664
    return;
7665
    break;
7666
  case 7:
7667
    // DINSM
7668
    printUImm<6, 2>(MI, 3, STI, O);
7669
    return;
7670
    break;
7671
  case 8:
7672
    // DLSA, DLSA_R6, LSA, LSA_R6
7673
    printUImm<2, 1>(MI, 3, STI, O);
7674
    return;
7675
    break;
7676
  case 9:
7677
    // MADD_D32, MADD_D32_MM, MADD_D64, MADD_S, MADD_S_MM, MOVEP_MM, MOVEP_MM...
7678
    printOperand(MI, 3, STI, O);
7679
    return;
7680
    break;
7681
  }
7682
7683
7684
  // Fragment 7 encoded into 1 bits for 2 unique commands.
7685
  if ((Bits >> 46) & 1) {
7686
    // MFTR
7687
    O << ", ";
7688
    printUImm<1>(MI, 4, STI, O);
7689
    return;
7690
  } else {
7691
    // DALIGN
7692
    return;
7693
  }
7694
7695
}
7696
7697
7698
/// getRegisterName - This method is automatically generated by tblgen
7699
/// from the register set description.  This returns the assembler name
7700
/// for the specified register.
7701
0
const char *MipsInstPrinter::getRegisterName(MCRegister Reg) {
7702
0
  unsigned RegNo = Reg.id();
7703
0
  assert(RegNo && RegNo < 442 && "Invalid register number!");
7704
7705
7706
0
#ifdef __GNUC__
7707
0
#pragma GCC diagnostic push
7708
0
#pragma GCC diagnostic ignored "-Woverlength-strings"
7709
0
#endif
7710
0
  static const char AsmStrs[] = {
7711
0
  /* 0 */ "f10\0"
7712
0
  /* 4 */ "w10\0"
7713
0
  /* 8 */ "f20\0"
7714
0
  /* 12 */ "DSPOutFlag20\0"
7715
0
  /* 25 */ "w20\0"
7716
0
  /* 29 */ "f30\0"
7717
0
  /* 33 */ "w30\0"
7718
0
  /* 37 */ "ac0\0"
7719
0
  /* 41 */ "fcc0\0"
7720
0
  /* 46 */ "f0\0"
7721
0
  /* 49 */ "mpl0\0"
7722
0
  /* 54 */ "p0\0"
7723
0
  /* 57 */ "w0\0"
7724
0
  /* 60 */ "f11\0"
7725
0
  /* 64 */ "w11\0"
7726
0
  /* 68 */ "f21\0"
7727
0
  /* 72 */ "DSPOutFlag21\0"
7728
0
  /* 85 */ "w21\0"
7729
0
  /* 89 */ "f31\0"
7730
0
  /* 93 */ "w31\0"
7731
0
  /* 97 */ "ac1\0"
7732
0
  /* 101 */ "fcc1\0"
7733
0
  /* 106 */ "f1\0"
7734
0
  /* 109 */ "mpl1\0"
7735
0
  /* 114 */ "p1\0"
7736
0
  /* 117 */ "w1\0"
7737
0
  /* 120 */ "f12\0"
7738
0
  /* 124 */ "w12\0"
7739
0
  /* 128 */ "f22\0"
7740
0
  /* 132 */ "DSPOutFlag22\0"
7741
0
  /* 145 */ "w22\0"
7742
0
  /* 149 */ "ac2\0"
7743
0
  /* 153 */ "fcc2\0"
7744
0
  /* 158 */ "f2\0"
7745
0
  /* 161 */ "mpl2\0"
7746
0
  /* 166 */ "p2\0"
7747
0
  /* 169 */ "w2\0"
7748
0
  /* 172 */ "f13\0"
7749
0
  /* 176 */ "w13\0"
7750
0
  /* 180 */ "f23\0"
7751
0
  /* 184 */ "DSPOutFlag23\0"
7752
0
  /* 197 */ "w23\0"
7753
0
  /* 201 */ "ac3\0"
7754
0
  /* 205 */ "fcc3\0"
7755
0
  /* 210 */ "f3\0"
7756
0
  /* 213 */ "w3\0"
7757
0
  /* 216 */ "f14\0"
7758
0
  /* 220 */ "w14\0"
7759
0
  /* 224 */ "f24\0"
7760
0
  /* 228 */ "w24\0"
7761
0
  /* 232 */ "fcc4\0"
7762
0
  /* 237 */ "f4\0"
7763
0
  /* 240 */ "w4\0"
7764
0
  /* 243 */ "f15\0"
7765
0
  /* 247 */ "w15\0"
7766
0
  /* 251 */ "f25\0"
7767
0
  /* 255 */ "w25\0"
7768
0
  /* 259 */ "fcc5\0"
7769
0
  /* 264 */ "f5\0"
7770
0
  /* 267 */ "w5\0"
7771
0
  /* 270 */ "f16\0"
7772
0
  /* 274 */ "w16\0"
7773
0
  /* 278 */ "f26\0"
7774
0
  /* 282 */ "w26\0"
7775
0
  /* 286 */ "fcc6\0"
7776
0
  /* 291 */ "f6\0"
7777
0
  /* 294 */ "w6\0"
7778
0
  /* 297 */ "f17\0"
7779
0
  /* 301 */ "w17\0"
7780
0
  /* 305 */ "f27\0"
7781
0
  /* 309 */ "w27\0"
7782
0
  /* 313 */ "fcc7\0"
7783
0
  /* 318 */ "f7\0"
7784
0
  /* 321 */ "w7\0"
7785
0
  /* 324 */ "f18\0"
7786
0
  /* 328 */ "w18\0"
7787
0
  /* 332 */ "f28\0"
7788
0
  /* 336 */ "w28\0"
7789
0
  /* 340 */ "f8\0"
7790
0
  /* 343 */ "w8\0"
7791
0
  /* 346 */ "DSPOutFlag16_19\0"
7792
0
  /* 362 */ "f19\0"
7793
0
  /* 366 */ "w19\0"
7794
0
  /* 370 */ "f29\0"
7795
0
  /* 374 */ "w29\0"
7796
0
  /* 378 */ "f9\0"
7797
0
  /* 381 */ "w9\0"
7798
0
  /* 384 */ "DSPEFI\0"
7799
0
  /* 391 */ "ra\0"
7800
0
  /* 394 */ "hwr_cc\0"
7801
0
  /* 401 */ "pc\0"
7802
0
  /* 404 */ "DSPCCond\0"
7803
0
  /* 413 */ "DSPOutFlag\0"
7804
0
  /* 424 */ "hi\0"
7805
0
  /* 427 */ "hwr_cpunum\0"
7806
0
  /* 438 */ "lo\0"
7807
0
  /* 441 */ "zero\0"
7808
0
  /* 446 */ "hwr_synci_step\0"
7809
0
  /* 461 */ "fp\0"
7810
0
  /* 464 */ "gp\0"
7811
0
  /* 467 */ "sp\0"
7812
0
  /* 470 */ "hwr_ccres\0"
7813
0
  /* 480 */ "DSPPos\0"
7814
0
  /* 487 */ "DSPSCount\0"
7815
0
  /* 497 */ "DSPCarry\0"
7816
0
};
7817
0
#ifdef __GNUC__
7818
0
#pragma GCC diagnostic pop
7819
0
#endif
7820
7821
0
  static const uint16_t RegAsmOffset[] = {
7822
0
    62, 404, 497, 384, 413, 480, 487, 461, 464, 122, 62, 2, 272, 218, 
7823
0
    245, 174, 299, 401, 391, 467, 441, 218, 245, 272, 299, 37, 97, 149, 
7824
0
    201, 62, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 
7825
0
    122, 174, 218, 245, 272, 299, 326, 360, 2, 62, 122, 174, 218, 245, 
7826
0
    272, 299, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 
7827
0
    9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 1, 61, 
7828
0
    121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 225, 252, 
7829
0
    279, 306, 333, 371, 30, 90, 1, 61, 121, 173, 217, 244, 271, 298, 
7830
0
    325, 359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 
7831
0
    46, 158, 237, 291, 340, 0, 120, 216, 270, 324, 8, 128, 224, 278, 
7832
0
    332, 29, 12, 72, 132, 184, 46, 106, 158, 210, 237, 264, 291, 318, 
7833
0
    340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, 
7834
0
    128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 41, 101, 153, 205, 
7835
0
    232, 259, 286, 313, 2, 62, 122, 174, 218, 245, 272, 299, 326, 360, 
7836
0
    1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 
7837
0
    225, 252, 279, 306, 333, 371, 30, 90, 461, 46, 106, 158, 210, 237, 
7838
0
    264, 291, 318, 340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 
7839
0
    362, 8, 68, 128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 464, 
7840
0
    37, 97, 149, 201, 427, 446, 394, 470, 218, 245, 272, 299, 326, 360, 
7841
0
    1, 61, 121, 173, 217, 244, 271, 298, 325, 359, 9, 69, 129, 181, 
7842
0
    225, 252, 279, 306, 333, 371, 30, 90, 279, 306, 37, 97, 149, 201, 
7843
0
    49, 109, 161, 326, 360, 1, 61, 121, 173, 217, 244, 271, 298, 325, 
7844
0
    359, 9, 69, 129, 181, 225, 252, 279, 306, 333, 371, 30, 90, 54, 
7845
0
    114, 166, 391, 271, 298, 325, 359, 9, 69, 129, 181, 467, 326, 360, 
7846
0
    1, 61, 121, 173, 217, 244, 225, 252, 122, 174, 57, 117, 169, 213, 
7847
0
    240, 267, 294, 321, 343, 381, 4, 64, 124, 176, 220, 247, 274, 301, 
7848
0
    328, 366, 25, 85, 145, 197, 228, 255, 282, 309, 336, 374, 33, 93, 
7849
0
    441, 218, 245, 272, 299, 37, 46, 106, 158, 210, 237, 264, 291, 318, 
7850
0
    340, 378, 0, 60, 120, 172, 216, 243, 270, 297, 324, 362, 8, 68, 
7851
0
    128, 180, 224, 251, 278, 305, 332, 370, 29, 89, 346, 424, 279, 306, 
7852
0
    438, 271, 298, 325, 359, 9, 69, 129, 181, 326, 360, 1, 61, 121, 
7853
0
    173, 217, 244, 225, 252, 122, 174, 
7854
0
  };
7855
7856
0
  assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&
7857
0
          "Invalid alt name index for register!");
7858
0
  return AsmStrs+RegAsmOffset[RegNo-1];
7859
0
}
7860
7861
#ifdef PRINT_ALIAS_INSTR
7862
#undef PRINT_ALIAS_INSTR
7863
7864
0
bool MipsInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
7865
0
  static const PatternsForOpcode OpToPatterns[] = {
7866
0
    {Mips::MFTACX, 0, 1 },
7867
0
    {Mips::MFTC0, 1, 1 },
7868
0
    {Mips::MFTHI, 2, 1 },
7869
0
    {Mips::MFTLO, 3, 1 },
7870
0
    {Mips::MTTACX, 4, 1 },
7871
0
    {Mips::MTTC0, 5, 1 },
7872
0
    {Mips::MTTHI, 6, 1 },
7873
0
    {Mips::MTTLO, 7, 1 },
7874
0
    {Mips::NORImm, 8, 1 },
7875
0
    {Mips::NORImm64, 9, 1 },
7876
0
    {Mips::SLTImm64, 10, 1 },
7877
0
    {Mips::SLTUImm64, 11, 1 },
7878
0
    {Mips::ADDIUPC, 12, 1 },
7879
0
    {Mips::ADDIUPC_MMR6, 13, 1 },
7880
0
    {Mips::ADDu, 14, 1 },
7881
0
    {Mips::BC1F, 15, 1 },
7882
0
    {Mips::BC1FL, 16, 1 },
7883
0
    {Mips::BC1F_MM, 17, 1 },
7884
0
    {Mips::BC1T, 18, 1 },
7885
0
    {Mips::BC1TL, 19, 1 },
7886
0
    {Mips::BC1T_MM, 20, 1 },
7887
0
    {Mips::BEQL, 21, 1 },
7888
0
    {Mips::BGEZAL, 22, 1 },
7889
0
    {Mips::BGEZAL_MM, 23, 1 },
7890
0
    {Mips::BNEL, 24, 1 },
7891
0
    {Mips::BREAK, 25, 2 },
7892
0
    {Mips::BREAK_MM, 27, 2 },
7893
0
    {Mips::C_EQ_D32, 29, 1 },
7894
0
    {Mips::C_EQ_D32_MM, 30, 1 },
7895
0
    {Mips::C_EQ_D64, 31, 1 },
7896
0
    {Mips::C_EQ_D64_MM, 32, 1 },
7897
0
    {Mips::C_EQ_S, 33, 1 },
7898
0
    {Mips::C_EQ_S_MM, 34, 1 },
7899
0
    {Mips::C_F_D32, 35, 1 },
7900
0
    {Mips::C_F_D32_MM, 36, 1 },
7901
0
    {Mips::C_F_D64, 37, 1 },
7902
0
    {Mips::C_F_D64_MM, 38, 1 },
7903
0
    {Mips::C_F_S, 39, 1 },
7904
0
    {Mips::C_F_S_MM, 40, 1 },
7905
0
    {Mips::C_LE_D32, 41, 1 },
7906
0
    {Mips::C_LE_D32_MM, 42, 1 },
7907
0
    {Mips::C_LE_D64, 43, 1 },
7908
0
    {Mips::C_LE_D64_MM, 44, 1 },
7909
0
    {Mips::C_LE_S, 45, 1 },
7910
0
    {Mips::C_LE_S_MM, 46, 1 },
7911
0
    {Mips::C_LT_D32, 47, 1 },
7912
0
    {Mips::C_LT_D32_MM, 48, 1 },
7913
0
    {Mips::C_LT_D64, 49, 1 },
7914
0
    {Mips::C_LT_D64_MM, 50, 1 },
7915
0
    {Mips::C_LT_S, 51, 1 },
7916
0
    {Mips::C_LT_S_MM, 52, 1 },
7917
0
    {Mips::C_NGE_D32, 53, 1 },
7918
0
    {Mips::C_NGE_D32_MM, 54, 1 },
7919
0
    {Mips::C_NGE_D64, 55, 1 },
7920
0
    {Mips::C_NGE_D64_MM, 56, 1 },
7921
0
    {Mips::C_NGE_S, 57, 1 },
7922
0
    {Mips::C_NGE_S_MM, 58, 1 },
7923
0
    {Mips::C_NGLE_D32, 59, 1 },
7924
0
    {Mips::C_NGLE_D32_MM, 60, 1 },
7925
0
    {Mips::C_NGLE_D64, 61, 1 },
7926
0
    {Mips::C_NGLE_D64_MM, 62, 1 },
7927
0
    {Mips::C_NGLE_S, 63, 1 },
7928
0
    {Mips::C_NGLE_S_MM, 64, 1 },
7929
0
    {Mips::C_NGL_D32, 65, 1 },
7930
0
    {Mips::C_NGL_D32_MM, 66, 1 },
7931
0
    {Mips::C_NGL_D64, 67, 1 },
7932
0
    {Mips::C_NGL_D64_MM, 68, 1 },
7933
0
    {Mips::C_NGL_S, 69, 1 },
7934
0
    {Mips::C_NGL_S_MM, 70, 1 },
7935
0
    {Mips::C_NGT_D32, 71, 1 },
7936
0
    {Mips::C_NGT_D32_MM, 72, 1 },
7937
0
    {Mips::C_NGT_D64, 73, 1 },
7938
0
    {Mips::C_NGT_D64_MM, 74, 1 },
7939
0
    {Mips::C_NGT_S, 75, 1 },
7940
0
    {Mips::C_NGT_S_MM, 76, 1 },
7941
0
    {Mips::C_OLE_D32, 77, 1 },
7942
0
    {Mips::C_OLE_D32_MM, 78, 1 },
7943
0
    {Mips::C_OLE_D64, 79, 1 },
7944
0
    {Mips::C_OLE_D64_MM, 80, 1 },
7945
0
    {Mips::C_OLE_S, 81, 1 },
7946
0
    {Mips::C_OLE_S_MM, 82, 1 },
7947
0
    {Mips::C_OLT_D32, 83, 1 },
7948
0
    {Mips::C_OLT_D32_MM, 84, 1 },
7949
0
    {Mips::C_OLT_D64, 85, 1 },
7950
0
    {Mips::C_OLT_D64_MM, 86, 1 },
7951
0
    {Mips::C_OLT_S, 87, 1 },
7952
0
    {Mips::C_OLT_S_MM, 88, 1 },
7953
0
    {Mips::C_SEQ_D32, 89, 1 },
7954
0
    {Mips::C_SEQ_D32_MM, 90, 1 },
7955
0
    {Mips::C_SEQ_D64, 91, 1 },
7956
0
    {Mips::C_SEQ_D64_MM, 92, 1 },
7957
0
    {Mips::C_SEQ_S, 93, 1 },
7958
0
    {Mips::C_SEQ_S_MM, 94, 1 },
7959
0
    {Mips::C_SF_D32, 95, 1 },
7960
0
    {Mips::C_SF_D32_MM, 96, 1 },
7961
0
    {Mips::C_SF_D64, 97, 1 },
7962
0
    {Mips::C_SF_D64_MM, 98, 1 },
7963
0
    {Mips::C_SF_S, 99, 1 },
7964
0
    {Mips::C_SF_S_MM, 100, 1 },
7965
0
    {Mips::C_UEQ_D32, 101, 1 },
7966
0
    {Mips::C_UEQ_D32_MM, 102, 1 },
7967
0
    {Mips::C_UEQ_D64, 103, 1 },
7968
0
    {Mips::C_UEQ_D64_MM, 104, 1 },
7969
0
    {Mips::C_UEQ_S, 105, 1 },
7970
0
    {Mips::C_UEQ_S_MM, 106, 1 },
7971
0
    {Mips::C_ULE_D32, 107, 1 },
7972
0
    {Mips::C_ULE_D32_MM, 108, 1 },
7973
0
    {Mips::C_ULE_D64, 109, 1 },
7974
0
    {Mips::C_ULE_D64_MM, 110, 1 },
7975
0
    {Mips::C_ULE_S, 111, 1 },
7976
0
    {Mips::C_ULE_S_MM, 112, 1 },
7977
0
    {Mips::C_ULT_D32, 113, 1 },
7978
0
    {Mips::C_ULT_D32_MM, 114, 1 },
7979
0
    {Mips::C_ULT_D64, 115, 1 },
7980
0
    {Mips::C_ULT_D64_MM, 116, 1 },
7981
0
    {Mips::C_ULT_S, 117, 1 },
7982
0
    {Mips::C_ULT_S_MM, 118, 1 },
7983
0
    {Mips::C_UN_D32, 119, 1 },
7984
0
    {Mips::C_UN_D32_MM, 120, 1 },
7985
0
    {Mips::C_UN_D64, 121, 1 },
7986
0
    {Mips::C_UN_D64_MM, 122, 1 },
7987
0
    {Mips::C_UN_S, 123, 1 },
7988
0
    {Mips::C_UN_S_MM, 124, 1 },
7989
0
    {Mips::DADDu, 125, 1 },
7990
0
    {Mips::DI, 126, 1 },
7991
0
    {Mips::DIV, 127, 1 },
7992
0
    {Mips::DIVU, 128, 1 },
7993
0
    {Mips::DI_MM, 129, 1 },
7994
0
    {Mips::DI_MMR6, 130, 1 },
7995
0
    {Mips::DMT, 131, 1 },
7996
0
    {Mips::DSUB, 132, 2 },
7997
0
    {Mips::DSUBu, 134, 2 },
7998
0
    {Mips::DVPE, 136, 1 },
7999
0
    {Mips::EI, 137, 1 },
8000
0
    {Mips::EI_MM, 138, 1 },
8001
0
    {Mips::EI_MMR6, 139, 1 },
8002
0
    {Mips::EMT, 140, 1 },
8003
0
    {Mips::EVPE, 141, 1 },
8004
0
    {Mips::HYPCALL, 142, 1 },
8005
0
    {Mips::HYPCALL_MM, 143, 1 },
8006
0
    {Mips::JALR, 144, 1 },
8007
0
    {Mips::JALR64, 145, 1 },
8008
0
    {Mips::JALRC_HB_MMR6, 146, 1 },
8009
0
    {Mips::JALRC_MMR6, 147, 1 },
8010
0
    {Mips::JALR_HB, 148, 1 },
8011
0
    {Mips::JALR_HB64, 149, 1 },
8012
0
    {Mips::JIALC, 150, 1 },
8013
0
    {Mips::JIALC64, 151, 1 },
8014
0
    {Mips::JIC, 152, 1 },
8015
0
    {Mips::JIC64, 153, 1 },
8016
0
    {Mips::MOVE16_MM, 154, 1 },
8017
0
    {Mips::Move32R16, 155, 1 },
8018
0
    {Mips::OR, 156, 1 },
8019
0
    {Mips::OR64, 157, 1 },
8020
0
    {Mips::RDHWR, 158, 1 },
8021
0
    {Mips::RDHWR64, 159, 1 },
8022
0
    {Mips::RDHWR_MM, 160, 1 },
8023
0
    {Mips::RDHWR_MMR6, 161, 1 },
8024
0
    {Mips::SDBBP, 162, 1 },
8025
0
    {Mips::SDBBP_MMR6, 163, 1 },
8026
0
    {Mips::SDBBP_R6, 164, 1 },
8027
0
    {Mips::SIGRIE, 165, 1 },
8028
0
    {Mips::SIGRIE_MMR6, 166, 1 },
8029
0
    {Mips::SLL, 167, 1 },
8030
0
    {Mips::SLL_MM, 168, 1 },
8031
0
    {Mips::SLL_MMR6, 169, 1 },
8032
0
    {Mips::SUB, 170, 2 },
8033
0
    {Mips::SUBU_MMR6, 172, 2 },
8034
0
    {Mips::SUB_MM, 174, 2 },
8035
0
    {Mips::SUB_MMR6, 176, 2 },
8036
0
    {Mips::SUBu, 178, 2 },
8037
0
    {Mips::SUBu_MM, 180, 2 },
8038
0
    {Mips::SWSP_MM, 182, 1 },
8039
0
    {Mips::SYNC, 183, 1 },
8040
0
    {Mips::SYNC_MM, 184, 1 },
8041
0
    {Mips::SYNC_MMR6, 185, 1 },
8042
0
    {Mips::SYSCALL, 186, 1 },
8043
0
    {Mips::SYSCALL_MM, 187, 1 },
8044
0
    {Mips::TEQ, 188, 1 },
8045
0
    {Mips::TEQ_MM, 189, 1 },
8046
0
    {Mips::TGE, 190, 1 },
8047
0
    {Mips::TGEU, 191, 1 },
8048
0
    {Mips::TGEU_MM, 192, 1 },
8049
0
    {Mips::TGE_MM, 193, 1 },
8050
0
    {Mips::TLT, 194, 1 },
8051
0
    {Mips::TLTU, 195, 1 },
8052
0
    {Mips::TLTU_MM, 196, 1 },
8053
0
    {Mips::TLT_MM, 197, 1 },
8054
0
    {Mips::TNE, 198, 1 },
8055
0
    {Mips::TNE_MM, 199, 1 },
8056
0
    {Mips::WAIT_MM, 200, 1 },
8057
0
    {Mips::WRDSP, 201, 1 },
8058
0
    {Mips::WRDSP_MM, 202, 1 },
8059
0
    {Mips::YIELD, 203, 1 },
8060
0
  };
8061
8062
0
  static const AliasPattern Patterns[] = {
8063
    // Mips::MFTACX - 0
8064
0
    {0, 0, 2, 4 },
8065
    // Mips::MFTC0 - 1
8066
0
    {10, 4, 3, 5 },
8067
    // Mips::MFTHI - 2
8068
0
    {23, 9, 2, 4 },
8069
    // Mips::MFTLO - 3
8070
0
    {32, 13, 2, 4 },
8071
    // Mips::MTTACX - 4
8072
0
    {41, 17, 2, 4 },
8073
    // Mips::MTTC0 - 5
8074
0
    {51, 21, 3, 5 },
8075
    // Mips::MTTHI - 6
8076
0
    {64, 26, 2, 4 },
8077
    // Mips::MTTLO - 7
8078
0
    {73, 30, 2, 4 },
8079
    // Mips::NORImm - 8
8080
0
    {82, 34, 3, 3 },
8081
    // Mips::NORImm64 - 9
8082
0
    {82, 37, 3, 3 },
8083
    // Mips::SLTImm64 - 10
8084
0
    {93, 40, 3, 3 },
8085
    // Mips::SLTUImm64 - 11
8086
0
    {104, 43, 3, 3 },
8087
    // Mips::ADDIUPC - 12
8088
0
    {116, 46, 2, 3 },
8089
    // Mips::ADDIUPC_MMR6 - 13
8090
0
    {116, 49, 2, 3 },
8091
    // Mips::ADDu - 14
8092
0
    {128, 52, 3, 6 },
8093
    // Mips::BC1F - 15
8094
0
    {140, 58, 2, 6 },
8095
    // Mips::BC1FL - 16
8096
0
    {150, 64, 2, 7 },
8097
    // Mips::BC1F_MM - 17
8098
0
    {140, 71, 2, 4 },
8099
    // Mips::BC1T - 18
8100
0
    {161, 75, 2, 6 },
8101
    // Mips::BC1TL - 19
8102
0
    {171, 81, 2, 7 },
8103
    // Mips::BC1T_MM - 20
8104
0
    {161, 88, 2, 4 },
8105
    // Mips::BEQL - 21
8106
0
    {182, 92, 3, 5 },
8107
    // Mips::BGEZAL - 22
8108
0
    {197, 97, 2, 5 },
8109
    // Mips::BGEZAL_MM - 23
8110
0
    {197, 102, 2, 3 },
8111
    // Mips::BNEL - 24
8112
0
    {206, 105, 3, 5 },
8113
    // Mips::BREAK - 25
8114
0
    {221, 110, 2, 4 },
8115
0
    {227, 114, 2, 4 },
8116
    // Mips::BREAK_MM - 27
8117
0
    {221, 118, 2, 3 },
8118
0
    {227, 121, 2, 3 },
8119
    // Mips::C_EQ_D32 - 29
8120
0
    {238, 124, 3, 9 },
8121
    // Mips::C_EQ_D32_MM - 30
8122
0
    {238, 133, 3, 7 },
8123
    // Mips::C_EQ_D64 - 31
8124
0
    {238, 140, 3, 9 },
8125
    // Mips::C_EQ_D64_MM - 32
8126
0
    {238, 149, 3, 7 },
8127
    // Mips::C_EQ_S - 33
8128
0
    {252, 156, 3, 8 },
8129
    // Mips::C_EQ_S_MM - 34
8130
0
    {252, 164, 3, 6 },
8131
    // Mips::C_F_D32 - 35
8132
0
    {266, 170, 3, 9 },
8133
    // Mips::C_F_D32_MM - 36
8134
0
    {266, 179, 3, 7 },
8135
    // Mips::C_F_D64 - 37
8136
0
    {266, 186, 3, 9 },
8137
    // Mips::C_F_D64_MM - 38
8138
0
    {266, 195, 3, 7 },
8139
    // Mips::C_F_S - 39
8140
0
    {279, 202, 3, 8 },
8141
    // Mips::C_F_S_MM - 40
8142
0
    {279, 210, 3, 6 },
8143
    // Mips::C_LE_D32 - 41
8144
0
    {292, 216, 3, 9 },
8145
    // Mips::C_LE_D32_MM - 42
8146
0
    {292, 225, 3, 7 },
8147
    // Mips::C_LE_D64 - 43
8148
0
    {292, 232, 3, 9 },
8149
    // Mips::C_LE_D64_MM - 44
8150
0
    {292, 241, 3, 7 },
8151
    // Mips::C_LE_S - 45
8152
0
    {306, 248, 3, 8 },
8153
    // Mips::C_LE_S_MM - 46
8154
0
    {306, 256, 3, 6 },
8155
    // Mips::C_LT_D32 - 47
8156
0
    {320, 262, 3, 9 },
8157
    // Mips::C_LT_D32_MM - 48
8158
0
    {320, 271, 3, 7 },
8159
    // Mips::C_LT_D64 - 49
8160
0
    {320, 278, 3, 9 },
8161
    // Mips::C_LT_D64_MM - 50
8162
0
    {320, 287, 3, 7 },
8163
    // Mips::C_LT_S - 51
8164
0
    {334, 294, 3, 8 },
8165
    // Mips::C_LT_S_MM - 52
8166
0
    {334, 302, 3, 6 },
8167
    // Mips::C_NGE_D32 - 53
8168
0
    {348, 308, 3, 9 },
8169
    // Mips::C_NGE_D32_MM - 54
8170
0
    {348, 317, 3, 7 },
8171
    // Mips::C_NGE_D64 - 55
8172
0
    {348, 324, 3, 9 },
8173
    // Mips::C_NGE_D64_MM - 56
8174
0
    {348, 333, 3, 7 },
8175
    // Mips::C_NGE_S - 57
8176
0
    {363, 340, 3, 8 },
8177
    // Mips::C_NGE_S_MM - 58
8178
0
    {363, 348, 3, 6 },
8179
    // Mips::C_NGLE_D32 - 59
8180
0
    {378, 354, 3, 9 },
8181
    // Mips::C_NGLE_D32_MM - 60
8182
0
    {378, 363, 3, 7 },
8183
    // Mips::C_NGLE_D64 - 61
8184
0
    {378, 370, 3, 9 },
8185
    // Mips::C_NGLE_D64_MM - 62
8186
0
    {378, 379, 3, 7 },
8187
    // Mips::C_NGLE_S - 63
8188
0
    {394, 386, 3, 8 },
8189
    // Mips::C_NGLE_S_MM - 64
8190
0
    {394, 394, 3, 6 },
8191
    // Mips::C_NGL_D32 - 65
8192
0
    {410, 400, 3, 9 },
8193
    // Mips::C_NGL_D32_MM - 66
8194
0
    {410, 409, 3, 7 },
8195
    // Mips::C_NGL_D64 - 67
8196
0
    {410, 416, 3, 9 },
8197
    // Mips::C_NGL_D64_MM - 68
8198
0
    {410, 425, 3, 7 },
8199
    // Mips::C_NGL_S - 69
8200
0
    {425, 432, 3, 8 },
8201
    // Mips::C_NGL_S_MM - 70
8202
0
    {425, 440, 3, 6 },
8203
    // Mips::C_NGT_D32 - 71
8204
0
    {440, 446, 3, 9 },
8205
    // Mips::C_NGT_D32_MM - 72
8206
0
    {440, 455, 3, 7 },
8207
    // Mips::C_NGT_D64 - 73
8208
0
    {440, 462, 3, 9 },
8209
    // Mips::C_NGT_D64_MM - 74
8210
0
    {440, 471, 3, 7 },
8211
    // Mips::C_NGT_S - 75
8212
0
    {455, 478, 3, 8 },
8213
    // Mips::C_NGT_S_MM - 76
8214
0
    {455, 486, 3, 6 },
8215
    // Mips::C_OLE_D32 - 77
8216
0
    {470, 492, 3, 9 },
8217
    // Mips::C_OLE_D32_MM - 78
8218
0
    {470, 501, 3, 7 },
8219
    // Mips::C_OLE_D64 - 79
8220
0
    {470, 508, 3, 9 },
8221
    // Mips::C_OLE_D64_MM - 80
8222
0
    {470, 517, 3, 7 },
8223
    // Mips::C_OLE_S - 81
8224
0
    {485, 524, 3, 8 },
8225
    // Mips::C_OLE_S_MM - 82
8226
0
    {485, 532, 3, 6 },
8227
    // Mips::C_OLT_D32 - 83
8228
0
    {500, 538, 3, 9 },
8229
    // Mips::C_OLT_D32_MM - 84
8230
0
    {500, 547, 3, 7 },
8231
    // Mips::C_OLT_D64 - 85
8232
0
    {500, 554, 3, 9 },
8233
    // Mips::C_OLT_D64_MM - 86
8234
0
    {500, 563, 3, 7 },
8235
    // Mips::C_OLT_S - 87
8236
0
    {515, 570, 3, 8 },
8237
    // Mips::C_OLT_S_MM - 88
8238
0
    {515, 578, 3, 6 },
8239
    // Mips::C_SEQ_D32 - 89
8240
0
    {530, 584, 3, 9 },
8241
    // Mips::C_SEQ_D32_MM - 90
8242
0
    {530, 593, 3, 7 },
8243
    // Mips::C_SEQ_D64 - 91
8244
0
    {530, 600, 3, 9 },
8245
    // Mips::C_SEQ_D64_MM - 92
8246
0
    {530, 609, 3, 7 },
8247
    // Mips::C_SEQ_S - 93
8248
0
    {545, 616, 3, 8 },
8249
    // Mips::C_SEQ_S_MM - 94
8250
0
    {545, 624, 3, 6 },
8251
    // Mips::C_SF_D32 - 95
8252
0
    {560, 630, 3, 9 },
8253
    // Mips::C_SF_D32_MM - 96
8254
0
    {560, 639, 3, 7 },
8255
    // Mips::C_SF_D64 - 97
8256
0
    {560, 646, 3, 9 },
8257
    // Mips::C_SF_D64_MM - 98
8258
0
    {560, 655, 3, 7 },
8259
    // Mips::C_SF_S - 99
8260
0
    {574, 662, 3, 8 },
8261
    // Mips::C_SF_S_MM - 100
8262
0
    {574, 670, 3, 6 },
8263
    // Mips::C_UEQ_D32 - 101
8264
0
    {588, 676, 3, 9 },
8265
    // Mips::C_UEQ_D32_MM - 102
8266
0
    {588, 685, 3, 7 },
8267
    // Mips::C_UEQ_D64 - 103
8268
0
    {588, 692, 3, 9 },
8269
    // Mips::C_UEQ_D64_MM - 104
8270
0
    {588, 701, 3, 7 },
8271
    // Mips::C_UEQ_S - 105
8272
0
    {603, 708, 3, 8 },
8273
    // Mips::C_UEQ_S_MM - 106
8274
0
    {603, 716, 3, 6 },
8275
    // Mips::C_ULE_D32 - 107
8276
0
    {618, 722, 3, 9 },
8277
    // Mips::C_ULE_D32_MM - 108
8278
0
    {618, 731, 3, 7 },
8279
    // Mips::C_ULE_D64 - 109
8280
0
    {618, 738, 3, 9 },
8281
    // Mips::C_ULE_D64_MM - 110
8282
0
    {618, 747, 3, 7 },
8283
    // Mips::C_ULE_S - 111
8284
0
    {633, 754, 3, 8 },
8285
    // Mips::C_ULE_S_MM - 112
8286
0
    {633, 762, 3, 6 },
8287
    // Mips::C_ULT_D32 - 113
8288
0
    {648, 768, 3, 9 },
8289
    // Mips::C_ULT_D32_MM - 114
8290
0
    {648, 777, 3, 7 },
8291
    // Mips::C_ULT_D64 - 115
8292
0
    {648, 784, 3, 9 },
8293
    // Mips::C_ULT_D64_MM - 116
8294
0
    {648, 793, 3, 7 },
8295
    // Mips::C_ULT_S - 117
8296
0
    {663, 800, 3, 8 },
8297
    // Mips::C_ULT_S_MM - 118
8298
0
    {663, 808, 3, 6 },
8299
    // Mips::C_UN_D32 - 119
8300
0
    {678, 814, 3, 9 },
8301
    // Mips::C_UN_D32_MM - 120
8302
0
    {678, 823, 3, 7 },
8303
    // Mips::C_UN_D64 - 121
8304
0
    {678, 830, 3, 9 },
8305
    // Mips::C_UN_D64_MM - 122
8306
0
    {678, 839, 3, 7 },
8307
    // Mips::C_UN_S - 123
8308
0
    {692, 846, 3, 8 },
8309
    // Mips::C_UN_S_MM - 124
8310
0
    {692, 854, 3, 6 },
8311
    // Mips::DADDu - 125
8312
0
    {128, 860, 3, 5 },
8313
    // Mips::DI - 126
8314
0
    {706, 865, 1, 4 },
8315
    // Mips::DIV - 127
8316
0
    {709, 869, 3, 5 },
8317
    // Mips::DIVU - 128
8318
0
    {720, 874, 3, 5 },
8319
    // Mips::DI_MM - 129
8320
0
    {706, 879, 1, 2 },
8321
    // Mips::DI_MMR6 - 130
8322
0
    {706, 881, 1, 3 },
8323
    // Mips::DMT - 131
8324
0
    {732, 884, 1, 3 },
8325
    // Mips::DSUB - 132
8326
0
    {736, 887, 3, 6 },
8327
0
    {748, 893, 3, 6 },
8328
    // Mips::DSUBu - 134
8329
0
    {756, 899, 3, 6 },
8330
0
    {769, 905, 3, 6 },
8331
    // Mips::DVPE - 136
8332
0
    {778, 911, 1, 3 },
8333
    // Mips::EI - 137
8334
0
    {783, 914, 1, 4 },
8335
    // Mips::EI_MM - 138
8336
0
    {783, 918, 1, 2 },
8337
    // Mips::EI_MMR6 - 139
8338
0
    {783, 920, 1, 3 },
8339
    // Mips::EMT - 140
8340
0
    {786, 923, 1, 3 },
8341
    // Mips::EVPE - 141
8342
0
    {790, 926, 1, 3 },
8343
    // Mips::HYPCALL - 142
8344
0
    {795, 929, 1, 5 },
8345
    // Mips::HYPCALL_MM - 143
8346
0
    {795, 934, 1, 4 },
8347
    // Mips::JALR - 144
8348
0
    {803, 938, 2, 6 },
8349
    // Mips::JALR64 - 145
8350
0
    {803, 944, 2, 4 },
8351
    // Mips::JALRC_HB_MMR6 - 146
8352
0
    {809, 948, 2, 4 },
8353
    // Mips::JALRC_MMR6 - 147
8354
0
    {821, 952, 2, 4 },
8355
    // Mips::JALR_HB - 148
8356
0
    {830, 956, 2, 5 },
8357
    // Mips::JALR_HB64 - 149
8358
0
    {830, 961, 2, 5 },
8359
    // Mips::JIALC - 150
8360
0
    {841, 966, 2, 6 },
8361
    // Mips::JIALC64 - 151
8362
0
    {841, 972, 2, 4 },
8363
    // Mips::JIC - 152
8364
0
    {850, 976, 2, 5 },
8365
    // Mips::JIC64 - 153
8366
0
    {850, 981, 2, 4 },
8367
    // Mips::MOVE16_MM - 154
8368
0
    {857, 985, 2, 3 },
8369
    // Mips::Move32R16 - 155
8370
0
    {857, 988, 2, 3 },
8371
    // Mips::OR - 156
8372
0
    {128, 991, 3, 6 },
8373
    // Mips::OR64 - 157
8374
0
    {128, 997, 3, 5 },
8375
    // Mips::RDHWR - 158
8376
0
    {861, 1002, 3, 5 },
8377
    // Mips::RDHWR64 - 159
8378
0
    {861, 1007, 3, 4 },
8379
    // Mips::RDHWR_MM - 160
8380
0
    {861, 1011, 3, 5 },
8381
    // Mips::RDHWR_MMR6 - 161
8382
0
    {861, 1016, 3, 5 },
8383
    // Mips::SDBBP - 162
8384
0
    {874, 1021, 1, 5 },
8385
    // Mips::SDBBP_MMR6 - 163
8386
0
    {874, 1026, 1, 3 },
8387
    // Mips::SDBBP_R6 - 164
8388
0
    {874, 1029, 1, 4 },
8389
    // Mips::SIGRIE - 165
8390
0
    {880, 1033, 1, 4 },
8391
    // Mips::SIGRIE_MMR6 - 166
8392
0
    {880, 1037, 1, 3 },
8393
    // Mips::SLL - 167
8394
0
    {857, 1040, 3, 5 },
8395
    // Mips::SLL_MM - 168
8396
0
    {857, 1045, 3, 4 },
8397
    // Mips::SLL_MMR6 - 169
8398
0
    {857, 1049, 3, 5 },
8399
    // Mips::SUB - 170
8400
0
    {887, 1054, 3, 5 },
8401
0
    {898, 1059, 3, 5 },
8402
    // Mips::SUBU_MMR6 - 172
8403
0
    {905, 1064, 3, 5 },
8404
0
    {917, 1069, 3, 5 },
8405
    // Mips::SUB_MM - 174
8406
0
    {887, 1074, 3, 5 },
8407
0
    {898, 1079, 3, 5 },
8408
    // Mips::SUB_MMR6 - 176
8409
0
    {887, 1084, 3, 5 },
8410
0
    {898, 1089, 3, 5 },
8411
    // Mips::SUBu - 178
8412
0
    {905, 1094, 3, 5 },
8413
0
    {917, 1099, 3, 5 },
8414
    // Mips::SUBu_MM - 180
8415
0
    {905, 1104, 3, 5 },
8416
0
    {917, 1109, 3, 5 },
8417
    // Mips::SWSP_MM - 182
8418
0
    {925, 1114, 3, 2 },
8419
    // Mips::SYNC - 183
8420
0
    {937, 1116, 1, 4 },
8421
    // Mips::SYNC_MM - 184
8422
0
    {937, 1120, 1, 2 },
8423
    // Mips::SYNC_MMR6 - 185
8424
0
    {937, 1122, 1, 3 },
8425
    // Mips::SYSCALL - 186
8426
0
    {942, 1125, 1, 3 },
8427
    // Mips::SYSCALL_MM - 187
8428
0
    {942, 1128, 1, 2 },
8429
    // Mips::TEQ - 188
8430
0
    {950, 1130, 3, 6 },
8431
    // Mips::TEQ_MM - 189
8432
0
    {950, 1136, 3, 4 },
8433
    // Mips::TGE - 190
8434
0
    {961, 1140, 3, 6 },
8435
    // Mips::TGEU - 191
8436
0
    {972, 1146, 3, 6 },
8437
    // Mips::TGEU_MM - 192
8438
0
    {972, 1152, 3, 4 },
8439
    // Mips::TGE_MM - 193
8440
0
    {961, 1156, 3, 4 },
8441
    // Mips::TLT - 194
8442
0
    {984, 1160, 3, 6 },
8443
    // Mips::TLTU - 195
8444
0
    {995, 1166, 3, 6 },
8445
    // Mips::TLTU_MM - 196
8446
0
    {995, 1172, 3, 4 },
8447
    // Mips::TLT_MM - 197
8448
0
    {984, 1176, 3, 4 },
8449
    // Mips::TNE - 198
8450
0
    {1007, 1180, 3, 6 },
8451
    // Mips::TNE_MM - 199
8452
0
    {1007, 1186, 3, 4 },
8453
    // Mips::WAIT_MM - 200
8454
0
    {1018, 1190, 1, 2 },
8455
    // Mips::WRDSP - 201
8456
0
    {1023, 1192, 2, 4 },
8457
    // Mips::WRDSP_MM - 202
8458
0
    {1023, 1196, 2, 4 },
8459
    // Mips::YIELD - 203
8460
0
    {1032, 1200, 2, 4 },
8461
0
  };
8462
8463
0
  static const AliasPatternCond Conds[] = {
8464
    // (MFTACX GPR32Opnd:$rt, AC0) - 0
8465
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8466
0
    {AliasPatternCond::K_Reg, Mips::AC0},
8467
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8468
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8469
    // (MFTC0 GPR32Opnd:$rd, COP0Opnd:$rt, 0) - 4
8470
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8471
0
    {AliasPatternCond::K_RegClass, Mips::COP0RegClassID},
8472
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8473
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8474
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8475
    // (MFTHI GPR32Opnd:$rt, AC0) - 9
8476
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8477
0
    {AliasPatternCond::K_Reg, Mips::AC0},
8478
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8479
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8480
    // (MFTLO GPR32Opnd:$rt, AC0) - 13
8481
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8482
0
    {AliasPatternCond::K_Reg, Mips::AC0},
8483
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8484
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8485
    // (MTTACX AC0, GPR32Opnd:$rt) - 17
8486
0
    {AliasPatternCond::K_Reg, Mips::AC0},
8487
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8488
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8489
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8490
    // (MTTC0 COP0Opnd:$rt, GPR32Opnd:$rd, 0) - 21
8491
0
    {AliasPatternCond::K_RegClass, Mips::COP0RegClassID},
8492
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8493
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8494
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8495
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8496
    // (MTTHI AC0, GPR32Opnd:$rt) - 26
8497
0
    {AliasPatternCond::K_Reg, Mips::AC0},
8498
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8499
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8500
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8501
    // (MTTLO AC0, GPR32Opnd:$rt) - 30
8502
0
    {AliasPatternCond::K_Reg, Mips::AC0},
8503
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8504
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
8505
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8506
    // (NORImm GPR32Opnd:$rs, GPR32Opnd:$rs, simm32_relaxed:$imm) - 34
8507
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8508
0
    {AliasPatternCond::K_TiedReg, 0},
8509
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
8510
    // (NORImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 37
8511
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
8512
0
    {AliasPatternCond::K_TiedReg, 0},
8513
0
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
8514
    // (SLTImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 40
8515
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
8516
0
    {AliasPatternCond::K_TiedReg, 0},
8517
0
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
8518
    // (SLTUImm64 GPR64Opnd:$rs, GPR64Opnd:$rs, imm64:$imm) - 43
8519
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
8520
0
    {AliasPatternCond::K_TiedReg, 0},
8521
0
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
8522
    // (ADDIUPC GPR32Opnd:$rd, simm19_lsl2:$imm) - 46
8523
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8524
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8525
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
8526
    // (ADDIUPC_MMR6 GPR32Opnd:$rd, simm19_lsl2:$imm) - 49
8527
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8528
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8529
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
8530
    // (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 52
8531
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8532
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8533
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
8534
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8535
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
8536
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8537
    // (BC1F FCC0, brtarget:$offset) - 58
8538
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8539
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8540
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8541
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8542
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8543
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8544
    // (BC1FL FCC0, brtarget:$offset) - 64
8545
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8546
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8547
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
8548
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8549
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8550
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8551
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8552
    // (BC1F_MM FCC0, brtarget:$offset) - 71
8553
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8554
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8555
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8556
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8557
    // (BC1T FCC0, brtarget:$offset) - 75
8558
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8559
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8560
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8561
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8562
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8563
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8564
    // (BC1TL FCC0, brtarget:$offset) - 81
8565
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8566
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8567
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
8568
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8569
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8570
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8571
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8572
    // (BC1T_MM FCC0, brtarget:$offset) - 88
8573
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8574
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8575
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8576
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8577
    // (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 92
8578
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8579
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
8580
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8581
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
8582
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8583
    // (BGEZAL ZERO, brtarget:$offset) - 97
8584
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
8585
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8586
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8587
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8588
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8589
    // (BGEZAL_MM ZERO, brtarget_mm:$offset) - 102
8590
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
8591
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8592
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8593
    // (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset) - 105
8594
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
8595
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
8596
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8597
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
8598
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8599
    // (BREAK 0, 0) - 110
8600
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8601
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8602
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8603
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8604
    // (BREAK uimm10:$imm, 0) - 114
8605
0
    {AliasPatternCond::K_Ignore, 0},
8606
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8607
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8608
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8609
    // (BREAK_MM 0, 0) - 118
8610
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8611
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8612
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8613
    // (BREAK_MM uimm10:$imm, 0) - 121
8614
0
    {AliasPatternCond::K_Ignore, 0},
8615
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
8616
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8617
    // (C_EQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 124
8618
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8619
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8620
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8621
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8622
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8623
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8624
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8625
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8626
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8627
    // (C_EQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 133
8628
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8629
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8630
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8631
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8632
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8633
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8634
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8635
    // (C_EQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 140
8636
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8637
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8638
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8639
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8640
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8641
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8642
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8643
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8644
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8645
    // (C_EQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 149
8646
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8647
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8648
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8649
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8650
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8651
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8652
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8653
    // (C_EQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 156
8654
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8655
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8656
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8657
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8658
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8659
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8660
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8661
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8662
    // (C_EQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 164
8663
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8664
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8665
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8666
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8667
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8668
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8669
    // (C_F_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 170
8670
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8671
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8672
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8673
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8674
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8675
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8676
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8677
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8678
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8679
    // (C_F_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 179
8680
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8681
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8682
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8683
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8684
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8685
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8686
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8687
    // (C_F_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 186
8688
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8689
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8690
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8691
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8692
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8693
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8694
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8695
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8696
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8697
    // (C_F_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 195
8698
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8699
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8700
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8701
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8702
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8703
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8704
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8705
    // (C_F_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 202
8706
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8707
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8708
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8709
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8710
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8711
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8712
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8713
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8714
    // (C_F_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 210
8715
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8716
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8717
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8718
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8719
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8720
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8721
    // (C_LE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 216
8722
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8723
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8724
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8725
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8726
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8727
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8728
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8729
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8730
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8731
    // (C_LE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 225
8732
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8733
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8734
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8735
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8736
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8737
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8738
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8739
    // (C_LE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 232
8740
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8741
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8742
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8743
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8744
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8745
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8746
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8747
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8748
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8749
    // (C_LE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 241
8750
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8751
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8752
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8753
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8754
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8755
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8756
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8757
    // (C_LE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 248
8758
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8759
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8760
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8761
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8762
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8763
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8764
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8765
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8766
    // (C_LE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 256
8767
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8768
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8769
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8770
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8771
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8772
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8773
    // (C_LT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 262
8774
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8775
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8776
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8777
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8778
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8779
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8780
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8781
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8782
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8783
    // (C_LT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 271
8784
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8785
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8786
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8787
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8788
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8789
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8790
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8791
    // (C_LT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 278
8792
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8793
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8794
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8795
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8796
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8797
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8798
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8799
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8800
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8801
    // (C_LT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 287
8802
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8803
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8804
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8805
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8806
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8807
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8808
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8809
    // (C_LT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 294
8810
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8811
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8812
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8813
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8814
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8815
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8816
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8817
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8818
    // (C_LT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 302
8819
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8820
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8821
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8822
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8823
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8824
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8825
    // (C_NGE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 308
8826
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8827
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8828
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8829
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8830
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8831
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8832
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8833
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8834
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8835
    // (C_NGE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 317
8836
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8837
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8838
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8839
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8840
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8841
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8842
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8843
    // (C_NGE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 324
8844
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8845
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8846
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8847
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8848
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8849
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8850
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8851
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8852
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8853
    // (C_NGE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 333
8854
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8855
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8856
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8857
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8858
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8859
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8860
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8861
    // (C_NGE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 340
8862
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8863
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8864
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8865
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8866
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8867
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8868
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8869
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8870
    // (C_NGE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 348
8871
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8872
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8873
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8874
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8875
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8876
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8877
    // (C_NGLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 354
8878
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8879
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8880
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8881
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8882
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8883
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8884
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8885
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8886
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8887
    // (C_NGLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 363
8888
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8889
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8890
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8891
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8892
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8893
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8894
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8895
    // (C_NGLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 370
8896
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8897
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8898
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8899
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8900
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8901
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8902
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8903
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8904
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8905
    // (C_NGLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 379
8906
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8907
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8908
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8909
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8910
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8911
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8912
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8913
    // (C_NGLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 386
8914
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8915
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8916
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8917
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8918
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8919
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8920
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8921
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8922
    // (C_NGLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 394
8923
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8924
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8925
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8926
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8927
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8928
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8929
    // (C_NGL_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 400
8930
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8931
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8932
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8933
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8934
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8935
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8936
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8937
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8938
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8939
    // (C_NGL_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 409
8940
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8941
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8942
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8943
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8944
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8945
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8946
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8947
    // (C_NGL_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 416
8948
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8949
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8950
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8951
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8952
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8953
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8954
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8955
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8956
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8957
    // (C_NGL_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 425
8958
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8959
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8960
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
8961
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8962
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
8963
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8964
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8965
    // (C_NGL_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 432
8966
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8967
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8968
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8969
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8970
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8971
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8972
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8973
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8974
    // (C_NGL_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 440
8975
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8976
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8977
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
8978
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8979
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8980
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8981
    // (C_NGT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 446
8982
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8983
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8984
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8985
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
8986
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8987
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8988
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
8989
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8990
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
8991
    // (C_NGT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 455
8992
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
8993
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8994
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
8995
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
8996
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
8997
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
8998
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
8999
    // (C_NGT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 462
9000
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9001
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9002
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9003
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9004
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9005
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9006
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9007
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9008
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9009
    // (C_NGT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 471
9010
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9011
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9012
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9013
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9014
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9015
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9016
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9017
    // (C_NGT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 478
9018
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9019
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9020
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9021
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9022
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9023
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9024
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9025
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9026
    // (C_NGT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 486
9027
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9028
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9029
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9030
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9031
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9032
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9033
    // (C_OLE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 492
9034
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9035
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9036
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9037
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9038
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9039
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9040
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9041
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9042
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9043
    // (C_OLE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 501
9044
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9045
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9046
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9047
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9048
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9049
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9050
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9051
    // (C_OLE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 508
9052
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9053
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9054
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9055
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9056
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9057
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9058
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9059
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9060
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9061
    // (C_OLE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 517
9062
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9063
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9064
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9065
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9066
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9067
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9068
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9069
    // (C_OLE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 524
9070
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9071
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9072
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9073
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9074
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9075
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9076
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9077
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9078
    // (C_OLE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 532
9079
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9080
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9081
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9082
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9083
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9084
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9085
    // (C_OLT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 538
9086
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9087
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9088
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9089
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9090
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9091
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9092
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9093
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9094
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9095
    // (C_OLT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 547
9096
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9097
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9098
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9099
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9100
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9101
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9102
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9103
    // (C_OLT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 554
9104
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9105
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9106
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9107
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9108
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9109
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9110
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9111
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9112
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9113
    // (C_OLT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 563
9114
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9115
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9116
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9117
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9118
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9119
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9120
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9121
    // (C_OLT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 570
9122
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9123
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9124
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9125
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9126
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9127
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9128
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9129
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9130
    // (C_OLT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 578
9131
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9132
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9133
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9134
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9135
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9136
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9137
    // (C_SEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 584
9138
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9139
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9140
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9141
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9142
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9143
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9144
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9145
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9146
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9147
    // (C_SEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 593
9148
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9149
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9150
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9151
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9152
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9153
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9154
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9155
    // (C_SEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 600
9156
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9157
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9158
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9159
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9160
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9161
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9162
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9163
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9164
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9165
    // (C_SEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 609
9166
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9167
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9168
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9169
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9170
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9171
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9172
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9173
    // (C_SEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 616
9174
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9175
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9176
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9177
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9178
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9179
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9180
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9181
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9182
    // (C_SEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 624
9183
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9184
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9185
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9186
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9187
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9188
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9189
    // (C_SF_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 630
9190
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9191
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9192
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9193
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9194
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9195
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9196
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9197
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9198
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9199
    // (C_SF_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 639
9200
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9201
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9202
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9203
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9204
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9205
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9206
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9207
    // (C_SF_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 646
9208
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9209
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9210
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9211
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9212
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9213
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9214
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9215
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9216
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9217
    // (C_SF_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 655
9218
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9219
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9220
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9221
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9222
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9223
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9224
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9225
    // (C_SF_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 662
9226
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9227
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9228
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9229
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9230
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9231
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9232
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9233
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9234
    // (C_SF_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 670
9235
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9236
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9237
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9238
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9239
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9240
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9241
    // (C_UEQ_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 676
9242
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9243
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9244
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9245
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9246
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9247
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9248
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9249
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9250
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9251
    // (C_UEQ_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 685
9252
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9253
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9254
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9255
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9256
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9257
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9258
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9259
    // (C_UEQ_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 692
9260
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9261
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9262
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9263
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9264
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9265
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9266
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9267
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9268
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9269
    // (C_UEQ_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 701
9270
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9271
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9272
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9273
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9274
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9275
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9276
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9277
    // (C_UEQ_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 708
9278
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9279
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9280
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9281
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9282
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9283
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9284
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9285
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9286
    // (C_UEQ_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 716
9287
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9288
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9289
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9290
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9291
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9292
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9293
    // (C_ULE_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 722
9294
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9295
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9296
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9297
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9298
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9299
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9300
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9301
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9302
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9303
    // (C_ULE_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 731
9304
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9305
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9306
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9307
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9308
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9309
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9310
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9311
    // (C_ULE_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 738
9312
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9313
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9314
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9315
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9316
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9317
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9318
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9319
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9320
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9321
    // (C_ULE_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 747
9322
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9323
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9324
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9325
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9326
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9327
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9328
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9329
    // (C_ULE_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 754
9330
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9331
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9332
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9333
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9334
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9335
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9336
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9337
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9338
    // (C_ULE_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 762
9339
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9340
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9341
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9342
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9343
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9344
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9345
    // (C_ULT_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 768
9346
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9347
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9348
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9349
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9350
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9351
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9352
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9353
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9354
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9355
    // (C_ULT_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 777
9356
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9357
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9358
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9359
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9360
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9361
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9362
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9363
    // (C_ULT_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 784
9364
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9365
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9366
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9367
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9368
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9369
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9370
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9371
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9372
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9373
    // (C_ULT_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 793
9374
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9375
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9376
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9377
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9378
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9379
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9380
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9381
    // (C_ULT_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 800
9382
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9383
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9384
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9385
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9386
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9387
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9388
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9389
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9390
    // (C_ULT_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 808
9391
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9392
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9393
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9394
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9395
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9396
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9397
    // (C_UN_D32 FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 814
9398
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9399
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9400
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9401
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9402
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9403
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9404
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9405
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9406
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9407
    // (C_UN_D32_MM FCC0, AFGR64Opnd:$fs, AFGR64Opnd:$ft) - 823
9408
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9409
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9410
0
    {AliasPatternCond::K_RegClass, Mips::AFGR64RegClassID},
9411
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9412
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureFP64Bit},
9413
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9414
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9415
    // (C_UN_D64 FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 830
9416
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9417
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9418
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9419
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9420
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9421
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9422
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9423
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9424
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9425
    // (C_UN_D64_MM FCC0, FGR64Opnd:$fs, FGR64Opnd:$ft) - 839
9426
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9427
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9428
0
    {AliasPatternCond::K_RegClass, Mips::FGR64RegClassID},
9429
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9430
0
    {AliasPatternCond::K_Feature, Mips::FeatureFP64Bit},
9431
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9432
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9433
    // (C_UN_S FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 846
9434
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9435
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9436
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9437
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9438
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9439
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9440
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9441
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9442
    // (C_UN_S_MM FCC0, FGR32Opnd:$fs, FGR32Opnd:$ft) - 854
9443
0
    {AliasPatternCond::K_Reg, Mips::FCC0},
9444
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9445
0
    {AliasPatternCond::K_RegClass, Mips::FGR32RegClassID},
9446
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9447
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9448
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureSoftFloat},
9449
    // (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 860
9450
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9451
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9452
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9453
0
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
9454
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9455
    // (DI ZERO) - 865
9456
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9457
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9458
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r2},
9459
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9460
    // (DIV GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 869
9461
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9462
0
    {AliasPatternCond::K_TiedReg, 0},
9463
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9464
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9465
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9466
    // (DIVU GPR32Opnd:$rs, GPR32Opnd:$rs, GPR32Opnd:$rt) - 874
9467
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9468
0
    {AliasPatternCond::K_TiedReg, 0},
9469
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9470
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9471
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9472
    // (DI_MM ZERO) - 879
9473
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9474
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9475
    // (DI_MMR6 ZERO) - 881
9476
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9477
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9478
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9479
    // (DMT ZERO) - 884
9480
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9481
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
9482
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9483
    // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 887
9484
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9485
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9486
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9487
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9488
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
9489
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9490
    // (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 893
9491
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9492
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9493
0
    {AliasPatternCond::K_TiedReg, 0},
9494
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9495
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
9496
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9497
    // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs) - 899
9498
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9499
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9500
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9501
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9502
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
9503
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9504
    // (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt) - 905
9505
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9506
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9507
0
    {AliasPatternCond::K_TiedReg, 0},
9508
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9509
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips3},
9510
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9511
    // (DVPE ZERO) - 911
9512
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9513
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
9514
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9515
    // (EI ZERO) - 914
9516
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9517
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9518
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r2},
9519
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9520
    // (EI_MM ZERO) - 918
9521
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9522
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9523
    // (EI_MMR6 ZERO) - 920
9524
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9525
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9526
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9527
    // (EMT ZERO) - 923
9528
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9529
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
9530
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9531
    // (EVPE ZERO) - 926
9532
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9533
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
9534
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9535
    // (HYPCALL 0) - 929
9536
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9537
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9538
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r5},
9539
0
    {AliasPatternCond::K_Feature, Mips::FeatureVirt},
9540
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9541
    // (HYPCALL_MM 0) - 934
9542
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9543
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9544
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r5},
9545
0
    {AliasPatternCond::K_Feature, Mips::FeatureVirt},
9546
    // (JALR ZERO, GPR32Opnd:$rs) - 938
9547
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9548
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9549
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9550
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
9551
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9552
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9553
    // (JALR64 ZERO_64, GPR64Opnd:$rs) - 944
9554
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9555
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9556
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9557
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips64r6},
9558
    // (JALRC_HB_MMR6 RA, GPR32Opnd:$rs) - 948
9559
0
    {AliasPatternCond::K_Reg, Mips::RA},
9560
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9561
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9562
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9563
    // (JALRC_MMR6 RA, GPR32Opnd:$rs) - 952
9564
0
    {AliasPatternCond::K_Reg, Mips::RA},
9565
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9566
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9567
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9568
    // (JALR_HB RA, GPR32Opnd:$rs) - 956
9569
0
    {AliasPatternCond::K_Reg, Mips::RA},
9570
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9571
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9572
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32},
9573
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9574
    // (JALR_HB64 RA_64, GPR64Opnd:$rs) - 961
9575
0
    {AliasPatternCond::K_Reg, Mips::RA_64},
9576
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9577
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9578
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips64},
9579
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9580
    // (JIALC GPR32Opnd:$rs, 0) - 966
9581
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9582
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9583
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9584
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
9585
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9586
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9587
    // (JIALC64 GPR64Opnd:$rs, 0) - 972
9588
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9589
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9590
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9591
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips64r6},
9592
    // (JIC GPR32Opnd:$rs, 0) - 976
9593
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9594
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9595
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9596
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
9597
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9598
    // (JIC64 GPR64Opnd:$rs, 0) - 981
9599
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9600
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9601
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9602
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips64r6},
9603
    // (MOVE16_MM ZERO, ZERO) - 985
9604
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9605
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9606
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9607
    // (Move32R16 ZERO, S0) - 988
9608
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9609
0
    {AliasPatternCond::K_Reg, Mips::S0},
9610
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips16},
9611
    // (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO) - 991
9612
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9613
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9614
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9615
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9616
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureGP64Bit},
9617
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9618
    // (OR64 GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64) - 997
9619
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9620
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9621
0
    {AliasPatternCond::K_Reg, Mips::ZERO_64},
9622
0
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
9623
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9624
    // (RDHWR GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1002
9625
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9626
0
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
9627
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9628
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9629
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9630
    // (RDHWR64 GPR64Opnd:$rt, HWRegsOpnd:$rs, 0) - 1007
9631
0
    {AliasPatternCond::K_RegClass, Mips::GPR64RegClassID},
9632
0
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
9633
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9634
0
    {AliasPatternCond::K_Feature, Mips::FeatureGP64Bit},
9635
    // (RDHWR_MM GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1011
9636
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9637
0
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
9638
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9639
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9640
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9641
    // (RDHWR_MMR6 GPR32Opnd:$rt, HWRegsOpnd:$rs, 0) - 1016
9642
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9643
0
    {AliasPatternCond::K_RegClass, Mips::HWRegsRegClassID},
9644
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9645
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9646
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9647
    // (SDBBP 0) - 1021
9648
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9649
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9650
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32},
9651
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9652
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips64r6},
9653
    // (SDBBP_MMR6 0) - 1026
9654
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9655
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9656
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9657
    // (SDBBP_R6 0) - 1029
9658
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9659
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9660
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9661
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9662
    // (SIGRIE 0) - 1033
9663
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9664
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9665
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9666
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9667
    // (SIGRIE_MMR6 0) - 1037
9668
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9669
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9670
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9671
    // (SLL ZERO, ZERO, 0) - 1040
9672
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9673
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9674
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9675
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9676
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9677
    // (SLL_MM ZERO, ZERO, 0) - 1045
9678
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9679
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9680
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9681
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9682
    // (SLL_MMR6 ZERO, ZERO, 0) - 1049
9683
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9684
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9685
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9686
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9687
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9688
    // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1054
9689
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9690
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9691
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9692
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9693
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9694
    // (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1059
9695
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9696
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9697
0
    {AliasPatternCond::K_TiedReg, 0},
9698
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9699
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9700
    // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1064
9701
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9702
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9703
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9704
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9705
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9706
    // (SUBU_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1069
9707
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9708
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9709
0
    {AliasPatternCond::K_TiedReg, 0},
9710
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9711
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9712
    // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1074
9713
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9714
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9715
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9716
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9717
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9718
    // (SUB_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1079
9719
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9720
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9721
0
    {AliasPatternCond::K_TiedReg, 0},
9722
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9723
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9724
    // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1084
9725
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9726
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9727
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9728
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9729
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9730
    // (SUB_MMR6 GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1089
9731
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9732
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9733
0
    {AliasPatternCond::K_TiedReg, 0},
9734
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9735
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9736
    // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1094
9737
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9738
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9739
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9740
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9741
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9742
    // (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1099
9743
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9744
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9745
0
    {AliasPatternCond::K_TiedReg, 0},
9746
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9747
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9748
    // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs) - 1104
9749
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9750
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9751
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9752
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9753
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9754
    // (SUBu_MM GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt) - 1109
9755
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9756
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9757
0
    {AliasPatternCond::K_TiedReg, 0},
9758
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9759
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips32r6},
9760
    // (SWSP_MM GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset) - 1114
9761
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9762
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9763
    // (SYNC 0) - 1116
9764
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9765
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9766
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9767
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9768
    // (SYNC_MM 0) - 1120
9769
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9770
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9771
    // (SYNC_MMR6 0) - 1122
9772
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9773
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9774
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips32r6},
9775
    // (SYSCALL 0) - 1125
9776
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9777
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9778
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9779
    // (SYSCALL_MM 0) - 1128
9780
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9781
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9782
    // (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1130
9783
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9784
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9785
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9786
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9787
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9788
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9789
    // (TEQ_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1136
9790
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9791
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9792
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9793
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9794
    // (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1140
9795
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9796
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9797
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9798
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9799
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9800
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9801
    // (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1146
9802
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9803
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9804
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9805
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9806
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9807
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9808
    // (TGEU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1152
9809
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9810
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9811
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9812
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9813
    // (TGE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1156
9814
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9815
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9816
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9817
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9818
    // (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1160
9819
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9820
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9821
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9822
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9823
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9824
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9825
    // (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1166
9826
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9827
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9828
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9829
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9830
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9831
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9832
    // (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1172
9833
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9834
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9835
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9836
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9837
    // (TLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1176
9838
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9839
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9840
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9841
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9842
    // (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1180
9843
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9844
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9845
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9846
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMips16},
9847
0
    {AliasPatternCond::K_Feature, Mips::FeatureMips2},
9848
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9849
    // (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0) - 1186
9850
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9851
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9852
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9853
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9854
    // (WAIT_MM 0) - 1190
9855
0
    {AliasPatternCond::K_Imm, uint32_t(0)},
9856
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9857
    // (WRDSP GPR32Opnd:$rt, 31) - 1192
9858
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9859
0
    {AliasPatternCond::K_Imm, uint32_t(31)},
9860
0
    {AliasPatternCond::K_Feature, Mips::FeatureDSP},
9861
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9862
    // (WRDSP_MM GPR32Opnd:$rt, 31) - 1196
9863
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9864
0
    {AliasPatternCond::K_Imm, uint32_t(31)},
9865
0
    {AliasPatternCond::K_Feature, Mips::FeatureDSP},
9866
0
    {AliasPatternCond::K_Feature, Mips::FeatureMicroMips},
9867
    // (YIELD ZERO, GPR32Opnd:$rs) - 1200
9868
0
    {AliasPatternCond::K_Reg, Mips::ZERO},
9869
0
    {AliasPatternCond::K_RegClass, Mips::GPR32RegClassID},
9870
0
    {AliasPatternCond::K_Feature, Mips::FeatureMT},
9871
0
    {AliasPatternCond::K_NegFeature, Mips::FeatureMicroMips},
9872
0
  };
9873
9874
0
  static const char AsmStrings[] =
9875
0
    /* 0 */ "mftacx $\x01\0"
9876
0
    /* 10 */ "mftc0 $\x01, $\x02\0"
9877
0
    /* 23 */ "mfthi $\x01\0"
9878
0
    /* 32 */ "mftlo $\x01\0"
9879
0
    /* 41 */ "mttacx $\x02\0"
9880
0
    /* 51 */ "mttc0 $\x02, $\x01\0"
9881
0
    /* 64 */ "mtthi $\x02\0"
9882
0
    /* 73 */ "mttlo $\x02\0"
9883
0
    /* 82 */ "nor $\x01, $\x03\0"
9884
0
    /* 93 */ "slt $\x01, $\x03\0"
9885
0
    /* 104 */ "sltu $\x01, $\x03\0"
9886
0
    /* 116 */ "lapc $\x01, $\x02\0"
9887
0
    /* 128 */ "move $\x01, $\x02\0"
9888
0
    /* 140 */ "bc1f $\xFF\x02\x01\0"
9889
0
    /* 150 */ "bc1fl $\xFF\x02\x01\0"
9890
0
    /* 161 */ "bc1t $\xFF\x02\x01\0"
9891
0
    /* 171 */ "bc1tl $\xFF\x02\x01\0"
9892
0
    /* 182 */ "beqzl $\x01, $\xFF\x03\x01\0"
9893
0
    /* 197 */ "bal $\xFF\x02\x01\0"
9894
0
    /* 206 */ "bnezl $\x01, $\xFF\x03\x01\0"
9895
0
    /* 221 */ "break\0"
9896
0
    /* 227 */ "break $\xFF\x01\x02\0"
9897
0
    /* 238 */ "c.eq.d $\x02, $\x03\0"
9898
0
    /* 252 */ "c.eq.s $\x02, $\x03\0"
9899
0
    /* 266 */ "c.f.d $\x02, $\x03\0"
9900
0
    /* 279 */ "c.f.s $\x02, $\x03\0"
9901
0
    /* 292 */ "c.le.d $\x02, $\x03\0"
9902
0
    /* 306 */ "c.le.s $\x02, $\x03\0"
9903
0
    /* 320 */ "c.lt.d $\x02, $\x03\0"
9904
0
    /* 334 */ "c.lt.s $\x02, $\x03\0"
9905
0
    /* 348 */ "c.nge.d $\x02, $\x03\0"
9906
0
    /* 363 */ "c.nge.s $\x02, $\x03\0"
9907
0
    /* 378 */ "c.ngle.d $\x02, $\x03\0"
9908
0
    /* 394 */ "c.ngle.s $\x02, $\x03\0"
9909
0
    /* 410 */ "c.ngl.d $\x02, $\x03\0"
9910
0
    /* 425 */ "c.ngl.s $\x02, $\x03\0"
9911
0
    /* 440 */ "c.ngt.d $\x02, $\x03\0"
9912
0
    /* 455 */ "c.ngt.s $\x02, $\x03\0"
9913
0
    /* 470 */ "c.ole.d $\x02, $\x03\0"
9914
0
    /* 485 */ "c.ole.s $\x02, $\x03\0"
9915
0
    /* 500 */ "c.olt.d $\x02, $\x03\0"
9916
0
    /* 515 */ "c.olt.s $\x02, $\x03\0"
9917
0
    /* 530 */ "c.seq.d $\x02, $\x03\0"
9918
0
    /* 545 */ "c.seq.s $\x02, $\x03\0"
9919
0
    /* 560 */ "c.sf.d $\x02, $\x03\0"
9920
0
    /* 574 */ "c.sf.s $\x02, $\x03\0"
9921
0
    /* 588 */ "c.ueq.d $\x02, $\x03\0"
9922
0
    /* 603 */ "c.ueq.s $\x02, $\x03\0"
9923
0
    /* 618 */ "c.ule.d $\x02, $\x03\0"
9924
0
    /* 633 */ "c.ule.s $\x02, $\x03\0"
9925
0
    /* 648 */ "c.ult.d $\x02, $\x03\0"
9926
0
    /* 663 */ "c.ult.s $\x02, $\x03\0"
9927
0
    /* 678 */ "c.un.d $\x02, $\x03\0"
9928
0
    /* 692 */ "c.un.s $\x02, $\x03\0"
9929
0
    /* 706 */ "di\0"
9930
0
    /* 709 */ "div $\x01, $\x03\0"
9931
0
    /* 720 */ "divu $\x01, $\x03\0"
9932
0
    /* 732 */ "dmt\0"
9933
0
    /* 736 */ "dneg $\x01, $\x03\0"
9934
0
    /* 748 */ "dneg $\x01\0"
9935
0
    /* 756 */ "dnegu $\x01, $\x03\0"
9936
0
    /* 769 */ "dnegu $\x01\0"
9937
0
    /* 778 */ "dvpe\0"
9938
0
    /* 783 */ "ei\0"
9939
0
    /* 786 */ "emt\0"
9940
0
    /* 790 */ "evpe\0"
9941
0
    /* 795 */ "hypcall\0"
9942
0
    /* 803 */ "jr $\x02\0"
9943
0
    /* 809 */ "jalrc.hb $\x02\0"
9944
0
    /* 821 */ "jalrc $\x02\0"
9945
0
    /* 830 */ "jalr.hb $\x02\0"
9946
0
    /* 841 */ "jalrc $\x01\0"
9947
0
    /* 850 */ "jrc $\x01\0"
9948
0
    /* 857 */ "nop\0"
9949
0
    /* 861 */ "rdhwr $\x01, $\x02\0"
9950
0
    /* 874 */ "sdbbp\0"
9951
0
    /* 880 */ "sigrie\0"
9952
0
    /* 887 */ "neg $\x01, $\x03\0"
9953
0
    /* 898 */ "neg $\x01\0"
9954
0
    /* 905 */ "negu $\x01, $\x03\0"
9955
0
    /* 917 */ "negu $\x01\0"
9956
0
    /* 925 */ "sw $\x01, $\xFF\x02\x03\0"
9957
0
    /* 937 */ "sync\0"
9958
0
    /* 942 */ "syscall\0"
9959
0
    /* 950 */ "teq $\x01, $\x02\0"
9960
0
    /* 961 */ "tge $\x01, $\x02\0"
9961
0
    /* 972 */ "tgeu $\x01, $\x02\0"
9962
0
    /* 984 */ "tlt $\x01, $\x02\0"
9963
0
    /* 995 */ "tltu $\x01, $\x02\0"
9964
0
    /* 1007 */ "tne $\x01, $\x02\0"
9965
0
    /* 1018 */ "wait\0"
9966
0
    /* 1023 */ "wrdsp $\x01\0"
9967
0
    /* 1032 */ "yield $\x02\0"
9968
0
  ;
9969
9970
0
#ifndef NDEBUG
9971
0
  static struct SortCheck {
9972
0
    SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
9973
0
      assert(std::is_sorted(
9974
0
                 OpToPatterns.begin(), OpToPatterns.end(),
9975
0
                 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
9976
0
                   return L.Opcode < R.Opcode;
9977
0
                 }) &&
9978
0
             "tablegen failed to sort opcode patterns");
9979
0
    }
9980
0
  } sortCheckVar(OpToPatterns);
9981
0
#endif
9982
9983
0
  AliasMatchingData M {
9984
0
    ArrayRef(OpToPatterns),
9985
0
    ArrayRef(Patterns),
9986
0
    ArrayRef(Conds),
9987
0
    StringRef(AsmStrings, std::size(AsmStrings)),
9988
0
    nullptr,
9989
0
  };
9990
0
  const char *AsmString = matchAliasPatterns(MI, &STI, M);
9991
0
  if (!AsmString) return false;
9992
9993
0
  unsigned I = 0;
9994
0
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
9995
0
         AsmString[I] != '$' && AsmString[I] != '\0')
9996
0
    ++I;
9997
0
  OS << '\t' << StringRef(AsmString, I);
9998
0
  if (AsmString[I] != '\0') {
9999
0
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
10000
0
      OS << '\t';
10001
0
      ++I;
10002
0
    }
10003
0
    do {
10004
0
      if (AsmString[I] == '$') {
10005
0
        ++I;
10006
0
        if (AsmString[I] == (char)0xff) {
10007
0
          ++I;
10008
0
          int OpIdx = AsmString[I++] - 1;
10009
0
          int PrintMethodIdx = AsmString[I++] - 1;
10010
0
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS);
10011
0
        } else
10012
0
          printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
10013
0
      } else {
10014
0
        OS << AsmString[I++];
10015
0
      }
10016
0
    } while (AsmString[I] != '\0');
10017
0
  }
10018
10019
0
  return true;
10020
0
}
10021
10022
void MipsInstPrinter::printCustomAliasOperand(
10023
         const MCInst *MI, uint64_t Address, unsigned OpIdx,
10024
         unsigned PrintMethodIdx,
10025
         const MCSubtargetInfo &STI,
10026
0
         raw_ostream &OS) {
10027
0
  switch (PrintMethodIdx) {
10028
0
  default:
10029
0
    llvm_unreachable("Unknown PrintMethod kind");
10030
0
    break;
10031
0
  case 0:
10032
0
    printBranchOperand(MI, Address, OpIdx, STI, OS);
10033
0
    break;
10034
0
  case 1:
10035
0
    printUImm<10>(MI, OpIdx, STI, OS);
10036
0
    break;
10037
0
  case 2:
10038
0
    printMemOperand(MI, OpIdx, STI, OS);
10039
0
    break;
10040
0
  }
10041
0
}
10042
10043
#endif // PRINT_ALIAS_INSTR