/src/build/lib/Target/Mips/MipsGenCallingConv.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Calling Convention Implementation Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifndef GET_CC_REGISTER_LISTS |
10 | | |
11 | | static bool CC_Mips(unsigned ValNo, MVT ValVT, |
12 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
13 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
14 | | static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT, |
15 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
16 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
17 | | static bool CC_MipsN(unsigned ValNo, MVT ValVT, |
18 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
19 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
20 | | static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT, |
21 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
22 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
23 | | static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT, |
24 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
25 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
26 | | static bool CC_MipsN_VarArg(unsigned ValNo, MVT ValVT, |
27 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
28 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
29 | | static bool CC_MipsO32(unsigned ValNo, MVT ValVT, |
30 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
31 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
32 | | static bool CC_MipsO32_FP(unsigned ValNo, MVT ValVT, |
33 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
34 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
35 | | static bool CC_MipsO32_FastCC(unsigned ValNo, MVT ValVT, |
36 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
37 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
38 | | static bool CC_Mips_ByVal(unsigned ValNo, MVT ValVT, |
39 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
40 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
41 | | static bool CC_Mips_FastCC(unsigned ValNo, MVT ValVT, |
42 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
43 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
44 | | static bool CC_Mips_FixedArg(unsigned ValNo, MVT ValVT, |
45 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
46 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
47 | | static bool CC_Mips_VarArg(unsigned ValNo, MVT ValVT, |
48 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
49 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
50 | | static bool RetCC_F128(unsigned ValNo, MVT ValVT, |
51 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
52 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
53 | | static bool RetCC_F128HardFloat(unsigned ValNo, MVT ValVT, |
54 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
55 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
56 | | static bool RetCC_F128SoftFloat(unsigned ValNo, MVT ValVT, |
57 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
58 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
59 | | static bool RetCC_Mips(unsigned ValNo, MVT ValVT, |
60 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
61 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
62 | | static bool RetCC_MipsN(unsigned ValNo, MVT ValVT, |
63 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
64 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
65 | | static bool RetCC_MipsO32(unsigned ValNo, MVT ValVT, |
66 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
67 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
68 | | |
69 | | |
70 | | static bool CC_Mips(unsigned ValNo, MVT ValVT, |
71 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
72 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
73 | |
|
74 | 0 | if (State.isVarArg()) { |
75 | 0 | if (!static_cast<MipsCCState *>(&State)->IsCallOperandFixed(ValNo)) { |
76 | 0 | if (!CC_Mips_VarArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
77 | 0 | return false; |
78 | 0 | } |
79 | 0 | } |
80 | | |
81 | 0 | if (!CC_Mips_FixedArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
82 | 0 | return false; |
83 | | |
84 | 0 | return true; // CC didn't match. |
85 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_Mips(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_Mips(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
86 | | |
87 | | |
88 | | static bool CC_Mips16RetHelper(unsigned ValNo, MVT ValVT, |
89 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
90 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
91 | |
|
92 | 0 | if (ArgFlags.isByVal()) { |
93 | 0 | if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
94 | 0 | return false; |
95 | 0 | } |
96 | | |
97 | 0 | if (LocVT == MVT::i32) { |
98 | 0 | static const MCPhysReg RegList1[] = { |
99 | 0 | Mips::V0, Mips::V1, Mips::A0, Mips::A1 |
100 | 0 | }; |
101 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
102 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
103 | 0 | return false; |
104 | 0 | } |
105 | 0 | } |
106 | | |
107 | 0 | return true; // CC didn't match. |
108 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_Mips16RetHelper(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_Mips16RetHelper(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
109 | | |
110 | | |
111 | | static bool CC_MipsN(unsigned ValNo, MVT ValVT, |
112 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
113 | 67 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
114 | | |
115 | 67 | if (LocVT == MVT::i8 || |
116 | 67 | LocVT == MVT::i16 || |
117 | 67 | LocVT == MVT::i32 || |
118 | 67 | LocVT == MVT::i64) { |
119 | 47 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { |
120 | 47 | if (ArgFlags.isInReg()) { |
121 | 0 | LocVT = MVT::i64; |
122 | 0 | if (ArgFlags.isSExt()) |
123 | 0 | LocInfo = CCValAssign::SExtUpper; |
124 | 0 | else if (ArgFlags.isZExt()) |
125 | 0 | LocInfo = CCValAssign::ZExtUpper; |
126 | 0 | else |
127 | 0 | LocInfo = CCValAssign::AExtUpper; |
128 | 0 | } |
129 | 47 | } |
130 | 47 | } |
131 | | |
132 | 67 | if (LocVT == MVT::i8 || |
133 | 67 | LocVT == MVT::i16 || |
134 | 67 | LocVT == MVT::i32) { |
135 | 43 | if (!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)) { |
136 | 43 | LocVT = MVT::i64; |
137 | 43 | if (ArgFlags.isSExt()) |
138 | 0 | LocInfo = CCValAssign::SExt; |
139 | 43 | else if (ArgFlags.isZExt()) |
140 | 0 | LocInfo = CCValAssign::ZExt; |
141 | 43 | else |
142 | 43 | LocInfo = CCValAssign::AExt; |
143 | 43 | } |
144 | 43 | } |
145 | | |
146 | 67 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
147 | 0 | if (LocVT == MVT::i32) { |
148 | 0 | if (!CC_MipsN_SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
149 | 0 | return false; |
150 | 0 | } |
151 | 0 | } |
152 | | |
153 | 67 | if (LocVT == MVT::i64) { |
154 | 47 | static const MCPhysReg RegList1[] = { |
155 | 47 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 |
156 | 47 | }; |
157 | 47 | static const MCPhysReg RegList2[] = { |
158 | 47 | Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 |
159 | 47 | }; |
160 | 47 | if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { |
161 | 47 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
162 | 47 | return false; |
163 | 47 | } |
164 | 47 | } |
165 | | |
166 | 20 | if (LocVT == MVT::f32) { |
167 | 3 | static const MCPhysReg RegList3[] = { |
168 | 3 | Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19 |
169 | 3 | }; |
170 | 3 | static const MCPhysReg RegList4[] = { |
171 | 3 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 |
172 | 3 | }; |
173 | 3 | if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { |
174 | 3 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
175 | 3 | return false; |
176 | 3 | } |
177 | 3 | } |
178 | | |
179 | 17 | if (LocVT == MVT::f64) { |
180 | 17 | static const MCPhysReg RegList5[] = { |
181 | 17 | Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 |
182 | 17 | }; |
183 | 17 | static const MCPhysReg RegList6[] = { |
184 | 17 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 |
185 | 17 | }; |
186 | 17 | if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { |
187 | 17 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
188 | 17 | return false; |
189 | 17 | } |
190 | 17 | } |
191 | | |
192 | 0 | if (LocVT == MVT::f32) { |
193 | 0 | int64_t Offset7 = State.AllocateStack(4, Align(8)); |
194 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
195 | 0 | return false; |
196 | 0 | } |
197 | | |
198 | 0 | if (LocVT == MVT::i64 || |
199 | 0 | LocVT == MVT::f64) { |
200 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(8)); |
201 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
202 | 0 | return false; |
203 | 0 | } |
204 | | |
205 | 0 | return true; // CC didn't match. |
206 | 0 | } MipsISelLowering.cpp:CC_MipsN(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 113 | 67 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 114 | | | 115 | 67 | if (LocVT == MVT::i8 || | 116 | 67 | LocVT == MVT::i16 || | 117 | 67 | LocVT == MVT::i32 || | 118 | 67 | LocVT == MVT::i64) { | 119 | 47 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { | 120 | 47 | if (ArgFlags.isInReg()) { | 121 | 0 | LocVT = MVT::i64; | 122 | 0 | if (ArgFlags.isSExt()) | 123 | 0 | LocInfo = CCValAssign::SExtUpper; | 124 | 0 | else if (ArgFlags.isZExt()) | 125 | 0 | LocInfo = CCValAssign::ZExtUpper; | 126 | 0 | else | 127 | 0 | LocInfo = CCValAssign::AExtUpper; | 128 | 0 | } | 129 | 47 | } | 130 | 47 | } | 131 | | | 132 | 67 | if (LocVT == MVT::i8 || | 133 | 67 | LocVT == MVT::i16 || | 134 | 67 | LocVT == MVT::i32) { | 135 | 43 | if (!static_cast<MipsCCState *>(&State)->WasOriginalArgFloat(ValNo)) { | 136 | 43 | LocVT = MVT::i64; | 137 | 43 | if (ArgFlags.isSExt()) | 138 | 0 | LocInfo = CCValAssign::SExt; | 139 | 43 | else if (ArgFlags.isZExt()) | 140 | 0 | LocInfo = CCValAssign::ZExt; | 141 | 43 | else | 142 | 43 | LocInfo = CCValAssign::AExt; | 143 | 43 | } | 144 | 43 | } | 145 | | | 146 | 67 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { | 147 | 0 | if (LocVT == MVT::i32) { | 148 | 0 | if (!CC_MipsN_SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 149 | 0 | return false; | 150 | 0 | } | 151 | 0 | } | 152 | | | 153 | 67 | if (LocVT == MVT::i64) { | 154 | 47 | static const MCPhysReg RegList1[] = { | 155 | 47 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 | 156 | 47 | }; | 157 | 47 | static const MCPhysReg RegList2[] = { | 158 | 47 | Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 | 159 | 47 | }; | 160 | 47 | if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { | 161 | 47 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 162 | 47 | return false; | 163 | 47 | } | 164 | 47 | } | 165 | | | 166 | 20 | if (LocVT == MVT::f32) { | 167 | 3 | static const MCPhysReg RegList3[] = { | 168 | 3 | Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19 | 169 | 3 | }; | 170 | 3 | static const MCPhysReg RegList4[] = { | 171 | 3 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 | 172 | 3 | }; | 173 | 3 | if (unsigned Reg = State.AllocateReg(RegList3, RegList4)) { | 174 | 3 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 175 | 3 | return false; | 176 | 3 | } | 177 | 3 | } | 178 | | | 179 | 17 | if (LocVT == MVT::f64) { | 180 | 17 | static const MCPhysReg RegList5[] = { | 181 | 17 | Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 | 182 | 17 | }; | 183 | 17 | static const MCPhysReg RegList6[] = { | 184 | 17 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 | 185 | 17 | }; | 186 | 17 | if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { | 187 | 17 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 188 | 17 | return false; | 189 | 17 | } | 190 | 17 | } | 191 | | | 192 | 0 | if (LocVT == MVT::f32) { | 193 | 0 | int64_t Offset7 = State.AllocateStack(4, Align(8)); | 194 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); | 195 | 0 | return false; | 196 | 0 | } | 197 | | | 198 | 0 | if (LocVT == MVT::i64 || | 199 | 0 | LocVT == MVT::f64) { | 200 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(8)); | 201 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); | 202 | 0 | return false; | 203 | 0 | } | 204 | | | 205 | 0 | return true; // CC didn't match. | 206 | 0 | } |
Unexecuted instantiation: MipsFastISel.cpp:CC_MipsN(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
207 | | |
208 | | |
209 | | static bool CC_MipsN_FastCC(unsigned ValNo, MVT ValVT, |
210 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
211 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
212 | |
|
213 | 0 | if (LocVT == MVT::i64) { |
214 | 0 | static const MCPhysReg RegList1[] = { |
215 | 0 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::T8_64, Mips::V1_64 |
216 | 0 | }; |
217 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
218 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
219 | 0 | return false; |
220 | 0 | } |
221 | 0 | } |
222 | | |
223 | 0 | if (LocVT == MVT::f64) { |
224 | 0 | static const MCPhysReg RegList2[] = { |
225 | 0 | Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 |
226 | 0 | }; |
227 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
228 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
229 | 0 | return false; |
230 | 0 | } |
231 | 0 | } |
232 | | |
233 | 0 | if (LocVT == MVT::i64 || |
234 | 0 | LocVT == MVT::f64) { |
235 | 0 | int64_t Offset3 = State.AllocateStack(8, Align(8)); |
236 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
237 | 0 | return false; |
238 | 0 | } |
239 | | |
240 | 0 | return true; // CC didn't match. |
241 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_MipsN_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_MipsN_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
242 | | |
243 | | |
244 | | static bool CC_MipsN_SoftFloat(unsigned ValNo, MVT ValVT, |
245 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
246 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
247 | |
|
248 | 0 | static const MCPhysReg RegList1[] = { |
249 | 0 | Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3 |
250 | 0 | }; |
251 | 0 | static const MCPhysReg RegList2[] = { |
252 | 0 | Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 |
253 | 0 | }; |
254 | 0 | if (unsigned Reg = State.AllocateReg(RegList1, RegList2)) { |
255 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
256 | 0 | return false; |
257 | 0 | } |
258 | | |
259 | 0 | int64_t Offset3 = State.AllocateStack(4, Align(8)); |
260 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
261 | 0 | return false; |
262 | | |
263 | 0 | return true; // CC didn't match. |
264 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_MipsN_SoftFloat(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_MipsN_SoftFloat(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
265 | | |
266 | | |
267 | | static bool CC_MipsN_VarArg(unsigned ValNo, MVT ValVT, |
268 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
269 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
270 | |
|
271 | 0 | if (LocVT == MVT::i8 || |
272 | 0 | LocVT == MVT::i16 || |
273 | 0 | LocVT == MVT::i32 || |
274 | 0 | LocVT == MVT::i64) { |
275 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { |
276 | 0 | if (ArgFlags.isInReg()) { |
277 | 0 | LocVT = MVT::i64; |
278 | 0 | if (ArgFlags.isSExt()) |
279 | 0 | LocInfo = CCValAssign::SExtUpper; |
280 | 0 | else if (ArgFlags.isZExt()) |
281 | 0 | LocInfo = CCValAssign::ZExtUpper; |
282 | 0 | else |
283 | 0 | LocInfo = CCValAssign::AExtUpper; |
284 | 0 | } |
285 | 0 | } |
286 | 0 | } |
287 | |
|
288 | 0 | if (LocVT == MVT::i8 || |
289 | 0 | LocVT == MVT::i16 || |
290 | 0 | LocVT == MVT::i32) { |
291 | 0 | LocVT = MVT::i64; |
292 | 0 | if (ArgFlags.isSExt()) |
293 | 0 | LocInfo = CCValAssign::SExt; |
294 | 0 | else if (ArgFlags.isZExt()) |
295 | 0 | LocInfo = CCValAssign::ZExt; |
296 | 0 | else |
297 | 0 | LocInfo = CCValAssign::AExt; |
298 | 0 | } |
299 | |
|
300 | 0 | if (LocVT == MVT::f32) { |
301 | 0 | static const MCPhysReg RegList1[] = { |
302 | 0 | Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3 |
303 | 0 | }; |
304 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
305 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
306 | 0 | return false; |
307 | 0 | } |
308 | 0 | } |
309 | | |
310 | 0 | if (LocVT == MVT::i64 || |
311 | 0 | LocVT == MVT::f64) { |
312 | 0 | static const MCPhysReg RegList2[] = { |
313 | 0 | Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64 |
314 | 0 | }; |
315 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
316 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
317 | 0 | return false; |
318 | 0 | } |
319 | 0 | } |
320 | | |
321 | 0 | if (LocVT == MVT::f32) { |
322 | 0 | int64_t Offset3 = State.AllocateStack(4, Align(8)); |
323 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
324 | 0 | return false; |
325 | 0 | } |
326 | | |
327 | 0 | if (LocVT == MVT::i64 || |
328 | 0 | LocVT == MVT::f64) { |
329 | 0 | int64_t Offset4 = State.AllocateStack(8, Align(8)); |
330 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
331 | 0 | return false; |
332 | 0 | } |
333 | | |
334 | 0 | return true; // CC didn't match. |
335 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_MipsN_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_MipsN_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
336 | | |
337 | | |
338 | | static bool CC_MipsO32(unsigned ValNo, MVT ValVT, |
339 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
340 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
341 | |
|
342 | 0 | if (LocVT == MVT::i1 || |
343 | 0 | LocVT == MVT::i8 || |
344 | 0 | LocVT == MVT::i16) { |
345 | 0 | LocVT = MVT::i32; |
346 | 0 | if (ArgFlags.isSExt()) |
347 | 0 | LocInfo = CCValAssign::SExt; |
348 | 0 | else if (ArgFlags.isZExt()) |
349 | 0 | LocInfo = CCValAssign::ZExt; |
350 | 0 | else |
351 | 0 | LocInfo = CCValAssign::AExt; |
352 | 0 | } |
353 | |
|
354 | 0 | if (LocVT == MVT::i32 || |
355 | 0 | LocVT == MVT::f32) { |
356 | 0 | int64_t Offset1 = State.AllocateStack(4, Align(4)); |
357 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
358 | 0 | return false; |
359 | 0 | } |
360 | | |
361 | 0 | if (LocVT == MVT::f64) { |
362 | 0 | int64_t Offset2 = State.AllocateStack(8, Align(8)); |
363 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
364 | 0 | return false; |
365 | 0 | } |
366 | | |
367 | 0 | return true; // CC didn't match. |
368 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_MipsO32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_MipsO32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
369 | | |
370 | | |
371 | | static bool CC_MipsO32_FP(unsigned ValNo, MVT ValVT, |
372 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
373 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
374 | |
|
375 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
376 | 0 | if (!CC_MipsO32_FP32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
377 | 0 | return false; |
378 | 0 | } |
379 | | |
380 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
381 | 0 | if (!CC_MipsO32_FP64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
382 | 0 | return false; |
383 | 0 | } |
384 | | |
385 | 0 | return true; // CC didn't match. |
386 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_MipsO32_FP(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_MipsO32_FP(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
387 | | |
388 | | |
389 | | static bool CC_MipsO32_FastCC(unsigned ValNo, MVT ValVT, |
390 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
391 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
392 | |
|
393 | 0 | if (LocVT == MVT::f64) { |
394 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
395 | 0 | static const MCPhysReg RegList1[] = { |
396 | 0 | Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9 |
397 | 0 | }; |
398 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
399 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
400 | 0 | return false; |
401 | 0 | } |
402 | 0 | } |
403 | 0 | } |
404 | | |
405 | 0 | if (LocVT == MVT::f64) { |
406 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
407 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) { |
408 | 0 | static const MCPhysReg RegList2[] = { |
409 | 0 | Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64 |
410 | 0 | }; |
411 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
412 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
413 | 0 | return false; |
414 | 0 | } |
415 | 0 | } |
416 | 0 | } |
417 | 0 | } |
418 | | |
419 | 0 | if (LocVT == MVT::f64) { |
420 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
421 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) { |
422 | 0 | static const MCPhysReg RegList3[] = { |
423 | 0 | Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64 |
424 | 0 | }; |
425 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
426 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
427 | 0 | return false; |
428 | 0 | } |
429 | 0 | } |
430 | 0 | } |
431 | 0 | } |
432 | | |
433 | 0 | if (LocVT == MVT::f64) { |
434 | 0 | int64_t Offset4 = State.AllocateStack(8, Align(8)); |
435 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
436 | 0 | return false; |
437 | 0 | } |
438 | | |
439 | 0 | return true; // CC didn't match. |
440 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_MipsO32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_MipsO32_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
441 | | |
442 | | |
443 | | static bool CC_Mips_ByVal(unsigned ValNo, MVT ValVT, |
444 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
445 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
446 | |
|
447 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) { |
448 | 0 | if (ArgFlags.isByVal()) { |
449 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
450 | 0 | return false; |
451 | 0 | } |
452 | 0 | } |
453 | | |
454 | 0 | if (ArgFlags.isByVal()) { |
455 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
456 | 0 | return false; |
457 | 0 | } |
458 | | |
459 | 0 | return true; // CC didn't match. |
460 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_Mips_ByVal(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_Mips_ByVal(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
461 | | |
462 | | |
463 | | static bool CC_Mips_FastCC(unsigned ValNo, MVT ValVT, |
464 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
465 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
466 | |
|
467 | 0 | if (ArgFlags.isByVal()) { |
468 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
469 | 0 | return false; |
470 | 0 | } |
471 | | |
472 | 0 | if (LocVT == MVT::i8 || |
473 | 0 | LocVT == MVT::i16) { |
474 | 0 | LocVT = MVT::i32; |
475 | 0 | if (ArgFlags.isSExt()) |
476 | 0 | LocInfo = CCValAssign::SExt; |
477 | 0 | else if (ArgFlags.isZExt()) |
478 | 0 | LocInfo = CCValAssign::ZExt; |
479 | 0 | else |
480 | 0 | LocInfo = CCValAssign::AExt; |
481 | 0 | } |
482 | |
|
483 | 0 | if (LocVT == MVT::i32) { |
484 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) { |
485 | 0 | static const MCPhysReg RegList1[] = { |
486 | 0 | Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::T8, Mips::V1 |
487 | 0 | }; |
488 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
489 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
490 | 0 | return false; |
491 | 0 | } |
492 | 0 | } |
493 | 0 | } |
494 | | |
495 | 0 | if (LocVT == MVT::i32) { |
496 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isTargetNaCl()) { |
497 | 0 | static const MCPhysReg RegList2[] = { |
498 | 0 | Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::V1 |
499 | 0 | }; |
500 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
501 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
502 | 0 | return false; |
503 | 0 | } |
504 | 0 | } |
505 | 0 | } |
506 | | |
507 | 0 | if (LocVT == MVT::f32) { |
508 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useOddSPReg()) { |
509 | 0 | static const MCPhysReg RegList3[] = { |
510 | 0 | Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19 |
511 | 0 | }; |
512 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
513 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
514 | 0 | return false; |
515 | 0 | } |
516 | 0 | } |
517 | 0 | } |
518 | | |
519 | 0 | if (LocVT == MVT::f32) { |
520 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).noOddSPReg()) { |
521 | 0 | static const MCPhysReg RegList4[] = { |
522 | 0 | Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18 |
523 | 0 | }; |
524 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
525 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
526 | 0 | return false; |
527 | 0 | } |
528 | 0 | } |
529 | 0 | } |
530 | | |
531 | 0 | if (LocVT == MVT::i32 || |
532 | 0 | LocVT == MVT::f32) { |
533 | 0 | int64_t Offset5 = State.AllocateStack(4, Align(4)); |
534 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); |
535 | 0 | return false; |
536 | 0 | } |
537 | | |
538 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) { |
539 | 0 | if (!CC_MipsO32_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
540 | 0 | return false; |
541 | 0 | } |
542 | | |
543 | 0 | if (!CC_MipsN_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
544 | 0 | return false; |
545 | | |
546 | 0 | return true; // CC didn't match. |
547 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_Mips_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_Mips_FastCC(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
548 | | |
549 | | |
550 | | static bool CC_Mips_FixedArg(unsigned ValNo, MVT ValVT, |
551 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
552 | 67 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
553 | | |
554 | 67 | if (State.getCallingConv() != CallingConv::Fast) { |
555 | 67 | if (static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == MipsCCState::Mips16RetHelperConv) { |
556 | 0 | if (!CC_Mips16RetHelper(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
557 | 0 | return false; |
558 | 0 | } |
559 | 67 | } |
560 | | |
561 | 67 | if (ArgFlags.isByVal()) { |
562 | 0 | if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
563 | 0 | return false; |
564 | 0 | } |
565 | | |
566 | 67 | if (LocVT == MVT::i64) { |
567 | 4 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
568 | 4 | if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) { |
569 | 0 | LocVT = MVT::f64; |
570 | 0 | LocInfo = CCValAssign::BCvt; |
571 | 0 | } |
572 | 4 | } |
573 | 4 | } |
574 | | |
575 | 67 | if (State.getCallingConv() == CallingConv::Fast) { |
576 | 0 | if (!CC_Mips_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
577 | 0 | return false; |
578 | 0 | } |
579 | | |
580 | 67 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) { |
581 | 0 | if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
582 | 0 | return false; |
583 | 0 | } |
584 | | |
585 | 67 | if (!CC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
586 | 67 | return false; |
587 | | |
588 | 0 | return true; // CC didn't match. |
589 | 67 | } MipsISelLowering.cpp:CC_Mips_FixedArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 552 | 67 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 553 | | | 554 | 67 | if (State.getCallingConv() != CallingConv::Fast) { | 555 | 67 | if (static_cast<MipsCCState *>(&State)->getSpecialCallingConv() == MipsCCState::Mips16RetHelperConv) { | 556 | 0 | if (!CC_Mips16RetHelper(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 557 | 0 | return false; | 558 | 0 | } | 559 | 67 | } | 560 | | | 561 | 67 | if (ArgFlags.isByVal()) { | 562 | 0 | if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 563 | 0 | return false; | 564 | 0 | } | 565 | | | 566 | 67 | if (LocVT == MVT::i64) { | 567 | 4 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { | 568 | 4 | if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) { | 569 | 0 | LocVT = MVT::f64; | 570 | 0 | LocInfo = CCValAssign::BCvt; | 571 | 0 | } | 572 | 4 | } | 573 | 4 | } | 574 | | | 575 | 67 | if (State.getCallingConv() == CallingConv::Fast) { | 576 | 0 | if (!CC_Mips_FastCC(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 577 | 0 | return false; | 578 | 0 | } | 579 | | | 580 | 67 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) { | 581 | 0 | if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 582 | 0 | return false; | 583 | 0 | } | 584 | | | 585 | 67 | if (!CC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 586 | 67 | return false; | 587 | | | 588 | 0 | return true; // CC didn't match. | 589 | 67 | } |
Unexecuted instantiation: MipsFastISel.cpp:CC_Mips_FixedArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
590 | | |
591 | | |
592 | | static bool CC_Mips_VarArg(unsigned ValNo, MVT ValVT, |
593 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
594 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
595 | |
|
596 | 0 | if (ArgFlags.isByVal()) { |
597 | 0 | if (!CC_Mips_ByVal(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
598 | 0 | return false; |
599 | 0 | } |
600 | | |
601 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_O32()) { |
602 | 0 | if (!CC_MipsO32_FP(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
603 | 0 | return false; |
604 | 0 | } |
605 | | |
606 | 0 | if (!CC_MipsN_VarArg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
607 | 0 | return false; |
608 | | |
609 | 0 | return true; // CC didn't match. |
610 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:CC_Mips_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:CC_Mips_VarArg(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
611 | | |
612 | | |
613 | | static bool RetCC_F128(unsigned ValNo, MVT ValVT, |
614 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
615 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
616 | |
|
617 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
618 | 0 | if (LocVT == MVT::i64) { |
619 | 0 | if (!RetCC_F128SoftFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
620 | 0 | return false; |
621 | 0 | } |
622 | 0 | } |
623 | | |
624 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
625 | 0 | if (LocVT == MVT::i64) { |
626 | 0 | if (!RetCC_F128HardFloat(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
627 | 0 | return false; |
628 | 0 | } |
629 | 0 | } |
630 | | |
631 | 0 | return true; // CC didn't match. |
632 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:RetCC_F128(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:RetCC_F128(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
633 | | |
634 | | |
635 | | static bool RetCC_F128HardFloat(unsigned ValNo, MVT ValVT, |
636 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
637 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
638 | |
|
639 | 0 | LocVT = MVT::f64; |
640 | 0 | LocInfo = CCValAssign::BCvt; |
641 | |
|
642 | 0 | if (ArgFlags.isInReg()) { |
643 | 0 | static const MCPhysReg RegList1[] = { |
644 | 0 | Mips::D0_64, Mips::D1_64 |
645 | 0 | }; |
646 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
647 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
648 | 0 | return false; |
649 | 0 | } |
650 | 0 | } |
651 | | |
652 | 0 | static const MCPhysReg RegList2[] = { |
653 | 0 | Mips::D0_64, Mips::D2_64 |
654 | 0 | }; |
655 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
656 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
657 | 0 | return false; |
658 | 0 | } |
659 | | |
660 | 0 | return true; // CC didn't match. |
661 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:RetCC_F128HardFloat(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:RetCC_F128HardFloat(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
662 | | |
663 | | |
664 | | static bool RetCC_F128SoftFloat(unsigned ValNo, MVT ValVT, |
665 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
666 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
667 | |
|
668 | 0 | static const MCPhysReg RegList1[] = { |
669 | 0 | Mips::V0_64, Mips::A0_64 |
670 | 0 | }; |
671 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
672 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
673 | 0 | return false; |
674 | 0 | } |
675 | | |
676 | 0 | return true; // CC didn't match. |
677 | 0 | } Unexecuted instantiation: MipsISelLowering.cpp:RetCC_F128SoftFloat(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Unexecuted instantiation: MipsFastISel.cpp:RetCC_F128SoftFloat(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
678 | | |
679 | | |
680 | | static bool RetCC_Mips(unsigned ValNo, MVT ValVT, |
681 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
682 | 48 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
683 | | |
684 | 48 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N32()) { |
685 | 0 | if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
686 | 0 | return false; |
687 | 0 | } |
688 | | |
689 | 48 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N64()) { |
690 | 48 | if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
691 | 22 | return false; |
692 | 48 | } |
693 | | |
694 | 26 | if (!RetCC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
695 | 26 | return false; |
696 | | |
697 | 0 | return true; // CC didn't match. |
698 | 26 | } MipsISelLowering.cpp:RetCC_Mips(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 682 | 48 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 683 | | | 684 | 48 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N32()) { | 685 | 0 | if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 686 | 0 | return false; | 687 | 0 | } | 688 | | | 689 | 48 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isABI_N64()) { | 690 | 48 | if (!RetCC_MipsN(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 691 | 22 | return false; | 692 | 48 | } | 693 | | | 694 | 26 | if (!RetCC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 695 | 26 | return false; | 696 | | | 697 | 0 | return true; // CC didn't match. | 698 | 26 | } |
Unexecuted instantiation: MipsFastISel.cpp:RetCC_Mips(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
699 | | |
700 | | |
701 | | static bool RetCC_MipsN(unsigned ValNo, MVT ValVT, |
702 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
703 | 48 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
704 | | |
705 | 48 | if (LocVT == MVT::i64) { |
706 | 0 | if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) { |
707 | 0 | if (!RetCC_F128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
708 | 0 | return false; |
709 | 0 | } |
710 | 0 | } |
711 | | |
712 | 48 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { |
713 | 0 | if (LocVT == MVT::i8 || |
714 | 0 | LocVT == MVT::i16 || |
715 | 0 | LocVT == MVT::i32 || |
716 | 0 | LocVT == MVT::i64) { |
717 | 0 | if (ArgFlags.isInReg()) { |
718 | 0 | LocVT = MVT::i64; |
719 | 0 | if (ArgFlags.isSExt()) |
720 | 0 | LocInfo = CCValAssign::SExt; |
721 | 0 | else if (ArgFlags.isZExt()) |
722 | 0 | LocInfo = CCValAssign::ZExt; |
723 | 0 | else |
724 | 0 | LocInfo = CCValAssign::AExt; |
725 | 0 | } |
726 | 0 | } |
727 | 0 | } |
728 | | |
729 | 48 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { |
730 | 48 | if (LocVT == MVT::i8 || |
731 | 48 | LocVT == MVT::i16 || |
732 | 48 | LocVT == MVT::i32 || |
733 | 48 | LocVT == MVT::i64) { |
734 | 26 | if (ArgFlags.isInReg()) { |
735 | 0 | LocVT = MVT::i64; |
736 | 0 | if (ArgFlags.isSExt()) |
737 | 0 | LocInfo = CCValAssign::SExtUpper; |
738 | 0 | else if (ArgFlags.isZExt()) |
739 | 0 | LocInfo = CCValAssign::ZExtUpper; |
740 | 0 | else |
741 | 0 | LocInfo = CCValAssign::AExtUpper; |
742 | 0 | } |
743 | 26 | } |
744 | 48 | } |
745 | | |
746 | 48 | if (LocVT == MVT::i64) { |
747 | 0 | static const MCPhysReg RegList1[] = { |
748 | 0 | Mips::V0_64, Mips::V1_64 |
749 | 0 | }; |
750 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
751 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
752 | 0 | return false; |
753 | 0 | } |
754 | 0 | } |
755 | | |
756 | 48 | if (LocVT == MVT::f32) { |
757 | 10 | static const MCPhysReg RegList2[] = { |
758 | 10 | Mips::F0, Mips::F2 |
759 | 10 | }; |
760 | 10 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
761 | 10 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
762 | 10 | return false; |
763 | 10 | } |
764 | 10 | } |
765 | | |
766 | 38 | if (LocVT == MVT::f64) { |
767 | 12 | static const MCPhysReg RegList3[] = { |
768 | 12 | Mips::D0_64, Mips::D2_64 |
769 | 12 | }; |
770 | 12 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
771 | 12 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
772 | 12 | return false; |
773 | 12 | } |
774 | 12 | } |
775 | | |
776 | 26 | return true; // CC didn't match. |
777 | 38 | } MipsISelLowering.cpp:RetCC_MipsN(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 703 | 48 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 704 | | | 705 | 48 | if (LocVT == MVT::i64) { | 706 | 0 | if (static_cast<MipsCCState *>(&State)->WasOriginalArgF128(ValNo)) { | 707 | 0 | if (!RetCC_F128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) | 708 | 0 | return false; | 709 | 0 | } | 710 | 0 | } | 711 | | | 712 | 48 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { | 713 | 0 | if (LocVT == MVT::i8 || | 714 | 0 | LocVT == MVT::i16 || | 715 | 0 | LocVT == MVT::i32 || | 716 | 0 | LocVT == MVT::i64) { | 717 | 0 | if (ArgFlags.isInReg()) { | 718 | 0 | LocVT = MVT::i64; | 719 | 0 | if (ArgFlags.isSExt()) | 720 | 0 | LocInfo = CCValAssign::SExt; | 721 | 0 | else if (ArgFlags.isZExt()) | 722 | 0 | LocInfo = CCValAssign::ZExt; | 723 | 0 | else | 724 | 0 | LocInfo = CCValAssign::AExt; | 725 | 0 | } | 726 | 0 | } | 727 | 0 | } | 728 | | | 729 | 48 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isLittle()) { | 730 | 48 | if (LocVT == MVT::i8 || | 731 | 48 | LocVT == MVT::i16 || | 732 | 48 | LocVT == MVT::i32 || | 733 | 48 | LocVT == MVT::i64) { | 734 | 26 | if (ArgFlags.isInReg()) { | 735 | 0 | LocVT = MVT::i64; | 736 | 0 | if (ArgFlags.isSExt()) | 737 | 0 | LocInfo = CCValAssign::SExtUpper; | 738 | 0 | else if (ArgFlags.isZExt()) | 739 | 0 | LocInfo = CCValAssign::ZExtUpper; | 740 | 0 | else | 741 | 0 | LocInfo = CCValAssign::AExtUpper; | 742 | 0 | } | 743 | 26 | } | 744 | 48 | } | 745 | | | 746 | 48 | if (LocVT == MVT::i64) { | 747 | 0 | static const MCPhysReg RegList1[] = { | 748 | 0 | Mips::V0_64, Mips::V1_64 | 749 | 0 | }; | 750 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { | 751 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 752 | 0 | return false; | 753 | 0 | } | 754 | 0 | } | 755 | | | 756 | 48 | if (LocVT == MVT::f32) { | 757 | 10 | static const MCPhysReg RegList2[] = { | 758 | 10 | Mips::F0, Mips::F2 | 759 | 10 | }; | 760 | 10 | if (unsigned Reg = State.AllocateReg(RegList2)) { | 761 | 10 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 762 | 10 | return false; | 763 | 10 | } | 764 | 10 | } | 765 | | | 766 | 38 | if (LocVT == MVT::f64) { | 767 | 12 | static const MCPhysReg RegList3[] = { | 768 | 12 | Mips::D0_64, Mips::D2_64 | 769 | 12 | }; | 770 | 12 | if (unsigned Reg = State.AllocateReg(RegList3)) { | 771 | 12 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 772 | 12 | return false; | 773 | 12 | } | 774 | 12 | } | 775 | | | 776 | 26 | return true; // CC didn't match. | 777 | 38 | } |
Unexecuted instantiation: MipsFastISel.cpp:RetCC_MipsN(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
778 | | |
779 | | |
780 | | static bool RetCC_MipsO32(unsigned ValNo, MVT ValVT, |
781 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
782 | 26 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
783 | | |
784 | 26 | if (LocVT == MVT::i1 || |
785 | 26 | LocVT == MVT::i8 || |
786 | 26 | LocVT == MVT::i16) { |
787 | 0 | LocVT = MVT::i32; |
788 | 0 | if (ArgFlags.isSExt()) |
789 | 0 | LocInfo = CCValAssign::SExt; |
790 | 0 | else if (ArgFlags.isZExt()) |
791 | 0 | LocInfo = CCValAssign::ZExt; |
792 | 0 | else |
793 | 0 | LocInfo = CCValAssign::AExt; |
794 | 0 | } |
795 | | |
796 | 26 | if (!static_cast<MipsCCState *>(&State)->WasOriginalRetVectorFloat(ValNo)) { |
797 | 26 | if (LocVT == MVT::i32) { |
798 | 26 | static const MCPhysReg RegList1[] = { |
799 | 26 | Mips::V0, Mips::V1, Mips::A0, Mips::A1 |
800 | 26 | }; |
801 | 26 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
802 | 26 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
803 | 26 | return false; |
804 | 26 | } |
805 | 26 | } |
806 | 26 | } |
807 | | |
808 | 0 | if (LocVT == MVT::f32) { |
809 | 0 | static const MCPhysReg RegList2[] = { |
810 | 0 | Mips::F0, Mips::F2 |
811 | 0 | }; |
812 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
813 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
814 | 0 | return false; |
815 | 0 | } |
816 | 0 | } |
817 | | |
818 | 0 | if (LocVT == MVT::f64) { |
819 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
820 | 0 | static const MCPhysReg RegList3[] = { |
821 | 0 | Mips::D0_64, Mips::D2_64 |
822 | 0 | }; |
823 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
824 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
825 | 0 | return false; |
826 | 0 | } |
827 | 0 | } |
828 | 0 | } |
829 | | |
830 | 0 | if (LocVT == MVT::f64) { |
831 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { |
832 | 0 | static const MCPhysReg RegList4[] = { |
833 | 0 | Mips::D0, Mips::D1 |
834 | 0 | }; |
835 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
836 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
837 | 0 | return false; |
838 | 0 | } |
839 | 0 | } |
840 | 0 | } |
841 | | |
842 | 0 | return true; // CC didn't match. |
843 | 0 | } MipsISelLowering.cpp:RetCC_MipsO32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) Line | Count | Source | 782 | 26 | ISD::ArgFlagsTy ArgFlags, CCState &State) { | 783 | | | 784 | 26 | if (LocVT == MVT::i1 || | 785 | 26 | LocVT == MVT::i8 || | 786 | 26 | LocVT == MVT::i16) { | 787 | 0 | LocVT = MVT::i32; | 788 | 0 | if (ArgFlags.isSExt()) | 789 | 0 | LocInfo = CCValAssign::SExt; | 790 | 0 | else if (ArgFlags.isZExt()) | 791 | 0 | LocInfo = CCValAssign::ZExt; | 792 | 0 | else | 793 | 0 | LocInfo = CCValAssign::AExt; | 794 | 0 | } | 795 | | | 796 | 26 | if (!static_cast<MipsCCState *>(&State)->WasOriginalRetVectorFloat(ValNo)) { | 797 | 26 | if (LocVT == MVT::i32) { | 798 | 26 | static const MCPhysReg RegList1[] = { | 799 | 26 | Mips::V0, Mips::V1, Mips::A0, Mips::A1 | 800 | 26 | }; | 801 | 26 | if (unsigned Reg = State.AllocateReg(RegList1)) { | 802 | 26 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 803 | 26 | return false; | 804 | 26 | } | 805 | 26 | } | 806 | 26 | } | 807 | | | 808 | 0 | if (LocVT == MVT::f32) { | 809 | 0 | static const MCPhysReg RegList2[] = { | 810 | 0 | Mips::F0, Mips::F2 | 811 | 0 | }; | 812 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { | 813 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 814 | 0 | return false; | 815 | 0 | } | 816 | 0 | } | 817 | | | 818 | 0 | if (LocVT == MVT::f64) { | 819 | 0 | if (static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { | 820 | 0 | static const MCPhysReg RegList3[] = { | 821 | 0 | Mips::D0_64, Mips::D2_64 | 822 | 0 | }; | 823 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { | 824 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 825 | 0 | return false; | 826 | 0 | } | 827 | 0 | } | 828 | 0 | } | 829 | | | 830 | 0 | if (LocVT == MVT::f64) { | 831 | 0 | if (!static_cast<const MipsSubtarget&>(State.getMachineFunction().getSubtarget()).isFP64bit()) { | 832 | 0 | static const MCPhysReg RegList4[] = { | 833 | 0 | Mips::D0, Mips::D1 | 834 | 0 | }; | 835 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { | 836 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); | 837 | 0 | return false; | 838 | 0 | } | 839 | 0 | } | 840 | 0 | } | 841 | | | 842 | 0 | return true; // CC didn't match. | 843 | 0 | } |
Unexecuted instantiation: MipsFastISel.cpp:RetCC_MipsO32(unsigned int, llvm::MVT, llvm::MVT, llvm::CCValAssign::LocInfo, llvm::ISD::ArgFlagsTy, llvm::CCState&) |
844 | | |
845 | | #else |
846 | | |
847 | | const MCRegister CC_Mips_ArgRegs[] = { 0 }; |
848 | | const MCRegister CC_Mips16RetHelper_ArgRegs[] = { Mips::A0, Mips::A1, Mips::V0, Mips::V1 }; |
849 | | const MCRegister CC_MipsN_ArgRegs[] = { 0 }; |
850 | | const MCRegister CC_MipsN_FastCC_ArgRegs[] = { Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::D0_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::T8_64, Mips::V1_64 }; |
851 | | const MCRegister CC_MipsN_SoftFloat_ArgRegs[] = { 0 }; |
852 | | const MCRegister CC_MipsN_VarArg_ArgRegs[] = { Mips::A0, Mips::A0_64, Mips::A1, Mips::A1_64, Mips::A2, Mips::A2_64, Mips::A3, Mips::A3_64, Mips::T0, Mips::T0_64, Mips::T1, Mips::T1_64, Mips::T2, Mips::T2_64, Mips::T3, Mips::T3_64 }; |
853 | | const MCRegister CC_MipsO32_ArgRegs[] = { 0 }; |
854 | | const MCRegister CC_MipsO32_FP_ArgRegs[] = { 0 }; |
855 | | const MCRegister CC_MipsO32_FastCC_ArgRegs[] = { Mips::D0, Mips::D0_64, Mips::D1, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D1_64, Mips::D2, Mips::D2_64, Mips::D3, Mips::D3_64, Mips::D4, Mips::D4_64, Mips::D5, Mips::D5_64, Mips::D6, Mips::D6_64, Mips::D7, Mips::D7_64, Mips::D8, Mips::D8_64, Mips::D9, Mips::D9_64 }; |
856 | | const MCRegister CC_Mips_ByVal_ArgRegs[] = { 0 }; |
857 | | const MCRegister CC_Mips_FastCC_ArgRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::F0, Mips::F1, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::T8, Mips::V1 }; |
858 | | const MCRegister CC_Mips_FixedArg_ArgRegs[] = { 0 }; |
859 | | const MCRegister CC_Mips_VarArg_ArgRegs[] = { 0 }; |
860 | | const MCRegister RetCC_F128_ArgRegs[] = { 0 }; |
861 | | const MCRegister RetCC_F128HardFloat_ArgRegs[] = { Mips::D0_64, Mips::D1_64, Mips::D2_64 }; |
862 | | const MCRegister RetCC_F128SoftFloat_ArgRegs[] = { Mips::A0_64, Mips::V0_64 }; |
863 | | const MCRegister RetCC_Mips_ArgRegs[] = { 0 }; |
864 | | const MCRegister RetCC_MipsN_ArgRegs[] = { Mips::D0_64, Mips::D2_64, Mips::F0, Mips::F2, Mips::V0_64, Mips::V1_64 }; |
865 | | const MCRegister RetCC_MipsO32_ArgRegs[] = { Mips::A0, Mips::A1, Mips::D0, Mips::D0_64, Mips::D1, Mips::D2_64, Mips::F0, Mips::F2, Mips::V0, Mips::V1 }; |
866 | | |
867 | | #endif // CC_REGISTER_LIST |