/src/build/lib/Target/Mips/MipsGenInstrInfo.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Target Instruction Enum Values and Descriptors *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifdef GET_INSTRINFO_ENUM |
10 | | #undef GET_INSTRINFO_ENUM |
11 | | namespace llvm { |
12 | | |
13 | | namespace Mips { |
14 | | enum { |
15 | | PHI = 0, |
16 | | INLINEASM = 1, |
17 | | INLINEASM_BR = 2, |
18 | | CFI_INSTRUCTION = 3, |
19 | | EH_LABEL = 4, |
20 | | GC_LABEL = 5, |
21 | | ANNOTATION_LABEL = 6, |
22 | | KILL = 7, |
23 | | EXTRACT_SUBREG = 8, |
24 | | INSERT_SUBREG = 9, |
25 | | IMPLICIT_DEF = 10, |
26 | | SUBREG_TO_REG = 11, |
27 | | COPY_TO_REGCLASS = 12, |
28 | | DBG_VALUE = 13, |
29 | | DBG_VALUE_LIST = 14, |
30 | | DBG_INSTR_REF = 15, |
31 | | DBG_PHI = 16, |
32 | | DBG_LABEL = 17, |
33 | | REG_SEQUENCE = 18, |
34 | | COPY = 19, |
35 | | BUNDLE = 20, |
36 | | LIFETIME_START = 21, |
37 | | LIFETIME_END = 22, |
38 | | PSEUDO_PROBE = 23, |
39 | | ARITH_FENCE = 24, |
40 | | STACKMAP = 25, |
41 | | FENTRY_CALL = 26, |
42 | | PATCHPOINT = 27, |
43 | | LOAD_STACK_GUARD = 28, |
44 | | PREALLOCATED_SETUP = 29, |
45 | | PREALLOCATED_ARG = 30, |
46 | | STATEPOINT = 31, |
47 | | LOCAL_ESCAPE = 32, |
48 | | FAULTING_OP = 33, |
49 | | PATCHABLE_OP = 34, |
50 | | PATCHABLE_FUNCTION_ENTER = 35, |
51 | | PATCHABLE_RET = 36, |
52 | | PATCHABLE_FUNCTION_EXIT = 37, |
53 | | PATCHABLE_TAIL_CALL = 38, |
54 | | PATCHABLE_EVENT_CALL = 39, |
55 | | PATCHABLE_TYPED_EVENT_CALL = 40, |
56 | | ICALL_BRANCH_FUNNEL = 41, |
57 | | MEMBARRIER = 42, |
58 | | JUMP_TABLE_DEBUG_INFO = 43, |
59 | | G_ASSERT_SEXT = 44, |
60 | | G_ASSERT_ZEXT = 45, |
61 | | G_ASSERT_ALIGN = 46, |
62 | | G_ADD = 47, |
63 | | G_SUB = 48, |
64 | | G_MUL = 49, |
65 | | G_SDIV = 50, |
66 | | G_UDIV = 51, |
67 | | G_SREM = 52, |
68 | | G_UREM = 53, |
69 | | G_SDIVREM = 54, |
70 | | G_UDIVREM = 55, |
71 | | G_AND = 56, |
72 | | G_OR = 57, |
73 | | G_XOR = 58, |
74 | | G_IMPLICIT_DEF = 59, |
75 | | G_PHI = 60, |
76 | | G_FRAME_INDEX = 61, |
77 | | G_GLOBAL_VALUE = 62, |
78 | | G_CONSTANT_POOL = 63, |
79 | | G_EXTRACT = 64, |
80 | | G_UNMERGE_VALUES = 65, |
81 | | G_INSERT = 66, |
82 | | G_MERGE_VALUES = 67, |
83 | | G_BUILD_VECTOR = 68, |
84 | | G_BUILD_VECTOR_TRUNC = 69, |
85 | | G_CONCAT_VECTORS = 70, |
86 | | G_PTRTOINT = 71, |
87 | | G_INTTOPTR = 72, |
88 | | G_BITCAST = 73, |
89 | | G_FREEZE = 74, |
90 | | G_CONSTANT_FOLD_BARRIER = 75, |
91 | | G_INTRINSIC_FPTRUNC_ROUND = 76, |
92 | | G_INTRINSIC_TRUNC = 77, |
93 | | G_INTRINSIC_ROUND = 78, |
94 | | G_INTRINSIC_LRINT = 79, |
95 | | G_INTRINSIC_ROUNDEVEN = 80, |
96 | | G_READCYCLECOUNTER = 81, |
97 | | G_LOAD = 82, |
98 | | G_SEXTLOAD = 83, |
99 | | G_ZEXTLOAD = 84, |
100 | | G_INDEXED_LOAD = 85, |
101 | | G_INDEXED_SEXTLOAD = 86, |
102 | | G_INDEXED_ZEXTLOAD = 87, |
103 | | G_STORE = 88, |
104 | | G_INDEXED_STORE = 89, |
105 | | G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90, |
106 | | G_ATOMIC_CMPXCHG = 91, |
107 | | G_ATOMICRMW_XCHG = 92, |
108 | | G_ATOMICRMW_ADD = 93, |
109 | | G_ATOMICRMW_SUB = 94, |
110 | | G_ATOMICRMW_AND = 95, |
111 | | G_ATOMICRMW_NAND = 96, |
112 | | G_ATOMICRMW_OR = 97, |
113 | | G_ATOMICRMW_XOR = 98, |
114 | | G_ATOMICRMW_MAX = 99, |
115 | | G_ATOMICRMW_MIN = 100, |
116 | | G_ATOMICRMW_UMAX = 101, |
117 | | G_ATOMICRMW_UMIN = 102, |
118 | | G_ATOMICRMW_FADD = 103, |
119 | | G_ATOMICRMW_FSUB = 104, |
120 | | G_ATOMICRMW_FMAX = 105, |
121 | | G_ATOMICRMW_FMIN = 106, |
122 | | G_ATOMICRMW_UINC_WRAP = 107, |
123 | | G_ATOMICRMW_UDEC_WRAP = 108, |
124 | | G_FENCE = 109, |
125 | | G_PREFETCH = 110, |
126 | | G_BRCOND = 111, |
127 | | G_BRINDIRECT = 112, |
128 | | G_INVOKE_REGION_START = 113, |
129 | | G_INTRINSIC = 114, |
130 | | G_INTRINSIC_W_SIDE_EFFECTS = 115, |
131 | | G_INTRINSIC_CONVERGENT = 116, |
132 | | G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117, |
133 | | G_ANYEXT = 118, |
134 | | G_TRUNC = 119, |
135 | | G_CONSTANT = 120, |
136 | | G_FCONSTANT = 121, |
137 | | G_VASTART = 122, |
138 | | G_VAARG = 123, |
139 | | G_SEXT = 124, |
140 | | G_SEXT_INREG = 125, |
141 | | G_ZEXT = 126, |
142 | | G_SHL = 127, |
143 | | G_LSHR = 128, |
144 | | G_ASHR = 129, |
145 | | G_FSHL = 130, |
146 | | G_FSHR = 131, |
147 | | G_ROTR = 132, |
148 | | G_ROTL = 133, |
149 | | G_ICMP = 134, |
150 | | G_FCMP = 135, |
151 | | G_SELECT = 136, |
152 | | G_UADDO = 137, |
153 | | G_UADDE = 138, |
154 | | G_USUBO = 139, |
155 | | G_USUBE = 140, |
156 | | G_SADDO = 141, |
157 | | G_SADDE = 142, |
158 | | G_SSUBO = 143, |
159 | | G_SSUBE = 144, |
160 | | G_UMULO = 145, |
161 | | G_SMULO = 146, |
162 | | G_UMULH = 147, |
163 | | G_SMULH = 148, |
164 | | G_UADDSAT = 149, |
165 | | G_SADDSAT = 150, |
166 | | G_USUBSAT = 151, |
167 | | G_SSUBSAT = 152, |
168 | | G_USHLSAT = 153, |
169 | | G_SSHLSAT = 154, |
170 | | G_SMULFIX = 155, |
171 | | G_UMULFIX = 156, |
172 | | G_SMULFIXSAT = 157, |
173 | | G_UMULFIXSAT = 158, |
174 | | G_SDIVFIX = 159, |
175 | | G_UDIVFIX = 160, |
176 | | G_SDIVFIXSAT = 161, |
177 | | G_UDIVFIXSAT = 162, |
178 | | G_FADD = 163, |
179 | | G_FSUB = 164, |
180 | | G_FMUL = 165, |
181 | | G_FMA = 166, |
182 | | G_FMAD = 167, |
183 | | G_FDIV = 168, |
184 | | G_FREM = 169, |
185 | | G_FPOW = 170, |
186 | | G_FPOWI = 171, |
187 | | G_FEXP = 172, |
188 | | G_FEXP2 = 173, |
189 | | G_FEXP10 = 174, |
190 | | G_FLOG = 175, |
191 | | G_FLOG2 = 176, |
192 | | G_FLOG10 = 177, |
193 | | G_FLDEXP = 178, |
194 | | G_FFREXP = 179, |
195 | | G_FNEG = 180, |
196 | | G_FPEXT = 181, |
197 | | G_FPTRUNC = 182, |
198 | | G_FPTOSI = 183, |
199 | | G_FPTOUI = 184, |
200 | | G_SITOFP = 185, |
201 | | G_UITOFP = 186, |
202 | | G_FABS = 187, |
203 | | G_FCOPYSIGN = 188, |
204 | | G_IS_FPCLASS = 189, |
205 | | G_FCANONICALIZE = 190, |
206 | | G_FMINNUM = 191, |
207 | | G_FMAXNUM = 192, |
208 | | G_FMINNUM_IEEE = 193, |
209 | | G_FMAXNUM_IEEE = 194, |
210 | | G_FMINIMUM = 195, |
211 | | G_FMAXIMUM = 196, |
212 | | G_GET_FPENV = 197, |
213 | | G_SET_FPENV = 198, |
214 | | G_RESET_FPENV = 199, |
215 | | G_GET_FPMODE = 200, |
216 | | G_SET_FPMODE = 201, |
217 | | G_RESET_FPMODE = 202, |
218 | | G_PTR_ADD = 203, |
219 | | G_PTRMASK = 204, |
220 | | G_SMIN = 205, |
221 | | G_SMAX = 206, |
222 | | G_UMIN = 207, |
223 | | G_UMAX = 208, |
224 | | G_ABS = 209, |
225 | | G_LROUND = 210, |
226 | | G_LLROUND = 211, |
227 | | G_BR = 212, |
228 | | G_BRJT = 213, |
229 | | G_INSERT_VECTOR_ELT = 214, |
230 | | G_EXTRACT_VECTOR_ELT = 215, |
231 | | G_SHUFFLE_VECTOR = 216, |
232 | | G_CTTZ = 217, |
233 | | G_CTTZ_ZERO_UNDEF = 218, |
234 | | G_CTLZ = 219, |
235 | | G_CTLZ_ZERO_UNDEF = 220, |
236 | | G_CTPOP = 221, |
237 | | G_BSWAP = 222, |
238 | | G_BITREVERSE = 223, |
239 | | G_FCEIL = 224, |
240 | | G_FCOS = 225, |
241 | | G_FSIN = 226, |
242 | | G_FSQRT = 227, |
243 | | G_FFLOOR = 228, |
244 | | G_FRINT = 229, |
245 | | G_FNEARBYINT = 230, |
246 | | G_ADDRSPACE_CAST = 231, |
247 | | G_BLOCK_ADDR = 232, |
248 | | G_JUMP_TABLE = 233, |
249 | | G_DYN_STACKALLOC = 234, |
250 | | G_STACKSAVE = 235, |
251 | | G_STACKRESTORE = 236, |
252 | | G_STRICT_FADD = 237, |
253 | | G_STRICT_FSUB = 238, |
254 | | G_STRICT_FMUL = 239, |
255 | | G_STRICT_FDIV = 240, |
256 | | G_STRICT_FREM = 241, |
257 | | G_STRICT_FMA = 242, |
258 | | G_STRICT_FSQRT = 243, |
259 | | G_STRICT_FLDEXP = 244, |
260 | | G_READ_REGISTER = 245, |
261 | | G_WRITE_REGISTER = 246, |
262 | | G_MEMCPY = 247, |
263 | | G_MEMCPY_INLINE = 248, |
264 | | G_MEMMOVE = 249, |
265 | | G_MEMSET = 250, |
266 | | G_BZERO = 251, |
267 | | G_VECREDUCE_SEQ_FADD = 252, |
268 | | G_VECREDUCE_SEQ_FMUL = 253, |
269 | | G_VECREDUCE_FADD = 254, |
270 | | G_VECREDUCE_FMUL = 255, |
271 | | G_VECREDUCE_FMAX = 256, |
272 | | G_VECREDUCE_FMIN = 257, |
273 | | G_VECREDUCE_FMAXIMUM = 258, |
274 | | G_VECREDUCE_FMINIMUM = 259, |
275 | | G_VECREDUCE_ADD = 260, |
276 | | G_VECREDUCE_MUL = 261, |
277 | | G_VECREDUCE_AND = 262, |
278 | | G_VECREDUCE_OR = 263, |
279 | | G_VECREDUCE_XOR = 264, |
280 | | G_VECREDUCE_SMAX = 265, |
281 | | G_VECREDUCE_SMIN = 266, |
282 | | G_VECREDUCE_UMAX = 267, |
283 | | G_VECREDUCE_UMIN = 268, |
284 | | G_SBFX = 269, |
285 | | G_UBFX = 270, |
286 | | ABSMacro = 271, |
287 | | ADJCALLSTACKDOWN = 272, |
288 | | ADJCALLSTACKUP = 273, |
289 | | AND_V_D_PSEUDO = 274, |
290 | | AND_V_H_PSEUDO = 275, |
291 | | AND_V_W_PSEUDO = 276, |
292 | | ATOMIC_CMP_SWAP_I16 = 277, |
293 | | ATOMIC_CMP_SWAP_I16_POSTRA = 278, |
294 | | ATOMIC_CMP_SWAP_I32 = 279, |
295 | | ATOMIC_CMP_SWAP_I32_POSTRA = 280, |
296 | | ATOMIC_CMP_SWAP_I64 = 281, |
297 | | ATOMIC_CMP_SWAP_I64_POSTRA = 282, |
298 | | ATOMIC_CMP_SWAP_I8 = 283, |
299 | | ATOMIC_CMP_SWAP_I8_POSTRA = 284, |
300 | | ATOMIC_LOAD_ADD_I16 = 285, |
301 | | ATOMIC_LOAD_ADD_I16_POSTRA = 286, |
302 | | ATOMIC_LOAD_ADD_I32 = 287, |
303 | | ATOMIC_LOAD_ADD_I32_POSTRA = 288, |
304 | | ATOMIC_LOAD_ADD_I64 = 289, |
305 | | ATOMIC_LOAD_ADD_I64_POSTRA = 290, |
306 | | ATOMIC_LOAD_ADD_I8 = 291, |
307 | | ATOMIC_LOAD_ADD_I8_POSTRA = 292, |
308 | | ATOMIC_LOAD_AND_I16 = 293, |
309 | | ATOMIC_LOAD_AND_I16_POSTRA = 294, |
310 | | ATOMIC_LOAD_AND_I32 = 295, |
311 | | ATOMIC_LOAD_AND_I32_POSTRA = 296, |
312 | | ATOMIC_LOAD_AND_I64 = 297, |
313 | | ATOMIC_LOAD_AND_I64_POSTRA = 298, |
314 | | ATOMIC_LOAD_AND_I8 = 299, |
315 | | ATOMIC_LOAD_AND_I8_POSTRA = 300, |
316 | | ATOMIC_LOAD_MAX_I16 = 301, |
317 | | ATOMIC_LOAD_MAX_I16_POSTRA = 302, |
318 | | ATOMIC_LOAD_MAX_I32 = 303, |
319 | | ATOMIC_LOAD_MAX_I32_POSTRA = 304, |
320 | | ATOMIC_LOAD_MAX_I64 = 305, |
321 | | ATOMIC_LOAD_MAX_I64_POSTRA = 306, |
322 | | ATOMIC_LOAD_MAX_I8 = 307, |
323 | | ATOMIC_LOAD_MAX_I8_POSTRA = 308, |
324 | | ATOMIC_LOAD_MIN_I16 = 309, |
325 | | ATOMIC_LOAD_MIN_I16_POSTRA = 310, |
326 | | ATOMIC_LOAD_MIN_I32 = 311, |
327 | | ATOMIC_LOAD_MIN_I32_POSTRA = 312, |
328 | | ATOMIC_LOAD_MIN_I64 = 313, |
329 | | ATOMIC_LOAD_MIN_I64_POSTRA = 314, |
330 | | ATOMIC_LOAD_MIN_I8 = 315, |
331 | | ATOMIC_LOAD_MIN_I8_POSTRA = 316, |
332 | | ATOMIC_LOAD_NAND_I16 = 317, |
333 | | ATOMIC_LOAD_NAND_I16_POSTRA = 318, |
334 | | ATOMIC_LOAD_NAND_I32 = 319, |
335 | | ATOMIC_LOAD_NAND_I32_POSTRA = 320, |
336 | | ATOMIC_LOAD_NAND_I64 = 321, |
337 | | ATOMIC_LOAD_NAND_I64_POSTRA = 322, |
338 | | ATOMIC_LOAD_NAND_I8 = 323, |
339 | | ATOMIC_LOAD_NAND_I8_POSTRA = 324, |
340 | | ATOMIC_LOAD_OR_I16 = 325, |
341 | | ATOMIC_LOAD_OR_I16_POSTRA = 326, |
342 | | ATOMIC_LOAD_OR_I32 = 327, |
343 | | ATOMIC_LOAD_OR_I32_POSTRA = 328, |
344 | | ATOMIC_LOAD_OR_I64 = 329, |
345 | | ATOMIC_LOAD_OR_I64_POSTRA = 330, |
346 | | ATOMIC_LOAD_OR_I8 = 331, |
347 | | ATOMIC_LOAD_OR_I8_POSTRA = 332, |
348 | | ATOMIC_LOAD_SUB_I16 = 333, |
349 | | ATOMIC_LOAD_SUB_I16_POSTRA = 334, |
350 | | ATOMIC_LOAD_SUB_I32 = 335, |
351 | | ATOMIC_LOAD_SUB_I32_POSTRA = 336, |
352 | | ATOMIC_LOAD_SUB_I64 = 337, |
353 | | ATOMIC_LOAD_SUB_I64_POSTRA = 338, |
354 | | ATOMIC_LOAD_SUB_I8 = 339, |
355 | | ATOMIC_LOAD_SUB_I8_POSTRA = 340, |
356 | | ATOMIC_LOAD_UMAX_I16 = 341, |
357 | | ATOMIC_LOAD_UMAX_I16_POSTRA = 342, |
358 | | ATOMIC_LOAD_UMAX_I32 = 343, |
359 | | ATOMIC_LOAD_UMAX_I32_POSTRA = 344, |
360 | | ATOMIC_LOAD_UMAX_I64 = 345, |
361 | | ATOMIC_LOAD_UMAX_I64_POSTRA = 346, |
362 | | ATOMIC_LOAD_UMAX_I8 = 347, |
363 | | ATOMIC_LOAD_UMAX_I8_POSTRA = 348, |
364 | | ATOMIC_LOAD_UMIN_I16 = 349, |
365 | | ATOMIC_LOAD_UMIN_I16_POSTRA = 350, |
366 | | ATOMIC_LOAD_UMIN_I32 = 351, |
367 | | ATOMIC_LOAD_UMIN_I32_POSTRA = 352, |
368 | | ATOMIC_LOAD_UMIN_I64 = 353, |
369 | | ATOMIC_LOAD_UMIN_I64_POSTRA = 354, |
370 | | ATOMIC_LOAD_UMIN_I8 = 355, |
371 | | ATOMIC_LOAD_UMIN_I8_POSTRA = 356, |
372 | | ATOMIC_LOAD_XOR_I16 = 357, |
373 | | ATOMIC_LOAD_XOR_I16_POSTRA = 358, |
374 | | ATOMIC_LOAD_XOR_I32 = 359, |
375 | | ATOMIC_LOAD_XOR_I32_POSTRA = 360, |
376 | | ATOMIC_LOAD_XOR_I64 = 361, |
377 | | ATOMIC_LOAD_XOR_I64_POSTRA = 362, |
378 | | ATOMIC_LOAD_XOR_I8 = 363, |
379 | | ATOMIC_LOAD_XOR_I8_POSTRA = 364, |
380 | | ATOMIC_SWAP_I16 = 365, |
381 | | ATOMIC_SWAP_I16_POSTRA = 366, |
382 | | ATOMIC_SWAP_I32 = 367, |
383 | | ATOMIC_SWAP_I32_POSTRA = 368, |
384 | | ATOMIC_SWAP_I64 = 369, |
385 | | ATOMIC_SWAP_I64_POSTRA = 370, |
386 | | ATOMIC_SWAP_I8 = 371, |
387 | | ATOMIC_SWAP_I8_POSTRA = 372, |
388 | | B = 373, |
389 | | BAL_BR = 374, |
390 | | BAL_BR_MM = 375, |
391 | | BEQLImmMacro = 376, |
392 | | BGE = 377, |
393 | | BGEImmMacro = 378, |
394 | | BGEL = 379, |
395 | | BGELImmMacro = 380, |
396 | | BGEU = 381, |
397 | | BGEUImmMacro = 382, |
398 | | BGEUL = 383, |
399 | | BGEULImmMacro = 384, |
400 | | BGT = 385, |
401 | | BGTImmMacro = 386, |
402 | | BGTL = 387, |
403 | | BGTLImmMacro = 388, |
404 | | BGTU = 389, |
405 | | BGTUImmMacro = 390, |
406 | | BGTUL = 391, |
407 | | BGTULImmMacro = 392, |
408 | | BLE = 393, |
409 | | BLEImmMacro = 394, |
410 | | BLEL = 395, |
411 | | BLELImmMacro = 396, |
412 | | BLEU = 397, |
413 | | BLEUImmMacro = 398, |
414 | | BLEUL = 399, |
415 | | BLEULImmMacro = 400, |
416 | | BLT = 401, |
417 | | BLTImmMacro = 402, |
418 | | BLTL = 403, |
419 | | BLTLImmMacro = 404, |
420 | | BLTU = 405, |
421 | | BLTUImmMacro = 406, |
422 | | BLTUL = 407, |
423 | | BLTULImmMacro = 408, |
424 | | BNELImmMacro = 409, |
425 | | BPOSGE32_PSEUDO = 410, |
426 | | BSEL_D_PSEUDO = 411, |
427 | | BSEL_FD_PSEUDO = 412, |
428 | | BSEL_FW_PSEUDO = 413, |
429 | | BSEL_H_PSEUDO = 414, |
430 | | BSEL_W_PSEUDO = 415, |
431 | | B_MM = 416, |
432 | | B_MMR6_Pseudo = 417, |
433 | | B_MM_Pseudo = 418, |
434 | | BeqImm = 419, |
435 | | BneImm = 420, |
436 | | BteqzT8CmpX16 = 421, |
437 | | BteqzT8CmpiX16 = 422, |
438 | | BteqzT8SltX16 = 423, |
439 | | BteqzT8SltiX16 = 424, |
440 | | BteqzT8SltiuX16 = 425, |
441 | | BteqzT8SltuX16 = 426, |
442 | | BtnezT8CmpX16 = 427, |
443 | | BtnezT8CmpiX16 = 428, |
444 | | BtnezT8SltX16 = 429, |
445 | | BtnezT8SltiX16 = 430, |
446 | | BtnezT8SltiuX16 = 431, |
447 | | BtnezT8SltuX16 = 432, |
448 | | BuildPairF64 = 433, |
449 | | BuildPairF64_64 = 434, |
450 | | CFTC1 = 435, |
451 | | CONSTPOOL_ENTRY = 436, |
452 | | COPY_FD_PSEUDO = 437, |
453 | | COPY_FW_PSEUDO = 438, |
454 | | CTTC1 = 439, |
455 | | Constant32 = 440, |
456 | | DMULImmMacro = 441, |
457 | | DMULMacro = 442, |
458 | | DMULOMacro = 443, |
459 | | DMULOUMacro = 444, |
460 | | DROL = 445, |
461 | | DROLImm = 446, |
462 | | DROR = 447, |
463 | | DRORImm = 448, |
464 | | DSDivIMacro = 449, |
465 | | DSDivMacro = 450, |
466 | | DSRemIMacro = 451, |
467 | | DSRemMacro = 452, |
468 | | DUDivIMacro = 453, |
469 | | DUDivMacro = 454, |
470 | | DURemIMacro = 455, |
471 | | DURemMacro = 456, |
472 | | ERet = 457, |
473 | | ExtractElementF64 = 458, |
474 | | ExtractElementF64_64 = 459, |
475 | | FABS_D = 460, |
476 | | FABS_W = 461, |
477 | | FEXP2_D_1_PSEUDO = 462, |
478 | | FEXP2_W_1_PSEUDO = 463, |
479 | | FILL_FD_PSEUDO = 464, |
480 | | FILL_FW_PSEUDO = 465, |
481 | | GotPrologue16 = 466, |
482 | | INSERT_B_VIDX64_PSEUDO = 467, |
483 | | INSERT_B_VIDX_PSEUDO = 468, |
484 | | INSERT_D_VIDX64_PSEUDO = 469, |
485 | | INSERT_D_VIDX_PSEUDO = 470, |
486 | | INSERT_FD_PSEUDO = 471, |
487 | | INSERT_FD_VIDX64_PSEUDO = 472, |
488 | | INSERT_FD_VIDX_PSEUDO = 473, |
489 | | INSERT_FW_PSEUDO = 474, |
490 | | INSERT_FW_VIDX64_PSEUDO = 475, |
491 | | INSERT_FW_VIDX_PSEUDO = 476, |
492 | | INSERT_H_VIDX64_PSEUDO = 477, |
493 | | INSERT_H_VIDX_PSEUDO = 478, |
494 | | INSERT_W_VIDX64_PSEUDO = 479, |
495 | | INSERT_W_VIDX_PSEUDO = 480, |
496 | | JALR64Pseudo = 481, |
497 | | JALRHB64Pseudo = 482, |
498 | | JALRHBPseudo = 483, |
499 | | JALRPseudo = 484, |
500 | | JAL_MMR6 = 485, |
501 | | JalOneReg = 486, |
502 | | JalTwoReg = 487, |
503 | | LDMacro = 488, |
504 | | LDR_D = 489, |
505 | | LDR_W = 490, |
506 | | LD_F16 = 491, |
507 | | LOAD_ACC128 = 492, |
508 | | LOAD_ACC64 = 493, |
509 | | LOAD_ACC64DSP = 494, |
510 | | LOAD_CCOND_DSP = 495, |
511 | | LONG_BRANCH_ADDiu = 496, |
512 | | LONG_BRANCH_ADDiu2Op = 497, |
513 | | LONG_BRANCH_DADDiu = 498, |
514 | | LONG_BRANCH_DADDiu2Op = 499, |
515 | | LONG_BRANCH_LUi = 500, |
516 | | LONG_BRANCH_LUi2Op = 501, |
517 | | LONG_BRANCH_LUi2Op_64 = 502, |
518 | | LWM_MM = 503, |
519 | | LoadAddrImm32 = 504, |
520 | | LoadAddrImm64 = 505, |
521 | | LoadAddrReg32 = 506, |
522 | | LoadAddrReg64 = 507, |
523 | | LoadImm32 = 508, |
524 | | LoadImm64 = 509, |
525 | | LoadImmDoubleFGR = 510, |
526 | | LoadImmDoubleFGR_32 = 511, |
527 | | LoadImmDoubleGPR = 512, |
528 | | LoadImmSingleFGR = 513, |
529 | | LoadImmSingleGPR = 514, |
530 | | LwConstant32 = 515, |
531 | | MFTACX = 516, |
532 | | MFTC0 = 517, |
533 | | MFTC1 = 518, |
534 | | MFTDSP = 519, |
535 | | MFTGPR = 520, |
536 | | MFTHC1 = 521, |
537 | | MFTHI = 522, |
538 | | MFTLO = 523, |
539 | | MIPSeh_return32 = 524, |
540 | | MIPSeh_return64 = 525, |
541 | | MSA_FP_EXTEND_D_PSEUDO = 526, |
542 | | MSA_FP_EXTEND_W_PSEUDO = 527, |
543 | | MSA_FP_ROUND_D_PSEUDO = 528, |
544 | | MSA_FP_ROUND_W_PSEUDO = 529, |
545 | | MTTACX = 530, |
546 | | MTTC0 = 531, |
547 | | MTTC1 = 532, |
548 | | MTTDSP = 533, |
549 | | MTTGPR = 534, |
550 | | MTTHC1 = 535, |
551 | | MTTHI = 536, |
552 | | MTTLO = 537, |
553 | | MULImmMacro = 538, |
554 | | MULOMacro = 539, |
555 | | MULOUMacro = 540, |
556 | | MultRxRy16 = 541, |
557 | | MultRxRyRz16 = 542, |
558 | | MultuRxRy16 = 543, |
559 | | MultuRxRyRz16 = 544, |
560 | | NOP = 545, |
561 | | NORImm = 546, |
562 | | NORImm64 = 547, |
563 | | NOR_V_D_PSEUDO = 548, |
564 | | NOR_V_H_PSEUDO = 549, |
565 | | NOR_V_W_PSEUDO = 550, |
566 | | OR_V_D_PSEUDO = 551, |
567 | | OR_V_H_PSEUDO = 552, |
568 | | OR_V_W_PSEUDO = 553, |
569 | | PseudoCMPU_EQ_QB = 554, |
570 | | PseudoCMPU_LE_QB = 555, |
571 | | PseudoCMPU_LT_QB = 556, |
572 | | PseudoCMP_EQ_PH = 557, |
573 | | PseudoCMP_LE_PH = 558, |
574 | | PseudoCMP_LT_PH = 559, |
575 | | PseudoCVT_D32_W = 560, |
576 | | PseudoCVT_D64_L = 561, |
577 | | PseudoCVT_D64_W = 562, |
578 | | PseudoCVT_S_L = 563, |
579 | | PseudoCVT_S_W = 564, |
580 | | PseudoDMULT = 565, |
581 | | PseudoDMULTu = 566, |
582 | | PseudoDSDIV = 567, |
583 | | PseudoDUDIV = 568, |
584 | | PseudoD_SELECT_I = 569, |
585 | | PseudoD_SELECT_I64 = 570, |
586 | | PseudoIndirectBranch = 571, |
587 | | PseudoIndirectBranch64 = 572, |
588 | | PseudoIndirectBranch64R6 = 573, |
589 | | PseudoIndirectBranchR6 = 574, |
590 | | PseudoIndirectBranch_MM = 575, |
591 | | PseudoIndirectBranch_MMR6 = 576, |
592 | | PseudoIndirectHazardBranch = 577, |
593 | | PseudoIndirectHazardBranch64 = 578, |
594 | | PseudoIndrectHazardBranch64R6 = 579, |
595 | | PseudoIndrectHazardBranchR6 = 580, |
596 | | PseudoMADD = 581, |
597 | | PseudoMADDU = 582, |
598 | | PseudoMADDU_MM = 583, |
599 | | PseudoMADD_MM = 584, |
600 | | PseudoMFHI = 585, |
601 | | PseudoMFHI64 = 586, |
602 | | PseudoMFHI_MM = 587, |
603 | | PseudoMFLO = 588, |
604 | | PseudoMFLO64 = 589, |
605 | | PseudoMFLO_MM = 590, |
606 | | PseudoMSUB = 591, |
607 | | PseudoMSUBU = 592, |
608 | | PseudoMSUBU_MM = 593, |
609 | | PseudoMSUB_MM = 594, |
610 | | PseudoMTLOHI = 595, |
611 | | PseudoMTLOHI64 = 596, |
612 | | PseudoMTLOHI_DSP = 597, |
613 | | PseudoMTLOHI_MM = 598, |
614 | | PseudoMULT = 599, |
615 | | PseudoMULT_MM = 600, |
616 | | PseudoMULTu = 601, |
617 | | PseudoMULTu_MM = 602, |
618 | | PseudoPICK_PH = 603, |
619 | | PseudoPICK_QB = 604, |
620 | | PseudoReturn = 605, |
621 | | PseudoReturn64 = 606, |
622 | | PseudoSDIV = 607, |
623 | | PseudoSELECTFP_F_D32 = 608, |
624 | | PseudoSELECTFP_F_D64 = 609, |
625 | | PseudoSELECTFP_F_I = 610, |
626 | | PseudoSELECTFP_F_I64 = 611, |
627 | | PseudoSELECTFP_F_S = 612, |
628 | | PseudoSELECTFP_T_D32 = 613, |
629 | | PseudoSELECTFP_T_D64 = 614, |
630 | | PseudoSELECTFP_T_I = 615, |
631 | | PseudoSELECTFP_T_I64 = 616, |
632 | | PseudoSELECTFP_T_S = 617, |
633 | | PseudoSELECT_D32 = 618, |
634 | | PseudoSELECT_D64 = 619, |
635 | | PseudoSELECT_I = 620, |
636 | | PseudoSELECT_I64 = 621, |
637 | | PseudoSELECT_S = 622, |
638 | | PseudoTRUNC_W_D = 623, |
639 | | PseudoTRUNC_W_D32 = 624, |
640 | | PseudoTRUNC_W_S = 625, |
641 | | PseudoUDIV = 626, |
642 | | ROL = 627, |
643 | | ROLImm = 628, |
644 | | ROR = 629, |
645 | | RORImm = 630, |
646 | | RetRA = 631, |
647 | | RetRA16 = 632, |
648 | | SDC1_M1 = 633, |
649 | | SDIV_MM_Pseudo = 634, |
650 | | SDMacro = 635, |
651 | | SDivIMacro = 636, |
652 | | SDivMacro = 637, |
653 | | SEQIMacro = 638, |
654 | | SEQMacro = 639, |
655 | | SGE = 640, |
656 | | SGEImm = 641, |
657 | | SGEImm64 = 642, |
658 | | SGEU = 643, |
659 | | SGEUImm = 644, |
660 | | SGEUImm64 = 645, |
661 | | SGTImm = 646, |
662 | | SGTImm64 = 647, |
663 | | SGTUImm = 648, |
664 | | SGTUImm64 = 649, |
665 | | SLE = 650, |
666 | | SLEImm = 651, |
667 | | SLEImm64 = 652, |
668 | | SLEU = 653, |
669 | | SLEUImm = 654, |
670 | | SLEUImm64 = 655, |
671 | | SLTImm64 = 656, |
672 | | SLTUImm64 = 657, |
673 | | SNEIMacro = 658, |
674 | | SNEMacro = 659, |
675 | | SNZ_B_PSEUDO = 660, |
676 | | SNZ_D_PSEUDO = 661, |
677 | | SNZ_H_PSEUDO = 662, |
678 | | SNZ_V_PSEUDO = 663, |
679 | | SNZ_W_PSEUDO = 664, |
680 | | SRemIMacro = 665, |
681 | | SRemMacro = 666, |
682 | | STORE_ACC128 = 667, |
683 | | STORE_ACC64 = 668, |
684 | | STORE_ACC64DSP = 669, |
685 | | STORE_CCOND_DSP = 670, |
686 | | STR_D = 671, |
687 | | STR_W = 672, |
688 | | ST_F16 = 673, |
689 | | SWM_MM = 674, |
690 | | SZ_B_PSEUDO = 675, |
691 | | SZ_D_PSEUDO = 676, |
692 | | SZ_H_PSEUDO = 677, |
693 | | SZ_V_PSEUDO = 678, |
694 | | SZ_W_PSEUDO = 679, |
695 | | SaaAddr = 680, |
696 | | SaadAddr = 681, |
697 | | SelBeqZ = 682, |
698 | | SelBneZ = 683, |
699 | | SelTBteqZCmp = 684, |
700 | | SelTBteqZCmpi = 685, |
701 | | SelTBteqZSlt = 686, |
702 | | SelTBteqZSlti = 687, |
703 | | SelTBteqZSltiu = 688, |
704 | | SelTBteqZSltu = 689, |
705 | | SelTBtneZCmp = 690, |
706 | | SelTBtneZCmpi = 691, |
707 | | SelTBtneZSlt = 692, |
708 | | SelTBtneZSlti = 693, |
709 | | SelTBtneZSltiu = 694, |
710 | | SelTBtneZSltu = 695, |
711 | | SltCCRxRy16 = 696, |
712 | | SltiCCRxImmX16 = 697, |
713 | | SltiuCCRxImmX16 = 698, |
714 | | SltuCCRxRy16 = 699, |
715 | | SltuRxRyRz16 = 700, |
716 | | TAILCALL = 701, |
717 | | TAILCALL64R6REG = 702, |
718 | | TAILCALLHB64R6REG = 703, |
719 | | TAILCALLHBR6REG = 704, |
720 | | TAILCALLR6REG = 705, |
721 | | TAILCALLREG = 706, |
722 | | TAILCALLREG64 = 707, |
723 | | TAILCALLREGHB = 708, |
724 | | TAILCALLREGHB64 = 709, |
725 | | TAILCALLREG_MM = 710, |
726 | | TAILCALLREG_MMR6 = 711, |
727 | | TAILCALL_MM = 712, |
728 | | TAILCALL_MMR6 = 713, |
729 | | TRAP = 714, |
730 | | TRAP_MM = 715, |
731 | | UDIV_MM_Pseudo = 716, |
732 | | UDivIMacro = 717, |
733 | | UDivMacro = 718, |
734 | | URemIMacro = 719, |
735 | | URemMacro = 720, |
736 | | Ulh = 721, |
737 | | Ulhu = 722, |
738 | | Ulw = 723, |
739 | | Ush = 724, |
740 | | Usw = 725, |
741 | | XOR_V_D_PSEUDO = 726, |
742 | | XOR_V_H_PSEUDO = 727, |
743 | | XOR_V_W_PSEUDO = 728, |
744 | | ABSQ_S_PH = 729, |
745 | | ABSQ_S_PH_MM = 730, |
746 | | ABSQ_S_QB = 731, |
747 | | ABSQ_S_QB_MMR2 = 732, |
748 | | ABSQ_S_W = 733, |
749 | | ABSQ_S_W_MM = 734, |
750 | | ADD = 735, |
751 | | ADDIUPC = 736, |
752 | | ADDIUPC_MM = 737, |
753 | | ADDIUPC_MMR6 = 738, |
754 | | ADDIUR1SP_MM = 739, |
755 | | ADDIUR2_MM = 740, |
756 | | ADDIUS5_MM = 741, |
757 | | ADDIUSP_MM = 742, |
758 | | ADDIU_MMR6 = 743, |
759 | | ADDQH_PH = 744, |
760 | | ADDQH_PH_MMR2 = 745, |
761 | | ADDQH_R_PH = 746, |
762 | | ADDQH_R_PH_MMR2 = 747, |
763 | | ADDQH_R_W = 748, |
764 | | ADDQH_R_W_MMR2 = 749, |
765 | | ADDQH_W = 750, |
766 | | ADDQH_W_MMR2 = 751, |
767 | | ADDQ_PH = 752, |
768 | | ADDQ_PH_MM = 753, |
769 | | ADDQ_S_PH = 754, |
770 | | ADDQ_S_PH_MM = 755, |
771 | | ADDQ_S_W = 756, |
772 | | ADDQ_S_W_MM = 757, |
773 | | ADDR_PS64 = 758, |
774 | | ADDSC = 759, |
775 | | ADDSC_MM = 760, |
776 | | ADDS_A_B = 761, |
777 | | ADDS_A_D = 762, |
778 | | ADDS_A_H = 763, |
779 | | ADDS_A_W = 764, |
780 | | ADDS_S_B = 765, |
781 | | ADDS_S_D = 766, |
782 | | ADDS_S_H = 767, |
783 | | ADDS_S_W = 768, |
784 | | ADDS_U_B = 769, |
785 | | ADDS_U_D = 770, |
786 | | ADDS_U_H = 771, |
787 | | ADDS_U_W = 772, |
788 | | ADDU16_MM = 773, |
789 | | ADDU16_MMR6 = 774, |
790 | | ADDUH_QB = 775, |
791 | | ADDUH_QB_MMR2 = 776, |
792 | | ADDUH_R_QB = 777, |
793 | | ADDUH_R_QB_MMR2 = 778, |
794 | | ADDU_MMR6 = 779, |
795 | | ADDU_PH = 780, |
796 | | ADDU_PH_MMR2 = 781, |
797 | | ADDU_QB = 782, |
798 | | ADDU_QB_MM = 783, |
799 | | ADDU_S_PH = 784, |
800 | | ADDU_S_PH_MMR2 = 785, |
801 | | ADDU_S_QB = 786, |
802 | | ADDU_S_QB_MM = 787, |
803 | | ADDVI_B = 788, |
804 | | ADDVI_D = 789, |
805 | | ADDVI_H = 790, |
806 | | ADDVI_W = 791, |
807 | | ADDV_B = 792, |
808 | | ADDV_D = 793, |
809 | | ADDV_H = 794, |
810 | | ADDV_W = 795, |
811 | | ADDWC = 796, |
812 | | ADDWC_MM = 797, |
813 | | ADD_A_B = 798, |
814 | | ADD_A_D = 799, |
815 | | ADD_A_H = 800, |
816 | | ADD_A_W = 801, |
817 | | ADD_MM = 802, |
818 | | ADD_MMR6 = 803, |
819 | | ADDi = 804, |
820 | | ADDi_MM = 805, |
821 | | ADDiu = 806, |
822 | | ADDiu_MM = 807, |
823 | | ADDu = 808, |
824 | | ADDu_MM = 809, |
825 | | ALIGN = 810, |
826 | | ALIGN_MMR6 = 811, |
827 | | ALUIPC = 812, |
828 | | ALUIPC_MMR6 = 813, |
829 | | AND = 814, |
830 | | AND16_MM = 815, |
831 | | AND16_MMR6 = 816, |
832 | | AND64 = 817, |
833 | | ANDI16_MM = 818, |
834 | | ANDI16_MMR6 = 819, |
835 | | ANDI_B = 820, |
836 | | ANDI_MMR6 = 821, |
837 | | AND_MM = 822, |
838 | | AND_MMR6 = 823, |
839 | | AND_V = 824, |
840 | | ANDi = 825, |
841 | | ANDi64 = 826, |
842 | | ANDi_MM = 827, |
843 | | APPEND = 828, |
844 | | APPEND_MMR2 = 829, |
845 | | ASUB_S_B = 830, |
846 | | ASUB_S_D = 831, |
847 | | ASUB_S_H = 832, |
848 | | ASUB_S_W = 833, |
849 | | ASUB_U_B = 834, |
850 | | ASUB_U_D = 835, |
851 | | ASUB_U_H = 836, |
852 | | ASUB_U_W = 837, |
853 | | AUI = 838, |
854 | | AUIPC = 839, |
855 | | AUIPC_MMR6 = 840, |
856 | | AUI_MMR6 = 841, |
857 | | AVER_S_B = 842, |
858 | | AVER_S_D = 843, |
859 | | AVER_S_H = 844, |
860 | | AVER_S_W = 845, |
861 | | AVER_U_B = 846, |
862 | | AVER_U_D = 847, |
863 | | AVER_U_H = 848, |
864 | | AVER_U_W = 849, |
865 | | AVE_S_B = 850, |
866 | | AVE_S_D = 851, |
867 | | AVE_S_H = 852, |
868 | | AVE_S_W = 853, |
869 | | AVE_U_B = 854, |
870 | | AVE_U_D = 855, |
871 | | AVE_U_H = 856, |
872 | | AVE_U_W = 857, |
873 | | AddiuRxImmX16 = 858, |
874 | | AddiuRxPcImmX16 = 859, |
875 | | AddiuRxRxImm16 = 860, |
876 | | AddiuRxRxImmX16 = 861, |
877 | | AddiuRxRyOffMemX16 = 862, |
878 | | AddiuSpImm16 = 863, |
879 | | AddiuSpImmX16 = 864, |
880 | | AdduRxRyRz16 = 865, |
881 | | AndRxRxRy16 = 866, |
882 | | B16_MM = 867, |
883 | | BADDu = 868, |
884 | | BAL = 869, |
885 | | BALC = 870, |
886 | | BALC_MMR6 = 871, |
887 | | BALIGN = 872, |
888 | | BALIGN_MMR2 = 873, |
889 | | BBIT0 = 874, |
890 | | BBIT032 = 875, |
891 | | BBIT1 = 876, |
892 | | BBIT132 = 877, |
893 | | BC = 878, |
894 | | BC16_MMR6 = 879, |
895 | | BC1EQZ = 880, |
896 | | BC1EQZC_MMR6 = 881, |
897 | | BC1F = 882, |
898 | | BC1FL = 883, |
899 | | BC1F_MM = 884, |
900 | | BC1NEZ = 885, |
901 | | BC1NEZC_MMR6 = 886, |
902 | | BC1T = 887, |
903 | | BC1TL = 888, |
904 | | BC1T_MM = 889, |
905 | | BC2EQZ = 890, |
906 | | BC2EQZC_MMR6 = 891, |
907 | | BC2NEZ = 892, |
908 | | BC2NEZC_MMR6 = 893, |
909 | | BCLRI_B = 894, |
910 | | BCLRI_D = 895, |
911 | | BCLRI_H = 896, |
912 | | BCLRI_W = 897, |
913 | | BCLR_B = 898, |
914 | | BCLR_D = 899, |
915 | | BCLR_H = 900, |
916 | | BCLR_W = 901, |
917 | | BC_MMR6 = 902, |
918 | | BEQ = 903, |
919 | | BEQ64 = 904, |
920 | | BEQC = 905, |
921 | | BEQC64 = 906, |
922 | | BEQC_MMR6 = 907, |
923 | | BEQL = 908, |
924 | | BEQZ16_MM = 909, |
925 | | BEQZALC = 910, |
926 | | BEQZALC_MMR6 = 911, |
927 | | BEQZC = 912, |
928 | | BEQZC16_MMR6 = 913, |
929 | | BEQZC64 = 914, |
930 | | BEQZC_MM = 915, |
931 | | BEQZC_MMR6 = 916, |
932 | | BEQ_MM = 917, |
933 | | BGEC = 918, |
934 | | BGEC64 = 919, |
935 | | BGEC_MMR6 = 920, |
936 | | BGEUC = 921, |
937 | | BGEUC64 = 922, |
938 | | BGEUC_MMR6 = 923, |
939 | | BGEZ = 924, |
940 | | BGEZ64 = 925, |
941 | | BGEZAL = 926, |
942 | | BGEZALC = 927, |
943 | | BGEZALC_MMR6 = 928, |
944 | | BGEZALL = 929, |
945 | | BGEZALS_MM = 930, |
946 | | BGEZAL_MM = 931, |
947 | | BGEZC = 932, |
948 | | BGEZC64 = 933, |
949 | | BGEZC_MMR6 = 934, |
950 | | BGEZL = 935, |
951 | | BGEZ_MM = 936, |
952 | | BGTZ = 937, |
953 | | BGTZ64 = 938, |
954 | | BGTZALC = 939, |
955 | | BGTZALC_MMR6 = 940, |
956 | | BGTZC = 941, |
957 | | BGTZC64 = 942, |
958 | | BGTZC_MMR6 = 943, |
959 | | BGTZL = 944, |
960 | | BGTZ_MM = 945, |
961 | | BINSLI_B = 946, |
962 | | BINSLI_D = 947, |
963 | | BINSLI_H = 948, |
964 | | BINSLI_W = 949, |
965 | | BINSL_B = 950, |
966 | | BINSL_D = 951, |
967 | | BINSL_H = 952, |
968 | | BINSL_W = 953, |
969 | | BINSRI_B = 954, |
970 | | BINSRI_D = 955, |
971 | | BINSRI_H = 956, |
972 | | BINSRI_W = 957, |
973 | | BINSR_B = 958, |
974 | | BINSR_D = 959, |
975 | | BINSR_H = 960, |
976 | | BINSR_W = 961, |
977 | | BITREV = 962, |
978 | | BITREV_MM = 963, |
979 | | BITSWAP = 964, |
980 | | BITSWAP_MMR6 = 965, |
981 | | BLEZ = 966, |
982 | | BLEZ64 = 967, |
983 | | BLEZALC = 968, |
984 | | BLEZALC_MMR6 = 969, |
985 | | BLEZC = 970, |
986 | | BLEZC64 = 971, |
987 | | BLEZC_MMR6 = 972, |
988 | | BLEZL = 973, |
989 | | BLEZ_MM = 974, |
990 | | BLTC = 975, |
991 | | BLTC64 = 976, |
992 | | BLTC_MMR6 = 977, |
993 | | BLTUC = 978, |
994 | | BLTUC64 = 979, |
995 | | BLTUC_MMR6 = 980, |
996 | | BLTZ = 981, |
997 | | BLTZ64 = 982, |
998 | | BLTZAL = 983, |
999 | | BLTZALC = 984, |
1000 | | BLTZALC_MMR6 = 985, |
1001 | | BLTZALL = 986, |
1002 | | BLTZALS_MM = 987, |
1003 | | BLTZAL_MM = 988, |
1004 | | BLTZC = 989, |
1005 | | BLTZC64 = 990, |
1006 | | BLTZC_MMR6 = 991, |
1007 | | BLTZL = 992, |
1008 | | BLTZ_MM = 993, |
1009 | | BMNZI_B = 994, |
1010 | | BMNZ_V = 995, |
1011 | | BMZI_B = 996, |
1012 | | BMZ_V = 997, |
1013 | | BNE = 998, |
1014 | | BNE64 = 999, |
1015 | | BNEC = 1000, |
1016 | | BNEC64 = 1001, |
1017 | | BNEC_MMR6 = 1002, |
1018 | | BNEGI_B = 1003, |
1019 | | BNEGI_D = 1004, |
1020 | | BNEGI_H = 1005, |
1021 | | BNEGI_W = 1006, |
1022 | | BNEG_B = 1007, |
1023 | | BNEG_D = 1008, |
1024 | | BNEG_H = 1009, |
1025 | | BNEG_W = 1010, |
1026 | | BNEL = 1011, |
1027 | | BNEZ16_MM = 1012, |
1028 | | BNEZALC = 1013, |
1029 | | BNEZALC_MMR6 = 1014, |
1030 | | BNEZC = 1015, |
1031 | | BNEZC16_MMR6 = 1016, |
1032 | | BNEZC64 = 1017, |
1033 | | BNEZC_MM = 1018, |
1034 | | BNEZC_MMR6 = 1019, |
1035 | | BNE_MM = 1020, |
1036 | | BNVC = 1021, |
1037 | | BNVC_MMR6 = 1022, |
1038 | | BNZ_B = 1023, |
1039 | | BNZ_D = 1024, |
1040 | | BNZ_H = 1025, |
1041 | | BNZ_V = 1026, |
1042 | | BNZ_W = 1027, |
1043 | | BOVC = 1028, |
1044 | | BOVC_MMR6 = 1029, |
1045 | | BPOSGE32 = 1030, |
1046 | | BPOSGE32C_MMR3 = 1031, |
1047 | | BPOSGE32_MM = 1032, |
1048 | | BREAK = 1033, |
1049 | | BREAK16_MM = 1034, |
1050 | | BREAK16_MMR6 = 1035, |
1051 | | BREAK_MM = 1036, |
1052 | | BREAK_MMR6 = 1037, |
1053 | | BSELI_B = 1038, |
1054 | | BSEL_V = 1039, |
1055 | | BSETI_B = 1040, |
1056 | | BSETI_D = 1041, |
1057 | | BSETI_H = 1042, |
1058 | | BSETI_W = 1043, |
1059 | | BSET_B = 1044, |
1060 | | BSET_D = 1045, |
1061 | | BSET_H = 1046, |
1062 | | BSET_W = 1047, |
1063 | | BZ_B = 1048, |
1064 | | BZ_D = 1049, |
1065 | | BZ_H = 1050, |
1066 | | BZ_V = 1051, |
1067 | | BZ_W = 1052, |
1068 | | BeqzRxImm16 = 1053, |
1069 | | BeqzRxImmX16 = 1054, |
1070 | | Bimm16 = 1055, |
1071 | | BimmX16 = 1056, |
1072 | | BnezRxImm16 = 1057, |
1073 | | BnezRxImmX16 = 1058, |
1074 | | Break16 = 1059, |
1075 | | Bteqz16 = 1060, |
1076 | | BteqzX16 = 1061, |
1077 | | Btnez16 = 1062, |
1078 | | BtnezX16 = 1063, |
1079 | | CACHE = 1064, |
1080 | | CACHEE = 1065, |
1081 | | CACHEE_MM = 1066, |
1082 | | CACHE_MM = 1067, |
1083 | | CACHE_MMR6 = 1068, |
1084 | | CACHE_R6 = 1069, |
1085 | | CEIL_L_D64 = 1070, |
1086 | | CEIL_L_D_MMR6 = 1071, |
1087 | | CEIL_L_S = 1072, |
1088 | | CEIL_L_S_MMR6 = 1073, |
1089 | | CEIL_W_D32 = 1074, |
1090 | | CEIL_W_D64 = 1075, |
1091 | | CEIL_W_D_MMR6 = 1076, |
1092 | | CEIL_W_MM = 1077, |
1093 | | CEIL_W_S = 1078, |
1094 | | CEIL_W_S_MM = 1079, |
1095 | | CEIL_W_S_MMR6 = 1080, |
1096 | | CEQI_B = 1081, |
1097 | | CEQI_D = 1082, |
1098 | | CEQI_H = 1083, |
1099 | | CEQI_W = 1084, |
1100 | | CEQ_B = 1085, |
1101 | | CEQ_D = 1086, |
1102 | | CEQ_H = 1087, |
1103 | | CEQ_W = 1088, |
1104 | | CFC1 = 1089, |
1105 | | CFC1_MM = 1090, |
1106 | | CFC2_MM = 1091, |
1107 | | CFCMSA = 1092, |
1108 | | CINS = 1093, |
1109 | | CINS32 = 1094, |
1110 | | CINS64_32 = 1095, |
1111 | | CINS_i32 = 1096, |
1112 | | CLASS_D = 1097, |
1113 | | CLASS_D_MMR6 = 1098, |
1114 | | CLASS_S = 1099, |
1115 | | CLASS_S_MMR6 = 1100, |
1116 | | CLEI_S_B = 1101, |
1117 | | CLEI_S_D = 1102, |
1118 | | CLEI_S_H = 1103, |
1119 | | CLEI_S_W = 1104, |
1120 | | CLEI_U_B = 1105, |
1121 | | CLEI_U_D = 1106, |
1122 | | CLEI_U_H = 1107, |
1123 | | CLEI_U_W = 1108, |
1124 | | CLE_S_B = 1109, |
1125 | | CLE_S_D = 1110, |
1126 | | CLE_S_H = 1111, |
1127 | | CLE_S_W = 1112, |
1128 | | CLE_U_B = 1113, |
1129 | | CLE_U_D = 1114, |
1130 | | CLE_U_H = 1115, |
1131 | | CLE_U_W = 1116, |
1132 | | CLO = 1117, |
1133 | | CLO_MM = 1118, |
1134 | | CLO_MMR6 = 1119, |
1135 | | CLO_R6 = 1120, |
1136 | | CLTI_S_B = 1121, |
1137 | | CLTI_S_D = 1122, |
1138 | | CLTI_S_H = 1123, |
1139 | | CLTI_S_W = 1124, |
1140 | | CLTI_U_B = 1125, |
1141 | | CLTI_U_D = 1126, |
1142 | | CLTI_U_H = 1127, |
1143 | | CLTI_U_W = 1128, |
1144 | | CLT_S_B = 1129, |
1145 | | CLT_S_D = 1130, |
1146 | | CLT_S_H = 1131, |
1147 | | CLT_S_W = 1132, |
1148 | | CLT_U_B = 1133, |
1149 | | CLT_U_D = 1134, |
1150 | | CLT_U_H = 1135, |
1151 | | CLT_U_W = 1136, |
1152 | | CLZ = 1137, |
1153 | | CLZ_MM = 1138, |
1154 | | CLZ_MMR6 = 1139, |
1155 | | CLZ_R6 = 1140, |
1156 | | CMPGDU_EQ_QB = 1141, |
1157 | | CMPGDU_EQ_QB_MMR2 = 1142, |
1158 | | CMPGDU_LE_QB = 1143, |
1159 | | CMPGDU_LE_QB_MMR2 = 1144, |
1160 | | CMPGDU_LT_QB = 1145, |
1161 | | CMPGDU_LT_QB_MMR2 = 1146, |
1162 | | CMPGU_EQ_QB = 1147, |
1163 | | CMPGU_EQ_QB_MM = 1148, |
1164 | | CMPGU_LE_QB = 1149, |
1165 | | CMPGU_LE_QB_MM = 1150, |
1166 | | CMPGU_LT_QB = 1151, |
1167 | | CMPGU_LT_QB_MM = 1152, |
1168 | | CMPU_EQ_QB = 1153, |
1169 | | CMPU_EQ_QB_MM = 1154, |
1170 | | CMPU_LE_QB = 1155, |
1171 | | CMPU_LE_QB_MM = 1156, |
1172 | | CMPU_LT_QB = 1157, |
1173 | | CMPU_LT_QB_MM = 1158, |
1174 | | CMP_AF_D_MMR6 = 1159, |
1175 | | CMP_AF_S_MMR6 = 1160, |
1176 | | CMP_EQ_D = 1161, |
1177 | | CMP_EQ_D_MMR6 = 1162, |
1178 | | CMP_EQ_PH = 1163, |
1179 | | CMP_EQ_PH_MM = 1164, |
1180 | | CMP_EQ_S = 1165, |
1181 | | CMP_EQ_S_MMR6 = 1166, |
1182 | | CMP_F_D = 1167, |
1183 | | CMP_F_S = 1168, |
1184 | | CMP_LE_D = 1169, |
1185 | | CMP_LE_D_MMR6 = 1170, |
1186 | | CMP_LE_PH = 1171, |
1187 | | CMP_LE_PH_MM = 1172, |
1188 | | CMP_LE_S = 1173, |
1189 | | CMP_LE_S_MMR6 = 1174, |
1190 | | CMP_LT_D = 1175, |
1191 | | CMP_LT_D_MMR6 = 1176, |
1192 | | CMP_LT_PH = 1177, |
1193 | | CMP_LT_PH_MM = 1178, |
1194 | | CMP_LT_S = 1179, |
1195 | | CMP_LT_S_MMR6 = 1180, |
1196 | | CMP_SAF_D = 1181, |
1197 | | CMP_SAF_D_MMR6 = 1182, |
1198 | | CMP_SAF_S = 1183, |
1199 | | CMP_SAF_S_MMR6 = 1184, |
1200 | | CMP_SEQ_D = 1185, |
1201 | | CMP_SEQ_D_MMR6 = 1186, |
1202 | | CMP_SEQ_S = 1187, |
1203 | | CMP_SEQ_S_MMR6 = 1188, |
1204 | | CMP_SLE_D = 1189, |
1205 | | CMP_SLE_D_MMR6 = 1190, |
1206 | | CMP_SLE_S = 1191, |
1207 | | CMP_SLE_S_MMR6 = 1192, |
1208 | | CMP_SLT_D = 1193, |
1209 | | CMP_SLT_D_MMR6 = 1194, |
1210 | | CMP_SLT_S = 1195, |
1211 | | CMP_SLT_S_MMR6 = 1196, |
1212 | | CMP_SUEQ_D = 1197, |
1213 | | CMP_SUEQ_D_MMR6 = 1198, |
1214 | | CMP_SUEQ_S = 1199, |
1215 | | CMP_SUEQ_S_MMR6 = 1200, |
1216 | | CMP_SULE_D = 1201, |
1217 | | CMP_SULE_D_MMR6 = 1202, |
1218 | | CMP_SULE_S = 1203, |
1219 | | CMP_SULE_S_MMR6 = 1204, |
1220 | | CMP_SULT_D = 1205, |
1221 | | CMP_SULT_D_MMR6 = 1206, |
1222 | | CMP_SULT_S = 1207, |
1223 | | CMP_SULT_S_MMR6 = 1208, |
1224 | | CMP_SUN_D = 1209, |
1225 | | CMP_SUN_D_MMR6 = 1210, |
1226 | | CMP_SUN_S = 1211, |
1227 | | CMP_SUN_S_MMR6 = 1212, |
1228 | | CMP_UEQ_D = 1213, |
1229 | | CMP_UEQ_D_MMR6 = 1214, |
1230 | | CMP_UEQ_S = 1215, |
1231 | | CMP_UEQ_S_MMR6 = 1216, |
1232 | | CMP_ULE_D = 1217, |
1233 | | CMP_ULE_D_MMR6 = 1218, |
1234 | | CMP_ULE_S = 1219, |
1235 | | CMP_ULE_S_MMR6 = 1220, |
1236 | | CMP_ULT_D = 1221, |
1237 | | CMP_ULT_D_MMR6 = 1222, |
1238 | | CMP_ULT_S = 1223, |
1239 | | CMP_ULT_S_MMR6 = 1224, |
1240 | | CMP_UN_D = 1225, |
1241 | | CMP_UN_D_MMR6 = 1226, |
1242 | | CMP_UN_S = 1227, |
1243 | | CMP_UN_S_MMR6 = 1228, |
1244 | | COPY_S_B = 1229, |
1245 | | COPY_S_D = 1230, |
1246 | | COPY_S_H = 1231, |
1247 | | COPY_S_W = 1232, |
1248 | | COPY_U_B = 1233, |
1249 | | COPY_U_H = 1234, |
1250 | | COPY_U_W = 1235, |
1251 | | CRC32B = 1236, |
1252 | | CRC32CB = 1237, |
1253 | | CRC32CD = 1238, |
1254 | | CRC32CH = 1239, |
1255 | | CRC32CW = 1240, |
1256 | | CRC32D = 1241, |
1257 | | CRC32H = 1242, |
1258 | | CRC32W = 1243, |
1259 | | CTC1 = 1244, |
1260 | | CTC1_MM = 1245, |
1261 | | CTC2_MM = 1246, |
1262 | | CTCMSA = 1247, |
1263 | | CVT_D32_S = 1248, |
1264 | | CVT_D32_S_MM = 1249, |
1265 | | CVT_D32_W = 1250, |
1266 | | CVT_D32_W_MM = 1251, |
1267 | | CVT_D64_L = 1252, |
1268 | | CVT_D64_S = 1253, |
1269 | | CVT_D64_S_MM = 1254, |
1270 | | CVT_D64_W = 1255, |
1271 | | CVT_D64_W_MM = 1256, |
1272 | | CVT_D_L_MMR6 = 1257, |
1273 | | CVT_L_D64 = 1258, |
1274 | | CVT_L_D64_MM = 1259, |
1275 | | CVT_L_D_MMR6 = 1260, |
1276 | | CVT_L_S = 1261, |
1277 | | CVT_L_S_MM = 1262, |
1278 | | CVT_L_S_MMR6 = 1263, |
1279 | | CVT_PS_PW64 = 1264, |
1280 | | CVT_PS_S64 = 1265, |
1281 | | CVT_PW_PS64 = 1266, |
1282 | | CVT_S_D32 = 1267, |
1283 | | CVT_S_D32_MM = 1268, |
1284 | | CVT_S_D64 = 1269, |
1285 | | CVT_S_D64_MM = 1270, |
1286 | | CVT_S_L = 1271, |
1287 | | CVT_S_L_MMR6 = 1272, |
1288 | | CVT_S_PL64 = 1273, |
1289 | | CVT_S_PU64 = 1274, |
1290 | | CVT_S_W = 1275, |
1291 | | CVT_S_W_MM = 1276, |
1292 | | CVT_S_W_MMR6 = 1277, |
1293 | | CVT_W_D32 = 1278, |
1294 | | CVT_W_D32_MM = 1279, |
1295 | | CVT_W_D64 = 1280, |
1296 | | CVT_W_D64_MM = 1281, |
1297 | | CVT_W_S = 1282, |
1298 | | CVT_W_S_MM = 1283, |
1299 | | CVT_W_S_MMR6 = 1284, |
1300 | | C_EQ_D32 = 1285, |
1301 | | C_EQ_D32_MM = 1286, |
1302 | | C_EQ_D64 = 1287, |
1303 | | C_EQ_D64_MM = 1288, |
1304 | | C_EQ_S = 1289, |
1305 | | C_EQ_S_MM = 1290, |
1306 | | C_F_D32 = 1291, |
1307 | | C_F_D32_MM = 1292, |
1308 | | C_F_D64 = 1293, |
1309 | | C_F_D64_MM = 1294, |
1310 | | C_F_S = 1295, |
1311 | | C_F_S_MM = 1296, |
1312 | | C_LE_D32 = 1297, |
1313 | | C_LE_D32_MM = 1298, |
1314 | | C_LE_D64 = 1299, |
1315 | | C_LE_D64_MM = 1300, |
1316 | | C_LE_S = 1301, |
1317 | | C_LE_S_MM = 1302, |
1318 | | C_LT_D32 = 1303, |
1319 | | C_LT_D32_MM = 1304, |
1320 | | C_LT_D64 = 1305, |
1321 | | C_LT_D64_MM = 1306, |
1322 | | C_LT_S = 1307, |
1323 | | C_LT_S_MM = 1308, |
1324 | | C_NGE_D32 = 1309, |
1325 | | C_NGE_D32_MM = 1310, |
1326 | | C_NGE_D64 = 1311, |
1327 | | C_NGE_D64_MM = 1312, |
1328 | | C_NGE_S = 1313, |
1329 | | C_NGE_S_MM = 1314, |
1330 | | C_NGLE_D32 = 1315, |
1331 | | C_NGLE_D32_MM = 1316, |
1332 | | C_NGLE_D64 = 1317, |
1333 | | C_NGLE_D64_MM = 1318, |
1334 | | C_NGLE_S = 1319, |
1335 | | C_NGLE_S_MM = 1320, |
1336 | | C_NGL_D32 = 1321, |
1337 | | C_NGL_D32_MM = 1322, |
1338 | | C_NGL_D64 = 1323, |
1339 | | C_NGL_D64_MM = 1324, |
1340 | | C_NGL_S = 1325, |
1341 | | C_NGL_S_MM = 1326, |
1342 | | C_NGT_D32 = 1327, |
1343 | | C_NGT_D32_MM = 1328, |
1344 | | C_NGT_D64 = 1329, |
1345 | | C_NGT_D64_MM = 1330, |
1346 | | C_NGT_S = 1331, |
1347 | | C_NGT_S_MM = 1332, |
1348 | | C_OLE_D32 = 1333, |
1349 | | C_OLE_D32_MM = 1334, |
1350 | | C_OLE_D64 = 1335, |
1351 | | C_OLE_D64_MM = 1336, |
1352 | | C_OLE_S = 1337, |
1353 | | C_OLE_S_MM = 1338, |
1354 | | C_OLT_D32 = 1339, |
1355 | | C_OLT_D32_MM = 1340, |
1356 | | C_OLT_D64 = 1341, |
1357 | | C_OLT_D64_MM = 1342, |
1358 | | C_OLT_S = 1343, |
1359 | | C_OLT_S_MM = 1344, |
1360 | | C_SEQ_D32 = 1345, |
1361 | | C_SEQ_D32_MM = 1346, |
1362 | | C_SEQ_D64 = 1347, |
1363 | | C_SEQ_D64_MM = 1348, |
1364 | | C_SEQ_S = 1349, |
1365 | | C_SEQ_S_MM = 1350, |
1366 | | C_SF_D32 = 1351, |
1367 | | C_SF_D32_MM = 1352, |
1368 | | C_SF_D64 = 1353, |
1369 | | C_SF_D64_MM = 1354, |
1370 | | C_SF_S = 1355, |
1371 | | C_SF_S_MM = 1356, |
1372 | | C_UEQ_D32 = 1357, |
1373 | | C_UEQ_D32_MM = 1358, |
1374 | | C_UEQ_D64 = 1359, |
1375 | | C_UEQ_D64_MM = 1360, |
1376 | | C_UEQ_S = 1361, |
1377 | | C_UEQ_S_MM = 1362, |
1378 | | C_ULE_D32 = 1363, |
1379 | | C_ULE_D32_MM = 1364, |
1380 | | C_ULE_D64 = 1365, |
1381 | | C_ULE_D64_MM = 1366, |
1382 | | C_ULE_S = 1367, |
1383 | | C_ULE_S_MM = 1368, |
1384 | | C_ULT_D32 = 1369, |
1385 | | C_ULT_D32_MM = 1370, |
1386 | | C_ULT_D64 = 1371, |
1387 | | C_ULT_D64_MM = 1372, |
1388 | | C_ULT_S = 1373, |
1389 | | C_ULT_S_MM = 1374, |
1390 | | C_UN_D32 = 1375, |
1391 | | C_UN_D32_MM = 1376, |
1392 | | C_UN_D64 = 1377, |
1393 | | C_UN_D64_MM = 1378, |
1394 | | C_UN_S = 1379, |
1395 | | C_UN_S_MM = 1380, |
1396 | | CmpRxRy16 = 1381, |
1397 | | CmpiRxImm16 = 1382, |
1398 | | CmpiRxImmX16 = 1383, |
1399 | | DADD = 1384, |
1400 | | DADDi = 1385, |
1401 | | DADDiu = 1386, |
1402 | | DADDu = 1387, |
1403 | | DAHI = 1388, |
1404 | | DALIGN = 1389, |
1405 | | DATI = 1390, |
1406 | | DAUI = 1391, |
1407 | | DBITSWAP = 1392, |
1408 | | DCLO = 1393, |
1409 | | DCLO_R6 = 1394, |
1410 | | DCLZ = 1395, |
1411 | | DCLZ_R6 = 1396, |
1412 | | DDIV = 1397, |
1413 | | DDIVU = 1398, |
1414 | | DERET = 1399, |
1415 | | DERET_MM = 1400, |
1416 | | DERET_MMR6 = 1401, |
1417 | | DEXT = 1402, |
1418 | | DEXT64_32 = 1403, |
1419 | | DEXTM = 1404, |
1420 | | DEXTU = 1405, |
1421 | | DI = 1406, |
1422 | | DINS = 1407, |
1423 | | DINSM = 1408, |
1424 | | DINSU = 1409, |
1425 | | DIV = 1410, |
1426 | | DIVU = 1411, |
1427 | | DIVU_MMR6 = 1412, |
1428 | | DIV_MMR6 = 1413, |
1429 | | DIV_S_B = 1414, |
1430 | | DIV_S_D = 1415, |
1431 | | DIV_S_H = 1416, |
1432 | | DIV_S_W = 1417, |
1433 | | DIV_U_B = 1418, |
1434 | | DIV_U_D = 1419, |
1435 | | DIV_U_H = 1420, |
1436 | | DIV_U_W = 1421, |
1437 | | DI_MM = 1422, |
1438 | | DI_MMR6 = 1423, |
1439 | | DLSA = 1424, |
1440 | | DLSA_R6 = 1425, |
1441 | | DMFC0 = 1426, |
1442 | | DMFC1 = 1427, |
1443 | | DMFC2 = 1428, |
1444 | | DMFC2_OCTEON = 1429, |
1445 | | DMFGC0 = 1430, |
1446 | | DMOD = 1431, |
1447 | | DMODU = 1432, |
1448 | | DMT = 1433, |
1449 | | DMTC0 = 1434, |
1450 | | DMTC1 = 1435, |
1451 | | DMTC2 = 1436, |
1452 | | DMTC2_OCTEON = 1437, |
1453 | | DMTGC0 = 1438, |
1454 | | DMUH = 1439, |
1455 | | DMUHU = 1440, |
1456 | | DMUL = 1441, |
1457 | | DMULT = 1442, |
1458 | | DMULTu = 1443, |
1459 | | DMULU = 1444, |
1460 | | DMUL_R6 = 1445, |
1461 | | DOTP_S_D = 1446, |
1462 | | DOTP_S_H = 1447, |
1463 | | DOTP_S_W = 1448, |
1464 | | DOTP_U_D = 1449, |
1465 | | DOTP_U_H = 1450, |
1466 | | DOTP_U_W = 1451, |
1467 | | DPADD_S_D = 1452, |
1468 | | DPADD_S_H = 1453, |
1469 | | DPADD_S_W = 1454, |
1470 | | DPADD_U_D = 1455, |
1471 | | DPADD_U_H = 1456, |
1472 | | DPADD_U_W = 1457, |
1473 | | DPAQX_SA_W_PH = 1458, |
1474 | | DPAQX_SA_W_PH_MMR2 = 1459, |
1475 | | DPAQX_S_W_PH = 1460, |
1476 | | DPAQX_S_W_PH_MMR2 = 1461, |
1477 | | DPAQ_SA_L_W = 1462, |
1478 | | DPAQ_SA_L_W_MM = 1463, |
1479 | | DPAQ_S_W_PH = 1464, |
1480 | | DPAQ_S_W_PH_MM = 1465, |
1481 | | DPAU_H_QBL = 1466, |
1482 | | DPAU_H_QBL_MM = 1467, |
1483 | | DPAU_H_QBR = 1468, |
1484 | | DPAU_H_QBR_MM = 1469, |
1485 | | DPAX_W_PH = 1470, |
1486 | | DPAX_W_PH_MMR2 = 1471, |
1487 | | DPA_W_PH = 1472, |
1488 | | DPA_W_PH_MMR2 = 1473, |
1489 | | DPOP = 1474, |
1490 | | DPSQX_SA_W_PH = 1475, |
1491 | | DPSQX_SA_W_PH_MMR2 = 1476, |
1492 | | DPSQX_S_W_PH = 1477, |
1493 | | DPSQX_S_W_PH_MMR2 = 1478, |
1494 | | DPSQ_SA_L_W = 1479, |
1495 | | DPSQ_SA_L_W_MM = 1480, |
1496 | | DPSQ_S_W_PH = 1481, |
1497 | | DPSQ_S_W_PH_MM = 1482, |
1498 | | DPSUB_S_D = 1483, |
1499 | | DPSUB_S_H = 1484, |
1500 | | DPSUB_S_W = 1485, |
1501 | | DPSUB_U_D = 1486, |
1502 | | DPSUB_U_H = 1487, |
1503 | | DPSUB_U_W = 1488, |
1504 | | DPSU_H_QBL = 1489, |
1505 | | DPSU_H_QBL_MM = 1490, |
1506 | | DPSU_H_QBR = 1491, |
1507 | | DPSU_H_QBR_MM = 1492, |
1508 | | DPSX_W_PH = 1493, |
1509 | | DPSX_W_PH_MMR2 = 1494, |
1510 | | DPS_W_PH = 1495, |
1511 | | DPS_W_PH_MMR2 = 1496, |
1512 | | DROTR = 1497, |
1513 | | DROTR32 = 1498, |
1514 | | DROTRV = 1499, |
1515 | | DSBH = 1500, |
1516 | | DSDIV = 1501, |
1517 | | DSHD = 1502, |
1518 | | DSLL = 1503, |
1519 | | DSLL32 = 1504, |
1520 | | DSLL64_32 = 1505, |
1521 | | DSLLV = 1506, |
1522 | | DSRA = 1507, |
1523 | | DSRA32 = 1508, |
1524 | | DSRAV = 1509, |
1525 | | DSRL = 1510, |
1526 | | DSRL32 = 1511, |
1527 | | DSRLV = 1512, |
1528 | | DSUB = 1513, |
1529 | | DSUBu = 1514, |
1530 | | DUDIV = 1515, |
1531 | | DVP = 1516, |
1532 | | DVPE = 1517, |
1533 | | DVP_MMR6 = 1518, |
1534 | | DivRxRy16 = 1519, |
1535 | | DivuRxRy16 = 1520, |
1536 | | EHB = 1521, |
1537 | | EHB_MM = 1522, |
1538 | | EHB_MMR6 = 1523, |
1539 | | EI = 1524, |
1540 | | EI_MM = 1525, |
1541 | | EI_MMR6 = 1526, |
1542 | | EMT = 1527, |
1543 | | ERET = 1528, |
1544 | | ERETNC = 1529, |
1545 | | ERETNC_MMR6 = 1530, |
1546 | | ERET_MM = 1531, |
1547 | | ERET_MMR6 = 1532, |
1548 | | EVP = 1533, |
1549 | | EVPE = 1534, |
1550 | | EVP_MMR6 = 1535, |
1551 | | EXT = 1536, |
1552 | | EXTP = 1537, |
1553 | | EXTPDP = 1538, |
1554 | | EXTPDPV = 1539, |
1555 | | EXTPDPV_MM = 1540, |
1556 | | EXTPDP_MM = 1541, |
1557 | | EXTPV = 1542, |
1558 | | EXTPV_MM = 1543, |
1559 | | EXTP_MM = 1544, |
1560 | | EXTRV_RS_W = 1545, |
1561 | | EXTRV_RS_W_MM = 1546, |
1562 | | EXTRV_R_W = 1547, |
1563 | | EXTRV_R_W_MM = 1548, |
1564 | | EXTRV_S_H = 1549, |
1565 | | EXTRV_S_H_MM = 1550, |
1566 | | EXTRV_W = 1551, |
1567 | | EXTRV_W_MM = 1552, |
1568 | | EXTR_RS_W = 1553, |
1569 | | EXTR_RS_W_MM = 1554, |
1570 | | EXTR_R_W = 1555, |
1571 | | EXTR_R_W_MM = 1556, |
1572 | | EXTR_S_H = 1557, |
1573 | | EXTR_S_H_MM = 1558, |
1574 | | EXTR_W = 1559, |
1575 | | EXTR_W_MM = 1560, |
1576 | | EXTS = 1561, |
1577 | | EXTS32 = 1562, |
1578 | | EXT_MM = 1563, |
1579 | | EXT_MMR6 = 1564, |
1580 | | FABS_D32 = 1565, |
1581 | | FABS_D32_MM = 1566, |
1582 | | FABS_D64 = 1567, |
1583 | | FABS_D64_MM = 1568, |
1584 | | FABS_S = 1569, |
1585 | | FABS_S_MM = 1570, |
1586 | | FADD_D = 1571, |
1587 | | FADD_D32 = 1572, |
1588 | | FADD_D32_MM = 1573, |
1589 | | FADD_D64 = 1574, |
1590 | | FADD_D64_MM = 1575, |
1591 | | FADD_PS64 = 1576, |
1592 | | FADD_S = 1577, |
1593 | | FADD_S_MM = 1578, |
1594 | | FADD_S_MMR6 = 1579, |
1595 | | FADD_W = 1580, |
1596 | | FCAF_D = 1581, |
1597 | | FCAF_W = 1582, |
1598 | | FCEQ_D = 1583, |
1599 | | FCEQ_W = 1584, |
1600 | | FCLASS_D = 1585, |
1601 | | FCLASS_W = 1586, |
1602 | | FCLE_D = 1587, |
1603 | | FCLE_W = 1588, |
1604 | | FCLT_D = 1589, |
1605 | | FCLT_W = 1590, |
1606 | | FCMP_D32 = 1591, |
1607 | | FCMP_D32_MM = 1592, |
1608 | | FCMP_D64 = 1593, |
1609 | | FCMP_S32 = 1594, |
1610 | | FCMP_S32_MM = 1595, |
1611 | | FCNE_D = 1596, |
1612 | | FCNE_W = 1597, |
1613 | | FCOR_D = 1598, |
1614 | | FCOR_W = 1599, |
1615 | | FCUEQ_D = 1600, |
1616 | | FCUEQ_W = 1601, |
1617 | | FCULE_D = 1602, |
1618 | | FCULE_W = 1603, |
1619 | | FCULT_D = 1604, |
1620 | | FCULT_W = 1605, |
1621 | | FCUNE_D = 1606, |
1622 | | FCUNE_W = 1607, |
1623 | | FCUN_D = 1608, |
1624 | | FCUN_W = 1609, |
1625 | | FDIV_D = 1610, |
1626 | | FDIV_D32 = 1611, |
1627 | | FDIV_D32_MM = 1612, |
1628 | | FDIV_D64 = 1613, |
1629 | | FDIV_D64_MM = 1614, |
1630 | | FDIV_S = 1615, |
1631 | | FDIV_S_MM = 1616, |
1632 | | FDIV_S_MMR6 = 1617, |
1633 | | FDIV_W = 1618, |
1634 | | FEXDO_H = 1619, |
1635 | | FEXDO_W = 1620, |
1636 | | FEXP2_D = 1621, |
1637 | | FEXP2_W = 1622, |
1638 | | FEXUPL_D = 1623, |
1639 | | FEXUPL_W = 1624, |
1640 | | FEXUPR_D = 1625, |
1641 | | FEXUPR_W = 1626, |
1642 | | FFINT_S_D = 1627, |
1643 | | FFINT_S_W = 1628, |
1644 | | FFINT_U_D = 1629, |
1645 | | FFINT_U_W = 1630, |
1646 | | FFQL_D = 1631, |
1647 | | FFQL_W = 1632, |
1648 | | FFQR_D = 1633, |
1649 | | FFQR_W = 1634, |
1650 | | FILL_B = 1635, |
1651 | | FILL_D = 1636, |
1652 | | FILL_H = 1637, |
1653 | | FILL_W = 1638, |
1654 | | FLOG2_D = 1639, |
1655 | | FLOG2_W = 1640, |
1656 | | FLOOR_L_D64 = 1641, |
1657 | | FLOOR_L_D_MMR6 = 1642, |
1658 | | FLOOR_L_S = 1643, |
1659 | | FLOOR_L_S_MMR6 = 1644, |
1660 | | FLOOR_W_D32 = 1645, |
1661 | | FLOOR_W_D64 = 1646, |
1662 | | FLOOR_W_D_MMR6 = 1647, |
1663 | | FLOOR_W_MM = 1648, |
1664 | | FLOOR_W_S = 1649, |
1665 | | FLOOR_W_S_MM = 1650, |
1666 | | FLOOR_W_S_MMR6 = 1651, |
1667 | | FMADD_D = 1652, |
1668 | | FMADD_W = 1653, |
1669 | | FMAX_A_D = 1654, |
1670 | | FMAX_A_W = 1655, |
1671 | | FMAX_D = 1656, |
1672 | | FMAX_W = 1657, |
1673 | | FMIN_A_D = 1658, |
1674 | | FMIN_A_W = 1659, |
1675 | | FMIN_D = 1660, |
1676 | | FMIN_W = 1661, |
1677 | | FMOV_D32 = 1662, |
1678 | | FMOV_D32_MM = 1663, |
1679 | | FMOV_D64 = 1664, |
1680 | | FMOV_D64_MM = 1665, |
1681 | | FMOV_D_MMR6 = 1666, |
1682 | | FMOV_S = 1667, |
1683 | | FMOV_S_MM = 1668, |
1684 | | FMOV_S_MMR6 = 1669, |
1685 | | FMSUB_D = 1670, |
1686 | | FMSUB_W = 1671, |
1687 | | FMUL_D = 1672, |
1688 | | FMUL_D32 = 1673, |
1689 | | FMUL_D32_MM = 1674, |
1690 | | FMUL_D64 = 1675, |
1691 | | FMUL_D64_MM = 1676, |
1692 | | FMUL_PS64 = 1677, |
1693 | | FMUL_S = 1678, |
1694 | | FMUL_S_MM = 1679, |
1695 | | FMUL_S_MMR6 = 1680, |
1696 | | FMUL_W = 1681, |
1697 | | FNEG_D32 = 1682, |
1698 | | FNEG_D32_MM = 1683, |
1699 | | FNEG_D64 = 1684, |
1700 | | FNEG_D64_MM = 1685, |
1701 | | FNEG_S = 1686, |
1702 | | FNEG_S_MM = 1687, |
1703 | | FNEG_S_MMR6 = 1688, |
1704 | | FORK = 1689, |
1705 | | FRCP_D = 1690, |
1706 | | FRCP_W = 1691, |
1707 | | FRINT_D = 1692, |
1708 | | FRINT_W = 1693, |
1709 | | FRSQRT_D = 1694, |
1710 | | FRSQRT_W = 1695, |
1711 | | FSAF_D = 1696, |
1712 | | FSAF_W = 1697, |
1713 | | FSEQ_D = 1698, |
1714 | | FSEQ_W = 1699, |
1715 | | FSLE_D = 1700, |
1716 | | FSLE_W = 1701, |
1717 | | FSLT_D = 1702, |
1718 | | FSLT_W = 1703, |
1719 | | FSNE_D = 1704, |
1720 | | FSNE_W = 1705, |
1721 | | FSOR_D = 1706, |
1722 | | FSOR_W = 1707, |
1723 | | FSQRT_D = 1708, |
1724 | | FSQRT_D32 = 1709, |
1725 | | FSQRT_D32_MM = 1710, |
1726 | | FSQRT_D64 = 1711, |
1727 | | FSQRT_D64_MM = 1712, |
1728 | | FSQRT_S = 1713, |
1729 | | FSQRT_S_MM = 1714, |
1730 | | FSQRT_W = 1715, |
1731 | | FSUB_D = 1716, |
1732 | | FSUB_D32 = 1717, |
1733 | | FSUB_D32_MM = 1718, |
1734 | | FSUB_D64 = 1719, |
1735 | | FSUB_D64_MM = 1720, |
1736 | | FSUB_PS64 = 1721, |
1737 | | FSUB_S = 1722, |
1738 | | FSUB_S_MM = 1723, |
1739 | | FSUB_S_MMR6 = 1724, |
1740 | | FSUB_W = 1725, |
1741 | | FSUEQ_D = 1726, |
1742 | | FSUEQ_W = 1727, |
1743 | | FSULE_D = 1728, |
1744 | | FSULE_W = 1729, |
1745 | | FSULT_D = 1730, |
1746 | | FSULT_W = 1731, |
1747 | | FSUNE_D = 1732, |
1748 | | FSUNE_W = 1733, |
1749 | | FSUN_D = 1734, |
1750 | | FSUN_W = 1735, |
1751 | | FTINT_S_D = 1736, |
1752 | | FTINT_S_W = 1737, |
1753 | | FTINT_U_D = 1738, |
1754 | | FTINT_U_W = 1739, |
1755 | | FTQ_H = 1740, |
1756 | | FTQ_W = 1741, |
1757 | | FTRUNC_S_D = 1742, |
1758 | | FTRUNC_S_W = 1743, |
1759 | | FTRUNC_U_D = 1744, |
1760 | | FTRUNC_U_W = 1745, |
1761 | | GINVI = 1746, |
1762 | | GINVI_MMR6 = 1747, |
1763 | | GINVT = 1748, |
1764 | | GINVT_MMR6 = 1749, |
1765 | | HADD_S_D = 1750, |
1766 | | HADD_S_H = 1751, |
1767 | | HADD_S_W = 1752, |
1768 | | HADD_U_D = 1753, |
1769 | | HADD_U_H = 1754, |
1770 | | HADD_U_W = 1755, |
1771 | | HSUB_S_D = 1756, |
1772 | | HSUB_S_H = 1757, |
1773 | | HSUB_S_W = 1758, |
1774 | | HSUB_U_D = 1759, |
1775 | | HSUB_U_H = 1760, |
1776 | | HSUB_U_W = 1761, |
1777 | | HYPCALL = 1762, |
1778 | | HYPCALL_MM = 1763, |
1779 | | ILVEV_B = 1764, |
1780 | | ILVEV_D = 1765, |
1781 | | ILVEV_H = 1766, |
1782 | | ILVEV_W = 1767, |
1783 | | ILVL_B = 1768, |
1784 | | ILVL_D = 1769, |
1785 | | ILVL_H = 1770, |
1786 | | ILVL_W = 1771, |
1787 | | ILVOD_B = 1772, |
1788 | | ILVOD_D = 1773, |
1789 | | ILVOD_H = 1774, |
1790 | | ILVOD_W = 1775, |
1791 | | ILVR_B = 1776, |
1792 | | ILVR_D = 1777, |
1793 | | ILVR_H = 1778, |
1794 | | ILVR_W = 1779, |
1795 | | INS = 1780, |
1796 | | INSERT_B = 1781, |
1797 | | INSERT_D = 1782, |
1798 | | INSERT_H = 1783, |
1799 | | INSERT_W = 1784, |
1800 | | INSV = 1785, |
1801 | | INSVE_B = 1786, |
1802 | | INSVE_D = 1787, |
1803 | | INSVE_H = 1788, |
1804 | | INSVE_W = 1789, |
1805 | | INSV_MM = 1790, |
1806 | | INS_MM = 1791, |
1807 | | INS_MMR6 = 1792, |
1808 | | J = 1793, |
1809 | | JAL = 1794, |
1810 | | JALR = 1795, |
1811 | | JALR16_MM = 1796, |
1812 | | JALR64 = 1797, |
1813 | | JALRC16_MMR6 = 1798, |
1814 | | JALRC_HB_MMR6 = 1799, |
1815 | | JALRC_MMR6 = 1800, |
1816 | | JALRS16_MM = 1801, |
1817 | | JALRS_MM = 1802, |
1818 | | JALR_HB = 1803, |
1819 | | JALR_HB64 = 1804, |
1820 | | JALR_MM = 1805, |
1821 | | JALS_MM = 1806, |
1822 | | JALX = 1807, |
1823 | | JALX_MM = 1808, |
1824 | | JAL_MM = 1809, |
1825 | | JIALC = 1810, |
1826 | | JIALC64 = 1811, |
1827 | | JIALC_MMR6 = 1812, |
1828 | | JIC = 1813, |
1829 | | JIC64 = 1814, |
1830 | | JIC_MMR6 = 1815, |
1831 | | JR = 1816, |
1832 | | JR16_MM = 1817, |
1833 | | JR64 = 1818, |
1834 | | JRADDIUSP = 1819, |
1835 | | JRC16_MM = 1820, |
1836 | | JRC16_MMR6 = 1821, |
1837 | | JRCADDIUSP_MMR6 = 1822, |
1838 | | JR_HB = 1823, |
1839 | | JR_HB64 = 1824, |
1840 | | JR_HB64_R6 = 1825, |
1841 | | JR_HB_R6 = 1826, |
1842 | | JR_MM = 1827, |
1843 | | J_MM = 1828, |
1844 | | Jal16 = 1829, |
1845 | | JalB16 = 1830, |
1846 | | JrRa16 = 1831, |
1847 | | JrcRa16 = 1832, |
1848 | | JrcRx16 = 1833, |
1849 | | JumpLinkReg16 = 1834, |
1850 | | LB = 1835, |
1851 | | LB64 = 1836, |
1852 | | LBE = 1837, |
1853 | | LBE_MM = 1838, |
1854 | | LBU16_MM = 1839, |
1855 | | LBUX = 1840, |
1856 | | LBUX_MM = 1841, |
1857 | | LBU_MMR6 = 1842, |
1858 | | LB_MM = 1843, |
1859 | | LB_MMR6 = 1844, |
1860 | | LBu = 1845, |
1861 | | LBu64 = 1846, |
1862 | | LBuE = 1847, |
1863 | | LBuE_MM = 1848, |
1864 | | LBu_MM = 1849, |
1865 | | LD = 1850, |
1866 | | LDC1 = 1851, |
1867 | | LDC164 = 1852, |
1868 | | LDC1_D64_MMR6 = 1853, |
1869 | | LDC1_MM_D32 = 1854, |
1870 | | LDC1_MM_D64 = 1855, |
1871 | | LDC2 = 1856, |
1872 | | LDC2_MMR6 = 1857, |
1873 | | LDC2_R6 = 1858, |
1874 | | LDC3 = 1859, |
1875 | | LDI_B = 1860, |
1876 | | LDI_D = 1861, |
1877 | | LDI_H = 1862, |
1878 | | LDI_W = 1863, |
1879 | | LDL = 1864, |
1880 | | LDPC = 1865, |
1881 | | LDR = 1866, |
1882 | | LDXC1 = 1867, |
1883 | | LDXC164 = 1868, |
1884 | | LD_B = 1869, |
1885 | | LD_D = 1870, |
1886 | | LD_H = 1871, |
1887 | | LD_W = 1872, |
1888 | | LEA_ADDiu = 1873, |
1889 | | LEA_ADDiu64 = 1874, |
1890 | | LEA_ADDiu_MM = 1875, |
1891 | | LH = 1876, |
1892 | | LH64 = 1877, |
1893 | | LHE = 1878, |
1894 | | LHE_MM = 1879, |
1895 | | LHU16_MM = 1880, |
1896 | | LHX = 1881, |
1897 | | LHX_MM = 1882, |
1898 | | LH_MM = 1883, |
1899 | | LHu = 1884, |
1900 | | LHu64 = 1885, |
1901 | | LHuE = 1886, |
1902 | | LHuE_MM = 1887, |
1903 | | LHu_MM = 1888, |
1904 | | LI16_MM = 1889, |
1905 | | LI16_MMR6 = 1890, |
1906 | | LL = 1891, |
1907 | | LL64 = 1892, |
1908 | | LL64_R6 = 1893, |
1909 | | LLD = 1894, |
1910 | | LLD_R6 = 1895, |
1911 | | LLE = 1896, |
1912 | | LLE_MM = 1897, |
1913 | | LL_MM = 1898, |
1914 | | LL_MMR6 = 1899, |
1915 | | LL_R6 = 1900, |
1916 | | LSA = 1901, |
1917 | | LSA_MMR6 = 1902, |
1918 | | LSA_R6 = 1903, |
1919 | | LUI_MMR6 = 1904, |
1920 | | LUXC1 = 1905, |
1921 | | LUXC164 = 1906, |
1922 | | LUXC1_MM = 1907, |
1923 | | LUi = 1908, |
1924 | | LUi64 = 1909, |
1925 | | LUi_MM = 1910, |
1926 | | LW = 1911, |
1927 | | LW16_MM = 1912, |
1928 | | LW64 = 1913, |
1929 | | LWC1 = 1914, |
1930 | | LWC1_MM = 1915, |
1931 | | LWC2 = 1916, |
1932 | | LWC2_MMR6 = 1917, |
1933 | | LWC2_R6 = 1918, |
1934 | | LWC3 = 1919, |
1935 | | LWDSP = 1920, |
1936 | | LWDSP_MM = 1921, |
1937 | | LWE = 1922, |
1938 | | LWE_MM = 1923, |
1939 | | LWGP_MM = 1924, |
1940 | | LWL = 1925, |
1941 | | LWL64 = 1926, |
1942 | | LWLE = 1927, |
1943 | | LWLE_MM = 1928, |
1944 | | LWL_MM = 1929, |
1945 | | LWM16_MM = 1930, |
1946 | | LWM16_MMR6 = 1931, |
1947 | | LWM32_MM = 1932, |
1948 | | LWPC = 1933, |
1949 | | LWPC_MMR6 = 1934, |
1950 | | LWP_MM = 1935, |
1951 | | LWR = 1936, |
1952 | | LWR64 = 1937, |
1953 | | LWRE = 1938, |
1954 | | LWRE_MM = 1939, |
1955 | | LWR_MM = 1940, |
1956 | | LWSP_MM = 1941, |
1957 | | LWUPC = 1942, |
1958 | | LWU_MM = 1943, |
1959 | | LWX = 1944, |
1960 | | LWXC1 = 1945, |
1961 | | LWXC1_MM = 1946, |
1962 | | LWXS_MM = 1947, |
1963 | | LWX_MM = 1948, |
1964 | | LW_MM = 1949, |
1965 | | LW_MMR6 = 1950, |
1966 | | LWu = 1951, |
1967 | | LbRxRyOffMemX16 = 1952, |
1968 | | LbuRxRyOffMemX16 = 1953, |
1969 | | LhRxRyOffMemX16 = 1954, |
1970 | | LhuRxRyOffMemX16 = 1955, |
1971 | | LiRxImm16 = 1956, |
1972 | | LiRxImmAlignX16 = 1957, |
1973 | | LiRxImmX16 = 1958, |
1974 | | LwRxPcTcp16 = 1959, |
1975 | | LwRxPcTcpX16 = 1960, |
1976 | | LwRxRyOffMemX16 = 1961, |
1977 | | LwRxSpImmX16 = 1962, |
1978 | | MADD = 1963, |
1979 | | MADDF_D = 1964, |
1980 | | MADDF_D_MMR6 = 1965, |
1981 | | MADDF_S = 1966, |
1982 | | MADDF_S_MMR6 = 1967, |
1983 | | MADDR_Q_H = 1968, |
1984 | | MADDR_Q_W = 1969, |
1985 | | MADDU = 1970, |
1986 | | MADDU_DSP = 1971, |
1987 | | MADDU_DSP_MM = 1972, |
1988 | | MADDU_MM = 1973, |
1989 | | MADDV_B = 1974, |
1990 | | MADDV_D = 1975, |
1991 | | MADDV_H = 1976, |
1992 | | MADDV_W = 1977, |
1993 | | MADD_D32 = 1978, |
1994 | | MADD_D32_MM = 1979, |
1995 | | MADD_D64 = 1980, |
1996 | | MADD_DSP = 1981, |
1997 | | MADD_DSP_MM = 1982, |
1998 | | MADD_MM = 1983, |
1999 | | MADD_Q_H = 1984, |
2000 | | MADD_Q_W = 1985, |
2001 | | MADD_S = 1986, |
2002 | | MADD_S_MM = 1987, |
2003 | | MAQ_SA_W_PHL = 1988, |
2004 | | MAQ_SA_W_PHL_MM = 1989, |
2005 | | MAQ_SA_W_PHR = 1990, |
2006 | | MAQ_SA_W_PHR_MM = 1991, |
2007 | | MAQ_S_W_PHL = 1992, |
2008 | | MAQ_S_W_PHL_MM = 1993, |
2009 | | MAQ_S_W_PHR = 1994, |
2010 | | MAQ_S_W_PHR_MM = 1995, |
2011 | | MAXA_D = 1996, |
2012 | | MAXA_D_MMR6 = 1997, |
2013 | | MAXA_S = 1998, |
2014 | | MAXA_S_MMR6 = 1999, |
2015 | | MAXI_S_B = 2000, |
2016 | | MAXI_S_D = 2001, |
2017 | | MAXI_S_H = 2002, |
2018 | | MAXI_S_W = 2003, |
2019 | | MAXI_U_B = 2004, |
2020 | | MAXI_U_D = 2005, |
2021 | | MAXI_U_H = 2006, |
2022 | | MAXI_U_W = 2007, |
2023 | | MAX_A_B = 2008, |
2024 | | MAX_A_D = 2009, |
2025 | | MAX_A_H = 2010, |
2026 | | MAX_A_W = 2011, |
2027 | | MAX_D = 2012, |
2028 | | MAX_D_MMR6 = 2013, |
2029 | | MAX_S = 2014, |
2030 | | MAX_S_B = 2015, |
2031 | | MAX_S_D = 2016, |
2032 | | MAX_S_H = 2017, |
2033 | | MAX_S_MMR6 = 2018, |
2034 | | MAX_S_W = 2019, |
2035 | | MAX_U_B = 2020, |
2036 | | MAX_U_D = 2021, |
2037 | | MAX_U_H = 2022, |
2038 | | MAX_U_W = 2023, |
2039 | | MFC0 = 2024, |
2040 | | MFC0_MMR6 = 2025, |
2041 | | MFC1 = 2026, |
2042 | | MFC1_D64 = 2027, |
2043 | | MFC1_MM = 2028, |
2044 | | MFC1_MMR6 = 2029, |
2045 | | MFC2 = 2030, |
2046 | | MFC2_MMR6 = 2031, |
2047 | | MFGC0 = 2032, |
2048 | | MFGC0_MM = 2033, |
2049 | | MFHC0_MMR6 = 2034, |
2050 | | MFHC1_D32 = 2035, |
2051 | | MFHC1_D32_MM = 2036, |
2052 | | MFHC1_D64 = 2037, |
2053 | | MFHC1_D64_MM = 2038, |
2054 | | MFHC2_MMR6 = 2039, |
2055 | | MFHGC0 = 2040, |
2056 | | MFHGC0_MM = 2041, |
2057 | | MFHI = 2042, |
2058 | | MFHI16_MM = 2043, |
2059 | | MFHI64 = 2044, |
2060 | | MFHI_DSP = 2045, |
2061 | | MFHI_DSP_MM = 2046, |
2062 | | MFHI_MM = 2047, |
2063 | | MFLO = 2048, |
2064 | | MFLO16_MM = 2049, |
2065 | | MFLO64 = 2050, |
2066 | | MFLO_DSP = 2051, |
2067 | | MFLO_DSP_MM = 2052, |
2068 | | MFLO_MM = 2053, |
2069 | | MFTR = 2054, |
2070 | | MINA_D = 2055, |
2071 | | MINA_D_MMR6 = 2056, |
2072 | | MINA_S = 2057, |
2073 | | MINA_S_MMR6 = 2058, |
2074 | | MINI_S_B = 2059, |
2075 | | MINI_S_D = 2060, |
2076 | | MINI_S_H = 2061, |
2077 | | MINI_S_W = 2062, |
2078 | | MINI_U_B = 2063, |
2079 | | MINI_U_D = 2064, |
2080 | | MINI_U_H = 2065, |
2081 | | MINI_U_W = 2066, |
2082 | | MIN_A_B = 2067, |
2083 | | MIN_A_D = 2068, |
2084 | | MIN_A_H = 2069, |
2085 | | MIN_A_W = 2070, |
2086 | | MIN_D = 2071, |
2087 | | MIN_D_MMR6 = 2072, |
2088 | | MIN_S = 2073, |
2089 | | MIN_S_B = 2074, |
2090 | | MIN_S_D = 2075, |
2091 | | MIN_S_H = 2076, |
2092 | | MIN_S_MMR6 = 2077, |
2093 | | MIN_S_W = 2078, |
2094 | | MIN_U_B = 2079, |
2095 | | MIN_U_D = 2080, |
2096 | | MIN_U_H = 2081, |
2097 | | MIN_U_W = 2082, |
2098 | | MOD = 2083, |
2099 | | MODSUB = 2084, |
2100 | | MODSUB_MM = 2085, |
2101 | | MODU = 2086, |
2102 | | MODU_MMR6 = 2087, |
2103 | | MOD_MMR6 = 2088, |
2104 | | MOD_S_B = 2089, |
2105 | | MOD_S_D = 2090, |
2106 | | MOD_S_H = 2091, |
2107 | | MOD_S_W = 2092, |
2108 | | MOD_U_B = 2093, |
2109 | | MOD_U_D = 2094, |
2110 | | MOD_U_H = 2095, |
2111 | | MOD_U_W = 2096, |
2112 | | MOVE16_MM = 2097, |
2113 | | MOVE16_MMR6 = 2098, |
2114 | | MOVEP_MM = 2099, |
2115 | | MOVEP_MMR6 = 2100, |
2116 | | MOVE_V = 2101, |
2117 | | MOVF_D32 = 2102, |
2118 | | MOVF_D32_MM = 2103, |
2119 | | MOVF_D64 = 2104, |
2120 | | MOVF_I = 2105, |
2121 | | MOVF_I64 = 2106, |
2122 | | MOVF_I_MM = 2107, |
2123 | | MOVF_S = 2108, |
2124 | | MOVF_S_MM = 2109, |
2125 | | MOVN_I64_D64 = 2110, |
2126 | | MOVN_I64_I = 2111, |
2127 | | MOVN_I64_I64 = 2112, |
2128 | | MOVN_I64_S = 2113, |
2129 | | MOVN_I_D32 = 2114, |
2130 | | MOVN_I_D32_MM = 2115, |
2131 | | MOVN_I_D64 = 2116, |
2132 | | MOVN_I_I = 2117, |
2133 | | MOVN_I_I64 = 2118, |
2134 | | MOVN_I_MM = 2119, |
2135 | | MOVN_I_S = 2120, |
2136 | | MOVN_I_S_MM = 2121, |
2137 | | MOVT_D32 = 2122, |
2138 | | MOVT_D32_MM = 2123, |
2139 | | MOVT_D64 = 2124, |
2140 | | MOVT_I = 2125, |
2141 | | MOVT_I64 = 2126, |
2142 | | MOVT_I_MM = 2127, |
2143 | | MOVT_S = 2128, |
2144 | | MOVT_S_MM = 2129, |
2145 | | MOVZ_I64_D64 = 2130, |
2146 | | MOVZ_I64_I = 2131, |
2147 | | MOVZ_I64_I64 = 2132, |
2148 | | MOVZ_I64_S = 2133, |
2149 | | MOVZ_I_D32 = 2134, |
2150 | | MOVZ_I_D32_MM = 2135, |
2151 | | MOVZ_I_D64 = 2136, |
2152 | | MOVZ_I_I = 2137, |
2153 | | MOVZ_I_I64 = 2138, |
2154 | | MOVZ_I_MM = 2139, |
2155 | | MOVZ_I_S = 2140, |
2156 | | MOVZ_I_S_MM = 2141, |
2157 | | MSUB = 2142, |
2158 | | MSUBF_D = 2143, |
2159 | | MSUBF_D_MMR6 = 2144, |
2160 | | MSUBF_S = 2145, |
2161 | | MSUBF_S_MMR6 = 2146, |
2162 | | MSUBR_Q_H = 2147, |
2163 | | MSUBR_Q_W = 2148, |
2164 | | MSUBU = 2149, |
2165 | | MSUBU_DSP = 2150, |
2166 | | MSUBU_DSP_MM = 2151, |
2167 | | MSUBU_MM = 2152, |
2168 | | MSUBV_B = 2153, |
2169 | | MSUBV_D = 2154, |
2170 | | MSUBV_H = 2155, |
2171 | | MSUBV_W = 2156, |
2172 | | MSUB_D32 = 2157, |
2173 | | MSUB_D32_MM = 2158, |
2174 | | MSUB_D64 = 2159, |
2175 | | MSUB_DSP = 2160, |
2176 | | MSUB_DSP_MM = 2161, |
2177 | | MSUB_MM = 2162, |
2178 | | MSUB_Q_H = 2163, |
2179 | | MSUB_Q_W = 2164, |
2180 | | MSUB_S = 2165, |
2181 | | MSUB_S_MM = 2166, |
2182 | | MTC0 = 2167, |
2183 | | MTC0_MMR6 = 2168, |
2184 | | MTC1 = 2169, |
2185 | | MTC1_D64 = 2170, |
2186 | | MTC1_D64_MM = 2171, |
2187 | | MTC1_MM = 2172, |
2188 | | MTC1_MMR6 = 2173, |
2189 | | MTC2 = 2174, |
2190 | | MTC2_MMR6 = 2175, |
2191 | | MTGC0 = 2176, |
2192 | | MTGC0_MM = 2177, |
2193 | | MTHC0_MMR6 = 2178, |
2194 | | MTHC1_D32 = 2179, |
2195 | | MTHC1_D32_MM = 2180, |
2196 | | MTHC1_D64 = 2181, |
2197 | | MTHC1_D64_MM = 2182, |
2198 | | MTHC2_MMR6 = 2183, |
2199 | | MTHGC0 = 2184, |
2200 | | MTHGC0_MM = 2185, |
2201 | | MTHI = 2186, |
2202 | | MTHI64 = 2187, |
2203 | | MTHI_DSP = 2188, |
2204 | | MTHI_DSP_MM = 2189, |
2205 | | MTHI_MM = 2190, |
2206 | | MTHLIP = 2191, |
2207 | | MTHLIP_MM = 2192, |
2208 | | MTLO = 2193, |
2209 | | MTLO64 = 2194, |
2210 | | MTLO_DSP = 2195, |
2211 | | MTLO_DSP_MM = 2196, |
2212 | | MTLO_MM = 2197, |
2213 | | MTM0 = 2198, |
2214 | | MTM1 = 2199, |
2215 | | MTM2 = 2200, |
2216 | | MTP0 = 2201, |
2217 | | MTP1 = 2202, |
2218 | | MTP2 = 2203, |
2219 | | MTTR = 2204, |
2220 | | MUH = 2205, |
2221 | | MUHU = 2206, |
2222 | | MUHU_MMR6 = 2207, |
2223 | | MUH_MMR6 = 2208, |
2224 | | MUL = 2209, |
2225 | | MULEQ_S_W_PHL = 2210, |
2226 | | MULEQ_S_W_PHL_MM = 2211, |
2227 | | MULEQ_S_W_PHR = 2212, |
2228 | | MULEQ_S_W_PHR_MM = 2213, |
2229 | | MULEU_S_PH_QBL = 2214, |
2230 | | MULEU_S_PH_QBL_MM = 2215, |
2231 | | MULEU_S_PH_QBR = 2216, |
2232 | | MULEU_S_PH_QBR_MM = 2217, |
2233 | | MULQ_RS_PH = 2218, |
2234 | | MULQ_RS_PH_MM = 2219, |
2235 | | MULQ_RS_W = 2220, |
2236 | | MULQ_RS_W_MMR2 = 2221, |
2237 | | MULQ_S_PH = 2222, |
2238 | | MULQ_S_PH_MMR2 = 2223, |
2239 | | MULQ_S_W = 2224, |
2240 | | MULQ_S_W_MMR2 = 2225, |
2241 | | MULR_PS64 = 2226, |
2242 | | MULR_Q_H = 2227, |
2243 | | MULR_Q_W = 2228, |
2244 | | MULSAQ_S_W_PH = 2229, |
2245 | | MULSAQ_S_W_PH_MM = 2230, |
2246 | | MULSA_W_PH = 2231, |
2247 | | MULSA_W_PH_MMR2 = 2232, |
2248 | | MULT = 2233, |
2249 | | MULTU_DSP = 2234, |
2250 | | MULTU_DSP_MM = 2235, |
2251 | | MULT_DSP = 2236, |
2252 | | MULT_DSP_MM = 2237, |
2253 | | MULT_MM = 2238, |
2254 | | MULTu = 2239, |
2255 | | MULTu_MM = 2240, |
2256 | | MULU = 2241, |
2257 | | MULU_MMR6 = 2242, |
2258 | | MULV_B = 2243, |
2259 | | MULV_D = 2244, |
2260 | | MULV_H = 2245, |
2261 | | MULV_W = 2246, |
2262 | | MUL_MM = 2247, |
2263 | | MUL_MMR6 = 2248, |
2264 | | MUL_PH = 2249, |
2265 | | MUL_PH_MMR2 = 2250, |
2266 | | MUL_Q_H = 2251, |
2267 | | MUL_Q_W = 2252, |
2268 | | MUL_R6 = 2253, |
2269 | | MUL_S_PH = 2254, |
2270 | | MUL_S_PH_MMR2 = 2255, |
2271 | | Mfhi16 = 2256, |
2272 | | Mflo16 = 2257, |
2273 | | Move32R16 = 2258, |
2274 | | MoveR3216 = 2259, |
2275 | | NLOC_B = 2260, |
2276 | | NLOC_D = 2261, |
2277 | | NLOC_H = 2262, |
2278 | | NLOC_W = 2263, |
2279 | | NLZC_B = 2264, |
2280 | | NLZC_D = 2265, |
2281 | | NLZC_H = 2266, |
2282 | | NLZC_W = 2267, |
2283 | | NMADD_D32 = 2268, |
2284 | | NMADD_D32_MM = 2269, |
2285 | | NMADD_D64 = 2270, |
2286 | | NMADD_S = 2271, |
2287 | | NMADD_S_MM = 2272, |
2288 | | NMSUB_D32 = 2273, |
2289 | | NMSUB_D32_MM = 2274, |
2290 | | NMSUB_D64 = 2275, |
2291 | | NMSUB_S = 2276, |
2292 | | NMSUB_S_MM = 2277, |
2293 | | NOR = 2278, |
2294 | | NOR64 = 2279, |
2295 | | NORI_B = 2280, |
2296 | | NOR_MM = 2281, |
2297 | | NOR_MMR6 = 2282, |
2298 | | NOR_V = 2283, |
2299 | | NOT16_MM = 2284, |
2300 | | NOT16_MMR6 = 2285, |
2301 | | NegRxRy16 = 2286, |
2302 | | NotRxRy16 = 2287, |
2303 | | OR = 2288, |
2304 | | OR16_MM = 2289, |
2305 | | OR16_MMR6 = 2290, |
2306 | | OR64 = 2291, |
2307 | | ORI_B = 2292, |
2308 | | ORI_MMR6 = 2293, |
2309 | | OR_MM = 2294, |
2310 | | OR_MMR6 = 2295, |
2311 | | OR_V = 2296, |
2312 | | ORi = 2297, |
2313 | | ORi64 = 2298, |
2314 | | ORi_MM = 2299, |
2315 | | OrRxRxRy16 = 2300, |
2316 | | PACKRL_PH = 2301, |
2317 | | PACKRL_PH_MM = 2302, |
2318 | | PAUSE = 2303, |
2319 | | PAUSE_MM = 2304, |
2320 | | PAUSE_MMR6 = 2305, |
2321 | | PCKEV_B = 2306, |
2322 | | PCKEV_D = 2307, |
2323 | | PCKEV_H = 2308, |
2324 | | PCKEV_W = 2309, |
2325 | | PCKOD_B = 2310, |
2326 | | PCKOD_D = 2311, |
2327 | | PCKOD_H = 2312, |
2328 | | PCKOD_W = 2313, |
2329 | | PCNT_B = 2314, |
2330 | | PCNT_D = 2315, |
2331 | | PCNT_H = 2316, |
2332 | | PCNT_W = 2317, |
2333 | | PICK_PH = 2318, |
2334 | | PICK_PH_MM = 2319, |
2335 | | PICK_QB = 2320, |
2336 | | PICK_QB_MM = 2321, |
2337 | | PLL_PS64 = 2322, |
2338 | | PLU_PS64 = 2323, |
2339 | | POP = 2324, |
2340 | | PRECEQU_PH_QBL = 2325, |
2341 | | PRECEQU_PH_QBLA = 2326, |
2342 | | PRECEQU_PH_QBLA_MM = 2327, |
2343 | | PRECEQU_PH_QBL_MM = 2328, |
2344 | | PRECEQU_PH_QBR = 2329, |
2345 | | PRECEQU_PH_QBRA = 2330, |
2346 | | PRECEQU_PH_QBRA_MM = 2331, |
2347 | | PRECEQU_PH_QBR_MM = 2332, |
2348 | | PRECEQ_W_PHL = 2333, |
2349 | | PRECEQ_W_PHL_MM = 2334, |
2350 | | PRECEQ_W_PHR = 2335, |
2351 | | PRECEQ_W_PHR_MM = 2336, |
2352 | | PRECEU_PH_QBL = 2337, |
2353 | | PRECEU_PH_QBLA = 2338, |
2354 | | PRECEU_PH_QBLA_MM = 2339, |
2355 | | PRECEU_PH_QBL_MM = 2340, |
2356 | | PRECEU_PH_QBR = 2341, |
2357 | | PRECEU_PH_QBRA = 2342, |
2358 | | PRECEU_PH_QBRA_MM = 2343, |
2359 | | PRECEU_PH_QBR_MM = 2344, |
2360 | | PRECRQU_S_QB_PH = 2345, |
2361 | | PRECRQU_S_QB_PH_MM = 2346, |
2362 | | PRECRQ_PH_W = 2347, |
2363 | | PRECRQ_PH_W_MM = 2348, |
2364 | | PRECRQ_QB_PH = 2349, |
2365 | | PRECRQ_QB_PH_MM = 2350, |
2366 | | PRECRQ_RS_PH_W = 2351, |
2367 | | PRECRQ_RS_PH_W_MM = 2352, |
2368 | | PRECR_QB_PH = 2353, |
2369 | | PRECR_QB_PH_MMR2 = 2354, |
2370 | | PRECR_SRA_PH_W = 2355, |
2371 | | PRECR_SRA_PH_W_MMR2 = 2356, |
2372 | | PRECR_SRA_R_PH_W = 2357, |
2373 | | PRECR_SRA_R_PH_W_MMR2 = 2358, |
2374 | | PREF = 2359, |
2375 | | PREFE = 2360, |
2376 | | PREFE_MM = 2361, |
2377 | | PREFX_MM = 2362, |
2378 | | PREF_MM = 2363, |
2379 | | PREF_MMR6 = 2364, |
2380 | | PREF_R6 = 2365, |
2381 | | PREPEND = 2366, |
2382 | | PREPEND_MMR2 = 2367, |
2383 | | PUL_PS64 = 2368, |
2384 | | PUU_PS64 = 2369, |
2385 | | RADDU_W_QB = 2370, |
2386 | | RADDU_W_QB_MM = 2371, |
2387 | | RDDSP = 2372, |
2388 | | RDDSP_MM = 2373, |
2389 | | RDHWR = 2374, |
2390 | | RDHWR64 = 2375, |
2391 | | RDHWR_MM = 2376, |
2392 | | RDHWR_MMR6 = 2377, |
2393 | | RDPGPR_MMR6 = 2378, |
2394 | | RECIP_D32 = 2379, |
2395 | | RECIP_D32_MM = 2380, |
2396 | | RECIP_D64 = 2381, |
2397 | | RECIP_D64_MM = 2382, |
2398 | | RECIP_S = 2383, |
2399 | | RECIP_S_MM = 2384, |
2400 | | REPLV_PH = 2385, |
2401 | | REPLV_PH_MM = 2386, |
2402 | | REPLV_QB = 2387, |
2403 | | REPLV_QB_MM = 2388, |
2404 | | REPL_PH = 2389, |
2405 | | REPL_PH_MM = 2390, |
2406 | | REPL_QB = 2391, |
2407 | | REPL_QB_MM = 2392, |
2408 | | RINT_D = 2393, |
2409 | | RINT_D_MMR6 = 2394, |
2410 | | RINT_S = 2395, |
2411 | | RINT_S_MMR6 = 2396, |
2412 | | ROTR = 2397, |
2413 | | ROTRV = 2398, |
2414 | | ROTRV_MM = 2399, |
2415 | | ROTR_MM = 2400, |
2416 | | ROUND_L_D64 = 2401, |
2417 | | ROUND_L_D_MMR6 = 2402, |
2418 | | ROUND_L_S = 2403, |
2419 | | ROUND_L_S_MMR6 = 2404, |
2420 | | ROUND_W_D32 = 2405, |
2421 | | ROUND_W_D64 = 2406, |
2422 | | ROUND_W_D_MMR6 = 2407, |
2423 | | ROUND_W_MM = 2408, |
2424 | | ROUND_W_S = 2409, |
2425 | | ROUND_W_S_MM = 2410, |
2426 | | ROUND_W_S_MMR6 = 2411, |
2427 | | RSQRT_D32 = 2412, |
2428 | | RSQRT_D32_MM = 2413, |
2429 | | RSQRT_D64 = 2414, |
2430 | | RSQRT_D64_MM = 2415, |
2431 | | RSQRT_S = 2416, |
2432 | | RSQRT_S_MM = 2417, |
2433 | | Restore16 = 2418, |
2434 | | RestoreX16 = 2419, |
2435 | | SAA = 2420, |
2436 | | SAAD = 2421, |
2437 | | SAT_S_B = 2422, |
2438 | | SAT_S_D = 2423, |
2439 | | SAT_S_H = 2424, |
2440 | | SAT_S_W = 2425, |
2441 | | SAT_U_B = 2426, |
2442 | | SAT_U_D = 2427, |
2443 | | SAT_U_H = 2428, |
2444 | | SAT_U_W = 2429, |
2445 | | SB = 2430, |
2446 | | SB16_MM = 2431, |
2447 | | SB16_MMR6 = 2432, |
2448 | | SB64 = 2433, |
2449 | | SBE = 2434, |
2450 | | SBE_MM = 2435, |
2451 | | SB_MM = 2436, |
2452 | | SB_MMR6 = 2437, |
2453 | | SC = 2438, |
2454 | | SC64 = 2439, |
2455 | | SC64_R6 = 2440, |
2456 | | SCD = 2441, |
2457 | | SCD_R6 = 2442, |
2458 | | SCE = 2443, |
2459 | | SCE_MM = 2444, |
2460 | | SC_MM = 2445, |
2461 | | SC_MMR6 = 2446, |
2462 | | SC_R6 = 2447, |
2463 | | SD = 2448, |
2464 | | SDBBP = 2449, |
2465 | | SDBBP16_MM = 2450, |
2466 | | SDBBP16_MMR6 = 2451, |
2467 | | SDBBP_MM = 2452, |
2468 | | SDBBP_MMR6 = 2453, |
2469 | | SDBBP_R6 = 2454, |
2470 | | SDC1 = 2455, |
2471 | | SDC164 = 2456, |
2472 | | SDC1_D64_MMR6 = 2457, |
2473 | | SDC1_MM_D32 = 2458, |
2474 | | SDC1_MM_D64 = 2459, |
2475 | | SDC2 = 2460, |
2476 | | SDC2_MMR6 = 2461, |
2477 | | SDC2_R6 = 2462, |
2478 | | SDC3 = 2463, |
2479 | | SDIV = 2464, |
2480 | | SDIV_MM = 2465, |
2481 | | SDL = 2466, |
2482 | | SDR = 2467, |
2483 | | SDXC1 = 2468, |
2484 | | SDXC164 = 2469, |
2485 | | SEB = 2470, |
2486 | | SEB64 = 2471, |
2487 | | SEB_MM = 2472, |
2488 | | SEH = 2473, |
2489 | | SEH64 = 2474, |
2490 | | SEH_MM = 2475, |
2491 | | SELEQZ = 2476, |
2492 | | SELEQZ64 = 2477, |
2493 | | SELEQZ_D = 2478, |
2494 | | SELEQZ_D_MMR6 = 2479, |
2495 | | SELEQZ_MMR6 = 2480, |
2496 | | SELEQZ_S = 2481, |
2497 | | SELEQZ_S_MMR6 = 2482, |
2498 | | SELNEZ = 2483, |
2499 | | SELNEZ64 = 2484, |
2500 | | SELNEZ_D = 2485, |
2501 | | SELNEZ_D_MMR6 = 2486, |
2502 | | SELNEZ_MMR6 = 2487, |
2503 | | SELNEZ_S = 2488, |
2504 | | SELNEZ_S_MMR6 = 2489, |
2505 | | SEL_D = 2490, |
2506 | | SEL_D_MMR6 = 2491, |
2507 | | SEL_S = 2492, |
2508 | | SEL_S_MMR6 = 2493, |
2509 | | SEQ = 2494, |
2510 | | SEQi = 2495, |
2511 | | SH = 2496, |
2512 | | SH16_MM = 2497, |
2513 | | SH16_MMR6 = 2498, |
2514 | | SH64 = 2499, |
2515 | | SHE = 2500, |
2516 | | SHE_MM = 2501, |
2517 | | SHF_B = 2502, |
2518 | | SHF_H = 2503, |
2519 | | SHF_W = 2504, |
2520 | | SHILO = 2505, |
2521 | | SHILOV = 2506, |
2522 | | SHILOV_MM = 2507, |
2523 | | SHILO_MM = 2508, |
2524 | | SHLLV_PH = 2509, |
2525 | | SHLLV_PH_MM = 2510, |
2526 | | SHLLV_QB = 2511, |
2527 | | SHLLV_QB_MM = 2512, |
2528 | | SHLLV_S_PH = 2513, |
2529 | | SHLLV_S_PH_MM = 2514, |
2530 | | SHLLV_S_W = 2515, |
2531 | | SHLLV_S_W_MM = 2516, |
2532 | | SHLL_PH = 2517, |
2533 | | SHLL_PH_MM = 2518, |
2534 | | SHLL_QB = 2519, |
2535 | | SHLL_QB_MM = 2520, |
2536 | | SHLL_S_PH = 2521, |
2537 | | SHLL_S_PH_MM = 2522, |
2538 | | SHLL_S_W = 2523, |
2539 | | SHLL_S_W_MM = 2524, |
2540 | | SHRAV_PH = 2525, |
2541 | | SHRAV_PH_MM = 2526, |
2542 | | SHRAV_QB = 2527, |
2543 | | SHRAV_QB_MMR2 = 2528, |
2544 | | SHRAV_R_PH = 2529, |
2545 | | SHRAV_R_PH_MM = 2530, |
2546 | | SHRAV_R_QB = 2531, |
2547 | | SHRAV_R_QB_MMR2 = 2532, |
2548 | | SHRAV_R_W = 2533, |
2549 | | SHRAV_R_W_MM = 2534, |
2550 | | SHRA_PH = 2535, |
2551 | | SHRA_PH_MM = 2536, |
2552 | | SHRA_QB = 2537, |
2553 | | SHRA_QB_MMR2 = 2538, |
2554 | | SHRA_R_PH = 2539, |
2555 | | SHRA_R_PH_MM = 2540, |
2556 | | SHRA_R_QB = 2541, |
2557 | | SHRA_R_QB_MMR2 = 2542, |
2558 | | SHRA_R_W = 2543, |
2559 | | SHRA_R_W_MM = 2544, |
2560 | | SHRLV_PH = 2545, |
2561 | | SHRLV_PH_MMR2 = 2546, |
2562 | | SHRLV_QB = 2547, |
2563 | | SHRLV_QB_MM = 2548, |
2564 | | SHRL_PH = 2549, |
2565 | | SHRL_PH_MMR2 = 2550, |
2566 | | SHRL_QB = 2551, |
2567 | | SHRL_QB_MM = 2552, |
2568 | | SH_MM = 2553, |
2569 | | SH_MMR6 = 2554, |
2570 | | SIGRIE = 2555, |
2571 | | SIGRIE_MMR6 = 2556, |
2572 | | SLDI_B = 2557, |
2573 | | SLDI_D = 2558, |
2574 | | SLDI_H = 2559, |
2575 | | SLDI_W = 2560, |
2576 | | SLD_B = 2561, |
2577 | | SLD_D = 2562, |
2578 | | SLD_H = 2563, |
2579 | | SLD_W = 2564, |
2580 | | SLL = 2565, |
2581 | | SLL16_MM = 2566, |
2582 | | SLL16_MMR6 = 2567, |
2583 | | SLL64_32 = 2568, |
2584 | | SLL64_64 = 2569, |
2585 | | SLLI_B = 2570, |
2586 | | SLLI_D = 2571, |
2587 | | SLLI_H = 2572, |
2588 | | SLLI_W = 2573, |
2589 | | SLLV = 2574, |
2590 | | SLLV_MM = 2575, |
2591 | | SLL_B = 2576, |
2592 | | SLL_D = 2577, |
2593 | | SLL_H = 2578, |
2594 | | SLL_MM = 2579, |
2595 | | SLL_MMR6 = 2580, |
2596 | | SLL_W = 2581, |
2597 | | SLT = 2582, |
2598 | | SLT64 = 2583, |
2599 | | SLT_MM = 2584, |
2600 | | SLTi = 2585, |
2601 | | SLTi64 = 2586, |
2602 | | SLTi_MM = 2587, |
2603 | | SLTiu = 2588, |
2604 | | SLTiu64 = 2589, |
2605 | | SLTiu_MM = 2590, |
2606 | | SLTu = 2591, |
2607 | | SLTu64 = 2592, |
2608 | | SLTu_MM = 2593, |
2609 | | SNE = 2594, |
2610 | | SNEi = 2595, |
2611 | | SPLATI_B = 2596, |
2612 | | SPLATI_D = 2597, |
2613 | | SPLATI_H = 2598, |
2614 | | SPLATI_W = 2599, |
2615 | | SPLAT_B = 2600, |
2616 | | SPLAT_D = 2601, |
2617 | | SPLAT_H = 2602, |
2618 | | SPLAT_W = 2603, |
2619 | | SRA = 2604, |
2620 | | SRAI_B = 2605, |
2621 | | SRAI_D = 2606, |
2622 | | SRAI_H = 2607, |
2623 | | SRAI_W = 2608, |
2624 | | SRARI_B = 2609, |
2625 | | SRARI_D = 2610, |
2626 | | SRARI_H = 2611, |
2627 | | SRARI_W = 2612, |
2628 | | SRAR_B = 2613, |
2629 | | SRAR_D = 2614, |
2630 | | SRAR_H = 2615, |
2631 | | SRAR_W = 2616, |
2632 | | SRAV = 2617, |
2633 | | SRAV_MM = 2618, |
2634 | | SRA_B = 2619, |
2635 | | SRA_D = 2620, |
2636 | | SRA_H = 2621, |
2637 | | SRA_MM = 2622, |
2638 | | SRA_W = 2623, |
2639 | | SRL = 2624, |
2640 | | SRL16_MM = 2625, |
2641 | | SRL16_MMR6 = 2626, |
2642 | | SRLI_B = 2627, |
2643 | | SRLI_D = 2628, |
2644 | | SRLI_H = 2629, |
2645 | | SRLI_W = 2630, |
2646 | | SRLRI_B = 2631, |
2647 | | SRLRI_D = 2632, |
2648 | | SRLRI_H = 2633, |
2649 | | SRLRI_W = 2634, |
2650 | | SRLR_B = 2635, |
2651 | | SRLR_D = 2636, |
2652 | | SRLR_H = 2637, |
2653 | | SRLR_W = 2638, |
2654 | | SRLV = 2639, |
2655 | | SRLV_MM = 2640, |
2656 | | SRL_B = 2641, |
2657 | | SRL_D = 2642, |
2658 | | SRL_H = 2643, |
2659 | | SRL_MM = 2644, |
2660 | | SRL_W = 2645, |
2661 | | SSNOP = 2646, |
2662 | | SSNOP_MM = 2647, |
2663 | | SSNOP_MMR6 = 2648, |
2664 | | ST_B = 2649, |
2665 | | ST_D = 2650, |
2666 | | ST_H = 2651, |
2667 | | ST_W = 2652, |
2668 | | SUB = 2653, |
2669 | | SUBQH_PH = 2654, |
2670 | | SUBQH_PH_MMR2 = 2655, |
2671 | | SUBQH_R_PH = 2656, |
2672 | | SUBQH_R_PH_MMR2 = 2657, |
2673 | | SUBQH_R_W = 2658, |
2674 | | SUBQH_R_W_MMR2 = 2659, |
2675 | | SUBQH_W = 2660, |
2676 | | SUBQH_W_MMR2 = 2661, |
2677 | | SUBQ_PH = 2662, |
2678 | | SUBQ_PH_MM = 2663, |
2679 | | SUBQ_S_PH = 2664, |
2680 | | SUBQ_S_PH_MM = 2665, |
2681 | | SUBQ_S_W = 2666, |
2682 | | SUBQ_S_W_MM = 2667, |
2683 | | SUBSUS_U_B = 2668, |
2684 | | SUBSUS_U_D = 2669, |
2685 | | SUBSUS_U_H = 2670, |
2686 | | SUBSUS_U_W = 2671, |
2687 | | SUBSUU_S_B = 2672, |
2688 | | SUBSUU_S_D = 2673, |
2689 | | SUBSUU_S_H = 2674, |
2690 | | SUBSUU_S_W = 2675, |
2691 | | SUBS_S_B = 2676, |
2692 | | SUBS_S_D = 2677, |
2693 | | SUBS_S_H = 2678, |
2694 | | SUBS_S_W = 2679, |
2695 | | SUBS_U_B = 2680, |
2696 | | SUBS_U_D = 2681, |
2697 | | SUBS_U_H = 2682, |
2698 | | SUBS_U_W = 2683, |
2699 | | SUBU16_MM = 2684, |
2700 | | SUBU16_MMR6 = 2685, |
2701 | | SUBUH_QB = 2686, |
2702 | | SUBUH_QB_MMR2 = 2687, |
2703 | | SUBUH_R_QB = 2688, |
2704 | | SUBUH_R_QB_MMR2 = 2689, |
2705 | | SUBU_MMR6 = 2690, |
2706 | | SUBU_PH = 2691, |
2707 | | SUBU_PH_MMR2 = 2692, |
2708 | | SUBU_QB = 2693, |
2709 | | SUBU_QB_MM = 2694, |
2710 | | SUBU_S_PH = 2695, |
2711 | | SUBU_S_PH_MMR2 = 2696, |
2712 | | SUBU_S_QB = 2697, |
2713 | | SUBU_S_QB_MM = 2698, |
2714 | | SUBVI_B = 2699, |
2715 | | SUBVI_D = 2700, |
2716 | | SUBVI_H = 2701, |
2717 | | SUBVI_W = 2702, |
2718 | | SUBV_B = 2703, |
2719 | | SUBV_D = 2704, |
2720 | | SUBV_H = 2705, |
2721 | | SUBV_W = 2706, |
2722 | | SUB_MM = 2707, |
2723 | | SUB_MMR6 = 2708, |
2724 | | SUBu = 2709, |
2725 | | SUBu_MM = 2710, |
2726 | | SUXC1 = 2711, |
2727 | | SUXC164 = 2712, |
2728 | | SUXC1_MM = 2713, |
2729 | | SW = 2714, |
2730 | | SW16_MM = 2715, |
2731 | | SW16_MMR6 = 2716, |
2732 | | SW64 = 2717, |
2733 | | SWC1 = 2718, |
2734 | | SWC1_MM = 2719, |
2735 | | SWC2 = 2720, |
2736 | | SWC2_MMR6 = 2721, |
2737 | | SWC2_R6 = 2722, |
2738 | | SWC3 = 2723, |
2739 | | SWDSP = 2724, |
2740 | | SWDSP_MM = 2725, |
2741 | | SWE = 2726, |
2742 | | SWE_MM = 2727, |
2743 | | SWL = 2728, |
2744 | | SWL64 = 2729, |
2745 | | SWLE = 2730, |
2746 | | SWLE_MM = 2731, |
2747 | | SWL_MM = 2732, |
2748 | | SWM16_MM = 2733, |
2749 | | SWM16_MMR6 = 2734, |
2750 | | SWM32_MM = 2735, |
2751 | | SWP_MM = 2736, |
2752 | | SWR = 2737, |
2753 | | SWR64 = 2738, |
2754 | | SWRE = 2739, |
2755 | | SWRE_MM = 2740, |
2756 | | SWR_MM = 2741, |
2757 | | SWSP_MM = 2742, |
2758 | | SWSP_MMR6 = 2743, |
2759 | | SWXC1 = 2744, |
2760 | | SWXC1_MM = 2745, |
2761 | | SW_MM = 2746, |
2762 | | SW_MMR6 = 2747, |
2763 | | SYNC = 2748, |
2764 | | SYNCI = 2749, |
2765 | | SYNCI_MM = 2750, |
2766 | | SYNCI_MMR6 = 2751, |
2767 | | SYNC_MM = 2752, |
2768 | | SYNC_MMR6 = 2753, |
2769 | | SYSCALL = 2754, |
2770 | | SYSCALL_MM = 2755, |
2771 | | Save16 = 2756, |
2772 | | SaveX16 = 2757, |
2773 | | SbRxRyOffMemX16 = 2758, |
2774 | | SebRx16 = 2759, |
2775 | | SehRx16 = 2760, |
2776 | | ShRxRyOffMemX16 = 2761, |
2777 | | SllX16 = 2762, |
2778 | | SllvRxRy16 = 2763, |
2779 | | SltRxRy16 = 2764, |
2780 | | SltiRxImm16 = 2765, |
2781 | | SltiRxImmX16 = 2766, |
2782 | | SltiuRxImm16 = 2767, |
2783 | | SltiuRxImmX16 = 2768, |
2784 | | SltuRxRy16 = 2769, |
2785 | | SraX16 = 2770, |
2786 | | SravRxRy16 = 2771, |
2787 | | SrlX16 = 2772, |
2788 | | SrlvRxRy16 = 2773, |
2789 | | SubuRxRyRz16 = 2774, |
2790 | | SwRxRyOffMemX16 = 2775, |
2791 | | SwRxSpImmX16 = 2776, |
2792 | | TEQ = 2777, |
2793 | | TEQI = 2778, |
2794 | | TEQI_MM = 2779, |
2795 | | TEQ_MM = 2780, |
2796 | | TGE = 2781, |
2797 | | TGEI = 2782, |
2798 | | TGEIU = 2783, |
2799 | | TGEIU_MM = 2784, |
2800 | | TGEI_MM = 2785, |
2801 | | TGEU = 2786, |
2802 | | TGEU_MM = 2787, |
2803 | | TGE_MM = 2788, |
2804 | | TLBGINV = 2789, |
2805 | | TLBGINVF = 2790, |
2806 | | TLBGINVF_MM = 2791, |
2807 | | TLBGINV_MM = 2792, |
2808 | | TLBGP = 2793, |
2809 | | TLBGP_MM = 2794, |
2810 | | TLBGR = 2795, |
2811 | | TLBGR_MM = 2796, |
2812 | | TLBGWI = 2797, |
2813 | | TLBGWI_MM = 2798, |
2814 | | TLBGWR = 2799, |
2815 | | TLBGWR_MM = 2800, |
2816 | | TLBINV = 2801, |
2817 | | TLBINVF = 2802, |
2818 | | TLBINVF_MMR6 = 2803, |
2819 | | TLBINV_MMR6 = 2804, |
2820 | | TLBP = 2805, |
2821 | | TLBP_MM = 2806, |
2822 | | TLBR = 2807, |
2823 | | TLBR_MM = 2808, |
2824 | | TLBWI = 2809, |
2825 | | TLBWI_MM = 2810, |
2826 | | TLBWR = 2811, |
2827 | | TLBWR_MM = 2812, |
2828 | | TLT = 2813, |
2829 | | TLTI = 2814, |
2830 | | TLTIU_MM = 2815, |
2831 | | TLTI_MM = 2816, |
2832 | | TLTU = 2817, |
2833 | | TLTU_MM = 2818, |
2834 | | TLT_MM = 2819, |
2835 | | TNE = 2820, |
2836 | | TNEI = 2821, |
2837 | | TNEI_MM = 2822, |
2838 | | TNE_MM = 2823, |
2839 | | TRUNC_L_D64 = 2824, |
2840 | | TRUNC_L_D_MMR6 = 2825, |
2841 | | TRUNC_L_S = 2826, |
2842 | | TRUNC_L_S_MMR6 = 2827, |
2843 | | TRUNC_W_D32 = 2828, |
2844 | | TRUNC_W_D64 = 2829, |
2845 | | TRUNC_W_D_MMR6 = 2830, |
2846 | | TRUNC_W_MM = 2831, |
2847 | | TRUNC_W_S = 2832, |
2848 | | TRUNC_W_S_MM = 2833, |
2849 | | TRUNC_W_S_MMR6 = 2834, |
2850 | | TTLTIU = 2835, |
2851 | | UDIV = 2836, |
2852 | | UDIV_MM = 2837, |
2853 | | V3MULU = 2838, |
2854 | | VMM0 = 2839, |
2855 | | VMULU = 2840, |
2856 | | VSHF_B = 2841, |
2857 | | VSHF_D = 2842, |
2858 | | VSHF_H = 2843, |
2859 | | VSHF_W = 2844, |
2860 | | WAIT = 2845, |
2861 | | WAIT_MM = 2846, |
2862 | | WAIT_MMR6 = 2847, |
2863 | | WRDSP = 2848, |
2864 | | WRDSP_MM = 2849, |
2865 | | WRPGPR_MMR6 = 2850, |
2866 | | WSBH = 2851, |
2867 | | WSBH_MM = 2852, |
2868 | | WSBH_MMR6 = 2853, |
2869 | | XOR = 2854, |
2870 | | XOR16_MM = 2855, |
2871 | | XOR16_MMR6 = 2856, |
2872 | | XOR64 = 2857, |
2873 | | XORI_B = 2858, |
2874 | | XORI_MMR6 = 2859, |
2875 | | XOR_MM = 2860, |
2876 | | XOR_MMR6 = 2861, |
2877 | | XOR_V = 2862, |
2878 | | XORi = 2863, |
2879 | | XORi64 = 2864, |
2880 | | XORi_MM = 2865, |
2881 | | XorRxRxRy16 = 2866, |
2882 | | YIELD = 2867, |
2883 | | INSTRUCTION_LIST_END = 2868 |
2884 | | }; |
2885 | | |
2886 | | } // end namespace Mips |
2887 | | } // end namespace llvm |
2888 | | #endif // GET_INSTRINFO_ENUM |
2889 | | |
2890 | | #ifdef GET_INSTRINFO_SCHED_ENUM |
2891 | | #undef GET_INSTRINFO_SCHED_ENUM |
2892 | | namespace llvm { |
2893 | | |
2894 | | namespace Mips { |
2895 | | namespace Sched { |
2896 | | enum { |
2897 | | NoInstrModel = 0, |
2898 | | IIPseudo = 1, |
2899 | | II_B = 2, |
2900 | | II_BCCZAL = 3, |
2901 | | II_MTC1 = 4, |
2902 | | II_MFC1 = 5, |
2903 | | II_JALR = 6, |
2904 | | II_JAL = 7, |
2905 | | II_CVT = 8, |
2906 | | II_DMULT = 9, |
2907 | | II_DMULTU = 10, |
2908 | | II_DDIV = 11, |
2909 | | II_DDIVU = 12, |
2910 | | II_IndirectBranchPseudo = 13, |
2911 | | II_MADD = 14, |
2912 | | II_MADDU = 15, |
2913 | | II_MFHI_MFLO = 16, |
2914 | | II_MSUB = 17, |
2915 | | II_MSUBU = 18, |
2916 | | II_MTHI_MTLO = 19, |
2917 | | II_MULT = 20, |
2918 | | II_MULTU = 21, |
2919 | | II_ReturnPseudo = 22, |
2920 | | II_DIV = 23, |
2921 | | II_DIVU = 24, |
2922 | | II_J = 25, |
2923 | | II_JR = 26, |
2924 | | II_TRAP = 27, |
2925 | | II_ADD = 28, |
2926 | | II_ADDIUPC = 29, |
2927 | | II_ADDIU = 30, |
2928 | | II_ADDR_PS = 31, |
2929 | | II_ADDU = 32, |
2930 | | II_ADDI = 33, |
2931 | | II_ALIGN = 34, |
2932 | | II_ALUIPC = 35, |
2933 | | II_AND = 36, |
2934 | | II_ANDI = 37, |
2935 | | II_AUI = 38, |
2936 | | II_AUIPC = 39, |
2937 | | IIM16Alu = 40, |
2938 | | II_BADDU = 41, |
2939 | | II_BC = 42, |
2940 | | II_BALC = 43, |
2941 | | II_BBIT = 44, |
2942 | | II_BC1CCZ = 45, |
2943 | | II_BC1F = 46, |
2944 | | II_BC1FL = 47, |
2945 | | II_BC1T = 48, |
2946 | | II_BC1TL = 49, |
2947 | | II_BC2CCZ = 50, |
2948 | | II_BCC = 51, |
2949 | | II_BCCC = 52, |
2950 | | II_BCCZ = 53, |
2951 | | II_BCCZC = 54, |
2952 | | II_BCCZALS = 55, |
2953 | | II_BITSWAP = 56, |
2954 | | II_BREAK = 57, |
2955 | | II_CACHE = 58, |
2956 | | II_CACHEE = 59, |
2957 | | II_CEIL = 60, |
2958 | | II_CFC1 = 61, |
2959 | | II_CFC2 = 62, |
2960 | | II_INS = 63, |
2961 | | II_CLASS_D = 64, |
2962 | | II_CLASS_S = 65, |
2963 | | II_CLO = 66, |
2964 | | II_CLZ = 67, |
2965 | | II_CMP_CC_D = 68, |
2966 | | II_CMP_CC_S = 69, |
2967 | | II_CRC32B = 70, |
2968 | | II_CRC32CB = 71, |
2969 | | II_CRC32CD = 72, |
2970 | | II_CRC32CH = 73, |
2971 | | II_CRC32CW = 74, |
2972 | | II_CRC32D = 75, |
2973 | | II_CRC32H = 76, |
2974 | | II_CRC32W = 77, |
2975 | | II_CTC1 = 78, |
2976 | | II_CTC2 = 79, |
2977 | | II_C_CC_D = 80, |
2978 | | II_C_CC_S = 81, |
2979 | | II_DADD = 82, |
2980 | | II_DADDI = 83, |
2981 | | II_DADDIU = 84, |
2982 | | II_DADDU = 85, |
2983 | | II_DAHI = 86, |
2984 | | II_DALIGN = 87, |
2985 | | II_DATI = 88, |
2986 | | II_DAUI = 89, |
2987 | | II_DBITSWAP = 90, |
2988 | | II_DCLO = 91, |
2989 | | II_DCLZ = 92, |
2990 | | II_DERET = 93, |
2991 | | II_EXT = 94, |
2992 | | II_DI = 95, |
2993 | | II_DLSA = 96, |
2994 | | II_DMFC0 = 97, |
2995 | | II_DMFC1 = 98, |
2996 | | II_DMFC2 = 99, |
2997 | | II_DMFGC0 = 100, |
2998 | | II_DMOD = 101, |
2999 | | II_DMODU = 102, |
3000 | | II_DMT = 103, |
3001 | | II_DMTC0 = 104, |
3002 | | II_DMTC1 = 105, |
3003 | | II_DMTC2 = 106, |
3004 | | II_DMTGC0 = 107, |
3005 | | II_DMUH = 108, |
3006 | | II_DMUHU = 109, |
3007 | | II_DMUL = 110, |
3008 | | II_POP = 111, |
3009 | | II_DROTR = 112, |
3010 | | II_DROTR32 = 113, |
3011 | | II_DROTRV = 114, |
3012 | | II_DSBH = 115, |
3013 | | II_DSHD = 116, |
3014 | | II_DSLL = 117, |
3015 | | II_DSLL32 = 118, |
3016 | | II_DSLLV = 119, |
3017 | | II_DSRA = 120, |
3018 | | II_DSRA32 = 121, |
3019 | | II_DSRAV = 122, |
3020 | | II_DSRL = 123, |
3021 | | II_DSRL32 = 124, |
3022 | | II_DSRLV = 125, |
3023 | | II_DSUB = 126, |
3024 | | II_DSUBU = 127, |
3025 | | II_DVP = 128, |
3026 | | II_DVPE = 129, |
3027 | | II_EHB = 130, |
3028 | | II_EI = 131, |
3029 | | II_EMT = 132, |
3030 | | II_ERET = 133, |
3031 | | II_ERETNC = 134, |
3032 | | II_EVP = 135, |
3033 | | II_EVPE = 136, |
3034 | | II_ABS = 137, |
3035 | | II_SQRT_D = 138, |
3036 | | II_ADD_D = 139, |
3037 | | II_ADD_PS = 140, |
3038 | | II_ADD_S = 141, |
3039 | | II_DIV_D = 142, |
3040 | | II_DIV_S = 143, |
3041 | | II_FLOOR = 144, |
3042 | | II_MOV_D = 145, |
3043 | | II_MOV_S = 146, |
3044 | | II_MUL_D = 147, |
3045 | | II_MUL_PS = 148, |
3046 | | II_MUL_S = 149, |
3047 | | II_NEG = 150, |
3048 | | II_FORK = 151, |
3049 | | II_SQRT_S = 152, |
3050 | | II_SUB_D = 153, |
3051 | | II_SUB_PS = 154, |
3052 | | II_SUB_S = 155, |
3053 | | II_GINVI = 156, |
3054 | | II_GINVT = 157, |
3055 | | II_HYPCALL = 158, |
3056 | | II_JALR_HB = 159, |
3057 | | II_JALRC = 160, |
3058 | | II_JALRS = 161, |
3059 | | II_JALS = 162, |
3060 | | II_JIALC = 163, |
3061 | | II_JIC = 164, |
3062 | | II_JRADDIUSP = 165, |
3063 | | II_JRC = 166, |
3064 | | II_JR_HB = 167, |
3065 | | II_LB = 168, |
3066 | | II_LBE = 169, |
3067 | | II_LBU = 170, |
3068 | | II_LBUE = 171, |
3069 | | II_LD = 172, |
3070 | | II_LDC1 = 173, |
3071 | | II_LDC2 = 174, |
3072 | | II_LDC3 = 175, |
3073 | | II_LDL = 176, |
3074 | | II_LDPC = 177, |
3075 | | II_LDR = 178, |
3076 | | II_LDXC1 = 179, |
3077 | | II_LH = 180, |
3078 | | II_LHE = 181, |
3079 | | II_LHU = 182, |
3080 | | II_LHUE = 183, |
3081 | | II_LI = 184, |
3082 | | II_LL = 185, |
3083 | | II_LLD = 186, |
3084 | | II_LLE = 187, |
3085 | | II_LSA = 188, |
3086 | | II_LUI = 189, |
3087 | | II_LUXC1 = 190, |
3088 | | II_LW = 191, |
3089 | | II_LWC1 = 192, |
3090 | | II_LWC2 = 193, |
3091 | | II_LWC3 = 194, |
3092 | | II_LWE = 195, |
3093 | | II_LWL = 196, |
3094 | | II_LWLE = 197, |
3095 | | II_LWM = 198, |
3096 | | II_LWPC = 199, |
3097 | | II_LWP = 200, |
3098 | | II_LWR = 201, |
3099 | | II_LWRE = 202, |
3100 | | II_LWUPC = 203, |
3101 | | II_LWU = 204, |
3102 | | II_LWXC1 = 205, |
3103 | | II_LWXS = 206, |
3104 | | II_MADDF_D = 207, |
3105 | | II_MADDF_S = 208, |
3106 | | II_MADD_D = 209, |
3107 | | II_MADD_S = 210, |
3108 | | II_MAX_D = 211, |
3109 | | II_MAXA_D = 212, |
3110 | | II_MAX_S = 213, |
3111 | | II_MAXA_S = 214, |
3112 | | II_MFC0 = 215, |
3113 | | II_MFC2 = 216, |
3114 | | II_MFGC0 = 217, |
3115 | | II_MFHC0 = 218, |
3116 | | II_MFHC1 = 219, |
3117 | | II_MFHGC0 = 220, |
3118 | | II_MFTR = 221, |
3119 | | II_MIN_S = 222, |
3120 | | II_MINA_D = 223, |
3121 | | II_MIN_D = 224, |
3122 | | II_MINA_S = 225, |
3123 | | II_MOD = 226, |
3124 | | II_MODU = 227, |
3125 | | II_MOVE = 228, |
3126 | | II_MOVF_D = 229, |
3127 | | II_MOVF = 230, |
3128 | | II_MOVF_S = 231, |
3129 | | II_MOVN_D = 232, |
3130 | | II_MOVN = 233, |
3131 | | II_MOVN_S = 234, |
3132 | | II_MOVT_D = 235, |
3133 | | II_MOVT = 236, |
3134 | | II_MOVT_S = 237, |
3135 | | II_MOVZ_D = 238, |
3136 | | II_MOVZ = 239, |
3137 | | II_MOVZ_S = 240, |
3138 | | II_MSUBF_D = 241, |
3139 | | II_MSUBF_S = 242, |
3140 | | II_MSUB_D = 243, |
3141 | | II_MSUB_S = 244, |
3142 | | II_MTC0 = 245, |
3143 | | II_MTC2 = 246, |
3144 | | II_MTGC0 = 247, |
3145 | | II_MTHC0 = 248, |
3146 | | II_MTHC1 = 249, |
3147 | | II_MTHGC0 = 250, |
3148 | | II_MTTR = 251, |
3149 | | II_MUH = 252, |
3150 | | II_MUHU = 253, |
3151 | | II_MUL = 254, |
3152 | | II_MULR_PS = 255, |
3153 | | II_MULU = 256, |
3154 | | II_NMADD_D = 257, |
3155 | | II_NMADD_S = 258, |
3156 | | II_NMSUB_D = 259, |
3157 | | II_NMSUB_S = 260, |
3158 | | II_NOR = 261, |
3159 | | II_NOT = 262, |
3160 | | II_OR = 263, |
3161 | | II_ORI = 264, |
3162 | | II_PAUSE = 265, |
3163 | | II_PREF = 266, |
3164 | | II_PREFE = 267, |
3165 | | II_RDHWR = 268, |
3166 | | II_RDPGPR = 269, |
3167 | | II_RECIP_D = 270, |
3168 | | II_RECIP_S = 271, |
3169 | | II_RINT_D = 272, |
3170 | | II_RINT_S = 273, |
3171 | | II_ROTR = 274, |
3172 | | II_ROTRV = 275, |
3173 | | II_ROUND = 276, |
3174 | | II_RSQRT_D = 277, |
3175 | | II_RSQRT_S = 278, |
3176 | | II_RESTORE = 279, |
3177 | | II_SB = 280, |
3178 | | II_SBE = 281, |
3179 | | II_SC = 282, |
3180 | | II_SCD = 283, |
3181 | | II_SCE = 284, |
3182 | | II_SD = 285, |
3183 | | II_SDBBP = 286, |
3184 | | II_SDC1 = 287, |
3185 | | II_SDC2 = 288, |
3186 | | II_SDC3 = 289, |
3187 | | II_SDL = 290, |
3188 | | II_SDR = 291, |
3189 | | II_SDXC1 = 292, |
3190 | | II_SEB = 293, |
3191 | | II_SEH = 294, |
3192 | | II_SELCCZ = 295, |
3193 | | II_SELCCZ_D = 296, |
3194 | | II_SELCCZ_S = 297, |
3195 | | II_SEL_D = 298, |
3196 | | II_SEL_S = 299, |
3197 | | II_SEQ_SNE = 300, |
3198 | | II_SEQI_SNEI = 301, |
3199 | | II_SH = 302, |
3200 | | II_SHE = 303, |
3201 | | II_SIGRIE = 304, |
3202 | | II_SLL = 305, |
3203 | | II_SLLV = 306, |
3204 | | II_SLT_SLTU = 307, |
3205 | | II_SLTI_SLTIU = 308, |
3206 | | II_SRA = 309, |
3207 | | II_SRAV = 310, |
3208 | | II_SRL = 311, |
3209 | | II_SRLV = 312, |
3210 | | II_SSNOP = 313, |
3211 | | II_SUB = 314, |
3212 | | II_SUBU = 315, |
3213 | | II_SUXC1 = 316, |
3214 | | II_SW = 317, |
3215 | | II_SWC1 = 318, |
3216 | | II_SWC2 = 319, |
3217 | | II_SWC3 = 320, |
3218 | | II_SWE = 321, |
3219 | | II_SWL = 322, |
3220 | | II_SWLE = 323, |
3221 | | II_SWM = 324, |
3222 | | II_SWP = 325, |
3223 | | II_SWR = 326, |
3224 | | II_SWRE = 327, |
3225 | | II_SWXC1 = 328, |
3226 | | II_SYNC = 329, |
3227 | | II_SYNCI = 330, |
3228 | | II_SYSCALL = 331, |
3229 | | II_SAVE = 332, |
3230 | | II_TEQ = 333, |
3231 | | II_TEQI = 334, |
3232 | | II_TGE = 335, |
3233 | | II_TGEI = 336, |
3234 | | II_TGEIU = 337, |
3235 | | II_TGEU = 338, |
3236 | | II_TLBGINV = 339, |
3237 | | II_TLBGINVF = 340, |
3238 | | II_TLBGP = 341, |
3239 | | II_TLBGR = 342, |
3240 | | II_TLBGWI = 343, |
3241 | | II_TLBGWR = 344, |
3242 | | II_TLBINV = 345, |
3243 | | II_TLBINVF = 346, |
3244 | | II_TLBP = 347, |
3245 | | II_TLBR = 348, |
3246 | | II_TLBWI = 349, |
3247 | | II_TLBWR = 350, |
3248 | | II_TLT = 351, |
3249 | | II_TLTI = 352, |
3250 | | II_TTLTIU = 353, |
3251 | | II_TLTU = 354, |
3252 | | II_TNE = 355, |
3253 | | II_TNEI = 356, |
3254 | | II_TRUNC = 357, |
3255 | | II_WAIT = 358, |
3256 | | II_WRPGPR = 359, |
3257 | | II_WSBH = 360, |
3258 | | II_XOR = 361, |
3259 | | II_XORI = 362, |
3260 | | II_YIELD = 363, |
3261 | | AND = 364, |
3262 | | LUi = 365, |
3263 | | NOR = 366, |
3264 | | OR = 367, |
3265 | | SLTi_SLTiu = 368, |
3266 | | SUB = 369, |
3267 | | SUBu = 370, |
3268 | | XOR = 371, |
3269 | | SSNOP = 372, |
3270 | | NOP = 373, |
3271 | | B = 374, |
3272 | | BAL = 375, |
3273 | | BAL_BR_BGEZAL_BGEZALL_BLTZAL_BLTZALL = 376, |
3274 | | BEQ_BEQL_BNE_BNEL = 377, |
3275 | | BGEZ_BGEZL_BGTZ_BGTZL_BLEZ_BLEZL_BLTZ_BLTZL = 378, |
3276 | | BREAK = 379, |
3277 | | DERET = 380, |
3278 | | ERET = 381, |
3279 | | ERet_RetRA = 382, |
3280 | | ERETNC = 383, |
3281 | | J_TAILCALL = 384, |
3282 | | JR_TAILCALLREG_TAILCALLREGHB = 385, |
3283 | | JR_HB = 386, |
3284 | | PseudoIndirectBranch_PseudoIndirectHazardBranch = 387, |
3285 | | PseudoReturn = 388, |
3286 | | SDBBP = 389, |
3287 | | SYSCALL = 390, |
3288 | | TEQ = 391, |
3289 | | TEQI = 392, |
3290 | | TGE = 393, |
3291 | | TGEI = 394, |
3292 | | TGEIU = 395, |
3293 | | TGEU = 396, |
3294 | | TLT = 397, |
3295 | | TLTI = 398, |
3296 | | TLTU = 399, |
3297 | | TNE = 400, |
3298 | | TNEI = 401, |
3299 | | TRAP = 402, |
3300 | | TTLTIU = 403, |
3301 | | WAIT = 404, |
3302 | | PAUSE = 405, |
3303 | | JAL = 406, |
3304 | | JALR_JALRHBPseudo_JALRPseudo = 407, |
3305 | | JALR_HB = 408, |
3306 | | JALX = 409, |
3307 | | TLBINV = 410, |
3308 | | TLBINVF = 411, |
3309 | | TLBP = 412, |
3310 | | TLBR = 413, |
3311 | | TLBWI = 414, |
3312 | | TLBWR = 415, |
3313 | | MFC0 = 416, |
3314 | | MTC0 = 417, |
3315 | | MFC2 = 418, |
3316 | | MTC2 = 419, |
3317 | | HYPCALL = 420, |
3318 | | MFGC0 = 421, |
3319 | | MFHGC0 = 422, |
3320 | | MTGC0 = 423, |
3321 | | MTHGC0 = 424, |
3322 | | TLBGINV = 425, |
3323 | | TLBGINVF = 426, |
3324 | | TLBGP = 427, |
3325 | | TLBGR = 428, |
3326 | | TLBGWI = 429, |
3327 | | TLBGWR = 430, |
3328 | | LB = 431, |
3329 | | LBu = 432, |
3330 | | LH = 433, |
3331 | | LHu = 434, |
3332 | | LW = 435, |
3333 | | LL = 436, |
3334 | | LWC2 = 437, |
3335 | | LWC3 = 438, |
3336 | | LDC2 = 439, |
3337 | | LDC3 = 440, |
3338 | | LBE = 441, |
3339 | | LBuE = 442, |
3340 | | LHE = 443, |
3341 | | LHuE = 444, |
3342 | | LWE = 445, |
3343 | | LLE = 446, |
3344 | | LWPC = 447, |
3345 | | LWL = 448, |
3346 | | LWR = 449, |
3347 | | LWLE = 450, |
3348 | | LWRE = 451, |
3349 | | SB = 452, |
3350 | | SH = 453, |
3351 | | SW = 454, |
3352 | | SWC2 = 455, |
3353 | | SWC3 = 456, |
3354 | | SDC2 = 457, |
3355 | | SDC3 = 458, |
3356 | | SC = 459, |
3357 | | SBE = 460, |
3358 | | SHE = 461, |
3359 | | SWE = 462, |
3360 | | SCE = 463, |
3361 | | SWL = 464, |
3362 | | SWR = 465, |
3363 | | SWLE = 466, |
3364 | | SWRE = 467, |
3365 | | PREF = 468, |
3366 | | PREFE = 469, |
3367 | | CACHE = 470, |
3368 | | CACHEE = 471, |
3369 | | SYNC = 472, |
3370 | | SYNCI = 473, |
3371 | | CLO = 474, |
3372 | | CLZ = 475, |
3373 | | DI = 476, |
3374 | | EI = 477, |
3375 | | MFHI_MFLO_PseudoMFHI_PseudoMFLO = 478, |
3376 | | EHB = 479, |
3377 | | RDHWR = 480, |
3378 | | WSBH = 481, |
3379 | | MOVN_I_I = 482, |
3380 | | MOVZ_I_I = 483, |
3381 | | DIV_PseudoSDIV_SDIV = 484, |
3382 | | DIVU_PseudoUDIV_UDIV = 485, |
3383 | | MUL = 486, |
3384 | | MULT_PseudoMULT = 487, |
3385 | | MULTu_PseudoMULTu = 488, |
3386 | | MADD_PseudoMADD = 489, |
3387 | | MADDU_PseudoMADDU = 490, |
3388 | | MSUB_PseudoMSUB = 491, |
3389 | | MSUBU_PseudoMSUBU = 492, |
3390 | | MTHI_MTLO_PseudoMTLOHI = 493, |
3391 | | EXT = 494, |
3392 | | INS = 495, |
3393 | | ADD = 496, |
3394 | | ADDi = 497, |
3395 | | ADDiu = 498, |
3396 | | ANDi = 499, |
3397 | | ORi = 500, |
3398 | | ROTR = 501, |
3399 | | SEB = 502, |
3400 | | SEH = 503, |
3401 | | SLT_SLTu = 504, |
3402 | | SLL = 505, |
3403 | | SRA = 506, |
3404 | | SRL = 507, |
3405 | | XORi = 508, |
3406 | | ADDu = 509, |
3407 | | SLLV = 510, |
3408 | | SRAV = 511, |
3409 | | SRLV = 512, |
3410 | | LSA = 513, |
3411 | | COPY = 514, |
3412 | | VSHF_B_VSHF_D_VSHF_H_VSHF_W = 515, |
3413 | | BINSLI_B_BINSLI_D_BINSLI_H_BINSLI_W_BINSL_B_BINSL_D_BINSL_H_BINSL_W = 516, |
3414 | | BINSRI_B_BINSRI_D_BINSRI_H_BINSRI_W_BINSR_B_BINSR_D_BINSR_H_BINSR_W = 517, |
3415 | | INSERT_B_INSERT_D_INSERT_H_INSERT_W = 518, |
3416 | | SLDI_B_SLDI_D_SLDI_H_SLDI_W_SLD_B_SLD_D_SLD_H_SLD_W = 519, |
3417 | | BSETI_B_BSETI_D_BSETI_H_BSETI_W_BSET_B_BSET_D_BSET_H_BSET_W = 520, |
3418 | | BCLRI_B_BCLRI_D_BCLRI_H_BCLRI_W_BCLR_B_BCLR_D_BCLR_H_BCLR_W = 521, |
3419 | | BNEGI_B_BNEGI_D_BNEGI_H_BNEGI_W_BNEG_B_BNEG_D_BNEG_H_BNEG_W = 522, |
3420 | | BSELI_B_BSEL_V = 523, |
3421 | | BMNZI_B_BMNZ_V_BMZI_B_BMZ_V = 524, |
3422 | | BSEL_D_PSEUDO_BSEL_FD_PSEUDO_BSEL_FW_PSEUDO_BSEL_H_PSEUDO_BSEL_W_PSEUDO = 525, |
3423 | | PCNT_B_PCNT_D_PCNT_H_PCNT_W = 526, |
3424 | | SAT_S_B_SAT_S_D_SAT_S_H_SAT_S_W_SAT_U_B_SAT_U_D_SAT_U_H_SAT_U_W = 527, |
3425 | | BNZ_B_BNZ_D_BNZ_H_BNZ_V_BNZ_W_BZ_B_BZ_D_BZ_H_BZ_V_BZ_W = 528, |
3426 | | CFCMSA_CTCMSA = 529, |
3427 | | FABS_S_FABS_D32_FABS_D64 = 530, |
3428 | | MOVF_D32_MOVF_D64 = 531, |
3429 | | MOVF_S = 532, |
3430 | | MOVT_D32_MOVT_D64 = 533, |
3431 | | MOVT_S = 534, |
3432 | | FMOV_D32_FMOV_D64 = 535, |
3433 | | FMOV_S = 536, |
3434 | | FNEG_S_FNEG_D32_FNEG_D64 = 537, |
3435 | | ADD_A_B_ADD_A_D_ADD_A_H_ADD_A_W = 538, |
3436 | | ADDS_A_B_ADDS_A_D_ADDS_A_H_ADDS_A_W_ADDS_S_B_ADDS_S_D_ADDS_S_H_ADDS_S_W_ADDS_U_B_ADDS_U_D_ADDS_U_H_ADDS_U_W = 539, |
3437 | | ADDVI_B_ADDVI_D_ADDVI_H_ADDVI_W_ADDV_B_ADDV_D_ADDV_H_ADDV_W = 540, |
3438 | | ASUB_S_B_ASUB_S_D_ASUB_S_H_ASUB_S_W_ASUB_U_B_ASUB_U_D_ASUB_U_H_ASUB_U_W = 541, |
3439 | | AVER_S_B_AVER_S_D_AVER_S_H_AVER_S_W_AVER_U_B_AVER_U_D_AVER_U_H_AVER_U_W_AVE_S_B_AVE_S_D_AVE_S_H_AVE_S_W_AVE_U_B_AVE_U_D_AVE_U_H_AVE_U_W = 542, |
3440 | | SHF_B_SHF_H_SHF_W = 543, |
3441 | | FILL_B_FILL_D_FILL_H_FILL_W = 544, |
3442 | | SPLATI_B_SPLATI_D_SPLATI_H_SPLATI_W_SPLAT_B_SPLAT_D_SPLAT_H_SPLAT_W = 545, |
3443 | | MOVE_V = 546, |
3444 | | LDI_B_LDI_D_LDI_H_LDI_W = 547, |
3445 | | AND_V_NOR_V_OR_V_XOR_V = 548, |
3446 | | ANDI_B_NORI_B_ORI_B_XORI_B = 549, |
3447 | | AND_V_D_PSEUDO_AND_V_H_PSEUDO_AND_V_W_PSEUDO_NOR_V_D_PSEUDO_NOR_V_H_PSEUDO_NOR_V_W_PSEUDO_OR_V_D_PSEUDO_OR_V_H_PSEUDO_OR_V_W_PSEUDO_XOR_V_D_PSEUDO_XOR_V_H_PSEUDO_XOR_V_W_PSEUDO = 550, |
3448 | | FILL_FD_PSEUDO_FILL_FW_PSEUDO = 551, |
3449 | | INSERT_FD_PSEUDO_INSERT_FW_PSEUDO = 552, |
3450 | | FEXP2_D_FEXP2_W = 553, |
3451 | | CLTI_S_B_CLTI_S_D_CLTI_S_H_CLTI_S_W_CLTI_U_B_CLTI_U_D_CLTI_U_H_CLTI_U_W_CLT_S_B_CLT_S_D_CLT_S_H_CLT_S_W_CLT_U_B_CLT_U_D_CLT_U_H_CLT_U_W = 554, |
3452 | | CLEI_S_B_CLEI_S_D_CLEI_S_H_CLEI_S_W_CLEI_U_B_CLEI_U_D_CLEI_U_H_CLEI_U_W_CLE_S_B_CLE_S_D_CLE_S_H_CLE_S_W_CLE_U_B_CLE_U_D_CLE_U_H_CLE_U_W = 555, |
3453 | | CEQI_B_CEQI_D_CEQI_H_CEQI_W_CEQ_B_CEQ_D_CEQ_H_CEQ_W = 556, |
3454 | | CMP_UN_D = 557, |
3455 | | CMP_UN_S = 558, |
3456 | | CMP_UEQ_D = 559, |
3457 | | CMP_UEQ_S = 560, |
3458 | | CMP_EQ_D = 561, |
3459 | | CMP_EQ_S = 562, |
3460 | | CMP_LT_D = 563, |
3461 | | CMP_LT_S = 564, |
3462 | | CMP_ULT_D = 565, |
3463 | | CMP_ULT_S = 566, |
3464 | | CMP_LE_D = 567, |
3465 | | CMP_LE_S = 568, |
3466 | | CMP_ULE_D = 569, |
3467 | | CMP_ULE_S = 570, |
3468 | | FSAF_D_FSAF_W_FSEQ_D_FSEQ_W_FSLE_D_FSLE_W_FSLT_D_FSLT_W_FSNE_D_FSNE_W_FSOR_D_FSOR_W = 571, |
3469 | | FSUEQ_D_FSUEQ_W = 572, |
3470 | | FSULE_D_FSULE_W = 573, |
3471 | | FSULT_D_FSULT_W = 574, |
3472 | | FSUNE_D_FSUNE_W = 575, |
3473 | | FSUN_D_FSUN_W = 576, |
3474 | | FCAF_D_FCAF_W = 577, |
3475 | | FCEQ_D_FCEQ_W = 578, |
3476 | | FCLE_D_FCLE_W = 579, |
3477 | | FCLT_D_FCLT_W = 580, |
3478 | | FCNE_D_FCNE_W = 581, |
3479 | | FCOR_D_FCOR_W = 582, |
3480 | | FCUEQ_D_FCUEQ_W = 583, |
3481 | | FCULE_D_FCULE_W = 584, |
3482 | | FCULT_D_FCULT_W = 585, |
3483 | | FCUNE_D_FCUNE_W = 586, |
3484 | | FCUN_D_FCUN_W = 587, |
3485 | | FABS_D_FABS_W = 588, |
3486 | | FFINT_S_D_FFINT_S_W_FFINT_U_D_FFINT_U_W = 589, |
3487 | | FFQL_D_FFQL_W = 590, |
3488 | | FFQR_D_FFQR_W = 591, |
3489 | | FTINT_S_D_FTINT_S_W_FTINT_U_D_FTINT_U_W = 592, |
3490 | | FRINT_D_FRINT_W = 593, |
3491 | | FTQ_H_FTQ_W = 594, |
3492 | | FTRUNC_S_D_FTRUNC_S_W_FTRUNC_U_D_FTRUNC_U_W = 595, |
3493 | | FEXDO_H_FEXDO_W = 596, |
3494 | | FEXUPL_D_FEXUPL_W = 597, |
3495 | | FEXUPR_D_FEXUPR_W = 598, |
3496 | | FCLASS_D_FCLASS_W = 599, |
3497 | | FMAX_A_D_FMAX_A_W = 600, |
3498 | | FMAX_D_FMAX_W = 601, |
3499 | | FMIN_A_D_FMIN_A_W = 602, |
3500 | | FMIN_D_FMIN_W = 603, |
3501 | | FLOG2_D_FLOG2_W = 604, |
3502 | | ILVL_B_ILVL_D_ILVL_H_ILVL_W_ILVR_B_ILVR_D_ILVR_H_ILVR_W = 605, |
3503 | | ILVEV_B_ILVEV_D_ILVEV_H_ILVEV_W_ILVOD_B_ILVOD_D_ILVOD_H_ILVOD_W = 606, |
3504 | | INSVE_B_INSVE_D_INSVE_H_INSVE_W = 607, |
3505 | | SUBS_S_B_SUBS_S_D_SUBS_S_H_SUBS_S_W_SUBS_U_B_SUBS_U_D_SUBS_U_H_SUBS_U_W = 608, |
3506 | | SUBSUS_U_B_SUBSUS_U_D_SUBSUS_U_H_SUBSUS_U_W = 609, |
3507 | | SUBSUU_S_B_SUBSUU_S_D_SUBSUU_S_H_SUBSUU_S_W = 610, |
3508 | | SUBVI_B_SUBVI_D_SUBVI_H_SUBVI_W = 611, |
3509 | | SUBV_B_SUBV_D_SUBV_H_SUBV_W = 612, |
3510 | | MOD_S_B_MOD_S_D_MOD_S_H_MOD_S_W_MOD_U_B_MOD_U_D_MOD_U_H_MOD_U_W = 613, |
3511 | | DIV_S_B_DIV_S_D_DIV_S_H_DIV_S_W_DIV_U_B_DIV_U_D_DIV_U_H_DIV_U_W = 614, |
3512 | | HADD_S_D_HADD_S_H_HADD_S_W_HADD_U_D_HADD_U_H_HADD_U_W = 615, |
3513 | | HSUB_S_D_HSUB_S_H_HSUB_S_W_HSUB_U_D_HSUB_U_H_HSUB_U_W = 616, |
3514 | | MAX_S_B_MAX_S_D_MAX_S_H_MAX_S_W_MIN_S_B_MIN_S_D_MIN_S_H_MIN_S_W = 617, |
3515 | | MAX_U_B_MAX_U_D_MAX_U_H_MAX_U_W_MIN_U_B_MIN_U_D_MIN_U_H_MIN_U_W = 618, |
3516 | | MAX_A_B_MAX_A_D_MAX_A_H_MAX_A_W_MIN_A_B_MIN_A_D_MIN_A_H_MIN_A_W = 619, |
3517 | | MAXI_S_B_MAXI_S_D_MAXI_S_H_MAXI_S_W_MAXI_U_B_MAXI_U_D_MAXI_U_H_MAXI_U_W_MINI_S_B_MINI_S_D_MINI_S_H_MINI_S_W_MINI_U_B_MINI_U_D_MINI_U_H_MINI_U_W = 620, |
3518 | | SRAI_B_SRAI_D_SRAI_H_SRAI_W_SRA_B_SRA_D_SRA_H_SRA_W = 621, |
3519 | | SRLI_B_SRLI_D_SRLI_H_SRLI_W_SRL_B_SRL_D_SRL_H_SRL_W = 622, |
3520 | | SRARI_B_SRARI_D_SRARI_H_SRARI_W_SRAR_B_SRAR_D_SRAR_H_SRAR_W = 623, |
3521 | | SRLRI_B_SRLRI_D_SRLRI_H_SRLRI_W_SRLR_B_SRLR_D_SRLR_H_SRLR_W = 624, |
3522 | | SLLI_B_SLLI_D_SLLI_H_SLLI_W_SLL_B_SLL_D_SLL_H_SLL_W = 625, |
3523 | | PCKEV_B_PCKEV_D_PCKEV_H_PCKEV_W_PCKOD_B_PCKOD_D_PCKOD_H_PCKOD_W = 626, |
3524 | | NLOC_B_NLOC_D_NLOC_H_NLOC_W_NLZC_B_NLZC_D_NLZC_H_NLZC_W = 627, |
3525 | | FADD_D32_FADD_D64 = 628, |
3526 | | FADD_PS64 = 629, |
3527 | | FADD_S = 630, |
3528 | | FMUL_D32_FMUL_D64 = 631, |
3529 | | FMUL_PS64 = 632, |
3530 | | FMUL_S = 633, |
3531 | | FSUB_D32_FSUB_D64 = 634, |
3532 | | FSUB_PS64 = 635, |
3533 | | FSUB_S = 636, |
3534 | | TRUNC_L_D64_TRUNC_L_S_TRUNC_W_D32_TRUNC_W_D64_TRUNC_W_S = 637, |
3535 | | CVT_D32_S_CVT_D32_W_CVT_D64_L_CVT_D64_S_CVT_D64_W_CVT_L_D64_CVT_L_S_CVT_S_D32_CVT_S_D64_CVT_S_L_CVT_S_W_CVT_W_D32_CVT_W_D64_CVT_W_S = 638, |
3536 | | CVT_PS_S64_CVT_S_PL64_CVT_S_PU64 = 639, |
3537 | | C_EQ_D32_C_EQ_D64_C_F_D32_C_F_D64_C_LE_D32_C_LE_D64_C_LT_D32_C_LT_D64_C_NGE_D32_C_NGE_D64_C_NGLE_D32_C_NGLE_D64_C_NGL_D32_C_NGL_D64_C_NGT_D32_C_NGT_D64_C_OLE_D32_C_OLE_D64_C_OLT_D32_C_OLT_D64_C_SEQ_D32_C_SEQ_D64_C_SF_D32_C_SF_D64_C_UEQ_D32_C_UEQ_D64_C_ULE_D32_C_ULE_D64_C_ULT_D32_C_ULT_D64_C_UN_D32_C_UN_D64 = 640, |
3538 | | C_EQ_S_C_F_S_C_LE_S_C_LT_S_C_NGE_S_C_NGLE_S_C_NGL_S_C_NGT_S_C_OLE_S_C_OLT_S_C_SEQ_S_C_SF_S_C_UEQ_S_C_ULE_S_C_ULT_S_C_UN_S = 641, |
3539 | | FCMP_D32_FCMP_D64 = 642, |
3540 | | FCMP_S32 = 643, |
3541 | | PseudoCVT_D32_W_PseudoCVT_D64_L_PseudoCVT_D64_W_PseudoCVT_S_L_PseudoCVT_S_W = 644, |
3542 | | PLL_PS64_PLU_PS64_PUL_PS64_PUU_PS64 = 645, |
3543 | | FDIV_S = 646, |
3544 | | FDIV_D32_FDIV_D64 = 647, |
3545 | | FSQRT_S = 648, |
3546 | | FSQRT_D32_FSQRT_D64 = 649, |
3547 | | FRCP_D_FRCP_W = 650, |
3548 | | FRSQRT_D_FRSQRT_W = 651, |
3549 | | RECIP_D32_RECIP_D64 = 652, |
3550 | | RSQRT_D32_RSQRT_D64 = 653, |
3551 | | RECIP_S = 654, |
3552 | | RSQRT_S = 655, |
3553 | | FMADD_D_FMADD_W = 656, |
3554 | | FMSUB_D_FMSUB_W = 657, |
3555 | | FDIV_W = 658, |
3556 | | FDIV_D = 659, |
3557 | | FSQRT_W = 660, |
3558 | | FSQRT_D = 661, |
3559 | | FMUL_D_FMUL_W = 662, |
3560 | | FADD_D_FADD_W = 663, |
3561 | | FSUB_D_FSUB_W = 664, |
3562 | | DPADD_S_D_DPADD_S_H_DPADD_S_W_DPADD_U_D_DPADD_U_H_DPADD_U_W = 665, |
3563 | | DPSUB_S_D_DPSUB_S_H_DPSUB_S_W_DPSUB_U_D_DPSUB_U_H_DPSUB_U_W = 666, |
3564 | | DOTP_S_D_DOTP_S_H_DOTP_S_W_DOTP_U_D_DOTP_U_H_DOTP_U_W = 667, |
3565 | | MSUBV_B_MSUBV_D_MSUBV_H_MSUBV_W = 668, |
3566 | | MADDV_B_MADDV_D_MADDV_H_MADDV_W = 669, |
3567 | | MULV_B_MULV_D_MULV_H_MULV_W = 670, |
3568 | | MADDR_Q_H_MADDR_Q_W = 671, |
3569 | | MADD_Q_H_MADD_Q_W = 672, |
3570 | | MSUBR_Q_H_MSUBR_Q_W = 673, |
3571 | | MSUB_Q_H_MSUB_Q_W = 674, |
3572 | | MULR_Q_H_MULR_Q_W = 675, |
3573 | | MUL_Q_H_MUL_Q_W = 676, |
3574 | | MADD_D32_MADD_D64 = 677, |
3575 | | MADD_S = 678, |
3576 | | MSUB_D32_MSUB_D64 = 679, |
3577 | | MSUB_S = 680, |
3578 | | NMADD_D32_NMADD_D64 = 681, |
3579 | | NMADD_S = 682, |
3580 | | NMSUB_D32_NMSUB_D64 = 683, |
3581 | | NMSUB_S = 684, |
3582 | | CTC1 = 685, |
3583 | | MTC1_MTC1_D64_BuildPairF64_BuildPairF64_64 = 686, |
3584 | | MTHC1_D32_MTHC1_D64 = 687, |
3585 | | COPY_U_B_COPY_U_H_COPY_U_W = 688, |
3586 | | COPY_S_B_COPY_S_D_COPY_S_H_COPY_S_W = 689, |
3587 | | BC1F = 690, |
3588 | | BC1FL = 691, |
3589 | | BC1T = 692, |
3590 | | BC1TL = 693, |
3591 | | CFC1 = 694, |
3592 | | MFC1_MFC1_D64_ExtractElementF64_ExtractElementF64_64 = 695, |
3593 | | MFHC1_D32_MFHC1_D64 = 696, |
3594 | | MOVF_I = 697, |
3595 | | MOVT_I = 698, |
3596 | | SDC1_SDC164 = 699, |
3597 | | SDXC1_SDXC164 = 700, |
3598 | | SWC1 = 701, |
3599 | | SWXC1 = 702, |
3600 | | SUXC1_SUXC164 = 703, |
3601 | | ST_B_ST_D_ST_H_ST_W = 704, |
3602 | | ST_F16 = 705, |
3603 | | MOVN_I_D32_MOVN_I_D64 = 706, |
3604 | | MOVN_I_S = 707, |
3605 | | MOVZ_I_D32_MOVZ_I_D64 = 708, |
3606 | | MOVZ_I_S = 709, |
3607 | | LDC1_LDC164 = 710, |
3608 | | LDXC1_LDXC164 = 711, |
3609 | | LWC1 = 712, |
3610 | | LWXC1 = 713, |
3611 | | LUXC1_LUXC164 = 714, |
3612 | | LD_B_LD_D_LD_H_LD_W = 715, |
3613 | | LD_F16 = 716, |
3614 | | CEIL_L_D64_CEIL_L_S_CEIL_W_D32_CEIL_W_D64_CEIL_W_S = 717, |
3615 | | FLOOR_L_D64_FLOOR_L_S_FLOOR_W_D32_FLOOR_W_D64_FLOOR_W_S = 718, |
3616 | | ROUND_L_D64_ROUND_L_S_ROUND_W_D32_ROUND_W_D64_ROUND_W_S = 719, |
3617 | | ROTRV = 720, |
3618 | | ATOMIC_SWAP_I16_POSTRA_ATOMIC_SWAP_I32_POSTRA_ATOMIC_SWAP_I64_POSTRA_ATOMIC_SWAP_I8_POSTRA = 721, |
3619 | | ATOMIC_CMP_SWAP_I16_POSTRA_ATOMIC_CMP_SWAP_I32_POSTRA_ATOMIC_CMP_SWAP_I64_POSTRA_ATOMIC_CMP_SWAP_I8_POSTRA = 722, |
3620 | | ATOMIC_LOAD_ADD_I16_POSTRA_ATOMIC_LOAD_ADD_I32_POSTRA_ATOMIC_LOAD_ADD_I64_POSTRA_ATOMIC_LOAD_ADD_I8_POSTRA_ATOMIC_LOAD_AND_I16_POSTRA_ATOMIC_LOAD_AND_I32_POSTRA_ATOMIC_LOAD_AND_I64_POSTRA_ATOMIC_LOAD_AND_I8_POSTRA_ATOMIC_LOAD_MAX_I16_POSTRA_ATOMIC_LOAD_MAX_I32_POSTRA_ATOMIC_LOAD_MAX_I64_POSTRA_ATOMIC_LOAD_MAX_I8_POSTRA_ATOMIC_LOAD_MIN_I16_POSTRA_ATOMIC_LOAD_MIN_I32_POSTRA_ATOMIC_LOAD_MIN_I64_POSTRA_ATOMIC_LOAD_MIN_I8_POSTRA_ATOMIC_LOAD_NAND_I16_POSTRA_ATOMIC_LOAD_NAND_I32_POSTRA_ATOMIC_LOAD_NAND_I64_POSTRA_ATOMIC_LOAD_NAND_I8_POSTRA_ATOMIC_LOAD_OR_I16_POSTRA_ATOMIC_LOAD_OR_I32_POSTRA_ATOMIC_LOAD_OR_I64_POSTRA_ATOMIC_LOAD_OR_I8_POSTRA_ATOMIC_LOAD_SUB_I16_POSTRA_ATOMIC_LOAD_SUB_I32_POSTRA_ATOMIC_LOAD_SUB_I64_POSTRA_ATOMIC_LOAD_SUB_I8_POSTRA_ATOMIC_LOAD_UMAX_I16_POSTRA_ATOMIC_LOAD_UMAX_I32_POSTRA_ATOMIC_LOAD_UMAX_I64_POSTRA_ATOMIC_LOAD_UMAX_I8_POSTRA_ATOMIC_LOAD_UMIN_I16_POSTRA_ATOMIC_LOAD_UMIN_I32_POSTRA_ATOMIC_LOAD_UMIN_I64_POSTRA_ATOMIC_LOAD_UMIN_I8_POSTRA_ATOMIC_LOAD_XOR_I16_POSTRA_ATOMIC_LOAD_XOR_I32_POSTRA_ATOMIC_LOAD_XOR_I64_POSTRA_ATOMIC_LOAD_XOR_I8_POSTRA = 723, |
3621 | | LEA_ADDiu = 724, |
3622 | | ADDIUPC = 725, |
3623 | | ALIGN = 726, |
3624 | | ALUIPC = 727, |
3625 | | AUI = 728, |
3626 | | AUIPC = 729, |
3627 | | BITSWAP = 730, |
3628 | | CLO_R6 = 731, |
3629 | | CLZ_R6 = 732, |
3630 | | LSA_R6 = 733, |
3631 | | SELEQZ_SELNEZ = 734, |
3632 | | AddiuRxImmX16_AddiuRxRxImm16_AddiuRxRxImmX16_AddiuRxRyOffMemX16_AddiuRxPcImmX16_AddiuSpImm16_AddiuSpImmX16_AdduRxRyRz16_AndRxRxRy16_CmpRxRy16_CmpiRxImm16_CmpiRxImmX16_LiRxImm16_LiRxImmX16_LiRxImmAlignX16_Move32R16_MoveR3216_Mfhi16_Mflo16_NegRxRy16_NotRxRy16_OrRxRxRy16_SebRx16_SehRx16_SllX16_SllvRxRy16_SltiRxImm16_SltiRxImmX16_SltiuRxImm16_SltiuRxImmX16_SltRxRy16_SltuRxRy16_SravRxRy16_SraX16_SrlvRxRy16_SrlX16_SubuRxRyRz16_XorRxRxRy16 = 735, |
3633 | | SltiCCRxImmX16_SltiuCCRxImmX16_SltCCRxRy16_SltuRxRyRz16_SltuCCRxRy16 = 736, |
3634 | | Constant32_LwConstant32_GotPrologue16_CONSTPOOL_ENTRY = 737, |
3635 | | ADDIUPC_MM_ADDIUR1SP_MM_ADDIUR2_MM_ADDIUS5_MM_ADDIUSP_MM_ADDiu_MM_LEA_ADDiu_MM = 738, |
3636 | | ADDU16_MM_ADDu_MM = 739, |
3637 | | ADD_MM = 740, |
3638 | | ADDi_MM = 741, |
3639 | | AND16_MM_ANDI16_MM_AND_MM = 742, |
3640 | | ANDi_MM = 743, |
3641 | | CLO_MM = 744, |
3642 | | CLZ_MM = 745, |
3643 | | EXT_MM = 746, |
3644 | | INS_MM = 747, |
3645 | | LI16_MM = 748, |
3646 | | LUi_MM = 749, |
3647 | | MOVE16_MM = 750, |
3648 | | MOVEP_MM = 751, |
3649 | | NOR_MM = 752, |
3650 | | NOT16_MM = 753, |
3651 | | OR16_MM_OR_MM = 754, |
3652 | | ORi_MM = 755, |
3653 | | ROTRV_MM = 756, |
3654 | | ROTR_MM = 757, |
3655 | | SEB_MM = 758, |
3656 | | SEH_MM = 759, |
3657 | | SLL16_MM_SLL_MM = 760, |
3658 | | SLLV_MM = 761, |
3659 | | SLT_MM_SLTu_MM = 762, |
3660 | | SLTi_MM_SLTiu_MM = 763, |
3661 | | SRAV_MM = 764, |
3662 | | SRA_MM = 765, |
3663 | | SRL16_MM_SRL_MM = 766, |
3664 | | SRLV_MM = 767, |
3665 | | SSNOP_MM = 768, |
3666 | | SUBU16_MM_SUBu_MM = 769, |
3667 | | SUB_MM = 770, |
3668 | | WSBH_MM = 771, |
3669 | | XOR16_MM_XOR_MM = 772, |
3670 | | XORi_MM = 773, |
3671 | | ADDIUPC_MMR6 = 774, |
3672 | | ADDIU_MMR6 = 775, |
3673 | | ADDU16_MMR6_ADDU_MMR6 = 776, |
3674 | | ADD_MMR6 = 777, |
3675 | | ALIGN_MMR6 = 778, |
3676 | | ALUIPC_MMR6 = 779, |
3677 | | AND16_MMR6_ANDI16_MMR6_AND_MMR6 = 780, |
3678 | | ANDI_MMR6 = 781, |
3679 | | AUIPC_MMR6 = 782, |
3680 | | AUI_MMR6 = 783, |
3681 | | BITSWAP_MMR6 = 784, |
3682 | | CLO_MMR6 = 785, |
3683 | | CLZ_MMR6 = 786, |
3684 | | EXT_MMR6 = 787, |
3685 | | INS_MMR6 = 788, |
3686 | | LI16_MMR6 = 789, |
3687 | | LSA_MMR6 = 790, |
3688 | | LUI_MMR6 = 791, |
3689 | | MOVE16_MMR6 = 792, |
3690 | | NOR_MMR6 = 793, |
3691 | | NOT16_MMR6 = 794, |
3692 | | OR16_MMR6_OR_MMR6 = 795, |
3693 | | ORI_MMR6 = 796, |
3694 | | SELEQZ_MMR6_SELNEZ_MMR6 = 797, |
3695 | | SLL16_MMR6_SLL_MMR6 = 798, |
3696 | | SRL16_MMR6 = 799, |
3697 | | SSNOP_MMR6 = 800, |
3698 | | SUBU16_MMR6_SUBU_MMR6 = 801, |
3699 | | SUB_MMR6 = 802, |
3700 | | WSBH_MMR6 = 803, |
3701 | | XOR16_MMR6_XOR_MMR6 = 804, |
3702 | | XORI_MMR6 = 805, |
3703 | | AND64_ANDi64 = 806, |
3704 | | DEXT64_32 = 807, |
3705 | | DSLL64_32 = 808, |
3706 | | ORi64 = 809, |
3707 | | SEB64 = 810, |
3708 | | SEH64 = 811, |
3709 | | SLL64_32_SLL64_64 = 812, |
3710 | | SLT64_SLTu64 = 813, |
3711 | | SLTi64_SLTiu64 = 814, |
3712 | | XOR64_XORi64 = 815, |
3713 | | DADD = 816, |
3714 | | DADDi = 817, |
3715 | | DADDiu = 818, |
3716 | | DADDu = 819, |
3717 | | DCLO = 820, |
3718 | | DCLZ = 821, |
3719 | | DEXT_DEXTM_DEXTU = 822, |
3720 | | DINS_DINSM_DINSU = 823, |
3721 | | DROTR = 824, |
3722 | | DROTR32 = 825, |
3723 | | DROTRV = 826, |
3724 | | DSBH = 827, |
3725 | | DSHD = 828, |
3726 | | DSLL = 829, |
3727 | | DSLL32 = 830, |
3728 | | DSLLV = 831, |
3729 | | DSRA = 832, |
3730 | | DSRA32 = 833, |
3731 | | DSRAV = 834, |
3732 | | DSRL = 835, |
3733 | | DSRL32 = 836, |
3734 | | DSRLV = 837, |
3735 | | DSUB = 838, |
3736 | | DSUBu = 839, |
3737 | | LEA_ADDiu64 = 840, |
3738 | | LUi64 = 841, |
3739 | | NOR64 = 842, |
3740 | | OR64 = 843, |
3741 | | DALIGN = 844, |
3742 | | DAHI = 845, |
3743 | | DATI = 846, |
3744 | | DAUI = 847, |
3745 | | DCLO_R6 = 848, |
3746 | | DCLZ_R6 = 849, |
3747 | | DBITSWAP = 850, |
3748 | | DLSA_DLSA_R6 = 851, |
3749 | | SELEQZ64_SELNEZ64 = 852, |
3750 | | MADD = 853, |
3751 | | MADDU = 854, |
3752 | | MSUB = 855, |
3753 | | MSUBU = 856, |
3754 | | PseudoMADD_MM = 857, |
3755 | | PseudoMADDU_MM = 858, |
3756 | | PseudoMSUB_MM = 859, |
3757 | | PseudoMSUBU_MM = 860, |
3758 | | PseudoMULT_MM = 861, |
3759 | | PseudoMULTu_MM = 862, |
3760 | | PseudoMULT = 863, |
3761 | | PseudoMULTu = 864, |
3762 | | PseudoSDIV_SDIV = 865, |
3763 | | PseudoUDIV_UDIV = 866, |
3764 | | PseudoMFHI_MM_PseudoMFLO_MM = 867, |
3765 | | PseudoMTLOHI_MM = 868, |
3766 | | MUH = 869, |
3767 | | MUHU = 870, |
3768 | | MULU = 871, |
3769 | | MUL_R6 = 872, |
3770 | | MOD = 873, |
3771 | | MODU = 874, |
3772 | | MultRxRy16_MultuRxRy16_MultRxRyRz16_MultuRxRyRz16 = 875, |
3773 | | DivRxRy16 = 876, |
3774 | | DivuRxRy16 = 877, |
3775 | | MULT_MM = 878, |
3776 | | MULTu_MM = 879, |
3777 | | MADD_MM = 880, |
3778 | | MADDU_MM = 881, |
3779 | | MSUB_MM = 882, |
3780 | | MSUBU_MM = 883, |
3781 | | MUL_MM = 884, |
3782 | | SDIV_MM_SDIV_MM_Pseudo = 885, |
3783 | | UDIV_MM_UDIV_MM_Pseudo = 886, |
3784 | | MFHI16_MM_MFLO16_MM_MFHI_MM_MFLO_MM = 887, |
3785 | | MOVF_I_MM = 888, |
3786 | | MOVT_I_MM = 889, |
3787 | | MTHI_MM_MTLO_MM = 890, |
3788 | | RDHWR_MM = 891, |
3789 | | MUHU_MMR6 = 892, |
3790 | | MUH_MMR6 = 893, |
3791 | | MULU_MMR6 = 894, |
3792 | | MUL_MMR6 = 895, |
3793 | | MODU_MMR6 = 896, |
3794 | | MOD_MMR6 = 897, |
3795 | | DIVU_MMR6 = 898, |
3796 | | DIV_MMR6 = 899, |
3797 | | RDHWR_MMR6 = 900, |
3798 | | DMULU = 901, |
3799 | | DMULT_PseudoDMULT = 902, |
3800 | | DMULTu_PseudoDMULTu = 903, |
3801 | | DSDIV_PseudoDSDIV = 904, |
3802 | | DUDIV_PseudoDUDIV = 905, |
3803 | | MFHI64_MFLO64_PseudoMFHI64_PseudoMFLO64 = 906, |
3804 | | PseudoMTLOHI64 = 907, |
3805 | | MTHI64_MTLO64 = 908, |
3806 | | RDHWR64 = 909, |
3807 | | MOVN_I_I64_MOVN_I64_I_MOVN_I64_I64 = 910, |
3808 | | MOVZ_I_I64_MOVZ_I64_I_MOVZ_I64_I64 = 911, |
3809 | | DMUH = 912, |
3810 | | DMUHU = 913, |
3811 | | DMUL_R6 = 914, |
3812 | | DDIV = 915, |
3813 | | DMOD = 916, |
3814 | | DDIVU = 917, |
3815 | | DMODU = 918, |
3816 | | BAL_BR_BLTZAL = 919, |
3817 | | BEQ_BNE = 920, |
3818 | | BGTZ_BGEZ_BLEZ_BLTZ = 921, |
3819 | | J = 922, |
3820 | | JR = 923, |
3821 | | ERet = 924, |
3822 | | BGEZAL = 925, |
3823 | | BALC = 926, |
3824 | | BEQZALC_BGEZALC_BGTZALC_BLEZALC_BLTZALC_BNEZALC = 927, |
3825 | | JIALC = 928, |
3826 | | BC = 929, |
3827 | | BC2EQZ_BC2NEZ = 930, |
3828 | | BEQC_BGEC_BGEUC_BLTC_BLTUC_BNEC_BNVC_BOVC = 931, |
3829 | | BEQZC_BGEZC_BGTZC_BLEZC_BLTZC_BNEZC = 932, |
3830 | | JIC = 933, |
3831 | | JR_HB_R6 = 934, |
3832 | | SIGRIE = 935, |
3833 | | PseudoIndirectBranchR6_PseudoIndrectHazardBranchR6 = 936, |
3834 | | TAILCALLR6REG_TAILCALLHBR6REG = 937, |
3835 | | SDBBP_R6 = 938, |
3836 | | Bimm16_BimmX16_BeqzRxImm16_BeqzRxImmX16_BnezRxImm16_BnezRxImmX16_Bteqz16_BteqzX16_Btnez16_BtnezX16_JrRa16_JrcRa16_JrcRx16 = 939, |
3837 | | BteqzT8CmpX16_BteqzT8CmpiX16_BteqzT8SltX16_BteqzT8SltuX16_BteqzT8SltiX16_BteqzT8SltiuX16_BtnezT8CmpX16_BtnezT8CmpiX16_BtnezT8SltX16_BtnezT8SltuX16_BtnezT8SltiX16_BtnezT8SltiuX16_RetRA16 = 940, |
3838 | | Jal16_JalB16 = 941, |
3839 | | JumpLinkReg16 = 942, |
3840 | | Break16 = 943, |
3841 | | SelBeqZ_SelTBteqZCmp_SelTBteqZCmpi_SelTBteqZSlt_SelTBteqZSlti_SelTBteqZSltu_SelTBteqZSltiu_SelBneZ_SelTBtneZCmp_SelTBtneZCmpi_SelTBtneZSlt_SelTBtneZSlti_SelTBtneZSltu_SelTBtneZSltiu = 944, |
3842 | | B16_MM_B_MM = 945, |
3843 | | BAL_BR_MM = 946, |
3844 | | BC1F_MM = 947, |
3845 | | BC1T_MM = 948, |
3846 | | BEQZ16_MM_BGEZ_MM_BGTZ_MM_BLEZ_MM_BLTZ_MM_BNEZ16_MM = 949, |
3847 | | BEQZC_MM_BNEZC_MM = 950, |
3848 | | BEQ_MM_BNE_MM = 951, |
3849 | | DERET_MM = 952, |
3850 | | ERET_MM = 953, |
3851 | | JR16_MM_JR_MM = 954, |
3852 | | J_MM = 955, |
3853 | | B_MM_Pseudo = 956, |
3854 | | BGEZALS_MM_BLTZALS_MM = 957, |
3855 | | BGEZAL_MM_BLTZAL_MM = 958, |
3856 | | JALR16_MM_JALR_MM = 959, |
3857 | | JALRS16_MM_JALRS_MM = 960, |
3858 | | JALS_MM = 961, |
3859 | | JALX_MM_JAL_MM = 962, |
3860 | | TAILCALLREG_MM = 963, |
3861 | | TAILCALL_MM = 964, |
3862 | | PseudoIndirectBranch_MM = 965, |
3863 | | BREAK16_MM_BREAK_MM = 966, |
3864 | | SDBBP16_MM_SDBBP_MM = 967, |
3865 | | SYSCALL_MM = 968, |
3866 | | TEQI_MM = 969, |
3867 | | TEQ_MM = 970, |
3868 | | TGEIU_MM = 971, |
3869 | | TGEI_MM = 972, |
3870 | | TGEU_MM = 973, |
3871 | | TGE_MM = 974, |
3872 | | TLTIU_MM = 975, |
3873 | | TLTI_MM = 976, |
3874 | | TLTU_MM = 977, |
3875 | | TLT_MM = 978, |
3876 | | TNEI_MM = 979, |
3877 | | TNE_MM = 980, |
3878 | | TRAP_MM = 981, |
3879 | | BC16_MMR6_BC_MMR6 = 982, |
3880 | | BC1EQZC_MMR6_BC1NEZC_MMR6 = 983, |
3881 | | BC2EQZC_MMR6_BC2NEZC_MMR6 = 984, |
3882 | | BEQC_MMR6_BGEC_MMR6_BGEUC_MMR6_BLTC_MMR6_BLTUC_MMR6_BNEC_MMR6_BNVC_MMR6_BOVC_MMR6 = 985, |
3883 | | BEQZC16_MMR6_BNEZC16_MMR6 = 986, |
3884 | | BEQZC_MMR6_BGEZC_MMR6_BGTZC_MMR6_BLEZC_MMR6_BLTZC_MMR6_BNEZC_MMR6 = 987, |
3885 | | DERET_MMR6 = 988, |
3886 | | ERETNC_MMR6 = 989, |
3887 | | JAL_MMR6 = 990, |
3888 | | ERET_MMR6 = 991, |
3889 | | JIC_MMR6 = 992, |
3890 | | JRADDIUSP_JRCADDIUSP_MMR6 = 993, |
3891 | | JRC16_MM = 994, |
3892 | | JRC16_MMR6 = 995, |
3893 | | SIGRIE_MMR6 = 996, |
3894 | | B_MMR6_Pseudo = 997, |
3895 | | PseudoIndirectBranch_MMR6 = 998, |
3896 | | BALC_MMR6 = 999, |
3897 | | BEQZALC_MMR6_BGEZALC_MMR6_BGTZALC_MMR6_BLEZALC_MMR6_BLTZALC_MMR6_BNEZALC_MMR6 = 1000, |
3898 | | JALRC16_MMR6 = 1001, |
3899 | | JALRC_HB_MMR6 = 1002, |
3900 | | JALRC_MMR6 = 1003, |
3901 | | JIALC_MMR6 = 1004, |
3902 | | TAILCALLREG_MMR6 = 1005, |
3903 | | TAILCALL_MMR6 = 1006, |
3904 | | BREAK16_MMR6_BREAK_MMR6 = 1007, |
3905 | | SDBBP_MMR6_SDBBP16_MMR6 = 1008, |
3906 | | BEQ64_BNE64 = 1009, |
3907 | | BGEZ64_BGTZ64_BLEZ64_BLTZ64 = 1010, |
3908 | | JR64 = 1011, |
3909 | | JALR64_JALR64Pseudo_JALRHB64Pseudo = 1012, |
3910 | | JALR_HB64 = 1013, |
3911 | | JR_HB64 = 1014, |
3912 | | TAILCALLREG64_TAILCALLREGHB64 = 1015, |
3913 | | PseudoReturn64 = 1016, |
3914 | | BEQC64_BGEC64_BGEUC64_BLTC64_BLTUC64_BNEC64 = 1017, |
3915 | | BEQZC64_BGEZC64_BGTZC64_BLEZC64_BLTZC64_BNEZC64 = 1018, |
3916 | | JIC64 = 1019, |
3917 | | PseudoIndirectBranch64_PseudoIndirectHazardBranch64 = 1020, |
3918 | | JIALC64 = 1021, |
3919 | | JR_HB64_R6 = 1022, |
3920 | | TAILCALL64R6REG_TAILCALLHB64R6REG = 1023, |
3921 | | PseudoIndirectBranch64R6_PseudoIndrectHazardBranch64R6 = 1024, |
3922 | | EVP = 1025, |
3923 | | DVP = 1026, |
3924 | | TLBP_MM = 1027, |
3925 | | TLBR_MM = 1028, |
3926 | | TLBWI_MM = 1029, |
3927 | | TLBWR_MM = 1030, |
3928 | | DI_MM = 1031, |
3929 | | EI_MM = 1032, |
3930 | | EHB_MM = 1033, |
3931 | | PAUSE_MM = 1034, |
3932 | | WAIT_MM = 1035, |
3933 | | RDPGPR_MMR6 = 1036, |
3934 | | WRPGPR_MMR6 = 1037, |
3935 | | TLBINV_MMR6 = 1038, |
3936 | | TLBINVF_MMR6 = 1039, |
3937 | | MFHC0_MMR6 = 1040, |
3938 | | MFC0_MMR6 = 1041, |
3939 | | MFHC2_MMR6_MFC2_MMR6 = 1042, |
3940 | | MTHC0_MMR6 = 1043, |
3941 | | MTC0_MMR6 = 1044, |
3942 | | MTHC2_MMR6_MTC2_MMR6 = 1045, |
3943 | | EVP_MMR6 = 1046, |
3944 | | DVP_MMR6 = 1047, |
3945 | | DI_MMR6 = 1048, |
3946 | | EI_MMR6 = 1049, |
3947 | | EHB_MMR6 = 1050, |
3948 | | PAUSE_MMR6 = 1051, |
3949 | | WAIT_MMR6 = 1052, |
3950 | | DMFC0 = 1053, |
3951 | | DMTC0 = 1054, |
3952 | | DMFC2 = 1055, |
3953 | | DMTC2 = 1056, |
3954 | | CFC2_MM = 1057, |
3955 | | CTC2_MM = 1058, |
3956 | | DMT = 1059, |
3957 | | DVPE = 1060, |
3958 | | EMT = 1061, |
3959 | | EVPE = 1062, |
3960 | | MFTR = 1063, |
3961 | | MTTR = 1064, |
3962 | | YIELD = 1065, |
3963 | | FORK = 1066, |
3964 | | DMFGC0 = 1067, |
3965 | | DMTGC0 = 1068, |
3966 | | HYPCALL_MM = 1069, |
3967 | | TLBGINVF_MM = 1070, |
3968 | | TLBGINV_MM = 1071, |
3969 | | TLBGP_MM = 1072, |
3970 | | TLBGR_MM = 1073, |
3971 | | TLBGWI_MM = 1074, |
3972 | | TLBGWR_MM = 1075, |
3973 | | MFGC0_MM = 1076, |
3974 | | MFHGC0_MM = 1077, |
3975 | | MTGC0_MM = 1078, |
3976 | | MTHGC0_MM = 1079, |
3977 | | SC_MMR6 = 1080, |
3978 | | LDC2_R6 = 1081, |
3979 | | LL_R6 = 1082, |
3980 | | LWC2_R6 = 1083, |
3981 | | SWC2_R6 = 1084, |
3982 | | SDC2_R6 = 1085, |
3983 | | SC_R6 = 1086, |
3984 | | PREF_R6 = 1087, |
3985 | | CACHE_R6 = 1088, |
3986 | | GINVI = 1089, |
3987 | | GINVT = 1090, |
3988 | | LBE_MM = 1091, |
3989 | | LBuE_MM = 1092, |
3990 | | LHE_MM = 1093, |
3991 | | LHuE_MM = 1094, |
3992 | | LWE_MM = 1095, |
3993 | | LWLE_MM = 1096, |
3994 | | LWRE_MM = 1097, |
3995 | | LLE_MM = 1098, |
3996 | | SBE_MM = 1099, |
3997 | | SB_MM = 1100, |
3998 | | SHE_MM = 1101, |
3999 | | SWE_MM = 1102, |
4000 | | SWLE_MM = 1103, |
4001 | | SWRE_MM = 1104, |
4002 | | SCE_MM = 1105, |
4003 | | PREFE_MM = 1106, |
4004 | | CACHEE_MM = 1107, |
4005 | | Restore16_RestoreX16 = 1108, |
4006 | | LbRxRyOffMemX16 = 1109, |
4007 | | LbuRxRyOffMemX16 = 1110, |
4008 | | LhRxRyOffMemX16 = 1111, |
4009 | | LhuRxRyOffMemX16 = 1112, |
4010 | | LwRxRyOffMemX16_LwRxSpImmX16_LwRxPcTcp16_LwRxPcTcpX16 = 1113, |
4011 | | Save16_SaveX16 = 1114, |
4012 | | SbRxRyOffMemX16 = 1115, |
4013 | | ShRxRyOffMemX16 = 1116, |
4014 | | SwRxRyOffMemX16_SwRxSpImmX16 = 1117, |
4015 | | LBU16_MM_LBu_MM = 1118, |
4016 | | LB_MM = 1119, |
4017 | | LHU16_MM_LHu_MM = 1120, |
4018 | | LH_MM = 1121, |
4019 | | LL_MM = 1122, |
4020 | | LW16_MM_LWGP_MM_LWSP_MM_LW_MM = 1123, |
4021 | | LWL_MM = 1124, |
4022 | | LWM16_MM_LWM32_MM = 1125, |
4023 | | LWP_MM = 1126, |
4024 | | LWR_MM = 1127, |
4025 | | LWU_MM = 1128, |
4026 | | LWXS_MM = 1129, |
4027 | | SB16_MM = 1130, |
4028 | | SC_MM = 1131, |
4029 | | SH16_MM_SH_MM = 1132, |
4030 | | SW16_MM_SWSP_MM_SW_MM = 1133, |
4031 | | SWL_MM = 1134, |
4032 | | SWM16_MM_SWM32_MM = 1135, |
4033 | | SWM_MM = 1136, |
4034 | | SWP_MM = 1137, |
4035 | | SWR_MM = 1138, |
4036 | | PREF_MM_PREFX_MM = 1139, |
4037 | | CACHE_MM = 1140, |
4038 | | SYNC_MM = 1141, |
4039 | | SYNCI_MM = 1142, |
4040 | | GINVI_MMR6 = 1143, |
4041 | | GINVT_MMR6 = 1144, |
4042 | | LBU_MMR6 = 1145, |
4043 | | LB_MMR6 = 1146, |
4044 | | LDC2_MMR6 = 1147, |
4045 | | LL_MMR6 = 1148, |
4046 | | LWM16_MMR6 = 1149, |
4047 | | LWC2_MMR6 = 1150, |
4048 | | LWPC_MMR6 = 1151, |
4049 | | LW_MMR6 = 1152, |
4050 | | SB16_MMR6_SB_MMR6 = 1153, |
4051 | | SDC2_MMR6 = 1154, |
4052 | | SH16_MMR6_SH_MMR6 = 1155, |
4053 | | SW16_MMR6_SWSP_MMR6_SW_MMR6 = 1156, |
4054 | | SWC2_MMR6 = 1157, |
4055 | | SWM16_MMR6 = 1158, |
4056 | | SYNC_MMR6 = 1159, |
4057 | | SYNCI_MMR6 = 1160, |
4058 | | PREF_MMR6 = 1161, |
4059 | | CACHE_MMR6 = 1162, |
4060 | | LD = 1163, |
4061 | | LL64_LLD = 1164, |
4062 | | LWu = 1165, |
4063 | | LB64 = 1166, |
4064 | | LBu64 = 1167, |
4065 | | LH64 = 1168, |
4066 | | LHu64 = 1169, |
4067 | | LW64 = 1170, |
4068 | | LWL64 = 1171, |
4069 | | LWR64 = 1172, |
4070 | | LDL = 1173, |
4071 | | LDR = 1174, |
4072 | | SD = 1175, |
4073 | | SC64_SCD = 1176, |
4074 | | SB64 = 1177, |
4075 | | SH64 = 1178, |
4076 | | SW64 = 1179, |
4077 | | SWL64 = 1180, |
4078 | | SWR64 = 1181, |
4079 | | SDL = 1182, |
4080 | | SDR = 1183, |
4081 | | LWUPC = 1184, |
4082 | | LDPC = 1185, |
4083 | | LLD_R6 = 1186, |
4084 | | LL64_R6 = 1187, |
4085 | | SC64_R6 = 1188, |
4086 | | SCD_R6 = 1189, |
4087 | | CRC32B = 1190, |
4088 | | CRC32H = 1191, |
4089 | | CRC32W = 1192, |
4090 | | CRC32CB = 1193, |
4091 | | CRC32CH = 1194, |
4092 | | CRC32CW = 1195, |
4093 | | CRC32D = 1196, |
4094 | | CRC32CD = 1197, |
4095 | | BADDu = 1198, |
4096 | | BBIT0_BBIT032_BBIT1_BBIT132 = 1199, |
4097 | | CINS_CINS32_CINS64_32_CINS_i32 = 1200, |
4098 | | DMFC2_OCTEON = 1201, |
4099 | | DMTC2_OCTEON = 1202, |
4100 | | DPOP_POP = 1203, |
4101 | | EXTS_EXTS32 = 1204, |
4102 | | MTM0_MTM1_MTM2_MTP0_MTP1_MTP2 = 1205, |
4103 | | SEQ_SNE = 1206, |
4104 | | SEQi_SNEi = 1207, |
4105 | | V3MULU_VMM0_VMULU = 1208, |
4106 | | DMUL = 1209, |
4107 | | SAA_SAAD = 1210, |
4108 | | ADDR_PS64 = 1211, |
4109 | | CVT_PS_PW64_CVT_PW_PS64 = 1212, |
4110 | | MULR_PS64 = 1213, |
4111 | | PseudoTRUNC_W_D_PseudoTRUNC_W_D32_PseudoTRUNC_W_S = 1214, |
4112 | | MOVT_I64 = 1215, |
4113 | | MOVF_I64 = 1216, |
4114 | | MOVZ_I64_S = 1217, |
4115 | | MOVN_I64_D64 = 1218, |
4116 | | MOVN_I64_S = 1219, |
4117 | | MOVZ_I64_D64 = 1220, |
4118 | | SELEQZ_S_SELNEZ_S = 1221, |
4119 | | SELEQZ_D_SELNEZ_D = 1222, |
4120 | | MAX_S_MAXA_S = 1223, |
4121 | | MAX_D_MAXA_D = 1224, |
4122 | | MIN_S_MINA_D = 1225, |
4123 | | MIN_D_MINA_S = 1226, |
4124 | | CLASS_S = 1227, |
4125 | | CLASS_D = 1228, |
4126 | | RINT_S = 1229, |
4127 | | RINT_D = 1230, |
4128 | | BC1EQZ_BC1NEZ = 1231, |
4129 | | SEL_D = 1232, |
4130 | | SEL_S = 1233, |
4131 | | MADDF_S = 1234, |
4132 | | MSUBF_S = 1235, |
4133 | | MADDF_D = 1236, |
4134 | | MSUBF_D = 1237, |
4135 | | MOVF_D32_MM = 1238, |
4136 | | MOVF_S_MM = 1239, |
4137 | | MOVN_I_D32_MM = 1240, |
4138 | | MOVN_I_S_MM = 1241, |
4139 | | MOVT_D32_MM = 1242, |
4140 | | MOVT_S_MM = 1243, |
4141 | | MOVZ_I_D32_MM = 1244, |
4142 | | MOVZ_I_S_MM = 1245, |
4143 | | CVT_D32_S_MM_CVT_D32_W_MM_CVT_D64_S_MM_CVT_D64_W_MM_CVT_L_D64_MM_CVT_L_S_MM_CVT_S_D32_MM_CVT_S_D64_MM_CVT_S_W_MM_CVT_W_D32_MM_CVT_W_D64_MM_CVT_W_S_MM = 1246, |
4144 | | CEIL_W_MM_CEIL_W_S_MM = 1247, |
4145 | | FLOOR_W_MM_FLOOR_W_S_MM = 1248, |
4146 | | NMADD_S_MM = 1249, |
4147 | | NMADD_D32_MM = 1250, |
4148 | | NMSUB_S_MM = 1251, |
4149 | | NMSUB_D32_MM = 1252, |
4150 | | MADD_S_MM = 1253, |
4151 | | MADD_D32_MM = 1254, |
4152 | | ROUND_W_MM_ROUND_W_S_MM = 1255, |
4153 | | TRUNC_W_MM_TRUNC_W_S_MM = 1256, |
4154 | | C_F_D32_MM_C_F_D64_MM = 1257, |
4155 | | C_F_S_MM = 1258, |
4156 | | C_EQ_D32_MM_C_EQ_D64_MM_C_LE_D32_MM_C_LE_D64_MM_C_LT_D32_MM_C_LT_D64_MM_C_SF_D32_MM_C_SF_D64_MM_C_UN_D32_MM_C_UN_D64_MM = 1259, |
4157 | | C_EQ_S_MM_C_LE_S_MM_C_LT_S_MM_C_SF_S_MM_C_UN_S_MM = 1260, |
4158 | | C_NGE_D32_MM_C_NGE_D64_MM_C_NGL_D32_MM_C_NGL_D64_MM_C_NGT_D32_MM_C_NGT_D64_MM_C_OLE_D32_MM_C_OLE_D64_MM_C_OLT_D32_MM_C_OLT_D64_MM_C_SEQ_D32_MM_C_SEQ_D64_MM_C_UEQ_D32_MM_C_UEQ_D64_MM_C_ULE_D32_MM_C_ULE_D64_MM_C_ULT_D32_MM_C_ULT_D64_MM = 1261, |
4159 | | C_NGE_S_MM_C_NGL_S_MM_C_NGT_S_MM_C_OLE_S_MM_C_OLT_S_MM_C_SEQ_S_MM_C_UEQ_S_MM_C_ULE_S_MM_C_ULT_S_MM = 1262, |
4160 | | C_NGLE_D32_MM_C_NGLE_D64_MM = 1263, |
4161 | | C_NGLE_S_MM = 1264, |
4162 | | FCMP_S32_MM = 1265, |
4163 | | FCMP_D32_MM = 1266, |
4164 | | MFC1_MM = 1267, |
4165 | | MFHC1_D32_MM_MFHC1_D64_MM = 1268, |
4166 | | MTC1_MM_MTC1_D64_MM = 1269, |
4167 | | MTHC1_D32_MM_MTHC1_D64_MM = 1270, |
4168 | | FABS_D32_MM_FABS_D64_MM = 1271, |
4169 | | FABS_S_MM = 1272, |
4170 | | FNEG_D32_MM_FNEG_D64_MM_FNEG_S_MM = 1273, |
4171 | | FADD_D32_MM_FADD_D64_MM = 1274, |
4172 | | FADD_S_MM = 1275, |
4173 | | FMOV_D32_MM_FMOV_D64_MM = 1276, |
4174 | | FMOV_S_MM = 1277, |
4175 | | FMUL_D32_MM_FMUL_D64_MM = 1278, |
4176 | | FMUL_S_MM = 1279, |
4177 | | FSUB_D32_MM_FSUB_D64_MM = 1280, |
4178 | | FSUB_S_MM = 1281, |
4179 | | MSUB_S_MM = 1282, |
4180 | | MSUB_D32_MM = 1283, |
4181 | | FDIV_S_MM = 1284, |
4182 | | FDIV_D32_MM_FDIV_D64_MM = 1285, |
4183 | | FSQRT_S_MM = 1286, |
4184 | | FSQRT_D32_MM_FSQRT_D64_MM = 1287, |
4185 | | RECIP_S_MM_RSQRT_S_MM = 1288, |
4186 | | RECIP_D32_MM_RECIP_D64_MM_RSQRT_D32_MM_RSQRT_D64_MM = 1289, |
4187 | | SDC1_MM_D32_SDC1_MM_D64 = 1290, |
4188 | | SWC1_MM = 1291, |
4189 | | SUXC1_MM = 1292, |
4190 | | SWXC1_MM = 1293, |
4191 | | CFC1_MM = 1294, |
4192 | | CTC1_MM = 1295, |
4193 | | LDC1_MM_D32_LDC1_MM_D64 = 1296, |
4194 | | LUXC1_MM = 1297, |
4195 | | LWC1_MM = 1298, |
4196 | | LWXC1_MM = 1299, |
4197 | | FNEG_S_MMR6 = 1300, |
4198 | | CMP_AF_D_MMR6_CMP_EQ_D_MMR6_CMP_LE_D_MMR6_CMP_LT_D_MMR6_CMP_UN_D_MMR6 = 1301, |
4199 | | CMP_AF_S_MMR6_CMP_EQ_S_MMR6_CMP_LE_S_MMR6_CMP_LT_S_MMR6_CMP_UN_S_MMR6 = 1302, |
4200 | | CMP_SAF_D_MMR6_CMP_SEQ_D_MMR6_CMP_SLE_D_MMR6_CMP_SLT_D_MMR6_CMP_SUN_D_MMR6_CMP_UEQ_D_MMR6_CMP_ULE_D_MMR6_CMP_ULT_D_MMR6 = 1303, |
4201 | | CMP_SAF_S_MMR6_CMP_SEQ_S_MMR6_CMP_SLE_S_MMR6_CMP_SLT_S_MMR6_CMP_SUN_S_MMR6_CMP_UEQ_S_MMR6_CMP_ULE_S_MMR6_CMP_ULT_S_MMR6 = 1304, |
4202 | | CMP_SUEQ_D_MMR6_CMP_SULE_D_MMR6_CMP_SULT_D_MMR6 = 1305, |
4203 | | CMP_SUEQ_S_MMR6_CMP_SULE_S_MMR6_CMP_SULT_S_MMR6 = 1306, |
4204 | | CVT_D_L_MMR6_CVT_L_D_MMR6_CVT_L_S_MMR6_CVT_S_L_MMR6_CVT_S_W_MMR6_CVT_W_S_MMR6 = 1307, |
4205 | | TRUNC_L_D_MMR6_TRUNC_L_S_MMR6_TRUNC_W_D_MMR6_TRUNC_W_S_MMR6 = 1308, |
4206 | | ROUND_L_D_MMR6_ROUND_L_S_MMR6_ROUND_W_D_MMR6_ROUND_W_S_MMR6 = 1309, |
4207 | | FLOOR_L_D_MMR6_FLOOR_L_S_MMR6_FLOOR_W_D_MMR6_FLOOR_W_S_MMR6 = 1310, |
4208 | | CEIL_L_D_MMR6_CEIL_L_S_MMR6_CEIL_W_D_MMR6_CEIL_W_S_MMR6 = 1311, |
4209 | | MFC1_MMR6 = 1312, |
4210 | | MTC1_MMR6 = 1313, |
4211 | | CLASS_S_MMR6_CLASS_D_MMR6 = 1314, |
4212 | | FADD_S_MMR6 = 1315, |
4213 | | MAX_D_MMR6 = 1316, |
4214 | | MAX_S_MMR6 = 1317, |
4215 | | MIN_D_MMR6 = 1318, |
4216 | | MIN_S_MMR6 = 1319, |
4217 | | MAXA_D_MMR6 = 1320, |
4218 | | MAXA_S_MMR6 = 1321, |
4219 | | MINA_D_MMR6 = 1322, |
4220 | | MINA_S_MMR6 = 1323, |
4221 | | SELEQZ_D_MMR6_SELNEZ_D_MMR6 = 1324, |
4222 | | SELEQZ_S_MMR6_SELNEZ_S_MMR6 = 1325, |
4223 | | SEL_D_MMR6 = 1326, |
4224 | | SEL_S_MMR6 = 1327, |
4225 | | RINT_S_MMR6_RINT_D_MMR6 = 1328, |
4226 | | MADDF_D_MMR6 = 1329, |
4227 | | MADDF_S_MMR6 = 1330, |
4228 | | MSUBF_D_MMR6 = 1331, |
4229 | | MSUBF_S_MMR6 = 1332, |
4230 | | FMOV_S_MMR6 = 1333, |
4231 | | FMUL_S_MMR6 = 1334, |
4232 | | FSUB_S_MMR6 = 1335, |
4233 | | FMOV_D_MMR6 = 1336, |
4234 | | FDIV_S_MMR6 = 1337, |
4235 | | SDC1_D64_MMR6 = 1338, |
4236 | | LDC1_D64_MMR6 = 1339, |
4237 | | DMFC1 = 1340, |
4238 | | DMTC1 = 1341, |
4239 | | SWDSP = 1342, |
4240 | | LWDSP = 1343, |
4241 | | PseudoMTLOHI_DSP = 1344, |
4242 | | EXTRV_RS_W = 1345, |
4243 | | EXTRV_R_W = 1346, |
4244 | | EXTRV_S_H = 1347, |
4245 | | EXTRV_W = 1348, |
4246 | | EXTR_RS_W = 1349, |
4247 | | EXTR_R_W = 1350, |
4248 | | EXTR_S_H = 1351, |
4249 | | EXTR_W = 1352, |
4250 | | INSV = 1353, |
4251 | | MTHLIP = 1354, |
4252 | | MTHI_DSP = 1355, |
4253 | | MTLO_DSP = 1356, |
4254 | | ABSQ_S_PH = 1357, |
4255 | | ABSQ_S_W = 1358, |
4256 | | ADDQ_PH = 1359, |
4257 | | ADDQ_S_PH = 1360, |
4258 | | ADDQ_S_W = 1361, |
4259 | | ADDSC = 1362, |
4260 | | ADDU_QB = 1363, |
4261 | | ADDU_S_QB = 1364, |
4262 | | ADDWC = 1365, |
4263 | | BITREV = 1366, |
4264 | | BPOSGE32 = 1367, |
4265 | | CMPGU_EQ_QB = 1368, |
4266 | | CMPGU_LE_QB = 1369, |
4267 | | CMPGU_LT_QB = 1370, |
4268 | | CMPU_EQ_QB = 1371, |
4269 | | CMPU_LE_QB = 1372, |
4270 | | CMPU_LT_QB = 1373, |
4271 | | CMP_EQ_PH = 1374, |
4272 | | CMP_LE_PH = 1375, |
4273 | | CMP_LT_PH = 1376, |
4274 | | DPAQ_SA_L_W = 1377, |
4275 | | DPAQ_S_W_PH = 1378, |
4276 | | DPAU_H_QBL = 1379, |
4277 | | DPAU_H_QBR = 1380, |
4278 | | DPSQ_SA_L_W = 1381, |
4279 | | DPSQ_S_W_PH = 1382, |
4280 | | DPSU_H_QBL = 1383, |
4281 | | DPSU_H_QBR = 1384, |
4282 | | EXTPDPV = 1385, |
4283 | | EXTPDP = 1386, |
4284 | | EXTPV = 1387, |
4285 | | EXTP = 1388, |
4286 | | LBUX = 1389, |
4287 | | LHX = 1390, |
4288 | | LWX = 1391, |
4289 | | MADDU_DSP = 1392, |
4290 | | MADD_DSP = 1393, |
4291 | | MAQ_SA_W_PHL = 1394, |
4292 | | MAQ_SA_W_PHR = 1395, |
4293 | | MAQ_S_W_PHL = 1396, |
4294 | | MAQ_S_W_PHR = 1397, |
4295 | | MFHI_DSP = 1398, |
4296 | | MFLO_DSP = 1399, |
4297 | | MODSUB = 1400, |
4298 | | MSUBU_DSP = 1401, |
4299 | | MSUB_DSP = 1402, |
4300 | | MULEQ_S_W_PHL = 1403, |
4301 | | MULEQ_S_W_PHR = 1404, |
4302 | | MULEU_S_PH_QBL = 1405, |
4303 | | MULEU_S_PH_QBR = 1406, |
4304 | | MULQ_RS_PH = 1407, |
4305 | | MULSAQ_S_W_PH = 1408, |
4306 | | MULTU_DSP = 1409, |
4307 | | MULT_DSP = 1410, |
4308 | | PACKRL_PH = 1411, |
4309 | | PICK_PH = 1412, |
4310 | | PICK_QB = 1413, |
4311 | | PRECEQU_PH_QBLA = 1414, |
4312 | | PRECEQU_PH_QBL = 1415, |
4313 | | PRECEQU_PH_QBRA = 1416, |
4314 | | PRECEQU_PH_QBR = 1417, |
4315 | | PRECEQ_W_PHL = 1418, |
4316 | | PRECEQ_W_PHR = 1419, |
4317 | | PRECEU_PH_QBLA = 1420, |
4318 | | PRECEU_PH_QBL = 1421, |
4319 | | PRECEU_PH_QBRA = 1422, |
4320 | | PRECEU_PH_QBR = 1423, |
4321 | | PRECRQU_S_QB_PH = 1424, |
4322 | | PRECRQ_PH_W = 1425, |
4323 | | PRECRQ_QB_PH = 1426, |
4324 | | PRECRQ_RS_PH_W = 1427, |
4325 | | RADDU_W_QB = 1428, |
4326 | | RDDSP = 1429, |
4327 | | REPLV_PH = 1430, |
4328 | | REPLV_QB = 1431, |
4329 | | REPL_PH = 1432, |
4330 | | REPL_QB = 1433, |
4331 | | SHILOV = 1434, |
4332 | | SHILO = 1435, |
4333 | | SHLLV_PH = 1436, |
4334 | | SHLLV_QB = 1437, |
4335 | | SHLLV_S_PH = 1438, |
4336 | | SHLLV_S_W = 1439, |
4337 | | SHLL_PH = 1440, |
4338 | | SHLL_QB = 1441, |
4339 | | SHLL_S_PH = 1442, |
4340 | | SHLL_S_W = 1443, |
4341 | | SHRAV_PH = 1444, |
4342 | | SHRAV_R_PH = 1445, |
4343 | | SHRAV_R_W = 1446, |
4344 | | SHRA_PH = 1447, |
4345 | | SHRA_R_PH = 1448, |
4346 | | SHRA_R_W = 1449, |
4347 | | SHRLV_QB = 1450, |
4348 | | SHRL_QB = 1451, |
4349 | | SUBQ_PH = 1452, |
4350 | | SUBQ_S_PH = 1453, |
4351 | | SUBQ_S_W = 1454, |
4352 | | SUBU_QB = 1455, |
4353 | | SUBU_S_QB = 1456, |
4354 | | WRDSP = 1457, |
4355 | | PseudoCMPU_EQ_QB_PseudoCMPU_LE_QB_PseudoCMPU_LT_QB_PseudoCMP_EQ_PH_PseudoCMP_LE_PH_PseudoCMP_LT_PH = 1458, |
4356 | | PseudoPICK_PH_PseudoPICK_QB = 1459, |
4357 | | ABSQ_S_QB = 1460, |
4358 | | ADDQH_PH = 1461, |
4359 | | ADDQH_R_PH = 1462, |
4360 | | ADDQH_R_W = 1463, |
4361 | | ADDQH_W = 1464, |
4362 | | ADDUH_QB = 1465, |
4363 | | ADDUH_R_QB = 1466, |
4364 | | ADDU_PH = 1467, |
4365 | | ADDU_S_PH = 1468, |
4366 | | APPEND = 1469, |
4367 | | BALIGN = 1470, |
4368 | | CMPGDU_EQ_QB = 1471, |
4369 | | CMPGDU_LE_QB = 1472, |
4370 | | CMPGDU_LT_QB = 1473, |
4371 | | DPA_W_PH = 1474, |
4372 | | DPAQX_SA_W_PH = 1475, |
4373 | | DPAQX_S_W_PH = 1476, |
4374 | | DPAX_W_PH = 1477, |
4375 | | DPS_W_PH = 1478, |
4376 | | DPSQX_S_W_PH = 1479, |
4377 | | DPSQX_SA_W_PH = 1480, |
4378 | | DPSX_W_PH = 1481, |
4379 | | MUL_PH = 1482, |
4380 | | MUL_S_PH = 1483, |
4381 | | MULQ_RS_W = 1484, |
4382 | | MULQ_S_PH = 1485, |
4383 | | MULQ_S_W = 1486, |
4384 | | MULSA_W_PH = 1487, |
4385 | | PRECR_QB_PH = 1488, |
4386 | | PRECR_SRA_PH_W = 1489, |
4387 | | PRECR_SRA_R_PH_W = 1490, |
4388 | | PREPEND = 1491, |
4389 | | SHRA_QB = 1492, |
4390 | | SHRA_R_QB = 1493, |
4391 | | SHRAV_QB = 1494, |
4392 | | SHRAV_R_QB = 1495, |
4393 | | SHRL_PH = 1496, |
4394 | | SHRLV_PH = 1497, |
4395 | | SUBQH_PH = 1498, |
4396 | | SUBQH_R_PH = 1499, |
4397 | | SUBQH_W = 1500, |
4398 | | SUBQH_R_W = 1501, |
4399 | | SUBU_PH = 1502, |
4400 | | SUBU_S_PH = 1503, |
4401 | | SUBUH_QB = 1504, |
4402 | | SUBUH_R_QB = 1505, |
4403 | | LWDSP_MM = 1506, |
4404 | | SWDSP_MM = 1507, |
4405 | | ABSQ_S_PH_MM = 1508, |
4406 | | ABSQ_S_W_MM = 1509, |
4407 | | ADDQ_PH_MM = 1510, |
4408 | | ADDQ_S_PH_MM = 1511, |
4409 | | ADDQ_S_W_MM = 1512, |
4410 | | ADDSC_MM = 1513, |
4411 | | ADDU_QB_MM = 1514, |
4412 | | ADDU_S_QB_MM = 1515, |
4413 | | ADDWC_MM = 1516, |
4414 | | BITREV_MM = 1517, |
4415 | | BPOSGE32_MM = 1518, |
4416 | | CMPGU_EQ_QB_MM = 1519, |
4417 | | CMPGU_LE_QB_MM = 1520, |
4418 | | CMPGU_LT_QB_MM = 1521, |
4419 | | CMPU_EQ_QB_MM = 1522, |
4420 | | CMPU_LE_QB_MM = 1523, |
4421 | | CMPU_LT_QB_MM = 1524, |
4422 | | CMP_EQ_PH_MM = 1525, |
4423 | | CMP_LE_PH_MM = 1526, |
4424 | | CMP_LT_PH_MM = 1527, |
4425 | | DPAQ_SA_L_W_MM = 1528, |
4426 | | DPAQ_S_W_PH_MM = 1529, |
4427 | | DPAU_H_QBL_MM = 1530, |
4428 | | DPAU_H_QBR_MM = 1531, |
4429 | | DPSQ_SA_L_W_MM = 1532, |
4430 | | DPSQ_S_W_PH_MM = 1533, |
4431 | | DPSU_H_QBL_MM = 1534, |
4432 | | DPSU_H_QBR_MM = 1535, |
4433 | | EXTPDPV_MM = 1536, |
4434 | | EXTPDP_MM = 1537, |
4435 | | EXTPV_MM = 1538, |
4436 | | EXTP_MM = 1539, |
4437 | | EXTRV_RS_W_MM = 1540, |
4438 | | EXTRV_R_W_MM = 1541, |
4439 | | EXTRV_S_H_MM = 1542, |
4440 | | EXTRV_W_MM = 1543, |
4441 | | EXTR_RS_W_MM = 1544, |
4442 | | EXTR_R_W_MM = 1545, |
4443 | | EXTR_S_H_MM = 1546, |
4444 | | EXTR_W_MM = 1547, |
4445 | | INSV_MM = 1548, |
4446 | | LBUX_MM = 1549, |
4447 | | LHX_MM = 1550, |
4448 | | LWX_MM = 1551, |
4449 | | MADDU_DSP_MM = 1552, |
4450 | | MADD_DSP_MM = 1553, |
4451 | | MAQ_SA_W_PHL_MM = 1554, |
4452 | | MAQ_SA_W_PHR_MM = 1555, |
4453 | | MAQ_S_W_PHL_MM = 1556, |
4454 | | MAQ_S_W_PHR_MM = 1557, |
4455 | | MFHI_DSP_MM = 1558, |
4456 | | MFLO_DSP_MM = 1559, |
4457 | | MODSUB_MM = 1560, |
4458 | | MOVEP_MMR6 = 1561, |
4459 | | MOVN_I_MM = 1562, |
4460 | | MOVZ_I_MM = 1563, |
4461 | | MSUBU_DSP_MM = 1564, |
4462 | | MSUB_DSP_MM = 1565, |
4463 | | MTHI_DSP_MM = 1566, |
4464 | | MTHLIP_MM = 1567, |
4465 | | MTLO_DSP_MM = 1568, |
4466 | | MULEQ_S_W_PHL_MM = 1569, |
4467 | | MULEQ_S_W_PHR_MM = 1570, |
4468 | | MULEU_S_PH_QBL_MM = 1571, |
4469 | | MULEU_S_PH_QBR_MM = 1572, |
4470 | | MULQ_RS_PH_MM = 1573, |
4471 | | MULSAQ_S_W_PH_MM = 1574, |
4472 | | MULTU_DSP_MM = 1575, |
4473 | | MULT_DSP_MM = 1576, |
4474 | | PACKRL_PH_MM = 1577, |
4475 | | PICK_PH_MM = 1578, |
4476 | | PICK_QB_MM = 1579, |
4477 | | PRECEQU_PH_QBLA_MM = 1580, |
4478 | | PRECEQU_PH_QBL_MM = 1581, |
4479 | | PRECEQU_PH_QBRA_MM = 1582, |
4480 | | PRECEQU_PH_QBR_MM = 1583, |
4481 | | PRECEQ_W_PHL_MM = 1584, |
4482 | | PRECEQ_W_PHR_MM = 1585, |
4483 | | PRECEU_PH_QBLA_MM = 1586, |
4484 | | PRECEU_PH_QBL_MM = 1587, |
4485 | | PRECEU_PH_QBRA_MM = 1588, |
4486 | | PRECEU_PH_QBR_MM = 1589, |
4487 | | PRECRQU_S_QB_PH_MM = 1590, |
4488 | | PRECRQ_PH_W_MM = 1591, |
4489 | | PRECRQ_QB_PH_MM = 1592, |
4490 | | PRECRQ_RS_PH_W_MM = 1593, |
4491 | | RADDU_W_QB_MM = 1594, |
4492 | | RDDSP_MM = 1595, |
4493 | | REPLV_PH_MM = 1596, |
4494 | | REPLV_QB_MM = 1597, |
4495 | | REPL_PH_MM = 1598, |
4496 | | REPL_QB_MM = 1599, |
4497 | | SHILOV_MM = 1600, |
4498 | | SHILO_MM = 1601, |
4499 | | SHLLV_PH_MM = 1602, |
4500 | | SHLLV_QB_MM = 1603, |
4501 | | SHLLV_S_PH_MM = 1604, |
4502 | | SHLLV_S_W_MM = 1605, |
4503 | | SHLL_PH_MM = 1606, |
4504 | | SHLL_QB_MM = 1607, |
4505 | | SHLL_S_PH_MM = 1608, |
4506 | | SHLL_S_W_MM = 1609, |
4507 | | SHRAV_PH_MM = 1610, |
4508 | | SHRAV_R_PH_MM = 1611, |
4509 | | SHRAV_R_W_MM = 1612, |
4510 | | SHRA_PH_MM = 1613, |
4511 | | SHRA_R_PH_MM = 1614, |
4512 | | SHRA_R_W_MM = 1615, |
4513 | | SHRLV_QB_MM = 1616, |
4514 | | SHRL_QB_MM = 1617, |
4515 | | SUBQ_PH_MM = 1618, |
4516 | | SUBQ_S_PH_MM = 1619, |
4517 | | SUBQ_S_W_MM = 1620, |
4518 | | SUBU_QB_MM = 1621, |
4519 | | SUBU_S_QB_MM = 1622, |
4520 | | WRDSP_MM = 1623, |
4521 | | ABSQ_S_QB_MMR2 = 1624, |
4522 | | ADDQH_PH_MMR2 = 1625, |
4523 | | ADDQH_R_PH_MMR2 = 1626, |
4524 | | ADDQH_R_W_MMR2 = 1627, |
4525 | | ADDQH_W_MMR2 = 1628, |
4526 | | ADDUH_QB_MMR2 = 1629, |
4527 | | ADDUH_R_QB_MMR2 = 1630, |
4528 | | ADDU_PH_MMR2 = 1631, |
4529 | | ADDU_S_PH_MMR2 = 1632, |
4530 | | APPEND_MMR2 = 1633, |
4531 | | BALIGN_MMR2 = 1634, |
4532 | | CMPGDU_EQ_QB_MMR2 = 1635, |
4533 | | CMPGDU_LE_QB_MMR2 = 1636, |
4534 | | CMPGDU_LT_QB_MMR2 = 1637, |
4535 | | DPA_W_PH_MMR2 = 1638, |
4536 | | DPAQX_SA_W_PH_MMR2 = 1639, |
4537 | | DPAQX_S_W_PH_MMR2 = 1640, |
4538 | | DPAX_W_PH_MMR2 = 1641, |
4539 | | DPS_W_PH_MMR2 = 1642, |
4540 | | DPSQX_S_W_PH_MMR2 = 1643, |
4541 | | DPSQX_SA_W_PH_MMR2 = 1644, |
4542 | | DPSX_W_PH_MMR2 = 1645, |
4543 | | MUL_PH_MMR2 = 1646, |
4544 | | MUL_S_PH_MMR2 = 1647, |
4545 | | MULQ_RS_W_MMR2 = 1648, |
4546 | | MULQ_S_PH_MMR2 = 1649, |
4547 | | MULQ_S_W_MMR2 = 1650, |
4548 | | MULSA_W_PH_MMR2 = 1651, |
4549 | | PRECR_QB_PH_MMR2 = 1652, |
4550 | | PRECR_SRA_PH_W_MMR2 = 1653, |
4551 | | PRECR_SRA_R_PH_W_MMR2 = 1654, |
4552 | | PREPEND_MMR2 = 1655, |
4553 | | SHRA_QB_MMR2 = 1656, |
4554 | | SHRA_R_QB_MMR2 = 1657, |
4555 | | SHRAV_QB_MMR2 = 1658, |
4556 | | SHRAV_R_QB_MMR2 = 1659, |
4557 | | SHRL_PH_MMR2 = 1660, |
4558 | | SHRLV_PH_MMR2 = 1661, |
4559 | | SUBQH_PH_MMR2 = 1662, |
4560 | | SUBQH_R_PH_MMR2 = 1663, |
4561 | | SUBQH_W_MMR2 = 1664, |
4562 | | SUBQH_R_W_MMR2 = 1665, |
4563 | | SUBU_PH_MMR2 = 1666, |
4564 | | SUBU_S_PH_MMR2 = 1667, |
4565 | | SUBUH_QB_MMR2 = 1668, |
4566 | | SUBUH_R_QB_MMR2 = 1669, |
4567 | | BPOSGE32C_MMR3 = 1670, |
4568 | | CMP_F_D = 1671, |
4569 | | CMP_F_S = 1672, |
4570 | | CMP_SAF_D = 1673, |
4571 | | CMP_SAF_S = 1674, |
4572 | | CMP_SEQ_D = 1675, |
4573 | | CMP_SEQ_S = 1676, |
4574 | | CMP_SLE_D = 1677, |
4575 | | CMP_SLE_S = 1678, |
4576 | | CMP_SLT_D = 1679, |
4577 | | CMP_SLT_S = 1680, |
4578 | | CMP_SUEQ_D = 1681, |
4579 | | CMP_SUEQ_S = 1682, |
4580 | | CMP_SULE_D = 1683, |
4581 | | CMP_SULE_S = 1684, |
4582 | | CMP_SULT_D = 1685, |
4583 | | CMP_SULT_S = 1686, |
4584 | | CMP_SUN_D = 1687, |
4585 | | CMP_SUN_S = 1688, |
4586 | | SCHED_LIST_END = 1689 |
4587 | | }; |
4588 | | } // end namespace Sched |
4589 | | } // end namespace Mips |
4590 | | } // end namespace llvm |
4591 | | #endif // GET_INSTRINFO_SCHED_ENUM |
4592 | | |
4593 | | #if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
4594 | | namespace llvm { |
4595 | | |
4596 | | struct MipsInstrTable { |
4597 | | MCInstrDesc Insts[2868]; |
4598 | | static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo"); |
4599 | | MCOperandInfo OperandInfo[1130]; |
4600 | | static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps"); |
4601 | | MCPhysReg ImplicitOps[67]; |
4602 | | }; |
4603 | | |
4604 | | } // end namespace llvm |
4605 | | #endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR) |
4606 | | |
4607 | | #ifdef GET_INSTRINFO_MC_DESC |
4608 | | #undef GET_INSTRINFO_MC_DESC |
4609 | | namespace llvm { |
4610 | | |
4611 | | static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0); |
4612 | | static constexpr unsigned MipsImpOpBase = sizeof MipsInstrTable::OperandInfo / (sizeof(MCPhysReg)); |
4613 | | |
4614 | | extern const MipsInstrTable MipsDescs = { |
4615 | | { |
4616 | | { 2867, 2, 1, 4, 1065, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2867 = YIELD |
4617 | | { 2866, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 576, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2866 = XorRxRxRy16 |
4618 | | { 2865, 3, 1, 4, 773, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2865 = XORi_MM |
4619 | | { 2864, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2864 = XORi64 |
4620 | | { 2863, 3, 1, 4, 508, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2863 = XORi |
4621 | | { 2862, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2862 = XOR_V |
4622 | | { 2861, 3, 1, 4, 804, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2861 = XOR_MMR6 |
4623 | | { 2860, 3, 1, 4, 772, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2860 = XOR_MM |
4624 | | { 2859, 3, 1, 4, 805, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2859 = XORI_MMR6 |
4625 | | { 2858, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2858 = XORI_B |
4626 | | { 2857, 3, 1, 4, 815, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2857 = XOR64 |
4627 | | { 2856, 3, 1, 2, 804, 0, 0, MipsImpOpBase + 0, 561, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2856 = XOR16_MMR6 |
4628 | | { 2855, 3, 1, 2, 772, 0, 0, MipsImpOpBase + 0, 561, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2855 = XOR16_MM |
4629 | | { 2854, 3, 1, 4, 371, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2854 = XOR |
4630 | | { 2853, 2, 1, 4, 803, 0, 0, MipsImpOpBase + 0, 140, 0, 0x6ULL }, // Inst #2853 = WSBH_MMR6 |
4631 | | { 2852, 2, 1, 4, 771, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2852 = WSBH_MM |
4632 | | { 2851, 2, 1, 4, 481, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2851 = WSBH |
4633 | | { 2850, 2, 1, 4, 1037, 0, 0, MipsImpOpBase + 0, 140, 0, 0x6ULL }, // Inst #2850 = WRPGPR_MMR6 |
4634 | | { 2849, 2, 0, 4, 1623, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2849 = WRDSP_MM |
4635 | | { 2848, 2, 0, 4, 1457, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2848 = WRDSP |
4636 | | { 2847, 1, 0, 4, 1052, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2847 = WAIT_MMR6 |
4637 | | { 2846, 1, 0, 4, 1035, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2846 = WAIT_MM |
4638 | | { 2845, 0, 0, 4, 404, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2845 = WAIT |
4639 | | { 2844, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2844 = VSHF_W |
4640 | | { 2843, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #2843 = VSHF_H |
4641 | | { 2842, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2842 = VSHF_D |
4642 | | { 2841, 4, 1, 4, 515, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #2841 = VSHF_B |
4643 | | { 2840, 3, 1, 4, 1208, 0, 5, MipsImpOpBase + 62, 223, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2840 = VMULU |
4644 | | { 2839, 3, 1, 4, 1208, 0, 4, MipsImpOpBase + 42, 223, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2839 = VMM0 |
4645 | | { 2838, 3, 1, 4, 1208, 0, 3, MipsImpOpBase + 59, 223, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2838 = V3MULU |
4646 | | { 2837, 2, 0, 4, 886, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2837 = UDIV_MM |
4647 | | { 2836, 2, 0, 4, 866, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2836 = UDIV |
4648 | | { 2835, 2, 0, 4, 403, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2835 = TTLTIU |
4649 | | { 2834, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2834 = TRUNC_W_S_MMR6 |
4650 | | { 2833, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2833 = TRUNC_W_S_MM |
4651 | | { 2832, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2832 = TRUNC_W_S |
4652 | | { 2831, 2, 1, 4, 1256, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2831 = TRUNC_W_MM |
4653 | | { 2830, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #2830 = TRUNC_W_D_MMR6 |
4654 | | { 2829, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #2829 = TRUNC_W_D64 |
4655 | | { 2828, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2828 = TRUNC_W_D32 |
4656 | | { 2827, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2827 = TRUNC_L_S_MMR6 |
4657 | | { 2826, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2826 = TRUNC_L_S |
4658 | | { 2825, 2, 1, 4, 1308, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2825 = TRUNC_L_D_MMR6 |
4659 | | { 2824, 2, 1, 4, 637, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2824 = TRUNC_L_D64 |
4660 | | { 2823, 3, 0, 4, 980, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2823 = TNE_MM |
4661 | | { 2822, 2, 0, 4, 979, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2822 = TNEI_MM |
4662 | | { 2821, 2, 0, 4, 401, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2821 = TNEI |
4663 | | { 2820, 3, 0, 4, 400, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2820 = TNE |
4664 | | { 2819, 3, 0, 4, 978, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2819 = TLT_MM |
4665 | | { 2818, 3, 0, 4, 977, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2818 = TLTU_MM |
4666 | | { 2817, 3, 0, 4, 399, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2817 = TLTU |
4667 | | { 2816, 2, 0, 4, 976, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2816 = TLTI_MM |
4668 | | { 2815, 2, 0, 4, 975, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2815 = TLTIU_MM |
4669 | | { 2814, 2, 0, 4, 398, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2814 = TLTI |
4670 | | { 2813, 3, 0, 4, 397, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2813 = TLT |
4671 | | { 2812, 0, 0, 4, 1030, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2812 = TLBWR_MM |
4672 | | { 2811, 0, 0, 4, 415, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2811 = TLBWR |
4673 | | { 2810, 0, 0, 4, 1029, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2810 = TLBWI_MM |
4674 | | { 2809, 0, 0, 4, 414, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2809 = TLBWI |
4675 | | { 2808, 0, 0, 4, 1028, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2808 = TLBR_MM |
4676 | | { 2807, 0, 0, 4, 413, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2807 = TLBR |
4677 | | { 2806, 0, 0, 4, 1027, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2806 = TLBP_MM |
4678 | | { 2805, 0, 0, 4, 412, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2805 = TLBP |
4679 | | { 2804, 0, 0, 4, 1038, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2804 = TLBINV_MMR6 |
4680 | | { 2803, 0, 0, 4, 1039, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2803 = TLBINVF_MMR6 |
4681 | | { 2802, 0, 0, 4, 411, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2802 = TLBINVF |
4682 | | { 2801, 0, 0, 4, 410, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2801 = TLBINV |
4683 | | { 2800, 0, 0, 4, 1075, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2800 = TLBGWR_MM |
4684 | | { 2799, 0, 0, 4, 430, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2799 = TLBGWR |
4685 | | { 2798, 0, 0, 4, 1074, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2798 = TLBGWI_MM |
4686 | | { 2797, 0, 0, 4, 429, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2797 = TLBGWI |
4687 | | { 2796, 0, 0, 4, 1073, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2796 = TLBGR_MM |
4688 | | { 2795, 0, 0, 4, 428, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2795 = TLBGR |
4689 | | { 2794, 0, 0, 4, 1072, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2794 = TLBGP_MM |
4690 | | { 2793, 0, 0, 4, 427, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2793 = TLBGP |
4691 | | { 2792, 0, 0, 4, 1071, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2792 = TLBGINV_MM |
4692 | | { 2791, 0, 0, 4, 1070, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2791 = TLBGINVF_MM |
4693 | | { 2790, 0, 0, 4, 426, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2790 = TLBGINVF |
4694 | | { 2789, 0, 0, 4, 425, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2789 = TLBGINV |
4695 | | { 2788, 3, 0, 4, 974, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2788 = TGE_MM |
4696 | | { 2787, 3, 0, 4, 973, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2787 = TGEU_MM |
4697 | | { 2786, 3, 0, 4, 396, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2786 = TGEU |
4698 | | { 2785, 2, 0, 4, 972, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2785 = TGEI_MM |
4699 | | { 2784, 2, 0, 4, 971, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2784 = TGEIU_MM |
4700 | | { 2783, 2, 0, 4, 395, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2783 = TGEIU |
4701 | | { 2782, 2, 0, 4, 394, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2782 = TGEI |
4702 | | { 2781, 3, 0, 4, 393, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2781 = TGE |
4703 | | { 2780, 3, 0, 4, 970, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2780 = TEQ_MM |
4704 | | { 2779, 2, 0, 4, 969, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2779 = TEQI_MM |
4705 | | { 2778, 2, 0, 4, 392, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2778 = TEQI |
4706 | | { 2777, 3, 0, 4, 391, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2777 = TEQ |
4707 | | { 2776, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2776 = SwRxSpImmX16 |
4708 | | { 2775, 3, 0, 4, 1117, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2775 = SwRxRyOffMemX16 |
4709 | | { 2774, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 396, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2774 = SubuRxRyRz16 |
4710 | | { 2773, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 576, 0, 0x0ULL }, // Inst #2773 = SrlvRxRy16 |
4711 | | { 2772, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 520, 0, 0x0ULL }, // Inst #2772 = SrlX16 |
4712 | | { 2771, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 576, 0, 0x0ULL }, // Inst #2771 = SravRxRy16 |
4713 | | { 2770, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 520, 0, 0x0ULL }, // Inst #2770 = SraX16 |
4714 | | { 2769, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 394, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2769 = SltuRxRy16 |
4715 | | { 2768, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2768 = SltiuRxImmX16 |
4716 | | { 2767, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2767 = SltiuRxImm16 |
4717 | | { 2766, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2766 = SltiRxImmX16 |
4718 | | { 2765, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2765 = SltiRxImm16 |
4719 | | { 2764, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 394, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2764 = SltRxRy16 |
4720 | | { 2763, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 576, 0, 0x0ULL }, // Inst #2763 = SllvRxRy16 |
4721 | | { 2762, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 520, 0, 0x0ULL }, // Inst #2762 = SllX16 |
4722 | | { 2761, 3, 0, 4, 1116, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2761 = ShRxRyOffMemX16 |
4723 | | { 2760, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1128, 0, 0x0ULL }, // Inst #2760 = SehRx16 |
4724 | | { 2759, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1128, 0, 0x0ULL }, // Inst #2759 = SebRx16 |
4725 | | { 2758, 3, 0, 4, 1115, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2758 = SbRxRyOffMemX16 |
4726 | | { 2757, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2757 = SaveX16 |
4727 | | { 2756, 0, 0, 2, 1114, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2756 = Save16 |
4728 | | { 2755, 1, 0, 4, 968, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2755 = SYSCALL_MM |
4729 | | { 2754, 1, 0, 4, 390, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2754 = SYSCALL |
4730 | | { 2753, 1, 0, 4, 1159, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2753 = SYNC_MMR6 |
4731 | | { 2752, 1, 0, 4, 1141, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2752 = SYNC_MM |
4732 | | { 2751, 2, 0, 4, 1160, 0, 0, MipsImpOpBase + 0, 1126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2751 = SYNCI_MMR6 |
4733 | | { 2750, 2, 0, 4, 1142, 0, 0, MipsImpOpBase + 0, 1126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2750 = SYNCI_MM |
4734 | | { 2749, 2, 0, 4, 473, 0, 0, MipsImpOpBase + 0, 1126, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2749 = SYNCI |
4735 | | { 2748, 1, 0, 4, 472, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2748 = SYNC |
4736 | | { 2747, 3, 0, 4, 1156, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2747 = SW_MMR6 |
4737 | | { 2746, 3, 0, 4, 1133, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2746 = SW_MM |
4738 | | { 2745, 3, 0, 4, 1293, 0, 0, MipsImpOpBase + 0, 911, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2745 = SWXC1_MM |
4739 | | { 2744, 3, 0, 4, 702, 0, 0, MipsImpOpBase + 0, 911, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2744 = SWXC1 |
4740 | | { 2743, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 908, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2743 = SWSP_MMR6 |
4741 | | { 2742, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 908, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2742 = SWSP_MM |
4742 | | { 2741, 3, 0, 4, 1138, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2741 = SWR_MM |
4743 | | { 2740, 3, 0, 4, 1104, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2740 = SWRE_MM |
4744 | | { 2739, 3, 0, 4, 467, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2739 = SWRE |
4745 | | { 2738, 3, 0, 4, 1181, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2738 = SWR64 |
4746 | | { 2737, 3, 0, 4, 465, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2737 = SWR |
4747 | | { 2736, 4, 0, 4, 1137, 0, 0, MipsImpOpBase + 0, 904, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2736 = SWP_MM |
4748 | | { 2735, 3, 0, 4, 1135, 0, 0, MipsImpOpBase + 0, 349, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2735 = SWM32_MM |
4749 | | { 2734, 3, 0, 2, 1158, 0, 0, MipsImpOpBase + 0, 901, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2734 = SWM16_MMR6 |
4750 | | { 2733, 3, 0, 2, 1135, 0, 0, MipsImpOpBase + 0, 901, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2733 = SWM16_MM |
4751 | | { 2732, 3, 0, 4, 1134, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2732 = SWL_MM |
4752 | | { 2731, 3, 0, 4, 1103, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2731 = SWLE_MM |
4753 | | { 2730, 3, 0, 4, 466, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2730 = SWLE |
4754 | | { 2729, 3, 0, 4, 1180, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2729 = SWL64 |
4755 | | { 2728, 3, 0, 4, 464, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2728 = SWL |
4756 | | { 2727, 3, 0, 4, 1102, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2727 = SWE_MM |
4757 | | { 2726, 3, 0, 4, 462, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2726 = SWE |
4758 | | { 2725, 3, 0, 4, 1507, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2725 = SWDSP_MM |
4759 | | { 2724, 3, 0, 4, 1342, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2724 = SWDSP |
4760 | | { 2723, 3, 0, 4, 456, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2723 = SWC3 |
4761 | | { 2722, 3, 0, 4, 1084, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2722 = SWC2_R6 |
4762 | | { 2721, 3, 0, 4, 1157, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2721 = SWC2_MMR6 |
4763 | | { 2720, 3, 0, 4, 455, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2720 = SWC2 |
4764 | | { 2719, 3, 0, 4, 1291, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2719 = SWC1_MM |
4765 | | { 2718, 3, 0, 4, 701, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2718 = SWC1 |
4766 | | { 2717, 3, 0, 4, 1179, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2717 = SW64 |
4767 | | { 2716, 3, 0, 2, 1156, 0, 0, MipsImpOpBase + 0, 1060, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2716 = SW16_MMR6 |
4768 | | { 2715, 3, 0, 2, 1133, 0, 0, MipsImpOpBase + 0, 1060, 0|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #2715 = SW16_MM |
4769 | | { 2714, 3, 0, 4, 454, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2714 = SW |
4770 | | { 2713, 3, 0, 4, 1292, 0, 0, MipsImpOpBase + 0, 867, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2713 = SUXC1_MM |
4771 | | { 2712, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 867, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2712 = SUXC164 |
4772 | | { 2711, 3, 0, 4, 703, 0, 0, MipsImpOpBase + 0, 864, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #2711 = SUXC1 |
4773 | | { 2710, 3, 1, 4, 769, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2710 = SUBu_MM |
4774 | | { 2709, 3, 1, 4, 370, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2709 = SUBu |
4775 | | { 2708, 3, 1, 4, 802, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2708 = SUB_MMR6 |
4776 | | { 2707, 3, 1, 4, 770, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2707 = SUB_MM |
4777 | | { 2706, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2706 = SUBV_W |
4778 | | { 2705, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2705 = SUBV_H |
4779 | | { 2704, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2704 = SUBV_D |
4780 | | { 2703, 3, 1, 4, 612, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2703 = SUBV_B |
4781 | | { 2702, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2702 = SUBVI_W |
4782 | | { 2701, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2701 = SUBVI_H |
4783 | | { 2700, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2700 = SUBVI_D |
4784 | | { 2699, 3, 1, 4, 611, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2699 = SUBVI_B |
4785 | | { 2698, 3, 1, 4, 1622, 0, 1, MipsImpOpBase + 10, 533, 0, 0x6ULL }, // Inst #2698 = SUBU_S_QB_MM |
4786 | | { 2697, 3, 1, 4, 1456, 0, 1, MipsImpOpBase + 10, 533, 0, 0x6ULL }, // Inst #2697 = SUBU_S_QB |
4787 | | { 2696, 3, 1, 4, 1667, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2696 = SUBU_S_PH_MMR2 |
4788 | | { 2695, 3, 1, 4, 1503, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2695 = SUBU_S_PH |
4789 | | { 2694, 3, 1, 4, 1621, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2694 = SUBU_QB_MM |
4790 | | { 2693, 3, 1, 4, 1455, 0, 1, MipsImpOpBase + 10, 533, 0, 0x6ULL }, // Inst #2693 = SUBU_QB |
4791 | | { 2692, 3, 1, 4, 1666, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2692 = SUBU_PH_MMR2 |
4792 | | { 2691, 3, 1, 4, 1502, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2691 = SUBU_PH |
4793 | | { 2690, 3, 1, 4, 801, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2690 = SUBU_MMR6 |
4794 | | { 2689, 3, 1, 4, 1669, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2689 = SUBUH_R_QB_MMR2 |
4795 | | { 2688, 3, 1, 4, 1505, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2688 = SUBUH_R_QB |
4796 | | { 2687, 3, 1, 4, 1668, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2687 = SUBUH_QB_MMR2 |
4797 | | { 2686, 3, 1, 4, 1504, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2686 = SUBUH_QB |
4798 | | { 2685, 3, 1, 2, 801, 0, 0, MipsImpOpBase + 0, 542, 0, 0x0ULL }, // Inst #2685 = SUBU16_MMR6 |
4799 | | { 2684, 3, 1, 2, 769, 0, 0, MipsImpOpBase + 0, 542, 0, 0x0ULL }, // Inst #2684 = SUBU16_MM |
4800 | | { 2683, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2683 = SUBS_U_W |
4801 | | { 2682, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2682 = SUBS_U_H |
4802 | | { 2681, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2681 = SUBS_U_D |
4803 | | { 2680, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2680 = SUBS_U_B |
4804 | | { 2679, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2679 = SUBS_S_W |
4805 | | { 2678, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2678 = SUBS_S_H |
4806 | | { 2677, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2677 = SUBS_S_D |
4807 | | { 2676, 3, 1, 4, 608, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2676 = SUBS_S_B |
4808 | | { 2675, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2675 = SUBSUU_S_W |
4809 | | { 2674, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2674 = SUBSUU_S_H |
4810 | | { 2673, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2673 = SUBSUU_S_D |
4811 | | { 2672, 3, 1, 4, 610, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2672 = SUBSUU_S_B |
4812 | | { 2671, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2671 = SUBSUS_U_W |
4813 | | { 2670, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2670 = SUBSUS_U_H |
4814 | | { 2669, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2669 = SUBSUS_U_D |
4815 | | { 2668, 3, 1, 4, 609, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2668 = SUBSUS_U_B |
4816 | | { 2667, 3, 1, 4, 1620, 0, 1, MipsImpOpBase + 10, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2667 = SUBQ_S_W_MM |
4817 | | { 2666, 3, 1, 4, 1454, 0, 1, MipsImpOpBase + 10, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2666 = SUBQ_S_W |
4818 | | { 2665, 3, 1, 4, 1619, 0, 1, MipsImpOpBase + 10, 533, 0, 0x6ULL }, // Inst #2665 = SUBQ_S_PH_MM |
4819 | | { 2664, 3, 1, 4, 1453, 0, 1, MipsImpOpBase + 10, 533, 0, 0x6ULL }, // Inst #2664 = SUBQ_S_PH |
4820 | | { 2663, 3, 1, 4, 1618, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2663 = SUBQ_PH_MM |
4821 | | { 2662, 3, 1, 4, 1452, 0, 1, MipsImpOpBase + 10, 533, 0, 0x6ULL }, // Inst #2662 = SUBQ_PH |
4822 | | { 2661, 3, 1, 4, 1664, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2661 = SUBQH_W_MMR2 |
4823 | | { 2660, 3, 1, 4, 1500, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2660 = SUBQH_W |
4824 | | { 2659, 3, 1, 4, 1665, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2659 = SUBQH_R_W_MMR2 |
4825 | | { 2658, 3, 1, 4, 1501, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2658 = SUBQH_R_W |
4826 | | { 2657, 3, 1, 4, 1663, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2657 = SUBQH_R_PH_MMR2 |
4827 | | { 2656, 3, 1, 4, 1499, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2656 = SUBQH_R_PH |
4828 | | { 2655, 3, 1, 4, 1662, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2655 = SUBQH_PH_MMR2 |
4829 | | { 2654, 3, 1, 4, 1498, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2654 = SUBQH_PH |
4830 | | { 2653, 3, 1, 4, 369, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2653 = SUB |
4831 | | { 2652, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2652 = ST_W |
4832 | | { 2651, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2651 = ST_H |
4833 | | { 2650, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 873, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2650 = ST_D |
4834 | | { 2649, 3, 0, 4, 704, 0, 0, MipsImpOpBase + 0, 870, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2649 = ST_B |
4835 | | { 2648, 0, 0, 4, 800, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2648 = SSNOP_MMR6 |
4836 | | { 2647, 0, 0, 4, 768, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2647 = SSNOP_MM |
4837 | | { 2646, 0, 0, 4, 372, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2646 = SSNOP |
4838 | | { 2645, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2645 = SRL_W |
4839 | | { 2644, 3, 1, 4, 766, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2644 = SRL_MM |
4840 | | { 2643, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2643 = SRL_H |
4841 | | { 2642, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2642 = SRL_D |
4842 | | { 2641, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2641 = SRL_B |
4843 | | { 2640, 3, 1, 4, 767, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2640 = SRLV_MM |
4844 | | { 2639, 3, 1, 4, 512, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2639 = SRLV |
4845 | | { 2638, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2638 = SRLR_W |
4846 | | { 2637, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2637 = SRLR_H |
4847 | | { 2636, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2636 = SRLR_D |
4848 | | { 2635, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2635 = SRLR_B |
4849 | | { 2634, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2634 = SRLRI_W |
4850 | | { 2633, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2633 = SRLRI_H |
4851 | | { 2632, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2632 = SRLRI_D |
4852 | | { 2631, 3, 1, 4, 624, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2631 = SRLRI_B |
4853 | | { 2630, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2630 = SRLI_W |
4854 | | { 2629, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2629 = SRLI_H |
4855 | | { 2628, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2628 = SRLI_D |
4856 | | { 2627, 3, 1, 4, 622, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2627 = SRLI_B |
4857 | | { 2626, 3, 1, 2, 799, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2626 = SRL16_MMR6 |
4858 | | { 2625, 3, 1, 2, 766, 0, 0, MipsImpOpBase + 0, 527, 0, 0x0ULL }, // Inst #2625 = SRL16_MM |
4859 | | { 2624, 3, 1, 4, 507, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2624 = SRL |
4860 | | { 2623, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2623 = SRA_W |
4861 | | { 2622, 3, 1, 4, 765, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2622 = SRA_MM |
4862 | | { 2621, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2621 = SRA_H |
4863 | | { 2620, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2620 = SRA_D |
4864 | | { 2619, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2619 = SRA_B |
4865 | | { 2618, 3, 1, 4, 764, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2618 = SRAV_MM |
4866 | | { 2617, 3, 1, 4, 511, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2617 = SRAV |
4867 | | { 2616, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2616 = SRAR_W |
4868 | | { 2615, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2615 = SRAR_H |
4869 | | { 2614, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2614 = SRAR_D |
4870 | | { 2613, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2613 = SRAR_B |
4871 | | { 2612, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2612 = SRARI_W |
4872 | | { 2611, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2611 = SRARI_H |
4873 | | { 2610, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2610 = SRARI_D |
4874 | | { 2609, 3, 1, 4, 623, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2609 = SRARI_B |
4875 | | { 2608, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2608 = SRAI_W |
4876 | | { 2607, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2607 = SRAI_H |
4877 | | { 2606, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2606 = SRAI_D |
4878 | | { 2605, 3, 1, 4, 621, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2605 = SRAI_B |
4879 | | { 2604, 3, 1, 4, 506, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2604 = SRA |
4880 | | { 2603, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1123, 0, 0x6ULL }, // Inst #2603 = SPLAT_W |
4881 | | { 2602, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1120, 0, 0x6ULL }, // Inst #2602 = SPLAT_H |
4882 | | { 2601, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1117, 0, 0x6ULL }, // Inst #2601 = SPLAT_D |
4883 | | { 2600, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 1114, 0, 0x6ULL }, // Inst #2600 = SPLAT_B |
4884 | | { 2599, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2599 = SPLATI_W |
4885 | | { 2598, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2598 = SPLATI_H |
4886 | | { 2597, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2597 = SPLATI_D |
4887 | | { 2596, 3, 1, 4, 545, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2596 = SPLATI_B |
4888 | | { 2595, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 220, 0, 0x2ULL }, // Inst #2595 = SNEi |
4889 | | { 2594, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 223, 0, 0x1ULL }, // Inst #2594 = SNE |
4890 | | { 2593, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2593 = SLTu_MM |
4891 | | { 2592, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1108, 0, 0x1ULL }, // Inst #2592 = SLTu64 |
4892 | | { 2591, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2591 = SLTu |
4893 | | { 2590, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 229, 0, 0x2ULL }, // Inst #2590 = SLTiu_MM |
4894 | | { 2589, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1111, 0, 0x2ULL }, // Inst #2589 = SLTiu64 |
4895 | | { 2588, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 229, 0, 0x2ULL }, // Inst #2588 = SLTiu |
4896 | | { 2587, 3, 1, 4, 763, 0, 0, MipsImpOpBase + 0, 229, 0, 0x2ULL }, // Inst #2587 = SLTi_MM |
4897 | | { 2586, 3, 1, 4, 814, 0, 0, MipsImpOpBase + 0, 1111, 0, 0x2ULL }, // Inst #2586 = SLTi64 |
4898 | | { 2585, 3, 1, 4, 368, 0, 0, MipsImpOpBase + 0, 229, 0, 0x2ULL }, // Inst #2585 = SLTi |
4899 | | { 2584, 3, 1, 4, 762, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2584 = SLT_MM |
4900 | | { 2583, 3, 1, 4, 813, 0, 0, MipsImpOpBase + 0, 1108, 0, 0x1ULL }, // Inst #2583 = SLT64 |
4901 | | { 2582, 3, 1, 4, 504, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2582 = SLT |
4902 | | { 2581, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2581 = SLL_W |
4903 | | { 2580, 3, 1, 4, 798, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2580 = SLL_MMR6 |
4904 | | { 2579, 3, 1, 4, 760, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2579 = SLL_MM |
4905 | | { 2578, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2578 = SLL_H |
4906 | | { 2577, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2577 = SLL_D |
4907 | | { 2576, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2576 = SLL_B |
4908 | | { 2575, 3, 1, 4, 761, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2575 = SLLV_MM |
4909 | | { 2574, 3, 1, 4, 510, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2574 = SLLV |
4910 | | { 2573, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2573 = SLLI_W |
4911 | | { 2572, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2572 = SLLI_H |
4912 | | { 2571, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2571 = SLLI_D |
4913 | | { 2570, 3, 1, 4, 625, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2570 = SLLI_B |
4914 | | { 2569, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 377, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2569 = SLL64_64 |
4915 | | { 2568, 2, 1, 4, 812, 0, 0, MipsImpOpBase + 0, 746, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2568 = SLL64_32 |
4916 | | { 2567, 3, 1, 2, 798, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2567 = SLL16_MMR6 |
4917 | | { 2566, 3, 1, 2, 760, 0, 0, MipsImpOpBase + 0, 527, 0, 0x0ULL }, // Inst #2566 = SLL16_MM |
4918 | | { 2565, 3, 1, 4, 505, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2565 = SLL |
4919 | | { 2564, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1104, 0, 0x6ULL }, // Inst #2564 = SLD_W |
4920 | | { 2563, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1100, 0, 0x6ULL }, // Inst #2563 = SLD_H |
4921 | | { 2562, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1096, 0, 0x6ULL }, // Inst #2562 = SLD_D |
4922 | | { 2561, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 1092, 0, 0x6ULL }, // Inst #2561 = SLD_B |
4923 | | { 2560, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #2560 = SLDI_W |
4924 | | { 2559, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #2559 = SLDI_H |
4925 | | { 2558, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #2558 = SLDI_D |
4926 | | { 2557, 4, 1, 4, 519, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #2557 = SLDI_B |
4927 | | { 2556, 1, 0, 4, 996, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2556 = SIGRIE_MMR6 |
4928 | | { 2555, 1, 0, 4, 935, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2555 = SIGRIE |
4929 | | { 2554, 3, 0, 4, 1155, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2554 = SH_MMR6 |
4930 | | { 2553, 3, 0, 4, 1132, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2553 = SH_MM |
4931 | | { 2552, 3, 1, 4, 1617, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2552 = SHRL_QB_MM |
4932 | | { 2551, 3, 1, 4, 1451, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2551 = SHRL_QB |
4933 | | { 2550, 3, 1, 4, 1660, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2550 = SHRL_PH_MMR2 |
4934 | | { 2549, 3, 1, 4, 1496, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2549 = SHRL_PH |
4935 | | { 2548, 3, 1, 4, 1616, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2548 = SHRLV_QB_MM |
4936 | | { 2547, 3, 1, 4, 1450, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2547 = SHRLV_QB |
4937 | | { 2546, 3, 1, 4, 1661, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2546 = SHRLV_PH_MMR2 |
4938 | | { 2545, 3, 1, 4, 1497, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2545 = SHRLV_PH |
4939 | | { 2544, 3, 1, 4, 1615, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2544 = SHRA_R_W_MM |
4940 | | { 2543, 3, 1, 4, 1449, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2543 = SHRA_R_W |
4941 | | { 2542, 3, 1, 4, 1657, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2542 = SHRA_R_QB_MMR2 |
4942 | | { 2541, 3, 1, 4, 1493, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2541 = SHRA_R_QB |
4943 | | { 2540, 3, 1, 4, 1614, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2540 = SHRA_R_PH_MM |
4944 | | { 2539, 3, 1, 4, 1448, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2539 = SHRA_R_PH |
4945 | | { 2538, 3, 1, 4, 1656, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2538 = SHRA_QB_MMR2 |
4946 | | { 2537, 3, 1, 4, 1492, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2537 = SHRA_QB |
4947 | | { 2536, 3, 1, 4, 1613, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2536 = SHRA_PH_MM |
4948 | | { 2535, 3, 1, 4, 1447, 0, 0, MipsImpOpBase + 0, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2535 = SHRA_PH |
4949 | | { 2534, 3, 1, 4, 1612, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2534 = SHRAV_R_W_MM |
4950 | | { 2533, 3, 1, 4, 1446, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2533 = SHRAV_R_W |
4951 | | { 2532, 3, 1, 4, 1659, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2532 = SHRAV_R_QB_MMR2 |
4952 | | { 2531, 3, 1, 4, 1495, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2531 = SHRAV_R_QB |
4953 | | { 2530, 3, 1, 4, 1611, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2530 = SHRAV_R_PH_MM |
4954 | | { 2529, 3, 1, 4, 1445, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2529 = SHRAV_R_PH |
4955 | | { 2528, 3, 1, 4, 1658, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2528 = SHRAV_QB_MMR2 |
4956 | | { 2527, 3, 1, 4, 1494, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2527 = SHRAV_QB |
4957 | | { 2526, 3, 1, 4, 1610, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2526 = SHRAV_PH_MM |
4958 | | { 2525, 3, 1, 4, 1444, 0, 0, MipsImpOpBase + 0, 1086, 0, 0x6ULL }, // Inst #2525 = SHRAV_PH |
4959 | | { 2524, 3, 1, 4, 1609, 0, 1, MipsImpOpBase + 58, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2524 = SHLL_S_W_MM |
4960 | | { 2523, 3, 1, 4, 1443, 0, 1, MipsImpOpBase + 58, 229, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2523 = SHLL_S_W |
4961 | | { 2522, 3, 1, 4, 1608, 0, 1, MipsImpOpBase + 58, 1089, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2522 = SHLL_S_PH_MM |
4962 | | { 2521, 3, 1, 4, 1442, 0, 1, MipsImpOpBase + 58, 1089, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2521 = SHLL_S_PH |
4963 | | { 2520, 3, 1, 4, 1607, 0, 1, MipsImpOpBase + 58, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2520 = SHLL_QB_MM |
4964 | | { 2519, 3, 1, 4, 1441, 0, 1, MipsImpOpBase + 58, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2519 = SHLL_QB |
4965 | | { 2518, 3, 1, 4, 1606, 0, 1, MipsImpOpBase + 58, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2518 = SHLL_PH_MM |
4966 | | { 2517, 3, 1, 4, 1440, 0, 1, MipsImpOpBase + 58, 1089, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2517 = SHLL_PH |
4967 | | { 2516, 3, 1, 4, 1605, 0, 1, MipsImpOpBase + 58, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2516 = SHLLV_S_W_MM |
4968 | | { 2515, 3, 1, 4, 1439, 0, 1, MipsImpOpBase + 58, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2515 = SHLLV_S_W |
4969 | | { 2514, 3, 1, 4, 1604, 0, 1, MipsImpOpBase + 58, 1086, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2514 = SHLLV_S_PH_MM |
4970 | | { 2513, 3, 1, 4, 1438, 0, 1, MipsImpOpBase + 58, 1086, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2513 = SHLLV_S_PH |
4971 | | { 2512, 3, 1, 4, 1603, 0, 1, MipsImpOpBase + 58, 1086, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2512 = SHLLV_QB_MM |
4972 | | { 2511, 3, 1, 4, 1437, 0, 1, MipsImpOpBase + 58, 1086, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2511 = SHLLV_QB |
4973 | | { 2510, 3, 1, 4, 1602, 0, 1, MipsImpOpBase + 58, 1086, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2510 = SHLLV_PH_MM |
4974 | | { 2509, 3, 1, 4, 1436, 0, 1, MipsImpOpBase + 58, 1086, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2509 = SHLLV_PH |
4975 | | { 2508, 3, 1, 4, 1601, 0, 0, MipsImpOpBase + 0, 1083, 0, 0x6ULL }, // Inst #2508 = SHILO_MM |
4976 | | { 2507, 3, 1, 4, 1600, 0, 0, MipsImpOpBase + 0, 1025, 0, 0x6ULL }, // Inst #2507 = SHILOV_MM |
4977 | | { 2506, 3, 1, 4, 1434, 0, 0, MipsImpOpBase + 0, 1025, 0, 0x6ULL }, // Inst #2506 = SHILOV |
4978 | | { 2505, 3, 1, 4, 1435, 0, 0, MipsImpOpBase + 0, 1083, 0, 0x6ULL }, // Inst #2505 = SHILO |
4979 | | { 2504, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2504 = SHF_W |
4980 | | { 2503, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2503 = SHF_H |
4981 | | { 2502, 3, 1, 4, 543, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2502 = SHF_B |
4982 | | { 2501, 3, 0, 4, 1101, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2501 = SHE_MM |
4983 | | { 2500, 3, 0, 4, 461, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2500 = SHE |
4984 | | { 2499, 3, 0, 4, 1178, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2499 = SH64 |
4985 | | { 2498, 3, 0, 2, 1155, 0, 0, MipsImpOpBase + 0, 1060, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2498 = SH16_MMR6 |
4986 | | { 2497, 3, 0, 2, 1132, 0, 0, MipsImpOpBase + 0, 1060, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2497 = SH16_MM |
4987 | | { 2496, 3, 0, 4, 453, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2496 = SH |
4988 | | { 2495, 3, 1, 4, 1207, 0, 0, MipsImpOpBase + 0, 220, 0, 0x2ULL }, // Inst #2495 = SEQi |
4989 | | { 2494, 3, 1, 4, 1206, 0, 0, MipsImpOpBase + 0, 223, 0, 0x1ULL }, // Inst #2494 = SEQ |
4990 | | { 2493, 4, 1, 4, 1327, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2493 = SEL_S_MMR6 |
4991 | | { 2492, 4, 1, 4, 1233, 0, 0, MipsImpOpBase + 0, 1079, 0, 0x6ULL }, // Inst #2492 = SEL_S |
4992 | | { 2491, 4, 1, 4, 1326, 0, 0, MipsImpOpBase + 0, 920, 0, 0x6ULL }, // Inst #2491 = SEL_D_MMR6 |
4993 | | { 2490, 4, 1, 4, 1232, 0, 0, MipsImpOpBase + 0, 920, 0, 0x6ULL }, // Inst #2490 = SEL_D |
4994 | | { 2489, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2489 = SELNEZ_S_MMR6 |
4995 | | { 2488, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2488 = SELNEZ_S |
4996 | | { 2487, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2487 = SELNEZ_MMR6 |
4997 | | { 2486, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2486 = SELNEZ_D_MMR6 |
4998 | | { 2485, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2485 = SELNEZ_D |
4999 | | { 2484, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 223, 0, 0x6ULL }, // Inst #2484 = SELNEZ64 |
5000 | | { 2483, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2483 = SELNEZ |
5001 | | { 2482, 3, 1, 4, 1325, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2482 = SELEQZ_S_MMR6 |
5002 | | { 2481, 3, 1, 4, 1221, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2481 = SELEQZ_S |
5003 | | { 2480, 3, 1, 4, 797, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2480 = SELEQZ_MMR6 |
5004 | | { 2479, 3, 1, 4, 1324, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2479 = SELEQZ_D_MMR6 |
5005 | | { 2478, 3, 1, 4, 1222, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2478 = SELEQZ_D |
5006 | | { 2477, 3, 1, 4, 852, 0, 0, MipsImpOpBase + 0, 223, 0, 0x6ULL }, // Inst #2477 = SELEQZ64 |
5007 | | { 2476, 3, 1, 4, 734, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2476 = SELEQZ |
5008 | | { 2475, 2, 1, 4, 759, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2475 = SEH_MM |
5009 | | { 2474, 2, 1, 4, 811, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #2474 = SEH64 |
5010 | | { 2473, 2, 1, 4, 503, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2473 = SEH |
5011 | | { 2472, 2, 1, 4, 758, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2472 = SEB_MM |
5012 | | { 2471, 2, 1, 4, 810, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #2471 = SEB64 |
5013 | | { 2470, 2, 1, 4, 502, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2470 = SEB |
5014 | | { 2469, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 867, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2469 = SDXC164 |
5015 | | { 2468, 3, 0, 4, 700, 0, 0, MipsImpOpBase + 0, 864, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2468 = SDXC1 |
5016 | | { 2467, 3, 0, 4, 1183, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2467 = SDR |
5017 | | { 2466, 3, 0, 4, 1182, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2466 = SDL |
5018 | | { 2465, 2, 0, 4, 885, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2465 = SDIV_MM |
5019 | | { 2464, 2, 0, 4, 865, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2464 = SDIV |
5020 | | { 2463, 3, 0, 4, 458, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2463 = SDC3 |
5021 | | { 2462, 3, 0, 4, 1085, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2462 = SDC2_R6 |
5022 | | { 2461, 3, 0, 4, 1154, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2461 = SDC2_MMR6 |
5023 | | { 2460, 3, 0, 4, 457, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2460 = SDC2 |
5024 | | { 2459, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2459 = SDC1_MM_D64 |
5025 | | { 2458, 3, 0, 4, 1290, 0, 0, MipsImpOpBase + 0, 492, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2458 = SDC1_MM_D32 |
5026 | | { 2457, 3, 0, 4, 1338, 0, 0, MipsImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x6ULL }, // Inst #2457 = SDC1_D64_MMR6 |
5027 | | { 2456, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 840, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2456 = SDC164 |
5028 | | { 2455, 3, 0, 4, 699, 0, 0, MipsImpOpBase + 0, 492, 0|(1ULL<<MCID::MayStore), 0x5ULL }, // Inst #2455 = SDC1 |
5029 | | { 2454, 1, 0, 4, 938, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2454 = SDBBP_R6 |
5030 | | { 2453, 1, 0, 4, 1008, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2453 = SDBBP_MMR6 |
5031 | | { 2452, 1, 0, 4, 967, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2452 = SDBBP_MM |
5032 | | { 2451, 1, 0, 2, 1008, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2451 = SDBBP16_MMR6 |
5033 | | { 2450, 1, 0, 2, 967, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2450 = SDBBP16_MM |
5034 | | { 2449, 1, 0, 4, 389, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #2449 = SDBBP |
5035 | | { 2448, 3, 0, 4, 1175, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2448 = SD |
5036 | | { 2447, 4, 1, 4, 1086, 0, 0, MipsImpOpBase + 0, 1067, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2447 = SC_R6 |
5037 | | { 2446, 4, 1, 4, 1080, 0, 0, MipsImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2446 = SC_MMR6 |
5038 | | { 2445, 4, 1, 4, 1131, 0, 0, MipsImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2445 = SC_MM |
5039 | | { 2444, 4, 1, 4, 1105, 0, 0, MipsImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2444 = SCE_MM |
5040 | | { 2443, 4, 1, 4, 463, 0, 0, MipsImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2443 = SCE |
5041 | | { 2442, 4, 1, 4, 1189, 0, 0, MipsImpOpBase + 0, 1075, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2442 = SCD_R6 |
5042 | | { 2441, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1071, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2441 = SCD |
5043 | | { 2440, 4, 1, 4, 1188, 0, 0, MipsImpOpBase + 0, 1067, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2440 = SC64_R6 |
5044 | | { 2439, 4, 1, 4, 1176, 0, 0, MipsImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2439 = SC64 |
5045 | | { 2438, 4, 1, 4, 459, 0, 0, MipsImpOpBase + 0, 1063, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2438 = SC |
5046 | | { 2437, 3, 0, 4, 1153, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2437 = SB_MMR6 |
5047 | | { 2436, 3, 0, 4, 1100, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2436 = SB_MM |
5048 | | { 2435, 3, 0, 4, 1099, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #2435 = SBE_MM |
5049 | | { 2434, 3, 0, 4, 460, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2434 = SBE |
5050 | | { 2433, 3, 0, 4, 1177, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2433 = SB64 |
5051 | | { 2432, 3, 0, 2, 1153, 0, 0, MipsImpOpBase + 0, 1060, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2432 = SB16_MMR6 |
5052 | | { 2431, 3, 0, 2, 1130, 0, 0, MipsImpOpBase + 0, 1060, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2431 = SB16_MM |
5053 | | { 2430, 3, 0, 4, 452, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayStore), 0x2ULL }, // Inst #2430 = SB |
5054 | | { 2429, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2429 = SAT_U_W |
5055 | | { 2428, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2428 = SAT_U_H |
5056 | | { 2427, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2427 = SAT_U_D |
5057 | | { 2426, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2426 = SAT_U_B |
5058 | | { 2425, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2425 = SAT_S_W |
5059 | | { 2424, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2424 = SAT_S_H |
5060 | | { 2423, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2423 = SAT_S_D |
5061 | | { 2422, 3, 1, 4, 527, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2422 = SAT_S_B |
5062 | | { 2421, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2421 = SAAD |
5063 | | { 2420, 2, 0, 4, 1210, 0, 0, MipsImpOpBase + 0, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2420 = SAA |
5064 | | { 2419, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2419 = RestoreX16 |
5065 | | { 2418, 0, 0, 2, 1108, 1, 1, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2418 = Restore16 |
5066 | | { 2417, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2417 = RSQRT_S_MM |
5067 | | { 2416, 2, 1, 4, 655, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2416 = RSQRT_S |
5068 | | { 2415, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2415 = RSQRT_D64_MM |
5069 | | { 2414, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2414 = RSQRT_D64 |
5070 | | { 2413, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #2413 = RSQRT_D32_MM |
5071 | | { 2412, 2, 1, 4, 653, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #2412 = RSQRT_D32 |
5072 | | { 2411, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2411 = ROUND_W_S_MMR6 |
5073 | | { 2410, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2410 = ROUND_W_S_MM |
5074 | | { 2409, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2409 = ROUND_W_S |
5075 | | { 2408, 2, 1, 4, 1255, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2408 = ROUND_W_MM |
5076 | | { 2407, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2407 = ROUND_W_D_MMR6 |
5077 | | { 2406, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #2406 = ROUND_W_D64 |
5078 | | { 2405, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #2405 = ROUND_W_D32 |
5079 | | { 2404, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2404 = ROUND_L_S_MMR6 |
5080 | | { 2403, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #2403 = ROUND_L_S |
5081 | | { 2402, 2, 1, 4, 1309, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2402 = ROUND_L_D_MMR6 |
5082 | | { 2401, 2, 1, 4, 719, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2401 = ROUND_L_D64 |
5083 | | { 2400, 3, 1, 4, 757, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2400 = ROTR_MM |
5084 | | { 2399, 3, 1, 4, 756, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2399 = ROTRV_MM |
5085 | | { 2398, 3, 1, 4, 720, 0, 0, MipsImpOpBase + 0, 226, 0, 0x1ULL }, // Inst #2398 = ROTRV |
5086 | | { 2397, 3, 1, 4, 501, 0, 0, MipsImpOpBase + 0, 229, 0, 0x1ULL }, // Inst #2397 = ROTR |
5087 | | { 2396, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 631, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2396 = RINT_S_MMR6 |
5088 | | { 2395, 2, 1, 4, 1229, 0, 0, MipsImpOpBase + 0, 631, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2395 = RINT_S |
5089 | | { 2394, 2, 1, 4, 1328, 0, 0, MipsImpOpBase + 0, 623, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2394 = RINT_D_MMR6 |
5090 | | { 2393, 2, 1, 4, 1230, 0, 0, MipsImpOpBase + 0, 623, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2393 = RINT_D |
5091 | | { 2392, 2, 1, 4, 1599, 0, 0, MipsImpOpBase + 0, 1058, 0, 0x6ULL }, // Inst #2392 = REPL_QB_MM |
5092 | | { 2391, 2, 1, 4, 1433, 0, 0, MipsImpOpBase + 0, 1058, 0, 0x6ULL }, // Inst #2391 = REPL_QB |
5093 | | { 2390, 2, 1, 4, 1598, 0, 0, MipsImpOpBase + 0, 1058, 0, 0x6ULL }, // Inst #2390 = REPL_PH_MM |
5094 | | { 2389, 2, 1, 4, 1432, 0, 0, MipsImpOpBase + 0, 1058, 0, 0x6ULL }, // Inst #2389 = REPL_PH |
5095 | | { 2388, 2, 1, 4, 1597, 0, 0, MipsImpOpBase + 0, 1056, 0, 0x6ULL }, // Inst #2388 = REPLV_QB_MM |
5096 | | { 2387, 2, 1, 4, 1431, 0, 0, MipsImpOpBase + 0, 1056, 0, 0x6ULL }, // Inst #2387 = REPLV_QB |
5097 | | { 2386, 2, 1, 4, 1596, 0, 0, MipsImpOpBase + 0, 1056, 0, 0x6ULL }, // Inst #2386 = REPLV_PH_MM |
5098 | | { 2385, 2, 1, 4, 1430, 0, 0, MipsImpOpBase + 0, 1056, 0, 0x6ULL }, // Inst #2385 = REPLV_PH |
5099 | | { 2384, 2, 1, 4, 1288, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2384 = RECIP_S_MM |
5100 | | { 2383, 2, 1, 4, 654, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #2383 = RECIP_S |
5101 | | { 2382, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2382 = RECIP_D64_MM |
5102 | | { 2381, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #2381 = RECIP_D64 |
5103 | | { 2380, 2, 1, 4, 1289, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #2380 = RECIP_D32_MM |
5104 | | { 2379, 2, 1, 4, 652, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #2379 = RECIP_D32 |
5105 | | { 2378, 2, 1, 4, 1036, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2378 = RDPGPR_MMR6 |
5106 | | { 2377, 3, 1, 4, 900, 0, 0, MipsImpOpBase + 0, 1050, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2377 = RDHWR_MMR6 |
5107 | | { 2376, 3, 1, 4, 891, 0, 0, MipsImpOpBase + 0, 1050, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2376 = RDHWR_MM |
5108 | | { 2375, 3, 1, 4, 909, 0, 0, MipsImpOpBase + 0, 1053, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2375 = RDHWR64 |
5109 | | { 2374, 3, 1, 4, 480, 0, 0, MipsImpOpBase + 0, 1050, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2374 = RDHWR |
5110 | | { 2373, 2, 1, 4, 1595, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2373 = RDDSP_MM |
5111 | | { 2372, 2, 1, 4, 1429, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2372 = RDDSP |
5112 | | { 2371, 2, 1, 4, 1594, 0, 0, MipsImpOpBase + 0, 1038, 0, 0x6ULL }, // Inst #2371 = RADDU_W_QB_MM |
5113 | | { 2370, 2, 1, 4, 1428, 0, 0, MipsImpOpBase + 0, 1038, 0, 0x6ULL }, // Inst #2370 = RADDU_W_QB |
5114 | | { 2369, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2369 = PUU_PS64 |
5115 | | { 2368, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2368 = PUL_PS64 |
5116 | | { 2367, 4, 1, 4, 1655, 0, 0, MipsImpOpBase + 0, 564, 0, 0x6ULL }, // Inst #2367 = PREPEND_MMR2 |
5117 | | { 2366, 4, 1, 4, 1491, 0, 0, MipsImpOpBase + 0, 564, 0, 0x6ULL }, // Inst #2366 = PREPEND |
5118 | | { 2365, 3, 0, 4, 1087, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2365 = PREF_R6 |
5119 | | { 2364, 3, 0, 4, 1161, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2364 = PREF_MMR6 |
5120 | | { 2363, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2363 = PREF_MM |
5121 | | { 2362, 3, 0, 4, 1139, 0, 0, MipsImpOpBase + 0, 1047, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2362 = PREFX_MM |
5122 | | { 2361, 3, 0, 4, 1106, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2361 = PREFE_MM |
5123 | | { 2360, 3, 0, 4, 469, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2360 = PREFE |
5124 | | { 2359, 3, 0, 4, 468, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2359 = PREF |
5125 | | { 2358, 4, 1, 4, 1654, 0, 0, MipsImpOpBase + 0, 1043, 0, 0x6ULL }, // Inst #2358 = PRECR_SRA_R_PH_W_MMR2 |
5126 | | { 2357, 4, 1, 4, 1490, 0, 0, MipsImpOpBase + 0, 1043, 0, 0x6ULL }, // Inst #2357 = PRECR_SRA_R_PH_W |
5127 | | { 2356, 4, 1, 4, 1653, 0, 0, MipsImpOpBase + 0, 1043, 0, 0x6ULL }, // Inst #2356 = PRECR_SRA_PH_W_MMR2 |
5128 | | { 2355, 4, 1, 4, 1489, 0, 0, MipsImpOpBase + 0, 1043, 0, 0x6ULL }, // Inst #2355 = PRECR_SRA_PH_W |
5129 | | { 2354, 3, 1, 4, 1652, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2354 = PRECR_QB_PH_MMR2 |
5130 | | { 2353, 3, 1, 4, 1488, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2353 = PRECR_QB_PH |
5131 | | { 2352, 3, 1, 4, 1593, 0, 1, MipsImpOpBase + 58, 1040, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2352 = PRECRQ_RS_PH_W_MM |
5132 | | { 2351, 3, 1, 4, 1427, 0, 1, MipsImpOpBase + 58, 1040, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2351 = PRECRQ_RS_PH_W |
5133 | | { 2350, 3, 1, 4, 1592, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2350 = PRECRQ_QB_PH_MM |
5134 | | { 2349, 3, 1, 4, 1426, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2349 = PRECRQ_QB_PH |
5135 | | { 2348, 3, 1, 4, 1591, 0, 0, MipsImpOpBase + 0, 1040, 0, 0x6ULL }, // Inst #2348 = PRECRQ_PH_W_MM |
5136 | | { 2347, 3, 1, 4, 1425, 0, 0, MipsImpOpBase + 0, 1040, 0, 0x6ULL }, // Inst #2347 = PRECRQ_PH_W |
5137 | | { 2346, 3, 1, 4, 1590, 0, 1, MipsImpOpBase + 58, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2346 = PRECRQU_S_QB_PH_MM |
5138 | | { 2345, 3, 1, 4, 1424, 0, 1, MipsImpOpBase + 58, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2345 = PRECRQU_S_QB_PH |
5139 | | { 2344, 2, 1, 4, 1589, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2344 = PRECEU_PH_QBR_MM |
5140 | | { 2343, 2, 1, 4, 1588, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2343 = PRECEU_PH_QBRA_MM |
5141 | | { 2342, 2, 1, 4, 1422, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2342 = PRECEU_PH_QBRA |
5142 | | { 2341, 2, 1, 4, 1423, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2341 = PRECEU_PH_QBR |
5143 | | { 2340, 2, 1, 4, 1587, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2340 = PRECEU_PH_QBL_MM |
5144 | | { 2339, 2, 1, 4, 1586, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2339 = PRECEU_PH_QBLA_MM |
5145 | | { 2338, 2, 1, 4, 1420, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2338 = PRECEU_PH_QBLA |
5146 | | { 2337, 2, 1, 4, 1421, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2337 = PRECEU_PH_QBL |
5147 | | { 2336, 2, 1, 4, 1585, 0, 0, MipsImpOpBase + 0, 1038, 0, 0x6ULL }, // Inst #2336 = PRECEQ_W_PHR_MM |
5148 | | { 2335, 2, 1, 4, 1419, 0, 0, MipsImpOpBase + 0, 1038, 0, 0x6ULL }, // Inst #2335 = PRECEQ_W_PHR |
5149 | | { 2334, 2, 1, 4, 1584, 0, 0, MipsImpOpBase + 0, 1038, 0, 0x6ULL }, // Inst #2334 = PRECEQ_W_PHL_MM |
5150 | | { 2333, 2, 1, 4, 1418, 0, 0, MipsImpOpBase + 0, 1038, 0, 0x6ULL }, // Inst #2333 = PRECEQ_W_PHL |
5151 | | { 2332, 2, 1, 4, 1583, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2332 = PRECEQU_PH_QBR_MM |
5152 | | { 2331, 2, 1, 4, 1582, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2331 = PRECEQU_PH_QBRA_MM |
5153 | | { 2330, 2, 1, 4, 1416, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2330 = PRECEQU_PH_QBRA |
5154 | | { 2329, 2, 1, 4, 1417, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2329 = PRECEQU_PH_QBR |
5155 | | { 2328, 2, 1, 4, 1581, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2328 = PRECEQU_PH_QBL_MM |
5156 | | { 2327, 2, 1, 4, 1580, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2327 = PRECEQU_PH_QBLA_MM |
5157 | | { 2326, 2, 1, 4, 1414, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2326 = PRECEQU_PH_QBLA |
5158 | | { 2325, 2, 1, 4, 1415, 0, 0, MipsImpOpBase + 0, 523, 0, 0x6ULL }, // Inst #2325 = PRECEQU_PH_QBL |
5159 | | { 2324, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #2324 = POP |
5160 | | { 2323, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2323 = PLU_PS64 |
5161 | | { 2322, 3, 1, 4, 645, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2322 = PLL_PS64 |
5162 | | { 2321, 3, 1, 4, 1579, 1, 0, MipsImpOpBase + 14, 533, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2321 = PICK_QB_MM |
5163 | | { 2320, 3, 1, 4, 1413, 1, 0, MipsImpOpBase + 14, 533, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2320 = PICK_QB |
5164 | | { 2319, 3, 1, 4, 1578, 1, 0, MipsImpOpBase + 14, 533, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2319 = PICK_PH_MM |
5165 | | { 2318, 3, 1, 4, 1412, 1, 0, MipsImpOpBase + 14, 533, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #2318 = PICK_PH |
5166 | | { 2317, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #2317 = PCNT_W |
5167 | | { 2316, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2316 = PCNT_H |
5168 | | { 2315, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2315 = PCNT_D |
5169 | | { 2314, 2, 1, 4, 526, 0, 0, MipsImpOpBase + 0, 956, 0, 0x6ULL }, // Inst #2314 = PCNT_B |
5170 | | { 2313, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2313 = PCKOD_W |
5171 | | { 2312, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2312 = PCKOD_H |
5172 | | { 2311, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2311 = PCKOD_D |
5173 | | { 2310, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2310 = PCKOD_B |
5174 | | { 2309, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2309 = PCKEV_W |
5175 | | { 2308, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2308 = PCKEV_H |
5176 | | { 2307, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2307 = PCKEV_D |
5177 | | { 2306, 3, 1, 4, 626, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2306 = PCKEV_B |
5178 | | { 2305, 0, 0, 4, 1051, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2305 = PAUSE_MMR6 |
5179 | | { 2304, 0, 0, 4, 1034, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2304 = PAUSE_MM |
5180 | | { 2303, 0, 0, 4, 405, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #2303 = PAUSE |
5181 | | { 2302, 3, 1, 4, 1577, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2302 = PACKRL_PH_MM |
5182 | | { 2301, 3, 1, 4, 1411, 0, 0, MipsImpOpBase + 0, 533, 0, 0x6ULL }, // Inst #2301 = PACKRL_PH |
5183 | | { 2300, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 576, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #2300 = OrRxRxRy16 |
5184 | | { 2299, 3, 1, 4, 755, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2299 = ORi_MM |
5185 | | { 2298, 3, 1, 4, 809, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2298 = ORi64 |
5186 | | { 2297, 3, 1, 4, 500, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2297 = ORi |
5187 | | { 2296, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2296 = OR_V |
5188 | | { 2295, 3, 1, 4, 795, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2295 = OR_MMR6 |
5189 | | { 2294, 3, 1, 4, 754, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2294 = OR_MM |
5190 | | { 2293, 3, 1, 4, 796, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #2293 = ORI_MMR6 |
5191 | | { 2292, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2292 = ORI_B |
5192 | | { 2291, 3, 1, 4, 843, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2291 = OR64 |
5193 | | { 2290, 3, 1, 2, 795, 0, 0, MipsImpOpBase + 0, 561, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2290 = OR16_MMR6 |
5194 | | { 2289, 3, 1, 2, 754, 0, 0, MipsImpOpBase + 0, 561, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #2289 = OR16_MM |
5195 | | { 2288, 3, 1, 4, 367, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2288 = OR |
5196 | | { 2287, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 394, 0, 0x0ULL }, // Inst #2287 = NotRxRy16 |
5197 | | { 2286, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 394, 0, 0x0ULL }, // Inst #2286 = NegRxRy16 |
5198 | | { 2285, 2, 1, 2, 794, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x0ULL }, // Inst #2285 = NOT16_MMR6 |
5199 | | { 2284, 2, 1, 2, 753, 0, 0, MipsImpOpBase + 0, 1036, 0, 0x0ULL }, // Inst #2284 = NOT16_MM |
5200 | | { 2283, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2283 = NOR_V |
5201 | | { 2282, 3, 1, 4, 793, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2282 = NOR_MMR6 |
5202 | | { 2281, 3, 1, 4, 752, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2281 = NOR_MM |
5203 | | { 2280, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2280 = NORI_B |
5204 | | { 2279, 3, 1, 4, 842, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2279 = NOR64 |
5205 | | { 2278, 3, 1, 4, 366, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2278 = NOR |
5206 | | { 2277, 4, 1, 4, 1251, 0, 0, MipsImpOpBase + 0, 936, 0, 0x4ULL }, // Inst #2277 = NMSUB_S_MM |
5207 | | { 2276, 4, 1, 4, 684, 0, 0, MipsImpOpBase + 0, 936, 0, 0x4ULL }, // Inst #2276 = NMSUB_S |
5208 | | { 2275, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2275 = NMSUB_D64 |
5209 | | { 2274, 4, 1, 4, 1252, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2274 = NMSUB_D32_MM |
5210 | | { 2273, 4, 1, 4, 683, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2273 = NMSUB_D32 |
5211 | | { 2272, 4, 1, 4, 1249, 0, 0, MipsImpOpBase + 0, 936, 0, 0x4ULL }, // Inst #2272 = NMADD_S_MM |
5212 | | { 2271, 4, 1, 4, 682, 0, 0, MipsImpOpBase + 0, 936, 0, 0x4ULL }, // Inst #2271 = NMADD_S |
5213 | | { 2270, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2270 = NMADD_D64 |
5214 | | { 2269, 4, 1, 4, 1250, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2269 = NMADD_D32_MM |
5215 | | { 2268, 4, 1, 4, 681, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2268 = NMADD_D32 |
5216 | | { 2267, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #2267 = NLZC_W |
5217 | | { 2266, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2266 = NLZC_H |
5218 | | { 2265, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2265 = NLZC_D |
5219 | | { 2264, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 956, 0, 0x6ULL }, // Inst #2264 = NLZC_B |
5220 | | { 2263, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #2263 = NLOC_W |
5221 | | { 2262, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 1034, 0, 0x6ULL }, // Inst #2262 = NLOC_H |
5222 | | { 2261, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #2261 = NLOC_D |
5223 | | { 2260, 2, 1, 4, 627, 0, 0, MipsImpOpBase + 0, 956, 0, 0x6ULL }, // Inst #2260 = NLOC_B |
5224 | | { 2259, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1032, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2259 = MoveR3216 |
5225 | | { 2258, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 1030, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2258 = Move32R16 |
5226 | | { 2257, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 40, 833, 0, 0x0ULL }, // Inst #2257 = Mflo16 |
5227 | | { 2256, 1, 1, 2, 735, 1, 0, MipsImpOpBase + 38, 833, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2256 = Mfhi16 |
5228 | | { 2255, 3, 1, 4, 1647, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2255 = MUL_S_PH_MMR2 |
5229 | | { 2254, 3, 1, 4, 1483, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2254 = MUL_S_PH |
5230 | | { 2253, 3, 1, 4, 872, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2253 = MUL_R6 |
5231 | | { 2252, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2252 = MUL_Q_W |
5232 | | { 2251, 3, 1, 4, 676, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2251 = MUL_Q_H |
5233 | | { 2250, 3, 1, 4, 1646, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2250 = MUL_PH_MMR2 |
5234 | | { 2249, 3, 1, 4, 1482, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2249 = MUL_PH |
5235 | | { 2248, 3, 1, 4, 895, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2248 = MUL_MMR6 |
5236 | | { 2247, 3, 1, 4, 884, 0, 2, MipsImpOpBase + 7, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2247 = MUL_MM |
5237 | | { 2246, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2246 = MULV_W |
5238 | | { 2245, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2245 = MULV_H |
5239 | | { 2244, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2244 = MULV_D |
5240 | | { 2243, 3, 1, 4, 670, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2243 = MULV_B |
5241 | | { 2242, 3, 1, 4, 894, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2242 = MULU_MMR6 |
5242 | | { 2241, 3, 1, 4, 871, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2241 = MULU |
5243 | | { 2240, 2, 0, 4, 879, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2240 = MULTu_MM |
5244 | | { 2239, 2, 0, 4, 488, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2239 = MULTu |
5245 | | { 2238, 2, 0, 4, 878, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2238 = MULT_MM |
5246 | | { 2237, 3, 1, 4, 1576, 0, 0, MipsImpOpBase + 0, 436, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2237 = MULT_DSP_MM |
5247 | | { 2236, 3, 1, 4, 1410, 0, 0, MipsImpOpBase + 0, 436, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2236 = MULT_DSP |
5248 | | { 2235, 3, 1, 4, 1575, 0, 0, MipsImpOpBase + 0, 436, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2235 = MULTU_DSP_MM |
5249 | | { 2234, 3, 1, 4, 1409, 0, 0, MipsImpOpBase + 0, 436, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #2234 = MULTU_DSP |
5250 | | { 2233, 2, 0, 4, 487, 0, 2, MipsImpOpBase + 7, 140, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #2233 = MULT |
5251 | | { 2232, 4, 1, 4, 1651, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #2232 = MULSA_W_PH_MMR2 |
5252 | | { 2231, 4, 1, 4, 1487, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #2231 = MULSA_W_PH |
5253 | | { 2230, 4, 1, 4, 1574, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2230 = MULSAQ_S_W_PH_MM |
5254 | | { 2229, 4, 1, 4, 1408, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2229 = MULSAQ_S_W_PH |
5255 | | { 2228, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2228 = MULR_Q_W |
5256 | | { 2227, 3, 1, 4, 675, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2227 = MULR_Q_H |
5257 | | { 2226, 3, 1, 4, 1213, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2226 = MULR_PS64 |
5258 | | { 2225, 3, 1, 4, 1650, 0, 1, MipsImpOpBase + 57, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2225 = MULQ_S_W_MMR2 |
5259 | | { 2224, 3, 1, 4, 1486, 0, 1, MipsImpOpBase + 57, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2224 = MULQ_S_W |
5260 | | { 2223, 3, 1, 4, 1649, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2223 = MULQ_S_PH_MMR2 |
5261 | | { 2222, 3, 1, 4, 1485, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2222 = MULQ_S_PH |
5262 | | { 2221, 3, 1, 4, 1648, 0, 1, MipsImpOpBase + 57, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2221 = MULQ_RS_W_MMR2 |
5263 | | { 2220, 3, 1, 4, 1484, 0, 1, MipsImpOpBase + 57, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2220 = MULQ_RS_W |
5264 | | { 2219, 3, 1, 4, 1573, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2219 = MULQ_RS_PH_MM |
5265 | | { 2218, 3, 1, 4, 1407, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2218 = MULQ_RS_PH |
5266 | | { 2217, 3, 1, 4, 1572, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2217 = MULEU_S_PH_QBR_MM |
5267 | | { 2216, 3, 1, 4, 1406, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2216 = MULEU_S_PH_QBR |
5268 | | { 2215, 3, 1, 4, 1571, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2215 = MULEU_S_PH_QBL_MM |
5269 | | { 2214, 3, 1, 4, 1405, 0, 1, MipsImpOpBase + 57, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2214 = MULEU_S_PH_QBL |
5270 | | { 2213, 3, 1, 4, 1570, 0, 1, MipsImpOpBase + 57, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2213 = MULEQ_S_W_PHR_MM |
5271 | | { 2212, 3, 1, 4, 1404, 0, 1, MipsImpOpBase + 57, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2212 = MULEQ_S_W_PHR |
5272 | | { 2211, 3, 1, 4, 1569, 0, 1, MipsImpOpBase + 57, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2211 = MULEQ_S_W_PHL_MM |
5273 | | { 2210, 3, 1, 4, 1403, 0, 1, MipsImpOpBase + 57, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2210 = MULEQ_S_W_PHL |
5274 | | { 2209, 3, 1, 4, 486, 0, 2, MipsImpOpBase + 7, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2209 = MUL |
5275 | | { 2208, 3, 1, 4, 893, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2208 = MUH_MMR6 |
5276 | | { 2207, 3, 1, 4, 892, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #2207 = MUHU_MMR6 |
5277 | | { 2206, 3, 1, 4, 870, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2206 = MUHU |
5278 | | { 2205, 3, 1, 4, 869, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2205 = MUH |
5279 | | { 2204, 5, 1, 4, 1064, 0, 0, MipsImpOpBase + 0, 947, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2204 = MTTR |
5280 | | { 2203, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 56, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2203 = MTP2 |
5281 | | { 2202, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 55, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2202 = MTP1 |
5282 | | { 2201, 1, 0, 4, 1205, 0, 1, MipsImpOpBase + 54, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2201 = MTP0 |
5283 | | { 2200, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 50, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2200 = MTM2 |
5284 | | { 2199, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 46, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2199 = MTM1 |
5285 | | { 2198, 1, 0, 4, 1205, 0, 4, MipsImpOpBase + 42, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2198 = MTM0 |
5286 | | { 2197, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 40, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2197 = MTLO_MM |
5287 | | { 2196, 2, 1, 4, 1568, 0, 0, MipsImpOpBase + 0, 1028, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2196 = MTLO_DSP_MM |
5288 | | { 2195, 2, 1, 4, 1356, 0, 0, MipsImpOpBase + 0, 1028, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2195 = MTLO_DSP |
5289 | | { 2194, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 41, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2194 = MTLO64 |
5290 | | { 2193, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 40, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2193 = MTLO |
5291 | | { 2192, 3, 1, 4, 1567, 0, 1, MipsImpOpBase + 4, 1025, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2192 = MTHLIP_MM |
5292 | | { 2191, 3, 1, 4, 1354, 0, 1, MipsImpOpBase + 4, 1025, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2191 = MTHLIP |
5293 | | { 2190, 1, 0, 4, 890, 0, 1, MipsImpOpBase + 38, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2190 = MTHI_MM |
5294 | | { 2189, 2, 1, 4, 1566, 0, 0, MipsImpOpBase + 0, 1023, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2189 = MTHI_DSP_MM |
5295 | | { 2188, 2, 1, 4, 1355, 0, 0, MipsImpOpBase + 0, 1023, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2188 = MTHI_DSP |
5296 | | { 2187, 1, 0, 4, 908, 0, 1, MipsImpOpBase + 39, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2187 = MTHI64 |
5297 | | { 2186, 1, 0, 4, 493, 0, 1, MipsImpOpBase + 38, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2186 = MTHI |
5298 | | { 2185, 3, 1, 4, 1079, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2185 = MTHGC0_MM |
5299 | | { 2184, 3, 1, 4, 424, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2184 = MTHGC0 |
5300 | | { 2183, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 674, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2183 = MTHC2_MMR6 |
5301 | | { 2182, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1020, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2182 = MTHC1_D64_MM |
5302 | | { 2181, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1020, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2181 = MTHC1_D64 |
5303 | | { 2180, 3, 1, 4, 1270, 0, 0, MipsImpOpBase + 0, 1017, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2180 = MTHC1_D32_MM |
5304 | | { 2179, 3, 1, 4, 687, 0, 0, MipsImpOpBase + 0, 1017, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2179 = MTHC1_D32 |
5305 | | { 2178, 3, 1, 4, 1043, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2178 = MTHC0_MMR6 |
5306 | | { 2177, 3, 1, 4, 1078, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2177 = MTGC0_MM |
5307 | | { 2176, 3, 1, 4, 423, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2176 = MTGC0 |
5308 | | { 2175, 2, 1, 4, 1045, 0, 0, MipsImpOpBase + 0, 674, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2175 = MTC2_MMR6 |
5309 | | { 2174, 3, 1, 4, 419, 0, 0, MipsImpOpBase + 0, 1014, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2174 = MTC2 |
5310 | | { 2173, 2, 1, 4, 1313, 0, 0, MipsImpOpBase + 0, 392, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2173 = MTC1_MMR6 |
5311 | | { 2172, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 392, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2172 = MTC1_MM |
5312 | | { 2171, 2, 1, 4, 1269, 0, 0, MipsImpOpBase + 0, 406, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2171 = MTC1_D64_MM |
5313 | | { 2170, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 406, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #2170 = MTC1_D64 |
5314 | | { 2169, 2, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 392, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2169 = MTC1 |
5315 | | { 2168, 3, 1, 4, 1044, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2168 = MTC0_MMR6 |
5316 | | { 2167, 3, 1, 4, 417, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2167 = MTC0 |
5317 | | { 2166, 4, 1, 4, 1282, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2166 = MSUB_S_MM |
5318 | | { 2165, 4, 1, 4, 680, 0, 0, MipsImpOpBase + 0, 936, 0, 0x4ULL }, // Inst #2165 = MSUB_S |
5319 | | { 2164, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2164 = MSUB_Q_W |
5320 | | { 2163, 4, 1, 4, 674, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #2163 = MSUB_Q_H |
5321 | | { 2162, 2, 0, 4, 882, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2162 = MSUB_MM |
5322 | | { 2161, 4, 1, 4, 1565, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #2161 = MSUB_DSP_MM |
5323 | | { 2160, 4, 1, 4, 1402, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #2160 = MSUB_DSP |
5324 | | { 2159, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #2159 = MSUB_D64 |
5325 | | { 2158, 4, 1, 4, 1283, 0, 0, MipsImpOpBase + 0, 928, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2158 = MSUB_D32_MM |
5326 | | { 2157, 4, 1, 4, 679, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #2157 = MSUB_D32 |
5327 | | { 2156, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2156 = MSUBV_W |
5328 | | { 2155, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #2155 = MSUBV_H |
5329 | | { 2154, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #2154 = MSUBV_D |
5330 | | { 2153, 4, 1, 4, 668, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #2153 = MSUBV_B |
5331 | | { 2152, 2, 0, 4, 883, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2152 = MSUBU_MM |
5332 | | { 2151, 4, 1, 4, 1564, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #2151 = MSUBU_DSP_MM |
5333 | | { 2150, 4, 1, 4, 1401, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #2150 = MSUBU_DSP |
5334 | | { 2149, 2, 0, 4, 856, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2149 = MSUBU |
5335 | | { 2148, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #2148 = MSUBR_Q_W |
5336 | | { 2147, 4, 1, 4, 673, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #2147 = MSUBR_Q_H |
5337 | | { 2146, 4, 1, 4, 1332, 0, 0, MipsImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2146 = MSUBF_S_MMR6 |
5338 | | { 2145, 4, 1, 4, 1235, 0, 0, MipsImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2145 = MSUBF_S |
5339 | | { 2144, 4, 1, 4, 1331, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2144 = MSUBF_D_MMR6 |
5340 | | { 2143, 4, 1, 4, 1237, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2143 = MSUBF_D |
5341 | | { 2142, 2, 0, 4, 855, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2142 = MSUB |
5342 | | { 2141, 4, 1, 4, 1245, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2141 = MOVZ_I_S_MM |
5343 | | { 2140, 4, 1, 4, 709, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2140 = MOVZ_I_S |
5344 | | { 2139, 4, 1, 4, 1563, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2139 = MOVZ_I_MM |
5345 | | { 2138, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2138 = MOVZ_I_I64 |
5346 | | { 2137, 4, 1, 4, 483, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2137 = MOVZ_I_I |
5347 | | { 2136, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2136 = MOVZ_I_D64 |
5348 | | { 2135, 4, 1, 4, 1244, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2135 = MOVZ_I_D32_MM |
5349 | | { 2134, 4, 1, 4, 708, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2134 = MOVZ_I_D32 |
5350 | | { 2133, 4, 1, 4, 1217, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2133 = MOVZ_I64_S |
5351 | | { 2132, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2132 = MOVZ_I64_I64 |
5352 | | { 2131, 4, 1, 4, 911, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2131 = MOVZ_I64_I |
5353 | | { 2130, 4, 1, 4, 1220, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2130 = MOVZ_I64_D64 |
5354 | | { 2129, 4, 1, 4, 1243, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2129 = MOVT_S_MM |
5355 | | { 2128, 4, 1, 4, 534, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2128 = MOVT_S |
5356 | | { 2127, 4, 1, 4, 889, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2127 = MOVT_I_MM |
5357 | | { 2126, 4, 1, 4, 1215, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2126 = MOVT_I64 |
5358 | | { 2125, 4, 1, 4, 698, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2125 = MOVT_I |
5359 | | { 2124, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2124 = MOVT_D64 |
5360 | | { 2123, 4, 1, 4, 1242, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2123 = MOVT_D32_MM |
5361 | | { 2122, 4, 1, 4, 533, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2122 = MOVT_D32 |
5362 | | { 2121, 4, 1, 4, 1241, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2121 = MOVN_I_S_MM |
5363 | | { 2120, 4, 1, 4, 707, 0, 0, MipsImpOpBase + 0, 1010, 0, 0x4ULL }, // Inst #2120 = MOVN_I_S |
5364 | | { 2119, 4, 1, 4, 1562, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2119 = MOVN_I_MM |
5365 | | { 2118, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 1006, 0, 0x4ULL }, // Inst #2118 = MOVN_I_I64 |
5366 | | { 2117, 4, 1, 4, 482, 0, 0, MipsImpOpBase + 0, 1002, 0, 0x4ULL }, // Inst #2117 = MOVN_I_I |
5367 | | { 2116, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 998, 0, 0x4ULL }, // Inst #2116 = MOVN_I_D64 |
5368 | | { 2115, 4, 1, 4, 1240, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2115 = MOVN_I_D32_MM |
5369 | | { 2114, 4, 1, 4, 706, 0, 0, MipsImpOpBase + 0, 994, 0, 0x4ULL }, // Inst #2114 = MOVN_I_D32 |
5370 | | { 2113, 4, 1, 4, 1219, 0, 0, MipsImpOpBase + 0, 990, 0, 0x4ULL }, // Inst #2113 = MOVN_I64_S |
5371 | | { 2112, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 986, 0, 0x4ULL }, // Inst #2112 = MOVN_I64_I64 |
5372 | | { 2111, 4, 1, 4, 910, 0, 0, MipsImpOpBase + 0, 982, 0, 0x4ULL }, // Inst #2111 = MOVN_I64_I |
5373 | | { 2110, 4, 1, 4, 1218, 0, 0, MipsImpOpBase + 0, 978, 0, 0x4ULL }, // Inst #2110 = MOVN_I64_D64 |
5374 | | { 2109, 4, 1, 4, 1239, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2109 = MOVF_S_MM |
5375 | | { 2108, 4, 1, 4, 532, 0, 0, MipsImpOpBase + 0, 974, 0, 0x4ULL }, // Inst #2108 = MOVF_S |
5376 | | { 2107, 4, 1, 4, 888, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2107 = MOVF_I_MM |
5377 | | { 2106, 4, 1, 4, 1216, 0, 0, MipsImpOpBase + 0, 970, 0, 0x4ULL }, // Inst #2106 = MOVF_I64 |
5378 | | { 2105, 4, 1, 4, 697, 0, 0, MipsImpOpBase + 0, 966, 0, 0x4ULL }, // Inst #2105 = MOVF_I |
5379 | | { 2104, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 962, 0, 0x4ULL }, // Inst #2104 = MOVF_D64 |
5380 | | { 2103, 4, 1, 4, 1238, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2103 = MOVF_D32_MM |
5381 | | { 2102, 4, 1, 4, 531, 0, 0, MipsImpOpBase + 0, 958, 0, 0x4ULL }, // Inst #2102 = MOVF_D32 |
5382 | | { 2101, 2, 1, 4, 546, 0, 0, MipsImpOpBase + 0, 956, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2101 = MOVE_V |
5383 | | { 2100, 4, 2, 2, 1561, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2100 = MOVEP_MMR6 |
5384 | | { 2099, 4, 2, 2, 751, 0, 0, MipsImpOpBase + 0, 952, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2099 = MOVEP_MM |
5385 | | { 2098, 2, 1, 2, 792, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2098 = MOVE16_MMR6 |
5386 | | { 2097, 2, 1, 2, 750, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2097 = MOVE16_MM |
5387 | | { 2096, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2096 = MOD_U_W |
5388 | | { 2095, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2095 = MOD_U_H |
5389 | | { 2094, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2094 = MOD_U_D |
5390 | | { 2093, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2093 = MOD_U_B |
5391 | | { 2092, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2092 = MOD_S_W |
5392 | | { 2091, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2091 = MOD_S_H |
5393 | | { 2090, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2090 = MOD_S_D |
5394 | | { 2089, 3, 1, 4, 613, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2089 = MOD_S_B |
5395 | | { 2088, 3, 1, 4, 897, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2088 = MOD_MMR6 |
5396 | | { 2087, 3, 1, 4, 896, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2087 = MODU_MMR6 |
5397 | | { 2086, 3, 1, 4, 874, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2086 = MODU |
5398 | | { 2085, 3, 1, 4, 1560, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2085 = MODSUB_MM |
5399 | | { 2084, 3, 1, 4, 1400, 0, 0, MipsImpOpBase + 0, 226, 0, 0x6ULL }, // Inst #2084 = MODSUB |
5400 | | { 2083, 3, 1, 4, 873, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #2083 = MOD |
5401 | | { 2082, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2082 = MIN_U_W |
5402 | | { 2081, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2081 = MIN_U_H |
5403 | | { 2080, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2080 = MIN_U_D |
5404 | | { 2079, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2079 = MIN_U_B |
5405 | | { 2078, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2078 = MIN_S_W |
5406 | | { 2077, 3, 1, 4, 1319, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2077 = MIN_S_MMR6 |
5407 | | { 2076, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2076 = MIN_S_H |
5408 | | { 2075, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2075 = MIN_S_D |
5409 | | { 2074, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2074 = MIN_S_B |
5410 | | { 2073, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2073 = MIN_S |
5411 | | { 2072, 3, 1, 4, 1318, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2072 = MIN_D_MMR6 |
5412 | | { 2071, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2071 = MIN_D |
5413 | | { 2070, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2070 = MIN_A_W |
5414 | | { 2069, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2069 = MIN_A_H |
5415 | | { 2068, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2068 = MIN_A_D |
5416 | | { 2067, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2067 = MIN_A_B |
5417 | | { 2066, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2066 = MINI_U_W |
5418 | | { 2065, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2065 = MINI_U_H |
5419 | | { 2064, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2064 = MINI_U_D |
5420 | | { 2063, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2063 = MINI_U_B |
5421 | | { 2062, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2062 = MINI_S_W |
5422 | | { 2061, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2061 = MINI_S_H |
5423 | | { 2060, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2060 = MINI_S_D |
5424 | | { 2059, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2059 = MINI_S_B |
5425 | | { 2058, 3, 1, 4, 1323, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2058 = MINA_S_MMR6 |
5426 | | { 2057, 3, 1, 4, 1226, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2057 = MINA_S |
5427 | | { 2056, 3, 1, 4, 1322, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2056 = MINA_D_MMR6 |
5428 | | { 2055, 3, 1, 4, 1225, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2055 = MINA_D |
5429 | | { 2054, 5, 1, 4, 1063, 0, 0, MipsImpOpBase + 0, 947, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2054 = MFTR |
5430 | | { 2053, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2053 = MFLO_MM |
5431 | | { 2052, 2, 1, 4, 1559, 0, 0, MipsImpOpBase + 0, 370, 0, 0x6ULL }, // Inst #2052 = MFLO_DSP_MM |
5432 | | { 2051, 2, 1, 4, 1399, 0, 0, MipsImpOpBase + 0, 370, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2051 = MFLO_DSP |
5433 | | { 2050, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2050 = MFLO64 |
5434 | | { 2049, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 185, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2049 = MFLO16_MM |
5435 | | { 2048, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2048 = MFLO |
5436 | | { 2047, 1, 1, 4, 887, 1, 0, MipsImpOpBase + 36, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2047 = MFHI_MM |
5437 | | { 2046, 2, 1, 4, 1558, 0, 0, MipsImpOpBase + 0, 370, 0, 0x6ULL }, // Inst #2046 = MFHI_DSP_MM |
5438 | | { 2045, 2, 1, 4, 1398, 0, 0, MipsImpOpBase + 0, 370, 0|(1ULL<<MCID::MoveReg), 0x6ULL }, // Inst #2045 = MFHI_DSP |
5439 | | { 2044, 1, 1, 4, 906, 1, 0, MipsImpOpBase + 37, 306, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2044 = MFHI64 |
5440 | | { 2043, 1, 1, 2, 887, 1, 0, MipsImpOpBase + 36, 185, 0|(1ULL<<MCID::MoveReg), 0x0ULL }, // Inst #2043 = MFHI16_MM |
5441 | | { 2042, 1, 1, 4, 478, 1, 0, MipsImpOpBase + 36, 185, 0|(1ULL<<MCID::MoveReg), 0x1ULL }, // Inst #2042 = MFHI |
5442 | | { 2041, 3, 1, 4, 1077, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2041 = MFHGC0_MM |
5443 | | { 2040, 3, 1, 4, 422, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2040 = MFHGC0 |
5444 | | { 2039, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2039 = MFHC2_MMR6 |
5445 | | { 2038, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2038 = MFHC1_D64_MM |
5446 | | { 2037, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2037 = MFHC1_D64 |
5447 | | { 2036, 2, 1, 4, 1268, 0, 0, MipsImpOpBase + 0, 945, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2036 = MFHC1_D32_MM |
5448 | | { 2035, 2, 1, 4, 696, 0, 0, MipsImpOpBase + 0, 945, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2035 = MFHC1_D32 |
5449 | | { 2034, 3, 1, 4, 1040, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2034 = MFHC0_MMR6 |
5450 | | { 2033, 3, 1, 4, 1076, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #2033 = MFGC0_MM |
5451 | | { 2032, 3, 1, 4, 421, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2032 = MFGC0 |
5452 | | { 2031, 2, 1, 4, 1042, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2031 = MFC2_MMR6 |
5453 | | { 2030, 3, 1, 4, 418, 0, 0, MipsImpOpBase + 0, 942, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2030 = MFC2 |
5454 | | { 2029, 2, 1, 4, 1312, 0, 0, MipsImpOpBase + 0, 375, 0|(1ULL<<MCID::Bitcast), 0x6ULL }, // Inst #2029 = MFC1_MMR6 |
5455 | | { 2028, 2, 1, 4, 1267, 0, 0, MipsImpOpBase + 0, 375, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2028 = MFC1_MM |
5456 | | { 2027, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 940, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2027 = MFC1_D64 |
5457 | | { 2026, 2, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 375, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #2026 = MFC1 |
5458 | | { 2025, 3, 1, 4, 1041, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2025 = MFC0_MMR6 |
5459 | | { 2024, 3, 1, 4, 416, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #2024 = MFC0 |
5460 | | { 2023, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2023 = MAX_U_W |
5461 | | { 2022, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2022 = MAX_U_H |
5462 | | { 2021, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2021 = MAX_U_D |
5463 | | { 2020, 3, 1, 4, 618, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2020 = MAX_U_B |
5464 | | { 2019, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2019 = MAX_S_W |
5465 | | { 2018, 3, 1, 4, 1317, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2018 = MAX_S_MMR6 |
5466 | | { 2017, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2017 = MAX_S_H |
5467 | | { 2016, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2016 = MAX_S_D |
5468 | | { 2015, 3, 1, 4, 617, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2015 = MAX_S_B |
5469 | | { 2014, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2014 = MAX_S |
5470 | | { 2013, 3, 1, 4, 1316, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2013 = MAX_D_MMR6 |
5471 | | { 2012, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #2012 = MAX_D |
5472 | | { 2011, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #2011 = MAX_A_W |
5473 | | { 2010, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #2010 = MAX_A_H |
5474 | | { 2009, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #2009 = MAX_A_D |
5475 | | { 2008, 3, 1, 4, 619, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #2008 = MAX_A_B |
5476 | | { 2007, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2007 = MAXI_U_W |
5477 | | { 2006, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2006 = MAXI_U_H |
5478 | | { 2005, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2005 = MAXI_U_D |
5479 | | { 2004, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2004 = MAXI_U_B |
5480 | | { 2003, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #2003 = MAXI_S_W |
5481 | | { 2002, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #2002 = MAXI_S_H |
5482 | | { 2001, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #2001 = MAXI_S_D |
5483 | | { 2000, 3, 1, 4, 620, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #2000 = MAXI_S_B |
5484 | | { 1999, 3, 1, 4, 1321, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1999 = MAXA_S_MMR6 |
5485 | | { 1998, 3, 1, 4, 1223, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1998 = MAXA_S |
5486 | | { 1997, 3, 1, 4, 1320, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1997 = MAXA_D_MMR6 |
5487 | | { 1996, 3, 1, 4, 1224, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1996 = MAXA_D |
5488 | | { 1995, 4, 1, 4, 1557, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1995 = MAQ_S_W_PHR_MM |
5489 | | { 1994, 4, 1, 4, 1397, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1994 = MAQ_S_W_PHR |
5490 | | { 1993, 4, 1, 4, 1556, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1993 = MAQ_S_W_PHL_MM |
5491 | | { 1992, 4, 1, 4, 1396, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1992 = MAQ_S_W_PHL |
5492 | | { 1991, 4, 1, 4, 1555, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1991 = MAQ_SA_W_PHR_MM |
5493 | | { 1990, 4, 1, 4, 1395, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1990 = MAQ_SA_W_PHR |
5494 | | { 1989, 4, 1, 4, 1554, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1989 = MAQ_SA_W_PHL_MM |
5495 | | { 1988, 4, 1, 4, 1394, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1988 = MAQ_SA_W_PHL |
5496 | | { 1987, 4, 1, 4, 1253, 0, 0, MipsImpOpBase + 0, 936, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1987 = MADD_S_MM |
5497 | | { 1986, 4, 1, 4, 678, 0, 0, MipsImpOpBase + 0, 936, 0, 0x4ULL }, // Inst #1986 = MADD_S |
5498 | | { 1985, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1985 = MADD_Q_W |
5499 | | { 1984, 4, 1, 4, 672, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #1984 = MADD_Q_H |
5500 | | { 1983, 2, 0, 4, 880, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1983 = MADD_MM |
5501 | | { 1982, 4, 1, 4, 1553, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1982 = MADD_DSP_MM |
5502 | | { 1981, 4, 1, 4, 1393, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1981 = MADD_DSP |
5503 | | { 1980, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 932, 0, 0x4ULL }, // Inst #1980 = MADD_D64 |
5504 | | { 1979, 4, 1, 4, 1254, 0, 0, MipsImpOpBase + 0, 928, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1979 = MADD_D32_MM |
5505 | | { 1978, 4, 1, 4, 677, 0, 0, MipsImpOpBase + 0, 928, 0, 0x4ULL }, // Inst #1978 = MADD_D32 |
5506 | | { 1977, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1977 = MADDV_W |
5507 | | { 1976, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #1976 = MADDV_H |
5508 | | { 1975, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1975 = MADDV_D |
5509 | | { 1974, 4, 1, 4, 669, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #1974 = MADDV_B |
5510 | | { 1973, 2, 0, 4, 881, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1973 = MADDU_MM |
5511 | | { 1972, 4, 1, 4, 1552, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1972 = MADDU_DSP_MM |
5512 | | { 1971, 4, 1, 4, 1392, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1971 = MADDU_DSP |
5513 | | { 1970, 2, 0, 4, 854, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1970 = MADDU |
5514 | | { 1969, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1969 = MADDR_Q_W |
5515 | | { 1968, 4, 1, 4, 671, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #1968 = MADDR_Q_H |
5516 | | { 1967, 4, 1, 4, 1330, 0, 0, MipsImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1967 = MADDF_S_MMR6 |
5517 | | { 1966, 4, 1, 4, 1234, 0, 0, MipsImpOpBase + 0, 924, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1966 = MADDF_S |
5518 | | { 1965, 4, 1, 4, 1329, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1965 = MADDF_D_MMR6 |
5519 | | { 1964, 4, 1, 4, 1236, 0, 0, MipsImpOpBase + 0, 920, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1964 = MADDF_D |
5520 | | { 1963, 2, 0, 4, 853, 2, 2, MipsImpOpBase + 32, 140, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1963 = MADD |
5521 | | { 1962, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 573, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1962 = LwRxSpImmX16 |
5522 | | { 1961, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1961 = LwRxRyOffMemX16 |
5523 | | { 1960, 3, 1, 4, 1113, 0, 0, MipsImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1960 = LwRxPcTcpX16 |
5524 | | { 1959, 3, 1, 2, 1113, 0, 0, MipsImpOpBase + 0, 917, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1959 = LwRxPcTcp16 |
5525 | | { 1958, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 568, 0, 0x0ULL }, // Inst #1958 = LiRxImmX16 |
5526 | | { 1957, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1957 = LiRxImmAlignX16 |
5527 | | { 1956, 2, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1956 = LiRxImm16 |
5528 | | { 1955, 3, 1, 4, 1112, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1955 = LhuRxRyOffMemX16 |
5529 | | { 1954, 3, 1, 4, 1111, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1954 = LhRxRyOffMemX16 |
5530 | | { 1953, 3, 1, 4, 1110, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1953 = LbuRxRyOffMemX16 |
5531 | | { 1952, 3, 1, 4, 1109, 0, 0, MipsImpOpBase + 0, 914, 0|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1952 = LbRxRyOffMemX16 |
5532 | | { 1951, 3, 1, 4, 1165, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1951 = LWu |
5533 | | { 1950, 3, 1, 4, 1152, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1950 = LW_MMR6 |
5534 | | { 1949, 3, 1, 4, 1123, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1949 = LW_MM |
5535 | | { 1948, 3, 1, 4, 1551, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1948 = LWX_MM |
5536 | | { 1947, 3, 1, 4, 1129, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1947 = LWXS_MM |
5537 | | { 1946, 3, 1, 4, 1299, 0, 0, MipsImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1946 = LWXC1_MM |
5538 | | { 1945, 3, 1, 4, 713, 0, 0, MipsImpOpBase + 0, 911, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1945 = LWXC1 |
5539 | | { 1944, 3, 1, 4, 1391, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1944 = LWX |
5540 | | { 1943, 3, 1, 4, 1128, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1943 = LWU_MM |
5541 | | { 1942, 2, 1, 4, 1184, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1942 = LWUPC |
5542 | | { 1941, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 908, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1941 = LWSP_MM |
5543 | | { 1940, 4, 1, 4, 1127, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1940 = LWR_MM |
5544 | | { 1939, 4, 1, 4, 1097, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1939 = LWRE_MM |
5545 | | { 1938, 4, 1, 4, 451, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1938 = LWRE |
5546 | | { 1937, 4, 1, 4, 1172, 0, 0, MipsImpOpBase + 0, 860, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1937 = LWR64 |
5547 | | { 1936, 4, 1, 4, 449, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1936 = LWR |
5548 | | { 1935, 4, 2, 4, 1126, 0, 0, MipsImpOpBase + 0, 904, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1935 = LWP_MM |
5549 | | { 1934, 2, 1, 4, 1151, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1934 = LWPC_MMR6 |
5550 | | { 1933, 2, 1, 4, 447, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1933 = LWPC |
5551 | | { 1932, 3, 1, 4, 1125, 0, 0, MipsImpOpBase + 0, 349, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1932 = LWM32_MM |
5552 | | { 1931, 3, 1, 2, 1149, 0, 0, MipsImpOpBase + 0, 901, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1931 = LWM16_MMR6 |
5553 | | { 1930, 3, 1, 2, 1125, 0, 0, MipsImpOpBase + 0, 901, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1930 = LWM16_MM |
5554 | | { 1929, 4, 1, 4, 1124, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1929 = LWL_MM |
5555 | | { 1928, 4, 1, 4, 1096, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1928 = LWLE_MM |
5556 | | { 1927, 4, 1, 4, 450, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1927 = LWLE |
5557 | | { 1926, 4, 1, 4, 1171, 0, 0, MipsImpOpBase + 0, 860, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1926 = LWL64 |
5558 | | { 1925, 4, 1, 4, 448, 0, 0, MipsImpOpBase + 0, 897, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1925 = LWL |
5559 | | { 1924, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 894, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1924 = LWGP_MM |
5560 | | { 1923, 3, 1, 4, 1095, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1923 = LWE_MM |
5561 | | { 1922, 3, 1, 4, 445, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1922 = LWE |
5562 | | { 1921, 3, 1, 4, 1506, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1921 = LWDSP_MM |
5563 | | { 1920, 3, 1, 4, 1343, 0, 0, MipsImpOpBase + 0, 891, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1920 = LWDSP |
5564 | | { 1919, 3, 1, 4, 438, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1919 = LWC3 |
5565 | | { 1918, 3, 1, 4, 1083, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1918 = LWC2_R6 |
5566 | | { 1917, 3, 1, 4, 1150, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1917 = LWC2_MMR6 |
5567 | | { 1916, 3, 1, 4, 437, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1916 = LWC2 |
5568 | | { 1915, 3, 1, 4, 1298, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1915 = LWC1_MM |
5569 | | { 1914, 3, 1, 4, 712, 0, 0, MipsImpOpBase + 0, 888, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1914 = LWC1 |
5570 | | { 1913, 3, 1, 4, 1170, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1913 = LW64 |
5571 | | { 1912, 3, 1, 2, 1123, 0, 0, MipsImpOpBase + 0, 834, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #1912 = LW16_MM |
5572 | | { 1911, 3, 1, 4, 435, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1911 = LW |
5573 | | { 1910, 2, 1, 4, 749, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1910 = LUi_MM |
5574 | | { 1909, 2, 1, 4, 841, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1909 = LUi64 |
5575 | | { 1908, 2, 1, 4, 365, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1908 = LUi |
5576 | | { 1907, 3, 1, 4, 1297, 0, 0, MipsImpOpBase + 0, 867, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1907 = LUXC1_MM |
5577 | | { 1906, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 867, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1906 = LUXC164 |
5578 | | { 1905, 3, 1, 4, 714, 0, 0, MipsImpOpBase + 0, 864, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x5ULL }, // Inst #1905 = LUXC1 |
5579 | | { 1904, 2, 1, 4, 791, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #1904 = LUI_MMR6 |
5580 | | { 1903, 4, 1, 4, 733, 0, 0, MipsImpOpBase + 0, 557, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1903 = LSA_R6 |
5581 | | { 1902, 4, 1, 4, 790, 0, 0, MipsImpOpBase + 0, 557, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1902 = LSA_MMR6 |
5582 | | { 1901, 4, 1, 4, 513, 0, 0, MipsImpOpBase + 0, 557, 0, 0x6ULL }, // Inst #1901 = LSA |
5583 | | { 1900, 3, 1, 4, 1082, 0, 0, MipsImpOpBase + 0, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1900 = LL_R6 |
5584 | | { 1899, 3, 1, 4, 1148, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1899 = LL_MMR6 |
5585 | | { 1898, 3, 1, 4, 1122, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1898 = LL_MM |
5586 | | { 1897, 3, 1, 4, 1098, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1897 = LLE_MM |
5587 | | { 1896, 3, 1, 4, 446, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1896 = LLE |
5588 | | { 1895, 3, 1, 4, 1186, 0, 0, MipsImpOpBase + 0, 885, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1895 = LLD_R6 |
5589 | | { 1894, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1894 = LLD |
5590 | | { 1893, 3, 1, 4, 1187, 0, 0, MipsImpOpBase + 0, 882, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1893 = LL64_R6 |
5591 | | { 1892, 3, 1, 4, 1164, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1892 = LL64 |
5592 | | { 1891, 3, 1, 4, 436, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1891 = LL |
5593 | | { 1890, 2, 1, 2, 789, 0, 0, MipsImpOpBase + 0, 525, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1890 = LI16_MMR6 |
5594 | | { 1889, 2, 1, 2, 748, 0, 0, MipsImpOpBase + 0, 525, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #1889 = LI16_MM |
5595 | | { 1888, 3, 1, 4, 1120, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1888 = LHu_MM |
5596 | | { 1887, 3, 1, 4, 1094, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1887 = LHuE_MM |
5597 | | { 1886, 3, 1, 4, 444, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1886 = LHuE |
5598 | | { 1885, 3, 1, 4, 1169, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1885 = LHu64 |
5599 | | { 1884, 3, 1, 4, 434, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1884 = LHu |
5600 | | { 1883, 3, 1, 4, 1121, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1883 = LH_MM |
5601 | | { 1882, 3, 1, 4, 1550, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1882 = LHX_MM |
5602 | | { 1881, 3, 1, 4, 1390, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1881 = LHX |
5603 | | { 1880, 3, 1, 2, 1120, 0, 0, MipsImpOpBase + 0, 834, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1880 = LHU16_MM |
5604 | | { 1879, 3, 1, 4, 1093, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1879 = LHE_MM |
5605 | | { 1878, 3, 1, 4, 443, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1878 = LHE |
5606 | | { 1877, 3, 1, 4, 1168, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1877 = LH64 |
5607 | | { 1876, 3, 1, 4, 433, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1876 = LH |
5608 | | { 1875, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 307, 0, 0x2ULL }, // Inst #1875 = LEA_ADDiu_MM |
5609 | | { 1874, 3, 1, 4, 840, 0, 0, MipsImpOpBase + 0, 356, 0, 0x2ULL }, // Inst #1874 = LEA_ADDiu64 |
5610 | | { 1873, 3, 1, 4, 724, 0, 0, MipsImpOpBase + 0, 307, 0, 0x2ULL }, // Inst #1873 = LEA_ADDiu |
5611 | | { 1872, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 879, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1872 = LD_W |
5612 | | { 1871, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 876, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1871 = LD_H |
5613 | | { 1870, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 873, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1870 = LD_D |
5614 | | { 1869, 3, 1, 4, 715, 0, 0, MipsImpOpBase + 0, 870, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1869 = LD_B |
5615 | | { 1868, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 867, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1868 = LDXC164 |
5616 | | { 1867, 3, 1, 4, 711, 0, 0, MipsImpOpBase + 0, 864, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1867 = LDXC1 |
5617 | | { 1866, 4, 1, 4, 1174, 0, 0, MipsImpOpBase + 0, 860, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1866 = LDR |
5618 | | { 1865, 2, 1, 4, 1185, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1865 = LDPC |
5619 | | { 1864, 4, 1, 4, 1173, 0, 0, MipsImpOpBase + 0, 860, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1864 = LDL |
5620 | | { 1863, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 858, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1863 = LDI_W |
5621 | | { 1862, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 856, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1862 = LDI_H |
5622 | | { 1861, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 854, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1861 = LDI_D |
5623 | | { 1860, 2, 1, 4, 547, 0, 0, MipsImpOpBase + 0, 852, 0|(1ULL<<MCID::Rematerializable), 0x6ULL }, // Inst #1860 = LDI_B |
5624 | | { 1859, 3, 1, 4, 440, 0, 0, MipsImpOpBase + 0, 849, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1859 = LDC3 |
5625 | | { 1858, 3, 1, 4, 1081, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1858 = LDC2_R6 |
5626 | | { 1857, 3, 1, 4, 1147, 0, 0, MipsImpOpBase + 0, 846, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1857 = LDC2_MMR6 |
5627 | | { 1856, 3, 1, 4, 439, 0, 0, MipsImpOpBase + 0, 843, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1856 = LDC2 |
5628 | | { 1855, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 840, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1855 = LDC1_MM_D64 |
5629 | | { 1854, 3, 1, 4, 1296, 0, 0, MipsImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1854 = LDC1_MM_D32 |
5630 | | { 1853, 3, 1, 4, 1339, 0, 0, MipsImpOpBase + 0, 840, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1853 = LDC1_D64_MMR6 |
5631 | | { 1852, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 840, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1852 = LDC164 |
5632 | | { 1851, 3, 1, 4, 710, 0, 0, MipsImpOpBase + 0, 492, 0|(1ULL<<MCID::MayLoad), 0x5ULL }, // Inst #1851 = LDC1 |
5633 | | { 1850, 3, 1, 4, 1163, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1850 = LD |
5634 | | { 1849, 3, 1, 4, 1118, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1849 = LBu_MM |
5635 | | { 1848, 3, 1, 4, 1092, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1848 = LBuE_MM |
5636 | | { 1847, 3, 1, 4, 442, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1847 = LBuE |
5637 | | { 1846, 3, 1, 4, 1167, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1846 = LBu64 |
5638 | | { 1845, 3, 1, 4, 432, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1845 = LBu |
5639 | | { 1844, 3, 1, 4, 1146, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1844 = LB_MMR6 |
5640 | | { 1843, 3, 1, 4, 1119, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1843 = LB_MM |
5641 | | { 1842, 3, 1, 4, 1145, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1842 = LBU_MMR6 |
5642 | | { 1841, 3, 1, 4, 1549, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1841 = LBUX_MM |
5643 | | { 1840, 3, 1, 4, 1389, 0, 0, MipsImpOpBase + 0, 837, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1840 = LBUX |
5644 | | { 1839, 3, 1, 2, 1118, 0, 0, MipsImpOpBase + 0, 834, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1839 = LBU16_MM |
5645 | | { 1838, 3, 1, 4, 1091, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1838 = LBE_MM |
5646 | | { 1837, 3, 1, 4, 441, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1837 = LBE |
5647 | | { 1836, 3, 1, 4, 1166, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1836 = LB64 |
5648 | | { 1835, 3, 1, 4, 431, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL }, // Inst #1835 = LB |
5649 | | { 1834, 1, 0, 2, 942, 0, 1, MipsImpOpBase + 3, 833, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1834 = JumpLinkReg16 |
5650 | | { 1833, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 833, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1833 = JrcRx16 |
5651 | | { 1832, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1832 = JrcRa16 |
5652 | | { 1831, 0, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1831 = JrRa16 |
5653 | | { 1830, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1830 = JalB16 |
5654 | | { 1829, 1, 0, 6, 941, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Call), 0x0ULL }, // Inst #1829 = Jal16 |
5655 | | { 1828, 1, 0, 4, 955, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1828 = J_MM |
5656 | | { 1827, 1, 0, 4, 954, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1827 = JR_MM |
5657 | | { 1826, 1, 0, 4, 934, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1826 = JR_HB_R6 |
5658 | | { 1825, 1, 0, 4, 1022, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1825 = JR_HB64_R6 |
5659 | | { 1824, 1, 0, 4, 1014, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1824 = JR_HB64 |
5660 | | { 1823, 1, 0, 4, 386, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1823 = JR_HB |
5661 | | { 1822, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1822 = JRCADDIUSP_MMR6 |
5662 | | { 1821, 1, 0, 2, 995, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1821 = JRC16_MMR6 |
5663 | | { 1820, 1, 0, 2, 994, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1820 = JRC16_MM |
5664 | | { 1819, 1, 0, 2, 993, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1819 = JRADDIUSP |
5665 | | { 1818, 1, 0, 4, 1011, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1818 = JR64 |
5666 | | { 1817, 1, 0, 2, 954, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1817 = JR16_MM |
5667 | | { 1816, 1, 0, 4, 923, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1816 = JR |
5668 | | { 1815, 2, 0, 4, 992, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1815 = JIC_MMR6 |
5669 | | { 1814, 2, 0, 4, 1019, 0, 1, MipsImpOpBase + 2, 354, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1814 = JIC64 |
5670 | | { 1813, 2, 0, 4, 933, 0, 1, MipsImpOpBase + 2, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1813 = JIC |
5671 | | { 1812, 2, 0, 4, 1004, 0, 1, MipsImpOpBase + 3, 359, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1812 = JIALC_MMR6 |
5672 | | { 1811, 2, 0, 4, 1021, 0, 1, MipsImpOpBase + 3, 354, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1811 = JIALC64 |
5673 | | { 1810, 2, 0, 4, 928, 0, 1, MipsImpOpBase + 3, 359, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1810 = JIALC |
5674 | | { 1809, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1809 = JAL_MM |
5675 | | { 1808, 1, 0, 4, 962, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1808 = JALX_MM |
5676 | | { 1807, 1, 0, 4, 409, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1807 = JALX |
5677 | | { 1806, 1, 0, 4, 961, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1806 = JALS_MM |
5678 | | { 1805, 2, 1, 4, 959, 0, 1, MipsImpOpBase + 3, 140, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1805 = JALR_MM |
5679 | | { 1804, 2, 1, 4, 1013, 0, 0, MipsImpOpBase + 0, 377, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1804 = JALR_HB64 |
5680 | | { 1803, 2, 1, 4, 408, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL }, // Inst #1803 = JALR_HB |
5681 | | { 1802, 2, 1, 4, 960, 0, 1, MipsImpOpBase + 3, 140, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1802 = JALRS_MM |
5682 | | { 1801, 1, 0, 2, 960, 0, 1, MipsImpOpBase + 3, 185, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1801 = JALRS16_MM |
5683 | | { 1800, 2, 1, 4, 1003, 0, 1, MipsImpOpBase + 3, 140, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1800 = JALRC_MMR6 |
5684 | | { 1799, 2, 1, 4, 1002, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL }, // Inst #1799 = JALRC_HB_MMR6 |
5685 | | { 1798, 1, 0, 2, 1001, 0, 1, MipsImpOpBase + 3, 185, 0|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1798 = JALRC16_MMR6 |
5686 | | { 1797, 2, 1, 4, 1012, 0, 1, MipsImpOpBase + 3, 377, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1797 = JALR64 |
5687 | | { 1796, 1, 0, 2, 959, 0, 1, MipsImpOpBase + 3, 185, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x0ULL }, // Inst #1796 = JALR16_MM |
5688 | | { 1795, 2, 1, 4, 407, 0, 1, MipsImpOpBase + 3, 140, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL }, // Inst #1795 = JALR |
5689 | | { 1794, 1, 0, 4, 406, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call), 0x13ULL }, // Inst #1794 = JAL |
5690 | | { 1793, 1, 0, 4, 922, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x13ULL }, // Inst #1793 = J |
5691 | | { 1792, 5, 1, 4, 788, 0, 0, MipsImpOpBase + 0, 789, 0, 0x1ULL }, // Inst #1792 = INS_MMR6 |
5692 | | { 1791, 5, 1, 4, 747, 0, 0, MipsImpOpBase + 0, 789, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1791 = INS_MM |
5693 | | { 1790, 3, 1, 4, 1548, 2, 0, MipsImpOpBase + 30, 810, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1790 = INSV_MM |
5694 | | { 1789, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 828, 0, 0x6ULL }, // Inst #1789 = INSVE_W |
5695 | | { 1788, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 823, 0, 0x6ULL }, // Inst #1788 = INSVE_H |
5696 | | { 1787, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 818, 0, 0x6ULL }, // Inst #1787 = INSVE_D |
5697 | | { 1786, 5, 1, 4, 607, 0, 0, MipsImpOpBase + 0, 813, 0, 0x6ULL }, // Inst #1786 = INSVE_B |
5698 | | { 1785, 3, 1, 4, 1353, 2, 0, MipsImpOpBase + 30, 810, 0|(1ULL<<MCID::MayLoad), 0x6ULL }, // Inst #1785 = INSV |
5699 | | { 1784, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 806, 0, 0x6ULL }, // Inst #1784 = INSERT_W |
5700 | | { 1783, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 802, 0, 0x6ULL }, // Inst #1783 = INSERT_H |
5701 | | { 1782, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 798, 0, 0x6ULL }, // Inst #1782 = INSERT_D |
5702 | | { 1781, 4, 1, 4, 518, 0, 0, MipsImpOpBase + 0, 794, 0, 0x6ULL }, // Inst #1781 = INSERT_B |
5703 | | { 1780, 5, 1, 4, 495, 0, 0, MipsImpOpBase + 0, 789, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1780 = INS |
5704 | | { 1779, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1779 = ILVR_W |
5705 | | { 1778, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1778 = ILVR_H |
5706 | | { 1777, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1777 = ILVR_D |
5707 | | { 1776, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1776 = ILVR_B |
5708 | | { 1775, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1775 = ILVOD_W |
5709 | | { 1774, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1774 = ILVOD_H |
5710 | | { 1773, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1773 = ILVOD_D |
5711 | | { 1772, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1772 = ILVOD_B |
5712 | | { 1771, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1771 = ILVL_W |
5713 | | { 1770, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1770 = ILVL_H |
5714 | | { 1769, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1769 = ILVL_D |
5715 | | { 1768, 3, 1, 4, 605, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1768 = ILVL_B |
5716 | | { 1767, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1767 = ILVEV_W |
5717 | | { 1766, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1766 = ILVEV_H |
5718 | | { 1765, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1765 = ILVEV_D |
5719 | | { 1764, 3, 1, 4, 606, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1764 = ILVEV_B |
5720 | | { 1763, 1, 0, 4, 1069, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1763 = HYPCALL_MM |
5721 | | { 1762, 1, 0, 4, 420, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1762 = HYPCALL |
5722 | | { 1761, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 724, 0, 0x6ULL }, // Inst #1761 = HSUB_U_W |
5723 | | { 1760, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 721, 0, 0x6ULL }, // Inst #1760 = HSUB_U_H |
5724 | | { 1759, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 718, 0, 0x6ULL }, // Inst #1759 = HSUB_U_D |
5725 | | { 1758, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 724, 0, 0x6ULL }, // Inst #1758 = HSUB_S_W |
5726 | | { 1757, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 721, 0, 0x6ULL }, // Inst #1757 = HSUB_S_H |
5727 | | { 1756, 3, 1, 4, 616, 0, 0, MipsImpOpBase + 0, 718, 0, 0x6ULL }, // Inst #1756 = HSUB_S_D |
5728 | | { 1755, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 724, 0, 0x6ULL }, // Inst #1755 = HADD_U_W |
5729 | | { 1754, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 721, 0, 0x6ULL }, // Inst #1754 = HADD_U_H |
5730 | | { 1753, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 718, 0, 0x6ULL }, // Inst #1753 = HADD_U_D |
5731 | | { 1752, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 724, 0, 0x6ULL }, // Inst #1752 = HADD_S_W |
5732 | | { 1751, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 721, 0, 0x6ULL }, // Inst #1751 = HADD_S_H |
5733 | | { 1750, 3, 1, 4, 615, 0, 0, MipsImpOpBase + 0, 718, 0, 0x6ULL }, // Inst #1750 = HADD_S_D |
5734 | | { 1749, 2, 0, 4, 1144, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1749 = GINVT_MMR6 |
5735 | | { 1748, 2, 0, 4, 1090, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1748 = GINVT |
5736 | | { 1747, 1, 0, 4, 1143, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1747 = GINVI_MMR6 |
5737 | | { 1746, 1, 0, 4, 1089, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1746 = GINVI |
5738 | | { 1745, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1745 = FTRUNC_U_W |
5739 | | { 1744, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1744 = FTRUNC_U_D |
5740 | | { 1743, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1743 = FTRUNC_S_W |
5741 | | { 1742, 2, 1, 4, 595, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1742 = FTRUNC_S_D |
5742 | | { 1741, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 774, 0, 0x6ULL }, // Inst #1741 = FTQ_W |
5743 | | { 1740, 3, 1, 4, 594, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #1740 = FTQ_H |
5744 | | { 1739, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1739 = FTINT_U_W |
5745 | | { 1738, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1738 = FTINT_U_D |
5746 | | { 1737, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1737 = FTINT_S_W |
5747 | | { 1736, 2, 1, 4, 592, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1736 = FTINT_S_D |
5748 | | { 1735, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1735 = FSUN_W |
5749 | | { 1734, 3, 1, 4, 576, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1734 = FSUN_D |
5750 | | { 1733, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1733 = FSUNE_W |
5751 | | { 1732, 3, 1, 4, 575, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1732 = FSUNE_D |
5752 | | { 1731, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1731 = FSULT_W |
5753 | | { 1730, 3, 1, 4, 574, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1730 = FSULT_D |
5754 | | { 1729, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1729 = FSULE_W |
5755 | | { 1728, 3, 1, 4, 573, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1728 = FSULE_D |
5756 | | { 1727, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1727 = FSUEQ_W |
5757 | | { 1726, 3, 1, 4, 572, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1726 = FSUEQ_D |
5758 | | { 1725, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1725 = FSUB_W |
5759 | | { 1724, 3, 1, 4, 1335, 0, 0, MipsImpOpBase + 0, 759, 0, 0x6ULL }, // Inst #1724 = FSUB_S_MMR6 |
5760 | | { 1723, 3, 1, 4, 1281, 0, 0, MipsImpOpBase + 0, 759, 0, 0x4ULL }, // Inst #1723 = FSUB_S_MM |
5761 | | { 1722, 3, 1, 4, 636, 0, 0, MipsImpOpBase + 0, 759, 0, 0x4ULL }, // Inst #1722 = FSUB_S |
5762 | | { 1721, 3, 1, 4, 635, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1721 = FSUB_PS64 |
5763 | | { 1720, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 536, 0, 0x4ULL }, // Inst #1720 = FSUB_D64_MM |
5764 | | { 1719, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 536, 0, 0x4ULL }, // Inst #1719 = FSUB_D64 |
5765 | | { 1718, 3, 1, 4, 1280, 0, 0, MipsImpOpBase + 0, 756, 0, 0x4ULL }, // Inst #1718 = FSUB_D32_MM |
5766 | | { 1717, 3, 1, 4, 634, 0, 0, MipsImpOpBase + 0, 756, 0, 0x4ULL }, // Inst #1717 = FSUB_D32 |
5767 | | { 1716, 3, 1, 4, 664, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1716 = FSUB_D |
5768 | | { 1715, 2, 1, 4, 660, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1715 = FSQRT_W |
5769 | | { 1714, 2, 1, 4, 1286, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1714 = FSQRT_S_MM |
5770 | | { 1713, 2, 1, 4, 648, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1713 = FSQRT_S |
5771 | | { 1712, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1712 = FSQRT_D64_MM |
5772 | | { 1711, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1711 = FSQRT_D64 |
5773 | | { 1710, 2, 1, 4, 1287, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1710 = FSQRT_D32_MM |
5774 | | { 1709, 2, 1, 4, 649, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1709 = FSQRT_D32 |
5775 | | { 1708, 2, 1, 4, 661, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1708 = FSQRT_D |
5776 | | { 1707, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1707 = FSOR_W |
5777 | | { 1706, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1706 = FSOR_D |
5778 | | { 1705, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1705 = FSNE_W |
5779 | | { 1704, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1704 = FSNE_D |
5780 | | { 1703, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1703 = FSLT_W |
5781 | | { 1702, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1702 = FSLT_D |
5782 | | { 1701, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1701 = FSLE_W |
5783 | | { 1700, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1700 = FSLE_D |
5784 | | { 1699, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1699 = FSEQ_W |
5785 | | { 1698, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1698 = FSEQ_D |
5786 | | { 1697, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1697 = FSAF_W |
5787 | | { 1696, 3, 1, 4, 571, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1696 = FSAF_D |
5788 | | { 1695, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1695 = FRSQRT_W |
5789 | | { 1694, 2, 1, 4, 651, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1694 = FRSQRT_D |
5790 | | { 1693, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1693 = FRINT_W |
5791 | | { 1692, 2, 1, 4, 593, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1692 = FRINT_D |
5792 | | { 1691, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1691 = FRCP_W |
5793 | | { 1690, 2, 1, 4, 650, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1690 = FRCP_D |
5794 | | { 1689, 3, 2, 4, 1066, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1689 = FORK |
5795 | | { 1688, 2, 1, 4, 1300, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1688 = FNEG_S_MMR6 |
5796 | | { 1687, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1687 = FNEG_S_MM |
5797 | | { 1686, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1686 = FNEG_S |
5798 | | { 1685, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1685 = FNEG_D64_MM |
5799 | | { 1684, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1684 = FNEG_D64 |
5800 | | { 1683, 2, 1, 4, 1273, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1683 = FNEG_D32_MM |
5801 | | { 1682, 2, 1, 4, 537, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1682 = FNEG_D32 |
5802 | | { 1681, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1681 = FMUL_W |
5803 | | { 1680, 3, 1, 4, 1334, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1680 = FMUL_S_MMR6 |
5804 | | { 1679, 3, 1, 4, 1279, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1679 = FMUL_S_MM |
5805 | | { 1678, 3, 1, 4, 633, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1678 = FMUL_S |
5806 | | { 1677, 3, 1, 4, 632, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1677 = FMUL_PS64 |
5807 | | { 1676, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1676 = FMUL_D64_MM |
5808 | | { 1675, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1675 = FMUL_D64 |
5809 | | { 1674, 3, 1, 4, 1278, 0, 0, MipsImpOpBase + 0, 756, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1674 = FMUL_D32_MM |
5810 | | { 1673, 3, 1, 4, 631, 0, 0, MipsImpOpBase + 0, 756, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1673 = FMUL_D32 |
5811 | | { 1672, 3, 1, 4, 662, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1672 = FMUL_D |
5812 | | { 1671, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1671 = FMSUB_W |
5813 | | { 1670, 4, 1, 4, 657, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1670 = FMSUB_D |
5814 | | { 1669, 2, 1, 4, 1333, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1669 = FMOV_S_MMR6 |
5815 | | { 1668, 2, 1, 4, 1277, 0, 0, MipsImpOpBase + 0, 631, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1668 = FMOV_S_MM |
5816 | | { 1667, 2, 1, 4, 536, 0, 0, MipsImpOpBase + 0, 631, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1667 = FMOV_S |
5817 | | { 1666, 2, 1, 4, 1336, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1666 = FMOV_D_MMR6 |
5818 | | { 1665, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1665 = FMOV_D64_MM |
5819 | | { 1664, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 623, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1664 = FMOV_D64 |
5820 | | { 1663, 2, 1, 4, 1276, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1663 = FMOV_D32_MM |
5821 | | { 1662, 2, 1, 4, 535, 0, 0, MipsImpOpBase + 0, 754, 0|(1ULL<<MCID::MoveReg), 0x4ULL }, // Inst #1662 = FMOV_D32 |
5822 | | { 1661, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1661 = FMIN_W |
5823 | | { 1660, 3, 1, 4, 603, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1660 = FMIN_D |
5824 | | { 1659, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1659 = FMIN_A_W |
5825 | | { 1658, 3, 1, 4, 602, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1658 = FMIN_A_D |
5826 | | { 1657, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1657 = FMAX_W |
5827 | | { 1656, 3, 1, 4, 601, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1656 = FMAX_D |
5828 | | { 1655, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1655 = FMAX_A_W |
5829 | | { 1654, 3, 1, 4, 600, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1654 = FMAX_A_D |
5830 | | { 1653, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #1653 = FMADD_W |
5831 | | { 1652, 4, 1, 4, 656, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #1652 = FMADD_D |
5832 | | { 1651, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1651 = FLOOR_W_S_MMR6 |
5833 | | { 1650, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1650 = FLOOR_W_S_MM |
5834 | | { 1649, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1649 = FLOOR_W_S |
5835 | | { 1648, 2, 1, 4, 1248, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1648 = FLOOR_W_MM |
5836 | | { 1647, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1647 = FLOOR_W_D_MMR6 |
5837 | | { 1646, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1646 = FLOOR_W_D64 |
5838 | | { 1645, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1645 = FLOOR_W_D32 |
5839 | | { 1644, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1644 = FLOOR_L_S_MMR6 |
5840 | | { 1643, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1643 = FLOOR_L_S |
5841 | | { 1642, 2, 1, 4, 1310, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1642 = FLOOR_L_D_MMR6 |
5842 | | { 1641, 2, 1, 4, 718, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1641 = FLOOR_L_D64 |
5843 | | { 1640, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1640 = FLOG2_W |
5844 | | { 1639, 2, 1, 4, 604, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1639 = FLOG2_D |
5845 | | { 1638, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 787, 0, 0x6ULL }, // Inst #1638 = FILL_W |
5846 | | { 1637, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 785, 0, 0x6ULL }, // Inst #1637 = FILL_H |
5847 | | { 1636, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 783, 0, 0x6ULL }, // Inst #1636 = FILL_D |
5848 | | { 1635, 2, 1, 4, 544, 0, 0, MipsImpOpBase + 0, 781, 0, 0x6ULL }, // Inst #1635 = FILL_B |
5849 | | { 1634, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1634 = FFQR_W |
5850 | | { 1633, 2, 1, 4, 591, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1633 = FFQR_D |
5851 | | { 1632, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1632 = FFQL_W |
5852 | | { 1631, 2, 1, 4, 590, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1631 = FFQL_D |
5853 | | { 1630, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1630 = FFINT_U_W |
5854 | | { 1629, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1629 = FFINT_U_D |
5855 | | { 1628, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1628 = FFINT_S_W |
5856 | | { 1627, 2, 1, 4, 589, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1627 = FFINT_S_D |
5857 | | { 1626, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1626 = FEXUPR_W |
5858 | | { 1625, 2, 1, 4, 598, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1625 = FEXUPR_D |
5859 | | { 1624, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 779, 0, 0x6ULL }, // Inst #1624 = FEXUPL_W |
5860 | | { 1623, 2, 1, 4, 597, 0, 0, MipsImpOpBase + 0, 777, 0, 0x6ULL }, // Inst #1623 = FEXUPL_D |
5861 | | { 1622, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1622 = FEXP2_W |
5862 | | { 1621, 3, 1, 4, 553, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1621 = FEXP2_D |
5863 | | { 1620, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 774, 0, 0x6ULL }, // Inst #1620 = FEXDO_W |
5864 | | { 1619, 3, 1, 4, 596, 0, 0, MipsImpOpBase + 0, 771, 0, 0x6ULL }, // Inst #1619 = FEXDO_H |
5865 | | { 1618, 3, 1, 4, 658, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1618 = FDIV_W |
5866 | | { 1617, 3, 1, 4, 1337, 0, 0, MipsImpOpBase + 0, 759, 0, 0x6ULL }, // Inst #1617 = FDIV_S_MMR6 |
5867 | | { 1616, 3, 1, 4, 1284, 0, 0, MipsImpOpBase + 0, 759, 0, 0x4ULL }, // Inst #1616 = FDIV_S_MM |
5868 | | { 1615, 3, 1, 4, 646, 0, 0, MipsImpOpBase + 0, 759, 0, 0x4ULL }, // Inst #1615 = FDIV_S |
5869 | | { 1614, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 536, 0, 0x4ULL }, // Inst #1614 = FDIV_D64_MM |
5870 | | { 1613, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 536, 0, 0x4ULL }, // Inst #1613 = FDIV_D64 |
5871 | | { 1612, 3, 1, 4, 1285, 0, 0, MipsImpOpBase + 0, 756, 0, 0x4ULL }, // Inst #1612 = FDIV_D32_MM |
5872 | | { 1611, 3, 1, 4, 647, 0, 0, MipsImpOpBase + 0, 756, 0, 0x4ULL }, // Inst #1611 = FDIV_D32 |
5873 | | { 1610, 3, 1, 4, 659, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1610 = FDIV_D |
5874 | | { 1609, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1609 = FCUN_W |
5875 | | { 1608, 3, 1, 4, 587, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1608 = FCUN_D |
5876 | | { 1607, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1607 = FCUNE_W |
5877 | | { 1606, 3, 1, 4, 586, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1606 = FCUNE_D |
5878 | | { 1605, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1605 = FCULT_W |
5879 | | { 1604, 3, 1, 4, 585, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1604 = FCULT_D |
5880 | | { 1603, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1603 = FCULE_W |
5881 | | { 1602, 3, 1, 4, 584, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1602 = FCULE_D |
5882 | | { 1601, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1601 = FCUEQ_W |
5883 | | { 1600, 3, 1, 4, 583, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1600 = FCUEQ_D |
5884 | | { 1599, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1599 = FCOR_W |
5885 | | { 1598, 3, 1, 4, 582, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1598 = FCOR_D |
5886 | | { 1597, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1597 = FCNE_W |
5887 | | { 1596, 3, 1, 4, 581, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1596 = FCNE_D |
5888 | | { 1595, 3, 0, 4, 1265, 0, 1, MipsImpOpBase + 29, 768, 0, 0x44ULL }, // Inst #1595 = FCMP_S32_MM |
5889 | | { 1594, 3, 0, 4, 643, 0, 1, MipsImpOpBase + 29, 768, 0, 0x44ULL }, // Inst #1594 = FCMP_S32 |
5890 | | { 1593, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 765, 0, 0x44ULL }, // Inst #1593 = FCMP_D64 |
5891 | | { 1592, 3, 0, 4, 1266, 0, 1, MipsImpOpBase + 29, 762, 0, 0x44ULL }, // Inst #1592 = FCMP_D32_MM |
5892 | | { 1591, 3, 0, 4, 642, 0, 1, MipsImpOpBase + 29, 762, 0, 0x44ULL }, // Inst #1591 = FCMP_D32 |
5893 | | { 1590, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1590 = FCLT_W |
5894 | | { 1589, 3, 1, 4, 580, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1589 = FCLT_D |
5895 | | { 1588, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1588 = FCLE_W |
5896 | | { 1587, 3, 1, 4, 579, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1587 = FCLE_D |
5897 | | { 1586, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 240, 0, 0x6ULL }, // Inst #1586 = FCLASS_W |
5898 | | { 1585, 2, 1, 4, 599, 0, 0, MipsImpOpBase + 0, 238, 0, 0x6ULL }, // Inst #1585 = FCLASS_D |
5899 | | { 1584, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1584 = FCEQ_W |
5900 | | { 1583, 3, 1, 4, 578, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1583 = FCEQ_D |
5901 | | { 1582, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1582 = FCAF_W |
5902 | | { 1581, 3, 1, 4, 577, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1581 = FCAF_D |
5903 | | { 1580, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1580 = FADD_W |
5904 | | { 1579, 3, 1, 4, 1315, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1579 = FADD_S_MMR6 |
5905 | | { 1578, 3, 1, 4, 1275, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1578 = FADD_S_MM |
5906 | | { 1577, 3, 1, 4, 630, 0, 0, MipsImpOpBase + 0, 759, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1577 = FADD_S |
5907 | | { 1576, 3, 1, 4, 629, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1576 = FADD_PS64 |
5908 | | { 1575, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1575 = FADD_D64_MM |
5909 | | { 1574, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1574 = FADD_D64 |
5910 | | { 1573, 3, 1, 4, 1274, 0, 0, MipsImpOpBase + 0, 756, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1573 = FADD_D32_MM |
5911 | | { 1572, 3, 1, 4, 628, 0, 0, MipsImpOpBase + 0, 756, 0|(1ULL<<MCID::Commutable), 0x4ULL }, // Inst #1572 = FADD_D32 |
5912 | | { 1571, 3, 1, 4, 663, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1571 = FADD_D |
5913 | | { 1570, 2, 1, 4, 1272, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1570 = FABS_S_MM |
5914 | | { 1569, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1569 = FABS_S |
5915 | | { 1568, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1568 = FABS_D64_MM |
5916 | | { 1567, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1567 = FABS_D64 |
5917 | | { 1566, 2, 1, 4, 1271, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1566 = FABS_D32_MM |
5918 | | { 1565, 2, 1, 4, 530, 0, 0, MipsImpOpBase + 0, 754, 0, 0x4ULL }, // Inst #1565 = FABS_D32 |
5919 | | { 1564, 4, 1, 4, 787, 0, 0, MipsImpOpBase + 0, 647, 0, 0x1ULL }, // Inst #1564 = EXT_MMR6 |
5920 | | { 1563, 4, 1, 4, 746, 0, 0, MipsImpOpBase + 0, 647, 0, 0x1ULL }, // Inst #1563 = EXT_MM |
5921 | | { 1562, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 639, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1562 = EXTS32 |
5922 | | { 1561, 4, 1, 4, 1204, 0, 0, MipsImpOpBase + 0, 639, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1561 = EXTS |
5923 | | { 1560, 3, 1, 4, 1547, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1560 = EXTR_W_MM |
5924 | | { 1559, 3, 1, 4, 1352, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1559 = EXTR_W |
5925 | | { 1558, 3, 1, 4, 1546, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1558 = EXTR_S_H_MM |
5926 | | { 1557, 3, 1, 4, 1351, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1557 = EXTR_S_H |
5927 | | { 1556, 3, 1, 4, 1545, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1556 = EXTR_R_W_MM |
5928 | | { 1555, 3, 1, 4, 1350, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1555 = EXTR_R_W |
5929 | | { 1554, 3, 1, 4, 1544, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1554 = EXTR_RS_W_MM |
5930 | | { 1553, 3, 1, 4, 1349, 0, 1, MipsImpOpBase + 28, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1553 = EXTR_RS_W |
5931 | | { 1552, 3, 1, 4, 1543, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1552 = EXTRV_W_MM |
5932 | | { 1551, 3, 1, 4, 1348, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1551 = EXTRV_W |
5933 | | { 1550, 3, 1, 4, 1542, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1550 = EXTRV_S_H_MM |
5934 | | { 1549, 3, 1, 4, 1347, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1549 = EXTRV_S_H |
5935 | | { 1548, 3, 1, 4, 1541, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1548 = EXTRV_R_W_MM |
5936 | | { 1547, 3, 1, 4, 1346, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1547 = EXTRV_R_W |
5937 | | { 1546, 3, 1, 4, 1540, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1546 = EXTRV_RS_W_MM |
5938 | | { 1545, 3, 1, 4, 1345, 0, 1, MipsImpOpBase + 28, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1545 = EXTRV_RS_W |
5939 | | { 1544, 3, 1, 4, 1539, 1, 1, MipsImpOpBase + 23, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1544 = EXTP_MM |
5940 | | { 1543, 3, 1, 4, 1538, 1, 1, MipsImpOpBase + 23, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1543 = EXTPV_MM |
5941 | | { 1542, 3, 1, 4, 1387, 1, 1, MipsImpOpBase + 23, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1542 = EXTPV |
5942 | | { 1541, 3, 1, 4, 1537, 1, 2, MipsImpOpBase + 25, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1541 = EXTPDP_MM |
5943 | | { 1540, 3, 1, 4, 1536, 1, 2, MipsImpOpBase + 25, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1540 = EXTPDPV_MM |
5944 | | { 1539, 3, 1, 4, 1385, 1, 2, MipsImpOpBase + 25, 751, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1539 = EXTPDPV |
5945 | | { 1538, 3, 1, 4, 1386, 1, 2, MipsImpOpBase + 25, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1538 = EXTPDP |
5946 | | { 1537, 3, 1, 4, 1388, 1, 1, MipsImpOpBase + 23, 748, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1537 = EXTP |
5947 | | { 1536, 4, 1, 4, 494, 0, 0, MipsImpOpBase + 0, 647, 0, 0x1ULL }, // Inst #1536 = EXT |
5948 | | { 1535, 1, 1, 4, 1046, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1535 = EVP_MMR6 |
5949 | | { 1534, 1, 1, 4, 1062, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1534 = EVPE |
5950 | | { 1533, 1, 1, 4, 1025, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1533 = EVP |
5951 | | { 1532, 0, 0, 4, 991, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1532 = ERET_MMR6 |
5952 | | { 1531, 0, 0, 4, 953, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1531 = ERET_MM |
5953 | | { 1530, 0, 0, 4, 989, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1530 = ERETNC_MMR6 |
5954 | | { 1529, 0, 0, 4, 383, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1529 = ERETNC |
5955 | | { 1528, 0, 0, 4, 381, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1528 = ERET |
5956 | | { 1527, 1, 1, 4, 1061, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1527 = EMT |
5957 | | { 1526, 1, 1, 4, 1049, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1526 = EI_MMR6 |
5958 | | { 1525, 1, 1, 4, 1032, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1525 = EI_MM |
5959 | | { 1524, 1, 1, 4, 477, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1524 = EI |
5960 | | { 1523, 0, 0, 4, 1050, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1523 = EHB_MMR6 |
5961 | | { 1522, 0, 0, 4, 1033, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1522 = EHB_MM |
5962 | | { 1521, 0, 0, 4, 479, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1521 = EHB |
5963 | | { 1520, 2, 0, 2, 877, 0, 2, MipsImpOpBase + 7, 394, 0, 0x0ULL }, // Inst #1520 = DivuRxRy16 |
5964 | | { 1519, 2, 0, 2, 876, 0, 2, MipsImpOpBase + 7, 394, 0, 0x0ULL }, // Inst #1519 = DivRxRy16 |
5965 | | { 1518, 1, 1, 4, 1047, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1518 = DVP_MMR6 |
5966 | | { 1517, 1, 1, 4, 1060, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1517 = DVPE |
5967 | | { 1516, 1, 1, 4, 1026, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1516 = DVP |
5968 | | { 1515, 2, 0, 4, 905, 0, 2, MipsImpOpBase + 20, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1515 = DUDIV |
5969 | | { 1514, 3, 1, 4, 839, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1514 = DSUBu |
5970 | | { 1513, 3, 1, 4, 838, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1513 = DSUB |
5971 | | { 1512, 3, 1, 4, 837, 0, 0, MipsImpOpBase + 0, 743, 0, 0x1ULL }, // Inst #1512 = DSRLV |
5972 | | { 1511, 3, 1, 4, 836, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1511 = DSRL32 |
5973 | | { 1510, 3, 1, 4, 835, 0, 0, MipsImpOpBase + 0, 220, 0, 0x1ULL }, // Inst #1510 = DSRL |
5974 | | { 1509, 3, 1, 4, 834, 0, 0, MipsImpOpBase + 0, 743, 0, 0x1ULL }, // Inst #1509 = DSRAV |
5975 | | { 1508, 3, 1, 4, 833, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1508 = DSRA32 |
5976 | | { 1507, 3, 1, 4, 832, 0, 0, MipsImpOpBase + 0, 220, 0, 0x1ULL }, // Inst #1507 = DSRA |
5977 | | { 1506, 3, 1, 4, 831, 0, 0, MipsImpOpBase + 0, 743, 0, 0x1ULL }, // Inst #1506 = DSLLV |
5978 | | { 1505, 2, 1, 4, 808, 0, 0, MipsImpOpBase + 0, 746, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1505 = DSLL64_32 |
5979 | | { 1504, 3, 1, 4, 830, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1504 = DSLL32 |
5980 | | { 1503, 3, 1, 4, 829, 0, 0, MipsImpOpBase + 0, 220, 0, 0x1ULL }, // Inst #1503 = DSLL |
5981 | | { 1502, 2, 1, 4, 828, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #1502 = DSHD |
5982 | | { 1501, 2, 0, 4, 904, 0, 2, MipsImpOpBase + 20, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1501 = DSDIV |
5983 | | { 1500, 2, 1, 4, 827, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #1500 = DSBH |
5984 | | { 1499, 3, 1, 4, 826, 0, 0, MipsImpOpBase + 0, 743, 0, 0x1ULL }, // Inst #1499 = DROTRV |
5985 | | { 1498, 3, 1, 4, 825, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1498 = DROTR32 |
5986 | | { 1497, 3, 1, 4, 824, 0, 0, MipsImpOpBase + 0, 220, 0, 0x1ULL }, // Inst #1497 = DROTR |
5987 | | { 1496, 4, 1, 4, 1642, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1496 = DPS_W_PH_MMR2 |
5988 | | { 1495, 4, 1, 4, 1478, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1495 = DPS_W_PH |
5989 | | { 1494, 4, 1, 4, 1645, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1494 = DPSX_W_PH_MMR2 |
5990 | | { 1493, 4, 1, 4, 1481, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1493 = DPSX_W_PH |
5991 | | { 1492, 4, 1, 4, 1535, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1492 = DPSU_H_QBR_MM |
5992 | | { 1491, 4, 1, 4, 1384, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1491 = DPSU_H_QBR |
5993 | | { 1490, 4, 1, 4, 1534, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1490 = DPSU_H_QBL_MM |
5994 | | { 1489, 4, 1, 4, 1383, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1489 = DPSU_H_QBL |
5995 | | { 1488, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1488 = DPSUB_U_W |
5996 | | { 1487, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1487 = DPSUB_U_H |
5997 | | { 1486, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1486 = DPSUB_U_D |
5998 | | { 1485, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 735, 0, 0x6ULL }, // Inst #1485 = DPSUB_S_W |
5999 | | { 1484, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 731, 0, 0x6ULL }, // Inst #1484 = DPSUB_S_H |
6000 | | { 1483, 4, 1, 4, 666, 0, 0, MipsImpOpBase + 0, 727, 0, 0x6ULL }, // Inst #1483 = DPSUB_S_D |
6001 | | { 1482, 4, 1, 4, 1533, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1482 = DPSQ_S_W_PH_MM |
6002 | | { 1481, 4, 1, 4, 1382, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1481 = DPSQ_S_W_PH |
6003 | | { 1480, 4, 1, 4, 1532, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1480 = DPSQ_SA_L_W_MM |
6004 | | { 1479, 4, 1, 4, 1381, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1479 = DPSQ_SA_L_W |
6005 | | { 1478, 4, 1, 4, 1643, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1478 = DPSQX_S_W_PH_MMR2 |
6006 | | { 1477, 4, 1, 4, 1479, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1477 = DPSQX_S_W_PH |
6007 | | { 1476, 4, 1, 4, 1644, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1476 = DPSQX_SA_W_PH_MMR2 |
6008 | | { 1475, 4, 1, 4, 1480, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1475 = DPSQX_SA_W_PH |
6009 | | { 1474, 2, 1, 4, 1203, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #1474 = DPOP |
6010 | | { 1473, 4, 1, 4, 1638, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1473 = DPA_W_PH_MMR2 |
6011 | | { 1472, 4, 1, 4, 1474, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1472 = DPA_W_PH |
6012 | | { 1471, 4, 1, 4, 1641, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1471 = DPAX_W_PH_MMR2 |
6013 | | { 1470, 4, 1, 4, 1477, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1470 = DPAX_W_PH |
6014 | | { 1469, 4, 1, 4, 1531, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1469 = DPAU_H_QBR_MM |
6015 | | { 1468, 4, 1, 4, 1380, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1468 = DPAU_H_QBR |
6016 | | { 1467, 4, 1, 4, 1530, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1467 = DPAU_H_QBL_MM |
6017 | | { 1466, 4, 1, 4, 1379, 0, 0, MipsImpOpBase + 0, 739, 0, 0x6ULL }, // Inst #1466 = DPAU_H_QBL |
6018 | | { 1465, 4, 1, 4, 1529, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1465 = DPAQ_S_W_PH_MM |
6019 | | { 1464, 4, 1, 4, 1378, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1464 = DPAQ_S_W_PH |
6020 | | { 1463, 4, 1, 4, 1528, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1463 = DPAQ_SA_L_W_MM |
6021 | | { 1462, 4, 1, 4, 1377, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1462 = DPAQ_SA_L_W |
6022 | | { 1461, 4, 1, 4, 1640, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1461 = DPAQX_S_W_PH_MMR2 |
6023 | | { 1460, 4, 1, 4, 1476, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1460 = DPAQX_S_W_PH |
6024 | | { 1459, 4, 1, 4, 1639, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1459 = DPAQX_SA_W_PH_MMR2 |
6025 | | { 1458, 4, 1, 4, 1475, 0, 1, MipsImpOpBase + 22, 739, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1458 = DPAQX_SA_W_PH |
6026 | | { 1457, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 735, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1457 = DPADD_U_W |
6027 | | { 1456, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1456 = DPADD_U_H |
6028 | | { 1455, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1455 = DPADD_U_D |
6029 | | { 1454, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 735, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1454 = DPADD_S_W |
6030 | | { 1453, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 731, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1453 = DPADD_S_H |
6031 | | { 1452, 4, 1, 4, 665, 0, 0, MipsImpOpBase + 0, 727, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1452 = DPADD_S_D |
6032 | | { 1451, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 724, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1451 = DOTP_U_W |
6033 | | { 1450, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 721, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1450 = DOTP_U_H |
6034 | | { 1449, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 718, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1449 = DOTP_U_D |
6035 | | { 1448, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 724, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1448 = DOTP_S_W |
6036 | | { 1447, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 721, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1447 = DOTP_S_H |
6037 | | { 1446, 3, 1, 4, 667, 0, 0, MipsImpOpBase + 0, 718, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1446 = DOTP_S_D |
6038 | | { 1445, 3, 1, 4, 914, 0, 0, MipsImpOpBase + 0, 223, 0, 0x6ULL }, // Inst #1445 = DMUL_R6 |
6039 | | { 1444, 3, 1, 4, 901, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1444 = DMULU |
6040 | | { 1443, 2, 0, 4, 903, 0, 2, MipsImpOpBase + 20, 377, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1443 = DMULTu |
6041 | | { 1442, 2, 0, 4, 902, 0, 2, MipsImpOpBase + 20, 377, 0|(1ULL<<MCID::Commutable), 0x1ULL }, // Inst #1442 = DMULT |
6042 | | { 1441, 3, 1, 4, 1209, 0, 5, MipsImpOpBase + 15, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1441 = DMUL |
6043 | | { 1440, 3, 1, 4, 913, 0, 0, MipsImpOpBase + 0, 223, 0, 0x6ULL }, // Inst #1440 = DMUHU |
6044 | | { 1439, 3, 1, 4, 912, 0, 0, MipsImpOpBase + 0, 223, 0, 0x6ULL }, // Inst #1439 = DMUH |
6045 | | { 1438, 3, 1, 4, 1068, 0, 0, MipsImpOpBase + 0, 712, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1438 = DMTGC0 |
6046 | | { 1437, 2, 2, 4, 1202, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1437 = DMTC2_OCTEON |
6047 | | { 1436, 3, 1, 4, 1056, 0, 0, MipsImpOpBase + 0, 715, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1436 = DMTC2 |
6048 | | { 1435, 2, 1, 4, 1341, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1435 = DMTC1 |
6049 | | { 1434, 3, 1, 4, 1054, 0, 0, MipsImpOpBase + 0, 712, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1434 = DMTC0 |
6050 | | { 1433, 1, 1, 4, 1059, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1433 = DMT |
6051 | | { 1432, 3, 1, 4, 918, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1432 = DMODU |
6052 | | { 1431, 3, 1, 4, 916, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1431 = DMOD |
6053 | | { 1430, 3, 1, 4, 1067, 0, 0, MipsImpOpBase + 0, 704, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1430 = DMFGC0 |
6054 | | { 1429, 2, 2, 4, 1201, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1429 = DMFC2_OCTEON |
6055 | | { 1428, 3, 1, 4, 1055, 0, 0, MipsImpOpBase + 0, 709, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1428 = DMFC2 |
6056 | | { 1427, 2, 1, 4, 1340, 0, 0, MipsImpOpBase + 0, 707, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL }, // Inst #1427 = DMFC1 |
6057 | | { 1426, 3, 1, 4, 1053, 0, 0, MipsImpOpBase + 0, 704, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1426 = DMFC0 |
6058 | | { 1425, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1425 = DLSA_R6 |
6059 | | { 1424, 4, 1, 4, 851, 0, 0, MipsImpOpBase + 0, 695, 0, 0x6ULL }, // Inst #1424 = DLSA |
6060 | | { 1423, 1, 1, 4, 1048, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1423 = DI_MMR6 |
6061 | | { 1422, 1, 1, 4, 1031, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1422 = DI_MM |
6062 | | { 1421, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1421 = DIV_U_W |
6063 | | { 1420, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1420 = DIV_U_H |
6064 | | { 1419, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1419 = DIV_U_D |
6065 | | { 1418, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1418 = DIV_U_B |
6066 | | { 1417, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1417 = DIV_S_W |
6067 | | { 1416, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1416 = DIV_S_H |
6068 | | { 1415, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1415 = DIV_S_D |
6069 | | { 1414, 3, 1, 4, 614, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1414 = DIV_S_B |
6070 | | { 1413, 3, 1, 4, 899, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1413 = DIV_MMR6 |
6071 | | { 1412, 3, 1, 4, 898, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1412 = DIVU_MMR6 |
6072 | | { 1411, 3, 1, 4, 485, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1411 = DIVU |
6073 | | { 1410, 3, 1, 4, 484, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1410 = DIV |
6074 | | { 1409, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 699, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1409 = DINSU |
6075 | | { 1408, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 699, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1408 = DINSM |
6076 | | { 1407, 5, 1, 4, 823, 0, 0, MipsImpOpBase + 0, 699, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1407 = DINS |
6077 | | { 1406, 1, 1, 4, 476, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1406 = DI |
6078 | | { 1405, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1405 = DEXTU |
6079 | | { 1404, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1404 = DEXTM |
6080 | | { 1403, 4, 1, 4, 807, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1403 = DEXT64_32 |
6081 | | { 1402, 4, 1, 4, 822, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1402 = DEXT |
6082 | | { 1401, 0, 0, 4, 988, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1401 = DERET_MMR6 |
6083 | | { 1400, 0, 0, 4, 952, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1400 = DERET_MM |
6084 | | { 1399, 0, 0, 4, 380, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1399 = DERET |
6085 | | { 1398, 3, 1, 4, 917, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1398 = DDIVU |
6086 | | { 1397, 3, 1, 4, 915, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::UsesCustomInserter), 0x6ULL }, // Inst #1397 = DDIV |
6087 | | { 1396, 2, 1, 4, 849, 0, 0, MipsImpOpBase + 0, 377, 0, 0x6ULL }, // Inst #1396 = DCLZ_R6 |
6088 | | { 1395, 2, 1, 4, 821, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #1395 = DCLZ |
6089 | | { 1394, 2, 1, 4, 848, 0, 0, MipsImpOpBase + 0, 377, 0, 0x6ULL }, // Inst #1394 = DCLO_R6 |
6090 | | { 1393, 2, 1, 4, 820, 0, 0, MipsImpOpBase + 0, 377, 0, 0x1ULL }, // Inst #1393 = DCLO |
6091 | | { 1392, 2, 1, 4, 850, 0, 0, MipsImpOpBase + 0, 377, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1392 = DBITSWAP |
6092 | | { 1391, 3, 1, 4, 847, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1391 = DAUI |
6093 | | { 1390, 3, 1, 4, 846, 0, 0, MipsImpOpBase + 0, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1390 = DATI |
6094 | | { 1389, 4, 1, 4, 844, 0, 0, MipsImpOpBase + 0, 695, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1389 = DALIGN |
6095 | | { 1388, 3, 1, 4, 845, 0, 0, MipsImpOpBase + 0, 692, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1388 = DAHI |
6096 | | { 1387, 3, 1, 4, 819, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #1387 = DADDu |
6097 | | { 1386, 3, 1, 4, 818, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #1386 = DADDiu |
6098 | | { 1385, 3, 1, 4, 817, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1385 = DADDi |
6099 | | { 1384, 3, 1, 4, 816, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #1384 = DADD |
6100 | | { 1383, 2, 0, 4, 735, 0, 1, MipsImpOpBase + 9, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1383 = CmpiRxImmX16 |
6101 | | { 1382, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1382 = CmpiRxImm16 |
6102 | | { 1381, 2, 0, 2, 735, 0, 1, MipsImpOpBase + 9, 394, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1381 = CmpRxRy16 |
6103 | | { 1380, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1380 = C_UN_S_MM |
6104 | | { 1379, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1379 = C_UN_S |
6105 | | { 1378, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1378 = C_UN_D64_MM |
6106 | | { 1377, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1377 = C_UN_D64 |
6107 | | { 1376, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1376 = C_UN_D32_MM |
6108 | | { 1375, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1375 = C_UN_D32 |
6109 | | { 1374, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1374 = C_ULT_S_MM |
6110 | | { 1373, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1373 = C_ULT_S |
6111 | | { 1372, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1372 = C_ULT_D64_MM |
6112 | | { 1371, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1371 = C_ULT_D64 |
6113 | | { 1370, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1370 = C_ULT_D32_MM |
6114 | | { 1369, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1369 = C_ULT_D32 |
6115 | | { 1368, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1368 = C_ULE_S_MM |
6116 | | { 1367, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1367 = C_ULE_S |
6117 | | { 1366, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1366 = C_ULE_D64_MM |
6118 | | { 1365, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1365 = C_ULE_D64 |
6119 | | { 1364, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1364 = C_ULE_D32_MM |
6120 | | { 1363, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1363 = C_ULE_D32 |
6121 | | { 1362, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1362 = C_UEQ_S_MM |
6122 | | { 1361, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1361 = C_UEQ_S |
6123 | | { 1360, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1360 = C_UEQ_D64_MM |
6124 | | { 1359, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1359 = C_UEQ_D64 |
6125 | | { 1358, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1358 = C_UEQ_D32_MM |
6126 | | { 1357, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1357 = C_UEQ_D32 |
6127 | | { 1356, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1356 = C_SF_S_MM |
6128 | | { 1355, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1355 = C_SF_S |
6129 | | { 1354, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1354 = C_SF_D64_MM |
6130 | | { 1353, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1353 = C_SF_D64 |
6131 | | { 1352, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1352 = C_SF_D32_MM |
6132 | | { 1351, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1351 = C_SF_D32 |
6133 | | { 1350, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1350 = C_SEQ_S_MM |
6134 | | { 1349, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1349 = C_SEQ_S |
6135 | | { 1348, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1348 = C_SEQ_D64_MM |
6136 | | { 1347, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1347 = C_SEQ_D64 |
6137 | | { 1346, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1346 = C_SEQ_D32_MM |
6138 | | { 1345, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1345 = C_SEQ_D32 |
6139 | | { 1344, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1344 = C_OLT_S_MM |
6140 | | { 1343, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1343 = C_OLT_S |
6141 | | { 1342, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1342 = C_OLT_D64_MM |
6142 | | { 1341, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1341 = C_OLT_D64 |
6143 | | { 1340, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1340 = C_OLT_D32_MM |
6144 | | { 1339, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1339 = C_OLT_D32 |
6145 | | { 1338, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1338 = C_OLE_S_MM |
6146 | | { 1337, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1337 = C_OLE_S |
6147 | | { 1336, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1336 = C_OLE_D64_MM |
6148 | | { 1335, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1335 = C_OLE_D64 |
6149 | | { 1334, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1334 = C_OLE_D32_MM |
6150 | | { 1333, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1333 = C_OLE_D32 |
6151 | | { 1332, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1332 = C_NGT_S_MM |
6152 | | { 1331, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1331 = C_NGT_S |
6153 | | { 1330, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1330 = C_NGT_D64_MM |
6154 | | { 1329, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1329 = C_NGT_D64 |
6155 | | { 1328, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1328 = C_NGT_D32_MM |
6156 | | { 1327, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1327 = C_NGT_D32 |
6157 | | { 1326, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1326 = C_NGL_S_MM |
6158 | | { 1325, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1325 = C_NGL_S |
6159 | | { 1324, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1324 = C_NGL_D64_MM |
6160 | | { 1323, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1323 = C_NGL_D64 |
6161 | | { 1322, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1322 = C_NGL_D32_MM |
6162 | | { 1321, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1321 = C_NGL_D32 |
6163 | | { 1320, 3, 1, 4, 1264, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1320 = C_NGLE_S_MM |
6164 | | { 1319, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1319 = C_NGLE_S |
6165 | | { 1318, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1318 = C_NGLE_D64_MM |
6166 | | { 1317, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1317 = C_NGLE_D64 |
6167 | | { 1316, 3, 1, 4, 1263, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1316 = C_NGLE_D32_MM |
6168 | | { 1315, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1315 = C_NGLE_D32 |
6169 | | { 1314, 3, 1, 4, 1262, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1314 = C_NGE_S_MM |
6170 | | { 1313, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1313 = C_NGE_S |
6171 | | { 1312, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1312 = C_NGE_D64_MM |
6172 | | { 1311, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1311 = C_NGE_D64 |
6173 | | { 1310, 3, 1, 4, 1261, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1310 = C_NGE_D32_MM |
6174 | | { 1309, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1309 = C_NGE_D32 |
6175 | | { 1308, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1308 = C_LT_S_MM |
6176 | | { 1307, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1307 = C_LT_S |
6177 | | { 1306, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1306 = C_LT_D64_MM |
6178 | | { 1305, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1305 = C_LT_D64 |
6179 | | { 1304, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1304 = C_LT_D32_MM |
6180 | | { 1303, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1303 = C_LT_D32 |
6181 | | { 1302, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1302 = C_LE_S_MM |
6182 | | { 1301, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1301 = C_LE_S |
6183 | | { 1300, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1300 = C_LE_D64_MM |
6184 | | { 1299, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1299 = C_LE_D64 |
6185 | | { 1298, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1298 = C_LE_D32_MM |
6186 | | { 1297, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1297 = C_LE_D32 |
6187 | | { 1296, 3, 1, 4, 1258, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1296 = C_F_S_MM |
6188 | | { 1295, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1295 = C_F_S |
6189 | | { 1294, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1294 = C_F_D64_MM |
6190 | | { 1293, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1293 = C_F_D64 |
6191 | | { 1292, 3, 1, 4, 1257, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1292 = C_F_D32_MM |
6192 | | { 1291, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1291 = C_F_D32 |
6193 | | { 1290, 3, 1, 4, 1260, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1290 = C_EQ_S_MM |
6194 | | { 1289, 3, 1, 4, 641, 0, 0, MipsImpOpBase + 0, 689, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1289 = C_EQ_S |
6195 | | { 1288, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1288 = C_EQ_D64_MM |
6196 | | { 1287, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 686, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1287 = C_EQ_D64 |
6197 | | { 1286, 3, 1, 4, 1259, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1286 = C_EQ_D32_MM |
6198 | | { 1285, 3, 1, 4, 640, 0, 0, MipsImpOpBase + 0, 683, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x44ULL }, // Inst #1285 = C_EQ_D32 |
6199 | | { 1284, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1284 = CVT_W_S_MMR6 |
6200 | | { 1283, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1283 = CVT_W_S_MM |
6201 | | { 1282, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1282 = CVT_W_S |
6202 | | { 1281, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1281 = CVT_W_D64_MM |
6203 | | { 1280, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1280 = CVT_W_D64 |
6204 | | { 1279, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1279 = CVT_W_D32_MM |
6205 | | { 1278, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1278 = CVT_W_D32 |
6206 | | { 1277, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1277 = CVT_S_W_MMR6 |
6207 | | { 1276, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1276 = CVT_S_W_MM |
6208 | | { 1275, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1275 = CVT_S_W |
6209 | | { 1274, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1274 = CVT_S_PU64 |
6210 | | { 1273, 2, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1273 = CVT_S_PL64 |
6211 | | { 1272, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1272 = CVT_S_L_MMR6 |
6212 | | { 1271, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1271 = CVT_S_L |
6213 | | { 1270, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1270 = CVT_S_D64_MM |
6214 | | { 1269, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1269 = CVT_S_D64 |
6215 | | { 1268, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1268 = CVT_S_D32_MM |
6216 | | { 1267, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1267 = CVT_S_D32 |
6217 | | { 1266, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1266 = CVT_PW_PS64 |
6218 | | { 1265, 3, 1, 4, 639, 0, 0, MipsImpOpBase + 0, 680, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1265 = CVT_PS_S64 |
6219 | | { 1264, 2, 1, 4, 1212, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1264 = CVT_PS_PW64 |
6220 | | { 1263, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1263 = CVT_L_S_MMR6 |
6221 | | { 1262, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1262 = CVT_L_S_MM |
6222 | | { 1261, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1261 = CVT_L_S |
6223 | | { 1260, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1260 = CVT_L_D_MMR6 |
6224 | | { 1259, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1259 = CVT_L_D64_MM |
6225 | | { 1258, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1258 = CVT_L_D64 |
6226 | | { 1257, 2, 1, 4, 1307, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1257 = CVT_D_L_MMR6 |
6227 | | { 1256, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1256 = CVT_D64_W_MM |
6228 | | { 1255, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1255 = CVT_D64_W |
6229 | | { 1254, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1254 = CVT_D64_S_MM |
6230 | | { 1253, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1253 = CVT_D64_S |
6231 | | { 1252, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1252 = CVT_D64_L |
6232 | | { 1251, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 678, 0, 0x4ULL }, // Inst #1251 = CVT_D32_W_MM |
6233 | | { 1250, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 678, 0, 0x4ULL }, // Inst #1250 = CVT_D32_W |
6234 | | { 1249, 2, 1, 4, 1246, 0, 0, MipsImpOpBase + 0, 678, 0, 0x4ULL }, // Inst #1249 = CVT_D32_S_MM |
6235 | | { 1248, 2, 1, 4, 638, 0, 0, MipsImpOpBase + 0, 678, 0, 0x4ULL }, // Inst #1248 = CVT_D32_S |
6236 | | { 1247, 2, 0, 4, 529, 0, 0, MipsImpOpBase + 0, 676, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1247 = CTCMSA |
6237 | | { 1246, 2, 1, 4, 1058, 0, 0, MipsImpOpBase + 0, 674, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1246 = CTC2_MM |
6238 | | { 1245, 2, 1, 4, 1295, 0, 0, MipsImpOpBase + 0, 672, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1245 = CTC1_MM |
6239 | | { 1244, 2, 1, 4, 685, 0, 0, MipsImpOpBase + 0, 672, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1244 = CTC1 |
6240 | | { 1243, 3, 1, 4, 1192, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1243 = CRC32W |
6241 | | { 1242, 3, 1, 4, 1191, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1242 = CRC32H |
6242 | | { 1241, 3, 1, 4, 1196, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1241 = CRC32D |
6243 | | { 1240, 3, 1, 4, 1195, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1240 = CRC32CW |
6244 | | { 1239, 3, 1, 4, 1194, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1239 = CRC32CH |
6245 | | { 1238, 3, 1, 4, 1197, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1238 = CRC32CD |
6246 | | { 1237, 3, 1, 4, 1193, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1237 = CRC32CB |
6247 | | { 1236, 3, 1, 4, 1190, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1236 = CRC32B |
6248 | | { 1235, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 669, 0, 0x6ULL }, // Inst #1235 = COPY_U_W |
6249 | | { 1234, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 666, 0, 0x6ULL }, // Inst #1234 = COPY_U_H |
6250 | | { 1233, 3, 1, 4, 688, 0, 0, MipsImpOpBase + 0, 660, 0, 0x6ULL }, // Inst #1233 = COPY_U_B |
6251 | | { 1232, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 669, 0, 0x6ULL }, // Inst #1232 = COPY_S_W |
6252 | | { 1231, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 666, 0, 0x6ULL }, // Inst #1231 = COPY_S_H |
6253 | | { 1230, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 663, 0, 0x6ULL }, // Inst #1230 = COPY_S_D |
6254 | | { 1229, 3, 1, 4, 689, 0, 0, MipsImpOpBase + 0, 660, 0, 0x6ULL }, // Inst #1229 = COPY_S_B |
6255 | | { 1228, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1228 = CMP_UN_S_MMR6 |
6256 | | { 1227, 3, 1, 4, 558, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1227 = CMP_UN_S |
6257 | | { 1226, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1226 = CMP_UN_D_MMR6 |
6258 | | { 1225, 3, 1, 4, 557, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1225 = CMP_UN_D |
6259 | | { 1224, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1224 = CMP_ULT_S_MMR6 |
6260 | | { 1223, 3, 1, 4, 566, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1223 = CMP_ULT_S |
6261 | | { 1222, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1222 = CMP_ULT_D_MMR6 |
6262 | | { 1221, 3, 1, 4, 565, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1221 = CMP_ULT_D |
6263 | | { 1220, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1220 = CMP_ULE_S_MMR6 |
6264 | | { 1219, 3, 1, 4, 570, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1219 = CMP_ULE_S |
6265 | | { 1218, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1218 = CMP_ULE_D_MMR6 |
6266 | | { 1217, 3, 1, 4, 569, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1217 = CMP_ULE_D |
6267 | | { 1216, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1216 = CMP_UEQ_S_MMR6 |
6268 | | { 1215, 3, 1, 4, 560, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1215 = CMP_UEQ_S |
6269 | | { 1214, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1214 = CMP_UEQ_D_MMR6 |
6270 | | { 1213, 3, 1, 4, 559, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1213 = CMP_UEQ_D |
6271 | | { 1212, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1212 = CMP_SUN_S_MMR6 |
6272 | | { 1211, 3, 1, 4, 1688, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1211 = CMP_SUN_S |
6273 | | { 1210, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1210 = CMP_SUN_D_MMR6 |
6274 | | { 1209, 3, 1, 4, 1687, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1209 = CMP_SUN_D |
6275 | | { 1208, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1208 = CMP_SULT_S_MMR6 |
6276 | | { 1207, 3, 1, 4, 1686, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1207 = CMP_SULT_S |
6277 | | { 1206, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1206 = CMP_SULT_D_MMR6 |
6278 | | { 1205, 3, 1, 4, 1685, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1205 = CMP_SULT_D |
6279 | | { 1204, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1204 = CMP_SULE_S_MMR6 |
6280 | | { 1203, 3, 1, 4, 1684, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1203 = CMP_SULE_S |
6281 | | { 1202, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1202 = CMP_SULE_D_MMR6 |
6282 | | { 1201, 3, 1, 4, 1683, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1201 = CMP_SULE_D |
6283 | | { 1200, 3, 1, 4, 1306, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1200 = CMP_SUEQ_S_MMR6 |
6284 | | { 1199, 3, 1, 4, 1682, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1199 = CMP_SUEQ_S |
6285 | | { 1198, 3, 1, 4, 1305, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1198 = CMP_SUEQ_D_MMR6 |
6286 | | { 1197, 3, 1, 4, 1681, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1197 = CMP_SUEQ_D |
6287 | | { 1196, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1196 = CMP_SLT_S_MMR6 |
6288 | | { 1195, 3, 1, 4, 1680, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1195 = CMP_SLT_S |
6289 | | { 1194, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1194 = CMP_SLT_D_MMR6 |
6290 | | { 1193, 3, 1, 4, 1679, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1193 = CMP_SLT_D |
6291 | | { 1192, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1192 = CMP_SLE_S_MMR6 |
6292 | | { 1191, 3, 1, 4, 1678, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1191 = CMP_SLE_S |
6293 | | { 1190, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1190 = CMP_SLE_D_MMR6 |
6294 | | { 1189, 3, 1, 4, 1677, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1189 = CMP_SLE_D |
6295 | | { 1188, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1188 = CMP_SEQ_S_MMR6 |
6296 | | { 1187, 3, 1, 4, 1676, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1187 = CMP_SEQ_S |
6297 | | { 1186, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1186 = CMP_SEQ_D_MMR6 |
6298 | | { 1185, 3, 1, 4, 1675, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1185 = CMP_SEQ_D |
6299 | | { 1184, 3, 1, 4, 1304, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1184 = CMP_SAF_S_MMR6 |
6300 | | { 1183, 3, 1, 4, 1674, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1183 = CMP_SAF_S |
6301 | | { 1182, 3, 1, 4, 1303, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1182 = CMP_SAF_D_MMR6 |
6302 | | { 1181, 3, 1, 4, 1673, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1181 = CMP_SAF_D |
6303 | | { 1180, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1180 = CMP_LT_S_MMR6 |
6304 | | { 1179, 3, 1, 4, 564, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1179 = CMP_LT_S |
6305 | | { 1178, 2, 0, 4, 1527, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1178 = CMP_LT_PH_MM |
6306 | | { 1177, 2, 0, 4, 1376, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1177 = CMP_LT_PH |
6307 | | { 1176, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1176 = CMP_LT_D_MMR6 |
6308 | | { 1175, 3, 1, 4, 563, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1175 = CMP_LT_D |
6309 | | { 1174, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1174 = CMP_LE_S_MMR6 |
6310 | | { 1173, 3, 1, 4, 568, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1173 = CMP_LE_S |
6311 | | { 1172, 2, 0, 4, 1526, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1172 = CMP_LE_PH_MM |
6312 | | { 1171, 2, 0, 4, 1375, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1171 = CMP_LE_PH |
6313 | | { 1170, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1170 = CMP_LE_D_MMR6 |
6314 | | { 1169, 3, 1, 4, 567, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1169 = CMP_LE_D |
6315 | | { 1168, 3, 1, 4, 1672, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1168 = CMP_F_S |
6316 | | { 1167, 3, 1, 4, 1671, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1167 = CMP_F_D |
6317 | | { 1166, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1166 = CMP_EQ_S_MMR6 |
6318 | | { 1165, 3, 1, 4, 562, 0, 0, MipsImpOpBase + 0, 657, 0, 0x16ULL }, // Inst #1165 = CMP_EQ_S |
6319 | | { 1164, 2, 0, 4, 1525, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1164 = CMP_EQ_PH_MM |
6320 | | { 1163, 2, 0, 4, 1374, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1163 = CMP_EQ_PH |
6321 | | { 1162, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1162 = CMP_EQ_D_MMR6 |
6322 | | { 1161, 3, 1, 4, 561, 0, 0, MipsImpOpBase + 0, 654, 0, 0x16ULL }, // Inst #1161 = CMP_EQ_D |
6323 | | { 1160, 3, 1, 4, 1302, 0, 0, MipsImpOpBase + 0, 657, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1160 = CMP_AF_S_MMR6 |
6324 | | { 1159, 3, 1, 4, 1301, 0, 0, MipsImpOpBase + 0, 654, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1159 = CMP_AF_D_MMR6 |
6325 | | { 1158, 2, 0, 4, 1524, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1158 = CMPU_LT_QB_MM |
6326 | | { 1157, 2, 0, 4, 1373, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1157 = CMPU_LT_QB |
6327 | | { 1156, 2, 0, 4, 1523, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1156 = CMPU_LE_QB_MM |
6328 | | { 1155, 2, 0, 4, 1372, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1155 = CMPU_LE_QB |
6329 | | { 1154, 2, 0, 4, 1522, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1154 = CMPU_EQ_QB_MM |
6330 | | { 1153, 2, 0, 4, 1371, 0, 1, MipsImpOpBase + 14, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1153 = CMPU_EQ_QB |
6331 | | { 1152, 3, 1, 4, 1521, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1152 = CMPGU_LT_QB_MM |
6332 | | { 1151, 3, 1, 4, 1370, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1151 = CMPGU_LT_QB |
6333 | | { 1150, 3, 1, 4, 1520, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1150 = CMPGU_LE_QB_MM |
6334 | | { 1149, 3, 1, 4, 1369, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1149 = CMPGU_LE_QB |
6335 | | { 1148, 3, 1, 4, 1519, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1148 = CMPGU_EQ_QB_MM |
6336 | | { 1147, 3, 1, 4, 1368, 0, 0, MipsImpOpBase + 0, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1147 = CMPGU_EQ_QB |
6337 | | { 1146, 3, 1, 4, 1637, 0, 1, MipsImpOpBase + 14, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1146 = CMPGDU_LT_QB_MMR2 |
6338 | | { 1145, 3, 1, 4, 1473, 0, 1, MipsImpOpBase + 14, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1145 = CMPGDU_LT_QB |
6339 | | { 1144, 3, 1, 4, 1636, 0, 1, MipsImpOpBase + 14, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1144 = CMPGDU_LE_QB_MMR2 |
6340 | | { 1143, 3, 1, 4, 1472, 0, 1, MipsImpOpBase + 14, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1143 = CMPGDU_LE_QB |
6341 | | { 1142, 3, 1, 4, 1635, 0, 1, MipsImpOpBase + 14, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1142 = CMPGDU_EQ_QB_MMR2 |
6342 | | { 1141, 3, 1, 4, 1471, 0, 1, MipsImpOpBase + 14, 651, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1141 = CMPGDU_EQ_QB |
6343 | | { 1140, 2, 1, 4, 732, 0, 0, MipsImpOpBase + 0, 140, 0, 0x6ULL }, // Inst #1140 = CLZ_R6 |
6344 | | { 1139, 2, 1, 4, 786, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1139 = CLZ_MMR6 |
6345 | | { 1138, 2, 1, 4, 745, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #1138 = CLZ_MM |
6346 | | { 1137, 2, 1, 4, 475, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #1137 = CLZ |
6347 | | { 1136, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1136 = CLT_U_W |
6348 | | { 1135, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1135 = CLT_U_H |
6349 | | { 1134, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1134 = CLT_U_D |
6350 | | { 1133, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1133 = CLT_U_B |
6351 | | { 1132, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1132 = CLT_S_W |
6352 | | { 1131, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1131 = CLT_S_H |
6353 | | { 1130, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1130 = CLT_S_D |
6354 | | { 1129, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1129 = CLT_S_B |
6355 | | { 1128, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1128 = CLTI_U_W |
6356 | | { 1127, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1127 = CLTI_U_H |
6357 | | { 1126, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1126 = CLTI_U_D |
6358 | | { 1125, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1125 = CLTI_U_B |
6359 | | { 1124, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1124 = CLTI_S_W |
6360 | | { 1123, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1123 = CLTI_S_H |
6361 | | { 1122, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1122 = CLTI_S_D |
6362 | | { 1121, 3, 1, 4, 554, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1121 = CLTI_S_B |
6363 | | { 1120, 2, 1, 4, 731, 0, 0, MipsImpOpBase + 0, 140, 0, 0x6ULL }, // Inst #1120 = CLO_R6 |
6364 | | { 1119, 2, 1, 4, 785, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1119 = CLO_MMR6 |
6365 | | { 1118, 2, 1, 4, 744, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #1118 = CLO_MM |
6366 | | { 1117, 2, 1, 4, 474, 0, 0, MipsImpOpBase + 0, 140, 0, 0x1ULL }, // Inst #1117 = CLO |
6367 | | { 1116, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1116 = CLE_U_W |
6368 | | { 1115, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1115 = CLE_U_H |
6369 | | { 1114, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1114 = CLE_U_D |
6370 | | { 1113, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1113 = CLE_U_B |
6371 | | { 1112, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1112 = CLE_S_W |
6372 | | { 1111, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1111 = CLE_S_H |
6373 | | { 1110, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1110 = CLE_S_D |
6374 | | { 1109, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1109 = CLE_S_B |
6375 | | { 1108, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1108 = CLEI_U_W |
6376 | | { 1107, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1107 = CLEI_U_H |
6377 | | { 1106, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1106 = CLEI_U_D |
6378 | | { 1105, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1105 = CLEI_U_B |
6379 | | { 1104, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1104 = CLEI_S_W |
6380 | | { 1103, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1103 = CLEI_S_H |
6381 | | { 1102, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1102 = CLEI_S_D |
6382 | | { 1101, 3, 1, 4, 555, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1101 = CLEI_S_B |
6383 | | { 1100, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 631, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1100 = CLASS_S_MMR6 |
6384 | | { 1099, 2, 1, 4, 1227, 0, 0, MipsImpOpBase + 0, 631, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1099 = CLASS_S |
6385 | | { 1098, 2, 1, 4, 1314, 0, 0, MipsImpOpBase + 0, 623, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1098 = CLASS_D_MMR6 |
6386 | | { 1097, 2, 1, 4, 1228, 0, 0, MipsImpOpBase + 0, 623, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1097 = CLASS_D |
6387 | | { 1096, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 647, 0, 0x1ULL }, // Inst #1096 = CINS_i32 |
6388 | | { 1095, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 643, 0, 0x1ULL }, // Inst #1095 = CINS64_32 |
6389 | | { 1094, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1094 = CINS32 |
6390 | | { 1093, 4, 1, 4, 1200, 0, 0, MipsImpOpBase + 0, 639, 0, 0x1ULL }, // Inst #1093 = CINS |
6391 | | { 1092, 2, 1, 4, 529, 0, 0, MipsImpOpBase + 0, 637, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1092 = CFCMSA |
6392 | | { 1091, 2, 1, 4, 1057, 0, 0, MipsImpOpBase + 0, 635, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1091 = CFC2_MM |
6393 | | { 1090, 2, 1, 4, 1294, 0, 0, MipsImpOpBase + 0, 633, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1090 = CFC1_MM |
6394 | | { 1089, 2, 1, 4, 694, 0, 0, MipsImpOpBase + 0, 633, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #1089 = CFC1 |
6395 | | { 1088, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1088 = CEQ_W |
6396 | | { 1087, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1087 = CEQ_H |
6397 | | { 1086, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1086 = CEQ_D |
6398 | | { 1085, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #1085 = CEQ_B |
6399 | | { 1084, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1084 = CEQI_W |
6400 | | { 1083, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1083 = CEQI_H |
6401 | | { 1082, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1082 = CEQI_D |
6402 | | { 1081, 3, 1, 4, 556, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1081 = CEQI_B |
6403 | | { 1080, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1080 = CEIL_W_S_MMR6 |
6404 | | { 1079, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1079 = CEIL_W_S_MM |
6405 | | { 1078, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 631, 0, 0x4ULL }, // Inst #1078 = CEIL_W_S |
6406 | | { 1077, 2, 1, 4, 1247, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1077 = CEIL_W_MM |
6407 | | { 1076, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1076 = CEIL_W_D_MMR6 |
6408 | | { 1075, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 629, 0, 0x4ULL }, // Inst #1075 = CEIL_W_D64 |
6409 | | { 1074, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 627, 0, 0x4ULL }, // Inst #1074 = CEIL_W_D32 |
6410 | | { 1073, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1073 = CEIL_L_S_MMR6 |
6411 | | { 1072, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 625, 0, 0x4ULL }, // Inst #1072 = CEIL_L_S |
6412 | | { 1071, 2, 1, 4, 1311, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1071 = CEIL_L_D_MMR6 |
6413 | | { 1070, 2, 1, 4, 717, 0, 0, MipsImpOpBase + 0, 623, 0, 0x4ULL }, // Inst #1070 = CEIL_L_D64 |
6414 | | { 1069, 3, 0, 4, 1088, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1069 = CACHE_R6 |
6415 | | { 1068, 3, 0, 4, 1162, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1068 = CACHE_MMR6 |
6416 | | { 1067, 3, 0, 4, 1140, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1067 = CACHE_MM |
6417 | | { 1066, 3, 0, 4, 1107, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1066 = CACHEE_MM |
6418 | | { 1065, 3, 0, 4, 471, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1065 = CACHEE |
6419 | | { 1064, 3, 0, 4, 470, 0, 0, MipsImpOpBase + 0, 620, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1064 = CACHE |
6420 | | { 1063, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1063 = BtnezX16 |
6421 | | { 1062, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1062 = Btnez16 |
6422 | | { 1061, 1, 0, 4, 939, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1061 = BteqzX16 |
6423 | | { 1060, 1, 0, 2, 939, 1, 0, MipsImpOpBase + 9, 0, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1060 = Bteqz16 |
6424 | | { 1059, 0, 0, 2, 943, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1059 = Break16 |
6425 | | { 1058, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 618, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1058 = BnezRxImmX16 |
6426 | | { 1057, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 618, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1057 = BnezRxImm16 |
6427 | | { 1056, 1, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1056 = BimmX16 |
6428 | | { 1055, 1, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1055 = Bimm16 |
6429 | | { 1054, 2, 0, 4, 939, 0, 0, MipsImpOpBase + 0, 618, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1054 = BeqzRxImmX16 |
6430 | | { 1053, 2, 0, 2, 939, 0, 0, MipsImpOpBase + 0, 618, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #1053 = BeqzRxImm16 |
6431 | | { 1052, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 616, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1052 = BZ_W |
6432 | | { 1051, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1051 = BZ_V |
6433 | | { 1050, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 614, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1050 = BZ_H |
6434 | | { 1049, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1049 = BZ_D |
6435 | | { 1048, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1048 = BZ_B |
6436 | | { 1047, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1047 = BSET_W |
6437 | | { 1046, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1046 = BSET_H |
6438 | | { 1045, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1045 = BSET_D |
6439 | | { 1044, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1044 = BSET_B |
6440 | | { 1043, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1043 = BSETI_W |
6441 | | { 1042, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1042 = BSETI_H |
6442 | | { 1041, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1041 = BSETI_D |
6443 | | { 1040, 3, 1, 4, 520, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1040 = BSETI_B |
6444 | | { 1039, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #1039 = BSEL_V |
6445 | | { 1038, 4, 1, 4, 523, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #1038 = BSELI_B |
6446 | | { 1037, 2, 0, 4, 1007, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1037 = BREAK_MMR6 |
6447 | | { 1036, 2, 0, 4, 966, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1036 = BREAK_MM |
6448 | | { 1035, 1, 0, 2, 1007, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1035 = BREAK16_MMR6 |
6449 | | { 1034, 1, 0, 2, 966, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1034 = BREAK16_MM |
6450 | | { 1033, 2, 0, 4, 379, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1033 = BREAK |
6451 | | { 1032, 1, 0, 4, 1518, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1032 = BPOSGE32_MM |
6452 | | { 1031, 1, 0, 4, 1670, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1031 = BPOSGE32C_MMR3 |
6453 | | { 1030, 1, 0, 4, 1367, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1030 = BPOSGE32 |
6454 | | { 1029, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1029 = BOVC_MMR6 |
6455 | | { 1028, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1028 = BOVC |
6456 | | { 1027, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 616, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1027 = BNZ_W |
6457 | | { 1026, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1026 = BNZ_V |
6458 | | { 1025, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 614, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1025 = BNZ_H |
6459 | | { 1024, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 612, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1024 = BNZ_D |
6460 | | { 1023, 2, 0, 4, 528, 0, 1, MipsImpOpBase + 2, 610, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #1023 = BNZ_B |
6461 | | { 1022, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1022 = BNVC_MMR6 |
6462 | | { 1021, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1021 = BNVC |
6463 | | { 1020, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #1020 = BNE_MM |
6464 | | { 1019, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #1019 = BNEZC_MMR6 |
6465 | | { 1018, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #1018 = BNEZC_MM |
6466 | | { 1017, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1017 = BNEZC64 |
6467 | | { 1016, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 588, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1016 = BNEZC16_MMR6 |
6468 | | { 1015, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1015 = BNEZC |
6469 | | { 1014, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1014 = BNEZALC_MMR6 |
6470 | | { 1013, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1013 = BNEZALC |
6471 | | { 1012, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 588, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #1012 = BNEZ16_MM |
6472 | | { 1011, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #1011 = BNEL |
6473 | | { 1010, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #1010 = BNEG_W |
6474 | | { 1009, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #1009 = BNEG_H |
6475 | | { 1008, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #1008 = BNEG_D |
6476 | | { 1007, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #1007 = BNEG_B |
6477 | | { 1006, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #1006 = BNEGI_W |
6478 | | { 1005, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #1005 = BNEGI_H |
6479 | | { 1004, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #1004 = BNEGI_D |
6480 | | { 1003, 3, 1, 4, 522, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #1003 = BNEGI_B |
6481 | | { 1002, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #1002 = BNEC_MMR6 |
6482 | | { 1001, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1001 = BNEC64 |
6483 | | { 1000, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #1000 = BNEC |
6484 | | { 999, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #999 = BNE64 |
6485 | | { 998, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #998 = BNE |
6486 | | { 997, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #997 = BMZ_V |
6487 | | { 996, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #996 = BMZI_B |
6488 | | { 995, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #995 = BMNZ_V |
6489 | | { 994, 4, 1, 4, 524, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #994 = BMNZI_B |
6490 | | { 993, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #993 = BLTZ_MM |
6491 | | { 992, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #992 = BLTZL |
6492 | | { 991, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #991 = BLTZC_MMR6 |
6493 | | { 990, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #990 = BLTZC64 |
6494 | | { 989, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #989 = BLTZC |
6495 | | { 988, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #988 = BLTZAL_MM |
6496 | | { 987, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #987 = BLTZALS_MM |
6497 | | { 986, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #986 = BLTZALL |
6498 | | { 985, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #985 = BLTZALC_MMR6 |
6499 | | { 984, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #984 = BLTZALC |
6500 | | { 983, 2, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #983 = BLTZAL |
6501 | | { 982, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #982 = BLTZ64 |
6502 | | { 981, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #981 = BLTZ |
6503 | | { 980, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #980 = BLTUC_MMR6 |
6504 | | { 979, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #979 = BLTUC64 |
6505 | | { 978, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #978 = BLTUC |
6506 | | { 977, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #977 = BLTC_MMR6 |
6507 | | { 976, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #976 = BLTC64 |
6508 | | { 975, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #975 = BLTC |
6509 | | { 974, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #974 = BLEZ_MM |
6510 | | { 973, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #973 = BLEZL |
6511 | | { 972, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #972 = BLEZC_MMR6 |
6512 | | { 971, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #971 = BLEZC64 |
6513 | | { 970, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #970 = BLEZC |
6514 | | { 969, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #969 = BLEZALC_MMR6 |
6515 | | { 968, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #968 = BLEZALC |
6516 | | { 967, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #967 = BLEZ64 |
6517 | | { 966, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #966 = BLEZ |
6518 | | { 965, 2, 1, 4, 784, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #965 = BITSWAP_MMR6 |
6519 | | { 964, 2, 1, 4, 730, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #964 = BITSWAP |
6520 | | { 963, 2, 1, 4, 1517, 0, 0, MipsImpOpBase + 0, 140, 0, 0x6ULL }, // Inst #963 = BITREV_MM |
6521 | | { 962, 2, 1, 4, 1366, 0, 0, MipsImpOpBase + 0, 140, 0, 0x6ULL }, // Inst #962 = BITREV |
6522 | | { 961, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #961 = BINSR_W |
6523 | | { 960, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #960 = BINSR_H |
6524 | | { 959, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #959 = BINSR_D |
6525 | | { 958, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #958 = BINSR_B |
6526 | | { 957, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #957 = BINSRI_W |
6527 | | { 956, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #956 = BINSRI_H |
6528 | | { 955, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #955 = BINSRI_D |
6529 | | { 954, 4, 1, 4, 517, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #954 = BINSRI_B |
6530 | | { 953, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 190, 0, 0x6ULL }, // Inst #953 = BINSL_W |
6531 | | { 952, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 194, 0, 0x6ULL }, // Inst #952 = BINSL_H |
6532 | | { 951, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 186, 0, 0x6ULL }, // Inst #951 = BINSL_D |
6533 | | { 950, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 606, 0, 0x6ULL }, // Inst #950 = BINSL_B |
6534 | | { 949, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 602, 0, 0x6ULL }, // Inst #949 = BINSLI_W |
6535 | | { 948, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 598, 0, 0x6ULL }, // Inst #948 = BINSLI_H |
6536 | | { 947, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 594, 0, 0x6ULL }, // Inst #947 = BINSLI_D |
6537 | | { 946, 4, 1, 4, 516, 0, 0, MipsImpOpBase + 0, 590, 0, 0x6ULL }, // Inst #946 = BINSLI_B |
6538 | | { 945, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #945 = BGTZ_MM |
6539 | | { 944, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #944 = BGTZL |
6540 | | { 943, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #943 = BGTZC_MMR6 |
6541 | | { 942, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #942 = BGTZC64 |
6542 | | { 941, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #941 = BGTZC |
6543 | | { 940, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #940 = BGTZALC_MMR6 |
6544 | | { 939, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #939 = BGTZALC |
6545 | | { 938, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #938 = BGTZ64 |
6546 | | { 937, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #937 = BGTZ |
6547 | | { 936, 2, 0, 4, 949, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #936 = BGEZ_MM |
6548 | | { 935, 2, 0, 4, 378, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #935 = BGEZL |
6549 | | { 934, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #934 = BGEZC_MMR6 |
6550 | | { 933, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #933 = BGEZC64 |
6551 | | { 932, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #932 = BGEZC |
6552 | | { 931, 2, 0, 4, 958, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #931 = BGEZAL_MM |
6553 | | { 930, 2, 0, 4, 957, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #930 = BGEZALS_MM |
6554 | | { 929, 2, 0, 4, 376, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #929 = BGEZALL |
6555 | | { 928, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #928 = BGEZALC_MMR6 |
6556 | | { 927, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #927 = BGEZALC |
6557 | | { 926, 2, 0, 4, 925, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #926 = BGEZAL |
6558 | | { 925, 2, 0, 4, 1010, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #925 = BGEZ64 |
6559 | | { 924, 2, 0, 4, 921, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #924 = BGEZ |
6560 | | { 923, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #923 = BGEUC_MMR6 |
6561 | | { 922, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #922 = BGEUC64 |
6562 | | { 921, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #921 = BGEUC |
6563 | | { 920, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #920 = BGEC_MMR6 |
6564 | | { 919, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #919 = BGEC64 |
6565 | | { 918, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #918 = BGEC |
6566 | | { 917, 3, 0, 4, 951, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #917 = BEQ_MM |
6567 | | { 916, 2, 0, 4, 987, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x36ULL }, // Inst #916 = BEQZC_MMR6 |
6568 | | { 915, 2, 0, 4, 950, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #915 = BEQZC_MM |
6569 | | { 914, 2, 0, 4, 1018, 0, 1, MipsImpOpBase + 2, 347, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #914 = BEQZC64 |
6570 | | { 913, 2, 0, 2, 986, 0, 1, MipsImpOpBase + 2, 588, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #913 = BEQZC16_MMR6 |
6571 | | { 912, 2, 0, 4, 932, 0, 1, MipsImpOpBase + 2, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #912 = BEQZC |
6572 | | { 911, 2, 0, 4, 1000, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #911 = BEQZALC_MMR6 |
6573 | | { 910, 2, 0, 4, 927, 0, 1, MipsImpOpBase + 3, 345, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #910 = BEQZALC |
6574 | | { 909, 2, 0, 2, 949, 0, 1, MipsImpOpBase + 2, 588, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #909 = BEQZ16_MM |
6575 | | { 908, 3, 0, 4, 377, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #908 = BEQL |
6576 | | { 907, 3, 0, 4, 985, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #907 = BEQC_MMR6 |
6577 | | { 906, 3, 0, 4, 1017, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #906 = BEQC64 |
6578 | | { 905, 3, 0, 4, 931, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x36ULL }, // Inst #905 = BEQC |
6579 | | { 904, 3, 0, 4, 1009, 0, 1, MipsImpOpBase + 2, 339, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #904 = BEQ64 |
6580 | | { 903, 3, 0, 4, 920, 0, 1, MipsImpOpBase + 2, 182, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x12ULL }, // Inst #903 = BEQ |
6581 | | { 902, 1, 0, 4, 982, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x16ULL }, // Inst #902 = BC_MMR6 |
6582 | | { 901, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #901 = BCLR_W |
6583 | | { 900, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #900 = BCLR_H |
6584 | | { 899, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #899 = BCLR_D |
6585 | | { 898, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #898 = BCLR_B |
6586 | | { 897, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #897 = BCLRI_W |
6587 | | { 896, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #896 = BCLRI_H |
6588 | | { 895, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #895 = BCLRI_D |
6589 | | { 894, 3, 1, 4, 521, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #894 = BCLRI_B |
6590 | | { 893, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 586, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #893 = BC2NEZC_MMR6 |
6591 | | { 892, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 586, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #892 = BC2NEZ |
6592 | | { 891, 2, 0, 4, 984, 0, 1, MipsImpOpBase + 2, 586, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #891 = BC2EQZC_MMR6 |
6593 | | { 890, 2, 0, 4, 930, 0, 0, MipsImpOpBase + 0, 586, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #890 = BC2EQZ |
6594 | | { 889, 2, 0, 4, 948, 0, 1, MipsImpOpBase + 2, 584, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #889 = BC1T_MM |
6595 | | { 888, 2, 0, 4, 693, 0, 1, MipsImpOpBase + 2, 584, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #888 = BC1TL |
6596 | | { 887, 2, 0, 4, 692, 0, 1, MipsImpOpBase + 2, 584, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #887 = BC1T |
6597 | | { 886, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 582, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #886 = BC1NEZC_MMR6 |
6598 | | { 885, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 582, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #885 = BC1NEZ |
6599 | | { 884, 2, 0, 4, 947, 0, 1, MipsImpOpBase + 2, 584, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #884 = BC1F_MM |
6600 | | { 883, 2, 0, 4, 691, 0, 1, MipsImpOpBase + 2, 584, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x45ULL }, // Inst #883 = BC1FL |
6601 | | { 882, 2, 0, 4, 690, 0, 1, MipsImpOpBase + 2, 584, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x45ULL }, // Inst #882 = BC1F |
6602 | | { 881, 2, 0, 4, 983, 0, 1, MipsImpOpBase + 2, 582, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x12ULL }, // Inst #881 = BC1EQZC_MMR6 |
6603 | | { 880, 2, 0, 4, 1231, 0, 0, MipsImpOpBase + 0, 582, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #880 = BC1EQZ |
6604 | | { 879, 1, 0, 2, 982, 0, 1, MipsImpOpBase + 2, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #879 = BC16_MMR6 |
6605 | | { 878, 1, 0, 4, 929, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #878 = BC |
6606 | | { 877, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 579, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #877 = BBIT132 |
6607 | | { 876, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 579, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #876 = BBIT1 |
6608 | | { 875, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 579, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #875 = BBIT032 |
6609 | | { 874, 3, 0, 4, 1199, 0, 1, MipsImpOpBase + 2, 579, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x2ULL }, // Inst #874 = BBIT0 |
6610 | | { 873, 4, 1, 4, 1634, 0, 0, MipsImpOpBase + 0, 564, 0, 0x6ULL }, // Inst #873 = BALIGN_MMR2 |
6611 | | { 872, 4, 1, 4, 1470, 0, 0, MipsImpOpBase + 0, 564, 0, 0x6ULL }, // Inst #872 = BALIGN |
6612 | | { 871, 1, 0, 4, 999, 0, 1, MipsImpOpBase + 3, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #871 = BALC_MMR6 |
6613 | | { 870, 1, 0, 4, 926, 0, 1, MipsImpOpBase + 3, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #870 = BALC |
6614 | | { 869, 1, 0, 4, 375, 0, 1, MipsImpOpBase + 3, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL }, // Inst #869 = BAL |
6615 | | { 868, 3, 1, 4, 1198, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #868 = BADDu |
6616 | | { 867, 1, 0, 2, 945, 0, 1, MipsImpOpBase + 2, 178, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #867 = B16_MM |
6617 | | { 866, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 576, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #866 = AndRxRxRy16 |
6618 | | { 865, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 396, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #865 = AdduRxRyRz16 |
6619 | | { 864, 1, 0, 4, 735, 1, 1, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #864 = AddiuSpImmX16 |
6620 | | { 863, 1, 0, 2, 735, 1, 1, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #863 = AddiuSpImm16 |
6621 | | { 862, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 573, 0, 0x0ULL }, // Inst #862 = AddiuRxRyOffMemX16 |
6622 | | { 861, 3, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 570, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #861 = AddiuRxRxImmX16 |
6623 | | { 860, 3, 1, 2, 735, 0, 0, MipsImpOpBase + 0, 570, 0|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #860 = AddiuRxRxImm16 |
6624 | | { 859, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #859 = AddiuRxPcImmX16 |
6625 | | { 858, 2, 1, 4, 735, 0, 0, MipsImpOpBase + 0, 568, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #858 = AddiuRxImmX16 |
6626 | | { 857, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #857 = AVE_U_W |
6627 | | { 856, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #856 = AVE_U_H |
6628 | | { 855, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #855 = AVE_U_D |
6629 | | { 854, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #854 = AVE_U_B |
6630 | | { 853, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #853 = AVE_S_W |
6631 | | { 852, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #852 = AVE_S_H |
6632 | | { 851, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #851 = AVE_S_D |
6633 | | { 850, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #850 = AVE_S_B |
6634 | | { 849, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #849 = AVER_U_W |
6635 | | { 848, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #848 = AVER_U_H |
6636 | | { 847, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #847 = AVER_U_D |
6637 | | { 846, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #846 = AVER_U_B |
6638 | | { 845, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #845 = AVER_S_W |
6639 | | { 844, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #844 = AVER_S_H |
6640 | | { 843, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #843 = AVER_S_D |
6641 | | { 842, 3, 1, 4, 542, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #842 = AVER_S_B |
6642 | | { 841, 3, 1, 4, 783, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #841 = AUI_MMR6 |
6643 | | { 840, 2, 1, 4, 782, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #840 = AUIPC_MMR6 |
6644 | | { 839, 2, 1, 4, 729, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #839 = AUIPC |
6645 | | { 838, 3, 1, 4, 728, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #838 = AUI |
6646 | | { 837, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #837 = ASUB_U_W |
6647 | | { 836, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #836 = ASUB_U_H |
6648 | | { 835, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #835 = ASUB_U_D |
6649 | | { 834, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #834 = ASUB_U_B |
6650 | | { 833, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 148, 0, 0x6ULL }, // Inst #833 = ASUB_S_W |
6651 | | { 832, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 145, 0, 0x6ULL }, // Inst #832 = ASUB_S_H |
6652 | | { 831, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 142, 0, 0x6ULL }, // Inst #831 = ASUB_S_D |
6653 | | { 830, 3, 1, 4, 541, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #830 = ASUB_S_B |
6654 | | { 829, 4, 1, 4, 1633, 0, 0, MipsImpOpBase + 0, 564, 0, 0x6ULL }, // Inst #829 = APPEND_MMR2 |
6655 | | { 828, 4, 1, 4, 1469, 0, 0, MipsImpOpBase + 0, 564, 0, 0x6ULL }, // Inst #828 = APPEND |
6656 | | { 827, 3, 1, 4, 743, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #827 = ANDi_MM |
6657 | | { 826, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #826 = ANDi64 |
6658 | | { 825, 3, 1, 4, 499, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #825 = ANDi |
6659 | | { 824, 3, 1, 4, 548, 0, 0, MipsImpOpBase + 0, 539, 0, 0x6ULL }, // Inst #824 = AND_V |
6660 | | { 823, 3, 1, 4, 780, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #823 = AND_MMR6 |
6661 | | { 822, 3, 1, 4, 742, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #822 = AND_MM |
6662 | | { 821, 3, 1, 4, 781, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #821 = ANDI_MMR6 |
6663 | | { 820, 3, 1, 4, 549, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #820 = ANDI_B |
6664 | | { 819, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 527, 0, 0x0ULL }, // Inst #819 = ANDI16_MMR6 |
6665 | | { 818, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 527, 0, 0x0ULL }, // Inst #818 = ANDI16_MM |
6666 | | { 817, 3, 1, 4, 806, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #817 = AND64 |
6667 | | { 816, 3, 1, 2, 780, 0, 0, MipsImpOpBase + 0, 561, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #816 = AND16_MMR6 |
6668 | | { 815, 3, 1, 2, 742, 0, 0, MipsImpOpBase + 0, 561, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #815 = AND16_MM |
6669 | | { 814, 3, 1, 4, 364, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #814 = AND |
6670 | | { 813, 2, 1, 4, 779, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #813 = ALUIPC_MMR6 |
6671 | | { 812, 2, 1, 4, 727, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #812 = ALUIPC |
6672 | | { 811, 4, 1, 4, 778, 0, 0, MipsImpOpBase + 0, 557, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #811 = ALIGN_MMR6 |
6673 | | { 810, 4, 1, 4, 726, 0, 0, MipsImpOpBase + 0, 557, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #810 = ALIGN |
6674 | | { 809, 3, 1, 4, 739, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #809 = ADDu_MM |
6675 | | { 808, 3, 1, 4, 509, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable), 0x1ULL }, // Inst #808 = ADDu |
6676 | | { 807, 3, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #807 = ADDiu_MM |
6677 | | { 806, 3, 1, 4, 498, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x2ULL }, // Inst #806 = ADDiu |
6678 | | { 805, 3, 1, 4, 741, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #805 = ADDi_MM |
6679 | | { 804, 3, 1, 4, 497, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #804 = ADDi |
6680 | | { 803, 3, 1, 4, 777, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #803 = ADD_MMR6 |
6681 | | { 802, 3, 1, 4, 740, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #802 = ADD_MM |
6682 | | { 801, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #801 = ADD_A_W |
6683 | | { 800, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #800 = ADD_A_H |
6684 | | { 799, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #799 = ADD_A_D |
6685 | | { 798, 3, 1, 4, 538, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #798 = ADD_A_B |
6686 | | { 797, 3, 1, 4, 1516, 1, 1, MipsImpOpBase + 12, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #797 = ADDWC_MM |
6687 | | { 796, 3, 1, 4, 1365, 1, 1, MipsImpOpBase + 12, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #796 = ADDWC |
6688 | | { 795, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #795 = ADDV_W |
6689 | | { 794, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #794 = ADDV_H |
6690 | | { 793, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #793 = ADDV_D |
6691 | | { 792, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #792 = ADDV_B |
6692 | | { 791, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 554, 0, 0x6ULL }, // Inst #791 = ADDVI_W |
6693 | | { 790, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 551, 0, 0x6ULL }, // Inst #790 = ADDVI_H |
6694 | | { 789, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 548, 0, 0x6ULL }, // Inst #789 = ADDVI_D |
6695 | | { 788, 3, 1, 4, 540, 0, 0, MipsImpOpBase + 0, 545, 0, 0x6ULL }, // Inst #788 = ADDVI_B |
6696 | | { 787, 3, 1, 4, 1515, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #787 = ADDU_S_QB_MM |
6697 | | { 786, 3, 1, 4, 1364, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #786 = ADDU_S_QB |
6698 | | { 785, 3, 1, 4, 1632, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #785 = ADDU_S_PH_MMR2 |
6699 | | { 784, 3, 1, 4, 1468, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #784 = ADDU_S_PH |
6700 | | { 783, 3, 1, 4, 1514, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #783 = ADDU_QB_MM |
6701 | | { 782, 3, 1, 4, 1363, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #782 = ADDU_QB |
6702 | | { 781, 3, 1, 4, 1631, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #781 = ADDU_PH_MMR2 |
6703 | | { 780, 3, 1, 4, 1467, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #780 = ADDU_PH |
6704 | | { 779, 3, 1, 4, 776, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #779 = ADDU_MMR6 |
6705 | | { 778, 3, 1, 4, 1630, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #778 = ADDUH_R_QB_MMR2 |
6706 | | { 777, 3, 1, 4, 1466, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #777 = ADDUH_R_QB |
6707 | | { 776, 3, 1, 4, 1629, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #776 = ADDUH_QB_MMR2 |
6708 | | { 775, 3, 1, 4, 1465, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #775 = ADDUH_QB |
6709 | | { 774, 3, 1, 2, 776, 0, 0, MipsImpOpBase + 0, 542, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #774 = ADDU16_MMR6 |
6710 | | { 773, 3, 1, 2, 739, 0, 0, MipsImpOpBase + 0, 542, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #773 = ADDU16_MM |
6711 | | { 772, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #772 = ADDS_U_W |
6712 | | { 771, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #771 = ADDS_U_H |
6713 | | { 770, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #770 = ADDS_U_D |
6714 | | { 769, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #769 = ADDS_U_B |
6715 | | { 768, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #768 = ADDS_S_W |
6716 | | { 767, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #767 = ADDS_S_H |
6717 | | { 766, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #766 = ADDS_S_D |
6718 | | { 765, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #765 = ADDS_S_B |
6719 | | { 764, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #764 = ADDS_A_W |
6720 | | { 763, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #763 = ADDS_A_H |
6721 | | { 762, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #762 = ADDS_A_D |
6722 | | { 761, 3, 1, 4, 539, 0, 0, MipsImpOpBase + 0, 539, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #761 = ADDS_A_B |
6723 | | { 760, 3, 1, 4, 1513, 0, 1, MipsImpOpBase + 11, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #760 = ADDSC_MM |
6724 | | { 759, 3, 1, 4, 1362, 0, 1, MipsImpOpBase + 11, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #759 = ADDSC |
6725 | | { 758, 3, 1, 4, 1211, 0, 0, MipsImpOpBase + 0, 536, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL }, // Inst #758 = ADDR_PS64 |
6726 | | { 757, 3, 1, 4, 1512, 0, 1, MipsImpOpBase + 10, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #757 = ADDQ_S_W_MM |
6727 | | { 756, 3, 1, 4, 1361, 0, 1, MipsImpOpBase + 10, 226, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #756 = ADDQ_S_W |
6728 | | { 755, 3, 1, 4, 1511, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #755 = ADDQ_S_PH_MM |
6729 | | { 754, 3, 1, 4, 1360, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #754 = ADDQ_S_PH |
6730 | | { 753, 3, 1, 4, 1510, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #753 = ADDQ_PH_MM |
6731 | | { 752, 3, 1, 4, 1359, 0, 1, MipsImpOpBase + 10, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #752 = ADDQ_PH |
6732 | | { 751, 3, 1, 4, 1628, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #751 = ADDQH_W_MMR2 |
6733 | | { 750, 3, 1, 4, 1464, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #750 = ADDQH_W |
6734 | | { 749, 3, 1, 4, 1627, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #749 = ADDQH_R_W_MMR2 |
6735 | | { 748, 3, 1, 4, 1463, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #748 = ADDQH_R_W |
6736 | | { 747, 3, 1, 4, 1626, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #747 = ADDQH_R_PH_MMR2 |
6737 | | { 746, 3, 1, 4, 1462, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #746 = ADDQH_R_PH |
6738 | | { 745, 3, 1, 4, 1625, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #745 = ADDQH_PH_MMR2 |
6739 | | { 744, 3, 1, 4, 1461, 0, 0, MipsImpOpBase + 0, 533, 0|(1ULL<<MCID::Commutable), 0x6ULL }, // Inst #744 = ADDQH_PH |
6740 | | { 743, 3, 1, 4, 775, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Rematerializable), 0x2ULL }, // Inst #743 = ADDIU_MMR6 |
6741 | | { 742, 1, 0, 2, 738, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #742 = ADDIUSP_MM |
6742 | | { 741, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 530, 0, 0x0ULL }, // Inst #741 = ADDIUS5_MM |
6743 | | { 740, 3, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 527, 0|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #740 = ADDIUR2_MM |
6744 | | { 739, 2, 1, 2, 738, 0, 0, MipsImpOpBase + 0, 525, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #739 = ADDIUR1SP_MM |
6745 | | { 738, 2, 1, 4, 774, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #738 = ADDIUPC_MMR6 |
6746 | | { 737, 2, 1, 4, 738, 0, 0, MipsImpOpBase + 0, 525, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #737 = ADDIUPC_MM |
6747 | | { 736, 2, 1, 4, 725, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #736 = ADDIUPC |
6748 | | { 735, 3, 1, 4, 496, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL }, // Inst #735 = ADD |
6749 | | { 734, 2, 1, 4, 1509, 0, 1, MipsImpOpBase + 10, 140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #734 = ABSQ_S_W_MM |
6750 | | { 733, 2, 1, 4, 1358, 0, 1, MipsImpOpBase + 10, 140, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #733 = ABSQ_S_W |
6751 | | { 732, 2, 1, 4, 1624, 0, 1, MipsImpOpBase + 10, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #732 = ABSQ_S_QB_MMR2 |
6752 | | { 731, 2, 1, 4, 1460, 0, 1, MipsImpOpBase + 10, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #731 = ABSQ_S_QB |
6753 | | { 730, 2, 1, 4, 1508, 0, 1, MipsImpOpBase + 10, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #730 = ABSQ_S_PH_MM |
6754 | | { 729, 2, 1, 4, 1357, 0, 1, MipsImpOpBase + 10, 523, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL }, // Inst #729 = ABSQ_S_PH |
6755 | | { 728, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #728 = XOR_V_W_PSEUDO |
6756 | | { 727, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #727 = XOR_V_H_PSEUDO |
6757 | | { 726, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #726 = XOR_V_D_PSEUDO |
6758 | | { 725, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #725 = Usw |
6759 | | { 724, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #724 = Ush |
6760 | | { 723, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #723 = Ulw |
6761 | | { 722, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #722 = Ulhu |
6762 | | { 721, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #721 = Ulh |
6763 | | { 720, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #720 = URemMacro |
6764 | | { 719, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #719 = URemIMacro |
6765 | | { 718, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #718 = UDivMacro |
6766 | | { 717, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #717 = UDivIMacro |
6767 | | { 716, 3, 1, 4, 886, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #716 = UDIV_MM_Pseudo |
6768 | | { 715, 0, 0, 4, 981, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #715 = TRAP_MM |
6769 | | { 714, 0, 0, 4, 402, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Trap)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #714 = TRAP |
6770 | | { 713, 1, 0, 4, 1006, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #713 = TAILCALL_MMR6 |
6771 | | { 712, 1, 0, 4, 964, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #712 = TAILCALL_MM |
6772 | | { 711, 1, 0, 4, 1005, 0, 1, MipsImpOpBase + 2, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #711 = TAILCALLREG_MMR6 |
6773 | | { 710, 1, 0, 4, 963, 0, 1, MipsImpOpBase + 2, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #710 = TAILCALLREG_MM |
6774 | | { 709, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #709 = TAILCALLREGHB64 |
6775 | | { 708, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #708 = TAILCALLREGHB |
6776 | | { 707, 1, 0, 4, 1015, 0, 1, MipsImpOpBase + 2, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #707 = TAILCALLREG64 |
6777 | | { 706, 1, 0, 4, 385, 0, 1, MipsImpOpBase + 2, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #706 = TAILCALLREG |
6778 | | { 705, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #705 = TAILCALLR6REG |
6779 | | { 704, 1, 0, 4, 937, 0, 1, MipsImpOpBase + 2, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #704 = TAILCALLHBR6REG |
6780 | | { 703, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #703 = TAILCALLHB64R6REG |
6781 | | { 702, 1, 0, 4, 1023, 0, 1, MipsImpOpBase + 2, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #702 = TAILCALL64R6REG |
6782 | | { 701, 1, 0, 4, 384, 0, 1, MipsImpOpBase + 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #701 = TAILCALL |
6783 | | { 700, 3, 1, 2, 736, 0, 1, MipsImpOpBase + 9, 396, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #700 = SltuRxRyRz16 |
6784 | | { 699, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #699 = SltuCCRxRy16 |
6785 | | { 698, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 520, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #698 = SltiuCCRxImmX16 |
6786 | | { 697, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 520, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #697 = SltiCCRxImmX16 |
6787 | | { 696, 3, 1, 2, 736, 0, 0, MipsImpOpBase + 0, 396, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #696 = SltCCRxRy16 |
6788 | | { 695, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #695 = SelTBtneZSltu |
6789 | | { 694, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 515, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #694 = SelTBtneZSltiu |
6790 | | { 693, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 515, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #693 = SelTBtneZSlti |
6791 | | { 692, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #692 = SelTBtneZSlt |
6792 | | { 691, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 515, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #691 = SelTBtneZCmpi |
6793 | | { 690, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #690 = SelTBtneZCmp |
6794 | | { 689, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #689 = SelTBteqZSltu |
6795 | | { 688, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 515, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #688 = SelTBteqZSltiu |
6796 | | { 687, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 515, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #687 = SelTBteqZSlti |
6797 | | { 686, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #686 = SelTBteqZSlt |
6798 | | { 685, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 515, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #685 = SelTBteqZCmpi |
6799 | | { 684, 5, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 510, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #684 = SelTBteqZCmp |
6800 | | { 683, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #683 = SelBneZ |
6801 | | { 682, 4, 1, 2, 944, 0, 0, MipsImpOpBase + 0, 506, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #682 = SelBeqZ |
6802 | | { 681, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #681 = SaadAddr |
6803 | | { 680, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #680 = SaaAddr |
6804 | | { 679, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #679 = SZ_W_PSEUDO |
6805 | | { 678, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #678 = SZ_V_PSEUDO |
6806 | | { 677, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 502, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #677 = SZ_H_PSEUDO |
6807 | | { 676, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #676 = SZ_D_PSEUDO |
6808 | | { 675, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #675 = SZ_B_PSEUDO |
6809 | | { 674, 3, 0, 4, 1136, 0, 0, MipsImpOpBase + 0, 349, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #674 = SWM_MM |
6810 | | { 673, 3, 0, 4, 705, 0, 0, MipsImpOpBase + 0, 316, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #673 = ST_F16 |
6811 | | { 672, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 313, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #672 = STR_W |
6812 | | { 671, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 310, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #671 = STR_D |
6813 | | { 670, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #670 = STORE_CCOND_DSP |
6814 | | { 669, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 325, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #669 = STORE_ACC64DSP |
6815 | | { 668, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 322, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #668 = STORE_ACC64 |
6816 | | { 667, 3, 0, 4, 0, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #667 = STORE_ACC128 |
6817 | | { 666, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #666 = SRemMacro |
6818 | | { 665, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #665 = SRemIMacro |
6819 | | { 664, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 504, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #664 = SNZ_W_PSEUDO |
6820 | | { 663, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #663 = SNZ_V_PSEUDO |
6821 | | { 662, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 502, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #662 = SNZ_H_PSEUDO |
6822 | | { 661, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 500, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #661 = SNZ_D_PSEUDO |
6823 | | { 660, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 498, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #660 = SNZ_B_PSEUDO |
6824 | | { 659, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #659 = SNEMacro |
6825 | | { 658, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #658 = SNEIMacro |
6826 | | { 657, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #657 = SLTUImm64 |
6827 | | { 656, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #656 = SLTImm64 |
6828 | | { 655, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #655 = SLEUImm64 |
6829 | | { 654, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #654 = SLEUImm |
6830 | | { 653, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #653 = SLEU |
6831 | | { 652, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #652 = SLEImm64 |
6832 | | { 651, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #651 = SLEImm |
6833 | | { 650, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #650 = SLE |
6834 | | { 649, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #649 = SGTUImm64 |
6835 | | { 648, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #648 = SGTUImm |
6836 | | { 647, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #647 = SGTImm64 |
6837 | | { 646, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #646 = SGTImm |
6838 | | { 645, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #645 = SGEUImm64 |
6839 | | { 644, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #644 = SGEUImm |
6840 | | { 643, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #643 = SGEU |
6841 | | { 642, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #642 = SGEImm64 |
6842 | | { 641, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #641 = SGEImm |
6843 | | { 640, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #640 = SGE |
6844 | | { 639, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #639 = SEQMacro |
6845 | | { 638, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #638 = SEQIMacro |
6846 | | { 637, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 495, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #637 = SDivMacro |
6847 | | { 636, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #636 = SDivIMacro |
6848 | | { 635, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #635 = SDMacro |
6849 | | { 634, 3, 1, 4, 885, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #634 = SDIV_MM_Pseudo |
6850 | | { 633, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 492, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #633 = SDC1_M1 |
6851 | | { 632, 0, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x0ULL }, // Inst #632 = RetRA16 |
6852 | | { 631, 0, 0, 4, 382, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #631 = RetRA |
6853 | | { 630, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #630 = RORImm |
6854 | | { 629, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #629 = ROR |
6855 | | { 628, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #628 = ROLImm |
6856 | | { 627, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #627 = ROL |
6857 | | { 626, 3, 1, 4, 866, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #626 = PseudoUDIV |
6858 | | { 625, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 489, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #625 = PseudoTRUNC_W_S |
6859 | | { 624, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 486, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #624 = PseudoTRUNC_W_D32 |
6860 | | { 623, 3, 1, 4, 1214, 0, 0, MipsImpOpBase + 0, 483, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #623 = PseudoTRUNC_W_D |
6861 | | { 622, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 479, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #622 = PseudoSELECT_S |
6862 | | { 621, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 475, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #621 = PseudoSELECT_I64 |
6863 | | { 620, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 471, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #620 = PseudoSELECT_I |
6864 | | { 619, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 467, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #619 = PseudoSELECT_D64 |
6865 | | { 618, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 463, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #618 = PseudoSELECT_D32 |
6866 | | { 617, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #617 = PseudoSELECTFP_T_S |
6867 | | { 616, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #616 = PseudoSELECTFP_T_I64 |
6868 | | { 615, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #615 = PseudoSELECTFP_T_I |
6869 | | { 614, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #614 = PseudoSELECTFP_T_D64 |
6870 | | { 613, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #613 = PseudoSELECTFP_T_D32 |
6871 | | { 612, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 459, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #612 = PseudoSELECTFP_F_S |
6872 | | { 611, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 455, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #611 = PseudoSELECTFP_F_I64 |
6873 | | { 610, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 451, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #610 = PseudoSELECTFP_F_I |
6874 | | { 609, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 447, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #609 = PseudoSELECTFP_F_D64 |
6875 | | { 608, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 443, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #608 = PseudoSELECTFP_F_D32 |
6876 | | { 607, 3, 1, 4, 865, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #607 = PseudoSDIV |
6877 | | { 606, 1, 0, 4, 1016, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #606 = PseudoReturn64 |
6878 | | { 605, 1, 0, 4, 388, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x10ULL }, // Inst #605 = PseudoReturn |
6879 | | { 604, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 439, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #604 = PseudoPICK_QB |
6880 | | { 603, 4, 1, 4, 1459, 0, 0, MipsImpOpBase + 0, 439, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #603 = PseudoPICK_PH |
6881 | | { 602, 3, 1, 4, 862, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #602 = PseudoMULTu_MM |
6882 | | { 601, 3, 1, 4, 864, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #601 = PseudoMULTu |
6883 | | { 600, 3, 1, 4, 861, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #600 = PseudoMULT_MM |
6884 | | { 599, 3, 1, 4, 863, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #599 = PseudoMULT |
6885 | | { 598, 3, 1, 4, 868, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #598 = PseudoMTLOHI_MM |
6886 | | { 597, 3, 1, 4, 1344, 0, 0, MipsImpOpBase + 0, 436, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #597 = PseudoMTLOHI_DSP |
6887 | | { 596, 3, 1, 4, 907, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #596 = PseudoMTLOHI64 |
6888 | | { 595, 3, 1, 4, 493, 0, 0, MipsImpOpBase + 0, 433, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #595 = PseudoMTLOHI |
6889 | | { 594, 4, 1, 4, 859, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #594 = PseudoMSUB_MM |
6890 | | { 593, 4, 1, 4, 860, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #593 = PseudoMSUBU_MM |
6891 | | { 592, 4, 1, 4, 492, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #592 = PseudoMSUBU |
6892 | | { 591, 4, 1, 4, 491, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #591 = PseudoMSUB |
6893 | | { 590, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 429, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #590 = PseudoMFLO_MM |
6894 | | { 589, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 431, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #589 = PseudoMFLO64 |
6895 | | { 588, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 429, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #588 = PseudoMFLO |
6896 | | { 587, 2, 1, 4, 867, 0, 0, MipsImpOpBase + 0, 429, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #587 = PseudoMFHI_MM |
6897 | | { 586, 2, 1, 4, 906, 0, 0, MipsImpOpBase + 0, 431, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #586 = PseudoMFHI64 |
6898 | | { 585, 2, 1, 4, 478, 0, 0, MipsImpOpBase + 0, 429, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #585 = PseudoMFHI |
6899 | | { 584, 4, 1, 4, 857, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #584 = PseudoMADD_MM |
6900 | | { 583, 4, 1, 4, 858, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #583 = PseudoMADDU_MM |
6901 | | { 582, 4, 1, 4, 490, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #582 = PseudoMADDU |
6902 | | { 581, 4, 1, 4, 489, 0, 0, MipsImpOpBase + 0, 425, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #581 = PseudoMADD |
6903 | | { 580, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #580 = PseudoIndrectHazardBranchR6 |
6904 | | { 579, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #579 = PseudoIndrectHazardBranch64R6 |
6905 | | { 578, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #578 = PseudoIndirectHazardBranch64 |
6906 | | { 577, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #577 = PseudoIndirectHazardBranch |
6907 | | { 576, 1, 0, 4, 998, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #576 = PseudoIndirectBranch_MMR6 |
6908 | | { 575, 1, 0, 4, 965, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #575 = PseudoIndirectBranch_MM |
6909 | | { 574, 1, 0, 4, 936, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #574 = PseudoIndirectBranchR6 |
6910 | | { 573, 1, 0, 4, 1024, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #573 = PseudoIndirectBranch64R6 |
6911 | | { 572, 1, 0, 4, 1020, 0, 0, MipsImpOpBase + 0, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #572 = PseudoIndirectBranch64 |
6912 | | { 571, 1, 0, 4, 387, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #571 = PseudoIndirectBranch |
6913 | | { 570, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 418, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #570 = PseudoD_SELECT_I64 |
6914 | | { 569, 7, 2, 4, 1, 0, 0, MipsImpOpBase + 0, 411, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #569 = PseudoD_SELECT_I |
6915 | | { 568, 3, 1, 4, 905, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #568 = PseudoDUDIV |
6916 | | { 567, 3, 1, 4, 904, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #567 = PseudoDSDIV |
6917 | | { 566, 3, 1, 4, 903, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #566 = PseudoDMULTu |
6918 | | { 565, 3, 1, 4, 902, 0, 0, MipsImpOpBase + 0, 408, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #565 = PseudoDMULT |
6919 | | { 564, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #564 = PseudoCVT_S_W |
6920 | | { 563, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #563 = PseudoCVT_S_L |
6921 | | { 562, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 406, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #562 = PseudoCVT_D64_W |
6922 | | { 561, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 404, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #561 = PseudoCVT_D64_L |
6923 | | { 560, 2, 1, 4, 644, 0, 0, MipsImpOpBase + 0, 402, 0|(1ULL<<MCID::Pseudo), 0x4ULL }, // Inst #560 = PseudoCVT_D32_W |
6924 | | { 559, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #559 = PseudoCMP_LT_PH |
6925 | | { 558, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #558 = PseudoCMP_LE_PH |
6926 | | { 557, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #557 = PseudoCMP_EQ_PH |
6927 | | { 556, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #556 = PseudoCMPU_LT_QB |
6928 | | { 555, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #555 = PseudoCMPU_LE_QB |
6929 | | { 554, 3, 1, 4, 1458, 0, 0, MipsImpOpBase + 0, 399, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #554 = PseudoCMPU_EQ_QB |
6930 | | { 553, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #553 = OR_V_W_PSEUDO |
6931 | | { 552, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #552 = OR_V_H_PSEUDO |
6932 | | { 551, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #551 = OR_V_D_PSEUDO |
6933 | | { 550, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #550 = NOR_V_W_PSEUDO |
6934 | | { 549, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #549 = NOR_V_H_PSEUDO |
6935 | | { 548, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #548 = NOR_V_D_PSEUDO |
6936 | | { 547, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #547 = NORImm64 |
6937 | | { 546, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #546 = NORImm |
6938 | | { 545, 0, 0, 4, 373, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #545 = NOP |
6939 | | { 544, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 396, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #544 = MultuRxRyRz16 |
6940 | | { 543, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 394, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #543 = MultuRxRy16 |
6941 | | { 542, 3, 1, 2, 875, 0, 2, MipsImpOpBase + 7, 396, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #542 = MultRxRyRz16 |
6942 | | { 541, 2, 0, 2, 875, 0, 2, MipsImpOpBase + 7, 394, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #541 = MultRxRy16 |
6943 | | { 540, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #540 = MULOUMacro |
6944 | | { 539, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #539 = MULOMacro |
6945 | | { 538, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #538 = MULImmMacro |
6946 | | { 537, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #537 = MTTLO |
6947 | | { 536, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #536 = MTTHI |
6948 | | { 535, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #535 = MTTHC1 |
6949 | | { 534, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #534 = MTTGPR |
6950 | | { 533, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #533 = MTTDSP |
6951 | | { 532, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 392, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #532 = MTTC1 |
6952 | | { 531, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 389, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #531 = MTTC0 |
6953 | | { 530, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 387, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #530 = MTTACX |
6954 | | { 529, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 385, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #529 = MSA_FP_ROUND_W_PSEUDO |
6955 | | { 528, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 383, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #528 = MSA_FP_ROUND_D_PSEUDO |
6956 | | { 527, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 381, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #527 = MSA_FP_EXTEND_W_PSEUDO |
6957 | | { 526, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 379, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #526 = MSA_FP_EXTEND_D_PSEUDO |
6958 | | { 525, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 377, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #525 = MIPSeh_return64 |
6959 | | { 524, 2, 0, 4, 1, 2, 0, MipsImpOpBase + 5, 140, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #524 = MIPSeh_return32 |
6960 | | { 523, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 370, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #523 = MFTLO |
6961 | | { 522, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 370, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #522 = MFTHI |
6962 | | { 521, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #521 = MFTHC1 |
6963 | | { 520, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #520 = MFTGPR |
6964 | | { 519, 1, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #519 = MFTDSP |
6965 | | { 518, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 375, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #518 = MFTC1 |
6966 | | { 517, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 372, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #517 = MFTC0 |
6967 | | { 516, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 370, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #516 = MFTACX |
6968 | | { 515, 3, 1, 2, 737, 0, 0, MipsImpOpBase + 0, 367, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #515 = LwConstant32 |
6969 | | { 514, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #514 = LoadImmSingleGPR |
6970 | | { 513, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 365, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #513 = LoadImmSingleFGR |
6971 | | { 512, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #512 = LoadImmDoubleGPR |
6972 | | { 511, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 363, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #511 = LoadImmDoubleFGR_32 |
6973 | | { 510, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 361, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #510 = LoadImmDoubleFGR |
6974 | | { 509, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #509 = LoadImm64 |
6975 | | { 508, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 359, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #508 = LoadImm32 |
6976 | | { 507, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 356, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #507 = LoadAddrReg64 |
6977 | | { 506, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #506 = LoadAddrReg32 |
6978 | | { 505, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 354, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #505 = LoadAddrImm64 |
6979 | | { 504, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #504 = LoadAddrImm32 |
6980 | | { 503, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 349, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #503 = LWM_MM |
6981 | | { 502, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 347, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #502 = LONG_BRANCH_LUi2Op_64 |
6982 | | { 501, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 345, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #501 = LONG_BRANCH_LUi2Op |
6983 | | { 500, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 342, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #500 = LONG_BRANCH_LUi |
6984 | | { 499, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 339, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #499 = LONG_BRANCH_DADDiu2Op |
6985 | | { 498, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 335, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #498 = LONG_BRANCH_DADDiu |
6986 | | { 497, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #497 = LONG_BRANCH_ADDiu2Op |
6987 | | { 496, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 331, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #496 = LONG_BRANCH_ADDiu |
6988 | | { 495, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 328, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #495 = LOAD_CCOND_DSP |
6989 | | { 494, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 325, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #494 = LOAD_ACC64DSP |
6990 | | { 493, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 322, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #493 = LOAD_ACC64 |
6991 | | { 492, 3, 1, 4, 0, 0, 0, MipsImpOpBase + 0, 319, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL }, // Inst #492 = LOAD_ACC128 |
6992 | | { 491, 3, 1, 4, 716, 0, 0, MipsImpOpBase + 0, 316, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #491 = LD_F16 |
6993 | | { 490, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 313, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #490 = LDR_W |
6994 | | { 489, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 310, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #489 = LDR_D |
6995 | | { 488, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 307, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #488 = LDMacro |
6996 | | { 487, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #487 = JalTwoReg |
6997 | | { 486, 1, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #486 = JalOneReg |
6998 | | { 485, 1, 0, 4, 990, 0, 1, MipsImpOpBase + 3, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call), 0x10ULL }, // Inst #485 = JAL_MMR6 |
6999 | | { 484, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #484 = JALRPseudo |
7000 | | { 483, 1, 0, 4, 407, 0, 1, MipsImpOpBase + 3, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #483 = JALRHBPseudo |
7001 | | { 482, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #482 = JALRHB64Pseudo |
7002 | | { 481, 1, 0, 4, 1012, 0, 1, MipsImpOpBase + 3, 306, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::HasPostISelHook), 0x10ULL }, // Inst #481 = JALR64Pseudo |
7003 | | { 480, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 302, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #480 = INSERT_W_VIDX_PSEUDO |
7004 | | { 479, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 298, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #479 = INSERT_W_VIDX64_PSEUDO |
7005 | | { 478, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 294, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #478 = INSERT_H_VIDX_PSEUDO |
7006 | | { 477, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 290, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #477 = INSERT_H_VIDX64_PSEUDO |
7007 | | { 476, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 286, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #476 = INSERT_FW_VIDX_PSEUDO |
7008 | | { 475, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 282, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #475 = INSERT_FW_VIDX64_PSEUDO |
7009 | | { 474, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 278, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #474 = INSERT_FW_PSEUDO |
7010 | | { 473, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 274, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #473 = INSERT_FD_VIDX_PSEUDO |
7011 | | { 472, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 270, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #472 = INSERT_FD_VIDX64_PSEUDO |
7012 | | { 471, 4, 1, 4, 552, 0, 0, MipsImpOpBase + 0, 266, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #471 = INSERT_FD_PSEUDO |
7013 | | { 470, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 262, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #470 = INSERT_D_VIDX_PSEUDO |
7014 | | { 469, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 258, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #469 = INSERT_D_VIDX64_PSEUDO |
7015 | | { 468, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 254, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #468 = INSERT_B_VIDX_PSEUDO |
7016 | | { 467, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 250, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #467 = INSERT_B_VIDX64_PSEUDO |
7017 | | { 466, 4, 2, 2, 737, 0, 0, MipsImpOpBase + 0, 246, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #466 = GotPrologue16 |
7018 | | { 465, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 244, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #465 = FILL_FW_PSEUDO |
7019 | | { 464, 2, 1, 4, 551, 0, 0, MipsImpOpBase + 0, 242, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #464 = FILL_FD_PSEUDO |
7020 | | { 463, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 240, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #463 = FEXP2_W_1_PSEUDO |
7021 | | { 462, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #462 = FEXP2_D_1_PSEUDO |
7022 | | { 461, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 240, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #461 = FABS_W |
7023 | | { 460, 2, 1, 4, 588, 0, 0, MipsImpOpBase + 0, 238, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #460 = FABS_D |
7024 | | { 459, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 235, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #459 = ExtractElementF64_64 |
7025 | | { 458, 3, 1, 4, 695, 0, 0, MipsImpOpBase + 0, 232, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #458 = ExtractElementF64 |
7026 | | { 457, 0, 0, 4, 924, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #457 = ERet |
7027 | | { 456, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #456 = DURemMacro |
7028 | | { 455, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #455 = DURemIMacro |
7029 | | { 454, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #454 = DUDivMacro |
7030 | | { 453, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #453 = DUDivIMacro |
7031 | | { 452, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #452 = DSRemMacro |
7032 | | { 451, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #451 = DSRemIMacro |
7033 | | { 450, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #450 = DSDivMacro |
7034 | | { 449, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #449 = DSDivIMacro |
7035 | | { 448, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #448 = DRORImm |
7036 | | { 447, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #447 = DROR |
7037 | | { 446, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 229, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #446 = DROLImm |
7038 | | { 445, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 226, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #445 = DROL |
7039 | | { 444, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #444 = DMULOUMacro |
7040 | | { 443, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #443 = DMULOMacro |
7041 | | { 442, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 223, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #442 = DMULMacro |
7042 | | { 441, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 220, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #441 = DMULImmMacro |
7043 | | { 440, 1, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #440 = Constant32 |
7044 | | { 439, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 218, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #439 = CTTC1 |
7045 | | { 438, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 215, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #438 = COPY_FW_PSEUDO |
7046 | | { 437, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 212, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #437 = COPY_FD_PSEUDO |
7047 | | { 436, 3, 0, 2, 737, 0, 0, MipsImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #436 = CONSTPOOL_ENTRY |
7048 | | { 435, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 210, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #435 = CFTC1 |
7049 | | { 434, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 207, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #434 = BuildPairF64_64 |
7050 | | { 433, 3, 1, 4, 686, 0, 0, MipsImpOpBase + 0, 204, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #433 = BuildPairF64 |
7051 | | { 432, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #432 = BtnezT8SltuX16 |
7052 | | { 431, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #431 = BtnezT8SltiuX16 |
7053 | | { 430, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #430 = BtnezT8SltiX16 |
7054 | | { 429, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #429 = BtnezT8SltX16 |
7055 | | { 428, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #428 = BtnezT8CmpiX16 |
7056 | | { 427, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #427 = BtnezT8CmpX16 |
7057 | | { 426, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #426 = BteqzT8SltuX16 |
7058 | | { 425, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #425 = BteqzT8SltiuX16 |
7059 | | { 424, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #424 = BteqzT8SltiX16 |
7060 | | { 423, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #423 = BteqzT8SltX16 |
7061 | | { 422, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 201, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #422 = BteqzT8CmpiX16 |
7062 | | { 421, 3, 0, 2, 940, 0, 0, MipsImpOpBase + 0, 198, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #421 = BteqzT8CmpX16 |
7063 | | { 420, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #420 = BneImm |
7064 | | { 419, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #419 = BeqImm |
7065 | | { 418, 1, 0, 4, 956, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #418 = B_MM_Pseudo |
7066 | | { 417, 1, 0, 4, 997, 0, 0, MipsImpOpBase + 0, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #417 = B_MMR6_Pseudo |
7067 | | { 416, 1, 0, 4, 945, 0, 1, MipsImpOpBase + 2, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #416 = B_MM |
7068 | | { 415, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #415 = BSEL_W_PSEUDO |
7069 | | { 414, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 194, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #414 = BSEL_H_PSEUDO |
7070 | | { 413, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 190, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #413 = BSEL_FW_PSEUDO |
7071 | | { 412, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #412 = BSEL_FD_PSEUDO |
7072 | | { 411, 4, 1, 4, 525, 0, 0, MipsImpOpBase + 0, 186, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #411 = BSEL_D_PSEUDO |
7073 | | { 410, 1, 1, 4, 1, 1, 0, MipsImpOpBase + 4, 185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #410 = BPOSGE32_PSEUDO |
7074 | | { 409, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #409 = BNELImmMacro |
7075 | | { 408, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #408 = BLTULImmMacro |
7076 | | { 407, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #407 = BLTUL |
7077 | | { 406, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #406 = BLTUImmMacro |
7078 | | { 405, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #405 = BLTU |
7079 | | { 404, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #404 = BLTLImmMacro |
7080 | | { 403, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #403 = BLTL |
7081 | | { 402, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #402 = BLTImmMacro |
7082 | | { 401, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #401 = BLT |
7083 | | { 400, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #400 = BLEULImmMacro |
7084 | | { 399, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #399 = BLEUL |
7085 | | { 398, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #398 = BLEUImmMacro |
7086 | | { 397, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #397 = BLEU |
7087 | | { 396, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #396 = BLELImmMacro |
7088 | | { 395, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #395 = BLEL |
7089 | | { 394, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #394 = BLEImmMacro |
7090 | | { 393, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #393 = BLE |
7091 | | { 392, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #392 = BGTULImmMacro |
7092 | | { 391, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #391 = BGTUL |
7093 | | { 390, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #390 = BGTUImmMacro |
7094 | | { 389, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #389 = BGTU |
7095 | | { 388, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #388 = BGTLImmMacro |
7096 | | { 387, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #387 = BGTL |
7097 | | { 386, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #386 = BGTImmMacro |
7098 | | { 385, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #385 = BGT |
7099 | | { 384, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #384 = BGEULImmMacro |
7100 | | { 383, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #383 = BGEUL |
7101 | | { 382, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #382 = BGEUImmMacro |
7102 | | { 381, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #381 = BGEU |
7103 | | { 380, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #380 = BGELImmMacro |
7104 | | { 379, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #379 = BGEL |
7105 | | { 378, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #378 = BGEImmMacro |
7106 | | { 377, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 182, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #377 = BGE |
7107 | | { 376, 3, 0, 4, 1, 0, 0, MipsImpOpBase + 0, 179, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #376 = BEQLImmMacro |
7108 | | { 375, 1, 0, 4, 946, 0, 1, MipsImpOpBase + 3, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #375 = BAL_BR_MM |
7109 | | { 374, 1, 0, 4, 919, 0, 1, MipsImpOpBase + 3, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x10ULL }, // Inst #374 = BAL_BR |
7110 | | { 373, 1, 0, 4, 374, 0, 1, MipsImpOpBase + 2, 178, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL }, // Inst #373 = B |
7111 | | { 372, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #372 = ATOMIC_SWAP_I8_POSTRA |
7112 | | { 371, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #371 = ATOMIC_SWAP_I8 |
7113 | | { 370, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #370 = ATOMIC_SWAP_I64_POSTRA |
7114 | | { 369, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #369 = ATOMIC_SWAP_I64 |
7115 | | { 368, 3, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #368 = ATOMIC_SWAP_I32_POSTRA |
7116 | | { 367, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #367 = ATOMIC_SWAP_I32 |
7117 | | { 366, 6, 1, 4, 721, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #366 = ATOMIC_SWAP_I16_POSTRA |
7118 | | { 365, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #365 = ATOMIC_SWAP_I16 |
7119 | | { 364, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #364 = ATOMIC_LOAD_XOR_I8_POSTRA |
7120 | | { 363, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #363 = ATOMIC_LOAD_XOR_I8 |
7121 | | { 362, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #362 = ATOMIC_LOAD_XOR_I64_POSTRA |
7122 | | { 361, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #361 = ATOMIC_LOAD_XOR_I64 |
7123 | | { 360, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #360 = ATOMIC_LOAD_XOR_I32_POSTRA |
7124 | | { 359, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #359 = ATOMIC_LOAD_XOR_I32 |
7125 | | { 358, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #358 = ATOMIC_LOAD_XOR_I16_POSTRA |
7126 | | { 357, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #357 = ATOMIC_LOAD_XOR_I16 |
7127 | | { 356, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #356 = ATOMIC_LOAD_UMIN_I8_POSTRA |
7128 | | { 355, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #355 = ATOMIC_LOAD_UMIN_I8 |
7129 | | { 354, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #354 = ATOMIC_LOAD_UMIN_I64_POSTRA |
7130 | | { 353, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #353 = ATOMIC_LOAD_UMIN_I64 |
7131 | | { 352, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #352 = ATOMIC_LOAD_UMIN_I32_POSTRA |
7132 | | { 351, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #351 = ATOMIC_LOAD_UMIN_I32 |
7133 | | { 350, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #350 = ATOMIC_LOAD_UMIN_I16_POSTRA |
7134 | | { 349, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #349 = ATOMIC_LOAD_UMIN_I16 |
7135 | | { 348, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #348 = ATOMIC_LOAD_UMAX_I8_POSTRA |
7136 | | { 347, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #347 = ATOMIC_LOAD_UMAX_I8 |
7137 | | { 346, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #346 = ATOMIC_LOAD_UMAX_I64_POSTRA |
7138 | | { 345, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #345 = ATOMIC_LOAD_UMAX_I64 |
7139 | | { 344, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #344 = ATOMIC_LOAD_UMAX_I32_POSTRA |
7140 | | { 343, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #343 = ATOMIC_LOAD_UMAX_I32 |
7141 | | { 342, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #342 = ATOMIC_LOAD_UMAX_I16_POSTRA |
7142 | | { 341, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #341 = ATOMIC_LOAD_UMAX_I16 |
7143 | | { 340, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #340 = ATOMIC_LOAD_SUB_I8_POSTRA |
7144 | | { 339, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #339 = ATOMIC_LOAD_SUB_I8 |
7145 | | { 338, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #338 = ATOMIC_LOAD_SUB_I64_POSTRA |
7146 | | { 337, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #337 = ATOMIC_LOAD_SUB_I64 |
7147 | | { 336, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #336 = ATOMIC_LOAD_SUB_I32_POSTRA |
7148 | | { 335, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #335 = ATOMIC_LOAD_SUB_I32 |
7149 | | { 334, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #334 = ATOMIC_LOAD_SUB_I16_POSTRA |
7150 | | { 333, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #333 = ATOMIC_LOAD_SUB_I16 |
7151 | | { 332, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #332 = ATOMIC_LOAD_OR_I8_POSTRA |
7152 | | { 331, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #331 = ATOMIC_LOAD_OR_I8 |
7153 | | { 330, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #330 = ATOMIC_LOAD_OR_I64_POSTRA |
7154 | | { 329, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #329 = ATOMIC_LOAD_OR_I64 |
7155 | | { 328, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #328 = ATOMIC_LOAD_OR_I32_POSTRA |
7156 | | { 327, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #327 = ATOMIC_LOAD_OR_I32 |
7157 | | { 326, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #326 = ATOMIC_LOAD_OR_I16_POSTRA |
7158 | | { 325, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #325 = ATOMIC_LOAD_OR_I16 |
7159 | | { 324, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #324 = ATOMIC_LOAD_NAND_I8_POSTRA |
7160 | | { 323, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #323 = ATOMIC_LOAD_NAND_I8 |
7161 | | { 322, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #322 = ATOMIC_LOAD_NAND_I64_POSTRA |
7162 | | { 321, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #321 = ATOMIC_LOAD_NAND_I64 |
7163 | | { 320, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #320 = ATOMIC_LOAD_NAND_I32_POSTRA |
7164 | | { 319, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #319 = ATOMIC_LOAD_NAND_I32 |
7165 | | { 318, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #318 = ATOMIC_LOAD_NAND_I16_POSTRA |
7166 | | { 317, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #317 = ATOMIC_LOAD_NAND_I16 |
7167 | | { 316, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #316 = ATOMIC_LOAD_MIN_I8_POSTRA |
7168 | | { 315, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #315 = ATOMIC_LOAD_MIN_I8 |
7169 | | { 314, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #314 = ATOMIC_LOAD_MIN_I64_POSTRA |
7170 | | { 313, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #313 = ATOMIC_LOAD_MIN_I64 |
7171 | | { 312, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #312 = ATOMIC_LOAD_MIN_I32_POSTRA |
7172 | | { 311, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #311 = ATOMIC_LOAD_MIN_I32 |
7173 | | { 310, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #310 = ATOMIC_LOAD_MIN_I16_POSTRA |
7174 | | { 309, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #309 = ATOMIC_LOAD_MIN_I16 |
7175 | | { 308, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #308 = ATOMIC_LOAD_MAX_I8_POSTRA |
7176 | | { 307, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #307 = ATOMIC_LOAD_MAX_I8 |
7177 | | { 306, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #306 = ATOMIC_LOAD_MAX_I64_POSTRA |
7178 | | { 305, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #305 = ATOMIC_LOAD_MAX_I64 |
7179 | | { 304, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #304 = ATOMIC_LOAD_MAX_I32_POSTRA |
7180 | | { 303, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #303 = ATOMIC_LOAD_MAX_I32 |
7181 | | { 302, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #302 = ATOMIC_LOAD_MAX_I16_POSTRA |
7182 | | { 301, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #301 = ATOMIC_LOAD_MAX_I16 |
7183 | | { 300, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #300 = ATOMIC_LOAD_AND_I8_POSTRA |
7184 | | { 299, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #299 = ATOMIC_LOAD_AND_I8 |
7185 | | { 298, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #298 = ATOMIC_LOAD_AND_I64_POSTRA |
7186 | | { 297, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #297 = ATOMIC_LOAD_AND_I64 |
7187 | | { 296, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #296 = ATOMIC_LOAD_AND_I32_POSTRA |
7188 | | { 295, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #295 = ATOMIC_LOAD_AND_I32 |
7189 | | { 294, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #294 = ATOMIC_LOAD_AND_I16_POSTRA |
7190 | | { 293, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #293 = ATOMIC_LOAD_AND_I16 |
7191 | | { 292, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #292 = ATOMIC_LOAD_ADD_I8_POSTRA |
7192 | | { 291, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #291 = ATOMIC_LOAD_ADD_I8 |
7193 | | { 290, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #290 = ATOMIC_LOAD_ADD_I64_POSTRA |
7194 | | { 289, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 175, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #289 = ATOMIC_LOAD_ADD_I64 |
7195 | | { 288, 3, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #288 = ATOMIC_LOAD_ADD_I32_POSTRA |
7196 | | { 287, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #287 = ATOMIC_LOAD_ADD_I32 |
7197 | | { 286, 6, 1, 4, 723, 0, 0, MipsImpOpBase + 0, 169, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #286 = ATOMIC_LOAD_ADD_I16_POSTRA |
7198 | | { 285, 3, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 166, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #285 = ATOMIC_LOAD_ADD_I16 |
7199 | | { 284, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #284 = ATOMIC_CMP_SWAP_I8_POSTRA |
7200 | | { 283, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 151, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #283 = ATOMIC_CMP_SWAP_I8 |
7201 | | { 282, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 162, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #282 = ATOMIC_CMP_SWAP_I64_POSTRA |
7202 | | { 281, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 162, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #281 = ATOMIC_CMP_SWAP_I64 |
7203 | | { 280, 4, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 151, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #280 = ATOMIC_CMP_SWAP_I32_POSTRA |
7204 | | { 279, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 151, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #279 = ATOMIC_CMP_SWAP_I32 |
7205 | | { 278, 7, 1, 4, 722, 0, 0, MipsImpOpBase + 0, 155, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #278 = ATOMIC_CMP_SWAP_I16_POSTRA |
7206 | | { 277, 4, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 151, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL }, // Inst #277 = ATOMIC_CMP_SWAP_I16 |
7207 | | { 276, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 148, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #276 = AND_V_W_PSEUDO |
7208 | | { 275, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 145, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #275 = AND_V_H_PSEUDO |
7209 | | { 274, 3, 1, 4, 550, 0, 0, MipsImpOpBase + 0, 142, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #274 = AND_V_D_PSEUDO |
7210 | | { 273, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #273 = ADJCALLSTACKUP |
7211 | | { 272, 2, 0, 4, 1, 1, 1, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #272 = ADJCALLSTACKDOWN |
7212 | | { 271, 2, 1, 4, 1, 0, 0, MipsImpOpBase + 0, 140, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #271 = ABSMacro |
7213 | | { 270, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 136, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #270 = G_UBFX |
7214 | | { 269, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 136, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #269 = G_SBFX |
7215 | | { 268, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #268 = G_VECREDUCE_UMIN |
7216 | | { 267, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #267 = G_VECREDUCE_UMAX |
7217 | | { 266, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #266 = G_VECREDUCE_SMIN |
7218 | | { 265, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #265 = G_VECREDUCE_SMAX |
7219 | | { 264, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #264 = G_VECREDUCE_XOR |
7220 | | { 263, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #263 = G_VECREDUCE_OR |
7221 | | { 262, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #262 = G_VECREDUCE_AND |
7222 | | { 261, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #261 = G_VECREDUCE_MUL |
7223 | | { 260, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #260 = G_VECREDUCE_ADD |
7224 | | { 259, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #259 = G_VECREDUCE_FMINIMUM |
7225 | | { 258, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #258 = G_VECREDUCE_FMAXIMUM |
7226 | | { 257, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #257 = G_VECREDUCE_FMIN |
7227 | | { 256, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #256 = G_VECREDUCE_FMAX |
7228 | | { 255, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #255 = G_VECREDUCE_FMUL |
7229 | | { 254, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #254 = G_VECREDUCE_FADD |
7230 | | { 253, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 123, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #253 = G_VECREDUCE_SEQ_FMUL |
7231 | | { 252, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 123, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #252 = G_VECREDUCE_SEQ_FADD |
7232 | | { 251, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #251 = G_BZERO |
7233 | | { 250, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #250 = G_MEMSET |
7234 | | { 249, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #249 = G_MEMMOVE |
7235 | | { 248, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 123, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #248 = G_MEMCPY_INLINE |
7236 | | { 247, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 132, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #247 = G_MEMCPY |
7237 | | { 246, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 130, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #246 = G_WRITE_REGISTER |
7238 | | { 245, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #245 = G_READ_REGISTER |
7239 | | { 244, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #244 = G_STRICT_FLDEXP |
7240 | | { 243, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #243 = G_STRICT_FSQRT |
7241 | | { 242, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #242 = G_STRICT_FMA |
7242 | | { 241, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #241 = G_STRICT_FREM |
7243 | | { 240, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #240 = G_STRICT_FDIV |
7244 | | { 239, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #239 = G_STRICT_FMUL |
7245 | | { 238, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #238 = G_STRICT_FSUB |
7246 | | { 237, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #237 = G_STRICT_FADD |
7247 | | { 236, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #236 = G_STACKRESTORE |
7248 | | { 235, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #235 = G_STACKSAVE |
7249 | | { 234, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #234 = G_DYN_STACKALLOC |
7250 | | { 233, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #233 = G_JUMP_TABLE |
7251 | | { 232, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #232 = G_BLOCK_ADDR |
7252 | | { 231, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #231 = G_ADDRSPACE_CAST |
7253 | | { 230, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #230 = G_FNEARBYINT |
7254 | | { 229, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #229 = G_FRINT |
7255 | | { 228, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #228 = G_FFLOOR |
7256 | | { 227, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #227 = G_FSQRT |
7257 | | { 226, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #226 = G_FSIN |
7258 | | { 225, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #225 = G_FCOS |
7259 | | { 224, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #224 = G_FCEIL |
7260 | | { 223, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #223 = G_BITREVERSE |
7261 | | { 222, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #222 = G_BSWAP |
7262 | | { 221, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #221 = G_CTPOP |
7263 | | { 220, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #220 = G_CTLZ_ZERO_UNDEF |
7264 | | { 219, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #219 = G_CTLZ |
7265 | | { 218, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #218 = G_CTTZ_ZERO_UNDEF |
7266 | | { 217, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #217 = G_CTTZ |
7267 | | { 216, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 126, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #216 = G_SHUFFLE_VECTOR |
7268 | | { 215, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 123, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #215 = G_EXTRACT_VECTOR_ELT |
7269 | | { 214, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 119, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #214 = G_INSERT_VECTOR_ELT |
7270 | | { 213, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 116, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #213 = G_BRJT |
7271 | | { 212, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #212 = G_BR |
7272 | | { 211, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #211 = G_LLROUND |
7273 | | { 210, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #210 = G_LROUND |
7274 | | { 209, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #209 = G_ABS |
7275 | | { 208, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #208 = G_UMAX |
7276 | | { 207, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #207 = G_UMIN |
7277 | | { 206, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #206 = G_SMAX |
7278 | | { 205, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #205 = G_SMIN |
7279 | | { 204, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #204 = G_PTRMASK |
7280 | | { 203, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #203 = G_PTR_ADD |
7281 | | { 202, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #202 = G_RESET_FPMODE |
7282 | | { 201, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #201 = G_SET_FPMODE |
7283 | | { 200, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #200 = G_GET_FPMODE |
7284 | | { 199, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #199 = G_RESET_FPENV |
7285 | | { 198, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #198 = G_SET_FPENV |
7286 | | { 197, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #197 = G_GET_FPENV |
7287 | | { 196, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #196 = G_FMAXIMUM |
7288 | | { 195, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #195 = G_FMINIMUM |
7289 | | { 194, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #194 = G_FMAXNUM_IEEE |
7290 | | { 193, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #193 = G_FMINNUM_IEEE |
7291 | | { 192, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #192 = G_FMAXNUM |
7292 | | { 191, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #191 = G_FMINNUM |
7293 | | { 190, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #190 = G_FCANONICALIZE |
7294 | | { 189, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #189 = G_IS_FPCLASS |
7295 | | { 188, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #188 = G_FCOPYSIGN |
7296 | | { 187, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #187 = G_FABS |
7297 | | { 186, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #186 = G_UITOFP |
7298 | | { 185, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #185 = G_SITOFP |
7299 | | { 184, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #184 = G_FPTOUI |
7300 | | { 183, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #183 = G_FPTOSI |
7301 | | { 182, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #182 = G_FPTRUNC |
7302 | | { 181, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #181 = G_FPEXT |
7303 | | { 180, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #180 = G_FNEG |
7304 | | { 179, 3, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #179 = G_FFREXP |
7305 | | { 178, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #178 = G_FLDEXP |
7306 | | { 177, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #177 = G_FLOG10 |
7307 | | { 176, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #176 = G_FLOG2 |
7308 | | { 175, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #175 = G_FLOG |
7309 | | { 174, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #174 = G_FEXP10 |
7310 | | { 173, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #173 = G_FEXP2 |
7311 | | { 172, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #172 = G_FEXP |
7312 | | { 171, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #171 = G_FPOWI |
7313 | | { 170, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #170 = G_FPOW |
7314 | | { 169, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #169 = G_FREM |
7315 | | { 168, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #168 = G_FDIV |
7316 | | { 167, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #167 = G_FMAD |
7317 | | { 166, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #166 = G_FMA |
7318 | | { 165, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #165 = G_FMUL |
7319 | | { 164, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #164 = G_FSUB |
7320 | | { 163, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #163 = G_FADD |
7321 | | { 162, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #162 = G_UDIVFIXSAT |
7322 | | { 161, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #161 = G_SDIVFIXSAT |
7323 | | { 160, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #160 = G_UDIVFIX |
7324 | | { 159, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #159 = G_SDIVFIX |
7325 | | { 158, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #158 = G_UMULFIXSAT |
7326 | | { 157, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #157 = G_SMULFIXSAT |
7327 | | { 156, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #156 = G_UMULFIX |
7328 | | { 155, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 112, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #155 = G_SMULFIX |
7329 | | { 154, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #154 = G_SSHLSAT |
7330 | | { 153, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #153 = G_USHLSAT |
7331 | | { 152, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #152 = G_SSUBSAT |
7332 | | { 151, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #151 = G_USUBSAT |
7333 | | { 150, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #150 = G_SADDSAT |
7334 | | { 149, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #149 = G_UADDSAT |
7335 | | { 148, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #148 = G_SMULH |
7336 | | { 147, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #147 = G_UMULH |
7337 | | { 146, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #146 = G_SMULO |
7338 | | { 145, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #145 = G_UMULO |
7339 | | { 144, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 107, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #144 = G_SSUBE |
7340 | | { 143, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #143 = G_SSUBO |
7341 | | { 142, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 107, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #142 = G_SADDE |
7342 | | { 141, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #141 = G_SADDO |
7343 | | { 140, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 107, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #140 = G_USUBE |
7344 | | { 139, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #139 = G_USUBO |
7345 | | { 138, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 107, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #138 = G_UADDE |
7346 | | { 137, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #137 = G_UADDO |
7347 | | { 136, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #136 = G_SELECT |
7348 | | { 135, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #135 = G_FCMP |
7349 | | { 134, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 103, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #134 = G_ICMP |
7350 | | { 133, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #133 = G_ROTL |
7351 | | { 132, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #132 = G_ROTR |
7352 | | { 131, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #131 = G_FSHR |
7353 | | { 130, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #130 = G_FSHL |
7354 | | { 129, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #129 = G_ASHR |
7355 | | { 128, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #128 = G_LSHR |
7356 | | { 127, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #127 = G_SHL |
7357 | | { 126, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #126 = G_ZEXT |
7358 | | { 125, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #125 = G_SEXT_INREG |
7359 | | { 124, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #124 = G_SEXT |
7360 | | { 123, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #123 = G_VAARG |
7361 | | { 122, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #122 = G_VASTART |
7362 | | { 121, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #121 = G_FCONSTANT |
7363 | | { 120, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #120 = G_CONSTANT |
7364 | | { 119, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #119 = G_TRUNC |
7365 | | { 118, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #118 = G_ANYEXT |
7366 | | { 117, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS |
7367 | | { 116, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL }, // Inst #116 = G_INTRINSIC_CONVERGENT |
7368 | | { 115, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS |
7369 | | { 114, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #114 = G_INTRINSIC |
7370 | | { 113, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #113 = G_INVOKE_REGION_START |
7371 | | { 112, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #112 = G_BRINDIRECT |
7372 | | { 111, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL }, // Inst #111 = G_BRCOND |
7373 | | { 110, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #110 = G_PREFETCH |
7374 | | { 109, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #109 = G_FENCE |
7375 | | { 108, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #108 = G_ATOMICRMW_UDEC_WRAP |
7376 | | { 107, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #107 = G_ATOMICRMW_UINC_WRAP |
7377 | | { 106, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #106 = G_ATOMICRMW_FMIN |
7378 | | { 105, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #105 = G_ATOMICRMW_FMAX |
7379 | | { 104, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #104 = G_ATOMICRMW_FSUB |
7380 | | { 103, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #103 = G_ATOMICRMW_FADD |
7381 | | { 102, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #102 = G_ATOMICRMW_UMIN |
7382 | | { 101, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #101 = G_ATOMICRMW_UMAX |
7383 | | { 100, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #100 = G_ATOMICRMW_MIN |
7384 | | { 99, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #99 = G_ATOMICRMW_MAX |
7385 | | { 98, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #98 = G_ATOMICRMW_XOR |
7386 | | { 97, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #97 = G_ATOMICRMW_OR |
7387 | | { 96, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #96 = G_ATOMICRMW_NAND |
7388 | | { 95, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #95 = G_ATOMICRMW_AND |
7389 | | { 94, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #94 = G_ATOMICRMW_SUB |
7390 | | { 93, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #93 = G_ATOMICRMW_ADD |
7391 | | { 92, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #92 = G_ATOMICRMW_XCHG |
7392 | | { 91, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #91 = G_ATOMIC_CMPXCHG |
7393 | | { 90, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS |
7394 | | { 89, 5, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #89 = G_INDEXED_STORE |
7395 | | { 88, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL }, // Inst #88 = G_STORE |
7396 | | { 87, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #87 = G_INDEXED_ZEXTLOAD |
7397 | | { 86, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #86 = G_INDEXED_SEXTLOAD |
7398 | | { 85, 5, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #85 = G_INDEXED_LOAD |
7399 | | { 84, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #84 = G_ZEXTLOAD |
7400 | | { 83, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #83 = G_SEXTLOAD |
7401 | | { 82, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL }, // Inst #82 = G_LOAD |
7402 | | { 81, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #81 = G_READCYCLECOUNTER |
7403 | | { 80, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #80 = G_INTRINSIC_ROUNDEVEN |
7404 | | { 79, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #79 = G_INTRINSIC_LRINT |
7405 | | { 78, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #78 = G_INTRINSIC_ROUND |
7406 | | { 77, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #77 = G_INTRINSIC_TRUNC |
7407 | | { 76, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND |
7408 | | { 75, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #75 = G_CONSTANT_FOLD_BARRIER |
7409 | | { 74, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #74 = G_FREEZE |
7410 | | { 73, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #73 = G_BITCAST |
7411 | | { 72, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #72 = G_INTTOPTR |
7412 | | { 71, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #71 = G_PTRTOINT |
7413 | | { 70, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #70 = G_CONCAT_VECTORS |
7414 | | { 69, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #69 = G_BUILD_VECTOR_TRUNC |
7415 | | { 68, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #68 = G_BUILD_VECTOR |
7416 | | { 67, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #67 = G_MERGE_VALUES |
7417 | | { 66, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #66 = G_INSERT |
7418 | | { 65, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #65 = G_UNMERGE_VALUES |
7419 | | { 64, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #64 = G_EXTRACT |
7420 | | { 63, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #63 = G_CONSTANT_POOL |
7421 | | { 62, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #62 = G_GLOBAL_VALUE |
7422 | | { 61, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #61 = G_FRAME_INDEX |
7423 | | { 60, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #60 = G_PHI |
7424 | | { 59, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #59 = G_IMPLICIT_DEF |
7425 | | { 58, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #58 = G_XOR |
7426 | | { 57, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #57 = G_OR |
7427 | | { 56, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #56 = G_AND |
7428 | | { 55, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #55 = G_UDIVREM |
7429 | | { 54, 4, 2, 0, 0, 0, 0, MipsImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #54 = G_SDIVREM |
7430 | | { 53, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #53 = G_UREM |
7431 | | { 52, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #52 = G_SREM |
7432 | | { 51, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #51 = G_UDIV |
7433 | | { 50, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #50 = G_SDIV |
7434 | | { 49, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #49 = G_MUL |
7435 | | { 48, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #48 = G_SUB |
7436 | | { 47, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL }, // Inst #47 = G_ADD |
7437 | | { 46, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #46 = G_ASSERT_ALIGN |
7438 | | { 45, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #45 = G_ASSERT_ZEXT |
7439 | | { 44, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #44 = G_ASSERT_SEXT |
7440 | | { 43, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #43 = JUMP_TABLE_DEBUG_INFO |
7441 | | { 42, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #42 = MEMBARRIER |
7442 | | { 41, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #41 = ICALL_BRANCH_FUNNEL |
7443 | | { 40, 3, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #40 = PATCHABLE_TYPED_EVENT_CALL |
7444 | | { 39, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #39 = PATCHABLE_EVENT_CALL |
7445 | | { 38, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #38 = PATCHABLE_TAIL_CALL |
7446 | | { 37, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #37 = PATCHABLE_FUNCTION_EXIT |
7447 | | { 36, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #36 = PATCHABLE_RET |
7448 | | { 35, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #35 = PATCHABLE_FUNCTION_ENTER |
7449 | | { 34, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #34 = PATCHABLE_OP |
7450 | | { 33, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #33 = FAULTING_OP |
7451 | | { 32, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #32 = LOCAL_ESCAPE |
7452 | | { 31, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #31 = STATEPOINT |
7453 | | { 30, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #30 = PREALLOCATED_ARG |
7454 | | { 29, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #29 = PREALLOCATED_SETUP |
7455 | | { 28, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL }, // Inst #28 = LOAD_STACK_GUARD |
7456 | | { 27, 6, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #27 = PATCHPOINT |
7457 | | { 26, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #26 = FENTRY_CALL |
7458 | | { 25, 2, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #25 = STACKMAP |
7459 | | { 24, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #24 = ARITH_FENCE |
7460 | | { 23, 4, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #23 = PSEUDO_PROBE |
7461 | | { 22, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #22 = LIFETIME_END |
7462 | | { 21, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #21 = LIFETIME_START |
7463 | | { 20, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #20 = BUNDLE |
7464 | | { 19, 2, 1, 0, 514, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #19 = COPY |
7465 | | { 18, 2, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #18 = REG_SEQUENCE |
7466 | | { 17, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL }, // Inst #17 = DBG_LABEL |
7467 | | { 16, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #16 = DBG_PHI |
7468 | | { 15, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #15 = DBG_INSTR_REF |
7469 | | { 14, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #14 = DBG_VALUE_LIST |
7470 | | { 13, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #13 = DBG_VALUE |
7471 | | { 12, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #12 = COPY_TO_REGCLASS |
7472 | | { 11, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 9, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #11 = SUBREG_TO_REG |
7473 | | { 10, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL }, // Inst #10 = IMPLICIT_DEF |
7474 | | { 9, 4, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 5, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #9 = INSERT_SUBREG |
7475 | | { 8, 3, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 2, 0|(1ULL<<MCID::Pseudo), 0x0ULL }, // Inst #8 = EXTRACT_SUBREG |
7476 | | { 7, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #7 = KILL |
7477 | | { 6, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #6 = ANNOTATION_LABEL |
7478 | | { 5, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #5 = GC_LABEL |
7479 | | { 4, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #4 = EH_LABEL |
7480 | | { 3, 1, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL }, // Inst #3 = CFI_INSTRUCTION |
7481 | | { 2, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL }, // Inst #2 = INLINEASM_BR |
7482 | | { 1, 0, 0, 0, 0, 0, 0, MipsImpOpBase + 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #1 = INLINEASM |
7483 | | { 0, 1, 1, 0, 0, 0, 0, MipsImpOpBase + 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL }, // Inst #0 = PHI |
7484 | | }, { |
7485 | | /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7486 | | /* 1 */ |
7487 | | /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7488 | | /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7489 | | /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7490 | | /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7491 | | /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7492 | | /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7493 | | /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, |
7494 | | /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7495 | | /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7496 | | /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
7497 | | /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7498 | | /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7499 | | /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7500 | | /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7501 | | /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
7502 | | /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7503 | | /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7504 | | /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7505 | | /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7506 | | /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
7507 | | /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7508 | | /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
7509 | | /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7510 | | /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7511 | | /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7512 | | /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7513 | | /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7514 | | /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7515 | | /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7516 | | /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7517 | | /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7518 | | /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7519 | | /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7520 | | /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7521 | | /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7522 | | /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
7523 | | /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7524 | | /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
7525 | | /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, |
7526 | | /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7527 | | /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, |
7528 | | /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 }, |
7529 | | /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, |
7530 | | /* 140 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7531 | | /* 142 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7532 | | /* 145 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7533 | | /* 148 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7534 | | /* 151 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7535 | | /* 155 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7536 | | /* 162 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7537 | | /* 166 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7538 | | /* 169 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7539 | | /* 175 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7540 | | /* 178 */ { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7541 | | /* 179 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7542 | | /* 182 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7543 | | /* 185 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7544 | | /* 186 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7545 | | /* 190 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7546 | | /* 194 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7547 | | /* 198 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7548 | | /* 201 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7549 | | /* 204 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7550 | | /* 207 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7551 | | /* 210 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7552 | | /* 212 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7553 | | /* 215 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7554 | | /* 218 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7555 | | /* 220 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7556 | | /* 223 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7557 | | /* 226 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7558 | | /* 229 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7559 | | /* 232 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7560 | | /* 235 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7561 | | /* 238 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7562 | | /* 240 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7563 | | /* 242 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7564 | | /* 244 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7565 | | /* 246 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7566 | | /* 250 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7567 | | /* 254 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7568 | | /* 258 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7569 | | /* 262 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7570 | | /* 266 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7571 | | /* 270 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7572 | | /* 274 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7573 | | /* 278 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7574 | | /* 282 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7575 | | /* 286 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7576 | | /* 290 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7577 | | /* 294 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7578 | | /* 298 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7579 | | /* 302 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7580 | | /* 306 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7581 | | /* 307 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7582 | | /* 310 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7583 | | /* 313 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7584 | | /* 316 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7585 | | /* 319 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7586 | | /* 322 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7587 | | /* 325 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7588 | | /* 328 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7589 | | /* 331 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7590 | | /* 335 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7591 | | /* 339 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7592 | | /* 342 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7593 | | /* 345 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7594 | | /* 347 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7595 | | /* 349 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7596 | | /* 352 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7597 | | /* 354 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7598 | | /* 356 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7599 | | /* 359 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7600 | | /* 361 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7601 | | /* 363 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7602 | | /* 365 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7603 | | /* 367 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7604 | | /* 370 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7605 | | /* 372 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7606 | | /* 375 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7607 | | /* 377 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7608 | | /* 379 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7609 | | /* 381 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7610 | | /* 383 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7611 | | /* 385 */ { Mips::MSA128F16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7612 | | /* 387 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7613 | | /* 389 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7614 | | /* 392 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7615 | | /* 394 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7616 | | /* 396 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7617 | | /* 399 */ { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7618 | | /* 402 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7619 | | /* 404 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7620 | | /* 406 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7621 | | /* 408 */ { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7622 | | /* 411 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7623 | | /* 418 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7624 | | /* 425 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7625 | | /* 429 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7626 | | /* 431 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC128RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7627 | | /* 433 */ { Mips::ACC64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7628 | | /* 436 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7629 | | /* 439 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7630 | | /* 443 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7631 | | /* 447 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7632 | | /* 451 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7633 | | /* 455 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7634 | | /* 459 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7635 | | /* 463 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7636 | | /* 467 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7637 | | /* 471 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7638 | | /* 475 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7639 | | /* 479 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7640 | | /* 483 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7641 | | /* 486 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7642 | | /* 489 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7643 | | /* 492 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7644 | | /* 495 */ { Mips::GPR32NONZERORegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7645 | | /* 498 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7646 | | /* 500 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7647 | | /* 502 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7648 | | /* 504 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7649 | | /* 506 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7650 | | /* 510 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7651 | | /* 515 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7652 | | /* 520 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7653 | | /* 523 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7654 | | /* 525 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7655 | | /* 527 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7656 | | /* 530 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7657 | | /* 533 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7658 | | /* 536 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7659 | | /* 539 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7660 | | /* 542 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7661 | | /* 545 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7662 | | /* 548 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7663 | | /* 551 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7664 | | /* 554 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7665 | | /* 557 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7666 | | /* 561 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7667 | | /* 564 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7668 | | /* 568 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7669 | | /* 570 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7670 | | /* 573 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsPlusSPRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7671 | | /* 576 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7672 | | /* 579 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7673 | | /* 582 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7674 | | /* 584 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7675 | | /* 586 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7676 | | /* 588 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7677 | | /* 590 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7678 | | /* 594 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7679 | | /* 598 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7680 | | /* 602 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7681 | | /* 606 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7682 | | /* 610 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7683 | | /* 612 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7684 | | /* 614 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7685 | | /* 616 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7686 | | /* 618 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_PCREL, 0 }, |
7687 | | /* 620 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7688 | | /* 623 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7689 | | /* 625 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7690 | | /* 627 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7691 | | /* 629 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7692 | | /* 631 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7693 | | /* 633 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7694 | | /* 635 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7695 | | /* 637 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7696 | | /* 639 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7697 | | /* 643 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7698 | | /* 647 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7699 | | /* 651 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7700 | | /* 654 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7701 | | /* 657 */ { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7702 | | /* 660 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7703 | | /* 663 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7704 | | /* 666 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7705 | | /* 669 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7706 | | /* 672 */ { Mips::CCRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7707 | | /* 674 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7708 | | /* 676 */ { Mips::MSACtrlRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7709 | | /* 678 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7710 | | /* 680 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7711 | | /* 683 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7712 | | /* 686 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7713 | | /* 689 */ { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7714 | | /* 692 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7715 | | /* 695 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7716 | | /* 699 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7717 | | /* 704 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7718 | | /* 707 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7719 | | /* 709 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7720 | | /* 712 */ { Mips::COP0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7721 | | /* 715 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7722 | | /* 718 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7723 | | /* 721 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7724 | | /* 724 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7725 | | /* 727 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7726 | | /* 731 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7727 | | /* 735 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7728 | | /* 739 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7729 | | /* 743 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7730 | | /* 746 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7731 | | /* 748 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7732 | | /* 751 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7733 | | /* 754 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7734 | | /* 756 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7735 | | /* 759 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7736 | | /* 762 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7737 | | /* 765 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7738 | | /* 768 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7739 | | /* 771 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7740 | | /* 774 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7741 | | /* 777 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7742 | | /* 779 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7743 | | /* 781 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7744 | | /* 783 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7745 | | /* 785 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7746 | | /* 787 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7747 | | /* 789 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7748 | | /* 794 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7749 | | /* 798 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7750 | | /* 802 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7751 | | /* 806 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7752 | | /* 810 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7753 | | /* 813 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7754 | | /* 818 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7755 | | /* 823 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7756 | | /* 828 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7757 | | /* 833 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7758 | | /* 834 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7759 | | /* 837 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
7760 | | /* 840 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7761 | | /* 843 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7762 | | /* 846 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7763 | | /* 849 */ { Mips::COP3RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7764 | | /* 852 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7765 | | /* 854 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7766 | | /* 856 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7767 | | /* 858 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7768 | | /* 860 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7769 | | /* 864 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
7770 | | /* 867 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
7771 | | /* 870 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7772 | | /* 873 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7773 | | /* 876 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7774 | | /* 879 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7775 | | /* 882 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
7776 | | /* 885 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
7777 | | /* 888 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7778 | | /* 891 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7779 | | /* 894 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 3, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7780 | | /* 897 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7781 | | /* 901 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7782 | | /* 904 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7783 | | /* 908 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 2, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7784 | | /* 911 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, |
7785 | | /* 914 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7786 | | /* 917 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, |
7787 | | /* 920 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7788 | | /* 924 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7789 | | /* 928 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7790 | | /* 932 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7791 | | /* 936 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7792 | | /* 940 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7793 | | /* 942 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7794 | | /* 945 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7795 | | /* 947 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7796 | | /* 952 */ { Mips::GPRMM16MovePPairFirstRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePPairSecondRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16MovePRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7797 | | /* 956 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7798 | | /* 958 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7799 | | /* 962 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7800 | | /* 966 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7801 | | /* 970 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7802 | | /* 974 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FCCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7803 | | /* 978 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7804 | | /* 982 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7805 | | /* 986 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7806 | | /* 990 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7807 | | /* 994 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7808 | | /* 998 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7809 | | /* 1002 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7810 | | /* 1006 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7811 | | /* 1010 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7812 | | /* 1014 */ { Mips::COP2RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7813 | | /* 1017 */ { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::AFGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7814 | | /* 1020 */ { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7815 | | /* 1023 */ { Mips::HI32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7816 | | /* 1025 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7817 | | /* 1028 */ { Mips::LO32DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7818 | | /* 1030 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7819 | | /* 1032 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7820 | | /* 1034 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7821 | | /* 1036 */ { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPRMM16RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7822 | | /* 1038 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7823 | | /* 1040 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7824 | | /* 1043 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7825 | | /* 1047 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7826 | | /* 1050 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7827 | | /* 1053 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::HWRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7828 | | /* 1056 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7829 | | /* 1058 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7830 | | /* 1060 */ { Mips::GPRMM16ZeroRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7831 | | /* 1063 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7832 | | /* 1067 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
7833 | | /* 1071 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7834 | | /* 1075 */ { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MipsII::OPERAND_MEM_SIMM9, 0 }, { -1, 0, MipsII::OPERAND_MEM_SIMM9, 0 }, |
7835 | | /* 1079 */ { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGRCCRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::FGR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7836 | | /* 1083 */ { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { Mips::ACC64DSPRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7837 | | /* 1086 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7838 | | /* 1089 */ { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::DSPRRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7839 | | /* 1092 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7840 | | /* 1096 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7841 | | /* 1100 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7842 | | /* 1104 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7843 | | /* 1108 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7844 | | /* 1111 */ { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR64RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, |
7845 | | /* 1114 */ { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128BRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7846 | | /* 1117 */ { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128DRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7847 | | /* 1120 */ { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128HRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7848 | | /* 1123 */ { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::MSA128WRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::GPR32RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, |
7849 | | /* 1126 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_MEMORY, 0 }, { -1, 0, MCOI::OPERAND_MEMORY, 0 }, |
7850 | | /* 1128 */ { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { Mips::CPU16RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, |
7851 | | }, { |
7852 | | /* 0 */ |
7853 | | /* 0 */ Mips::SP, Mips::SP, |
7854 | | /* 2 */ Mips::AT, |
7855 | | /* 3 */ Mips::RA, |
7856 | | /* 4 */ Mips::DSPPos, |
7857 | | /* 5 */ Mips::V0, Mips::V1, |
7858 | | /* 7 */ Mips::HI0, Mips::LO0, |
7859 | | /* 9 */ Mips::T8, |
7860 | | /* 10 */ Mips::DSPOutFlag20, |
7861 | | /* 11 */ Mips::DSPCarry, |
7862 | | /* 12 */ Mips::DSPCarry, Mips::DSPOutFlag20, |
7863 | | /* 14 */ Mips::DSPCCond, |
7864 | | /* 15 */ Mips::HI0, Mips::LO0, Mips::P0, Mips::P1, Mips::P2, |
7865 | | /* 20 */ Mips::HI0_64, Mips::LO0_64, |
7866 | | /* 22 */ Mips::DSPOutFlag16_19, |
7867 | | /* 23 */ Mips::DSPPos, Mips::DSPEFI, |
7868 | | /* 25 */ Mips::DSPPos, Mips::DSPPos, Mips::DSPEFI, |
7869 | | /* 28 */ Mips::DSPOutFlag23, |
7870 | | /* 29 */ Mips::FCC0, |
7871 | | /* 30 */ Mips::DSPPos, Mips::DSPSCount, |
7872 | | /* 32 */ Mips::HI0, Mips::LO0, Mips::HI0, Mips::LO0, |
7873 | | /* 36 */ Mips::AC0, |
7874 | | /* 37 */ Mips::AC0_64, |
7875 | | /* 38 */ Mips::HI0, |
7876 | | /* 39 */ Mips::HI0_64, |
7877 | | /* 40 */ Mips::LO0, |
7878 | | /* 41 */ Mips::LO0_64, |
7879 | | /* 42 */ Mips::MPL0, Mips::P0, Mips::P1, Mips::P2, |
7880 | | /* 46 */ Mips::MPL1, Mips::P0, Mips::P1, Mips::P2, |
7881 | | /* 50 */ Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, |
7882 | | /* 54 */ Mips::P0, |
7883 | | /* 55 */ Mips::P1, |
7884 | | /* 56 */ Mips::P2, |
7885 | | /* 57 */ Mips::DSPOutFlag21, |
7886 | | /* 58 */ Mips::DSPOutFlag22, |
7887 | | /* 59 */ Mips::P0, Mips::P1, Mips::P2, |
7888 | | /* 62 */ Mips::MPL1, Mips::MPL2, Mips::P0, Mips::P1, Mips::P2, |
7889 | | } |
7890 | | }; |
7891 | | |
7892 | | |
7893 | | #ifdef __GNUC__ |
7894 | | #pragma GCC diagnostic push |
7895 | | #pragma GCC diagnostic ignored "-Woverlength-strings" |
7896 | | #endif |
7897 | | extern const char MipsInstrNameData[] = { |
7898 | | /* 0 */ "G_FLOG10\0" |
7899 | | /* 9 */ "G_FEXP10\0" |
7900 | | /* 18 */ "DMFC0\0" |
7901 | | /* 24 */ "DMFGC0\0" |
7902 | | /* 31 */ "MFHGC0\0" |
7903 | | /* 38 */ "MTHGC0\0" |
7904 | | /* 45 */ "DMTGC0\0" |
7905 | | /* 52 */ "MFTC0\0" |
7906 | | /* 58 */ "DMTC0\0" |
7907 | | /* 64 */ "MTTC0\0" |
7908 | | /* 70 */ "VMM0\0" |
7909 | | /* 75 */ "MTM0\0" |
7910 | | /* 80 */ "MTP0\0" |
7911 | | /* 85 */ "BBIT0\0" |
7912 | | /* 91 */ "LDC1\0" |
7913 | | /* 96 */ "SDC1\0" |
7914 | | /* 101 */ "CFC1\0" |
7915 | | /* 106 */ "DMFC1\0" |
7916 | | /* 112 */ "MFTHC1\0" |
7917 | | /* 119 */ "MTTHC1\0" |
7918 | | /* 126 */ "CTC1\0" |
7919 | | /* 131 */ "CFTC1\0" |
7920 | | /* 137 */ "MFTC1\0" |
7921 | | /* 143 */ "DMTC1\0" |
7922 | | /* 149 */ "CTTC1\0" |
7923 | | /* 155 */ "MTTC1\0" |
7924 | | /* 161 */ "LWC1\0" |
7925 | | /* 166 */ "SWC1\0" |
7926 | | /* 171 */ "LDXC1\0" |
7927 | | /* 177 */ "SDXC1\0" |
7928 | | /* 183 */ "LUXC1\0" |
7929 | | /* 189 */ "SUXC1\0" |
7930 | | /* 195 */ "LWXC1\0" |
7931 | | /* 201 */ "SWXC1\0" |
7932 | | /* 207 */ "MTM1\0" |
7933 | | /* 212 */ "SDC1_M1\0" |
7934 | | /* 220 */ "MTP1\0" |
7935 | | /* 225 */ "BBIT1\0" |
7936 | | /* 231 */ "BBIT032\0" |
7937 | | /* 239 */ "BBIT132\0" |
7938 | | /* 247 */ "DSRA32\0" |
7939 | | /* 254 */ "MFHC1_D32\0" |
7940 | | /* 264 */ "MTHC1_D32\0" |
7941 | | /* 274 */ "FSUB_D32\0" |
7942 | | /* 283 */ "NMSUB_D32\0" |
7943 | | /* 293 */ "FADD_D32\0" |
7944 | | /* 302 */ "NMADD_D32\0" |
7945 | | /* 312 */ "C_NGE_D32\0" |
7946 | | /* 322 */ "C_NGLE_D32\0" |
7947 | | /* 333 */ "C_OLE_D32\0" |
7948 | | /* 343 */ "C_ULE_D32\0" |
7949 | | /* 353 */ "C_LE_D32\0" |
7950 | | /* 362 */ "C_SF_D32\0" |
7951 | | /* 371 */ "MOVF_D32\0" |
7952 | | /* 380 */ "C_F_D32\0" |
7953 | | /* 388 */ "PseudoSELECTFP_F_D32\0" |
7954 | | /* 409 */ "FNEG_D32\0" |
7955 | | /* 418 */ "MOVN_I_D32\0" |
7956 | | /* 429 */ "MOVZ_I_D32\0" |
7957 | | /* 440 */ "C_NGL_D32\0" |
7958 | | /* 450 */ "FMUL_D32\0" |
7959 | | /* 459 */ "LDC1_MM_D32\0" |
7960 | | /* 471 */ "SDC1_MM_D32\0" |
7961 | | /* 483 */ "C_UN_D32\0" |
7962 | | /* 492 */ "RECIP_D32\0" |
7963 | | /* 502 */ "FCMP_D32\0" |
7964 | | /* 511 */ "C_SEQ_D32\0" |
7965 | | /* 521 */ "C_UEQ_D32\0" |
7966 | | /* 531 */ "C_EQ_D32\0" |
7967 | | /* 540 */ "FABS_D32\0" |
7968 | | /* 549 */ "CVT_S_D32\0" |
7969 | | /* 559 */ "PseudoSELECT_D32\0" |
7970 | | /* 576 */ "C_NGT_D32\0" |
7971 | | /* 586 */ "C_OLT_D32\0" |
7972 | | /* 596 */ "C_ULT_D32\0" |
7973 | | /* 606 */ "C_LT_D32\0" |
7974 | | /* 615 */ "FSQRT_D32\0" |
7975 | | /* 625 */ "RSQRT_D32\0" |
7976 | | /* 635 */ "MOVT_D32\0" |
7977 | | /* 644 */ "PseudoSELECTFP_T_D32\0" |
7978 | | /* 665 */ "FDIV_D32\0" |
7979 | | /* 674 */ "FMOV_D32\0" |
7980 | | /* 683 */ "PseudoTRUNC_W_D32\0" |
7981 | | /* 701 */ "ROUND_W_D32\0" |
7982 | | /* 713 */ "CEIL_W_D32\0" |
7983 | | /* 724 */ "FLOOR_W_D32\0" |
7984 | | /* 736 */ "CVT_W_D32\0" |
7985 | | /* 746 */ "BPOSGE32\0" |
7986 | | /* 755 */ "ATOMIC_LOAD_SUB_I32\0" |
7987 | | /* 775 */ "ATOMIC_LOAD_ADD_I32\0" |
7988 | | /* 795 */ "ATOMIC_LOAD_NAND_I32\0" |
7989 | | /* 816 */ "ATOMIC_LOAD_AND_I32\0" |
7990 | | /* 836 */ "ATOMIC_LOAD_UMIN_I32\0" |
7991 | | /* 857 */ "ATOMIC_LOAD_MIN_I32\0" |
7992 | | /* 877 */ "ATOMIC_SWAP_I32\0" |
7993 | | /* 893 */ "ATOMIC_CMP_SWAP_I32\0" |
7994 | | /* 913 */ "ATOMIC_LOAD_XOR_I32\0" |
7995 | | /* 933 */ "ATOMIC_LOAD_OR_I32\0" |
7996 | | /* 952 */ "ATOMIC_LOAD_UMAX_I32\0" |
7997 | | /* 973 */ "ATOMIC_LOAD_MAX_I32\0" |
7998 | | /* 993 */ "DSLL32\0" |
7999 | | /* 1000 */ "DSRL32\0" |
8000 | | /* 1007 */ "DROTR32\0" |
8001 | | /* 1015 */ "CINS32\0" |
8002 | | /* 1022 */ "EXTS32\0" |
8003 | | /* 1029 */ "FCMP_S32\0" |
8004 | | /* 1038 */ "DSLL64_32\0" |
8005 | | /* 1048 */ "CINS64_32\0" |
8006 | | /* 1058 */ "DEXT64_32\0" |
8007 | | /* 1068 */ "LoadImmDoubleFGR_32\0" |
8008 | | /* 1088 */ "LoadAddrReg32\0" |
8009 | | /* 1102 */ "CINS_i32\0" |
8010 | | /* 1111 */ "LoadImm32\0" |
8011 | | /* 1121 */ "LoadAddrImm32\0" |
8012 | | /* 1135 */ "MIPSeh_return32\0" |
8013 | | /* 1151 */ "LwConstant32\0" |
8014 | | /* 1164 */ "LDC2\0" |
8015 | | /* 1169 */ "SDC2\0" |
8016 | | /* 1174 */ "DMFC2\0" |
8017 | | /* 1180 */ "DMTC2\0" |
8018 | | /* 1186 */ "LWC2\0" |
8019 | | /* 1191 */ "SWC2\0" |
8020 | | /* 1196 */ "G_FLOG2\0" |
8021 | | /* 1204 */ "MTM2\0" |
8022 | | /* 1209 */ "MTP2\0" |
8023 | | /* 1214 */ "G_FEXP2\0" |
8024 | | /* 1222 */ "SHRA_QB_MMR2\0" |
8025 | | /* 1235 */ "CMPGDU_LE_QB_MMR2\0" |
8026 | | /* 1253 */ "SUBUH_QB_MMR2\0" |
8027 | | /* 1267 */ "ADDUH_QB_MMR2\0" |
8028 | | /* 1281 */ "CMPGDU_EQ_QB_MMR2\0" |
8029 | | /* 1299 */ "SHRA_R_QB_MMR2\0" |
8030 | | /* 1314 */ "SUBUH_R_QB_MMR2\0" |
8031 | | /* 1330 */ "ADDUH_R_QB_MMR2\0" |
8032 | | /* 1346 */ "SHRAV_R_QB_MMR2\0" |
8033 | | /* 1362 */ "ABSQ_S_QB_MMR2\0" |
8034 | | /* 1377 */ "CMPGDU_LT_QB_MMR2\0" |
8035 | | /* 1395 */ "SHRAV_QB_MMR2\0" |
8036 | | /* 1409 */ "PREPEND_MMR2\0" |
8037 | | /* 1422 */ "APPEND_MMR2\0" |
8038 | | /* 1434 */ "PRECR_QB_PH_MMR2\0" |
8039 | | /* 1451 */ "SUBQH_PH_MMR2\0" |
8040 | | /* 1465 */ "ADDQH_PH_MMR2\0" |
8041 | | /* 1479 */ "SHRL_PH_MMR2\0" |
8042 | | /* 1492 */ "MUL_PH_MMR2\0" |
8043 | | /* 1504 */ "SUBQH_R_PH_MMR2\0" |
8044 | | /* 1520 */ "ADDQH_R_PH_MMR2\0" |
8045 | | /* 1536 */ "MUL_S_PH_MMR2\0" |
8046 | | /* 1550 */ "MULQ_S_PH_MMR2\0" |
8047 | | /* 1565 */ "SUBU_S_PH_MMR2\0" |
8048 | | /* 1580 */ "ADDU_S_PH_MMR2\0" |
8049 | | /* 1595 */ "SUBU_PH_MMR2\0" |
8050 | | /* 1608 */ "ADDU_PH_MMR2\0" |
8051 | | /* 1621 */ "SHRLV_PH_MMR2\0" |
8052 | | /* 1635 */ "DPA_W_PH_MMR2\0" |
8053 | | /* 1649 */ "MULSA_W_PH_MMR2\0" |
8054 | | /* 1665 */ "DPAQX_SA_W_PH_MMR2\0" |
8055 | | /* 1684 */ "DPSQX_SA_W_PH_MMR2\0" |
8056 | | /* 1703 */ "DPS_W_PH_MMR2\0" |
8057 | | /* 1717 */ "DPAQX_S_W_PH_MMR2\0" |
8058 | | /* 1735 */ "DPSQX_S_W_PH_MMR2\0" |
8059 | | /* 1753 */ "DPAX_W_PH_MMR2\0" |
8060 | | /* 1768 */ "DPSX_W_PH_MMR2\0" |
8061 | | /* 1783 */ "BALIGN_MMR2\0" |
8062 | | /* 1795 */ "PRECR_SRA_PH_W_MMR2\0" |
8063 | | /* 1815 */ "PRECR_SRA_R_PH_W_MMR2\0" |
8064 | | /* 1837 */ "SUBQH_W_MMR2\0" |
8065 | | /* 1850 */ "ADDQH_W_MMR2\0" |
8066 | | /* 1863 */ "SUBQH_R_W_MMR2\0" |
8067 | | /* 1878 */ "ADDQH_R_W_MMR2\0" |
8068 | | /* 1893 */ "MULQ_RS_W_MMR2\0" |
8069 | | /* 1908 */ "MULQ_S_W_MMR2\0" |
8070 | | /* 1922 */ "LDC3\0" |
8071 | | /* 1927 */ "SDC3\0" |
8072 | | /* 1932 */ "LWC3\0" |
8073 | | /* 1937 */ "SWC3\0" |
8074 | | /* 1942 */ "BPOSGE32C_MMR3\0" |
8075 | | /* 1957 */ "LDC164\0" |
8076 | | /* 1964 */ "SDC164\0" |
8077 | | /* 1971 */ "LDXC164\0" |
8078 | | /* 1979 */ "SDXC164\0" |
8079 | | /* 1987 */ "LUXC164\0" |
8080 | | /* 1995 */ "SUXC164\0" |
8081 | | /* 2003 */ "SEB64\0" |
8082 | | /* 2009 */ "TAILCALLREGHB64\0" |
8083 | | /* 2025 */ "JR_HB64\0" |
8084 | | /* 2033 */ "JALR_HB64\0" |
8085 | | /* 2043 */ "LB64\0" |
8086 | | /* 2048 */ "SB64\0" |
8087 | | /* 2053 */ "LOAD_ACC64\0" |
8088 | | /* 2064 */ "STORE_ACC64\0" |
8089 | | /* 2076 */ "BGEC64\0" |
8090 | | /* 2083 */ "BNEC64\0" |
8091 | | /* 2090 */ "JIC64\0" |
8092 | | /* 2096 */ "JIALC64\0" |
8093 | | /* 2104 */ "BEQC64\0" |
8094 | | /* 2111 */ "SC64\0" |
8095 | | /* 2116 */ "BLTC64\0" |
8096 | | /* 2123 */ "BGEUC64\0" |
8097 | | /* 2131 */ "BLTUC64\0" |
8098 | | /* 2139 */ "BGEZC64\0" |
8099 | | /* 2147 */ "BLEZC64\0" |
8100 | | /* 2155 */ "BNEZC64\0" |
8101 | | /* 2163 */ "BEQZC64\0" |
8102 | | /* 2171 */ "BGTZC64\0" |
8103 | | /* 2179 */ "BLTZC64\0" |
8104 | | /* 2187 */ "AND64\0" |
8105 | | /* 2193 */ "MFC1_D64\0" |
8106 | | /* 2202 */ "MFHC1_D64\0" |
8107 | | /* 2212 */ "MTHC1_D64\0" |
8108 | | /* 2222 */ "MTC1_D64\0" |
8109 | | /* 2231 */ "MOVN_I64_D64\0" |
8110 | | /* 2244 */ "MOVZ_I64_D64\0" |
8111 | | /* 2257 */ "FSUB_D64\0" |
8112 | | /* 2266 */ "NMSUB_D64\0" |
8113 | | /* 2276 */ "FADD_D64\0" |
8114 | | /* 2285 */ "NMADD_D64\0" |
8115 | | /* 2295 */ "C_NGE_D64\0" |
8116 | | /* 2305 */ "C_NGLE_D64\0" |
8117 | | /* 2316 */ "C_OLE_D64\0" |
8118 | | /* 2326 */ "C_ULE_D64\0" |
8119 | | /* 2336 */ "C_LE_D64\0" |
8120 | | /* 2345 */ "C_SF_D64\0" |
8121 | | /* 2354 */ "MOVF_D64\0" |
8122 | | /* 2363 */ "C_F_D64\0" |
8123 | | /* 2371 */ "PseudoSELECTFP_F_D64\0" |
8124 | | /* 2392 */ "FNEG_D64\0" |
8125 | | /* 2401 */ "MOVN_I_D64\0" |
8126 | | /* 2412 */ "MOVZ_I_D64\0" |
8127 | | /* 2423 */ "C_NGL_D64\0" |
8128 | | /* 2433 */ "FMUL_D64\0" |
8129 | | /* 2442 */ "TRUNC_L_D64\0" |
8130 | | /* 2454 */ "ROUND_L_D64\0" |
8131 | | /* 2466 */ "CEIL_L_D64\0" |
8132 | | /* 2477 */ "FLOOR_L_D64\0" |
8133 | | /* 2489 */ "CVT_L_D64\0" |
8134 | | /* 2499 */ "LDC1_MM_D64\0" |
8135 | | /* 2511 */ "SDC1_MM_D64\0" |
8136 | | /* 2523 */ "C_UN_D64\0" |
8137 | | /* 2532 */ "RECIP_D64\0" |
8138 | | /* 2542 */ "FCMP_D64\0" |
8139 | | /* 2551 */ "C_SEQ_D64\0" |
8140 | | /* 2561 */ "C_UEQ_D64\0" |
8141 | | /* 2571 */ "C_EQ_D64\0" |
8142 | | /* 2580 */ "FABS_D64\0" |
8143 | | /* 2589 */ "CVT_S_D64\0" |
8144 | | /* 2599 */ "PseudoSELECT_D64\0" |
8145 | | /* 2616 */ "C_NGT_D64\0" |
8146 | | /* 2626 */ "C_OLT_D64\0" |
8147 | | /* 2636 */ "C_ULT_D64\0" |
8148 | | /* 2646 */ "C_LT_D64\0" |
8149 | | /* 2655 */ "FSQRT_D64\0" |
8150 | | /* 2665 */ "RSQRT_D64\0" |
8151 | | /* 2675 */ "MOVT_D64\0" |
8152 | | /* 2684 */ "PseudoSELECTFP_T_D64\0" |
8153 | | /* 2705 */ "FDIV_D64\0" |
8154 | | /* 2714 */ "FMOV_D64\0" |
8155 | | /* 2723 */ "TRUNC_W_D64\0" |
8156 | | /* 2735 */ "ROUND_W_D64\0" |
8157 | | /* 2747 */ "CEIL_W_D64\0" |
8158 | | /* 2758 */ "FLOOR_W_D64\0" |
8159 | | /* 2770 */ "CVT_W_D64\0" |
8160 | | /* 2780 */ "BNE64\0" |
8161 | | /* 2786 */ "BuildPairF64\0" |
8162 | | /* 2799 */ "ExtractElementF64\0" |
8163 | | /* 2817 */ "TAILCALLREG64\0" |
8164 | | /* 2831 */ "SEH64\0" |
8165 | | /* 2837 */ "LH64\0" |
8166 | | /* 2842 */ "SH64\0" |
8167 | | /* 2847 */ "PseudoMFHI64\0" |
8168 | | /* 2860 */ "PseudoMTLOHI64\0" |
8169 | | /* 2875 */ "MTHI64\0" |
8170 | | /* 2882 */ "MOVN_I64_I64\0" |
8171 | | /* 2895 */ "MOVZ_I64_I64\0" |
8172 | | /* 2908 */ "ATOMIC_LOAD_SUB_I64\0" |
8173 | | /* 2928 */ "ATOMIC_LOAD_ADD_I64\0" |
8174 | | /* 2948 */ "ATOMIC_LOAD_NAND_I64\0" |
8175 | | /* 2969 */ "ATOMIC_LOAD_AND_I64\0" |
8176 | | /* 2989 */ "MOVF_I64\0" |
8177 | | /* 2998 */ "PseudoSELECTFP_F_I64\0" |
8178 | | /* 3019 */ "MOVN_I_I64\0" |
8179 | | /* 3030 */ "MOVZ_I_I64\0" |
8180 | | /* 3041 */ "ATOMIC_LOAD_UMIN_I64\0" |
8181 | | /* 3062 */ "ATOMIC_LOAD_MIN_I64\0" |
8182 | | /* 3082 */ "ATOMIC_SWAP_I64\0" |
8183 | | /* 3098 */ "ATOMIC_CMP_SWAP_I64\0" |
8184 | | /* 3118 */ "ATOMIC_LOAD_XOR_I64\0" |
8185 | | /* 3138 */ "ATOMIC_LOAD_OR_I64\0" |
8186 | | /* 3157 */ "PseudoD_SELECT_I64\0" |
8187 | | /* 3176 */ "PseudoSELECT_I64\0" |
8188 | | /* 3193 */ "MOVT_I64\0" |
8189 | | /* 3202 */ "PseudoSELECTFP_T_I64\0" |
8190 | | /* 3223 */ "ATOMIC_LOAD_UMAX_I64\0" |
8191 | | /* 3244 */ "ATOMIC_LOAD_MAX_I64\0" |
8192 | | /* 3264 */ "LL64\0" |
8193 | | /* 3269 */ "CVT_S_PL64\0" |
8194 | | /* 3280 */ "LWL64\0" |
8195 | | /* 3286 */ "SWL64\0" |
8196 | | /* 3292 */ "PseudoMFLO64\0" |
8197 | | /* 3305 */ "MTLO64\0" |
8198 | | /* 3312 */ "BEQ64\0" |
8199 | | /* 3318 */ "JR64\0" |
8200 | | /* 3323 */ "JALR64\0" |
8201 | | /* 3330 */ "NOR64\0" |
8202 | | /* 3336 */ "XOR64\0" |
8203 | | /* 3342 */ "RDHWR64\0" |
8204 | | /* 3350 */ "LWR64\0" |
8205 | | /* 3356 */ "SWR64\0" |
8206 | | /* 3362 */ "FSUB_PS64\0" |
8207 | | /* 3372 */ "FADD_PS64\0" |
8208 | | /* 3382 */ "PLL_PS64\0" |
8209 | | /* 3391 */ "FMUL_PS64\0" |
8210 | | /* 3401 */ "PUL_PS64\0" |
8211 | | /* 3410 */ "ADDR_PS64\0" |
8212 | | /* 3420 */ "MULR_PS64\0" |
8213 | | /* 3430 */ "PLU_PS64\0" |
8214 | | /* 3439 */ "PUU_PS64\0" |
8215 | | /* 3448 */ "CVT_PW_PS64\0" |
8216 | | /* 3460 */ "CVT_PS_S64\0" |
8217 | | /* 3471 */ "SLT64\0" |
8218 | | /* 3477 */ "CVT_S_PU64\0" |
8219 | | /* 3488 */ "LW64\0" |
8220 | | /* 3493 */ "CVT_PS_PW64\0" |
8221 | | /* 3505 */ "SW64\0" |
8222 | | /* 3510 */ "BGEZ64\0" |
8223 | | /* 3517 */ "BLEZ64\0" |
8224 | | /* 3524 */ "SELNEZ64\0" |
8225 | | /* 3533 */ "SELEQZ64\0" |
8226 | | /* 3542 */ "BGTZ64\0" |
8227 | | /* 3549 */ "BLTZ64\0" |
8228 | | /* 3556 */ "BuildPairF64_64\0" |
8229 | | /* 3572 */ "ExtractElementF64_64\0" |
8230 | | /* 3593 */ "SLL64_64\0" |
8231 | | /* 3602 */ "LONG_BRANCH_LUi2Op_64\0" |
8232 | | /* 3624 */ "LoadAddrReg64\0" |
8233 | | /* 3638 */ "PseudoIndirectHazardBranch64\0" |
8234 | | /* 3667 */ "PseudoIndirectBranch64\0" |
8235 | | /* 3690 */ "ANDi64\0" |
8236 | | /* 3697 */ "XORi64\0" |
8237 | | /* 3704 */ "SLTi64\0" |
8238 | | /* 3711 */ "LUi64\0" |
8239 | | /* 3717 */ "SGEImm64\0" |
8240 | | /* 3726 */ "SLEImm64\0" |
8241 | | /* 3735 */ "NORImm64\0" |
8242 | | /* 3744 */ "SGTImm64\0" |
8243 | | /* 3753 */ "SLTImm64\0" |
8244 | | /* 3762 */ "SGEUImm64\0" |
8245 | | /* 3772 */ "SLEUImm64\0" |
8246 | | /* 3782 */ "SGTUImm64\0" |
8247 | | /* 3792 */ "SLTUImm64\0" |
8248 | | /* 3802 */ "LoadImm64\0" |
8249 | | /* 3812 */ "LoadAddrImm64\0" |
8250 | | /* 3826 */ "PseudoReturn64\0" |
8251 | | /* 3841 */ "MIPSeh_return64\0" |
8252 | | /* 3857 */ "LBu64\0" |
8253 | | /* 3863 */ "LHu64\0" |
8254 | | /* 3869 */ "SLTu64\0" |
8255 | | /* 3876 */ "LEA_ADDiu64\0" |
8256 | | /* 3888 */ "SLTiu64\0" |
8257 | | /* 3896 */ "MoveR3216\0" |
8258 | | /* 3906 */ "RetRA16\0" |
8259 | | /* 3914 */ "JalB16\0" |
8260 | | /* 3921 */ "LD_F16\0" |
8261 | | /* 3928 */ "ST_F16\0" |
8262 | | /* 3935 */ "ATOMIC_LOAD_SUB_I16\0" |
8263 | | /* 3955 */ "ATOMIC_LOAD_ADD_I16\0" |
8264 | | /* 3975 */ "ATOMIC_LOAD_NAND_I16\0" |
8265 | | /* 3996 */ "ATOMIC_LOAD_AND_I16\0" |
8266 | | /* 4016 */ "ATOMIC_LOAD_UMIN_I16\0" |
8267 | | /* 4037 */ "ATOMIC_LOAD_MIN_I16\0" |
8268 | | /* 4057 */ "ATOMIC_SWAP_I16\0" |
8269 | | /* 4073 */ "ATOMIC_CMP_SWAP_I16\0" |
8270 | | /* 4093 */ "ATOMIC_LOAD_XOR_I16\0" |
8271 | | /* 4113 */ "ATOMIC_LOAD_OR_I16\0" |
8272 | | /* 4132 */ "ATOMIC_LOAD_UMAX_I16\0" |
8273 | | /* 4153 */ "ATOMIC_LOAD_MAX_I16\0" |
8274 | | /* 4173 */ "Move32R16\0" |
8275 | | /* 4183 */ "SraX16\0" |
8276 | | /* 4190 */ "RestoreX16\0" |
8277 | | /* 4201 */ "SaveX16\0" |
8278 | | /* 4209 */ "BtnezT8CmpiX16\0" |
8279 | | /* 4224 */ "BteqzT8CmpiX16\0" |
8280 | | /* 4239 */ "BtnezT8SltiX16\0" |
8281 | | /* 4254 */ "BteqzT8SltiX16\0" |
8282 | | /* 4269 */ "SllX16\0" |
8283 | | /* 4276 */ "SrlX16\0" |
8284 | | /* 4283 */ "LbRxRyOffMemX16\0" |
8285 | | /* 4299 */ "SbRxRyOffMemX16\0" |
8286 | | /* 4315 */ "LhRxRyOffMemX16\0" |
8287 | | /* 4331 */ "ShRxRyOffMemX16\0" |
8288 | | /* 4347 */ "LbuRxRyOffMemX16\0" |
8289 | | /* 4364 */ "LhuRxRyOffMemX16\0" |
8290 | | /* 4381 */ "AddiuRxRyOffMemX16\0" |
8291 | | /* 4400 */ "LwRxRyOffMemX16\0" |
8292 | | /* 4416 */ "SwRxRyOffMemX16\0" |
8293 | | /* 4432 */ "AddiuRxPcImmX16\0" |
8294 | | /* 4448 */ "AddiuSpImmX16\0" |
8295 | | /* 4462 */ "LwRxSpImmX16\0" |
8296 | | /* 4475 */ "SwRxSpImmX16\0" |
8297 | | /* 4488 */ "SltiCCRxImmX16\0" |
8298 | | /* 4503 */ "SltiuCCRxImmX16\0" |
8299 | | /* 4519 */ "LiRxImmX16\0" |
8300 | | /* 4530 */ "CmpiRxImmX16\0" |
8301 | | /* 4543 */ "SltiRxImmX16\0" |
8302 | | /* 4556 */ "AddiuRxImmX16\0" |
8303 | | /* 4570 */ "SltiuRxImmX16\0" |
8304 | | /* 4584 */ "AddiuRxRxImmX16\0" |
8305 | | /* 4600 */ "BnezRxImmX16\0" |
8306 | | /* 4613 */ "BeqzRxImmX16\0" |
8307 | | /* 4626 */ "BimmX16\0" |
8308 | | /* 4634 */ "LiRxImmAlignX16\0" |
8309 | | /* 4650 */ "LwRxPcTcpX16\0" |
8310 | | /* 4663 */ "BtnezT8CmpX16\0" |
8311 | | /* 4677 */ "BteqzT8CmpX16\0" |
8312 | | /* 4691 */ "BtnezT8SltX16\0" |
8313 | | /* 4705 */ "BteqzT8SltX16\0" |
8314 | | /* 4719 */ "BtnezT8SltiuX16\0" |
8315 | | /* 4735 */ "BteqzT8SltiuX16\0" |
8316 | | /* 4751 */ "BtnezT8SltuX16\0" |
8317 | | /* 4766 */ "BteqzT8SltuX16\0" |
8318 | | /* 4781 */ "BtnezX16\0" |
8319 | | /* 4790 */ "BteqzX16\0" |
8320 | | /* 4799 */ "JrcRa16\0" |
8321 | | /* 4807 */ "JrRa16\0" |
8322 | | /* 4814 */ "Restore16\0" |
8323 | | /* 4824 */ "GotPrologue16\0" |
8324 | | /* 4838 */ "Save16\0" |
8325 | | /* 4845 */ "JumpLinkReg16\0" |
8326 | | /* 4859 */ "Mfhi16\0" |
8327 | | /* 4866 */ "Break16\0" |
8328 | | /* 4874 */ "Jal16\0" |
8329 | | /* 4880 */ "AddiuSpImm16\0" |
8330 | | /* 4893 */ "LiRxImm16\0" |
8331 | | /* 4903 */ "CmpiRxImm16\0" |
8332 | | /* 4915 */ "SltiRxImm16\0" |
8333 | | /* 4927 */ "SltiuRxImm16\0" |
8334 | | /* 4940 */ "AddiuRxRxImm16\0" |
8335 | | /* 4955 */ "BnezRxImm16\0" |
8336 | | /* 4967 */ "BeqzRxImm16\0" |
8337 | | /* 4979 */ "Bimm16\0" |
8338 | | /* 4986 */ "Mflo16\0" |
8339 | | /* 4993 */ "LwRxPcTcp16\0" |
8340 | | /* 5005 */ "SebRx16\0" |
8341 | | /* 5013 */ "JrcRx16\0" |
8342 | | /* 5021 */ "SehRx16\0" |
8343 | | /* 5029 */ "SltCCRxRy16\0" |
8344 | | /* 5041 */ "SltuCCRxRy16\0" |
8345 | | /* 5054 */ "NegRxRy16\0" |
8346 | | /* 5064 */ "CmpRxRy16\0" |
8347 | | /* 5074 */ "SltRxRy16\0" |
8348 | | /* 5084 */ "MultRxRy16\0" |
8349 | | /* 5095 */ "NotRxRy16\0" |
8350 | | /* 5105 */ "SltuRxRy16\0" |
8351 | | /* 5116 */ "MultuRxRy16\0" |
8352 | | /* 5128 */ "DivuRxRy16\0" |
8353 | | /* 5139 */ "SravRxRy16\0" |
8354 | | /* 5150 */ "DivRxRy16\0" |
8355 | | /* 5160 */ "SllvRxRy16\0" |
8356 | | /* 5171 */ "SrlvRxRy16\0" |
8357 | | /* 5182 */ "AndRxRxRy16\0" |
8358 | | /* 5194 */ "OrRxRxRy16\0" |
8359 | | /* 5205 */ "XorRxRxRy16\0" |
8360 | | /* 5217 */ "MultRxRyRz16\0" |
8361 | | /* 5230 */ "SubuRxRyRz16\0" |
8362 | | /* 5243 */ "AdduRxRyRz16\0" |
8363 | | /* 5256 */ "SltuRxRyRz16\0" |
8364 | | /* 5269 */ "MultuRxRyRz16\0" |
8365 | | /* 5283 */ "Btnez16\0" |
8366 | | /* 5291 */ "Bteqz16\0" |
8367 | | /* 5299 */ "PseudoIndrectHazardBranch64R6\0" |
8368 | | /* 5329 */ "PseudoIndirectBranch64R6\0" |
8369 | | /* 5354 */ "MFC0_MMR6\0" |
8370 | | /* 5364 */ "MFHC0_MMR6\0" |
8371 | | /* 5375 */ "MTHC0_MMR6\0" |
8372 | | /* 5386 */ "MTC0_MMR6\0" |
8373 | | /* 5396 */ "MFC1_MMR6\0" |
8374 | | /* 5406 */ "MTC1_MMR6\0" |
8375 | | /* 5416 */ "LDC2_MMR6\0" |
8376 | | /* 5426 */ "SDC2_MMR6\0" |
8377 | | /* 5436 */ "MFC2_MMR6\0" |
8378 | | /* 5446 */ "MFHC2_MMR6\0" |
8379 | | /* 5457 */ "MTHC2_MMR6\0" |
8380 | | /* 5468 */ "MTC2_MMR6\0" |
8381 | | /* 5478 */ "LWC2_MMR6\0" |
8382 | | /* 5488 */ "SWC2_MMR6\0" |
8383 | | /* 5498 */ "LDC1_D64_MMR6\0" |
8384 | | /* 5512 */ "SDC1_D64_MMR6\0" |
8385 | | /* 5526 */ "SB16_MMR6\0" |
8386 | | /* 5536 */ "BC16_MMR6\0" |
8387 | | /* 5546 */ "JRC16_MMR6\0" |
8388 | | /* 5557 */ "JALRC16_MMR6\0" |
8389 | | /* 5570 */ "BNEZC16_MMR6\0" |
8390 | | /* 5583 */ "BEQZC16_MMR6\0" |
8391 | | /* 5596 */ "AND16_MMR6\0" |
8392 | | /* 5607 */ "MOVE16_MMR6\0" |
8393 | | /* 5619 */ "SH16_MMR6\0" |
8394 | | /* 5629 */ "ANDI16_MMR6\0" |
8395 | | /* 5641 */ "LI16_MMR6\0" |
8396 | | /* 5651 */ "BREAK16_MMR6\0" |
8397 | | /* 5664 */ "SLL16_MMR6\0" |
8398 | | /* 5675 */ "SRL16_MMR6\0" |
8399 | | /* 5686 */ "LWM16_MMR6\0" |
8400 | | /* 5697 */ "SWM16_MMR6\0" |
8401 | | /* 5708 */ "SDBBP16_MMR6\0" |
8402 | | /* 5721 */ "XOR16_MMR6\0" |
8403 | | /* 5732 */ "NOT16_MMR6\0" |
8404 | | /* 5743 */ "SUBU16_MMR6\0" |
8405 | | /* 5755 */ "ADDU16_MMR6\0" |
8406 | | /* 5767 */ "SW16_MMR6\0" |
8407 | | /* 5777 */ "LSA_MMR6\0" |
8408 | | /* 5786 */ "EHB_MMR6\0" |
8409 | | /* 5795 */ "JALRC_HB_MMR6\0" |
8410 | | /* 5809 */ "LB_MMR6\0" |
8411 | | /* 5817 */ "SB_MMR6\0" |
8412 | | /* 5825 */ "SUB_MMR6\0" |
8413 | | /* 5834 */ "BC_MMR6\0" |
8414 | | /* 5842 */ "BGEC_MMR6\0" |
8415 | | /* 5852 */ "BNEC_MMR6\0" |
8416 | | /* 5862 */ "JIC_MMR6\0" |
8417 | | /* 5871 */ "BALC_MMR6\0" |
8418 | | /* 5881 */ "JIALC_MMR6\0" |
8419 | | /* 5892 */ "BGEZALC_MMR6\0" |
8420 | | /* 5905 */ "BLEZALC_MMR6\0" |
8421 | | /* 5918 */ "BNEZALC_MMR6\0" |
8422 | | /* 5931 */ "BEQZALC_MMR6\0" |
8423 | | /* 5944 */ "BGTZALC_MMR6\0" |
8424 | | /* 5957 */ "BLTZALC_MMR6\0" |
8425 | | /* 5970 */ "ERETNC_MMR6\0" |
8426 | | /* 5982 */ "SYNC_MMR6\0" |
8427 | | /* 5992 */ "AUIPC_MMR6\0" |
8428 | | /* 6003 */ "ALUIPC_MMR6\0" |
8429 | | /* 6015 */ "ADDIUPC_MMR6\0" |
8430 | | /* 6028 */ "LWPC_MMR6\0" |
8431 | | /* 6038 */ "BEQC_MMR6\0" |
8432 | | /* 6048 */ "JALRC_MMR6\0" |
8433 | | /* 6059 */ "SC_MMR6\0" |
8434 | | /* 6067 */ "BLTC_MMR6\0" |
8435 | | /* 6077 */ "BGEUC_MMR6\0" |
8436 | | /* 6088 */ "BLTUC_MMR6\0" |
8437 | | /* 6099 */ "BNVC_MMR6\0" |
8438 | | /* 6109 */ "BOVC_MMR6\0" |
8439 | | /* 6119 */ "BGEZC_MMR6\0" |
8440 | | /* 6130 */ "BLEZC_MMR6\0" |
8441 | | /* 6141 */ "BC1NEZC_MMR6\0" |
8442 | | /* 6154 */ "BC2NEZC_MMR6\0" |
8443 | | /* 6167 */ "BNEZC_MMR6\0" |
8444 | | /* 6178 */ "BC1EQZC_MMR6\0" |
8445 | | /* 6191 */ "BC2EQZC_MMR6\0" |
8446 | | /* 6204 */ "BEQZC_MMR6\0" |
8447 | | /* 6215 */ "BGTZC_MMR6\0" |
8448 | | /* 6226 */ "BLTZC_MMR6\0" |
8449 | | /* 6237 */ "ADD_MMR6\0" |
8450 | | /* 6246 */ "AND_MMR6\0" |
8451 | | /* 6255 */ "MOD_MMR6\0" |
8452 | | /* 6264 */ "MINA_D_MMR6\0" |
8453 | | /* 6276 */ "MAXA_D_MMR6\0" |
8454 | | /* 6288 */ "CMP_SLE_D_MMR6\0" |
8455 | | /* 6303 */ "CMP_SULE_D_MMR6\0" |
8456 | | /* 6319 */ "CMP_ULE_D_MMR6\0" |
8457 | | /* 6334 */ "CMP_LE_D_MMR6\0" |
8458 | | /* 6348 */ "CMP_SAF_D_MMR6\0" |
8459 | | /* 6363 */ "CMP_AF_D_MMR6\0" |
8460 | | /* 6377 */ "MSUBF_D_MMR6\0" |
8461 | | /* 6390 */ "MADDF_D_MMR6\0" |
8462 | | /* 6403 */ "SEL_D_MMR6\0" |
8463 | | /* 6414 */ "TRUNC_L_D_MMR6\0" |
8464 | | /* 6429 */ "ROUND_L_D_MMR6\0" |
8465 | | /* 6444 */ "CEIL_L_D_MMR6\0" |
8466 | | /* 6458 */ "FLOOR_L_D_MMR6\0" |
8467 | | /* 6473 */ "CVT_L_D_MMR6\0" |
8468 | | /* 6486 */ "MIN_D_MMR6\0" |
8469 | | /* 6497 */ "CMP_SUN_D_MMR6\0" |
8470 | | /* 6512 */ "CMP_UN_D_MMR6\0" |
8471 | | /* 6526 */ "CMP_SEQ_D_MMR6\0" |
8472 | | /* 6541 */ "CMP_SUEQ_D_MMR6\0" |
8473 | | /* 6557 */ "CMP_UEQ_D_MMR6\0" |
8474 | | /* 6572 */ "CMP_EQ_D_MMR6\0" |
8475 | | /* 6586 */ "CLASS_D_MMR6\0" |
8476 | | /* 6599 */ "CMP_SLT_D_MMR6\0" |
8477 | | /* 6614 */ "CMP_SULT_D_MMR6\0" |
8478 | | /* 6630 */ "CMP_ULT_D_MMR6\0" |
8479 | | /* 6645 */ "CMP_LT_D_MMR6\0" |
8480 | | /* 6659 */ "RINT_D_MMR6\0" |
8481 | | /* 6671 */ "FMOV_D_MMR6\0" |
8482 | | /* 6683 */ "TRUNC_W_D_MMR6\0" |
8483 | | /* 6698 */ "ROUND_W_D_MMR6\0" |
8484 | | /* 6713 */ "CEIL_W_D_MMR6\0" |
8485 | | /* 6727 */ "FLOOR_W_D_MMR6\0" |
8486 | | /* 6742 */ "MAX_D_MMR6\0" |
8487 | | /* 6753 */ "SELNEZ_D_MMR6\0" |
8488 | | /* 6767 */ "SELEQZ_D_MMR6\0" |
8489 | | /* 6781 */ "CACHE_MMR6\0" |
8490 | | /* 6792 */ "SIGRIE_MMR6\0" |
8491 | | /* 6804 */ "PAUSE_MMR6\0" |
8492 | | /* 6815 */ "PREF_MMR6\0" |
8493 | | /* 6825 */ "TLBINVF_MMR6\0" |
8494 | | /* 6838 */ "TAILCALLREG_MMR6\0" |
8495 | | /* 6855 */ "WSBH_MMR6\0" |
8496 | | /* 6865 */ "SH_MMR6\0" |
8497 | | /* 6873 */ "MUH_MMR6\0" |
8498 | | /* 6882 */ "SYNCI_MMR6\0" |
8499 | | /* 6893 */ "ANDI_MMR6\0" |
8500 | | /* 6903 */ "EI_MMR6\0" |
8501 | | /* 6911 */ "XORI_MMR6\0" |
8502 | | /* 6921 */ "AUI_MMR6\0" |
8503 | | /* 6930 */ "LUI_MMR6\0" |
8504 | | /* 6939 */ "GINVI_MMR6\0" |
8505 | | /* 6950 */ "BREAK_MMR6\0" |
8506 | | /* 6961 */ "JAL_MMR6\0" |
8507 | | /* 6970 */ "TAILCALL_MMR6\0" |
8508 | | /* 6984 */ "SLL_MMR6\0" |
8509 | | /* 6993 */ "MUL_MMR6\0" |
8510 | | /* 7002 */ "CVT_D_L_MMR6\0" |
8511 | | /* 7015 */ "CVT_S_L_MMR6\0" |
8512 | | /* 7028 */ "ALIGN_MMR6\0" |
8513 | | /* 7039 */ "CLO_MMR6\0" |
8514 | | /* 7048 */ "BITSWAP_MMR6\0" |
8515 | | /* 7061 */ "SDBBP_MMR6\0" |
8516 | | /* 7072 */ "MOVEP_MMR6\0" |
8517 | | /* 7083 */ "SSNOP_MMR6\0" |
8518 | | /* 7094 */ "JRCADDIUSP_MMR6\0" |
8519 | | /* 7110 */ "SWSP_MMR6\0" |
8520 | | /* 7120 */ "DVP_MMR6\0" |
8521 | | /* 7129 */ "EVP_MMR6\0" |
8522 | | /* 7138 */ "NOR_MMR6\0" |
8523 | | /* 7147 */ "XOR_MMR6\0" |
8524 | | /* 7156 */ "RDPGPR_MMR6\0" |
8525 | | /* 7168 */ "WRPGPR_MMR6\0" |
8526 | | /* 7180 */ "RDHWR_MMR6\0" |
8527 | | /* 7191 */ "INS_MMR6\0" |
8528 | | /* 7200 */ "MINA_S_MMR6\0" |
8529 | | /* 7212 */ "MAXA_S_MMR6\0" |
8530 | | /* 7224 */ "FSUB_S_MMR6\0" |
8531 | | /* 7236 */ "FADD_S_MMR6\0" |
8532 | | /* 7248 */ "CMP_SLE_S_MMR6\0" |
8533 | | /* 7263 */ "CMP_SULE_S_MMR6\0" |
8534 | | /* 7279 */ "CMP_ULE_S_MMR6\0" |
8535 | | /* 7294 */ "CMP_LE_S_MMR6\0" |
8536 | | /* 7308 */ "CMP_SAF_S_MMR6\0" |
8537 | | /* 7323 */ "CMP_AF_S_MMR6\0" |
8538 | | /* 7337 */ "MSUBF_S_MMR6\0" |
8539 | | /* 7350 */ "MADDF_S_MMR6\0" |
8540 | | /* 7363 */ "FNEG_S_MMR6\0" |
8541 | | /* 7375 */ "SEL_S_MMR6\0" |
8542 | | /* 7386 */ "FMUL_S_MMR6\0" |
8543 | | /* 7398 */ "TRUNC_L_S_MMR6\0" |
8544 | | /* 7413 */ "ROUND_L_S_MMR6\0" |
8545 | | /* 7428 */ "CEIL_L_S_MMR6\0" |
8546 | | /* 7442 */ "FLOOR_L_S_MMR6\0" |
8547 | | /* 7457 */ "CVT_L_S_MMR6\0" |
8548 | | /* 7470 */ "MIN_S_MMR6\0" |
8549 | | /* 7481 */ "CMP_SUN_S_MMR6\0" |
8550 | | /* 7496 */ "CMP_UN_S_MMR6\0" |
8551 | | /* 7510 */ "CMP_SEQ_S_MMR6\0" |
8552 | | /* 7525 */ "CMP_SUEQ_S_MMR6\0" |
8553 | | /* 7541 */ "CMP_UEQ_S_MMR6\0" |
8554 | | /* 7556 */ "CMP_EQ_S_MMR6\0" |
8555 | | /* 7570 */ "CLASS_S_MMR6\0" |
8556 | | /* 7583 */ "CMP_SLT_S_MMR6\0" |
8557 | | /* 7598 */ "CMP_SULT_S_MMR6\0" |
8558 | | /* 7614 */ "CMP_ULT_S_MMR6\0" |
8559 | | /* 7629 */ "CMP_LT_S_MMR6\0" |
8560 | | /* 7643 */ "RINT_S_MMR6\0" |
8561 | | /* 7655 */ "FDIV_S_MMR6\0" |
8562 | | /* 7667 */ "FMOV_S_MMR6\0" |
8563 | | /* 7679 */ "TRUNC_W_S_MMR6\0" |
8564 | | /* 7694 */ "ROUND_W_S_MMR6\0" |
8565 | | /* 7709 */ "CEIL_W_S_MMR6\0" |
8566 | | /* 7723 */ "FLOOR_W_S_MMR6\0" |
8567 | | /* 7738 */ "CVT_W_S_MMR6\0" |
8568 | | /* 7751 */ "MAX_S_MMR6\0" |
8569 | | /* 7762 */ "SELNEZ_S_MMR6\0" |
8570 | | /* 7776 */ "SELEQZ_S_MMR6\0" |
8571 | | /* 7790 */ "DERET_MMR6\0" |
8572 | | /* 7801 */ "WAIT_MMR6\0" |
8573 | | /* 7811 */ "GINVT_MMR6\0" |
8574 | | /* 7822 */ "EXT_MMR6\0" |
8575 | | /* 7831 */ "LBU_MMR6\0" |
8576 | | /* 7840 */ "SUBU_MMR6\0" |
8577 | | /* 7850 */ "ADDU_MMR6\0" |
8578 | | /* 7860 */ "MODU_MMR6\0" |
8579 | | /* 7870 */ "MUHU_MMR6\0" |
8580 | | /* 7880 */ "ADDIU_MMR6\0" |
8581 | | /* 7891 */ "MULU_MMR6\0" |
8582 | | /* 7901 */ "DIVU_MMR6\0" |
8583 | | /* 7911 */ "DIV_MMR6\0" |
8584 | | /* 7920 */ "TLBINV_MMR6\0" |
8585 | | /* 7932 */ "LW_MMR6\0" |
8586 | | /* 7940 */ "SW_MMR6\0" |
8587 | | /* 7948 */ "CVT_S_W_MMR6\0" |
8588 | | /* 7961 */ "SELNEZ_MMR6\0" |
8589 | | /* 7973 */ "CLZ_MMR6\0" |
8590 | | /* 7982 */ "SELEQZ_MMR6\0" |
8591 | | /* 7994 */ "PseudoIndirectBranch_MMR6\0" |
8592 | | /* 8020 */ "LDC2_R6\0" |
8593 | | /* 8028 */ "SDC2_R6\0" |
8594 | | /* 8036 */ "LWC2_R6\0" |
8595 | | /* 8044 */ "SWC2_R6\0" |
8596 | | /* 8052 */ "JR_HB64_R6\0" |
8597 | | /* 8063 */ "SC64_R6\0" |
8598 | | /* 8071 */ "LL64_R6\0" |
8599 | | /* 8079 */ "DLSA_R6\0" |
8600 | | /* 8087 */ "JR_HB_R6\0" |
8601 | | /* 8096 */ "SC_R6\0" |
8602 | | /* 8102 */ "SCD_R6\0" |
8603 | | /* 8109 */ "LLD_R6\0" |
8604 | | /* 8116 */ "CACHE_R6\0" |
8605 | | /* 8125 */ "PREF_R6\0" |
8606 | | /* 8133 */ "LL_R6\0" |
8607 | | /* 8139 */ "DMUL_R6\0" |
8608 | | /* 8147 */ "DCLO_R6\0" |
8609 | | /* 8155 */ "SDBBP_R6\0" |
8610 | | /* 8164 */ "DCLZ_R6\0" |
8611 | | /* 8172 */ "PseudoIndrectHazardBranchR6\0" |
8612 | | /* 8200 */ "PseudoIndirectBranchR6\0" |
8613 | | /* 8223 */ "LOAD_ACC128\0" |
8614 | | /* 8235 */ "STORE_ACC128\0" |
8615 | | /* 8248 */ "ATOMIC_LOAD_SUB_I8\0" |
8616 | | /* 8267 */ "ATOMIC_LOAD_ADD_I8\0" |
8617 | | /* 8286 */ "ATOMIC_LOAD_NAND_I8\0" |
8618 | | /* 8306 */ "ATOMIC_LOAD_AND_I8\0" |
8619 | | /* 8325 */ "ATOMIC_LOAD_UMIN_I8\0" |
8620 | | /* 8345 */ "ATOMIC_LOAD_MIN_I8\0" |
8621 | | /* 8364 */ "ATOMIC_SWAP_I8\0" |
8622 | | /* 8379 */ "ATOMIC_CMP_SWAP_I8\0" |
8623 | | /* 8398 */ "ATOMIC_LOAD_XOR_I8\0" |
8624 | | /* 8417 */ "ATOMIC_LOAD_OR_I8\0" |
8625 | | /* 8435 */ "ATOMIC_LOAD_UMAX_I8\0" |
8626 | | /* 8455 */ "ATOMIC_LOAD_MAX_I8\0" |
8627 | | /* 8474 */ "SAA\0" |
8628 | | /* 8478 */ "PRECEU_PH_QBLA\0" |
8629 | | /* 8493 */ "PRECEQU_PH_QBLA\0" |
8630 | | /* 8509 */ "G_FMA\0" |
8631 | | /* 8515 */ "G_STRICT_FMA\0" |
8632 | | /* 8528 */ "PRECEU_PH_QBRA\0" |
8633 | | /* 8543 */ "PRECEQU_PH_QBRA\0" |
8634 | | /* 8559 */ "DSRA\0" |
8635 | | /* 8564 */ "ATOMIC_LOAD_SUB_I32_POSTRA\0" |
8636 | | /* 8591 */ "ATOMIC_LOAD_ADD_I32_POSTRA\0" |
8637 | | /* 8618 */ "ATOMIC_LOAD_NAND_I32_POSTRA\0" |
8638 | | /* 8646 */ "ATOMIC_LOAD_AND_I32_POSTRA\0" |
8639 | | /* 8673 */ "ATOMIC_LOAD_UMIN_I32_POSTRA\0" |
8640 | | /* 8701 */ "ATOMIC_LOAD_MIN_I32_POSTRA\0" |
8641 | | /* 8728 */ "ATOMIC_SWAP_I32_POSTRA\0" |
8642 | | /* 8751 */ "ATOMIC_CMP_SWAP_I32_POSTRA\0" |
8643 | | /* 8778 */ "ATOMIC_LOAD_XOR_I32_POSTRA\0" |
8644 | | /* 8805 */ "ATOMIC_LOAD_OR_I32_POSTRA\0" |
8645 | | /* 8831 */ "ATOMIC_LOAD_UMAX_I32_POSTRA\0" |
8646 | | /* 8859 */ "ATOMIC_LOAD_MAX_I32_POSTRA\0" |
8647 | | /* 8886 */ "ATOMIC_LOAD_SUB_I64_POSTRA\0" |
8648 | | /* 8913 */ "ATOMIC_LOAD_ADD_I64_POSTRA\0" |
8649 | | /* 8940 */ "ATOMIC_LOAD_NAND_I64_POSTRA\0" |
8650 | | /* 8968 */ "ATOMIC_LOAD_AND_I64_POSTRA\0" |
8651 | | /* 8995 */ "ATOMIC_LOAD_UMIN_I64_POSTRA\0" |
8652 | | /* 9023 */ "ATOMIC_LOAD_MIN_I64_POSTRA\0" |
8653 | | /* 9050 */ "ATOMIC_SWAP_I64_POSTRA\0" |
8654 | | /* 9073 */ "ATOMIC_CMP_SWAP_I64_POSTRA\0" |
8655 | | /* 9100 */ "ATOMIC_LOAD_XOR_I64_POSTRA\0" |
8656 | | /* 9127 */ "ATOMIC_LOAD_OR_I64_POSTRA\0" |
8657 | | /* 9153 */ "ATOMIC_LOAD_UMAX_I64_POSTRA\0" |
8658 | | /* 9181 */ "ATOMIC_LOAD_MAX_I64_POSTRA\0" |
8659 | | /* 9208 */ "ATOMIC_LOAD_SUB_I16_POSTRA\0" |
8660 | | /* 9235 */ "ATOMIC_LOAD_ADD_I16_POSTRA\0" |
8661 | | /* 9262 */ "ATOMIC_LOAD_NAND_I16_POSTRA\0" |
8662 | | /* 9290 */ "ATOMIC_LOAD_AND_I16_POSTRA\0" |
8663 | | /* 9317 */ "ATOMIC_LOAD_UMIN_I16_POSTRA\0" |
8664 | | /* 9345 */ "ATOMIC_LOAD_MIN_I16_POSTRA\0" |
8665 | | /* 9372 */ "ATOMIC_SWAP_I16_POSTRA\0" |
8666 | | /* 9395 */ "ATOMIC_CMP_SWAP_I16_POSTRA\0" |
8667 | | /* 9422 */ "ATOMIC_LOAD_XOR_I16_POSTRA\0" |
8668 | | /* 9449 */ "ATOMIC_LOAD_OR_I16_POSTRA\0" |
8669 | | /* 9475 */ "ATOMIC_LOAD_UMAX_I16_POSTRA\0" |
8670 | | /* 9503 */ "ATOMIC_LOAD_MAX_I16_POSTRA\0" |
8671 | | /* 9530 */ "ATOMIC_LOAD_SUB_I8_POSTRA\0" |
8672 | | /* 9556 */ "ATOMIC_LOAD_ADD_I8_POSTRA\0" |
8673 | | /* 9582 */ "ATOMIC_LOAD_NAND_I8_POSTRA\0" |
8674 | | /* 9609 */ "ATOMIC_LOAD_AND_I8_POSTRA\0" |
8675 | | /* 9635 */ "ATOMIC_LOAD_UMIN_I8_POSTRA\0" |
8676 | | /* 9662 */ "ATOMIC_LOAD_MIN_I8_POSTRA\0" |
8677 | | /* 9688 */ "ATOMIC_SWAP_I8_POSTRA\0" |
8678 | | /* 9710 */ "ATOMIC_CMP_SWAP_I8_POSTRA\0" |
8679 | | /* 9736 */ "ATOMIC_LOAD_XOR_I8_POSTRA\0" |
8680 | | /* 9762 */ "ATOMIC_LOAD_OR_I8_POSTRA\0" |
8681 | | /* 9787 */ "ATOMIC_LOAD_UMAX_I8_POSTRA\0" |
8682 | | /* 9814 */ "ATOMIC_LOAD_MAX_I8_POSTRA\0" |
8683 | | /* 9840 */ "RetRA\0" |
8684 | | /* 9846 */ "DLSA\0" |
8685 | | /* 9851 */ "CFCMSA\0" |
8686 | | /* 9858 */ "CTCMSA\0" |
8687 | | /* 9865 */ "CRC32B\0" |
8688 | | /* 9872 */ "CRC32CB\0" |
8689 | | /* 9880 */ "SEB\0" |
8690 | | /* 9884 */ "EHB\0" |
8691 | | /* 9888 */ "TAILCALLREGHB\0" |
8692 | | /* 9902 */ "JR_HB\0" |
8693 | | /* 9908 */ "JALR_HB\0" |
8694 | | /* 9916 */ "LB\0" |
8695 | | /* 9919 */ "SHRA_QB\0" |
8696 | | /* 9927 */ "CMPGDU_LE_QB\0" |
8697 | | /* 9940 */ "CMPGU_LE_QB\0" |
8698 | | /* 9952 */ "PseudoCMPU_LE_QB\0" |
8699 | | /* 9969 */ "SUBUH_QB\0" |
8700 | | /* 9978 */ "ADDUH_QB\0" |
8701 | | /* 9987 */ "PseudoPICK_QB\0" |
8702 | | /* 10001 */ "SHLL_QB\0" |
8703 | | /* 10009 */ "REPL_QB\0" |
8704 | | /* 10017 */ "SHRL_QB\0" |
8705 | | /* 10025 */ "CMPGDU_EQ_QB\0" |
8706 | | /* 10038 */ "CMPGU_EQ_QB\0" |
8707 | | /* 10050 */ "PseudoCMPU_EQ_QB\0" |
8708 | | /* 10067 */ "SHRA_R_QB\0" |
8709 | | /* 10077 */ "SUBUH_R_QB\0" |
8710 | | /* 10088 */ "ADDUH_R_QB\0" |
8711 | | /* 10099 */ "SHRAV_R_QB\0" |
8712 | | /* 10110 */ "ABSQ_S_QB\0" |
8713 | | /* 10120 */ "SUBU_S_QB\0" |
8714 | | /* 10130 */ "ADDU_S_QB\0" |
8715 | | /* 10140 */ "CMPGDU_LT_QB\0" |
8716 | | /* 10153 */ "CMPGU_LT_QB\0" |
8717 | | /* 10165 */ "PseudoCMPU_LT_QB\0" |
8718 | | /* 10182 */ "SUBU_QB\0" |
8719 | | /* 10190 */ "ADDU_QB\0" |
8720 | | /* 10198 */ "SHRAV_QB\0" |
8721 | | /* 10207 */ "SHLLV_QB\0" |
8722 | | /* 10216 */ "REPLV_QB\0" |
8723 | | /* 10225 */ "SHRLV_QB\0" |
8724 | | /* 10234 */ "RADDU_W_QB\0" |
8725 | | /* 10245 */ "SB\0" |
8726 | | /* 10248 */ "MODSUB\0" |
8727 | | /* 10255 */ "G_FSUB\0" |
8728 | | /* 10262 */ "G_STRICT_FSUB\0" |
8729 | | /* 10276 */ "G_ATOMICRMW_FSUB\0" |
8730 | | /* 10293 */ "PseudoMSUB\0" |
8731 | | /* 10304 */ "G_SUB\0" |
8732 | | /* 10310 */ "G_ATOMICRMW_SUB\0" |
8733 | | /* 10326 */ "SRA_B\0" |
8734 | | /* 10332 */ "ADD_A_B\0" |
8735 | | /* 10340 */ "MIN_A_B\0" |
8736 | | /* 10348 */ "ADDS_A_B\0" |
8737 | | /* 10357 */ "MAX_A_B\0" |
8738 | | /* 10365 */ "NLOC_B\0" |
8739 | | /* 10372 */ "NLZC_B\0" |
8740 | | /* 10379 */ "SLD_B\0" |
8741 | | /* 10385 */ "PCKOD_B\0" |
8742 | | /* 10393 */ "ILVOD_B\0" |
8743 | | /* 10401 */ "INSVE_B\0" |
8744 | | /* 10409 */ "VSHF_B\0" |
8745 | | /* 10416 */ "BNEG_B\0" |
8746 | | /* 10423 */ "SRAI_B\0" |
8747 | | /* 10430 */ "SLDI_B\0" |
8748 | | /* 10437 */ "ANDI_B\0" |
8749 | | /* 10444 */ "BNEGI_B\0" |
8750 | | /* 10452 */ "BSELI_B\0" |
8751 | | /* 10460 */ "SLLI_B\0" |
8752 | | /* 10467 */ "SRLI_B\0" |
8753 | | /* 10474 */ "BINSLI_B\0" |
8754 | | /* 10483 */ "CEQI_B\0" |
8755 | | /* 10490 */ "SRARI_B\0" |
8756 | | /* 10498 */ "BCLRI_B\0" |
8757 | | /* 10506 */ "SRLRI_B\0" |
8758 | | /* 10514 */ "NORI_B\0" |
8759 | | /* 10521 */ "XORI_B\0" |
8760 | | /* 10528 */ "BINSRI_B\0" |
8761 | | /* 10537 */ "SPLATI_B\0" |
8762 | | /* 10546 */ "BSETI_B\0" |
8763 | | /* 10554 */ "SUBVI_B\0" |
8764 | | /* 10562 */ "ADDVI_B\0" |
8765 | | /* 10570 */ "BMZI_B\0" |
8766 | | /* 10577 */ "BMNZI_B\0" |
8767 | | /* 10585 */ "FILL_B\0" |
8768 | | /* 10592 */ "SLL_B\0" |
8769 | | /* 10598 */ "SRL_B\0" |
8770 | | /* 10604 */ "BINSL_B\0" |
8771 | | /* 10612 */ "ILVL_B\0" |
8772 | | /* 10619 */ "CEQ_B\0" |
8773 | | /* 10625 */ "SRAR_B\0" |
8774 | | /* 10632 */ "BCLR_B\0" |
8775 | | /* 10639 */ "SRLR_B\0" |
8776 | | /* 10646 */ "BINSR_B\0" |
8777 | | /* 10654 */ "ILVR_B\0" |
8778 | | /* 10661 */ "ASUB_S_B\0" |
8779 | | /* 10670 */ "MOD_S_B\0" |
8780 | | /* 10678 */ "CLE_S_B\0" |
8781 | | /* 10686 */ "AVE_S_B\0" |
8782 | | /* 10694 */ "CLEI_S_B\0" |
8783 | | /* 10703 */ "MINI_S_B\0" |
8784 | | /* 10712 */ "CLTI_S_B\0" |
8785 | | /* 10721 */ "MAXI_S_B\0" |
8786 | | /* 10730 */ "MIN_S_B\0" |
8787 | | /* 10738 */ "AVER_S_B\0" |
8788 | | /* 10747 */ "SUBS_S_B\0" |
8789 | | /* 10756 */ "ADDS_S_B\0" |
8790 | | /* 10765 */ "SAT_S_B\0" |
8791 | | /* 10773 */ "CLT_S_B\0" |
8792 | | /* 10781 */ "SUBSUU_S_B\0" |
8793 | | /* 10792 */ "DIV_S_B\0" |
8794 | | /* 10800 */ "MAX_S_B\0" |
8795 | | /* 10808 */ "COPY_S_B\0" |
8796 | | /* 10817 */ "SPLAT_B\0" |
8797 | | /* 10825 */ "BSET_B\0" |
8798 | | /* 10832 */ "PCNT_B\0" |
8799 | | /* 10839 */ "INSERT_B\0" |
8800 | | /* 10848 */ "ST_B\0" |
8801 | | /* 10853 */ "ASUB_U_B\0" |
8802 | | /* 10862 */ "MOD_U_B\0" |
8803 | | /* 10870 */ "CLE_U_B\0" |
8804 | | /* 10878 */ "AVE_U_B\0" |
8805 | | /* 10886 */ "CLEI_U_B\0" |
8806 | | /* 10895 */ "MINI_U_B\0" |
8807 | | /* 10904 */ "CLTI_U_B\0" |
8808 | | /* 10913 */ "MAXI_U_B\0" |
8809 | | /* 10922 */ "MIN_U_B\0" |
8810 | | /* 10930 */ "AVER_U_B\0" |
8811 | | /* 10939 */ "SUBS_U_B\0" |
8812 | | /* 10948 */ "ADDS_U_B\0" |
8813 | | /* 10957 */ "SUBSUS_U_B\0" |
8814 | | /* 10968 */ "SAT_U_B\0" |
8815 | | /* 10976 */ "CLT_U_B\0" |
8816 | | /* 10984 */ "DIV_U_B\0" |
8817 | | /* 10992 */ "MAX_U_B\0" |
8818 | | /* 11000 */ "COPY_U_B\0" |
8819 | | /* 11009 */ "MSUBV_B\0" |
8820 | | /* 11017 */ "MADDV_B\0" |
8821 | | /* 11025 */ "PCKEV_B\0" |
8822 | | /* 11033 */ "ILVEV_B\0" |
8823 | | /* 11041 */ "MULV_B\0" |
8824 | | /* 11048 */ "BZ_B\0" |
8825 | | /* 11053 */ "BNZ_B\0" |
8826 | | /* 11059 */ "BC\0" |
8827 | | /* 11062 */ "BGEC\0" |
8828 | | /* 11067 */ "BNEC\0" |
8829 | | /* 11072 */ "JIC\0" |
8830 | | /* 11076 */ "G_INTRINSIC\0" |
8831 | | /* 11088 */ "BALC\0" |
8832 | | /* 11093 */ "JIALC\0" |
8833 | | /* 11099 */ "BGEZALC\0" |
8834 | | /* 11107 */ "BLEZALC\0" |
8835 | | /* 11115 */ "BNEZALC\0" |
8836 | | /* 11123 */ "BEQZALC\0" |
8837 | | /* 11131 */ "BGTZALC\0" |
8838 | | /* 11139 */ "BLTZALC\0" |
8839 | | /* 11147 */ "ERETNC\0" |
8840 | | /* 11154 */ "G_FPTRUNC\0" |
8841 | | /* 11164 */ "G_INTRINSIC_TRUNC\0" |
8842 | | /* 11182 */ "G_TRUNC\0" |
8843 | | /* 11190 */ "G_BUILD_VECTOR_TRUNC\0" |
8844 | | /* 11211 */ "SYNC\0" |
8845 | | /* 11216 */ "G_DYN_STACKALLOC\0" |
8846 | | /* 11233 */ "LDPC\0" |
8847 | | /* 11238 */ "AUIPC\0" |
8848 | | /* 11244 */ "ALUIPC\0" |
8849 | | /* 11251 */ "ADDIUPC\0" |
8850 | | /* 11259 */ "LWUPC\0" |
8851 | | /* 11265 */ "LWPC\0" |
8852 | | /* 11270 */ "BEQC\0" |
8853 | | /* 11275 */ "ADDSC\0" |
8854 | | /* 11281 */ "BLTC\0" |
8855 | | /* 11286 */ "BGEUC\0" |
8856 | | /* 11292 */ "BLTUC\0" |
8857 | | /* 11298 */ "BNVC\0" |
8858 | | /* 11303 */ "BOVC\0" |
8859 | | /* 11308 */ "ADDWC\0" |
8860 | | /* 11314 */ "BGEZC\0" |
8861 | | /* 11320 */ "BLEZC\0" |
8862 | | /* 11326 */ "BNEZC\0" |
8863 | | /* 11332 */ "BEQZC\0" |
8864 | | /* 11338 */ "BGTZC\0" |
8865 | | /* 11344 */ "BLTZC\0" |
8866 | | /* 11350 */ "CRC32D\0" |
8867 | | /* 11357 */ "SAAD\0" |
8868 | | /* 11362 */ "G_FMAD\0" |
8869 | | /* 11369 */ "G_INDEXED_SEXTLOAD\0" |
8870 | | /* 11388 */ "G_SEXTLOAD\0" |
8871 | | /* 11399 */ "G_INDEXED_ZEXTLOAD\0" |
8872 | | /* 11418 */ "G_ZEXTLOAD\0" |
8873 | | /* 11429 */ "G_INDEXED_LOAD\0" |
8874 | | /* 11444 */ "G_LOAD\0" |
8875 | | /* 11451 */ "CRC32CD\0" |
8876 | | /* 11459 */ "SCD\0" |
8877 | | /* 11463 */ "DADD\0" |
8878 | | /* 11468 */ "G_VECREDUCE_FADD\0" |
8879 | | /* 11485 */ "G_FADD\0" |
8880 | | /* 11492 */ "G_VECREDUCE_SEQ_FADD\0" |
8881 | | /* 11513 */ "G_STRICT_FADD\0" |
8882 | | /* 11527 */ "G_ATOMICRMW_FADD\0" |
8883 | | /* 11544 */ "PseudoMADD\0" |
8884 | | /* 11555 */ "G_VECREDUCE_ADD\0" |
8885 | | /* 11571 */ "G_ADD\0" |
8886 | | /* 11577 */ "G_PTR_ADD\0" |
8887 | | /* 11587 */ "G_ATOMICRMW_ADD\0" |
8888 | | /* 11603 */ "DSHD\0" |
8889 | | /* 11608 */ "YIELD\0" |
8890 | | /* 11614 */ "LLD\0" |
8891 | | /* 11618 */ "G_ATOMICRMW_NAND\0" |
8892 | | /* 11635 */ "G_VECREDUCE_AND\0" |
8893 | | /* 11651 */ "G_AND\0" |
8894 | | /* 11657 */ "G_ATOMICRMW_AND\0" |
8895 | | /* 11673 */ "PREPEND\0" |
8896 | | /* 11681 */ "APPEND\0" |
8897 | | /* 11688 */ "LIFETIME_END\0" |
8898 | | /* 11701 */ "G_BRCOND\0" |
8899 | | /* 11710 */ "G_LLROUND\0" |
8900 | | /* 11720 */ "G_LROUND\0" |
8901 | | /* 11729 */ "G_INTRINSIC_ROUND\0" |
8902 | | /* 11747 */ "G_INTRINSIC_FPTRUNC_ROUND\0" |
8903 | | /* 11773 */ "DMOD\0" |
8904 | | /* 11778 */ "LOAD_STACK_GUARD\0" |
8905 | | /* 11795 */ "SD\0" |
8906 | | /* 11798 */ "FLOG2_D\0" |
8907 | | /* 11806 */ "FEXP2_D\0" |
8908 | | /* 11814 */ "MINA_D\0" |
8909 | | /* 11821 */ "SRA_D\0" |
8910 | | /* 11827 */ "MAXA_D\0" |
8911 | | /* 11834 */ "ADD_A_D\0" |
8912 | | /* 11842 */ "FMIN_A_D\0" |
8913 | | /* 11851 */ "ADDS_A_D\0" |
8914 | | /* 11860 */ "FMAX_A_D\0" |
8915 | | /* 11869 */ "FSUB_D\0" |
8916 | | /* 11876 */ "FMSUB_D\0" |
8917 | | /* 11884 */ "NLOC_D\0" |
8918 | | /* 11891 */ "NLZC_D\0" |
8919 | | /* 11898 */ "FADD_D\0" |
8920 | | /* 11905 */ "FMADD_D\0" |
8921 | | /* 11913 */ "SLD_D\0" |
8922 | | /* 11919 */ "PCKOD_D\0" |
8923 | | /* 11927 */ "ILVOD_D\0" |
8924 | | /* 11935 */ "FCLE_D\0" |
8925 | | /* 11942 */ "FSLE_D\0" |
8926 | | /* 11949 */ "CMP_SLE_D\0" |
8927 | | /* 11959 */ "FCULE_D\0" |
8928 | | /* 11967 */ "FSULE_D\0" |
8929 | | /* 11975 */ "CMP_SULE_D\0" |
8930 | | /* 11986 */ "CMP_ULE_D\0" |
8931 | | /* 11996 */ "CMP_LE_D\0" |
8932 | | /* 12005 */ "FCNE_D\0" |
8933 | | /* 12012 */ "FSNE_D\0" |
8934 | | /* 12019 */ "FCUNE_D\0" |
8935 | | /* 12027 */ "FSUNE_D\0" |
8936 | | /* 12035 */ "INSVE_D\0" |
8937 | | /* 12043 */ "FCAF_D\0" |
8938 | | /* 12050 */ "FSAF_D\0" |
8939 | | /* 12057 */ "CMP_SAF_D\0" |
8940 | | /* 12067 */ "MSUBF_D\0" |
8941 | | /* 12075 */ "MADDF_D\0" |
8942 | | /* 12083 */ "VSHF_D\0" |
8943 | | /* 12090 */ "CMP_F_D\0" |
8944 | | /* 12098 */ "BNEG_D\0" |
8945 | | /* 12105 */ "SRAI_D\0" |
8946 | | /* 12112 */ "SLDI_D\0" |
8947 | | /* 12119 */ "BNEGI_D\0" |
8948 | | /* 12127 */ "SLLI_D\0" |
8949 | | /* 12134 */ "SRLI_D\0" |
8950 | | /* 12141 */ "BINSLI_D\0" |
8951 | | /* 12150 */ "CEQI_D\0" |
8952 | | /* 12157 */ "SRARI_D\0" |
8953 | | /* 12165 */ "BCLRI_D\0" |
8954 | | /* 12173 */ "SRLRI_D\0" |
8955 | | /* 12181 */ "BINSRI_D\0" |
8956 | | /* 12190 */ "SPLATI_D\0" |
8957 | | /* 12199 */ "BSETI_D\0" |
8958 | | /* 12207 */ "SUBVI_D\0" |
8959 | | /* 12215 */ "ADDVI_D\0" |
8960 | | /* 12223 */ "SEL_D\0" |
8961 | | /* 12229 */ "FILL_D\0" |
8962 | | /* 12236 */ "SLL_D\0" |
8963 | | /* 12242 */ "FEXUPL_D\0" |
8964 | | /* 12251 */ "FFQL_D\0" |
8965 | | /* 12258 */ "SRL_D\0" |
8966 | | /* 12264 */ "BINSL_D\0" |
8967 | | /* 12272 */ "FMUL_D\0" |
8968 | | /* 12279 */ "ILVL_D\0" |
8969 | | /* 12286 */ "FMIN_D\0" |
8970 | | /* 12293 */ "FCUN_D\0" |
8971 | | /* 12300 */ "FSUN_D\0" |
8972 | | /* 12307 */ "CMP_SUN_D\0" |
8973 | | /* 12317 */ "CMP_UN_D\0" |
8974 | | /* 12326 */ "FRCP_D\0" |
8975 | | /* 12333 */ "FCEQ_D\0" |
8976 | | /* 12340 */ "FSEQ_D\0" |
8977 | | /* 12347 */ "CMP_SEQ_D\0" |
8978 | | /* 12357 */ "FCUEQ_D\0" |
8979 | | /* 12365 */ "FSUEQ_D\0" |
8980 | | /* 12373 */ "CMP_SUEQ_D\0" |
8981 | | /* 12384 */ "CMP_UEQ_D\0" |
8982 | | /* 12394 */ "CMP_EQ_D\0" |
8983 | | /* 12403 */ "SRAR_D\0" |
8984 | | /* 12410 */ "LDR_D\0" |
8985 | | /* 12416 */ "BCLR_D\0" |
8986 | | /* 12423 */ "SRLR_D\0" |
8987 | | /* 12430 */ "FCOR_D\0" |
8988 | | /* 12437 */ "FSOR_D\0" |
8989 | | /* 12444 */ "FEXUPR_D\0" |
8990 | | /* 12453 */ "FFQR_D\0" |
8991 | | /* 12460 */ "BINSR_D\0" |
8992 | | /* 12468 */ "STR_D\0" |
8993 | | /* 12474 */ "ILVR_D\0" |
8994 | | /* 12481 */ "FABS_D\0" |
8995 | | /* 12488 */ "FCLASS_D\0" |
8996 | | /* 12497 */ "ASUB_S_D\0" |
8997 | | /* 12506 */ "HSUB_S_D\0" |
8998 | | /* 12515 */ "DPSUB_S_D\0" |
8999 | | /* 12525 */ "FTRUNC_S_D\0" |
9000 | | /* 12536 */ "HADD_S_D\0" |
9001 | | /* 12545 */ "DPADD_S_D\0" |
9002 | | /* 12555 */ "MOD_S_D\0" |
9003 | | /* 12563 */ "CLE_S_D\0" |
9004 | | /* 12571 */ "AVE_S_D\0" |
9005 | | /* 12579 */ "CLEI_S_D\0" |
9006 | | /* 12588 */ "MINI_S_D\0" |
9007 | | /* 12597 */ "CLTI_S_D\0" |
9008 | | /* 12606 */ "MAXI_S_D\0" |
9009 | | /* 12615 */ "MIN_S_D\0" |
9010 | | /* 12623 */ "DOTP_S_D\0" |
9011 | | /* 12632 */ "AVER_S_D\0" |
9012 | | /* 12641 */ "SUBS_S_D\0" |
9013 | | /* 12650 */ "ADDS_S_D\0" |
9014 | | /* 12659 */ "SAT_S_D\0" |
9015 | | /* 12667 */ "CLT_S_D\0" |
9016 | | /* 12675 */ "FFINT_S_D\0" |
9017 | | /* 12685 */ "FTINT_S_D\0" |
9018 | | /* 12695 */ "SUBSUU_S_D\0" |
9019 | | /* 12706 */ "DIV_S_D\0" |
9020 | | /* 12714 */ "MAX_S_D\0" |
9021 | | /* 12722 */ "COPY_S_D\0" |
9022 | | /* 12731 */ "SPLAT_D\0" |
9023 | | /* 12739 */ "BSET_D\0" |
9024 | | /* 12746 */ "FCLT_D\0" |
9025 | | /* 12753 */ "FSLT_D\0" |
9026 | | /* 12760 */ "CMP_SLT_D\0" |
9027 | | /* 12770 */ "FCULT_D\0" |
9028 | | /* 12778 */ "FSULT_D\0" |
9029 | | /* 12786 */ "CMP_SULT_D\0" |
9030 | | /* 12797 */ "CMP_ULT_D\0" |
9031 | | /* 12807 */ "CMP_LT_D\0" |
9032 | | /* 12816 */ "PCNT_D\0" |
9033 | | /* 12823 */ "FRINT_D\0" |
9034 | | /* 12831 */ "INSERT_D\0" |
9035 | | /* 12840 */ "FSQRT_D\0" |
9036 | | /* 12848 */ "FRSQRT_D\0" |
9037 | | /* 12857 */ "ST_D\0" |
9038 | | /* 12862 */ "ASUB_U_D\0" |
9039 | | /* 12871 */ "HSUB_U_D\0" |
9040 | | /* 12880 */ "DPSUB_U_D\0" |
9041 | | /* 12890 */ "FTRUNC_U_D\0" |
9042 | | /* 12901 */ "HADD_U_D\0" |
9043 | | /* 12910 */ "DPADD_U_D\0" |
9044 | | /* 12920 */ "MOD_U_D\0" |
9045 | | /* 12928 */ "CLE_U_D\0" |
9046 | | /* 12936 */ "AVE_U_D\0" |
9047 | | /* 12944 */ "CLEI_U_D\0" |
9048 | | /* 12953 */ "MINI_U_D\0" |
9049 | | /* 12962 */ "CLTI_U_D\0" |
9050 | | /* 12971 */ "MAXI_U_D\0" |
9051 | | /* 12980 */ "MIN_U_D\0" |
9052 | | /* 12988 */ "DOTP_U_D\0" |
9053 | | /* 12997 */ "AVER_U_D\0" |
9054 | | /* 13006 */ "SUBS_U_D\0" |
9055 | | /* 13015 */ "ADDS_U_D\0" |
9056 | | /* 13024 */ "SUBSUS_U_D\0" |
9057 | | /* 13035 */ "SAT_U_D\0" |
9058 | | /* 13043 */ "CLT_U_D\0" |
9059 | | /* 13051 */ "FFINT_U_D\0" |
9060 | | /* 13061 */ "FTINT_U_D\0" |
9061 | | /* 13071 */ "DIV_U_D\0" |
9062 | | /* 13079 */ "MAX_U_D\0" |
9063 | | /* 13087 */ "MSUBV_D\0" |
9064 | | /* 13095 */ "MADDV_D\0" |
9065 | | /* 13103 */ "PCKEV_D\0" |
9066 | | /* 13111 */ "ILVEV_D\0" |
9067 | | /* 13119 */ "FDIV_D\0" |
9068 | | /* 13126 */ "MULV_D\0" |
9069 | | /* 13133 */ "PseudoTRUNC_W_D\0" |
9070 | | /* 13149 */ "FMAX_D\0" |
9071 | | /* 13156 */ "BZ_D\0" |
9072 | | /* 13161 */ "SELNEZ_D\0" |
9073 | | /* 13170 */ "BNZ_D\0" |
9074 | | /* 13176 */ "SELEQZ_D\0" |
9075 | | /* 13185 */ "LBE\0" |
9076 | | /* 13189 */ "PSEUDO_PROBE\0" |
9077 | | /* 13202 */ "SBE\0" |
9078 | | /* 13206 */ "G_SSUBE\0" |
9079 | | /* 13214 */ "G_USUBE\0" |
9080 | | /* 13222 */ "G_FENCE\0" |
9081 | | /* 13230 */ "ARITH_FENCE\0" |
9082 | | /* 13242 */ "REG_SEQUENCE\0" |
9083 | | /* 13255 */ "SCE\0" |
9084 | | /* 13259 */ "G_SADDE\0" |
9085 | | /* 13267 */ "G_UADDE\0" |
9086 | | /* 13275 */ "G_GET_FPMODE\0" |
9087 | | /* 13288 */ "G_RESET_FPMODE\0" |
9088 | | /* 13303 */ "G_SET_FPMODE\0" |
9089 | | /* 13316 */ "G_FMINNUM_IEEE\0" |
9090 | | /* 13331 */ "G_FMAXNUM_IEEE\0" |
9091 | | /* 13346 */ "CACHEE\0" |
9092 | | /* 13353 */ "PREFE\0" |
9093 | | /* 13359 */ "BGE\0" |
9094 | | /* 13363 */ "SGE\0" |
9095 | | /* 13367 */ "TGE\0" |
9096 | | /* 13371 */ "CACHE\0" |
9097 | | /* 13377 */ "LHE\0" |
9098 | | /* 13381 */ "SHE\0" |
9099 | | /* 13385 */ "SIGRIE\0" |
9100 | | /* 13392 */ "G_JUMP_TABLE\0" |
9101 | | /* 13405 */ "BUNDLE\0" |
9102 | | /* 13412 */ "LLE\0" |
9103 | | /* 13416 */ "SLE\0" |
9104 | | /* 13420 */ "LWLE\0" |
9105 | | /* 13425 */ "SWLE\0" |
9106 | | /* 13430 */ "BNE\0" |
9107 | | /* 13434 */ "G_MEMCPY_INLINE\0" |
9108 | | /* 13450 */ "SNE\0" |
9109 | | /* 13454 */ "TNE\0" |
9110 | | /* 13458 */ "LOCAL_ESCAPE\0" |
9111 | | /* 13471 */ "DVPE\0" |
9112 | | /* 13476 */ "EVPE\0" |
9113 | | /* 13481 */ "G_STACKRESTORE\0" |
9114 | | /* 13496 */ "G_INDEXED_STORE\0" |
9115 | | /* 13512 */ "G_STORE\0" |
9116 | | /* 13520 */ "LWRE\0" |
9117 | | /* 13525 */ "SWRE\0" |
9118 | | /* 13530 */ "G_BITREVERSE\0" |
9119 | | /* 13543 */ "PAUSE\0" |
9120 | | /* 13549 */ "DBG_VALUE\0" |
9121 | | /* 13559 */ "G_GLOBAL_VALUE\0" |
9122 | | /* 13574 */ "G_STACKSAVE\0" |
9123 | | /* 13586 */ "G_MEMMOVE\0" |
9124 | | /* 13596 */ "LWE\0" |
9125 | | /* 13600 */ "SWE\0" |
9126 | | /* 13604 */ "G_FREEZE\0" |
9127 | | /* 13613 */ "G_FCANONICALIZE\0" |
9128 | | /* 13629 */ "LBuE\0" |
9129 | | /* 13634 */ "LHuE\0" |
9130 | | /* 13639 */ "BC1F\0" |
9131 | | /* 13644 */ "G_CTLZ_ZERO_UNDEF\0" |
9132 | | /* 13662 */ "G_CTTZ_ZERO_UNDEF\0" |
9133 | | /* 13680 */ "G_IMPLICIT_DEF\0" |
9134 | | /* 13695 */ "PREF\0" |
9135 | | /* 13700 */ "DBG_INSTR_REF\0" |
9136 | | /* 13714 */ "TLBINVF\0" |
9137 | | /* 13722 */ "TLBGINVF\0" |
9138 | | /* 13731 */ "G_FNEG\0" |
9139 | | /* 13738 */ "TAILCALLHB64R6REG\0" |
9140 | | /* 13756 */ "TAILCALL64R6REG\0" |
9141 | | /* 13772 */ "TAILCALLHBR6REG\0" |
9142 | | /* 13788 */ "TAILCALLR6REG\0" |
9143 | | /* 13802 */ "EXTRACT_SUBREG\0" |
9144 | | /* 13817 */ "INSERT_SUBREG\0" |
9145 | | /* 13831 */ "TAILCALLREG\0" |
9146 | | /* 13843 */ "G_SEXT_INREG\0" |
9147 | | /* 13856 */ "SUBREG_TO_REG\0" |
9148 | | /* 13870 */ "G_ATOMIC_CMPXCHG\0" |
9149 | | /* 13887 */ "G_ATOMICRMW_XCHG\0" |
9150 | | /* 13904 */ "G_FLOG\0" |
9151 | | /* 13911 */ "G_VAARG\0" |
9152 | | /* 13919 */ "PREALLOCATED_ARG\0" |
9153 | | /* 13936 */ "CRC32H\0" |
9154 | | /* 13943 */ "DSBH\0" |
9155 | | /* 13948 */ "WSBH\0" |
9156 | | /* 13953 */ "CRC32CH\0" |
9157 | | /* 13961 */ "G_PREFETCH\0" |
9158 | | /* 13972 */ "SEH\0" |
9159 | | /* 13976 */ "G_SMULH\0" |
9160 | | /* 13984 */ "G_UMULH\0" |
9161 | | /* 13992 */ "SHRA_PH\0" |
9162 | | /* 14000 */ "PRECRQ_QB_PH\0" |
9163 | | /* 14013 */ "PRECR_QB_PH\0" |
9164 | | /* 14025 */ "PRECRQU_S_QB_PH\0" |
9165 | | /* 14041 */ "PseudoCMP_LE_PH\0" |
9166 | | /* 14057 */ "SUBQH_PH\0" |
9167 | | /* 14066 */ "ADDQH_PH\0" |
9168 | | /* 14075 */ "PseudoPICK_PH\0" |
9169 | | /* 14089 */ "SHLL_PH\0" |
9170 | | /* 14097 */ "REPL_PH\0" |
9171 | | /* 14105 */ "SHRL_PH\0" |
9172 | | /* 14113 */ "PACKRL_PH\0" |
9173 | | /* 14123 */ "MUL_PH\0" |
9174 | | /* 14130 */ "SUBQ_PH\0" |
9175 | | /* 14138 */ "ADDQ_PH\0" |
9176 | | /* 14146 */ "PseudoCMP_EQ_PH\0" |
9177 | | /* 14162 */ "SHRA_R_PH\0" |
9178 | | /* 14172 */ "SUBQH_R_PH\0" |
9179 | | /* 14183 */ "ADDQH_R_PH\0" |
9180 | | /* 14194 */ "SHRAV_R_PH\0" |
9181 | | /* 14205 */ "MULQ_RS_PH\0" |
9182 | | /* 14216 */ "SHLL_S_PH\0" |
9183 | | /* 14226 */ "MUL_S_PH\0" |
9184 | | /* 14235 */ "SUBQ_S_PH\0" |
9185 | | /* 14245 */ "ADDQ_S_PH\0" |
9186 | | /* 14255 */ "MULQ_S_PH\0" |
9187 | | /* 14265 */ "ABSQ_S_PH\0" |
9188 | | /* 14275 */ "SUBU_S_PH\0" |
9189 | | /* 14285 */ "ADDU_S_PH\0" |
9190 | | /* 14295 */ "SHLLV_S_PH\0" |
9191 | | /* 14306 */ "PseudoCMP_LT_PH\0" |
9192 | | /* 14322 */ "SUBU_PH\0" |
9193 | | /* 14330 */ "ADDU_PH\0" |
9194 | | /* 14338 */ "SHRAV_PH\0" |
9195 | | /* 14347 */ "SHLLV_PH\0" |
9196 | | /* 14356 */ "REPLV_PH\0" |
9197 | | /* 14365 */ "SHRLV_PH\0" |
9198 | | /* 14374 */ "DPA_W_PH\0" |
9199 | | /* 14383 */ "MULSA_W_PH\0" |
9200 | | /* 14394 */ "DPAQX_SA_W_PH\0" |
9201 | | /* 14408 */ "DPSQX_SA_W_PH\0" |
9202 | | /* 14422 */ "DPS_W_PH\0" |
9203 | | /* 14431 */ "DPAQ_S_W_PH\0" |
9204 | | /* 14443 */ "MULSAQ_S_W_PH\0" |
9205 | | /* 14457 */ "DPSQ_S_W_PH\0" |
9206 | | /* 14469 */ "DPAQX_S_W_PH\0" |
9207 | | /* 14482 */ "DPSQX_S_W_PH\0" |
9208 | | /* 14495 */ "DPAX_W_PH\0" |
9209 | | /* 14505 */ "DPSX_W_PH\0" |
9210 | | /* 14515 */ "SH\0" |
9211 | | /* 14518 */ "DMUH\0" |
9212 | | /* 14523 */ "SRA_H\0" |
9213 | | /* 14529 */ "ADD_A_H\0" |
9214 | | /* 14537 */ "MIN_A_H\0" |
9215 | | /* 14545 */ "ADDS_A_H\0" |
9216 | | /* 14554 */ "MAX_A_H\0" |
9217 | | /* 14562 */ "NLOC_H\0" |
9218 | | /* 14569 */ "NLZC_H\0" |
9219 | | /* 14576 */ "SLD_H\0" |
9220 | | /* 14582 */ "PCKOD_H\0" |
9221 | | /* 14590 */ "ILVOD_H\0" |
9222 | | /* 14598 */ "INSVE_H\0" |
9223 | | /* 14606 */ "VSHF_H\0" |
9224 | | /* 14613 */ "BNEG_H\0" |
9225 | | /* 14620 */ "SRAI_H\0" |
9226 | | /* 14627 */ "SLDI_H\0" |
9227 | | /* 14634 */ "BNEGI_H\0" |
9228 | | /* 14642 */ "SLLI_H\0" |
9229 | | /* 14649 */ "SRLI_H\0" |
9230 | | /* 14656 */ "BINSLI_H\0" |
9231 | | /* 14665 */ "CEQI_H\0" |
9232 | | /* 14672 */ "SRARI_H\0" |
9233 | | /* 14680 */ "BCLRI_H\0" |
9234 | | /* 14688 */ "SRLRI_H\0" |
9235 | | /* 14696 */ "BINSRI_H\0" |
9236 | | /* 14705 */ "SPLATI_H\0" |
9237 | | /* 14714 */ "BSETI_H\0" |
9238 | | /* 14722 */ "SUBVI_H\0" |
9239 | | /* 14730 */ "ADDVI_H\0" |
9240 | | /* 14738 */ "FILL_H\0" |
9241 | | /* 14745 */ "SLL_H\0" |
9242 | | /* 14751 */ "SRL_H\0" |
9243 | | /* 14757 */ "BINSL_H\0" |
9244 | | /* 14765 */ "ILVL_H\0" |
9245 | | /* 14772 */ "FEXDO_H\0" |
9246 | | /* 14780 */ "CEQ_H\0" |
9247 | | /* 14786 */ "FTQ_H\0" |
9248 | | /* 14792 */ "MSUB_Q_H\0" |
9249 | | /* 14801 */ "MADD_Q_H\0" |
9250 | | /* 14810 */ "MUL_Q_H\0" |
9251 | | /* 14818 */ "MSUBR_Q_H\0" |
9252 | | /* 14828 */ "MADDR_Q_H\0" |
9253 | | /* 14838 */ "MULR_Q_H\0" |
9254 | | /* 14847 */ "SRAR_H\0" |
9255 | | /* 14854 */ "BCLR_H\0" |
9256 | | /* 14861 */ "SRLR_H\0" |
9257 | | /* 14868 */ "BINSR_H\0" |
9258 | | /* 14876 */ "ILVR_H\0" |
9259 | | /* 14883 */ "ASUB_S_H\0" |
9260 | | /* 14892 */ "HSUB_S_H\0" |
9261 | | /* 14901 */ "DPSUB_S_H\0" |
9262 | | /* 14911 */ "HADD_S_H\0" |
9263 | | /* 14920 */ "DPADD_S_H\0" |
9264 | | /* 14930 */ "MOD_S_H\0" |
9265 | | /* 14938 */ "CLE_S_H\0" |
9266 | | /* 14946 */ "AVE_S_H\0" |
9267 | | /* 14954 */ "CLEI_S_H\0" |
9268 | | /* 14963 */ "MINI_S_H\0" |
9269 | | /* 14972 */ "CLTI_S_H\0" |
9270 | | /* 14981 */ "MAXI_S_H\0" |
9271 | | /* 14990 */ "MIN_S_H\0" |
9272 | | /* 14998 */ "DOTP_S_H\0" |
9273 | | /* 15007 */ "AVER_S_H\0" |
9274 | | /* 15016 */ "EXTR_S_H\0" |
9275 | | /* 15025 */ "SUBS_S_H\0" |
9276 | | /* 15034 */ "ADDS_S_H\0" |
9277 | | /* 15043 */ "SAT_S_H\0" |
9278 | | /* 15051 */ "CLT_S_H\0" |
9279 | | /* 15059 */ "SUBSUU_S_H\0" |
9280 | | /* 15070 */ "DIV_S_H\0" |
9281 | | /* 15078 */ "EXTRV_S_H\0" |
9282 | | /* 15088 */ "MAX_S_H\0" |
9283 | | /* 15096 */ "COPY_S_H\0" |
9284 | | /* 15105 */ "SPLAT_H\0" |
9285 | | /* 15113 */ "BSET_H\0" |
9286 | | /* 15120 */ "PCNT_H\0" |
9287 | | /* 15127 */ "INSERT_H\0" |
9288 | | /* 15136 */ "ST_H\0" |
9289 | | /* 15141 */ "ASUB_U_H\0" |
9290 | | /* 15150 */ "HSUB_U_H\0" |
9291 | | /* 15159 */ "DPSUB_U_H\0" |
9292 | | /* 15169 */ "HADD_U_H\0" |
9293 | | /* 15178 */ "DPADD_U_H\0" |
9294 | | /* 15188 */ "MOD_U_H\0" |
9295 | | /* 15196 */ "CLE_U_H\0" |
9296 | | /* 15204 */ "AVE_U_H\0" |
9297 | | /* 15212 */ "CLEI_U_H\0" |
9298 | | /* 15221 */ "MINI_U_H\0" |
9299 | | /* 15230 */ "CLTI_U_H\0" |
9300 | | /* 15239 */ "MAXI_U_H\0" |
9301 | | /* 15248 */ "MIN_U_H\0" |
9302 | | /* 15256 */ "DOTP_U_H\0" |
9303 | | /* 15265 */ "AVER_U_H\0" |
9304 | | /* 15274 */ "SUBS_U_H\0" |
9305 | | /* 15283 */ "ADDS_U_H\0" |
9306 | | /* 15292 */ "SUBSUS_U_H\0" |
9307 | | /* 15303 */ "SAT_U_H\0" |
9308 | | /* 15311 */ "CLT_U_H\0" |
9309 | | /* 15319 */ "DIV_U_H\0" |
9310 | | /* 15327 */ "MAX_U_H\0" |
9311 | | /* 15335 */ "COPY_U_H\0" |
9312 | | /* 15344 */ "MSUBV_H\0" |
9313 | | /* 15352 */ "MADDV_H\0" |
9314 | | /* 15360 */ "PCKEV_H\0" |
9315 | | /* 15368 */ "ILVEV_H\0" |
9316 | | /* 15376 */ "MULV_H\0" |
9317 | | /* 15383 */ "BZ_H\0" |
9318 | | /* 15388 */ "BNZ_H\0" |
9319 | | /* 15394 */ "SYNCI\0" |
9320 | | /* 15400 */ "DI\0" |
9321 | | /* 15403 */ "TGEI\0" |
9322 | | /* 15408 */ "TNEI\0" |
9323 | | /* 15413 */ "DAHI\0" |
9324 | | /* 15418 */ "PseudoMFHI\0" |
9325 | | /* 15429 */ "PseudoMTLOHI\0" |
9326 | | /* 15442 */ "DBG_PHI\0" |
9327 | | /* 15450 */ "MFTHI\0" |
9328 | | /* 15456 */ "MTHI\0" |
9329 | | /* 15461 */ "MTTHI\0" |
9330 | | /* 15467 */ "TEQI\0" |
9331 | | /* 15472 */ "G_FPTOSI\0" |
9332 | | /* 15481 */ "DATI\0" |
9333 | | /* 15486 */ "TLTI\0" |
9334 | | /* 15491 */ "DAUI\0" |
9335 | | /* 15496 */ "G_FPTOUI\0" |
9336 | | /* 15505 */ "GINVI\0" |
9337 | | /* 15511 */ "TLBWI\0" |
9338 | | /* 15517 */ "TLBGWI\0" |
9339 | | /* 15524 */ "G_FPOWI\0" |
9340 | | /* 15532 */ "MOVN_I64_I\0" |
9341 | | /* 15543 */ "MOVZ_I64_I\0" |
9342 | | /* 15554 */ "MOVF_I\0" |
9343 | | /* 15561 */ "PseudoSELECTFP_F_I\0" |
9344 | | /* 15580 */ "MOVN_I_I\0" |
9345 | | /* 15589 */ "MOVZ_I_I\0" |
9346 | | /* 15598 */ "PseudoD_SELECT_I\0" |
9347 | | /* 15615 */ "PseudoSELECT_I\0" |
9348 | | /* 15630 */ "MOVT_I\0" |
9349 | | /* 15637 */ "PseudoSELECTFP_T_I\0" |
9350 | | /* 15656 */ "J\0" |
9351 | | /* 15658 */ "BREAK\0" |
9352 | | /* 15664 */ "FORK\0" |
9353 | | /* 15669 */ "G_PTRMASK\0" |
9354 | | /* 15679 */ "BAL\0" |
9355 | | /* 15683 */ "JAL\0" |
9356 | | /* 15687 */ "BGEZAL\0" |
9357 | | /* 15694 */ "BLTZAL\0" |
9358 | | /* 15701 */ "MULEU_S_PH_QBL\0" |
9359 | | /* 15716 */ "PRECEU_PH_QBL\0" |
9360 | | /* 15730 */ "PRECEQU_PH_QBL\0" |
9361 | | /* 15745 */ "DPAU_H_QBL\0" |
9362 | | /* 15756 */ "DPSU_H_QBL\0" |
9363 | | /* 15767 */ "LDL\0" |
9364 | | /* 15771 */ "SDL\0" |
9365 | | /* 15775 */ "GC_LABEL\0" |
9366 | | /* 15784 */ "DBG_LABEL\0" |
9367 | | /* 15794 */ "EH_LABEL\0" |
9368 | | /* 15803 */ "ANNOTATION_LABEL\0" |
9369 | | /* 15820 */ "BGEL\0" |
9370 | | /* 15825 */ "BLEL\0" |
9371 | | /* 15830 */ "BNEL\0" |
9372 | | /* 15835 */ "ICALL_BRANCH_FUNNEL\0" |
9373 | | /* 15855 */ "BC1FL\0" |
9374 | | /* 15861 */ "MAQ_SA_W_PHL\0" |
9375 | | /* 15874 */ "PRECEQ_W_PHL\0" |
9376 | | /* 15887 */ "MAQ_S_W_PHL\0" |
9377 | | /* 15899 */ "MULEQ_S_W_PHL\0" |
9378 | | /* 15913 */ "G_FSHL\0" |
9379 | | /* 15920 */ "G_SHL\0" |
9380 | | /* 15926 */ "G_FCEIL\0" |
9381 | | /* 15934 */ "TAILCALL\0" |
9382 | | /* 15943 */ "HYPCALL\0" |
9383 | | /* 15951 */ "SYSCALL\0" |
9384 | | /* 15959 */ "PATCHABLE_TAIL_CALL\0" |
9385 | | /* 15979 */ "PATCHABLE_TYPED_EVENT_CALL\0" |
9386 | | /* 16006 */ "PATCHABLE_EVENT_CALL\0" |
9387 | | /* 16027 */ "FENTRY_CALL\0" |
9388 | | /* 16039 */ "BGEZALL\0" |
9389 | | /* 16047 */ "BLTZALL\0" |
9390 | | /* 16055 */ "KILL\0" |
9391 | | /* 16060 */ "DSLL\0" |
9392 | | /* 16065 */ "G_CONSTANT_POOL\0" |
9393 | | /* 16081 */ "DROL\0" |
9394 | | /* 16086 */ "BEQL\0" |
9395 | | /* 16091 */ "DSRL\0" |
9396 | | /* 16096 */ "BC1TL\0" |
9397 | | /* 16102 */ "BGTL\0" |
9398 | | /* 16107 */ "BLTL\0" |
9399 | | /* 16112 */ "G_ROTL\0" |
9400 | | /* 16119 */ "BGEUL\0" |
9401 | | /* 16125 */ "BLEUL\0" |
9402 | | /* 16131 */ "DMUL\0" |
9403 | | /* 16136 */ "G_VECREDUCE_FMUL\0" |
9404 | | /* 16153 */ "G_FMUL\0" |
9405 | | /* 16160 */ "G_VECREDUCE_SEQ_FMUL\0" |
9406 | | /* 16181 */ "G_STRICT_FMUL\0" |
9407 | | /* 16195 */ "G_VECREDUCE_MUL\0" |
9408 | | /* 16211 */ "G_MUL\0" |
9409 | | /* 16217 */ "BGTUL\0" |
9410 | | /* 16223 */ "BLTUL\0" |
9411 | | /* 16229 */ "LWL\0" |
9412 | | /* 16233 */ "SWL\0" |
9413 | | /* 16237 */ "BGEZL\0" |
9414 | | /* 16243 */ "BLEZL\0" |
9415 | | /* 16249 */ "BGTZL\0" |
9416 | | /* 16255 */ "BLTZL\0" |
9417 | | /* 16261 */ "PseudoCVT_D64_L\0" |
9418 | | /* 16277 */ "PseudoCVT_S_L\0" |
9419 | | /* 16291 */ "G_FREM\0" |
9420 | | /* 16298 */ "G_STRICT_FREM\0" |
9421 | | /* 16312 */ "G_SREM\0" |
9422 | | /* 16319 */ "G_UREM\0" |
9423 | | /* 16326 */ "G_SDIVREM\0" |
9424 | | /* 16336 */ "G_UDIVREM\0" |
9425 | | /* 16346 */ "MFGC0_MM\0" |
9426 | | /* 16355 */ "MFHGC0_MM\0" |
9427 | | /* 16365 */ "MTHGC0_MM\0" |
9428 | | /* 16375 */ "MTGC0_MM\0" |
9429 | | /* 16384 */ "CFC1_MM\0" |
9430 | | /* 16392 */ "MFC1_MM\0" |
9431 | | /* 16400 */ "CTC1_MM\0" |
9432 | | /* 16408 */ "MTC1_MM\0" |
9433 | | /* 16416 */ "LWC1_MM\0" |
9434 | | /* 16424 */ "SWC1_MM\0" |
9435 | | /* 16432 */ "LUXC1_MM\0" |
9436 | | /* 16441 */ "SUXC1_MM\0" |
9437 | | /* 16450 */ "LWXC1_MM\0" |
9438 | | /* 16459 */ "SWXC1_MM\0" |
9439 | | /* 16468 */ "MFHC1_D32_MM\0" |
9440 | | /* 16481 */ "MTHC1_D32_MM\0" |
9441 | | /* 16494 */ "FSUB_D32_MM\0" |
9442 | | /* 16506 */ "NMSUB_D32_MM\0" |
9443 | | /* 16519 */ "FADD_D32_MM\0" |
9444 | | /* 16531 */ "NMADD_D32_MM\0" |
9445 | | /* 16544 */ "C_NGE_D32_MM\0" |
9446 | | /* 16557 */ "C_NGLE_D32_MM\0" |
9447 | | /* 16571 */ "C_OLE_D32_MM\0" |
9448 | | /* 16584 */ "C_ULE_D32_MM\0" |
9449 | | /* 16597 */ "C_LE_D32_MM\0" |
9450 | | /* 16609 */ "C_SF_D32_MM\0" |
9451 | | /* 16621 */ "MOVF_D32_MM\0" |
9452 | | /* 16633 */ "C_F_D32_MM\0" |
9453 | | /* 16644 */ "FNEG_D32_MM\0" |
9454 | | /* 16656 */ "MOVN_I_D32_MM\0" |
9455 | | /* 16670 */ "MOVZ_I_D32_MM\0" |
9456 | | /* 16684 */ "C_NGL_D32_MM\0" |
9457 | | /* 16697 */ "FMUL_D32_MM\0" |
9458 | | /* 16709 */ "C_UN_D32_MM\0" |
9459 | | /* 16721 */ "RECIP_D32_MM\0" |
9460 | | /* 16734 */ "FCMP_D32_MM\0" |
9461 | | /* 16746 */ "C_SEQ_D32_MM\0" |
9462 | | /* 16759 */ "C_UEQ_D32_MM\0" |
9463 | | /* 16772 */ "C_EQ_D32_MM\0" |
9464 | | /* 16784 */ "FABS_D32_MM\0" |
9465 | | /* 16796 */ "CVT_S_D32_MM\0" |
9466 | | /* 16809 */ "C_NGT_D32_MM\0" |
9467 | | /* 16822 */ "C_OLT_D32_MM\0" |
9468 | | /* 16835 */ "C_ULT_D32_MM\0" |
9469 | | /* 16848 */ "C_LT_D32_MM\0" |
9470 | | /* 16860 */ "FSQRT_D32_MM\0" |
9471 | | /* 16873 */ "RSQRT_D32_MM\0" |
9472 | | /* 16886 */ "MOVT_D32_MM\0" |
9473 | | /* 16898 */ "FDIV_D32_MM\0" |
9474 | | /* 16910 */ "FMOV_D32_MM\0" |
9475 | | /* 16922 */ "CVT_W_D32_MM\0" |
9476 | | /* 16935 */ "BPOSGE32_MM\0" |
9477 | | /* 16947 */ "LWM32_MM\0" |
9478 | | /* 16956 */ "SWM32_MM\0" |
9479 | | /* 16965 */ "FCMP_S32_MM\0" |
9480 | | /* 16977 */ "CFC2_MM\0" |
9481 | | /* 16985 */ "CTC2_MM\0" |
9482 | | /* 16993 */ "ADDIUR2_MM\0" |
9483 | | /* 17004 */ "MFHC1_D64_MM\0" |
9484 | | /* 17017 */ "MTHC1_D64_MM\0" |
9485 | | /* 17030 */ "MTC1_D64_MM\0" |
9486 | | /* 17042 */ "FSUB_D64_MM\0" |
9487 | | /* 17054 */ "FADD_D64_MM\0" |
9488 | | /* 17066 */ "C_NGE_D64_MM\0" |
9489 | | /* 17079 */ "C_NGLE_D64_MM\0" |
9490 | | /* 17093 */ "C_OLE_D64_MM\0" |
9491 | | /* 17106 */ "C_ULE_D64_MM\0" |
9492 | | /* 17119 */ "C_LE_D64_MM\0" |
9493 | | /* 17131 */ "C_SF_D64_MM\0" |
9494 | | /* 17143 */ "C_F_D64_MM\0" |
9495 | | /* 17154 */ "FNEG_D64_MM\0" |
9496 | | /* 17166 */ "C_NGL_D64_MM\0" |
9497 | | /* 17179 */ "FMUL_D64_MM\0" |
9498 | | /* 17191 */ "CVT_L_D64_MM\0" |
9499 | | /* 17204 */ "C_UN_D64_MM\0" |
9500 | | /* 17216 */ "RECIP_D64_MM\0" |
9501 | | /* 17229 */ "C_SEQ_D64_MM\0" |
9502 | | /* 17242 */ "C_UEQ_D64_MM\0" |
9503 | | /* 17255 */ "C_EQ_D64_MM\0" |
9504 | | /* 17267 */ "FABS_D64_MM\0" |
9505 | | /* 17279 */ "CVT_S_D64_MM\0" |
9506 | | /* 17292 */ "C_NGT_D64_MM\0" |
9507 | | /* 17305 */ "C_OLT_D64_MM\0" |
9508 | | /* 17318 */ "C_ULT_D64_MM\0" |
9509 | | /* 17331 */ "C_LT_D64_MM\0" |
9510 | | /* 17343 */ "FSQRT_D64_MM\0" |
9511 | | /* 17356 */ "RSQRT_D64_MM\0" |
9512 | | /* 17369 */ "FDIV_D64_MM\0" |
9513 | | /* 17381 */ "FMOV_D64_MM\0" |
9514 | | /* 17393 */ "CVT_W_D64_MM\0" |
9515 | | /* 17406 */ "ADDIUS5_MM\0" |
9516 | | /* 17417 */ "SB16_MM\0" |
9517 | | /* 17425 */ "JRC16_MM\0" |
9518 | | /* 17434 */ "AND16_MM\0" |
9519 | | /* 17443 */ "MOVE16_MM\0" |
9520 | | /* 17453 */ "SH16_MM\0" |
9521 | | /* 17461 */ "ANDI16_MM\0" |
9522 | | /* 17471 */ "MFHI16_MM\0" |
9523 | | /* 17481 */ "LI16_MM\0" |
9524 | | /* 17489 */ "BREAK16_MM\0" |
9525 | | /* 17500 */ "SLL16_MM\0" |
9526 | | /* 17509 */ "SRL16_MM\0" |
9527 | | /* 17518 */ "LWM16_MM\0" |
9528 | | /* 17527 */ "SWM16_MM\0" |
9529 | | /* 17536 */ "MFLO16_MM\0" |
9530 | | /* 17546 */ "SDBBP16_MM\0" |
9531 | | /* 17557 */ "JR16_MM\0" |
9532 | | /* 17565 */ "JALR16_MM\0" |
9533 | | /* 17575 */ "XOR16_MM\0" |
9534 | | /* 17584 */ "JALRS16_MM\0" |
9535 | | /* 17595 */ "NOT16_MM\0" |
9536 | | /* 17604 */ "LBU16_MM\0" |
9537 | | /* 17613 */ "SUBU16_MM\0" |
9538 | | /* 17623 */ "ADDU16_MM\0" |
9539 | | /* 17633 */ "LHU16_MM\0" |
9540 | | /* 17642 */ "LW16_MM\0" |
9541 | | /* 17650 */ "SW16_MM\0" |
9542 | | /* 17658 */ "BNEZ16_MM\0" |
9543 | | /* 17668 */ "BEQZ16_MM\0" |
9544 | | /* 17678 */ "PRECEU_PH_QBLA_MM\0" |
9545 | | /* 17696 */ "PRECEQU_PH_QBLA_MM\0" |
9546 | | /* 17715 */ "PRECEU_PH_QBRA_MM\0" |
9547 | | /* 17733 */ "PRECEQU_PH_QBRA_MM\0" |
9548 | | /* 17752 */ "SRA_MM\0" |
9549 | | /* 17759 */ "SEB_MM\0" |
9550 | | /* 17766 */ "EHB_MM\0" |
9551 | | /* 17773 */ "LB_MM\0" |
9552 | | /* 17779 */ "CMPGU_LE_QB_MM\0" |
9553 | | /* 17794 */ "CMPU_LE_QB_MM\0" |
9554 | | /* 17808 */ "PICK_QB_MM\0" |
9555 | | /* 17819 */ "SHLL_QB_MM\0" |
9556 | | /* 17830 */ "REPL_QB_MM\0" |
9557 | | /* 17841 */ "SHRL_QB_MM\0" |
9558 | | /* 17852 */ "CMPGU_EQ_QB_MM\0" |
9559 | | /* 17867 */ "CMPU_EQ_QB_MM\0" |
9560 | | /* 17881 */ "SUBU_S_QB_MM\0" |
9561 | | /* 17894 */ "ADDU_S_QB_MM\0" |
9562 | | /* 17907 */ "CMPGU_LT_QB_MM\0" |
9563 | | /* 17922 */ "CMPU_LT_QB_MM\0" |
9564 | | /* 17936 */ "SUBU_QB_MM\0" |
9565 | | /* 17947 */ "ADDU_QB_MM\0" |
9566 | | /* 17958 */ "SHLLV_QB_MM\0" |
9567 | | /* 17970 */ "REPLV_QB_MM\0" |
9568 | | /* 17982 */ "SHRLV_QB_MM\0" |
9569 | | /* 17994 */ "RADDU_W_QB_MM\0" |
9570 | | /* 18008 */ "SB_MM\0" |
9571 | | /* 18014 */ "MODSUB_MM\0" |
9572 | | /* 18024 */ "PseudoMSUB_MM\0" |
9573 | | /* 18038 */ "SYNC_MM\0" |
9574 | | /* 18046 */ "ADDIUPC_MM\0" |
9575 | | /* 18057 */ "ADDSC_MM\0" |
9576 | | /* 18066 */ "ADDWC_MM\0" |
9577 | | /* 18075 */ "BNEZC_MM\0" |
9578 | | /* 18084 */ "BEQZC_MM\0" |
9579 | | /* 18093 */ "PseudoMADD_MM\0" |
9580 | | /* 18107 */ "AND_MM\0" |
9581 | | /* 18114 */ "LBE_MM\0" |
9582 | | /* 18121 */ "SBE_MM\0" |
9583 | | /* 18128 */ "SCE_MM\0" |
9584 | | /* 18135 */ "CACHEE_MM\0" |
9585 | | /* 18145 */ "PREFE_MM\0" |
9586 | | /* 18154 */ "TGE_MM\0" |
9587 | | /* 18161 */ "CACHE_MM\0" |
9588 | | /* 18170 */ "LHE_MM\0" |
9589 | | /* 18177 */ "SHE_MM\0" |
9590 | | /* 18184 */ "LLE_MM\0" |
9591 | | /* 18191 */ "LWLE_MM\0" |
9592 | | /* 18199 */ "SWLE_MM\0" |
9593 | | /* 18207 */ "BNE_MM\0" |
9594 | | /* 18214 */ "TNE_MM\0" |
9595 | | /* 18221 */ "LWRE_MM\0" |
9596 | | /* 18229 */ "SWRE_MM\0" |
9597 | | /* 18237 */ "PAUSE_MM\0" |
9598 | | /* 18246 */ "LWE_MM\0" |
9599 | | /* 18253 */ "SWE_MM\0" |
9600 | | /* 18260 */ "LBuE_MM\0" |
9601 | | /* 18268 */ "LHuE_MM\0" |
9602 | | /* 18276 */ "BC1F_MM\0" |
9603 | | /* 18284 */ "PREF_MM\0" |
9604 | | /* 18292 */ "TLBGINVF_MM\0" |
9605 | | /* 18304 */ "TAILCALLREG_MM\0" |
9606 | | /* 18319 */ "WSBH_MM\0" |
9607 | | /* 18327 */ "SEH_MM\0" |
9608 | | /* 18334 */ "LH_MM\0" |
9609 | | /* 18340 */ "SHRA_PH_MM\0" |
9610 | | /* 18351 */ "PRECRQ_QB_PH_MM\0" |
9611 | | /* 18367 */ "PRECRQU_S_QB_PH_MM\0" |
9612 | | /* 18386 */ "CMP_LE_PH_MM\0" |
9613 | | /* 18399 */ "PICK_PH_MM\0" |
9614 | | /* 18410 */ "SHLL_PH_MM\0" |
9615 | | /* 18421 */ "REPL_PH_MM\0" |
9616 | | /* 18432 */ "PACKRL_PH_MM\0" |
9617 | | /* 18445 */ "SUBQ_PH_MM\0" |
9618 | | /* 18456 */ "ADDQ_PH_MM\0" |
9619 | | /* 18467 */ "CMP_EQ_PH_MM\0" |
9620 | | /* 18480 */ "SHRA_R_PH_MM\0" |
9621 | | /* 18493 */ "SHRAV_R_PH_MM\0" |
9622 | | /* 18507 */ "MULQ_RS_PH_MM\0" |
9623 | | /* 18521 */ "SHLL_S_PH_MM\0" |
9624 | | /* 18534 */ "SUBQ_S_PH_MM\0" |
9625 | | /* 18547 */ "ADDQ_S_PH_MM\0" |
9626 | | /* 18560 */ "ABSQ_S_PH_MM\0" |
9627 | | /* 18573 */ "SHLLV_S_PH_MM\0" |
9628 | | /* 18587 */ "CMP_LT_PH_MM\0" |
9629 | | /* 18600 */ "SHRAV_PH_MM\0" |
9630 | | /* 18612 */ "SHLLV_PH_MM\0" |
9631 | | /* 18624 */ "REPLV_PH_MM\0" |
9632 | | /* 18636 */ "DPAQ_S_W_PH_MM\0" |
9633 | | /* 18651 */ "MULSAQ_S_W_PH_MM\0" |
9634 | | /* 18668 */ "DPSQ_S_W_PH_MM\0" |
9635 | | /* 18683 */ "SH_MM\0" |
9636 | | /* 18689 */ "EXTR_S_H_MM\0" |
9637 | | /* 18701 */ "EXTRV_S_H_MM\0" |
9638 | | /* 18714 */ "SYNCI_MM\0" |
9639 | | /* 18723 */ "DI_MM\0" |
9640 | | /* 18729 */ "TGEI_MM\0" |
9641 | | /* 18737 */ "TNEI_MM\0" |
9642 | | /* 18745 */ "PseudoMFHI_MM\0" |
9643 | | /* 18759 */ "PseudoMTLOHI_MM\0" |
9644 | | /* 18775 */ "MTHI_MM\0" |
9645 | | /* 18783 */ "TEQI_MM\0" |
9646 | | /* 18791 */ "TLTI_MM\0" |
9647 | | /* 18799 */ "TLBWI_MM\0" |
9648 | | /* 18808 */ "TLBGWI_MM\0" |
9649 | | /* 18818 */ "MOVF_I_MM\0" |
9650 | | /* 18828 */ "MOVN_I_MM\0" |
9651 | | /* 18838 */ "MOVT_I_MM\0" |
9652 | | /* 18848 */ "MOVZ_I_MM\0" |
9653 | | /* 18858 */ "J_MM\0" |
9654 | | /* 18863 */ "BREAK_MM\0" |
9655 | | /* 18872 */ "JAL_MM\0" |
9656 | | /* 18879 */ "BGEZAL_MM\0" |
9657 | | /* 18889 */ "BLTZAL_MM\0" |
9658 | | /* 18899 */ "MULEU_S_PH_QBL_MM\0" |
9659 | | /* 18917 */ "PRECEU_PH_QBL_MM\0" |
9660 | | /* 18934 */ "PRECEQU_PH_QBL_MM\0" |
9661 | | /* 18952 */ "DPAU_H_QBL_MM\0" |
9662 | | /* 18966 */ "DPSU_H_QBL_MM\0" |
9663 | | /* 18980 */ "MAQ_SA_W_PHL_MM\0" |
9664 | | /* 18996 */ "PRECEQ_W_PHL_MM\0" |
9665 | | /* 19012 */ "MAQ_S_W_PHL_MM\0" |
9666 | | /* 19027 */ "MULEQ_S_W_PHL_MM\0" |
9667 | | /* 19044 */ "TAILCALL_MM\0" |
9668 | | /* 19056 */ "HYPCALL_MM\0" |
9669 | | /* 19067 */ "SYSCALL_MM\0" |
9670 | | /* 19078 */ "SLL_MM\0" |
9671 | | /* 19085 */ "SRL_MM\0" |
9672 | | /* 19092 */ "MUL_MM\0" |
9673 | | /* 19099 */ "LWL_MM\0" |
9674 | | /* 19106 */ "SWL_MM\0" |
9675 | | /* 19113 */ "LWM_MM\0" |
9676 | | /* 19120 */ "SWM_MM\0" |
9677 | | /* 19127 */ "CLO_MM\0" |
9678 | | /* 19134 */ "PseudoMFLO_MM\0" |
9679 | | /* 19148 */ "SHILO_MM\0" |
9680 | | /* 19157 */ "MTLO_MM\0" |
9681 | | /* 19165 */ "TRAP_MM\0" |
9682 | | /* 19173 */ "SDBBP_MM\0" |
9683 | | /* 19182 */ "TLBP_MM\0" |
9684 | | /* 19190 */ "EXTPDP_MM\0" |
9685 | | /* 19200 */ "MOVEP_MM\0" |
9686 | | /* 19209 */ "TLBGP_MM\0" |
9687 | | /* 19218 */ "LWGP_MM\0" |
9688 | | /* 19226 */ "MTHLIP_MM\0" |
9689 | | /* 19236 */ "SSNOP_MM\0" |
9690 | | /* 19245 */ "ADDIUR1SP_MM\0" |
9691 | | /* 19258 */ "RDDSP_MM\0" |
9692 | | /* 19267 */ "WRDSP_MM\0" |
9693 | | /* 19276 */ "LWDSP_MM\0" |
9694 | | /* 19285 */ "SWDSP_MM\0" |
9695 | | /* 19294 */ "MSUB_DSP_MM\0" |
9696 | | /* 19306 */ "MADD_DSP_MM\0" |
9697 | | /* 19318 */ "MFHI_DSP_MM\0" |
9698 | | /* 19330 */ "MTHI_DSP_MM\0" |
9699 | | /* 19342 */ "MFLO_DSP_MM\0" |
9700 | | /* 19354 */ "MTLO_DSP_MM\0" |
9701 | | /* 19366 */ "MULT_DSP_MM\0" |
9702 | | /* 19378 */ "MSUBU_DSP_MM\0" |
9703 | | /* 19391 */ "MADDU_DSP_MM\0" |
9704 | | /* 19404 */ "MULTU_DSP_MM\0" |
9705 | | /* 19417 */ "ADDIUSP_MM\0" |
9706 | | /* 19428 */ "LWSP_MM\0" |
9707 | | /* 19436 */ "SWSP_MM\0" |
9708 | | /* 19444 */ "EXTP_MM\0" |
9709 | | /* 19452 */ "LWP_MM\0" |
9710 | | /* 19459 */ "SWP_MM\0" |
9711 | | /* 19466 */ "BEQ_MM\0" |
9712 | | /* 19473 */ "TEQ_MM\0" |
9713 | | /* 19480 */ "TLBR_MM\0" |
9714 | | /* 19488 */ "MULEU_S_PH_QBR_MM\0" |
9715 | | /* 19506 */ "PRECEU_PH_QBR_MM\0" |
9716 | | /* 19523 */ "PRECEQU_PH_QBR_MM\0" |
9717 | | /* 19541 */ "DPAU_H_QBR_MM\0" |
9718 | | /* 19555 */ "DPSU_H_QBR_MM\0" |
9719 | | /* 19569 */ "BAL_BR_MM\0" |
9720 | | /* 19579 */ "TLBGR_MM\0" |
9721 | | /* 19588 */ "MAQ_SA_W_PHR_MM\0" |
9722 | | /* 19604 */ "PRECEQ_W_PHR_MM\0" |
9723 | | /* 19620 */ "MAQ_S_W_PHR_MM\0" |
9724 | | /* 19635 */ "MULEQ_S_W_PHR_MM\0" |
9725 | | /* 19652 */ "JR_MM\0" |
9726 | | /* 19658 */ "JALR_MM\0" |
9727 | | /* 19666 */ "NOR_MM\0" |
9728 | | /* 19673 */ "XOR_MM\0" |
9729 | | /* 19680 */ "ROTR_MM\0" |
9730 | | /* 19688 */ "TLBWR_MM\0" |
9731 | | /* 19697 */ "TLBGWR_MM\0" |
9732 | | /* 19707 */ "RDHWR_MM\0" |
9733 | | /* 19716 */ "LWR_MM\0" |
9734 | | /* 19723 */ "SWR_MM\0" |
9735 | | /* 19730 */ "JALS_MM\0" |
9736 | | /* 19738 */ "BGEZALS_MM\0" |
9737 | | /* 19749 */ "BLTZALS_MM\0" |
9738 | | /* 19760 */ "INS_MM\0" |
9739 | | /* 19767 */ "JALRS_MM\0" |
9740 | | /* 19776 */ "LWXS_MM\0" |
9741 | | /* 19784 */ "CVT_D32_S_MM\0" |
9742 | | /* 19797 */ "CVT_D64_S_MM\0" |
9743 | | /* 19810 */ "FSUB_S_MM\0" |
9744 | | /* 19820 */ "NMSUB_S_MM\0" |
9745 | | /* 19831 */ "FADD_S_MM\0" |
9746 | | /* 19841 */ "NMADD_S_MM\0" |
9747 | | /* 19852 */ "C_NGE_S_MM\0" |
9748 | | /* 19863 */ "C_NGLE_S_MM\0" |
9749 | | /* 19875 */ "C_OLE_S_MM\0" |
9750 | | /* 19886 */ "C_ULE_S_MM\0" |
9751 | | /* 19897 */ "C_LE_S_MM\0" |
9752 | | /* 19907 */ "C_SF_S_MM\0" |
9753 | | /* 19917 */ "MOVF_S_MM\0" |
9754 | | /* 19927 */ "C_F_S_MM\0" |
9755 | | /* 19936 */ "FNEG_S_MM\0" |
9756 | | /* 19946 */ "MOVN_I_S_MM\0" |
9757 | | /* 19958 */ "MOVZ_I_S_MM\0" |
9758 | | /* 19970 */ "C_NGL_S_MM\0" |
9759 | | /* 19981 */ "FMUL_S_MM\0" |
9760 | | /* 19991 */ "CVT_L_S_MM\0" |
9761 | | /* 20002 */ "C_UN_S_MM\0" |
9762 | | /* 20012 */ "RECIP_S_MM\0" |
9763 | | /* 20023 */ "C_SEQ_S_MM\0" |
9764 | | /* 20034 */ "C_UEQ_S_MM\0" |
9765 | | /* 20045 */ "C_EQ_S_MM\0" |
9766 | | /* 20055 */ "FABS_S_MM\0" |
9767 | | /* 20065 */ "C_NGT_S_MM\0" |
9768 | | /* 20076 */ "C_OLT_S_MM\0" |
9769 | | /* 20087 */ "C_ULT_S_MM\0" |
9770 | | /* 20098 */ "C_LT_S_MM\0" |
9771 | | /* 20108 */ "FSQRT_S_MM\0" |
9772 | | /* 20119 */ "RSQRT_S_MM\0" |
9773 | | /* 20130 */ "MOVT_S_MM\0" |
9774 | | /* 20140 */ "FDIV_S_MM\0" |
9775 | | /* 20150 */ "FMOV_S_MM\0" |
9776 | | /* 20160 */ "TRUNC_W_S_MM\0" |
9777 | | /* 20173 */ "ROUND_W_S_MM\0" |
9778 | | /* 20186 */ "CEIL_W_S_MM\0" |
9779 | | /* 20198 */ "FLOOR_W_S_MM\0" |
9780 | | /* 20211 */ "CVT_W_S_MM\0" |
9781 | | /* 20222 */ "BC1T_MM\0" |
9782 | | /* 20230 */ "DERET_MM\0" |
9783 | | /* 20239 */ "WAIT_MM\0" |
9784 | | /* 20247 */ "SLT_MM\0" |
9785 | | /* 20254 */ "TLT_MM\0" |
9786 | | /* 20261 */ "PseudoMULT_MM\0" |
9787 | | /* 20275 */ "EXT_MM\0" |
9788 | | /* 20282 */ "PseudoMSUBU_MM\0" |
9789 | | /* 20297 */ "PseudoMADDU_MM\0" |
9790 | | /* 20312 */ "TGEU_MM\0" |
9791 | | /* 20320 */ "TGEIU_MM\0" |
9792 | | /* 20329 */ "TLTIU_MM\0" |
9793 | | /* 20338 */ "TLTU_MM\0" |
9794 | | /* 20346 */ "LWU_MM\0" |
9795 | | /* 20353 */ "SRAV_MM\0" |
9796 | | /* 20361 */ "BITREV_MM\0" |
9797 | | /* 20371 */ "SDIV_MM\0" |
9798 | | /* 20379 */ "UDIV_MM\0" |
9799 | | /* 20387 */ "SLLV_MM\0" |
9800 | | /* 20395 */ "SRLV_MM\0" |
9801 | | /* 20403 */ "TLBGINV_MM\0" |
9802 | | /* 20414 */ "SHILOV_MM\0" |
9803 | | /* 20424 */ "EXTPDPV_MM\0" |
9804 | | /* 20435 */ "EXTPV_MM\0" |
9805 | | /* 20444 */ "ROTRV_MM\0" |
9806 | | /* 20453 */ "INSV_MM\0" |
9807 | | /* 20461 */ "LW_MM\0" |
9808 | | /* 20467 */ "SW_MM\0" |
9809 | | /* 20473 */ "CVT_D32_W_MM\0" |
9810 | | /* 20486 */ "CVT_D64_W_MM\0" |
9811 | | /* 20499 */ "TRUNC_W_MM\0" |
9812 | | /* 20510 */ "ROUND_W_MM\0" |
9813 | | /* 20521 */ "PRECRQ_PH_W_MM\0" |
9814 | | /* 20536 */ "PRECRQ_RS_PH_W_MM\0" |
9815 | | /* 20554 */ "CEIL_W_MM\0" |
9816 | | /* 20564 */ "DPAQ_SA_L_W_MM\0" |
9817 | | /* 20579 */ "DPSQ_SA_L_W_MM\0" |
9818 | | /* 20594 */ "FLOOR_W_MM\0" |
9819 | | /* 20605 */ "EXTR_W_MM\0" |
9820 | | /* 20615 */ "SHRA_R_W_MM\0" |
9821 | | /* 20627 */ "EXTR_R_W_MM\0" |
9822 | | /* 20639 */ "SHRAV_R_W_MM\0" |
9823 | | /* 20652 */ "EXTRV_R_W_MM\0" |
9824 | | /* 20665 */ "EXTR_RS_W_MM\0" |
9825 | | /* 20678 */ "EXTRV_RS_W_MM\0" |
9826 | | /* 20692 */ "SHLL_S_W_MM\0" |
9827 | | /* 20704 */ "SUBQ_S_W_MM\0" |
9828 | | /* 20716 */ "ADDQ_S_W_MM\0" |
9829 | | /* 20728 */ "ABSQ_S_W_MM\0" |
9830 | | /* 20740 */ "CVT_S_W_MM\0" |
9831 | | /* 20751 */ "SHLLV_S_W_MM\0" |
9832 | | /* 20764 */ "EXTRV_W_MM\0" |
9833 | | /* 20775 */ "PREFX_MM\0" |
9834 | | /* 20784 */ "LHX_MM\0" |
9835 | | /* 20791 */ "JALX_MM\0" |
9836 | | /* 20799 */ "LBUX_MM\0" |
9837 | | /* 20807 */ "LWX_MM\0" |
9838 | | /* 20814 */ "BGEZ_MM\0" |
9839 | | /* 20822 */ "BLEZ_MM\0" |
9840 | | /* 20830 */ "CLZ_MM\0" |
9841 | | /* 20837 */ "BGTZ_MM\0" |
9842 | | /* 20845 */ "BLTZ_MM\0" |
9843 | | /* 20853 */ "PseudoIndirectBranch_MM\0" |
9844 | | /* 20877 */ "ADDi_MM\0" |
9845 | | /* 20885 */ "ANDi_MM\0" |
9846 | | /* 20893 */ "XORi_MM\0" |
9847 | | /* 20901 */ "SLTi_MM\0" |
9848 | | /* 20909 */ "LUi_MM\0" |
9849 | | /* 20916 */ "LBu_MM\0" |
9850 | | /* 20923 */ "SUBu_MM\0" |
9851 | | /* 20931 */ "ADDu_MM\0" |
9852 | | /* 20939 */ "LHu_MM\0" |
9853 | | /* 20946 */ "SLTu_MM\0" |
9854 | | /* 20954 */ "PseudoMULTu_MM\0" |
9855 | | /* 20969 */ "LEA_ADDiu_MM\0" |
9856 | | /* 20982 */ "SLTiu_MM\0" |
9857 | | /* 20991 */ "INLINEASM\0" |
9858 | | /* 21001 */ "DINSM\0" |
9859 | | /* 21007 */ "DEXTM\0" |
9860 | | /* 21013 */ "G_VECREDUCE_FMINIMUM\0" |
9861 | | /* 21034 */ "G_FMINIMUM\0" |
9862 | | /* 21045 */ "G_VECREDUCE_FMAXIMUM\0" |
9863 | | /* 21066 */ "G_FMAXIMUM\0" |
9864 | | /* 21077 */ "G_FMINNUM\0" |
9865 | | /* 21087 */ "G_FMAXNUM\0" |
9866 | | /* 21097 */ "G_INTRINSIC_ROUNDEVEN\0" |
9867 | | /* 21119 */ "BALIGN\0" |
9868 | | /* 21126 */ "DALIGN\0" |
9869 | | /* 21133 */ "G_ASSERT_ALIGN\0" |
9870 | | /* 21148 */ "G_FCOPYSIGN\0" |
9871 | | /* 21160 */ "G_VECREDUCE_FMIN\0" |
9872 | | /* 21177 */ "G_ATOMICRMW_FMIN\0" |
9873 | | /* 21194 */ "G_VECREDUCE_SMIN\0" |
9874 | | /* 21211 */ "G_SMIN\0" |
9875 | | /* 21218 */ "G_VECREDUCE_UMIN\0" |
9876 | | /* 21235 */ "G_UMIN\0" |
9877 | | /* 21242 */ "G_ATOMICRMW_UMIN\0" |
9878 | | /* 21259 */ "G_ATOMICRMW_MIN\0" |
9879 | | /* 21275 */ "G_FSIN\0" |
9880 | | /* 21282 */ "DMFC2_OCTEON\0" |
9881 | | /* 21295 */ "DMTC2_OCTEON\0" |
9882 | | /* 21308 */ "CFI_INSTRUCTION\0" |
9883 | | /* 21324 */ "ADJCALLSTACKDOWN\0" |
9884 | | /* 21341 */ "G_SSUBO\0" |
9885 | | /* 21349 */ "G_USUBO\0" |
9886 | | /* 21357 */ "G_SADDO\0" |
9887 | | /* 21365 */ "G_UADDO\0" |
9888 | | /* 21373 */ "FEXP2_D_1_PSEUDO\0" |
9889 | | /* 21390 */ "FEXP2_W_1_PSEUDO\0" |
9890 | | /* 21407 */ "BPOSGE32_PSEUDO\0" |
9891 | | /* 21423 */ "INSERT_B_VIDX64_PSEUDO\0" |
9892 | | /* 21446 */ "INSERT_FD_VIDX64_PSEUDO\0" |
9893 | | /* 21470 */ "INSERT_D_VIDX64_PSEUDO\0" |
9894 | | /* 21493 */ "INSERT_H_VIDX64_PSEUDO\0" |
9895 | | /* 21516 */ "INSERT_FW_VIDX64_PSEUDO\0" |
9896 | | /* 21540 */ "INSERT_W_VIDX64_PSEUDO\0" |
9897 | | /* 21563 */ "SNZ_B_PSEUDO\0" |
9898 | | /* 21576 */ "SZ_B_PSEUDO\0" |
9899 | | /* 21588 */ "BSEL_FD_PSEUDO\0" |
9900 | | /* 21603 */ "FILL_FD_PSEUDO\0" |
9901 | | /* 21618 */ "INSERT_FD_PSEUDO\0" |
9902 | | /* 21635 */ "COPY_FD_PSEUDO\0" |
9903 | | /* 21650 */ "MSA_FP_EXTEND_D_PSEUDO\0" |
9904 | | /* 21673 */ "MSA_FP_ROUND_D_PSEUDO\0" |
9905 | | /* 21695 */ "BSEL_D_PSEUDO\0" |
9906 | | /* 21709 */ "AND_V_D_PSEUDO\0" |
9907 | | /* 21724 */ "NOR_V_D_PSEUDO\0" |
9908 | | /* 21739 */ "XOR_V_D_PSEUDO\0" |
9909 | | /* 21754 */ "SNZ_D_PSEUDO\0" |
9910 | | /* 21767 */ "SZ_D_PSEUDO\0" |
9911 | | /* 21779 */ "BSEL_H_PSEUDO\0" |
9912 | | /* 21793 */ "AND_V_H_PSEUDO\0" |
9913 | | /* 21808 */ "NOR_V_H_PSEUDO\0" |
9914 | | /* 21823 */ "XOR_V_H_PSEUDO\0" |
9915 | | /* 21838 */ "SNZ_H_PSEUDO\0" |
9916 | | /* 21851 */ "SZ_H_PSEUDO\0" |
9917 | | /* 21863 */ "SNZ_V_PSEUDO\0" |
9918 | | /* 21876 */ "SZ_V_PSEUDO\0" |
9919 | | /* 21888 */ "BSEL_FW_PSEUDO\0" |
9920 | | /* 21903 */ "FILL_FW_PSEUDO\0" |
9921 | | /* 21918 */ "INSERT_FW_PSEUDO\0" |
9922 | | /* 21935 */ "COPY_FW_PSEUDO\0" |
9923 | | /* 21950 */ "MSA_FP_EXTEND_W_PSEUDO\0" |
9924 | | /* 21973 */ "MSA_FP_ROUND_W_PSEUDO\0" |
9925 | | /* 21995 */ "BSEL_W_PSEUDO\0" |
9926 | | /* 22009 */ "AND_V_W_PSEUDO\0" |
9927 | | /* 22024 */ "NOR_V_W_PSEUDO\0" |
9928 | | /* 22039 */ "XOR_V_W_PSEUDO\0" |
9929 | | /* 22054 */ "SNZ_W_PSEUDO\0" |
9930 | | /* 22067 */ "SZ_W_PSEUDO\0" |
9931 | | /* 22079 */ "INSERT_B_VIDX_PSEUDO\0" |
9932 | | /* 22100 */ "INSERT_FD_VIDX_PSEUDO\0" |
9933 | | /* 22122 */ "INSERT_D_VIDX_PSEUDO\0" |
9934 | | /* 22143 */ "INSERT_H_VIDX_PSEUDO\0" |
9935 | | /* 22164 */ "INSERT_FW_VIDX_PSEUDO\0" |
9936 | | /* 22186 */ "INSERT_W_VIDX_PSEUDO\0" |
9937 | | /* 22207 */ "JUMP_TABLE_DEBUG_INFO\0" |
9938 | | /* 22229 */ "DCLO\0" |
9939 | | /* 22234 */ "PseudoMFLO\0" |
9940 | | /* 22245 */ "SHILO\0" |
9941 | | /* 22251 */ "MFTLO\0" |
9942 | | /* 22257 */ "MTLO\0" |
9943 | | /* 22262 */ "MTTLO\0" |
9944 | | /* 22268 */ "G_SMULO\0" |
9945 | | /* 22276 */ "G_UMULO\0" |
9946 | | /* 22284 */ "G_BZERO\0" |
9947 | | /* 22292 */ "STACKMAP\0" |
9948 | | /* 22301 */ "TRAP\0" |
9949 | | /* 22306 */ "G_ATOMICRMW_UDEC_WRAP\0" |
9950 | | /* 22328 */ "G_ATOMICRMW_UINC_WRAP\0" |
9951 | | /* 22350 */ "G_BSWAP\0" |
9952 | | /* 22358 */ "DBITSWAP\0" |
9953 | | /* 22367 */ "SDBBP\0" |
9954 | | /* 22373 */ "TLBP\0" |
9955 | | /* 22378 */ "EXTPDP\0" |
9956 | | /* 22385 */ "G_SITOFP\0" |
9957 | | /* 22394 */ "G_UITOFP\0" |
9958 | | /* 22403 */ "TLBGP\0" |
9959 | | /* 22409 */ "MTHLIP\0" |
9960 | | /* 22416 */ "G_FCMP\0" |
9961 | | /* 22423 */ "G_ICMP\0" |
9962 | | /* 22430 */ "SSNOP\0" |
9963 | | /* 22436 */ "DPOP\0" |
9964 | | /* 22441 */ "G_CTPOP\0" |
9965 | | /* 22449 */ "PATCHABLE_OP\0" |
9966 | | /* 22462 */ "FAULTING_OP\0" |
9967 | | /* 22474 */ "LOAD_ACC64DSP\0" |
9968 | | /* 22488 */ "STORE_ACC64DSP\0" |
9969 | | /* 22503 */ "RDDSP\0" |
9970 | | /* 22509 */ "WRDSP\0" |
9971 | | /* 22515 */ "MFTDSP\0" |
9972 | | /* 22522 */ "MTTDSP\0" |
9973 | | /* 22529 */ "LWDSP\0" |
9974 | | /* 22535 */ "SWDSP\0" |
9975 | | /* 22541 */ "MSUB_DSP\0" |
9976 | | /* 22550 */ "MADD_DSP\0" |
9977 | | /* 22559 */ "LOAD_CCOND_DSP\0" |
9978 | | /* 22574 */ "STORE_CCOND_DSP\0" |
9979 | | /* 22590 */ "MFHI_DSP\0" |
9980 | | /* 22599 */ "PseudoMTLOHI_DSP\0" |
9981 | | /* 22616 */ "MTHI_DSP\0" |
9982 | | /* 22625 */ "MFLO_DSP\0" |
9983 | | /* 22634 */ "MTLO_DSP\0" |
9984 | | /* 22643 */ "MULT_DSP\0" |
9985 | | /* 22652 */ "MSUBU_DSP\0" |
9986 | | /* 22662 */ "MADDU_DSP\0" |
9987 | | /* 22672 */ "MULTU_DSP\0" |
9988 | | /* 22682 */ "JRADDIUSP\0" |
9989 | | /* 22692 */ "EXTP\0" |
9990 | | /* 22697 */ "ADJCALLSTACKUP\0" |
9991 | | /* 22712 */ "PREALLOCATED_SETUP\0" |
9992 | | /* 22731 */ "DVP\0" |
9993 | | /* 22735 */ "EVP\0" |
9994 | | /* 22739 */ "G_FLDEXP\0" |
9995 | | /* 22748 */ "G_STRICT_FLDEXP\0" |
9996 | | /* 22764 */ "G_FEXP\0" |
9997 | | /* 22771 */ "G_FFREXP\0" |
9998 | | /* 22780 */ "BEQ\0" |
9999 | | /* 22784 */ "SEQ\0" |
10000 | | /* 22788 */ "TEQ\0" |
10001 | | /* 22792 */ "TLBR\0" |
10002 | | /* 22797 */ "MULEU_S_PH_QBR\0" |
10003 | | /* 22812 */ "PRECEU_PH_QBR\0" |
10004 | | /* 22826 */ "PRECEQU_PH_QBR\0" |
10005 | | /* 22841 */ "DPAU_H_QBR\0" |
10006 | | /* 22852 */ "DPSU_H_QBR\0" |
10007 | | /* 22863 */ "G_BR\0" |
10008 | | /* 22868 */ "BAL_BR\0" |
10009 | | /* 22875 */ "INLINEASM_BR\0" |
10010 | | /* 22888 */ "G_BLOCK_ADDR\0" |
10011 | | /* 22901 */ "LDR\0" |
10012 | | /* 22905 */ "SDR\0" |
10013 | | /* 22909 */ "MEMBARRIER\0" |
10014 | | /* 22920 */ "G_CONSTANT_FOLD_BARRIER\0" |
10015 | | /* 22944 */ "PATCHABLE_FUNCTION_ENTER\0" |
10016 | | /* 22969 */ "G_READCYCLECOUNTER\0" |
10017 | | /* 22988 */ "G_READ_REGISTER\0" |
10018 | | /* 23004 */ "G_WRITE_REGISTER\0" |
10019 | | /* 23021 */ "TLBGR\0" |
10020 | | /* 23027 */ "LoadImmDoubleFGR\0" |
10021 | | /* 23044 */ "LoadImmSingleFGR\0" |
10022 | | /* 23061 */ "MAQ_SA_W_PHR\0" |
10023 | | /* 23074 */ "PRECEQ_W_PHR\0" |
10024 | | /* 23087 */ "MAQ_S_W_PHR\0" |
10025 | | /* 23099 */ "MULEQ_S_W_PHR\0" |
10026 | | /* 23113 */ "G_ASHR\0" |
10027 | | /* 23120 */ "G_FSHR\0" |
10028 | | /* 23127 */ "G_LSHR\0" |
10029 | | /* 23134 */ "JR\0" |
10030 | | /* 23137 */ "JALR\0" |
10031 | | /* 23142 */ "NOR\0" |
10032 | | /* 23146 */ "G_FFLOOR\0" |
10033 | | /* 23155 */ "DROR\0" |
10034 | | /* 23160 */ "G_BUILD_VECTOR\0" |
10035 | | /* 23175 */ "G_SHUFFLE_VECTOR\0" |
10036 | | /* 23192 */ "G_VECREDUCE_XOR\0" |
10037 | | /* 23208 */ "G_XOR\0" |
10038 | | /* 23214 */ "G_ATOMICRMW_XOR\0" |
10039 | | /* 23230 */ "G_VECREDUCE_OR\0" |
10040 | | /* 23245 */ "G_OR\0" |
10041 | | /* 23250 */ "G_ATOMICRMW_OR\0" |
10042 | | /* 23265 */ "MFTGPR\0" |
10043 | | /* 23272 */ "MTTGPR\0" |
10044 | | /* 23279 */ "LoadImmDoubleGPR\0" |
10045 | | /* 23296 */ "LoadImmSingleGPR\0" |
10046 | | /* 23313 */ "MFTR\0" |
10047 | | /* 23318 */ "DROTR\0" |
10048 | | /* 23324 */ "G_ROTR\0" |
10049 | | /* 23331 */ "G_INTTOPTR\0" |
10050 | | /* 23342 */ "MTTR\0" |
10051 | | /* 23347 */ "TLBWR\0" |
10052 | | /* 23353 */ "TLBGWR\0" |
10053 | | /* 23360 */ "RDHWR\0" |
10054 | | /* 23366 */ "LWR\0" |
10055 | | /* 23370 */ "SWR\0" |
10056 | | /* 23374 */ "G_FABS\0" |
10057 | | /* 23381 */ "G_ABS\0" |
10058 | | /* 23387 */ "G_UNMERGE_VALUES\0" |
10059 | | /* 23404 */ "G_MERGE_VALUES\0" |
10060 | | /* 23419 */ "CINS\0" |
10061 | | /* 23424 */ "DINS\0" |
10062 | | /* 23429 */ "G_FCOS\0" |
10063 | | /* 23436 */ "G_CONCAT_VECTORS\0" |
10064 | | /* 23453 */ "COPY_TO_REGCLASS\0" |
10065 | | /* 23470 */ "G_IS_FPCLASS\0" |
10066 | | /* 23483 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0" |
10067 | | /* 23513 */ "G_INTRINSIC_W_SIDE_EFFECTS\0" |
10068 | | /* 23540 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0" |
10069 | | /* 23578 */ "EXTS\0" |
10070 | | /* 23583 */ "CVT_D32_S\0" |
10071 | | /* 23593 */ "CVT_D64_S\0" |
10072 | | /* 23603 */ "MOVN_I64_S\0" |
10073 | | /* 23614 */ "MOVZ_I64_S\0" |
10074 | | /* 23625 */ "MINA_S\0" |
10075 | | /* 23632 */ "MAXA_S\0" |
10076 | | /* 23639 */ "FSUB_S\0" |
10077 | | /* 23646 */ "NMSUB_S\0" |
10078 | | /* 23654 */ "FADD_S\0" |
10079 | | /* 23661 */ "NMADD_S\0" |
10080 | | /* 23669 */ "C_NGE_S\0" |
10081 | | /* 23677 */ "C_NGLE_S\0" |
10082 | | /* 23686 */ "C_OLE_S\0" |
10083 | | /* 23694 */ "CMP_SLE_S\0" |
10084 | | /* 23704 */ "CMP_SULE_S\0" |
10085 | | /* 23715 */ "C_ULE_S\0" |
10086 | | /* 23723 */ "CMP_ULE_S\0" |
10087 | | /* 23733 */ "C_LE_S\0" |
10088 | | /* 23740 */ "CMP_LE_S\0" |
10089 | | /* 23749 */ "CMP_SAF_S\0" |
10090 | | /* 23759 */ "MSUBF_S\0" |
10091 | | /* 23767 */ "MADDF_S\0" |
10092 | | /* 23775 */ "C_SF_S\0" |
10093 | | /* 23782 */ "MOVF_S\0" |
10094 | | /* 23789 */ "C_F_S\0" |
10095 | | /* 23795 */ "PseudoSELECTFP_F_S\0" |
10096 | | /* 23814 */ "CMP_F_S\0" |
10097 | | /* 23822 */ "FNEG_S\0" |
10098 | | /* 23829 */ "MOVN_I_S\0" |
10099 | | /* 23838 */ "MOVZ_I_S\0" |
10100 | | /* 23847 */ "SEL_S\0" |
10101 | | /* 23853 */ "C_NGL_S\0" |
10102 | | /* 23861 */ "FMUL_S\0" |
10103 | | /* 23868 */ "TRUNC_L_S\0" |
10104 | | /* 23878 */ "ROUND_L_S\0" |
10105 | | /* 23888 */ "CEIL_L_S\0" |
10106 | | /* 23897 */ "FLOOR_L_S\0" |
10107 | | /* 23907 */ "CVT_L_S\0" |
10108 | | /* 23915 */ "MIN_S\0" |
10109 | | /* 23921 */ "CMP_SUN_S\0" |
10110 | | /* 23931 */ "C_UN_S\0" |
10111 | | /* 23938 */ "CMP_UN_S\0" |
10112 | | /* 23947 */ "RECIP_S\0" |
10113 | | /* 23955 */ "C_SEQ_S\0" |
10114 | | /* 23963 */ "CMP_SEQ_S\0" |
10115 | | /* 23973 */ "CMP_SUEQ_S\0" |
10116 | | /* 23984 */ "C_UEQ_S\0" |
10117 | | /* 23992 */ "CMP_UEQ_S\0" |
10118 | | /* 24002 */ "C_EQ_S\0" |
10119 | | /* 24009 */ "CMP_EQ_S\0" |
10120 | | /* 24018 */ "FABS_S\0" |
10121 | | /* 24025 */ "CLASS_S\0" |
10122 | | /* 24033 */ "PseudoSELECT_S\0" |
10123 | | /* 24048 */ "C_NGT_S\0" |
10124 | | /* 24056 */ "C_OLT_S\0" |
10125 | | /* 24064 */ "CMP_SLT_S\0" |
10126 | | /* 24074 */ "CMP_SULT_S\0" |
10127 | | /* 24085 */ "C_ULT_S\0" |
10128 | | /* 24093 */ "CMP_ULT_S\0" |
10129 | | /* 24103 */ "C_LT_S\0" |
10130 | | /* 24110 */ "CMP_LT_S\0" |
10131 | | /* 24119 */ "RINT_S\0" |
10132 | | /* 24126 */ "FSQRT_S\0" |
10133 | | /* 24134 */ "RSQRT_S\0" |
10134 | | /* 24142 */ "MOVT_S\0" |
10135 | | /* 24149 */ "PseudoSELECTFP_T_S\0" |
10136 | | /* 24168 */ "FDIV_S\0" |
10137 | | /* 24175 */ "FMOV_S\0" |
10138 | | /* 24182 */ "PseudoTRUNC_W_S\0" |
10139 | | /* 24198 */ "ROUND_W_S\0" |
10140 | | /* 24208 */ "CEIL_W_S\0" |
10141 | | /* 24217 */ "FLOOR_W_S\0" |
10142 | | /* 24227 */ "CVT_W_S\0" |
10143 | | /* 24235 */ "MAX_S\0" |
10144 | | /* 24241 */ "SELNEZ_S\0" |
10145 | | /* 24250 */ "SELEQZ_S\0" |
10146 | | /* 24259 */ "BC1T\0" |
10147 | | /* 24264 */ "G_SSUBSAT\0" |
10148 | | /* 24274 */ "G_USUBSAT\0" |
10149 | | /* 24284 */ "G_SADDSAT\0" |
10150 | | /* 24294 */ "G_UADDSAT\0" |
10151 | | /* 24304 */ "G_SSHLSAT\0" |
10152 | | /* 24314 */ "G_USHLSAT\0" |
10153 | | /* 24324 */ "G_SMULFIXSAT\0" |
10154 | | /* 24337 */ "G_UMULFIXSAT\0" |
10155 | | /* 24350 */ "G_SDIVFIXSAT\0" |
10156 | | /* 24363 */ "G_UDIVFIXSAT\0" |
10157 | | /* 24376 */ "G_EXTRACT\0" |
10158 | | /* 24386 */ "G_SELECT\0" |
10159 | | /* 24395 */ "G_BRINDIRECT\0" |
10160 | | /* 24408 */ "DERET\0" |
10161 | | /* 24414 */ "PATCHABLE_RET\0" |
10162 | | /* 24428 */ "G_MEMSET\0" |
10163 | | /* 24437 */ "BGT\0" |
10164 | | /* 24441 */ "WAIT\0" |
10165 | | /* 24446 */ "PATCHABLE_FUNCTION_EXIT\0" |
10166 | | /* 24470 */ "G_BRJT\0" |
10167 | | /* 24477 */ "BLT\0" |
10168 | | /* 24481 */ "G_EXTRACT_VECTOR_ELT\0" |
10169 | | /* 24502 */ "G_INSERT_VECTOR_ELT\0" |
10170 | | /* 24522 */ "SLT\0" |
10171 | | /* 24526 */ "TLT\0" |
10172 | | /* 24530 */ "PseudoDMULT\0" |
10173 | | /* 24542 */ "PseudoMULT\0" |
10174 | | /* 24553 */ "DMT\0" |
10175 | | /* 24557 */ "EMT\0" |
10176 | | /* 24561 */ "G_FCONSTANT\0" |
10177 | | /* 24573 */ "G_CONSTANT\0" |
10178 | | /* 24584 */ "G_INTRINSIC_CONVERGENT\0" |
10179 | | /* 24607 */ "STATEPOINT\0" |
10180 | | /* 24618 */ "PATCHPOINT\0" |
10181 | | /* 24629 */ "G_PTRTOINT\0" |
10182 | | /* 24640 */ "G_FRINT\0" |
10183 | | /* 24648 */ "G_INTRINSIC_LRINT\0" |
10184 | | /* 24666 */ "G_FNEARBYINT\0" |
10185 | | /* 24679 */ "G_VASTART\0" |
10186 | | /* 24689 */ "LIFETIME_START\0" |
10187 | | /* 24704 */ "G_INVOKE_REGION_START\0" |
10188 | | /* 24726 */ "G_INSERT\0" |
10189 | | /* 24735 */ "G_FSQRT\0" |
10190 | | /* 24743 */ "G_STRICT_FSQRT\0" |
10191 | | /* 24758 */ "G_BITCAST\0" |
10192 | | /* 24768 */ "G_ADDRSPACE_CAST\0" |
10193 | | /* 24785 */ "DBG_VALUE_LIST\0" |
10194 | | /* 24800 */ "GINVT\0" |
10195 | | /* 24806 */ "DEXT\0" |
10196 | | /* 24811 */ "G_FPEXT\0" |
10197 | | /* 24819 */ "G_SEXT\0" |
10198 | | /* 24826 */ "G_ASSERT_SEXT\0" |
10199 | | /* 24840 */ "G_ANYEXT\0" |
10200 | | /* 24849 */ "G_ZEXT\0" |
10201 | | /* 24856 */ "G_ASSERT_ZEXT\0" |
10202 | | /* 24870 */ "PseudoMSUBU\0" |
10203 | | /* 24882 */ "PseudoMADDU\0" |
10204 | | /* 24894 */ "DMODU\0" |
10205 | | /* 24900 */ "BGEU\0" |
10206 | | /* 24905 */ "SGEU\0" |
10207 | | /* 24910 */ "TGEU\0" |
10208 | | /* 24915 */ "BLEU\0" |
10209 | | /* 24920 */ "SLEU\0" |
10210 | | /* 24925 */ "DMUHU\0" |
10211 | | /* 24931 */ "TGEIU\0" |
10212 | | /* 24937 */ "TTLTIU\0" |
10213 | | /* 24944 */ "V3MULU\0" |
10214 | | /* 24951 */ "DMULU\0" |
10215 | | /* 24957 */ "VMULU\0" |
10216 | | /* 24963 */ "DINSU\0" |
10217 | | /* 24969 */ "BGTU\0" |
10218 | | /* 24974 */ "BLTU\0" |
10219 | | /* 24979 */ "TLTU\0" |
10220 | | /* 24984 */ "DEXTU\0" |
10221 | | /* 24990 */ "DDIVU\0" |
10222 | | /* 24996 */ "DSRAV\0" |
10223 | | /* 25002 */ "BITREV\0" |
10224 | | /* 25009 */ "DDIV\0" |
10225 | | /* 25014 */ "G_FDIV\0" |
10226 | | /* 25021 */ "G_STRICT_FDIV\0" |
10227 | | /* 25035 */ "PseudoDSDIV\0" |
10228 | | /* 25047 */ "G_SDIV\0" |
10229 | | /* 25054 */ "PseudoSDIV\0" |
10230 | | /* 25065 */ "PseudoDUDIV\0" |
10231 | | /* 25077 */ "G_UDIV\0" |
10232 | | /* 25084 */ "PseudoUDIV\0" |
10233 | | /* 25095 */ "DSLLV\0" |
10234 | | /* 25101 */ "DSRLV\0" |
10235 | | /* 25107 */ "G_GET_FPENV\0" |
10236 | | /* 25119 */ "G_RESET_FPENV\0" |
10237 | | /* 25133 */ "G_SET_FPENV\0" |
10238 | | /* 25145 */ "TLBINV\0" |
10239 | | /* 25152 */ "TLBGINV\0" |
10240 | | /* 25160 */ "SHILOV\0" |
10241 | | /* 25167 */ "EXTPDPV\0" |
10242 | | /* 25175 */ "EXTPV\0" |
10243 | | /* 25181 */ "DROTRV\0" |
10244 | | /* 25188 */ "INSV\0" |
10245 | | /* 25193 */ "AND_V\0" |
10246 | | /* 25199 */ "MOVE_V\0" |
10247 | | /* 25206 */ "BSEL_V\0" |
10248 | | /* 25213 */ "NOR_V\0" |
10249 | | /* 25219 */ "XOR_V\0" |
10250 | | /* 25225 */ "BZ_V\0" |
10251 | | /* 25230 */ "BMZ_V\0" |
10252 | | /* 25236 */ "BNZ_V\0" |
10253 | | /* 25242 */ "BMNZ_V\0" |
10254 | | /* 25249 */ "CRC32W\0" |
10255 | | /* 25256 */ "CRC32CW\0" |
10256 | | /* 25264 */ "LW\0" |
10257 | | /* 25267 */ "G_FPOW\0" |
10258 | | /* 25274 */ "SW\0" |
10259 | | /* 25277 */ "PseudoCVT_D32_W\0" |
10260 | | /* 25293 */ "FLOG2_W\0" |
10261 | | /* 25301 */ "FEXP2_W\0" |
10262 | | /* 25309 */ "PseudoCVT_D64_W\0" |
10263 | | /* 25325 */ "SRA_W\0" |
10264 | | /* 25331 */ "ADD_A_W\0" |
10265 | | /* 25339 */ "FMIN_A_W\0" |
10266 | | /* 25348 */ "ADDS_A_W\0" |
10267 | | /* 25357 */ "FMAX_A_W\0" |
10268 | | /* 25366 */ "FSUB_W\0" |
10269 | | /* 25373 */ "FMSUB_W\0" |
10270 | | /* 25381 */ "NLOC_W\0" |
10271 | | /* 25388 */ "NLZC_W\0" |
10272 | | /* 25395 */ "FADD_W\0" |
10273 | | /* 25402 */ "FMADD_W\0" |
10274 | | /* 25410 */ "SLD_W\0" |
10275 | | /* 25416 */ "PCKOD_W\0" |
10276 | | /* 25424 */ "ILVOD_W\0" |
10277 | | /* 25432 */ "FCLE_W\0" |
10278 | | /* 25439 */ "FSLE_W\0" |
10279 | | /* 25446 */ "FCULE_W\0" |
10280 | | /* 25454 */ "FSULE_W\0" |
10281 | | /* 25462 */ "FCNE_W\0" |
10282 | | /* 25469 */ "FSNE_W\0" |
10283 | | /* 25476 */ "FCUNE_W\0" |
10284 | | /* 25484 */ "FSUNE_W\0" |
10285 | | /* 25492 */ "INSVE_W\0" |
10286 | | /* 25500 */ "FCAF_W\0" |
10287 | | /* 25507 */ "FSAF_W\0" |
10288 | | /* 25514 */ "VSHF_W\0" |
10289 | | /* 25521 */ "BNEG_W\0" |
10290 | | /* 25528 */ "PRECR_SRA_PH_W\0" |
10291 | | /* 25543 */ "PRECRQ_PH_W\0" |
10292 | | /* 25555 */ "PRECR_SRA_R_PH_W\0" |
10293 | | /* 25572 */ "PRECRQ_RS_PH_W\0" |
10294 | | /* 25587 */ "SUBQH_W\0" |
10295 | | /* 25595 */ "ADDQH_W\0" |
10296 | | /* 25603 */ "SRAI_W\0" |
10297 | | /* 25610 */ "SLDI_W\0" |
10298 | | /* 25617 */ "BNEGI_W\0" |
10299 | | /* 25625 */ "SLLI_W\0" |
10300 | | /* 25632 */ "SRLI_W\0" |
10301 | | /* 25639 */ "BINSLI_W\0" |
10302 | | /* 25648 */ "CEQI_W\0" |
10303 | | /* 25655 */ "SRARI_W\0" |
10304 | | /* 25663 */ "BCLRI_W\0" |
10305 | | /* 25671 */ "SRLRI_W\0" |
10306 | | /* 25679 */ "BINSRI_W\0" |
10307 | | /* 25688 */ "SPLATI_W\0" |
10308 | | /* 25697 */ "BSETI_W\0" |
10309 | | /* 25705 */ "SUBVI_W\0" |
10310 | | /* 25713 */ "ADDVI_W\0" |
10311 | | /* 25721 */ "FILL_W\0" |
10312 | | /* 25728 */ "SLL_W\0" |
10313 | | /* 25734 */ "FEXUPL_W\0" |
10314 | | /* 25743 */ "FFQL_W\0" |
10315 | | /* 25750 */ "SRL_W\0" |
10316 | | /* 25756 */ "BINSL_W\0" |
10317 | | /* 25764 */ "FMUL_W\0" |
10318 | | /* 25771 */ "ILVL_W\0" |
10319 | | /* 25778 */ "DPAQ_SA_L_W\0" |
10320 | | /* 25790 */ "DPSQ_SA_L_W\0" |
10321 | | /* 25802 */ "FMIN_W\0" |
10322 | | /* 25809 */ "FCUN_W\0" |
10323 | | /* 25816 */ "FSUN_W\0" |
10324 | | /* 25823 */ "FEXDO_W\0" |
10325 | | /* 25831 */ "FRCP_W\0" |
10326 | | /* 25838 */ "FCEQ_W\0" |
10327 | | /* 25845 */ "FSEQ_W\0" |
10328 | | /* 25852 */ "FCUEQ_W\0" |
10329 | | /* 25860 */ "FSUEQ_W\0" |
10330 | | /* 25868 */ "FTQ_W\0" |
10331 | | /* 25874 */ "MSUB_Q_W\0" |
10332 | | /* 25883 */ "MADD_Q_W\0" |
10333 | | /* 25892 */ "MUL_Q_W\0" |
10334 | | /* 25900 */ "MSUBR_Q_W\0" |
10335 | | /* 25910 */ "MADDR_Q_W\0" |
10336 | | /* 25920 */ "MULR_Q_W\0" |
10337 | | /* 25929 */ "SRAR_W\0" |
10338 | | /* 25936 */ "LDR_W\0" |
10339 | | /* 25942 */ "BCLR_W\0" |
10340 | | /* 25949 */ "SRLR_W\0" |
10341 | | /* 25956 */ "FCOR_W\0" |
10342 | | /* 25963 */ "FSOR_W\0" |
10343 | | /* 25970 */ "FEXUPR_W\0" |
10344 | | /* 25979 */ "FFQR_W\0" |
10345 | | /* 25986 */ "BINSR_W\0" |
10346 | | /* 25994 */ "STR_W\0" |
10347 | | /* 26000 */ "EXTR_W\0" |
10348 | | /* 26007 */ "ILVR_W\0" |
10349 | | /* 26014 */ "SHRA_R_W\0" |
10350 | | /* 26023 */ "SUBQH_R_W\0" |
10351 | | /* 26033 */ "ADDQH_R_W\0" |
10352 | | /* 26043 */ "EXTR_R_W\0" |
10353 | | /* 26052 */ "SHRAV_R_W\0" |
10354 | | /* 26062 */ "EXTRV_R_W\0" |
10355 | | /* 26072 */ "FABS_W\0" |
10356 | | /* 26079 */ "MULQ_RS_W\0" |
10357 | | /* 26089 */ "EXTR_RS_W\0" |
10358 | | /* 26099 */ "EXTRV_RS_W\0" |
10359 | | /* 26110 */ "FCLASS_W\0" |
10360 | | /* 26119 */ "ASUB_S_W\0" |
10361 | | /* 26128 */ "HSUB_S_W\0" |
10362 | | /* 26137 */ "DPSUB_S_W\0" |
10363 | | /* 26147 */ "FTRUNC_S_W\0" |
10364 | | /* 26158 */ "HADD_S_W\0" |
10365 | | /* 26167 */ "DPADD_S_W\0" |
10366 | | /* 26177 */ "MOD_S_W\0" |
10367 | | /* 26185 */ "CLE_S_W\0" |
10368 | | /* 26193 */ "AVE_S_W\0" |
10369 | | /* 26201 */ "CLEI_S_W\0" |
10370 | | /* 26210 */ "MINI_S_W\0" |
10371 | | /* 26219 */ "CLTI_S_W\0" |
10372 | | /* 26228 */ "MAXI_S_W\0" |
10373 | | /* 26237 */ "SHLL_S_W\0" |
10374 | | /* 26246 */ "MIN_S_W\0" |
10375 | | /* 26254 */ "DOTP_S_W\0" |
10376 | | /* 26263 */ "SUBQ_S_W\0" |
10377 | | /* 26272 */ "ADDQ_S_W\0" |
10378 | | /* 26281 */ "MULQ_S_W\0" |
10379 | | /* 26290 */ "ABSQ_S_W\0" |
10380 | | /* 26299 */ "AVER_S_W\0" |
10381 | | /* 26308 */ "SUBS_S_W\0" |
10382 | | /* 26317 */ "ADDS_S_W\0" |
10383 | | /* 26326 */ "SAT_S_W\0" |
10384 | | /* 26334 */ "CLT_S_W\0" |
10385 | | /* 26342 */ "FFINT_S_W\0" |
10386 | | /* 26352 */ "FTINT_S_W\0" |
10387 | | /* 26362 */ "PseudoCVT_S_W\0" |
10388 | | /* 26376 */ "SUBSUU_S_W\0" |
10389 | | /* 26387 */ "DIV_S_W\0" |
10390 | | /* 26395 */ "SHLLV_S_W\0" |
10391 | | /* 26405 */ "MAX_S_W\0" |
10392 | | /* 26413 */ "COPY_S_W\0" |
10393 | | /* 26422 */ "SPLAT_W\0" |
10394 | | /* 26430 */ "BSET_W\0" |
10395 | | /* 26437 */ "FCLT_W\0" |
10396 | | /* 26444 */ "FSLT_W\0" |
10397 | | /* 26451 */ "FCULT_W\0" |
10398 | | /* 26459 */ "FSULT_W\0" |
10399 | | /* 26467 */ "PCNT_W\0" |
10400 | | /* 26474 */ "FRINT_W\0" |
10401 | | /* 26482 */ "INSERT_W\0" |
10402 | | /* 26491 */ "FSQRT_W\0" |
10403 | | /* 26499 */ "FRSQRT_W\0" |
10404 | | /* 26508 */ "ST_W\0" |
10405 | | /* 26513 */ "ASUB_U_W\0" |
10406 | | /* 26522 */ "HSUB_U_W\0" |
10407 | | /* 26531 */ "DPSUB_U_W\0" |
10408 | | /* 26541 */ "FTRUNC_U_W\0" |
10409 | | /* 26552 */ "HADD_U_W\0" |
10410 | | /* 26561 */ "DPADD_U_W\0" |
10411 | | /* 26571 */ "MOD_U_W\0" |
10412 | | /* 26579 */ "CLE_U_W\0" |
10413 | | /* 26587 */ "AVE_U_W\0" |
10414 | | /* 26595 */ "CLEI_U_W\0" |
10415 | | /* 26604 */ "MINI_U_W\0" |
10416 | | /* 26613 */ "CLTI_U_W\0" |
10417 | | /* 26622 */ "MAXI_U_W\0" |
10418 | | /* 26631 */ "MIN_U_W\0" |
10419 | | /* 26639 */ "DOTP_U_W\0" |
10420 | | /* 26648 */ "AVER_U_W\0" |
10421 | | /* 26657 */ "SUBS_U_W\0" |
10422 | | /* 26666 */ "ADDS_U_W\0" |
10423 | | /* 26675 */ "SUBSUS_U_W\0" |
10424 | | /* 26686 */ "SAT_U_W\0" |
10425 | | /* 26694 */ "CLT_U_W\0" |
10426 | | /* 26702 */ "FFINT_U_W\0" |
10427 | | /* 26712 */ "FTINT_U_W\0" |
10428 | | /* 26722 */ "DIV_U_W\0" |
10429 | | /* 26730 */ "MAX_U_W\0" |
10430 | | /* 26738 */ "COPY_U_W\0" |
10431 | | /* 26747 */ "MSUBV_W\0" |
10432 | | /* 26755 */ "MADDV_W\0" |
10433 | | /* 26763 */ "PCKEV_W\0" |
10434 | | /* 26771 */ "ILVEV_W\0" |
10435 | | /* 26779 */ "FDIV_W\0" |
10436 | | /* 26786 */ "MULV_W\0" |
10437 | | /* 26793 */ "EXTRV_W\0" |
10438 | | /* 26801 */ "FMAX_W\0" |
10439 | | /* 26808 */ "BZ_W\0" |
10440 | | /* 26813 */ "BNZ_W\0" |
10441 | | /* 26819 */ "G_VECREDUCE_FMAX\0" |
10442 | | /* 26836 */ "G_ATOMICRMW_FMAX\0" |
10443 | | /* 26853 */ "G_VECREDUCE_SMAX\0" |
10444 | | /* 26870 */ "G_SMAX\0" |
10445 | | /* 26877 */ "G_VECREDUCE_UMAX\0" |
10446 | | /* 26894 */ "G_UMAX\0" |
10447 | | /* 26901 */ "G_ATOMICRMW_UMAX\0" |
10448 | | /* 26918 */ "G_ATOMICRMW_MAX\0" |
10449 | | /* 26934 */ "MFTACX\0" |
10450 | | /* 26941 */ "MTTACX\0" |
10451 | | /* 26948 */ "G_FRAME_INDEX\0" |
10452 | | /* 26962 */ "G_SBFX\0" |
10453 | | /* 26969 */ "G_UBFX\0" |
10454 | | /* 26976 */ "LHX\0" |
10455 | | /* 26980 */ "G_SMULFIX\0" |
10456 | | /* 26990 */ "G_UMULFIX\0" |
10457 | | /* 27000 */ "G_SDIVFIX\0" |
10458 | | /* 27010 */ "G_UDIVFIX\0" |
10459 | | /* 27020 */ "JALX\0" |
10460 | | /* 27025 */ "LBUX\0" |
10461 | | /* 27030 */ "LWX\0" |
10462 | | /* 27034 */ "G_MEMCPY\0" |
10463 | | /* 27043 */ "COPY\0" |
10464 | | /* 27048 */ "CONSTPOOL_ENTRY\0" |
10465 | | /* 27064 */ "BGEZ\0" |
10466 | | /* 27069 */ "BLEZ\0" |
10467 | | /* 27074 */ "BC1NEZ\0" |
10468 | | /* 27081 */ "BC2NEZ\0" |
10469 | | /* 27088 */ "SELNEZ\0" |
10470 | | /* 27095 */ "DCLZ\0" |
10471 | | /* 27100 */ "G_CTLZ\0" |
10472 | | /* 27107 */ "BC1EQZ\0" |
10473 | | /* 27114 */ "BC2EQZ\0" |
10474 | | /* 27121 */ "SELEQZ\0" |
10475 | | /* 27128 */ "BGTZ\0" |
10476 | | /* 27133 */ "BLTZ\0" |
10477 | | /* 27138 */ "G_CTTZ\0" |
10478 | | /* 27145 */ "SelBneZ\0" |
10479 | | /* 27153 */ "SelBeqZ\0" |
10480 | | /* 27161 */ "JalOneReg\0" |
10481 | | /* 27171 */ "JalTwoReg\0" |
10482 | | /* 27181 */ "PseudoIndirectHazardBranch\0" |
10483 | | /* 27208 */ "PseudoIndirectBranch\0" |
10484 | | /* 27229 */ "Ulh\0" |
10485 | | /* 27233 */ "Ush\0" |
10486 | | /* 27237 */ "DADDi\0" |
10487 | | /* 27243 */ "ANDi\0" |
10488 | | /* 27248 */ "SNEi\0" |
10489 | | /* 27253 */ "SEQi\0" |
10490 | | /* 27258 */ "XORi\0" |
10491 | | /* 27263 */ "SLTi\0" |
10492 | | /* 27268 */ "LONG_BRANCH_LUi\0" |
10493 | | /* 27284 */ "SelTBtneZCmpi\0" |
10494 | | /* 27298 */ "SelTBteqZCmpi\0" |
10495 | | /* 27312 */ "SelTBtneZSlti\0" |
10496 | | /* 27326 */ "SelTBteqZSlti\0" |
10497 | | /* 27340 */ "SGEImm\0" |
10498 | | /* 27347 */ "SLEImm\0" |
10499 | | /* 27354 */ "DROLImm\0" |
10500 | | /* 27362 */ "NORImm\0" |
10501 | | /* 27369 */ "DRORImm\0" |
10502 | | /* 27377 */ "SGTImm\0" |
10503 | | /* 27384 */ "SGEUImm\0" |
10504 | | /* 27392 */ "SLEUImm\0" |
10505 | | /* 27400 */ "SGTUImm\0" |
10506 | | /* 27408 */ "BneImm\0" |
10507 | | /* 27415 */ "BeqImm\0" |
10508 | | /* 27422 */ "PseudoReturn\0" |
10509 | | /* 27435 */ "JALRHB64Pseudo\0" |
10510 | | /* 27450 */ "JALR64Pseudo\0" |
10511 | | /* 27463 */ "JALRHBPseudo\0" |
10512 | | /* 27476 */ "JALRPseudo\0" |
10513 | | /* 27487 */ "B_MMR6_Pseudo\0" |
10514 | | /* 27501 */ "B_MM_Pseudo\0" |
10515 | | /* 27513 */ "SDIV_MM_Pseudo\0" |
10516 | | /* 27528 */ "UDIV_MM_Pseudo\0" |
10517 | | /* 27543 */ "LDMacro\0" |
10518 | | /* 27551 */ "SDMacro\0" |
10519 | | /* 27559 */ "SNEMacro\0" |
10520 | | /* 27568 */ "SNEIMacro\0" |
10521 | | /* 27578 */ "SEQIMacro\0" |
10522 | | /* 27588 */ "DSRemIMacro\0" |
10523 | | /* 27600 */ "DURemIMacro\0" |
10524 | | /* 27612 */ "DSDivIMacro\0" |
10525 | | /* 27624 */ "DUDivIMacro\0" |
10526 | | /* 27636 */ "DMULMacro\0" |
10527 | | /* 27646 */ "DMULOMacro\0" |
10528 | | /* 27657 */ "SEQMacro\0" |
10529 | | /* 27666 */ "ABSMacro\0" |
10530 | | /* 27675 */ "DMULOUMacro\0" |
10531 | | /* 27687 */ "DSRemMacro\0" |
10532 | | /* 27698 */ "DURemMacro\0" |
10533 | | /* 27709 */ "BGEImmMacro\0" |
10534 | | /* 27721 */ "BLEImmMacro\0" |
10535 | | /* 27733 */ "BGELImmMacro\0" |
10536 | | /* 27746 */ "BLELImmMacro\0" |
10537 | | /* 27759 */ "BNELImmMacro\0" |
10538 | | /* 27772 */ "BEQLImmMacro\0" |
10539 | | /* 27785 */ "BGTLImmMacro\0" |
10540 | | /* 27798 */ "BLTLImmMacro\0" |
10541 | | /* 27811 */ "BGEULImmMacro\0" |
10542 | | /* 27825 */ "BLEULImmMacro\0" |
10543 | | /* 27839 */ "DMULImmMacro\0" |
10544 | | /* 27852 */ "BGTULImmMacro\0" |
10545 | | /* 27866 */ "BLTULImmMacro\0" |
10546 | | /* 27880 */ "BGTImmMacro\0" |
10547 | | /* 27892 */ "BLTImmMacro\0" |
10548 | | /* 27904 */ "BGEUImmMacro\0" |
10549 | | /* 27917 */ "BLEUImmMacro\0" |
10550 | | /* 27930 */ "BGTUImmMacro\0" |
10551 | | /* 27943 */ "BLTUImmMacro\0" |
10552 | | /* 27956 */ "DSDivMacro\0" |
10553 | | /* 27967 */ "DUDivMacro\0" |
10554 | | /* 27978 */ "LONG_BRANCH_LUi2Op\0" |
10555 | | /* 27997 */ "LONG_BRANCH_DADDiu2Op\0" |
10556 | | /* 28019 */ "LONG_BRANCH_ADDiu2Op\0" |
10557 | | /* 28040 */ "SelTBtneZCmp\0" |
10558 | | /* 28053 */ "SelTBteqZCmp\0" |
10559 | | /* 28066 */ "SaaAddr\0" |
10560 | | /* 28074 */ "SaadAddr\0" |
10561 | | /* 28083 */ "ERet\0" |
10562 | | /* 28088 */ "SelTBtneZSlt\0" |
10563 | | /* 28101 */ "SelTBteqZSlt\0" |
10564 | | /* 28114 */ "LBu\0" |
10565 | | /* 28118 */ "DSUBu\0" |
10566 | | /* 28124 */ "BADDu\0" |
10567 | | /* 28130 */ "DADDu\0" |
10568 | | /* 28136 */ "LHu\0" |
10569 | | /* 28140 */ "SLTu\0" |
10570 | | /* 28145 */ "PseudoDMULTu\0" |
10571 | | /* 28158 */ "PseudoMULTu\0" |
10572 | | /* 28170 */ "LWu\0" |
10573 | | /* 28174 */ "Ulhu\0" |
10574 | | /* 28179 */ "LONG_BRANCH_DADDiu\0" |
10575 | | /* 28198 */ "LEA_ADDiu\0" |
10576 | | /* 28208 */ "LONG_BRANCH_ADDiu\0" |
10577 | | /* 28226 */ "SLTiu\0" |
10578 | | /* 28232 */ "SelTBtneZSltiu\0" |
10579 | | /* 28247 */ "SelTBteqZSltiu\0" |
10580 | | /* 28262 */ "SelTBtneZSltu\0" |
10581 | | /* 28276 */ "SelTBteqZSltu\0" |
10582 | | /* 28290 */ "Ulw\0" |
10583 | | /* 28294 */ "Usw\0" |
10584 | | }; |
10585 | | #ifdef __GNUC__ |
10586 | | #pragma GCC diagnostic pop |
10587 | | #endif |
10588 | | |
10589 | | extern const unsigned MipsInstrNameIndices[] = { |
10590 | | 15446U, 20991U, 22875U, 21308U, 15794U, 15775U, 15803U, 16055U, |
10591 | | 13802U, 13817U, 13682U, 13856U, 23453U, 13549U, 24785U, 13700U, |
10592 | | 15442U, 15784U, 13242U, 27043U, 13405U, 24689U, 11688U, 13189U, |
10593 | | 13230U, 22292U, 16027U, 24618U, 11778U, 22712U, 13919U, 24607U, |
10594 | | 13458U, 22462U, 22449U, 22944U, 24414U, 24446U, 15959U, 16006U, |
10595 | | 15979U, 15835U, 22909U, 22207U, 24826U, 24856U, 21133U, 11571U, |
10596 | | 10304U, 16211U, 25047U, 25077U, 16312U, 16319U, 16326U, 16336U, |
10597 | | 11651U, 23245U, 23208U, 13680U, 15444U, 26948U, 13559U, 16065U, |
10598 | | 24376U, 23387U, 24726U, 23404U, 23160U, 11190U, 23436U, 24629U, |
10599 | | 23331U, 24758U, 13604U, 22920U, 11747U, 11164U, 11729U, 24648U, |
10600 | | 21097U, 22969U, 11444U, 11388U, 11418U, 11429U, 11369U, 11399U, |
10601 | | 13512U, 13496U, 23483U, 13870U, 13887U, 11587U, 10310U, 11657U, |
10602 | | 11618U, 23250U, 23214U, 26918U, 21259U, 26901U, 21242U, 11527U, |
10603 | | 10276U, 26836U, 21177U, 22328U, 22306U, 13222U, 13961U, 11701U, |
10604 | | 24395U, 24704U, 11076U, 23513U, 24584U, 23540U, 24840U, 11182U, |
10605 | | 24573U, 24561U, 24679U, 13911U, 24819U, 13843U, 24849U, 15920U, |
10606 | | 23127U, 23113U, 15913U, 23120U, 23324U, 16112U, 22423U, 22416U, |
10607 | | 24386U, 21365U, 13267U, 21349U, 13214U, 21357U, 13259U, 21341U, |
10608 | | 13206U, 22276U, 22268U, 13984U, 13976U, 24294U, 24284U, 24274U, |
10609 | | 24264U, 24314U, 24304U, 26980U, 26990U, 24324U, 24337U, 27000U, |
10610 | | 27010U, 24350U, 24363U, 11485U, 10255U, 16153U, 8509U, 11362U, |
10611 | | 25014U, 16291U, 25267U, 15524U, 22764U, 1214U, 9U, 13904U, |
10612 | | 1196U, 0U, 22739U, 22771U, 13731U, 24811U, 11154U, 15472U, |
10613 | | 15496U, 22385U, 22394U, 23374U, 21148U, 23470U, 13613U, 21077U, |
10614 | | 21087U, 13316U, 13331U, 21034U, 21066U, 25107U, 25133U, 25119U, |
10615 | | 13275U, 13303U, 13288U, 11577U, 15669U, 21211U, 26870U, 21235U, |
10616 | | 26894U, 23381U, 11720U, 11710U, 22863U, 24470U, 24502U, 24481U, |
10617 | | 23175U, 27138U, 13662U, 27100U, 13644U, 22441U, 22350U, 13530U, |
10618 | | 15926U, 23429U, 21275U, 24735U, 23146U, 24640U, 24666U, 24768U, |
10619 | | 22888U, 13392U, 11216U, 13574U, 13481U, 11513U, 10262U, 16181U, |
10620 | | 25021U, 16298U, 8515U, 24743U, 22748U, 22988U, 23004U, 27034U, |
10621 | | 13434U, 13586U, 24428U, 22284U, 11492U, 16160U, 11468U, 16136U, |
10622 | | 26819U, 21160U, 21045U, 21013U, 11555U, 16195U, 11635U, 23230U, |
10623 | | 23192U, 26853U, 21194U, 26877U, 21218U, 26962U, 26969U, 27666U, |
10624 | | 21324U, 22697U, 21709U, 21793U, 22009U, 4073U, 9395U, 893U, |
10625 | | 8751U, 3098U, 9073U, 8379U, 9710U, 3955U, 9235U, 775U, |
10626 | | 8591U, 2928U, 8913U, 8267U, 9556U, 3996U, 9290U, 816U, |
10627 | | 8646U, 2969U, 8968U, 8306U, 9609U, 4153U, 9503U, 973U, |
10628 | | 8859U, 3244U, 9181U, 8455U, 9814U, 4037U, 9345U, 857U, |
10629 | | 8701U, 3062U, 9023U, 8345U, 9662U, 3975U, 9262U, 795U, |
10630 | | 8618U, 2948U, 8940U, 8286U, 9582U, 4113U, 9449U, 933U, |
10631 | | 8805U, 3138U, 9127U, 8417U, 9762U, 3935U, 9208U, 755U, |
10632 | | 8564U, 2908U, 8886U, 8248U, 9530U, 4132U, 9475U, 952U, |
10633 | | 8831U, 3223U, 9153U, 8435U, 9787U, 4016U, 9317U, 836U, |
10634 | | 8673U, 3041U, 8995U, 8325U, 9635U, 4093U, 9422U, 913U, |
10635 | | 8778U, 3118U, 9100U, 8398U, 9736U, 4057U, 9372U, 877U, |
10636 | | 8728U, 3082U, 9050U, 8364U, 9688U, 9870U, 22868U, 19569U, |
10637 | | 27772U, 13359U, 27709U, 15820U, 27733U, 24900U, 27904U, 16119U, |
10638 | | 27811U, 24437U, 27880U, 16102U, 27785U, 24969U, 27930U, 16217U, |
10639 | | 27852U, 13401U, 27721U, 15825U, 27746U, 24915U, 27917U, 16125U, |
10640 | | 27825U, 24477U, 27892U, 16107U, 27798U, 24974U, 27943U, 16223U, |
10641 | | 27866U, 27759U, 21407U, 21695U, 21588U, 21888U, 21779U, 21995U, |
10642 | | 17761U, 27487U, 27501U, 27415U, 27408U, 4677U, 4224U, 4705U, |
10643 | | 4254U, 4735U, 4766U, 4663U, 4209U, 4691U, 4239U, 4719U, |
10644 | | 4751U, 2786U, 3556U, 131U, 27048U, 21635U, 21935U, 149U, |
10645 | | 1153U, 27839U, 27636U, 27646U, 27675U, 16081U, 27354U, 23155U, |
10646 | | 27369U, 27612U, 27956U, 27588U, 27687U, 27624U, 27967U, 27600U, |
10647 | | 27698U, 28083U, 2799U, 3572U, 12481U, 26072U, 21373U, 21390U, |
10648 | | 21603U, 21903U, 4824U, 21423U, 22079U, 21470U, 22122U, 21618U, |
10649 | | 21446U, 22100U, 21918U, 21516U, 22164U, 21493U, 22143U, 21540U, |
10650 | | 22186U, 27450U, 27435U, 27463U, 27476U, 6961U, 27161U, 27171U, |
10651 | | 27543U, 12410U, 25936U, 3921U, 8223U, 2053U, 22474U, 22559U, |
10652 | | 28208U, 28019U, 28179U, 27997U, 27268U, 27978U, 3602U, 19113U, |
10653 | | 1121U, 3812U, 1088U, 3624U, 1111U, 3802U, 23027U, 1068U, |
10654 | | 23279U, 23044U, 23296U, 1151U, 26934U, 52U, 137U, 22515U, |
10655 | | 23265U, 112U, 15450U, 22251U, 1135U, 3841U, 21650U, 21950U, |
10656 | | 21673U, 21973U, 26941U, 64U, 155U, 22522U, 23272U, 119U, |
10657 | | 15461U, 22262U, 27840U, 27647U, 27676U, 5084U, 5217U, 5116U, |
10658 | | 5269U, 22432U, 27362U, 3735U, 21724U, 21808U, 22024U, 21725U, |
10659 | | 21809U, 22025U, 10050U, 9952U, 10165U, 14146U, 14041U, 14306U, |
10660 | | 25277U, 16261U, 25309U, 16277U, 26362U, 24530U, 28145U, 25035U, |
10661 | | 25065U, 15598U, 3157U, 27208U, 3667U, 5329U, 8200U, 20853U, |
10662 | | 7994U, 27181U, 3638U, 5299U, 8172U, 11544U, 24882U, 20297U, |
10663 | | 18093U, 15418U, 2847U, 18745U, 22234U, 3292U, 19134U, 10293U, |
10664 | | 24870U, 20282U, 18024U, 15429U, 2860U, 22599U, 18759U, 24542U, |
10665 | | 20261U, 28158U, 20954U, 14075U, 9987U, 27422U, 3826U, 25054U, |
10666 | | 388U, 2371U, 15561U, 2998U, 23795U, 644U, 2684U, 15637U, |
10667 | | 3202U, 24149U, 559U, 2599U, 15615U, 3176U, 24033U, 13133U, |
10668 | | 683U, 24182U, 25084U, 16082U, 27355U, 23156U, 27370U, 9840U, |
10669 | | 3906U, 212U, 27513U, 27551U, 27613U, 27957U, 27578U, 27657U, |
10670 | | 13363U, 27340U, 3717U, 24905U, 27384U, 3762U, 27377U, 3744U, |
10671 | | 27400U, 3782U, 13416U, 27347U, 3726U, 24920U, 27392U, 3772U, |
10672 | | 3753U, 3792U, 27568U, 27559U, 21563U, 21754U, 21838U, 21863U, |
10673 | | 22054U, 27589U, 27688U, 8235U, 2064U, 22488U, 22574U, 12468U, |
10674 | | 25994U, 3928U, 19120U, 21576U, 21767U, 21851U, 21876U, 22067U, |
10675 | | 28066U, 28074U, 27153U, 27145U, 28053U, 27298U, 28101U, 27326U, |
10676 | | 28247U, 28276U, 28040U, 27284U, 28088U, 27312U, 28232U, 28262U, |
10677 | | 5029U, 4488U, 4503U, 5041U, 5256U, 15934U, 13756U, 13738U, |
10678 | | 13772U, 13788U, 13831U, 2817U, 9888U, 2009U, 18304U, 6838U, |
10679 | | 19044U, 6970U, 22301U, 19165U, 27528U, 27625U, 27968U, 27601U, |
10680 | | 27699U, 27229U, 28174U, 28290U, 27233U, 28294U, 21739U, 21823U, |
10681 | | 22039U, 14265U, 18560U, 10110U, 1362U, 26290U, 20728U, 11464U, |
10682 | | 11251U, 18046U, 6015U, 19245U, 16993U, 17406U, 19417U, 7880U, |
10683 | | 14066U, 1465U, 14183U, 1520U, 26033U, 1878U, 25595U, 1850U, |
10684 | | 14138U, 18456U, 14245U, 18547U, 26272U, 20716U, 3410U, 11275U, |
10685 | | 18057U, 10348U, 11851U, 14545U, 25348U, 10756U, 12650U, 15034U, |
10686 | | 26317U, 10948U, 13015U, 15283U, 26666U, 17623U, 5755U, 9978U, |
10687 | | 1267U, 10088U, 1330U, 7850U, 14330U, 1608U, 10190U, 17947U, |
10688 | | 14285U, 1580U, 10130U, 17894U, 10562U, 12215U, 14730U, 25713U, |
10689 | | 11018U, 13096U, 15353U, 26756U, 11308U, 18066U, 10332U, 11834U, |
10690 | | 14529U, 25331U, 18100U, 6237U, 27238U, 20877U, 28192U, 20973U, |
10691 | | 28125U, 20931U, 21120U, 7028U, 11244U, 6003U, 11631U, 17434U, |
10692 | | 5596U, 2187U, 17461U, 5629U, 10437U, 6893U, 18107U, 6246U, |
10693 | | 25193U, 27243U, 3690U, 20885U, 11681U, 1422U, 10661U, 12497U, |
10694 | | 14883U, 26119U, 10853U, 12862U, 15141U, 26513U, 15492U, 11238U, |
10695 | | 5992U, 6921U, 10738U, 12632U, 15007U, 26299U, 10930U, 12997U, |
10696 | | 15265U, 26648U, 10686U, 12571U, 14946U, 26193U, 10878U, 12936U, |
10697 | | 15204U, 26587U, 4556U, 4432U, 4940U, 4584U, 4381U, 4880U, |
10698 | | 4448U, 5243U, 5182U, 17418U, 28124U, 15679U, 11088U, 5871U, |
10699 | | 21119U, 1783U, 85U, 231U, 225U, 239U, 11059U, 5536U, |
10700 | | 27107U, 6178U, 13639U, 15855U, 18276U, 27074U, 6141U, 24259U, |
10701 | | 16096U, 20222U, 27114U, 6191U, 27081U, 6154U, 10498U, 12165U, |
10702 | | 14680U, 25663U, 10632U, 12416U, 14854U, 25942U, 5834U, 22780U, |
10703 | | 3312U, 11270U, 2104U, 6038U, 16086U, 17668U, 11123U, 5931U, |
10704 | | 11332U, 5583U, 2163U, 18084U, 6204U, 19466U, 11062U, 2076U, |
10705 | | 5842U, 11286U, 2123U, 6077U, 27064U, 3510U, 15687U, 11099U, |
10706 | | 5892U, 16039U, 19738U, 18879U, 11314U, 2139U, 6119U, 16237U, |
10707 | | 20814U, 27128U, 3542U, 11131U, 5944U, 11338U, 2171U, 6215U, |
10708 | | 16249U, 20837U, 10474U, 12141U, 14656U, 25639U, 10604U, 12264U, |
10709 | | 14757U, 25756U, 10528U, 12181U, 14696U, 25679U, 10646U, 12460U, |
10710 | | 14868U, 25986U, 25002U, 20361U, 22359U, 7048U, 27069U, 3517U, |
10711 | | 11107U, 5905U, 11320U, 2147U, 6130U, 16243U, 20822U, 11281U, |
10712 | | 2116U, 6067U, 11292U, 2131U, 6088U, 27133U, 3549U, 15694U, |
10713 | | 11139U, 5957U, 16047U, 19749U, 18889U, 11344U, 2179U, 6226U, |
10714 | | 16255U, 20845U, 10577U, 25242U, 10570U, 25230U, 13430U, 2780U, |
10715 | | 11067U, 2083U, 5852U, 10444U, 12119U, 14634U, 25617U, 10416U, |
10716 | | 12098U, 14613U, 25521U, 15830U, 17658U, 11115U, 5918U, 11326U, |
10717 | | 5570U, 2155U, 18075U, 6167U, 18207U, 11298U, 6099U, 11053U, |
10718 | | 13170U, 15388U, 25236U, 26813U, 11303U, 6109U, 746U, 1942U, |
10719 | | 16935U, 15658U, 17489U, 5651U, 18863U, 6950U, 10452U, 25206U, |
10720 | | 10546U, 12199U, 14714U, 25697U, 10825U, 12739U, 15113U, 26430U, |
10721 | | 11048U, 13156U, 15383U, 25225U, 26808U, 4967U, 4613U, 4979U, |
10722 | | 4626U, 4955U, 4600U, 4866U, 5291U, 4790U, 5283U, 4781U, |
10723 | | 13371U, 13346U, 18135U, 18161U, 6781U, 8116U, 2466U, 6444U, |
10724 | | 23888U, 7428U, 713U, 2747U, 6713U, 20554U, 24208U, 20186U, |
10725 | | 7709U, 10483U, 12150U, 14665U, 25648U, 10619U, 12334U, 14780U, |
10726 | | 25839U, 101U, 16384U, 16977U, 9851U, 23419U, 1015U, 1048U, |
10727 | | 1102U, 12489U, 6586U, 24025U, 7570U, 10694U, 12579U, 14954U, |
10728 | | 26201U, 10886U, 12944U, 15212U, 26595U, 10678U, 12563U, 14938U, |
10729 | | 26185U, 10870U, 12928U, 15196U, 26579U, 22230U, 19127U, 7039U, |
10730 | | 8148U, 10712U, 12597U, 14972U, 26219U, 10904U, 12962U, 15230U, |
10731 | | 26613U, 10773U, 12667U, 15051U, 26334U, 10976U, 13043U, 15311U, |
10732 | | 26694U, 27096U, 20830U, 7973U, 8165U, 10025U, 1281U, 9927U, |
10733 | | 1235U, 10140U, 1377U, 10038U, 17852U, 9940U, 17779U, 10153U, |
10734 | | 17907U, 10056U, 17867U, 9958U, 17794U, 10171U, 17922U, 6363U, |
10735 | | 7323U, 12394U, 6572U, 14152U, 18467U, 24009U, 7556U, 12090U, |
10736 | | 23814U, 11996U, 6334U, 14047U, 18386U, 23740U, 7294U, 12807U, |
10737 | | 6645U, 14312U, 18587U, 24110U, 7629U, 12057U, 6348U, 23749U, |
10738 | | 7308U, 12347U, 6526U, 23963U, 7510U, 11949U, 6288U, 23694U, |
10739 | | 7248U, 12760U, 6599U, 24064U, 7583U, 12373U, 6541U, 23973U, |
10740 | | 7525U, 11975U, 6303U, 23704U, 7263U, 12786U, 6614U, 24074U, |
10741 | | 7598U, 12307U, 6497U, 23921U, 7481U, 12384U, 6557U, 23992U, |
10742 | | 7541U, 11986U, 6319U, 23723U, 7279U, 12797U, 6630U, 24093U, |
10743 | | 7614U, 12317U, 6512U, 23938U, 7496U, 10808U, 12722U, 15096U, |
10744 | | 26413U, 11000U, 15335U, 26738U, 9865U, 9872U, 11451U, 13953U, |
10745 | | 25256U, 11350U, 13936U, 25249U, 126U, 16400U, 16985U, 9858U, |
10746 | | 23583U, 19784U, 25283U, 20473U, 16267U, 23593U, 19797U, 25315U, |
10747 | | 20486U, 7002U, 2489U, 17191U, 6473U, 23907U, 19991U, 7457U, |
10748 | | 3493U, 3460U, 3448U, 549U, 16796U, 2589U, 17279U, 16283U, |
10749 | | 7015U, 3269U, 3477U, 26368U, 20740U, 7948U, 736U, 16922U, |
10750 | | 2770U, 17393U, 24227U, 20211U, 7738U, 531U, 16772U, 2571U, |
10751 | | 17255U, 24002U, 20045U, 380U, 16633U, 2363U, 17143U, 23789U, |
10752 | | 19927U, 353U, 16597U, 2336U, 17119U, 23733U, 19897U, 606U, |
10753 | | 16848U, 2646U, 17331U, 24103U, 20098U, 312U, 16544U, 2295U, |
10754 | | 17066U, 23669U, 19852U, 322U, 16557U, 2305U, 17079U, 23677U, |
10755 | | 19863U, 440U, 16684U, 2423U, 17166U, 23853U, 19970U, 576U, |
10756 | | 16809U, 2616U, 17292U, 24048U, 20065U, 333U, 16571U, 2316U, |
10757 | | 17093U, 23686U, 19875U, 586U, 16822U, 2626U, 17305U, 24056U, |
10758 | | 20076U, 511U, 16746U, 2551U, 17229U, 23955U, 20023U, 362U, |
10759 | | 16609U, 2345U, 17131U, 23775U, 19907U, 521U, 16759U, 2561U, |
10760 | | 17242U, 23984U, 20034U, 343U, 16584U, 2326U, 17106U, 23715U, |
10761 | | 19886U, 596U, 16835U, 2636U, 17318U, 24085U, 20087U, 483U, |
10762 | | 16709U, 2523U, 17204U, 23931U, 20002U, 5064U, 4903U, 4530U, |
10763 | | 11463U, 27237U, 28191U, 28130U, 15413U, 21126U, 15481U, 15491U, |
10764 | | 22358U, 22229U, 8147U, 27095U, 8164U, 25009U, 24990U, 24408U, |
10765 | | 20230U, 7790U, 24806U, 1058U, 21007U, 24984U, 15400U, 23424U, |
10766 | | 21001U, 24963U, 25010U, 24991U, 7901U, 7911U, 10792U, 12706U, |
10767 | | 15070U, 26387U, 10984U, 13071U, 15319U, 26722U, 18723U, 6895U, |
10768 | | 9846U, 8079U, 18U, 106U, 1174U, 21282U, 24U, 11773U, |
10769 | | 24894U, 24553U, 58U, 143U, 1180U, 21295U, 45U, 14518U, |
10770 | | 24925U, 16131U, 24536U, 28151U, 24951U, 8139U, 12623U, 14998U, |
10771 | | 26254U, 12988U, 15256U, 26639U, 12545U, 14920U, 26167U, 12910U, |
10772 | | 15178U, 26561U, 14394U, 1665U, 14469U, 1717U, 25778U, 20564U, |
10773 | | 14431U, 18636U, 15745U, 18952U, 22841U, 19541U, 14495U, 1753U, |
10774 | | 14374U, 1635U, 22436U, 14408U, 1684U, 14482U, 1735U, 25790U, |
10775 | | 20579U, 14457U, 18668U, 12515U, 14901U, 26137U, 12880U, 15159U, |
10776 | | 26531U, 15756U, 18966U, 22852U, 19555U, 14505U, 1768U, 14422U, |
10777 | | 1703U, 23318U, 1007U, 25181U, 13943U, 25041U, 11603U, 16060U, |
10778 | | 993U, 1038U, 25095U, 8559U, 247U, 24996U, 16091U, 1000U, |
10779 | | 25101U, 10250U, 28118U, 25071U, 22731U, 13471U, 7120U, 5150U, |
10780 | | 5128U, 9884U, 17766U, 5786U, 15405U, 18731U, 6903U, 24557U, |
10781 | | 24409U, 11147U, 5970U, 20231U, 7791U, 22735U, 13476U, 7129U, |
10782 | | 24807U, 22692U, 22378U, 25167U, 20424U, 19190U, 25175U, 20435U, |
10783 | | 19444U, 26099U, 20678U, 26062U, 20652U, 15078U, 18701U, 26793U, |
10784 | | 20764U, 26089U, 20665U, 26043U, 20627U, 15016U, 18689U, 26000U, |
10785 | | 20605U, 23578U, 1022U, 20275U, 7822U, 540U, 16784U, 2580U, |
10786 | | 17267U, 24018U, 20055U, 11898U, 293U, 16519U, 2276U, 17054U, |
10787 | | 3372U, 23654U, 19831U, 7236U, 25395U, 12043U, 25500U, 12333U, |
10788 | | 25838U, 12488U, 26110U, 11935U, 25432U, 12746U, 26437U, 502U, |
10789 | | 16734U, 2542U, 1029U, 16965U, 12005U, 25462U, 12430U, 25956U, |
10790 | | 12357U, 25852U, 11959U, 25446U, 12770U, 26451U, 12019U, 25476U, |
10791 | | 12293U, 25809U, 13119U, 665U, 16898U, 2705U, 17369U, 24168U, |
10792 | | 20140U, 7655U, 26779U, 14772U, 25823U, 11806U, 25301U, 12242U, |
10793 | | 25734U, 12444U, 25970U, 12675U, 26342U, 13051U, 26702U, 12251U, |
10794 | | 25743U, 12453U, 25979U, 10585U, 12229U, 14738U, 25721U, 11798U, |
10795 | | 25293U, 2477U, 6458U, 23897U, 7442U, 724U, 2758U, 6727U, |
10796 | | 20594U, 24217U, 20198U, 7723U, 11905U, 25402U, 11860U, 25357U, |
10797 | | 13149U, 26801U, 11842U, 25339U, 12286U, 25802U, 674U, 16910U, |
10798 | | 2714U, 17381U, 6671U, 24175U, 20150U, 7667U, 11876U, 25373U, |
10799 | | 12272U, 450U, 16697U, 2433U, 17179U, 3391U, 23861U, 19981U, |
10800 | | 7386U, 25764U, 409U, 16644U, 2392U, 17154U, 23822U, 19936U, |
10801 | | 7363U, 15664U, 12326U, 25831U, 12823U, 26474U, 12848U, 26499U, |
10802 | | 12050U, 25507U, 12340U, 25845U, 11942U, 25439U, 12753U, 26444U, |
10803 | | 12012U, 25469U, 12437U, 25963U, 12840U, 615U, 16860U, 2655U, |
10804 | | 17343U, 24126U, 20108U, 26491U, 11869U, 274U, 16494U, 2257U, |
10805 | | 17042U, 3362U, 23639U, 19810U, 7224U, 25366U, 12365U, 25860U, |
10806 | | 11967U, 25454U, 12778U, 26459U, 12027U, 25484U, 12300U, 25816U, |
10807 | | 12685U, 26352U, 13061U, 26712U, 14786U, 25868U, 12525U, 26147U, |
10808 | | 12890U, 26541U, 15505U, 6939U, 24800U, 7811U, 12536U, 14911U, |
10809 | | 26158U, 12901U, 15169U, 26552U, 12506U, 14892U, 26128U, 12871U, |
10810 | | 15150U, 26522U, 15943U, 19056U, 11033U, 13111U, 15368U, 26771U, |
10811 | | 10612U, 12279U, 14765U, 25771U, 10393U, 11927U, 14590U, 25424U, |
10812 | | 10654U, 12474U, 14876U, 26007U, 23420U, 10839U, 12831U, 15127U, |
10813 | | 26482U, 25188U, 10401U, 12035U, 14598U, 25492U, 20453U, 19760U, |
10814 | | 7191U, 15656U, 15683U, 23137U, 17565U, 3323U, 5557U, 5795U, |
10815 | | 6048U, 17584U, 19767U, 9908U, 2033U, 19658U, 19730U, 27020U, |
10816 | | 20791U, 18872U, 11093U, 2096U, 5881U, 11072U, 2090U, 5862U, |
10817 | | 23134U, 17557U, 3318U, 22682U, 17425U, 5546U, 7094U, 9902U, |
10818 | | 2025U, 8052U, 8087U, 19652U, 18858U, 4874U, 3914U, 4807U, |
10819 | | 4799U, 5013U, 4845U, 9916U, 2043U, 13185U, 18114U, 17604U, |
10820 | | 27025U, 20799U, 7831U, 17773U, 5809U, 28114U, 3857U, 13629U, |
10821 | | 18260U, 20916U, 11611U, 91U, 1957U, 5498U, 459U, 2499U, |
10822 | | 1164U, 5416U, 8020U, 1922U, 10431U, 12113U, 14628U, 25611U, |
10823 | | 15767U, 11233U, 22901U, 171U, 1971U, 10380U, 11914U, 14577U, |
10824 | | 25411U, 28198U, 3876U, 20969U, 13981U, 2837U, 13377U, 18170U, |
10825 | | 17633U, 26976U, 20784U, 18334U, 28136U, 3863U, 13634U, 18268U, |
10826 | | 20939U, 17481U, 5641U, 15940U, 3264U, 8071U, 11614U, 8109U, |
10827 | | 13412U, 18184U, 19050U, 6976U, 8133U, 9847U, 5777U, 8080U, |
10828 | | 6930U, 183U, 1987U, 16432U, 27280U, 3711U, 20909U, 25264U, |
10829 | | 17642U, 3488U, 161U, 16416U, 1186U, 5478U, 8036U, 1932U, |
10830 | | 22529U, 19276U, 13596U, 18246U, 19218U, 16229U, 3280U, 13420U, |
10831 | | 18191U, 19099U, 17518U, 5686U, 16947U, 11265U, 6028U, 19452U, |
10832 | | 23366U, 3350U, 13520U, 18221U, 19716U, 19428U, 11259U, 20346U, |
10833 | | 27030U, 195U, 16450U, 19776U, 20807U, 20461U, 7932U, 28170U, |
10834 | | 4283U, 4347U, 4315U, 4364U, 4893U, 4634U, 4519U, 4993U, |
10835 | | 4650U, 4400U, 4462U, 11550U, 12075U, 6390U, 23767U, 7350U, |
10836 | | 14828U, 25910U, 24888U, 22662U, 19391U, 20303U, 11017U, 13095U, |
10837 | | 15352U, 26755U, 303U, 16532U, 2286U, 22550U, 19306U, 18099U, |
10838 | | 14801U, 25883U, 23662U, 19842U, 15861U, 18980U, 23061U, 19588U, |
10839 | | 15887U, 19012U, 23087U, 19620U, 11827U, 6276U, 23632U, 7212U, |
10840 | | 10721U, 12606U, 14981U, 26228U, 10913U, 12971U, 15239U, 26622U, |
10841 | | 10357U, 11861U, 14554U, 25358U, 13150U, 6742U, 24235U, 10800U, |
10842 | | 12714U, 15088U, 7751U, 26405U, 10992U, 13079U, 15327U, 26730U, |
10843 | | 19U, 5354U, 107U, 2193U, 16392U, 5396U, 1175U, 5436U, |
10844 | | 25U, 16346U, 5364U, 254U, 16468U, 2202U, 17004U, 5446U, |
10845 | | 31U, 16355U, 15424U, 17471U, 2853U, 22590U, 19318U, 18751U, |
10846 | | 22240U, 17536U, 3298U, 22625U, 19342U, 19140U, 23313U, 11814U, |
10847 | | 6264U, 23625U, 7200U, 10703U, 12588U, 14963U, 26210U, 10895U, |
10848 | | 12953U, 15221U, 26604U, 10340U, 11843U, 14537U, 25340U, 12287U, |
10849 | | 6486U, 23915U, 10730U, 12615U, 14990U, 7470U, 26246U, 10922U, |
10850 | | 12980U, 15248U, 26631U, 11774U, 10248U, 18014U, 24895U, 7860U, |
10851 | | 6255U, 10670U, 12555U, 14930U, 26177U, 10862U, 12920U, 15188U, |
10852 | | 26571U, 17443U, 5607U, 19200U, 7072U, 25199U, 371U, 16621U, |
10853 | | 2354U, 15554U, 2989U, 18818U, 23782U, 19917U, 2231U, 15532U, |
10854 | | 2882U, 23603U, 418U, 16656U, 2401U, 15580U, 3019U, 18828U, |
10855 | | 23829U, 19946U, 635U, 16886U, 2675U, 15630U, 3193U, 18838U, |
10856 | | 24142U, 20130U, 2244U, 15543U, 2895U, 23614U, 429U, 16670U, |
10857 | | 2412U, 15589U, 3030U, 18848U, 23838U, 19958U, 10299U, 12067U, |
10858 | | 6377U, 23759U, 7337U, 14818U, 25900U, 24876U, 22652U, 19378U, |
10859 | | 20288U, 11009U, 13087U, 15344U, 26747U, 284U, 16507U, 2267U, |
10860 | | 22541U, 19294U, 18030U, 14792U, 25874U, 23647U, 19821U, 59U, |
10861 | | 5386U, 144U, 2222U, 17030U, 16408U, 5406U, 1181U, 5468U, |
10862 | | 46U, 16375U, 5375U, 264U, 16481U, 2212U, 17017U, 5457U, |
10863 | | 38U, 16365U, 15456U, 2875U, 22616U, 19330U, 18775U, 22409U, |
10864 | | 19226U, 22257U, 3305U, 22634U, 19354U, 19157U, 75U, 207U, |
10865 | | 1204U, 80U, 220U, 1209U, 23342U, 14519U, 24926U, 7870U, |
10866 | | 6873U, 16132U, 15899U, 19027U, 23099U, 19635U, 15701U, 18899U, |
10867 | | 22797U, 19488U, 14205U, 18507U, 26079U, 1893U, 14255U, 1550U, |
10868 | | 26281U, 1908U, 3420U, 14838U, 25920U, 14443U, 18651U, 14383U, |
10869 | | 1649U, 24537U, 22672U, 19404U, 22643U, 19366U, 20267U, 28152U, |
10870 | | 20960U, 24946U, 7891U, 11041U, 13126U, 15376U, 26786U, 19092U, |
10871 | | 6993U, 14123U, 1492U, 14810U, 25892U, 8140U, 14226U, 1536U, |
10872 | | 4859U, 4986U, 4173U, 3896U, 10365U, 11884U, 14562U, 25381U, |
10873 | | 10372U, 11891U, 14569U, 25388U, 302U, 16531U, 2285U, 23661U, |
10874 | | 19841U, 283U, 16506U, 2266U, 23646U, 19820U, 23142U, 3330U, |
10875 | | 10514U, 19666U, 7138U, 25213U, 17595U, 5732U, 5054U, 5095U, |
10876 | | 23143U, 17576U, 5722U, 3331U, 10515U, 6912U, 19667U, 7139U, |
10877 | | 25214U, 27259U, 3698U, 20894U, 5194U, 14113U, 18432U, 13543U, |
10878 | | 18237U, 6804U, 11025U, 13103U, 15360U, 26763U, 10385U, 11919U, |
10879 | | 14582U, 25416U, 10832U, 12816U, 15120U, 26467U, 14081U, 18399U, |
10880 | | 9993U, 17808U, 3382U, 3430U, 22437U, 15730U, 8493U, 17696U, |
10881 | | 18934U, 22826U, 8543U, 17733U, 19523U, 15874U, 18996U, 23074U, |
10882 | | 19604U, 15716U, 8478U, 17678U, 18917U, 22812U, 8528U, 17715U, |
10883 | | 19506U, 14025U, 18367U, 25543U, 20521U, 14000U, 18351U, 25572U, |
10884 | | 20536U, 14013U, 1434U, 25528U, 1795U, 25555U, 1815U, 13695U, |
10885 | | 13353U, 18145U, 20775U, 18284U, 6815U, 8125U, 11673U, 1409U, |
10886 | | 3401U, 3439U, 10234U, 17994U, 22503U, 19258U, 23360U, 3342U, |
10887 | | 19707U, 7180U, 7156U, 492U, 16721U, 2532U, 17216U, 23947U, |
10888 | | 20012U, 14356U, 18624U, 10216U, 17970U, 14097U, 18421U, 10009U, |
10889 | | 17830U, 12824U, 6659U, 24119U, 7643U, 23319U, 25182U, 20444U, |
10890 | | 19680U, 2454U, 6429U, 23878U, 7413U, 701U, 2735U, 6698U, |
10891 | | 20510U, 24198U, 20173U, 7694U, 625U, 16873U, 2665U, 17356U, |
10892 | | 24134U, 20119U, 4814U, 4190U, 8474U, 11357U, 10765U, 12659U, |
10893 | | 15043U, 26326U, 10968U, 13035U, 15303U, 26686U, 10245U, 17417U, |
10894 | | 5526U, 2048U, 13202U, 18121U, 18008U, 5817U, 11278U, 2111U, |
10895 | | 8063U, 11459U, 8102U, 13255U, 18128U, 18060U, 6059U, 8096U, |
10896 | | 11795U, 22367U, 17546U, 5708U, 19173U, 7061U, 8155U, 96U, |
10897 | | 1964U, 5512U, 471U, 2511U, 1169U, 5426U, 8028U, 1927U, |
10898 | | 25042U, 20371U, 15771U, 22905U, 177U, 1979U, 9880U, 2003U, |
10899 | | 17759U, 13972U, 2831U, 18327U, 27121U, 3533U, 13176U, 6767U, |
10900 | | 7982U, 24250U, 7776U, 27088U, 3524U, 13161U, 6753U, 7961U, |
10901 | | 24241U, 7762U, 12223U, 6403U, 23847U, 7375U, 22784U, 27253U, |
10902 | | 14515U, 17453U, 5619U, 2842U, 13381U, 18177U, 10410U, 14607U, |
10903 | | 25515U, 22245U, 25160U, 20414U, 19148U, 14347U, 18612U, 10207U, |
10904 | | 17958U, 14295U, 18573U, 26395U, 20751U, 14089U, 18410U, 10001U, |
10905 | | 17819U, 14216U, 18521U, 26237U, 20692U, 14338U, 18600U, 10198U, |
10906 | | 1395U, 14194U, 18493U, 10099U, 1346U, 26052U, 20639U, 13992U, |
10907 | | 18340U, 9919U, 1222U, 14162U, 18480U, 10067U, 1299U, 26014U, |
10908 | | 20615U, 14365U, 1621U, 10225U, 17982U, 14105U, 1479U, 10017U, |
10909 | | 17841U, 18683U, 6865U, 13385U, 6792U, 10430U, 12112U, 14627U, |
10910 | | 25610U, 10379U, 11913U, 14576U, 25410U, 16061U, 17500U, 5664U, |
10911 | | 1039U, 3593U, 10460U, 12127U, 14642U, 25625U, 25096U, 20387U, |
10912 | | 10592U, 12236U, 14745U, 19078U, 6984U, 25728U, 24522U, 3471U, |
10913 | | 20247U, 27263U, 3704U, 20901U, 28226U, 3888U, 20982U, 28140U, |
10914 | | 3869U, 20946U, 13450U, 27248U, 10537U, 12190U, 14705U, 25688U, |
10915 | | 10817U, 12731U, 15105U, 26422U, 8560U, 10423U, 12105U, 14620U, |
10916 | | 25603U, 10490U, 12157U, 14672U, 25655U, 10625U, 12403U, 14847U, |
10917 | | 25929U, 24997U, 20353U, 10326U, 11821U, 14523U, 17752U, 25325U, |
10918 | | 16092U, 17509U, 5675U, 10467U, 12134U, 14649U, 25632U, 10506U, |
10919 | | 12173U, 14688U, 25671U, 10639U, 12423U, 14861U, 25949U, 25102U, |
10920 | | 20395U, 10598U, 12258U, 14751U, 19085U, 25750U, 22430U, 19236U, |
10921 | | 7083U, 10848U, 12857U, 15136U, 26508U, 10251U, 14057U, 1451U, |
10922 | | 14172U, 1504U, 26023U, 1863U, 25587U, 1837U, 14130U, 18445U, |
10923 | | 14235U, 18534U, 26263U, 20704U, 10957U, 13024U, 15292U, 26675U, |
10924 | | 10781U, 12695U, 15059U, 26376U, 10747U, 12641U, 15025U, 26308U, |
10925 | | 10939U, 13006U, 15274U, 26657U, 17613U, 5743U, 9969U, 1253U, |
10926 | | 10077U, 1314U, 7840U, 14322U, 1595U, 10182U, 17936U, 14275U, |
10927 | | 1565U, 10120U, 17881U, 10554U, 12207U, 14722U, 25705U, 11010U, |
10928 | | 13088U, 15345U, 26748U, 18017U, 5825U, 28119U, 20923U, 189U, |
10929 | | 1995U, 16441U, 25274U, 17650U, 5767U, 3505U, 166U, 16424U, |
10930 | | 1191U, 5488U, 8044U, 1937U, 22535U, 19285U, 13600U, 18253U, |
10931 | | 16233U, 3286U, 13425U, 18199U, 19106U, 17527U, 5697U, 16956U, |
10932 | | 19459U, 23370U, 3356U, 13525U, 18229U, 19723U, 19436U, 7110U, |
10933 | | 201U, 16459U, 20467U, 7940U, 11211U, 15394U, 18714U, 6882U, |
10934 | | 18038U, 5982U, 15951U, 19067U, 4838U, 4201U, 4299U, 5005U, |
10935 | | 5021U, 4331U, 4269U, 5160U, 5074U, 4915U, 4543U, 4927U, |
10936 | | 4570U, 5105U, 4183U, 5139U, 4276U, 5171U, 5230U, 4416U, |
10937 | | 4475U, 22788U, 15467U, 18783U, 19473U, 13367U, 15403U, 24931U, |
10938 | | 20320U, 18729U, 24910U, 20312U, 18154U, 25152U, 13722U, 18292U, |
10939 | | 20403U, 22403U, 19209U, 23021U, 19579U, 15517U, 18808U, 23353U, |
10940 | | 19697U, 25145U, 13714U, 6825U, 7920U, 22373U, 19182U, 22792U, |
10941 | | 19480U, 15511U, 18799U, 23347U, 19688U, 24526U, 15486U, 20329U, |
10942 | | 18791U, 24979U, 20338U, 20254U, 13454U, 15408U, 18737U, 18214U, |
10943 | | 2442U, 6414U, 23868U, 7398U, 689U, 2723U, 6683U, 20499U, |
10944 | | 24188U, 20160U, 7679U, 24937U, 25072U, 20379U, 24944U, 70U, |
10945 | | 24957U, 10409U, 12083U, 14606U, 25514U, 24441U, 20239U, 7801U, |
10946 | | 22509U, 19267U, 7168U, 13948U, 18319U, 6855U, 23204U, 17575U, |
10947 | | 5721U, 3336U, 10521U, 6911U, 19673U, 7147U, 25219U, 27258U, |
10948 | | 3697U, 20893U, 5205U, 11608U, |
10949 | | }; |
10950 | | |
10951 | 5 | static inline void InitMipsMCInstrInfo(MCInstrInfo *II) { |
10952 | 5 | II->InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2868); |
10953 | 5 | } |
10954 | | |
10955 | | } // end namespace llvm |
10956 | | #endif // GET_INSTRINFO_MC_DESC |
10957 | | |
10958 | | #ifdef GET_INSTRINFO_HEADER |
10959 | | #undef GET_INSTRINFO_HEADER |
10960 | | namespace llvm { |
10961 | | struct MipsGenInstrInfo : public TargetInstrInfo { |
10962 | | explicit MipsGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u); |
10963 | | ~MipsGenInstrInfo() override = default; |
10964 | | |
10965 | | }; |
10966 | | } // end namespace llvm |
10967 | | #endif // GET_INSTRINFO_HEADER |
10968 | | |
10969 | | #ifdef GET_INSTRINFO_HELPER_DECLS |
10970 | | #undef GET_INSTRINFO_HELPER_DECLS |
10971 | | |
10972 | | |
10973 | | #endif // GET_INSTRINFO_HELPER_DECLS |
10974 | | |
10975 | | #ifdef GET_INSTRINFO_HELPERS |
10976 | | #undef GET_INSTRINFO_HELPERS |
10977 | | |
10978 | | #endif // GET_INSTRINFO_HELPERS |
10979 | | |
10980 | | #ifdef GET_INSTRINFO_CTOR_DTOR |
10981 | | #undef GET_INSTRINFO_CTOR_DTOR |
10982 | | namespace llvm { |
10983 | | extern const MipsInstrTable MipsDescs; |
10984 | | extern const unsigned MipsInstrNameIndices[]; |
10985 | | extern const char MipsInstrNameData[]; |
10986 | | MipsGenInstrInfo::MipsGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode) |
10987 | 78 | : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) { |
10988 | 78 | InitMCInstrInfo(MipsDescs.Insts, MipsInstrNameIndices, MipsInstrNameData, nullptr, nullptr, 2868); |
10989 | 78 | } |
10990 | | } // end namespace llvm |
10991 | | #endif // GET_INSTRINFO_CTOR_DTOR |
10992 | | |
10993 | | #ifdef GET_INSTRINFO_OPERAND_ENUM |
10994 | | #undef GET_INSTRINFO_OPERAND_ENUM |
10995 | | namespace llvm { |
10996 | | namespace Mips { |
10997 | | namespace OpName { |
10998 | | enum { |
10999 | | OPERAND_LAST |
11000 | | }; |
11001 | | } // end namespace OpName |
11002 | | } // end namespace Mips |
11003 | | } // end namespace llvm |
11004 | | #endif //GET_INSTRINFO_OPERAND_ENUM |
11005 | | |
11006 | | #ifdef GET_INSTRINFO_NAMED_OPS |
11007 | | #undef GET_INSTRINFO_NAMED_OPS |
11008 | | namespace llvm { |
11009 | | namespace Mips { |
11010 | | LLVM_READONLY |
11011 | | int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) { |
11012 | | return -1; |
11013 | | } |
11014 | | } // end namespace Mips |
11015 | | } // end namespace llvm |
11016 | | #endif //GET_INSTRINFO_NAMED_OPS |
11017 | | |
11018 | | #ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM |
11019 | | #undef GET_INSTRINFO_OPERAND_TYPES_ENUM |
11020 | | namespace llvm { |
11021 | | namespace Mips { |
11022 | | namespace OpTypes { |
11023 | | enum OperandType { |
11024 | | InvertedImOperand = 0, |
11025 | | InvertedImOperand64 = 1, |
11026 | | PtrRC = 2, |
11027 | | brtarget = 3, |
11028 | | brtarget1SImm16 = 4, |
11029 | | brtarget7_mm = 5, |
11030 | | brtarget10_mm = 6, |
11031 | | brtarget21 = 7, |
11032 | | brtarget21_mm = 8, |
11033 | | brtarget26 = 9, |
11034 | | brtarget26_mm = 10, |
11035 | | brtarget_lsl2_mm = 11, |
11036 | | brtarget_mm = 12, |
11037 | | brtargetr6 = 13, |
11038 | | calloffset16 = 14, |
11039 | | calltarget = 15, |
11040 | | calltarget_mm = 16, |
11041 | | condcode = 17, |
11042 | | cpinst_operand = 18, |
11043 | | f32imm = 19, |
11044 | | f64imm = 20, |
11045 | | i1imm = 21, |
11046 | | i8imm = 22, |
11047 | | i16imm = 23, |
11048 | | i32imm = 24, |
11049 | | i64imm = 25, |
11050 | | imm64 = 26, |
11051 | | jmpoffset16 = 27, |
11052 | | jmptarget = 28, |
11053 | | jmptarget_mm = 29, |
11054 | | li16_imm = 30, |
11055 | | mem = 31, |
11056 | | mem16 = 32, |
11057 | | mem16_ea = 33, |
11058 | | mem16sp = 34, |
11059 | | mem_ea = 35, |
11060 | | mem_mm_4 = 36, |
11061 | | mem_mm_4_lsl1 = 37, |
11062 | | mem_mm_4_lsl2 = 38, |
11063 | | mem_mm_4sp = 39, |
11064 | | mem_mm_9 = 40, |
11065 | | mem_mm_11 = 41, |
11066 | | mem_mm_12 = 42, |
11067 | | mem_mm_16 = 43, |
11068 | | mem_mm_gp_simm7_lsl2 = 44, |
11069 | | mem_mm_sp_imm5_lsl2 = 45, |
11070 | | mem_msa = 46, |
11071 | | mem_simm9 = 47, |
11072 | | mem_simm9_exp = 48, |
11073 | | mem_simm10 = 49, |
11074 | | mem_simm10_lsl1 = 50, |
11075 | | mem_simm10_lsl2 = 51, |
11076 | | mem_simm10_lsl3 = 52, |
11077 | | mem_simm11 = 53, |
11078 | | mem_simm12 = 54, |
11079 | | mem_simm16 = 55, |
11080 | | mem_simmptr = 56, |
11081 | | pcrel16 = 57, |
11082 | | ptype0 = 58, |
11083 | | ptype1 = 59, |
11084 | | ptype2 = 60, |
11085 | | ptype3 = 61, |
11086 | | ptype4 = 62, |
11087 | | ptype5 = 63, |
11088 | | reglist = 64, |
11089 | | reglist16 = 65, |
11090 | | simm3_lsa2 = 66, |
11091 | | simm4 = 67, |
11092 | | simm5 = 68, |
11093 | | simm6 = 69, |
11094 | | simm7_lsl2 = 70, |
11095 | | simm9 = 71, |
11096 | | simm9_addiusp = 72, |
11097 | | simm10 = 73, |
11098 | | simm10_64 = 74, |
11099 | | simm10_lsl1 = 75, |
11100 | | simm10_lsl2 = 76, |
11101 | | simm10_lsl3 = 77, |
11102 | | simm11 = 78, |
11103 | | simm12 = 79, |
11104 | | simm16 = 80, |
11105 | | simm16_64 = 81, |
11106 | | simm16_relaxed = 82, |
11107 | | simm18_lsl3 = 83, |
11108 | | simm19_lsl2 = 84, |
11109 | | simm23_lsl2 = 85, |
11110 | | simm32 = 86, |
11111 | | simm32_relaxed = 87, |
11112 | | size_ins = 88, |
11113 | | type0 = 89, |
11114 | | type1 = 90, |
11115 | | type2 = 91, |
11116 | | type3 = 92, |
11117 | | type4 = 93, |
11118 | | type5 = 94, |
11119 | | uimm1 = 95, |
11120 | | uimm1_ptr = 96, |
11121 | | uimm2 = 97, |
11122 | | uimm2_plus1 = 98, |
11123 | | uimm2_ptr = 99, |
11124 | | uimm3 = 100, |
11125 | | uimm3_ptr = 101, |
11126 | | uimm3_shift = 102, |
11127 | | uimm4 = 103, |
11128 | | uimm4_andi = 104, |
11129 | | uimm4_ptr = 105, |
11130 | | uimm5 = 106, |
11131 | | uimm5_64 = 107, |
11132 | | uimm5_64_report_uimm6 = 108, |
11133 | | uimm5_inssize_plus1 = 109, |
11134 | | uimm5_lsl2 = 110, |
11135 | | uimm5_plus1 = 111, |
11136 | | uimm5_plus1_report_uimm6 = 112, |
11137 | | uimm5_plus32 = 113, |
11138 | | uimm5_plus32_normalize = 114, |
11139 | | uimm5_plus32_normalize_64 = 115, |
11140 | | uimm5_plus33 = 116, |
11141 | | uimm5_report_uimm6 = 117, |
11142 | | uimm6 = 118, |
11143 | | uimm6_lsl2 = 119, |
11144 | | uimm7 = 120, |
11145 | | uimm8 = 121, |
11146 | | uimm10 = 122, |
11147 | | uimm16 = 123, |
11148 | | uimm16_64 = 124, |
11149 | | uimm16_64_relaxed = 125, |
11150 | | uimm16_altrelaxed = 126, |
11151 | | uimm16_relaxed = 127, |
11152 | | uimm20 = 128, |
11153 | | uimm26 = 129, |
11154 | | uimm32_coerced = 130, |
11155 | | uimm_range_2_64 = 131, |
11156 | | uimmz = 132, |
11157 | | untyped_imm_0 = 133, |
11158 | | vsplat_simm5 = 134, |
11159 | | vsplat_simm10 = 135, |
11160 | | vsplat_uimm1 = 136, |
11161 | | vsplat_uimm2 = 137, |
11162 | | vsplat_uimm3 = 138, |
11163 | | vsplat_uimm4 = 139, |
11164 | | vsplat_uimm5 = 140, |
11165 | | vsplat_uimm6 = 141, |
11166 | | vsplat_uimm8 = 142, |
11167 | | ACC64DSPOpnd = 143, |
11168 | | AFGR64Opnd = 144, |
11169 | | CCROpnd = 145, |
11170 | | COP0Opnd = 146, |
11171 | | COP2Opnd = 147, |
11172 | | COP3Opnd = 148, |
11173 | | DSPROpnd = 149, |
11174 | | FCCRegsOpnd = 150, |
11175 | | FGR32Opnd = 151, |
11176 | | FGR64Opnd = 152, |
11177 | | FGRCCOpnd = 153, |
11178 | | GPR32NonZeroOpnd = 154, |
11179 | | GPR32Opnd = 155, |
11180 | | GPR32ZeroOpnd = 156, |
11181 | | GPR64Opnd = 157, |
11182 | | GPRMM16Opnd = 158, |
11183 | | GPRMM16OpndMoveP = 159, |
11184 | | GPRMM16OpndMovePPairFirst = 160, |
11185 | | GPRMM16OpndMovePPairSecond = 161, |
11186 | | GPRMM16OpndZero = 162, |
11187 | | HI32DSPOpnd = 163, |
11188 | | HWRegsOpnd = 164, |
11189 | | LO32DSPOpnd = 165, |
11190 | | MSA128BOpnd = 166, |
11191 | | MSA128CROpnd = 167, |
11192 | | MSA128DOpnd = 168, |
11193 | | MSA128F16Opnd = 169, |
11194 | | MSA128HOpnd = 170, |
11195 | | MSA128WOpnd = 171, |
11196 | | StrictlyAFGR64Opnd = 172, |
11197 | | StrictlyFGR32Opnd = 173, |
11198 | | StrictlyFGR64Opnd = 174, |
11199 | | ACC64 = 175, |
11200 | | ACC64DSP = 176, |
11201 | | ACC128 = 177, |
11202 | | AFGR64 = 178, |
11203 | | CCR = 179, |
11204 | | COP0 = 180, |
11205 | | COP2 = 181, |
11206 | | COP3 = 182, |
11207 | | CPU16Regs = 183, |
11208 | | CPU16RegsPlusSP = 184, |
11209 | | CPURAReg = 185, |
11210 | | CPUSPReg = 186, |
11211 | | DSPCC = 187, |
11212 | | DSPR = 188, |
11213 | | FCC = 189, |
11214 | | FGR32 = 190, |
11215 | | FGR64 = 191, |
11216 | | FGRCC = 192, |
11217 | | GP32 = 193, |
11218 | | GP64 = 194, |
11219 | | GPR32 = 195, |
11220 | | GPR32NONZERO = 196, |
11221 | | GPR32ZERO = 197, |
11222 | | GPR64 = 198, |
11223 | | GPRMM16 = 199, |
11224 | | GPRMM16MoveP = 200, |
11225 | | GPRMM16MovePPairFirst = 201, |
11226 | | GPRMM16MovePPairSecond = 202, |
11227 | | GPRMM16Zero = 203, |
11228 | | HI32 = 204, |
11229 | | HI32DSP = 205, |
11230 | | HI64 = 206, |
11231 | | HWRegs = 207, |
11232 | | LO32 = 208, |
11233 | | LO32DSP = 209, |
11234 | | LO64 = 210, |
11235 | | MSA128B = 211, |
11236 | | MSA128D = 212, |
11237 | | MSA128F16 = 213, |
11238 | | MSA128H = 214, |
11239 | | MSA128W = 215, |
11240 | | MSA128WEvens = 216, |
11241 | | MSACtrl = 217, |
11242 | | OCTEON_MPL = 218, |
11243 | | OCTEON_P = 219, |
11244 | | SP32 = 220, |
11245 | | SP64 = 221, |
11246 | | OPERAND_TYPE_LIST_END |
11247 | | }; |
11248 | | } // end namespace OpTypes |
11249 | | } // end namespace Mips |
11250 | | } // end namespace llvm |
11251 | | #endif // GET_INSTRINFO_OPERAND_TYPES_ENUM |
11252 | | |
11253 | | #ifdef GET_INSTRINFO_OPERAND_TYPE |
11254 | | #undef GET_INSTRINFO_OPERAND_TYPE |
11255 | | namespace llvm { |
11256 | | namespace Mips { |
11257 | | LLVM_READONLY |
11258 | | static int getOperandType(uint16_t Opcode, uint16_t OpIdx) { |
11259 | | static const uint16_t Offsets[] = { |
11260 | | /* PHI */ |
11261 | | 0, |
11262 | | /* INLINEASM */ |
11263 | | 1, |
11264 | | /* INLINEASM_BR */ |
11265 | | 1, |
11266 | | /* CFI_INSTRUCTION */ |
11267 | | 1, |
11268 | | /* EH_LABEL */ |
11269 | | 2, |
11270 | | /* GC_LABEL */ |
11271 | | 3, |
11272 | | /* ANNOTATION_LABEL */ |
11273 | | 4, |
11274 | | /* KILL */ |
11275 | | 5, |
11276 | | /* EXTRACT_SUBREG */ |
11277 | | 5, |
11278 | | /* INSERT_SUBREG */ |
11279 | | 8, |
11280 | | /* IMPLICIT_DEF */ |
11281 | | 12, |
11282 | | /* SUBREG_TO_REG */ |
11283 | | 13, |
11284 | | /* COPY_TO_REGCLASS */ |
11285 | | 17, |
11286 | | /* DBG_VALUE */ |
11287 | | 20, |
11288 | | /* DBG_VALUE_LIST */ |
11289 | | 20, |
11290 | | /* DBG_INSTR_REF */ |
11291 | | 20, |
11292 | | /* DBG_PHI */ |
11293 | | 20, |
11294 | | /* DBG_LABEL */ |
11295 | | 20, |
11296 | | /* REG_SEQUENCE */ |
11297 | | 21, |
11298 | | /* COPY */ |
11299 | | 23, |
11300 | | /* BUNDLE */ |
11301 | | 25, |
11302 | | /* LIFETIME_START */ |
11303 | | 25, |
11304 | | /* LIFETIME_END */ |
11305 | | 26, |
11306 | | /* PSEUDO_PROBE */ |
11307 | | 27, |
11308 | | /* ARITH_FENCE */ |
11309 | | 31, |
11310 | | /* STACKMAP */ |
11311 | | 33, |
11312 | | /* FENTRY_CALL */ |
11313 | | 35, |
11314 | | /* PATCHPOINT */ |
11315 | | 35, |
11316 | | /* LOAD_STACK_GUARD */ |
11317 | | 41, |
11318 | | /* PREALLOCATED_SETUP */ |
11319 | | 42, |
11320 | | /* PREALLOCATED_ARG */ |
11321 | | 43, |
11322 | | /* STATEPOINT */ |
11323 | | 46, |
11324 | | /* LOCAL_ESCAPE */ |
11325 | | 46, |
11326 | | /* FAULTING_OP */ |
11327 | | 48, |
11328 | | /* PATCHABLE_OP */ |
11329 | | 49, |
11330 | | /* PATCHABLE_FUNCTION_ENTER */ |
11331 | | 49, |
11332 | | /* PATCHABLE_RET */ |
11333 | | 49, |
11334 | | /* PATCHABLE_FUNCTION_EXIT */ |
11335 | | 49, |
11336 | | /* PATCHABLE_TAIL_CALL */ |
11337 | | 49, |
11338 | | /* PATCHABLE_EVENT_CALL */ |
11339 | | 49, |
11340 | | /* PATCHABLE_TYPED_EVENT_CALL */ |
11341 | | 51, |
11342 | | /* ICALL_BRANCH_FUNNEL */ |
11343 | | 54, |
11344 | | /* MEMBARRIER */ |
11345 | | 54, |
11346 | | /* JUMP_TABLE_DEBUG_INFO */ |
11347 | | 54, |
11348 | | /* G_ASSERT_SEXT */ |
11349 | | 55, |
11350 | | /* G_ASSERT_ZEXT */ |
11351 | | 58, |
11352 | | /* G_ASSERT_ALIGN */ |
11353 | | 61, |
11354 | | /* G_ADD */ |
11355 | | 64, |
11356 | | /* G_SUB */ |
11357 | | 67, |
11358 | | /* G_MUL */ |
11359 | | 70, |
11360 | | /* G_SDIV */ |
11361 | | 73, |
11362 | | /* G_UDIV */ |
11363 | | 76, |
11364 | | /* G_SREM */ |
11365 | | 79, |
11366 | | /* G_UREM */ |
11367 | | 82, |
11368 | | /* G_SDIVREM */ |
11369 | | 85, |
11370 | | /* G_UDIVREM */ |
11371 | | 89, |
11372 | | /* G_AND */ |
11373 | | 93, |
11374 | | /* G_OR */ |
11375 | | 96, |
11376 | | /* G_XOR */ |
11377 | | 99, |
11378 | | /* G_IMPLICIT_DEF */ |
11379 | | 102, |
11380 | | /* G_PHI */ |
11381 | | 103, |
11382 | | /* G_FRAME_INDEX */ |
11383 | | 104, |
11384 | | /* G_GLOBAL_VALUE */ |
11385 | | 106, |
11386 | | /* G_CONSTANT_POOL */ |
11387 | | 108, |
11388 | | /* G_EXTRACT */ |
11389 | | 110, |
11390 | | /* G_UNMERGE_VALUES */ |
11391 | | 113, |
11392 | | /* G_INSERT */ |
11393 | | 115, |
11394 | | /* G_MERGE_VALUES */ |
11395 | | 119, |
11396 | | /* G_BUILD_VECTOR */ |
11397 | | 121, |
11398 | | /* G_BUILD_VECTOR_TRUNC */ |
11399 | | 123, |
11400 | | /* G_CONCAT_VECTORS */ |
11401 | | 125, |
11402 | | /* G_PTRTOINT */ |
11403 | | 127, |
11404 | | /* G_INTTOPTR */ |
11405 | | 129, |
11406 | | /* G_BITCAST */ |
11407 | | 131, |
11408 | | /* G_FREEZE */ |
11409 | | 133, |
11410 | | /* G_CONSTANT_FOLD_BARRIER */ |
11411 | | 135, |
11412 | | /* G_INTRINSIC_FPTRUNC_ROUND */ |
11413 | | 137, |
11414 | | /* G_INTRINSIC_TRUNC */ |
11415 | | 140, |
11416 | | /* G_INTRINSIC_ROUND */ |
11417 | | 142, |
11418 | | /* G_INTRINSIC_LRINT */ |
11419 | | 144, |
11420 | | /* G_INTRINSIC_ROUNDEVEN */ |
11421 | | 146, |
11422 | | /* G_READCYCLECOUNTER */ |
11423 | | 148, |
11424 | | /* G_LOAD */ |
11425 | | 149, |
11426 | | /* G_SEXTLOAD */ |
11427 | | 151, |
11428 | | /* G_ZEXTLOAD */ |
11429 | | 153, |
11430 | | /* G_INDEXED_LOAD */ |
11431 | | 155, |
11432 | | /* G_INDEXED_SEXTLOAD */ |
11433 | | 160, |
11434 | | /* G_INDEXED_ZEXTLOAD */ |
11435 | | 165, |
11436 | | /* G_STORE */ |
11437 | | 170, |
11438 | | /* G_INDEXED_STORE */ |
11439 | | 172, |
11440 | | /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
11441 | | 177, |
11442 | | /* G_ATOMIC_CMPXCHG */ |
11443 | | 182, |
11444 | | /* G_ATOMICRMW_XCHG */ |
11445 | | 186, |
11446 | | /* G_ATOMICRMW_ADD */ |
11447 | | 189, |
11448 | | /* G_ATOMICRMW_SUB */ |
11449 | | 192, |
11450 | | /* G_ATOMICRMW_AND */ |
11451 | | 195, |
11452 | | /* G_ATOMICRMW_NAND */ |
11453 | | 198, |
11454 | | /* G_ATOMICRMW_OR */ |
11455 | | 201, |
11456 | | /* G_ATOMICRMW_XOR */ |
11457 | | 204, |
11458 | | /* G_ATOMICRMW_MAX */ |
11459 | | 207, |
11460 | | /* G_ATOMICRMW_MIN */ |
11461 | | 210, |
11462 | | /* G_ATOMICRMW_UMAX */ |
11463 | | 213, |
11464 | | /* G_ATOMICRMW_UMIN */ |
11465 | | 216, |
11466 | | /* G_ATOMICRMW_FADD */ |
11467 | | 219, |
11468 | | /* G_ATOMICRMW_FSUB */ |
11469 | | 222, |
11470 | | /* G_ATOMICRMW_FMAX */ |
11471 | | 225, |
11472 | | /* G_ATOMICRMW_FMIN */ |
11473 | | 228, |
11474 | | /* G_ATOMICRMW_UINC_WRAP */ |
11475 | | 231, |
11476 | | /* G_ATOMICRMW_UDEC_WRAP */ |
11477 | | 234, |
11478 | | /* G_FENCE */ |
11479 | | 237, |
11480 | | /* G_PREFETCH */ |
11481 | | 239, |
11482 | | /* G_BRCOND */ |
11483 | | 243, |
11484 | | /* G_BRINDIRECT */ |
11485 | | 245, |
11486 | | /* G_INVOKE_REGION_START */ |
11487 | | 246, |
11488 | | /* G_INTRINSIC */ |
11489 | | 246, |
11490 | | /* G_INTRINSIC_W_SIDE_EFFECTS */ |
11491 | | 247, |
11492 | | /* G_INTRINSIC_CONVERGENT */ |
11493 | | 248, |
11494 | | /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ |
11495 | | 249, |
11496 | | /* G_ANYEXT */ |
11497 | | 250, |
11498 | | /* G_TRUNC */ |
11499 | | 252, |
11500 | | /* G_CONSTANT */ |
11501 | | 254, |
11502 | | /* G_FCONSTANT */ |
11503 | | 256, |
11504 | | /* G_VASTART */ |
11505 | | 258, |
11506 | | /* G_VAARG */ |
11507 | | 259, |
11508 | | /* G_SEXT */ |
11509 | | 262, |
11510 | | /* G_SEXT_INREG */ |
11511 | | 264, |
11512 | | /* G_ZEXT */ |
11513 | | 267, |
11514 | | /* G_SHL */ |
11515 | | 269, |
11516 | | /* G_LSHR */ |
11517 | | 272, |
11518 | | /* G_ASHR */ |
11519 | | 275, |
11520 | | /* G_FSHL */ |
11521 | | 278, |
11522 | | /* G_FSHR */ |
11523 | | 282, |
11524 | | /* G_ROTR */ |
11525 | | 286, |
11526 | | /* G_ROTL */ |
11527 | | 289, |
11528 | | /* G_ICMP */ |
11529 | | 292, |
11530 | | /* G_FCMP */ |
11531 | | 296, |
11532 | | /* G_SELECT */ |
11533 | | 300, |
11534 | | /* G_UADDO */ |
11535 | | 304, |
11536 | | /* G_UADDE */ |
11537 | | 308, |
11538 | | /* G_USUBO */ |
11539 | | 313, |
11540 | | /* G_USUBE */ |
11541 | | 317, |
11542 | | /* G_SADDO */ |
11543 | | 322, |
11544 | | /* G_SADDE */ |
11545 | | 326, |
11546 | | /* G_SSUBO */ |
11547 | | 331, |
11548 | | /* G_SSUBE */ |
11549 | | 335, |
11550 | | /* G_UMULO */ |
11551 | | 340, |
11552 | | /* G_SMULO */ |
11553 | | 344, |
11554 | | /* G_UMULH */ |
11555 | | 348, |
11556 | | /* G_SMULH */ |
11557 | | 351, |
11558 | | /* G_UADDSAT */ |
11559 | | 354, |
11560 | | /* G_SADDSAT */ |
11561 | | 357, |
11562 | | /* G_USUBSAT */ |
11563 | | 360, |
11564 | | /* G_SSUBSAT */ |
11565 | | 363, |
11566 | | /* G_USHLSAT */ |
11567 | | 366, |
11568 | | /* G_SSHLSAT */ |
11569 | | 369, |
11570 | | /* G_SMULFIX */ |
11571 | | 372, |
11572 | | /* G_UMULFIX */ |
11573 | | 376, |
11574 | | /* G_SMULFIXSAT */ |
11575 | | 380, |
11576 | | /* G_UMULFIXSAT */ |
11577 | | 384, |
11578 | | /* G_SDIVFIX */ |
11579 | | 388, |
11580 | | /* G_UDIVFIX */ |
11581 | | 392, |
11582 | | /* G_SDIVFIXSAT */ |
11583 | | 396, |
11584 | | /* G_UDIVFIXSAT */ |
11585 | | 400, |
11586 | | /* G_FADD */ |
11587 | | 404, |
11588 | | /* G_FSUB */ |
11589 | | 407, |
11590 | | /* G_FMUL */ |
11591 | | 410, |
11592 | | /* G_FMA */ |
11593 | | 413, |
11594 | | /* G_FMAD */ |
11595 | | 417, |
11596 | | /* G_FDIV */ |
11597 | | 421, |
11598 | | /* G_FREM */ |
11599 | | 424, |
11600 | | /* G_FPOW */ |
11601 | | 427, |
11602 | | /* G_FPOWI */ |
11603 | | 430, |
11604 | | /* G_FEXP */ |
11605 | | 433, |
11606 | | /* G_FEXP2 */ |
11607 | | 435, |
11608 | | /* G_FEXP10 */ |
11609 | | 437, |
11610 | | /* G_FLOG */ |
11611 | | 439, |
11612 | | /* G_FLOG2 */ |
11613 | | 441, |
11614 | | /* G_FLOG10 */ |
11615 | | 443, |
11616 | | /* G_FLDEXP */ |
11617 | | 445, |
11618 | | /* G_FFREXP */ |
11619 | | 448, |
11620 | | /* G_FNEG */ |
11621 | | 451, |
11622 | | /* G_FPEXT */ |
11623 | | 453, |
11624 | | /* G_FPTRUNC */ |
11625 | | 455, |
11626 | | /* G_FPTOSI */ |
11627 | | 457, |
11628 | | /* G_FPTOUI */ |
11629 | | 459, |
11630 | | /* G_SITOFP */ |
11631 | | 461, |
11632 | | /* G_UITOFP */ |
11633 | | 463, |
11634 | | /* G_FABS */ |
11635 | | 465, |
11636 | | /* G_FCOPYSIGN */ |
11637 | | 467, |
11638 | | /* G_IS_FPCLASS */ |
11639 | | 470, |
11640 | | /* G_FCANONICALIZE */ |
11641 | | 473, |
11642 | | /* G_FMINNUM */ |
11643 | | 475, |
11644 | | /* G_FMAXNUM */ |
11645 | | 478, |
11646 | | /* G_FMINNUM_IEEE */ |
11647 | | 481, |
11648 | | /* G_FMAXNUM_IEEE */ |
11649 | | 484, |
11650 | | /* G_FMINIMUM */ |
11651 | | 487, |
11652 | | /* G_FMAXIMUM */ |
11653 | | 490, |
11654 | | /* G_GET_FPENV */ |
11655 | | 493, |
11656 | | /* G_SET_FPENV */ |
11657 | | 494, |
11658 | | /* G_RESET_FPENV */ |
11659 | | 495, |
11660 | | /* G_GET_FPMODE */ |
11661 | | 495, |
11662 | | /* G_SET_FPMODE */ |
11663 | | 496, |
11664 | | /* G_RESET_FPMODE */ |
11665 | | 497, |
11666 | | /* G_PTR_ADD */ |
11667 | | 497, |
11668 | | /* G_PTRMASK */ |
11669 | | 500, |
11670 | | /* G_SMIN */ |
11671 | | 503, |
11672 | | /* G_SMAX */ |
11673 | | 506, |
11674 | | /* G_UMIN */ |
11675 | | 509, |
11676 | | /* G_UMAX */ |
11677 | | 512, |
11678 | | /* G_ABS */ |
11679 | | 515, |
11680 | | /* G_LROUND */ |
11681 | | 517, |
11682 | | /* G_LLROUND */ |
11683 | | 519, |
11684 | | /* G_BR */ |
11685 | | 521, |
11686 | | /* G_BRJT */ |
11687 | | 522, |
11688 | | /* G_INSERT_VECTOR_ELT */ |
11689 | | 525, |
11690 | | /* G_EXTRACT_VECTOR_ELT */ |
11691 | | 529, |
11692 | | /* G_SHUFFLE_VECTOR */ |
11693 | | 532, |
11694 | | /* G_CTTZ */ |
11695 | | 536, |
11696 | | /* G_CTTZ_ZERO_UNDEF */ |
11697 | | 538, |
11698 | | /* G_CTLZ */ |
11699 | | 540, |
11700 | | /* G_CTLZ_ZERO_UNDEF */ |
11701 | | 542, |
11702 | | /* G_CTPOP */ |
11703 | | 544, |
11704 | | /* G_BSWAP */ |
11705 | | 546, |
11706 | | /* G_BITREVERSE */ |
11707 | | 548, |
11708 | | /* G_FCEIL */ |
11709 | | 550, |
11710 | | /* G_FCOS */ |
11711 | | 552, |
11712 | | /* G_FSIN */ |
11713 | | 554, |
11714 | | /* G_FSQRT */ |
11715 | | 556, |
11716 | | /* G_FFLOOR */ |
11717 | | 558, |
11718 | | /* G_FRINT */ |
11719 | | 560, |
11720 | | /* G_FNEARBYINT */ |
11721 | | 562, |
11722 | | /* G_ADDRSPACE_CAST */ |
11723 | | 564, |
11724 | | /* G_BLOCK_ADDR */ |
11725 | | 566, |
11726 | | /* G_JUMP_TABLE */ |
11727 | | 568, |
11728 | | /* G_DYN_STACKALLOC */ |
11729 | | 570, |
11730 | | /* G_STACKSAVE */ |
11731 | | 573, |
11732 | | /* G_STACKRESTORE */ |
11733 | | 574, |
11734 | | /* G_STRICT_FADD */ |
11735 | | 575, |
11736 | | /* G_STRICT_FSUB */ |
11737 | | 578, |
11738 | | /* G_STRICT_FMUL */ |
11739 | | 581, |
11740 | | /* G_STRICT_FDIV */ |
11741 | | 584, |
11742 | | /* G_STRICT_FREM */ |
11743 | | 587, |
11744 | | /* G_STRICT_FMA */ |
11745 | | 590, |
11746 | | /* G_STRICT_FSQRT */ |
11747 | | 594, |
11748 | | /* G_STRICT_FLDEXP */ |
11749 | | 596, |
11750 | | /* G_READ_REGISTER */ |
11751 | | 599, |
11752 | | /* G_WRITE_REGISTER */ |
11753 | | 601, |
11754 | | /* G_MEMCPY */ |
11755 | | 603, |
11756 | | /* G_MEMCPY_INLINE */ |
11757 | | 607, |
11758 | | /* G_MEMMOVE */ |
11759 | | 610, |
11760 | | /* G_MEMSET */ |
11761 | | 614, |
11762 | | /* G_BZERO */ |
11763 | | 618, |
11764 | | /* G_VECREDUCE_SEQ_FADD */ |
11765 | | 621, |
11766 | | /* G_VECREDUCE_SEQ_FMUL */ |
11767 | | 624, |
11768 | | /* G_VECREDUCE_FADD */ |
11769 | | 627, |
11770 | | /* G_VECREDUCE_FMUL */ |
11771 | | 629, |
11772 | | /* G_VECREDUCE_FMAX */ |
11773 | | 631, |
11774 | | /* G_VECREDUCE_FMIN */ |
11775 | | 633, |
11776 | | /* G_VECREDUCE_FMAXIMUM */ |
11777 | | 635, |
11778 | | /* G_VECREDUCE_FMINIMUM */ |
11779 | | 637, |
11780 | | /* G_VECREDUCE_ADD */ |
11781 | | 639, |
11782 | | /* G_VECREDUCE_MUL */ |
11783 | | 641, |
11784 | | /* G_VECREDUCE_AND */ |
11785 | | 643, |
11786 | | /* G_VECREDUCE_OR */ |
11787 | | 645, |
11788 | | /* G_VECREDUCE_XOR */ |
11789 | | 647, |
11790 | | /* G_VECREDUCE_SMAX */ |
11791 | | 649, |
11792 | | /* G_VECREDUCE_SMIN */ |
11793 | | 651, |
11794 | | /* G_VECREDUCE_UMAX */ |
11795 | | 653, |
11796 | | /* G_VECREDUCE_UMIN */ |
11797 | | 655, |
11798 | | /* G_SBFX */ |
11799 | | 657, |
11800 | | /* G_UBFX */ |
11801 | | 661, |
11802 | | /* ABSMacro */ |
11803 | | 665, |
11804 | | /* ADJCALLSTACKDOWN */ |
11805 | | 667, |
11806 | | /* ADJCALLSTACKUP */ |
11807 | | 669, |
11808 | | /* AND_V_D_PSEUDO */ |
11809 | | 671, |
11810 | | /* AND_V_H_PSEUDO */ |
11811 | | 674, |
11812 | | /* AND_V_W_PSEUDO */ |
11813 | | 677, |
11814 | | /* ATOMIC_CMP_SWAP_I16 */ |
11815 | | 680, |
11816 | | /* ATOMIC_CMP_SWAP_I16_POSTRA */ |
11817 | | 684, |
11818 | | /* ATOMIC_CMP_SWAP_I32 */ |
11819 | | 691, |
11820 | | /* ATOMIC_CMP_SWAP_I32_POSTRA */ |
11821 | | 695, |
11822 | | /* ATOMIC_CMP_SWAP_I64 */ |
11823 | | 699, |
11824 | | /* ATOMIC_CMP_SWAP_I64_POSTRA */ |
11825 | | 703, |
11826 | | /* ATOMIC_CMP_SWAP_I8 */ |
11827 | | 707, |
11828 | | /* ATOMIC_CMP_SWAP_I8_POSTRA */ |
11829 | | 711, |
11830 | | /* ATOMIC_LOAD_ADD_I16 */ |
11831 | | 718, |
11832 | | /* ATOMIC_LOAD_ADD_I16_POSTRA */ |
11833 | | 721, |
11834 | | /* ATOMIC_LOAD_ADD_I32 */ |
11835 | | 727, |
11836 | | /* ATOMIC_LOAD_ADD_I32_POSTRA */ |
11837 | | 730, |
11838 | | /* ATOMIC_LOAD_ADD_I64 */ |
11839 | | 733, |
11840 | | /* ATOMIC_LOAD_ADD_I64_POSTRA */ |
11841 | | 736, |
11842 | | /* ATOMIC_LOAD_ADD_I8 */ |
11843 | | 739, |
11844 | | /* ATOMIC_LOAD_ADD_I8_POSTRA */ |
11845 | | 742, |
11846 | | /* ATOMIC_LOAD_AND_I16 */ |
11847 | | 748, |
11848 | | /* ATOMIC_LOAD_AND_I16_POSTRA */ |
11849 | | 751, |
11850 | | /* ATOMIC_LOAD_AND_I32 */ |
11851 | | 757, |
11852 | | /* ATOMIC_LOAD_AND_I32_POSTRA */ |
11853 | | 760, |
11854 | | /* ATOMIC_LOAD_AND_I64 */ |
11855 | | 763, |
11856 | | /* ATOMIC_LOAD_AND_I64_POSTRA */ |
11857 | | 766, |
11858 | | /* ATOMIC_LOAD_AND_I8 */ |
11859 | | 769, |
11860 | | /* ATOMIC_LOAD_AND_I8_POSTRA */ |
11861 | | 772, |
11862 | | /* ATOMIC_LOAD_MAX_I16 */ |
11863 | | 778, |
11864 | | /* ATOMIC_LOAD_MAX_I16_POSTRA */ |
11865 | | 781, |
11866 | | /* ATOMIC_LOAD_MAX_I32 */ |
11867 | | 787, |
11868 | | /* ATOMIC_LOAD_MAX_I32_POSTRA */ |
11869 | | 790, |
11870 | | /* ATOMIC_LOAD_MAX_I64 */ |
11871 | | 793, |
11872 | | /* ATOMIC_LOAD_MAX_I64_POSTRA */ |
11873 | | 796, |
11874 | | /* ATOMIC_LOAD_MAX_I8 */ |
11875 | | 799, |
11876 | | /* ATOMIC_LOAD_MAX_I8_POSTRA */ |
11877 | | 802, |
11878 | | /* ATOMIC_LOAD_MIN_I16 */ |
11879 | | 808, |
11880 | | /* ATOMIC_LOAD_MIN_I16_POSTRA */ |
11881 | | 811, |
11882 | | /* ATOMIC_LOAD_MIN_I32 */ |
11883 | | 817, |
11884 | | /* ATOMIC_LOAD_MIN_I32_POSTRA */ |
11885 | | 820, |
11886 | | /* ATOMIC_LOAD_MIN_I64 */ |
11887 | | 823, |
11888 | | /* ATOMIC_LOAD_MIN_I64_POSTRA */ |
11889 | | 826, |
11890 | | /* ATOMIC_LOAD_MIN_I8 */ |
11891 | | 829, |
11892 | | /* ATOMIC_LOAD_MIN_I8_POSTRA */ |
11893 | | 832, |
11894 | | /* ATOMIC_LOAD_NAND_I16 */ |
11895 | | 838, |
11896 | | /* ATOMIC_LOAD_NAND_I16_POSTRA */ |
11897 | | 841, |
11898 | | /* ATOMIC_LOAD_NAND_I32 */ |
11899 | | 847, |
11900 | | /* ATOMIC_LOAD_NAND_I32_POSTRA */ |
11901 | | 850, |
11902 | | /* ATOMIC_LOAD_NAND_I64 */ |
11903 | | 853, |
11904 | | /* ATOMIC_LOAD_NAND_I64_POSTRA */ |
11905 | | 856, |
11906 | | /* ATOMIC_LOAD_NAND_I8 */ |
11907 | | 859, |
11908 | | /* ATOMIC_LOAD_NAND_I8_POSTRA */ |
11909 | | 862, |
11910 | | /* ATOMIC_LOAD_OR_I16 */ |
11911 | | 868, |
11912 | | /* ATOMIC_LOAD_OR_I16_POSTRA */ |
11913 | | 871, |
11914 | | /* ATOMIC_LOAD_OR_I32 */ |
11915 | | 877, |
11916 | | /* ATOMIC_LOAD_OR_I32_POSTRA */ |
11917 | | 880, |
11918 | | /* ATOMIC_LOAD_OR_I64 */ |
11919 | | 883, |
11920 | | /* ATOMIC_LOAD_OR_I64_POSTRA */ |
11921 | | 886, |
11922 | | /* ATOMIC_LOAD_OR_I8 */ |
11923 | | 889, |
11924 | | /* ATOMIC_LOAD_OR_I8_POSTRA */ |
11925 | | 892, |
11926 | | /* ATOMIC_LOAD_SUB_I16 */ |
11927 | | 898, |
11928 | | /* ATOMIC_LOAD_SUB_I16_POSTRA */ |
11929 | | 901, |
11930 | | /* ATOMIC_LOAD_SUB_I32 */ |
11931 | | 907, |
11932 | | /* ATOMIC_LOAD_SUB_I32_POSTRA */ |
11933 | | 910, |
11934 | | /* ATOMIC_LOAD_SUB_I64 */ |
11935 | | 913, |
11936 | | /* ATOMIC_LOAD_SUB_I64_POSTRA */ |
11937 | | 916, |
11938 | | /* ATOMIC_LOAD_SUB_I8 */ |
11939 | | 919, |
11940 | | /* ATOMIC_LOAD_SUB_I8_POSTRA */ |
11941 | | 922, |
11942 | | /* ATOMIC_LOAD_UMAX_I16 */ |
11943 | | 928, |
11944 | | /* ATOMIC_LOAD_UMAX_I16_POSTRA */ |
11945 | | 931, |
11946 | | /* ATOMIC_LOAD_UMAX_I32 */ |
11947 | | 937, |
11948 | | /* ATOMIC_LOAD_UMAX_I32_POSTRA */ |
11949 | | 940, |
11950 | | /* ATOMIC_LOAD_UMAX_I64 */ |
11951 | | 943, |
11952 | | /* ATOMIC_LOAD_UMAX_I64_POSTRA */ |
11953 | | 946, |
11954 | | /* ATOMIC_LOAD_UMAX_I8 */ |
11955 | | 949, |
11956 | | /* ATOMIC_LOAD_UMAX_I8_POSTRA */ |
11957 | | 952, |
11958 | | /* ATOMIC_LOAD_UMIN_I16 */ |
11959 | | 958, |
11960 | | /* ATOMIC_LOAD_UMIN_I16_POSTRA */ |
11961 | | 961, |
11962 | | /* ATOMIC_LOAD_UMIN_I32 */ |
11963 | | 967, |
11964 | | /* ATOMIC_LOAD_UMIN_I32_POSTRA */ |
11965 | | 970, |
11966 | | /* ATOMIC_LOAD_UMIN_I64 */ |
11967 | | 973, |
11968 | | /* ATOMIC_LOAD_UMIN_I64_POSTRA */ |
11969 | | 976, |
11970 | | /* ATOMIC_LOAD_UMIN_I8 */ |
11971 | | 979, |
11972 | | /* ATOMIC_LOAD_UMIN_I8_POSTRA */ |
11973 | | 982, |
11974 | | /* ATOMIC_LOAD_XOR_I16 */ |
11975 | | 988, |
11976 | | /* ATOMIC_LOAD_XOR_I16_POSTRA */ |
11977 | | 991, |
11978 | | /* ATOMIC_LOAD_XOR_I32 */ |
11979 | | 997, |
11980 | | /* ATOMIC_LOAD_XOR_I32_POSTRA */ |
11981 | | 1000, |
11982 | | /* ATOMIC_LOAD_XOR_I64 */ |
11983 | | 1003, |
11984 | | /* ATOMIC_LOAD_XOR_I64_POSTRA */ |
11985 | | 1006, |
11986 | | /* ATOMIC_LOAD_XOR_I8 */ |
11987 | | 1009, |
11988 | | /* ATOMIC_LOAD_XOR_I8_POSTRA */ |
11989 | | 1012, |
11990 | | /* ATOMIC_SWAP_I16 */ |
11991 | | 1018, |
11992 | | /* ATOMIC_SWAP_I16_POSTRA */ |
11993 | | 1021, |
11994 | | /* ATOMIC_SWAP_I32 */ |
11995 | | 1027, |
11996 | | /* ATOMIC_SWAP_I32_POSTRA */ |
11997 | | 1030, |
11998 | | /* ATOMIC_SWAP_I64 */ |
11999 | | 1033, |
12000 | | /* ATOMIC_SWAP_I64_POSTRA */ |
12001 | | 1036, |
12002 | | /* ATOMIC_SWAP_I8 */ |
12003 | | 1039, |
12004 | | /* ATOMIC_SWAP_I8_POSTRA */ |
12005 | | 1042, |
12006 | | /* B */ |
12007 | | 1048, |
12008 | | /* BAL_BR */ |
12009 | | 1049, |
12010 | | /* BAL_BR_MM */ |
12011 | | 1050, |
12012 | | /* BEQLImmMacro */ |
12013 | | 1051, |
12014 | | /* BGE */ |
12015 | | 1054, |
12016 | | /* BGEImmMacro */ |
12017 | | 1057, |
12018 | | /* BGEL */ |
12019 | | 1060, |
12020 | | /* BGELImmMacro */ |
12021 | | 1063, |
12022 | | /* BGEU */ |
12023 | | 1066, |
12024 | | /* BGEUImmMacro */ |
12025 | | 1069, |
12026 | | /* BGEUL */ |
12027 | | 1072, |
12028 | | /* BGEULImmMacro */ |
12029 | | 1075, |
12030 | | /* BGT */ |
12031 | | 1078, |
12032 | | /* BGTImmMacro */ |
12033 | | 1081, |
12034 | | /* BGTL */ |
12035 | | 1084, |
12036 | | /* BGTLImmMacro */ |
12037 | | 1087, |
12038 | | /* BGTU */ |
12039 | | 1090, |
12040 | | /* BGTUImmMacro */ |
12041 | | 1093, |
12042 | | /* BGTUL */ |
12043 | | 1096, |
12044 | | /* BGTULImmMacro */ |
12045 | | 1099, |
12046 | | /* BLE */ |
12047 | | 1102, |
12048 | | /* BLEImmMacro */ |
12049 | | 1105, |
12050 | | /* BLEL */ |
12051 | | 1108, |
12052 | | /* BLELImmMacro */ |
12053 | | 1111, |
12054 | | /* BLEU */ |
12055 | | 1114, |
12056 | | /* BLEUImmMacro */ |
12057 | | 1117, |
12058 | | /* BLEUL */ |
12059 | | 1120, |
12060 | | /* BLEULImmMacro */ |
12061 | | 1123, |
12062 | | /* BLT */ |
12063 | | 1126, |
12064 | | /* BLTImmMacro */ |
12065 | | 1129, |
12066 | | /* BLTL */ |
12067 | | 1132, |
12068 | | /* BLTLImmMacro */ |
12069 | | 1135, |
12070 | | /* BLTU */ |
12071 | | 1138, |
12072 | | /* BLTUImmMacro */ |
12073 | | 1141, |
12074 | | /* BLTUL */ |
12075 | | 1144, |
12076 | | /* BLTULImmMacro */ |
12077 | | 1147, |
12078 | | /* BNELImmMacro */ |
12079 | | 1150, |
12080 | | /* BPOSGE32_PSEUDO */ |
12081 | | 1153, |
12082 | | /* BSEL_D_PSEUDO */ |
12083 | | 1154, |
12084 | | /* BSEL_FD_PSEUDO */ |
12085 | | 1158, |
12086 | | /* BSEL_FW_PSEUDO */ |
12087 | | 1162, |
12088 | | /* BSEL_H_PSEUDO */ |
12089 | | 1166, |
12090 | | /* BSEL_W_PSEUDO */ |
12091 | | 1170, |
12092 | | /* B_MM */ |
12093 | | 1174, |
12094 | | /* B_MMR6_Pseudo */ |
12095 | | 1175, |
12096 | | /* B_MM_Pseudo */ |
12097 | | 1176, |
12098 | | /* BeqImm */ |
12099 | | 1177, |
12100 | | /* BneImm */ |
12101 | | 1180, |
12102 | | /* BteqzT8CmpX16 */ |
12103 | | 1183, |
12104 | | /* BteqzT8CmpiX16 */ |
12105 | | 1186, |
12106 | | /* BteqzT8SltX16 */ |
12107 | | 1189, |
12108 | | /* BteqzT8SltiX16 */ |
12109 | | 1192, |
12110 | | /* BteqzT8SltiuX16 */ |
12111 | | 1195, |
12112 | | /* BteqzT8SltuX16 */ |
12113 | | 1198, |
12114 | | /* BtnezT8CmpX16 */ |
12115 | | 1201, |
12116 | | /* BtnezT8CmpiX16 */ |
12117 | | 1204, |
12118 | | /* BtnezT8SltX16 */ |
12119 | | 1207, |
12120 | | /* BtnezT8SltiX16 */ |
12121 | | 1210, |
12122 | | /* BtnezT8SltiuX16 */ |
12123 | | 1213, |
12124 | | /* BtnezT8SltuX16 */ |
12125 | | 1216, |
12126 | | /* BuildPairF64 */ |
12127 | | 1219, |
12128 | | /* BuildPairF64_64 */ |
12129 | | 1222, |
12130 | | /* CFTC1 */ |
12131 | | 1225, |
12132 | | /* CONSTPOOL_ENTRY */ |
12133 | | 1227, |
12134 | | /* COPY_FD_PSEUDO */ |
12135 | | 1230, |
12136 | | /* COPY_FW_PSEUDO */ |
12137 | | 1233, |
12138 | | /* CTTC1 */ |
12139 | | 1236, |
12140 | | /* Constant32 */ |
12141 | | 1238, |
12142 | | /* DMULImmMacro */ |
12143 | | 1239, |
12144 | | /* DMULMacro */ |
12145 | | 1242, |
12146 | | /* DMULOMacro */ |
12147 | | 1245, |
12148 | | /* DMULOUMacro */ |
12149 | | 1248, |
12150 | | /* DROL */ |
12151 | | 1251, |
12152 | | /* DROLImm */ |
12153 | | 1254, |
12154 | | /* DROR */ |
12155 | | 1257, |
12156 | | /* DRORImm */ |
12157 | | 1260, |
12158 | | /* DSDivIMacro */ |
12159 | | 1263, |
12160 | | /* DSDivMacro */ |
12161 | | 1266, |
12162 | | /* DSRemIMacro */ |
12163 | | 1269, |
12164 | | /* DSRemMacro */ |
12165 | | 1272, |
12166 | | /* DUDivIMacro */ |
12167 | | 1275, |
12168 | | /* DUDivMacro */ |
12169 | | 1278, |
12170 | | /* DURemIMacro */ |
12171 | | 1281, |
12172 | | /* DURemMacro */ |
12173 | | 1284, |
12174 | | /* ERet */ |
12175 | | 1287, |
12176 | | /* ExtractElementF64 */ |
12177 | | 1287, |
12178 | | /* ExtractElementF64_64 */ |
12179 | | 1290, |
12180 | | /* FABS_D */ |
12181 | | 1293, |
12182 | | /* FABS_W */ |
12183 | | 1295, |
12184 | | /* FEXP2_D_1_PSEUDO */ |
12185 | | 1297, |
12186 | | /* FEXP2_W_1_PSEUDO */ |
12187 | | 1299, |
12188 | | /* FILL_FD_PSEUDO */ |
12189 | | 1301, |
12190 | | /* FILL_FW_PSEUDO */ |
12191 | | 1303, |
12192 | | /* GotPrologue16 */ |
12193 | | 1305, |
12194 | | /* INSERT_B_VIDX64_PSEUDO */ |
12195 | | 1309, |
12196 | | /* INSERT_B_VIDX_PSEUDO */ |
12197 | | 1313, |
12198 | | /* INSERT_D_VIDX64_PSEUDO */ |
12199 | | 1317, |
12200 | | /* INSERT_D_VIDX_PSEUDO */ |
12201 | | 1321, |
12202 | | /* INSERT_FD_PSEUDO */ |
12203 | | 1325, |
12204 | | /* INSERT_FD_VIDX64_PSEUDO */ |
12205 | | 1329, |
12206 | | /* INSERT_FD_VIDX_PSEUDO */ |
12207 | | 1333, |
12208 | | /* INSERT_FW_PSEUDO */ |
12209 | | 1337, |
12210 | | /* INSERT_FW_VIDX64_PSEUDO */ |
12211 | | 1341, |
12212 | | /* INSERT_FW_VIDX_PSEUDO */ |
12213 | | 1345, |
12214 | | /* INSERT_H_VIDX64_PSEUDO */ |
12215 | | 1349, |
12216 | | /* INSERT_H_VIDX_PSEUDO */ |
12217 | | 1353, |
12218 | | /* INSERT_W_VIDX64_PSEUDO */ |
12219 | | 1357, |
12220 | | /* INSERT_W_VIDX_PSEUDO */ |
12221 | | 1361, |
12222 | | /* JALR64Pseudo */ |
12223 | | 1365, |
12224 | | /* JALRHB64Pseudo */ |
12225 | | 1366, |
12226 | | /* JALRHBPseudo */ |
12227 | | 1367, |
12228 | | /* JALRPseudo */ |
12229 | | 1368, |
12230 | | /* JAL_MMR6 */ |
12231 | | 1369, |
12232 | | /* JalOneReg */ |
12233 | | 1370, |
12234 | | /* JalTwoReg */ |
12235 | | 1371, |
12236 | | /* LDMacro */ |
12237 | | 1373, |
12238 | | /* LDR_D */ |
12239 | | 1376, |
12240 | | /* LDR_W */ |
12241 | | 1379, |
12242 | | /* LD_F16 */ |
12243 | | 1382, |
12244 | | /* LOAD_ACC128 */ |
12245 | | 1385, |
12246 | | /* LOAD_ACC64 */ |
12247 | | 1388, |
12248 | | /* LOAD_ACC64DSP */ |
12249 | | 1391, |
12250 | | /* LOAD_CCOND_DSP */ |
12251 | | 1394, |
12252 | | /* LONG_BRANCH_ADDiu */ |
12253 | | 1397, |
12254 | | /* LONG_BRANCH_ADDiu2Op */ |
12255 | | 1401, |
12256 | | /* LONG_BRANCH_DADDiu */ |
12257 | | 1404, |
12258 | | /* LONG_BRANCH_DADDiu2Op */ |
12259 | | 1408, |
12260 | | /* LONG_BRANCH_LUi */ |
12261 | | 1411, |
12262 | | /* LONG_BRANCH_LUi2Op */ |
12263 | | 1414, |
12264 | | /* LONG_BRANCH_LUi2Op_64 */ |
12265 | | 1416, |
12266 | | /* LWM_MM */ |
12267 | | 1418, |
12268 | | /* LoadAddrImm32 */ |
12269 | | 1421, |
12270 | | /* LoadAddrImm64 */ |
12271 | | 1423, |
12272 | | /* LoadAddrReg32 */ |
12273 | | 1425, |
12274 | | /* LoadAddrReg64 */ |
12275 | | 1428, |
12276 | | /* LoadImm32 */ |
12277 | | 1431, |
12278 | | /* LoadImm64 */ |
12279 | | 1433, |
12280 | | /* LoadImmDoubleFGR */ |
12281 | | 1435, |
12282 | | /* LoadImmDoubleFGR_32 */ |
12283 | | 1437, |
12284 | | /* LoadImmDoubleGPR */ |
12285 | | 1439, |
12286 | | /* LoadImmSingleFGR */ |
12287 | | 1441, |
12288 | | /* LoadImmSingleGPR */ |
12289 | | 1443, |
12290 | | /* LwConstant32 */ |
12291 | | 1445, |
12292 | | /* MFTACX */ |
12293 | | 1448, |
12294 | | /* MFTC0 */ |
12295 | | 1450, |
12296 | | /* MFTC1 */ |
12297 | | 1453, |
12298 | | /* MFTDSP */ |
12299 | | 1455, |
12300 | | /* MFTGPR */ |
12301 | | 1456, |
12302 | | /* MFTHC1 */ |
12303 | | 1459, |
12304 | | /* MFTHI */ |
12305 | | 1461, |
12306 | | /* MFTLO */ |
12307 | | 1463, |
12308 | | /* MIPSeh_return32 */ |
12309 | | 1465, |
12310 | | /* MIPSeh_return64 */ |
12311 | | 1467, |
12312 | | /* MSA_FP_EXTEND_D_PSEUDO */ |
12313 | | 1469, |
12314 | | /* MSA_FP_EXTEND_W_PSEUDO */ |
12315 | | 1471, |
12316 | | /* MSA_FP_ROUND_D_PSEUDO */ |
12317 | | 1473, |
12318 | | /* MSA_FP_ROUND_W_PSEUDO */ |
12319 | | 1475, |
12320 | | /* MTTACX */ |
12321 | | 1477, |
12322 | | /* MTTC0 */ |
12323 | | 1479, |
12324 | | /* MTTC1 */ |
12325 | | 1482, |
12326 | | /* MTTDSP */ |
12327 | | 1484, |
12328 | | /* MTTGPR */ |
12329 | | 1485, |
12330 | | /* MTTHC1 */ |
12331 | | 1487, |
12332 | | /* MTTHI */ |
12333 | | 1489, |
12334 | | /* MTTLO */ |
12335 | | 1491, |
12336 | | /* MULImmMacro */ |
12337 | | 1493, |
12338 | | /* MULOMacro */ |
12339 | | 1496, |
12340 | | /* MULOUMacro */ |
12341 | | 1499, |
12342 | | /* MultRxRy16 */ |
12343 | | 1502, |
12344 | | /* MultRxRyRz16 */ |
12345 | | 1504, |
12346 | | /* MultuRxRy16 */ |
12347 | | 1507, |
12348 | | /* MultuRxRyRz16 */ |
12349 | | 1509, |
12350 | | /* NOP */ |
12351 | | 1512, |
12352 | | /* NORImm */ |
12353 | | 1512, |
12354 | | /* NORImm64 */ |
12355 | | 1515, |
12356 | | /* NOR_V_D_PSEUDO */ |
12357 | | 1518, |
12358 | | /* NOR_V_H_PSEUDO */ |
12359 | | 1521, |
12360 | | /* NOR_V_W_PSEUDO */ |
12361 | | 1524, |
12362 | | /* OR_V_D_PSEUDO */ |
12363 | | 1527, |
12364 | | /* OR_V_H_PSEUDO */ |
12365 | | 1530, |
12366 | | /* OR_V_W_PSEUDO */ |
12367 | | 1533, |
12368 | | /* PseudoCMPU_EQ_QB */ |
12369 | | 1536, |
12370 | | /* PseudoCMPU_LE_QB */ |
12371 | | 1539, |
12372 | | /* PseudoCMPU_LT_QB */ |
12373 | | 1542, |
12374 | | /* PseudoCMP_EQ_PH */ |
12375 | | 1545, |
12376 | | /* PseudoCMP_LE_PH */ |
12377 | | 1548, |
12378 | | /* PseudoCMP_LT_PH */ |
12379 | | 1551, |
12380 | | /* PseudoCVT_D32_W */ |
12381 | | 1554, |
12382 | | /* PseudoCVT_D64_L */ |
12383 | | 1556, |
12384 | | /* PseudoCVT_D64_W */ |
12385 | | 1558, |
12386 | | /* PseudoCVT_S_L */ |
12387 | | 1560, |
12388 | | /* PseudoCVT_S_W */ |
12389 | | 1562, |
12390 | | /* PseudoDMULT */ |
12391 | | 1564, |
12392 | | /* PseudoDMULTu */ |
12393 | | 1567, |
12394 | | /* PseudoDSDIV */ |
12395 | | 1570, |
12396 | | /* PseudoDUDIV */ |
12397 | | 1573, |
12398 | | /* PseudoD_SELECT_I */ |
12399 | | 1576, |
12400 | | /* PseudoD_SELECT_I64 */ |
12401 | | 1583, |
12402 | | /* PseudoIndirectBranch */ |
12403 | | 1590, |
12404 | | /* PseudoIndirectBranch64 */ |
12405 | | 1591, |
12406 | | /* PseudoIndirectBranch64R6 */ |
12407 | | 1592, |
12408 | | /* PseudoIndirectBranchR6 */ |
12409 | | 1593, |
12410 | | /* PseudoIndirectBranch_MM */ |
12411 | | 1594, |
12412 | | /* PseudoIndirectBranch_MMR6 */ |
12413 | | 1595, |
12414 | | /* PseudoIndirectHazardBranch */ |
12415 | | 1596, |
12416 | | /* PseudoIndirectHazardBranch64 */ |
12417 | | 1597, |
12418 | | /* PseudoIndrectHazardBranch64R6 */ |
12419 | | 1598, |
12420 | | /* PseudoIndrectHazardBranchR6 */ |
12421 | | 1599, |
12422 | | /* PseudoMADD */ |
12423 | | 1600, |
12424 | | /* PseudoMADDU */ |
12425 | | 1604, |
12426 | | /* PseudoMADDU_MM */ |
12427 | | 1608, |
12428 | | /* PseudoMADD_MM */ |
12429 | | 1612, |
12430 | | /* PseudoMFHI */ |
12431 | | 1616, |
12432 | | /* PseudoMFHI64 */ |
12433 | | 1618, |
12434 | | /* PseudoMFHI_MM */ |
12435 | | 1620, |
12436 | | /* PseudoMFLO */ |
12437 | | 1622, |
12438 | | /* PseudoMFLO64 */ |
12439 | | 1624, |
12440 | | /* PseudoMFLO_MM */ |
12441 | | 1626, |
12442 | | /* PseudoMSUB */ |
12443 | | 1628, |
12444 | | /* PseudoMSUBU */ |
12445 | | 1632, |
12446 | | /* PseudoMSUBU_MM */ |
12447 | | 1636, |
12448 | | /* PseudoMSUB_MM */ |
12449 | | 1640, |
12450 | | /* PseudoMTLOHI */ |
12451 | | 1644, |
12452 | | /* PseudoMTLOHI64 */ |
12453 | | 1647, |
12454 | | /* PseudoMTLOHI_DSP */ |
12455 | | 1650, |
12456 | | /* PseudoMTLOHI_MM */ |
12457 | | 1653, |
12458 | | /* PseudoMULT */ |
12459 | | 1656, |
12460 | | /* PseudoMULT_MM */ |
12461 | | 1659, |
12462 | | /* PseudoMULTu */ |
12463 | | 1662, |
12464 | | /* PseudoMULTu_MM */ |
12465 | | 1665, |
12466 | | /* PseudoPICK_PH */ |
12467 | | 1668, |
12468 | | /* PseudoPICK_QB */ |
12469 | | 1672, |
12470 | | /* PseudoReturn */ |
12471 | | 1676, |
12472 | | /* PseudoReturn64 */ |
12473 | | 1677, |
12474 | | /* PseudoSDIV */ |
12475 | | 1678, |
12476 | | /* PseudoSELECTFP_F_D32 */ |
12477 | | 1681, |
12478 | | /* PseudoSELECTFP_F_D64 */ |
12479 | | 1685, |
12480 | | /* PseudoSELECTFP_F_I */ |
12481 | | 1689, |
12482 | | /* PseudoSELECTFP_F_I64 */ |
12483 | | 1693, |
12484 | | /* PseudoSELECTFP_F_S */ |
12485 | | 1697, |
12486 | | /* PseudoSELECTFP_T_D32 */ |
12487 | | 1701, |
12488 | | /* PseudoSELECTFP_T_D64 */ |
12489 | | 1705, |
12490 | | /* PseudoSELECTFP_T_I */ |
12491 | | 1709, |
12492 | | /* PseudoSELECTFP_T_I64 */ |
12493 | | 1713, |
12494 | | /* PseudoSELECTFP_T_S */ |
12495 | | 1717, |
12496 | | /* PseudoSELECT_D32 */ |
12497 | | 1721, |
12498 | | /* PseudoSELECT_D64 */ |
12499 | | 1725, |
12500 | | /* PseudoSELECT_I */ |
12501 | | 1729, |
12502 | | /* PseudoSELECT_I64 */ |
12503 | | 1733, |
12504 | | /* PseudoSELECT_S */ |
12505 | | 1737, |
12506 | | /* PseudoTRUNC_W_D */ |
12507 | | 1741, |
12508 | | /* PseudoTRUNC_W_D32 */ |
12509 | | 1744, |
12510 | | /* PseudoTRUNC_W_S */ |
12511 | | 1747, |
12512 | | /* PseudoUDIV */ |
12513 | | 1750, |
12514 | | /* ROL */ |
12515 | | 1753, |
12516 | | /* ROLImm */ |
12517 | | 1756, |
12518 | | /* ROR */ |
12519 | | 1759, |
12520 | | /* RORImm */ |
12521 | | 1762, |
12522 | | /* RetRA */ |
12523 | | 1765, |
12524 | | /* RetRA16 */ |
12525 | | 1765, |
12526 | | /* SDC1_M1 */ |
12527 | | 1765, |
12528 | | /* SDIV_MM_Pseudo */ |
12529 | | 1768, |
12530 | | /* SDMacro */ |
12531 | | 1771, |
12532 | | /* SDivIMacro */ |
12533 | | 1774, |
12534 | | /* SDivMacro */ |
12535 | | 1777, |
12536 | | /* SEQIMacro */ |
12537 | | 1780, |
12538 | | /* SEQMacro */ |
12539 | | 1783, |
12540 | | /* SGE */ |
12541 | | 1786, |
12542 | | /* SGEImm */ |
12543 | | 1789, |
12544 | | /* SGEImm64 */ |
12545 | | 1792, |
12546 | | /* SGEU */ |
12547 | | 1795, |
12548 | | /* SGEUImm */ |
12549 | | 1798, |
12550 | | /* SGEUImm64 */ |
12551 | | 1801, |
12552 | | /* SGTImm */ |
12553 | | 1804, |
12554 | | /* SGTImm64 */ |
12555 | | 1807, |
12556 | | /* SGTUImm */ |
12557 | | 1810, |
12558 | | /* SGTUImm64 */ |
12559 | | 1813, |
12560 | | /* SLE */ |
12561 | | 1816, |
12562 | | /* SLEImm */ |
12563 | | 1819, |
12564 | | /* SLEImm64 */ |
12565 | | 1822, |
12566 | | /* SLEU */ |
12567 | | 1825, |
12568 | | /* SLEUImm */ |
12569 | | 1828, |
12570 | | /* SLEUImm64 */ |
12571 | | 1831, |
12572 | | /* SLTImm64 */ |
12573 | | 1834, |
12574 | | /* SLTUImm64 */ |
12575 | | 1837, |
12576 | | /* SNEIMacro */ |
12577 | | 1840, |
12578 | | /* SNEMacro */ |
12579 | | 1843, |
12580 | | /* SNZ_B_PSEUDO */ |
12581 | | 1846, |
12582 | | /* SNZ_D_PSEUDO */ |
12583 | | 1848, |
12584 | | /* SNZ_H_PSEUDO */ |
12585 | | 1850, |
12586 | | /* SNZ_V_PSEUDO */ |
12587 | | 1852, |
12588 | | /* SNZ_W_PSEUDO */ |
12589 | | 1854, |
12590 | | /* SRemIMacro */ |
12591 | | 1856, |
12592 | | /* SRemMacro */ |
12593 | | 1859, |
12594 | | /* STORE_ACC128 */ |
12595 | | 1862, |
12596 | | /* STORE_ACC64 */ |
12597 | | 1865, |
12598 | | /* STORE_ACC64DSP */ |
12599 | | 1868, |
12600 | | /* STORE_CCOND_DSP */ |
12601 | | 1871, |
12602 | | /* STR_D */ |
12603 | | 1874, |
12604 | | /* STR_W */ |
12605 | | 1877, |
12606 | | /* ST_F16 */ |
12607 | | 1880, |
12608 | | /* SWM_MM */ |
12609 | | 1883, |
12610 | | /* SZ_B_PSEUDO */ |
12611 | | 1886, |
12612 | | /* SZ_D_PSEUDO */ |
12613 | | 1888, |
12614 | | /* SZ_H_PSEUDO */ |
12615 | | 1890, |
12616 | | /* SZ_V_PSEUDO */ |
12617 | | 1892, |
12618 | | /* SZ_W_PSEUDO */ |
12619 | | 1894, |
12620 | | /* SaaAddr */ |
12621 | | 1896, |
12622 | | /* SaadAddr */ |
12623 | | 1899, |
12624 | | /* SelBeqZ */ |
12625 | | 1902, |
12626 | | /* SelBneZ */ |
12627 | | 1906, |
12628 | | /* SelTBteqZCmp */ |
12629 | | 1910, |
12630 | | /* SelTBteqZCmpi */ |
12631 | | 1915, |
12632 | | /* SelTBteqZSlt */ |
12633 | | 1920, |
12634 | | /* SelTBteqZSlti */ |
12635 | | 1925, |
12636 | | /* SelTBteqZSltiu */ |
12637 | | 1930, |
12638 | | /* SelTBteqZSltu */ |
12639 | | 1935, |
12640 | | /* SelTBtneZCmp */ |
12641 | | 1940, |
12642 | | /* SelTBtneZCmpi */ |
12643 | | 1945, |
12644 | | /* SelTBtneZSlt */ |
12645 | | 1950, |
12646 | | /* SelTBtneZSlti */ |
12647 | | 1955, |
12648 | | /* SelTBtneZSltiu */ |
12649 | | 1960, |
12650 | | /* SelTBtneZSltu */ |
12651 | | 1965, |
12652 | | /* SltCCRxRy16 */ |
12653 | | 1970, |
12654 | | /* SltiCCRxImmX16 */ |
12655 | | 1973, |
12656 | | /* SltiuCCRxImmX16 */ |
12657 | | 1976, |
12658 | | /* SltuCCRxRy16 */ |
12659 | | 1979, |
12660 | | /* SltuRxRyRz16 */ |
12661 | | 1982, |
12662 | | /* TAILCALL */ |
12663 | | 1985, |
12664 | | /* TAILCALL64R6REG */ |
12665 | | 1986, |
12666 | | /* TAILCALLHB64R6REG */ |
12667 | | 1987, |
12668 | | /* TAILCALLHBR6REG */ |
12669 | | 1988, |
12670 | | /* TAILCALLR6REG */ |
12671 | | 1989, |
12672 | | /* TAILCALLREG */ |
12673 | | 1990, |
12674 | | /* TAILCALLREG64 */ |
12675 | | 1991, |
12676 | | /* TAILCALLREGHB */ |
12677 | | 1992, |
12678 | | /* TAILCALLREGHB64 */ |
12679 | | 1993, |
12680 | | /* TAILCALLREG_MM */ |
12681 | | 1994, |
12682 | | /* TAILCALLREG_MMR6 */ |
12683 | | 1995, |
12684 | | /* TAILCALL_MM */ |
12685 | | 1996, |
12686 | | /* TAILCALL_MMR6 */ |
12687 | | 1997, |
12688 | | /* TRAP */ |
12689 | | 1998, |
12690 | | /* TRAP_MM */ |
12691 | | 1998, |
12692 | | /* UDIV_MM_Pseudo */ |
12693 | | 1998, |
12694 | | /* UDivIMacro */ |
12695 | | 2001, |
12696 | | /* UDivMacro */ |
12697 | | 2004, |
12698 | | /* URemIMacro */ |
12699 | | 2007, |
12700 | | /* URemMacro */ |
12701 | | 2010, |
12702 | | /* Ulh */ |
12703 | | 2013, |
12704 | | /* Ulhu */ |
12705 | | 2016, |
12706 | | /* Ulw */ |
12707 | | 2019, |
12708 | | /* Ush */ |
12709 | | 2022, |
12710 | | /* Usw */ |
12711 | | 2025, |
12712 | | /* XOR_V_D_PSEUDO */ |
12713 | | 2028, |
12714 | | /* XOR_V_H_PSEUDO */ |
12715 | | 2031, |
12716 | | /* XOR_V_W_PSEUDO */ |
12717 | | 2034, |
12718 | | /* ABSQ_S_PH */ |
12719 | | 2037, |
12720 | | /* ABSQ_S_PH_MM */ |
12721 | | 2039, |
12722 | | /* ABSQ_S_QB */ |
12723 | | 2041, |
12724 | | /* ABSQ_S_QB_MMR2 */ |
12725 | | 2043, |
12726 | | /* ABSQ_S_W */ |
12727 | | 2045, |
12728 | | /* ABSQ_S_W_MM */ |
12729 | | 2047, |
12730 | | /* ADD */ |
12731 | | 2049, |
12732 | | /* ADDIUPC */ |
12733 | | 2052, |
12734 | | /* ADDIUPC_MM */ |
12735 | | 2054, |
12736 | | /* ADDIUPC_MMR6 */ |
12737 | | 2056, |
12738 | | /* ADDIUR1SP_MM */ |
12739 | | 2058, |
12740 | | /* ADDIUR2_MM */ |
12741 | | 2060, |
12742 | | /* ADDIUS5_MM */ |
12743 | | 2063, |
12744 | | /* ADDIUSP_MM */ |
12745 | | 2066, |
12746 | | /* ADDIU_MMR6 */ |
12747 | | 2067, |
12748 | | /* ADDQH_PH */ |
12749 | | 2070, |
12750 | | /* ADDQH_PH_MMR2 */ |
12751 | | 2073, |
12752 | | /* ADDQH_R_PH */ |
12753 | | 2076, |
12754 | | /* ADDQH_R_PH_MMR2 */ |
12755 | | 2079, |
12756 | | /* ADDQH_R_W */ |
12757 | | 2082, |
12758 | | /* ADDQH_R_W_MMR2 */ |
12759 | | 2085, |
12760 | | /* ADDQH_W */ |
12761 | | 2088, |
12762 | | /* ADDQH_W_MMR2 */ |
12763 | | 2091, |
12764 | | /* ADDQ_PH */ |
12765 | | 2094, |
12766 | | /* ADDQ_PH_MM */ |
12767 | | 2097, |
12768 | | /* ADDQ_S_PH */ |
12769 | | 2100, |
12770 | | /* ADDQ_S_PH_MM */ |
12771 | | 2103, |
12772 | | /* ADDQ_S_W */ |
12773 | | 2106, |
12774 | | /* ADDQ_S_W_MM */ |
12775 | | 2109, |
12776 | | /* ADDR_PS64 */ |
12777 | | 2112, |
12778 | | /* ADDSC */ |
12779 | | 2115, |
12780 | | /* ADDSC_MM */ |
12781 | | 2118, |
12782 | | /* ADDS_A_B */ |
12783 | | 2121, |
12784 | | /* ADDS_A_D */ |
12785 | | 2124, |
12786 | | /* ADDS_A_H */ |
12787 | | 2127, |
12788 | | /* ADDS_A_W */ |
12789 | | 2130, |
12790 | | /* ADDS_S_B */ |
12791 | | 2133, |
12792 | | /* ADDS_S_D */ |
12793 | | 2136, |
12794 | | /* ADDS_S_H */ |
12795 | | 2139, |
12796 | | /* ADDS_S_W */ |
12797 | | 2142, |
12798 | | /* ADDS_U_B */ |
12799 | | 2145, |
12800 | | /* ADDS_U_D */ |
12801 | | 2148, |
12802 | | /* ADDS_U_H */ |
12803 | | 2151, |
12804 | | /* ADDS_U_W */ |
12805 | | 2154, |
12806 | | /* ADDU16_MM */ |
12807 | | 2157, |
12808 | | /* ADDU16_MMR6 */ |
12809 | | 2160, |
12810 | | /* ADDUH_QB */ |
12811 | | 2163, |
12812 | | /* ADDUH_QB_MMR2 */ |
12813 | | 2166, |
12814 | | /* ADDUH_R_QB */ |
12815 | | 2169, |
12816 | | /* ADDUH_R_QB_MMR2 */ |
12817 | | 2172, |
12818 | | /* ADDU_MMR6 */ |
12819 | | 2175, |
12820 | | /* ADDU_PH */ |
12821 | | 2178, |
12822 | | /* ADDU_PH_MMR2 */ |
12823 | | 2181, |
12824 | | /* ADDU_QB */ |
12825 | | 2184, |
12826 | | /* ADDU_QB_MM */ |
12827 | | 2187, |
12828 | | /* ADDU_S_PH */ |
12829 | | 2190, |
12830 | | /* ADDU_S_PH_MMR2 */ |
12831 | | 2193, |
12832 | | /* ADDU_S_QB */ |
12833 | | 2196, |
12834 | | /* ADDU_S_QB_MM */ |
12835 | | 2199, |
12836 | | /* ADDVI_B */ |
12837 | | 2202, |
12838 | | /* ADDVI_D */ |
12839 | | 2205, |
12840 | | /* ADDVI_H */ |
12841 | | 2208, |
12842 | | /* ADDVI_W */ |
12843 | | 2211, |
12844 | | /* ADDV_B */ |
12845 | | 2214, |
12846 | | /* ADDV_D */ |
12847 | | 2217, |
12848 | | /* ADDV_H */ |
12849 | | 2220, |
12850 | | /* ADDV_W */ |
12851 | | 2223, |
12852 | | /* ADDWC */ |
12853 | | 2226, |
12854 | | /* ADDWC_MM */ |
12855 | | 2229, |
12856 | | /* ADD_A_B */ |
12857 | | 2232, |
12858 | | /* ADD_A_D */ |
12859 | | 2235, |
12860 | | /* ADD_A_H */ |
12861 | | 2238, |
12862 | | /* ADD_A_W */ |
12863 | | 2241, |
12864 | | /* ADD_MM */ |
12865 | | 2244, |
12866 | | /* ADD_MMR6 */ |
12867 | | 2247, |
12868 | | /* ADDi */ |
12869 | | 2250, |
12870 | | /* ADDi_MM */ |
12871 | | 2253, |
12872 | | /* ADDiu */ |
12873 | | 2256, |
12874 | | /* ADDiu_MM */ |
12875 | | 2259, |
12876 | | /* ADDu */ |
12877 | | 2262, |
12878 | | /* ADDu_MM */ |
12879 | | 2265, |
12880 | | /* ALIGN */ |
12881 | | 2268, |
12882 | | /* ALIGN_MMR6 */ |
12883 | | 2272, |
12884 | | /* ALUIPC */ |
12885 | | 2276, |
12886 | | /* ALUIPC_MMR6 */ |
12887 | | 2278, |
12888 | | /* AND */ |
12889 | | 2280, |
12890 | | /* AND16_MM */ |
12891 | | 2283, |
12892 | | /* AND16_MMR6 */ |
12893 | | 2286, |
12894 | | /* AND64 */ |
12895 | | 2289, |
12896 | | /* ANDI16_MM */ |
12897 | | 2292, |
12898 | | /* ANDI16_MMR6 */ |
12899 | | 2295, |
12900 | | /* ANDI_B */ |
12901 | | 2298, |
12902 | | /* ANDI_MMR6 */ |
12903 | | 2301, |
12904 | | /* AND_MM */ |
12905 | | 2304, |
12906 | | /* AND_MMR6 */ |
12907 | | 2307, |
12908 | | /* AND_V */ |
12909 | | 2310, |
12910 | | /* ANDi */ |
12911 | | 2313, |
12912 | | /* ANDi64 */ |
12913 | | 2316, |
12914 | | /* ANDi_MM */ |
12915 | | 2319, |
12916 | | /* APPEND */ |
12917 | | 2322, |
12918 | | /* APPEND_MMR2 */ |
12919 | | 2326, |
12920 | | /* ASUB_S_B */ |
12921 | | 2330, |
12922 | | /* ASUB_S_D */ |
12923 | | 2333, |
12924 | | /* ASUB_S_H */ |
12925 | | 2336, |
12926 | | /* ASUB_S_W */ |
12927 | | 2339, |
12928 | | /* ASUB_U_B */ |
12929 | | 2342, |
12930 | | /* ASUB_U_D */ |
12931 | | 2345, |
12932 | | /* ASUB_U_H */ |
12933 | | 2348, |
12934 | | /* ASUB_U_W */ |
12935 | | 2351, |
12936 | | /* AUI */ |
12937 | | 2354, |
12938 | | /* AUIPC */ |
12939 | | 2357, |
12940 | | /* AUIPC_MMR6 */ |
12941 | | 2359, |
12942 | | /* AUI_MMR6 */ |
12943 | | 2361, |
12944 | | /* AVER_S_B */ |
12945 | | 2364, |
12946 | | /* AVER_S_D */ |
12947 | | 2367, |
12948 | | /* AVER_S_H */ |
12949 | | 2370, |
12950 | | /* AVER_S_W */ |
12951 | | 2373, |
12952 | | /* AVER_U_B */ |
12953 | | 2376, |
12954 | | /* AVER_U_D */ |
12955 | | 2379, |
12956 | | /* AVER_U_H */ |
12957 | | 2382, |
12958 | | /* AVER_U_W */ |
12959 | | 2385, |
12960 | | /* AVE_S_B */ |
12961 | | 2388, |
12962 | | /* AVE_S_D */ |
12963 | | 2391, |
12964 | | /* AVE_S_H */ |
12965 | | 2394, |
12966 | | /* AVE_S_W */ |
12967 | | 2397, |
12968 | | /* AVE_U_B */ |
12969 | | 2400, |
12970 | | /* AVE_U_D */ |
12971 | | 2403, |
12972 | | /* AVE_U_H */ |
12973 | | 2406, |
12974 | | /* AVE_U_W */ |
12975 | | 2409, |
12976 | | /* AddiuRxImmX16 */ |
12977 | | 2412, |
12978 | | /* AddiuRxPcImmX16 */ |
12979 | | 2414, |
12980 | | /* AddiuRxRxImm16 */ |
12981 | | 2416, |
12982 | | /* AddiuRxRxImmX16 */ |
12983 | | 2419, |
12984 | | /* AddiuRxRyOffMemX16 */ |
12985 | | 2422, |
12986 | | /* AddiuSpImm16 */ |
12987 | | 2425, |
12988 | | /* AddiuSpImmX16 */ |
12989 | | 2426, |
12990 | | /* AdduRxRyRz16 */ |
12991 | | 2427, |
12992 | | /* AndRxRxRy16 */ |
12993 | | 2430, |
12994 | | /* B16_MM */ |
12995 | | 2433, |
12996 | | /* BADDu */ |
12997 | | 2434, |
12998 | | /* BAL */ |
12999 | | 2437, |
13000 | | /* BALC */ |
13001 | | 2438, |
13002 | | /* BALC_MMR6 */ |
13003 | | 2439, |
13004 | | /* BALIGN */ |
13005 | | 2440, |
13006 | | /* BALIGN_MMR2 */ |
13007 | | 2444, |
13008 | | /* BBIT0 */ |
13009 | | 2448, |
13010 | | /* BBIT032 */ |
13011 | | 2451, |
13012 | | /* BBIT1 */ |
13013 | | 2454, |
13014 | | /* BBIT132 */ |
13015 | | 2457, |
13016 | | /* BC */ |
13017 | | 2460, |
13018 | | /* BC16_MMR6 */ |
13019 | | 2461, |
13020 | | /* BC1EQZ */ |
13021 | | 2462, |
13022 | | /* BC1EQZC_MMR6 */ |
13023 | | 2464, |
13024 | | /* BC1F */ |
13025 | | 2466, |
13026 | | /* BC1FL */ |
13027 | | 2468, |
13028 | | /* BC1F_MM */ |
13029 | | 2470, |
13030 | | /* BC1NEZ */ |
13031 | | 2472, |
13032 | | /* BC1NEZC_MMR6 */ |
13033 | | 2474, |
13034 | | /* BC1T */ |
13035 | | 2476, |
13036 | | /* BC1TL */ |
13037 | | 2478, |
13038 | | /* BC1T_MM */ |
13039 | | 2480, |
13040 | | /* BC2EQZ */ |
13041 | | 2482, |
13042 | | /* BC2EQZC_MMR6 */ |
13043 | | 2484, |
13044 | | /* BC2NEZ */ |
13045 | | 2486, |
13046 | | /* BC2NEZC_MMR6 */ |
13047 | | 2488, |
13048 | | /* BCLRI_B */ |
13049 | | 2490, |
13050 | | /* BCLRI_D */ |
13051 | | 2493, |
13052 | | /* BCLRI_H */ |
13053 | | 2496, |
13054 | | /* BCLRI_W */ |
13055 | | 2499, |
13056 | | /* BCLR_B */ |
13057 | | 2502, |
13058 | | /* BCLR_D */ |
13059 | | 2505, |
13060 | | /* BCLR_H */ |
13061 | | 2508, |
13062 | | /* BCLR_W */ |
13063 | | 2511, |
13064 | | /* BC_MMR6 */ |
13065 | | 2514, |
13066 | | /* BEQ */ |
13067 | | 2515, |
13068 | | /* BEQ64 */ |
13069 | | 2518, |
13070 | | /* BEQC */ |
13071 | | 2521, |
13072 | | /* BEQC64 */ |
13073 | | 2524, |
13074 | | /* BEQC_MMR6 */ |
13075 | | 2527, |
13076 | | /* BEQL */ |
13077 | | 2530, |
13078 | | /* BEQZ16_MM */ |
13079 | | 2533, |
13080 | | /* BEQZALC */ |
13081 | | 2535, |
13082 | | /* BEQZALC_MMR6 */ |
13083 | | 2537, |
13084 | | /* BEQZC */ |
13085 | | 2539, |
13086 | | /* BEQZC16_MMR6 */ |
13087 | | 2541, |
13088 | | /* BEQZC64 */ |
13089 | | 2543, |
13090 | | /* BEQZC_MM */ |
13091 | | 2545, |
13092 | | /* BEQZC_MMR6 */ |
13093 | | 2547, |
13094 | | /* BEQ_MM */ |
13095 | | 2549, |
13096 | | /* BGEC */ |
13097 | | 2552, |
13098 | | /* BGEC64 */ |
13099 | | 2555, |
13100 | | /* BGEC_MMR6 */ |
13101 | | 2558, |
13102 | | /* BGEUC */ |
13103 | | 2561, |
13104 | | /* BGEUC64 */ |
13105 | | 2564, |
13106 | | /* BGEUC_MMR6 */ |
13107 | | 2567, |
13108 | | /* BGEZ */ |
13109 | | 2570, |
13110 | | /* BGEZ64 */ |
13111 | | 2572, |
13112 | | /* BGEZAL */ |
13113 | | 2574, |
13114 | | /* BGEZALC */ |
13115 | | 2576, |
13116 | | /* BGEZALC_MMR6 */ |
13117 | | 2578, |
13118 | | /* BGEZALL */ |
13119 | | 2580, |
13120 | | /* BGEZALS_MM */ |
13121 | | 2582, |
13122 | | /* BGEZAL_MM */ |
13123 | | 2584, |
13124 | | /* BGEZC */ |
13125 | | 2586, |
13126 | | /* BGEZC64 */ |
13127 | | 2588, |
13128 | | /* BGEZC_MMR6 */ |
13129 | | 2590, |
13130 | | /* BGEZL */ |
13131 | | 2592, |
13132 | | /* BGEZ_MM */ |
13133 | | 2594, |
13134 | | /* BGTZ */ |
13135 | | 2596, |
13136 | | /* BGTZ64 */ |
13137 | | 2598, |
13138 | | /* BGTZALC */ |
13139 | | 2600, |
13140 | | /* BGTZALC_MMR6 */ |
13141 | | 2602, |
13142 | | /* BGTZC */ |
13143 | | 2604, |
13144 | | /* BGTZC64 */ |
13145 | | 2606, |
13146 | | /* BGTZC_MMR6 */ |
13147 | | 2608, |
13148 | | /* BGTZL */ |
13149 | | 2610, |
13150 | | /* BGTZ_MM */ |
13151 | | 2612, |
13152 | | /* BINSLI_B */ |
13153 | | 2614, |
13154 | | /* BINSLI_D */ |
13155 | | 2618, |
13156 | | /* BINSLI_H */ |
13157 | | 2622, |
13158 | | /* BINSLI_W */ |
13159 | | 2626, |
13160 | | /* BINSL_B */ |
13161 | | 2630, |
13162 | | /* BINSL_D */ |
13163 | | 2634, |
13164 | | /* BINSL_H */ |
13165 | | 2638, |
13166 | | /* BINSL_W */ |
13167 | | 2642, |
13168 | | /* BINSRI_B */ |
13169 | | 2646, |
13170 | | /* BINSRI_D */ |
13171 | | 2650, |
13172 | | /* BINSRI_H */ |
13173 | | 2654, |
13174 | | /* BINSRI_W */ |
13175 | | 2658, |
13176 | | /* BINSR_B */ |
13177 | | 2662, |
13178 | | /* BINSR_D */ |
13179 | | 2666, |
13180 | | /* BINSR_H */ |
13181 | | 2670, |
13182 | | /* BINSR_W */ |
13183 | | 2674, |
13184 | | /* BITREV */ |
13185 | | 2678, |
13186 | | /* BITREV_MM */ |
13187 | | 2680, |
13188 | | /* BITSWAP */ |
13189 | | 2682, |
13190 | | /* BITSWAP_MMR6 */ |
13191 | | 2684, |
13192 | | /* BLEZ */ |
13193 | | 2686, |
13194 | | /* BLEZ64 */ |
13195 | | 2688, |
13196 | | /* BLEZALC */ |
13197 | | 2690, |
13198 | | /* BLEZALC_MMR6 */ |
13199 | | 2692, |
13200 | | /* BLEZC */ |
13201 | | 2694, |
13202 | | /* BLEZC64 */ |
13203 | | 2696, |
13204 | | /* BLEZC_MMR6 */ |
13205 | | 2698, |
13206 | | /* BLEZL */ |
13207 | | 2700, |
13208 | | /* BLEZ_MM */ |
13209 | | 2702, |
13210 | | /* BLTC */ |
13211 | | 2704, |
13212 | | /* BLTC64 */ |
13213 | | 2707, |
13214 | | /* BLTC_MMR6 */ |
13215 | | 2710, |
13216 | | /* BLTUC */ |
13217 | | 2713, |
13218 | | /* BLTUC64 */ |
13219 | | 2716, |
13220 | | /* BLTUC_MMR6 */ |
13221 | | 2719, |
13222 | | /* BLTZ */ |
13223 | | 2722, |
13224 | | /* BLTZ64 */ |
13225 | | 2724, |
13226 | | /* BLTZAL */ |
13227 | | 2726, |
13228 | | /* BLTZALC */ |
13229 | | 2728, |
13230 | | /* BLTZALC_MMR6 */ |
13231 | | 2730, |
13232 | | /* BLTZALL */ |
13233 | | 2732, |
13234 | | /* BLTZALS_MM */ |
13235 | | 2734, |
13236 | | /* BLTZAL_MM */ |
13237 | | 2736, |
13238 | | /* BLTZC */ |
13239 | | 2738, |
13240 | | /* BLTZC64 */ |
13241 | | 2740, |
13242 | | /* BLTZC_MMR6 */ |
13243 | | 2742, |
13244 | | /* BLTZL */ |
13245 | | 2744, |
13246 | | /* BLTZ_MM */ |
13247 | | 2746, |
13248 | | /* BMNZI_B */ |
13249 | | 2748, |
13250 | | /* BMNZ_V */ |
13251 | | 2752, |
13252 | | /* BMZI_B */ |
13253 | | 2756, |
13254 | | /* BMZ_V */ |
13255 | | 2760, |
13256 | | /* BNE */ |
13257 | | 2764, |
13258 | | /* BNE64 */ |
13259 | | 2767, |
13260 | | /* BNEC */ |
13261 | | 2770, |
13262 | | /* BNEC64 */ |
13263 | | 2773, |
13264 | | /* BNEC_MMR6 */ |
13265 | | 2776, |
13266 | | /* BNEGI_B */ |
13267 | | 2779, |
13268 | | /* BNEGI_D */ |
13269 | | 2782, |
13270 | | /* BNEGI_H */ |
13271 | | 2785, |
13272 | | /* BNEGI_W */ |
13273 | | 2788, |
13274 | | /* BNEG_B */ |
13275 | | 2791, |
13276 | | /* BNEG_D */ |
13277 | | 2794, |
13278 | | /* BNEG_H */ |
13279 | | 2797, |
13280 | | /* BNEG_W */ |
13281 | | 2800, |
13282 | | /* BNEL */ |
13283 | | 2803, |
13284 | | /* BNEZ16_MM */ |
13285 | | 2806, |
13286 | | /* BNEZALC */ |
13287 | | 2808, |
13288 | | /* BNEZALC_MMR6 */ |
13289 | | 2810, |
13290 | | /* BNEZC */ |
13291 | | 2812, |
13292 | | /* BNEZC16_MMR6 */ |
13293 | | 2814, |
13294 | | /* BNEZC64 */ |
13295 | | 2816, |
13296 | | /* BNEZC_MM */ |
13297 | | 2818, |
13298 | | /* BNEZC_MMR6 */ |
13299 | | 2820, |
13300 | | /* BNE_MM */ |
13301 | | 2822, |
13302 | | /* BNVC */ |
13303 | | 2825, |
13304 | | /* BNVC_MMR6 */ |
13305 | | 2828, |
13306 | | /* BNZ_B */ |
13307 | | 2831, |
13308 | | /* BNZ_D */ |
13309 | | 2833, |
13310 | | /* BNZ_H */ |
13311 | | 2835, |
13312 | | /* BNZ_V */ |
13313 | | 2837, |
13314 | | /* BNZ_W */ |
13315 | | 2839, |
13316 | | /* BOVC */ |
13317 | | 2841, |
13318 | | /* BOVC_MMR6 */ |
13319 | | 2844, |
13320 | | /* BPOSGE32 */ |
13321 | | 2847, |
13322 | | /* BPOSGE32C_MMR3 */ |
13323 | | 2848, |
13324 | | /* BPOSGE32_MM */ |
13325 | | 2849, |
13326 | | /* BREAK */ |
13327 | | 2850, |
13328 | | /* BREAK16_MM */ |
13329 | | 2852, |
13330 | | /* BREAK16_MMR6 */ |
13331 | | 2853, |
13332 | | /* BREAK_MM */ |
13333 | | 2854, |
13334 | | /* BREAK_MMR6 */ |
13335 | | 2856, |
13336 | | /* BSELI_B */ |
13337 | | 2858, |
13338 | | /* BSEL_V */ |
13339 | | 2862, |
13340 | | /* BSETI_B */ |
13341 | | 2866, |
13342 | | /* BSETI_D */ |
13343 | | 2869, |
13344 | | /* BSETI_H */ |
13345 | | 2872, |
13346 | | /* BSETI_W */ |
13347 | | 2875, |
13348 | | /* BSET_B */ |
13349 | | 2878, |
13350 | | /* BSET_D */ |
13351 | | 2881, |
13352 | | /* BSET_H */ |
13353 | | 2884, |
13354 | | /* BSET_W */ |
13355 | | 2887, |
13356 | | /* BZ_B */ |
13357 | | 2890, |
13358 | | /* BZ_D */ |
13359 | | 2892, |
13360 | | /* BZ_H */ |
13361 | | 2894, |
13362 | | /* BZ_V */ |
13363 | | 2896, |
13364 | | /* BZ_W */ |
13365 | | 2898, |
13366 | | /* BeqzRxImm16 */ |
13367 | | 2900, |
13368 | | /* BeqzRxImmX16 */ |
13369 | | 2902, |
13370 | | /* Bimm16 */ |
13371 | | 2904, |
13372 | | /* BimmX16 */ |
13373 | | 2905, |
13374 | | /* BnezRxImm16 */ |
13375 | | 2906, |
13376 | | /* BnezRxImmX16 */ |
13377 | | 2908, |
13378 | | /* Break16 */ |
13379 | | 2910, |
13380 | | /* Bteqz16 */ |
13381 | | 2910, |
13382 | | /* BteqzX16 */ |
13383 | | 2911, |
13384 | | /* Btnez16 */ |
13385 | | 2912, |
13386 | | /* BtnezX16 */ |
13387 | | 2913, |
13388 | | /* CACHE */ |
13389 | | 2914, |
13390 | | /* CACHEE */ |
13391 | | 2917, |
13392 | | /* CACHEE_MM */ |
13393 | | 2920, |
13394 | | /* CACHE_MM */ |
13395 | | 2923, |
13396 | | /* CACHE_MMR6 */ |
13397 | | 2926, |
13398 | | /* CACHE_R6 */ |
13399 | | 2929, |
13400 | | /* CEIL_L_D64 */ |
13401 | | 2932, |
13402 | | /* CEIL_L_D_MMR6 */ |
13403 | | 2934, |
13404 | | /* CEIL_L_S */ |
13405 | | 2936, |
13406 | | /* CEIL_L_S_MMR6 */ |
13407 | | 2938, |
13408 | | /* CEIL_W_D32 */ |
13409 | | 2940, |
13410 | | /* CEIL_W_D64 */ |
13411 | | 2942, |
13412 | | /* CEIL_W_D_MMR6 */ |
13413 | | 2944, |
13414 | | /* CEIL_W_MM */ |
13415 | | 2946, |
13416 | | /* CEIL_W_S */ |
13417 | | 2948, |
13418 | | /* CEIL_W_S_MM */ |
13419 | | 2950, |
13420 | | /* CEIL_W_S_MMR6 */ |
13421 | | 2952, |
13422 | | /* CEQI_B */ |
13423 | | 2954, |
13424 | | /* CEQI_D */ |
13425 | | 2957, |
13426 | | /* CEQI_H */ |
13427 | | 2960, |
13428 | | /* CEQI_W */ |
13429 | | 2963, |
13430 | | /* CEQ_B */ |
13431 | | 2966, |
13432 | | /* CEQ_D */ |
13433 | | 2969, |
13434 | | /* CEQ_H */ |
13435 | | 2972, |
13436 | | /* CEQ_W */ |
13437 | | 2975, |
13438 | | /* CFC1 */ |
13439 | | 2978, |
13440 | | /* CFC1_MM */ |
13441 | | 2980, |
13442 | | /* CFC2_MM */ |
13443 | | 2982, |
13444 | | /* CFCMSA */ |
13445 | | 2984, |
13446 | | /* CINS */ |
13447 | | 2986, |
13448 | | /* CINS32 */ |
13449 | | 2990, |
13450 | | /* CINS64_32 */ |
13451 | | 2994, |
13452 | | /* CINS_i32 */ |
13453 | | 2998, |
13454 | | /* CLASS_D */ |
13455 | | 3002, |
13456 | | /* CLASS_D_MMR6 */ |
13457 | | 3004, |
13458 | | /* CLASS_S */ |
13459 | | 3006, |
13460 | | /* CLASS_S_MMR6 */ |
13461 | | 3008, |
13462 | | /* CLEI_S_B */ |
13463 | | 3010, |
13464 | | /* CLEI_S_D */ |
13465 | | 3013, |
13466 | | /* CLEI_S_H */ |
13467 | | 3016, |
13468 | | /* CLEI_S_W */ |
13469 | | 3019, |
13470 | | /* CLEI_U_B */ |
13471 | | 3022, |
13472 | | /* CLEI_U_D */ |
13473 | | 3025, |
13474 | | /* CLEI_U_H */ |
13475 | | 3028, |
13476 | | /* CLEI_U_W */ |
13477 | | 3031, |
13478 | | /* CLE_S_B */ |
13479 | | 3034, |
13480 | | /* CLE_S_D */ |
13481 | | 3037, |
13482 | | /* CLE_S_H */ |
13483 | | 3040, |
13484 | | /* CLE_S_W */ |
13485 | | 3043, |
13486 | | /* CLE_U_B */ |
13487 | | 3046, |
13488 | | /* CLE_U_D */ |
13489 | | 3049, |
13490 | | /* CLE_U_H */ |
13491 | | 3052, |
13492 | | /* CLE_U_W */ |
13493 | | 3055, |
13494 | | /* CLO */ |
13495 | | 3058, |
13496 | | /* CLO_MM */ |
13497 | | 3060, |
13498 | | /* CLO_MMR6 */ |
13499 | | 3062, |
13500 | | /* CLO_R6 */ |
13501 | | 3064, |
13502 | | /* CLTI_S_B */ |
13503 | | 3066, |
13504 | | /* CLTI_S_D */ |
13505 | | 3069, |
13506 | | /* CLTI_S_H */ |
13507 | | 3072, |
13508 | | /* CLTI_S_W */ |
13509 | | 3075, |
13510 | | /* CLTI_U_B */ |
13511 | | 3078, |
13512 | | /* CLTI_U_D */ |
13513 | | 3081, |
13514 | | /* CLTI_U_H */ |
13515 | | 3084, |
13516 | | /* CLTI_U_W */ |
13517 | | 3087, |
13518 | | /* CLT_S_B */ |
13519 | | 3090, |
13520 | | /* CLT_S_D */ |
13521 | | 3093, |
13522 | | /* CLT_S_H */ |
13523 | | 3096, |
13524 | | /* CLT_S_W */ |
13525 | | 3099, |
13526 | | /* CLT_U_B */ |
13527 | | 3102, |
13528 | | /* CLT_U_D */ |
13529 | | 3105, |
13530 | | /* CLT_U_H */ |
13531 | | 3108, |
13532 | | /* CLT_U_W */ |
13533 | | 3111, |
13534 | | /* CLZ */ |
13535 | | 3114, |
13536 | | /* CLZ_MM */ |
13537 | | 3116, |
13538 | | /* CLZ_MMR6 */ |
13539 | | 3118, |
13540 | | /* CLZ_R6 */ |
13541 | | 3120, |
13542 | | /* CMPGDU_EQ_QB */ |
13543 | | 3122, |
13544 | | /* CMPGDU_EQ_QB_MMR2 */ |
13545 | | 3125, |
13546 | | /* CMPGDU_LE_QB */ |
13547 | | 3128, |
13548 | | /* CMPGDU_LE_QB_MMR2 */ |
13549 | | 3131, |
13550 | | /* CMPGDU_LT_QB */ |
13551 | | 3134, |
13552 | | /* CMPGDU_LT_QB_MMR2 */ |
13553 | | 3137, |
13554 | | /* CMPGU_EQ_QB */ |
13555 | | 3140, |
13556 | | /* CMPGU_EQ_QB_MM */ |
13557 | | 3143, |
13558 | | /* CMPGU_LE_QB */ |
13559 | | 3146, |
13560 | | /* CMPGU_LE_QB_MM */ |
13561 | | 3149, |
13562 | | /* CMPGU_LT_QB */ |
13563 | | 3152, |
13564 | | /* CMPGU_LT_QB_MM */ |
13565 | | 3155, |
13566 | | /* CMPU_EQ_QB */ |
13567 | | 3158, |
13568 | | /* CMPU_EQ_QB_MM */ |
13569 | | 3160, |
13570 | | /* CMPU_LE_QB */ |
13571 | | 3162, |
13572 | | /* CMPU_LE_QB_MM */ |
13573 | | 3164, |
13574 | | /* CMPU_LT_QB */ |
13575 | | 3166, |
13576 | | /* CMPU_LT_QB_MM */ |
13577 | | 3168, |
13578 | | /* CMP_AF_D_MMR6 */ |
13579 | | 3170, |
13580 | | /* CMP_AF_S_MMR6 */ |
13581 | | 3173, |
13582 | | /* CMP_EQ_D */ |
13583 | | 3176, |
13584 | | /* CMP_EQ_D_MMR6 */ |
13585 | | 3179, |
13586 | | /* CMP_EQ_PH */ |
13587 | | 3182, |
13588 | | /* CMP_EQ_PH_MM */ |
13589 | | 3184, |
13590 | | /* CMP_EQ_S */ |
13591 | | 3186, |
13592 | | /* CMP_EQ_S_MMR6 */ |
13593 | | 3189, |
13594 | | /* CMP_F_D */ |
13595 | | 3192, |
13596 | | /* CMP_F_S */ |
13597 | | 3195, |
13598 | | /* CMP_LE_D */ |
13599 | | 3198, |
13600 | | /* CMP_LE_D_MMR6 */ |
13601 | | 3201, |
13602 | | /* CMP_LE_PH */ |
13603 | | 3204, |
13604 | | /* CMP_LE_PH_MM */ |
13605 | | 3206, |
13606 | | /* CMP_LE_S */ |
13607 | | 3208, |
13608 | | /* CMP_LE_S_MMR6 */ |
13609 | | 3211, |
13610 | | /* CMP_LT_D */ |
13611 | | 3214, |
13612 | | /* CMP_LT_D_MMR6 */ |
13613 | | 3217, |
13614 | | /* CMP_LT_PH */ |
13615 | | 3220, |
13616 | | /* CMP_LT_PH_MM */ |
13617 | | 3222, |
13618 | | /* CMP_LT_S */ |
13619 | | 3224, |
13620 | | /* CMP_LT_S_MMR6 */ |
13621 | | 3227, |
13622 | | /* CMP_SAF_D */ |
13623 | | 3230, |
13624 | | /* CMP_SAF_D_MMR6 */ |
13625 | | 3233, |
13626 | | /* CMP_SAF_S */ |
13627 | | 3236, |
13628 | | /* CMP_SAF_S_MMR6 */ |
13629 | | 3239, |
13630 | | /* CMP_SEQ_D */ |
13631 | | 3242, |
13632 | | /* CMP_SEQ_D_MMR6 */ |
13633 | | 3245, |
13634 | | /* CMP_SEQ_S */ |
13635 | | 3248, |
13636 | | /* CMP_SEQ_S_MMR6 */ |
13637 | | 3251, |
13638 | | /* CMP_SLE_D */ |
13639 | | 3254, |
13640 | | /* CMP_SLE_D_MMR6 */ |
13641 | | 3257, |
13642 | | /* CMP_SLE_S */ |
13643 | | 3260, |
13644 | | /* CMP_SLE_S_MMR6 */ |
13645 | | 3263, |
13646 | | /* CMP_SLT_D */ |
13647 | | 3266, |
13648 | | /* CMP_SLT_D_MMR6 */ |
13649 | | 3269, |
13650 | | /* CMP_SLT_S */ |
13651 | | 3272, |
13652 | | /* CMP_SLT_S_MMR6 */ |
13653 | | 3275, |
13654 | | /* CMP_SUEQ_D */ |
13655 | | 3278, |
13656 | | /* CMP_SUEQ_D_MMR6 */ |
13657 | | 3281, |
13658 | | /* CMP_SUEQ_S */ |
13659 | | 3284, |
13660 | | /* CMP_SUEQ_S_MMR6 */ |
13661 | | 3287, |
13662 | | /* CMP_SULE_D */ |
13663 | | 3290, |
13664 | | /* CMP_SULE_D_MMR6 */ |
13665 | | 3293, |
13666 | | /* CMP_SULE_S */ |
13667 | | 3296, |
13668 | | /* CMP_SULE_S_MMR6 */ |
13669 | | 3299, |
13670 | | /* CMP_SULT_D */ |
13671 | | 3302, |
13672 | | /* CMP_SULT_D_MMR6 */ |
13673 | | 3305, |
13674 | | /* CMP_SULT_S */ |
13675 | | 3308, |
13676 | | /* CMP_SULT_S_MMR6 */ |
13677 | | 3311, |
13678 | | /* CMP_SUN_D */ |
13679 | | 3314, |
13680 | | /* CMP_SUN_D_MMR6 */ |
13681 | | 3317, |
13682 | | /* CMP_SUN_S */ |
13683 | | 3320, |
13684 | | /* CMP_SUN_S_MMR6 */ |
13685 | | 3323, |
13686 | | /* CMP_UEQ_D */ |
13687 | | 3326, |
13688 | | /* CMP_UEQ_D_MMR6 */ |
13689 | | 3329, |
13690 | | /* CMP_UEQ_S */ |
13691 | | 3332, |
13692 | | /* CMP_UEQ_S_MMR6 */ |
13693 | | 3335, |
13694 | | /* CMP_ULE_D */ |
13695 | | 3338, |
13696 | | /* CMP_ULE_D_MMR6 */ |
13697 | | 3341, |
13698 | | /* CMP_ULE_S */ |
13699 | | 3344, |
13700 | | /* CMP_ULE_S_MMR6 */ |
13701 | | 3347, |
13702 | | /* CMP_ULT_D */ |
13703 | | 3350, |
13704 | | /* CMP_ULT_D_MMR6 */ |
13705 | | 3353, |
13706 | | /* CMP_ULT_S */ |
13707 | | 3356, |
13708 | | /* CMP_ULT_S_MMR6 */ |
13709 | | 3359, |
13710 | | /* CMP_UN_D */ |
13711 | | 3362, |
13712 | | /* CMP_UN_D_MMR6 */ |
13713 | | 3365, |
13714 | | /* CMP_UN_S */ |
13715 | | 3368, |
13716 | | /* CMP_UN_S_MMR6 */ |
13717 | | 3371, |
13718 | | /* COPY_S_B */ |
13719 | | 3374, |
13720 | | /* COPY_S_D */ |
13721 | | 3377, |
13722 | | /* COPY_S_H */ |
13723 | | 3380, |
13724 | | /* COPY_S_W */ |
13725 | | 3383, |
13726 | | /* COPY_U_B */ |
13727 | | 3386, |
13728 | | /* COPY_U_H */ |
13729 | | 3389, |
13730 | | /* COPY_U_W */ |
13731 | | 3392, |
13732 | | /* CRC32B */ |
13733 | | 3395, |
13734 | | /* CRC32CB */ |
13735 | | 3398, |
13736 | | /* CRC32CD */ |
13737 | | 3401, |
13738 | | /* CRC32CH */ |
13739 | | 3404, |
13740 | | /* CRC32CW */ |
13741 | | 3407, |
13742 | | /* CRC32D */ |
13743 | | 3410, |
13744 | | /* CRC32H */ |
13745 | | 3413, |
13746 | | /* CRC32W */ |
13747 | | 3416, |
13748 | | /* CTC1 */ |
13749 | | 3419, |
13750 | | /* CTC1_MM */ |
13751 | | 3421, |
13752 | | /* CTC2_MM */ |
13753 | | 3423, |
13754 | | /* CTCMSA */ |
13755 | | 3425, |
13756 | | /* CVT_D32_S */ |
13757 | | 3427, |
13758 | | /* CVT_D32_S_MM */ |
13759 | | 3429, |
13760 | | /* CVT_D32_W */ |
13761 | | 3431, |
13762 | | /* CVT_D32_W_MM */ |
13763 | | 3433, |
13764 | | /* CVT_D64_L */ |
13765 | | 3435, |
13766 | | /* CVT_D64_S */ |
13767 | | 3437, |
13768 | | /* CVT_D64_S_MM */ |
13769 | | 3439, |
13770 | | /* CVT_D64_W */ |
13771 | | 3441, |
13772 | | /* CVT_D64_W_MM */ |
13773 | | 3443, |
13774 | | /* CVT_D_L_MMR6 */ |
13775 | | 3445, |
13776 | | /* CVT_L_D64 */ |
13777 | | 3447, |
13778 | | /* CVT_L_D64_MM */ |
13779 | | 3449, |
13780 | | /* CVT_L_D_MMR6 */ |
13781 | | 3451, |
13782 | | /* CVT_L_S */ |
13783 | | 3453, |
13784 | | /* CVT_L_S_MM */ |
13785 | | 3455, |
13786 | | /* CVT_L_S_MMR6 */ |
13787 | | 3457, |
13788 | | /* CVT_PS_PW64 */ |
13789 | | 3459, |
13790 | | /* CVT_PS_S64 */ |
13791 | | 3461, |
13792 | | /* CVT_PW_PS64 */ |
13793 | | 3464, |
13794 | | /* CVT_S_D32 */ |
13795 | | 3466, |
13796 | | /* CVT_S_D32_MM */ |
13797 | | 3468, |
13798 | | /* CVT_S_D64 */ |
13799 | | 3470, |
13800 | | /* CVT_S_D64_MM */ |
13801 | | 3472, |
13802 | | /* CVT_S_L */ |
13803 | | 3474, |
13804 | | /* CVT_S_L_MMR6 */ |
13805 | | 3476, |
13806 | | /* CVT_S_PL64 */ |
13807 | | 3478, |
13808 | | /* CVT_S_PU64 */ |
13809 | | 3480, |
13810 | | /* CVT_S_W */ |
13811 | | 3482, |
13812 | | /* CVT_S_W_MM */ |
13813 | | 3484, |
13814 | | /* CVT_S_W_MMR6 */ |
13815 | | 3486, |
13816 | | /* CVT_W_D32 */ |
13817 | | 3488, |
13818 | | /* CVT_W_D32_MM */ |
13819 | | 3490, |
13820 | | /* CVT_W_D64 */ |
13821 | | 3492, |
13822 | | /* CVT_W_D64_MM */ |
13823 | | 3494, |
13824 | | /* CVT_W_S */ |
13825 | | 3496, |
13826 | | /* CVT_W_S_MM */ |
13827 | | 3498, |
13828 | | /* CVT_W_S_MMR6 */ |
13829 | | 3500, |
13830 | | /* C_EQ_D32 */ |
13831 | | 3502, |
13832 | | /* C_EQ_D32_MM */ |
13833 | | 3505, |
13834 | | /* C_EQ_D64 */ |
13835 | | 3508, |
13836 | | /* C_EQ_D64_MM */ |
13837 | | 3511, |
13838 | | /* C_EQ_S */ |
13839 | | 3514, |
13840 | | /* C_EQ_S_MM */ |
13841 | | 3517, |
13842 | | /* C_F_D32 */ |
13843 | | 3520, |
13844 | | /* C_F_D32_MM */ |
13845 | | 3523, |
13846 | | /* C_F_D64 */ |
13847 | | 3526, |
13848 | | /* C_F_D64_MM */ |
13849 | | 3529, |
13850 | | /* C_F_S */ |
13851 | | 3532, |
13852 | | /* C_F_S_MM */ |
13853 | | 3535, |
13854 | | /* C_LE_D32 */ |
13855 | | 3538, |
13856 | | /* C_LE_D32_MM */ |
13857 | | 3541, |
13858 | | /* C_LE_D64 */ |
13859 | | 3544, |
13860 | | /* C_LE_D64_MM */ |
13861 | | 3547, |
13862 | | /* C_LE_S */ |
13863 | | 3550, |
13864 | | /* C_LE_S_MM */ |
13865 | | 3553, |
13866 | | /* C_LT_D32 */ |
13867 | | 3556, |
13868 | | /* C_LT_D32_MM */ |
13869 | | 3559, |
13870 | | /* C_LT_D64 */ |
13871 | | 3562, |
13872 | | /* C_LT_D64_MM */ |
13873 | | 3565, |
13874 | | /* C_LT_S */ |
13875 | | 3568, |
13876 | | /* C_LT_S_MM */ |
13877 | | 3571, |
13878 | | /* C_NGE_D32 */ |
13879 | | 3574, |
13880 | | /* C_NGE_D32_MM */ |
13881 | | 3577, |
13882 | | /* C_NGE_D64 */ |
13883 | | 3580, |
13884 | | /* C_NGE_D64_MM */ |
13885 | | 3583, |
13886 | | /* C_NGE_S */ |
13887 | | 3586, |
13888 | | /* C_NGE_S_MM */ |
13889 | | 3589, |
13890 | | /* C_NGLE_D32 */ |
13891 | | 3592, |
13892 | | /* C_NGLE_D32_MM */ |
13893 | | 3595, |
13894 | | /* C_NGLE_D64 */ |
13895 | | 3598, |
13896 | | /* C_NGLE_D64_MM */ |
13897 | | 3601, |
13898 | | /* C_NGLE_S */ |
13899 | | 3604, |
13900 | | /* C_NGLE_S_MM */ |
13901 | | 3607, |
13902 | | /* C_NGL_D32 */ |
13903 | | 3610, |
13904 | | /* C_NGL_D32_MM */ |
13905 | | 3613, |
13906 | | /* C_NGL_D64 */ |
13907 | | 3616, |
13908 | | /* C_NGL_D64_MM */ |
13909 | | 3619, |
13910 | | /* C_NGL_S */ |
13911 | | 3622, |
13912 | | /* C_NGL_S_MM */ |
13913 | | 3625, |
13914 | | /* C_NGT_D32 */ |
13915 | | 3628, |
13916 | | /* C_NGT_D32_MM */ |
13917 | | 3631, |
13918 | | /* C_NGT_D64 */ |
13919 | | 3634, |
13920 | | /* C_NGT_D64_MM */ |
13921 | | 3637, |
13922 | | /* C_NGT_S */ |
13923 | | 3640, |
13924 | | /* C_NGT_S_MM */ |
13925 | | 3643, |
13926 | | /* C_OLE_D32 */ |
13927 | | 3646, |
13928 | | /* C_OLE_D32_MM */ |
13929 | | 3649, |
13930 | | /* C_OLE_D64 */ |
13931 | | 3652, |
13932 | | /* C_OLE_D64_MM */ |
13933 | | 3655, |
13934 | | /* C_OLE_S */ |
13935 | | 3658, |
13936 | | /* C_OLE_S_MM */ |
13937 | | 3661, |
13938 | | /* C_OLT_D32 */ |
13939 | | 3664, |
13940 | | /* C_OLT_D32_MM */ |
13941 | | 3667, |
13942 | | /* C_OLT_D64 */ |
13943 | | 3670, |
13944 | | /* C_OLT_D64_MM */ |
13945 | | 3673, |
13946 | | /* C_OLT_S */ |
13947 | | 3676, |
13948 | | /* C_OLT_S_MM */ |
13949 | | 3679, |
13950 | | /* C_SEQ_D32 */ |
13951 | | 3682, |
13952 | | /* C_SEQ_D32_MM */ |
13953 | | 3685, |
13954 | | /* C_SEQ_D64 */ |
13955 | | 3688, |
13956 | | /* C_SEQ_D64_MM */ |
13957 | | 3691, |
13958 | | /* C_SEQ_S */ |
13959 | | 3694, |
13960 | | /* C_SEQ_S_MM */ |
13961 | | 3697, |
13962 | | /* C_SF_D32 */ |
13963 | | 3700, |
13964 | | /* C_SF_D32_MM */ |
13965 | | 3703, |
13966 | | /* C_SF_D64 */ |
13967 | | 3706, |
13968 | | /* C_SF_D64_MM */ |
13969 | | 3709, |
13970 | | /* C_SF_S */ |
13971 | | 3712, |
13972 | | /* C_SF_S_MM */ |
13973 | | 3715, |
13974 | | /* C_UEQ_D32 */ |
13975 | | 3718, |
13976 | | /* C_UEQ_D32_MM */ |
13977 | | 3721, |
13978 | | /* C_UEQ_D64 */ |
13979 | | 3724, |
13980 | | /* C_UEQ_D64_MM */ |
13981 | | 3727, |
13982 | | /* C_UEQ_S */ |
13983 | | 3730, |
13984 | | /* C_UEQ_S_MM */ |
13985 | | 3733, |
13986 | | /* C_ULE_D32 */ |
13987 | | 3736, |
13988 | | /* C_ULE_D32_MM */ |
13989 | | 3739, |
13990 | | /* C_ULE_D64 */ |
13991 | | 3742, |
13992 | | /* C_ULE_D64_MM */ |
13993 | | 3745, |
13994 | | /* C_ULE_S */ |
13995 | | 3748, |
13996 | | /* C_ULE_S_MM */ |
13997 | | 3751, |
13998 | | /* C_ULT_D32 */ |
13999 | | 3754, |
14000 | | /* C_ULT_D32_MM */ |
14001 | | 3757, |
14002 | | /* C_ULT_D64 */ |
14003 | | 3760, |
14004 | | /* C_ULT_D64_MM */ |
14005 | | 3763, |
14006 | | /* C_ULT_S */ |
14007 | | 3766, |
14008 | | /* C_ULT_S_MM */ |
14009 | | 3769, |
14010 | | /* C_UN_D32 */ |
14011 | | 3772, |
14012 | | /* C_UN_D32_MM */ |
14013 | | 3775, |
14014 | | /* C_UN_D64 */ |
14015 | | 3778, |
14016 | | /* C_UN_D64_MM */ |
14017 | | 3781, |
14018 | | /* C_UN_S */ |
14019 | | 3784, |
14020 | | /* C_UN_S_MM */ |
14021 | | 3787, |
14022 | | /* CmpRxRy16 */ |
14023 | | 3790, |
14024 | | /* CmpiRxImm16 */ |
14025 | | 3792, |
14026 | | /* CmpiRxImmX16 */ |
14027 | | 3794, |
14028 | | /* DADD */ |
14029 | | 3796, |
14030 | | /* DADDi */ |
14031 | | 3799, |
14032 | | /* DADDiu */ |
14033 | | 3802, |
14034 | | /* DADDu */ |
14035 | | 3805, |
14036 | | /* DAHI */ |
14037 | | 3808, |
14038 | | /* DALIGN */ |
14039 | | 3811, |
14040 | | /* DATI */ |
14041 | | 3815, |
14042 | | /* DAUI */ |
14043 | | 3818, |
14044 | | /* DBITSWAP */ |
14045 | | 3821, |
14046 | | /* DCLO */ |
14047 | | 3823, |
14048 | | /* DCLO_R6 */ |
14049 | | 3825, |
14050 | | /* DCLZ */ |
14051 | | 3827, |
14052 | | /* DCLZ_R6 */ |
14053 | | 3829, |
14054 | | /* DDIV */ |
14055 | | 3831, |
14056 | | /* DDIVU */ |
14057 | | 3834, |
14058 | | /* DERET */ |
14059 | | 3837, |
14060 | | /* DERET_MM */ |
14061 | | 3837, |
14062 | | /* DERET_MMR6 */ |
14063 | | 3837, |
14064 | | /* DEXT */ |
14065 | | 3837, |
14066 | | /* DEXT64_32 */ |
14067 | | 3841, |
14068 | | /* DEXTM */ |
14069 | | 3845, |
14070 | | /* DEXTU */ |
14071 | | 3849, |
14072 | | /* DI */ |
14073 | | 3853, |
14074 | | /* DINS */ |
14075 | | 3854, |
14076 | | /* DINSM */ |
14077 | | 3859, |
14078 | | /* DINSU */ |
14079 | | 3864, |
14080 | | /* DIV */ |
14081 | | 3869, |
14082 | | /* DIVU */ |
14083 | | 3872, |
14084 | | /* DIVU_MMR6 */ |
14085 | | 3875, |
14086 | | /* DIV_MMR6 */ |
14087 | | 3878, |
14088 | | /* DIV_S_B */ |
14089 | | 3881, |
14090 | | /* DIV_S_D */ |
14091 | | 3884, |
14092 | | /* DIV_S_H */ |
14093 | | 3887, |
14094 | | /* DIV_S_W */ |
14095 | | 3890, |
14096 | | /* DIV_U_B */ |
14097 | | 3893, |
14098 | | /* DIV_U_D */ |
14099 | | 3896, |
14100 | | /* DIV_U_H */ |
14101 | | 3899, |
14102 | | /* DIV_U_W */ |
14103 | | 3902, |
14104 | | /* DI_MM */ |
14105 | | 3905, |
14106 | | /* DI_MMR6 */ |
14107 | | 3906, |
14108 | | /* DLSA */ |
14109 | | 3907, |
14110 | | /* DLSA_R6 */ |
14111 | | 3911, |
14112 | | /* DMFC0 */ |
14113 | | 3915, |
14114 | | /* DMFC1 */ |
14115 | | 3918, |
14116 | | /* DMFC2 */ |
14117 | | 3920, |
14118 | | /* DMFC2_OCTEON */ |
14119 | | 3923, |
14120 | | /* DMFGC0 */ |
14121 | | 3925, |
14122 | | /* DMOD */ |
14123 | | 3928, |
14124 | | /* DMODU */ |
14125 | | 3931, |
14126 | | /* DMT */ |
14127 | | 3934, |
14128 | | /* DMTC0 */ |
14129 | | 3935, |
14130 | | /* DMTC1 */ |
14131 | | 3938, |
14132 | | /* DMTC2 */ |
14133 | | 3940, |
14134 | | /* DMTC2_OCTEON */ |
14135 | | 3943, |
14136 | | /* DMTGC0 */ |
14137 | | 3945, |
14138 | | /* DMUH */ |
14139 | | 3948, |
14140 | | /* DMUHU */ |
14141 | | 3951, |
14142 | | /* DMUL */ |
14143 | | 3954, |
14144 | | /* DMULT */ |
14145 | | 3957, |
14146 | | /* DMULTu */ |
14147 | | 3959, |
14148 | | /* DMULU */ |
14149 | | 3961, |
14150 | | /* DMUL_R6 */ |
14151 | | 3964, |
14152 | | /* DOTP_S_D */ |
14153 | | 3967, |
14154 | | /* DOTP_S_H */ |
14155 | | 3970, |
14156 | | /* DOTP_S_W */ |
14157 | | 3973, |
14158 | | /* DOTP_U_D */ |
14159 | | 3976, |
14160 | | /* DOTP_U_H */ |
14161 | | 3979, |
14162 | | /* DOTP_U_W */ |
14163 | | 3982, |
14164 | | /* DPADD_S_D */ |
14165 | | 3985, |
14166 | | /* DPADD_S_H */ |
14167 | | 3989, |
14168 | | /* DPADD_S_W */ |
14169 | | 3993, |
14170 | | /* DPADD_U_D */ |
14171 | | 3997, |
14172 | | /* DPADD_U_H */ |
14173 | | 4001, |
14174 | | /* DPADD_U_W */ |
14175 | | 4005, |
14176 | | /* DPAQX_SA_W_PH */ |
14177 | | 4009, |
14178 | | /* DPAQX_SA_W_PH_MMR2 */ |
14179 | | 4013, |
14180 | | /* DPAQX_S_W_PH */ |
14181 | | 4017, |
14182 | | /* DPAQX_S_W_PH_MMR2 */ |
14183 | | 4021, |
14184 | | /* DPAQ_SA_L_W */ |
14185 | | 4025, |
14186 | | /* DPAQ_SA_L_W_MM */ |
14187 | | 4029, |
14188 | | /* DPAQ_S_W_PH */ |
14189 | | 4033, |
14190 | | /* DPAQ_S_W_PH_MM */ |
14191 | | 4037, |
14192 | | /* DPAU_H_QBL */ |
14193 | | 4041, |
14194 | | /* DPAU_H_QBL_MM */ |
14195 | | 4045, |
14196 | | /* DPAU_H_QBR */ |
14197 | | 4049, |
14198 | | /* DPAU_H_QBR_MM */ |
14199 | | 4053, |
14200 | | /* DPAX_W_PH */ |
14201 | | 4057, |
14202 | | /* DPAX_W_PH_MMR2 */ |
14203 | | 4061, |
14204 | | /* DPA_W_PH */ |
14205 | | 4065, |
14206 | | /* DPA_W_PH_MMR2 */ |
14207 | | 4069, |
14208 | | /* DPOP */ |
14209 | | 4073, |
14210 | | /* DPSQX_SA_W_PH */ |
14211 | | 4075, |
14212 | | /* DPSQX_SA_W_PH_MMR2 */ |
14213 | | 4079, |
14214 | | /* DPSQX_S_W_PH */ |
14215 | | 4083, |
14216 | | /* DPSQX_S_W_PH_MMR2 */ |
14217 | | 4087, |
14218 | | /* DPSQ_SA_L_W */ |
14219 | | 4091, |
14220 | | /* DPSQ_SA_L_W_MM */ |
14221 | | 4095, |
14222 | | /* DPSQ_S_W_PH */ |
14223 | | 4099, |
14224 | | /* DPSQ_S_W_PH_MM */ |
14225 | | 4103, |
14226 | | /* DPSUB_S_D */ |
14227 | | 4107, |
14228 | | /* DPSUB_S_H */ |
14229 | | 4111, |
14230 | | /* DPSUB_S_W */ |
14231 | | 4115, |
14232 | | /* DPSUB_U_D */ |
14233 | | 4119, |
14234 | | /* DPSUB_U_H */ |
14235 | | 4123, |
14236 | | /* DPSUB_U_W */ |
14237 | | 4127, |
14238 | | /* DPSU_H_QBL */ |
14239 | | 4131, |
14240 | | /* DPSU_H_QBL_MM */ |
14241 | | 4135, |
14242 | | /* DPSU_H_QBR */ |
14243 | | 4139, |
14244 | | /* DPSU_H_QBR_MM */ |
14245 | | 4143, |
14246 | | /* DPSX_W_PH */ |
14247 | | 4147, |
14248 | | /* DPSX_W_PH_MMR2 */ |
14249 | | 4151, |
14250 | | /* DPS_W_PH */ |
14251 | | 4155, |
14252 | | /* DPS_W_PH_MMR2 */ |
14253 | | 4159, |
14254 | | /* DROTR */ |
14255 | | 4163, |
14256 | | /* DROTR32 */ |
14257 | | 4166, |
14258 | | /* DROTRV */ |
14259 | | 4169, |
14260 | | /* DSBH */ |
14261 | | 4172, |
14262 | | /* DSDIV */ |
14263 | | 4174, |
14264 | | /* DSHD */ |
14265 | | 4176, |
14266 | | /* DSLL */ |
14267 | | 4178, |
14268 | | /* DSLL32 */ |
14269 | | 4181, |
14270 | | /* DSLL64_32 */ |
14271 | | 4184, |
14272 | | /* DSLLV */ |
14273 | | 4186, |
14274 | | /* DSRA */ |
14275 | | 4189, |
14276 | | /* DSRA32 */ |
14277 | | 4192, |
14278 | | /* DSRAV */ |
14279 | | 4195, |
14280 | | /* DSRL */ |
14281 | | 4198, |
14282 | | /* DSRL32 */ |
14283 | | 4201, |
14284 | | /* DSRLV */ |
14285 | | 4204, |
14286 | | /* DSUB */ |
14287 | | 4207, |
14288 | | /* DSUBu */ |
14289 | | 4210, |
14290 | | /* DUDIV */ |
14291 | | 4213, |
14292 | | /* DVP */ |
14293 | | 4215, |
14294 | | /* DVPE */ |
14295 | | 4216, |
14296 | | /* DVP_MMR6 */ |
14297 | | 4217, |
14298 | | /* DivRxRy16 */ |
14299 | | 4218, |
14300 | | /* DivuRxRy16 */ |
14301 | | 4220, |
14302 | | /* EHB */ |
14303 | | 4222, |
14304 | | /* EHB_MM */ |
14305 | | 4222, |
14306 | | /* EHB_MMR6 */ |
14307 | | 4222, |
14308 | | /* EI */ |
14309 | | 4222, |
14310 | | /* EI_MM */ |
14311 | | 4223, |
14312 | | /* EI_MMR6 */ |
14313 | | 4224, |
14314 | | /* EMT */ |
14315 | | 4225, |
14316 | | /* ERET */ |
14317 | | 4226, |
14318 | | /* ERETNC */ |
14319 | | 4226, |
14320 | | /* ERETNC_MMR6 */ |
14321 | | 4226, |
14322 | | /* ERET_MM */ |
14323 | | 4226, |
14324 | | /* ERET_MMR6 */ |
14325 | | 4226, |
14326 | | /* EVP */ |
14327 | | 4226, |
14328 | | /* EVPE */ |
14329 | | 4227, |
14330 | | /* EVP_MMR6 */ |
14331 | | 4228, |
14332 | | /* EXT */ |
14333 | | 4229, |
14334 | | /* EXTP */ |
14335 | | 4233, |
14336 | | /* EXTPDP */ |
14337 | | 4236, |
14338 | | /* EXTPDPV */ |
14339 | | 4239, |
14340 | | /* EXTPDPV_MM */ |
14341 | | 4242, |
14342 | | /* EXTPDP_MM */ |
14343 | | 4245, |
14344 | | /* EXTPV */ |
14345 | | 4248, |
14346 | | /* EXTPV_MM */ |
14347 | | 4251, |
14348 | | /* EXTP_MM */ |
14349 | | 4254, |
14350 | | /* EXTRV_RS_W */ |
14351 | | 4257, |
14352 | | /* EXTRV_RS_W_MM */ |
14353 | | 4260, |
14354 | | /* EXTRV_R_W */ |
14355 | | 4263, |
14356 | | /* EXTRV_R_W_MM */ |
14357 | | 4266, |
14358 | | /* EXTRV_S_H */ |
14359 | | 4269, |
14360 | | /* EXTRV_S_H_MM */ |
14361 | | 4272, |
14362 | | /* EXTRV_W */ |
14363 | | 4275, |
14364 | | /* EXTRV_W_MM */ |
14365 | | 4278, |
14366 | | /* EXTR_RS_W */ |
14367 | | 4281, |
14368 | | /* EXTR_RS_W_MM */ |
14369 | | 4284, |
14370 | | /* EXTR_R_W */ |
14371 | | 4287, |
14372 | | /* EXTR_R_W_MM */ |
14373 | | 4290, |
14374 | | /* EXTR_S_H */ |
14375 | | 4293, |
14376 | | /* EXTR_S_H_MM */ |
14377 | | 4296, |
14378 | | /* EXTR_W */ |
14379 | | 4299, |
14380 | | /* EXTR_W_MM */ |
14381 | | 4302, |
14382 | | /* EXTS */ |
14383 | | 4305, |
14384 | | /* EXTS32 */ |
14385 | | 4309, |
14386 | | /* EXT_MM */ |
14387 | | 4313, |
14388 | | /* EXT_MMR6 */ |
14389 | | 4317, |
14390 | | /* FABS_D32 */ |
14391 | | 4321, |
14392 | | /* FABS_D32_MM */ |
14393 | | 4323, |
14394 | | /* FABS_D64 */ |
14395 | | 4325, |
14396 | | /* FABS_D64_MM */ |
14397 | | 4327, |
14398 | | /* FABS_S */ |
14399 | | 4329, |
14400 | | /* FABS_S_MM */ |
14401 | | 4331, |
14402 | | /* FADD_D */ |
14403 | | 4333, |
14404 | | /* FADD_D32 */ |
14405 | | 4336, |
14406 | | /* FADD_D32_MM */ |
14407 | | 4339, |
14408 | | /* FADD_D64 */ |
14409 | | 4342, |
14410 | | /* FADD_D64_MM */ |
14411 | | 4345, |
14412 | | /* FADD_PS64 */ |
14413 | | 4348, |
14414 | | /* FADD_S */ |
14415 | | 4351, |
14416 | | /* FADD_S_MM */ |
14417 | | 4354, |
14418 | | /* FADD_S_MMR6 */ |
14419 | | 4357, |
14420 | | /* FADD_W */ |
14421 | | 4360, |
14422 | | /* FCAF_D */ |
14423 | | 4363, |
14424 | | /* FCAF_W */ |
14425 | | 4366, |
14426 | | /* FCEQ_D */ |
14427 | | 4369, |
14428 | | /* FCEQ_W */ |
14429 | | 4372, |
14430 | | /* FCLASS_D */ |
14431 | | 4375, |
14432 | | /* FCLASS_W */ |
14433 | | 4377, |
14434 | | /* FCLE_D */ |
14435 | | 4379, |
14436 | | /* FCLE_W */ |
14437 | | 4382, |
14438 | | /* FCLT_D */ |
14439 | | 4385, |
14440 | | /* FCLT_W */ |
14441 | | 4388, |
14442 | | /* FCMP_D32 */ |
14443 | | 4391, |
14444 | | /* FCMP_D32_MM */ |
14445 | | 4394, |
14446 | | /* FCMP_D64 */ |
14447 | | 4397, |
14448 | | /* FCMP_S32 */ |
14449 | | 4400, |
14450 | | /* FCMP_S32_MM */ |
14451 | | 4403, |
14452 | | /* FCNE_D */ |
14453 | | 4406, |
14454 | | /* FCNE_W */ |
14455 | | 4409, |
14456 | | /* FCOR_D */ |
14457 | | 4412, |
14458 | | /* FCOR_W */ |
14459 | | 4415, |
14460 | | /* FCUEQ_D */ |
14461 | | 4418, |
14462 | | /* FCUEQ_W */ |
14463 | | 4421, |
14464 | | /* FCULE_D */ |
14465 | | 4424, |
14466 | | /* FCULE_W */ |
14467 | | 4427, |
14468 | | /* FCULT_D */ |
14469 | | 4430, |
14470 | | /* FCULT_W */ |
14471 | | 4433, |
14472 | | /* FCUNE_D */ |
14473 | | 4436, |
14474 | | /* FCUNE_W */ |
14475 | | 4439, |
14476 | | /* FCUN_D */ |
14477 | | 4442, |
14478 | | /* FCUN_W */ |
14479 | | 4445, |
14480 | | /* FDIV_D */ |
14481 | | 4448, |
14482 | | /* FDIV_D32 */ |
14483 | | 4451, |
14484 | | /* FDIV_D32_MM */ |
14485 | | 4454, |
14486 | | /* FDIV_D64 */ |
14487 | | 4457, |
14488 | | /* FDIV_D64_MM */ |
14489 | | 4460, |
14490 | | /* FDIV_S */ |
14491 | | 4463, |
14492 | | /* FDIV_S_MM */ |
14493 | | 4466, |
14494 | | /* FDIV_S_MMR6 */ |
14495 | | 4469, |
14496 | | /* FDIV_W */ |
14497 | | 4472, |
14498 | | /* FEXDO_H */ |
14499 | | 4475, |
14500 | | /* FEXDO_W */ |
14501 | | 4478, |
14502 | | /* FEXP2_D */ |
14503 | | 4481, |
14504 | | /* FEXP2_W */ |
14505 | | 4484, |
14506 | | /* FEXUPL_D */ |
14507 | | 4487, |
14508 | | /* FEXUPL_W */ |
14509 | | 4489, |
14510 | | /* FEXUPR_D */ |
14511 | | 4491, |
14512 | | /* FEXUPR_W */ |
14513 | | 4493, |
14514 | | /* FFINT_S_D */ |
14515 | | 4495, |
14516 | | /* FFINT_S_W */ |
14517 | | 4497, |
14518 | | /* FFINT_U_D */ |
14519 | | 4499, |
14520 | | /* FFINT_U_W */ |
14521 | | 4501, |
14522 | | /* FFQL_D */ |
14523 | | 4503, |
14524 | | /* FFQL_W */ |
14525 | | 4505, |
14526 | | /* FFQR_D */ |
14527 | | 4507, |
14528 | | /* FFQR_W */ |
14529 | | 4509, |
14530 | | /* FILL_B */ |
14531 | | 4511, |
14532 | | /* FILL_D */ |
14533 | | 4513, |
14534 | | /* FILL_H */ |
14535 | | 4515, |
14536 | | /* FILL_W */ |
14537 | | 4517, |
14538 | | /* FLOG2_D */ |
14539 | | 4519, |
14540 | | /* FLOG2_W */ |
14541 | | 4521, |
14542 | | /* FLOOR_L_D64 */ |
14543 | | 4523, |
14544 | | /* FLOOR_L_D_MMR6 */ |
14545 | | 4525, |
14546 | | /* FLOOR_L_S */ |
14547 | | 4527, |
14548 | | /* FLOOR_L_S_MMR6 */ |
14549 | | 4529, |
14550 | | /* FLOOR_W_D32 */ |
14551 | | 4531, |
14552 | | /* FLOOR_W_D64 */ |
14553 | | 4533, |
14554 | | /* FLOOR_W_D_MMR6 */ |
14555 | | 4535, |
14556 | | /* FLOOR_W_MM */ |
14557 | | 4537, |
14558 | | /* FLOOR_W_S */ |
14559 | | 4539, |
14560 | | /* FLOOR_W_S_MM */ |
14561 | | 4541, |
14562 | | /* FLOOR_W_S_MMR6 */ |
14563 | | 4543, |
14564 | | /* FMADD_D */ |
14565 | | 4545, |
14566 | | /* FMADD_W */ |
14567 | | 4549, |
14568 | | /* FMAX_A_D */ |
14569 | | 4553, |
14570 | | /* FMAX_A_W */ |
14571 | | 4556, |
14572 | | /* FMAX_D */ |
14573 | | 4559, |
14574 | | /* FMAX_W */ |
14575 | | 4562, |
14576 | | /* FMIN_A_D */ |
14577 | | 4565, |
14578 | | /* FMIN_A_W */ |
14579 | | 4568, |
14580 | | /* FMIN_D */ |
14581 | | 4571, |
14582 | | /* FMIN_W */ |
14583 | | 4574, |
14584 | | /* FMOV_D32 */ |
14585 | | 4577, |
14586 | | /* FMOV_D32_MM */ |
14587 | | 4579, |
14588 | | /* FMOV_D64 */ |
14589 | | 4581, |
14590 | | /* FMOV_D64_MM */ |
14591 | | 4583, |
14592 | | /* FMOV_D_MMR6 */ |
14593 | | 4585, |
14594 | | /* FMOV_S */ |
14595 | | 4587, |
14596 | | /* FMOV_S_MM */ |
14597 | | 4589, |
14598 | | /* FMOV_S_MMR6 */ |
14599 | | 4591, |
14600 | | /* FMSUB_D */ |
14601 | | 4593, |
14602 | | /* FMSUB_W */ |
14603 | | 4597, |
14604 | | /* FMUL_D */ |
14605 | | 4601, |
14606 | | /* FMUL_D32 */ |
14607 | | 4604, |
14608 | | /* FMUL_D32_MM */ |
14609 | | 4607, |
14610 | | /* FMUL_D64 */ |
14611 | | 4610, |
14612 | | /* FMUL_D64_MM */ |
14613 | | 4613, |
14614 | | /* FMUL_PS64 */ |
14615 | | 4616, |
14616 | | /* FMUL_S */ |
14617 | | 4619, |
14618 | | /* FMUL_S_MM */ |
14619 | | 4622, |
14620 | | /* FMUL_S_MMR6 */ |
14621 | | 4625, |
14622 | | /* FMUL_W */ |
14623 | | 4628, |
14624 | | /* FNEG_D32 */ |
14625 | | 4631, |
14626 | | /* FNEG_D32_MM */ |
14627 | | 4633, |
14628 | | /* FNEG_D64 */ |
14629 | | 4635, |
14630 | | /* FNEG_D64_MM */ |
14631 | | 4637, |
14632 | | /* FNEG_S */ |
14633 | | 4639, |
14634 | | /* FNEG_S_MM */ |
14635 | | 4641, |
14636 | | /* FNEG_S_MMR6 */ |
14637 | | 4643, |
14638 | | /* FORK */ |
14639 | | 4645, |
14640 | | /* FRCP_D */ |
14641 | | 4648, |
14642 | | /* FRCP_W */ |
14643 | | 4650, |
14644 | | /* FRINT_D */ |
14645 | | 4652, |
14646 | | /* FRINT_W */ |
14647 | | 4654, |
14648 | | /* FRSQRT_D */ |
14649 | | 4656, |
14650 | | /* FRSQRT_W */ |
14651 | | 4658, |
14652 | | /* FSAF_D */ |
14653 | | 4660, |
14654 | | /* FSAF_W */ |
14655 | | 4663, |
14656 | | /* FSEQ_D */ |
14657 | | 4666, |
14658 | | /* FSEQ_W */ |
14659 | | 4669, |
14660 | | /* FSLE_D */ |
14661 | | 4672, |
14662 | | /* FSLE_W */ |
14663 | | 4675, |
14664 | | /* FSLT_D */ |
14665 | | 4678, |
14666 | | /* FSLT_W */ |
14667 | | 4681, |
14668 | | /* FSNE_D */ |
14669 | | 4684, |
14670 | | /* FSNE_W */ |
14671 | | 4687, |
14672 | | /* FSOR_D */ |
14673 | | 4690, |
14674 | | /* FSOR_W */ |
14675 | | 4693, |
14676 | | /* FSQRT_D */ |
14677 | | 4696, |
14678 | | /* FSQRT_D32 */ |
14679 | | 4698, |
14680 | | /* FSQRT_D32_MM */ |
14681 | | 4700, |
14682 | | /* FSQRT_D64 */ |
14683 | | 4702, |
14684 | | /* FSQRT_D64_MM */ |
14685 | | 4704, |
14686 | | /* FSQRT_S */ |
14687 | | 4706, |
14688 | | /* FSQRT_S_MM */ |
14689 | | 4708, |
14690 | | /* FSQRT_W */ |
14691 | | 4710, |
14692 | | /* FSUB_D */ |
14693 | | 4712, |
14694 | | /* FSUB_D32 */ |
14695 | | 4715, |
14696 | | /* FSUB_D32_MM */ |
14697 | | 4718, |
14698 | | /* FSUB_D64 */ |
14699 | | 4721, |
14700 | | /* FSUB_D64_MM */ |
14701 | | 4724, |
14702 | | /* FSUB_PS64 */ |
14703 | | 4727, |
14704 | | /* FSUB_S */ |
14705 | | 4730, |
14706 | | /* FSUB_S_MM */ |
14707 | | 4733, |
14708 | | /* FSUB_S_MMR6 */ |
14709 | | 4736, |
14710 | | /* FSUB_W */ |
14711 | | 4739, |
14712 | | /* FSUEQ_D */ |
14713 | | 4742, |
14714 | | /* FSUEQ_W */ |
14715 | | 4745, |
14716 | | /* FSULE_D */ |
14717 | | 4748, |
14718 | | /* FSULE_W */ |
14719 | | 4751, |
14720 | | /* FSULT_D */ |
14721 | | 4754, |
14722 | | /* FSULT_W */ |
14723 | | 4757, |
14724 | | /* FSUNE_D */ |
14725 | | 4760, |
14726 | | /* FSUNE_W */ |
14727 | | 4763, |
14728 | | /* FSUN_D */ |
14729 | | 4766, |
14730 | | /* FSUN_W */ |
14731 | | 4769, |
14732 | | /* FTINT_S_D */ |
14733 | | 4772, |
14734 | | /* FTINT_S_W */ |
14735 | | 4774, |
14736 | | /* FTINT_U_D */ |
14737 | | 4776, |
14738 | | /* FTINT_U_W */ |
14739 | | 4778, |
14740 | | /* FTQ_H */ |
14741 | | 4780, |
14742 | | /* FTQ_W */ |
14743 | | 4783, |
14744 | | /* FTRUNC_S_D */ |
14745 | | 4786, |
14746 | | /* FTRUNC_S_W */ |
14747 | | 4788, |
14748 | | /* FTRUNC_U_D */ |
14749 | | 4790, |
14750 | | /* FTRUNC_U_W */ |
14751 | | 4792, |
14752 | | /* GINVI */ |
14753 | | 4794, |
14754 | | /* GINVI_MMR6 */ |
14755 | | 4795, |
14756 | | /* GINVT */ |
14757 | | 4796, |
14758 | | /* GINVT_MMR6 */ |
14759 | | 4798, |
14760 | | /* HADD_S_D */ |
14761 | | 4800, |
14762 | | /* HADD_S_H */ |
14763 | | 4803, |
14764 | | /* HADD_S_W */ |
14765 | | 4806, |
14766 | | /* HADD_U_D */ |
14767 | | 4809, |
14768 | | /* HADD_U_H */ |
14769 | | 4812, |
14770 | | /* HADD_U_W */ |
14771 | | 4815, |
14772 | | /* HSUB_S_D */ |
14773 | | 4818, |
14774 | | /* HSUB_S_H */ |
14775 | | 4821, |
14776 | | /* HSUB_S_W */ |
14777 | | 4824, |
14778 | | /* HSUB_U_D */ |
14779 | | 4827, |
14780 | | /* HSUB_U_H */ |
14781 | | 4830, |
14782 | | /* HSUB_U_W */ |
14783 | | 4833, |
14784 | | /* HYPCALL */ |
14785 | | 4836, |
14786 | | /* HYPCALL_MM */ |
14787 | | 4837, |
14788 | | /* ILVEV_B */ |
14789 | | 4838, |
14790 | | /* ILVEV_D */ |
14791 | | 4841, |
14792 | | /* ILVEV_H */ |
14793 | | 4844, |
14794 | | /* ILVEV_W */ |
14795 | | 4847, |
14796 | | /* ILVL_B */ |
14797 | | 4850, |
14798 | | /* ILVL_D */ |
14799 | | 4853, |
14800 | | /* ILVL_H */ |
14801 | | 4856, |
14802 | | /* ILVL_W */ |
14803 | | 4859, |
14804 | | /* ILVOD_B */ |
14805 | | 4862, |
14806 | | /* ILVOD_D */ |
14807 | | 4865, |
14808 | | /* ILVOD_H */ |
14809 | | 4868, |
14810 | | /* ILVOD_W */ |
14811 | | 4871, |
14812 | | /* ILVR_B */ |
14813 | | 4874, |
14814 | | /* ILVR_D */ |
14815 | | 4877, |
14816 | | /* ILVR_H */ |
14817 | | 4880, |
14818 | | /* ILVR_W */ |
14819 | | 4883, |
14820 | | /* INS */ |
14821 | | 4886, |
14822 | | /* INSERT_B */ |
14823 | | 4891, |
14824 | | /* INSERT_D */ |
14825 | | 4895, |
14826 | | /* INSERT_H */ |
14827 | | 4899, |
14828 | | /* INSERT_W */ |
14829 | | 4903, |
14830 | | /* INSV */ |
14831 | | 4907, |
14832 | | /* INSVE_B */ |
14833 | | 4910, |
14834 | | /* INSVE_D */ |
14835 | | 4915, |
14836 | | /* INSVE_H */ |
14837 | | 4920, |
14838 | | /* INSVE_W */ |
14839 | | 4925, |
14840 | | /* INSV_MM */ |
14841 | | 4930, |
14842 | | /* INS_MM */ |
14843 | | 4933, |
14844 | | /* INS_MMR6 */ |
14845 | | 4938, |
14846 | | /* J */ |
14847 | | 4943, |
14848 | | /* JAL */ |
14849 | | 4944, |
14850 | | /* JALR */ |
14851 | | 4945, |
14852 | | /* JALR16_MM */ |
14853 | | 4947, |
14854 | | /* JALR64 */ |
14855 | | 4948, |
14856 | | /* JALRC16_MMR6 */ |
14857 | | 4950, |
14858 | | /* JALRC_HB_MMR6 */ |
14859 | | 4951, |
14860 | | /* JALRC_MMR6 */ |
14861 | | 4953, |
14862 | | /* JALRS16_MM */ |
14863 | | 4955, |
14864 | | /* JALRS_MM */ |
14865 | | 4956, |
14866 | | /* JALR_HB */ |
14867 | | 4958, |
14868 | | /* JALR_HB64 */ |
14869 | | 4960, |
14870 | | /* JALR_MM */ |
14871 | | 4962, |
14872 | | /* JALS_MM */ |
14873 | | 4964, |
14874 | | /* JALX */ |
14875 | | 4965, |
14876 | | /* JALX_MM */ |
14877 | | 4966, |
14878 | | /* JAL_MM */ |
14879 | | 4967, |
14880 | | /* JIALC */ |
14881 | | 4968, |
14882 | | /* JIALC64 */ |
14883 | | 4970, |
14884 | | /* JIALC_MMR6 */ |
14885 | | 4972, |
14886 | | /* JIC */ |
14887 | | 4974, |
14888 | | /* JIC64 */ |
14889 | | 4976, |
14890 | | /* JIC_MMR6 */ |
14891 | | 4978, |
14892 | | /* JR */ |
14893 | | 4980, |
14894 | | /* JR16_MM */ |
14895 | | 4981, |
14896 | | /* JR64 */ |
14897 | | 4982, |
14898 | | /* JRADDIUSP */ |
14899 | | 4983, |
14900 | | /* JRC16_MM */ |
14901 | | 4984, |
14902 | | /* JRC16_MMR6 */ |
14903 | | 4985, |
14904 | | /* JRCADDIUSP_MMR6 */ |
14905 | | 4986, |
14906 | | /* JR_HB */ |
14907 | | 4987, |
14908 | | /* JR_HB64 */ |
14909 | | 4988, |
14910 | | /* JR_HB64_R6 */ |
14911 | | 4989, |
14912 | | /* JR_HB_R6 */ |
14913 | | 4990, |
14914 | | /* JR_MM */ |
14915 | | 4991, |
14916 | | /* J_MM */ |
14917 | | 4992, |
14918 | | /* Jal16 */ |
14919 | | 4993, |
14920 | | /* JalB16 */ |
14921 | | 4994, |
14922 | | /* JrRa16 */ |
14923 | | 4995, |
14924 | | /* JrcRa16 */ |
14925 | | 4995, |
14926 | | /* JrcRx16 */ |
14927 | | 4995, |
14928 | | /* JumpLinkReg16 */ |
14929 | | 4996, |
14930 | | /* LB */ |
14931 | | 4997, |
14932 | | /* LB64 */ |
14933 | | 5000, |
14934 | | /* LBE */ |
14935 | | 5003, |
14936 | | /* LBE_MM */ |
14937 | | 5006, |
14938 | | /* LBU16_MM */ |
14939 | | 5009, |
14940 | | /* LBUX */ |
14941 | | 5012, |
14942 | | /* LBUX_MM */ |
14943 | | 5015, |
14944 | | /* LBU_MMR6 */ |
14945 | | 5018, |
14946 | | /* LB_MM */ |
14947 | | 5021, |
14948 | | /* LB_MMR6 */ |
14949 | | 5024, |
14950 | | /* LBu */ |
14951 | | 5027, |
14952 | | /* LBu64 */ |
14953 | | 5030, |
14954 | | /* LBuE */ |
14955 | | 5033, |
14956 | | /* LBuE_MM */ |
14957 | | 5036, |
14958 | | /* LBu_MM */ |
14959 | | 5039, |
14960 | | /* LD */ |
14961 | | 5042, |
14962 | | /* LDC1 */ |
14963 | | 5045, |
14964 | | /* LDC164 */ |
14965 | | 5048, |
14966 | | /* LDC1_D64_MMR6 */ |
14967 | | 5051, |
14968 | | /* LDC1_MM_D32 */ |
14969 | | 5054, |
14970 | | /* LDC1_MM_D64 */ |
14971 | | 5057, |
14972 | | /* LDC2 */ |
14973 | | 5060, |
14974 | | /* LDC2_MMR6 */ |
14975 | | 5063, |
14976 | | /* LDC2_R6 */ |
14977 | | 5066, |
14978 | | /* LDC3 */ |
14979 | | 5069, |
14980 | | /* LDI_B */ |
14981 | | 5072, |
14982 | | /* LDI_D */ |
14983 | | 5074, |
14984 | | /* LDI_H */ |
14985 | | 5076, |
14986 | | /* LDI_W */ |
14987 | | 5078, |
14988 | | /* LDL */ |
14989 | | 5080, |
14990 | | /* LDPC */ |
14991 | | 5084, |
14992 | | /* LDR */ |
14993 | | 5086, |
14994 | | /* LDXC1 */ |
14995 | | 5090, |
14996 | | /* LDXC164 */ |
14997 | | 5093, |
14998 | | /* LD_B */ |
14999 | | 5096, |
15000 | | /* LD_D */ |
15001 | | 5099, |
15002 | | /* LD_H */ |
15003 | | 5102, |
15004 | | /* LD_W */ |
15005 | | 5105, |
15006 | | /* LEA_ADDiu */ |
15007 | | 5108, |
15008 | | /* LEA_ADDiu64 */ |
15009 | | 5111, |
15010 | | /* LEA_ADDiu_MM */ |
15011 | | 5114, |
15012 | | /* LH */ |
15013 | | 5117, |
15014 | | /* LH64 */ |
15015 | | 5120, |
15016 | | /* LHE */ |
15017 | | 5123, |
15018 | | /* LHE_MM */ |
15019 | | 5126, |
15020 | | /* LHU16_MM */ |
15021 | | 5129, |
15022 | | /* LHX */ |
15023 | | 5132, |
15024 | | /* LHX_MM */ |
15025 | | 5135, |
15026 | | /* LH_MM */ |
15027 | | 5138, |
15028 | | /* LHu */ |
15029 | | 5141, |
15030 | | /* LHu64 */ |
15031 | | 5144, |
15032 | | /* LHuE */ |
15033 | | 5147, |
15034 | | /* LHuE_MM */ |
15035 | | 5150, |
15036 | | /* LHu_MM */ |
15037 | | 5153, |
15038 | | /* LI16_MM */ |
15039 | | 5156, |
15040 | | /* LI16_MMR6 */ |
15041 | | 5158, |
15042 | | /* LL */ |
15043 | | 5160, |
15044 | | /* LL64 */ |
15045 | | 5163, |
15046 | | /* LL64_R6 */ |
15047 | | 5166, |
15048 | | /* LLD */ |
15049 | | 5169, |
15050 | | /* LLD_R6 */ |
15051 | | 5172, |
15052 | | /* LLE */ |
15053 | | 5175, |
15054 | | /* LLE_MM */ |
15055 | | 5178, |
15056 | | /* LL_MM */ |
15057 | | 5181, |
15058 | | /* LL_MMR6 */ |
15059 | | 5184, |
15060 | | /* LL_R6 */ |
15061 | | 5187, |
15062 | | /* LSA */ |
15063 | | 5190, |
15064 | | /* LSA_MMR6 */ |
15065 | | 5194, |
15066 | | /* LSA_R6 */ |
15067 | | 5198, |
15068 | | /* LUI_MMR6 */ |
15069 | | 5202, |
15070 | | /* LUXC1 */ |
15071 | | 5204, |
15072 | | /* LUXC164 */ |
15073 | | 5207, |
15074 | | /* LUXC1_MM */ |
15075 | | 5210, |
15076 | | /* LUi */ |
15077 | | 5213, |
15078 | | /* LUi64 */ |
15079 | | 5215, |
15080 | | /* LUi_MM */ |
15081 | | 5217, |
15082 | | /* LW */ |
15083 | | 5219, |
15084 | | /* LW16_MM */ |
15085 | | 5222, |
15086 | | /* LW64 */ |
15087 | | 5225, |
15088 | | /* LWC1 */ |
15089 | | 5228, |
15090 | | /* LWC1_MM */ |
15091 | | 5231, |
15092 | | /* LWC2 */ |
15093 | | 5234, |
15094 | | /* LWC2_MMR6 */ |
15095 | | 5237, |
15096 | | /* LWC2_R6 */ |
15097 | | 5240, |
15098 | | /* LWC3 */ |
15099 | | 5243, |
15100 | | /* LWDSP */ |
15101 | | 5246, |
15102 | | /* LWDSP_MM */ |
15103 | | 5249, |
15104 | | /* LWE */ |
15105 | | 5252, |
15106 | | /* LWE_MM */ |
15107 | | 5255, |
15108 | | /* LWGP_MM */ |
15109 | | 5258, |
15110 | | /* LWL */ |
15111 | | 5261, |
15112 | | /* LWL64 */ |
15113 | | 5265, |
15114 | | /* LWLE */ |
15115 | | 5269, |
15116 | | /* LWLE_MM */ |
15117 | | 5273, |
15118 | | /* LWL_MM */ |
15119 | | 5277, |
15120 | | /* LWM16_MM */ |
15121 | | 5281, |
15122 | | /* LWM16_MMR6 */ |
15123 | | 5284, |
15124 | | /* LWM32_MM */ |
15125 | | 5287, |
15126 | | /* LWPC */ |
15127 | | 5290, |
15128 | | /* LWPC_MMR6 */ |
15129 | | 5292, |
15130 | | /* LWP_MM */ |
15131 | | 5294, |
15132 | | /* LWR */ |
15133 | | 5298, |
15134 | | /* LWR64 */ |
15135 | | 5302, |
15136 | | /* LWRE */ |
15137 | | 5306, |
15138 | | /* LWRE_MM */ |
15139 | | 5310, |
15140 | | /* LWR_MM */ |
15141 | | 5314, |
15142 | | /* LWSP_MM */ |
15143 | | 5318, |
15144 | | /* LWUPC */ |
15145 | | 5321, |
15146 | | /* LWU_MM */ |
15147 | | 5323, |
15148 | | /* LWX */ |
15149 | | 5326, |
15150 | | /* LWXC1 */ |
15151 | | 5329, |
15152 | | /* LWXC1_MM */ |
15153 | | 5332, |
15154 | | /* LWXS_MM */ |
15155 | | 5335, |
15156 | | /* LWX_MM */ |
15157 | | 5338, |
15158 | | /* LW_MM */ |
15159 | | 5341, |
15160 | | /* LW_MMR6 */ |
15161 | | 5344, |
15162 | | /* LWu */ |
15163 | | 5347, |
15164 | | /* LbRxRyOffMemX16 */ |
15165 | | 5350, |
15166 | | /* LbuRxRyOffMemX16 */ |
15167 | | 5353, |
15168 | | /* LhRxRyOffMemX16 */ |
15169 | | 5356, |
15170 | | /* LhuRxRyOffMemX16 */ |
15171 | | 5359, |
15172 | | /* LiRxImm16 */ |
15173 | | 5362, |
15174 | | /* LiRxImmAlignX16 */ |
15175 | | 5364, |
15176 | | /* LiRxImmX16 */ |
15177 | | 5366, |
15178 | | /* LwRxPcTcp16 */ |
15179 | | 5368, |
15180 | | /* LwRxPcTcpX16 */ |
15181 | | 5371, |
15182 | | /* LwRxRyOffMemX16 */ |
15183 | | 5374, |
15184 | | /* LwRxSpImmX16 */ |
15185 | | 5377, |
15186 | | /* MADD */ |
15187 | | 5380, |
15188 | | /* MADDF_D */ |
15189 | | 5382, |
15190 | | /* MADDF_D_MMR6 */ |
15191 | | 5386, |
15192 | | /* MADDF_S */ |
15193 | | 5390, |
15194 | | /* MADDF_S_MMR6 */ |
15195 | | 5394, |
15196 | | /* MADDR_Q_H */ |
15197 | | 5398, |
15198 | | /* MADDR_Q_W */ |
15199 | | 5402, |
15200 | | /* MADDU */ |
15201 | | 5406, |
15202 | | /* MADDU_DSP */ |
15203 | | 5408, |
15204 | | /* MADDU_DSP_MM */ |
15205 | | 5412, |
15206 | | /* MADDU_MM */ |
15207 | | 5416, |
15208 | | /* MADDV_B */ |
15209 | | 5418, |
15210 | | /* MADDV_D */ |
15211 | | 5422, |
15212 | | /* MADDV_H */ |
15213 | | 5426, |
15214 | | /* MADDV_W */ |
15215 | | 5430, |
15216 | | /* MADD_D32 */ |
15217 | | 5434, |
15218 | | /* MADD_D32_MM */ |
15219 | | 5438, |
15220 | | /* MADD_D64 */ |
15221 | | 5442, |
15222 | | /* MADD_DSP */ |
15223 | | 5446, |
15224 | | /* MADD_DSP_MM */ |
15225 | | 5450, |
15226 | | /* MADD_MM */ |
15227 | | 5454, |
15228 | | /* MADD_Q_H */ |
15229 | | 5456, |
15230 | | /* MADD_Q_W */ |
15231 | | 5460, |
15232 | | /* MADD_S */ |
15233 | | 5464, |
15234 | | /* MADD_S_MM */ |
15235 | | 5468, |
15236 | | /* MAQ_SA_W_PHL */ |
15237 | | 5472, |
15238 | | /* MAQ_SA_W_PHL_MM */ |
15239 | | 5476, |
15240 | | /* MAQ_SA_W_PHR */ |
15241 | | 5480, |
15242 | | /* MAQ_SA_W_PHR_MM */ |
15243 | | 5484, |
15244 | | /* MAQ_S_W_PHL */ |
15245 | | 5488, |
15246 | | /* MAQ_S_W_PHL_MM */ |
15247 | | 5492, |
15248 | | /* MAQ_S_W_PHR */ |
15249 | | 5496, |
15250 | | /* MAQ_S_W_PHR_MM */ |
15251 | | 5500, |
15252 | | /* MAXA_D */ |
15253 | | 5504, |
15254 | | /* MAXA_D_MMR6 */ |
15255 | | 5507, |
15256 | | /* MAXA_S */ |
15257 | | 5510, |
15258 | | /* MAXA_S_MMR6 */ |
15259 | | 5513, |
15260 | | /* MAXI_S_B */ |
15261 | | 5516, |
15262 | | /* MAXI_S_D */ |
15263 | | 5519, |
15264 | | /* MAXI_S_H */ |
15265 | | 5522, |
15266 | | /* MAXI_S_W */ |
15267 | | 5525, |
15268 | | /* MAXI_U_B */ |
15269 | | 5528, |
15270 | | /* MAXI_U_D */ |
15271 | | 5531, |
15272 | | /* MAXI_U_H */ |
15273 | | 5534, |
15274 | | /* MAXI_U_W */ |
15275 | | 5537, |
15276 | | /* MAX_A_B */ |
15277 | | 5540, |
15278 | | /* MAX_A_D */ |
15279 | | 5543, |
15280 | | /* MAX_A_H */ |
15281 | | 5546, |
15282 | | /* MAX_A_W */ |
15283 | | 5549, |
15284 | | /* MAX_D */ |
15285 | | 5552, |
15286 | | /* MAX_D_MMR6 */ |
15287 | | 5555, |
15288 | | /* MAX_S */ |
15289 | | 5558, |
15290 | | /* MAX_S_B */ |
15291 | | 5561, |
15292 | | /* MAX_S_D */ |
15293 | | 5564, |
15294 | | /* MAX_S_H */ |
15295 | | 5567, |
15296 | | /* MAX_S_MMR6 */ |
15297 | | 5570, |
15298 | | /* MAX_S_W */ |
15299 | | 5573, |
15300 | | /* MAX_U_B */ |
15301 | | 5576, |
15302 | | /* MAX_U_D */ |
15303 | | 5579, |
15304 | | /* MAX_U_H */ |
15305 | | 5582, |
15306 | | /* MAX_U_W */ |
15307 | | 5585, |
15308 | | /* MFC0 */ |
15309 | | 5588, |
15310 | | /* MFC0_MMR6 */ |
15311 | | 5591, |
15312 | | /* MFC1 */ |
15313 | | 5594, |
15314 | | /* MFC1_D64 */ |
15315 | | 5596, |
15316 | | /* MFC1_MM */ |
15317 | | 5598, |
15318 | | /* MFC1_MMR6 */ |
15319 | | 5600, |
15320 | | /* MFC2 */ |
15321 | | 5602, |
15322 | | /* MFC2_MMR6 */ |
15323 | | 5605, |
15324 | | /* MFGC0 */ |
15325 | | 5607, |
15326 | | /* MFGC0_MM */ |
15327 | | 5610, |
15328 | | /* MFHC0_MMR6 */ |
15329 | | 5613, |
15330 | | /* MFHC1_D32 */ |
15331 | | 5616, |
15332 | | /* MFHC1_D32_MM */ |
15333 | | 5618, |
15334 | | /* MFHC1_D64 */ |
15335 | | 5620, |
15336 | | /* MFHC1_D64_MM */ |
15337 | | 5622, |
15338 | | /* MFHC2_MMR6 */ |
15339 | | 5624, |
15340 | | /* MFHGC0 */ |
15341 | | 5626, |
15342 | | /* MFHGC0_MM */ |
15343 | | 5629, |
15344 | | /* MFHI */ |
15345 | | 5632, |
15346 | | /* MFHI16_MM */ |
15347 | | 5633, |
15348 | | /* MFHI64 */ |
15349 | | 5634, |
15350 | | /* MFHI_DSP */ |
15351 | | 5635, |
15352 | | /* MFHI_DSP_MM */ |
15353 | | 5637, |
15354 | | /* MFHI_MM */ |
15355 | | 5639, |
15356 | | /* MFLO */ |
15357 | | 5640, |
15358 | | /* MFLO16_MM */ |
15359 | | 5641, |
15360 | | /* MFLO64 */ |
15361 | | 5642, |
15362 | | /* MFLO_DSP */ |
15363 | | 5643, |
15364 | | /* MFLO_DSP_MM */ |
15365 | | 5645, |
15366 | | /* MFLO_MM */ |
15367 | | 5647, |
15368 | | /* MFTR */ |
15369 | | 5648, |
15370 | | /* MINA_D */ |
15371 | | 5653, |
15372 | | /* MINA_D_MMR6 */ |
15373 | | 5656, |
15374 | | /* MINA_S */ |
15375 | | 5659, |
15376 | | /* MINA_S_MMR6 */ |
15377 | | 5662, |
15378 | | /* MINI_S_B */ |
15379 | | 5665, |
15380 | | /* MINI_S_D */ |
15381 | | 5668, |
15382 | | /* MINI_S_H */ |
15383 | | 5671, |
15384 | | /* MINI_S_W */ |
15385 | | 5674, |
15386 | | /* MINI_U_B */ |
15387 | | 5677, |
15388 | | /* MINI_U_D */ |
15389 | | 5680, |
15390 | | /* MINI_U_H */ |
15391 | | 5683, |
15392 | | /* MINI_U_W */ |
15393 | | 5686, |
15394 | | /* MIN_A_B */ |
15395 | | 5689, |
15396 | | /* MIN_A_D */ |
15397 | | 5692, |
15398 | | /* MIN_A_H */ |
15399 | | 5695, |
15400 | | /* MIN_A_W */ |
15401 | | 5698, |
15402 | | /* MIN_D */ |
15403 | | 5701, |
15404 | | /* MIN_D_MMR6 */ |
15405 | | 5704, |
15406 | | /* MIN_S */ |
15407 | | 5707, |
15408 | | /* MIN_S_B */ |
15409 | | 5710, |
15410 | | /* MIN_S_D */ |
15411 | | 5713, |
15412 | | /* MIN_S_H */ |
15413 | | 5716, |
15414 | | /* MIN_S_MMR6 */ |
15415 | | 5719, |
15416 | | /* MIN_S_W */ |
15417 | | 5722, |
15418 | | /* MIN_U_B */ |
15419 | | 5725, |
15420 | | /* MIN_U_D */ |
15421 | | 5728, |
15422 | | /* MIN_U_H */ |
15423 | | 5731, |
15424 | | /* MIN_U_W */ |
15425 | | 5734, |
15426 | | /* MOD */ |
15427 | | 5737, |
15428 | | /* MODSUB */ |
15429 | | 5740, |
15430 | | /* MODSUB_MM */ |
15431 | | 5743, |
15432 | | /* MODU */ |
15433 | | 5746, |
15434 | | /* MODU_MMR6 */ |
15435 | | 5749, |
15436 | | /* MOD_MMR6 */ |
15437 | | 5752, |
15438 | | /* MOD_S_B */ |
15439 | | 5755, |
15440 | | /* MOD_S_D */ |
15441 | | 5758, |
15442 | | /* MOD_S_H */ |
15443 | | 5761, |
15444 | | /* MOD_S_W */ |
15445 | | 5764, |
15446 | | /* MOD_U_B */ |
15447 | | 5767, |
15448 | | /* MOD_U_D */ |
15449 | | 5770, |
15450 | | /* MOD_U_H */ |
15451 | | 5773, |
15452 | | /* MOD_U_W */ |
15453 | | 5776, |
15454 | | /* MOVE16_MM */ |
15455 | | 5779, |
15456 | | /* MOVE16_MMR6 */ |
15457 | | 5781, |
15458 | | /* MOVEP_MM */ |
15459 | | 5783, |
15460 | | /* MOVEP_MMR6 */ |
15461 | | 5787, |
15462 | | /* MOVE_V */ |
15463 | | 5791, |
15464 | | /* MOVF_D32 */ |
15465 | | 5793, |
15466 | | /* MOVF_D32_MM */ |
15467 | | 5797, |
15468 | | /* MOVF_D64 */ |
15469 | | 5801, |
15470 | | /* MOVF_I */ |
15471 | | 5805, |
15472 | | /* MOVF_I64 */ |
15473 | | 5809, |
15474 | | /* MOVF_I_MM */ |
15475 | | 5813, |
15476 | | /* MOVF_S */ |
15477 | | 5817, |
15478 | | /* MOVF_S_MM */ |
15479 | | 5821, |
15480 | | /* MOVN_I64_D64 */ |
15481 | | 5825, |
15482 | | /* MOVN_I64_I */ |
15483 | | 5829, |
15484 | | /* MOVN_I64_I64 */ |
15485 | | 5833, |
15486 | | /* MOVN_I64_S */ |
15487 | | 5837, |
15488 | | /* MOVN_I_D32 */ |
15489 | | 5841, |
15490 | | /* MOVN_I_D32_MM */ |
15491 | | 5845, |
15492 | | /* MOVN_I_D64 */ |
15493 | | 5849, |
15494 | | /* MOVN_I_I */ |
15495 | | 5853, |
15496 | | /* MOVN_I_I64 */ |
15497 | | 5857, |
15498 | | /* MOVN_I_MM */ |
15499 | | 5861, |
15500 | | /* MOVN_I_S */ |
15501 | | 5865, |
15502 | | /* MOVN_I_S_MM */ |
15503 | | 5869, |
15504 | | /* MOVT_D32 */ |
15505 | | 5873, |
15506 | | /* MOVT_D32_MM */ |
15507 | | 5877, |
15508 | | /* MOVT_D64 */ |
15509 | | 5881, |
15510 | | /* MOVT_I */ |
15511 | | 5885, |
15512 | | /* MOVT_I64 */ |
15513 | | 5889, |
15514 | | /* MOVT_I_MM */ |
15515 | | 5893, |
15516 | | /* MOVT_S */ |
15517 | | 5897, |
15518 | | /* MOVT_S_MM */ |
15519 | | 5901, |
15520 | | /* MOVZ_I64_D64 */ |
15521 | | 5905, |
15522 | | /* MOVZ_I64_I */ |
15523 | | 5909, |
15524 | | /* MOVZ_I64_I64 */ |
15525 | | 5913, |
15526 | | /* MOVZ_I64_S */ |
15527 | | 5917, |
15528 | | /* MOVZ_I_D32 */ |
15529 | | 5921, |
15530 | | /* MOVZ_I_D32_MM */ |
15531 | | 5925, |
15532 | | /* MOVZ_I_D64 */ |
15533 | | 5929, |
15534 | | /* MOVZ_I_I */ |
15535 | | 5933, |
15536 | | /* MOVZ_I_I64 */ |
15537 | | 5937, |
15538 | | /* MOVZ_I_MM */ |
15539 | | 5941, |
15540 | | /* MOVZ_I_S */ |
15541 | | 5945, |
15542 | | /* MOVZ_I_S_MM */ |
15543 | | 5949, |
15544 | | /* MSUB */ |
15545 | | 5953, |
15546 | | /* MSUBF_D */ |
15547 | | 5955, |
15548 | | /* MSUBF_D_MMR6 */ |
15549 | | 5959, |
15550 | | /* MSUBF_S */ |
15551 | | 5963, |
15552 | | /* MSUBF_S_MMR6 */ |
15553 | | 5967, |
15554 | | /* MSUBR_Q_H */ |
15555 | | 5971, |
15556 | | /* MSUBR_Q_W */ |
15557 | | 5975, |
15558 | | /* MSUBU */ |
15559 | | 5979, |
15560 | | /* MSUBU_DSP */ |
15561 | | 5981, |
15562 | | /* MSUBU_DSP_MM */ |
15563 | | 5985, |
15564 | | /* MSUBU_MM */ |
15565 | | 5989, |
15566 | | /* MSUBV_B */ |
15567 | | 5991, |
15568 | | /* MSUBV_D */ |
15569 | | 5995, |
15570 | | /* MSUBV_H */ |
15571 | | 5999, |
15572 | | /* MSUBV_W */ |
15573 | | 6003, |
15574 | | /* MSUB_D32 */ |
15575 | | 6007, |
15576 | | /* MSUB_D32_MM */ |
15577 | | 6011, |
15578 | | /* MSUB_D64 */ |
15579 | | 6015, |
15580 | | /* MSUB_DSP */ |
15581 | | 6019, |
15582 | | /* MSUB_DSP_MM */ |
15583 | | 6023, |
15584 | | /* MSUB_MM */ |
15585 | | 6027, |
15586 | | /* MSUB_Q_H */ |
15587 | | 6029, |
15588 | | /* MSUB_Q_W */ |
15589 | | 6033, |
15590 | | /* MSUB_S */ |
15591 | | 6037, |
15592 | | /* MSUB_S_MM */ |
15593 | | 6041, |
15594 | | /* MTC0 */ |
15595 | | 6045, |
15596 | | /* MTC0_MMR6 */ |
15597 | | 6048, |
15598 | | /* MTC1 */ |
15599 | | 6051, |
15600 | | /* MTC1_D64 */ |
15601 | | 6053, |
15602 | | /* MTC1_D64_MM */ |
15603 | | 6055, |
15604 | | /* MTC1_MM */ |
15605 | | 6057, |
15606 | | /* MTC1_MMR6 */ |
15607 | | 6059, |
15608 | | /* MTC2 */ |
15609 | | 6061, |
15610 | | /* MTC2_MMR6 */ |
15611 | | 6064, |
15612 | | /* MTGC0 */ |
15613 | | 6066, |
15614 | | /* MTGC0_MM */ |
15615 | | 6069, |
15616 | | /* MTHC0_MMR6 */ |
15617 | | 6072, |
15618 | | /* MTHC1_D32 */ |
15619 | | 6075, |
15620 | | /* MTHC1_D32_MM */ |
15621 | | 6078, |
15622 | | /* MTHC1_D64 */ |
15623 | | 6081, |
15624 | | /* MTHC1_D64_MM */ |
15625 | | 6084, |
15626 | | /* MTHC2_MMR6 */ |
15627 | | 6087, |
15628 | | /* MTHGC0 */ |
15629 | | 6089, |
15630 | | /* MTHGC0_MM */ |
15631 | | 6092, |
15632 | | /* MTHI */ |
15633 | | 6095, |
15634 | | /* MTHI64 */ |
15635 | | 6096, |
15636 | | /* MTHI_DSP */ |
15637 | | 6097, |
15638 | | /* MTHI_DSP_MM */ |
15639 | | 6099, |
15640 | | /* MTHI_MM */ |
15641 | | 6101, |
15642 | | /* MTHLIP */ |
15643 | | 6102, |
15644 | | /* MTHLIP_MM */ |
15645 | | 6105, |
15646 | | /* MTLO */ |
15647 | | 6108, |
15648 | | /* MTLO64 */ |
15649 | | 6109, |
15650 | | /* MTLO_DSP */ |
15651 | | 6110, |
15652 | | /* MTLO_DSP_MM */ |
15653 | | 6112, |
15654 | | /* MTLO_MM */ |
15655 | | 6114, |
15656 | | /* MTM0 */ |
15657 | | 6115, |
15658 | | /* MTM1 */ |
15659 | | 6116, |
15660 | | /* MTM2 */ |
15661 | | 6117, |
15662 | | /* MTP0 */ |
15663 | | 6118, |
15664 | | /* MTP1 */ |
15665 | | 6119, |
15666 | | /* MTP2 */ |
15667 | | 6120, |
15668 | | /* MTTR */ |
15669 | | 6121, |
15670 | | /* MUH */ |
15671 | | 6126, |
15672 | | /* MUHU */ |
15673 | | 6129, |
15674 | | /* MUHU_MMR6 */ |
15675 | | 6132, |
15676 | | /* MUH_MMR6 */ |
15677 | | 6135, |
15678 | | /* MUL */ |
15679 | | 6138, |
15680 | | /* MULEQ_S_W_PHL */ |
15681 | | 6141, |
15682 | | /* MULEQ_S_W_PHL_MM */ |
15683 | | 6144, |
15684 | | /* MULEQ_S_W_PHR */ |
15685 | | 6147, |
15686 | | /* MULEQ_S_W_PHR_MM */ |
15687 | | 6150, |
15688 | | /* MULEU_S_PH_QBL */ |
15689 | | 6153, |
15690 | | /* MULEU_S_PH_QBL_MM */ |
15691 | | 6156, |
15692 | | /* MULEU_S_PH_QBR */ |
15693 | | 6159, |
15694 | | /* MULEU_S_PH_QBR_MM */ |
15695 | | 6162, |
15696 | | /* MULQ_RS_PH */ |
15697 | | 6165, |
15698 | | /* MULQ_RS_PH_MM */ |
15699 | | 6168, |
15700 | | /* MULQ_RS_W */ |
15701 | | 6171, |
15702 | | /* MULQ_RS_W_MMR2 */ |
15703 | | 6174, |
15704 | | /* MULQ_S_PH */ |
15705 | | 6177, |
15706 | | /* MULQ_S_PH_MMR2 */ |
15707 | | 6180, |
15708 | | /* MULQ_S_W */ |
15709 | | 6183, |
15710 | | /* MULQ_S_W_MMR2 */ |
15711 | | 6186, |
15712 | | /* MULR_PS64 */ |
15713 | | 6189, |
15714 | | /* MULR_Q_H */ |
15715 | | 6192, |
15716 | | /* MULR_Q_W */ |
15717 | | 6195, |
15718 | | /* MULSAQ_S_W_PH */ |
15719 | | 6198, |
15720 | | /* MULSAQ_S_W_PH_MM */ |
15721 | | 6202, |
15722 | | /* MULSA_W_PH */ |
15723 | | 6206, |
15724 | | /* MULSA_W_PH_MMR2 */ |
15725 | | 6210, |
15726 | | /* MULT */ |
15727 | | 6214, |
15728 | | /* MULTU_DSP */ |
15729 | | 6216, |
15730 | | /* MULTU_DSP_MM */ |
15731 | | 6219, |
15732 | | /* MULT_DSP */ |
15733 | | 6222, |
15734 | | /* MULT_DSP_MM */ |
15735 | | 6225, |
15736 | | /* MULT_MM */ |
15737 | | 6228, |
15738 | | /* MULTu */ |
15739 | | 6230, |
15740 | | /* MULTu_MM */ |
15741 | | 6232, |
15742 | | /* MULU */ |
15743 | | 6234, |
15744 | | /* MULU_MMR6 */ |
15745 | | 6237, |
15746 | | /* MULV_B */ |
15747 | | 6240, |
15748 | | /* MULV_D */ |
15749 | | 6243, |
15750 | | /* MULV_H */ |
15751 | | 6246, |
15752 | | /* MULV_W */ |
15753 | | 6249, |
15754 | | /* MUL_MM */ |
15755 | | 6252, |
15756 | | /* MUL_MMR6 */ |
15757 | | 6255, |
15758 | | /* MUL_PH */ |
15759 | | 6258, |
15760 | | /* MUL_PH_MMR2 */ |
15761 | | 6261, |
15762 | | /* MUL_Q_H */ |
15763 | | 6264, |
15764 | | /* MUL_Q_W */ |
15765 | | 6267, |
15766 | | /* MUL_R6 */ |
15767 | | 6270, |
15768 | | /* MUL_S_PH */ |
15769 | | 6273, |
15770 | | /* MUL_S_PH_MMR2 */ |
15771 | | 6276, |
15772 | | /* Mfhi16 */ |
15773 | | 6279, |
15774 | | /* Mflo16 */ |
15775 | | 6280, |
15776 | | /* Move32R16 */ |
15777 | | 6281, |
15778 | | /* MoveR3216 */ |
15779 | | 6283, |
15780 | | /* NLOC_B */ |
15781 | | 6285, |
15782 | | /* NLOC_D */ |
15783 | | 6287, |
15784 | | /* NLOC_H */ |
15785 | | 6289, |
15786 | | /* NLOC_W */ |
15787 | | 6291, |
15788 | | /* NLZC_B */ |
15789 | | 6293, |
15790 | | /* NLZC_D */ |
15791 | | 6295, |
15792 | | /* NLZC_H */ |
15793 | | 6297, |
15794 | | /* NLZC_W */ |
15795 | | 6299, |
15796 | | /* NMADD_D32 */ |
15797 | | 6301, |
15798 | | /* NMADD_D32_MM */ |
15799 | | 6305, |
15800 | | /* NMADD_D64 */ |
15801 | | 6309, |
15802 | | /* NMADD_S */ |
15803 | | 6313, |
15804 | | /* NMADD_S_MM */ |
15805 | | 6317, |
15806 | | /* NMSUB_D32 */ |
15807 | | 6321, |
15808 | | /* NMSUB_D32_MM */ |
15809 | | 6325, |
15810 | | /* NMSUB_D64 */ |
15811 | | 6329, |
15812 | | /* NMSUB_S */ |
15813 | | 6333, |
15814 | | /* NMSUB_S_MM */ |
15815 | | 6337, |
15816 | | /* NOR */ |
15817 | | 6341, |
15818 | | /* NOR64 */ |
15819 | | 6344, |
15820 | | /* NORI_B */ |
15821 | | 6347, |
15822 | | /* NOR_MM */ |
15823 | | 6350, |
15824 | | /* NOR_MMR6 */ |
15825 | | 6353, |
15826 | | /* NOR_V */ |
15827 | | 6356, |
15828 | | /* NOT16_MM */ |
15829 | | 6359, |
15830 | | /* NOT16_MMR6 */ |
15831 | | 6361, |
15832 | | /* NegRxRy16 */ |
15833 | | 6363, |
15834 | | /* NotRxRy16 */ |
15835 | | 6365, |
15836 | | /* OR */ |
15837 | | 6367, |
15838 | | /* OR16_MM */ |
15839 | | 6370, |
15840 | | /* OR16_MMR6 */ |
15841 | | 6373, |
15842 | | /* OR64 */ |
15843 | | 6376, |
15844 | | /* ORI_B */ |
15845 | | 6379, |
15846 | | /* ORI_MMR6 */ |
15847 | | 6382, |
15848 | | /* OR_MM */ |
15849 | | 6385, |
15850 | | /* OR_MMR6 */ |
15851 | | 6388, |
15852 | | /* OR_V */ |
15853 | | 6391, |
15854 | | /* ORi */ |
15855 | | 6394, |
15856 | | /* ORi64 */ |
15857 | | 6397, |
15858 | | /* ORi_MM */ |
15859 | | 6400, |
15860 | | /* OrRxRxRy16 */ |
15861 | | 6403, |
15862 | | /* PACKRL_PH */ |
15863 | | 6406, |
15864 | | /* PACKRL_PH_MM */ |
15865 | | 6409, |
15866 | | /* PAUSE */ |
15867 | | 6412, |
15868 | | /* PAUSE_MM */ |
15869 | | 6412, |
15870 | | /* PAUSE_MMR6 */ |
15871 | | 6412, |
15872 | | /* PCKEV_B */ |
15873 | | 6412, |
15874 | | /* PCKEV_D */ |
15875 | | 6415, |
15876 | | /* PCKEV_H */ |
15877 | | 6418, |
15878 | | /* PCKEV_W */ |
15879 | | 6421, |
15880 | | /* PCKOD_B */ |
15881 | | 6424, |
15882 | | /* PCKOD_D */ |
15883 | | 6427, |
15884 | | /* PCKOD_H */ |
15885 | | 6430, |
15886 | | /* PCKOD_W */ |
15887 | | 6433, |
15888 | | /* PCNT_B */ |
15889 | | 6436, |
15890 | | /* PCNT_D */ |
15891 | | 6438, |
15892 | | /* PCNT_H */ |
15893 | | 6440, |
15894 | | /* PCNT_W */ |
15895 | | 6442, |
15896 | | /* PICK_PH */ |
15897 | | 6444, |
15898 | | /* PICK_PH_MM */ |
15899 | | 6447, |
15900 | | /* PICK_QB */ |
15901 | | 6450, |
15902 | | /* PICK_QB_MM */ |
15903 | | 6453, |
15904 | | /* PLL_PS64 */ |
15905 | | 6456, |
15906 | | /* PLU_PS64 */ |
15907 | | 6459, |
15908 | | /* POP */ |
15909 | | 6462, |
15910 | | /* PRECEQU_PH_QBL */ |
15911 | | 6464, |
15912 | | /* PRECEQU_PH_QBLA */ |
15913 | | 6466, |
15914 | | /* PRECEQU_PH_QBLA_MM */ |
15915 | | 6468, |
15916 | | /* PRECEQU_PH_QBL_MM */ |
15917 | | 6470, |
15918 | | /* PRECEQU_PH_QBR */ |
15919 | | 6472, |
15920 | | /* PRECEQU_PH_QBRA */ |
15921 | | 6474, |
15922 | | /* PRECEQU_PH_QBRA_MM */ |
15923 | | 6476, |
15924 | | /* PRECEQU_PH_QBR_MM */ |
15925 | | 6478, |
15926 | | /* PRECEQ_W_PHL */ |
15927 | | 6480, |
15928 | | /* PRECEQ_W_PHL_MM */ |
15929 | | 6482, |
15930 | | /* PRECEQ_W_PHR */ |
15931 | | 6484, |
15932 | | /* PRECEQ_W_PHR_MM */ |
15933 | | 6486, |
15934 | | /* PRECEU_PH_QBL */ |
15935 | | 6488, |
15936 | | /* PRECEU_PH_QBLA */ |
15937 | | 6490, |
15938 | | /* PRECEU_PH_QBLA_MM */ |
15939 | | 6492, |
15940 | | /* PRECEU_PH_QBL_MM */ |
15941 | | 6494, |
15942 | | /* PRECEU_PH_QBR */ |
15943 | | 6496, |
15944 | | /* PRECEU_PH_QBRA */ |
15945 | | 6498, |
15946 | | /* PRECEU_PH_QBRA_MM */ |
15947 | | 6500, |
15948 | | /* PRECEU_PH_QBR_MM */ |
15949 | | 6502, |
15950 | | /* PRECRQU_S_QB_PH */ |
15951 | | 6504, |
15952 | | /* PRECRQU_S_QB_PH_MM */ |
15953 | | 6507, |
15954 | | /* PRECRQ_PH_W */ |
15955 | | 6510, |
15956 | | /* PRECRQ_PH_W_MM */ |
15957 | | 6513, |
15958 | | /* PRECRQ_QB_PH */ |
15959 | | 6516, |
15960 | | /* PRECRQ_QB_PH_MM */ |
15961 | | 6519, |
15962 | | /* PRECRQ_RS_PH_W */ |
15963 | | 6522, |
15964 | | /* PRECRQ_RS_PH_W_MM */ |
15965 | | 6525, |
15966 | | /* PRECR_QB_PH */ |
15967 | | 6528, |
15968 | | /* PRECR_QB_PH_MMR2 */ |
15969 | | 6531, |
15970 | | /* PRECR_SRA_PH_W */ |
15971 | | 6534, |
15972 | | /* PRECR_SRA_PH_W_MMR2 */ |
15973 | | 6538, |
15974 | | /* PRECR_SRA_R_PH_W */ |
15975 | | 6542, |
15976 | | /* PRECR_SRA_R_PH_W_MMR2 */ |
15977 | | 6546, |
15978 | | /* PREF */ |
15979 | | 6550, |
15980 | | /* PREFE */ |
15981 | | 6553, |
15982 | | /* PREFE_MM */ |
15983 | | 6556, |
15984 | | /* PREFX_MM */ |
15985 | | 6559, |
15986 | | /* PREF_MM */ |
15987 | | 6562, |
15988 | | /* PREF_MMR6 */ |
15989 | | 6565, |
15990 | | /* PREF_R6 */ |
15991 | | 6568, |
15992 | | /* PREPEND */ |
15993 | | 6571, |
15994 | | /* PREPEND_MMR2 */ |
15995 | | 6575, |
15996 | | /* PUL_PS64 */ |
15997 | | 6579, |
15998 | | /* PUU_PS64 */ |
15999 | | 6582, |
16000 | | /* RADDU_W_QB */ |
16001 | | 6585, |
16002 | | /* RADDU_W_QB_MM */ |
16003 | | 6587, |
16004 | | /* RDDSP */ |
16005 | | 6589, |
16006 | | /* RDDSP_MM */ |
16007 | | 6591, |
16008 | | /* RDHWR */ |
16009 | | 6593, |
16010 | | /* RDHWR64 */ |
16011 | | 6596, |
16012 | | /* RDHWR_MM */ |
16013 | | 6599, |
16014 | | /* RDHWR_MMR6 */ |
16015 | | 6602, |
16016 | | /* RDPGPR_MMR6 */ |
16017 | | 6605, |
16018 | | /* RECIP_D32 */ |
16019 | | 6607, |
16020 | | /* RECIP_D32_MM */ |
16021 | | 6609, |
16022 | | /* RECIP_D64 */ |
16023 | | 6611, |
16024 | | /* RECIP_D64_MM */ |
16025 | | 6613, |
16026 | | /* RECIP_S */ |
16027 | | 6615, |
16028 | | /* RECIP_S_MM */ |
16029 | | 6617, |
16030 | | /* REPLV_PH */ |
16031 | | 6619, |
16032 | | /* REPLV_PH_MM */ |
16033 | | 6621, |
16034 | | /* REPLV_QB */ |
16035 | | 6623, |
16036 | | /* REPLV_QB_MM */ |
16037 | | 6625, |
16038 | | /* REPL_PH */ |
16039 | | 6627, |
16040 | | /* REPL_PH_MM */ |
16041 | | 6629, |
16042 | | /* REPL_QB */ |
16043 | | 6631, |
16044 | | /* REPL_QB_MM */ |
16045 | | 6633, |
16046 | | /* RINT_D */ |
16047 | | 6635, |
16048 | | /* RINT_D_MMR6 */ |
16049 | | 6637, |
16050 | | /* RINT_S */ |
16051 | | 6639, |
16052 | | /* RINT_S_MMR6 */ |
16053 | | 6641, |
16054 | | /* ROTR */ |
16055 | | 6643, |
16056 | | /* ROTRV */ |
16057 | | 6646, |
16058 | | /* ROTRV_MM */ |
16059 | | 6649, |
16060 | | /* ROTR_MM */ |
16061 | | 6652, |
16062 | | /* ROUND_L_D64 */ |
16063 | | 6655, |
16064 | | /* ROUND_L_D_MMR6 */ |
16065 | | 6657, |
16066 | | /* ROUND_L_S */ |
16067 | | 6659, |
16068 | | /* ROUND_L_S_MMR6 */ |
16069 | | 6661, |
16070 | | /* ROUND_W_D32 */ |
16071 | | 6663, |
16072 | | /* ROUND_W_D64 */ |
16073 | | 6665, |
16074 | | /* ROUND_W_D_MMR6 */ |
16075 | | 6667, |
16076 | | /* ROUND_W_MM */ |
16077 | | 6669, |
16078 | | /* ROUND_W_S */ |
16079 | | 6671, |
16080 | | /* ROUND_W_S_MM */ |
16081 | | 6673, |
16082 | | /* ROUND_W_S_MMR6 */ |
16083 | | 6675, |
16084 | | /* RSQRT_D32 */ |
16085 | | 6677, |
16086 | | /* RSQRT_D32_MM */ |
16087 | | 6679, |
16088 | | /* RSQRT_D64 */ |
16089 | | 6681, |
16090 | | /* RSQRT_D64_MM */ |
16091 | | 6683, |
16092 | | /* RSQRT_S */ |
16093 | | 6685, |
16094 | | /* RSQRT_S_MM */ |
16095 | | 6687, |
16096 | | /* Restore16 */ |
16097 | | 6689, |
16098 | | /* RestoreX16 */ |
16099 | | 6689, |
16100 | | /* SAA */ |
16101 | | 6689, |
16102 | | /* SAAD */ |
16103 | | 6691, |
16104 | | /* SAT_S_B */ |
16105 | | 6693, |
16106 | | /* SAT_S_D */ |
16107 | | 6696, |
16108 | | /* SAT_S_H */ |
16109 | | 6699, |
16110 | | /* SAT_S_W */ |
16111 | | 6702, |
16112 | | /* SAT_U_B */ |
16113 | | 6705, |
16114 | | /* SAT_U_D */ |
16115 | | 6708, |
16116 | | /* SAT_U_H */ |
16117 | | 6711, |
16118 | | /* SAT_U_W */ |
16119 | | 6714, |
16120 | | /* SB */ |
16121 | | 6717, |
16122 | | /* SB16_MM */ |
16123 | | 6720, |
16124 | | /* SB16_MMR6 */ |
16125 | | 6723, |
16126 | | /* SB64 */ |
16127 | | 6726, |
16128 | | /* SBE */ |
16129 | | 6729, |
16130 | | /* SBE_MM */ |
16131 | | 6732, |
16132 | | /* SB_MM */ |
16133 | | 6735, |
16134 | | /* SB_MMR6 */ |
16135 | | 6738, |
16136 | | /* SC */ |
16137 | | 6741, |
16138 | | /* SC64 */ |
16139 | | 6745, |
16140 | | /* SC64_R6 */ |
16141 | | 6749, |
16142 | | /* SCD */ |
16143 | | 6753, |
16144 | | /* SCD_R6 */ |
16145 | | 6757, |
16146 | | /* SCE */ |
16147 | | 6761, |
16148 | | /* SCE_MM */ |
16149 | | 6765, |
16150 | | /* SC_MM */ |
16151 | | 6769, |
16152 | | /* SC_MMR6 */ |
16153 | | 6773, |
16154 | | /* SC_R6 */ |
16155 | | 6777, |
16156 | | /* SD */ |
16157 | | 6781, |
16158 | | /* SDBBP */ |
16159 | | 6784, |
16160 | | /* SDBBP16_MM */ |
16161 | | 6785, |
16162 | | /* SDBBP16_MMR6 */ |
16163 | | 6786, |
16164 | | /* SDBBP_MM */ |
16165 | | 6787, |
16166 | | /* SDBBP_MMR6 */ |
16167 | | 6788, |
16168 | | /* SDBBP_R6 */ |
16169 | | 6789, |
16170 | | /* SDC1 */ |
16171 | | 6790, |
16172 | | /* SDC164 */ |
16173 | | 6793, |
16174 | | /* SDC1_D64_MMR6 */ |
16175 | | 6796, |
16176 | | /* SDC1_MM_D32 */ |
16177 | | 6799, |
16178 | | /* SDC1_MM_D64 */ |
16179 | | 6802, |
16180 | | /* SDC2 */ |
16181 | | 6805, |
16182 | | /* SDC2_MMR6 */ |
16183 | | 6808, |
16184 | | /* SDC2_R6 */ |
16185 | | 6811, |
16186 | | /* SDC3 */ |
16187 | | 6814, |
16188 | | /* SDIV */ |
16189 | | 6817, |
16190 | | /* SDIV_MM */ |
16191 | | 6819, |
16192 | | /* SDL */ |
16193 | | 6821, |
16194 | | /* SDR */ |
16195 | | 6824, |
16196 | | /* SDXC1 */ |
16197 | | 6827, |
16198 | | /* SDXC164 */ |
16199 | | 6830, |
16200 | | /* SEB */ |
16201 | | 6833, |
16202 | | /* SEB64 */ |
16203 | | 6835, |
16204 | | /* SEB_MM */ |
16205 | | 6837, |
16206 | | /* SEH */ |
16207 | | 6839, |
16208 | | /* SEH64 */ |
16209 | | 6841, |
16210 | | /* SEH_MM */ |
16211 | | 6843, |
16212 | | /* SELEQZ */ |
16213 | | 6845, |
16214 | | /* SELEQZ64 */ |
16215 | | 6848, |
16216 | | /* SELEQZ_D */ |
16217 | | 6851, |
16218 | | /* SELEQZ_D_MMR6 */ |
16219 | | 6854, |
16220 | | /* SELEQZ_MMR6 */ |
16221 | | 6857, |
16222 | | /* SELEQZ_S */ |
16223 | | 6860, |
16224 | | /* SELEQZ_S_MMR6 */ |
16225 | | 6863, |
16226 | | /* SELNEZ */ |
16227 | | 6866, |
16228 | | /* SELNEZ64 */ |
16229 | | 6869, |
16230 | | /* SELNEZ_D */ |
16231 | | 6872, |
16232 | | /* SELNEZ_D_MMR6 */ |
16233 | | 6875, |
16234 | | /* SELNEZ_MMR6 */ |
16235 | | 6878, |
16236 | | /* SELNEZ_S */ |
16237 | | 6881, |
16238 | | /* SELNEZ_S_MMR6 */ |
16239 | | 6884, |
16240 | | /* SEL_D */ |
16241 | | 6887, |
16242 | | /* SEL_D_MMR6 */ |
16243 | | 6891, |
16244 | | /* SEL_S */ |
16245 | | 6895, |
16246 | | /* SEL_S_MMR6 */ |
16247 | | 6899, |
16248 | | /* SEQ */ |
16249 | | 6903, |
16250 | | /* SEQi */ |
16251 | | 6906, |
16252 | | /* SH */ |
16253 | | 6909, |
16254 | | /* SH16_MM */ |
16255 | | 6912, |
16256 | | /* SH16_MMR6 */ |
16257 | | 6915, |
16258 | | /* SH64 */ |
16259 | | 6918, |
16260 | | /* SHE */ |
16261 | | 6921, |
16262 | | /* SHE_MM */ |
16263 | | 6924, |
16264 | | /* SHF_B */ |
16265 | | 6927, |
16266 | | /* SHF_H */ |
16267 | | 6930, |
16268 | | /* SHF_W */ |
16269 | | 6933, |
16270 | | /* SHILO */ |
16271 | | 6936, |
16272 | | /* SHILOV */ |
16273 | | 6939, |
16274 | | /* SHILOV_MM */ |
16275 | | 6942, |
16276 | | /* SHILO_MM */ |
16277 | | 6945, |
16278 | | /* SHLLV_PH */ |
16279 | | 6948, |
16280 | | /* SHLLV_PH_MM */ |
16281 | | 6951, |
16282 | | /* SHLLV_QB */ |
16283 | | 6954, |
16284 | | /* SHLLV_QB_MM */ |
16285 | | 6957, |
16286 | | /* SHLLV_S_PH */ |
16287 | | 6960, |
16288 | | /* SHLLV_S_PH_MM */ |
16289 | | 6963, |
16290 | | /* SHLLV_S_W */ |
16291 | | 6966, |
16292 | | /* SHLLV_S_W_MM */ |
16293 | | 6969, |
16294 | | /* SHLL_PH */ |
16295 | | 6972, |
16296 | | /* SHLL_PH_MM */ |
16297 | | 6975, |
16298 | | /* SHLL_QB */ |
16299 | | 6978, |
16300 | | /* SHLL_QB_MM */ |
16301 | | 6981, |
16302 | | /* SHLL_S_PH */ |
16303 | | 6984, |
16304 | | /* SHLL_S_PH_MM */ |
16305 | | 6987, |
16306 | | /* SHLL_S_W */ |
16307 | | 6990, |
16308 | | /* SHLL_S_W_MM */ |
16309 | | 6993, |
16310 | | /* SHRAV_PH */ |
16311 | | 6996, |
16312 | | /* SHRAV_PH_MM */ |
16313 | | 6999, |
16314 | | /* SHRAV_QB */ |
16315 | | 7002, |
16316 | | /* SHRAV_QB_MMR2 */ |
16317 | | 7005, |
16318 | | /* SHRAV_R_PH */ |
16319 | | 7008, |
16320 | | /* SHRAV_R_PH_MM */ |
16321 | | 7011, |
16322 | | /* SHRAV_R_QB */ |
16323 | | 7014, |
16324 | | /* SHRAV_R_QB_MMR2 */ |
16325 | | 7017, |
16326 | | /* SHRAV_R_W */ |
16327 | | 7020, |
16328 | | /* SHRAV_R_W_MM */ |
16329 | | 7023, |
16330 | | /* SHRA_PH */ |
16331 | | 7026, |
16332 | | /* SHRA_PH_MM */ |
16333 | | 7029, |
16334 | | /* SHRA_QB */ |
16335 | | 7032, |
16336 | | /* SHRA_QB_MMR2 */ |
16337 | | 7035, |
16338 | | /* SHRA_R_PH */ |
16339 | | 7038, |
16340 | | /* SHRA_R_PH_MM */ |
16341 | | 7041, |
16342 | | /* SHRA_R_QB */ |
16343 | | 7044, |
16344 | | /* SHRA_R_QB_MMR2 */ |
16345 | | 7047, |
16346 | | /* SHRA_R_W */ |
16347 | | 7050, |
16348 | | /* SHRA_R_W_MM */ |
16349 | | 7053, |
16350 | | /* SHRLV_PH */ |
16351 | | 7056, |
16352 | | /* SHRLV_PH_MMR2 */ |
16353 | | 7059, |
16354 | | /* SHRLV_QB */ |
16355 | | 7062, |
16356 | | /* SHRLV_QB_MM */ |
16357 | | 7065, |
16358 | | /* SHRL_PH */ |
16359 | | 7068, |
16360 | | /* SHRL_PH_MMR2 */ |
16361 | | 7071, |
16362 | | /* SHRL_QB */ |
16363 | | 7074, |
16364 | | /* SHRL_QB_MM */ |
16365 | | 7077, |
16366 | | /* SH_MM */ |
16367 | | 7080, |
16368 | | /* SH_MMR6 */ |
16369 | | 7083, |
16370 | | /* SIGRIE */ |
16371 | | 7086, |
16372 | | /* SIGRIE_MMR6 */ |
16373 | | 7087, |
16374 | | /* SLDI_B */ |
16375 | | 7088, |
16376 | | /* SLDI_D */ |
16377 | | 7092, |
16378 | | /* SLDI_H */ |
16379 | | 7096, |
16380 | | /* SLDI_W */ |
16381 | | 7100, |
16382 | | /* SLD_B */ |
16383 | | 7104, |
16384 | | /* SLD_D */ |
16385 | | 7108, |
16386 | | /* SLD_H */ |
16387 | | 7112, |
16388 | | /* SLD_W */ |
16389 | | 7116, |
16390 | | /* SLL */ |
16391 | | 7120, |
16392 | | /* SLL16_MM */ |
16393 | | 7123, |
16394 | | /* SLL16_MMR6 */ |
16395 | | 7126, |
16396 | | /* SLL64_32 */ |
16397 | | 7129, |
16398 | | /* SLL64_64 */ |
16399 | | 7131, |
16400 | | /* SLLI_B */ |
16401 | | 7133, |
16402 | | /* SLLI_D */ |
16403 | | 7136, |
16404 | | /* SLLI_H */ |
16405 | | 7139, |
16406 | | /* SLLI_W */ |
16407 | | 7142, |
16408 | | /* SLLV */ |
16409 | | 7145, |
16410 | | /* SLLV_MM */ |
16411 | | 7148, |
16412 | | /* SLL_B */ |
16413 | | 7151, |
16414 | | /* SLL_D */ |
16415 | | 7154, |
16416 | | /* SLL_H */ |
16417 | | 7157, |
16418 | | /* SLL_MM */ |
16419 | | 7160, |
16420 | | /* SLL_MMR6 */ |
16421 | | 7163, |
16422 | | /* SLL_W */ |
16423 | | 7166, |
16424 | | /* SLT */ |
16425 | | 7169, |
16426 | | /* SLT64 */ |
16427 | | 7172, |
16428 | | /* SLT_MM */ |
16429 | | 7175, |
16430 | | /* SLTi */ |
16431 | | 7178, |
16432 | | /* SLTi64 */ |
16433 | | 7181, |
16434 | | /* SLTi_MM */ |
16435 | | 7184, |
16436 | | /* SLTiu */ |
16437 | | 7187, |
16438 | | /* SLTiu64 */ |
16439 | | 7190, |
16440 | | /* SLTiu_MM */ |
16441 | | 7193, |
16442 | | /* SLTu */ |
16443 | | 7196, |
16444 | | /* SLTu64 */ |
16445 | | 7199, |
16446 | | /* SLTu_MM */ |
16447 | | 7202, |
16448 | | /* SNE */ |
16449 | | 7205, |
16450 | | /* SNEi */ |
16451 | | 7208, |
16452 | | /* SPLATI_B */ |
16453 | | 7211, |
16454 | | /* SPLATI_D */ |
16455 | | 7214, |
16456 | | /* SPLATI_H */ |
16457 | | 7217, |
16458 | | /* SPLATI_W */ |
16459 | | 7220, |
16460 | | /* SPLAT_B */ |
16461 | | 7223, |
16462 | | /* SPLAT_D */ |
16463 | | 7226, |
16464 | | /* SPLAT_H */ |
16465 | | 7229, |
16466 | | /* SPLAT_W */ |
16467 | | 7232, |
16468 | | /* SRA */ |
16469 | | 7235, |
16470 | | /* SRAI_B */ |
16471 | | 7238, |
16472 | | /* SRAI_D */ |
16473 | | 7241, |
16474 | | /* SRAI_H */ |
16475 | | 7244, |
16476 | | /* SRAI_W */ |
16477 | | 7247, |
16478 | | /* SRARI_B */ |
16479 | | 7250, |
16480 | | /* SRARI_D */ |
16481 | | 7253, |
16482 | | /* SRARI_H */ |
16483 | | 7256, |
16484 | | /* SRARI_W */ |
16485 | | 7259, |
16486 | | /* SRAR_B */ |
16487 | | 7262, |
16488 | | /* SRAR_D */ |
16489 | | 7265, |
16490 | | /* SRAR_H */ |
16491 | | 7268, |
16492 | | /* SRAR_W */ |
16493 | | 7271, |
16494 | | /* SRAV */ |
16495 | | 7274, |
16496 | | /* SRAV_MM */ |
16497 | | 7277, |
16498 | | /* SRA_B */ |
16499 | | 7280, |
16500 | | /* SRA_D */ |
16501 | | 7283, |
16502 | | /* SRA_H */ |
16503 | | 7286, |
16504 | | /* SRA_MM */ |
16505 | | 7289, |
16506 | | /* SRA_W */ |
16507 | | 7292, |
16508 | | /* SRL */ |
16509 | | 7295, |
16510 | | /* SRL16_MM */ |
16511 | | 7298, |
16512 | | /* SRL16_MMR6 */ |
16513 | | 7301, |
16514 | | /* SRLI_B */ |
16515 | | 7304, |
16516 | | /* SRLI_D */ |
16517 | | 7307, |
16518 | | /* SRLI_H */ |
16519 | | 7310, |
16520 | | /* SRLI_W */ |
16521 | | 7313, |
16522 | | /* SRLRI_B */ |
16523 | | 7316, |
16524 | | /* SRLRI_D */ |
16525 | | 7319, |
16526 | | /* SRLRI_H */ |
16527 | | 7322, |
16528 | | /* SRLRI_W */ |
16529 | | 7325, |
16530 | | /* SRLR_B */ |
16531 | | 7328, |
16532 | | /* SRLR_D */ |
16533 | | 7331, |
16534 | | /* SRLR_H */ |
16535 | | 7334, |
16536 | | /* SRLR_W */ |
16537 | | 7337, |
16538 | | /* SRLV */ |
16539 | | 7340, |
16540 | | /* SRLV_MM */ |
16541 | | 7343, |
16542 | | /* SRL_B */ |
16543 | | 7346, |
16544 | | /* SRL_D */ |
16545 | | 7349, |
16546 | | /* SRL_H */ |
16547 | | 7352, |
16548 | | /* SRL_MM */ |
16549 | | 7355, |
16550 | | /* SRL_W */ |
16551 | | 7358, |
16552 | | /* SSNOP */ |
16553 | | 7361, |
16554 | | /* SSNOP_MM */ |
16555 | | 7361, |
16556 | | /* SSNOP_MMR6 */ |
16557 | | 7361, |
16558 | | /* ST_B */ |
16559 | | 7361, |
16560 | | /* ST_D */ |
16561 | | 7364, |
16562 | | /* ST_H */ |
16563 | | 7367, |
16564 | | /* ST_W */ |
16565 | | 7370, |
16566 | | /* SUB */ |
16567 | | 7373, |
16568 | | /* SUBQH_PH */ |
16569 | | 7376, |
16570 | | /* SUBQH_PH_MMR2 */ |
16571 | | 7379, |
16572 | | /* SUBQH_R_PH */ |
16573 | | 7382, |
16574 | | /* SUBQH_R_PH_MMR2 */ |
16575 | | 7385, |
16576 | | /* SUBQH_R_W */ |
16577 | | 7388, |
16578 | | /* SUBQH_R_W_MMR2 */ |
16579 | | 7391, |
16580 | | /* SUBQH_W */ |
16581 | | 7394, |
16582 | | /* SUBQH_W_MMR2 */ |
16583 | | 7397, |
16584 | | /* SUBQ_PH */ |
16585 | | 7400, |
16586 | | /* SUBQ_PH_MM */ |
16587 | | 7403, |
16588 | | /* SUBQ_S_PH */ |
16589 | | 7406, |
16590 | | /* SUBQ_S_PH_MM */ |
16591 | | 7409, |
16592 | | /* SUBQ_S_W */ |
16593 | | 7412, |
16594 | | /* SUBQ_S_W_MM */ |
16595 | | 7415, |
16596 | | /* SUBSUS_U_B */ |
16597 | | 7418, |
16598 | | /* SUBSUS_U_D */ |
16599 | | 7421, |
16600 | | /* SUBSUS_U_H */ |
16601 | | 7424, |
16602 | | /* SUBSUS_U_W */ |
16603 | | 7427, |
16604 | | /* SUBSUU_S_B */ |
16605 | | 7430, |
16606 | | /* SUBSUU_S_D */ |
16607 | | 7433, |
16608 | | /* SUBSUU_S_H */ |
16609 | | 7436, |
16610 | | /* SUBSUU_S_W */ |
16611 | | 7439, |
16612 | | /* SUBS_S_B */ |
16613 | | 7442, |
16614 | | /* SUBS_S_D */ |
16615 | | 7445, |
16616 | | /* SUBS_S_H */ |
16617 | | 7448, |
16618 | | /* SUBS_S_W */ |
16619 | | 7451, |
16620 | | /* SUBS_U_B */ |
16621 | | 7454, |
16622 | | /* SUBS_U_D */ |
16623 | | 7457, |
16624 | | /* SUBS_U_H */ |
16625 | | 7460, |
16626 | | /* SUBS_U_W */ |
16627 | | 7463, |
16628 | | /* SUBU16_MM */ |
16629 | | 7466, |
16630 | | /* SUBU16_MMR6 */ |
16631 | | 7469, |
16632 | | /* SUBUH_QB */ |
16633 | | 7472, |
16634 | | /* SUBUH_QB_MMR2 */ |
16635 | | 7475, |
16636 | | /* SUBUH_R_QB */ |
16637 | | 7478, |
16638 | | /* SUBUH_R_QB_MMR2 */ |
16639 | | 7481, |
16640 | | /* SUBU_MMR6 */ |
16641 | | 7484, |
16642 | | /* SUBU_PH */ |
16643 | | 7487, |
16644 | | /* SUBU_PH_MMR2 */ |
16645 | | 7490, |
16646 | | /* SUBU_QB */ |
16647 | | 7493, |
16648 | | /* SUBU_QB_MM */ |
16649 | | 7496, |
16650 | | /* SUBU_S_PH */ |
16651 | | 7499, |
16652 | | /* SUBU_S_PH_MMR2 */ |
16653 | | 7502, |
16654 | | /* SUBU_S_QB */ |
16655 | | 7505, |
16656 | | /* SUBU_S_QB_MM */ |
16657 | | 7508, |
16658 | | /* SUBVI_B */ |
16659 | | 7511, |
16660 | | /* SUBVI_D */ |
16661 | | 7514, |
16662 | | /* SUBVI_H */ |
16663 | | 7517, |
16664 | | /* SUBVI_W */ |
16665 | | 7520, |
16666 | | /* SUBV_B */ |
16667 | | 7523, |
16668 | | /* SUBV_D */ |
16669 | | 7526, |
16670 | | /* SUBV_H */ |
16671 | | 7529, |
16672 | | /* SUBV_W */ |
16673 | | 7532, |
16674 | | /* SUB_MM */ |
16675 | | 7535, |
16676 | | /* SUB_MMR6 */ |
16677 | | 7538, |
16678 | | /* SUBu */ |
16679 | | 7541, |
16680 | | /* SUBu_MM */ |
16681 | | 7544, |
16682 | | /* SUXC1 */ |
16683 | | 7547, |
16684 | | /* SUXC164 */ |
16685 | | 7550, |
16686 | | /* SUXC1_MM */ |
16687 | | 7553, |
16688 | | /* SW */ |
16689 | | 7556, |
16690 | | /* SW16_MM */ |
16691 | | 7559, |
16692 | | /* SW16_MMR6 */ |
16693 | | 7562, |
16694 | | /* SW64 */ |
16695 | | 7565, |
16696 | | /* SWC1 */ |
16697 | | 7568, |
16698 | | /* SWC1_MM */ |
16699 | | 7571, |
16700 | | /* SWC2 */ |
16701 | | 7574, |
16702 | | /* SWC2_MMR6 */ |
16703 | | 7577, |
16704 | | /* SWC2_R6 */ |
16705 | | 7580, |
16706 | | /* SWC3 */ |
16707 | | 7583, |
16708 | | /* SWDSP */ |
16709 | | 7586, |
16710 | | /* SWDSP_MM */ |
16711 | | 7589, |
16712 | | /* SWE */ |
16713 | | 7592, |
16714 | | /* SWE_MM */ |
16715 | | 7595, |
16716 | | /* SWL */ |
16717 | | 7598, |
16718 | | /* SWL64 */ |
16719 | | 7601, |
16720 | | /* SWLE */ |
16721 | | 7604, |
16722 | | /* SWLE_MM */ |
16723 | | 7607, |
16724 | | /* SWL_MM */ |
16725 | | 7610, |
16726 | | /* SWM16_MM */ |
16727 | | 7613, |
16728 | | /* SWM16_MMR6 */ |
16729 | | 7616, |
16730 | | /* SWM32_MM */ |
16731 | | 7619, |
16732 | | /* SWP_MM */ |
16733 | | 7622, |
16734 | | /* SWR */ |
16735 | | 7626, |
16736 | | /* SWR64 */ |
16737 | | 7629, |
16738 | | /* SWRE */ |
16739 | | 7632, |
16740 | | /* SWRE_MM */ |
16741 | | 7635, |
16742 | | /* SWR_MM */ |
16743 | | 7638, |
16744 | | /* SWSP_MM */ |
16745 | | 7641, |
16746 | | /* SWSP_MMR6 */ |
16747 | | 7644, |
16748 | | /* SWXC1 */ |
16749 | | 7647, |
16750 | | /* SWXC1_MM */ |
16751 | | 7650, |
16752 | | /* SW_MM */ |
16753 | | 7653, |
16754 | | /* SW_MMR6 */ |
16755 | | 7656, |
16756 | | /* SYNC */ |
16757 | | 7659, |
16758 | | /* SYNCI */ |
16759 | | 7660, |
16760 | | /* SYNCI_MM */ |
16761 | | 7662, |
16762 | | /* SYNCI_MMR6 */ |
16763 | | 7664, |
16764 | | /* SYNC_MM */ |
16765 | | 7666, |
16766 | | /* SYNC_MMR6 */ |
16767 | | 7667, |
16768 | | /* SYSCALL */ |
16769 | | 7668, |
16770 | | /* SYSCALL_MM */ |
16771 | | 7669, |
16772 | | /* Save16 */ |
16773 | | 7670, |
16774 | | /* SaveX16 */ |
16775 | | 7670, |
16776 | | /* SbRxRyOffMemX16 */ |
16777 | | 7670, |
16778 | | /* SebRx16 */ |
16779 | | 7673, |
16780 | | /* SehRx16 */ |
16781 | | 7675, |
16782 | | /* ShRxRyOffMemX16 */ |
16783 | | 7677, |
16784 | | /* SllX16 */ |
16785 | | 7680, |
16786 | | /* SllvRxRy16 */ |
16787 | | 7683, |
16788 | | /* SltRxRy16 */ |
16789 | | 7686, |
16790 | | /* SltiRxImm16 */ |
16791 | | 7688, |
16792 | | /* SltiRxImmX16 */ |
16793 | | 7690, |
16794 | | /* SltiuRxImm16 */ |
16795 | | 7692, |
16796 | | /* SltiuRxImmX16 */ |
16797 | | 7694, |
16798 | | /* SltuRxRy16 */ |
16799 | | 7696, |
16800 | | /* SraX16 */ |
16801 | | 7698, |
16802 | | /* SravRxRy16 */ |
16803 | | 7701, |
16804 | | /* SrlX16 */ |
16805 | | 7704, |
16806 | | /* SrlvRxRy16 */ |
16807 | | 7707, |
16808 | | /* SubuRxRyRz16 */ |
16809 | | 7710, |
16810 | | /* SwRxRyOffMemX16 */ |
16811 | | 7713, |
16812 | | /* SwRxSpImmX16 */ |
16813 | | 7716, |
16814 | | /* TEQ */ |
16815 | | 7719, |
16816 | | /* TEQI */ |
16817 | | 7722, |
16818 | | /* TEQI_MM */ |
16819 | | 7724, |
16820 | | /* TEQ_MM */ |
16821 | | 7726, |
16822 | | /* TGE */ |
16823 | | 7729, |
16824 | | /* TGEI */ |
16825 | | 7732, |
16826 | | /* TGEIU */ |
16827 | | 7734, |
16828 | | /* TGEIU_MM */ |
16829 | | 7736, |
16830 | | /* TGEI_MM */ |
16831 | | 7738, |
16832 | | /* TGEU */ |
16833 | | 7740, |
16834 | | /* TGEU_MM */ |
16835 | | 7743, |
16836 | | /* TGE_MM */ |
16837 | | 7746, |
16838 | | /* TLBGINV */ |
16839 | | 7749, |
16840 | | /* TLBGINVF */ |
16841 | | 7749, |
16842 | | /* TLBGINVF_MM */ |
16843 | | 7749, |
16844 | | /* TLBGINV_MM */ |
16845 | | 7749, |
16846 | | /* TLBGP */ |
16847 | | 7749, |
16848 | | /* TLBGP_MM */ |
16849 | | 7749, |
16850 | | /* TLBGR */ |
16851 | | 7749, |
16852 | | /* TLBGR_MM */ |
16853 | | 7749, |
16854 | | /* TLBGWI */ |
16855 | | 7749, |
16856 | | /* TLBGWI_MM */ |
16857 | | 7749, |
16858 | | /* TLBGWR */ |
16859 | | 7749, |
16860 | | /* TLBGWR_MM */ |
16861 | | 7749, |
16862 | | /* TLBINV */ |
16863 | | 7749, |
16864 | | /* TLBINVF */ |
16865 | | 7749, |
16866 | | /* TLBINVF_MMR6 */ |
16867 | | 7749, |
16868 | | /* TLBINV_MMR6 */ |
16869 | | 7749, |
16870 | | /* TLBP */ |
16871 | | 7749, |
16872 | | /* TLBP_MM */ |
16873 | | 7749, |
16874 | | /* TLBR */ |
16875 | | 7749, |
16876 | | /* TLBR_MM */ |
16877 | | 7749, |
16878 | | /* TLBWI */ |
16879 | | 7749, |
16880 | | /* TLBWI_MM */ |
16881 | | 7749, |
16882 | | /* TLBWR */ |
16883 | | 7749, |
16884 | | /* TLBWR_MM */ |
16885 | | 7749, |
16886 | | /* TLT */ |
16887 | | 7749, |
16888 | | /* TLTI */ |
16889 | | 7752, |
16890 | | /* TLTIU_MM */ |
16891 | | 7754, |
16892 | | /* TLTI_MM */ |
16893 | | 7756, |
16894 | | /* TLTU */ |
16895 | | 7758, |
16896 | | /* TLTU_MM */ |
16897 | | 7761, |
16898 | | /* TLT_MM */ |
16899 | | 7764, |
16900 | | /* TNE */ |
16901 | | 7767, |
16902 | | /* TNEI */ |
16903 | | 7770, |
16904 | | /* TNEI_MM */ |
16905 | | 7772, |
16906 | | /* TNE_MM */ |
16907 | | 7774, |
16908 | | /* TRUNC_L_D64 */ |
16909 | | 7777, |
16910 | | /* TRUNC_L_D_MMR6 */ |
16911 | | 7779, |
16912 | | /* TRUNC_L_S */ |
16913 | | 7781, |
16914 | | /* TRUNC_L_S_MMR6 */ |
16915 | | 7783, |
16916 | | /* TRUNC_W_D32 */ |
16917 | | 7785, |
16918 | | /* TRUNC_W_D64 */ |
16919 | | 7787, |
16920 | | /* TRUNC_W_D_MMR6 */ |
16921 | | 7789, |
16922 | | /* TRUNC_W_MM */ |
16923 | | 7791, |
16924 | | /* TRUNC_W_S */ |
16925 | | 7793, |
16926 | | /* TRUNC_W_S_MM */ |
16927 | | 7795, |
16928 | | /* TRUNC_W_S_MMR6 */ |
16929 | | 7797, |
16930 | | /* TTLTIU */ |
16931 | | 7799, |
16932 | | /* UDIV */ |
16933 | | 7801, |
16934 | | /* UDIV_MM */ |
16935 | | 7803, |
16936 | | /* V3MULU */ |
16937 | | 7805, |
16938 | | /* VMM0 */ |
16939 | | 7808, |
16940 | | /* VMULU */ |
16941 | | 7811, |
16942 | | /* VSHF_B */ |
16943 | | 7814, |
16944 | | /* VSHF_D */ |
16945 | | 7818, |
16946 | | /* VSHF_H */ |
16947 | | 7822, |
16948 | | /* VSHF_W */ |
16949 | | 7826, |
16950 | | /* WAIT */ |
16951 | | 7830, |
16952 | | /* WAIT_MM */ |
16953 | | 7830, |
16954 | | /* WAIT_MMR6 */ |
16955 | | 7831, |
16956 | | /* WRDSP */ |
16957 | | 7832, |
16958 | | /* WRDSP_MM */ |
16959 | | 7834, |
16960 | | /* WRPGPR_MMR6 */ |
16961 | | 7836, |
16962 | | /* WSBH */ |
16963 | | 7838, |
16964 | | /* WSBH_MM */ |
16965 | | 7840, |
16966 | | /* WSBH_MMR6 */ |
16967 | | 7842, |
16968 | | /* XOR */ |
16969 | | 7844, |
16970 | | /* XOR16_MM */ |
16971 | | 7847, |
16972 | | /* XOR16_MMR6 */ |
16973 | | 7850, |
16974 | | /* XOR64 */ |
16975 | | 7853, |
16976 | | /* XORI_B */ |
16977 | | 7856, |
16978 | | /* XORI_MMR6 */ |
16979 | | 7859, |
16980 | | /* XOR_MM */ |
16981 | | 7862, |
16982 | | /* XOR_MMR6 */ |
16983 | | 7865, |
16984 | | /* XOR_V */ |
16985 | | 7868, |
16986 | | /* XORi */ |
16987 | | 7871, |
16988 | | /* XORi64 */ |
16989 | | 7874, |
16990 | | /* XORi_MM */ |
16991 | | 7877, |
16992 | | /* XorRxRxRy16 */ |
16993 | | 7880, |
16994 | | /* YIELD */ |
16995 | | 7883, |
16996 | | }; |
16997 | | |
16998 | | using namespace OpTypes; |
16999 | | static const int16_t OpcodeOperandTypes[] = { |
17000 | | |
17001 | | /* PHI */ |
17002 | | -1, |
17003 | | /* INLINEASM */ |
17004 | | /* INLINEASM_BR */ |
17005 | | /* CFI_INSTRUCTION */ |
17006 | | i32imm, |
17007 | | /* EH_LABEL */ |
17008 | | i32imm, |
17009 | | /* GC_LABEL */ |
17010 | | i32imm, |
17011 | | /* ANNOTATION_LABEL */ |
17012 | | i32imm, |
17013 | | /* KILL */ |
17014 | | /* EXTRACT_SUBREG */ |
17015 | | -1, -1, i32imm, |
17016 | | /* INSERT_SUBREG */ |
17017 | | -1, -1, -1, i32imm, |
17018 | | /* IMPLICIT_DEF */ |
17019 | | -1, |
17020 | | /* SUBREG_TO_REG */ |
17021 | | -1, -1, -1, i32imm, |
17022 | | /* COPY_TO_REGCLASS */ |
17023 | | -1, -1, i32imm, |
17024 | | /* DBG_VALUE */ |
17025 | | /* DBG_VALUE_LIST */ |
17026 | | /* DBG_INSTR_REF */ |
17027 | | /* DBG_PHI */ |
17028 | | /* DBG_LABEL */ |
17029 | | -1, |
17030 | | /* REG_SEQUENCE */ |
17031 | | -1, -1, |
17032 | | /* COPY */ |
17033 | | -1, -1, |
17034 | | /* BUNDLE */ |
17035 | | /* LIFETIME_START */ |
17036 | | i32imm, |
17037 | | /* LIFETIME_END */ |
17038 | | i32imm, |
17039 | | /* PSEUDO_PROBE */ |
17040 | | i64imm, i64imm, i8imm, i32imm, |
17041 | | /* ARITH_FENCE */ |
17042 | | -1, -1, |
17043 | | /* STACKMAP */ |
17044 | | i64imm, i32imm, |
17045 | | /* FENTRY_CALL */ |
17046 | | /* PATCHPOINT */ |
17047 | | -1, i64imm, i32imm, -1, i32imm, i32imm, |
17048 | | /* LOAD_STACK_GUARD */ |
17049 | | -1, |
17050 | | /* PREALLOCATED_SETUP */ |
17051 | | i32imm, |
17052 | | /* PREALLOCATED_ARG */ |
17053 | | -1, i32imm, i32imm, |
17054 | | /* STATEPOINT */ |
17055 | | /* LOCAL_ESCAPE */ |
17056 | | -1, i32imm, |
17057 | | /* FAULTING_OP */ |
17058 | | -1, |
17059 | | /* PATCHABLE_OP */ |
17060 | | /* PATCHABLE_FUNCTION_ENTER */ |
17061 | | /* PATCHABLE_RET */ |
17062 | | /* PATCHABLE_FUNCTION_EXIT */ |
17063 | | /* PATCHABLE_TAIL_CALL */ |
17064 | | /* PATCHABLE_EVENT_CALL */ |
17065 | | -1, -1, |
17066 | | /* PATCHABLE_TYPED_EVENT_CALL */ |
17067 | | -1, -1, -1, |
17068 | | /* ICALL_BRANCH_FUNNEL */ |
17069 | | /* MEMBARRIER */ |
17070 | | /* JUMP_TABLE_DEBUG_INFO */ |
17071 | | i64imm, |
17072 | | /* G_ASSERT_SEXT */ |
17073 | | type0, type0, untyped_imm_0, |
17074 | | /* G_ASSERT_ZEXT */ |
17075 | | type0, type0, untyped_imm_0, |
17076 | | /* G_ASSERT_ALIGN */ |
17077 | | type0, type0, untyped_imm_0, |
17078 | | /* G_ADD */ |
17079 | | type0, type0, type0, |
17080 | | /* G_SUB */ |
17081 | | type0, type0, type0, |
17082 | | /* G_MUL */ |
17083 | | type0, type0, type0, |
17084 | | /* G_SDIV */ |
17085 | | type0, type0, type0, |
17086 | | /* G_UDIV */ |
17087 | | type0, type0, type0, |
17088 | | /* G_SREM */ |
17089 | | type0, type0, type0, |
17090 | | /* G_UREM */ |
17091 | | type0, type0, type0, |
17092 | | /* G_SDIVREM */ |
17093 | | type0, type0, type0, type0, |
17094 | | /* G_UDIVREM */ |
17095 | | type0, type0, type0, type0, |
17096 | | /* G_AND */ |
17097 | | type0, type0, type0, |
17098 | | /* G_OR */ |
17099 | | type0, type0, type0, |
17100 | | /* G_XOR */ |
17101 | | type0, type0, type0, |
17102 | | /* G_IMPLICIT_DEF */ |
17103 | | type0, |
17104 | | /* G_PHI */ |
17105 | | type0, |
17106 | | /* G_FRAME_INDEX */ |
17107 | | type0, -1, |
17108 | | /* G_GLOBAL_VALUE */ |
17109 | | type0, -1, |
17110 | | /* G_CONSTANT_POOL */ |
17111 | | type0, -1, |
17112 | | /* G_EXTRACT */ |
17113 | | type0, type1, untyped_imm_0, |
17114 | | /* G_UNMERGE_VALUES */ |
17115 | | type0, type1, |
17116 | | /* G_INSERT */ |
17117 | | type0, type0, type1, untyped_imm_0, |
17118 | | /* G_MERGE_VALUES */ |
17119 | | type0, type1, |
17120 | | /* G_BUILD_VECTOR */ |
17121 | | type0, type1, |
17122 | | /* G_BUILD_VECTOR_TRUNC */ |
17123 | | type0, type1, |
17124 | | /* G_CONCAT_VECTORS */ |
17125 | | type0, type1, |
17126 | | /* G_PTRTOINT */ |
17127 | | type0, type1, |
17128 | | /* G_INTTOPTR */ |
17129 | | type0, type1, |
17130 | | /* G_BITCAST */ |
17131 | | type0, type1, |
17132 | | /* G_FREEZE */ |
17133 | | type0, type0, |
17134 | | /* G_CONSTANT_FOLD_BARRIER */ |
17135 | | type0, type0, |
17136 | | /* G_INTRINSIC_FPTRUNC_ROUND */ |
17137 | | type0, type1, i32imm, |
17138 | | /* G_INTRINSIC_TRUNC */ |
17139 | | type0, type0, |
17140 | | /* G_INTRINSIC_ROUND */ |
17141 | | type0, type0, |
17142 | | /* G_INTRINSIC_LRINT */ |
17143 | | type0, type1, |
17144 | | /* G_INTRINSIC_ROUNDEVEN */ |
17145 | | type0, type0, |
17146 | | /* G_READCYCLECOUNTER */ |
17147 | | type0, |
17148 | | /* G_LOAD */ |
17149 | | type0, ptype1, |
17150 | | /* G_SEXTLOAD */ |
17151 | | type0, ptype1, |
17152 | | /* G_ZEXTLOAD */ |
17153 | | type0, ptype1, |
17154 | | /* G_INDEXED_LOAD */ |
17155 | | type0, ptype1, ptype1, type2, -1, |
17156 | | /* G_INDEXED_SEXTLOAD */ |
17157 | | type0, ptype1, ptype1, type2, -1, |
17158 | | /* G_INDEXED_ZEXTLOAD */ |
17159 | | type0, ptype1, ptype1, type2, -1, |
17160 | | /* G_STORE */ |
17161 | | type0, ptype1, |
17162 | | /* G_INDEXED_STORE */ |
17163 | | ptype0, type1, ptype0, ptype2, -1, |
17164 | | /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */ |
17165 | | type0, type1, type2, type0, type0, |
17166 | | /* G_ATOMIC_CMPXCHG */ |
17167 | | type0, ptype1, type0, type0, |
17168 | | /* G_ATOMICRMW_XCHG */ |
17169 | | type0, ptype1, type0, |
17170 | | /* G_ATOMICRMW_ADD */ |
17171 | | type0, ptype1, type0, |
17172 | | /* G_ATOMICRMW_SUB */ |
17173 | | type0, ptype1, type0, |
17174 | | /* G_ATOMICRMW_AND */ |
17175 | | type0, ptype1, type0, |
17176 | | /* G_ATOMICRMW_NAND */ |
17177 | | type0, ptype1, type0, |
17178 | | /* G_ATOMICRMW_OR */ |
17179 | | type0, ptype1, type0, |
17180 | | /* G_ATOMICRMW_XOR */ |
17181 | | type0, ptype1, type0, |
17182 | | /* G_ATOMICRMW_MAX */ |
17183 | | type0, ptype1, type0, |
17184 | | /* G_ATOMICRMW_MIN */ |
17185 | | type0, ptype1, type0, |
17186 | | /* G_ATOMICRMW_UMAX */ |
17187 | | type0, ptype1, type0, |
17188 | | /* G_ATOMICRMW_UMIN */ |
17189 | | type0, ptype1, type0, |
17190 | | /* G_ATOMICRMW_FADD */ |
17191 | | type0, ptype1, type0, |
17192 | | /* G_ATOMICRMW_FSUB */ |
17193 | | type0, ptype1, type0, |
17194 | | /* G_ATOMICRMW_FMAX */ |
17195 | | type0, ptype1, type0, |
17196 | | /* G_ATOMICRMW_FMIN */ |
17197 | | type0, ptype1, type0, |
17198 | | /* G_ATOMICRMW_UINC_WRAP */ |
17199 | | type0, ptype1, type0, |
17200 | | /* G_ATOMICRMW_UDEC_WRAP */ |
17201 | | type0, ptype1, type0, |
17202 | | /* G_FENCE */ |
17203 | | i32imm, i32imm, |
17204 | | /* G_PREFETCH */ |
17205 | | ptype0, i32imm, i32imm, i32imm, |
17206 | | /* G_BRCOND */ |
17207 | | type0, -1, |
17208 | | /* G_BRINDIRECT */ |
17209 | | type0, |
17210 | | /* G_INVOKE_REGION_START */ |
17211 | | /* G_INTRINSIC */ |
17212 | | -1, |
17213 | | /* G_INTRINSIC_W_SIDE_EFFECTS */ |
17214 | | -1, |
17215 | | /* G_INTRINSIC_CONVERGENT */ |
17216 | | -1, |
17217 | | /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */ |
17218 | | -1, |
17219 | | /* G_ANYEXT */ |
17220 | | type0, type1, |
17221 | | /* G_TRUNC */ |
17222 | | type0, type1, |
17223 | | /* G_CONSTANT */ |
17224 | | type0, -1, |
17225 | | /* G_FCONSTANT */ |
17226 | | type0, -1, |
17227 | | /* G_VASTART */ |
17228 | | type0, |
17229 | | /* G_VAARG */ |
17230 | | type0, type1, -1, |
17231 | | /* G_SEXT */ |
17232 | | type0, type1, |
17233 | | /* G_SEXT_INREG */ |
17234 | | type0, type0, untyped_imm_0, |
17235 | | /* G_ZEXT */ |
17236 | | type0, type1, |
17237 | | /* G_SHL */ |
17238 | | type0, type0, type1, |
17239 | | /* G_LSHR */ |
17240 | | type0, type0, type1, |
17241 | | /* G_ASHR */ |
17242 | | type0, type0, type1, |
17243 | | /* G_FSHL */ |
17244 | | type0, type0, type0, type1, |
17245 | | /* G_FSHR */ |
17246 | | type0, type0, type0, type1, |
17247 | | /* G_ROTR */ |
17248 | | type0, type0, type1, |
17249 | | /* G_ROTL */ |
17250 | | type0, type0, type1, |
17251 | | /* G_ICMP */ |
17252 | | type0, -1, type1, type1, |
17253 | | /* G_FCMP */ |
17254 | | type0, -1, type1, type1, |
17255 | | /* G_SELECT */ |
17256 | | type0, type1, type0, type0, |
17257 | | /* G_UADDO */ |
17258 | | type0, type1, type0, type0, |
17259 | | /* G_UADDE */ |
17260 | | type0, type1, type0, type0, type1, |
17261 | | /* G_USUBO */ |
17262 | | type0, type1, type0, type0, |
17263 | | /* G_USUBE */ |
17264 | | type0, type1, type0, type0, type1, |
17265 | | /* G_SADDO */ |
17266 | | type0, type1, type0, type0, |
17267 | | /* G_SADDE */ |
17268 | | type0, type1, type0, type0, type1, |
17269 | | /* G_SSUBO */ |
17270 | | type0, type1, type0, type0, |
17271 | | /* G_SSUBE */ |
17272 | | type0, type1, type0, type0, type1, |
17273 | | /* G_UMULO */ |
17274 | | type0, type1, type0, type0, |
17275 | | /* G_SMULO */ |
17276 | | type0, type1, type0, type0, |
17277 | | /* G_UMULH */ |
17278 | | type0, type0, type0, |
17279 | | /* G_SMULH */ |
17280 | | type0, type0, type0, |
17281 | | /* G_UADDSAT */ |
17282 | | type0, type0, type0, |
17283 | | /* G_SADDSAT */ |
17284 | | type0, type0, type0, |
17285 | | /* G_USUBSAT */ |
17286 | | type0, type0, type0, |
17287 | | /* G_SSUBSAT */ |
17288 | | type0, type0, type0, |
17289 | | /* G_USHLSAT */ |
17290 | | type0, type0, type1, |
17291 | | /* G_SSHLSAT */ |
17292 | | type0, type0, type1, |
17293 | | /* G_SMULFIX */ |
17294 | | type0, type0, type0, untyped_imm_0, |
17295 | | /* G_UMULFIX */ |
17296 | | type0, type0, type0, untyped_imm_0, |
17297 | | /* G_SMULFIXSAT */ |
17298 | | type0, type0, type0, untyped_imm_0, |
17299 | | /* G_UMULFIXSAT */ |
17300 | | type0, type0, type0, untyped_imm_0, |
17301 | | /* G_SDIVFIX */ |
17302 | | type0, type0, type0, untyped_imm_0, |
17303 | | /* G_UDIVFIX */ |
17304 | | type0, type0, type0, untyped_imm_0, |
17305 | | /* G_SDIVFIXSAT */ |
17306 | | type0, type0, type0, untyped_imm_0, |
17307 | | /* G_UDIVFIXSAT */ |
17308 | | type0, type0, type0, untyped_imm_0, |
17309 | | /* G_FADD */ |
17310 | | type0, type0, type0, |
17311 | | /* G_FSUB */ |
17312 | | type0, type0, type0, |
17313 | | /* G_FMUL */ |
17314 | | type0, type0, type0, |
17315 | | /* G_FMA */ |
17316 | | type0, type0, type0, type0, |
17317 | | /* G_FMAD */ |
17318 | | type0, type0, type0, type0, |
17319 | | /* G_FDIV */ |
17320 | | type0, type0, type0, |
17321 | | /* G_FREM */ |
17322 | | type0, type0, type0, |
17323 | | /* G_FPOW */ |
17324 | | type0, type0, type0, |
17325 | | /* G_FPOWI */ |
17326 | | type0, type0, type1, |
17327 | | /* G_FEXP */ |
17328 | | type0, type0, |
17329 | | /* G_FEXP2 */ |
17330 | | type0, type0, |
17331 | | /* G_FEXP10 */ |
17332 | | type0, type0, |
17333 | | /* G_FLOG */ |
17334 | | type0, type0, |
17335 | | /* G_FLOG2 */ |
17336 | | type0, type0, |
17337 | | /* G_FLOG10 */ |
17338 | | type0, type0, |
17339 | | /* G_FLDEXP */ |
17340 | | type0, type0, type1, |
17341 | | /* G_FFREXP */ |
17342 | | type0, type1, type0, |
17343 | | /* G_FNEG */ |
17344 | | type0, type0, |
17345 | | /* G_FPEXT */ |
17346 | | type0, type1, |
17347 | | /* G_FPTRUNC */ |
17348 | | type0, type1, |
17349 | | /* G_FPTOSI */ |
17350 | | type0, type1, |
17351 | | /* G_FPTOUI */ |
17352 | | type0, type1, |
17353 | | /* G_SITOFP */ |
17354 | | type0, type1, |
17355 | | /* G_UITOFP */ |
17356 | | type0, type1, |
17357 | | /* G_FABS */ |
17358 | | type0, type0, |
17359 | | /* G_FCOPYSIGN */ |
17360 | | type0, type0, type1, |
17361 | | /* G_IS_FPCLASS */ |
17362 | | type0, type1, -1, |
17363 | | /* G_FCANONICALIZE */ |
17364 | | type0, type0, |
17365 | | /* G_FMINNUM */ |
17366 | | type0, type0, type0, |
17367 | | /* G_FMAXNUM */ |
17368 | | type0, type0, type0, |
17369 | | /* G_FMINNUM_IEEE */ |
17370 | | type0, type0, type0, |
17371 | | /* G_FMAXNUM_IEEE */ |
17372 | | type0, type0, type0, |
17373 | | /* G_FMINIMUM */ |
17374 | | type0, type0, type0, |
17375 | | /* G_FMAXIMUM */ |
17376 | | type0, type0, type0, |
17377 | | /* G_GET_FPENV */ |
17378 | | type0, |
17379 | | /* G_SET_FPENV */ |
17380 | | type0, |
17381 | | /* G_RESET_FPENV */ |
17382 | | /* G_GET_FPMODE */ |
17383 | | type0, |
17384 | | /* G_SET_FPMODE */ |
17385 | | type0, |
17386 | | /* G_RESET_FPMODE */ |
17387 | | /* G_PTR_ADD */ |
17388 | | ptype0, ptype0, type1, |
17389 | | /* G_PTRMASK */ |
17390 | | ptype0, ptype0, type1, |
17391 | | /* G_SMIN */ |
17392 | | type0, type0, type0, |
17393 | | /* G_SMAX */ |
17394 | | type0, type0, type0, |
17395 | | /* G_UMIN */ |
17396 | | type0, type0, type0, |
17397 | | /* G_UMAX */ |
17398 | | type0, type0, type0, |
17399 | | /* G_ABS */ |
17400 | | type0, type0, |
17401 | | /* G_LROUND */ |
17402 | | type0, type1, |
17403 | | /* G_LLROUND */ |
17404 | | type0, type1, |
17405 | | /* G_BR */ |
17406 | | -1, |
17407 | | /* G_BRJT */ |
17408 | | ptype0, -1, type1, |
17409 | | /* G_INSERT_VECTOR_ELT */ |
17410 | | type0, type0, type1, type2, |
17411 | | /* G_EXTRACT_VECTOR_ELT */ |
17412 | | type0, type1, type2, |
17413 | | /* G_SHUFFLE_VECTOR */ |
17414 | | type0, type1, type1, -1, |
17415 | | /* G_CTTZ */ |
17416 | | type0, type1, |
17417 | | /* G_CTTZ_ZERO_UNDEF */ |
17418 | | type0, type1, |
17419 | | /* G_CTLZ */ |
17420 | | type0, type1, |
17421 | | /* G_CTLZ_ZERO_UNDEF */ |
17422 | | type0, type1, |
17423 | | /* G_CTPOP */ |
17424 | | type0, type1, |
17425 | | /* G_BSWAP */ |
17426 | | type0, type0, |
17427 | | /* G_BITREVERSE */ |
17428 | | type0, type0, |
17429 | | /* G_FCEIL */ |
17430 | | type0, type0, |
17431 | | /* G_FCOS */ |
17432 | | type0, type0, |
17433 | | /* G_FSIN */ |
17434 | | type0, type0, |
17435 | | /* G_FSQRT */ |
17436 | | type0, type0, |
17437 | | /* G_FFLOOR */ |
17438 | | type0, type0, |
17439 | | /* G_FRINT */ |
17440 | | type0, type0, |
17441 | | /* G_FNEARBYINT */ |
17442 | | type0, type0, |
17443 | | /* G_ADDRSPACE_CAST */ |
17444 | | type0, type1, |
17445 | | /* G_BLOCK_ADDR */ |
17446 | | type0, -1, |
17447 | | /* G_JUMP_TABLE */ |
17448 | | type0, -1, |
17449 | | /* G_DYN_STACKALLOC */ |
17450 | | ptype0, type1, i32imm, |
17451 | | /* G_STACKSAVE */ |
17452 | | ptype0, |
17453 | | /* G_STACKRESTORE */ |
17454 | | ptype0, |
17455 | | /* G_STRICT_FADD */ |
17456 | | type0, type0, type0, |
17457 | | /* G_STRICT_FSUB */ |
17458 | | type0, type0, type0, |
17459 | | /* G_STRICT_FMUL */ |
17460 | | type0, type0, type0, |
17461 | | /* G_STRICT_FDIV */ |
17462 | | type0, type0, type0, |
17463 | | /* G_STRICT_FREM */ |
17464 | | type0, type0, type0, |
17465 | | /* G_STRICT_FMA */ |
17466 | | type0, type0, type0, type0, |
17467 | | /* G_STRICT_FSQRT */ |
17468 | | type0, type0, |
17469 | | /* G_STRICT_FLDEXP */ |
17470 | | type0, type0, type1, |
17471 | | /* G_READ_REGISTER */ |
17472 | | type0, -1, |
17473 | | /* G_WRITE_REGISTER */ |
17474 | | -1, type0, |
17475 | | /* G_MEMCPY */ |
17476 | | ptype0, ptype1, type2, untyped_imm_0, |
17477 | | /* G_MEMCPY_INLINE */ |
17478 | | ptype0, ptype1, type2, |
17479 | | /* G_MEMMOVE */ |
17480 | | ptype0, ptype1, type2, untyped_imm_0, |
17481 | | /* G_MEMSET */ |
17482 | | ptype0, type1, type2, untyped_imm_0, |
17483 | | /* G_BZERO */ |
17484 | | ptype0, type1, untyped_imm_0, |
17485 | | /* G_VECREDUCE_SEQ_FADD */ |
17486 | | type0, type1, type2, |
17487 | | /* G_VECREDUCE_SEQ_FMUL */ |
17488 | | type0, type1, type2, |
17489 | | /* G_VECREDUCE_FADD */ |
17490 | | type0, type1, |
17491 | | /* G_VECREDUCE_FMUL */ |
17492 | | type0, type1, |
17493 | | /* G_VECREDUCE_FMAX */ |
17494 | | type0, type1, |
17495 | | /* G_VECREDUCE_FMIN */ |
17496 | | type0, type1, |
17497 | | /* G_VECREDUCE_FMAXIMUM */ |
17498 | | type0, type1, |
17499 | | /* G_VECREDUCE_FMINIMUM */ |
17500 | | type0, type1, |
17501 | | /* G_VECREDUCE_ADD */ |
17502 | | type0, type1, |
17503 | | /* G_VECREDUCE_MUL */ |
17504 | | type0, type1, |
17505 | | /* G_VECREDUCE_AND */ |
17506 | | type0, type1, |
17507 | | /* G_VECREDUCE_OR */ |
17508 | | type0, type1, |
17509 | | /* G_VECREDUCE_XOR */ |
17510 | | type0, type1, |
17511 | | /* G_VECREDUCE_SMAX */ |
17512 | | type0, type1, |
17513 | | /* G_VECREDUCE_SMIN */ |
17514 | | type0, type1, |
17515 | | /* G_VECREDUCE_UMAX */ |
17516 | | type0, type1, |
17517 | | /* G_VECREDUCE_UMIN */ |
17518 | | type0, type1, |
17519 | | /* G_SBFX */ |
17520 | | type0, type0, type1, type1, |
17521 | | /* G_UBFX */ |
17522 | | type0, type0, type1, type1, |
17523 | | /* ABSMacro */ |
17524 | | GPR32Opnd, GPR32Opnd, |
17525 | | /* ADJCALLSTACKDOWN */ |
17526 | | i32imm, i32imm, |
17527 | | /* ADJCALLSTACKUP */ |
17528 | | i32imm, i32imm, |
17529 | | /* AND_V_D_PSEUDO */ |
17530 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
17531 | | /* AND_V_H_PSEUDO */ |
17532 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
17533 | | /* AND_V_W_PSEUDO */ |
17534 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
17535 | | /* ATOMIC_CMP_SWAP_I16 */ |
17536 | | GPR32, -1, GPR32, GPR32, |
17537 | | /* ATOMIC_CMP_SWAP_I16_POSTRA */ |
17538 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, |
17539 | | /* ATOMIC_CMP_SWAP_I32 */ |
17540 | | GPR32, -1, GPR32, GPR32, |
17541 | | /* ATOMIC_CMP_SWAP_I32_POSTRA */ |
17542 | | GPR32, -1, GPR32, GPR32, |
17543 | | /* ATOMIC_CMP_SWAP_I64 */ |
17544 | | GPR64, -1, GPR64, GPR64, |
17545 | | /* ATOMIC_CMP_SWAP_I64_POSTRA */ |
17546 | | GPR64, -1, GPR64, GPR64, |
17547 | | /* ATOMIC_CMP_SWAP_I8 */ |
17548 | | GPR32, -1, GPR32, GPR32, |
17549 | | /* ATOMIC_CMP_SWAP_I8_POSTRA */ |
17550 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, GPR32, |
17551 | | /* ATOMIC_LOAD_ADD_I16 */ |
17552 | | GPR32, -1, GPR32, |
17553 | | /* ATOMIC_LOAD_ADD_I16_POSTRA */ |
17554 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17555 | | /* ATOMIC_LOAD_ADD_I32 */ |
17556 | | GPR32, -1, GPR32, |
17557 | | /* ATOMIC_LOAD_ADD_I32_POSTRA */ |
17558 | | GPR32, -1, GPR32, |
17559 | | /* ATOMIC_LOAD_ADD_I64 */ |
17560 | | GPR64, -1, GPR64, |
17561 | | /* ATOMIC_LOAD_ADD_I64_POSTRA */ |
17562 | | GPR64, -1, GPR64, |
17563 | | /* ATOMIC_LOAD_ADD_I8 */ |
17564 | | GPR32, -1, GPR32, |
17565 | | /* ATOMIC_LOAD_ADD_I8_POSTRA */ |
17566 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17567 | | /* ATOMIC_LOAD_AND_I16 */ |
17568 | | GPR32, -1, GPR32, |
17569 | | /* ATOMIC_LOAD_AND_I16_POSTRA */ |
17570 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17571 | | /* ATOMIC_LOAD_AND_I32 */ |
17572 | | GPR32, -1, GPR32, |
17573 | | /* ATOMIC_LOAD_AND_I32_POSTRA */ |
17574 | | GPR32, -1, GPR32, |
17575 | | /* ATOMIC_LOAD_AND_I64 */ |
17576 | | GPR64, -1, GPR64, |
17577 | | /* ATOMIC_LOAD_AND_I64_POSTRA */ |
17578 | | GPR64, -1, GPR64, |
17579 | | /* ATOMIC_LOAD_AND_I8 */ |
17580 | | GPR32, -1, GPR32, |
17581 | | /* ATOMIC_LOAD_AND_I8_POSTRA */ |
17582 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17583 | | /* ATOMIC_LOAD_MAX_I16 */ |
17584 | | GPR32, -1, GPR32, |
17585 | | /* ATOMIC_LOAD_MAX_I16_POSTRA */ |
17586 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17587 | | /* ATOMIC_LOAD_MAX_I32 */ |
17588 | | GPR32, -1, GPR32, |
17589 | | /* ATOMIC_LOAD_MAX_I32_POSTRA */ |
17590 | | GPR32, -1, GPR32, |
17591 | | /* ATOMIC_LOAD_MAX_I64 */ |
17592 | | GPR64, -1, GPR64, |
17593 | | /* ATOMIC_LOAD_MAX_I64_POSTRA */ |
17594 | | GPR64, -1, GPR64, |
17595 | | /* ATOMIC_LOAD_MAX_I8 */ |
17596 | | GPR32, -1, GPR32, |
17597 | | /* ATOMIC_LOAD_MAX_I8_POSTRA */ |
17598 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17599 | | /* ATOMIC_LOAD_MIN_I16 */ |
17600 | | GPR32, -1, GPR32, |
17601 | | /* ATOMIC_LOAD_MIN_I16_POSTRA */ |
17602 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17603 | | /* ATOMIC_LOAD_MIN_I32 */ |
17604 | | GPR32, -1, GPR32, |
17605 | | /* ATOMIC_LOAD_MIN_I32_POSTRA */ |
17606 | | GPR32, -1, GPR32, |
17607 | | /* ATOMIC_LOAD_MIN_I64 */ |
17608 | | GPR64, -1, GPR64, |
17609 | | /* ATOMIC_LOAD_MIN_I64_POSTRA */ |
17610 | | GPR64, -1, GPR64, |
17611 | | /* ATOMIC_LOAD_MIN_I8 */ |
17612 | | GPR32, -1, GPR32, |
17613 | | /* ATOMIC_LOAD_MIN_I8_POSTRA */ |
17614 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17615 | | /* ATOMIC_LOAD_NAND_I16 */ |
17616 | | GPR32, -1, GPR32, |
17617 | | /* ATOMIC_LOAD_NAND_I16_POSTRA */ |
17618 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17619 | | /* ATOMIC_LOAD_NAND_I32 */ |
17620 | | GPR32, -1, GPR32, |
17621 | | /* ATOMIC_LOAD_NAND_I32_POSTRA */ |
17622 | | GPR32, -1, GPR32, |
17623 | | /* ATOMIC_LOAD_NAND_I64 */ |
17624 | | GPR64, -1, GPR64, |
17625 | | /* ATOMIC_LOAD_NAND_I64_POSTRA */ |
17626 | | GPR64, -1, GPR64, |
17627 | | /* ATOMIC_LOAD_NAND_I8 */ |
17628 | | GPR32, -1, GPR32, |
17629 | | /* ATOMIC_LOAD_NAND_I8_POSTRA */ |
17630 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17631 | | /* ATOMIC_LOAD_OR_I16 */ |
17632 | | GPR32, -1, GPR32, |
17633 | | /* ATOMIC_LOAD_OR_I16_POSTRA */ |
17634 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17635 | | /* ATOMIC_LOAD_OR_I32 */ |
17636 | | GPR32, -1, GPR32, |
17637 | | /* ATOMIC_LOAD_OR_I32_POSTRA */ |
17638 | | GPR32, -1, GPR32, |
17639 | | /* ATOMIC_LOAD_OR_I64 */ |
17640 | | GPR64, -1, GPR64, |
17641 | | /* ATOMIC_LOAD_OR_I64_POSTRA */ |
17642 | | GPR64, -1, GPR64, |
17643 | | /* ATOMIC_LOAD_OR_I8 */ |
17644 | | GPR32, -1, GPR32, |
17645 | | /* ATOMIC_LOAD_OR_I8_POSTRA */ |
17646 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17647 | | /* ATOMIC_LOAD_SUB_I16 */ |
17648 | | GPR32, -1, GPR32, |
17649 | | /* ATOMIC_LOAD_SUB_I16_POSTRA */ |
17650 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17651 | | /* ATOMIC_LOAD_SUB_I32 */ |
17652 | | GPR32, -1, GPR32, |
17653 | | /* ATOMIC_LOAD_SUB_I32_POSTRA */ |
17654 | | GPR32, -1, GPR32, |
17655 | | /* ATOMIC_LOAD_SUB_I64 */ |
17656 | | GPR64, -1, GPR64, |
17657 | | /* ATOMIC_LOAD_SUB_I64_POSTRA */ |
17658 | | GPR64, -1, GPR64, |
17659 | | /* ATOMIC_LOAD_SUB_I8 */ |
17660 | | GPR32, -1, GPR32, |
17661 | | /* ATOMIC_LOAD_SUB_I8_POSTRA */ |
17662 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17663 | | /* ATOMIC_LOAD_UMAX_I16 */ |
17664 | | GPR32, -1, GPR32, |
17665 | | /* ATOMIC_LOAD_UMAX_I16_POSTRA */ |
17666 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17667 | | /* ATOMIC_LOAD_UMAX_I32 */ |
17668 | | GPR32, -1, GPR32, |
17669 | | /* ATOMIC_LOAD_UMAX_I32_POSTRA */ |
17670 | | GPR32, -1, GPR32, |
17671 | | /* ATOMIC_LOAD_UMAX_I64 */ |
17672 | | GPR64, -1, GPR64, |
17673 | | /* ATOMIC_LOAD_UMAX_I64_POSTRA */ |
17674 | | GPR64, -1, GPR64, |
17675 | | /* ATOMIC_LOAD_UMAX_I8 */ |
17676 | | GPR32, -1, GPR32, |
17677 | | /* ATOMIC_LOAD_UMAX_I8_POSTRA */ |
17678 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17679 | | /* ATOMIC_LOAD_UMIN_I16 */ |
17680 | | GPR32, -1, GPR32, |
17681 | | /* ATOMIC_LOAD_UMIN_I16_POSTRA */ |
17682 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17683 | | /* ATOMIC_LOAD_UMIN_I32 */ |
17684 | | GPR32, -1, GPR32, |
17685 | | /* ATOMIC_LOAD_UMIN_I32_POSTRA */ |
17686 | | GPR32, -1, GPR32, |
17687 | | /* ATOMIC_LOAD_UMIN_I64 */ |
17688 | | GPR64, -1, GPR64, |
17689 | | /* ATOMIC_LOAD_UMIN_I64_POSTRA */ |
17690 | | GPR64, -1, GPR64, |
17691 | | /* ATOMIC_LOAD_UMIN_I8 */ |
17692 | | GPR32, -1, GPR32, |
17693 | | /* ATOMIC_LOAD_UMIN_I8_POSTRA */ |
17694 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17695 | | /* ATOMIC_LOAD_XOR_I16 */ |
17696 | | GPR32, -1, GPR32, |
17697 | | /* ATOMIC_LOAD_XOR_I16_POSTRA */ |
17698 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17699 | | /* ATOMIC_LOAD_XOR_I32 */ |
17700 | | GPR32, -1, GPR32, |
17701 | | /* ATOMIC_LOAD_XOR_I32_POSTRA */ |
17702 | | GPR32, -1, GPR32, |
17703 | | /* ATOMIC_LOAD_XOR_I64 */ |
17704 | | GPR64, -1, GPR64, |
17705 | | /* ATOMIC_LOAD_XOR_I64_POSTRA */ |
17706 | | GPR64, -1, GPR64, |
17707 | | /* ATOMIC_LOAD_XOR_I8 */ |
17708 | | GPR32, -1, GPR32, |
17709 | | /* ATOMIC_LOAD_XOR_I8_POSTRA */ |
17710 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17711 | | /* ATOMIC_SWAP_I16 */ |
17712 | | GPR32, -1, GPR32, |
17713 | | /* ATOMIC_SWAP_I16_POSTRA */ |
17714 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17715 | | /* ATOMIC_SWAP_I32 */ |
17716 | | GPR32, -1, GPR32, |
17717 | | /* ATOMIC_SWAP_I32_POSTRA */ |
17718 | | GPR32, -1, GPR32, |
17719 | | /* ATOMIC_SWAP_I64 */ |
17720 | | GPR64, -1, GPR64, |
17721 | | /* ATOMIC_SWAP_I64_POSTRA */ |
17722 | | GPR64, -1, GPR64, |
17723 | | /* ATOMIC_SWAP_I8 */ |
17724 | | GPR32, -1, GPR32, |
17725 | | /* ATOMIC_SWAP_I8_POSTRA */ |
17726 | | GPR32, -1, GPR32, GPR32, GPR32, GPR32, |
17727 | | /* B */ |
17728 | | brtarget, |
17729 | | /* BAL_BR */ |
17730 | | brtarget, |
17731 | | /* BAL_BR_MM */ |
17732 | | brtarget_mm, |
17733 | | /* BEQLImmMacro */ |
17734 | | GPR32Opnd, imm64, brtarget, |
17735 | | /* BGE */ |
17736 | | GPR32Opnd, GPR32Opnd, brtarget, |
17737 | | /* BGEImmMacro */ |
17738 | | GPR32Opnd, imm64, brtarget, |
17739 | | /* BGEL */ |
17740 | | GPR32Opnd, GPR32Opnd, brtarget, |
17741 | | /* BGELImmMacro */ |
17742 | | GPR32Opnd, imm64, brtarget, |
17743 | | /* BGEU */ |
17744 | | GPR32Opnd, GPR32Opnd, brtarget, |
17745 | | /* BGEUImmMacro */ |
17746 | | GPR32Opnd, imm64, brtarget, |
17747 | | /* BGEUL */ |
17748 | | GPR32Opnd, GPR32Opnd, brtarget, |
17749 | | /* BGEULImmMacro */ |
17750 | | GPR32Opnd, imm64, brtarget, |
17751 | | /* BGT */ |
17752 | | GPR32Opnd, GPR32Opnd, brtarget, |
17753 | | /* BGTImmMacro */ |
17754 | | GPR32Opnd, imm64, brtarget, |
17755 | | /* BGTL */ |
17756 | | GPR32Opnd, GPR32Opnd, brtarget, |
17757 | | /* BGTLImmMacro */ |
17758 | | GPR32Opnd, imm64, brtarget, |
17759 | | /* BGTU */ |
17760 | | GPR32Opnd, GPR32Opnd, brtarget, |
17761 | | /* BGTUImmMacro */ |
17762 | | GPR32Opnd, imm64, brtarget, |
17763 | | /* BGTUL */ |
17764 | | GPR32Opnd, GPR32Opnd, brtarget, |
17765 | | /* BGTULImmMacro */ |
17766 | | GPR32Opnd, imm64, brtarget, |
17767 | | /* BLE */ |
17768 | | GPR32Opnd, GPR32Opnd, brtarget, |
17769 | | /* BLEImmMacro */ |
17770 | | GPR32Opnd, imm64, brtarget, |
17771 | | /* BLEL */ |
17772 | | GPR32Opnd, GPR32Opnd, brtarget, |
17773 | | /* BLELImmMacro */ |
17774 | | GPR32Opnd, imm64, brtarget, |
17775 | | /* BLEU */ |
17776 | | GPR32Opnd, GPR32Opnd, brtarget, |
17777 | | /* BLEUImmMacro */ |
17778 | | GPR32Opnd, imm64, brtarget, |
17779 | | /* BLEUL */ |
17780 | | GPR32Opnd, GPR32Opnd, brtarget, |
17781 | | /* BLEULImmMacro */ |
17782 | | GPR32Opnd, imm64, brtarget, |
17783 | | /* BLT */ |
17784 | | GPR32Opnd, GPR32Opnd, brtarget, |
17785 | | /* BLTImmMacro */ |
17786 | | GPR32Opnd, imm64, brtarget, |
17787 | | /* BLTL */ |
17788 | | GPR32Opnd, GPR32Opnd, brtarget, |
17789 | | /* BLTLImmMacro */ |
17790 | | GPR32Opnd, imm64, brtarget, |
17791 | | /* BLTU */ |
17792 | | GPR32Opnd, GPR32Opnd, brtarget, |
17793 | | /* BLTUImmMacro */ |
17794 | | GPR32Opnd, imm64, brtarget, |
17795 | | /* BLTUL */ |
17796 | | GPR32Opnd, GPR32Opnd, brtarget, |
17797 | | /* BLTULImmMacro */ |
17798 | | GPR32Opnd, imm64, brtarget, |
17799 | | /* BNELImmMacro */ |
17800 | | GPR32Opnd, imm64, brtarget, |
17801 | | /* BPOSGE32_PSEUDO */ |
17802 | | GPR32Opnd, |
17803 | | /* BSEL_D_PSEUDO */ |
17804 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
17805 | | /* BSEL_FD_PSEUDO */ |
17806 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
17807 | | /* BSEL_FW_PSEUDO */ |
17808 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
17809 | | /* BSEL_H_PSEUDO */ |
17810 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
17811 | | /* BSEL_W_PSEUDO */ |
17812 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
17813 | | /* B_MM */ |
17814 | | brtarget, |
17815 | | /* B_MMR6_Pseudo */ |
17816 | | brtarget_mm, |
17817 | | /* B_MM_Pseudo */ |
17818 | | brtarget_mm, |
17819 | | /* BeqImm */ |
17820 | | GPR32Opnd, imm64, brtarget, |
17821 | | /* BneImm */ |
17822 | | GPR32Opnd, imm64, brtarget, |
17823 | | /* BteqzT8CmpX16 */ |
17824 | | CPU16Regs, CPU16Regs, brtarget, |
17825 | | /* BteqzT8CmpiX16 */ |
17826 | | CPU16Regs, simm16, brtarget, |
17827 | | /* BteqzT8SltX16 */ |
17828 | | CPU16Regs, CPU16Regs, brtarget, |
17829 | | /* BteqzT8SltiX16 */ |
17830 | | CPU16Regs, simm16, brtarget, |
17831 | | /* BteqzT8SltiuX16 */ |
17832 | | CPU16Regs, simm16, brtarget, |
17833 | | /* BteqzT8SltuX16 */ |
17834 | | CPU16Regs, CPU16Regs, brtarget, |
17835 | | /* BtnezT8CmpX16 */ |
17836 | | CPU16Regs, CPU16Regs, brtarget, |
17837 | | /* BtnezT8CmpiX16 */ |
17838 | | CPU16Regs, simm16, brtarget, |
17839 | | /* BtnezT8SltX16 */ |
17840 | | CPU16Regs, CPU16Regs, brtarget, |
17841 | | /* BtnezT8SltiX16 */ |
17842 | | CPU16Regs, simm16, brtarget, |
17843 | | /* BtnezT8SltiuX16 */ |
17844 | | CPU16Regs, simm16, brtarget, |
17845 | | /* BtnezT8SltuX16 */ |
17846 | | CPU16Regs, CPU16Regs, brtarget, |
17847 | | /* BuildPairF64 */ |
17848 | | AFGR64Opnd, GPR32Opnd, GPR32Opnd, |
17849 | | /* BuildPairF64_64 */ |
17850 | | FGR64Opnd, GPR32Opnd, GPR32Opnd, |
17851 | | /* CFTC1 */ |
17852 | | GPR32Opnd, FGRCCOpnd, |
17853 | | /* CONSTPOOL_ENTRY */ |
17854 | | cpinst_operand, cpinst_operand, i32imm, |
17855 | | /* COPY_FD_PSEUDO */ |
17856 | | FGR64, MSA128D, uimm1_ptr, |
17857 | | /* COPY_FW_PSEUDO */ |
17858 | | FGR32, MSA128W, uimm2_ptr, |
17859 | | /* CTTC1 */ |
17860 | | FGRCCOpnd, GPR32Opnd, |
17861 | | /* Constant32 */ |
17862 | | simm32, |
17863 | | /* DMULImmMacro */ |
17864 | | GPR64Opnd, GPR64Opnd, simm32_relaxed, |
17865 | | /* DMULMacro */ |
17866 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17867 | | /* DMULOMacro */ |
17868 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17869 | | /* DMULOUMacro */ |
17870 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17871 | | /* DROL */ |
17872 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
17873 | | /* DROLImm */ |
17874 | | GPR32Opnd, GPR32Opnd, simm16, |
17875 | | /* DROR */ |
17876 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
17877 | | /* DRORImm */ |
17878 | | GPR32Opnd, GPR32Opnd, simm16, |
17879 | | /* DSDivIMacro */ |
17880 | | GPR64Opnd, GPR64Opnd, imm64, |
17881 | | /* DSDivMacro */ |
17882 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17883 | | /* DSRemIMacro */ |
17884 | | GPR64Opnd, GPR64Opnd, simm32_relaxed, |
17885 | | /* DSRemMacro */ |
17886 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17887 | | /* DUDivIMacro */ |
17888 | | GPR64Opnd, GPR64Opnd, imm64, |
17889 | | /* DUDivMacro */ |
17890 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17891 | | /* DURemIMacro */ |
17892 | | GPR64Opnd, GPR64Opnd, simm32_relaxed, |
17893 | | /* DURemMacro */ |
17894 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
17895 | | /* ERet */ |
17896 | | /* ExtractElementF64 */ |
17897 | | GPR32Opnd, AFGR64Opnd, i32imm, |
17898 | | /* ExtractElementF64_64 */ |
17899 | | GPR32Opnd, FGR64Opnd, i32imm, |
17900 | | /* FABS_D */ |
17901 | | MSA128DOpnd, MSA128DOpnd, |
17902 | | /* FABS_W */ |
17903 | | MSA128WOpnd, MSA128WOpnd, |
17904 | | /* FEXP2_D_1_PSEUDO */ |
17905 | | MSA128D, MSA128D, |
17906 | | /* FEXP2_W_1_PSEUDO */ |
17907 | | MSA128W, MSA128W, |
17908 | | /* FILL_FD_PSEUDO */ |
17909 | | MSA128D, FGR64, |
17910 | | /* FILL_FW_PSEUDO */ |
17911 | | MSA128W, FGR32, |
17912 | | /* GotPrologue16 */ |
17913 | | CPU16Regs, CPU16Regs, simm16, simm16, |
17914 | | /* INSERT_B_VIDX64_PSEUDO */ |
17915 | | MSA128BOpnd, MSA128BOpnd, GPR64Opnd, GPR32Opnd, |
17916 | | /* INSERT_B_VIDX_PSEUDO */ |
17917 | | MSA128BOpnd, MSA128BOpnd, GPR32Opnd, GPR32Opnd, |
17918 | | /* INSERT_D_VIDX64_PSEUDO */ |
17919 | | MSA128DOpnd, MSA128DOpnd, GPR64Opnd, GPR64Opnd, |
17920 | | /* INSERT_D_VIDX_PSEUDO */ |
17921 | | MSA128DOpnd, MSA128DOpnd, GPR32Opnd, GPR64Opnd, |
17922 | | /* INSERT_FD_PSEUDO */ |
17923 | | MSA128DOpnd, MSA128DOpnd, uimm1, FGR64Opnd, |
17924 | | /* INSERT_FD_VIDX64_PSEUDO */ |
17925 | | MSA128DOpnd, MSA128DOpnd, GPR64Opnd, FGR64Opnd, |
17926 | | /* INSERT_FD_VIDX_PSEUDO */ |
17927 | | MSA128DOpnd, MSA128DOpnd, GPR32Opnd, FGR64Opnd, |
17928 | | /* INSERT_FW_PSEUDO */ |
17929 | | MSA128WOpnd, MSA128WOpnd, uimm2, FGR32Opnd, |
17930 | | /* INSERT_FW_VIDX64_PSEUDO */ |
17931 | | MSA128WOpnd, MSA128WOpnd, GPR64Opnd, FGR32Opnd, |
17932 | | /* INSERT_FW_VIDX_PSEUDO */ |
17933 | | MSA128WOpnd, MSA128WOpnd, GPR32Opnd, FGR32Opnd, |
17934 | | /* INSERT_H_VIDX64_PSEUDO */ |
17935 | | MSA128HOpnd, MSA128HOpnd, GPR64Opnd, GPR32Opnd, |
17936 | | /* INSERT_H_VIDX_PSEUDO */ |
17937 | | MSA128HOpnd, MSA128HOpnd, GPR32Opnd, GPR32Opnd, |
17938 | | /* INSERT_W_VIDX64_PSEUDO */ |
17939 | | MSA128WOpnd, MSA128WOpnd, GPR64Opnd, GPR32Opnd, |
17940 | | /* INSERT_W_VIDX_PSEUDO */ |
17941 | | MSA128WOpnd, MSA128WOpnd, GPR32Opnd, GPR32Opnd, |
17942 | | /* JALR64Pseudo */ |
17943 | | GPR64Opnd, |
17944 | | /* JALRHB64Pseudo */ |
17945 | | GPR64Opnd, |
17946 | | /* JALRHBPseudo */ |
17947 | | GPR32Opnd, |
17948 | | /* JALRPseudo */ |
17949 | | GPR32Opnd, |
17950 | | /* JAL_MMR6 */ |
17951 | | calltarget, |
17952 | | /* JalOneReg */ |
17953 | | GPR32Opnd, |
17954 | | /* JalTwoReg */ |
17955 | | GPR32Opnd, GPR32Opnd, |
17956 | | /* LDMacro */ |
17957 | | GPR32Opnd, -1, simm16, |
17958 | | /* LDR_D */ |
17959 | | MSA128DOpnd, -1, GPR32, |
17960 | | /* LDR_W */ |
17961 | | MSA128WOpnd, -1, GPR32, |
17962 | | /* LD_F16 */ |
17963 | | MSA128F16, -1, simm10, |
17964 | | /* LOAD_ACC128 */ |
17965 | | ACC128, -1, simm16, |
17966 | | /* LOAD_ACC64 */ |
17967 | | ACC64, -1, simm16, |
17968 | | /* LOAD_ACC64DSP */ |
17969 | | ACC64DSPOpnd, -1, simm16, |
17970 | | /* LOAD_CCOND_DSP */ |
17971 | | DSPCC, -1, simm16, |
17972 | | /* LONG_BRANCH_ADDiu */ |
17973 | | GPR32Opnd, GPR32Opnd, brtarget, brtarget, |
17974 | | /* LONG_BRANCH_ADDiu2Op */ |
17975 | | GPR32Opnd, GPR32Opnd, brtarget, |
17976 | | /* LONG_BRANCH_DADDiu */ |
17977 | | GPR64Opnd, GPR64Opnd, brtarget, brtarget, |
17978 | | /* LONG_BRANCH_DADDiu2Op */ |
17979 | | GPR64Opnd, GPR64Opnd, brtarget, |
17980 | | /* LONG_BRANCH_LUi */ |
17981 | | GPR32Opnd, brtarget, brtarget, |
17982 | | /* LONG_BRANCH_LUi2Op */ |
17983 | | GPR32Opnd, brtarget, |
17984 | | /* LONG_BRANCH_LUi2Op_64 */ |
17985 | | GPR64Opnd, brtarget, |
17986 | | /* LWM_MM */ |
17987 | | reglist, -1, simm12, |
17988 | | /* LoadAddrImm32 */ |
17989 | | GPR32Opnd, i32imm, |
17990 | | /* LoadAddrImm64 */ |
17991 | | GPR64Opnd, imm64, |
17992 | | /* LoadAddrReg32 */ |
17993 | | GPR32Opnd, -1, simm16, |
17994 | | /* LoadAddrReg64 */ |
17995 | | GPR64Opnd, -1, simm16, |
17996 | | /* LoadImm32 */ |
17997 | | GPR32Opnd, uimm32_coerced, |
17998 | | /* LoadImm64 */ |
17999 | | GPR64Opnd, imm64, |
18000 | | /* LoadImmDoubleFGR */ |
18001 | | StrictlyFGR64Opnd, imm64, |
18002 | | /* LoadImmDoubleFGR_32 */ |
18003 | | StrictlyAFGR64Opnd, imm64, |
18004 | | /* LoadImmDoubleGPR */ |
18005 | | GPR32Opnd, imm64, |
18006 | | /* LoadImmSingleFGR */ |
18007 | | StrictlyFGR32Opnd, imm64, |
18008 | | /* LoadImmSingleGPR */ |
18009 | | GPR32Opnd, imm64, |
18010 | | /* LwConstant32 */ |
18011 | | CPU16Regs, simm32, simm32, |
18012 | | /* MFTACX */ |
18013 | | GPR32Opnd, ACC64DSPOpnd, |
18014 | | /* MFTC0 */ |
18015 | | GPR32Opnd, COP0Opnd, uimm3, |
18016 | | /* MFTC1 */ |
18017 | | GPR32Opnd, FGR32Opnd, |
18018 | | /* MFTDSP */ |
18019 | | GPR32Opnd, |
18020 | | /* MFTGPR */ |
18021 | | GPR32Opnd, GPR32Opnd, uimm3, |
18022 | | /* MFTHC1 */ |
18023 | | GPR32Opnd, FGR32Opnd, |
18024 | | /* MFTHI */ |
18025 | | GPR32Opnd, ACC64DSPOpnd, |
18026 | | /* MFTLO */ |
18027 | | GPR32Opnd, ACC64DSPOpnd, |
18028 | | /* MIPSeh_return32 */ |
18029 | | GPR32, GPR32, |
18030 | | /* MIPSeh_return64 */ |
18031 | | GPR64, GPR64, |
18032 | | /* MSA_FP_EXTEND_D_PSEUDO */ |
18033 | | FGR64Opnd, MSA128F16, |
18034 | | /* MSA_FP_EXTEND_W_PSEUDO */ |
18035 | | FGR32Opnd, MSA128F16, |
18036 | | /* MSA_FP_ROUND_D_PSEUDO */ |
18037 | | MSA128F16, FGR64Opnd, |
18038 | | /* MSA_FP_ROUND_W_PSEUDO */ |
18039 | | MSA128F16, FGR32Opnd, |
18040 | | /* MTTACX */ |
18041 | | ACC64DSPOpnd, GPR32Opnd, |
18042 | | /* MTTC0 */ |
18043 | | COP0Opnd, GPR32Opnd, uimm3, |
18044 | | /* MTTC1 */ |
18045 | | FGR32Opnd, GPR32Opnd, |
18046 | | /* MTTDSP */ |
18047 | | GPR32Opnd, |
18048 | | /* MTTGPR */ |
18049 | | GPR32Opnd, GPR32Opnd, |
18050 | | /* MTTHC1 */ |
18051 | | FGR32Opnd, GPR32Opnd, |
18052 | | /* MTTHI */ |
18053 | | ACC64DSPOpnd, GPR32Opnd, |
18054 | | /* MTTLO */ |
18055 | | ACC64DSPOpnd, GPR32Opnd, |
18056 | | /* MULImmMacro */ |
18057 | | GPR32Opnd, GPR32Opnd, simm32_relaxed, |
18058 | | /* MULOMacro */ |
18059 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18060 | | /* MULOUMacro */ |
18061 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18062 | | /* MultRxRy16 */ |
18063 | | CPU16Regs, CPU16Regs, |
18064 | | /* MultRxRyRz16 */ |
18065 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18066 | | /* MultuRxRy16 */ |
18067 | | CPU16Regs, CPU16Regs, |
18068 | | /* MultuRxRyRz16 */ |
18069 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18070 | | /* NOP */ |
18071 | | /* NORImm */ |
18072 | | GPR32Opnd, GPR32Opnd, simm32_relaxed, |
18073 | | /* NORImm64 */ |
18074 | | GPR64Opnd, GPR64Opnd, imm64, |
18075 | | /* NOR_V_D_PSEUDO */ |
18076 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18077 | | /* NOR_V_H_PSEUDO */ |
18078 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18079 | | /* NOR_V_W_PSEUDO */ |
18080 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18081 | | /* OR_V_D_PSEUDO */ |
18082 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18083 | | /* OR_V_H_PSEUDO */ |
18084 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18085 | | /* OR_V_W_PSEUDO */ |
18086 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18087 | | /* PseudoCMPU_EQ_QB */ |
18088 | | DSPCC, DSPROpnd, DSPROpnd, |
18089 | | /* PseudoCMPU_LE_QB */ |
18090 | | DSPCC, DSPROpnd, DSPROpnd, |
18091 | | /* PseudoCMPU_LT_QB */ |
18092 | | DSPCC, DSPROpnd, DSPROpnd, |
18093 | | /* PseudoCMP_EQ_PH */ |
18094 | | DSPCC, DSPROpnd, DSPROpnd, |
18095 | | /* PseudoCMP_LE_PH */ |
18096 | | DSPCC, DSPROpnd, DSPROpnd, |
18097 | | /* PseudoCMP_LT_PH */ |
18098 | | DSPCC, DSPROpnd, DSPROpnd, |
18099 | | /* PseudoCVT_D32_W */ |
18100 | | AFGR64Opnd, GPR32Opnd, |
18101 | | /* PseudoCVT_D64_L */ |
18102 | | FGR64Opnd, GPR64Opnd, |
18103 | | /* PseudoCVT_D64_W */ |
18104 | | FGR64Opnd, GPR32Opnd, |
18105 | | /* PseudoCVT_S_L */ |
18106 | | FGR64Opnd, GPR64Opnd, |
18107 | | /* PseudoCVT_S_W */ |
18108 | | FGR32Opnd, GPR32Opnd, |
18109 | | /* PseudoDMULT */ |
18110 | | ACC128, GPR64Opnd, GPR64Opnd, |
18111 | | /* PseudoDMULTu */ |
18112 | | ACC128, GPR64Opnd, GPR64Opnd, |
18113 | | /* PseudoDSDIV */ |
18114 | | ACC128, GPR64Opnd, GPR64Opnd, |
18115 | | /* PseudoDUDIV */ |
18116 | | ACC128, GPR64Opnd, GPR64Opnd, |
18117 | | /* PseudoD_SELECT_I */ |
18118 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18119 | | /* PseudoD_SELECT_I64 */ |
18120 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, |
18121 | | /* PseudoIndirectBranch */ |
18122 | | GPR32Opnd, |
18123 | | /* PseudoIndirectBranch64 */ |
18124 | | GPR64Opnd, |
18125 | | /* PseudoIndirectBranch64R6 */ |
18126 | | GPR64Opnd, |
18127 | | /* PseudoIndirectBranchR6 */ |
18128 | | GPR32Opnd, |
18129 | | /* PseudoIndirectBranch_MM */ |
18130 | | GPR32Opnd, |
18131 | | /* PseudoIndirectBranch_MMR6 */ |
18132 | | GPR32Opnd, |
18133 | | /* PseudoIndirectHazardBranch */ |
18134 | | GPR32Opnd, |
18135 | | /* PseudoIndirectHazardBranch64 */ |
18136 | | GPR64Opnd, |
18137 | | /* PseudoIndrectHazardBranch64R6 */ |
18138 | | GPR64Opnd, |
18139 | | /* PseudoIndrectHazardBranchR6 */ |
18140 | | GPR32Opnd, |
18141 | | /* PseudoMADD */ |
18142 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18143 | | /* PseudoMADDU */ |
18144 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18145 | | /* PseudoMADDU_MM */ |
18146 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18147 | | /* PseudoMADD_MM */ |
18148 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18149 | | /* PseudoMFHI */ |
18150 | | GPR32, ACC64, |
18151 | | /* PseudoMFHI64 */ |
18152 | | GPR64, ACC128, |
18153 | | /* PseudoMFHI_MM */ |
18154 | | GPR32, ACC64, |
18155 | | /* PseudoMFLO */ |
18156 | | GPR32, ACC64, |
18157 | | /* PseudoMFLO64 */ |
18158 | | GPR64, ACC128, |
18159 | | /* PseudoMFLO_MM */ |
18160 | | GPR32, ACC64, |
18161 | | /* PseudoMSUB */ |
18162 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18163 | | /* PseudoMSUBU */ |
18164 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18165 | | /* PseudoMSUBU_MM */ |
18166 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18167 | | /* PseudoMSUB_MM */ |
18168 | | ACC64, GPR32Opnd, GPR32Opnd, ACC64, |
18169 | | /* PseudoMTLOHI */ |
18170 | | ACC64, GPR32, GPR32, |
18171 | | /* PseudoMTLOHI64 */ |
18172 | | ACC128, GPR64, GPR64, |
18173 | | /* PseudoMTLOHI_DSP */ |
18174 | | ACC64DSP, GPR32, GPR32, |
18175 | | /* PseudoMTLOHI_MM */ |
18176 | | ACC64, GPR32, GPR32, |
18177 | | /* PseudoMULT */ |
18178 | | ACC64, GPR32Opnd, GPR32Opnd, |
18179 | | /* PseudoMULT_MM */ |
18180 | | ACC64, GPR32Opnd, GPR32Opnd, |
18181 | | /* PseudoMULTu */ |
18182 | | ACC64, GPR32Opnd, GPR32Opnd, |
18183 | | /* PseudoMULTu_MM */ |
18184 | | ACC64, GPR32Opnd, GPR32Opnd, |
18185 | | /* PseudoPICK_PH */ |
18186 | | DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, |
18187 | | /* PseudoPICK_QB */ |
18188 | | DSPROpnd, DSPCC, DSPROpnd, DSPROpnd, |
18189 | | /* PseudoReturn */ |
18190 | | GPR32Opnd, |
18191 | | /* PseudoReturn64 */ |
18192 | | GPR64Opnd, |
18193 | | /* PseudoSDIV */ |
18194 | | ACC64, GPR32Opnd, GPR32Opnd, |
18195 | | /* PseudoSELECTFP_F_D32 */ |
18196 | | AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
18197 | | /* PseudoSELECTFP_F_D64 */ |
18198 | | FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
18199 | | /* PseudoSELECTFP_F_I */ |
18200 | | GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, |
18201 | | /* PseudoSELECTFP_F_I64 */ |
18202 | | GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, |
18203 | | /* PseudoSELECTFP_F_S */ |
18204 | | FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
18205 | | /* PseudoSELECTFP_T_D32 */ |
18206 | | AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
18207 | | /* PseudoSELECTFP_T_D64 */ |
18208 | | FGR64Opnd, FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
18209 | | /* PseudoSELECTFP_T_I */ |
18210 | | GPR32Opnd, FCCRegsOpnd, GPR32Opnd, GPR32Opnd, |
18211 | | /* PseudoSELECTFP_T_I64 */ |
18212 | | GPR64Opnd, FCCRegsOpnd, GPR64Opnd, GPR64Opnd, |
18213 | | /* PseudoSELECTFP_T_S */ |
18214 | | FGR32Opnd, FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
18215 | | /* PseudoSELECT_D32 */ |
18216 | | AFGR64Opnd, GPR32Opnd, AFGR64Opnd, AFGR64Opnd, |
18217 | | /* PseudoSELECT_D64 */ |
18218 | | FGR64Opnd, GPR32Opnd, FGR64Opnd, FGR64Opnd, |
18219 | | /* PseudoSELECT_I */ |
18220 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18221 | | /* PseudoSELECT_I64 */ |
18222 | | GPR64Opnd, GPR32Opnd, GPR64Opnd, GPR64Opnd, |
18223 | | /* PseudoSELECT_S */ |
18224 | | FGR32Opnd, GPR32Opnd, FGR32Opnd, FGR32Opnd, |
18225 | | /* PseudoTRUNC_W_D */ |
18226 | | FGR32Opnd, FGR64Opnd, GPR32Opnd, |
18227 | | /* PseudoTRUNC_W_D32 */ |
18228 | | FGR32Opnd, AFGR64Opnd, GPR32Opnd, |
18229 | | /* PseudoTRUNC_W_S */ |
18230 | | FGR32Opnd, FGR32Opnd, GPR32Opnd, |
18231 | | /* PseudoUDIV */ |
18232 | | ACC64, GPR32Opnd, GPR32Opnd, |
18233 | | /* ROL */ |
18234 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18235 | | /* ROLImm */ |
18236 | | GPR32Opnd, GPR32Opnd, simm16, |
18237 | | /* ROR */ |
18238 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18239 | | /* RORImm */ |
18240 | | GPR32Opnd, GPR32Opnd, simm16, |
18241 | | /* RetRA */ |
18242 | | /* RetRA16 */ |
18243 | | /* SDC1_M1 */ |
18244 | | AFGR64Opnd, -1, simm16, |
18245 | | /* SDIV_MM_Pseudo */ |
18246 | | ACC64, GPR32Opnd, GPR32Opnd, |
18247 | | /* SDMacro */ |
18248 | | GPR32Opnd, -1, simm16, |
18249 | | /* SDivIMacro */ |
18250 | | GPR32Opnd, GPR32Opnd, simm32, |
18251 | | /* SDivMacro */ |
18252 | | GPR32NonZeroOpnd, GPR32Opnd, GPR32Opnd, |
18253 | | /* SEQIMacro */ |
18254 | | GPR32Opnd, GPR32Opnd, simm32_relaxed, |
18255 | | /* SEQMacro */ |
18256 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18257 | | /* SGE */ |
18258 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18259 | | /* SGEImm */ |
18260 | | GPR32Opnd, GPR32Opnd, simm32, |
18261 | | /* SGEImm64 */ |
18262 | | GPR64Opnd, GPR64Opnd, imm64, |
18263 | | /* SGEU */ |
18264 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18265 | | /* SGEUImm */ |
18266 | | GPR32Opnd, GPR32Opnd, uimm32_coerced, |
18267 | | /* SGEUImm64 */ |
18268 | | GPR64Opnd, GPR64Opnd, imm64, |
18269 | | /* SGTImm */ |
18270 | | GPR32Opnd, GPR32Opnd, simm32, |
18271 | | /* SGTImm64 */ |
18272 | | GPR64Opnd, GPR64Opnd, imm64, |
18273 | | /* SGTUImm */ |
18274 | | GPR32Opnd, GPR32Opnd, uimm32_coerced, |
18275 | | /* SGTUImm64 */ |
18276 | | GPR64Opnd, GPR64Opnd, imm64, |
18277 | | /* SLE */ |
18278 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18279 | | /* SLEImm */ |
18280 | | GPR32Opnd, GPR32Opnd, simm32, |
18281 | | /* SLEImm64 */ |
18282 | | GPR64Opnd, GPR64Opnd, imm64, |
18283 | | /* SLEU */ |
18284 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18285 | | /* SLEUImm */ |
18286 | | GPR32Opnd, GPR32Opnd, uimm32_coerced, |
18287 | | /* SLEUImm64 */ |
18288 | | GPR64Opnd, GPR64Opnd, imm64, |
18289 | | /* SLTImm64 */ |
18290 | | GPR64Opnd, GPR64Opnd, imm64, |
18291 | | /* SLTUImm64 */ |
18292 | | GPR64Opnd, GPR64Opnd, imm64, |
18293 | | /* SNEIMacro */ |
18294 | | GPR32Opnd, GPR32Opnd, simm32_relaxed, |
18295 | | /* SNEMacro */ |
18296 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18297 | | /* SNZ_B_PSEUDO */ |
18298 | | GPR32, MSA128B, |
18299 | | /* SNZ_D_PSEUDO */ |
18300 | | GPR32, MSA128D, |
18301 | | /* SNZ_H_PSEUDO */ |
18302 | | GPR32, MSA128H, |
18303 | | /* SNZ_V_PSEUDO */ |
18304 | | GPR32, MSA128B, |
18305 | | /* SNZ_W_PSEUDO */ |
18306 | | GPR32, MSA128W, |
18307 | | /* SRemIMacro */ |
18308 | | GPR32Opnd, GPR32Opnd, simm32_relaxed, |
18309 | | /* SRemMacro */ |
18310 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18311 | | /* STORE_ACC128 */ |
18312 | | ACC128, -1, simm16, |
18313 | | /* STORE_ACC64 */ |
18314 | | ACC64, -1, simm16, |
18315 | | /* STORE_ACC64DSP */ |
18316 | | ACC64DSPOpnd, -1, simm16, |
18317 | | /* STORE_CCOND_DSP */ |
18318 | | DSPCC, -1, simm16, |
18319 | | /* STR_D */ |
18320 | | MSA128DOpnd, -1, GPR32, |
18321 | | /* STR_W */ |
18322 | | MSA128WOpnd, -1, GPR32, |
18323 | | /* ST_F16 */ |
18324 | | MSA128F16, -1, simm10, |
18325 | | /* SWM_MM */ |
18326 | | reglist, -1, simm12, |
18327 | | /* SZ_B_PSEUDO */ |
18328 | | GPR32, MSA128B, |
18329 | | /* SZ_D_PSEUDO */ |
18330 | | GPR32, MSA128D, |
18331 | | /* SZ_H_PSEUDO */ |
18332 | | GPR32, MSA128H, |
18333 | | /* SZ_V_PSEUDO */ |
18334 | | GPR32, MSA128B, |
18335 | | /* SZ_W_PSEUDO */ |
18336 | | GPR32, MSA128W, |
18337 | | /* SaaAddr */ |
18338 | | GPR64Opnd, -1, simm16, |
18339 | | /* SaadAddr */ |
18340 | | GPR64Opnd, -1, simm16, |
18341 | | /* SelBeqZ */ |
18342 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18343 | | /* SelBneZ */ |
18344 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18345 | | /* SelTBteqZCmp */ |
18346 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18347 | | /* SelTBteqZCmpi */ |
18348 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
18349 | | /* SelTBteqZSlt */ |
18350 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18351 | | /* SelTBteqZSlti */ |
18352 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
18353 | | /* SelTBteqZSltiu */ |
18354 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
18355 | | /* SelTBteqZSltu */ |
18356 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18357 | | /* SelTBtneZCmp */ |
18358 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18359 | | /* SelTBtneZCmpi */ |
18360 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
18361 | | /* SelTBtneZSlt */ |
18362 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18363 | | /* SelTBtneZSlti */ |
18364 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
18365 | | /* SelTBtneZSltiu */ |
18366 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, simm16, |
18367 | | /* SelTBtneZSltu */ |
18368 | | CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, CPU16Regs, |
18369 | | /* SltCCRxRy16 */ |
18370 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18371 | | /* SltiCCRxImmX16 */ |
18372 | | CPU16Regs, CPU16Regs, simm16, |
18373 | | /* SltiuCCRxImmX16 */ |
18374 | | CPU16Regs, CPU16Regs, simm16, |
18375 | | /* SltuCCRxRy16 */ |
18376 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18377 | | /* SltuRxRyRz16 */ |
18378 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18379 | | /* TAILCALL */ |
18380 | | calltarget, |
18381 | | /* TAILCALL64R6REG */ |
18382 | | GPR64Opnd, |
18383 | | /* TAILCALLHB64R6REG */ |
18384 | | GPR64Opnd, |
18385 | | /* TAILCALLHBR6REG */ |
18386 | | GPR32Opnd, |
18387 | | /* TAILCALLR6REG */ |
18388 | | GPR32Opnd, |
18389 | | /* TAILCALLREG */ |
18390 | | GPR32Opnd, |
18391 | | /* TAILCALLREG64 */ |
18392 | | GPR64Opnd, |
18393 | | /* TAILCALLREGHB */ |
18394 | | GPR32Opnd, |
18395 | | /* TAILCALLREGHB64 */ |
18396 | | GPR64Opnd, |
18397 | | /* TAILCALLREG_MM */ |
18398 | | GPR32Opnd, |
18399 | | /* TAILCALLREG_MMR6 */ |
18400 | | GPR32Opnd, |
18401 | | /* TAILCALL_MM */ |
18402 | | calltarget, |
18403 | | /* TAILCALL_MMR6 */ |
18404 | | calltarget, |
18405 | | /* TRAP */ |
18406 | | /* TRAP_MM */ |
18407 | | /* UDIV_MM_Pseudo */ |
18408 | | ACC64, GPR32Opnd, GPR32Opnd, |
18409 | | /* UDivIMacro */ |
18410 | | GPR32Opnd, GPR32Opnd, simm32, |
18411 | | /* UDivMacro */ |
18412 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18413 | | /* URemIMacro */ |
18414 | | GPR32Opnd, GPR32Opnd, simm32_relaxed, |
18415 | | /* URemMacro */ |
18416 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18417 | | /* Ulh */ |
18418 | | GPR32Opnd, -1, simm16, |
18419 | | /* Ulhu */ |
18420 | | GPR32Opnd, -1, simm16, |
18421 | | /* Ulw */ |
18422 | | GPR32Opnd, -1, simm16, |
18423 | | /* Ush */ |
18424 | | GPR32Opnd, -1, simm16, |
18425 | | /* Usw */ |
18426 | | GPR32Opnd, -1, simm16, |
18427 | | /* XOR_V_D_PSEUDO */ |
18428 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18429 | | /* XOR_V_H_PSEUDO */ |
18430 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18431 | | /* XOR_V_W_PSEUDO */ |
18432 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18433 | | /* ABSQ_S_PH */ |
18434 | | DSPROpnd, DSPROpnd, |
18435 | | /* ABSQ_S_PH_MM */ |
18436 | | DSPROpnd, DSPROpnd, |
18437 | | /* ABSQ_S_QB */ |
18438 | | DSPROpnd, DSPROpnd, |
18439 | | /* ABSQ_S_QB_MMR2 */ |
18440 | | DSPROpnd, DSPROpnd, |
18441 | | /* ABSQ_S_W */ |
18442 | | GPR32Opnd, GPR32Opnd, |
18443 | | /* ABSQ_S_W_MM */ |
18444 | | GPR32Opnd, GPR32Opnd, |
18445 | | /* ADD */ |
18446 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18447 | | /* ADDIUPC */ |
18448 | | GPR32Opnd, simm19_lsl2, |
18449 | | /* ADDIUPC_MM */ |
18450 | | GPRMM16Opnd, simm23_lsl2, |
18451 | | /* ADDIUPC_MMR6 */ |
18452 | | GPR32Opnd, simm19_lsl2, |
18453 | | /* ADDIUR1SP_MM */ |
18454 | | GPRMM16Opnd, uimm6_lsl2, |
18455 | | /* ADDIUR2_MM */ |
18456 | | GPRMM16Opnd, GPRMM16Opnd, simm3_lsa2, |
18457 | | /* ADDIUS5_MM */ |
18458 | | GPR32Opnd, GPR32Opnd, simm4, |
18459 | | /* ADDIUSP_MM */ |
18460 | | simm9_addiusp, |
18461 | | /* ADDIU_MMR6 */ |
18462 | | GPR32Opnd, GPR32Opnd, simm16, |
18463 | | /* ADDQH_PH */ |
18464 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18465 | | /* ADDQH_PH_MMR2 */ |
18466 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18467 | | /* ADDQH_R_PH */ |
18468 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18469 | | /* ADDQH_R_PH_MMR2 */ |
18470 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18471 | | /* ADDQH_R_W */ |
18472 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18473 | | /* ADDQH_R_W_MMR2 */ |
18474 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18475 | | /* ADDQH_W */ |
18476 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18477 | | /* ADDQH_W_MMR2 */ |
18478 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18479 | | /* ADDQ_PH */ |
18480 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18481 | | /* ADDQ_PH_MM */ |
18482 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18483 | | /* ADDQ_S_PH */ |
18484 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18485 | | /* ADDQ_S_PH_MM */ |
18486 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18487 | | /* ADDQ_S_W */ |
18488 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18489 | | /* ADDQ_S_W_MM */ |
18490 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18491 | | /* ADDR_PS64 */ |
18492 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
18493 | | /* ADDSC */ |
18494 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18495 | | /* ADDSC_MM */ |
18496 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18497 | | /* ADDS_A_B */ |
18498 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18499 | | /* ADDS_A_D */ |
18500 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18501 | | /* ADDS_A_H */ |
18502 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18503 | | /* ADDS_A_W */ |
18504 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18505 | | /* ADDS_S_B */ |
18506 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18507 | | /* ADDS_S_D */ |
18508 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18509 | | /* ADDS_S_H */ |
18510 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18511 | | /* ADDS_S_W */ |
18512 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18513 | | /* ADDS_U_B */ |
18514 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18515 | | /* ADDS_U_D */ |
18516 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18517 | | /* ADDS_U_H */ |
18518 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18519 | | /* ADDS_U_W */ |
18520 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18521 | | /* ADDU16_MM */ |
18522 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
18523 | | /* ADDU16_MMR6 */ |
18524 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
18525 | | /* ADDUH_QB */ |
18526 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18527 | | /* ADDUH_QB_MMR2 */ |
18528 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18529 | | /* ADDUH_R_QB */ |
18530 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18531 | | /* ADDUH_R_QB_MMR2 */ |
18532 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18533 | | /* ADDU_MMR6 */ |
18534 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18535 | | /* ADDU_PH */ |
18536 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18537 | | /* ADDU_PH_MMR2 */ |
18538 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18539 | | /* ADDU_QB */ |
18540 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18541 | | /* ADDU_QB_MM */ |
18542 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18543 | | /* ADDU_S_PH */ |
18544 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18545 | | /* ADDU_S_PH_MMR2 */ |
18546 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18547 | | /* ADDU_S_QB */ |
18548 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18549 | | /* ADDU_S_QB_MM */ |
18550 | | DSPROpnd, DSPROpnd, DSPROpnd, |
18551 | | /* ADDVI_B */ |
18552 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
18553 | | /* ADDVI_D */ |
18554 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
18555 | | /* ADDVI_H */ |
18556 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
18557 | | /* ADDVI_W */ |
18558 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
18559 | | /* ADDV_B */ |
18560 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18561 | | /* ADDV_D */ |
18562 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18563 | | /* ADDV_H */ |
18564 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18565 | | /* ADDV_W */ |
18566 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18567 | | /* ADDWC */ |
18568 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18569 | | /* ADDWC_MM */ |
18570 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18571 | | /* ADD_A_B */ |
18572 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18573 | | /* ADD_A_D */ |
18574 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18575 | | /* ADD_A_H */ |
18576 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18577 | | /* ADD_A_W */ |
18578 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18579 | | /* ADD_MM */ |
18580 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18581 | | /* ADD_MMR6 */ |
18582 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18583 | | /* ADDi */ |
18584 | | GPR32Opnd, GPR32Opnd, simm16_relaxed, |
18585 | | /* ADDi_MM */ |
18586 | | GPR32Opnd, GPR32Opnd, simm16, |
18587 | | /* ADDiu */ |
18588 | | GPR32Opnd, GPR32Opnd, simm16_relaxed, |
18589 | | /* ADDiu_MM */ |
18590 | | GPR32Opnd, GPR32Opnd, simm16, |
18591 | | /* ADDu */ |
18592 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18593 | | /* ADDu_MM */ |
18594 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18595 | | /* ALIGN */ |
18596 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, |
18597 | | /* ALIGN_MMR6 */ |
18598 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2, |
18599 | | /* ALUIPC */ |
18600 | | GPR32Opnd, simm16, |
18601 | | /* ALUIPC_MMR6 */ |
18602 | | GPR32Opnd, simm16, |
18603 | | /* AND */ |
18604 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18605 | | /* AND16_MM */ |
18606 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
18607 | | /* AND16_MMR6 */ |
18608 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
18609 | | /* AND64 */ |
18610 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
18611 | | /* ANDI16_MM */ |
18612 | | GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, |
18613 | | /* ANDI16_MMR6 */ |
18614 | | GPRMM16Opnd, GPRMM16Opnd, uimm4_andi, |
18615 | | /* ANDI_B */ |
18616 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
18617 | | /* ANDI_MMR6 */ |
18618 | | GPR32Opnd, GPR32Opnd, uimm16, |
18619 | | /* AND_MM */ |
18620 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18621 | | /* AND_MMR6 */ |
18622 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
18623 | | /* AND_V */ |
18624 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18625 | | /* ANDi */ |
18626 | | GPR32Opnd, GPR32Opnd, uimm16, |
18627 | | /* ANDi64 */ |
18628 | | GPR64Opnd, GPR64Opnd, uimm16_64, |
18629 | | /* ANDi_MM */ |
18630 | | GPR32Opnd, GPR32Opnd, uimm16, |
18631 | | /* APPEND */ |
18632 | | GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
18633 | | /* APPEND_MMR2 */ |
18634 | | GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
18635 | | /* ASUB_S_B */ |
18636 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18637 | | /* ASUB_S_D */ |
18638 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18639 | | /* ASUB_S_H */ |
18640 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18641 | | /* ASUB_S_W */ |
18642 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18643 | | /* ASUB_U_B */ |
18644 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18645 | | /* ASUB_U_D */ |
18646 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18647 | | /* ASUB_U_H */ |
18648 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18649 | | /* ASUB_U_W */ |
18650 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18651 | | /* AUI */ |
18652 | | GPR32Opnd, GPR32Opnd, uimm16, |
18653 | | /* AUIPC */ |
18654 | | GPR32Opnd, simm16, |
18655 | | /* AUIPC_MMR6 */ |
18656 | | GPR32Opnd, simm16, |
18657 | | /* AUI_MMR6 */ |
18658 | | GPR32Opnd, GPR32Opnd, uimm16, |
18659 | | /* AVER_S_B */ |
18660 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18661 | | /* AVER_S_D */ |
18662 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18663 | | /* AVER_S_H */ |
18664 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18665 | | /* AVER_S_W */ |
18666 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18667 | | /* AVER_U_B */ |
18668 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18669 | | /* AVER_U_D */ |
18670 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18671 | | /* AVER_U_H */ |
18672 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18673 | | /* AVER_U_W */ |
18674 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18675 | | /* AVE_S_B */ |
18676 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18677 | | /* AVE_S_D */ |
18678 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18679 | | /* AVE_S_H */ |
18680 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18681 | | /* AVE_S_W */ |
18682 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18683 | | /* AVE_U_B */ |
18684 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18685 | | /* AVE_U_D */ |
18686 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18687 | | /* AVE_U_H */ |
18688 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18689 | | /* AVE_U_W */ |
18690 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18691 | | /* AddiuRxImmX16 */ |
18692 | | CPU16Regs, simm16, |
18693 | | /* AddiuRxPcImmX16 */ |
18694 | | CPU16Regs, simm16, |
18695 | | /* AddiuRxRxImm16 */ |
18696 | | CPU16Regs, CPU16Regs, simm16, |
18697 | | /* AddiuRxRxImmX16 */ |
18698 | | CPU16Regs, CPU16Regs, simm16, |
18699 | | /* AddiuRxRyOffMemX16 */ |
18700 | | CPU16Regs, CPU16RegsPlusSP, simm16, |
18701 | | /* AddiuSpImm16 */ |
18702 | | simm16, |
18703 | | /* AddiuSpImmX16 */ |
18704 | | simm16, |
18705 | | /* AdduRxRyRz16 */ |
18706 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18707 | | /* AndRxRxRy16 */ |
18708 | | CPU16Regs, CPU16Regs, CPU16Regs, |
18709 | | /* B16_MM */ |
18710 | | brtarget10_mm, |
18711 | | /* BADDu */ |
18712 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
18713 | | /* BAL */ |
18714 | | brtarget, |
18715 | | /* BALC */ |
18716 | | brtarget26, |
18717 | | /* BALC_MMR6 */ |
18718 | | brtarget26_mm, |
18719 | | /* BALIGN */ |
18720 | | GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, |
18721 | | /* BALIGN_MMR2 */ |
18722 | | GPR32Opnd, GPR32Opnd, uimm2, GPR32Opnd, |
18723 | | /* BBIT0 */ |
18724 | | GPR64Opnd, uimm5_64_report_uimm6, brtarget, |
18725 | | /* BBIT032 */ |
18726 | | GPR64Opnd, uimm5_64, brtarget, |
18727 | | /* BBIT1 */ |
18728 | | GPR64Opnd, uimm5_64_report_uimm6, brtarget, |
18729 | | /* BBIT132 */ |
18730 | | GPR64Opnd, uimm5_64, brtarget, |
18731 | | /* BC */ |
18732 | | brtarget26, |
18733 | | /* BC16_MMR6 */ |
18734 | | brtarget10_mm, |
18735 | | /* BC1EQZ */ |
18736 | | FGR64Opnd, brtarget, |
18737 | | /* BC1EQZC_MMR6 */ |
18738 | | FGR64Opnd, brtarget_mm, |
18739 | | /* BC1F */ |
18740 | | FCCRegsOpnd, brtarget, |
18741 | | /* BC1FL */ |
18742 | | FCCRegsOpnd, brtarget, |
18743 | | /* BC1F_MM */ |
18744 | | FCCRegsOpnd, brtarget_mm, |
18745 | | /* BC1NEZ */ |
18746 | | FGR64Opnd, brtarget, |
18747 | | /* BC1NEZC_MMR6 */ |
18748 | | FGR64Opnd, brtarget_mm, |
18749 | | /* BC1T */ |
18750 | | FCCRegsOpnd, brtarget, |
18751 | | /* BC1TL */ |
18752 | | FCCRegsOpnd, brtarget, |
18753 | | /* BC1T_MM */ |
18754 | | FCCRegsOpnd, brtarget_mm, |
18755 | | /* BC2EQZ */ |
18756 | | COP2Opnd, brtarget, |
18757 | | /* BC2EQZC_MMR6 */ |
18758 | | COP2Opnd, brtarget_mm, |
18759 | | /* BC2NEZ */ |
18760 | | COP2Opnd, brtarget, |
18761 | | /* BC2NEZC_MMR6 */ |
18762 | | COP2Opnd, brtarget_mm, |
18763 | | /* BCLRI_B */ |
18764 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
18765 | | /* BCLRI_D */ |
18766 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
18767 | | /* BCLRI_H */ |
18768 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
18769 | | /* BCLRI_W */ |
18770 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
18771 | | /* BCLR_B */ |
18772 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18773 | | /* BCLR_D */ |
18774 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18775 | | /* BCLR_H */ |
18776 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18777 | | /* BCLR_W */ |
18778 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18779 | | /* BC_MMR6 */ |
18780 | | brtarget26_mm, |
18781 | | /* BEQ */ |
18782 | | GPR32Opnd, GPR32Opnd, brtarget, |
18783 | | /* BEQ64 */ |
18784 | | GPR64Opnd, GPR64Opnd, brtarget, |
18785 | | /* BEQC */ |
18786 | | GPR32Opnd, GPR32Opnd, brtarget, |
18787 | | /* BEQC64 */ |
18788 | | GPR64Opnd, GPR64Opnd, brtarget, |
18789 | | /* BEQC_MMR6 */ |
18790 | | GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
18791 | | /* BEQL */ |
18792 | | GPR32Opnd, GPR32Opnd, brtarget, |
18793 | | /* BEQZ16_MM */ |
18794 | | GPRMM16Opnd, brtarget7_mm, |
18795 | | /* BEQZALC */ |
18796 | | GPR32Opnd, brtarget, |
18797 | | /* BEQZALC_MMR6 */ |
18798 | | GPR32Opnd, brtarget_mm, |
18799 | | /* BEQZC */ |
18800 | | GPR32Opnd, brtarget21, |
18801 | | /* BEQZC16_MMR6 */ |
18802 | | GPRMM16Opnd, brtarget7_mm, |
18803 | | /* BEQZC64 */ |
18804 | | GPR64Opnd, brtarget21, |
18805 | | /* BEQZC_MM */ |
18806 | | GPR32Opnd, brtarget_mm, |
18807 | | /* BEQZC_MMR6 */ |
18808 | | GPR32Opnd, brtarget21_mm, |
18809 | | /* BEQ_MM */ |
18810 | | GPR32Opnd, GPR32Opnd, brtarget_mm, |
18811 | | /* BGEC */ |
18812 | | GPR32Opnd, GPR32Opnd, brtarget, |
18813 | | /* BGEC64 */ |
18814 | | GPR64Opnd, GPR64Opnd, brtarget, |
18815 | | /* BGEC_MMR6 */ |
18816 | | GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
18817 | | /* BGEUC */ |
18818 | | GPR32Opnd, GPR32Opnd, brtarget, |
18819 | | /* BGEUC64 */ |
18820 | | GPR64Opnd, GPR64Opnd, brtarget, |
18821 | | /* BGEUC_MMR6 */ |
18822 | | GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
18823 | | /* BGEZ */ |
18824 | | GPR32Opnd, brtarget, |
18825 | | /* BGEZ64 */ |
18826 | | GPR64Opnd, brtarget, |
18827 | | /* BGEZAL */ |
18828 | | GPR32Opnd, brtarget, |
18829 | | /* BGEZALC */ |
18830 | | GPR32Opnd, brtarget, |
18831 | | /* BGEZALC_MMR6 */ |
18832 | | GPR32Opnd, brtarget_mm, |
18833 | | /* BGEZALL */ |
18834 | | GPR32Opnd, brtarget, |
18835 | | /* BGEZALS_MM */ |
18836 | | GPR32Opnd, brtarget_mm, |
18837 | | /* BGEZAL_MM */ |
18838 | | GPR32Opnd, brtarget_mm, |
18839 | | /* BGEZC */ |
18840 | | GPR32Opnd, brtarget, |
18841 | | /* BGEZC64 */ |
18842 | | GPR64Opnd, brtarget, |
18843 | | /* BGEZC_MMR6 */ |
18844 | | GPR32Opnd, brtarget_lsl2_mm, |
18845 | | /* BGEZL */ |
18846 | | GPR32Opnd, brtarget, |
18847 | | /* BGEZ_MM */ |
18848 | | GPR32Opnd, brtarget_mm, |
18849 | | /* BGTZ */ |
18850 | | GPR32Opnd, brtarget, |
18851 | | /* BGTZ64 */ |
18852 | | GPR64Opnd, brtarget, |
18853 | | /* BGTZALC */ |
18854 | | GPR32Opnd, brtarget, |
18855 | | /* BGTZALC_MMR6 */ |
18856 | | GPR32Opnd, brtarget_mm, |
18857 | | /* BGTZC */ |
18858 | | GPR32Opnd, brtarget, |
18859 | | /* BGTZC64 */ |
18860 | | GPR64Opnd, brtarget, |
18861 | | /* BGTZC_MMR6 */ |
18862 | | GPR32Opnd, brtarget_lsl2_mm, |
18863 | | /* BGTZL */ |
18864 | | GPR32Opnd, brtarget, |
18865 | | /* BGTZ_MM */ |
18866 | | GPR32Opnd, brtarget_mm, |
18867 | | /* BINSLI_B */ |
18868 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
18869 | | /* BINSLI_D */ |
18870 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
18871 | | /* BINSLI_H */ |
18872 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
18873 | | /* BINSLI_W */ |
18874 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
18875 | | /* BINSL_B */ |
18876 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18877 | | /* BINSL_D */ |
18878 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18879 | | /* BINSL_H */ |
18880 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18881 | | /* BINSL_W */ |
18882 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18883 | | /* BINSRI_B */ |
18884 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
18885 | | /* BINSRI_D */ |
18886 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
18887 | | /* BINSRI_H */ |
18888 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
18889 | | /* BINSRI_W */ |
18890 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
18891 | | /* BINSR_B */ |
18892 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18893 | | /* BINSR_D */ |
18894 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18895 | | /* BINSR_H */ |
18896 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18897 | | /* BINSR_W */ |
18898 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18899 | | /* BITREV */ |
18900 | | GPR32Opnd, GPR32Opnd, |
18901 | | /* BITREV_MM */ |
18902 | | GPR32Opnd, GPR32Opnd, |
18903 | | /* BITSWAP */ |
18904 | | GPR32Opnd, GPR32Opnd, |
18905 | | /* BITSWAP_MMR6 */ |
18906 | | GPR32Opnd, GPR32Opnd, |
18907 | | /* BLEZ */ |
18908 | | GPR32Opnd, brtarget, |
18909 | | /* BLEZ64 */ |
18910 | | GPR64Opnd, brtarget, |
18911 | | /* BLEZALC */ |
18912 | | GPR32Opnd, brtarget, |
18913 | | /* BLEZALC_MMR6 */ |
18914 | | GPR32Opnd, brtarget_mm, |
18915 | | /* BLEZC */ |
18916 | | GPR32Opnd, brtarget, |
18917 | | /* BLEZC64 */ |
18918 | | GPR64Opnd, brtarget, |
18919 | | /* BLEZC_MMR6 */ |
18920 | | GPR32Opnd, brtarget_lsl2_mm, |
18921 | | /* BLEZL */ |
18922 | | GPR32Opnd, brtarget, |
18923 | | /* BLEZ_MM */ |
18924 | | GPR32Opnd, brtarget_mm, |
18925 | | /* BLTC */ |
18926 | | GPR32Opnd, GPR32Opnd, brtarget, |
18927 | | /* BLTC64 */ |
18928 | | GPR64Opnd, GPR64Opnd, brtarget, |
18929 | | /* BLTC_MMR6 */ |
18930 | | GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
18931 | | /* BLTUC */ |
18932 | | GPR32Opnd, GPR32Opnd, brtarget, |
18933 | | /* BLTUC64 */ |
18934 | | GPR64Opnd, GPR64Opnd, brtarget, |
18935 | | /* BLTUC_MMR6 */ |
18936 | | GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
18937 | | /* BLTZ */ |
18938 | | GPR32Opnd, brtarget, |
18939 | | /* BLTZ64 */ |
18940 | | GPR64Opnd, brtarget, |
18941 | | /* BLTZAL */ |
18942 | | GPR32Opnd, brtarget, |
18943 | | /* BLTZALC */ |
18944 | | GPR32Opnd, brtarget, |
18945 | | /* BLTZALC_MMR6 */ |
18946 | | GPR32Opnd, brtarget_mm, |
18947 | | /* BLTZALL */ |
18948 | | GPR32Opnd, brtarget, |
18949 | | /* BLTZALS_MM */ |
18950 | | GPR32Opnd, brtarget_mm, |
18951 | | /* BLTZAL_MM */ |
18952 | | GPR32Opnd, brtarget_mm, |
18953 | | /* BLTZC */ |
18954 | | GPR32Opnd, brtarget, |
18955 | | /* BLTZC64 */ |
18956 | | GPR64Opnd, brtarget, |
18957 | | /* BLTZC_MMR6 */ |
18958 | | GPR32Opnd, brtarget_lsl2_mm, |
18959 | | /* BLTZL */ |
18960 | | GPR32Opnd, brtarget, |
18961 | | /* BLTZ_MM */ |
18962 | | GPR32Opnd, brtarget_mm, |
18963 | | /* BMNZI_B */ |
18964 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
18965 | | /* BMNZ_V */ |
18966 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18967 | | /* BMZI_B */ |
18968 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
18969 | | /* BMZ_V */ |
18970 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18971 | | /* BNE */ |
18972 | | GPR32Opnd, GPR32Opnd, brtarget, |
18973 | | /* BNE64 */ |
18974 | | GPR64Opnd, GPR64Opnd, brtarget, |
18975 | | /* BNEC */ |
18976 | | GPR32Opnd, GPR32Opnd, brtarget, |
18977 | | /* BNEC64 */ |
18978 | | GPR64Opnd, GPR64Opnd, brtarget, |
18979 | | /* BNEC_MMR6 */ |
18980 | | GPR32Opnd, GPR32Opnd, brtarget_lsl2_mm, |
18981 | | /* BNEGI_B */ |
18982 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
18983 | | /* BNEGI_D */ |
18984 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
18985 | | /* BNEGI_H */ |
18986 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
18987 | | /* BNEGI_W */ |
18988 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
18989 | | /* BNEG_B */ |
18990 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
18991 | | /* BNEG_D */ |
18992 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
18993 | | /* BNEG_H */ |
18994 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
18995 | | /* BNEG_W */ |
18996 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
18997 | | /* BNEL */ |
18998 | | GPR32Opnd, GPR32Opnd, brtarget, |
18999 | | /* BNEZ16_MM */ |
19000 | | GPRMM16Opnd, brtarget7_mm, |
19001 | | /* BNEZALC */ |
19002 | | GPR32Opnd, brtarget, |
19003 | | /* BNEZALC_MMR6 */ |
19004 | | GPR32Opnd, brtarget_mm, |
19005 | | /* BNEZC */ |
19006 | | GPR32Opnd, brtarget21, |
19007 | | /* BNEZC16_MMR6 */ |
19008 | | GPRMM16Opnd, brtarget7_mm, |
19009 | | /* BNEZC64 */ |
19010 | | GPR64Opnd, brtarget21, |
19011 | | /* BNEZC_MM */ |
19012 | | GPR32Opnd, brtarget_mm, |
19013 | | /* BNEZC_MMR6 */ |
19014 | | GPR32Opnd, brtarget21_mm, |
19015 | | /* BNE_MM */ |
19016 | | GPR32Opnd, GPR32Opnd, brtarget_mm, |
19017 | | /* BNVC */ |
19018 | | GPR32Opnd, GPR32Opnd, brtarget, |
19019 | | /* BNVC_MMR6 */ |
19020 | | GPR32Opnd, GPR32Opnd, brtargetr6, |
19021 | | /* BNZ_B */ |
19022 | | MSA128BOpnd, brtarget, |
19023 | | /* BNZ_D */ |
19024 | | MSA128DOpnd, brtarget, |
19025 | | /* BNZ_H */ |
19026 | | MSA128HOpnd, brtarget, |
19027 | | /* BNZ_V */ |
19028 | | MSA128BOpnd, brtarget, |
19029 | | /* BNZ_W */ |
19030 | | MSA128WOpnd, brtarget, |
19031 | | /* BOVC */ |
19032 | | GPR32Opnd, GPR32Opnd, brtarget, |
19033 | | /* BOVC_MMR6 */ |
19034 | | GPR32Opnd, GPR32Opnd, brtargetr6, |
19035 | | /* BPOSGE32 */ |
19036 | | brtarget, |
19037 | | /* BPOSGE32C_MMR3 */ |
19038 | | brtarget1SImm16, |
19039 | | /* BPOSGE32_MM */ |
19040 | | brtarget_mm, |
19041 | | /* BREAK */ |
19042 | | uimm10, uimm10, |
19043 | | /* BREAK16_MM */ |
19044 | | uimm4, |
19045 | | /* BREAK16_MMR6 */ |
19046 | | uimm4, |
19047 | | /* BREAK_MM */ |
19048 | | uimm10, uimm10, |
19049 | | /* BREAK_MMR6 */ |
19050 | | uimm10, uimm10, |
19051 | | /* BSELI_B */ |
19052 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
19053 | | /* BSEL_V */ |
19054 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19055 | | /* BSETI_B */ |
19056 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
19057 | | /* BSETI_D */ |
19058 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
19059 | | /* BSETI_H */ |
19060 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
19061 | | /* BSETI_W */ |
19062 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
19063 | | /* BSET_B */ |
19064 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19065 | | /* BSET_D */ |
19066 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19067 | | /* BSET_H */ |
19068 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19069 | | /* BSET_W */ |
19070 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19071 | | /* BZ_B */ |
19072 | | MSA128BOpnd, brtarget, |
19073 | | /* BZ_D */ |
19074 | | MSA128DOpnd, brtarget, |
19075 | | /* BZ_H */ |
19076 | | MSA128HOpnd, brtarget, |
19077 | | /* BZ_V */ |
19078 | | MSA128BOpnd, brtarget, |
19079 | | /* BZ_W */ |
19080 | | MSA128WOpnd, brtarget, |
19081 | | /* BeqzRxImm16 */ |
19082 | | CPU16Regs, brtarget, |
19083 | | /* BeqzRxImmX16 */ |
19084 | | CPU16Regs, brtarget, |
19085 | | /* Bimm16 */ |
19086 | | brtarget, |
19087 | | /* BimmX16 */ |
19088 | | brtarget, |
19089 | | /* BnezRxImm16 */ |
19090 | | CPU16Regs, brtarget, |
19091 | | /* BnezRxImmX16 */ |
19092 | | CPU16Regs, brtarget, |
19093 | | /* Break16 */ |
19094 | | /* Bteqz16 */ |
19095 | | simm16, |
19096 | | /* BteqzX16 */ |
19097 | | simm16, |
19098 | | /* Btnez16 */ |
19099 | | simm16, |
19100 | | /* BtnezX16 */ |
19101 | | simm16, |
19102 | | /* CACHE */ |
19103 | | -1, simm16, uimm5, |
19104 | | /* CACHEE */ |
19105 | | -1, simm9, uimm5, |
19106 | | /* CACHEE_MM */ |
19107 | | -1, simm9, uimm5, |
19108 | | /* CACHE_MM */ |
19109 | | -1, simm12, uimm5, |
19110 | | /* CACHE_MMR6 */ |
19111 | | -1, simm12, uimm5, |
19112 | | /* CACHE_R6 */ |
19113 | | -1, simm9, uimm5, |
19114 | | /* CEIL_L_D64 */ |
19115 | | FGR64Opnd, FGR64Opnd, |
19116 | | /* CEIL_L_D_MMR6 */ |
19117 | | FGR64Opnd, FGR64Opnd, |
19118 | | /* CEIL_L_S */ |
19119 | | FGR64Opnd, FGR32Opnd, |
19120 | | /* CEIL_L_S_MMR6 */ |
19121 | | FGR64Opnd, FGR32Opnd, |
19122 | | /* CEIL_W_D32 */ |
19123 | | FGR32Opnd, AFGR64Opnd, |
19124 | | /* CEIL_W_D64 */ |
19125 | | FGR32Opnd, FGR64Opnd, |
19126 | | /* CEIL_W_D_MMR6 */ |
19127 | | FGR32Opnd, AFGR64Opnd, |
19128 | | /* CEIL_W_MM */ |
19129 | | FGR32Opnd, AFGR64Opnd, |
19130 | | /* CEIL_W_S */ |
19131 | | FGR32Opnd, FGR32Opnd, |
19132 | | /* CEIL_W_S_MM */ |
19133 | | FGR32Opnd, FGR32Opnd, |
19134 | | /* CEIL_W_S_MMR6 */ |
19135 | | FGR32Opnd, FGR32Opnd, |
19136 | | /* CEQI_B */ |
19137 | | MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
19138 | | /* CEQI_D */ |
19139 | | MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
19140 | | /* CEQI_H */ |
19141 | | MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
19142 | | /* CEQI_W */ |
19143 | | MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
19144 | | /* CEQ_B */ |
19145 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19146 | | /* CEQ_D */ |
19147 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19148 | | /* CEQ_H */ |
19149 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19150 | | /* CEQ_W */ |
19151 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19152 | | /* CFC1 */ |
19153 | | GPR32Opnd, CCROpnd, |
19154 | | /* CFC1_MM */ |
19155 | | GPR32Opnd, CCROpnd, |
19156 | | /* CFC2_MM */ |
19157 | | GPR32Opnd, COP2Opnd, |
19158 | | /* CFCMSA */ |
19159 | | GPR32Opnd, MSA128CROpnd, |
19160 | | /* CINS */ |
19161 | | GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
19162 | | /* CINS32 */ |
19163 | | GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
19164 | | /* CINS64_32 */ |
19165 | | GPR64Opnd, GPR32Opnd, uimm5, uimm5, |
19166 | | /* CINS_i32 */ |
19167 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5, |
19168 | | /* CLASS_D */ |
19169 | | FGR64Opnd, FGR64Opnd, |
19170 | | /* CLASS_D_MMR6 */ |
19171 | | FGR64Opnd, FGR64Opnd, |
19172 | | /* CLASS_S */ |
19173 | | FGR32Opnd, FGR32Opnd, |
19174 | | /* CLASS_S_MMR6 */ |
19175 | | FGR32Opnd, FGR32Opnd, |
19176 | | /* CLEI_S_B */ |
19177 | | MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
19178 | | /* CLEI_S_D */ |
19179 | | MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
19180 | | /* CLEI_S_H */ |
19181 | | MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
19182 | | /* CLEI_S_W */ |
19183 | | MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
19184 | | /* CLEI_U_B */ |
19185 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
19186 | | /* CLEI_U_D */ |
19187 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
19188 | | /* CLEI_U_H */ |
19189 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
19190 | | /* CLEI_U_W */ |
19191 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
19192 | | /* CLE_S_B */ |
19193 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19194 | | /* CLE_S_D */ |
19195 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19196 | | /* CLE_S_H */ |
19197 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19198 | | /* CLE_S_W */ |
19199 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19200 | | /* CLE_U_B */ |
19201 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19202 | | /* CLE_U_D */ |
19203 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19204 | | /* CLE_U_H */ |
19205 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19206 | | /* CLE_U_W */ |
19207 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19208 | | /* CLO */ |
19209 | | GPR32Opnd, GPR32Opnd, |
19210 | | /* CLO_MM */ |
19211 | | GPR32Opnd, GPR32Opnd, |
19212 | | /* CLO_MMR6 */ |
19213 | | GPR32Opnd, GPR32Opnd, |
19214 | | /* CLO_R6 */ |
19215 | | GPR32Opnd, GPR32Opnd, |
19216 | | /* CLTI_S_B */ |
19217 | | MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
19218 | | /* CLTI_S_D */ |
19219 | | MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
19220 | | /* CLTI_S_H */ |
19221 | | MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
19222 | | /* CLTI_S_W */ |
19223 | | MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
19224 | | /* CLTI_U_B */ |
19225 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
19226 | | /* CLTI_U_D */ |
19227 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
19228 | | /* CLTI_U_H */ |
19229 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
19230 | | /* CLTI_U_W */ |
19231 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
19232 | | /* CLT_S_B */ |
19233 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19234 | | /* CLT_S_D */ |
19235 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19236 | | /* CLT_S_H */ |
19237 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19238 | | /* CLT_S_W */ |
19239 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19240 | | /* CLT_U_B */ |
19241 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19242 | | /* CLT_U_D */ |
19243 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19244 | | /* CLT_U_H */ |
19245 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19246 | | /* CLT_U_W */ |
19247 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19248 | | /* CLZ */ |
19249 | | GPR32Opnd, GPR32Opnd, |
19250 | | /* CLZ_MM */ |
19251 | | GPR32Opnd, GPR32Opnd, |
19252 | | /* CLZ_MMR6 */ |
19253 | | GPR32Opnd, GPR32Opnd, |
19254 | | /* CLZ_R6 */ |
19255 | | GPR32Opnd, GPR32Opnd, |
19256 | | /* CMPGDU_EQ_QB */ |
19257 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19258 | | /* CMPGDU_EQ_QB_MMR2 */ |
19259 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19260 | | /* CMPGDU_LE_QB */ |
19261 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19262 | | /* CMPGDU_LE_QB_MMR2 */ |
19263 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19264 | | /* CMPGDU_LT_QB */ |
19265 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19266 | | /* CMPGDU_LT_QB_MMR2 */ |
19267 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19268 | | /* CMPGU_EQ_QB */ |
19269 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19270 | | /* CMPGU_EQ_QB_MM */ |
19271 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19272 | | /* CMPGU_LE_QB */ |
19273 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19274 | | /* CMPGU_LE_QB_MM */ |
19275 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19276 | | /* CMPGU_LT_QB */ |
19277 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19278 | | /* CMPGU_LT_QB_MM */ |
19279 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
19280 | | /* CMPU_EQ_QB */ |
19281 | | DSPROpnd, DSPROpnd, |
19282 | | /* CMPU_EQ_QB_MM */ |
19283 | | DSPROpnd, DSPROpnd, |
19284 | | /* CMPU_LE_QB */ |
19285 | | DSPROpnd, DSPROpnd, |
19286 | | /* CMPU_LE_QB_MM */ |
19287 | | DSPROpnd, DSPROpnd, |
19288 | | /* CMPU_LT_QB */ |
19289 | | DSPROpnd, DSPROpnd, |
19290 | | /* CMPU_LT_QB_MM */ |
19291 | | DSPROpnd, DSPROpnd, |
19292 | | /* CMP_AF_D_MMR6 */ |
19293 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19294 | | /* CMP_AF_S_MMR6 */ |
19295 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19296 | | /* CMP_EQ_D */ |
19297 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19298 | | /* CMP_EQ_D_MMR6 */ |
19299 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19300 | | /* CMP_EQ_PH */ |
19301 | | DSPROpnd, DSPROpnd, |
19302 | | /* CMP_EQ_PH_MM */ |
19303 | | DSPROpnd, DSPROpnd, |
19304 | | /* CMP_EQ_S */ |
19305 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19306 | | /* CMP_EQ_S_MMR6 */ |
19307 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19308 | | /* CMP_F_D */ |
19309 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19310 | | /* CMP_F_S */ |
19311 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19312 | | /* CMP_LE_D */ |
19313 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19314 | | /* CMP_LE_D_MMR6 */ |
19315 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19316 | | /* CMP_LE_PH */ |
19317 | | DSPROpnd, DSPROpnd, |
19318 | | /* CMP_LE_PH_MM */ |
19319 | | DSPROpnd, DSPROpnd, |
19320 | | /* CMP_LE_S */ |
19321 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19322 | | /* CMP_LE_S_MMR6 */ |
19323 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19324 | | /* CMP_LT_D */ |
19325 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19326 | | /* CMP_LT_D_MMR6 */ |
19327 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19328 | | /* CMP_LT_PH */ |
19329 | | DSPROpnd, DSPROpnd, |
19330 | | /* CMP_LT_PH_MM */ |
19331 | | DSPROpnd, DSPROpnd, |
19332 | | /* CMP_LT_S */ |
19333 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19334 | | /* CMP_LT_S_MMR6 */ |
19335 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19336 | | /* CMP_SAF_D */ |
19337 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19338 | | /* CMP_SAF_D_MMR6 */ |
19339 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19340 | | /* CMP_SAF_S */ |
19341 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19342 | | /* CMP_SAF_S_MMR6 */ |
19343 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19344 | | /* CMP_SEQ_D */ |
19345 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19346 | | /* CMP_SEQ_D_MMR6 */ |
19347 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19348 | | /* CMP_SEQ_S */ |
19349 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19350 | | /* CMP_SEQ_S_MMR6 */ |
19351 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19352 | | /* CMP_SLE_D */ |
19353 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19354 | | /* CMP_SLE_D_MMR6 */ |
19355 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19356 | | /* CMP_SLE_S */ |
19357 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19358 | | /* CMP_SLE_S_MMR6 */ |
19359 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19360 | | /* CMP_SLT_D */ |
19361 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19362 | | /* CMP_SLT_D_MMR6 */ |
19363 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19364 | | /* CMP_SLT_S */ |
19365 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19366 | | /* CMP_SLT_S_MMR6 */ |
19367 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19368 | | /* CMP_SUEQ_D */ |
19369 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19370 | | /* CMP_SUEQ_D_MMR6 */ |
19371 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19372 | | /* CMP_SUEQ_S */ |
19373 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19374 | | /* CMP_SUEQ_S_MMR6 */ |
19375 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19376 | | /* CMP_SULE_D */ |
19377 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19378 | | /* CMP_SULE_D_MMR6 */ |
19379 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19380 | | /* CMP_SULE_S */ |
19381 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19382 | | /* CMP_SULE_S_MMR6 */ |
19383 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19384 | | /* CMP_SULT_D */ |
19385 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19386 | | /* CMP_SULT_D_MMR6 */ |
19387 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19388 | | /* CMP_SULT_S */ |
19389 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19390 | | /* CMP_SULT_S_MMR6 */ |
19391 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19392 | | /* CMP_SUN_D */ |
19393 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19394 | | /* CMP_SUN_D_MMR6 */ |
19395 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19396 | | /* CMP_SUN_S */ |
19397 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19398 | | /* CMP_SUN_S_MMR6 */ |
19399 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19400 | | /* CMP_UEQ_D */ |
19401 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19402 | | /* CMP_UEQ_D_MMR6 */ |
19403 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19404 | | /* CMP_UEQ_S */ |
19405 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19406 | | /* CMP_UEQ_S_MMR6 */ |
19407 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19408 | | /* CMP_ULE_D */ |
19409 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19410 | | /* CMP_ULE_D_MMR6 */ |
19411 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19412 | | /* CMP_ULE_S */ |
19413 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19414 | | /* CMP_ULE_S_MMR6 */ |
19415 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19416 | | /* CMP_ULT_D */ |
19417 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19418 | | /* CMP_ULT_D_MMR6 */ |
19419 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19420 | | /* CMP_ULT_S */ |
19421 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19422 | | /* CMP_ULT_S_MMR6 */ |
19423 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19424 | | /* CMP_UN_D */ |
19425 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19426 | | /* CMP_UN_D_MMR6 */ |
19427 | | FGRCCOpnd, FGR64Opnd, FGR64Opnd, |
19428 | | /* CMP_UN_S */ |
19429 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19430 | | /* CMP_UN_S_MMR6 */ |
19431 | | FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
19432 | | /* COPY_S_B */ |
19433 | | GPR32Opnd, MSA128BOpnd, uimm4_ptr, |
19434 | | /* COPY_S_D */ |
19435 | | GPR64Opnd, MSA128DOpnd, uimm1_ptr, |
19436 | | /* COPY_S_H */ |
19437 | | GPR32Opnd, MSA128HOpnd, uimm3_ptr, |
19438 | | /* COPY_S_W */ |
19439 | | GPR32Opnd, MSA128WOpnd, uimm2_ptr, |
19440 | | /* COPY_U_B */ |
19441 | | GPR32Opnd, MSA128BOpnd, uimm4_ptr, |
19442 | | /* COPY_U_H */ |
19443 | | GPR32Opnd, MSA128HOpnd, uimm3_ptr, |
19444 | | /* COPY_U_W */ |
19445 | | GPR32Opnd, MSA128WOpnd, uimm2_ptr, |
19446 | | /* CRC32B */ |
19447 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19448 | | /* CRC32CB */ |
19449 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19450 | | /* CRC32CD */ |
19451 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19452 | | /* CRC32CH */ |
19453 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19454 | | /* CRC32CW */ |
19455 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19456 | | /* CRC32D */ |
19457 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19458 | | /* CRC32H */ |
19459 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19460 | | /* CRC32W */ |
19461 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19462 | | /* CTC1 */ |
19463 | | CCROpnd, GPR32Opnd, |
19464 | | /* CTC1_MM */ |
19465 | | CCROpnd, GPR32Opnd, |
19466 | | /* CTC2_MM */ |
19467 | | COP2Opnd, GPR32Opnd, |
19468 | | /* CTCMSA */ |
19469 | | MSA128CROpnd, GPR32Opnd, |
19470 | | /* CVT_D32_S */ |
19471 | | AFGR64Opnd, FGR32Opnd, |
19472 | | /* CVT_D32_S_MM */ |
19473 | | AFGR64Opnd, FGR32Opnd, |
19474 | | /* CVT_D32_W */ |
19475 | | AFGR64Opnd, FGR32Opnd, |
19476 | | /* CVT_D32_W_MM */ |
19477 | | AFGR64Opnd, FGR32Opnd, |
19478 | | /* CVT_D64_L */ |
19479 | | FGR64Opnd, FGR64Opnd, |
19480 | | /* CVT_D64_S */ |
19481 | | FGR64Opnd, FGR32Opnd, |
19482 | | /* CVT_D64_S_MM */ |
19483 | | FGR64Opnd, FGR32Opnd, |
19484 | | /* CVT_D64_W */ |
19485 | | FGR64Opnd, FGR32Opnd, |
19486 | | /* CVT_D64_W_MM */ |
19487 | | FGR64Opnd, FGR32Opnd, |
19488 | | /* CVT_D_L_MMR6 */ |
19489 | | FGR64Opnd, FGR64Opnd, |
19490 | | /* CVT_L_D64 */ |
19491 | | FGR64Opnd, FGR64Opnd, |
19492 | | /* CVT_L_D64_MM */ |
19493 | | FGR64Opnd, FGR64Opnd, |
19494 | | /* CVT_L_D_MMR6 */ |
19495 | | FGR64Opnd, FGR64Opnd, |
19496 | | /* CVT_L_S */ |
19497 | | FGR64Opnd, FGR32Opnd, |
19498 | | /* CVT_L_S_MM */ |
19499 | | FGR64Opnd, FGR32Opnd, |
19500 | | /* CVT_L_S_MMR6 */ |
19501 | | FGR64Opnd, FGR32Opnd, |
19502 | | /* CVT_PS_PW64 */ |
19503 | | FGR64Opnd, FGR64Opnd, |
19504 | | /* CVT_PS_S64 */ |
19505 | | FGR64Opnd, FGR32Opnd, FGR32Opnd, |
19506 | | /* CVT_PW_PS64 */ |
19507 | | FGR64Opnd, FGR64Opnd, |
19508 | | /* CVT_S_D32 */ |
19509 | | FGR32Opnd, AFGR64Opnd, |
19510 | | /* CVT_S_D32_MM */ |
19511 | | FGR32Opnd, AFGR64Opnd, |
19512 | | /* CVT_S_D64 */ |
19513 | | FGR32Opnd, FGR64Opnd, |
19514 | | /* CVT_S_D64_MM */ |
19515 | | FGR32Opnd, FGR64Opnd, |
19516 | | /* CVT_S_L */ |
19517 | | FGR32Opnd, FGR64Opnd, |
19518 | | /* CVT_S_L_MMR6 */ |
19519 | | FGR64Opnd, FGR32Opnd, |
19520 | | /* CVT_S_PL64 */ |
19521 | | FGR32Opnd, FGR64Opnd, |
19522 | | /* CVT_S_PU64 */ |
19523 | | FGR32Opnd, FGR64Opnd, |
19524 | | /* CVT_S_W */ |
19525 | | FGR32Opnd, FGR32Opnd, |
19526 | | /* CVT_S_W_MM */ |
19527 | | FGR32Opnd, FGR32Opnd, |
19528 | | /* CVT_S_W_MMR6 */ |
19529 | | FGR32Opnd, FGR32Opnd, |
19530 | | /* CVT_W_D32 */ |
19531 | | FGR32Opnd, AFGR64Opnd, |
19532 | | /* CVT_W_D32_MM */ |
19533 | | FGR32Opnd, AFGR64Opnd, |
19534 | | /* CVT_W_D64 */ |
19535 | | FGR32Opnd, FGR64Opnd, |
19536 | | /* CVT_W_D64_MM */ |
19537 | | FGR32Opnd, FGR64Opnd, |
19538 | | /* CVT_W_S */ |
19539 | | FGR32Opnd, FGR32Opnd, |
19540 | | /* CVT_W_S_MM */ |
19541 | | FGR32Opnd, FGR32Opnd, |
19542 | | /* CVT_W_S_MMR6 */ |
19543 | | FGR32Opnd, FGR32Opnd, |
19544 | | /* C_EQ_D32 */ |
19545 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19546 | | /* C_EQ_D32_MM */ |
19547 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19548 | | /* C_EQ_D64 */ |
19549 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19550 | | /* C_EQ_D64_MM */ |
19551 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19552 | | /* C_EQ_S */ |
19553 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19554 | | /* C_EQ_S_MM */ |
19555 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19556 | | /* C_F_D32 */ |
19557 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19558 | | /* C_F_D32_MM */ |
19559 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19560 | | /* C_F_D64 */ |
19561 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19562 | | /* C_F_D64_MM */ |
19563 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19564 | | /* C_F_S */ |
19565 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19566 | | /* C_F_S_MM */ |
19567 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19568 | | /* C_LE_D32 */ |
19569 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19570 | | /* C_LE_D32_MM */ |
19571 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19572 | | /* C_LE_D64 */ |
19573 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19574 | | /* C_LE_D64_MM */ |
19575 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19576 | | /* C_LE_S */ |
19577 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19578 | | /* C_LE_S_MM */ |
19579 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19580 | | /* C_LT_D32 */ |
19581 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19582 | | /* C_LT_D32_MM */ |
19583 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19584 | | /* C_LT_D64 */ |
19585 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19586 | | /* C_LT_D64_MM */ |
19587 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19588 | | /* C_LT_S */ |
19589 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19590 | | /* C_LT_S_MM */ |
19591 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19592 | | /* C_NGE_D32 */ |
19593 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19594 | | /* C_NGE_D32_MM */ |
19595 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19596 | | /* C_NGE_D64 */ |
19597 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19598 | | /* C_NGE_D64_MM */ |
19599 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19600 | | /* C_NGE_S */ |
19601 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19602 | | /* C_NGE_S_MM */ |
19603 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19604 | | /* C_NGLE_D32 */ |
19605 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19606 | | /* C_NGLE_D32_MM */ |
19607 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19608 | | /* C_NGLE_D64 */ |
19609 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19610 | | /* C_NGLE_D64_MM */ |
19611 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19612 | | /* C_NGLE_S */ |
19613 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19614 | | /* C_NGLE_S_MM */ |
19615 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19616 | | /* C_NGL_D32 */ |
19617 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19618 | | /* C_NGL_D32_MM */ |
19619 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19620 | | /* C_NGL_D64 */ |
19621 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19622 | | /* C_NGL_D64_MM */ |
19623 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19624 | | /* C_NGL_S */ |
19625 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19626 | | /* C_NGL_S_MM */ |
19627 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19628 | | /* C_NGT_D32 */ |
19629 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19630 | | /* C_NGT_D32_MM */ |
19631 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19632 | | /* C_NGT_D64 */ |
19633 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19634 | | /* C_NGT_D64_MM */ |
19635 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19636 | | /* C_NGT_S */ |
19637 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19638 | | /* C_NGT_S_MM */ |
19639 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19640 | | /* C_OLE_D32 */ |
19641 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19642 | | /* C_OLE_D32_MM */ |
19643 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19644 | | /* C_OLE_D64 */ |
19645 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19646 | | /* C_OLE_D64_MM */ |
19647 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19648 | | /* C_OLE_S */ |
19649 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19650 | | /* C_OLE_S_MM */ |
19651 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19652 | | /* C_OLT_D32 */ |
19653 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19654 | | /* C_OLT_D32_MM */ |
19655 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19656 | | /* C_OLT_D64 */ |
19657 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19658 | | /* C_OLT_D64_MM */ |
19659 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19660 | | /* C_OLT_S */ |
19661 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19662 | | /* C_OLT_S_MM */ |
19663 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19664 | | /* C_SEQ_D32 */ |
19665 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19666 | | /* C_SEQ_D32_MM */ |
19667 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19668 | | /* C_SEQ_D64 */ |
19669 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19670 | | /* C_SEQ_D64_MM */ |
19671 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19672 | | /* C_SEQ_S */ |
19673 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19674 | | /* C_SEQ_S_MM */ |
19675 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19676 | | /* C_SF_D32 */ |
19677 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19678 | | /* C_SF_D32_MM */ |
19679 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19680 | | /* C_SF_D64 */ |
19681 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19682 | | /* C_SF_D64_MM */ |
19683 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19684 | | /* C_SF_S */ |
19685 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19686 | | /* C_SF_S_MM */ |
19687 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19688 | | /* C_UEQ_D32 */ |
19689 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19690 | | /* C_UEQ_D32_MM */ |
19691 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19692 | | /* C_UEQ_D64 */ |
19693 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19694 | | /* C_UEQ_D64_MM */ |
19695 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19696 | | /* C_UEQ_S */ |
19697 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19698 | | /* C_UEQ_S_MM */ |
19699 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19700 | | /* C_ULE_D32 */ |
19701 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19702 | | /* C_ULE_D32_MM */ |
19703 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19704 | | /* C_ULE_D64 */ |
19705 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19706 | | /* C_ULE_D64_MM */ |
19707 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19708 | | /* C_ULE_S */ |
19709 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19710 | | /* C_ULE_S_MM */ |
19711 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19712 | | /* C_ULT_D32 */ |
19713 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19714 | | /* C_ULT_D32_MM */ |
19715 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19716 | | /* C_ULT_D64 */ |
19717 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19718 | | /* C_ULT_D64_MM */ |
19719 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19720 | | /* C_ULT_S */ |
19721 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19722 | | /* C_ULT_S_MM */ |
19723 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19724 | | /* C_UN_D32 */ |
19725 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19726 | | /* C_UN_D32_MM */ |
19727 | | FCCRegsOpnd, AFGR64Opnd, AFGR64Opnd, |
19728 | | /* C_UN_D64 */ |
19729 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19730 | | /* C_UN_D64_MM */ |
19731 | | FCCRegsOpnd, FGR64Opnd, FGR64Opnd, |
19732 | | /* C_UN_S */ |
19733 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19734 | | /* C_UN_S_MM */ |
19735 | | FCCRegsOpnd, FGR32Opnd, FGR32Opnd, |
19736 | | /* CmpRxRy16 */ |
19737 | | CPU16Regs, CPU16Regs, |
19738 | | /* CmpiRxImm16 */ |
19739 | | CPU16Regs, simm16, |
19740 | | /* CmpiRxImmX16 */ |
19741 | | CPU16Regs, simm16, |
19742 | | /* DADD */ |
19743 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19744 | | /* DADDi */ |
19745 | | GPR64Opnd, GPR64Opnd, simm16_64, |
19746 | | /* DADDiu */ |
19747 | | GPR64Opnd, GPR64Opnd, simm16_64, |
19748 | | /* DADDu */ |
19749 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19750 | | /* DAHI */ |
19751 | | GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, |
19752 | | /* DALIGN */ |
19753 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm3, |
19754 | | /* DATI */ |
19755 | | GPR64Opnd, GPR64Opnd, uimm16_altrelaxed, |
19756 | | /* DAUI */ |
19757 | | GPR64Opnd, GPR64Opnd, uimm16, |
19758 | | /* DBITSWAP */ |
19759 | | GPR64Opnd, GPR64Opnd, |
19760 | | /* DCLO */ |
19761 | | GPR64Opnd, GPR64Opnd, |
19762 | | /* DCLO_R6 */ |
19763 | | GPR64Opnd, GPR64Opnd, |
19764 | | /* DCLZ */ |
19765 | | GPR64Opnd, GPR64Opnd, |
19766 | | /* DCLZ_R6 */ |
19767 | | GPR64Opnd, GPR64Opnd, |
19768 | | /* DDIV */ |
19769 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19770 | | /* DDIVU */ |
19771 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19772 | | /* DERET */ |
19773 | | /* DERET_MM */ |
19774 | | /* DERET_MMR6 */ |
19775 | | /* DEXT */ |
19776 | | GPR64Opnd, GPR64Opnd, uimm5_report_uimm6, uimm5_plus1_report_uimm6, |
19777 | | /* DEXT64_32 */ |
19778 | | GPR64Opnd, GPR32Opnd, uimm5_report_uimm6, uimm5_plus1, |
19779 | | /* DEXTM */ |
19780 | | GPR64Opnd, GPR64Opnd, uimm5, uimm5_plus33, |
19781 | | /* DEXTU */ |
19782 | | GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_plus1, |
19783 | | /* DI */ |
19784 | | GPR32Opnd, |
19785 | | /* DINS */ |
19786 | | GPR64Opnd, GPR64Opnd, uimm6, uimm5_inssize_plus1, GPR64Opnd, |
19787 | | /* DINSM */ |
19788 | | GPR64Opnd, GPR64Opnd, uimm5, uimm_range_2_64, GPR64Opnd, |
19789 | | /* DINSU */ |
19790 | | GPR64Opnd, GPR64Opnd, uimm5_plus32, uimm5_inssize_plus1, GPR64Opnd, |
19791 | | /* DIV */ |
19792 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19793 | | /* DIVU */ |
19794 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19795 | | /* DIVU_MMR6 */ |
19796 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19797 | | /* DIV_MMR6 */ |
19798 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
19799 | | /* DIV_S_B */ |
19800 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19801 | | /* DIV_S_D */ |
19802 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19803 | | /* DIV_S_H */ |
19804 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19805 | | /* DIV_S_W */ |
19806 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19807 | | /* DIV_U_B */ |
19808 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
19809 | | /* DIV_U_D */ |
19810 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
19811 | | /* DIV_U_H */ |
19812 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
19813 | | /* DIV_U_W */ |
19814 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
19815 | | /* DI_MM */ |
19816 | | GPR32Opnd, |
19817 | | /* DI_MMR6 */ |
19818 | | GPR32Opnd, |
19819 | | /* DLSA */ |
19820 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, |
19821 | | /* DLSA_R6 */ |
19822 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, uimm2_plus1, |
19823 | | /* DMFC0 */ |
19824 | | GPR64Opnd, COP0Opnd, uimm3, |
19825 | | /* DMFC1 */ |
19826 | | GPR64Opnd, FGR64Opnd, |
19827 | | /* DMFC2 */ |
19828 | | GPR64Opnd, COP2Opnd, uimm3, |
19829 | | /* DMFC2_OCTEON */ |
19830 | | GPR64Opnd, uimm16, |
19831 | | /* DMFGC0 */ |
19832 | | GPR64Opnd, COP0Opnd, uimm3, |
19833 | | /* DMOD */ |
19834 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19835 | | /* DMODU */ |
19836 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19837 | | /* DMT */ |
19838 | | GPR32Opnd, |
19839 | | /* DMTC0 */ |
19840 | | COP0Opnd, GPR64Opnd, uimm3, |
19841 | | /* DMTC1 */ |
19842 | | FGR64Opnd, GPR64Opnd, |
19843 | | /* DMTC2 */ |
19844 | | COP2Opnd, GPR64Opnd, uimm3, |
19845 | | /* DMTC2_OCTEON */ |
19846 | | GPR64Opnd, uimm16, |
19847 | | /* DMTGC0 */ |
19848 | | COP0Opnd, GPR64Opnd, uimm3, |
19849 | | /* DMUH */ |
19850 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19851 | | /* DMUHU */ |
19852 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19853 | | /* DMUL */ |
19854 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19855 | | /* DMULT */ |
19856 | | GPR64Opnd, GPR64Opnd, |
19857 | | /* DMULTu */ |
19858 | | GPR64Opnd, GPR64Opnd, |
19859 | | /* DMULU */ |
19860 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19861 | | /* DMUL_R6 */ |
19862 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19863 | | /* DOTP_S_D */ |
19864 | | MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
19865 | | /* DOTP_S_H */ |
19866 | | MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
19867 | | /* DOTP_S_W */ |
19868 | | MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
19869 | | /* DOTP_U_D */ |
19870 | | MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
19871 | | /* DOTP_U_H */ |
19872 | | MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
19873 | | /* DOTP_U_W */ |
19874 | | MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
19875 | | /* DPADD_S_D */ |
19876 | | MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
19877 | | /* DPADD_S_H */ |
19878 | | MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
19879 | | /* DPADD_S_W */ |
19880 | | MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
19881 | | /* DPADD_U_D */ |
19882 | | MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
19883 | | /* DPADD_U_H */ |
19884 | | MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
19885 | | /* DPADD_U_W */ |
19886 | | MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
19887 | | /* DPAQX_SA_W_PH */ |
19888 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19889 | | /* DPAQX_SA_W_PH_MMR2 */ |
19890 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19891 | | /* DPAQX_S_W_PH */ |
19892 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19893 | | /* DPAQX_S_W_PH_MMR2 */ |
19894 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19895 | | /* DPAQ_SA_L_W */ |
19896 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19897 | | /* DPAQ_SA_L_W_MM */ |
19898 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19899 | | /* DPAQ_S_W_PH */ |
19900 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19901 | | /* DPAQ_S_W_PH_MM */ |
19902 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19903 | | /* DPAU_H_QBL */ |
19904 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19905 | | /* DPAU_H_QBL_MM */ |
19906 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19907 | | /* DPAU_H_QBR */ |
19908 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19909 | | /* DPAU_H_QBR_MM */ |
19910 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19911 | | /* DPAX_W_PH */ |
19912 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19913 | | /* DPAX_W_PH_MMR2 */ |
19914 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19915 | | /* DPA_W_PH */ |
19916 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19917 | | /* DPA_W_PH_MMR2 */ |
19918 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19919 | | /* DPOP */ |
19920 | | GPR64Opnd, GPR64Opnd, |
19921 | | /* DPSQX_SA_W_PH */ |
19922 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19923 | | /* DPSQX_SA_W_PH_MMR2 */ |
19924 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19925 | | /* DPSQX_S_W_PH */ |
19926 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19927 | | /* DPSQX_S_W_PH_MMR2 */ |
19928 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19929 | | /* DPSQ_SA_L_W */ |
19930 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19931 | | /* DPSQ_SA_L_W_MM */ |
19932 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19933 | | /* DPSQ_S_W_PH */ |
19934 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19935 | | /* DPSQ_S_W_PH_MM */ |
19936 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19937 | | /* DPSUB_S_D */ |
19938 | | MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
19939 | | /* DPSUB_S_H */ |
19940 | | MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
19941 | | /* DPSUB_S_W */ |
19942 | | MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
19943 | | /* DPSUB_U_D */ |
19944 | | MSA128DOpnd, MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
19945 | | /* DPSUB_U_H */ |
19946 | | MSA128HOpnd, MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
19947 | | /* DPSUB_U_W */ |
19948 | | MSA128WOpnd, MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
19949 | | /* DPSU_H_QBL */ |
19950 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19951 | | /* DPSU_H_QBL_MM */ |
19952 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19953 | | /* DPSU_H_QBR */ |
19954 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19955 | | /* DPSU_H_QBR_MM */ |
19956 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19957 | | /* DPSX_W_PH */ |
19958 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19959 | | /* DPSX_W_PH_MMR2 */ |
19960 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19961 | | /* DPS_W_PH */ |
19962 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19963 | | /* DPS_W_PH_MMR2 */ |
19964 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
19965 | | /* DROTR */ |
19966 | | GPR64Opnd, GPR64Opnd, uimm6, |
19967 | | /* DROTR32 */ |
19968 | | GPR64Opnd, GPR64Opnd, uimm5, |
19969 | | /* DROTRV */ |
19970 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, |
19971 | | /* DSBH */ |
19972 | | GPR64Opnd, GPR64Opnd, |
19973 | | /* DSDIV */ |
19974 | | GPR64Opnd, GPR64Opnd, |
19975 | | /* DSHD */ |
19976 | | GPR64Opnd, GPR64Opnd, |
19977 | | /* DSLL */ |
19978 | | GPR64Opnd, GPR64Opnd, uimm6, |
19979 | | /* DSLL32 */ |
19980 | | GPR64Opnd, GPR64Opnd, uimm5, |
19981 | | /* DSLL64_32 */ |
19982 | | GPR64, GPR32, |
19983 | | /* DSLLV */ |
19984 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, |
19985 | | /* DSRA */ |
19986 | | GPR64Opnd, GPR64Opnd, uimm6, |
19987 | | /* DSRA32 */ |
19988 | | GPR64Opnd, GPR64Opnd, uimm5, |
19989 | | /* DSRAV */ |
19990 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, |
19991 | | /* DSRL */ |
19992 | | GPR64Opnd, GPR64Opnd, uimm6, |
19993 | | /* DSRL32 */ |
19994 | | GPR64Opnd, GPR64Opnd, uimm5, |
19995 | | /* DSRLV */ |
19996 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, |
19997 | | /* DSUB */ |
19998 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
19999 | | /* DSUBu */ |
20000 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
20001 | | /* DUDIV */ |
20002 | | GPR64Opnd, GPR64Opnd, |
20003 | | /* DVP */ |
20004 | | GPR32Opnd, |
20005 | | /* DVPE */ |
20006 | | GPR32Opnd, |
20007 | | /* DVP_MMR6 */ |
20008 | | GPR32Opnd, |
20009 | | /* DivRxRy16 */ |
20010 | | CPU16Regs, CPU16Regs, |
20011 | | /* DivuRxRy16 */ |
20012 | | CPU16Regs, CPU16Regs, |
20013 | | /* EHB */ |
20014 | | /* EHB_MM */ |
20015 | | /* EHB_MMR6 */ |
20016 | | /* EI */ |
20017 | | GPR32Opnd, |
20018 | | /* EI_MM */ |
20019 | | GPR32Opnd, |
20020 | | /* EI_MMR6 */ |
20021 | | GPR32Opnd, |
20022 | | /* EMT */ |
20023 | | GPR32Opnd, |
20024 | | /* ERET */ |
20025 | | /* ERETNC */ |
20026 | | /* ERETNC_MMR6 */ |
20027 | | /* ERET_MM */ |
20028 | | /* ERET_MMR6 */ |
20029 | | /* EVP */ |
20030 | | GPR32Opnd, |
20031 | | /* EVPE */ |
20032 | | GPR32Opnd, |
20033 | | /* EVP_MMR6 */ |
20034 | | GPR32Opnd, |
20035 | | /* EXT */ |
20036 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, |
20037 | | /* EXTP */ |
20038 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20039 | | /* EXTPDP */ |
20040 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20041 | | /* EXTPDPV */ |
20042 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20043 | | /* EXTPDPV_MM */ |
20044 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20045 | | /* EXTPDP_MM */ |
20046 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20047 | | /* EXTPV */ |
20048 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20049 | | /* EXTPV_MM */ |
20050 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20051 | | /* EXTP_MM */ |
20052 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20053 | | /* EXTRV_RS_W */ |
20054 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20055 | | /* EXTRV_RS_W_MM */ |
20056 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20057 | | /* EXTRV_R_W */ |
20058 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20059 | | /* EXTRV_R_W_MM */ |
20060 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20061 | | /* EXTRV_S_H */ |
20062 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20063 | | /* EXTRV_S_H_MM */ |
20064 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20065 | | /* EXTRV_W */ |
20066 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20067 | | /* EXTRV_W_MM */ |
20068 | | GPR32Opnd, ACC64DSPOpnd, GPR32Opnd, |
20069 | | /* EXTR_RS_W */ |
20070 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20071 | | /* EXTR_RS_W_MM */ |
20072 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20073 | | /* EXTR_R_W */ |
20074 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20075 | | /* EXTR_R_W_MM */ |
20076 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20077 | | /* EXTR_S_H */ |
20078 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20079 | | /* EXTR_S_H_MM */ |
20080 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20081 | | /* EXTR_W */ |
20082 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20083 | | /* EXTR_W_MM */ |
20084 | | GPR32Opnd, ACC64DSPOpnd, uimm5, |
20085 | | /* EXTS */ |
20086 | | GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
20087 | | /* EXTS32 */ |
20088 | | GPR64Opnd, GPR64Opnd, uimm5, uimm5, |
20089 | | /* EXT_MM */ |
20090 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, |
20091 | | /* EXT_MMR6 */ |
20092 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5_plus1, |
20093 | | /* FABS_D32 */ |
20094 | | AFGR64Opnd, AFGR64Opnd, |
20095 | | /* FABS_D32_MM */ |
20096 | | AFGR64Opnd, AFGR64Opnd, |
20097 | | /* FABS_D64 */ |
20098 | | FGR64Opnd, FGR64Opnd, |
20099 | | /* FABS_D64_MM */ |
20100 | | FGR64Opnd, FGR64Opnd, |
20101 | | /* FABS_S */ |
20102 | | FGR32Opnd, FGR32Opnd, |
20103 | | /* FABS_S_MM */ |
20104 | | FGR32Opnd, FGR32Opnd, |
20105 | | /* FADD_D */ |
20106 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20107 | | /* FADD_D32 */ |
20108 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20109 | | /* FADD_D32_MM */ |
20110 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20111 | | /* FADD_D64 */ |
20112 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20113 | | /* FADD_D64_MM */ |
20114 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20115 | | /* FADD_PS64 */ |
20116 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20117 | | /* FADD_S */ |
20118 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20119 | | /* FADD_S_MM */ |
20120 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20121 | | /* FADD_S_MMR6 */ |
20122 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20123 | | /* FADD_W */ |
20124 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20125 | | /* FCAF_D */ |
20126 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20127 | | /* FCAF_W */ |
20128 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20129 | | /* FCEQ_D */ |
20130 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20131 | | /* FCEQ_W */ |
20132 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20133 | | /* FCLASS_D */ |
20134 | | MSA128DOpnd, MSA128DOpnd, |
20135 | | /* FCLASS_W */ |
20136 | | MSA128WOpnd, MSA128WOpnd, |
20137 | | /* FCLE_D */ |
20138 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20139 | | /* FCLE_W */ |
20140 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20141 | | /* FCLT_D */ |
20142 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20143 | | /* FCLT_W */ |
20144 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20145 | | /* FCMP_D32 */ |
20146 | | AFGR64, AFGR64, condcode, |
20147 | | /* FCMP_D32_MM */ |
20148 | | AFGR64, AFGR64, condcode, |
20149 | | /* FCMP_D64 */ |
20150 | | FGR64, FGR64, condcode, |
20151 | | /* FCMP_S32 */ |
20152 | | FGR32, FGR32, condcode, |
20153 | | /* FCMP_S32_MM */ |
20154 | | FGR32, FGR32, condcode, |
20155 | | /* FCNE_D */ |
20156 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20157 | | /* FCNE_W */ |
20158 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20159 | | /* FCOR_D */ |
20160 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20161 | | /* FCOR_W */ |
20162 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20163 | | /* FCUEQ_D */ |
20164 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20165 | | /* FCUEQ_W */ |
20166 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20167 | | /* FCULE_D */ |
20168 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20169 | | /* FCULE_W */ |
20170 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20171 | | /* FCULT_D */ |
20172 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20173 | | /* FCULT_W */ |
20174 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20175 | | /* FCUNE_D */ |
20176 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20177 | | /* FCUNE_W */ |
20178 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20179 | | /* FCUN_D */ |
20180 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20181 | | /* FCUN_W */ |
20182 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20183 | | /* FDIV_D */ |
20184 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20185 | | /* FDIV_D32 */ |
20186 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20187 | | /* FDIV_D32_MM */ |
20188 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20189 | | /* FDIV_D64 */ |
20190 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20191 | | /* FDIV_D64_MM */ |
20192 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20193 | | /* FDIV_S */ |
20194 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20195 | | /* FDIV_S_MM */ |
20196 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20197 | | /* FDIV_S_MMR6 */ |
20198 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20199 | | /* FDIV_W */ |
20200 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20201 | | /* FEXDO_H */ |
20202 | | MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, |
20203 | | /* FEXDO_W */ |
20204 | | MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, |
20205 | | /* FEXP2_D */ |
20206 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20207 | | /* FEXP2_W */ |
20208 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20209 | | /* FEXUPL_D */ |
20210 | | MSA128DOpnd, MSA128WOpnd, |
20211 | | /* FEXUPL_W */ |
20212 | | MSA128WOpnd, MSA128HOpnd, |
20213 | | /* FEXUPR_D */ |
20214 | | MSA128DOpnd, MSA128WOpnd, |
20215 | | /* FEXUPR_W */ |
20216 | | MSA128WOpnd, MSA128HOpnd, |
20217 | | /* FFINT_S_D */ |
20218 | | MSA128DOpnd, MSA128DOpnd, |
20219 | | /* FFINT_S_W */ |
20220 | | MSA128WOpnd, MSA128WOpnd, |
20221 | | /* FFINT_U_D */ |
20222 | | MSA128DOpnd, MSA128DOpnd, |
20223 | | /* FFINT_U_W */ |
20224 | | MSA128WOpnd, MSA128WOpnd, |
20225 | | /* FFQL_D */ |
20226 | | MSA128DOpnd, MSA128WOpnd, |
20227 | | /* FFQL_W */ |
20228 | | MSA128WOpnd, MSA128HOpnd, |
20229 | | /* FFQR_D */ |
20230 | | MSA128DOpnd, MSA128WOpnd, |
20231 | | /* FFQR_W */ |
20232 | | MSA128WOpnd, MSA128HOpnd, |
20233 | | /* FILL_B */ |
20234 | | MSA128BOpnd, GPR32Opnd, |
20235 | | /* FILL_D */ |
20236 | | MSA128DOpnd, GPR64Opnd, |
20237 | | /* FILL_H */ |
20238 | | MSA128HOpnd, GPR32Opnd, |
20239 | | /* FILL_W */ |
20240 | | MSA128WOpnd, GPR32Opnd, |
20241 | | /* FLOG2_D */ |
20242 | | MSA128DOpnd, MSA128DOpnd, |
20243 | | /* FLOG2_W */ |
20244 | | MSA128WOpnd, MSA128WOpnd, |
20245 | | /* FLOOR_L_D64 */ |
20246 | | FGR64Opnd, FGR64Opnd, |
20247 | | /* FLOOR_L_D_MMR6 */ |
20248 | | FGR64Opnd, FGR64Opnd, |
20249 | | /* FLOOR_L_S */ |
20250 | | FGR64Opnd, FGR32Opnd, |
20251 | | /* FLOOR_L_S_MMR6 */ |
20252 | | FGR64Opnd, FGR32Opnd, |
20253 | | /* FLOOR_W_D32 */ |
20254 | | FGR32Opnd, AFGR64Opnd, |
20255 | | /* FLOOR_W_D64 */ |
20256 | | FGR32Opnd, FGR64Opnd, |
20257 | | /* FLOOR_W_D_MMR6 */ |
20258 | | FGR32Opnd, AFGR64Opnd, |
20259 | | /* FLOOR_W_MM */ |
20260 | | FGR32Opnd, AFGR64Opnd, |
20261 | | /* FLOOR_W_S */ |
20262 | | FGR32Opnd, FGR32Opnd, |
20263 | | /* FLOOR_W_S_MM */ |
20264 | | FGR32Opnd, FGR32Opnd, |
20265 | | /* FLOOR_W_S_MMR6 */ |
20266 | | FGR32Opnd, FGR32Opnd, |
20267 | | /* FMADD_D */ |
20268 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20269 | | /* FMADD_W */ |
20270 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20271 | | /* FMAX_A_D */ |
20272 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20273 | | /* FMAX_A_W */ |
20274 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20275 | | /* FMAX_D */ |
20276 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20277 | | /* FMAX_W */ |
20278 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20279 | | /* FMIN_A_D */ |
20280 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20281 | | /* FMIN_A_W */ |
20282 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20283 | | /* FMIN_D */ |
20284 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20285 | | /* FMIN_W */ |
20286 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20287 | | /* FMOV_D32 */ |
20288 | | AFGR64Opnd, AFGR64Opnd, |
20289 | | /* FMOV_D32_MM */ |
20290 | | AFGR64Opnd, AFGR64Opnd, |
20291 | | /* FMOV_D64 */ |
20292 | | FGR64Opnd, FGR64Opnd, |
20293 | | /* FMOV_D64_MM */ |
20294 | | FGR64Opnd, FGR64Opnd, |
20295 | | /* FMOV_D_MMR6 */ |
20296 | | FGR64Opnd, FGR64Opnd, |
20297 | | /* FMOV_S */ |
20298 | | FGR32Opnd, FGR32Opnd, |
20299 | | /* FMOV_S_MM */ |
20300 | | FGR32Opnd, FGR32Opnd, |
20301 | | /* FMOV_S_MMR6 */ |
20302 | | FGR32Opnd, FGR32Opnd, |
20303 | | /* FMSUB_D */ |
20304 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20305 | | /* FMSUB_W */ |
20306 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20307 | | /* FMUL_D */ |
20308 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20309 | | /* FMUL_D32 */ |
20310 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20311 | | /* FMUL_D32_MM */ |
20312 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20313 | | /* FMUL_D64 */ |
20314 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20315 | | /* FMUL_D64_MM */ |
20316 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20317 | | /* FMUL_PS64 */ |
20318 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20319 | | /* FMUL_S */ |
20320 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20321 | | /* FMUL_S_MM */ |
20322 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20323 | | /* FMUL_S_MMR6 */ |
20324 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20325 | | /* FMUL_W */ |
20326 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20327 | | /* FNEG_D32 */ |
20328 | | AFGR64Opnd, AFGR64Opnd, |
20329 | | /* FNEG_D32_MM */ |
20330 | | AFGR64Opnd, AFGR64Opnd, |
20331 | | /* FNEG_D64 */ |
20332 | | FGR64Opnd, FGR64Opnd, |
20333 | | /* FNEG_D64_MM */ |
20334 | | FGR64Opnd, FGR64Opnd, |
20335 | | /* FNEG_S */ |
20336 | | FGR32Opnd, FGR32Opnd, |
20337 | | /* FNEG_S_MM */ |
20338 | | FGR32Opnd, FGR32Opnd, |
20339 | | /* FNEG_S_MMR6 */ |
20340 | | FGR32Opnd, FGR32Opnd, |
20341 | | /* FORK */ |
20342 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
20343 | | /* FRCP_D */ |
20344 | | MSA128DOpnd, MSA128DOpnd, |
20345 | | /* FRCP_W */ |
20346 | | MSA128WOpnd, MSA128WOpnd, |
20347 | | /* FRINT_D */ |
20348 | | MSA128DOpnd, MSA128DOpnd, |
20349 | | /* FRINT_W */ |
20350 | | MSA128WOpnd, MSA128WOpnd, |
20351 | | /* FRSQRT_D */ |
20352 | | MSA128DOpnd, MSA128DOpnd, |
20353 | | /* FRSQRT_W */ |
20354 | | MSA128WOpnd, MSA128WOpnd, |
20355 | | /* FSAF_D */ |
20356 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20357 | | /* FSAF_W */ |
20358 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20359 | | /* FSEQ_D */ |
20360 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20361 | | /* FSEQ_W */ |
20362 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20363 | | /* FSLE_D */ |
20364 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20365 | | /* FSLE_W */ |
20366 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20367 | | /* FSLT_D */ |
20368 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20369 | | /* FSLT_W */ |
20370 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20371 | | /* FSNE_D */ |
20372 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20373 | | /* FSNE_W */ |
20374 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20375 | | /* FSOR_D */ |
20376 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20377 | | /* FSOR_W */ |
20378 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20379 | | /* FSQRT_D */ |
20380 | | MSA128DOpnd, MSA128DOpnd, |
20381 | | /* FSQRT_D32 */ |
20382 | | AFGR64Opnd, AFGR64Opnd, |
20383 | | /* FSQRT_D32_MM */ |
20384 | | AFGR64Opnd, AFGR64Opnd, |
20385 | | /* FSQRT_D64 */ |
20386 | | FGR64Opnd, FGR64Opnd, |
20387 | | /* FSQRT_D64_MM */ |
20388 | | FGR64Opnd, FGR64Opnd, |
20389 | | /* FSQRT_S */ |
20390 | | FGR32Opnd, FGR32Opnd, |
20391 | | /* FSQRT_S_MM */ |
20392 | | FGR32Opnd, FGR32Opnd, |
20393 | | /* FSQRT_W */ |
20394 | | MSA128WOpnd, MSA128WOpnd, |
20395 | | /* FSUB_D */ |
20396 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20397 | | /* FSUB_D32 */ |
20398 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20399 | | /* FSUB_D32_MM */ |
20400 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20401 | | /* FSUB_D64 */ |
20402 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20403 | | /* FSUB_D64_MM */ |
20404 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20405 | | /* FSUB_PS64 */ |
20406 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20407 | | /* FSUB_S */ |
20408 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20409 | | /* FSUB_S_MM */ |
20410 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20411 | | /* FSUB_S_MMR6 */ |
20412 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20413 | | /* FSUB_W */ |
20414 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20415 | | /* FSUEQ_D */ |
20416 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20417 | | /* FSUEQ_W */ |
20418 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20419 | | /* FSULE_D */ |
20420 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20421 | | /* FSULE_W */ |
20422 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20423 | | /* FSULT_D */ |
20424 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20425 | | /* FSULT_W */ |
20426 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20427 | | /* FSUNE_D */ |
20428 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20429 | | /* FSUNE_W */ |
20430 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20431 | | /* FSUN_D */ |
20432 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20433 | | /* FSUN_W */ |
20434 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20435 | | /* FTINT_S_D */ |
20436 | | MSA128DOpnd, MSA128DOpnd, |
20437 | | /* FTINT_S_W */ |
20438 | | MSA128WOpnd, MSA128WOpnd, |
20439 | | /* FTINT_U_D */ |
20440 | | MSA128DOpnd, MSA128DOpnd, |
20441 | | /* FTINT_U_W */ |
20442 | | MSA128WOpnd, MSA128WOpnd, |
20443 | | /* FTQ_H */ |
20444 | | MSA128HOpnd, MSA128WOpnd, MSA128WOpnd, |
20445 | | /* FTQ_W */ |
20446 | | MSA128WOpnd, MSA128DOpnd, MSA128DOpnd, |
20447 | | /* FTRUNC_S_D */ |
20448 | | MSA128DOpnd, MSA128DOpnd, |
20449 | | /* FTRUNC_S_W */ |
20450 | | MSA128WOpnd, MSA128WOpnd, |
20451 | | /* FTRUNC_U_D */ |
20452 | | MSA128DOpnd, MSA128DOpnd, |
20453 | | /* FTRUNC_U_W */ |
20454 | | MSA128WOpnd, MSA128WOpnd, |
20455 | | /* GINVI */ |
20456 | | GPR32Opnd, |
20457 | | /* GINVI_MMR6 */ |
20458 | | GPR32Opnd, |
20459 | | /* GINVT */ |
20460 | | GPR32Opnd, uimm2, |
20461 | | /* GINVT_MMR6 */ |
20462 | | GPR32Opnd, uimm2, |
20463 | | /* HADD_S_D */ |
20464 | | MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
20465 | | /* HADD_S_H */ |
20466 | | MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
20467 | | /* HADD_S_W */ |
20468 | | MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
20469 | | /* HADD_U_D */ |
20470 | | MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
20471 | | /* HADD_U_H */ |
20472 | | MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
20473 | | /* HADD_U_W */ |
20474 | | MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
20475 | | /* HSUB_S_D */ |
20476 | | MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
20477 | | /* HSUB_S_H */ |
20478 | | MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
20479 | | /* HSUB_S_W */ |
20480 | | MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
20481 | | /* HSUB_U_D */ |
20482 | | MSA128DOpnd, MSA128WOpnd, MSA128WOpnd, |
20483 | | /* HSUB_U_H */ |
20484 | | MSA128HOpnd, MSA128BOpnd, MSA128BOpnd, |
20485 | | /* HSUB_U_W */ |
20486 | | MSA128WOpnd, MSA128HOpnd, MSA128HOpnd, |
20487 | | /* HYPCALL */ |
20488 | | uimm10, |
20489 | | /* HYPCALL_MM */ |
20490 | | uimm10, |
20491 | | /* ILVEV_B */ |
20492 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20493 | | /* ILVEV_D */ |
20494 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20495 | | /* ILVEV_H */ |
20496 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20497 | | /* ILVEV_W */ |
20498 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20499 | | /* ILVL_B */ |
20500 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20501 | | /* ILVL_D */ |
20502 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20503 | | /* ILVL_H */ |
20504 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20505 | | /* ILVL_W */ |
20506 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20507 | | /* ILVOD_B */ |
20508 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20509 | | /* ILVOD_D */ |
20510 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20511 | | /* ILVOD_H */ |
20512 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20513 | | /* ILVOD_W */ |
20514 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20515 | | /* ILVR_B */ |
20516 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20517 | | /* ILVR_D */ |
20518 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20519 | | /* ILVR_H */ |
20520 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20521 | | /* ILVR_W */ |
20522 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20523 | | /* INS */ |
20524 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, |
20525 | | /* INSERT_B */ |
20526 | | MSA128BOpnd, MSA128BOpnd, GPR32Opnd, uimm4, |
20527 | | /* INSERT_D */ |
20528 | | MSA128DOpnd, MSA128DOpnd, GPR64Opnd, uimm1, |
20529 | | /* INSERT_H */ |
20530 | | MSA128HOpnd, MSA128HOpnd, GPR32Opnd, uimm3, |
20531 | | /* INSERT_W */ |
20532 | | MSA128WOpnd, MSA128WOpnd, GPR32Opnd, uimm2, |
20533 | | /* INSV */ |
20534 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
20535 | | /* INSVE_B */ |
20536 | | MSA128BOpnd, MSA128BOpnd, uimm4, MSA128BOpnd, uimmz, |
20537 | | /* INSVE_D */ |
20538 | | MSA128DOpnd, MSA128DOpnd, uimm1, MSA128DOpnd, uimmz, |
20539 | | /* INSVE_H */ |
20540 | | MSA128HOpnd, MSA128HOpnd, uimm3, MSA128HOpnd, uimmz, |
20541 | | /* INSVE_W */ |
20542 | | MSA128WOpnd, MSA128WOpnd, uimm2, MSA128WOpnd, uimmz, |
20543 | | /* INSV_MM */ |
20544 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
20545 | | /* INS_MM */ |
20546 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, |
20547 | | /* INS_MMR6 */ |
20548 | | GPR32Opnd, GPR32Opnd, uimm5, uimm5_inssize_plus1, GPR32Opnd, |
20549 | | /* J */ |
20550 | | jmptarget, |
20551 | | /* JAL */ |
20552 | | calltarget, |
20553 | | /* JALR */ |
20554 | | GPR32Opnd, GPR32Opnd, |
20555 | | /* JALR16_MM */ |
20556 | | GPR32Opnd, |
20557 | | /* JALR64 */ |
20558 | | GPR64Opnd, GPR64Opnd, |
20559 | | /* JALRC16_MMR6 */ |
20560 | | GPR32Opnd, |
20561 | | /* JALRC_HB_MMR6 */ |
20562 | | GPR32Opnd, GPR32Opnd, |
20563 | | /* JALRC_MMR6 */ |
20564 | | GPR32Opnd, GPR32Opnd, |
20565 | | /* JALRS16_MM */ |
20566 | | GPR32Opnd, |
20567 | | /* JALRS_MM */ |
20568 | | GPR32Opnd, GPR32Opnd, |
20569 | | /* JALR_HB */ |
20570 | | GPR32Opnd, GPR32Opnd, |
20571 | | /* JALR_HB64 */ |
20572 | | GPR64Opnd, GPR64Opnd, |
20573 | | /* JALR_MM */ |
20574 | | GPR32Opnd, GPR32Opnd, |
20575 | | /* JALS_MM */ |
20576 | | calltarget_mm, |
20577 | | /* JALX */ |
20578 | | calltarget, |
20579 | | /* JALX_MM */ |
20580 | | calltarget, |
20581 | | /* JAL_MM */ |
20582 | | calltarget_mm, |
20583 | | /* JIALC */ |
20584 | | GPR32Opnd, calloffset16, |
20585 | | /* JIALC64 */ |
20586 | | GPR64Opnd, calloffset16, |
20587 | | /* JIALC_MMR6 */ |
20588 | | GPR32Opnd, calloffset16, |
20589 | | /* JIC */ |
20590 | | GPR32Opnd, jmpoffset16, |
20591 | | /* JIC64 */ |
20592 | | GPR64Opnd, jmpoffset16, |
20593 | | /* JIC_MMR6 */ |
20594 | | GPR32Opnd, jmpoffset16, |
20595 | | /* JR */ |
20596 | | GPR32Opnd, |
20597 | | /* JR16_MM */ |
20598 | | GPR32Opnd, |
20599 | | /* JR64 */ |
20600 | | GPR64Opnd, |
20601 | | /* JRADDIUSP */ |
20602 | | uimm5_lsl2, |
20603 | | /* JRC16_MM */ |
20604 | | GPR32Opnd, |
20605 | | /* JRC16_MMR6 */ |
20606 | | GPR32Opnd, |
20607 | | /* JRCADDIUSP_MMR6 */ |
20608 | | uimm5_lsl2, |
20609 | | /* JR_HB */ |
20610 | | GPR32Opnd, |
20611 | | /* JR_HB64 */ |
20612 | | GPR64Opnd, |
20613 | | /* JR_HB64_R6 */ |
20614 | | GPR64Opnd, |
20615 | | /* JR_HB_R6 */ |
20616 | | GPR32Opnd, |
20617 | | /* JR_MM */ |
20618 | | GPR32Opnd, |
20619 | | /* J_MM */ |
20620 | | jmptarget_mm, |
20621 | | /* Jal16 */ |
20622 | | uimm26, |
20623 | | /* JalB16 */ |
20624 | | uimm26, |
20625 | | /* JrRa16 */ |
20626 | | /* JrcRa16 */ |
20627 | | /* JrcRx16 */ |
20628 | | CPU16Regs, |
20629 | | /* JumpLinkReg16 */ |
20630 | | CPU16Regs, |
20631 | | /* LB */ |
20632 | | GPR32Opnd, -1, simm16, |
20633 | | /* LB64 */ |
20634 | | GPR64Opnd, -1, simm16, |
20635 | | /* LBE */ |
20636 | | GPR32Opnd, -1, simm9, |
20637 | | /* LBE_MM */ |
20638 | | GPR32Opnd, -1, simm16, |
20639 | | /* LBU16_MM */ |
20640 | | GPRMM16Opnd, -1, simm4, |
20641 | | /* LBUX */ |
20642 | | GPR32Opnd, -1, -1, |
20643 | | /* LBUX_MM */ |
20644 | | GPR32Opnd, -1, -1, |
20645 | | /* LBU_MMR6 */ |
20646 | | GPR32Opnd, -1, simm16, |
20647 | | /* LB_MM */ |
20648 | | GPR32Opnd, -1, simm16, |
20649 | | /* LB_MMR6 */ |
20650 | | GPR32Opnd, -1, simm16, |
20651 | | /* LBu */ |
20652 | | GPR32Opnd, -1, simm16, |
20653 | | /* LBu64 */ |
20654 | | GPR64Opnd, -1, simm16, |
20655 | | /* LBuE */ |
20656 | | GPR32Opnd, -1, simm9, |
20657 | | /* LBuE_MM */ |
20658 | | GPR32Opnd, -1, simm16, |
20659 | | /* LBu_MM */ |
20660 | | GPR32Opnd, -1, simm16, |
20661 | | /* LD */ |
20662 | | GPR64Opnd, -1, simm16, |
20663 | | /* LDC1 */ |
20664 | | AFGR64Opnd, -1, simm16, |
20665 | | /* LDC164 */ |
20666 | | FGR64Opnd, -1, simm16, |
20667 | | /* LDC1_D64_MMR6 */ |
20668 | | FGR64Opnd, -1, simm16, |
20669 | | /* LDC1_MM_D32 */ |
20670 | | AFGR64Opnd, -1, simm16, |
20671 | | /* LDC1_MM_D64 */ |
20672 | | FGR64Opnd, -1, simm16, |
20673 | | /* LDC2 */ |
20674 | | COP2Opnd, -1, simm16, |
20675 | | /* LDC2_MMR6 */ |
20676 | | COP2Opnd, GPR32, simm11, |
20677 | | /* LDC2_R6 */ |
20678 | | COP2Opnd, -1, simm11, |
20679 | | /* LDC3 */ |
20680 | | COP3Opnd, -1, simm16, |
20681 | | /* LDI_B */ |
20682 | | MSA128BOpnd, vsplat_simm10, |
20683 | | /* LDI_D */ |
20684 | | MSA128DOpnd, vsplat_simm10, |
20685 | | /* LDI_H */ |
20686 | | MSA128HOpnd, vsplat_simm10, |
20687 | | /* LDI_W */ |
20688 | | MSA128WOpnd, vsplat_simm10, |
20689 | | /* LDL */ |
20690 | | GPR64Opnd, -1, simm16, GPR64Opnd, |
20691 | | /* LDPC */ |
20692 | | GPR64Opnd, simm18_lsl3, |
20693 | | /* LDR */ |
20694 | | GPR64Opnd, -1, simm16, GPR64Opnd, |
20695 | | /* LDXC1 */ |
20696 | | AFGR64Opnd, -1, -1, |
20697 | | /* LDXC164 */ |
20698 | | FGR64Opnd, -1, -1, |
20699 | | /* LD_B */ |
20700 | | MSA128BOpnd, -1, simm10, |
20701 | | /* LD_D */ |
20702 | | MSA128DOpnd, -1, simm10_lsl3, |
20703 | | /* LD_H */ |
20704 | | MSA128HOpnd, -1, simm10_lsl1, |
20705 | | /* LD_W */ |
20706 | | MSA128WOpnd, -1, simm10_lsl2, |
20707 | | /* LEA_ADDiu */ |
20708 | | GPR32Opnd, -1, simm16, |
20709 | | /* LEA_ADDiu64 */ |
20710 | | GPR64Opnd, -1, simm16, |
20711 | | /* LEA_ADDiu_MM */ |
20712 | | GPR32Opnd, -1, simm16, |
20713 | | /* LH */ |
20714 | | GPR32Opnd, -1, simm16, |
20715 | | /* LH64 */ |
20716 | | GPR64Opnd, -1, simm16, |
20717 | | /* LHE */ |
20718 | | GPR32Opnd, -1, simm9, |
20719 | | /* LHE_MM */ |
20720 | | GPR32Opnd, -1, simm9, |
20721 | | /* LHU16_MM */ |
20722 | | GPRMM16Opnd, -1, simm4, |
20723 | | /* LHX */ |
20724 | | GPR32Opnd, -1, -1, |
20725 | | /* LHX_MM */ |
20726 | | GPR32Opnd, -1, -1, |
20727 | | /* LH_MM */ |
20728 | | GPR32Opnd, -1, simm16, |
20729 | | /* LHu */ |
20730 | | GPR32Opnd, -1, simm16, |
20731 | | /* LHu64 */ |
20732 | | GPR64Opnd, -1, simm16, |
20733 | | /* LHuE */ |
20734 | | GPR32Opnd, -1, simm9, |
20735 | | /* LHuE_MM */ |
20736 | | GPR32Opnd, -1, simm9, |
20737 | | /* LHu_MM */ |
20738 | | GPR32Opnd, -1, simm16, |
20739 | | /* LI16_MM */ |
20740 | | GPRMM16Opnd, li16_imm, |
20741 | | /* LI16_MMR6 */ |
20742 | | GPRMM16Opnd, li16_imm, |
20743 | | /* LL */ |
20744 | | GPR32Opnd, -1, simm16, |
20745 | | /* LL64 */ |
20746 | | GPR32Opnd, -1, simm16, |
20747 | | /* LL64_R6 */ |
20748 | | GPR32Opnd, -1, simm9, |
20749 | | /* LLD */ |
20750 | | GPR64Opnd, -1, simm16, |
20751 | | /* LLD_R6 */ |
20752 | | GPR64Opnd, -1, simm9, |
20753 | | /* LLE */ |
20754 | | GPR32Opnd, -1, simm9, |
20755 | | /* LLE_MM */ |
20756 | | GPR32Opnd, -1, simm9, |
20757 | | /* LL_MM */ |
20758 | | GPR32Opnd, -1, simm12, |
20759 | | /* LL_MMR6 */ |
20760 | | GPR32Opnd, -1, simm9, |
20761 | | /* LL_R6 */ |
20762 | | GPR32Opnd, -1, simm9, |
20763 | | /* LSA */ |
20764 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, |
20765 | | /* LSA_MMR6 */ |
20766 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, |
20767 | | /* LSA_R6 */ |
20768 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, uimm2_plus1, |
20769 | | /* LUI_MMR6 */ |
20770 | | GPR32Opnd, uimm16, |
20771 | | /* LUXC1 */ |
20772 | | AFGR64Opnd, -1, -1, |
20773 | | /* LUXC164 */ |
20774 | | FGR64Opnd, -1, -1, |
20775 | | /* LUXC1_MM */ |
20776 | | FGR64Opnd, -1, -1, |
20777 | | /* LUi */ |
20778 | | GPR32Opnd, uimm16_relaxed, |
20779 | | /* LUi64 */ |
20780 | | GPR64Opnd, uimm16_64_relaxed, |
20781 | | /* LUi_MM */ |
20782 | | GPR32Opnd, uimm16_relaxed, |
20783 | | /* LW */ |
20784 | | GPR32Opnd, -1, simm16, |
20785 | | /* LW16_MM */ |
20786 | | GPRMM16Opnd, -1, simm4, |
20787 | | /* LW64 */ |
20788 | | GPR64Opnd, -1, simm16, |
20789 | | /* LWC1 */ |
20790 | | FGR32Opnd, -1, simm16, |
20791 | | /* LWC1_MM */ |
20792 | | FGR32Opnd, -1, simm16, |
20793 | | /* LWC2 */ |
20794 | | COP2Opnd, -1, simm16, |
20795 | | /* LWC2_MMR6 */ |
20796 | | COP2Opnd, GPR32, simm11, |
20797 | | /* LWC2_R6 */ |
20798 | | COP2Opnd, -1, simm11, |
20799 | | /* LWC3 */ |
20800 | | COP3Opnd, -1, simm16, |
20801 | | /* LWDSP */ |
20802 | | DSPROpnd, -1, simm16, |
20803 | | /* LWDSP_MM */ |
20804 | | DSPROpnd, -1, simm16, |
20805 | | /* LWE */ |
20806 | | GPR32Opnd, -1, simm9, |
20807 | | /* LWE_MM */ |
20808 | | GPR32Opnd, -1, simm9, |
20809 | | /* LWGP_MM */ |
20810 | | GPRMM16Opnd, -1, simm7_lsl2, |
20811 | | /* LWL */ |
20812 | | GPR32Opnd, -1, simm16, GPR32Opnd, |
20813 | | /* LWL64 */ |
20814 | | GPR64Opnd, -1, simm16, GPR64Opnd, |
20815 | | /* LWLE */ |
20816 | | GPR32Opnd, -1, simm9, GPR32Opnd, |
20817 | | /* LWLE_MM */ |
20818 | | GPR32Opnd, -1, simm9, GPR32Opnd, |
20819 | | /* LWL_MM */ |
20820 | | GPR32Opnd, -1, simm12, GPR32Opnd, |
20821 | | /* LWM16_MM */ |
20822 | | reglist16, -1, uimm8, |
20823 | | /* LWM16_MMR6 */ |
20824 | | reglist16, -1, uimm8, |
20825 | | /* LWM32_MM */ |
20826 | | reglist, -1, simm12, |
20827 | | /* LWPC */ |
20828 | | GPR32Opnd, simm19_lsl2, |
20829 | | /* LWPC_MMR6 */ |
20830 | | GPR32Opnd, simm19_lsl2, |
20831 | | /* LWP_MM */ |
20832 | | GPR32Opnd, GPR32Opnd, -1, simm12, |
20833 | | /* LWR */ |
20834 | | GPR32Opnd, -1, simm16, GPR32Opnd, |
20835 | | /* LWR64 */ |
20836 | | GPR64Opnd, -1, simm16, GPR64Opnd, |
20837 | | /* LWRE */ |
20838 | | GPR32Opnd, -1, simm9, GPR32Opnd, |
20839 | | /* LWRE_MM */ |
20840 | | GPR32Opnd, -1, simm9, GPR32Opnd, |
20841 | | /* LWR_MM */ |
20842 | | GPR32Opnd, -1, simm12, GPR32Opnd, |
20843 | | /* LWSP_MM */ |
20844 | | GPR32Opnd, -1, simm5, |
20845 | | /* LWUPC */ |
20846 | | GPR32Opnd, simm19_lsl2, |
20847 | | /* LWU_MM */ |
20848 | | GPR32Opnd, -1, simm12, |
20849 | | /* LWX */ |
20850 | | GPR32Opnd, -1, -1, |
20851 | | /* LWXC1 */ |
20852 | | FGR32Opnd, -1, -1, |
20853 | | /* LWXC1_MM */ |
20854 | | FGR32Opnd, -1, -1, |
20855 | | /* LWXS_MM */ |
20856 | | GPR32Opnd, -1, -1, |
20857 | | /* LWX_MM */ |
20858 | | GPR32Opnd, -1, -1, |
20859 | | /* LW_MM */ |
20860 | | GPR32Opnd, -1, simm16, |
20861 | | /* LW_MMR6 */ |
20862 | | GPR32Opnd, -1, simm16, |
20863 | | /* LWu */ |
20864 | | GPR64Opnd, -1, simm16, |
20865 | | /* LbRxRyOffMemX16 */ |
20866 | | CPU16Regs, CPU16Regs, simm16, |
20867 | | /* LbuRxRyOffMemX16 */ |
20868 | | CPU16Regs, CPU16Regs, simm16, |
20869 | | /* LhRxRyOffMemX16 */ |
20870 | | CPU16Regs, CPU16Regs, simm16, |
20871 | | /* LhuRxRyOffMemX16 */ |
20872 | | CPU16Regs, CPU16Regs, simm16, |
20873 | | /* LiRxImm16 */ |
20874 | | CPU16Regs, simm16, |
20875 | | /* LiRxImmAlignX16 */ |
20876 | | CPU16Regs, simm16, |
20877 | | /* LiRxImmX16 */ |
20878 | | CPU16Regs, simm16, |
20879 | | /* LwRxPcTcp16 */ |
20880 | | CPU16Regs, pcrel16, i32imm, |
20881 | | /* LwRxPcTcpX16 */ |
20882 | | CPU16Regs, pcrel16, i32imm, |
20883 | | /* LwRxRyOffMemX16 */ |
20884 | | CPU16Regs, CPU16Regs, simm16, |
20885 | | /* LwRxSpImmX16 */ |
20886 | | CPU16Regs, CPU16RegsPlusSP, simm16, |
20887 | | /* MADD */ |
20888 | | GPR32Opnd, GPR32Opnd, |
20889 | | /* MADDF_D */ |
20890 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20891 | | /* MADDF_D_MMR6 */ |
20892 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20893 | | /* MADDF_S */ |
20894 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20895 | | /* MADDF_S_MMR6 */ |
20896 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20897 | | /* MADDR_Q_H */ |
20898 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20899 | | /* MADDR_Q_W */ |
20900 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20901 | | /* MADDU */ |
20902 | | GPR32Opnd, GPR32Opnd, |
20903 | | /* MADDU_DSP */ |
20904 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20905 | | /* MADDU_DSP_MM */ |
20906 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20907 | | /* MADDU_MM */ |
20908 | | GPR32Opnd, GPR32Opnd, |
20909 | | /* MADDV_B */ |
20910 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20911 | | /* MADDV_D */ |
20912 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20913 | | /* MADDV_H */ |
20914 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20915 | | /* MADDV_W */ |
20916 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20917 | | /* MADD_D32 */ |
20918 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20919 | | /* MADD_D32_MM */ |
20920 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
20921 | | /* MADD_D64 */ |
20922 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20923 | | /* MADD_DSP */ |
20924 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20925 | | /* MADD_DSP_MM */ |
20926 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20927 | | /* MADD_MM */ |
20928 | | GPR32Opnd, GPR32Opnd, |
20929 | | /* MADD_Q_H */ |
20930 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20931 | | /* MADD_Q_W */ |
20932 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20933 | | /* MADD_S */ |
20934 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20935 | | /* MADD_S_MM */ |
20936 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20937 | | /* MAQ_SA_W_PHL */ |
20938 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20939 | | /* MAQ_SA_W_PHL_MM */ |
20940 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20941 | | /* MAQ_SA_W_PHR */ |
20942 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20943 | | /* MAQ_SA_W_PHR_MM */ |
20944 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20945 | | /* MAQ_S_W_PHL */ |
20946 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20947 | | /* MAQ_S_W_PHL_MM */ |
20948 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20949 | | /* MAQ_S_W_PHR */ |
20950 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20951 | | /* MAQ_S_W_PHR_MM */ |
20952 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
20953 | | /* MAXA_D */ |
20954 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20955 | | /* MAXA_D_MMR6 */ |
20956 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20957 | | /* MAXA_S */ |
20958 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20959 | | /* MAXA_S_MMR6 */ |
20960 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20961 | | /* MAXI_S_B */ |
20962 | | MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
20963 | | /* MAXI_S_D */ |
20964 | | MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
20965 | | /* MAXI_S_H */ |
20966 | | MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
20967 | | /* MAXI_S_W */ |
20968 | | MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
20969 | | /* MAXI_U_B */ |
20970 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
20971 | | /* MAXI_U_D */ |
20972 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
20973 | | /* MAXI_U_H */ |
20974 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
20975 | | /* MAXI_U_W */ |
20976 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
20977 | | /* MAX_A_B */ |
20978 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20979 | | /* MAX_A_D */ |
20980 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20981 | | /* MAX_A_H */ |
20982 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20983 | | /* MAX_A_W */ |
20984 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
20985 | | /* MAX_D */ |
20986 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20987 | | /* MAX_D_MMR6 */ |
20988 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
20989 | | /* MAX_S */ |
20990 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20991 | | /* MAX_S_B */ |
20992 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
20993 | | /* MAX_S_D */ |
20994 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
20995 | | /* MAX_S_H */ |
20996 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
20997 | | /* MAX_S_MMR6 */ |
20998 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
20999 | | /* MAX_S_W */ |
21000 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21001 | | /* MAX_U_B */ |
21002 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21003 | | /* MAX_U_D */ |
21004 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21005 | | /* MAX_U_H */ |
21006 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21007 | | /* MAX_U_W */ |
21008 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21009 | | /* MFC0 */ |
21010 | | GPR32Opnd, COP0Opnd, uimm3, |
21011 | | /* MFC0_MMR6 */ |
21012 | | GPR32Opnd, COP0Opnd, uimm3, |
21013 | | /* MFC1 */ |
21014 | | GPR32Opnd, FGR32Opnd, |
21015 | | /* MFC1_D64 */ |
21016 | | GPR32Opnd, FGR64Opnd, |
21017 | | /* MFC1_MM */ |
21018 | | GPR32Opnd, FGR32Opnd, |
21019 | | /* MFC1_MMR6 */ |
21020 | | GPR32Opnd, FGR32Opnd, |
21021 | | /* MFC2 */ |
21022 | | GPR32Opnd, COP2Opnd, uimm3, |
21023 | | /* MFC2_MMR6 */ |
21024 | | GPR32Opnd, COP2Opnd, |
21025 | | /* MFGC0 */ |
21026 | | GPR32Opnd, COP0Opnd, uimm3, |
21027 | | /* MFGC0_MM */ |
21028 | | GPR32Opnd, COP0Opnd, uimm3, |
21029 | | /* MFHC0_MMR6 */ |
21030 | | GPR32Opnd, COP0Opnd, uimm3, |
21031 | | /* MFHC1_D32 */ |
21032 | | GPR32Opnd, AFGR64Opnd, |
21033 | | /* MFHC1_D32_MM */ |
21034 | | GPR32Opnd, AFGR64Opnd, |
21035 | | /* MFHC1_D64 */ |
21036 | | GPR32Opnd, FGR64Opnd, |
21037 | | /* MFHC1_D64_MM */ |
21038 | | GPR32Opnd, FGR64Opnd, |
21039 | | /* MFHC2_MMR6 */ |
21040 | | GPR32Opnd, COP2Opnd, |
21041 | | /* MFHGC0 */ |
21042 | | GPR32Opnd, COP0Opnd, uimm3, |
21043 | | /* MFHGC0_MM */ |
21044 | | GPR32Opnd, COP0Opnd, uimm3, |
21045 | | /* MFHI */ |
21046 | | GPR32Opnd, |
21047 | | /* MFHI16_MM */ |
21048 | | GPR32Opnd, |
21049 | | /* MFHI64 */ |
21050 | | GPR64Opnd, |
21051 | | /* MFHI_DSP */ |
21052 | | GPR32Opnd, ACC64DSPOpnd, |
21053 | | /* MFHI_DSP_MM */ |
21054 | | GPR32Opnd, ACC64DSPOpnd, |
21055 | | /* MFHI_MM */ |
21056 | | GPR32Opnd, |
21057 | | /* MFLO */ |
21058 | | GPR32Opnd, |
21059 | | /* MFLO16_MM */ |
21060 | | GPR32Opnd, |
21061 | | /* MFLO64 */ |
21062 | | GPR64Opnd, |
21063 | | /* MFLO_DSP */ |
21064 | | GPR32Opnd, ACC64DSPOpnd, |
21065 | | /* MFLO_DSP_MM */ |
21066 | | GPR32Opnd, ACC64DSPOpnd, |
21067 | | /* MFLO_MM */ |
21068 | | GPR32Opnd, |
21069 | | /* MFTR */ |
21070 | | GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, |
21071 | | /* MINA_D */ |
21072 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21073 | | /* MINA_D_MMR6 */ |
21074 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21075 | | /* MINA_S */ |
21076 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21077 | | /* MINA_S_MMR6 */ |
21078 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21079 | | /* MINI_S_B */ |
21080 | | MSA128BOpnd, MSA128BOpnd, vsplat_simm5, |
21081 | | /* MINI_S_D */ |
21082 | | MSA128DOpnd, MSA128DOpnd, vsplat_simm5, |
21083 | | /* MINI_S_H */ |
21084 | | MSA128HOpnd, MSA128HOpnd, vsplat_simm5, |
21085 | | /* MINI_S_W */ |
21086 | | MSA128WOpnd, MSA128WOpnd, vsplat_simm5, |
21087 | | /* MINI_U_B */ |
21088 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
21089 | | /* MINI_U_D */ |
21090 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
21091 | | /* MINI_U_H */ |
21092 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
21093 | | /* MINI_U_W */ |
21094 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
21095 | | /* MIN_A_B */ |
21096 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21097 | | /* MIN_A_D */ |
21098 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21099 | | /* MIN_A_H */ |
21100 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21101 | | /* MIN_A_W */ |
21102 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21103 | | /* MIN_D */ |
21104 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21105 | | /* MIN_D_MMR6 */ |
21106 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21107 | | /* MIN_S */ |
21108 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21109 | | /* MIN_S_B */ |
21110 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21111 | | /* MIN_S_D */ |
21112 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21113 | | /* MIN_S_H */ |
21114 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21115 | | /* MIN_S_MMR6 */ |
21116 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21117 | | /* MIN_S_W */ |
21118 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21119 | | /* MIN_U_B */ |
21120 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21121 | | /* MIN_U_D */ |
21122 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21123 | | /* MIN_U_H */ |
21124 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21125 | | /* MIN_U_W */ |
21126 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21127 | | /* MOD */ |
21128 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21129 | | /* MODSUB */ |
21130 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21131 | | /* MODSUB_MM */ |
21132 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21133 | | /* MODU */ |
21134 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21135 | | /* MODU_MMR6 */ |
21136 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21137 | | /* MOD_MMR6 */ |
21138 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21139 | | /* MOD_S_B */ |
21140 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21141 | | /* MOD_S_D */ |
21142 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21143 | | /* MOD_S_H */ |
21144 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21145 | | /* MOD_S_W */ |
21146 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21147 | | /* MOD_U_B */ |
21148 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21149 | | /* MOD_U_D */ |
21150 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21151 | | /* MOD_U_H */ |
21152 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21153 | | /* MOD_U_W */ |
21154 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21155 | | /* MOVE16_MM */ |
21156 | | GPR32Opnd, GPR32Opnd, |
21157 | | /* MOVE16_MMR6 */ |
21158 | | GPR32Opnd, GPR32Opnd, |
21159 | | /* MOVEP_MM */ |
21160 | | GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, |
21161 | | /* MOVEP_MMR6 */ |
21162 | | GPRMM16OpndMovePPairFirst, GPRMM16OpndMovePPairSecond, GPRMM16OpndMoveP, GPRMM16OpndMoveP, |
21163 | | /* MOVE_V */ |
21164 | | MSA128BOpnd, MSA128BOpnd, |
21165 | | /* MOVF_D32 */ |
21166 | | AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
21167 | | /* MOVF_D32_MM */ |
21168 | | AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
21169 | | /* MOVF_D64 */ |
21170 | | FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, |
21171 | | /* MOVF_I */ |
21172 | | GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
21173 | | /* MOVF_I64 */ |
21174 | | GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, |
21175 | | /* MOVF_I_MM */ |
21176 | | GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
21177 | | /* MOVF_S */ |
21178 | | FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
21179 | | /* MOVF_S_MM */ |
21180 | | FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
21181 | | /* MOVN_I64_D64 */ |
21182 | | FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, |
21183 | | /* MOVN_I64_I */ |
21184 | | GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, |
21185 | | /* MOVN_I64_I64 */ |
21186 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21187 | | /* MOVN_I64_S */ |
21188 | | FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, |
21189 | | /* MOVN_I_D32 */ |
21190 | | AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
21191 | | /* MOVN_I_D32_MM */ |
21192 | | AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
21193 | | /* MOVN_I_D64 */ |
21194 | | FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, |
21195 | | /* MOVN_I_I */ |
21196 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21197 | | /* MOVN_I_I64 */ |
21198 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, |
21199 | | /* MOVN_I_MM */ |
21200 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21201 | | /* MOVN_I_S */ |
21202 | | FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
21203 | | /* MOVN_I_S_MM */ |
21204 | | FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
21205 | | /* MOVT_D32 */ |
21206 | | AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
21207 | | /* MOVT_D32_MM */ |
21208 | | AFGR64Opnd, AFGR64Opnd, FCCRegsOpnd, AFGR64Opnd, |
21209 | | /* MOVT_D64 */ |
21210 | | FGR64Opnd, FGR64Opnd, FCCRegsOpnd, FGR64Opnd, |
21211 | | /* MOVT_I */ |
21212 | | GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
21213 | | /* MOVT_I64 */ |
21214 | | GPR64Opnd, GPR64Opnd, FCCRegsOpnd, GPR64Opnd, |
21215 | | /* MOVT_I_MM */ |
21216 | | GPR32Opnd, GPR32Opnd, FCCRegsOpnd, GPR32Opnd, |
21217 | | /* MOVT_S */ |
21218 | | FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
21219 | | /* MOVT_S_MM */ |
21220 | | FGR32Opnd, FGR32Opnd, FCCRegsOpnd, FGR32Opnd, |
21221 | | /* MOVZ_I64_D64 */ |
21222 | | FGR64Opnd, FGR64Opnd, GPR64Opnd, FGR64Opnd, |
21223 | | /* MOVZ_I64_I */ |
21224 | | GPR32Opnd, GPR32Opnd, GPR64Opnd, GPR32Opnd, |
21225 | | /* MOVZ_I64_I64 */ |
21226 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21227 | | /* MOVZ_I64_S */ |
21228 | | FGR32Opnd, FGR32Opnd, GPR64Opnd, FGR32Opnd, |
21229 | | /* MOVZ_I_D32 */ |
21230 | | AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
21231 | | /* MOVZ_I_D32_MM */ |
21232 | | AFGR64Opnd, AFGR64Opnd, GPR32Opnd, AFGR64Opnd, |
21233 | | /* MOVZ_I_D64 */ |
21234 | | FGR64Opnd, FGR64Opnd, GPR32Opnd, FGR64Opnd, |
21235 | | /* MOVZ_I_I */ |
21236 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21237 | | /* MOVZ_I_I64 */ |
21238 | | GPR64Opnd, GPR64Opnd, GPR32Opnd, GPR64Opnd, |
21239 | | /* MOVZ_I_MM */ |
21240 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21241 | | /* MOVZ_I_S */ |
21242 | | FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
21243 | | /* MOVZ_I_S_MM */ |
21244 | | FGR32Opnd, FGR32Opnd, GPR32Opnd, FGR32Opnd, |
21245 | | /* MSUB */ |
21246 | | GPR32Opnd, GPR32Opnd, |
21247 | | /* MSUBF_D */ |
21248 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21249 | | /* MSUBF_D_MMR6 */ |
21250 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21251 | | /* MSUBF_S */ |
21252 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21253 | | /* MSUBF_S_MMR6 */ |
21254 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21255 | | /* MSUBR_Q_H */ |
21256 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21257 | | /* MSUBR_Q_W */ |
21258 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21259 | | /* MSUBU */ |
21260 | | GPR32Opnd, GPR32Opnd, |
21261 | | /* MSUBU_DSP */ |
21262 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21263 | | /* MSUBU_DSP_MM */ |
21264 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21265 | | /* MSUBU_MM */ |
21266 | | GPR32Opnd, GPR32Opnd, |
21267 | | /* MSUBV_B */ |
21268 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21269 | | /* MSUBV_D */ |
21270 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21271 | | /* MSUBV_H */ |
21272 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21273 | | /* MSUBV_W */ |
21274 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21275 | | /* MSUB_D32 */ |
21276 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
21277 | | /* MSUB_D32_MM */ |
21278 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
21279 | | /* MSUB_D64 */ |
21280 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21281 | | /* MSUB_DSP */ |
21282 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21283 | | /* MSUB_DSP_MM */ |
21284 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21285 | | /* MSUB_MM */ |
21286 | | GPR32Opnd, GPR32Opnd, |
21287 | | /* MSUB_Q_H */ |
21288 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21289 | | /* MSUB_Q_W */ |
21290 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21291 | | /* MSUB_S */ |
21292 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21293 | | /* MSUB_S_MM */ |
21294 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21295 | | /* MTC0 */ |
21296 | | COP0Opnd, GPR32Opnd, uimm3, |
21297 | | /* MTC0_MMR6 */ |
21298 | | COP0Opnd, GPR32Opnd, uimm3, |
21299 | | /* MTC1 */ |
21300 | | FGR32Opnd, GPR32Opnd, |
21301 | | /* MTC1_D64 */ |
21302 | | FGR64Opnd, GPR32Opnd, |
21303 | | /* MTC1_D64_MM */ |
21304 | | FGR64Opnd, GPR32Opnd, |
21305 | | /* MTC1_MM */ |
21306 | | FGR32Opnd, GPR32Opnd, |
21307 | | /* MTC1_MMR6 */ |
21308 | | FGR32Opnd, GPR32Opnd, |
21309 | | /* MTC2 */ |
21310 | | COP2Opnd, GPR32Opnd, uimm3, |
21311 | | /* MTC2_MMR6 */ |
21312 | | COP2Opnd, GPR32Opnd, |
21313 | | /* MTGC0 */ |
21314 | | COP0Opnd, GPR32Opnd, uimm3, |
21315 | | /* MTGC0_MM */ |
21316 | | COP0Opnd, GPR32Opnd, uimm3, |
21317 | | /* MTHC0_MMR6 */ |
21318 | | COP0Opnd, GPR32Opnd, uimm3, |
21319 | | /* MTHC1_D32 */ |
21320 | | AFGR64Opnd, AFGR64Opnd, GPR32Opnd, |
21321 | | /* MTHC1_D32_MM */ |
21322 | | AFGR64Opnd, AFGR64Opnd, GPR32Opnd, |
21323 | | /* MTHC1_D64 */ |
21324 | | FGR64Opnd, FGR64Opnd, GPR32Opnd, |
21325 | | /* MTHC1_D64_MM */ |
21326 | | FGR64Opnd, FGR64Opnd, GPR32Opnd, |
21327 | | /* MTHC2_MMR6 */ |
21328 | | COP2Opnd, GPR32Opnd, |
21329 | | /* MTHGC0 */ |
21330 | | COP0Opnd, GPR32Opnd, uimm3, |
21331 | | /* MTHGC0_MM */ |
21332 | | COP0Opnd, GPR32Opnd, uimm3, |
21333 | | /* MTHI */ |
21334 | | GPR32Opnd, |
21335 | | /* MTHI64 */ |
21336 | | GPR64Opnd, |
21337 | | /* MTHI_DSP */ |
21338 | | HI32DSPOpnd, GPR32Opnd, |
21339 | | /* MTHI_DSP_MM */ |
21340 | | HI32DSPOpnd, GPR32Opnd, |
21341 | | /* MTHI_MM */ |
21342 | | GPR32Opnd, |
21343 | | /* MTHLIP */ |
21344 | | ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
21345 | | /* MTHLIP_MM */ |
21346 | | ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
21347 | | /* MTLO */ |
21348 | | GPR32Opnd, |
21349 | | /* MTLO64 */ |
21350 | | GPR64Opnd, |
21351 | | /* MTLO_DSP */ |
21352 | | LO32DSPOpnd, GPR32Opnd, |
21353 | | /* MTLO_DSP_MM */ |
21354 | | LO32DSPOpnd, GPR32Opnd, |
21355 | | /* MTLO_MM */ |
21356 | | GPR32Opnd, |
21357 | | /* MTM0 */ |
21358 | | GPR64Opnd, |
21359 | | /* MTM1 */ |
21360 | | GPR64Opnd, |
21361 | | /* MTM2 */ |
21362 | | GPR64Opnd, |
21363 | | /* MTP0 */ |
21364 | | GPR64Opnd, |
21365 | | /* MTP1 */ |
21366 | | GPR64Opnd, |
21367 | | /* MTP2 */ |
21368 | | GPR64Opnd, |
21369 | | /* MTTR */ |
21370 | | GPR32Opnd, GPR32Opnd, uimm1, uimm3, uimm1, |
21371 | | /* MUH */ |
21372 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21373 | | /* MUHU */ |
21374 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21375 | | /* MUHU_MMR6 */ |
21376 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21377 | | /* MUH_MMR6 */ |
21378 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21379 | | /* MUL */ |
21380 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21381 | | /* MULEQ_S_W_PHL */ |
21382 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
21383 | | /* MULEQ_S_W_PHL_MM */ |
21384 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
21385 | | /* MULEQ_S_W_PHR */ |
21386 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
21387 | | /* MULEQ_S_W_PHR_MM */ |
21388 | | GPR32Opnd, DSPROpnd, DSPROpnd, |
21389 | | /* MULEU_S_PH_QBL */ |
21390 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21391 | | /* MULEU_S_PH_QBL_MM */ |
21392 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21393 | | /* MULEU_S_PH_QBR */ |
21394 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21395 | | /* MULEU_S_PH_QBR_MM */ |
21396 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21397 | | /* MULQ_RS_PH */ |
21398 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21399 | | /* MULQ_RS_PH_MM */ |
21400 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21401 | | /* MULQ_RS_W */ |
21402 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21403 | | /* MULQ_RS_W_MMR2 */ |
21404 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21405 | | /* MULQ_S_PH */ |
21406 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21407 | | /* MULQ_S_PH_MMR2 */ |
21408 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21409 | | /* MULQ_S_W */ |
21410 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21411 | | /* MULQ_S_W_MMR2 */ |
21412 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21413 | | /* MULR_PS64 */ |
21414 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21415 | | /* MULR_Q_H */ |
21416 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21417 | | /* MULR_Q_W */ |
21418 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21419 | | /* MULSAQ_S_W_PH */ |
21420 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21421 | | /* MULSAQ_S_W_PH_MM */ |
21422 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21423 | | /* MULSA_W_PH */ |
21424 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21425 | | /* MULSA_W_PH_MMR2 */ |
21426 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, ACC64DSPOpnd, |
21427 | | /* MULT */ |
21428 | | GPR32Opnd, GPR32Opnd, |
21429 | | /* MULTU_DSP */ |
21430 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
21431 | | /* MULTU_DSP_MM */ |
21432 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
21433 | | /* MULT_DSP */ |
21434 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
21435 | | /* MULT_DSP_MM */ |
21436 | | ACC64DSPOpnd, GPR32Opnd, GPR32Opnd, |
21437 | | /* MULT_MM */ |
21438 | | GPR32Opnd, GPR32Opnd, |
21439 | | /* MULTu */ |
21440 | | GPR32Opnd, GPR32Opnd, |
21441 | | /* MULTu_MM */ |
21442 | | GPR32Opnd, GPR32Opnd, |
21443 | | /* MULU */ |
21444 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21445 | | /* MULU_MMR6 */ |
21446 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21447 | | /* MULV_B */ |
21448 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21449 | | /* MULV_D */ |
21450 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21451 | | /* MULV_H */ |
21452 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21453 | | /* MULV_W */ |
21454 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21455 | | /* MUL_MM */ |
21456 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21457 | | /* MUL_MMR6 */ |
21458 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21459 | | /* MUL_PH */ |
21460 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21461 | | /* MUL_PH_MMR2 */ |
21462 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21463 | | /* MUL_Q_H */ |
21464 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21465 | | /* MUL_Q_W */ |
21466 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21467 | | /* MUL_R6 */ |
21468 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21469 | | /* MUL_S_PH */ |
21470 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21471 | | /* MUL_S_PH_MMR2 */ |
21472 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21473 | | /* Mfhi16 */ |
21474 | | CPU16Regs, |
21475 | | /* Mflo16 */ |
21476 | | CPU16Regs, |
21477 | | /* Move32R16 */ |
21478 | | GPR32, CPU16Regs, |
21479 | | /* MoveR3216 */ |
21480 | | CPU16Regs, GPR32, |
21481 | | /* NLOC_B */ |
21482 | | MSA128BOpnd, MSA128BOpnd, |
21483 | | /* NLOC_D */ |
21484 | | MSA128DOpnd, MSA128DOpnd, |
21485 | | /* NLOC_H */ |
21486 | | MSA128HOpnd, MSA128HOpnd, |
21487 | | /* NLOC_W */ |
21488 | | MSA128WOpnd, MSA128WOpnd, |
21489 | | /* NLZC_B */ |
21490 | | MSA128BOpnd, MSA128BOpnd, |
21491 | | /* NLZC_D */ |
21492 | | MSA128DOpnd, MSA128DOpnd, |
21493 | | /* NLZC_H */ |
21494 | | MSA128HOpnd, MSA128HOpnd, |
21495 | | /* NLZC_W */ |
21496 | | MSA128WOpnd, MSA128WOpnd, |
21497 | | /* NMADD_D32 */ |
21498 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
21499 | | /* NMADD_D32_MM */ |
21500 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
21501 | | /* NMADD_D64 */ |
21502 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21503 | | /* NMADD_S */ |
21504 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21505 | | /* NMADD_S_MM */ |
21506 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21507 | | /* NMSUB_D32 */ |
21508 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
21509 | | /* NMSUB_D32_MM */ |
21510 | | AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, AFGR64Opnd, |
21511 | | /* NMSUB_D64 */ |
21512 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21513 | | /* NMSUB_S */ |
21514 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21515 | | /* NMSUB_S_MM */ |
21516 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21517 | | /* NOR */ |
21518 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21519 | | /* NOR64 */ |
21520 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21521 | | /* NORI_B */ |
21522 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
21523 | | /* NOR_MM */ |
21524 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21525 | | /* NOR_MMR6 */ |
21526 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21527 | | /* NOR_V */ |
21528 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21529 | | /* NOT16_MM */ |
21530 | | GPRMM16Opnd, GPRMM16Opnd, |
21531 | | /* NOT16_MMR6 */ |
21532 | | GPRMM16Opnd, GPRMM16Opnd, |
21533 | | /* NegRxRy16 */ |
21534 | | CPU16Regs, CPU16Regs, |
21535 | | /* NotRxRy16 */ |
21536 | | CPU16Regs, CPU16Regs, |
21537 | | /* OR */ |
21538 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21539 | | /* OR16_MM */ |
21540 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
21541 | | /* OR16_MMR6 */ |
21542 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
21543 | | /* OR64 */ |
21544 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21545 | | /* ORI_B */ |
21546 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
21547 | | /* ORI_MMR6 */ |
21548 | | GPR32Opnd, GPR32Opnd, uimm16, |
21549 | | /* OR_MM */ |
21550 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21551 | | /* OR_MMR6 */ |
21552 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21553 | | /* OR_V */ |
21554 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21555 | | /* ORi */ |
21556 | | GPR32Opnd, GPR32Opnd, uimm16, |
21557 | | /* ORi64 */ |
21558 | | GPR64Opnd, GPR64Opnd, uimm16_64, |
21559 | | /* ORi_MM */ |
21560 | | GPR32Opnd, GPR32Opnd, uimm16, |
21561 | | /* OrRxRxRy16 */ |
21562 | | CPU16Regs, CPU16Regs, CPU16Regs, |
21563 | | /* PACKRL_PH */ |
21564 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21565 | | /* PACKRL_PH_MM */ |
21566 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21567 | | /* PAUSE */ |
21568 | | /* PAUSE_MM */ |
21569 | | /* PAUSE_MMR6 */ |
21570 | | /* PCKEV_B */ |
21571 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21572 | | /* PCKEV_D */ |
21573 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21574 | | /* PCKEV_H */ |
21575 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21576 | | /* PCKEV_W */ |
21577 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21578 | | /* PCKOD_B */ |
21579 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
21580 | | /* PCKOD_D */ |
21581 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
21582 | | /* PCKOD_H */ |
21583 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
21584 | | /* PCKOD_W */ |
21585 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
21586 | | /* PCNT_B */ |
21587 | | MSA128BOpnd, MSA128BOpnd, |
21588 | | /* PCNT_D */ |
21589 | | MSA128DOpnd, MSA128DOpnd, |
21590 | | /* PCNT_H */ |
21591 | | MSA128HOpnd, MSA128HOpnd, |
21592 | | /* PCNT_W */ |
21593 | | MSA128WOpnd, MSA128WOpnd, |
21594 | | /* PICK_PH */ |
21595 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21596 | | /* PICK_PH_MM */ |
21597 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21598 | | /* PICK_QB */ |
21599 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21600 | | /* PICK_QB_MM */ |
21601 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21602 | | /* PLL_PS64 */ |
21603 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21604 | | /* PLU_PS64 */ |
21605 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21606 | | /* POP */ |
21607 | | GPR32Opnd, GPR32Opnd, |
21608 | | /* PRECEQU_PH_QBL */ |
21609 | | DSPROpnd, DSPROpnd, |
21610 | | /* PRECEQU_PH_QBLA */ |
21611 | | DSPROpnd, DSPROpnd, |
21612 | | /* PRECEQU_PH_QBLA_MM */ |
21613 | | DSPROpnd, DSPROpnd, |
21614 | | /* PRECEQU_PH_QBL_MM */ |
21615 | | DSPROpnd, DSPROpnd, |
21616 | | /* PRECEQU_PH_QBR */ |
21617 | | DSPROpnd, DSPROpnd, |
21618 | | /* PRECEQU_PH_QBRA */ |
21619 | | DSPROpnd, DSPROpnd, |
21620 | | /* PRECEQU_PH_QBRA_MM */ |
21621 | | DSPROpnd, DSPROpnd, |
21622 | | /* PRECEQU_PH_QBR_MM */ |
21623 | | DSPROpnd, DSPROpnd, |
21624 | | /* PRECEQ_W_PHL */ |
21625 | | GPR32Opnd, DSPROpnd, |
21626 | | /* PRECEQ_W_PHL_MM */ |
21627 | | GPR32Opnd, DSPROpnd, |
21628 | | /* PRECEQ_W_PHR */ |
21629 | | GPR32Opnd, DSPROpnd, |
21630 | | /* PRECEQ_W_PHR_MM */ |
21631 | | GPR32Opnd, DSPROpnd, |
21632 | | /* PRECEU_PH_QBL */ |
21633 | | DSPROpnd, DSPROpnd, |
21634 | | /* PRECEU_PH_QBLA */ |
21635 | | DSPROpnd, DSPROpnd, |
21636 | | /* PRECEU_PH_QBLA_MM */ |
21637 | | DSPROpnd, DSPROpnd, |
21638 | | /* PRECEU_PH_QBL_MM */ |
21639 | | DSPROpnd, DSPROpnd, |
21640 | | /* PRECEU_PH_QBR */ |
21641 | | DSPROpnd, DSPROpnd, |
21642 | | /* PRECEU_PH_QBRA */ |
21643 | | DSPROpnd, DSPROpnd, |
21644 | | /* PRECEU_PH_QBRA_MM */ |
21645 | | DSPROpnd, DSPROpnd, |
21646 | | /* PRECEU_PH_QBR_MM */ |
21647 | | DSPROpnd, DSPROpnd, |
21648 | | /* PRECRQU_S_QB_PH */ |
21649 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21650 | | /* PRECRQU_S_QB_PH_MM */ |
21651 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21652 | | /* PRECRQ_PH_W */ |
21653 | | DSPROpnd, GPR32Opnd, GPR32Opnd, |
21654 | | /* PRECRQ_PH_W_MM */ |
21655 | | DSPROpnd, GPR32Opnd, GPR32Opnd, |
21656 | | /* PRECRQ_QB_PH */ |
21657 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21658 | | /* PRECRQ_QB_PH_MM */ |
21659 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21660 | | /* PRECRQ_RS_PH_W */ |
21661 | | DSPROpnd, GPR32Opnd, GPR32Opnd, |
21662 | | /* PRECRQ_RS_PH_W_MM */ |
21663 | | DSPROpnd, GPR32Opnd, GPR32Opnd, |
21664 | | /* PRECR_QB_PH */ |
21665 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21666 | | /* PRECR_QB_PH_MMR2 */ |
21667 | | DSPROpnd, DSPROpnd, DSPROpnd, |
21668 | | /* PRECR_SRA_PH_W */ |
21669 | | DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
21670 | | /* PRECR_SRA_PH_W_MMR2 */ |
21671 | | DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
21672 | | /* PRECR_SRA_R_PH_W */ |
21673 | | DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
21674 | | /* PRECR_SRA_R_PH_W_MMR2 */ |
21675 | | DSPROpnd, GPR32Opnd, uimm5, GPR32Opnd, |
21676 | | /* PREF */ |
21677 | | -1, simm16, uimm5, |
21678 | | /* PREFE */ |
21679 | | -1, simm9, uimm5, |
21680 | | /* PREFE_MM */ |
21681 | | -1, simm9, uimm5, |
21682 | | /* PREFX_MM */ |
21683 | | -1, -1, uimm5, |
21684 | | /* PREF_MM */ |
21685 | | -1, simm12, uimm5, |
21686 | | /* PREF_MMR6 */ |
21687 | | -1, simm12, uimm5, |
21688 | | /* PREF_R6 */ |
21689 | | -1, simm9, uimm5, |
21690 | | /* PREPEND */ |
21691 | | GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
21692 | | /* PREPEND_MMR2 */ |
21693 | | GPR32Opnd, GPR32Opnd, uimm5, GPR32Opnd, |
21694 | | /* PUL_PS64 */ |
21695 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21696 | | /* PUU_PS64 */ |
21697 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21698 | | /* RADDU_W_QB */ |
21699 | | GPR32Opnd, DSPROpnd, |
21700 | | /* RADDU_W_QB_MM */ |
21701 | | GPR32Opnd, DSPROpnd, |
21702 | | /* RDDSP */ |
21703 | | GPR32Opnd, uimm10, |
21704 | | /* RDDSP_MM */ |
21705 | | GPR32Opnd, uimm7, |
21706 | | /* RDHWR */ |
21707 | | GPR32Opnd, HWRegsOpnd, uimm8, |
21708 | | /* RDHWR64 */ |
21709 | | GPR64Opnd, HWRegsOpnd, uimm8, |
21710 | | /* RDHWR_MM */ |
21711 | | GPR32Opnd, HWRegsOpnd, uimm8, |
21712 | | /* RDHWR_MMR6 */ |
21713 | | GPR32Opnd, HWRegsOpnd, uimm3, |
21714 | | /* RDPGPR_MMR6 */ |
21715 | | GPR32Opnd, GPR32Opnd, |
21716 | | /* RECIP_D32 */ |
21717 | | AFGR64Opnd, AFGR64Opnd, |
21718 | | /* RECIP_D32_MM */ |
21719 | | AFGR64Opnd, AFGR64Opnd, |
21720 | | /* RECIP_D64 */ |
21721 | | FGR64Opnd, FGR64Opnd, |
21722 | | /* RECIP_D64_MM */ |
21723 | | FGR64Opnd, FGR64Opnd, |
21724 | | /* RECIP_S */ |
21725 | | FGR32Opnd, FGR32Opnd, |
21726 | | /* RECIP_S_MM */ |
21727 | | FGR32Opnd, FGR32Opnd, |
21728 | | /* REPLV_PH */ |
21729 | | DSPROpnd, GPR32Opnd, |
21730 | | /* REPLV_PH_MM */ |
21731 | | DSPROpnd, GPR32Opnd, |
21732 | | /* REPLV_QB */ |
21733 | | DSPROpnd, GPR32Opnd, |
21734 | | /* REPLV_QB_MM */ |
21735 | | DSPROpnd, GPR32Opnd, |
21736 | | /* REPL_PH */ |
21737 | | DSPROpnd, simm10, |
21738 | | /* REPL_PH_MM */ |
21739 | | DSPROpnd, simm10, |
21740 | | /* REPL_QB */ |
21741 | | DSPROpnd, uimm8, |
21742 | | /* REPL_QB_MM */ |
21743 | | DSPROpnd, uimm8, |
21744 | | /* RINT_D */ |
21745 | | FGR64Opnd, FGR64Opnd, |
21746 | | /* RINT_D_MMR6 */ |
21747 | | FGR64Opnd, FGR64Opnd, |
21748 | | /* RINT_S */ |
21749 | | FGR32Opnd, FGR32Opnd, |
21750 | | /* RINT_S_MMR6 */ |
21751 | | FGR32Opnd, FGR32Opnd, |
21752 | | /* ROTR */ |
21753 | | GPR32Opnd, GPR32Opnd, uimm5, |
21754 | | /* ROTRV */ |
21755 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21756 | | /* ROTRV_MM */ |
21757 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21758 | | /* ROTR_MM */ |
21759 | | GPR32Opnd, GPR32Opnd, uimm5, |
21760 | | /* ROUND_L_D64 */ |
21761 | | FGR64Opnd, FGR64Opnd, |
21762 | | /* ROUND_L_D_MMR6 */ |
21763 | | FGR64Opnd, FGR64Opnd, |
21764 | | /* ROUND_L_S */ |
21765 | | FGR64Opnd, FGR32Opnd, |
21766 | | /* ROUND_L_S_MMR6 */ |
21767 | | FGR64Opnd, FGR32Opnd, |
21768 | | /* ROUND_W_D32 */ |
21769 | | FGR32Opnd, AFGR64Opnd, |
21770 | | /* ROUND_W_D64 */ |
21771 | | FGR32Opnd, FGR64Opnd, |
21772 | | /* ROUND_W_D_MMR6 */ |
21773 | | FGR64Opnd, FGR64Opnd, |
21774 | | /* ROUND_W_MM */ |
21775 | | FGR32Opnd, AFGR64Opnd, |
21776 | | /* ROUND_W_S */ |
21777 | | FGR32Opnd, FGR32Opnd, |
21778 | | /* ROUND_W_S_MM */ |
21779 | | FGR32Opnd, FGR32Opnd, |
21780 | | /* ROUND_W_S_MMR6 */ |
21781 | | FGR32Opnd, FGR32Opnd, |
21782 | | /* RSQRT_D32 */ |
21783 | | AFGR64Opnd, AFGR64Opnd, |
21784 | | /* RSQRT_D32_MM */ |
21785 | | AFGR64Opnd, AFGR64Opnd, |
21786 | | /* RSQRT_D64 */ |
21787 | | FGR64Opnd, FGR64Opnd, |
21788 | | /* RSQRT_D64_MM */ |
21789 | | FGR64Opnd, FGR64Opnd, |
21790 | | /* RSQRT_S */ |
21791 | | FGR32Opnd, FGR32Opnd, |
21792 | | /* RSQRT_S_MM */ |
21793 | | FGR32Opnd, FGR32Opnd, |
21794 | | /* Restore16 */ |
21795 | | /* RestoreX16 */ |
21796 | | /* SAA */ |
21797 | | GPR64Opnd, GPR64Opnd, |
21798 | | /* SAAD */ |
21799 | | GPR64Opnd, GPR64Opnd, |
21800 | | /* SAT_S_B */ |
21801 | | MSA128BOpnd, MSA128BOpnd, uimm3, |
21802 | | /* SAT_S_D */ |
21803 | | MSA128DOpnd, MSA128DOpnd, uimm6, |
21804 | | /* SAT_S_H */ |
21805 | | MSA128HOpnd, MSA128HOpnd, uimm4, |
21806 | | /* SAT_S_W */ |
21807 | | MSA128WOpnd, MSA128WOpnd, uimm5, |
21808 | | /* SAT_U_B */ |
21809 | | MSA128BOpnd, MSA128BOpnd, uimm3, |
21810 | | /* SAT_U_D */ |
21811 | | MSA128DOpnd, MSA128DOpnd, uimm6, |
21812 | | /* SAT_U_H */ |
21813 | | MSA128HOpnd, MSA128HOpnd, uimm4, |
21814 | | /* SAT_U_W */ |
21815 | | MSA128WOpnd, MSA128WOpnd, uimm5, |
21816 | | /* SB */ |
21817 | | GPR32Opnd, -1, simm16, |
21818 | | /* SB16_MM */ |
21819 | | GPRMM16OpndZero, -1, simm4, |
21820 | | /* SB16_MMR6 */ |
21821 | | GPRMM16OpndZero, -1, simm4, |
21822 | | /* SB64 */ |
21823 | | GPR64Opnd, -1, simm16, |
21824 | | /* SBE */ |
21825 | | GPR32Opnd, -1, simm9, |
21826 | | /* SBE_MM */ |
21827 | | GPR32Opnd, -1, simm9, |
21828 | | /* SB_MM */ |
21829 | | GPR32Opnd, -1, simm16, |
21830 | | /* SB_MMR6 */ |
21831 | | GPR32Opnd, -1, simm16, |
21832 | | /* SC */ |
21833 | | GPR32Opnd, GPR32Opnd, -1, simm16, |
21834 | | /* SC64 */ |
21835 | | GPR32Opnd, GPR32Opnd, -1, simm16, |
21836 | | /* SC64_R6 */ |
21837 | | GPR32Opnd, GPR32Opnd, -1, simm9, |
21838 | | /* SCD */ |
21839 | | GPR64Opnd, GPR64Opnd, -1, simm16, |
21840 | | /* SCD_R6 */ |
21841 | | GPR64Opnd, GPR64Opnd, -1, simm9, |
21842 | | /* SCE */ |
21843 | | GPR32Opnd, GPR32Opnd, -1, simm9, |
21844 | | /* SCE_MM */ |
21845 | | GPR32Opnd, GPR32Opnd, -1, simm9, |
21846 | | /* SC_MM */ |
21847 | | GPR32Opnd, GPR32Opnd, -1, simm12, |
21848 | | /* SC_MMR6 */ |
21849 | | GPR32Opnd, GPR32Opnd, -1, simm9, |
21850 | | /* SC_R6 */ |
21851 | | GPR32Opnd, GPR32Opnd, -1, simm9, |
21852 | | /* SD */ |
21853 | | GPR64Opnd, -1, simm16, |
21854 | | /* SDBBP */ |
21855 | | uimm20, |
21856 | | /* SDBBP16_MM */ |
21857 | | uimm4, |
21858 | | /* SDBBP16_MMR6 */ |
21859 | | uimm4, |
21860 | | /* SDBBP_MM */ |
21861 | | uimm10, |
21862 | | /* SDBBP_MMR6 */ |
21863 | | uimm20, |
21864 | | /* SDBBP_R6 */ |
21865 | | uimm20, |
21866 | | /* SDC1 */ |
21867 | | AFGR64Opnd, -1, simm16, |
21868 | | /* SDC164 */ |
21869 | | FGR64Opnd, -1, simm16, |
21870 | | /* SDC1_D64_MMR6 */ |
21871 | | FGR64Opnd, -1, simm16, |
21872 | | /* SDC1_MM_D32 */ |
21873 | | AFGR64Opnd, -1, simm16, |
21874 | | /* SDC1_MM_D64 */ |
21875 | | FGR64Opnd, -1, simm16, |
21876 | | /* SDC2 */ |
21877 | | COP2Opnd, -1, simm16, |
21878 | | /* SDC2_MMR6 */ |
21879 | | COP2Opnd, GPR32, simm11, |
21880 | | /* SDC2_R6 */ |
21881 | | COP2Opnd, -1, simm11, |
21882 | | /* SDC3 */ |
21883 | | COP3Opnd, -1, simm16, |
21884 | | /* SDIV */ |
21885 | | GPR32Opnd, GPR32Opnd, |
21886 | | /* SDIV_MM */ |
21887 | | GPR32Opnd, GPR32Opnd, |
21888 | | /* SDL */ |
21889 | | GPR64Opnd, -1, simm16, |
21890 | | /* SDR */ |
21891 | | GPR64Opnd, -1, simm16, |
21892 | | /* SDXC1 */ |
21893 | | AFGR64Opnd, -1, -1, |
21894 | | /* SDXC164 */ |
21895 | | FGR64Opnd, -1, -1, |
21896 | | /* SEB */ |
21897 | | GPR32Opnd, GPR32Opnd, |
21898 | | /* SEB64 */ |
21899 | | GPR64Opnd, GPR64Opnd, |
21900 | | /* SEB_MM */ |
21901 | | GPR32Opnd, GPR32Opnd, |
21902 | | /* SEH */ |
21903 | | GPR32Opnd, GPR32Opnd, |
21904 | | /* SEH64 */ |
21905 | | GPR64Opnd, GPR64Opnd, |
21906 | | /* SEH_MM */ |
21907 | | GPR32Opnd, GPR32Opnd, |
21908 | | /* SELEQZ */ |
21909 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21910 | | /* SELEQZ64 */ |
21911 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21912 | | /* SELEQZ_D */ |
21913 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21914 | | /* SELEQZ_D_MMR6 */ |
21915 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21916 | | /* SELEQZ_MMR6 */ |
21917 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21918 | | /* SELEQZ_S */ |
21919 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21920 | | /* SELEQZ_S_MMR6 */ |
21921 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21922 | | /* SELNEZ */ |
21923 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21924 | | /* SELNEZ64 */ |
21925 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21926 | | /* SELNEZ_D */ |
21927 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21928 | | /* SELNEZ_D_MMR6 */ |
21929 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21930 | | /* SELNEZ_MMR6 */ |
21931 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21932 | | /* SELNEZ_S */ |
21933 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21934 | | /* SELNEZ_S_MMR6 */ |
21935 | | FGR32Opnd, FGR32Opnd, FGR32Opnd, |
21936 | | /* SEL_D */ |
21937 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21938 | | /* SEL_D_MMR6 */ |
21939 | | FGR64Opnd, FGR64Opnd, FGR64Opnd, FGR64Opnd, |
21940 | | /* SEL_S */ |
21941 | | FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
21942 | | /* SEL_S_MMR6 */ |
21943 | | FGR32Opnd, FGRCCOpnd, FGR32Opnd, FGR32Opnd, |
21944 | | /* SEQ */ |
21945 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
21946 | | /* SEQi */ |
21947 | | GPR64Opnd, GPR64Opnd, simm10_64, |
21948 | | /* SH */ |
21949 | | GPR32Opnd, -1, simm16, |
21950 | | /* SH16_MM */ |
21951 | | GPRMM16OpndZero, -1, simm4, |
21952 | | /* SH16_MMR6 */ |
21953 | | GPRMM16OpndZero, -1, simm4, |
21954 | | /* SH64 */ |
21955 | | GPR64Opnd, -1, simm16, |
21956 | | /* SHE */ |
21957 | | GPR32Opnd, -1, simm9, |
21958 | | /* SHE_MM */ |
21959 | | GPR32Opnd, -1, simm9, |
21960 | | /* SHF_B */ |
21961 | | MSA128BOpnd, MSA128BOpnd, uimm8, |
21962 | | /* SHF_H */ |
21963 | | MSA128HOpnd, MSA128HOpnd, uimm8, |
21964 | | /* SHF_W */ |
21965 | | MSA128WOpnd, MSA128WOpnd, uimm8, |
21966 | | /* SHILO */ |
21967 | | ACC64DSPOpnd, simm6, ACC64DSPOpnd, |
21968 | | /* SHILOV */ |
21969 | | ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
21970 | | /* SHILOV_MM */ |
21971 | | ACC64DSPOpnd, GPR32Opnd, ACC64DSPOpnd, |
21972 | | /* SHILO_MM */ |
21973 | | ACC64DSPOpnd, simm6, ACC64DSPOpnd, |
21974 | | /* SHLLV_PH */ |
21975 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
21976 | | /* SHLLV_PH_MM */ |
21977 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
21978 | | /* SHLLV_QB */ |
21979 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
21980 | | /* SHLLV_QB_MM */ |
21981 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
21982 | | /* SHLLV_S_PH */ |
21983 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
21984 | | /* SHLLV_S_PH_MM */ |
21985 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
21986 | | /* SHLLV_S_W */ |
21987 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21988 | | /* SHLLV_S_W_MM */ |
21989 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
21990 | | /* SHLL_PH */ |
21991 | | DSPROpnd, DSPROpnd, uimm4, |
21992 | | /* SHLL_PH_MM */ |
21993 | | DSPROpnd, DSPROpnd, uimm4, |
21994 | | /* SHLL_QB */ |
21995 | | DSPROpnd, DSPROpnd, uimm3, |
21996 | | /* SHLL_QB_MM */ |
21997 | | DSPROpnd, DSPROpnd, uimm3, |
21998 | | /* SHLL_S_PH */ |
21999 | | DSPROpnd, DSPROpnd, uimm4, |
22000 | | /* SHLL_S_PH_MM */ |
22001 | | DSPROpnd, DSPROpnd, uimm4, |
22002 | | /* SHLL_S_W */ |
22003 | | GPR32Opnd, GPR32Opnd, uimm5, |
22004 | | /* SHLL_S_W_MM */ |
22005 | | GPR32Opnd, GPR32Opnd, uimm5, |
22006 | | /* SHRAV_PH */ |
22007 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22008 | | /* SHRAV_PH_MM */ |
22009 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22010 | | /* SHRAV_QB */ |
22011 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22012 | | /* SHRAV_QB_MMR2 */ |
22013 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22014 | | /* SHRAV_R_PH */ |
22015 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22016 | | /* SHRAV_R_PH_MM */ |
22017 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22018 | | /* SHRAV_R_QB */ |
22019 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22020 | | /* SHRAV_R_QB_MMR2 */ |
22021 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22022 | | /* SHRAV_R_W */ |
22023 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22024 | | /* SHRAV_R_W_MM */ |
22025 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22026 | | /* SHRA_PH */ |
22027 | | DSPROpnd, DSPROpnd, uimm4, |
22028 | | /* SHRA_PH_MM */ |
22029 | | DSPROpnd, DSPROpnd, uimm4, |
22030 | | /* SHRA_QB */ |
22031 | | DSPROpnd, DSPROpnd, uimm3, |
22032 | | /* SHRA_QB_MMR2 */ |
22033 | | DSPROpnd, DSPROpnd, uimm3, |
22034 | | /* SHRA_R_PH */ |
22035 | | DSPROpnd, DSPROpnd, uimm4, |
22036 | | /* SHRA_R_PH_MM */ |
22037 | | DSPROpnd, DSPROpnd, uimm4, |
22038 | | /* SHRA_R_QB */ |
22039 | | DSPROpnd, DSPROpnd, uimm3, |
22040 | | /* SHRA_R_QB_MMR2 */ |
22041 | | DSPROpnd, DSPROpnd, uimm3, |
22042 | | /* SHRA_R_W */ |
22043 | | GPR32Opnd, GPR32Opnd, uimm5, |
22044 | | /* SHRA_R_W_MM */ |
22045 | | GPR32Opnd, GPR32Opnd, uimm5, |
22046 | | /* SHRLV_PH */ |
22047 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22048 | | /* SHRLV_PH_MMR2 */ |
22049 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22050 | | /* SHRLV_QB */ |
22051 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22052 | | /* SHRLV_QB_MM */ |
22053 | | DSPROpnd, DSPROpnd, GPR32Opnd, |
22054 | | /* SHRL_PH */ |
22055 | | DSPROpnd, DSPROpnd, uimm4, |
22056 | | /* SHRL_PH_MMR2 */ |
22057 | | DSPROpnd, DSPROpnd, uimm4, |
22058 | | /* SHRL_QB */ |
22059 | | DSPROpnd, DSPROpnd, uimm3, |
22060 | | /* SHRL_QB_MM */ |
22061 | | DSPROpnd, DSPROpnd, uimm3, |
22062 | | /* SH_MM */ |
22063 | | GPR32Opnd, -1, simm16, |
22064 | | /* SH_MMR6 */ |
22065 | | GPR32Opnd, -1, simm16, |
22066 | | /* SIGRIE */ |
22067 | | uimm16, |
22068 | | /* SIGRIE_MMR6 */ |
22069 | | uimm16, |
22070 | | /* SLDI_B */ |
22071 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, uimm4, |
22072 | | /* SLDI_D */ |
22073 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, uimm1, |
22074 | | /* SLDI_H */ |
22075 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, uimm3, |
22076 | | /* SLDI_W */ |
22077 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, uimm2, |
22078 | | /* SLD_B */ |
22079 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, GPR32Opnd, |
22080 | | /* SLD_D */ |
22081 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, GPR32Opnd, |
22082 | | /* SLD_H */ |
22083 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, GPR32Opnd, |
22084 | | /* SLD_W */ |
22085 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, GPR32Opnd, |
22086 | | /* SLL */ |
22087 | | GPR32Opnd, GPR32Opnd, uimm5, |
22088 | | /* SLL16_MM */ |
22089 | | GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
22090 | | /* SLL16_MMR6 */ |
22091 | | GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
22092 | | /* SLL64_32 */ |
22093 | | GPR64, GPR32, |
22094 | | /* SLL64_64 */ |
22095 | | GPR64, GPR64, |
22096 | | /* SLLI_B */ |
22097 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
22098 | | /* SLLI_D */ |
22099 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
22100 | | /* SLLI_H */ |
22101 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
22102 | | /* SLLI_W */ |
22103 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
22104 | | /* SLLV */ |
22105 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22106 | | /* SLLV_MM */ |
22107 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22108 | | /* SLL_B */ |
22109 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22110 | | /* SLL_D */ |
22111 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22112 | | /* SLL_H */ |
22113 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22114 | | /* SLL_MM */ |
22115 | | GPR32Opnd, GPR32Opnd, uimm5, |
22116 | | /* SLL_MMR6 */ |
22117 | | GPR32Opnd, GPR32Opnd, uimm5, |
22118 | | /* SLL_W */ |
22119 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22120 | | /* SLT */ |
22121 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22122 | | /* SLT64 */ |
22123 | | GPR32Opnd, GPR64Opnd, GPR64Opnd, |
22124 | | /* SLT_MM */ |
22125 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22126 | | /* SLTi */ |
22127 | | GPR32Opnd, GPR32Opnd, simm16, |
22128 | | /* SLTi64 */ |
22129 | | GPR32Opnd, GPR64Opnd, simm16_64, |
22130 | | /* SLTi_MM */ |
22131 | | GPR32Opnd, GPR32Opnd, simm16, |
22132 | | /* SLTiu */ |
22133 | | GPR32Opnd, GPR32Opnd, simm16, |
22134 | | /* SLTiu64 */ |
22135 | | GPR32Opnd, GPR64Opnd, simm16_64, |
22136 | | /* SLTiu_MM */ |
22137 | | GPR32Opnd, GPR32Opnd, simm16, |
22138 | | /* SLTu */ |
22139 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22140 | | /* SLTu64 */ |
22141 | | GPR32Opnd, GPR64Opnd, GPR64Opnd, |
22142 | | /* SLTu_MM */ |
22143 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22144 | | /* SNE */ |
22145 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
22146 | | /* SNEi */ |
22147 | | GPR64Opnd, GPR64Opnd, simm10_64, |
22148 | | /* SPLATI_B */ |
22149 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm4, |
22150 | | /* SPLATI_D */ |
22151 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm1, |
22152 | | /* SPLATI_H */ |
22153 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm3, |
22154 | | /* SPLATI_W */ |
22155 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm2, |
22156 | | /* SPLAT_B */ |
22157 | | MSA128BOpnd, MSA128BOpnd, GPR32Opnd, |
22158 | | /* SPLAT_D */ |
22159 | | MSA128DOpnd, MSA128DOpnd, GPR32Opnd, |
22160 | | /* SPLAT_H */ |
22161 | | MSA128HOpnd, MSA128HOpnd, GPR32Opnd, |
22162 | | /* SPLAT_W */ |
22163 | | MSA128WOpnd, MSA128WOpnd, GPR32Opnd, |
22164 | | /* SRA */ |
22165 | | GPR32Opnd, GPR32Opnd, uimm5, |
22166 | | /* SRAI_B */ |
22167 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
22168 | | /* SRAI_D */ |
22169 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
22170 | | /* SRAI_H */ |
22171 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
22172 | | /* SRAI_W */ |
22173 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
22174 | | /* SRARI_B */ |
22175 | | MSA128BOpnd, MSA128BOpnd, uimm3, |
22176 | | /* SRARI_D */ |
22177 | | MSA128DOpnd, MSA128DOpnd, uimm6, |
22178 | | /* SRARI_H */ |
22179 | | MSA128HOpnd, MSA128HOpnd, uimm4, |
22180 | | /* SRARI_W */ |
22181 | | MSA128WOpnd, MSA128WOpnd, uimm5, |
22182 | | /* SRAR_B */ |
22183 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22184 | | /* SRAR_D */ |
22185 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22186 | | /* SRAR_H */ |
22187 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22188 | | /* SRAR_W */ |
22189 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22190 | | /* SRAV */ |
22191 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22192 | | /* SRAV_MM */ |
22193 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22194 | | /* SRA_B */ |
22195 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22196 | | /* SRA_D */ |
22197 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22198 | | /* SRA_H */ |
22199 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22200 | | /* SRA_MM */ |
22201 | | GPR32Opnd, GPR32Opnd, uimm5, |
22202 | | /* SRA_W */ |
22203 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22204 | | /* SRL */ |
22205 | | GPR32Opnd, GPR32Opnd, uimm5, |
22206 | | /* SRL16_MM */ |
22207 | | GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
22208 | | /* SRL16_MMR6 */ |
22209 | | GPRMM16Opnd, GPRMM16Opnd, uimm3_shift, |
22210 | | /* SRLI_B */ |
22211 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm3, |
22212 | | /* SRLI_D */ |
22213 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm6, |
22214 | | /* SRLI_H */ |
22215 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm4, |
22216 | | /* SRLI_W */ |
22217 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
22218 | | /* SRLRI_B */ |
22219 | | MSA128BOpnd, MSA128BOpnd, uimm3, |
22220 | | /* SRLRI_D */ |
22221 | | MSA128DOpnd, MSA128DOpnd, uimm6, |
22222 | | /* SRLRI_H */ |
22223 | | MSA128HOpnd, MSA128HOpnd, uimm4, |
22224 | | /* SRLRI_W */ |
22225 | | MSA128WOpnd, MSA128WOpnd, uimm5, |
22226 | | /* SRLR_B */ |
22227 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22228 | | /* SRLR_D */ |
22229 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22230 | | /* SRLR_H */ |
22231 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22232 | | /* SRLR_W */ |
22233 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22234 | | /* SRLV */ |
22235 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22236 | | /* SRLV_MM */ |
22237 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22238 | | /* SRL_B */ |
22239 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22240 | | /* SRL_D */ |
22241 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22242 | | /* SRL_H */ |
22243 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22244 | | /* SRL_MM */ |
22245 | | GPR32Opnd, GPR32Opnd, uimm5, |
22246 | | /* SRL_W */ |
22247 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22248 | | /* SSNOP */ |
22249 | | /* SSNOP_MM */ |
22250 | | /* SSNOP_MMR6 */ |
22251 | | /* ST_B */ |
22252 | | MSA128BOpnd, -1, simm10, |
22253 | | /* ST_D */ |
22254 | | MSA128DOpnd, -1, simm10_lsl3, |
22255 | | /* ST_H */ |
22256 | | MSA128HOpnd, -1, simm10_lsl1, |
22257 | | /* ST_W */ |
22258 | | MSA128WOpnd, -1, simm10_lsl2, |
22259 | | /* SUB */ |
22260 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22261 | | /* SUBQH_PH */ |
22262 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22263 | | /* SUBQH_PH_MMR2 */ |
22264 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22265 | | /* SUBQH_R_PH */ |
22266 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22267 | | /* SUBQH_R_PH_MMR2 */ |
22268 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22269 | | /* SUBQH_R_W */ |
22270 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22271 | | /* SUBQH_R_W_MMR2 */ |
22272 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22273 | | /* SUBQH_W */ |
22274 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22275 | | /* SUBQH_W_MMR2 */ |
22276 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22277 | | /* SUBQ_PH */ |
22278 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22279 | | /* SUBQ_PH_MM */ |
22280 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22281 | | /* SUBQ_S_PH */ |
22282 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22283 | | /* SUBQ_S_PH_MM */ |
22284 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22285 | | /* SUBQ_S_W */ |
22286 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22287 | | /* SUBQ_S_W_MM */ |
22288 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22289 | | /* SUBSUS_U_B */ |
22290 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22291 | | /* SUBSUS_U_D */ |
22292 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22293 | | /* SUBSUS_U_H */ |
22294 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22295 | | /* SUBSUS_U_W */ |
22296 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22297 | | /* SUBSUU_S_B */ |
22298 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22299 | | /* SUBSUU_S_D */ |
22300 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22301 | | /* SUBSUU_S_H */ |
22302 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22303 | | /* SUBSUU_S_W */ |
22304 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22305 | | /* SUBS_S_B */ |
22306 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22307 | | /* SUBS_S_D */ |
22308 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22309 | | /* SUBS_S_H */ |
22310 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22311 | | /* SUBS_S_W */ |
22312 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22313 | | /* SUBS_U_B */ |
22314 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22315 | | /* SUBS_U_D */ |
22316 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22317 | | /* SUBS_U_H */ |
22318 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22319 | | /* SUBS_U_W */ |
22320 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22321 | | /* SUBU16_MM */ |
22322 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
22323 | | /* SUBU16_MMR6 */ |
22324 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
22325 | | /* SUBUH_QB */ |
22326 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22327 | | /* SUBUH_QB_MMR2 */ |
22328 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22329 | | /* SUBUH_R_QB */ |
22330 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22331 | | /* SUBUH_R_QB_MMR2 */ |
22332 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22333 | | /* SUBU_MMR6 */ |
22334 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22335 | | /* SUBU_PH */ |
22336 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22337 | | /* SUBU_PH_MMR2 */ |
22338 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22339 | | /* SUBU_QB */ |
22340 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22341 | | /* SUBU_QB_MM */ |
22342 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22343 | | /* SUBU_S_PH */ |
22344 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22345 | | /* SUBU_S_PH_MMR2 */ |
22346 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22347 | | /* SUBU_S_QB */ |
22348 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22349 | | /* SUBU_S_QB_MM */ |
22350 | | DSPROpnd, DSPROpnd, DSPROpnd, |
22351 | | /* SUBVI_B */ |
22352 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm5, |
22353 | | /* SUBVI_D */ |
22354 | | MSA128DOpnd, MSA128DOpnd, vsplat_uimm5, |
22355 | | /* SUBVI_H */ |
22356 | | MSA128HOpnd, MSA128HOpnd, vsplat_uimm5, |
22357 | | /* SUBVI_W */ |
22358 | | MSA128WOpnd, MSA128WOpnd, vsplat_uimm5, |
22359 | | /* SUBV_B */ |
22360 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22361 | | /* SUBV_D */ |
22362 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22363 | | /* SUBV_H */ |
22364 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22365 | | /* SUBV_W */ |
22366 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22367 | | /* SUB_MM */ |
22368 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22369 | | /* SUB_MMR6 */ |
22370 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22371 | | /* SUBu */ |
22372 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22373 | | /* SUBu_MM */ |
22374 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22375 | | /* SUXC1 */ |
22376 | | AFGR64Opnd, -1, -1, |
22377 | | /* SUXC164 */ |
22378 | | FGR64Opnd, -1, -1, |
22379 | | /* SUXC1_MM */ |
22380 | | FGR64Opnd, -1, -1, |
22381 | | /* SW */ |
22382 | | GPR32Opnd, -1, simm16, |
22383 | | /* SW16_MM */ |
22384 | | GPRMM16OpndZero, -1, simm4, |
22385 | | /* SW16_MMR6 */ |
22386 | | GPRMM16OpndZero, -1, simm4, |
22387 | | /* SW64 */ |
22388 | | GPR64Opnd, -1, simm16, |
22389 | | /* SWC1 */ |
22390 | | FGR32Opnd, -1, simm16, |
22391 | | /* SWC1_MM */ |
22392 | | FGR32Opnd, -1, simm16, |
22393 | | /* SWC2 */ |
22394 | | COP2Opnd, -1, simm16, |
22395 | | /* SWC2_MMR6 */ |
22396 | | COP2Opnd, GPR32, simm11, |
22397 | | /* SWC2_R6 */ |
22398 | | COP2Opnd, -1, simm11, |
22399 | | /* SWC3 */ |
22400 | | COP3Opnd, -1, simm16, |
22401 | | /* SWDSP */ |
22402 | | DSPROpnd, -1, simm16, |
22403 | | /* SWDSP_MM */ |
22404 | | DSPROpnd, -1, simm16, |
22405 | | /* SWE */ |
22406 | | GPR32Opnd, -1, simm9, |
22407 | | /* SWE_MM */ |
22408 | | GPR32Opnd, -1, simm9, |
22409 | | /* SWL */ |
22410 | | GPR32Opnd, -1, simm16, |
22411 | | /* SWL64 */ |
22412 | | GPR64Opnd, -1, simm16, |
22413 | | /* SWLE */ |
22414 | | GPR32Opnd, -1, simm9, |
22415 | | /* SWLE_MM */ |
22416 | | GPR32Opnd, -1, simm9, |
22417 | | /* SWL_MM */ |
22418 | | GPR32Opnd, -1, simm12, |
22419 | | /* SWM16_MM */ |
22420 | | reglist16, -1, uimm8, |
22421 | | /* SWM16_MMR6 */ |
22422 | | reglist16, -1, uimm8, |
22423 | | /* SWM32_MM */ |
22424 | | reglist, -1, simm12, |
22425 | | /* SWP_MM */ |
22426 | | GPR32Opnd, GPR32Opnd, -1, simm12, |
22427 | | /* SWR */ |
22428 | | GPR32Opnd, -1, simm16, |
22429 | | /* SWR64 */ |
22430 | | GPR64Opnd, -1, simm16, |
22431 | | /* SWRE */ |
22432 | | GPR32Opnd, -1, simm9, |
22433 | | /* SWRE_MM */ |
22434 | | GPR32Opnd, -1, simm9, |
22435 | | /* SWR_MM */ |
22436 | | GPR32Opnd, -1, simm12, |
22437 | | /* SWSP_MM */ |
22438 | | GPR32Opnd, -1, simm5, |
22439 | | /* SWSP_MMR6 */ |
22440 | | GPR32Opnd, -1, simm5, |
22441 | | /* SWXC1 */ |
22442 | | FGR32Opnd, -1, -1, |
22443 | | /* SWXC1_MM */ |
22444 | | FGR32Opnd, -1, -1, |
22445 | | /* SW_MM */ |
22446 | | GPR32Opnd, -1, simm16, |
22447 | | /* SW_MMR6 */ |
22448 | | GPR32Opnd, -1, simm16, |
22449 | | /* SYNC */ |
22450 | | uimm5, |
22451 | | /* SYNCI */ |
22452 | | -1, simm16, |
22453 | | /* SYNCI_MM */ |
22454 | | -1, simm16, |
22455 | | /* SYNCI_MMR6 */ |
22456 | | -1, simm16, |
22457 | | /* SYNC_MM */ |
22458 | | uimm5, |
22459 | | /* SYNC_MMR6 */ |
22460 | | uimm5, |
22461 | | /* SYSCALL */ |
22462 | | uimm20, |
22463 | | /* SYSCALL_MM */ |
22464 | | uimm10, |
22465 | | /* Save16 */ |
22466 | | /* SaveX16 */ |
22467 | | /* SbRxRyOffMemX16 */ |
22468 | | CPU16Regs, CPU16Regs, simm16, |
22469 | | /* SebRx16 */ |
22470 | | CPU16Regs, CPU16Regs, |
22471 | | /* SehRx16 */ |
22472 | | CPU16Regs, CPU16Regs, |
22473 | | /* ShRxRyOffMemX16 */ |
22474 | | CPU16Regs, CPU16Regs, simm16, |
22475 | | /* SllX16 */ |
22476 | | CPU16Regs, CPU16Regs, uimm5, |
22477 | | /* SllvRxRy16 */ |
22478 | | CPU16Regs, CPU16Regs, CPU16Regs, |
22479 | | /* SltRxRy16 */ |
22480 | | CPU16Regs, CPU16Regs, |
22481 | | /* SltiRxImm16 */ |
22482 | | CPU16Regs, simm16, |
22483 | | /* SltiRxImmX16 */ |
22484 | | CPU16Regs, simm16, |
22485 | | /* SltiuRxImm16 */ |
22486 | | CPU16Regs, simm16, |
22487 | | /* SltiuRxImmX16 */ |
22488 | | CPU16Regs, simm16, |
22489 | | /* SltuRxRy16 */ |
22490 | | CPU16Regs, CPU16Regs, |
22491 | | /* SraX16 */ |
22492 | | CPU16Regs, CPU16Regs, uimm5, |
22493 | | /* SravRxRy16 */ |
22494 | | CPU16Regs, CPU16Regs, CPU16Regs, |
22495 | | /* SrlX16 */ |
22496 | | CPU16Regs, CPU16Regs, uimm5, |
22497 | | /* SrlvRxRy16 */ |
22498 | | CPU16Regs, CPU16Regs, CPU16Regs, |
22499 | | /* SubuRxRyRz16 */ |
22500 | | CPU16Regs, CPU16Regs, CPU16Regs, |
22501 | | /* SwRxRyOffMemX16 */ |
22502 | | CPU16Regs, CPU16Regs, simm16, |
22503 | | /* SwRxSpImmX16 */ |
22504 | | CPU16Regs, CPU16RegsPlusSP, simm16, |
22505 | | /* TEQ */ |
22506 | | GPR32Opnd, GPR32Opnd, uimm10, |
22507 | | /* TEQI */ |
22508 | | GPR32Opnd, simm16, |
22509 | | /* TEQI_MM */ |
22510 | | GPR32Opnd, simm16, |
22511 | | /* TEQ_MM */ |
22512 | | GPR32Opnd, GPR32Opnd, uimm4, |
22513 | | /* TGE */ |
22514 | | GPR32Opnd, GPR32Opnd, uimm10, |
22515 | | /* TGEI */ |
22516 | | GPR32Opnd, simm16, |
22517 | | /* TGEIU */ |
22518 | | GPR32Opnd, simm16, |
22519 | | /* TGEIU_MM */ |
22520 | | GPR32Opnd, simm16, |
22521 | | /* TGEI_MM */ |
22522 | | GPR32Opnd, simm16, |
22523 | | /* TGEU */ |
22524 | | GPR32Opnd, GPR32Opnd, uimm10, |
22525 | | /* TGEU_MM */ |
22526 | | GPR32Opnd, GPR32Opnd, uimm4, |
22527 | | /* TGE_MM */ |
22528 | | GPR32Opnd, GPR32Opnd, uimm4, |
22529 | | /* TLBGINV */ |
22530 | | /* TLBGINVF */ |
22531 | | /* TLBGINVF_MM */ |
22532 | | /* TLBGINV_MM */ |
22533 | | /* TLBGP */ |
22534 | | /* TLBGP_MM */ |
22535 | | /* TLBGR */ |
22536 | | /* TLBGR_MM */ |
22537 | | /* TLBGWI */ |
22538 | | /* TLBGWI_MM */ |
22539 | | /* TLBGWR */ |
22540 | | /* TLBGWR_MM */ |
22541 | | /* TLBINV */ |
22542 | | /* TLBINVF */ |
22543 | | /* TLBINVF_MMR6 */ |
22544 | | /* TLBINV_MMR6 */ |
22545 | | /* TLBP */ |
22546 | | /* TLBP_MM */ |
22547 | | /* TLBR */ |
22548 | | /* TLBR_MM */ |
22549 | | /* TLBWI */ |
22550 | | /* TLBWI_MM */ |
22551 | | /* TLBWR */ |
22552 | | /* TLBWR_MM */ |
22553 | | /* TLT */ |
22554 | | GPR32Opnd, GPR32Opnd, uimm10, |
22555 | | /* TLTI */ |
22556 | | GPR32Opnd, simm16, |
22557 | | /* TLTIU_MM */ |
22558 | | GPR32Opnd, simm16, |
22559 | | /* TLTI_MM */ |
22560 | | GPR32Opnd, simm16, |
22561 | | /* TLTU */ |
22562 | | GPR32Opnd, GPR32Opnd, uimm10, |
22563 | | /* TLTU_MM */ |
22564 | | GPR32Opnd, GPR32Opnd, uimm4, |
22565 | | /* TLT_MM */ |
22566 | | GPR32Opnd, GPR32Opnd, uimm4, |
22567 | | /* TNE */ |
22568 | | GPR32Opnd, GPR32Opnd, uimm10, |
22569 | | /* TNEI */ |
22570 | | GPR32Opnd, simm16, |
22571 | | /* TNEI_MM */ |
22572 | | GPR32Opnd, simm16, |
22573 | | /* TNE_MM */ |
22574 | | GPR32Opnd, GPR32Opnd, uimm4, |
22575 | | /* TRUNC_L_D64 */ |
22576 | | FGR64Opnd, FGR64Opnd, |
22577 | | /* TRUNC_L_D_MMR6 */ |
22578 | | FGR64Opnd, FGR64Opnd, |
22579 | | /* TRUNC_L_S */ |
22580 | | FGR64Opnd, FGR32Opnd, |
22581 | | /* TRUNC_L_S_MMR6 */ |
22582 | | FGR64Opnd, FGR32Opnd, |
22583 | | /* TRUNC_W_D32 */ |
22584 | | FGR32Opnd, AFGR64Opnd, |
22585 | | /* TRUNC_W_D64 */ |
22586 | | FGR32Opnd, FGR64Opnd, |
22587 | | /* TRUNC_W_D_MMR6 */ |
22588 | | FGR32Opnd, FGR64Opnd, |
22589 | | /* TRUNC_W_MM */ |
22590 | | FGR32Opnd, AFGR64Opnd, |
22591 | | /* TRUNC_W_S */ |
22592 | | FGR32Opnd, FGR32Opnd, |
22593 | | /* TRUNC_W_S_MM */ |
22594 | | FGR32Opnd, FGR32Opnd, |
22595 | | /* TRUNC_W_S_MMR6 */ |
22596 | | FGR32Opnd, FGR32Opnd, |
22597 | | /* TTLTIU */ |
22598 | | GPR32Opnd, simm16, |
22599 | | /* UDIV */ |
22600 | | GPR32Opnd, GPR32Opnd, |
22601 | | /* UDIV_MM */ |
22602 | | GPR32Opnd, GPR32Opnd, |
22603 | | /* V3MULU */ |
22604 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
22605 | | /* VMM0 */ |
22606 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
22607 | | /* VMULU */ |
22608 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
22609 | | /* VSHF_B */ |
22610 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22611 | | /* VSHF_D */ |
22612 | | MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, MSA128DOpnd, |
22613 | | /* VSHF_H */ |
22614 | | MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, MSA128HOpnd, |
22615 | | /* VSHF_W */ |
22616 | | MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, MSA128WOpnd, |
22617 | | /* WAIT */ |
22618 | | /* WAIT_MM */ |
22619 | | uimm10, |
22620 | | /* WAIT_MMR6 */ |
22621 | | uimm10, |
22622 | | /* WRDSP */ |
22623 | | GPR32Opnd, uimm10, |
22624 | | /* WRDSP_MM */ |
22625 | | GPR32Opnd, uimm7, |
22626 | | /* WRPGPR_MMR6 */ |
22627 | | GPR32Opnd, GPR32Opnd, |
22628 | | /* WSBH */ |
22629 | | GPR32Opnd, GPR32Opnd, |
22630 | | /* WSBH_MM */ |
22631 | | GPR32Opnd, GPR32Opnd, |
22632 | | /* WSBH_MMR6 */ |
22633 | | GPR32Opnd, GPR32Opnd, |
22634 | | /* XOR */ |
22635 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22636 | | /* XOR16_MM */ |
22637 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
22638 | | /* XOR16_MMR6 */ |
22639 | | GPRMM16Opnd, GPRMM16Opnd, GPRMM16Opnd, |
22640 | | /* XOR64 */ |
22641 | | GPR64Opnd, GPR64Opnd, GPR64Opnd, |
22642 | | /* XORI_B */ |
22643 | | MSA128BOpnd, MSA128BOpnd, vsplat_uimm8, |
22644 | | /* XORI_MMR6 */ |
22645 | | GPR32Opnd, GPR32Opnd, uimm16, |
22646 | | /* XOR_MM */ |
22647 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22648 | | /* XOR_MMR6 */ |
22649 | | GPR32Opnd, GPR32Opnd, GPR32Opnd, |
22650 | | /* XOR_V */ |
22651 | | MSA128BOpnd, MSA128BOpnd, MSA128BOpnd, |
22652 | | /* XORi */ |
22653 | | GPR32Opnd, GPR32Opnd, uimm16, |
22654 | | /* XORi64 */ |
22655 | | GPR64Opnd, GPR64Opnd, uimm16_64, |
22656 | | /* XORi_MM */ |
22657 | | GPR32Opnd, GPR32Opnd, uimm16, |
22658 | | /* XorRxRxRy16 */ |
22659 | | CPU16Regs, CPU16Regs, CPU16Regs, |
22660 | | /* YIELD */ |
22661 | | GPR32Opnd, GPR32Opnd, |
22662 | | }; |
22663 | | return OpcodeOperandTypes[Offsets[Opcode] + OpIdx]; |
22664 | | } |
22665 | | } // end namespace Mips |
22666 | | } // end namespace llvm |
22667 | | #endif // GET_INSTRINFO_OPERAND_TYPE |
22668 | | |
22669 | | #ifdef GET_INSTRINFO_MEM_OPERAND_SIZE |
22670 | | #undef GET_INSTRINFO_MEM_OPERAND_SIZE |
22671 | | namespace llvm { |
22672 | | namespace Mips { |
22673 | | LLVM_READONLY |
22674 | | static int getMemOperandSize(int OpType) { |
22675 | | switch (OpType) { |
22676 | | default: return 0; |
22677 | | } |
22678 | | } |
22679 | | } // end namespace Mips |
22680 | | } // end namespace llvm |
22681 | | #endif // GET_INSTRINFO_MEM_OPERAND_SIZE |
22682 | | |
22683 | | #ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
22684 | | #undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
22685 | | namespace llvm { |
22686 | | namespace Mips { |
22687 | | LLVM_READONLY static unsigned |
22688 | | getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) { |
22689 | | return LogicalOpIdx; |
22690 | | } |
22691 | | LLVM_READONLY static inline unsigned |
22692 | | getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) { |
22693 | | auto S = 0U; |
22694 | | for (auto i = 0U; i < LogicalOpIdx; ++i) |
22695 | | S += getLogicalOperandSize(Opcode, i); |
22696 | | return S; |
22697 | | } |
22698 | | } // end namespace Mips |
22699 | | } // end namespace llvm |
22700 | | #endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP |
22701 | | |
22702 | | #ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
22703 | | #undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
22704 | | namespace llvm { |
22705 | | namespace Mips { |
22706 | | LLVM_READONLY static int |
22707 | | getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) { |
22708 | | return -1; |
22709 | | } |
22710 | | } // end namespace Mips |
22711 | | } // end namespace llvm |
22712 | | #endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP |
22713 | | |
22714 | | #ifdef GET_INSTRINFO_MC_HELPER_DECLS |
22715 | | #undef GET_INSTRINFO_MC_HELPER_DECLS |
22716 | | |
22717 | | namespace llvm { |
22718 | | class MCInst; |
22719 | | class FeatureBitset; |
22720 | | |
22721 | | namespace Mips_MC { |
22722 | | |
22723 | | void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features); |
22724 | | |
22725 | | } // end namespace Mips_MC |
22726 | | } // end namespace llvm |
22727 | | |
22728 | | #endif // GET_INSTRINFO_MC_HELPER_DECLS |
22729 | | |
22730 | | #ifdef GET_INSTRINFO_MC_HELPERS |
22731 | | #undef GET_INSTRINFO_MC_HELPERS |
22732 | | |
22733 | | namespace llvm { |
22734 | | namespace Mips_MC { |
22735 | | |
22736 | | } // end namespace Mips_MC |
22737 | | } // end namespace llvm |
22738 | | |
22739 | | #endif // GET_GENISTRINFO_MC_HELPERS |
22740 | | |
22741 | | #if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\ |
22742 | | defined(GET_AVAILABLE_OPCODE_CHECKER) |
22743 | | #define GET_COMPUTE_FEATURES |
22744 | | #endif |
22745 | | #ifdef GET_COMPUTE_FEATURES |
22746 | | #undef GET_COMPUTE_FEATURES |
22747 | | namespace llvm { |
22748 | | namespace Mips_MC { |
22749 | | |
22750 | | // Bits for subtarget features that participate in instruction matching. |
22751 | | enum SubtargetFeatureBits : uint8_t { |
22752 | | Feature_HasMips2Bit = 11, |
22753 | | Feature_HasMips3_32Bit = 14, |
22754 | | Feature_HasMips3_32r2Bit = 15, |
22755 | | Feature_HasMips3Bit = 12, |
22756 | | Feature_NotMips3Bit = 47, |
22757 | | Feature_HasMips4_32Bit = 16, |
22758 | | Feature_NotMips4_32Bit = 48, |
22759 | | Feature_HasMips4_32r2Bit = 17, |
22760 | | Feature_HasMips5_32r2Bit = 18, |
22761 | | Feature_HasMips32Bit = 19, |
22762 | | Feature_HasMips32r2Bit = 20, |
22763 | | Feature_HasMips32r5Bit = 21, |
22764 | | Feature_HasMips32r6Bit = 22, |
22765 | | Feature_NotMips32r6Bit = 49, |
22766 | | Feature_IsGP64bitBit = 33, |
22767 | | Feature_IsGP32bitBit = 32, |
22768 | | Feature_IsPTR64bitBit = 37, |
22769 | | Feature_IsPTR32bitBit = 36, |
22770 | | Feature_HasMips64Bit = 23, |
22771 | | Feature_NotMips64Bit = 50, |
22772 | | Feature_HasMips64r2Bit = 24, |
22773 | | Feature_HasMips64r5Bit = 25, |
22774 | | Feature_HasMips64r6Bit = 26, |
22775 | | Feature_NotMips64r6Bit = 51, |
22776 | | Feature_InMips16ModeBit = 30, |
22777 | | Feature_NotInMips16ModeBit = 46, |
22778 | | Feature_HasCnMipsBit = 1, |
22779 | | Feature_NotCnMipsBit = 42, |
22780 | | Feature_HasCnMipsPBit = 2, |
22781 | | Feature_NotCnMipsPBit = 43, |
22782 | | Feature_IsSym32Bit = 39, |
22783 | | Feature_IsSym64Bit = 40, |
22784 | | Feature_HasStdEncBit = 27, |
22785 | | Feature_InMicroMipsBit = 29, |
22786 | | Feature_NotInMicroMipsBit = 45, |
22787 | | Feature_HasEVABit = 6, |
22788 | | Feature_HasMSABit = 8, |
22789 | | Feature_HasMadd4Bit = 10, |
22790 | | Feature_HasMTBit = 9, |
22791 | | Feature_UseIndirectJumpsHazardBit = 52, |
22792 | | Feature_NoIndirectJumpGuardsBit = 41, |
22793 | | Feature_HasCRCBit = 0, |
22794 | | Feature_HasVirtBit = 28, |
22795 | | Feature_HasGINVBit = 7, |
22796 | | Feature_IsFP64bitBit = 31, |
22797 | | Feature_NotFP64bitBit = 44, |
22798 | | Feature_IsSingleFloatBit = 38, |
22799 | | Feature_IsNotSingleFloatBit = 34, |
22800 | | Feature_IsNotSoftFloatBit = 35, |
22801 | | Feature_HasMips3DBit = 13, |
22802 | | Feature_HasDSPBit = 3, |
22803 | | Feature_HasDSPR2Bit = 4, |
22804 | | Feature_HasDSPR3Bit = 5, |
22805 | | }; |
22806 | | |
22807 | 0 | inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) { |
22808 | 0 | FeatureBitset Features; |
22809 | 0 | if (FB[Mips::FeatureMips2]) |
22810 | 0 | Features.set(Feature_HasMips2Bit); |
22811 | 0 | if (FB[Mips::FeatureMips3_32]) |
22812 | 0 | Features.set(Feature_HasMips3_32Bit); |
22813 | 0 | if (FB[Mips::FeatureMips3_32r2]) |
22814 | 0 | Features.set(Feature_HasMips3_32r2Bit); |
22815 | 0 | if (FB[Mips::FeatureMips3]) |
22816 | 0 | Features.set(Feature_HasMips3Bit); |
22817 | 0 | if (!FB[Mips::FeatureMips3]) |
22818 | 0 | Features.set(Feature_NotMips3Bit); |
22819 | 0 | if (FB[Mips::FeatureMips4_32]) |
22820 | 0 | Features.set(Feature_HasMips4_32Bit); |
22821 | 0 | if (!FB[Mips::FeatureMips4_32]) |
22822 | 0 | Features.set(Feature_NotMips4_32Bit); |
22823 | 0 | if (FB[Mips::FeatureMips4_32r2]) |
22824 | 0 | Features.set(Feature_HasMips4_32r2Bit); |
22825 | 0 | if (FB[Mips::FeatureMips5_32r2]) |
22826 | 0 | Features.set(Feature_HasMips5_32r2Bit); |
22827 | 0 | if (FB[Mips::FeatureMips32]) |
22828 | 0 | Features.set(Feature_HasMips32Bit); |
22829 | 0 | if (FB[Mips::FeatureMips32r2]) |
22830 | 0 | Features.set(Feature_HasMips32r2Bit); |
22831 | 0 | if (FB[Mips::FeatureMips32r5]) |
22832 | 0 | Features.set(Feature_HasMips32r5Bit); |
22833 | 0 | if (FB[Mips::FeatureMips32r6]) |
22834 | 0 | Features.set(Feature_HasMips32r6Bit); |
22835 | 0 | if (!FB[Mips::FeatureMips32r6]) |
22836 | 0 | Features.set(Feature_NotMips32r6Bit); |
22837 | 0 | if (FB[Mips::FeatureGP64Bit]) |
22838 | 0 | Features.set(Feature_IsGP64bitBit); |
22839 | 0 | if (!FB[Mips::FeatureGP64Bit]) |
22840 | 0 | Features.set(Feature_IsGP32bitBit); |
22841 | 0 | if (FB[Mips::FeaturePTR64Bit]) |
22842 | 0 | Features.set(Feature_IsPTR64bitBit); |
22843 | 0 | if (!FB[Mips::FeaturePTR64Bit]) |
22844 | 0 | Features.set(Feature_IsPTR32bitBit); |
22845 | 0 | if (FB[Mips::FeatureMips64]) |
22846 | 0 | Features.set(Feature_HasMips64Bit); |
22847 | 0 | if (!FB[Mips::FeatureMips64]) |
22848 | 0 | Features.set(Feature_NotMips64Bit); |
22849 | 0 | if (FB[Mips::FeatureMips64r2]) |
22850 | 0 | Features.set(Feature_HasMips64r2Bit); |
22851 | 0 | if (FB[Mips::FeatureMips64r5]) |
22852 | 0 | Features.set(Feature_HasMips64r5Bit); |
22853 | 0 | if (FB[Mips::FeatureMips64r6]) |
22854 | 0 | Features.set(Feature_HasMips64r6Bit); |
22855 | 0 | if (!FB[Mips::FeatureMips64r6]) |
22856 | 0 | Features.set(Feature_NotMips64r6Bit); |
22857 | 0 | if (FB[Mips::FeatureMips16]) |
22858 | 0 | Features.set(Feature_InMips16ModeBit); |
22859 | 0 | if (!FB[Mips::FeatureMips16]) |
22860 | 0 | Features.set(Feature_NotInMips16ModeBit); |
22861 | 0 | if (FB[Mips::FeatureCnMips]) |
22862 | 0 | Features.set(Feature_HasCnMipsBit); |
22863 | 0 | if (!FB[Mips::FeatureCnMips]) |
22864 | 0 | Features.set(Feature_NotCnMipsBit); |
22865 | 0 | if (FB[Mips::FeatureCnMipsP]) |
22866 | 0 | Features.set(Feature_HasCnMipsPBit); |
22867 | 0 | if (!FB[Mips::FeatureCnMipsP]) |
22868 | 0 | Features.set(Feature_NotCnMipsPBit); |
22869 | 0 | if (FB[Mips::FeatureSym32]) |
22870 | 0 | Features.set(Feature_IsSym32Bit); |
22871 | 0 | if (!FB[Mips::FeatureSym32]) |
22872 | 0 | Features.set(Feature_IsSym64Bit); |
22873 | 0 | if (!FB[Mips::FeatureMips16]) |
22874 | 0 | Features.set(Feature_HasStdEncBit); |
22875 | 0 | if (FB[Mips::FeatureMicroMips]) |
22876 | 0 | Features.set(Feature_InMicroMipsBit); |
22877 | 0 | if (!FB[Mips::FeatureMicroMips]) |
22878 | 0 | Features.set(Feature_NotInMicroMipsBit); |
22879 | 0 | if (FB[Mips::FeatureEVA]) |
22880 | 0 | Features.set(Feature_HasEVABit); |
22881 | 0 | if (FB[Mips::FeatureMSA]) |
22882 | 0 | Features.set(Feature_HasMSABit); |
22883 | 0 | if (!FB[Mips::FeatureNoMadd4]) |
22884 | 0 | Features.set(Feature_HasMadd4Bit); |
22885 | 0 | if (FB[Mips::FeatureMT]) |
22886 | 0 | Features.set(Feature_HasMTBit); |
22887 | 0 | if (FB[Mips::FeatureUseIndirectJumpsHazard]) |
22888 | 0 | Features.set(Feature_UseIndirectJumpsHazardBit); |
22889 | 0 | if (!FB[Mips::FeatureUseIndirectJumpsHazard]) |
22890 | 0 | Features.set(Feature_NoIndirectJumpGuardsBit); |
22891 | 0 | if (FB[Mips::FeatureCRC]) |
22892 | 0 | Features.set(Feature_HasCRCBit); |
22893 | 0 | if (FB[Mips::FeatureVirt]) |
22894 | 0 | Features.set(Feature_HasVirtBit); |
22895 | 0 | if (FB[Mips::FeatureGINV]) |
22896 | 0 | Features.set(Feature_HasGINVBit); |
22897 | 0 | if (FB[Mips::FeatureFP64Bit]) |
22898 | 0 | Features.set(Feature_IsFP64bitBit); |
22899 | 0 | if (!FB[Mips::FeatureFP64Bit]) |
22900 | 0 | Features.set(Feature_NotFP64bitBit); |
22901 | 0 | if (FB[Mips::FeatureSingleFloat]) |
22902 | 0 | Features.set(Feature_IsSingleFloatBit); |
22903 | 0 | if (!FB[Mips::FeatureSingleFloat]) |
22904 | 0 | Features.set(Feature_IsNotSingleFloatBit); |
22905 | 0 | if (!FB[Mips::FeatureSoftFloat]) |
22906 | 0 | Features.set(Feature_IsNotSoftFloatBit); |
22907 | 0 | if (FB[Mips::FeatureMips3D]) |
22908 | 0 | Features.set(Feature_HasMips3DBit); |
22909 | 0 | if (FB[Mips::FeatureDSP]) |
22910 | 0 | Features.set(Feature_HasDSPBit); |
22911 | 0 | if (FB[Mips::FeatureDSPR2]) |
22912 | 0 | Features.set(Feature_HasDSPR2Bit); |
22913 | 0 | if (FB[Mips::FeatureDSPR3]) |
22914 | 0 | Features.set(Feature_HasDSPR3Bit); |
22915 | 0 | return Features; |
22916 | 0 | } |
22917 | | |
22918 | 0 | inline FeatureBitset computeRequiredFeatures(unsigned Opcode) { |
22919 | 0 | enum : uint8_t { |
22920 | 0 | CEFBS_None, |
22921 | 0 | CEFBS_HasCnMips, |
22922 | 0 | CEFBS_HasCnMipsP, |
22923 | 0 | CEFBS_HasDSP, |
22924 | 0 | CEFBS_HasDSPR2, |
22925 | 0 | CEFBS_HasMSA, |
22926 | 0 | CEFBS_HasMT, |
22927 | 0 | CEFBS_InMicroMips, |
22928 | 0 | CEFBS_InMips16Mode, |
22929 | 0 | CEFBS_IsGP32bit, |
22930 | 0 | CEFBS_IsGP64bit, |
22931 | 0 | CEFBS_IsNotSoftFloat, |
22932 | 0 | CEFBS_NotCnMips, |
22933 | 0 | CEFBS_NotInMips16Mode, |
22934 | 0 | CEFBS_HasDSP_NotInMicroMips, |
22935 | 0 | CEFBS_HasStdEnc_HasMSA, |
22936 | 0 | CEFBS_HasStdEnc_HasMips32, |
22937 | 0 | CEFBS_HasStdEnc_HasMips32r6, |
22938 | 0 | CEFBS_HasStdEnc_HasMips64, |
22939 | 0 | CEFBS_HasStdEnc_HasMips64r6, |
22940 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat, |
22941 | 0 | CEFBS_HasStdEnc_NotInMicroMips, |
22942 | 0 | CEFBS_HasStdEnc_NotMips3, |
22943 | 0 | CEFBS_HasStdEnc_NotMips4_32, |
22944 | 0 | CEFBS_InMicroMips_HasDSP, |
22945 | 0 | CEFBS_InMicroMips_HasDSPR2, |
22946 | 0 | CEFBS_InMicroMips_HasDSPR3, |
22947 | 0 | CEFBS_InMicroMips_HasEVA, |
22948 | 0 | CEFBS_InMicroMips_HasMips32r6, |
22949 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, |
22950 | 0 | CEFBS_InMicroMips_NotMips32r6, |
22951 | 0 | CEFBS_IsFP64bit_IsNotSoftFloat, |
22952 | 0 | CEFBS_IsGP32bit_NotInMicroMips, |
22953 | 0 | CEFBS_NotFP64bit_IsNotSoftFloat, |
22954 | 0 | CEFBS_NotInMips16Mode_HasDSP, |
22955 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, |
22956 | 0 | CEFBS_NotInMips16Mode_IsNotSoftFloat, |
22957 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit, |
22958 | 0 | CEFBS_HasMips3_NotMips64r6_NotCnMips, |
22959 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, |
22960 | 0 | CEFBS_HasStdEnc_HasMSA_HasMips64, |
22961 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, |
22962 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, |
22963 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, |
22964 | 0 | CEFBS_HasStdEnc_HasMips32_NotInMicroMips, |
22965 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, |
22966 | 0 | CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, |
22967 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, |
22968 | 0 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, |
22969 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, |
22970 | 0 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, |
22971 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, |
22972 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, |
22973 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, |
22974 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, |
22975 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, |
22976 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, |
22977 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, |
22978 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, |
22979 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, |
22980 | 0 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, |
22981 | 0 | CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, |
22982 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, |
22983 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, |
22984 | 0 | CEFBS_InMicroMips_HasMips32r6_HasGINV, |
22985 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, |
22986 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, |
22987 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, |
22988 | 0 | CEFBS_InMicroMips_NotMips32r6_HasDSP, |
22989 | 0 | CEFBS_InMicroMips_NotMips32r6_HasEVA, |
22990 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, |
22991 | 0 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, |
22992 | 0 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, |
22993 | 0 | CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, |
22994 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, |
22995 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, |
22996 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, |
22997 | 0 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, |
22998 | 0 | CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
22999 | 0 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, |
23000 | 0 | CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, |
23001 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, |
23002 | 0 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, |
23003 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, |
23004 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, |
23005 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, |
23006 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, |
23007 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, |
23008 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, |
23009 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, |
23010 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, |
23011 | 0 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
23012 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
23013 | 0 | CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, |
23014 | 0 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, |
23015 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, |
23016 | 0 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, |
23017 | 0 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, |
23018 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, |
23019 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, |
23020 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, |
23021 | 0 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, |
23022 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, |
23023 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, |
23024 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, |
23025 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
23026 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, |
23027 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, |
23028 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
23029 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
23030 | 0 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
23031 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
23032 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
23033 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
23034 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
23035 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
23036 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
23037 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, |
23038 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, |
23039 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
23040 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
23041 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, |
23042 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, |
23043 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, |
23044 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, |
23045 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23046 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, |
23047 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, |
23048 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23049 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, |
23050 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23051 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, |
23052 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23053 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, |
23054 | 0 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
23055 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, |
23056 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23057 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
23058 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
23059 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
23060 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
23061 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
23062 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
23063 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, |
23064 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23065 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23066 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23067 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23068 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23069 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23070 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23071 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
23072 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
23073 | 0 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, |
23074 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, |
23075 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, |
23076 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, |
23077 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, |
23078 | 0 | }; |
23079 | |
|
23080 | 0 | static constexpr FeatureBitset FeatureBitsets[] = { |
23081 | 0 | {}, // CEFBS_None |
23082 | 0 | {Feature_HasCnMipsBit, }, |
23083 | 0 | {Feature_HasCnMipsPBit, }, |
23084 | 0 | {Feature_HasDSPBit, }, |
23085 | 0 | {Feature_HasDSPR2Bit, }, |
23086 | 0 | {Feature_HasMSABit, }, |
23087 | 0 | {Feature_HasMTBit, }, |
23088 | 0 | {Feature_InMicroMipsBit, }, |
23089 | 0 | {Feature_InMips16ModeBit, }, |
23090 | 0 | {Feature_IsGP32bitBit, }, |
23091 | 0 | {Feature_IsGP64bitBit, }, |
23092 | 0 | {Feature_IsNotSoftFloatBit, }, |
23093 | 0 | {Feature_NotCnMipsBit, }, |
23094 | 0 | {Feature_NotInMips16ModeBit, }, |
23095 | 0 | {Feature_HasDSPBit, Feature_NotInMicroMipsBit, }, |
23096 | 0 | {Feature_HasStdEncBit, Feature_HasMSABit, }, |
23097 | 0 | {Feature_HasStdEncBit, Feature_HasMips32Bit, }, |
23098 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, }, |
23099 | 0 | {Feature_HasStdEncBit, Feature_HasMips64Bit, }, |
23100 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, }, |
23101 | 0 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, }, |
23102 | 0 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, }, |
23103 | 0 | {Feature_HasStdEncBit, Feature_NotMips3Bit, }, |
23104 | 0 | {Feature_HasStdEncBit, Feature_NotMips4_32Bit, }, |
23105 | 0 | {Feature_InMicroMipsBit, Feature_HasDSPBit, }, |
23106 | 0 | {Feature_InMicroMipsBit, Feature_HasDSPR2Bit, }, |
23107 | 0 | {Feature_InMicroMipsBit, Feature_HasDSPR3Bit, }, |
23108 | 0 | {Feature_InMicroMipsBit, Feature_HasEVABit, }, |
23109 | 0 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, }, |
23110 | 0 | {Feature_InMicroMipsBit, Feature_IsNotSoftFloatBit, }, |
23111 | 0 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, }, |
23112 | 0 | {Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23113 | 0 | {Feature_IsGP32bitBit, Feature_NotInMicroMipsBit, }, |
23114 | 0 | {Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23115 | 0 | {Feature_NotInMips16ModeBit, Feature_HasDSPBit, }, |
23116 | 0 | {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, }, |
23117 | 0 | {Feature_NotInMips16ModeBit, Feature_IsNotSoftFloatBit, }, |
23118 | 0 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, }, |
23119 | 0 | {Feature_HasMips3Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, }, |
23120 | 0 | {Feature_HasMips64Bit, Feature_HasCnMipsBit, Feature_NotInMicroMipsBit, }, |
23121 | 0 | {Feature_HasStdEncBit, Feature_HasMSABit, Feature_HasMips64Bit, }, |
23122 | 0 | {Feature_HasStdEncBit, Feature_HasMTBit, Feature_NotInMicroMipsBit, }, |
23123 | 0 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotInMicroMipsBit, }, |
23124 | 0 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotInMicroMipsBit, }, |
23125 | 0 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotInMicroMipsBit, }, |
23126 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotInMicroMipsBit, }, |
23127 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_NotInMicroMipsBit, }, |
23128 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
23129 | 0 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotInMicroMipsBit, }, |
23130 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r2Bit, Feature_NotInMicroMipsBit, }, |
23131 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r5Bit, Feature_HasVirtBit, }, |
23132 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23133 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips4_32Bit, }, |
23134 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips3Bit, }, |
23135 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r2Bit, }, |
23136 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips32r6Bit, }, |
23137 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64r6Bit, }, |
23138 | 0 | {Feature_HasStdEncBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23139 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23140 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips4_32Bit, }, |
23141 | 0 | {Feature_HasStdEncBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
23142 | 0 | {Feature_HasStdEncBit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, }, |
23143 | 0 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
23144 | 0 | {Feature_InMicroMipsBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, }, |
23145 | 0 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, }, |
23146 | 0 | {Feature_InMicroMipsBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
23147 | 0 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23148 | 0 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23149 | 0 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasDSPBit, }, |
23150 | 0 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_HasEVABit, }, |
23151 | 0 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
23152 | 0 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
23153 | 0 | {Feature_NotInMips16ModeBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23154 | 0 | {Feature_NotInMips16ModeBit, Feature_IsGP64bitBit, Feature_NotInMicroMipsBit, }, |
23155 | 0 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NoIndirectJumpGuardsBit, }, |
23156 | 0 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_NotInMicroMipsBit, }, |
23157 | 0 | {Feature_NotInMips16ModeBit, Feature_IsPTR64bitBit, Feature_UseIndirectJumpsHazardBit, }, |
23158 | 0 | {Feature_NotInMips16ModeBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, }, |
23159 | 0 | {Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
23160 | 0 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23161 | 0 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
23162 | 0 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
23163 | 0 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23164 | 0 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
23165 | 0 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
23166 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
23167 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, }, |
23168 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r5Bit, Feature_HasVirtBit, Feature_NotInMicroMipsBit, }, |
23169 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
23170 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_HasGINVBit, Feature_NotInMicroMipsBit, }, |
23171 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23172 | 0 | {Feature_HasStdEncBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23173 | 0 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23174 | 0 | {Feature_HasStdEncBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23175 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_HasCRCBit, Feature_NotInMicroMipsBit, }, |
23176 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23177 | 0 | {Feature_HasStdEncBit, Feature_IsGP32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
23178 | 0 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips32r6Bit, Feature_NotInMicroMipsBit, }, |
23179 | 0 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23180 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23181 | 0 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23182 | 0 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_HasMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
23183 | 0 | {Feature_InMicroMipsBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
23184 | 0 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, }, |
23185 | 0 | {Feature_InMicroMipsBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
23186 | 0 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23187 | 0 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23188 | 0 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23189 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
23190 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
23191 | 0 | {Feature_HasStdEncBit, Feature_HasMips3_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23192 | 0 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23193 | 0 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
23194 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
23195 | 0 | {Feature_HasStdEncBit, Feature_HasMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
23196 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23197 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23198 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23199 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips3_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23200 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23201 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
23202 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips64Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23203 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23204 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23205 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23206 | 0 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23207 | 0 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotCnMipsBit, Feature_NotInMicroMipsBit, }, |
23208 | 0 | {Feature_InMicroMipsBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, }, |
23209 | 0 | {Feature_HasStdEncBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23210 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_HasEVABit, Feature_NotInMicroMipsBit, }, |
23211 | 0 | {Feature_HasStdEncBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23212 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, }, |
23213 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23214 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23215 | 0 | {Feature_HasStdEncBit, Feature_IsPTR32bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23216 | 0 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMicroMipsBit, }, |
23217 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23218 | 0 | {Feature_HasStdEncBit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
23219 | 0 | {Feature_HasStdEncBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
23220 | 0 | {Feature_HasStdEncBit, Feature_HasMips32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
23221 | 0 | {Feature_HasStdEncBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
23222 | 0 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
23223 | 0 | {Feature_HasStdEncBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
23224 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMips3DBit, }, |
23225 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23226 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23227 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23228 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23229 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23230 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23231 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips5_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23232 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
23233 | 0 | {Feature_HasStdEncBit, Feature_IsFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
23234 | 0 | {Feature_HasStdEncBit, Feature_IsGP64bitBit, Feature_IsFP64bitBit, Feature_HasMips4_32Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, }, |
23235 | 0 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips3Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_NoIndirectJumpGuardsBit, }, |
23236 | 0 | {Feature_HasStdEncBit, Feature_IsPTR64bitBit, Feature_HasMips32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_NotInMips16ModeBit, Feature_NotInMicroMipsBit, Feature_UseIndirectJumpsHazardBit, }, |
23237 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_HasMadd4Bit, Feature_NotInMicroMipsBit, }, |
23238 | 0 | {Feature_HasStdEncBit, Feature_NotFP64bitBit, Feature_HasMips4_32r2Bit, Feature_NotMips32r6Bit, Feature_NotMips64r6Bit, Feature_IsNotSoftFloatBit, Feature_NotInMicroMipsBit, Feature_HasMadd4Bit, }, |
23239 | 0 | }; |
23240 | 0 | static constexpr uint8_t RequiredFeaturesRefs[] = { |
23241 | 0 | CEFBS_None, // PHI = 0 |
23242 | 0 | CEFBS_None, // INLINEASM = 1 |
23243 | 0 | CEFBS_None, // INLINEASM_BR = 2 |
23244 | 0 | CEFBS_None, // CFI_INSTRUCTION = 3 |
23245 | 0 | CEFBS_None, // EH_LABEL = 4 |
23246 | 0 | CEFBS_None, // GC_LABEL = 5 |
23247 | 0 | CEFBS_None, // ANNOTATION_LABEL = 6 |
23248 | 0 | CEFBS_None, // KILL = 7 |
23249 | 0 | CEFBS_None, // EXTRACT_SUBREG = 8 |
23250 | 0 | CEFBS_None, // INSERT_SUBREG = 9 |
23251 | 0 | CEFBS_None, // IMPLICIT_DEF = 10 |
23252 | 0 | CEFBS_None, // SUBREG_TO_REG = 11 |
23253 | 0 | CEFBS_None, // COPY_TO_REGCLASS = 12 |
23254 | 0 | CEFBS_None, // DBG_VALUE = 13 |
23255 | 0 | CEFBS_None, // DBG_VALUE_LIST = 14 |
23256 | 0 | CEFBS_None, // DBG_INSTR_REF = 15 |
23257 | 0 | CEFBS_None, // DBG_PHI = 16 |
23258 | 0 | CEFBS_None, // DBG_LABEL = 17 |
23259 | 0 | CEFBS_None, // REG_SEQUENCE = 18 |
23260 | 0 | CEFBS_None, // COPY = 19 |
23261 | 0 | CEFBS_None, // BUNDLE = 20 |
23262 | 0 | CEFBS_None, // LIFETIME_START = 21 |
23263 | 0 | CEFBS_None, // LIFETIME_END = 22 |
23264 | 0 | CEFBS_None, // PSEUDO_PROBE = 23 |
23265 | 0 | CEFBS_None, // ARITH_FENCE = 24 |
23266 | 0 | CEFBS_None, // STACKMAP = 25 |
23267 | 0 | CEFBS_None, // FENTRY_CALL = 26 |
23268 | 0 | CEFBS_None, // PATCHPOINT = 27 |
23269 | 0 | CEFBS_None, // LOAD_STACK_GUARD = 28 |
23270 | 0 | CEFBS_None, // PREALLOCATED_SETUP = 29 |
23271 | 0 | CEFBS_None, // PREALLOCATED_ARG = 30 |
23272 | 0 | CEFBS_None, // STATEPOINT = 31 |
23273 | 0 | CEFBS_None, // LOCAL_ESCAPE = 32 |
23274 | 0 | CEFBS_None, // FAULTING_OP = 33 |
23275 | 0 | CEFBS_None, // PATCHABLE_OP = 34 |
23276 | 0 | CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35 |
23277 | 0 | CEFBS_None, // PATCHABLE_RET = 36 |
23278 | 0 | CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37 |
23279 | 0 | CEFBS_None, // PATCHABLE_TAIL_CALL = 38 |
23280 | 0 | CEFBS_None, // PATCHABLE_EVENT_CALL = 39 |
23281 | 0 | CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40 |
23282 | 0 | CEFBS_None, // ICALL_BRANCH_FUNNEL = 41 |
23283 | 0 | CEFBS_None, // MEMBARRIER = 42 |
23284 | 0 | CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43 |
23285 | 0 | CEFBS_None, // G_ASSERT_SEXT = 44 |
23286 | 0 | CEFBS_None, // G_ASSERT_ZEXT = 45 |
23287 | 0 | CEFBS_None, // G_ASSERT_ALIGN = 46 |
23288 | 0 | CEFBS_None, // G_ADD = 47 |
23289 | 0 | CEFBS_None, // G_SUB = 48 |
23290 | 0 | CEFBS_None, // G_MUL = 49 |
23291 | 0 | CEFBS_None, // G_SDIV = 50 |
23292 | 0 | CEFBS_None, // G_UDIV = 51 |
23293 | 0 | CEFBS_None, // G_SREM = 52 |
23294 | 0 | CEFBS_None, // G_UREM = 53 |
23295 | 0 | CEFBS_None, // G_SDIVREM = 54 |
23296 | 0 | CEFBS_None, // G_UDIVREM = 55 |
23297 | 0 | CEFBS_None, // G_AND = 56 |
23298 | 0 | CEFBS_None, // G_OR = 57 |
23299 | 0 | CEFBS_None, // G_XOR = 58 |
23300 | 0 | CEFBS_None, // G_IMPLICIT_DEF = 59 |
23301 | 0 | CEFBS_None, // G_PHI = 60 |
23302 | 0 | CEFBS_None, // G_FRAME_INDEX = 61 |
23303 | 0 | CEFBS_None, // G_GLOBAL_VALUE = 62 |
23304 | 0 | CEFBS_None, // G_CONSTANT_POOL = 63 |
23305 | 0 | CEFBS_None, // G_EXTRACT = 64 |
23306 | 0 | CEFBS_None, // G_UNMERGE_VALUES = 65 |
23307 | 0 | CEFBS_None, // G_INSERT = 66 |
23308 | 0 | CEFBS_None, // G_MERGE_VALUES = 67 |
23309 | 0 | CEFBS_None, // G_BUILD_VECTOR = 68 |
23310 | 0 | CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69 |
23311 | 0 | CEFBS_None, // G_CONCAT_VECTORS = 70 |
23312 | 0 | CEFBS_None, // G_PTRTOINT = 71 |
23313 | 0 | CEFBS_None, // G_INTTOPTR = 72 |
23314 | 0 | CEFBS_None, // G_BITCAST = 73 |
23315 | 0 | CEFBS_None, // G_FREEZE = 74 |
23316 | 0 | CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75 |
23317 | 0 | CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76 |
23318 | 0 | CEFBS_None, // G_INTRINSIC_TRUNC = 77 |
23319 | 0 | CEFBS_None, // G_INTRINSIC_ROUND = 78 |
23320 | 0 | CEFBS_None, // G_INTRINSIC_LRINT = 79 |
23321 | 0 | CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80 |
23322 | 0 | CEFBS_None, // G_READCYCLECOUNTER = 81 |
23323 | 0 | CEFBS_None, // G_LOAD = 82 |
23324 | 0 | CEFBS_None, // G_SEXTLOAD = 83 |
23325 | 0 | CEFBS_None, // G_ZEXTLOAD = 84 |
23326 | 0 | CEFBS_None, // G_INDEXED_LOAD = 85 |
23327 | 0 | CEFBS_None, // G_INDEXED_SEXTLOAD = 86 |
23328 | 0 | CEFBS_None, // G_INDEXED_ZEXTLOAD = 87 |
23329 | 0 | CEFBS_None, // G_STORE = 88 |
23330 | 0 | CEFBS_None, // G_INDEXED_STORE = 89 |
23331 | 0 | CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90 |
23332 | 0 | CEFBS_None, // G_ATOMIC_CMPXCHG = 91 |
23333 | 0 | CEFBS_None, // G_ATOMICRMW_XCHG = 92 |
23334 | 0 | CEFBS_None, // G_ATOMICRMW_ADD = 93 |
23335 | 0 | CEFBS_None, // G_ATOMICRMW_SUB = 94 |
23336 | 0 | CEFBS_None, // G_ATOMICRMW_AND = 95 |
23337 | 0 | CEFBS_None, // G_ATOMICRMW_NAND = 96 |
23338 | 0 | CEFBS_None, // G_ATOMICRMW_OR = 97 |
23339 | 0 | CEFBS_None, // G_ATOMICRMW_XOR = 98 |
23340 | 0 | CEFBS_None, // G_ATOMICRMW_MAX = 99 |
23341 | 0 | CEFBS_None, // G_ATOMICRMW_MIN = 100 |
23342 | 0 | CEFBS_None, // G_ATOMICRMW_UMAX = 101 |
23343 | 0 | CEFBS_None, // G_ATOMICRMW_UMIN = 102 |
23344 | 0 | CEFBS_None, // G_ATOMICRMW_FADD = 103 |
23345 | 0 | CEFBS_None, // G_ATOMICRMW_FSUB = 104 |
23346 | 0 | CEFBS_None, // G_ATOMICRMW_FMAX = 105 |
23347 | 0 | CEFBS_None, // G_ATOMICRMW_FMIN = 106 |
23348 | 0 | CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107 |
23349 | 0 | CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108 |
23350 | 0 | CEFBS_None, // G_FENCE = 109 |
23351 | 0 | CEFBS_None, // G_PREFETCH = 110 |
23352 | 0 | CEFBS_None, // G_BRCOND = 111 |
23353 | 0 | CEFBS_None, // G_BRINDIRECT = 112 |
23354 | 0 | CEFBS_None, // G_INVOKE_REGION_START = 113 |
23355 | 0 | CEFBS_None, // G_INTRINSIC = 114 |
23356 | 0 | CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115 |
23357 | 0 | CEFBS_None, // G_INTRINSIC_CONVERGENT = 116 |
23358 | 0 | CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117 |
23359 | 0 | CEFBS_None, // G_ANYEXT = 118 |
23360 | 0 | CEFBS_None, // G_TRUNC = 119 |
23361 | 0 | CEFBS_None, // G_CONSTANT = 120 |
23362 | 0 | CEFBS_None, // G_FCONSTANT = 121 |
23363 | 0 | CEFBS_None, // G_VASTART = 122 |
23364 | 0 | CEFBS_None, // G_VAARG = 123 |
23365 | 0 | CEFBS_None, // G_SEXT = 124 |
23366 | 0 | CEFBS_None, // G_SEXT_INREG = 125 |
23367 | 0 | CEFBS_None, // G_ZEXT = 126 |
23368 | 0 | CEFBS_None, // G_SHL = 127 |
23369 | 0 | CEFBS_None, // G_LSHR = 128 |
23370 | 0 | CEFBS_None, // G_ASHR = 129 |
23371 | 0 | CEFBS_None, // G_FSHL = 130 |
23372 | 0 | CEFBS_None, // G_FSHR = 131 |
23373 | 0 | CEFBS_None, // G_ROTR = 132 |
23374 | 0 | CEFBS_None, // G_ROTL = 133 |
23375 | 0 | CEFBS_None, // G_ICMP = 134 |
23376 | 0 | CEFBS_None, // G_FCMP = 135 |
23377 | 0 | CEFBS_None, // G_SELECT = 136 |
23378 | 0 | CEFBS_None, // G_UADDO = 137 |
23379 | 0 | CEFBS_None, // G_UADDE = 138 |
23380 | 0 | CEFBS_None, // G_USUBO = 139 |
23381 | 0 | CEFBS_None, // G_USUBE = 140 |
23382 | 0 | CEFBS_None, // G_SADDO = 141 |
23383 | 0 | CEFBS_None, // G_SADDE = 142 |
23384 | 0 | CEFBS_None, // G_SSUBO = 143 |
23385 | 0 | CEFBS_None, // G_SSUBE = 144 |
23386 | 0 | CEFBS_None, // G_UMULO = 145 |
23387 | 0 | CEFBS_None, // G_SMULO = 146 |
23388 | 0 | CEFBS_None, // G_UMULH = 147 |
23389 | 0 | CEFBS_None, // G_SMULH = 148 |
23390 | 0 | CEFBS_None, // G_UADDSAT = 149 |
23391 | 0 | CEFBS_None, // G_SADDSAT = 150 |
23392 | 0 | CEFBS_None, // G_USUBSAT = 151 |
23393 | 0 | CEFBS_None, // G_SSUBSAT = 152 |
23394 | 0 | CEFBS_None, // G_USHLSAT = 153 |
23395 | 0 | CEFBS_None, // G_SSHLSAT = 154 |
23396 | 0 | CEFBS_None, // G_SMULFIX = 155 |
23397 | 0 | CEFBS_None, // G_UMULFIX = 156 |
23398 | 0 | CEFBS_None, // G_SMULFIXSAT = 157 |
23399 | 0 | CEFBS_None, // G_UMULFIXSAT = 158 |
23400 | 0 | CEFBS_None, // G_SDIVFIX = 159 |
23401 | 0 | CEFBS_None, // G_UDIVFIX = 160 |
23402 | 0 | CEFBS_None, // G_SDIVFIXSAT = 161 |
23403 | 0 | CEFBS_None, // G_UDIVFIXSAT = 162 |
23404 | 0 | CEFBS_None, // G_FADD = 163 |
23405 | 0 | CEFBS_None, // G_FSUB = 164 |
23406 | 0 | CEFBS_None, // G_FMUL = 165 |
23407 | 0 | CEFBS_None, // G_FMA = 166 |
23408 | 0 | CEFBS_None, // G_FMAD = 167 |
23409 | 0 | CEFBS_None, // G_FDIV = 168 |
23410 | 0 | CEFBS_None, // G_FREM = 169 |
23411 | 0 | CEFBS_None, // G_FPOW = 170 |
23412 | 0 | CEFBS_None, // G_FPOWI = 171 |
23413 | 0 | CEFBS_None, // G_FEXP = 172 |
23414 | 0 | CEFBS_None, // G_FEXP2 = 173 |
23415 | 0 | CEFBS_None, // G_FEXP10 = 174 |
23416 | 0 | CEFBS_None, // G_FLOG = 175 |
23417 | 0 | CEFBS_None, // G_FLOG2 = 176 |
23418 | 0 | CEFBS_None, // G_FLOG10 = 177 |
23419 | 0 | CEFBS_None, // G_FLDEXP = 178 |
23420 | 0 | CEFBS_None, // G_FFREXP = 179 |
23421 | 0 | CEFBS_None, // G_FNEG = 180 |
23422 | 0 | CEFBS_None, // G_FPEXT = 181 |
23423 | 0 | CEFBS_None, // G_FPTRUNC = 182 |
23424 | 0 | CEFBS_None, // G_FPTOSI = 183 |
23425 | 0 | CEFBS_None, // G_FPTOUI = 184 |
23426 | 0 | CEFBS_None, // G_SITOFP = 185 |
23427 | 0 | CEFBS_None, // G_UITOFP = 186 |
23428 | 0 | CEFBS_None, // G_FABS = 187 |
23429 | 0 | CEFBS_None, // G_FCOPYSIGN = 188 |
23430 | 0 | CEFBS_None, // G_IS_FPCLASS = 189 |
23431 | 0 | CEFBS_None, // G_FCANONICALIZE = 190 |
23432 | 0 | CEFBS_None, // G_FMINNUM = 191 |
23433 | 0 | CEFBS_None, // G_FMAXNUM = 192 |
23434 | 0 | CEFBS_None, // G_FMINNUM_IEEE = 193 |
23435 | 0 | CEFBS_None, // G_FMAXNUM_IEEE = 194 |
23436 | 0 | CEFBS_None, // G_FMINIMUM = 195 |
23437 | 0 | CEFBS_None, // G_FMAXIMUM = 196 |
23438 | 0 | CEFBS_None, // G_GET_FPENV = 197 |
23439 | 0 | CEFBS_None, // G_SET_FPENV = 198 |
23440 | 0 | CEFBS_None, // G_RESET_FPENV = 199 |
23441 | 0 | CEFBS_None, // G_GET_FPMODE = 200 |
23442 | 0 | CEFBS_None, // G_SET_FPMODE = 201 |
23443 | 0 | CEFBS_None, // G_RESET_FPMODE = 202 |
23444 | 0 | CEFBS_None, // G_PTR_ADD = 203 |
23445 | 0 | CEFBS_None, // G_PTRMASK = 204 |
23446 | 0 | CEFBS_None, // G_SMIN = 205 |
23447 | 0 | CEFBS_None, // G_SMAX = 206 |
23448 | 0 | CEFBS_None, // G_UMIN = 207 |
23449 | 0 | CEFBS_None, // G_UMAX = 208 |
23450 | 0 | CEFBS_None, // G_ABS = 209 |
23451 | 0 | CEFBS_None, // G_LROUND = 210 |
23452 | 0 | CEFBS_None, // G_LLROUND = 211 |
23453 | 0 | CEFBS_None, // G_BR = 212 |
23454 | 0 | CEFBS_None, // G_BRJT = 213 |
23455 | 0 | CEFBS_None, // G_INSERT_VECTOR_ELT = 214 |
23456 | 0 | CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215 |
23457 | 0 | CEFBS_None, // G_SHUFFLE_VECTOR = 216 |
23458 | 0 | CEFBS_None, // G_CTTZ = 217 |
23459 | 0 | CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218 |
23460 | 0 | CEFBS_None, // G_CTLZ = 219 |
23461 | 0 | CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220 |
23462 | 0 | CEFBS_None, // G_CTPOP = 221 |
23463 | 0 | CEFBS_None, // G_BSWAP = 222 |
23464 | 0 | CEFBS_None, // G_BITREVERSE = 223 |
23465 | 0 | CEFBS_None, // G_FCEIL = 224 |
23466 | 0 | CEFBS_None, // G_FCOS = 225 |
23467 | 0 | CEFBS_None, // G_FSIN = 226 |
23468 | 0 | CEFBS_None, // G_FSQRT = 227 |
23469 | 0 | CEFBS_None, // G_FFLOOR = 228 |
23470 | 0 | CEFBS_None, // G_FRINT = 229 |
23471 | 0 | CEFBS_None, // G_FNEARBYINT = 230 |
23472 | 0 | CEFBS_None, // G_ADDRSPACE_CAST = 231 |
23473 | 0 | CEFBS_None, // G_BLOCK_ADDR = 232 |
23474 | 0 | CEFBS_None, // G_JUMP_TABLE = 233 |
23475 | 0 | CEFBS_None, // G_DYN_STACKALLOC = 234 |
23476 | 0 | CEFBS_None, // G_STACKSAVE = 235 |
23477 | 0 | CEFBS_None, // G_STACKRESTORE = 236 |
23478 | 0 | CEFBS_None, // G_STRICT_FADD = 237 |
23479 | 0 | CEFBS_None, // G_STRICT_FSUB = 238 |
23480 | 0 | CEFBS_None, // G_STRICT_FMUL = 239 |
23481 | 0 | CEFBS_None, // G_STRICT_FDIV = 240 |
23482 | 0 | CEFBS_None, // G_STRICT_FREM = 241 |
23483 | 0 | CEFBS_None, // G_STRICT_FMA = 242 |
23484 | 0 | CEFBS_None, // G_STRICT_FSQRT = 243 |
23485 | 0 | CEFBS_None, // G_STRICT_FLDEXP = 244 |
23486 | 0 | CEFBS_None, // G_READ_REGISTER = 245 |
23487 | 0 | CEFBS_None, // G_WRITE_REGISTER = 246 |
23488 | 0 | CEFBS_None, // G_MEMCPY = 247 |
23489 | 0 | CEFBS_None, // G_MEMCPY_INLINE = 248 |
23490 | 0 | CEFBS_None, // G_MEMMOVE = 249 |
23491 | 0 | CEFBS_None, // G_MEMSET = 250 |
23492 | 0 | CEFBS_None, // G_BZERO = 251 |
23493 | 0 | CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252 |
23494 | 0 | CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253 |
23495 | 0 | CEFBS_None, // G_VECREDUCE_FADD = 254 |
23496 | 0 | CEFBS_None, // G_VECREDUCE_FMUL = 255 |
23497 | 0 | CEFBS_None, // G_VECREDUCE_FMAX = 256 |
23498 | 0 | CEFBS_None, // G_VECREDUCE_FMIN = 257 |
23499 | 0 | CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258 |
23500 | 0 | CEFBS_None, // G_VECREDUCE_FMINIMUM = 259 |
23501 | 0 | CEFBS_None, // G_VECREDUCE_ADD = 260 |
23502 | 0 | CEFBS_None, // G_VECREDUCE_MUL = 261 |
23503 | 0 | CEFBS_None, // G_VECREDUCE_AND = 262 |
23504 | 0 | CEFBS_None, // G_VECREDUCE_OR = 263 |
23505 | 0 | CEFBS_None, // G_VECREDUCE_XOR = 264 |
23506 | 0 | CEFBS_None, // G_VECREDUCE_SMAX = 265 |
23507 | 0 | CEFBS_None, // G_VECREDUCE_SMIN = 266 |
23508 | 0 | CEFBS_None, // G_VECREDUCE_UMAX = 267 |
23509 | 0 | CEFBS_None, // G_VECREDUCE_UMIN = 268 |
23510 | 0 | CEFBS_None, // G_SBFX = 269 |
23511 | 0 | CEFBS_None, // G_UBFX = 270 |
23512 | 0 | CEFBS_None, // ABSMacro = 271 |
23513 | 0 | CEFBS_None, // ADJCALLSTACKDOWN = 272 |
23514 | 0 | CEFBS_None, // ADJCALLSTACKUP = 273 |
23515 | 0 | CEFBS_HasStdEnc_HasMSA, // AND_V_D_PSEUDO = 274 |
23516 | 0 | CEFBS_HasStdEnc_HasMSA, // AND_V_H_PSEUDO = 275 |
23517 | 0 | CEFBS_HasStdEnc_HasMSA, // AND_V_W_PSEUDO = 276 |
23518 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16 = 277 |
23519 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I16_POSTRA = 278 |
23520 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32 = 279 |
23521 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I32_POSTRA = 280 |
23522 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64 = 281 |
23523 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I64_POSTRA = 282 |
23524 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8 = 283 |
23525 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_CMP_SWAP_I8_POSTRA = 284 |
23526 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16 = 285 |
23527 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I16_POSTRA = 286 |
23528 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32 = 287 |
23529 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I32_POSTRA = 288 |
23530 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64 = 289 |
23531 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I64_POSTRA = 290 |
23532 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8 = 291 |
23533 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_ADD_I8_POSTRA = 292 |
23534 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16 = 293 |
23535 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I16_POSTRA = 294 |
23536 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32 = 295 |
23537 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I32_POSTRA = 296 |
23538 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64 = 297 |
23539 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I64_POSTRA = 298 |
23540 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8 = 299 |
23541 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_AND_I8_POSTRA = 300 |
23542 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16 = 301 |
23543 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I16_POSTRA = 302 |
23544 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32 = 303 |
23545 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I32_POSTRA = 304 |
23546 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64 = 305 |
23547 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I64_POSTRA = 306 |
23548 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8 = 307 |
23549 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MAX_I8_POSTRA = 308 |
23550 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16 = 309 |
23551 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I16_POSTRA = 310 |
23552 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32 = 311 |
23553 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I32_POSTRA = 312 |
23554 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64 = 313 |
23555 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I64_POSTRA = 314 |
23556 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8 = 315 |
23557 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_MIN_I8_POSTRA = 316 |
23558 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16 = 317 |
23559 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I16_POSTRA = 318 |
23560 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32 = 319 |
23561 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I32_POSTRA = 320 |
23562 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64 = 321 |
23563 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I64_POSTRA = 322 |
23564 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8 = 323 |
23565 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_NAND_I8_POSTRA = 324 |
23566 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16 = 325 |
23567 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I16_POSTRA = 326 |
23568 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32 = 327 |
23569 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I32_POSTRA = 328 |
23570 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64 = 329 |
23571 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I64_POSTRA = 330 |
23572 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8 = 331 |
23573 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_OR_I8_POSTRA = 332 |
23574 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16 = 333 |
23575 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I16_POSTRA = 334 |
23576 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32 = 335 |
23577 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I32_POSTRA = 336 |
23578 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64 = 337 |
23579 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I64_POSTRA = 338 |
23580 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8 = 339 |
23581 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_SUB_I8_POSTRA = 340 |
23582 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16 = 341 |
23583 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I16_POSTRA = 342 |
23584 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32 = 343 |
23585 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I32_POSTRA = 344 |
23586 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64 = 345 |
23587 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I64_POSTRA = 346 |
23588 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8 = 347 |
23589 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMAX_I8_POSTRA = 348 |
23590 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16 = 349 |
23591 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I16_POSTRA = 350 |
23592 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32 = 351 |
23593 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I32_POSTRA = 352 |
23594 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64 = 353 |
23595 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I64_POSTRA = 354 |
23596 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8 = 355 |
23597 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_UMIN_I8_POSTRA = 356 |
23598 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16 = 357 |
23599 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I16_POSTRA = 358 |
23600 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32 = 359 |
23601 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I32_POSTRA = 360 |
23602 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64 = 361 |
23603 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I64_POSTRA = 362 |
23604 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8 = 363 |
23605 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_LOAD_XOR_I8_POSTRA = 364 |
23606 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16 = 365 |
23607 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I16_POSTRA = 366 |
23608 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32 = 367 |
23609 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I32_POSTRA = 368 |
23610 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64 = 369 |
23611 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I64_POSTRA = 370 |
23612 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8 = 371 |
23613 | 0 | CEFBS_NotInMips16Mode, // ATOMIC_SWAP_I8_POSTRA = 372 |
23614 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // B = 373 |
23615 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BAL_BR = 374 |
23616 | 0 | CEFBS_InMicroMips_NotMips32r6, // BAL_BR_MM = 375 |
23617 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BEQLImmMacro = 376 |
23618 | 0 | CEFBS_None, // BGE = 377 |
23619 | 0 | CEFBS_None, // BGEImmMacro = 378 |
23620 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEL = 379 |
23621 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGELImmMacro = 380 |
23622 | 0 | CEFBS_None, // BGEU = 381 |
23623 | 0 | CEFBS_None, // BGEUImmMacro = 382 |
23624 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEUL = 383 |
23625 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGEULImmMacro = 384 |
23626 | 0 | CEFBS_None, // BGT = 385 |
23627 | 0 | CEFBS_None, // BGTImmMacro = 386 |
23628 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTL = 387 |
23629 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTLImmMacro = 388 |
23630 | 0 | CEFBS_None, // BGTU = 389 |
23631 | 0 | CEFBS_None, // BGTUImmMacro = 390 |
23632 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTUL = 391 |
23633 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BGTULImmMacro = 392 |
23634 | 0 | CEFBS_None, // BLE = 393 |
23635 | 0 | CEFBS_None, // BLEImmMacro = 394 |
23636 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEL = 395 |
23637 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLELImmMacro = 396 |
23638 | 0 | CEFBS_None, // BLEU = 397 |
23639 | 0 | CEFBS_None, // BLEUImmMacro = 398 |
23640 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEUL = 399 |
23641 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLEULImmMacro = 400 |
23642 | 0 | CEFBS_None, // BLT = 401 |
23643 | 0 | CEFBS_None, // BLTImmMacro = 402 |
23644 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTL = 403 |
23645 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTLImmMacro = 404 |
23646 | 0 | CEFBS_None, // BLTU = 405 |
23647 | 0 | CEFBS_None, // BLTUImmMacro = 406 |
23648 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTUL = 407 |
23649 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BLTULImmMacro = 408 |
23650 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6, // BNELImmMacro = 409 |
23651 | 0 | CEFBS_None, // BPOSGE32_PSEUDO = 410 |
23652 | 0 | CEFBS_HasStdEnc_HasMSA, // BSEL_D_PSEUDO = 411 |
23653 | 0 | CEFBS_HasStdEnc_HasMSA, // BSEL_FD_PSEUDO = 412 |
23654 | 0 | CEFBS_HasStdEnc_HasMSA, // BSEL_FW_PSEUDO = 413 |
23655 | 0 | CEFBS_HasStdEnc_HasMSA, // BSEL_H_PSEUDO = 414 |
23656 | 0 | CEFBS_HasStdEnc_HasMSA, // BSEL_W_PSEUDO = 415 |
23657 | 0 | CEFBS_InMicroMips_NotMips32r6, // B_MM = 416 |
23658 | 0 | CEFBS_None, // B_MMR6_Pseudo = 417 |
23659 | 0 | CEFBS_InMicroMips, // B_MM_Pseudo = 418 |
23660 | 0 | CEFBS_None, // BeqImm = 419 |
23661 | 0 | CEFBS_None, // BneImm = 420 |
23662 | 0 | CEFBS_InMips16Mode, // BteqzT8CmpX16 = 421 |
23663 | 0 | CEFBS_InMips16Mode, // BteqzT8CmpiX16 = 422 |
23664 | 0 | CEFBS_InMips16Mode, // BteqzT8SltX16 = 423 |
23665 | 0 | CEFBS_InMips16Mode, // BteqzT8SltiX16 = 424 |
23666 | 0 | CEFBS_InMips16Mode, // BteqzT8SltiuX16 = 425 |
23667 | 0 | CEFBS_InMips16Mode, // BteqzT8SltuX16 = 426 |
23668 | 0 | CEFBS_InMips16Mode, // BtnezT8CmpX16 = 427 |
23669 | 0 | CEFBS_InMips16Mode, // BtnezT8CmpiX16 = 428 |
23670 | 0 | CEFBS_InMips16Mode, // BtnezT8SltX16 = 429 |
23671 | 0 | CEFBS_InMips16Mode, // BtnezT8SltiX16 = 430 |
23672 | 0 | CEFBS_InMips16Mode, // BtnezT8SltiuX16 = 431 |
23673 | 0 | CEFBS_InMips16Mode, // BtnezT8SltuX16 = 432 |
23674 | 0 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // BuildPairF64 = 433 |
23675 | 0 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // BuildPairF64_64 = 434 |
23676 | 0 | CEFBS_HasMT, // CFTC1 = 435 |
23677 | 0 | CEFBS_InMips16Mode, // CONSTPOOL_ENTRY = 436 |
23678 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_FD_PSEUDO = 437 |
23679 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_FW_PSEUDO = 438 |
23680 | 0 | CEFBS_HasMT, // CTTC1 = 439 |
23681 | 0 | CEFBS_InMips16Mode, // Constant32 = 440 |
23682 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULImmMacro = 441 |
23683 | 0 | CEFBS_HasMips3_NotMips64r6_NotCnMips, // DMULMacro = 442 |
23684 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOMacro = 443 |
23685 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DMULOUMacro = 444 |
23686 | 0 | CEFBS_HasStdEnc_HasMips64, // DROL = 445 |
23687 | 0 | CEFBS_HasStdEnc_HasMips64, // DROLImm = 446 |
23688 | 0 | CEFBS_HasStdEnc_HasMips64, // DROR = 447 |
23689 | 0 | CEFBS_HasStdEnc_HasMips64, // DRORImm = 448 |
23690 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivIMacro = 449 |
23691 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDivMacro = 450 |
23692 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemIMacro = 451 |
23693 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSRemMacro = 452 |
23694 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivIMacro = 453 |
23695 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDivMacro = 454 |
23696 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemIMacro = 455 |
23697 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DURemMacro = 456 |
23698 | 0 | CEFBS_NotInMips16Mode, // ERet = 457 |
23699 | 0 | CEFBS_NotInMips16Mode_NotFP64bit_IsNotSoftFloat, // ExtractElementF64 = 458 |
23700 | 0 | CEFBS_NotInMips16Mode_IsFP64bit_IsNotSoftFloat, // ExtractElementF64_64 = 459 |
23701 | 0 | CEFBS_HasStdEnc_HasMSA, // FABS_D = 460 |
23702 | 0 | CEFBS_HasStdEnc_HasMSA, // FABS_W = 461 |
23703 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXP2_D_1_PSEUDO = 462 |
23704 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXP2_W_1_PSEUDO = 463 |
23705 | 0 | CEFBS_HasStdEnc_HasMSA, // FILL_FD_PSEUDO = 464 |
23706 | 0 | CEFBS_HasStdEnc_HasMSA, // FILL_FW_PSEUDO = 465 |
23707 | 0 | CEFBS_InMips16Mode, // GotPrologue16 = 466 |
23708 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX64_PSEUDO = 467 |
23709 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_B_VIDX_PSEUDO = 468 |
23710 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX64_PSEUDO = 469 |
23711 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_D_VIDX_PSEUDO = 470 |
23712 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_PSEUDO = 471 |
23713 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX64_PSEUDO = 472 |
23714 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_FD_VIDX_PSEUDO = 473 |
23715 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_PSEUDO = 474 |
23716 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX64_PSEUDO = 475 |
23717 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_FW_VIDX_PSEUDO = 476 |
23718 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX64_PSEUDO = 477 |
23719 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_H_VIDX_PSEUDO = 478 |
23720 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX64_PSEUDO = 479 |
23721 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_W_VIDX_PSEUDO = 480 |
23722 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit_NoIndirectJumpGuards, // JALR64Pseudo = 481 |
23723 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit_UseIndirectJumpsHazard, // JALRHB64Pseudo = 482 |
23724 | 0 | CEFBS_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // JALRHBPseudo = 483 |
23725 | 0 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALRPseudo = 484 |
23726 | 0 | CEFBS_InMicroMips_HasMips32r6, // JAL_MMR6 = 485 |
23727 | 0 | CEFBS_None, // JalOneReg = 486 |
23728 | 0 | CEFBS_None, // JalTwoReg = 487 |
23729 | 0 | CEFBS_HasStdEnc_NotMips3, // LDMacro = 488 |
23730 | 0 | CEFBS_NotInMips16Mode, // LDR_D = 489 |
23731 | 0 | CEFBS_NotInMips16Mode, // LDR_W = 490 |
23732 | 0 | CEFBS_HasMSA, // LD_F16 = 491 |
23733 | 0 | CEFBS_NotInMips16Mode, // LOAD_ACC128 = 492 |
23734 | 0 | CEFBS_NotInMips16Mode, // LOAD_ACC64 = 493 |
23735 | 0 | CEFBS_NotInMips16Mode, // LOAD_ACC64DSP = 494 |
23736 | 0 | CEFBS_NotInMips16Mode, // LOAD_CCOND_DSP = 495 |
23737 | 0 | CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu = 496 |
23738 | 0 | CEFBS_NotInMips16Mode, // LONG_BRANCH_ADDiu2Op = 497 |
23739 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu = 498 |
23740 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_DADDiu2Op = 499 |
23741 | 0 | CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi = 500 |
23742 | 0 | CEFBS_NotInMips16Mode, // LONG_BRANCH_LUi2Op = 501 |
23743 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LONG_BRANCH_LUi2Op_64 = 502 |
23744 | 0 | CEFBS_InMicroMips, // LWM_MM = 503 |
23745 | 0 | CEFBS_None, // LoadAddrImm32 = 504 |
23746 | 0 | CEFBS_None, // LoadAddrImm64 = 505 |
23747 | 0 | CEFBS_None, // LoadAddrReg32 = 506 |
23748 | 0 | CEFBS_None, // LoadAddrReg64 = 507 |
23749 | 0 | CEFBS_None, // LoadImm32 = 508 |
23750 | 0 | CEFBS_None, // LoadImm64 = 509 |
23751 | 0 | CEFBS_IsFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR = 510 |
23752 | 0 | CEFBS_NotFP64bit_IsNotSoftFloat, // LoadImmDoubleFGR_32 = 511 |
23753 | 0 | CEFBS_None, // LoadImmDoubleGPR = 512 |
23754 | 0 | CEFBS_IsNotSoftFloat, // LoadImmSingleFGR = 513 |
23755 | 0 | CEFBS_None, // LoadImmSingleGPR = 514 |
23756 | 0 | CEFBS_InMips16Mode, // LwConstant32 = 515 |
23757 | 0 | CEFBS_HasMT, // MFTACX = 516 |
23758 | 0 | CEFBS_HasMT, // MFTC0 = 517 |
23759 | 0 | CEFBS_HasMT, // MFTC1 = 518 |
23760 | 0 | CEFBS_HasMT, // MFTDSP = 519 |
23761 | 0 | CEFBS_HasMT, // MFTGPR = 520 |
23762 | 0 | CEFBS_HasMT, // MFTHC1 = 521 |
23763 | 0 | CEFBS_HasMT, // MFTHI = 522 |
23764 | 0 | CEFBS_HasMT, // MFTLO = 523 |
23765 | 0 | CEFBS_None, // MIPSeh_return32 = 524 |
23766 | 0 | CEFBS_None, // MIPSeh_return64 = 525 |
23767 | 0 | CEFBS_HasMSA, // MSA_FP_EXTEND_D_PSEUDO = 526 |
23768 | 0 | CEFBS_HasMSA, // MSA_FP_EXTEND_W_PSEUDO = 527 |
23769 | 0 | CEFBS_HasMSA, // MSA_FP_ROUND_D_PSEUDO = 528 |
23770 | 0 | CEFBS_HasMSA, // MSA_FP_ROUND_W_PSEUDO = 529 |
23771 | 0 | CEFBS_HasMT, // MTTACX = 530 |
23772 | 0 | CEFBS_HasMT, // MTTC0 = 531 |
23773 | 0 | CEFBS_HasMT, // MTTC1 = 532 |
23774 | 0 | CEFBS_HasMT, // MTTDSP = 533 |
23775 | 0 | CEFBS_HasMT, // MTTGPR = 534 |
23776 | 0 | CEFBS_HasMT, // MTTHC1 = 535 |
23777 | 0 | CEFBS_HasMT, // MTTHI = 536 |
23778 | 0 | CEFBS_HasMT, // MTTLO = 537 |
23779 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULImmMacro = 538 |
23780 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOMacro = 539 |
23781 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // MULOUMacro = 540 |
23782 | 0 | CEFBS_InMips16Mode, // MultRxRy16 = 541 |
23783 | 0 | CEFBS_InMips16Mode, // MultRxRyRz16 = 542 |
23784 | 0 | CEFBS_InMips16Mode, // MultuRxRy16 = 543 |
23785 | 0 | CEFBS_InMips16Mode, // MultuRxRyRz16 = 544 |
23786 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // NOP = 545 |
23787 | 0 | CEFBS_IsGP32bit, // NORImm = 546 |
23788 | 0 | CEFBS_IsGP64bit, // NORImm64 = 547 |
23789 | 0 | CEFBS_HasStdEnc_HasMSA, // NOR_V_D_PSEUDO = 548 |
23790 | 0 | CEFBS_HasStdEnc_HasMSA, // NOR_V_H_PSEUDO = 549 |
23791 | 0 | CEFBS_HasStdEnc_HasMSA, // NOR_V_W_PSEUDO = 550 |
23792 | 0 | CEFBS_HasStdEnc_HasMSA, // OR_V_D_PSEUDO = 551 |
23793 | 0 | CEFBS_HasStdEnc_HasMSA, // OR_V_H_PSEUDO = 552 |
23794 | 0 | CEFBS_HasStdEnc_HasMSA, // OR_V_W_PSEUDO = 553 |
23795 | 0 | CEFBS_HasDSP, // PseudoCMPU_EQ_QB = 554 |
23796 | 0 | CEFBS_HasDSP, // PseudoCMPU_LE_QB = 555 |
23797 | 0 | CEFBS_HasDSP, // PseudoCMPU_LT_QB = 556 |
23798 | 0 | CEFBS_HasDSP, // PseudoCMP_EQ_PH = 557 |
23799 | 0 | CEFBS_HasDSP, // PseudoCMP_LE_PH = 558 |
23800 | 0 | CEFBS_HasDSP, // PseudoCMP_LT_PH = 559 |
23801 | 0 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D32_W = 560 |
23802 | 0 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_L = 561 |
23803 | 0 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_D64_W = 562 |
23804 | 0 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_L = 563 |
23805 | 0 | CEFBS_NotInMips16Mode_IsNotSoftFloat, // PseudoCVT_S_W = 564 |
23806 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULT = 565 |
23807 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDMULTu = 566 |
23808 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDSDIV = 567 |
23809 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoDUDIV = 568 |
23810 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I = 569 |
23811 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoD_SELECT_I64 = 570 |
23812 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch = 571 |
23813 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64 = 572 |
23814 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranch64R6 = 573 |
23815 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // PseudoIndirectBranchR6 = 574 |
23816 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoIndirectBranch_MM = 575 |
23817 | 0 | CEFBS_InMicroMips_HasMips32r6, // PseudoIndirectBranch_MMR6 = 576 |
23818 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch = 577 |
23819 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndirectHazardBranch64 = 578 |
23820 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranch64R6 = 579 |
23821 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // PseudoIndrectHazardBranchR6 = 580 |
23822 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADD = 581 |
23823 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMADDU = 582 |
23824 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMADDU_MM = 583 |
23825 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMADD_MM = 584 |
23826 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFHI = 585 |
23827 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFHI64 = 586 |
23828 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMFHI_MM = 587 |
23829 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMFLO = 588 |
23830 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMFLO64 = 589 |
23831 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMFLO_MM = 590 |
23832 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUB = 591 |
23833 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6, // PseudoMSUBU = 592 |
23834 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMSUBU_MM = 593 |
23835 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMSUB_MM = 594 |
23836 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMTLOHI = 595 |
23837 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // PseudoMTLOHI64 = 596 |
23838 | 0 | CEFBS_NotInMips16Mode_HasDSP, // PseudoMTLOHI_DSP = 597 |
23839 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMTLOHI_MM = 598 |
23840 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULT = 599 |
23841 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMULT_MM = 600 |
23842 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // PseudoMULTu = 601 |
23843 | 0 | CEFBS_InMicroMips_NotMips32r6, // PseudoMULTu_MM = 602 |
23844 | 0 | CEFBS_HasDSP, // PseudoPICK_PH = 603 |
23845 | 0 | CEFBS_HasDSP, // PseudoPICK_QB = 604 |
23846 | 0 | CEFBS_None, // PseudoReturn = 605 |
23847 | 0 | CEFBS_IsGP64bit, // PseudoReturn64 = 606 |
23848 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoSDIV = 607 |
23849 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_F_D32 = 608 |
23850 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_F_D64 = 609 |
23851 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I = 610 |
23852 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_I64 = 611 |
23853 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_F_S = 612 |
23854 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECTFP_T_D32 = 613 |
23855 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECTFP_T_D64 = 614 |
23856 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I = 615 |
23857 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_I64 = 616 |
23858 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECTFP_T_S = 617 |
23859 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips4_32, // PseudoSELECT_D32 = 618 |
23860 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips4_32, // PseudoSELECT_D64 = 619 |
23861 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I = 620 |
23862 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_I64 = 621 |
23863 | 0 | CEFBS_HasStdEnc_NotMips4_32, // PseudoSELECT_S = 622 |
23864 | 0 | CEFBS_IsFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D = 623 |
23865 | 0 | CEFBS_NotFP64bit_IsNotSoftFloat, // PseudoTRUNC_W_D32 = 624 |
23866 | 0 | CEFBS_None, // PseudoTRUNC_W_S = 625 |
23867 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // PseudoUDIV = 626 |
23868 | 0 | CEFBS_None, // ROL = 627 |
23869 | 0 | CEFBS_None, // ROLImm = 628 |
23870 | 0 | CEFBS_None, // ROR = 629 |
23871 | 0 | CEFBS_None, // RORImm = 630 |
23872 | 0 | CEFBS_NotInMips16Mode, // RetRA = 631 |
23873 | 0 | CEFBS_InMips16Mode, // RetRA16 = 632 |
23874 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat, // SDC1_M1 = 633 |
23875 | 0 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // SDIV_MM_Pseudo = 634 |
23876 | 0 | CEFBS_HasStdEnc_NotMips3, // SDMacro = 635 |
23877 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivIMacro = 636 |
23878 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SDivMacro = 637 |
23879 | 0 | CEFBS_NotCnMips, // SEQIMacro = 638 |
23880 | 0 | CEFBS_NotCnMips, // SEQMacro = 639 |
23881 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SGE = 640 |
23882 | 0 | CEFBS_IsGP32bit_NotInMicroMips, // SGEImm = 641 |
23883 | 0 | CEFBS_IsGP64bit, // SGEImm64 = 642 |
23884 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SGEU = 643 |
23885 | 0 | CEFBS_IsGP32bit_NotInMicroMips, // SGEUImm = 644 |
23886 | 0 | CEFBS_IsGP64bit, // SGEUImm64 = 645 |
23887 | 0 | CEFBS_IsGP32bit_NotInMicroMips, // SGTImm = 646 |
23888 | 0 | CEFBS_IsGP64bit, // SGTImm64 = 647 |
23889 | 0 | CEFBS_IsGP32bit_NotInMicroMips, // SGTUImm = 648 |
23890 | 0 | CEFBS_IsGP64bit, // SGTUImm64 = 649 |
23891 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLE = 650 |
23892 | 0 | CEFBS_IsGP32bit_NotInMicroMips, // SLEImm = 651 |
23893 | 0 | CEFBS_IsGP64bit, // SLEImm64 = 652 |
23894 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLEU = 653 |
23895 | 0 | CEFBS_IsGP32bit_NotInMicroMips, // SLEUImm = 654 |
23896 | 0 | CEFBS_IsGP64bit, // SLEUImm64 = 655 |
23897 | 0 | CEFBS_IsGP64bit, // SLTImm64 = 656 |
23898 | 0 | CEFBS_IsGP64bit, // SLTUImm64 = 657 |
23899 | 0 | CEFBS_NotCnMips, // SNEIMacro = 658 |
23900 | 0 | CEFBS_NotCnMips, // SNEMacro = 659 |
23901 | 0 | CEFBS_None, // SNZ_B_PSEUDO = 660 |
23902 | 0 | CEFBS_None, // SNZ_D_PSEUDO = 661 |
23903 | 0 | CEFBS_None, // SNZ_H_PSEUDO = 662 |
23904 | 0 | CEFBS_None, // SNZ_V_PSEUDO = 663 |
23905 | 0 | CEFBS_None, // SNZ_W_PSEUDO = 664 |
23906 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemIMacro = 665 |
23907 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // SRemMacro = 666 |
23908 | 0 | CEFBS_NotInMips16Mode, // STORE_ACC128 = 667 |
23909 | 0 | CEFBS_NotInMips16Mode, // STORE_ACC64 = 668 |
23910 | 0 | CEFBS_NotInMips16Mode, // STORE_ACC64DSP = 669 |
23911 | 0 | CEFBS_NotInMips16Mode, // STORE_CCOND_DSP = 670 |
23912 | 0 | CEFBS_NotInMips16Mode, // STR_D = 671 |
23913 | 0 | CEFBS_NotInMips16Mode, // STR_W = 672 |
23914 | 0 | CEFBS_HasMSA, // ST_F16 = 673 |
23915 | 0 | CEFBS_InMicroMips, // SWM_MM = 674 |
23916 | 0 | CEFBS_None, // SZ_B_PSEUDO = 675 |
23917 | 0 | CEFBS_None, // SZ_D_PSEUDO = 676 |
23918 | 0 | CEFBS_None, // SZ_H_PSEUDO = 677 |
23919 | 0 | CEFBS_None, // SZ_V_PSEUDO = 678 |
23920 | 0 | CEFBS_None, // SZ_W_PSEUDO = 679 |
23921 | 0 | CEFBS_HasCnMipsP, // SaaAddr = 680 |
23922 | 0 | CEFBS_HasCnMipsP, // SaadAddr = 681 |
23923 | 0 | CEFBS_InMips16Mode, // SelBeqZ = 682 |
23924 | 0 | CEFBS_InMips16Mode, // SelBneZ = 683 |
23925 | 0 | CEFBS_InMips16Mode, // SelTBteqZCmp = 684 |
23926 | 0 | CEFBS_InMips16Mode, // SelTBteqZCmpi = 685 |
23927 | 0 | CEFBS_InMips16Mode, // SelTBteqZSlt = 686 |
23928 | 0 | CEFBS_InMips16Mode, // SelTBteqZSlti = 687 |
23929 | 0 | CEFBS_InMips16Mode, // SelTBteqZSltiu = 688 |
23930 | 0 | CEFBS_InMips16Mode, // SelTBteqZSltu = 689 |
23931 | 0 | CEFBS_InMips16Mode, // SelTBtneZCmp = 690 |
23932 | 0 | CEFBS_InMips16Mode, // SelTBtneZCmpi = 691 |
23933 | 0 | CEFBS_InMips16Mode, // SelTBtneZSlt = 692 |
23934 | 0 | CEFBS_InMips16Mode, // SelTBtneZSlti = 693 |
23935 | 0 | CEFBS_InMips16Mode, // SelTBtneZSltiu = 694 |
23936 | 0 | CEFBS_InMips16Mode, // SelTBtneZSltu = 695 |
23937 | 0 | CEFBS_InMips16Mode, // SltCCRxRy16 = 696 |
23938 | 0 | CEFBS_InMips16Mode, // SltiCCRxImmX16 = 697 |
23939 | 0 | CEFBS_InMips16Mode, // SltiuCCRxImmX16 = 698 |
23940 | 0 | CEFBS_InMips16Mode, // SltuCCRxRy16 = 699 |
23941 | 0 | CEFBS_InMips16Mode, // SltuRxRyRz16 = 700 |
23942 | 0 | CEFBS_HasStdEnc_NotInMips16Mode_NotInMicroMips, // TAILCALL = 701 |
23943 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALL64R6REG = 702 |
23944 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHB64R6REG = 703 |
23945 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLHBR6REG = 704 |
23946 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLR6REG = 705 |
23947 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG = 706 |
23948 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips3_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_NoIndirectJumpGuards, // TAILCALLREG64 = 707 |
23949 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB = 708 |
23950 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips32r2_NotMips32r6_NotMips64r6_NotInMips16Mode_NotInMicroMips_UseIndirectJumpsHazard, // TAILCALLREGHB64 = 709 |
23951 | 0 | CEFBS_InMicroMips_NotMips32r6, // TAILCALLREG_MM = 710 |
23952 | 0 | CEFBS_InMicroMips_HasMips32r6, // TAILCALLREG_MMR6 = 711 |
23953 | 0 | CEFBS_InMicroMips_NotMips32r6, // TAILCALL_MM = 712 |
23954 | 0 | CEFBS_InMicroMips_HasMips32r6, // TAILCALL_MMR6 = 713 |
23955 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // TRAP = 714 |
23956 | 0 | CEFBS_InMicroMips, // TRAP_MM = 715 |
23957 | 0 | CEFBS_InMicroMips_NotMips32r6_NotMips64r6, // UDIV_MM_Pseudo = 716 |
23958 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivIMacro = 717 |
23959 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // UDivMacro = 718 |
23960 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemIMacro = 719 |
23961 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6, // URemMacro = 720 |
23962 | 0 | CEFBS_None, // Ulh = 721 |
23963 | 0 | CEFBS_None, // Ulhu = 722 |
23964 | 0 | CEFBS_None, // Ulw = 723 |
23965 | 0 | CEFBS_None, // Ush = 724 |
23966 | 0 | CEFBS_None, // Usw = 725 |
23967 | 0 | CEFBS_HasStdEnc_HasMSA, // XOR_V_D_PSEUDO = 726 |
23968 | 0 | CEFBS_HasStdEnc_HasMSA, // XOR_V_H_PSEUDO = 727 |
23969 | 0 | CEFBS_HasStdEnc_HasMSA, // XOR_V_W_PSEUDO = 728 |
23970 | 0 | CEFBS_HasDSP, // ABSQ_S_PH = 729 |
23971 | 0 | CEFBS_InMicroMips_HasDSP, // ABSQ_S_PH_MM = 730 |
23972 | 0 | CEFBS_HasDSPR2, // ABSQ_S_QB = 731 |
23973 | 0 | CEFBS_InMicroMips_HasDSPR2, // ABSQ_S_QB_MMR2 = 732 |
23974 | 0 | CEFBS_HasDSP, // ABSQ_S_W = 733 |
23975 | 0 | CEFBS_InMicroMips_HasDSP, // ABSQ_S_W_MM = 734 |
23976 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // ADD = 735 |
23977 | 0 | CEFBS_HasStdEnc_HasMips32r6, // ADDIUPC = 736 |
23978 | 0 | CEFBS_InMicroMips_NotMips32r6, // ADDIUPC_MM = 737 |
23979 | 0 | CEFBS_InMicroMips_HasMips32r6, // ADDIUPC_MMR6 = 738 |
23980 | 0 | CEFBS_InMicroMips, // ADDIUR1SP_MM = 739 |
23981 | 0 | CEFBS_InMicroMips, // ADDIUR2_MM = 740 |
23982 | 0 | CEFBS_InMicroMips, // ADDIUS5_MM = 741 |
23983 | 0 | CEFBS_InMicroMips, // ADDIUSP_MM = 742 |
23984 | 0 | CEFBS_InMicroMips_HasMips32r6, // ADDIU_MMR6 = 743 |
23985 | 0 | CEFBS_HasDSPR2, // ADDQH_PH = 744 |
23986 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_PH_MMR2 = 745 |
23987 | 0 | CEFBS_HasDSPR2, // ADDQH_R_PH = 746 |
23988 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_PH_MMR2 = 747 |
23989 | 0 | CEFBS_HasDSPR2, // ADDQH_R_W = 748 |
23990 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_R_W_MMR2 = 749 |
23991 | 0 | CEFBS_HasDSPR2, // ADDQH_W = 750 |
23992 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDQH_W_MMR2 = 751 |
23993 | 0 | CEFBS_HasDSP, // ADDQ_PH = 752 |
23994 | 0 | CEFBS_InMicroMips_HasDSP, // ADDQ_PH_MM = 753 |
23995 | 0 | CEFBS_HasDSP, // ADDQ_S_PH = 754 |
23996 | 0 | CEFBS_InMicroMips_HasDSP, // ADDQ_S_PH_MM = 755 |
23997 | 0 | CEFBS_HasDSP, // ADDQ_S_W = 756 |
23998 | 0 | CEFBS_InMicroMips_HasDSP, // ADDQ_S_W_MM = 757 |
23999 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // ADDR_PS64 = 758 |
24000 | 0 | CEFBS_HasDSP, // ADDSC = 759 |
24001 | 0 | CEFBS_InMicroMips_HasDSP, // ADDSC_MM = 760 |
24002 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_B = 761 |
24003 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_D = 762 |
24004 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_H = 763 |
24005 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_A_W = 764 |
24006 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_B = 765 |
24007 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_D = 766 |
24008 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_H = 767 |
24009 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_S_W = 768 |
24010 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_B = 769 |
24011 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_D = 770 |
24012 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_H = 771 |
24013 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDS_U_W = 772 |
24014 | 0 | CEFBS_InMicroMips_NotMips32r6, // ADDU16_MM = 773 |
24015 | 0 | CEFBS_InMicroMips_HasMips32r6, // ADDU16_MMR6 = 774 |
24016 | 0 | CEFBS_HasDSPR2, // ADDUH_QB = 775 |
24017 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDUH_QB_MMR2 = 776 |
24018 | 0 | CEFBS_HasDSPR2, // ADDUH_R_QB = 777 |
24019 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDUH_R_QB_MMR2 = 778 |
24020 | 0 | CEFBS_InMicroMips_HasMips32r6, // ADDU_MMR6 = 779 |
24021 | 0 | CEFBS_HasDSPR2, // ADDU_PH = 780 |
24022 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDU_PH_MMR2 = 781 |
24023 | 0 | CEFBS_HasDSP, // ADDU_QB = 782 |
24024 | 0 | CEFBS_InMicroMips_HasDSP, // ADDU_QB_MM = 783 |
24025 | 0 | CEFBS_HasDSPR2, // ADDU_S_PH = 784 |
24026 | 0 | CEFBS_InMicroMips_HasDSPR2, // ADDU_S_PH_MMR2 = 785 |
24027 | 0 | CEFBS_HasDSP, // ADDU_S_QB = 786 |
24028 | 0 | CEFBS_InMicroMips_HasDSP, // ADDU_S_QB_MM = 787 |
24029 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDVI_B = 788 |
24030 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDVI_D = 789 |
24031 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDVI_H = 790 |
24032 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDVI_W = 791 |
24033 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDV_B = 792 |
24034 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDV_D = 793 |
24035 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDV_H = 794 |
24036 | 0 | CEFBS_HasStdEnc_HasMSA, // ADDV_W = 795 |
24037 | 0 | CEFBS_HasDSP, // ADDWC = 796 |
24038 | 0 | CEFBS_InMicroMips_HasDSP, // ADDWC_MM = 797 |
24039 | 0 | CEFBS_HasStdEnc_HasMSA, // ADD_A_B = 798 |
24040 | 0 | CEFBS_HasStdEnc_HasMSA, // ADD_A_D = 799 |
24041 | 0 | CEFBS_HasStdEnc_HasMSA, // ADD_A_H = 800 |
24042 | 0 | CEFBS_HasStdEnc_HasMSA, // ADD_A_W = 801 |
24043 | 0 | CEFBS_InMicroMips_NotMips32r6, // ADD_MM = 802 |
24044 | 0 | CEFBS_InMicroMips_HasMips32r6, // ADD_MMR6 = 803 |
24045 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // ADDi = 804 |
24046 | 0 | CEFBS_InMicroMips_NotMips32r6, // ADDi_MM = 805 |
24047 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // ADDiu = 806 |
24048 | 0 | CEFBS_InMicroMips_NotMips32r6, // ADDiu_MM = 807 |
24049 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // ADDu = 808 |
24050 | 0 | CEFBS_InMicroMips_NotMips32r6, // ADDu_MM = 809 |
24051 | 0 | CEFBS_HasStdEnc_HasMips32r6, // ALIGN = 810 |
24052 | 0 | CEFBS_InMicroMips_HasMips32r6, // ALIGN_MMR6 = 811 |
24053 | 0 | CEFBS_HasStdEnc_HasMips32r6, // ALUIPC = 812 |
24054 | 0 | CEFBS_InMicroMips_HasMips32r6, // ALUIPC_MMR6 = 813 |
24055 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // AND = 814 |
24056 | 0 | CEFBS_InMicroMips_NotMips32r6, // AND16_MM = 815 |
24057 | 0 | CEFBS_InMicroMips_HasMips32r6, // AND16_MMR6 = 816 |
24058 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // AND64 = 817 |
24059 | 0 | CEFBS_InMicroMips_NotMips32r6, // ANDI16_MM = 818 |
24060 | 0 | CEFBS_InMicroMips_HasMips32r6, // ANDI16_MMR6 = 819 |
24061 | 0 | CEFBS_HasStdEnc_HasMSA, // ANDI_B = 820 |
24062 | 0 | CEFBS_InMicroMips_HasMips32r6, // ANDI_MMR6 = 821 |
24063 | 0 | CEFBS_InMicroMips_NotMips32r6, // AND_MM = 822 |
24064 | 0 | CEFBS_InMicroMips_HasMips32r6, // AND_MMR6 = 823 |
24065 | 0 | CEFBS_HasStdEnc_HasMSA, // AND_V = 824 |
24066 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // ANDi = 825 |
24067 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // ANDi64 = 826 |
24068 | 0 | CEFBS_InMicroMips_NotMips32r6, // ANDi_MM = 827 |
24069 | 0 | CEFBS_HasDSPR2, // APPEND = 828 |
24070 | 0 | CEFBS_InMicroMips_HasDSPR2, // APPEND_MMR2 = 829 |
24071 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_B = 830 |
24072 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_D = 831 |
24073 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_H = 832 |
24074 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_S_W = 833 |
24075 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_B = 834 |
24076 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_D = 835 |
24077 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_H = 836 |
24078 | 0 | CEFBS_HasStdEnc_HasMSA, // ASUB_U_W = 837 |
24079 | 0 | CEFBS_HasStdEnc_HasMips32r6, // AUI = 838 |
24080 | 0 | CEFBS_HasStdEnc_HasMips32r6, // AUIPC = 839 |
24081 | 0 | CEFBS_InMicroMips_HasMips32r6, // AUIPC_MMR6 = 840 |
24082 | 0 | CEFBS_InMicroMips_HasMips32r6, // AUI_MMR6 = 841 |
24083 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_S_B = 842 |
24084 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_S_D = 843 |
24085 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_S_H = 844 |
24086 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_S_W = 845 |
24087 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_U_B = 846 |
24088 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_U_D = 847 |
24089 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_U_H = 848 |
24090 | 0 | CEFBS_HasStdEnc_HasMSA, // AVER_U_W = 849 |
24091 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_S_B = 850 |
24092 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_S_D = 851 |
24093 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_S_H = 852 |
24094 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_S_W = 853 |
24095 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_U_B = 854 |
24096 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_U_D = 855 |
24097 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_U_H = 856 |
24098 | 0 | CEFBS_HasStdEnc_HasMSA, // AVE_U_W = 857 |
24099 | 0 | CEFBS_InMips16Mode, // AddiuRxImmX16 = 858 |
24100 | 0 | CEFBS_InMips16Mode, // AddiuRxPcImmX16 = 859 |
24101 | 0 | CEFBS_InMips16Mode, // AddiuRxRxImm16 = 860 |
24102 | 0 | CEFBS_InMips16Mode, // AddiuRxRxImmX16 = 861 |
24103 | 0 | CEFBS_InMips16Mode, // AddiuRxRyOffMemX16 = 862 |
24104 | 0 | CEFBS_InMips16Mode, // AddiuSpImm16 = 863 |
24105 | 0 | CEFBS_InMips16Mode, // AddiuSpImmX16 = 864 |
24106 | 0 | CEFBS_InMips16Mode, // AdduRxRyRz16 = 865 |
24107 | 0 | CEFBS_InMips16Mode, // AndRxRxRy16 = 866 |
24108 | 0 | CEFBS_InMicroMips, // B16_MM = 867 |
24109 | 0 | CEFBS_HasCnMips, // BADDu = 868 |
24110 | 0 | CEFBS_HasStdEnc_HasMips32r6, // BAL = 869 |
24111 | 0 | CEFBS_HasStdEnc_HasMips32r6, // BALC = 870 |
24112 | 0 | CEFBS_InMicroMips_HasMips32r6, // BALC_MMR6 = 871 |
24113 | 0 | CEFBS_HasDSPR2, // BALIGN = 872 |
24114 | 0 | CEFBS_InMicroMips_HasDSPR2, // BALIGN_MMR2 = 873 |
24115 | 0 | CEFBS_HasCnMips, // BBIT0 = 874 |
24116 | 0 | CEFBS_HasCnMips, // BBIT032 = 875 |
24117 | 0 | CEFBS_HasCnMips, // BBIT1 = 876 |
24118 | 0 | CEFBS_HasCnMips, // BBIT132 = 877 |
24119 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC = 878 |
24120 | 0 | CEFBS_InMicroMips_HasMips32r6, // BC16_MMR6 = 879 |
24121 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1EQZ = 880 |
24122 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1EQZC_MMR6 = 881 |
24123 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1F = 882 |
24124 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1FL = 883 |
24125 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1F_MM = 884 |
24126 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // BC1NEZ = 885 |
24127 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // BC1NEZC_MMR6 = 886 |
24128 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1T = 887 |
24129 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // BC1TL = 888 |
24130 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // BC1T_MM = 889 |
24131 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2EQZ = 890 |
24132 | 0 | CEFBS_InMicroMips_HasMips32r6, // BC2EQZC_MMR6 = 891 |
24133 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BC2NEZ = 892 |
24134 | 0 | CEFBS_InMicroMips_HasMips32r6, // BC2NEZC_MMR6 = 893 |
24135 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLRI_B = 894 |
24136 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLRI_D = 895 |
24137 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLRI_H = 896 |
24138 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLRI_W = 897 |
24139 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLR_B = 898 |
24140 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLR_D = 899 |
24141 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLR_H = 900 |
24142 | 0 | CEFBS_HasStdEnc_HasMSA, // BCLR_W = 901 |
24143 | 0 | CEFBS_InMicroMips_HasMips32r6, // BC_MMR6 = 902 |
24144 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BEQ = 903 |
24145 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // BEQ64 = 904 |
24146 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQC = 905 |
24147 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQC64 = 906 |
24148 | 0 | CEFBS_InMicroMips_HasMips32r6, // BEQC_MMR6 = 907 |
24149 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BEQL = 908 |
24150 | 0 | CEFBS_InMicroMips_NotMips32r6, // BEQZ16_MM = 909 |
24151 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZALC = 910 |
24152 | 0 | CEFBS_InMicroMips_HasMips32r6, // BEQZALC_MMR6 = 911 |
24153 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BEQZC = 912 |
24154 | 0 | CEFBS_InMicroMips_HasMips32r6, // BEQZC16_MMR6 = 913 |
24155 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BEQZC64 = 914 |
24156 | 0 | CEFBS_InMicroMips_NotMips32r6, // BEQZC_MM = 915 |
24157 | 0 | CEFBS_InMicroMips_HasMips32r6, // BEQZC_MMR6 = 916 |
24158 | 0 | CEFBS_InMicroMips_NotMips32r6, // BEQ_MM = 917 |
24159 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEC = 918 |
24160 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEC64 = 919 |
24161 | 0 | CEFBS_InMicroMips_HasMips32r6, // BGEC_MMR6 = 920 |
24162 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEUC = 921 |
24163 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEUC64 = 922 |
24164 | 0 | CEFBS_InMicroMips_HasMips32r6, // BGEUC_MMR6 = 923 |
24165 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BGEZ = 924 |
24166 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // BGEZ64 = 925 |
24167 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZAL = 926 |
24168 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZALC = 927 |
24169 | 0 | CEFBS_InMicroMips_HasMips32r6, // BGEZALC_MMR6 = 928 |
24170 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZALL = 929 |
24171 | 0 | CEFBS_InMicroMips_NotMips32r6, // BGEZALS_MM = 930 |
24172 | 0 | CEFBS_InMicroMips_NotMips32r6, // BGEZAL_MM = 931 |
24173 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGEZC = 932 |
24174 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGEZC64 = 933 |
24175 | 0 | CEFBS_InMicroMips_HasMips32r6, // BGEZC_MMR6 = 934 |
24176 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGEZL = 935 |
24177 | 0 | CEFBS_InMicroMips_NotMips32r6, // BGEZ_MM = 936 |
24178 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BGTZ = 937 |
24179 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // BGTZ64 = 938 |
24180 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZALC = 939 |
24181 | 0 | CEFBS_InMicroMips_HasMips32r6, // BGTZALC_MMR6 = 940 |
24182 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BGTZC = 941 |
24183 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BGTZC64 = 942 |
24184 | 0 | CEFBS_InMicroMips_HasMips32r6, // BGTZC_MMR6 = 943 |
24185 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BGTZL = 944 |
24186 | 0 | CEFBS_InMicroMips_NotMips32r6, // BGTZ_MM = 945 |
24187 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSLI_B = 946 |
24188 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSLI_D = 947 |
24189 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSLI_H = 948 |
24190 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSLI_W = 949 |
24191 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSL_B = 950 |
24192 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSL_D = 951 |
24193 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSL_H = 952 |
24194 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSL_W = 953 |
24195 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSRI_B = 954 |
24196 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSRI_D = 955 |
24197 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSRI_H = 956 |
24198 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSRI_W = 957 |
24199 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSR_B = 958 |
24200 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSR_D = 959 |
24201 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSR_H = 960 |
24202 | 0 | CEFBS_HasStdEnc_HasMSA, // BINSR_W = 961 |
24203 | 0 | CEFBS_HasDSP, // BITREV = 962 |
24204 | 0 | CEFBS_InMicroMips_HasDSP, // BITREV_MM = 963 |
24205 | 0 | CEFBS_HasStdEnc_HasMips32r6, // BITSWAP = 964 |
24206 | 0 | CEFBS_InMicroMips_HasMips32r6, // BITSWAP_MMR6 = 965 |
24207 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BLEZ = 966 |
24208 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // BLEZ64 = 967 |
24209 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZALC = 968 |
24210 | 0 | CEFBS_InMicroMips_HasMips32r6, // BLEZALC_MMR6 = 969 |
24211 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLEZC = 970 |
24212 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLEZC64 = 971 |
24213 | 0 | CEFBS_InMicroMips_HasMips32r6, // BLEZC_MMR6 = 972 |
24214 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLEZL = 973 |
24215 | 0 | CEFBS_InMicroMips_NotMips32r6, // BLEZ_MM = 974 |
24216 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTC = 975 |
24217 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTC64 = 976 |
24218 | 0 | CEFBS_InMicroMips_HasMips32r6, // BLTC_MMR6 = 977 |
24219 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTUC = 978 |
24220 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTUC64 = 979 |
24221 | 0 | CEFBS_InMicroMips_HasMips32r6, // BLTUC_MMR6 = 980 |
24222 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BLTZ = 981 |
24223 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // BLTZ64 = 982 |
24224 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZAL = 983 |
24225 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZALC = 984 |
24226 | 0 | CEFBS_InMicroMips_HasMips32r6, // BLTZALC_MMR6 = 985 |
24227 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZALL = 986 |
24228 | 0 | CEFBS_InMicroMips_NotMips32r6, // BLTZALS_MM = 987 |
24229 | 0 | CEFBS_InMicroMips_NotMips32r6, // BLTZAL_MM = 988 |
24230 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BLTZC = 989 |
24231 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BLTZC64 = 990 |
24232 | 0 | CEFBS_InMicroMips_HasMips32r6, // BLTZC_MMR6 = 991 |
24233 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BLTZL = 992 |
24234 | 0 | CEFBS_InMicroMips_NotMips32r6, // BLTZ_MM = 993 |
24235 | 0 | CEFBS_HasStdEnc_HasMSA, // BMNZI_B = 994 |
24236 | 0 | CEFBS_HasStdEnc_HasMSA, // BMNZ_V = 995 |
24237 | 0 | CEFBS_HasStdEnc_HasMSA, // BMZI_B = 996 |
24238 | 0 | CEFBS_HasStdEnc_HasMSA, // BMZ_V = 997 |
24239 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BNE = 998 |
24240 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // BNE64 = 999 |
24241 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEC = 1000 |
24242 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEC64 = 1001 |
24243 | 0 | CEFBS_InMicroMips_HasMips32r6, // BNEC_MMR6 = 1002 |
24244 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEGI_B = 1003 |
24245 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEGI_D = 1004 |
24246 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEGI_H = 1005 |
24247 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEGI_W = 1006 |
24248 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEG_B = 1007 |
24249 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEG_D = 1008 |
24250 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEG_H = 1009 |
24251 | 0 | CEFBS_HasStdEnc_HasMSA, // BNEG_W = 1010 |
24252 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // BNEL = 1011 |
24253 | 0 | CEFBS_InMicroMips_NotMips32r6, // BNEZ16_MM = 1012 |
24254 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZALC = 1013 |
24255 | 0 | CEFBS_InMicroMips_HasMips32r6, // BNEZALC_MMR6 = 1014 |
24256 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNEZC = 1015 |
24257 | 0 | CEFBS_InMicroMips_HasMips32r6, // BNEZC16_MMR6 = 1016 |
24258 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // BNEZC64 = 1017 |
24259 | 0 | CEFBS_InMicroMips_NotMips32r6, // BNEZC_MM = 1018 |
24260 | 0 | CEFBS_InMicroMips_HasMips32r6, // BNEZC_MMR6 = 1019 |
24261 | 0 | CEFBS_InMicroMips_NotMips32r6, // BNE_MM = 1020 |
24262 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BNVC = 1021 |
24263 | 0 | CEFBS_InMicroMips_HasMips32r6, // BNVC_MMR6 = 1022 |
24264 | 0 | CEFBS_HasStdEnc_HasMSA, // BNZ_B = 1023 |
24265 | 0 | CEFBS_HasStdEnc_HasMSA, // BNZ_D = 1024 |
24266 | 0 | CEFBS_HasStdEnc_HasMSA, // BNZ_H = 1025 |
24267 | 0 | CEFBS_HasStdEnc_HasMSA, // BNZ_V = 1026 |
24268 | 0 | CEFBS_HasStdEnc_HasMSA, // BNZ_W = 1027 |
24269 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // BOVC = 1028 |
24270 | 0 | CEFBS_InMicroMips_HasMips32r6, // BOVC_MMR6 = 1029 |
24271 | 0 | CEFBS_HasDSP_NotInMicroMips, // BPOSGE32 = 1030 |
24272 | 0 | CEFBS_InMicroMips_HasDSPR3, // BPOSGE32C_MMR3 = 1031 |
24273 | 0 | CEFBS_InMicroMips_NotMips32r6_HasDSP, // BPOSGE32_MM = 1032 |
24274 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // BREAK = 1033 |
24275 | 0 | CEFBS_InMicroMips_NotMips32r6, // BREAK16_MM = 1034 |
24276 | 0 | CEFBS_InMicroMips_HasMips32r6, // BREAK16_MMR6 = 1035 |
24277 | 0 | CEFBS_InMicroMips, // BREAK_MM = 1036 |
24278 | 0 | CEFBS_InMicroMips_HasMips32r6, // BREAK_MMR6 = 1037 |
24279 | 0 | CEFBS_HasStdEnc_HasMSA, // BSELI_B = 1038 |
24280 | 0 | CEFBS_HasStdEnc_HasMSA, // BSEL_V = 1039 |
24281 | 0 | CEFBS_HasStdEnc_HasMSA, // BSETI_B = 1040 |
24282 | 0 | CEFBS_HasStdEnc_HasMSA, // BSETI_D = 1041 |
24283 | 0 | CEFBS_HasStdEnc_HasMSA, // BSETI_H = 1042 |
24284 | 0 | CEFBS_HasStdEnc_HasMSA, // BSETI_W = 1043 |
24285 | 0 | CEFBS_HasStdEnc_HasMSA, // BSET_B = 1044 |
24286 | 0 | CEFBS_HasStdEnc_HasMSA, // BSET_D = 1045 |
24287 | 0 | CEFBS_HasStdEnc_HasMSA, // BSET_H = 1046 |
24288 | 0 | CEFBS_HasStdEnc_HasMSA, // BSET_W = 1047 |
24289 | 0 | CEFBS_HasStdEnc_HasMSA, // BZ_B = 1048 |
24290 | 0 | CEFBS_HasStdEnc_HasMSA, // BZ_D = 1049 |
24291 | 0 | CEFBS_HasStdEnc_HasMSA, // BZ_H = 1050 |
24292 | 0 | CEFBS_HasStdEnc_HasMSA, // BZ_V = 1051 |
24293 | 0 | CEFBS_HasStdEnc_HasMSA, // BZ_W = 1052 |
24294 | 0 | CEFBS_InMips16Mode, // BeqzRxImm16 = 1053 |
24295 | 0 | CEFBS_InMips16Mode, // BeqzRxImmX16 = 1054 |
24296 | 0 | CEFBS_InMips16Mode, // Bimm16 = 1055 |
24297 | 0 | CEFBS_InMips16Mode, // BimmX16 = 1056 |
24298 | 0 | CEFBS_InMips16Mode, // BnezRxImm16 = 1057 |
24299 | 0 | CEFBS_InMips16Mode, // BnezRxImmX16 = 1058 |
24300 | 0 | CEFBS_InMips16Mode, // Break16 = 1059 |
24301 | 0 | CEFBS_InMips16Mode, // Bteqz16 = 1060 |
24302 | 0 | CEFBS_InMips16Mode, // BteqzX16 = 1061 |
24303 | 0 | CEFBS_InMips16Mode, // Btnez16 = 1062 |
24304 | 0 | CEFBS_InMips16Mode, // BtnezX16 = 1063 |
24305 | 0 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // CACHE = 1064 |
24306 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // CACHEE = 1065 |
24307 | 0 | CEFBS_InMicroMips_HasEVA, // CACHEE_MM = 1066 |
24308 | 0 | CEFBS_InMicroMips_NotMips32r6, // CACHE_MM = 1067 |
24309 | 0 | CEFBS_InMicroMips_HasMips32r6, // CACHE_MMR6 = 1068 |
24310 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // CACHE_R6 = 1069 |
24311 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // CEIL_L_D64 = 1070 |
24312 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_D_MMR6 = 1071 |
24313 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_L_S = 1072 |
24314 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_L_S_MMR6 = 1073 |
24315 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D32 = 1074 |
24316 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_D64 = 1075 |
24317 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_D_MMR6 = 1076 |
24318 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CEIL_W_MM = 1077 |
24319 | 0 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // CEIL_W_S = 1078 |
24320 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // CEIL_W_S_MM = 1079 |
24321 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CEIL_W_S_MMR6 = 1080 |
24322 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQI_B = 1081 |
24323 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQI_D = 1082 |
24324 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQI_H = 1083 |
24325 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQI_W = 1084 |
24326 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQ_B = 1085 |
24327 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQ_D = 1086 |
24328 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQ_H = 1087 |
24329 | 0 | CEFBS_HasStdEnc_HasMSA, // CEQ_W = 1088 |
24330 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CFC1 = 1089 |
24331 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // CFC1_MM = 1090 |
24332 | 0 | CEFBS_InMicroMips, // CFC2_MM = 1091 |
24333 | 0 | CEFBS_HasStdEnc_HasMSA, // CFCMSA = 1092 |
24334 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS = 1093 |
24335 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS32 = 1094 |
24336 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS64_32 = 1095 |
24337 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // CINS_i32 = 1096 |
24338 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_D = 1097 |
24339 | 0 | CEFBS_InMicroMips_HasMips32r6, // CLASS_D_MMR6 = 1098 |
24340 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CLASS_S = 1099 |
24341 | 0 | CEFBS_InMicroMips_HasMips32r6, // CLASS_S_MMR6 = 1100 |
24342 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_B = 1101 |
24343 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_D = 1102 |
24344 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_H = 1103 |
24345 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_S_W = 1104 |
24346 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_B = 1105 |
24347 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_D = 1106 |
24348 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_H = 1107 |
24349 | 0 | CEFBS_HasStdEnc_HasMSA, // CLEI_U_W = 1108 |
24350 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_S_B = 1109 |
24351 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_S_D = 1110 |
24352 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_S_H = 1111 |
24353 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_S_W = 1112 |
24354 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_U_B = 1113 |
24355 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_U_D = 1114 |
24356 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_U_H = 1115 |
24357 | 0 | CEFBS_HasStdEnc_HasMSA, // CLE_U_W = 1116 |
24358 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLO = 1117 |
24359 | 0 | CEFBS_InMicroMips, // CLO_MM = 1118 |
24360 | 0 | CEFBS_InMicroMips_HasMips32r6, // CLO_MMR6 = 1119 |
24361 | 0 | CEFBS_HasStdEnc_HasMips32r6, // CLO_R6 = 1120 |
24362 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_B = 1121 |
24363 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_D = 1122 |
24364 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_H = 1123 |
24365 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_S_W = 1124 |
24366 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_B = 1125 |
24367 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_D = 1126 |
24368 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_H = 1127 |
24369 | 0 | CEFBS_HasStdEnc_HasMSA, // CLTI_U_W = 1128 |
24370 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_S_B = 1129 |
24371 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_S_D = 1130 |
24372 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_S_H = 1131 |
24373 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_S_W = 1132 |
24374 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_U_B = 1133 |
24375 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_U_D = 1134 |
24376 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_U_H = 1135 |
24377 | 0 | CEFBS_HasStdEnc_HasMSA, // CLT_U_W = 1136 |
24378 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // CLZ = 1137 |
24379 | 0 | CEFBS_InMicroMips, // CLZ_MM = 1138 |
24380 | 0 | CEFBS_InMicroMips_HasMips32r6, // CLZ_MMR6 = 1139 |
24381 | 0 | CEFBS_HasStdEnc_HasMips32r6, // CLZ_R6 = 1140 |
24382 | 0 | CEFBS_HasDSPR2, // CMPGDU_EQ_QB = 1141 |
24383 | 0 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_EQ_QB_MMR2 = 1142 |
24384 | 0 | CEFBS_HasDSPR2, // CMPGDU_LE_QB = 1143 |
24385 | 0 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LE_QB_MMR2 = 1144 |
24386 | 0 | CEFBS_HasDSPR2, // CMPGDU_LT_QB = 1145 |
24387 | 0 | CEFBS_InMicroMips_HasDSPR2, // CMPGDU_LT_QB_MMR2 = 1146 |
24388 | 0 | CEFBS_HasDSP, // CMPGU_EQ_QB = 1147 |
24389 | 0 | CEFBS_InMicroMips_HasDSP, // CMPGU_EQ_QB_MM = 1148 |
24390 | 0 | CEFBS_HasDSP, // CMPGU_LE_QB = 1149 |
24391 | 0 | CEFBS_InMicroMips_HasDSP, // CMPGU_LE_QB_MM = 1150 |
24392 | 0 | CEFBS_HasDSP, // CMPGU_LT_QB = 1151 |
24393 | 0 | CEFBS_InMicroMips_HasDSP, // CMPGU_LT_QB_MM = 1152 |
24394 | 0 | CEFBS_HasDSP, // CMPU_EQ_QB = 1153 |
24395 | 0 | CEFBS_InMicroMips_HasDSP, // CMPU_EQ_QB_MM = 1154 |
24396 | 0 | CEFBS_HasDSP, // CMPU_LE_QB = 1155 |
24397 | 0 | CEFBS_InMicroMips_HasDSP, // CMPU_LE_QB_MM = 1156 |
24398 | 0 | CEFBS_HasDSP, // CMPU_LT_QB = 1157 |
24399 | 0 | CEFBS_InMicroMips_HasDSP, // CMPU_LT_QB_MM = 1158 |
24400 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_D_MMR6 = 1159 |
24401 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_AF_S_MMR6 = 1160 |
24402 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_D = 1161 |
24403 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_D_MMR6 = 1162 |
24404 | 0 | CEFBS_HasDSP, // CMP_EQ_PH = 1163 |
24405 | 0 | CEFBS_InMicroMips_HasDSP, // CMP_EQ_PH_MM = 1164 |
24406 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_EQ_S = 1165 |
24407 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_EQ_S_MMR6 = 1166 |
24408 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_D = 1167 |
24409 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_F_S = 1168 |
24410 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_D = 1169 |
24411 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_D_MMR6 = 1170 |
24412 | 0 | CEFBS_HasDSP, // CMP_LE_PH = 1171 |
24413 | 0 | CEFBS_InMicroMips_HasDSP, // CMP_LE_PH_MM = 1172 |
24414 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LE_S = 1173 |
24415 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LE_S_MMR6 = 1174 |
24416 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_D = 1175 |
24417 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_D_MMR6 = 1176 |
24418 | 0 | CEFBS_HasDSP, // CMP_LT_PH = 1177 |
24419 | 0 | CEFBS_InMicroMips_HasDSP, // CMP_LT_PH_MM = 1178 |
24420 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_LT_S = 1179 |
24421 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_LT_S_MMR6 = 1180 |
24422 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_D = 1181 |
24423 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_D_MMR6 = 1182 |
24424 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SAF_S = 1183 |
24425 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SAF_S_MMR6 = 1184 |
24426 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_D = 1185 |
24427 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_D_MMR6 = 1186 |
24428 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SEQ_S = 1187 |
24429 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SEQ_S_MMR6 = 1188 |
24430 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_D = 1189 |
24431 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_D_MMR6 = 1190 |
24432 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLE_S = 1191 |
24433 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLE_S_MMR6 = 1192 |
24434 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_D = 1193 |
24435 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_D_MMR6 = 1194 |
24436 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SLT_S = 1195 |
24437 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SLT_S_MMR6 = 1196 |
24438 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_D = 1197 |
24439 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_D_MMR6 = 1198 |
24440 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUEQ_S = 1199 |
24441 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUEQ_S_MMR6 = 1200 |
24442 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_D = 1201 |
24443 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_D_MMR6 = 1202 |
24444 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULE_S = 1203 |
24445 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULE_S_MMR6 = 1204 |
24446 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_D = 1205 |
24447 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_D_MMR6 = 1206 |
24448 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SULT_S = 1207 |
24449 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SULT_S_MMR6 = 1208 |
24450 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_D = 1209 |
24451 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_D_MMR6 = 1210 |
24452 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_SUN_S = 1211 |
24453 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_SUN_S_MMR6 = 1212 |
24454 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_D = 1213 |
24455 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_D_MMR6 = 1214 |
24456 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UEQ_S = 1215 |
24457 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UEQ_S_MMR6 = 1216 |
24458 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_D = 1217 |
24459 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_D_MMR6 = 1218 |
24460 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULE_S = 1219 |
24461 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULE_S_MMR6 = 1220 |
24462 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_D = 1221 |
24463 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_D_MMR6 = 1222 |
24464 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_ULT_S = 1223 |
24465 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_ULT_S_MMR6 = 1224 |
24466 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_D = 1225 |
24467 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_D_MMR6 = 1226 |
24468 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // CMP_UN_S = 1227 |
24469 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CMP_UN_S_MMR6 = 1228 |
24470 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_S_B = 1229 |
24471 | 0 | CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_S_D = 1230 |
24472 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_S_H = 1231 |
24473 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_S_W = 1232 |
24474 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_U_B = 1233 |
24475 | 0 | CEFBS_HasStdEnc_HasMSA, // COPY_U_H = 1234 |
24476 | 0 | CEFBS_HasStdEnc_HasMSA_HasMips64, // COPY_U_W = 1235 |
24477 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32B = 1236 |
24478 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CB = 1237 |
24479 | 0 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32CD = 1238 |
24480 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CH = 1239 |
24481 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32CW = 1240 |
24482 | 0 | CEFBS_HasStdEnc_HasMips64r6_HasCRC_NotInMicroMips, // CRC32D = 1241 |
24483 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32H = 1242 |
24484 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasCRC_NotInMicroMips, // CRC32W = 1243 |
24485 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CTC1 = 1244 |
24486 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // CTC1_MM = 1245 |
24487 | 0 | CEFBS_InMicroMips, // CTC2_MM = 1246 |
24488 | 0 | CEFBS_HasStdEnc_HasMSA, // CTCMSA = 1247 |
24489 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_S = 1248 |
24490 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_S_MM = 1249 |
24491 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D32_W = 1250 |
24492 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_D32_W_MM = 1251 |
24493 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_D64_L = 1252 |
24494 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_S = 1253 |
24495 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_S_MM = 1254 |
24496 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_D64_W = 1255 |
24497 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_D64_W_MM = 1256 |
24498 | 0 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_D_L_MMR6 = 1257 |
24499 | 0 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_D64 = 1258 |
24500 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_D64_MM = 1259 |
24501 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_D_MMR6 = 1260 |
24502 | 0 | CEFBS_HasStdEnc_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_L_S = 1261 |
24503 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_L_S_MM = 1262 |
24504 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_L_S_MMR6 = 1263 |
24505 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PS_PW64 = 1264 |
24506 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_PS_S64 = 1265 |
24507 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // CVT_PW_PS64 = 1266 |
24508 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D32 = 1267 |
24509 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_S_D32_MM = 1268 |
24510 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_S_D64 = 1269 |
24511 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_S_D64_MM = 1270 |
24512 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32r2_IsNotSoftFloat_NotInMicroMips, // CVT_S_L = 1271 |
24513 | 0 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // CVT_S_L_MMR6 = 1272 |
24514 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PL64 = 1273 |
24515 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // CVT_S_PU64 = 1274 |
24516 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_S_W = 1275 |
24517 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // CVT_S_W_MM = 1276 |
24518 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_S_W_MMR6 = 1277 |
24519 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D32 = 1278 |
24520 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // CVT_W_D32_MM = 1279 |
24521 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // CVT_W_D64 = 1280 |
24522 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // CVT_W_D64_MM = 1281 |
24523 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // CVT_W_S = 1282 |
24524 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // CVT_W_S_MM = 1283 |
24525 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // CVT_W_S_MMR6 = 1284 |
24526 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D32 = 1285 |
24527 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D32_MM = 1286 |
24528 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_D64 = 1287 |
24529 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_EQ_D64_MM = 1288 |
24530 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_EQ_S = 1289 |
24531 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_EQ_S_MM = 1290 |
24532 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D32 = 1291 |
24533 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D32_MM = 1292 |
24534 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_D64 = 1293 |
24535 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_F_D64_MM = 1294 |
24536 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_F_S = 1295 |
24537 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_F_S_MM = 1296 |
24538 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D32 = 1297 |
24539 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D32_MM = 1298 |
24540 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_D64 = 1299 |
24541 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LE_D64_MM = 1300 |
24542 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LE_S = 1301 |
24543 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LE_S_MM = 1302 |
24544 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D32 = 1303 |
24545 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D32_MM = 1304 |
24546 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_D64 = 1305 |
24547 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_LT_D64_MM = 1306 |
24548 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_LT_S = 1307 |
24549 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_LT_S_MM = 1308 |
24550 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D32 = 1309 |
24551 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D32_MM = 1310 |
24552 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_D64 = 1311 |
24553 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGE_D64_MM = 1312 |
24554 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGE_S = 1313 |
24555 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGE_S_MM = 1314 |
24556 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D32 = 1315 |
24557 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D32_MM = 1316 |
24558 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_D64 = 1317 |
24559 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGLE_D64_MM = 1318 |
24560 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGLE_S = 1319 |
24561 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGLE_S_MM = 1320 |
24562 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D32 = 1321 |
24563 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D32_MM = 1322 |
24564 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_D64 = 1323 |
24565 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGL_D64_MM = 1324 |
24566 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGL_S = 1325 |
24567 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGL_S_MM = 1326 |
24568 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D32 = 1327 |
24569 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D32_MM = 1328 |
24570 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_D64 = 1329 |
24571 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_NGT_D64_MM = 1330 |
24572 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_NGT_S = 1331 |
24573 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_NGT_S_MM = 1332 |
24574 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D32 = 1333 |
24575 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D32_MM = 1334 |
24576 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_D64 = 1335 |
24577 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLE_D64_MM = 1336 |
24578 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLE_S = 1337 |
24579 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLE_S_MM = 1338 |
24580 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D32 = 1339 |
24581 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D32_MM = 1340 |
24582 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_D64 = 1341 |
24583 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_OLT_D64_MM = 1342 |
24584 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_OLT_S = 1343 |
24585 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_OLT_S_MM = 1344 |
24586 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D32 = 1345 |
24587 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D32_MM = 1346 |
24588 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_D64 = 1347 |
24589 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SEQ_D64_MM = 1348 |
24590 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SEQ_S = 1349 |
24591 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SEQ_S_MM = 1350 |
24592 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D32 = 1351 |
24593 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D32_MM = 1352 |
24594 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_D64 = 1353 |
24595 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_SF_D64_MM = 1354 |
24596 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_SF_S = 1355 |
24597 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_SF_S_MM = 1356 |
24598 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D32 = 1357 |
24599 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D32_MM = 1358 |
24600 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_D64 = 1359 |
24601 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UEQ_D64_MM = 1360 |
24602 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UEQ_S = 1361 |
24603 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UEQ_S_MM = 1362 |
24604 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D32 = 1363 |
24605 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D32_MM = 1364 |
24606 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_D64 = 1365 |
24607 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULE_D64_MM = 1366 |
24608 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULE_S = 1367 |
24609 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULE_S_MM = 1368 |
24610 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D32 = 1369 |
24611 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D32_MM = 1370 |
24612 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_D64 = 1371 |
24613 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_ULT_D64_MM = 1372 |
24614 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_ULT_S = 1373 |
24615 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_ULT_S_MM = 1374 |
24616 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D32 = 1375 |
24617 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D32_MM = 1376 |
24618 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_D64 = 1377 |
24619 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // C_UN_D64_MM = 1378 |
24620 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // C_UN_S = 1379 |
24621 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // C_UN_S_MM = 1380 |
24622 | 0 | CEFBS_InMips16Mode, // CmpRxRy16 = 1381 |
24623 | 0 | CEFBS_InMips16Mode, // CmpiRxImm16 = 1382 |
24624 | 0 | CEFBS_InMips16Mode, // CmpiRxImmX16 = 1383 |
24625 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADD = 1384 |
24626 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // DADDi = 1385 |
24627 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDiu = 1386 |
24628 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DADDu = 1387 |
24629 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAHI = 1388 |
24630 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DALIGN = 1389 |
24631 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DATI = 1390 |
24632 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DAUI = 1391 |
24633 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DBITSWAP = 1392 |
24634 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLO = 1393 |
24635 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLO_R6 = 1394 |
24636 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64_NotMips64r6_NotInMicroMips, // DCLZ = 1395 |
24637 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DCLZ_R6 = 1396 |
24638 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIV = 1397 |
24639 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DDIVU = 1398 |
24640 | 0 | CEFBS_HasStdEnc_HasMips32_NotInMicroMips, // DERET = 1399 |
24641 | 0 | CEFBS_InMicroMips, // DERET_MM = 1400 |
24642 | 0 | CEFBS_InMicroMips_HasMips32r6, // DERET_MMR6 = 1401 |
24643 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT = 1402 |
24644 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXT64_32 = 1403 |
24645 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTM = 1404 |
24646 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DEXTU = 1405 |
24647 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // DI = 1406 |
24648 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINS = 1407 |
24649 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSM = 1408 |
24650 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DINSU = 1409 |
24651 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIV = 1410 |
24652 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // DIVU = 1411 |
24653 | 0 | CEFBS_InMicroMips_HasMips32r6, // DIVU_MMR6 = 1412 |
24654 | 0 | CEFBS_InMicroMips_HasMips32r6, // DIV_MMR6 = 1413 |
24655 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_S_B = 1414 |
24656 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_S_D = 1415 |
24657 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_S_H = 1416 |
24658 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_S_W = 1417 |
24659 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_U_B = 1418 |
24660 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_U_D = 1419 |
24661 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_U_H = 1420 |
24662 | 0 | CEFBS_HasStdEnc_HasMSA, // DIV_U_W = 1421 |
24663 | 0 | CEFBS_InMicroMips, // DI_MM = 1422 |
24664 | 0 | CEFBS_InMicroMips_HasMips32r6, // DI_MMR6 = 1423 |
24665 | 0 | CEFBS_HasStdEnc_HasMSA_HasMips64, // DLSA = 1424 |
24666 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DLSA_R6 = 1425 |
24667 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC0 = 1426 |
24668 | 0 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMFC1 = 1427 |
24669 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMFC2 = 1428 |
24670 | 0 | CEFBS_HasCnMips, // DMFC2_OCTEON = 1429 |
24671 | 0 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMFGC0 = 1430 |
24672 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMOD = 1431 |
24673 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMODU = 1432 |
24674 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DMT = 1433 |
24675 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC0 = 1434 |
24676 | 0 | CEFBS_HasStdEnc_HasMips3_IsNotSoftFloat_NotInMicroMips, // DMTC1 = 1435 |
24677 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips3, // DMTC2 = 1436 |
24678 | 0 | CEFBS_HasCnMips, // DMTC2_OCTEON = 1437 |
24679 | 0 | CEFBS_HasStdEnc_HasMips64r5_HasVirt, // DMTGC0 = 1438 |
24680 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUH = 1439 |
24681 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUHU = 1440 |
24682 | 0 | CEFBS_HasCnMips, // DMUL = 1441 |
24683 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULT = 1442 |
24684 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DMULTu = 1443 |
24685 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMULU = 1444 |
24686 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // DMUL_R6 = 1445 |
24687 | 0 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_D = 1446 |
24688 | 0 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_H = 1447 |
24689 | 0 | CEFBS_HasStdEnc_HasMSA, // DOTP_S_W = 1448 |
24690 | 0 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_D = 1449 |
24691 | 0 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_H = 1450 |
24692 | 0 | CEFBS_HasStdEnc_HasMSA, // DOTP_U_W = 1451 |
24693 | 0 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_D = 1452 |
24694 | 0 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_H = 1453 |
24695 | 0 | CEFBS_HasStdEnc_HasMSA, // DPADD_S_W = 1454 |
24696 | 0 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_D = 1455 |
24697 | 0 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_H = 1456 |
24698 | 0 | CEFBS_HasStdEnc_HasMSA, // DPADD_U_W = 1457 |
24699 | 0 | CEFBS_HasDSPR2, // DPAQX_SA_W_PH = 1458 |
24700 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPAQX_SA_W_PH_MMR2 = 1459 |
24701 | 0 | CEFBS_HasDSPR2, // DPAQX_S_W_PH = 1460 |
24702 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPAQX_S_W_PH_MMR2 = 1461 |
24703 | 0 | CEFBS_HasDSP, // DPAQ_SA_L_W = 1462 |
24704 | 0 | CEFBS_InMicroMips_HasDSP, // DPAQ_SA_L_W_MM = 1463 |
24705 | 0 | CEFBS_HasDSP, // DPAQ_S_W_PH = 1464 |
24706 | 0 | CEFBS_InMicroMips_HasDSP, // DPAQ_S_W_PH_MM = 1465 |
24707 | 0 | CEFBS_HasDSP, // DPAU_H_QBL = 1466 |
24708 | 0 | CEFBS_InMicroMips_HasDSP, // DPAU_H_QBL_MM = 1467 |
24709 | 0 | CEFBS_HasDSP, // DPAU_H_QBR = 1468 |
24710 | 0 | CEFBS_InMicroMips_HasDSP, // DPAU_H_QBR_MM = 1469 |
24711 | 0 | CEFBS_HasDSPR2, // DPAX_W_PH = 1470 |
24712 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPAX_W_PH_MMR2 = 1471 |
24713 | 0 | CEFBS_HasDSPR2, // DPA_W_PH = 1472 |
24714 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPA_W_PH_MMR2 = 1473 |
24715 | 0 | CEFBS_HasCnMips, // DPOP = 1474 |
24716 | 0 | CEFBS_HasDSPR2, // DPSQX_SA_W_PH = 1475 |
24717 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPSQX_SA_W_PH_MMR2 = 1476 |
24718 | 0 | CEFBS_HasDSPR2, // DPSQX_S_W_PH = 1477 |
24719 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPSQX_S_W_PH_MMR2 = 1478 |
24720 | 0 | CEFBS_HasDSP, // DPSQ_SA_L_W = 1479 |
24721 | 0 | CEFBS_InMicroMips_HasDSP, // DPSQ_SA_L_W_MM = 1480 |
24722 | 0 | CEFBS_HasDSP, // DPSQ_S_W_PH = 1481 |
24723 | 0 | CEFBS_InMicroMips_HasDSP, // DPSQ_S_W_PH_MM = 1482 |
24724 | 0 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_D = 1483 |
24725 | 0 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_H = 1484 |
24726 | 0 | CEFBS_HasStdEnc_HasMSA, // DPSUB_S_W = 1485 |
24727 | 0 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_D = 1486 |
24728 | 0 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_H = 1487 |
24729 | 0 | CEFBS_HasStdEnc_HasMSA, // DPSUB_U_W = 1488 |
24730 | 0 | CEFBS_HasDSP, // DPSU_H_QBL = 1489 |
24731 | 0 | CEFBS_InMicroMips_HasDSP, // DPSU_H_QBL_MM = 1490 |
24732 | 0 | CEFBS_HasDSP, // DPSU_H_QBR = 1491 |
24733 | 0 | CEFBS_InMicroMips_HasDSP, // DPSU_H_QBR_MM = 1492 |
24734 | 0 | CEFBS_HasDSPR2, // DPSX_W_PH = 1493 |
24735 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPSX_W_PH_MMR2 = 1494 |
24736 | 0 | CEFBS_HasDSPR2, // DPS_W_PH = 1495 |
24737 | 0 | CEFBS_InMicroMips_HasDSPR2, // DPS_W_PH_MMR2 = 1496 |
24738 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR = 1497 |
24739 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTR32 = 1498 |
24740 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DROTRV = 1499 |
24741 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSBH = 1500 |
24742 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DSDIV = 1501 |
24743 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // DSHD = 1502 |
24744 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL = 1503 |
24745 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLL32 = 1504 |
24746 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // DSLL64_32 = 1505 |
24747 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSLLV = 1506 |
24748 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA = 1507 |
24749 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRA32 = 1508 |
24750 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRAV = 1509 |
24751 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL = 1510 |
24752 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRL32 = 1511 |
24753 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSRLV = 1512 |
24754 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUB = 1513 |
24755 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // DSUBu = 1514 |
24756 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // DUDIV = 1515 |
24757 | 0 | CEFBS_HasStdEnc_HasMips32r6, // DVP = 1516 |
24758 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // DVPE = 1517 |
24759 | 0 | CEFBS_InMicroMips_HasMips32r6, // DVP_MMR6 = 1518 |
24760 | 0 | CEFBS_InMips16Mode, // DivRxRy16 = 1519 |
24761 | 0 | CEFBS_InMips16Mode, // DivuRxRy16 = 1520 |
24762 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // EHB = 1521 |
24763 | 0 | CEFBS_InMicroMips, // EHB_MM = 1522 |
24764 | 0 | CEFBS_InMicroMips_HasMips32r6, // EHB_MMR6 = 1523 |
24765 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EI = 1524 |
24766 | 0 | CEFBS_InMicroMips, // EI_MM = 1525 |
24767 | 0 | CEFBS_InMicroMips_HasMips32r6, // EI_MMR6 = 1526 |
24768 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EMT = 1527 |
24769 | 0 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // ERET = 1528 |
24770 | 0 | CEFBS_HasStdEnc_HasMips32r5_NotInMicroMips, // ERETNC = 1529 |
24771 | 0 | CEFBS_InMicroMips_HasMips32r6, // ERETNC_MMR6 = 1530 |
24772 | 0 | CEFBS_InMicroMips, // ERET_MM = 1531 |
24773 | 0 | CEFBS_InMicroMips_HasMips32r6, // ERET_MMR6 = 1532 |
24774 | 0 | CEFBS_HasStdEnc_HasMips32r6, // EVP = 1533 |
24775 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // EVPE = 1534 |
24776 | 0 | CEFBS_InMicroMips_HasMips32r6, // EVP_MMR6 = 1535 |
24777 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // EXT = 1536 |
24778 | 0 | CEFBS_HasDSP, // EXTP = 1537 |
24779 | 0 | CEFBS_HasDSP, // EXTPDP = 1538 |
24780 | 0 | CEFBS_HasDSP, // EXTPDPV = 1539 |
24781 | 0 | CEFBS_InMicroMips_HasDSP, // EXTPDPV_MM = 1540 |
24782 | 0 | CEFBS_InMicroMips_HasDSP, // EXTPDP_MM = 1541 |
24783 | 0 | CEFBS_HasDSP, // EXTPV = 1542 |
24784 | 0 | CEFBS_InMicroMips_HasDSP, // EXTPV_MM = 1543 |
24785 | 0 | CEFBS_InMicroMips_HasDSP, // EXTP_MM = 1544 |
24786 | 0 | CEFBS_HasDSP, // EXTRV_RS_W = 1545 |
24787 | 0 | CEFBS_InMicroMips_HasDSP, // EXTRV_RS_W_MM = 1546 |
24788 | 0 | CEFBS_HasDSP, // EXTRV_R_W = 1547 |
24789 | 0 | CEFBS_InMicroMips_HasDSP, // EXTRV_R_W_MM = 1548 |
24790 | 0 | CEFBS_HasDSP, // EXTRV_S_H = 1549 |
24791 | 0 | CEFBS_InMicroMips_HasDSP, // EXTRV_S_H_MM = 1550 |
24792 | 0 | CEFBS_HasDSP, // EXTRV_W = 1551 |
24793 | 0 | CEFBS_InMicroMips_HasDSP, // EXTRV_W_MM = 1552 |
24794 | 0 | CEFBS_HasDSP, // EXTR_RS_W = 1553 |
24795 | 0 | CEFBS_InMicroMips_HasDSP, // EXTR_RS_W_MM = 1554 |
24796 | 0 | CEFBS_HasDSP, // EXTR_R_W = 1555 |
24797 | 0 | CEFBS_InMicroMips_HasDSP, // EXTR_R_W_MM = 1556 |
24798 | 0 | CEFBS_HasDSP, // EXTR_S_H = 1557 |
24799 | 0 | CEFBS_InMicroMips_HasDSP, // EXTR_S_H_MM = 1558 |
24800 | 0 | CEFBS_HasDSP, // EXTR_W = 1559 |
24801 | 0 | CEFBS_InMicroMips_HasDSP, // EXTR_W_MM = 1560 |
24802 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS = 1561 |
24803 | 0 | CEFBS_HasMips64_HasCnMips_NotInMicroMips, // EXTS32 = 1562 |
24804 | 0 | CEFBS_InMicroMips_NotMips32r6, // EXT_MM = 1563 |
24805 | 0 | CEFBS_InMicroMips_HasMips32r6, // EXT_MMR6 = 1564 |
24806 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D32 = 1565 |
24807 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FABS_D32_MM = 1566 |
24808 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FABS_D64 = 1567 |
24809 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FABS_D64_MM = 1568 |
24810 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FABS_S = 1569 |
24811 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FABS_S_MM = 1570 |
24812 | 0 | CEFBS_HasStdEnc_HasMSA, // FADD_D = 1571 |
24813 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D32 = 1572 |
24814 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FADD_D32_MM = 1573 |
24815 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FADD_D64 = 1574 |
24816 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FADD_D64_MM = 1575 |
24817 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FADD_PS64 = 1576 |
24818 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FADD_S = 1577 |
24819 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FADD_S_MM = 1578 |
24820 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FADD_S_MMR6 = 1579 |
24821 | 0 | CEFBS_HasStdEnc_HasMSA, // FADD_W = 1580 |
24822 | 0 | CEFBS_HasStdEnc_HasMSA, // FCAF_D = 1581 |
24823 | 0 | CEFBS_HasStdEnc_HasMSA, // FCAF_W = 1582 |
24824 | 0 | CEFBS_HasStdEnc_HasMSA, // FCEQ_D = 1583 |
24825 | 0 | CEFBS_HasStdEnc_HasMSA, // FCEQ_W = 1584 |
24826 | 0 | CEFBS_HasStdEnc_HasMSA, // FCLASS_D = 1585 |
24827 | 0 | CEFBS_HasStdEnc_HasMSA, // FCLASS_W = 1586 |
24828 | 0 | CEFBS_HasStdEnc_HasMSA, // FCLE_D = 1587 |
24829 | 0 | CEFBS_HasStdEnc_HasMSA, // FCLE_W = 1588 |
24830 | 0 | CEFBS_HasStdEnc_HasMSA, // FCLT_D = 1589 |
24831 | 0 | CEFBS_HasStdEnc_HasMSA, // FCLT_W = 1590 |
24832 | 0 | CEFBS_HasStdEnc_NotFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_D32 = 1591 |
24833 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_D32_MM = 1592 |
24834 | 0 | CEFBS_HasStdEnc_IsFP64bit_NotMips32r6_NotMips64r6_IsNotSoftFloat, // FCMP_D64 = 1593 |
24835 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FCMP_S32 = 1594 |
24836 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // FCMP_S32_MM = 1595 |
24837 | 0 | CEFBS_HasStdEnc_HasMSA, // FCNE_D = 1596 |
24838 | 0 | CEFBS_HasStdEnc_HasMSA, // FCNE_W = 1597 |
24839 | 0 | CEFBS_HasStdEnc_HasMSA, // FCOR_D = 1598 |
24840 | 0 | CEFBS_HasStdEnc_HasMSA, // FCOR_W = 1599 |
24841 | 0 | CEFBS_HasStdEnc_HasMSA, // FCUEQ_D = 1600 |
24842 | 0 | CEFBS_HasStdEnc_HasMSA, // FCUEQ_W = 1601 |
24843 | 0 | CEFBS_HasStdEnc_HasMSA, // FCULE_D = 1602 |
24844 | 0 | CEFBS_HasStdEnc_HasMSA, // FCULE_W = 1603 |
24845 | 0 | CEFBS_HasStdEnc_HasMSA, // FCULT_D = 1604 |
24846 | 0 | CEFBS_HasStdEnc_HasMSA, // FCULT_W = 1605 |
24847 | 0 | CEFBS_HasStdEnc_HasMSA, // FCUNE_D = 1606 |
24848 | 0 | CEFBS_HasStdEnc_HasMSA, // FCUNE_W = 1607 |
24849 | 0 | CEFBS_HasStdEnc_HasMSA, // FCUN_D = 1608 |
24850 | 0 | CEFBS_HasStdEnc_HasMSA, // FCUN_W = 1609 |
24851 | 0 | CEFBS_HasStdEnc_HasMSA, // FDIV_D = 1610 |
24852 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D32 = 1611 |
24853 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FDIV_D32_MM = 1612 |
24854 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FDIV_D64 = 1613 |
24855 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FDIV_D64_MM = 1614 |
24856 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FDIV_S = 1615 |
24857 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FDIV_S_MM = 1616 |
24858 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FDIV_S_MMR6 = 1617 |
24859 | 0 | CEFBS_HasStdEnc_HasMSA, // FDIV_W = 1618 |
24860 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXDO_H = 1619 |
24861 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXDO_W = 1620 |
24862 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXP2_D = 1621 |
24863 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXP2_W = 1622 |
24864 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXUPL_D = 1623 |
24865 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXUPL_W = 1624 |
24866 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXUPR_D = 1625 |
24867 | 0 | CEFBS_HasStdEnc_HasMSA, // FEXUPR_W = 1626 |
24868 | 0 | CEFBS_HasStdEnc_HasMSA, // FFINT_S_D = 1627 |
24869 | 0 | CEFBS_HasStdEnc_HasMSA, // FFINT_S_W = 1628 |
24870 | 0 | CEFBS_HasStdEnc_HasMSA, // FFINT_U_D = 1629 |
24871 | 0 | CEFBS_HasStdEnc_HasMSA, // FFINT_U_W = 1630 |
24872 | 0 | CEFBS_HasStdEnc_HasMSA, // FFQL_D = 1631 |
24873 | 0 | CEFBS_HasStdEnc_HasMSA, // FFQL_W = 1632 |
24874 | 0 | CEFBS_HasStdEnc_HasMSA, // FFQR_D = 1633 |
24875 | 0 | CEFBS_HasStdEnc_HasMSA, // FFQR_W = 1634 |
24876 | 0 | CEFBS_HasStdEnc_HasMSA, // FILL_B = 1635 |
24877 | 0 | CEFBS_HasStdEnc_HasMSA_HasMips64, // FILL_D = 1636 |
24878 | 0 | CEFBS_HasStdEnc_HasMSA, // FILL_H = 1637 |
24879 | 0 | CEFBS_HasStdEnc_HasMSA, // FILL_W = 1638 |
24880 | 0 | CEFBS_HasStdEnc_HasMSA, // FLOG2_D = 1639 |
24881 | 0 | CEFBS_HasStdEnc_HasMSA, // FLOG2_W = 1640 |
24882 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_D64 = 1641 |
24883 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_D_MMR6 = 1642 |
24884 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_L_S = 1643 |
24885 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_L_S_MMR6 = 1644 |
24886 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D32 = 1645 |
24887 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_D64 = 1646 |
24888 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_D_MMR6 = 1647 |
24889 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FLOOR_W_MM = 1648 |
24890 | 0 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FLOOR_W_S = 1649 |
24891 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FLOOR_W_S_MM = 1650 |
24892 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FLOOR_W_S_MMR6 = 1651 |
24893 | 0 | CEFBS_HasStdEnc_HasMSA, // FMADD_D = 1652 |
24894 | 0 | CEFBS_HasStdEnc_HasMSA, // FMADD_W = 1653 |
24895 | 0 | CEFBS_HasStdEnc_HasMSA, // FMAX_A_D = 1654 |
24896 | 0 | CEFBS_HasStdEnc_HasMSA, // FMAX_A_W = 1655 |
24897 | 0 | CEFBS_HasStdEnc_HasMSA, // FMAX_D = 1656 |
24898 | 0 | CEFBS_HasStdEnc_HasMSA, // FMAX_W = 1657 |
24899 | 0 | CEFBS_HasStdEnc_HasMSA, // FMIN_A_D = 1658 |
24900 | 0 | CEFBS_HasStdEnc_HasMSA, // FMIN_A_W = 1659 |
24901 | 0 | CEFBS_HasStdEnc_HasMSA, // FMIN_D = 1660 |
24902 | 0 | CEFBS_HasStdEnc_HasMSA, // FMIN_W = 1661 |
24903 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D32 = 1662 |
24904 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMOV_D32_MM = 1663 |
24905 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMOV_D64 = 1664 |
24906 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMOV_D64_MM = 1665 |
24907 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_D_MMR6 = 1666 |
24908 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMOV_S = 1667 |
24909 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FMOV_S_MM = 1668 |
24910 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMOV_S_MMR6 = 1669 |
24911 | 0 | CEFBS_HasStdEnc_HasMSA, // FMSUB_D = 1670 |
24912 | 0 | CEFBS_HasStdEnc_HasMSA, // FMSUB_W = 1671 |
24913 | 0 | CEFBS_HasStdEnc_HasMSA, // FMUL_D = 1672 |
24914 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D32 = 1673 |
24915 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FMUL_D32_MM = 1674 |
24916 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FMUL_D64 = 1675 |
24917 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FMUL_D64_MM = 1676 |
24918 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FMUL_PS64 = 1677 |
24919 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FMUL_S = 1678 |
24920 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FMUL_S_MM = 1679 |
24921 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FMUL_S_MMR6 = 1680 |
24922 | 0 | CEFBS_HasStdEnc_HasMSA, // FMUL_W = 1681 |
24923 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D32 = 1682 |
24924 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FNEG_D32_MM = 1683 |
24925 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FNEG_D64 = 1684 |
24926 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FNEG_D64_MM = 1685 |
24927 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat, // FNEG_S = 1686 |
24928 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FNEG_S_MM = 1687 |
24929 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FNEG_S_MMR6 = 1688 |
24930 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // FORK = 1689 |
24931 | 0 | CEFBS_HasStdEnc_HasMSA, // FRCP_D = 1690 |
24932 | 0 | CEFBS_HasStdEnc_HasMSA, // FRCP_W = 1691 |
24933 | 0 | CEFBS_HasStdEnc_HasMSA, // FRINT_D = 1692 |
24934 | 0 | CEFBS_HasStdEnc_HasMSA, // FRINT_W = 1693 |
24935 | 0 | CEFBS_HasStdEnc_HasMSA, // FRSQRT_D = 1694 |
24936 | 0 | CEFBS_HasStdEnc_HasMSA, // FRSQRT_W = 1695 |
24937 | 0 | CEFBS_HasStdEnc_HasMSA, // FSAF_D = 1696 |
24938 | 0 | CEFBS_HasStdEnc_HasMSA, // FSAF_W = 1697 |
24939 | 0 | CEFBS_HasStdEnc_HasMSA, // FSEQ_D = 1698 |
24940 | 0 | CEFBS_HasStdEnc_HasMSA, // FSEQ_W = 1699 |
24941 | 0 | CEFBS_HasStdEnc_HasMSA, // FSLE_D = 1700 |
24942 | 0 | CEFBS_HasStdEnc_HasMSA, // FSLE_W = 1701 |
24943 | 0 | CEFBS_HasStdEnc_HasMSA, // FSLT_D = 1702 |
24944 | 0 | CEFBS_HasStdEnc_HasMSA, // FSLT_W = 1703 |
24945 | 0 | CEFBS_HasStdEnc_HasMSA, // FSNE_D = 1704 |
24946 | 0 | CEFBS_HasStdEnc_HasMSA, // FSNE_W = 1705 |
24947 | 0 | CEFBS_HasStdEnc_HasMSA, // FSOR_D = 1706 |
24948 | 0 | CEFBS_HasStdEnc_HasMSA, // FSOR_W = 1707 |
24949 | 0 | CEFBS_HasStdEnc_HasMSA, // FSQRT_D = 1708 |
24950 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D32 = 1709 |
24951 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSQRT_D32_MM = 1710 |
24952 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_D64 = 1711 |
24953 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSQRT_D64_MM = 1712 |
24954 | 0 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // FSQRT_S = 1713 |
24955 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FSQRT_S_MM = 1714 |
24956 | 0 | CEFBS_HasStdEnc_HasMSA, // FSQRT_W = 1715 |
24957 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUB_D = 1716 |
24958 | 0 | CEFBS_HasStdEnc_NotFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D32 = 1717 |
24959 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // FSUB_D32_MM = 1718 |
24960 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // FSUB_D64 = 1719 |
24961 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // FSUB_D64_MM = 1720 |
24962 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // FSUB_PS64 = 1721 |
24963 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // FSUB_S = 1722 |
24964 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // FSUB_S_MM = 1723 |
24965 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // FSUB_S_MMR6 = 1724 |
24966 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUB_W = 1725 |
24967 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUEQ_D = 1726 |
24968 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUEQ_W = 1727 |
24969 | 0 | CEFBS_HasStdEnc_HasMSA, // FSULE_D = 1728 |
24970 | 0 | CEFBS_HasStdEnc_HasMSA, // FSULE_W = 1729 |
24971 | 0 | CEFBS_HasStdEnc_HasMSA, // FSULT_D = 1730 |
24972 | 0 | CEFBS_HasStdEnc_HasMSA, // FSULT_W = 1731 |
24973 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUNE_D = 1732 |
24974 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUNE_W = 1733 |
24975 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUN_D = 1734 |
24976 | 0 | CEFBS_HasStdEnc_HasMSA, // FSUN_W = 1735 |
24977 | 0 | CEFBS_HasStdEnc_HasMSA, // FTINT_S_D = 1736 |
24978 | 0 | CEFBS_HasStdEnc_HasMSA, // FTINT_S_W = 1737 |
24979 | 0 | CEFBS_HasStdEnc_HasMSA, // FTINT_U_D = 1738 |
24980 | 0 | CEFBS_HasStdEnc_HasMSA, // FTINT_U_W = 1739 |
24981 | 0 | CEFBS_HasStdEnc_HasMSA, // FTQ_H = 1740 |
24982 | 0 | CEFBS_HasStdEnc_HasMSA, // FTQ_W = 1741 |
24983 | 0 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_D = 1742 |
24984 | 0 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_S_W = 1743 |
24985 | 0 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_D = 1744 |
24986 | 0 | CEFBS_HasStdEnc_HasMSA, // FTRUNC_U_W = 1745 |
24987 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVI = 1746 |
24988 | 0 | CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVI_MMR6 = 1747 |
24989 | 0 | CEFBS_HasStdEnc_HasMips32r6_HasGINV_NotInMicroMips, // GINVT = 1748 |
24990 | 0 | CEFBS_InMicroMips_HasMips32r6_HasGINV, // GINVT_MMR6 = 1749 |
24991 | 0 | CEFBS_HasStdEnc_HasMSA, // HADD_S_D = 1750 |
24992 | 0 | CEFBS_HasStdEnc_HasMSA, // HADD_S_H = 1751 |
24993 | 0 | CEFBS_HasStdEnc_HasMSA, // HADD_S_W = 1752 |
24994 | 0 | CEFBS_HasStdEnc_HasMSA, // HADD_U_D = 1753 |
24995 | 0 | CEFBS_HasStdEnc_HasMSA, // HADD_U_H = 1754 |
24996 | 0 | CEFBS_HasStdEnc_HasMSA, // HADD_U_W = 1755 |
24997 | 0 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_D = 1756 |
24998 | 0 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_H = 1757 |
24999 | 0 | CEFBS_HasStdEnc_HasMSA, // HSUB_S_W = 1758 |
25000 | 0 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_D = 1759 |
25001 | 0 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_H = 1760 |
25002 | 0 | CEFBS_HasStdEnc_HasMSA, // HSUB_U_W = 1761 |
25003 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // HYPCALL = 1762 |
25004 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // HYPCALL_MM = 1763 |
25005 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVEV_B = 1764 |
25006 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVEV_D = 1765 |
25007 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVEV_H = 1766 |
25008 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVEV_W = 1767 |
25009 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVL_B = 1768 |
25010 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVL_D = 1769 |
25011 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVL_H = 1770 |
25012 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVL_W = 1771 |
25013 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVOD_B = 1772 |
25014 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVOD_D = 1773 |
25015 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVOD_H = 1774 |
25016 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVOD_W = 1775 |
25017 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVR_B = 1776 |
25018 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVR_D = 1777 |
25019 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVR_H = 1778 |
25020 | 0 | CEFBS_HasStdEnc_HasMSA, // ILVR_W = 1779 |
25021 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // INS = 1780 |
25022 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_B = 1781 |
25023 | 0 | CEFBS_HasStdEnc_HasMSA_HasMips64, // INSERT_D = 1782 |
25024 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_H = 1783 |
25025 | 0 | CEFBS_HasStdEnc_HasMSA, // INSERT_W = 1784 |
25026 | 0 | CEFBS_HasDSP, // INSV = 1785 |
25027 | 0 | CEFBS_HasStdEnc_HasMSA, // INSVE_B = 1786 |
25028 | 0 | CEFBS_HasStdEnc_HasMSA, // INSVE_D = 1787 |
25029 | 0 | CEFBS_HasStdEnc_HasMSA, // INSVE_H = 1788 |
25030 | 0 | CEFBS_HasStdEnc_HasMSA, // INSVE_W = 1789 |
25031 | 0 | CEFBS_InMicroMips_HasDSP, // INSV_MM = 1790 |
25032 | 0 | CEFBS_InMicroMips_NotMips32r6, // INS_MM = 1791 |
25033 | 0 | CEFBS_InMicroMips_HasMips32r6, // INS_MMR6 = 1792 |
25034 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // J = 1793 |
25035 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // JAL = 1794 |
25036 | 0 | CEFBS_HasStdEnc_NotInMicroMips_NoIndirectJumpGuards, // JALR = 1795 |
25037 | 0 | CEFBS_InMicroMips_NotMips32r6, // JALR16_MM = 1796 |
25038 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit, // JALR64 = 1797 |
25039 | 0 | CEFBS_InMicroMips_HasMips32r6, // JALRC16_MMR6 = 1798 |
25040 | 0 | CEFBS_InMicroMips_HasMips32r6, // JALRC_HB_MMR6 = 1799 |
25041 | 0 | CEFBS_InMicroMips_HasMips32r6, // JALRC_MMR6 = 1800 |
25042 | 0 | CEFBS_InMicroMips_NotMips32r6, // JALRS16_MM = 1801 |
25043 | 0 | CEFBS_InMicroMips_NotMips32r6, // JALRS_MM = 1802 |
25044 | 0 | CEFBS_HasStdEnc_HasMips32, // JALR_HB = 1803 |
25045 | 0 | CEFBS_HasStdEnc_HasMips64r2_NotInMicroMips, // JALR_HB64 = 1804 |
25046 | 0 | CEFBS_InMicroMips_NotMips32r6, // JALR_MM = 1805 |
25047 | 0 | CEFBS_InMicroMips_NotMips32r6, // JALS_MM = 1806 |
25048 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // JALX = 1807 |
25049 | 0 | CEFBS_InMicroMips_NotMips32r6, // JALX_MM = 1808 |
25050 | 0 | CEFBS_InMicroMips_NotMips32r6, // JAL_MM = 1809 |
25051 | 0 | CEFBS_HasStdEnc_HasMips32r6, // JIALC = 1810 |
25052 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIALC64 = 1811 |
25053 | 0 | CEFBS_InMicroMips_HasMips32r6, // JIALC_MMR6 = 1812 |
25054 | 0 | CEFBS_HasStdEnc_HasMips32r6, // JIC = 1813 |
25055 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips64r6, // JIC64 = 1814 |
25056 | 0 | CEFBS_InMicroMips_HasMips32r6, // JIC_MMR6 = 1815 |
25057 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // JR = 1816 |
25058 | 0 | CEFBS_InMicroMips_NotMips32r6, // JR16_MM = 1817 |
25059 | 0 | CEFBS_NotInMips16Mode_IsPTR64bit_NotInMicroMips, // JR64 = 1818 |
25060 | 0 | CEFBS_InMicroMips_NotMips32r6, // JRADDIUSP = 1819 |
25061 | 0 | CEFBS_InMicroMips_NotMips32r6, // JRC16_MM = 1820 |
25062 | 0 | CEFBS_InMicroMips_HasMips32r6, // JRC16_MMR6 = 1821 |
25063 | 0 | CEFBS_InMicroMips_HasMips32r6, // JRCADDIUSP_MMR6 = 1822 |
25064 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6, // JR_HB = 1823 |
25065 | 0 | CEFBS_HasStdEnc_HasMips64_NotMips64r6_NotInMicroMips, // JR_HB64 = 1824 |
25066 | 0 | CEFBS_HasStdEnc_HasMips32r6, // JR_HB64_R6 = 1825 |
25067 | 0 | CEFBS_HasStdEnc_HasMips32r6, // JR_HB_R6 = 1826 |
25068 | 0 | CEFBS_InMicroMips_NotMips32r6, // JR_MM = 1827 |
25069 | 0 | CEFBS_InMicroMips_NotMips32r6, // J_MM = 1828 |
25070 | 0 | CEFBS_InMips16Mode, // Jal16 = 1829 |
25071 | 0 | CEFBS_InMips16Mode, // JalB16 = 1830 |
25072 | 0 | CEFBS_InMips16Mode, // JrRa16 = 1831 |
25073 | 0 | CEFBS_InMips16Mode, // JrcRa16 = 1832 |
25074 | 0 | CEFBS_InMips16Mode, // JrcRx16 = 1833 |
25075 | 0 | CEFBS_InMips16Mode, // JumpLinkReg16 = 1834 |
25076 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LB = 1835 |
25077 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LB64 = 1836 |
25078 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBE = 1837 |
25079 | 0 | CEFBS_InMicroMips_HasEVA, // LBE_MM = 1838 |
25080 | 0 | CEFBS_InMicroMips, // LBU16_MM = 1839 |
25081 | 0 | CEFBS_HasDSP, // LBUX = 1840 |
25082 | 0 | CEFBS_InMicroMips_HasDSP, // LBUX_MM = 1841 |
25083 | 0 | CEFBS_InMicroMips_HasMips32r6, // LBU_MMR6 = 1842 |
25084 | 0 | CEFBS_InMicroMips, // LB_MM = 1843 |
25085 | 0 | CEFBS_InMicroMips_HasMips32r6, // LB_MMR6 = 1844 |
25086 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LBu = 1845 |
25087 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LBu64 = 1846 |
25088 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LBuE = 1847 |
25089 | 0 | CEFBS_InMicroMips_HasEVA, // LBuE_MM = 1848 |
25090 | 0 | CEFBS_InMicroMips, // LBu_MM = 1849 |
25091 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LD = 1850 |
25092 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC1 = 1851 |
25093 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // LDC164 = 1852 |
25094 | 0 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // LDC1_D64_MMR6 = 1853 |
25095 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // LDC1_MM_D32 = 1854 |
25096 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // LDC1_MM_D64 = 1855 |
25097 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LDC2 = 1856 |
25098 | 0 | CEFBS_InMicroMips_HasMips32r6, // LDC2_MMR6 = 1857 |
25099 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LDC2_R6 = 1858 |
25100 | 0 | CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // LDC3 = 1859 |
25101 | 0 | CEFBS_HasStdEnc_HasMSA, // LDI_B = 1860 |
25102 | 0 | CEFBS_HasStdEnc_HasMSA, // LDI_D = 1861 |
25103 | 0 | CEFBS_HasStdEnc_HasMSA, // LDI_H = 1862 |
25104 | 0 | CEFBS_HasStdEnc_HasMSA, // LDI_W = 1863 |
25105 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDL = 1864 |
25106 | 0 | CEFBS_HasStdEnc_HasMips64r6, // LDPC = 1865 |
25107 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // LDR = 1866 |
25108 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LDXC1 = 1867 |
25109 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LDXC164 = 1868 |
25110 | 0 | CEFBS_HasStdEnc_HasMSA, // LD_B = 1869 |
25111 | 0 | CEFBS_HasStdEnc_HasMSA, // LD_D = 1870 |
25112 | 0 | CEFBS_HasStdEnc_HasMSA, // LD_H = 1871 |
25113 | 0 | CEFBS_HasStdEnc_HasMSA, // LD_W = 1872 |
25114 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LEA_ADDiu = 1873 |
25115 | 0 | CEFBS_NotInMips16Mode_IsGP64bit_NotInMicroMips, // LEA_ADDiu64 = 1874 |
25116 | 0 | CEFBS_InMicroMips, // LEA_ADDiu_MM = 1875 |
25117 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LH = 1876 |
25118 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LH64 = 1877 |
25119 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHE = 1878 |
25120 | 0 | CEFBS_InMicroMips_HasEVA, // LHE_MM = 1879 |
25121 | 0 | CEFBS_InMicroMips, // LHU16_MM = 1880 |
25122 | 0 | CEFBS_HasDSP, // LHX = 1881 |
25123 | 0 | CEFBS_InMicroMips_HasDSP, // LHX_MM = 1882 |
25124 | 0 | CEFBS_InMicroMips, // LH_MM = 1883 |
25125 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LHu = 1884 |
25126 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LHu64 = 1885 |
25127 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LHuE = 1886 |
25128 | 0 | CEFBS_InMicroMips_HasEVA, // LHuE_MM = 1887 |
25129 | 0 | CEFBS_InMicroMips, // LHu_MM = 1888 |
25130 | 0 | CEFBS_InMicroMips_NotMips32r6, // LI16_MM = 1889 |
25131 | 0 | CEFBS_InMicroMips_HasMips32r6, // LI16_MMR6 = 1890 |
25132 | 0 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL = 1891 |
25133 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // LL64 = 1892 |
25134 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // LL64_R6 = 1893 |
25135 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6_NotInMicroMips, // LLD = 1894 |
25136 | 0 | CEFBS_HasStdEnc_HasMips64r6_NotInMicroMips, // LLD_R6 = 1895 |
25137 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LLE = 1896 |
25138 | 0 | CEFBS_InMicroMips_HasEVA, // LLE_MM = 1897 |
25139 | 0 | CEFBS_InMicroMips_NotMips32r6, // LL_MM = 1898 |
25140 | 0 | CEFBS_InMicroMips_HasMips32r6, // LL_MMR6 = 1899 |
25141 | 0 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // LL_R6 = 1900 |
25142 | 0 | CEFBS_HasStdEnc_HasMSA, // LSA = 1901 |
25143 | 0 | CEFBS_InMicroMips_HasMips32r6, // LSA_MMR6 = 1902 |
25144 | 0 | CEFBS_HasStdEnc_HasMips32r6, // LSA_R6 = 1903 |
25145 | 0 | CEFBS_InMicroMips_HasMips32r6, // LUI_MMR6 = 1904 |
25146 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC1 = 1905 |
25147 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // LUXC164 = 1906 |
25148 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // LUXC1_MM = 1907 |
25149 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LUi = 1908 |
25150 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LUi64 = 1909 |
25151 | 0 | CEFBS_InMicroMips_NotMips32r6, // LUi_MM = 1910 |
25152 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // LW = 1911 |
25153 | 0 | CEFBS_InMicroMips, // LW16_MM = 1912 |
25154 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LW64 = 1913 |
25155 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // LWC1 = 1914 |
25156 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // LWC1_MM = 1915 |
25157 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWC2 = 1916 |
25158 | 0 | CEFBS_InMicroMips_HasMips32r6, // LWC2_MMR6 = 1917 |
25159 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // LWC2_R6 = 1918 |
25160 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // LWC3 = 1919 |
25161 | 0 | CEFBS_NotInMips16Mode_HasDSP, // LWDSP = 1920 |
25162 | 0 | CEFBS_InMicroMips_HasDSP, // LWDSP_MM = 1921 |
25163 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1922 |
25164 | 0 | CEFBS_InMicroMips_HasEVA, // LWE_MM = 1923 |
25165 | 0 | CEFBS_InMicroMips, // LWGP_MM = 1924 |
25166 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWL = 1925 |
25167 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LWL64 = 1926 |
25168 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWLE = 1927 |
25169 | 0 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWLE_MM = 1928 |
25170 | 0 | CEFBS_InMicroMips_NotMips32r6, // LWL_MM = 1929 |
25171 | 0 | CEFBS_InMicroMips_NotMips32r6, // LWM16_MM = 1930 |
25172 | 0 | CEFBS_InMicroMips_HasMips32r6, // LWM16_MMR6 = 1931 |
25173 | 0 | CEFBS_InMicroMips, // LWM32_MM = 1932 |
25174 | 0 | CEFBS_HasStdEnc_HasMips32r6, // LWPC = 1933 |
25175 | 0 | CEFBS_InMicroMips_HasMips32r6, // LWPC_MMR6 = 1934 |
25176 | 0 | CEFBS_InMicroMips, // LWP_MM = 1935 |
25177 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // LWR = 1936 |
25178 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // LWR64 = 1937 |
25179 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // LWRE = 1938 |
25180 | 0 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // LWRE_MM = 1939 |
25181 | 0 | CEFBS_InMicroMips_NotMips32r6, // LWR_MM = 1940 |
25182 | 0 | CEFBS_InMicroMips, // LWSP_MM = 1941 |
25183 | 0 | CEFBS_HasStdEnc_HasMips64r6, // LWUPC = 1942 |
25184 | 0 | CEFBS_InMicroMips_NotMips32r6, // LWU_MM = 1943 |
25185 | 0 | CEFBS_HasDSP, // LWX = 1944 |
25186 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // LWXC1 = 1945 |
25187 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // LWXC1_MM = 1946 |
25188 | 0 | CEFBS_InMicroMips, // LWXS_MM = 1947 |
25189 | 0 | CEFBS_InMicroMips_HasDSP, // LWX_MM = 1948 |
25190 | 0 | CEFBS_InMicroMips, // LW_MM = 1949 |
25191 | 0 | CEFBS_InMicroMips_HasMips32r6, // LW_MMR6 = 1950 |
25192 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // LWu = 1951 |
25193 | 0 | CEFBS_InMips16Mode, // LbRxRyOffMemX16 = 1952 |
25194 | 0 | CEFBS_InMips16Mode, // LbuRxRyOffMemX16 = 1953 |
25195 | 0 | CEFBS_InMips16Mode, // LhRxRyOffMemX16 = 1954 |
25196 | 0 | CEFBS_InMips16Mode, // LhuRxRyOffMemX16 = 1955 |
25197 | 0 | CEFBS_InMips16Mode, // LiRxImm16 = 1956 |
25198 | 0 | CEFBS_InMips16Mode, // LiRxImmAlignX16 = 1957 |
25199 | 0 | CEFBS_InMips16Mode, // LiRxImmX16 = 1958 |
25200 | 0 | CEFBS_InMips16Mode, // LwRxPcTcp16 = 1959 |
25201 | 0 | CEFBS_InMips16Mode, // LwRxPcTcpX16 = 1960 |
25202 | 0 | CEFBS_InMips16Mode, // LwRxRyOffMemX16 = 1961 |
25203 | 0 | CEFBS_InMips16Mode, // LwRxSpImmX16 = 1962 |
25204 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADD = 1963 |
25205 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_D = 1964 |
25206 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_D_MMR6 = 1965 |
25207 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MADDF_S = 1966 |
25208 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MADDF_S_MMR6 = 1967 |
25209 | 0 | CEFBS_HasStdEnc_HasMSA, // MADDR_Q_H = 1968 |
25210 | 0 | CEFBS_HasStdEnc_HasMSA, // MADDR_Q_W = 1969 |
25211 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MADDU = 1970 |
25212 | 0 | CEFBS_HasDSP, // MADDU_DSP = 1971 |
25213 | 0 | CEFBS_InMicroMips_HasDSP, // MADDU_DSP_MM = 1972 |
25214 | 0 | CEFBS_InMicroMips_NotMips32r6, // MADDU_MM = 1973 |
25215 | 0 | CEFBS_HasStdEnc_HasMSA, // MADDV_B = 1974 |
25216 | 0 | CEFBS_HasStdEnc_HasMSA, // MADDV_D = 1975 |
25217 | 0 | CEFBS_HasStdEnc_HasMSA, // MADDV_H = 1976 |
25218 | 0 | CEFBS_HasStdEnc_HasMSA, // MADDV_W = 1977 |
25219 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D32 = 1978 |
25220 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_D32_MM = 1979 |
25221 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_D64 = 1980 |
25222 | 0 | CEFBS_HasDSP, // MADD_DSP = 1981 |
25223 | 0 | CEFBS_InMicroMips_HasDSP, // MADD_DSP_MM = 1982 |
25224 | 0 | CEFBS_InMicroMips_NotMips32r6, // MADD_MM = 1983 |
25225 | 0 | CEFBS_HasStdEnc_HasMSA, // MADD_Q_H = 1984 |
25226 | 0 | CEFBS_HasStdEnc_HasMSA, // MADD_Q_W = 1985 |
25227 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MADD_S = 1986 |
25228 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MADD_S_MM = 1987 |
25229 | 0 | CEFBS_HasDSP, // MAQ_SA_W_PHL = 1988 |
25230 | 0 | CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHL_MM = 1989 |
25231 | 0 | CEFBS_HasDSP, // MAQ_SA_W_PHR = 1990 |
25232 | 0 | CEFBS_InMicroMips_HasDSP, // MAQ_SA_W_PHR_MM = 1991 |
25233 | 0 | CEFBS_HasDSP, // MAQ_S_W_PHL = 1992 |
25234 | 0 | CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHL_MM = 1993 |
25235 | 0 | CEFBS_HasDSP, // MAQ_S_W_PHR = 1994 |
25236 | 0 | CEFBS_InMicroMips_HasDSP, // MAQ_S_W_PHR_MM = 1995 |
25237 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_D = 1996 |
25238 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_D_MMR6 = 1997 |
25239 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAXA_S = 1998 |
25240 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAXA_S_MMR6 = 1999 |
25241 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_B = 2000 |
25242 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_D = 2001 |
25243 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_H = 2002 |
25244 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_S_W = 2003 |
25245 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_B = 2004 |
25246 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_D = 2005 |
25247 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_H = 2006 |
25248 | 0 | CEFBS_HasStdEnc_HasMSA, // MAXI_U_W = 2007 |
25249 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_A_B = 2008 |
25250 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_A_D = 2009 |
25251 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_A_H = 2010 |
25252 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_A_W = 2011 |
25253 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_D = 2012 |
25254 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_D_MMR6 = 2013 |
25255 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MAX_S = 2014 |
25256 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_S_B = 2015 |
25257 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_S_D = 2016 |
25258 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_S_H = 2017 |
25259 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MAX_S_MMR6 = 2018 |
25260 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_S_W = 2019 |
25261 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_U_B = 2020 |
25262 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_U_D = 2021 |
25263 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_U_H = 2022 |
25264 | 0 | CEFBS_HasStdEnc_HasMSA, // MAX_U_W = 2023 |
25265 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // MFC0 = 2024 |
25266 | 0 | CEFBS_InMicroMips_HasMips32r6, // MFC0_MMR6 = 2025 |
25267 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 2026 |
25268 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MFC1_D64 = 2027 |
25269 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // MFC1_MM = 2028 |
25270 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MFC1_MMR6 = 2029 |
25271 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // MFC2 = 2030 |
25272 | 0 | CEFBS_InMicroMips_HasMips32r6, // MFC2_MMR6 = 2031 |
25273 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFGC0 = 2032 |
25274 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFGC0_MM = 2033 |
25275 | 0 | CEFBS_InMicroMips_HasMips32r6, // MFHC0_MMR6 = 2034 |
25276 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D32 = 2035 |
25277 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MFHC1_D32_MM = 2036 |
25278 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MFHC1_D64 = 2037 |
25279 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MFHC1_D64_MM = 2038 |
25280 | 0 | CEFBS_InMicroMips_HasMips32r6, // MFHC2_MMR6 = 2039 |
25281 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MFHGC0 = 2040 |
25282 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MFHGC0_MM = 2041 |
25283 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFHI = 2042 |
25284 | 0 | CEFBS_InMicroMips_NotMips32r6, // MFHI16_MM = 2043 |
25285 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFHI64 = 2044 |
25286 | 0 | CEFBS_HasDSP, // MFHI_DSP = 2045 |
25287 | 0 | CEFBS_InMicroMips_HasDSP, // MFHI_DSP_MM = 2046 |
25288 | 0 | CEFBS_InMicroMips_NotMips32r6, // MFHI_MM = 2047 |
25289 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MFLO = 2048 |
25290 | 0 | CEFBS_InMicroMips_NotMips32r6, // MFLO16_MM = 2049 |
25291 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MFLO64 = 2050 |
25292 | 0 | CEFBS_HasDSP, // MFLO_DSP = 2051 |
25293 | 0 | CEFBS_InMicroMips_HasDSP, // MFLO_DSP_MM = 2052 |
25294 | 0 | CEFBS_InMicroMips_NotMips32r6, // MFLO_MM = 2053 |
25295 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MFTR = 2054 |
25296 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_D = 2055 |
25297 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_D_MMR6 = 2056 |
25298 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MINA_S = 2057 |
25299 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MINA_S_MMR6 = 2058 |
25300 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_S_B = 2059 |
25301 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_S_D = 2060 |
25302 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_S_H = 2061 |
25303 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_S_W = 2062 |
25304 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_U_B = 2063 |
25305 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_U_D = 2064 |
25306 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_U_H = 2065 |
25307 | 0 | CEFBS_HasStdEnc_HasMSA, // MINI_U_W = 2066 |
25308 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_A_B = 2067 |
25309 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_A_D = 2068 |
25310 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_A_H = 2069 |
25311 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_A_W = 2070 |
25312 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_D = 2071 |
25313 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_D_MMR6 = 2072 |
25314 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MIN_S = 2073 |
25315 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_S_B = 2074 |
25316 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_S_D = 2075 |
25317 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_S_H = 2076 |
25318 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MIN_S_MMR6 = 2077 |
25319 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_S_W = 2078 |
25320 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_U_B = 2079 |
25321 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_U_D = 2080 |
25322 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_U_H = 2081 |
25323 | 0 | CEFBS_HasStdEnc_HasMSA, // MIN_U_W = 2082 |
25324 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MOD = 2083 |
25325 | 0 | CEFBS_HasDSP, // MODSUB = 2084 |
25326 | 0 | CEFBS_InMicroMips_HasDSP, // MODSUB_MM = 2085 |
25327 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MODU = 2086 |
25328 | 0 | CEFBS_InMicroMips_HasMips32r6, // MODU_MMR6 = 2087 |
25329 | 0 | CEFBS_InMicroMips_HasMips32r6, // MOD_MMR6 = 2088 |
25330 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_S_B = 2089 |
25331 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_S_D = 2090 |
25332 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_S_H = 2091 |
25333 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_S_W = 2092 |
25334 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_U_B = 2093 |
25335 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_U_D = 2094 |
25336 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_U_H = 2095 |
25337 | 0 | CEFBS_HasStdEnc_HasMSA, // MOD_U_W = 2096 |
25338 | 0 | CEFBS_InMicroMips_NotMips32r6, // MOVE16_MM = 2097 |
25339 | 0 | CEFBS_InMicroMips_HasMips32r6, // MOVE16_MMR6 = 2098 |
25340 | 0 | CEFBS_InMicroMips_NotMips32r6, // MOVEP_MM = 2099 |
25341 | 0 | CEFBS_InMicroMips_HasMips32r6, // MOVEP_MMR6 = 2100 |
25342 | 0 | CEFBS_HasStdEnc_HasMSA, // MOVE_V = 2101 |
25343 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D32 = 2102 |
25344 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVF_D32_MM = 2103 |
25345 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_D64 = 2104 |
25346 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I = 2105 |
25347 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_I64 = 2106 |
25348 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_I_MM = 2107 |
25349 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVF_S = 2108 |
25350 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVF_S_MM = 2109 |
25351 | 0 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_D64 = 2110 |
25352 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I = 2111 |
25353 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I64_I64 = 2112 |
25354 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I64_S = 2113 |
25355 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D32 = 2114 |
25356 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVN_I_D32_MM = 2115 |
25357 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_D64 = 2116 |
25358 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I = 2117 |
25359 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVN_I_I64 = 2118 |
25360 | 0 | CEFBS_InMicroMips_NotMips32r6, // MOVN_I_MM = 2119 |
25361 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVN_I_S = 2120 |
25362 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVN_I_S_MM = 2121 |
25363 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D32 = 2122 |
25364 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVT_D32_MM = 2123 |
25365 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_D64 = 2124 |
25366 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I = 2125 |
25367 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_I64 = 2126 |
25368 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_I_MM = 2127 |
25369 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVT_S = 2128 |
25370 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVT_S_MM = 2129 |
25371 | 0 | CEFBS_HasStdEnc_IsGP64bit_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_D64 = 2130 |
25372 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I = 2131 |
25373 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I64_I64 = 2132 |
25374 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I64_S = 2133 |
25375 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D32 = 2134 |
25376 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat, // MOVZ_I_D32_MM = 2135 |
25377 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_D64 = 2136 |
25378 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I = 2137 |
25379 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips4_32_NotMips32r6_NotMips64r6_NotInMicroMips, // MOVZ_I_I64 = 2138 |
25380 | 0 | CEFBS_InMicroMips_NotMips32r6, // MOVZ_I_MM = 2139 |
25381 | 0 | CEFBS_HasStdEnc_HasMips4_32_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // MOVZ_I_S = 2140 |
25382 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // MOVZ_I_S_MM = 2141 |
25383 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUB = 2142 |
25384 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_D = 2143 |
25385 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_D_MMR6 = 2144 |
25386 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // MSUBF_S = 2145 |
25387 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MSUBF_S_MMR6 = 2146 |
25388 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_H = 2147 |
25389 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUBR_Q_W = 2148 |
25390 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MSUBU = 2149 |
25391 | 0 | CEFBS_HasDSP, // MSUBU_DSP = 2150 |
25392 | 0 | CEFBS_InMicroMips_HasDSP, // MSUBU_DSP_MM = 2151 |
25393 | 0 | CEFBS_InMicroMips_NotMips32r6, // MSUBU_MM = 2152 |
25394 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUBV_B = 2153 |
25395 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUBV_D = 2154 |
25396 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUBV_H = 2155 |
25397 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUBV_W = 2156 |
25398 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D32 = 2157 |
25399 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_D32_MM = 2158 |
25400 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_D64 = 2159 |
25401 | 0 | CEFBS_HasDSP, // MSUB_DSP = 2160 |
25402 | 0 | CEFBS_InMicroMips_HasDSP, // MSUB_DSP_MM = 2161 |
25403 | 0 | CEFBS_InMicroMips_NotMips32r6, // MSUB_MM = 2162 |
25404 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUB_Q_H = 2163 |
25405 | 0 | CEFBS_HasStdEnc_HasMSA, // MSUB_Q_W = 2164 |
25406 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips_HasMadd4, // MSUB_S = 2165 |
25407 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // MSUB_S_MM = 2166 |
25408 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // MTC0 = 2167 |
25409 | 0 | CEFBS_InMicroMips_HasMips32r6, // MTC0_MMR6 = 2168 |
25410 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MTC1 = 2169 |
25411 | 0 | CEFBS_HasStdEnc_IsFP64bit_IsNotSoftFloat_NotInMicroMips, // MTC1_D64 = 2170 |
25412 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTC1_D64_MM = 2171 |
25413 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // MTC1_MM = 2172 |
25414 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // MTC1_MMR6 = 2173 |
25415 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // MTC2 = 2174 |
25416 | 0 | CEFBS_InMicroMips_HasMips32r6, // MTC2_MMR6 = 2175 |
25417 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTGC0 = 2176 |
25418 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTGC0_MM = 2177 |
25419 | 0 | CEFBS_InMicroMips_HasMips32r6, // MTHC0_MMR6 = 2178 |
25420 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D32 = 2179 |
25421 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // MTHC1_D32_MM = 2180 |
25422 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_IsNotSoftFloat_NotInMicroMips, // MTHC1_D64 = 2181 |
25423 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // MTHC1_D64_MM = 2182 |
25424 | 0 | CEFBS_InMicroMips_HasMips32r6, // MTHC2_MMR6 = 2183 |
25425 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // MTHGC0 = 2184 |
25426 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // MTHGC0_MM = 2185 |
25427 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTHI = 2186 |
25428 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTHI64 = 2187 |
25429 | 0 | CEFBS_HasDSP, // MTHI_DSP = 2188 |
25430 | 0 | CEFBS_InMicroMips_HasDSP, // MTHI_DSP_MM = 2189 |
25431 | 0 | CEFBS_InMicroMips_NotMips32r6, // MTHI_MM = 2190 |
25432 | 0 | CEFBS_HasDSP, // MTHLIP = 2191 |
25433 | 0 | CEFBS_InMicroMips_HasDSP, // MTHLIP_MM = 2192 |
25434 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MTLO = 2193 |
25435 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // MTLO64 = 2194 |
25436 | 0 | CEFBS_HasDSP, // MTLO_DSP = 2195 |
25437 | 0 | CEFBS_InMicroMips_HasDSP, // MTLO_DSP_MM = 2196 |
25438 | 0 | CEFBS_InMicroMips_NotMips32r6, // MTLO_MM = 2197 |
25439 | 0 | CEFBS_HasCnMips, // MTM0 = 2198 |
25440 | 0 | CEFBS_HasCnMips, // MTM1 = 2199 |
25441 | 0 | CEFBS_HasCnMips, // MTM2 = 2200 |
25442 | 0 | CEFBS_HasCnMips, // MTP0 = 2201 |
25443 | 0 | CEFBS_HasCnMips, // MTP1 = 2202 |
25444 | 0 | CEFBS_HasCnMips, // MTP2 = 2203 |
25445 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // MTTR = 2204 |
25446 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUH = 2205 |
25447 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2206 |
25448 | 0 | CEFBS_InMicroMips_HasMips32r6, // MUHU_MMR6 = 2207 |
25449 | 0 | CEFBS_InMicroMips_HasMips32r6, // MUH_MMR6 = 2208 |
25450 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // MUL = 2209 |
25451 | 0 | CEFBS_HasDSP, // MULEQ_S_W_PHL = 2210 |
25452 | 0 | CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHL_MM = 2211 |
25453 | 0 | CEFBS_HasDSP, // MULEQ_S_W_PHR = 2212 |
25454 | 0 | CEFBS_InMicroMips_HasDSP, // MULEQ_S_W_PHR_MM = 2213 |
25455 | 0 | CEFBS_HasDSP, // MULEU_S_PH_QBL = 2214 |
25456 | 0 | CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBL_MM = 2215 |
25457 | 0 | CEFBS_HasDSP, // MULEU_S_PH_QBR = 2216 |
25458 | 0 | CEFBS_InMicroMips_HasDSP, // MULEU_S_PH_QBR_MM = 2217 |
25459 | 0 | CEFBS_HasDSP, // MULQ_RS_PH = 2218 |
25460 | 0 | CEFBS_InMicroMips_HasDSP, // MULQ_RS_PH_MM = 2219 |
25461 | 0 | CEFBS_HasDSPR2, // MULQ_RS_W = 2220 |
25462 | 0 | CEFBS_InMicroMips_HasDSPR2, // MULQ_RS_W_MMR2 = 2221 |
25463 | 0 | CEFBS_HasDSPR2, // MULQ_S_PH = 2222 |
25464 | 0 | CEFBS_InMicroMips_HasDSPR2, // MULQ_S_PH_MMR2 = 2223 |
25465 | 0 | CEFBS_HasDSPR2, // MULQ_S_W = 2224 |
25466 | 0 | CEFBS_InMicroMips_HasDSPR2, // MULQ_S_W_MMR2 = 2225 |
25467 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMips3D, // MULR_PS64 = 2226 |
25468 | 0 | CEFBS_HasStdEnc_HasMSA, // MULR_Q_H = 2227 |
25469 | 0 | CEFBS_HasStdEnc_HasMSA, // MULR_Q_W = 2228 |
25470 | 0 | CEFBS_HasDSP, // MULSAQ_S_W_PH = 2229 |
25471 | 0 | CEFBS_InMicroMips_HasDSP, // MULSAQ_S_W_PH_MM = 2230 |
25472 | 0 | CEFBS_HasDSPR2, // MULSA_W_PH = 2231 |
25473 | 0 | CEFBS_InMicroMips_HasDSPR2, // MULSA_W_PH_MMR2 = 2232 |
25474 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULT = 2233 |
25475 | 0 | CEFBS_HasDSP, // MULTU_DSP = 2234 |
25476 | 0 | CEFBS_InMicroMips_HasDSP, // MULTU_DSP_MM = 2235 |
25477 | 0 | CEFBS_HasDSP, // MULT_DSP = 2236 |
25478 | 0 | CEFBS_InMicroMips_HasDSP, // MULT_DSP_MM = 2237 |
25479 | 0 | CEFBS_InMicroMips_NotMips32r6, // MULT_MM = 2238 |
25480 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // MULTu = 2239 |
25481 | 0 | CEFBS_InMicroMips_NotMips32r6, // MULTu_MM = 2240 |
25482 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MULU = 2241 |
25483 | 0 | CEFBS_InMicroMips_HasMips32r6, // MULU_MMR6 = 2242 |
25484 | 0 | CEFBS_HasStdEnc_HasMSA, // MULV_B = 2243 |
25485 | 0 | CEFBS_HasStdEnc_HasMSA, // MULV_D = 2244 |
25486 | 0 | CEFBS_HasStdEnc_HasMSA, // MULV_H = 2245 |
25487 | 0 | CEFBS_HasStdEnc_HasMSA, // MULV_W = 2246 |
25488 | 0 | CEFBS_InMicroMips_NotMips32r6, // MUL_MM = 2247 |
25489 | 0 | CEFBS_InMicroMips_HasMips32r6, // MUL_MMR6 = 2248 |
25490 | 0 | CEFBS_HasDSPR2, // MUL_PH = 2249 |
25491 | 0 | CEFBS_InMicroMips_HasDSPR2, // MUL_PH_MMR2 = 2250 |
25492 | 0 | CEFBS_HasStdEnc_HasMSA, // MUL_Q_H = 2251 |
25493 | 0 | CEFBS_HasStdEnc_HasMSA, // MUL_Q_W = 2252 |
25494 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUL_R6 = 2253 |
25495 | 0 | CEFBS_HasDSPR2, // MUL_S_PH = 2254 |
25496 | 0 | CEFBS_InMicroMips_HasDSPR2, // MUL_S_PH_MMR2 = 2255 |
25497 | 0 | CEFBS_InMips16Mode, // Mfhi16 = 2256 |
25498 | 0 | CEFBS_InMips16Mode, // Mflo16 = 2257 |
25499 | 0 | CEFBS_InMips16Mode, // Move32R16 = 2258 |
25500 | 0 | CEFBS_InMips16Mode, // MoveR3216 = 2259 |
25501 | 0 | CEFBS_HasStdEnc_HasMSA, // NLOC_B = 2260 |
25502 | 0 | CEFBS_HasStdEnc_HasMSA, // NLOC_D = 2261 |
25503 | 0 | CEFBS_HasStdEnc_HasMSA, // NLOC_H = 2262 |
25504 | 0 | CEFBS_HasStdEnc_HasMSA, // NLOC_W = 2263 |
25505 | 0 | CEFBS_HasStdEnc_HasMSA, // NLZC_B = 2264 |
25506 | 0 | CEFBS_HasStdEnc_HasMSA, // NLZC_D = 2265 |
25507 | 0 | CEFBS_HasStdEnc_HasMSA, // NLZC_H = 2266 |
25508 | 0 | CEFBS_HasStdEnc_HasMSA, // NLZC_W = 2267 |
25509 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D32 = 2268 |
25510 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_D32_MM = 2269 |
25511 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_D64 = 2270 |
25512 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMADD_S = 2271 |
25513 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMADD_S_MM = 2272 |
25514 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D32 = 2273 |
25515 | 0 | CEFBS_InMicroMips_NotFP64bit_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_D32_MM = 2274 |
25516 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_D64 = 2275 |
25517 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_HasMadd4_NotInMicroMips, // NMSUB_S = 2276 |
25518 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat_HasMadd4, // NMSUB_S_MM = 2277 |
25519 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // NOR = 2278 |
25520 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // NOR64 = 2279 |
25521 | 0 | CEFBS_HasStdEnc_HasMSA, // NORI_B = 2280 |
25522 | 0 | CEFBS_InMicroMips_NotMips32r6, // NOR_MM = 2281 |
25523 | 0 | CEFBS_InMicroMips_HasMips32r6, // NOR_MMR6 = 2282 |
25524 | 0 | CEFBS_HasStdEnc_HasMSA, // NOR_V = 2283 |
25525 | 0 | CEFBS_InMicroMips_NotMips32r6, // NOT16_MM = 2284 |
25526 | 0 | CEFBS_InMicroMips_HasMips32r6, // NOT16_MMR6 = 2285 |
25527 | 0 | CEFBS_InMips16Mode, // NegRxRy16 = 2286 |
25528 | 0 | CEFBS_InMips16Mode, // NotRxRy16 = 2287 |
25529 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // OR = 2288 |
25530 | 0 | CEFBS_InMicroMips_NotMips32r6, // OR16_MM = 2289 |
25531 | 0 | CEFBS_InMicroMips_HasMips32r6, // OR16_MMR6 = 2290 |
25532 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // OR64 = 2291 |
25533 | 0 | CEFBS_HasStdEnc_HasMSA, // ORI_B = 2292 |
25534 | 0 | CEFBS_InMicroMips_HasMips32r6, // ORI_MMR6 = 2293 |
25535 | 0 | CEFBS_InMicroMips_NotMips32r6, // OR_MM = 2294 |
25536 | 0 | CEFBS_InMicroMips_HasMips32r6, // OR_MMR6 = 2295 |
25537 | 0 | CEFBS_HasStdEnc_HasMSA, // OR_V = 2296 |
25538 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // ORi = 2297 |
25539 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // ORi64 = 2298 |
25540 | 0 | CEFBS_InMicroMips_NotMips32r6, // ORi_MM = 2299 |
25541 | 0 | CEFBS_InMips16Mode, // OrRxRxRy16 = 2300 |
25542 | 0 | CEFBS_HasDSP, // PACKRL_PH = 2301 |
25543 | 0 | CEFBS_InMicroMips_HasDSP, // PACKRL_PH_MM = 2302 |
25544 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // PAUSE = 2303 |
25545 | 0 | CEFBS_InMicroMips, // PAUSE_MM = 2304 |
25546 | 0 | CEFBS_InMicroMips_HasMips32r6, // PAUSE_MMR6 = 2305 |
25547 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKEV_B = 2306 |
25548 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKEV_D = 2307 |
25549 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKEV_H = 2308 |
25550 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKEV_W = 2309 |
25551 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKOD_B = 2310 |
25552 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKOD_D = 2311 |
25553 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKOD_H = 2312 |
25554 | 0 | CEFBS_HasStdEnc_HasMSA, // PCKOD_W = 2313 |
25555 | 0 | CEFBS_HasStdEnc_HasMSA, // PCNT_B = 2314 |
25556 | 0 | CEFBS_HasStdEnc_HasMSA, // PCNT_D = 2315 |
25557 | 0 | CEFBS_HasStdEnc_HasMSA, // PCNT_H = 2316 |
25558 | 0 | CEFBS_HasStdEnc_HasMSA, // PCNT_W = 2317 |
25559 | 0 | CEFBS_HasDSP, // PICK_PH = 2318 |
25560 | 0 | CEFBS_InMicroMips_HasDSP, // PICK_PH_MM = 2319 |
25561 | 0 | CEFBS_HasDSP, // PICK_QB = 2320 |
25562 | 0 | CEFBS_InMicroMips_HasDSP, // PICK_QB_MM = 2321 |
25563 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLL_PS64 = 2322 |
25564 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PLU_PS64 = 2323 |
25565 | 0 | CEFBS_HasCnMips, // POP = 2324 |
25566 | 0 | CEFBS_HasDSP, // PRECEQU_PH_QBL = 2325 |
25567 | 0 | CEFBS_HasDSP, // PRECEQU_PH_QBLA = 2326 |
25568 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBLA_MM = 2327 |
25569 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBL_MM = 2328 |
25570 | 0 | CEFBS_HasDSP, // PRECEQU_PH_QBR = 2329 |
25571 | 0 | CEFBS_HasDSP, // PRECEQU_PH_QBRA = 2330 |
25572 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBRA_MM = 2331 |
25573 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEQU_PH_QBR_MM = 2332 |
25574 | 0 | CEFBS_HasDSP, // PRECEQ_W_PHL = 2333 |
25575 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHL_MM = 2334 |
25576 | 0 | CEFBS_HasDSP, // PRECEQ_W_PHR = 2335 |
25577 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEQ_W_PHR_MM = 2336 |
25578 | 0 | CEFBS_HasDSP, // PRECEU_PH_QBL = 2337 |
25579 | 0 | CEFBS_HasDSP, // PRECEU_PH_QBLA = 2338 |
25580 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBLA_MM = 2339 |
25581 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBL_MM = 2340 |
25582 | 0 | CEFBS_HasDSP, // PRECEU_PH_QBR = 2341 |
25583 | 0 | CEFBS_HasDSP, // PRECEU_PH_QBRA = 2342 |
25584 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBRA_MM = 2343 |
25585 | 0 | CEFBS_InMicroMips_HasDSP, // PRECEU_PH_QBR_MM = 2344 |
25586 | 0 | CEFBS_HasDSP, // PRECRQU_S_QB_PH = 2345 |
25587 | 0 | CEFBS_InMicroMips_HasDSP, // PRECRQU_S_QB_PH_MM = 2346 |
25588 | 0 | CEFBS_HasDSP, // PRECRQ_PH_W = 2347 |
25589 | 0 | CEFBS_InMicroMips_HasDSP, // PRECRQ_PH_W_MM = 2348 |
25590 | 0 | CEFBS_HasDSP, // PRECRQ_QB_PH = 2349 |
25591 | 0 | CEFBS_InMicroMips_HasDSP, // PRECRQ_QB_PH_MM = 2350 |
25592 | 0 | CEFBS_HasDSP, // PRECRQ_RS_PH_W = 2351 |
25593 | 0 | CEFBS_InMicroMips_HasDSP, // PRECRQ_RS_PH_W_MM = 2352 |
25594 | 0 | CEFBS_HasDSPR2, // PRECR_QB_PH = 2353 |
25595 | 0 | CEFBS_InMicroMips_HasDSPR2, // PRECR_QB_PH_MMR2 = 2354 |
25596 | 0 | CEFBS_HasDSPR2, // PRECR_SRA_PH_W = 2355 |
25597 | 0 | CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_PH_W_MMR2 = 2356 |
25598 | 0 | CEFBS_HasDSPR2, // PRECR_SRA_R_PH_W = 2357 |
25599 | 0 | CEFBS_InMicroMips_HasDSPR2, // PRECR_SRA_R_PH_W_MMR2 = 2358 |
25600 | 0 | CEFBS_HasStdEnc_HasMips3_32_NotMips32r6_NotMips64r6_NotInMicroMips, // PREF = 2359 |
25601 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // PREFE = 2360 |
25602 | 0 | CEFBS_InMicroMips_HasEVA, // PREFE_MM = 2361 |
25603 | 0 | CEFBS_InMicroMips_NotMips32r6, // PREFX_MM = 2362 |
25604 | 0 | CEFBS_InMicroMips_NotMips32r6, // PREF_MM = 2363 |
25605 | 0 | CEFBS_InMicroMips_HasMips32r6, // PREF_MMR6 = 2364 |
25606 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // PREF_R6 = 2365 |
25607 | 0 | CEFBS_HasDSPR2, // PREPEND = 2366 |
25608 | 0 | CEFBS_InMicroMips_HasDSPR2, // PREPEND_MMR2 = 2367 |
25609 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUL_PS64 = 2368 |
25610 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // PUU_PS64 = 2369 |
25611 | 0 | CEFBS_HasDSP, // RADDU_W_QB = 2370 |
25612 | 0 | CEFBS_InMicroMips_HasDSP, // RADDU_W_QB_MM = 2371 |
25613 | 0 | CEFBS_HasDSP, // RDDSP = 2372 |
25614 | 0 | CEFBS_InMicroMips_HasDSP, // RDDSP_MM = 2373 |
25615 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // RDHWR = 2374 |
25616 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // RDHWR64 = 2375 |
25617 | 0 | CEFBS_InMicroMips_NotMips32r6, // RDHWR_MM = 2376 |
25618 | 0 | CEFBS_InMicroMips_HasMips32r6, // RDHWR_MMR6 = 2377 |
25619 | 0 | CEFBS_InMicroMips_HasMips32r6, // RDPGPR_MMR6 = 2378 |
25620 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D32 = 2379 |
25621 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RECIP_D32_MM = 2380 |
25622 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_D64 = 2381 |
25623 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RECIP_D64_MM = 2382 |
25624 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RECIP_S = 2383 |
25625 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // RECIP_S_MM = 2384 |
25626 | 0 | CEFBS_HasDSP, // REPLV_PH = 2385 |
25627 | 0 | CEFBS_InMicroMips_HasDSP, // REPLV_PH_MM = 2386 |
25628 | 0 | CEFBS_HasDSP, // REPLV_QB = 2387 |
25629 | 0 | CEFBS_InMicroMips_HasDSP, // REPLV_QB_MM = 2388 |
25630 | 0 | CEFBS_HasDSP, // REPL_PH = 2389 |
25631 | 0 | CEFBS_InMicroMips_HasDSP, // REPL_PH_MM = 2390 |
25632 | 0 | CEFBS_HasDSP, // REPL_QB = 2391 |
25633 | 0 | CEFBS_InMicroMips_HasDSP, // REPL_QB_MM = 2392 |
25634 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_D = 2393 |
25635 | 0 | CEFBS_InMicroMips_HasMips32r6, // RINT_D_MMR6 = 2394 |
25636 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // RINT_S = 2395 |
25637 | 0 | CEFBS_InMicroMips_HasMips32r6, // RINT_S_MMR6 = 2396 |
25638 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTR = 2397 |
25639 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // ROTRV = 2398 |
25640 | 0 | CEFBS_InMicroMips, // ROTRV_MM = 2399 |
25641 | 0 | CEFBS_InMicroMips, // ROTR_MM = 2400 |
25642 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // ROUND_L_D64 = 2401 |
25643 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_D_MMR6 = 2402 |
25644 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_L_S = 2403 |
25645 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_L_S_MMR6 = 2404 |
25646 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D32 = 2405 |
25647 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_D64 = 2406 |
25648 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_D_MMR6 = 2407 |
25649 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // ROUND_W_MM = 2408 |
25650 | 0 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // ROUND_W_S = 2409 |
25651 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // ROUND_W_S_MM = 2410 |
25652 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // ROUND_W_S_MMR6 = 2411 |
25653 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D32 = 2412 |
25654 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // RSQRT_D32_MM = 2413 |
25655 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_D64 = 2414 |
25656 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // RSQRT_D64_MM = 2415 |
25657 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_IsNotSoftFloat_NotInMicroMips, // RSQRT_S = 2416 |
25658 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // RSQRT_S_MM = 2417 |
25659 | 0 | CEFBS_InMips16Mode, // Restore16 = 2418 |
25660 | 0 | CEFBS_InMips16Mode, // RestoreX16 = 2419 |
25661 | 0 | CEFBS_HasCnMipsP, // SAA = 2420 |
25662 | 0 | CEFBS_HasCnMipsP, // SAAD = 2421 |
25663 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_S_B = 2422 |
25664 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_S_D = 2423 |
25665 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_S_H = 2424 |
25666 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_S_W = 2425 |
25667 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_U_B = 2426 |
25668 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_U_D = 2427 |
25669 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_U_H = 2428 |
25670 | 0 | CEFBS_HasStdEnc_HasMSA, // SAT_U_W = 2429 |
25671 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SB = 2430 |
25672 | 0 | CEFBS_InMicroMips_NotMips32r6, // SB16_MM = 2431 |
25673 | 0 | CEFBS_InMicroMips_HasMips32r6, // SB16_MMR6 = 2432 |
25674 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SB64 = 2433 |
25675 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SBE = 2434 |
25676 | 0 | CEFBS_InMicroMips_HasEVA, // SBE_MM = 2435 |
25677 | 0 | CEFBS_InMicroMips, // SB_MM = 2436 |
25678 | 0 | CEFBS_InMicroMips_HasMips32r6, // SB_MMR6 = 2437 |
25679 | 0 | CEFBS_HasStdEnc_IsPTR32bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC = 2438 |
25680 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SC64 = 2439 |
25681 | 0 | CEFBS_HasStdEnc_IsPTR64bit_HasMips64r6_NotInMicroMips, // SC64_R6 = 2440 |
25682 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SCD = 2441 |
25683 | 0 | CEFBS_HasStdEnc_HasMips32r6, // SCD_R6 = 2442 |
25684 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SCE = 2443 |
25685 | 0 | CEFBS_InMicroMips_HasEVA, // SCE_MM = 2444 |
25686 | 0 | CEFBS_InMicroMips_NotMips32r6, // SC_MM = 2445 |
25687 | 0 | CEFBS_InMicroMips_HasMips32r6, // SC_MMR6 = 2446 |
25688 | 0 | CEFBS_HasStdEnc_IsPTR32bit_HasMips32r6_NotInMicroMips, // SC_R6 = 2447 |
25689 | 0 | CEFBS_HasStdEnc_HasMips3_NotInMicroMips, // SD = 2448 |
25690 | 0 | CEFBS_HasStdEnc_HasMips32_NotMips32r6_NotMips64r6_NotInMicroMips, // SDBBP = 2449 |
25691 | 0 | CEFBS_InMicroMips_NotMips32r6, // SDBBP16_MM = 2450 |
25692 | 0 | CEFBS_InMicroMips_HasMips32r6, // SDBBP16_MMR6 = 2451 |
25693 | 0 | CEFBS_InMicroMips, // SDBBP_MM = 2452 |
25694 | 0 | CEFBS_InMicroMips_HasMips32r6, // SDBBP_MMR6 = 2453 |
25695 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDBBP_R6 = 2454 |
25696 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC1 = 2455 |
25697 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // SDC164 = 2456 |
25698 | 0 | CEFBS_InMicroMips_IsFP64bit_HasMips32r6_IsNotSoftFloat, // SDC1_D64_MMR6 = 2457 |
25699 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // SDC1_MM_D32 = 2458 |
25700 | 0 | CEFBS_InMicroMips_IsFP64bit_IsNotSoftFloat, // SDC1_MM_D64 = 2459 |
25701 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // SDC2 = 2460 |
25702 | 0 | CEFBS_InMicroMips_HasMips32r6, // SDC2_MMR6 = 2461 |
25703 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SDC2_R6 = 2462 |
25704 | 0 | CEFBS_HasStdEnc_HasMips2_NotCnMips_NotInMicroMips, // SDC3 = 2463 |
25705 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SDIV = 2464 |
25706 | 0 | CEFBS_InMicroMips_NotMips32r6, // SDIV_MM = 2465 |
25707 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDL = 2466 |
25708 | 0 | CEFBS_HasStdEnc_HasMips3_NotMips32r6_NotMips64r6, // SDR = 2467 |
25709 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SDXC1 = 2468 |
25710 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SDXC164 = 2469 |
25711 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEB = 2470 |
25712 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEB64 = 2471 |
25713 | 0 | CEFBS_InMicroMips, // SEB_MM = 2472 |
25714 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SEH = 2473 |
25715 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r2, // SEH64 = 2474 |
25716 | 0 | CEFBS_InMicroMips, // SEH_MM = 2475 |
25717 | 0 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELEQZ = 2476 |
25718 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELEQZ64 = 2477 |
25719 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_D = 2478 |
25720 | 0 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_D_MMR6 = 2479 |
25721 | 0 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_MMR6 = 2480 |
25722 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELEQZ_S = 2481 |
25723 | 0 | CEFBS_InMicroMips_HasMips32r6, // SELEQZ_S_MMR6 = 2482 |
25724 | 0 | CEFBS_HasStdEnc_IsGP32bit_HasMips32r6_NotInMicroMips, // SELNEZ = 2483 |
25725 | 0 | CEFBS_HasStdEnc_IsGP64bit_HasMips32r6, // SELNEZ64 = 2484 |
25726 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_D = 2485 |
25727 | 0 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_D_MMR6 = 2486 |
25728 | 0 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_MMR6 = 2487 |
25729 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SELNEZ_S = 2488 |
25730 | 0 | CEFBS_InMicroMips_HasMips32r6, // SELNEZ_S_MMR6 = 2489 |
25731 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_D = 2490 |
25732 | 0 | CEFBS_InMicroMips_HasMips32r6, // SEL_D_MMR6 = 2491 |
25733 | 0 | CEFBS_HasStdEnc_HasMips32r6_IsNotSoftFloat_NotInMicroMips, // SEL_S = 2492 |
25734 | 0 | CEFBS_InMicroMips_HasMips32r6, // SEL_S_MMR6 = 2493 |
25735 | 0 | CEFBS_HasCnMips, // SEQ = 2494 |
25736 | 0 | CEFBS_HasCnMips, // SEQi = 2495 |
25737 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SH = 2496 |
25738 | 0 | CEFBS_InMicroMips_NotMips32r6, // SH16_MM = 2497 |
25739 | 0 | CEFBS_InMicroMips_HasMips32r6, // SH16_MMR6 = 2498 |
25740 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SH64 = 2499 |
25741 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SHE = 2500 |
25742 | 0 | CEFBS_InMicroMips_HasEVA, // SHE_MM = 2501 |
25743 | 0 | CEFBS_HasStdEnc_HasMSA, // SHF_B = 2502 |
25744 | 0 | CEFBS_HasStdEnc_HasMSA, // SHF_H = 2503 |
25745 | 0 | CEFBS_HasStdEnc_HasMSA, // SHF_W = 2504 |
25746 | 0 | CEFBS_HasDSP, // SHILO = 2505 |
25747 | 0 | CEFBS_HasDSP, // SHILOV = 2506 |
25748 | 0 | CEFBS_InMicroMips_HasDSP, // SHILOV_MM = 2507 |
25749 | 0 | CEFBS_InMicroMips_HasDSP, // SHILO_MM = 2508 |
25750 | 0 | CEFBS_HasDSP, // SHLLV_PH = 2509 |
25751 | 0 | CEFBS_InMicroMips_HasDSP, // SHLLV_PH_MM = 2510 |
25752 | 0 | CEFBS_HasDSP, // SHLLV_QB = 2511 |
25753 | 0 | CEFBS_InMicroMips_HasDSP, // SHLLV_QB_MM = 2512 |
25754 | 0 | CEFBS_HasDSP, // SHLLV_S_PH = 2513 |
25755 | 0 | CEFBS_InMicroMips_HasDSP, // SHLLV_S_PH_MM = 2514 |
25756 | 0 | CEFBS_HasDSP, // SHLLV_S_W = 2515 |
25757 | 0 | CEFBS_InMicroMips_HasDSP, // SHLLV_S_W_MM = 2516 |
25758 | 0 | CEFBS_HasDSP, // SHLL_PH = 2517 |
25759 | 0 | CEFBS_InMicroMips_HasDSP, // SHLL_PH_MM = 2518 |
25760 | 0 | CEFBS_HasDSP, // SHLL_QB = 2519 |
25761 | 0 | CEFBS_InMicroMips_HasDSP, // SHLL_QB_MM = 2520 |
25762 | 0 | CEFBS_HasDSP, // SHLL_S_PH = 2521 |
25763 | 0 | CEFBS_InMicroMips_HasDSP, // SHLL_S_PH_MM = 2522 |
25764 | 0 | CEFBS_HasDSP, // SHLL_S_W = 2523 |
25765 | 0 | CEFBS_InMicroMips_HasDSP, // SHLL_S_W_MM = 2524 |
25766 | 0 | CEFBS_HasDSP, // SHRAV_PH = 2525 |
25767 | 0 | CEFBS_InMicroMips_HasDSP, // SHRAV_PH_MM = 2526 |
25768 | 0 | CEFBS_HasDSPR2, // SHRAV_QB = 2527 |
25769 | 0 | CEFBS_InMicroMips_HasDSPR2, // SHRAV_QB_MMR2 = 2528 |
25770 | 0 | CEFBS_HasDSP, // SHRAV_R_PH = 2529 |
25771 | 0 | CEFBS_InMicroMips_HasDSP, // SHRAV_R_PH_MM = 2530 |
25772 | 0 | CEFBS_HasDSPR2, // SHRAV_R_QB = 2531 |
25773 | 0 | CEFBS_InMicroMips_HasDSPR2, // SHRAV_R_QB_MMR2 = 2532 |
25774 | 0 | CEFBS_HasDSP, // SHRAV_R_W = 2533 |
25775 | 0 | CEFBS_InMicroMips_HasDSP, // SHRAV_R_W_MM = 2534 |
25776 | 0 | CEFBS_HasDSP, // SHRA_PH = 2535 |
25777 | 0 | CEFBS_InMicroMips_HasDSP, // SHRA_PH_MM = 2536 |
25778 | 0 | CEFBS_HasDSPR2, // SHRA_QB = 2537 |
25779 | 0 | CEFBS_InMicroMips_HasDSPR2, // SHRA_QB_MMR2 = 2538 |
25780 | 0 | CEFBS_HasDSP, // SHRA_R_PH = 2539 |
25781 | 0 | CEFBS_InMicroMips_HasDSP, // SHRA_R_PH_MM = 2540 |
25782 | 0 | CEFBS_HasDSPR2, // SHRA_R_QB = 2541 |
25783 | 0 | CEFBS_InMicroMips_HasDSPR2, // SHRA_R_QB_MMR2 = 2542 |
25784 | 0 | CEFBS_HasDSP, // SHRA_R_W = 2543 |
25785 | 0 | CEFBS_InMicroMips_HasDSP, // SHRA_R_W_MM = 2544 |
25786 | 0 | CEFBS_HasDSPR2, // SHRLV_PH = 2545 |
25787 | 0 | CEFBS_InMicroMips_HasDSPR2, // SHRLV_PH_MMR2 = 2546 |
25788 | 0 | CEFBS_HasDSP, // SHRLV_QB = 2547 |
25789 | 0 | CEFBS_InMicroMips_HasDSP, // SHRLV_QB_MM = 2548 |
25790 | 0 | CEFBS_HasDSPR2, // SHRL_PH = 2549 |
25791 | 0 | CEFBS_InMicroMips_HasDSPR2, // SHRL_PH_MMR2 = 2550 |
25792 | 0 | CEFBS_HasDSP, // SHRL_QB = 2551 |
25793 | 0 | CEFBS_InMicroMips_HasDSP, // SHRL_QB_MM = 2552 |
25794 | 0 | CEFBS_InMicroMips, // SH_MM = 2553 |
25795 | 0 | CEFBS_InMicroMips_HasMips32r6, // SH_MMR6 = 2554 |
25796 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SIGRIE = 2555 |
25797 | 0 | CEFBS_InMicroMips_HasMips32r6, // SIGRIE_MMR6 = 2556 |
25798 | 0 | CEFBS_HasStdEnc_HasMSA, // SLDI_B = 2557 |
25799 | 0 | CEFBS_HasStdEnc_HasMSA, // SLDI_D = 2558 |
25800 | 0 | CEFBS_HasStdEnc_HasMSA, // SLDI_H = 2559 |
25801 | 0 | CEFBS_HasStdEnc_HasMSA, // SLDI_W = 2560 |
25802 | 0 | CEFBS_HasStdEnc_HasMSA, // SLD_B = 2561 |
25803 | 0 | CEFBS_HasStdEnc_HasMSA, // SLD_D = 2562 |
25804 | 0 | CEFBS_HasStdEnc_HasMSA, // SLD_H = 2563 |
25805 | 0 | CEFBS_HasStdEnc_HasMSA, // SLD_W = 2564 |
25806 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLL = 2565 |
25807 | 0 | CEFBS_InMicroMips_NotMips32r6, // SLL16_MM = 2566 |
25808 | 0 | CEFBS_InMicroMips_HasMips32r6, // SLL16_MMR6 = 2567 |
25809 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_32 = 2568 |
25810 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SLL64_64 = 2569 |
25811 | 0 | CEFBS_HasStdEnc_HasMSA, // SLLI_B = 2570 |
25812 | 0 | CEFBS_HasStdEnc_HasMSA, // SLLI_D = 2571 |
25813 | 0 | CEFBS_HasStdEnc_HasMSA, // SLLI_H = 2572 |
25814 | 0 | CEFBS_HasStdEnc_HasMSA, // SLLI_W = 2573 |
25815 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLLV = 2574 |
25816 | 0 | CEFBS_InMicroMips, // SLLV_MM = 2575 |
25817 | 0 | CEFBS_HasStdEnc_HasMSA, // SLL_B = 2576 |
25818 | 0 | CEFBS_HasStdEnc_HasMSA, // SLL_D = 2577 |
25819 | 0 | CEFBS_HasStdEnc_HasMSA, // SLL_H = 2578 |
25820 | 0 | CEFBS_InMicroMips, // SLL_MM = 2579 |
25821 | 0 | CEFBS_InMicroMips_HasMips32r6, // SLL_MMR6 = 2580 |
25822 | 0 | CEFBS_HasStdEnc_HasMSA, // SLL_W = 2581 |
25823 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLT = 2582 |
25824 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SLT64 = 2583 |
25825 | 0 | CEFBS_InMicroMips, // SLT_MM = 2584 |
25826 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLTi = 2585 |
25827 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTi64 = 2586 |
25828 | 0 | CEFBS_InMicroMips, // SLTi_MM = 2587 |
25829 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLTiu = 2588 |
25830 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTiu64 = 2589 |
25831 | 0 | CEFBS_InMicroMips, // SLTiu_MM = 2590 |
25832 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SLTu = 2591 |
25833 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SLTu64 = 2592 |
25834 | 0 | CEFBS_InMicroMips, // SLTu_MM = 2593 |
25835 | 0 | CEFBS_HasCnMips, // SNE = 2594 |
25836 | 0 | CEFBS_HasCnMips, // SNEi = 2595 |
25837 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLATI_B = 2596 |
25838 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLATI_D = 2597 |
25839 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLATI_H = 2598 |
25840 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLATI_W = 2599 |
25841 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLAT_B = 2600 |
25842 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLAT_D = 2601 |
25843 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLAT_H = 2602 |
25844 | 0 | CEFBS_HasStdEnc_HasMSA, // SPLAT_W = 2603 |
25845 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SRA = 2604 |
25846 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAI_B = 2605 |
25847 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAI_D = 2606 |
25848 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAI_H = 2607 |
25849 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAI_W = 2608 |
25850 | 0 | CEFBS_HasStdEnc_HasMSA, // SRARI_B = 2609 |
25851 | 0 | CEFBS_HasStdEnc_HasMSA, // SRARI_D = 2610 |
25852 | 0 | CEFBS_HasStdEnc_HasMSA, // SRARI_H = 2611 |
25853 | 0 | CEFBS_HasStdEnc_HasMSA, // SRARI_W = 2612 |
25854 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAR_B = 2613 |
25855 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAR_D = 2614 |
25856 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAR_H = 2615 |
25857 | 0 | CEFBS_HasStdEnc_HasMSA, // SRAR_W = 2616 |
25858 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SRAV = 2617 |
25859 | 0 | CEFBS_InMicroMips, // SRAV_MM = 2618 |
25860 | 0 | CEFBS_HasStdEnc_HasMSA, // SRA_B = 2619 |
25861 | 0 | CEFBS_HasStdEnc_HasMSA, // SRA_D = 2620 |
25862 | 0 | CEFBS_HasStdEnc_HasMSA, // SRA_H = 2621 |
25863 | 0 | CEFBS_InMicroMips, // SRA_MM = 2622 |
25864 | 0 | CEFBS_HasStdEnc_HasMSA, // SRA_W = 2623 |
25865 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SRL = 2624 |
25866 | 0 | CEFBS_InMicroMips_NotMips32r6, // SRL16_MM = 2625 |
25867 | 0 | CEFBS_InMicroMips_HasMips32r6, // SRL16_MMR6 = 2626 |
25868 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLI_B = 2627 |
25869 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLI_D = 2628 |
25870 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLI_H = 2629 |
25871 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLI_W = 2630 |
25872 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLRI_B = 2631 |
25873 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLRI_D = 2632 |
25874 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLRI_H = 2633 |
25875 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLRI_W = 2634 |
25876 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLR_B = 2635 |
25877 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLR_D = 2636 |
25878 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLR_H = 2637 |
25879 | 0 | CEFBS_HasStdEnc_HasMSA, // SRLR_W = 2638 |
25880 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SRLV = 2639 |
25881 | 0 | CEFBS_InMicroMips, // SRLV_MM = 2640 |
25882 | 0 | CEFBS_HasStdEnc_HasMSA, // SRL_B = 2641 |
25883 | 0 | CEFBS_HasStdEnc_HasMSA, // SRL_D = 2642 |
25884 | 0 | CEFBS_HasStdEnc_HasMSA, // SRL_H = 2643 |
25885 | 0 | CEFBS_InMicroMips, // SRL_MM = 2644 |
25886 | 0 | CEFBS_HasStdEnc_HasMSA, // SRL_W = 2645 |
25887 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SSNOP = 2646 |
25888 | 0 | CEFBS_InMicroMips, // SSNOP_MM = 2647 |
25889 | 0 | CEFBS_InMicroMips_HasMips32r6, // SSNOP_MMR6 = 2648 |
25890 | 0 | CEFBS_HasStdEnc_HasMSA, // ST_B = 2649 |
25891 | 0 | CEFBS_HasStdEnc_HasMSA, // ST_D = 2650 |
25892 | 0 | CEFBS_HasStdEnc_HasMSA, // ST_H = 2651 |
25893 | 0 | CEFBS_HasStdEnc_HasMSA, // ST_W = 2652 |
25894 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SUB = 2653 |
25895 | 0 | CEFBS_HasDSPR2, // SUBQH_PH = 2654 |
25896 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_PH_MMR2 = 2655 |
25897 | 0 | CEFBS_HasDSPR2, // SUBQH_R_PH = 2656 |
25898 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_PH_MMR2 = 2657 |
25899 | 0 | CEFBS_HasDSPR2, // SUBQH_R_W = 2658 |
25900 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_R_W_MMR2 = 2659 |
25901 | 0 | CEFBS_HasDSPR2, // SUBQH_W = 2660 |
25902 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBQH_W_MMR2 = 2661 |
25903 | 0 | CEFBS_HasDSP, // SUBQ_PH = 2662 |
25904 | 0 | CEFBS_InMicroMips_HasDSP, // SUBQ_PH_MM = 2663 |
25905 | 0 | CEFBS_HasDSP, // SUBQ_S_PH = 2664 |
25906 | 0 | CEFBS_InMicroMips_HasDSP, // SUBQ_S_PH_MM = 2665 |
25907 | 0 | CEFBS_HasDSP, // SUBQ_S_W = 2666 |
25908 | 0 | CEFBS_InMicroMips_HasDSP, // SUBQ_S_W_MM = 2667 |
25909 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_B = 2668 |
25910 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_D = 2669 |
25911 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_H = 2670 |
25912 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUS_U_W = 2671 |
25913 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_B = 2672 |
25914 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_D = 2673 |
25915 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_H = 2674 |
25916 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBSUU_S_W = 2675 |
25917 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_B = 2676 |
25918 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_D = 2677 |
25919 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_H = 2678 |
25920 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_S_W = 2679 |
25921 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_B = 2680 |
25922 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_D = 2681 |
25923 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_H = 2682 |
25924 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBS_U_W = 2683 |
25925 | 0 | CEFBS_InMicroMips_NotMips32r6, // SUBU16_MM = 2684 |
25926 | 0 | CEFBS_InMicroMips_HasMips32r6, // SUBU16_MMR6 = 2685 |
25927 | 0 | CEFBS_HasDSPR2, // SUBUH_QB = 2686 |
25928 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBUH_QB_MMR2 = 2687 |
25929 | 0 | CEFBS_HasDSPR2, // SUBUH_R_QB = 2688 |
25930 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBUH_R_QB_MMR2 = 2689 |
25931 | 0 | CEFBS_InMicroMips_HasMips32r6, // SUBU_MMR6 = 2690 |
25932 | 0 | CEFBS_HasDSPR2, // SUBU_PH = 2691 |
25933 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBU_PH_MMR2 = 2692 |
25934 | 0 | CEFBS_HasDSP, // SUBU_QB = 2693 |
25935 | 0 | CEFBS_InMicroMips_HasDSP, // SUBU_QB_MM = 2694 |
25936 | 0 | CEFBS_HasDSPR2, // SUBU_S_PH = 2695 |
25937 | 0 | CEFBS_InMicroMips_HasDSPR2, // SUBU_S_PH_MMR2 = 2696 |
25938 | 0 | CEFBS_HasDSP, // SUBU_S_QB = 2697 |
25939 | 0 | CEFBS_InMicroMips_HasDSP, // SUBU_S_QB_MM = 2698 |
25940 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBVI_B = 2699 |
25941 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBVI_D = 2700 |
25942 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBVI_H = 2701 |
25943 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBVI_W = 2702 |
25944 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBV_B = 2703 |
25945 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBV_D = 2704 |
25946 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBV_H = 2705 |
25947 | 0 | CEFBS_HasStdEnc_HasMSA, // SUBV_W = 2706 |
25948 | 0 | CEFBS_InMicroMips_NotMips32r6, // SUB_MM = 2707 |
25949 | 0 | CEFBS_InMicroMips_HasMips32r6, // SUB_MMR6 = 2708 |
25950 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SUBu = 2709 |
25951 | 0 | CEFBS_InMicroMips_NotMips32r6, // SUBu_MM = 2710 |
25952 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC1 = 2711 |
25953 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips5_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat_NotInMicroMips, // SUXC164 = 2712 |
25954 | 0 | CEFBS_InMicroMips_IsFP64bit_NotMips32r6_IsNotSoftFloat, // SUXC1_MM = 2713 |
25955 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SW = 2714 |
25956 | 0 | CEFBS_InMicroMips_NotMips32r6, // SW16_MM = 2715 |
25957 | 0 | CEFBS_InMicroMips_HasMips32r6, // SW16_MMR6 = 2716 |
25958 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SW64 = 2717 |
25959 | 0 | CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // SWC1 = 2718 |
25960 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // SWC1_MM = 2719 |
25961 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWC2 = 2720 |
25962 | 0 | CEFBS_InMicroMips_HasMips32r6, // SWC2_MMR6 = 2721 |
25963 | 0 | CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // SWC2_R6 = 2722 |
25964 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotCnMips_NotInMicroMips, // SWC3 = 2723 |
25965 | 0 | CEFBS_NotInMips16Mode_HasDSP, // SWDSP = 2724 |
25966 | 0 | CEFBS_InMicroMips_HasDSP, // SWDSP_MM = 2725 |
25967 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // SWE = 2726 |
25968 | 0 | CEFBS_InMicroMips_HasEVA, // SWE_MM = 2727 |
25969 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWL = 2728 |
25970 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SWL64 = 2729 |
25971 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWLE = 2730 |
25972 | 0 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWLE_MM = 2731 |
25973 | 0 | CEFBS_InMicroMips_NotMips32r6, // SWL_MM = 2732 |
25974 | 0 | CEFBS_InMicroMips_NotMips32r6, // SWM16_MM = 2733 |
25975 | 0 | CEFBS_InMicroMips_HasMips32r6, // SWM16_MMR6 = 2734 |
25976 | 0 | CEFBS_InMicroMips, // SWM32_MM = 2735 |
25977 | 0 | CEFBS_InMicroMips, // SWP_MM = 2736 |
25978 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // SWR = 2737 |
25979 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // SWR64 = 2738 |
25980 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotMips32r6_NotMips64r6_HasEVA_NotInMicroMips, // SWRE = 2739 |
25981 | 0 | CEFBS_InMicroMips_NotMips32r6_HasEVA, // SWRE_MM = 2740 |
25982 | 0 | CEFBS_InMicroMips_NotMips32r6, // SWR_MM = 2741 |
25983 | 0 | CEFBS_InMicroMips_NotMips32r6, // SWSP_MM = 2742 |
25984 | 0 | CEFBS_InMicroMips_HasMips32r6, // SWSP_MMR6 = 2743 |
25985 | 0 | CEFBS_HasStdEnc_HasMips4_32r2_NotMips32r6_NotMips64r6_IsNotSoftFloat, // SWXC1 = 2744 |
25986 | 0 | CEFBS_InMicroMips_NotMips32r6_IsNotSoftFloat, // SWXC1_MM = 2745 |
25987 | 0 | CEFBS_InMicroMips, // SW_MM = 2746 |
25988 | 0 | CEFBS_InMicroMips_HasMips32r6, // SW_MMR6 = 2747 |
25989 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // SYNC = 2748 |
25990 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // SYNCI = 2749 |
25991 | 0 | CEFBS_InMicroMips_NotMips32r6, // SYNCI_MM = 2750 |
25992 | 0 | CEFBS_InMicroMips_HasMips32r6, // SYNCI_MMR6 = 2751 |
25993 | 0 | CEFBS_InMicroMips, // SYNC_MM = 2752 |
25994 | 0 | CEFBS_InMicroMips_HasMips32r6, // SYNC_MMR6 = 2753 |
25995 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // SYSCALL = 2754 |
25996 | 0 | CEFBS_InMicroMips, // SYSCALL_MM = 2755 |
25997 | 0 | CEFBS_InMips16Mode, // Save16 = 2756 |
25998 | 0 | CEFBS_InMips16Mode, // SaveX16 = 2757 |
25999 | 0 | CEFBS_InMips16Mode, // SbRxRyOffMemX16 = 2758 |
26000 | 0 | CEFBS_InMips16Mode, // SebRx16 = 2759 |
26001 | 0 | CEFBS_InMips16Mode, // SehRx16 = 2760 |
26002 | 0 | CEFBS_InMips16Mode, // ShRxRyOffMemX16 = 2761 |
26003 | 0 | CEFBS_InMips16Mode, // SllX16 = 2762 |
26004 | 0 | CEFBS_InMips16Mode, // SllvRxRy16 = 2763 |
26005 | 0 | CEFBS_InMips16Mode, // SltRxRy16 = 2764 |
26006 | 0 | CEFBS_InMips16Mode, // SltiRxImm16 = 2765 |
26007 | 0 | CEFBS_InMips16Mode, // SltiRxImmX16 = 2766 |
26008 | 0 | CEFBS_InMips16Mode, // SltiuRxImm16 = 2767 |
26009 | 0 | CEFBS_InMips16Mode, // SltiuRxImmX16 = 2768 |
26010 | 0 | CEFBS_InMips16Mode, // SltuRxRy16 = 2769 |
26011 | 0 | CEFBS_InMips16Mode, // SraX16 = 2770 |
26012 | 0 | CEFBS_InMips16Mode, // SravRxRy16 = 2771 |
26013 | 0 | CEFBS_InMips16Mode, // SrlX16 = 2772 |
26014 | 0 | CEFBS_InMips16Mode, // SrlvRxRy16 = 2773 |
26015 | 0 | CEFBS_InMips16Mode, // SubuRxRyRz16 = 2774 |
26016 | 0 | CEFBS_InMips16Mode, // SwRxRyOffMemX16 = 2775 |
26017 | 0 | CEFBS_InMips16Mode, // SwRxSpImmX16 = 2776 |
26018 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TEQ = 2777 |
26019 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TEQI = 2778 |
26020 | 0 | CEFBS_InMicroMips_NotMips32r6, // TEQI_MM = 2779 |
26021 | 0 | CEFBS_InMicroMips, // TEQ_MM = 2780 |
26022 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGE = 2781 |
26023 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEI = 2782 |
26024 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TGEIU = 2783 |
26025 | 0 | CEFBS_InMicroMips_NotMips32r6, // TGEIU_MM = 2784 |
26026 | 0 | CEFBS_InMicroMips_NotMips32r6, // TGEI_MM = 2785 |
26027 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TGEU = 2786 |
26028 | 0 | CEFBS_InMicroMips, // TGEU_MM = 2787 |
26029 | 0 | CEFBS_InMicroMips, // TGE_MM = 2788 |
26030 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINV = 2789 |
26031 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGINVF = 2790 |
26032 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINVF_MM = 2791 |
26033 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGINV_MM = 2792 |
26034 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGP = 2793 |
26035 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGP_MM = 2794 |
26036 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGR = 2795 |
26037 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGR_MM = 2796 |
26038 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWI = 2797 |
26039 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWI_MM = 2798 |
26040 | 0 | CEFBS_HasStdEnc_HasMips32r5_HasVirt_NotInMicroMips, // TLBGWR = 2799 |
26041 | 0 | CEFBS_InMicroMips_HasMips32r5_HasVirt, // TLBGWR_MM = 2800 |
26042 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINV = 2801 |
26043 | 0 | CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // TLBINVF = 2802 |
26044 | 0 | CEFBS_InMicroMips_HasMips32r6, // TLBINVF_MMR6 = 2803 |
26045 | 0 | CEFBS_InMicroMips_HasMips32r6, // TLBINV_MMR6 = 2804 |
26046 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // TLBP = 2805 |
26047 | 0 | CEFBS_InMicroMips, // TLBP_MM = 2806 |
26048 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // TLBR = 2807 |
26049 | 0 | CEFBS_InMicroMips, // TLBR_MM = 2808 |
26050 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // TLBWI = 2809 |
26051 | 0 | CEFBS_InMicroMips, // TLBWI_MM = 2810 |
26052 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // TLBWR = 2811 |
26053 | 0 | CEFBS_InMicroMips, // TLBWR_MM = 2812 |
26054 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLT = 2813 |
26055 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TLTI = 2814 |
26056 | 0 | CEFBS_InMicroMips_NotMips32r6, // TLTIU_MM = 2815 |
26057 | 0 | CEFBS_InMicroMips_NotMips32r6, // TLTI_MM = 2816 |
26058 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TLTU = 2817 |
26059 | 0 | CEFBS_InMicroMips, // TLTU_MM = 2818 |
26060 | 0 | CEFBS_InMicroMips, // TLT_MM = 2819 |
26061 | 0 | CEFBS_HasStdEnc_HasMips2_NotInMicroMips, // TNE = 2820 |
26062 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TNEI = 2821 |
26063 | 0 | CEFBS_InMicroMips_NotMips32r6, // TNEI_MM = 2822 |
26064 | 0 | CEFBS_InMicroMips, // TNE_MM = 2823 |
26065 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips3_32_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_D64 = 2824 |
26066 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_D_MMR6 = 2825 |
26067 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_L_S = 2826 |
26068 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_L_S_MMR6 = 2827 |
26069 | 0 | CEFBS_HasStdEnc_NotFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D32 = 2828 |
26070 | 0 | CEFBS_HasStdEnc_IsFP64bit_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_D64 = 2829 |
26071 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_D_MMR6 = 2830 |
26072 | 0 | CEFBS_InMicroMips_NotFP64bit_IsNotSoftFloat, // TRUNC_W_MM = 2831 |
26073 | 0 | CEFBS_HasStdEnc_HasMips2_IsNotSoftFloat_NotInMicroMips, // TRUNC_W_S = 2832 |
26074 | 0 | CEFBS_InMicroMips_IsNotSoftFloat, // TRUNC_W_S_MM = 2833 |
26075 | 0 | CEFBS_InMicroMips_HasMips32r6_IsNotSoftFloat, // TRUNC_W_S_MMR6 = 2834 |
26076 | 0 | CEFBS_HasStdEnc_HasMips2_NotMips32r6_NotMips64r6_NotInMicroMips, // TTLTIU = 2835 |
26077 | 0 | CEFBS_HasStdEnc_NotMips32r6_NotMips64r6_NotInMicroMips, // UDIV = 2836 |
26078 | 0 | CEFBS_InMicroMips_NotMips32r6, // UDIV_MM = 2837 |
26079 | 0 | CEFBS_HasCnMips, // V3MULU = 2838 |
26080 | 0 | CEFBS_HasCnMips, // VMM0 = 2839 |
26081 | 0 | CEFBS_HasCnMips, // VMULU = 2840 |
26082 | 0 | CEFBS_HasStdEnc_HasMSA, // VSHF_B = 2841 |
26083 | 0 | CEFBS_HasStdEnc_HasMSA, // VSHF_D = 2842 |
26084 | 0 | CEFBS_HasStdEnc_HasMSA, // VSHF_H = 2843 |
26085 | 0 | CEFBS_HasStdEnc_HasMSA, // VSHF_W = 2844 |
26086 | 0 | CEFBS_HasStdEnc_HasMips3_32_NotInMicroMips, // WAIT = 2845 |
26087 | 0 | CEFBS_InMicroMips, // WAIT_MM = 2846 |
26088 | 0 | CEFBS_InMicroMips_HasMips32r6, // WAIT_MMR6 = 2847 |
26089 | 0 | CEFBS_HasDSP_NotInMicroMips, // WRDSP = 2848 |
26090 | 0 | CEFBS_InMicroMips_HasDSP, // WRDSP_MM = 2849 |
26091 | 0 | CEFBS_InMicroMips_HasMips32r6, // WRPGPR_MMR6 = 2850 |
26092 | 0 | CEFBS_HasStdEnc_HasMips32r2_NotInMicroMips, // WSBH = 2851 |
26093 | 0 | CEFBS_InMicroMips, // WSBH_MM = 2852 |
26094 | 0 | CEFBS_InMicroMips_HasMips32r6, // WSBH_MMR6 = 2853 |
26095 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // XOR = 2854 |
26096 | 0 | CEFBS_InMicroMips_NotMips32r6, // XOR16_MM = 2855 |
26097 | 0 | CEFBS_InMicroMips_HasMips32r6, // XOR16_MMR6 = 2856 |
26098 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // XOR64 = 2857 |
26099 | 0 | CEFBS_HasStdEnc_HasMSA, // XORI_B = 2858 |
26100 | 0 | CEFBS_InMicroMips_HasMips32r6, // XORI_MMR6 = 2859 |
26101 | 0 | CEFBS_InMicroMips_NotMips32r6, // XOR_MM = 2860 |
26102 | 0 | CEFBS_InMicroMips_HasMips32r6, // XOR_MMR6 = 2861 |
26103 | 0 | CEFBS_HasStdEnc_HasMSA, // XOR_V = 2862 |
26104 | 0 | CEFBS_HasStdEnc_NotInMicroMips, // XORi = 2863 |
26105 | 0 | CEFBS_NotInMips16Mode_IsGP64bit, // XORi64 = 2864 |
26106 | 0 | CEFBS_InMicroMips_NotMips32r6, // XORi_MM = 2865 |
26107 | 0 | CEFBS_InMips16Mode, // XorRxRxRy16 = 2866 |
26108 | 0 | CEFBS_HasStdEnc_HasMT_NotInMicroMips, // YIELD = 2867 |
26109 | 0 | }; |
26110 | |
|
26111 | 0 | assert(Opcode < 2868); |
26112 | 0 | return FeatureBitsets[RequiredFeaturesRefs[Opcode]]; |
26113 | 0 | } |
26114 | | |
26115 | | } // end namespace Mips_MC |
26116 | | } // end namespace llvm |
26117 | | #endif // GET_COMPUTE_FEATURES |
26118 | | |
26119 | | #ifdef GET_AVAILABLE_OPCODE_CHECKER |
26120 | | #undef GET_AVAILABLE_OPCODE_CHECKER |
26121 | | namespace llvm { |
26122 | | namespace Mips_MC { |
26123 | | bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) { |
26124 | | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
26125 | | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
26126 | | FeatureBitset MissingFeatures = |
26127 | | (AvailableFeatures & RequiredFeatures) ^ |
26128 | | RequiredFeatures; |
26129 | | return !MissingFeatures.any(); |
26130 | | } |
26131 | | } // end namespace Mips_MC |
26132 | | } // end namespace llvm |
26133 | | #endif // GET_AVAILABLE_OPCODE_CHECKER |
26134 | | |
26135 | | #ifdef ENABLE_INSTR_PREDICATE_VERIFIER |
26136 | | #undef ENABLE_INSTR_PREDICATE_VERIFIER |
26137 | | #include <sstream> |
26138 | | |
26139 | | namespace llvm { |
26140 | | namespace Mips_MC { |
26141 | | |
26142 | | #ifndef NDEBUG |
26143 | | static const char *SubtargetFeatureNames[] = { |
26144 | | "Feature_HasCRC", |
26145 | | "Feature_HasCnMips", |
26146 | | "Feature_HasCnMipsP", |
26147 | | "Feature_HasDSP", |
26148 | | "Feature_HasDSPR2", |
26149 | | "Feature_HasDSPR3", |
26150 | | "Feature_HasEVA", |
26151 | | "Feature_HasGINV", |
26152 | | "Feature_HasMSA", |
26153 | | "Feature_HasMT", |
26154 | | "Feature_HasMadd4", |
26155 | | "Feature_HasMips2", |
26156 | | "Feature_HasMips3", |
26157 | | "Feature_HasMips3D", |
26158 | | "Feature_HasMips3_32", |
26159 | | "Feature_HasMips3_32r2", |
26160 | | "Feature_HasMips4_32", |
26161 | | "Feature_HasMips4_32r2", |
26162 | | "Feature_HasMips5_32r2", |
26163 | | "Feature_HasMips32", |
26164 | | "Feature_HasMips32r2", |
26165 | | "Feature_HasMips32r5", |
26166 | | "Feature_HasMips32r6", |
26167 | | "Feature_HasMips64", |
26168 | | "Feature_HasMips64r2", |
26169 | | "Feature_HasMips64r5", |
26170 | | "Feature_HasMips64r6", |
26171 | | "Feature_HasStdEnc", |
26172 | | "Feature_HasVirt", |
26173 | | "Feature_InMicroMips", |
26174 | | "Feature_InMips16Mode", |
26175 | | "Feature_IsFP64bit", |
26176 | | "Feature_IsGP32bit", |
26177 | | "Feature_IsGP64bit", |
26178 | | "Feature_IsNotSingleFloat", |
26179 | | "Feature_IsNotSoftFloat", |
26180 | | "Feature_IsPTR32bit", |
26181 | | "Feature_IsPTR64bit", |
26182 | | "Feature_IsSingleFloat", |
26183 | | "Feature_IsSym32", |
26184 | | "Feature_IsSym64", |
26185 | | "Feature_NoIndirectJumpGuards", |
26186 | | "Feature_NotCnMips", |
26187 | | "Feature_NotCnMipsP", |
26188 | | "Feature_NotFP64bit", |
26189 | | "Feature_NotInMicroMips", |
26190 | | "Feature_NotInMips16Mode", |
26191 | | "Feature_NotMips3", |
26192 | | "Feature_NotMips4_32", |
26193 | | "Feature_NotMips32r6", |
26194 | | "Feature_NotMips64", |
26195 | | "Feature_NotMips64r6", |
26196 | | "Feature_UseIndirectJumpsHazard", |
26197 | | nullptr |
26198 | | }; |
26199 | | |
26200 | | #endif // NDEBUG |
26201 | | |
26202 | | void verifyInstructionPredicates( |
26203 | 0 | unsigned Opcode, const FeatureBitset &Features) { |
26204 | 0 | #ifndef NDEBUG |
26205 | 0 | FeatureBitset AvailableFeatures = computeAvailableFeatures(Features); |
26206 | 0 | FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode); |
26207 | 0 | FeatureBitset MissingFeatures = |
26208 | 0 | (AvailableFeatures & RequiredFeatures) ^ |
26209 | 0 | RequiredFeatures; |
26210 | 0 | if (MissingFeatures.any()) { |
26211 | 0 | std::ostringstream Msg; |
26212 | 0 | Msg << "Attempting to emit " << &MipsInstrNameData[MipsInstrNameIndices[Opcode]] |
26213 | 0 | << " instruction but the "; |
26214 | 0 | for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i) |
26215 | 0 | if (MissingFeatures.test(i)) |
26216 | 0 | Msg << SubtargetFeatureNames[i] << " "; |
26217 | 0 | Msg << "predicate(s) are not met"; |
26218 | 0 | report_fatal_error(Msg.str().c_str()); |
26219 | 0 | } |
26220 | 0 | #endif // NDEBUG |
26221 | 0 | } |
26222 | | } // end namespace Mips_MC |
26223 | | } // end namespace llvm |
26224 | | #endif // ENABLE_INSTR_PREDICATE_VERIFIER |
26225 | | |
26226 | | #ifdef GET_INSTRMAP_INFO |
26227 | | #undef GET_INSTRMAP_INFO |
26228 | | namespace llvm { |
26229 | | |
26230 | | namespace Mips { |
26231 | | |
26232 | | enum Arch { |
26233 | | Arch_dsp, |
26234 | | Arch_mmdsp, |
26235 | | Arch_mipsr6, |
26236 | | Arch_micromipsr6, |
26237 | | Arch_se, |
26238 | | Arch_micromips |
26239 | | }; |
26240 | | |
26241 | | // Dsp2MicroMips |
26242 | | LLVM_READONLY |
26243 | 0 | int Dsp2MicroMips(uint16_t Opcode, enum Arch inArch) { |
26244 | 0 | static const uint16_t Dsp2MicroMipsTable[][3] = { |
26245 | 0 | { Mips::ABSQ_S_PH, Mips::ABSQ_S_PH, Mips::ABSQ_S_PH_MM }, |
26246 | 0 | { Mips::ABSQ_S_QB, Mips::ABSQ_S_QB, Mips::ABSQ_S_QB_MMR2 }, |
26247 | 0 | { Mips::ABSQ_S_W, Mips::ABSQ_S_W, Mips::ABSQ_S_W_MM }, |
26248 | 0 | { Mips::ADDQH_PH, Mips::ADDQH_PH, Mips::ADDQH_PH_MMR2 }, |
26249 | 0 | { Mips::ADDQH_R_PH, Mips::ADDQH_R_PH, Mips::ADDQH_R_PH_MMR2 }, |
26250 | 0 | { Mips::ADDQH_R_W, Mips::ADDQH_R_W, Mips::ADDQH_R_W_MMR2 }, |
26251 | 0 | { Mips::ADDQH_W, Mips::ADDQH_W, Mips::ADDQH_W_MMR2 }, |
26252 | 0 | { Mips::ADDQ_PH, Mips::ADDQ_PH, Mips::ADDQ_PH_MM }, |
26253 | 0 | { Mips::ADDQ_S_PH, Mips::ADDQ_S_PH, Mips::ADDQ_S_PH_MM }, |
26254 | 0 | { Mips::ADDQ_S_W, Mips::ADDQ_S_W, Mips::ADDQ_S_W_MM }, |
26255 | 0 | { Mips::ADDSC, Mips::ADDSC, Mips::ADDSC_MM }, |
26256 | 0 | { Mips::ADDUH_QB, Mips::ADDUH_QB, Mips::ADDUH_QB_MMR2 }, |
26257 | 0 | { Mips::ADDUH_R_QB, Mips::ADDUH_R_QB, Mips::ADDUH_R_QB_MMR2 }, |
26258 | 0 | { Mips::ADDU_PH, Mips::ADDU_PH, Mips::ADDU_PH_MMR2 }, |
26259 | 0 | { Mips::ADDU_QB, Mips::ADDU_QB, Mips::ADDU_QB_MM }, |
26260 | 0 | { Mips::ADDU_S_PH, Mips::ADDU_S_PH, Mips::ADDU_S_PH_MMR2 }, |
26261 | 0 | { Mips::ADDU_S_QB, Mips::ADDU_S_QB, Mips::ADDU_S_QB_MM }, |
26262 | 0 | { Mips::ADDWC, Mips::ADDWC, Mips::ADDWC_MM }, |
26263 | 0 | { Mips::APPEND, Mips::APPEND, Mips::APPEND_MMR2 }, |
26264 | 0 | { Mips::BALIGN, Mips::BALIGN, Mips::BALIGN_MMR2 }, |
26265 | 0 | { Mips::BITREV, Mips::BITREV, Mips::BITREV_MM }, |
26266 | 0 | { Mips::BPOSGE32, Mips::BPOSGE32, Mips::BPOSGE32_MM }, |
26267 | 0 | { Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB, Mips::CMPGDU_EQ_QB_MMR2 }, |
26268 | 0 | { Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB, Mips::CMPGDU_LE_QB_MMR2 }, |
26269 | 0 | { Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB, Mips::CMPGDU_LT_QB_MMR2 }, |
26270 | 0 | { Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB, Mips::CMPGU_EQ_QB_MM }, |
26271 | 0 | { Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB, Mips::CMPGU_LE_QB_MM }, |
26272 | 0 | { Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB, Mips::CMPGU_LT_QB_MM }, |
26273 | 0 | { Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB, Mips::CMPU_EQ_QB_MM }, |
26274 | 0 | { Mips::CMPU_LE_QB, Mips::CMPU_LE_QB, Mips::CMPU_LE_QB_MM }, |
26275 | 0 | { Mips::CMPU_LT_QB, Mips::CMPU_LT_QB, Mips::CMPU_LT_QB_MM }, |
26276 | 0 | { Mips::CMP_EQ_PH, Mips::CMP_EQ_PH, Mips::CMP_EQ_PH_MM }, |
26277 | 0 | { Mips::CMP_LE_PH, Mips::CMP_LE_PH, Mips::CMP_LE_PH_MM }, |
26278 | 0 | { Mips::CMP_LT_PH, Mips::CMP_LT_PH, Mips::CMP_LT_PH_MM }, |
26279 | 0 | { Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH, Mips::DPAQX_SA_W_PH_MMR2 }, |
26280 | 0 | { Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH, Mips::DPAQX_S_W_PH_MMR2 }, |
26281 | 0 | { Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W, Mips::DPAQ_SA_L_W_MM }, |
26282 | 0 | { Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH, Mips::DPAQ_S_W_PH_MM }, |
26283 | 0 | { Mips::DPAU_H_QBL, Mips::DPAU_H_QBL, Mips::DPAU_H_QBL_MM }, |
26284 | 0 | { Mips::DPAU_H_QBR, Mips::DPAU_H_QBR, Mips::DPAU_H_QBR_MM }, |
26285 | 0 | { Mips::DPAX_W_PH, Mips::DPAX_W_PH, Mips::DPAX_W_PH_MMR2 }, |
26286 | 0 | { Mips::DPA_W_PH, Mips::DPA_W_PH, Mips::DPA_W_PH_MMR2 }, |
26287 | 0 | { Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH, Mips::DPSQX_SA_W_PH_MMR2 }, |
26288 | 0 | { Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH, Mips::DPSQX_S_W_PH_MMR2 }, |
26289 | 0 | { Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W, Mips::DPSQ_SA_L_W_MM }, |
26290 | 0 | { Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH, Mips::DPSQ_S_W_PH_MM }, |
26291 | 0 | { Mips::DPSU_H_QBL, Mips::DPSU_H_QBL, Mips::DPSU_H_QBL_MM }, |
26292 | 0 | { Mips::DPSU_H_QBR, Mips::DPSU_H_QBR, Mips::DPSU_H_QBR_MM }, |
26293 | 0 | { Mips::DPSX_W_PH, Mips::DPSX_W_PH, Mips::DPSX_W_PH_MMR2 }, |
26294 | 0 | { Mips::DPS_W_PH, Mips::DPS_W_PH, Mips::DPS_W_PH_MMR2 }, |
26295 | 0 | { Mips::EXTP, Mips::EXTP, Mips::EXTP_MM }, |
26296 | 0 | { Mips::EXTPDP, Mips::EXTPDP, Mips::EXTPDP_MM }, |
26297 | 0 | { Mips::EXTPDPV, Mips::EXTPDPV, Mips::EXTPDPV_MM }, |
26298 | 0 | { Mips::EXTPV, Mips::EXTPV, Mips::EXTPV_MM }, |
26299 | 0 | { Mips::EXTRV_RS_W, Mips::EXTRV_RS_W, Mips::EXTRV_RS_W_MM }, |
26300 | 0 | { Mips::EXTRV_R_W, Mips::EXTRV_R_W, Mips::EXTRV_R_W_MM }, |
26301 | 0 | { Mips::EXTRV_S_H, Mips::EXTRV_S_H, Mips::EXTRV_S_H_MM }, |
26302 | 0 | { Mips::EXTRV_W, Mips::EXTRV_W, Mips::EXTRV_W_MM }, |
26303 | 0 | { Mips::EXTR_RS_W, Mips::EXTR_RS_W, Mips::EXTR_RS_W_MM }, |
26304 | 0 | { Mips::EXTR_R_W, Mips::EXTR_R_W, Mips::EXTR_R_W_MM }, |
26305 | 0 | { Mips::EXTR_S_H, Mips::EXTR_S_H, Mips::EXTR_S_H_MM }, |
26306 | 0 | { Mips::EXTR_W, Mips::EXTR_W, Mips::EXTR_W_MM }, |
26307 | 0 | { Mips::INSV, Mips::INSV, Mips::INSV_MM }, |
26308 | 0 | { Mips::LBUX, Mips::LBUX, Mips::LBUX_MM }, |
26309 | 0 | { Mips::LHX, Mips::LHX, Mips::LHX_MM }, |
26310 | 0 | { Mips::LWDSP, Mips::LWDSP, Mips::LWDSP_MM }, |
26311 | 0 | { Mips::LWX, Mips::LWX, Mips::LWX_MM }, |
26312 | 0 | { Mips::MADDU_DSP, Mips::MADDU_DSP, Mips::MADDU_DSP_MM }, |
26313 | 0 | { Mips::MADD_DSP, Mips::MADD_DSP, Mips::MADD_DSP_MM }, |
26314 | 0 | { Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL, Mips::MAQ_SA_W_PHL_MM }, |
26315 | 0 | { Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR, Mips::MAQ_SA_W_PHR_MM }, |
26316 | 0 | { Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL, Mips::MAQ_S_W_PHL_MM }, |
26317 | 0 | { Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR, Mips::MAQ_S_W_PHR_MM }, |
26318 | 0 | { Mips::MFHI_DSP, Mips::MFHI_DSP, Mips::MFHI_DSP_MM }, |
26319 | 0 | { Mips::MFLO_DSP, Mips::MFLO_DSP, Mips::MFLO_DSP_MM }, |
26320 | 0 | { Mips::MODSUB, Mips::MODSUB, Mips::MODSUB_MM }, |
26321 | 0 | { Mips::MSUBU_DSP, Mips::MSUBU_DSP, Mips::MSUBU_DSP_MM }, |
26322 | 0 | { Mips::MSUB_DSP, Mips::MSUB_DSP, Mips::MSUB_DSP_MM }, |
26323 | 0 | { Mips::MTHI_DSP, Mips::MTHI_DSP, Mips::MTHI_DSP_MM }, |
26324 | 0 | { Mips::MTHLIP, Mips::MTHLIP, Mips::MTHLIP_MM }, |
26325 | 0 | { Mips::MTLO_DSP, Mips::MTLO_DSP, Mips::MTLO_DSP_MM }, |
26326 | 0 | { Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL, Mips::MULEQ_S_W_PHL_MM }, |
26327 | 0 | { Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR, Mips::MULEQ_S_W_PHR_MM }, |
26328 | 0 | { Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL, Mips::MULEU_S_PH_QBL_MM }, |
26329 | 0 | { Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR, Mips::MULEU_S_PH_QBR_MM }, |
26330 | 0 | { Mips::MULQ_RS_PH, Mips::MULQ_RS_PH, Mips::MULQ_RS_PH_MM }, |
26331 | 0 | { Mips::MULQ_RS_W, Mips::MULQ_RS_W, Mips::MULQ_RS_W_MMR2 }, |
26332 | 0 | { Mips::MULQ_S_PH, Mips::MULQ_S_PH, Mips::MULQ_S_PH_MMR2 }, |
26333 | 0 | { Mips::MULQ_S_W, Mips::MULQ_S_W, Mips::MULQ_S_W_MMR2 }, |
26334 | 0 | { Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH, Mips::MULSAQ_S_W_PH_MM }, |
26335 | 0 | { Mips::MULSA_W_PH, Mips::MULSA_W_PH, Mips::MULSA_W_PH_MMR2 }, |
26336 | 0 | { Mips::MULTU_DSP, Mips::MULTU_DSP, Mips::MULTU_DSP_MM }, |
26337 | 0 | { Mips::MULT_DSP, Mips::MULT_DSP, Mips::MULT_DSP_MM }, |
26338 | 0 | { Mips::MUL_PH, Mips::MUL_PH, Mips::MUL_PH_MMR2 }, |
26339 | 0 | { Mips::MUL_S_PH, Mips::MUL_S_PH, Mips::MUL_S_PH_MMR2 }, |
26340 | 0 | { Mips::PACKRL_PH, Mips::PACKRL_PH, Mips::PACKRL_PH_MM }, |
26341 | 0 | { Mips::PICK_PH, Mips::PICK_PH, Mips::PICK_PH_MM }, |
26342 | 0 | { Mips::PICK_QB, Mips::PICK_QB, Mips::PICK_QB_MM }, |
26343 | 0 | { Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL, Mips::PRECEQU_PH_QBL_MM }, |
26344 | 0 | { Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA, Mips::PRECEQU_PH_QBLA_MM }, |
26345 | 0 | { Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR, Mips::PRECEQU_PH_QBR_MM }, |
26346 | 0 | { Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA, Mips::PRECEQU_PH_QBRA_MM }, |
26347 | 0 | { Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL, Mips::PRECEQ_W_PHL_MM }, |
26348 | 0 | { Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR, Mips::PRECEQ_W_PHR_MM }, |
26349 | 0 | { Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL, Mips::PRECEU_PH_QBL_MM }, |
26350 | 0 | { Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA, Mips::PRECEU_PH_QBLA_MM }, |
26351 | 0 | { Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR, Mips::PRECEU_PH_QBR_MM }, |
26352 | 0 | { Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA, Mips::PRECEU_PH_QBRA_MM }, |
26353 | 0 | { Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH, Mips::PRECRQU_S_QB_PH_MM }, |
26354 | 0 | { Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W, Mips::PRECRQ_PH_W_MM }, |
26355 | 0 | { Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH, Mips::PRECRQ_QB_PH_MM }, |
26356 | 0 | { Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W, Mips::PRECRQ_RS_PH_W_MM }, |
26357 | 0 | { Mips::PRECR_QB_PH, Mips::PRECR_QB_PH, Mips::PRECR_QB_PH_MMR2 }, |
26358 | 0 | { Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W, Mips::PRECR_SRA_PH_W_MMR2 }, |
26359 | 0 | { Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W, Mips::PRECR_SRA_R_PH_W_MMR2 }, |
26360 | 0 | { Mips::PREPEND, Mips::PREPEND, Mips::PREPEND_MMR2 }, |
26361 | 0 | { Mips::RADDU_W_QB, Mips::RADDU_W_QB, Mips::RADDU_W_QB_MM }, |
26362 | 0 | { Mips::RDDSP, Mips::RDDSP, Mips::RDDSP_MM }, |
26363 | 0 | { Mips::REPLV_PH, Mips::REPLV_PH, Mips::REPLV_PH_MM }, |
26364 | 0 | { Mips::REPLV_QB, Mips::REPLV_QB, Mips::REPLV_QB_MM }, |
26365 | 0 | { Mips::REPL_PH, Mips::REPL_PH, Mips::REPL_PH_MM }, |
26366 | 0 | { Mips::REPL_QB, Mips::REPL_QB, Mips::REPL_QB_MM }, |
26367 | 0 | { Mips::SHILO, Mips::SHILO, Mips::SHILO_MM }, |
26368 | 0 | { Mips::SHILOV, Mips::SHILOV, Mips::SHILOV_MM }, |
26369 | 0 | { Mips::SHLLV_PH, Mips::SHLLV_PH, Mips::SHLLV_PH_MM }, |
26370 | 0 | { Mips::SHLLV_QB, Mips::SHLLV_QB, Mips::SHLLV_QB_MM }, |
26371 | 0 | { Mips::SHLLV_S_PH, Mips::SHLLV_S_PH, Mips::SHLLV_S_PH_MM }, |
26372 | 0 | { Mips::SHLLV_S_W, Mips::SHLLV_S_W, Mips::SHLLV_S_W_MM }, |
26373 | 0 | { Mips::SHLL_PH, Mips::SHLL_PH, Mips::SHLL_PH_MM }, |
26374 | 0 | { Mips::SHLL_QB, Mips::SHLL_QB, Mips::SHLL_QB_MM }, |
26375 | 0 | { Mips::SHLL_S_PH, Mips::SHLL_S_PH, Mips::SHLL_S_PH_MM }, |
26376 | 0 | { Mips::SHLL_S_W, Mips::SHLL_S_W, Mips::SHLL_S_W_MM }, |
26377 | 0 | { Mips::SHRAV_PH, Mips::SHRAV_PH, Mips::SHRAV_PH_MM }, |
26378 | 0 | { Mips::SHRAV_QB, Mips::SHRAV_QB, Mips::SHRAV_QB_MMR2 }, |
26379 | 0 | { Mips::SHRAV_R_PH, Mips::SHRAV_R_PH, Mips::SHRAV_R_PH_MM }, |
26380 | 0 | { Mips::SHRAV_R_QB, Mips::SHRAV_R_QB, Mips::SHRAV_R_QB_MMR2 }, |
26381 | 0 | { Mips::SHRAV_R_W, Mips::SHRAV_R_W, Mips::SHRAV_R_W_MM }, |
26382 | 0 | { Mips::SHRA_PH, Mips::SHRA_PH, Mips::SHRA_PH_MM }, |
26383 | 0 | { Mips::SHRA_QB, Mips::SHRA_QB, Mips::SHRA_QB_MMR2 }, |
26384 | 0 | { Mips::SHRA_R_PH, Mips::SHRA_R_PH, Mips::SHRA_R_PH_MM }, |
26385 | 0 | { Mips::SHRA_R_QB, Mips::SHRA_R_QB, Mips::SHRA_R_QB_MMR2 }, |
26386 | 0 | { Mips::SHRA_R_W, Mips::SHRA_R_W, Mips::SHRA_R_W_MM }, |
26387 | 0 | { Mips::SHRLV_PH, Mips::SHRLV_PH, Mips::SHRLV_PH_MMR2 }, |
26388 | 0 | { Mips::SHRLV_QB, Mips::SHRLV_QB, Mips::SHRLV_QB_MM }, |
26389 | 0 | { Mips::SHRL_PH, Mips::SHRL_PH, Mips::SHRL_PH_MMR2 }, |
26390 | 0 | { Mips::SHRL_QB, Mips::SHRL_QB, Mips::SHRL_QB_MM }, |
26391 | 0 | { Mips::SUBQH_PH, Mips::SUBQH_PH, Mips::SUBQH_PH_MMR2 }, |
26392 | 0 | { Mips::SUBQH_R_PH, Mips::SUBQH_R_PH, Mips::SUBQH_R_PH_MMR2 }, |
26393 | 0 | { Mips::SUBQH_R_W, Mips::SUBQH_R_W, Mips::SUBQH_R_W_MMR2 }, |
26394 | 0 | { Mips::SUBQH_W, Mips::SUBQH_W, Mips::SUBQH_W_MMR2 }, |
26395 | 0 | { Mips::SUBQ_PH, Mips::SUBQ_PH, Mips::SUBQ_PH_MM }, |
26396 | 0 | { Mips::SUBQ_S_PH, Mips::SUBQ_S_PH, Mips::SUBQ_S_PH_MM }, |
26397 | 0 | { Mips::SUBQ_S_W, Mips::SUBQ_S_W, Mips::SUBQ_S_W_MM }, |
26398 | 0 | { Mips::SUBUH_QB, Mips::SUBUH_QB, Mips::SUBUH_QB_MMR2 }, |
26399 | 0 | { Mips::SUBUH_R_QB, Mips::SUBUH_R_QB, Mips::SUBUH_R_QB_MMR2 }, |
26400 | 0 | { Mips::SUBU_PH, Mips::SUBU_PH, Mips::SUBU_PH_MMR2 }, |
26401 | 0 | { Mips::SUBU_QB, Mips::SUBU_QB, Mips::SUBU_QB_MM }, |
26402 | 0 | { Mips::SUBU_S_PH, Mips::SUBU_S_PH, Mips::SUBU_S_PH_MMR2 }, |
26403 | 0 | { Mips::SUBU_S_QB, Mips::SUBU_S_QB, Mips::SUBU_S_QB_MM }, |
26404 | 0 | { Mips::SWDSP, Mips::SWDSP, Mips::SWDSP_MM }, |
26405 | 0 | }; // End of Dsp2MicroMipsTable |
26406 | |
|
26407 | 0 | unsigned mid; |
26408 | 0 | unsigned start = 0; |
26409 | 0 | unsigned end = 160; |
26410 | 0 | while (start < end) { |
26411 | 0 | mid = start + (end - start) / 2; |
26412 | 0 | if (Opcode == Dsp2MicroMipsTable[mid][0]) { |
26413 | 0 | break; |
26414 | 0 | } |
26415 | 0 | if (Opcode < Dsp2MicroMipsTable[mid][0]) |
26416 | 0 | end = mid; |
26417 | 0 | else |
26418 | 0 | start = mid + 1; |
26419 | 0 | } |
26420 | 0 | if (start == end) |
26421 | 0 | return -1; // Instruction doesn't exist in this table. |
26422 | | |
26423 | 0 | if (inArch == Arch_dsp) |
26424 | 0 | return Dsp2MicroMipsTable[mid][1]; |
26425 | 0 | if (inArch == Arch_mmdsp) |
26426 | 0 | return Dsp2MicroMipsTable[mid][2]; |
26427 | 0 | return -1;} |
26428 | | |
26429 | | // MipsR62MicroMipsR6 |
26430 | | LLVM_READONLY |
26431 | 0 | int MipsR62MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
26432 | 0 | static const uint16_t MipsR62MicroMipsR6Table[][3] = { |
26433 | 0 | { Mips::ADDIUPC, Mips::ADDIUPC, Mips::ADDIUPC_MMR6 }, |
26434 | 0 | { Mips::ALIGN, Mips::ALIGN, Mips::ALIGN_MMR6 }, |
26435 | 0 | { Mips::ALUIPC, Mips::ALUIPC, Mips::ALUIPC_MMR6 }, |
26436 | 0 | { Mips::AUI, Mips::AUI, Mips::AUI_MMR6 }, |
26437 | 0 | { Mips::AUIPC, Mips::AUIPC, Mips::AUIPC_MMR6 }, |
26438 | 0 | { Mips::BALC, Mips::BALC, Mips::BALC_MMR6 }, |
26439 | 0 | { Mips::BC, Mips::BC, Mips::BC_MMR6 }, |
26440 | 0 | { Mips::BEQC, Mips::BEQC, Mips::BEQC_MMR6 }, |
26441 | 0 | { Mips::BEQZALC, Mips::BEQZALC, Mips::BEQZALC_MMR6 }, |
26442 | 0 | { Mips::BEQZC, Mips::BEQZC, Mips::BEQZC_MMR6 }, |
26443 | 0 | { Mips::BGEC, Mips::BGEC, Mips::BGEC_MMR6 }, |
26444 | 0 | { Mips::BGEUC, Mips::BGEUC, Mips::BGEUC_MMR6 }, |
26445 | 0 | { Mips::BGEZALC, Mips::BGEZALC, Mips::BGEZALC_MMR6 }, |
26446 | 0 | { Mips::BGEZC, Mips::BGEZC, Mips::BGEZC_MMR6 }, |
26447 | 0 | { Mips::BGTZALC, Mips::BGTZALC, Mips::BGTZALC_MMR6 }, |
26448 | 0 | { Mips::BGTZC, Mips::BGTZC, Mips::BGTZC_MMR6 }, |
26449 | 0 | { Mips::BITSWAP, Mips::BITSWAP, Mips::BITSWAP_MMR6 }, |
26450 | 0 | { Mips::BLEZALC, Mips::BLEZALC, Mips::BLEZALC_MMR6 }, |
26451 | 0 | { Mips::BLEZC, Mips::BLEZC, Mips::BLEZC_MMR6 }, |
26452 | 0 | { Mips::BLTC, Mips::BLTC, Mips::BLTC_MMR6 }, |
26453 | 0 | { Mips::BLTUC, Mips::BLTUC, Mips::BLTUC_MMR6 }, |
26454 | 0 | { Mips::BLTZALC, Mips::BLTZALC, Mips::BLTZALC_MMR6 }, |
26455 | 0 | { Mips::BLTZC, Mips::BLTZC, Mips::BLTZC_MMR6 }, |
26456 | 0 | { Mips::BNEC, Mips::BNEC, Mips::BNEC_MMR6 }, |
26457 | 0 | { Mips::BNEZALC, Mips::BNEZALC, Mips::BNEZALC_MMR6 }, |
26458 | 0 | { Mips::BNEZC, Mips::BNEZC, Mips::BNEZC_MMR6 }, |
26459 | 0 | { Mips::BNVC, Mips::BNVC, Mips::BNVC_MMR6 }, |
26460 | 0 | { Mips::BOVC, Mips::BOVC, Mips::BOVC_MMR6 }, |
26461 | 0 | { Mips::CACHE_R6, Mips::CACHE_R6, Mips::CACHE_MMR6 }, |
26462 | 0 | { Mips::CLO_R6, Mips::CLO_R6, Mips::CLO_MMR6 }, |
26463 | 0 | { Mips::CLZ_R6, Mips::CLZ_R6, Mips::CLZ_MMR6 }, |
26464 | 0 | { Mips::CMP_EQ_D, Mips::CMP_EQ_D, Mips::CMP_EQ_D_MMR6 }, |
26465 | 0 | { Mips::CMP_EQ_S, Mips::CMP_EQ_S, Mips::CMP_EQ_S_MMR6 }, |
26466 | 0 | { Mips::CMP_F_D, Mips::CMP_F_D, Mips::CMP_AF_D_MMR6 }, |
26467 | 0 | { Mips::CMP_F_S, Mips::CMP_F_S, Mips::CMP_AF_S_MMR6 }, |
26468 | 0 | { Mips::CMP_LE_D, Mips::CMP_LE_D, Mips::CMP_LE_D_MMR6 }, |
26469 | 0 | { Mips::CMP_LE_S, Mips::CMP_LE_S, Mips::CMP_LE_S_MMR6 }, |
26470 | 0 | { Mips::CMP_LT_D, Mips::CMP_LT_D, Mips::CMP_LT_D_MMR6 }, |
26471 | 0 | { Mips::CMP_LT_S, Mips::CMP_LT_S, Mips::CMP_LT_S_MMR6 }, |
26472 | 0 | { Mips::CMP_SAF_D, Mips::CMP_SAF_D, Mips::CMP_SAF_D_MMR6 }, |
26473 | 0 | { Mips::CMP_SAF_S, Mips::CMP_SAF_S, Mips::CMP_SAF_S_MMR6 }, |
26474 | 0 | { Mips::CMP_SEQ_D, Mips::CMP_SEQ_D, Mips::CMP_SEQ_D_MMR6 }, |
26475 | 0 | { Mips::CMP_SEQ_S, Mips::CMP_SEQ_S, Mips::CMP_SEQ_S_MMR6 }, |
26476 | 0 | { Mips::CMP_SLE_D, Mips::CMP_SLE_D, Mips::CMP_SLE_D_MMR6 }, |
26477 | 0 | { Mips::CMP_SLE_S, Mips::CMP_SLE_S, Mips::CMP_SLE_S_MMR6 }, |
26478 | 0 | { Mips::CMP_SLT_D, Mips::CMP_SLT_D, Mips::CMP_SLT_D_MMR6 }, |
26479 | 0 | { Mips::CMP_SLT_S, Mips::CMP_SLT_S, Mips::CMP_SLT_S_MMR6 }, |
26480 | 0 | { Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D, Mips::CMP_SUEQ_D_MMR6 }, |
26481 | 0 | { Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S, Mips::CMP_SUEQ_S_MMR6 }, |
26482 | 0 | { Mips::CMP_SULE_D, Mips::CMP_SULE_D, Mips::CMP_SULE_D_MMR6 }, |
26483 | 0 | { Mips::CMP_SULE_S, Mips::CMP_SULE_S, Mips::CMP_SULE_S_MMR6 }, |
26484 | 0 | { Mips::CMP_SULT_D, Mips::CMP_SULT_D, Mips::CMP_SULT_D_MMR6 }, |
26485 | 0 | { Mips::CMP_SULT_S, Mips::CMP_SULT_S, Mips::CMP_SULT_S_MMR6 }, |
26486 | 0 | { Mips::CMP_SUN_D, Mips::CMP_SUN_D, Mips::CMP_SUN_D_MMR6 }, |
26487 | 0 | { Mips::CMP_SUN_S, Mips::CMP_SUN_S, Mips::CMP_SUN_S_MMR6 }, |
26488 | 0 | { Mips::CMP_UEQ_D, Mips::CMP_UEQ_D, Mips::CMP_UEQ_D_MMR6 }, |
26489 | 0 | { Mips::CMP_UEQ_S, Mips::CMP_UEQ_S, Mips::CMP_UEQ_S_MMR6 }, |
26490 | 0 | { Mips::CMP_ULE_D, Mips::CMP_ULE_D, Mips::CMP_ULE_D_MMR6 }, |
26491 | 0 | { Mips::CMP_ULE_S, Mips::CMP_ULE_S, Mips::CMP_ULE_S_MMR6 }, |
26492 | 0 | { Mips::CMP_ULT_D, Mips::CMP_ULT_D, Mips::CMP_ULT_D_MMR6 }, |
26493 | 0 | { Mips::CMP_ULT_S, Mips::CMP_ULT_S, Mips::CMP_ULT_S_MMR6 }, |
26494 | 0 | { Mips::CMP_UN_D, Mips::CMP_UN_D, Mips::CMP_UN_D_MMR6 }, |
26495 | 0 | { Mips::CMP_UN_S, Mips::CMP_UN_S, Mips::CMP_UN_S_MMR6 }, |
26496 | 0 | { Mips::CRC32B, Mips::CRC32B, (uint16_t)-1U }, |
26497 | 0 | { Mips::CRC32CB, Mips::CRC32CB, (uint16_t)-1U }, |
26498 | 0 | { Mips::CRC32CD, Mips::CRC32CD, (uint16_t)-1U }, |
26499 | 0 | { Mips::CRC32CH, Mips::CRC32CH, (uint16_t)-1U }, |
26500 | 0 | { Mips::CRC32CW, Mips::CRC32CW, (uint16_t)-1U }, |
26501 | 0 | { Mips::CRC32D, Mips::CRC32D, (uint16_t)-1U }, |
26502 | 0 | { Mips::CRC32H, Mips::CRC32H, (uint16_t)-1U }, |
26503 | 0 | { Mips::CRC32W, Mips::CRC32W, (uint16_t)-1U }, |
26504 | 0 | { Mips::DIV, Mips::DIV, Mips::DIV_MMR6 }, |
26505 | 0 | { Mips::DIVU, Mips::DIVU, Mips::DIVU_MMR6 }, |
26506 | 0 | { Mips::DVP, Mips::DVP, Mips::DVP_MMR6 }, |
26507 | 0 | { Mips::EVP, Mips::EVP, Mips::EVP_MMR6 }, |
26508 | 0 | { Mips::GINVI, Mips::GINVI, Mips::GINVI_MMR6 }, |
26509 | 0 | { Mips::GINVT, Mips::GINVT, Mips::GINVT_MMR6 }, |
26510 | 0 | { Mips::JIALC, Mips::JIALC, Mips::JIALC_MMR6 }, |
26511 | 0 | { Mips::JIC, Mips::JIC, Mips::JIC_MMR6 }, |
26512 | 0 | { Mips::LSA_R6, Mips::LSA_R6, Mips::LSA_MMR6 }, |
26513 | 0 | { Mips::LWPC, Mips::LWPC, Mips::LWPC_MMR6 }, |
26514 | 0 | { Mips::MOD, Mips::MOD, Mips::MOD_MMR6 }, |
26515 | 0 | { Mips::MODU, Mips::MODU, Mips::MODU_MMR6 }, |
26516 | 0 | { Mips::MUH, Mips::MUH, Mips::MUH_MMR6 }, |
26517 | 0 | { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 }, |
26518 | 0 | { Mips::MULU, Mips::MULU, Mips::MULU_MMR6 }, |
26519 | 0 | { Mips::MUL_R6, Mips::MUL_R6, Mips::MUL_MMR6 }, |
26520 | 0 | { Mips::PREF_R6, Mips::PREF_R6, Mips::PREF_MMR6 }, |
26521 | 0 | { Mips::SELEQZ, Mips::SELEQZ, Mips::SELEQZ_MMR6 }, |
26522 | 0 | { Mips::SELEQZ_D, Mips::SELEQZ_D, Mips::SELEQZ_D_MMR6 }, |
26523 | 0 | { Mips::SELEQZ_S, Mips::SELEQZ_S, Mips::SELEQZ_S_MMR6 }, |
26524 | 0 | { Mips::SELNEZ, Mips::SELNEZ, Mips::SELNEZ_MMR6 }, |
26525 | 0 | { Mips::SELNEZ_D, Mips::SELNEZ_D, Mips::SELNEZ_D_MMR6 }, |
26526 | 0 | { Mips::SELNEZ_S, Mips::SELNEZ_S, Mips::SELNEZ_S_MMR6 }, |
26527 | 0 | { Mips::SEL_D, Mips::SEL_D, Mips::SEL_D_MMR6 }, |
26528 | 0 | { Mips::SEL_S, Mips::SEL_S, Mips::SEL_S_MMR6 }, |
26529 | 0 | }; // End of MipsR62MicroMipsR6Table |
26530 | |
|
26531 | 0 | unsigned mid; |
26532 | 0 | unsigned start = 0; |
26533 | 0 | unsigned end = 96; |
26534 | 0 | while (start < end) { |
26535 | 0 | mid = start + (end - start) / 2; |
26536 | 0 | if (Opcode == MipsR62MicroMipsR6Table[mid][0]) { |
26537 | 0 | break; |
26538 | 0 | } |
26539 | 0 | if (Opcode < MipsR62MicroMipsR6Table[mid][0]) |
26540 | 0 | end = mid; |
26541 | 0 | else |
26542 | 0 | start = mid + 1; |
26543 | 0 | } |
26544 | 0 | if (start == end) |
26545 | 0 | return -1; // Instruction doesn't exist in this table. |
26546 | | |
26547 | 0 | if (inArch == Arch_mipsr6) |
26548 | 0 | return MipsR62MicroMipsR6Table[mid][1]; |
26549 | 0 | if (inArch == Arch_micromipsr6) |
26550 | 0 | return MipsR62MicroMipsR6Table[mid][2]; |
26551 | 0 | return -1;} |
26552 | | |
26553 | | // Std2MicroMips |
26554 | | LLVM_READONLY |
26555 | 0 | int Std2MicroMips(uint16_t Opcode, enum Arch inArch) { |
26556 | 0 | static const uint16_t Std2MicroMipsTable[][3] = { |
26557 | 0 | { Mips::ADD, Mips::ADD, Mips::ADD_MM }, |
26558 | 0 | { Mips::ADDi, Mips::ADDi, Mips::ADDi_MM }, |
26559 | 0 | { Mips::ADDiu, Mips::ADDiu, Mips::ADDiu_MM }, |
26560 | 0 | { Mips::ADDu, Mips::ADDu, Mips::ADDu_MM }, |
26561 | 0 | { Mips::AND, Mips::AND, Mips::AND_MM }, |
26562 | 0 | { Mips::ANDi, Mips::ANDi, Mips::ANDi_MM }, |
26563 | 0 | { Mips::BC1F, Mips::BC1F, Mips::BC1F_MM }, |
26564 | 0 | { Mips::BC1FL, Mips::BC1FL, (uint16_t)-1U }, |
26565 | 0 | { Mips::BC1T, Mips::BC1T, Mips::BC1T_MM }, |
26566 | 0 | { Mips::BC1TL, Mips::BC1TL, (uint16_t)-1U }, |
26567 | 0 | { Mips::BEQ, Mips::BEQ, Mips::BEQ_MM }, |
26568 | 0 | { Mips::BEQL, Mips::BEQL, (uint16_t)-1U }, |
26569 | 0 | { Mips::BGEZ, Mips::BGEZ, Mips::BGEZ_MM }, |
26570 | 0 | { Mips::BGEZAL, Mips::BGEZAL, Mips::BGEZAL_MM }, |
26571 | 0 | { Mips::BGEZALL, Mips::BGEZALL, (uint16_t)-1U }, |
26572 | 0 | { Mips::BGEZL, Mips::BGEZL, (uint16_t)-1U }, |
26573 | 0 | { Mips::BGTZ, Mips::BGTZ, Mips::BGTZ_MM }, |
26574 | 0 | { Mips::BGTZL, Mips::BGTZL, (uint16_t)-1U }, |
26575 | 0 | { Mips::BLEZ, Mips::BLEZ, Mips::BLEZ_MM }, |
26576 | 0 | { Mips::BLEZL, Mips::BLEZL, (uint16_t)-1U }, |
26577 | 0 | { Mips::BLTZ, Mips::BLTZ, Mips::BLTZ_MM }, |
26578 | 0 | { Mips::BLTZAL, Mips::BLTZAL, Mips::BLTZAL_MM }, |
26579 | 0 | { Mips::BLTZALL, Mips::BLTZALL, (uint16_t)-1U }, |
26580 | 0 | { Mips::BLTZL, Mips::BLTZL, (uint16_t)-1U }, |
26581 | 0 | { Mips::BNE, Mips::BNE, Mips::BNE_MM }, |
26582 | 0 | { Mips::BNEL, Mips::BNEL, (uint16_t)-1U }, |
26583 | 0 | { Mips::BREAK, Mips::BREAK, Mips::BREAK_MM }, |
26584 | 0 | { Mips::CACHE, Mips::CACHE, Mips::CACHE_MM }, |
26585 | 0 | { Mips::CACHEE, Mips::CACHEE, Mips::CACHEE_MM }, |
26586 | 0 | { Mips::CEIL_W_D32, Mips::CEIL_W_D32, Mips::CEIL_W_MM }, |
26587 | 0 | { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MM }, |
26588 | 0 | { Mips::CFC1, Mips::CFC1, Mips::CFC1_MM }, |
26589 | 0 | { Mips::CLO, Mips::CLO, Mips::CLO_MM }, |
26590 | 0 | { Mips::CLZ, Mips::CLZ, Mips::CLZ_MM }, |
26591 | 0 | { Mips::CTC1, Mips::CTC1, Mips::CTC1_MM }, |
26592 | 0 | { Mips::CVT_D32_S, Mips::CVT_D32_S, Mips::CVT_D32_S_MM }, |
26593 | 0 | { Mips::CVT_D32_W, Mips::CVT_D32_W, Mips::CVT_D32_W_MM }, |
26594 | 0 | { Mips::CVT_L_D64, Mips::CVT_L_D64, Mips::CVT_L_D64_MM }, |
26595 | 0 | { Mips::CVT_L_S, Mips::CVT_L_S, Mips::CVT_L_S_MM }, |
26596 | 0 | { Mips::CVT_S_D32, Mips::CVT_S_D32, Mips::CVT_S_D32_MM }, |
26597 | 0 | { Mips::CVT_S_W, Mips::CVT_S_W, Mips::CVT_S_W_MM }, |
26598 | 0 | { Mips::CVT_W_D32, Mips::CVT_W_D32, Mips::CVT_W_D32_MM }, |
26599 | 0 | { Mips::CVT_W_S, Mips::CVT_W_S, Mips::CVT_W_S_MM }, |
26600 | 0 | { Mips::C_EQ_D32, Mips::C_EQ_D32, Mips::C_EQ_D32_MM }, |
26601 | 0 | { Mips::C_EQ_D64, Mips::C_EQ_D64, Mips::C_EQ_D64_MM }, |
26602 | 0 | { Mips::C_EQ_S, Mips::C_EQ_S, Mips::C_EQ_S_MM }, |
26603 | 0 | { Mips::C_F_D32, Mips::C_F_D32, Mips::C_F_D32_MM }, |
26604 | 0 | { Mips::C_F_D64, Mips::C_F_D64, Mips::C_F_D64_MM }, |
26605 | 0 | { Mips::C_F_S, Mips::C_F_S, Mips::C_F_S_MM }, |
26606 | 0 | { Mips::C_LE_D32, Mips::C_LE_D32, Mips::C_LE_D32_MM }, |
26607 | 0 | { Mips::C_LE_D64, Mips::C_LE_D64, Mips::C_LE_D64_MM }, |
26608 | 0 | { Mips::C_LE_S, Mips::C_LE_S, Mips::C_LE_S_MM }, |
26609 | 0 | { Mips::C_LT_D32, Mips::C_LT_D32, Mips::C_LT_D32_MM }, |
26610 | 0 | { Mips::C_LT_D64, Mips::C_LT_D64, Mips::C_LT_D64_MM }, |
26611 | 0 | { Mips::C_LT_S, Mips::C_LT_S, Mips::C_LT_S_MM }, |
26612 | 0 | { Mips::C_NGE_D32, Mips::C_NGE_D32, Mips::C_NGE_D32_MM }, |
26613 | 0 | { Mips::C_NGE_D64, Mips::C_NGE_D64, Mips::C_NGE_D64_MM }, |
26614 | 0 | { Mips::C_NGE_S, Mips::C_NGE_S, Mips::C_NGE_S_MM }, |
26615 | 0 | { Mips::C_NGLE_D32, Mips::C_NGLE_D32, Mips::C_NGLE_D32_MM }, |
26616 | 0 | { Mips::C_NGLE_D64, Mips::C_NGLE_D64, Mips::C_NGLE_D64_MM }, |
26617 | 0 | { Mips::C_NGLE_S, Mips::C_NGLE_S, Mips::C_NGLE_S_MM }, |
26618 | 0 | { Mips::C_NGL_D32, Mips::C_NGL_D32, Mips::C_NGL_D32_MM }, |
26619 | 0 | { Mips::C_NGL_D64, Mips::C_NGL_D64, Mips::C_NGL_D64_MM }, |
26620 | 0 | { Mips::C_NGL_S, Mips::C_NGL_S, Mips::C_NGL_S_MM }, |
26621 | 0 | { Mips::C_NGT_D32, Mips::C_NGT_D32, Mips::C_NGT_D32_MM }, |
26622 | 0 | { Mips::C_NGT_D64, Mips::C_NGT_D64, Mips::C_NGT_D64_MM }, |
26623 | 0 | { Mips::C_NGT_S, Mips::C_NGT_S, Mips::C_NGT_S_MM }, |
26624 | 0 | { Mips::C_OLE_D32, Mips::C_OLE_D32, Mips::C_OLE_D32_MM }, |
26625 | 0 | { Mips::C_OLE_D64, Mips::C_OLE_D64, Mips::C_OLE_D64_MM }, |
26626 | 0 | { Mips::C_OLE_S, Mips::C_OLE_S, Mips::C_OLE_S_MM }, |
26627 | 0 | { Mips::C_OLT_D32, Mips::C_OLT_D32, Mips::C_OLT_D32_MM }, |
26628 | 0 | { Mips::C_OLT_D64, Mips::C_OLT_D64, Mips::C_OLT_D64_MM }, |
26629 | 0 | { Mips::C_OLT_S, Mips::C_OLT_S, Mips::C_OLT_S_MM }, |
26630 | 0 | { Mips::C_SEQ_D32, Mips::C_SEQ_D32, Mips::C_SEQ_D32_MM }, |
26631 | 0 | { Mips::C_SEQ_D64, Mips::C_SEQ_D64, Mips::C_SEQ_D64_MM }, |
26632 | 0 | { Mips::C_SEQ_S, Mips::C_SEQ_S, Mips::C_SEQ_S_MM }, |
26633 | 0 | { Mips::C_SF_D32, Mips::C_SF_D32, Mips::C_SF_D32_MM }, |
26634 | 0 | { Mips::C_SF_D64, Mips::C_SF_D64, Mips::C_SF_D64_MM }, |
26635 | 0 | { Mips::C_SF_S, Mips::C_SF_S, Mips::C_SF_S_MM }, |
26636 | 0 | { Mips::C_UEQ_D32, Mips::C_UEQ_D32, Mips::C_UEQ_D32_MM }, |
26637 | 0 | { Mips::C_UEQ_D64, Mips::C_UEQ_D64, Mips::C_UEQ_D64_MM }, |
26638 | 0 | { Mips::C_UEQ_S, Mips::C_UEQ_S, Mips::C_UEQ_S_MM }, |
26639 | 0 | { Mips::C_ULE_D32, Mips::C_ULE_D32, Mips::C_ULE_D32_MM }, |
26640 | 0 | { Mips::C_ULE_D64, Mips::C_ULE_D64, Mips::C_ULE_D64_MM }, |
26641 | 0 | { Mips::C_ULE_S, Mips::C_ULE_S, Mips::C_ULE_S_MM }, |
26642 | 0 | { Mips::C_ULT_D32, Mips::C_ULT_D32, Mips::C_ULT_D32_MM }, |
26643 | 0 | { Mips::C_ULT_D64, Mips::C_ULT_D64, Mips::C_ULT_D64_MM }, |
26644 | 0 | { Mips::C_ULT_S, Mips::C_ULT_S, Mips::C_ULT_S_MM }, |
26645 | 0 | { Mips::C_UN_D32, Mips::C_UN_D32, Mips::C_UN_D32_MM }, |
26646 | 0 | { Mips::C_UN_D64, Mips::C_UN_D64, Mips::C_UN_D64_MM }, |
26647 | 0 | { Mips::C_UN_S, Mips::C_UN_S, Mips::C_UN_S_MM }, |
26648 | 0 | { Mips::DERET, Mips::DERET, Mips::DERET_MM }, |
26649 | 0 | { Mips::DI, Mips::DI, Mips::DI_MM }, |
26650 | 0 | { Mips::EHB, Mips::EHB, Mips::EHB_MM }, |
26651 | 0 | { Mips::EI, Mips::EI, Mips::EI_MM }, |
26652 | 0 | { Mips::ERET, Mips::ERET, Mips::ERET_MM }, |
26653 | 0 | { Mips::ERETNC, Mips::ERETNC, (uint16_t)-1U }, |
26654 | 0 | { Mips::EXT, Mips::EXT, Mips::EXT_MM }, |
26655 | 0 | { Mips::FABS_D32, Mips::FABS_D32, Mips::FABS_D32_MM }, |
26656 | 0 | { Mips::FABS_S, Mips::FABS_S, Mips::FABS_S_MM }, |
26657 | 0 | { Mips::FADD_D32, Mips::FADD_D32, Mips::FADD_D32_MM }, |
26658 | 0 | { Mips::FADD_S, Mips::FADD_S, Mips::FADD_S_MM }, |
26659 | 0 | { Mips::FCMP_D32, Mips::FCMP_D32, Mips::FCMP_D32_MM }, |
26660 | 0 | { Mips::FCMP_S32, Mips::FCMP_S32, Mips::FCMP_S32_MM }, |
26661 | 0 | { Mips::FDIV_D32, Mips::FDIV_D32, Mips::FDIV_D32_MM }, |
26662 | 0 | { Mips::FDIV_S, Mips::FDIV_S, Mips::FDIV_S_MM }, |
26663 | 0 | { Mips::FLOOR_W_D32, Mips::FLOOR_W_D32, Mips::FLOOR_W_MM }, |
26664 | 0 | { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MM }, |
26665 | 0 | { Mips::FMOV_D32, Mips::FMOV_D32, Mips::FMOV_D32_MM }, |
26666 | 0 | { Mips::FMOV_S, Mips::FMOV_S, Mips::FMOV_S_MM }, |
26667 | 0 | { Mips::FMUL_D32, Mips::FMUL_D32, Mips::FMUL_D32_MM }, |
26668 | 0 | { Mips::FMUL_S, Mips::FMUL_S, Mips::FMUL_S_MM }, |
26669 | 0 | { Mips::FNEG_D32, Mips::FNEG_D32, Mips::FNEG_D32_MM }, |
26670 | 0 | { Mips::FNEG_S, Mips::FNEG_S, Mips::FNEG_S_MM }, |
26671 | 0 | { Mips::FSQRT_D32, Mips::FSQRT_D32, Mips::FSQRT_D32_MM }, |
26672 | 0 | { Mips::FSQRT_S, Mips::FSQRT_S, Mips::FSQRT_S_MM }, |
26673 | 0 | { Mips::FSUB_D32, Mips::FSUB_D32, Mips::FSUB_D32_MM }, |
26674 | 0 | { Mips::FSUB_S, Mips::FSUB_S, Mips::FSUB_S_MM }, |
26675 | 0 | { Mips::HYPCALL, Mips::HYPCALL, Mips::HYPCALL_MM }, |
26676 | 0 | { Mips::INS, Mips::INS, Mips::INS_MM }, |
26677 | 0 | { Mips::J, Mips::J, Mips::J_MM }, |
26678 | 0 | { Mips::JAL, Mips::JAL, Mips::JAL_MM }, |
26679 | 0 | { Mips::JALX, Mips::JALX, Mips::JALX_MM }, |
26680 | 0 | { Mips::JR, Mips::JR, Mips::JR_MM }, |
26681 | 0 | { Mips::LB, Mips::LB, Mips::LB_MM }, |
26682 | 0 | { Mips::LBE, Mips::LBE, Mips::LBE_MM }, |
26683 | 0 | { Mips::LBu, Mips::LBu, Mips::LBu_MM }, |
26684 | 0 | { Mips::LBuE, Mips::LBuE, Mips::LBuE_MM }, |
26685 | 0 | { Mips::LDC1, Mips::LDC1, Mips::LDC1_MM_D32 }, |
26686 | 0 | { Mips::LEA_ADDiu, Mips::LEA_ADDiu, Mips::LEA_ADDiu_MM }, |
26687 | 0 | { Mips::LH, Mips::LH, Mips::LH_MM }, |
26688 | 0 | { Mips::LHE, Mips::LHE, Mips::LHE_MM }, |
26689 | 0 | { Mips::LHu, Mips::LHu, Mips::LHu_MM }, |
26690 | 0 | { Mips::LHuE, Mips::LHuE, Mips::LHuE_MM }, |
26691 | 0 | { Mips::LLE, Mips::LLE, Mips::LLE_MM }, |
26692 | 0 | { Mips::LUXC1, Mips::LUXC1, Mips::LUXC1_MM }, |
26693 | 0 | { Mips::LUi, Mips::LUi, Mips::LUi_MM }, |
26694 | 0 | { Mips::LW, Mips::LW, Mips::LW_MM }, |
26695 | 0 | { Mips::LWC1, Mips::LWC1, Mips::LWC1_MM }, |
26696 | 0 | { Mips::LWE, Mips::LWE, Mips::LWE_MM }, |
26697 | 0 | { Mips::LWL, Mips::LWL, Mips::LWL_MM }, |
26698 | 0 | { Mips::LWLE, Mips::LWLE, Mips::LWLE_MM }, |
26699 | 0 | { Mips::LWR, Mips::LWR, Mips::LWR_MM }, |
26700 | 0 | { Mips::LWRE, Mips::LWRE, Mips::LWRE_MM }, |
26701 | 0 | { Mips::LWXC1, Mips::LWXC1, Mips::LWXC1_MM }, |
26702 | 0 | { Mips::LWu, Mips::LWu, Mips::LWU_MM }, |
26703 | 0 | { Mips::MADD, Mips::MADD, Mips::MADD_MM }, |
26704 | 0 | { Mips::MADDU, Mips::MADDU, Mips::MADDU_MM }, |
26705 | 0 | { Mips::MADD_D32, Mips::MADD_D32, Mips::MADD_D32_MM }, |
26706 | 0 | { Mips::MADD_S, Mips::MADD_S, Mips::MADD_S_MM }, |
26707 | 0 | { Mips::MFC1, Mips::MFC1, Mips::MFC1_MM }, |
26708 | 0 | { Mips::MFGC0, Mips::MFGC0, Mips::MFGC0_MM }, |
26709 | 0 | { Mips::MFHC1_D32, Mips::MFHC1_D32, Mips::MFHC1_D32_MM }, |
26710 | 0 | { Mips::MFHGC0, Mips::MFHGC0, Mips::MFHGC0_MM }, |
26711 | 0 | { Mips::MFHI, Mips::MFHI, Mips::MFHI_MM }, |
26712 | 0 | { Mips::MFLO, Mips::MFLO, Mips::MFLO_MM }, |
26713 | 0 | { Mips::MOVF_D32, Mips::MOVF_D32, Mips::MOVF_D32_MM }, |
26714 | 0 | { Mips::MOVF_I, Mips::MOVF_I, Mips::MOVF_I_MM }, |
26715 | 0 | { Mips::MOVF_S, Mips::MOVF_S, Mips::MOVF_S_MM }, |
26716 | 0 | { Mips::MOVN_I_D32, Mips::MOVN_I_D32, Mips::MOVN_I_D32_MM }, |
26717 | 0 | { Mips::MOVN_I_I, Mips::MOVN_I_I, Mips::MOVN_I_MM }, |
26718 | 0 | { Mips::MOVN_I_S, Mips::MOVN_I_S, Mips::MOVN_I_S_MM }, |
26719 | 0 | { Mips::MOVT_D32, Mips::MOVT_D32, Mips::MOVT_D32_MM }, |
26720 | 0 | { Mips::MOVT_I, Mips::MOVT_I, Mips::MOVT_I_MM }, |
26721 | 0 | { Mips::MOVT_S, Mips::MOVT_S, Mips::MOVT_S_MM }, |
26722 | 0 | { Mips::MOVZ_I_D32, Mips::MOVZ_I_D32, Mips::MOVZ_I_D32_MM }, |
26723 | 0 | { Mips::MOVZ_I_I, Mips::MOVZ_I_I, Mips::MOVZ_I_MM }, |
26724 | 0 | { Mips::MOVZ_I_S, Mips::MOVZ_I_S, Mips::MOVZ_I_S_MM }, |
26725 | 0 | { Mips::MSUB, Mips::MSUB, Mips::MSUB_MM }, |
26726 | 0 | { Mips::MSUBU, Mips::MSUBU, Mips::MSUBU_MM }, |
26727 | 0 | { Mips::MSUB_D32, Mips::MSUB_D32, Mips::MSUB_D32_MM }, |
26728 | 0 | { Mips::MSUB_S, Mips::MSUB_S, Mips::MSUB_S_MM }, |
26729 | 0 | { Mips::MTC1, Mips::MTC1, Mips::MTC1_MM }, |
26730 | 0 | { Mips::MTGC0, Mips::MTGC0, Mips::MTGC0_MM }, |
26731 | 0 | { Mips::MTHC1_D32, Mips::MTHC1_D32, Mips::MTHC1_D32_MM }, |
26732 | 0 | { Mips::MTHGC0, Mips::MTHGC0, Mips::MTHGC0_MM }, |
26733 | 0 | { Mips::MTHI, Mips::MTHI, Mips::MTHI_MM }, |
26734 | 0 | { Mips::MTLO, Mips::MTLO, Mips::MTLO_MM }, |
26735 | 0 | { Mips::MUL, Mips::MUL, Mips::MUL_MM }, |
26736 | 0 | { Mips::MULT, Mips::MULT, Mips::MULT_MM }, |
26737 | 0 | { Mips::MULTu, Mips::MULTu, Mips::MULTu_MM }, |
26738 | 0 | { Mips::NMADD_D32, Mips::NMADD_D32, Mips::NMADD_D32_MM }, |
26739 | 0 | { Mips::NMADD_S, Mips::NMADD_S, Mips::NMADD_S_MM }, |
26740 | 0 | { Mips::NMSUB_D32, Mips::NMSUB_D32, Mips::NMSUB_D32_MM }, |
26741 | 0 | { Mips::NMSUB_S, Mips::NMSUB_S, Mips::NMSUB_S_MM }, |
26742 | 0 | { Mips::NOR, Mips::NOR, Mips::NOR_MM }, |
26743 | 0 | { Mips::OR, Mips::OR, Mips::OR_MM }, |
26744 | 0 | { Mips::ORi, Mips::ORi, Mips::ORi_MM }, |
26745 | 0 | { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MM }, |
26746 | 0 | { Mips::PREF, Mips::PREF, Mips::PREF_MM }, |
26747 | 0 | { Mips::PREFE, Mips::PREFE, Mips::PREFE_MM }, |
26748 | 0 | { Mips::RDHWR, Mips::RDHWR, Mips::RDHWR_MM }, |
26749 | 0 | { Mips::RECIP_D32, Mips::RECIP_D32, Mips::RECIP_D32_MM }, |
26750 | 0 | { Mips::RECIP_D64, Mips::RECIP_D64, Mips::RECIP_D64_MM }, |
26751 | 0 | { Mips::RECIP_S, Mips::RECIP_S, Mips::RECIP_S_MM }, |
26752 | 0 | { Mips::ROTR, Mips::ROTR, Mips::ROTR_MM }, |
26753 | 0 | { Mips::ROTRV, Mips::ROTRV, Mips::ROTRV_MM }, |
26754 | 0 | { Mips::ROUND_W_D32, Mips::ROUND_W_D32, Mips::ROUND_W_MM }, |
26755 | 0 | { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MM }, |
26756 | 0 | { Mips::RSQRT_D32, Mips::RSQRT_D32, Mips::RSQRT_D32_MM }, |
26757 | 0 | { Mips::RSQRT_D64, Mips::RSQRT_D64, Mips::RSQRT_D64_MM }, |
26758 | 0 | { Mips::RSQRT_S, Mips::RSQRT_S, Mips::RSQRT_S_MM }, |
26759 | 0 | { Mips::SB, Mips::SB, Mips::SB_MM }, |
26760 | 0 | { Mips::SBE, Mips::SBE, Mips::SBE_MM }, |
26761 | 0 | { Mips::SCE, Mips::SCE, Mips::SCE_MM }, |
26762 | 0 | { Mips::SDBBP, Mips::SDBBP, Mips::SDBBP_MM }, |
26763 | 0 | { Mips::SDC1, Mips::SDC1, (uint16_t)-1U }, |
26764 | 0 | { Mips::SDIV, Mips::SDIV, Mips::SDIV_MM }, |
26765 | 0 | { Mips::SEB, Mips::SEB, Mips::SEB_MM }, |
26766 | 0 | { Mips::SEH, Mips::SEH, Mips::SEH_MM }, |
26767 | 0 | { Mips::SH, Mips::SH, Mips::SH_MM }, |
26768 | 0 | { Mips::SHE, Mips::SHE, Mips::SHE_MM }, |
26769 | 0 | { Mips::SLL, Mips::SLL, Mips::SLL_MM }, |
26770 | 0 | { Mips::SLLV, Mips::SLLV, Mips::SLLV_MM }, |
26771 | 0 | { Mips::SLT, Mips::SLT, Mips::SLT_MM }, |
26772 | 0 | { Mips::SLTi, Mips::SLTi, Mips::SLTi_MM }, |
26773 | 0 | { Mips::SLTiu, Mips::SLTiu, Mips::SLTiu_MM }, |
26774 | 0 | { Mips::SLTu, Mips::SLTu, Mips::SLTu_MM }, |
26775 | 0 | { Mips::SRA, Mips::SRA, Mips::SRA_MM }, |
26776 | 0 | { Mips::SRAV, Mips::SRAV, Mips::SRAV_MM }, |
26777 | 0 | { Mips::SRL, Mips::SRL, Mips::SRL_MM }, |
26778 | 0 | { Mips::SRLV, Mips::SRLV, Mips::SRLV_MM }, |
26779 | 0 | { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MM }, |
26780 | 0 | { Mips::SUB, Mips::SUB, Mips::SUB_MM }, |
26781 | 0 | { Mips::SUBu, Mips::SUBu, Mips::SUBu_MM }, |
26782 | 0 | { Mips::SUXC1, Mips::SUXC1, Mips::SUXC1_MM }, |
26783 | 0 | { Mips::SW, Mips::SW, Mips::SW_MM }, |
26784 | 0 | { Mips::SWC1, Mips::SWC1, Mips::SWC1_MM }, |
26785 | 0 | { Mips::SWE, Mips::SWE, Mips::SWE_MM }, |
26786 | 0 | { Mips::SWL, Mips::SWL, Mips::SWL_MM }, |
26787 | 0 | { Mips::SWLE, Mips::SWLE, Mips::SWLE_MM }, |
26788 | 0 | { Mips::SWR, Mips::SWR, Mips::SWR_MM }, |
26789 | 0 | { Mips::SWRE, Mips::SWRE, Mips::SWRE_MM }, |
26790 | 0 | { Mips::SWXC1, Mips::SWXC1, Mips::SWXC1_MM }, |
26791 | 0 | { Mips::SYNC, Mips::SYNC, Mips::SYNC_MM }, |
26792 | 0 | { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MM }, |
26793 | 0 | { Mips::SYSCALL, Mips::SYSCALL, Mips::SYSCALL_MM }, |
26794 | 0 | { Mips::TEQ, Mips::TEQ, Mips::TEQ_MM }, |
26795 | 0 | { Mips::TEQI, Mips::TEQI, Mips::TEQI_MM }, |
26796 | 0 | { Mips::TGE, Mips::TGE, Mips::TGE_MM }, |
26797 | 0 | { Mips::TGEI, Mips::TGEI, Mips::TGEI_MM }, |
26798 | 0 | { Mips::TGEIU, Mips::TGEIU, Mips::TGEIU_MM }, |
26799 | 0 | { Mips::TGEU, Mips::TGEU, Mips::TGEU_MM }, |
26800 | 0 | { Mips::TLBGINV, Mips::TLBGINV, Mips::TLBGINV_MM }, |
26801 | 0 | { Mips::TLBGINVF, Mips::TLBGINVF, Mips::TLBGINVF_MM }, |
26802 | 0 | { Mips::TLBGP, Mips::TLBGP, Mips::TLBGP_MM }, |
26803 | 0 | { Mips::TLBGR, Mips::TLBGR, Mips::TLBGR_MM }, |
26804 | 0 | { Mips::TLBGWI, Mips::TLBGWI, Mips::TLBGWI_MM }, |
26805 | 0 | { Mips::TLBGWR, Mips::TLBGWR, Mips::TLBGWR_MM }, |
26806 | 0 | { Mips::TLBP, Mips::TLBP, Mips::TLBP_MM }, |
26807 | 0 | { Mips::TLBR, Mips::TLBR, Mips::TLBR_MM }, |
26808 | 0 | { Mips::TLBWI, Mips::TLBWI, Mips::TLBWI_MM }, |
26809 | 0 | { Mips::TLBWR, Mips::TLBWR, Mips::TLBWR_MM }, |
26810 | 0 | { Mips::TLT, Mips::TLT, Mips::TLT_MM }, |
26811 | 0 | { Mips::TLTI, Mips::TLTI, Mips::TLTI_MM }, |
26812 | 0 | { Mips::TLTU, Mips::TLTU, Mips::TLTU_MM }, |
26813 | 0 | { Mips::TNE, Mips::TNE, Mips::TNE_MM }, |
26814 | 0 | { Mips::TNEI, Mips::TNEI, Mips::TNEI_MM }, |
26815 | 0 | { Mips::TRUNC_W_D32, Mips::TRUNC_W_D32, Mips::TRUNC_W_MM }, |
26816 | 0 | { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MM }, |
26817 | 0 | { Mips::TTLTIU, Mips::TTLTIU, Mips::TLTIU_MM }, |
26818 | 0 | { Mips::UDIV, Mips::UDIV, Mips::UDIV_MM }, |
26819 | 0 | { Mips::WAIT, Mips::WAIT, Mips::WAIT_MM }, |
26820 | 0 | { Mips::WSBH, Mips::WSBH, Mips::WSBH_MM }, |
26821 | 0 | { Mips::XOR, Mips::XOR, Mips::XOR_MM }, |
26822 | 0 | { Mips::XORi, Mips::XORi, Mips::XORi_MM }, |
26823 | 0 | }; // End of Std2MicroMipsTable |
26824 | |
|
26825 | 0 | unsigned mid; |
26826 | 0 | unsigned start = 0; |
26827 | 0 | unsigned end = 266; |
26828 | 0 | while (start < end) { |
26829 | 0 | mid = start + (end - start) / 2; |
26830 | 0 | if (Opcode == Std2MicroMipsTable[mid][0]) { |
26831 | 0 | break; |
26832 | 0 | } |
26833 | 0 | if (Opcode < Std2MicroMipsTable[mid][0]) |
26834 | 0 | end = mid; |
26835 | 0 | else |
26836 | 0 | start = mid + 1; |
26837 | 0 | } |
26838 | 0 | if (start == end) |
26839 | 0 | return -1; // Instruction doesn't exist in this table. |
26840 | | |
26841 | 0 | if (inArch == Arch_se) |
26842 | 0 | return Std2MicroMipsTable[mid][1]; |
26843 | 0 | if (inArch == Arch_micromips) |
26844 | 0 | return Std2MicroMipsTable[mid][2]; |
26845 | 0 | return -1;} |
26846 | | |
26847 | | // Std2MicroMipsR6 |
26848 | | LLVM_READONLY |
26849 | 0 | int Std2MicroMipsR6(uint16_t Opcode, enum Arch inArch) { |
26850 | 0 | static const uint16_t Std2MicroMipsR6Table[][3] = { |
26851 | 0 | { Mips::ADD, Mips::ADD, Mips::ADD_MMR6 }, |
26852 | 0 | { Mips::ADDiu, Mips::ADDiu, Mips::ADDIU_MMR6 }, |
26853 | 0 | { Mips::ADDu, Mips::ADDu, Mips::ADDU_MMR6 }, |
26854 | 0 | { Mips::AND, Mips::AND, Mips::AND_MMR6 }, |
26855 | 0 | { Mips::ANDi, Mips::ANDi, Mips::ANDI_MMR6 }, |
26856 | 0 | { Mips::BREAK, Mips::BREAK, Mips::BREAK_MMR6 }, |
26857 | 0 | { Mips::CEIL_W_D64, Mips::CEIL_W_D64, Mips::CEIL_W_D_MMR6 }, |
26858 | 0 | { Mips::CEIL_W_S, Mips::CEIL_W_S, Mips::CEIL_W_S_MMR6 }, |
26859 | 0 | { Mips::CVT_W_D64, Mips::CVT_W_D64, (uint16_t)-1U }, |
26860 | 0 | { Mips::DI, Mips::DI, Mips::DI_MMR6 }, |
26861 | 0 | { Mips::EI, Mips::EI, Mips::EI_MMR6 }, |
26862 | 0 | { Mips::EXT, Mips::EXT, Mips::EXT_MMR6 }, |
26863 | 0 | { Mips::FABS_D64, Mips::FABS_D64, (uint16_t)-1U }, |
26864 | 0 | { Mips::FLOOR_W_D64, Mips::FLOOR_W_D64, Mips::FLOOR_W_D_MMR6 }, |
26865 | 0 | { Mips::FLOOR_W_S, Mips::FLOOR_W_S, Mips::FLOOR_W_S_MMR6 }, |
26866 | 0 | { Mips::FMOV_D64, Mips::FMOV_D64, Mips::FMOV_D_MMR6 }, |
26867 | 0 | { Mips::FNEG_D64, Mips::FNEG_D64, (uint16_t)-1U }, |
26868 | 0 | { Mips::FSQRT_D64, Mips::FSQRT_D64, (uint16_t)-1U }, |
26869 | 0 | { Mips::FSQRT_S, Mips::FSQRT_S, (uint16_t)-1U }, |
26870 | 0 | { Mips::INS, Mips::INS, Mips::INS_MMR6 }, |
26871 | 0 | { Mips::LDC1, Mips::LDC1, (uint16_t)-1U }, |
26872 | 0 | { Mips::LDC164, Mips::LDC164, Mips::LDC1_D64_MMR6 }, |
26873 | 0 | { Mips::LDC2, Mips::LDC2, Mips::LDC2_MMR6 }, |
26874 | 0 | { Mips::LW, Mips::LW, Mips::LW_MMR6 }, |
26875 | 0 | { Mips::LWC2, Mips::LWC2, Mips::LWC2_MMR6 }, |
26876 | 0 | { Mips::MFC1, Mips::MFC1, Mips::MFC1_MMR6 }, |
26877 | 0 | { Mips::MTC1, Mips::MTC1, Mips::MTC1_MMR6 }, |
26878 | 0 | { Mips::MTHC1_D32, Mips::MTHC1_D32, (uint16_t)-1U }, |
26879 | 0 | { Mips::NOR, Mips::NOR, Mips::NOR_MMR6 }, |
26880 | 0 | { Mips::OR, Mips::OR, Mips::OR_MMR6 }, |
26881 | 0 | { Mips::ORi, Mips::ORi, Mips::ORI_MMR6 }, |
26882 | 0 | { Mips::PAUSE, Mips::PAUSE, Mips::PAUSE_MMR6 }, |
26883 | 0 | { Mips::ROUND_W_D64, Mips::ROUND_W_D64, Mips::ROUND_W_D_MMR6 }, |
26884 | 0 | { Mips::ROUND_W_S, Mips::ROUND_W_S, Mips::ROUND_W_S_MMR6 }, |
26885 | 0 | { Mips::SB, Mips::SB, Mips::SB_MMR6 }, |
26886 | 0 | { Mips::SDC164, Mips::SDC164, Mips::SDC1_D64_MMR6 }, |
26887 | 0 | { Mips::SDC2, Mips::SDC2, Mips::SDC2_MMR6 }, |
26888 | 0 | { Mips::SEB, Mips::SEB, (uint16_t)-1U }, |
26889 | 0 | { Mips::SEH, Mips::SEH, (uint16_t)-1U }, |
26890 | 0 | { Mips::SSNOP, Mips::SSNOP, Mips::SSNOP_MMR6 }, |
26891 | 0 | { Mips::SUB, Mips::SUB, Mips::SUB_MMR6 }, |
26892 | 0 | { Mips::SUBu, Mips::SUBu, Mips::SUBU_MMR6 }, |
26893 | 0 | { Mips::SW, Mips::SW, Mips::SW_MMR6 }, |
26894 | 0 | { Mips::SWC2, Mips::SWC2, Mips::SWC2_MMR6 }, |
26895 | 0 | { Mips::SYNC, Mips::SYNC, Mips::SYNC_MMR6 }, |
26896 | 0 | { Mips::SYNCI, Mips::SYNCI, Mips::SYNCI_MMR6 }, |
26897 | 0 | { Mips::TRUNC_W_D64, Mips::TRUNC_W_D64, Mips::TRUNC_W_D_MMR6 }, |
26898 | 0 | { Mips::TRUNC_W_S, Mips::TRUNC_W_S, Mips::TRUNC_W_S_MMR6 }, |
26899 | 0 | { Mips::WAIT, Mips::WAIT, Mips::WAIT_MMR6 }, |
26900 | 0 | { Mips::XOR, Mips::XOR, Mips::XOR_MMR6 }, |
26901 | 0 | { Mips::XORi, Mips::XORi, Mips::XORI_MMR6 }, |
26902 | 0 | }; // End of Std2MicroMipsR6Table |
26903 | |
|
26904 | 0 | unsigned mid; |
26905 | 0 | unsigned start = 0; |
26906 | 0 | unsigned end = 51; |
26907 | 0 | while (start < end) { |
26908 | 0 | mid = start + (end - start) / 2; |
26909 | 0 | if (Opcode == Std2MicroMipsR6Table[mid][0]) { |
26910 | 0 | break; |
26911 | 0 | } |
26912 | 0 | if (Opcode < Std2MicroMipsR6Table[mid][0]) |
26913 | 0 | end = mid; |
26914 | 0 | else |
26915 | 0 | start = mid + 1; |
26916 | 0 | } |
26917 | 0 | if (start == end) |
26918 | 0 | return -1; // Instruction doesn't exist in this table. |
26919 | | |
26920 | 0 | if (inArch == Arch_se) |
26921 | 0 | return Std2MicroMipsR6Table[mid][1]; |
26922 | 0 | if (inArch == Arch_micromipsr6) |
26923 | 0 | return Std2MicroMipsR6Table[mid][2]; |
26924 | 0 | return -1;} |
26925 | | |
26926 | | } // end namespace Mips |
26927 | | } // end namespace llvm |
26928 | | #endif // GET_INSTRMAP_INFO |
26929 | | |