Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Mips/MipsGenMCCodeEmitter.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Machine Code Emitter                                                       *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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uint64_t MipsMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,
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    SmallVectorImpl<MCFixup> &Fixups,
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0
    const MCSubtargetInfo &STI) const {
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0
  static const uint64_t InstBits[] = {
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508
0
    UINT64_C(0),
509
0
    UINT64_C(0),
510
0
    UINT64_C(0),
511
0
    UINT64_C(0),
512
0
    UINT64_C(0),
513
0
    UINT64_C(0),
514
0
    UINT64_C(0),
515
0
    UINT64_C(0),
516
0
    UINT64_C(0),
517
0
    UINT64_C(0),
518
0
    UINT64_C(0),
519
0
    UINT64_C(0),
520
0
    UINT64_C(0),
521
0
    UINT64_C(0),
522
0
    UINT64_C(0),
523
0
    UINT64_C(0),
524
0
    UINT64_C(0),
525
0
    UINT64_C(0),
526
0
    UINT64_C(0),
527
0
    UINT64_C(0),
528
0
    UINT64_C(0),
529
0
    UINT64_C(0),
530
0
    UINT64_C(0),
531
0
    UINT64_C(0),
532
0
    UINT64_C(0),
533
0
    UINT64_C(0),
534
0
    UINT64_C(0),
535
0
    UINT64_C(0),
536
0
    UINT64_C(0),
537
0
    UINT64_C(0),
538
0
    UINT64_C(0),
539
0
    UINT64_C(0),
540
0
    UINT64_C(0),
541
0
    UINT64_C(0),
542
0
    UINT64_C(0),
543
0
    UINT64_C(0),
544
0
    UINT64_C(0),
545
0
    UINT64_C(0),
546
0
    UINT64_C(0),
547
0
    UINT64_C(0),
548
0
    UINT64_C(0),
549
0
    UINT64_C(0),
550
0
    UINT64_C(0),
551
0
    UINT64_C(0),
552
0
    UINT64_C(0),
553
0
    UINT64_C(0),
554
0
    UINT64_C(0),
555
0
    UINT64_C(0),
556
0
    UINT64_C(0),
557
0
    UINT64_C(0),
558
0
    UINT64_C(0),
559
0
    UINT64_C(0),
560
0
    UINT64_C(0),
561
0
    UINT64_C(0),
562
0
    UINT64_C(0),
563
0
    UINT64_C(0),
564
0
    UINT64_C(0),
565
0
    UINT64_C(0),
566
0
    UINT64_C(0),
567
0
    UINT64_C(0),
568
0
    UINT64_C(0),
569
0
    UINT64_C(0),
570
0
    UINT64_C(0),
571
0
    UINT64_C(0),
572
0
    UINT64_C(0),
573
0
    UINT64_C(0),
574
0
    UINT64_C(0),
575
0
    UINT64_C(0),
576
0
    UINT64_C(0),
577
0
    UINT64_C(0),
578
0
    UINT64_C(0),
579
0
    UINT64_C(0),
580
0
    UINT64_C(0),
581
0
    UINT64_C(0),
582
0
    UINT64_C(0),
583
0
    UINT64_C(0),
584
0
    UINT64_C(0),
585
0
    UINT64_C(0),
586
0
    UINT64_C(0),
587
0
    UINT64_C(0),
588
0
    UINT64_C(0),
589
0
    UINT64_C(0),
590
0
    UINT64_C(0),
591
0
    UINT64_C(0),
592
0
    UINT64_C(0),
593
0
    UINT64_C(0),
594
0
    UINT64_C(0),
595
0
    UINT64_C(0),
596
0
    UINT64_C(0),
597
0
    UINT64_C(0),
598
0
    UINT64_C(0),
599
0
    UINT64_C(0),
600
0
    UINT64_C(0),
601
0
    UINT64_C(0),
602
0
    UINT64_C(0),
603
0
    UINT64_C(0),
604
0
    UINT64_C(0),
605
0
    UINT64_C(0),
606
0
    UINT64_C(0),
607
0
    UINT64_C(0),
608
0
    UINT64_C(0),
609
0
    UINT64_C(0),
610
0
    UINT64_C(0),
611
0
    UINT64_C(0),
612
0
    UINT64_C(0),
613
0
    UINT64_C(0),
614
0
    UINT64_C(0),
615
0
    UINT64_C(0),
616
0
    UINT64_C(0),
617
0
    UINT64_C(0),
618
0
    UINT64_C(0),
619
0
    UINT64_C(0),
620
0
    UINT64_C(0),
621
0
    UINT64_C(0),
622
0
    UINT64_C(0),
623
0
    UINT64_C(0),
624
0
    UINT64_C(0),
625
0
    UINT64_C(0),
626
0
    UINT64_C(0),
627
0
    UINT64_C(0),
628
0
    UINT64_C(0),
629
0
    UINT64_C(0),
630
0
    UINT64_C(0),
631
0
    UINT64_C(0),
632
0
    UINT64_C(0),
633
0
    UINT64_C(0),
634
0
    UINT64_C(0),
635
0
    UINT64_C(0),
636
0
    UINT64_C(0),
637
0
    UINT64_C(0),
638
0
    UINT64_C(0),
639
0
    UINT64_C(0),
640
0
    UINT64_C(0),
641
0
    UINT64_C(0),
642
0
    UINT64_C(0),
643
0
    UINT64_C(0),
644
0
    UINT64_C(0),
645
0
    UINT64_C(0),
646
0
    UINT64_C(0),
647
0
    UINT64_C(0),
648
0
    UINT64_C(0),
649
0
    UINT64_C(0),
650
0
    UINT64_C(0),
651
0
    UINT64_C(0),
652
0
    UINT64_C(0),
653
0
    UINT64_C(0),
654
0
    UINT64_C(0),
655
0
    UINT64_C(0),
656
0
    UINT64_C(0),
657
0
    UINT64_C(0),
658
0
    UINT64_C(0),
659
0
    UINT64_C(0),
660
0
    UINT64_C(0),
661
0
    UINT64_C(0),
662
0
    UINT64_C(0),
663
0
    UINT64_C(0),
664
0
    UINT64_C(0),
665
0
    UINT64_C(0),
666
0
    UINT64_C(0),
667
0
    UINT64_C(0),
668
0
    UINT64_C(0),
669
0
    UINT64_C(0),
670
0
    UINT64_C(0),
671
0
    UINT64_C(0),
672
0
    UINT64_C(0),
673
0
    UINT64_C(0),
674
0
    UINT64_C(0),
675
0
    UINT64_C(0),
676
0
    UINT64_C(0),
677
0
    UINT64_C(0),
678
0
    UINT64_C(0),
679
0
    UINT64_C(0),
680
0
    UINT64_C(0),
681
0
    UINT64_C(0),
682
0
    UINT64_C(0),
683
0
    UINT64_C(0),
684
0
    UINT64_C(0),
685
0
    UINT64_C(0),
686
0
    UINT64_C(0),
687
0
    UINT64_C(0),
688
0
    UINT64_C(0),
689
0
    UINT64_C(0),
690
0
    UINT64_C(0),
691
0
    UINT64_C(0),
692
0
    UINT64_C(0),
693
0
    UINT64_C(0),
694
0
    UINT64_C(0),
695
0
    UINT64_C(0),
696
0
    UINT64_C(0),
697
0
    UINT64_C(0),
698
0
    UINT64_C(0),
699
0
    UINT64_C(0),
700
0
    UINT64_C(0),
701
0
    UINT64_C(0),
702
0
    UINT64_C(0),
703
0
    UINT64_C(0),
704
0
    UINT64_C(0),
705
0
    UINT64_C(0),
706
0
    UINT64_C(0),
707
0
    UINT64_C(0),
708
0
    UINT64_C(0),
709
0
    UINT64_C(0),
710
0
    UINT64_C(0),
711
0
    UINT64_C(0),
712
0
    UINT64_C(0),
713
0
    UINT64_C(0),
714
0
    UINT64_C(0),
715
0
    UINT64_C(0),
716
0
    UINT64_C(0),
717
0
    UINT64_C(0),
718
0
    UINT64_C(0),
719
0
    UINT64_C(0),
720
0
    UINT64_C(0),
721
0
    UINT64_C(0),
722
0
    UINT64_C(0),
723
0
    UINT64_C(0),
724
0
    UINT64_C(0),
725
0
    UINT64_C(0),
726
0
    UINT64_C(0),
727
0
    UINT64_C(0),
728
0
    UINT64_C(0),
729
0
    UINT64_C(0),
730
0
    UINT64_C(0),
731
0
    UINT64_C(0),
732
0
    UINT64_C(0),
733
0
    UINT64_C(0),
734
0
    UINT64_C(0),
735
0
    UINT64_C(0),
736
0
    UINT64_C(0),
737
0
    UINT64_C(0),
738
0
    UINT64_C(0),
739
0
    UINT64_C(0),
740
0
    UINT64_C(0),
741
0
    UINT64_C(0),
742
0
    UINT64_C(2080375378), // ABSQ_S_PH
743
0
    UINT64_C(4412), // ABSQ_S_PH_MM
744
0
    UINT64_C(2080374866), // ABSQ_S_QB
745
0
    UINT64_C(316),  // ABSQ_S_QB_MMR2
746
0
    UINT64_C(2080375890), // ABSQ_S_W
747
0
    UINT64_C(8508), // ABSQ_S_W_MM
748
0
    UINT64_C(32), // ADD
749
0
    UINT64_C(3959422976), // ADDIUPC
750
0
    UINT64_C(2013265920), // ADDIUPC_MM
751
0
    UINT64_C(2013265920), // ADDIUPC_MMR6
752
0
    UINT64_C(27649),  // ADDIUR1SP_MM
753
0
    UINT64_C(27648),  // ADDIUR2_MM
754
0
    UINT64_C(19456),  // ADDIUS5_MM
755
0
    UINT64_C(19457),  // ADDIUSP_MM
756
0
    UINT64_C(805306368),  // ADDIU_MMR6
757
0
    UINT64_C(2080375320), // ADDQH_PH
758
0
    UINT64_C(77), // ADDQH_PH_MMR2
759
0
    UINT64_C(2080375448), // ADDQH_R_PH
760
0
    UINT64_C(1101), // ADDQH_R_PH_MMR2
761
0
    UINT64_C(2080375960), // ADDQH_R_W
762
0
    UINT64_C(1165), // ADDQH_R_W_MMR2
763
0
    UINT64_C(2080375832), // ADDQH_W
764
0
    UINT64_C(141),  // ADDQH_W_MMR2
765
0
    UINT64_C(2080375440), // ADDQ_PH
766
0
    UINT64_C(13), // ADDQ_PH_MM
767
0
    UINT64_C(2080375696), // ADDQ_S_PH
768
0
    UINT64_C(1037), // ADDQ_S_PH_MM
769
0
    UINT64_C(2080376208), // ADDQ_S_W
770
0
    UINT64_C(773),  // ADDQ_S_W_MM
771
0
    UINT64_C(1186988056), // ADDR_PS64
772
0
    UINT64_C(2080375824), // ADDSC
773
0
    UINT64_C(901),  // ADDSC_MM
774
0
    UINT64_C(2021654544), // ADDS_A_B
775
0
    UINT64_C(2027946000), // ADDS_A_D
776
0
    UINT64_C(2023751696), // ADDS_A_H
777
0
    UINT64_C(2025848848), // ADDS_A_W
778
0
    UINT64_C(2030043152), // ADDS_S_B
779
0
    UINT64_C(2036334608), // ADDS_S_D
780
0
    UINT64_C(2032140304), // ADDS_S_H
781
0
    UINT64_C(2034237456), // ADDS_S_W
782
0
    UINT64_C(2038431760), // ADDS_U_B
783
0
    UINT64_C(2044723216), // ADDS_U_D
784
0
    UINT64_C(2040528912), // ADDS_U_H
785
0
    UINT64_C(2042626064), // ADDS_U_W
786
0
    UINT64_C(1024), // ADDU16_MM
787
0
    UINT64_C(1024), // ADDU16_MMR6
788
0
    UINT64_C(2080374808), // ADDUH_QB
789
0
    UINT64_C(333),  // ADDUH_QB_MMR2
790
0
    UINT64_C(2080374936), // ADDUH_R_QB
791
0
    UINT64_C(1357), // ADDUH_R_QB_MMR2
792
0
    UINT64_C(336),  // ADDU_MMR6
793
0
    UINT64_C(2080375312), // ADDU_PH
794
0
    UINT64_C(269),  // ADDU_PH_MMR2
795
0
    UINT64_C(2080374800), // ADDU_QB
796
0
    UINT64_C(205),  // ADDU_QB_MM
797
0
    UINT64_C(2080375568), // ADDU_S_PH
798
0
    UINT64_C(1293), // ADDU_S_PH_MMR2
799
0
    UINT64_C(2080375056), // ADDU_S_QB
800
0
    UINT64_C(1229), // ADDU_S_QB_MM
801
0
    UINT64_C(2013265926), // ADDVI_B
802
0
    UINT64_C(2019557382), // ADDVI_D
803
0
    UINT64_C(2015363078), // ADDVI_H
804
0
    UINT64_C(2017460230), // ADDVI_W
805
0
    UINT64_C(2013265934), // ADDV_B
806
0
    UINT64_C(2019557390), // ADDV_D
807
0
    UINT64_C(2015363086), // ADDV_H
808
0
    UINT64_C(2017460238), // ADDV_W
809
0
    UINT64_C(2080375888), // ADDWC
810
0
    UINT64_C(965),  // ADDWC_MM
811
0
    UINT64_C(2013265936), // ADD_A_B
812
0
    UINT64_C(2019557392), // ADD_A_D
813
0
    UINT64_C(2015363088), // ADD_A_H
814
0
    UINT64_C(2017460240), // ADD_A_W
815
0
    UINT64_C(272),  // ADD_MM
816
0
    UINT64_C(272),  // ADD_MMR6
817
0
    UINT64_C(536870912),  // ADDi
818
0
    UINT64_C(268435456),  // ADDi_MM
819
0
    UINT64_C(603979776),  // ADDiu
820
0
    UINT64_C(805306368),  // ADDiu_MM
821
0
    UINT64_C(33), // ADDu
822
0
    UINT64_C(336),  // ADDu_MM
823
0
    UINT64_C(2080375328), // ALIGN
824
0
    UINT64_C(31), // ALIGN_MMR6
825
0
    UINT64_C(3961454592), // ALUIPC
826
0
    UINT64_C(2015297536), // ALUIPC_MMR6
827
0
    UINT64_C(36), // AND
828
0
    UINT64_C(17536),  // AND16_MM
829
0
    UINT64_C(17409),  // AND16_MMR6
830
0
    UINT64_C(36), // AND64
831
0
    UINT64_C(11264),  // ANDI16_MM
832
0
    UINT64_C(11264),  // ANDI16_MMR6
833
0
    UINT64_C(2013265920), // ANDI_B
834
0
    UINT64_C(3489660928), // ANDI_MMR6
835
0
    UINT64_C(592),  // AND_MM
836
0
    UINT64_C(592),  // AND_MMR6
837
0
    UINT64_C(2013265950), // AND_V
838
0
    UINT64_C(805306368),  // ANDi
839
0
    UINT64_C(805306368),  // ANDi64
840
0
    UINT64_C(3489660928), // ANDi_MM
841
0
    UINT64_C(2080374833), // APPEND
842
0
    UINT64_C(533),  // APPEND_MMR2
843
0
    UINT64_C(2046820369), // ASUB_S_B
844
0
    UINT64_C(2053111825), // ASUB_S_D
845
0
    UINT64_C(2048917521), // ASUB_S_H
846
0
    UINT64_C(2051014673), // ASUB_S_W
847
0
    UINT64_C(2055208977), // ASUB_U_B
848
0
    UINT64_C(2061500433), // ASUB_U_D
849
0
    UINT64_C(2057306129), // ASUB_U_H
850
0
    UINT64_C(2059403281), // ASUB_U_W
851
0
    UINT64_C(1006632960), // AUI
852
0
    UINT64_C(3961389056), // AUIPC
853
0
    UINT64_C(2015232000), // AUIPC_MMR6
854
0
    UINT64_C(268435456),  // AUI_MMR6
855
0
    UINT64_C(2063597584), // AVER_S_B
856
0
    UINT64_C(2069889040), // AVER_S_D
857
0
    UINT64_C(2065694736), // AVER_S_H
858
0
    UINT64_C(2067791888), // AVER_S_W
859
0
    UINT64_C(2071986192), // AVER_U_B
860
0
    UINT64_C(2078277648), // AVER_U_D
861
0
    UINT64_C(2074083344), // AVER_U_H
862
0
    UINT64_C(2076180496), // AVER_U_W
863
0
    UINT64_C(2046820368), // AVE_S_B
864
0
    UINT64_C(2053111824), // AVE_S_D
865
0
    UINT64_C(2048917520), // AVE_S_H
866
0
    UINT64_C(2051014672), // AVE_S_W
867
0
    UINT64_C(2055208976), // AVE_U_B
868
0
    UINT64_C(2061500432), // AVE_U_D
869
0
    UINT64_C(2057306128), // AVE_U_H
870
0
    UINT64_C(2059403280), // AVE_U_W
871
0
    UINT64_C(4026550272), // AddiuRxImmX16
872
0
    UINT64_C(4026533888), // AddiuRxPcImmX16
873
0
    UINT64_C(18432),  // AddiuRxRxImm16
874
0
    UINT64_C(4026550272), // AddiuRxRxImmX16
875
0
    UINT64_C(4026548224), // AddiuRxRyOffMemX16
876
0
    UINT64_C(25344),  // AddiuSpImm16
877
0
    UINT64_C(4026544896), // AddiuSpImmX16
878
0
    UINT64_C(57345),  // AdduRxRyRz16
879
0
    UINT64_C(59404),  // AndRxRxRy16
880
0
    UINT64_C(52224),  // B16_MM
881
0
    UINT64_C(1879048232), // BADDu
882
0
    UINT64_C(68222976), // BAL
883
0
    UINT64_C(3892314112), // BALC
884
0
    UINT64_C(3019898880), // BALC_MMR6
885
0
    UINT64_C(2080375857), // BALIGN
886
0
    UINT64_C(2236), // BALIGN_MMR2
887
0
    UINT64_C(3355443200), // BBIT0
888
0
    UINT64_C(3623878656), // BBIT032
889
0
    UINT64_C(3892314112), // BBIT1
890
0
    UINT64_C(4160749568), // BBIT132
891
0
    UINT64_C(3355443200), // BC
892
0
    UINT64_C(52224),  // BC16_MMR6
893
0
    UINT64_C(1159725056), // BC1EQZ
894
0
    UINT64_C(1090519040), // BC1EQZC_MMR6
895
0
    UINT64_C(1157627904), // BC1F
896
0
    UINT64_C(1157758976), // BC1FL
897
0
    UINT64_C(1132462080), // BC1F_MM
898
0
    UINT64_C(1168113664), // BC1NEZ
899
0
    UINT64_C(1092616192), // BC1NEZC_MMR6
900
0
    UINT64_C(1157693440), // BC1T
901
0
    UINT64_C(1157824512), // BC1TL
902
0
    UINT64_C(1134559232), // BC1T_MM
903
0
    UINT64_C(1226833920), // BC2EQZ
904
0
    UINT64_C(1094713344), // BC2EQZC_MMR6
905
0
    UINT64_C(1235222528), // BC2NEZ
906
0
    UINT64_C(1096810496), // BC2NEZC_MMR6
907
0
    UINT64_C(2045771785), // BCLRI_B
908
0
    UINT64_C(2038431753), // BCLRI_D
909
0
    UINT64_C(2044723209), // BCLRI_H
910
0
    UINT64_C(2042626057), // BCLRI_W
911
0
    UINT64_C(2038431757), // BCLR_B
912
0
    UINT64_C(2044723213), // BCLR_D
913
0
    UINT64_C(2040528909), // BCLR_H
914
0
    UINT64_C(2042626061), // BCLR_W
915
0
    UINT64_C(2483027968), // BC_MMR6
916
0
    UINT64_C(268435456),  // BEQ
917
0
    UINT64_C(268435456),  // BEQ64
918
0
    UINT64_C(536870912),  // BEQC
919
0
    UINT64_C(536870912),  // BEQC64
920
0
    UINT64_C(1946157056), // BEQC_MMR6
921
0
    UINT64_C(1342177280), // BEQL
922
0
    UINT64_C(35840),  // BEQZ16_MM
923
0
    UINT64_C(536870912),  // BEQZALC
924
0
    UINT64_C(1946157056), // BEQZALC_MMR6
925
0
    UINT64_C(3623878656), // BEQZC
926
0
    UINT64_C(35840),  // BEQZC16_MMR6
927
0
    UINT64_C(3623878656), // BEQZC64
928
0
    UINT64_C(1088421888), // BEQZC_MM
929
0
    UINT64_C(2147483648), // BEQZC_MMR6
930
0
    UINT64_C(2483027968), // BEQ_MM
931
0
    UINT64_C(1476395008), // BGEC
932
0
    UINT64_C(1476395008), // BGEC64
933
0
    UINT64_C(4093640704), // BGEC_MMR6
934
0
    UINT64_C(402653184),  // BGEUC
935
0
    UINT64_C(402653184),  // BGEUC64
936
0
    UINT64_C(3221225472), // BGEUC_MMR6
937
0
    UINT64_C(67174400), // BGEZ
938
0
    UINT64_C(67174400), // BGEZ64
939
0
    UINT64_C(68222976), // BGEZAL
940
0
    UINT64_C(402653184),  // BGEZALC
941
0
    UINT64_C(3221225472), // BGEZALC_MMR6
942
0
    UINT64_C(68354048), // BGEZALL
943
0
    UINT64_C(1113587712), // BGEZALS_MM
944
0
    UINT64_C(1080033280), // BGEZAL_MM
945
0
    UINT64_C(1476395008), // BGEZC
946
0
    UINT64_C(1476395008), // BGEZC64
947
0
    UINT64_C(4093640704), // BGEZC_MMR6
948
0
    UINT64_C(67305472), // BGEZL
949
0
    UINT64_C(1077936128), // BGEZ_MM
950
0
    UINT64_C(469762048),  // BGTZ
951
0
    UINT64_C(469762048),  // BGTZ64
952
0
    UINT64_C(469762048),  // BGTZALC
953
0
    UINT64_C(3758096384), // BGTZALC_MMR6
954
0
    UINT64_C(1543503872), // BGTZC
955
0
    UINT64_C(1543503872), // BGTZC64
956
0
    UINT64_C(3556769792), // BGTZC_MMR6
957
0
    UINT64_C(1543503872), // BGTZL
958
0
    UINT64_C(1086324736), // BGTZ_MM
959
0
    UINT64_C(2070937609), // BINSLI_B
960
0
    UINT64_C(2063597577), // BINSLI_D
961
0
    UINT64_C(2069889033), // BINSLI_H
962
0
    UINT64_C(2067791881), // BINSLI_W
963
0
    UINT64_C(2063597581), // BINSL_B
964
0
    UINT64_C(2069889037), // BINSL_D
965
0
    UINT64_C(2065694733), // BINSL_H
966
0
    UINT64_C(2067791885), // BINSL_W
967
0
    UINT64_C(2079326217), // BINSRI_B
968
0
    UINT64_C(2071986185), // BINSRI_D
969
0
    UINT64_C(2078277641), // BINSRI_H
970
0
    UINT64_C(2076180489), // BINSRI_W
971
0
    UINT64_C(2071986189), // BINSR_B
972
0
    UINT64_C(2078277645), // BINSR_D
973
0
    UINT64_C(2074083341), // BINSR_H
974
0
    UINT64_C(2076180493), // BINSR_W
975
0
    UINT64_C(2080376530), // BITREV
976
0
    UINT64_C(12604),  // BITREV_MM
977
0
    UINT64_C(2080374816), // BITSWAP
978
0
    UINT64_C(2876), // BITSWAP_MMR6
979
0
    UINT64_C(402653184),  // BLEZ
980
0
    UINT64_C(402653184),  // BLEZ64
981
0
    UINT64_C(402653184),  // BLEZALC
982
0
    UINT64_C(3221225472), // BLEZALC_MMR6
983
0
    UINT64_C(1476395008), // BLEZC
984
0
    UINT64_C(1476395008), // BLEZC64
985
0
    UINT64_C(4093640704), // BLEZC_MMR6
986
0
    UINT64_C(1476395008), // BLEZL
987
0
    UINT64_C(1082130432), // BLEZ_MM
988
0
    UINT64_C(1543503872), // BLTC
989
0
    UINT64_C(1543503872), // BLTC64
990
0
    UINT64_C(3556769792), // BLTC_MMR6
991
0
    UINT64_C(469762048),  // BLTUC
992
0
    UINT64_C(469762048),  // BLTUC64
993
0
    UINT64_C(3758096384), // BLTUC_MMR6
994
0
    UINT64_C(67108864), // BLTZ
995
0
    UINT64_C(67108864), // BLTZ64
996
0
    UINT64_C(68157440), // BLTZAL
997
0
    UINT64_C(469762048),  // BLTZALC
998
0
    UINT64_C(3758096384), // BLTZALC_MMR6
999
0
    UINT64_C(68288512), // BLTZALL
1000
0
    UINT64_C(1109393408), // BLTZALS_MM
1001
0
    UINT64_C(1075838976), // BLTZAL_MM
1002
0
    UINT64_C(1543503872), // BLTZC
1003
0
    UINT64_C(1543503872), // BLTZC64
1004
0
    UINT64_C(3556769792), // BLTZC_MMR6
1005
0
    UINT64_C(67239936), // BLTZL
1006
0
    UINT64_C(1073741824), // BLTZ_MM
1007
0
    UINT64_C(2013265921), // BMNZI_B
1008
0
    UINT64_C(2021654558), // BMNZ_V
1009
0
    UINT64_C(2030043137), // BMZI_B
1010
0
    UINT64_C(2023751710), // BMZ_V
1011
0
    UINT64_C(335544320),  // BNE
1012
0
    UINT64_C(335544320),  // BNE64
1013
0
    UINT64_C(1610612736), // BNEC
1014
0
    UINT64_C(1610612736), // BNEC64
1015
0
    UINT64_C(2080374784), // BNEC_MMR6
1016
0
    UINT64_C(2062549001), // BNEGI_B
1017
0
    UINT64_C(2055208969), // BNEGI_D
1018
0
    UINT64_C(2061500425), // BNEGI_H
1019
0
    UINT64_C(2059403273), // BNEGI_W
1020
0
    UINT64_C(2055208973), // BNEG_B
1021
0
    UINT64_C(2061500429), // BNEG_D
1022
0
    UINT64_C(2057306125), // BNEG_H
1023
0
    UINT64_C(2059403277), // BNEG_W
1024
0
    UINT64_C(1409286144), // BNEL
1025
0
    UINT64_C(44032),  // BNEZ16_MM
1026
0
    UINT64_C(1610612736), // BNEZALC
1027
0
    UINT64_C(2080374784), // BNEZALC_MMR6
1028
0
    UINT64_C(4160749568), // BNEZC
1029
0
    UINT64_C(44032),  // BNEZC16_MMR6
1030
0
    UINT64_C(4160749568), // BNEZC64
1031
0
    UINT64_C(1084227584), // BNEZC_MM
1032
0
    UINT64_C(2684354560), // BNEZC_MMR6
1033
0
    UINT64_C(3019898880), // BNE_MM
1034
0
    UINT64_C(1610612736), // BNVC
1035
0
    UINT64_C(2080374784), // BNVC_MMR6
1036
0
    UINT64_C(1199570944), // BNZ_B
1037
0
    UINT64_C(1205862400), // BNZ_D
1038
0
    UINT64_C(1201668096), // BNZ_H
1039
0
    UINT64_C(1172307968), // BNZ_V
1040
0
    UINT64_C(1203765248), // BNZ_W
1041
0
    UINT64_C(536870912),  // BOVC
1042
0
    UINT64_C(1946157056), // BOVC_MMR6
1043
0
    UINT64_C(68943872), // BPOSGE32
1044
0
    UINT64_C(1126170624), // BPOSGE32C_MMR3
1045
0
    UINT64_C(1130364928), // BPOSGE32_MM
1046
0
    UINT64_C(13), // BREAK
1047
0
    UINT64_C(18048),  // BREAK16_MM
1048
0
    UINT64_C(17435),  // BREAK16_MMR6
1049
0
    UINT64_C(7),  // BREAK_MM
1050
0
    UINT64_C(7),  // BREAK_MMR6
1051
0
    UINT64_C(2046820353), // BSELI_B
1052
0
    UINT64_C(2025848862), // BSEL_V
1053
0
    UINT64_C(2054160393), // BSETI_B
1054
0
    UINT64_C(2046820361), // BSETI_D
1055
0
    UINT64_C(2053111817), // BSETI_H
1056
0
    UINT64_C(2051014665), // BSETI_W
1057
0
    UINT64_C(2046820365), // BSET_B
1058
0
    UINT64_C(2053111821), // BSET_D
1059
0
    UINT64_C(2048917517), // BSET_H
1060
0
    UINT64_C(2051014669), // BSET_W
1061
0
    UINT64_C(1191182336), // BZ_B
1062
0
    UINT64_C(1197473792), // BZ_D
1063
0
    UINT64_C(1193279488), // BZ_H
1064
0
    UINT64_C(1163919360), // BZ_V
1065
0
    UINT64_C(1195376640), // BZ_W
1066
0
    UINT64_C(8192), // BeqzRxImm16
1067
0
    UINT64_C(4026540032), // BeqzRxImmX16
1068
0
    UINT64_C(4096), // Bimm16
1069
0
    UINT64_C(4026535936), // BimmX16
1070
0
    UINT64_C(10240),  // BnezRxImm16
1071
0
    UINT64_C(4026542080), // BnezRxImmX16
1072
0
    UINT64_C(59397),  // Break16
1073
0
    UINT64_C(24576),  // Bteqz16
1074
0
    UINT64_C(4026544128), // BteqzX16
1075
0
    UINT64_C(24832),  // Btnez16
1076
0
    UINT64_C(4026544384), // BtnezX16
1077
0
    UINT64_C(3154116608), // CACHE
1078
0
    UINT64_C(2080374811), // CACHEE
1079
0
    UINT64_C(1610655232), // CACHEE_MM
1080
0
    UINT64_C(536895488),  // CACHE_MM
1081
0
    UINT64_C(536895488),  // CACHE_MMR6
1082
0
    UINT64_C(2080374821), // CACHE_R6
1083
0
    UINT64_C(1176502282), // CEIL_L_D64
1084
0
    UINT64_C(1409307451), // CEIL_L_D_MMR6
1085
0
    UINT64_C(1174405130), // CEIL_L_S
1086
0
    UINT64_C(1409291067), // CEIL_L_S_MMR6
1087
0
    UINT64_C(1176502286), // CEIL_W_D32
1088
0
    UINT64_C(1176502286), // CEIL_W_D64
1089
0
    UINT64_C(1409309499), // CEIL_W_D_MMR6
1090
0
    UINT64_C(1409309499), // CEIL_W_MM
1091
0
    UINT64_C(1174405134), // CEIL_W_S
1092
0
    UINT64_C(1409293115), // CEIL_W_S_MM
1093
0
    UINT64_C(1409293115), // CEIL_W_S_MMR6
1094
0
    UINT64_C(2013265927), // CEQI_B
1095
0
    UINT64_C(2019557383), // CEQI_D
1096
0
    UINT64_C(2015363079), // CEQI_H
1097
0
    UINT64_C(2017460231), // CEQI_W
1098
0
    UINT64_C(2013265935), // CEQ_B
1099
0
    UINT64_C(2019557391), // CEQ_D
1100
0
    UINT64_C(2015363087), // CEQ_H
1101
0
    UINT64_C(2017460239), // CEQ_W
1102
0
    UINT64_C(1145044992), // CFC1
1103
0
    UINT64_C(1409290299), // CFC1_MM
1104
0
    UINT64_C(52540),  // CFC2_MM
1105
0
    UINT64_C(2021523481), // CFCMSA
1106
0
    UINT64_C(1879048242), // CINS
1107
0
    UINT64_C(1879048243), // CINS32
1108
0
    UINT64_C(1879048242), // CINS64_32
1109
0
    UINT64_C(1879048242), // CINS_i32
1110
0
    UINT64_C(1176502299), // CLASS_D
1111
0
    UINT64_C(1409286752), // CLASS_D_MMR6
1112
0
    UINT64_C(1174405147), // CLASS_S
1113
0
    UINT64_C(1409286240), // CLASS_S_MMR6
1114
0
    UINT64_C(2046820359), // CLEI_S_B
1115
0
    UINT64_C(2053111815), // CLEI_S_D
1116
0
    UINT64_C(2048917511), // CLEI_S_H
1117
0
    UINT64_C(2051014663), // CLEI_S_W
1118
0
    UINT64_C(2055208967), // CLEI_U_B
1119
0
    UINT64_C(2061500423), // CLEI_U_D
1120
0
    UINT64_C(2057306119), // CLEI_U_H
1121
0
    UINT64_C(2059403271), // CLEI_U_W
1122
0
    UINT64_C(2046820367), // CLE_S_B
1123
0
    UINT64_C(2053111823), // CLE_S_D
1124
0
    UINT64_C(2048917519), // CLE_S_H
1125
0
    UINT64_C(2051014671), // CLE_S_W
1126
0
    UINT64_C(2055208975), // CLE_U_B
1127
0
    UINT64_C(2061500431), // CLE_U_D
1128
0
    UINT64_C(2057306127), // CLE_U_H
1129
0
    UINT64_C(2059403279), // CLE_U_W
1130
0
    UINT64_C(1879048225), // CLO
1131
0
    UINT64_C(19260),  // CLO_MM
1132
0
    UINT64_C(19260),  // CLO_MMR6
1133
0
    UINT64_C(81), // CLO_R6
1134
0
    UINT64_C(2030043143), // CLTI_S_B
1135
0
    UINT64_C(2036334599), // CLTI_S_D
1136
0
    UINT64_C(2032140295), // CLTI_S_H
1137
0
    UINT64_C(2034237447), // CLTI_S_W
1138
0
    UINT64_C(2038431751), // CLTI_U_B
1139
0
    UINT64_C(2044723207), // CLTI_U_D
1140
0
    UINT64_C(2040528903), // CLTI_U_H
1141
0
    UINT64_C(2042626055), // CLTI_U_W
1142
0
    UINT64_C(2030043151), // CLT_S_B
1143
0
    UINT64_C(2036334607), // CLT_S_D
1144
0
    UINT64_C(2032140303), // CLT_S_H
1145
0
    UINT64_C(2034237455), // CLT_S_W
1146
0
    UINT64_C(2038431759), // CLT_U_B
1147
0
    UINT64_C(2044723215), // CLT_U_D
1148
0
    UINT64_C(2040528911), // CLT_U_H
1149
0
    UINT64_C(2042626063), // CLT_U_W
1150
0
    UINT64_C(1879048224), // CLZ
1151
0
    UINT64_C(23356),  // CLZ_MM
1152
0
    UINT64_C(80), // CLZ_MMR6
1153
0
    UINT64_C(80), // CLZ_R6
1154
0
    UINT64_C(2080376337), // CMPGDU_EQ_QB
1155
0
    UINT64_C(389),  // CMPGDU_EQ_QB_MMR2
1156
0
    UINT64_C(2080376465), // CMPGDU_LE_QB
1157
0
    UINT64_C(517),  // CMPGDU_LE_QB_MMR2
1158
0
    UINT64_C(2080376401), // CMPGDU_LT_QB
1159
0
    UINT64_C(453),  // CMPGDU_LT_QB_MMR2
1160
0
    UINT64_C(2080375057), // CMPGU_EQ_QB
1161
0
    UINT64_C(1476395205), // CMPGU_EQ_QB_MM
1162
0
    UINT64_C(2080375185), // CMPGU_LE_QB
1163
0
    UINT64_C(1476395333), // CMPGU_LE_QB_MM
1164
0
    UINT64_C(2080375121), // CMPGU_LT_QB
1165
0
    UINT64_C(1476395269), // CMPGU_LT_QB_MM
1166
0
    UINT64_C(2080374801), // CMPU_EQ_QB
1167
0
    UINT64_C(581),  // CMPU_EQ_QB_MM
1168
0
    UINT64_C(2080374929), // CMPU_LE_QB
1169
0
    UINT64_C(709),  // CMPU_LE_QB_MM
1170
0
    UINT64_C(2080374865), // CMPU_LT_QB
1171
0
    UINT64_C(645),  // CMPU_LT_QB_MM
1172
0
    UINT64_C(1409286165), // CMP_AF_D_MMR6
1173
0
    UINT64_C(1409286149), // CMP_AF_S_MMR6
1174
0
    UINT64_C(1184890882), // CMP_EQ_D
1175
0
    UINT64_C(1409286293), // CMP_EQ_D_MMR6
1176
0
    UINT64_C(2080375313), // CMP_EQ_PH
1177
0
    UINT64_C(5),  // CMP_EQ_PH_MM
1178
0
    UINT64_C(1182793730), // CMP_EQ_S
1179
0
    UINT64_C(1409286277), // CMP_EQ_S_MMR6
1180
0
    UINT64_C(1184890880), // CMP_F_D
1181
0
    UINT64_C(1182793728), // CMP_F_S
1182
0
    UINT64_C(1184890886), // CMP_LE_D
1183
0
    UINT64_C(1409286549), // CMP_LE_D_MMR6
1184
0
    UINT64_C(2080375441), // CMP_LE_PH
1185
0
    UINT64_C(133),  // CMP_LE_PH_MM
1186
0
    UINT64_C(1182793734), // CMP_LE_S
1187
0
    UINT64_C(1409286533), // CMP_LE_S_MMR6
1188
0
    UINT64_C(1184890884), // CMP_LT_D
1189
0
    UINT64_C(1409286421), // CMP_LT_D_MMR6
1190
0
    UINT64_C(2080375377), // CMP_LT_PH
1191
0
    UINT64_C(69), // CMP_LT_PH_MM
1192
0
    UINT64_C(1182793732), // CMP_LT_S
1193
0
    UINT64_C(1409286405), // CMP_LT_S_MMR6
1194
0
    UINT64_C(1184890888), // CMP_SAF_D
1195
0
    UINT64_C(1409286677), // CMP_SAF_D_MMR6
1196
0
    UINT64_C(1182793736), // CMP_SAF_S
1197
0
    UINT64_C(1409286661), // CMP_SAF_S_MMR6
1198
0
    UINT64_C(1184890890), // CMP_SEQ_D
1199
0
    UINT64_C(1409286805), // CMP_SEQ_D_MMR6
1200
0
    UINT64_C(1182793738), // CMP_SEQ_S
1201
0
    UINT64_C(1409286789), // CMP_SEQ_S_MMR6
1202
0
    UINT64_C(1184890894), // CMP_SLE_D
1203
0
    UINT64_C(1409287061), // CMP_SLE_D_MMR6
1204
0
    UINT64_C(1182793742), // CMP_SLE_S
1205
0
    UINT64_C(1409287045), // CMP_SLE_S_MMR6
1206
0
    UINT64_C(1184890892), // CMP_SLT_D
1207
0
    UINT64_C(1409286933), // CMP_SLT_D_MMR6
1208
0
    UINT64_C(1182793740), // CMP_SLT_S
1209
0
    UINT64_C(1409286917), // CMP_SLT_S_MMR6
1210
0
    UINT64_C(1184890891), // CMP_SUEQ_D
1211
0
    UINT64_C(1409286869), // CMP_SUEQ_D_MMR6
1212
0
    UINT64_C(1182793739), // CMP_SUEQ_S
1213
0
    UINT64_C(1409286853), // CMP_SUEQ_S_MMR6
1214
0
    UINT64_C(1184890895), // CMP_SULE_D
1215
0
    UINT64_C(1409287125), // CMP_SULE_D_MMR6
1216
0
    UINT64_C(1182793743), // CMP_SULE_S
1217
0
    UINT64_C(1409287109), // CMP_SULE_S_MMR6
1218
0
    UINT64_C(1184890893), // CMP_SULT_D
1219
0
    UINT64_C(1409286997), // CMP_SULT_D_MMR6
1220
0
    UINT64_C(1182793741), // CMP_SULT_S
1221
0
    UINT64_C(1409286981), // CMP_SULT_S_MMR6
1222
0
    UINT64_C(1184890889), // CMP_SUN_D
1223
0
    UINT64_C(1409286741), // CMP_SUN_D_MMR6
1224
0
    UINT64_C(1182793737), // CMP_SUN_S
1225
0
    UINT64_C(1409286725), // CMP_SUN_S_MMR6
1226
0
    UINT64_C(1184890883), // CMP_UEQ_D
1227
0
    UINT64_C(1409286357), // CMP_UEQ_D_MMR6
1228
0
    UINT64_C(1182793731), // CMP_UEQ_S
1229
0
    UINT64_C(1409286341), // CMP_UEQ_S_MMR6
1230
0
    UINT64_C(1184890887), // CMP_ULE_D
1231
0
    UINT64_C(1409286613), // CMP_ULE_D_MMR6
1232
0
    UINT64_C(1182793735), // CMP_ULE_S
1233
0
    UINT64_C(1409286597), // CMP_ULE_S_MMR6
1234
0
    UINT64_C(1184890885), // CMP_ULT_D
1235
0
    UINT64_C(1409286485), // CMP_ULT_D_MMR6
1236
0
    UINT64_C(1182793733), // CMP_ULT_S
1237
0
    UINT64_C(1409286469), // CMP_ULT_S_MMR6
1238
0
    UINT64_C(1184890881), // CMP_UN_D
1239
0
    UINT64_C(1409286229), // CMP_UN_D_MMR6
1240
0
    UINT64_C(1182793729), // CMP_UN_S
1241
0
    UINT64_C(1409286213), // CMP_UN_S_MMR6
1242
0
    UINT64_C(2021654553), // COPY_S_B
1243
0
    UINT64_C(2025324569), // COPY_S_D
1244
0
    UINT64_C(2023751705), // COPY_S_H
1245
0
    UINT64_C(2024800281), // COPY_S_W
1246
0
    UINT64_C(2025848857), // COPY_U_B
1247
0
    UINT64_C(2027946009), // COPY_U_H
1248
0
    UINT64_C(2028994585), // COPY_U_W
1249
0
    UINT64_C(2080374799), // CRC32B
1250
0
    UINT64_C(2080375055), // CRC32CB
1251
0
    UINT64_C(2080375247), // CRC32CD
1252
0
    UINT64_C(2080375119), // CRC32CH
1253
0
    UINT64_C(2080375183), // CRC32CW
1254
0
    UINT64_C(2080374991), // CRC32D
1255
0
    UINT64_C(2080374863), // CRC32H
1256
0
    UINT64_C(2080374927), // CRC32W
1257
0
    UINT64_C(1153433600), // CTC1
1258
0
    UINT64_C(1409292347), // CTC1_MM
1259
0
    UINT64_C(56636),  // CTC2_MM
1260
0
    UINT64_C(2017329177), // CTCMSA
1261
0
    UINT64_C(1174405153), // CVT_D32_S
1262
0
    UINT64_C(1409291131), // CVT_D32_S_MM
1263
0
    UINT64_C(1182793761), // CVT_D32_W
1264
0
    UINT64_C(1409299323), // CVT_D32_W_MM
1265
0
    UINT64_C(1184890913), // CVT_D64_L
1266
0
    UINT64_C(1174405153), // CVT_D64_S
1267
0
    UINT64_C(1409291131), // CVT_D64_S_MM
1268
0
    UINT64_C(1182793761), // CVT_D64_W
1269
0
    UINT64_C(1409299323), // CVT_D64_W_MM
1270
0
    UINT64_C(1409307515), // CVT_D_L_MMR6
1271
0
    UINT64_C(1176502309), // CVT_L_D64
1272
0
    UINT64_C(1409302843), // CVT_L_D64_MM
1273
0
    UINT64_C(1409302843), // CVT_L_D_MMR6
1274
0
    UINT64_C(1174405157), // CVT_L_S
1275
0
    UINT64_C(1409286459), // CVT_L_S_MM
1276
0
    UINT64_C(1409286459), // CVT_L_S_MMR6
1277
0
    UINT64_C(1182793766), // CVT_PS_PW64
1278
0
    UINT64_C(1174405158), // CVT_PS_S64
1279
0
    UINT64_C(1186988068), // CVT_PW_PS64
1280
0
    UINT64_C(1176502304), // CVT_S_D32
1281
0
    UINT64_C(1409293179), // CVT_S_D32_MM
1282
0
    UINT64_C(1176502304), // CVT_S_D64
1283
0
    UINT64_C(1409293179), // CVT_S_D64_MM
1284
0
    UINT64_C(1184890912), // CVT_S_L
1285
0
    UINT64_C(1409309563), // CVT_S_L_MMR6
1286
0
    UINT64_C(1186988072), // CVT_S_PL64
1287
0
    UINT64_C(1186988064), // CVT_S_PU64
1288
0
    UINT64_C(1182793760), // CVT_S_W
1289
0
    UINT64_C(1409301371), // CVT_S_W_MM
1290
0
    UINT64_C(1409301371), // CVT_S_W_MMR6
1291
0
    UINT64_C(1176502308), // CVT_W_D32
1292
0
    UINT64_C(1409304891), // CVT_W_D32_MM
1293
0
    UINT64_C(1176502308), // CVT_W_D64
1294
0
    UINT64_C(1409304891), // CVT_W_D64_MM
1295
0
    UINT64_C(1174405156), // CVT_W_S
1296
0
    UINT64_C(1409288507), // CVT_W_S_MM
1297
0
    UINT64_C(1409288507), // CVT_W_S_MMR6
1298
0
    UINT64_C(1176502322), // C_EQ_D32
1299
0
    UINT64_C(1409287356), // C_EQ_D32_MM
1300
0
    UINT64_C(1176502322), // C_EQ_D64
1301
0
    UINT64_C(1409287356), // C_EQ_D64_MM
1302
0
    UINT64_C(1174405170), // C_EQ_S
1303
0
    UINT64_C(1409286332), // C_EQ_S_MM
1304
0
    UINT64_C(1176502320), // C_F_D32
1305
0
    UINT64_C(1409287228), // C_F_D32_MM
1306
0
    UINT64_C(1176502320), // C_F_D64
1307
0
    UINT64_C(1409287228), // C_F_D64_MM
1308
0
    UINT64_C(1174405168), // C_F_S
1309
0
    UINT64_C(1409286204), // C_F_S_MM
1310
0
    UINT64_C(1176502334), // C_LE_D32
1311
0
    UINT64_C(1409288124), // C_LE_D32_MM
1312
0
    UINT64_C(1176502334), // C_LE_D64
1313
0
    UINT64_C(1409288124), // C_LE_D64_MM
1314
0
    UINT64_C(1174405182), // C_LE_S
1315
0
    UINT64_C(1409287100), // C_LE_S_MM
1316
0
    UINT64_C(1176502332), // C_LT_D32
1317
0
    UINT64_C(1409287996), // C_LT_D32_MM
1318
0
    UINT64_C(1176502332), // C_LT_D64
1319
0
    UINT64_C(1409287996), // C_LT_D64_MM
1320
0
    UINT64_C(1174405180), // C_LT_S
1321
0
    UINT64_C(1409286972), // C_LT_S_MM
1322
0
    UINT64_C(1176502333), // C_NGE_D32
1323
0
    UINT64_C(1409288060), // C_NGE_D32_MM
1324
0
    UINT64_C(1176502333), // C_NGE_D64
1325
0
    UINT64_C(1409288060), // C_NGE_D64_MM
1326
0
    UINT64_C(1174405181), // C_NGE_S
1327
0
    UINT64_C(1409287036), // C_NGE_S_MM
1328
0
    UINT64_C(1176502329), // C_NGLE_D32
1329
0
    UINT64_C(1409287804), // C_NGLE_D32_MM
1330
0
    UINT64_C(1176502329), // C_NGLE_D64
1331
0
    UINT64_C(1409287804), // C_NGLE_D64_MM
1332
0
    UINT64_C(1174405177), // C_NGLE_S
1333
0
    UINT64_C(1409286780), // C_NGLE_S_MM
1334
0
    UINT64_C(1176502331), // C_NGL_D32
1335
0
    UINT64_C(1409287932), // C_NGL_D32_MM
1336
0
    UINT64_C(1176502331), // C_NGL_D64
1337
0
    UINT64_C(1409287932), // C_NGL_D64_MM
1338
0
    UINT64_C(1174405179), // C_NGL_S
1339
0
    UINT64_C(1409286908), // C_NGL_S_MM
1340
0
    UINT64_C(1176502335), // C_NGT_D32
1341
0
    UINT64_C(1409288188), // C_NGT_D32_MM
1342
0
    UINT64_C(1176502335), // C_NGT_D64
1343
0
    UINT64_C(1409288188), // C_NGT_D64_MM
1344
0
    UINT64_C(1174405183), // C_NGT_S
1345
0
    UINT64_C(1409287164), // C_NGT_S_MM
1346
0
    UINT64_C(1176502326), // C_OLE_D32
1347
0
    UINT64_C(1409287612), // C_OLE_D32_MM
1348
0
    UINT64_C(1176502326), // C_OLE_D64
1349
0
    UINT64_C(1409287612), // C_OLE_D64_MM
1350
0
    UINT64_C(1174405174), // C_OLE_S
1351
0
    UINT64_C(1409286588), // C_OLE_S_MM
1352
0
    UINT64_C(1176502324), // C_OLT_D32
1353
0
    UINT64_C(1409287484), // C_OLT_D32_MM
1354
0
    UINT64_C(1176502324), // C_OLT_D64
1355
0
    UINT64_C(1409287484), // C_OLT_D64_MM
1356
0
    UINT64_C(1174405172), // C_OLT_S
1357
0
    UINT64_C(1409286460), // C_OLT_S_MM
1358
0
    UINT64_C(1176502330), // C_SEQ_D32
1359
0
    UINT64_C(1409287868), // C_SEQ_D32_MM
1360
0
    UINT64_C(1176502330), // C_SEQ_D64
1361
0
    UINT64_C(1409287868), // C_SEQ_D64_MM
1362
0
    UINT64_C(1174405178), // C_SEQ_S
1363
0
    UINT64_C(1409286844), // C_SEQ_S_MM
1364
0
    UINT64_C(1176502328), // C_SF_D32
1365
0
    UINT64_C(1409287740), // C_SF_D32_MM
1366
0
    UINT64_C(1176502328), // C_SF_D64
1367
0
    UINT64_C(1409287740), // C_SF_D64_MM
1368
0
    UINT64_C(1174405176), // C_SF_S
1369
0
    UINT64_C(1409286716), // C_SF_S_MM
1370
0
    UINT64_C(1176502323), // C_UEQ_D32
1371
0
    UINT64_C(1409287420), // C_UEQ_D32_MM
1372
0
    UINT64_C(1176502323), // C_UEQ_D64
1373
0
    UINT64_C(1409287420), // C_UEQ_D64_MM
1374
0
    UINT64_C(1174405171), // C_UEQ_S
1375
0
    UINT64_C(1409286396), // C_UEQ_S_MM
1376
0
    UINT64_C(1176502327), // C_ULE_D32
1377
0
    UINT64_C(1409287676), // C_ULE_D32_MM
1378
0
    UINT64_C(1176502327), // C_ULE_D64
1379
0
    UINT64_C(1409287676), // C_ULE_D64_MM
1380
0
    UINT64_C(1174405175), // C_ULE_S
1381
0
    UINT64_C(1409286652), // C_ULE_S_MM
1382
0
    UINT64_C(1176502325), // C_ULT_D32
1383
0
    UINT64_C(1409287548), // C_ULT_D32_MM
1384
0
    UINT64_C(1176502325), // C_ULT_D64
1385
0
    UINT64_C(1409287548), // C_ULT_D64_MM
1386
0
    UINT64_C(1174405173), // C_ULT_S
1387
0
    UINT64_C(1409286524), // C_ULT_S_MM
1388
0
    UINT64_C(1176502321), // C_UN_D32
1389
0
    UINT64_C(1409287292), // C_UN_D32_MM
1390
0
    UINT64_C(1176502321), // C_UN_D64
1391
0
    UINT64_C(1409287292), // C_UN_D64_MM
1392
0
    UINT64_C(1174405169), // C_UN_S
1393
0
    UINT64_C(1409286268), // C_UN_S_MM
1394
0
    UINT64_C(59402),  // CmpRxRy16
1395
0
    UINT64_C(28672),  // CmpiRxImm16
1396
0
    UINT64_C(4026560512), // CmpiRxImmX16
1397
0
    UINT64_C(44), // DADD
1398
0
    UINT64_C(1610612736), // DADDi
1399
0
    UINT64_C(1677721600), // DADDiu
1400
0
    UINT64_C(45), // DADDu
1401
0
    UINT64_C(67502080), // DAHI
1402
0
    UINT64_C(2080375332), // DALIGN
1403
0
    UINT64_C(69074944), // DATI
1404
0
    UINT64_C(1946157056), // DAUI
1405
0
    UINT64_C(2080374820), // DBITSWAP
1406
0
    UINT64_C(1879048229), // DCLO
1407
0
    UINT64_C(83), // DCLO_R6
1408
0
    UINT64_C(1879048228), // DCLZ
1409
0
    UINT64_C(82), // DCLZ_R6
1410
0
    UINT64_C(158),  // DDIV
1411
0
    UINT64_C(159),  // DDIVU
1412
0
    UINT64_C(1107296287), // DERET
1413
0
    UINT64_C(58236),  // DERET_MM
1414
0
    UINT64_C(58236),  // DERET_MMR6
1415
0
    UINT64_C(2080374787), // DEXT
1416
0
    UINT64_C(2080374787), // DEXT64_32
1417
0
    UINT64_C(2080374785), // DEXTM
1418
0
    UINT64_C(2080374786), // DEXTU
1419
0
    UINT64_C(1096835072), // DI
1420
0
    UINT64_C(2080374791), // DINS
1421
0
    UINT64_C(2080374789), // DINSM
1422
0
    UINT64_C(2080374790), // DINSU
1423
0
    UINT64_C(154),  // DIV
1424
0
    UINT64_C(155),  // DIVU
1425
0
    UINT64_C(408),  // DIVU_MMR6
1426
0
    UINT64_C(280),  // DIV_MMR6
1427
0
    UINT64_C(2046820370), // DIV_S_B
1428
0
    UINT64_C(2053111826), // DIV_S_D
1429
0
    UINT64_C(2048917522), // DIV_S_H
1430
0
    UINT64_C(2051014674), // DIV_S_W
1431
0
    UINT64_C(2055208978), // DIV_U_B
1432
0
    UINT64_C(2061500434), // DIV_U_D
1433
0
    UINT64_C(2057306130), // DIV_U_H
1434
0
    UINT64_C(2059403282), // DIV_U_W
1435
0
    UINT64_C(18300),  // DI_MM
1436
0
    UINT64_C(18300),  // DI_MMR6
1437
0
    UINT64_C(21), // DLSA
1438
0
    UINT64_C(21), // DLSA_R6
1439
0
    UINT64_C(1075838976), // DMFC0
1440
0
    UINT64_C(1142947840), // DMFC1
1441
0
    UINT64_C(1210056704), // DMFC2
1442
0
    UINT64_C(1210056704), // DMFC2_OCTEON
1443
0
    UINT64_C(1080033536), // DMFGC0
1444
0
    UINT64_C(222),  // DMOD
1445
0
    UINT64_C(223),  // DMODU
1446
0
    UINT64_C(1096813505), // DMT
1447
0
    UINT64_C(1084227584), // DMTC0
1448
0
    UINT64_C(1151336448), // DMTC1
1449
0
    UINT64_C(1218445312), // DMTC2
1450
0
    UINT64_C(1218445312), // DMTC2_OCTEON
1451
0
    UINT64_C(1080034048), // DMTGC0
1452
0
    UINT64_C(220),  // DMUH
1453
0
    UINT64_C(221),  // DMUHU
1454
0
    UINT64_C(1879048195), // DMUL
1455
0
    UINT64_C(28), // DMULT
1456
0
    UINT64_C(29), // DMULTu
1457
0
    UINT64_C(157),  // DMULU
1458
0
    UINT64_C(156),  // DMUL_R6
1459
0
    UINT64_C(2019557395), // DOTP_S_D
1460
0
    UINT64_C(2015363091), // DOTP_S_H
1461
0
    UINT64_C(2017460243), // DOTP_S_W
1462
0
    UINT64_C(2027946003), // DOTP_U_D
1463
0
    UINT64_C(2023751699), // DOTP_U_H
1464
0
    UINT64_C(2025848851), // DOTP_U_W
1465
0
    UINT64_C(2036334611), // DPADD_S_D
1466
0
    UINT64_C(2032140307), // DPADD_S_H
1467
0
    UINT64_C(2034237459), // DPADD_S_W
1468
0
    UINT64_C(2044723219), // DPADD_U_D
1469
0
    UINT64_C(2040528915), // DPADD_U_H
1470
0
    UINT64_C(2042626067), // DPADD_U_W
1471
0
    UINT64_C(2080376496), // DPAQX_SA_W_PH
1472
0
    UINT64_C(12988),  // DPAQX_SA_W_PH_MMR2
1473
0
    UINT64_C(2080376368), // DPAQX_S_W_PH
1474
0
    UINT64_C(8892), // DPAQX_S_W_PH_MMR2
1475
0
    UINT64_C(2080375600), // DPAQ_SA_L_W
1476
0
    UINT64_C(4796), // DPAQ_SA_L_W_MM
1477
0
    UINT64_C(2080375088), // DPAQ_S_W_PH
1478
0
    UINT64_C(700),  // DPAQ_S_W_PH_MM
1479
0
    UINT64_C(2080375024), // DPAU_H_QBL
1480
0
    UINT64_C(8380), // DPAU_H_QBL_MM
1481
0
    UINT64_C(2080375280), // DPAU_H_QBR
1482
0
    UINT64_C(12476),  // DPAU_H_QBR_MM
1483
0
    UINT64_C(2080375344), // DPAX_W_PH
1484
0
    UINT64_C(4284), // DPAX_W_PH_MMR2
1485
0
    UINT64_C(2080374832), // DPA_W_PH
1486
0
    UINT64_C(188),  // DPA_W_PH_MMR2
1487
0
    UINT64_C(1879048237), // DPOP
1488
0
    UINT64_C(2080376560), // DPSQX_SA_W_PH
1489
0
    UINT64_C(14012),  // DPSQX_SA_W_PH_MMR2
1490
0
    UINT64_C(2080376432), // DPSQX_S_W_PH
1491
0
    UINT64_C(9916), // DPSQX_S_W_PH_MMR2
1492
0
    UINT64_C(2080375664), // DPSQ_SA_L_W
1493
0
    UINT64_C(5820), // DPSQ_SA_L_W_MM
1494
0
    UINT64_C(2080375152), // DPSQ_S_W_PH
1495
0
    UINT64_C(1724), // DPSQ_S_W_PH_MM
1496
0
    UINT64_C(2053111827), // DPSUB_S_D
1497
0
    UINT64_C(2048917523), // DPSUB_S_H
1498
0
    UINT64_C(2051014675), // DPSUB_S_W
1499
0
    UINT64_C(2061500435), // DPSUB_U_D
1500
0
    UINT64_C(2057306131), // DPSUB_U_H
1501
0
    UINT64_C(2059403283), // DPSUB_U_W
1502
0
    UINT64_C(2080375536), // DPSU_H_QBL
1503
0
    UINT64_C(9404), // DPSU_H_QBL_MM
1504
0
    UINT64_C(2080375792), // DPSU_H_QBR
1505
0
    UINT64_C(13500),  // DPSU_H_QBR_MM
1506
0
    UINT64_C(2080375408), // DPSX_W_PH
1507
0
    UINT64_C(5308), // DPSX_W_PH_MMR2
1508
0
    UINT64_C(2080374896), // DPS_W_PH
1509
0
    UINT64_C(1212), // DPS_W_PH_MMR2
1510
0
    UINT64_C(2097210),  // DROTR
1511
0
    UINT64_C(2097214),  // DROTR32
1512
0
    UINT64_C(86), // DROTRV
1513
0
    UINT64_C(2080374948), // DSBH
1514
0
    UINT64_C(30), // DSDIV
1515
0
    UINT64_C(2080375140), // DSHD
1516
0
    UINT64_C(56), // DSLL
1517
0
    UINT64_C(60), // DSLL32
1518
0
    UINT64_C(60), // DSLL64_32
1519
0
    UINT64_C(20), // DSLLV
1520
0
    UINT64_C(59), // DSRA
1521
0
    UINT64_C(63), // DSRA32
1522
0
    UINT64_C(23), // DSRAV
1523
0
    UINT64_C(58), // DSRL
1524
0
    UINT64_C(62), // DSRL32
1525
0
    UINT64_C(22), // DSRLV
1526
0
    UINT64_C(46), // DSUB
1527
0
    UINT64_C(47), // DSUBu
1528
0
    UINT64_C(31), // DUDIV
1529
0
    UINT64_C(1096810532), // DVP
1530
0
    UINT64_C(1096810497), // DVPE
1531
0
    UINT64_C(6524), // DVP_MMR6
1532
0
    UINT64_C(59418),  // DivRxRy16
1533
0
    UINT64_C(59419),  // DivuRxRy16
1534
0
    UINT64_C(192),  // EHB
1535
0
    UINT64_C(6144), // EHB_MM
1536
0
    UINT64_C(6144), // EHB_MMR6
1537
0
    UINT64_C(1096835104), // EI
1538
0
    UINT64_C(22396),  // EI_MM
1539
0
    UINT64_C(22396),  // EI_MMR6
1540
0
    UINT64_C(1096813537), // EMT
1541
0
    UINT64_C(1107296280), // ERET
1542
0
    UINT64_C(1107296344), // ERETNC
1543
0
    UINT64_C(127868), // ERETNC_MMR6
1544
0
    UINT64_C(62332),  // ERET_MM
1545
0
    UINT64_C(62332),  // ERET_MMR6
1546
0
    UINT64_C(1096810500), // EVP
1547
0
    UINT64_C(1096810529), // EVPE
1548
0
    UINT64_C(14716),  // EVP_MMR6
1549
0
    UINT64_C(2080374784), // EXT
1550
0
    UINT64_C(2080374968), // EXTP
1551
0
    UINT64_C(2080375480), // EXTPDP
1552
0
    UINT64_C(2080375544), // EXTPDPV
1553
0
    UINT64_C(14524),  // EXTPDPV_MM
1554
0
    UINT64_C(13948),  // EXTPDP_MM
1555
0
    UINT64_C(2080375032), // EXTPV
1556
0
    UINT64_C(10428),  // EXTPV_MM
1557
0
    UINT64_C(9852), // EXTP_MM
1558
0
    UINT64_C(2080375288), // EXTRV_RS_W
1559
0
    UINT64_C(11964),  // EXTRV_RS_W_MM
1560
0
    UINT64_C(2080375160), // EXTRV_R_W
1561
0
    UINT64_C(7868), // EXTRV_R_W_MM
1562
0
    UINT64_C(2080375800), // EXTRV_S_H
1563
0
    UINT64_C(16060),  // EXTRV_S_H_MM
1564
0
    UINT64_C(2080374904), // EXTRV_W
1565
0
    UINT64_C(3772), // EXTRV_W_MM
1566
0
    UINT64_C(2080375224), // EXTR_RS_W
1567
0
    UINT64_C(11900),  // EXTR_RS_W_MM
1568
0
    UINT64_C(2080375096), // EXTR_R_W
1569
0
    UINT64_C(7804), // EXTR_R_W_MM
1570
0
    UINT64_C(2080375736), // EXTR_S_H
1571
0
    UINT64_C(15996),  // EXTR_S_H_MM
1572
0
    UINT64_C(2080374840), // EXTR_W
1573
0
    UINT64_C(3708), // EXTR_W_MM
1574
0
    UINT64_C(1879048250), // EXTS
1575
0
    UINT64_C(1879048251), // EXTS32
1576
0
    UINT64_C(44), // EXT_MM
1577
0
    UINT64_C(44), // EXT_MMR6
1578
0
    UINT64_C(1176502277), // FABS_D32
1579
0
    UINT64_C(1409295227), // FABS_D32_MM
1580
0
    UINT64_C(1176502277), // FABS_D64
1581
0
    UINT64_C(1409295227), // FABS_D64_MM
1582
0
    UINT64_C(1174405125), // FABS_S
1583
0
    UINT64_C(1409287035), // FABS_S_MM
1584
0
    UINT64_C(2015363099), // FADD_D
1585
0
    UINT64_C(1176502272), // FADD_D32
1586
0
    UINT64_C(1409286448), // FADD_D32_MM
1587
0
    UINT64_C(1176502272), // FADD_D64
1588
0
    UINT64_C(1409286448), // FADD_D64_MM
1589
0
    UINT64_C(1186988032), // FADD_PS64
1590
0
    UINT64_C(1174405120), // FADD_S
1591
0
    UINT64_C(1409286192), // FADD_S_MM
1592
0
    UINT64_C(1409286192), // FADD_S_MMR6
1593
0
    UINT64_C(2013265947), // FADD_W
1594
0
    UINT64_C(2015363098), // FCAF_D
1595
0
    UINT64_C(2013265946), // FCAF_W
1596
0
    UINT64_C(2023751706), // FCEQ_D
1597
0
    UINT64_C(2021654554), // FCEQ_W
1598
0
    UINT64_C(2065760286), // FCLASS_D
1599
0
    UINT64_C(2065694750), // FCLASS_W
1600
0
    UINT64_C(2040528922), // FCLE_D
1601
0
    UINT64_C(2038431770), // FCLE_W
1602
0
    UINT64_C(2032140314), // FCLT_D
1603
0
    UINT64_C(2030043162), // FCLT_W
1604
0
    UINT64_C(1176502320), // FCMP_D32
1605
0
    UINT64_C(1409287228), // FCMP_D32_MM
1606
0
    UINT64_C(1176502320), // FCMP_D64
1607
0
    UINT64_C(1174405168), // FCMP_S32
1608
0
    UINT64_C(1409286204), // FCMP_S32_MM
1609
0
    UINT64_C(2027946012), // FCNE_D
1610
0
    UINT64_C(2025848860), // FCNE_W
1611
0
    UINT64_C(2019557404), // FCOR_D
1612
0
    UINT64_C(2017460252), // FCOR_W
1613
0
    UINT64_C(2027946010), // FCUEQ_D
1614
0
    UINT64_C(2025848858), // FCUEQ_W
1615
0
    UINT64_C(2044723226), // FCULE_D
1616
0
    UINT64_C(2042626074), // FCULE_W
1617
0
    UINT64_C(2036334618), // FCULT_D
1618
0
    UINT64_C(2034237466), // FCULT_W
1619
0
    UINT64_C(2023751708), // FCUNE_D
1620
0
    UINT64_C(2021654556), // FCUNE_W
1621
0
    UINT64_C(2019557402), // FCUN_D
1622
0
    UINT64_C(2017460250), // FCUN_W
1623
0
    UINT64_C(2027946011), // FDIV_D
1624
0
    UINT64_C(1176502275), // FDIV_D32
1625
0
    UINT64_C(1409286640), // FDIV_D32_MM
1626
0
    UINT64_C(1176502275), // FDIV_D64
1627
0
    UINT64_C(1409286640), // FDIV_D64_MM
1628
0
    UINT64_C(1174405123), // FDIV_S
1629
0
    UINT64_C(1409286384), // FDIV_S_MM
1630
0
    UINT64_C(1409286384), // FDIV_S_MMR6
1631
0
    UINT64_C(2025848859), // FDIV_W
1632
0
    UINT64_C(2046820379), // FEXDO_H
1633
0
    UINT64_C(2048917531), // FEXDO_W
1634
0
    UINT64_C(2044723227), // FEXP2_D
1635
0
    UINT64_C(2042626075), // FEXP2_W
1636
0
    UINT64_C(2066808862), // FEXUPL_D
1637
0
    UINT64_C(2066743326), // FEXUPL_W
1638
0
    UINT64_C(2066939934), // FEXUPR_D
1639
0
    UINT64_C(2066874398), // FEXUPR_W
1640
0
    UINT64_C(2067595294), // FFINT_S_D
1641
0
    UINT64_C(2067529758), // FFINT_S_W
1642
0
    UINT64_C(2067726366), // FFINT_U_D
1643
0
    UINT64_C(2067660830), // FFINT_U_W
1644
0
    UINT64_C(2067071006), // FFQL_D
1645
0
    UINT64_C(2067005470), // FFQL_W
1646
0
    UINT64_C(2067202078), // FFQR_D
1647
0
    UINT64_C(2067136542), // FFQR_W
1648
0
    UINT64_C(2063597598), // FILL_B
1649
0
    UINT64_C(2063794206), // FILL_D
1650
0
    UINT64_C(2063663134), // FILL_H
1651
0
    UINT64_C(2063728670), // FILL_W
1652
0
    UINT64_C(2066677790), // FLOG2_D
1653
0
    UINT64_C(2066612254), // FLOG2_W
1654
0
    UINT64_C(1176502283), // FLOOR_L_D64
1655
0
    UINT64_C(1409303355), // FLOOR_L_D_MMR6
1656
0
    UINT64_C(1174405131), // FLOOR_L_S
1657
0
    UINT64_C(1409286971), // FLOOR_L_S_MMR6
1658
0
    UINT64_C(1176502287), // FLOOR_W_D32
1659
0
    UINT64_C(1176502287), // FLOOR_W_D64
1660
0
    UINT64_C(1409305403), // FLOOR_W_D_MMR6
1661
0
    UINT64_C(1409305403), // FLOOR_W_MM
1662
0
    UINT64_C(1174405135), // FLOOR_W_S
1663
0
    UINT64_C(1409289019), // FLOOR_W_S_MM
1664
0
    UINT64_C(1409289019), // FLOOR_W_S_MMR6
1665
0
    UINT64_C(2032140315), // FMADD_D
1666
0
    UINT64_C(2030043163), // FMADD_W
1667
0
    UINT64_C(2078277659), // FMAX_A_D
1668
0
    UINT64_C(2076180507), // FMAX_A_W
1669
0
    UINT64_C(2074083355), // FMAX_D
1670
0
    UINT64_C(2071986203), // FMAX_W
1671
0
    UINT64_C(2069889051), // FMIN_A_D
1672
0
    UINT64_C(2067791899), // FMIN_A_W
1673
0
    UINT64_C(2065694747), // FMIN_D
1674
0
    UINT64_C(2063597595), // FMIN_W
1675
0
    UINT64_C(1176502278), // FMOV_D32
1676
0
    UINT64_C(1409294459), // FMOV_D32_MM
1677
0
    UINT64_C(1176502278), // FMOV_D64
1678
0
    UINT64_C(1409294459), // FMOV_D64_MM
1679
0
    UINT64_C(1409294459), // FMOV_D_MMR6
1680
0
    UINT64_C(1174405126), // FMOV_S
1681
0
    UINT64_C(1409286267), // FMOV_S_MM
1682
0
    UINT64_C(1409286267), // FMOV_S_MMR6
1683
0
    UINT64_C(2036334619), // FMSUB_D
1684
0
    UINT64_C(2034237467), // FMSUB_W
1685
0
    UINT64_C(2023751707), // FMUL_D
1686
0
    UINT64_C(1176502274), // FMUL_D32
1687
0
    UINT64_C(1409286576), // FMUL_D32_MM
1688
0
    UINT64_C(1176502274), // FMUL_D64
1689
0
    UINT64_C(1409286576), // FMUL_D64_MM
1690
0
    UINT64_C(1186988034), // FMUL_PS64
1691
0
    UINT64_C(1174405122), // FMUL_S
1692
0
    UINT64_C(1409286320), // FMUL_S_MM
1693
0
    UINT64_C(1409286320), // FMUL_S_MMR6
1694
0
    UINT64_C(2021654555), // FMUL_W
1695
0
    UINT64_C(1176502279), // FNEG_D32
1696
0
    UINT64_C(1409297275), // FNEG_D32_MM
1697
0
    UINT64_C(1176502279), // FNEG_D64
1698
0
    UINT64_C(1409297275), // FNEG_D64_MM
1699
0
    UINT64_C(1174405127), // FNEG_S
1700
0
    UINT64_C(1409289083), // FNEG_S_MM
1701
0
    UINT64_C(1409289083), // FNEG_S_MMR6
1702
0
    UINT64_C(2080374792), // FORK
1703
0
    UINT64_C(2066415646), // FRCP_D
1704
0
    UINT64_C(2066350110), // FRCP_W
1705
0
    UINT64_C(2066546718), // FRINT_D
1706
0
    UINT64_C(2066481182), // FRINT_W
1707
0
    UINT64_C(2066284574), // FRSQRT_D
1708
0
    UINT64_C(2066219038), // FRSQRT_W
1709
0
    UINT64_C(2048917530), // FSAF_D
1710
0
    UINT64_C(2046820378), // FSAF_W
1711
0
    UINT64_C(2057306138), // FSEQ_D
1712
0
    UINT64_C(2055208986), // FSEQ_W
1713
0
    UINT64_C(2074083354), // FSLE_D
1714
0
    UINT64_C(2071986202), // FSLE_W
1715
0
    UINT64_C(2065694746), // FSLT_D
1716
0
    UINT64_C(2063597594), // FSLT_W
1717
0
    UINT64_C(2061500444), // FSNE_D
1718
0
    UINT64_C(2059403292), // FSNE_W
1719
0
    UINT64_C(2053111836), // FSOR_D
1720
0
    UINT64_C(2051014684), // FSOR_W
1721
0
    UINT64_C(2066153502), // FSQRT_D
1722
0
    UINT64_C(1176502276), // FSQRT_D32
1723
0
    UINT64_C(1409305147), // FSQRT_D32_MM
1724
0
    UINT64_C(1176502276), // FSQRT_D64
1725
0
    UINT64_C(1409305147), // FSQRT_D64_MM
1726
0
    UINT64_C(1174405124), // FSQRT_S
1727
0
    UINT64_C(1409288763), // FSQRT_S_MM
1728
0
    UINT64_C(2066087966), // FSQRT_W
1729
0
    UINT64_C(2019557403), // FSUB_D
1730
0
    UINT64_C(1176502273), // FSUB_D32
1731
0
    UINT64_C(1409286512), // FSUB_D32_MM
1732
0
    UINT64_C(1176502273), // FSUB_D64
1733
0
    UINT64_C(1409286512), // FSUB_D64_MM
1734
0
    UINT64_C(1186988033), // FSUB_PS64
1735
0
    UINT64_C(1174405121), // FSUB_S
1736
0
    UINT64_C(1409286256), // FSUB_S_MM
1737
0
    UINT64_C(1409286256), // FSUB_S_MMR6
1738
0
    UINT64_C(2017460251), // FSUB_W
1739
0
    UINT64_C(2061500442), // FSUEQ_D
1740
0
    UINT64_C(2059403290), // FSUEQ_W
1741
0
    UINT64_C(2078277658), // FSULE_D
1742
0
    UINT64_C(2076180506), // FSULE_W
1743
0
    UINT64_C(2069889050), // FSULT_D
1744
0
    UINT64_C(2067791898), // FSULT_W
1745
0
    UINT64_C(2057306140), // FSUNE_D
1746
0
    UINT64_C(2055208988), // FSUNE_W
1747
0
    UINT64_C(2053111834), // FSUN_D
1748
0
    UINT64_C(2051014682), // FSUN_W
1749
0
    UINT64_C(2067333150), // FTINT_S_D
1750
0
    UINT64_C(2067267614), // FTINT_S_W
1751
0
    UINT64_C(2067464222), // FTINT_U_D
1752
0
    UINT64_C(2067398686), // FTINT_U_W
1753
0
    UINT64_C(2055208987), // FTQ_H
1754
0
    UINT64_C(2057306139), // FTQ_W
1755
0
    UINT64_C(2065891358), // FTRUNC_S_D
1756
0
    UINT64_C(2065825822), // FTRUNC_S_W
1757
0
    UINT64_C(2066022430), // FTRUNC_U_D
1758
0
    UINT64_C(2065956894), // FTRUNC_U_W
1759
0
    UINT64_C(2080374845), // GINVI
1760
0
    UINT64_C(24956),  // GINVI_MMR6
1761
0
    UINT64_C(2080374973), // GINVT
1762
0
    UINT64_C(29052),  // GINVT_MMR6
1763
0
    UINT64_C(2053111829), // HADD_S_D
1764
0
    UINT64_C(2048917525), // HADD_S_H
1765
0
    UINT64_C(2051014677), // HADD_S_W
1766
0
    UINT64_C(2061500437), // HADD_U_D
1767
0
    UINT64_C(2057306133), // HADD_U_H
1768
0
    UINT64_C(2059403285), // HADD_U_W
1769
0
    UINT64_C(2069889045), // HSUB_S_D
1770
0
    UINT64_C(2065694741), // HSUB_S_H
1771
0
    UINT64_C(2067791893), // HSUB_S_W
1772
0
    UINT64_C(2078277653), // HSUB_U_D
1773
0
    UINT64_C(2074083349), // HSUB_U_H
1774
0
    UINT64_C(2076180501), // HSUB_U_W
1775
0
    UINT64_C(1107296296), // HYPCALL
1776
0
    UINT64_C(50044),  // HYPCALL_MM
1777
0
    UINT64_C(2063597588), // ILVEV_B
1778
0
    UINT64_C(2069889044), // ILVEV_D
1779
0
    UINT64_C(2065694740), // ILVEV_H
1780
0
    UINT64_C(2067791892), // ILVEV_W
1781
0
    UINT64_C(2046820372), // ILVL_B
1782
0
    UINT64_C(2053111828), // ILVL_D
1783
0
    UINT64_C(2048917524), // ILVL_H
1784
0
    UINT64_C(2051014676), // ILVL_W
1785
0
    UINT64_C(2071986196), // ILVOD_B
1786
0
    UINT64_C(2078277652), // ILVOD_D
1787
0
    UINT64_C(2074083348), // ILVOD_H
1788
0
    UINT64_C(2076180500), // ILVOD_W
1789
0
    UINT64_C(2055208980), // ILVR_B
1790
0
    UINT64_C(2061500436), // ILVR_D
1791
0
    UINT64_C(2057306132), // ILVR_H
1792
0
    UINT64_C(2059403284), // ILVR_W
1793
0
    UINT64_C(2080374788), // INS
1794
0
    UINT64_C(2030043161), // INSERT_B
1795
0
    UINT64_C(2033713177), // INSERT_D
1796
0
    UINT64_C(2032140313), // INSERT_H
1797
0
    UINT64_C(2033188889), // INSERT_W
1798
0
    UINT64_C(2080374796), // INSV
1799
0
    UINT64_C(2034237465), // INSVE_B
1800
0
    UINT64_C(2037907481), // INSVE_D
1801
0
    UINT64_C(2036334617), // INSVE_H
1802
0
    UINT64_C(2037383193), // INSVE_W
1803
0
    UINT64_C(16700),  // INSV_MM
1804
0
    UINT64_C(12), // INS_MM
1805
0
    UINT64_C(12), // INS_MMR6
1806
0
    UINT64_C(134217728),  // J
1807
0
    UINT64_C(201326592),  // JAL
1808
0
    UINT64_C(9),  // JALR
1809
0
    UINT64_C(17856),  // JALR16_MM
1810
0
    UINT64_C(9),  // JALR64
1811
0
    UINT64_C(17419),  // JALRC16_MMR6
1812
0
    UINT64_C(7996), // JALRC_HB_MMR6
1813
0
    UINT64_C(3900), // JALRC_MMR6
1814
0
    UINT64_C(17888),  // JALRS16_MM
1815
0
    UINT64_C(20284),  // JALRS_MM
1816
0
    UINT64_C(1033), // JALR_HB
1817
0
    UINT64_C(1033), // JALR_HB64
1818
0
    UINT64_C(3900), // JALR_MM
1819
0
    UINT64_C(1946157056), // JALS_MM
1820
0
    UINT64_C(1946157056), // JALX
1821
0
    UINT64_C(4026531840), // JALX_MM
1822
0
    UINT64_C(4093640704), // JAL_MM
1823
0
    UINT64_C(4160749568), // JIALC
1824
0
    UINT64_C(4160749568), // JIALC64
1825
0
    UINT64_C(2147483648), // JIALC_MMR6
1826
0
    UINT64_C(3623878656), // JIC
1827
0
    UINT64_C(3623878656), // JIC64
1828
0
    UINT64_C(2684354560), // JIC_MMR6
1829
0
    UINT64_C(8),  // JR
1830
0
    UINT64_C(17792),  // JR16_MM
1831
0
    UINT64_C(8),  // JR64
1832
0
    UINT64_C(18176),  // JRADDIUSP
1833
0
    UINT64_C(17824),  // JRC16_MM
1834
0
    UINT64_C(17411),  // JRC16_MMR6
1835
0
    UINT64_C(17427),  // JRCADDIUSP_MMR6
1836
0
    UINT64_C(1032), // JR_HB
1837
0
    UINT64_C(1032), // JR_HB64
1838
0
    UINT64_C(1033), // JR_HB64_R6
1839
0
    UINT64_C(1033), // JR_HB_R6
1840
0
    UINT64_C(3900), // JR_MM
1841
0
    UINT64_C(3556769792), // J_MM
1842
0
    UINT64_C(402653184),  // Jal16
1843
0
    UINT64_C(402653184),  // JalB16
1844
0
    UINT64_C(59424),  // JrRa16
1845
0
    UINT64_C(59616),  // JrcRa16
1846
0
    UINT64_C(59584),  // JrcRx16
1847
0
    UINT64_C(59392),  // JumpLinkReg16
1848
0
    UINT64_C(2147483648), // LB
1849
0
    UINT64_C(2147483648), // LB64
1850
0
    UINT64_C(2080374828), // LBE
1851
0
    UINT64_C(1610639360), // LBE_MM
1852
0
    UINT64_C(2048), // LBU16_MM
1853
0
    UINT64_C(2080375178), // LBUX
1854
0
    UINT64_C(549),  // LBUX_MM
1855
0
    UINT64_C(335544320),  // LBU_MMR6
1856
0
    UINT64_C(469762048),  // LB_MM
1857
0
    UINT64_C(469762048),  // LB_MMR6
1858
0
    UINT64_C(2415919104), // LBu
1859
0
    UINT64_C(2415919104), // LBu64
1860
0
    UINT64_C(2080374824), // LBuE
1861
0
    UINT64_C(1610637312), // LBuE_MM
1862
0
    UINT64_C(335544320),  // LBu_MM
1863
0
    UINT64_C(3690987520), // LD
1864
0
    UINT64_C(3556769792), // LDC1
1865
0
    UINT64_C(3556769792), // LDC164
1866
0
    UINT64_C(3154116608), // LDC1_D64_MMR6
1867
0
    UINT64_C(3154116608), // LDC1_MM_D32
1868
0
    UINT64_C(3154116608), // LDC1_MM_D64
1869
0
    UINT64_C(3623878656), // LDC2
1870
0
    UINT64_C(536879104),  // LDC2_MMR6
1871
0
    UINT64_C(1237319680), // LDC2_R6
1872
0
    UINT64_C(3690987520), // LDC3
1873
0
    UINT64_C(2063597575), // LDI_B
1874
0
    UINT64_C(2069889031), // LDI_D
1875
0
    UINT64_C(2065694727), // LDI_H
1876
0
    UINT64_C(2067791879), // LDI_W
1877
0
    UINT64_C(1744830464), // LDL
1878
0
    UINT64_C(3960995840), // LDPC
1879
0
    UINT64_C(1811939328), // LDR
1880
0
    UINT64_C(1275068417), // LDXC1
1881
0
    UINT64_C(1275068417), // LDXC164
1882
0
    UINT64_C(2013265952), // LD_B
1883
0
    UINT64_C(2013265955), // LD_D
1884
0
    UINT64_C(2013265953), // LD_H
1885
0
    UINT64_C(2013265954), // LD_W
1886
0
    UINT64_C(603979776),  // LEA_ADDiu
1887
0
    UINT64_C(1677721600), // LEA_ADDiu64
1888
0
    UINT64_C(805306368),  // LEA_ADDiu_MM
1889
0
    UINT64_C(2214592512), // LH
1890
0
    UINT64_C(2214592512), // LH64
1891
0
    UINT64_C(2080374829), // LHE
1892
0
    UINT64_C(1610639872), // LHE_MM
1893
0
    UINT64_C(10240),  // LHU16_MM
1894
0
    UINT64_C(2080375050), // LHX
1895
0
    UINT64_C(357),  // LHX_MM
1896
0
    UINT64_C(1006632960), // LH_MM
1897
0
    UINT64_C(2483027968), // LHu
1898
0
    UINT64_C(2483027968), // LHu64
1899
0
    UINT64_C(2080374825), // LHuE
1900
0
    UINT64_C(1610637824), // LHuE_MM
1901
0
    UINT64_C(872415232),  // LHu_MM
1902
0
    UINT64_C(60416),  // LI16_MM
1903
0
    UINT64_C(60416),  // LI16_MMR6
1904
0
    UINT64_C(3221225472), // LL
1905
0
    UINT64_C(3221225472), // LL64
1906
0
    UINT64_C(2080374838), // LL64_R6
1907
0
    UINT64_C(3489660928), // LLD
1908
0
    UINT64_C(2080374839), // LLD_R6
1909
0
    UINT64_C(2080374830), // LLE
1910
0
    UINT64_C(1610640384), // LLE_MM
1911
0
    UINT64_C(1610625024), // LL_MM
1912
0
    UINT64_C(1610625024), // LL_MMR6
1913
0
    UINT64_C(2080374838), // LL_R6
1914
0
    UINT64_C(5),  // LSA
1915
0
    UINT64_C(15), // LSA_MMR6
1916
0
    UINT64_C(5),  // LSA_R6
1917
0
    UINT64_C(268435456),  // LUI_MMR6
1918
0
    UINT64_C(1275068421), // LUXC1
1919
0
    UINT64_C(1275068421), // LUXC164
1920
0
    UINT64_C(1409286472), // LUXC1_MM
1921
0
    UINT64_C(1006632960), // LUi
1922
0
    UINT64_C(1006632960), // LUi64
1923
0
    UINT64_C(1101004800), // LUi_MM
1924
0
    UINT64_C(2348810240), // LW
1925
0
    UINT64_C(26624),  // LW16_MM
1926
0
    UINT64_C(2348810240), // LW64
1927
0
    UINT64_C(3288334336), // LWC1
1928
0
    UINT64_C(2617245696), // LWC1_MM
1929
0
    UINT64_C(3355443200), // LWC2
1930
0
    UINT64_C(536870912),  // LWC2_MMR6
1931
0
    UINT64_C(1228931072), // LWC2_R6
1932
0
    UINT64_C(3422552064), // LWC3
1933
0
    UINT64_C(2348810240), // LWDSP
1934
0
    UINT64_C(4227858432), // LWDSP_MM
1935
0
    UINT64_C(2080374831), // LWE
1936
0
    UINT64_C(1610640896), // LWE_MM
1937
0
    UINT64_C(25600),  // LWGP_MM
1938
0
    UINT64_C(2281701376), // LWL
1939
0
    UINT64_C(2281701376), // LWL64
1940
0
    UINT64_C(2080374809), // LWLE
1941
0
    UINT64_C(1610638336), // LWLE_MM
1942
0
    UINT64_C(1610612736), // LWL_MM
1943
0
    UINT64_C(17664),  // LWM16_MM
1944
0
    UINT64_C(17410),  // LWM16_MMR6
1945
0
    UINT64_C(536891392),  // LWM32_MM
1946
0
    UINT64_C(3959947264), // LWPC
1947
0
    UINT64_C(2013790208), // LWPC_MMR6
1948
0
    UINT64_C(536875008),  // LWP_MM
1949
0
    UINT64_C(2550136832), // LWR
1950
0
    UINT64_C(2550136832), // LWR64
1951
0
    UINT64_C(2080374810), // LWRE
1952
0
    UINT64_C(1610638848), // LWRE_MM
1953
0
    UINT64_C(1610616832), // LWR_MM
1954
0
    UINT64_C(18432),  // LWSP_MM
1955
0
    UINT64_C(3960471552), // LWUPC
1956
0
    UINT64_C(1610670080), // LWU_MM
1957
0
    UINT64_C(2080374794), // LWX
1958
0
    UINT64_C(1275068416), // LWXC1
1959
0
    UINT64_C(1409286216), // LWXC1_MM
1960
0
    UINT64_C(280),  // LWXS_MM
1961
0
    UINT64_C(421),  // LWX_MM
1962
0
    UINT64_C(4227858432), // LW_MM
1963
0
    UINT64_C(4227858432), // LW_MMR6
1964
0
    UINT64_C(2617245696), // LWu
1965
0
    UINT64_C(4026570752), // LbRxRyOffMemX16
1966
0
    UINT64_C(4026572800), // LbuRxRyOffMemX16
1967
0
    UINT64_C(4026572800), // LhRxRyOffMemX16
1968
0
    UINT64_C(4026572800), // LhuRxRyOffMemX16
1969
0
    UINT64_C(26624),  // LiRxImm16
1970
0
    UINT64_C(4026558464), // LiRxImmAlignX16
1971
0
    UINT64_C(4026558464), // LiRxImmX16
1972
0
    UINT64_C(45056),  // LwRxPcTcp16
1973
0
    UINT64_C(4026576896), // LwRxPcTcpX16
1974
0
    UINT64_C(4026570752), // LwRxRyOffMemX16
1975
0
    UINT64_C(4026568704), // LwRxSpImmX16
1976
0
    UINT64_C(1879048192), // MADD
1977
0
    UINT64_C(1176502296), // MADDF_D
1978
0
    UINT64_C(1409287096), // MADDF_D_MMR6
1979
0
    UINT64_C(1174405144), // MADDF_S
1980
0
    UINT64_C(1409286584), // MADDF_S_MMR6
1981
0
    UINT64_C(2067791900), // MADDR_Q_H
1982
0
    UINT64_C(2069889052), // MADDR_Q_W
1983
0
    UINT64_C(1879048193), // MADDU
1984
0
    UINT64_C(1879048193), // MADDU_DSP
1985
0
    UINT64_C(6844), // MADDU_DSP_MM
1986
0
    UINT64_C(56124),  // MADDU_MM
1987
0
    UINT64_C(2021654546), // MADDV_B
1988
0
    UINT64_C(2027946002), // MADDV_D
1989
0
    UINT64_C(2023751698), // MADDV_H
1990
0
    UINT64_C(2025848850), // MADDV_W
1991
0
    UINT64_C(1275068449), // MADD_D32
1992
0
    UINT64_C(1409286153), // MADD_D32_MM
1993
0
    UINT64_C(1275068449), // MADD_D64
1994
0
    UINT64_C(1879048192), // MADD_DSP
1995
0
    UINT64_C(2748), // MADD_DSP_MM
1996
0
    UINT64_C(52028),  // MADD_MM
1997
0
    UINT64_C(2034237468), // MADD_Q_H
1998
0
    UINT64_C(2036334620), // MADD_Q_W
1999
0
    UINT64_C(1275068448), // MADD_S
2000
0
    UINT64_C(1409286145), // MADD_S_MM
2001
0
    UINT64_C(2080375856), // MAQ_SA_W_PHL
2002
0
    UINT64_C(14972),  // MAQ_SA_W_PHL_MM
2003
0
    UINT64_C(2080375984), // MAQ_SA_W_PHR
2004
0
    UINT64_C(10876),  // MAQ_SA_W_PHR_MM
2005
0
    UINT64_C(2080376112), // MAQ_S_W_PHL
2006
0
    UINT64_C(6780), // MAQ_S_W_PHL_MM
2007
0
    UINT64_C(2080376240), // MAQ_S_W_PHR
2008
0
    UINT64_C(2684), // MAQ_S_W_PHR_MM
2009
0
    UINT64_C(1176502303), // MAXA_D
2010
0
    UINT64_C(1409286699), // MAXA_D_MMR6
2011
0
    UINT64_C(1174405151), // MAXA_S
2012
0
    UINT64_C(1409286187), // MAXA_S_MMR6
2013
0
    UINT64_C(2030043142), // MAXI_S_B
2014
0
    UINT64_C(2036334598), // MAXI_S_D
2015
0
    UINT64_C(2032140294), // MAXI_S_H
2016
0
    UINT64_C(2034237446), // MAXI_S_W
2017
0
    UINT64_C(2038431750), // MAXI_U_B
2018
0
    UINT64_C(2044723206), // MAXI_U_D
2019
0
    UINT64_C(2040528902), // MAXI_U_H
2020
0
    UINT64_C(2042626054), // MAXI_U_W
2021
0
    UINT64_C(2063597582), // MAX_A_B
2022
0
    UINT64_C(2069889038), // MAX_A_D
2023
0
    UINT64_C(2065694734), // MAX_A_H
2024
0
    UINT64_C(2067791886), // MAX_A_W
2025
0
    UINT64_C(1176502301), // MAX_D
2026
0
    UINT64_C(1409286667), // MAX_D_MMR6
2027
0
    UINT64_C(1174405149), // MAX_S
2028
0
    UINT64_C(2030043150), // MAX_S_B
2029
0
    UINT64_C(2036334606), // MAX_S_D
2030
0
    UINT64_C(2032140302), // MAX_S_H
2031
0
    UINT64_C(1409286155), // MAX_S_MMR6
2032
0
    UINT64_C(2034237454), // MAX_S_W
2033
0
    UINT64_C(2038431758), // MAX_U_B
2034
0
    UINT64_C(2044723214), // MAX_U_D
2035
0
    UINT64_C(2040528910), // MAX_U_H
2036
0
    UINT64_C(2042626062), // MAX_U_W
2037
0
    UINT64_C(1073741824), // MFC0
2038
0
    UINT64_C(252),  // MFC0_MMR6
2039
0
    UINT64_C(1140850688), // MFC1
2040
0
    UINT64_C(1140850688), // MFC1_D64
2041
0
    UINT64_C(1409294395), // MFC1_MM
2042
0
    UINT64_C(1409294395), // MFC1_MMR6
2043
0
    UINT64_C(1207959552), // MFC2
2044
0
    UINT64_C(19772),  // MFC2_MMR6
2045
0
    UINT64_C(1080033280), // MFGC0
2046
0
    UINT64_C(1276), // MFGC0_MM
2047
0
    UINT64_C(244),  // MFHC0_MMR6
2048
0
    UINT64_C(1147142144), // MFHC1_D32
2049
0
    UINT64_C(1409298491), // MFHC1_D32_MM
2050
0
    UINT64_C(1147142144), // MFHC1_D64
2051
0
    UINT64_C(1409298491), // MFHC1_D64_MM
2052
0
    UINT64_C(36156),  // MFHC2_MMR6
2053
0
    UINT64_C(1080034304), // MFHGC0
2054
0
    UINT64_C(1268), // MFHGC0_MM
2055
0
    UINT64_C(16), // MFHI
2056
0
    UINT64_C(17920),  // MFHI16_MM
2057
0
    UINT64_C(16), // MFHI64
2058
0
    UINT64_C(16), // MFHI_DSP
2059
0
    UINT64_C(124),  // MFHI_DSP_MM
2060
0
    UINT64_C(3452), // MFHI_MM
2061
0
    UINT64_C(18), // MFLO
2062
0
    UINT64_C(17984),  // MFLO16_MM
2063
0
    UINT64_C(18), // MFLO64
2064
0
    UINT64_C(18), // MFLO_DSP
2065
0
    UINT64_C(4220), // MFLO_DSP_MM
2066
0
    UINT64_C(7548), // MFLO_MM
2067
0
    UINT64_C(1090519040), // MFTR
2068
0
    UINT64_C(1176502302), // MINA_D
2069
0
    UINT64_C(1409286691), // MINA_D_MMR6
2070
0
    UINT64_C(1174405150), // MINA_S
2071
0
    UINT64_C(1409286179), // MINA_S_MMR6
2072
0
    UINT64_C(2046820358), // MINI_S_B
2073
0
    UINT64_C(2053111814), // MINI_S_D
2074
0
    UINT64_C(2048917510), // MINI_S_H
2075
0
    UINT64_C(2051014662), // MINI_S_W
2076
0
    UINT64_C(2055208966), // MINI_U_B
2077
0
    UINT64_C(2061500422), // MINI_U_D
2078
0
    UINT64_C(2057306118), // MINI_U_H
2079
0
    UINT64_C(2059403270), // MINI_U_W
2080
0
    UINT64_C(2071986190), // MIN_A_B
2081
0
    UINT64_C(2078277646), // MIN_A_D
2082
0
    UINT64_C(2074083342), // MIN_A_H
2083
0
    UINT64_C(2076180494), // MIN_A_W
2084
0
    UINT64_C(1176502300), // MIN_D
2085
0
    UINT64_C(1409286659), // MIN_D_MMR6
2086
0
    UINT64_C(1174405148), // MIN_S
2087
0
    UINT64_C(2046820366), // MIN_S_B
2088
0
    UINT64_C(2053111822), // MIN_S_D
2089
0
    UINT64_C(2048917518), // MIN_S_H
2090
0
    UINT64_C(1409286147), // MIN_S_MMR6
2091
0
    UINT64_C(2051014670), // MIN_S_W
2092
0
    UINT64_C(2055208974), // MIN_U_B
2093
0
    UINT64_C(2061500430), // MIN_U_D
2094
0
    UINT64_C(2057306126), // MIN_U_H
2095
0
    UINT64_C(2059403278), // MIN_U_W
2096
0
    UINT64_C(218),  // MOD
2097
0
    UINT64_C(2080375952), // MODSUB
2098
0
    UINT64_C(661),  // MODSUB_MM
2099
0
    UINT64_C(219),  // MODU
2100
0
    UINT64_C(472),  // MODU_MMR6
2101
0
    UINT64_C(344),  // MOD_MMR6
2102
0
    UINT64_C(2063597586), // MOD_S_B
2103
0
    UINT64_C(2069889042), // MOD_S_D
2104
0
    UINT64_C(2065694738), // MOD_S_H
2105
0
    UINT64_C(2067791890), // MOD_S_W
2106
0
    UINT64_C(2071986194), // MOD_U_B
2107
0
    UINT64_C(2078277650), // MOD_U_D
2108
0
    UINT64_C(2074083346), // MOD_U_H
2109
0
    UINT64_C(2076180498), // MOD_U_W
2110
0
    UINT64_C(3072), // MOVE16_MM
2111
0
    UINT64_C(3072), // MOVE16_MMR6
2112
0
    UINT64_C(33792),  // MOVEP_MM
2113
0
    UINT64_C(17412),  // MOVEP_MMR6
2114
0
    UINT64_C(2025717785), // MOVE_V
2115
0
    UINT64_C(1176502289), // MOVF_D32
2116
0
    UINT64_C(1409286688), // MOVF_D32_MM
2117
0
    UINT64_C(1176502289), // MOVF_D64
2118
0
    UINT64_C(1),  // MOVF_I
2119
0
    UINT64_C(1),  // MOVF_I64
2120
0
    UINT64_C(1409286523), // MOVF_I_MM
2121
0
    UINT64_C(1174405137), // MOVF_S
2122
0
    UINT64_C(1409286176), // MOVF_S_MM
2123
0
    UINT64_C(1176502291), // MOVN_I64_D64
2124
0
    UINT64_C(11), // MOVN_I64_I
2125
0
    UINT64_C(11), // MOVN_I64_I64
2126
0
    UINT64_C(1174405139), // MOVN_I64_S
2127
0
    UINT64_C(1176502291), // MOVN_I_D32
2128
0
    UINT64_C(1409286456), // MOVN_I_D32_MM
2129
0
    UINT64_C(1176502291), // MOVN_I_D64
2130
0
    UINT64_C(11), // MOVN_I_I
2131
0
    UINT64_C(11), // MOVN_I_I64
2132
0
    UINT64_C(24), // MOVN_I_MM
2133
0
    UINT64_C(1174405139), // MOVN_I_S
2134
0
    UINT64_C(1409286200), // MOVN_I_S_MM
2135
0
    UINT64_C(1176567825), // MOVT_D32
2136
0
    UINT64_C(1409286752), // MOVT_D32_MM
2137
0
    UINT64_C(1176567825), // MOVT_D64
2138
0
    UINT64_C(65537),  // MOVT_I
2139
0
    UINT64_C(65537),  // MOVT_I64
2140
0
    UINT64_C(1409288571), // MOVT_I_MM
2141
0
    UINT64_C(1174470673), // MOVT_S
2142
0
    UINT64_C(1409286240), // MOVT_S_MM
2143
0
    UINT64_C(1176502290), // MOVZ_I64_D64
2144
0
    UINT64_C(10), // MOVZ_I64_I
2145
0
    UINT64_C(10), // MOVZ_I64_I64
2146
0
    UINT64_C(1174405138), // MOVZ_I64_S
2147
0
    UINT64_C(1176502290), // MOVZ_I_D32
2148
0
    UINT64_C(1409286520), // MOVZ_I_D32_MM
2149
0
    UINT64_C(1176502290), // MOVZ_I_D64
2150
0
    UINT64_C(10), // MOVZ_I_I
2151
0
    UINT64_C(10), // MOVZ_I_I64
2152
0
    UINT64_C(88), // MOVZ_I_MM
2153
0
    UINT64_C(1174405138), // MOVZ_I_S
2154
0
    UINT64_C(1409286264), // MOVZ_I_S_MM
2155
0
    UINT64_C(1879048196), // MSUB
2156
0
    UINT64_C(1176502297), // MSUBF_D
2157
0
    UINT64_C(1409287160), // MSUBF_D_MMR6
2158
0
    UINT64_C(1174405145), // MSUBF_S
2159
0
    UINT64_C(1409286648), // MSUBF_S_MMR6
2160
0
    UINT64_C(2071986204), // MSUBR_Q_H
2161
0
    UINT64_C(2074083356), // MSUBR_Q_W
2162
0
    UINT64_C(1879048197), // MSUBU
2163
0
    UINT64_C(1879048197), // MSUBU_DSP
2164
0
    UINT64_C(15036),  // MSUBU_DSP_MM
2165
0
    UINT64_C(64316),  // MSUBU_MM
2166
0
    UINT64_C(2030043154), // MSUBV_B
2167
0
    UINT64_C(2036334610), // MSUBV_D
2168
0
    UINT64_C(2032140306), // MSUBV_H
2169
0
    UINT64_C(2034237458), // MSUBV_W
2170
0
    UINT64_C(1275068457), // MSUB_D32
2171
0
    UINT64_C(1409286185), // MSUB_D32_MM
2172
0
    UINT64_C(1275068457), // MSUB_D64
2173
0
    UINT64_C(1879048196), // MSUB_DSP
2174
0
    UINT64_C(10940),  // MSUB_DSP_MM
2175
0
    UINT64_C(60220),  // MSUB_MM
2176
0
    UINT64_C(2038431772), // MSUB_Q_H
2177
0
    UINT64_C(2040528924), // MSUB_Q_W
2178
0
    UINT64_C(1275068456), // MSUB_S
2179
0
    UINT64_C(1409286177), // MSUB_S_MM
2180
0
    UINT64_C(1082130432), // MTC0
2181
0
    UINT64_C(764),  // MTC0_MMR6
2182
0
    UINT64_C(1149239296), // MTC1
2183
0
    UINT64_C(1149239296), // MTC1_D64
2184
0
    UINT64_C(1409296443), // MTC1_D64_MM
2185
0
    UINT64_C(1409296443), // MTC1_MM
2186
0
    UINT64_C(1409296443), // MTC1_MMR6
2187
0
    UINT64_C(1216348160), // MTC2
2188
0
    UINT64_C(23868),  // MTC2_MMR6
2189
0
    UINT64_C(1080033792), // MTGC0
2190
0
    UINT64_C(1788), // MTGC0_MM
2191
0
    UINT64_C(756),  // MTHC0_MMR6
2192
0
    UINT64_C(1155530752), // MTHC1_D32
2193
0
    UINT64_C(1409300539), // MTHC1_D32_MM
2194
0
    UINT64_C(1155530752), // MTHC1_D64
2195
0
    UINT64_C(1409300539), // MTHC1_D64_MM
2196
0
    UINT64_C(40252),  // MTHC2_MMR6
2197
0
    UINT64_C(1080034816), // MTHGC0
2198
0
    UINT64_C(1780), // MTHGC0_MM
2199
0
    UINT64_C(17), // MTHI
2200
0
    UINT64_C(17), // MTHI64
2201
0
    UINT64_C(17), // MTHI_DSP
2202
0
    UINT64_C(8316), // MTHI_DSP_MM
2203
0
    UINT64_C(11644),  // MTHI_MM
2204
0
    UINT64_C(2080376824), // MTHLIP
2205
0
    UINT64_C(636),  // MTHLIP_MM
2206
0
    UINT64_C(19), // MTLO
2207
0
    UINT64_C(19), // MTLO64
2208
0
    UINT64_C(19), // MTLO_DSP
2209
0
    UINT64_C(12412),  // MTLO_DSP_MM
2210
0
    UINT64_C(15740),  // MTLO_MM
2211
0
    UINT64_C(1879048200), // MTM0
2212
0
    UINT64_C(1879048204), // MTM1
2213
0
    UINT64_C(1879048205), // MTM2
2214
0
    UINT64_C(1879048201), // MTP0
2215
0
    UINT64_C(1879048202), // MTP1
2216
0
    UINT64_C(1879048203), // MTP2
2217
0
    UINT64_C(1098907648), // MTTR
2218
0
    UINT64_C(216),  // MUH
2219
0
    UINT64_C(217),  // MUHU
2220
0
    UINT64_C(216),  // MUHU_MMR6
2221
0
    UINT64_C(88), // MUH_MMR6
2222
0
    UINT64_C(1879048194), // MUL
2223
0
    UINT64_C(2080376592), // MULEQ_S_W_PHL
2224
0
    UINT64_C(37), // MULEQ_S_W_PHL_MM
2225
0
    UINT64_C(2080376656), // MULEQ_S_W_PHR
2226
0
    UINT64_C(101),  // MULEQ_S_W_PHR_MM
2227
0
    UINT64_C(2080375184), // MULEU_S_PH_QBL
2228
0
    UINT64_C(149),  // MULEU_S_PH_QBL_MM
2229
0
    UINT64_C(2080375248), // MULEU_S_PH_QBR
2230
0
    UINT64_C(213),  // MULEU_S_PH_QBR_MM
2231
0
    UINT64_C(2080376784), // MULQ_RS_PH
2232
0
    UINT64_C(277),  // MULQ_RS_PH_MM
2233
0
    UINT64_C(2080376280), // MULQ_RS_W
2234
0
    UINT64_C(405),  // MULQ_RS_W_MMR2
2235
0
    UINT64_C(2080376720), // MULQ_S_PH
2236
0
    UINT64_C(341),  // MULQ_S_PH_MMR2
2237
0
    UINT64_C(2080376216), // MULQ_S_W
2238
0
    UINT64_C(469),  // MULQ_S_W_MMR2
2239
0
    UINT64_C(1186988058), // MULR_PS64
2240
0
    UINT64_C(2063597596), // MULR_Q_H
2241
0
    UINT64_C(2065694748), // MULR_Q_W
2242
0
    UINT64_C(2080375216), // MULSAQ_S_W_PH
2243
0
    UINT64_C(15548),  // MULSAQ_S_W_PH_MM
2244
0
    UINT64_C(2080374960), // MULSA_W_PH
2245
0
    UINT64_C(11452),  // MULSA_W_PH_MMR2
2246
0
    UINT64_C(24), // MULT
2247
0
    UINT64_C(25), // MULTU_DSP
2248
0
    UINT64_C(7356), // MULTU_DSP_MM
2249
0
    UINT64_C(24), // MULT_DSP
2250
0
    UINT64_C(3260), // MULT_DSP_MM
2251
0
    UINT64_C(35644),  // MULT_MM
2252
0
    UINT64_C(25), // MULTu
2253
0
    UINT64_C(39740),  // MULTu_MM
2254
0
    UINT64_C(153),  // MULU
2255
0
    UINT64_C(152),  // MULU_MMR6
2256
0
    UINT64_C(2013265938), // MULV_B
2257
0
    UINT64_C(2019557394), // MULV_D
2258
0
    UINT64_C(2015363090), // MULV_H
2259
0
    UINT64_C(2017460242), // MULV_W
2260
0
    UINT64_C(528),  // MUL_MM
2261
0
    UINT64_C(24), // MUL_MMR6
2262
0
    UINT64_C(2080375576), // MUL_PH
2263
0
    UINT64_C(45), // MUL_PH_MMR2
2264
0
    UINT64_C(2030043164), // MUL_Q_H
2265
0
    UINT64_C(2032140316), // MUL_Q_W
2266
0
    UINT64_C(152),  // MUL_R6
2267
0
    UINT64_C(2080375704), // MUL_S_PH
2268
0
    UINT64_C(1069), // MUL_S_PH_MMR2
2269
0
    UINT64_C(59408),  // Mfhi16
2270
0
    UINT64_C(59410),  // Mflo16
2271
0
    UINT64_C(25856),  // Move32R16
2272
0
    UINT64_C(26368),  // MoveR3216
2273
0
    UINT64_C(2064121886), // NLOC_B
2274
0
    UINT64_C(2064318494), // NLOC_D
2275
0
    UINT64_C(2064187422), // NLOC_H
2276
0
    UINT64_C(2064252958), // NLOC_W
2277
0
    UINT64_C(2064384030), // NLZC_B
2278
0
    UINT64_C(2064580638), // NLZC_D
2279
0
    UINT64_C(2064449566), // NLZC_H
2280
0
    UINT64_C(2064515102), // NLZC_W
2281
0
    UINT64_C(1275068465), // NMADD_D32
2282
0
    UINT64_C(1409286154), // NMADD_D32_MM
2283
0
    UINT64_C(1275068465), // NMADD_D64
2284
0
    UINT64_C(1275068464), // NMADD_S
2285
0
    UINT64_C(1409286146), // NMADD_S_MM
2286
0
    UINT64_C(1275068473), // NMSUB_D32
2287
0
    UINT64_C(1409286186), // NMSUB_D32_MM
2288
0
    UINT64_C(1275068473), // NMSUB_D64
2289
0
    UINT64_C(1275068472), // NMSUB_S
2290
0
    UINT64_C(1409286178), // NMSUB_S_MM
2291
0
    UINT64_C(39), // NOR
2292
0
    UINT64_C(39), // NOR64
2293
0
    UINT64_C(2046820352), // NORI_B
2294
0
    UINT64_C(720),  // NOR_MM
2295
0
    UINT64_C(720),  // NOR_MMR6
2296
0
    UINT64_C(2017460254), // NOR_V
2297
0
    UINT64_C(17408),  // NOT16_MM
2298
0
    UINT64_C(17408),  // NOT16_MMR6
2299
0
    UINT64_C(59421),  // NegRxRy16
2300
0
    UINT64_C(59407),  // NotRxRy16
2301
0
    UINT64_C(37), // OR
2302
0
    UINT64_C(17600),  // OR16_MM
2303
0
    UINT64_C(17417),  // OR16_MMR6
2304
0
    UINT64_C(37), // OR64
2305
0
    UINT64_C(2030043136), // ORI_B
2306
0
    UINT64_C(1342177280), // ORI_MMR6
2307
0
    UINT64_C(656),  // OR_MM
2308
0
    UINT64_C(656),  // OR_MMR6
2309
0
    UINT64_C(2015363102), // OR_V
2310
0
    UINT64_C(872415232),  // ORi
2311
0
    UINT64_C(872415232),  // ORi64
2312
0
    UINT64_C(1342177280), // ORi_MM
2313
0
    UINT64_C(59405),  // OrRxRxRy16
2314
0
    UINT64_C(2080375697), // PACKRL_PH
2315
0
    UINT64_C(429),  // PACKRL_PH_MM
2316
0
    UINT64_C(320),  // PAUSE
2317
0
    UINT64_C(10240),  // PAUSE_MM
2318
0
    UINT64_C(10240),  // PAUSE_MMR6
2319
0
    UINT64_C(2030043156), // PCKEV_B
2320
0
    UINT64_C(2036334612), // PCKEV_D
2321
0
    UINT64_C(2032140308), // PCKEV_H
2322
0
    UINT64_C(2034237460), // PCKEV_W
2323
0
    UINT64_C(2038431764), // PCKOD_B
2324
0
    UINT64_C(2044723220), // PCKOD_D
2325
0
    UINT64_C(2040528916), // PCKOD_H
2326
0
    UINT64_C(2042626068), // PCKOD_W
2327
0
    UINT64_C(2063859742), // PCNT_B
2328
0
    UINT64_C(2064056350), // PCNT_D
2329
0
    UINT64_C(2063925278), // PCNT_H
2330
0
    UINT64_C(2063990814), // PCNT_W
2331
0
    UINT64_C(2080375505), // PICK_PH
2332
0
    UINT64_C(557),  // PICK_PH_MM
2333
0
    UINT64_C(2080374993), // PICK_QB
2334
0
    UINT64_C(493),  // PICK_QB_MM
2335
0
    UINT64_C(1186988076), // PLL_PS64
2336
0
    UINT64_C(1186988077), // PLU_PS64
2337
0
    UINT64_C(1879048236), // POP
2338
0
    UINT64_C(2080375058), // PRECEQU_PH_QBL
2339
0
    UINT64_C(2080375186), // PRECEQU_PH_QBLA
2340
0
    UINT64_C(29500),  // PRECEQU_PH_QBLA_MM
2341
0
    UINT64_C(28988),  // PRECEQU_PH_QBL_MM
2342
0
    UINT64_C(2080375122), // PRECEQU_PH_QBR
2343
0
    UINT64_C(2080375250), // PRECEQU_PH_QBRA
2344
0
    UINT64_C(37692),  // PRECEQU_PH_QBRA_MM
2345
0
    UINT64_C(37180),  // PRECEQU_PH_QBR_MM
2346
0
    UINT64_C(2080375570), // PRECEQ_W_PHL
2347
0
    UINT64_C(20796),  // PRECEQ_W_PHL_MM
2348
0
    UINT64_C(2080375634), // PRECEQ_W_PHR
2349
0
    UINT64_C(24892),  // PRECEQ_W_PHR_MM
2350
0
    UINT64_C(2080376594), // PRECEU_PH_QBL
2351
0
    UINT64_C(2080376722), // PRECEU_PH_QBLA
2352
0
    UINT64_C(45884),  // PRECEU_PH_QBLA_MM
2353
0
    UINT64_C(45372),  // PRECEU_PH_QBL_MM
2354
0
    UINT64_C(2080376658), // PRECEU_PH_QBR
2355
0
    UINT64_C(2080376786), // PRECEU_PH_QBRA
2356
0
    UINT64_C(54076),  // PRECEU_PH_QBRA_MM
2357
0
    UINT64_C(53564),  // PRECEU_PH_QBR_MM
2358
0
    UINT64_C(2080375761), // PRECRQU_S_QB_PH
2359
0
    UINT64_C(365),  // PRECRQU_S_QB_PH_MM
2360
0
    UINT64_C(2080376081), // PRECRQ_PH_W
2361
0
    UINT64_C(237),  // PRECRQ_PH_W_MM
2362
0
    UINT64_C(2080375569), // PRECRQ_QB_PH
2363
0
    UINT64_C(173),  // PRECRQ_QB_PH_MM
2364
0
    UINT64_C(2080376145), // PRECRQ_RS_PH_W
2365
0
    UINT64_C(301),  // PRECRQ_RS_PH_W_MM
2366
0
    UINT64_C(2080375633), // PRECR_QB_PH
2367
0
    UINT64_C(109),  // PRECR_QB_PH_MMR2
2368
0
    UINT64_C(2080376721), // PRECR_SRA_PH_W
2369
0
    UINT64_C(973),  // PRECR_SRA_PH_W_MMR2
2370
0
    UINT64_C(2080376785), // PRECR_SRA_R_PH_W
2371
0
    UINT64_C(1997), // PRECR_SRA_R_PH_W_MMR2
2372
0
    UINT64_C(3422552064), // PREF
2373
0
    UINT64_C(2080374819), // PREFE
2374
0
    UINT64_C(1610654720), // PREFE_MM
2375
0
    UINT64_C(1409286560), // PREFX_MM
2376
0
    UINT64_C(1610620928), // PREF_MM
2377
0
    UINT64_C(1610620928), // PREF_MMR6
2378
0
    UINT64_C(2080374837), // PREF_R6
2379
0
    UINT64_C(2080374897), // PREPEND
2380
0
    UINT64_C(597),  // PREPEND_MMR2
2381
0
    UINT64_C(1186988078), // PUL_PS64
2382
0
    UINT64_C(1186988079), // PUU_PS64
2383
0
    UINT64_C(2080376080), // RADDU_W_QB
2384
0
    UINT64_C(61756),  // RADDU_W_QB_MM
2385
0
    UINT64_C(2080375992), // RDDSP
2386
0
    UINT64_C(1660), // RDDSP_MM
2387
0
    UINT64_C(2080374843), // RDHWR
2388
0
    UINT64_C(2080374843), // RDHWR64
2389
0
    UINT64_C(27452),  // RDHWR_MM
2390
0
    UINT64_C(448),  // RDHWR_MMR6
2391
0
    UINT64_C(57724),  // RDPGPR_MMR6
2392
0
    UINT64_C(1176502293), // RECIP_D32
2393
0
    UINT64_C(1409307195), // RECIP_D32_MM
2394
0
    UINT64_C(1176502293), // RECIP_D64
2395
0
    UINT64_C(1409307195), // RECIP_D64_MM
2396
0
    UINT64_C(1174405141), // RECIP_S
2397
0
    UINT64_C(1409290811), // RECIP_S_MM
2398
0
    UINT64_C(2080375506), // REPLV_PH
2399
0
    UINT64_C(828),  // REPLV_PH_MM
2400
0
    UINT64_C(2080374994), // REPLV_QB
2401
0
    UINT64_C(4924), // REPLV_QB_MM
2402
0
    UINT64_C(2080375442), // REPL_PH
2403
0
    UINT64_C(61), // REPL_PH_MM
2404
0
    UINT64_C(2080374930), // REPL_QB
2405
0
    UINT64_C(1532), // REPL_QB_MM
2406
0
    UINT64_C(1176502298), // RINT_D
2407
0
    UINT64_C(1409286688), // RINT_D_MMR6
2408
0
    UINT64_C(1174405146), // RINT_S
2409
0
    UINT64_C(1409286176), // RINT_S_MMR6
2410
0
    UINT64_C(2097154),  // ROTR
2411
0
    UINT64_C(70), // ROTRV
2412
0
    UINT64_C(208),  // ROTRV_MM
2413
0
    UINT64_C(192),  // ROTR_MM
2414
0
    UINT64_C(1176502280), // ROUND_L_D64
2415
0
    UINT64_C(1409315643), // ROUND_L_D_MMR6
2416
0
    UINT64_C(1174405128), // ROUND_L_S
2417
0
    UINT64_C(1409299259), // ROUND_L_S_MMR6
2418
0
    UINT64_C(1176502284), // ROUND_W_D32
2419
0
    UINT64_C(1176502284), // ROUND_W_D64
2420
0
    UINT64_C(1409317691), // ROUND_W_D_MMR6
2421
0
    UINT64_C(1409317691), // ROUND_W_MM
2422
0
    UINT64_C(1174405132), // ROUND_W_S
2423
0
    UINT64_C(1409301307), // ROUND_W_S_MM
2424
0
    UINT64_C(1409301307), // ROUND_W_S_MMR6
2425
0
    UINT64_C(1176502294), // RSQRT_D32
2426
0
    UINT64_C(1409303099), // RSQRT_D32_MM
2427
0
    UINT64_C(1176502294), // RSQRT_D64
2428
0
    UINT64_C(1409303099), // RSQRT_D64_MM
2429
0
    UINT64_C(1174405142), // RSQRT_S
2430
0
    UINT64_C(1409286715), // RSQRT_S_MM
2431
0
    UINT64_C(25728),  // Restore16
2432
0
    UINT64_C(25728),  // RestoreX16
2433
0
    UINT64_C(1879048216), // SAA
2434
0
    UINT64_C(1879048217), // SAAD
2435
0
    UINT64_C(2020605962), // SAT_S_B
2436
0
    UINT64_C(2013265930), // SAT_S_D
2437
0
    UINT64_C(2019557386), // SAT_S_H
2438
0
    UINT64_C(2017460234), // SAT_S_W
2439
0
    UINT64_C(2028994570), // SAT_U_B
2440
0
    UINT64_C(2021654538), // SAT_U_D
2441
0
    UINT64_C(2027945994), // SAT_U_H
2442
0
    UINT64_C(2025848842), // SAT_U_W
2443
0
    UINT64_C(2684354560), // SB
2444
0
    UINT64_C(34816),  // SB16_MM
2445
0
    UINT64_C(34816),  // SB16_MMR6
2446
0
    UINT64_C(2684354560), // SB64
2447
0
    UINT64_C(2080374812), // SBE
2448
0
    UINT64_C(1610655744), // SBE_MM
2449
0
    UINT64_C(402653184),  // SB_MM
2450
0
    UINT64_C(402653184),  // SB_MMR6
2451
0
    UINT64_C(3758096384), // SC
2452
0
    UINT64_C(3758096384), // SC64
2453
0
    UINT64_C(2080374822), // SC64_R6
2454
0
    UINT64_C(4026531840), // SCD
2455
0
    UINT64_C(2080374823), // SCD_R6
2456
0
    UINT64_C(2080374814), // SCE
2457
0
    UINT64_C(1610656768), // SCE_MM
2458
0
    UINT64_C(1610657792), // SC_MM
2459
0
    UINT64_C(1610657792), // SC_MMR6
2460
0
    UINT64_C(2080374822), // SC_R6
2461
0
    UINT64_C(4227858432), // SD
2462
0
    UINT64_C(1879048255), // SDBBP
2463
0
    UINT64_C(18112),  // SDBBP16_MM
2464
0
    UINT64_C(17467),  // SDBBP16_MMR6
2465
0
    UINT64_C(56188),  // SDBBP_MM
2466
0
    UINT64_C(56188),  // SDBBP_MMR6
2467
0
    UINT64_C(14), // SDBBP_R6
2468
0
    UINT64_C(4093640704), // SDC1
2469
0
    UINT64_C(4093640704), // SDC164
2470
0
    UINT64_C(3087007744), // SDC1_D64_MMR6
2471
0
    UINT64_C(3087007744), // SDC1_MM_D32
2472
0
    UINT64_C(3087007744), // SDC1_MM_D64
2473
0
    UINT64_C(4160749568), // SDC2
2474
0
    UINT64_C(536911872),  // SDC2_MMR6
2475
0
    UINT64_C(1239416832), // SDC2_R6
2476
0
    UINT64_C(4227858432), // SDC3
2477
0
    UINT64_C(26), // SDIV
2478
0
    UINT64_C(43836),  // SDIV_MM
2479
0
    UINT64_C(2952790016), // SDL
2480
0
    UINT64_C(3019898880), // SDR
2481
0
    UINT64_C(1275068425), // SDXC1
2482
0
    UINT64_C(1275068425), // SDXC164
2483
0
    UINT64_C(2080375840), // SEB
2484
0
    UINT64_C(2080375840), // SEB64
2485
0
    UINT64_C(11068),  // SEB_MM
2486
0
    UINT64_C(2080376352), // SEH
2487
0
    UINT64_C(2080376352), // SEH64
2488
0
    UINT64_C(15164),  // SEH_MM
2489
0
    UINT64_C(53), // SELEQZ
2490
0
    UINT64_C(53), // SELEQZ64
2491
0
    UINT64_C(1176502292), // SELEQZ_D
2492
0
    UINT64_C(1409286712), // SELEQZ_D_MMR6
2493
0
    UINT64_C(320),  // SELEQZ_MMR6
2494
0
    UINT64_C(1174405140), // SELEQZ_S
2495
0
    UINT64_C(1409286200), // SELEQZ_S_MMR6
2496
0
    UINT64_C(55), // SELNEZ
2497
0
    UINT64_C(55), // SELNEZ64
2498
0
    UINT64_C(1176502295), // SELNEZ_D
2499
0
    UINT64_C(1409286776), // SELNEZ_D_MMR6
2500
0
    UINT64_C(384),  // SELNEZ_MMR6
2501
0
    UINT64_C(1174405143), // SELNEZ_S
2502
0
    UINT64_C(1409286264), // SELNEZ_S_MMR6
2503
0
    UINT64_C(1176502288), // SEL_D
2504
0
    UINT64_C(1409286840), // SEL_D_MMR6
2505
0
    UINT64_C(1174405136), // SEL_S
2506
0
    UINT64_C(1409286328), // SEL_S_MMR6
2507
0
    UINT64_C(1879048234), // SEQ
2508
0
    UINT64_C(1879048238), // SEQi
2509
0
    UINT64_C(2751463424), // SH
2510
0
    UINT64_C(43008),  // SH16_MM
2511
0
    UINT64_C(43008),  // SH16_MMR6
2512
0
    UINT64_C(2751463424), // SH64
2513
0
    UINT64_C(2080374813), // SHE
2514
0
    UINT64_C(1610656256), // SHE_MM
2515
0
    UINT64_C(2013265922), // SHF_B
2516
0
    UINT64_C(2030043138), // SHF_H
2517
0
    UINT64_C(2046820354), // SHF_W
2518
0
    UINT64_C(2080376504), // SHILO
2519
0
    UINT64_C(2080376568), // SHILOV
2520
0
    UINT64_C(4732), // SHILOV_MM
2521
0
    UINT64_C(29), // SHILO_MM
2522
0
    UINT64_C(2080375443), // SHLLV_PH
2523
0
    UINT64_C(14), // SHLLV_PH_MM
2524
0
    UINT64_C(2080374931), // SHLLV_QB
2525
0
    UINT64_C(917),  // SHLLV_QB_MM
2526
0
    UINT64_C(2080375699), // SHLLV_S_PH
2527
0
    UINT64_C(1038), // SHLLV_S_PH_MM
2528
0
    UINT64_C(2080376211), // SHLLV_S_W
2529
0
    UINT64_C(981),  // SHLLV_S_W_MM
2530
0
    UINT64_C(2080375315), // SHLL_PH
2531
0
    UINT64_C(949),  // SHLL_PH_MM
2532
0
    UINT64_C(2080374803), // SHLL_QB
2533
0
    UINT64_C(2172), // SHLL_QB_MM
2534
0
    UINT64_C(2080375571), // SHLL_S_PH
2535
0
    UINT64_C(2997), // SHLL_S_PH_MM
2536
0
    UINT64_C(2080376083), // SHLL_S_W
2537
0
    UINT64_C(1013), // SHLL_S_W_MM
2538
0
    UINT64_C(2080375507), // SHRAV_PH
2539
0
    UINT64_C(397),  // SHRAV_PH_MM
2540
0
    UINT64_C(2080375187), // SHRAV_QB
2541
0
    UINT64_C(461),  // SHRAV_QB_MMR2
2542
0
    UINT64_C(2080375763), // SHRAV_R_PH
2543
0
    UINT64_C(1421), // SHRAV_R_PH_MM
2544
0
    UINT64_C(2080375251), // SHRAV_R_QB
2545
0
    UINT64_C(1485), // SHRAV_R_QB_MMR2
2546
0
    UINT64_C(2080376275), // SHRAV_R_W
2547
0
    UINT64_C(725),  // SHRAV_R_W_MM
2548
0
    UINT64_C(2080375379), // SHRA_PH
2549
0
    UINT64_C(821),  // SHRA_PH_MM
2550
0
    UINT64_C(2080375059), // SHRA_QB
2551
0
    UINT64_C(508),  // SHRA_QB_MMR2
2552
0
    UINT64_C(2080375635), // SHRA_R_PH
2553
0
    UINT64_C(1845), // SHRA_R_PH_MM
2554
0
    UINT64_C(2080375123), // SHRA_R_QB
2555
0
    UINT64_C(4604), // SHRA_R_QB_MMR2
2556
0
    UINT64_C(2080376147), // SHRA_R_W
2557
0
    UINT64_C(757),  // SHRA_R_W_MM
2558
0
    UINT64_C(2080376531), // SHRLV_PH
2559
0
    UINT64_C(789),  // SHRLV_PH_MMR2
2560
0
    UINT64_C(2080374995), // SHRLV_QB
2561
0
    UINT64_C(853),  // SHRLV_QB_MM
2562
0
    UINT64_C(2080376403), // SHRL_PH
2563
0
    UINT64_C(1020), // SHRL_PH_MMR2
2564
0
    UINT64_C(2080374867), // SHRL_QB
2565
0
    UINT64_C(6268), // SHRL_QB_MM
2566
0
    UINT64_C(939524096),  // SH_MM
2567
0
    UINT64_C(939524096),  // SH_MMR6
2568
0
    UINT64_C(68616192), // SIGRIE
2569
0
    UINT64_C(63), // SIGRIE_MMR6
2570
0
    UINT64_C(2013265945), // SLDI_B
2571
0
    UINT64_C(2016935961), // SLDI_D
2572
0
    UINT64_C(2015363097), // SLDI_H
2573
0
    UINT64_C(2016411673), // SLDI_W
2574
0
    UINT64_C(2013265940), // SLD_B
2575
0
    UINT64_C(2019557396), // SLD_D
2576
0
    UINT64_C(2015363092), // SLD_H
2577
0
    UINT64_C(2017460244), // SLD_W
2578
0
    UINT64_C(0),  // SLL
2579
0
    UINT64_C(9216), // SLL16_MM
2580
0
    UINT64_C(9216), // SLL16_MMR6
2581
0
    UINT64_C(0),  // SLL64_32
2582
0
    UINT64_C(0),  // SLL64_64
2583
0
    UINT64_C(2020605961), // SLLI_B
2584
0
    UINT64_C(2013265929), // SLLI_D
2585
0
    UINT64_C(2019557385), // SLLI_H
2586
0
    UINT64_C(2017460233), // SLLI_W
2587
0
    UINT64_C(4),  // SLLV
2588
0
    UINT64_C(16), // SLLV_MM
2589
0
    UINT64_C(2013265933), // SLL_B
2590
0
    UINT64_C(2019557389), // SLL_D
2591
0
    UINT64_C(2015363085), // SLL_H
2592
0
    UINT64_C(0),  // SLL_MM
2593
0
    UINT64_C(0),  // SLL_MMR6
2594
0
    UINT64_C(2017460237), // SLL_W
2595
0
    UINT64_C(42), // SLT
2596
0
    UINT64_C(42), // SLT64
2597
0
    UINT64_C(848),  // SLT_MM
2598
0
    UINT64_C(671088640),  // SLTi
2599
0
    UINT64_C(671088640),  // SLTi64
2600
0
    UINT64_C(2415919104), // SLTi_MM
2601
0
    UINT64_C(738197504),  // SLTiu
2602
0
    UINT64_C(738197504),  // SLTiu64
2603
0
    UINT64_C(2952790016), // SLTiu_MM
2604
0
    UINT64_C(43), // SLTu
2605
0
    UINT64_C(43), // SLTu64
2606
0
    UINT64_C(912),  // SLTu_MM
2607
0
    UINT64_C(1879048235), // SNE
2608
0
    UINT64_C(1879048239), // SNEi
2609
0
    UINT64_C(2017460249), // SPLATI_B
2610
0
    UINT64_C(2021130265), // SPLATI_D
2611
0
    UINT64_C(2019557401), // SPLATI_H
2612
0
    UINT64_C(2020605977), // SPLATI_W
2613
0
    UINT64_C(2021654548), // SPLAT_B
2614
0
    UINT64_C(2027946004), // SPLAT_D
2615
0
    UINT64_C(2023751700), // SPLAT_H
2616
0
    UINT64_C(2025848852), // SPLAT_W
2617
0
    UINT64_C(3),  // SRA
2618
0
    UINT64_C(2028994569), // SRAI_B
2619
0
    UINT64_C(2021654537), // SRAI_D
2620
0
    UINT64_C(2027945993), // SRAI_H
2621
0
    UINT64_C(2025848841), // SRAI_W
2622
0
    UINT64_C(2037383178), // SRARI_B
2623
0
    UINT64_C(2030043146), // SRARI_D
2624
0
    UINT64_C(2036334602), // SRARI_H
2625
0
    UINT64_C(2034237450), // SRARI_W
2626
0
    UINT64_C(2021654549), // SRAR_B
2627
0
    UINT64_C(2027946005), // SRAR_D
2628
0
    UINT64_C(2023751701), // SRAR_H
2629
0
    UINT64_C(2025848853), // SRAR_W
2630
0
    UINT64_C(7),  // SRAV
2631
0
    UINT64_C(144),  // SRAV_MM
2632
0
    UINT64_C(2021654541), // SRA_B
2633
0
    UINT64_C(2027945997), // SRA_D
2634
0
    UINT64_C(2023751693), // SRA_H
2635
0
    UINT64_C(128),  // SRA_MM
2636
0
    UINT64_C(2025848845), // SRA_W
2637
0
    UINT64_C(2),  // SRL
2638
0
    UINT64_C(9217), // SRL16_MM
2639
0
    UINT64_C(9217), // SRL16_MMR6
2640
0
    UINT64_C(2037383177), // SRLI_B
2641
0
    UINT64_C(2030043145), // SRLI_D
2642
0
    UINT64_C(2036334601), // SRLI_H
2643
0
    UINT64_C(2034237449), // SRLI_W
2644
0
    UINT64_C(2045771786), // SRLRI_B
2645
0
    UINT64_C(2038431754), // SRLRI_D
2646
0
    UINT64_C(2044723210), // SRLRI_H
2647
0
    UINT64_C(2042626058), // SRLRI_W
2648
0
    UINT64_C(2030043157), // SRLR_B
2649
0
    UINT64_C(2036334613), // SRLR_D
2650
0
    UINT64_C(2032140309), // SRLR_H
2651
0
    UINT64_C(2034237461), // SRLR_W
2652
0
    UINT64_C(6),  // SRLV
2653
0
    UINT64_C(80), // SRLV_MM
2654
0
    UINT64_C(2030043149), // SRL_B
2655
0
    UINT64_C(2036334605), // SRL_D
2656
0
    UINT64_C(2032140301), // SRL_H
2657
0
    UINT64_C(64), // SRL_MM
2658
0
    UINT64_C(2034237453), // SRL_W
2659
0
    UINT64_C(64), // SSNOP
2660
0
    UINT64_C(2048), // SSNOP_MM
2661
0
    UINT64_C(2048), // SSNOP_MMR6
2662
0
    UINT64_C(2013265956), // ST_B
2663
0
    UINT64_C(2013265959), // ST_D
2664
0
    UINT64_C(2013265957), // ST_H
2665
0
    UINT64_C(2013265958), // ST_W
2666
0
    UINT64_C(34), // SUB
2667
0
    UINT64_C(2080375384), // SUBQH_PH
2668
0
    UINT64_C(589),  // SUBQH_PH_MMR2
2669
0
    UINT64_C(2080375512), // SUBQH_R_PH
2670
0
    UINT64_C(1613), // SUBQH_R_PH_MMR2
2671
0
    UINT64_C(2080376024), // SUBQH_R_W
2672
0
    UINT64_C(1677), // SUBQH_R_W_MMR2
2673
0
    UINT64_C(2080375896), // SUBQH_W
2674
0
    UINT64_C(653),  // SUBQH_W_MMR2
2675
0
    UINT64_C(2080375504), // SUBQ_PH
2676
0
    UINT64_C(525),  // SUBQ_PH_MM
2677
0
    UINT64_C(2080375760), // SUBQ_S_PH
2678
0
    UINT64_C(1549), // SUBQ_S_PH_MM
2679
0
    UINT64_C(2080376272), // SUBQ_S_W
2680
0
    UINT64_C(837),  // SUBQ_S_W_MM
2681
0
    UINT64_C(2030043153), // SUBSUS_U_B
2682
0
    UINT64_C(2036334609), // SUBSUS_U_D
2683
0
    UINT64_C(2032140305), // SUBSUS_U_H
2684
0
    UINT64_C(2034237457), // SUBSUS_U_W
2685
0
    UINT64_C(2038431761), // SUBSUU_S_B
2686
0
    UINT64_C(2044723217), // SUBSUU_S_D
2687
0
    UINT64_C(2040528913), // SUBSUU_S_H
2688
0
    UINT64_C(2042626065), // SUBSUU_S_W
2689
0
    UINT64_C(2013265937), // SUBS_S_B
2690
0
    UINT64_C(2019557393), // SUBS_S_D
2691
0
    UINT64_C(2015363089), // SUBS_S_H
2692
0
    UINT64_C(2017460241), // SUBS_S_W
2693
0
    UINT64_C(2021654545), // SUBS_U_B
2694
0
    UINT64_C(2027946001), // SUBS_U_D
2695
0
    UINT64_C(2023751697), // SUBS_U_H
2696
0
    UINT64_C(2025848849), // SUBS_U_W
2697
0
    UINT64_C(1025), // SUBU16_MM
2698
0
    UINT64_C(1025), // SUBU16_MMR6
2699
0
    UINT64_C(2080374872), // SUBUH_QB
2700
0
    UINT64_C(845),  // SUBUH_QB_MMR2
2701
0
    UINT64_C(2080375000), // SUBUH_R_QB
2702
0
    UINT64_C(1869), // SUBUH_R_QB_MMR2
2703
0
    UINT64_C(464),  // SUBU_MMR6
2704
0
    UINT64_C(2080375376), // SUBU_PH
2705
0
    UINT64_C(781),  // SUBU_PH_MMR2
2706
0
    UINT64_C(2080374864), // SUBU_QB
2707
0
    UINT64_C(717),  // SUBU_QB_MM
2708
0
    UINT64_C(2080375632), // SUBU_S_PH
2709
0
    UINT64_C(1805), // SUBU_S_PH_MMR2
2710
0
    UINT64_C(2080375120), // SUBU_S_QB
2711
0
    UINT64_C(1741), // SUBU_S_QB_MM
2712
0
    UINT64_C(2021654534), // SUBVI_B
2713
0
    UINT64_C(2027945990), // SUBVI_D
2714
0
    UINT64_C(2023751686), // SUBVI_H
2715
0
    UINT64_C(2025848838), // SUBVI_W
2716
0
    UINT64_C(2021654542), // SUBV_B
2717
0
    UINT64_C(2027945998), // SUBV_D
2718
0
    UINT64_C(2023751694), // SUBV_H
2719
0
    UINT64_C(2025848846), // SUBV_W
2720
0
    UINT64_C(400),  // SUB_MM
2721
0
    UINT64_C(400),  // SUB_MMR6
2722
0
    UINT64_C(35), // SUBu
2723
0
    UINT64_C(464),  // SUBu_MM
2724
0
    UINT64_C(1275068429), // SUXC1
2725
0
    UINT64_C(1275068429), // SUXC164
2726
0
    UINT64_C(1409286536), // SUXC1_MM
2727
0
    UINT64_C(2885681152), // SW
2728
0
    UINT64_C(59392),  // SW16_MM
2729
0
    UINT64_C(59392),  // SW16_MMR6
2730
0
    UINT64_C(2885681152), // SW64
2731
0
    UINT64_C(3825205248), // SWC1
2732
0
    UINT64_C(2550136832), // SWC1_MM
2733
0
    UINT64_C(3892314112), // SWC2
2734
0
    UINT64_C(536903680),  // SWC2_MMR6
2735
0
    UINT64_C(1231028224), // SWC2_R6
2736
0
    UINT64_C(3959422976), // SWC3
2737
0
    UINT64_C(2885681152), // SWDSP
2738
0
    UINT64_C(4160749568), // SWDSP_MM
2739
0
    UINT64_C(2080374815), // SWE
2740
0
    UINT64_C(1610657280), // SWE_MM
2741
0
    UINT64_C(2818572288), // SWL
2742
0
    UINT64_C(2818572288), // SWL64
2743
0
    UINT64_C(2080374817), // SWLE
2744
0
    UINT64_C(1610653696), // SWLE_MM
2745
0
    UINT64_C(1610645504), // SWL_MM
2746
0
    UINT64_C(17728),  // SWM16_MM
2747
0
    UINT64_C(17418),  // SWM16_MMR6
2748
0
    UINT64_C(536924160),  // SWM32_MM
2749
0
    UINT64_C(536907776),  // SWP_MM
2750
0
    UINT64_C(3087007744), // SWR
2751
0
    UINT64_C(3087007744), // SWR64
2752
0
    UINT64_C(2080374818), // SWRE
2753
0
    UINT64_C(1610654208), // SWRE_MM
2754
0
    UINT64_C(1610649600), // SWR_MM
2755
0
    UINT64_C(51200),  // SWSP_MM
2756
0
    UINT64_C(51200),  // SWSP_MMR6
2757
0
    UINT64_C(1275068424), // SWXC1
2758
0
    UINT64_C(1409286280), // SWXC1_MM
2759
0
    UINT64_C(4160749568), // SW_MM
2760
0
    UINT64_C(4160749568), // SW_MMR6
2761
0
    UINT64_C(15), // SYNC
2762
0
    UINT64_C(69140480), // SYNCI
2763
0
    UINT64_C(1107296256), // SYNCI_MM
2764
0
    UINT64_C(1098907648), // SYNCI_MMR6
2765
0
    UINT64_C(27516),  // SYNC_MM
2766
0
    UINT64_C(27516),  // SYNC_MMR6
2767
0
    UINT64_C(12), // SYSCALL
2768
0
    UINT64_C(35708),  // SYSCALL_MM
2769
0
    UINT64_C(25728),  // Save16
2770
0
    UINT64_C(25728),  // SaveX16
2771
0
    UINT64_C(4026580992), // SbRxRyOffMemX16
2772
0
    UINT64_C(59537),  // SebRx16
2773
0
    UINT64_C(59569),  // SehRx16
2774
0
    UINT64_C(4026583040), // ShRxRyOffMemX16
2775
0
    UINT64_C(4026544128), // SllX16
2776
0
    UINT64_C(59396),  // SllvRxRy16
2777
0
    UINT64_C(59394),  // SltRxRy16
2778
0
    UINT64_C(20480),  // SltiRxImm16
2779
0
    UINT64_C(4026552320), // SltiRxImmX16
2780
0
    UINT64_C(22528),  // SltiuRxImm16
2781
0
    UINT64_C(4026554368), // SltiuRxImmX16
2782
0
    UINT64_C(59395),  // SltuRxRy16
2783
0
    UINT64_C(4026544131), // SraX16
2784
0
    UINT64_C(59399),  // SravRxRy16
2785
0
    UINT64_C(4026544130), // SrlX16
2786
0
    UINT64_C(59398),  // SrlvRxRy16
2787
0
    UINT64_C(57347),  // SubuRxRyRz16
2788
0
    UINT64_C(4026587136), // SwRxRyOffMemX16
2789
0
    UINT64_C(4026585088), // SwRxSpImmX16
2790
0
    UINT64_C(52), // TEQ
2791
0
    UINT64_C(67895296), // TEQI
2792
0
    UINT64_C(1103101952), // TEQI_MM
2793
0
    UINT64_C(60), // TEQ_MM
2794
0
    UINT64_C(48), // TGE
2795
0
    UINT64_C(67633152), // TGEI
2796
0
    UINT64_C(67698688), // TGEIU
2797
0
    UINT64_C(1096810496), // TGEIU_MM
2798
0
    UINT64_C(1092616192), // TGEI_MM
2799
0
    UINT64_C(49), // TGEU
2800
0
    UINT64_C(1084), // TGEU_MM
2801
0
    UINT64_C(572),  // TGE_MM
2802
0
    UINT64_C(1107296267), // TLBGINV
2803
0
    UINT64_C(1107296268), // TLBGINVF
2804
0
    UINT64_C(20860),  // TLBGINVF_MM
2805
0
    UINT64_C(16764),  // TLBGINV_MM
2806
0
    UINT64_C(1107296272), // TLBGP
2807
0
    UINT64_C(380),  // TLBGP_MM
2808
0
    UINT64_C(1107296265), // TLBGR
2809
0
    UINT64_C(4476), // TLBGR_MM
2810
0
    UINT64_C(1107296266), // TLBGWI
2811
0
    UINT64_C(8572), // TLBGWI_MM
2812
0
    UINT64_C(1107296270), // TLBGWR
2813
0
    UINT64_C(12668),  // TLBGWR_MM
2814
0
    UINT64_C(1107296259), // TLBINV
2815
0
    UINT64_C(1107296260), // TLBINVF
2816
0
    UINT64_C(21372),  // TLBINVF_MMR6
2817
0
    UINT64_C(17276),  // TLBINV_MMR6
2818
0
    UINT64_C(1107296264), // TLBP
2819
0
    UINT64_C(892),  // TLBP_MM
2820
0
    UINT64_C(1107296257), // TLBR
2821
0
    UINT64_C(4988), // TLBR_MM
2822
0
    UINT64_C(1107296258), // TLBWI
2823
0
    UINT64_C(9084), // TLBWI_MM
2824
0
    UINT64_C(1107296262), // TLBWR
2825
0
    UINT64_C(13180),  // TLBWR_MM
2826
0
    UINT64_C(50), // TLT
2827
0
    UINT64_C(67764224), // TLTI
2828
0
    UINT64_C(1094713344), // TLTIU_MM
2829
0
    UINT64_C(1090519040), // TLTI_MM
2830
0
    UINT64_C(51), // TLTU
2831
0
    UINT64_C(2620), // TLTU_MM
2832
0
    UINT64_C(2108), // TLT_MM
2833
0
    UINT64_C(54), // TNE
2834
0
    UINT64_C(68026368), // TNEI
2835
0
    UINT64_C(1098907648), // TNEI_MM
2836
0
    UINT64_C(3132), // TNE_MM
2837
0
    UINT64_C(1176502281), // TRUNC_L_D64
2838
0
    UINT64_C(1409311547), // TRUNC_L_D_MMR6
2839
0
    UINT64_C(1174405129), // TRUNC_L_S
2840
0
    UINT64_C(1409295163), // TRUNC_L_S_MMR6
2841
0
    UINT64_C(1176502285), // TRUNC_W_D32
2842
0
    UINT64_C(1176502285), // TRUNC_W_D64
2843
0
    UINT64_C(1409313595), // TRUNC_W_D_MMR6
2844
0
    UINT64_C(1409313595), // TRUNC_W_MM
2845
0
    UINT64_C(1174405133), // TRUNC_W_S
2846
0
    UINT64_C(1409297211), // TRUNC_W_S_MM
2847
0
    UINT64_C(1409297211), // TRUNC_W_S_MMR6
2848
0
    UINT64_C(67829760), // TTLTIU
2849
0
    UINT64_C(27), // UDIV
2850
0
    UINT64_C(47932),  // UDIV_MM
2851
0
    UINT64_C(1879048209), // V3MULU
2852
0
    UINT64_C(1879048208), // VMM0
2853
0
    UINT64_C(1879048207), // VMULU
2854
0
    UINT64_C(2013265941), // VSHF_B
2855
0
    UINT64_C(2019557397), // VSHF_D
2856
0
    UINT64_C(2015363093), // VSHF_H
2857
0
    UINT64_C(2017460245), // VSHF_W
2858
0
    UINT64_C(1107296288), // WAIT
2859
0
    UINT64_C(37756),  // WAIT_MM
2860
0
    UINT64_C(37756),  // WAIT_MMR6
2861
0
    UINT64_C(2080376056), // WRDSP
2862
0
    UINT64_C(5756), // WRDSP_MM
2863
0
    UINT64_C(61820),  // WRPGPR_MMR6
2864
0
    UINT64_C(2080374944), // WSBH
2865
0
    UINT64_C(31548),  // WSBH_MM
2866
0
    UINT64_C(31548),  // WSBH_MMR6
2867
0
    UINT64_C(38), // XOR
2868
0
    UINT64_C(17472),  // XOR16_MM
2869
0
    UINT64_C(17416),  // XOR16_MMR6
2870
0
    UINT64_C(38), // XOR64
2871
0
    UINT64_C(2063597568), // XORI_B
2872
0
    UINT64_C(1879048192), // XORI_MMR6
2873
0
    UINT64_C(784),  // XOR_MM
2874
0
    UINT64_C(784),  // XOR_MMR6
2875
0
    UINT64_C(2019557406), // XOR_V
2876
0
    UINT64_C(939524096),  // XORi
2877
0
    UINT64_C(939524096),  // XORi64
2878
0
    UINT64_C(1879048192), // XORi_MM
2879
0
    UINT64_C(59406),  // XorRxRxRy16
2880
0
    UINT64_C(2080374793), // YIELD
2881
0
    UINT64_C(0)
2882
0
  };
2883
0
  const unsigned opcode = MI.getOpcode();
2884
0
  uint64_t Value = InstBits[opcode];
2885
0
  uint64_t op = 0;
2886
0
  (void)op;  // suppress warning
2887
0
  switch (opcode) {
2888
0
    case Mips::Break16:
2889
0
    case Mips::DERET:
2890
0
    case Mips::DERET_MM:
2891
0
    case Mips::DERET_MMR6:
2892
0
    case Mips::EHB:
2893
0
    case Mips::EHB_MM:
2894
0
    case Mips::EHB_MMR6:
2895
0
    case Mips::ERET:
2896
0
    case Mips::ERETNC:
2897
0
    case Mips::ERETNC_MMR6:
2898
0
    case Mips::ERET_MM:
2899
0
    case Mips::ERET_MMR6:
2900
0
    case Mips::JrRa16:
2901
0
    case Mips::JrcRa16:
2902
0
    case Mips::JrcRx16:
2903
0
    case Mips::PAUSE:
2904
0
    case Mips::PAUSE_MM:
2905
0
    case Mips::PAUSE_MMR6:
2906
0
    case Mips::Restore16:
2907
0
    case Mips::RestoreX16:
2908
0
    case Mips::SSNOP:
2909
0
    case Mips::SSNOP_MM:
2910
0
    case Mips::SSNOP_MMR6:
2911
0
    case Mips::Save16:
2912
0
    case Mips::SaveX16:
2913
0
    case Mips::TLBGINV:
2914
0
    case Mips::TLBGINVF:
2915
0
    case Mips::TLBGINVF_MM:
2916
0
    case Mips::TLBGINV_MM:
2917
0
    case Mips::TLBGP:
2918
0
    case Mips::TLBGP_MM:
2919
0
    case Mips::TLBGR:
2920
0
    case Mips::TLBGR_MM:
2921
0
    case Mips::TLBGWI:
2922
0
    case Mips::TLBGWI_MM:
2923
0
    case Mips::TLBGWR:
2924
0
    case Mips::TLBGWR_MM:
2925
0
    case Mips::TLBINV:
2926
0
    case Mips::TLBINVF:
2927
0
    case Mips::TLBINVF_MMR6:
2928
0
    case Mips::TLBINV_MMR6:
2929
0
    case Mips::TLBP:
2930
0
    case Mips::TLBP_MM:
2931
0
    case Mips::TLBR:
2932
0
    case Mips::TLBR_MM:
2933
0
    case Mips::TLBWI:
2934
0
    case Mips::TLBWI_MM:
2935
0
    case Mips::TLBWR:
2936
0
    case Mips::TLBWR_MM:
2937
0
    case Mips::WAIT: {
2938
0
      break;
2939
0
    }
2940
0
    case Mips::MTHLIP:
2941
0
    case Mips::SHILOV: {
2942
      // op: ac
2943
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2944
0
      op &= UINT64_C(3);
2945
0
      op <<= 11;
2946
0
      Value |= op;
2947
      // op: rs
2948
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2949
0
      op &= UINT64_C(31);
2950
0
      op <<= 21;
2951
0
      Value |= op;
2952
0
      break;
2953
0
    }
2954
0
    case Mips::DPAQX_SA_W_PH:
2955
0
    case Mips::DPAQX_S_W_PH:
2956
0
    case Mips::DPAQ_SA_L_W:
2957
0
    case Mips::DPAQ_S_W_PH:
2958
0
    case Mips::DPAU_H_QBL:
2959
0
    case Mips::DPAU_H_QBR:
2960
0
    case Mips::DPAX_W_PH:
2961
0
    case Mips::DPA_W_PH:
2962
0
    case Mips::DPSQX_SA_W_PH:
2963
0
    case Mips::DPSQX_S_W_PH:
2964
0
    case Mips::DPSQ_SA_L_W:
2965
0
    case Mips::DPSQ_S_W_PH:
2966
0
    case Mips::DPSU_H_QBL:
2967
0
    case Mips::DPSU_H_QBR:
2968
0
    case Mips::DPSX_W_PH:
2969
0
    case Mips::DPS_W_PH:
2970
0
    case Mips::MADDU_DSP:
2971
0
    case Mips::MADD_DSP:
2972
0
    case Mips::MAQ_SA_W_PHL:
2973
0
    case Mips::MAQ_SA_W_PHR:
2974
0
    case Mips::MAQ_S_W_PHL:
2975
0
    case Mips::MAQ_S_W_PHR:
2976
0
    case Mips::MSUBU_DSP:
2977
0
    case Mips::MSUB_DSP:
2978
0
    case Mips::MULSAQ_S_W_PH:
2979
0
    case Mips::MULSA_W_PH:
2980
0
    case Mips::MULTU_DSP:
2981
0
    case Mips::MULT_DSP: {
2982
      // op: ac
2983
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2984
0
      op &= UINT64_C(3);
2985
0
      op <<= 11;
2986
0
      Value |= op;
2987
      // op: rs
2988
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2989
0
      op &= UINT64_C(31);
2990
0
      op <<= 21;
2991
0
      Value |= op;
2992
      // op: rt
2993
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2994
0
      op &= UINT64_C(31);
2995
0
      op <<= 16;
2996
0
      Value |= op;
2997
0
      break;
2998
0
    }
2999
0
    case Mips::SHILO: {
3000
      // op: ac
3001
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3002
0
      op &= UINT64_C(3);
3003
0
      op <<= 11;
3004
0
      Value |= op;
3005
      // op: shift
3006
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3007
0
      op &= UINT64_C(63);
3008
0
      op <<= 20;
3009
0
      Value |= op;
3010
0
      break;
3011
0
    }
3012
0
    case Mips::CACHEE:
3013
0
    case Mips::CACHE_R6:
3014
0
    case Mips::PREFE:
3015
0
    case Mips::PREF_R6: {
3016
      // op: addr
3017
0
      op = getMemEncoding(MI, 0, Fixups, STI);
3018
0
      Value |= (op & UINT64_C(2031616)) << 5;
3019
0
      Value |= (op & UINT64_C(511)) << 7;
3020
      // op: hint
3021
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3022
0
      op &= UINT64_C(31);
3023
0
      op <<= 16;
3024
0
      Value |= op;
3025
0
      break;
3026
0
    }
3027
0
    case Mips::SYNCI: {
3028
      // op: addr
3029
0
      op = getMemEncoding(MI, 0, Fixups, STI);
3030
0
      Value |= (op & UINT64_C(2031616)) << 5;
3031
0
      Value |= (op & UINT64_C(65535));
3032
0
      break;
3033
0
    }
3034
0
    case Mips::CACHE:
3035
0
    case Mips::PREF: {
3036
      // op: addr
3037
0
      op = getMemEncoding(MI, 0, Fixups, STI);
3038
0
      Value |= (op & UINT64_C(2031616)) << 5;
3039
0
      Value |= (op & UINT64_C(65535));
3040
      // op: hint
3041
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3042
0
      op &= UINT64_C(31);
3043
0
      op <<= 16;
3044
0
      Value |= op;
3045
0
      break;
3046
0
    }
3047
0
    case Mips::LD_B:
3048
0
    case Mips::ST_B: {
3049
      // op: addr
3050
0
      op = getMemEncoding(MI, 1, Fixups, STI);
3051
0
      Value |= (op & UINT64_C(1023)) << 16;
3052
0
      Value |= (op & UINT64_C(2031616)) >> 5;
3053
      // op: wd
3054
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3055
0
      op &= UINT64_C(31);
3056
0
      op <<= 6;
3057
0
      Value |= op;
3058
0
      break;
3059
0
    }
3060
0
    case Mips::LBE:
3061
0
    case Mips::LBuE:
3062
0
    case Mips::LHE:
3063
0
    case Mips::LHuE:
3064
0
    case Mips::LLE:
3065
0
    case Mips::LWE:
3066
0
    case Mips::LWLE:
3067
0
    case Mips::LWRE:
3068
0
    case Mips::SBE:
3069
0
    case Mips::SHE:
3070
0
    case Mips::SWE:
3071
0
    case Mips::SWLE:
3072
0
    case Mips::SWRE: {
3073
      // op: addr
3074
0
      op = getMemEncoding(MI, 1, Fixups, STI);
3075
0
      Value |= (op & UINT64_C(2031616)) << 5;
3076
0
      Value |= (op & UINT64_C(511)) << 7;
3077
      // op: rt
3078
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3079
0
      op &= UINT64_C(31);
3080
0
      op <<= 16;
3081
0
      Value |= op;
3082
0
      break;
3083
0
    }
3084
0
    case Mips::SCE: {
3085
      // op: addr
3086
0
      op = getMemEncoding(MI, 2, Fixups, STI);
3087
0
      Value |= (op & UINT64_C(2031616)) << 5;
3088
0
      Value |= (op & UINT64_C(511)) << 7;
3089
      // op: rt
3090
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3091
0
      op &= UINT64_C(31);
3092
0
      op <<= 16;
3093
0
      Value |= op;
3094
0
      break;
3095
0
    }
3096
0
    case Mips::LD_H:
3097
0
    case Mips::ST_H: {
3098
      // op: addr
3099
0
      op = getMemEncoding<1>(MI, 1, Fixups, STI);
3100
0
      Value |= (op & UINT64_C(1023)) << 16;
3101
0
      Value |= (op & UINT64_C(2031616)) >> 5;
3102
      // op: wd
3103
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3104
0
      op &= UINT64_C(31);
3105
0
      op <<= 6;
3106
0
      Value |= op;
3107
0
      break;
3108
0
    }
3109
0
    case Mips::LD_W:
3110
0
    case Mips::ST_W: {
3111
      // op: addr
3112
0
      op = getMemEncoding<2>(MI, 1, Fixups, STI);
3113
0
      Value |= (op & UINT64_C(1023)) << 16;
3114
0
      Value |= (op & UINT64_C(2031616)) >> 5;
3115
      // op: wd
3116
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3117
0
      op &= UINT64_C(31);
3118
0
      op <<= 6;
3119
0
      Value |= op;
3120
0
      break;
3121
0
    }
3122
0
    case Mips::LD_D:
3123
0
    case Mips::ST_D: {
3124
      // op: addr
3125
0
      op = getMemEncoding<3>(MI, 1, Fixups, STI);
3126
0
      Value |= (op & UINT64_C(1023)) << 16;
3127
0
      Value |= (op & UINT64_C(2031616)) >> 5;
3128
      // op: wd
3129
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3130
0
      op &= UINT64_C(31);
3131
0
      op <<= 6;
3132
0
      Value |= op;
3133
0
      break;
3134
0
    }
3135
0
    case Mips::CACHE_MM:
3136
0
    case Mips::CACHE_MMR6:
3137
0
    case Mips::PREF_MM:
3138
0
    case Mips::PREF_MMR6: {
3139
      // op: addr
3140
0
      op = getMemEncodingMMImm12(MI, 0, Fixups, STI);
3141
0
      Value |= (op & UINT64_C(2031616));
3142
0
      Value |= (op & UINT64_C(4095));
3143
      // op: hint
3144
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3145
0
      op &= UINT64_C(31);
3146
0
      op <<= 21;
3147
0
      Value |= op;
3148
0
      break;
3149
0
    }
3150
0
    case Mips::SYNCI_MM:
3151
0
    case Mips::SYNCI_MMR6: {
3152
      // op: addr
3153
0
      op = getMemEncodingMMImm16(MI, 0, Fixups, STI);
3154
0
      op &= UINT64_C(2097151);
3155
0
      Value |= op;
3156
0
      break;
3157
0
    }
3158
0
    case Mips::LBU_MMR6:
3159
0
    case Mips::LB_MMR6: {
3160
      // op: addr
3161
0
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
3162
0
      op &= UINT64_C(2097151);
3163
0
      Value |= op;
3164
      // op: rt
3165
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3166
0
      op &= UINT64_C(31);
3167
0
      op <<= 21;
3168
0
      Value |= op;
3169
0
      break;
3170
0
    }
3171
0
    case Mips::CACHEE_MM:
3172
0
    case Mips::PREFE_MM: {
3173
      // op: addr
3174
0
      op = getMemEncodingMMImm9(MI, 0, Fixups, STI);
3175
0
      Value |= (op & UINT64_C(2031616));
3176
0
      Value |= (op & UINT64_C(511));
3177
      // op: hint
3178
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3179
0
      op &= UINT64_C(31);
3180
0
      op <<= 21;
3181
0
      Value |= op;
3182
0
      break;
3183
0
    }
3184
0
    case Mips::HYPCALL: {
3185
      // op: code_
3186
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3187
0
      op &= UINT64_C(1023);
3188
0
      op <<= 11;
3189
0
      Value |= op;
3190
0
      break;
3191
0
    }
3192
0
    case Mips::HYPCALL_MM:
3193
0
    case Mips::SDBBP_MM:
3194
0
    case Mips::SDBBP_MMR6:
3195
0
    case Mips::SYSCALL_MM:
3196
0
    case Mips::WAIT_MM:
3197
0
    case Mips::WAIT_MMR6: {
3198
      // op: code_
3199
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3200
0
      op &= UINT64_C(1023);
3201
0
      op <<= 16;
3202
0
      Value |= op;
3203
0
      break;
3204
0
    }
3205
0
    case Mips::SDBBP:
3206
0
    case Mips::SDBBP_R6:
3207
0
    case Mips::SYSCALL: {
3208
      // op: code_
3209
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3210
0
      op &= UINT64_C(1048575);
3211
0
      op <<= 6;
3212
0
      Value |= op;
3213
0
      break;
3214
0
    }
3215
0
    case Mips::BREAK16_MM:
3216
0
    case Mips::SDBBP16_MM: {
3217
      // op: code_
3218
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3219
0
      op &= UINT64_C(15);
3220
0
      Value |= op;
3221
0
      break;
3222
0
    }
3223
0
    case Mips::BREAK16_MMR6:
3224
0
    case Mips::SDBBP16_MMR6: {
3225
      // op: code_
3226
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3227
0
      op &= UINT64_C(15);
3228
0
      op <<= 6;
3229
0
      Value |= op;
3230
0
      break;
3231
0
    }
3232
0
    case Mips::SIGRIE: {
3233
      // op: code_
3234
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3235
0
      op &= UINT64_C(65535);
3236
0
      Value |= op;
3237
0
      break;
3238
0
    }
3239
0
    case Mips::SIGRIE_MMR6: {
3240
      // op: code_
3241
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3242
0
      op &= UINT64_C(65535);
3243
0
      op <<= 6;
3244
0
      Value |= op;
3245
0
      break;
3246
0
    }
3247
0
    case Mips::BREAK:
3248
0
    case Mips::BREAK_MM:
3249
0
    case Mips::BREAK_MMR6: {
3250
      // op: code_1
3251
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3252
0
      op &= UINT64_C(1023);
3253
0
      op <<= 16;
3254
0
      Value |= op;
3255
      // op: code_2
3256
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3257
0
      op &= UINT64_C(1023);
3258
0
      op <<= 6;
3259
0
      Value |= op;
3260
0
      break;
3261
0
    }
3262
0
    case Mips::BC2EQZ:
3263
0
    case Mips::BC2NEZ: {
3264
      // op: ct
3265
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3266
0
      op &= UINT64_C(31);
3267
0
      op <<= 16;
3268
0
      Value |= op;
3269
      // op: offset
3270
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3271
0
      op &= UINT64_C(65535);
3272
0
      Value |= op;
3273
0
      break;
3274
0
    }
3275
0
    case Mips::BC1F:
3276
0
    case Mips::BC1FL:
3277
0
    case Mips::BC1T:
3278
0
    case Mips::BC1TL: {
3279
      // op: fcc
3280
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3281
0
      op &= UINT64_C(7);
3282
0
      op <<= 18;
3283
0
      Value |= op;
3284
      // op: offset
3285
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3286
0
      op &= UINT64_C(65535);
3287
0
      Value |= op;
3288
0
      break;
3289
0
    }
3290
0
    case Mips::BC1F_MM:
3291
0
    case Mips::BC1T_MM: {
3292
      // op: fcc
3293
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3294
0
      op &= UINT64_C(7);
3295
0
      op <<= 18;
3296
0
      Value |= op;
3297
      // op: offset
3298
0
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
3299
0
      op &= UINT64_C(65535);
3300
0
      Value |= op;
3301
0
      break;
3302
0
    }
3303
0
    case Mips::LUXC1_MM:
3304
0
    case Mips::LWXC1_MM: {
3305
      // op: fd
3306
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3307
0
      op &= UINT64_C(31);
3308
0
      op <<= 11;
3309
0
      Value |= op;
3310
      // op: base
3311
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3312
0
      op &= UINT64_C(31);
3313
0
      op <<= 16;
3314
0
      Value |= op;
3315
      // op: index
3316
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3317
0
      op &= UINT64_C(31);
3318
0
      op <<= 21;
3319
0
      Value |= op;
3320
0
      break;
3321
0
    }
3322
0
    case Mips::MOVN_I_D32_MM:
3323
0
    case Mips::MOVN_I_S_MM:
3324
0
    case Mips::MOVZ_I_D32_MM:
3325
0
    case Mips::MOVZ_I_S_MM: {
3326
      // op: fd
3327
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3328
0
      op &= UINT64_C(31);
3329
0
      op <<= 11;
3330
0
      Value |= op;
3331
      // op: fs
3332
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3333
0
      op &= UINT64_C(31);
3334
0
      op <<= 16;
3335
0
      Value |= op;
3336
      // op: rt
3337
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3338
0
      op &= UINT64_C(31);
3339
0
      op <<= 21;
3340
0
      Value |= op;
3341
0
      break;
3342
0
    }
3343
0
    case Mips::CEIL_W_MM:
3344
0
    case Mips::CEIL_W_S_MM:
3345
0
    case Mips::CVT_D32_S_MM:
3346
0
    case Mips::CVT_D32_W_MM:
3347
0
    case Mips::CVT_D64_S_MM:
3348
0
    case Mips::CVT_D64_W_MM:
3349
0
    case Mips::CVT_L_D64_MM:
3350
0
    case Mips::CVT_L_S_MM:
3351
0
    case Mips::CVT_S_D32_MM:
3352
0
    case Mips::CVT_S_D64_MM:
3353
0
    case Mips::CVT_S_W_MM:
3354
0
    case Mips::CVT_W_D32_MM:
3355
0
    case Mips::CVT_W_D64_MM:
3356
0
    case Mips::CVT_W_S_MM:
3357
0
    case Mips::FABS_D32_MM:
3358
0
    case Mips::FABS_D64_MM:
3359
0
    case Mips::FABS_S_MM:
3360
0
    case Mips::FLOOR_W_MM:
3361
0
    case Mips::FLOOR_W_S_MM:
3362
0
    case Mips::FMOV_D32_MM:
3363
0
    case Mips::FMOV_D64_MM:
3364
0
    case Mips::FMOV_S_MM:
3365
0
    case Mips::FNEG_D32_MM:
3366
0
    case Mips::FNEG_D64_MM:
3367
0
    case Mips::FNEG_S_MM:
3368
0
    case Mips::FSQRT_D32_MM:
3369
0
    case Mips::FSQRT_D64_MM:
3370
0
    case Mips::FSQRT_S_MM:
3371
0
    case Mips::RECIP_D32_MM:
3372
0
    case Mips::RECIP_D64_MM:
3373
0
    case Mips::RECIP_S_MM:
3374
0
    case Mips::ROUND_W_MM:
3375
0
    case Mips::ROUND_W_S_MM:
3376
0
    case Mips::RSQRT_D32_MM:
3377
0
    case Mips::RSQRT_D64_MM:
3378
0
    case Mips::RSQRT_S_MM:
3379
0
    case Mips::TRUNC_W_MM:
3380
0
    case Mips::TRUNC_W_S_MM: {
3381
      // op: fd
3382
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3383
0
      op &= UINT64_C(31);
3384
0
      op <<= 21;
3385
0
      Value |= op;
3386
      // op: fs
3387
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3388
0
      op &= UINT64_C(31);
3389
0
      op <<= 16;
3390
0
      Value |= op;
3391
0
      break;
3392
0
    }
3393
0
    case Mips::MOVF_D32_MM:
3394
0
    case Mips::MOVF_S_MM:
3395
0
    case Mips::MOVT_D32_MM:
3396
0
    case Mips::MOVT_S_MM: {
3397
      // op: fd
3398
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3399
0
      op &= UINT64_C(31);
3400
0
      op <<= 21;
3401
0
      Value |= op;
3402
      // op: fs
3403
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3404
0
      op &= UINT64_C(31);
3405
0
      op <<= 16;
3406
0
      Value |= op;
3407
      // op: fcc
3408
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3409
0
      op &= UINT64_C(7);
3410
0
      op <<= 13;
3411
0
      Value |= op;
3412
0
      break;
3413
0
    }
3414
0
    case Mips::LDXC1:
3415
0
    case Mips::LDXC164:
3416
0
    case Mips::LUXC1:
3417
0
    case Mips::LUXC164:
3418
0
    case Mips::LWXC1: {
3419
      // op: fd
3420
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3421
0
      op &= UINT64_C(31);
3422
0
      op <<= 6;
3423
0
      Value |= op;
3424
      // op: base
3425
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3426
0
      op &= UINT64_C(31);
3427
0
      op <<= 21;
3428
0
      Value |= op;
3429
      // op: index
3430
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3431
0
      op &= UINT64_C(31);
3432
0
      op <<= 16;
3433
0
      Value |= op;
3434
0
      break;
3435
0
    }
3436
0
    case Mips::MADD_D32:
3437
0
    case Mips::MADD_D64:
3438
0
    case Mips::MADD_S:
3439
0
    case Mips::MSUB_D32:
3440
0
    case Mips::MSUB_D64:
3441
0
    case Mips::MSUB_S:
3442
0
    case Mips::NMADD_D32:
3443
0
    case Mips::NMADD_D64:
3444
0
    case Mips::NMADD_S:
3445
0
    case Mips::NMSUB_D32:
3446
0
    case Mips::NMSUB_D64:
3447
0
    case Mips::NMSUB_S: {
3448
      // op: fd
3449
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3450
0
      op &= UINT64_C(31);
3451
0
      op <<= 6;
3452
0
      Value |= op;
3453
      // op: fr
3454
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3455
0
      op &= UINT64_C(31);
3456
0
      op <<= 21;
3457
0
      Value |= op;
3458
      // op: fs
3459
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3460
0
      op &= UINT64_C(31);
3461
0
      op <<= 11;
3462
0
      Value |= op;
3463
      // op: ft
3464
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
3465
0
      op &= UINT64_C(31);
3466
0
      op <<= 16;
3467
0
      Value |= op;
3468
0
      break;
3469
0
    }
3470
0
    case Mips::CEIL_L_D64:
3471
0
    case Mips::CEIL_L_S:
3472
0
    case Mips::CEIL_W_D32:
3473
0
    case Mips::CEIL_W_D64:
3474
0
    case Mips::CEIL_W_S:
3475
0
    case Mips::CVT_D32_S:
3476
0
    case Mips::CVT_D32_W:
3477
0
    case Mips::CVT_D64_L:
3478
0
    case Mips::CVT_D64_S:
3479
0
    case Mips::CVT_D64_W:
3480
0
    case Mips::CVT_L_D64:
3481
0
    case Mips::CVT_L_S:
3482
0
    case Mips::CVT_PS_PW64:
3483
0
    case Mips::CVT_PW_PS64:
3484
0
    case Mips::CVT_S_D32:
3485
0
    case Mips::CVT_S_D64:
3486
0
    case Mips::CVT_S_L:
3487
0
    case Mips::CVT_S_PL64:
3488
0
    case Mips::CVT_S_PU64:
3489
0
    case Mips::CVT_S_W:
3490
0
    case Mips::CVT_W_D32:
3491
0
    case Mips::CVT_W_D64:
3492
0
    case Mips::CVT_W_S:
3493
0
    case Mips::FABS_D32:
3494
0
    case Mips::FABS_D64:
3495
0
    case Mips::FABS_S:
3496
0
    case Mips::FLOOR_L_D64:
3497
0
    case Mips::FLOOR_L_S:
3498
0
    case Mips::FLOOR_W_D32:
3499
0
    case Mips::FLOOR_W_D64:
3500
0
    case Mips::FLOOR_W_S:
3501
0
    case Mips::FMOV_D32:
3502
0
    case Mips::FMOV_D64:
3503
0
    case Mips::FMOV_S:
3504
0
    case Mips::FNEG_D32:
3505
0
    case Mips::FNEG_D64:
3506
0
    case Mips::FNEG_S:
3507
0
    case Mips::FSQRT_D32:
3508
0
    case Mips::FSQRT_D64:
3509
0
    case Mips::FSQRT_S:
3510
0
    case Mips::RECIP_D32:
3511
0
    case Mips::RECIP_D64:
3512
0
    case Mips::RECIP_S:
3513
0
    case Mips::ROUND_L_D64:
3514
0
    case Mips::ROUND_L_S:
3515
0
    case Mips::ROUND_W_D32:
3516
0
    case Mips::ROUND_W_D64:
3517
0
    case Mips::ROUND_W_S:
3518
0
    case Mips::RSQRT_D32:
3519
0
    case Mips::RSQRT_D64:
3520
0
    case Mips::RSQRT_S:
3521
0
    case Mips::TRUNC_L_D64:
3522
0
    case Mips::TRUNC_L_S:
3523
0
    case Mips::TRUNC_W_D32:
3524
0
    case Mips::TRUNC_W_D64:
3525
0
    case Mips::TRUNC_W_S: {
3526
      // op: fd
3527
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3528
0
      op &= UINT64_C(31);
3529
0
      op <<= 6;
3530
0
      Value |= op;
3531
      // op: fs
3532
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3533
0
      op &= UINT64_C(31);
3534
0
      op <<= 11;
3535
0
      Value |= op;
3536
0
      break;
3537
0
    }
3538
0
    case Mips::MOVF_D32:
3539
0
    case Mips::MOVF_D64:
3540
0
    case Mips::MOVF_S:
3541
0
    case Mips::MOVT_D32:
3542
0
    case Mips::MOVT_D64:
3543
0
    case Mips::MOVT_S: {
3544
      // op: fd
3545
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3546
0
      op &= UINT64_C(31);
3547
0
      op <<= 6;
3548
0
      Value |= op;
3549
      // op: fs
3550
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3551
0
      op &= UINT64_C(31);
3552
0
      op <<= 11;
3553
0
      Value |= op;
3554
      // op: fcc
3555
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3556
0
      op &= UINT64_C(7);
3557
0
      op <<= 18;
3558
0
      Value |= op;
3559
0
      break;
3560
0
    }
3561
0
    case Mips::ADDR_PS64:
3562
0
    case Mips::CMP_EQ_D:
3563
0
    case Mips::CMP_EQ_S:
3564
0
    case Mips::CMP_F_D:
3565
0
    case Mips::CMP_F_S:
3566
0
    case Mips::CMP_LE_D:
3567
0
    case Mips::CMP_LE_S:
3568
0
    case Mips::CMP_LT_D:
3569
0
    case Mips::CMP_LT_S:
3570
0
    case Mips::CMP_SAF_D:
3571
0
    case Mips::CMP_SAF_S:
3572
0
    case Mips::CMP_SEQ_D:
3573
0
    case Mips::CMP_SEQ_S:
3574
0
    case Mips::CMP_SLE_D:
3575
0
    case Mips::CMP_SLE_S:
3576
0
    case Mips::CMP_SLT_D:
3577
0
    case Mips::CMP_SLT_S:
3578
0
    case Mips::CMP_SUEQ_D:
3579
0
    case Mips::CMP_SUEQ_S:
3580
0
    case Mips::CMP_SULE_D:
3581
0
    case Mips::CMP_SULE_S:
3582
0
    case Mips::CMP_SULT_D:
3583
0
    case Mips::CMP_SULT_S:
3584
0
    case Mips::CMP_SUN_D:
3585
0
    case Mips::CMP_SUN_S:
3586
0
    case Mips::CMP_UEQ_D:
3587
0
    case Mips::CMP_UEQ_S:
3588
0
    case Mips::CMP_ULE_D:
3589
0
    case Mips::CMP_ULE_S:
3590
0
    case Mips::CMP_ULT_D:
3591
0
    case Mips::CMP_ULT_S:
3592
0
    case Mips::CMP_UN_D:
3593
0
    case Mips::CMP_UN_S:
3594
0
    case Mips::CVT_PS_S64:
3595
0
    case Mips::FADD_D32:
3596
0
    case Mips::FADD_D64:
3597
0
    case Mips::FADD_PS64:
3598
0
    case Mips::FADD_S:
3599
0
    case Mips::FDIV_D32:
3600
0
    case Mips::FDIV_D64:
3601
0
    case Mips::FDIV_S:
3602
0
    case Mips::FMUL_D32:
3603
0
    case Mips::FMUL_D64:
3604
0
    case Mips::FMUL_PS64:
3605
0
    case Mips::FMUL_S:
3606
0
    case Mips::FSUB_D32:
3607
0
    case Mips::FSUB_D64:
3608
0
    case Mips::FSUB_PS64:
3609
0
    case Mips::FSUB_S:
3610
0
    case Mips::MULR_PS64:
3611
0
    case Mips::PLL_PS64:
3612
0
    case Mips::PLU_PS64:
3613
0
    case Mips::PUL_PS64:
3614
0
    case Mips::PUU_PS64: {
3615
      // op: fd
3616
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3617
0
      op &= UINT64_C(31);
3618
0
      op <<= 6;
3619
0
      Value |= op;
3620
      // op: fs
3621
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3622
0
      op &= UINT64_C(31);
3623
0
      op <<= 11;
3624
0
      Value |= op;
3625
      // op: ft
3626
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3627
0
      op &= UINT64_C(31);
3628
0
      op <<= 16;
3629
0
      Value |= op;
3630
0
      break;
3631
0
    }
3632
0
    case Mips::MOVN_I64_D64:
3633
0
    case Mips::MOVN_I64_S:
3634
0
    case Mips::MOVN_I_D32:
3635
0
    case Mips::MOVN_I_D64:
3636
0
    case Mips::MOVN_I_S:
3637
0
    case Mips::MOVZ_I64_D64:
3638
0
    case Mips::MOVZ_I64_S:
3639
0
    case Mips::MOVZ_I_D32:
3640
0
    case Mips::MOVZ_I_D64:
3641
0
    case Mips::MOVZ_I_S: {
3642
      // op: fd
3643
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3644
0
      op &= UINT64_C(31);
3645
0
      op <<= 6;
3646
0
      Value |= op;
3647
      // op: fs
3648
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3649
0
      op &= UINT64_C(31);
3650
0
      op <<= 11;
3651
0
      Value |= op;
3652
      // op: rt
3653
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3654
0
      op &= UINT64_C(31);
3655
0
      op <<= 16;
3656
0
      Value |= op;
3657
0
      break;
3658
0
    }
3659
0
    case Mips::SUXC1_MM:
3660
0
    case Mips::SWXC1_MM: {
3661
      // op: fs
3662
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3663
0
      op &= UINT64_C(31);
3664
0
      op <<= 11;
3665
0
      Value |= op;
3666
      // op: base
3667
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3668
0
      op &= UINT64_C(31);
3669
0
      op <<= 16;
3670
0
      Value |= op;
3671
      // op: index
3672
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3673
0
      op &= UINT64_C(31);
3674
0
      op <<= 21;
3675
0
      Value |= op;
3676
0
      break;
3677
0
    }
3678
0
    case Mips::SDXC1:
3679
0
    case Mips::SDXC164:
3680
0
    case Mips::SUXC1:
3681
0
    case Mips::SUXC164:
3682
0
    case Mips::SWXC1: {
3683
      // op: fs
3684
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3685
0
      op &= UINT64_C(31);
3686
0
      op <<= 11;
3687
0
      Value |= op;
3688
      // op: base
3689
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3690
0
      op &= UINT64_C(31);
3691
0
      op <<= 21;
3692
0
      Value |= op;
3693
      // op: index
3694
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3695
0
      op &= UINT64_C(31);
3696
0
      op <<= 16;
3697
0
      Value |= op;
3698
0
      break;
3699
0
    }
3700
0
    case Mips::FCMP_D32:
3701
0
    case Mips::FCMP_D64:
3702
0
    case Mips::FCMP_S32: {
3703
      // op: fs
3704
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3705
0
      op &= UINT64_C(31);
3706
0
      op <<= 11;
3707
0
      Value |= op;
3708
      // op: ft
3709
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3710
0
      op &= UINT64_C(31);
3711
0
      op <<= 16;
3712
0
      Value |= op;
3713
      // op: cond
3714
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3715
0
      op &= UINT64_C(15);
3716
0
      Value |= op;
3717
0
      break;
3718
0
    }
3719
0
    case Mips::FCMP_D32_MM:
3720
0
    case Mips::FCMP_S32_MM: {
3721
      // op: fs
3722
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3723
0
      op &= UINT64_C(31);
3724
0
      op <<= 16;
3725
0
      Value |= op;
3726
      // op: ft
3727
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3728
0
      op &= UINT64_C(31);
3729
0
      op <<= 21;
3730
0
      Value |= op;
3731
      // op: cond
3732
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3733
0
      op &= UINT64_C(15);
3734
0
      op <<= 6;
3735
0
      Value |= op;
3736
0
      break;
3737
0
    }
3738
0
    case Mips::CLASS_D:
3739
0
    case Mips::CLASS_S:
3740
0
    case Mips::RINT_D:
3741
0
    case Mips::RINT_S: {
3742
      // op: fs
3743
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3744
0
      op &= UINT64_C(31);
3745
0
      op <<= 11;
3746
0
      Value |= op;
3747
      // op: fd
3748
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3749
0
      op &= UINT64_C(31);
3750
0
      op <<= 6;
3751
0
      Value |= op;
3752
0
      break;
3753
0
    }
3754
0
    case Mips::C_EQ_D32:
3755
0
    case Mips::C_EQ_D64:
3756
0
    case Mips::C_EQ_S:
3757
0
    case Mips::C_F_D32:
3758
0
    case Mips::C_F_D64:
3759
0
    case Mips::C_F_S:
3760
0
    case Mips::C_LE_D32:
3761
0
    case Mips::C_LE_D64:
3762
0
    case Mips::C_LE_S:
3763
0
    case Mips::C_LT_D32:
3764
0
    case Mips::C_LT_D64:
3765
0
    case Mips::C_LT_S:
3766
0
    case Mips::C_NGE_D32:
3767
0
    case Mips::C_NGE_D64:
3768
0
    case Mips::C_NGE_S:
3769
0
    case Mips::C_NGLE_D32:
3770
0
    case Mips::C_NGLE_D64:
3771
0
    case Mips::C_NGLE_S:
3772
0
    case Mips::C_NGL_D32:
3773
0
    case Mips::C_NGL_D64:
3774
0
    case Mips::C_NGL_S:
3775
0
    case Mips::C_NGT_D32:
3776
0
    case Mips::C_NGT_D64:
3777
0
    case Mips::C_NGT_S:
3778
0
    case Mips::C_OLE_D32:
3779
0
    case Mips::C_OLE_D64:
3780
0
    case Mips::C_OLE_S:
3781
0
    case Mips::C_OLT_D32:
3782
0
    case Mips::C_OLT_D64:
3783
0
    case Mips::C_OLT_S:
3784
0
    case Mips::C_SEQ_D32:
3785
0
    case Mips::C_SEQ_D64:
3786
0
    case Mips::C_SEQ_S:
3787
0
    case Mips::C_SF_D32:
3788
0
    case Mips::C_SF_D64:
3789
0
    case Mips::C_SF_S:
3790
0
    case Mips::C_UEQ_D32:
3791
0
    case Mips::C_UEQ_D64:
3792
0
    case Mips::C_UEQ_S:
3793
0
    case Mips::C_ULE_D32:
3794
0
    case Mips::C_ULE_D64:
3795
0
    case Mips::C_ULE_S:
3796
0
    case Mips::C_ULT_D32:
3797
0
    case Mips::C_ULT_D64:
3798
0
    case Mips::C_ULT_S:
3799
0
    case Mips::C_UN_D32:
3800
0
    case Mips::C_UN_D64:
3801
0
    case Mips::C_UN_S: {
3802
      // op: fs
3803
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3804
0
      op &= UINT64_C(31);
3805
0
      op <<= 11;
3806
0
      Value |= op;
3807
      // op: ft
3808
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3809
0
      op &= UINT64_C(31);
3810
0
      op <<= 16;
3811
0
      Value |= op;
3812
      // op: fcc
3813
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3814
0
      op &= UINT64_C(7);
3815
0
      op <<= 8;
3816
0
      Value |= op;
3817
0
      break;
3818
0
    }
3819
0
    case Mips::C_EQ_D32_MM:
3820
0
    case Mips::C_EQ_D64_MM:
3821
0
    case Mips::C_EQ_S_MM:
3822
0
    case Mips::C_F_D32_MM:
3823
0
    case Mips::C_F_D64_MM:
3824
0
    case Mips::C_F_S_MM:
3825
0
    case Mips::C_LE_D32_MM:
3826
0
    case Mips::C_LE_D64_MM:
3827
0
    case Mips::C_LE_S_MM:
3828
0
    case Mips::C_LT_D32_MM:
3829
0
    case Mips::C_LT_D64_MM:
3830
0
    case Mips::C_LT_S_MM:
3831
0
    case Mips::C_NGE_D32_MM:
3832
0
    case Mips::C_NGE_D64_MM:
3833
0
    case Mips::C_NGE_S_MM:
3834
0
    case Mips::C_NGLE_D32_MM:
3835
0
    case Mips::C_NGLE_D64_MM:
3836
0
    case Mips::C_NGLE_S_MM:
3837
0
    case Mips::C_NGL_D32_MM:
3838
0
    case Mips::C_NGL_D64_MM:
3839
0
    case Mips::C_NGL_S_MM:
3840
0
    case Mips::C_NGT_D32_MM:
3841
0
    case Mips::C_NGT_D64_MM:
3842
0
    case Mips::C_NGT_S_MM:
3843
0
    case Mips::C_OLE_D32_MM:
3844
0
    case Mips::C_OLE_D64_MM:
3845
0
    case Mips::C_OLE_S_MM:
3846
0
    case Mips::C_OLT_D32_MM:
3847
0
    case Mips::C_OLT_D64_MM:
3848
0
    case Mips::C_OLT_S_MM:
3849
0
    case Mips::C_SEQ_D32_MM:
3850
0
    case Mips::C_SEQ_D64_MM:
3851
0
    case Mips::C_SEQ_S_MM:
3852
0
    case Mips::C_SF_D32_MM:
3853
0
    case Mips::C_SF_D64_MM:
3854
0
    case Mips::C_SF_S_MM:
3855
0
    case Mips::C_UEQ_D32_MM:
3856
0
    case Mips::C_UEQ_D64_MM:
3857
0
    case Mips::C_UEQ_S_MM:
3858
0
    case Mips::C_ULE_D32_MM:
3859
0
    case Mips::C_ULE_D64_MM:
3860
0
    case Mips::C_ULE_S_MM:
3861
0
    case Mips::C_ULT_D32_MM:
3862
0
    case Mips::C_ULT_D64_MM:
3863
0
    case Mips::C_ULT_S_MM:
3864
0
    case Mips::C_UN_D32_MM:
3865
0
    case Mips::C_UN_D64_MM:
3866
0
    case Mips::C_UN_S_MM: {
3867
      // op: fs
3868
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3869
0
      op &= UINT64_C(31);
3870
0
      op <<= 16;
3871
0
      Value |= op;
3872
      // op: ft
3873
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3874
0
      op &= UINT64_C(31);
3875
0
      op <<= 21;
3876
0
      Value |= op;
3877
      // op: fcc
3878
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3879
0
      op &= UINT64_C(7);
3880
0
      op <<= 13;
3881
0
      Value |= op;
3882
0
      break;
3883
0
    }
3884
0
    case Mips::CLASS_D_MMR6:
3885
0
    case Mips::CLASS_S_MMR6:
3886
0
    case Mips::RINT_D_MMR6:
3887
0
    case Mips::RINT_S_MMR6: {
3888
      // op: fs
3889
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3890
0
      op &= UINT64_C(31);
3891
0
      op <<= 21;
3892
0
      Value |= op;
3893
      // op: fd
3894
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3895
0
      op &= UINT64_C(31);
3896
0
      op <<= 16;
3897
0
      Value |= op;
3898
0
      break;
3899
0
    }
3900
0
    case Mips::BC1EQZ:
3901
0
    case Mips::BC1NEZ: {
3902
      // op: ft
3903
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3904
0
      op &= UINT64_C(31);
3905
0
      op <<= 16;
3906
0
      Value |= op;
3907
      // op: offset
3908
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
3909
0
      op &= UINT64_C(65535);
3910
0
      Value |= op;
3911
0
      break;
3912
0
    }
3913
0
    case Mips::LDC1_D64_MMR6:
3914
0
    case Mips::SDC1_D64_MMR6: {
3915
      // op: ft
3916
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3917
0
      op &= UINT64_C(31);
3918
0
      op <<= 21;
3919
0
      Value |= op;
3920
      // op: addr
3921
0
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
3922
0
      op &= UINT64_C(2097151);
3923
0
      Value |= op;
3924
0
      break;
3925
0
    }
3926
0
    case Mips::CEIL_L_D_MMR6:
3927
0
    case Mips::CEIL_L_S_MMR6:
3928
0
    case Mips::CEIL_W_D_MMR6:
3929
0
    case Mips::CEIL_W_S_MMR6:
3930
0
    case Mips::CVT_D_L_MMR6:
3931
0
    case Mips::CVT_L_D_MMR6:
3932
0
    case Mips::CVT_L_S_MMR6:
3933
0
    case Mips::CVT_S_L_MMR6:
3934
0
    case Mips::CVT_S_W_MMR6:
3935
0
    case Mips::CVT_W_S_MMR6:
3936
0
    case Mips::FLOOR_L_D_MMR6:
3937
0
    case Mips::FLOOR_L_S_MMR6:
3938
0
    case Mips::FLOOR_W_D_MMR6:
3939
0
    case Mips::FLOOR_W_S_MMR6:
3940
0
    case Mips::FMOV_D_MMR6:
3941
0
    case Mips::FMOV_S_MMR6:
3942
0
    case Mips::FNEG_S_MMR6:
3943
0
    case Mips::ROUND_L_D_MMR6:
3944
0
    case Mips::ROUND_L_S_MMR6:
3945
0
    case Mips::ROUND_W_D_MMR6:
3946
0
    case Mips::ROUND_W_S_MMR6:
3947
0
    case Mips::TRUNC_L_D_MMR6:
3948
0
    case Mips::TRUNC_L_S_MMR6:
3949
0
    case Mips::TRUNC_W_D_MMR6:
3950
0
    case Mips::TRUNC_W_S_MMR6: {
3951
      // op: ft
3952
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3953
0
      op &= UINT64_C(31);
3954
0
      op <<= 21;
3955
0
      Value |= op;
3956
      // op: fs
3957
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3958
0
      op &= UINT64_C(31);
3959
0
      op <<= 16;
3960
0
      Value |= op;
3961
0
      break;
3962
0
    }
3963
0
    case Mips::FADD_S_MMR6:
3964
0
    case Mips::FDIV_S_MMR6:
3965
0
    case Mips::FMUL_S_MMR6:
3966
0
    case Mips::FSUB_S_MMR6: {
3967
      // op: ft
3968
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3969
0
      op &= UINT64_C(31);
3970
0
      op <<= 21;
3971
0
      Value |= op;
3972
      // op: fs
3973
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3974
0
      op &= UINT64_C(31);
3975
0
      op <<= 16;
3976
0
      Value |= op;
3977
      // op: fd
3978
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3979
0
      op &= UINT64_C(31);
3980
0
      op <<= 11;
3981
0
      Value |= op;
3982
0
      break;
3983
0
    }
3984
0
    case Mips::MAXA_D:
3985
0
    case Mips::MAXA_S:
3986
0
    case Mips::MAX_D:
3987
0
    case Mips::MAX_S:
3988
0
    case Mips::MINA_D:
3989
0
    case Mips::MINA_S:
3990
0
    case Mips::MIN_D:
3991
0
    case Mips::MIN_S:
3992
0
    case Mips::SELEQZ_D:
3993
0
    case Mips::SELEQZ_S:
3994
0
    case Mips::SELNEZ_D:
3995
0
    case Mips::SELNEZ_S: {
3996
      // op: ft
3997
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3998
0
      op &= UINT64_C(31);
3999
0
      op <<= 16;
4000
0
      Value |= op;
4001
      // op: fs
4002
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4003
0
      op &= UINT64_C(31);
4004
0
      op <<= 11;
4005
0
      Value |= op;
4006
      // op: fd
4007
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4008
0
      op &= UINT64_C(31);
4009
0
      op <<= 6;
4010
0
      Value |= op;
4011
0
      break;
4012
0
    }
4013
0
    case Mips::CMP_AF_D_MMR6:
4014
0
    case Mips::CMP_AF_S_MMR6:
4015
0
    case Mips::CMP_EQ_D_MMR6:
4016
0
    case Mips::CMP_EQ_S_MMR6:
4017
0
    case Mips::CMP_LE_D_MMR6:
4018
0
    case Mips::CMP_LE_S_MMR6:
4019
0
    case Mips::CMP_LT_D_MMR6:
4020
0
    case Mips::CMP_LT_S_MMR6:
4021
0
    case Mips::CMP_SAF_D_MMR6:
4022
0
    case Mips::CMP_SAF_S_MMR6:
4023
0
    case Mips::CMP_SEQ_D_MMR6:
4024
0
    case Mips::CMP_SEQ_S_MMR6:
4025
0
    case Mips::CMP_SLE_D_MMR6:
4026
0
    case Mips::CMP_SLE_S_MMR6:
4027
0
    case Mips::CMP_SLT_D_MMR6:
4028
0
    case Mips::CMP_SLT_S_MMR6:
4029
0
    case Mips::CMP_SUEQ_D_MMR6:
4030
0
    case Mips::CMP_SUEQ_S_MMR6:
4031
0
    case Mips::CMP_SULE_D_MMR6:
4032
0
    case Mips::CMP_SULE_S_MMR6:
4033
0
    case Mips::CMP_SULT_D_MMR6:
4034
0
    case Mips::CMP_SULT_S_MMR6:
4035
0
    case Mips::CMP_SUN_D_MMR6:
4036
0
    case Mips::CMP_SUN_S_MMR6:
4037
0
    case Mips::CMP_UEQ_D_MMR6:
4038
0
    case Mips::CMP_UEQ_S_MMR6:
4039
0
    case Mips::CMP_ULE_D_MMR6:
4040
0
    case Mips::CMP_ULE_S_MMR6:
4041
0
    case Mips::CMP_ULT_D_MMR6:
4042
0
    case Mips::CMP_ULT_S_MMR6:
4043
0
    case Mips::CMP_UN_D_MMR6:
4044
0
    case Mips::CMP_UN_S_MMR6:
4045
0
    case Mips::FADD_D32_MM:
4046
0
    case Mips::FADD_D64_MM:
4047
0
    case Mips::FADD_S_MM:
4048
0
    case Mips::FDIV_D32_MM:
4049
0
    case Mips::FDIV_D64_MM:
4050
0
    case Mips::FDIV_S_MM:
4051
0
    case Mips::FMUL_D32_MM:
4052
0
    case Mips::FMUL_D64_MM:
4053
0
    case Mips::FMUL_S_MM:
4054
0
    case Mips::FSUB_D32_MM:
4055
0
    case Mips::FSUB_D64_MM:
4056
0
    case Mips::FSUB_S_MM:
4057
0
    case Mips::MAXA_D_MMR6:
4058
0
    case Mips::MAXA_S_MMR6:
4059
0
    case Mips::MAX_D_MMR6:
4060
0
    case Mips::MAX_S_MMR6:
4061
0
    case Mips::MINA_D_MMR6:
4062
0
    case Mips::MINA_S_MMR6:
4063
0
    case Mips::MIN_D_MMR6:
4064
0
    case Mips::MIN_S_MMR6:
4065
0
    case Mips::SELEQZ_D_MMR6:
4066
0
    case Mips::SELEQZ_S_MMR6:
4067
0
    case Mips::SELNEZ_D_MMR6:
4068
0
    case Mips::SELNEZ_S_MMR6: {
4069
      // op: ft
4070
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4071
0
      op &= UINT64_C(31);
4072
0
      op <<= 21;
4073
0
      Value |= op;
4074
      // op: fs
4075
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4076
0
      op &= UINT64_C(31);
4077
0
      op <<= 16;
4078
0
      Value |= op;
4079
      // op: fd
4080
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4081
0
      op &= UINT64_C(31);
4082
0
      op <<= 11;
4083
0
      Value |= op;
4084
0
      break;
4085
0
    }
4086
0
    case Mips::MADDF_D:
4087
0
    case Mips::MADDF_S:
4088
0
    case Mips::MSUBF_D:
4089
0
    case Mips::MSUBF_S:
4090
0
    case Mips::SEL_D:
4091
0
    case Mips::SEL_S: {
4092
      // op: ft
4093
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4094
0
      op &= UINT64_C(31);
4095
0
      op <<= 16;
4096
0
      Value |= op;
4097
      // op: fs
4098
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4099
0
      op &= UINT64_C(31);
4100
0
      op <<= 11;
4101
0
      Value |= op;
4102
      // op: fd
4103
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4104
0
      op &= UINT64_C(31);
4105
0
      op <<= 6;
4106
0
      Value |= op;
4107
0
      break;
4108
0
    }
4109
0
    case Mips::MADDF_D_MMR6:
4110
0
    case Mips::MADDF_S_MMR6:
4111
0
    case Mips::MSUBF_D_MMR6:
4112
0
    case Mips::MSUBF_S_MMR6:
4113
0
    case Mips::SEL_D_MMR6:
4114
0
    case Mips::SEL_S_MMR6: {
4115
      // op: ft
4116
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4117
0
      op &= UINT64_C(31);
4118
0
      op <<= 21;
4119
0
      Value |= op;
4120
      // op: fs
4121
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4122
0
      op &= UINT64_C(31);
4123
0
      op <<= 16;
4124
0
      Value |= op;
4125
      // op: fd
4126
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4127
0
      op &= UINT64_C(31);
4128
0
      op <<= 11;
4129
0
      Value |= op;
4130
0
      break;
4131
0
    }
4132
0
    case Mips::MADD_D32_MM:
4133
0
    case Mips::MADD_S_MM:
4134
0
    case Mips::MSUB_D32_MM:
4135
0
    case Mips::MSUB_S_MM:
4136
0
    case Mips::NMADD_D32_MM:
4137
0
    case Mips::NMADD_S_MM:
4138
0
    case Mips::NMSUB_D32_MM:
4139
0
    case Mips::NMSUB_S_MM: {
4140
      // op: ft
4141
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4142
0
      op &= UINT64_C(31);
4143
0
      op <<= 21;
4144
0
      Value |= op;
4145
      // op: fs
4146
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4147
0
      op &= UINT64_C(31);
4148
0
      op <<= 16;
4149
0
      Value |= op;
4150
      // op: fd
4151
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4152
0
      op &= UINT64_C(31);
4153
0
      op <<= 11;
4154
0
      Value |= op;
4155
      // op: fr
4156
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4157
0
      op &= UINT64_C(31);
4158
0
      op <<= 6;
4159
0
      Value |= op;
4160
0
      break;
4161
0
    }
4162
0
    case Mips::ADDVI_B:
4163
0
    case Mips::ADDVI_D:
4164
0
    case Mips::ADDVI_H:
4165
0
    case Mips::ADDVI_W:
4166
0
    case Mips::CEQI_B:
4167
0
    case Mips::CEQI_D:
4168
0
    case Mips::CEQI_H:
4169
0
    case Mips::CEQI_W:
4170
0
    case Mips::CLEI_S_B:
4171
0
    case Mips::CLEI_S_D:
4172
0
    case Mips::CLEI_S_H:
4173
0
    case Mips::CLEI_S_W:
4174
0
    case Mips::CLEI_U_B:
4175
0
    case Mips::CLEI_U_D:
4176
0
    case Mips::CLEI_U_H:
4177
0
    case Mips::CLEI_U_W:
4178
0
    case Mips::CLTI_S_B:
4179
0
    case Mips::CLTI_S_D:
4180
0
    case Mips::CLTI_S_H:
4181
0
    case Mips::CLTI_S_W:
4182
0
    case Mips::CLTI_U_B:
4183
0
    case Mips::CLTI_U_D:
4184
0
    case Mips::CLTI_U_H:
4185
0
    case Mips::CLTI_U_W:
4186
0
    case Mips::MAXI_S_B:
4187
0
    case Mips::MAXI_S_D:
4188
0
    case Mips::MAXI_S_H:
4189
0
    case Mips::MAXI_S_W:
4190
0
    case Mips::MAXI_U_B:
4191
0
    case Mips::MAXI_U_D:
4192
0
    case Mips::MAXI_U_H:
4193
0
    case Mips::MAXI_U_W:
4194
0
    case Mips::MINI_S_B:
4195
0
    case Mips::MINI_S_D:
4196
0
    case Mips::MINI_S_H:
4197
0
    case Mips::MINI_S_W:
4198
0
    case Mips::MINI_U_B:
4199
0
    case Mips::MINI_U_D:
4200
0
    case Mips::MINI_U_H:
4201
0
    case Mips::MINI_U_W:
4202
0
    case Mips::SUBVI_B:
4203
0
    case Mips::SUBVI_D:
4204
0
    case Mips::SUBVI_H:
4205
0
    case Mips::SUBVI_W: {
4206
      // op: imm
4207
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4208
0
      op &= UINT64_C(31);
4209
0
      op <<= 16;
4210
0
      Value |= op;
4211
      // op: ws
4212
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4213
0
      op &= UINT64_C(31);
4214
0
      op <<= 11;
4215
0
      Value |= op;
4216
      // op: wd
4217
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4218
0
      op &= UINT64_C(31);
4219
0
      op <<= 6;
4220
0
      Value |= op;
4221
0
      break;
4222
0
    }
4223
0
    case Mips::ADDIUSP_MM: {
4224
      // op: imm
4225
0
      op = getSImm9AddiuspValue(MI, 0, Fixups, STI);
4226
0
      op &= UINT64_C(511);
4227
0
      op <<= 1;
4228
0
      Value |= op;
4229
0
      break;
4230
0
    }
4231
0
    case Mips::JRADDIUSP: {
4232
      // op: imm
4233
0
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
4234
0
      op &= UINT64_C(31);
4235
0
      Value |= op;
4236
0
      break;
4237
0
    }
4238
0
    case Mips::JRCADDIUSP_MMR6: {
4239
      // op: imm
4240
0
      op = getUImm5Lsl2Encoding(MI, 0, Fixups, STI);
4241
0
      op &= UINT64_C(31);
4242
0
      op <<= 5;
4243
0
      Value |= op;
4244
0
      break;
4245
0
    }
4246
0
    case Mips::Bimm16: {
4247
      // op: imm11
4248
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
4249
0
      op &= UINT64_C(2047);
4250
0
      Value |= op;
4251
0
      break;
4252
0
    }
4253
0
    case Mips::AddiuRxRyOffMemX16: {
4254
      // op: imm15
4255
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4256
0
      Value |= (op & UINT64_C(2032)) << 16;
4257
0
      Value |= (op & UINT64_C(30720)) << 5;
4258
0
      Value |= (op & UINT64_C(15));
4259
      // op: rx
4260
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4261
0
      op &= UINT64_C(7);
4262
0
      op <<= 8;
4263
0
      Value |= op;
4264
      // op: ry
4265
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4266
0
      op &= UINT64_C(7);
4267
0
      op <<= 5;
4268
0
      Value |= op;
4269
0
      break;
4270
0
    }
4271
0
    case Mips::BimmX16: {
4272
      // op: imm16
4273
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
4274
0
      Value |= (op & UINT64_C(2016)) << 16;
4275
0
      Value |= (op & UINT64_C(63488)) << 5;
4276
0
      Value |= (op & UINT64_C(31));
4277
0
      break;
4278
0
    }
4279
0
    case Mips::BeqzRxImmX16:
4280
0
    case Mips::BnezRxImmX16: {
4281
      // op: imm16
4282
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
4283
0
      Value |= (op & UINT64_C(2016)) << 16;
4284
0
      Value |= (op & UINT64_C(63488)) << 5;
4285
0
      Value |= (op & UINT64_C(31));
4286
      // op: rx
4287
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4288
0
      op &= UINT64_C(7);
4289
0
      op <<= 8;
4290
0
      Value |= op;
4291
0
      break;
4292
0
    }
4293
0
    case Mips::AddiuSpImmX16:
4294
0
    case Mips::BteqzX16:
4295
0
    case Mips::BtnezX16: {
4296
      // op: imm16
4297
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4298
0
      Value |= (op & UINT64_C(2016)) << 16;
4299
0
      Value |= (op & UINT64_C(63488)) << 5;
4300
0
      Value |= (op & UINT64_C(31));
4301
0
      break;
4302
0
    }
4303
0
    case Mips::AddiuRxImmX16:
4304
0
    case Mips::AddiuRxPcImmX16:
4305
0
    case Mips::CmpiRxImmX16:
4306
0
    case Mips::LiRxImmAlignX16:
4307
0
    case Mips::LiRxImmX16:
4308
0
    case Mips::LwRxPcTcpX16:
4309
0
    case Mips::SltiRxImmX16:
4310
0
    case Mips::SltiuRxImmX16: {
4311
      // op: imm16
4312
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4313
0
      Value |= (op & UINT64_C(2016)) << 16;
4314
0
      Value |= (op & UINT64_C(63488)) << 5;
4315
0
      Value |= (op & UINT64_C(31));
4316
      // op: rx
4317
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4318
0
      op &= UINT64_C(7);
4319
0
      op <<= 8;
4320
0
      Value |= op;
4321
0
      break;
4322
0
    }
4323
0
    case Mips::AddiuRxRxImmX16: {
4324
      // op: imm16
4325
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4326
0
      Value |= (op & UINT64_C(2016)) << 16;
4327
0
      Value |= (op & UINT64_C(63488)) << 5;
4328
0
      Value |= (op & UINT64_C(31));
4329
      // op: rx
4330
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4331
0
      op &= UINT64_C(7);
4332
0
      op <<= 8;
4333
0
      Value |= op;
4334
0
      break;
4335
0
    }
4336
0
    case Mips::LbRxRyOffMemX16:
4337
0
    case Mips::LbuRxRyOffMemX16:
4338
0
    case Mips::LhRxRyOffMemX16:
4339
0
    case Mips::LhuRxRyOffMemX16:
4340
0
    case Mips::LwRxRyOffMemX16:
4341
0
    case Mips::LwRxSpImmX16:
4342
0
    case Mips::SbRxRyOffMemX16:
4343
0
    case Mips::ShRxRyOffMemX16:
4344
0
    case Mips::SwRxRyOffMemX16:
4345
0
    case Mips::SwRxSpImmX16: {
4346
      // op: imm16
4347
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4348
0
      Value |= (op & UINT64_C(2016)) << 16;
4349
0
      Value |= (op & UINT64_C(63488)) << 5;
4350
0
      Value |= (op & UINT64_C(31));
4351
      // op: rx
4352
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4353
0
      op &= UINT64_C(7);
4354
0
      op <<= 8;
4355
0
      Value |= op;
4356
      // op: ry
4357
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4358
0
      op &= UINT64_C(7);
4359
0
      op <<= 5;
4360
0
      Value |= op;
4361
0
      break;
4362
0
    }
4363
0
    case Mips::Jal16:
4364
0
    case Mips::JalB16: {
4365
      // op: imm26
4366
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4367
0
      Value |= (op & UINT64_C(2031616)) << 5;
4368
0
      Value |= (op & UINT64_C(65011712)) >> 5;
4369
0
      Value |= (op & UINT64_C(65535));
4370
0
      break;
4371
0
    }
4372
0
    case Mips::AddiuSpImm16:
4373
0
    case Mips::Bteqz16:
4374
0
    case Mips::Btnez16: {
4375
      // op: imm8
4376
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4377
0
      op &= UINT64_C(255);
4378
0
      Value |= op;
4379
0
      break;
4380
0
    }
4381
0
    case Mips::PREFX_MM: {
4382
      // op: index
4383
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4384
0
      op &= UINT64_C(31);
4385
0
      op <<= 21;
4386
0
      Value |= op;
4387
      // op: base
4388
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4389
0
      op &= UINT64_C(31);
4390
0
      op <<= 16;
4391
0
      Value |= op;
4392
      // op: hint
4393
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4394
0
      op &= UINT64_C(31);
4395
0
      op <<= 11;
4396
0
      Value |= op;
4397
0
      break;
4398
0
    }
4399
0
    case Mips::LBUX_MM:
4400
0
    case Mips::LHX_MM:
4401
0
    case Mips::LWX_MM: {
4402
      // op: index
4403
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4404
0
      op &= UINT64_C(31);
4405
0
      op <<= 21;
4406
0
      Value |= op;
4407
      // op: base
4408
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4409
0
      op &= UINT64_C(31);
4410
0
      op <<= 16;
4411
0
      Value |= op;
4412
      // op: rd
4413
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4414
0
      op &= UINT64_C(31);
4415
0
      op <<= 11;
4416
0
      Value |= op;
4417
0
      break;
4418
0
    }
4419
0
    case Mips::COPY_S_D: {
4420
      // op: n
4421
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4422
0
      op &= UINT64_C(1);
4423
0
      op <<= 16;
4424
0
      Value |= op;
4425
      // op: ws
4426
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4427
0
      op &= UINT64_C(31);
4428
0
      op <<= 11;
4429
0
      Value |= op;
4430
      // op: rd
4431
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4432
0
      op &= UINT64_C(31);
4433
0
      op <<= 6;
4434
0
      Value |= op;
4435
0
      break;
4436
0
    }
4437
0
    case Mips::SPLATI_D: {
4438
      // op: n
4439
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4440
0
      op &= UINT64_C(1);
4441
0
      op <<= 16;
4442
0
      Value |= op;
4443
      // op: ws
4444
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4445
0
      op &= UINT64_C(31);
4446
0
      op <<= 11;
4447
0
      Value |= op;
4448
      // op: wd
4449
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4450
0
      op &= UINT64_C(31);
4451
0
      op <<= 6;
4452
0
      Value |= op;
4453
0
      break;
4454
0
    }
4455
0
    case Mips::INSVE_D: {
4456
      // op: n
4457
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4458
0
      op &= UINT64_C(1);
4459
0
      op <<= 16;
4460
0
      Value |= op;
4461
      // op: ws
4462
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4463
0
      op &= UINT64_C(31);
4464
0
      op <<= 11;
4465
0
      Value |= op;
4466
      // op: wd
4467
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4468
0
      op &= UINT64_C(31);
4469
0
      op <<= 6;
4470
0
      Value |= op;
4471
0
      break;
4472
0
    }
4473
0
    case Mips::COPY_S_B:
4474
0
    case Mips::COPY_U_B: {
4475
      // op: n
4476
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4477
0
      op &= UINT64_C(15);
4478
0
      op <<= 16;
4479
0
      Value |= op;
4480
      // op: ws
4481
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4482
0
      op &= UINT64_C(31);
4483
0
      op <<= 11;
4484
0
      Value |= op;
4485
      // op: rd
4486
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4487
0
      op &= UINT64_C(31);
4488
0
      op <<= 6;
4489
0
      Value |= op;
4490
0
      break;
4491
0
    }
4492
0
    case Mips::SPLATI_B: {
4493
      // op: n
4494
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4495
0
      op &= UINT64_C(15);
4496
0
      op <<= 16;
4497
0
      Value |= op;
4498
      // op: ws
4499
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4500
0
      op &= UINT64_C(31);
4501
0
      op <<= 11;
4502
0
      Value |= op;
4503
      // op: wd
4504
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4505
0
      op &= UINT64_C(31);
4506
0
      op <<= 6;
4507
0
      Value |= op;
4508
0
      break;
4509
0
    }
4510
0
    case Mips::INSVE_B: {
4511
      // op: n
4512
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4513
0
      op &= UINT64_C(15);
4514
0
      op <<= 16;
4515
0
      Value |= op;
4516
      // op: ws
4517
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4518
0
      op &= UINT64_C(31);
4519
0
      op <<= 11;
4520
0
      Value |= op;
4521
      // op: wd
4522
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4523
0
      op &= UINT64_C(31);
4524
0
      op <<= 6;
4525
0
      Value |= op;
4526
0
      break;
4527
0
    }
4528
0
    case Mips::COPY_S_W:
4529
0
    case Mips::COPY_U_W: {
4530
      // op: n
4531
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4532
0
      op &= UINT64_C(3);
4533
0
      op <<= 16;
4534
0
      Value |= op;
4535
      // op: ws
4536
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4537
0
      op &= UINT64_C(31);
4538
0
      op <<= 11;
4539
0
      Value |= op;
4540
      // op: rd
4541
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4542
0
      op &= UINT64_C(31);
4543
0
      op <<= 6;
4544
0
      Value |= op;
4545
0
      break;
4546
0
    }
4547
0
    case Mips::SPLATI_W: {
4548
      // op: n
4549
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4550
0
      op &= UINT64_C(3);
4551
0
      op <<= 16;
4552
0
      Value |= op;
4553
      // op: ws
4554
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4555
0
      op &= UINT64_C(31);
4556
0
      op <<= 11;
4557
0
      Value |= op;
4558
      // op: wd
4559
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4560
0
      op &= UINT64_C(31);
4561
0
      op <<= 6;
4562
0
      Value |= op;
4563
0
      break;
4564
0
    }
4565
0
    case Mips::INSVE_W: {
4566
      // op: n
4567
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4568
0
      op &= UINT64_C(3);
4569
0
      op <<= 16;
4570
0
      Value |= op;
4571
      // op: ws
4572
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4573
0
      op &= UINT64_C(31);
4574
0
      op <<= 11;
4575
0
      Value |= op;
4576
      // op: wd
4577
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4578
0
      op &= UINT64_C(31);
4579
0
      op <<= 6;
4580
0
      Value |= op;
4581
0
      break;
4582
0
    }
4583
0
    case Mips::COPY_S_H:
4584
0
    case Mips::COPY_U_H: {
4585
      // op: n
4586
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4587
0
      op &= UINT64_C(7);
4588
0
      op <<= 16;
4589
0
      Value |= op;
4590
      // op: ws
4591
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4592
0
      op &= UINT64_C(31);
4593
0
      op <<= 11;
4594
0
      Value |= op;
4595
      // op: rd
4596
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4597
0
      op &= UINT64_C(31);
4598
0
      op <<= 6;
4599
0
      Value |= op;
4600
0
      break;
4601
0
    }
4602
0
    case Mips::SPLATI_H: {
4603
      // op: n
4604
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4605
0
      op &= UINT64_C(7);
4606
0
      op <<= 16;
4607
0
      Value |= op;
4608
      // op: ws
4609
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4610
0
      op &= UINT64_C(31);
4611
0
      op <<= 11;
4612
0
      Value |= op;
4613
      // op: wd
4614
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4615
0
      op &= UINT64_C(31);
4616
0
      op <<= 6;
4617
0
      Value |= op;
4618
0
      break;
4619
0
    }
4620
0
    case Mips::INSVE_H: {
4621
      // op: n
4622
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4623
0
      op &= UINT64_C(7);
4624
0
      op <<= 16;
4625
0
      Value |= op;
4626
      // op: ws
4627
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4628
0
      op &= UINT64_C(31);
4629
0
      op <<= 11;
4630
0
      Value |= op;
4631
      // op: wd
4632
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4633
0
      op &= UINT64_C(31);
4634
0
      op <<= 6;
4635
0
      Value |= op;
4636
0
      break;
4637
0
    }
4638
0
    case Mips::INSERT_D: {
4639
      // op: n
4640
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4641
0
      op &= UINT64_C(1);
4642
0
      op <<= 16;
4643
0
      Value |= op;
4644
      // op: rs
4645
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4646
0
      op &= UINT64_C(31);
4647
0
      op <<= 11;
4648
0
      Value |= op;
4649
      // op: wd
4650
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4651
0
      op &= UINT64_C(31);
4652
0
      op <<= 6;
4653
0
      Value |= op;
4654
0
      break;
4655
0
    }
4656
0
    case Mips::SLDI_D: {
4657
      // op: n
4658
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4659
0
      op &= UINT64_C(1);
4660
0
      op <<= 16;
4661
0
      Value |= op;
4662
      // op: ws
4663
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4664
0
      op &= UINT64_C(31);
4665
0
      op <<= 11;
4666
0
      Value |= op;
4667
      // op: wd
4668
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4669
0
      op &= UINT64_C(31);
4670
0
      op <<= 6;
4671
0
      Value |= op;
4672
0
      break;
4673
0
    }
4674
0
    case Mips::INSERT_B: {
4675
      // op: n
4676
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4677
0
      op &= UINT64_C(15);
4678
0
      op <<= 16;
4679
0
      Value |= op;
4680
      // op: rs
4681
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4682
0
      op &= UINT64_C(31);
4683
0
      op <<= 11;
4684
0
      Value |= op;
4685
      // op: wd
4686
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4687
0
      op &= UINT64_C(31);
4688
0
      op <<= 6;
4689
0
      Value |= op;
4690
0
      break;
4691
0
    }
4692
0
    case Mips::SLDI_B: {
4693
      // op: n
4694
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4695
0
      op &= UINT64_C(15);
4696
0
      op <<= 16;
4697
0
      Value |= op;
4698
      // op: ws
4699
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4700
0
      op &= UINT64_C(31);
4701
0
      op <<= 11;
4702
0
      Value |= op;
4703
      // op: wd
4704
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4705
0
      op &= UINT64_C(31);
4706
0
      op <<= 6;
4707
0
      Value |= op;
4708
0
      break;
4709
0
    }
4710
0
    case Mips::INSERT_W: {
4711
      // op: n
4712
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4713
0
      op &= UINT64_C(3);
4714
0
      op <<= 16;
4715
0
      Value |= op;
4716
      // op: rs
4717
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4718
0
      op &= UINT64_C(31);
4719
0
      op <<= 11;
4720
0
      Value |= op;
4721
      // op: wd
4722
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4723
0
      op &= UINT64_C(31);
4724
0
      op <<= 6;
4725
0
      Value |= op;
4726
0
      break;
4727
0
    }
4728
0
    case Mips::SLDI_W: {
4729
      // op: n
4730
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4731
0
      op &= UINT64_C(3);
4732
0
      op <<= 16;
4733
0
      Value |= op;
4734
      // op: ws
4735
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4736
0
      op &= UINT64_C(31);
4737
0
      op <<= 11;
4738
0
      Value |= op;
4739
      // op: wd
4740
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4741
0
      op &= UINT64_C(31);
4742
0
      op <<= 6;
4743
0
      Value |= op;
4744
0
      break;
4745
0
    }
4746
0
    case Mips::INSERT_H: {
4747
      // op: n
4748
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4749
0
      op &= UINT64_C(7);
4750
0
      op <<= 16;
4751
0
      Value |= op;
4752
      // op: rs
4753
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4754
0
      op &= UINT64_C(31);
4755
0
      op <<= 11;
4756
0
      Value |= op;
4757
      // op: wd
4758
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4759
0
      op &= UINT64_C(31);
4760
0
      op <<= 6;
4761
0
      Value |= op;
4762
0
      break;
4763
0
    }
4764
0
    case Mips::SLDI_H: {
4765
      // op: n
4766
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4767
0
      op &= UINT64_C(7);
4768
0
      op <<= 16;
4769
0
      Value |= op;
4770
      // op: ws
4771
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4772
0
      op &= UINT64_C(31);
4773
0
      op <<= 11;
4774
0
      Value |= op;
4775
      // op: wd
4776
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4777
0
      op &= UINT64_C(31);
4778
0
      op <<= 6;
4779
0
      Value |= op;
4780
0
      break;
4781
0
    }
4782
0
    case Mips::BALC:
4783
0
    case Mips::BC: {
4784
      // op: offset
4785
0
      op = getBranchTarget26OpValue(MI, 0, Fixups, STI);
4786
0
      op &= UINT64_C(67108863);
4787
0
      Value |= op;
4788
0
      break;
4789
0
    }
4790
0
    case Mips::BALC_MMR6:
4791
0
    case Mips::BC_MMR6: {
4792
      // op: offset
4793
0
      op = getBranchTarget26OpValueMM(MI, 0, Fixups, STI);
4794
0
      op &= UINT64_C(67108863);
4795
0
      Value |= op;
4796
0
      break;
4797
0
    }
4798
0
    case Mips::BAL:
4799
0
    case Mips::BPOSGE32: {
4800
      // op: offset
4801
0
      op = getBranchTargetOpValue(MI, 0, Fixups, STI);
4802
0
      op &= UINT64_C(65535);
4803
0
      Value |= op;
4804
0
      break;
4805
0
    }
4806
0
    case Mips::BNZ_B:
4807
0
    case Mips::BNZ_D:
4808
0
    case Mips::BNZ_H:
4809
0
    case Mips::BNZ_V:
4810
0
    case Mips::BNZ_W:
4811
0
    case Mips::BZ_B:
4812
0
    case Mips::BZ_D:
4813
0
    case Mips::BZ_H:
4814
0
    case Mips::BZ_V:
4815
0
    case Mips::BZ_W: {
4816
      // op: offset
4817
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
4818
0
      op &= UINT64_C(65535);
4819
0
      Value |= op;
4820
      // op: wt
4821
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4822
0
      op &= UINT64_C(31);
4823
0
      op <<= 16;
4824
0
      Value |= op;
4825
0
      break;
4826
0
    }
4827
0
    case Mips::BPOSGE32C_MMR3: {
4828
      // op: offset
4829
0
      op = getBranchTargetOpValue1SImm16(MI, 0, Fixups, STI);
4830
0
      op &= UINT64_C(65535);
4831
0
      Value |= op;
4832
0
      break;
4833
0
    }
4834
0
    case Mips::BPOSGE32_MM: {
4835
      // op: offset
4836
0
      op = getBranchTargetOpValueMM(MI, 0, Fixups, STI);
4837
0
      op &= UINT64_C(65535);
4838
0
      Value |= op;
4839
0
      break;
4840
0
    }
4841
0
    case Mips::B16_MM:
4842
0
    case Mips::BC16_MMR6: {
4843
      // op: offset
4844
0
      op = getBranchTargetOpValueMMPC10(MI, 0, Fixups, STI);
4845
0
      op &= UINT64_C(1023);
4846
0
      Value |= op;
4847
0
      break;
4848
0
    }
4849
0
    case Mips::Move32R16: {
4850
      // op: r32
4851
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4852
0
      Value |= (op & UINT64_C(7)) << 5;
4853
0
      Value |= (op & UINT64_C(24));
4854
      // op: rz
4855
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4856
0
      op &= UINT64_C(7);
4857
0
      Value |= op;
4858
0
      break;
4859
0
    }
4860
0
    case Mips::CLO:
4861
0
    case Mips::CLZ:
4862
0
    case Mips::DCLO:
4863
0
    case Mips::DCLZ: {
4864
      // op: rd
4865
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4866
0
      Value |= (op & UINT64_C(31)) << 16;
4867
0
      Value |= (op & UINT64_C(31)) << 11;
4868
      // op: rs
4869
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4870
0
      op &= UINT64_C(31);
4871
0
      op <<= 21;
4872
0
      Value |= op;
4873
0
      break;
4874
0
    }
4875
0
    case Mips::MFHI16_MM:
4876
0
    case Mips::MFLO16_MM: {
4877
      // op: rd
4878
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4879
0
      op &= UINT64_C(31);
4880
0
      Value |= op;
4881
0
      break;
4882
0
    }
4883
0
    case Mips::MFHI:
4884
0
    case Mips::MFHI64:
4885
0
    case Mips::MFLO:
4886
0
    case Mips::MFLO64: {
4887
      // op: rd
4888
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4889
0
      op &= UINT64_C(31);
4890
0
      op <<= 11;
4891
0
      Value |= op;
4892
0
      break;
4893
0
    }
4894
0
    case Mips::MFHI_DSP:
4895
0
    case Mips::MFLO_DSP: {
4896
      // op: rd
4897
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4898
0
      op &= UINT64_C(31);
4899
0
      op <<= 11;
4900
0
      Value |= op;
4901
      // op: ac
4902
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4903
0
      op &= UINT64_C(3);
4904
0
      op <<= 21;
4905
0
      Value |= op;
4906
0
      break;
4907
0
    }
4908
0
    case Mips::LWXS_MM: {
4909
      // op: rd
4910
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4911
0
      op &= UINT64_C(31);
4912
0
      op <<= 11;
4913
0
      Value |= op;
4914
      // op: base
4915
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4916
0
      op &= UINT64_C(31);
4917
0
      op <<= 16;
4918
0
      Value |= op;
4919
      // op: index
4920
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4921
0
      op &= UINT64_C(31);
4922
0
      op <<= 21;
4923
0
      Value |= op;
4924
0
      break;
4925
0
    }
4926
0
    case Mips::LBUX:
4927
0
    case Mips::LHX:
4928
0
    case Mips::LWX: {
4929
      // op: rd
4930
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4931
0
      op &= UINT64_C(31);
4932
0
      op <<= 11;
4933
0
      Value |= op;
4934
      // op: base
4935
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4936
0
      op &= UINT64_C(31);
4937
0
      op <<= 21;
4938
0
      Value |= op;
4939
      // op: index
4940
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4941
0
      op &= UINT64_C(31);
4942
0
      op <<= 16;
4943
0
      Value |= op;
4944
0
      break;
4945
0
    }
4946
0
    case Mips::REPL_PH:
4947
0
    case Mips::REPL_PH_MM:
4948
0
    case Mips::REPL_QB: {
4949
      // op: rd
4950
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4951
0
      op &= UINT64_C(31);
4952
0
      op <<= 11;
4953
0
      Value |= op;
4954
      // op: imm
4955
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4956
0
      op &= UINT64_C(1023);
4957
0
      op <<= 16;
4958
0
      Value |= op;
4959
0
      break;
4960
0
    }
4961
0
    case Mips::RDDSP: {
4962
      // op: rd
4963
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4964
0
      op &= UINT64_C(31);
4965
0
      op <<= 11;
4966
0
      Value |= op;
4967
      // op: mask
4968
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4969
0
      op &= UINT64_C(1023);
4970
0
      op <<= 16;
4971
0
      Value |= op;
4972
0
      break;
4973
0
    }
4974
0
    case Mips::ADDQH_PH_MMR2:
4975
0
    case Mips::ADDQH_R_PH_MMR2:
4976
0
    case Mips::ADDQH_R_W_MMR2:
4977
0
    case Mips::ADDQH_W_MMR2:
4978
0
    case Mips::ADDQ_PH_MM:
4979
0
    case Mips::ADDQ_S_PH_MM:
4980
0
    case Mips::ADDQ_S_W_MM:
4981
0
    case Mips::ADDSC_MM:
4982
0
    case Mips::ADDUH_QB_MMR2:
4983
0
    case Mips::ADDUH_R_QB_MMR2:
4984
0
    case Mips::ADDU_PH_MMR2:
4985
0
    case Mips::ADDU_QB_MM:
4986
0
    case Mips::ADDU_S_PH_MMR2:
4987
0
    case Mips::ADDU_S_QB_MM:
4988
0
    case Mips::ADDWC_MM:
4989
0
    case Mips::CMPGDU_EQ_QB_MMR2:
4990
0
    case Mips::CMPGDU_LE_QB_MMR2:
4991
0
    case Mips::CMPGDU_LT_QB_MMR2:
4992
0
    case Mips::MODSUB_MM:
4993
0
    case Mips::MULEQ_S_W_PHL_MM:
4994
0
    case Mips::MULEQ_S_W_PHR_MM:
4995
0
    case Mips::MULEU_S_PH_QBL_MM:
4996
0
    case Mips::MULEU_S_PH_QBR_MM:
4997
0
    case Mips::MULQ_RS_PH_MM:
4998
0
    case Mips::MULQ_RS_W_MMR2:
4999
0
    case Mips::MULQ_S_PH_MMR2:
5000
0
    case Mips::MULQ_S_W_MMR2:
5001
0
    case Mips::MUL_PH_MMR2:
5002
0
    case Mips::MUL_S_PH_MMR2:
5003
0
    case Mips::PACKRL_PH_MM:
5004
0
    case Mips::PICK_PH_MM:
5005
0
    case Mips::PICK_QB_MM:
5006
0
    case Mips::PRECRQU_S_QB_PH_MM:
5007
0
    case Mips::PRECRQ_PH_W_MM:
5008
0
    case Mips::PRECRQ_QB_PH_MM:
5009
0
    case Mips::PRECRQ_RS_PH_W_MM:
5010
0
    case Mips::PRECR_QB_PH_MMR2:
5011
0
    case Mips::SELEQZ_MMR6:
5012
0
    case Mips::SELNEZ_MMR6:
5013
0
    case Mips::SUBQH_PH_MMR2:
5014
0
    case Mips::SUBQH_R_PH_MMR2:
5015
0
    case Mips::SUBQH_R_W_MMR2:
5016
0
    case Mips::SUBQH_W_MMR2:
5017
0
    case Mips::SUBQ_PH_MM:
5018
0
    case Mips::SUBQ_S_PH_MM:
5019
0
    case Mips::SUBQ_S_W_MM:
5020
0
    case Mips::SUBUH_QB_MMR2:
5021
0
    case Mips::SUBUH_R_QB_MMR2:
5022
0
    case Mips::SUBU_PH_MMR2:
5023
0
    case Mips::SUBU_QB_MM:
5024
0
    case Mips::SUBU_S_PH_MMR2:
5025
0
    case Mips::SUBU_S_QB_MM: {
5026
      // op: rd
5027
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5028
0
      op &= UINT64_C(31);
5029
0
      op <<= 11;
5030
0
      Value |= op;
5031
      // op: rs
5032
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5033
0
      op &= UINT64_C(31);
5034
0
      op <<= 16;
5035
0
      Value |= op;
5036
      // op: rt
5037
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5038
0
      op &= UINT64_C(31);
5039
0
      op <<= 21;
5040
0
      Value |= op;
5041
0
      break;
5042
0
    }
5043
0
    case Mips::LSA_MMR6: {
5044
      // op: rd
5045
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5046
0
      op &= UINT64_C(31);
5047
0
      op <<= 11;
5048
0
      Value |= op;
5049
      // op: rs
5050
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5051
0
      op &= UINT64_C(31);
5052
0
      op <<= 16;
5053
0
      Value |= op;
5054
      // op: rt
5055
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5056
0
      op &= UINT64_C(31);
5057
0
      op <<= 21;
5058
0
      Value |= op;
5059
      // op: imm2
5060
0
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
5061
0
      op &= UINT64_C(3);
5062
0
      op <<= 9;
5063
0
      Value |= op;
5064
0
      break;
5065
0
    }
5066
0
    case Mips::CLO_R6:
5067
0
    case Mips::CLZ_R6:
5068
0
    case Mips::DCLO_R6:
5069
0
    case Mips::DCLZ_R6:
5070
0
    case Mips::DPOP:
5071
0
    case Mips::JALR:
5072
0
    case Mips::JALR64:
5073
0
    case Mips::JALR_HB:
5074
0
    case Mips::JALR_HB64:
5075
0
    case Mips::POP:
5076
0
    case Mips::RADDU_W_QB: {
5077
      // op: rd
5078
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5079
0
      op &= UINT64_C(31);
5080
0
      op <<= 11;
5081
0
      Value |= op;
5082
      // op: rs
5083
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5084
0
      op &= UINT64_C(31);
5085
0
      op <<= 21;
5086
0
      Value |= op;
5087
0
      break;
5088
0
    }
5089
0
    case Mips::MOVF_I:
5090
0
    case Mips::MOVF_I64:
5091
0
    case Mips::MOVT_I:
5092
0
    case Mips::MOVT_I64: {
5093
      // op: rd
5094
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5095
0
      op &= UINT64_C(31);
5096
0
      op <<= 11;
5097
0
      Value |= op;
5098
      // op: rs
5099
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5100
0
      op &= UINT64_C(31);
5101
0
      op <<= 21;
5102
0
      Value |= op;
5103
      // op: fcc
5104
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5105
0
      op &= UINT64_C(7);
5106
0
      op <<= 18;
5107
0
      Value |= op;
5108
0
      break;
5109
0
    }
5110
0
    case Mips::ADD:
5111
0
    case Mips::ADDQH_PH:
5112
0
    case Mips::ADDQH_R_PH:
5113
0
    case Mips::ADDQH_R_W:
5114
0
    case Mips::ADDQH_W:
5115
0
    case Mips::ADDQ_PH:
5116
0
    case Mips::ADDQ_S_PH:
5117
0
    case Mips::ADDQ_S_W:
5118
0
    case Mips::ADDSC:
5119
0
    case Mips::ADDUH_QB:
5120
0
    case Mips::ADDUH_R_QB:
5121
0
    case Mips::ADDU_PH:
5122
0
    case Mips::ADDU_QB:
5123
0
    case Mips::ADDU_S_PH:
5124
0
    case Mips::ADDU_S_QB:
5125
0
    case Mips::ADDWC:
5126
0
    case Mips::ADDu:
5127
0
    case Mips::AND:
5128
0
    case Mips::AND64:
5129
0
    case Mips::BADDu:
5130
0
    case Mips::DADD:
5131
0
    case Mips::DADDu:
5132
0
    case Mips::DDIV:
5133
0
    case Mips::DDIVU:
5134
0
    case Mips::DIV:
5135
0
    case Mips::DIVU:
5136
0
    case Mips::DMOD:
5137
0
    case Mips::DMODU:
5138
0
    case Mips::DMUH:
5139
0
    case Mips::DMUHU:
5140
0
    case Mips::DMUL:
5141
0
    case Mips::DMULU:
5142
0
    case Mips::DMUL_R6:
5143
0
    case Mips::DSUB:
5144
0
    case Mips::DSUBu:
5145
0
    case Mips::MOD:
5146
0
    case Mips::MODSUB:
5147
0
    case Mips::MODU:
5148
0
    case Mips::MOVN_I64_I:
5149
0
    case Mips::MOVN_I64_I64:
5150
0
    case Mips::MOVN_I_I:
5151
0
    case Mips::MOVN_I_I64:
5152
0
    case Mips::MOVZ_I64_I:
5153
0
    case Mips::MOVZ_I64_I64:
5154
0
    case Mips::MOVZ_I_I:
5155
0
    case Mips::MOVZ_I_I64:
5156
0
    case Mips::MUH:
5157
0
    case Mips::MUHU:
5158
0
    case Mips::MUL:
5159
0
    case Mips::MULEQ_S_W_PHL:
5160
0
    case Mips::MULEQ_S_W_PHR:
5161
0
    case Mips::MULEU_S_PH_QBL:
5162
0
    case Mips::MULEU_S_PH_QBR:
5163
0
    case Mips::MULQ_RS_PH:
5164
0
    case Mips::MULQ_RS_W:
5165
0
    case Mips::MULQ_S_PH:
5166
0
    case Mips::MULQ_S_W:
5167
0
    case Mips::MULU:
5168
0
    case Mips::MUL_PH:
5169
0
    case Mips::MUL_R6:
5170
0
    case Mips::MUL_S_PH:
5171
0
    case Mips::NOR:
5172
0
    case Mips::NOR64:
5173
0
    case Mips::OR:
5174
0
    case Mips::OR64:
5175
0
    case Mips::SELEQZ:
5176
0
    case Mips::SELEQZ64:
5177
0
    case Mips::SELNEZ:
5178
0
    case Mips::SELNEZ64:
5179
0
    case Mips::SEQ:
5180
0
    case Mips::SLT:
5181
0
    case Mips::SLT64:
5182
0
    case Mips::SLTu:
5183
0
    case Mips::SLTu64:
5184
0
    case Mips::SNE:
5185
0
    case Mips::SUB:
5186
0
    case Mips::SUBQH_PH:
5187
0
    case Mips::SUBQH_R_PH:
5188
0
    case Mips::SUBQH_R_W:
5189
0
    case Mips::SUBQH_W:
5190
0
    case Mips::SUBQ_PH:
5191
0
    case Mips::SUBQ_S_PH:
5192
0
    case Mips::SUBQ_S_W:
5193
0
    case Mips::SUBUH_QB:
5194
0
    case Mips::SUBUH_R_QB:
5195
0
    case Mips::SUBU_PH:
5196
0
    case Mips::SUBU_QB:
5197
0
    case Mips::SUBU_S_PH:
5198
0
    case Mips::SUBU_S_QB:
5199
0
    case Mips::SUBu:
5200
0
    case Mips::V3MULU:
5201
0
    case Mips::VMM0:
5202
0
    case Mips::VMULU:
5203
0
    case Mips::XOR:
5204
0
    case Mips::XOR64: {
5205
      // op: rd
5206
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5207
0
      op &= UINT64_C(31);
5208
0
      op <<= 11;
5209
0
      Value |= op;
5210
      // op: rs
5211
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5212
0
      op &= UINT64_C(31);
5213
0
      op <<= 21;
5214
0
      Value |= op;
5215
      // op: rt
5216
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5217
0
      op &= UINT64_C(31);
5218
0
      op <<= 16;
5219
0
      Value |= op;
5220
0
      break;
5221
0
    }
5222
0
    case Mips::ALIGN: {
5223
      // op: rd
5224
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5225
0
      op &= UINT64_C(31);
5226
0
      op <<= 11;
5227
0
      Value |= op;
5228
      // op: rs
5229
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5230
0
      op &= UINT64_C(31);
5231
0
      op <<= 21;
5232
0
      Value |= op;
5233
      // op: rt
5234
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5235
0
      op &= UINT64_C(31);
5236
0
      op <<= 16;
5237
0
      Value |= op;
5238
      // op: bp
5239
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5240
0
      op &= UINT64_C(3);
5241
0
      op <<= 6;
5242
0
      Value |= op;
5243
0
      break;
5244
0
    }
5245
0
    case Mips::ALIGN_MMR6: {
5246
      // op: rd
5247
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5248
0
      op &= UINT64_C(31);
5249
0
      op <<= 11;
5250
0
      Value |= op;
5251
      // op: rs
5252
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5253
0
      op &= UINT64_C(31);
5254
0
      op <<= 21;
5255
0
      Value |= op;
5256
      // op: rt
5257
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5258
0
      op &= UINT64_C(31);
5259
0
      op <<= 16;
5260
0
      Value |= op;
5261
      // op: bp
5262
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5263
0
      op &= UINT64_C(3);
5264
0
      op <<= 9;
5265
0
      Value |= op;
5266
0
      break;
5267
0
    }
5268
0
    case Mips::DALIGN: {
5269
      // op: rd
5270
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5271
0
      op &= UINT64_C(31);
5272
0
      op <<= 11;
5273
0
      Value |= op;
5274
      // op: rs
5275
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5276
0
      op &= UINT64_C(31);
5277
0
      op <<= 21;
5278
0
      Value |= op;
5279
      // op: rt
5280
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5281
0
      op &= UINT64_C(31);
5282
0
      op <<= 16;
5283
0
      Value |= op;
5284
      // op: bp
5285
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
5286
0
      op &= UINT64_C(7);
5287
0
      op <<= 6;
5288
0
      Value |= op;
5289
0
      break;
5290
0
    }
5291
0
    case Mips::DLSA_R6:
5292
0
    case Mips::LSA_R6: {
5293
      // op: rd
5294
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5295
0
      op &= UINT64_C(31);
5296
0
      op <<= 11;
5297
0
      Value |= op;
5298
      // op: rs
5299
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5300
0
      op &= UINT64_C(31);
5301
0
      op <<= 21;
5302
0
      Value |= op;
5303
      // op: rt
5304
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5305
0
      op &= UINT64_C(31);
5306
0
      op <<= 16;
5307
0
      Value |= op;
5308
      // op: imm2
5309
0
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
5310
0
      op &= UINT64_C(3);
5311
0
      op <<= 6;
5312
0
      Value |= op;
5313
0
      break;
5314
0
    }
5315
0
    case Mips::SHLLV_PH_MM:
5316
0
    case Mips::SHLLV_QB_MM:
5317
0
    case Mips::SHLLV_S_PH_MM:
5318
0
    case Mips::SHLLV_S_W_MM:
5319
0
    case Mips::SHRAV_PH_MM:
5320
0
    case Mips::SHRAV_QB_MMR2:
5321
0
    case Mips::SHRAV_R_PH_MM:
5322
0
    case Mips::SHRAV_R_QB_MMR2:
5323
0
    case Mips::SHRAV_R_W_MM:
5324
0
    case Mips::SHRLV_PH_MMR2:
5325
0
    case Mips::SHRLV_QB_MM: {
5326
      // op: rd
5327
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5328
0
      op &= UINT64_C(31);
5329
0
      op <<= 11;
5330
0
      Value |= op;
5331
      // op: rs
5332
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5333
0
      op &= UINT64_C(31);
5334
0
      op <<= 16;
5335
0
      Value |= op;
5336
      // op: rt
5337
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5338
0
      op &= UINT64_C(31);
5339
0
      op <<= 21;
5340
0
      Value |= op;
5341
0
      break;
5342
0
    }
5343
0
    case Mips::ABSQ_S_PH:
5344
0
    case Mips::ABSQ_S_QB:
5345
0
    case Mips::ABSQ_S_W:
5346
0
    case Mips::BITREV:
5347
0
    case Mips::BITSWAP:
5348
0
    case Mips::DBITSWAP:
5349
0
    case Mips::DSBH:
5350
0
    case Mips::DSHD:
5351
0
    case Mips::DSLL64_32:
5352
0
    case Mips::PRECEQU_PH_QBL:
5353
0
    case Mips::PRECEQU_PH_QBLA:
5354
0
    case Mips::PRECEQU_PH_QBR:
5355
0
    case Mips::PRECEQU_PH_QBRA:
5356
0
    case Mips::PRECEQ_W_PHL:
5357
0
    case Mips::PRECEQ_W_PHR:
5358
0
    case Mips::PRECEU_PH_QBL:
5359
0
    case Mips::PRECEU_PH_QBLA:
5360
0
    case Mips::PRECEU_PH_QBR:
5361
0
    case Mips::PRECEU_PH_QBRA:
5362
0
    case Mips::REPLV_PH:
5363
0
    case Mips::REPLV_QB:
5364
0
    case Mips::SEB:
5365
0
    case Mips::SEB64:
5366
0
    case Mips::SEH:
5367
0
    case Mips::SEH64:
5368
0
    case Mips::SLL64_32:
5369
0
    case Mips::SLL64_64:
5370
0
    case Mips::WSBH: {
5371
      // op: rd
5372
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5373
0
      op &= UINT64_C(31);
5374
0
      op <<= 11;
5375
0
      Value |= op;
5376
      // op: rt
5377
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5378
0
      op &= UINT64_C(31);
5379
0
      op <<= 16;
5380
0
      Value |= op;
5381
0
      break;
5382
0
    }
5383
0
    case Mips::DROTRV:
5384
0
    case Mips::DSLLV:
5385
0
    case Mips::DSRAV:
5386
0
    case Mips::DSRLV:
5387
0
    case Mips::ROTRV:
5388
0
    case Mips::SLLV:
5389
0
    case Mips::SRAV:
5390
0
    case Mips::SRLV: {
5391
      // op: rd
5392
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5393
0
      op &= UINT64_C(31);
5394
0
      op <<= 11;
5395
0
      Value |= op;
5396
      // op: rt
5397
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5398
0
      op &= UINT64_C(31);
5399
0
      op <<= 16;
5400
0
      Value |= op;
5401
      // op: rs
5402
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5403
0
      op &= UINT64_C(31);
5404
0
      op <<= 21;
5405
0
      Value |= op;
5406
0
      break;
5407
0
    }
5408
0
    case Mips::SHLLV_PH:
5409
0
    case Mips::SHLLV_QB:
5410
0
    case Mips::SHLLV_S_PH:
5411
0
    case Mips::SHLLV_S_W:
5412
0
    case Mips::SHLL_PH:
5413
0
    case Mips::SHLL_QB:
5414
0
    case Mips::SHLL_S_PH:
5415
0
    case Mips::SHLL_S_W:
5416
0
    case Mips::SHRAV_PH:
5417
0
    case Mips::SHRAV_QB:
5418
0
    case Mips::SHRAV_R_PH:
5419
0
    case Mips::SHRAV_R_QB:
5420
0
    case Mips::SHRAV_R_W:
5421
0
    case Mips::SHRA_PH:
5422
0
    case Mips::SHRA_QB:
5423
0
    case Mips::SHRA_R_PH:
5424
0
    case Mips::SHRA_R_QB:
5425
0
    case Mips::SHRA_R_W:
5426
0
    case Mips::SHRLV_PH:
5427
0
    case Mips::SHRLV_QB:
5428
0
    case Mips::SHRL_PH:
5429
0
    case Mips::SHRL_QB: {
5430
      // op: rd
5431
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5432
0
      op &= UINT64_C(31);
5433
0
      op <<= 11;
5434
0
      Value |= op;
5435
      // op: rt
5436
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5437
0
      op &= UINT64_C(31);
5438
0
      op <<= 16;
5439
0
      Value |= op;
5440
      // op: rs_sa
5441
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5442
0
      op &= UINT64_C(31);
5443
0
      op <<= 21;
5444
0
      Value |= op;
5445
0
      break;
5446
0
    }
5447
0
    case Mips::DROTR:
5448
0
    case Mips::DROTR32:
5449
0
    case Mips::DSLL:
5450
0
    case Mips::DSLL32:
5451
0
    case Mips::DSRA:
5452
0
    case Mips::DSRA32:
5453
0
    case Mips::DSRL:
5454
0
    case Mips::DSRL32:
5455
0
    case Mips::ROTR:
5456
0
    case Mips::SLL:
5457
0
    case Mips::SRA:
5458
0
    case Mips::SRL: {
5459
      // op: rd
5460
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5461
0
      op &= UINT64_C(31);
5462
0
      op <<= 11;
5463
0
      Value |= op;
5464
      // op: rt
5465
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5466
0
      op &= UINT64_C(31);
5467
0
      op <<= 16;
5468
0
      Value |= op;
5469
      // op: shamt
5470
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5471
0
      op &= UINT64_C(31);
5472
0
      op <<= 6;
5473
0
      Value |= op;
5474
0
      break;
5475
0
    }
5476
0
    case Mips::ROTRV_MM:
5477
0
    case Mips::SLLV_MM:
5478
0
    case Mips::SRAV_MM:
5479
0
    case Mips::SRLV_MM: {
5480
      // op: rd
5481
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5482
0
      op &= UINT64_C(31);
5483
0
      op <<= 11;
5484
0
      Value |= op;
5485
      // op: rt
5486
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5487
0
      op &= UINT64_C(31);
5488
0
      op <<= 21;
5489
0
      Value |= op;
5490
      // op: rs
5491
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5492
0
      op &= UINT64_C(31);
5493
0
      op <<= 16;
5494
0
      Value |= op;
5495
0
      break;
5496
0
    }
5497
0
    case Mips::ADDU_MMR6:
5498
0
    case Mips::ADD_MMR6:
5499
0
    case Mips::AND_MMR6:
5500
0
    case Mips::DIVU_MMR6:
5501
0
    case Mips::DIV_MMR6:
5502
0
    case Mips::MODU_MMR6:
5503
0
    case Mips::MOD_MMR6:
5504
0
    case Mips::MUHU_MMR6:
5505
0
    case Mips::MUH_MMR6:
5506
0
    case Mips::MULU_MMR6:
5507
0
    case Mips::MUL_MMR6:
5508
0
    case Mips::NOR_MMR6:
5509
0
    case Mips::OR_MMR6:
5510
0
    case Mips::SUBU_MMR6:
5511
0
    case Mips::SUB_MMR6:
5512
0
    case Mips::XOR_MMR6: {
5513
      // op: rd
5514
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5515
0
      op &= UINT64_C(31);
5516
0
      op <<= 11;
5517
0
      Value |= op;
5518
      // op: rt
5519
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5520
0
      op &= UINT64_C(31);
5521
0
      op <<= 21;
5522
0
      Value |= op;
5523
      // op: rs
5524
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5525
0
      op &= UINT64_C(31);
5526
0
      op <<= 16;
5527
0
      Value |= op;
5528
0
      break;
5529
0
    }
5530
0
    case Mips::MFHI_MM:
5531
0
    case Mips::MFLO_MM: {
5532
      // op: rd
5533
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5534
0
      op &= UINT64_C(31);
5535
0
      op <<= 16;
5536
0
      Value |= op;
5537
0
      break;
5538
0
    }
5539
0
    case Mips::BITSWAP_MMR6: {
5540
      // op: rd
5541
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5542
0
      op &= UINT64_C(31);
5543
0
      op <<= 16;
5544
0
      Value |= op;
5545
      // op: rt
5546
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5547
0
      op &= UINT64_C(31);
5548
0
      op <<= 21;
5549
0
      Value |= op;
5550
0
      break;
5551
0
    }
5552
0
    case Mips::CLO_MM:
5553
0
    case Mips::CLZ_MM: {
5554
      // op: rd
5555
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5556
0
      op &= UINT64_C(31);
5557
0
      op <<= 21;
5558
0
      Value |= op;
5559
      // op: rs
5560
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5561
0
      op &= UINT64_C(31);
5562
0
      op <<= 16;
5563
0
      Value |= op;
5564
0
      break;
5565
0
    }
5566
0
    case Mips::MOVF_I_MM:
5567
0
    case Mips::MOVT_I_MM: {
5568
      // op: rd
5569
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5570
0
      op &= UINT64_C(31);
5571
0
      op <<= 21;
5572
0
      Value |= op;
5573
      // op: rs
5574
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5575
0
      op &= UINT64_C(31);
5576
0
      op <<= 16;
5577
0
      Value |= op;
5578
      // op: fcc
5579
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5580
0
      op &= UINT64_C(7);
5581
0
      op <<= 13;
5582
0
      Value |= op;
5583
0
      break;
5584
0
    }
5585
0
    case Mips::SEB_MM:
5586
0
    case Mips::SEH_MM:
5587
0
    case Mips::WSBH_MM: {
5588
      // op: rd
5589
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5590
0
      op &= UINT64_C(31);
5591
0
      op <<= 21;
5592
0
      Value |= op;
5593
      // op: rt
5594
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5595
0
      op &= UINT64_C(31);
5596
0
      op <<= 16;
5597
0
      Value |= op;
5598
0
      break;
5599
0
    }
5600
0
    case Mips::ROTR_MM:
5601
0
    case Mips::SLL_MM:
5602
0
    case Mips::SLL_MMR6:
5603
0
    case Mips::SRA_MM:
5604
0
    case Mips::SRL_MM: {
5605
      // op: rd
5606
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5607
0
      op &= UINT64_C(31);
5608
0
      op <<= 21;
5609
0
      Value |= op;
5610
      // op: rt
5611
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5612
0
      op &= UINT64_C(31);
5613
0
      op <<= 16;
5614
0
      Value |= op;
5615
      // op: shamt
5616
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5617
0
      op &= UINT64_C(31);
5618
0
      op <<= 11;
5619
0
      Value |= op;
5620
0
      break;
5621
0
    }
5622
0
    case Mips::CFCMSA: {
5623
      // op: rd
5624
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5625
0
      op &= UINT64_C(31);
5626
0
      op <<= 6;
5627
0
      Value |= op;
5628
      // op: cs
5629
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5630
0
      op &= UINT64_C(31);
5631
0
      op <<= 11;
5632
0
      Value |= op;
5633
0
      break;
5634
0
    }
5635
0
    case Mips::LI16_MM:
5636
0
    case Mips::LI16_MMR6: {
5637
      // op: rd
5638
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5639
0
      op &= UINT64_C(7);
5640
0
      op <<= 7;
5641
0
      Value |= op;
5642
      // op: imm
5643
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5644
0
      op &= UINT64_C(127);
5645
0
      Value |= op;
5646
0
      break;
5647
0
    }
5648
0
    case Mips::ADDIUR1SP_MM: {
5649
      // op: rd
5650
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5651
0
      op &= UINT64_C(7);
5652
0
      op <<= 7;
5653
0
      Value |= op;
5654
      // op: imm
5655
0
      op = getUImm6Lsl2Encoding(MI, 1, Fixups, STI);
5656
0
      op &= UINT64_C(63);
5657
0
      op <<= 1;
5658
0
      Value |= op;
5659
0
      break;
5660
0
    }
5661
0
    case Mips::ADDIUR2_MM: {
5662
      // op: rd
5663
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5664
0
      op &= UINT64_C(7);
5665
0
      op <<= 7;
5666
0
      Value |= op;
5667
      // op: rs
5668
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5669
0
      op &= UINT64_C(7);
5670
0
      op <<= 4;
5671
0
      Value |= op;
5672
      // op: imm
5673
0
      op = getSImm3Lsa2Value(MI, 2, Fixups, STI);
5674
0
      op &= UINT64_C(7);
5675
0
      op <<= 1;
5676
0
      Value |= op;
5677
0
      break;
5678
0
    }
5679
0
    case Mips::ANDI16_MM:
5680
0
    case Mips::ANDI16_MMR6: {
5681
      // op: rd
5682
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5683
0
      op &= UINT64_C(7);
5684
0
      op <<= 7;
5685
0
      Value |= op;
5686
      // op: rs
5687
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5688
0
      op &= UINT64_C(7);
5689
0
      op <<= 4;
5690
0
      Value |= op;
5691
      // op: imm
5692
0
      op = getUImm4AndValue(MI, 2, Fixups, STI);
5693
0
      op &= UINT64_C(15);
5694
0
      Value |= op;
5695
0
      break;
5696
0
    }
5697
0
    case Mips::SLL16_MM:
5698
0
    case Mips::SLL16_MMR6:
5699
0
    case Mips::SRL16_MM:
5700
0
    case Mips::SRL16_MMR6: {
5701
      // op: rd
5702
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5703
0
      op &= UINT64_C(7);
5704
0
      op <<= 7;
5705
0
      Value |= op;
5706
      // op: rt
5707
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5708
0
      op &= UINT64_C(7);
5709
0
      op <<= 4;
5710
0
      Value |= op;
5711
      // op: shamt
5712
0
      op = getUImm3Mod8Encoding(MI, 2, Fixups, STI);
5713
0
      op &= UINT64_C(7);
5714
0
      op <<= 1;
5715
0
      Value |= op;
5716
0
      break;
5717
0
    }
5718
0
    case Mips::ADDU16_MM:
5719
0
    case Mips::SUBU16_MM: {
5720
      // op: rd
5721
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5722
0
      op &= UINT64_C(7);
5723
0
      op <<= 7;
5724
0
      Value |= op;
5725
      // op: rt
5726
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5727
0
      op &= UINT64_C(7);
5728
0
      op <<= 4;
5729
0
      Value |= op;
5730
      // op: rs
5731
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5732
0
      op &= UINT64_C(7);
5733
0
      op <<= 1;
5734
0
      Value |= op;
5735
0
      break;
5736
0
    }
5737
0
    case Mips::ADDIUS5_MM: {
5738
      // op: rd
5739
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5740
0
      op &= UINT64_C(31);
5741
0
      op <<= 5;
5742
0
      Value |= op;
5743
      // op: imm
5744
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5745
0
      op &= UINT64_C(15);
5746
0
      op <<= 1;
5747
0
      Value |= op;
5748
0
      break;
5749
0
    }
5750
0
    case Mips::JALR16_MM:
5751
0
    case Mips::JALRS16_MM:
5752
0
    case Mips::JR16_MM:
5753
0
    case Mips::JRC16_MM: {
5754
      // op: rs
5755
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5756
0
      op &= UINT64_C(31);
5757
0
      Value |= op;
5758
0
      break;
5759
0
    }
5760
0
    case Mips::DVP_MMR6:
5761
0
    case Mips::EVP_MMR6:
5762
0
    case Mips::GINVI_MMR6:
5763
0
    case Mips::JR_MM:
5764
0
    case Mips::MTHI_MM:
5765
0
    case Mips::MTLO_MM: {
5766
      // op: rs
5767
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5768
0
      op &= UINT64_C(31);
5769
0
      op <<= 16;
5770
0
      Value |= op;
5771
0
      break;
5772
0
    }
5773
0
    case Mips::MFHI_DSP_MM:
5774
0
    case Mips::MFLO_DSP_MM: {
5775
      // op: rs
5776
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5777
0
      op &= UINT64_C(31);
5778
0
      op <<= 16;
5779
0
      Value |= op;
5780
      // op: ac
5781
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5782
0
      op &= UINT64_C(3);
5783
0
      op <<= 14;
5784
0
      Value |= op;
5785
0
      break;
5786
0
    }
5787
0
    case Mips::TEQI_MM:
5788
0
    case Mips::TGEIU_MM:
5789
0
    case Mips::TGEI_MM:
5790
0
    case Mips::TLTIU_MM:
5791
0
    case Mips::TLTI_MM:
5792
0
    case Mips::TNEI_MM: {
5793
      // op: rs
5794
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5795
0
      op &= UINT64_C(31);
5796
0
      op <<= 16;
5797
0
      Value |= op;
5798
      // op: imm16
5799
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5800
0
      op &= UINT64_C(65535);
5801
0
      Value |= op;
5802
0
      break;
5803
0
    }
5804
0
    case Mips::BEQZC_MM:
5805
0
    case Mips::BGEZALS_MM:
5806
0
    case Mips::BGEZAL_MM:
5807
0
    case Mips::BGEZ_MM:
5808
0
    case Mips::BGTZ_MM:
5809
0
    case Mips::BLEZ_MM:
5810
0
    case Mips::BLTZALS_MM:
5811
0
    case Mips::BLTZAL_MM:
5812
0
    case Mips::BLTZ_MM:
5813
0
    case Mips::BNEZC_MM: {
5814
      // op: rs
5815
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5816
0
      op &= UINT64_C(31);
5817
0
      op <<= 16;
5818
0
      Value |= op;
5819
      // op: offset
5820
0
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
5821
0
      op &= UINT64_C(65535);
5822
0
      Value |= op;
5823
0
      break;
5824
0
    }
5825
0
    case Mips::MADDU_MM:
5826
0
    case Mips::MADD_MM:
5827
0
    case Mips::MSUBU_MM:
5828
0
    case Mips::MSUB_MM:
5829
0
    case Mips::MULT_MM:
5830
0
    case Mips::MULTu_MM:
5831
0
    case Mips::SDIV_MM:
5832
0
    case Mips::UDIV_MM: {
5833
      // op: rs
5834
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5835
0
      op &= UINT64_C(31);
5836
0
      op <<= 16;
5837
0
      Value |= op;
5838
      // op: rt
5839
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5840
0
      op &= UINT64_C(31);
5841
0
      op <<= 21;
5842
0
      Value |= op;
5843
0
      break;
5844
0
    }
5845
0
    case Mips::TEQ_MM:
5846
0
    case Mips::TGEU_MM:
5847
0
    case Mips::TGE_MM:
5848
0
    case Mips::TLTU_MM:
5849
0
    case Mips::TLT_MM:
5850
0
    case Mips::TNE_MM: {
5851
      // op: rs
5852
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5853
0
      op &= UINT64_C(31);
5854
0
      op <<= 16;
5855
0
      Value |= op;
5856
      // op: rt
5857
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5858
0
      op &= UINT64_C(31);
5859
0
      op <<= 21;
5860
0
      Value |= op;
5861
      // op: code_
5862
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5863
0
      op &= UINT64_C(15);
5864
0
      op <<= 12;
5865
0
      Value |= op;
5866
0
      break;
5867
0
    }
5868
0
    case Mips::BEQ_MM:
5869
0
    case Mips::BNE_MM: {
5870
      // op: rs
5871
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5872
0
      op &= UINT64_C(31);
5873
0
      op <<= 16;
5874
0
      Value |= op;
5875
      // op: rt
5876
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5877
0
      op &= UINT64_C(31);
5878
0
      op <<= 21;
5879
0
      Value |= op;
5880
      // op: offset
5881
0
      op = getBranchTargetOpValueMM(MI, 2, Fixups, STI);
5882
0
      op &= UINT64_C(65535);
5883
0
      Value |= op;
5884
0
      break;
5885
0
    }
5886
0
    case Mips::GINVT_MMR6: {
5887
      // op: rs
5888
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5889
0
      op &= UINT64_C(31);
5890
0
      op <<= 16;
5891
0
      Value |= op;
5892
      // op: type
5893
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5894
0
      op &= UINT64_C(3);
5895
0
      op <<= 9;
5896
0
      Value |= op;
5897
0
      break;
5898
0
    }
5899
0
    case Mips::GINVI:
5900
0
    case Mips::JR:
5901
0
    case Mips::JR64:
5902
0
    case Mips::JR_HB:
5903
0
    case Mips::JR_HB64:
5904
0
    case Mips::JR_HB64_R6:
5905
0
    case Mips::JR_HB_R6:
5906
0
    case Mips::MTHI:
5907
0
    case Mips::MTHI64:
5908
0
    case Mips::MTLO:
5909
0
    case Mips::MTLO64:
5910
0
    case Mips::MTM0:
5911
0
    case Mips::MTM1:
5912
0
    case Mips::MTM2:
5913
0
    case Mips::MTP0:
5914
0
    case Mips::MTP1:
5915
0
    case Mips::MTP2: {
5916
      // op: rs
5917
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5918
0
      op &= UINT64_C(31);
5919
0
      op <<= 21;
5920
0
      Value |= op;
5921
0
      break;
5922
0
    }
5923
0
    case Mips::ALUIPC:
5924
0
    case Mips::AUIPC: {
5925
      // op: rs
5926
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5927
0
      op &= UINT64_C(31);
5928
0
      op <<= 21;
5929
0
      Value |= op;
5930
      // op: imm
5931
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5932
0
      op &= UINT64_C(65535);
5933
0
      Value |= op;
5934
0
      break;
5935
0
    }
5936
0
    case Mips::DAHI:
5937
0
    case Mips::DATI: {
5938
      // op: rs
5939
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5940
0
      op &= UINT64_C(31);
5941
0
      op <<= 21;
5942
0
      Value |= op;
5943
      // op: imm
5944
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
5945
0
      op &= UINT64_C(65535);
5946
0
      Value |= op;
5947
0
      break;
5948
0
    }
5949
0
    case Mips::LDPC: {
5950
      // op: rs
5951
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5952
0
      op &= UINT64_C(31);
5953
0
      op <<= 21;
5954
0
      Value |= op;
5955
      // op: imm
5956
0
      op = getSimm18Lsl3Encoding(MI, 1, Fixups, STI);
5957
0
      op &= UINT64_C(262143);
5958
0
      Value |= op;
5959
0
      break;
5960
0
    }
5961
0
    case Mips::ADDIUPC:
5962
0
    case Mips::LWPC:
5963
0
    case Mips::LWUPC: {
5964
      // op: rs
5965
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5966
0
      op &= UINT64_C(31);
5967
0
      op <<= 21;
5968
0
      Value |= op;
5969
      // op: imm
5970
0
      op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
5971
0
      op &= UINT64_C(524287);
5972
0
      Value |= op;
5973
0
      break;
5974
0
    }
5975
0
    case Mips::TEQI:
5976
0
    case Mips::TGEI:
5977
0
    case Mips::TGEIU:
5978
0
    case Mips::TLTI:
5979
0
    case Mips::TNEI:
5980
0
    case Mips::TTLTIU: {
5981
      // op: rs
5982
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5983
0
      op &= UINT64_C(31);
5984
0
      op <<= 21;
5985
0
      Value |= op;
5986
      // op: imm16
5987
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
5988
0
      op &= UINT64_C(65535);
5989
0
      Value |= op;
5990
0
      break;
5991
0
    }
5992
0
    case Mips::WRDSP: {
5993
      // op: rs
5994
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
5995
0
      op &= UINT64_C(31);
5996
0
      op <<= 21;
5997
0
      Value |= op;
5998
      // op: mask
5999
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6000
0
      op &= UINT64_C(1023);
6001
0
      op <<= 11;
6002
0
      Value |= op;
6003
0
      break;
6004
0
    }
6005
0
    case Mips::BEQZC:
6006
0
    case Mips::BEQZC64:
6007
0
    case Mips::BNEZC:
6008
0
    case Mips::BNEZC64: {
6009
      // op: rs
6010
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6011
0
      op &= UINT64_C(31);
6012
0
      op <<= 21;
6013
0
      Value |= op;
6014
      // op: offset
6015
0
      op = getBranchTarget21OpValue(MI, 1, Fixups, STI);
6016
0
      op &= UINT64_C(2097151);
6017
0
      Value |= op;
6018
0
      break;
6019
0
    }
6020
0
    case Mips::BEQZC_MMR6:
6021
0
    case Mips::BNEZC_MMR6: {
6022
      // op: rs
6023
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6024
0
      op &= UINT64_C(31);
6025
0
      op <<= 21;
6026
0
      Value |= op;
6027
      // op: offset
6028
0
      op = getBranchTarget21OpValueMM(MI, 1, Fixups, STI);
6029
0
      op &= UINT64_C(2097151);
6030
0
      Value |= op;
6031
0
      break;
6032
0
    }
6033
0
    case Mips::BGEZ:
6034
0
    case Mips::BGEZ64:
6035
0
    case Mips::BGEZAL:
6036
0
    case Mips::BGEZALL:
6037
0
    case Mips::BGEZL:
6038
0
    case Mips::BGTZ:
6039
0
    case Mips::BGTZ64:
6040
0
    case Mips::BGTZL:
6041
0
    case Mips::BLEZ:
6042
0
    case Mips::BLEZ64:
6043
0
    case Mips::BLEZL:
6044
0
    case Mips::BLTZ:
6045
0
    case Mips::BLTZ64:
6046
0
    case Mips::BLTZAL:
6047
0
    case Mips::BLTZALL:
6048
0
    case Mips::BLTZL: {
6049
      // op: rs
6050
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6051
0
      op &= UINT64_C(31);
6052
0
      op <<= 21;
6053
0
      Value |= op;
6054
      // op: offset
6055
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
6056
0
      op &= UINT64_C(65535);
6057
0
      Value |= op;
6058
0
      break;
6059
0
    }
6060
0
    case Mips::BBIT0:
6061
0
    case Mips::BBIT1:
6062
0
    case Mips::BBIT032:
6063
0
    case Mips::BBIT132: {
6064
      // op: rs
6065
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6066
0
      op &= UINT64_C(31);
6067
0
      op <<= 21;
6068
0
      Value |= op;
6069
      // op: p
6070
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6071
0
      op &= UINT64_C(31);
6072
0
      op <<= 16;
6073
0
      Value |= op;
6074
      // op: offset
6075
0
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
6076
0
      op &= UINT64_C(65535);
6077
0
      Value |= op;
6078
0
      break;
6079
0
    }
6080
0
    case Mips::CMPU_EQ_QB:
6081
0
    case Mips::CMPU_LE_QB:
6082
0
    case Mips::CMPU_LT_QB:
6083
0
    case Mips::CMP_EQ_PH:
6084
0
    case Mips::CMP_LE_PH:
6085
0
    case Mips::CMP_LT_PH:
6086
0
    case Mips::DMULT:
6087
0
    case Mips::DMULTu:
6088
0
    case Mips::DSDIV:
6089
0
    case Mips::DUDIV:
6090
0
    case Mips::MADD:
6091
0
    case Mips::MADDU:
6092
0
    case Mips::MSUB:
6093
0
    case Mips::MSUBU:
6094
0
    case Mips::MULT:
6095
0
    case Mips::MULTu:
6096
0
    case Mips::SDIV:
6097
0
    case Mips::UDIV: {
6098
      // op: rs
6099
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6100
0
      op &= UINT64_C(31);
6101
0
      op <<= 21;
6102
0
      Value |= op;
6103
      // op: rt
6104
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6105
0
      op &= UINT64_C(31);
6106
0
      op <<= 16;
6107
0
      Value |= op;
6108
0
      break;
6109
0
    }
6110
0
    case Mips::TEQ:
6111
0
    case Mips::TGE:
6112
0
    case Mips::TGEU:
6113
0
    case Mips::TLT:
6114
0
    case Mips::TLTU:
6115
0
    case Mips::TNE: {
6116
      // op: rs
6117
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6118
0
      op &= UINT64_C(31);
6119
0
      op <<= 21;
6120
0
      Value |= op;
6121
      // op: rt
6122
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6123
0
      op &= UINT64_C(31);
6124
0
      op <<= 16;
6125
0
      Value |= op;
6126
      // op: code_
6127
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6128
0
      op &= UINT64_C(1023);
6129
0
      op <<= 6;
6130
0
      Value |= op;
6131
0
      break;
6132
0
    }
6133
0
    case Mips::BEQ:
6134
0
    case Mips::BEQ64:
6135
0
    case Mips::BEQC:
6136
0
    case Mips::BEQC64:
6137
0
    case Mips::BEQL:
6138
0
    case Mips::BGEC:
6139
0
    case Mips::BGEC64:
6140
0
    case Mips::BGEUC:
6141
0
    case Mips::BGEUC64:
6142
0
    case Mips::BLTC:
6143
0
    case Mips::BLTC64:
6144
0
    case Mips::BLTUC:
6145
0
    case Mips::BLTUC64:
6146
0
    case Mips::BNE:
6147
0
    case Mips::BNE64:
6148
0
    case Mips::BNEC:
6149
0
    case Mips::BNEC64:
6150
0
    case Mips::BNEL:
6151
0
    case Mips::BNVC:
6152
0
    case Mips::BOVC: {
6153
      // op: rs
6154
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6155
0
      op &= UINT64_C(31);
6156
0
      op <<= 21;
6157
0
      Value |= op;
6158
      // op: rt
6159
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6160
0
      op &= UINT64_C(31);
6161
0
      op <<= 16;
6162
0
      Value |= op;
6163
      // op: offset
6164
0
      op = getBranchTargetOpValue(MI, 2, Fixups, STI);
6165
0
      op &= UINT64_C(65535);
6166
0
      Value |= op;
6167
0
      break;
6168
0
    }
6169
0
    case Mips::FORK: {
6170
      // op: rs
6171
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6172
0
      op &= UINT64_C(31);
6173
0
      op <<= 21;
6174
0
      Value |= op;
6175
      // op: rt
6176
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6177
0
      op &= UINT64_C(31);
6178
0
      op <<= 16;
6179
0
      Value |= op;
6180
      // op: rd
6181
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6182
0
      op &= UINT64_C(31);
6183
0
      op <<= 11;
6184
0
      Value |= op;
6185
0
      break;
6186
0
    }
6187
0
    case Mips::GINVT: {
6188
      // op: rs
6189
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6190
0
      op &= UINT64_C(31);
6191
0
      op <<= 21;
6192
0
      Value |= op;
6193
      // op: type_
6194
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6195
0
      op &= UINT64_C(3);
6196
0
      op <<= 8;
6197
0
      Value |= op;
6198
0
      break;
6199
0
    }
6200
0
    case Mips::JALRC16_MMR6:
6201
0
    case Mips::JRC16_MMR6: {
6202
      // op: rs
6203
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6204
0
      op &= UINT64_C(31);
6205
0
      op <<= 5;
6206
0
      Value |= op;
6207
0
      break;
6208
0
    }
6209
0
    case Mips::ADDIUPC_MM: {
6210
      // op: rs
6211
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6212
0
      op &= UINT64_C(7);
6213
0
      op <<= 23;
6214
0
      Value |= op;
6215
      // op: imm
6216
0
      op = getSimm23Lsl2Encoding(MI, 1, Fixups, STI);
6217
0
      op &= UINT64_C(8388607);
6218
0
      Value |= op;
6219
0
      break;
6220
0
    }
6221
0
    case Mips::BEQZ16_MM:
6222
0
    case Mips::BEQZC16_MMR6:
6223
0
    case Mips::BNEZ16_MM:
6224
0
    case Mips::BNEZC16_MMR6: {
6225
      // op: rs
6226
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6227
0
      op &= UINT64_C(7);
6228
0
      op <<= 7;
6229
0
      Value |= op;
6230
      // op: offset
6231
0
      op = getBranchTarget7OpValueMM(MI, 1, Fixups, STI);
6232
0
      op &= UINT64_C(127);
6233
0
      Value |= op;
6234
0
      break;
6235
0
    }
6236
0
    case Mips::MOVE16_MM:
6237
0
    case Mips::MOVE16_MMR6: {
6238
      // op: rs
6239
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6240
0
      op &= UINT64_C(31);
6241
0
      Value |= op;
6242
      // op: rd
6243
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6244
0
      op &= UINT64_C(31);
6245
0
      op <<= 5;
6246
0
      Value |= op;
6247
0
      break;
6248
0
    }
6249
0
    case Mips::CTCMSA: {
6250
      // op: rs
6251
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6252
0
      op &= UINT64_C(31);
6253
0
      op <<= 11;
6254
0
      Value |= op;
6255
      // op: cd
6256
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6257
0
      op &= UINT64_C(31);
6258
0
      op <<= 6;
6259
0
      Value |= op;
6260
0
      break;
6261
0
    }
6262
0
    case Mips::FILL_B:
6263
0
    case Mips::FILL_D:
6264
0
    case Mips::FILL_H:
6265
0
    case Mips::FILL_W: {
6266
      // op: rs
6267
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6268
0
      op &= UINT64_C(31);
6269
0
      op <<= 11;
6270
0
      Value |= op;
6271
      // op: wd
6272
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6273
0
      op &= UINT64_C(31);
6274
0
      op <<= 6;
6275
0
      Value |= op;
6276
0
      break;
6277
0
    }
6278
0
    case Mips::MTHI_DSP_MM:
6279
0
    case Mips::MTHLIP_MM:
6280
0
    case Mips::MTLO_DSP_MM:
6281
0
    case Mips::SHILOV_MM: {
6282
      // op: rs
6283
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6284
0
      op &= UINT64_C(31);
6285
0
      op <<= 16;
6286
0
      Value |= op;
6287
      // op: ac
6288
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6289
0
      op &= UINT64_C(3);
6290
0
      op <<= 14;
6291
0
      Value |= op;
6292
0
      break;
6293
0
    }
6294
0
    case Mips::JALRS_MM:
6295
0
    case Mips::JALR_MM: {
6296
      // op: rs
6297
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6298
0
      op &= UINT64_C(31);
6299
0
      op <<= 16;
6300
0
      Value |= op;
6301
      // op: rd
6302
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6303
0
      op &= UINT64_C(31);
6304
0
      op <<= 21;
6305
0
      Value |= op;
6306
0
      break;
6307
0
    }
6308
0
    case Mips::CLO_MMR6: {
6309
      // op: rs
6310
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6311
0
      op &= UINT64_C(31);
6312
0
      op <<= 16;
6313
0
      Value |= op;
6314
      // op: rt
6315
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6316
0
      op &= UINT64_C(31);
6317
0
      op <<= 21;
6318
0
      Value |= op;
6319
0
      break;
6320
0
    }
6321
0
    case Mips::AUI_MMR6: {
6322
      // op: rs
6323
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6324
0
      op &= UINT64_C(31);
6325
0
      op <<= 16;
6326
0
      Value |= op;
6327
      // op: rt
6328
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6329
0
      op &= UINT64_C(31);
6330
0
      op <<= 21;
6331
0
      Value |= op;
6332
      // op: imm
6333
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6334
0
      op &= UINT64_C(65535);
6335
0
      Value |= op;
6336
0
      break;
6337
0
    }
6338
0
    case Mips::ADDi_MM:
6339
0
    case Mips::ADDiu_MM:
6340
0
    case Mips::ANDi_MM:
6341
0
    case Mips::ORi_MM:
6342
0
    case Mips::XORi_MM: {
6343
      // op: rs
6344
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6345
0
      op &= UINT64_C(31);
6346
0
      op <<= 16;
6347
0
      Value |= op;
6348
      // op: rt
6349
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6350
0
      op &= UINT64_C(31);
6351
0
      op <<= 21;
6352
0
      Value |= op;
6353
      // op: imm16
6354
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6355
0
      op &= UINT64_C(65535);
6356
0
      Value |= op;
6357
0
      break;
6358
0
    }
6359
0
    case Mips::MTHI_DSP:
6360
0
    case Mips::MTLO_DSP: {
6361
      // op: rs
6362
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6363
0
      op &= UINT64_C(31);
6364
0
      op <<= 21;
6365
0
      Value |= op;
6366
      // op: ac
6367
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6368
0
      op &= UINT64_C(3);
6369
0
      op <<= 11;
6370
0
      Value |= op;
6371
0
      break;
6372
0
    }
6373
0
    case Mips::YIELD: {
6374
      // op: rs
6375
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6376
0
      op &= UINT64_C(31);
6377
0
      op <<= 21;
6378
0
      Value |= op;
6379
      // op: rd
6380
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6381
0
      op &= UINT64_C(31);
6382
0
      op <<= 11;
6383
0
      Value |= op;
6384
0
      break;
6385
0
    }
6386
0
    case Mips::CLZ_MMR6: {
6387
      // op: rs
6388
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6389
0
      op &= UINT64_C(31);
6390
0
      op <<= 21;
6391
0
      Value |= op;
6392
      // op: rt
6393
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6394
0
      op &= UINT64_C(31);
6395
0
      op <<= 11;
6396
0
      Value |= op;
6397
0
      break;
6398
0
    }
6399
0
    case Mips::AUI:
6400
0
    case Mips::DAUI: {
6401
      // op: rs
6402
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6403
0
      op &= UINT64_C(31);
6404
0
      op <<= 21;
6405
0
      Value |= op;
6406
      // op: rt
6407
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6408
0
      op &= UINT64_C(31);
6409
0
      op <<= 16;
6410
0
      Value |= op;
6411
      // op: imm
6412
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6413
0
      op &= UINT64_C(65535);
6414
0
      Value |= op;
6415
0
      break;
6416
0
    }
6417
0
    case Mips::SEQi:
6418
0
    case Mips::SNEi: {
6419
      // op: rs
6420
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6421
0
      op &= UINT64_C(31);
6422
0
      op <<= 21;
6423
0
      Value |= op;
6424
      // op: rt
6425
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6426
0
      op &= UINT64_C(31);
6427
0
      op <<= 16;
6428
0
      Value |= op;
6429
      // op: imm10
6430
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6431
0
      op &= UINT64_C(1023);
6432
0
      op <<= 6;
6433
0
      Value |= op;
6434
0
      break;
6435
0
    }
6436
0
    case Mips::ADDi:
6437
0
    case Mips::ADDiu:
6438
0
    case Mips::ANDi:
6439
0
    case Mips::ANDi64:
6440
0
    case Mips::DADDi:
6441
0
    case Mips::DADDiu:
6442
0
    case Mips::ORi:
6443
0
    case Mips::ORi64:
6444
0
    case Mips::XORi:
6445
0
    case Mips::XORi64: {
6446
      // op: rs
6447
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6448
0
      op &= UINT64_C(31);
6449
0
      op <<= 21;
6450
0
      Value |= op;
6451
      // op: rt
6452
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6453
0
      op &= UINT64_C(31);
6454
0
      op <<= 16;
6455
0
      Value |= op;
6456
      // op: imm16
6457
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6458
0
      op &= UINT64_C(65535);
6459
0
      Value |= op;
6460
0
      break;
6461
0
    }
6462
0
    case Mips::PRECR_SRA_PH_W:
6463
0
    case Mips::PRECR_SRA_R_PH_W: {
6464
      // op: rs
6465
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6466
0
      op &= UINT64_C(31);
6467
0
      op <<= 21;
6468
0
      Value |= op;
6469
      // op: rt
6470
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6471
0
      op &= UINT64_C(31);
6472
0
      op <<= 16;
6473
0
      Value |= op;
6474
      // op: sa
6475
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6476
0
      op &= UINT64_C(31);
6477
0
      op <<= 11;
6478
0
      Value |= op;
6479
0
      break;
6480
0
    }
6481
0
    case Mips::CRC32B:
6482
0
    case Mips::CRC32CB:
6483
0
    case Mips::CRC32CD:
6484
0
    case Mips::CRC32CH:
6485
0
    case Mips::CRC32CW:
6486
0
    case Mips::CRC32D:
6487
0
    case Mips::CRC32H:
6488
0
    case Mips::CRC32W: {
6489
      // op: rs
6490
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6491
0
      op &= UINT64_C(31);
6492
0
      op <<= 21;
6493
0
      Value |= op;
6494
      // op: rt
6495
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6496
0
      op &= UINT64_C(31);
6497
0
      op <<= 16;
6498
0
      Value |= op;
6499
0
      break;
6500
0
    }
6501
0
    case Mips::CMPGDU_EQ_QB:
6502
0
    case Mips::CMPGDU_LE_QB:
6503
0
    case Mips::CMPGDU_LT_QB:
6504
0
    case Mips::CMPGU_EQ_QB:
6505
0
    case Mips::CMPGU_LE_QB:
6506
0
    case Mips::CMPGU_LT_QB:
6507
0
    case Mips::PACKRL_PH:
6508
0
    case Mips::PICK_PH:
6509
0
    case Mips::PICK_QB:
6510
0
    case Mips::PRECRQU_S_QB_PH:
6511
0
    case Mips::PRECRQ_PH_W:
6512
0
    case Mips::PRECRQ_QB_PH:
6513
0
    case Mips::PRECRQ_RS_PH_W:
6514
0
    case Mips::PRECR_QB_PH: {
6515
      // op: rs
6516
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6517
0
      op &= UINT64_C(31);
6518
0
      op <<= 21;
6519
0
      Value |= op;
6520
      // op: rt
6521
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6522
0
      op &= UINT64_C(31);
6523
0
      op <<= 16;
6524
0
      Value |= op;
6525
      // op: rd
6526
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6527
0
      op &= UINT64_C(31);
6528
0
      op <<= 11;
6529
0
      Value |= op;
6530
0
      break;
6531
0
    }
6532
0
    case Mips::DLSA:
6533
0
    case Mips::LSA: {
6534
      // op: rs
6535
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6536
0
      op &= UINT64_C(31);
6537
0
      op <<= 21;
6538
0
      Value |= op;
6539
      // op: rt
6540
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6541
0
      op &= UINT64_C(31);
6542
0
      op <<= 16;
6543
0
      Value |= op;
6544
      // op: rd
6545
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6546
0
      op &= UINT64_C(31);
6547
0
      op <<= 11;
6548
0
      Value |= op;
6549
      // op: sa
6550
0
      op = getUImmWithOffsetEncoding<2, 1>(MI, 3, Fixups, STI);
6551
0
      op &= UINT64_C(3);
6552
0
      op <<= 6;
6553
0
      Value |= op;
6554
0
      break;
6555
0
    }
6556
0
    case Mips::ADDU16_MMR6:
6557
0
    case Mips::SUBU16_MMR6: {
6558
      // op: rs
6559
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6560
0
      op &= UINT64_C(7);
6561
0
      op <<= 7;
6562
0
      Value |= op;
6563
      // op: rt
6564
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6565
0
      op &= UINT64_C(7);
6566
0
      op <<= 4;
6567
0
      Value |= op;
6568
      // op: rd
6569
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6570
0
      op &= UINT64_C(7);
6571
0
      op <<= 1;
6572
0
      Value |= op;
6573
0
      break;
6574
0
    }
6575
0
    case Mips::BGEZALC:
6576
0
    case Mips::BGEZC:
6577
0
    case Mips::BGEZC64:
6578
0
    case Mips::BLTZALC:
6579
0
    case Mips::BLTZC:
6580
0
    case Mips::BLTZC64: {
6581
      // op: rt
6582
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6583
0
      Value |= (op & UINT64_C(31)) << 21;
6584
0
      Value |= (op & UINT64_C(31)) << 16;
6585
      // op: offset
6586
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
6587
0
      op &= UINT64_C(65535);
6588
0
      Value |= op;
6589
0
      break;
6590
0
    }
6591
0
    case Mips::BGEZC_MMR6:
6592
0
    case Mips::BLTZC_MMR6: {
6593
      // op: rt
6594
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6595
0
      Value |= (op & UINT64_C(31)) << 21;
6596
0
      Value |= (op & UINT64_C(31)) << 16;
6597
      // op: offset
6598
0
      op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI);
6599
0
      op &= UINT64_C(65535);
6600
0
      Value |= op;
6601
0
      break;
6602
0
    }
6603
0
    case Mips::BGEZALC_MMR6:
6604
0
    case Mips::BLTZALC_MMR6: {
6605
      // op: rt
6606
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6607
0
      Value |= (op & UINT64_C(31)) << 21;
6608
0
      Value |= (op & UINT64_C(31)) << 16;
6609
      // op: offset
6610
0
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
6611
0
      op &= UINT64_C(65535);
6612
0
      Value |= op;
6613
0
      break;
6614
0
    }
6615
0
    case Mips::DI:
6616
0
    case Mips::DI_MM:
6617
0
    case Mips::DI_MMR6:
6618
0
    case Mips::DMT:
6619
0
    case Mips::DVP:
6620
0
    case Mips::DVPE:
6621
0
    case Mips::EI:
6622
0
    case Mips::EI_MM:
6623
0
    case Mips::EI_MMR6:
6624
0
    case Mips::EMT:
6625
0
    case Mips::EVP:
6626
0
    case Mips::EVPE: {
6627
      // op: rt
6628
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6629
0
      op &= UINT64_C(31);
6630
0
      op <<= 16;
6631
0
      Value |= op;
6632
0
      break;
6633
0
    }
6634
0
    case Mips::EXTP:
6635
0
    case Mips::EXTPDP:
6636
0
    case Mips::EXTPDPV:
6637
0
    case Mips::EXTPV:
6638
0
    case Mips::EXTRV_RS_W:
6639
0
    case Mips::EXTRV_R_W:
6640
0
    case Mips::EXTRV_S_H:
6641
0
    case Mips::EXTRV_W:
6642
0
    case Mips::EXTR_RS_W:
6643
0
    case Mips::EXTR_R_W:
6644
0
    case Mips::EXTR_S_H:
6645
0
    case Mips::EXTR_W: {
6646
      // op: rt
6647
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6648
0
      op &= UINT64_C(31);
6649
0
      op <<= 16;
6650
0
      Value |= op;
6651
      // op: ac
6652
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6653
0
      op &= UINT64_C(3);
6654
0
      op <<= 11;
6655
0
      Value |= op;
6656
      // op: shift_rs
6657
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6658
0
      op &= UINT64_C(31);
6659
0
      op <<= 21;
6660
0
      Value |= op;
6661
0
      break;
6662
0
    }
6663
0
    case Mips::LL64_R6:
6664
0
    case Mips::LLD_R6:
6665
0
    case Mips::LL_R6: {
6666
      // op: rt
6667
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6668
0
      op &= UINT64_C(31);
6669
0
      op <<= 16;
6670
0
      Value |= op;
6671
      // op: addr
6672
0
      op = getMemEncoding(MI, 1, Fixups, STI);
6673
0
      Value |= (op & UINT64_C(2031616)) << 5;
6674
0
      Value |= (op & UINT64_C(511)) << 7;
6675
0
      break;
6676
0
    }
6677
0
    case Mips::LB:
6678
0
    case Mips::LB64:
6679
0
    case Mips::LBu:
6680
0
    case Mips::LBu64:
6681
0
    case Mips::LD:
6682
0
    case Mips::LDC1:
6683
0
    case Mips::LDC2:
6684
0
    case Mips::LDC3:
6685
0
    case Mips::LDC164:
6686
0
    case Mips::LDL:
6687
0
    case Mips::LDR:
6688
0
    case Mips::LEA_ADDiu:
6689
0
    case Mips::LEA_ADDiu64:
6690
0
    case Mips::LH:
6691
0
    case Mips::LH64:
6692
0
    case Mips::LHu:
6693
0
    case Mips::LHu64:
6694
0
    case Mips::LL:
6695
0
    case Mips::LL64:
6696
0
    case Mips::LLD:
6697
0
    case Mips::LW:
6698
0
    case Mips::LW64:
6699
0
    case Mips::LWC1:
6700
0
    case Mips::LWC2:
6701
0
    case Mips::LWC3:
6702
0
    case Mips::LWDSP:
6703
0
    case Mips::LWL:
6704
0
    case Mips::LWL64:
6705
0
    case Mips::LWR:
6706
0
    case Mips::LWR64:
6707
0
    case Mips::LWu:
6708
0
    case Mips::SB:
6709
0
    case Mips::SB64:
6710
0
    case Mips::SD:
6711
0
    case Mips::SDC1:
6712
0
    case Mips::SDC2:
6713
0
    case Mips::SDC3:
6714
0
    case Mips::SDC164:
6715
0
    case Mips::SDL:
6716
0
    case Mips::SDR:
6717
0
    case Mips::SH:
6718
0
    case Mips::SH64:
6719
0
    case Mips::SW:
6720
0
    case Mips::SW64:
6721
0
    case Mips::SWC1:
6722
0
    case Mips::SWC2:
6723
0
    case Mips::SWC3:
6724
0
    case Mips::SWDSP:
6725
0
    case Mips::SWL:
6726
0
    case Mips::SWL64:
6727
0
    case Mips::SWR:
6728
0
    case Mips::SWR64: {
6729
      // op: rt
6730
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6731
0
      op &= UINT64_C(31);
6732
0
      op <<= 16;
6733
0
      Value |= op;
6734
      // op: addr
6735
0
      op = getMemEncoding(MI, 1, Fixups, STI);
6736
0
      Value |= (op & UINT64_C(2031616)) << 5;
6737
0
      Value |= (op & UINT64_C(65535));
6738
0
      break;
6739
0
    }
6740
0
    case Mips::LDC2_R6:
6741
0
    case Mips::LWC2_R6:
6742
0
    case Mips::SDC2_R6:
6743
0
    case Mips::SWC2_R6: {
6744
      // op: rt
6745
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6746
0
      op &= UINT64_C(31);
6747
0
      op <<= 16;
6748
0
      Value |= op;
6749
      // op: addr
6750
0
      op = getMemEncoding(MI, 1, Fixups, STI);
6751
0
      Value |= (op & UINT64_C(2031616)) >> 5;
6752
0
      Value |= (op & UINT64_C(2047));
6753
0
      break;
6754
0
    }
6755
0
    case Mips::CFC1:
6756
0
    case Mips::DMFC1:
6757
0
    case Mips::MFC1:
6758
0
    case Mips::MFC1_D64:
6759
0
    case Mips::MFHC1_D32:
6760
0
    case Mips::MFHC1_D64: {
6761
      // op: rt
6762
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6763
0
      op &= UINT64_C(31);
6764
0
      op <<= 16;
6765
0
      Value |= op;
6766
      // op: fs
6767
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6768
0
      op &= UINT64_C(31);
6769
0
      op <<= 11;
6770
0
      Value |= op;
6771
0
      break;
6772
0
    }
6773
0
    case Mips::DMFC2_OCTEON:
6774
0
    case Mips::DMTC2_OCTEON:
6775
0
    case Mips::LUi:
6776
0
    case Mips::LUi64:
6777
0
    case Mips::LUi_MM: {
6778
      // op: rt
6779
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6780
0
      op &= UINT64_C(31);
6781
0
      op <<= 16;
6782
0
      Value |= op;
6783
      // op: imm16
6784
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6785
0
      op &= UINT64_C(65535);
6786
0
      Value |= op;
6787
0
      break;
6788
0
    }
6789
0
    case Mips::BEQZALC:
6790
0
    case Mips::BGTZALC:
6791
0
    case Mips::BGTZC:
6792
0
    case Mips::BGTZC64:
6793
0
    case Mips::BLEZALC:
6794
0
    case Mips::BLEZC:
6795
0
    case Mips::BLEZC64:
6796
0
    case Mips::BNEZALC: {
6797
      // op: rt
6798
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6799
0
      op &= UINT64_C(31);
6800
0
      op <<= 16;
6801
0
      Value |= op;
6802
      // op: offset
6803
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
6804
0
      op &= UINT64_C(65535);
6805
0
      Value |= op;
6806
0
      break;
6807
0
    }
6808
0
    case Mips::BC1EQZC_MMR6:
6809
0
    case Mips::BC1NEZC_MMR6:
6810
0
    case Mips::BC2EQZC_MMR6:
6811
0
    case Mips::BC2NEZC_MMR6: {
6812
      // op: rt
6813
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6814
0
      op &= UINT64_C(31);
6815
0
      op <<= 16;
6816
0
      Value |= op;
6817
      // op: offset
6818
0
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
6819
0
      op &= UINT64_C(65535);
6820
0
      Value |= op;
6821
0
      break;
6822
0
    }
6823
0
    case Mips::JIALC:
6824
0
    case Mips::JIALC64:
6825
0
    case Mips::JIALC_MMR6:
6826
0
    case Mips::JIC:
6827
0
    case Mips::JIC64:
6828
0
    case Mips::JIC_MMR6: {
6829
      // op: rt
6830
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6831
0
      op &= UINT64_C(31);
6832
0
      op <<= 16;
6833
0
      Value |= op;
6834
      // op: offset
6835
0
      op = getJumpOffset16OpValue(MI, 1, Fixups, STI);
6836
0
      op &= UINT64_C(65535);
6837
0
      Value |= op;
6838
0
      break;
6839
0
    }
6840
0
    case Mips::DMFC0:
6841
0
    case Mips::DMFC2:
6842
0
    case Mips::DMFGC0:
6843
0
    case Mips::MFC0:
6844
0
    case Mips::MFC2:
6845
0
    case Mips::MFGC0:
6846
0
    case Mips::MFHGC0: {
6847
      // op: rt
6848
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6849
0
      op &= UINT64_C(31);
6850
0
      op <<= 16;
6851
0
      Value |= op;
6852
      // op: rd
6853
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6854
0
      op &= UINT64_C(31);
6855
0
      op <<= 11;
6856
0
      Value |= op;
6857
      // op: sel
6858
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6859
0
      op &= UINT64_C(7);
6860
0
      Value |= op;
6861
0
      break;
6862
0
    }
6863
0
    case Mips::RDHWR:
6864
0
    case Mips::RDHWR64: {
6865
      // op: rt
6866
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6867
0
      op &= UINT64_C(31);
6868
0
      op <<= 16;
6869
0
      Value |= op;
6870
      // op: rd
6871
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6872
0
      op &= UINT64_C(31);
6873
0
      op <<= 11;
6874
0
      Value |= op;
6875
      // op: sel
6876
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6877
0
      op &= UINT64_C(7);
6878
0
      op <<= 6;
6879
0
      Value |= op;
6880
0
      break;
6881
0
    }
6882
0
    case Mips::SAA:
6883
0
    case Mips::SAAD: {
6884
      // op: rt
6885
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6886
0
      op &= UINT64_C(31);
6887
0
      op <<= 16;
6888
0
      Value |= op;
6889
      // op: rs
6890
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6891
0
      op &= UINT64_C(31);
6892
0
      op <<= 21;
6893
0
      Value |= op;
6894
0
      break;
6895
0
    }
6896
0
    case Mips::SLTi:
6897
0
    case Mips::SLTi64:
6898
0
    case Mips::SLTiu:
6899
0
    case Mips::SLTiu64: {
6900
      // op: rt
6901
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6902
0
      op &= UINT64_C(31);
6903
0
      op <<= 16;
6904
0
      Value |= op;
6905
      // op: rs
6906
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6907
0
      op &= UINT64_C(31);
6908
0
      op <<= 21;
6909
0
      Value |= op;
6910
      // op: imm16
6911
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6912
0
      op &= UINT64_C(65535);
6913
0
      Value |= op;
6914
0
      break;
6915
0
    }
6916
0
    case Mips::CINS:
6917
0
    case Mips::CINS32:
6918
0
    case Mips::CINS64_32:
6919
0
    case Mips::CINS_i32:
6920
0
    case Mips::EXTS:
6921
0
    case Mips::EXTS32: {
6922
      // op: rt
6923
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6924
0
      op &= UINT64_C(31);
6925
0
      op <<= 16;
6926
0
      Value |= op;
6927
      // op: rs
6928
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6929
0
      op &= UINT64_C(31);
6930
0
      op <<= 21;
6931
0
      Value |= op;
6932
      // op: pos
6933
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6934
0
      op &= UINT64_C(31);
6935
0
      op <<= 6;
6936
0
      Value |= op;
6937
      // op: lenm1
6938
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
6939
0
      op &= UINT64_C(31);
6940
0
      op <<= 11;
6941
0
      Value |= op;
6942
0
      break;
6943
0
    }
6944
0
    case Mips::DINS:
6945
0
    case Mips::DINSM:
6946
0
    case Mips::DINSU:
6947
0
    case Mips::INS: {
6948
      // op: rt
6949
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6950
0
      op &= UINT64_C(31);
6951
0
      op <<= 16;
6952
0
      Value |= op;
6953
      // op: rs
6954
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6955
0
      op &= UINT64_C(31);
6956
0
      op <<= 21;
6957
0
      Value |= op;
6958
      // op: pos
6959
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6960
0
      op &= UINT64_C(31);
6961
0
      op <<= 6;
6962
0
      Value |= op;
6963
      // op: size
6964
0
      op = getSizeInsEncoding(MI, 3, Fixups, STI);
6965
0
      op &= UINT64_C(31);
6966
0
      op <<= 11;
6967
0
      Value |= op;
6968
0
      break;
6969
0
    }
6970
0
    case Mips::DEXT:
6971
0
    case Mips::DEXT64_32:
6972
0
    case Mips::DEXTM:
6973
0
    case Mips::DEXTU:
6974
0
    case Mips::EXT: {
6975
      // op: rt
6976
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
6977
0
      op &= UINT64_C(31);
6978
0
      op <<= 16;
6979
0
      Value |= op;
6980
      // op: rs
6981
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
6982
0
      op &= UINT64_C(31);
6983
0
      op <<= 21;
6984
0
      Value |= op;
6985
      // op: pos
6986
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
6987
0
      op &= UINT64_C(31);
6988
0
      op <<= 6;
6989
0
      Value |= op;
6990
      // op: size
6991
0
      op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
6992
0
      op &= UINT64_C(31);
6993
0
      op <<= 11;
6994
0
      Value |= op;
6995
0
      break;
6996
0
    }
6997
0
    case Mips::APPEND:
6998
0
    case Mips::BALIGN:
6999
0
    case Mips::PREPEND: {
7000
      // op: rt
7001
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7002
0
      op &= UINT64_C(31);
7003
0
      op <<= 16;
7004
0
      Value |= op;
7005
      // op: rs
7006
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7007
0
      op &= UINT64_C(31);
7008
0
      op <<= 21;
7009
0
      Value |= op;
7010
      // op: sa
7011
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7012
0
      op &= UINT64_C(31);
7013
0
      op <<= 11;
7014
0
      Value |= op;
7015
0
      break;
7016
0
    }
7017
0
    case Mips::INSV: {
7018
      // op: rt
7019
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7020
0
      op &= UINT64_C(31);
7021
0
      op <<= 16;
7022
0
      Value |= op;
7023
      // op: rs
7024
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7025
0
      op &= UINT64_C(31);
7026
0
      op <<= 21;
7027
0
      Value |= op;
7028
0
      break;
7029
0
    }
7030
0
    case Mips::LWU_MM: {
7031
      // op: rt
7032
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7033
0
      op &= UINT64_C(31);
7034
0
      op <<= 21;
7035
0
      Value |= op;
7036
      // op: addr
7037
0
      op = getMemEncoding(MI, 1, Fixups, STI);
7038
0
      Value |= (op & UINT64_C(2031616));
7039
0
      Value |= (op & UINT64_C(4095));
7040
0
      break;
7041
0
    }
7042
0
    case Mips::LBE_MM:
7043
0
    case Mips::LBuE_MM:
7044
0
    case Mips::LHE_MM:
7045
0
    case Mips::LHuE_MM:
7046
0
    case Mips::LLE_MM:
7047
0
    case Mips::LWE_MM:
7048
0
    case Mips::SBE_MM:
7049
0
    case Mips::SHE_MM:
7050
0
    case Mips::SWE_MM: {
7051
      // op: rt
7052
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7053
0
      op &= UINT64_C(31);
7054
0
      op <<= 21;
7055
0
      Value |= op;
7056
      // op: addr
7057
0
      op = getMemEncoding(MI, 1, Fixups, STI);
7058
0
      Value |= (op & UINT64_C(2031616));
7059
0
      Value |= (op & UINT64_C(511));
7060
0
      break;
7061
0
    }
7062
0
    case Mips::LEA_ADDiu_MM:
7063
0
    case Mips::LH_MM:
7064
0
    case Mips::LHu_MM:
7065
0
    case Mips::LWDSP_MM:
7066
0
    case Mips::LW_MM:
7067
0
    case Mips::LW_MMR6:
7068
0
    case Mips::SB_MM:
7069
0
    case Mips::SB_MMR6:
7070
0
    case Mips::SH_MM:
7071
0
    case Mips::SH_MMR6:
7072
0
    case Mips::SWDSP_MM:
7073
0
    case Mips::SW_MM:
7074
0
    case Mips::SW_MMR6: {
7075
      // op: rt
7076
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7077
0
      op &= UINT64_C(31);
7078
0
      op <<= 21;
7079
0
      Value |= op;
7080
      // op: addr
7081
0
      op = getMemEncoding(MI, 1, Fixups, STI);
7082
0
      op &= UINT64_C(2097151);
7083
0
      Value |= op;
7084
0
      break;
7085
0
    }
7086
0
    case Mips::LWP_MM:
7087
0
    case Mips::SWP_MM: {
7088
      // op: rt
7089
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7090
0
      op &= UINT64_C(31);
7091
0
      op <<= 21;
7092
0
      Value |= op;
7093
      // op: addr
7094
0
      op = getMemEncoding(MI, 2, Fixups, STI);
7095
0
      Value |= (op & UINT64_C(2031616));
7096
0
      Value |= (op & UINT64_C(4095));
7097
0
      break;
7098
0
    }
7099
0
    case Mips::LDC2_MMR6:
7100
0
    case Mips::LWC2_MMR6:
7101
0
    case Mips::SDC2_MMR6:
7102
0
    case Mips::SWC2_MMR6: {
7103
      // op: rt
7104
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7105
0
      op &= UINT64_C(31);
7106
0
      op <<= 21;
7107
0
      Value |= op;
7108
      // op: addr
7109
0
      op = getMemEncodingMMImm11(MI, 1, Fixups, STI);
7110
0
      Value |= (op & UINT64_C(2031616));
7111
0
      Value |= (op & UINT64_C(2047));
7112
0
      break;
7113
0
    }
7114
0
    case Mips::LL_MM:
7115
0
    case Mips::LWL_MM:
7116
0
    case Mips::LWR_MM:
7117
0
    case Mips::SWL_MM:
7118
0
    case Mips::SWR_MM: {
7119
      // op: rt
7120
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7121
0
      op &= UINT64_C(31);
7122
0
      op <<= 21;
7123
0
      Value |= op;
7124
      // op: addr
7125
0
      op = getMemEncodingMMImm12(MI, 1, Fixups, STI);
7126
0
      Value |= (op & UINT64_C(2031616));
7127
0
      Value |= (op & UINT64_C(4095));
7128
0
      break;
7129
0
    }
7130
0
    case Mips::LB_MM:
7131
0
    case Mips::LBu_MM:
7132
0
    case Mips::LDC1_MM_D32:
7133
0
    case Mips::LDC1_MM_D64:
7134
0
    case Mips::LWC1_MM:
7135
0
    case Mips::SDC1_MM_D32:
7136
0
    case Mips::SDC1_MM_D64:
7137
0
    case Mips::SWC1_MM: {
7138
      // op: rt
7139
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7140
0
      op &= UINT64_C(31);
7141
0
      op <<= 21;
7142
0
      Value |= op;
7143
      // op: addr
7144
0
      op = getMemEncodingMMImm16(MI, 1, Fixups, STI);
7145
0
      op &= UINT64_C(2097151);
7146
0
      Value |= op;
7147
0
      break;
7148
0
    }
7149
0
    case Mips::LL_MMR6:
7150
0
    case Mips::LWLE_MM:
7151
0
    case Mips::LWRE_MM:
7152
0
    case Mips::SWLE_MM:
7153
0
    case Mips::SWRE_MM: {
7154
      // op: rt
7155
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7156
0
      op &= UINT64_C(31);
7157
0
      op <<= 21;
7158
0
      Value |= op;
7159
      // op: addr
7160
0
      op = getMemEncodingMMImm9(MI, 1, Fixups, STI);
7161
0
      Value |= (op & UINT64_C(2031616));
7162
0
      Value |= (op & UINT64_C(511));
7163
0
      break;
7164
0
    }
7165
0
    case Mips::CFC1_MM:
7166
0
    case Mips::MFC1_MM:
7167
0
    case Mips::MFC1_MMR6:
7168
0
    case Mips::MFHC1_D32_MM:
7169
0
    case Mips::MFHC1_D64_MM: {
7170
      // op: rt
7171
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7172
0
      op &= UINT64_C(31);
7173
0
      op <<= 21;
7174
0
      Value |= op;
7175
      // op: fs
7176
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7177
0
      op &= UINT64_C(31);
7178
0
      op <<= 16;
7179
0
      Value |= op;
7180
0
      break;
7181
0
    }
7182
0
    case Mips::REPL_QB_MM: {
7183
      // op: rt
7184
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7185
0
      op &= UINT64_C(31);
7186
0
      op <<= 21;
7187
0
      Value |= op;
7188
      // op: imm
7189
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7190
0
      op &= UINT64_C(255);
7191
0
      op <<= 13;
7192
0
      Value |= op;
7193
0
      break;
7194
0
    }
7195
0
    case Mips::ALUIPC_MMR6:
7196
0
    case Mips::AUIPC_MMR6: {
7197
      // op: rt
7198
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7199
0
      op &= UINT64_C(31);
7200
0
      op <<= 21;
7201
0
      Value |= op;
7202
      // op: imm
7203
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7204
0
      op &= UINT64_C(65535);
7205
0
      Value |= op;
7206
0
      break;
7207
0
    }
7208
0
    case Mips::EXTPDP_MM:
7209
0
    case Mips::EXTP_MM:
7210
0
    case Mips::EXTR_RS_W_MM:
7211
0
    case Mips::EXTR_R_W_MM:
7212
0
    case Mips::EXTR_S_H_MM:
7213
0
    case Mips::EXTR_W_MM: {
7214
      // op: rt
7215
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7216
0
      op &= UINT64_C(31);
7217
0
      op <<= 21;
7218
0
      Value |= op;
7219
      // op: imm
7220
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7221
0
      op &= UINT64_C(31);
7222
0
      op <<= 16;
7223
0
      Value |= op;
7224
      // op: ac
7225
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7226
0
      op &= UINT64_C(3);
7227
0
      op <<= 14;
7228
0
      Value |= op;
7229
0
      break;
7230
0
    }
7231
0
    case Mips::ADDIUPC_MMR6:
7232
0
    case Mips::LWPC_MMR6: {
7233
      // op: rt
7234
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7235
0
      op &= UINT64_C(31);
7236
0
      op <<= 21;
7237
0
      Value |= op;
7238
      // op: imm
7239
0
      op = getSimm19Lsl2Encoding(MI, 1, Fixups, STI);
7240
0
      op &= UINT64_C(524287);
7241
0
      Value |= op;
7242
0
      break;
7243
0
    }
7244
0
    case Mips::LUI_MMR6: {
7245
      // op: rt
7246
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7247
0
      op &= UINT64_C(31);
7248
0
      op <<= 21;
7249
0
      Value |= op;
7250
      // op: imm16
7251
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7252
0
      op &= UINT64_C(65535);
7253
0
      Value |= op;
7254
0
      break;
7255
0
    }
7256
0
    case Mips::CFC2_MM:
7257
0
    case Mips::MFC2_MMR6:
7258
0
    case Mips::MFHC2_MMR6: {
7259
      // op: rt
7260
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7261
0
      op &= UINT64_C(31);
7262
0
      op <<= 21;
7263
0
      Value |= op;
7264
      // op: impl
7265
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7266
0
      op &= UINT64_C(31);
7267
0
      op <<= 16;
7268
0
      Value |= op;
7269
0
      break;
7270
0
    }
7271
0
    case Mips::RDDSP_MM:
7272
0
    case Mips::WRDSP_MM: {
7273
      // op: rt
7274
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7275
0
      op &= UINT64_C(31);
7276
0
      op <<= 21;
7277
0
      Value |= op;
7278
      // op: mask
7279
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7280
0
      op &= UINT64_C(127);
7281
0
      op <<= 14;
7282
0
      Value |= op;
7283
0
      break;
7284
0
    }
7285
0
    case Mips::BGTZC_MMR6:
7286
0
    case Mips::BLEZC_MMR6: {
7287
      // op: rt
7288
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7289
0
      op &= UINT64_C(31);
7290
0
      op <<= 21;
7291
0
      Value |= op;
7292
      // op: offset
7293
0
      op = getBranchTargetOpValueLsl2MMR6(MI, 1, Fixups, STI);
7294
0
      op &= UINT64_C(65535);
7295
0
      Value |= op;
7296
0
      break;
7297
0
    }
7298
0
    case Mips::BEQZALC_MMR6:
7299
0
    case Mips::BGTZALC_MMR6:
7300
0
    case Mips::BLEZALC_MMR6:
7301
0
    case Mips::BNEZALC_MMR6: {
7302
      // op: rt
7303
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7304
0
      op &= UINT64_C(31);
7305
0
      op <<= 21;
7306
0
      Value |= op;
7307
      // op: offset
7308
0
      op = getBranchTargetOpValueMM(MI, 1, Fixups, STI);
7309
0
      op &= UINT64_C(65535);
7310
0
      Value |= op;
7311
0
      break;
7312
0
    }
7313
0
    case Mips::RDHWR_MM:
7314
0
    case Mips::RDPGPR_MMR6: {
7315
      // op: rt
7316
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7317
0
      op &= UINT64_C(31);
7318
0
      op <<= 21;
7319
0
      Value |= op;
7320
      // op: rd
7321
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7322
0
      op &= UINT64_C(31);
7323
0
      op <<= 16;
7324
0
      Value |= op;
7325
0
      break;
7326
0
    }
7327
0
    case Mips::ABSQ_S_PH_MM:
7328
0
    case Mips::ABSQ_S_QB_MMR2:
7329
0
    case Mips::ABSQ_S_W_MM:
7330
0
    case Mips::BITREV_MM:
7331
0
    case Mips::JALRC_HB_MMR6:
7332
0
    case Mips::JALRC_MMR6:
7333
0
    case Mips::PRECEQU_PH_QBLA_MM:
7334
0
    case Mips::PRECEQU_PH_QBL_MM:
7335
0
    case Mips::PRECEQU_PH_QBRA_MM:
7336
0
    case Mips::PRECEQU_PH_QBR_MM:
7337
0
    case Mips::PRECEQ_W_PHL_MM:
7338
0
    case Mips::PRECEQ_W_PHR_MM:
7339
0
    case Mips::PRECEU_PH_QBLA_MM:
7340
0
    case Mips::PRECEU_PH_QBL_MM:
7341
0
    case Mips::PRECEU_PH_QBRA_MM:
7342
0
    case Mips::PRECEU_PH_QBR_MM:
7343
0
    case Mips::RADDU_W_QB_MM:
7344
0
    case Mips::REPLV_PH_MM:
7345
0
    case Mips::REPLV_QB_MM:
7346
0
    case Mips::WRPGPR_MMR6:
7347
0
    case Mips::WSBH_MMR6: {
7348
      // op: rt
7349
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7350
0
      op &= UINT64_C(31);
7351
0
      op <<= 21;
7352
0
      Value |= op;
7353
      // op: rs
7354
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7355
0
      op &= UINT64_C(31);
7356
0
      op <<= 16;
7357
0
      Value |= op;
7358
0
      break;
7359
0
    }
7360
0
    case Mips::BALIGN_MMR2: {
7361
      // op: rt
7362
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7363
0
      op &= UINT64_C(31);
7364
0
      op <<= 21;
7365
0
      Value |= op;
7366
      // op: rs
7367
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7368
0
      op &= UINT64_C(31);
7369
0
      op <<= 16;
7370
0
      Value |= op;
7371
      // op: bp
7372
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7373
0
      op &= UINT64_C(3);
7374
0
      op <<= 14;
7375
0
      Value |= op;
7376
0
      break;
7377
0
    }
7378
0
    case Mips::ADDIU_MMR6:
7379
0
    case Mips::ANDI_MMR6:
7380
0
    case Mips::ORI_MMR6:
7381
0
    case Mips::SLTi_MM:
7382
0
    case Mips::SLTiu_MM:
7383
0
    case Mips::XORI_MMR6: {
7384
      // op: rt
7385
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7386
0
      op &= UINT64_C(31);
7387
0
      op <<= 21;
7388
0
      Value |= op;
7389
      // op: rs
7390
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7391
0
      op &= UINT64_C(31);
7392
0
      op <<= 16;
7393
0
      Value |= op;
7394
      // op: imm16
7395
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7396
0
      op &= UINT64_C(65535);
7397
0
      Value |= op;
7398
0
      break;
7399
0
    }
7400
0
    case Mips::BNVC_MMR6:
7401
0
    case Mips::BOVC_MMR6: {
7402
      // op: rt
7403
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7404
0
      op &= UINT64_C(31);
7405
0
      op <<= 21;
7406
0
      Value |= op;
7407
      // op: rs
7408
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7409
0
      op &= UINT64_C(31);
7410
0
      op <<= 16;
7411
0
      Value |= op;
7412
      // op: offset
7413
0
      op = getBranchTargetOpValueMMR6(MI, 2, Fixups, STI);
7414
0
      op &= UINT64_C(65535);
7415
0
      Value |= op;
7416
0
      break;
7417
0
    }
7418
0
    case Mips::INS_MM: {
7419
      // op: rt
7420
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7421
0
      op &= UINT64_C(31);
7422
0
      op <<= 21;
7423
0
      Value |= op;
7424
      // op: rs
7425
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7426
0
      op &= UINT64_C(31);
7427
0
      op <<= 16;
7428
0
      Value |= op;
7429
      // op: pos
7430
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7431
0
      op &= UINT64_C(31);
7432
0
      op <<= 6;
7433
0
      Value |= op;
7434
      // op: size
7435
0
      op = getSizeInsEncoding(MI, 3, Fixups, STI);
7436
0
      op &= UINT64_C(31);
7437
0
      op <<= 11;
7438
0
      Value |= op;
7439
0
      break;
7440
0
    }
7441
0
    case Mips::EXT_MM: {
7442
      // op: rt
7443
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7444
0
      op &= UINT64_C(31);
7445
0
      op <<= 21;
7446
0
      Value |= op;
7447
      // op: rs
7448
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7449
0
      op &= UINT64_C(31);
7450
0
      op <<= 16;
7451
0
      Value |= op;
7452
      // op: pos
7453
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7454
0
      op &= UINT64_C(31);
7455
0
      op <<= 6;
7456
0
      Value |= op;
7457
      // op: size
7458
0
      op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
7459
0
      op &= UINT64_C(31);
7460
0
      op <<= 11;
7461
0
      Value |= op;
7462
0
      break;
7463
0
    }
7464
0
    case Mips::SHLL_PH_MM:
7465
0
    case Mips::SHLL_S_PH_MM:
7466
0
    case Mips::SHRA_PH_MM:
7467
0
    case Mips::SHRA_R_PH_MM:
7468
0
    case Mips::SHRL_PH_MMR2: {
7469
      // op: rt
7470
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7471
0
      op &= UINT64_C(31);
7472
0
      op <<= 21;
7473
0
      Value |= op;
7474
      // op: rs
7475
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7476
0
      op &= UINT64_C(31);
7477
0
      op <<= 16;
7478
0
      Value |= op;
7479
      // op: sa
7480
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7481
0
      op &= UINT64_C(15);
7482
0
      op <<= 12;
7483
0
      Value |= op;
7484
0
      break;
7485
0
    }
7486
0
    case Mips::APPEND_MMR2:
7487
0
    case Mips::PRECR_SRA_PH_W_MMR2:
7488
0
    case Mips::PRECR_SRA_R_PH_W_MMR2:
7489
0
    case Mips::PREPEND_MMR2:
7490
0
    case Mips::SHLL_S_W_MM:
7491
0
    case Mips::SHRA_R_W_MM: {
7492
      // op: rt
7493
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7494
0
      op &= UINT64_C(31);
7495
0
      op <<= 21;
7496
0
      Value |= op;
7497
      // op: rs
7498
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7499
0
      op &= UINT64_C(31);
7500
0
      op <<= 16;
7501
0
      Value |= op;
7502
      // op: sa
7503
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7504
0
      op &= UINT64_C(31);
7505
0
      op <<= 11;
7506
0
      Value |= op;
7507
0
      break;
7508
0
    }
7509
0
    case Mips::SHLL_QB_MM:
7510
0
    case Mips::SHRA_QB_MMR2:
7511
0
    case Mips::SHRA_R_QB_MMR2:
7512
0
    case Mips::SHRL_QB_MM: {
7513
      // op: rt
7514
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7515
0
      op &= UINT64_C(31);
7516
0
      op <<= 21;
7517
0
      Value |= op;
7518
      // op: rs
7519
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7520
0
      op &= UINT64_C(31);
7521
0
      op <<= 16;
7522
0
      Value |= op;
7523
      // op: sa
7524
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7525
0
      op &= UINT64_C(7);
7526
0
      op <<= 13;
7527
0
      Value |= op;
7528
0
      break;
7529
0
    }
7530
0
    case Mips::MFC0_MMR6:
7531
0
    case Mips::MFGC0_MM:
7532
0
    case Mips::MFHC0_MMR6:
7533
0
    case Mips::MFHGC0_MM:
7534
0
    case Mips::RDHWR_MMR6: {
7535
      // op: rt
7536
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7537
0
      op &= UINT64_C(31);
7538
0
      op <<= 21;
7539
0
      Value |= op;
7540
      // op: rs
7541
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7542
0
      op &= UINT64_C(31);
7543
0
      op <<= 16;
7544
0
      Value |= op;
7545
      // op: sel
7546
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7547
0
      op &= UINT64_C(7);
7548
0
      op <<= 11;
7549
0
      Value |= op;
7550
0
      break;
7551
0
    }
7552
0
    case Mips::INS_MMR6: {
7553
      // op: rt
7554
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7555
0
      op &= UINT64_C(31);
7556
0
      op <<= 21;
7557
0
      Value |= op;
7558
      // op: rs
7559
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7560
0
      op &= UINT64_C(31);
7561
0
      op <<= 16;
7562
0
      Value |= op;
7563
      // op: size
7564
0
      op = getSizeInsEncoding(MI, 3, Fixups, STI);
7565
0
      op &= UINT64_C(31);
7566
0
      op <<= 11;
7567
0
      Value |= op;
7568
      // op: pos
7569
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7570
0
      op &= UINT64_C(31);
7571
0
      op <<= 6;
7572
0
      Value |= op;
7573
0
      break;
7574
0
    }
7575
0
    case Mips::EXT_MMR6: {
7576
      // op: rt
7577
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7578
0
      op &= UINT64_C(31);
7579
0
      op <<= 21;
7580
0
      Value |= op;
7581
      // op: rs
7582
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7583
0
      op &= UINT64_C(31);
7584
0
      op <<= 16;
7585
0
      Value |= op;
7586
      // op: size
7587
0
      op = getUImmWithOffsetEncoding<5, 1>(MI, 3, Fixups, STI);
7588
0
      op &= UINT64_C(31);
7589
0
      op <<= 11;
7590
0
      Value |= op;
7591
      // op: pos
7592
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7593
0
      op &= UINT64_C(31);
7594
0
      op <<= 6;
7595
0
      Value |= op;
7596
0
      break;
7597
0
    }
7598
0
    case Mips::INSV_MM: {
7599
      // op: rt
7600
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7601
0
      op &= UINT64_C(31);
7602
0
      op <<= 21;
7603
0
      Value |= op;
7604
      // op: rs
7605
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7606
0
      op &= UINT64_C(31);
7607
0
      op <<= 16;
7608
0
      Value |= op;
7609
0
      break;
7610
0
    }
7611
0
    case Mips::EXTPDPV_MM:
7612
0
    case Mips::EXTPV_MM:
7613
0
    case Mips::EXTRV_RS_W_MM:
7614
0
    case Mips::EXTRV_R_W_MM:
7615
0
    case Mips::EXTRV_S_H_MM:
7616
0
    case Mips::EXTRV_W_MM: {
7617
      // op: rt
7618
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7619
0
      op &= UINT64_C(31);
7620
0
      op <<= 21;
7621
0
      Value |= op;
7622
      // op: rs
7623
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7624
0
      op &= UINT64_C(31);
7625
0
      op <<= 16;
7626
0
      Value |= op;
7627
      // op: ac
7628
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7629
0
      op &= UINT64_C(3);
7630
0
      op <<= 14;
7631
0
      Value |= op;
7632
0
      break;
7633
0
    }
7634
0
    case Mips::LWSP_MM:
7635
0
    case Mips::SWSP_MM:
7636
0
    case Mips::SWSP_MMR6: {
7637
      // op: rt
7638
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7639
0
      op &= UINT64_C(31);
7640
0
      op <<= 5;
7641
0
      Value |= op;
7642
      // op: offset
7643
0
      op = getMemEncodingMMSPImm5Lsl2(MI, 1, Fixups, STI);
7644
0
      op &= UINT64_C(31);
7645
0
      Value |= op;
7646
0
      break;
7647
0
    }
7648
0
    case Mips::NOT16_MM: {
7649
      // op: rt
7650
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7651
0
      op &= UINT64_C(7);
7652
0
      op <<= 3;
7653
0
      Value |= op;
7654
      // op: rs
7655
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7656
0
      op &= UINT64_C(7);
7657
0
      Value |= op;
7658
0
      break;
7659
0
    }
7660
0
    case Mips::LBU16_MM:
7661
0
    case Mips::SB16_MM:
7662
0
    case Mips::SB16_MMR6: {
7663
      // op: rt
7664
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7665
0
      op &= UINT64_C(7);
7666
0
      op <<= 7;
7667
0
      Value |= op;
7668
      // op: addr
7669
0
      op = getMemEncodingMMImm4(MI, 1, Fixups, STI);
7670
0
      op &= UINT64_C(127);
7671
0
      Value |= op;
7672
0
      break;
7673
0
    }
7674
0
    case Mips::LHU16_MM:
7675
0
    case Mips::SH16_MM:
7676
0
    case Mips::SH16_MMR6: {
7677
      // op: rt
7678
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7679
0
      op &= UINT64_C(7);
7680
0
      op <<= 7;
7681
0
      Value |= op;
7682
      // op: addr
7683
0
      op = getMemEncodingMMImm4Lsl1(MI, 1, Fixups, STI);
7684
0
      op &= UINT64_C(127);
7685
0
      Value |= op;
7686
0
      break;
7687
0
    }
7688
0
    case Mips::LW16_MM:
7689
0
    case Mips::SW16_MM:
7690
0
    case Mips::SW16_MMR6: {
7691
      // op: rt
7692
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7693
0
      op &= UINT64_C(7);
7694
0
      op <<= 7;
7695
0
      Value |= op;
7696
      // op: addr
7697
0
      op = getMemEncodingMMImm4Lsl2(MI, 1, Fixups, STI);
7698
0
      op &= UINT64_C(127);
7699
0
      Value |= op;
7700
0
      break;
7701
0
    }
7702
0
    case Mips::LWGP_MM: {
7703
      // op: rt
7704
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7705
0
      op &= UINT64_C(7);
7706
0
      op <<= 7;
7707
0
      Value |= op;
7708
      // op: offset
7709
0
      op = getMemEncodingMMGPImm7Lsl2(MI, 1, Fixups, STI);
7710
0
      op &= UINT64_C(127);
7711
0
      Value |= op;
7712
0
      break;
7713
0
    }
7714
0
    case Mips::NOT16_MMR6: {
7715
      // op: rt
7716
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7717
0
      op &= UINT64_C(7);
7718
0
      op <<= 7;
7719
0
      Value |= op;
7720
      // op: rs
7721
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7722
0
      op &= UINT64_C(7);
7723
0
      op <<= 4;
7724
0
      Value |= op;
7725
0
      break;
7726
0
    }
7727
0
    case Mips::SC64_R6:
7728
0
    case Mips::SCD_R6:
7729
0
    case Mips::SC_R6: {
7730
      // op: rt
7731
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7732
0
      op &= UINT64_C(31);
7733
0
      op <<= 16;
7734
0
      Value |= op;
7735
      // op: addr
7736
0
      op = getMemEncoding(MI, 2, Fixups, STI);
7737
0
      Value |= (op & UINT64_C(2031616)) << 5;
7738
0
      Value |= (op & UINT64_C(511)) << 7;
7739
0
      break;
7740
0
    }
7741
0
    case Mips::SC:
7742
0
    case Mips::SC64:
7743
0
    case Mips::SCD: {
7744
      // op: rt
7745
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7746
0
      op &= UINT64_C(31);
7747
0
      op <<= 16;
7748
0
      Value |= op;
7749
      // op: addr
7750
0
      op = getMemEncoding(MI, 2, Fixups, STI);
7751
0
      Value |= (op & UINT64_C(2031616)) << 5;
7752
0
      Value |= (op & UINT64_C(65535));
7753
0
      break;
7754
0
    }
7755
0
    case Mips::CTC1:
7756
0
    case Mips::DMTC1:
7757
0
    case Mips::MTC1:
7758
0
    case Mips::MTC1_D64: {
7759
      // op: rt
7760
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7761
0
      op &= UINT64_C(31);
7762
0
      op <<= 16;
7763
0
      Value |= op;
7764
      // op: fs
7765
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7766
0
      op &= UINT64_C(31);
7767
0
      op <<= 11;
7768
0
      Value |= op;
7769
0
      break;
7770
0
    }
7771
0
    case Mips::DMTC0:
7772
0
    case Mips::DMTC2:
7773
0
    case Mips::DMTGC0:
7774
0
    case Mips::MTC0:
7775
0
    case Mips::MTC2:
7776
0
    case Mips::MTGC0:
7777
0
    case Mips::MTHGC0: {
7778
      // op: rt
7779
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7780
0
      op &= UINT64_C(31);
7781
0
      op <<= 16;
7782
0
      Value |= op;
7783
      // op: rd
7784
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7785
0
      op &= UINT64_C(31);
7786
0
      op <<= 11;
7787
0
      Value |= op;
7788
      // op: sel
7789
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7790
0
      op &= UINT64_C(7);
7791
0
      Value |= op;
7792
0
      break;
7793
0
    }
7794
0
    case Mips::MFTR:
7795
0
    case Mips::MTTR: {
7796
      // op: rt
7797
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7798
0
      op &= UINT64_C(31);
7799
0
      op <<= 16;
7800
0
      Value |= op;
7801
      // op: rd
7802
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7803
0
      op &= UINT64_C(31);
7804
0
      op <<= 11;
7805
0
      Value |= op;
7806
      // op: u
7807
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7808
0
      op &= UINT64_C(1);
7809
0
      op <<= 5;
7810
0
      Value |= op;
7811
      // op: h
7812
0
      op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI);
7813
0
      op &= UINT64_C(1);
7814
0
      op <<= 4;
7815
0
      Value |= op;
7816
      // op: sel
7817
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
7818
0
      op &= UINT64_C(7);
7819
0
      Value |= op;
7820
0
      break;
7821
0
    }
7822
0
    case Mips::SCE_MM: {
7823
      // op: rt
7824
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7825
0
      op &= UINT64_C(31);
7826
0
      op <<= 21;
7827
0
      Value |= op;
7828
      // op: addr
7829
0
      op = getMemEncoding(MI, 2, Fixups, STI);
7830
0
      Value |= (op & UINT64_C(2031616));
7831
0
      Value |= (op & UINT64_C(511));
7832
0
      break;
7833
0
    }
7834
0
    case Mips::SC_MM: {
7835
      // op: rt
7836
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7837
0
      op &= UINT64_C(31);
7838
0
      op <<= 21;
7839
0
      Value |= op;
7840
      // op: addr
7841
0
      op = getMemEncodingMMImm12(MI, 2, Fixups, STI);
7842
0
      Value |= (op & UINT64_C(2031616));
7843
0
      Value |= (op & UINT64_C(4095));
7844
0
      break;
7845
0
    }
7846
0
    case Mips::SC_MMR6: {
7847
      // op: rt
7848
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7849
0
      op &= UINT64_C(31);
7850
0
      op <<= 21;
7851
0
      Value |= op;
7852
      // op: addr
7853
0
      op = getMemEncodingMMImm9(MI, 2, Fixups, STI);
7854
0
      Value |= (op & UINT64_C(2031616));
7855
0
      Value |= (op & UINT64_C(511));
7856
0
      break;
7857
0
    }
7858
0
    case Mips::CTC1_MM:
7859
0
    case Mips::MTC1_D64_MM:
7860
0
    case Mips::MTC1_MM:
7861
0
    case Mips::MTC1_MMR6: {
7862
      // op: rt
7863
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7864
0
      op &= UINT64_C(31);
7865
0
      op <<= 21;
7866
0
      Value |= op;
7867
      // op: fs
7868
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7869
0
      op &= UINT64_C(31);
7870
0
      op <<= 16;
7871
0
      Value |= op;
7872
0
      break;
7873
0
    }
7874
0
    case Mips::CTC2_MM:
7875
0
    case Mips::MTC2_MMR6:
7876
0
    case Mips::MTHC2_MMR6: {
7877
      // op: rt
7878
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7879
0
      op &= UINT64_C(31);
7880
0
      op <<= 21;
7881
0
      Value |= op;
7882
      // op: impl
7883
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7884
0
      op &= UINT64_C(31);
7885
0
      op <<= 16;
7886
0
      Value |= op;
7887
0
      break;
7888
0
    }
7889
0
    case Mips::CMPU_EQ_QB_MM:
7890
0
    case Mips::CMPU_LE_QB_MM:
7891
0
    case Mips::CMPU_LT_QB_MM:
7892
0
    case Mips::CMP_EQ_PH_MM:
7893
0
    case Mips::CMP_LE_PH_MM:
7894
0
    case Mips::CMP_LT_PH_MM: {
7895
      // op: rt
7896
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7897
0
      op &= UINT64_C(31);
7898
0
      op <<= 21;
7899
0
      Value |= op;
7900
      // op: rs
7901
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7902
0
      op &= UINT64_C(31);
7903
0
      op <<= 16;
7904
0
      Value |= op;
7905
0
      break;
7906
0
    }
7907
0
    case Mips::BEQC_MMR6:
7908
0
    case Mips::BGEC_MMR6:
7909
0
    case Mips::BGEUC_MMR6:
7910
0
    case Mips::BLTC_MMR6:
7911
0
    case Mips::BLTUC_MMR6:
7912
0
    case Mips::BNEC_MMR6: {
7913
      // op: rt
7914
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7915
0
      op &= UINT64_C(31);
7916
0
      op <<= 21;
7917
0
      Value |= op;
7918
      // op: rs
7919
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7920
0
      op &= UINT64_C(31);
7921
0
      op <<= 16;
7922
0
      Value |= op;
7923
      // op: offset
7924
0
      op = getBranchTargetOpValueLsl2MMR6(MI, 2, Fixups, STI);
7925
0
      op &= UINT64_C(65535);
7926
0
      Value |= op;
7927
0
      break;
7928
0
    }
7929
0
    case Mips::MTC0_MMR6:
7930
0
    case Mips::MTGC0_MM:
7931
0
    case Mips::MTHC0_MMR6:
7932
0
    case Mips::MTHGC0_MM: {
7933
      // op: rt
7934
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7935
0
      op &= UINT64_C(31);
7936
0
      op <<= 21;
7937
0
      Value |= op;
7938
      // op: rs
7939
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7940
0
      op &= UINT64_C(31);
7941
0
      op <<= 16;
7942
0
      Value |= op;
7943
      // op: sel
7944
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7945
0
      op &= UINT64_C(7);
7946
0
      op <<= 11;
7947
0
      Value |= op;
7948
0
      break;
7949
0
    }
7950
0
    case Mips::MTHC1_D32:
7951
0
    case Mips::MTHC1_D64: {
7952
      // op: rt
7953
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7954
0
      op &= UINT64_C(31);
7955
0
      op <<= 16;
7956
0
      Value |= op;
7957
      // op: fs
7958
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7959
0
      op &= UINT64_C(31);
7960
0
      op <<= 11;
7961
0
      Value |= op;
7962
0
      break;
7963
0
    }
7964
0
    case Mips::SPLAT_B:
7965
0
    case Mips::SPLAT_D:
7966
0
    case Mips::SPLAT_H:
7967
0
    case Mips::SPLAT_W: {
7968
      // op: rt
7969
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7970
0
      op &= UINT64_C(31);
7971
0
      op <<= 16;
7972
0
      Value |= op;
7973
      // op: ws
7974
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
7975
0
      op &= UINT64_C(31);
7976
0
      op <<= 11;
7977
0
      Value |= op;
7978
      // op: wd
7979
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7980
0
      op &= UINT64_C(31);
7981
0
      op <<= 6;
7982
0
      Value |= op;
7983
0
      break;
7984
0
    }
7985
0
    case Mips::MTHC1_D32_MM:
7986
0
    case Mips::MTHC1_D64_MM: {
7987
      // op: rt
7988
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
7989
0
      op &= UINT64_C(31);
7990
0
      op <<= 21;
7991
0
      Value |= op;
7992
      // op: fs
7993
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
7994
0
      op &= UINT64_C(31);
7995
0
      op <<= 16;
7996
0
      Value |= op;
7997
0
      break;
7998
0
    }
7999
0
    case Mips::DPAQX_SA_W_PH_MMR2:
8000
0
    case Mips::DPAQX_S_W_PH_MMR2:
8001
0
    case Mips::DPAQ_SA_L_W_MM:
8002
0
    case Mips::DPAQ_S_W_PH_MM:
8003
0
    case Mips::DPAU_H_QBL_MM:
8004
0
    case Mips::DPAU_H_QBR_MM:
8005
0
    case Mips::DPAX_W_PH_MMR2:
8006
0
    case Mips::DPA_W_PH_MMR2:
8007
0
    case Mips::DPSQX_SA_W_PH_MMR2:
8008
0
    case Mips::DPSQX_S_W_PH_MMR2:
8009
0
    case Mips::DPSQ_SA_L_W_MM:
8010
0
    case Mips::DPSQ_S_W_PH_MM:
8011
0
    case Mips::DPSU_H_QBL_MM:
8012
0
    case Mips::DPSU_H_QBR_MM:
8013
0
    case Mips::DPSX_W_PH_MMR2:
8014
0
    case Mips::DPS_W_PH_MMR2:
8015
0
    case Mips::MADDU_DSP_MM:
8016
0
    case Mips::MADD_DSP_MM:
8017
0
    case Mips::MAQ_SA_W_PHL_MM:
8018
0
    case Mips::MAQ_SA_W_PHR_MM:
8019
0
    case Mips::MAQ_S_W_PHL_MM:
8020
0
    case Mips::MAQ_S_W_PHR_MM:
8021
0
    case Mips::MSUBU_DSP_MM:
8022
0
    case Mips::MSUB_DSP_MM:
8023
0
    case Mips::MULSAQ_S_W_PH_MM:
8024
0
    case Mips::MULSA_W_PH_MMR2:
8025
0
    case Mips::MULTU_DSP_MM:
8026
0
    case Mips::MULT_DSP_MM: {
8027
      // op: rt
8028
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8029
0
      op &= UINT64_C(31);
8030
0
      op <<= 21;
8031
0
      Value |= op;
8032
      // op: rs
8033
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8034
0
      op &= UINT64_C(31);
8035
0
      op <<= 16;
8036
0
      Value |= op;
8037
      // op: ac
8038
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8039
0
      op &= UINT64_C(3);
8040
0
      op <<= 14;
8041
0
      Value |= op;
8042
0
      break;
8043
0
    }
8044
0
    case Mips::ADD_MM:
8045
0
    case Mips::ADDu_MM:
8046
0
    case Mips::AND_MM:
8047
0
    case Mips::CMPGU_EQ_QB_MM:
8048
0
    case Mips::CMPGU_LE_QB_MM:
8049
0
    case Mips::CMPGU_LT_QB_MM:
8050
0
    case Mips::MOVN_I_MM:
8051
0
    case Mips::MOVZ_I_MM:
8052
0
    case Mips::MUL_MM:
8053
0
    case Mips::NOR_MM:
8054
0
    case Mips::OR_MM:
8055
0
    case Mips::SLT_MM:
8056
0
    case Mips::SLTu_MM:
8057
0
    case Mips::SUB_MM:
8058
0
    case Mips::SUBu_MM:
8059
0
    case Mips::XOR_MM: {
8060
      // op: rt
8061
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8062
0
      op &= UINT64_C(31);
8063
0
      op <<= 21;
8064
0
      Value |= op;
8065
      // op: rs
8066
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8067
0
      op &= UINT64_C(31);
8068
0
      op <<= 16;
8069
0
      Value |= op;
8070
      // op: rd
8071
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8072
0
      op &= UINT64_C(31);
8073
0
      op <<= 11;
8074
0
      Value |= op;
8075
0
      break;
8076
0
    }
8077
0
    case Mips::AND16_MM:
8078
0
    case Mips::OR16_MM:
8079
0
    case Mips::XOR16_MM: {
8080
      // op: rt
8081
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8082
0
      op &= UINT64_C(7);
8083
0
      op <<= 3;
8084
0
      Value |= op;
8085
      // op: rs
8086
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8087
0
      op &= UINT64_C(7);
8088
0
      Value |= op;
8089
0
      break;
8090
0
    }
8091
0
    case Mips::AND16_MMR6:
8092
0
    case Mips::OR16_MMR6:
8093
0
    case Mips::XOR16_MMR6: {
8094
      // op: rt
8095
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8096
0
      op &= UINT64_C(7);
8097
0
      op <<= 7;
8098
0
      Value |= op;
8099
      // op: rs
8100
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8101
0
      op &= UINT64_C(7);
8102
0
      op <<= 4;
8103
0
      Value |= op;
8104
0
      break;
8105
0
    }
8106
0
    case Mips::SLD_B:
8107
0
    case Mips::SLD_D:
8108
0
    case Mips::SLD_H:
8109
0
    case Mips::SLD_W: {
8110
      // op: rt
8111
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8112
0
      op &= UINT64_C(31);
8113
0
      op <<= 16;
8114
0
      Value |= op;
8115
      // op: ws
8116
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8117
0
      op &= UINT64_C(31);
8118
0
      op <<= 11;
8119
0
      Value |= op;
8120
      // op: wd
8121
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8122
0
      op &= UINT64_C(31);
8123
0
      op <<= 6;
8124
0
      Value |= op;
8125
0
      break;
8126
0
    }
8127
0
    case Mips::MOVEP_MMR6: {
8128
      // op: rt
8129
0
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
8130
0
      op &= UINT64_C(7);
8131
0
      op <<= 4;
8132
0
      Value |= op;
8133
      // op: rs
8134
0
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
8135
0
      Value |= (op & UINT64_C(4)) << 1;
8136
0
      Value |= (op & UINT64_C(3));
8137
0
      break;
8138
0
    }
8139
0
    case Mips::MOVEP_MM: {
8140
      // op: rt
8141
0
      op = getMovePRegSingleOpValue(MI, 3, Fixups, STI);
8142
0
      op &= UINT64_C(7);
8143
0
      op <<= 4;
8144
0
      Value |= op;
8145
      // op: rs
8146
0
      op = getMovePRegSingleOpValue(MI, 2, Fixups, STI);
8147
0
      op &= UINT64_C(7);
8148
0
      op <<= 1;
8149
0
      Value |= op;
8150
0
      break;
8151
0
    }
8152
0
    case Mips::LWM32_MM:
8153
0
    case Mips::SWM32_MM: {
8154
      // op: rt
8155
0
      op = getRegisterListOpValue(MI, 0, Fixups, STI);
8156
0
      op &= UINT64_C(31);
8157
0
      op <<= 21;
8158
0
      Value |= op;
8159
      // op: addr
8160
0
      op = getMemEncodingMMImm12(MI, 1, Fixups, STI);
8161
0
      Value |= (op & UINT64_C(2031616));
8162
0
      Value |= (op & UINT64_C(4095));
8163
0
      break;
8164
0
    }
8165
0
    case Mips::LWM16_MM:
8166
0
    case Mips::SWM16_MM: {
8167
      // op: rt
8168
0
      op = getRegisterListOpValue16(MI, 0, Fixups, STI);
8169
0
      op &= UINT64_C(3);
8170
0
      op <<= 4;
8171
0
      Value |= op;
8172
      // op: addr
8173
0
      op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI);
8174
0
      op &= UINT64_C(15);
8175
0
      Value |= op;
8176
0
      break;
8177
0
    }
8178
0
    case Mips::LWM16_MMR6:
8179
0
    case Mips::SWM16_MMR6: {
8180
      // op: rt
8181
0
      op = getRegisterListOpValue16(MI, 0, Fixups, STI);
8182
0
      op &= UINT64_C(3);
8183
0
      op <<= 8;
8184
0
      Value |= op;
8185
      // op: addr
8186
0
      op = getMemEncodingMMImm4sp(MI, 1, Fixups, STI);
8187
0
      op &= UINT64_C(15);
8188
0
      op <<= 4;
8189
0
      Value |= op;
8190
0
      break;
8191
0
    }
8192
0
    case Mips::JumpLinkReg16:
8193
0
    case Mips::Mfhi16:
8194
0
    case Mips::Mflo16:
8195
0
    case Mips::SebRx16:
8196
0
    case Mips::SehRx16: {
8197
      // op: rx
8198
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8199
0
      op &= UINT64_C(7);
8200
0
      op <<= 8;
8201
0
      Value |= op;
8202
0
      break;
8203
0
    }
8204
0
    case Mips::BeqzRxImm16:
8205
0
    case Mips::BnezRxImm16: {
8206
      // op: rx
8207
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8208
0
      op &= UINT64_C(7);
8209
0
      op <<= 8;
8210
0
      Value |= op;
8211
      // op: imm8
8212
0
      op = getBranchTargetOpValue(MI, 1, Fixups, STI);
8213
0
      op &= UINT64_C(255);
8214
0
      Value |= op;
8215
0
      break;
8216
0
    }
8217
0
    case Mips::CmpiRxImm16:
8218
0
    case Mips::LiRxImm16:
8219
0
    case Mips::LwRxPcTcp16:
8220
0
    case Mips::SltiRxImm16:
8221
0
    case Mips::SltiuRxImm16: {
8222
      // op: rx
8223
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8224
0
      op &= UINT64_C(7);
8225
0
      op <<= 8;
8226
0
      Value |= op;
8227
      // op: imm8
8228
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8229
0
      op &= UINT64_C(255);
8230
0
      Value |= op;
8231
0
      break;
8232
0
    }
8233
0
    case Mips::AddiuRxRxImm16: {
8234
      // op: rx
8235
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8236
0
      op &= UINT64_C(7);
8237
0
      op <<= 8;
8238
0
      Value |= op;
8239
      // op: imm8
8240
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8241
0
      op &= UINT64_C(255);
8242
0
      Value |= op;
8243
0
      break;
8244
0
    }
8245
0
    case Mips::CmpRxRy16:
8246
0
    case Mips::DivRxRy16:
8247
0
    case Mips::DivuRxRy16:
8248
0
    case Mips::NegRxRy16:
8249
0
    case Mips::NotRxRy16:
8250
0
    case Mips::SltRxRy16:
8251
0
    case Mips::SltuRxRy16: {
8252
      // op: rx
8253
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8254
0
      op &= UINT64_C(7);
8255
0
      op <<= 8;
8256
0
      Value |= op;
8257
      // op: ry
8258
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8259
0
      op &= UINT64_C(7);
8260
0
      op <<= 5;
8261
0
      Value |= op;
8262
0
      break;
8263
0
    }
8264
0
    case Mips::AndRxRxRy16:
8265
0
    case Mips::OrRxRxRy16:
8266
0
    case Mips::SllvRxRy16:
8267
0
    case Mips::SravRxRy16:
8268
0
    case Mips::SrlvRxRy16:
8269
0
    case Mips::XorRxRxRy16: {
8270
      // op: rx
8271
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8272
0
      op &= UINT64_C(7);
8273
0
      op <<= 8;
8274
0
      Value |= op;
8275
      // op: ry
8276
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8277
0
      op &= UINT64_C(7);
8278
0
      op <<= 5;
8279
0
      Value |= op;
8280
0
      break;
8281
0
    }
8282
0
    case Mips::AdduRxRyRz16:
8283
0
    case Mips::SubuRxRyRz16: {
8284
      // op: rx
8285
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8286
0
      op &= UINT64_C(7);
8287
0
      op <<= 8;
8288
0
      Value |= op;
8289
      // op: ry
8290
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8291
0
      op &= UINT64_C(7);
8292
0
      op <<= 5;
8293
0
      Value |= op;
8294
      // op: rz
8295
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8296
0
      op &= UINT64_C(7);
8297
0
      op <<= 2;
8298
0
      Value |= op;
8299
0
      break;
8300
0
    }
8301
0
    case Mips::MoveR3216: {
8302
      // op: ry
8303
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8304
0
      op &= UINT64_C(15);
8305
0
      op <<= 4;
8306
0
      Value |= op;
8307
      // op: r32
8308
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8309
0
      op &= UINT64_C(15);
8310
0
      Value |= op;
8311
0
      break;
8312
0
    }
8313
0
    case Mips::LDI_B:
8314
0
    case Mips::LDI_D:
8315
0
    case Mips::LDI_H:
8316
0
    case Mips::LDI_W: {
8317
      // op: s10
8318
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8319
0
      op &= UINT64_C(1023);
8320
0
      op <<= 11;
8321
0
      Value |= op;
8322
      // op: wd
8323
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8324
0
      op &= UINT64_C(31);
8325
0
      op <<= 6;
8326
0
      Value |= op;
8327
0
      break;
8328
0
    }
8329
0
    case Mips::SllX16:
8330
0
    case Mips::SraX16:
8331
0
    case Mips::SrlX16: {
8332
      // op: sa6
8333
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8334
0
      Value |= (op & UINT64_C(31)) << 22;
8335
0
      Value |= (op & UINT64_C(32)) << 16;
8336
      // op: rx
8337
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8338
0
      op &= UINT64_C(7);
8339
0
      op <<= 8;
8340
0
      Value |= op;
8341
      // op: ry
8342
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8343
0
      op &= UINT64_C(7);
8344
0
      op <<= 5;
8345
0
      Value |= op;
8346
0
      break;
8347
0
    }
8348
0
    case Mips::SHILO_MM: {
8349
      // op: shift
8350
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8351
0
      op &= UINT64_C(63);
8352
0
      op <<= 16;
8353
0
      Value |= op;
8354
      // op: ac
8355
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8356
0
      op &= UINT64_C(3);
8357
0
      op <<= 14;
8358
0
      Value |= op;
8359
0
      break;
8360
0
    }
8361
0
    case Mips::SYNC_MM:
8362
0
    case Mips::SYNC_MMR6: {
8363
      // op: stype
8364
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8365
0
      op &= UINT64_C(31);
8366
0
      op <<= 16;
8367
0
      Value |= op;
8368
0
      break;
8369
0
    }
8370
0
    case Mips::SYNC: {
8371
      // op: stype
8372
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8373
0
      op &= UINT64_C(31);
8374
0
      op <<= 6;
8375
0
      Value |= op;
8376
0
      break;
8377
0
    }
8378
0
    case Mips::J:
8379
0
    case Mips::JAL:
8380
0
    case Mips::JALX:
8381
0
    case Mips::JALX_MM: {
8382
      // op: target
8383
0
      op = getJumpTargetOpValue(MI, 0, Fixups, STI);
8384
0
      op &= UINT64_C(67108863);
8385
0
      Value |= op;
8386
0
      break;
8387
0
    }
8388
0
    case Mips::JALS_MM:
8389
0
    case Mips::JAL_MM:
8390
0
    case Mips::J_MM: {
8391
      // op: target
8392
0
      op = getJumpTargetOpValueMM(MI, 0, Fixups, STI);
8393
0
      op &= UINT64_C(67108863);
8394
0
      Value |= op;
8395
0
      break;
8396
0
    }
8397
0
    case Mips::ANDI_B:
8398
0
    case Mips::NORI_B:
8399
0
    case Mips::ORI_B:
8400
0
    case Mips::SHF_B:
8401
0
    case Mips::SHF_H:
8402
0
    case Mips::SHF_W:
8403
0
    case Mips::XORI_B: {
8404
      // op: u8
8405
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8406
0
      op &= UINT64_C(255);
8407
0
      op <<= 16;
8408
0
      Value |= op;
8409
      // op: ws
8410
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8411
0
      op &= UINT64_C(31);
8412
0
      op <<= 11;
8413
0
      Value |= op;
8414
      // op: wd
8415
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8416
0
      op &= UINT64_C(31);
8417
0
      op <<= 6;
8418
0
      Value |= op;
8419
0
      break;
8420
0
    }
8421
0
    case Mips::BMNZI_B:
8422
0
    case Mips::BMZI_B:
8423
0
    case Mips::BSELI_B: {
8424
      // op: u8
8425
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8426
0
      op &= UINT64_C(255);
8427
0
      op <<= 16;
8428
0
      Value |= op;
8429
      // op: ws
8430
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8431
0
      op &= UINT64_C(31);
8432
0
      op <<= 11;
8433
0
      Value |= op;
8434
      // op: wd
8435
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8436
0
      op &= UINT64_C(31);
8437
0
      op <<= 6;
8438
0
      Value |= op;
8439
0
      break;
8440
0
    }
8441
0
    case Mips::FCLASS_D:
8442
0
    case Mips::FCLASS_W:
8443
0
    case Mips::FEXUPL_D:
8444
0
    case Mips::FEXUPL_W:
8445
0
    case Mips::FEXUPR_D:
8446
0
    case Mips::FEXUPR_W:
8447
0
    case Mips::FFINT_S_D:
8448
0
    case Mips::FFINT_S_W:
8449
0
    case Mips::FFINT_U_D:
8450
0
    case Mips::FFINT_U_W:
8451
0
    case Mips::FFQL_D:
8452
0
    case Mips::FFQL_W:
8453
0
    case Mips::FFQR_D:
8454
0
    case Mips::FFQR_W:
8455
0
    case Mips::FLOG2_D:
8456
0
    case Mips::FLOG2_W:
8457
0
    case Mips::FRCP_D:
8458
0
    case Mips::FRCP_W:
8459
0
    case Mips::FRINT_D:
8460
0
    case Mips::FRINT_W:
8461
0
    case Mips::FRSQRT_D:
8462
0
    case Mips::FRSQRT_W:
8463
0
    case Mips::FSQRT_D:
8464
0
    case Mips::FSQRT_W:
8465
0
    case Mips::FTINT_S_D:
8466
0
    case Mips::FTINT_S_W:
8467
0
    case Mips::FTINT_U_D:
8468
0
    case Mips::FTINT_U_W:
8469
0
    case Mips::FTRUNC_S_D:
8470
0
    case Mips::FTRUNC_S_W:
8471
0
    case Mips::FTRUNC_U_D:
8472
0
    case Mips::FTRUNC_U_W:
8473
0
    case Mips::MOVE_V:
8474
0
    case Mips::NLOC_B:
8475
0
    case Mips::NLOC_D:
8476
0
    case Mips::NLOC_H:
8477
0
    case Mips::NLOC_W:
8478
0
    case Mips::NLZC_B:
8479
0
    case Mips::NLZC_D:
8480
0
    case Mips::NLZC_H:
8481
0
    case Mips::NLZC_W:
8482
0
    case Mips::PCNT_B:
8483
0
    case Mips::PCNT_D:
8484
0
    case Mips::PCNT_H:
8485
0
    case Mips::PCNT_W: {
8486
      // op: ws
8487
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8488
0
      op &= UINT64_C(31);
8489
0
      op <<= 11;
8490
0
      Value |= op;
8491
      // op: wd
8492
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8493
0
      op &= UINT64_C(31);
8494
0
      op <<= 6;
8495
0
      Value |= op;
8496
0
      break;
8497
0
    }
8498
0
    case Mips::BCLRI_H:
8499
0
    case Mips::BNEGI_H:
8500
0
    case Mips::BSETI_H:
8501
0
    case Mips::SAT_S_H:
8502
0
    case Mips::SAT_U_H:
8503
0
    case Mips::SLLI_H:
8504
0
    case Mips::SRAI_H:
8505
0
    case Mips::SRARI_H:
8506
0
    case Mips::SRLI_H:
8507
0
    case Mips::SRLRI_H: {
8508
      // op: ws
8509
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8510
0
      op &= UINT64_C(31);
8511
0
      op <<= 11;
8512
0
      Value |= op;
8513
      // op: wd
8514
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8515
0
      op &= UINT64_C(31);
8516
0
      op <<= 6;
8517
0
      Value |= op;
8518
      // op: m
8519
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8520
0
      op &= UINT64_C(15);
8521
0
      op <<= 16;
8522
0
      Value |= op;
8523
0
      break;
8524
0
    }
8525
0
    case Mips::BCLRI_W:
8526
0
    case Mips::BNEGI_W:
8527
0
    case Mips::BSETI_W:
8528
0
    case Mips::SAT_S_W:
8529
0
    case Mips::SAT_U_W:
8530
0
    case Mips::SLLI_W:
8531
0
    case Mips::SRAI_W:
8532
0
    case Mips::SRARI_W:
8533
0
    case Mips::SRLI_W:
8534
0
    case Mips::SRLRI_W: {
8535
      // op: ws
8536
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8537
0
      op &= UINT64_C(31);
8538
0
      op <<= 11;
8539
0
      Value |= op;
8540
      // op: wd
8541
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8542
0
      op &= UINT64_C(31);
8543
0
      op <<= 6;
8544
0
      Value |= op;
8545
      // op: m
8546
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8547
0
      op &= UINT64_C(31);
8548
0
      op <<= 16;
8549
0
      Value |= op;
8550
0
      break;
8551
0
    }
8552
0
    case Mips::BCLRI_D:
8553
0
    case Mips::BNEGI_D:
8554
0
    case Mips::BSETI_D:
8555
0
    case Mips::SAT_S_D:
8556
0
    case Mips::SAT_U_D:
8557
0
    case Mips::SLLI_D:
8558
0
    case Mips::SRAI_D:
8559
0
    case Mips::SRARI_D:
8560
0
    case Mips::SRLI_D:
8561
0
    case Mips::SRLRI_D: {
8562
      // op: ws
8563
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8564
0
      op &= UINT64_C(31);
8565
0
      op <<= 11;
8566
0
      Value |= op;
8567
      // op: wd
8568
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8569
0
      op &= UINT64_C(31);
8570
0
      op <<= 6;
8571
0
      Value |= op;
8572
      // op: m
8573
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8574
0
      op &= UINT64_C(63);
8575
0
      op <<= 16;
8576
0
      Value |= op;
8577
0
      break;
8578
0
    }
8579
0
    case Mips::BCLRI_B:
8580
0
    case Mips::BNEGI_B:
8581
0
    case Mips::BSETI_B:
8582
0
    case Mips::SAT_S_B:
8583
0
    case Mips::SAT_U_B:
8584
0
    case Mips::SLLI_B:
8585
0
    case Mips::SRAI_B:
8586
0
    case Mips::SRARI_B:
8587
0
    case Mips::SRLI_B:
8588
0
    case Mips::SRLRI_B: {
8589
      // op: ws
8590
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8591
0
      op &= UINT64_C(31);
8592
0
      op <<= 11;
8593
0
      Value |= op;
8594
      // op: wd
8595
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8596
0
      op &= UINT64_C(31);
8597
0
      op <<= 6;
8598
0
      Value |= op;
8599
      // op: m
8600
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8601
0
      op &= UINT64_C(7);
8602
0
      op <<= 16;
8603
0
      Value |= op;
8604
0
      break;
8605
0
    }
8606
0
    case Mips::BINSLI_H:
8607
0
    case Mips::BINSRI_H: {
8608
      // op: ws
8609
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8610
0
      op &= UINT64_C(31);
8611
0
      op <<= 11;
8612
0
      Value |= op;
8613
      // op: wd
8614
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8615
0
      op &= UINT64_C(31);
8616
0
      op <<= 6;
8617
0
      Value |= op;
8618
      // op: m
8619
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8620
0
      op &= UINT64_C(15);
8621
0
      op <<= 16;
8622
0
      Value |= op;
8623
0
      break;
8624
0
    }
8625
0
    case Mips::BINSLI_W:
8626
0
    case Mips::BINSRI_W: {
8627
      // op: ws
8628
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8629
0
      op &= UINT64_C(31);
8630
0
      op <<= 11;
8631
0
      Value |= op;
8632
      // op: wd
8633
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8634
0
      op &= UINT64_C(31);
8635
0
      op <<= 6;
8636
0
      Value |= op;
8637
      // op: m
8638
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8639
0
      op &= UINT64_C(31);
8640
0
      op <<= 16;
8641
0
      Value |= op;
8642
0
      break;
8643
0
    }
8644
0
    case Mips::BINSLI_D:
8645
0
    case Mips::BINSRI_D: {
8646
      // op: ws
8647
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8648
0
      op &= UINT64_C(31);
8649
0
      op <<= 11;
8650
0
      Value |= op;
8651
      // op: wd
8652
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8653
0
      op &= UINT64_C(31);
8654
0
      op <<= 6;
8655
0
      Value |= op;
8656
      // op: m
8657
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8658
0
      op &= UINT64_C(63);
8659
0
      op <<= 16;
8660
0
      Value |= op;
8661
0
      break;
8662
0
    }
8663
0
    case Mips::BINSLI_B:
8664
0
    case Mips::BINSRI_B: {
8665
      // op: ws
8666
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8667
0
      op &= UINT64_C(31);
8668
0
      op <<= 11;
8669
0
      Value |= op;
8670
      // op: wd
8671
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8672
0
      op &= UINT64_C(31);
8673
0
      op <<= 6;
8674
0
      Value |= op;
8675
      // op: m
8676
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
8677
0
      op &= UINT64_C(7);
8678
0
      op <<= 16;
8679
0
      Value |= op;
8680
0
      break;
8681
0
    }
8682
0
    case Mips::ADDS_A_B:
8683
0
    case Mips::ADDS_A_D:
8684
0
    case Mips::ADDS_A_H:
8685
0
    case Mips::ADDS_A_W:
8686
0
    case Mips::ADDS_S_B:
8687
0
    case Mips::ADDS_S_D:
8688
0
    case Mips::ADDS_S_H:
8689
0
    case Mips::ADDS_S_W:
8690
0
    case Mips::ADDS_U_B:
8691
0
    case Mips::ADDS_U_D:
8692
0
    case Mips::ADDS_U_H:
8693
0
    case Mips::ADDS_U_W:
8694
0
    case Mips::ADDV_B:
8695
0
    case Mips::ADDV_D:
8696
0
    case Mips::ADDV_H:
8697
0
    case Mips::ADDV_W:
8698
0
    case Mips::ADD_A_B:
8699
0
    case Mips::ADD_A_D:
8700
0
    case Mips::ADD_A_H:
8701
0
    case Mips::ADD_A_W:
8702
0
    case Mips::AND_V:
8703
0
    case Mips::ASUB_S_B:
8704
0
    case Mips::ASUB_S_D:
8705
0
    case Mips::ASUB_S_H:
8706
0
    case Mips::ASUB_S_W:
8707
0
    case Mips::ASUB_U_B:
8708
0
    case Mips::ASUB_U_D:
8709
0
    case Mips::ASUB_U_H:
8710
0
    case Mips::ASUB_U_W:
8711
0
    case Mips::AVER_S_B:
8712
0
    case Mips::AVER_S_D:
8713
0
    case Mips::AVER_S_H:
8714
0
    case Mips::AVER_S_W:
8715
0
    case Mips::AVER_U_B:
8716
0
    case Mips::AVER_U_D:
8717
0
    case Mips::AVER_U_H:
8718
0
    case Mips::AVER_U_W:
8719
0
    case Mips::AVE_S_B:
8720
0
    case Mips::AVE_S_D:
8721
0
    case Mips::AVE_S_H:
8722
0
    case Mips::AVE_S_W:
8723
0
    case Mips::AVE_U_B:
8724
0
    case Mips::AVE_U_D:
8725
0
    case Mips::AVE_U_H:
8726
0
    case Mips::AVE_U_W:
8727
0
    case Mips::BCLR_B:
8728
0
    case Mips::BCLR_D:
8729
0
    case Mips::BCLR_H:
8730
0
    case Mips::BCLR_W:
8731
0
    case Mips::BNEG_B:
8732
0
    case Mips::BNEG_D:
8733
0
    case Mips::BNEG_H:
8734
0
    case Mips::BNEG_W:
8735
0
    case Mips::BSET_B:
8736
0
    case Mips::BSET_D:
8737
0
    case Mips::BSET_H:
8738
0
    case Mips::BSET_W:
8739
0
    case Mips::CEQ_B:
8740
0
    case Mips::CEQ_D:
8741
0
    case Mips::CEQ_H:
8742
0
    case Mips::CEQ_W:
8743
0
    case Mips::CLE_S_B:
8744
0
    case Mips::CLE_S_D:
8745
0
    case Mips::CLE_S_H:
8746
0
    case Mips::CLE_S_W:
8747
0
    case Mips::CLE_U_B:
8748
0
    case Mips::CLE_U_D:
8749
0
    case Mips::CLE_U_H:
8750
0
    case Mips::CLE_U_W:
8751
0
    case Mips::CLT_S_B:
8752
0
    case Mips::CLT_S_D:
8753
0
    case Mips::CLT_S_H:
8754
0
    case Mips::CLT_S_W:
8755
0
    case Mips::CLT_U_B:
8756
0
    case Mips::CLT_U_D:
8757
0
    case Mips::CLT_U_H:
8758
0
    case Mips::CLT_U_W:
8759
0
    case Mips::DIV_S_B:
8760
0
    case Mips::DIV_S_D:
8761
0
    case Mips::DIV_S_H:
8762
0
    case Mips::DIV_S_W:
8763
0
    case Mips::DIV_U_B:
8764
0
    case Mips::DIV_U_D:
8765
0
    case Mips::DIV_U_H:
8766
0
    case Mips::DIV_U_W:
8767
0
    case Mips::DOTP_S_D:
8768
0
    case Mips::DOTP_S_H:
8769
0
    case Mips::DOTP_S_W:
8770
0
    case Mips::DOTP_U_D:
8771
0
    case Mips::DOTP_U_H:
8772
0
    case Mips::DOTP_U_W:
8773
0
    case Mips::FADD_D:
8774
0
    case Mips::FADD_W:
8775
0
    case Mips::FCAF_D:
8776
0
    case Mips::FCAF_W:
8777
0
    case Mips::FCEQ_D:
8778
0
    case Mips::FCEQ_W:
8779
0
    case Mips::FCLE_D:
8780
0
    case Mips::FCLE_W:
8781
0
    case Mips::FCLT_D:
8782
0
    case Mips::FCLT_W:
8783
0
    case Mips::FCNE_D:
8784
0
    case Mips::FCNE_W:
8785
0
    case Mips::FCOR_D:
8786
0
    case Mips::FCOR_W:
8787
0
    case Mips::FCUEQ_D:
8788
0
    case Mips::FCUEQ_W:
8789
0
    case Mips::FCULE_D:
8790
0
    case Mips::FCULE_W:
8791
0
    case Mips::FCULT_D:
8792
0
    case Mips::FCULT_W:
8793
0
    case Mips::FCUNE_D:
8794
0
    case Mips::FCUNE_W:
8795
0
    case Mips::FCUN_D:
8796
0
    case Mips::FCUN_W:
8797
0
    case Mips::FDIV_D:
8798
0
    case Mips::FDIV_W:
8799
0
    case Mips::FEXDO_H:
8800
0
    case Mips::FEXDO_W:
8801
0
    case Mips::FEXP2_D:
8802
0
    case Mips::FEXP2_W:
8803
0
    case Mips::FMAX_A_D:
8804
0
    case Mips::FMAX_A_W:
8805
0
    case Mips::FMAX_D:
8806
0
    case Mips::FMAX_W:
8807
0
    case Mips::FMIN_A_D:
8808
0
    case Mips::FMIN_A_W:
8809
0
    case Mips::FMIN_D:
8810
0
    case Mips::FMIN_W:
8811
0
    case Mips::FMUL_D:
8812
0
    case Mips::FMUL_W:
8813
0
    case Mips::FSAF_D:
8814
0
    case Mips::FSAF_W:
8815
0
    case Mips::FSEQ_D:
8816
0
    case Mips::FSEQ_W:
8817
0
    case Mips::FSLE_D:
8818
0
    case Mips::FSLE_W:
8819
0
    case Mips::FSLT_D:
8820
0
    case Mips::FSLT_W:
8821
0
    case Mips::FSNE_D:
8822
0
    case Mips::FSNE_W:
8823
0
    case Mips::FSOR_D:
8824
0
    case Mips::FSOR_W:
8825
0
    case Mips::FSUB_D:
8826
0
    case Mips::FSUB_W:
8827
0
    case Mips::FSUEQ_D:
8828
0
    case Mips::FSUEQ_W:
8829
0
    case Mips::FSULE_D:
8830
0
    case Mips::FSULE_W:
8831
0
    case Mips::FSULT_D:
8832
0
    case Mips::FSULT_W:
8833
0
    case Mips::FSUNE_D:
8834
0
    case Mips::FSUNE_W:
8835
0
    case Mips::FSUN_D:
8836
0
    case Mips::FSUN_W:
8837
0
    case Mips::FTQ_H:
8838
0
    case Mips::FTQ_W:
8839
0
    case Mips::HADD_S_D:
8840
0
    case Mips::HADD_S_H:
8841
0
    case Mips::HADD_S_W:
8842
0
    case Mips::HADD_U_D:
8843
0
    case Mips::HADD_U_H:
8844
0
    case Mips::HADD_U_W:
8845
0
    case Mips::HSUB_S_D:
8846
0
    case Mips::HSUB_S_H:
8847
0
    case Mips::HSUB_S_W:
8848
0
    case Mips::HSUB_U_D:
8849
0
    case Mips::HSUB_U_H:
8850
0
    case Mips::HSUB_U_W:
8851
0
    case Mips::ILVEV_B:
8852
0
    case Mips::ILVEV_D:
8853
0
    case Mips::ILVEV_H:
8854
0
    case Mips::ILVEV_W:
8855
0
    case Mips::ILVL_B:
8856
0
    case Mips::ILVL_D:
8857
0
    case Mips::ILVL_H:
8858
0
    case Mips::ILVL_W:
8859
0
    case Mips::ILVOD_B:
8860
0
    case Mips::ILVOD_D:
8861
0
    case Mips::ILVOD_H:
8862
0
    case Mips::ILVOD_W:
8863
0
    case Mips::ILVR_B:
8864
0
    case Mips::ILVR_D:
8865
0
    case Mips::ILVR_H:
8866
0
    case Mips::ILVR_W:
8867
0
    case Mips::MAX_A_B:
8868
0
    case Mips::MAX_A_D:
8869
0
    case Mips::MAX_A_H:
8870
0
    case Mips::MAX_A_W:
8871
0
    case Mips::MAX_S_B:
8872
0
    case Mips::MAX_S_D:
8873
0
    case Mips::MAX_S_H:
8874
0
    case Mips::MAX_S_W:
8875
0
    case Mips::MAX_U_B:
8876
0
    case Mips::MAX_U_D:
8877
0
    case Mips::MAX_U_H:
8878
0
    case Mips::MAX_U_W:
8879
0
    case Mips::MIN_A_B:
8880
0
    case Mips::MIN_A_D:
8881
0
    case Mips::MIN_A_H:
8882
0
    case Mips::MIN_A_W:
8883
0
    case Mips::MIN_S_B:
8884
0
    case Mips::MIN_S_D:
8885
0
    case Mips::MIN_S_H:
8886
0
    case Mips::MIN_S_W:
8887
0
    case Mips::MIN_U_B:
8888
0
    case Mips::MIN_U_D:
8889
0
    case Mips::MIN_U_H:
8890
0
    case Mips::MIN_U_W:
8891
0
    case Mips::MOD_S_B:
8892
0
    case Mips::MOD_S_D:
8893
0
    case Mips::MOD_S_H:
8894
0
    case Mips::MOD_S_W:
8895
0
    case Mips::MOD_U_B:
8896
0
    case Mips::MOD_U_D:
8897
0
    case Mips::MOD_U_H:
8898
0
    case Mips::MOD_U_W:
8899
0
    case Mips::MULR_Q_H:
8900
0
    case Mips::MULR_Q_W:
8901
0
    case Mips::MULV_B:
8902
0
    case Mips::MULV_D:
8903
0
    case Mips::MULV_H:
8904
0
    case Mips::MULV_W:
8905
0
    case Mips::MUL_Q_H:
8906
0
    case Mips::MUL_Q_W:
8907
0
    case Mips::NOR_V:
8908
0
    case Mips::OR_V:
8909
0
    case Mips::PCKEV_B:
8910
0
    case Mips::PCKEV_D:
8911
0
    case Mips::PCKEV_H:
8912
0
    case Mips::PCKEV_W:
8913
0
    case Mips::PCKOD_B:
8914
0
    case Mips::PCKOD_D:
8915
0
    case Mips::PCKOD_H:
8916
0
    case Mips::PCKOD_W:
8917
0
    case Mips::SLL_B:
8918
0
    case Mips::SLL_D:
8919
0
    case Mips::SLL_H:
8920
0
    case Mips::SLL_W:
8921
0
    case Mips::SRAR_B:
8922
0
    case Mips::SRAR_D:
8923
0
    case Mips::SRAR_H:
8924
0
    case Mips::SRAR_W:
8925
0
    case Mips::SRA_B:
8926
0
    case Mips::SRA_D:
8927
0
    case Mips::SRA_H:
8928
0
    case Mips::SRA_W:
8929
0
    case Mips::SRLR_B:
8930
0
    case Mips::SRLR_D:
8931
0
    case Mips::SRLR_H:
8932
0
    case Mips::SRLR_W:
8933
0
    case Mips::SRL_B:
8934
0
    case Mips::SRL_D:
8935
0
    case Mips::SRL_H:
8936
0
    case Mips::SRL_W:
8937
0
    case Mips::SUBSUS_U_B:
8938
0
    case Mips::SUBSUS_U_D:
8939
0
    case Mips::SUBSUS_U_H:
8940
0
    case Mips::SUBSUS_U_W:
8941
0
    case Mips::SUBSUU_S_B:
8942
0
    case Mips::SUBSUU_S_D:
8943
0
    case Mips::SUBSUU_S_H:
8944
0
    case Mips::SUBSUU_S_W:
8945
0
    case Mips::SUBS_S_B:
8946
0
    case Mips::SUBS_S_D:
8947
0
    case Mips::SUBS_S_H:
8948
0
    case Mips::SUBS_S_W:
8949
0
    case Mips::SUBS_U_B:
8950
0
    case Mips::SUBS_U_D:
8951
0
    case Mips::SUBS_U_H:
8952
0
    case Mips::SUBS_U_W:
8953
0
    case Mips::SUBV_B:
8954
0
    case Mips::SUBV_D:
8955
0
    case Mips::SUBV_H:
8956
0
    case Mips::SUBV_W:
8957
0
    case Mips::XOR_V: {
8958
      // op: wt
8959
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
8960
0
      op &= UINT64_C(31);
8961
0
      op <<= 16;
8962
0
      Value |= op;
8963
      // op: ws
8964
0
      op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
8965
0
      op &= UINT64_C(31);
8966
0
      op <<= 11;
8967
0
      Value |= op;
8968
      // op: wd
8969
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
8970
0
      op &= UINT64_C(31);
8971
0
      op <<= 6;
8972
0
      Value |= op;
8973
0
      break;
8974
0
    }
8975
0
    case Mips::BINSL_B:
8976
0
    case Mips::BINSL_D:
8977
0
    case Mips::BINSL_H:
8978
0
    case Mips::BINSL_W:
8979
0
    case Mips::BINSR_B:
8980
0
    case Mips::BINSR_D:
8981
0
    case Mips::BINSR_H:
8982
0
    case Mips::BINSR_W:
8983
0
    case Mips::BMNZ_V:
8984
0
    case Mips::BMZ_V:
8985
0
    case Mips::BSEL_V:
8986
0
    case Mips::DPADD_S_D:
8987
0
    case Mips::DPADD_S_H:
8988
0
    case Mips::DPADD_S_W:
8989
0
    case Mips::DPADD_U_D:
8990
0
    case Mips::DPADD_U_H:
8991
0
    case Mips::DPADD_U_W:
8992
0
    case Mips::DPSUB_S_D:
8993
0
    case Mips::DPSUB_S_H:
8994
0
    case Mips::DPSUB_S_W:
8995
0
    case Mips::DPSUB_U_D:
8996
0
    case Mips::DPSUB_U_H:
8997
0
    case Mips::DPSUB_U_W:
8998
0
    case Mips::FMADD_D:
8999
0
    case Mips::FMADD_W:
9000
0
    case Mips::FMSUB_D:
9001
0
    case Mips::FMSUB_W:
9002
0
    case Mips::MADDR_Q_H:
9003
0
    case Mips::MADDR_Q_W:
9004
0
    case Mips::MADDV_B:
9005
0
    case Mips::MADDV_D:
9006
0
    case Mips::MADDV_H:
9007
0
    case Mips::MADDV_W:
9008
0
    case Mips::MADD_Q_H:
9009
0
    case Mips::MADD_Q_W:
9010
0
    case Mips::MSUBR_Q_H:
9011
0
    case Mips::MSUBR_Q_W:
9012
0
    case Mips::MSUBV_B:
9013
0
    case Mips::MSUBV_D:
9014
0
    case Mips::MSUBV_H:
9015
0
    case Mips::MSUBV_W:
9016
0
    case Mips::MSUB_Q_H:
9017
0
    case Mips::MSUB_Q_W:
9018
0
    case Mips::VSHF_B:
9019
0
    case Mips::VSHF_D:
9020
0
    case Mips::VSHF_H:
9021
0
    case Mips::VSHF_W: {
9022
      // op: wt
9023
0
      op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
9024
0
      op &= UINT64_C(31);
9025
0
      op <<= 16;
9026
0
      Value |= op;
9027
      // op: ws
9028
0
      op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
9029
0
      op &= UINT64_C(31);
9030
0
      op <<= 11;
9031
0
      Value |= op;
9032
      // op: wd
9033
0
      op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
9034
0
      op &= UINT64_C(31);
9035
0
      op <<= 6;
9036
0
      Value |= op;
9037
0
      break;
9038
0
    }
9039
0
  default:
9040
0
    std::string msg;
9041
0
    raw_string_ostream Msg(msg);
9042
0
    Msg << "Not supported instr: " << MI;
9043
0
    report_fatal_error(Msg.str().c_str());
9044
0
  }
9045
0
  return Value;
9046
0
}
9047
9048
#ifdef GET_OPERAND_BIT_OFFSET
9049
#undef GET_OPERAND_BIT_OFFSET
9050
9051
uint32_t MipsMCCodeEmitter::getOperandBitOffset(const MCInst &MI,
9052
    unsigned OpNum,
9053
    const MCSubtargetInfo &STI) const {
9054
  switch (MI.getOpcode()) {
9055
    case Mips::Break16:
9056
    case Mips::DERET:
9057
    case Mips::DERET_MM:
9058
    case Mips::DERET_MMR6:
9059
    case Mips::EHB:
9060
    case Mips::EHB_MM:
9061
    case Mips::EHB_MMR6:
9062
    case Mips::ERET:
9063
    case Mips::ERETNC:
9064
    case Mips::ERETNC_MMR6:
9065
    case Mips::ERET_MM:
9066
    case Mips::ERET_MMR6:
9067
    case Mips::JrRa16:
9068
    case Mips::JrcRa16:
9069
    case Mips::JrcRx16:
9070
    case Mips::PAUSE:
9071
    case Mips::PAUSE_MM:
9072
    case Mips::PAUSE_MMR6:
9073
    case Mips::Restore16:
9074
    case Mips::RestoreX16:
9075
    case Mips::SSNOP:
9076
    case Mips::SSNOP_MM:
9077
    case Mips::SSNOP_MMR6:
9078
    case Mips::Save16:
9079
    case Mips::SaveX16:
9080
    case Mips::TLBGINV:
9081
    case Mips::TLBGINVF:
9082
    case Mips::TLBGINVF_MM:
9083
    case Mips::TLBGINV_MM:
9084
    case Mips::TLBGP:
9085
    case Mips::TLBGP_MM:
9086
    case Mips::TLBGR:
9087
    case Mips::TLBGR_MM:
9088
    case Mips::TLBGWI:
9089
    case Mips::TLBGWI_MM:
9090
    case Mips::TLBGWR:
9091
    case Mips::TLBGWR_MM:
9092
    case Mips::TLBINV:
9093
    case Mips::TLBINVF:
9094
    case Mips::TLBINVF_MMR6:
9095
    case Mips::TLBINV_MMR6:
9096
    case Mips::TLBP:
9097
    case Mips::TLBP_MM:
9098
    case Mips::TLBR:
9099
    case Mips::TLBR_MM:
9100
    case Mips::TLBWI:
9101
    case Mips::TLBWI_MM:
9102
    case Mips::TLBWR:
9103
    case Mips::TLBWR_MM:
9104
    case Mips::WAIT: {
9105
      break;
9106
    }
9107
    case Mips::DPAQX_SA_W_PH:
9108
    case Mips::DPAQX_S_W_PH:
9109
    case Mips::DPAQ_SA_L_W:
9110
    case Mips::DPAQ_S_W_PH:
9111
    case Mips::DPAU_H_QBL:
9112
    case Mips::DPAU_H_QBR:
9113
    case Mips::DPAX_W_PH:
9114
    case Mips::DPA_W_PH:
9115
    case Mips::DPSQX_SA_W_PH:
9116
    case Mips::DPSQX_S_W_PH:
9117
    case Mips::DPSQ_SA_L_W:
9118
    case Mips::DPSQ_S_W_PH:
9119
    case Mips::DPSU_H_QBL:
9120
    case Mips::DPSU_H_QBR:
9121
    case Mips::DPSX_W_PH:
9122
    case Mips::DPS_W_PH:
9123
    case Mips::MADDU_DSP:
9124
    case Mips::MADD_DSP:
9125
    case Mips::MAQ_SA_W_PHL:
9126
    case Mips::MAQ_SA_W_PHR:
9127
    case Mips::MAQ_S_W_PHL:
9128
    case Mips::MAQ_S_W_PHR:
9129
    case Mips::MSUBU_DSP:
9130
    case Mips::MSUB_DSP:
9131
    case Mips::MULSAQ_S_W_PH:
9132
    case Mips::MULSA_W_PH:
9133
    case Mips::MULTU_DSP:
9134
    case Mips::MULT_DSP: {
9135
      switch (OpNum) {
9136
      case 0:
9137
        // op: ac
9138
        return 11;
9139
      case 1:
9140
        // op: rs
9141
        return 21;
9142
      case 2:
9143
        // op: rt
9144
        return 16;
9145
      }
9146
      break;
9147
    }
9148
    case Mips::MTHLIP:
9149
    case Mips::SHILOV: {
9150
      switch (OpNum) {
9151
      case 0:
9152
        // op: ac
9153
        return 11;
9154
      case 1:
9155
        // op: rs
9156
        return 21;
9157
      }
9158
      break;
9159
    }
9160
    case Mips::SHILO: {
9161
      switch (OpNum) {
9162
      case 0:
9163
        // op: ac
9164
        return 11;
9165
      case 1:
9166
        // op: shift
9167
        return 20;
9168
      }
9169
      break;
9170
    }
9171
    case Mips::CACHE:
9172
    case Mips::PREF: {
9173
      switch (OpNum) {
9174
      case 0:
9175
        // op: addr
9176
        return 0;
9177
      case 2:
9178
        // op: hint
9179
        return 16;
9180
      }
9181
      break;
9182
    }
9183
    case Mips::CACHEE_MM:
9184
    case Mips::CACHE_MM:
9185
    case Mips::CACHE_MMR6:
9186
    case Mips::PREFE_MM:
9187
    case Mips::PREF_MM:
9188
    case Mips::PREF_MMR6: {
9189
      switch (OpNum) {
9190
      case 0:
9191
        // op: addr
9192
        return 0;
9193
      case 2:
9194
        // op: hint
9195
        return 21;
9196
      }
9197
      break;
9198
    }
9199
    case Mips::SYNCI:
9200
    case Mips::SYNCI_MM:
9201
    case Mips::SYNCI_MMR6: {
9202
      switch (OpNum) {
9203
      case 0:
9204
        // op: addr
9205
        return 0;
9206
      }
9207
      break;
9208
    }
9209
    case Mips::CACHEE:
9210
    case Mips::CACHE_R6:
9211
    case Mips::PREFE:
9212
    case Mips::PREF_R6: {
9213
      switch (OpNum) {
9214
      case 0:
9215
        // op: addr
9216
        return 7;
9217
      case 2:
9218
        // op: hint
9219
        return 16;
9220
      }
9221
      break;
9222
    }
9223
    case Mips::BREAK16_MM:
9224
    case Mips::SDBBP16_MM:
9225
    case Mips::SIGRIE: {
9226
      switch (OpNum) {
9227
      case 0:
9228
        // op: code_
9229
        return 0;
9230
      }
9231
      break;
9232
    }
9233
    case Mips::HYPCALL: {
9234
      switch (OpNum) {
9235
      case 0:
9236
        // op: code_
9237
        return 11;
9238
      }
9239
      break;
9240
    }
9241
    case Mips::HYPCALL_MM:
9242
    case Mips::SDBBP_MM:
9243
    case Mips::SDBBP_MMR6:
9244
    case Mips::SYSCALL_MM:
9245
    case Mips::WAIT_MM:
9246
    case Mips::WAIT_MMR6: {
9247
      switch (OpNum) {
9248
      case 0:
9249
        // op: code_
9250
        return 16;
9251
      }
9252
      break;
9253
    }
9254
    case Mips::BREAK16_MMR6:
9255
    case Mips::SDBBP:
9256
    case Mips::SDBBP16_MMR6:
9257
    case Mips::SDBBP_R6:
9258
    case Mips::SIGRIE_MMR6:
9259
    case Mips::SYSCALL: {
9260
      switch (OpNum) {
9261
      case 0:
9262
        // op: code_
9263
        return 6;
9264
      }
9265
      break;
9266
    }
9267
    case Mips::BREAK:
9268
    case Mips::BREAK_MM:
9269
    case Mips::BREAK_MMR6: {
9270
      switch (OpNum) {
9271
      case 0:
9272
        // op: code_1
9273
        return 16;
9274
      case 1:
9275
        // op: code_2
9276
        return 6;
9277
      }
9278
      break;
9279
    }
9280
    case Mips::BC2EQZ:
9281
    case Mips::BC2NEZ: {
9282
      switch (OpNum) {
9283
      case 0:
9284
        // op: ct
9285
        return 16;
9286
      case 1:
9287
        // op: offset
9288
        return 0;
9289
      }
9290
      break;
9291
    }
9292
    case Mips::BC1F:
9293
    case Mips::BC1FL:
9294
    case Mips::BC1F_MM:
9295
    case Mips::BC1T:
9296
    case Mips::BC1TL:
9297
    case Mips::BC1T_MM: {
9298
      switch (OpNum) {
9299
      case 0:
9300
        // op: fcc
9301
        return 18;
9302
      case 1:
9303
        // op: offset
9304
        return 0;
9305
      }
9306
      break;
9307
    }
9308
    case Mips::LUXC1_MM:
9309
    case Mips::LWXC1_MM: {
9310
      switch (OpNum) {
9311
      case 0:
9312
        // op: fd
9313
        return 11;
9314
      case 1:
9315
        // op: base
9316
        return 16;
9317
      case 2:
9318
        // op: index
9319
        return 21;
9320
      }
9321
      break;
9322
    }
9323
    case Mips::MOVN_I_D32_MM:
9324
    case Mips::MOVN_I_S_MM:
9325
    case Mips::MOVZ_I_D32_MM:
9326
    case Mips::MOVZ_I_S_MM: {
9327
      switch (OpNum) {
9328
      case 0:
9329
        // op: fd
9330
        return 11;
9331
      case 1:
9332
        // op: fs
9333
        return 16;
9334
      case 2:
9335
        // op: rt
9336
        return 21;
9337
      }
9338
      break;
9339
    }
9340
    case Mips::MOVF_D32_MM:
9341
    case Mips::MOVF_S_MM:
9342
    case Mips::MOVT_D32_MM:
9343
    case Mips::MOVT_S_MM: {
9344
      switch (OpNum) {
9345
      case 0:
9346
        // op: fd
9347
        return 21;
9348
      case 1:
9349
        // op: fs
9350
        return 16;
9351
      case 2:
9352
        // op: fcc
9353
        return 13;
9354
      }
9355
      break;
9356
    }
9357
    case Mips::CEIL_W_MM:
9358
    case Mips::CEIL_W_S_MM:
9359
    case Mips::CVT_D32_S_MM:
9360
    case Mips::CVT_D32_W_MM:
9361
    case Mips::CVT_D64_S_MM:
9362
    case Mips::CVT_D64_W_MM:
9363
    case Mips::CVT_L_D64_MM:
9364
    case Mips::CVT_L_S_MM:
9365
    case Mips::CVT_S_D32_MM:
9366
    case Mips::CVT_S_D64_MM:
9367
    case Mips::CVT_S_W_MM:
9368
    case Mips::CVT_W_D32_MM:
9369
    case Mips::CVT_W_D64_MM:
9370
    case Mips::CVT_W_S_MM:
9371
    case Mips::FABS_D32_MM:
9372
    case Mips::FABS_D64_MM:
9373
    case Mips::FABS_S_MM:
9374
    case Mips::FLOOR_W_MM:
9375
    case Mips::FLOOR_W_S_MM:
9376
    case Mips::FMOV_D32_MM:
9377
    case Mips::FMOV_D64_MM:
9378
    case Mips::FMOV_S_MM:
9379
    case Mips::FNEG_D32_MM:
9380
    case Mips::FNEG_D64_MM:
9381
    case Mips::FNEG_S_MM:
9382
    case Mips::FSQRT_D32_MM:
9383
    case Mips::FSQRT_D64_MM:
9384
    case Mips::FSQRT_S_MM:
9385
    case Mips::RECIP_D32_MM:
9386
    case Mips::RECIP_D64_MM:
9387
    case Mips::RECIP_S_MM:
9388
    case Mips::ROUND_W_MM:
9389
    case Mips::ROUND_W_S_MM:
9390
    case Mips::RSQRT_D32_MM:
9391
    case Mips::RSQRT_D64_MM:
9392
    case Mips::RSQRT_S_MM:
9393
    case Mips::TRUNC_W_MM:
9394
    case Mips::TRUNC_W_S_MM: {
9395
      switch (OpNum) {
9396
      case 0:
9397
        // op: fd
9398
        return 21;
9399
      case 1:
9400
        // op: fs
9401
        return 16;
9402
      }
9403
      break;
9404
    }
9405
    case Mips::LDXC1:
9406
    case Mips::LDXC164:
9407
    case Mips::LUXC1:
9408
    case Mips::LUXC164:
9409
    case Mips::LWXC1: {
9410
      switch (OpNum) {
9411
      case 0:
9412
        // op: fd
9413
        return 6;
9414
      case 1:
9415
        // op: base
9416
        return 21;
9417
      case 2:
9418
        // op: index
9419
        return 16;
9420
      }
9421
      break;
9422
    }
9423
    case Mips::MADD_D32:
9424
    case Mips::MADD_D64:
9425
    case Mips::MADD_S:
9426
    case Mips::MSUB_D32:
9427
    case Mips::MSUB_D64:
9428
    case Mips::MSUB_S:
9429
    case Mips::NMADD_D32:
9430
    case Mips::NMADD_D64:
9431
    case Mips::NMADD_S:
9432
    case Mips::NMSUB_D32:
9433
    case Mips::NMSUB_D64:
9434
    case Mips::NMSUB_S: {
9435
      switch (OpNum) {
9436
      case 0:
9437
        // op: fd
9438
        return 6;
9439
      case 1:
9440
        // op: fr
9441
        return 21;
9442
      case 2:
9443
        // op: fs
9444
        return 11;
9445
      case 3:
9446
        // op: ft
9447
        return 16;
9448
      }
9449
      break;
9450
    }
9451
    case Mips::MOVF_D32:
9452
    case Mips::MOVF_D64:
9453
    case Mips::MOVF_S:
9454
    case Mips::MOVT_D32:
9455
    case Mips::MOVT_D64:
9456
    case Mips::MOVT_S: {
9457
      switch (OpNum) {
9458
      case 0:
9459
        // op: fd
9460
        return 6;
9461
      case 1:
9462
        // op: fs
9463
        return 11;
9464
      case 2:
9465
        // op: fcc
9466
        return 18;
9467
      }
9468
      break;
9469
    }
9470
    case Mips::ADDR_PS64:
9471
    case Mips::CMP_EQ_D:
9472
    case Mips::CMP_EQ_S:
9473
    case Mips::CMP_F_D:
9474
    case Mips::CMP_F_S:
9475
    case Mips::CMP_LE_D:
9476
    case Mips::CMP_LE_S:
9477
    case Mips::CMP_LT_D:
9478
    case Mips::CMP_LT_S:
9479
    case Mips::CMP_SAF_D:
9480
    case Mips::CMP_SAF_S:
9481
    case Mips::CMP_SEQ_D:
9482
    case Mips::CMP_SEQ_S:
9483
    case Mips::CMP_SLE_D:
9484
    case Mips::CMP_SLE_S:
9485
    case Mips::CMP_SLT_D:
9486
    case Mips::CMP_SLT_S:
9487
    case Mips::CMP_SUEQ_D:
9488
    case Mips::CMP_SUEQ_S:
9489
    case Mips::CMP_SULE_D:
9490
    case Mips::CMP_SULE_S:
9491
    case Mips::CMP_SULT_D:
9492
    case Mips::CMP_SULT_S:
9493
    case Mips::CMP_SUN_D:
9494
    case Mips::CMP_SUN_S:
9495
    case Mips::CMP_UEQ_D:
9496
    case Mips::CMP_UEQ_S:
9497
    case Mips::CMP_ULE_D:
9498
    case Mips::CMP_ULE_S:
9499
    case Mips::CMP_ULT_D:
9500
    case Mips::CMP_ULT_S:
9501
    case Mips::CMP_UN_D:
9502
    case Mips::CMP_UN_S:
9503
    case Mips::CVT_PS_S64:
9504
    case Mips::FADD_D32:
9505
    case Mips::FADD_D64:
9506
    case Mips::FADD_PS64:
9507
    case Mips::FADD_S:
9508
    case Mips::FDIV_D32:
9509
    case Mips::FDIV_D64:
9510
    case Mips::FDIV_S:
9511
    case Mips::FMUL_D32:
9512
    case Mips::FMUL_D64:
9513
    case Mips::FMUL_PS64:
9514
    case Mips::FMUL_S:
9515
    case Mips::FSUB_D32:
9516
    case Mips::FSUB_D64:
9517
    case Mips::FSUB_PS64:
9518
    case Mips::FSUB_S:
9519
    case Mips::MULR_PS64:
9520
    case Mips::PLL_PS64:
9521
    case Mips::PLU_PS64:
9522
    case Mips::PUL_PS64:
9523
    case Mips::PUU_PS64: {
9524
      switch (OpNum) {
9525
      case 0:
9526
        // op: fd
9527
        return 6;
9528
      case 1:
9529
        // op: fs
9530
        return 11;
9531
      case 2:
9532
        // op: ft
9533
        return 16;
9534
      }
9535
      break;
9536
    }
9537
    case Mips::MOVN_I64_D64:
9538
    case Mips::MOVN_I64_S:
9539
    case Mips::MOVN_I_D32:
9540
    case Mips::MOVN_I_D64:
9541
    case Mips::MOVN_I_S:
9542
    case Mips::MOVZ_I64_D64:
9543
    case Mips::MOVZ_I64_S:
9544
    case Mips::MOVZ_I_D32:
9545
    case Mips::MOVZ_I_D64:
9546
    case Mips::MOVZ_I_S: {
9547
      switch (OpNum) {
9548
      case 0:
9549
        // op: fd
9550
        return 6;
9551
      case 1:
9552
        // op: fs
9553
        return 11;
9554
      case 2:
9555
        // op: rt
9556
        return 16;
9557
      }
9558
      break;
9559
    }
9560
    case Mips::CEIL_L_D64:
9561
    case Mips::CEIL_L_S:
9562
    case Mips::CEIL_W_D32:
9563
    case Mips::CEIL_W_D64:
9564
    case Mips::CEIL_W_S:
9565
    case Mips::CVT_D32_S:
9566
    case Mips::CVT_D32_W:
9567
    case Mips::CVT_D64_L:
9568
    case Mips::CVT_D64_S:
9569
    case Mips::CVT_D64_W:
9570
    case Mips::CVT_L_D64:
9571
    case Mips::CVT_L_S:
9572
    case Mips::CVT_PS_PW64:
9573
    case Mips::CVT_PW_PS64:
9574
    case Mips::CVT_S_D32:
9575
    case Mips::CVT_S_D64:
9576
    case Mips::CVT_S_L:
9577
    case Mips::CVT_S_PL64:
9578
    case Mips::CVT_S_PU64:
9579
    case Mips::CVT_S_W:
9580
    case Mips::CVT_W_D32:
9581
    case Mips::CVT_W_D64:
9582
    case Mips::CVT_W_S:
9583
    case Mips::FABS_D32:
9584
    case Mips::FABS_D64:
9585
    case Mips::FABS_S:
9586
    case Mips::FLOOR_L_D64:
9587
    case Mips::FLOOR_L_S:
9588
    case Mips::FLOOR_W_D32:
9589
    case Mips::FLOOR_W_D64:
9590
    case Mips::FLOOR_W_S:
9591
    case Mips::FMOV_D32:
9592
    case Mips::FMOV_D64:
9593
    case Mips::FMOV_S:
9594
    case Mips::FNEG_D32:
9595
    case Mips::FNEG_D64:
9596
    case Mips::FNEG_S:
9597
    case Mips::FSQRT_D32:
9598
    case Mips::FSQRT_D64:
9599
    case Mips::FSQRT_S:
9600
    case Mips::RECIP_D32:
9601
    case Mips::RECIP_D64:
9602
    case Mips::RECIP_S:
9603
    case Mips::ROUND_L_D64:
9604
    case Mips::ROUND_L_S:
9605
    case Mips::ROUND_W_D32:
9606
    case Mips::ROUND_W_D64:
9607
    case Mips::ROUND_W_S:
9608
    case Mips::RSQRT_D32:
9609
    case Mips::RSQRT_D64:
9610
    case Mips::RSQRT_S:
9611
    case Mips::TRUNC_L_D64:
9612
    case Mips::TRUNC_L_S:
9613
    case Mips::TRUNC_W_D32:
9614
    case Mips::TRUNC_W_D64:
9615
    case Mips::TRUNC_W_S: {
9616
      switch (OpNum) {
9617
      case 0:
9618
        // op: fd
9619
        return 6;
9620
      case 1:
9621
        // op: fs
9622
        return 11;
9623
      }
9624
      break;
9625
    }
9626
    case Mips::SUXC1_MM:
9627
    case Mips::SWXC1_MM: {
9628
      switch (OpNum) {
9629
      case 0:
9630
        // op: fs
9631
        return 11;
9632
      case 1:
9633
        // op: base
9634
        return 16;
9635
      case 2:
9636
        // op: index
9637
        return 21;
9638
      }
9639
      break;
9640
    }
9641
    case Mips::SDXC1:
9642
    case Mips::SDXC164:
9643
    case Mips::SUXC1:
9644
    case Mips::SUXC164:
9645
    case Mips::SWXC1: {
9646
      switch (OpNum) {
9647
      case 0:
9648
        // op: fs
9649
        return 11;
9650
      case 1:
9651
        // op: base
9652
        return 21;
9653
      case 2:
9654
        // op: index
9655
        return 16;
9656
      }
9657
      break;
9658
    }
9659
    case Mips::FCMP_D32:
9660
    case Mips::FCMP_D64:
9661
    case Mips::FCMP_S32: {
9662
      switch (OpNum) {
9663
      case 0:
9664
        // op: fs
9665
        return 11;
9666
      case 1:
9667
        // op: ft
9668
        return 16;
9669
      case 2:
9670
        // op: cond
9671
        return 0;
9672
      }
9673
      break;
9674
    }
9675
    case Mips::FCMP_D32_MM:
9676
    case Mips::FCMP_S32_MM: {
9677
      switch (OpNum) {
9678
      case 0:
9679
        // op: fs
9680
        return 16;
9681
      case 1:
9682
        // op: ft
9683
        return 21;
9684
      case 2:
9685
        // op: cond
9686
        return 6;
9687
      }
9688
      break;
9689
    }
9690
    case Mips::BC1EQZ:
9691
    case Mips::BC1NEZ: {
9692
      switch (OpNum) {
9693
      case 0:
9694
        // op: ft
9695
        return 16;
9696
      case 1:
9697
        // op: offset
9698
        return 0;
9699
      }
9700
      break;
9701
    }
9702
    case Mips::LDC1_D64_MMR6:
9703
    case Mips::SDC1_D64_MMR6: {
9704
      switch (OpNum) {
9705
      case 0:
9706
        // op: ft
9707
        return 21;
9708
      case 1:
9709
        // op: addr
9710
        return 0;
9711
      }
9712
      break;
9713
    }
9714
    case Mips::CEIL_L_D_MMR6:
9715
    case Mips::CEIL_L_S_MMR6:
9716
    case Mips::CEIL_W_D_MMR6:
9717
    case Mips::CEIL_W_S_MMR6:
9718
    case Mips::CVT_D_L_MMR6:
9719
    case Mips::CVT_L_D_MMR6:
9720
    case Mips::CVT_L_S_MMR6:
9721
    case Mips::CVT_S_L_MMR6:
9722
    case Mips::CVT_S_W_MMR6:
9723
    case Mips::CVT_W_S_MMR6:
9724
    case Mips::FLOOR_L_D_MMR6:
9725
    case Mips::FLOOR_L_S_MMR6:
9726
    case Mips::FLOOR_W_D_MMR6:
9727
    case Mips::FLOOR_W_S_MMR6:
9728
    case Mips::FMOV_D_MMR6:
9729
    case Mips::FMOV_S_MMR6:
9730
    case Mips::FNEG_S_MMR6:
9731
    case Mips::ROUND_L_D_MMR6:
9732
    case Mips::ROUND_L_S_MMR6:
9733
    case Mips::ROUND_W_D_MMR6:
9734
    case Mips::ROUND_W_S_MMR6:
9735
    case Mips::TRUNC_L_D_MMR6:
9736
    case Mips::TRUNC_L_S_MMR6:
9737
    case Mips::TRUNC_W_D_MMR6:
9738
    case Mips::TRUNC_W_S_MMR6: {
9739
      switch (OpNum) {
9740
      case 0:
9741
        // op: ft
9742
        return 21;
9743
      case 1:
9744
        // op: fs
9745
        return 16;
9746
      }
9747
      break;
9748
    }
9749
    case Mips::JRADDIUSP: {
9750
      switch (OpNum) {
9751
      case 0:
9752
        // op: imm
9753
        return 0;
9754
      }
9755
      break;
9756
    }
9757
    case Mips::ADDIUSP_MM: {
9758
      switch (OpNum) {
9759
      case 0:
9760
        // op: imm
9761
        return 1;
9762
      }
9763
      break;
9764
    }
9765
    case Mips::JRCADDIUSP_MMR6: {
9766
      switch (OpNum) {
9767
      case 0:
9768
        // op: imm
9769
        return 5;
9770
      }
9771
      break;
9772
    }
9773
    case Mips::Bimm16: {
9774
      switch (OpNum) {
9775
      case 0:
9776
        // op: imm11
9777
        return 0;
9778
      }
9779
      break;
9780
    }
9781
    case Mips::AddiuSpImmX16:
9782
    case Mips::BimmX16:
9783
    case Mips::BteqzX16:
9784
    case Mips::BtnezX16: {
9785
      switch (OpNum) {
9786
      case 0:
9787
        // op: imm16
9788
        return 0;
9789
      }
9790
      break;
9791
    }
9792
    case Mips::Jal16:
9793
    case Mips::JalB16: {
9794
      switch (OpNum) {
9795
      case 0:
9796
        // op: imm26
9797
        return 0;
9798
      }
9799
      break;
9800
    }
9801
    case Mips::AddiuSpImm16:
9802
    case Mips::Bteqz16:
9803
    case Mips::Btnez16: {
9804
      switch (OpNum) {
9805
      case 0:
9806
        // op: imm8
9807
        return 0;
9808
      }
9809
      break;
9810
    }
9811
    case Mips::B16_MM:
9812
    case Mips::BAL:
9813
    case Mips::BALC:
9814
    case Mips::BALC_MMR6:
9815
    case Mips::BC:
9816
    case Mips::BC16_MMR6:
9817
    case Mips::BC_MMR6:
9818
    case Mips::BPOSGE32:
9819
    case Mips::BPOSGE32C_MMR3:
9820
    case Mips::BPOSGE32_MM: {
9821
      switch (OpNum) {
9822
      case 0:
9823
        // op: offset
9824
        return 0;
9825
      }
9826
      break;
9827
    }
9828
    case Mips::Move32R16: {
9829
      switch (OpNum) {
9830
      case 0:
9831
        // op: r32
9832
        return 3;
9833
      case 1:
9834
        // op: rz
9835
        return 0;
9836
      }
9837
      break;
9838
    }
9839
    case Mips::MFHI16_MM:
9840
    case Mips::MFLO16_MM: {
9841
      switch (OpNum) {
9842
      case 0:
9843
        // op: rd
9844
        return 0;
9845
      }
9846
      break;
9847
    }
9848
    case Mips::MFHI_DSP:
9849
    case Mips::MFLO_DSP: {
9850
      switch (OpNum) {
9851
      case 0:
9852
        // op: rd
9853
        return 11;
9854
      case 1:
9855
        // op: ac
9856
        return 21;
9857
      }
9858
      break;
9859
    }
9860
    case Mips::LWXS_MM: {
9861
      switch (OpNum) {
9862
      case 0:
9863
        // op: rd
9864
        return 11;
9865
      case 1:
9866
        // op: base
9867
        return 16;
9868
      case 2:
9869
        // op: index
9870
        return 21;
9871
      }
9872
      break;
9873
    }
9874
    case Mips::LBUX:
9875
    case Mips::LHX:
9876
    case Mips::LWX: {
9877
      switch (OpNum) {
9878
      case 0:
9879
        // op: rd
9880
        return 11;
9881
      case 1:
9882
        // op: base
9883
        return 21;
9884
      case 2:
9885
        // op: index
9886
        return 16;
9887
      }
9888
      break;
9889
    }
9890
    case Mips::REPL_PH:
9891
    case Mips::REPL_PH_MM:
9892
    case Mips::REPL_QB: {
9893
      switch (OpNum) {
9894
      case 0:
9895
        // op: rd
9896
        return 11;
9897
      case 1:
9898
        // op: imm
9899
        return 16;
9900
      }
9901
      break;
9902
    }
9903
    case Mips::RDDSP: {
9904
      switch (OpNum) {
9905
      case 0:
9906
        // op: rd
9907
        return 11;
9908
      case 1:
9909
        // op: mask
9910
        return 16;
9911
      }
9912
      break;
9913
    }
9914
    case Mips::LSA_MMR6: {
9915
      switch (OpNum) {
9916
      case 0:
9917
        // op: rd
9918
        return 11;
9919
      case 1:
9920
        // op: rs
9921
        return 16;
9922
      case 2:
9923
        // op: rt
9924
        return 21;
9925
      case 3:
9926
        // op: imm2
9927
        return 9;
9928
      }
9929
      break;
9930
    }
9931
    case Mips::ADDQH_PH_MMR2:
9932
    case Mips::ADDQH_R_PH_MMR2:
9933
    case Mips::ADDQH_R_W_MMR2:
9934
    case Mips::ADDQH_W_MMR2:
9935
    case Mips::ADDQ_PH_MM:
9936
    case Mips::ADDQ_S_PH_MM:
9937
    case Mips::ADDQ_S_W_MM:
9938
    case Mips::ADDSC_MM:
9939
    case Mips::ADDUH_QB_MMR2:
9940
    case Mips::ADDUH_R_QB_MMR2:
9941
    case Mips::ADDU_PH_MMR2:
9942
    case Mips::ADDU_QB_MM:
9943
    case Mips::ADDU_S_PH_MMR2:
9944
    case Mips::ADDU_S_QB_MM:
9945
    case Mips::ADDWC_MM:
9946
    case Mips::CMPGDU_EQ_QB_MMR2:
9947
    case Mips::CMPGDU_LE_QB_MMR2:
9948
    case Mips::CMPGDU_LT_QB_MMR2:
9949
    case Mips::MODSUB_MM:
9950
    case Mips::MULEQ_S_W_PHL_MM:
9951
    case Mips::MULEQ_S_W_PHR_MM:
9952
    case Mips::MULEU_S_PH_QBL_MM:
9953
    case Mips::MULEU_S_PH_QBR_MM:
9954
    case Mips::MULQ_RS_PH_MM:
9955
    case Mips::MULQ_RS_W_MMR2:
9956
    case Mips::MULQ_S_PH_MMR2:
9957
    case Mips::MULQ_S_W_MMR2:
9958
    case Mips::MUL_PH_MMR2:
9959
    case Mips::MUL_S_PH_MMR2:
9960
    case Mips::PACKRL_PH_MM:
9961
    case Mips::PICK_PH_MM:
9962
    case Mips::PICK_QB_MM:
9963
    case Mips::PRECRQU_S_QB_PH_MM:
9964
    case Mips::PRECRQ_PH_W_MM:
9965
    case Mips::PRECRQ_QB_PH_MM:
9966
    case Mips::PRECRQ_RS_PH_W_MM:
9967
    case Mips::PRECR_QB_PH_MMR2:
9968
    case Mips::SELEQZ_MMR6:
9969
    case Mips::SELNEZ_MMR6:
9970
    case Mips::SUBQH_PH_MMR2:
9971
    case Mips::SUBQH_R_PH_MMR2:
9972
    case Mips::SUBQH_R_W_MMR2:
9973
    case Mips::SUBQH_W_MMR2:
9974
    case Mips::SUBQ_PH_MM:
9975
    case Mips::SUBQ_S_PH_MM:
9976
    case Mips::SUBQ_S_W_MM:
9977
    case Mips::SUBUH_QB_MMR2:
9978
    case Mips::SUBUH_R_QB_MMR2:
9979
    case Mips::SUBU_PH_MMR2:
9980
    case Mips::SUBU_QB_MM:
9981
    case Mips::SUBU_S_PH_MMR2:
9982
    case Mips::SUBU_S_QB_MM: {
9983
      switch (OpNum) {
9984
      case 0:
9985
        // op: rd
9986
        return 11;
9987
      case 1:
9988
        // op: rs
9989
        return 16;
9990
      case 2:
9991
        // op: rt
9992
        return 21;
9993
      }
9994
      break;
9995
    }
9996
    case Mips::MOVF_I:
9997
    case Mips::MOVF_I64:
9998
    case Mips::MOVT_I:
9999
    case Mips::MOVT_I64: {
10000
      switch (OpNum) {
10001
      case 0:
10002
        // op: rd
10003
        return 11;
10004
      case 1:
10005
        // op: rs
10006
        return 21;
10007
      case 2:
10008
        // op: fcc
10009
        return 18;
10010
      }
10011
      break;
10012
    }
10013
    case Mips::ALIGN:
10014
    case Mips::DALIGN: {
10015
      switch (OpNum) {
10016
      case 0:
10017
        // op: rd
10018
        return 11;
10019
      case 1:
10020
        // op: rs
10021
        return 21;
10022
      case 2:
10023
        // op: rt
10024
        return 16;
10025
      case 3:
10026
        // op: bp
10027
        return 6;
10028
      }
10029
      break;
10030
    }
10031
    case Mips::ALIGN_MMR6: {
10032
      switch (OpNum) {
10033
      case 0:
10034
        // op: rd
10035
        return 11;
10036
      case 1:
10037
        // op: rs
10038
        return 21;
10039
      case 2:
10040
        // op: rt
10041
        return 16;
10042
      case 3:
10043
        // op: bp
10044
        return 9;
10045
      }
10046
      break;
10047
    }
10048
    case Mips::DLSA_R6:
10049
    case Mips::LSA_R6: {
10050
      switch (OpNum) {
10051
      case 0:
10052
        // op: rd
10053
        return 11;
10054
      case 1:
10055
        // op: rs
10056
        return 21;
10057
      case 2:
10058
        // op: rt
10059
        return 16;
10060
      case 3:
10061
        // op: imm2
10062
        return 6;
10063
      }
10064
      break;
10065
    }
10066
    case Mips::ADD:
10067
    case Mips::ADDQH_PH:
10068
    case Mips::ADDQH_R_PH:
10069
    case Mips::ADDQH_R_W:
10070
    case Mips::ADDQH_W:
10071
    case Mips::ADDQ_PH:
10072
    case Mips::ADDQ_S_PH:
10073
    case Mips::ADDQ_S_W:
10074
    case Mips::ADDSC:
10075
    case Mips::ADDUH_QB:
10076
    case Mips::ADDUH_R_QB:
10077
    case Mips::ADDU_PH:
10078
    case Mips::ADDU_QB:
10079
    case Mips::ADDU_S_PH:
10080
    case Mips::ADDU_S_QB:
10081
    case Mips::ADDWC:
10082
    case Mips::ADDu:
10083
    case Mips::AND:
10084
    case Mips::AND64:
10085
    case Mips::BADDu:
10086
    case Mips::DADD:
10087
    case Mips::DADDu:
10088
    case Mips::DDIV:
10089
    case Mips::DDIVU:
10090
    case Mips::DIV:
10091
    case Mips::DIVU:
10092
    case Mips::DMOD:
10093
    case Mips::DMODU:
10094
    case Mips::DMUH:
10095
    case Mips::DMUHU:
10096
    case Mips::DMUL:
10097
    case Mips::DMULU:
10098
    case Mips::DMUL_R6:
10099
    case Mips::DSUB:
10100
    case Mips::DSUBu:
10101
    case Mips::MOD:
10102
    case Mips::MODSUB:
10103
    case Mips::MODU:
10104
    case Mips::MOVN_I64_I:
10105
    case Mips::MOVN_I64_I64:
10106
    case Mips::MOVN_I_I:
10107
    case Mips::MOVN_I_I64:
10108
    case Mips::MOVZ_I64_I:
10109
    case Mips::MOVZ_I64_I64:
10110
    case Mips::MOVZ_I_I:
10111
    case Mips::MOVZ_I_I64:
10112
    case Mips::MUH:
10113
    case Mips::MUHU:
10114
    case Mips::MUL:
10115
    case Mips::MULEQ_S_W_PHL:
10116
    case Mips::MULEQ_S_W_PHR:
10117
    case Mips::MULEU_S_PH_QBL:
10118
    case Mips::MULEU_S_PH_QBR:
10119
    case Mips::MULQ_RS_PH:
10120
    case Mips::MULQ_RS_W:
10121
    case Mips::MULQ_S_PH:
10122
    case Mips::MULQ_S_W:
10123
    case Mips::MULU:
10124
    case Mips::MUL_PH:
10125
    case Mips::MUL_R6:
10126
    case Mips::MUL_S_PH:
10127
    case Mips::NOR:
10128
    case Mips::NOR64:
10129
    case Mips::OR:
10130
    case Mips::OR64:
10131
    case Mips::SELEQZ:
10132
    case Mips::SELEQZ64:
10133
    case Mips::SELNEZ:
10134
    case Mips::SELNEZ64:
10135
    case Mips::SEQ:
10136
    case Mips::SLT:
10137
    case Mips::SLT64:
10138
    case Mips::SLTu:
10139
    case Mips::SLTu64:
10140
    case Mips::SNE:
10141
    case Mips::SUB:
10142
    case Mips::SUBQH_PH:
10143
    case Mips::SUBQH_R_PH:
10144
    case Mips::SUBQH_R_W:
10145
    case Mips::SUBQH_W:
10146
    case Mips::SUBQ_PH:
10147
    case Mips::SUBQ_S_PH:
10148
    case Mips::SUBQ_S_W:
10149
    case Mips::SUBUH_QB:
10150
    case Mips::SUBUH_R_QB:
10151
    case Mips::SUBU_PH:
10152
    case Mips::SUBU_QB:
10153
    case Mips::SUBU_S_PH:
10154
    case Mips::SUBU_S_QB:
10155
    case Mips::SUBu:
10156
    case Mips::V3MULU:
10157
    case Mips::VMM0:
10158
    case Mips::VMULU:
10159
    case Mips::XOR:
10160
    case Mips::XOR64: {
10161
      switch (OpNum) {
10162
      case 0:
10163
        // op: rd
10164
        return 11;
10165
      case 1:
10166
        // op: rs
10167
        return 21;
10168
      case 2:
10169
        // op: rt
10170
        return 16;
10171
      }
10172
      break;
10173
    }
10174
    case Mips::CLO:
10175
    case Mips::CLO_R6:
10176
    case Mips::CLZ:
10177
    case Mips::CLZ_R6:
10178
    case Mips::DCLO:
10179
    case Mips::DCLO_R6:
10180
    case Mips::DCLZ:
10181
    case Mips::DCLZ_R6:
10182
    case Mips::DPOP:
10183
    case Mips::JALR:
10184
    case Mips::JALR64:
10185
    case Mips::JALR_HB:
10186
    case Mips::JALR_HB64:
10187
    case Mips::POP:
10188
    case Mips::RADDU_W_QB: {
10189
      switch (OpNum) {
10190
      case 0:
10191
        // op: rd
10192
        return 11;
10193
      case 1:
10194
        // op: rs
10195
        return 21;
10196
      }
10197
      break;
10198
    }
10199
    case Mips::DROTRV:
10200
    case Mips::DSLLV:
10201
    case Mips::DSRAV:
10202
    case Mips::DSRLV:
10203
    case Mips::ROTRV:
10204
    case Mips::SLLV:
10205
    case Mips::SRAV:
10206
    case Mips::SRLV: {
10207
      switch (OpNum) {
10208
      case 0:
10209
        // op: rd
10210
        return 11;
10211
      case 1:
10212
        // op: rt
10213
        return 16;
10214
      case 2:
10215
        // op: rs
10216
        return 21;
10217
      }
10218
      break;
10219
    }
10220
    case Mips::SHLLV_PH:
10221
    case Mips::SHLLV_QB:
10222
    case Mips::SHLLV_S_PH:
10223
    case Mips::SHLLV_S_W:
10224
    case Mips::SHLL_PH:
10225
    case Mips::SHLL_QB:
10226
    case Mips::SHLL_S_PH:
10227
    case Mips::SHLL_S_W:
10228
    case Mips::SHRAV_PH:
10229
    case Mips::SHRAV_QB:
10230
    case Mips::SHRAV_R_PH:
10231
    case Mips::SHRAV_R_QB:
10232
    case Mips::SHRAV_R_W:
10233
    case Mips::SHRA_PH:
10234
    case Mips::SHRA_QB:
10235
    case Mips::SHRA_R_PH:
10236
    case Mips::SHRA_R_QB:
10237
    case Mips::SHRA_R_W:
10238
    case Mips::SHRLV_PH:
10239
    case Mips::SHRLV_QB:
10240
    case Mips::SHRL_PH:
10241
    case Mips::SHRL_QB: {
10242
      switch (OpNum) {
10243
      case 0:
10244
        // op: rd
10245
        return 11;
10246
      case 1:
10247
        // op: rt
10248
        return 16;
10249
      case 2:
10250
        // op: rs_sa
10251
        return 21;
10252
      }
10253
      break;
10254
    }
10255
    case Mips::DROTR:
10256
    case Mips::DROTR32:
10257
    case Mips::DSLL:
10258
    case Mips::DSLL32:
10259
    case Mips::DSRA:
10260
    case Mips::DSRA32:
10261
    case Mips::DSRL:
10262
    case Mips::DSRL32:
10263
    case Mips::ROTR:
10264
    case Mips::SLL:
10265
    case Mips::SRA:
10266
    case Mips::SRL: {
10267
      switch (OpNum) {
10268
      case 0:
10269
        // op: rd
10270
        return 11;
10271
      case 1:
10272
        // op: rt
10273
        return 16;
10274
      case 2:
10275
        // op: shamt
10276
        return 6;
10277
      }
10278
      break;
10279
    }
10280
    case Mips::ABSQ_S_PH:
10281
    case Mips::ABSQ_S_QB:
10282
    case Mips::ABSQ_S_W:
10283
    case Mips::BITREV:
10284
    case Mips::BITSWAP:
10285
    case Mips::DBITSWAP:
10286
    case Mips::DSBH:
10287
    case Mips::DSHD:
10288
    case Mips::DSLL64_32:
10289
    case Mips::PRECEQU_PH_QBL:
10290
    case Mips::PRECEQU_PH_QBLA:
10291
    case Mips::PRECEQU_PH_QBR:
10292
    case Mips::PRECEQU_PH_QBRA:
10293
    case Mips::PRECEQ_W_PHL:
10294
    case Mips::PRECEQ_W_PHR:
10295
    case Mips::PRECEU_PH_QBL:
10296
    case Mips::PRECEU_PH_QBLA:
10297
    case Mips::PRECEU_PH_QBR:
10298
    case Mips::PRECEU_PH_QBRA:
10299
    case Mips::REPLV_PH:
10300
    case Mips::REPLV_QB:
10301
    case Mips::SEB:
10302
    case Mips::SEB64:
10303
    case Mips::SEH:
10304
    case Mips::SEH64:
10305
    case Mips::SLL64_32:
10306
    case Mips::SLL64_64:
10307
    case Mips::WSBH: {
10308
      switch (OpNum) {
10309
      case 0:
10310
        // op: rd
10311
        return 11;
10312
      case 1:
10313
        // op: rt
10314
        return 16;
10315
      }
10316
      break;
10317
    }
10318
    case Mips::ROTRV_MM:
10319
    case Mips::SLLV_MM:
10320
    case Mips::SRAV_MM:
10321
    case Mips::SRLV_MM: {
10322
      switch (OpNum) {
10323
      case 0:
10324
        // op: rd
10325
        return 11;
10326
      case 1:
10327
        // op: rt
10328
        return 21;
10329
      case 2:
10330
        // op: rs
10331
        return 16;
10332
      }
10333
      break;
10334
    }
10335
    case Mips::SHLLV_PH_MM:
10336
    case Mips::SHLLV_QB_MM:
10337
    case Mips::SHLLV_S_PH_MM:
10338
    case Mips::SHLLV_S_W_MM:
10339
    case Mips::SHRAV_PH_MM:
10340
    case Mips::SHRAV_QB_MMR2:
10341
    case Mips::SHRAV_R_PH_MM:
10342
    case Mips::SHRAV_R_QB_MMR2:
10343
    case Mips::SHRAV_R_W_MM:
10344
    case Mips::SHRLV_PH_MMR2:
10345
    case Mips::SHRLV_QB_MM: {
10346
      switch (OpNum) {
10347
      case 0:
10348
        // op: rd
10349
        return 11;
10350
      case 2:
10351
        // op: rs
10352
        return 16;
10353
      case 1:
10354
        // op: rt
10355
        return 21;
10356
      }
10357
      break;
10358
    }
10359
    case Mips::ADDU_MMR6:
10360
    case Mips::ADD_MMR6:
10361
    case Mips::AND_MMR6:
10362
    case Mips::DIVU_MMR6:
10363
    case Mips::DIV_MMR6:
10364
    case Mips::MODU_MMR6:
10365
    case Mips::MOD_MMR6:
10366
    case Mips::MUHU_MMR6:
10367
    case Mips::MUH_MMR6:
10368
    case Mips::MULU_MMR6:
10369
    case Mips::MUL_MMR6:
10370
    case Mips::NOR_MMR6:
10371
    case Mips::OR_MMR6:
10372
    case Mips::SUBU_MMR6:
10373
    case Mips::SUB_MMR6:
10374
    case Mips::XOR_MMR6: {
10375
      switch (OpNum) {
10376
      case 0:
10377
        // op: rd
10378
        return 11;
10379
      case 2:
10380
        // op: rt
10381
        return 21;
10382
      case 1:
10383
        // op: rs
10384
        return 16;
10385
      }
10386
      break;
10387
    }
10388
    case Mips::MFHI:
10389
    case Mips::MFHI64:
10390
    case Mips::MFLO:
10391
    case Mips::MFLO64: {
10392
      switch (OpNum) {
10393
      case 0:
10394
        // op: rd
10395
        return 11;
10396
      }
10397
      break;
10398
    }
10399
    case Mips::BITSWAP_MMR6: {
10400
      switch (OpNum) {
10401
      case 0:
10402
        // op: rd
10403
        return 16;
10404
      case 1:
10405
        // op: rt
10406
        return 21;
10407
      }
10408
      break;
10409
    }
10410
    case Mips::MFHI_MM:
10411
    case Mips::MFLO_MM: {
10412
      switch (OpNum) {
10413
      case 0:
10414
        // op: rd
10415
        return 16;
10416
      }
10417
      break;
10418
    }
10419
    case Mips::MOVF_I_MM:
10420
    case Mips::MOVT_I_MM: {
10421
      switch (OpNum) {
10422
      case 0:
10423
        // op: rd
10424
        return 21;
10425
      case 1:
10426
        // op: rs
10427
        return 16;
10428
      case 2:
10429
        // op: fcc
10430
        return 13;
10431
      }
10432
      break;
10433
    }
10434
    case Mips::CLO_MM:
10435
    case Mips::CLZ_MM: {
10436
      switch (OpNum) {
10437
      case 0:
10438
        // op: rd
10439
        return 21;
10440
      case 1:
10441
        // op: rs
10442
        return 16;
10443
      }
10444
      break;
10445
    }
10446
    case Mips::ROTR_MM:
10447
    case Mips::SLL_MM:
10448
    case Mips::SLL_MMR6:
10449
    case Mips::SRA_MM:
10450
    case Mips::SRL_MM: {
10451
      switch (OpNum) {
10452
      case 0:
10453
        // op: rd
10454
        return 21;
10455
      case 1:
10456
        // op: rt
10457
        return 16;
10458
      case 2:
10459
        // op: shamt
10460
        return 11;
10461
      }
10462
      break;
10463
    }
10464
    case Mips::SEB_MM:
10465
    case Mips::SEH_MM:
10466
    case Mips::WSBH_MM: {
10467
      switch (OpNum) {
10468
      case 0:
10469
        // op: rd
10470
        return 21;
10471
      case 1:
10472
        // op: rt
10473
        return 16;
10474
      }
10475
      break;
10476
    }
10477
    case Mips::CFCMSA: {
10478
      switch (OpNum) {
10479
      case 0:
10480
        // op: rd
10481
        return 6;
10482
      case 1:
10483
        // op: cs
10484
        return 11;
10485
      }
10486
      break;
10487
    }
10488
    case Mips::LI16_MM:
10489
    case Mips::LI16_MMR6: {
10490
      switch (OpNum) {
10491
      case 0:
10492
        // op: rd
10493
        return 7;
10494
      case 1:
10495
        // op: imm
10496
        return 0;
10497
      }
10498
      break;
10499
    }
10500
    case Mips::ADDIUR1SP_MM: {
10501
      switch (OpNum) {
10502
      case 0:
10503
        // op: rd
10504
        return 7;
10505
      case 1:
10506
        // op: imm
10507
        return 1;
10508
      }
10509
      break;
10510
    }
10511
    case Mips::ANDI16_MM:
10512
    case Mips::ANDI16_MMR6: {
10513
      switch (OpNum) {
10514
      case 0:
10515
        // op: rd
10516
        return 7;
10517
      case 1:
10518
        // op: rs
10519
        return 4;
10520
      case 2:
10521
        // op: imm
10522
        return 0;
10523
      }
10524
      break;
10525
    }
10526
    case Mips::ADDIUR2_MM: {
10527
      switch (OpNum) {
10528
      case 0:
10529
        // op: rd
10530
        return 7;
10531
      case 1:
10532
        // op: rs
10533
        return 4;
10534
      case 2:
10535
        // op: imm
10536
        return 1;
10537
      }
10538
      break;
10539
    }
10540
    case Mips::SLL16_MM:
10541
    case Mips::SLL16_MMR6:
10542
    case Mips::SRL16_MM:
10543
    case Mips::SRL16_MMR6: {
10544
      switch (OpNum) {
10545
      case 0:
10546
        // op: rd
10547
        return 7;
10548
      case 1:
10549
        // op: rt
10550
        return 4;
10551
      case 2:
10552
        // op: shamt
10553
        return 1;
10554
      }
10555
      break;
10556
    }
10557
    case Mips::ADDU16_MM:
10558
    case Mips::SUBU16_MM: {
10559
      switch (OpNum) {
10560
      case 0:
10561
        // op: rd
10562
        return 7;
10563
      case 2:
10564
        // op: rt
10565
        return 4;
10566
      case 1:
10567
        // op: rs
10568
        return 1;
10569
      }
10570
      break;
10571
    }
10572
    case Mips::JALR16_MM:
10573
    case Mips::JALRS16_MM:
10574
    case Mips::JR16_MM:
10575
    case Mips::JRC16_MM: {
10576
      switch (OpNum) {
10577
      case 0:
10578
        // op: rs
10579
        return 0;
10580
      }
10581
      break;
10582
    }
10583
    case Mips::MFHI_DSP_MM:
10584
    case Mips::MFLO_DSP_MM: {
10585
      switch (OpNum) {
10586
      case 0:
10587
        // op: rs
10588
        return 16;
10589
      case 1:
10590
        // op: ac
10591
        return 14;
10592
      }
10593
      break;
10594
    }
10595
    case Mips::TEQI_MM:
10596
    case Mips::TGEIU_MM:
10597
    case Mips::TGEI_MM:
10598
    case Mips::TLTIU_MM:
10599
    case Mips::TLTI_MM:
10600
    case Mips::TNEI_MM: {
10601
      switch (OpNum) {
10602
      case 0:
10603
        // op: rs
10604
        return 16;
10605
      case 1:
10606
        // op: imm16
10607
        return 0;
10608
      }
10609
      break;
10610
    }
10611
    case Mips::BEQZC_MM:
10612
    case Mips::BGEZALS_MM:
10613
    case Mips::BGEZAL_MM:
10614
    case Mips::BGEZ_MM:
10615
    case Mips::BGTZ_MM:
10616
    case Mips::BLEZ_MM:
10617
    case Mips::BLTZALS_MM:
10618
    case Mips::BLTZAL_MM:
10619
    case Mips::BLTZ_MM:
10620
    case Mips::BNEZC_MM: {
10621
      switch (OpNum) {
10622
      case 0:
10623
        // op: rs
10624
        return 16;
10625
      case 1:
10626
        // op: offset
10627
        return 0;
10628
      }
10629
      break;
10630
    }
10631
    case Mips::TEQ_MM:
10632
    case Mips::TGEU_MM:
10633
    case Mips::TGE_MM:
10634
    case Mips::TLTU_MM:
10635
    case Mips::TLT_MM:
10636
    case Mips::TNE_MM: {
10637
      switch (OpNum) {
10638
      case 0:
10639
        // op: rs
10640
        return 16;
10641
      case 1:
10642
        // op: rt
10643
        return 21;
10644
      case 2:
10645
        // op: code_
10646
        return 12;
10647
      }
10648
      break;
10649
    }
10650
    case Mips::BEQ_MM:
10651
    case Mips::BNE_MM: {
10652
      switch (OpNum) {
10653
      case 0:
10654
        // op: rs
10655
        return 16;
10656
      case 1:
10657
        // op: rt
10658
        return 21;
10659
      case 2:
10660
        // op: offset
10661
        return 0;
10662
      }
10663
      break;
10664
    }
10665
    case Mips::MADDU_MM:
10666
    case Mips::MADD_MM:
10667
    case Mips::MSUBU_MM:
10668
    case Mips::MSUB_MM:
10669
    case Mips::MULT_MM:
10670
    case Mips::MULTu_MM:
10671
    case Mips::SDIV_MM:
10672
    case Mips::UDIV_MM: {
10673
      switch (OpNum) {
10674
      case 0:
10675
        // op: rs
10676
        return 16;
10677
      case 1:
10678
        // op: rt
10679
        return 21;
10680
      }
10681
      break;
10682
    }
10683
    case Mips::GINVT_MMR6: {
10684
      switch (OpNum) {
10685
      case 0:
10686
        // op: rs
10687
        return 16;
10688
      case 1:
10689
        // op: type
10690
        return 9;
10691
      }
10692
      break;
10693
    }
10694
    case Mips::DVP_MMR6:
10695
    case Mips::EVP_MMR6:
10696
    case Mips::GINVI_MMR6:
10697
    case Mips::JR_MM:
10698
    case Mips::MTHI_MM:
10699
    case Mips::MTLO_MM: {
10700
      switch (OpNum) {
10701
      case 0:
10702
        // op: rs
10703
        return 16;
10704
      }
10705
      break;
10706
    }
10707
    case Mips::ADDIUPC:
10708
    case Mips::ALUIPC:
10709
    case Mips::AUIPC:
10710
    case Mips::LDPC:
10711
    case Mips::LWPC:
10712
    case Mips::LWUPC: {
10713
      switch (OpNum) {
10714
      case 0:
10715
        // op: rs
10716
        return 21;
10717
      case 1:
10718
        // op: imm
10719
        return 0;
10720
      }
10721
      break;
10722
    }
10723
    case Mips::TEQI:
10724
    case Mips::TGEI:
10725
    case Mips::TGEIU:
10726
    case Mips::TLTI:
10727
    case Mips::TNEI:
10728
    case Mips::TTLTIU: {
10729
      switch (OpNum) {
10730
      case 0:
10731
        // op: rs
10732
        return 21;
10733
      case 1:
10734
        // op: imm16
10735
        return 0;
10736
      }
10737
      break;
10738
    }
10739
    case Mips::WRDSP: {
10740
      switch (OpNum) {
10741
      case 0:
10742
        // op: rs
10743
        return 21;
10744
      case 1:
10745
        // op: mask
10746
        return 11;
10747
      }
10748
      break;
10749
    }
10750
    case Mips::BEQZC:
10751
    case Mips::BEQZC64:
10752
    case Mips::BEQZC_MMR6:
10753
    case Mips::BGEZ:
10754
    case Mips::BGEZ64:
10755
    case Mips::BGEZAL:
10756
    case Mips::BGEZALL:
10757
    case Mips::BGEZL:
10758
    case Mips::BGTZ:
10759
    case Mips::BGTZ64:
10760
    case Mips::BGTZL:
10761
    case Mips::BLEZ:
10762
    case Mips::BLEZ64:
10763
    case Mips::BLEZL:
10764
    case Mips::BLTZ:
10765
    case Mips::BLTZ64:
10766
    case Mips::BLTZAL:
10767
    case Mips::BLTZALL:
10768
    case Mips::BLTZL:
10769
    case Mips::BNEZC:
10770
    case Mips::BNEZC64:
10771
    case Mips::BNEZC_MMR6: {
10772
      switch (OpNum) {
10773
      case 0:
10774
        // op: rs
10775
        return 21;
10776
      case 1:
10777
        // op: offset
10778
        return 0;
10779
      }
10780
      break;
10781
    }
10782
    case Mips::BBIT0:
10783
    case Mips::BBIT1:
10784
    case Mips::BBIT032:
10785
    case Mips::BBIT132: {
10786
      switch (OpNum) {
10787
      case 0:
10788
        // op: rs
10789
        return 21;
10790
      case 1:
10791
        // op: p
10792
        return 16;
10793
      case 2:
10794
        // op: offset
10795
        return 0;
10796
      }
10797
      break;
10798
    }
10799
    case Mips::TEQ:
10800
    case Mips::TGE:
10801
    case Mips::TGEU:
10802
    case Mips::TLT:
10803
    case Mips::TLTU:
10804
    case Mips::TNE: {
10805
      switch (OpNum) {
10806
      case 0:
10807
        // op: rs
10808
        return 21;
10809
      case 1:
10810
        // op: rt
10811
        return 16;
10812
      case 2:
10813
        // op: code_
10814
        return 6;
10815
      }
10816
      break;
10817
    }
10818
    case Mips::BEQ:
10819
    case Mips::BEQ64:
10820
    case Mips::BEQC:
10821
    case Mips::BEQC64:
10822
    case Mips::BEQL:
10823
    case Mips::BGEC:
10824
    case Mips::BGEC64:
10825
    case Mips::BGEUC:
10826
    case Mips::BGEUC64:
10827
    case Mips::BLTC:
10828
    case Mips::BLTC64:
10829
    case Mips::BLTUC:
10830
    case Mips::BLTUC64:
10831
    case Mips::BNE:
10832
    case Mips::BNE64:
10833
    case Mips::BNEC:
10834
    case Mips::BNEC64:
10835
    case Mips::BNEL:
10836
    case Mips::BNVC:
10837
    case Mips::BOVC: {
10838
      switch (OpNum) {
10839
      case 0:
10840
        // op: rs
10841
        return 21;
10842
      case 1:
10843
        // op: rt
10844
        return 16;
10845
      case 2:
10846
        // op: offset
10847
        return 0;
10848
      }
10849
      break;
10850
    }
10851
    case Mips::CMPU_EQ_QB:
10852
    case Mips::CMPU_LE_QB:
10853
    case Mips::CMPU_LT_QB:
10854
    case Mips::CMP_EQ_PH:
10855
    case Mips::CMP_LE_PH:
10856
    case Mips::CMP_LT_PH:
10857
    case Mips::DMULT:
10858
    case Mips::DMULTu:
10859
    case Mips::DSDIV:
10860
    case Mips::DUDIV:
10861
    case Mips::MADD:
10862
    case Mips::MADDU:
10863
    case Mips::MSUB:
10864
    case Mips::MSUBU:
10865
    case Mips::MULT:
10866
    case Mips::MULTu:
10867
    case Mips::SDIV:
10868
    case Mips::UDIV: {
10869
      switch (OpNum) {
10870
      case 0:
10871
        // op: rs
10872
        return 21;
10873
      case 1:
10874
        // op: rt
10875
        return 16;
10876
      }
10877
      break;
10878
    }
10879
    case Mips::GINVT: {
10880
      switch (OpNum) {
10881
      case 0:
10882
        // op: rs
10883
        return 21;
10884
      case 1:
10885
        // op: type_
10886
        return 8;
10887
      }
10888
      break;
10889
    }
10890
    case Mips::DAHI:
10891
    case Mips::DATI: {
10892
      switch (OpNum) {
10893
      case 0:
10894
        // op: rs
10895
        return 21;
10896
      case 2:
10897
        // op: imm
10898
        return 0;
10899
      }
10900
      break;
10901
    }
10902
    case Mips::FORK: {
10903
      switch (OpNum) {
10904
      case 0:
10905
        // op: rs
10906
        return 21;
10907
      case 2:
10908
        // op: rt
10909
        return 16;
10910
      case 1:
10911
        // op: rd
10912
        return 11;
10913
      }
10914
      break;
10915
    }
10916
    case Mips::GINVI:
10917
    case Mips::JR:
10918
    case Mips::JR64:
10919
    case Mips::JR_HB:
10920
    case Mips::JR_HB64:
10921
    case Mips::JR_HB64_R6:
10922
    case Mips::JR_HB_R6:
10923
    case Mips::MTHI:
10924
    case Mips::MTHI64:
10925
    case Mips::MTLO:
10926
    case Mips::MTLO64:
10927
    case Mips::MTM0:
10928
    case Mips::MTM1:
10929
    case Mips::MTM2:
10930
    case Mips::MTP0:
10931
    case Mips::MTP1:
10932
    case Mips::MTP2: {
10933
      switch (OpNum) {
10934
      case 0:
10935
        // op: rs
10936
        return 21;
10937
      }
10938
      break;
10939
    }
10940
    case Mips::ADDIUPC_MM: {
10941
      switch (OpNum) {
10942
      case 0:
10943
        // op: rs
10944
        return 23;
10945
      case 1:
10946
        // op: imm
10947
        return 0;
10948
      }
10949
      break;
10950
    }
10951
    case Mips::JALRC16_MMR6:
10952
    case Mips::JRC16_MMR6: {
10953
      switch (OpNum) {
10954
      case 0:
10955
        // op: rs
10956
        return 5;
10957
      }
10958
      break;
10959
    }
10960
    case Mips::BEQZ16_MM:
10961
    case Mips::BEQZC16_MMR6:
10962
    case Mips::BNEZ16_MM:
10963
    case Mips::BNEZC16_MMR6: {
10964
      switch (OpNum) {
10965
      case 0:
10966
        // op: rs
10967
        return 7;
10968
      case 1:
10969
        // op: offset
10970
        return 0;
10971
      }
10972
      break;
10973
    }
10974
    case Mips::EXTP:
10975
    case Mips::EXTPDP:
10976
    case Mips::EXTPDPV:
10977
    case Mips::EXTPV:
10978
    case Mips::EXTRV_RS_W:
10979
    case Mips::EXTRV_R_W:
10980
    case Mips::EXTRV_S_H:
10981
    case Mips::EXTRV_W:
10982
    case Mips::EXTR_RS_W:
10983
    case Mips::EXTR_R_W:
10984
    case Mips::EXTR_S_H:
10985
    case Mips::EXTR_W: {
10986
      switch (OpNum) {
10987
      case 0:
10988
        // op: rt
10989
        return 16;
10990
      case 1:
10991
        // op: ac
10992
        return 11;
10993
      case 2:
10994
        // op: shift_rs
10995
        return 21;
10996
      }
10997
      break;
10998
    }
10999
    case Mips::LB:
11000
    case Mips::LB64:
11001
    case Mips::LBu:
11002
    case Mips::LBu64:
11003
    case Mips::LD:
11004
    case Mips::LDC1:
11005
    case Mips::LDC2:
11006
    case Mips::LDC2_R6:
11007
    case Mips::LDC3:
11008
    case Mips::LDC164:
11009
    case Mips::LDL:
11010
    case Mips::LDR:
11011
    case Mips::LEA_ADDiu:
11012
    case Mips::LEA_ADDiu64:
11013
    case Mips::LH:
11014
    case Mips::LH64:
11015
    case Mips::LHu:
11016
    case Mips::LHu64:
11017
    case Mips::LL:
11018
    case Mips::LL64:
11019
    case Mips::LLD:
11020
    case Mips::LW:
11021
    case Mips::LW64:
11022
    case Mips::LWC1:
11023
    case Mips::LWC2:
11024
    case Mips::LWC2_R6:
11025
    case Mips::LWC3:
11026
    case Mips::LWDSP:
11027
    case Mips::LWL:
11028
    case Mips::LWL64:
11029
    case Mips::LWR:
11030
    case Mips::LWR64:
11031
    case Mips::LWu:
11032
    case Mips::SB:
11033
    case Mips::SB64:
11034
    case Mips::SD:
11035
    case Mips::SDC1:
11036
    case Mips::SDC2:
11037
    case Mips::SDC2_R6:
11038
    case Mips::SDC3:
11039
    case Mips::SDC164:
11040
    case Mips::SDL:
11041
    case Mips::SDR:
11042
    case Mips::SH:
11043
    case Mips::SH64:
11044
    case Mips::SW:
11045
    case Mips::SW64:
11046
    case Mips::SWC1:
11047
    case Mips::SWC2:
11048
    case Mips::SWC2_R6:
11049
    case Mips::SWC3:
11050
    case Mips::SWDSP:
11051
    case Mips::SWL:
11052
    case Mips::SWL64:
11053
    case Mips::SWR:
11054
    case Mips::SWR64: {
11055
      switch (OpNum) {
11056
      case 0:
11057
        // op: rt
11058
        return 16;
11059
      case 1:
11060
        // op: addr
11061
        return 0;
11062
      }
11063
      break;
11064
    }
11065
    case Mips::LL64_R6:
11066
    case Mips::LLD_R6:
11067
    case Mips::LL_R6: {
11068
      switch (OpNum) {
11069
      case 0:
11070
        // op: rt
11071
        return 16;
11072
      case 1:
11073
        // op: addr
11074
        return 7;
11075
      }
11076
      break;
11077
    }
11078
    case Mips::CFC1:
11079
    case Mips::DMFC1:
11080
    case Mips::MFC1:
11081
    case Mips::MFC1_D64:
11082
    case Mips::MFHC1_D32:
11083
    case Mips::MFHC1_D64: {
11084
      switch (OpNum) {
11085
      case 0:
11086
        // op: rt
11087
        return 16;
11088
      case 1:
11089
        // op: fs
11090
        return 11;
11091
      }
11092
      break;
11093
    }
11094
    case Mips::DMFC2_OCTEON:
11095
    case Mips::DMTC2_OCTEON:
11096
    case Mips::LUi:
11097
    case Mips::LUi64:
11098
    case Mips::LUi_MM: {
11099
      switch (OpNum) {
11100
      case 0:
11101
        // op: rt
11102
        return 16;
11103
      case 1:
11104
        // op: imm16
11105
        return 0;
11106
      }
11107
      break;
11108
    }
11109
    case Mips::BC1EQZC_MMR6:
11110
    case Mips::BC1NEZC_MMR6:
11111
    case Mips::BC2EQZC_MMR6:
11112
    case Mips::BC2NEZC_MMR6:
11113
    case Mips::BEQZALC:
11114
    case Mips::BGEZALC:
11115
    case Mips::BGEZALC_MMR6:
11116
    case Mips::BGEZC:
11117
    case Mips::BGEZC64:
11118
    case Mips::BGEZC_MMR6:
11119
    case Mips::BGTZALC:
11120
    case Mips::BGTZC:
11121
    case Mips::BGTZC64:
11122
    case Mips::BLEZALC:
11123
    case Mips::BLEZC:
11124
    case Mips::BLEZC64:
11125
    case Mips::BLTZALC:
11126
    case Mips::BLTZALC_MMR6:
11127
    case Mips::BLTZC:
11128
    case Mips::BLTZC64:
11129
    case Mips::BLTZC_MMR6:
11130
    case Mips::BNEZALC:
11131
    case Mips::JIALC:
11132
    case Mips::JIALC64:
11133
    case Mips::JIALC_MMR6:
11134
    case Mips::JIC:
11135
    case Mips::JIC64:
11136
    case Mips::JIC_MMR6: {
11137
      switch (OpNum) {
11138
      case 0:
11139
        // op: rt
11140
        return 16;
11141
      case 1:
11142
        // op: offset
11143
        return 0;
11144
      }
11145
      break;
11146
    }
11147
    case Mips::DMFC0:
11148
    case Mips::DMFC2:
11149
    case Mips::DMFGC0:
11150
    case Mips::MFC0:
11151
    case Mips::MFC2:
11152
    case Mips::MFGC0:
11153
    case Mips::MFHGC0: {
11154
      switch (OpNum) {
11155
      case 0:
11156
        // op: rt
11157
        return 16;
11158
      case 1:
11159
        // op: rd
11160
        return 11;
11161
      case 2:
11162
        // op: sel
11163
        return 0;
11164
      }
11165
      break;
11166
    }
11167
    case Mips::RDHWR:
11168
    case Mips::RDHWR64: {
11169
      switch (OpNum) {
11170
      case 0:
11171
        // op: rt
11172
        return 16;
11173
      case 1:
11174
        // op: rd
11175
        return 11;
11176
      case 2:
11177
        // op: sel
11178
        return 6;
11179
      }
11180
      break;
11181
    }
11182
    case Mips::SLTi:
11183
    case Mips::SLTi64:
11184
    case Mips::SLTiu:
11185
    case Mips::SLTiu64: {
11186
      switch (OpNum) {
11187
      case 0:
11188
        // op: rt
11189
        return 16;
11190
      case 1:
11191
        // op: rs
11192
        return 21;
11193
      case 2:
11194
        // op: imm16
11195
        return 0;
11196
      }
11197
      break;
11198
    }
11199
    case Mips::CINS:
11200
    case Mips::CINS32:
11201
    case Mips::CINS64_32:
11202
    case Mips::CINS_i32:
11203
    case Mips::EXTS:
11204
    case Mips::EXTS32: {
11205
      switch (OpNum) {
11206
      case 0:
11207
        // op: rt
11208
        return 16;
11209
      case 1:
11210
        // op: rs
11211
        return 21;
11212
      case 2:
11213
        // op: pos
11214
        return 6;
11215
      case 3:
11216
        // op: lenm1
11217
        return 11;
11218
      }
11219
      break;
11220
    }
11221
    case Mips::DEXT:
11222
    case Mips::DEXT64_32:
11223
    case Mips::DEXTM:
11224
    case Mips::DEXTU:
11225
    case Mips::DINS:
11226
    case Mips::DINSM:
11227
    case Mips::DINSU:
11228
    case Mips::EXT:
11229
    case Mips::INS: {
11230
      switch (OpNum) {
11231
      case 0:
11232
        // op: rt
11233
        return 16;
11234
      case 1:
11235
        // op: rs
11236
        return 21;
11237
      case 2:
11238
        // op: pos
11239
        return 6;
11240
      case 3:
11241
        // op: size
11242
        return 11;
11243
      }
11244
      break;
11245
    }
11246
    case Mips::APPEND:
11247
    case Mips::BALIGN:
11248
    case Mips::PREPEND: {
11249
      switch (OpNum) {
11250
      case 0:
11251
        // op: rt
11252
        return 16;
11253
      case 1:
11254
        // op: rs
11255
        return 21;
11256
      case 2:
11257
        // op: sa
11258
        return 11;
11259
      }
11260
      break;
11261
    }
11262
    case Mips::SAA:
11263
    case Mips::SAAD: {
11264
      switch (OpNum) {
11265
      case 0:
11266
        // op: rt
11267
        return 16;
11268
      case 1:
11269
        // op: rs
11270
        return 21;
11271
      }
11272
      break;
11273
    }
11274
    case Mips::INSV: {
11275
      switch (OpNum) {
11276
      case 0:
11277
        // op: rt
11278
        return 16;
11279
      case 2:
11280
        // op: rs
11281
        return 21;
11282
      }
11283
      break;
11284
    }
11285
    case Mips::DI:
11286
    case Mips::DI_MM:
11287
    case Mips::DI_MMR6:
11288
    case Mips::DMT:
11289
    case Mips::DVP:
11290
    case Mips::DVPE:
11291
    case Mips::EI:
11292
    case Mips::EI_MM:
11293
    case Mips::EI_MMR6:
11294
    case Mips::EMT:
11295
    case Mips::EVP:
11296
    case Mips::EVPE: {
11297
      switch (OpNum) {
11298
      case 0:
11299
        // op: rt
11300
        return 16;
11301
      }
11302
      break;
11303
    }
11304
    case Mips::LBE_MM:
11305
    case Mips::LB_MM:
11306
    case Mips::LBuE_MM:
11307
    case Mips::LBu_MM:
11308
    case Mips::LDC1_MM_D32:
11309
    case Mips::LDC1_MM_D64:
11310
    case Mips::LDC2_MMR6:
11311
    case Mips::LEA_ADDiu_MM:
11312
    case Mips::LHE_MM:
11313
    case Mips::LH_MM:
11314
    case Mips::LHuE_MM:
11315
    case Mips::LHu_MM:
11316
    case Mips::LLE_MM:
11317
    case Mips::LL_MM:
11318
    case Mips::LL_MMR6:
11319
    case Mips::LWC1_MM:
11320
    case Mips::LWC2_MMR6:
11321
    case Mips::LWDSP_MM:
11322
    case Mips::LWE_MM:
11323
    case Mips::LWLE_MM:
11324
    case Mips::LWL_MM:
11325
    case Mips::LWM32_MM:
11326
    case Mips::LWRE_MM:
11327
    case Mips::LWR_MM:
11328
    case Mips::LWU_MM:
11329
    case Mips::LW_MM:
11330
    case Mips::LW_MMR6:
11331
    case Mips::SBE_MM:
11332
    case Mips::SB_MM:
11333
    case Mips::SB_MMR6:
11334
    case Mips::SDC1_MM_D32:
11335
    case Mips::SDC1_MM_D64:
11336
    case Mips::SDC2_MMR6:
11337
    case Mips::SHE_MM:
11338
    case Mips::SH_MM:
11339
    case Mips::SH_MMR6:
11340
    case Mips::SWC1_MM:
11341
    case Mips::SWC2_MMR6:
11342
    case Mips::SWDSP_MM:
11343
    case Mips::SWE_MM:
11344
    case Mips::SWLE_MM:
11345
    case Mips::SWL_MM:
11346
    case Mips::SWM32_MM:
11347
    case Mips::SWRE_MM:
11348
    case Mips::SWR_MM:
11349
    case Mips::SW_MM:
11350
    case Mips::SW_MMR6: {
11351
      switch (OpNum) {
11352
      case 0:
11353
        // op: rt
11354
        return 21;
11355
      case 1:
11356
        // op: addr
11357
        return 0;
11358
      }
11359
      break;
11360
    }
11361
    case Mips::CFC1_MM:
11362
    case Mips::MFC1_MM:
11363
    case Mips::MFC1_MMR6:
11364
    case Mips::MFHC1_D32_MM:
11365
    case Mips::MFHC1_D64_MM: {
11366
      switch (OpNum) {
11367
      case 0:
11368
        // op: rt
11369
        return 21;
11370
      case 1:
11371
        // op: fs
11372
        return 16;
11373
      }
11374
      break;
11375
    }
11376
    case Mips::ADDIUPC_MMR6:
11377
    case Mips::ALUIPC_MMR6:
11378
    case Mips::AUIPC_MMR6:
11379
    case Mips::LWPC_MMR6: {
11380
      switch (OpNum) {
11381
      case 0:
11382
        // op: rt
11383
        return 21;
11384
      case 1:
11385
        // op: imm
11386
        return 0;
11387
      }
11388
      break;
11389
    }
11390
    case Mips::REPL_QB_MM: {
11391
      switch (OpNum) {
11392
      case 0:
11393
        // op: rt
11394
        return 21;
11395
      case 1:
11396
        // op: imm
11397
        return 13;
11398
      }
11399
      break;
11400
    }
11401
    case Mips::LUI_MMR6: {
11402
      switch (OpNum) {
11403
      case 0:
11404
        // op: rt
11405
        return 21;
11406
      case 1:
11407
        // op: imm16
11408
        return 0;
11409
      }
11410
      break;
11411
    }
11412
    case Mips::CFC2_MM:
11413
    case Mips::MFC2_MMR6:
11414
    case Mips::MFHC2_MMR6: {
11415
      switch (OpNum) {
11416
      case 0:
11417
        // op: rt
11418
        return 21;
11419
      case 1:
11420
        // op: impl
11421
        return 16;
11422
      }
11423
      break;
11424
    }
11425
    case Mips::RDDSP_MM:
11426
    case Mips::WRDSP_MM: {
11427
      switch (OpNum) {
11428
      case 0:
11429
        // op: rt
11430
        return 21;
11431
      case 1:
11432
        // op: mask
11433
        return 14;
11434
      }
11435
      break;
11436
    }
11437
    case Mips::BEQZALC_MMR6:
11438
    case Mips::BGTZALC_MMR6:
11439
    case Mips::BGTZC_MMR6:
11440
    case Mips::BLEZALC_MMR6:
11441
    case Mips::BLEZC_MMR6:
11442
    case Mips::BNEZALC_MMR6: {
11443
      switch (OpNum) {
11444
      case 0:
11445
        // op: rt
11446
        return 21;
11447
      case 1:
11448
        // op: offset
11449
        return 0;
11450
      }
11451
      break;
11452
    }
11453
    case Mips::RDHWR_MM:
11454
    case Mips::RDPGPR_MMR6: {
11455
      switch (OpNum) {
11456
      case 0:
11457
        // op: rt
11458
        return 21;
11459
      case 1:
11460
        // op: rd
11461
        return 16;
11462
      }
11463
      break;
11464
    }
11465
    case Mips::BALIGN_MMR2: {
11466
      switch (OpNum) {
11467
      case 0:
11468
        // op: rt
11469
        return 21;
11470
      case 1:
11471
        // op: rs
11472
        return 16;
11473
      case 2:
11474
        // op: bp
11475
        return 14;
11476
      }
11477
      break;
11478
    }
11479
    case Mips::ADDIU_MMR6:
11480
    case Mips::ANDI_MMR6:
11481
    case Mips::ORI_MMR6:
11482
    case Mips::SLTi_MM:
11483
    case Mips::SLTiu_MM:
11484
    case Mips::XORI_MMR6: {
11485
      switch (OpNum) {
11486
      case 0:
11487
        // op: rt
11488
        return 21;
11489
      case 1:
11490
        // op: rs
11491
        return 16;
11492
      case 2:
11493
        // op: imm16
11494
        return 0;
11495
      }
11496
      break;
11497
    }
11498
    case Mips::BNVC_MMR6:
11499
    case Mips::BOVC_MMR6: {
11500
      switch (OpNum) {
11501
      case 0:
11502
        // op: rt
11503
        return 21;
11504
      case 1:
11505
        // op: rs
11506
        return 16;
11507
      case 2:
11508
        // op: offset
11509
        return 0;
11510
      }
11511
      break;
11512
    }
11513
    case Mips::EXT_MM:
11514
    case Mips::INS_MM: {
11515
      switch (OpNum) {
11516
      case 0:
11517
        // op: rt
11518
        return 21;
11519
      case 1:
11520
        // op: rs
11521
        return 16;
11522
      case 2:
11523
        // op: pos
11524
        return 6;
11525
      case 3:
11526
        // op: size
11527
        return 11;
11528
      }
11529
      break;
11530
    }
11531
    case Mips::APPEND_MMR2:
11532
    case Mips::PRECR_SRA_PH_W_MMR2:
11533
    case Mips::PRECR_SRA_R_PH_W_MMR2:
11534
    case Mips::PREPEND_MMR2:
11535
    case Mips::SHLL_S_W_MM:
11536
    case Mips::SHRA_R_W_MM: {
11537
      switch (OpNum) {
11538
      case 0:
11539
        // op: rt
11540
        return 21;
11541
      case 1:
11542
        // op: rs
11543
        return 16;
11544
      case 2:
11545
        // op: sa
11546
        return 11;
11547
      }
11548
      break;
11549
    }
11550
    case Mips::SHLL_PH_MM:
11551
    case Mips::SHLL_S_PH_MM:
11552
    case Mips::SHRA_PH_MM:
11553
    case Mips::SHRA_R_PH_MM:
11554
    case Mips::SHRL_PH_MMR2: {
11555
      switch (OpNum) {
11556
      case 0:
11557
        // op: rt
11558
        return 21;
11559
      case 1:
11560
        // op: rs
11561
        return 16;
11562
      case 2:
11563
        // op: sa
11564
        return 12;
11565
      }
11566
      break;
11567
    }
11568
    case Mips::SHLL_QB_MM:
11569
    case Mips::SHRA_QB_MMR2:
11570
    case Mips::SHRA_R_QB_MMR2:
11571
    case Mips::SHRL_QB_MM: {
11572
      switch (OpNum) {
11573
      case 0:
11574
        // op: rt
11575
        return 21;
11576
      case 1:
11577
        // op: rs
11578
        return 16;
11579
      case 2:
11580
        // op: sa
11581
        return 13;
11582
      }
11583
      break;
11584
    }
11585
    case Mips::MFC0_MMR6:
11586
    case Mips::MFGC0_MM:
11587
    case Mips::MFHC0_MMR6:
11588
    case Mips::MFHGC0_MM:
11589
    case Mips::RDHWR_MMR6: {
11590
      switch (OpNum) {
11591
      case 0:
11592
        // op: rt
11593
        return 21;
11594
      case 1:
11595
        // op: rs
11596
        return 16;
11597
      case 2:
11598
        // op: sel
11599
        return 11;
11600
      }
11601
      break;
11602
    }
11603
    case Mips::EXT_MMR6:
11604
    case Mips::INS_MMR6: {
11605
      switch (OpNum) {
11606
      case 0:
11607
        // op: rt
11608
        return 21;
11609
      case 1:
11610
        // op: rs
11611
        return 16;
11612
      case 3:
11613
        // op: size
11614
        return 11;
11615
      case 2:
11616
        // op: pos
11617
        return 6;
11618
      }
11619
      break;
11620
    }
11621
    case Mips::ABSQ_S_PH_MM:
11622
    case Mips::ABSQ_S_QB_MMR2:
11623
    case Mips::ABSQ_S_W_MM:
11624
    case Mips::BITREV_MM:
11625
    case Mips::JALRC_HB_MMR6:
11626
    case Mips::JALRC_MMR6:
11627
    case Mips::PRECEQU_PH_QBLA_MM:
11628
    case Mips::PRECEQU_PH_QBL_MM:
11629
    case Mips::PRECEQU_PH_QBRA_MM:
11630
    case Mips::PRECEQU_PH_QBR_MM:
11631
    case Mips::PRECEQ_W_PHL_MM:
11632
    case Mips::PRECEQ_W_PHR_MM:
11633
    case Mips::PRECEU_PH_QBLA_MM:
11634
    case Mips::PRECEU_PH_QBL_MM:
11635
    case Mips::PRECEU_PH_QBRA_MM:
11636
    case Mips::PRECEU_PH_QBR_MM:
11637
    case Mips::RADDU_W_QB_MM:
11638
    case Mips::REPLV_PH_MM:
11639
    case Mips::REPLV_QB_MM:
11640
    case Mips::WRPGPR_MMR6:
11641
    case Mips::WSBH_MMR6: {
11642
      switch (OpNum) {
11643
      case 0:
11644
        // op: rt
11645
        return 21;
11646
      case 1:
11647
        // op: rs
11648
        return 16;
11649
      }
11650
      break;
11651
    }
11652
    case Mips::LWP_MM:
11653
    case Mips::SWP_MM: {
11654
      switch (OpNum) {
11655
      case 0:
11656
        // op: rt
11657
        return 21;
11658
      case 2:
11659
        // op: addr
11660
        return 0;
11661
      }
11662
      break;
11663
    }
11664
    case Mips::EXTPDP_MM:
11665
    case Mips::EXTP_MM:
11666
    case Mips::EXTR_RS_W_MM:
11667
    case Mips::EXTR_R_W_MM:
11668
    case Mips::EXTR_S_H_MM:
11669
    case Mips::EXTR_W_MM: {
11670
      switch (OpNum) {
11671
      case 0:
11672
        // op: rt
11673
        return 21;
11674
      case 2:
11675
        // op: imm
11676
        return 16;
11677
      case 1:
11678
        // op: ac
11679
        return 14;
11680
      }
11681
      break;
11682
    }
11683
    case Mips::EXTPDPV_MM:
11684
    case Mips::EXTPV_MM:
11685
    case Mips::EXTRV_RS_W_MM:
11686
    case Mips::EXTRV_R_W_MM:
11687
    case Mips::EXTRV_S_H_MM:
11688
    case Mips::EXTRV_W_MM: {
11689
      switch (OpNum) {
11690
      case 0:
11691
        // op: rt
11692
        return 21;
11693
      case 2:
11694
        // op: rs
11695
        return 16;
11696
      case 1:
11697
        // op: ac
11698
        return 14;
11699
      }
11700
      break;
11701
    }
11702
    case Mips::INSV_MM: {
11703
      switch (OpNum) {
11704
      case 0:
11705
        // op: rt
11706
        return 21;
11707
      case 2:
11708
        // op: rs
11709
        return 16;
11710
      }
11711
      break;
11712
    }
11713
    case Mips::NOT16_MM: {
11714
      switch (OpNum) {
11715
      case 0:
11716
        // op: rt
11717
        return 3;
11718
      case 1:
11719
        // op: rs
11720
        return 0;
11721
      }
11722
      break;
11723
    }
11724
    case Mips::LWM16_MM:
11725
    case Mips::SWM16_MM: {
11726
      switch (OpNum) {
11727
      case 0:
11728
        // op: rt
11729
        return 4;
11730
      case 1:
11731
        // op: addr
11732
        return 0;
11733
      }
11734
      break;
11735
    }
11736
    case Mips::LWSP_MM:
11737
    case Mips::SWSP_MM:
11738
    case Mips::SWSP_MMR6: {
11739
      switch (OpNum) {
11740
      case 0:
11741
        // op: rt
11742
        return 5;
11743
      case 1:
11744
        // op: offset
11745
        return 0;
11746
      }
11747
      break;
11748
    }
11749
    case Mips::LBU16_MM:
11750
    case Mips::LHU16_MM:
11751
    case Mips::LW16_MM:
11752
    case Mips::SB16_MM:
11753
    case Mips::SB16_MMR6:
11754
    case Mips::SH16_MM:
11755
    case Mips::SH16_MMR6:
11756
    case Mips::SW16_MM:
11757
    case Mips::SW16_MMR6: {
11758
      switch (OpNum) {
11759
      case 0:
11760
        // op: rt
11761
        return 7;
11762
      case 1:
11763
        // op: addr
11764
        return 0;
11765
      }
11766
      break;
11767
    }
11768
    case Mips::LWGP_MM: {
11769
      switch (OpNum) {
11770
      case 0:
11771
        // op: rt
11772
        return 7;
11773
      case 1:
11774
        // op: offset
11775
        return 0;
11776
      }
11777
      break;
11778
    }
11779
    case Mips::NOT16_MMR6: {
11780
      switch (OpNum) {
11781
      case 0:
11782
        // op: rt
11783
        return 7;
11784
      case 1:
11785
        // op: rs
11786
        return 4;
11787
      }
11788
      break;
11789
    }
11790
    case Mips::LWM16_MMR6:
11791
    case Mips::SWM16_MMR6: {
11792
      switch (OpNum) {
11793
      case 0:
11794
        // op: rt
11795
        return 8;
11796
      case 1:
11797
        // op: addr
11798
        return 4;
11799
      }
11800
      break;
11801
    }
11802
    case Mips::BeqzRxImm16:
11803
    case Mips::BnezRxImm16:
11804
    case Mips::CmpiRxImm16:
11805
    case Mips::LiRxImm16:
11806
    case Mips::LwRxPcTcp16:
11807
    case Mips::SltiRxImm16:
11808
    case Mips::SltiuRxImm16: {
11809
      switch (OpNum) {
11810
      case 0:
11811
        // op: rx
11812
        return 8;
11813
      case 1:
11814
        // op: imm8
11815
        return 0;
11816
      }
11817
      break;
11818
    }
11819
    case Mips::CmpRxRy16:
11820
    case Mips::DivRxRy16:
11821
    case Mips::DivuRxRy16:
11822
    case Mips::NegRxRy16:
11823
    case Mips::NotRxRy16:
11824
    case Mips::SltRxRy16:
11825
    case Mips::SltuRxRy16: {
11826
      switch (OpNum) {
11827
      case 0:
11828
        // op: rx
11829
        return 8;
11830
      case 1:
11831
        // op: ry
11832
        return 5;
11833
      }
11834
      break;
11835
    }
11836
    case Mips::AddiuRxRxImm16: {
11837
      switch (OpNum) {
11838
      case 0:
11839
        // op: rx
11840
        return 8;
11841
      case 2:
11842
        // op: imm8
11843
        return 0;
11844
      }
11845
      break;
11846
    }
11847
    case Mips::JumpLinkReg16:
11848
    case Mips::Mfhi16:
11849
    case Mips::Mflo16:
11850
    case Mips::SebRx16:
11851
    case Mips::SehRx16: {
11852
      switch (OpNum) {
11853
      case 0:
11854
        // op: rx
11855
        return 8;
11856
      }
11857
      break;
11858
    }
11859
    case Mips::MoveR3216: {
11860
      switch (OpNum) {
11861
      case 0:
11862
        // op: ry
11863
        return 4;
11864
      case 1:
11865
        // op: r32
11866
        return 0;
11867
      }
11868
      break;
11869
    }
11870
    case Mips::SYNC_MM:
11871
    case Mips::SYNC_MMR6: {
11872
      switch (OpNum) {
11873
      case 0:
11874
        // op: stype
11875
        return 16;
11876
      }
11877
      break;
11878
    }
11879
    case Mips::SYNC: {
11880
      switch (OpNum) {
11881
      case 0:
11882
        // op: stype
11883
        return 6;
11884
      }
11885
      break;
11886
    }
11887
    case Mips::J:
11888
    case Mips::JAL:
11889
    case Mips::JALS_MM:
11890
    case Mips::JALX:
11891
    case Mips::JALX_MM:
11892
    case Mips::JAL_MM:
11893
    case Mips::J_MM: {
11894
      switch (OpNum) {
11895
      case 0:
11896
        // op: target
11897
        return 0;
11898
      }
11899
      break;
11900
    }
11901
    case Mips::LBU_MMR6:
11902
    case Mips::LB_MMR6: {
11903
      switch (OpNum) {
11904
      case 1:
11905
        // op: addr
11906
        return 0;
11907
      case 0:
11908
        // op: rt
11909
        return 21;
11910
      }
11911
      break;
11912
    }
11913
    case Mips::LD_B:
11914
    case Mips::LD_D:
11915
    case Mips::LD_H:
11916
    case Mips::LD_W:
11917
    case Mips::ST_B:
11918
    case Mips::ST_D:
11919
    case Mips::ST_H:
11920
    case Mips::ST_W: {
11921
      switch (OpNum) {
11922
      case 1:
11923
        // op: addr
11924
        return 11;
11925
      case 0:
11926
        // op: wd
11927
        return 6;
11928
      }
11929
      break;
11930
    }
11931
    case Mips::LBE:
11932
    case Mips::LBuE:
11933
    case Mips::LHE:
11934
    case Mips::LHuE:
11935
    case Mips::LLE:
11936
    case Mips::LWE:
11937
    case Mips::LWLE:
11938
    case Mips::LWRE:
11939
    case Mips::SBE:
11940
    case Mips::SHE:
11941
    case Mips::SWE:
11942
    case Mips::SWLE:
11943
    case Mips::SWRE: {
11944
      switch (OpNum) {
11945
      case 1:
11946
        // op: addr
11947
        return 7;
11948
      case 0:
11949
        // op: rt
11950
        return 16;
11951
      }
11952
      break;
11953
    }
11954
    case Mips::CLASS_D:
11955
    case Mips::CLASS_S:
11956
    case Mips::RINT_D:
11957
    case Mips::RINT_S: {
11958
      switch (OpNum) {
11959
      case 1:
11960
        // op: fs
11961
        return 11;
11962
      case 0:
11963
        // op: fd
11964
        return 6;
11965
      }
11966
      break;
11967
    }
11968
    case Mips::C_EQ_D32:
11969
    case Mips::C_EQ_D64:
11970
    case Mips::C_EQ_S:
11971
    case Mips::C_F_D32:
11972
    case Mips::C_F_D64:
11973
    case Mips::C_F_S:
11974
    case Mips::C_LE_D32:
11975
    case Mips::C_LE_D64:
11976
    case Mips::C_LE_S:
11977
    case Mips::C_LT_D32:
11978
    case Mips::C_LT_D64:
11979
    case Mips::C_LT_S:
11980
    case Mips::C_NGE_D32:
11981
    case Mips::C_NGE_D64:
11982
    case Mips::C_NGE_S:
11983
    case Mips::C_NGLE_D32:
11984
    case Mips::C_NGLE_D64:
11985
    case Mips::C_NGLE_S:
11986
    case Mips::C_NGL_D32:
11987
    case Mips::C_NGL_D64:
11988
    case Mips::C_NGL_S:
11989
    case Mips::C_NGT_D32:
11990
    case Mips::C_NGT_D64:
11991
    case Mips::C_NGT_S:
11992
    case Mips::C_OLE_D32:
11993
    case Mips::C_OLE_D64:
11994
    case Mips::C_OLE_S:
11995
    case Mips::C_OLT_D32:
11996
    case Mips::C_OLT_D64:
11997
    case Mips::C_OLT_S:
11998
    case Mips::C_SEQ_D32:
11999
    case Mips::C_SEQ_D64:
12000
    case Mips::C_SEQ_S:
12001
    case Mips::C_SF_D32:
12002
    case Mips::C_SF_D64:
12003
    case Mips::C_SF_S:
12004
    case Mips::C_UEQ_D32:
12005
    case Mips::C_UEQ_D64:
12006
    case Mips::C_UEQ_S:
12007
    case Mips::C_ULE_D32:
12008
    case Mips::C_ULE_D64:
12009
    case Mips::C_ULE_S:
12010
    case Mips::C_ULT_D32:
12011
    case Mips::C_ULT_D64:
12012
    case Mips::C_ULT_S:
12013
    case Mips::C_UN_D32:
12014
    case Mips::C_UN_D64:
12015
    case Mips::C_UN_S: {
12016
      switch (OpNum) {
12017
      case 1:
12018
        // op: fs
12019
        return 11;
12020
      case 2:
12021
        // op: ft
12022
        return 16;
12023
      case 0:
12024
        // op: fcc
12025
        return 8;
12026
      }
12027
      break;
12028
    }
12029
    case Mips::C_EQ_D32_MM:
12030
    case Mips::C_EQ_D64_MM:
12031
    case Mips::C_EQ_S_MM:
12032
    case Mips::C_F_D32_MM:
12033
    case Mips::C_F_D64_MM:
12034
    case Mips::C_F_S_MM:
12035
    case Mips::C_LE_D32_MM:
12036
    case Mips::C_LE_D64_MM:
12037
    case Mips::C_LE_S_MM:
12038
    case Mips::C_LT_D32_MM:
12039
    case Mips::C_LT_D64_MM:
12040
    case Mips::C_LT_S_MM:
12041
    case Mips::C_NGE_D32_MM:
12042
    case Mips::C_NGE_D64_MM:
12043
    case Mips::C_NGE_S_MM:
12044
    case Mips::C_NGLE_D32_MM:
12045
    case Mips::C_NGLE_D64_MM:
12046
    case Mips::C_NGLE_S_MM:
12047
    case Mips::C_NGL_D32_MM:
12048
    case Mips::C_NGL_D64_MM:
12049
    case Mips::C_NGL_S_MM:
12050
    case Mips::C_NGT_D32_MM:
12051
    case Mips::C_NGT_D64_MM:
12052
    case Mips::C_NGT_S_MM:
12053
    case Mips::C_OLE_D32_MM:
12054
    case Mips::C_OLE_D64_MM:
12055
    case Mips::C_OLE_S_MM:
12056
    case Mips::C_OLT_D32_MM:
12057
    case Mips::C_OLT_D64_MM:
12058
    case Mips::C_OLT_S_MM:
12059
    case Mips::C_SEQ_D32_MM:
12060
    case Mips::C_SEQ_D64_MM:
12061
    case Mips::C_SEQ_S_MM:
12062
    case Mips::C_SF_D32_MM:
12063
    case Mips::C_SF_D64_MM:
12064
    case Mips::C_SF_S_MM:
12065
    case Mips::C_UEQ_D32_MM:
12066
    case Mips::C_UEQ_D64_MM:
12067
    case Mips::C_UEQ_S_MM:
12068
    case Mips::C_ULE_D32_MM:
12069
    case Mips::C_ULE_D64_MM:
12070
    case Mips::C_ULE_S_MM:
12071
    case Mips::C_ULT_D32_MM:
12072
    case Mips::C_ULT_D64_MM:
12073
    case Mips::C_ULT_S_MM:
12074
    case Mips::C_UN_D32_MM:
12075
    case Mips::C_UN_D64_MM:
12076
    case Mips::C_UN_S_MM: {
12077
      switch (OpNum) {
12078
      case 1:
12079
        // op: fs
12080
        return 16;
12081
      case 2:
12082
        // op: ft
12083
        return 21;
12084
      case 0:
12085
        // op: fcc
12086
        return 13;
12087
      }
12088
      break;
12089
    }
12090
    case Mips::CLASS_D_MMR6:
12091
    case Mips::CLASS_S_MMR6:
12092
    case Mips::RINT_D_MMR6:
12093
    case Mips::RINT_S_MMR6: {
12094
      switch (OpNum) {
12095
      case 1:
12096
        // op: fs
12097
        return 21;
12098
      case 0:
12099
        // op: fd
12100
        return 16;
12101
      }
12102
      break;
12103
    }
12104
    case Mips::FADD_S_MMR6:
12105
    case Mips::FDIV_S_MMR6:
12106
    case Mips::FMUL_S_MMR6:
12107
    case Mips::FSUB_S_MMR6: {
12108
      switch (OpNum) {
12109
      case 1:
12110
        // op: ft
12111
        return 21;
12112
      case 2:
12113
        // op: fs
12114
        return 16;
12115
      case 0:
12116
        // op: fd
12117
        return 11;
12118
      }
12119
      break;
12120
    }
12121
    case Mips::AddiuRxImmX16:
12122
    case Mips::AddiuRxPcImmX16:
12123
    case Mips::BeqzRxImmX16:
12124
    case Mips::BnezRxImmX16:
12125
    case Mips::CmpiRxImmX16:
12126
    case Mips::LiRxImmAlignX16:
12127
    case Mips::LiRxImmX16:
12128
    case Mips::LwRxPcTcpX16:
12129
    case Mips::SltiRxImmX16:
12130
    case Mips::SltiuRxImmX16: {
12131
      switch (OpNum) {
12132
      case 1:
12133
        // op: imm16
12134
        return 0;
12135
      case 0:
12136
        // op: rx
12137
        return 8;
12138
      }
12139
      break;
12140
    }
12141
    case Mips::PREFX_MM: {
12142
      switch (OpNum) {
12143
      case 1:
12144
        // op: index
12145
        return 21;
12146
      case 0:
12147
        // op: base
12148
        return 16;
12149
      case 2:
12150
        // op: hint
12151
        return 11;
12152
      }
12153
      break;
12154
    }
12155
    case Mips::BNZ_B:
12156
    case Mips::BNZ_D:
12157
    case Mips::BNZ_H:
12158
    case Mips::BNZ_V:
12159
    case Mips::BNZ_W:
12160
    case Mips::BZ_B:
12161
    case Mips::BZ_D:
12162
    case Mips::BZ_H:
12163
    case Mips::BZ_V:
12164
    case Mips::BZ_W: {
12165
      switch (OpNum) {
12166
      case 1:
12167
        // op: offset
12168
        return 0;
12169
      case 0:
12170
        // op: wt
12171
        return 16;
12172
      }
12173
      break;
12174
    }
12175
    case Mips::ADDIUS5_MM: {
12176
      switch (OpNum) {
12177
      case 1:
12178
        // op: rd
12179
        return 5;
12180
      case 2:
12181
        // op: imm
12182
        return 1;
12183
      }
12184
      break;
12185
    }
12186
    case Mips::MOVE16_MM:
12187
    case Mips::MOVE16_MMR6: {
12188
      switch (OpNum) {
12189
      case 1:
12190
        // op: rs
12191
        return 0;
12192
      case 0:
12193
        // op: rd
12194
        return 5;
12195
      }
12196
      break;
12197
    }
12198
    case Mips::CTCMSA: {
12199
      switch (OpNum) {
12200
      case 1:
12201
        // op: rs
12202
        return 11;
12203
      case 0:
12204
        // op: cd
12205
        return 6;
12206
      }
12207
      break;
12208
    }
12209
    case Mips::FILL_B:
12210
    case Mips::FILL_D:
12211
    case Mips::FILL_H:
12212
    case Mips::FILL_W: {
12213
      switch (OpNum) {
12214
      case 1:
12215
        // op: rs
12216
        return 11;
12217
      case 0:
12218
        // op: wd
12219
        return 6;
12220
      }
12221
      break;
12222
    }
12223
    case Mips::MTHI_DSP_MM:
12224
    case Mips::MTHLIP_MM:
12225
    case Mips::MTLO_DSP_MM:
12226
    case Mips::SHILOV_MM: {
12227
      switch (OpNum) {
12228
      case 1:
12229
        // op: rs
12230
        return 16;
12231
      case 0:
12232
        // op: ac
12233
        return 14;
12234
      }
12235
      break;
12236
    }
12237
    case Mips::JALRS_MM:
12238
    case Mips::JALR_MM: {
12239
      switch (OpNum) {
12240
      case 1:
12241
        // op: rs
12242
        return 16;
12243
      case 0:
12244
        // op: rd
12245
        return 21;
12246
      }
12247
      break;
12248
    }
12249
    case Mips::AUI_MMR6: {
12250
      switch (OpNum) {
12251
      case 1:
12252
        // op: rs
12253
        return 16;
12254
      case 0:
12255
        // op: rt
12256
        return 21;
12257
      case 2:
12258
        // op: imm
12259
        return 0;
12260
      }
12261
      break;
12262
    }
12263
    case Mips::ADDi_MM:
12264
    case Mips::ADDiu_MM:
12265
    case Mips::ANDi_MM:
12266
    case Mips::ORi_MM:
12267
    case Mips::XORi_MM: {
12268
      switch (OpNum) {
12269
      case 1:
12270
        // op: rs
12271
        return 16;
12272
      case 0:
12273
        // op: rt
12274
        return 21;
12275
      case 2:
12276
        // op: imm16
12277
        return 0;
12278
      }
12279
      break;
12280
    }
12281
    case Mips::CLO_MMR6: {
12282
      switch (OpNum) {
12283
      case 1:
12284
        // op: rs
12285
        return 16;
12286
      case 0:
12287
        // op: rt
12288
        return 21;
12289
      }
12290
      break;
12291
    }
12292
    case Mips::MTHI_DSP:
12293
    case Mips::MTLO_DSP: {
12294
      switch (OpNum) {
12295
      case 1:
12296
        // op: rs
12297
        return 21;
12298
      case 0:
12299
        // op: ac
12300
        return 11;
12301
      }
12302
      break;
12303
    }
12304
    case Mips::YIELD: {
12305
      switch (OpNum) {
12306
      case 1:
12307
        // op: rs
12308
        return 21;
12309
      case 0:
12310
        // op: rd
12311
        return 11;
12312
      }
12313
      break;
12314
    }
12315
    case Mips::CLZ_MMR6: {
12316
      switch (OpNum) {
12317
      case 1:
12318
        // op: rs
12319
        return 21;
12320
      case 0:
12321
        // op: rt
12322
        return 11;
12323
      }
12324
      break;
12325
    }
12326
    case Mips::AUI:
12327
    case Mips::DAUI: {
12328
      switch (OpNum) {
12329
      case 1:
12330
        // op: rs
12331
        return 21;
12332
      case 0:
12333
        // op: rt
12334
        return 16;
12335
      case 2:
12336
        // op: imm
12337
        return 0;
12338
      }
12339
      break;
12340
    }
12341
    case Mips::SEQi:
12342
    case Mips::SNEi: {
12343
      switch (OpNum) {
12344
      case 1:
12345
        // op: rs
12346
        return 21;
12347
      case 0:
12348
        // op: rt
12349
        return 16;
12350
      case 2:
12351
        // op: imm10
12352
        return 6;
12353
      }
12354
      break;
12355
    }
12356
    case Mips::ADDi:
12357
    case Mips::ADDiu:
12358
    case Mips::ANDi:
12359
    case Mips::ANDi64:
12360
    case Mips::DADDi:
12361
    case Mips::DADDiu:
12362
    case Mips::ORi:
12363
    case Mips::ORi64:
12364
    case Mips::XORi:
12365
    case Mips::XORi64: {
12366
      switch (OpNum) {
12367
      case 1:
12368
        // op: rs
12369
        return 21;
12370
      case 0:
12371
        // op: rt
12372
        return 16;
12373
      case 2:
12374
        // op: imm16
12375
        return 0;
12376
      }
12377
      break;
12378
    }
12379
    case Mips::PRECR_SRA_PH_W:
12380
    case Mips::PRECR_SRA_R_PH_W: {
12381
      switch (OpNum) {
12382
      case 1:
12383
        // op: rs
12384
        return 21;
12385
      case 0:
12386
        // op: rt
12387
        return 16;
12388
      case 2:
12389
        // op: sa
12390
        return 11;
12391
      }
12392
      break;
12393
    }
12394
    case Mips::DLSA:
12395
    case Mips::LSA: {
12396
      switch (OpNum) {
12397
      case 1:
12398
        // op: rs
12399
        return 21;
12400
      case 2:
12401
        // op: rt
12402
        return 16;
12403
      case 0:
12404
        // op: rd
12405
        return 11;
12406
      case 3:
12407
        // op: sa
12408
        return 6;
12409
      }
12410
      break;
12411
    }
12412
    case Mips::CMPGDU_EQ_QB:
12413
    case Mips::CMPGDU_LE_QB:
12414
    case Mips::CMPGDU_LT_QB:
12415
    case Mips::CMPGU_EQ_QB:
12416
    case Mips::CMPGU_LE_QB:
12417
    case Mips::CMPGU_LT_QB:
12418
    case Mips::PACKRL_PH:
12419
    case Mips::PICK_PH:
12420
    case Mips::PICK_QB:
12421
    case Mips::PRECRQU_S_QB_PH:
12422
    case Mips::PRECRQ_PH_W:
12423
    case Mips::PRECRQ_QB_PH:
12424
    case Mips::PRECRQ_RS_PH_W:
12425
    case Mips::PRECR_QB_PH: {
12426
      switch (OpNum) {
12427
      case 1:
12428
        // op: rs
12429
        return 21;
12430
      case 2:
12431
        // op: rt
12432
        return 16;
12433
      case 0:
12434
        // op: rd
12435
        return 11;
12436
      }
12437
      break;
12438
    }
12439
    case Mips::CRC32B:
12440
    case Mips::CRC32CB:
12441
    case Mips::CRC32CD:
12442
    case Mips::CRC32CH:
12443
    case Mips::CRC32CW:
12444
    case Mips::CRC32D:
12445
    case Mips::CRC32H:
12446
    case Mips::CRC32W: {
12447
      switch (OpNum) {
12448
      case 1:
12449
        // op: rs
12450
        return 21;
12451
      case 2:
12452
        // op: rt
12453
        return 16;
12454
      }
12455
      break;
12456
    }
12457
    case Mips::ADDU16_MMR6:
12458
    case Mips::SUBU16_MMR6: {
12459
      switch (OpNum) {
12460
      case 1:
12461
        // op: rs
12462
        return 7;
12463
      case 2:
12464
        // op: rt
12465
        return 4;
12466
      case 0:
12467
        // op: rd
12468
        return 1;
12469
      }
12470
      break;
12471
    }
12472
    case Mips::CTC1:
12473
    case Mips::DMTC1:
12474
    case Mips::MTC1:
12475
    case Mips::MTC1_D64: {
12476
      switch (OpNum) {
12477
      case 1:
12478
        // op: rt
12479
        return 16;
12480
      case 0:
12481
        // op: fs
12482
        return 11;
12483
      }
12484
      break;
12485
    }
12486
    case Mips::DMTC0:
12487
    case Mips::DMTC2:
12488
    case Mips::DMTGC0:
12489
    case Mips::MTC0:
12490
    case Mips::MTC2:
12491
    case Mips::MTGC0:
12492
    case Mips::MTHGC0: {
12493
      switch (OpNum) {
12494
      case 1:
12495
        // op: rt
12496
        return 16;
12497
      case 0:
12498
        // op: rd
12499
        return 11;
12500
      case 2:
12501
        // op: sel
12502
        return 0;
12503
      }
12504
      break;
12505
    }
12506
    case Mips::MFTR:
12507
    case Mips::MTTR: {
12508
      switch (OpNum) {
12509
      case 1:
12510
        // op: rt
12511
        return 16;
12512
      case 0:
12513
        // op: rd
12514
        return 11;
12515
      case 2:
12516
        // op: u
12517
        return 5;
12518
      case 4:
12519
        // op: h
12520
        return 4;
12521
      case 3:
12522
        // op: sel
12523
        return 0;
12524
      }
12525
      break;
12526
    }
12527
    case Mips::SC:
12528
    case Mips::SC64:
12529
    case Mips::SCD: {
12530
      switch (OpNum) {
12531
      case 1:
12532
        // op: rt
12533
        return 16;
12534
      case 2:
12535
        // op: addr
12536
        return 0;
12537
      }
12538
      break;
12539
    }
12540
    case Mips::SC64_R6:
12541
    case Mips::SCD_R6:
12542
    case Mips::SC_R6: {
12543
      switch (OpNum) {
12544
      case 1:
12545
        // op: rt
12546
        return 16;
12547
      case 2:
12548
        // op: addr
12549
        return 7;
12550
      }
12551
      break;
12552
    }
12553
    case Mips::CTC1_MM:
12554
    case Mips::MTC1_D64_MM:
12555
    case Mips::MTC1_MM:
12556
    case Mips::MTC1_MMR6: {
12557
      switch (OpNum) {
12558
      case 1:
12559
        // op: rt
12560
        return 21;
12561
      case 0:
12562
        // op: fs
12563
        return 16;
12564
      }
12565
      break;
12566
    }
12567
    case Mips::CTC2_MM:
12568
    case Mips::MTC2_MMR6:
12569
    case Mips::MTHC2_MMR6: {
12570
      switch (OpNum) {
12571
      case 1:
12572
        // op: rt
12573
        return 21;
12574
      case 0:
12575
        // op: impl
12576
        return 16;
12577
      }
12578
      break;
12579
    }
12580
    case Mips::BEQC_MMR6:
12581
    case Mips::BGEC_MMR6:
12582
    case Mips::BGEUC_MMR6:
12583
    case Mips::BLTC_MMR6:
12584
    case Mips::BLTUC_MMR6:
12585
    case Mips::BNEC_MMR6: {
12586
      switch (OpNum) {
12587
      case 1:
12588
        // op: rt
12589
        return 21;
12590
      case 0:
12591
        // op: rs
12592
        return 16;
12593
      case 2:
12594
        // op: offset
12595
        return 0;
12596
      }
12597
      break;
12598
    }
12599
    case Mips::MTC0_MMR6:
12600
    case Mips::MTGC0_MM:
12601
    case Mips::MTHC0_MMR6:
12602
    case Mips::MTHGC0_MM: {
12603
      switch (OpNum) {
12604
      case 1:
12605
        // op: rt
12606
        return 21;
12607
      case 0:
12608
        // op: rs
12609
        return 16;
12610
      case 2:
12611
        // op: sel
12612
        return 11;
12613
      }
12614
      break;
12615
    }
12616
    case Mips::CMPU_EQ_QB_MM:
12617
    case Mips::CMPU_LE_QB_MM:
12618
    case Mips::CMPU_LT_QB_MM:
12619
    case Mips::CMP_EQ_PH_MM:
12620
    case Mips::CMP_LE_PH_MM:
12621
    case Mips::CMP_LT_PH_MM: {
12622
      switch (OpNum) {
12623
      case 1:
12624
        // op: rt
12625
        return 21;
12626
      case 0:
12627
        // op: rs
12628
        return 16;
12629
      }
12630
      break;
12631
    }
12632
    case Mips::SCE_MM:
12633
    case Mips::SC_MM:
12634
    case Mips::SC_MMR6: {
12635
      switch (OpNum) {
12636
      case 1:
12637
        // op: rt
12638
        return 21;
12639
      case 2:
12640
        // op: addr
12641
        return 0;
12642
      }
12643
      break;
12644
    }
12645
    case Mips::AdduRxRyRz16:
12646
    case Mips::SubuRxRyRz16: {
12647
      switch (OpNum) {
12648
      case 1:
12649
        // op: rx
12650
        return 8;
12651
      case 2:
12652
        // op: ry
12653
        return 5;
12654
      case 0:
12655
        // op: rz
12656
        return 2;
12657
      }
12658
      break;
12659
    }
12660
    case Mips::AndRxRxRy16:
12661
    case Mips::OrRxRxRy16:
12662
    case Mips::SllvRxRy16:
12663
    case Mips::SravRxRy16:
12664
    case Mips::SrlvRxRy16:
12665
    case Mips::XorRxRxRy16: {
12666
      switch (OpNum) {
12667
      case 1:
12668
        // op: rx
12669
        return 8;
12670
      case 2:
12671
        // op: ry
12672
        return 5;
12673
      }
12674
      break;
12675
    }
12676
    case Mips::LDI_B:
12677
    case Mips::LDI_D:
12678
    case Mips::LDI_H:
12679
    case Mips::LDI_W: {
12680
      switch (OpNum) {
12681
      case 1:
12682
        // op: s10
12683
        return 11;
12684
      case 0:
12685
        // op: wd
12686
        return 6;
12687
      }
12688
      break;
12689
    }
12690
    case Mips::SHILO_MM: {
12691
      switch (OpNum) {
12692
      case 1:
12693
        // op: shift
12694
        return 16;
12695
      case 0:
12696
        // op: ac
12697
        return 14;
12698
      }
12699
      break;
12700
    }
12701
    case Mips::BCLRI_B:
12702
    case Mips::BCLRI_D:
12703
    case Mips::BCLRI_H:
12704
    case Mips::BCLRI_W:
12705
    case Mips::BNEGI_B:
12706
    case Mips::BNEGI_D:
12707
    case Mips::BNEGI_H:
12708
    case Mips::BNEGI_W:
12709
    case Mips::BSETI_B:
12710
    case Mips::BSETI_D:
12711
    case Mips::BSETI_H:
12712
    case Mips::BSETI_W:
12713
    case Mips::SAT_S_B:
12714
    case Mips::SAT_S_D:
12715
    case Mips::SAT_S_H:
12716
    case Mips::SAT_S_W:
12717
    case Mips::SAT_U_B:
12718
    case Mips::SAT_U_D:
12719
    case Mips::SAT_U_H:
12720
    case Mips::SAT_U_W:
12721
    case Mips::SLLI_B:
12722
    case Mips::SLLI_D:
12723
    case Mips::SLLI_H:
12724
    case Mips::SLLI_W:
12725
    case Mips::SRAI_B:
12726
    case Mips::SRAI_D:
12727
    case Mips::SRAI_H:
12728
    case Mips::SRAI_W:
12729
    case Mips::SRARI_B:
12730
    case Mips::SRARI_D:
12731
    case Mips::SRARI_H:
12732
    case Mips::SRARI_W:
12733
    case Mips::SRLI_B:
12734
    case Mips::SRLI_D:
12735
    case Mips::SRLI_H:
12736
    case Mips::SRLI_W:
12737
    case Mips::SRLRI_B:
12738
    case Mips::SRLRI_D:
12739
    case Mips::SRLRI_H:
12740
    case Mips::SRLRI_W: {
12741
      switch (OpNum) {
12742
      case 1:
12743
        // op: ws
12744
        return 11;
12745
      case 0:
12746
        // op: wd
12747
        return 6;
12748
      case 2:
12749
        // op: m
12750
        return 16;
12751
      }
12752
      break;
12753
    }
12754
    case Mips::FCLASS_D:
12755
    case Mips::FCLASS_W:
12756
    case Mips::FEXUPL_D:
12757
    case Mips::FEXUPL_W:
12758
    case Mips::FEXUPR_D:
12759
    case Mips::FEXUPR_W:
12760
    case Mips::FFINT_S_D:
12761
    case Mips::FFINT_S_W:
12762
    case Mips::FFINT_U_D:
12763
    case Mips::FFINT_U_W:
12764
    case Mips::FFQL_D:
12765
    case Mips::FFQL_W:
12766
    case Mips::FFQR_D:
12767
    case Mips::FFQR_W:
12768
    case Mips::FLOG2_D:
12769
    case Mips::FLOG2_W:
12770
    case Mips::FRCP_D:
12771
    case Mips::FRCP_W:
12772
    case Mips::FRINT_D:
12773
    case Mips::FRINT_W:
12774
    case Mips::FRSQRT_D:
12775
    case Mips::FRSQRT_W:
12776
    case Mips::FSQRT_D:
12777
    case Mips::FSQRT_W:
12778
    case Mips::FTINT_S_D:
12779
    case Mips::FTINT_S_W:
12780
    case Mips::FTINT_U_D:
12781
    case Mips::FTINT_U_W:
12782
    case Mips::FTRUNC_S_D:
12783
    case Mips::FTRUNC_S_W:
12784
    case Mips::FTRUNC_U_D:
12785
    case Mips::FTRUNC_U_W:
12786
    case Mips::MOVE_V:
12787
    case Mips::NLOC_B:
12788
    case Mips::NLOC_D:
12789
    case Mips::NLOC_H:
12790
    case Mips::NLOC_W:
12791
    case Mips::NLZC_B:
12792
    case Mips::NLZC_D:
12793
    case Mips::NLZC_H:
12794
    case Mips::NLZC_W:
12795
    case Mips::PCNT_B:
12796
    case Mips::PCNT_D:
12797
    case Mips::PCNT_H:
12798
    case Mips::PCNT_W: {
12799
      switch (OpNum) {
12800
      case 1:
12801
        // op: ws
12802
        return 11;
12803
      case 0:
12804
        // op: wd
12805
        return 6;
12806
      }
12807
      break;
12808
    }
12809
    case Mips::SCE: {
12810
      switch (OpNum) {
12811
      case 2:
12812
        // op: addr
12813
        return 7;
12814
      case 1:
12815
        // op: rt
12816
        return 16;
12817
      }
12818
      break;
12819
    }
12820
    case Mips::MAXA_D:
12821
    case Mips::MAXA_S:
12822
    case Mips::MAX_D:
12823
    case Mips::MAX_S:
12824
    case Mips::MINA_D:
12825
    case Mips::MINA_S:
12826
    case Mips::MIN_D:
12827
    case Mips::MIN_S:
12828
    case Mips::SELEQZ_D:
12829
    case Mips::SELEQZ_S:
12830
    case Mips::SELNEZ_D:
12831
    case Mips::SELNEZ_S: {
12832
      switch (OpNum) {
12833
      case 2:
12834
        // op: ft
12835
        return 16;
12836
      case 1:
12837
        // op: fs
12838
        return 11;
12839
      case 0:
12840
        // op: fd
12841
        return 6;
12842
      }
12843
      break;
12844
    }
12845
    case Mips::CMP_AF_D_MMR6:
12846
    case Mips::CMP_AF_S_MMR6:
12847
    case Mips::CMP_EQ_D_MMR6:
12848
    case Mips::CMP_EQ_S_MMR6:
12849
    case Mips::CMP_LE_D_MMR6:
12850
    case Mips::CMP_LE_S_MMR6:
12851
    case Mips::CMP_LT_D_MMR6:
12852
    case Mips::CMP_LT_S_MMR6:
12853
    case Mips::CMP_SAF_D_MMR6:
12854
    case Mips::CMP_SAF_S_MMR6:
12855
    case Mips::CMP_SEQ_D_MMR6:
12856
    case Mips::CMP_SEQ_S_MMR6:
12857
    case Mips::CMP_SLE_D_MMR6:
12858
    case Mips::CMP_SLE_S_MMR6:
12859
    case Mips::CMP_SLT_D_MMR6:
12860
    case Mips::CMP_SLT_S_MMR6:
12861
    case Mips::CMP_SUEQ_D_MMR6:
12862
    case Mips::CMP_SUEQ_S_MMR6:
12863
    case Mips::CMP_SULE_D_MMR6:
12864
    case Mips::CMP_SULE_S_MMR6:
12865
    case Mips::CMP_SULT_D_MMR6:
12866
    case Mips::CMP_SULT_S_MMR6:
12867
    case Mips::CMP_SUN_D_MMR6:
12868
    case Mips::CMP_SUN_S_MMR6:
12869
    case Mips::CMP_UEQ_D_MMR6:
12870
    case Mips::CMP_UEQ_S_MMR6:
12871
    case Mips::CMP_ULE_D_MMR6:
12872
    case Mips::CMP_ULE_S_MMR6:
12873
    case Mips::CMP_ULT_D_MMR6:
12874
    case Mips::CMP_ULT_S_MMR6:
12875
    case Mips::CMP_UN_D_MMR6:
12876
    case Mips::CMP_UN_S_MMR6:
12877
    case Mips::FADD_D32_MM:
12878
    case Mips::FADD_D64_MM:
12879
    case Mips::FADD_S_MM:
12880
    case Mips::FDIV_D32_MM:
12881
    case Mips::FDIV_D64_MM:
12882
    case Mips::FDIV_S_MM:
12883
    case Mips::FMUL_D32_MM:
12884
    case Mips::FMUL_D64_MM:
12885
    case Mips::FMUL_S_MM:
12886
    case Mips::FSUB_D32_MM:
12887
    case Mips::FSUB_D64_MM:
12888
    case Mips::FSUB_S_MM:
12889
    case Mips::MAXA_D_MMR6:
12890
    case Mips::MAXA_S_MMR6:
12891
    case Mips::MAX_D_MMR6:
12892
    case Mips::MAX_S_MMR6:
12893
    case Mips::MINA_D_MMR6:
12894
    case Mips::MINA_S_MMR6:
12895
    case Mips::MIN_D_MMR6:
12896
    case Mips::MIN_S_MMR6:
12897
    case Mips::SELEQZ_D_MMR6:
12898
    case Mips::SELEQZ_S_MMR6:
12899
    case Mips::SELNEZ_D_MMR6:
12900
    case Mips::SELNEZ_S_MMR6: {
12901
      switch (OpNum) {
12902
      case 2:
12903
        // op: ft
12904
        return 21;
12905
      case 1:
12906
        // op: fs
12907
        return 16;
12908
      case 0:
12909
        // op: fd
12910
        return 11;
12911
      }
12912
      break;
12913
    }
12914
    case Mips::ADDVI_B:
12915
    case Mips::ADDVI_D:
12916
    case Mips::ADDVI_H:
12917
    case Mips::ADDVI_W:
12918
    case Mips::CEQI_B:
12919
    case Mips::CEQI_D:
12920
    case Mips::CEQI_H:
12921
    case Mips::CEQI_W:
12922
    case Mips::CLEI_S_B:
12923
    case Mips::CLEI_S_D:
12924
    case Mips::CLEI_S_H:
12925
    case Mips::CLEI_S_W:
12926
    case Mips::CLEI_U_B:
12927
    case Mips::CLEI_U_D:
12928
    case Mips::CLEI_U_H:
12929
    case Mips::CLEI_U_W:
12930
    case Mips::CLTI_S_B:
12931
    case Mips::CLTI_S_D:
12932
    case Mips::CLTI_S_H:
12933
    case Mips::CLTI_S_W:
12934
    case Mips::CLTI_U_B:
12935
    case Mips::CLTI_U_D:
12936
    case Mips::CLTI_U_H:
12937
    case Mips::CLTI_U_W:
12938
    case Mips::MAXI_S_B:
12939
    case Mips::MAXI_S_D:
12940
    case Mips::MAXI_S_H:
12941
    case Mips::MAXI_S_W:
12942
    case Mips::MAXI_U_B:
12943
    case Mips::MAXI_U_D:
12944
    case Mips::MAXI_U_H:
12945
    case Mips::MAXI_U_W:
12946
    case Mips::MINI_S_B:
12947
    case Mips::MINI_S_D:
12948
    case Mips::MINI_S_H:
12949
    case Mips::MINI_S_W:
12950
    case Mips::MINI_U_B:
12951
    case Mips::MINI_U_D:
12952
    case Mips::MINI_U_H:
12953
    case Mips::MINI_U_W:
12954
    case Mips::SUBVI_B:
12955
    case Mips::SUBVI_D:
12956
    case Mips::SUBVI_H:
12957
    case Mips::SUBVI_W: {
12958
      switch (OpNum) {
12959
      case 2:
12960
        // op: imm
12961
        return 16;
12962
      case 1:
12963
        // op: ws
12964
        return 11;
12965
      case 0:
12966
        // op: wd
12967
        return 6;
12968
      }
12969
      break;
12970
    }
12971
    case Mips::AddiuRxRyOffMemX16: {
12972
      switch (OpNum) {
12973
      case 2:
12974
        // op: imm15
12975
        return 0;
12976
      case 1:
12977
        // op: rx
12978
        return 8;
12979
      case 0:
12980
        // op: ry
12981
        return 5;
12982
      }
12983
      break;
12984
    }
12985
    case Mips::AddiuRxRxImmX16: {
12986
      switch (OpNum) {
12987
      case 2:
12988
        // op: imm16
12989
        return 0;
12990
      case 0:
12991
        // op: rx
12992
        return 8;
12993
      }
12994
      break;
12995
    }
12996
    case Mips::LbRxRyOffMemX16:
12997
    case Mips::LbuRxRyOffMemX16:
12998
    case Mips::LhRxRyOffMemX16:
12999
    case Mips::LhuRxRyOffMemX16:
13000
    case Mips::LwRxRyOffMemX16:
13001
    case Mips::LwRxSpImmX16:
13002
    case Mips::SbRxRyOffMemX16:
13003
    case Mips::ShRxRyOffMemX16:
13004
    case Mips::SwRxRyOffMemX16:
13005
    case Mips::SwRxSpImmX16: {
13006
      switch (OpNum) {
13007
      case 2:
13008
        // op: imm16
13009
        return 0;
13010
      case 1:
13011
        // op: rx
13012
        return 8;
13013
      case 0:
13014
        // op: ry
13015
        return 5;
13016
      }
13017
      break;
13018
    }
13019
    case Mips::LBUX_MM:
13020
    case Mips::LHX_MM:
13021
    case Mips::LWX_MM: {
13022
      switch (OpNum) {
13023
      case 2:
13024
        // op: index
13025
        return 21;
13026
      case 1:
13027
        // op: base
13028
        return 16;
13029
      case 0:
13030
        // op: rd
13031
        return 11;
13032
      }
13033
      break;
13034
    }
13035
    case Mips::COPY_S_B:
13036
    case Mips::COPY_S_D:
13037
    case Mips::COPY_S_H:
13038
    case Mips::COPY_S_W:
13039
    case Mips::COPY_U_B:
13040
    case Mips::COPY_U_H:
13041
    case Mips::COPY_U_W: {
13042
      switch (OpNum) {
13043
      case 2:
13044
        // op: n
13045
        return 16;
13046
      case 1:
13047
        // op: ws
13048
        return 11;
13049
      case 0:
13050
        // op: rd
13051
        return 6;
13052
      }
13053
      break;
13054
    }
13055
    case Mips::SPLATI_B:
13056
    case Mips::SPLATI_D:
13057
    case Mips::SPLATI_H:
13058
    case Mips::SPLATI_W: {
13059
      switch (OpNum) {
13060
      case 2:
13061
        // op: n
13062
        return 16;
13063
      case 1:
13064
        // op: ws
13065
        return 11;
13066
      case 0:
13067
        // op: wd
13068
        return 6;
13069
      }
13070
      break;
13071
    }
13072
    case Mips::INSVE_B:
13073
    case Mips::INSVE_D:
13074
    case Mips::INSVE_H:
13075
    case Mips::INSVE_W: {
13076
      switch (OpNum) {
13077
      case 2:
13078
        // op: n
13079
        return 16;
13080
      case 3:
13081
        // op: ws
13082
        return 11;
13083
      case 0:
13084
        // op: wd
13085
        return 6;
13086
      }
13087
      break;
13088
    }
13089
    case Mips::MTHC1_D32:
13090
    case Mips::MTHC1_D64: {
13091
      switch (OpNum) {
13092
      case 2:
13093
        // op: rt
13094
        return 16;
13095
      case 0:
13096
        // op: fs
13097
        return 11;
13098
      }
13099
      break;
13100
    }
13101
    case Mips::SPLAT_B:
13102
    case Mips::SPLAT_D:
13103
    case Mips::SPLAT_H:
13104
    case Mips::SPLAT_W: {
13105
      switch (OpNum) {
13106
      case 2:
13107
        // op: rt
13108
        return 16;
13109
      case 1:
13110
        // op: ws
13111
        return 11;
13112
      case 0:
13113
        // op: wd
13114
        return 6;
13115
      }
13116
      break;
13117
    }
13118
    case Mips::MTHC1_D32_MM:
13119
    case Mips::MTHC1_D64_MM: {
13120
      switch (OpNum) {
13121
      case 2:
13122
        // op: rt
13123
        return 21;
13124
      case 0:
13125
        // op: fs
13126
        return 16;
13127
      }
13128
      break;
13129
    }
13130
    case Mips::DPAQX_SA_W_PH_MMR2:
13131
    case Mips::DPAQX_S_W_PH_MMR2:
13132
    case Mips::DPAQ_SA_L_W_MM:
13133
    case Mips::DPAQ_S_W_PH_MM:
13134
    case Mips::DPAU_H_QBL_MM:
13135
    case Mips::DPAU_H_QBR_MM:
13136
    case Mips::DPAX_W_PH_MMR2:
13137
    case Mips::DPA_W_PH_MMR2:
13138
    case Mips::DPSQX_SA_W_PH_MMR2:
13139
    case Mips::DPSQX_S_W_PH_MMR2:
13140
    case Mips::DPSQ_SA_L_W_MM:
13141
    case Mips::DPSQ_S_W_PH_MM:
13142
    case Mips::DPSU_H_QBL_MM:
13143
    case Mips::DPSU_H_QBR_MM:
13144
    case Mips::DPSX_W_PH_MMR2:
13145
    case Mips::DPS_W_PH_MMR2:
13146
    case Mips::MADDU_DSP_MM:
13147
    case Mips::MADD_DSP_MM:
13148
    case Mips::MAQ_SA_W_PHL_MM:
13149
    case Mips::MAQ_SA_W_PHR_MM:
13150
    case Mips::MAQ_S_W_PHL_MM:
13151
    case Mips::MAQ_S_W_PHR_MM:
13152
    case Mips::MSUBU_DSP_MM:
13153
    case Mips::MSUB_DSP_MM:
13154
    case Mips::MULSAQ_S_W_PH_MM:
13155
    case Mips::MULSA_W_PH_MMR2:
13156
    case Mips::MULTU_DSP_MM:
13157
    case Mips::MULT_DSP_MM: {
13158
      switch (OpNum) {
13159
      case 2:
13160
        // op: rt
13161
        return 21;
13162
      case 1:
13163
        // op: rs
13164
        return 16;
13165
      case 0:
13166
        // op: ac
13167
        return 14;
13168
      }
13169
      break;
13170
    }
13171
    case Mips::ADD_MM:
13172
    case Mips::ADDu_MM:
13173
    case Mips::AND_MM:
13174
    case Mips::CMPGU_EQ_QB_MM:
13175
    case Mips::CMPGU_LE_QB_MM:
13176
    case Mips::CMPGU_LT_QB_MM:
13177
    case Mips::MOVN_I_MM:
13178
    case Mips::MOVZ_I_MM:
13179
    case Mips::MUL_MM:
13180
    case Mips::NOR_MM:
13181
    case Mips::OR_MM:
13182
    case Mips::SLT_MM:
13183
    case Mips::SLTu_MM:
13184
    case Mips::SUB_MM:
13185
    case Mips::SUBu_MM:
13186
    case Mips::XOR_MM: {
13187
      switch (OpNum) {
13188
      case 2:
13189
        // op: rt
13190
        return 21;
13191
      case 1:
13192
        // op: rs
13193
        return 16;
13194
      case 0:
13195
        // op: rd
13196
        return 11;
13197
      }
13198
      break;
13199
    }
13200
    case Mips::AND16_MM:
13201
    case Mips::OR16_MM:
13202
    case Mips::XOR16_MM: {
13203
      switch (OpNum) {
13204
      case 2:
13205
        // op: rt
13206
        return 3;
13207
      case 1:
13208
        // op: rs
13209
        return 0;
13210
      }
13211
      break;
13212
    }
13213
    case Mips::AND16_MMR6:
13214
    case Mips::OR16_MMR6:
13215
    case Mips::XOR16_MMR6: {
13216
      switch (OpNum) {
13217
      case 2:
13218
        // op: rt
13219
        return 7;
13220
      case 1:
13221
        // op: rs
13222
        return 4;
13223
      }
13224
      break;
13225
    }
13226
    case Mips::SllX16:
13227
    case Mips::SraX16:
13228
    case Mips::SrlX16: {
13229
      switch (OpNum) {
13230
      case 2:
13231
        // op: sa6
13232
        return 21;
13233
      case 0:
13234
        // op: rx
13235
        return 8;
13236
      case 1:
13237
        // op: ry
13238
        return 5;
13239
      }
13240
      break;
13241
    }
13242
    case Mips::ANDI_B:
13243
    case Mips::NORI_B:
13244
    case Mips::ORI_B:
13245
    case Mips::SHF_B:
13246
    case Mips::SHF_H:
13247
    case Mips::SHF_W:
13248
    case Mips::XORI_B: {
13249
      switch (OpNum) {
13250
      case 2:
13251
        // op: u8
13252
        return 16;
13253
      case 1:
13254
        // op: ws
13255
        return 11;
13256
      case 0:
13257
        // op: wd
13258
        return 6;
13259
      }
13260
      break;
13261
    }
13262
    case Mips::BINSLI_B:
13263
    case Mips::BINSLI_D:
13264
    case Mips::BINSLI_H:
13265
    case Mips::BINSLI_W:
13266
    case Mips::BINSRI_B:
13267
    case Mips::BINSRI_D:
13268
    case Mips::BINSRI_H:
13269
    case Mips::BINSRI_W: {
13270
      switch (OpNum) {
13271
      case 2:
13272
        // op: ws
13273
        return 11;
13274
      case 0:
13275
        // op: wd
13276
        return 6;
13277
      case 3:
13278
        // op: m
13279
        return 16;
13280
      }
13281
      break;
13282
    }
13283
    case Mips::ADDS_A_B:
13284
    case Mips::ADDS_A_D:
13285
    case Mips::ADDS_A_H:
13286
    case Mips::ADDS_A_W:
13287
    case Mips::ADDS_S_B:
13288
    case Mips::ADDS_S_D:
13289
    case Mips::ADDS_S_H:
13290
    case Mips::ADDS_S_W:
13291
    case Mips::ADDS_U_B:
13292
    case Mips::ADDS_U_D:
13293
    case Mips::ADDS_U_H:
13294
    case Mips::ADDS_U_W:
13295
    case Mips::ADDV_B:
13296
    case Mips::ADDV_D:
13297
    case Mips::ADDV_H:
13298
    case Mips::ADDV_W:
13299
    case Mips::ADD_A_B:
13300
    case Mips::ADD_A_D:
13301
    case Mips::ADD_A_H:
13302
    case Mips::ADD_A_W:
13303
    case Mips::AND_V:
13304
    case Mips::ASUB_S_B:
13305
    case Mips::ASUB_S_D:
13306
    case Mips::ASUB_S_H:
13307
    case Mips::ASUB_S_W:
13308
    case Mips::ASUB_U_B:
13309
    case Mips::ASUB_U_D:
13310
    case Mips::ASUB_U_H:
13311
    case Mips::ASUB_U_W:
13312
    case Mips::AVER_S_B:
13313
    case Mips::AVER_S_D:
13314
    case Mips::AVER_S_H:
13315
    case Mips::AVER_S_W:
13316
    case Mips::AVER_U_B:
13317
    case Mips::AVER_U_D:
13318
    case Mips::AVER_U_H:
13319
    case Mips::AVER_U_W:
13320
    case Mips::AVE_S_B:
13321
    case Mips::AVE_S_D:
13322
    case Mips::AVE_S_H:
13323
    case Mips::AVE_S_W:
13324
    case Mips::AVE_U_B:
13325
    case Mips::AVE_U_D:
13326
    case Mips::AVE_U_H:
13327
    case Mips::AVE_U_W:
13328
    case Mips::BCLR_B:
13329
    case Mips::BCLR_D:
13330
    case Mips::BCLR_H:
13331
    case Mips::BCLR_W:
13332
    case Mips::BNEG_B:
13333
    case Mips::BNEG_D:
13334
    case Mips::BNEG_H:
13335
    case Mips::BNEG_W:
13336
    case Mips::BSET_B:
13337
    case Mips::BSET_D:
13338
    case Mips::BSET_H:
13339
    case Mips::BSET_W:
13340
    case Mips::CEQ_B:
13341
    case Mips::CEQ_D:
13342
    case Mips::CEQ_H:
13343
    case Mips::CEQ_W:
13344
    case Mips::CLE_S_B:
13345
    case Mips::CLE_S_D:
13346
    case Mips::CLE_S_H:
13347
    case Mips::CLE_S_W:
13348
    case Mips::CLE_U_B:
13349
    case Mips::CLE_U_D:
13350
    case Mips::CLE_U_H:
13351
    case Mips::CLE_U_W:
13352
    case Mips::CLT_S_B:
13353
    case Mips::CLT_S_D:
13354
    case Mips::CLT_S_H:
13355
    case Mips::CLT_S_W:
13356
    case Mips::CLT_U_B:
13357
    case Mips::CLT_U_D:
13358
    case Mips::CLT_U_H:
13359
    case Mips::CLT_U_W:
13360
    case Mips::DIV_S_B:
13361
    case Mips::DIV_S_D:
13362
    case Mips::DIV_S_H:
13363
    case Mips::DIV_S_W:
13364
    case Mips::DIV_U_B:
13365
    case Mips::DIV_U_D:
13366
    case Mips::DIV_U_H:
13367
    case Mips::DIV_U_W:
13368
    case Mips::DOTP_S_D:
13369
    case Mips::DOTP_S_H:
13370
    case Mips::DOTP_S_W:
13371
    case Mips::DOTP_U_D:
13372
    case Mips::DOTP_U_H:
13373
    case Mips::DOTP_U_W:
13374
    case Mips::FADD_D:
13375
    case Mips::FADD_W:
13376
    case Mips::FCAF_D:
13377
    case Mips::FCAF_W:
13378
    case Mips::FCEQ_D:
13379
    case Mips::FCEQ_W:
13380
    case Mips::FCLE_D:
13381
    case Mips::FCLE_W:
13382
    case Mips::FCLT_D:
13383
    case Mips::FCLT_W:
13384
    case Mips::FCNE_D:
13385
    case Mips::FCNE_W:
13386
    case Mips::FCOR_D:
13387
    case Mips::FCOR_W:
13388
    case Mips::FCUEQ_D:
13389
    case Mips::FCUEQ_W:
13390
    case Mips::FCULE_D:
13391
    case Mips::FCULE_W:
13392
    case Mips::FCULT_D:
13393
    case Mips::FCULT_W:
13394
    case Mips::FCUNE_D:
13395
    case Mips::FCUNE_W:
13396
    case Mips::FCUN_D:
13397
    case Mips::FCUN_W:
13398
    case Mips::FDIV_D:
13399
    case Mips::FDIV_W:
13400
    case Mips::FEXDO_H:
13401
    case Mips::FEXDO_W:
13402
    case Mips::FEXP2_D:
13403
    case Mips::FEXP2_W:
13404
    case Mips::FMAX_A_D:
13405
    case Mips::FMAX_A_W:
13406
    case Mips::FMAX_D:
13407
    case Mips::FMAX_W:
13408
    case Mips::FMIN_A_D:
13409
    case Mips::FMIN_A_W:
13410
    case Mips::FMIN_D:
13411
    case Mips::FMIN_W:
13412
    case Mips::FMUL_D:
13413
    case Mips::FMUL_W:
13414
    case Mips::FSAF_D:
13415
    case Mips::FSAF_W:
13416
    case Mips::FSEQ_D:
13417
    case Mips::FSEQ_W:
13418
    case Mips::FSLE_D:
13419
    case Mips::FSLE_W:
13420
    case Mips::FSLT_D:
13421
    case Mips::FSLT_W:
13422
    case Mips::FSNE_D:
13423
    case Mips::FSNE_W:
13424
    case Mips::FSOR_D:
13425
    case Mips::FSOR_W:
13426
    case Mips::FSUB_D:
13427
    case Mips::FSUB_W:
13428
    case Mips::FSUEQ_D:
13429
    case Mips::FSUEQ_W:
13430
    case Mips::FSULE_D:
13431
    case Mips::FSULE_W:
13432
    case Mips::FSULT_D:
13433
    case Mips::FSULT_W:
13434
    case Mips::FSUNE_D:
13435
    case Mips::FSUNE_W:
13436
    case Mips::FSUN_D:
13437
    case Mips::FSUN_W:
13438
    case Mips::FTQ_H:
13439
    case Mips::FTQ_W:
13440
    case Mips::HADD_S_D:
13441
    case Mips::HADD_S_H:
13442
    case Mips::HADD_S_W:
13443
    case Mips::HADD_U_D:
13444
    case Mips::HADD_U_H:
13445
    case Mips::HADD_U_W:
13446
    case Mips::HSUB_S_D:
13447
    case Mips::HSUB_S_H:
13448
    case Mips::HSUB_S_W:
13449
    case Mips::HSUB_U_D:
13450
    case Mips::HSUB_U_H:
13451
    case Mips::HSUB_U_W:
13452
    case Mips::ILVEV_B:
13453
    case Mips::ILVEV_D:
13454
    case Mips::ILVEV_H:
13455
    case Mips::ILVEV_W:
13456
    case Mips::ILVL_B:
13457
    case Mips::ILVL_D:
13458
    case Mips::ILVL_H:
13459
    case Mips::ILVL_W:
13460
    case Mips::ILVOD_B:
13461
    case Mips::ILVOD_D:
13462
    case Mips::ILVOD_H:
13463
    case Mips::ILVOD_W:
13464
    case Mips::ILVR_B:
13465
    case Mips::ILVR_D:
13466
    case Mips::ILVR_H:
13467
    case Mips::ILVR_W:
13468
    case Mips::MAX_A_B:
13469
    case Mips::MAX_A_D:
13470
    case Mips::MAX_A_H:
13471
    case Mips::MAX_A_W:
13472
    case Mips::MAX_S_B:
13473
    case Mips::MAX_S_D:
13474
    case Mips::MAX_S_H:
13475
    case Mips::MAX_S_W:
13476
    case Mips::MAX_U_B:
13477
    case Mips::MAX_U_D:
13478
    case Mips::MAX_U_H:
13479
    case Mips::MAX_U_W:
13480
    case Mips::MIN_A_B:
13481
    case Mips::MIN_A_D:
13482
    case Mips::MIN_A_H:
13483
    case Mips::MIN_A_W:
13484
    case Mips::MIN_S_B:
13485
    case Mips::MIN_S_D:
13486
    case Mips::MIN_S_H:
13487
    case Mips::MIN_S_W:
13488
    case Mips::MIN_U_B:
13489
    case Mips::MIN_U_D:
13490
    case Mips::MIN_U_H:
13491
    case Mips::MIN_U_W:
13492
    case Mips::MOD_S_B:
13493
    case Mips::MOD_S_D:
13494
    case Mips::MOD_S_H:
13495
    case Mips::MOD_S_W:
13496
    case Mips::MOD_U_B:
13497
    case Mips::MOD_U_D:
13498
    case Mips::MOD_U_H:
13499
    case Mips::MOD_U_W:
13500
    case Mips::MULR_Q_H:
13501
    case Mips::MULR_Q_W:
13502
    case Mips::MULV_B:
13503
    case Mips::MULV_D:
13504
    case Mips::MULV_H:
13505
    case Mips::MULV_W:
13506
    case Mips::MUL_Q_H:
13507
    case Mips::MUL_Q_W:
13508
    case Mips::NOR_V:
13509
    case Mips::OR_V:
13510
    case Mips::PCKEV_B:
13511
    case Mips::PCKEV_D:
13512
    case Mips::PCKEV_H:
13513
    case Mips::PCKEV_W:
13514
    case Mips::PCKOD_B:
13515
    case Mips::PCKOD_D:
13516
    case Mips::PCKOD_H:
13517
    case Mips::PCKOD_W:
13518
    case Mips::SLL_B:
13519
    case Mips::SLL_D:
13520
    case Mips::SLL_H:
13521
    case Mips::SLL_W:
13522
    case Mips::SRAR_B:
13523
    case Mips::SRAR_D:
13524
    case Mips::SRAR_H:
13525
    case Mips::SRAR_W:
13526
    case Mips::SRA_B:
13527
    case Mips::SRA_D:
13528
    case Mips::SRA_H:
13529
    case Mips::SRA_W:
13530
    case Mips::SRLR_B:
13531
    case Mips::SRLR_D:
13532
    case Mips::SRLR_H:
13533
    case Mips::SRLR_W:
13534
    case Mips::SRL_B:
13535
    case Mips::SRL_D:
13536
    case Mips::SRL_H:
13537
    case Mips::SRL_W:
13538
    case Mips::SUBSUS_U_B:
13539
    case Mips::SUBSUS_U_D:
13540
    case Mips::SUBSUS_U_H:
13541
    case Mips::SUBSUS_U_W:
13542
    case Mips::SUBSUU_S_B:
13543
    case Mips::SUBSUU_S_D:
13544
    case Mips::SUBSUU_S_H:
13545
    case Mips::SUBSUU_S_W:
13546
    case Mips::SUBS_S_B:
13547
    case Mips::SUBS_S_D:
13548
    case Mips::SUBS_S_H:
13549
    case Mips::SUBS_S_W:
13550
    case Mips::SUBS_U_B:
13551
    case Mips::SUBS_U_D:
13552
    case Mips::SUBS_U_H:
13553
    case Mips::SUBS_U_W:
13554
    case Mips::SUBV_B:
13555
    case Mips::SUBV_D:
13556
    case Mips::SUBV_H:
13557
    case Mips::SUBV_W:
13558
    case Mips::XOR_V: {
13559
      switch (OpNum) {
13560
      case 2:
13561
        // op: wt
13562
        return 16;
13563
      case 1:
13564
        // op: ws
13565
        return 11;
13566
      case 0:
13567
        // op: wd
13568
        return 6;
13569
      }
13570
      break;
13571
    }
13572
    case Mips::MADDF_D:
13573
    case Mips::MADDF_S:
13574
    case Mips::MSUBF_D:
13575
    case Mips::MSUBF_S:
13576
    case Mips::SEL_D:
13577
    case Mips::SEL_S: {
13578
      switch (OpNum) {
13579
      case 3:
13580
        // op: ft
13581
        return 16;
13582
      case 2:
13583
        // op: fs
13584
        return 11;
13585
      case 0:
13586
        // op: fd
13587
        return 6;
13588
      }
13589
      break;
13590
    }
13591
    case Mips::MADD_D32_MM:
13592
    case Mips::MADD_S_MM:
13593
    case Mips::MSUB_D32_MM:
13594
    case Mips::MSUB_S_MM:
13595
    case Mips::NMADD_D32_MM:
13596
    case Mips::NMADD_S_MM:
13597
    case Mips::NMSUB_D32_MM:
13598
    case Mips::NMSUB_S_MM: {
13599
      switch (OpNum) {
13600
      case 3:
13601
        // op: ft
13602
        return 21;
13603
      case 2:
13604
        // op: fs
13605
        return 16;
13606
      case 0:
13607
        // op: fd
13608
        return 11;
13609
      case 1:
13610
        // op: fr
13611
        return 6;
13612
      }
13613
      break;
13614
    }
13615
    case Mips::MADDF_D_MMR6:
13616
    case Mips::MADDF_S_MMR6:
13617
    case Mips::MSUBF_D_MMR6:
13618
    case Mips::MSUBF_S_MMR6:
13619
    case Mips::SEL_D_MMR6:
13620
    case Mips::SEL_S_MMR6: {
13621
      switch (OpNum) {
13622
      case 3:
13623
        // op: ft
13624
        return 21;
13625
      case 2:
13626
        // op: fs
13627
        return 16;
13628
      case 0:
13629
        // op: fd
13630
        return 11;
13631
      }
13632
      break;
13633
    }
13634
    case Mips::INSERT_B:
13635
    case Mips::INSERT_D:
13636
    case Mips::INSERT_H:
13637
    case Mips::INSERT_W: {
13638
      switch (OpNum) {
13639
      case 3:
13640
        // op: n
13641
        return 16;
13642
      case 2:
13643
        // op: rs
13644
        return 11;
13645
      case 0:
13646
        // op: wd
13647
        return 6;
13648
      }
13649
      break;
13650
    }
13651
    case Mips::SLDI_B:
13652
    case Mips::SLDI_D:
13653
    case Mips::SLDI_H:
13654
    case Mips::SLDI_W: {
13655
      switch (OpNum) {
13656
      case 3:
13657
        // op: n
13658
        return 16;
13659
      case 2:
13660
        // op: ws
13661
        return 11;
13662
      case 0:
13663
        // op: wd
13664
        return 6;
13665
      }
13666
      break;
13667
    }
13668
    case Mips::SLD_B:
13669
    case Mips::SLD_D:
13670
    case Mips::SLD_H:
13671
    case Mips::SLD_W: {
13672
      switch (OpNum) {
13673
      case 3:
13674
        // op: rt
13675
        return 16;
13676
      case 2:
13677
        // op: ws
13678
        return 11;
13679
      case 0:
13680
        // op: wd
13681
        return 6;
13682
      }
13683
      break;
13684
    }
13685
    case Mips::MOVEP_MMR6: {
13686
      switch (OpNum) {
13687
      case 3:
13688
        // op: rt
13689
        return 4;
13690
      case 2:
13691
        // op: rs
13692
        return 0;
13693
      }
13694
      break;
13695
    }
13696
    case Mips::MOVEP_MM: {
13697
      switch (OpNum) {
13698
      case 3:
13699
        // op: rt
13700
        return 4;
13701
      case 2:
13702
        // op: rs
13703
        return 1;
13704
      }
13705
      break;
13706
    }
13707
    case Mips::BMNZI_B:
13708
    case Mips::BMZI_B:
13709
    case Mips::BSELI_B: {
13710
      switch (OpNum) {
13711
      case 3:
13712
        // op: u8
13713
        return 16;
13714
      case 2:
13715
        // op: ws
13716
        return 11;
13717
      case 0:
13718
        // op: wd
13719
        return 6;
13720
      }
13721
      break;
13722
    }
13723
    case Mips::BINSL_B:
13724
    case Mips::BINSL_D:
13725
    case Mips::BINSL_H:
13726
    case Mips::BINSL_W:
13727
    case Mips::BINSR_B:
13728
    case Mips::BINSR_D:
13729
    case Mips::BINSR_H:
13730
    case Mips::BINSR_W:
13731
    case Mips::BMNZ_V:
13732
    case Mips::BMZ_V:
13733
    case Mips::BSEL_V:
13734
    case Mips::DPADD_S_D:
13735
    case Mips::DPADD_S_H:
13736
    case Mips::DPADD_S_W:
13737
    case Mips::DPADD_U_D:
13738
    case Mips::DPADD_U_H:
13739
    case Mips::DPADD_U_W:
13740
    case Mips::DPSUB_S_D:
13741
    case Mips::DPSUB_S_H:
13742
    case Mips::DPSUB_S_W:
13743
    case Mips::DPSUB_U_D:
13744
    case Mips::DPSUB_U_H:
13745
    case Mips::DPSUB_U_W:
13746
    case Mips::FMADD_D:
13747
    case Mips::FMADD_W:
13748
    case Mips::FMSUB_D:
13749
    case Mips::FMSUB_W:
13750
    case Mips::MADDR_Q_H:
13751
    case Mips::MADDR_Q_W:
13752
    case Mips::MADDV_B:
13753
    case Mips::MADDV_D:
13754
    case Mips::MADDV_H:
13755
    case Mips::MADDV_W:
13756
    case Mips::MADD_Q_H:
13757
    case Mips::MADD_Q_W:
13758
    case Mips::MSUBR_Q_H:
13759
    case Mips::MSUBR_Q_W:
13760
    case Mips::MSUBV_B:
13761
    case Mips::MSUBV_D:
13762
    case Mips::MSUBV_H:
13763
    case Mips::MSUBV_W:
13764
    case Mips::MSUB_Q_H:
13765
    case Mips::MSUB_Q_W:
13766
    case Mips::VSHF_B:
13767
    case Mips::VSHF_D:
13768
    case Mips::VSHF_H:
13769
    case Mips::VSHF_W: {
13770
      switch (OpNum) {
13771
      case 3:
13772
        // op: wt
13773
        return 16;
13774
      case 2:
13775
        // op: ws
13776
        return 11;
13777
      case 0:
13778
        // op: wd
13779
        return 6;
13780
      }
13781
      break;
13782
    }
13783
  }
13784
  std::string msg;
13785
  raw_string_ostream Msg(msg);
13786
  Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]";
13787
  report_fatal_error(Msg.str().c_str());
13788
}
13789
13790
#endif // GET_OPERAND_BIT_OFFSET
13791