/src/build/lib/Target/Mips/MipsGenMCPseudoLowering.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | bool MipsAsmPrinter:: |
10 | | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | 206 | const MachineInstr *MI) { |
12 | 206 | switch (MI->getOpcode()) { |
13 | 206 | default: return false; |
14 | 0 | case Mips::AND_V_D_PSEUDO: { |
15 | 0 | MCInst TmpInst; |
16 | 0 | MCOperand MCOp; |
17 | 0 | TmpInst.setOpcode(Mips::AND_V); |
18 | | // Operand: wd |
19 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
20 | 0 | TmpInst.addOperand(MCOp); |
21 | | // Operand: ws |
22 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
23 | 0 | TmpInst.addOperand(MCOp); |
24 | | // Operand: wt |
25 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
26 | 0 | TmpInst.addOperand(MCOp); |
27 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
28 | 0 | break; |
29 | 0 | } |
30 | 0 | case Mips::AND_V_H_PSEUDO: { |
31 | 0 | MCInst TmpInst; |
32 | 0 | MCOperand MCOp; |
33 | 0 | TmpInst.setOpcode(Mips::AND_V); |
34 | | // Operand: wd |
35 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
36 | 0 | TmpInst.addOperand(MCOp); |
37 | | // Operand: ws |
38 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
39 | 0 | TmpInst.addOperand(MCOp); |
40 | | // Operand: wt |
41 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
42 | 0 | TmpInst.addOperand(MCOp); |
43 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
44 | 0 | break; |
45 | 0 | } |
46 | 0 | case Mips::AND_V_W_PSEUDO: { |
47 | 0 | MCInst TmpInst; |
48 | 0 | MCOperand MCOp; |
49 | 0 | TmpInst.setOpcode(Mips::AND_V); |
50 | | // Operand: wd |
51 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
52 | 0 | TmpInst.addOperand(MCOp); |
53 | | // Operand: ws |
54 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
55 | 0 | TmpInst.addOperand(MCOp); |
56 | | // Operand: wt |
57 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
58 | 0 | TmpInst.addOperand(MCOp); |
59 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
60 | 0 | break; |
61 | 0 | } |
62 | 0 | case Mips::B: { |
63 | 0 | MCInst TmpInst; |
64 | 0 | MCOperand MCOp; |
65 | 0 | TmpInst.setOpcode(Mips::BEQ); |
66 | | // Operand: rs |
67 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
68 | | // Operand: rt |
69 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
70 | | // Operand: offset |
71 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
72 | 0 | TmpInst.addOperand(MCOp); |
73 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
74 | 0 | break; |
75 | 0 | } |
76 | 0 | case Mips::BAL_BR: { |
77 | 0 | MCInst TmpInst; |
78 | 0 | MCOperand MCOp; |
79 | 0 | TmpInst.setOpcode(Mips::BGEZAL); |
80 | | // Operand: rs |
81 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
82 | | // Operand: offset |
83 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
84 | 0 | TmpInst.addOperand(MCOp); |
85 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
86 | 0 | break; |
87 | 0 | } |
88 | 0 | case Mips::BAL_BR_MM: { |
89 | 0 | MCInst TmpInst; |
90 | 0 | MCOperand MCOp; |
91 | 0 | TmpInst.setOpcode(Mips::BGEZAL_MM); |
92 | | // Operand: rs |
93 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
94 | | // Operand: offset |
95 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
96 | 0 | TmpInst.addOperand(MCOp); |
97 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
98 | 0 | break; |
99 | 0 | } |
100 | 0 | case Mips::BSEL_D_PSEUDO: { |
101 | 0 | MCInst TmpInst; |
102 | 0 | MCOperand MCOp; |
103 | 0 | TmpInst.setOpcode(Mips::BSEL_V); |
104 | | // Operand: wd |
105 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
106 | 0 | TmpInst.addOperand(MCOp); |
107 | | // Operand: wd_in |
108 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
109 | 0 | TmpInst.addOperand(MCOp); |
110 | | // Operand: ws |
111 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
112 | 0 | TmpInst.addOperand(MCOp); |
113 | | // Operand: wt |
114 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
115 | 0 | TmpInst.addOperand(MCOp); |
116 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
117 | 0 | break; |
118 | 0 | } |
119 | 0 | case Mips::BSEL_FD_PSEUDO: { |
120 | 0 | MCInst TmpInst; |
121 | 0 | MCOperand MCOp; |
122 | 0 | TmpInst.setOpcode(Mips::BSEL_V); |
123 | | // Operand: wd |
124 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
125 | 0 | TmpInst.addOperand(MCOp); |
126 | | // Operand: wd_in |
127 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
128 | 0 | TmpInst.addOperand(MCOp); |
129 | | // Operand: ws |
130 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
131 | 0 | TmpInst.addOperand(MCOp); |
132 | | // Operand: wt |
133 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
134 | 0 | TmpInst.addOperand(MCOp); |
135 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
136 | 0 | break; |
137 | 0 | } |
138 | 0 | case Mips::BSEL_FW_PSEUDO: { |
139 | 0 | MCInst TmpInst; |
140 | 0 | MCOperand MCOp; |
141 | 0 | TmpInst.setOpcode(Mips::BSEL_V); |
142 | | // Operand: wd |
143 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
144 | 0 | TmpInst.addOperand(MCOp); |
145 | | // Operand: wd_in |
146 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
147 | 0 | TmpInst.addOperand(MCOp); |
148 | | // Operand: ws |
149 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
150 | 0 | TmpInst.addOperand(MCOp); |
151 | | // Operand: wt |
152 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
153 | 0 | TmpInst.addOperand(MCOp); |
154 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
155 | 0 | break; |
156 | 0 | } |
157 | 0 | case Mips::BSEL_H_PSEUDO: { |
158 | 0 | MCInst TmpInst; |
159 | 0 | MCOperand MCOp; |
160 | 0 | TmpInst.setOpcode(Mips::BSEL_V); |
161 | | // Operand: wd |
162 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
163 | 0 | TmpInst.addOperand(MCOp); |
164 | | // Operand: wd_in |
165 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
166 | 0 | TmpInst.addOperand(MCOp); |
167 | | // Operand: ws |
168 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
169 | 0 | TmpInst.addOperand(MCOp); |
170 | | // Operand: wt |
171 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
172 | 0 | TmpInst.addOperand(MCOp); |
173 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
174 | 0 | break; |
175 | 0 | } |
176 | 0 | case Mips::BSEL_W_PSEUDO: { |
177 | 0 | MCInst TmpInst; |
178 | 0 | MCOperand MCOp; |
179 | 0 | TmpInst.setOpcode(Mips::BSEL_V); |
180 | | // Operand: wd |
181 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
182 | 0 | TmpInst.addOperand(MCOp); |
183 | | // Operand: wd_in |
184 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
185 | 0 | TmpInst.addOperand(MCOp); |
186 | | // Operand: ws |
187 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
188 | 0 | TmpInst.addOperand(MCOp); |
189 | | // Operand: wt |
190 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
191 | 0 | TmpInst.addOperand(MCOp); |
192 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
193 | 0 | break; |
194 | 0 | } |
195 | 0 | case Mips::B_MM: { |
196 | 0 | MCInst TmpInst; |
197 | 0 | MCOperand MCOp; |
198 | 0 | TmpInst.setOpcode(Mips::BEQ_MM); |
199 | | // Operand: rs |
200 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
201 | | // Operand: rt |
202 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
203 | | // Operand: offset |
204 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
205 | 0 | TmpInst.addOperand(MCOp); |
206 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
207 | 0 | break; |
208 | 0 | } |
209 | 0 | case Mips::FABS_D: { |
210 | 0 | MCInst TmpInst; |
211 | 0 | MCOperand MCOp; |
212 | 0 | TmpInst.setOpcode(Mips::FMAX_A_D); |
213 | | // Operand: wd |
214 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
215 | 0 | TmpInst.addOperand(MCOp); |
216 | | // Operand: ws |
217 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
218 | 0 | TmpInst.addOperand(MCOp); |
219 | | // Operand: wt |
220 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
221 | 0 | TmpInst.addOperand(MCOp); |
222 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
223 | 0 | break; |
224 | 0 | } |
225 | 0 | case Mips::FABS_W: { |
226 | 0 | MCInst TmpInst; |
227 | 0 | MCOperand MCOp; |
228 | 0 | TmpInst.setOpcode(Mips::FMAX_A_W); |
229 | | // Operand: wd |
230 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
231 | 0 | TmpInst.addOperand(MCOp); |
232 | | // Operand: ws |
233 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
234 | 0 | TmpInst.addOperand(MCOp); |
235 | | // Operand: wt |
236 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
237 | 0 | TmpInst.addOperand(MCOp); |
238 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
239 | 0 | break; |
240 | 0 | } |
241 | 0 | case Mips::JALR64Pseudo: { |
242 | 0 | MCInst TmpInst; |
243 | 0 | MCOperand MCOp; |
244 | 0 | TmpInst.setOpcode(Mips::JALR); |
245 | | // Operand: rd |
246 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::RA)); |
247 | | // Operand: rs |
248 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
249 | 0 | TmpInst.addOperand(MCOp); |
250 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
251 | 0 | break; |
252 | 0 | } |
253 | 0 | case Mips::JALRHB64Pseudo: { |
254 | 0 | MCInst TmpInst; |
255 | 0 | MCOperand MCOp; |
256 | 0 | TmpInst.setOpcode(Mips::JALR_HB64); |
257 | | // Operand: rd |
258 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::RA_64)); |
259 | | // Operand: rs |
260 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
261 | 0 | TmpInst.addOperand(MCOp); |
262 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
263 | 0 | break; |
264 | 0 | } |
265 | 0 | case Mips::JALRHBPseudo: { |
266 | 0 | MCInst TmpInst; |
267 | 0 | MCOperand MCOp; |
268 | 0 | TmpInst.setOpcode(Mips::JALR_HB); |
269 | | // Operand: rd |
270 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::RA)); |
271 | | // Operand: rs |
272 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
273 | 0 | TmpInst.addOperand(MCOp); |
274 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
275 | 0 | break; |
276 | 0 | } |
277 | 0 | case Mips::JALRPseudo: { |
278 | 0 | MCInst TmpInst; |
279 | 0 | MCOperand MCOp; |
280 | 0 | TmpInst.setOpcode(Mips::JALR); |
281 | | // Operand: rd |
282 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::RA)); |
283 | | // Operand: rs |
284 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
285 | 0 | TmpInst.addOperand(MCOp); |
286 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
287 | 0 | break; |
288 | 0 | } |
289 | 0 | case Mips::JAL_MMR6: { |
290 | 0 | MCInst TmpInst; |
291 | 0 | MCOperand MCOp; |
292 | 0 | TmpInst.setOpcode(Mips::BALC_MMR6); |
293 | | // Operand: offset |
294 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
295 | 0 | TmpInst.addOperand(MCOp); |
296 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
297 | 0 | break; |
298 | 0 | } |
299 | 0 | case Mips::NOP: { |
300 | 0 | MCInst TmpInst; |
301 | 0 | MCOperand MCOp; |
302 | 0 | TmpInst.setOpcode(Mips::SLL); |
303 | | // Operand: rd |
304 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
305 | | // Operand: rt |
306 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
307 | | // Operand: shamt |
308 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
309 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
310 | 0 | break; |
311 | 0 | } |
312 | 0 | case Mips::NOR_V_D_PSEUDO: { |
313 | 0 | MCInst TmpInst; |
314 | 0 | MCOperand MCOp; |
315 | 0 | TmpInst.setOpcode(Mips::NOR_V); |
316 | | // Operand: wd |
317 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
318 | 0 | TmpInst.addOperand(MCOp); |
319 | | // Operand: ws |
320 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
321 | 0 | TmpInst.addOperand(MCOp); |
322 | | // Operand: wt |
323 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
324 | 0 | TmpInst.addOperand(MCOp); |
325 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
326 | 0 | break; |
327 | 0 | } |
328 | 0 | case Mips::NOR_V_H_PSEUDO: { |
329 | 0 | MCInst TmpInst; |
330 | 0 | MCOperand MCOp; |
331 | 0 | TmpInst.setOpcode(Mips::NOR_V); |
332 | | // Operand: wd |
333 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
334 | 0 | TmpInst.addOperand(MCOp); |
335 | | // Operand: ws |
336 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
337 | 0 | TmpInst.addOperand(MCOp); |
338 | | // Operand: wt |
339 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
340 | 0 | TmpInst.addOperand(MCOp); |
341 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
342 | 0 | break; |
343 | 0 | } |
344 | 0 | case Mips::NOR_V_W_PSEUDO: { |
345 | 0 | MCInst TmpInst; |
346 | 0 | MCOperand MCOp; |
347 | 0 | TmpInst.setOpcode(Mips::NOR_V); |
348 | | // Operand: wd |
349 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
350 | 0 | TmpInst.addOperand(MCOp); |
351 | | // Operand: ws |
352 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
353 | 0 | TmpInst.addOperand(MCOp); |
354 | | // Operand: wt |
355 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
356 | 0 | TmpInst.addOperand(MCOp); |
357 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
358 | 0 | break; |
359 | 0 | } |
360 | 0 | case Mips::OR_V_D_PSEUDO: { |
361 | 0 | MCInst TmpInst; |
362 | 0 | MCOperand MCOp; |
363 | 0 | TmpInst.setOpcode(Mips::OR_V); |
364 | | // Operand: wd |
365 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
366 | 0 | TmpInst.addOperand(MCOp); |
367 | | // Operand: ws |
368 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
369 | 0 | TmpInst.addOperand(MCOp); |
370 | | // Operand: wt |
371 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
372 | 0 | TmpInst.addOperand(MCOp); |
373 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
374 | 0 | break; |
375 | 0 | } |
376 | 0 | case Mips::OR_V_H_PSEUDO: { |
377 | 0 | MCInst TmpInst; |
378 | 0 | MCOperand MCOp; |
379 | 0 | TmpInst.setOpcode(Mips::OR_V); |
380 | | // Operand: wd |
381 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
382 | 0 | TmpInst.addOperand(MCOp); |
383 | | // Operand: ws |
384 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
385 | 0 | TmpInst.addOperand(MCOp); |
386 | | // Operand: wt |
387 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
388 | 0 | TmpInst.addOperand(MCOp); |
389 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
390 | 0 | break; |
391 | 0 | } |
392 | 0 | case Mips::OR_V_W_PSEUDO: { |
393 | 0 | MCInst TmpInst; |
394 | 0 | MCOperand MCOp; |
395 | 0 | TmpInst.setOpcode(Mips::OR_V); |
396 | | // Operand: wd |
397 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
398 | 0 | TmpInst.addOperand(MCOp); |
399 | | // Operand: ws |
400 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
401 | 0 | TmpInst.addOperand(MCOp); |
402 | | // Operand: wt |
403 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
404 | 0 | TmpInst.addOperand(MCOp); |
405 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
406 | 0 | break; |
407 | 0 | } |
408 | 0 | case Mips::PseudoCMPU_EQ_QB: { |
409 | 0 | MCInst TmpInst; |
410 | 0 | MCOperand MCOp; |
411 | 0 | TmpInst.setOpcode(Mips::CMPU_EQ_QB); |
412 | | // Operand: rs |
413 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
414 | 0 | TmpInst.addOperand(MCOp); |
415 | | // Operand: rt |
416 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
417 | 0 | TmpInst.addOperand(MCOp); |
418 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
419 | 0 | break; |
420 | 0 | } |
421 | 0 | case Mips::PseudoCMPU_LE_QB: { |
422 | 0 | MCInst TmpInst; |
423 | 0 | MCOperand MCOp; |
424 | 0 | TmpInst.setOpcode(Mips::CMPU_LE_QB); |
425 | | // Operand: rs |
426 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
427 | 0 | TmpInst.addOperand(MCOp); |
428 | | // Operand: rt |
429 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
430 | 0 | TmpInst.addOperand(MCOp); |
431 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
432 | 0 | break; |
433 | 0 | } |
434 | 0 | case Mips::PseudoCMPU_LT_QB: { |
435 | 0 | MCInst TmpInst; |
436 | 0 | MCOperand MCOp; |
437 | 0 | TmpInst.setOpcode(Mips::CMPU_LT_QB); |
438 | | // Operand: rs |
439 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
440 | 0 | TmpInst.addOperand(MCOp); |
441 | | // Operand: rt |
442 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
443 | 0 | TmpInst.addOperand(MCOp); |
444 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
445 | 0 | break; |
446 | 0 | } |
447 | 0 | case Mips::PseudoCMP_EQ_PH: { |
448 | 0 | MCInst TmpInst; |
449 | 0 | MCOperand MCOp; |
450 | 0 | TmpInst.setOpcode(Mips::CMP_EQ_PH); |
451 | | // Operand: rs |
452 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
453 | 0 | TmpInst.addOperand(MCOp); |
454 | | // Operand: rt |
455 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
456 | 0 | TmpInst.addOperand(MCOp); |
457 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
458 | 0 | break; |
459 | 0 | } |
460 | 0 | case Mips::PseudoCMP_LE_PH: { |
461 | 0 | MCInst TmpInst; |
462 | 0 | MCOperand MCOp; |
463 | 0 | TmpInst.setOpcode(Mips::CMP_LE_PH); |
464 | | // Operand: rs |
465 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
466 | 0 | TmpInst.addOperand(MCOp); |
467 | | // Operand: rt |
468 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
469 | 0 | TmpInst.addOperand(MCOp); |
470 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
471 | 0 | break; |
472 | 0 | } |
473 | 0 | case Mips::PseudoCMP_LT_PH: { |
474 | 0 | MCInst TmpInst; |
475 | 0 | MCOperand MCOp; |
476 | 0 | TmpInst.setOpcode(Mips::CMP_LT_PH); |
477 | | // Operand: rs |
478 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
479 | 0 | TmpInst.addOperand(MCOp); |
480 | | // Operand: rt |
481 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
482 | 0 | TmpInst.addOperand(MCOp); |
483 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
484 | 0 | break; |
485 | 0 | } |
486 | 0 | case Mips::PseudoDMULT: { |
487 | 0 | MCInst TmpInst; |
488 | 0 | MCOperand MCOp; |
489 | 0 | TmpInst.setOpcode(Mips::DMULT); |
490 | | // Operand: rs |
491 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
492 | 0 | TmpInst.addOperand(MCOp); |
493 | | // Operand: rt |
494 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
495 | 0 | TmpInst.addOperand(MCOp); |
496 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
497 | 0 | break; |
498 | 0 | } |
499 | 0 | case Mips::PseudoDMULTu: { |
500 | 0 | MCInst TmpInst; |
501 | 0 | MCOperand MCOp; |
502 | 0 | TmpInst.setOpcode(Mips::DMULTu); |
503 | | // Operand: rs |
504 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
505 | 0 | TmpInst.addOperand(MCOp); |
506 | | // Operand: rt |
507 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
508 | 0 | TmpInst.addOperand(MCOp); |
509 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
510 | 0 | break; |
511 | 0 | } |
512 | 0 | case Mips::PseudoDSDIV: { |
513 | 0 | MCInst TmpInst; |
514 | 0 | MCOperand MCOp; |
515 | 0 | TmpInst.setOpcode(Mips::DSDIV); |
516 | | // Operand: rs |
517 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
518 | 0 | TmpInst.addOperand(MCOp); |
519 | | // Operand: rt |
520 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
521 | 0 | TmpInst.addOperand(MCOp); |
522 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
523 | 0 | break; |
524 | 0 | } |
525 | 0 | case Mips::PseudoDUDIV: { |
526 | 0 | MCInst TmpInst; |
527 | 0 | MCOperand MCOp; |
528 | 0 | TmpInst.setOpcode(Mips::DUDIV); |
529 | | // Operand: rs |
530 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
531 | 0 | TmpInst.addOperand(MCOp); |
532 | | // Operand: rt |
533 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
534 | 0 | TmpInst.addOperand(MCOp); |
535 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
536 | 0 | break; |
537 | 0 | } |
538 | 0 | case Mips::PseudoIndirectBranch: { |
539 | 0 | MCInst TmpInst; |
540 | 0 | MCOperand MCOp; |
541 | 0 | TmpInst.setOpcode(Mips::JR); |
542 | | // Operand: rs |
543 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
544 | 0 | TmpInst.addOperand(MCOp); |
545 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
546 | 0 | break; |
547 | 0 | } |
548 | 0 | case Mips::PseudoIndirectBranch64: { |
549 | 0 | MCInst TmpInst; |
550 | 0 | MCOperand MCOp; |
551 | 0 | TmpInst.setOpcode(Mips::JR64); |
552 | | // Operand: rs |
553 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
554 | 0 | TmpInst.addOperand(MCOp); |
555 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
556 | 0 | break; |
557 | 0 | } |
558 | 0 | case Mips::PseudoIndirectBranch64R6: { |
559 | 0 | MCInst TmpInst; |
560 | 0 | MCOperand MCOp; |
561 | 0 | TmpInst.setOpcode(Mips::JALR64); |
562 | | // Operand: rd |
563 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64)); |
564 | | // Operand: rs |
565 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
566 | 0 | TmpInst.addOperand(MCOp); |
567 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
568 | 0 | break; |
569 | 0 | } |
570 | 0 | case Mips::PseudoIndirectBranchR6: { |
571 | 0 | MCInst TmpInst; |
572 | 0 | MCOperand MCOp; |
573 | 0 | TmpInst.setOpcode(Mips::JALR); |
574 | | // Operand: rd |
575 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
576 | | // Operand: rs |
577 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
578 | 0 | TmpInst.addOperand(MCOp); |
579 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
580 | 0 | break; |
581 | 0 | } |
582 | 0 | case Mips::PseudoIndirectBranch_MM: { |
583 | 0 | MCInst TmpInst; |
584 | 0 | MCOperand MCOp; |
585 | 0 | TmpInst.setOpcode(Mips::JR_MM); |
586 | | // Operand: rs |
587 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
588 | 0 | TmpInst.addOperand(MCOp); |
589 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
590 | 0 | break; |
591 | 0 | } |
592 | 0 | case Mips::PseudoIndirectBranch_MMR6: { |
593 | 0 | MCInst TmpInst; |
594 | 0 | MCOperand MCOp; |
595 | 0 | TmpInst.setOpcode(Mips::JRC16_MMR6); |
596 | | // Operand: rs |
597 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
598 | 0 | TmpInst.addOperand(MCOp); |
599 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
600 | 0 | break; |
601 | 0 | } |
602 | 0 | case Mips::PseudoIndirectHazardBranch: { |
603 | 0 | MCInst TmpInst; |
604 | 0 | MCOperand MCOp; |
605 | 0 | TmpInst.setOpcode(Mips::JR_HB); |
606 | | // Operand: rs |
607 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
608 | 0 | TmpInst.addOperand(MCOp); |
609 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
610 | 0 | break; |
611 | 0 | } |
612 | 0 | case Mips::PseudoIndirectHazardBranch64: { |
613 | 0 | MCInst TmpInst; |
614 | 0 | MCOperand MCOp; |
615 | 0 | TmpInst.setOpcode(Mips::JR_HB64); |
616 | | // Operand: rs |
617 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
618 | 0 | TmpInst.addOperand(MCOp); |
619 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
620 | 0 | break; |
621 | 0 | } |
622 | 0 | case Mips::PseudoIndrectHazardBranch64R6: { |
623 | 0 | MCInst TmpInst; |
624 | 0 | MCOperand MCOp; |
625 | 0 | TmpInst.setOpcode(Mips::JR_HB64_R6); |
626 | | // Operand: rs |
627 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
628 | 0 | TmpInst.addOperand(MCOp); |
629 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
630 | 0 | break; |
631 | 0 | } |
632 | 0 | case Mips::PseudoIndrectHazardBranchR6: { |
633 | 0 | MCInst TmpInst; |
634 | 0 | MCOperand MCOp; |
635 | 0 | TmpInst.setOpcode(Mips::JR_HB_R6); |
636 | | // Operand: rs |
637 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
638 | 0 | TmpInst.addOperand(MCOp); |
639 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
640 | 0 | break; |
641 | 0 | } |
642 | 0 | case Mips::PseudoMADD: { |
643 | 0 | MCInst TmpInst; |
644 | 0 | MCOperand MCOp; |
645 | 0 | TmpInst.setOpcode(Mips::MADD); |
646 | | // Operand: rs |
647 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
648 | 0 | TmpInst.addOperand(MCOp); |
649 | | // Operand: rt |
650 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
651 | 0 | TmpInst.addOperand(MCOp); |
652 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
653 | 0 | break; |
654 | 0 | } |
655 | 0 | case Mips::PseudoMADDU: { |
656 | 0 | MCInst TmpInst; |
657 | 0 | MCOperand MCOp; |
658 | 0 | TmpInst.setOpcode(Mips::MADDU); |
659 | | // Operand: rs |
660 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
661 | 0 | TmpInst.addOperand(MCOp); |
662 | | // Operand: rt |
663 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
664 | 0 | TmpInst.addOperand(MCOp); |
665 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
666 | 0 | break; |
667 | 0 | } |
668 | 0 | case Mips::PseudoMADDU_MM: { |
669 | 0 | MCInst TmpInst; |
670 | 0 | MCOperand MCOp; |
671 | 0 | TmpInst.setOpcode(Mips::MADDU); |
672 | | // Operand: rs |
673 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
674 | 0 | TmpInst.addOperand(MCOp); |
675 | | // Operand: rt |
676 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
677 | 0 | TmpInst.addOperand(MCOp); |
678 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
679 | 0 | break; |
680 | 0 | } |
681 | 0 | case Mips::PseudoMADD_MM: { |
682 | 0 | MCInst TmpInst; |
683 | 0 | MCOperand MCOp; |
684 | 0 | TmpInst.setOpcode(Mips::MADD); |
685 | | // Operand: rs |
686 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
687 | 0 | TmpInst.addOperand(MCOp); |
688 | | // Operand: rt |
689 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
690 | 0 | TmpInst.addOperand(MCOp); |
691 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
692 | 0 | break; |
693 | 0 | } |
694 | 0 | case Mips::PseudoMSUB: { |
695 | 0 | MCInst TmpInst; |
696 | 0 | MCOperand MCOp; |
697 | 0 | TmpInst.setOpcode(Mips::MSUB); |
698 | | // Operand: rs |
699 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
700 | 0 | TmpInst.addOperand(MCOp); |
701 | | // Operand: rt |
702 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
703 | 0 | TmpInst.addOperand(MCOp); |
704 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
705 | 0 | break; |
706 | 0 | } |
707 | 0 | case Mips::PseudoMSUBU: { |
708 | 0 | MCInst TmpInst; |
709 | 0 | MCOperand MCOp; |
710 | 0 | TmpInst.setOpcode(Mips::MSUBU); |
711 | | // Operand: rs |
712 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
713 | 0 | TmpInst.addOperand(MCOp); |
714 | | // Operand: rt |
715 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
716 | 0 | TmpInst.addOperand(MCOp); |
717 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
718 | 0 | break; |
719 | 0 | } |
720 | 0 | case Mips::PseudoMSUBU_MM: { |
721 | 0 | MCInst TmpInst; |
722 | 0 | MCOperand MCOp; |
723 | 0 | TmpInst.setOpcode(Mips::MSUBU); |
724 | | // Operand: rs |
725 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
726 | 0 | TmpInst.addOperand(MCOp); |
727 | | // Operand: rt |
728 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
729 | 0 | TmpInst.addOperand(MCOp); |
730 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
731 | 0 | break; |
732 | 0 | } |
733 | 0 | case Mips::PseudoMSUB_MM: { |
734 | 0 | MCInst TmpInst; |
735 | 0 | MCOperand MCOp; |
736 | 0 | TmpInst.setOpcode(Mips::MSUB); |
737 | | // Operand: rs |
738 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
739 | 0 | TmpInst.addOperand(MCOp); |
740 | | // Operand: rt |
741 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
742 | 0 | TmpInst.addOperand(MCOp); |
743 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
744 | 0 | break; |
745 | 0 | } |
746 | 0 | case Mips::PseudoMULT: { |
747 | 0 | MCInst TmpInst; |
748 | 0 | MCOperand MCOp; |
749 | 0 | TmpInst.setOpcode(Mips::MULT); |
750 | | // Operand: rs |
751 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
752 | 0 | TmpInst.addOperand(MCOp); |
753 | | // Operand: rt |
754 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
755 | 0 | TmpInst.addOperand(MCOp); |
756 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
757 | 0 | break; |
758 | 0 | } |
759 | 0 | case Mips::PseudoMULT_MM: { |
760 | 0 | MCInst TmpInst; |
761 | 0 | MCOperand MCOp; |
762 | 0 | TmpInst.setOpcode(Mips::MULT); |
763 | | // Operand: rs |
764 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
765 | 0 | TmpInst.addOperand(MCOp); |
766 | | // Operand: rt |
767 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
768 | 0 | TmpInst.addOperand(MCOp); |
769 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
770 | 0 | break; |
771 | 0 | } |
772 | 0 | case Mips::PseudoMULTu: { |
773 | 0 | MCInst TmpInst; |
774 | 0 | MCOperand MCOp; |
775 | 0 | TmpInst.setOpcode(Mips::MULTu); |
776 | | // Operand: rs |
777 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
778 | 0 | TmpInst.addOperand(MCOp); |
779 | | // Operand: rt |
780 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
781 | 0 | TmpInst.addOperand(MCOp); |
782 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
783 | 0 | break; |
784 | 0 | } |
785 | 0 | case Mips::PseudoMULTu_MM: { |
786 | 0 | MCInst TmpInst; |
787 | 0 | MCOperand MCOp; |
788 | 0 | TmpInst.setOpcode(Mips::MULTu); |
789 | | // Operand: rs |
790 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
791 | 0 | TmpInst.addOperand(MCOp); |
792 | | // Operand: rt |
793 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
794 | 0 | TmpInst.addOperand(MCOp); |
795 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
796 | 0 | break; |
797 | 0 | } |
798 | 0 | case Mips::PseudoPICK_PH: { |
799 | 0 | MCInst TmpInst; |
800 | 0 | MCOperand MCOp; |
801 | 0 | TmpInst.setOpcode(Mips::PICK_PH); |
802 | | // Operand: rd |
803 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
804 | 0 | TmpInst.addOperand(MCOp); |
805 | | // Operand: rs |
806 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
807 | 0 | TmpInst.addOperand(MCOp); |
808 | | // Operand: rt |
809 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
810 | 0 | TmpInst.addOperand(MCOp); |
811 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
812 | 0 | break; |
813 | 0 | } |
814 | 0 | case Mips::PseudoPICK_QB: { |
815 | 0 | MCInst TmpInst; |
816 | 0 | MCOperand MCOp; |
817 | 0 | TmpInst.setOpcode(Mips::PICK_QB); |
818 | | // Operand: rd |
819 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
820 | 0 | TmpInst.addOperand(MCOp); |
821 | | // Operand: rs |
822 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
823 | 0 | TmpInst.addOperand(MCOp); |
824 | | // Operand: rt |
825 | 0 | lowerOperand(MI->getOperand(3), MCOp); |
826 | 0 | TmpInst.addOperand(MCOp); |
827 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
828 | 0 | break; |
829 | 0 | } |
830 | 0 | case Mips::PseudoSDIV: { |
831 | 0 | MCInst TmpInst; |
832 | 0 | MCOperand MCOp; |
833 | 0 | TmpInst.setOpcode(Mips::SDIV); |
834 | | // Operand: rs |
835 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
836 | 0 | TmpInst.addOperand(MCOp); |
837 | | // Operand: rt |
838 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
839 | 0 | TmpInst.addOperand(MCOp); |
840 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
841 | 0 | break; |
842 | 0 | } |
843 | 0 | case Mips::PseudoUDIV: { |
844 | 0 | MCInst TmpInst; |
845 | 0 | MCOperand MCOp; |
846 | 0 | TmpInst.setOpcode(Mips::UDIV); |
847 | | // Operand: rs |
848 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
849 | 0 | TmpInst.addOperand(MCOp); |
850 | | // Operand: rt |
851 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
852 | 0 | TmpInst.addOperand(MCOp); |
853 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
854 | 0 | break; |
855 | 0 | } |
856 | 0 | case Mips::SDIV_MM_Pseudo: { |
857 | 0 | MCInst TmpInst; |
858 | 0 | MCOperand MCOp; |
859 | 0 | TmpInst.setOpcode(Mips::SDIV_MM); |
860 | | // Operand: rs |
861 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
862 | 0 | TmpInst.addOperand(MCOp); |
863 | | // Operand: rt |
864 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
865 | 0 | TmpInst.addOperand(MCOp); |
866 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
867 | 0 | break; |
868 | 0 | } |
869 | 0 | case Mips::TAILCALL: { |
870 | 0 | MCInst TmpInst; |
871 | 0 | MCOperand MCOp; |
872 | 0 | TmpInst.setOpcode(Mips::J); |
873 | | // Operand: target |
874 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
875 | 0 | TmpInst.addOperand(MCOp); |
876 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
877 | 0 | break; |
878 | 0 | } |
879 | 0 | case Mips::TAILCALL64R6REG: { |
880 | 0 | MCInst TmpInst; |
881 | 0 | MCOperand MCOp; |
882 | 0 | TmpInst.setOpcode(Mips::JALR64); |
883 | | // Operand: rd |
884 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO_64)); |
885 | | // Operand: rs |
886 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
887 | 0 | TmpInst.addOperand(MCOp); |
888 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
889 | 0 | break; |
890 | 0 | } |
891 | 0 | case Mips::TAILCALLHB64R6REG: { |
892 | 0 | MCInst TmpInst; |
893 | 0 | MCOperand MCOp; |
894 | 0 | TmpInst.setOpcode(Mips::JR_HB64_R6); |
895 | | // Operand: rs |
896 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
897 | 0 | TmpInst.addOperand(MCOp); |
898 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
899 | 0 | break; |
900 | 0 | } |
901 | 0 | case Mips::TAILCALLHBR6REG: { |
902 | 0 | MCInst TmpInst; |
903 | 0 | MCOperand MCOp; |
904 | 0 | TmpInst.setOpcode(Mips::JR_HB_R6); |
905 | | // Operand: rs |
906 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
907 | 0 | TmpInst.addOperand(MCOp); |
908 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
909 | 0 | break; |
910 | 0 | } |
911 | 0 | case Mips::TAILCALLR6REG: { |
912 | 0 | MCInst TmpInst; |
913 | 0 | MCOperand MCOp; |
914 | 0 | TmpInst.setOpcode(Mips::JALR); |
915 | | // Operand: rd |
916 | 0 | TmpInst.addOperand(MCOperand::createReg(Mips::ZERO)); |
917 | | // Operand: rs |
918 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
919 | 0 | TmpInst.addOperand(MCOp); |
920 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
921 | 0 | break; |
922 | 0 | } |
923 | 0 | case Mips::TAILCALLREG: { |
924 | 0 | MCInst TmpInst; |
925 | 0 | MCOperand MCOp; |
926 | 0 | TmpInst.setOpcode(Mips::JR); |
927 | | // Operand: rs |
928 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
929 | 0 | TmpInst.addOperand(MCOp); |
930 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
931 | 0 | break; |
932 | 0 | } |
933 | 0 | case Mips::TAILCALLREG64: { |
934 | 0 | MCInst TmpInst; |
935 | 0 | MCOperand MCOp; |
936 | 0 | TmpInst.setOpcode(Mips::JR64); |
937 | | // Operand: rs |
938 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
939 | 0 | TmpInst.addOperand(MCOp); |
940 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
941 | 0 | break; |
942 | 0 | } |
943 | 0 | case Mips::TAILCALLREGHB: { |
944 | 0 | MCInst TmpInst; |
945 | 0 | MCOperand MCOp; |
946 | 0 | TmpInst.setOpcode(Mips::JR_HB); |
947 | | // Operand: rs |
948 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
949 | 0 | TmpInst.addOperand(MCOp); |
950 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
951 | 0 | break; |
952 | 0 | } |
953 | 0 | case Mips::TAILCALLREGHB64: { |
954 | 0 | MCInst TmpInst; |
955 | 0 | MCOperand MCOp; |
956 | 0 | TmpInst.setOpcode(Mips::JR_HB64); |
957 | | // Operand: rs |
958 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
959 | 0 | TmpInst.addOperand(MCOp); |
960 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
961 | 0 | break; |
962 | 0 | } |
963 | 0 | case Mips::TAILCALLREG_MM: { |
964 | 0 | MCInst TmpInst; |
965 | 0 | MCOperand MCOp; |
966 | 0 | TmpInst.setOpcode(Mips::JRC16_MM); |
967 | | // Operand: rs |
968 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
969 | 0 | TmpInst.addOperand(MCOp); |
970 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
971 | 0 | break; |
972 | 0 | } |
973 | 0 | case Mips::TAILCALLREG_MMR6: { |
974 | 0 | MCInst TmpInst; |
975 | 0 | MCOperand MCOp; |
976 | 0 | TmpInst.setOpcode(Mips::JRC16_MM); |
977 | | // Operand: rs |
978 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
979 | 0 | TmpInst.addOperand(MCOp); |
980 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
981 | 0 | break; |
982 | 0 | } |
983 | 0 | case Mips::TAILCALL_MM: { |
984 | 0 | MCInst TmpInst; |
985 | 0 | MCOperand MCOp; |
986 | 0 | TmpInst.setOpcode(Mips::J_MM); |
987 | | // Operand: target |
988 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
989 | 0 | TmpInst.addOperand(MCOp); |
990 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
991 | 0 | break; |
992 | 0 | } |
993 | 0 | case Mips::TAILCALL_MMR6: { |
994 | 0 | MCInst TmpInst; |
995 | 0 | MCOperand MCOp; |
996 | 0 | TmpInst.setOpcode(Mips::BC_MMR6); |
997 | | // Operand: offset |
998 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
999 | 0 | TmpInst.addOperand(MCOp); |
1000 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1001 | 0 | break; |
1002 | 0 | } |
1003 | 0 | case Mips::TRAP: { |
1004 | 0 | MCInst TmpInst; |
1005 | 0 | MCOperand MCOp; |
1006 | 0 | TmpInst.setOpcode(Mips::BREAK); |
1007 | | // Operand: code_1 |
1008 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
1009 | | // Operand: code_2 |
1010 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
1011 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1012 | 0 | break; |
1013 | 0 | } |
1014 | 0 | case Mips::TRAP_MM: { |
1015 | 0 | MCInst TmpInst; |
1016 | 0 | MCOperand MCOp; |
1017 | 0 | TmpInst.setOpcode(Mips::BREAK_MM); |
1018 | | // Operand: code_1 |
1019 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
1020 | | // Operand: code_2 |
1021 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
1022 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1023 | 0 | break; |
1024 | 0 | } |
1025 | 0 | case Mips::UDIV_MM_Pseudo: { |
1026 | 0 | MCInst TmpInst; |
1027 | 0 | MCOperand MCOp; |
1028 | 0 | TmpInst.setOpcode(Mips::UDIV_MM); |
1029 | | // Operand: rs |
1030 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1031 | 0 | TmpInst.addOperand(MCOp); |
1032 | | // Operand: rt |
1033 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1034 | 0 | TmpInst.addOperand(MCOp); |
1035 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1036 | 0 | break; |
1037 | 0 | } |
1038 | 0 | case Mips::XOR_V_D_PSEUDO: { |
1039 | 0 | MCInst TmpInst; |
1040 | 0 | MCOperand MCOp; |
1041 | 0 | TmpInst.setOpcode(Mips::XOR_V); |
1042 | | // Operand: wd |
1043 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1044 | 0 | TmpInst.addOperand(MCOp); |
1045 | | // Operand: ws |
1046 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1047 | 0 | TmpInst.addOperand(MCOp); |
1048 | | // Operand: wt |
1049 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1050 | 0 | TmpInst.addOperand(MCOp); |
1051 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1052 | 0 | break; |
1053 | 0 | } |
1054 | 0 | case Mips::XOR_V_H_PSEUDO: { |
1055 | 0 | MCInst TmpInst; |
1056 | 0 | MCOperand MCOp; |
1057 | 0 | TmpInst.setOpcode(Mips::XOR_V); |
1058 | | // Operand: wd |
1059 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1060 | 0 | TmpInst.addOperand(MCOp); |
1061 | | // Operand: ws |
1062 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1063 | 0 | TmpInst.addOperand(MCOp); |
1064 | | // Operand: wt |
1065 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1066 | 0 | TmpInst.addOperand(MCOp); |
1067 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1068 | 0 | break; |
1069 | 0 | } |
1070 | 0 | case Mips::XOR_V_W_PSEUDO: { |
1071 | 0 | MCInst TmpInst; |
1072 | 0 | MCOperand MCOp; |
1073 | 0 | TmpInst.setOpcode(Mips::XOR_V); |
1074 | | // Operand: wd |
1075 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
1076 | 0 | TmpInst.addOperand(MCOp); |
1077 | | // Operand: ws |
1078 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
1079 | 0 | TmpInst.addOperand(MCOp); |
1080 | | // Operand: wt |
1081 | 0 | lowerOperand(MI->getOperand(2), MCOp); |
1082 | 0 | TmpInst.addOperand(MCOp); |
1083 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
1084 | 0 | break; |
1085 | 0 | } |
1086 | 206 | } |
1087 | 0 | return true; |
1088 | 206 | } |
1089 | | |