Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Mips/MipsGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace Mips {
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enum : unsigned {
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  InvalidRegBankID = ~0u,
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  FPRBRegBankID = 0,
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  GPRBRegBankID = 1,
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  NumRegisterBanks,
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};
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} // end namespace Mips
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static const RegisterBank *RegBanks[];
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  static const unsigned Sizes[];
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protected:
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  MipsGenRegisterBankInfo(unsigned HwMode = 0);
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace Mips {
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const uint32_t FPRBRegBankCoverageData[] = {
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    // 0-31
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    (1u << (Mips::FGR32RegClassID - 0)) |
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    (1u << (Mips::FGRCCRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (Mips::FGR64RegClassID - 32)) |
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    (1u << (Mips::AFGR64RegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (Mips::MSA128DRegClassID - 64)) |
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    (1u << (Mips::MSA128BRegClassID - 64)) |
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    (1u << (Mips::MSA128HRegClassID - 64)) |
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    (1u << (Mips::MSA128WRegClassID - 64)) |
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    (1u << (Mips::MSA128WEvensRegClassID - 64)) |
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    0,
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};
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const uint32_t GPRBRegBankCoverageData[] = {
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    // 0-31
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    (1u << (Mips::GPR32RegClassID - 0)) |
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    (1u << (Mips::GPR32NONZERORegClassID - 0)) |
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    (1u << (Mips::CPU16RegsPlusSPRegClassID - 0)) |
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    (1u << (Mips::CPU16RegsRegClassID - 0)) |
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    (1u << (Mips::GPRMM16RegClassID - 0)) |
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    (1u << (Mips::CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
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    (1u << (Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MovePPairFirstRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID - 0)) |
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    (1u << (Mips::CPU16Regs_and_GPRMM16MovePRegClassID - 0)) |
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    (1u << (Mips::CPUSPRegRegClassID - 0)) |
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    (1u << (Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MovePPairSecondRegClassID - 0)) |
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    (1u << (Mips::CPURARegRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MovePRegClassID - 0)) |
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    (1u << (Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID - 0)) |
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    (1u << (Mips::GPRMM16ZeroRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (Mips::SP32RegClassID - 32)) |
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    (1u << (Mips::GP32RegClassID - 32)) |
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    (1u << (Mips::GPR32ZERORegClassID - 32)) |
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    0,
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    // 64-95
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    0,
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};
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constexpr RegisterBank FPRBRegBank(/* ID */ Mips::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 70);
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constexpr RegisterBank GPRBRegBank(/* ID */ Mips::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 70);
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} // end namespace Mips
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const RegisterBank *MipsGenRegisterBankInfo::RegBanks[] = {
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    &Mips::FPRBRegBank,
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    &Mips::GPRBRegBank,
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};
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const unsigned MipsGenRegisterBankInfo::Sizes[] = {
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    // Mode = 0 (Default)
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    128,
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    32,
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};
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MipsGenRegisterBankInfo::MipsGenRegisterBankInfo(unsigned HwMode)
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    : RegisterBankInfo(RegBanks, Mips::NumRegisterBanks, Sizes, HwMode) {
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  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  for (auto RB : enumerate(RegBanks))
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    assert(RB.index() == RB.value()->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL