/src/build/lib/Target/Mips/MipsGenRegisterInfo.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass MipsMCRegisterClasses[];

namespace Mips {
enum {
  NoRegister,
  AT = 1,
  DSPCCond = 2,
  DSPCarry = 3,
  DSPEFI = 4,
  DSPOutFlag = 5,
  DSPPos = 6,
  DSPSCount = 7,
  FP = 8,
  GP = 9,
  MSAAccess = 10,
  MSACSR = 11,
  MSAIR = 12,
  MSAMap = 13,
  MSAModify = 14,
  MSARequest = 15,
  MSASave = 16,
  MSAUnmap = 17,
  PC = 18,
  RA = 19,
  SP = 20,
  ZERO = 21,
  A0 = 22,
  A1 = 23,
  A2 = 24,
  A3 = 25,
  AC0 = 26,
  AC1 = 27,
  AC2 = 28,
  AC3 = 29,
  AT_64 = 30,
  COP00 = 31,
  COP01 = 32,
  COP02 = 33,
  COP03 = 34,
  COP04 = 35,
  COP05 = 36,
  COP06 = 37,
  COP07 = 38,
  COP08 = 39,
  COP09 = 40,
  COP20 = 41,
  COP21 = 42,
  COP22 = 43,
  COP23 = 44,
  COP24 = 45,
  COP25 = 46,
  COP26 = 47,
  COP27 = 48,
  COP28 = 49,
  COP29 = 50,
  COP30 = 51,
  COP31 = 52,
  COP32 = 53,
  COP33 = 54,
  COP34 = 55,
  COP35 = 56,
  COP36 = 57,
  COP37 = 58,
  COP38 = 59,
  COP39 = 60,
  COP010 = 61,
  COP011 = 62,
  COP012 = 63,
  COP013 = 64,
  COP014 = 65,
  COP015 = 66,
  COP016 = 67,
  COP017 = 68,
  COP018 = 69,
  COP019 = 70,
  COP020 = 71,
  COP021 = 72,
  COP022 = 73,
  COP023 = 74,
  COP024 = 75,
  COP025 = 76,
  COP026 = 77,
  COP027 = 78,
  COP028 = 79,
  COP029 = 80,
  COP030 = 81,
  COP031 = 82,
  COP210 = 83,
  COP211 = 84,
  COP212 = 85,
  COP213 = 86,
  COP214 = 87,
  COP215 = 88,
  COP216 = 89,
  COP217 = 90,
  COP218 = 91,
  COP219 = 92,
  COP220 = 93,
  COP221 = 94,
  COP222 = 95,
  COP223 = 96,
  COP224 = 97,
  COP225 = 98,
  COP226 = 99,
  COP227 = 100,
  COP228 = 101,
  COP229 = 102,
  COP230 = 103,
  COP231 = 104,
  COP310 = 105,
  COP311 = 106,
  COP312 = 107,
  COP313 = 108,
  COP314 = 109,
  COP315 = 110,
  COP316 = 111,
  COP317 = 112,
  COP318 = 113,
  COP319 = 114,
  COP320 = 115,
  COP321 = 116,
  COP322 = 117,
  COP323 = 118,
  COP324 = 119,
  COP325 = 120,
  COP326 = 121,
  COP327 = 122,
  COP328 = 123,
  COP329 = 124,
  COP330 = 125,
  COP331 = 126,
  D0 = 127,
  D1 = 128,
  D2 = 129,
  D3 = 130,
  D4 = 131,
  D5 = 132,
  D6 = 133,
  D7 = 134,
  D8 = 135,
  D9 = 136,
  D10 = 137,
  D11 = 138,
  D12 = 139,
  D13 = 140,
  D14 = 141,
  D15 = 142,
  DSPOutFlag20 = 143,
  DSPOutFlag21 = 144,
  DSPOutFlag22 = 145,
  DSPOutFlag23 = 146,
  F0 = 147,
  F1 = 148,
  F2 = 149,
  F3 = 150,
  F4 = 151,
  F5 = 152,
  F6 = 153,
  F7 = 154,
  F8 = 155,
  F9 = 156,
  F10 = 157,
  F11 = 158,
  F12 = 159,
  F13 = 160,
  F14 = 161,
  F15 = 162,
  F16 = 163,
  F17 = 164,
  F18 = 165,
  F19 = 166,
  F20 = 167,
  F21 = 168,
  F22 = 169,
  F23 = 170,
  F24 = 171,
  F25 = 172,
  F26 = 173,
  F27 = 174,
  F28 = 175,
  F29 = 176,
  F30 = 177,
  F31 = 178,
  FCC0 = 179,
  FCC1 = 180,
  FCC2 = 181,
  FCC3 = 182,
  FCC4 = 183,
  FCC5 = 184,
  FCC6 = 185,
  FCC7 = 186,
  FCR0 = 187,
  FCR1 = 188,
  FCR2 = 189,
  FCR3 = 190,
  FCR4 = 191,
  FCR5 = 192,
  FCR6 = 193,
  FCR7 = 194,
  FCR8 = 195,
  FCR9 = 196,
  FCR10 = 197,
  FCR11 = 198,
  FCR12 = 199,
  FCR13 = 200,
  FCR14 = 201,
  FCR15 = 202,
  FCR16 = 203,
  FCR17 = 204,
  FCR18 = 205,
  FCR19 = 206,
  FCR20 = 207,
  FCR21 = 208,
  FCR22 = 209,
  FCR23 = 210,
  FCR24 = 211,
  FCR25 = 212,
  FCR26 = 213,
  FCR27 = 214,
  FCR28 = 215,
  FCR29 = 216,
  FCR30 = 217,
  FCR31 = 218,
  FP_64 = 219,
  F_HI0 = 220,
  F_HI1 = 221,
  F_HI2 = 222,
  F_HI3 = 223,
  F_HI4 = 224,
  F_HI5 = 225,
  F_HI6 = 226,
  F_HI7 = 227,
  F_HI8 = 228,
  F_HI9 = 229,
  F_HI10 = 230,
  F_HI11 = 231,
  F_HI12 = 232,
  F_HI13 = 233,
  F_HI14 = 234,
  F_HI15 = 235,
  F_HI16 = 236,
  F_HI17 = 237,
  F_HI18 = 238,
  F_HI19 = 239,
  F_HI20 = 240,
  F_HI21 = 241,
  F_HI22 = 242,
  F_HI23 = 243,
  F_HI24 = 244,
  F_HI25 = 245,
  F_HI26 = 246,
  F_HI27 = 247,
  F_HI28 = 248,
  F_HI29 = 249,
  F_HI30 = 250,
  F_HI31 = 251,
  GP_64 = 252,
  HI0 = 253,
  HI1 = 254,
  HI2 = 255,
  HI3 = 256,
  HWR0 = 257,
  HWR1 = 258,
  HWR2 = 259,
  HWR3 = 260,
  HWR4 = 261,
  HWR5 = 262,
  HWR6 = 263,
  HWR7 = 264,
  HWR8 = 265,
  HWR9 = 266,
  HWR10 = 267,
  HWR11 = 268,
  HWR12 = 269,
  HWR13 = 270,
  HWR14 = 271,
  HWR15 = 272,
  HWR16 = 273,
  HWR17 = 274,
  HWR18 = 275,
  HWR19 = 276,
  HWR20 = 277,
  HWR21 = 278,
  HWR22 = 279,
  HWR23 = 280,
  HWR24 = 281,
  HWR25 = 282,
  HWR26 = 283,
  HWR27 = 284,
  HWR28 = 285,
  HWR29 = 286,
  HWR30 = 287,
  HWR31 = 288,
  K0 = 289,
  K1 = 290,
  LO0 = 291,
  LO1 = 292,
  LO2 = 293,
  LO3 = 294,
  MPL0 = 295,
  MPL1 = 296,
  MPL2 = 297,
  MSA8 = 298,
  MSA9 = 299,
  MSA10 = 300,
  MSA11 = 301,
  MSA12 = 302,
  MSA13 = 303,
  MSA14 = 304,
  MSA15 = 305,
  MSA16 = 306,
  MSA17 = 307,
  MSA18 = 308,
  MSA19 = 309,
  MSA20 = 310,
  MSA21 = 311,
  MSA22 = 312,
  MSA23 = 313,
  MSA24 = 314,
  MSA25 = 315,
  MSA26 = 316,
  MSA27 = 317,
  MSA28 = 318,
  MSA29 = 319,
  MSA30 = 320,
  MSA31 = 321,
  P0 = 322,
  P1 = 323,
  P2 = 324,
  RA_64 = 325,
  S0 = 326,
  S1 = 327,
  S2 = 328,
  S3 = 329,
  S4 = 330,
  S5 = 331,
  S6 = 332,
  S7 = 333,
  SP_64 = 334,
  T0 = 335,
  T1 = 336,
  T2 = 337,
  T3 = 338,
  T4 = 339,
  T5 = 340,
  T6 = 341,
  T7 = 342,
  T8 = 343,
  T9 = 344,
  V0 = 345,
  V1 = 346,
  W0 = 347,
  W1 = 348,
  W2 = 349,
  W3 = 350,
  W4 = 351,
  W5 = 352,
  W6 = 353,
  W7 = 354,
  W8 = 355,
  W9 = 356,
  W10 = 357,
  W11 = 358,
  W12 = 359,
  W13 = 360,
  W14 = 361,
  W15 = 362,
  W16 = 363,
  W17 = 364,
  W18 = 365,
  W19 = 366,
  W20 = 367,
  W21 = 368,
  W22 = 369,
  W23 = 370,
  W24 = 371,
  W25 = 372,
  W26 = 373,
  W27 = 374,
  W28 = 375,
  W29 = 376,
  W30 = 377,
  W31 = 378,
  ZERO_64 = 379,
  A0_64 = 380,
  A1_64 = 381,
  A2_64 = 382,
  A3_64 = 383,
  AC0_64 = 384,
  D0_64 = 385,
  D1_64 = 386,
  D2_64 = 387,
  D3_64 = 388,
  D4_64 = 389,
  D5_64 = 390,
  D6_64 = 391,
  D7_64 = 392,
  D8_64 = 393,
  D9_64 = 394,
  D10_64 = 395,
  D11_64 = 396,
  D12_64 = 397,
  D13_64 = 398,
  D14_64 = 399,
  D15_64 = 400,
  D16_64 = 401,
  D17_64 = 402,
  D18_64 = 403,
  D19_64 = 404,
  D20_64 = 405,
  D21_64 = 406,
  D22_64 = 407,
  D23_64 = 408,
  D24_64 = 409,
  D25_64 = 410,
  D26_64 = 411,
  D27_64 = 412,
  D28_64 = 413,
  D29_64 = 414,
  D30_64 = 415,
  D31_64 = 416,
  DSPOutFlag16_19 = 417,
  HI0_64 = 418,
  K0_64 = 419,
  K1_64 = 420,
  LO0_64 = 421,
  S0_64 = 422,
  S1_64 = 423,
  S2_64 = 424,
  S3_64 = 425,
  S4_64 = 426,
  S5_64 = 427,
  S6_64 = 428,
  S7_64 = 429,
  T0_64 = 430,
  T1_64 = 431,
  T2_64 = 432,
  T3_64 = 433,
  T4_64 = 434,
  T5_64 = 435,
  T6_64 = 436,
  T7_64 = 437,
  T8_64 = 438,
  T9_64 = 439,
  V0_64 = 440,
  V1_64 = 441,
  NUM_TARGET_REGS // 442
};
} // end namespace Mips

// Register classes

namespace Mips {
enum {
  MSA128F16RegClassID = 0,
  CCRRegClassID = 1,
  COP0RegClassID = 2,
  COP2RegClassID = 3,
  COP3RegClassID = 4,
  DSPRRegClassID = 5,
  FGR32RegClassID = 6,
  FGRCCRegClassID = 7,
  GPR32RegClassID = 8,
  HWRegsRegClassID = 9,
  MSACtrlRegClassID = 10,
  GPR32NONZERORegClassID = 11,
  CPU16RegsPlusSPRegClassID = 12,
  CPU16RegsRegClassID = 13,
  FCCRegClassID = 14,
  GPRMM16RegClassID = 15,
  GPRMM16MovePRegClassID = 16,
  GPRMM16ZeroRegClassID = 17,
  CPU16Regs_and_GPRMM16ZeroRegClassID = 18,
  GPR32NONZERO_and_GPRMM16MovePRegClassID = 19,
  GPRMM16MovePPairSecondRegClassID = 20,
  CPU16Regs_and_GPRMM16MovePRegClassID = 21,
  GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 22,
  HI32DSPRegClassID = 23,
  LO32DSPRegClassID = 24,
  CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 25,
  GPRMM16MovePPairFirstRegClassID = 26,
  GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 27,
  GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 28,
  CPURARegRegClassID = 29,
  CPUSPRegRegClassID = 30,
  DSPCCRegClassID = 31,
  GP32RegClassID = 32,
  GPR32ZERORegClassID = 33,
  HI32RegClassID = 34,
  LO32RegClassID = 35,
  SP32RegClassID = 36,
  FGR64RegClassID = 37,
  GPR64RegClassID = 38,
  GPR64_with_sub_32_in_GPR32NONZERORegClassID = 39,
  AFGR64RegClassID = 40,
  GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 41,
  GPR64_with_sub_32_in_CPU16RegsRegClassID = 42,
  GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 43,
  GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 44,
  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 45,
  GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID = 46,
  GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID = 47,
  ACC64DSPRegClassID = 48,
  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 49,
  GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 50,
  GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID = 51,
  GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID = 52,
  GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 53,
  OCTEON_MPLRegClassID = 54,
  OCTEON_PRegClassID = 55,
  GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID = 56,
  ACC64RegClassID = 57,
  GP64RegClassID = 58,
  GPR64_with_sub_32_in_CPURARegRegClassID = 59,
  GPR64_with_sub_32_in_GPR32ZERORegClassID = 60,
  HI64RegClassID = 61,
  LO64RegClassID = 62,
  SP64RegClassID = 63,
  MSA128BRegClassID = 64,
  MSA128DRegClassID = 65,
  MSA128HRegClassID = 66,
  MSA128WRegClassID = 67,
  MSA128WEvensRegClassID = 68,
  ACC128RegClassID = 69,

};
} // end namespace Mips


// Subregister indices

namespace Mips {
enum : uint16_t {
  NoSubRegister,
  sub_32, // 1
  sub_64, // 2
  sub_dsp16_19, // 3
  sub_dsp20,  // 4
  sub_dsp21,  // 5
  sub_dsp22,  // 6
  sub_dsp23,  // 7
  sub_hi, // 8
  sub_lo, // 9
  sub_hi_then_sub_32, // 10
  sub_32_sub_hi_then_sub_32,  // 11
  NUM_TARGET_SUBREGS
};
} // end namespace Mips

// Register pressure sets enum.
namespace Mips {
enum RegisterPressureSets {
  DSPCC = 0,
  GPR32ZERO = 1,
  GPR64_with_sub_32_in_CPURAReg = 2,
  HI32 = 3,
  GPRMM16MovePPairFirst = 4,
  CPU16Regs_and_GPRMM16MoveP = 5,
  HI32DSP = 6,
  LO32DSP = 7,
  GPRMM16MovePPairSecond = 8,
  GPRMM16MoveP = 9,
  ACC64DSP = 10,
  CPU16Regs = 11,
  GPRMM16Zero_with_GPRMM16MovePPairSecond = 12,
  CPU16Regs_with_GPRMM16MovePPairSecond = 13,
  CPU16Regs_with_GPRMM16MoveP = 14,
  DSPR = 15,
  FGR32 = 16,
  MSA128WEvens = 17,
  FGR32_with_MSA128WEvens = 18,
  MSA128F16 = 19,
};
} // end namespace Mips

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t MipsRegDiffLists[] = {
  /* 0 */ -412, 0,
  /* 2 */ -358, 0,
  /* 4 */ -314, 0,
  /* 6 */ -306, 0,
  /* 8 */ -265, 0,
  /* 10 */ -243, 0,
  /* 12 */ 37, -130, 127, -165, -227, 0,
  /* 18 */ -211, 0,
  /* 20 */ -165, 0,
  /* 22 */ -141, 0,
  /* 24 */ -140, 0,
  /* 26 */ -139, 0,
  /* 28 */ -138, 0,
  /* 30 */ -130, 0,
  /* 32 */ -96, 0,
  /* 34 */ -95, 0,
  /* 36 */ 165, -38, 0,
  /* 39 */ -20, 258, -38, 0,
  /* 43 */ -21, 259, -38, 0,
  /* 47 */ -22, 260, -38, 0,
  /* 51 */ -23, 261, -38, 0,
  /* 55 */ -24, 262, -38, 0,
  /* 59 */ -25, 263, -38, 0,
  /* 63 */ -26, 264, -38, 0,
  /* 67 */ -27, 265, -38, 0,
  /* 71 */ -28, 266, -38, 0,
  /* 75 */ -29, 267, -38, 0,
  /* 79 */ -30, 268, -38, 0,
  /* 83 */ -31, 269, -38, 0,
  /* 87 */ -32, 270, -38, 0,
  /* 91 */ -33, 271, -38, 0,
  /* 95 */ -34, 272, -38, 0,
  /* 99 */ -35, 273, -38, 0,
  /* 103 */ -36, 274, -38, 0,
  /* 107 */ -265, 395, -37, 0,
  /* 111 */ -227, 392, -34, 0,
  /* 115 */ -29, 0,
  /* 117 */ 412, -274, 1, 1, 1, 0,
  /* 123 */ 1, 1, 1, 1, 0,
  /* 128 */ 20, 1, 0,
  /* 131 */ 21, 1, 0,
  /* 134 */ 22, 1, 0,
  /* 137 */ 23, 1, 0,
  /* 140 */ 24, 1, 0,
  /* 143 */ 25, 1, 0,
  /* 146 */ 26, 1, 0,
  /* 149 */ 27, 1, 0,
  /* 152 */ 28, 1, 0,
  /* 155 */ 29, 1, 0,
  /* 158 */ 30, 1, 0,
  /* 161 */ 31, 1, 0,
  /* 164 */ 32, 1, 0,
  /* 167 */ 33, 1, 0,
  /* 170 */ 34, 1, 0,
  /* 173 */ 35, 1, 0,
  /* 176 */ 29, 0,
  /* 178 */ 72, 0,
  /* 180 */ 38, -238, 73, 0,
  /* 184 */ 95, 0,
  /* 186 */ 96, 0,
  /* 188 */ 130, 0,
  /* 190 */ 211, 0,
  /* 192 */ 243, 0,
  /* 194 */ 306, 0,
  /* 196 */ 314, 0,
  /* 198 */ 358, 0,
};

extern const LaneBitmask MipsLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
  /* 8 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
  /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t MipsSubRegIdxLists[] = {
  /* 0 */ 1, 0,
  /* 2 */ 3, 4, 5, 6, 7, 0,
  /* 8 */ 2, 9, 8, 0,
  /* 12 */ 9, 1, 8, 10, 11, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 32 },  // sub_32
  { 0, 64 },  // sub_64
  { 16, 4 },  // sub_dsp16_19
  { 20, 1 },  // sub_dsp20
  { 21, 1 },  // sub_dsp21
  { 22, 1 },  // sub_dsp22
  { 23, 1 },  // sub_dsp23
  { 32, 32 }, // sub_hi
  { 0, 32 },  // sub_lo
  { 32, 32 }, // sub_hi_then_sub_32
  { 0, 64 },  // sub_32_sub_hi_then_sub_32
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char MipsRegStrings[] = {
  /* 0 */ "COP00\0"
  /* 6 */ "COP010\0"
  /* 13 */ "COP210\0"
  /* 20 */ "COP310\0"
  /* 27 */ "MSA10\0"
  /* 33 */ "D10\0"
  /* 37 */ "F10\0"
  /* 41 */ "F_HI10\0"
  /* 48 */ "FCR10\0"
  /* 54 */ "HWR10\0"
  /* 60 */ "W10\0"
  /* 64 */ "COP020\0"
  /* 71 */ "COP220\0"
  /* 78 */ "COP320\0"
  /* 85 */ "MSA20\0"
  /* 91 */ "F20\0"
  /* 95 */ "F_HI20\0"
  /* 102 */ "COP20\0"
  /* 108 */ "FCR20\0"
  /* 114 */ "HWR20\0"
  /* 120 */ "W20\0"
  /* 124 */ "DSPOutFlag20\0"
  /* 137 */ "COP030\0"
  /* 144 */ "COP230\0"
  /* 151 */ "COP330\0"
  /* 158 */ "MSA30\0"
  /* 164 */ "F30\0"
  /* 168 */ "F_HI30\0"
  /* 175 */ "COP30\0"
  /* 181 */ "FCR30\0"
  /* 187 */ "HWR30\0"
  /* 193 */ "W30\0"
  /* 197 */ "A0\0"
  /* 200 */ "AC0\0"
  /* 204 */ "FCC0\0"
  /* 209 */ "D0\0"
  /* 212 */ "F0\0"
  /* 215 */ "F_HI0\0"
  /* 221 */ "K0\0"
  /* 224 */ "MPL0\0"
  /* 229 */ "LO0\0"
  /* 233 */ "P0\0"
  /* 236 */ "FCR0\0"
  /* 241 */ "HWR0\0"
  /* 246 */ "S0\0"
  /* 249 */ "T0\0"
  /* 252 */ "V0\0"
  /* 255 */ "W0\0"
  /* 258 */ "COP01\0"
  /* 264 */ "COP011\0"
  /* 271 */ "COP211\0"
  /* 278 */ "COP311\0"
  /* 285 */ "MSA11\0"
  /* 291 */ "D11\0"
  /* 295 */ "F11\0"
  /* 299 */ "F_HI11\0"
  /* 306 */ "FCR11\0"
  /* 312 */ "HWR11\0"
  /* 318 */ "W11\0"
  /* 322 */ "COP021\0"
  /* 329 */ "COP221\0"
  /* 336 */ "COP321\0"
  /* 343 */ "MSA21\0"
  /* 349 */ "F21\0"
  /* 353 */ "F_HI21\0"
  /* 360 */ "COP21\0"
  /* 366 */ "FCR21\0"
  /* 372 */ "HWR21\0"
  /* 378 */ "W21\0"
  /* 382 */ "DSPOutFlag21\0"
  /* 395 */ "COP031\0"
  /* 402 */ "COP231\0"
  /* 409 */ "COP331\0"
  /* 416 */ "MSA31\0"
  /* 422 */ "F31\0"
  /* 426 */ "F_HI31\0"
  /* 433 */ "COP31\0"
  /* 439 */ "FCR31\0"
  /* 445 */ "HWR31\0"
  /* 451 */ "W31\0"
  /* 455 */ "A1\0"
  /* 458 */ "AC1\0"
  /* 462 */ "FCC1\0"
  /* 467 */ "D1\0"
  /* 470 */ "F1\0"
  /* 473 */ "F_HI1\0"
  /* 479 */ "K1\0"
  /* 482 */ "MPL1\0"
  /* 487 */ "LO1\0"
  /* 491 */ "P1\0"
  /* 494 */ "FCR1\0"
  /* 499 */ "HWR1\0"
  /* 504 */ "S1\0"
  /* 507 */ "T1\0"
  /* 510 */ "V1\0"
  /* 513 */ "W1\0"
  /* 516 */ "COP02\0"
  /* 522 */ "COP012\0"
  /* 529 */ "COP212\0"
  /* 536 */ "COP312\0"
  /* 543 */ "MSA12\0"
  /* 549 */ "D12\0"
  /* 553 */ "F12\0"
  /* 557 */ "F_HI12\0"
  /* 564 */ "FCR12\0"
  /* 570 */ "HWR12\0"
  /* 576 */ "W12\0"
  /* 580 */ "COP022\0"
  /* 587 */ "COP222\0"
  /* 594 */ "COP322\0"
  /* 601 */ "MSA22\0"
  /* 607 */ "F22\0"
  /* 611 */ "F_HI22\0"
  /* 618 */ "COP22\0"
  /* 624 */ "FCR22\0"
  /* 630 */ "HWR22\0"
  /* 636 */ "W22\0"
  /* 640 */ "DSPOutFlag22\0"
  /* 653 */ "COP32\0"
  /* 659 */ "A2\0"
  /* 662 */ "AC2\0"
  /* 666 */ "FCC2\0"
  /* 671 */ "D2\0"
  /* 674 */ "F2\0"
  /* 677 */ "F_HI2\0"
  /* 683 */ "MPL2\0"
  /* 688 */ "LO2\0"
  /* 692 */ "P2\0"
  /* 695 */ "FCR2\0"
  /* 700 */ "HWR2\0"
  /* 705 */ "S2\0"
  /* 708 */ "T2\0"
  /* 711 */ "W2\0"
  /* 714 */ "COP03\0"
  /* 720 */ "COP013\0"
  /* 727 */ "COP213\0"
  /* 734 */ "COP313\0"
  /* 741 */ "MSA13\0"
  /* 747 */ "D13\0"
  /* 751 */ "F13\0"
  /* 755 */ "F_HI13\0"
  /* 762 */ "FCR13\0"
  /* 768 */ "HWR13\0"
  /* 774 */ "W13\0"
  /* 778 */ "COP023\0"
  /* 785 */ "COP223\0"
  /* 792 */ "COP323\0"
  /* 799 */ "MSA23\0"
  /* 805 */ "F23\0"
  /* 809 */ "F_HI23\0"
  /* 816 */ "COP23\0"
  /* 822 */ "FCR23\0"
  /* 828 */ "HWR23\0"
  /* 834 */ "W23\0"
  /* 838 */ "DSPOutFlag23\0"
  /* 851 */ "COP33\0"
  /* 857 */ "A3\0"
  /* 860 */ "AC3\0"
  /* 864 */ "FCC3\0"
  /* 869 */ "D3\0"
  /* 872 */ "F3\0"
  /* 875 */ "F_HI3\0"
  /* 881 */ "LO3\0"
  /* 885 */ "FCR3\0"
  /* 890 */ "HWR3\0"
  /* 895 */ "S3\0"
  /* 898 */ "T3\0"
  /* 901 */ "W3\0"
  /* 904 */ "COP04\0"
  /* 910 */ "COP014\0"
  /* 917 */ "COP214\0"
  /* 924 */ "COP314\0"
  /* 931 */ "MSA14\0"
  /* 937 */ "D14\0"
  /* 941 */ "F14\0"
  /* 945 */ "F_HI14\0"
  /* 952 */ "FCR14\0"
  /* 958 */ "HWR14\0"
  /* 964 */ "W14\0"
  /* 968 */ "COP024\0"
  /* 975 */ "COP224\0"
  /* 982 */ "COP324\0"
  /* 989 */ "MSA24\0"
  /* 995 */ "F24\0"
  /* 999 */ "F_HI24\0"
  /* 1006 */ "COP24\0"
  /* 1012 */ "FCR24\0"
  /* 1018 */ "HWR24\0"
  /* 1024 */ "W24\0"
  /* 1028 */ "COP34\0"
  /* 1034 */ "D10_64\0"
  /* 1041 */ "D20_64\0"
  /* 1048 */ "D30_64\0"
  /* 1055 */ "A0_64\0"
  /* 1061 */ "AC0_64\0"
  /* 1068 */ "D0_64\0"
  /* 1074 */ "HI0_64\0"
  /* 1081 */ "K0_64\0"
  /* 1087 */ "LO0_64\0"
  /* 1094 */ "S0_64\0"
  /* 1100 */ "T0_64\0"
  /* 1106 */ "V0_64\0"
  /* 1112 */ "D11_64\0"
  /* 1119 */ "D21_64\0"
  /* 1126 */ "D31_64\0"
  /* 1133 */ "A1_64\0"
  /* 1139 */ "D1_64\0"
  /* 1145 */ "K1_64\0"
  /* 1151 */ "S1_64\0"
  /* 1157 */ "T1_64\0"
  /* 1163 */ "V1_64\0"
  /* 1169 */ "D12_64\0"
  /* 1176 */ "D22_64\0"
  /* 1183 */ "A2_64\0"
  /* 1189 */ "D2_64\0"
  /* 1195 */ "S2_64\0"
  /* 1201 */ "T2_64\0"
  /* 1207 */ "D13_64\0"
  /* 1214 */ "D23_64\0"
  /* 1221 */ "A3_64\0"
  /* 1227 */ "D3_64\0"
  /* 1233 */ "S3_64\0"
  /* 1239 */ "T3_64\0"
  /* 1245 */ "D14_64\0"
  /* 1252 */ "D24_64\0"
  /* 1259 */ "D4_64\0"
  /* 1265 */ "S4_64\0"
  /* 1271 */ "T4_64\0"
  /* 1277 */ "D15_64\0"
  /* 1284 */ "D25_64\0"
  /* 1291 */ "D5_64\0"
  /* 1297 */ "S5_64\0"
  /* 1303 */ "T5_64\0"
  /* 1309 */ "D16_64\0"
  /* 1316 */ "D26_64\0"
  /* 1323 */ "D6_64\0"
  /* 1329 */ "S6_64\0"
  /* 1335 */ "T6_64\0"
  /* 1341 */ "D17_64\0"
  /* 1348 */ "D27_64\0"
  /* 1355 */ "D7_64\0"
  /* 1361 */ "S7_64\0"
  /* 1367 */ "T7_64\0"
  /* 1373 */ "D18_64\0"
  /* 1380 */ "D28_64\0"
  /* 1387 */ "D8_64\0"
  /* 1393 */ "T8_64\0"
  /* 1399 */ "D19_64\0"
  /* 1406 */ "D29_64\0"
  /* 1413 */ "D9_64\0"
  /* 1419 */ "T9_64\0"
  /* 1425 */ "RA_64\0"
  /* 1431 */ "ZERO_64\0"
  /* 1439 */ "FP_64\0"
  /* 1445 */ "GP_64\0"
  /* 1451 */ "SP_64\0"
  /* 1457 */ "AT_64\0"
  /* 1463 */ "FCC4\0"
  /* 1468 */ "D4\0"
  /* 1471 */ "F4\0"
  /* 1474 */ "F_HI4\0"
  /* 1480 */ "FCR4\0"
  /* 1485 */ "HWR4\0"
  /* 1490 */ "S4\0"
  /* 1493 */ "T4\0"
  /* 1496 */ "W4\0"
  /* 1499 */ "COP05\0"
  /* 1505 */ "COP015\0"
  /* 1512 */ "COP215\0"
  /* 1519 */ "COP315\0"
  /* 1526 */ "MSA15\0"
  /* 1532 */ "D15\0"
  /* 1536 */ "F15\0"
  /* 1540 */ "F_HI15\0"
  /* 1547 */ "FCR15\0"
  /* 1553 */ "HWR15\0"
  /* 1559 */ "W15\0"
  /* 1563 */ "COP025\0"
  /* 1570 */ "COP225\0"
  /* 1577 */ "COP325\0"
  /* 1584 */ "MSA25\0"
  /* 1590 */ "F25\0"
  /* 1594 */ "F_HI25\0"
  /* 1601 */ "COP25\0"
  /* 1607 */ "FCR25\0"
  /* 1613 */ "HWR25\0"
  /* 1619 */ "W25\0"
  /* 1623 */ "COP35\0"
  /* 1629 */ "FCC5\0"
  /* 1634 */ "D5\0"
  /* 1637 */ "F5\0"
  /* 1640 */ "F_HI5\0"
  /* 1646 */ "FCR5\0"
  /* 1651 */ "HWR5\0"
  /* 1656 */ "S5\0"
  /* 1659 */ "T5\0"
  /* 1662 */ "W5\0"
  /* 1665 */ "COP06\0"
  /* 1671 */ "COP016\0"
  /* 1678 */ "COP216\0"
  /* 1685 */ "COP316\0"
  /* 1692 */ "MSA16\0"
  /* 1698 */ "F16\0"
  /* 1702 */ "F_HI16\0"
  /* 1709 */ "FCR16\0"
  /* 1715 */ "HWR16\0"
  /* 1721 */ "W16\0"
  /* 1725 */ "COP026\0"
  /* 1732 */ "COP226\0"
  /* 1739 */ "COP326\0"
  /* 1746 */ "MSA26\0"
  /* 1752 */ "F26\0"
  /* 1756 */ "F_HI26\0"
  /* 1763 */ "COP26\0"
  /* 1769 */ "FCR26\0"
  /* 1775 */ "HWR26\0"
  /* 1781 */ "W26\0"
  /* 1785 */ "COP36\0"
  /* 1791 */ "FCC6\0"
  /* 1796 */ "D6\0"
  /* 1799 */ "F6\0"
  /* 1802 */ "F_HI6\0"
  /* 1808 */ "FCR6\0"
  /* 1813 */ "HWR6\0"
  /* 1818 */ "S6\0"
  /* 1821 */ "T6\0"
  /* 1824 */ "W6\0"
  /* 1827 */ "COP07\0"
  /* 1833 */ "COP017\0"
  /* 1840 */ "COP217\0"
  /* 1847 */ "COP317\0"
  /* 1854 */ "MSA17\0"
  /* 1860 */ "F17\0"
  /* 1864 */ "F_HI17\0"
  /* 1871 */ "FCR17\0"
  /* 1877 */ "HWR17\0"
  /* 1883 */ "W17\0"
  /* 1887 */ "COP027\0"
  /* 1894 */ "COP227\0"
  /* 1901 */ "COP327\0"
  /* 1908 */ "MSA27\0"
  /* 1914 */ "F27\0"
  /* 1918 */ "F_HI27\0"
  /* 1925 */ "COP27\0"
  /* 1931 */ "FCR27\0"
  /* 1937 */ "HWR27\0"
  /* 1943 */ "W27\0"
  /* 1947 */ "COP37\0"
  /* 1953 */ "FCC7\0"
  /* 1958 */ "D7\0"
  /* 1961 */ "F7\0"
  /* 1964 */ "F_HI7\0"
  /* 1970 */ "FCR7\0"
  /* 1975 */ "HWR7\0"
  /* 1980 */ "S7\0"
  /* 1983 */ "T7\0"
  /* 1986 */ "W7\0"
  /* 1989 */ "COP08\0"
  /* 1995 */ "COP018\0"
  /* 2002 */ "COP218\0"
  /* 2009 */ "COP318\0"
  /* 2016 */ "MSA18\0"
  /* 2022 */ "F18\0"
  /* 2026 */ "F_HI18\0"
  /* 2033 */ "FCR18\0"
  /* 2039 */ "HWR18\0"
  /* 2045 */ "W18\0"
  /* 2049 */ "COP028\0"
  /* 2056 */ "COP228\0"
  /* 2063 */ "COP328\0"
  /* 2070 */ "MSA28\0"
  /* 2076 */ "F28\0"
  /* 2080 */ "F_HI28\0"
  /* 2087 */ "COP28\0"
  /* 2093 */ "FCR28\0"
  /* 2099 */ "HWR28\0"
  /* 2105 */ "W28\0"
  /* 2109 */ "COP38\0"
  /* 2115 */ "MSA8\0"
  /* 2120 */ "D8\0"
  /* 2123 */ "F8\0"
  /* 2126 */ "F_HI8\0"
  /* 2132 */ "FCR8\0"
  /* 2137 */ "HWR8\0"
  /* 2142 */ "T8\0"
  /* 2145 */ "W8\0"
  /* 2148 */ "COP09\0"
  /* 2154 */ "COP019\0"
  /* 2161 */ "COP219\0"
  /* 2168 */ "COP319\0"
  /* 2175 */ "MSA19\0"
  /* 2181 */ "F19\0"
  /* 2185 */ "F_HI19\0"
  /* 2192 */ "FCR19\0"
  /* 2198 */ "HWR19\0"
  /* 2204 */ "W19\0"
  /* 2208 */ "DSPOutFlag16_19\0"
  /* 2224 */ "COP029\0"
  /* 2231 */ "COP229\0"
  /* 2238 */ "COP329\0"
  /* 2245 */ "MSA29\0"
  /* 2251 */ "F29\0"
  /* 2255 */ "F_HI29\0"
  /* 2262 */ "COP29\0"
  /* 2268 */ "FCR29\0"
  /* 2274 */ "HWR29\0"
  /* 2280 */ "W29\0"
  /* 2284 */ "COP39\0"
  /* 2290 */ "MSA9\0"
  /* 2295 */ "D9\0"
  /* 2298 */ "F9\0"
  /* 2301 */ "F_HI9\0"
  /* 2307 */ "FCR9\0"
  /* 2312 */ "HWR9\0"
  /* 2317 */ "T9\0"
  /* 2320 */ "W9\0"
  /* 2323 */ "RA\0"
  /* 2326 */ "PC\0"
  /* 2329 */ "DSPEFI\0"
  /* 2336 */ "ZERO\0"
  /* 2341 */ "FP\0"
  /* 2344 */ "GP\0"
  /* 2347 */ "SP\0"
  /* 2350 */ "MSAIR\0"
  /* 2356 */ "MSACSR\0"
  /* 2363 */ "AT\0"
  /* 2366 */ "DSPCCond\0"
  /* 2375 */ "MSASave\0"
  /* 2383 */ "DSPOutFlag\0"
  /* 2394 */ "MSAMap\0"
  /* 2401 */ "MSAUnmap\0"
  /* 2410 */ "DSPPos\0"
  /* 2417 */ "MSAAccess\0"
  /* 2427 */ "DSPSCount\0"
  /* 2437 */ "MSARequest\0"
  /* 2448 */ "MSAModify\0"
  /* 2458 */ "DSPCarry\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc MipsRegDesc[] = { // Descriptors
  { 5, 0, 0, 0, 0, 0 },
  { 2363, 1, 176, 1, 4096, 11 },
  { 2366, 1, 1, 1, 4097, 11 },
  { 2458, 1, 1, 1, 4098, 11 },
  { 2329, 1, 1, 1, 4099, 11 },
  { 2383, 117, 1, 2, 503812, 2 },
  { 2410, 1, 1, 1, 4105, 11 },
  { 2427, 1, 1, 1, 4106, 11 },
  { 2341, 1, 190, 1, 4107, 11 },
  { 2344, 1, 192, 1, 4108, 11 },
  { 2417, 1, 1, 1, 4109, 11 },
  { 2356, 1, 1, 1, 4110, 11 },
  { 2350, 1, 1, 1, 4111, 11 },
  { 2394, 1, 1, 1, 4112, 11 },
  { 2448, 1, 1, 1, 4113, 11 },
  { 2437, 1, 1, 1, 4114, 11 },
  { 2375, 1, 1, 1, 4115, 11 },
  { 2401, 1, 1, 1, 4116, 11 },
  { 2326, 1, 1, 1, 4117, 11 },
  { 2323, 1, 194, 1, 4118, 11 },
  { 2347, 1, 196, 1, 4119, 11 },
  { 2336, 1, 198, 1, 4120, 11 },
  { 197, 1, 198, 1, 4121, 11 },
  { 455, 1, 198, 1, 4122, 11 },
  { 659, 1, 198, 1, 4123, 11 },
  { 857, 1, 198, 1, 4124, 11 },
  { 200, 68, 198, 9, 495645, 8 },
  { 458, 68, 1, 9, 495647, 8 },
  { 662, 68, 1, 9, 495649, 8 },
  { 860, 68, 1, 9, 495651, 8 },
  { 1457, 115, 1, 0, 4096, 0 },
  { 0, 1, 1, 1, 4133, 11 },
  { 258, 1, 1, 1, 4134, 11 },
  { 516, 1, 1, 1, 4135, 11 },
  { 714, 1, 1, 1, 4136, 11 },
  { 904, 1, 1, 1, 4137, 11 },
  { 1499, 1, 1, 1, 4138, 11 },
  { 1665, 1, 1, 1, 4139, 11 },
  { 1827, 1, 1, 1, 4140, 11 },
  { 1989, 1, 1, 1, 4141, 11 },
  { 2148, 1, 1, 1, 4142, 11 },
  { 102, 1, 1, 1, 4143, 11 },
  { 360, 1, 1, 1, 4144, 11 },
  { 618, 1, 1, 1, 4145, 11 },
  { 816, 1, 1, 1, 4146, 11 },
  { 1006, 1, 1, 1, 4147, 11 },
  { 1601, 1, 1, 1, 4148, 11 },
  { 1763, 1, 1, 1, 4149, 11 },
  { 1925, 1, 1, 1, 4150, 11 },
  { 2087, 1, 1, 1, 4151, 11 },
  { 2262, 1, 1, 1, 4152, 11 },
  { 175, 1, 1, 1, 4153, 11 },
  { 433, 1, 1, 1, 4154, 11 },
  { 653, 1, 1, 1, 4155, 11 },
  { 851, 1, 1, 1, 4156, 11 },
  { 1028, 1, 1, 1, 4157, 11 },
  { 1623, 1, 1, 1, 4158, 11 },
  { 1785, 1, 1, 1, 4159, 11 },
  { 1947, 1, 1, 1, 4160, 11 },
  { 2109, 1, 1, 1, 4161, 11 },
  { 2284, 1, 1, 1, 4162, 11 },
  { 6, 1, 1, 1, 4163, 11 },
  { 264, 1, 1, 1, 4164, 11 },
  { 522, 1, 1, 1, 4165, 11 },
  { 720, 1, 1, 1, 4166, 11 },
  { 910, 1, 1, 1, 4167, 11 },
  { 1505, 1, 1, 1, 4168, 11 },
  { 1671, 1, 1, 1, 4169, 11 },
  { 1833, 1, 1, 1, 4170, 11 },
  { 1995, 1, 1, 1, 4171, 11 },
  { 2154, 1, 1, 1, 4172, 11 },
  { 64, 1, 1, 1, 4173, 11 },
  { 322, 1, 1, 1, 4174, 11 },
  { 580, 1, 1, 1, 4175, 11 },
  { 778, 1, 1, 1, 4176, 11 },
  { 968, 1, 1, 1, 4177, 11 },
  { 1563, 1, 1, 1, 4178, 11 },
  { 1725, 1, 1, 1, 4179, 11 },
  { 1887, 1, 1, 1, 4180, 11 },
  { 2049, 1, 1, 1, 4181, 11 },
  { 2224, 1, 1, 1, 4182, 11 },
  { 137, 1, 1, 1, 4183, 11 },
  { 395, 1, 1, 1, 4184, 11 },
  { 13, 1, 1, 1, 4185, 11 },
  { 271, 1, 1, 1, 4186, 11 },
  { 529, 1, 1, 1, 4187, 11 },
  { 727, 1, 1, 1, 4188, 11 },
  { 917, 1, 1, 1, 4189, 11 },
  { 1512, 1, 1, 1, 4190, 11 },
  { 1678, 1, 1, 1, 4191, 11 },
  { 1840, 1, 1, 1, 4192, 11 },
  { 2002, 1, 1, 1, 4193, 11 },
  { 2161, 1, 1, 1, 4194, 11 },
  { 71, 1, 1, 1, 4195, 11 },
  { 329, 1, 1, 1, 4196, 11 },
  { 587, 1, 1, 1, 4197, 11 },
  { 785, 1, 1, 1, 4198, 11 },
  { 975, 1, 1, 1, 4199, 11 },
  { 1570, 1, 1, 1, 4200, 11 },
  { 1732, 1, 1, 1, 4201, 11 },
  { 1894, 1, 1, 1, 4202, 11 },
  { 2056, 1, 1, 1, 4203, 11 },
  { 2231, 1, 1, 1, 4204, 11 },
  { 144, 1, 1, 1, 4205, 11 },
  { 402, 1, 1, 1, 4206, 11 },
  { 20, 1, 1, 1, 4207, 11 },
  { 278, 1, 1, 1, 4208, 11 },
  { 536, 1, 1, 1, 4209, 11 },
  { 734, 1, 1, 1, 4210, 11 },
  { 924, 1, 1, 1, 4211, 11 },
  { 1519, 1, 1, 1, 4212, 11 },
  { 1685, 1, 1, 1, 4213, 11 },
  { 1847, 1, 1, 1, 4214, 11 },
  { 2009, 1, 1, 1, 4215, 11 },
  { 2168, 1, 1, 1, 4216, 11 },
  { 78, 1, 1, 1, 4217, 11 },
  { 336, 1, 1, 1, 4218, 11 },
  { 594, 1, 1, 1, 4219, 11 },
  { 792, 1, 1, 1, 4220, 11 },
  { 982, 1, 1, 1, 4221, 11 },
  { 1577, 1, 1, 1, 4222, 11 },
  { 1739, 1, 1, 1, 4223, 11 },
  { 1901, 1, 1, 1, 4224, 11 },
  { 2063, 1, 1, 1, 4225, 11 },
  { 2238, 1, 1, 1, 4226, 11 },
  { 151, 1, 1, 1, 4227, 11 },
  { 409, 1, 1, 1, 4228, 11 },
  { 209, 128, 1, 9, 495749, 8 },
  { 467, 131, 1, 9, 495751, 8 },
  { 671, 134, 1, 9, 495753, 8 },
  { 869, 137, 1, 9, 495755, 8 },
  { 1468, 140, 1, 9, 495757, 8 },
  { 1634, 143, 1, 9, 495759, 8 },
  { 1796, 146, 1, 9, 495761, 8 },
  { 1958, 149, 1, 9, 495763, 8 },
  { 2120, 152, 1, 9, 495765, 8 },
  { 2295, 155, 1, 9, 495767, 8 },
  { 33, 158, 1, 9, 495769, 8 },
  { 291, 161, 1, 9, 495771, 8 },
  { 549, 164, 1, 9, 495773, 8 },
  { 747, 167, 1, 9, 495775, 8 },
  { 937, 170, 1, 9, 495777, 8 },
  { 1532, 173, 1, 9, 495779, 8 },
  { 124, 1, 28, 1, 4101, 11 },
  { 382, 1, 26, 1, 4102, 11 },
  { 640, 1, 24, 1, 4103, 11 },
  { 838, 1, 22, 1, 4104, 11 },
  { 212, 1, 39, 1, 4229, 11 },
  { 470, 1, 43, 1, 4230, 11 },
  { 674, 1, 43, 1, 4231, 11 },
  { 872, 1, 47, 1, 4232, 11 },
  { 1471, 1, 47, 1, 4233, 11 },
  { 1637, 1, 51, 1, 4234, 11 },
  { 1799, 1, 51, 1, 4235, 11 },
  { 1961, 1, 55, 1, 4236, 11 },
  { 2123, 1, 55, 1, 4237, 11 },
  { 2298, 1, 59, 1, 4238, 11 },
  { 37, 1, 59, 1, 4239, 11 },
  { 295, 1, 63, 1, 4240, 11 },
  { 553, 1, 63, 1, 4241, 11 },
  { 751, 1, 67, 1, 4242, 11 },
  { 941, 1, 67, 1, 4243, 11 },
  { 1536, 1, 71, 1, 4244, 11 },
  { 1698, 1, 71, 1, 4245, 11 },
  { 1860, 1, 75, 1, 4246, 11 },
  { 2022, 1, 75, 1, 4247, 11 },
  { 2181, 1, 79, 1, 4248, 11 },
  { 91, 1, 79, 1, 4249, 11 },
  { 349, 1, 83, 1, 4250, 11 },
  { 607, 1, 83, 1, 4251, 11 },
  { 805, 1, 87, 1, 4252, 11 },
  { 995, 1, 87, 1, 4253, 11 },
  { 1590, 1, 91, 1, 4254, 11 },
  { 1752, 1, 91, 1, 4255, 11 },
  { 1914, 1, 95, 1, 4256, 11 },
  { 2076, 1, 95, 1, 4257, 11 },
  { 2251, 1, 99, 1, 4258, 11 },
  { 164, 1, 99, 1, 4259, 11 },
  { 422, 1, 103, 1, 4260, 11 },
  { 204, 1, 1, 1, 4261, 11 },
  { 462, 1, 1, 1, 4262, 11 },
  { 666, 1, 1, 1, 4263, 11 },
  { 864, 1, 1, 1, 4264, 11 },
  { 1463, 1, 1, 1, 4265, 11 },
  { 1629, 1, 1, 1, 4266, 11 },
  { 1791, 1, 1, 1, 4267, 11 },
  { 1953, 1, 1, 1, 4268, 11 },
  { 236, 1, 1, 1, 4269, 11 },
  { 494, 1, 1, 1, 4270, 11 },
  { 695, 1, 1, 1, 4271, 11 },
  { 885, 1, 1, 1, 4272, 11 },
  { 1480, 1, 1, 1, 4273, 11 },
  { 1646, 1, 1, 1, 4274, 11 },
  { 1808, 1, 1, 1, 4275, 11 },
  { 1970, 1, 1, 1, 4276, 11 },
  { 2132, 1, 1, 1, 4277, 11 },
  { 2307, 1, 1, 1, 4278, 11 },
  { 48, 1, 1, 1, 4279, 11 },
  { 306, 1, 1, 1, 4280, 11 },
  { 564, 1, 1, 1, 4281, 11 },
  { 762, 1, 1, 1, 4282, 11 },
  { 952, 1, 1, 1, 4283, 11 },
  { 1547, 1, 1, 1, 4284, 11 },
  { 1709, 1, 1, 1, 4285, 11 },
  { 1871, 1, 1, 1, 4286, 11 },
  { 2033, 1, 1, 1, 4287, 11 },
  { 2192, 1, 1, 1, 4288, 11 },
  { 108, 1, 1, 1, 4289, 11 },
  { 366, 1, 1, 1, 4290, 11 },
  { 624, 1, 1, 1, 4291, 11 },
  { 822, 1, 1, 1, 4292, 11 },
  { 1012, 1, 1, 1, 4293, 11 },
  { 1607, 1, 1, 1, 4294, 11 },
  { 1769, 1, 1, 1, 4295, 11 },
  { 1931, 1, 1, 1, 4296, 11 },
  { 2093, 1, 1, 1, 4297, 11 },
  { 2268, 1, 1, 1, 4298, 11 },
  { 181, 1, 1, 1, 4299, 11 },
  { 439, 1, 1, 1, 4300, 11 },
  { 1439, 18, 1, 0, 4107, 0 },
  { 215, 1, 36, 1, 4301, 11 },
  { 473, 1, 36, 1, 4302, 11 },
  { 677, 1, 36, 1, 4303, 11 },
  { 875, 1, 36, 1, 4304, 11 },
  { 1474, 1, 36, 1, 4305, 11 },
  { 1640, 1, 36, 1, 4306, 11 },
  { 1802, 1, 36, 1, 4307, 11 },
  { 1964, 1, 36, 1, 4308, 11 },
  { 2126, 1, 36, 1, 4309, 11 },
  { 2301, 1, 36, 1, 4310, 11 },
  { 41, 1, 36, 1, 4311, 11 },
  { 299, 1, 36, 1, 4312, 11 },
  { 557, 1, 36, 1, 4313, 11 },
  { 755, 1, 36, 1, 4314, 11 },
  { 945, 1, 36, 1, 4315, 11 },
  { 1540, 1, 36, 1, 4316, 11 },
  { 1702, 1, 36, 1, 4317, 11 },
  { 1864, 1, 36, 1, 4318, 11 },
  { 2026, 1, 36, 1, 4319, 11 },
  { 2185, 1, 36, 1, 4320, 11 },
  { 95, 1, 36, 1, 4321, 11 },
  { 353, 1, 36, 1, 4322, 11 },
  { 611, 1, 36, 1, 4323, 11 },
  { 809, 1, 36, 1, 4324, 11 },
  { 999, 1, 36, 1, 4325, 11 },
  { 1594, 1, 36, 1, 4326, 11 },
  { 1756, 1, 36, 1, 4327, 11 },
  { 1918, 1, 36, 1, 4328, 11 },
  { 2080, 1, 36, 1, 4329, 11 },
  { 2255, 1, 36, 1, 4330, 11 },
  { 168, 1, 36, 1, 4331, 11 },
  { 426, 1, 36, 1, 4332, 11 },
  { 1445, 10, 1, 0, 4108, 0 },
  { 217, 1, 111, 1, 4126, 11 },
  { 475, 1, 16, 1, 4128, 11 },
  { 679, 1, 16, 1, 4130, 11 },
  { 877, 1, 16, 1, 4132, 11 },
  { 241, 1, 1, 1, 4333, 11 },
  { 499, 1, 1, 1, 4334, 11 },
  { 700, 1, 1, 1, 4335, 11 },
  { 890, 1, 1, 1, 4336, 11 },
  { 1485, 1, 1, 1, 4337, 11 },
  { 1651, 1, 1, 1, 4338, 11 },
  { 1813, 1, 1, 1, 4339, 11 },
  { 1975, 1, 1, 1, 4340, 11 },
  { 2137, 1, 1, 1, 4341, 11 },
  { 2312, 1, 1, 1, 4342, 11 },
  { 54, 1, 1, 1, 4343, 11 },
  { 312, 1, 1, 1, 4344, 11 },
  { 570, 1, 1, 1, 4345, 11 },
  { 768, 1, 1, 1, 4346, 11 },
  { 958, 1, 1, 1, 4347, 11 },
  { 1553, 1, 1, 1, 4348, 11 },
  { 1715, 1, 1, 1, 4349, 11 },
  { 1877, 1, 1, 1, 4350, 11 },
  { 2039, 1, 1, 1, 4351, 11 },
  { 2198, 1, 1, 1, 4352, 11 },
  { 114, 1, 1, 1, 4353, 11 },
  { 372, 1, 1, 1, 4354, 11 },
  { 630, 1, 1, 1, 4355, 11 },
  { 828, 1, 1, 1, 4356, 11 },
  { 1018, 1, 1, 1, 4357, 11 },
  { 1613, 1, 1, 1, 4358, 11 },
  { 1775, 1, 1, 1, 4359, 11 },
  { 1937, 1, 1, 1, 4360, 11 },
  { 2099, 1, 1, 1, 4361, 11 },
  { 2274, 1, 1, 1, 4362, 11 },
  { 187, 1, 1, 1, 4363, 11 },
  { 445, 1, 1, 1, 4364, 11 },
  { 221, 1, 188, 1, 4365, 11 },
  { 479, 1, 188, 1, 4366, 11 },
  { 229, 1, 107, 1, 4125, 11 },
  { 487, 1, 8, 1, 4127, 11 },
  { 688, 1, 8, 1, 4129, 11 },
  { 881, 1, 8, 1, 4131, 11 },
  { 224, 1, 1, 1, 4367, 11 },
  { 482, 1, 1, 1, 4368, 11 },
  { 683, 1, 1, 1, 4369, 11 },
  { 2115, 1, 1, 1, 4370, 11 },
  { 2290, 1, 1, 1, 4371, 11 },
  { 27, 1, 1, 1, 4372, 11 },
  { 285, 1, 1, 1, 4373, 11 },
  { 543, 1, 1, 1, 4374, 11 },
  { 741, 1, 1, 1, 4375, 11 },
  { 931, 1, 1, 1, 4376, 11 },
  { 1526, 1, 1, 1, 4377, 11 },
  { 1692, 1, 1, 1, 4378, 11 },
  { 1854, 1, 1, 1, 4379, 11 },
  { 2016, 1, 1, 1, 4380, 11 },
  { 2175, 1, 1, 1, 4381, 11 },
  { 85, 1, 1, 1, 4382, 11 },
  { 343, 1, 1, 1, 4383, 11 },
  { 601, 1, 1, 1, 4384, 11 },
  { 799, 1, 1, 1, 4385, 11 },
  { 989, 1, 1, 1, 4386, 11 },
  { 1584, 1, 1, 1, 4387, 11 },
  { 1746, 1, 1, 1, 4388, 11 },
  { 1908, 1, 1, 1, 4389, 11 },
  { 2070, 1, 1, 1, 4390, 11 },
  { 2245, 1, 1, 1, 4391, 11 },
  { 158, 1, 1, 1, 4392, 11 },
  { 416, 1, 1, 1, 4393, 11 },
  { 233, 1, 1, 1, 4394, 11 },
  { 491, 1, 1, 1, 4395, 11 },
  { 692, 1, 1, 1, 4396, 11 },
  { 1425, 6, 1, 0, 4118, 0 },
  { 246, 1, 186, 1, 4397, 11 },
  { 504, 1, 186, 1, 4398, 11 },
  { 705, 1, 186, 1, 4399, 11 },
  { 895, 1, 186, 1, 4400, 11 },
  { 1490, 1, 186, 1, 4401, 11 },
  { 1656, 1, 186, 1, 4402, 11 },
  { 1818, 1, 186, 1, 4403, 11 },
  { 1980, 1, 186, 1, 4404, 11 },
  { 1451, 4, 1, 0, 4119, 0 },
  { 249, 1, 184, 1, 4405, 11 },
  { 507, 1, 184, 1, 4406, 11 },
  { 708, 1, 184, 1, 4407, 11 },
  { 898, 1, 184, 1, 4408, 11 },
  { 1493, 1, 184, 1, 4409, 11 },
  { 1659, 1, 184, 1, 4410, 11 },
  { 1821, 1, 184, 1, 4411, 11 },
  { 1983, 1, 184, 1, 4412, 11 },
  { 2142, 1, 184, 1, 4413, 11 },
  { 2317, 1, 184, 1, 4414, 11 },
  { 252, 1, 184, 1, 4415, 11 },
  { 510, 1, 184, 1, 4416, 11 },
  { 255, 180, 1, 8, 729221, 8 },
  { 513, 180, 1, 8, 729222, 8 },
  { 711, 180, 1, 8, 729223, 8 },
  { 901, 180, 1, 8, 729224, 8 },
  { 1496, 180, 1, 8, 729225, 8 },
  { 1662, 180, 1, 8, 729226, 8 },
  { 1824, 180, 1, 8, 729227, 8 },
  { 1986, 180, 1, 8, 729228, 8 },
  { 2145, 180, 1, 8, 729229, 8 },
  { 2320, 180, 1, 8, 729230, 8 },
  { 60, 180, 1, 8, 729231, 8 },
  { 318, 180, 1, 8, 729232, 8 },
  { 576, 180, 1, 8, 729233, 8 },
  { 774, 180, 1, 8, 729234, 8 },
  { 964, 180, 1, 8, 729235, 8 },
  { 1559, 180, 1, 8, 729236, 8 },
  { 1721, 180, 1, 8, 729237, 8 },
  { 1883, 180, 1, 8, 729238, 8 },
  { 2045, 180, 1, 8, 729239, 8 },
  { 2204, 180, 1, 8, 729240, 8 },
  { 120, 180, 1, 8, 729241, 8 },
  { 378, 180, 1, 8, 729242, 8 },
  { 636, 180, 1, 8, 729243, 8 },
  { 834, 180, 1, 8, 729244, 8 },
  { 1024, 180, 1, 8, 729245, 8 },
  { 1619, 180, 1, 8, 729246, 8 },
  { 1781, 180, 1, 8, 729247, 8 },
  { 1943, 180, 1, 8, 729248, 8 },
  { 2105, 180, 1, 8, 729249, 8 },
  { 2280, 180, 1, 8, 729250, 8 },
  { 193, 180, 1, 8, 729251, 8 },
  { 451, 180, 1, 8, 729252, 8 },
  { 1431, 2, 1, 0, 4120, 0 },
  { 1055, 2, 1, 0, 4121, 0 },
  { 1133, 2, 1, 0, 4122, 0 },
  { 1183, 2, 1, 0, 4123, 0 },
  { 1221, 2, 1, 0, 4124, 0 },
  { 1061, 12, 1, 12, 495645, 8 },
  { 1068, 181, 37, 9, 729221, 8 },
  { 1139, 181, 37, 9, 729222, 8 },
  { 1189, 181, 37, 9, 729223, 8 },
  { 1227, 181, 37, 9, 729224, 8 },
  { 1259, 181, 37, 9, 729225, 8 },
  { 1291, 181, 37, 9, 729226, 8 },
  { 1323, 181, 37, 9, 729227, 8 },
  { 1355, 181, 37, 9, 729228, 8 },
  { 1387, 181, 37, 9, 729229, 8 },
  { 1413, 181, 37, 9, 729230, 8 },
  { 1034, 181, 37, 9, 729231, 8 },
  { 1112, 181, 37, 9, 729232, 8 },
  { 1169, 181, 37, 9, 729233, 8 },
  { 1207, 181, 37, 9, 729234, 8 },
  { 1245, 181, 37, 9, 729235, 8 },
  { 1277, 181, 37, 9, 729236, 8 },
  { 1309, 181, 37, 9, 729237, 8 },
  { 1341, 181, 37, 9, 729238, 8 },
  { 1373, 181, 37, 9, 729239, 8 },
  { 1399, 181, 37, 9, 729240, 8 },
  { 1041, 181, 37, 9, 729241, 8 },
  { 1119, 181, 37, 9, 729242, 8 },
  { 1176, 181, 37, 9, 729243, 8 },
  { 1214, 181, 37, 9, 729244, 8 },
  { 1252, 181, 37, 9, 729245, 8 },
  { 1284, 181, 37, 9, 729246, 8 },
  { 1316, 181, 37, 9, 729247, 8 },
  { 1348, 181, 37, 9, 729248, 8 },
  { 1380, 181, 37, 9, 729249, 8 },
  { 1406, 181, 37, 9, 729250, 8 },
  { 1048, 181, 37, 9, 729251, 8 },
  { 1126, 181, 37, 9, 729252, 8 },
  { 2208, 1, 0, 1, 4100, 11 },
  { 1074, 20, 113, 0, 4126, 0 },
  { 1081, 30, 1, 0, 4365, 0 },
  { 1145, 30, 1, 0, 4366, 0 },
  { 1087, 30, 109, 0, 4125, 0 },
  { 1094, 32, 1, 0, 4397, 0 },
  { 1151, 32, 1, 0, 4398, 0 },
  { 1195, 32, 1, 0, 4399, 0 },
  { 1233, 32, 1, 0, 4400, 0 },
  { 1265, 32, 1, 0, 4401, 0 },
  { 1297, 32, 1, 0, 4402, 0 },
  { 1329, 32, 1, 0, 4403, 0 },
  { 1361, 32, 1, 0, 4404, 0 },
  { 1100, 34, 1, 0, 4405, 0 },
  { 1157, 34, 1, 0, 4406, 0 },
  { 1201, 34, 1, 0, 4407, 0 },
  { 1239, 34, 1, 0, 4408, 0 },
  { 1271, 34, 1, 0, 4409, 0 },
  { 1303, 34, 1, 0, 4410, 0 },
  { 1335, 34, 1, 0, 4411, 0 },
  { 1367, 34, 1, 0, 4412, 0 },
  { 1393, 34, 1, 0, 4413, 0 },
  { 1419, 34, 1, 0, 4414, 0 },
  { 1106, 34, 1, 0, 4415, 0 },
  { 1163, 34, 1, 0, 4416, 0 },
};

extern const MCPhysReg MipsRegUnitRoots[][2] = {
  { Mips::AT },
  { Mips::DSPCCond },
  { Mips::DSPCarry },
  { Mips::DSPEFI },
  { Mips::DSPOutFlag16_19 },
  { Mips::DSPOutFlag20 },
  { Mips::DSPOutFlag21 },
  { Mips::DSPOutFlag22 },
  { Mips::DSPOutFlag23 },
  { Mips::DSPPos },
  { Mips::DSPSCount },
  { Mips::FP },
  { Mips::GP },
  { Mips::MSAAccess },
  { Mips::MSACSR },
  { Mips::MSAIR },
  { Mips::MSAMap },
  { Mips::MSAModify },
  { Mips::MSARequest },
  { Mips::MSASave },
  { Mips::MSAUnmap },
  { Mips::PC },
  { Mips::RA },
  { Mips::SP },
  { Mips::ZERO },
  { Mips::A0 },
  { Mips::A1 },
  { Mips::A2 },
  { Mips::A3 },
  { Mips::LO0 },
  { Mips::HI0 },
  { Mips::LO1 },
  { Mips::HI1 },
  { Mips::LO2 },
  { Mips::HI2 },
  { Mips::LO3 },
  { Mips::HI3 },
  { Mips::COP00 },
  { Mips::COP01 },
  { Mips::COP02 },
  { Mips::COP03 },
  { Mips::COP04 },
  { Mips::COP05 },
  { Mips::COP06 },
  { Mips::COP07 },
  { Mips::COP08 },
  { Mips::COP09 },
  { Mips::COP20 },
  { Mips::COP21 },
  { Mips::COP22 },
  { Mips::COP23 },
  { Mips::COP24 },
  { Mips::COP25 },
  { Mips::COP26 },
  { Mips::COP27 },
  { Mips::COP28 },
  { Mips::COP29 },
  { Mips::COP30 },
  { Mips::COP31 },
  { Mips::COP32 },
  { Mips::COP33 },
  { Mips::COP34 },
  { Mips::COP35 },
  { Mips::COP36 },
  { Mips::COP37 },
  { Mips::COP38 },
  { Mips::COP39 },
  { Mips::COP010 },
  { Mips::COP011 },
  { Mips::COP012 },
  { Mips::COP013 },
  { Mips::COP014 },
  { Mips::COP015 },
  { Mips::COP016 },
  { Mips::COP017 },
  { Mips::COP018 },
  { Mips::COP019 },
  { Mips::COP020 },
  { Mips::COP021 },
  { Mips::COP022 },
  { Mips::COP023 },
  { Mips::COP024 },
  { Mips::COP025 },
  { Mips::COP026 },
  { Mips::COP027 },
  { Mips::COP028 },
  { Mips::COP029 },
  { Mips::COP030 },
  { Mips::COP031 },
  { Mips::COP210 },
  { Mips::COP211 },
  { Mips::COP212 },
  { Mips::COP213 },
  { Mips::COP214 },
  { Mips::COP215 },
  { Mips::COP216 },
  { Mips::COP217 },
  { Mips::COP218 },
  { Mips::COP219 },
  { Mips::COP220 },
  { Mips::COP221 },
  { Mips::COP222 },
  { Mips::COP223 },
  { Mips::COP224 },
  { Mips::COP225 },
  { Mips::COP226 },
  { Mips::COP227 },
  { Mips::COP228 },
  { Mips::COP229 },
  { Mips::COP230 },
  { Mips::COP231 },
  { Mips::COP310 },
  { Mips::COP311 },
  { Mips::COP312 },
  { Mips::COP313 },
  { Mips::COP314 },
  { Mips::COP315 },
  { Mips::COP316 },
  { Mips::COP317 },
  { Mips::COP318 },
  { Mips::COP319 },
  { Mips::COP320 },
  { Mips::COP321 },
  { Mips::COP322 },
  { Mips::COP323 },
  { Mips::COP324 },
  { Mips::COP325 },
  { Mips::COP326 },
  { Mips::COP327 },
  { Mips::COP328 },
  { Mips::COP329 },
  { Mips::COP330 },
  { Mips::COP331 },
  { Mips::F0 },
  { Mips::F1 },
  { Mips::F2 },
  { Mips::F3 },
  { Mips::F4 },
  { Mips::F5 },
  { Mips::F6 },
  { Mips::F7 },
  { Mips::F8 },
  { Mips::F9 },
  { Mips::F10 },
  { Mips::F11 },
  { Mips::F12 },
  { Mips::F13 },
  { Mips::F14 },
  { Mips::F15 },
  { Mips::F16 },
  { Mips::F17 },
  { Mips::F18 },
  { Mips::F19 },
  { Mips::F20 },
  { Mips::F21 },
  { Mips::F22 },
  { Mips::F23 },
  { Mips::F24 },
  { Mips::F25 },
  { Mips::F26 },
  { Mips::F27 },
  { Mips::F28 },
  { Mips::F29 },
  { Mips::F30 },
  { Mips::F31 },
  { Mips::FCC0 },
  { Mips::FCC1 },
  { Mips::FCC2 },
  { Mips::FCC3 },
  { Mips::FCC4 },
  { Mips::FCC5 },
  { Mips::FCC6 },
  { Mips::FCC7 },
  { Mips::FCR0 },
  { Mips::FCR1 },
  { Mips::FCR2 },
  { Mips::FCR3 },
  { Mips::FCR4 },
  { Mips::FCR5 },
  { Mips::FCR6 },
  { Mips::FCR7 },
  { Mips::FCR8 },
  { Mips::FCR9 },
  { Mips::FCR10 },
  { Mips::FCR11 },
  { Mips::FCR12 },
  { Mips::FCR13 },
  { Mips::FCR14 },
  { Mips::FCR15 },
  { Mips::FCR16 },
  { Mips::FCR17 },
  { Mips::FCR18 },
  { Mips::FCR19 },
  { Mips::FCR20 },
  { Mips::FCR21 },
  { Mips::FCR22 },
  { Mips::FCR23 },
  { Mips::FCR24 },
  { Mips::FCR25 },
  { Mips::FCR26 },
  { Mips::FCR27 },
  { Mips::FCR28 },
  { Mips::FCR29 },
  { Mips::FCR30 },
  { Mips::FCR31 },
  { Mips::F_HI0 },
  { Mips::F_HI1 },
  { Mips::F_HI2 },
  { Mips::F_HI3 },
  { Mips::F_HI4 },
  { Mips::F_HI5 },
  { Mips::F_HI6 },
  { Mips::F_HI7 },
  { Mips::F_HI8 },
  { Mips::F_HI9 },
  { Mips::F_HI10 },
  { Mips::F_HI11 },
  { Mips::F_HI12 },
  { Mips::F_HI13 },
  { Mips::F_HI14 },
  { Mips::F_HI15 },
  { Mips::F_HI16 },
  { Mips::F_HI17 },
  { Mips::F_HI18 },
  { Mips::F_HI19 },
  { Mips::F_HI20 },
  { Mips::F_HI21 },
  { Mips::F_HI22 },
  { Mips::F_HI23 },
  { Mips::F_HI24 },
  { Mips::F_HI25 },
  { Mips::F_HI26 },
  { Mips::F_HI27 },
  { Mips::F_HI28 },
  { Mips::F_HI29 },
  { Mips::F_HI30 },
  { Mips::F_HI31 },
  { Mips::HWR0 },
  { Mips::HWR1 },
  { Mips::HWR2 },
  { Mips::HWR3 },
  { Mips::HWR4 },
  { Mips::HWR5 },
  { Mips::HWR6 },
  { Mips::HWR7 },
  { Mips::HWR8 },
  { Mips::HWR9 },
  { Mips::HWR10 },
  { Mips::HWR11 },
  { Mips::HWR12 },
  { Mips::HWR13 },
  { Mips::HWR14 },
  { Mips::HWR15 },
  { Mips::HWR16 },
  { Mips::HWR17 },
  { Mips::HWR18 },
  { Mips::HWR19 },
  { Mips::HWR20 },
  { Mips::HWR21 },
  { Mips::HWR22 },
  { Mips::HWR23 },
  { Mips::HWR24 },
  { Mips::HWR25 },
  { Mips::HWR26 },
  { Mips::HWR27 },
  { Mips::HWR28 },
  { Mips::HWR29 },
  { Mips::HWR30 },
  { Mips::HWR31 },
  { Mips::K0 },
  { Mips::K1 },
  { Mips::MPL0 },
  { Mips::MPL1 },
  { Mips::MPL2 },
  { Mips::MSA8 },
  { Mips::MSA9 },
  { Mips::MSA10 },
  { Mips::MSA11 },
  { Mips::MSA12 },
  { Mips::MSA13 },
  { Mips::MSA14 },
  { Mips::MSA15 },
  { Mips::MSA16 },
  { Mips::MSA17 },
  { Mips::MSA18 },
  { Mips::MSA19 },
  { Mips::MSA20 },
  { Mips::MSA21 },
  { Mips::MSA22 },
  { Mips::MSA23 },
  { Mips::MSA24 },
  { Mips::MSA25 },
  { Mips::MSA26 },
  { Mips::MSA27 },
  { Mips::MSA28 },
  { Mips::MSA29 },
  { Mips::MSA30 },
  { Mips::MSA31 },
  { Mips::P0 },
  { Mips::P1 },
  { Mips::P2 },
  { Mips::S0 },
  { Mips::S1 },
  { Mips::S2 },
  { Mips::S3 },
  { Mips::S4 },
  { Mips::S5 },
  { Mips::S6 },
  { Mips::S7 },
  { Mips::T0 },
  { Mips::T1 },
  { Mips::T2 },
  { Mips::T3 },
  { Mips::T4 },
  { Mips::T5 },
  { Mips::T6 },
  { Mips::T7 },
  { Mips::T8 },
  { Mips::T9 },
  { Mips::V0 },
  { Mips::V1 },
};

namespace {     // Register classes...
  // MSA128F16 Register Class...
  const MCPhysReg MSA128F16[] = {
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
  };

  // MSA128F16 Bit set.
  const uint8_t MSA128F16Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    Mips::FCR0, Mips::FCR1, Mips::FCR2, Mips::FCR3, Mips::FCR4, Mips::FCR5, Mips::FCR6, Mips::FCR7, Mips::FCR8, Mips::FCR9, Mips::FCR10, Mips::FCR11, Mips::FCR12, Mips::FCR13, Mips::FCR14, Mips::FCR15, Mips::FCR16, Mips::FCR17, Mips::FCR18, Mips::FCR19, Mips::FCR20, Mips::FCR21, Mips::FCR22, Mips::FCR23, Mips::FCR24, Mips::FCR25, Mips::FCR26, Mips::FCR27, Mips::FCR28, Mips::FCR29, Mips::FCR30, Mips::FCR31, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // COP0 Register Class...
  const MCPhysReg COP0[] = {
    Mips::COP00, Mips::COP01, Mips::COP02, Mips::COP03, Mips::COP04, Mips::COP05, Mips::COP06, Mips::COP07, Mips::COP08, Mips::COP09, Mips::COP010, Mips::COP011, Mips::COP012, Mips::COP013, Mips::COP014, Mips::COP015, Mips::COP016, Mips::COP017, Mips::COP018, Mips::COP019, Mips::COP020, Mips::COP021, Mips::COP022, Mips::COP023, Mips::COP024, Mips::COP025, Mips::COP026, Mips::COP027, Mips::COP028, Mips::COP029, Mips::COP030, Mips::COP031, 
  };

  // COP0 Bit set.
  const uint8_t COP0Bits[] = {
    0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0x00, 0xe0, 0xff, 0xff, 0x07, 
  };

  // COP2 Register Class...
  const MCPhysReg COP2[] = {
    Mips::COP20, Mips::COP21, Mips::COP22, Mips::COP23, Mips::COP24, Mips::COP25, Mips::COP26, Mips::COP27, Mips::COP28, Mips::COP29, Mips::COP210, Mips::COP211, Mips::COP212, Mips::COP213, Mips::COP214, Mips::COP215, Mips::COP216, Mips::COP217, Mips::COP218, Mips::COP219, Mips::COP220, Mips::COP221, Mips::COP222, Mips::COP223, Mips::COP224, Mips::COP225, Mips::COP226, Mips::COP227, Mips::COP228, Mips::COP229, Mips::COP230, Mips::COP231, 
  };

  // COP2 Bit set.
  const uint8_t COP2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0x01, 
  };

  // COP3 Register Class...
  const MCPhysReg COP3[] = {
    Mips::COP30, Mips::COP31, Mips::COP32, Mips::COP33, Mips::COP34, Mips::COP35, Mips::COP36, Mips::COP37, Mips::COP38, Mips::COP39, Mips::COP310, Mips::COP311, Mips::COP312, Mips::COP313, Mips::COP314, Mips::COP315, Mips::COP316, Mips::COP317, Mips::COP318, Mips::COP319, Mips::COP320, Mips::COP321, Mips::COP322, Mips::COP323, Mips::COP324, Mips::COP325, Mips::COP326, Mips::COP327, Mips::COP328, Mips::COP329, Mips::COP330, Mips::COP331, 
  };

  // COP3 Bit set.
  const uint8_t COP3Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x7f, 
  };

  // DSPR Register Class...
  const MCPhysReg DSPR[] = {
    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 
  };

  // DSPR Bit set.
  const uint8_t DSPRBits[] = {
    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, 
  };

  // FGR32 Register Class...
  const MCPhysReg FGR32[] = {
    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, 
  };

  // FGR32 Bit set.
  const uint8_t FGR32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // FGRCC Register Class...
  const MCPhysReg FGRCC[] = {
    Mips::F0, Mips::F1, Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, Mips::F12, Mips::F13, Mips::F14, Mips::F15, Mips::F16, Mips::F17, Mips::F18, Mips::F19, Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, Mips::F30, Mips::F31, 
  };

  // FGRCC Bit set.
  const uint8_t FGRCCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // GPR32 Register Class...
  const MCPhysReg GPR32[] = {
    Mips::ZERO, Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 
  };

  // GPR32 Bit set.
  const uint8_t GPR32Bits[] = {
    0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, 
  };

  // HWRegs Register Class...
  const MCPhysReg HWRegs[] = {
    Mips::HWR0, Mips::HWR1, Mips::HWR2, Mips::HWR3, Mips::HWR4, Mips::HWR5, Mips::HWR6, Mips::HWR7, Mips::HWR8, Mips::HWR9, Mips::HWR10, Mips::HWR11, Mips::HWR12, Mips::HWR13, Mips::HWR14, Mips::HWR15, Mips::HWR16, Mips::HWR17, Mips::HWR18, Mips::HWR19, Mips::HWR20, Mips::HWR21, Mips::HWR22, Mips::HWR23, Mips::HWR24, Mips::HWR25, Mips::HWR26, Mips::HWR27, Mips::HWR28, Mips::HWR29, Mips::HWR30, Mips::HWR31, 
  };

  // HWRegs Bit set.
  const uint8_t HWRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // MSACtrl Register Class...
  const MCPhysReg MSACtrl[] = {
    Mips::MSAIR, Mips::MSACSR, Mips::MSAAccess, Mips::MSASave, Mips::MSAModify, Mips::MSARequest, Mips::MSAMap, Mips::MSAUnmap, Mips::MSA8, Mips::MSA9, Mips::MSA10, Mips::MSA11, Mips::MSA12, Mips::MSA13, Mips::MSA14, Mips::MSA15, Mips::MSA16, Mips::MSA17, Mips::MSA18, Mips::MSA19, Mips::MSA20, Mips::MSA21, Mips::MSA22, Mips::MSA23, Mips::MSA24, Mips::MSA25, Mips::MSA26, Mips::MSA27, Mips::MSA28, Mips::MSA29, Mips::MSA30, Mips::MSA31, 
  };

  // MSACtrl Bit set.
  const uint8_t MSACtrlBits[] = {
    0x00, 0xfc, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03, 
  };

  // GPR32NONZERO Register Class...
  const MCPhysReg GPR32NONZERO[] = {
    Mips::AT, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::T0, Mips::T1, Mips::T2, Mips::T3, Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, Mips::T8, Mips::T9, Mips::K0, Mips::K1, Mips::GP, Mips::SP, Mips::FP, Mips::RA, 
  };

  // GPR32NONZERO Bit set.
  const uint8_t GPR32NONZEROBits[] = {
    0x02, 0x03, 0xd8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc0, 0xbf, 0xff, 0x07, 
  };

  // CPU16RegsPlusSP Register Class...
  const MCPhysReg CPU16RegsPlusSP[] = {
    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, Mips::SP, 
  };

  // CPU16RegsPlusSP Bit set.
  const uint8_t CPU16RegsPlusSPBits[] = {
    0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
  };

  // CPU16Regs Register Class...
  const MCPhysReg CPU16Regs[] = {
    Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, Mips::S0, Mips::S1, 
  };

  // CPU16Regs Bit set.
  const uint8_t CPU16RegsBits[] = {
    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
  };

  // FCC Register Class...
  const MCPhysReg FCC[] = {
    Mips::FCC0, Mips::FCC1, Mips::FCC2, Mips::FCC3, Mips::FCC4, Mips::FCC5, Mips::FCC6, Mips::FCC7, 
  };

  // FCC Bit set.
  const uint8_t FCCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // GPRMM16 Register Class...
  const MCPhysReg GPRMM16[] = {
    Mips::S0, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 
  };

  // GPRMM16 Bit set.
  const uint8_t GPRMM16Bits[] = {
    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
  };

  // GPRMM16MoveP Register Class...
  const MCPhysReg GPRMM16MoveP[] = {
    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, 
  };

  // GPRMM16MoveP Bit set.
  const uint8_t GPRMM16MovePBits[] = {
    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, 
  };

  // GPRMM16Zero Register Class...
  const MCPhysReg GPRMM16Zero[] = {
    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 
  };

  // GPRMM16Zero Bit set.
  const uint8_t GPRMM16ZeroBits[] = {
    0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
  };

  // CPU16Regs_and_GPRMM16Zero Register Class...
  const MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
    Mips::S1, Mips::V0, Mips::V1, Mips::A0, Mips::A1, Mips::A2, Mips::A3, 
  };

  // CPU16Regs_and_GPRMM16Zero Bit set.
  const uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
  };

  // GPR32NONZERO_and_GPRMM16MoveP Register Class...
  const MCPhysReg GPR32NONZERO_and_GPRMM16MoveP[] = {
    Mips::S1, Mips::V0, Mips::V1, Mips::S0, Mips::S2, Mips::S3, Mips::S4, 
  };

  // GPR32NONZERO_and_GPRMM16MoveP Bit set.
  const uint8_t GPR32NONZERO_and_GPRMM16MovePBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06, 
  };

  // GPRMM16MovePPairSecond Register Class...
  const MCPhysReg GPRMM16MovePPairSecond[] = {
    Mips::A1, Mips::A2, Mips::A3, Mips::S5, Mips::S6, 
  };

  // GPRMM16MovePPairSecond Bit set.
  const uint8_t GPRMM16MovePPairSecondBits[] = {
    0x00, 0x00, 0x80, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // CPU16Regs_and_GPRMM16MoveP Register Class...
  const MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
    Mips::S1, Mips::V0, Mips::V1, Mips::S0, 
  };

  // CPU16Regs_and_GPRMM16MoveP Bit set.
  const uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06, 
  };

  // GPRMM16MoveP_and_GPRMM16Zero Register Class...
  const MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
    Mips::ZERO, Mips::S1, Mips::V0, Mips::V1, 
  };

  // GPRMM16MoveP_and_GPRMM16Zero Bit set.
  const uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
  };

  // HI32DSP Register Class...
  const MCPhysReg HI32DSP[] = {
    Mips::HI0, Mips::HI1, Mips::HI2, Mips::HI3, 
  };

  // HI32DSP Bit set.
  const uint8_t HI32DSPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
  };

  // LO32DSP Register Class...
  const MCPhysReg LO32DSP[] = {
    Mips::LO0, Mips::LO1, Mips::LO2, Mips::LO3, 
  };

  // LO32DSP Bit set.
  const uint8_t LO32DSPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
  const MCPhysReg CPU16Regs_and_GPRMM16MovePPairSecond[] = {
    Mips::A1, Mips::A2, Mips::A3, 
  };

  // CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
  const uint8_t CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
    0x00, 0x00, 0x80, 0x03, 
  };

  // GPRMM16MovePPairFirst Register Class...
  const MCPhysReg GPRMM16MovePPairFirst[] = {
    Mips::A0, Mips::A1, Mips::A2, 
  };

  // GPRMM16MovePPairFirst Bit set.
  const uint8_t GPRMM16MovePPairFirstBits[] = {
    0x00, 0x00, 0xc0, 0x01, 
  };

  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
  const MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
    Mips::S1, Mips::V0, Mips::V1, 
  };

  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
  const uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06, 
  };

  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
  const MCPhysReg GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
    Mips::A1, Mips::A2, 
  };

  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
  const uint8_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
    0x00, 0x00, 0x80, 0x01, 
  };

  // CPURAReg Register Class...
  const MCPhysReg CPURAReg[] = {
    Mips::RA, 
  };

  // CPURAReg Bit set.
  const uint8_t CPURARegBits[] = {
    0x00, 0x00, 0x08, 
  };

  // CPUSPReg Register Class...
  const MCPhysReg CPUSPReg[] = {
    Mips::SP, 
  };

  // CPUSPReg Bit set.
  const uint8_t CPUSPRegBits[] = {
    0x00, 0x00, 0x10, 
  };

  // DSPCC Register Class...
  const MCPhysReg DSPCC[] = {
    Mips::DSPCCond, 
  };

  // DSPCC Bit set.
  const uint8_t DSPCCBits[] = {
    0x04, 
  };

  // GP32 Register Class...
  const MCPhysReg GP32[] = {
    Mips::GP, 
  };

  // GP32 Bit set.
  const uint8_t GP32Bits[] = {
    0x00, 0x02, 
  };

  // GPR32ZERO Register Class...
  const MCPhysReg GPR32ZERO[] = {
    Mips::ZERO, 
  };

  // GPR32ZERO Bit set.
  const uint8_t GPR32ZEROBits[] = {
    0x00, 0x00, 0x20, 
  };

  // HI32 Register Class...
  const MCPhysReg HI32[] = {
    Mips::HI0, 
  };

  // HI32 Bit set.
  const uint8_t HI32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

  // LO32 Register Class...
  const MCPhysReg LO32[] = {
    Mips::LO0, 
  };

  // LO32 Bit set.
  const uint8_t LO32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // SP32 Register Class...
  const MCPhysReg SP32[] = {
    Mips::SP, 
  };

  // SP32 Bit set.
  const uint8_t SP32Bits[] = {
    0x00, 0x00, 0x10, 
  };

  // FGR64 Register Class...
  const MCPhysReg FGR64[] = {
    Mips::D0_64, Mips::D1_64, Mips::D2_64, Mips::D3_64, Mips::D4_64, Mips::D5_64, Mips::D6_64, Mips::D7_64, Mips::D8_64, Mips::D9_64, Mips::D10_64, Mips::D11_64, Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64, Mips::D16_64, Mips::D17_64, Mips::D18_64, Mips::D19_64, Mips::D20_64, Mips::D21_64, Mips::D22_64, Mips::D23_64, Mips::D24_64, Mips::D25_64, Mips::D26_64, Mips::D27_64, Mips::D28_64, Mips::D29_64, Mips::D30_64, Mips::D31_64, 
  };

  // FGR64 Bit set.
  const uint8_t FGR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // GPR64 Register Class...
  const MCPhysReg GPR64[] = {
    Mips::ZERO_64, Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 
  };

  // GPR64 Bit set.
  const uint8_t GPR64Bits[] = {
    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, 
  };

  // GPR64_with_sub_32_in_GPR32NONZERO Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO[] = {
    Mips::AT_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64, Mips::T4_64, Mips::T5_64, Mips::T6_64, Mips::T7_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, Mips::S5_64, Mips::S6_64, Mips::S7_64, Mips::T8_64, Mips::T9_64, Mips::K0_64, Mips::K1_64, Mips::GP_64, Mips::SP_64, Mips::FP_64, Mips::RA_64, 
  };

  // GPR64_with_sub_32_in_GPR32NONZERO Bit set.
  const uint8_t GPR64_with_sub_32_in_GPR32NONZEROBits[] = {
    0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03, 
  };

  // AFGR64 Register Class...
  const MCPhysReg AFGR64[] = {
    Mips::D0, Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D6, Mips::D7, Mips::D8, Mips::D9, Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, 
  };

  // AFGR64 Bit set.
  const uint8_t AFGR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f, 
  };

  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
  const MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, Mips::SP_64, 
  };

  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
  const uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_CPU16Regs Register Class...
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S0_64, Mips::S1_64, 
  };

  // GPR64_with_sub_32_in_CPU16Regs Bit set.
  const uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
    Mips::V0_64, Mips::V1_64, Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S1_64, 
  };

  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP[] = {
    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, Mips::S2_64, Mips::S3_64, Mips::S4_64, 
  };

  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP Bit set.
  const uint8_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairSecond[] = {
    Mips::A1_64, Mips::A2_64, Mips::A3_64, Mips::S5_64, Mips::S6_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 
  };

  // ACC64DSP Register Class...
  const MCPhysReg ACC64DSP[] = {
    Mips::AC0, Mips::AC1, Mips::AC2, Mips::AC3, 
  };

  // ACC64DSP Bit set.
  const uint8_t ACC64DSPBits[] = {
    0x00, 0x00, 0x00, 0x3c, 
  };

  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
    Mips::V0_64, Mips::V1_64, Mips::S0_64, Mips::S1_64, 
  };

  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
    Mips::ZERO_64, Mips::V0_64, Mips::V1_64, Mips::S1_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
  };

  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Register Class...
  const MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond[] = {
    Mips::A1_64, Mips::A2_64, Mips::A3_64, 
  };

  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond Bit set.
  const uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 
  };

  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst[] = {
    Mips::A0_64, Mips::A1_64, Mips::A2_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 
  };

  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
    Mips::V0_64, Mips::V1_64, Mips::S1_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03, 
  };

  // OCTEON_MPL Register Class...
  const MCPhysReg OCTEON_MPL[] = {
    Mips::MPL0, Mips::MPL1, Mips::MPL2, 
  };

  // OCTEON_MPL Bit set.
  const uint8_t OCTEON_MPLBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03, 
  };

  // OCTEON_P Register Class...
  const MCPhysReg OCTEON_P[] = {
    Mips::P0, Mips::P1, Mips::P2, 
  };

  // OCTEON_P Bit set.
  const uint8_t OCTEON_PBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 
  };

  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond[] = {
    Mips::A1_64, Mips::A2_64, 
  };

  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond Bit set.
  const uint8_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 
  };

  // ACC64 Register Class...
  const MCPhysReg ACC64[] = {
    Mips::AC0, 
  };

  // ACC64 Bit set.
  const uint8_t ACC64Bits[] = {
    0x00, 0x00, 0x00, 0x04, 
  };

  // GP64 Register Class...
  const MCPhysReg GP64[] = {
    Mips::GP_64, 
  };

  // GP64 Bit set.
  const uint8_t GP64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // GPR64_with_sub_32_in_CPURAReg Register Class...
  const MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
    Mips::RA_64, 
  };

  // GPR64_with_sub_32_in_CPURAReg Bit set.
  const uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

  // GPR64_with_sub_32_in_GPR32ZERO Register Class...
  const MCPhysReg GPR64_with_sub_32_in_GPR32ZERO[] = {
    Mips::ZERO_64, 
  };

  // GPR64_with_sub_32_in_GPR32ZERO Bit set.
  const uint8_t GPR64_with_sub_32_in_GPR32ZEROBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // HI64 Register Class...
  const MCPhysReg HI64[] = {
    Mips::HI0_64, 
  };

  // HI64 Bit set.
  const uint8_t HI64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // LO64 Register Class...
  const MCPhysReg LO64[] = {
    Mips::LO0_64, 
  };

  // LO64 Bit set.
  const uint8_t LO64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

  // SP64 Register Class...
  const MCPhysReg SP64[] = {
    Mips::SP_64, 
  };

  // SP64 Bit set.
  const uint8_t SP64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // MSA128B Register Class...
  const MCPhysReg MSA128B[] = {
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
  };

  // MSA128B Bit set.
  const uint8_t MSA128BBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // MSA128D Register Class...
  const MCPhysReg MSA128D[] = {
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
  };

  // MSA128D Bit set.
  const uint8_t MSA128DBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // MSA128H Register Class...
  const MCPhysReg MSA128H[] = {
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
  };

  // MSA128H Bit set.
  const uint8_t MSA128HBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // MSA128W Register Class...
  const MCPhysReg MSA128W[] = {
    Mips::W0, Mips::W1, Mips::W2, Mips::W3, Mips::W4, Mips::W5, Mips::W6, Mips::W7, Mips::W8, Mips::W9, Mips::W10, Mips::W11, Mips::W12, Mips::W13, Mips::W14, Mips::W15, Mips::W16, Mips::W17, Mips::W18, Mips::W19, Mips::W20, Mips::W21, Mips::W22, Mips::W23, Mips::W24, Mips::W25, Mips::W26, Mips::W27, Mips::W28, Mips::W29, Mips::W30, Mips::W31, 
  };

  // MSA128W Bit set.
  const uint8_t MSA128WBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // MSA128WEvens Register Class...
  const MCPhysReg MSA128WEvens[] = {
    Mips::W0, Mips::W2, Mips::W4, Mips::W6, Mips::W8, Mips::W10, Mips::W12, Mips::W14, Mips::W16, Mips::W18, Mips::W20, Mips::W22, Mips::W24, Mips::W26, Mips::W28, Mips::W30, 
  };

  // MSA128WEvens Bit set.
  const uint8_t MSA128WEvensBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02, 
  };

  // ACC128 Register Class...
  const MCPhysReg ACC128[] = {
    Mips::AC0_64, 
  };

  // ACC128 Bit set.
  const uint8_t ACC128Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char MipsRegClassStrings[] = {
  /* 0 */ "COP0\0"
  /* 5 */ "HI32\0"
  /* 10 */ "LO32\0"
  /* 15 */ "GP32\0"
  /* 20 */ "SP32\0"
  /* 25 */ "FGR32\0"
  /* 31 */ "GPR32\0"
  /* 37 */ "COP2\0"
  /* 42 */ "COP3\0"
  /* 47 */ "ACC64\0"
  /* 53 */ "HI64\0"
  /* 58 */ "LO64\0"
  /* 63 */ "GP64\0"
  /* 68 */ "SP64\0"
  /* 73 */ "AFGR64\0"
  /* 80 */ "GPR64\0"
  /* 86 */ "MSA128F16\0"
  /* 96 */ "GPRMM16\0"
  /* 104 */ "ACC128\0"
  /* 111 */ "MSA128B\0"
  /* 119 */ "FCC\0"
  /* 123 */ "DSPCC\0"
  /* 129 */ "FGRCC\0"
  /* 135 */ "MSA128D\0"
  /* 143 */ "MSA128H\0"
  /* 151 */ "OCTEON_MPL\0"
  /* 162 */ "GPR64_with_sub_32_in_GPR32ZERO\0"
  /* 193 */ "GPR64_with_sub_32_in_GPR32NONZERO\0"
  /* 227 */ "HI32DSP\0"
  /* 235 */ "LO32DSP\0"
  /* 243 */ "ACC64DSP\0"
  /* 252 */ "GPR64_with_sub_32_in_CPU16RegsPlusSP\0"
  /* 289 */ "OCTEON_P\0"
  /* 298 */ "GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP\0"
  /* 349 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP\0"
  /* 397 */ "GPR64_with_sub_32_in_GPRMM16MoveP\0"
  /* 431 */ "CCR\0"
  /* 435 */ "DSPR\0"
  /* 440 */ "MSA128W\0"
  /* 448 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond\0"
  /* 506 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond\0"
  /* 576 */ "GPR64_with_sub_32_in_GPRMM16MovePPairSecond\0"
  /* 620 */ "GPR64_with_sub_32_in_CPURAReg\0"
  /* 650 */ "CPUSPReg\0"
  /* 659 */ "MSACtrl\0"
  /* 667 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero\0"
  /* 717 */ "GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero\0"
  /* 781 */ "GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero\0"
  /* 828 */ "GPR64_with_sub_32_in_GPRMM16Zero\0"
  /* 861 */ "GPR64_with_sub_32_in_CPU16Regs\0"
  /* 892 */ "HWRegs\0"
  /* 899 */ "MSA128WEvens\0"
  /* 912 */ "GPR64_with_sub_32_in_GPRMM16MovePPairFirst\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass MipsMCRegisterClasses[] = {
  { MSA128F16, MSA128F16Bits, 86, 32, sizeof(MSA128F16Bits), Mips::MSA128F16RegClassID, 16, 1, true },
  { CCR, CCRBits, 431, 32, sizeof(CCRBits), Mips::CCRRegClassID, 32, 1, false },
  { COP0, COP0Bits, 0, 32, sizeof(COP0Bits), Mips::COP0RegClassID, 32, 1, false },
  { COP2, COP2Bits, 37, 32, sizeof(COP2Bits), Mips::COP2RegClassID, 32, 1, false },
  { COP3, COP3Bits, 42, 32, sizeof(COP3Bits), Mips::COP3RegClassID, 32, 1, false },
  { DSPR, DSPRBits, 435, 32, sizeof(DSPRBits), Mips::DSPRRegClassID, 32, 1, true },
  { FGR32, FGR32Bits, 25, 32, sizeof(FGR32Bits), Mips::FGR32RegClassID, 32, 1, true },
  { FGRCC, FGRCCBits, 129, 32, sizeof(FGRCCBits), Mips::FGRCCRegClassID, 32, 1, true },
  { GPR32, GPR32Bits, 31, 32, sizeof(GPR32Bits), Mips::GPR32RegClassID, 32, 1, true },
  { HWRegs, HWRegsBits, 892, 32, sizeof(HWRegsBits), Mips::HWRegsRegClassID, 32, 1, false },
  { MSACtrl, MSACtrlBits, 659, 32, sizeof(MSACtrlBits), Mips::MSACtrlRegClassID, 32, 1, false },
  { GPR32NONZERO, GPR32NONZEROBits, 214, 31, sizeof(GPR32NONZEROBits), Mips::GPR32NONZERORegClassID, 32, 1, true },
  { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 273, 9, sizeof(CPU16RegsPlusSPBits), Mips::CPU16RegsPlusSPRegClassID, 32, 1, true },
  { CPU16Regs, CPU16RegsBits, 882, 8, sizeof(CPU16RegsBits), Mips::CPU16RegsRegClassID, 32, 1, true },
  { FCC, FCCBits, 119, 8, sizeof(FCCBits), Mips::FCCRegClassID, 32, 1, false },
  { GPRMM16, GPRMM16Bits, 96, 8, sizeof(GPRMM16Bits), Mips::GPRMM16RegClassID, 32, 1, true },
  { GPRMM16MoveP, GPRMM16MovePBits, 336, 8, sizeof(GPRMM16MovePBits), Mips::GPRMM16MovePRegClassID, 32, 1, true },
  { GPRMM16Zero, GPRMM16ZeroBits, 705, 8, sizeof(GPRMM16ZeroBits), Mips::GPRMM16ZeroRegClassID, 32, 1, true },
  { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 755, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips::CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },
  { GPR32NONZERO_and_GPRMM16MoveP, GPR32NONZERO_and_GPRMM16MovePBits, 319, 7, sizeof(GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR32NONZERO_and_GPRMM16MovePRegClassID, 32, 1, true },
  { GPRMM16MovePPairSecond, GPRMM16MovePPairSecondBits, 483, 5, sizeof(GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairSecondRegClassID, 32, 1, true },
  { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 370, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips::CPU16Regs_and_GPRMM16MovePRegClassID, 32, 1, true },
  { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 688, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 32, 1, true },
  { HI32DSP, HI32DSPBits, 227, 4, sizeof(HI32DSPBits), Mips::HI32DSPRegClassID, 32, 1, true },
  { LO32DSP, LO32DSPBits, 235, 4, sizeof(LO32DSPBits), Mips::LO32DSPRegClassID, 32, 1, true },
  { CPU16Regs_and_GPRMM16MovePPairSecond, CPU16Regs_and_GPRMM16MovePPairSecondBits, 469, 3, sizeof(CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },
  { GPRMM16MovePPairFirst, GPRMM16MovePPairFirstBits, 933, 3, sizeof(GPRMM16MovePPairFirstBits), Mips::GPRMM16MovePPairFirstRegClassID, 32, 1, true },
  { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 738, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 32, 1, true },
  { GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 527, 2, sizeof(GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 32, 1, true },
  { CPURAReg, CPURARegBits, 641, 1, sizeof(CPURARegBits), Mips::CPURARegRegClassID, 32, 1, false },
  { CPUSPReg, CPUSPRegBits, 650, 1, sizeof(CPUSPRegBits), Mips::CPUSPRegRegClassID, 32, 1, false },
  { DSPCC, DSPCCBits, 123, 1, sizeof(DSPCCBits), Mips::DSPCCRegClassID, 32, 1, true },
  { GP32, GP32Bits, 15, 1, sizeof(GP32Bits), Mips::GP32RegClassID, 32, 1, false },
  { GPR32ZERO, GPR32ZEROBits, 183, 1, sizeof(GPR32ZEROBits), Mips::GPR32ZERORegClassID, 32, 1, true },
  { HI32, HI32Bits, 5, 1, sizeof(HI32Bits), Mips::HI32RegClassID, 32, 1, true },
  { LO32, LO32Bits, 10, 1, sizeof(LO32Bits), Mips::LO32RegClassID, 32, 1, true },
  { SP32, SP32Bits, 20, 1, sizeof(SP32Bits), Mips::SP32RegClassID, 32, 1, false },
  { FGR64, FGR64Bits, 74, 32, sizeof(FGR64Bits), Mips::FGR64RegClassID, 64, 1, true },
  { GPR64, GPR64Bits, 80, 32, sizeof(GPR64Bits), Mips::GPR64RegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPR32NONZERO, GPR64_with_sub_32_in_GPR32NONZEROBits, 193, 31, sizeof(GPR64_with_sub_32_in_GPR32NONZEROBits), Mips::GPR64_with_sub_32_in_GPR32NONZERORegClassID, 64, 1, true },
  { AFGR64, AFGR64Bits, 73, 16, sizeof(AFGR64Bits), Mips::AFGR64RegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 252, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 861, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips::GPR64_with_sub_32_in_CPU16RegsRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 397, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 828, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 781, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP, GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits, 298, 7, sizeof(GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits, 576, 5, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
  { ACC64DSP, ACC64DSPBits, 243, 4, sizeof(ACC64DSPBits), Mips::ACC64DSPRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 349, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 667, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits, 448, 3, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst, GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits, 912, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirstBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 717, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 64, 1, true },
  { OCTEON_MPL, OCTEON_MPLBits, 151, 3, sizeof(OCTEON_MPLBits), Mips::OCTEON_MPLRegClassID, 64, 1, false },
  { OCTEON_P, OCTEON_PBits, 289, 3, sizeof(OCTEON_PBits), Mips::OCTEON_PRegClassID, 64, 1, false },
  { GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond, GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits, 506, 2, sizeof(GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondBits), Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID, 64, 1, true },
  { ACC64, ACC64Bits, 47, 1, sizeof(ACC64Bits), Mips::ACC64RegClassID, 64, 1, true },
  { GP64, GP64Bits, 63, 1, sizeof(GP64Bits), Mips::GP64RegClassID, 64, 1, false },
  { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 620, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips::GPR64_with_sub_32_in_CPURARegRegClassID, 64, 1, true },
  { GPR64_with_sub_32_in_GPR32ZERO, GPR64_with_sub_32_in_GPR32ZEROBits, 162, 1, sizeof(GPR64_with_sub_32_in_GPR32ZEROBits), Mips::GPR64_with_sub_32_in_GPR32ZERORegClassID, 64, 1, true },
  { HI64, HI64Bits, 53, 1, sizeof(HI64Bits), Mips::HI64RegClassID, 64, 1, true },
  { LO64, LO64Bits, 58, 1, sizeof(LO64Bits), Mips::LO64RegClassID, 64, 1, true },
  { SP64, SP64Bits, 68, 1, sizeof(SP64Bits), Mips::SP64RegClassID, 64, 1, false },
  { MSA128B, MSA128BBits, 111, 32, sizeof(MSA128BBits), Mips::MSA128BRegClassID, 128, 1, true },
  { MSA128D, MSA128DBits, 135, 32, sizeof(MSA128DBits), Mips::MSA128DRegClassID, 128, 1, true },
  { MSA128H, MSA128HBits, 143, 32, sizeof(MSA128HBits), Mips::MSA128HRegClassID, 128, 1, true },
  { MSA128W, MSA128WBits, 440, 32, sizeof(MSA128WBits), Mips::MSA128WRegClassID, 128, 1, true },
  { MSA128WEvens, MSA128WEvensBits, 899, 16, sizeof(MSA128WEvensBits), Mips::MSA128WEvensRegClassID, 128, 1, true },
  { ACC128, ACC128Bits, 104, 1, sizeof(ACC128Bits), Mips::ACC128RegClassID, 128, 1, true },
};

// Mips Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[] = {
  { 0U, Mips::ZERO_64 },
  { 1U, Mips::AT_64 },
  { 2U, Mips::V0_64 },
  { 3U, Mips::V1_64 },
  { 4U, Mips::A0_64 },
  { 5U, Mips::A1_64 },
  { 6U, Mips::A2_64 },
  { 7U, Mips::A3_64 },
  { 8U, Mips::T0_64 },
  { 9U, Mips::T1_64 },
  { 10U, Mips::T2_64 },
  { 11U, Mips::T3_64 },
  { 12U, Mips::T4_64 },
  { 13U, Mips::T5_64 },
  { 14U, Mips::T6_64 },
  { 15U, Mips::T7_64 },
  { 16U, Mips::S0_64 },
  { 17U, Mips::S1_64 },
  { 18U, Mips::S2_64 },
  { 19U, Mips::S3_64 },
  { 20U, Mips::S4_64 },
  { 21U, Mips::S5_64 },
  { 22U, Mips::S6_64 },
  { 23U, Mips::S7_64 },
  { 24U, Mips::T8_64 },
  { 25U, Mips::T9_64 },
  { 26U, Mips::K0_64 },
  { 27U, Mips::K1_64 },
  { 28U, Mips::GP_64 },
  { 29U, Mips::SP_64 },
  { 30U, Mips::FP_64 },
  { 31U, Mips::RA_64 },
  { 32U, Mips::D0_64 },
  { 33U, Mips::D1_64 },
  { 34U, Mips::D2_64 },
  { 35U, Mips::D3_64 },
  { 36U, Mips::D4_64 },
  { 37U, Mips::D5_64 },
  { 38U, Mips::D6_64 },
  { 39U, Mips::D7_64 },
  { 40U, Mips::D8_64 },
  { 41U, Mips::D9_64 },
  { 42U, Mips::D10_64 },
  { 43U, Mips::D11_64 },
  { 44U, Mips::D12_64 },
  { 45U, Mips::D13_64 },
  { 46U, Mips::D14_64 },
  { 47U, Mips::D15_64 },
  { 48U, Mips::D16_64 },
  { 49U, Mips::D17_64 },
  { 50U, Mips::D18_64 },
  { 51U, Mips::D19_64 },
  { 52U, Mips::D20_64 },
  { 53U, Mips::D21_64 },
  { 54U, Mips::D22_64 },
  { 55U, Mips::D23_64 },
  { 56U, Mips::D24_64 },
  { 57U, Mips::D25_64 },
  { 58U, Mips::D26_64 },
  { 59U, Mips::D27_64 },
  { 60U, Mips::D28_64 },
  { 61U, Mips::D29_64 },
  { 62U, Mips::D30_64 },
  { 63U, Mips::D31_64 },
  { 64U, Mips::HI0 },
  { 65U, Mips::LO0 },
  { 176U, Mips::HI1 },
  { 177U, Mips::LO1 },
  { 178U, Mips::HI2 },
  { 179U, Mips::LO2 },
  { 180U, Mips::HI3 },
  { 181U, Mips::LO3 },
};
extern const unsigned MipsDwarfFlavour0Dwarf2LSize = std::size(MipsDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[] = {
  { 0U, Mips::ZERO_64 },
  { 1U, Mips::AT_64 },
  { 2U, Mips::V0_64 },
  { 3U, Mips::V1_64 },
  { 4U, Mips::A0_64 },
  { 5U, Mips::A1_64 },
  { 6U, Mips::A2_64 },
  { 7U, Mips::A3_64 },
  { 8U, Mips::T0_64 },
  { 9U, Mips::T1_64 },
  { 10U, Mips::T2_64 },
  { 11U, Mips::T3_64 },
  { 12U, Mips::T4_64 },
  { 13U, Mips::T5_64 },
  { 14U, Mips::T6_64 },
  { 15U, Mips::T7_64 },
  { 16U, Mips::S0_64 },
  { 17U, Mips::S1_64 },
  { 18U, Mips::S2_64 },
  { 19U, Mips::S3_64 },
  { 20U, Mips::S4_64 },
  { 21U, Mips::S5_64 },
  { 22U, Mips::S6_64 },
  { 23U, Mips::S7_64 },
  { 24U, Mips::T8_64 },
  { 25U, Mips::T9_64 },
  { 26U, Mips::K0_64 },
  { 27U, Mips::K1_64 },
  { 28U, Mips::GP_64 },
  { 29U, Mips::SP_64 },
  { 30U, Mips::FP_64 },
  { 31U, Mips::RA_64 },
  { 32U, Mips::D0_64 },
  { 33U, Mips::D1_64 },
  { 34U, Mips::D2_64 },
  { 35U, Mips::D3_64 },
  { 36U, Mips::D4_64 },
  { 37U, Mips::D5_64 },
  { 38U, Mips::D6_64 },
  { 39U, Mips::D7_64 },
  { 40U, Mips::D8_64 },
  { 41U, Mips::D9_64 },
  { 42U, Mips::D10_64 },
  { 43U, Mips::D11_64 },
  { 44U, Mips::D12_64 },
  { 45U, Mips::D13_64 },
  { 46U, Mips::D14_64 },
  { 47U, Mips::D15_64 },
  { 48U, Mips::D16_64 },
  { 49U, Mips::D17_64 },
  { 50U, Mips::D18_64 },
  { 51U, Mips::D19_64 },
  { 52U, Mips::D20_64 },
  { 53U, Mips::D21_64 },
  { 54U, Mips::D22_64 },
  { 55U, Mips::D23_64 },
  { 56U, Mips::D24_64 },
  { 57U, Mips::D25_64 },
  { 58U, Mips::D26_64 },
  { 59U, Mips::D27_64 },
  { 60U, Mips::D28_64 },
  { 61U, Mips::D29_64 },
  { 62U, Mips::D30_64 },
  { 63U, Mips::D31_64 },
  { 64U, Mips::HI0 },
  { 65U, Mips::LO0 },
  { 176U, Mips::HI1 },
  { 177U, Mips::LO1 },
  { 178U, Mips::HI2 },
  { 179U, Mips::LO2 },
  { 180U, Mips::HI3 },
  { 181U, Mips::LO3 },
};
extern const unsigned MipsEHFlavour0Dwarf2LSize = std::size(MipsEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[] = {
  { Mips::AT, 1U },
  { Mips::FP, 30U },
  { Mips::GP, 28U },
  { Mips::RA, 31U },
  { Mips::SP, 29U },
  { Mips::ZERO, 0U },
  { Mips::A0, 4U },
  { Mips::A1, 5U },
  { Mips::A2, 6U },
  { Mips::A3, 7U },
  { Mips::AT_64, 1U },
  { Mips::F0, 32U },
  { Mips::F1, 33U },
  { Mips::F2, 34U },
  { Mips::F3, 35U },
  { Mips::F4, 36U },
  { Mips::F5, 37U },
  { Mips::F6, 38U },
  { Mips::F7, 39U },
  { Mips::F8, 40U },
  { Mips::F9, 41U },
  { Mips::F10, 42U },
  { Mips::F11, 43U },
  { Mips::F12, 44U },
  { Mips::F13, 45U },
  { Mips::F14, 46U },
  { Mips::F15, 47U },
  { Mips::F16, 48U },
  { Mips::F17, 49U },
  { Mips::F18, 50U },
  { Mips::F19, 51U },
  { Mips::F20, 52U },
  { Mips::F21, 53U },
  { Mips::F22, 54U },
  { Mips::F23, 55U },
  { Mips::F24, 56U },
  { Mips::F25, 57U },
  { Mips::F26, 58U },
  { Mips::F27, 59U },
  { Mips::F28, 60U },
  { Mips::F29, 61U },
  { Mips::F30, 62U },
  { Mips::F31, 63U },
  { Mips::FP_64, 30U },
  { Mips::F_HI0, 32U },
  { Mips::F_HI1, 33U },
  { Mips::F_HI2, 34U },
  { Mips::F_HI3, 35U },
  { Mips::F_HI4, 36U },
  { Mips::F_HI5, 37U },
  { Mips::F_HI6, 38U },
  { Mips::F_HI7, 39U },
  { Mips::F_HI8, 40U },
  { Mips::F_HI9, 41U },
  { Mips::F_HI10, 42U },
  { Mips::F_HI11, 43U },
  { Mips::F_HI12, 44U },
  { Mips::F_HI13, 45U },
  { Mips::F_HI14, 46U },
  { Mips::F_HI15, 47U },
  { Mips::F_HI16, 48U },
  { Mips::F_HI17, 49U },
  { Mips::F_HI18, 50U },
  { Mips::F_HI19, 51U },
  { Mips::F_HI20, 52U },
  { Mips::F_HI21, 53U },
  { Mips::F_HI22, 54U },
  { Mips::F_HI23, 55U },
  { Mips::F_HI24, 56U },
  { Mips::F_HI25, 57U },
  { Mips::F_HI26, 58U },
  { Mips::F_HI27, 59U },
  { Mips::F_HI28, 60U },
  { Mips::F_HI29, 61U },
  { Mips::F_HI30, 62U },
  { Mips::F_HI31, 63U },
  { Mips::GP_64, 28U },
  { Mips::HI0, 64U },
  { Mips::HI1, 176U },
  { Mips::HI2, 178U },
  { Mips::HI3, 180U },
  { Mips::K0, 26U },
  { Mips::K1, 27U },
  { Mips::LO0, 65U },
  { Mips::LO1, 177U },
  { Mips::LO2, 179U },
  { Mips::LO3, 181U },
  { Mips::RA_64, 31U },
  { Mips::S0, 16U },
  { Mips::S1, 17U },
  { Mips::S2, 18U },
  { Mips::S3, 19U },
  { Mips::S4, 20U },
  { Mips::S5, 21U },
  { Mips::S6, 22U },
  { Mips::S7, 23U },
  { Mips::SP_64, 29U },
  { Mips::T0, 8U },
  { Mips::T1, 9U },
  { Mips::T2, 10U },
  { Mips::T3, 11U },
  { Mips::T4, 12U },
  { Mips::T5, 13U },
  { Mips::T6, 14U },
  { Mips::T7, 15U },
  { Mips::T8, 24U },
  { Mips::T9, 25U },
  { Mips::V0, 2U },
  { Mips::V1, 3U },
  { Mips::W0, 32U },
  { Mips::W1, 33U },
  { Mips::W2, 34U },
  { Mips::W3, 35U },
  { Mips::W4, 36U },
  { Mips::W5, 37U },
  { Mips::W6, 38U },
  { Mips::W7, 39U },
  { Mips::W8, 40U },
  { Mips::W9, 41U },
  { Mips::W10, 42U },
  { Mips::W11, 43U },
  { Mips::W12, 44U },
  { Mips::W13, 45U },
  { Mips::W14, 46U },
  { Mips::W15, 47U },
  { Mips::W16, 48U },
  { Mips::W17, 49U },
  { Mips::W18, 50U },
  { Mips::W19, 51U },
  { Mips::W20, 52U },
  { Mips::W21, 53U },
  { Mips::W22, 54U },
  { Mips::W23, 55U },
  { Mips::W24, 56U },
  { Mips::W25, 57U },
  { Mips::W26, 58U },
  { Mips::W27, 59U },
  { Mips::W28, 60U },
  { Mips::W29, 61U },
  { Mips::W30, 62U },
  { Mips::W31, 63U },
  { Mips::ZERO_64, 0U },
  { Mips::A0_64, 4U },
  { Mips::A1_64, 5U },
  { Mips::A2_64, 6U },
  { Mips::A3_64, 7U },
  { Mips::D0_64, 32U },
  { Mips::D1_64, 33U },
  { Mips::D2_64, 34U },
  { Mips::D3_64, 35U },
  { Mips::D4_64, 36U },
  { Mips::D5_64, 37U },
  { Mips::D6_64, 38U },
  { Mips::D7_64, 39U },
  { Mips::D8_64, 40U },
  { Mips::D9_64, 41U },
  { Mips::D10_64, 42U },
  { Mips::D11_64, 43U },
  { Mips::D12_64, 44U },
  { Mips::D13_64, 45U },
  { Mips::D14_64, 46U },
  { Mips::D15_64, 47U },
  { Mips::D16_64, 48U },
  { Mips::D17_64, 49U },
  { Mips::D18_64, 50U },
  { Mips::D19_64, 51U },
  { Mips::D20_64, 52U },
  { Mips::D21_64, 53U },
  { Mips::D22_64, 54U },
  { Mips::D23_64, 55U },
  { Mips::D24_64, 56U },
  { Mips::D25_64, 57U },
  { Mips::D26_64, 58U },
  { Mips::D27_64, 59U },
  { Mips::D28_64, 60U },
  { Mips::D29_64, 61U },
  { Mips::D30_64, 62U },
  { Mips::D31_64, 63U },
  { Mips::K0_64, 26U },
  { Mips::K1_64, 27U },
  { Mips::S0_64, 16U },
  { Mips::S1_64, 17U },
  { Mips::S2_64, 18U },
  { Mips::S3_64, 19U },
  { Mips::S4_64, 20U },
  { Mips::S5_64, 21U },
  { Mips::S6_64, 22U },
  { Mips::S7_64, 23U },
  { Mips::T0_64, 8U },
  { Mips::T1_64, 9U },
  { Mips::T2_64, 10U },
  { Mips::T3_64, 11U },
  { Mips::T4_64, 12U },
  { Mips::T5_64, 13U },
  { Mips::T6_64, 14U },
  { Mips::T7_64, 15U },
  { Mips::T8_64, 24U },
  { Mips::T9_64, 25U },
  { Mips::V0_64, 2U },
  { Mips::V1_64, 3U },
};
extern const unsigned MipsDwarfFlavour0L2DwarfSize = std::size(MipsDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[] = {
  { Mips::AT, 1U },
  { Mips::FP, 30U },
  { Mips::GP, 28U },
  { Mips::RA, 31U },
  { Mips::SP, 29U },
  { Mips::ZERO, 0U },
  { Mips::A0, 4U },
  { Mips::A1, 5U },
  { Mips::A2, 6U },
  { Mips::A3, 7U },
  { Mips::AT_64, 1U },
  { Mips::F0, 32U },
  { Mips::F1, 33U },
  { Mips::F2, 34U },
  { Mips::F3, 35U },
  { Mips::F4, 36U },
  { Mips::F5, 37U },
  { Mips::F6, 38U },
  { Mips::F7, 39U },
  { Mips::F8, 40U },
  { Mips::F9, 41U },
  { Mips::F10, 42U },
  { Mips::F11, 43U },
  { Mips::F12, 44U },
  { Mips::F13, 45U },
  { Mips::F14, 46U },
  { Mips::F15, 47U },
  { Mips::F16, 48U },
  { Mips::F17, 49U },
  { Mips::F18, 50U },
  { Mips::F19, 51U },
  { Mips::F20, 52U },
  { Mips::F21, 53U },
  { Mips::F22, 54U },
  { Mips::F23, 55U },
  { Mips::F24, 56U },
  { Mips::F25, 57U },
  { Mips::F26, 58U },
  { Mips::F27, 59U },
  { Mips::F28, 60U },
  { Mips::F29, 61U },
  { Mips::F30, 62U },
  { Mips::F31, 63U },
  { Mips::FP_64, 30U },
  { Mips::F_HI0, 32U },
  { Mips::F_HI1, 33U },
  { Mips::F_HI2, 34U },
  { Mips::F_HI3, 35U },
  { Mips::F_HI4, 36U },
  { Mips::F_HI5, 37U },
  { Mips::F_HI6, 38U },
  { Mips::F_HI7, 39U },
  { Mips::F_HI8, 40U },
  { Mips::F_HI9, 41U },
  { Mips::F_HI10, 42U },
  { Mips::F_HI11, 43U },
  { Mips::F_HI12, 44U },
  { Mips::F_HI13, 45U },
  { Mips::F_HI14, 46U },
  { Mips::F_HI15, 47U },
  { Mips::F_HI16, 48U },
  { Mips::F_HI17, 49U },
  { Mips::F_HI18, 50U },
  { Mips::F_HI19, 51U },
  { Mips::F_HI20, 52U },
  { Mips::F_HI21, 53U },
  { Mips::F_HI22, 54U },
  { Mips::F_HI23, 55U },
  { Mips::F_HI24, 56U },
  { Mips::F_HI25, 57U },
  { Mips::F_HI26, 58U },
  { Mips::F_HI27, 59U },
  { Mips::F_HI28, 60U },
  { Mips::F_HI29, 61U },
  { Mips::F_HI30, 62U },
  { Mips::F_HI31, 63U },
  { Mips::GP_64, 28U },
  { Mips::HI0, 64U },
  { Mips::HI1, 176U },
  { Mips::HI2, 178U },
  { Mips::HI3, 180U },
  { Mips::K0, 26U },
  { Mips::K1, 27U },
  { Mips::LO0, 65U },
  { Mips::LO1, 177U },
  { Mips::LO2, 179U },
  { Mips::LO3, 181U },
  { Mips::RA_64, 31U },
  { Mips::S0, 16U },
  { Mips::S1, 17U },
  { Mips::S2, 18U },
  { Mips::S3, 19U },
  { Mips::S4, 20U },
  { Mips::S5, 21U },
  { Mips::S6, 22U },
  { Mips::S7, 23U },
  { Mips::SP_64, 29U },
  { Mips::T0, 8U },
  { Mips::T1, 9U },
  { Mips::T2, 10U },
  { Mips::T3, 11U },
  { Mips::T4, 12U },
  { Mips::T5, 13U },
  { Mips::T6, 14U },
  { Mips::T7, 15U },
  { Mips::T8, 24U },
  { Mips::T9, 25U },
  { Mips::V0, 2U },
  { Mips::V1, 3U },
  { Mips::W0, 32U },
  { Mips::W1, 33U },
  { Mips::W2, 34U },
  { Mips::W3, 35U },
  { Mips::W4, 36U },
  { Mips::W5, 37U },
  { Mips::W6, 38U },
  { Mips::W7, 39U },
  { Mips::W8, 40U },
  { Mips::W9, 41U },
  { Mips::W10, 42U },
  { Mips::W11, 43U },
  { Mips::W12, 44U },
  { Mips::W13, 45U },
  { Mips::W14, 46U },
  { Mips::W15, 47U },
  { Mips::W16, 48U },
  { Mips::W17, 49U },
  { Mips::W18, 50U },
  { Mips::W19, 51U },
  { Mips::W20, 52U },
  { Mips::W21, 53U },
  { Mips::W22, 54U },
  { Mips::W23, 55U },
  { Mips::W24, 56U },
  { Mips::W25, 57U },
  { Mips::W26, 58U },
  { Mips::W27, 59U },
  { Mips::W28, 60U },
  { Mips::W29, 61U },
  { Mips::W30, 62U },
  { Mips::W31, 63U },
  { Mips::ZERO_64, 0U },
  { Mips::A0_64, 4U },
  { Mips::A1_64, 5U },
  { Mips::A2_64, 6U },
  { Mips::A3_64, 7U },
  { Mips::D0_64, 32U },
  { Mips::D1_64, 33U },
  { Mips::D2_64, 34U },
  { Mips::D3_64, 35U },
  { Mips::D4_64, 36U },
  { Mips::D5_64, 37U },
  { Mips::D6_64, 38U },
  { Mips::D7_64, 39U },
  { Mips::D8_64, 40U },
  { Mips::D9_64, 41U },
  { Mips::D10_64, 42U },
  { Mips::D11_64, 43U },
  { Mips::D12_64, 44U },
  { Mips::D13_64, 45U },
  { Mips::D14_64, 46U },
  { Mips::D15_64, 47U },
  { Mips::D16_64, 48U },
  { Mips::D17_64, 49U },
  { Mips::D18_64, 50U },
  { Mips::D19_64, 51U },
  { Mips::D20_64, 52U },
  { Mips::D21_64, 53U },
  { Mips::D22_64, 54U },
  { Mips::D23_64, 55U },
  { Mips::D24_64, 56U },
  { Mips::D25_64, 57U },
  { Mips::D26_64, 58U },
  { Mips::D27_64, 59U },
  { Mips::D28_64, 60U },
  { Mips::D29_64, 61U },
  { Mips::D30_64, 62U },
  { Mips::D31_64, 63U },
  { Mips::K0_64, 26U },
  { Mips::K1_64, 27U },
  { Mips::S0_64, 16U },
  { Mips::S1_64, 17U },
  { Mips::S2_64, 18U },
  { Mips::S3_64, 19U },
  { Mips::S4_64, 20U },
  { Mips::S5_64, 21U },
  { Mips::S6_64, 22U },
  { Mips::S7_64, 23U },
  { Mips::T0_64, 8U },
  { Mips::T1_64, 9U },
  { Mips::T2_64, 10U },
  { Mips::T3_64, 11U },
  { Mips::T4_64, 12U },
  { Mips::T5_64, 13U },
  { Mips::T6_64, 14U },
  { Mips::T7_64, 15U },
  { Mips::T8_64, 24U },
  { Mips::T9_64, 25U },
  { Mips::V0_64, 2U },
  { Mips::V1_64, 3U },
};
extern const unsigned MipsEHFlavour0L2DwarfSize = std::size(MipsEHFlavour0L2Dwarf);

extern const uint16_t MipsRegEncodingTable[] = {
  0,
  1,
  0,
  0,
  0,
  0,
  0,
  0,
  30,
  28,
  2,
  1,
  0,
  6,
  4,
  5,
  3,
  7,
  0,
  31,
  29,
  0,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  1,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  0,
  0,
  0,
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  30,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  28,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  26,
  27,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  31,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  29,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  24,
  25,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  4,
  5,
  6,
  7,
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  0,
  26,
  27,
  0,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  24,
  25,
  2,
  3,
};
static inline void InitMipsMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(MipsRegDesc, 442, RA, PC, MipsMCRegisterClasses, 70, MipsRegUnitRoots, 321, MipsRegDiffLists, MipsLaneMaskLists, MipsRegStrings, MipsRegClassStrings, MipsSubRegIdxLists, 12,
MipsSubRegIdxRanges, MipsRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class MipsFrameLowering;

struct MipsGenRegisterInfo : public TargetRegisterInfo {
  explicit MipsGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const MipsFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace Mips { // Register classes
  extern const TargetRegisterClass MSA128F16RegClass;
  extern const TargetRegisterClass CCRRegClass;
  extern const TargetRegisterClass COP0RegClass;
  extern const TargetRegisterClass COP2RegClass;
  extern const TargetRegisterClass COP3RegClass;
  extern const TargetRegisterClass DSPRRegClass;
  extern const TargetRegisterClass FGR32RegClass;
  extern const TargetRegisterClass FGRCCRegClass;
  extern const TargetRegisterClass GPR32RegClass;
  extern const TargetRegisterClass HWRegsRegClass;
  extern const TargetRegisterClass MSACtrlRegClass;
  extern const TargetRegisterClass GPR32NONZERORegClass;
  extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
  extern const TargetRegisterClass CPU16RegsRegClass;
  extern const TargetRegisterClass FCCRegClass;
  extern const TargetRegisterClass GPRMM16RegClass;
  extern const TargetRegisterClass GPRMM16MovePRegClass;
  extern const TargetRegisterClass GPRMM16ZeroRegClass;
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass HI32DSPRegClass;
  extern const TargetRegisterClass LO32DSPRegClass;
  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
  extern const TargetRegisterClass CPURARegRegClass;
  extern const TargetRegisterClass CPUSPRegRegClass;
  extern const TargetRegisterClass DSPCCRegClass;
  extern const TargetRegisterClass GP32RegClass;
  extern const TargetRegisterClass GPR32ZERORegClass;
  extern const TargetRegisterClass HI32RegClass;
  extern const TargetRegisterClass LO32RegClass;
  extern const TargetRegisterClass SP32RegClass;
  extern const TargetRegisterClass FGR64RegClass;
  extern const TargetRegisterClass GPR64RegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
  extern const TargetRegisterClass AFGR64RegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
  extern const TargetRegisterClass ACC64DSPRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
  extern const TargetRegisterClass OCTEON_MPLRegClass;
  extern const TargetRegisterClass OCTEON_PRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
  extern const TargetRegisterClass ACC64RegClass;
  extern const TargetRegisterClass GP64RegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
  extern const TargetRegisterClass HI64RegClass;
  extern const TargetRegisterClass LO64RegClass;
  extern const TargetRegisterClass SP64RegClass;
  extern const TargetRegisterClass MSA128BRegClass;
  extern const TargetRegisterClass MSA128DRegClass;
  extern const TargetRegisterClass MSA128HRegClass;
  extern const TargetRegisterClass MSA128WRegClass;
  extern const TargetRegisterClass MSA128WEvensRegClass;
  extern const TargetRegisterClass ACC128RegClass;
} // end namespace Mips

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass MipsMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i32, MVT::Other,
  /* 2 */ MVT::i64, MVT::Other,
  /* 4 */ MVT::f16, MVT::Other,
  /* 6 */ MVT::f32, MVT::Other,
  /* 8 */ MVT::f64, MVT::Other,
  /* 10 */ MVT::v16i8, MVT::Other,
  /* 12 */ MVT::v4i8, MVT::v2i16, MVT::Other,
  /* 15 */ MVT::v8i16, MVT::v8f16, MVT::Other,
  /* 18 */ MVT::v4i32, MVT::v4f32, MVT::Other,
  /* 21 */ MVT::v2i64, MVT::v2f64, MVT::Other,
  /* 24 */ MVT::Untyped, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_32", "sub_64", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_hi_then_sub_32", "sub_32_sub_hi_then_sub_32", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_32
  LaneBitmask(0x0000000000000041), // sub_64
  LaneBitmask(0x0000000000000002), // sub_dsp16_19
  LaneBitmask(0x0000000000000004), // sub_dsp20
  LaneBitmask(0x0000000000000008), // sub_dsp21
  LaneBitmask(0x0000000000000010), // sub_dsp22
  LaneBitmask(0x0000000000000020), // sub_dsp23
  LaneBitmask(0x0000000000000040), // sub_hi
  LaneBitmask(0x0000000000000001), // sub_lo
  LaneBitmask(0x0000000000000040), // sub_hi_then_sub_32
  LaneBitmask(0x0000000000000041), // sub_32_sub_hi_then_sub_32
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 16, 16, 128, /*VTLists+*/4 },    // MSA128F16
  { 32, 32, 32, /*VTLists+*/0 },    // CCR
  { 32, 32, 32, /*VTLists+*/0 },    // COP0
  { 32, 32, 32, /*VTLists+*/0 },    // COP2
  { 32, 32, 32, /*VTLists+*/0 },    // COP3
  { 32, 32, 32, /*VTLists+*/12 },    // DSPR
  { 32, 32, 32, /*VTLists+*/6 },    // FGR32
  { 32, 32, 32, /*VTLists+*/0 },    // FGRCC
  { 32, 32, 32, /*VTLists+*/0 },    // GPR32
  { 32, 32, 32, /*VTLists+*/0 },    // HWRegs
  { 32, 32, 32, /*VTLists+*/0 },    // MSACtrl
  { 32, 32, 32, /*VTLists+*/0 },    // GPR32NONZERO
  { 32, 32, 32, /*VTLists+*/0 },    // CPU16RegsPlusSP
  { 32, 32, 32, /*VTLists+*/0 },    // CPU16Regs
  { 32, 32, 32, /*VTLists+*/0 },    // FCC
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/0 },    // CPU16Regs_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/0 },    // GPR32NONZERO_and_GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/0 },    // CPU16Regs_and_GPRMM16MoveP
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16MoveP_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/0 },    // HI32DSP
  { 32, 32, 32, /*VTLists+*/0 },    // LO32DSP
  { 32, 32, 32, /*VTLists+*/0 },    // CPU16Regs_and_GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16MovePPairFirst
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
  { 32, 32, 32, /*VTLists+*/0 },    // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
  { 32, 32, 32, /*VTLists+*/0 },    // CPURAReg
  { 32, 32, 32, /*VTLists+*/0 },    // CPUSPReg
  { 32, 32, 32, /*VTLists+*/12 },    // DSPCC
  { 32, 32, 32, /*VTLists+*/0 },    // GP32
  { 32, 32, 32, /*VTLists+*/0 },    // GPR32ZERO
  { 32, 32, 32, /*VTLists+*/0 },    // HI32
  { 32, 32, 32, /*VTLists+*/0 },    // LO32
  { 32, 32, 32, /*VTLists+*/0 },    // SP32
  { 64, 64, 64, /*VTLists+*/8 },    // FGR64
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPR32NONZERO
  { 64, 64, 64, /*VTLists+*/8 },    // AFGR64
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_CPU16RegsPlusSP
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_CPU16Regs
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/24 },    // ACC64DSP
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
  { 64, 64, 64, /*VTLists+*/2 },    // OCTEON_MPL
  { 64, 64, 64, /*VTLists+*/2 },    // OCTEON_P
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
  { 64, 64, 64, /*VTLists+*/24 },    // ACC64
  { 64, 64, 64, /*VTLists+*/2 },    // GP64
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_CPURAReg
  { 64, 64, 64, /*VTLists+*/2 },    // GPR64_with_sub_32_in_GPR32ZERO
  { 64, 64, 64, /*VTLists+*/2 },    // HI64
  { 64, 64, 64, /*VTLists+*/2 },    // LO64
  { 64, 64, 64, /*VTLists+*/2 },    // SP64
  { 128, 128, 128, /*VTLists+*/10 },    // MSA128B
  { 128, 128, 128, /*VTLists+*/21 },    // MSA128D
  { 128, 128, 128, /*VTLists+*/15 },    // MSA128H
  { 128, 128, 128, /*VTLists+*/18 },    // MSA128W
  { 128, 128, 128, /*VTLists+*/18 },    // MSA128WEvens
  { 128, 128, 128, /*VTLists+*/24 },    // ACC128
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t MSA128F16SubClassMask[] = {
  0x00000001, 0x00000000, 0x0000001f, 
};

static const uint32_t CCRSubClassMask[] = {
  0x00000002, 0x00000000, 0x00000000, 
};

static const uint32_t COP0SubClassMask[] = {
  0x00000004, 0x00000000, 0x00000000, 
};

static const uint32_t COP2SubClassMask[] = {
  0x00000008, 0x00000000, 0x00000000, 
};

static const uint32_t COP3SubClassMask[] = {
  0x00000010, 0x00000000, 0x00000000, 
};

static const uint32_t DSPRSubClassMask[] = {
  0x7e7fb920, 0x00000013, 0x00000000, 
  0x00000000, 0x9d3efec0, 0x00000000, // sub_32
};

static const uint32_t FGR32SubClassMask[] = {
  0x000000c0, 0x00000000, 0x00000000, 
  0x00000000, 0x00000100, 0x00000000, // sub_hi
  0x00000001, 0x00000120, 0x0000001f, // sub_lo
};

static const uint32_t FGRCCSubClassMask[] = {
  0x000000c0, 0x00000000, 0x00000000, 
  0x00000000, 0x00000100, 0x00000000, // sub_hi
  0x00000001, 0x00000120, 0x0000001f, // sub_lo
};

static const uint32_t GPR32SubClassMask[] = {
  0x7e7fb900, 0x00000013, 0x00000000, 
  0x00000000, 0x9d3efec0, 0x00000000, // sub_32
};

static const uint32_t HWRegsSubClassMask[] = {
  0x00000200, 0x00000000, 0x00000000, 
};

static const uint32_t MSACtrlSubClassMask[] = {
  0x00000400, 0x00000000, 0x00000000, 
};

static const uint32_t GPR32NONZEROSubClassMask[] = {
  0x7e3cb800, 0x00000011, 0x00000000, 
  0x00000000, 0x8d3ae680, 0x00000000, // sub_32
};

static const uint32_t CPU16RegsPlusSPSubClassMask[] = {
  0x5e24b000, 0x00000010, 0x00000000, 
  0x00000000, 0x813a2600, 0x00000000, // sub_32
};

static const uint32_t CPU16RegsSubClassMask[] = {
  0x1e24a000, 0x00000000, 0x00000000, 
  0x00000000, 0x013a2400, 0x00000000, // sub_32
};

static const uint32_t FCCSubClassMask[] = {
  0x00004000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRMM16SubClassMask[] = {
  0x1e248000, 0x00000000, 0x00000000, 
  0x00000000, 0x013a2400, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePSubClassMask[] = {
  0x08690000, 0x00000002, 0x00000000, 
  0x00000000, 0x10264800, 0x00000000, // sub_32
};

static const uint32_t GPRMM16ZeroSubClassMask[] = {
  0x1e460000, 0x00000002, 0x00000000, 
  0x00000000, 0x113c3000, 0x00000000, // sub_32
};

static const uint32_t CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x1e040000, 0x00000000, 0x00000000, 
  0x00000000, 0x01382000, 0x00000000, // sub_32
};

static const uint32_t GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
  0x08280000, 0x00000000, 0x00000000, 
  0x00000000, 0x00224000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePPairSecondSubClassMask[] = {
  0x12100000, 0x00000000, 0x00000000, 
  0x00000000, 0x01088000, 0x00000000, // sub_32
};

static const uint32_t CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
  0x08200000, 0x00000000, 0x00000000, 
  0x00000000, 0x00220000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
  0x08400000, 0x00000002, 0x00000000, 
  0x00000000, 0x10240000, 0x00000000, // sub_32
};

static const uint32_t HI32DSPSubClassMask[] = {
  0x00800000, 0x00000004, 0x00000000, 
  0x00000000, 0x20000000, 0x00000000, // sub_32
  0x00000000, 0x02010000, 0x00000000, // sub_hi
  0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
};

static const uint32_t LO32DSPSubClassMask[] = {
  0x01000000, 0x00000008, 0x00000000, 
  0x00000000, 0x40000000, 0x00000020, // sub_32
  0x00000000, 0x02010000, 0x00000000, // sub_lo
};

static const uint32_t CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x12000000, 0x00000000, 0x00000000, 
  0x00000000, 0x01080000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePPairFirstSubClassMask[] = {
  0x14000000, 0x00000000, 0x00000000, 
  0x00000000, 0x01100000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x08000000, 0x00000000, 0x00000000, 
  0x00000000, 0x00200000, 0x00000000, // sub_32
};

static const uint32_t GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x10000000, 0x00000000, 0x00000000, 
  0x00000000, 0x01000000, 0x00000000, // sub_32
};

static const uint32_t CPURARegSubClassMask[] = {
  0x20000000, 0x00000000, 0x00000000, 
  0x00000000, 0x08000000, 0x00000000, // sub_32
};

static const uint32_t CPUSPRegSubClassMask[] = {
  0x40000000, 0x00000010, 0x00000000, 
  0x00000000, 0x80000000, 0x00000000, // sub_32
};

static const uint32_t DSPCCSubClassMask[] = {
  0x80000000, 0x00000000, 0x00000000, 
};

static const uint32_t GP32SubClassMask[] = {
  0x00000000, 0x00000001, 0x00000000, 
  0x00000000, 0x04000000, 0x00000000, // sub_32
};

static const uint32_t GPR32ZEROSubClassMask[] = {
  0x00000000, 0x00000002, 0x00000000, 
  0x00000000, 0x10000000, 0x00000000, // sub_32
};

static const uint32_t HI32SubClassMask[] = {
  0x00000000, 0x00000004, 0x00000000, 
  0x00000000, 0x20000000, 0x00000000, // sub_32
  0x00000000, 0x02000000, 0x00000000, // sub_hi
  0x00000000, 0x00000000, 0x00000020, // sub_hi_then_sub_32
};

static const uint32_t LO32SubClassMask[] = {
  0x00000000, 0x00000008, 0x00000000, 
  0x00000000, 0x40000000, 0x00000020, // sub_32
  0x00000000, 0x02000000, 0x00000000, // sub_lo
};

static const uint32_t SP32SubClassMask[] = {
  0x00000000, 0x00000010, 0x00000000, 
  0x00000000, 0x80000000, 0x00000000, // sub_32
};

static const uint32_t FGR64SubClassMask[] = {
  0x00000000, 0x00000020, 0x00000000, 
  0x00000001, 0x00000000, 0x0000001f, // sub_64
};

static const uint32_t GPR64SubClassMask[] = {
  0x00000000, 0x9d3efec0, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPR32NONZEROSubClassMask[] = {
  0x00000000, 0x8d3ae680, 0x00000000, 
};

static const uint32_t AFGR64SubClassMask[] = {
  0x00000000, 0x00000100, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask[] = {
  0x00000000, 0x813a2600, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16RegsSubClassMask[] = {
  0x00000000, 0x013a2400, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePSubClassMask[] = {
  0x00000000, 0x10264800, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x113c3000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x01382000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask[] = {
  0x00000000, 0x00224000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask[] = {
  0x00000000, 0x01088000, 0x00000000, 
};

static const uint32_t ACC64DSPSubClassMask[] = {
  0x00000000, 0x02010000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
};

static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask[] = {
  0x00000000, 0x00220000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x10240000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x00000000, 0x01080000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask[] = {
  0x00000000, 0x01100000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask[] = {
  0x00000000, 0x00200000, 0x00000000, 
};

static const uint32_t OCTEON_MPLSubClassMask[] = {
  0x00000000, 0x00400000, 0x00000000, 
};

static const uint32_t OCTEON_PSubClassMask[] = {
  0x00000000, 0x00800000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask[] = {
  0x00000000, 0x01000000, 0x00000000, 
};

static const uint32_t ACC64SubClassMask[] = {
  0x00000000, 0x02000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000020, // sub_32_sub_hi_then_sub_32
};

static const uint32_t GP64SubClassMask[] = {
  0x00000000, 0x04000000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_CPURARegSubClassMask[] = {
  0x00000000, 0x08000000, 0x00000000, 
};

static const uint32_t GPR64_with_sub_32_in_GPR32ZEROSubClassMask[] = {
  0x00000000, 0x10000000, 0x00000000, 
};

static const uint32_t HI64SubClassMask[] = {
  0x00000000, 0x20000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000020, // sub_hi
};

static const uint32_t LO64SubClassMask[] = {
  0x00000000, 0x40000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000020, // sub_lo
};

static const uint32_t SP64SubClassMask[] = {
  0x00000000, 0x80000000, 0x00000000, 
};

static const uint32_t MSA128BSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000001f, 
};

static const uint32_t MSA128DSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000001f, 
};

static const uint32_t MSA128HSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000001f, 
};

static const uint32_t MSA128WSubClassMask[] = {
  0x00000000, 0x00000000, 0x0000001f, 
};

static const uint32_t MSA128WEvensSubClassMask[] = {
  0x00000000, 0x00000000, 0x00000010, 
};

static const uint32_t ACC128SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000020, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 0,
  /* 2 */ 2, 0,
  /* 4 */ 8, 0,
  /* 6 */ 1, 9, 0,
  /* 9 */ 8, 9, 0,
  /* 12 */ 1, 8, 10, 0,
  /* 16 */ 11, 0,
};

static const TargetRegisterClass *const FGR32Superclasses[] = {
  &Mips::FGRCCRegClass,
  nullptr
};

static const TargetRegisterClass *const FGRCCSuperclasses[] = {
  &Mips::FGR32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPR32Superclasses[] = {
  &Mips::DSPRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  nullptr
};

static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16Superclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  nullptr
};

static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  &Mips::GPRMM16RegClass,
  &Mips::GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::GPRMM16MovePRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  &Mips::GPRMM16RegClass,
  &Mips::GPRMM16MovePRegClass,
  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPRMM16MovePRegClass,
  &Mips::GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  &Mips::GPRMM16RegClass,
  &Mips::GPRMM16ZeroRegClass,
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
  &Mips::GPRMM16MovePPairSecondRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  &Mips::GPRMM16RegClass,
  &Mips::GPRMM16ZeroRegClass,
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  &Mips::GPRMM16RegClass,
  &Mips::GPRMM16MovePRegClass,
  &Mips::GPRMM16ZeroRegClass,
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
  &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
  &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPU16RegsRegClass,
  &Mips::GPRMM16RegClass,
  &Mips::GPRMM16ZeroRegClass,
  &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
  &Mips::GPRMM16MovePPairSecondRegClass,
  &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
  &Mips::GPRMM16MovePPairFirstRegClass,
  nullptr
};

static const TargetRegisterClass *const CPURARegSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GP32Superclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPRMM16MovePRegClass,
  &Mips::GPRMM16ZeroRegClass,
  &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const HI32Superclasses[] = {
  &Mips::HI32DSPRegClass,
  nullptr
};

static const TargetRegisterClass *const LO32Superclasses[] = {
  &Mips::LO32DSPRegClass,
  nullptr
};

static const TargetRegisterClass *const SP32Superclasses[] = {
  &Mips::DSPRRegClass,
  &Mips::GPR32RegClass,
  &Mips::GPR32NONZERORegClass,
  &Mips::CPU16RegsPlusSPRegClass,
  &Mips::CPUSPRegRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
  &Mips::GPR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
  &Mips::GPR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
  &Mips::GPR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
  &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
  nullptr
};

static const TargetRegisterClass *const ACC64Superclasses[] = {
  &Mips::ACC64DSPRegClass,
  nullptr
};

static const TargetRegisterClass *const GP64Superclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  nullptr
};

static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
  &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
  nullptr
};

static const TargetRegisterClass *const SP64Superclasses[] = {
  &Mips::GPR64RegClass,
  &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
  &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
  nullptr
};

static const TargetRegisterClass *const MSA128BSuperclasses[] = {
  &Mips::MSA128F16RegClass,
  &Mips::MSA128DRegClass,
  &Mips::MSA128HRegClass,
  &Mips::MSA128WRegClass,
  nullptr
};

static const TargetRegisterClass *const MSA128DSuperclasses[] = {
  &Mips::MSA128F16RegClass,
  &Mips::MSA128BRegClass,
  &Mips::MSA128HRegClass,
  &Mips::MSA128WRegClass,
  nullptr
};

static const TargetRegisterClass *const MSA128HSuperclasses[] = {
  &Mips::MSA128F16RegClass,
  &Mips::MSA128BRegClass,
  &Mips::MSA128DRegClass,
  &Mips::MSA128WRegClass,
  nullptr
};

static const TargetRegisterClass *const MSA128WSuperclasses[] = {
  &Mips::MSA128F16RegClass,
  &Mips::MSA128BRegClass,
  &Mips::MSA128DRegClass,
  &Mips::MSA128HRegClass,
  nullptr
};

static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
  &Mips::MSA128F16RegClass,
  &Mips::MSA128BRegClass,
  &Mips::MSA128DRegClass,
  &Mips::MSA128HRegClass,
  &Mips::MSA128WRegClass,
  nullptr
};


static inline unsigned FGR32AltOrderSelect(const MachineFunction &MF) {
    const auto & S = MF.getSubtarget<MipsSubtarget>();
    return S.isABI_O32() && !S.useOddSPReg();
  }

static ArrayRef<MCPhysReg> FGR32GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { Mips::F0, Mips::F2, Mips::F4, Mips::F6, Mips::F8, Mips::F10, Mips::F12, Mips::F14, Mips::F16, Mips::F18, Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30 };
  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = FGR32AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned FGR64AltOrderSelect(const MachineFunction &MF) {
    const auto & S = MF.getSubtarget<MipsSubtarget>();
    return S.isABI_O32() && !S.useOddSPReg();
  }

static ArrayRef<MCPhysReg> FGR64GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { Mips::D0_64, Mips::D2_64, Mips::D4_64, Mips::D6_64, Mips::D8_64, Mips::D10_64, Mips::D12_64, Mips::D14_64, Mips::D16_64, Mips::D18_64, Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64 };
  const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = FGR64AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

namespace Mips {   // Register class instances
  extern const TargetRegisterClass MSA128F16RegClass = {
    &MipsMCRegisterClasses[MSA128F16RegClassID],
    MSA128F16SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CCRRegClass = {
    &MipsMCRegisterClasses[CCRRegClassID],
    CCRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass COP0RegClass = {
    &MipsMCRegisterClasses[COP0RegClassID],
    COP0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass COP2RegClass = {
    &MipsMCRegisterClasses[COP2RegClassID],
    COP2SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass COP3RegClass = {
    &MipsMCRegisterClasses[COP3RegClassID],
    COP3SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DSPRRegClass = {
    &MipsMCRegisterClasses[DSPRRegClassID],
    DSPRSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FGR32RegClass = {
    &MipsMCRegisterClasses[FGR32RegClassID],
    FGR32SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FGR32Superclasses,
    FGR32GetRawAllocationOrder
  };

  extern const TargetRegisterClass FGRCCRegClass = {
    &MipsMCRegisterClasses[FGRCCRegClassID],
    FGRCCSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FGRCCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR32RegClass = {
    &MipsMCRegisterClasses[GPR32RegClassID],
    GPR32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass HWRegsRegClass = {
    &MipsMCRegisterClasses[HWRegsRegClassID],
    HWRegsSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass MSACtrlRegClass = {
    &MipsMCRegisterClasses[MSACtrlRegClassID],
    MSACtrlSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPR32NONZERORegClass = {
    &MipsMCRegisterClasses[GPR32NONZERORegClassID],
    GPR32NONZEROSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32NONZEROSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
    &MipsMCRegisterClasses[CPU16RegsPlusSPRegClassID],
    CPU16RegsPlusSPSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16RegsPlusSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CPU16RegsRegClass = {
    &MipsMCRegisterClasses[CPU16RegsRegClassID],
    CPU16RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FCCRegClass = {
    &MipsMCRegisterClasses[FCCRegClassID],
    FCCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16RegClass = {
    &MipsMCRegisterClasses[GPRMM16RegClassID],
    GPRMM16SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePRegClassID],
    GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPRMM16ZeroRegClassID],
    GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16ZeroRegClassID],
    CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16Regs_and_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR32NONZERO_and_GPRMM16MovePRegClassID],
    GPR32NONZERO_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32NONZERO_and_GPRMM16MovePSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePPairSecondRegClassID],
    GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePPairSecondSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePRegClassID],
    CPU16Regs_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16Regs_and_GPRMM16MovePSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
    GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass HI32DSPRegClass = {
    &MipsMCRegisterClasses[HI32DSPRegClassID],
    HI32DSPSubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LO32DSPRegClass = {
    &MipsMCRegisterClasses[LO32DSPRegClassID],
    LO32DSPSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
    CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePPairFirstRegClassID],
    GPRMM16MovePPairFirstSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePPairFirstSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CPURARegRegClass = {
    &MipsMCRegisterClasses[CPURARegRegClassID],
    CPURARegSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPURARegSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CPUSPRegRegClass = {
    &MipsMCRegisterClasses[CPUSPRegRegClassID],
    CPUSPRegSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    CPUSPRegSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DSPCCRegClass = {
    &MipsMCRegisterClasses[DSPCCRegClassID],
    DSPCCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GP32RegClass = {
    &MipsMCRegisterClasses[GP32RegClassID],
    GP32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GP32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR32ZERORegClass = {
    &MipsMCRegisterClasses[GPR32ZERORegClassID],
    GPR32ZEROSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR32ZEROSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass HI32RegClass = {
    &MipsMCRegisterClasses[HI32RegClassID],
    HI32SubClassMask,
    SuperRegIdxSeqs + 12,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    HI32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass LO32RegClass = {
    &MipsMCRegisterClasses[LO32RegClassID],
    LO32SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    LO32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass SP32RegClass = {
    &MipsMCRegisterClasses[SP32RegClassID],
    SP32SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SP32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass FGR64RegClass = {
    &MipsMCRegisterClasses[FGR64RegClassID],
    FGR64SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    FGR64GetRawAllocationOrder
  };

  extern const TargetRegisterClass GPR64RegClass = {
    &MipsMCRegisterClasses[GPR64RegClassID],
    GPR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERORegClassID],
    GPR64_with_sub_32_in_GPR32NONZEROSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPR32NONZEROSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass AFGR64RegClass = {
    &MipsMCRegisterClasses[AFGR64RegClassID],
    AFGR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID],
    GPR64_with_sub_32_in_CPU16RegsPlusSPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16RegsRegClassID],
    GPR64_with_sub_32_in_CPU16RegsSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClassID],
    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass ACC64DSPRegClass = {
    &MipsMCRegisterClasses[ACC64DSPRegClassID],
    ACC64DSPSubClassMask,
    SuperRegIdxSeqs + 16,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID],
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClassID],
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID],
    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass OCTEON_MPLRegClass = {
    &MipsMCRegisterClasses[OCTEON_MPLRegClassID],
    OCTEON_MPLSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass OCTEON_PRegClass = {
    &MipsMCRegisterClasses[OCTEON_PRegClassID],
    OCTEON_PSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClassID],
    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass ACC64RegClass = {
    &MipsMCRegisterClasses[ACC64RegClassID],
    ACC64SubClassMask,
    SuperRegIdxSeqs + 16,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    ACC64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GP64RegClass = {
    &MipsMCRegisterClasses[GP64RegClassID],
    GP64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GP64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_CPURARegRegClassID],
    GPR64_with_sub_32_in_CPURARegSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_CPURARegSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
    &MipsMCRegisterClasses[GPR64_with_sub_32_in_GPR32ZERORegClassID],
    GPR64_with_sub_32_in_GPR32ZEROSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPR64_with_sub_32_in_GPR32ZEROSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass HI64RegClass = {
    &MipsMCRegisterClasses[HI64RegClassID],
    HI64SubClassMask,
    SuperRegIdxSeqs + 4,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LO64RegClass = {
    &MipsMCRegisterClasses[LO64RegClassID],
    LO64SubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass SP64RegClass = {
    &MipsMCRegisterClasses[SP64RegClassID],
    SP64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SP64Superclasses,
    nullptr
  };

  extern const TargetRegisterClass MSA128BRegClass = {
    &MipsMCRegisterClasses[MSA128BRegClassID],
    MSA128BSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128BSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass MSA128DRegClass = {
    &MipsMCRegisterClasses[MSA128DRegClassID],
    MSA128DSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128DSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass MSA128HRegClass = {
    &MipsMCRegisterClasses[MSA128HRegClassID],
    MSA128HSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128HSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass MSA128WRegClass = {
    &MipsMCRegisterClasses[MSA128WRegClassID],
    MSA128WSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128WSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass MSA128WEvensRegClass = {
    &MipsMCRegisterClasses[MSA128WEvensRegClassID],
    MSA128WEvensSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    MSA128WEvensSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass ACC128RegClass = {
    &MipsMCRegisterClasses[ACC128RegClassID],
    ACC128SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000041),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

} // end namespace Mips

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &Mips::MSA128F16RegClass,
    &Mips::CCRRegClass,
    &Mips::COP0RegClass,
    &Mips::COP2RegClass,
    &Mips::COP3RegClass,
    &Mips::DSPRRegClass,
    &Mips::FGR32RegClass,
    &Mips::FGRCCRegClass,
    &Mips::GPR32RegClass,
    &Mips::HWRegsRegClass,
    &Mips::MSACtrlRegClass,
    &Mips::GPR32NONZERORegClass,
    &Mips::CPU16RegsPlusSPRegClass,
    &Mips::CPU16RegsRegClass,
    &Mips::FCCRegClass,
    &Mips::GPRMM16RegClass,
    &Mips::GPRMM16MovePRegClass,
    &Mips::GPRMM16ZeroRegClass,
    &Mips::CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::GPR32NONZERO_and_GPRMM16MovePRegClass,
    &Mips::GPRMM16MovePPairSecondRegClass,
    &Mips::CPU16Regs_and_GPRMM16MovePRegClass,
    &Mips::GPRMM16MoveP_and_GPRMM16ZeroRegClass,
    &Mips::HI32DSPRegClass,
    &Mips::LO32DSPRegClass,
    &Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
    &Mips::GPRMM16MovePPairFirstRegClass,
    &Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
    &Mips::CPURARegRegClass,
    &Mips::CPUSPRegRegClass,
    &Mips::DSPCCRegClass,
    &Mips::GP32RegClass,
    &Mips::GPR32ZERORegClass,
    &Mips::HI32RegClass,
    &Mips::LO32RegClass,
    &Mips::SP32RegClass,
    &Mips::FGR64RegClass,
    &Mips::GPR64RegClass,
    &Mips::GPR64_with_sub_32_in_GPR32NONZERORegClass,
    &Mips::AFGR64RegClass,
    &Mips::GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16RegsRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16ZeroRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass,
    &Mips::ACC64DSPRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass,
    &Mips::GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass,
    &Mips::OCTEON_MPLRegClass,
    &Mips::OCTEON_PRegClass,
    &Mips::GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass,
    &Mips::ACC64RegClass,
    &Mips::GP64RegClass,
    &Mips::GPR64_with_sub_32_in_CPURARegRegClass,
    &Mips::GPR64_with_sub_32_in_GPR32ZERORegClass,
    &Mips::HI64RegClass,
    &Mips::LO64RegClass,
    &Mips::SP64RegClass,
    &Mips::MSA128BRegClass,
    &Mips::MSA128DRegClass,
    &Mips::MSA128HRegClass,
    &Mips::MSA128WRegClass,
    &Mips::MSA128WEvensRegClass,
    &Mips::ACC128RegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, false, false, false, false, false, true, true, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc MipsRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned MipsGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[11] = {
    0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 
  };
  static const uint8_t Rows[2][11] = {
    { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
    { Mips::sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi_then_sub_32, Mips::sub_32, 0, 0, },
  };

  --IdxA; assert(IdxA < 11); (void) IdxA;
  --IdxB; assert(IdxB < 11);
  return Rows[RowMap[IdxA]][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 }  // Sequence 12
  };
  static const uint8_t CompositeSequences[] = {
    0, // to sub_32
    0, // to sub_64
    2, // to sub_dsp16_19
    4, // to sub_dsp20
    6, // to sub_dsp21
    8, // to sub_dsp22
    10, // to sub_dsp23
    12, // to sub_hi
    0, // to sub_lo
    12, // to sub_hi_then_sub_32
    0 // to sub_32_sub_hi_then_sub_32
  };

LaneBitmask MipsGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask MipsGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 11 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[70][11] = {
    { // MSA128F16
      0,  // sub_32
      1,  // sub_64 -> MSA128F16
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      1,  // sub_hi -> MSA128F16
      1,  // sub_lo -> MSA128F16
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CCR
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // COP0
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // COP2
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // COP3
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // DSPR
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // FGR32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // FGRCC
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // HWRegs
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // MSACtrl
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR32NONZERO
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPU16RegsPlusSP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // FCC
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MoveP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16Zero
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs_and_GPRMM16Zero
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR32NONZERO_and_GPRMM16MoveP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MovePPairSecond
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs_and_GPRMM16MoveP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MoveP_and_GPRMM16Zero
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // HI32DSP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // LO32DSP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs_and_GPRMM16MovePPairSecond
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MovePPairFirst
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPURAReg
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // CPUSPReg
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // DSPCC
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GP32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR32ZERO
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // HI32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // LO32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // SP32
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // FGR64
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      38, // sub_hi -> FGR64
      38, // sub_lo -> FGR64
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64
      39, // sub_32 -> GPR64
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPR32NONZERO
      40, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // AFGR64
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      41, // sub_hi -> AFGR64
      41, // sub_lo -> AFGR64
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16RegsPlusSP
      42, // sub_32 -> GPR64_with_sub_32_in_CPU16RegsPlusSP
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs
      43, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MoveP
      44, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16Zero
      45, // sub_32 -> GPR64_with_sub_32_in_GPRMM16Zero
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
      46, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
      47, // sub_32 -> GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
      48, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairSecond
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // ACC64DSP
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      49, // sub_hi -> ACC64DSP
      49, // sub_lo -> ACC64DSP
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
      50, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
      51, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
      52, // sub_32 -> GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
      53, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      54, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // OCTEON_MPL
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // OCTEON_P
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      57, // sub_32 -> GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // ACC64
      0,  // sub_32
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      58, // sub_hi -> ACC64
      58, // sub_lo -> ACC64
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GP64
      59, // sub_32 -> GP64
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPURAReg
      60, // sub_32 -> GPR64_with_sub_32_in_CPURAReg
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPR32ZERO
      61, // sub_32 -> GPR64_with_sub_32_in_GPR32ZERO
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // HI64
      62, // sub_32 -> HI64
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // LO64
      63, // sub_32 -> LO64
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // SP64
      64, // sub_32 -> SP64
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      0,  // sub_hi
      0,  // sub_lo
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // MSA128B
      0,  // sub_32
      65, // sub_64 -> MSA128B
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      65, // sub_hi -> MSA128B
      65, // sub_lo -> MSA128B
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // MSA128D
      0,  // sub_32
      66, // sub_64 -> MSA128D
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      66, // sub_hi -> MSA128D
      66, // sub_lo -> MSA128D
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // MSA128H
      0,  // sub_32
      67, // sub_64 -> MSA128H
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      67, // sub_hi -> MSA128H
      67, // sub_lo -> MSA128H
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // MSA128W
      0,  // sub_32
      68, // sub_64 -> MSA128W
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      68, // sub_hi -> MSA128W
      68, // sub_lo -> MSA128W
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // MSA128WEvens
      0,  // sub_32
      69, // sub_64 -> MSA128WEvens
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      69, // sub_hi -> MSA128WEvens
      69, // sub_lo -> MSA128WEvens
      0,  // sub_hi_then_sub_32
      0,  // sub_32_sub_hi_then_sub_32
    },
    { // ACC128
      70, // sub_32 -> ACC128
      0,  // sub_64
      0,  // sub_dsp16_19
      0,  // sub_dsp20
      0,  // sub_dsp21
      0,  // sub_dsp22
      0,  // sub_dsp23
      70, // sub_hi -> ACC128
      70, // sub_lo -> ACC128
      70, // sub_hi_then_sub_32 -> ACC128
      70, // sub_32_sub_hi_then_sub_32 -> ACC128
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *MipsGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[70][11] = {
    { // MSA128F16
      0,  // MSA128F16:sub_32
      38, // MSA128F16:sub_64 -> FGR64
      0,  // MSA128F16:sub_dsp16_19
      0,  // MSA128F16:sub_dsp20
      0,  // MSA128F16:sub_dsp21
      0,  // MSA128F16:sub_dsp22
      0,  // MSA128F16:sub_dsp23
      0,  // MSA128F16:sub_hi
      7,  // MSA128F16:sub_lo -> FGR32
      0,  // MSA128F16:sub_hi_then_sub_32
      0,  // MSA128F16:sub_32_sub_hi_then_sub_32
    },
    { // CCR
      0,  // CCR:sub_32
      0,  // CCR:sub_64
      0,  // CCR:sub_dsp16_19
      0,  // CCR:sub_dsp20
      0,  // CCR:sub_dsp21
      0,  // CCR:sub_dsp22
      0,  // CCR:sub_dsp23
      0,  // CCR:sub_hi
      0,  // CCR:sub_lo
      0,  // CCR:sub_hi_then_sub_32
      0,  // CCR:sub_32_sub_hi_then_sub_32
    },
    { // COP0
      0,  // COP0:sub_32
      0,  // COP0:sub_64
      0,  // COP0:sub_dsp16_19
      0,  // COP0:sub_dsp20
      0,  // COP0:sub_dsp21
      0,  // COP0:sub_dsp22
      0,  // COP0:sub_dsp23
      0,  // COP0:sub_hi
      0,  // COP0:sub_lo
      0,  // COP0:sub_hi_then_sub_32
      0,  // COP0:sub_32_sub_hi_then_sub_32
    },
    { // COP2
      0,  // COP2:sub_32
      0,  // COP2:sub_64
      0,  // COP2:sub_dsp16_19
      0,  // COP2:sub_dsp20
      0,  // COP2:sub_dsp21
      0,  // COP2:sub_dsp22
      0,  // COP2:sub_dsp23
      0,  // COP2:sub_hi
      0,  // COP2:sub_lo
      0,  // COP2:sub_hi_then_sub_32
      0,  // COP2:sub_32_sub_hi_then_sub_32
    },
    { // COP3
      0,  // COP3:sub_32
      0,  // COP3:sub_64
      0,  // COP3:sub_dsp16_19
      0,  // COP3:sub_dsp20
      0,  // COP3:sub_dsp21
      0,  // COP3:sub_dsp22
      0,  // COP3:sub_dsp23
      0,  // COP3:sub_hi
      0,  // COP3:sub_lo
      0,  // COP3:sub_hi_then_sub_32
      0,  // COP3:sub_32_sub_hi_then_sub_32
    },
    { // DSPR
      0,  // DSPR:sub_32
      0,  // DSPR:sub_64
      0,  // DSPR:sub_dsp16_19
      0,  // DSPR:sub_dsp20
      0,  // DSPR:sub_dsp21
      0,  // DSPR:sub_dsp22
      0,  // DSPR:sub_dsp23
      0,  // DSPR:sub_hi
      0,  // DSPR:sub_lo
      0,  // DSPR:sub_hi_then_sub_32
      0,  // DSPR:sub_32_sub_hi_then_sub_32
    },
    { // FGR32
      0,  // FGR32:sub_32
      0,  // FGR32:sub_64
      0,  // FGR32:sub_dsp16_19
      0,  // FGR32:sub_dsp20
      0,  // FGR32:sub_dsp21
      0,  // FGR32:sub_dsp22
      0,  // FGR32:sub_dsp23
      0,  // FGR32:sub_hi
      0,  // FGR32:sub_lo
      0,  // FGR32:sub_hi_then_sub_32
      0,  // FGR32:sub_32_sub_hi_then_sub_32
    },
    { // FGRCC
      0,  // FGRCC:sub_32
      0,  // FGRCC:sub_64
      0,  // FGRCC:sub_dsp16_19
      0,  // FGRCC:sub_dsp20
      0,  // FGRCC:sub_dsp21
      0,  // FGRCC:sub_dsp22
      0,  // FGRCC:sub_dsp23
      0,  // FGRCC:sub_hi
      0,  // FGRCC:sub_lo
      0,  // FGRCC:sub_hi_then_sub_32
      0,  // FGRCC:sub_32_sub_hi_then_sub_32
    },
    { // GPR32
      0,  // GPR32:sub_32
      0,  // GPR32:sub_64
      0,  // GPR32:sub_dsp16_19
      0,  // GPR32:sub_dsp20
      0,  // GPR32:sub_dsp21
      0,  // GPR32:sub_dsp22
      0,  // GPR32:sub_dsp23
      0,  // GPR32:sub_hi
      0,  // GPR32:sub_lo
      0,  // GPR32:sub_hi_then_sub_32
      0,  // GPR32:sub_32_sub_hi_then_sub_32
    },
    { // HWRegs
      0,  // HWRegs:sub_32
      0,  // HWRegs:sub_64
      0,  // HWRegs:sub_dsp16_19
      0,  // HWRegs:sub_dsp20
      0,  // HWRegs:sub_dsp21
      0,  // HWRegs:sub_dsp22
      0,  // HWRegs:sub_dsp23
      0,  // HWRegs:sub_hi
      0,  // HWRegs:sub_lo
      0,  // HWRegs:sub_hi_then_sub_32
      0,  // HWRegs:sub_32_sub_hi_then_sub_32
    },
    { // MSACtrl
      0,  // MSACtrl:sub_32
      0,  // MSACtrl:sub_64
      0,  // MSACtrl:sub_dsp16_19
      0,  // MSACtrl:sub_dsp20
      0,  // MSACtrl:sub_dsp21
      0,  // MSACtrl:sub_dsp22
      0,  // MSACtrl:sub_dsp23
      0,  // MSACtrl:sub_hi
      0,  // MSACtrl:sub_lo
      0,  // MSACtrl:sub_hi_then_sub_32
      0,  // MSACtrl:sub_32_sub_hi_then_sub_32
    },
    { // GPR32NONZERO
      0,  // GPR32NONZERO:sub_32
      0,  // GPR32NONZERO:sub_64
      0,  // GPR32NONZERO:sub_dsp16_19
      0,  // GPR32NONZERO:sub_dsp20
      0,  // GPR32NONZERO:sub_dsp21
      0,  // GPR32NONZERO:sub_dsp22
      0,  // GPR32NONZERO:sub_dsp23
      0,  // GPR32NONZERO:sub_hi
      0,  // GPR32NONZERO:sub_lo
      0,  // GPR32NONZERO:sub_hi_then_sub_32
      0,  // GPR32NONZERO:sub_32_sub_hi_then_sub_32
    },
    { // CPU16RegsPlusSP
      0,  // CPU16RegsPlusSP:sub_32
      0,  // CPU16RegsPlusSP:sub_64
      0,  // CPU16RegsPlusSP:sub_dsp16_19
      0,  // CPU16RegsPlusSP:sub_dsp20
      0,  // CPU16RegsPlusSP:sub_dsp21
      0,  // CPU16RegsPlusSP:sub_dsp22
      0,  // CPU16RegsPlusSP:sub_dsp23
      0,  // CPU16RegsPlusSP:sub_hi
      0,  // CPU16RegsPlusSP:sub_lo
      0,  // CPU16RegsPlusSP:sub_hi_then_sub_32
      0,  // CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs
      0,  // CPU16Regs:sub_32
      0,  // CPU16Regs:sub_64
      0,  // CPU16Regs:sub_dsp16_19
      0,  // CPU16Regs:sub_dsp20
      0,  // CPU16Regs:sub_dsp21
      0,  // CPU16Regs:sub_dsp22
      0,  // CPU16Regs:sub_dsp23
      0,  // CPU16Regs:sub_hi
      0,  // CPU16Regs:sub_lo
      0,  // CPU16Regs:sub_hi_then_sub_32
      0,  // CPU16Regs:sub_32_sub_hi_then_sub_32
    },
    { // FCC
      0,  // FCC:sub_32
      0,  // FCC:sub_64
      0,  // FCC:sub_dsp16_19
      0,  // FCC:sub_dsp20
      0,  // FCC:sub_dsp21
      0,  // FCC:sub_dsp22
      0,  // FCC:sub_dsp23
      0,  // FCC:sub_hi
      0,  // FCC:sub_lo
      0,  // FCC:sub_hi_then_sub_32
      0,  // FCC:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16
      0,  // GPRMM16:sub_32
      0,  // GPRMM16:sub_64
      0,  // GPRMM16:sub_dsp16_19
      0,  // GPRMM16:sub_dsp20
      0,  // GPRMM16:sub_dsp21
      0,  // GPRMM16:sub_dsp22
      0,  // GPRMM16:sub_dsp23
      0,  // GPRMM16:sub_hi
      0,  // GPRMM16:sub_lo
      0,  // GPRMM16:sub_hi_then_sub_32
      0,  // GPRMM16:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MoveP
      0,  // GPRMM16MoveP:sub_32
      0,  // GPRMM16MoveP:sub_64
      0,  // GPRMM16MoveP:sub_dsp16_19
      0,  // GPRMM16MoveP:sub_dsp20
      0,  // GPRMM16MoveP:sub_dsp21
      0,  // GPRMM16MoveP:sub_dsp22
      0,  // GPRMM16MoveP:sub_dsp23
      0,  // GPRMM16MoveP:sub_hi
      0,  // GPRMM16MoveP:sub_lo
      0,  // GPRMM16MoveP:sub_hi_then_sub_32
      0,  // GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16Zero
      0,  // GPRMM16Zero:sub_32
      0,  // GPRMM16Zero:sub_64
      0,  // GPRMM16Zero:sub_dsp16_19
      0,  // GPRMM16Zero:sub_dsp20
      0,  // GPRMM16Zero:sub_dsp21
      0,  // GPRMM16Zero:sub_dsp22
      0,  // GPRMM16Zero:sub_dsp23
      0,  // GPRMM16Zero:sub_hi
      0,  // GPRMM16Zero:sub_lo
      0,  // GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs_and_GPRMM16Zero
      0,  // CPU16Regs_and_GPRMM16Zero:sub_32
      0,  // CPU16Regs_and_GPRMM16Zero:sub_64
      0,  // CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,  // CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,  // CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,  // CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,  // CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,  // CPU16Regs_and_GPRMM16Zero:sub_hi
      0,  // CPU16Regs_and_GPRMM16Zero:sub_lo
      0,  // CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,  // CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // GPR32NONZERO_and_GPRMM16MoveP
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_32
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_64
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_hi
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_lo
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,  // GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MovePPairSecond
      0,  // GPRMM16MovePPairSecond:sub_32
      0,  // GPRMM16MovePPairSecond:sub_64
      0,  // GPRMM16MovePPairSecond:sub_dsp16_19
      0,  // GPRMM16MovePPairSecond:sub_dsp20
      0,  // GPRMM16MovePPairSecond:sub_dsp21
      0,  // GPRMM16MovePPairSecond:sub_dsp22
      0,  // GPRMM16MovePPairSecond:sub_dsp23
      0,  // GPRMM16MovePPairSecond:sub_hi
      0,  // GPRMM16MovePPairSecond:sub_lo
      0,  // GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,  // GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs_and_GPRMM16MoveP
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_32
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_64
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_dsp20
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_dsp21
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_dsp22
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_dsp23
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_hi
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_lo
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,  // CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MoveP_and_GPRMM16Zero
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_32
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_64
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_hi
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_lo
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // HI32DSP
      0,  // HI32DSP:sub_32
      0,  // HI32DSP:sub_64
      0,  // HI32DSP:sub_dsp16_19
      0,  // HI32DSP:sub_dsp20
      0,  // HI32DSP:sub_dsp21
      0,  // HI32DSP:sub_dsp22
      0,  // HI32DSP:sub_dsp23
      0,  // HI32DSP:sub_hi
      0,  // HI32DSP:sub_lo
      0,  // HI32DSP:sub_hi_then_sub_32
      0,  // HI32DSP:sub_32_sub_hi_then_sub_32
    },
    { // LO32DSP
      0,  // LO32DSP:sub_32
      0,  // LO32DSP:sub_64
      0,  // LO32DSP:sub_dsp16_19
      0,  // LO32DSP:sub_dsp20
      0,  // LO32DSP:sub_dsp21
      0,  // LO32DSP:sub_dsp22
      0,  // LO32DSP:sub_dsp23
      0,  // LO32DSP:sub_hi
      0,  // LO32DSP:sub_lo
      0,  // LO32DSP:sub_hi_then_sub_32
      0,  // LO32DSP:sub_32_sub_hi_then_sub_32
    },
    { // CPU16Regs_and_GPRMM16MovePPairSecond
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,  // CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MovePPairFirst
      0,  // GPRMM16MovePPairFirst:sub_32
      0,  // GPRMM16MovePPairFirst:sub_64
      0,  // GPRMM16MovePPairFirst:sub_dsp16_19
      0,  // GPRMM16MovePPairFirst:sub_dsp20
      0,  // GPRMM16MovePPairFirst:sub_dsp21
      0,  // GPRMM16MovePPairFirst:sub_dsp22
      0,  // GPRMM16MovePPairFirst:sub_dsp23
      0,  // GPRMM16MovePPairFirst:sub_hi
      0,  // GPRMM16MovePPairFirst:sub_lo
      0,  // GPRMM16MovePPairFirst:sub_hi_then_sub_32
      0,  // GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,  // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    { // CPURAReg
      0,  // CPURAReg:sub_32
      0,  // CPURAReg:sub_64
      0,  // CPURAReg:sub_dsp16_19
      0,  // CPURAReg:sub_dsp20
      0,  // CPURAReg:sub_dsp21
      0,  // CPURAReg:sub_dsp22
      0,  // CPURAReg:sub_dsp23
      0,  // CPURAReg:sub_hi
      0,  // CPURAReg:sub_lo
      0,  // CPURAReg:sub_hi_then_sub_32
      0,  // CPURAReg:sub_32_sub_hi_then_sub_32
    },
    { // CPUSPReg
      0,  // CPUSPReg:sub_32
      0,  // CPUSPReg:sub_64
      0,  // CPUSPReg:sub_dsp16_19
      0,  // CPUSPReg:sub_dsp20
      0,  // CPUSPReg:sub_dsp21
      0,  // CPUSPReg:sub_dsp22
      0,  // CPUSPReg:sub_dsp23
      0,  // CPUSPReg:sub_hi
      0,  // CPUSPReg:sub_lo
      0,  // CPUSPReg:sub_hi_then_sub_32
      0,  // CPUSPReg:sub_32_sub_hi_then_sub_32
    },
    { // DSPCC
      0,  // DSPCC:sub_32
      0,  // DSPCC:sub_64
      0,  // DSPCC:sub_dsp16_19
      0,  // DSPCC:sub_dsp20
      0,  // DSPCC:sub_dsp21
      0,  // DSPCC:sub_dsp22
      0,  // DSPCC:sub_dsp23
      0,  // DSPCC:sub_hi
      0,  // DSPCC:sub_lo
      0,  // DSPCC:sub_hi_then_sub_32
      0,  // DSPCC:sub_32_sub_hi_then_sub_32
    },
    { // GP32
      0,  // GP32:sub_32
      0,  // GP32:sub_64
      0,  // GP32:sub_dsp16_19
      0,  // GP32:sub_dsp20
      0,  // GP32:sub_dsp21
      0,  // GP32:sub_dsp22
      0,  // GP32:sub_dsp23
      0,  // GP32:sub_hi
      0,  // GP32:sub_lo
      0,  // GP32:sub_hi_then_sub_32
      0,  // GP32:sub_32_sub_hi_then_sub_32
    },
    { // GPR32ZERO
      0,  // GPR32ZERO:sub_32
      0,  // GPR32ZERO:sub_64
      0,  // GPR32ZERO:sub_dsp16_19
      0,  // GPR32ZERO:sub_dsp20
      0,  // GPR32ZERO:sub_dsp21
      0,  // GPR32ZERO:sub_dsp22
      0,  // GPR32ZERO:sub_dsp23
      0,  // GPR32ZERO:sub_hi
      0,  // GPR32ZERO:sub_lo
      0,  // GPR32ZERO:sub_hi_then_sub_32
      0,  // GPR32ZERO:sub_32_sub_hi_then_sub_32
    },
    { // HI32
      0,  // HI32:sub_32
      0,  // HI32:sub_64
      0,  // HI32:sub_dsp16_19
      0,  // HI32:sub_dsp20
      0,  // HI32:sub_dsp21
      0,  // HI32:sub_dsp22
      0,  // HI32:sub_dsp23
      0,  // HI32:sub_hi
      0,  // HI32:sub_lo
      0,  // HI32:sub_hi_then_sub_32
      0,  // HI32:sub_32_sub_hi_then_sub_32
    },
    { // LO32
      0,  // LO32:sub_32
      0,  // LO32:sub_64
      0,  // LO32:sub_dsp16_19
      0,  // LO32:sub_dsp20
      0,  // LO32:sub_dsp21
      0,  // LO32:sub_dsp22
      0,  // LO32:sub_dsp23
      0,  // LO32:sub_hi
      0,  // LO32:sub_lo
      0,  // LO32:sub_hi_then_sub_32
      0,  // LO32:sub_32_sub_hi_then_sub_32
    },
    { // SP32
      0,  // SP32:sub_32
      0,  // SP32:sub_64
      0,  // SP32:sub_dsp16_19
      0,  // SP32:sub_dsp20
      0,  // SP32:sub_dsp21
      0,  // SP32:sub_dsp22
      0,  // SP32:sub_dsp23
      0,  // SP32:sub_hi
      0,  // SP32:sub_lo
      0,  // SP32:sub_hi_then_sub_32
      0,  // SP32:sub_32_sub_hi_then_sub_32
    },
    { // FGR64
      0,  // FGR64:sub_32
      0,  // FGR64:sub_64
      0,  // FGR64:sub_dsp16_19
      0,  // FGR64:sub_dsp20
      0,  // FGR64:sub_dsp21
      0,  // FGR64:sub_dsp22
      0,  // FGR64:sub_dsp23
      0,  // FGR64:sub_hi
      7,  // FGR64:sub_lo -> FGR32
      0,  // FGR64:sub_hi_then_sub_32
      0,  // FGR64:sub_32_sub_hi_then_sub_32
    },
    { // GPR64
      6,  // GPR64:sub_32 -> DSPR
      0,  // GPR64:sub_64
      0,  // GPR64:sub_dsp16_19
      0,  // GPR64:sub_dsp20
      0,  // GPR64:sub_dsp21
      0,  // GPR64:sub_dsp22
      0,  // GPR64:sub_dsp23
      0,  // GPR64:sub_hi
      0,  // GPR64:sub_lo
      0,  // GPR64:sub_hi_then_sub_32
      0,  // GPR64:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPR32NONZERO
      12, // GPR64_with_sub_32_in_GPR32NONZERO:sub_32 -> GPR32NONZERO
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_64
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_lo
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPR32NONZERO:sub_32_sub_hi_then_sub_32
    },
    { // AFGR64
      0,  // AFGR64:sub_32
      0,  // AFGR64:sub_64
      0,  // AFGR64:sub_dsp16_19
      0,  // AFGR64:sub_dsp20
      0,  // AFGR64:sub_dsp21
      0,  // AFGR64:sub_dsp22
      0,  // AFGR64:sub_dsp23
      8,  // AFGR64:sub_hi -> FGRCC
      8,  // AFGR64:sub_lo -> FGRCC
      0,  // AFGR64:sub_hi_then_sub_32
      0,  // AFGR64:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16RegsPlusSP
      13, // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32 -> CPU16RegsPlusSP
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_64
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp20
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp21
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp22
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_dsp23
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_lo
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_CPU16RegsPlusSP:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs
      14, // GPR64_with_sub_32_in_CPU16Regs:sub_32 -> CPU16Regs
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_64
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_dsp20
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_dsp21
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_dsp22
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_dsp23
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_hi
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_lo
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_CPU16Regs:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MoveP
      17, // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32 -> GPRMM16MoveP
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16Zero
      18, // GPR64_with_sub_32_in_GPRMM16Zero:sub_32 -> GPRMM16Zero
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
      19, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32 -> CPU16Regs_and_GPRMM16Zero
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_64
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_lo
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
      20, // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32 -> GPR32NONZERO_and_GPRMM16MoveP
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_64
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_lo
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
      21, // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairSecond
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    { // ACC64DSP
      0,  // ACC64DSP:sub_32
      0,  // ACC64DSP:sub_64
      0,  // ACC64DSP:sub_dsp16_19
      0,  // ACC64DSP:sub_dsp20
      0,  // ACC64DSP:sub_dsp21
      0,  // ACC64DSP:sub_dsp22
      0,  // ACC64DSP:sub_dsp23
      24, // ACC64DSP:sub_hi -> HI32DSP
      25, // ACC64DSP:sub_lo -> LO32DSP
      0,  // ACC64DSP:sub_hi_then_sub_32
      0,  // ACC64DSP:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
      22, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32 -> CPU16Regs_and_GPRMM16MoveP
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_64
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp20
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp21
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp22
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_dsp23
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_lo
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
      23, // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_GPRMM16Zero
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
      26, // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32 -> CPU16Regs_and_GPRMM16MovePPairSecond
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_64
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp20
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp21
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp22
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_dsp23
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_lo
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
      27, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32 -> GPRMM16MovePPairFirst
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      28, // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32 -> GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero:sub_32_sub_hi_then_sub_32
    },
    { // OCTEON_MPL
      0,  // OCTEON_MPL:sub_32
      0,  // OCTEON_MPL:sub_64
      0,  // OCTEON_MPL:sub_dsp16_19
      0,  // OCTEON_MPL:sub_dsp20
      0,  // OCTEON_MPL:sub_dsp21
      0,  // OCTEON_MPL:sub_dsp22
      0,  // OCTEON_MPL:sub_dsp23
      0,  // OCTEON_MPL:sub_hi
      0,  // OCTEON_MPL:sub_lo
      0,  // OCTEON_MPL:sub_hi_then_sub_32
      0,  // OCTEON_MPL:sub_32_sub_hi_then_sub_32
    },
    { // OCTEON_P
      0,  // OCTEON_P:sub_32
      0,  // OCTEON_P:sub_64
      0,  // OCTEON_P:sub_dsp16_19
      0,  // OCTEON_P:sub_dsp20
      0,  // OCTEON_P:sub_dsp21
      0,  // OCTEON_P:sub_dsp22
      0,  // OCTEON_P:sub_dsp23
      0,  // OCTEON_P:sub_hi
      0,  // OCTEON_P:sub_lo
      0,  // OCTEON_P:sub_hi_then_sub_32
      0,  // OCTEON_P:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      29, // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32 -> GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_64
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_lo
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond:sub_32_sub_hi_then_sub_32
    },
    { // ACC64
      0,  // ACC64:sub_32
      0,  // ACC64:sub_64
      0,  // ACC64:sub_dsp16_19
      0,  // ACC64:sub_dsp20
      0,  // ACC64:sub_dsp21
      0,  // ACC64:sub_dsp22
      0,  // ACC64:sub_dsp23
      35, // ACC64:sub_hi -> HI32
      36, // ACC64:sub_lo -> LO32
      0,  // ACC64:sub_hi_then_sub_32
      0,  // ACC64:sub_32_sub_hi_then_sub_32
    },
    { // GP64
      33, // GP64:sub_32 -> GP32
      0,  // GP64:sub_64
      0,  // GP64:sub_dsp16_19
      0,  // GP64:sub_dsp20
      0,  // GP64:sub_dsp21
      0,  // GP64:sub_dsp22
      0,  // GP64:sub_dsp23
      0,  // GP64:sub_hi
      0,  // GP64:sub_lo
      0,  // GP64:sub_hi_then_sub_32
      0,  // GP64:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_CPURAReg
      30, // GPR64_with_sub_32_in_CPURAReg:sub_32 -> CPURAReg
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_64
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_dsp20
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_dsp21
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_dsp22
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_dsp23
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_hi
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_lo
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_CPURAReg:sub_32_sub_hi_then_sub_32
    },
    { // GPR64_with_sub_32_in_GPR32ZERO
      34, // GPR64_with_sub_32_in_GPR32ZERO:sub_32 -> GPR32ZERO
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_64
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp16_19
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp20
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp21
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp22
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_dsp23
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_hi
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_lo
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_hi_then_sub_32
      0,  // GPR64_with_sub_32_in_GPR32ZERO:sub_32_sub_hi_then_sub_32
    },
    { // HI64
      35, // HI64:sub_32 -> HI32
      0,  // HI64:sub_64
      0,  // HI64:sub_dsp16_19
      0,  // HI64:sub_dsp20
      0,  // HI64:sub_dsp21
      0,  // HI64:sub_dsp22
      0,  // HI64:sub_dsp23
      0,  // HI64:sub_hi
      0,  // HI64:sub_lo
      0,  // HI64:sub_hi_then_sub_32
      0,  // HI64:sub_32_sub_hi_then_sub_32
    },
    { // LO64
      36, // LO64:sub_32 -> LO32
      0,  // LO64:sub_64
      0,  // LO64:sub_dsp16_19
      0,  // LO64:sub_dsp20
      0,  // LO64:sub_dsp21
      0,  // LO64:sub_dsp22
      0,  // LO64:sub_dsp23
      0,  // LO64:sub_hi
      0,  // LO64:sub_lo
      0,  // LO64:sub_hi_then_sub_32
      0,  // LO64:sub_32_sub_hi_then_sub_32
    },
    { // SP64
      31, // SP64:sub_32 -> CPUSPReg
      0,  // SP64:sub_64
      0,  // SP64:sub_dsp16_19
      0,  // SP64:sub_dsp20
      0,  // SP64:sub_dsp21
      0,  // SP64:sub_dsp22
      0,  // SP64:sub_dsp23
      0,  // SP64:sub_hi
      0,  // SP64:sub_lo
      0,  // SP64:sub_hi_then_sub_32
      0,  // SP64:sub_32_sub_hi_then_sub_32
    },
    { // MSA128B
      0,  // MSA128B:sub_32
      38, // MSA128B:sub_64 -> FGR64
      0,  // MSA128B:sub_dsp16_19
      0,  // MSA128B:sub_dsp20
      0,  // MSA128B:sub_dsp21
      0,  // MSA128B:sub_dsp22
      0,  // MSA128B:sub_dsp23
      0,  // MSA128B:sub_hi
      7,  // MSA128B:sub_lo -> FGR32
      0,  // MSA128B:sub_hi_then_sub_32
      0,  // MSA128B:sub_32_sub_hi_then_sub_32
    },
    { // MSA128D
      0,  // MSA128D:sub_32
      38, // MSA128D:sub_64 -> FGR64
      0,  // MSA128D:sub_dsp16_19
      0,  // MSA128D:sub_dsp20
      0,  // MSA128D:sub_dsp21
      0,  // MSA128D:sub_dsp22
      0,  // MSA128D:sub_dsp23
      0,  // MSA128D:sub_hi
      7,  // MSA128D:sub_lo -> FGR32
      0,  // MSA128D:sub_hi_then_sub_32
      0,  // MSA128D:sub_32_sub_hi_then_sub_32
    },
    { // MSA128H
      0,  // MSA128H:sub_32
      38, // MSA128H:sub_64 -> FGR64
      0,  // MSA128H:sub_dsp16_19
      0,  // MSA128H:sub_dsp20
      0,  // MSA128H:sub_dsp21
      0,  // MSA128H:sub_dsp22
      0,  // MSA128H:sub_dsp23
      0,  // MSA128H:sub_hi
      7,  // MSA128H:sub_lo -> FGR32
      0,  // MSA128H:sub_hi_then_sub_32
      0,  // MSA128H:sub_32_sub_hi_then_sub_32
    },
    { // MSA128W
      0,  // MSA128W:sub_32
      38, // MSA128W:sub_64 -> FGR64
      0,  // MSA128W:sub_dsp16_19
      0,  // MSA128W:sub_dsp20
      0,  // MSA128W:sub_dsp21
      0,  // MSA128W:sub_dsp22
      0,  // MSA128W:sub_dsp23
      0,  // MSA128W:sub_hi
      7,  // MSA128W:sub_lo -> FGR32
      0,  // MSA128W:sub_hi_then_sub_32
      0,  // MSA128W:sub_32_sub_hi_then_sub_32
    },
    { // MSA128WEvens
      0,  // MSA128WEvens:sub_32
      38, // MSA128WEvens:sub_64 -> FGR64
      0,  // MSA128WEvens:sub_dsp16_19
      0,  // MSA128WEvens:sub_dsp20
      0,  // MSA128WEvens:sub_dsp21
      0,  // MSA128WEvens:sub_dsp22
      0,  // MSA128WEvens:sub_dsp23
      0,  // MSA128WEvens:sub_hi
      8,  // MSA128WEvens:sub_lo -> FGRCC
      0,  // MSA128WEvens:sub_hi_then_sub_32
      0,  // MSA128WEvens:sub_32_sub_hi_then_sub_32
    },
    { // ACC128
      36, // ACC128:sub_32 -> LO32
      0,  // ACC128:sub_64
      0,  // ACC128:sub_dsp16_19
      0,  // ACC128:sub_dsp20
      0,  // ACC128:sub_dsp21
      0,  // ACC128:sub_dsp22
      0,  // ACC128:sub_dsp23
      62, // ACC128:sub_hi -> HI64
      63, // ACC128:sub_lo -> LO64
      35, // ACC128:sub_hi_then_sub_32 -> HI32
      58, // ACC128:sub_32_sub_hi_then_sub_32 -> ACC64
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 11 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &MipsGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {2, 64},    // MSA128F16
    {0, 0},   // CCR
    {0, 0},   // COP0
    {0, 0},   // COP2
    {0, 0},   // COP3
    {1, 32},    // DSPR
    {1, 32},    // FGR32
    {1, 32},    // FGRCC
    {1, 32},    // GPR32
    {0, 0},   // HWRegs
    {0, 0},   // MSACtrl
    {1, 31},    // GPR32NONZERO
    {1, 9},   // CPU16RegsPlusSP
    {1, 8},   // CPU16Regs
    {0, 0},   // FCC
    {1, 8},   // GPRMM16
    {1, 8},   // GPRMM16MoveP
    {1, 8},   // GPRMM16Zero
    {1, 7},   // CPU16Regs_and_GPRMM16Zero
    {1, 7},   // GPR32NONZERO_and_GPRMM16MoveP
    {1, 5},   // GPRMM16MovePPairSecond
    {1, 4},   // CPU16Regs_and_GPRMM16MoveP
    {1, 4},   // GPRMM16MoveP_and_GPRMM16Zero
    {1, 4},   // HI32DSP
    {1, 4},   // LO32DSP
    {1, 3},   // CPU16Regs_and_GPRMM16MovePPairSecond
    {1, 3},   // GPRMM16MovePPairFirst
    {1, 3},   // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
    {1, 2},   // GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
    {1, 1},   // CPURAReg
    {1, 1},   // CPUSPReg
    {1, 1},   // DSPCC
    {1, 1},   // GP32
    {1, 1},   // GPR32ZERO
    {1, 1},   // HI32
    {1, 1},   // LO32
    {1, 1},   // SP32
    {2, 64},    // FGR64
    {1, 32},    // GPR64
    {1, 31},    // GPR64_with_sub_32_in_GPR32NONZERO
    {2, 32},    // AFGR64
    {1, 9},   // GPR64_with_sub_32_in_CPU16RegsPlusSP
    {1, 8},   // GPR64_with_sub_32_in_CPU16Regs
    {1, 8},   // GPR64_with_sub_32_in_GPRMM16MoveP
    {1, 8},   // GPR64_with_sub_32_in_GPRMM16Zero
    {1, 7},   // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero
    {1, 7},   // GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MoveP
    {1, 5},   // GPR64_with_sub_32_in_GPRMM16MovePPairSecond
    {2, 8},   // ACC64DSP
    {1, 4},   // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP
    {1, 4},   // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero
    {1, 3},   // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecond
    {1, 3},   // GPR64_with_sub_32_in_GPRMM16MovePPairFirst
    {1, 3},   // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero
    {0, 0},   // OCTEON_MPL
    {0, 0},   // OCTEON_P
    {1, 2},   // GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecond
    {2, 2},   // ACC64
    {1, 1},   // GP64
    {1, 1},   // GPR64_with_sub_32_in_CPURAReg
    {1, 1},   // GPR64_with_sub_32_in_GPR32ZERO
    {1, 1},   // HI64
    {1, 1},   // LO64
    {1, 1},   // SP64
    {2, 64},    // MSA128B
    {2, 64},    // MSA128D
    {2, 64},    // MSA128H
    {2, 64},    // MSA128W
    {2, 32},    // MSA128WEvens
    {2, 2},   // ACC128
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned MipsGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 321 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned MipsGenRegisterInfo::getNumRegPressureSets() const {
  return 20;
}

// Get the name of this register unit pressure set.
const char *MipsGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "DSPCC",
    "GPR32ZERO",
    "GPR64_with_sub_32_in_CPURAReg",
    "HI32",
    "GPRMM16MovePPairFirst",
    "CPU16Regs_and_GPRMM16MoveP",
    "HI32DSP",
    "LO32DSP",
    "GPRMM16MovePPairSecond",
    "GPRMM16MoveP",
    "ACC64DSP",
    "CPU16Regs",
    "GPRMM16Zero_with_GPRMM16MovePPairSecond",
    "CPU16Regs_with_GPRMM16MovePPairSecond",
    "CPU16Regs_with_GPRMM16MoveP",
    "DSPR",
    "FGR32",
    "MSA128WEvens",
    "FGR32_with_MSA128WEvens",
    "MSA128F16",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned MipsGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,    // 0: DSPCC
    1,    // 1: GPR32ZERO
    1,    // 2: GPR64_with_sub_32_in_CPURAReg
    2,    // 3: HI32
    3,    // 4: GPRMM16MovePPairFirst
    5,    // 5: CPU16Regs_and_GPRMM16MoveP
    5,    // 6: HI32DSP
    5,    // 7: LO32DSP
    6,    // 8: GPRMM16MovePPairSecond
    8,    // 9: GPRMM16MoveP
    8,    // 10: ACC64DSP
    10,   // 11: CPU16Regs
    10,   // 12: GPRMM16Zero_with_GPRMM16MovePPairSecond
    11,   // 13: CPU16Regs_with_GPRMM16MovePPairSecond
    13,   // 14: CPU16Regs_with_GPRMM16MoveP
    32,   // 15: DSPR
    32,   // 16: FGR32
    32,   // 17: MSA128WEvens
    48,   // 18: FGR32_with_MSA128WEvens
    64,   // 19: MSA128F16
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 6, 10, -1,
  /* 5 */ 3, 6, 7, 10, -1,
  /* 10 */ 2, 15, -1,
  /* 13 */ 8, 12, 13, 15, -1,
  /* 18 */ 9, 14, 15, -1,
  /* 22 */ 1, 5, 9, 11, 12, 14, 15, -1,
  /* 30 */ 5, 9, 11, 13, 14, 15, -1,
  /* 37 */ 4, 8, 11, 12, 13, 14, 15, -1,
  /* 45 */ 5, 9, 11, 12, 13, 14, 15, -1,
  /* 53 */ 16, 18, 19, -1,
  /* 57 */ 16, 17, 18, 19, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *MipsGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    55,1,1,1,1,11,53,53,11,1,1,11,32,32,1,32,18,25,39,18,13,30,23,2,7,38,37,45,37,1,1,0,1,22,5,5,1,55,11,11,53,32,32,18,25,39,18,13,3,30,23,38,37,45,1,1,37,5,1,10,22,5,5,1,55,55,55,55,58,5,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *MipsGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 321 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    11,0,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,10,32,22,37,37,37,38,5,5,7,2,7,2,7,2,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,57,53,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,58,55,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,11,11,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,30,45,18,18,18,13,13,11,11,11,11,11,11,11,11,11,11,11,45,45,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc MipsRegDesc[];
extern const int16_t MipsRegDiffLists[];
extern const LaneBitmask MipsLaneMaskLists[];
extern const char MipsRegStrings[];
extern const char MipsRegClassStrings[];
extern const MCPhysReg MipsRegUnitRoots[][2];
extern const uint16_t MipsSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits MipsSubRegIdxRanges[];
extern const uint16_t MipsRegEncodingTable[];
// Mips Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0Dwarf2L[];
extern const unsigned MipsDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0Dwarf2L[];
extern const unsigned MipsEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair MipsDwarfFlavour0L2Dwarf[];
extern const unsigned MipsDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair MipsEHFlavour0L2Dwarf[];
extern const unsigned MipsEHFlavour0L2DwarfSize;

MipsGenRegisterInfo::
MipsGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&MipsRegInfoDesc, RegisterClasses, RegisterClasses+70,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFF80), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(MipsRegDesc, 442, RA, PC,
                     MipsMCRegisterClasses, 70,
                     MipsRegUnitRoots,
                     321,
                     MipsRegDiffLists,
                     MipsLaneMaskLists,
                     MipsRegStrings,
                     MipsRegClassStrings,
                     MipsSubRegIdxLists,
                     12,
                     MipsSubRegIdxRanges,
                     MipsRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(MipsDwarfFlavour0Dwarf2L, MipsDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(MipsEHFlavour0Dwarf2L, MipsEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(MipsDwarfFlavour0L2Dwarf, MipsDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(MipsEHFlavour0L2Dwarf, MipsEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_Interrupt_32_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, Mips::LO0, Mips::HI0, 0 };
static const uint32_t CSR_Interrupt_32_RegMask[] = { 0x07e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x20000000, 0x00000000, 0x00000008, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Interrupt_32R6_SaveList[] = { Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::V1, Mips::V0, Mips::T9, Mips::T8, Mips::T7, Mips::T6, Mips::T5, Mips::T4, Mips::T3, Mips::T2, Mips::T1, Mips::T0, Mips::RA, Mips::FP, Mips::GP, Mips::AT, 0 };
static const uint32_t CSR_Interrupt_32R6_RegMask[] = { 0x03e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07ffbfc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Interrupt_64_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::V1_64, Mips::V0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, Mips::LO0_64, Mips::HI0_64, 0 };
static const uint32_t CSR_Interrupt_64_RegMask[] = { 0x47e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x30000000, 0x00000000, 0x00000008, 0x07ffbfe0, 0xf8000000, 0x00000001, 0x03ffffe4, };
static const MCPhysReg CSR_Interrupt_64R6_SaveList[] = { Mips::A3_64, Mips::A2_64, Mips::A1_64, Mips::A0_64, Mips::V1_64, Mips::V0_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, Mips::T9_64, Mips::T8_64, Mips::T7_64, Mips::T6_64, Mips::T5_64, Mips::T4_64, Mips::T3_64, Mips::T2_64, Mips::T1_64, Mips::T0_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::AT_64, 0 };
static const uint32_t CSR_Interrupt_64R6_RegMask[] = { 0x43e80302, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000000, 0x10000000, 0x00000000, 0x00000000, 0x07ffbfe0, 0xf8000000, 0x00000000, 0x03ffffc0, };
static const MCPhysReg CSR_Mips16RetHelper_SaveList[] = { Mips::V0, Mips::V1, Mips::FP, Mips::A3, Mips::A2, Mips::A1, Mips::A0, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, 0 };
static const uint32_t CSR_Mips16RetHelper_RegMask[] = { 0x03e00100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x06003fc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_N32_SaveList[] = { Mips::D20_64, Mips::D22_64, Mips::D24_64, Mips::D26_64, Mips::D28_64, Mips::D30_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
static const uint32_t CSR_N32_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x08000000, 0x15550000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xaaa00000, 0x00003fc0, };
static const MCPhysReg CSR_N64_SaveList[] = { Mips::D31_64, Mips::D30_64, Mips::D29_64, Mips::D28_64, Mips::D27_64, Mips::D26_64, Mips::D25_64, Mips::D24_64, Mips::RA_64, Mips::FP_64, Mips::GP_64, Mips::S7_64, Mips::S6_64, Mips::S5_64, Mips::S4_64, Mips::S3_64, Mips::S2_64, Mips::S1_64, Mips::S0_64, 0 };
static const uint32_t CSR_N64_RegMask[] = { 0x00280300, 0x00000000, 0x00000000, 0x00000000, 0x00007800, 0x0007f800, 0x08000000, 0x1ff00000, 0x00000000, 0x00000000, 0x00003fe0, 0x08000000, 0xfe000000, 0x00003fc1, };
static const MCPhysReg CSR_O32_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_O32_FP64_SaveList[] = { Mips::D30_64, Mips::D28_64, Mips::D26_64, Mips::D24_64, Mips::D22_64, Mips::D20_64, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_FP64_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x0002aa80, 0x00000000, 0x05550000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0xaaa00000, 0x00000000, };
static const MCPhysReg CSR_O32_FPXX_SaveList[] = { Mips::D15, Mips::D14, Mips::D13, Mips::D12, Mips::D11, Mips::D10, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_O32_FPXX_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SingleFloatOnly_SaveList[] = { Mips::F31, Mips::F30, Mips::F29, Mips::F28, Mips::F27, Mips::F26, Mips::F25, Mips::F24, Mips::F23, Mips::F22, Mips::F21, Mips::F20, Mips::RA, Mips::FP, Mips::S7, Mips::S6, Mips::S5, Mips::S4, Mips::S3, Mips::S2, Mips::S1, Mips::S0, 0 };
static const uint32_t CSR_SingleFloatOnly_RegMask[] = { 0x00280100, 0x00000000, 0x00000000, 0x00000000, 0x00007e00, 0x0007ff80, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003fc0, 0x08000000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> MipsGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_Interrupt_32_RegMask,
    CSR_Interrupt_32R6_RegMask,
    CSR_Interrupt_64_RegMask,
    CSR_Interrupt_64R6_RegMask,
    CSR_Mips16RetHelper_RegMask,
    CSR_N32_RegMask,
    CSR_N64_RegMask,
    CSR_O32_RegMask,
    CSR_O32_FP64_RegMask,
    CSR_O32_FPXX_RegMask,
    CSR_SingleFloatOnly_RegMask,
  };
  return ArrayRef(Masks);
}

bool MipsGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool MipsGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      PhysReg == Mips::ZERO ||
      PhysReg == Mips::ZERO_64 ||
      false;
}

ArrayRef<const char *> MipsGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR_Interrupt_32",
    "CSR_Interrupt_32R6",
    "CSR_Interrupt_64",
    "CSR_Interrupt_64R6",
    "CSR_Mips16RetHelper",
    "CSR_N32",
    "CSR_N64",
    "CSR_O32",
    "CSR_O32_FP64",
    "CSR_O32_FPXX",
    "CSR_SingleFloatOnly",
  };
  return ArrayRef(Names);
}

const MipsFrameLowering *
MipsGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const MipsFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31