/src/build/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Target Register Enum Values *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | #ifdef GET_REGINFO_ENUM |
11 | | #undef GET_REGINFO_ENUM |
12 | | |
13 | | namespace llvm { |
14 | | |
15 | | class MCRegisterClass; |
16 | | extern const MCRegisterClass NVPTXMCRegisterClasses[]; |
17 | | |
18 | | namespace NVPTX { |
19 | | enum { |
20 | | NoRegister, |
21 | | VRDepot = 1, |
22 | | ENVREG0 = 2, |
23 | | ENVREG1 = 3, |
24 | | ENVREG2 = 4, |
25 | | ENVREG3 = 5, |
26 | | ENVREG4 = 6, |
27 | | ENVREG5 = 7, |
28 | | ENVREG6 = 8, |
29 | | ENVREG7 = 9, |
30 | | ENVREG8 = 10, |
31 | | ENVREG9 = 11, |
32 | | ENVREG10 = 12, |
33 | | ENVREG11 = 13, |
34 | | ENVREG12 = 14, |
35 | | ENVREG13 = 15, |
36 | | ENVREG14 = 16, |
37 | | ENVREG15 = 17, |
38 | | ENVREG16 = 18, |
39 | | ENVREG17 = 19, |
40 | | ENVREG18 = 20, |
41 | | ENVREG19 = 21, |
42 | | ENVREG20 = 22, |
43 | | ENVREG21 = 23, |
44 | | ENVREG22 = 24, |
45 | | ENVREG23 = 25, |
46 | | ENVREG24 = 26, |
47 | | ENVREG25 = 27, |
48 | | ENVREG26 = 28, |
49 | | ENVREG27 = 29, |
50 | | ENVREG28 = 30, |
51 | | ENVREG29 = 31, |
52 | | ENVREG30 = 32, |
53 | | ENVREG31 = 33, |
54 | | F0 = 34, |
55 | | F1 = 35, |
56 | | F2 = 36, |
57 | | F3 = 37, |
58 | | F4 = 38, |
59 | | FL0 = 39, |
60 | | FL1 = 40, |
61 | | FL2 = 41, |
62 | | FL3 = 42, |
63 | | FL4 = 43, |
64 | | H0 = 44, |
65 | | H1 = 45, |
66 | | H2 = 46, |
67 | | H3 = 47, |
68 | | H4 = 48, |
69 | | HH0 = 49, |
70 | | HH1 = 50, |
71 | | HH2 = 51, |
72 | | HH3 = 52, |
73 | | HH4 = 53, |
74 | | P0 = 54, |
75 | | P1 = 55, |
76 | | P2 = 56, |
77 | | P3 = 57, |
78 | | P4 = 58, |
79 | | R0 = 59, |
80 | | R1 = 60, |
81 | | R2 = 61, |
82 | | R3 = 62, |
83 | | R4 = 63, |
84 | | RL0 = 64, |
85 | | RL1 = 65, |
86 | | RL2 = 66, |
87 | | RL3 = 67, |
88 | | RL4 = 68, |
89 | | RS0 = 69, |
90 | | RS1 = 70, |
91 | | RS2 = 71, |
92 | | RS3 = 72, |
93 | | RS4 = 73, |
94 | | VRFrame32 = 74, |
95 | | VRFrame64 = 75, |
96 | | VRFrameLocal32 = 76, |
97 | | VRFrameLocal64 = 77, |
98 | | da0 = 78, |
99 | | da1 = 79, |
100 | | da2 = 80, |
101 | | da3 = 81, |
102 | | da4 = 82, |
103 | | fa0 = 83, |
104 | | fa1 = 84, |
105 | | fa2 = 85, |
106 | | fa3 = 86, |
107 | | fa4 = 87, |
108 | | ia0 = 88, |
109 | | ia1 = 89, |
110 | | ia2 = 90, |
111 | | ia3 = 91, |
112 | | ia4 = 92, |
113 | | la0 = 93, |
114 | | la1 = 94, |
115 | | la2 = 95, |
116 | | la3 = 96, |
117 | | la4 = 97, |
118 | | NUM_TARGET_REGS // 98 |
119 | | }; |
120 | | } // end namespace NVPTX |
121 | | |
122 | | // Register classes |
123 | | |
124 | | namespace NVPTX { |
125 | | enum { |
126 | | Int1RegsRegClassID = 0, |
127 | | Int16RegsRegClassID = 1, |
128 | | SpecialRegsRegClassID = 2, |
129 | | Int32RegsRegClassID = 3, |
130 | | Float32ArgRegsRegClassID = 4, |
131 | | Float32RegsRegClassID = 5, |
132 | | Int32ArgRegsRegClassID = 6, |
133 | | Int32Regs_and_SpecialRegsRegClassID = 7, |
134 | | Int64RegsRegClassID = 8, |
135 | | Float64ArgRegsRegClassID = 9, |
136 | | Float64RegsRegClassID = 10, |
137 | | Int64ArgRegsRegClassID = 11, |
138 | | |
139 | | }; |
140 | | } // end namespace NVPTX |
141 | | |
142 | | // Register pressure sets enum. |
143 | | namespace NVPTX { |
144 | | enum RegisterPressureSets { |
145 | | Int32Regs_and_SpecialRegs = 0, |
146 | | Int1Regs = 1, |
147 | | Int16Regs = 2, |
148 | | Float32ArgRegs = 3, |
149 | | Float32Regs = 4, |
150 | | Int32ArgRegs = 5, |
151 | | Float64ArgRegs = 6, |
152 | | Float64Regs = 7, |
153 | | Int64ArgRegs = 8, |
154 | | Int32Regs = 9, |
155 | | Int64Regs = 10, |
156 | | SpecialRegs = 11, |
157 | | SpecialRegs_with_Int32Regs = 12, |
158 | | }; |
159 | | } // end namespace NVPTX |
160 | | |
161 | | } // end namespace llvm |
162 | | |
163 | | #endif // GET_REGINFO_ENUM |
164 | | |
165 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
166 | | |* *| |
167 | | |* MC Register Information *| |
168 | | |* *| |
169 | | |* Automatically generated file, do not edit! *| |
170 | | |* *| |
171 | | \*===----------------------------------------------------------------------===*/ |
172 | | |
173 | | |
174 | | #ifdef GET_REGINFO_MC_DESC |
175 | | #undef GET_REGINFO_MC_DESC |
176 | | |
177 | | namespace llvm { |
178 | | |
179 | | extern const int16_t NVPTXRegDiffLists[] = { |
180 | | /* 0 */ 0, |
181 | | }; |
182 | | |
183 | | extern const LaneBitmask NVPTXLaneMaskLists[] = { |
184 | | /* 0 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(), |
185 | | }; |
186 | | |
187 | | extern const uint16_t NVPTXSubRegIdxLists[] = { |
188 | | /* 0 */ 0, |
189 | | }; |
190 | | |
191 | | extern const MCRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRanges[] = { |
192 | | { 65535, 65535 }, |
193 | | }; |
194 | | |
195 | | |
196 | | #ifdef __GNUC__ |
197 | | #pragma GCC diagnostic push |
198 | | #pragma GCC diagnostic ignored "-Woverlength-strings" |
199 | | #endif |
200 | | extern const char NVPTXRegStrings[] = { |
201 | | /* 0 */ "ENVREG10\0" |
202 | | /* 9 */ "ENVREG20\0" |
203 | | /* 18 */ "ENVREG30\0" |
204 | | /* 27 */ "F0\0" |
205 | | /* 30 */ "ENVREG0\0" |
206 | | /* 38 */ "HH0\0" |
207 | | /* 42 */ "FL0\0" |
208 | | /* 46 */ "RL0\0" |
209 | | /* 50 */ "P0\0" |
210 | | /* 53 */ "R0\0" |
211 | | /* 56 */ "RS0\0" |
212 | | /* 60 */ "da0\0" |
213 | | /* 64 */ "fa0\0" |
214 | | /* 68 */ "ia0\0" |
215 | | /* 72 */ "la0\0" |
216 | | /* 76 */ "ENVREG11\0" |
217 | | /* 85 */ "ENVREG21\0" |
218 | | /* 94 */ "ENVREG31\0" |
219 | | /* 103 */ "F1\0" |
220 | | /* 106 */ "ENVREG1\0" |
221 | | /* 114 */ "HH1\0" |
222 | | /* 118 */ "FL1\0" |
223 | | /* 122 */ "RL1\0" |
224 | | /* 126 */ "P1\0" |
225 | | /* 129 */ "R1\0" |
226 | | /* 132 */ "RS1\0" |
227 | | /* 136 */ "da1\0" |
228 | | /* 140 */ "fa1\0" |
229 | | /* 144 */ "ia1\0" |
230 | | /* 148 */ "la1\0" |
231 | | /* 152 */ "ENVREG12\0" |
232 | | /* 161 */ "ENVREG22\0" |
233 | | /* 170 */ "VRFrame32\0" |
234 | | /* 180 */ "VRFrameLocal32\0" |
235 | | /* 195 */ "F2\0" |
236 | | /* 198 */ "ENVREG2\0" |
237 | | /* 206 */ "HH2\0" |
238 | | /* 210 */ "FL2\0" |
239 | | /* 214 */ "RL2\0" |
240 | | /* 218 */ "P2\0" |
241 | | /* 221 */ "R2\0" |
242 | | /* 224 */ "RS2\0" |
243 | | /* 228 */ "da2\0" |
244 | | /* 232 */ "fa2\0" |
245 | | /* 236 */ "ia2\0" |
246 | | /* 240 */ "la2\0" |
247 | | /* 244 */ "ENVREG13\0" |
248 | | /* 253 */ "ENVREG23\0" |
249 | | /* 262 */ "F3\0" |
250 | | /* 265 */ "ENVREG3\0" |
251 | | /* 273 */ "HH3\0" |
252 | | /* 277 */ "FL3\0" |
253 | | /* 281 */ "RL3\0" |
254 | | /* 285 */ "P3\0" |
255 | | /* 288 */ "R3\0" |
256 | | /* 291 */ "RS3\0" |
257 | | /* 295 */ "da3\0" |
258 | | /* 299 */ "fa3\0" |
259 | | /* 303 */ "ia3\0" |
260 | | /* 307 */ "la3\0" |
261 | | /* 311 */ "ENVREG14\0" |
262 | | /* 320 */ "ENVREG24\0" |
263 | | /* 329 */ "VRFrame64\0" |
264 | | /* 339 */ "VRFrameLocal64\0" |
265 | | /* 354 */ "F4\0" |
266 | | /* 357 */ "ENVREG4\0" |
267 | | /* 365 */ "HH4\0" |
268 | | /* 369 */ "FL4\0" |
269 | | /* 373 */ "RL4\0" |
270 | | /* 377 */ "P4\0" |
271 | | /* 380 */ "R4\0" |
272 | | /* 383 */ "RS4\0" |
273 | | /* 387 */ "da4\0" |
274 | | /* 391 */ "fa4\0" |
275 | | /* 395 */ "ia4\0" |
276 | | /* 399 */ "la4\0" |
277 | | /* 403 */ "ENVREG15\0" |
278 | | /* 412 */ "ENVREG25\0" |
279 | | /* 421 */ "ENVREG5\0" |
280 | | /* 429 */ "ENVREG16\0" |
281 | | /* 438 */ "ENVREG26\0" |
282 | | /* 447 */ "ENVREG6\0" |
283 | | /* 455 */ "ENVREG17\0" |
284 | | /* 464 */ "ENVREG27\0" |
285 | | /* 473 */ "ENVREG7\0" |
286 | | /* 481 */ "ENVREG18\0" |
287 | | /* 490 */ "ENVREG28\0" |
288 | | /* 499 */ "ENVREG8\0" |
289 | | /* 507 */ "ENVREG19\0" |
290 | | /* 516 */ "ENVREG29\0" |
291 | | /* 525 */ "ENVREG9\0" |
292 | | /* 533 */ "VRDepot\0" |
293 | | }; |
294 | | #ifdef __GNUC__ |
295 | | #pragma GCC diagnostic pop |
296 | | #endif |
297 | | |
298 | | extern const MCRegisterDesc NVPTXRegDesc[] = { // Descriptors |
299 | | { 8, 0, 0, 0, 0, 0 }, |
300 | | { 533, 0, 0, 0, 0, 0 }, |
301 | | { 30, 0, 0, 0, 1, 0 }, |
302 | | { 106, 0, 0, 0, 2, 0 }, |
303 | | { 198, 0, 0, 0, 3, 0 }, |
304 | | { 265, 0, 0, 0, 4, 0 }, |
305 | | { 357, 0, 0, 0, 5, 0 }, |
306 | | { 421, 0, 0, 0, 6, 0 }, |
307 | | { 447, 0, 0, 0, 7, 0 }, |
308 | | { 473, 0, 0, 0, 8, 0 }, |
309 | | { 499, 0, 0, 0, 9, 0 }, |
310 | | { 525, 0, 0, 0, 10, 0 }, |
311 | | { 0, 0, 0, 0, 11, 0 }, |
312 | | { 76, 0, 0, 0, 12, 0 }, |
313 | | { 152, 0, 0, 0, 13, 0 }, |
314 | | { 244, 0, 0, 0, 14, 0 }, |
315 | | { 311, 0, 0, 0, 15, 0 }, |
316 | | { 403, 0, 0, 0, 16, 0 }, |
317 | | { 429, 0, 0, 0, 17, 0 }, |
318 | | { 455, 0, 0, 0, 18, 0 }, |
319 | | { 481, 0, 0, 0, 19, 0 }, |
320 | | { 507, 0, 0, 0, 20, 0 }, |
321 | | { 9, 0, 0, 0, 21, 0 }, |
322 | | { 85, 0, 0, 0, 22, 0 }, |
323 | | { 161, 0, 0, 0, 23, 0 }, |
324 | | { 253, 0, 0, 0, 24, 0 }, |
325 | | { 320, 0, 0, 0, 25, 0 }, |
326 | | { 412, 0, 0, 0, 26, 0 }, |
327 | | { 438, 0, 0, 0, 27, 0 }, |
328 | | { 464, 0, 0, 0, 28, 0 }, |
329 | | { 490, 0, 0, 0, 29, 0 }, |
330 | | { 516, 0, 0, 0, 30, 0 }, |
331 | | { 18, 0, 0, 0, 31, 0 }, |
332 | | { 94, 0, 0, 0, 32, 0 }, |
333 | | { 27, 0, 0, 0, 33, 0 }, |
334 | | { 103, 0, 0, 0, 34, 0 }, |
335 | | { 195, 0, 0, 0, 35, 0 }, |
336 | | { 262, 0, 0, 0, 36, 0 }, |
337 | | { 354, 0, 0, 0, 37, 0 }, |
338 | | { 42, 0, 0, 0, 38, 0 }, |
339 | | { 118, 0, 0, 0, 39, 0 }, |
340 | | { 210, 0, 0, 0, 40, 0 }, |
341 | | { 277, 0, 0, 0, 41, 0 }, |
342 | | { 369, 0, 0, 0, 42, 0 }, |
343 | | { 39, 0, 0, 0, 43, 0 }, |
344 | | { 115, 0, 0, 0, 44, 0 }, |
345 | | { 207, 0, 0, 0, 45, 0 }, |
346 | | { 274, 0, 0, 0, 46, 0 }, |
347 | | { 366, 0, 0, 0, 47, 0 }, |
348 | | { 38, 0, 0, 0, 48, 0 }, |
349 | | { 114, 0, 0, 0, 49, 0 }, |
350 | | { 206, 0, 0, 0, 50, 0 }, |
351 | | { 273, 0, 0, 0, 51, 0 }, |
352 | | { 365, 0, 0, 0, 52, 0 }, |
353 | | { 50, 0, 0, 0, 53, 0 }, |
354 | | { 126, 0, 0, 0, 54, 0 }, |
355 | | { 218, 0, 0, 0, 55, 0 }, |
356 | | { 285, 0, 0, 0, 56, 0 }, |
357 | | { 377, 0, 0, 0, 57, 0 }, |
358 | | { 53, 0, 0, 0, 58, 0 }, |
359 | | { 129, 0, 0, 0, 59, 0 }, |
360 | | { 221, 0, 0, 0, 60, 0 }, |
361 | | { 288, 0, 0, 0, 61, 0 }, |
362 | | { 380, 0, 0, 0, 62, 0 }, |
363 | | { 46, 0, 0, 0, 63, 0 }, |
364 | | { 122, 0, 0, 0, 64, 0 }, |
365 | | { 214, 0, 0, 0, 65, 0 }, |
366 | | { 281, 0, 0, 0, 66, 0 }, |
367 | | { 373, 0, 0, 0, 67, 0 }, |
368 | | { 56, 0, 0, 0, 68, 0 }, |
369 | | { 132, 0, 0, 0, 69, 0 }, |
370 | | { 224, 0, 0, 0, 70, 0 }, |
371 | | { 291, 0, 0, 0, 71, 0 }, |
372 | | { 383, 0, 0, 0, 72, 0 }, |
373 | | { 170, 0, 0, 0, 73, 0 }, |
374 | | { 329, 0, 0, 0, 74, 0 }, |
375 | | { 180, 0, 0, 0, 75, 0 }, |
376 | | { 339, 0, 0, 0, 76, 0 }, |
377 | | { 60, 0, 0, 0, 77, 0 }, |
378 | | { 136, 0, 0, 0, 78, 0 }, |
379 | | { 228, 0, 0, 0, 79, 0 }, |
380 | | { 295, 0, 0, 0, 80, 0 }, |
381 | | { 387, 0, 0, 0, 81, 0 }, |
382 | | { 64, 0, 0, 0, 82, 0 }, |
383 | | { 140, 0, 0, 0, 83, 0 }, |
384 | | { 232, 0, 0, 0, 84, 0 }, |
385 | | { 299, 0, 0, 0, 85, 0 }, |
386 | | { 391, 0, 0, 0, 86, 0 }, |
387 | | { 68, 0, 0, 0, 87, 0 }, |
388 | | { 144, 0, 0, 0, 88, 0 }, |
389 | | { 236, 0, 0, 0, 89, 0 }, |
390 | | { 303, 0, 0, 0, 90, 0 }, |
391 | | { 395, 0, 0, 0, 91, 0 }, |
392 | | { 72, 0, 0, 0, 92, 0 }, |
393 | | { 148, 0, 0, 0, 93, 0 }, |
394 | | { 240, 0, 0, 0, 94, 0 }, |
395 | | { 307, 0, 0, 0, 95, 0 }, |
396 | | { 399, 0, 0, 0, 96, 0 }, |
397 | | }; |
398 | | |
399 | | extern const MCPhysReg NVPTXRegUnitRoots[][2] = { |
400 | | { NVPTX::VRDepot }, |
401 | | { NVPTX::ENVREG0 }, |
402 | | { NVPTX::ENVREG1 }, |
403 | | { NVPTX::ENVREG2 }, |
404 | | { NVPTX::ENVREG3 }, |
405 | | { NVPTX::ENVREG4 }, |
406 | | { NVPTX::ENVREG5 }, |
407 | | { NVPTX::ENVREG6 }, |
408 | | { NVPTX::ENVREG7 }, |
409 | | { NVPTX::ENVREG8 }, |
410 | | { NVPTX::ENVREG9 }, |
411 | | { NVPTX::ENVREG10 }, |
412 | | { NVPTX::ENVREG11 }, |
413 | | { NVPTX::ENVREG12 }, |
414 | | { NVPTX::ENVREG13 }, |
415 | | { NVPTX::ENVREG14 }, |
416 | | { NVPTX::ENVREG15 }, |
417 | | { NVPTX::ENVREG16 }, |
418 | | { NVPTX::ENVREG17 }, |
419 | | { NVPTX::ENVREG18 }, |
420 | | { NVPTX::ENVREG19 }, |
421 | | { NVPTX::ENVREG20 }, |
422 | | { NVPTX::ENVREG21 }, |
423 | | { NVPTX::ENVREG22 }, |
424 | | { NVPTX::ENVREG23 }, |
425 | | { NVPTX::ENVREG24 }, |
426 | | { NVPTX::ENVREG25 }, |
427 | | { NVPTX::ENVREG26 }, |
428 | | { NVPTX::ENVREG27 }, |
429 | | { NVPTX::ENVREG28 }, |
430 | | { NVPTX::ENVREG29 }, |
431 | | { NVPTX::ENVREG30 }, |
432 | | { NVPTX::ENVREG31 }, |
433 | | { NVPTX::F0 }, |
434 | | { NVPTX::F1 }, |
435 | | { NVPTX::F2 }, |
436 | | { NVPTX::F3 }, |
437 | | { NVPTX::F4 }, |
438 | | { NVPTX::FL0 }, |
439 | | { NVPTX::FL1 }, |
440 | | { NVPTX::FL2 }, |
441 | | { NVPTX::FL3 }, |
442 | | { NVPTX::FL4 }, |
443 | | { NVPTX::H0 }, |
444 | | { NVPTX::H1 }, |
445 | | { NVPTX::H2 }, |
446 | | { NVPTX::H3 }, |
447 | | { NVPTX::H4 }, |
448 | | { NVPTX::HH0 }, |
449 | | { NVPTX::HH1 }, |
450 | | { NVPTX::HH2 }, |
451 | | { NVPTX::HH3 }, |
452 | | { NVPTX::HH4 }, |
453 | | { NVPTX::P0 }, |
454 | | { NVPTX::P1 }, |
455 | | { NVPTX::P2 }, |
456 | | { NVPTX::P3 }, |
457 | | { NVPTX::P4 }, |
458 | | { NVPTX::R0 }, |
459 | | { NVPTX::R1 }, |
460 | | { NVPTX::R2 }, |
461 | | { NVPTX::R3 }, |
462 | | { NVPTX::R4 }, |
463 | | { NVPTX::RL0 }, |
464 | | { NVPTX::RL1 }, |
465 | | { NVPTX::RL2 }, |
466 | | { NVPTX::RL3 }, |
467 | | { NVPTX::RL4 }, |
468 | | { NVPTX::RS0 }, |
469 | | { NVPTX::RS1 }, |
470 | | { NVPTX::RS2 }, |
471 | | { NVPTX::RS3 }, |
472 | | { NVPTX::RS4 }, |
473 | | { NVPTX::VRFrame32 }, |
474 | | { NVPTX::VRFrame64 }, |
475 | | { NVPTX::VRFrameLocal32 }, |
476 | | { NVPTX::VRFrameLocal64 }, |
477 | | { NVPTX::da0 }, |
478 | | { NVPTX::da1 }, |
479 | | { NVPTX::da2 }, |
480 | | { NVPTX::da3 }, |
481 | | { NVPTX::da4 }, |
482 | | { NVPTX::fa0 }, |
483 | | { NVPTX::fa1 }, |
484 | | { NVPTX::fa2 }, |
485 | | { NVPTX::fa3 }, |
486 | | { NVPTX::fa4 }, |
487 | | { NVPTX::ia0 }, |
488 | | { NVPTX::ia1 }, |
489 | | { NVPTX::ia2 }, |
490 | | { NVPTX::ia3 }, |
491 | | { NVPTX::ia4 }, |
492 | | { NVPTX::la0 }, |
493 | | { NVPTX::la1 }, |
494 | | { NVPTX::la2 }, |
495 | | { NVPTX::la3 }, |
496 | | { NVPTX::la4 }, |
497 | | }; |
498 | | |
499 | | namespace { // Register classes... |
500 | | // Int1Regs Register Class... |
501 | | const MCPhysReg Int1Regs[] = { |
502 | | NVPTX::P0, NVPTX::P1, NVPTX::P2, NVPTX::P3, NVPTX::P4, |
503 | | }; |
504 | | |
505 | | // Int1Regs Bit set. |
506 | | const uint8_t Int1RegsBits[] = { |
507 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, |
508 | | }; |
509 | | |
510 | | // Int16Regs Register Class... |
511 | | const MCPhysReg Int16Regs[] = { |
512 | | NVPTX::RS0, NVPTX::RS1, NVPTX::RS2, NVPTX::RS3, NVPTX::RS4, |
513 | | }; |
514 | | |
515 | | // Int16Regs Bit set. |
516 | | const uint8_t Int16RegsBits[] = { |
517 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, |
518 | | }; |
519 | | |
520 | | // SpecialRegs Register Class... |
521 | | const MCPhysReg SpecialRegs[] = { |
522 | | NVPTX::VRFrame32, NVPTX::VRFrameLocal32, NVPTX::VRDepot, NVPTX::ENVREG0, NVPTX::ENVREG1, NVPTX::ENVREG2, NVPTX::ENVREG3, NVPTX::ENVREG4, NVPTX::ENVREG5, NVPTX::ENVREG6, NVPTX::ENVREG7, NVPTX::ENVREG8, NVPTX::ENVREG9, NVPTX::ENVREG10, NVPTX::ENVREG11, NVPTX::ENVREG12, NVPTX::ENVREG13, NVPTX::ENVREG14, NVPTX::ENVREG15, NVPTX::ENVREG16, NVPTX::ENVREG17, NVPTX::ENVREG18, NVPTX::ENVREG19, NVPTX::ENVREG20, NVPTX::ENVREG21, NVPTX::ENVREG22, NVPTX::ENVREG23, NVPTX::ENVREG24, NVPTX::ENVREG25, NVPTX::ENVREG26, NVPTX::ENVREG27, NVPTX::ENVREG28, NVPTX::ENVREG29, NVPTX::ENVREG30, NVPTX::ENVREG31, |
523 | | }; |
524 | | |
525 | | // SpecialRegs Bit set. |
526 | | const uint8_t SpecialRegsBits[] = { |
527 | | 0xfe, 0xff, 0xff, 0xff, 0x03, 0x00, 0x00, 0x00, 0x00, 0x14, |
528 | | }; |
529 | | |
530 | | // Int32Regs Register Class... |
531 | | const MCPhysReg Int32Regs[] = { |
532 | | NVPTX::R0, NVPTX::R1, NVPTX::R2, NVPTX::R3, NVPTX::R4, NVPTX::VRFrame32, NVPTX::VRFrameLocal32, |
533 | | }; |
534 | | |
535 | | // Int32Regs Bit set. |
536 | | const uint8_t Int32RegsBits[] = { |
537 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x14, |
538 | | }; |
539 | | |
540 | | // Float32ArgRegs Register Class... |
541 | | const MCPhysReg Float32ArgRegs[] = { |
542 | | NVPTX::fa0, NVPTX::fa1, NVPTX::fa2, NVPTX::fa3, NVPTX::fa4, |
543 | | }; |
544 | | |
545 | | // Float32ArgRegs Bit set. |
546 | | const uint8_t Float32ArgRegsBits[] = { |
547 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, |
548 | | }; |
549 | | |
550 | | // Float32Regs Register Class... |
551 | | const MCPhysReg Float32Regs[] = { |
552 | | NVPTX::F0, NVPTX::F1, NVPTX::F2, NVPTX::F3, NVPTX::F4, |
553 | | }; |
554 | | |
555 | | // Float32Regs Bit set. |
556 | | const uint8_t Float32RegsBits[] = { |
557 | | 0x00, 0x00, 0x00, 0x00, 0x7c, |
558 | | }; |
559 | | |
560 | | // Int32ArgRegs Register Class... |
561 | | const MCPhysReg Int32ArgRegs[] = { |
562 | | NVPTX::ia0, NVPTX::ia1, NVPTX::ia2, NVPTX::ia3, NVPTX::ia4, |
563 | | }; |
564 | | |
565 | | // Int32ArgRegs Bit set. |
566 | | const uint8_t Int32ArgRegsBits[] = { |
567 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, |
568 | | }; |
569 | | |
570 | | // Int32Regs_and_SpecialRegs Register Class... |
571 | | const MCPhysReg Int32Regs_and_SpecialRegs[] = { |
572 | | NVPTX::VRFrame32, NVPTX::VRFrameLocal32, |
573 | | }; |
574 | | |
575 | | // Int32Regs_and_SpecialRegs Bit set. |
576 | | const uint8_t Int32Regs_and_SpecialRegsBits[] = { |
577 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14, |
578 | | }; |
579 | | |
580 | | // Int64Regs Register Class... |
581 | | const MCPhysReg Int64Regs[] = { |
582 | | NVPTX::RL0, NVPTX::RL1, NVPTX::RL2, NVPTX::RL3, NVPTX::RL4, NVPTX::VRFrame64, NVPTX::VRFrameLocal64, |
583 | | }; |
584 | | |
585 | | // Int64Regs Bit set. |
586 | | const uint8_t Int64RegsBits[] = { |
587 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1f, 0x28, |
588 | | }; |
589 | | |
590 | | // Float64ArgRegs Register Class... |
591 | | const MCPhysReg Float64ArgRegs[] = { |
592 | | NVPTX::da0, NVPTX::da1, NVPTX::da2, NVPTX::da3, NVPTX::da4, |
593 | | }; |
594 | | |
595 | | // Float64ArgRegs Bit set. |
596 | | const uint8_t Float64ArgRegsBits[] = { |
597 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, |
598 | | }; |
599 | | |
600 | | // Float64Regs Register Class... |
601 | | const MCPhysReg Float64Regs[] = { |
602 | | NVPTX::FL0, NVPTX::FL1, NVPTX::FL2, NVPTX::FL3, NVPTX::FL4, |
603 | | }; |
604 | | |
605 | | // Float64Regs Bit set. |
606 | | const uint8_t Float64RegsBits[] = { |
607 | | 0x00, 0x00, 0x00, 0x00, 0x80, 0x0f, |
608 | | }; |
609 | | |
610 | | // Int64ArgRegs Register Class... |
611 | | const MCPhysReg Int64ArgRegs[] = { |
612 | | NVPTX::la0, NVPTX::la1, NVPTX::la2, NVPTX::la3, NVPTX::la4, |
613 | | }; |
614 | | |
615 | | // Int64ArgRegs Bit set. |
616 | | const uint8_t Int64ArgRegsBits[] = { |
617 | | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x03, |
618 | | }; |
619 | | |
620 | | } // end anonymous namespace |
621 | | |
622 | | |
623 | | #ifdef __GNUC__ |
624 | | #pragma GCC diagnostic push |
625 | | #pragma GCC diagnostic ignored "-Woverlength-strings" |
626 | | #endif |
627 | | extern const char NVPTXRegClassStrings[] = { |
628 | | /* 0 */ "Int1Regs\0" |
629 | | /* 9 */ "Float32Regs\0" |
630 | | /* 21 */ "Int32Regs\0" |
631 | | /* 31 */ "Float64Regs\0" |
632 | | /* 43 */ "Int64Regs\0" |
633 | | /* 53 */ "Int16Regs\0" |
634 | | /* 63 */ "Float32ArgRegs\0" |
635 | | /* 78 */ "Int32ArgRegs\0" |
636 | | /* 91 */ "Float64ArgRegs\0" |
637 | | /* 106 */ "Int64ArgRegs\0" |
638 | | /* 119 */ "Int32Regs_and_SpecialRegs\0" |
639 | | }; |
640 | | #ifdef __GNUC__ |
641 | | #pragma GCC diagnostic pop |
642 | | #endif |
643 | | |
644 | | extern const MCRegisterClass NVPTXMCRegisterClasses[] = { |
645 | | { Int1Regs, Int1RegsBits, 0, 5, sizeof(Int1RegsBits), NVPTX::Int1RegsRegClassID, 1, 1, true }, |
646 | | { Int16Regs, Int16RegsBits, 53, 5, sizeof(Int16RegsBits), NVPTX::Int16RegsRegClassID, 16, 1, true }, |
647 | | { SpecialRegs, SpecialRegsBits, 133, 35, sizeof(SpecialRegsBits), NVPTX::SpecialRegsRegClassID, 32, 1, true }, |
648 | | { Int32Regs, Int32RegsBits, 21, 7, sizeof(Int32RegsBits), NVPTX::Int32RegsRegClassID, 32, 1, true }, |
649 | | { Float32ArgRegs, Float32ArgRegsBits, 63, 5, sizeof(Float32ArgRegsBits), NVPTX::Float32ArgRegsRegClassID, 32, 1, true }, |
650 | | { Float32Regs, Float32RegsBits, 9, 5, sizeof(Float32RegsBits), NVPTX::Float32RegsRegClassID, 32, 1, true }, |
651 | | { Int32ArgRegs, Int32ArgRegsBits, 78, 5, sizeof(Int32ArgRegsBits), NVPTX::Int32ArgRegsRegClassID, 32, 1, true }, |
652 | | { Int32Regs_and_SpecialRegs, Int32Regs_and_SpecialRegsBits, 119, 2, sizeof(Int32Regs_and_SpecialRegsBits), NVPTX::Int32Regs_and_SpecialRegsRegClassID, 32, 1, true }, |
653 | | { Int64Regs, Int64RegsBits, 43, 7, sizeof(Int64RegsBits), NVPTX::Int64RegsRegClassID, 64, 1, true }, |
654 | | { Float64ArgRegs, Float64ArgRegsBits, 91, 5, sizeof(Float64ArgRegsBits), NVPTX::Float64ArgRegsRegClassID, 64, 1, true }, |
655 | | { Float64Regs, Float64RegsBits, 31, 5, sizeof(Float64RegsBits), NVPTX::Float64RegsRegClassID, 64, 1, true }, |
656 | | { Int64ArgRegs, Int64ArgRegsBits, 106, 5, sizeof(Int64ArgRegsBits), NVPTX::Int64ArgRegsRegClassID, 64, 1, true }, |
657 | | }; |
658 | | |
659 | | extern const uint16_t NVPTXRegEncodingTable[] = { |
660 | | 0, |
661 | | 0, |
662 | | 0, |
663 | | 0, |
664 | | 0, |
665 | | 0, |
666 | | 0, |
667 | | 0, |
668 | | 0, |
669 | | 0, |
670 | | 0, |
671 | | 0, |
672 | | 0, |
673 | | 0, |
674 | | 0, |
675 | | 0, |
676 | | 0, |
677 | | 0, |
678 | | 0, |
679 | | 0, |
680 | | 0, |
681 | | 0, |
682 | | 0, |
683 | | 0, |
684 | | 0, |
685 | | 0, |
686 | | 0, |
687 | | 0, |
688 | | 0, |
689 | | 0, |
690 | | 0, |
691 | | 0, |
692 | | 0, |
693 | | 0, |
694 | | 0, |
695 | | 0, |
696 | | 0, |
697 | | 0, |
698 | | 0, |
699 | | 0, |
700 | | 0, |
701 | | 0, |
702 | | 0, |
703 | | 0, |
704 | | 0, |
705 | | 0, |
706 | | 0, |
707 | | 0, |
708 | | 0, |
709 | | 0, |
710 | | 0, |
711 | | 0, |
712 | | 0, |
713 | | 0, |
714 | | 0, |
715 | | 0, |
716 | | 0, |
717 | | 0, |
718 | | 0, |
719 | | 0, |
720 | | 0, |
721 | | 0, |
722 | | 0, |
723 | | 0, |
724 | | 0, |
725 | | 0, |
726 | | 0, |
727 | | 0, |
728 | | 0, |
729 | | 0, |
730 | | 0, |
731 | | 0, |
732 | | 0, |
733 | | 0, |
734 | | 0, |
735 | | 0, |
736 | | 0, |
737 | | 0, |
738 | | 0, |
739 | | 0, |
740 | | 0, |
741 | | 0, |
742 | | 0, |
743 | | 0, |
744 | | 0, |
745 | | 0, |
746 | | 0, |
747 | | 0, |
748 | | 0, |
749 | | 0, |
750 | | 0, |
751 | | 0, |
752 | | 0, |
753 | | 0, |
754 | | 0, |
755 | | 0, |
756 | | 0, |
757 | | 0, |
758 | | }; |
759 | 2 | static inline void InitNVPTXMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) { |
760 | 2 | RI->InitMCRegisterInfo(NVPTXRegDesc, 98, RA, PC, NVPTXMCRegisterClasses, 12, NVPTXRegUnitRoots, 97, NVPTXRegDiffLists, NVPTXLaneMaskLists, NVPTXRegStrings, NVPTXRegClassStrings, NVPTXSubRegIdxLists, 1, |
761 | 2 | NVPTXSubRegIdxRanges, NVPTXRegEncodingTable); |
762 | | |
763 | 2 | } |
764 | | |
765 | | } // end namespace llvm |
766 | | |
767 | | #endif // GET_REGINFO_MC_DESC |
768 | | |
769 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
770 | | |* *| |
771 | | |* Register Information Header Fragment *| |
772 | | |* *| |
773 | | |* Automatically generated file, do not edit! *| |
774 | | |* *| |
775 | | \*===----------------------------------------------------------------------===*/ |
776 | | |
777 | | |
778 | | #ifdef GET_REGINFO_HEADER |
779 | | #undef GET_REGINFO_HEADER |
780 | | |
781 | | #include "llvm/CodeGen/TargetRegisterInfo.h" |
782 | | |
783 | | namespace llvm { |
784 | | |
785 | | class NVPTXFrameLowering; |
786 | | |
787 | | struct NVPTXGenRegisterInfo : public TargetRegisterInfo { |
788 | | explicit NVPTXGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0, |
789 | | unsigned PC = 0, unsigned HwMode = 0); |
790 | | const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override; |
791 | | unsigned getRegUnitWeight(unsigned RegUnit) const override; |
792 | | unsigned getNumRegPressureSets() const override; |
793 | | const char *getRegPressureSetName(unsigned Idx) const override; |
794 | | unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override; |
795 | | const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override; |
796 | | const int *getRegUnitPressureSets(unsigned RegUnit) const override; |
797 | | ArrayRef<const char *> getRegMaskNames() const override; |
798 | | ArrayRef<const uint32_t *> getRegMasks() const override; |
799 | | bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override; |
800 | | bool isFixedRegister(const MachineFunction &, MCRegister) const override; |
801 | | bool isArgumentRegister(const MachineFunction &, MCRegister) const override; |
802 | | bool isConstantPhysReg(MCRegister PhysReg) const override final; |
803 | | /// Devirtualized TargetFrameLowering. |
804 | | static const NVPTXFrameLowering *getFrameLowering( |
805 | | const MachineFunction &MF); |
806 | | }; |
807 | | |
808 | | namespace NVPTX { // Register classes |
809 | | extern const TargetRegisterClass Int1RegsRegClass; |
810 | | extern const TargetRegisterClass Int16RegsRegClass; |
811 | | extern const TargetRegisterClass SpecialRegsRegClass; |
812 | | extern const TargetRegisterClass Int32RegsRegClass; |
813 | | extern const TargetRegisterClass Float32ArgRegsRegClass; |
814 | | extern const TargetRegisterClass Float32RegsRegClass; |
815 | | extern const TargetRegisterClass Int32ArgRegsRegClass; |
816 | | extern const TargetRegisterClass Int32Regs_and_SpecialRegsRegClass; |
817 | | extern const TargetRegisterClass Int64RegsRegClass; |
818 | | extern const TargetRegisterClass Float64ArgRegsRegClass; |
819 | | extern const TargetRegisterClass Float64RegsRegClass; |
820 | | extern const TargetRegisterClass Int64ArgRegsRegClass; |
821 | | } // end namespace NVPTX |
822 | | |
823 | | } // end namespace llvm |
824 | | |
825 | | #endif // GET_REGINFO_HEADER |
826 | | |
827 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
828 | | |* *| |
829 | | |* Target Register and Register Classes Information *| |
830 | | |* *| |
831 | | |* Automatically generated file, do not edit! *| |
832 | | |* *| |
833 | | \*===----------------------------------------------------------------------===*/ |
834 | | |
835 | | |
836 | | #ifdef GET_REGINFO_TARGET_DESC |
837 | | #undef GET_REGINFO_TARGET_DESC |
838 | | |
839 | | namespace llvm { |
840 | | |
841 | | extern const MCRegisterClass NVPTXMCRegisterClasses[]; |
842 | | |
843 | | static const MVT::SimpleValueType VTLists[] = { |
844 | | /* 0 */ MVT::i1, MVT::Other, |
845 | | /* 2 */ MVT::i32, MVT::Other, |
846 | | /* 4 */ MVT::i64, MVT::Other, |
847 | | /* 6 */ MVT::i16, MVT::f16, MVT::bf16, MVT::Other, |
848 | | /* 10 */ MVT::f32, MVT::Other, |
849 | | /* 12 */ MVT::f64, MVT::Other, |
850 | | /* 14 */ MVT::i32, MVT::v2f16, MVT::v2bf16, MVT::v2i16, MVT::v4i8, MVT::Other, |
851 | | }; |
852 | | |
853 | | static const char *SubRegIndexNameTable[] = { "" }; |
854 | | |
855 | | |
856 | | static const LaneBitmask SubRegIndexLaneMaskTable[] = { |
857 | | LaneBitmask::getAll(), |
858 | | }; |
859 | | |
860 | | |
861 | | |
862 | | static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = { |
863 | | // Mode = 0 (Default) |
864 | | { 1, 1, 8, /*VTLists+*/0 }, // Int1Regs |
865 | | { 16, 16, 16, /*VTLists+*/6 }, // Int16Regs |
866 | | { 32, 32, 32, /*VTLists+*/2 }, // SpecialRegs |
867 | | { 32, 32, 32, /*VTLists+*/14 }, // Int32Regs |
868 | | { 32, 32, 32, /*VTLists+*/10 }, // Float32ArgRegs |
869 | | { 32, 32, 32, /*VTLists+*/10 }, // Float32Regs |
870 | | { 32, 32, 32, /*VTLists+*/2 }, // Int32ArgRegs |
871 | | { 32, 32, 32, /*VTLists+*/14 }, // Int32Regs_and_SpecialRegs |
872 | | { 64, 64, 64, /*VTLists+*/4 }, // Int64Regs |
873 | | { 64, 64, 64, /*VTLists+*/12 }, // Float64ArgRegs |
874 | | { 64, 64, 64, /*VTLists+*/12 }, // Float64Regs |
875 | | { 64, 64, 64, /*VTLists+*/4 }, // Int64ArgRegs |
876 | | }; |
877 | | |
878 | | static const TargetRegisterClass *const NullRegClasses[] = { nullptr }; |
879 | | |
880 | | static const uint32_t Int1RegsSubClassMask[] = { |
881 | | 0x00000001, |
882 | | }; |
883 | | |
884 | | static const uint32_t Int16RegsSubClassMask[] = { |
885 | | 0x00000002, |
886 | | }; |
887 | | |
888 | | static const uint32_t SpecialRegsSubClassMask[] = { |
889 | | 0x00000084, |
890 | | }; |
891 | | |
892 | | static const uint32_t Int32RegsSubClassMask[] = { |
893 | | 0x00000088, |
894 | | }; |
895 | | |
896 | | static const uint32_t Float32ArgRegsSubClassMask[] = { |
897 | | 0x00000010, |
898 | | }; |
899 | | |
900 | | static const uint32_t Float32RegsSubClassMask[] = { |
901 | | 0x00000020, |
902 | | }; |
903 | | |
904 | | static const uint32_t Int32ArgRegsSubClassMask[] = { |
905 | | 0x00000040, |
906 | | }; |
907 | | |
908 | | static const uint32_t Int32Regs_and_SpecialRegsSubClassMask[] = { |
909 | | 0x00000080, |
910 | | }; |
911 | | |
912 | | static const uint32_t Int64RegsSubClassMask[] = { |
913 | | 0x00000100, |
914 | | }; |
915 | | |
916 | | static const uint32_t Float64ArgRegsSubClassMask[] = { |
917 | | 0x00000200, |
918 | | }; |
919 | | |
920 | | static const uint32_t Float64RegsSubClassMask[] = { |
921 | | 0x00000400, |
922 | | }; |
923 | | |
924 | | static const uint32_t Int64ArgRegsSubClassMask[] = { |
925 | | 0x00000800, |
926 | | }; |
927 | | |
928 | | static const uint16_t SuperRegIdxSeqs[] = { |
929 | | /* 0 */ 0, |
930 | | }; |
931 | | |
932 | | static const TargetRegisterClass *const Int32Regs_and_SpecialRegsSuperclasses[] = { |
933 | | &NVPTX::SpecialRegsRegClass, |
934 | | &NVPTX::Int32RegsRegClass, |
935 | | nullptr |
936 | | }; |
937 | | |
938 | | |
939 | | namespace NVPTX { // Register class instances |
940 | | extern const TargetRegisterClass Int1RegsRegClass = { |
941 | | &NVPTXMCRegisterClasses[Int1RegsRegClassID], |
942 | | Int1RegsSubClassMask, |
943 | | SuperRegIdxSeqs + 0, |
944 | | LaneBitmask(0x0000000000000001), |
945 | | 0, |
946 | | false, |
947 | | 0x00, /* TSFlags */ |
948 | | false, /* HasDisjunctSubRegs */ |
949 | | false, /* CoveredBySubRegs */ |
950 | | NullRegClasses, |
951 | | nullptr |
952 | | }; |
953 | | |
954 | | extern const TargetRegisterClass Int16RegsRegClass = { |
955 | | &NVPTXMCRegisterClasses[Int16RegsRegClassID], |
956 | | Int16RegsSubClassMask, |
957 | | SuperRegIdxSeqs + 0, |
958 | | LaneBitmask(0x0000000000000001), |
959 | | 0, |
960 | | false, |
961 | | 0x00, /* TSFlags */ |
962 | | false, /* HasDisjunctSubRegs */ |
963 | | false, /* CoveredBySubRegs */ |
964 | | NullRegClasses, |
965 | | nullptr |
966 | | }; |
967 | | |
968 | | extern const TargetRegisterClass SpecialRegsRegClass = { |
969 | | &NVPTXMCRegisterClasses[SpecialRegsRegClassID], |
970 | | SpecialRegsSubClassMask, |
971 | | SuperRegIdxSeqs + 0, |
972 | | LaneBitmask(0x0000000000000001), |
973 | | 0, |
974 | | false, |
975 | | 0x00, /* TSFlags */ |
976 | | false, /* HasDisjunctSubRegs */ |
977 | | false, /* CoveredBySubRegs */ |
978 | | NullRegClasses, |
979 | | nullptr |
980 | | }; |
981 | | |
982 | | extern const TargetRegisterClass Int32RegsRegClass = { |
983 | | &NVPTXMCRegisterClasses[Int32RegsRegClassID], |
984 | | Int32RegsSubClassMask, |
985 | | SuperRegIdxSeqs + 0, |
986 | | LaneBitmask(0x0000000000000001), |
987 | | 0, |
988 | | false, |
989 | | 0x00, /* TSFlags */ |
990 | | false, /* HasDisjunctSubRegs */ |
991 | | false, /* CoveredBySubRegs */ |
992 | | NullRegClasses, |
993 | | nullptr |
994 | | }; |
995 | | |
996 | | extern const TargetRegisterClass Float32ArgRegsRegClass = { |
997 | | &NVPTXMCRegisterClasses[Float32ArgRegsRegClassID], |
998 | | Float32ArgRegsSubClassMask, |
999 | | SuperRegIdxSeqs + 0, |
1000 | | LaneBitmask(0x0000000000000001), |
1001 | | 0, |
1002 | | false, |
1003 | | 0x00, /* TSFlags */ |
1004 | | false, /* HasDisjunctSubRegs */ |
1005 | | false, /* CoveredBySubRegs */ |
1006 | | NullRegClasses, |
1007 | | nullptr |
1008 | | }; |
1009 | | |
1010 | | extern const TargetRegisterClass Float32RegsRegClass = { |
1011 | | &NVPTXMCRegisterClasses[Float32RegsRegClassID], |
1012 | | Float32RegsSubClassMask, |
1013 | | SuperRegIdxSeqs + 0, |
1014 | | LaneBitmask(0x0000000000000001), |
1015 | | 0, |
1016 | | false, |
1017 | | 0x00, /* TSFlags */ |
1018 | | false, /* HasDisjunctSubRegs */ |
1019 | | false, /* CoveredBySubRegs */ |
1020 | | NullRegClasses, |
1021 | | nullptr |
1022 | | }; |
1023 | | |
1024 | | extern const TargetRegisterClass Int32ArgRegsRegClass = { |
1025 | | &NVPTXMCRegisterClasses[Int32ArgRegsRegClassID], |
1026 | | Int32ArgRegsSubClassMask, |
1027 | | SuperRegIdxSeqs + 0, |
1028 | | LaneBitmask(0x0000000000000001), |
1029 | | 0, |
1030 | | false, |
1031 | | 0x00, /* TSFlags */ |
1032 | | false, /* HasDisjunctSubRegs */ |
1033 | | false, /* CoveredBySubRegs */ |
1034 | | NullRegClasses, |
1035 | | nullptr |
1036 | | }; |
1037 | | |
1038 | | extern const TargetRegisterClass Int32Regs_and_SpecialRegsRegClass = { |
1039 | | &NVPTXMCRegisterClasses[Int32Regs_and_SpecialRegsRegClassID], |
1040 | | Int32Regs_and_SpecialRegsSubClassMask, |
1041 | | SuperRegIdxSeqs + 0, |
1042 | | LaneBitmask(0x0000000000000001), |
1043 | | 0, |
1044 | | false, |
1045 | | 0x00, /* TSFlags */ |
1046 | | false, /* HasDisjunctSubRegs */ |
1047 | | false, /* CoveredBySubRegs */ |
1048 | | Int32Regs_and_SpecialRegsSuperclasses, |
1049 | | nullptr |
1050 | | }; |
1051 | | |
1052 | | extern const TargetRegisterClass Int64RegsRegClass = { |
1053 | | &NVPTXMCRegisterClasses[Int64RegsRegClassID], |
1054 | | Int64RegsSubClassMask, |
1055 | | SuperRegIdxSeqs + 0, |
1056 | | LaneBitmask(0x0000000000000001), |
1057 | | 0, |
1058 | | false, |
1059 | | 0x00, /* TSFlags */ |
1060 | | false, /* HasDisjunctSubRegs */ |
1061 | | false, /* CoveredBySubRegs */ |
1062 | | NullRegClasses, |
1063 | | nullptr |
1064 | | }; |
1065 | | |
1066 | | extern const TargetRegisterClass Float64ArgRegsRegClass = { |
1067 | | &NVPTXMCRegisterClasses[Float64ArgRegsRegClassID], |
1068 | | Float64ArgRegsSubClassMask, |
1069 | | SuperRegIdxSeqs + 0, |
1070 | | LaneBitmask(0x0000000000000001), |
1071 | | 0, |
1072 | | false, |
1073 | | 0x00, /* TSFlags */ |
1074 | | false, /* HasDisjunctSubRegs */ |
1075 | | false, /* CoveredBySubRegs */ |
1076 | | NullRegClasses, |
1077 | | nullptr |
1078 | | }; |
1079 | | |
1080 | | extern const TargetRegisterClass Float64RegsRegClass = { |
1081 | | &NVPTXMCRegisterClasses[Float64RegsRegClassID], |
1082 | | Float64RegsSubClassMask, |
1083 | | SuperRegIdxSeqs + 0, |
1084 | | LaneBitmask(0x0000000000000001), |
1085 | | 0, |
1086 | | false, |
1087 | | 0x00, /* TSFlags */ |
1088 | | false, /* HasDisjunctSubRegs */ |
1089 | | false, /* CoveredBySubRegs */ |
1090 | | NullRegClasses, |
1091 | | nullptr |
1092 | | }; |
1093 | | |
1094 | | extern const TargetRegisterClass Int64ArgRegsRegClass = { |
1095 | | &NVPTXMCRegisterClasses[Int64ArgRegsRegClassID], |
1096 | | Int64ArgRegsSubClassMask, |
1097 | | SuperRegIdxSeqs + 0, |
1098 | | LaneBitmask(0x0000000000000001), |
1099 | | 0, |
1100 | | false, |
1101 | | 0x00, /* TSFlags */ |
1102 | | false, /* HasDisjunctSubRegs */ |
1103 | | false, /* CoveredBySubRegs */ |
1104 | | NullRegClasses, |
1105 | | nullptr |
1106 | | }; |
1107 | | |
1108 | | } // end namespace NVPTX |
1109 | | |
1110 | | namespace { |
1111 | | const TargetRegisterClass *const RegisterClasses[] = { |
1112 | | &NVPTX::Int1RegsRegClass, |
1113 | | &NVPTX::Int16RegsRegClass, |
1114 | | &NVPTX::SpecialRegsRegClass, |
1115 | | &NVPTX::Int32RegsRegClass, |
1116 | | &NVPTX::Float32ArgRegsRegClass, |
1117 | | &NVPTX::Float32RegsRegClass, |
1118 | | &NVPTX::Int32ArgRegsRegClass, |
1119 | | &NVPTX::Int32Regs_and_SpecialRegsRegClass, |
1120 | | &NVPTX::Int64RegsRegClass, |
1121 | | &NVPTX::Float64ArgRegsRegClass, |
1122 | | &NVPTX::Float64RegsRegClass, |
1123 | | &NVPTX::Int64ArgRegsRegClass, |
1124 | | }; |
1125 | | } // end anonymous namespace |
1126 | | |
1127 | | static const uint8_t CostPerUseTable[] = { |
1128 | | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, }; |
1129 | | |
1130 | | |
1131 | | static const bool InAllocatableClassTable[] = { |
1132 | | false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, }; |
1133 | | |
1134 | | |
1135 | | static const TargetRegisterInfoDesc NVPTXRegInfoDesc = { // Extra Descriptors |
1136 | | CostPerUseTable, 1, InAllocatableClassTable}; |
1137 | | |
1138 | | /// Get the weight in units of pressure for this register class. |
1139 | | const RegClassWeight &NVPTXGenRegisterInfo:: |
1140 | 0 | getRegClassWeight(const TargetRegisterClass *RC) const { |
1141 | 0 | static const RegClassWeight RCWeightTable[] = { |
1142 | 0 | {1, 5}, // Int1Regs |
1143 | 0 | {1, 5}, // Int16Regs |
1144 | 0 | {1, 35}, // SpecialRegs |
1145 | 0 | {1, 7}, // Int32Regs |
1146 | 0 | {1, 5}, // Float32ArgRegs |
1147 | 0 | {1, 5}, // Float32Regs |
1148 | 0 | {1, 5}, // Int32ArgRegs |
1149 | 0 | {1, 2}, // Int32Regs_and_SpecialRegs |
1150 | 0 | {1, 7}, // Int64Regs |
1151 | 0 | {1, 5}, // Float64ArgRegs |
1152 | 0 | {1, 5}, // Float64Regs |
1153 | 0 | {1, 5}, // Int64ArgRegs |
1154 | 0 | }; |
1155 | 0 | return RCWeightTable[RC->getID()]; |
1156 | 0 | } |
1157 | | |
1158 | | /// Get the weight in units of pressure for this register unit. |
1159 | | unsigned NVPTXGenRegisterInfo:: |
1160 | 0 | getRegUnitWeight(unsigned RegUnit) const { |
1161 | 0 | assert(RegUnit < 97 && "invalid register unit"); |
1162 | | // All register units have unit weight. |
1163 | 0 | return 1; |
1164 | 0 | } |
1165 | | |
1166 | | |
1167 | | // Get the number of dimensions of register pressure. |
1168 | 2.21k | unsigned NVPTXGenRegisterInfo::getNumRegPressureSets() const { |
1169 | 2.21k | return 13; |
1170 | 2.21k | } |
1171 | | |
1172 | | // Get the name of this register unit pressure set. |
1173 | | const char *NVPTXGenRegisterInfo:: |
1174 | 0 | getRegPressureSetName(unsigned Idx) const { |
1175 | 0 | static const char *PressureNameTable[] = { |
1176 | 0 | "Int32Regs_and_SpecialRegs", |
1177 | 0 | "Int1Regs", |
1178 | 0 | "Int16Regs", |
1179 | 0 | "Float32ArgRegs", |
1180 | 0 | "Float32Regs", |
1181 | 0 | "Int32ArgRegs", |
1182 | 0 | "Float64ArgRegs", |
1183 | 0 | "Float64Regs", |
1184 | 0 | "Int64ArgRegs", |
1185 | 0 | "Int32Regs", |
1186 | 0 | "Int64Regs", |
1187 | 0 | "SpecialRegs", |
1188 | 0 | "SpecialRegs_with_Int32Regs", |
1189 | 0 | }; |
1190 | 0 | return PressureNameTable[Idx]; |
1191 | 0 | } |
1192 | | |
1193 | | // Get the register unit pressure limit for this dimension. |
1194 | | // This limit must be adjusted dynamically for reserved registers. |
1195 | | unsigned NVPTXGenRegisterInfo:: |
1196 | 9.59k | getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const { |
1197 | 9.59k | static const uint8_t PressureLimitTable[] = { |
1198 | 9.59k | 2, // 0: Int32Regs_and_SpecialRegs |
1199 | 9.59k | 5, // 1: Int1Regs |
1200 | 9.59k | 5, // 2: Int16Regs |
1201 | 9.59k | 5, // 3: Float32ArgRegs |
1202 | 9.59k | 5, // 4: Float32Regs |
1203 | 9.59k | 5, // 5: Int32ArgRegs |
1204 | 9.59k | 5, // 6: Float64ArgRegs |
1205 | 9.59k | 5, // 7: Float64Regs |
1206 | 9.59k | 5, // 8: Int64ArgRegs |
1207 | 9.59k | 7, // 9: Int32Regs |
1208 | 9.59k | 7, // 10: Int64Regs |
1209 | 9.59k | 35, // 11: SpecialRegs |
1210 | 9.59k | 40, // 12: SpecialRegs_with_Int32Regs |
1211 | 9.59k | }; |
1212 | 9.59k | return PressureLimitTable[Idx]; |
1213 | 9.59k | } |
1214 | | |
1215 | | /// Table of pressure sets per register class or unit. |
1216 | | static const int RCSetsTable[] = { |
1217 | | /* 0 */ 1, -1, |
1218 | | /* 2 */ 2, -1, |
1219 | | /* 4 */ 3, -1, |
1220 | | /* 6 */ 4, -1, |
1221 | | /* 8 */ 5, -1, |
1222 | | /* 10 */ 6, -1, |
1223 | | /* 12 */ 7, -1, |
1224 | | /* 14 */ 8, -1, |
1225 | | /* 16 */ 10, -1, |
1226 | | /* 18 */ 9, 12, -1, |
1227 | | /* 21 */ 0, 9, 11, 12, -1, |
1228 | | }; |
1229 | | |
1230 | | /// Get the dimensions of register pressure impacted by this register class. |
1231 | | /// Returns a -1 terminated array of pressure set IDs |
1232 | | const int *NVPTXGenRegisterInfo:: |
1233 | 0 | getRegClassPressureSets(const TargetRegisterClass *RC) const { |
1234 | 0 | static const uint8_t RCSetStartTable[] = { |
1235 | 0 | 0,2,23,18,4,6,8,21,16,10,12,14,}; |
1236 | 0 | return &RCSetsTable[RCSetStartTable[RC->getID()]]; |
1237 | 0 | } |
1238 | | |
1239 | | /// Get the dimensions of register pressure impacted by this register unit. |
1240 | | /// Returns a -1 terminated array of pressure set IDs |
1241 | | const int *NVPTXGenRegisterInfo:: |
1242 | 0 | getRegUnitPressureSets(unsigned RegUnit) const { |
1243 | 0 | assert(RegUnit < 97 && "invalid register unit"); |
1244 | 0 | static const uint8_t RUSetStartTable[] = { |
1245 | 0 | 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,6,6,6,6,6,12,12,12,12,12,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,18,18,18,18,18,16,16,16,16,16,2,2,2,2,2,21,16,21,16,10,10,10,10,10,4,4,4,4,4,8,8,8,8,8,14,14,14,14,14,}; |
1246 | 0 | return &RCSetsTable[RUSetStartTable[RegUnit]]; |
1247 | 0 | } |
1248 | | |
1249 | | extern const MCRegisterDesc NVPTXRegDesc[]; |
1250 | | extern const int16_t NVPTXRegDiffLists[]; |
1251 | | extern const LaneBitmask NVPTXLaneMaskLists[]; |
1252 | | extern const char NVPTXRegStrings[]; |
1253 | | extern const char NVPTXRegClassStrings[]; |
1254 | | extern const MCPhysReg NVPTXRegUnitRoots[][2]; |
1255 | | extern const uint16_t NVPTXSubRegIdxLists[]; |
1256 | | extern const MCRegisterInfo::SubRegCoveredBits NVPTXSubRegIdxRanges[]; |
1257 | | extern const uint16_t NVPTXRegEncodingTable[]; |
1258 | | NVPTXGenRegisterInfo:: |
1259 | | NVPTXGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, |
1260 | | unsigned PC, unsigned HwMode) |
1261 | | : TargetRegisterInfo(&NVPTXRegInfoDesc, RegisterClasses, RegisterClasses+12, |
1262 | | SubRegIndexNameTable, SubRegIndexLaneMaskTable, |
1263 | 2 | LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) { |
1264 | 2 | InitMCRegisterInfo(NVPTXRegDesc, 98, RA, PC, |
1265 | 2 | NVPTXMCRegisterClasses, 12, |
1266 | 2 | NVPTXRegUnitRoots, |
1267 | 2 | 97, |
1268 | 2 | NVPTXRegDiffLists, |
1269 | 2 | NVPTXLaneMaskLists, |
1270 | 2 | NVPTXRegStrings, |
1271 | 2 | NVPTXRegClassStrings, |
1272 | 2 | NVPTXSubRegIdxLists, |
1273 | 2 | 1, |
1274 | 2 | NVPTXSubRegIdxRanges, |
1275 | 2 | NVPTXRegEncodingTable); |
1276 | | |
1277 | 2 | } |
1278 | | |
1279 | | |
1280 | | |
1281 | 0 | ArrayRef<const uint32_t *> NVPTXGenRegisterInfo::getRegMasks() const { |
1282 | 0 | return std::nullopt; |
1283 | 0 | } |
1284 | | |
1285 | | bool NVPTXGenRegisterInfo:: |
1286 | 0 | isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
1287 | 0 | return |
1288 | 0 | false; |
1289 | 0 | } |
1290 | | |
1291 | | bool NVPTXGenRegisterInfo:: |
1292 | 0 | isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
1293 | 0 | return |
1294 | 0 | false; |
1295 | 0 | } |
1296 | | |
1297 | | bool NVPTXGenRegisterInfo:: |
1298 | 0 | isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const { |
1299 | 0 | return |
1300 | 0 | false; |
1301 | 0 | } |
1302 | | |
1303 | | bool NVPTXGenRegisterInfo:: |
1304 | 0 | isConstantPhysReg(MCRegister PhysReg) const { |
1305 | 0 | return |
1306 | 0 | false; |
1307 | 0 | } |
1308 | | |
1309 | 0 | ArrayRef<const char *> NVPTXGenRegisterInfo::getRegMaskNames() const { |
1310 | 0 | return std::nullopt; |
1311 | 0 | } |
1312 | | |
1313 | | const NVPTXFrameLowering * |
1314 | 0 | NVPTXGenRegisterInfo::getFrameLowering(const MachineFunction &MF) { |
1315 | 0 | return static_cast<const NVPTXFrameLowering *>( |
1316 | 0 | MF.getSubtarget().getFrameLowering()); |
1317 | 0 | } |
1318 | | |
1319 | | } // end namespace llvm |
1320 | | |
1321 | | #endif // GET_REGINFO_TARGET_DESC |
1322 | | |