/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\

|*                                                                            *|

|* Subtarget Enumeration Source Fragment                                      *|

|*                                                                            *|

|* Automatically generated file, do not edit!                                 *|

|*                                                                            *|

\*===----------------------------------------------------------------------===*/

#ifdef GET_SUBTARGETINFO_ENUM

#undef GET_SUBTARGETINFO_ENUM

namespace llvm {

namespace NVPTX {

enum {

  PTX32 = 0,

  PTX40 = 1,

  PTX41 = 2,

  PTX42 = 3,

  PTX43 = 4,

  PTX50 = 5,

  PTX60 = 6,

  PTX61 = 7,

  PTX63 = 8,

  PTX64 = 9,

  PTX65 = 10,

  PTX70 = 11,

  PTX71 = 12,

  PTX72 = 13,

  PTX73 = 14,

  PTX74 = 15,

  PTX75 = 16,

  PTX76 = 17,

  PTX77 = 18,

  PTX78 = 19,

  PTX80 = 20,

  PTX81 = 21,

  PTX82 = 22,

  PTX83 = 23,

  SM20 = 24,

  SM21 = 25,

  SM30 = 26,

  SM32 = 27,

  SM35 = 28,

  SM37 = 29,

  SM50 = 30,

  SM52 = 31,

  SM53 = 32,

  SM60 = 33,

  SM61 = 34,

  SM62 = 35,

  SM70 = 36,

  SM72 = 37,

  SM75 = 38,

  SM80 = 39,

  SM86 = 40,

  SM87 = 41,

  SM89 = 42,

  SM90 = 43,

  SM90a = 44,

  NumSubtargetFeatures = 45

};

} // end namespace NVPTX

} // end namespace llvm

#endif // GET_SUBTARGETINFO_ENUM

#ifdef GET_SUBTARGETINFO_MACRO

#undef GET_SUBTARGETINFO_MACRO

#endif // GET_SUBTARGETINFO_MACRO

#ifdef GET_SUBTARGETINFO_MC_DESC

#undef GET_SUBTARGETINFO_MC_DESC

namespace llvm {

// Sorted (by key) array of values for CPU features.

extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[] = {

  { "ptx32", "Use PTX version 32", NVPTX::PTX32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx40", "Use PTX version 40", NVPTX::PTX40, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx41", "Use PTX version 41", NVPTX::PTX41, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx42", "Use PTX version 42", NVPTX::PTX42, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx43", "Use PTX version 43", NVPTX::PTX43, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx50", "Use PTX version 50", NVPTX::PTX50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx60", "Use PTX version 60", NVPTX::PTX60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx61", "Use PTX version 61", NVPTX::PTX61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx63", "Use PTX version 63", NVPTX::PTX63, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx64", "Use PTX version 64", NVPTX::PTX64, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx65", "Use PTX version 65", NVPTX::PTX65, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx70", "Use PTX version 70", NVPTX::PTX70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx71", "Use PTX version 71", NVPTX::PTX71, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx72", "Use PTX version 72", NVPTX::PTX72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx73", "Use PTX version 73", NVPTX::PTX73, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx74", "Use PTX version 74", NVPTX::PTX74, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx75", "Use PTX version 75", NVPTX::PTX75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx76", "Use PTX version 76", NVPTX::PTX76, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx77", "Use PTX version 77", NVPTX::PTX77, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx78", "Use PTX version 78", NVPTX::PTX78, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx80", "Use PTX version 80", NVPTX::PTX80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx81", "Use PTX version 81", NVPTX::PTX81, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx82", "Use PTX version 82", NVPTX::PTX82, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ptx83", "Use PTX version 83", NVPTX::PTX83, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_20", "Target SM 20", NVPTX::SM20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_21", "Target SM 21", NVPTX::SM21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_30", "Target SM 30", NVPTX::SM30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_32", "Target SM 32", NVPTX::SM32, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_35", "Target SM 35", NVPTX::SM35, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_37", "Target SM 37", NVPTX::SM37, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_50", "Target SM 50", NVPTX::SM50, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_52", "Target SM 52", NVPTX::SM52, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_53", "Target SM 53", NVPTX::SM53, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_60", "Target SM 60", NVPTX::SM60, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_61", "Target SM 61", NVPTX::SM61, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_62", "Target SM 62", NVPTX::SM62, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_70", "Target SM 70", NVPTX::SM70, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_72", "Target SM 72", NVPTX::SM72, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_75", "Target SM 75", NVPTX::SM75, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_80", "Target SM 80", NVPTX::SM80, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_86", "Target SM 86", NVPTX::SM86, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_87", "Target SM 87", NVPTX::SM87, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_89", "Target SM 89", NVPTX::SM89, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_90", "Target SM 90", NVPTX::SM90, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sm_90a", "Target SM 90a", NVPTX::SM90a, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

};

#ifdef DBGFIELD

#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"

#endif

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

#define DBGFIELD(x) x,

#else

#define DBGFIELD(x)

#endif

// ===============================================================

// Data tables for the new per-operand machine model.

// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}

extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[] = {

  { 0,  0,  0 }, // Invalid

}; // NVPTXWriteProcResTable

// {Cycles, WriteResourceID}

extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[] = {

  { 0,  0}, // Invalid

}; // NVPTXWriteLatencyTable

// {UseIdx, WriteResourceID, Cycles}

extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[] = {

  {0,  0,  0}, // Invalid

}; // NVPTXReadAdvanceTable

#undef DBGFIELD

static const llvm::MCSchedModel NoSchedModel = {

  MCSchedModel::DefaultIssueWidth,

  MCSchedModel::DefaultMicroOpBufferSize,

  MCSchedModel::DefaultLoopMicroOpBufferSize,

  MCSchedModel::DefaultLoadLatency,

  MCSchedModel::DefaultHighLatency,

  MCSchedModel::DefaultMispredictPenalty,

  false, // PostRAScheduler

  false, // CompleteModel

  false, // EnableIntervals

  0, // Processor ID

  nullptr, nullptr, 0, 0, // No instruction-level machine model.

  nullptr, // No Itinerary

  nullptr // No extra processor descriptor

};

// Sorted (by key) array of values for CPU subtype.

extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[] = {

 { "sm_20", { { { 0x1000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_21", { { { 0x2000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_30", { { { 0x4000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_32", { { { 0x8000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_35", { { { 0x10000001ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_37", { { { 0x20000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_50", { { { 0x40000002ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_52", { { { 0x80000004ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_53", { { { 0x100000008ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_60", { { { 0x200000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_61", { { { 0x400000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_62", { { { 0x800000020ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_70", { { { 0x1000000040ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_72", { { { 0x2000000080ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_75", { { { 0x4000000100ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_80", { { { 0x8000000800ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_86", { { { 0x10000001000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_87", { { { 0x20000008000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_89", { { { 0x40000080000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_90", { { { 0x80000080000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

 { "sm_90a", { { { 0x100000100000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } }, &NoSchedModel },

};

namespace NVPTX_MC {

unsigned resolveVariantSchedClassImpl(unsigned SchedClass,

    const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) {

  // Don't know how to resolve this scheduling class.

  return 0;

}

} // end namespace NVPTX_MC

struct NVPTXGenMCSubtargetInfo : public MCSubtargetInfo {

  NVPTXGenMCSubtargetInfo(const Triple &TT,

    StringRef CPU, StringRef TuneCPU, StringRef FS,

    ArrayRef<SubtargetFeatureKV> PF,

    ArrayRef<SubtargetSubTypeKV> PD,

    const MCWriteProcResEntry *WPR,

    const MCWriteLatencyEntry *WL,

    const MCReadAdvanceEntry *RA, const InstrStage *IS,

    const unsigned *OC, const unsigned *FP) :

      MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD,

                      WPR, WL, RA, IS, OC, FP) { }

  unsigned resolveVariantSchedClass(unsigned SchedClass,

      const MCInst *MI, const MCInstrInfo *MCII,

      unsigned CPUID) const override {

    return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);

  }

};

static inline MCSubtargetInfo *createNVPTXMCSubtargetInfoImpl(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS) {

  return new NVPTXGenMCSubtargetInfo(TT, CPU, TuneCPU, FS, NVPTXFeatureKV, NVPTXSubTypeKV, 

                      NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 

                      nullptr, nullptr, nullptr);

}

} // end namespace llvm

#endif // GET_SUBTARGETINFO_MC_DESC

#ifdef GET_SUBTARGETINFO_TARGET_DESC

#undef GET_SUBTARGETINFO_TARGET_DESC

#include "llvm/Support/Debug.h"

#include "llvm/Support/raw_ostream.h"

// ParseSubtargetFeatures - Parses features string setting specified

// subtarget options.

void llvm::NVPTXSubtarget::ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS) {

  LLVM_DEBUG(dbgs() << "\nFeatures:" << FS);

  LLVM_DEBUG(dbgs() << "\nCPU:" << CPU);

  LLVM_DEBUG(dbgs() << "\nTuneCPU:" << TuneCPU << "\n\n");

  InitMCProcessorInfo(CPU, TuneCPU, FS);

  const FeatureBitset &Bits = getFeatureBits();

  if (Bits[NVPTX::PTX32] && PTXVersion < 32) PTXVersion = 32;

  if (Bits[NVPTX::PTX40] && PTXVersion < 40) PTXVersion = 40;

  if (Bits[NVPTX::PTX41] && PTXVersion < 41) PTXVersion = 41;

  if (Bits[NVPTX::PTX42] && PTXVersion < 42) PTXVersion = 42;

  if (Bits[NVPTX::PTX43] && PTXVersion < 43) PTXVersion = 43;

  if (Bits[NVPTX::PTX50] && PTXVersion < 50) PTXVersion = 50;

  if (Bits[NVPTX::PTX60] && PTXVersion < 60) PTXVersion = 60;

  if (Bits[NVPTX::PTX61] && PTXVersion < 61) PTXVersion = 61;

  if (Bits[NVPTX::PTX63] && PTXVersion < 63) PTXVersion = 63;

  if (Bits[NVPTX::PTX64] && PTXVersion < 64) PTXVersion = 64;

  if (Bits[NVPTX::PTX65] && PTXVersion < 65) PTXVersion = 65;

  if (Bits[NVPTX::PTX70] && PTXVersion < 70) PTXVersion = 70;

  if (Bits[NVPTX::PTX71] && PTXVersion < 71) PTXVersion = 71;

  if (Bits[NVPTX::PTX72] && PTXVersion < 72) PTXVersion = 72;

  if (Bits[NVPTX::PTX73] && PTXVersion < 73) PTXVersion = 73;

  if (Bits[NVPTX::PTX74] && PTXVersion < 74) PTXVersion = 74;

  if (Bits[NVPTX::PTX75] && PTXVersion < 75) PTXVersion = 75;

  if (Bits[NVPTX::PTX76] && PTXVersion < 76) PTXVersion = 76;

  if (Bits[NVPTX::PTX77] && PTXVersion < 77) PTXVersion = 77;

  if (Bits[NVPTX::PTX78] && PTXVersion < 78) PTXVersion = 78;

  if (Bits[NVPTX::PTX80] && PTXVersion < 80) PTXVersion = 80;

  if (Bits[NVPTX::PTX81] && PTXVersion < 81) PTXVersion = 81;

  if (Bits[NVPTX::PTX82] && PTXVersion < 82) PTXVersion = 82;

  if (Bits[NVPTX::PTX83] && PTXVersion < 83) PTXVersion = 83;

  if (Bits[NVPTX::SM20] && FullSmVersion < 200) FullSmVersion = 200;

  if (Bits[NVPTX::SM21] && FullSmVersion < 210) FullSmVersion = 210;

  if (Bits[NVPTX::SM30] && FullSmVersion < 300) FullSmVersion = 300;

  if (Bits[NVPTX::SM32] && FullSmVersion < 320) FullSmVersion = 320;

  if (Bits[NVPTX::SM35] && FullSmVersion < 350) FullSmVersion = 350;

  if (Bits[NVPTX::SM37] && FullSmVersion < 370) FullSmVersion = 370;

  if (Bits[NVPTX::SM50] && FullSmVersion < 500) FullSmVersion = 500;

  if (Bits[NVPTX::SM52] && FullSmVersion < 520) FullSmVersion = 520;

  if (Bits[NVPTX::SM53] && FullSmVersion < 530) FullSmVersion = 530;

  if (Bits[NVPTX::SM60] && FullSmVersion < 600) FullSmVersion = 600;

  if (Bits[NVPTX::SM61] && FullSmVersion < 610) FullSmVersion = 610;

  if (Bits[NVPTX::SM62] && FullSmVersion < 620) FullSmVersion = 620;

  if (Bits[NVPTX::SM70] && FullSmVersion < 700) FullSmVersion = 700;

  if (Bits[NVPTX::SM72] && FullSmVersion < 720) FullSmVersion = 720;

  if (Bits[NVPTX::SM75] && FullSmVersion < 750) FullSmVersion = 750;

  if (Bits[NVPTX::SM80] && FullSmVersion < 800) FullSmVersion = 800;

  if (Bits[NVPTX::SM86] && FullSmVersion < 860) FullSmVersion = 860;

  if (Bits[NVPTX::SM87] && FullSmVersion < 870) FullSmVersion = 870;

  if (Bits[NVPTX::SM89] && FullSmVersion < 890) FullSmVersion = 890;

  if (Bits[NVPTX::SM90] && FullSmVersion < 900) FullSmVersion = 900;

  if (Bits[NVPTX::SM90a] && FullSmVersion < 901) FullSmVersion = 901;

}

#endif // GET_SUBTARGETINFO_TARGET_DESC

#ifdef GET_SUBTARGETINFO_HEADER

#undef GET_SUBTARGETINFO_HEADER

namespace llvm {

class DFAPacketizer;

namespace NVPTX_MC {

unsigned resolveVariantSchedClassImpl(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID);

} // end namespace NVPTX_MC

struct NVPTXGenSubtargetInfo : public TargetSubtargetInfo {

  explicit NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS);

public:

  unsigned resolveSchedClass(unsigned SchedClass,  const MachineInstr *DefMI, const TargetSchedModel *SchedModel) const override;

  unsigned resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const override;

  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID) const;

};

} // end namespace llvm

#endif // GET_SUBTARGETINFO_HEADER

#ifdef GET_SUBTARGETINFO_CTOR

#undef GET_SUBTARGETINFO_CTOR

#include "llvm/CodeGen/TargetSchedule.h"

namespace llvm {

extern const llvm::SubtargetFeatureKV NVPTXFeatureKV[];

extern const llvm::SubtargetSubTypeKV NVPTXSubTypeKV[];

extern const llvm::MCWriteProcResEntry NVPTXWriteProcResTable[];

extern const llvm::MCWriteLatencyEntry NVPTXWriteLatencyTable[];

extern const llvm::MCReadAdvanceEntry NVPTXReadAdvanceTable[];

NVPTXGenSubtargetInfo::NVPTXGenSubtargetInfo(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS)

  : TargetSubtargetInfo(TT, CPU, TuneCPU, FS, ArrayRef(NVPTXFeatureKV, 45), ArrayRef(NVPTXSubTypeKV, 21), 

                        NVPTXWriteProcResTable, NVPTXWriteLatencyTable, NVPTXReadAdvanceTable, 

                        nullptr, nullptr, nullptr) {}

unsigned NVPTXGenSubtargetInfo

::resolveSchedClass(unsigned SchedClass, const MachineInstr *MI, const TargetSchedModel *SchedModel) const {

  report_fatal_error("Expected a variant SchedClass");

} // NVPTXGenSubtargetInfo::resolveSchedClass

unsigned NVPTXGenSubtargetInfo

::resolveVariantSchedClass(unsigned SchedClass, const MCInst *MI, const MCInstrInfo *MCII, unsigned CPUID) const {

  return NVPTX_MC::resolveVariantSchedClassImpl(SchedClass, MI, MCII, CPUID);

} // NVPTXGenSubtargetInfo::resolveVariantSchedClass

} // end namespace llvm

#endif // GET_SUBTARGETINFO_CTOR

#ifdef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS

#undef GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS

#endif // GET_STIPREDICATE_DECLS_FOR_MC_ANALYSIS

#ifdef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS

#undef GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS

#endif // GET_STIPREDICATE_DEFS_FOR_MC_ANALYSIS