/src/build/lib/Target/PowerPC/PPCGenCallingConv.inc
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1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Calling Convention Implementation Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifndef GET_CC_REGISTER_LISTS |
10 | | |
11 | | bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, |
12 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
13 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
14 | | bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, |
15 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
16 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
17 | | static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT, |
18 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
19 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
20 | | bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, |
21 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
22 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
23 | | static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT, |
24 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
25 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
26 | | bool llvm::CC_PPC64_ELF(unsigned ValNo, MVT ValVT, |
27 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
28 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
29 | | bool llvm::CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, |
30 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
31 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
32 | | bool llvm::RetCC_PPC(unsigned ValNo, MVT ValVT, |
33 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
34 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
35 | | static bool RetCC_PPC64_AnyReg(unsigned ValNo, MVT ValVT, |
36 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
37 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
38 | | bool llvm::RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, |
39 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
40 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
41 | | bool llvm::RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, |
42 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
43 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
44 | | |
45 | | |
46 | | bool llvm::CC_PPC32_SVR4(unsigned ValNo, MVT ValVT, |
47 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
48 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
49 | |
|
50 | 0 | if (LocVT == MVT::v16i8 || |
51 | 0 | LocVT == MVT::v8i16 || |
52 | 0 | LocVT == MVT::v4i32 || |
53 | 0 | LocVT == MVT::v2i64 || |
54 | 0 | LocVT == MVT::v1i128 || |
55 | 0 | LocVT == MVT::v4f32 || |
56 | 0 | LocVT == MVT::v2f64) { |
57 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
58 | 0 | static const MCPhysReg RegList1[] = { |
59 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
60 | 0 | }; |
61 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
62 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
63 | 0 | return false; |
64 | 0 | } |
65 | 0 | } |
66 | 0 | } |
67 | | |
68 | 0 | if (LocVT == MVT::f128) { |
69 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
70 | 0 | static const MCPhysReg RegList2[] = { |
71 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
72 | 0 | }; |
73 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
74 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
75 | 0 | return false; |
76 | 0 | } |
77 | 0 | } |
78 | 0 | } |
79 | | |
80 | 0 | if (!CC_PPC32_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
81 | 0 | return false; |
82 | | |
83 | 0 | return true; // CC didn't match. |
84 | 0 | } |
85 | | |
86 | | |
87 | | bool llvm::CC_PPC32_SVR4_ByVal(unsigned ValNo, MVT ValVT, |
88 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
89 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
90 | |
|
91 | 0 | if (ArgFlags.isByVal()) { |
92 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 4, Align(4), ArgFlags); |
93 | 0 | return false; |
94 | 0 | } |
95 | | |
96 | 0 | if (CC_PPC32_SVR4_Custom_Dummy(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
97 | 0 | return false; |
98 | | |
99 | 0 | return true; // CC didn't match. |
100 | 0 | } |
101 | | |
102 | | |
103 | | static bool CC_PPC32_SVR4_Common(unsigned ValNo, MVT ValVT, |
104 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
105 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
106 | |
|
107 | 0 | if (LocVT == MVT::i1) { |
108 | 0 | LocVT = MVT::i32; |
109 | 0 | if (ArgFlags.isSExt()) |
110 | 0 | LocInfo = CCValAssign::SExt; |
111 | 0 | else if (ArgFlags.isZExt()) |
112 | 0 | LocInfo = CCValAssign::ZExt; |
113 | 0 | else |
114 | 0 | LocInfo = CCValAssign::AExt; |
115 | 0 | } |
116 | |
|
117 | 0 | if (LocVT == MVT::i32) { |
118 | 0 | if (ArgFlags.isSplit()) { |
119 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
120 | 0 | if (!static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)) { |
121 | 0 | if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
122 | 0 | return false; |
123 | 0 | } |
124 | 0 | } |
125 | 0 | } |
126 | 0 | } |
127 | | |
128 | 0 | if (LocVT == MVT::i32) { |
129 | 0 | if (ArgFlags.isSplit()) { |
130 | 0 | if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
131 | 0 | if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
132 | 0 | return false; |
133 | 0 | } |
134 | 0 | } |
135 | 0 | } |
136 | | |
137 | 0 | if (LocVT == MVT::f64) { |
138 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
139 | 0 | if (CC_PPC32_SVR4_Custom_AlignArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
140 | 0 | return false; |
141 | 0 | } |
142 | 0 | } |
143 | | |
144 | 0 | if (ArgFlags.isSplit()) { |
145 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).useSoftFloat()) { |
146 | 0 | if (static_cast<PPCCCState *>(&State)->WasOriginalArgPPCF128(ValNo)) { |
147 | 0 | if (CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
148 | 0 | return false; |
149 | 0 | } |
150 | 0 | } |
151 | 0 | } |
152 | | |
153 | 0 | if (ArgFlags.isNest()) { |
154 | 0 | if (unsigned Reg = State.AllocateReg(PPC::R11)) { |
155 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
156 | 0 | return false; |
157 | 0 | } |
158 | 0 | } |
159 | | |
160 | 0 | if (LocVT == MVT::i32) { |
161 | 0 | static const MCPhysReg RegList1[] = { |
162 | 0 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10 |
163 | 0 | }; |
164 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
165 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
166 | 0 | return false; |
167 | 0 | } |
168 | 0 | } |
169 | | |
170 | 0 | if (LocVT == MVT::f64) { |
171 | 0 | if (ArgFlags.isSplit()) { |
172 | 0 | if (CC_PPC32_SVR4_Custom_AlignFPArgRegs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
173 | 0 | return false; |
174 | 0 | } |
175 | 0 | } |
176 | | |
177 | 0 | if (LocVT == MVT::f32 || |
178 | 0 | LocVT == MVT::f64) { |
179 | 0 | if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
180 | 0 | static const MCPhysReg RegList2[] = { |
181 | 0 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 |
182 | 0 | }; |
183 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
184 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
185 | 0 | return false; |
186 | 0 | } |
187 | 0 | } |
188 | 0 | } |
189 | | |
190 | 0 | if (LocVT == MVT::f64) { |
191 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
192 | 0 | if (CC_PPC32_SPE_CustomSplitFP64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
193 | 0 | return false; |
194 | 0 | } |
195 | 0 | } |
196 | | |
197 | 0 | if (LocVT == MVT::f32) { |
198 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
199 | 0 | static const MCPhysReg RegList3[] = { |
200 | 0 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10 |
201 | 0 | }; |
202 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
203 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
204 | 0 | return false; |
205 | 0 | } |
206 | 0 | } |
207 | 0 | } |
208 | | |
209 | 0 | if (LocVT == MVT::i32) { |
210 | 0 | if (ArgFlags.isSplit()) { |
211 | 0 | int64_t Offset4 = State.AllocateStack(4, Align(8)); |
212 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
213 | 0 | return false; |
214 | 0 | } |
215 | 0 | } |
216 | | |
217 | 0 | if (LocVT == MVT::i32) { |
218 | 0 | int64_t Offset5 = State.AllocateStack(4, Align(4)); |
219 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset5, LocVT, LocInfo)); |
220 | 0 | return false; |
221 | 0 | } |
222 | | |
223 | 0 | if (LocVT == MVT::f32) { |
224 | 0 | int64_t Offset6 = State.AllocateStack(4, Align(4)); |
225 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset6, LocVT, LocInfo)); |
226 | 0 | return false; |
227 | 0 | } |
228 | | |
229 | 0 | if (LocVT == MVT::f64) { |
230 | 0 | int64_t Offset7 = State.AllocateStack(8, Align(8)); |
231 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset7, LocVT, LocInfo)); |
232 | 0 | return false; |
233 | 0 | } |
234 | | |
235 | 0 | if (LocVT == MVT::v16i8 || |
236 | 0 | LocVT == MVT::v8i16 || |
237 | 0 | LocVT == MVT::v4i32 || |
238 | 0 | LocVT == MVT::v4f32 || |
239 | 0 | LocVT == MVT::v2f64 || |
240 | 0 | LocVT == MVT::v2i64) { |
241 | 0 | int64_t Offset8 = State.AllocateStack(16, Align(16)); |
242 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
243 | 0 | return false; |
244 | 0 | } |
245 | | |
246 | 0 | if (LocVT == MVT::f128) { |
247 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
248 | 0 | int64_t Offset9 = State.AllocateStack(16, Align(16)); |
249 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset9, LocVT, LocInfo)); |
250 | 0 | return false; |
251 | 0 | } |
252 | 0 | } |
253 | | |
254 | 0 | return true; // CC didn't match. |
255 | 0 | } |
256 | | |
257 | | |
258 | | bool llvm::CC_PPC32_SVR4_VarArg(unsigned ValNo, MVT ValVT, |
259 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
260 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
261 | |
|
262 | 0 | if (!CC_PPC32_SVR4_Common(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
263 | 0 | return false; |
264 | | |
265 | 0 | return true; // CC didn't match. |
266 | 0 | } |
267 | | |
268 | | |
269 | | static bool CC_PPC64_AnyReg(unsigned ValNo, MVT ValVT, |
270 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
271 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
272 | |
|
273 | 0 | if (CC_PPC_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
274 | 0 | return false; |
275 | | |
276 | 0 | return true; // CC didn't match. |
277 | 0 | } |
278 | | |
279 | | |
280 | | bool llvm::CC_PPC64_ELF(unsigned ValNo, MVT ValVT, |
281 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
282 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
283 | |
|
284 | 0 | if (State.getCallingConv() == CallingConv::AnyReg) { |
285 | 0 | if (!CC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
286 | 0 | return false; |
287 | 0 | } |
288 | | |
289 | 0 | if (LocVT == MVT::i1) { |
290 | 0 | LocVT = MVT::i64; |
291 | 0 | if (ArgFlags.isSExt()) |
292 | 0 | LocInfo = CCValAssign::SExt; |
293 | 0 | else if (ArgFlags.isZExt()) |
294 | 0 | LocInfo = CCValAssign::ZExt; |
295 | 0 | else |
296 | 0 | LocInfo = CCValAssign::AExt; |
297 | 0 | } |
298 | |
|
299 | 0 | if (LocVT == MVT::i8) { |
300 | 0 | LocVT = MVT::i64; |
301 | 0 | if (ArgFlags.isSExt()) |
302 | 0 | LocInfo = CCValAssign::SExt; |
303 | 0 | else if (ArgFlags.isZExt()) |
304 | 0 | LocInfo = CCValAssign::ZExt; |
305 | 0 | else |
306 | 0 | LocInfo = CCValAssign::AExt; |
307 | 0 | } |
308 | |
|
309 | 0 | if (LocVT == MVT::i16) { |
310 | 0 | LocVT = MVT::i64; |
311 | 0 | if (ArgFlags.isSExt()) |
312 | 0 | LocInfo = CCValAssign::SExt; |
313 | 0 | else if (ArgFlags.isZExt()) |
314 | 0 | LocInfo = CCValAssign::ZExt; |
315 | 0 | else |
316 | 0 | LocInfo = CCValAssign::AExt; |
317 | 0 | } |
318 | |
|
319 | 0 | if (LocVT == MVT::i32) { |
320 | 0 | LocVT = MVT::i64; |
321 | 0 | if (ArgFlags.isSExt()) |
322 | 0 | LocInfo = CCValAssign::SExt; |
323 | 0 | else if (ArgFlags.isZExt()) |
324 | 0 | LocInfo = CCValAssign::ZExt; |
325 | 0 | else |
326 | 0 | LocInfo = CCValAssign::AExt; |
327 | 0 | } |
328 | |
|
329 | 0 | if (LocVT == MVT::i64) { |
330 | 0 | static const MCPhysReg RegList1[] = { |
331 | 0 | PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10 |
332 | 0 | }; |
333 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
334 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
335 | 0 | return false; |
336 | 0 | } |
337 | 0 | } |
338 | | |
339 | 0 | if (LocVT == MVT::f32 || |
340 | 0 | LocVT == MVT::f64) { |
341 | 0 | if (!State.isVarArg()) { |
342 | 0 | if (CC_PPC64_ELF_Shadow_GPR_Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
343 | 0 | return false; |
344 | 0 | } |
345 | 0 | } |
346 | | |
347 | 0 | if (LocVT == MVT::f32 || |
348 | 0 | LocVT == MVT::f64) { |
349 | 0 | if (!State.isVarArg()) { |
350 | 0 | static const MCPhysReg RegList2[] = { |
351 | 0 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 |
352 | 0 | }; |
353 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
354 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
355 | 0 | return false; |
356 | 0 | } |
357 | 0 | } |
358 | 0 | } |
359 | | |
360 | 0 | if (LocVT == MVT::f128) { |
361 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
362 | 0 | if (!State.isVarArg()) { |
363 | 0 | if (CC_PPC64_ELF_Shadow_GPR_Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
364 | 0 | return false; |
365 | 0 | } |
366 | 0 | } |
367 | 0 | } |
368 | | |
369 | 0 | if (LocVT == MVT::f128) { |
370 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
371 | 0 | if (!State.isVarArg()) { |
372 | 0 | static const MCPhysReg RegList3[] = { |
373 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
374 | 0 | }; |
375 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
376 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
377 | 0 | return false; |
378 | 0 | } |
379 | 0 | } |
380 | 0 | } |
381 | 0 | } |
382 | | |
383 | 0 | if (LocVT == MVT::v16i8 || |
384 | 0 | LocVT == MVT::v8i16 || |
385 | 0 | LocVT == MVT::v4i32 || |
386 | 0 | LocVT == MVT::v2i64 || |
387 | 0 | LocVT == MVT::v4f32 || |
388 | 0 | LocVT == MVT::v2f64 || |
389 | 0 | LocVT == MVT::v1i128) { |
390 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
391 | 0 | if (!State.isVarArg()) { |
392 | 0 | if (CC_PPC64_ELF_Shadow_GPR_Regs(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
393 | 0 | return false; |
394 | 0 | } |
395 | 0 | } |
396 | 0 | } |
397 | | |
398 | 0 | if (LocVT == MVT::v16i8 || |
399 | 0 | LocVT == MVT::v8i16 || |
400 | 0 | LocVT == MVT::v4i32 || |
401 | 0 | LocVT == MVT::v2i64 || |
402 | 0 | LocVT == MVT::v4f32 || |
403 | 0 | LocVT == MVT::v2f64 || |
404 | 0 | LocVT == MVT::v1i128) { |
405 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
406 | 0 | if (!State.isVarArg()) { |
407 | 0 | static const MCPhysReg RegList4[] = { |
408 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13 |
409 | 0 | }; |
410 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
411 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
412 | 0 | return false; |
413 | 0 | } |
414 | 0 | } |
415 | 0 | } |
416 | 0 | } |
417 | | |
418 | 0 | return true; // CC didn't match. |
419 | 0 | } |
420 | | |
421 | | |
422 | | bool llvm::CC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, |
423 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
424 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
425 | |
|
426 | 0 | if (State.getCallingConv() == CallingConv::AnyReg) { |
427 | 0 | if (!CC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
428 | 0 | return false; |
429 | 0 | } |
430 | | |
431 | 0 | if (LocVT == MVT::i1) { |
432 | 0 | LocVT = MVT::i64; |
433 | 0 | if (ArgFlags.isSExt()) |
434 | 0 | LocInfo = CCValAssign::SExt; |
435 | 0 | else if (ArgFlags.isZExt()) |
436 | 0 | LocInfo = CCValAssign::ZExt; |
437 | 0 | else |
438 | 0 | LocInfo = CCValAssign::AExt; |
439 | 0 | } |
440 | |
|
441 | 0 | if (LocVT == MVT::i8) { |
442 | 0 | LocVT = MVT::i64; |
443 | 0 | if (ArgFlags.isSExt()) |
444 | 0 | LocInfo = CCValAssign::SExt; |
445 | 0 | else if (ArgFlags.isZExt()) |
446 | 0 | LocInfo = CCValAssign::ZExt; |
447 | 0 | else |
448 | 0 | LocInfo = CCValAssign::AExt; |
449 | 0 | } |
450 | |
|
451 | 0 | if (LocVT == MVT::i16) { |
452 | 0 | LocVT = MVT::i64; |
453 | 0 | if (ArgFlags.isSExt()) |
454 | 0 | LocInfo = CCValAssign::SExt; |
455 | 0 | else if (ArgFlags.isZExt()) |
456 | 0 | LocInfo = CCValAssign::ZExt; |
457 | 0 | else |
458 | 0 | LocInfo = CCValAssign::AExt; |
459 | 0 | } |
460 | |
|
461 | 0 | if (LocVT == MVT::i32) { |
462 | 0 | LocVT = MVT::i64; |
463 | 0 | if (ArgFlags.isSExt()) |
464 | 0 | LocInfo = CCValAssign::SExt; |
465 | 0 | else if (ArgFlags.isZExt()) |
466 | 0 | LocInfo = CCValAssign::ZExt; |
467 | 0 | else |
468 | 0 | LocInfo = CCValAssign::AExt; |
469 | 0 | } |
470 | |
|
471 | 0 | if (LocVT == MVT::i64) { |
472 | 0 | static const MCPhysReg RegList1[] = { |
473 | 0 | PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10 |
474 | 0 | }; |
475 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
476 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
477 | 0 | return false; |
478 | 0 | } |
479 | 0 | } |
480 | | |
481 | 0 | if (LocVT == MVT::f32 || |
482 | 0 | LocVT == MVT::f64) { |
483 | 0 | static const MCPhysReg RegList2[] = { |
484 | 0 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 |
485 | 0 | }; |
486 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
487 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
488 | 0 | return false; |
489 | 0 | } |
490 | 0 | } |
491 | | |
492 | 0 | return true; // CC didn't match. |
493 | 0 | } |
494 | | |
495 | | |
496 | | bool llvm::RetCC_PPC(unsigned ValNo, MVT ValVT, |
497 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
498 | 102k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
499 | | |
500 | 102k | if (State.getCallingConv() == CallingConv::AnyReg) { |
501 | 0 | if (!RetCC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
502 | 0 | return false; |
503 | 0 | } |
504 | | |
505 | 102k | if (LocVT == MVT::i32 || |
506 | 102k | LocVT == MVT::i1) { |
507 | 51.0k | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) { |
508 | 51.0k | LocVT = MVT::i64; |
509 | 51.0k | if (ArgFlags.isSExt()) |
510 | 49 | LocInfo = CCValAssign::SExt; |
511 | 51.0k | else if (ArgFlags.isZExt()) |
512 | 2.08k | LocInfo = CCValAssign::ZExt; |
513 | 48.9k | else |
514 | 48.9k | LocInfo = CCValAssign::AExt; |
515 | 51.0k | } |
516 | 51.0k | } |
517 | | |
518 | 102k | if (LocVT == MVT::i1) { |
519 | 0 | if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) { |
520 | 0 | LocVT = MVT::i32; |
521 | 0 | if (ArgFlags.isSExt()) |
522 | 0 | LocInfo = CCValAssign::SExt; |
523 | 0 | else if (ArgFlags.isZExt()) |
524 | 0 | LocInfo = CCValAssign::ZExt; |
525 | 0 | else |
526 | 0 | LocInfo = CCValAssign::AExt; |
527 | 0 | } |
528 | 0 | } |
529 | | |
530 | 102k | if (LocVT == MVT::i32) { |
531 | 0 | static const MCPhysReg RegList1[] = { |
532 | 0 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10 |
533 | 0 | }; |
534 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
535 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
536 | 0 | return false; |
537 | 0 | } |
538 | 0 | } |
539 | | |
540 | 102k | if (LocVT == MVT::i64) { |
541 | 73.9k | static const MCPhysReg RegList2[] = { |
542 | 73.9k | PPC::X3, PPC::X4, PPC::X5, PPC::X6 |
543 | 73.9k | }; |
544 | 73.9k | if (unsigned Reg = State.AllocateReg(RegList2)) { |
545 | 71.5k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
546 | 71.5k | return false; |
547 | 71.5k | } |
548 | 73.9k | } |
549 | | |
550 | 30.9k | if (LocVT == MVT::i128) { |
551 | 0 | static const MCPhysReg RegList3[] = { |
552 | 0 | PPC::X3, PPC::X4, PPC::X5, PPC::X6 |
553 | 0 | }; |
554 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
555 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
556 | 0 | return false; |
557 | 0 | } |
558 | 0 | } |
559 | | |
560 | 30.9k | if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
561 | 30.9k | if (LocVT == MVT::f32) { |
562 | 17.2k | static const MCPhysReg RegList4[] = { |
563 | 17.2k | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 |
564 | 17.2k | }; |
565 | 17.2k | if (unsigned Reg = State.AllocateReg(RegList4)) { |
566 | 17.1k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
567 | 17.1k | return false; |
568 | 17.1k | } |
569 | 17.2k | } |
570 | 30.9k | } |
571 | | |
572 | 13.7k | if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
573 | 13.7k | if (LocVT == MVT::f64) { |
574 | 11.3k | static const MCPhysReg RegList5[] = { |
575 | 11.3k | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 |
576 | 11.3k | }; |
577 | 11.3k | if (unsigned Reg = State.AllocateReg(RegList5)) { |
578 | 11.3k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
579 | 11.3k | return false; |
580 | 11.3k | } |
581 | 11.3k | } |
582 | 13.7k | } |
583 | | |
584 | 2.42k | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
585 | 0 | if (LocVT == MVT::f32) { |
586 | 0 | static const MCPhysReg RegList6[] = { |
587 | 0 | PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10 |
588 | 0 | }; |
589 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
590 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
591 | 0 | return false; |
592 | 0 | } |
593 | 0 | } |
594 | 0 | } |
595 | | |
596 | 2.42k | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasSPE()) { |
597 | 0 | if (LocVT == MVT::f64) { |
598 | 0 | if (CC_PPC32_SPE_RetF64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
599 | 0 | return false; |
600 | 0 | } |
601 | 0 | } |
602 | | |
603 | 2.42k | if (LocVT == MVT::f128) { |
604 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
605 | 0 | static const MCPhysReg RegList7[] = { |
606 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 |
607 | 0 | }; |
608 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
609 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
610 | 0 | return false; |
611 | 0 | } |
612 | 0 | } |
613 | 0 | } |
614 | | |
615 | 2.42k | if (LocVT == MVT::v16i8 || |
616 | 2.42k | LocVT == MVT::v8i16 || |
617 | 2.42k | LocVT == MVT::v4i32 || |
618 | 2.42k | LocVT == MVT::v2i64 || |
619 | 2.42k | LocVT == MVT::v1i128 || |
620 | 2.42k | LocVT == MVT::v4f32 || |
621 | 2.42k | LocVT == MVT::v2f64) { |
622 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
623 | 0 | static const MCPhysReg RegList8[] = { |
624 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 |
625 | 0 | }; |
626 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
627 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
628 | 0 | return false; |
629 | 0 | } |
630 | 0 | } |
631 | 0 | } |
632 | | |
633 | 2.42k | return true; // CC didn't match. |
634 | 2.42k | } |
635 | | |
636 | | |
637 | | static bool RetCC_PPC64_AnyReg(unsigned ValNo, MVT ValVT, |
638 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
639 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
640 | |
|
641 | 0 | if (CC_PPC_AnyReg_Error(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
642 | 0 | return false; |
643 | | |
644 | 0 | return true; // CC didn't match. |
645 | 0 | } |
646 | | |
647 | | |
648 | | bool llvm::RetCC_PPC64_ELF_FIS(unsigned ValNo, MVT ValVT, |
649 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
650 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
651 | |
|
652 | 0 | if (State.getCallingConv() == CallingConv::AnyReg) { |
653 | 0 | if (!RetCC_PPC64_AnyReg(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
654 | 0 | return false; |
655 | 0 | } |
656 | | |
657 | 0 | if (LocVT == MVT::i1) { |
658 | 0 | LocVT = MVT::i64; |
659 | 0 | if (ArgFlags.isSExt()) |
660 | 0 | LocInfo = CCValAssign::SExt; |
661 | 0 | else if (ArgFlags.isZExt()) |
662 | 0 | LocInfo = CCValAssign::ZExt; |
663 | 0 | else |
664 | 0 | LocInfo = CCValAssign::AExt; |
665 | 0 | } |
666 | |
|
667 | 0 | if (LocVT == MVT::i8) { |
668 | 0 | LocVT = MVT::i64; |
669 | 0 | if (ArgFlags.isSExt()) |
670 | 0 | LocInfo = CCValAssign::SExt; |
671 | 0 | else if (ArgFlags.isZExt()) |
672 | 0 | LocInfo = CCValAssign::ZExt; |
673 | 0 | else |
674 | 0 | LocInfo = CCValAssign::AExt; |
675 | 0 | } |
676 | |
|
677 | 0 | if (LocVT == MVT::i16) { |
678 | 0 | LocVT = MVT::i64; |
679 | 0 | if (ArgFlags.isSExt()) |
680 | 0 | LocInfo = CCValAssign::SExt; |
681 | 0 | else if (ArgFlags.isZExt()) |
682 | 0 | LocInfo = CCValAssign::ZExt; |
683 | 0 | else |
684 | 0 | LocInfo = CCValAssign::AExt; |
685 | 0 | } |
686 | |
|
687 | 0 | if (LocVT == MVT::i32) { |
688 | 0 | LocVT = MVT::i64; |
689 | 0 | if (ArgFlags.isSExt()) |
690 | 0 | LocInfo = CCValAssign::SExt; |
691 | 0 | else if (ArgFlags.isZExt()) |
692 | 0 | LocInfo = CCValAssign::ZExt; |
693 | 0 | else |
694 | 0 | LocInfo = CCValAssign::AExt; |
695 | 0 | } |
696 | |
|
697 | 0 | if (LocVT == MVT::i64) { |
698 | 0 | static const MCPhysReg RegList1[] = { |
699 | 0 | PPC::X3, PPC::X4, PPC::X5, PPC::X6 |
700 | 0 | }; |
701 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
702 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
703 | 0 | return false; |
704 | 0 | } |
705 | 0 | } |
706 | | |
707 | 0 | if (LocVT == MVT::i128) { |
708 | 0 | static const MCPhysReg RegList2[] = { |
709 | 0 | PPC::X3, PPC::X4, PPC::X5, PPC::X6 |
710 | 0 | }; |
711 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
712 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
713 | 0 | return false; |
714 | 0 | } |
715 | 0 | } |
716 | | |
717 | 0 | if (LocVT == MVT::f32) { |
718 | 0 | static const MCPhysReg RegList3[] = { |
719 | 0 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 |
720 | 0 | }; |
721 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
722 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
723 | 0 | return false; |
724 | 0 | } |
725 | 0 | } |
726 | | |
727 | 0 | if (LocVT == MVT::f64) { |
728 | 0 | static const MCPhysReg RegList4[] = { |
729 | 0 | PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8 |
730 | 0 | }; |
731 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
732 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
733 | 0 | return false; |
734 | 0 | } |
735 | 0 | } |
736 | | |
737 | 0 | if (LocVT == MVT::f128) { |
738 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
739 | 0 | static const MCPhysReg RegList5[] = { |
740 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 |
741 | 0 | }; |
742 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
743 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
744 | 0 | return false; |
745 | 0 | } |
746 | 0 | } |
747 | 0 | } |
748 | | |
749 | 0 | if (LocVT == MVT::v16i8 || |
750 | 0 | LocVT == MVT::v8i16 || |
751 | 0 | LocVT == MVT::v4i32 || |
752 | 0 | LocVT == MVT::v2i64 || |
753 | 0 | LocVT == MVT::v1i128 || |
754 | 0 | LocVT == MVT::v4f32 || |
755 | 0 | LocVT == MVT::v2f64) { |
756 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
757 | 0 | static const MCPhysReg RegList6[] = { |
758 | 0 | PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 |
759 | 0 | }; |
760 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
761 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
762 | 0 | return false; |
763 | 0 | } |
764 | 0 | } |
765 | 0 | } |
766 | | |
767 | 0 | return true; // CC didn't match. |
768 | 0 | } |
769 | | |
770 | | |
771 | | bool llvm::RetCC_PPC_Cold(unsigned ValNo, MVT ValVT, |
772 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
773 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
774 | |
|
775 | 0 | if (LocVT == MVT::i32 || |
776 | 0 | LocVT == MVT::i1) { |
777 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) { |
778 | 0 | LocVT = MVT::i64; |
779 | 0 | if (ArgFlags.isSExt()) |
780 | 0 | LocInfo = CCValAssign::SExt; |
781 | 0 | else if (ArgFlags.isZExt()) |
782 | 0 | LocInfo = CCValAssign::ZExt; |
783 | 0 | else |
784 | 0 | LocInfo = CCValAssign::AExt; |
785 | 0 | } |
786 | 0 | } |
787 | |
|
788 | 0 | if (LocVT == MVT::i1) { |
789 | 0 | if (!static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).isPPC64()) { |
790 | 0 | LocVT = MVT::i32; |
791 | 0 | if (ArgFlags.isSExt()) |
792 | 0 | LocInfo = CCValAssign::SExt; |
793 | 0 | else if (ArgFlags.isZExt()) |
794 | 0 | LocInfo = CCValAssign::ZExt; |
795 | 0 | else |
796 | 0 | LocInfo = CCValAssign::AExt; |
797 | 0 | } |
798 | 0 | } |
799 | |
|
800 | 0 | if (LocVT == MVT::i32) { |
801 | 0 | if (unsigned Reg = State.AllocateReg(PPC::R3)) { |
802 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
803 | 0 | return false; |
804 | 0 | } |
805 | 0 | } |
806 | | |
807 | 0 | if (LocVT == MVT::i64) { |
808 | 0 | if (unsigned Reg = State.AllocateReg(PPC::X3)) { |
809 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
810 | 0 | return false; |
811 | 0 | } |
812 | 0 | } |
813 | | |
814 | 0 | if (LocVT == MVT::i128) { |
815 | 0 | if (unsigned Reg = State.AllocateReg(PPC::X3)) { |
816 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
817 | 0 | return false; |
818 | 0 | } |
819 | 0 | } |
820 | | |
821 | 0 | if (LocVT == MVT::f32) { |
822 | 0 | if (unsigned Reg = State.AllocateReg(PPC::F1)) { |
823 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
824 | 0 | return false; |
825 | 0 | } |
826 | 0 | } |
827 | | |
828 | 0 | if (LocVT == MVT::f64) { |
829 | 0 | if (unsigned Reg = State.AllocateReg(PPC::F1)) { |
830 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
831 | 0 | return false; |
832 | 0 | } |
833 | 0 | } |
834 | | |
835 | 0 | if (LocVT == MVT::f128) { |
836 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
837 | 0 | if (unsigned Reg = State.AllocateReg(PPC::V2)) { |
838 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
839 | 0 | return false; |
840 | 0 | } |
841 | 0 | } |
842 | 0 | } |
843 | | |
844 | 0 | if (LocVT == MVT::v16i8 || |
845 | 0 | LocVT == MVT::v8i16 || |
846 | 0 | LocVT == MVT::v4i32 || |
847 | 0 | LocVT == MVT::v2i64 || |
848 | 0 | LocVT == MVT::v1i128 || |
849 | 0 | LocVT == MVT::v4f32 || |
850 | 0 | LocVT == MVT::v2f64) { |
851 | 0 | if (static_cast<const PPCSubtarget&>(State.getMachineFunction().getSubtarget()).hasAltivec()) { |
852 | 0 | if (unsigned Reg = State.AllocateReg(PPC::V2)) { |
853 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
854 | 0 | return false; |
855 | 0 | } |
856 | 0 | } |
857 | 0 | } |
858 | | |
859 | 0 | return true; // CC didn't match. |
860 | 0 | } |
861 | | |
862 | | #else |
863 | | |
864 | | const MCRegister CC_PPC32_SVR4_ArgRegs[] = { PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9 }; |
865 | | const MCRegister CC_PPC32_SVR4_ByVal_ArgRegs[] = { 0 }; |
866 | | const MCRegister CC_PPC32_SVR4_Common_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::R10, PPC::R11, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9 }; |
867 | | const MCRegister CC_PPC32_SVR4_VarArg_ArgRegs[] = { 0 }; |
868 | | const MCRegister CC_PPC64_AnyReg_ArgRegs[] = { 0 }; |
869 | | const MCRegister CC_PPC64_ELF_ArgRegs[] = { PPC::F1, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X10, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9 }; |
870 | | const MCRegister CC_PPC64_ELF_FIS_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::X10, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9 }; |
871 | | const MCRegister RetCC_PPC_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::R10, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X3, PPC::X4, PPC::X5, PPC::X6 }; |
872 | | const MCRegister RetCC_PPC64_AnyReg_ArgRegs[] = { 0 }; |
873 | | const MCRegister RetCC_PPC64_ELF_FIS_ArgRegs[] = { PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::X3, PPC::X4, PPC::X5, PPC::X6 }; |
874 | | const MCRegister RetCC_PPC_Cold_ArgRegs[] = { PPC::F1, PPC::R3, PPC::V2, PPC::X3 }; |
875 | | |
876 | | #endif // CC_REGISTER_LIST |