/src/build/lib/Target/PowerPC/PPCGenFastISel.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* "Fast" Instruction Selector for the PPC target *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | |
10 | | // FastEmit Immediate Predicate functions. |
11 | 0 | static bool Predicate_imm32SExt16(int64_t Imm) { |
12 | | |
13 | | // imm32SExt16 predicate - True if the i32 immediate fits in a 16-bit |
14 | | // sign extended field. Used by instructions like 'addi'. |
15 | 0 | return (int32_t)Imm == (short)Imm; |
16 | |
|
17 | 0 | } |
18 | 0 | static bool Predicate_imm64SExt16(int64_t Imm) { |
19 | | |
20 | | // imm64SExt16 predicate - True if the i64 immediate fits in a 16-bit |
21 | | // sign extended field. Used by instructions like 'addi'. |
22 | 0 | return (int64_t)Imm == (short)Imm; |
23 | |
|
24 | 0 | } |
25 | 0 | static bool Predicate_immSExt5NonZero(int64_t Imm) { |
26 | 0 | return Imm && isInt<5>(Imm); |
27 | 0 | } |
28 | 0 | static bool Predicate_i32immNonAllOneNonZero(int64_t Imm) { |
29 | 0 | return Imm && (Imm != -1); |
30 | 0 | } |
31 | | |
32 | | |
33 | | // FastEmit functions for ISD::READCYCLECOUNTER. |
34 | | |
35 | 0 | unsigned fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(MVT RetVT) { |
36 | 0 | if (RetVT.SimpleTy != MVT::i64) |
37 | 0 | return 0; |
38 | 0 | return fastEmitInst_(PPC::MFTB8, &PPC::G8RCRegClass); |
39 | 0 | } |
40 | | |
41 | 0 | unsigned fastEmit_ISD_READCYCLECOUNTER_(MVT VT, MVT RetVT) { |
42 | 0 | switch (VT.SimpleTy) { |
43 | 0 | case MVT::i64: return fastEmit_ISD_READCYCLECOUNTER_MVT_i64_(RetVT); |
44 | 0 | default: return 0; |
45 | 0 | } |
46 | 0 | } |
47 | | |
48 | | // FastEmit functions for PPCISD::GET_TPOINTER. |
49 | | |
50 | 0 | unsigned fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(MVT RetVT) { |
51 | 0 | if (RetVT.SimpleTy != MVT::i32) |
52 | 0 | return 0; |
53 | 0 | return fastEmitInst_(PPC::GETtlsTpointer32AIX, &PPC::GPRCRegClass); |
54 | 0 | } |
55 | | |
56 | 0 | unsigned fastEmit_PPCISD_GET_TPOINTER_(MVT VT, MVT RetVT) { |
57 | 0 | switch (VT.SimpleTy) { |
58 | 0 | case MVT::i32: return fastEmit_PPCISD_GET_TPOINTER_MVT_i32_(RetVT); |
59 | 0 | default: return 0; |
60 | 0 | } |
61 | 0 | } |
62 | | |
63 | | // FastEmit functions for PPCISD::MFFS. |
64 | | |
65 | 0 | unsigned fastEmit_PPCISD_MFFS_MVT_f64_(MVT RetVT) { |
66 | 0 | if (RetVT.SimpleTy != MVT::f64) |
67 | 0 | return 0; |
68 | 0 | if ((Subtarget->hasFPU())) { |
69 | 0 | return fastEmitInst_(PPC::MFFS, &PPC::F8RCRegClass); |
70 | 0 | } |
71 | 0 | return 0; |
72 | 0 | } |
73 | | |
74 | 0 | unsigned fastEmit_PPCISD_MFFS_(MVT VT, MVT RetVT) { |
75 | 0 | switch (VT.SimpleTy) { |
76 | 0 | case MVT::f64: return fastEmit_PPCISD_MFFS_MVT_f64_(RetVT); |
77 | 0 | default: return 0; |
78 | 0 | } |
79 | 0 | } |
80 | | |
81 | | // FastEmit functions for PPCISD::PPC32_GOT. |
82 | | |
83 | 0 | unsigned fastEmit_PPCISD_PPC32_GOT_MVT_i32_(MVT RetVT) { |
84 | 0 | if (RetVT.SimpleTy != MVT::i32) |
85 | 0 | return 0; |
86 | 0 | return fastEmitInst_(PPC::PPC32GOT, &PPC::GPRCRegClass); |
87 | 0 | } |
88 | | |
89 | 0 | unsigned fastEmit_PPCISD_PPC32_GOT_(MVT VT, MVT RetVT) { |
90 | 0 | switch (VT.SimpleTy) { |
91 | 0 | case MVT::i32: return fastEmit_PPCISD_PPC32_GOT_MVT_i32_(RetVT); |
92 | 0 | default: return 0; |
93 | 0 | } |
94 | 0 | } |
95 | | |
96 | | // Top-level FastEmit function. |
97 | | |
98 | 0 | unsigned fastEmit_(MVT VT, MVT RetVT, unsigned Opcode) override { |
99 | 0 | switch (Opcode) { |
100 | 0 | case ISD::READCYCLECOUNTER: return fastEmit_ISD_READCYCLECOUNTER_(VT, RetVT); |
101 | 0 | case PPCISD::GET_TPOINTER: return fastEmit_PPCISD_GET_TPOINTER_(VT, RetVT); |
102 | 0 | case PPCISD::MFFS: return fastEmit_PPCISD_MFFS_(VT, RetVT); |
103 | 0 | case PPCISD::PPC32_GOT: return fastEmit_PPCISD_PPC32_GOT_(VT, RetVT); |
104 | 0 | default: return 0; |
105 | 0 | } |
106 | 0 | } |
107 | | |
108 | | // FastEmit functions for ISD::ANY_EXTEND. |
109 | | |
110 | 0 | unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { |
111 | 0 | if ((Subtarget->isISA3_1())) { |
112 | 0 | return fastEmitInst_r(PPC::SETBC, &PPC::GPRCRegClass, Op0); |
113 | 0 | } |
114 | 0 | return 0; |
115 | 0 | } |
116 | | |
117 | 0 | unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { |
118 | 0 | if ((Subtarget->isISA3_1())) { |
119 | 0 | return fastEmitInst_r(PPC::SETBC8, &PPC::G8RCRegClass, Op0); |
120 | 0 | } |
121 | 0 | return 0; |
122 | 0 | } |
123 | | |
124 | 0 | unsigned fastEmit_ISD_ANY_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { |
125 | 0 | switch (RetVT.SimpleTy) { |
126 | 0 | case MVT::i32: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i32_r(Op0); |
127 | 0 | case MVT::i64: return fastEmit_ISD_ANY_EXTEND_MVT_i1_MVT_i64_r(Op0); |
128 | 0 | default: return 0; |
129 | 0 | } |
130 | 0 | } |
131 | | |
132 | 0 | unsigned fastEmit_ISD_ANY_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
133 | 0 | switch (VT.SimpleTy) { |
134 | 0 | case MVT::i1: return fastEmit_ISD_ANY_EXTEND_MVT_i1_r(RetVT, Op0); |
135 | 0 | default: return 0; |
136 | 0 | } |
137 | 0 | } |
138 | | |
139 | | // FastEmit functions for ISD::BITCAST. |
140 | | |
141 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_i64_r(MVT RetVT, unsigned Op0) { |
142 | 0 | if (RetVT.SimpleTy != MVT::f64) |
143 | 0 | return 0; |
144 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
145 | 0 | return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0); |
146 | 0 | } |
147 | 0 | return 0; |
148 | 0 | } |
149 | | |
150 | 0 | unsigned fastEmit_ISD_BITCAST_MVT_f64_r(MVT RetVT, unsigned Op0) { |
151 | 0 | if (RetVT.SimpleTy != MVT::i64) |
152 | 0 | return 0; |
153 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
154 | 0 | return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0); |
155 | 0 | } |
156 | 0 | return 0; |
157 | 0 | } |
158 | | |
159 | 0 | unsigned fastEmit_ISD_BITCAST_r(MVT VT, MVT RetVT, unsigned Op0) { |
160 | 0 | switch (VT.SimpleTy) { |
161 | 0 | case MVT::i64: return fastEmit_ISD_BITCAST_MVT_i64_r(RetVT, Op0); |
162 | 0 | case MVT::f64: return fastEmit_ISD_BITCAST_MVT_f64_r(RetVT, Op0); |
163 | 0 | default: return 0; |
164 | 0 | } |
165 | 0 | } |
166 | | |
167 | | // FastEmit functions for ISD::BSWAP. |
168 | | |
169 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
170 | 0 | if (RetVT.SimpleTy != MVT::i32) |
171 | 0 | return 0; |
172 | 0 | if ((Subtarget->isISA3_1())) { |
173 | 0 | return fastEmitInst_r(PPC::BRW, &PPC::GPRCRegClass, Op0); |
174 | 0 | } |
175 | 0 | return 0; |
176 | 0 | } |
177 | | |
178 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
179 | 0 | if (RetVT.SimpleTy != MVT::i64) |
180 | 0 | return 0; |
181 | 0 | if ((Subtarget->isISA3_1())) { |
182 | 0 | return fastEmitInst_r(PPC::BRD, &PPC::G8RCRegClass, Op0); |
183 | 0 | } |
184 | 0 | return 0; |
185 | 0 | } |
186 | | |
187 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
188 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
189 | 0 | return 0; |
190 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
191 | 0 | return fastEmitInst_r(PPC::XXBRW, &PPC::VSRCRegClass, Op0); |
192 | 0 | } |
193 | 0 | return 0; |
194 | 0 | } |
195 | | |
196 | 0 | unsigned fastEmit_ISD_BSWAP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
197 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
198 | 0 | return 0; |
199 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
200 | 0 | return fastEmitInst_r(PPC::XXBRD, &PPC::VSRCRegClass, Op0); |
201 | 0 | } |
202 | 0 | return 0; |
203 | 0 | } |
204 | | |
205 | 0 | unsigned fastEmit_ISD_BSWAP_r(MVT VT, MVT RetVT, unsigned Op0) { |
206 | 0 | switch (VT.SimpleTy) { |
207 | 0 | case MVT::i32: return fastEmit_ISD_BSWAP_MVT_i32_r(RetVT, Op0); |
208 | 0 | case MVT::i64: return fastEmit_ISD_BSWAP_MVT_i64_r(RetVT, Op0); |
209 | 0 | case MVT::v4i32: return fastEmit_ISD_BSWAP_MVT_v4i32_r(RetVT, Op0); |
210 | 0 | case MVT::v2i64: return fastEmit_ISD_BSWAP_MVT_v2i64_r(RetVT, Op0); |
211 | 0 | default: return 0; |
212 | 0 | } |
213 | 0 | } |
214 | | |
215 | | // FastEmit functions for ISD::CTLZ. |
216 | | |
217 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
218 | 0 | if (RetVT.SimpleTy != MVT::i32) |
219 | 0 | return 0; |
220 | 0 | return fastEmitInst_r(PPC::CNTLZW, &PPC::GPRCRegClass, Op0); |
221 | 0 | } |
222 | | |
223 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
224 | 0 | if (RetVT.SimpleTy != MVT::i64) |
225 | 0 | return 0; |
226 | 0 | return fastEmitInst_r(PPC::CNTLZD, &PPC::G8RCRegClass, Op0); |
227 | 0 | } |
228 | | |
229 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
230 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
231 | 0 | return 0; |
232 | 0 | if ((Subtarget->hasP8Altivec())) { |
233 | 0 | return fastEmitInst_r(PPC::VCLZB, &PPC::VRRCRegClass, Op0); |
234 | 0 | } |
235 | 0 | return 0; |
236 | 0 | } |
237 | | |
238 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
239 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
240 | 0 | return 0; |
241 | 0 | if ((Subtarget->hasP8Altivec())) { |
242 | 0 | return fastEmitInst_r(PPC::VCLZH, &PPC::VRRCRegClass, Op0); |
243 | 0 | } |
244 | 0 | return 0; |
245 | 0 | } |
246 | | |
247 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
248 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
249 | 0 | return 0; |
250 | 0 | if ((Subtarget->hasP8Altivec())) { |
251 | 0 | return fastEmitInst_r(PPC::VCLZW, &PPC::VRRCRegClass, Op0); |
252 | 0 | } |
253 | 0 | return 0; |
254 | 0 | } |
255 | | |
256 | 0 | unsigned fastEmit_ISD_CTLZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
257 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
258 | 0 | return 0; |
259 | 0 | if ((Subtarget->hasP8Altivec())) { |
260 | 0 | return fastEmitInst_r(PPC::VCLZD, &PPC::VRRCRegClass, Op0); |
261 | 0 | } |
262 | 0 | return 0; |
263 | 0 | } |
264 | | |
265 | 0 | unsigned fastEmit_ISD_CTLZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
266 | 0 | switch (VT.SimpleTy) { |
267 | 0 | case MVT::i32: return fastEmit_ISD_CTLZ_MVT_i32_r(RetVT, Op0); |
268 | 0 | case MVT::i64: return fastEmit_ISD_CTLZ_MVT_i64_r(RetVT, Op0); |
269 | 0 | case MVT::v16i8: return fastEmit_ISD_CTLZ_MVT_v16i8_r(RetVT, Op0); |
270 | 0 | case MVT::v8i16: return fastEmit_ISD_CTLZ_MVT_v8i16_r(RetVT, Op0); |
271 | 0 | case MVT::v4i32: return fastEmit_ISD_CTLZ_MVT_v4i32_r(RetVT, Op0); |
272 | 0 | case MVT::v2i64: return fastEmit_ISD_CTLZ_MVT_v2i64_r(RetVT, Op0); |
273 | 0 | default: return 0; |
274 | 0 | } |
275 | 0 | } |
276 | | |
277 | | // FastEmit functions for ISD::CTPOP. |
278 | | |
279 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
280 | 0 | if (RetVT.SimpleTy != MVT::i32) |
281 | 0 | return 0; |
282 | 0 | return fastEmitInst_r(PPC::POPCNTW, &PPC::GPRCRegClass, Op0); |
283 | 0 | } |
284 | | |
285 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_i64_r(MVT RetVT, unsigned Op0) { |
286 | 0 | if (RetVT.SimpleTy != MVT::i64) |
287 | 0 | return 0; |
288 | 0 | return fastEmitInst_r(PPC::POPCNTD, &PPC::G8RCRegClass, Op0); |
289 | 0 | } |
290 | | |
291 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
292 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
293 | 0 | return 0; |
294 | 0 | if ((Subtarget->hasP8Altivec())) { |
295 | 0 | return fastEmitInst_r(PPC::VPOPCNTB, &PPC::VRRCRegClass, Op0); |
296 | 0 | } |
297 | 0 | return 0; |
298 | 0 | } |
299 | | |
300 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
301 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
302 | 0 | return 0; |
303 | 0 | if ((Subtarget->hasP8Altivec())) { |
304 | 0 | return fastEmitInst_r(PPC::VPOPCNTH, &PPC::VRRCRegClass, Op0); |
305 | 0 | } |
306 | 0 | return 0; |
307 | 0 | } |
308 | | |
309 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
310 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
311 | 0 | return 0; |
312 | 0 | if ((Subtarget->hasP8Altivec())) { |
313 | 0 | return fastEmitInst_r(PPC::VPOPCNTW, &PPC::VRRCRegClass, Op0); |
314 | 0 | } |
315 | 0 | return 0; |
316 | 0 | } |
317 | | |
318 | 0 | unsigned fastEmit_ISD_CTPOP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
319 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
320 | 0 | return 0; |
321 | 0 | if ((Subtarget->hasP8Altivec())) { |
322 | 0 | return fastEmitInst_r(PPC::VPOPCNTD, &PPC::VRRCRegClass, Op0); |
323 | 0 | } |
324 | 0 | return 0; |
325 | 0 | } |
326 | | |
327 | 0 | unsigned fastEmit_ISD_CTPOP_r(MVT VT, MVT RetVT, unsigned Op0) { |
328 | 0 | switch (VT.SimpleTy) { |
329 | 0 | case MVT::i32: return fastEmit_ISD_CTPOP_MVT_i32_r(RetVT, Op0); |
330 | 0 | case MVT::i64: return fastEmit_ISD_CTPOP_MVT_i64_r(RetVT, Op0); |
331 | 0 | case MVT::v16i8: return fastEmit_ISD_CTPOP_MVT_v16i8_r(RetVT, Op0); |
332 | 0 | case MVT::v8i16: return fastEmit_ISD_CTPOP_MVT_v8i16_r(RetVT, Op0); |
333 | 0 | case MVT::v4i32: return fastEmit_ISD_CTPOP_MVT_v4i32_r(RetVT, Op0); |
334 | 0 | case MVT::v2i64: return fastEmit_ISD_CTPOP_MVT_v2i64_r(RetVT, Op0); |
335 | 0 | default: return 0; |
336 | 0 | } |
337 | 0 | } |
338 | | |
339 | | // FastEmit functions for ISD::CTTZ. |
340 | | |
341 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
342 | 0 | if (RetVT.SimpleTy != MVT::i32) |
343 | 0 | return 0; |
344 | 0 | if ((Subtarget->isISA3_0())) { |
345 | 0 | return fastEmitInst_r(PPC::CNTTZW, &PPC::GPRCRegClass, Op0); |
346 | 0 | } |
347 | 0 | return 0; |
348 | 0 | } |
349 | | |
350 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_i64_r(MVT RetVT, unsigned Op0) { |
351 | 0 | if (RetVT.SimpleTy != MVT::i64) |
352 | 0 | return 0; |
353 | 0 | if ((Subtarget->isISA3_0())) { |
354 | 0 | return fastEmitInst_r(PPC::CNTTZD, &PPC::G8RCRegClass, Op0); |
355 | 0 | } |
356 | 0 | return 0; |
357 | 0 | } |
358 | | |
359 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_v16i8_r(MVT RetVT, unsigned Op0) { |
360 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
361 | 0 | return 0; |
362 | 0 | if ((Subtarget->hasP9Altivec())) { |
363 | 0 | return fastEmitInst_r(PPC::VCTZB, &PPC::VRRCRegClass, Op0); |
364 | 0 | } |
365 | 0 | return 0; |
366 | 0 | } |
367 | | |
368 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_v8i16_r(MVT RetVT, unsigned Op0) { |
369 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
370 | 0 | return 0; |
371 | 0 | if ((Subtarget->hasP9Altivec())) { |
372 | 0 | return fastEmitInst_r(PPC::VCTZH, &PPC::VRRCRegClass, Op0); |
373 | 0 | } |
374 | 0 | return 0; |
375 | 0 | } |
376 | | |
377 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
378 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
379 | 0 | return 0; |
380 | 0 | if ((Subtarget->hasP9Altivec())) { |
381 | 0 | return fastEmitInst_r(PPC::VCTZW, &PPC::VRRCRegClass, Op0); |
382 | 0 | } |
383 | 0 | return 0; |
384 | 0 | } |
385 | | |
386 | 0 | unsigned fastEmit_ISD_CTTZ_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
387 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
388 | 0 | return 0; |
389 | 0 | if ((Subtarget->hasP9Altivec())) { |
390 | 0 | return fastEmitInst_r(PPC::VCTZD, &PPC::VRRCRegClass, Op0); |
391 | 0 | } |
392 | 0 | return 0; |
393 | 0 | } |
394 | | |
395 | 0 | unsigned fastEmit_ISD_CTTZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
396 | 0 | switch (VT.SimpleTy) { |
397 | 0 | case MVT::i32: return fastEmit_ISD_CTTZ_MVT_i32_r(RetVT, Op0); |
398 | 0 | case MVT::i64: return fastEmit_ISD_CTTZ_MVT_i64_r(RetVT, Op0); |
399 | 0 | case MVT::v16i8: return fastEmit_ISD_CTTZ_MVT_v16i8_r(RetVT, Op0); |
400 | 0 | case MVT::v8i16: return fastEmit_ISD_CTTZ_MVT_v8i16_r(RetVT, Op0); |
401 | 0 | case MVT::v4i32: return fastEmit_ISD_CTTZ_MVT_v4i32_r(RetVT, Op0); |
402 | 0 | case MVT::v2i64: return fastEmit_ISD_CTTZ_MVT_v2i64_r(RetVT, Op0); |
403 | 0 | default: return 0; |
404 | 0 | } |
405 | 0 | } |
406 | | |
407 | | // FastEmit functions for ISD::FABS. |
408 | | |
409 | 0 | unsigned fastEmit_ISD_FABS_MVT_f32_r(MVT RetVT, unsigned Op0) { |
410 | 0 | if (RetVT.SimpleTy != MVT::f32) |
411 | 0 | return 0; |
412 | 0 | if ((Subtarget->hasSPE())) { |
413 | 0 | return fastEmitInst_r(PPC::EFSABS, &PPC::GPRCRegClass, Op0); |
414 | 0 | } |
415 | 0 | if ((Subtarget->hasFPU())) { |
416 | 0 | return fastEmitInst_r(PPC::FABSS, &PPC::F4RCRegClass, Op0); |
417 | 0 | } |
418 | 0 | return 0; |
419 | 0 | } |
420 | | |
421 | 0 | unsigned fastEmit_ISD_FABS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
422 | 0 | if (RetVT.SimpleTy != MVT::f64) |
423 | 0 | return 0; |
424 | 0 | if ((Subtarget->hasVSX())) { |
425 | 0 | return fastEmitInst_r(PPC::XSABSDP, &PPC::VSFRCRegClass, Op0); |
426 | 0 | } |
427 | 0 | if ((Subtarget->hasSPE())) { |
428 | 0 | return fastEmitInst_r(PPC::EFDABS, &PPC::SPERCRegClass, Op0); |
429 | 0 | } |
430 | 0 | if ((Subtarget->hasFPU())) { |
431 | 0 | return fastEmitInst_r(PPC::FABSD, &PPC::F8RCRegClass, Op0); |
432 | 0 | } |
433 | 0 | return 0; |
434 | 0 | } |
435 | | |
436 | 0 | unsigned fastEmit_ISD_FABS_MVT_f128_r(MVT RetVT, unsigned Op0) { |
437 | 0 | if (RetVT.SimpleTy != MVT::f128) |
438 | 0 | return 0; |
439 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
440 | 0 | return fastEmitInst_r(PPC::XSABSQP, &PPC::VRRCRegClass, Op0); |
441 | 0 | } |
442 | 0 | return 0; |
443 | 0 | } |
444 | | |
445 | 0 | unsigned fastEmit_ISD_FABS_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
446 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
447 | 0 | return 0; |
448 | 0 | if ((Subtarget->hasVSX())) { |
449 | 0 | return fastEmitInst_r(PPC::XVABSSP, &PPC::VSRCRegClass, Op0); |
450 | 0 | } |
451 | 0 | return 0; |
452 | 0 | } |
453 | | |
454 | 0 | unsigned fastEmit_ISD_FABS_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
455 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
456 | 0 | return 0; |
457 | 0 | if ((Subtarget->hasVSX())) { |
458 | 0 | return fastEmitInst_r(PPC::XVABSDP, &PPC::VSRCRegClass, Op0); |
459 | 0 | } |
460 | 0 | return 0; |
461 | 0 | } |
462 | | |
463 | 0 | unsigned fastEmit_ISD_FABS_r(MVT VT, MVT RetVT, unsigned Op0) { |
464 | 0 | switch (VT.SimpleTy) { |
465 | 0 | case MVT::f32: return fastEmit_ISD_FABS_MVT_f32_r(RetVT, Op0); |
466 | 0 | case MVT::f64: return fastEmit_ISD_FABS_MVT_f64_r(RetVT, Op0); |
467 | 0 | case MVT::f128: return fastEmit_ISD_FABS_MVT_f128_r(RetVT, Op0); |
468 | 0 | case MVT::v4f32: return fastEmit_ISD_FABS_MVT_v4f32_r(RetVT, Op0); |
469 | 0 | case MVT::v2f64: return fastEmit_ISD_FABS_MVT_v2f64_r(RetVT, Op0); |
470 | 0 | default: return 0; |
471 | 0 | } |
472 | 0 | } |
473 | | |
474 | | // FastEmit functions for ISD::FCEIL. |
475 | | |
476 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { |
477 | 0 | if (RetVT.SimpleTy != MVT::f32) |
478 | 0 | return 0; |
479 | 0 | if ((Subtarget->hasFPU())) { |
480 | 0 | return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0); |
481 | 0 | } |
482 | 0 | return 0; |
483 | 0 | } |
484 | | |
485 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { |
486 | 0 | if (RetVT.SimpleTy != MVT::f64) |
487 | 0 | return 0; |
488 | 0 | if ((Subtarget->hasVSX())) { |
489 | 0 | return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0); |
490 | 0 | } |
491 | 0 | if ((Subtarget->hasFPU())) { |
492 | 0 | return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0); |
493 | 0 | } |
494 | 0 | return 0; |
495 | 0 | } |
496 | | |
497 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
498 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
499 | 0 | return 0; |
500 | 0 | if ((Subtarget->hasVSX())) { |
501 | 0 | return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0); |
502 | 0 | } |
503 | 0 | if ((Subtarget->hasAltivec())) { |
504 | 0 | return fastEmitInst_r(PPC::VRFIP, &PPC::VRRCRegClass, Op0); |
505 | 0 | } |
506 | 0 | return 0; |
507 | 0 | } |
508 | | |
509 | 0 | unsigned fastEmit_ISD_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
510 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
511 | 0 | return 0; |
512 | 0 | if ((Subtarget->hasVSX())) { |
513 | 0 | return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0); |
514 | 0 | } |
515 | 0 | return 0; |
516 | 0 | } |
517 | | |
518 | 0 | unsigned fastEmit_ISD_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { |
519 | 0 | switch (VT.SimpleTy) { |
520 | 0 | case MVT::f32: return fastEmit_ISD_FCEIL_MVT_f32_r(RetVT, Op0); |
521 | 0 | case MVT::f64: return fastEmit_ISD_FCEIL_MVT_f64_r(RetVT, Op0); |
522 | 0 | case MVT::v4f32: return fastEmit_ISD_FCEIL_MVT_v4f32_r(RetVT, Op0); |
523 | 0 | case MVT::v2f64: return fastEmit_ISD_FCEIL_MVT_v2f64_r(RetVT, Op0); |
524 | 0 | default: return 0; |
525 | 0 | } |
526 | 0 | } |
527 | | |
528 | | // FastEmit functions for ISD::FFLOOR. |
529 | | |
530 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
531 | 0 | if (RetVT.SimpleTy != MVT::f32) |
532 | 0 | return 0; |
533 | 0 | if ((Subtarget->hasFPU())) { |
534 | 0 | return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0); |
535 | 0 | } |
536 | 0 | return 0; |
537 | 0 | } |
538 | | |
539 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
540 | 0 | if (RetVT.SimpleTy != MVT::f64) |
541 | 0 | return 0; |
542 | 0 | if ((Subtarget->hasVSX())) { |
543 | 0 | return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0); |
544 | 0 | } |
545 | 0 | if ((Subtarget->hasFPU())) { |
546 | 0 | return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0); |
547 | 0 | } |
548 | 0 | return 0; |
549 | 0 | } |
550 | | |
551 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
552 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
553 | 0 | return 0; |
554 | 0 | if ((Subtarget->hasVSX())) { |
555 | 0 | return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0); |
556 | 0 | } |
557 | 0 | if ((Subtarget->hasAltivec())) { |
558 | 0 | return fastEmitInst_r(PPC::VRFIM, &PPC::VRRCRegClass, Op0); |
559 | 0 | } |
560 | 0 | return 0; |
561 | 0 | } |
562 | | |
563 | 0 | unsigned fastEmit_ISD_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
564 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
565 | 0 | return 0; |
566 | 0 | if ((Subtarget->hasVSX())) { |
567 | 0 | return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0); |
568 | 0 | } |
569 | 0 | return 0; |
570 | 0 | } |
571 | | |
572 | 0 | unsigned fastEmit_ISD_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
573 | 0 | switch (VT.SimpleTy) { |
574 | 0 | case MVT::f32: return fastEmit_ISD_FFLOOR_MVT_f32_r(RetVT, Op0); |
575 | 0 | case MVT::f64: return fastEmit_ISD_FFLOOR_MVT_f64_r(RetVT, Op0); |
576 | 0 | case MVT::v4f32: return fastEmit_ISD_FFLOOR_MVT_v4f32_r(RetVT, Op0); |
577 | 0 | case MVT::v2f64: return fastEmit_ISD_FFLOOR_MVT_v2f64_r(RetVT, Op0); |
578 | 0 | default: return 0; |
579 | 0 | } |
580 | 0 | } |
581 | | |
582 | | // FastEmit functions for ISD::FNEARBYINT. |
583 | | |
584 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
585 | 0 | if (RetVT.SimpleTy != MVT::f64) |
586 | 0 | return 0; |
587 | 0 | if ((Subtarget->hasVSX())) { |
588 | 0 | return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); |
589 | 0 | } |
590 | 0 | return 0; |
591 | 0 | } |
592 | | |
593 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
594 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
595 | 0 | return 0; |
596 | 0 | if ((Subtarget->hasVSX())) { |
597 | 0 | return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); |
598 | 0 | } |
599 | 0 | if ((Subtarget->hasAltivec())) { |
600 | 0 | return fastEmitInst_r(PPC::VRFIN, &PPC::VRRCRegClass, Op0); |
601 | 0 | } |
602 | 0 | return 0; |
603 | 0 | } |
604 | | |
605 | 0 | unsigned fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
606 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
607 | 0 | return 0; |
608 | 0 | if ((Subtarget->hasVSX())) { |
609 | 0 | return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); |
610 | 0 | } |
611 | 0 | return 0; |
612 | 0 | } |
613 | | |
614 | 0 | unsigned fastEmit_ISD_FNEARBYINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
615 | 0 | switch (VT.SimpleTy) { |
616 | 0 | case MVT::f64: return fastEmit_ISD_FNEARBYINT_MVT_f64_r(RetVT, Op0); |
617 | 0 | case MVT::v4f32: return fastEmit_ISD_FNEARBYINT_MVT_v4f32_r(RetVT, Op0); |
618 | 0 | case MVT::v2f64: return fastEmit_ISD_FNEARBYINT_MVT_v2f64_r(RetVT, Op0); |
619 | 0 | default: return 0; |
620 | 0 | } |
621 | 0 | } |
622 | | |
623 | | // FastEmit functions for ISD::FNEG. |
624 | | |
625 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f32_r(MVT RetVT, unsigned Op0) { |
626 | 0 | if (RetVT.SimpleTy != MVT::f32) |
627 | 0 | return 0; |
628 | 0 | if ((Subtarget->hasSPE())) { |
629 | 0 | return fastEmitInst_r(PPC::EFSNEG, &PPC::GPRCRegClass, Op0); |
630 | 0 | } |
631 | 0 | if ((Subtarget->hasFPU())) { |
632 | 0 | return fastEmitInst_r(PPC::FNEGS, &PPC::F4RCRegClass, Op0); |
633 | 0 | } |
634 | 0 | return 0; |
635 | 0 | } |
636 | | |
637 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f64_r(MVT RetVT, unsigned Op0) { |
638 | 0 | if (RetVT.SimpleTy != MVT::f64) |
639 | 0 | return 0; |
640 | 0 | if ((Subtarget->hasVSX())) { |
641 | 0 | return fastEmitInst_r(PPC::XSNEGDP, &PPC::VSFRCRegClass, Op0); |
642 | 0 | } |
643 | 0 | if ((Subtarget->hasSPE())) { |
644 | 0 | return fastEmitInst_r(PPC::EFDNEG, &PPC::SPERCRegClass, Op0); |
645 | 0 | } |
646 | 0 | if ((Subtarget->hasFPU())) { |
647 | 0 | return fastEmitInst_r(PPC::FNEGD, &PPC::F8RCRegClass, Op0); |
648 | 0 | } |
649 | 0 | return 0; |
650 | 0 | } |
651 | | |
652 | 0 | unsigned fastEmit_ISD_FNEG_MVT_f128_r(MVT RetVT, unsigned Op0) { |
653 | 0 | if (RetVT.SimpleTy != MVT::f128) |
654 | 0 | return 0; |
655 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
656 | 0 | return fastEmitInst_r(PPC::XSNEGQP, &PPC::VRRCRegClass, Op0); |
657 | 0 | } |
658 | 0 | return 0; |
659 | 0 | } |
660 | | |
661 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
662 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
663 | 0 | return 0; |
664 | 0 | if ((Subtarget->hasVSX())) { |
665 | 0 | return fastEmitInst_r(PPC::XVNEGSP, &PPC::VSRCRegClass, Op0); |
666 | 0 | } |
667 | 0 | return 0; |
668 | 0 | } |
669 | | |
670 | 0 | unsigned fastEmit_ISD_FNEG_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
671 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
672 | 0 | return 0; |
673 | 0 | if ((Subtarget->hasVSX())) { |
674 | 0 | return fastEmitInst_r(PPC::XVNEGDP, &PPC::VSRCRegClass, Op0); |
675 | 0 | } |
676 | 0 | return 0; |
677 | 0 | } |
678 | | |
679 | 0 | unsigned fastEmit_ISD_FNEG_r(MVT VT, MVT RetVT, unsigned Op0) { |
680 | 0 | switch (VT.SimpleTy) { |
681 | 0 | case MVT::f32: return fastEmit_ISD_FNEG_MVT_f32_r(RetVT, Op0); |
682 | 0 | case MVT::f64: return fastEmit_ISD_FNEG_MVT_f64_r(RetVT, Op0); |
683 | 0 | case MVT::f128: return fastEmit_ISD_FNEG_MVT_f128_r(RetVT, Op0); |
684 | 0 | case MVT::v4f32: return fastEmit_ISD_FNEG_MVT_v4f32_r(RetVT, Op0); |
685 | 0 | case MVT::v2f64: return fastEmit_ISD_FNEG_MVT_v2f64_r(RetVT, Op0); |
686 | 0 | default: return 0; |
687 | 0 | } |
688 | 0 | } |
689 | | |
690 | | // FastEmit functions for ISD::FP_EXTEND. |
691 | | |
692 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
693 | 0 | if (RetVT.SimpleTy != MVT::f64) |
694 | 0 | return 0; |
695 | 0 | if ((Subtarget->hasSPE())) { |
696 | 0 | return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0); |
697 | 0 | } |
698 | 0 | return 0; |
699 | 0 | } |
700 | | |
701 | 0 | unsigned fastEmit_ISD_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
702 | 0 | if (RetVT.SimpleTy != MVT::f128) |
703 | 0 | return 0; |
704 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
705 | 0 | return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0); |
706 | 0 | } |
707 | 0 | return 0; |
708 | 0 | } |
709 | | |
710 | 0 | unsigned fastEmit_ISD_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
711 | 0 | switch (VT.SimpleTy) { |
712 | 0 | case MVT::f32: return fastEmit_ISD_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
713 | 0 | case MVT::f64: return fastEmit_ISD_FP_EXTEND_MVT_f64_r(RetVT, Op0); |
714 | 0 | default: return 0; |
715 | 0 | } |
716 | 0 | } |
717 | | |
718 | | // FastEmit functions for ISD::FP_ROUND. |
719 | | |
720 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
721 | 0 | if (RetVT.SimpleTy != MVT::f32) |
722 | 0 | return 0; |
723 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
724 | 0 | return fastEmitInst_r(PPC::XSRSP, &PPC::VSSRCRegClass, Op0); |
725 | 0 | } |
726 | 0 | if ((Subtarget->hasSPE())) { |
727 | 0 | return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0); |
728 | 0 | } |
729 | 0 | if ((Subtarget->hasFPU())) { |
730 | 0 | return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0); |
731 | 0 | } |
732 | 0 | return 0; |
733 | 0 | } |
734 | | |
735 | 0 | unsigned fastEmit_ISD_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) { |
736 | 0 | if (RetVT.SimpleTy != MVT::f64) |
737 | 0 | return 0; |
738 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
739 | 0 | return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0); |
740 | 0 | } |
741 | 0 | return 0; |
742 | 0 | } |
743 | | |
744 | 0 | unsigned fastEmit_ISD_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
745 | 0 | switch (VT.SimpleTy) { |
746 | 0 | case MVT::f64: return fastEmit_ISD_FP_ROUND_MVT_f64_r(RetVT, Op0); |
747 | 0 | case MVT::f128: return fastEmit_ISD_FP_ROUND_MVT_f128_r(RetVT, Op0); |
748 | 0 | default: return 0; |
749 | 0 | } |
750 | 0 | } |
751 | | |
752 | | // FastEmit functions for ISD::FP_TO_SINT. |
753 | | |
754 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
755 | 0 | if (RetVT.SimpleTy != MVT::i32) |
756 | 0 | return 0; |
757 | 0 | if ((Subtarget->hasSPE())) { |
758 | 0 | return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0); |
759 | 0 | } |
760 | 0 | return 0; |
761 | 0 | } |
762 | | |
763 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
764 | 0 | if (RetVT.SimpleTy != MVT::i32) |
765 | 0 | return 0; |
766 | 0 | if ((Subtarget->hasSPE())) { |
767 | 0 | return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0); |
768 | 0 | } |
769 | 0 | return 0; |
770 | 0 | } |
771 | | |
772 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
773 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
774 | 0 | return 0; |
775 | 0 | if ((Subtarget->hasVSX())) { |
776 | 0 | return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0); |
777 | 0 | } |
778 | 0 | if ((Subtarget->hasAltivec())) { |
779 | 0 | return fastEmitInst_r(PPC::VCTSXS_0, &PPC::VRRCRegClass, Op0); |
780 | 0 | } |
781 | 0 | return 0; |
782 | 0 | } |
783 | | |
784 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
785 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
786 | 0 | return 0; |
787 | 0 | if ((Subtarget->hasVSX())) { |
788 | 0 | return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0); |
789 | 0 | } |
790 | 0 | return 0; |
791 | 0 | } |
792 | | |
793 | 0 | unsigned fastEmit_ISD_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
794 | 0 | switch (VT.SimpleTy) { |
795 | 0 | case MVT::f32: return fastEmit_ISD_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
796 | 0 | case MVT::f64: return fastEmit_ISD_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
797 | 0 | case MVT::v4f32: return fastEmit_ISD_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); |
798 | 0 | case MVT::v2f64: return fastEmit_ISD_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); |
799 | 0 | default: return 0; |
800 | 0 | } |
801 | 0 | } |
802 | | |
803 | | // FastEmit functions for ISD::FP_TO_UINT. |
804 | | |
805 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
806 | 0 | if (RetVT.SimpleTy != MVT::i32) |
807 | 0 | return 0; |
808 | 0 | if ((Subtarget->hasSPE())) { |
809 | 0 | return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0); |
810 | 0 | } |
811 | 0 | return 0; |
812 | 0 | } |
813 | | |
814 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
815 | 0 | if (RetVT.SimpleTy != MVT::i32) |
816 | 0 | return 0; |
817 | 0 | if ((Subtarget->hasSPE())) { |
818 | 0 | return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0); |
819 | 0 | } |
820 | 0 | return 0; |
821 | 0 | } |
822 | | |
823 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
824 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
825 | 0 | return 0; |
826 | 0 | if ((Subtarget->hasVSX())) { |
827 | 0 | return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0); |
828 | 0 | } |
829 | 0 | if ((Subtarget->hasAltivec())) { |
830 | 0 | return fastEmitInst_r(PPC::VCTUXS_0, &PPC::VRRCRegClass, Op0); |
831 | 0 | } |
832 | 0 | return 0; |
833 | 0 | } |
834 | | |
835 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
836 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
837 | 0 | return 0; |
838 | 0 | if ((Subtarget->hasVSX())) { |
839 | 0 | return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0); |
840 | 0 | } |
841 | 0 | return 0; |
842 | 0 | } |
843 | | |
844 | 0 | unsigned fastEmit_ISD_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
845 | 0 | switch (VT.SimpleTy) { |
846 | 0 | case MVT::f32: return fastEmit_ISD_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
847 | 0 | case MVT::f64: return fastEmit_ISD_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
848 | 0 | case MVT::v4f32: return fastEmit_ISD_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); |
849 | 0 | case MVT::v2f64: return fastEmit_ISD_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); |
850 | 0 | default: return 0; |
851 | 0 | } |
852 | 0 | } |
853 | | |
854 | | // FastEmit functions for ISD::FRINT. |
855 | | |
856 | 0 | unsigned fastEmit_ISD_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
857 | 0 | if (RetVT.SimpleTy != MVT::f64) |
858 | 0 | return 0; |
859 | 0 | if ((Subtarget->hasVSX())) { |
860 | 0 | return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); |
861 | 0 | } |
862 | 0 | return 0; |
863 | 0 | } |
864 | | |
865 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
866 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
867 | 0 | return 0; |
868 | 0 | if ((Subtarget->hasVSX())) { |
869 | 0 | return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); |
870 | 0 | } |
871 | 0 | return 0; |
872 | 0 | } |
873 | | |
874 | 0 | unsigned fastEmit_ISD_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
875 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
876 | 0 | return 0; |
877 | 0 | if ((Subtarget->hasVSX())) { |
878 | 0 | return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); |
879 | 0 | } |
880 | 0 | return 0; |
881 | 0 | } |
882 | | |
883 | 0 | unsigned fastEmit_ISD_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
884 | 0 | switch (VT.SimpleTy) { |
885 | 0 | case MVT::f64: return fastEmit_ISD_FRINT_MVT_f64_r(RetVT, Op0); |
886 | 0 | case MVT::v4f32: return fastEmit_ISD_FRINT_MVT_v4f32_r(RetVT, Op0); |
887 | 0 | case MVT::v2f64: return fastEmit_ISD_FRINT_MVT_v2f64_r(RetVT, Op0); |
888 | 0 | default: return 0; |
889 | 0 | } |
890 | 0 | } |
891 | | |
892 | | // FastEmit functions for ISD::FROUND. |
893 | | |
894 | 0 | unsigned fastEmit_ISD_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
895 | 0 | if (RetVT.SimpleTy != MVT::f32) |
896 | 0 | return 0; |
897 | 0 | if ((Subtarget->hasFPU())) { |
898 | 0 | return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0); |
899 | 0 | } |
900 | 0 | return 0; |
901 | 0 | } |
902 | | |
903 | 0 | unsigned fastEmit_ISD_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
904 | 0 | if (RetVT.SimpleTy != MVT::f64) |
905 | 0 | return 0; |
906 | 0 | if ((Subtarget->hasVSX())) { |
907 | 0 | return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0); |
908 | 0 | } |
909 | 0 | if ((Subtarget->hasFPU())) { |
910 | 0 | return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0); |
911 | 0 | } |
912 | 0 | return 0; |
913 | 0 | } |
914 | | |
915 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
916 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
917 | 0 | return 0; |
918 | 0 | if ((Subtarget->hasVSX())) { |
919 | 0 | return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0); |
920 | 0 | } |
921 | 0 | return 0; |
922 | 0 | } |
923 | | |
924 | 0 | unsigned fastEmit_ISD_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
925 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
926 | 0 | return 0; |
927 | 0 | if ((Subtarget->hasVSX())) { |
928 | 0 | return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0); |
929 | 0 | } |
930 | 0 | return 0; |
931 | 0 | } |
932 | | |
933 | 0 | unsigned fastEmit_ISD_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
934 | 0 | switch (VT.SimpleTy) { |
935 | 0 | case MVT::f32: return fastEmit_ISD_FROUND_MVT_f32_r(RetVT, Op0); |
936 | 0 | case MVT::f64: return fastEmit_ISD_FROUND_MVT_f64_r(RetVT, Op0); |
937 | 0 | case MVT::v4f32: return fastEmit_ISD_FROUND_MVT_v4f32_r(RetVT, Op0); |
938 | 0 | case MVT::v2f64: return fastEmit_ISD_FROUND_MVT_v2f64_r(RetVT, Op0); |
939 | 0 | default: return 0; |
940 | 0 | } |
941 | 0 | } |
942 | | |
943 | | // FastEmit functions for ISD::FSQRT. |
944 | | |
945 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
946 | 0 | if (RetVT.SimpleTy != MVT::f32) |
947 | 0 | return 0; |
948 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
949 | 0 | return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0); |
950 | 0 | } |
951 | 0 | if ((Subtarget->hasFPU())) { |
952 | 0 | return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0); |
953 | 0 | } |
954 | 0 | return 0; |
955 | 0 | } |
956 | | |
957 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
958 | 0 | if (RetVT.SimpleTy != MVT::f64) |
959 | 0 | return 0; |
960 | 0 | if ((Subtarget->hasVSX())) { |
961 | 0 | return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); |
962 | 0 | } |
963 | 0 | if ((Subtarget->hasFPU())) { |
964 | 0 | return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); |
965 | 0 | } |
966 | 0 | return 0; |
967 | 0 | } |
968 | | |
969 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) { |
970 | 0 | if (RetVT.SimpleTy != MVT::f128) |
971 | 0 | return 0; |
972 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
973 | 0 | return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0); |
974 | 0 | } |
975 | 0 | return 0; |
976 | 0 | } |
977 | | |
978 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
979 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
980 | 0 | return 0; |
981 | 0 | if ((Subtarget->hasVSX())) { |
982 | 0 | return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); |
983 | 0 | } |
984 | 0 | return 0; |
985 | 0 | } |
986 | | |
987 | 0 | unsigned fastEmit_ISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
988 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
989 | 0 | return 0; |
990 | 0 | if ((Subtarget->hasVSX())) { |
991 | 0 | return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); |
992 | 0 | } |
993 | 0 | return 0; |
994 | 0 | } |
995 | | |
996 | 0 | unsigned fastEmit_ISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
997 | 0 | switch (VT.SimpleTy) { |
998 | 0 | case MVT::f32: return fastEmit_ISD_FSQRT_MVT_f32_r(RetVT, Op0); |
999 | 0 | case MVT::f64: return fastEmit_ISD_FSQRT_MVT_f64_r(RetVT, Op0); |
1000 | 0 | case MVT::f128: return fastEmit_ISD_FSQRT_MVT_f128_r(RetVT, Op0); |
1001 | 0 | case MVT::v4f32: return fastEmit_ISD_FSQRT_MVT_v4f32_r(RetVT, Op0); |
1002 | 0 | case MVT::v2f64: return fastEmit_ISD_FSQRT_MVT_v2f64_r(RetVT, Op0); |
1003 | 0 | default: return 0; |
1004 | 0 | } |
1005 | 0 | } |
1006 | | |
1007 | | // FastEmit functions for ISD::FTRUNC. |
1008 | | |
1009 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1010 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1011 | 0 | return 0; |
1012 | 0 | if ((Subtarget->hasFPU())) { |
1013 | 0 | return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0); |
1014 | 0 | } |
1015 | 0 | return 0; |
1016 | 0 | } |
1017 | | |
1018 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1019 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1020 | 0 | return 0; |
1021 | 0 | if ((Subtarget->hasVSX())) { |
1022 | 0 | return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0); |
1023 | 0 | } |
1024 | 0 | if ((Subtarget->hasFPU())) { |
1025 | 0 | return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0); |
1026 | 0 | } |
1027 | 0 | return 0; |
1028 | 0 | } |
1029 | | |
1030 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1031 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1032 | 0 | return 0; |
1033 | 0 | if ((Subtarget->hasVSX())) { |
1034 | 0 | return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0); |
1035 | 0 | } |
1036 | 0 | if ((Subtarget->hasAltivec())) { |
1037 | 0 | return fastEmitInst_r(PPC::VRFIZ, &PPC::VRRCRegClass, Op0); |
1038 | 0 | } |
1039 | 0 | return 0; |
1040 | 0 | } |
1041 | | |
1042 | 0 | unsigned fastEmit_ISD_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1043 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1044 | 0 | return 0; |
1045 | 0 | if ((Subtarget->hasVSX())) { |
1046 | 0 | return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0); |
1047 | 0 | } |
1048 | 0 | return 0; |
1049 | 0 | } |
1050 | | |
1051 | 0 | unsigned fastEmit_ISD_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
1052 | 0 | switch (VT.SimpleTy) { |
1053 | 0 | case MVT::f32: return fastEmit_ISD_FTRUNC_MVT_f32_r(RetVT, Op0); |
1054 | 0 | case MVT::f64: return fastEmit_ISD_FTRUNC_MVT_f64_r(RetVT, Op0); |
1055 | 0 | case MVT::v4f32: return fastEmit_ISD_FTRUNC_MVT_v4f32_r(RetVT, Op0); |
1056 | 0 | case MVT::v2f64: return fastEmit_ISD_FTRUNC_MVT_v2f64_r(RetVT, Op0); |
1057 | 0 | default: return 0; |
1058 | 0 | } |
1059 | 0 | } |
1060 | | |
1061 | | // FastEmit functions for ISD::SCALAR_TO_VECTOR. |
1062 | | |
1063 | 0 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1064 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1065 | 0 | return 0; |
1066 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
1067 | 0 | return fastEmitInst_r(PPC::MTVSRWS, &PPC::VSRCRegClass, Op0); |
1068 | 0 | } |
1069 | 0 | return 0; |
1070 | 0 | } |
1071 | | |
1072 | 0 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1073 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1074 | 0 | return 0; |
1075 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) { |
1076 | 0 | return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); |
1077 | 0 | } |
1078 | 0 | return 0; |
1079 | 0 | } |
1080 | | |
1081 | 0 | unsigned fastEmit_ISD_SCALAR_TO_VECTOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
1082 | 0 | switch (VT.SimpleTy) { |
1083 | 0 | case MVT::i32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_i32_r(RetVT, Op0); |
1084 | 0 | case MVT::f32: return fastEmit_ISD_SCALAR_TO_VECTOR_MVT_f32_r(RetVT, Op0); |
1085 | 0 | default: return 0; |
1086 | 0 | } |
1087 | 0 | } |
1088 | | |
1089 | | // FastEmit functions for ISD::SIGN_EXTEND. |
1090 | | |
1091 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { |
1092 | 0 | if ((Subtarget->isISA3_1())) { |
1093 | 0 | return fastEmitInst_r(PPC::SETNBC, &PPC::GPRCRegClass, Op0); |
1094 | 0 | } |
1095 | 0 | return 0; |
1096 | 0 | } |
1097 | | |
1098 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { |
1099 | 0 | if ((Subtarget->isISA3_1())) { |
1100 | 0 | return fastEmitInst_r(PPC::SETNBC8, &PPC::G8RCRegClass, Op0); |
1101 | 0 | } |
1102 | 0 | return 0; |
1103 | 0 | } |
1104 | | |
1105 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { |
1106 | 0 | switch (RetVT.SimpleTy) { |
1107 | 0 | case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i32_r(Op0); |
1108 | 0 | case MVT::i64: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_MVT_i64_r(Op0); |
1109 | 0 | default: return 0; |
1110 | 0 | } |
1111 | 0 | } |
1112 | | |
1113 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1114 | 0 | if (RetVT.SimpleTy != MVT::i64) |
1115 | 0 | return 0; |
1116 | 0 | return fastEmitInst_r(PPC::EXTSW_32_64, &PPC::G8RCRegClass, Op0); |
1117 | 0 | } |
1118 | | |
1119 | 0 | unsigned fastEmit_ISD_SIGN_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
1120 | 0 | switch (VT.SimpleTy) { |
1121 | 0 | case MVT::i1: return fastEmit_ISD_SIGN_EXTEND_MVT_i1_r(RetVT, Op0); |
1122 | 0 | case MVT::i32: return fastEmit_ISD_SIGN_EXTEND_MVT_i32_r(RetVT, Op0); |
1123 | 0 | default: return 0; |
1124 | 0 | } |
1125 | 0 | } |
1126 | | |
1127 | | // FastEmit functions for ISD::SINT_TO_FP. |
1128 | | |
1129 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
1130 | 0 | if ((Subtarget->hasSPE())) { |
1131 | 0 | return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0); |
1132 | 0 | } |
1133 | 0 | return 0; |
1134 | 0 | } |
1135 | | |
1136 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
1137 | 0 | if ((Subtarget->hasSPE())) { |
1138 | 0 | return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0); |
1139 | 0 | } |
1140 | 0 | return 0; |
1141 | 0 | } |
1142 | | |
1143 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1144 | 0 | switch (RetVT.SimpleTy) { |
1145 | 0 | case MVT::f32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
1146 | 0 | case MVT::f64: return fastEmit_ISD_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
1147 | 0 | default: return 0; |
1148 | 0 | } |
1149 | 0 | } |
1150 | | |
1151 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1152 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1153 | 0 | return 0; |
1154 | 0 | if ((Subtarget->hasVSX())) { |
1155 | 0 | return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0); |
1156 | 0 | } |
1157 | 0 | if ((Subtarget->hasAltivec())) { |
1158 | 0 | return fastEmitInst_r(PPC::VCFSX_0, &PPC::VRRCRegClass, Op0); |
1159 | 0 | } |
1160 | 0 | return 0; |
1161 | 0 | } |
1162 | | |
1163 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
1164 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1165 | 0 | return 0; |
1166 | 0 | if ((Subtarget->hasVSX())) { |
1167 | 0 | return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0); |
1168 | 0 | } |
1169 | 0 | return 0; |
1170 | 0 | } |
1171 | | |
1172 | 0 | unsigned fastEmit_ISD_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
1173 | 0 | switch (VT.SimpleTy) { |
1174 | 0 | case MVT::i32: return fastEmit_ISD_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
1175 | 0 | case MVT::v4i32: return fastEmit_ISD_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
1176 | 0 | case MVT::v2i64: return fastEmit_ISD_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
1177 | 0 | default: return 0; |
1178 | 0 | } |
1179 | 0 | } |
1180 | | |
1181 | | // FastEmit functions for ISD::STRICT_FCEIL. |
1182 | | |
1183 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1184 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1185 | 0 | return 0; |
1186 | 0 | if ((Subtarget->hasFPU())) { |
1187 | 0 | return fastEmitInst_r(PPC::FRIPS, &PPC::F4RCRegClass, Op0); |
1188 | 0 | } |
1189 | 0 | return 0; |
1190 | 0 | } |
1191 | | |
1192 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1193 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1194 | 0 | return 0; |
1195 | 0 | if ((Subtarget->hasVSX())) { |
1196 | 0 | return fastEmitInst_r(PPC::XSRDPIP, &PPC::VSFRCRegClass, Op0); |
1197 | 0 | } |
1198 | 0 | if ((Subtarget->hasFPU())) { |
1199 | 0 | return fastEmitInst_r(PPC::FRIPD, &PPC::F8RCRegClass, Op0); |
1200 | 0 | } |
1201 | 0 | return 0; |
1202 | 0 | } |
1203 | | |
1204 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1205 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1206 | 0 | return 0; |
1207 | 0 | if ((Subtarget->hasVSX())) { |
1208 | 0 | return fastEmitInst_r(PPC::XVRSPIP, &PPC::VSRCRegClass, Op0); |
1209 | 0 | } |
1210 | 0 | return 0; |
1211 | 0 | } |
1212 | | |
1213 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1214 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1215 | 0 | return 0; |
1216 | 0 | if ((Subtarget->hasVSX())) { |
1217 | 0 | return fastEmitInst_r(PPC::XVRDPIP, &PPC::VSRCRegClass, Op0); |
1218 | 0 | } |
1219 | 0 | return 0; |
1220 | 0 | } |
1221 | | |
1222 | 0 | unsigned fastEmit_ISD_STRICT_FCEIL_r(MVT VT, MVT RetVT, unsigned Op0) { |
1223 | 0 | switch (VT.SimpleTy) { |
1224 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FCEIL_MVT_f32_r(RetVT, Op0); |
1225 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FCEIL_MVT_f64_r(RetVT, Op0); |
1226 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FCEIL_MVT_v4f32_r(RetVT, Op0); |
1227 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FCEIL_MVT_v2f64_r(RetVT, Op0); |
1228 | 0 | default: return 0; |
1229 | 0 | } |
1230 | 0 | } |
1231 | | |
1232 | | // FastEmit functions for ISD::STRICT_FFLOOR. |
1233 | | |
1234 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1235 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1236 | 0 | return 0; |
1237 | 0 | if ((Subtarget->hasFPU())) { |
1238 | 0 | return fastEmitInst_r(PPC::FRIMS, &PPC::F4RCRegClass, Op0); |
1239 | 0 | } |
1240 | 0 | return 0; |
1241 | 0 | } |
1242 | | |
1243 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1244 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1245 | 0 | return 0; |
1246 | 0 | if ((Subtarget->hasVSX())) { |
1247 | 0 | return fastEmitInst_r(PPC::XSRDPIM, &PPC::VSFRCRegClass, Op0); |
1248 | 0 | } |
1249 | 0 | if ((Subtarget->hasFPU())) { |
1250 | 0 | return fastEmitInst_r(PPC::FRIMD, &PPC::F8RCRegClass, Op0); |
1251 | 0 | } |
1252 | 0 | return 0; |
1253 | 0 | } |
1254 | | |
1255 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1256 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1257 | 0 | return 0; |
1258 | 0 | if ((Subtarget->hasVSX())) { |
1259 | 0 | return fastEmitInst_r(PPC::XVRSPIM, &PPC::VSRCRegClass, Op0); |
1260 | 0 | } |
1261 | 0 | return 0; |
1262 | 0 | } |
1263 | | |
1264 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1265 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1266 | 0 | return 0; |
1267 | 0 | if ((Subtarget->hasVSX())) { |
1268 | 0 | return fastEmitInst_r(PPC::XVRDPIM, &PPC::VSRCRegClass, Op0); |
1269 | 0 | } |
1270 | 0 | return 0; |
1271 | 0 | } |
1272 | | |
1273 | 0 | unsigned fastEmit_ISD_STRICT_FFLOOR_r(MVT VT, MVT RetVT, unsigned Op0) { |
1274 | 0 | switch (VT.SimpleTy) { |
1275 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_f32_r(RetVT, Op0); |
1276 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_f64_r(RetVT, Op0); |
1277 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FFLOOR_MVT_v4f32_r(RetVT, Op0); |
1278 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FFLOOR_MVT_v2f64_r(RetVT, Op0); |
1279 | 0 | default: return 0; |
1280 | 0 | } |
1281 | 0 | } |
1282 | | |
1283 | | // FastEmit functions for ISD::STRICT_FP_EXTEND. |
1284 | | |
1285 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1286 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1287 | 0 | return 0; |
1288 | 0 | if ((Subtarget->hasSPE())) { |
1289 | 0 | return fastEmitInst_r(PPC::EFDCFS, &PPC::SPERCRegClass, Op0); |
1290 | 0 | } |
1291 | 0 | return 0; |
1292 | 0 | } |
1293 | | |
1294 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1295 | 0 | if (RetVT.SimpleTy != MVT::f128) |
1296 | 0 | return 0; |
1297 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
1298 | 0 | return fastEmitInst_r(PPC::XSCVDPQP, &PPC::VRRCRegClass, Op0); |
1299 | 0 | } |
1300 | 0 | return 0; |
1301 | 0 | } |
1302 | | |
1303 | 0 | unsigned fastEmit_ISD_STRICT_FP_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
1304 | 0 | switch (VT.SimpleTy) { |
1305 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f32_r(RetVT, Op0); |
1306 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_EXTEND_MVT_f64_r(RetVT, Op0); |
1307 | 0 | default: return 0; |
1308 | 0 | } |
1309 | 0 | } |
1310 | | |
1311 | | // FastEmit functions for ISD::STRICT_FP_ROUND. |
1312 | | |
1313 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1314 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1315 | 0 | return 0; |
1316 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
1317 | 0 | return fastEmitInst_r(PPC::XSRSP, &PPC::VSSRCRegClass, Op0); |
1318 | 0 | } |
1319 | 0 | if ((Subtarget->hasSPE())) { |
1320 | 0 | return fastEmitInst_r(PPC::EFSCFD, &PPC::GPRCRegClass, Op0); |
1321 | 0 | } |
1322 | 0 | if ((Subtarget->hasFPU())) { |
1323 | 0 | return fastEmitInst_r(PPC::FRSP, &PPC::F4RCRegClass, Op0); |
1324 | 0 | } |
1325 | 0 | return 0; |
1326 | 0 | } |
1327 | | |
1328 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(MVT RetVT, unsigned Op0) { |
1329 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1330 | 0 | return 0; |
1331 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
1332 | 0 | return fastEmitInst_r(PPC::XSCVQPDP, &PPC::VFRCRegClass, Op0); |
1333 | 0 | } |
1334 | 0 | return 0; |
1335 | 0 | } |
1336 | | |
1337 | 0 | unsigned fastEmit_ISD_STRICT_FP_ROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
1338 | 0 | switch (VT.SimpleTy) { |
1339 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f64_r(RetVT, Op0); |
1340 | 0 | case MVT::f128: return fastEmit_ISD_STRICT_FP_ROUND_MVT_f128_r(RetVT, Op0); |
1341 | 0 | default: return 0; |
1342 | 0 | } |
1343 | 0 | } |
1344 | | |
1345 | | // FastEmit functions for ISD::STRICT_FP_TO_SINT. |
1346 | | |
1347 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1348 | 0 | if (RetVT.SimpleTy != MVT::i32) |
1349 | 0 | return 0; |
1350 | 0 | if ((Subtarget->hasSPE())) { |
1351 | 0 | return fastEmitInst_r(PPC::EFSCTSIZ, &PPC::GPRCRegClass, Op0); |
1352 | 0 | } |
1353 | 0 | return 0; |
1354 | 0 | } |
1355 | | |
1356 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1357 | 0 | if (RetVT.SimpleTy != MVT::i32) |
1358 | 0 | return 0; |
1359 | 0 | if ((Subtarget->hasSPE())) { |
1360 | 0 | return fastEmitInst_r(PPC::EFDCTSIZ, &PPC::GPRCRegClass, Op0); |
1361 | 0 | } |
1362 | 0 | return 0; |
1363 | 0 | } |
1364 | | |
1365 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1366 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1367 | 0 | return 0; |
1368 | 0 | if ((Subtarget->hasVSX())) { |
1369 | 0 | return fastEmitInst_r(PPC::XVCVSPSXWS, &PPC::VSRCRegClass, Op0); |
1370 | 0 | } |
1371 | 0 | return 0; |
1372 | 0 | } |
1373 | | |
1374 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1375 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1376 | 0 | return 0; |
1377 | 0 | if ((Subtarget->hasVSX())) { |
1378 | 0 | return fastEmitInst_r(PPC::XVCVDPSXDS, &PPC::VSRCRegClass, Op0); |
1379 | 0 | } |
1380 | 0 | return 0; |
1381 | 0 | } |
1382 | | |
1383 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_SINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
1384 | 0 | switch (VT.SimpleTy) { |
1385 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f32_r(RetVT, Op0); |
1386 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_f64_r(RetVT, Op0); |
1387 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v4f32_r(RetVT, Op0); |
1388 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_SINT_MVT_v2f64_r(RetVT, Op0); |
1389 | 0 | default: return 0; |
1390 | 0 | } |
1391 | 0 | } |
1392 | | |
1393 | | // FastEmit functions for ISD::STRICT_FP_TO_UINT. |
1394 | | |
1395 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1396 | 0 | if (RetVT.SimpleTy != MVT::i32) |
1397 | 0 | return 0; |
1398 | 0 | if ((Subtarget->hasSPE())) { |
1399 | 0 | return fastEmitInst_r(PPC::EFSCTUIZ, &PPC::GPRCRegClass, Op0); |
1400 | 0 | } |
1401 | 0 | return 0; |
1402 | 0 | } |
1403 | | |
1404 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1405 | 0 | if (RetVT.SimpleTy != MVT::i32) |
1406 | 0 | return 0; |
1407 | 0 | if ((Subtarget->hasSPE())) { |
1408 | 0 | return fastEmitInst_r(PPC::EFDCTUIZ, &PPC::GPRCRegClass, Op0); |
1409 | 0 | } |
1410 | 0 | return 0; |
1411 | 0 | } |
1412 | | |
1413 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1414 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
1415 | 0 | return 0; |
1416 | 0 | if ((Subtarget->hasVSX())) { |
1417 | 0 | return fastEmitInst_r(PPC::XVCVSPUXWS, &PPC::VSRCRegClass, Op0); |
1418 | 0 | } |
1419 | 0 | return 0; |
1420 | 0 | } |
1421 | | |
1422 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1423 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
1424 | 0 | return 0; |
1425 | 0 | if ((Subtarget->hasVSX())) { |
1426 | 0 | return fastEmitInst_r(PPC::XVCVDPUXDS, &PPC::VSRCRegClass, Op0); |
1427 | 0 | } |
1428 | 0 | return 0; |
1429 | 0 | } |
1430 | | |
1431 | 0 | unsigned fastEmit_ISD_STRICT_FP_TO_UINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
1432 | 0 | switch (VT.SimpleTy) { |
1433 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f32_r(RetVT, Op0); |
1434 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_f64_r(RetVT, Op0); |
1435 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v4f32_r(RetVT, Op0); |
1436 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FP_TO_UINT_MVT_v2f64_r(RetVT, Op0); |
1437 | 0 | default: return 0; |
1438 | 0 | } |
1439 | 0 | } |
1440 | | |
1441 | | // FastEmit functions for ISD::STRICT_FRINT. |
1442 | | |
1443 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1444 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1445 | 0 | return 0; |
1446 | 0 | if ((Subtarget->hasVSX())) { |
1447 | 0 | return fastEmitInst_r(PPC::XSRDPIC, &PPC::VSFRCRegClass, Op0); |
1448 | 0 | } |
1449 | 0 | return 0; |
1450 | 0 | } |
1451 | | |
1452 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1453 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1454 | 0 | return 0; |
1455 | 0 | if ((Subtarget->hasVSX())) { |
1456 | 0 | return fastEmitInst_r(PPC::XVRSPIC, &PPC::VSRCRegClass, Op0); |
1457 | 0 | } |
1458 | 0 | return 0; |
1459 | 0 | } |
1460 | | |
1461 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1462 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1463 | 0 | return 0; |
1464 | 0 | if ((Subtarget->hasVSX())) { |
1465 | 0 | return fastEmitInst_r(PPC::XVRDPIC, &PPC::VSRCRegClass, Op0); |
1466 | 0 | } |
1467 | 0 | return 0; |
1468 | 0 | } |
1469 | | |
1470 | 0 | unsigned fastEmit_ISD_STRICT_FRINT_r(MVT VT, MVT RetVT, unsigned Op0) { |
1471 | 0 | switch (VT.SimpleTy) { |
1472 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FRINT_MVT_f64_r(RetVT, Op0); |
1473 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FRINT_MVT_v4f32_r(RetVT, Op0); |
1474 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FRINT_MVT_v2f64_r(RetVT, Op0); |
1475 | 0 | default: return 0; |
1476 | 0 | } |
1477 | 0 | } |
1478 | | |
1479 | | // FastEmit functions for ISD::STRICT_FROUND. |
1480 | | |
1481 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1482 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1483 | 0 | return 0; |
1484 | 0 | if ((Subtarget->hasFPU())) { |
1485 | 0 | return fastEmitInst_r(PPC::FRINS, &PPC::F4RCRegClass, Op0); |
1486 | 0 | } |
1487 | 0 | return 0; |
1488 | 0 | } |
1489 | | |
1490 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1491 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1492 | 0 | return 0; |
1493 | 0 | if ((Subtarget->hasVSX())) { |
1494 | 0 | return fastEmitInst_r(PPC::XSRDPI, &PPC::VSFRCRegClass, Op0); |
1495 | 0 | } |
1496 | 0 | if ((Subtarget->hasFPU())) { |
1497 | 0 | return fastEmitInst_r(PPC::FRIND, &PPC::F8RCRegClass, Op0); |
1498 | 0 | } |
1499 | 0 | return 0; |
1500 | 0 | } |
1501 | | |
1502 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1503 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1504 | 0 | return 0; |
1505 | 0 | if ((Subtarget->hasVSX())) { |
1506 | 0 | return fastEmitInst_r(PPC::XVRSPI, &PPC::VSRCRegClass, Op0); |
1507 | 0 | } |
1508 | 0 | return 0; |
1509 | 0 | } |
1510 | | |
1511 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1512 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1513 | 0 | return 0; |
1514 | 0 | if ((Subtarget->hasVSX())) { |
1515 | 0 | return fastEmitInst_r(PPC::XVRDPI, &PPC::VSRCRegClass, Op0); |
1516 | 0 | } |
1517 | 0 | return 0; |
1518 | 0 | } |
1519 | | |
1520 | 0 | unsigned fastEmit_ISD_STRICT_FROUND_r(MVT VT, MVT RetVT, unsigned Op0) { |
1521 | 0 | switch (VT.SimpleTy) { |
1522 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FROUND_MVT_f32_r(RetVT, Op0); |
1523 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FROUND_MVT_f64_r(RetVT, Op0); |
1524 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FROUND_MVT_v4f32_r(RetVT, Op0); |
1525 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FROUND_MVT_v2f64_r(RetVT, Op0); |
1526 | 0 | default: return 0; |
1527 | 0 | } |
1528 | 0 | } |
1529 | | |
1530 | | // FastEmit functions for ISD::STRICT_FSQRT. |
1531 | | |
1532 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1533 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1534 | 0 | return 0; |
1535 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
1536 | 0 | return fastEmitInst_r(PPC::XSSQRTSP, &PPC::VSSRCRegClass, Op0); |
1537 | 0 | } |
1538 | 0 | if ((Subtarget->hasFPU())) { |
1539 | 0 | return fastEmitInst_r(PPC::FSQRTS, &PPC::F4RCRegClass, Op0); |
1540 | 0 | } |
1541 | 0 | return 0; |
1542 | 0 | } |
1543 | | |
1544 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1545 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1546 | 0 | return 0; |
1547 | 0 | if ((Subtarget->hasVSX())) { |
1548 | 0 | return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); |
1549 | 0 | } |
1550 | 0 | if ((Subtarget->hasFPU())) { |
1551 | 0 | return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); |
1552 | 0 | } |
1553 | 0 | return 0; |
1554 | 0 | } |
1555 | | |
1556 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(MVT RetVT, unsigned Op0) { |
1557 | 0 | if (RetVT.SimpleTy != MVT::f128) |
1558 | 0 | return 0; |
1559 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
1560 | 0 | return fastEmitInst_r(PPC::XSSQRTQP, &PPC::VRRCRegClass, Op0); |
1561 | 0 | } |
1562 | 0 | return 0; |
1563 | 0 | } |
1564 | | |
1565 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1566 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1567 | 0 | return 0; |
1568 | 0 | if ((Subtarget->hasVSX())) { |
1569 | 0 | return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); |
1570 | 0 | } |
1571 | 0 | return 0; |
1572 | 0 | } |
1573 | | |
1574 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1575 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1576 | 0 | return 0; |
1577 | 0 | if ((Subtarget->hasVSX())) { |
1578 | 0 | return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); |
1579 | 0 | } |
1580 | 0 | return 0; |
1581 | 0 | } |
1582 | | |
1583 | 0 | unsigned fastEmit_ISD_STRICT_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
1584 | 0 | switch (VT.SimpleTy) { |
1585 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FSQRT_MVT_f32_r(RetVT, Op0); |
1586 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FSQRT_MVT_f64_r(RetVT, Op0); |
1587 | 0 | case MVT::f128: return fastEmit_ISD_STRICT_FSQRT_MVT_f128_r(RetVT, Op0); |
1588 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FSQRT_MVT_v4f32_r(RetVT, Op0); |
1589 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FSQRT_MVT_v2f64_r(RetVT, Op0); |
1590 | 0 | default: return 0; |
1591 | 0 | } |
1592 | 0 | } |
1593 | | |
1594 | | // FastEmit functions for ISD::STRICT_FTRUNC. |
1595 | | |
1596 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1597 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1598 | 0 | return 0; |
1599 | 0 | if ((Subtarget->hasFPU())) { |
1600 | 0 | return fastEmitInst_r(PPC::FRIZS, &PPC::F4RCRegClass, Op0); |
1601 | 0 | } |
1602 | 0 | return 0; |
1603 | 0 | } |
1604 | | |
1605 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1606 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1607 | 0 | return 0; |
1608 | 0 | if ((Subtarget->hasVSX())) { |
1609 | 0 | return fastEmitInst_r(PPC::XSRDPIZ, &PPC::VSFRCRegClass, Op0); |
1610 | 0 | } |
1611 | 0 | if ((Subtarget->hasFPU())) { |
1612 | 0 | return fastEmitInst_r(PPC::FRIZD, &PPC::F8RCRegClass, Op0); |
1613 | 0 | } |
1614 | 0 | return 0; |
1615 | 0 | } |
1616 | | |
1617 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
1618 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1619 | 0 | return 0; |
1620 | 0 | if ((Subtarget->hasVSX())) { |
1621 | 0 | return fastEmitInst_r(PPC::XVRSPIZ, &PPC::VSRCRegClass, Op0); |
1622 | 0 | } |
1623 | 0 | return 0; |
1624 | 0 | } |
1625 | | |
1626 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
1627 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1628 | 0 | return 0; |
1629 | 0 | if ((Subtarget->hasVSX())) { |
1630 | 0 | return fastEmitInst_r(PPC::XVRDPIZ, &PPC::VSRCRegClass, Op0); |
1631 | 0 | } |
1632 | 0 | return 0; |
1633 | 0 | } |
1634 | | |
1635 | 0 | unsigned fastEmit_ISD_STRICT_FTRUNC_r(MVT VT, MVT RetVT, unsigned Op0) { |
1636 | 0 | switch (VT.SimpleTy) { |
1637 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_f32_r(RetVT, Op0); |
1638 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_f64_r(RetVT, Op0); |
1639 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FTRUNC_MVT_v4f32_r(RetVT, Op0); |
1640 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FTRUNC_MVT_v2f64_r(RetVT, Op0); |
1641 | 0 | default: return 0; |
1642 | 0 | } |
1643 | 0 | } |
1644 | | |
1645 | | // FastEmit functions for ISD::STRICT_SINT_TO_FP. |
1646 | | |
1647 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
1648 | 0 | if ((Subtarget->hasSPE())) { |
1649 | 0 | return fastEmitInst_r(PPC::EFSCFSI, &PPC::GPRCRegClass, Op0); |
1650 | 0 | } |
1651 | 0 | return 0; |
1652 | 0 | } |
1653 | | |
1654 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
1655 | 0 | if ((Subtarget->hasSPE())) { |
1656 | 0 | return fastEmitInst_r(PPC::EFDCFSI, &PPC::SPERCRegClass, Op0); |
1657 | 0 | } |
1658 | 0 | return 0; |
1659 | 0 | } |
1660 | | |
1661 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1662 | 0 | switch (RetVT.SimpleTy) { |
1663 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
1664 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
1665 | 0 | default: return 0; |
1666 | 0 | } |
1667 | 0 | } |
1668 | | |
1669 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1670 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1671 | 0 | return 0; |
1672 | 0 | if ((Subtarget->hasVSX())) { |
1673 | 0 | return fastEmitInst_r(PPC::XVCVSXWSP, &PPC::VSRCRegClass, Op0); |
1674 | 0 | } |
1675 | 0 | return 0; |
1676 | 0 | } |
1677 | | |
1678 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
1679 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1680 | 0 | return 0; |
1681 | 0 | if ((Subtarget->hasVSX())) { |
1682 | 0 | return fastEmitInst_r(PPC::XVCVSXDDP, &PPC::VSRCRegClass, Op0); |
1683 | 0 | } |
1684 | 0 | return 0; |
1685 | 0 | } |
1686 | | |
1687 | 0 | unsigned fastEmit_ISD_STRICT_SINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
1688 | 0 | switch (VT.SimpleTy) { |
1689 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_i32_r(RetVT, Op0); |
1690 | 0 | case MVT::v4i32: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
1691 | 0 | case MVT::v2i64: return fastEmit_ISD_STRICT_SINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
1692 | 0 | default: return 0; |
1693 | 0 | } |
1694 | 0 | } |
1695 | | |
1696 | | // FastEmit functions for ISD::STRICT_UINT_TO_FP. |
1697 | | |
1698 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
1699 | 0 | if ((Subtarget->hasSPE())) { |
1700 | 0 | return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0); |
1701 | 0 | } |
1702 | 0 | return 0; |
1703 | 0 | } |
1704 | | |
1705 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
1706 | 0 | if ((Subtarget->hasSPE())) { |
1707 | 0 | return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0); |
1708 | 0 | } |
1709 | 0 | return 0; |
1710 | 0 | } |
1711 | | |
1712 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1713 | 0 | switch (RetVT.SimpleTy) { |
1714 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
1715 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
1716 | 0 | default: return 0; |
1717 | 0 | } |
1718 | 0 | } |
1719 | | |
1720 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1721 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1722 | 0 | return 0; |
1723 | 0 | if ((Subtarget->hasVSX())) { |
1724 | 0 | return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0); |
1725 | 0 | } |
1726 | 0 | return 0; |
1727 | 0 | } |
1728 | | |
1729 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
1730 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1731 | 0 | return 0; |
1732 | 0 | if ((Subtarget->hasVSX())) { |
1733 | 0 | return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0); |
1734 | 0 | } |
1735 | 0 | return 0; |
1736 | 0 | } |
1737 | | |
1738 | 0 | unsigned fastEmit_ISD_STRICT_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
1739 | 0 | switch (VT.SimpleTy) { |
1740 | 0 | case MVT::i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_i32_r(RetVT, Op0); |
1741 | 0 | case MVT::v4i32: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
1742 | 0 | case MVT::v2i64: return fastEmit_ISD_STRICT_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
1743 | 0 | default: return 0; |
1744 | 0 | } |
1745 | 0 | } |
1746 | | |
1747 | | // FastEmit functions for ISD::TRUNCATE. |
1748 | | |
1749 | 0 | unsigned fastEmit_ISD_TRUNCATE_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1750 | 0 | if (RetVT.SimpleTy != MVT::i1) |
1751 | 0 | return 0; |
1752 | 0 | return fastEmitInst_r(PPC::ANDI_rec_1_GT_BIT, &PPC::CRBITRCRegClass, Op0); |
1753 | 0 | } |
1754 | | |
1755 | 0 | unsigned fastEmit_ISD_TRUNCATE_MVT_i64_r(MVT RetVT, unsigned Op0) { |
1756 | 0 | if (RetVT.SimpleTy != MVT::i1) |
1757 | 0 | return 0; |
1758 | 0 | return fastEmitInst_r(PPC::ANDI_rec_1_GT_BIT8, &PPC::CRBITRCRegClass, Op0); |
1759 | 0 | } |
1760 | | |
1761 | 0 | unsigned fastEmit_ISD_TRUNCATE_r(MVT VT, MVT RetVT, unsigned Op0) { |
1762 | 0 | switch (VT.SimpleTy) { |
1763 | 0 | case MVT::i32: return fastEmit_ISD_TRUNCATE_MVT_i32_r(RetVT, Op0); |
1764 | 0 | case MVT::i64: return fastEmit_ISD_TRUNCATE_MVT_i64_r(RetVT, Op0); |
1765 | 0 | default: return 0; |
1766 | 0 | } |
1767 | 0 | } |
1768 | | |
1769 | | // FastEmit functions for ISD::UINT_TO_FP. |
1770 | | |
1771 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(unsigned Op0) { |
1772 | 0 | if ((Subtarget->hasSPE())) { |
1773 | 0 | return fastEmitInst_r(PPC::EFSCFUI, &PPC::GPRCRegClass, Op0); |
1774 | 0 | } |
1775 | 0 | return 0; |
1776 | 0 | } |
1777 | | |
1778 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(unsigned Op0) { |
1779 | 0 | if ((Subtarget->hasSPE())) { |
1780 | 0 | return fastEmitInst_r(PPC::EFDCFUI, &PPC::SPERCRegClass, Op0); |
1781 | 0 | } |
1782 | 0 | return 0; |
1783 | 0 | } |
1784 | | |
1785 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
1786 | 0 | switch (RetVT.SimpleTy) { |
1787 | 0 | case MVT::f32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f32_r(Op0); |
1788 | 0 | case MVT::f64: return fastEmit_ISD_UINT_TO_FP_MVT_i32_MVT_f64_r(Op0); |
1789 | 0 | default: return 0; |
1790 | 0 | } |
1791 | 0 | } |
1792 | | |
1793 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(MVT RetVT, unsigned Op0) { |
1794 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
1795 | 0 | return 0; |
1796 | 0 | if ((Subtarget->hasVSX())) { |
1797 | 0 | return fastEmitInst_r(PPC::XVCVUXWSP, &PPC::VSRCRegClass, Op0); |
1798 | 0 | } |
1799 | 0 | if ((Subtarget->hasAltivec())) { |
1800 | 0 | return fastEmitInst_r(PPC::VCFUX_0, &PPC::VRRCRegClass, Op0); |
1801 | 0 | } |
1802 | 0 | return 0; |
1803 | 0 | } |
1804 | | |
1805 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(MVT RetVT, unsigned Op0) { |
1806 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
1807 | 0 | return 0; |
1808 | 0 | if ((Subtarget->hasVSX())) { |
1809 | 0 | return fastEmitInst_r(PPC::XVCVUXDDP, &PPC::VSRCRegClass, Op0); |
1810 | 0 | } |
1811 | 0 | return 0; |
1812 | 0 | } |
1813 | | |
1814 | 0 | unsigned fastEmit_ISD_UINT_TO_FP_r(MVT VT, MVT RetVT, unsigned Op0) { |
1815 | 0 | switch (VT.SimpleTy) { |
1816 | 0 | case MVT::i32: return fastEmit_ISD_UINT_TO_FP_MVT_i32_r(RetVT, Op0); |
1817 | 0 | case MVT::v4i32: return fastEmit_ISD_UINT_TO_FP_MVT_v4i32_r(RetVT, Op0); |
1818 | 0 | case MVT::v2i64: return fastEmit_ISD_UINT_TO_FP_MVT_v2i64_r(RetVT, Op0); |
1819 | 0 | default: return 0; |
1820 | 0 | } |
1821 | 0 | } |
1822 | | |
1823 | | // FastEmit functions for ISD::ZERO_EXTEND. |
1824 | | |
1825 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(unsigned Op0) { |
1826 | 0 | if ((Subtarget->isISA3_1())) { |
1827 | 0 | return fastEmitInst_r(PPC::SETBC, &PPC::GPRCRegClass, Op0); |
1828 | 0 | } |
1829 | 0 | return 0; |
1830 | 0 | } |
1831 | | |
1832 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(unsigned Op0) { |
1833 | 0 | if ((Subtarget->isISA3_1())) { |
1834 | 0 | return fastEmitInst_r(PPC::SETBC8, &PPC::G8RCRegClass, Op0); |
1835 | 0 | } |
1836 | 0 | return 0; |
1837 | 0 | } |
1838 | | |
1839 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(MVT RetVT, unsigned Op0) { |
1840 | 0 | switch (RetVT.SimpleTy) { |
1841 | 0 | case MVT::i32: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i32_r(Op0); |
1842 | 0 | case MVT::i64: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_MVT_i64_r(Op0); |
1843 | 0 | default: return 0; |
1844 | 0 | } |
1845 | 0 | } |
1846 | | |
1847 | 0 | unsigned fastEmit_ISD_ZERO_EXTEND_r(MVT VT, MVT RetVT, unsigned Op0) { |
1848 | 0 | switch (VT.SimpleTy) { |
1849 | 0 | case MVT::i1: return fastEmit_ISD_ZERO_EXTEND_MVT_i1_r(RetVT, Op0); |
1850 | 0 | default: return 0; |
1851 | 0 | } |
1852 | 0 | } |
1853 | | |
1854 | | // FastEmit functions for PPCISD::FCFID. |
1855 | | |
1856 | 0 | unsigned fastEmit_PPCISD_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1857 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1858 | 0 | return 0; |
1859 | 0 | if ((Subtarget->hasVSX())) { |
1860 | 0 | return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0); |
1861 | 0 | } |
1862 | 0 | return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0); |
1863 | 0 | } |
1864 | | |
1865 | 0 | unsigned fastEmit_PPCISD_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) { |
1866 | 0 | switch (VT.SimpleTy) { |
1867 | 0 | case MVT::f64: return fastEmit_PPCISD_FCFID_MVT_f64_r(RetVT, Op0); |
1868 | 0 | default: return 0; |
1869 | 0 | } |
1870 | 0 | } |
1871 | | |
1872 | | // FastEmit functions for PPCISD::FCFIDS. |
1873 | | |
1874 | 0 | unsigned fastEmit_PPCISD_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1875 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1876 | 0 | return 0; |
1877 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
1878 | 0 | return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0); |
1879 | 0 | } |
1880 | 0 | return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0); |
1881 | 0 | } |
1882 | | |
1883 | 0 | unsigned fastEmit_PPCISD_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) { |
1884 | 0 | switch (VT.SimpleTy) { |
1885 | 0 | case MVT::f64: return fastEmit_PPCISD_FCFIDS_MVT_f64_r(RetVT, Op0); |
1886 | 0 | default: return 0; |
1887 | 0 | } |
1888 | 0 | } |
1889 | | |
1890 | | // FastEmit functions for PPCISD::FCFIDU. |
1891 | | |
1892 | 0 | unsigned fastEmit_PPCISD_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1893 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1894 | 0 | return 0; |
1895 | 0 | if ((Subtarget->hasVSX())) { |
1896 | 0 | return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0); |
1897 | 0 | } |
1898 | 0 | return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0); |
1899 | 0 | } |
1900 | | |
1901 | 0 | unsigned fastEmit_PPCISD_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) { |
1902 | 0 | switch (VT.SimpleTy) { |
1903 | 0 | case MVT::f64: return fastEmit_PPCISD_FCFIDU_MVT_f64_r(RetVT, Op0); |
1904 | 0 | default: return 0; |
1905 | 0 | } |
1906 | 0 | } |
1907 | | |
1908 | | // FastEmit functions for PPCISD::FCFIDUS. |
1909 | | |
1910 | 0 | unsigned fastEmit_PPCISD_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1911 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1912 | 0 | return 0; |
1913 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
1914 | 0 | return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0); |
1915 | 0 | } |
1916 | 0 | return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0); |
1917 | 0 | } |
1918 | | |
1919 | 0 | unsigned fastEmit_PPCISD_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) { |
1920 | 0 | switch (VT.SimpleTy) { |
1921 | 0 | case MVT::f64: return fastEmit_PPCISD_FCFIDUS_MVT_f64_r(RetVT, Op0); |
1922 | 0 | default: return 0; |
1923 | 0 | } |
1924 | 0 | } |
1925 | | |
1926 | | // FastEmit functions for PPCISD::FCTIDUZ. |
1927 | | |
1928 | 0 | unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1929 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1930 | 0 | return 0; |
1931 | 0 | if ((Subtarget->hasVSX())) { |
1932 | 0 | return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0); |
1933 | 0 | } |
1934 | 0 | return 0; |
1935 | 0 | } |
1936 | | |
1937 | 0 | unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1938 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1939 | 0 | return 0; |
1940 | 0 | if ((Subtarget->hasVSX())) { |
1941 | 0 | return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0); |
1942 | 0 | } |
1943 | 0 | return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0); |
1944 | 0 | } |
1945 | | |
1946 | 0 | unsigned fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
1947 | 0 | if (RetVT.SimpleTy != MVT::f128) |
1948 | 0 | return 0; |
1949 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
1950 | 0 | return fastEmitInst_r(PPC::XSCVQPUDZ, &PPC::VRRCRegClass, Op0); |
1951 | 0 | } |
1952 | 0 | return 0; |
1953 | 0 | } |
1954 | | |
1955 | 0 | unsigned fastEmit_PPCISD_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
1956 | 0 | switch (VT.SimpleTy) { |
1957 | 0 | case MVT::f32: return fastEmit_PPCISD_FCTIDUZ_MVT_f32_r(RetVT, Op0); |
1958 | 0 | case MVT::f64: return fastEmit_PPCISD_FCTIDUZ_MVT_f64_r(RetVT, Op0); |
1959 | 0 | case MVT::f128: return fastEmit_PPCISD_FCTIDUZ_MVT_f128_r(RetVT, Op0); |
1960 | 0 | default: return 0; |
1961 | 0 | } |
1962 | 0 | } |
1963 | | |
1964 | | // FastEmit functions for PPCISD::FCTIDZ. |
1965 | | |
1966 | 0 | unsigned fastEmit_PPCISD_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
1967 | 0 | if (RetVT.SimpleTy != MVT::f32) |
1968 | 0 | return 0; |
1969 | 0 | if ((Subtarget->hasVSX())) { |
1970 | 0 | return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0); |
1971 | 0 | } |
1972 | 0 | return 0; |
1973 | 0 | } |
1974 | | |
1975 | 0 | unsigned fastEmit_PPCISD_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
1976 | 0 | if (RetVT.SimpleTy != MVT::f64) |
1977 | 0 | return 0; |
1978 | 0 | if ((Subtarget->hasVSX())) { |
1979 | 0 | return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0); |
1980 | 0 | } |
1981 | 0 | return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0); |
1982 | 0 | } |
1983 | | |
1984 | 0 | unsigned fastEmit_PPCISD_FCTIDZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
1985 | 0 | if (RetVT.SimpleTy != MVT::f128) |
1986 | 0 | return 0; |
1987 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
1988 | 0 | return fastEmitInst_r(PPC::XSCVQPSDZ, &PPC::VRRCRegClass, Op0); |
1989 | 0 | } |
1990 | 0 | return 0; |
1991 | 0 | } |
1992 | | |
1993 | 0 | unsigned fastEmit_PPCISD_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
1994 | 0 | switch (VT.SimpleTy) { |
1995 | 0 | case MVT::f32: return fastEmit_PPCISD_FCTIDZ_MVT_f32_r(RetVT, Op0); |
1996 | 0 | case MVT::f64: return fastEmit_PPCISD_FCTIDZ_MVT_f64_r(RetVT, Op0); |
1997 | 0 | case MVT::f128: return fastEmit_PPCISD_FCTIDZ_MVT_f128_r(RetVT, Op0); |
1998 | 0 | default: return 0; |
1999 | 0 | } |
2000 | 0 | } |
2001 | | |
2002 | | // FastEmit functions for PPCISD::FCTIWUZ. |
2003 | | |
2004 | 0 | unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2005 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2006 | 0 | return 0; |
2007 | 0 | if ((Subtarget->hasVSX())) { |
2008 | 0 | return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0); |
2009 | 0 | } |
2010 | 0 | return 0; |
2011 | 0 | } |
2012 | | |
2013 | 0 | unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2014 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2015 | 0 | return 0; |
2016 | 0 | if ((Subtarget->hasVSX())) { |
2017 | 0 | return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0); |
2018 | 0 | } |
2019 | 0 | return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0); |
2020 | 0 | } |
2021 | | |
2022 | 0 | unsigned fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
2023 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2024 | 0 | return 0; |
2025 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2026 | 0 | return fastEmitInst_r(PPC::XSCVQPUWZ, &PPC::VRRCRegClass, Op0); |
2027 | 0 | } |
2028 | 0 | return 0; |
2029 | 0 | } |
2030 | | |
2031 | 0 | unsigned fastEmit_PPCISD_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2032 | 0 | switch (VT.SimpleTy) { |
2033 | 0 | case MVT::f32: return fastEmit_PPCISD_FCTIWUZ_MVT_f32_r(RetVT, Op0); |
2034 | 0 | case MVT::f64: return fastEmit_PPCISD_FCTIWUZ_MVT_f64_r(RetVT, Op0); |
2035 | 0 | case MVT::f128: return fastEmit_PPCISD_FCTIWUZ_MVT_f128_r(RetVT, Op0); |
2036 | 0 | default: return 0; |
2037 | 0 | } |
2038 | 0 | } |
2039 | | |
2040 | | // FastEmit functions for PPCISD::FCTIWZ. |
2041 | | |
2042 | 0 | unsigned fastEmit_PPCISD_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2043 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2044 | 0 | return 0; |
2045 | 0 | if ((Subtarget->hasVSX())) { |
2046 | 0 | return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0); |
2047 | 0 | } |
2048 | 0 | return 0; |
2049 | 0 | } |
2050 | | |
2051 | 0 | unsigned fastEmit_PPCISD_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2052 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2053 | 0 | return 0; |
2054 | 0 | if ((Subtarget->hasVSX())) { |
2055 | 0 | return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0); |
2056 | 0 | } |
2057 | 0 | if ((Subtarget->hasFPU())) { |
2058 | 0 | return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0); |
2059 | 0 | } |
2060 | 0 | return 0; |
2061 | 0 | } |
2062 | | |
2063 | 0 | unsigned fastEmit_PPCISD_FCTIWZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
2064 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2065 | 0 | return 0; |
2066 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2067 | 0 | return fastEmitInst_r(PPC::XSCVQPSWZ, &PPC::VRRCRegClass, Op0); |
2068 | 0 | } |
2069 | 0 | return 0; |
2070 | 0 | } |
2071 | | |
2072 | 0 | unsigned fastEmit_PPCISD_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2073 | 0 | switch (VT.SimpleTy) { |
2074 | 0 | case MVT::f32: return fastEmit_PPCISD_FCTIWZ_MVT_f32_r(RetVT, Op0); |
2075 | 0 | case MVT::f64: return fastEmit_PPCISD_FCTIWZ_MVT_f64_r(RetVT, Op0); |
2076 | 0 | case MVT::f128: return fastEmit_PPCISD_FCTIWZ_MVT_f128_r(RetVT, Op0); |
2077 | 0 | default: return 0; |
2078 | 0 | } |
2079 | 0 | } |
2080 | | |
2081 | | // FastEmit functions for PPCISD::FRE. |
2082 | | |
2083 | 0 | unsigned fastEmit_PPCISD_FRE_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2084 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2085 | 0 | return 0; |
2086 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
2087 | 0 | return fastEmitInst_r(PPC::XSRESP, &PPC::VSSRCRegClass, Op0); |
2088 | 0 | } |
2089 | 0 | if ((Subtarget->hasFPU())) { |
2090 | 0 | return fastEmitInst_r(PPC::FRES, &PPC::F4RCRegClass, Op0); |
2091 | 0 | } |
2092 | 0 | return 0; |
2093 | 0 | } |
2094 | | |
2095 | 0 | unsigned fastEmit_PPCISD_FRE_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2096 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2097 | 0 | return 0; |
2098 | 0 | if ((Subtarget->hasVSX())) { |
2099 | 0 | return fastEmitInst_r(PPC::XSREDP, &PPC::VSFRCRegClass, Op0); |
2100 | 0 | } |
2101 | 0 | if ((Subtarget->hasFPU())) { |
2102 | 0 | return fastEmitInst_r(PPC::FRE, &PPC::F8RCRegClass, Op0); |
2103 | 0 | } |
2104 | 0 | return 0; |
2105 | 0 | } |
2106 | | |
2107 | 0 | unsigned fastEmit_PPCISD_FRE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
2108 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2109 | 0 | return 0; |
2110 | 0 | if ((Subtarget->hasVSX())) { |
2111 | 0 | return fastEmitInst_r(PPC::XVRESP, &PPC::VSRCRegClass, Op0); |
2112 | 0 | } |
2113 | 0 | if ((Subtarget->hasAltivec())) { |
2114 | 0 | return fastEmitInst_r(PPC::VREFP, &PPC::VRRCRegClass, Op0); |
2115 | 0 | } |
2116 | 0 | return 0; |
2117 | 0 | } |
2118 | | |
2119 | 0 | unsigned fastEmit_PPCISD_FRE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
2120 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2121 | 0 | return 0; |
2122 | 0 | if ((Subtarget->hasVSX())) { |
2123 | 0 | return fastEmitInst_r(PPC::XVREDP, &PPC::VSRCRegClass, Op0); |
2124 | 0 | } |
2125 | 0 | return 0; |
2126 | 0 | } |
2127 | | |
2128 | 0 | unsigned fastEmit_PPCISD_FRE_r(MVT VT, MVT RetVT, unsigned Op0) { |
2129 | 0 | switch (VT.SimpleTy) { |
2130 | 0 | case MVT::f32: return fastEmit_PPCISD_FRE_MVT_f32_r(RetVT, Op0); |
2131 | 0 | case MVT::f64: return fastEmit_PPCISD_FRE_MVT_f64_r(RetVT, Op0); |
2132 | 0 | case MVT::v4f32: return fastEmit_PPCISD_FRE_MVT_v4f32_r(RetVT, Op0); |
2133 | 0 | case MVT::v2f64: return fastEmit_PPCISD_FRE_MVT_v2f64_r(RetVT, Op0); |
2134 | 0 | default: return 0; |
2135 | 0 | } |
2136 | 0 | } |
2137 | | |
2138 | | // FastEmit functions for PPCISD::FRSQRTE. |
2139 | | |
2140 | 0 | unsigned fastEmit_PPCISD_FRSQRTE_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2141 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2142 | 0 | return 0; |
2143 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
2144 | 0 | return fastEmitInst_r(PPC::XSRSQRTESP, &PPC::VSSRCRegClass, Op0); |
2145 | 0 | } |
2146 | 0 | if ((Subtarget->hasFPU())) { |
2147 | 0 | return fastEmitInst_r(PPC::FRSQRTES, &PPC::F4RCRegClass, Op0); |
2148 | 0 | } |
2149 | 0 | return 0; |
2150 | 0 | } |
2151 | | |
2152 | 0 | unsigned fastEmit_PPCISD_FRSQRTE_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2153 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2154 | 0 | return 0; |
2155 | 0 | if ((Subtarget->hasVSX())) { |
2156 | 0 | return fastEmitInst_r(PPC::XSRSQRTEDP, &PPC::VSFRCRegClass, Op0); |
2157 | 0 | } |
2158 | 0 | if ((Subtarget->hasFPU())) { |
2159 | 0 | return fastEmitInst_r(PPC::FRSQRTE, &PPC::F8RCRegClass, Op0); |
2160 | 0 | } |
2161 | 0 | return 0; |
2162 | 0 | } |
2163 | | |
2164 | 0 | unsigned fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
2165 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2166 | 0 | return 0; |
2167 | 0 | if ((Subtarget->hasVSX())) { |
2168 | 0 | return fastEmitInst_r(PPC::XVRSQRTESP, &PPC::VSRCRegClass, Op0); |
2169 | 0 | } |
2170 | 0 | if ((Subtarget->hasAltivec())) { |
2171 | 0 | return fastEmitInst_r(PPC::VRSQRTEFP, &PPC::VRRCRegClass, Op0); |
2172 | 0 | } |
2173 | 0 | return 0; |
2174 | 0 | } |
2175 | | |
2176 | 0 | unsigned fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
2177 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2178 | 0 | return 0; |
2179 | 0 | if ((Subtarget->hasVSX())) { |
2180 | 0 | return fastEmitInst_r(PPC::XVRSQRTEDP, &PPC::VSRCRegClass, Op0); |
2181 | 0 | } |
2182 | 0 | return 0; |
2183 | 0 | } |
2184 | | |
2185 | 0 | unsigned fastEmit_PPCISD_FRSQRTE_r(MVT VT, MVT RetVT, unsigned Op0) { |
2186 | 0 | switch (VT.SimpleTy) { |
2187 | 0 | case MVT::f32: return fastEmit_PPCISD_FRSQRTE_MVT_f32_r(RetVT, Op0); |
2188 | 0 | case MVT::f64: return fastEmit_PPCISD_FRSQRTE_MVT_f64_r(RetVT, Op0); |
2189 | 0 | case MVT::v4f32: return fastEmit_PPCISD_FRSQRTE_MVT_v4f32_r(RetVT, Op0); |
2190 | 0 | case MVT::v2f64: return fastEmit_PPCISD_FRSQRTE_MVT_v2f64_r(RetVT, Op0); |
2191 | 0 | default: return 0; |
2192 | 0 | } |
2193 | 0 | } |
2194 | | |
2195 | | // FastEmit functions for PPCISD::FSQRT. |
2196 | | |
2197 | 0 | unsigned fastEmit_PPCISD_FSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2198 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2199 | 0 | return 0; |
2200 | 0 | if ((Subtarget->hasVSX())) { |
2201 | 0 | return fastEmitInst_r(PPC::XSSQRTDP, &PPC::VSFRCRegClass, Op0); |
2202 | 0 | } |
2203 | 0 | return fastEmitInst_r(PPC::FSQRT, &PPC::F8RCRegClass, Op0); |
2204 | 0 | } |
2205 | | |
2206 | 0 | unsigned fastEmit_PPCISD_FSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
2207 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2208 | 0 | return 0; |
2209 | 0 | if ((Subtarget->hasVSX())) { |
2210 | 0 | return fastEmitInst_r(PPC::XVSQRTSP, &PPC::VSRCRegClass, Op0); |
2211 | 0 | } |
2212 | 0 | return 0; |
2213 | 0 | } |
2214 | | |
2215 | 0 | unsigned fastEmit_PPCISD_FSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
2216 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2217 | 0 | return 0; |
2218 | 0 | if ((Subtarget->hasVSX())) { |
2219 | 0 | return fastEmitInst_r(PPC::XVSQRTDP, &PPC::VSRCRegClass, Op0); |
2220 | 0 | } |
2221 | 0 | return 0; |
2222 | 0 | } |
2223 | | |
2224 | 0 | unsigned fastEmit_PPCISD_FSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
2225 | 0 | switch (VT.SimpleTy) { |
2226 | 0 | case MVT::f64: return fastEmit_PPCISD_FSQRT_MVT_f64_r(RetVT, Op0); |
2227 | 0 | case MVT::v4f32: return fastEmit_PPCISD_FSQRT_MVT_v4f32_r(RetVT, Op0); |
2228 | 0 | case MVT::v2f64: return fastEmit_PPCISD_FSQRT_MVT_v2f64_r(RetVT, Op0); |
2229 | 0 | default: return 0; |
2230 | 0 | } |
2231 | 0 | } |
2232 | | |
2233 | | // FastEmit functions for PPCISD::FTSQRT. |
2234 | | |
2235 | 0 | unsigned fastEmit_PPCISD_FTSQRT_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2236 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2237 | 0 | return 0; |
2238 | 0 | if ((Subtarget->hasVSX())) { |
2239 | 0 | return fastEmitInst_r(PPC::XSTSQRTDP, &PPC::CRRCRegClass, Op0); |
2240 | 0 | } |
2241 | 0 | if ((Subtarget->hasFPU())) { |
2242 | 0 | return fastEmitInst_r(PPC::FTSQRT, &PPC::CRRCRegClass, Op0); |
2243 | 0 | } |
2244 | 0 | return 0; |
2245 | 0 | } |
2246 | | |
2247 | 0 | unsigned fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(MVT RetVT, unsigned Op0) { |
2248 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2249 | 0 | return 0; |
2250 | 0 | if ((Subtarget->hasVSX())) { |
2251 | 0 | return fastEmitInst_r(PPC::XVTSQRTSP, &PPC::CRRCRegClass, Op0); |
2252 | 0 | } |
2253 | 0 | return 0; |
2254 | 0 | } |
2255 | | |
2256 | 0 | unsigned fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(MVT RetVT, unsigned Op0) { |
2257 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2258 | 0 | return 0; |
2259 | 0 | if ((Subtarget->hasVSX())) { |
2260 | 0 | return fastEmitInst_r(PPC::XVTSQRTDP, &PPC::CRRCRegClass, Op0); |
2261 | 0 | } |
2262 | 0 | return 0; |
2263 | 0 | } |
2264 | | |
2265 | 0 | unsigned fastEmit_PPCISD_FTSQRT_r(MVT VT, MVT RetVT, unsigned Op0) { |
2266 | 0 | switch (VT.SimpleTy) { |
2267 | 0 | case MVT::f64: return fastEmit_PPCISD_FTSQRT_MVT_f64_r(RetVT, Op0); |
2268 | 0 | case MVT::v4f32: return fastEmit_PPCISD_FTSQRT_MVT_v4f32_r(RetVT, Op0); |
2269 | 0 | case MVT::v2f64: return fastEmit_PPCISD_FTSQRT_MVT_v2f64_r(RetVT, Op0); |
2270 | 0 | default: return 0; |
2271 | 0 | } |
2272 | 0 | } |
2273 | | |
2274 | | // FastEmit functions for PPCISD::MFVSR. |
2275 | | |
2276 | 0 | unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(unsigned Op0) { |
2277 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
2278 | 0 | return fastEmitInst_r(PPC::MFVSRWZ, &PPC::GPRCRegClass, Op0); |
2279 | 0 | } |
2280 | 0 | return 0; |
2281 | 0 | } |
2282 | | |
2283 | 0 | unsigned fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(unsigned Op0) { |
2284 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
2285 | 0 | return fastEmitInst_r(PPC::MFVSRD, &PPC::G8RCRegClass, Op0); |
2286 | 0 | } |
2287 | 0 | return 0; |
2288 | 0 | } |
2289 | | |
2290 | 0 | unsigned fastEmit_PPCISD_MFVSR_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2291 | 0 | switch (RetVT.SimpleTy) { |
2292 | 0 | case MVT::i32: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i32_r(Op0); |
2293 | 0 | case MVT::i64: return fastEmit_PPCISD_MFVSR_MVT_f64_MVT_i64_r(Op0); |
2294 | 0 | default: return 0; |
2295 | 0 | } |
2296 | 0 | } |
2297 | | |
2298 | 0 | unsigned fastEmit_PPCISD_MFVSR_r(MVT VT, MVT RetVT, unsigned Op0) { |
2299 | 0 | switch (VT.SimpleTy) { |
2300 | 0 | case MVT::f64: return fastEmit_PPCISD_MFVSR_MVT_f64_r(RetVT, Op0); |
2301 | 0 | default: return 0; |
2302 | 0 | } |
2303 | 0 | } |
2304 | | |
2305 | | // FastEmit functions for PPCISD::MTCTR. |
2306 | | |
2307 | 0 | unsigned fastEmit_PPCISD_MTCTR_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2308 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2309 | 0 | return 0; |
2310 | 0 | return fastEmitInst_r(PPC::MTCTR, &PPC::GPRCRegClass, Op0); |
2311 | 0 | } |
2312 | | |
2313 | 0 | unsigned fastEmit_PPCISD_MTCTR_MVT_i64_r(MVT RetVT, unsigned Op0) { |
2314 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
2315 | 0 | return 0; |
2316 | 0 | return fastEmitInst_r(PPC::MTCTR8, &PPC::G8RCRegClass, Op0); |
2317 | 0 | } |
2318 | | |
2319 | 0 | unsigned fastEmit_PPCISD_MTCTR_r(MVT VT, MVT RetVT, unsigned Op0) { |
2320 | 0 | switch (VT.SimpleTy) { |
2321 | 0 | case MVT::i32: return fastEmit_PPCISD_MTCTR_MVT_i32_r(RetVT, Op0); |
2322 | 0 | case MVT::i64: return fastEmit_PPCISD_MTCTR_MVT_i64_r(RetVT, Op0); |
2323 | 0 | default: return 0; |
2324 | 0 | } |
2325 | 0 | } |
2326 | | |
2327 | | // FastEmit functions for PPCISD::MTVSRA. |
2328 | | |
2329 | 0 | unsigned fastEmit_PPCISD_MTVSRA_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2330 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2331 | 0 | return 0; |
2332 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
2333 | 0 | return fastEmitInst_r(PPC::MTVSRWA, &PPC::VSFRCRegClass, Op0); |
2334 | 0 | } |
2335 | 0 | return 0; |
2336 | 0 | } |
2337 | | |
2338 | 0 | unsigned fastEmit_PPCISD_MTVSRA_MVT_i64_r(MVT RetVT, unsigned Op0) { |
2339 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2340 | 0 | return 0; |
2341 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
2342 | 0 | return fastEmitInst_r(PPC::MTVSRD, &PPC::VSFRCRegClass, Op0); |
2343 | 0 | } |
2344 | 0 | return 0; |
2345 | 0 | } |
2346 | | |
2347 | 0 | unsigned fastEmit_PPCISD_MTVSRA_r(MVT VT, MVT RetVT, unsigned Op0) { |
2348 | 0 | switch (VT.SimpleTy) { |
2349 | 0 | case MVT::i32: return fastEmit_PPCISD_MTVSRA_MVT_i32_r(RetVT, Op0); |
2350 | 0 | case MVT::i64: return fastEmit_PPCISD_MTVSRA_MVT_i64_r(RetVT, Op0); |
2351 | 0 | default: return 0; |
2352 | 0 | } |
2353 | 0 | } |
2354 | | |
2355 | | // FastEmit functions for PPCISD::MTVSRZ. |
2356 | | |
2357 | 0 | unsigned fastEmit_PPCISD_MTVSRZ_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2358 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2359 | 0 | return 0; |
2360 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX())) { |
2361 | 0 | return fastEmitInst_r(PPC::MTVSRWZ, &PPC::VSFRCRegClass, Op0); |
2362 | 0 | } |
2363 | 0 | return 0; |
2364 | 0 | } |
2365 | | |
2366 | 0 | unsigned fastEmit_PPCISD_MTVSRZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2367 | 0 | switch (VT.SimpleTy) { |
2368 | 0 | case MVT::i32: return fastEmit_PPCISD_MTVSRZ_MVT_i32_r(RetVT, Op0); |
2369 | 0 | default: return 0; |
2370 | 0 | } |
2371 | 0 | } |
2372 | | |
2373 | | // FastEmit functions for PPCISD::SCALAR_TO_VECTOR_PERMUTED. |
2374 | | |
2375 | 0 | unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2376 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2377 | 0 | return 0; |
2378 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (Subtarget->isLittleEndian())) { |
2379 | 0 | return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); |
2380 | 0 | } |
2381 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian())) { |
2382 | 0 | return fastEmitInst_r(PPC::XSCVDPSPN, &PPC::VSRCRegClass, Op0); |
2383 | 0 | } |
2384 | 0 | return 0; |
2385 | 0 | } |
2386 | | |
2387 | 0 | unsigned fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(MVT VT, MVT RetVT, unsigned Op0) { |
2388 | 0 | switch (VT.SimpleTy) { |
2389 | 0 | case MVT::f32: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_MVT_f32_r(RetVT, Op0); |
2390 | 0 | default: return 0; |
2391 | 0 | } |
2392 | 0 | } |
2393 | | |
2394 | | // FastEmit functions for PPCISD::STRICT_FCFID. |
2395 | | |
2396 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2397 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2398 | 0 | return 0; |
2399 | 0 | if ((Subtarget->hasVSX())) { |
2400 | 0 | return fastEmitInst_r(PPC::XSCVSXDDP, &PPC::VSFRCRegClass, Op0); |
2401 | 0 | } |
2402 | 0 | return fastEmitInst_r(PPC::FCFID, &PPC::F8RCRegClass, Op0); |
2403 | 0 | } |
2404 | | |
2405 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFID_r(MVT VT, MVT RetVT, unsigned Op0) { |
2406 | 0 | switch (VT.SimpleTy) { |
2407 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCFID_MVT_f64_r(RetVT, Op0); |
2408 | 0 | default: return 0; |
2409 | 0 | } |
2410 | 0 | } |
2411 | | |
2412 | | // FastEmit functions for PPCISD::STRICT_FCFIDS. |
2413 | | |
2414 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2415 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2416 | 0 | return 0; |
2417 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
2418 | 0 | return fastEmitInst_r(PPC::XSCVSXDSP, &PPC::VSSRCRegClass, Op0); |
2419 | 0 | } |
2420 | 0 | return fastEmitInst_r(PPC::FCFIDS, &PPC::F4RCRegClass, Op0); |
2421 | 0 | } |
2422 | | |
2423 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFIDS_r(MVT VT, MVT RetVT, unsigned Op0) { |
2424 | 0 | switch (VT.SimpleTy) { |
2425 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDS_MVT_f64_r(RetVT, Op0); |
2426 | 0 | default: return 0; |
2427 | 0 | } |
2428 | 0 | } |
2429 | | |
2430 | | // FastEmit functions for PPCISD::STRICT_FCFIDU. |
2431 | | |
2432 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2433 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2434 | 0 | return 0; |
2435 | 0 | if ((Subtarget->hasVSX())) { |
2436 | 0 | return fastEmitInst_r(PPC::XSCVUXDDP, &PPC::VSFRCRegClass, Op0); |
2437 | 0 | } |
2438 | 0 | return fastEmitInst_r(PPC::FCFIDU, &PPC::F8RCRegClass, Op0); |
2439 | 0 | } |
2440 | | |
2441 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFIDU_r(MVT VT, MVT RetVT, unsigned Op0) { |
2442 | 0 | switch (VT.SimpleTy) { |
2443 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDU_MVT_f64_r(RetVT, Op0); |
2444 | 0 | default: return 0; |
2445 | 0 | } |
2446 | 0 | } |
2447 | | |
2448 | | // FastEmit functions for PPCISD::STRICT_FCFIDUS. |
2449 | | |
2450 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2451 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2452 | 0 | return 0; |
2453 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
2454 | 0 | return fastEmitInst_r(PPC::XSCVUXDSP, &PPC::VSSRCRegClass, Op0); |
2455 | 0 | } |
2456 | 0 | return fastEmitInst_r(PPC::FCFIDUS, &PPC::F4RCRegClass, Op0); |
2457 | 0 | } |
2458 | | |
2459 | 0 | unsigned fastEmit_PPCISD_STRICT_FCFIDUS_r(MVT VT, MVT RetVT, unsigned Op0) { |
2460 | 0 | switch (VT.SimpleTy) { |
2461 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCFIDUS_MVT_f64_r(RetVT, Op0); |
2462 | 0 | default: return 0; |
2463 | 0 | } |
2464 | 0 | } |
2465 | | |
2466 | | // FastEmit functions for PPCISD::STRICT_FCTIDUZ. |
2467 | | |
2468 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2469 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2470 | 0 | return 0; |
2471 | 0 | if ((Subtarget->hasVSX())) { |
2472 | 0 | return fastEmitInst_r(PPC::XSCVDPUXDSs, &PPC::VSSRCRegClass, Op0); |
2473 | 0 | } |
2474 | 0 | return 0; |
2475 | 0 | } |
2476 | | |
2477 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2478 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2479 | 0 | return 0; |
2480 | 0 | if ((Subtarget->hasVSX())) { |
2481 | 0 | return fastEmitInst_r(PPC::XSCVDPUXDS, &PPC::VSFRCRegClass, Op0); |
2482 | 0 | } |
2483 | 0 | return fastEmitInst_r(PPC::FCTIDUZ, &PPC::F8RCRegClass, Op0); |
2484 | 0 | } |
2485 | | |
2486 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
2487 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2488 | 0 | return 0; |
2489 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2490 | 0 | return fastEmitInst_r(PPC::XSCVQPUDZ, &PPC::VRRCRegClass, Op0); |
2491 | 0 | } |
2492 | 0 | return 0; |
2493 | 0 | } |
2494 | | |
2495 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2496 | 0 | switch (VT.SimpleTy) { |
2497 | 0 | case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f32_r(RetVT, Op0); |
2498 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f64_r(RetVT, Op0); |
2499 | 0 | case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDUZ_MVT_f128_r(RetVT, Op0); |
2500 | 0 | default: return 0; |
2501 | 0 | } |
2502 | 0 | } |
2503 | | |
2504 | | // FastEmit functions for PPCISD::STRICT_FCTIDZ. |
2505 | | |
2506 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2507 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2508 | 0 | return 0; |
2509 | 0 | if ((Subtarget->hasVSX())) { |
2510 | 0 | return fastEmitInst_r(PPC::XSCVDPSXDSs, &PPC::VSSRCRegClass, Op0); |
2511 | 0 | } |
2512 | 0 | return 0; |
2513 | 0 | } |
2514 | | |
2515 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2516 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2517 | 0 | return 0; |
2518 | 0 | if ((Subtarget->hasVSX())) { |
2519 | 0 | return fastEmitInst_r(PPC::XSCVDPSXDS, &PPC::VSFRCRegClass, Op0); |
2520 | 0 | } |
2521 | 0 | return fastEmitInst_r(PPC::FCTIDZ, &PPC::F8RCRegClass, Op0); |
2522 | 0 | } |
2523 | | |
2524 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
2525 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2526 | 0 | return 0; |
2527 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2528 | 0 | return fastEmitInst_r(PPC::XSCVQPSDZ, &PPC::VRRCRegClass, Op0); |
2529 | 0 | } |
2530 | 0 | return 0; |
2531 | 0 | } |
2532 | | |
2533 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIDZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2534 | 0 | switch (VT.SimpleTy) { |
2535 | 0 | case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f32_r(RetVT, Op0); |
2536 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f64_r(RetVT, Op0); |
2537 | 0 | case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIDZ_MVT_f128_r(RetVT, Op0); |
2538 | 0 | default: return 0; |
2539 | 0 | } |
2540 | 0 | } |
2541 | | |
2542 | | // FastEmit functions for PPCISD::STRICT_FCTIWUZ. |
2543 | | |
2544 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2545 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2546 | 0 | return 0; |
2547 | 0 | if ((Subtarget->hasVSX())) { |
2548 | 0 | return fastEmitInst_r(PPC::XSCVDPUXWSs, &PPC::VSSRCRegClass, Op0); |
2549 | 0 | } |
2550 | 0 | return 0; |
2551 | 0 | } |
2552 | | |
2553 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2554 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2555 | 0 | return 0; |
2556 | 0 | if ((Subtarget->hasVSX())) { |
2557 | 0 | return fastEmitInst_r(PPC::XSCVDPUXWS, &PPC::VSFRCRegClass, Op0); |
2558 | 0 | } |
2559 | 0 | return fastEmitInst_r(PPC::FCTIWUZ, &PPC::F8RCRegClass, Op0); |
2560 | 0 | } |
2561 | | |
2562 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
2563 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2564 | 0 | return 0; |
2565 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2566 | 0 | return fastEmitInst_r(PPC::XSCVQPUWZ, &PPC::VRRCRegClass, Op0); |
2567 | 0 | } |
2568 | 0 | return 0; |
2569 | 0 | } |
2570 | | |
2571 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWUZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2572 | 0 | switch (VT.SimpleTy) { |
2573 | 0 | case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f32_r(RetVT, Op0); |
2574 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f64_r(RetVT, Op0); |
2575 | 0 | case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWUZ_MVT_f128_r(RetVT, Op0); |
2576 | 0 | default: return 0; |
2577 | 0 | } |
2578 | 0 | } |
2579 | | |
2580 | | // FastEmit functions for PPCISD::STRICT_FCTIWZ. |
2581 | | |
2582 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(MVT RetVT, unsigned Op0) { |
2583 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2584 | 0 | return 0; |
2585 | 0 | if ((Subtarget->hasVSX())) { |
2586 | 0 | return fastEmitInst_r(PPC::XSCVDPSXWSs, &PPC::VSSRCRegClass, Op0); |
2587 | 0 | } |
2588 | 0 | return 0; |
2589 | 0 | } |
2590 | | |
2591 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(MVT RetVT, unsigned Op0) { |
2592 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2593 | 0 | return 0; |
2594 | 0 | if ((Subtarget->hasVSX())) { |
2595 | 0 | return fastEmitInst_r(PPC::XSCVDPSXWS, &PPC::VSFRCRegClass, Op0); |
2596 | 0 | } |
2597 | 0 | if ((Subtarget->hasFPU())) { |
2598 | 0 | return fastEmitInst_r(PPC::FCTIWZ, &PPC::F8RCRegClass, Op0); |
2599 | 0 | } |
2600 | 0 | return 0; |
2601 | 0 | } |
2602 | | |
2603 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(MVT RetVT, unsigned Op0) { |
2604 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2605 | 0 | return 0; |
2606 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2607 | 0 | return fastEmitInst_r(PPC::XSCVQPSWZ, &PPC::VRRCRegClass, Op0); |
2608 | 0 | } |
2609 | 0 | return 0; |
2610 | 0 | } |
2611 | | |
2612 | 0 | unsigned fastEmit_PPCISD_STRICT_FCTIWZ_r(MVT VT, MVT RetVT, unsigned Op0) { |
2613 | 0 | switch (VT.SimpleTy) { |
2614 | 0 | case MVT::f32: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f32_r(RetVT, Op0); |
2615 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f64_r(RetVT, Op0); |
2616 | 0 | case MVT::f128: return fastEmit_PPCISD_STRICT_FCTIWZ_MVT_f128_r(RetVT, Op0); |
2617 | 0 | default: return 0; |
2618 | 0 | } |
2619 | 0 | } |
2620 | | |
2621 | | // FastEmit functions for PPCISD::XXMFACC. |
2622 | | |
2623 | 0 | unsigned fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(MVT RetVT, unsigned Op0) { |
2624 | 0 | if (RetVT.SimpleTy != MVT::v512i1) |
2625 | 0 | return 0; |
2626 | 0 | if ((!Subtarget->isISAFuture()) && (Subtarget->hasMMA())) { |
2627 | 0 | return fastEmitInst_r(PPC::XXMFACC, &PPC::ACCRCRegClass, Op0); |
2628 | 0 | } |
2629 | 0 | return 0; |
2630 | 0 | } |
2631 | | |
2632 | 0 | unsigned fastEmit_PPCISD_XXMFACC_r(MVT VT, MVT RetVT, unsigned Op0) { |
2633 | 0 | switch (VT.SimpleTy) { |
2634 | 0 | case MVT::v512i1: return fastEmit_PPCISD_XXMFACC_MVT_v512i1_r(RetVT, Op0); |
2635 | 0 | default: return 0; |
2636 | 0 | } |
2637 | 0 | } |
2638 | | |
2639 | | // FastEmit functions for PPCISD::XXSPLTI_SP_TO_DP. |
2640 | | |
2641 | 0 | unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(MVT RetVT, unsigned Op0) { |
2642 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
2643 | 0 | return 0; |
2644 | 0 | if ((Subtarget->hasPrefixInstrs())) { |
2645 | 0 | return fastEmitInst_r(PPC::XXSPLTIDP, &PPC::VSRCRegClass, Op0); |
2646 | 0 | } |
2647 | 0 | return 0; |
2648 | 0 | } |
2649 | | |
2650 | 0 | unsigned fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(MVT VT, MVT RetVT, unsigned Op0) { |
2651 | 0 | switch (VT.SimpleTy) { |
2652 | 0 | case MVT::i32: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_MVT_i32_r(RetVT, Op0); |
2653 | 0 | default: return 0; |
2654 | 0 | } |
2655 | 0 | } |
2656 | | |
2657 | | // Top-level FastEmit function. |
2658 | | |
2659 | 0 | unsigned fastEmit_r(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0) override { |
2660 | 0 | switch (Opcode) { |
2661 | 0 | case ISD::ANY_EXTEND: return fastEmit_ISD_ANY_EXTEND_r(VT, RetVT, Op0); |
2662 | 0 | case ISD::BITCAST: return fastEmit_ISD_BITCAST_r(VT, RetVT, Op0); |
2663 | 0 | case ISD::BSWAP: return fastEmit_ISD_BSWAP_r(VT, RetVT, Op0); |
2664 | 0 | case ISD::CTLZ: return fastEmit_ISD_CTLZ_r(VT, RetVT, Op0); |
2665 | 0 | case ISD::CTPOP: return fastEmit_ISD_CTPOP_r(VT, RetVT, Op0); |
2666 | 0 | case ISD::CTTZ: return fastEmit_ISD_CTTZ_r(VT, RetVT, Op0); |
2667 | 0 | case ISD::FABS: return fastEmit_ISD_FABS_r(VT, RetVT, Op0); |
2668 | 0 | case ISD::FCEIL: return fastEmit_ISD_FCEIL_r(VT, RetVT, Op0); |
2669 | 0 | case ISD::FFLOOR: return fastEmit_ISD_FFLOOR_r(VT, RetVT, Op0); |
2670 | 0 | case ISD::FNEARBYINT: return fastEmit_ISD_FNEARBYINT_r(VT, RetVT, Op0); |
2671 | 0 | case ISD::FNEG: return fastEmit_ISD_FNEG_r(VT, RetVT, Op0); |
2672 | 0 | case ISD::FP_EXTEND: return fastEmit_ISD_FP_EXTEND_r(VT, RetVT, Op0); |
2673 | 0 | case ISD::FP_ROUND: return fastEmit_ISD_FP_ROUND_r(VT, RetVT, Op0); |
2674 | 0 | case ISD::FP_TO_SINT: return fastEmit_ISD_FP_TO_SINT_r(VT, RetVT, Op0); |
2675 | 0 | case ISD::FP_TO_UINT: return fastEmit_ISD_FP_TO_UINT_r(VT, RetVT, Op0); |
2676 | 0 | case ISD::FRINT: return fastEmit_ISD_FRINT_r(VT, RetVT, Op0); |
2677 | 0 | case ISD::FROUND: return fastEmit_ISD_FROUND_r(VT, RetVT, Op0); |
2678 | 0 | case ISD::FSQRT: return fastEmit_ISD_FSQRT_r(VT, RetVT, Op0); |
2679 | 0 | case ISD::FTRUNC: return fastEmit_ISD_FTRUNC_r(VT, RetVT, Op0); |
2680 | 0 | case ISD::SCALAR_TO_VECTOR: return fastEmit_ISD_SCALAR_TO_VECTOR_r(VT, RetVT, Op0); |
2681 | 0 | case ISD::SIGN_EXTEND: return fastEmit_ISD_SIGN_EXTEND_r(VT, RetVT, Op0); |
2682 | 0 | case ISD::SINT_TO_FP: return fastEmit_ISD_SINT_TO_FP_r(VT, RetVT, Op0); |
2683 | 0 | case ISD::STRICT_FCEIL: return fastEmit_ISD_STRICT_FCEIL_r(VT, RetVT, Op0); |
2684 | 0 | case ISD::STRICT_FFLOOR: return fastEmit_ISD_STRICT_FFLOOR_r(VT, RetVT, Op0); |
2685 | 0 | case ISD::STRICT_FP_EXTEND: return fastEmit_ISD_STRICT_FP_EXTEND_r(VT, RetVT, Op0); |
2686 | 0 | case ISD::STRICT_FP_ROUND: return fastEmit_ISD_STRICT_FP_ROUND_r(VT, RetVT, Op0); |
2687 | 0 | case ISD::STRICT_FP_TO_SINT: return fastEmit_ISD_STRICT_FP_TO_SINT_r(VT, RetVT, Op0); |
2688 | 0 | case ISD::STRICT_FP_TO_UINT: return fastEmit_ISD_STRICT_FP_TO_UINT_r(VT, RetVT, Op0); |
2689 | 0 | case ISD::STRICT_FRINT: return fastEmit_ISD_STRICT_FRINT_r(VT, RetVT, Op0); |
2690 | 0 | case ISD::STRICT_FROUND: return fastEmit_ISD_STRICT_FROUND_r(VT, RetVT, Op0); |
2691 | 0 | case ISD::STRICT_FSQRT: return fastEmit_ISD_STRICT_FSQRT_r(VT, RetVT, Op0); |
2692 | 0 | case ISD::STRICT_FTRUNC: return fastEmit_ISD_STRICT_FTRUNC_r(VT, RetVT, Op0); |
2693 | 0 | case ISD::STRICT_SINT_TO_FP: return fastEmit_ISD_STRICT_SINT_TO_FP_r(VT, RetVT, Op0); |
2694 | 0 | case ISD::STRICT_UINT_TO_FP: return fastEmit_ISD_STRICT_UINT_TO_FP_r(VT, RetVT, Op0); |
2695 | 0 | case ISD::TRUNCATE: return fastEmit_ISD_TRUNCATE_r(VT, RetVT, Op0); |
2696 | 0 | case ISD::UINT_TO_FP: return fastEmit_ISD_UINT_TO_FP_r(VT, RetVT, Op0); |
2697 | 0 | case ISD::ZERO_EXTEND: return fastEmit_ISD_ZERO_EXTEND_r(VT, RetVT, Op0); |
2698 | 0 | case PPCISD::FCFID: return fastEmit_PPCISD_FCFID_r(VT, RetVT, Op0); |
2699 | 0 | case PPCISD::FCFIDS: return fastEmit_PPCISD_FCFIDS_r(VT, RetVT, Op0); |
2700 | 0 | case PPCISD::FCFIDU: return fastEmit_PPCISD_FCFIDU_r(VT, RetVT, Op0); |
2701 | 0 | case PPCISD::FCFIDUS: return fastEmit_PPCISD_FCFIDUS_r(VT, RetVT, Op0); |
2702 | 0 | case PPCISD::FCTIDUZ: return fastEmit_PPCISD_FCTIDUZ_r(VT, RetVT, Op0); |
2703 | 0 | case PPCISD::FCTIDZ: return fastEmit_PPCISD_FCTIDZ_r(VT, RetVT, Op0); |
2704 | 0 | case PPCISD::FCTIWUZ: return fastEmit_PPCISD_FCTIWUZ_r(VT, RetVT, Op0); |
2705 | 0 | case PPCISD::FCTIWZ: return fastEmit_PPCISD_FCTIWZ_r(VT, RetVT, Op0); |
2706 | 0 | case PPCISD::FRE: return fastEmit_PPCISD_FRE_r(VT, RetVT, Op0); |
2707 | 0 | case PPCISD::FRSQRTE: return fastEmit_PPCISD_FRSQRTE_r(VT, RetVT, Op0); |
2708 | 0 | case PPCISD::FSQRT: return fastEmit_PPCISD_FSQRT_r(VT, RetVT, Op0); |
2709 | 0 | case PPCISD::FTSQRT: return fastEmit_PPCISD_FTSQRT_r(VT, RetVT, Op0); |
2710 | 0 | case PPCISD::MFVSR: return fastEmit_PPCISD_MFVSR_r(VT, RetVT, Op0); |
2711 | 0 | case PPCISD::MTCTR: return fastEmit_PPCISD_MTCTR_r(VT, RetVT, Op0); |
2712 | 0 | case PPCISD::MTVSRA: return fastEmit_PPCISD_MTVSRA_r(VT, RetVT, Op0); |
2713 | 0 | case PPCISD::MTVSRZ: return fastEmit_PPCISD_MTVSRZ_r(VT, RetVT, Op0); |
2714 | 0 | case PPCISD::SCALAR_TO_VECTOR_PERMUTED: return fastEmit_PPCISD_SCALAR_TO_VECTOR_PERMUTED_r(VT, RetVT, Op0); |
2715 | 0 | case PPCISD::STRICT_FCFID: return fastEmit_PPCISD_STRICT_FCFID_r(VT, RetVT, Op0); |
2716 | 0 | case PPCISD::STRICT_FCFIDS: return fastEmit_PPCISD_STRICT_FCFIDS_r(VT, RetVT, Op0); |
2717 | 0 | case PPCISD::STRICT_FCFIDU: return fastEmit_PPCISD_STRICT_FCFIDU_r(VT, RetVT, Op0); |
2718 | 0 | case PPCISD::STRICT_FCFIDUS: return fastEmit_PPCISD_STRICT_FCFIDUS_r(VT, RetVT, Op0); |
2719 | 0 | case PPCISD::STRICT_FCTIDUZ: return fastEmit_PPCISD_STRICT_FCTIDUZ_r(VT, RetVT, Op0); |
2720 | 0 | case PPCISD::STRICT_FCTIDZ: return fastEmit_PPCISD_STRICT_FCTIDZ_r(VT, RetVT, Op0); |
2721 | 0 | case PPCISD::STRICT_FCTIWUZ: return fastEmit_PPCISD_STRICT_FCTIWUZ_r(VT, RetVT, Op0); |
2722 | 0 | case PPCISD::STRICT_FCTIWZ: return fastEmit_PPCISD_STRICT_FCTIWZ_r(VT, RetVT, Op0); |
2723 | 0 | case PPCISD::XXMFACC: return fastEmit_PPCISD_XXMFACC_r(VT, RetVT, Op0); |
2724 | 0 | case PPCISD::XXSPLTI_SP_TO_DP: return fastEmit_PPCISD_XXSPLTI_SP_TO_DP_r(VT, RetVT, Op0); |
2725 | 0 | default: return 0; |
2726 | 0 | } |
2727 | 0 | } |
2728 | | |
2729 | | // FastEmit functions for ISD::ABDU. |
2730 | | |
2731 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2732 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
2733 | 0 | return 0; |
2734 | 0 | if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) { |
2735 | 0 | return fastEmitInst_rr(PPC::VABSDUB, &PPC::VRRCRegClass, Op0, Op1); |
2736 | 0 | } |
2737 | 0 | return 0; |
2738 | 0 | } |
2739 | | |
2740 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2741 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
2742 | 0 | return 0; |
2743 | 0 | if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) { |
2744 | 0 | return fastEmitInst_rr(PPC::VABSDUH, &PPC::VRRCRegClass, Op0, Op1); |
2745 | 0 | } |
2746 | 0 | return 0; |
2747 | 0 | } |
2748 | | |
2749 | 0 | unsigned fastEmit_ISD_ABDU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2750 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2751 | 0 | return 0; |
2752 | 0 | if ((Subtarget->hasP9Altivec()) && (Subtarget->hasVSX())) { |
2753 | 0 | return fastEmitInst_rr(PPC::VABSDUW, &PPC::VRRCRegClass, Op0, Op1); |
2754 | 0 | } |
2755 | 0 | return 0; |
2756 | 0 | } |
2757 | | |
2758 | 0 | unsigned fastEmit_ISD_ABDU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
2759 | 0 | switch (VT.SimpleTy) { |
2760 | 0 | case MVT::v16i8: return fastEmit_ISD_ABDU_MVT_v16i8_rr(RetVT, Op0, Op1); |
2761 | 0 | case MVT::v8i16: return fastEmit_ISD_ABDU_MVT_v8i16_rr(RetVT, Op0, Op1); |
2762 | 0 | case MVT::v4i32: return fastEmit_ISD_ABDU_MVT_v4i32_rr(RetVT, Op0, Op1); |
2763 | 0 | default: return 0; |
2764 | 0 | } |
2765 | 0 | } |
2766 | | |
2767 | | // FastEmit functions for ISD::ADD. |
2768 | | |
2769 | 0 | unsigned fastEmit_ISD_ADD_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2770 | 0 | if (RetVT.SimpleTy != MVT::i1) |
2771 | 0 | return 0; |
2772 | 0 | return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op1); |
2773 | 0 | } |
2774 | | |
2775 | 0 | unsigned fastEmit_ISD_ADD_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2776 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2777 | 0 | return 0; |
2778 | 0 | return fastEmitInst_rr(PPC::ADD4, &PPC::GPRCRegClass, Op0, Op1); |
2779 | 0 | } |
2780 | | |
2781 | 0 | unsigned fastEmit_ISD_ADD_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2782 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2783 | 0 | return 0; |
2784 | 0 | return fastEmitInst_rr(PPC::ADD8, &PPC::G8RCRegClass, Op0, Op1); |
2785 | 0 | } |
2786 | | |
2787 | 0 | unsigned fastEmit_ISD_ADD_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2788 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
2789 | 0 | return 0; |
2790 | 0 | if ((Subtarget->hasAltivec())) { |
2791 | 0 | return fastEmitInst_rr(PPC::VADDUBM, &PPC::VRRCRegClass, Op0, Op1); |
2792 | 0 | } |
2793 | 0 | return 0; |
2794 | 0 | } |
2795 | | |
2796 | 0 | unsigned fastEmit_ISD_ADD_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2797 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
2798 | 0 | return 0; |
2799 | 0 | if ((Subtarget->hasAltivec())) { |
2800 | 0 | return fastEmitInst_rr(PPC::VADDUHM, &PPC::VRRCRegClass, Op0, Op1); |
2801 | 0 | } |
2802 | 0 | return 0; |
2803 | 0 | } |
2804 | | |
2805 | 0 | unsigned fastEmit_ISD_ADD_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2806 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2807 | 0 | return 0; |
2808 | 0 | if ((Subtarget->hasAltivec())) { |
2809 | 0 | return fastEmitInst_rr(PPC::VADDUWM, &PPC::VRRCRegClass, Op0, Op1); |
2810 | 0 | } |
2811 | 0 | return 0; |
2812 | 0 | } |
2813 | | |
2814 | 0 | unsigned fastEmit_ISD_ADD_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2815 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2816 | 0 | return 0; |
2817 | 0 | if ((Subtarget->hasP8Altivec())) { |
2818 | 0 | return fastEmitInst_rr(PPC::VADDUDM, &PPC::VRRCRegClass, Op0, Op1); |
2819 | 0 | } |
2820 | 0 | return 0; |
2821 | 0 | } |
2822 | | |
2823 | 0 | unsigned fastEmit_ISD_ADD_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2824 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
2825 | 0 | return 0; |
2826 | 0 | if ((Subtarget->hasP8Altivec())) { |
2827 | 0 | return fastEmitInst_rr(PPC::VADDUQM, &PPC::VRRCRegClass, Op0, Op1); |
2828 | 0 | } |
2829 | 0 | return 0; |
2830 | 0 | } |
2831 | | |
2832 | 0 | unsigned fastEmit_ISD_ADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
2833 | 0 | switch (VT.SimpleTy) { |
2834 | 0 | case MVT::i1: return fastEmit_ISD_ADD_MVT_i1_rr(RetVT, Op0, Op1); |
2835 | 0 | case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_rr(RetVT, Op0, Op1); |
2836 | 0 | case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_rr(RetVT, Op0, Op1); |
2837 | 0 | case MVT::v16i8: return fastEmit_ISD_ADD_MVT_v16i8_rr(RetVT, Op0, Op1); |
2838 | 0 | case MVT::v8i16: return fastEmit_ISD_ADD_MVT_v8i16_rr(RetVT, Op0, Op1); |
2839 | 0 | case MVT::v4i32: return fastEmit_ISD_ADD_MVT_v4i32_rr(RetVT, Op0, Op1); |
2840 | 0 | case MVT::v2i64: return fastEmit_ISD_ADD_MVT_v2i64_rr(RetVT, Op0, Op1); |
2841 | 0 | case MVT::v1i128: return fastEmit_ISD_ADD_MVT_v1i128_rr(RetVT, Op0, Op1); |
2842 | 0 | default: return 0; |
2843 | 0 | } |
2844 | 0 | } |
2845 | | |
2846 | | // FastEmit functions for ISD::ADDC. |
2847 | | |
2848 | 0 | unsigned fastEmit_ISD_ADDC_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2849 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2850 | 0 | return 0; |
2851 | 0 | return fastEmitInst_rr(PPC::ADDC, &PPC::GPRCRegClass, Op0, Op1); |
2852 | 0 | } |
2853 | | |
2854 | 0 | unsigned fastEmit_ISD_ADDC_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2855 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2856 | 0 | return 0; |
2857 | 0 | return fastEmitInst_rr(PPC::ADDC8, &PPC::G8RCRegClass, Op0, Op1); |
2858 | 0 | } |
2859 | | |
2860 | 0 | unsigned fastEmit_ISD_ADDC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
2861 | 0 | switch (VT.SimpleTy) { |
2862 | 0 | case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_rr(RetVT, Op0, Op1); |
2863 | 0 | case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_rr(RetVT, Op0, Op1); |
2864 | 0 | default: return 0; |
2865 | 0 | } |
2866 | 0 | } |
2867 | | |
2868 | | // FastEmit functions for ISD::ADDE. |
2869 | | |
2870 | 0 | unsigned fastEmit_ISD_ADDE_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2871 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2872 | 0 | return 0; |
2873 | 0 | return fastEmitInst_rr(PPC::ADDE, &PPC::GPRCRegClass, Op0, Op1); |
2874 | 0 | } |
2875 | | |
2876 | 0 | unsigned fastEmit_ISD_ADDE_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2877 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2878 | 0 | return 0; |
2879 | 0 | return fastEmitInst_rr(PPC::ADDE8, &PPC::G8RCRegClass, Op0, Op1); |
2880 | 0 | } |
2881 | | |
2882 | 0 | unsigned fastEmit_ISD_ADDE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
2883 | 0 | switch (VT.SimpleTy) { |
2884 | 0 | case MVT::i32: return fastEmit_ISD_ADDE_MVT_i32_rr(RetVT, Op0, Op1); |
2885 | 0 | case MVT::i64: return fastEmit_ISD_ADDE_MVT_i64_rr(RetVT, Op0, Op1); |
2886 | 0 | default: return 0; |
2887 | 0 | } |
2888 | 0 | } |
2889 | | |
2890 | | // FastEmit functions for ISD::AND. |
2891 | | |
2892 | 0 | unsigned fastEmit_ISD_AND_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2893 | 0 | if (RetVT.SimpleTy != MVT::i1) |
2894 | 0 | return 0; |
2895 | 0 | return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op1); |
2896 | 0 | } |
2897 | | |
2898 | 0 | unsigned fastEmit_ISD_AND_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2899 | 0 | if (RetVT.SimpleTy != MVT::i32) |
2900 | 0 | return 0; |
2901 | 0 | return fastEmitInst_rr(PPC::AND, &PPC::GPRCRegClass, Op0, Op1); |
2902 | 0 | } |
2903 | | |
2904 | 0 | unsigned fastEmit_ISD_AND_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2905 | 0 | if (RetVT.SimpleTy != MVT::i64) |
2906 | 0 | return 0; |
2907 | 0 | return fastEmitInst_rr(PPC::AND8, &PPC::G8RCRegClass, Op0, Op1); |
2908 | 0 | } |
2909 | | |
2910 | 0 | unsigned fastEmit_ISD_AND_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2911 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
2912 | 0 | return 0; |
2913 | 0 | if ((Subtarget->hasVSX())) { |
2914 | 0 | return fastEmitInst_rr(PPC::XXLAND, &PPC::VSRCRegClass, Op0, Op1); |
2915 | 0 | } |
2916 | 0 | if ((Subtarget->hasAltivec())) { |
2917 | 0 | return fastEmitInst_rr(PPC::VAND, &PPC::VRRCRegClass, Op0, Op1); |
2918 | 0 | } |
2919 | 0 | return 0; |
2920 | 0 | } |
2921 | | |
2922 | 0 | unsigned fastEmit_ISD_AND_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
2923 | 0 | switch (VT.SimpleTy) { |
2924 | 0 | case MVT::i1: return fastEmit_ISD_AND_MVT_i1_rr(RetVT, Op0, Op1); |
2925 | 0 | case MVT::i32: return fastEmit_ISD_AND_MVT_i32_rr(RetVT, Op0, Op1); |
2926 | 0 | case MVT::i64: return fastEmit_ISD_AND_MVT_i64_rr(RetVT, Op0, Op1); |
2927 | 0 | case MVT::v4i32: return fastEmit_ISD_AND_MVT_v4i32_rr(RetVT, Op0, Op1); |
2928 | 0 | default: return 0; |
2929 | 0 | } |
2930 | 0 | } |
2931 | | |
2932 | | // FastEmit functions for ISD::BUILD_VECTOR. |
2933 | | |
2934 | 0 | unsigned fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2935 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
2936 | 0 | return 0; |
2937 | 0 | if ((Subtarget->hasDirectMove()) && (Subtarget->hasVSX()) && (!Subtarget->isLittleEndian()) && (Subtarget->isISA3_0()) && (Subtarget->isPPC64())) { |
2938 | 0 | return fastEmitInst_rr(PPC::MTVSRDD, &PPC::VSRCRegClass, Op0, Op1); |
2939 | 0 | } |
2940 | 0 | return 0; |
2941 | 0 | } |
2942 | | |
2943 | 0 | unsigned fastEmit_ISD_BUILD_VECTOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
2944 | 0 | switch (VT.SimpleTy) { |
2945 | 0 | case MVT::i64: return fastEmit_ISD_BUILD_VECTOR_MVT_i64_rr(RetVT, Op0, Op1); |
2946 | 0 | default: return 0; |
2947 | 0 | } |
2948 | 0 | } |
2949 | | |
2950 | | // FastEmit functions for ISD::FADD. |
2951 | | |
2952 | 0 | unsigned fastEmit_ISD_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2953 | 0 | if (RetVT.SimpleTy != MVT::f32) |
2954 | 0 | return 0; |
2955 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
2956 | 0 | return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op1); |
2957 | 0 | } |
2958 | 0 | if ((Subtarget->hasSPE())) { |
2959 | 0 | return fastEmitInst_rr(PPC::EFSADD, &PPC::GPRCRegClass, Op0, Op1); |
2960 | 0 | } |
2961 | 0 | if ((Subtarget->hasFPU())) { |
2962 | 0 | return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op1); |
2963 | 0 | } |
2964 | 0 | return 0; |
2965 | 0 | } |
2966 | | |
2967 | 0 | unsigned fastEmit_ISD_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2968 | 0 | if (RetVT.SimpleTy != MVT::f64) |
2969 | 0 | return 0; |
2970 | 0 | if ((Subtarget->hasVSX())) { |
2971 | 0 | return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op1); |
2972 | 0 | } |
2973 | 0 | if ((Subtarget->hasSPE())) { |
2974 | 0 | return fastEmitInst_rr(PPC::EFDADD, &PPC::SPERCRegClass, Op0, Op1); |
2975 | 0 | } |
2976 | 0 | if ((Subtarget->hasFPU())) { |
2977 | 0 | return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op1); |
2978 | 0 | } |
2979 | 0 | return 0; |
2980 | 0 | } |
2981 | | |
2982 | 0 | unsigned fastEmit_ISD_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2983 | 0 | if (RetVT.SimpleTy != MVT::f128) |
2984 | 0 | return 0; |
2985 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
2986 | 0 | return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op1); |
2987 | 0 | } |
2988 | 0 | return 0; |
2989 | 0 | } |
2990 | | |
2991 | 0 | unsigned fastEmit_ISD_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
2992 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
2993 | 0 | return 0; |
2994 | 0 | if ((Subtarget->hasVSX())) { |
2995 | 0 | return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op1); |
2996 | 0 | } |
2997 | 0 | if ((Subtarget->hasAltivec())) { |
2998 | 0 | return fastEmitInst_rr(PPC::VADDFP, &PPC::VRRCRegClass, Op0, Op1); |
2999 | 0 | } |
3000 | 0 | return 0; |
3001 | 0 | } |
3002 | | |
3003 | 0 | unsigned fastEmit_ISD_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3004 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3005 | 0 | return 0; |
3006 | 0 | if ((Subtarget->hasVSX())) { |
3007 | 0 | return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op1); |
3008 | 0 | } |
3009 | 0 | return 0; |
3010 | 0 | } |
3011 | | |
3012 | 0 | unsigned fastEmit_ISD_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3013 | 0 | switch (VT.SimpleTy) { |
3014 | 0 | case MVT::f32: return fastEmit_ISD_FADD_MVT_f32_rr(RetVT, Op0, Op1); |
3015 | 0 | case MVT::f64: return fastEmit_ISD_FADD_MVT_f64_rr(RetVT, Op0, Op1); |
3016 | 0 | case MVT::f128: return fastEmit_ISD_FADD_MVT_f128_rr(RetVT, Op0, Op1); |
3017 | 0 | case MVT::v4f32: return fastEmit_ISD_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); |
3018 | 0 | case MVT::v2f64: return fastEmit_ISD_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); |
3019 | 0 | default: return 0; |
3020 | 0 | } |
3021 | 0 | } |
3022 | | |
3023 | | // FastEmit functions for ISD::FDIV. |
3024 | | |
3025 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3026 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3027 | 0 | return 0; |
3028 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
3029 | 0 | return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op1); |
3030 | 0 | } |
3031 | 0 | if ((Subtarget->hasSPE())) { |
3032 | 0 | return fastEmitInst_rr(PPC::EFSDIV, &PPC::GPRCRegClass, Op0, Op1); |
3033 | 0 | } |
3034 | 0 | if ((Subtarget->hasFPU())) { |
3035 | 0 | return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op1); |
3036 | 0 | } |
3037 | 0 | return 0; |
3038 | 0 | } |
3039 | | |
3040 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3041 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3042 | 0 | return 0; |
3043 | 0 | if ((Subtarget->hasVSX())) { |
3044 | 0 | return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op1); |
3045 | 0 | } |
3046 | 0 | if ((Subtarget->hasSPE())) { |
3047 | 0 | return fastEmitInst_rr(PPC::EFDDIV, &PPC::SPERCRegClass, Op0, Op1); |
3048 | 0 | } |
3049 | 0 | if ((Subtarget->hasFPU())) { |
3050 | 0 | return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op1); |
3051 | 0 | } |
3052 | 0 | return 0; |
3053 | 0 | } |
3054 | | |
3055 | 0 | unsigned fastEmit_ISD_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3056 | 0 | if (RetVT.SimpleTy != MVT::f128) |
3057 | 0 | return 0; |
3058 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
3059 | 0 | return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op1); |
3060 | 0 | } |
3061 | 0 | return 0; |
3062 | 0 | } |
3063 | | |
3064 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3065 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3066 | 0 | return 0; |
3067 | 0 | if ((Subtarget->hasVSX())) { |
3068 | 0 | return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op1); |
3069 | 0 | } |
3070 | 0 | return 0; |
3071 | 0 | } |
3072 | | |
3073 | 0 | unsigned fastEmit_ISD_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3074 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3075 | 0 | return 0; |
3076 | 0 | if ((Subtarget->hasVSX())) { |
3077 | 0 | return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op1); |
3078 | 0 | } |
3079 | 0 | return 0; |
3080 | 0 | } |
3081 | | |
3082 | 0 | unsigned fastEmit_ISD_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3083 | 0 | switch (VT.SimpleTy) { |
3084 | 0 | case MVT::f32: return fastEmit_ISD_FDIV_MVT_f32_rr(RetVT, Op0, Op1); |
3085 | 0 | case MVT::f64: return fastEmit_ISD_FDIV_MVT_f64_rr(RetVT, Op0, Op1); |
3086 | 0 | case MVT::f128: return fastEmit_ISD_FDIV_MVT_f128_rr(RetVT, Op0, Op1); |
3087 | 0 | case MVT::v4f32: return fastEmit_ISD_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); |
3088 | 0 | case MVT::v2f64: return fastEmit_ISD_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); |
3089 | 0 | default: return 0; |
3090 | 0 | } |
3091 | 0 | } |
3092 | | |
3093 | | // FastEmit functions for ISD::FMAXNUM. |
3094 | | |
3095 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3096 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3097 | 0 | return 0; |
3098 | 0 | if ((Subtarget->hasVSX())) { |
3099 | 0 | return fastEmitInst_rr(PPC::XVMAXSP, &PPC::VSRCRegClass, Op0, Op1); |
3100 | 0 | } |
3101 | 0 | return 0; |
3102 | 0 | } |
3103 | | |
3104 | 0 | unsigned fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3105 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3106 | 0 | return 0; |
3107 | 0 | if ((Subtarget->hasVSX())) { |
3108 | 0 | return fastEmitInst_rr(PPC::XVMAXDP, &PPC::VSRCRegClass, Op0, Op1); |
3109 | 0 | } |
3110 | 0 | return 0; |
3111 | 0 | } |
3112 | | |
3113 | 0 | unsigned fastEmit_ISD_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3114 | 0 | switch (VT.SimpleTy) { |
3115 | 0 | case MVT::v4f32: return fastEmit_ISD_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
3116 | 0 | case MVT::v2f64: return fastEmit_ISD_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
3117 | 0 | default: return 0; |
3118 | 0 | } |
3119 | 0 | } |
3120 | | |
3121 | | // FastEmit functions for ISD::FMAXNUM_IEEE. |
3122 | | |
3123 | 0 | unsigned fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3124 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3125 | 0 | return 0; |
3126 | 0 | if ((Subtarget->hasVSX())) { |
3127 | 0 | return fastEmitInst_rr(PPC::XSMAXDP, &PPC::VSFRCRegClass, Op0, Op1); |
3128 | 0 | } |
3129 | 0 | return 0; |
3130 | 0 | } |
3131 | | |
3132 | 0 | unsigned fastEmit_ISD_FMAXNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3133 | 0 | switch (VT.SimpleTy) { |
3134 | 0 | case MVT::f64: return fastEmit_ISD_FMAXNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1); |
3135 | 0 | default: return 0; |
3136 | 0 | } |
3137 | 0 | } |
3138 | | |
3139 | | // FastEmit functions for ISD::FMINNUM. |
3140 | | |
3141 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3142 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3143 | 0 | return 0; |
3144 | 0 | if ((Subtarget->hasVSX())) { |
3145 | 0 | return fastEmitInst_rr(PPC::XVMINSP, &PPC::VSRCRegClass, Op0, Op1); |
3146 | 0 | } |
3147 | 0 | return 0; |
3148 | 0 | } |
3149 | | |
3150 | 0 | unsigned fastEmit_ISD_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3151 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3152 | 0 | return 0; |
3153 | 0 | if ((Subtarget->hasVSX())) { |
3154 | 0 | return fastEmitInst_rr(PPC::XVMINDP, &PPC::VSRCRegClass, Op0, Op1); |
3155 | 0 | } |
3156 | 0 | return 0; |
3157 | 0 | } |
3158 | | |
3159 | 0 | unsigned fastEmit_ISD_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3160 | 0 | switch (VT.SimpleTy) { |
3161 | 0 | case MVT::v4f32: return fastEmit_ISD_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
3162 | 0 | case MVT::v2f64: return fastEmit_ISD_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
3163 | 0 | default: return 0; |
3164 | 0 | } |
3165 | 0 | } |
3166 | | |
3167 | | // FastEmit functions for ISD::FMINNUM_IEEE. |
3168 | | |
3169 | 0 | unsigned fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3170 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3171 | 0 | return 0; |
3172 | 0 | if ((Subtarget->hasVSX())) { |
3173 | 0 | return fastEmitInst_rr(PPC::XSMINDP, &PPC::VSFRCRegClass, Op0, Op1); |
3174 | 0 | } |
3175 | 0 | return 0; |
3176 | 0 | } |
3177 | | |
3178 | 0 | unsigned fastEmit_ISD_FMINNUM_IEEE_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3179 | 0 | switch (VT.SimpleTy) { |
3180 | 0 | case MVT::f64: return fastEmit_ISD_FMINNUM_IEEE_MVT_f64_rr(RetVT, Op0, Op1); |
3181 | 0 | default: return 0; |
3182 | 0 | } |
3183 | 0 | } |
3184 | | |
3185 | | // FastEmit functions for ISD::FMUL. |
3186 | | |
3187 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3188 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3189 | 0 | return 0; |
3190 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
3191 | 0 | return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op1); |
3192 | 0 | } |
3193 | 0 | if ((Subtarget->hasSPE())) { |
3194 | 0 | return fastEmitInst_rr(PPC::EFSMUL, &PPC::GPRCRegClass, Op0, Op1); |
3195 | 0 | } |
3196 | 0 | if ((Subtarget->hasFPU())) { |
3197 | 0 | return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op1); |
3198 | 0 | } |
3199 | 0 | return 0; |
3200 | 0 | } |
3201 | | |
3202 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3203 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3204 | 0 | return 0; |
3205 | 0 | if ((Subtarget->hasVSX())) { |
3206 | 0 | return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op1); |
3207 | 0 | } |
3208 | 0 | if ((Subtarget->hasSPE())) { |
3209 | 0 | return fastEmitInst_rr(PPC::EFDMUL, &PPC::SPERCRegClass, Op0, Op1); |
3210 | 0 | } |
3211 | 0 | if ((Subtarget->hasFPU())) { |
3212 | 0 | return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op1); |
3213 | 0 | } |
3214 | 0 | return 0; |
3215 | 0 | } |
3216 | | |
3217 | 0 | unsigned fastEmit_ISD_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3218 | 0 | if (RetVT.SimpleTy != MVT::f128) |
3219 | 0 | return 0; |
3220 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
3221 | 0 | return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op1); |
3222 | 0 | } |
3223 | 0 | return 0; |
3224 | 0 | } |
3225 | | |
3226 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3227 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3228 | 0 | return 0; |
3229 | 0 | if ((Subtarget->hasVSX())) { |
3230 | 0 | return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op1); |
3231 | 0 | } |
3232 | 0 | return 0; |
3233 | 0 | } |
3234 | | |
3235 | 0 | unsigned fastEmit_ISD_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3236 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3237 | 0 | return 0; |
3238 | 0 | if ((Subtarget->hasVSX())) { |
3239 | 0 | return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op1); |
3240 | 0 | } |
3241 | 0 | return 0; |
3242 | 0 | } |
3243 | | |
3244 | 0 | unsigned fastEmit_ISD_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3245 | 0 | switch (VT.SimpleTy) { |
3246 | 0 | case MVT::f32: return fastEmit_ISD_FMUL_MVT_f32_rr(RetVT, Op0, Op1); |
3247 | 0 | case MVT::f64: return fastEmit_ISD_FMUL_MVT_f64_rr(RetVT, Op0, Op1); |
3248 | 0 | case MVT::f128: return fastEmit_ISD_FMUL_MVT_f128_rr(RetVT, Op0, Op1); |
3249 | 0 | case MVT::v4f32: return fastEmit_ISD_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); |
3250 | 0 | case MVT::v2f64: return fastEmit_ISD_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); |
3251 | 0 | default: return 0; |
3252 | 0 | } |
3253 | 0 | } |
3254 | | |
3255 | | // FastEmit functions for ISD::FSUB. |
3256 | | |
3257 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3258 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3259 | 0 | return 0; |
3260 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
3261 | 0 | return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op1); |
3262 | 0 | } |
3263 | 0 | if ((Subtarget->hasSPE())) { |
3264 | 0 | return fastEmitInst_rr(PPC::EFSSUB, &PPC::GPRCRegClass, Op0, Op1); |
3265 | 0 | } |
3266 | 0 | if ((Subtarget->hasFPU())) { |
3267 | 0 | return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op1); |
3268 | 0 | } |
3269 | 0 | return 0; |
3270 | 0 | } |
3271 | | |
3272 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3273 | 0 | if (RetVT.SimpleTy != MVT::f64) |
3274 | 0 | return 0; |
3275 | 0 | if ((Subtarget->hasVSX())) { |
3276 | 0 | return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op1); |
3277 | 0 | } |
3278 | 0 | if ((Subtarget->hasSPE())) { |
3279 | 0 | return fastEmitInst_rr(PPC::EFDSUB, &PPC::SPERCRegClass, Op0, Op1); |
3280 | 0 | } |
3281 | 0 | if ((Subtarget->hasFPU())) { |
3282 | 0 | return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op1); |
3283 | 0 | } |
3284 | 0 | return 0; |
3285 | 0 | } |
3286 | | |
3287 | 0 | unsigned fastEmit_ISD_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3288 | 0 | if (RetVT.SimpleTy != MVT::f128) |
3289 | 0 | return 0; |
3290 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
3291 | 0 | return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op1); |
3292 | 0 | } |
3293 | 0 | return 0; |
3294 | 0 | } |
3295 | | |
3296 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3297 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
3298 | 0 | return 0; |
3299 | 0 | if ((Subtarget->hasVSX())) { |
3300 | 0 | return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op1); |
3301 | 0 | } |
3302 | 0 | if ((Subtarget->hasAltivec())) { |
3303 | 0 | return fastEmitInst_rr(PPC::VSUBFP, &PPC::VRRCRegClass, Op0, Op1); |
3304 | 0 | } |
3305 | 0 | return 0; |
3306 | 0 | } |
3307 | | |
3308 | 0 | unsigned fastEmit_ISD_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3309 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
3310 | 0 | return 0; |
3311 | 0 | if ((Subtarget->hasVSX())) { |
3312 | 0 | return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op1); |
3313 | 0 | } |
3314 | 0 | return 0; |
3315 | 0 | } |
3316 | | |
3317 | 0 | unsigned fastEmit_ISD_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3318 | 0 | switch (VT.SimpleTy) { |
3319 | 0 | case MVT::f32: return fastEmit_ISD_FSUB_MVT_f32_rr(RetVT, Op0, Op1); |
3320 | 0 | case MVT::f64: return fastEmit_ISD_FSUB_MVT_f64_rr(RetVT, Op0, Op1); |
3321 | 0 | case MVT::f128: return fastEmit_ISD_FSUB_MVT_f128_rr(RetVT, Op0, Op1); |
3322 | 0 | case MVT::v4f32: return fastEmit_ISD_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); |
3323 | 0 | case MVT::v2f64: return fastEmit_ISD_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); |
3324 | 0 | default: return 0; |
3325 | 0 | } |
3326 | 0 | } |
3327 | | |
3328 | | // FastEmit functions for ISD::MUL. |
3329 | | |
3330 | 0 | unsigned fastEmit_ISD_MUL_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3331 | 0 | if (RetVT.SimpleTy != MVT::i1) |
3332 | 0 | return 0; |
3333 | 0 | return fastEmitInst_rr(PPC::CRAND, &PPC::CRBITRCRegClass, Op0, Op1); |
3334 | 0 | } |
3335 | | |
3336 | 0 | unsigned fastEmit_ISD_MUL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3337 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3338 | 0 | return 0; |
3339 | 0 | return fastEmitInst_rr(PPC::MULLW, &PPC::GPRCRegClass, Op0, Op1); |
3340 | 0 | } |
3341 | | |
3342 | 0 | unsigned fastEmit_ISD_MUL_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3343 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3344 | 0 | return 0; |
3345 | 0 | return fastEmitInst_rr(PPC::MULLD, &PPC::G8RCRegClass, Op0, Op1); |
3346 | 0 | } |
3347 | | |
3348 | 0 | unsigned fastEmit_ISD_MUL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3349 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3350 | 0 | return 0; |
3351 | 0 | if ((Subtarget->hasP8Altivec())) { |
3352 | 0 | return fastEmitInst_rr(PPC::VMULUWM, &PPC::VRRCRegClass, Op0, Op1); |
3353 | 0 | } |
3354 | 0 | return 0; |
3355 | 0 | } |
3356 | | |
3357 | 0 | unsigned fastEmit_ISD_MUL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3358 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3359 | 0 | return 0; |
3360 | 0 | if ((Subtarget->isISA3_1())) { |
3361 | 0 | return fastEmitInst_rr(PPC::VMULLD, &PPC::VRRCRegClass, Op0, Op1); |
3362 | 0 | } |
3363 | 0 | return 0; |
3364 | 0 | } |
3365 | | |
3366 | 0 | unsigned fastEmit_ISD_MUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3367 | 0 | switch (VT.SimpleTy) { |
3368 | 0 | case MVT::i1: return fastEmit_ISD_MUL_MVT_i1_rr(RetVT, Op0, Op1); |
3369 | 0 | case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_rr(RetVT, Op0, Op1); |
3370 | 0 | case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_rr(RetVT, Op0, Op1); |
3371 | 0 | case MVT::v4i32: return fastEmit_ISD_MUL_MVT_v4i32_rr(RetVT, Op0, Op1); |
3372 | 0 | case MVT::v2i64: return fastEmit_ISD_MUL_MVT_v2i64_rr(RetVT, Op0, Op1); |
3373 | 0 | default: return 0; |
3374 | 0 | } |
3375 | 0 | } |
3376 | | |
3377 | | // FastEmit functions for ISD::MULHS. |
3378 | | |
3379 | 0 | unsigned fastEmit_ISD_MULHS_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3380 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3381 | 0 | return 0; |
3382 | 0 | return fastEmitInst_rr(PPC::MULHW, &PPC::GPRCRegClass, Op0, Op1); |
3383 | 0 | } |
3384 | | |
3385 | 0 | unsigned fastEmit_ISD_MULHS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3386 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3387 | 0 | return 0; |
3388 | 0 | return fastEmitInst_rr(PPC::MULHD, &PPC::G8RCRegClass, Op0, Op1); |
3389 | 0 | } |
3390 | | |
3391 | 0 | unsigned fastEmit_ISD_MULHS_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3392 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3393 | 0 | return 0; |
3394 | 0 | if ((Subtarget->isISA3_1())) { |
3395 | 0 | return fastEmitInst_rr(PPC::VMULHSW, &PPC::VRRCRegClass, Op0, Op1); |
3396 | 0 | } |
3397 | 0 | return 0; |
3398 | 0 | } |
3399 | | |
3400 | 0 | unsigned fastEmit_ISD_MULHS_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3401 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3402 | 0 | return 0; |
3403 | 0 | if ((Subtarget->isISA3_1())) { |
3404 | 0 | return fastEmitInst_rr(PPC::VMULHSD, &PPC::VRRCRegClass, Op0, Op1); |
3405 | 0 | } |
3406 | 0 | return 0; |
3407 | 0 | } |
3408 | | |
3409 | 0 | unsigned fastEmit_ISD_MULHS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3410 | 0 | switch (VT.SimpleTy) { |
3411 | 0 | case MVT::i32: return fastEmit_ISD_MULHS_MVT_i32_rr(RetVT, Op0, Op1); |
3412 | 0 | case MVT::i64: return fastEmit_ISD_MULHS_MVT_i64_rr(RetVT, Op0, Op1); |
3413 | 0 | case MVT::v4i32: return fastEmit_ISD_MULHS_MVT_v4i32_rr(RetVT, Op0, Op1); |
3414 | 0 | case MVT::v2i64: return fastEmit_ISD_MULHS_MVT_v2i64_rr(RetVT, Op0, Op1); |
3415 | 0 | default: return 0; |
3416 | 0 | } |
3417 | 0 | } |
3418 | | |
3419 | | // FastEmit functions for ISD::MULHU. |
3420 | | |
3421 | 0 | unsigned fastEmit_ISD_MULHU_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3422 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3423 | 0 | return 0; |
3424 | 0 | return fastEmitInst_rr(PPC::MULHWU, &PPC::GPRCRegClass, Op0, Op1); |
3425 | 0 | } |
3426 | | |
3427 | 0 | unsigned fastEmit_ISD_MULHU_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3428 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3429 | 0 | return 0; |
3430 | 0 | return fastEmitInst_rr(PPC::MULHDU, &PPC::G8RCRegClass, Op0, Op1); |
3431 | 0 | } |
3432 | | |
3433 | 0 | unsigned fastEmit_ISD_MULHU_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3434 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3435 | 0 | return 0; |
3436 | 0 | if ((Subtarget->isISA3_1())) { |
3437 | 0 | return fastEmitInst_rr(PPC::VMULHUW, &PPC::VRRCRegClass, Op0, Op1); |
3438 | 0 | } |
3439 | 0 | return 0; |
3440 | 0 | } |
3441 | | |
3442 | 0 | unsigned fastEmit_ISD_MULHU_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3443 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3444 | 0 | return 0; |
3445 | 0 | if ((Subtarget->isISA3_1())) { |
3446 | 0 | return fastEmitInst_rr(PPC::VMULHUD, &PPC::VRRCRegClass, Op0, Op1); |
3447 | 0 | } |
3448 | 0 | return 0; |
3449 | 0 | } |
3450 | | |
3451 | 0 | unsigned fastEmit_ISD_MULHU_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3452 | 0 | switch (VT.SimpleTy) { |
3453 | 0 | case MVT::i32: return fastEmit_ISD_MULHU_MVT_i32_rr(RetVT, Op0, Op1); |
3454 | 0 | case MVT::i64: return fastEmit_ISD_MULHU_MVT_i64_rr(RetVT, Op0, Op1); |
3455 | 0 | case MVT::v4i32: return fastEmit_ISD_MULHU_MVT_v4i32_rr(RetVT, Op0, Op1); |
3456 | 0 | case MVT::v2i64: return fastEmit_ISD_MULHU_MVT_v2i64_rr(RetVT, Op0, Op1); |
3457 | 0 | default: return 0; |
3458 | 0 | } |
3459 | 0 | } |
3460 | | |
3461 | | // FastEmit functions for ISD::OR. |
3462 | | |
3463 | 0 | unsigned fastEmit_ISD_OR_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3464 | 0 | if (RetVT.SimpleTy != MVT::i1) |
3465 | 0 | return 0; |
3466 | 0 | return fastEmitInst_rr(PPC::CROR, &PPC::CRBITRCRegClass, Op0, Op1); |
3467 | 0 | } |
3468 | | |
3469 | 0 | unsigned fastEmit_ISD_OR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3470 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3471 | 0 | return 0; |
3472 | 0 | return fastEmitInst_rr(PPC::OR, &PPC::GPRCRegClass, Op0, Op1); |
3473 | 0 | } |
3474 | | |
3475 | 0 | unsigned fastEmit_ISD_OR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3476 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3477 | 0 | return 0; |
3478 | 0 | return fastEmitInst_rr(PPC::OR8, &PPC::G8RCRegClass, Op0, Op1); |
3479 | 0 | } |
3480 | | |
3481 | 0 | unsigned fastEmit_ISD_OR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3482 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3483 | 0 | return 0; |
3484 | 0 | if ((Subtarget->hasVSX())) { |
3485 | 0 | return fastEmitInst_rr(PPC::XXLOR, &PPC::VSRCRegClass, Op0, Op1); |
3486 | 0 | } |
3487 | 0 | if ((Subtarget->hasAltivec())) { |
3488 | 0 | return fastEmitInst_rr(PPC::VOR, &PPC::VRRCRegClass, Op0, Op1); |
3489 | 0 | } |
3490 | 0 | return 0; |
3491 | 0 | } |
3492 | | |
3493 | 0 | unsigned fastEmit_ISD_OR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3494 | 0 | switch (VT.SimpleTy) { |
3495 | 0 | case MVT::i1: return fastEmit_ISD_OR_MVT_i1_rr(RetVT, Op0, Op1); |
3496 | 0 | case MVT::i32: return fastEmit_ISD_OR_MVT_i32_rr(RetVT, Op0, Op1); |
3497 | 0 | case MVT::i64: return fastEmit_ISD_OR_MVT_i64_rr(RetVT, Op0, Op1); |
3498 | 0 | case MVT::v4i32: return fastEmit_ISD_OR_MVT_v4i32_rr(RetVT, Op0, Op1); |
3499 | 0 | default: return 0; |
3500 | 0 | } |
3501 | 0 | } |
3502 | | |
3503 | | // FastEmit functions for ISD::ROTL. |
3504 | | |
3505 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3506 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3507 | 0 | return 0; |
3508 | 0 | if ((Subtarget->hasAltivec())) { |
3509 | 0 | return fastEmitInst_rr(PPC::VRLB, &PPC::VRRCRegClass, Op0, Op1); |
3510 | 0 | } |
3511 | 0 | return 0; |
3512 | 0 | } |
3513 | | |
3514 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3515 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3516 | 0 | return 0; |
3517 | 0 | if ((Subtarget->hasAltivec())) { |
3518 | 0 | return fastEmitInst_rr(PPC::VRLH, &PPC::VRRCRegClass, Op0, Op1); |
3519 | 0 | } |
3520 | 0 | return 0; |
3521 | 0 | } |
3522 | | |
3523 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3524 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3525 | 0 | return 0; |
3526 | 0 | if ((Subtarget->hasAltivec())) { |
3527 | 0 | return fastEmitInst_rr(PPC::VRLW, &PPC::VRRCRegClass, Op0, Op1); |
3528 | 0 | } |
3529 | 0 | return 0; |
3530 | 0 | } |
3531 | | |
3532 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3533 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3534 | 0 | return 0; |
3535 | 0 | if ((Subtarget->hasP8Altivec())) { |
3536 | 0 | return fastEmitInst_rr(PPC::VRLD, &PPC::VRRCRegClass, Op0, Op1); |
3537 | 0 | } |
3538 | 0 | return 0; |
3539 | 0 | } |
3540 | | |
3541 | 0 | unsigned fastEmit_ISD_ROTL_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3542 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
3543 | 0 | return 0; |
3544 | 0 | if ((Subtarget->isISA3_1())) { |
3545 | 0 | return fastEmitInst_rr(PPC::VRLQ, &PPC::VRRCRegClass, Op0, Op1); |
3546 | 0 | } |
3547 | 0 | return 0; |
3548 | 0 | } |
3549 | | |
3550 | 0 | unsigned fastEmit_ISD_ROTL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3551 | 0 | switch (VT.SimpleTy) { |
3552 | 0 | case MVT::v16i8: return fastEmit_ISD_ROTL_MVT_v16i8_rr(RetVT, Op0, Op1); |
3553 | 0 | case MVT::v8i16: return fastEmit_ISD_ROTL_MVT_v8i16_rr(RetVT, Op0, Op1); |
3554 | 0 | case MVT::v4i32: return fastEmit_ISD_ROTL_MVT_v4i32_rr(RetVT, Op0, Op1); |
3555 | 0 | case MVT::v2i64: return fastEmit_ISD_ROTL_MVT_v2i64_rr(RetVT, Op0, Op1); |
3556 | 0 | case MVT::v1i128: return fastEmit_ISD_ROTL_MVT_v1i128_rr(RetVT, Op0, Op1); |
3557 | 0 | default: return 0; |
3558 | 0 | } |
3559 | 0 | } |
3560 | | |
3561 | | // FastEmit functions for ISD::SADDSAT. |
3562 | | |
3563 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3564 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3565 | 0 | return 0; |
3566 | 0 | if ((Subtarget->hasAltivec())) { |
3567 | 0 | return fastEmitInst_rr(PPC::VADDSBS, &PPC::VRRCRegClass, Op0, Op1); |
3568 | 0 | } |
3569 | 0 | return 0; |
3570 | 0 | } |
3571 | | |
3572 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3573 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3574 | 0 | return 0; |
3575 | 0 | if ((Subtarget->hasAltivec())) { |
3576 | 0 | return fastEmitInst_rr(PPC::VADDSHS, &PPC::VRRCRegClass, Op0, Op1); |
3577 | 0 | } |
3578 | 0 | return 0; |
3579 | 0 | } |
3580 | | |
3581 | 0 | unsigned fastEmit_ISD_SADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3582 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3583 | 0 | return 0; |
3584 | 0 | if ((Subtarget->hasAltivec())) { |
3585 | 0 | return fastEmitInst_rr(PPC::VADDSWS, &PPC::VRRCRegClass, Op0, Op1); |
3586 | 0 | } |
3587 | 0 | return 0; |
3588 | 0 | } |
3589 | | |
3590 | 0 | unsigned fastEmit_ISD_SADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3591 | 0 | switch (VT.SimpleTy) { |
3592 | 0 | case MVT::v16i8: return fastEmit_ISD_SADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
3593 | 0 | case MVT::v8i16: return fastEmit_ISD_SADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
3594 | 0 | case MVT::v4i32: return fastEmit_ISD_SADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
3595 | 0 | default: return 0; |
3596 | 0 | } |
3597 | 0 | } |
3598 | | |
3599 | | // FastEmit functions for ISD::SDIV. |
3600 | | |
3601 | 0 | unsigned fastEmit_ISD_SDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3602 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3603 | 0 | return 0; |
3604 | 0 | return fastEmitInst_rr(PPC::DIVW, &PPC::GPRCRegClass, Op0, Op1); |
3605 | 0 | } |
3606 | | |
3607 | 0 | unsigned fastEmit_ISD_SDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3608 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3609 | 0 | return 0; |
3610 | 0 | return fastEmitInst_rr(PPC::DIVD, &PPC::G8RCRegClass, Op0, Op1); |
3611 | 0 | } |
3612 | | |
3613 | 0 | unsigned fastEmit_ISD_SDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3614 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3615 | 0 | return 0; |
3616 | 0 | if ((Subtarget->isISA3_1())) { |
3617 | 0 | return fastEmitInst_rr(PPC::VDIVSW, &PPC::VRRCRegClass, Op0, Op1); |
3618 | 0 | } |
3619 | 0 | return 0; |
3620 | 0 | } |
3621 | | |
3622 | 0 | unsigned fastEmit_ISD_SDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3623 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3624 | 0 | return 0; |
3625 | 0 | if ((Subtarget->isISA3_1())) { |
3626 | 0 | return fastEmitInst_rr(PPC::VDIVSD, &PPC::VRRCRegClass, Op0, Op1); |
3627 | 0 | } |
3628 | 0 | return 0; |
3629 | 0 | } |
3630 | | |
3631 | 0 | unsigned fastEmit_ISD_SDIV_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3632 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
3633 | 0 | return 0; |
3634 | 0 | if ((Subtarget->isISA3_1())) { |
3635 | 0 | return fastEmitInst_rr(PPC::VDIVSQ, &PPC::VRRCRegClass, Op0, Op1); |
3636 | 0 | } |
3637 | 0 | return 0; |
3638 | 0 | } |
3639 | | |
3640 | 0 | unsigned fastEmit_ISD_SDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3641 | 0 | switch (VT.SimpleTy) { |
3642 | 0 | case MVT::i32: return fastEmit_ISD_SDIV_MVT_i32_rr(RetVT, Op0, Op1); |
3643 | 0 | case MVT::i64: return fastEmit_ISD_SDIV_MVT_i64_rr(RetVT, Op0, Op1); |
3644 | 0 | case MVT::v4i32: return fastEmit_ISD_SDIV_MVT_v4i32_rr(RetVT, Op0, Op1); |
3645 | 0 | case MVT::v2i64: return fastEmit_ISD_SDIV_MVT_v2i64_rr(RetVT, Op0, Op1); |
3646 | 0 | case MVT::v1i128: return fastEmit_ISD_SDIV_MVT_v1i128_rr(RetVT, Op0, Op1); |
3647 | 0 | default: return 0; |
3648 | 0 | } |
3649 | 0 | } |
3650 | | |
3651 | | // FastEmit functions for ISD::SHL. |
3652 | | |
3653 | 0 | unsigned fastEmit_ISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3654 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3655 | 0 | return 0; |
3656 | 0 | return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op1); |
3657 | 0 | } |
3658 | | |
3659 | 0 | unsigned fastEmit_ISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3660 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3661 | 0 | return 0; |
3662 | 0 | if ((Subtarget->hasAltivec())) { |
3663 | 0 | return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op1); |
3664 | 0 | } |
3665 | 0 | return 0; |
3666 | 0 | } |
3667 | | |
3668 | 0 | unsigned fastEmit_ISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3669 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3670 | 0 | return 0; |
3671 | 0 | if ((Subtarget->hasAltivec())) { |
3672 | 0 | return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op1); |
3673 | 0 | } |
3674 | 0 | return 0; |
3675 | 0 | } |
3676 | | |
3677 | 0 | unsigned fastEmit_ISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3678 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3679 | 0 | return 0; |
3680 | 0 | if ((Subtarget->hasAltivec())) { |
3681 | 0 | return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op1); |
3682 | 0 | } |
3683 | 0 | return 0; |
3684 | 0 | } |
3685 | | |
3686 | 0 | unsigned fastEmit_ISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3687 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3688 | 0 | return 0; |
3689 | 0 | if ((Subtarget->hasP8Altivec())) { |
3690 | 0 | return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op1); |
3691 | 0 | } |
3692 | 0 | return 0; |
3693 | 0 | } |
3694 | | |
3695 | 0 | unsigned fastEmit_ISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3696 | 0 | switch (VT.SimpleTy) { |
3697 | 0 | case MVT::i32: return fastEmit_ISD_SHL_MVT_i32_rr(RetVT, Op0, Op1); |
3698 | 0 | case MVT::v16i8: return fastEmit_ISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1); |
3699 | 0 | case MVT::v8i16: return fastEmit_ISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1); |
3700 | 0 | case MVT::v4i32: return fastEmit_ISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1); |
3701 | 0 | case MVT::v2i64: return fastEmit_ISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1); |
3702 | 0 | default: return 0; |
3703 | 0 | } |
3704 | 0 | } |
3705 | | |
3706 | | // FastEmit functions for ISD::SMAX. |
3707 | | |
3708 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3709 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3710 | 0 | return 0; |
3711 | 0 | if ((Subtarget->hasAltivec())) { |
3712 | 0 | return fastEmitInst_rr(PPC::VMAXSB, &PPC::VRRCRegClass, Op0, Op1); |
3713 | 0 | } |
3714 | 0 | return 0; |
3715 | 0 | } |
3716 | | |
3717 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3718 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3719 | 0 | return 0; |
3720 | 0 | if ((Subtarget->hasAltivec())) { |
3721 | 0 | return fastEmitInst_rr(PPC::VMAXSH, &PPC::VRRCRegClass, Op0, Op1); |
3722 | 0 | } |
3723 | 0 | return 0; |
3724 | 0 | } |
3725 | | |
3726 | 0 | unsigned fastEmit_ISD_SMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3727 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3728 | 0 | return 0; |
3729 | 0 | if ((Subtarget->hasAltivec())) { |
3730 | 0 | return fastEmitInst_rr(PPC::VMAXSW, &PPC::VRRCRegClass, Op0, Op1); |
3731 | 0 | } |
3732 | 0 | return 0; |
3733 | 0 | } |
3734 | | |
3735 | 0 | unsigned fastEmit_ISD_SMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3736 | 0 | switch (VT.SimpleTy) { |
3737 | 0 | case MVT::v16i8: return fastEmit_ISD_SMAX_MVT_v16i8_rr(RetVT, Op0, Op1); |
3738 | 0 | case MVT::v8i16: return fastEmit_ISD_SMAX_MVT_v8i16_rr(RetVT, Op0, Op1); |
3739 | 0 | case MVT::v4i32: return fastEmit_ISD_SMAX_MVT_v4i32_rr(RetVT, Op0, Op1); |
3740 | 0 | default: return 0; |
3741 | 0 | } |
3742 | 0 | } |
3743 | | |
3744 | | // FastEmit functions for ISD::SMIN. |
3745 | | |
3746 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3747 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3748 | 0 | return 0; |
3749 | 0 | if ((Subtarget->hasAltivec())) { |
3750 | 0 | return fastEmitInst_rr(PPC::VMINSB, &PPC::VRRCRegClass, Op0, Op1); |
3751 | 0 | } |
3752 | 0 | return 0; |
3753 | 0 | } |
3754 | | |
3755 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3756 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3757 | 0 | return 0; |
3758 | 0 | if ((Subtarget->hasAltivec())) { |
3759 | 0 | return fastEmitInst_rr(PPC::VMINSH, &PPC::VRRCRegClass, Op0, Op1); |
3760 | 0 | } |
3761 | 0 | return 0; |
3762 | 0 | } |
3763 | | |
3764 | 0 | unsigned fastEmit_ISD_SMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3765 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3766 | 0 | return 0; |
3767 | 0 | if ((Subtarget->hasAltivec())) { |
3768 | 0 | return fastEmitInst_rr(PPC::VMINSW, &PPC::VRRCRegClass, Op0, Op1); |
3769 | 0 | } |
3770 | 0 | return 0; |
3771 | 0 | } |
3772 | | |
3773 | 0 | unsigned fastEmit_ISD_SMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3774 | 0 | switch (VT.SimpleTy) { |
3775 | 0 | case MVT::v16i8: return fastEmit_ISD_SMIN_MVT_v16i8_rr(RetVT, Op0, Op1); |
3776 | 0 | case MVT::v8i16: return fastEmit_ISD_SMIN_MVT_v8i16_rr(RetVT, Op0, Op1); |
3777 | 0 | case MVT::v4i32: return fastEmit_ISD_SMIN_MVT_v4i32_rr(RetVT, Op0, Op1); |
3778 | 0 | default: return 0; |
3779 | 0 | } |
3780 | 0 | } |
3781 | | |
3782 | | // FastEmit functions for ISD::SRA. |
3783 | | |
3784 | 0 | unsigned fastEmit_ISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3785 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3786 | 0 | return 0; |
3787 | 0 | return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op1); |
3788 | 0 | } |
3789 | | |
3790 | 0 | unsigned fastEmit_ISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3791 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3792 | 0 | return 0; |
3793 | 0 | if ((Subtarget->hasAltivec())) { |
3794 | 0 | return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op1); |
3795 | 0 | } |
3796 | 0 | return 0; |
3797 | 0 | } |
3798 | | |
3799 | 0 | unsigned fastEmit_ISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3800 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3801 | 0 | return 0; |
3802 | 0 | if ((Subtarget->hasAltivec())) { |
3803 | 0 | return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op1); |
3804 | 0 | } |
3805 | 0 | return 0; |
3806 | 0 | } |
3807 | | |
3808 | 0 | unsigned fastEmit_ISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3809 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3810 | 0 | return 0; |
3811 | 0 | if ((Subtarget->hasAltivec())) { |
3812 | 0 | return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op1); |
3813 | 0 | } |
3814 | 0 | return 0; |
3815 | 0 | } |
3816 | | |
3817 | 0 | unsigned fastEmit_ISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3818 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3819 | 0 | return 0; |
3820 | 0 | if ((Subtarget->hasP8Altivec())) { |
3821 | 0 | return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op1); |
3822 | 0 | } |
3823 | 0 | return 0; |
3824 | 0 | } |
3825 | | |
3826 | 0 | unsigned fastEmit_ISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3827 | 0 | switch (VT.SimpleTy) { |
3828 | 0 | case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_rr(RetVT, Op0, Op1); |
3829 | 0 | case MVT::v16i8: return fastEmit_ISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1); |
3830 | 0 | case MVT::v8i16: return fastEmit_ISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1); |
3831 | 0 | case MVT::v4i32: return fastEmit_ISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1); |
3832 | 0 | case MVT::v2i64: return fastEmit_ISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1); |
3833 | 0 | default: return 0; |
3834 | 0 | } |
3835 | 0 | } |
3836 | | |
3837 | | // FastEmit functions for ISD::SREM. |
3838 | | |
3839 | 0 | unsigned fastEmit_ISD_SREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3840 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3841 | 0 | return 0; |
3842 | 0 | if ((Subtarget->isISA3_0())) { |
3843 | 0 | return fastEmitInst_rr(PPC::MODSW, &PPC::GPRCRegClass, Op0, Op1); |
3844 | 0 | } |
3845 | 0 | return 0; |
3846 | 0 | } |
3847 | | |
3848 | 0 | unsigned fastEmit_ISD_SREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3849 | 0 | if (RetVT.SimpleTy != MVT::i64) |
3850 | 0 | return 0; |
3851 | 0 | if ((Subtarget->isISA3_0())) { |
3852 | 0 | return fastEmitInst_rr(PPC::MODSD, &PPC::G8RCRegClass, Op0, Op1); |
3853 | 0 | } |
3854 | 0 | return 0; |
3855 | 0 | } |
3856 | | |
3857 | 0 | unsigned fastEmit_ISD_SREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3858 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3859 | 0 | return 0; |
3860 | 0 | if ((Subtarget->isISA3_1())) { |
3861 | 0 | return fastEmitInst_rr(PPC::VMODSW, &PPC::VRRCRegClass, Op0, Op1); |
3862 | 0 | } |
3863 | 0 | return 0; |
3864 | 0 | } |
3865 | | |
3866 | 0 | unsigned fastEmit_ISD_SREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3867 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3868 | 0 | return 0; |
3869 | 0 | if ((Subtarget->isISA3_1())) { |
3870 | 0 | return fastEmitInst_rr(PPC::VMODSD, &PPC::VRRCRegClass, Op0, Op1); |
3871 | 0 | } |
3872 | 0 | return 0; |
3873 | 0 | } |
3874 | | |
3875 | 0 | unsigned fastEmit_ISD_SREM_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3876 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
3877 | 0 | return 0; |
3878 | 0 | if ((Subtarget->isISA3_1())) { |
3879 | 0 | return fastEmitInst_rr(PPC::VMODSQ, &PPC::VRRCRegClass, Op0, Op1); |
3880 | 0 | } |
3881 | 0 | return 0; |
3882 | 0 | } |
3883 | | |
3884 | 0 | unsigned fastEmit_ISD_SREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3885 | 0 | switch (VT.SimpleTy) { |
3886 | 0 | case MVT::i32: return fastEmit_ISD_SREM_MVT_i32_rr(RetVT, Op0, Op1); |
3887 | 0 | case MVT::i64: return fastEmit_ISD_SREM_MVT_i64_rr(RetVT, Op0, Op1); |
3888 | 0 | case MVT::v4i32: return fastEmit_ISD_SREM_MVT_v4i32_rr(RetVT, Op0, Op1); |
3889 | 0 | case MVT::v2i64: return fastEmit_ISD_SREM_MVT_v2i64_rr(RetVT, Op0, Op1); |
3890 | 0 | case MVT::v1i128: return fastEmit_ISD_SREM_MVT_v1i128_rr(RetVT, Op0, Op1); |
3891 | 0 | default: return 0; |
3892 | 0 | } |
3893 | 0 | } |
3894 | | |
3895 | | // FastEmit functions for ISD::SRL. |
3896 | | |
3897 | 0 | unsigned fastEmit_ISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3898 | 0 | if (RetVT.SimpleTy != MVT::i32) |
3899 | 0 | return 0; |
3900 | 0 | return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op1); |
3901 | 0 | } |
3902 | | |
3903 | 0 | unsigned fastEmit_ISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3904 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3905 | 0 | return 0; |
3906 | 0 | if ((Subtarget->hasAltivec())) { |
3907 | 0 | return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op1); |
3908 | 0 | } |
3909 | 0 | return 0; |
3910 | 0 | } |
3911 | | |
3912 | 0 | unsigned fastEmit_ISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3913 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3914 | 0 | return 0; |
3915 | 0 | if ((Subtarget->hasAltivec())) { |
3916 | 0 | return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op1); |
3917 | 0 | } |
3918 | 0 | return 0; |
3919 | 0 | } |
3920 | | |
3921 | 0 | unsigned fastEmit_ISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3922 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3923 | 0 | return 0; |
3924 | 0 | if ((Subtarget->hasAltivec())) { |
3925 | 0 | return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op1); |
3926 | 0 | } |
3927 | 0 | return 0; |
3928 | 0 | } |
3929 | | |
3930 | 0 | unsigned fastEmit_ISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3931 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
3932 | 0 | return 0; |
3933 | 0 | if ((Subtarget->hasP8Altivec())) { |
3934 | 0 | return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op1); |
3935 | 0 | } |
3936 | 0 | return 0; |
3937 | 0 | } |
3938 | | |
3939 | 0 | unsigned fastEmit_ISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3940 | 0 | switch (VT.SimpleTy) { |
3941 | 0 | case MVT::i32: return fastEmit_ISD_SRL_MVT_i32_rr(RetVT, Op0, Op1); |
3942 | 0 | case MVT::v16i8: return fastEmit_ISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1); |
3943 | 0 | case MVT::v8i16: return fastEmit_ISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1); |
3944 | 0 | case MVT::v4i32: return fastEmit_ISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1); |
3945 | 0 | case MVT::v2i64: return fastEmit_ISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1); |
3946 | 0 | default: return 0; |
3947 | 0 | } |
3948 | 0 | } |
3949 | | |
3950 | | // FastEmit functions for ISD::SSUBSAT. |
3951 | | |
3952 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3953 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
3954 | 0 | return 0; |
3955 | 0 | if ((Subtarget->hasAltivec())) { |
3956 | 0 | return fastEmitInst_rr(PPC::VSUBSBS, &PPC::VRRCRegClass, Op0, Op1); |
3957 | 0 | } |
3958 | 0 | return 0; |
3959 | 0 | } |
3960 | | |
3961 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3962 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
3963 | 0 | return 0; |
3964 | 0 | if ((Subtarget->hasAltivec())) { |
3965 | 0 | return fastEmitInst_rr(PPC::VSUBSHS, &PPC::VRRCRegClass, Op0, Op1); |
3966 | 0 | } |
3967 | 0 | return 0; |
3968 | 0 | } |
3969 | | |
3970 | 0 | unsigned fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3971 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
3972 | 0 | return 0; |
3973 | 0 | if ((Subtarget->hasAltivec())) { |
3974 | 0 | return fastEmitInst_rr(PPC::VSUBSWS, &PPC::VRRCRegClass, Op0, Op1); |
3975 | 0 | } |
3976 | 0 | return 0; |
3977 | 0 | } |
3978 | | |
3979 | 0 | unsigned fastEmit_ISD_SSUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
3980 | 0 | switch (VT.SimpleTy) { |
3981 | 0 | case MVT::v16i8: return fastEmit_ISD_SSUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
3982 | 0 | case MVT::v8i16: return fastEmit_ISD_SSUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
3983 | 0 | case MVT::v4i32: return fastEmit_ISD_SSUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
3984 | 0 | default: return 0; |
3985 | 0 | } |
3986 | 0 | } |
3987 | | |
3988 | | // FastEmit functions for ISD::STRICT_FADD. |
3989 | | |
3990 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
3991 | 0 | if (RetVT.SimpleTy != MVT::f32) |
3992 | 0 | return 0; |
3993 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
3994 | 0 | return fastEmitInst_rr(PPC::XSADDSP, &PPC::VSSRCRegClass, Op0, Op1); |
3995 | 0 | } |
3996 | 0 | if ((Subtarget->hasSPE())) { |
3997 | 0 | return fastEmitInst_rr(PPC::EFSADD, &PPC::GPRCRegClass, Op0, Op1); |
3998 | 0 | } |
3999 | 0 | if ((Subtarget->hasFPU())) { |
4000 | 0 | return fastEmitInst_rr(PPC::FADDS, &PPC::F4RCRegClass, Op0, Op1); |
4001 | 0 | } |
4002 | 0 | return 0; |
4003 | 0 | } |
4004 | | |
4005 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4006 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4007 | 0 | return 0; |
4008 | 0 | if ((Subtarget->hasVSX())) { |
4009 | 0 | return fastEmitInst_rr(PPC::XSADDDP, &PPC::VSFRCRegClass, Op0, Op1); |
4010 | 0 | } |
4011 | 0 | if ((Subtarget->hasSPE())) { |
4012 | 0 | return fastEmitInst_rr(PPC::EFDADD, &PPC::SPERCRegClass, Op0, Op1); |
4013 | 0 | } |
4014 | 0 | if ((Subtarget->hasFPU())) { |
4015 | 0 | return fastEmitInst_rr(PPC::FADD, &PPC::F8RCRegClass, Op0, Op1); |
4016 | 0 | } |
4017 | 0 | return 0; |
4018 | 0 | } |
4019 | | |
4020 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4021 | 0 | if (RetVT.SimpleTy != MVT::f128) |
4022 | 0 | return 0; |
4023 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
4024 | 0 | return fastEmitInst_rr(PPC::XSADDQP, &PPC::VRRCRegClass, Op0, Op1); |
4025 | 0 | } |
4026 | 0 | return 0; |
4027 | 0 | } |
4028 | | |
4029 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4030 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4031 | 0 | return 0; |
4032 | 0 | if ((Subtarget->hasVSX())) { |
4033 | 0 | return fastEmitInst_rr(PPC::XVADDSP, &PPC::VSRCRegClass, Op0, Op1); |
4034 | 0 | } |
4035 | 0 | return 0; |
4036 | 0 | } |
4037 | | |
4038 | 0 | unsigned fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4039 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4040 | 0 | return 0; |
4041 | 0 | if ((Subtarget->hasVSX())) { |
4042 | 0 | return fastEmitInst_rr(PPC::XVADDDP, &PPC::VSRCRegClass, Op0, Op1); |
4043 | 0 | } |
4044 | 0 | return 0; |
4045 | 0 | } |
4046 | | |
4047 | 0 | unsigned fastEmit_ISD_STRICT_FADD_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4048 | 0 | switch (VT.SimpleTy) { |
4049 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FADD_MVT_f32_rr(RetVT, Op0, Op1); |
4050 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FADD_MVT_f64_rr(RetVT, Op0, Op1); |
4051 | 0 | case MVT::f128: return fastEmit_ISD_STRICT_FADD_MVT_f128_rr(RetVT, Op0, Op1); |
4052 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FADD_MVT_v4f32_rr(RetVT, Op0, Op1); |
4053 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FADD_MVT_v2f64_rr(RetVT, Op0, Op1); |
4054 | 0 | default: return 0; |
4055 | 0 | } |
4056 | 0 | } |
4057 | | |
4058 | | // FastEmit functions for ISD::STRICT_FDIV. |
4059 | | |
4060 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4061 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4062 | 0 | return 0; |
4063 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
4064 | 0 | return fastEmitInst_rr(PPC::XSDIVSP, &PPC::VSSRCRegClass, Op0, Op1); |
4065 | 0 | } |
4066 | 0 | if ((Subtarget->hasSPE())) { |
4067 | 0 | return fastEmitInst_rr(PPC::EFSDIV, &PPC::GPRCRegClass, Op0, Op1); |
4068 | 0 | } |
4069 | 0 | if ((Subtarget->hasFPU())) { |
4070 | 0 | return fastEmitInst_rr(PPC::FDIVS, &PPC::F4RCRegClass, Op0, Op1); |
4071 | 0 | } |
4072 | 0 | return 0; |
4073 | 0 | } |
4074 | | |
4075 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4076 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4077 | 0 | return 0; |
4078 | 0 | if ((Subtarget->hasVSX())) { |
4079 | 0 | return fastEmitInst_rr(PPC::XSDIVDP, &PPC::VSFRCRegClass, Op0, Op1); |
4080 | 0 | } |
4081 | 0 | if ((Subtarget->hasSPE())) { |
4082 | 0 | return fastEmitInst_rr(PPC::EFDDIV, &PPC::SPERCRegClass, Op0, Op1); |
4083 | 0 | } |
4084 | 0 | if ((Subtarget->hasFPU())) { |
4085 | 0 | return fastEmitInst_rr(PPC::FDIV, &PPC::F8RCRegClass, Op0, Op1); |
4086 | 0 | } |
4087 | 0 | return 0; |
4088 | 0 | } |
4089 | | |
4090 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4091 | 0 | if (RetVT.SimpleTy != MVT::f128) |
4092 | 0 | return 0; |
4093 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
4094 | 0 | return fastEmitInst_rr(PPC::XSDIVQP, &PPC::VRRCRegClass, Op0, Op1); |
4095 | 0 | } |
4096 | 0 | return 0; |
4097 | 0 | } |
4098 | | |
4099 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4100 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4101 | 0 | return 0; |
4102 | 0 | if ((Subtarget->hasVSX())) { |
4103 | 0 | return fastEmitInst_rr(PPC::XVDIVSP, &PPC::VSRCRegClass, Op0, Op1); |
4104 | 0 | } |
4105 | 0 | return 0; |
4106 | 0 | } |
4107 | | |
4108 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4109 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4110 | 0 | return 0; |
4111 | 0 | if ((Subtarget->hasVSX())) { |
4112 | 0 | return fastEmitInst_rr(PPC::XVDIVDP, &PPC::VSRCRegClass, Op0, Op1); |
4113 | 0 | } |
4114 | 0 | return 0; |
4115 | 0 | } |
4116 | | |
4117 | 0 | unsigned fastEmit_ISD_STRICT_FDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4118 | 0 | switch (VT.SimpleTy) { |
4119 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FDIV_MVT_f32_rr(RetVT, Op0, Op1); |
4120 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FDIV_MVT_f64_rr(RetVT, Op0, Op1); |
4121 | 0 | case MVT::f128: return fastEmit_ISD_STRICT_FDIV_MVT_f128_rr(RetVT, Op0, Op1); |
4122 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FDIV_MVT_v4f32_rr(RetVT, Op0, Op1); |
4123 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FDIV_MVT_v2f64_rr(RetVT, Op0, Op1); |
4124 | 0 | default: return 0; |
4125 | 0 | } |
4126 | 0 | } |
4127 | | |
4128 | | // FastEmit functions for ISD::STRICT_FMAXNUM. |
4129 | | |
4130 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4131 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4132 | 0 | return 0; |
4133 | 0 | if ((Subtarget->hasVSX())) { |
4134 | 0 | return fastEmitInst_rr(PPC::XVMAXSP, &PPC::VSRCRegClass, Op0, Op1); |
4135 | 0 | } |
4136 | 0 | return 0; |
4137 | 0 | } |
4138 | | |
4139 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4140 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4141 | 0 | return 0; |
4142 | 0 | if ((Subtarget->hasVSX())) { |
4143 | 0 | return fastEmitInst_rr(PPC::XVMAXDP, &PPC::VSRCRegClass, Op0, Op1); |
4144 | 0 | } |
4145 | 0 | return 0; |
4146 | 0 | } |
4147 | | |
4148 | 0 | unsigned fastEmit_ISD_STRICT_FMAXNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4149 | 0 | switch (VT.SimpleTy) { |
4150 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
4151 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMAXNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
4152 | 0 | default: return 0; |
4153 | 0 | } |
4154 | 0 | } |
4155 | | |
4156 | | // FastEmit functions for ISD::STRICT_FMINNUM. |
4157 | | |
4158 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4159 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4160 | 0 | return 0; |
4161 | 0 | if ((Subtarget->hasVSX())) { |
4162 | 0 | return fastEmitInst_rr(PPC::XVMINSP, &PPC::VSRCRegClass, Op0, Op1); |
4163 | 0 | } |
4164 | 0 | return 0; |
4165 | 0 | } |
4166 | | |
4167 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4168 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4169 | 0 | return 0; |
4170 | 0 | if ((Subtarget->hasVSX())) { |
4171 | 0 | return fastEmitInst_rr(PPC::XVMINDP, &PPC::VSRCRegClass, Op0, Op1); |
4172 | 0 | } |
4173 | 0 | return 0; |
4174 | 0 | } |
4175 | | |
4176 | 0 | unsigned fastEmit_ISD_STRICT_FMINNUM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4177 | 0 | switch (VT.SimpleTy) { |
4178 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMINNUM_MVT_v4f32_rr(RetVT, Op0, Op1); |
4179 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMINNUM_MVT_v2f64_rr(RetVT, Op0, Op1); |
4180 | 0 | default: return 0; |
4181 | 0 | } |
4182 | 0 | } |
4183 | | |
4184 | | // FastEmit functions for ISD::STRICT_FMUL. |
4185 | | |
4186 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4187 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4188 | 0 | return 0; |
4189 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
4190 | 0 | return fastEmitInst_rr(PPC::XSMULSP, &PPC::VSSRCRegClass, Op0, Op1); |
4191 | 0 | } |
4192 | 0 | if ((Subtarget->hasSPE())) { |
4193 | 0 | return fastEmitInst_rr(PPC::EFSMUL, &PPC::GPRCRegClass, Op0, Op1); |
4194 | 0 | } |
4195 | 0 | if ((Subtarget->hasFPU())) { |
4196 | 0 | return fastEmitInst_rr(PPC::FMULS, &PPC::F4RCRegClass, Op0, Op1); |
4197 | 0 | } |
4198 | 0 | return 0; |
4199 | 0 | } |
4200 | | |
4201 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4202 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4203 | 0 | return 0; |
4204 | 0 | if ((Subtarget->hasVSX())) { |
4205 | 0 | return fastEmitInst_rr(PPC::XSMULDP, &PPC::VSFRCRegClass, Op0, Op1); |
4206 | 0 | } |
4207 | 0 | if ((Subtarget->hasSPE())) { |
4208 | 0 | return fastEmitInst_rr(PPC::EFDMUL, &PPC::SPERCRegClass, Op0, Op1); |
4209 | 0 | } |
4210 | 0 | if ((Subtarget->hasFPU())) { |
4211 | 0 | return fastEmitInst_rr(PPC::FMUL, &PPC::F8RCRegClass, Op0, Op1); |
4212 | 0 | } |
4213 | 0 | return 0; |
4214 | 0 | } |
4215 | | |
4216 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4217 | 0 | if (RetVT.SimpleTy != MVT::f128) |
4218 | 0 | return 0; |
4219 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
4220 | 0 | return fastEmitInst_rr(PPC::XSMULQP, &PPC::VRRCRegClass, Op0, Op1); |
4221 | 0 | } |
4222 | 0 | return 0; |
4223 | 0 | } |
4224 | | |
4225 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4226 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4227 | 0 | return 0; |
4228 | 0 | if ((Subtarget->hasVSX())) { |
4229 | 0 | return fastEmitInst_rr(PPC::XVMULSP, &PPC::VSRCRegClass, Op0, Op1); |
4230 | 0 | } |
4231 | 0 | return 0; |
4232 | 0 | } |
4233 | | |
4234 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4235 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4236 | 0 | return 0; |
4237 | 0 | if ((Subtarget->hasVSX())) { |
4238 | 0 | return fastEmitInst_rr(PPC::XVMULDP, &PPC::VSRCRegClass, Op0, Op1); |
4239 | 0 | } |
4240 | 0 | return 0; |
4241 | 0 | } |
4242 | | |
4243 | 0 | unsigned fastEmit_ISD_STRICT_FMUL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4244 | 0 | switch (VT.SimpleTy) { |
4245 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FMUL_MVT_f32_rr(RetVT, Op0, Op1); |
4246 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FMUL_MVT_f64_rr(RetVT, Op0, Op1); |
4247 | 0 | case MVT::f128: return fastEmit_ISD_STRICT_FMUL_MVT_f128_rr(RetVT, Op0, Op1); |
4248 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FMUL_MVT_v4f32_rr(RetVT, Op0, Op1); |
4249 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FMUL_MVT_v2f64_rr(RetVT, Op0, Op1); |
4250 | 0 | default: return 0; |
4251 | 0 | } |
4252 | 0 | } |
4253 | | |
4254 | | // FastEmit functions for ISD::STRICT_FSUB. |
4255 | | |
4256 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4257 | 0 | if (RetVT.SimpleTy != MVT::f32) |
4258 | 0 | return 0; |
4259 | 0 | if ((Subtarget->hasP8Vector()) && (Subtarget->hasVSX())) { |
4260 | 0 | return fastEmitInst_rr(PPC::XSSUBSP, &PPC::VSSRCRegClass, Op0, Op1); |
4261 | 0 | } |
4262 | 0 | if ((Subtarget->hasSPE())) { |
4263 | 0 | return fastEmitInst_rr(PPC::EFSSUB, &PPC::GPRCRegClass, Op0, Op1); |
4264 | 0 | } |
4265 | 0 | if ((Subtarget->hasFPU())) { |
4266 | 0 | return fastEmitInst_rr(PPC::FSUBS, &PPC::F4RCRegClass, Op0, Op1); |
4267 | 0 | } |
4268 | 0 | return 0; |
4269 | 0 | } |
4270 | | |
4271 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4272 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4273 | 0 | return 0; |
4274 | 0 | if ((Subtarget->hasVSX())) { |
4275 | 0 | return fastEmitInst_rr(PPC::XSSUBDP, &PPC::VSFRCRegClass, Op0, Op1); |
4276 | 0 | } |
4277 | 0 | if ((Subtarget->hasSPE())) { |
4278 | 0 | return fastEmitInst_rr(PPC::EFDSUB, &PPC::SPERCRegClass, Op0, Op1); |
4279 | 0 | } |
4280 | 0 | if ((Subtarget->hasFPU())) { |
4281 | 0 | return fastEmitInst_rr(PPC::FSUB, &PPC::F8RCRegClass, Op0, Op1); |
4282 | 0 | } |
4283 | 0 | return 0; |
4284 | 0 | } |
4285 | | |
4286 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4287 | 0 | if (RetVT.SimpleTy != MVT::f128) |
4288 | 0 | return 0; |
4289 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
4290 | 0 | return fastEmitInst_rr(PPC::XSSUBQP, &PPC::VRRCRegClass, Op0, Op1); |
4291 | 0 | } |
4292 | 0 | return 0; |
4293 | 0 | } |
4294 | | |
4295 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4296 | 0 | if (RetVT.SimpleTy != MVT::v4f32) |
4297 | 0 | return 0; |
4298 | 0 | if ((Subtarget->hasVSX())) { |
4299 | 0 | return fastEmitInst_rr(PPC::XVSUBSP, &PPC::VSRCRegClass, Op0, Op1); |
4300 | 0 | } |
4301 | 0 | return 0; |
4302 | 0 | } |
4303 | | |
4304 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4305 | 0 | if (RetVT.SimpleTy != MVT::v2f64) |
4306 | 0 | return 0; |
4307 | 0 | if ((Subtarget->hasVSX())) { |
4308 | 0 | return fastEmitInst_rr(PPC::XVSUBDP, &PPC::VSRCRegClass, Op0, Op1); |
4309 | 0 | } |
4310 | 0 | return 0; |
4311 | 0 | } |
4312 | | |
4313 | 0 | unsigned fastEmit_ISD_STRICT_FSUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4314 | 0 | switch (VT.SimpleTy) { |
4315 | 0 | case MVT::f32: return fastEmit_ISD_STRICT_FSUB_MVT_f32_rr(RetVT, Op0, Op1); |
4316 | 0 | case MVT::f64: return fastEmit_ISD_STRICT_FSUB_MVT_f64_rr(RetVT, Op0, Op1); |
4317 | 0 | case MVT::f128: return fastEmit_ISD_STRICT_FSUB_MVT_f128_rr(RetVT, Op0, Op1); |
4318 | 0 | case MVT::v4f32: return fastEmit_ISD_STRICT_FSUB_MVT_v4f32_rr(RetVT, Op0, Op1); |
4319 | 0 | case MVT::v2f64: return fastEmit_ISD_STRICT_FSUB_MVT_v2f64_rr(RetVT, Op0, Op1); |
4320 | 0 | default: return 0; |
4321 | 0 | } |
4322 | 0 | } |
4323 | | |
4324 | | // FastEmit functions for ISD::SUB. |
4325 | | |
4326 | 0 | unsigned fastEmit_ISD_SUB_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4327 | 0 | if (RetVT.SimpleTy != MVT::i1) |
4328 | 0 | return 0; |
4329 | 0 | return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op1); |
4330 | 0 | } |
4331 | | |
4332 | 0 | unsigned fastEmit_ISD_SUB_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4333 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4334 | 0 | return 0; |
4335 | 0 | if ((Subtarget->hasAltivec())) { |
4336 | 0 | return fastEmitInst_rr(PPC::VSUBUBM, &PPC::VRRCRegClass, Op0, Op1); |
4337 | 0 | } |
4338 | 0 | return 0; |
4339 | 0 | } |
4340 | | |
4341 | 0 | unsigned fastEmit_ISD_SUB_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4342 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4343 | 0 | return 0; |
4344 | 0 | if ((Subtarget->hasAltivec())) { |
4345 | 0 | return fastEmitInst_rr(PPC::VSUBUHM, &PPC::VRRCRegClass, Op0, Op1); |
4346 | 0 | } |
4347 | 0 | return 0; |
4348 | 0 | } |
4349 | | |
4350 | 0 | unsigned fastEmit_ISD_SUB_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4351 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4352 | 0 | return 0; |
4353 | 0 | if ((Subtarget->hasAltivec())) { |
4354 | 0 | return fastEmitInst_rr(PPC::VSUBUWM, &PPC::VRRCRegClass, Op0, Op1); |
4355 | 0 | } |
4356 | 0 | return 0; |
4357 | 0 | } |
4358 | | |
4359 | 0 | unsigned fastEmit_ISD_SUB_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4360 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4361 | 0 | return 0; |
4362 | 0 | if ((Subtarget->hasP8Altivec())) { |
4363 | 0 | return fastEmitInst_rr(PPC::VSUBUDM, &PPC::VRRCRegClass, Op0, Op1); |
4364 | 0 | } |
4365 | 0 | return 0; |
4366 | 0 | } |
4367 | | |
4368 | 0 | unsigned fastEmit_ISD_SUB_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4369 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
4370 | 0 | return 0; |
4371 | 0 | if ((Subtarget->hasP8Altivec())) { |
4372 | 0 | return fastEmitInst_rr(PPC::VSUBUQM, &PPC::VRRCRegClass, Op0, Op1); |
4373 | 0 | } |
4374 | 0 | return 0; |
4375 | 0 | } |
4376 | | |
4377 | 0 | unsigned fastEmit_ISD_SUB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4378 | 0 | switch (VT.SimpleTy) { |
4379 | 0 | case MVT::i1: return fastEmit_ISD_SUB_MVT_i1_rr(RetVT, Op0, Op1); |
4380 | 0 | case MVT::v16i8: return fastEmit_ISD_SUB_MVT_v16i8_rr(RetVT, Op0, Op1); |
4381 | 0 | case MVT::v8i16: return fastEmit_ISD_SUB_MVT_v8i16_rr(RetVT, Op0, Op1); |
4382 | 0 | case MVT::v4i32: return fastEmit_ISD_SUB_MVT_v4i32_rr(RetVT, Op0, Op1); |
4383 | 0 | case MVT::v2i64: return fastEmit_ISD_SUB_MVT_v2i64_rr(RetVT, Op0, Op1); |
4384 | 0 | case MVT::v1i128: return fastEmit_ISD_SUB_MVT_v1i128_rr(RetVT, Op0, Op1); |
4385 | 0 | default: return 0; |
4386 | 0 | } |
4387 | 0 | } |
4388 | | |
4389 | | // FastEmit functions for ISD::UADDSAT. |
4390 | | |
4391 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4392 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4393 | 0 | return 0; |
4394 | 0 | if ((Subtarget->hasAltivec())) { |
4395 | 0 | return fastEmitInst_rr(PPC::VADDUBS, &PPC::VRRCRegClass, Op0, Op1); |
4396 | 0 | } |
4397 | 0 | return 0; |
4398 | 0 | } |
4399 | | |
4400 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4401 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4402 | 0 | return 0; |
4403 | 0 | if ((Subtarget->hasAltivec())) { |
4404 | 0 | return fastEmitInst_rr(PPC::VADDUHS, &PPC::VRRCRegClass, Op0, Op1); |
4405 | 0 | } |
4406 | 0 | return 0; |
4407 | 0 | } |
4408 | | |
4409 | 0 | unsigned fastEmit_ISD_UADDSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4410 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4411 | 0 | return 0; |
4412 | 0 | if ((Subtarget->hasAltivec())) { |
4413 | 0 | return fastEmitInst_rr(PPC::VADDUWS, &PPC::VRRCRegClass, Op0, Op1); |
4414 | 0 | } |
4415 | 0 | return 0; |
4416 | 0 | } |
4417 | | |
4418 | 0 | unsigned fastEmit_ISD_UADDSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4419 | 0 | switch (VT.SimpleTy) { |
4420 | 0 | case MVT::v16i8: return fastEmit_ISD_UADDSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
4421 | 0 | case MVT::v8i16: return fastEmit_ISD_UADDSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
4422 | 0 | case MVT::v4i32: return fastEmit_ISD_UADDSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
4423 | 0 | default: return 0; |
4424 | 0 | } |
4425 | 0 | } |
4426 | | |
4427 | | // FastEmit functions for ISD::UDIV. |
4428 | | |
4429 | 0 | unsigned fastEmit_ISD_UDIV_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4430 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4431 | 0 | return 0; |
4432 | 0 | return fastEmitInst_rr(PPC::DIVWU, &PPC::GPRCRegClass, Op0, Op1); |
4433 | 0 | } |
4434 | | |
4435 | 0 | unsigned fastEmit_ISD_UDIV_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4436 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4437 | 0 | return 0; |
4438 | 0 | return fastEmitInst_rr(PPC::DIVDU, &PPC::G8RCRegClass, Op0, Op1); |
4439 | 0 | } |
4440 | | |
4441 | 0 | unsigned fastEmit_ISD_UDIV_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4442 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4443 | 0 | return 0; |
4444 | 0 | if ((Subtarget->isISA3_1())) { |
4445 | 0 | return fastEmitInst_rr(PPC::VDIVUW, &PPC::VRRCRegClass, Op0, Op1); |
4446 | 0 | } |
4447 | 0 | return 0; |
4448 | 0 | } |
4449 | | |
4450 | 0 | unsigned fastEmit_ISD_UDIV_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4451 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4452 | 0 | return 0; |
4453 | 0 | if ((Subtarget->isISA3_1())) { |
4454 | 0 | return fastEmitInst_rr(PPC::VDIVUD, &PPC::VRRCRegClass, Op0, Op1); |
4455 | 0 | } |
4456 | 0 | return 0; |
4457 | 0 | } |
4458 | | |
4459 | 0 | unsigned fastEmit_ISD_UDIV_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4460 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
4461 | 0 | return 0; |
4462 | 0 | if ((Subtarget->isISA3_1())) { |
4463 | 0 | return fastEmitInst_rr(PPC::VDIVUQ, &PPC::VRRCRegClass, Op0, Op1); |
4464 | 0 | } |
4465 | 0 | return 0; |
4466 | 0 | } |
4467 | | |
4468 | 0 | unsigned fastEmit_ISD_UDIV_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4469 | 0 | switch (VT.SimpleTy) { |
4470 | 0 | case MVT::i32: return fastEmit_ISD_UDIV_MVT_i32_rr(RetVT, Op0, Op1); |
4471 | 0 | case MVT::i64: return fastEmit_ISD_UDIV_MVT_i64_rr(RetVT, Op0, Op1); |
4472 | 0 | case MVT::v4i32: return fastEmit_ISD_UDIV_MVT_v4i32_rr(RetVT, Op0, Op1); |
4473 | 0 | case MVT::v2i64: return fastEmit_ISD_UDIV_MVT_v2i64_rr(RetVT, Op0, Op1); |
4474 | 0 | case MVT::v1i128: return fastEmit_ISD_UDIV_MVT_v1i128_rr(RetVT, Op0, Op1); |
4475 | 0 | default: return 0; |
4476 | 0 | } |
4477 | 0 | } |
4478 | | |
4479 | | // FastEmit functions for ISD::UMAX. |
4480 | | |
4481 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4482 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4483 | 0 | return 0; |
4484 | 0 | if ((Subtarget->hasAltivec())) { |
4485 | 0 | return fastEmitInst_rr(PPC::VMAXUB, &PPC::VRRCRegClass, Op0, Op1); |
4486 | 0 | } |
4487 | 0 | return 0; |
4488 | 0 | } |
4489 | | |
4490 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4491 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4492 | 0 | return 0; |
4493 | 0 | if ((Subtarget->hasAltivec())) { |
4494 | 0 | return fastEmitInst_rr(PPC::VMAXUH, &PPC::VRRCRegClass, Op0, Op1); |
4495 | 0 | } |
4496 | 0 | return 0; |
4497 | 0 | } |
4498 | | |
4499 | 0 | unsigned fastEmit_ISD_UMAX_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4500 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4501 | 0 | return 0; |
4502 | 0 | if ((Subtarget->hasAltivec())) { |
4503 | 0 | return fastEmitInst_rr(PPC::VMAXUW, &PPC::VRRCRegClass, Op0, Op1); |
4504 | 0 | } |
4505 | 0 | return 0; |
4506 | 0 | } |
4507 | | |
4508 | 0 | unsigned fastEmit_ISD_UMAX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4509 | 0 | switch (VT.SimpleTy) { |
4510 | 0 | case MVT::v16i8: return fastEmit_ISD_UMAX_MVT_v16i8_rr(RetVT, Op0, Op1); |
4511 | 0 | case MVT::v8i16: return fastEmit_ISD_UMAX_MVT_v8i16_rr(RetVT, Op0, Op1); |
4512 | 0 | case MVT::v4i32: return fastEmit_ISD_UMAX_MVT_v4i32_rr(RetVT, Op0, Op1); |
4513 | 0 | default: return 0; |
4514 | 0 | } |
4515 | 0 | } |
4516 | | |
4517 | | // FastEmit functions for ISD::UMIN. |
4518 | | |
4519 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4520 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4521 | 0 | return 0; |
4522 | 0 | if ((Subtarget->hasAltivec())) { |
4523 | 0 | return fastEmitInst_rr(PPC::VMINUB, &PPC::VRRCRegClass, Op0, Op1); |
4524 | 0 | } |
4525 | 0 | return 0; |
4526 | 0 | } |
4527 | | |
4528 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4529 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4530 | 0 | return 0; |
4531 | 0 | if ((Subtarget->hasAltivec())) { |
4532 | 0 | return fastEmitInst_rr(PPC::VMINUH, &PPC::VRRCRegClass, Op0, Op1); |
4533 | 0 | } |
4534 | 0 | return 0; |
4535 | 0 | } |
4536 | | |
4537 | 0 | unsigned fastEmit_ISD_UMIN_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4538 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4539 | 0 | return 0; |
4540 | 0 | if ((Subtarget->hasAltivec())) { |
4541 | 0 | return fastEmitInst_rr(PPC::VMINUW, &PPC::VRRCRegClass, Op0, Op1); |
4542 | 0 | } |
4543 | 0 | return 0; |
4544 | 0 | } |
4545 | | |
4546 | 0 | unsigned fastEmit_ISD_UMIN_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4547 | 0 | switch (VT.SimpleTy) { |
4548 | 0 | case MVT::v16i8: return fastEmit_ISD_UMIN_MVT_v16i8_rr(RetVT, Op0, Op1); |
4549 | 0 | case MVT::v8i16: return fastEmit_ISD_UMIN_MVT_v8i16_rr(RetVT, Op0, Op1); |
4550 | 0 | case MVT::v4i32: return fastEmit_ISD_UMIN_MVT_v4i32_rr(RetVT, Op0, Op1); |
4551 | 0 | default: return 0; |
4552 | 0 | } |
4553 | 0 | } |
4554 | | |
4555 | | // FastEmit functions for ISD::UREM. |
4556 | | |
4557 | 0 | unsigned fastEmit_ISD_UREM_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4558 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4559 | 0 | return 0; |
4560 | 0 | if ((Subtarget->isISA3_0())) { |
4561 | 0 | return fastEmitInst_rr(PPC::MODUW, &PPC::GPRCRegClass, Op0, Op1); |
4562 | 0 | } |
4563 | 0 | return 0; |
4564 | 0 | } |
4565 | | |
4566 | 0 | unsigned fastEmit_ISD_UREM_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4567 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4568 | 0 | return 0; |
4569 | 0 | if ((Subtarget->isISA3_0())) { |
4570 | 0 | return fastEmitInst_rr(PPC::MODUD, &PPC::G8RCRegClass, Op0, Op1); |
4571 | 0 | } |
4572 | 0 | return 0; |
4573 | 0 | } |
4574 | | |
4575 | 0 | unsigned fastEmit_ISD_UREM_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4576 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4577 | 0 | return 0; |
4578 | 0 | if ((Subtarget->isISA3_1())) { |
4579 | 0 | return fastEmitInst_rr(PPC::VMODUW, &PPC::VRRCRegClass, Op0, Op1); |
4580 | 0 | } |
4581 | 0 | return 0; |
4582 | 0 | } |
4583 | | |
4584 | 0 | unsigned fastEmit_ISD_UREM_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4585 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4586 | 0 | return 0; |
4587 | 0 | if ((Subtarget->isISA3_1())) { |
4588 | 0 | return fastEmitInst_rr(PPC::VMODUD, &PPC::VRRCRegClass, Op0, Op1); |
4589 | 0 | } |
4590 | 0 | return 0; |
4591 | 0 | } |
4592 | | |
4593 | 0 | unsigned fastEmit_ISD_UREM_MVT_v1i128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4594 | 0 | if (RetVT.SimpleTy != MVT::v1i128) |
4595 | 0 | return 0; |
4596 | 0 | if ((Subtarget->isISA3_1())) { |
4597 | 0 | return fastEmitInst_rr(PPC::VMODUQ, &PPC::VRRCRegClass, Op0, Op1); |
4598 | 0 | } |
4599 | 0 | return 0; |
4600 | 0 | } |
4601 | | |
4602 | 0 | unsigned fastEmit_ISD_UREM_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4603 | 0 | switch (VT.SimpleTy) { |
4604 | 0 | case MVT::i32: return fastEmit_ISD_UREM_MVT_i32_rr(RetVT, Op0, Op1); |
4605 | 0 | case MVT::i64: return fastEmit_ISD_UREM_MVT_i64_rr(RetVT, Op0, Op1); |
4606 | 0 | case MVT::v4i32: return fastEmit_ISD_UREM_MVT_v4i32_rr(RetVT, Op0, Op1); |
4607 | 0 | case MVT::v2i64: return fastEmit_ISD_UREM_MVT_v2i64_rr(RetVT, Op0, Op1); |
4608 | 0 | case MVT::v1i128: return fastEmit_ISD_UREM_MVT_v1i128_rr(RetVT, Op0, Op1); |
4609 | 0 | default: return 0; |
4610 | 0 | } |
4611 | 0 | } |
4612 | | |
4613 | | // FastEmit functions for ISD::USUBSAT. |
4614 | | |
4615 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4616 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4617 | 0 | return 0; |
4618 | 0 | if ((Subtarget->hasAltivec())) { |
4619 | 0 | return fastEmitInst_rr(PPC::VSUBUBS, &PPC::VRRCRegClass, Op0, Op1); |
4620 | 0 | } |
4621 | 0 | return 0; |
4622 | 0 | } |
4623 | | |
4624 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4625 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4626 | 0 | return 0; |
4627 | 0 | if ((Subtarget->hasAltivec())) { |
4628 | 0 | return fastEmitInst_rr(PPC::VSUBUHS, &PPC::VRRCRegClass, Op0, Op1); |
4629 | 0 | } |
4630 | 0 | return 0; |
4631 | 0 | } |
4632 | | |
4633 | 0 | unsigned fastEmit_ISD_USUBSAT_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4634 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4635 | 0 | return 0; |
4636 | 0 | if ((Subtarget->hasAltivec())) { |
4637 | 0 | return fastEmitInst_rr(PPC::VSUBUWS, &PPC::VRRCRegClass, Op0, Op1); |
4638 | 0 | } |
4639 | 0 | return 0; |
4640 | 0 | } |
4641 | | |
4642 | 0 | unsigned fastEmit_ISD_USUBSAT_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4643 | 0 | switch (VT.SimpleTy) { |
4644 | 0 | case MVT::v16i8: return fastEmit_ISD_USUBSAT_MVT_v16i8_rr(RetVT, Op0, Op1); |
4645 | 0 | case MVT::v8i16: return fastEmit_ISD_USUBSAT_MVT_v8i16_rr(RetVT, Op0, Op1); |
4646 | 0 | case MVT::v4i32: return fastEmit_ISD_USUBSAT_MVT_v4i32_rr(RetVT, Op0, Op1); |
4647 | 0 | default: return 0; |
4648 | 0 | } |
4649 | 0 | } |
4650 | | |
4651 | | // FastEmit functions for ISD::XOR. |
4652 | | |
4653 | 0 | unsigned fastEmit_ISD_XOR_MVT_i1_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4654 | 0 | if (RetVT.SimpleTy != MVT::i1) |
4655 | 0 | return 0; |
4656 | 0 | return fastEmitInst_rr(PPC::CRXOR, &PPC::CRBITRCRegClass, Op0, Op1); |
4657 | 0 | } |
4658 | | |
4659 | 0 | unsigned fastEmit_ISD_XOR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4660 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4661 | 0 | return 0; |
4662 | 0 | return fastEmitInst_rr(PPC::XOR, &PPC::GPRCRegClass, Op0, Op1); |
4663 | 0 | } |
4664 | | |
4665 | 0 | unsigned fastEmit_ISD_XOR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4666 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4667 | 0 | return 0; |
4668 | 0 | return fastEmitInst_rr(PPC::XOR8, &PPC::G8RCRegClass, Op0, Op1); |
4669 | 0 | } |
4670 | | |
4671 | 0 | unsigned fastEmit_ISD_XOR_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4672 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4673 | 0 | return 0; |
4674 | 0 | if ((Subtarget->hasVSX())) { |
4675 | 0 | return fastEmitInst_rr(PPC::XXLXOR, &PPC::VSRCRegClass, Op0, Op1); |
4676 | 0 | } |
4677 | 0 | if ((Subtarget->hasAltivec())) { |
4678 | 0 | return fastEmitInst_rr(PPC::VXOR, &PPC::VRRCRegClass, Op0, Op1); |
4679 | 0 | } |
4680 | 0 | return 0; |
4681 | 0 | } |
4682 | | |
4683 | 0 | unsigned fastEmit_ISD_XOR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4684 | 0 | switch (VT.SimpleTy) { |
4685 | 0 | case MVT::i1: return fastEmit_ISD_XOR_MVT_i1_rr(RetVT, Op0, Op1); |
4686 | 0 | case MVT::i32: return fastEmit_ISD_XOR_MVT_i32_rr(RetVT, Op0, Op1); |
4687 | 0 | case MVT::i64: return fastEmit_ISD_XOR_MVT_i64_rr(RetVT, Op0, Op1); |
4688 | 0 | case MVT::v4i32: return fastEmit_ISD_XOR_MVT_v4i32_rr(RetVT, Op0, Op1); |
4689 | 0 | default: return 0; |
4690 | 0 | } |
4691 | 0 | } |
4692 | | |
4693 | | // FastEmit functions for PPCISD::ADD_TLS. |
4694 | | |
4695 | 0 | unsigned fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4696 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4697 | 0 | return 0; |
4698 | 0 | return fastEmitInst_rr(PPC::ADD4TLS, &PPC::GPRCRegClass, Op0, Op1); |
4699 | 0 | } |
4700 | | |
4701 | 0 | unsigned fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4702 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4703 | 0 | return 0; |
4704 | 0 | return fastEmitInst_rr(PPC::ADD8TLS, &PPC::G8RCRegClass, Op0, Op1); |
4705 | 0 | } |
4706 | | |
4707 | 0 | unsigned fastEmit_PPCISD_ADD_TLS_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4708 | 0 | switch (VT.SimpleTy) { |
4709 | 0 | case MVT::i32: return fastEmit_PPCISD_ADD_TLS_MVT_i32_rr(RetVT, Op0, Op1); |
4710 | 0 | case MVT::i64: return fastEmit_PPCISD_ADD_TLS_MVT_i64_rr(RetVT, Op0, Op1); |
4711 | 0 | default: return 0; |
4712 | 0 | } |
4713 | 0 | } |
4714 | | |
4715 | | // FastEmit functions for PPCISD::CMPB. |
4716 | | |
4717 | 0 | unsigned fastEmit_PPCISD_CMPB_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4718 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4719 | 0 | return 0; |
4720 | 0 | return fastEmitInst_rr(PPC::CMPB, &PPC::GPRCRegClass, Op0, Op1); |
4721 | 0 | } |
4722 | | |
4723 | 0 | unsigned fastEmit_PPCISD_CMPB_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4724 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4725 | 0 | return 0; |
4726 | 0 | return fastEmitInst_rr(PPC::CMPB8, &PPC::G8RCRegClass, Op0, Op1); |
4727 | 0 | } |
4728 | | |
4729 | 0 | unsigned fastEmit_PPCISD_CMPB_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4730 | 0 | switch (VT.SimpleTy) { |
4731 | 0 | case MVT::i32: return fastEmit_PPCISD_CMPB_MVT_i32_rr(RetVT, Op0, Op1); |
4732 | 0 | case MVT::i64: return fastEmit_PPCISD_CMPB_MVT_i64_rr(RetVT, Op0, Op1); |
4733 | 0 | default: return 0; |
4734 | 0 | } |
4735 | 0 | } |
4736 | | |
4737 | | // FastEmit functions for PPCISD::FADDRTZ. |
4738 | | |
4739 | 0 | unsigned fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4740 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4741 | 0 | return 0; |
4742 | 0 | if ((Subtarget->hasFPU())) { |
4743 | 0 | return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op1); |
4744 | 0 | } |
4745 | 0 | return 0; |
4746 | 0 | } |
4747 | | |
4748 | 0 | unsigned fastEmit_PPCISD_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4749 | 0 | switch (VT.SimpleTy) { |
4750 | 0 | case MVT::f64: return fastEmit_PPCISD_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1); |
4751 | 0 | default: return 0; |
4752 | 0 | } |
4753 | 0 | } |
4754 | | |
4755 | | // FastEmit functions for PPCISD::GET_TLS_ADDR. |
4756 | | |
4757 | 0 | unsigned fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4758 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4759 | 0 | return 0; |
4760 | 0 | return fastEmitInst_rr(PPC::GETtlsADDR32AIX, &PPC::GPRCRegClass, Op0, Op1); |
4761 | 0 | } |
4762 | | |
4763 | 0 | unsigned fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4764 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4765 | 0 | return 0; |
4766 | 0 | return fastEmitInst_rr(PPC::GETtlsADDR64AIX, &PPC::G8RCRegClass, Op0, Op1); |
4767 | 0 | } |
4768 | | |
4769 | 0 | unsigned fastEmit_PPCISD_GET_TLS_ADDR_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4770 | 0 | switch (VT.SimpleTy) { |
4771 | 0 | case MVT::i32: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i32_rr(RetVT, Op0, Op1); |
4772 | 0 | case MVT::i64: return fastEmit_PPCISD_GET_TLS_ADDR_MVT_i64_rr(RetVT, Op0, Op1); |
4773 | 0 | default: return 0; |
4774 | 0 | } |
4775 | 0 | } |
4776 | | |
4777 | | // FastEmit functions for PPCISD::SHL. |
4778 | | |
4779 | 0 | unsigned fastEmit_PPCISD_SHL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4780 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4781 | 0 | return 0; |
4782 | 0 | return fastEmitInst_rr(PPC::SLW, &PPC::GPRCRegClass, Op0, Op1); |
4783 | 0 | } |
4784 | | |
4785 | 0 | unsigned fastEmit_PPCISD_SHL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4786 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4787 | 0 | return 0; |
4788 | 0 | if ((Subtarget->hasAltivec())) { |
4789 | 0 | return fastEmitInst_rr(PPC::VSLB, &PPC::VRRCRegClass, Op0, Op1); |
4790 | 0 | } |
4791 | 0 | return 0; |
4792 | 0 | } |
4793 | | |
4794 | 0 | unsigned fastEmit_PPCISD_SHL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4795 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4796 | 0 | return 0; |
4797 | 0 | if ((Subtarget->hasAltivec())) { |
4798 | 0 | return fastEmitInst_rr(PPC::VSLH, &PPC::VRRCRegClass, Op0, Op1); |
4799 | 0 | } |
4800 | 0 | return 0; |
4801 | 0 | } |
4802 | | |
4803 | 0 | unsigned fastEmit_PPCISD_SHL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4804 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4805 | 0 | return 0; |
4806 | 0 | if ((Subtarget->hasAltivec())) { |
4807 | 0 | return fastEmitInst_rr(PPC::VSLW, &PPC::VRRCRegClass, Op0, Op1); |
4808 | 0 | } |
4809 | 0 | return 0; |
4810 | 0 | } |
4811 | | |
4812 | 0 | unsigned fastEmit_PPCISD_SHL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4813 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4814 | 0 | return 0; |
4815 | 0 | if ((Subtarget->hasP8Altivec())) { |
4816 | 0 | return fastEmitInst_rr(PPC::VSLD, &PPC::VRRCRegClass, Op0, Op1); |
4817 | 0 | } |
4818 | 0 | return 0; |
4819 | 0 | } |
4820 | | |
4821 | 0 | unsigned fastEmit_PPCISD_SHL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4822 | 0 | switch (VT.SimpleTy) { |
4823 | 0 | case MVT::i32: return fastEmit_PPCISD_SHL_MVT_i32_rr(RetVT, Op0, Op1); |
4824 | 0 | case MVT::v16i8: return fastEmit_PPCISD_SHL_MVT_v16i8_rr(RetVT, Op0, Op1); |
4825 | 0 | case MVT::v8i16: return fastEmit_PPCISD_SHL_MVT_v8i16_rr(RetVT, Op0, Op1); |
4826 | 0 | case MVT::v4i32: return fastEmit_PPCISD_SHL_MVT_v4i32_rr(RetVT, Op0, Op1); |
4827 | 0 | case MVT::v2i64: return fastEmit_PPCISD_SHL_MVT_v2i64_rr(RetVT, Op0, Op1); |
4828 | 0 | default: return 0; |
4829 | 0 | } |
4830 | 0 | } |
4831 | | |
4832 | | // FastEmit functions for PPCISD::SRA. |
4833 | | |
4834 | 0 | unsigned fastEmit_PPCISD_SRA_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4835 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4836 | 0 | return 0; |
4837 | 0 | return fastEmitInst_rr(PPC::SRAW, &PPC::GPRCRegClass, Op0, Op1); |
4838 | 0 | } |
4839 | | |
4840 | 0 | unsigned fastEmit_PPCISD_SRA_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4841 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4842 | 0 | return 0; |
4843 | 0 | if ((Subtarget->hasAltivec())) { |
4844 | 0 | return fastEmitInst_rr(PPC::VSRAB, &PPC::VRRCRegClass, Op0, Op1); |
4845 | 0 | } |
4846 | 0 | return 0; |
4847 | 0 | } |
4848 | | |
4849 | 0 | unsigned fastEmit_PPCISD_SRA_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4850 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4851 | 0 | return 0; |
4852 | 0 | if ((Subtarget->hasAltivec())) { |
4853 | 0 | return fastEmitInst_rr(PPC::VSRAH, &PPC::VRRCRegClass, Op0, Op1); |
4854 | 0 | } |
4855 | 0 | return 0; |
4856 | 0 | } |
4857 | | |
4858 | 0 | unsigned fastEmit_PPCISD_SRA_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4859 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4860 | 0 | return 0; |
4861 | 0 | if ((Subtarget->hasAltivec())) { |
4862 | 0 | return fastEmitInst_rr(PPC::VSRAW, &PPC::VRRCRegClass, Op0, Op1); |
4863 | 0 | } |
4864 | 0 | return 0; |
4865 | 0 | } |
4866 | | |
4867 | 0 | unsigned fastEmit_PPCISD_SRA_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4868 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4869 | 0 | return 0; |
4870 | 0 | if ((Subtarget->hasP8Altivec())) { |
4871 | 0 | return fastEmitInst_rr(PPC::VSRAD, &PPC::VRRCRegClass, Op0, Op1); |
4872 | 0 | } |
4873 | 0 | return 0; |
4874 | 0 | } |
4875 | | |
4876 | 0 | unsigned fastEmit_PPCISD_SRA_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4877 | 0 | switch (VT.SimpleTy) { |
4878 | 0 | case MVT::i32: return fastEmit_PPCISD_SRA_MVT_i32_rr(RetVT, Op0, Op1); |
4879 | 0 | case MVT::v16i8: return fastEmit_PPCISD_SRA_MVT_v16i8_rr(RetVT, Op0, Op1); |
4880 | 0 | case MVT::v8i16: return fastEmit_PPCISD_SRA_MVT_v8i16_rr(RetVT, Op0, Op1); |
4881 | 0 | case MVT::v4i32: return fastEmit_PPCISD_SRA_MVT_v4i32_rr(RetVT, Op0, Op1); |
4882 | 0 | case MVT::v2i64: return fastEmit_PPCISD_SRA_MVT_v2i64_rr(RetVT, Op0, Op1); |
4883 | 0 | default: return 0; |
4884 | 0 | } |
4885 | 0 | } |
4886 | | |
4887 | | // FastEmit functions for PPCISD::SRL. |
4888 | | |
4889 | 0 | unsigned fastEmit_PPCISD_SRL_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4890 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4891 | 0 | return 0; |
4892 | 0 | return fastEmitInst_rr(PPC::SRW, &PPC::GPRCRegClass, Op0, Op1); |
4893 | 0 | } |
4894 | | |
4895 | 0 | unsigned fastEmit_PPCISD_SRL_MVT_v16i8_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4896 | 0 | if (RetVT.SimpleTy != MVT::v16i8) |
4897 | 0 | return 0; |
4898 | 0 | if ((Subtarget->hasAltivec())) { |
4899 | 0 | return fastEmitInst_rr(PPC::VSRB, &PPC::VRRCRegClass, Op0, Op1); |
4900 | 0 | } |
4901 | 0 | return 0; |
4902 | 0 | } |
4903 | | |
4904 | 0 | unsigned fastEmit_PPCISD_SRL_MVT_v8i16_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4905 | 0 | if (RetVT.SimpleTy != MVT::v8i16) |
4906 | 0 | return 0; |
4907 | 0 | if ((Subtarget->hasAltivec())) { |
4908 | 0 | return fastEmitInst_rr(PPC::VSRH, &PPC::VRRCRegClass, Op0, Op1); |
4909 | 0 | } |
4910 | 0 | return 0; |
4911 | 0 | } |
4912 | | |
4913 | 0 | unsigned fastEmit_PPCISD_SRL_MVT_v4i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4914 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
4915 | 0 | return 0; |
4916 | 0 | if ((Subtarget->hasAltivec())) { |
4917 | 0 | return fastEmitInst_rr(PPC::VSRW, &PPC::VRRCRegClass, Op0, Op1); |
4918 | 0 | } |
4919 | 0 | return 0; |
4920 | 0 | } |
4921 | | |
4922 | 0 | unsigned fastEmit_PPCISD_SRL_MVT_v2i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4923 | 0 | if (RetVT.SimpleTy != MVT::v2i64) |
4924 | 0 | return 0; |
4925 | 0 | if ((Subtarget->hasP8Altivec())) { |
4926 | 0 | return fastEmitInst_rr(PPC::VSRD, &PPC::VRRCRegClass, Op0, Op1); |
4927 | 0 | } |
4928 | 0 | return 0; |
4929 | 0 | } |
4930 | | |
4931 | 0 | unsigned fastEmit_PPCISD_SRL_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4932 | 0 | switch (VT.SimpleTy) { |
4933 | 0 | case MVT::i32: return fastEmit_PPCISD_SRL_MVT_i32_rr(RetVT, Op0, Op1); |
4934 | 0 | case MVT::v16i8: return fastEmit_PPCISD_SRL_MVT_v16i8_rr(RetVT, Op0, Op1); |
4935 | 0 | case MVT::v8i16: return fastEmit_PPCISD_SRL_MVT_v8i16_rr(RetVT, Op0, Op1); |
4936 | 0 | case MVT::v4i32: return fastEmit_PPCISD_SRL_MVT_v4i32_rr(RetVT, Op0, Op1); |
4937 | 0 | case MVT::v2i64: return fastEmit_PPCISD_SRL_MVT_v2i64_rr(RetVT, Op0, Op1); |
4938 | 0 | default: return 0; |
4939 | 0 | } |
4940 | 0 | } |
4941 | | |
4942 | | // FastEmit functions for PPCISD::STRICT_FADDRTZ. |
4943 | | |
4944 | 0 | unsigned fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4945 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4946 | 0 | return 0; |
4947 | 0 | if ((Subtarget->hasFPU())) { |
4948 | 0 | return fastEmitInst_rr(PPC::FADDrtz, &PPC::F8RCRegClass, Op0, Op1); |
4949 | 0 | } |
4950 | 0 | return 0; |
4951 | 0 | } |
4952 | | |
4953 | 0 | unsigned fastEmit_PPCISD_STRICT_FADDRTZ_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4954 | 0 | switch (VT.SimpleTy) { |
4955 | 0 | case MVT::f64: return fastEmit_PPCISD_STRICT_FADDRTZ_MVT_f64_rr(RetVT, Op0, Op1); |
4956 | 0 | default: return 0; |
4957 | 0 | } |
4958 | 0 | } |
4959 | | |
4960 | | // FastEmit functions for PPCISD::TLSGD_AIX. |
4961 | | |
4962 | 0 | unsigned fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4963 | 0 | if (RetVT.SimpleTy != MVT::i32) |
4964 | 0 | return 0; |
4965 | 0 | return fastEmitInst_rr(PPC::TLSGDAIX, &PPC::GPRCRegClass, Op0, Op1); |
4966 | 0 | } |
4967 | | |
4968 | 0 | unsigned fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4969 | 0 | if (RetVT.SimpleTy != MVT::i64) |
4970 | 0 | return 0; |
4971 | 0 | return fastEmitInst_rr(PPC::TLSGDAIX8, &PPC::G8RCRegClass, Op0, Op1); |
4972 | 0 | } |
4973 | | |
4974 | 0 | unsigned fastEmit_PPCISD_TLSGD_AIX_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
4975 | 0 | switch (VT.SimpleTy) { |
4976 | 0 | case MVT::i32: return fastEmit_PPCISD_TLSGD_AIX_MVT_i32_rr(RetVT, Op0, Op1); |
4977 | 0 | case MVT::i64: return fastEmit_PPCISD_TLSGD_AIX_MVT_i64_rr(RetVT, Op0, Op1); |
4978 | 0 | default: return 0; |
4979 | 0 | } |
4980 | 0 | } |
4981 | | |
4982 | | // FastEmit functions for PPCISD::XSMAXC. |
4983 | | |
4984 | 0 | unsigned fastEmit_PPCISD_XSMAXC_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4985 | 0 | if (RetVT.SimpleTy != MVT::f64) |
4986 | 0 | return 0; |
4987 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
4988 | 0 | return fastEmitInst_rr(PPC::XSMAXCDP, &PPC::VSFRCRegClass, Op0, Op1); |
4989 | 0 | } |
4990 | 0 | return 0; |
4991 | 0 | } |
4992 | | |
4993 | 0 | unsigned fastEmit_PPCISD_XSMAXC_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
4994 | 0 | if (RetVT.SimpleTy != MVT::f128) |
4995 | 0 | return 0; |
4996 | 0 | if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) { |
4997 | 0 | return fastEmitInst_rr(PPC::XSMAXCQP, &PPC::VRRCRegClass, Op0, Op1); |
4998 | 0 | } |
4999 | 0 | return 0; |
5000 | 0 | } |
5001 | | |
5002 | 0 | unsigned fastEmit_PPCISD_XSMAXC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
5003 | 0 | switch (VT.SimpleTy) { |
5004 | 0 | case MVT::f64: return fastEmit_PPCISD_XSMAXC_MVT_f64_rr(RetVT, Op0, Op1); |
5005 | 0 | case MVT::f128: return fastEmit_PPCISD_XSMAXC_MVT_f128_rr(RetVT, Op0, Op1); |
5006 | 0 | default: return 0; |
5007 | 0 | } |
5008 | 0 | } |
5009 | | |
5010 | | // FastEmit functions for PPCISD::XSMINC. |
5011 | | |
5012 | 0 | unsigned fastEmit_PPCISD_XSMINC_MVT_f64_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
5013 | 0 | if (RetVT.SimpleTy != MVT::f64) |
5014 | 0 | return 0; |
5015 | 0 | if ((Subtarget->hasP9Vector()) && (Subtarget->hasVSX())) { |
5016 | 0 | return fastEmitInst_rr(PPC::XSMINCDP, &PPC::VSFRCRegClass, Op0, Op1); |
5017 | 0 | } |
5018 | 0 | return 0; |
5019 | 0 | } |
5020 | | |
5021 | 0 | unsigned fastEmit_PPCISD_XSMINC_MVT_f128_rr(MVT RetVT, unsigned Op0, unsigned Op1) { |
5022 | 0 | if (RetVT.SimpleTy != MVT::f128) |
5023 | 0 | return 0; |
5024 | 0 | if ((Subtarget->hasVSX()) && (Subtarget->isISA3_1())) { |
5025 | 0 | return fastEmitInst_rr(PPC::XSMINCQP, &PPC::VRRCRegClass, Op0, Op1); |
5026 | 0 | } |
5027 | 0 | return 0; |
5028 | 0 | } |
5029 | | |
5030 | 0 | unsigned fastEmit_PPCISD_XSMINC_rr(MVT VT, MVT RetVT, unsigned Op0, unsigned Op1) { |
5031 | 0 | switch (VT.SimpleTy) { |
5032 | 0 | case MVT::f64: return fastEmit_PPCISD_XSMINC_MVT_f64_rr(RetVT, Op0, Op1); |
5033 | 0 | case MVT::f128: return fastEmit_PPCISD_XSMINC_MVT_f128_rr(RetVT, Op0, Op1); |
5034 | 0 | default: return 0; |
5035 | 0 | } |
5036 | 0 | } |
5037 | | |
5038 | | // Top-level FastEmit function. |
5039 | | |
5040 | 0 | unsigned fastEmit_rr(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, unsigned Op1) override { |
5041 | 0 | switch (Opcode) { |
5042 | 0 | case ISD::ABDU: return fastEmit_ISD_ABDU_rr(VT, RetVT, Op0, Op1); |
5043 | 0 | case ISD::ADD: return fastEmit_ISD_ADD_rr(VT, RetVT, Op0, Op1); |
5044 | 0 | case ISD::ADDC: return fastEmit_ISD_ADDC_rr(VT, RetVT, Op0, Op1); |
5045 | 0 | case ISD::ADDE: return fastEmit_ISD_ADDE_rr(VT, RetVT, Op0, Op1); |
5046 | 0 | case ISD::AND: return fastEmit_ISD_AND_rr(VT, RetVT, Op0, Op1); |
5047 | 0 | case ISD::BUILD_VECTOR: return fastEmit_ISD_BUILD_VECTOR_rr(VT, RetVT, Op0, Op1); |
5048 | 0 | case ISD::FADD: return fastEmit_ISD_FADD_rr(VT, RetVT, Op0, Op1); |
5049 | 0 | case ISD::FDIV: return fastEmit_ISD_FDIV_rr(VT, RetVT, Op0, Op1); |
5050 | 0 | case ISD::FMAXNUM: return fastEmit_ISD_FMAXNUM_rr(VT, RetVT, Op0, Op1); |
5051 | 0 | case ISD::FMAXNUM_IEEE: return fastEmit_ISD_FMAXNUM_IEEE_rr(VT, RetVT, Op0, Op1); |
5052 | 0 | case ISD::FMINNUM: return fastEmit_ISD_FMINNUM_rr(VT, RetVT, Op0, Op1); |
5053 | 0 | case ISD::FMINNUM_IEEE: return fastEmit_ISD_FMINNUM_IEEE_rr(VT, RetVT, Op0, Op1); |
5054 | 0 | case ISD::FMUL: return fastEmit_ISD_FMUL_rr(VT, RetVT, Op0, Op1); |
5055 | 0 | case ISD::FSUB: return fastEmit_ISD_FSUB_rr(VT, RetVT, Op0, Op1); |
5056 | 0 | case ISD::MUL: return fastEmit_ISD_MUL_rr(VT, RetVT, Op0, Op1); |
5057 | 0 | case ISD::MULHS: return fastEmit_ISD_MULHS_rr(VT, RetVT, Op0, Op1); |
5058 | 0 | case ISD::MULHU: return fastEmit_ISD_MULHU_rr(VT, RetVT, Op0, Op1); |
5059 | 0 | case ISD::OR: return fastEmit_ISD_OR_rr(VT, RetVT, Op0, Op1); |
5060 | 0 | case ISD::ROTL: return fastEmit_ISD_ROTL_rr(VT, RetVT, Op0, Op1); |
5061 | 0 | case ISD::SADDSAT: return fastEmit_ISD_SADDSAT_rr(VT, RetVT, Op0, Op1); |
5062 | 0 | case ISD::SDIV: return fastEmit_ISD_SDIV_rr(VT, RetVT, Op0, Op1); |
5063 | 0 | case ISD::SHL: return fastEmit_ISD_SHL_rr(VT, RetVT, Op0, Op1); |
5064 | 0 | case ISD::SMAX: return fastEmit_ISD_SMAX_rr(VT, RetVT, Op0, Op1); |
5065 | 0 | case ISD::SMIN: return fastEmit_ISD_SMIN_rr(VT, RetVT, Op0, Op1); |
5066 | 0 | case ISD::SRA: return fastEmit_ISD_SRA_rr(VT, RetVT, Op0, Op1); |
5067 | 0 | case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op1); |
5068 | 0 | case ISD::SRL: return fastEmit_ISD_SRL_rr(VT, RetVT, Op0, Op1); |
5069 | 0 | case ISD::SSUBSAT: return fastEmit_ISD_SSUBSAT_rr(VT, RetVT, Op0, Op1); |
5070 | 0 | case ISD::STRICT_FADD: return fastEmit_ISD_STRICT_FADD_rr(VT, RetVT, Op0, Op1); |
5071 | 0 | case ISD::STRICT_FDIV: return fastEmit_ISD_STRICT_FDIV_rr(VT, RetVT, Op0, Op1); |
5072 | 0 | case ISD::STRICT_FMAXNUM: return fastEmit_ISD_STRICT_FMAXNUM_rr(VT, RetVT, Op0, Op1); |
5073 | 0 | case ISD::STRICT_FMINNUM: return fastEmit_ISD_STRICT_FMINNUM_rr(VT, RetVT, Op0, Op1); |
5074 | 0 | case ISD::STRICT_FMUL: return fastEmit_ISD_STRICT_FMUL_rr(VT, RetVT, Op0, Op1); |
5075 | 0 | case ISD::STRICT_FSUB: return fastEmit_ISD_STRICT_FSUB_rr(VT, RetVT, Op0, Op1); |
5076 | 0 | case ISD::SUB: return fastEmit_ISD_SUB_rr(VT, RetVT, Op0, Op1); |
5077 | 0 | case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op1); |
5078 | 0 | case ISD::UDIV: return fastEmit_ISD_UDIV_rr(VT, RetVT, Op0, Op1); |
5079 | 0 | case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op1); |
5080 | 0 | case ISD::UMIN: return fastEmit_ISD_UMIN_rr(VT, RetVT, Op0, Op1); |
5081 | 0 | case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op1); |
5082 | 0 | case ISD::USUBSAT: return fastEmit_ISD_USUBSAT_rr(VT, RetVT, Op0, Op1); |
5083 | 0 | case ISD::XOR: return fastEmit_ISD_XOR_rr(VT, RetVT, Op0, Op1); |
5084 | 0 | case PPCISD::ADD_TLS: return fastEmit_PPCISD_ADD_TLS_rr(VT, RetVT, Op0, Op1); |
5085 | 0 | case PPCISD::CMPB: return fastEmit_PPCISD_CMPB_rr(VT, RetVT, Op0, Op1); |
5086 | 0 | case PPCISD::FADDRTZ: return fastEmit_PPCISD_FADDRTZ_rr(VT, RetVT, Op0, Op1); |
5087 | 0 | case PPCISD::GET_TLS_ADDR: return fastEmit_PPCISD_GET_TLS_ADDR_rr(VT, RetVT, Op0, Op1); |
5088 | 0 | case PPCISD::SHL: return fastEmit_PPCISD_SHL_rr(VT, RetVT, Op0, Op1); |
5089 | 0 | case PPCISD::SRA: return fastEmit_PPCISD_SRA_rr(VT, RetVT, Op0, Op1); |
5090 | 0 | case PPCISD::SRL: return fastEmit_PPCISD_SRL_rr(VT, RetVT, Op0, Op1); |
5091 | 0 | case PPCISD::STRICT_FADDRTZ: return fastEmit_PPCISD_STRICT_FADDRTZ_rr(VT, RetVT, Op0, Op1); |
5092 | 0 | case PPCISD::TLSGD_AIX: return fastEmit_PPCISD_TLSGD_AIX_rr(VT, RetVT, Op0, Op1); |
5093 | 0 | case PPCISD::XSMAXC: return fastEmit_PPCISD_XSMAXC_rr(VT, RetVT, Op0, Op1); |
5094 | 0 | case PPCISD::XSMINC: return fastEmit_PPCISD_XSMINC_rr(VT, RetVT, Op0, Op1); |
5095 | 0 | default: return 0; |
5096 | 0 | } |
5097 | 0 | } |
5098 | | |
5099 | | // FastEmit functions for ISD::SRA. |
5100 | | |
5101 | 0 | unsigned fastEmit_ISD_SRA_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5102 | 0 | if (RetVT.SimpleTy != MVT::i32) |
5103 | 0 | return 0; |
5104 | 0 | return fastEmitInst_ri(PPC::SRAWI, &PPC::GPRCRegClass, Op0, imm1); |
5105 | 0 | } |
5106 | | |
5107 | 0 | unsigned fastEmit_ISD_SRA_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5108 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5109 | 0 | return 0; |
5110 | 0 | return fastEmitInst_ri(PPC::SRADI, &PPC::G8RCRegClass, Op0, imm1); |
5111 | 0 | } |
5112 | | |
5113 | 0 | unsigned fastEmit_ISD_SRA_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5114 | 0 | switch (VT.SimpleTy) { |
5115 | 0 | case MVT::i32: return fastEmit_ISD_SRA_MVT_i32_ri(RetVT, Op0, imm1); |
5116 | 0 | case MVT::i64: return fastEmit_ISD_SRA_MVT_i64_ri(RetVT, Op0, imm1); |
5117 | 0 | default: return 0; |
5118 | 0 | } |
5119 | 0 | } |
5120 | | |
5121 | | // FastEmit functions for PPCISD::EXTSWSLI. |
5122 | | |
5123 | 0 | unsigned fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5124 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5125 | 0 | return 0; |
5126 | 0 | if ((Subtarget->isISA3_0())) { |
5127 | 0 | return fastEmitInst_ri(PPC::EXTSWSLI_32_64, &PPC::G8RCRegClass, Op0, imm1); |
5128 | 0 | } |
5129 | 0 | return 0; |
5130 | 0 | } |
5131 | | |
5132 | 0 | unsigned fastEmit_PPCISD_EXTSWSLI_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5133 | 0 | switch (VT.SimpleTy) { |
5134 | 0 | case MVT::i32: return fastEmit_PPCISD_EXTSWSLI_MVT_i32_ri(RetVT, Op0, imm1); |
5135 | 0 | default: return 0; |
5136 | 0 | } |
5137 | 0 | } |
5138 | | |
5139 | | // FastEmit functions for PPCISD::TC_RETURN. |
5140 | | |
5141 | 0 | unsigned fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5142 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
5143 | 0 | return 0; |
5144 | 0 | return fastEmitInst_ri(PPC::TCRETURNri, &PPC::CTRRCRegClass, Op0, imm1); |
5145 | 0 | } |
5146 | | |
5147 | 0 | unsigned fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5148 | 0 | if (RetVT.SimpleTy != MVT::isVoid) |
5149 | 0 | return 0; |
5150 | 0 | return fastEmitInst_ri(PPC::TCRETURNri8, &PPC::CTRRC8RegClass, Op0, imm1); |
5151 | 0 | } |
5152 | | |
5153 | 0 | unsigned fastEmit_PPCISD_TC_RETURN_ri(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5154 | 0 | switch (VT.SimpleTy) { |
5155 | 0 | case MVT::i32: return fastEmit_PPCISD_TC_RETURN_MVT_i32_ri(RetVT, Op0, imm1); |
5156 | 0 | case MVT::i64: return fastEmit_PPCISD_TC_RETURN_MVT_i64_ri(RetVT, Op0, imm1); |
5157 | 0 | default: return 0; |
5158 | 0 | } |
5159 | 0 | } |
5160 | | |
5161 | | // Top-level FastEmit function. |
5162 | | |
5163 | 0 | unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) override { |
5164 | 0 | if (VT == MVT::i32 && Predicate_imm32SExt16(imm1)) |
5165 | 0 | if (unsigned Reg = fastEmit_ri_Predicate_imm32SExt16(VT, RetVT, Opcode, Op0, imm1)) |
5166 | 0 | return Reg; |
5167 | | |
5168 | 0 | if (VT == MVT::i64 && Predicate_imm64SExt16(imm1)) |
5169 | 0 | if (unsigned Reg = fastEmit_ri_Predicate_imm64SExt16(VT, RetVT, Opcode, Op0, imm1)) |
5170 | 0 | return Reg; |
5171 | | |
5172 | 0 | switch (Opcode) { |
5173 | 0 | case ISD::SRA: return fastEmit_ISD_SRA_ri(VT, RetVT, Op0, imm1); |
5174 | 0 | case PPCISD::EXTSWSLI: return fastEmit_PPCISD_EXTSWSLI_ri(VT, RetVT, Op0, imm1); |
5175 | 0 | case PPCISD::TC_RETURN: return fastEmit_PPCISD_TC_RETURN_ri(VT, RetVT, Op0, imm1); |
5176 | 0 | default: return 0; |
5177 | 0 | } |
5178 | 0 | } |
5179 | | |
5180 | | // FastEmit functions for ISD::ADD. |
5181 | | |
5182 | 0 | unsigned fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5183 | 0 | if (RetVT.SimpleTy != MVT::i32) |
5184 | 0 | return 0; |
5185 | 0 | return fastEmitInst_ri(PPC::ADDI, &PPC::GPRCRegClass, Op0, imm1); |
5186 | 0 | } |
5187 | | |
5188 | 0 | unsigned fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5189 | 0 | switch (VT.SimpleTy) { |
5190 | 0 | case MVT::i32: return fastEmit_ISD_ADD_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); |
5191 | 0 | default: return 0; |
5192 | 0 | } |
5193 | 0 | } |
5194 | | |
5195 | | // FastEmit functions for ISD::ADDC. |
5196 | | |
5197 | 0 | unsigned fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5198 | 0 | if (RetVT.SimpleTy != MVT::i32) |
5199 | 0 | return 0; |
5200 | 0 | return fastEmitInst_ri(PPC::ADDIC, &PPC::GPRCRegClass, Op0, imm1); |
5201 | 0 | } |
5202 | | |
5203 | 0 | unsigned fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5204 | 0 | switch (VT.SimpleTy) { |
5205 | 0 | case MVT::i32: return fastEmit_ISD_ADDC_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); |
5206 | 0 | default: return 0; |
5207 | 0 | } |
5208 | 0 | } |
5209 | | |
5210 | | // FastEmit functions for ISD::MUL. |
5211 | | |
5212 | 0 | unsigned fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5213 | 0 | if (RetVT.SimpleTy != MVT::i32) |
5214 | 0 | return 0; |
5215 | 0 | return fastEmitInst_ri(PPC::MULLI, &PPC::GPRCRegClass, Op0, imm1); |
5216 | 0 | } |
5217 | | |
5218 | 0 | unsigned fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5219 | 0 | switch (VT.SimpleTy) { |
5220 | 0 | case MVT::i32: return fastEmit_ISD_MUL_MVT_i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); |
5221 | 0 | default: return 0; |
5222 | 0 | } |
5223 | 0 | } |
5224 | | |
5225 | | // FastEmit functions for PPCISD::XXSPLT. |
5226 | | |
5227 | 0 | unsigned fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5228 | 0 | if (RetVT.SimpleTy != MVT::v4i32) |
5229 | 0 | return 0; |
5230 | 0 | if ((Subtarget->hasVSX())) { |
5231 | 0 | return fastEmitInst_ri(PPC::XXSPLTW, &PPC::VSRCRegClass, Op0, imm1); |
5232 | 0 | } |
5233 | 0 | return 0; |
5234 | 0 | } |
5235 | | |
5236 | 0 | unsigned fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5237 | 0 | switch (VT.SimpleTy) { |
5238 | 0 | case MVT::v4i32: return fastEmit_PPCISD_XXSPLT_MVT_v4i32_ri_Predicate_imm32SExt16(RetVT, Op0, imm1); |
5239 | 0 | default: return 0; |
5240 | 0 | } |
5241 | 0 | } |
5242 | | |
5243 | | // Top-level FastEmit function. |
5244 | | |
5245 | 0 | unsigned fastEmit_ri_Predicate_imm32SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
5246 | 0 | switch (Opcode) { |
5247 | 0 | case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); |
5248 | 0 | case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); |
5249 | 0 | case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); |
5250 | 0 | case PPCISD::XXSPLT: return fastEmit_PPCISD_XXSPLT_ri_Predicate_imm32SExt16(VT, RetVT, Op0, imm1); |
5251 | 0 | default: return 0; |
5252 | 0 | } |
5253 | 0 | } |
5254 | | |
5255 | | // FastEmit functions for ISD::ADD. |
5256 | | |
5257 | 0 | unsigned fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5258 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5259 | 0 | return 0; |
5260 | 0 | return fastEmitInst_ri(PPC::ADDI8, &PPC::G8RCRegClass, Op0, imm1); |
5261 | 0 | } |
5262 | | |
5263 | 0 | unsigned fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5264 | 0 | switch (VT.SimpleTy) { |
5265 | 0 | case MVT::i64: return fastEmit_ISD_ADD_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1); |
5266 | 0 | default: return 0; |
5267 | 0 | } |
5268 | 0 | } |
5269 | | |
5270 | | // FastEmit functions for ISD::ADDC. |
5271 | | |
5272 | 0 | unsigned fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5273 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5274 | 0 | return 0; |
5275 | 0 | return fastEmitInst_ri(PPC::ADDIC8, &PPC::G8RCRegClass, Op0, imm1); |
5276 | 0 | } |
5277 | | |
5278 | 0 | unsigned fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5279 | 0 | switch (VT.SimpleTy) { |
5280 | 0 | case MVT::i64: return fastEmit_ISD_ADDC_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1); |
5281 | 0 | default: return 0; |
5282 | 0 | } |
5283 | 0 | } |
5284 | | |
5285 | | // FastEmit functions for ISD::MUL. |
5286 | | |
5287 | 0 | unsigned fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(MVT RetVT, unsigned Op0, uint64_t imm1) { |
5288 | 0 | if (RetVT.SimpleTy != MVT::i64) |
5289 | 0 | return 0; |
5290 | 0 | return fastEmitInst_ri(PPC::MULLI8, &PPC::G8RCRegClass, Op0, imm1); |
5291 | 0 | } |
5292 | | |
5293 | 0 | unsigned fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Op0, uint64_t imm1) { |
5294 | 0 | switch (VT.SimpleTy) { |
5295 | 0 | case MVT::i64: return fastEmit_ISD_MUL_MVT_i64_ri_Predicate_imm64SExt16(RetVT, Op0, imm1); |
5296 | 0 | default: return 0; |
5297 | 0 | } |
5298 | 0 | } |
5299 | | |
5300 | | // Top-level FastEmit function. |
5301 | | |
5302 | 0 | unsigned fastEmit_ri_Predicate_imm64SExt16(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0, uint64_t imm1) { |
5303 | 0 | switch (Opcode) { |
5304 | 0 | case ISD::ADD: return fastEmit_ISD_ADD_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1); |
5305 | 0 | case ISD::ADDC: return fastEmit_ISD_ADDC_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1); |
5306 | 0 | case ISD::MUL: return fastEmit_ISD_MUL_ri_Predicate_imm64SExt16(VT, RetVT, Op0, imm1); |
5307 | 0 | default: return 0; |
5308 | 0 | } |
5309 | 0 | } |
5310 | | |