Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/PowerPC/PPCGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace PPC {
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enum : unsigned {
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  InvalidRegBankID = ~0u,
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  CRRegBankID = 0,
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  FPRRegBankID = 1,
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  GPRRegBankID = 2,
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  VECRegBankID = 3,
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  NumRegisterBanks,
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};
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} // end namespace PPC
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static const RegisterBank *RegBanks[];
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  static const unsigned Sizes[];
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protected:
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  PPCGenRegisterBankInfo(unsigned HwMode = 0);
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace PPC {
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const uint32_t CRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (PPC::CRRCRegClassID - 0)) |
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    (1u << (PPC::CRBITRCRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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};
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const uint32_t FPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (PPC::VSSRCRegClassID - 0)) |
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    (1u << (PPC::F4RCRegClassID - 0)) |
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    (1u << (PPC::F8RCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
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    (1u << (PPC::VSFRCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
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    (1u << (PPC::VFRCRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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};
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const uint32_t GPRRegBankCoverageData[] = {
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    // 0-31
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    (1u << (PPC::G8RCRegClassID - 0)) |
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    (1u << (PPC::GPRCRegClassID - 0)) |
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    (1u << (PPC::G8RC_and_G8RC_NOX0RegClassID - 0)) |
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    (1u << (PPC::GPRC_NOR0RegClassID - 0)) |
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    (1u << (PPC::GPRC_and_GPRC_NOR0RegClassID - 0)) |
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    (1u << (PPC::G8RC_NOX0RegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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};
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const uint32_t VECRegBankCoverageData[] = {
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    // 0-31
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    (1u << (PPC::VSRCRegClassID - 0)) |
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    (1u << (PPC::VSSRCRegClassID - 0)) |
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    (1u << (PPC::VSFRCRegClassID - 0)) |
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    (1u << (PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRC_and_VSFRCRegClassID - 0)) |
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    (1u << (PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 0)) |
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    (1u << (PPC::VFRCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRC_and_VFRCRegClassID - 0)) |
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    (1u << (PPC::F4RCRegClassID - 0)) |
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    (1u << (PPC::F8RCRegClassID - 0)) |
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    (1u << (PPC::SPILLTOVSRRC_and_F4RCRegClassID - 0)) |
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    (1u << (PPC::VRRCRegClassID - 0)) |
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    (1u << (PPC::VSLRCRegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID - 32)) |
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    0,
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};
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constexpr RegisterBank CRRegBank(/* ID */ PPC::CRRegBankID, /* Name */ "CR", /* CoveredRegClasses */ CRRegBankCoverageData, /* NumRegClasses */ 54);
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constexpr RegisterBank FPRRegBank(/* ID */ PPC::FPRRegBankID, /* Name */ "FPR", /* CoveredRegClasses */ FPRRegBankCoverageData, /* NumRegClasses */ 54);
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constexpr RegisterBank GPRRegBank(/* ID */ PPC::GPRRegBankID, /* Name */ "GPR", /* CoveredRegClasses */ GPRRegBankCoverageData, /* NumRegClasses */ 54);
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constexpr RegisterBank VECRegBank(/* ID */ PPC::VECRegBankID, /* Name */ "VEC", /* CoveredRegClasses */ VECRegBankCoverageData, /* NumRegClasses */ 54);
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} // end namespace PPC
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const RegisterBank *PPCGenRegisterBankInfo::RegBanks[] = {
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    &PPC::CRRegBank,
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    &PPC::FPRRegBank,
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    &PPC::GPRRegBank,
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    &PPC::VECRegBank,
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};
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const unsigned PPCGenRegisterBankInfo::Sizes[] = {
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    // Mode = 0 (Default)
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    32,
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    64,
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    64,
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    128,
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};
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PPCGenRegisterBankInfo::PPCGenRegisterBankInfo(unsigned HwMode)
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    : RegisterBankInfo(RegBanks, PPC::NumRegisterBanks, Sizes, HwMode) {
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  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  for (auto RB : enumerate(RegBanks))
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    assert(RB.index() == RB.value()->getID() && "Index != ID");
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#endif // NDEBUG
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}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL