/src/build/lib/Target/PowerPC/PPCGenRegisterInfo.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass PPCMCRegisterClasses[];

namespace PPC {
enum {
  NoRegister,
  BP = 1,
  CARRY = 2,
  CTR = 3,
  FP = 4,
  LR = 5,
  RM = 6,
  SPEFSCR = 7,
  VRSAVE = 8,
  XER = 9,
  ZERO = 10,
  ACC0 = 11,
  ACC1 = 12,
  ACC2 = 13,
  ACC3 = 14,
  ACC4 = 15,
  ACC5 = 16,
  ACC6 = 17,
  ACC7 = 18,
  BP8 = 19,
  CR0 = 20,
  CR1 = 21,
  CR2 = 22,
  CR3 = 23,
  CR4 = 24,
  CR5 = 25,
  CR6 = 26,
  CR7 = 27,
  CTR8 = 28,
  DMR0 = 29,
  DMR1 = 30,
  DMR2 = 31,
  DMR3 = 32,
  DMR4 = 33,
  DMR5 = 34,
  DMR6 = 35,
  DMR7 = 36,
  DMRROW0 = 37,
  DMRROW1 = 38,
  DMRROW2 = 39,
  DMRROW3 = 40,
  DMRROW4 = 41,
  DMRROW5 = 42,
  DMRROW6 = 43,
  DMRROW7 = 44,
  DMRROW8 = 45,
  DMRROW9 = 46,
  DMRROW10 = 47,
  DMRROW11 = 48,
  DMRROW12 = 49,
  DMRROW13 = 50,
  DMRROW14 = 51,
  DMRROW15 = 52,
  DMRROW16 = 53,
  DMRROW17 = 54,
  DMRROW18 = 55,
  DMRROW19 = 56,
  DMRROW20 = 57,
  DMRROW21 = 58,
  DMRROW22 = 59,
  DMRROW23 = 60,
  DMRROW24 = 61,
  DMRROW25 = 62,
  DMRROW26 = 63,
  DMRROW27 = 64,
  DMRROW28 = 65,
  DMRROW29 = 66,
  DMRROW30 = 67,
  DMRROW31 = 68,
  DMRROW32 = 69,
  DMRROW33 = 70,
  DMRROW34 = 71,
  DMRROW35 = 72,
  DMRROW36 = 73,
  DMRROW37 = 74,
  DMRROW38 = 75,
  DMRROW39 = 76,
  DMRROW40 = 77,
  DMRROW41 = 78,
  DMRROW42 = 79,
  DMRROW43 = 80,
  DMRROW44 = 81,
  DMRROW45 = 82,
  DMRROW46 = 83,
  DMRROW47 = 84,
  DMRROW48 = 85,
  DMRROW49 = 86,
  DMRROW50 = 87,
  DMRROW51 = 88,
  DMRROW52 = 89,
  DMRROW53 = 90,
  DMRROW54 = 91,
  DMRROW55 = 92,
  DMRROW56 = 93,
  DMRROW57 = 94,
  DMRROW58 = 95,
  DMRROW59 = 96,
  DMRROW60 = 97,
  DMRROW61 = 98,
  DMRROW62 = 99,
  DMRROW63 = 100,
  DMRROWp0 = 101,
  DMRROWp1 = 102,
  DMRROWp2 = 103,
  DMRROWp3 = 104,
  DMRROWp4 = 105,
  DMRROWp5 = 106,
  DMRROWp6 = 107,
  DMRROWp7 = 108,
  DMRROWp8 = 109,
  DMRROWp9 = 110,
  DMRROWp10 = 111,
  DMRROWp11 = 112,
  DMRROWp12 = 113,
  DMRROWp13 = 114,
  DMRROWp14 = 115,
  DMRROWp15 = 116,
  DMRROWp16 = 117,
  DMRROWp17 = 118,
  DMRROWp18 = 119,
  DMRROWp19 = 120,
  DMRROWp20 = 121,
  DMRROWp21 = 122,
  DMRROWp22 = 123,
  DMRROWp23 = 124,
  DMRROWp24 = 125,
  DMRROWp25 = 126,
  DMRROWp26 = 127,
  DMRROWp27 = 128,
  DMRROWp28 = 129,
  DMRROWp29 = 130,
  DMRROWp30 = 131,
  DMRROWp31 = 132,
  DMRp0 = 133,
  DMRp1 = 134,
  DMRp2 = 135,
  DMRp3 = 136,
  F0 = 137,
  F1 = 138,
  F2 = 139,
  F3 = 140,
  F4 = 141,
  F5 = 142,
  F6 = 143,
  F7 = 144,
  F8 = 145,
  F9 = 146,
  F10 = 147,
  F11 = 148,
  F12 = 149,
  F13 = 150,
  F14 = 151,
  F15 = 152,
  F16 = 153,
  F17 = 154,
  F18 = 155,
  F19 = 156,
  F20 = 157,
  F21 = 158,
  F22 = 159,
  F23 = 160,
  F24 = 161,
  F25 = 162,
  F26 = 163,
  F27 = 164,
  F28 = 165,
  F29 = 166,
  F30 = 167,
  F31 = 168,
  FP8 = 169,
  Fpair0 = 170,
  Fpair2 = 171,
  Fpair4 = 172,
  Fpair6 = 173,
  Fpair8 = 174,
  Fpair10 = 175,
  Fpair12 = 176,
  Fpair14 = 177,
  Fpair16 = 178,
  Fpair18 = 179,
  Fpair20 = 180,
  Fpair22 = 181,
  Fpair24 = 182,
  Fpair26 = 183,
  Fpair28 = 184,
  Fpair30 = 185,
  H0 = 186,
  H1 = 187,
  H2 = 188,
  H3 = 189,
  H4 = 190,
  H5 = 191,
  H6 = 192,
  H7 = 193,
  H8 = 194,
  H9 = 195,
  H10 = 196,
  H11 = 197,
  H12 = 198,
  H13 = 199,
  H14 = 200,
  H15 = 201,
  H16 = 202,
  H17 = 203,
  H18 = 204,
  H19 = 205,
  H20 = 206,
  H21 = 207,
  H22 = 208,
  H23 = 209,
  H24 = 210,
  H25 = 211,
  H26 = 212,
  H27 = 213,
  H28 = 214,
  H29 = 215,
  H30 = 216,
  H31 = 217,
  LR8 = 218,
  R0 = 219,
  R1 = 220,
  R2 = 221,
  R3 = 222,
  R4 = 223,
  R5 = 224,
  R6 = 225,
  R7 = 226,
  R8 = 227,
  R9 = 228,
  R10 = 229,
  R11 = 230,
  R12 = 231,
  R13 = 232,
  R14 = 233,
  R15 = 234,
  R16 = 235,
  R17 = 236,
  R18 = 237,
  R19 = 238,
  R20 = 239,
  R21 = 240,
  R22 = 241,
  R23 = 242,
  R24 = 243,
  R25 = 244,
  R26 = 245,
  R27 = 246,
  R28 = 247,
  R29 = 248,
  R30 = 249,
  R31 = 250,
  S0 = 251,
  S1 = 252,
  S2 = 253,
  S3 = 254,
  S4 = 255,
  S5 = 256,
  S6 = 257,
  S7 = 258,
  S8 = 259,
  S9 = 260,
  S10 = 261,
  S11 = 262,
  S12 = 263,
  S13 = 264,
  S14 = 265,
  S15 = 266,
  S16 = 267,
  S17 = 268,
  S18 = 269,
  S19 = 270,
  S20 = 271,
  S21 = 272,
  S22 = 273,
  S23 = 274,
  S24 = 275,
  S25 = 276,
  S26 = 277,
  S27 = 278,
  S28 = 279,
  S29 = 280,
  S30 = 281,
  S31 = 282,
  UACC0 = 283,
  UACC1 = 284,
  UACC2 = 285,
  UACC3 = 286,
  UACC4 = 287,
  UACC5 = 288,
  UACC6 = 289,
  UACC7 = 290,
  V0 = 291,
  V1 = 292,
  V2 = 293,
  V3 = 294,
  V4 = 295,
  V5 = 296,
  V6 = 297,
  V7 = 298,
  V8 = 299,
  V9 = 300,
  V10 = 301,
  V11 = 302,
  V12 = 303,
  V13 = 304,
  V14 = 305,
  V15 = 306,
  V16 = 307,
  V17 = 308,
  V18 = 309,
  V19 = 310,
  V20 = 311,
  V21 = 312,
  V22 = 313,
  V23 = 314,
  V24 = 315,
  V25 = 316,
  V26 = 317,
  V27 = 318,
  V28 = 319,
  V29 = 320,
  V30 = 321,
  V31 = 322,
  VF0 = 323,
  VF1 = 324,
  VF2 = 325,
  VF3 = 326,
  VF4 = 327,
  VF5 = 328,
  VF6 = 329,
  VF7 = 330,
  VF8 = 331,
  VF9 = 332,
  VF10 = 333,
  VF11 = 334,
  VF12 = 335,
  VF13 = 336,
  VF14 = 337,
  VF15 = 338,
  VF16 = 339,
  VF17 = 340,
  VF18 = 341,
  VF19 = 342,
  VF20 = 343,
  VF21 = 344,
  VF22 = 345,
  VF23 = 346,
  VF24 = 347,
  VF25 = 348,
  VF26 = 349,
  VF27 = 350,
  VF28 = 351,
  VF29 = 352,
  VF30 = 353,
  VF31 = 354,
  VSL0 = 355,
  VSL1 = 356,
  VSL2 = 357,
  VSL3 = 358,
  VSL4 = 359,
  VSL5 = 360,
  VSL6 = 361,
  VSL7 = 362,
  VSL8 = 363,
  VSL9 = 364,
  VSL10 = 365,
  VSL11 = 366,
  VSL12 = 367,
  VSL13 = 368,
  VSL14 = 369,
  VSL15 = 370,
  VSL16 = 371,
  VSL17 = 372,
  VSL18 = 373,
  VSL19 = 374,
  VSL20 = 375,
  VSL21 = 376,
  VSL22 = 377,
  VSL23 = 378,
  VSL24 = 379,
  VSL25 = 380,
  VSL26 = 381,
  VSL27 = 382,
  VSL28 = 383,
  VSL29 = 384,
  VSL30 = 385,
  VSL31 = 386,
  VSRp0 = 387,
  VSRp1 = 388,
  VSRp2 = 389,
  VSRp3 = 390,
  VSRp4 = 391,
  VSRp5 = 392,
  VSRp6 = 393,
  VSRp7 = 394,
  VSRp8 = 395,
  VSRp9 = 396,
  VSRp10 = 397,
  VSRp11 = 398,
  VSRp12 = 399,
  VSRp13 = 400,
  VSRp14 = 401,
  VSRp15 = 402,
  VSRp16 = 403,
  VSRp17 = 404,
  VSRp18 = 405,
  VSRp19 = 406,
  VSRp20 = 407,
  VSRp21 = 408,
  VSRp22 = 409,
  VSRp23 = 410,
  VSRp24 = 411,
  VSRp25 = 412,
  VSRp26 = 413,
  VSRp27 = 414,
  VSRp28 = 415,
  VSRp29 = 416,
  VSRp30 = 417,
  VSRp31 = 418,
  VSX32 = 419,
  VSX33 = 420,
  VSX34 = 421,
  VSX35 = 422,
  VSX36 = 423,
  VSX37 = 424,
  VSX38 = 425,
  VSX39 = 426,
  VSX40 = 427,
  VSX41 = 428,
  VSX42 = 429,
  VSX43 = 430,
  VSX44 = 431,
  VSX45 = 432,
  VSX46 = 433,
  VSX47 = 434,
  VSX48 = 435,
  VSX49 = 436,
  VSX50 = 437,
  VSX51 = 438,
  VSX52 = 439,
  VSX53 = 440,
  VSX54 = 441,
  VSX55 = 442,
  VSX56 = 443,
  VSX57 = 444,
  VSX58 = 445,
  VSX59 = 446,
  VSX60 = 447,
  VSX61 = 448,
  VSX62 = 449,
  VSX63 = 450,
  WACC0 = 451,
  WACC1 = 452,
  WACC2 = 453,
  WACC3 = 454,
  WACC4 = 455,
  WACC5 = 456,
  WACC6 = 457,
  WACC7 = 458,
  WACC_HI0 = 459,
  WACC_HI1 = 460,
  WACC_HI2 = 461,
  WACC_HI3 = 462,
  WACC_HI4 = 463,
  WACC_HI5 = 464,
  WACC_HI6 = 465,
  WACC_HI7 = 466,
  X0 = 467,
  X1 = 468,
  X2 = 469,
  X3 = 470,
  X4 = 471,
  X5 = 472,
  X6 = 473,
  X7 = 474,
  X8 = 475,
  X9 = 476,
  X10 = 477,
  X11 = 478,
  X12 = 479,
  X13 = 480,
  X14 = 481,
  X15 = 482,
  X16 = 483,
  X17 = 484,
  X18 = 485,
  X19 = 486,
  X20 = 487,
  X21 = 488,
  X22 = 489,
  X23 = 490,
  X24 = 491,
  X25 = 492,
  X26 = 493,
  X27 = 494,
  X28 = 495,
  X29 = 496,
  X30 = 497,
  X31 = 498,
  ZERO8 = 499,
  CR0EQ = 500,
  CR1EQ = 501,
  CR2EQ = 502,
  CR3EQ = 503,
  CR4EQ = 504,
  CR5EQ = 505,
  CR6EQ = 506,
  CR7EQ = 507,
  CR0GT = 508,
  CR1GT = 509,
  CR2GT = 510,
  CR3GT = 511,
  CR4GT = 512,
  CR5GT = 513,
  CR6GT = 514,
  CR7GT = 515,
  CR0LT = 516,
  CR1LT = 517,
  CR2LT = 518,
  CR3LT = 519,
  CR4LT = 520,
  CR5LT = 521,
  CR6LT = 522,
  CR7LT = 523,
  CR0UN = 524,
  CR1UN = 525,
  CR2UN = 526,
  CR3UN = 527,
  CR4UN = 528,
  CR5UN = 529,
  CR6UN = 530,
  CR7UN = 531,
  G8p0 = 532,
  G8p1 = 533,
  G8p2 = 534,
  G8p3 = 535,
  G8p4 = 536,
  G8p5 = 537,
  G8p6 = 538,
  G8p7 = 539,
  G8p8 = 540,
  G8p9 = 541,
  G8p10 = 542,
  G8p11 = 543,
  G8p12 = 544,
  G8p13 = 545,
  G8p14 = 546,
  G8p15 = 547,
  NUM_TARGET_REGS // 548
};
} // end namespace PPC

// Register classes

namespace PPC {
enum {
  VSSRCRegClassID = 0,
  GPRCRegClassID = 1,
  GPRC_NOR0RegClassID = 2,
  GPRC_and_GPRC_NOR0RegClassID = 3,
  CRBITRCRegClassID = 4,
  F4RCRegClassID = 5,
  GPRC32RegClassID = 6,
  CRRCRegClassID = 7,
  CARRYRCRegClassID = 8,
  CTRRCRegClassID = 9,
  LRRCRegClassID = 10,
  VRSAVERCRegClassID = 11,
  SPILLTOVSRRCRegClassID = 12,
  VSFRCRegClassID = 13,
  G8RCRegClassID = 14,
  G8RC_NOX0RegClassID = 15,
  SPILLTOVSRRC_and_VSFRCRegClassID = 16,
  G8RC_and_G8RC_NOX0RegClassID = 17,
  F8RCRegClassID = 18,
  SPERCRegClassID = 19,
  VFRCRegClassID = 20,
  SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 21,
  SPILLTOVSRRC_and_VFRCRegClassID = 22,
  SPILLTOVSRRC_and_F4RCRegClassID = 23,
  CTRRC8RegClassID = 24,
  LR8RCRegClassID = 25,
  DMRROWRCRegClassID = 26,
  VSRCRegClassID = 27,
  VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 28,
  VRRCRegClassID = 29,
  VSLRCRegClassID = 30,
  VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 31,
  FpRCRegClassID = 32,
  G8pRCRegClassID = 33,
  G8pRC_with_sub_32_in_GPRC_NOR0RegClassID = 34,
  VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 35,
  FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID = 36,
  DMRROWpRCRegClassID = 37,
  VSRpRCRegClassID = 38,
  VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 39,
  VSRpRC_with_sub_64_in_F4RCRegClassID = 40,
  VSRpRC_with_sub_64_in_VFRCRegClassID = 41,
  VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID = 42,
  VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID = 43,
  ACCRCRegClassID = 44,
  UACCRCRegClassID = 45,
  WACCRCRegClassID = 46,
  WACC_HIRCRegClassID = 47,
  ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 48,
  UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 49,
  ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 50,
  UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 51,
  DMRRCRegClassID = 52,
  DMRpRCRegClassID = 53,

};
} // end namespace PPC


// Subregister indices

namespace PPC {
enum : uint16_t {
  NoSubRegister,
  sub_32, // 1
  sub_32_hi_phony,  // 2
  sub_64, // 3
  sub_dmr0, // 4
  sub_dmr1, // 5
  sub_dmrrow0,  // 6
  sub_dmrrow1,  // 7
  sub_dmrrowp0, // 8
  sub_dmrrowp1, // 9
  sub_eq, // 10
  sub_fp0,  // 11
  sub_fp1,  // 12
  sub_gp8_x0, // 13
  sub_gp8_x1, // 14
  sub_gt, // 15
  sub_lt, // 16
  sub_pair0,  // 17
  sub_pair1,  // 18
  sub_un, // 19
  sub_vsx0, // 20
  sub_vsx1, // 21
  sub_wacc_hi,  // 22
  sub_wacc_lo,  // 23
  sub_vsx1_then_sub_64, // 24
  sub_pair1_then_sub_64,  // 25
  sub_pair1_then_sub_vsx0,  // 26
  sub_pair1_then_sub_vsx1,  // 27
  sub_pair1_then_sub_vsx1_then_sub_64,  // 28
  sub_dmrrowp1_then_sub_dmrrow0,  // 29
  sub_dmrrowp1_then_sub_dmrrow1,  // 30
  sub_wacc_hi_then_sub_dmrrow0, // 31
  sub_wacc_hi_then_sub_dmrrow1, // 32
  sub_wacc_hi_then_sub_dmrrowp0,  // 33
  sub_wacc_hi_then_sub_dmrrowp1,  // 34
  sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 35
  sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 36
  sub_dmr1_then_sub_dmrrow0,  // 37
  sub_dmr1_then_sub_dmrrow1,  // 38
  sub_dmr1_then_sub_dmrrowp0, // 39
  sub_dmr1_then_sub_dmrrowp1, // 40
  sub_dmr1_then_sub_wacc_hi,  // 41
  sub_dmr1_then_sub_wacc_lo,  // 42
  sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0,  // 43
  sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1,  // 44
  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, // 45
  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, // 46
  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0,  // 47
  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1,  // 48
  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 49
  sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 50
  sub_gp8_x1_then_sub_32, // 51
  NUM_TARGET_SUBREGS
};
} // end namespace PPC

// Register pressure sets enum.
namespace PPC {
enum RegisterPressureSets {
  CARRYRC = 0,
  VRSAVERC = 1,
  SPILLTOVSRRC_and_F4RC = 2,
  SPILLTOVSRRC_and_VFRC = 3,
  CRBITRC = 4,
  F4RC = 5,
  VFRC = 6,
  WACCRC = 7,
  WACC_HIRC = 8,
  GPRC = 9,
  SPILLTOVSRRC_and_VSFRC = 10,
  SPILLTOVSRRC_and_VSFRC_with_VFRC = 11,
  F4RC_with_SPILLTOVSRRC_and_VSFRC = 12,
  VSSRC = 13,
  DMRROWRC = 14,
  SPILLTOVSRRC = 15,
  SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC = 16,
  SPILLTOVSRRC_with_VFRC = 17,
  F4RC_with_SPILLTOVSRRC = 18,
  VSSRC_with_SPILLTOVSRRC = 19,
};
} // end namespace PPC

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t PPCRegDiffLists[] = {
  /* 0 */ -504, 0,
  /* 2 */ -496, 0,
  /* 4 */ -489, 0,
  /* 6 */ -488, 0,
  /* 8 */ -480, 0,
  /* 10 */ -65, -248, 249, -248, 0,
  /* 15 */ -64, -248, 249, -248, 0,
  /* 20 */ -63, -248, 249, -248, 0,
  /* 25 */ -62, -248, 249, -248, 0,
  /* 30 */ -61, -248, 249, -248, 0,
  /* 35 */ -60, -248, 249, -248, 0,
  /* 40 */ -59, -248, 249, -248, 0,
  /* 45 */ -58, -248, 249, -248, 0,
  /* 50 */ -57, -248, 249, -248, 0,
  /* 55 */ -56, -248, 249, -248, 0,
  /* 60 */ -55, -248, 249, -248, 0,
  /* 65 */ -54, -248, 249, -248, 0,
  /* 70 */ -53, -248, 249, -248, 0,
  /* 75 */ -52, -248, 249, -248, 0,
  /* 80 */ -51, -248, 249, -248, 0,
  /* 85 */ -50, -248, 249, -248, 0,
  /* 90 */ -32, -218, 219, -218, 0,
  /* 95 */ 104, -32, -218, 219, -218, 250, -31, -218, 219, -218, 0,
  /* 106 */ 376, -32, -218, 219, -218, 250, -31, -218, 219, -218, 0,
  /* 117 */ -30, -218, 219, -218, 0,
  /* 122 */ 105, -30, -218, 219, -218, 248, -29, -218, 219, -218, 0,
  /* 133 */ 377, -30, -218, 219, -218, 248, -29, -218, 219, -218, 0,
  /* 144 */ -28, -218, 219, -218, 0,
  /* 149 */ 106, -28, -218, 219, -218, 246, -27, -218, 219, -218, 0,
  /* 160 */ 378, -28, -218, 219, -218, 246, -27, -218, 219, -218, 0,
  /* 171 */ -26, -218, 219, -218, 0,
  /* 176 */ 107, -26, -218, 219, -218, 244, -25, -218, 219, -218, 0,
  /* 187 */ 379, -26, -218, 219, -218, 244, -25, -218, 219, -218, 0,
  /* 198 */ -24, -218, 219, -218, 0,
  /* 203 */ 108, -24, -218, 219, -218, 242, -23, -218, 219, -218, 0,
  /* 214 */ 380, -24, -218, 219, -218, 242, -23, -218, 219, -218, 0,
  /* 225 */ -22, -218, 219, -218, 0,
  /* 230 */ 109, -22, -218, 219, -218, 240, -21, -218, 219, -218, 0,
  /* 241 */ 381, -22, -218, 219, -218, 240, -21, -218, 219, -218, 0,
  /* 252 */ -20, -218, 219, -218, 0,
  /* 257 */ 110, -20, -218, 219, -218, 238, -19, -218, 219, -218, 0,
  /* 268 */ 382, -20, -218, 219, -218, 238, -19, -218, 219, -218, 0,
  /* 279 */ -18, -218, 219, -218, 0,
  /* 284 */ 111, -18, -218, 219, -218, 236, -17, -218, 219, -218, 0,
  /* 295 */ 383, -18, -218, 219, -218, 236, -17, -218, 219, -218, 0,
  /* 306 */ -165, 0,
  /* 308 */ -32, -33, 0,
  /* 311 */ -18, 0,
  /* 313 */ -64, 1, 0,
  /* 316 */ -350, -64, 1, 64, -63, 1, 0,
  /* 323 */ -62, 1, 0,
  /* 326 */ 422, -350, -64, 1, 64, -63, 1, 419, -356, -62, 1, 62, -61, 1, 0,
  /* 341 */ -60, 1, 0,
  /* 344 */ -347, -60, 1, 60, -59, 1, 0,
  /* 351 */ -58, 1, 0,
  /* 354 */ -104, 422, -350, -64, 1, 64, -63, 1, 419, -356, -62, 1, 62, -61, 1, -14, 422, -347, -60, 1, 60, -59, 1, 412, -353, -58, 1, 58, -57, 1, 0,
  /* 385 */ -56, 1, 0,
  /* 388 */ -344, -56, 1, 56, -55, 1, 0,
  /* 395 */ -54, 1, 0,
  /* 398 */ 422, -344, -56, 1, 56, -55, 1, 405, -350, -54, 1, 54, -53, 1, 0,
  /* 413 */ -52, 1, 0,
  /* 416 */ -341, -52, 1, 52, -51, 1, 0,
  /* 423 */ -50, 1, 0,
  /* 426 */ -103, 422, -344, -56, 1, 56, -55, 1, 405, -350, -54, 1, 54, -53, 1, -28, 422, -341, -52, 1, 52, -51, 1, 398, -347, -50, 1, 50, -49, 1, 0,
  /* 457 */ -48, 1, 0,
  /* 460 */ -338, -48, 1, 48, -47, 1, 0,
  /* 467 */ -46, 1, 0,
  /* 470 */ 422, -338, -48, 1, 48, -47, 1, 391, -344, -46, 1, 46, -45, 1, 0,
  /* 485 */ -44, 1, 0,
  /* 488 */ -335, -44, 1, 44, -43, 1, 0,
  /* 495 */ -42, 1, 0,
  /* 498 */ -102, 422, -338, -48, 1, 48, -47, 1, 391, -344, -46, 1, 46, -45, 1, -42, 422, -335, -44, 1, 44, -43, 1, 384, -341, -42, 1, 42, -41, 1, 0,
  /* 529 */ -40, 1, 0,
  /* 532 */ -332, -40, 1, 40, -39, 1, 0,
  /* 539 */ -38, 1, 0,
  /* 542 */ 422, -332, -40, 1, 40, -39, 1, 377, -338, -38, 1, 38, -37, 1, 0,
  /* 557 */ -36, 1, 0,
  /* 560 */ -329, -36, 1, 36, -35, 1, 0,
  /* 567 */ -34, 1, 0,
  /* 570 */ -101, 422, -332, -40, 1, 40, -39, 1, 377, -338, -38, 1, 38, -37, 1, -56, 422, -329, -36, 1, 36, -35, 1, 370, -335, -34, 1, 34, -33, 1, 0,
  /* 601 */ -32, 1, 0,
  /* 604 */ -31, 1, 0,
  /* 607 */ -30, 1, 0,
  /* 610 */ -29, 1, 0,
  /* 613 */ -28, 1, 0,
  /* 616 */ -27, 1, 0,
  /* 619 */ -26, 1, 0,
  /* 622 */ -25, 1, 0,
  /* 625 */ -24, 1, 0,
  /* 628 */ -23, 1, 0,
  /* 631 */ -22, 1, 0,
  /* 634 */ -21, 1, 0,
  /* 637 */ -20, 1, 0,
  /* 640 */ -19, 1, 0,
  /* 643 */ -18, 1, 0,
  /* 646 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
  /* 662 */ 18, 0,
  /* 664 */ 496, -8, -8, 24, 0,
  /* 669 */ -112, 32, -31, 32, 0,
  /* 674 */ -111, 32, -31, 32, 0,
  /* 679 */ -110, 32, -31, 32, 0,
  /* 684 */ -109, 32, -31, 32, 0,
  /* 689 */ -108, 32, -31, 32, 0,
  /* 694 */ -107, 32, -31, 32, 0,
  /* 699 */ -106, 32, -31, 32, 0,
  /* 704 */ -105, 32, -31, 32, 0,
  /* 709 */ -104, 32, -31, 32, 0,
  /* 714 */ -103, 32, -31, 32, 0,
  /* 719 */ -102, 32, -31, 32, 0,
  /* 724 */ -101, 32, -31, 32, 0,
  /* 729 */ -100, 32, -31, 32, 0,
  /* 734 */ -99, 32, -31, 32, 0,
  /* 739 */ -98, 32, -31, 32, 0,
  /* 744 */ -97, 32, -31, 32, 0,
  /* 749 */ 32, 216, 49, 0,
  /* 753 */ 32, 216, 50, 0,
  /* 757 */ 32, 216, 51, 0,
  /* 761 */ 32, 216, 52, 0,
  /* 765 */ 32, 216, 53, 0,
  /* 769 */ 32, 216, 54, 0,
  /* 773 */ 32, 216, 55, 0,
  /* 777 */ 32, 216, 56, 0,
  /* 781 */ 32, 216, 57, 0,
  /* 785 */ 32, 216, 58, 0,
  /* 789 */ 32, 216, 59, 0,
  /* 793 */ 32, 216, 60, 0,
  /* 797 */ 32, 216, 61, 0,
  /* 801 */ 32, 216, 62, 0,
  /* 805 */ 32, 216, 63, 0,
  /* 809 */ 32, 216, 64, 0,
  /* 813 */ 32, 216, 65, 0,
  /* 817 */ -32, 96, 0,
  /* 820 */ -32, 97, 0,
  /* 823 */ -32, 98, 0,
  /* 826 */ -32, 99, 0,
  /* 829 */ 32, 334, -430, 100, 0,
  /* 834 */ 33, 334, -430, 100, 0,
  /* 839 */ 33, 335, -430, 100, 0,
  /* 844 */ 34, 335, -430, 100, 0,
  /* 849 */ 34, 328, -422, 100, 0,
  /* 854 */ 35, 328, -422, 100, 0,
  /* 859 */ 35, 329, -422, 100, 0,
  /* 864 */ 36, 329, -422, 100, 0,
  /* 869 */ -32, 100, 0,
  /* 872 */ 36, 337, -430, 101, 0,
  /* 877 */ 37, 337, -430, 101, 0,
  /* 882 */ 37, 338, -430, 101, 0,
  /* 887 */ 38, 338, -430, 101, 0,
  /* 892 */ 40, 340, -430, 101, 0,
  /* 897 */ 41, 340, -430, 101, 0,
  /* 902 */ 41, 341, -430, 101, 0,
  /* 907 */ 42, 341, -430, 101, 0,
  /* 912 */ 38, 331, -422, 101, 0,
  /* 917 */ 39, 331, -422, 101, 0,
  /* 922 */ 39, 332, -422, 101, 0,
  /* 927 */ 40, 332, -422, 101, 0,
  /* 932 */ 42, 334, -422, 101, 0,
  /* 937 */ 43, 334, -422, 101, 0,
  /* 942 */ 43, 335, -422, 101, 0,
  /* 947 */ 44, 335, -422, 101, 0,
  /* 952 */ -32, 101, 0,
  /* 955 */ 44, 343, -430, 102, 0,
  /* 960 */ 45, 343, -430, 102, 0,
  /* 965 */ 45, 344, -430, 102, 0,
  /* 970 */ 46, 344, -430, 102, 0,
  /* 975 */ 48, 346, -430, 102, 0,
  /* 980 */ 49, 346, -430, 102, 0,
  /* 985 */ 49, 347, -430, 102, 0,
  /* 990 */ 50, 347, -430, 102, 0,
  /* 995 */ 46, 337, -422, 102, 0,
  /* 1000 */ 47, 337, -422, 102, 0,
  /* 1005 */ 47, 338, -422, 102, 0,
  /* 1010 */ 48, 338, -422, 102, 0,
  /* 1015 */ 50, 340, -422, 102, 0,
  /* 1020 */ 51, 340, -422, 102, 0,
  /* 1025 */ 51, 341, -422, 102, 0,
  /* 1030 */ 52, 341, -422, 102, 0,
  /* 1035 */ -32, 102, 0,
  /* 1038 */ 52, 349, -430, 103, 0,
  /* 1043 */ 53, 349, -430, 103, 0,
  /* 1048 */ 53, 350, -430, 103, 0,
  /* 1053 */ 54, 350, -430, 103, 0,
  /* 1058 */ 56, 352, -430, 103, 0,
  /* 1063 */ 57, 352, -430, 103, 0,
  /* 1068 */ 57, 353, -430, 103, 0,
  /* 1073 */ 58, 353, -430, 103, 0,
  /* 1078 */ 54, 343, -422, 103, 0,
  /* 1083 */ 55, 343, -422, 103, 0,
  /* 1088 */ 55, 344, -422, 103, 0,
  /* 1093 */ 56, 344, -422, 103, 0,
  /* 1098 */ 58, 346, -422, 103, 0,
  /* 1103 */ 59, 346, -422, 103, 0,
  /* 1108 */ 59, 347, -422, 103, 0,
  /* 1113 */ 60, 347, -422, 103, 0,
  /* 1118 */ -32, 103, 0,
  /* 1121 */ 60, 355, -430, 104, 0,
  /* 1126 */ 61, 355, -430, 104, 0,
  /* 1131 */ 61, 356, -430, 104, 0,
  /* 1136 */ 62, 356, -430, 104, 0,
  /* 1141 */ 62, 349, -422, 104, 0,
  /* 1146 */ 63, 349, -422, 104, 0,
  /* 1151 */ 63, 350, -422, 104, 0,
  /* 1156 */ 64, 350, -422, 104, 0,
  /* 1161 */ -32, 104, 0,
  /* 1164 */ -32, 105, 0,
  /* 1167 */ 218, 16, -384, 167, 105, 0,
  /* 1173 */ 218, 17, -384, 167, 105, 0,
  /* 1179 */ -32, 106, 0,
  /* 1182 */ 218, 17, -383, 166, 106, 0,
  /* 1188 */ 218, 18, -383, 166, 106, 0,
  /* 1194 */ 218, 19, -383, 166, 106, 0,
  /* 1200 */ -32, 107, 0,
  /* 1203 */ 218, 19, -382, 165, 107, 0,
  /* 1209 */ 218, 20, -382, 165, 107, 0,
  /* 1215 */ 218, 21, -382, 165, 107, 0,
  /* 1221 */ -32, 108, 0,
  /* 1224 */ 218, 21, -381, 164, 108, 0,
  /* 1230 */ 218, 22, -381, 164, 108, 0,
  /* 1236 */ 218, 23, -381, 164, 108, 0,
  /* 1242 */ -32, 109, 0,
  /* 1245 */ 218, 23, -380, 163, 109, 0,
  /* 1251 */ 218, 24, -380, 163, 109, 0,
  /* 1257 */ 218, 25, -380, 163, 109, 0,
  /* 1263 */ -32, 110, 0,
  /* 1266 */ 218, 25, -379, 162, 110, 0,
  /* 1272 */ 218, 26, -379, 162, 110, 0,
  /* 1278 */ 218, 27, -379, 162, 110, 0,
  /* 1284 */ -32, 111, 0,
  /* 1287 */ 218, 27, -378, 161, 111, 0,
  /* 1293 */ 218, 28, -378, 161, 111, 0,
  /* 1299 */ 218, 29, -378, 161, 111, 0,
  /* 1305 */ -32, 112, 0,
  /* 1308 */ 218, 29, -377, 160, 112, 0,
  /* 1314 */ 218, 30, -377, 160, 112, 0,
  /* 1320 */ 218, 31, -377, 160, 112, 0,
  /* 1326 */ 218, 31, -376, 159, 113, 0,
  /* 1332 */ 218, 32, -376, 159, 113, 0,
  /* 1338 */ 165, 0,
  /* 1340 */ 16, -384, 272, 0,
  /* 1344 */ 17, -384, 272, 0,
  /* 1348 */ 17, -383, 272, 0,
  /* 1352 */ 18, -383, 272, 0,
  /* 1356 */ 19, -383, 272, 0,
  /* 1360 */ 19, -382, 272, 0,
  /* 1364 */ 20, -382, 272, 0,
  /* 1368 */ 21, -382, 272, 0,
  /* 1372 */ 21, -381, 272, 0,
  /* 1376 */ 22, -381, 272, 0,
  /* 1380 */ 23, -381, 272, 0,
  /* 1384 */ 23, -380, 272, 0,
  /* 1388 */ 24, -380, 272, 0,
  /* 1392 */ 25, -380, 272, 0,
  /* 1396 */ 25, -379, 272, 0,
  /* 1400 */ 26, -379, 272, 0,
  /* 1404 */ 27, -379, 272, 0,
  /* 1408 */ 27, -378, 272, 0,
  /* 1412 */ 28, -378, 272, 0,
  /* 1416 */ 29, -378, 272, 0,
  /* 1420 */ 29, -377, 272, 0,
  /* 1424 */ 30, -377, 272, 0,
  /* 1428 */ 31, -377, 272, 0,
  /* 1432 */ 31, -376, 272, 0,
  /* 1436 */ 32, -376, 272, 0,
  /* 1440 */ 489, 0,
};

extern const LaneBitmask PPCLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
  /* 3 */ LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
  /* 5 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask::getAll(),
  /* 8 */ LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask::getAll(),
  /* 11 */ LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(),
  /* 16 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000800), LaneBitmask::getAll(),
  /* 19 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000800), LaneBitmask(0x0000000000001000), LaneBitmask(0x0000000000002000), LaneBitmask::getAll(),
  /* 24 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask::getAll(),
  /* 29 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask::getAll(),
  /* 38 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000004000), LaneBitmask(0x0000000000008000), LaneBitmask(0x0000000000010000), LaneBitmask(0x0000000000020000), LaneBitmask(0x0000000000040000), LaneBitmask(0x0000000000080000), LaneBitmask(0x0000000000100000), LaneBitmask(0x0000000000200000), LaneBitmask(0x0000000000400000), LaneBitmask(0x0000000000800000), LaneBitmask(0x0000000001000000), LaneBitmask(0x0000000002000000), LaneBitmask(0x0000000004000000), LaneBitmask(0x0000000008000000), LaneBitmask::getAll(),
  /* 55 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000010000000), LaneBitmask::getAll(),
  /* 58 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t PPCSubRegIdxLists[] = {
  /* 0 */ 1, 0,
  /* 2 */ 1, 2, 0,
  /* 5 */ 3, 0,
  /* 7 */ 6, 7, 0,
  /* 10 */ 11, 12, 0,
  /* 13 */ 16, 15, 10, 19, 0,
  /* 18 */ 20, 3, 21, 24, 0,
  /* 23 */ 17, 20, 3, 21, 24, 18, 26, 25, 27, 28, 0,
  /* 34 */ 8, 6, 7, 9, 29, 30, 0,
  /* 41 */ 23, 8, 6, 7, 9, 29, 30, 22, 33, 31, 32, 34, 35, 36, 0,
  /* 56 */ 4, 23, 8, 6, 7, 9, 29, 30, 22, 33, 31, 32, 34, 35, 36, 5, 42, 39, 37, 38, 40, 43, 44, 41, 47, 45, 46, 48, 49, 50, 0,
  /* 87 */ 13, 1, 14, 51, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 32 },  // sub_32
  { 32, 32 }, // sub_32_hi_phony
  { 0, 64 },  // sub_64
  { 0, 1024 },  // sub_dmr0
  { 1024, 1024 }, // sub_dmr1
  { 0, 128 }, // sub_dmrrow0
  { 128, 128 }, // sub_dmrrow1
  { 0, 256 }, // sub_dmrrowp0
  { 256, 256 }, // sub_dmrrowp1
  { 2, 1 }, // sub_eq
  { 0, 64 },  // sub_fp0
  { 64, 64 }, // sub_fp1
  { 0, 64 },  // sub_gp8_x0
  { 64, 64 }, // sub_gp8_x1
  { 1, 1 }, // sub_gt
  { 0, 1 }, // sub_lt
  { 0, 256 }, // sub_pair0
  { 256, 256 }, // sub_pair1
  { 3, 1 }, // sub_un
  { 0, 128 }, // sub_vsx0
  { 128, 128 }, // sub_vsx1
  { 512, 512 }, // sub_wacc_hi
  { 0, 512 }, // sub_wacc_lo
  { 128, 64 },  // sub_vsx1_then_sub_64
  { 256, 64 },  // sub_pair1_then_sub_64
  { 256, 128 }, // sub_pair1_then_sub_vsx0
  { 384, 128 }, // sub_pair1_then_sub_vsx1
  { 384, 64 },  // sub_pair1_then_sub_vsx1_then_sub_64
  { 256, 128 }, // sub_dmrrowp1_then_sub_dmrrow0
  { 384, 128 }, // sub_dmrrowp1_then_sub_dmrrow1
  { 512, 128 }, // sub_wacc_hi_then_sub_dmrrow0
  { 640, 128 }, // sub_wacc_hi_then_sub_dmrrow1
  { 512, 256 }, // sub_wacc_hi_then_sub_dmrrowp0
  { 768, 256 }, // sub_wacc_hi_then_sub_dmrrowp1
  { 768, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
  { 896, 128 }, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
  { 1024, 128 },  // sub_dmr1_then_sub_dmrrow0
  { 1152, 128 },  // sub_dmr1_then_sub_dmrrow1
  { 1024, 256 },  // sub_dmr1_then_sub_dmrrowp0
  { 1280, 256 },  // sub_dmr1_then_sub_dmrrowp1
  { 1536, 512 },  // sub_dmr1_then_sub_wacc_hi
  { 1024, 512 },  // sub_dmr1_then_sub_wacc_lo
  { 1280, 128 },  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
  { 1408, 128 },  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
  { 1536, 128 },  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
  { 1664, 128 },  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
  { 1536, 256 },  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
  { 1792, 256 },  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
  { 1792, 128 },  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
  { 1920, 128 },  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
  { 64, 32 }, // sub_gp8_x1_then_sub_32
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char PPCRegStrings[] = {
  /* 0 */ "VF10\0"
  /* 5 */ "H10\0"
  /* 9 */ "VSL10\0"
  /* 15 */ "R10\0"
  /* 19 */ "S10\0"
  /* 23 */ "V10\0"
  /* 27 */ "DMRROW10\0"
  /* 36 */ "X10\0"
  /* 40 */ "G8p10\0"
  /* 46 */ "VSRp10\0"
  /* 53 */ "DMRROWp10\0"
  /* 63 */ "Fpair10\0"
  /* 71 */ "VF20\0"
  /* 76 */ "H20\0"
  /* 80 */ "VSL20\0"
  /* 86 */ "R20\0"
  /* 90 */ "S20\0"
  /* 94 */ "V20\0"
  /* 98 */ "DMRROW20\0"
  /* 107 */ "X20\0"
  /* 111 */ "VSRp20\0"
  /* 118 */ "DMRROWp20\0"
  /* 128 */ "Fpair20\0"
  /* 136 */ "VF30\0"
  /* 141 */ "H30\0"
  /* 145 */ "VSL30\0"
  /* 151 */ "R30\0"
  /* 155 */ "S30\0"
  /* 159 */ "V30\0"
  /* 163 */ "DMRROW30\0"
  /* 172 */ "X30\0"
  /* 176 */ "VSRp30\0"
  /* 183 */ "DMRROWp30\0"
  /* 193 */ "Fpair30\0"
  /* 201 */ "DMRROW40\0"
  /* 210 */ "VSX40\0"
  /* 216 */ "DMRROW50\0"
  /* 225 */ "VSX50\0"
  /* 231 */ "DMRROW60\0"
  /* 240 */ "VSX60\0"
  /* 246 */ "UACC0\0"
  /* 252 */ "WACC0\0"
  /* 258 */ "VF0\0"
  /* 262 */ "H0\0"
  /* 265 */ "WACC_HI0\0"
  /* 274 */ "VSL0\0"
  /* 279 */ "CR0\0"
  /* 283 */ "DMR0\0"
  /* 288 */ "S0\0"
  /* 291 */ "V0\0"
  /* 294 */ "DMRROW0\0"
  /* 302 */ "X0\0"
  /* 305 */ "G8p0\0"
  /* 310 */ "DMRp0\0"
  /* 316 */ "VSRp0\0"
  /* 322 */ "DMRROWp0\0"
  /* 331 */ "Fpair0\0"
  /* 338 */ "VF11\0"
  /* 343 */ "H11\0"
  /* 347 */ "VSL11\0"
  /* 353 */ "R11\0"
  /* 357 */ "S11\0"
  /* 361 */ "V11\0"
  /* 365 */ "DMRROW11\0"
  /* 374 */ "X11\0"
  /* 378 */ "G8p11\0"
  /* 384 */ "VSRp11\0"
  /* 391 */ "DMRROWp11\0"
  /* 401 */ "VF21\0"
  /* 406 */ "H21\0"
  /* 410 */ "VSL21\0"
  /* 416 */ "R21\0"
  /* 420 */ "S21\0"
  /* 424 */ "V21\0"
  /* 428 */ "DMRROW21\0"
  /* 437 */ "X21\0"
  /* 441 */ "VSRp21\0"
  /* 448 */ "DMRROWp21\0"
  /* 458 */ "VF31\0"
  /* 463 */ "H31\0"
  /* 467 */ "VSL31\0"
  /* 473 */ "R31\0"
  /* 477 */ "S31\0"
  /* 481 */ "V31\0"
  /* 485 */ "DMRROW31\0"
  /* 494 */ "X31\0"
  /* 498 */ "VSRp31\0"
  /* 505 */ "DMRROWp31\0"
  /* 515 */ "DMRROW41\0"
  /* 524 */ "VSX41\0"
  /* 530 */ "DMRROW51\0"
  /* 539 */ "VSX51\0"
  /* 545 */ "DMRROW61\0"
  /* 554 */ "VSX61\0"
  /* 560 */ "UACC1\0"
  /* 566 */ "WACC1\0"
  /* 572 */ "VF1\0"
  /* 576 */ "H1\0"
  /* 579 */ "WACC_HI1\0"
  /* 588 */ "VSL1\0"
  /* 593 */ "CR1\0"
  /* 597 */ "DMR1\0"
  /* 602 */ "S1\0"
  /* 605 */ "V1\0"
  /* 608 */ "DMRROW1\0"
  /* 616 */ "X1\0"
  /* 619 */ "G8p1\0"
  /* 624 */ "DMRp1\0"
  /* 630 */ "VSRp1\0"
  /* 636 */ "DMRROWp1\0"
  /* 645 */ "VF12\0"
  /* 650 */ "H12\0"
  /* 654 */ "VSL12\0"
  /* 660 */ "R12\0"
  /* 664 */ "S12\0"
  /* 668 */ "V12\0"
  /* 672 */ "DMRROW12\0"
  /* 681 */ "X12\0"
  /* 685 */ "G8p12\0"
  /* 691 */ "VSRp12\0"
  /* 698 */ "DMRROWp12\0"
  /* 708 */ "Fpair12\0"
  /* 716 */ "VF22\0"
  /* 721 */ "H22\0"
  /* 725 */ "VSL22\0"
  /* 731 */ "R22\0"
  /* 735 */ "S22\0"
  /* 739 */ "V22\0"
  /* 743 */ "DMRROW22\0"
  /* 752 */ "X22\0"
  /* 756 */ "VSRp22\0"
  /* 763 */ "DMRROWp22\0"
  /* 773 */ "Fpair22\0"
  /* 781 */ "DMRROW32\0"
  /* 790 */ "VSX32\0"
  /* 796 */ "DMRROW42\0"
  /* 805 */ "VSX42\0"
  /* 811 */ "DMRROW52\0"
  /* 820 */ "VSX52\0"
  /* 826 */ "DMRROW62\0"
  /* 835 */ "VSX62\0"
  /* 841 */ "UACC2\0"
  /* 847 */ "WACC2\0"
  /* 853 */ "VF2\0"
  /* 857 */ "H2\0"
  /* 860 */ "WACC_HI2\0"
  /* 869 */ "VSL2\0"
  /* 874 */ "CR2\0"
  /* 878 */ "DMR2\0"
  /* 883 */ "S2\0"
  /* 886 */ "V2\0"
  /* 889 */ "DMRROW2\0"
  /* 897 */ "X2\0"
  /* 900 */ "G8p2\0"
  /* 905 */ "DMRp2\0"
  /* 911 */ "VSRp2\0"
  /* 917 */ "DMRROWp2\0"
  /* 926 */ "Fpair2\0"
  /* 933 */ "VF13\0"
  /* 938 */ "H13\0"
  /* 942 */ "VSL13\0"
  /* 948 */ "R13\0"
  /* 952 */ "S13\0"
  /* 956 */ "V13\0"
  /* 960 */ "DMRROW13\0"
  /* 969 */ "X13\0"
  /* 973 */ "G8p13\0"
  /* 979 */ "VSRp13\0"
  /* 986 */ "DMRROWp13\0"
  /* 996 */ "VF23\0"
  /* 1001 */ "H23\0"
  /* 1005 */ "VSL23\0"
  /* 1011 */ "R23\0"
  /* 1015 */ "S23\0"
  /* 1019 */ "V23\0"
  /* 1023 */ "DMRROW23\0"
  /* 1032 */ "X23\0"
  /* 1036 */ "VSRp23\0"
  /* 1043 */ "DMRROWp23\0"
  /* 1053 */ "DMRROW33\0"
  /* 1062 */ "VSX33\0"
  /* 1068 */ "DMRROW43\0"
  /* 1077 */ "VSX43\0"
  /* 1083 */ "DMRROW53\0"
  /* 1092 */ "VSX53\0"
  /* 1098 */ "DMRROW63\0"
  /* 1107 */ "VSX63\0"
  /* 1113 */ "UACC3\0"
  /* 1119 */ "WACC3\0"
  /* 1125 */ "VF3\0"
  /* 1129 */ "H3\0"
  /* 1132 */ "WACC_HI3\0"
  /* 1141 */ "VSL3\0"
  /* 1146 */ "CR3\0"
  /* 1150 */ "DMR3\0"
  /* 1155 */ "S3\0"
  /* 1158 */ "V3\0"
  /* 1161 */ "DMRROW3\0"
  /* 1169 */ "X3\0"
  /* 1172 */ "G8p3\0"
  /* 1177 */ "DMRp3\0"
  /* 1183 */ "VSRp3\0"
  /* 1189 */ "DMRROWp3\0"
  /* 1198 */ "VF14\0"
  /* 1203 */ "H14\0"
  /* 1207 */ "VSL14\0"
  /* 1213 */ "R14\0"
  /* 1217 */ "S14\0"
  /* 1221 */ "V14\0"
  /* 1225 */ "DMRROW14\0"
  /* 1234 */ "X14\0"
  /* 1238 */ "G8p14\0"
  /* 1244 */ "VSRp14\0"
  /* 1251 */ "DMRROWp14\0"
  /* 1261 */ "Fpair14\0"
  /* 1269 */ "VF24\0"
  /* 1274 */ "H24\0"
  /* 1278 */ "VSL24\0"
  /* 1284 */ "R24\0"
  /* 1288 */ "S24\0"
  /* 1292 */ "V24\0"
  /* 1296 */ "DMRROW24\0"
  /* 1305 */ "X24\0"
  /* 1309 */ "VSRp24\0"
  /* 1316 */ "DMRROWp24\0"
  /* 1326 */ "Fpair24\0"
  /* 1334 */ "DMRROW34\0"
  /* 1343 */ "VSX34\0"
  /* 1349 */ "DMRROW44\0"
  /* 1358 */ "VSX44\0"
  /* 1364 */ "DMRROW54\0"
  /* 1373 */ "VSX54\0"
  /* 1379 */ "UACC4\0"
  /* 1385 */ "WACC4\0"
  /* 1391 */ "VF4\0"
  /* 1395 */ "H4\0"
  /* 1398 */ "WACC_HI4\0"
  /* 1407 */ "VSL4\0"
  /* 1412 */ "CR4\0"
  /* 1416 */ "DMR4\0"
  /* 1421 */ "S4\0"
  /* 1424 */ "V4\0"
  /* 1427 */ "DMRROW4\0"
  /* 1435 */ "X4\0"
  /* 1438 */ "G8p4\0"
  /* 1443 */ "VSRp4\0"
  /* 1449 */ "DMRROWp4\0"
  /* 1458 */ "Fpair4\0"
  /* 1465 */ "VF15\0"
  /* 1470 */ "H15\0"
  /* 1474 */ "VSL15\0"
  /* 1480 */ "R15\0"
  /* 1484 */ "S15\0"
  /* 1488 */ "V15\0"
  /* 1492 */ "DMRROW15\0"
  /* 1501 */ "X15\0"
  /* 1505 */ "G8p15\0"
  /* 1511 */ "VSRp15\0"
  /* 1518 */ "DMRROWp15\0"
  /* 1528 */ "VF25\0"
  /* 1533 */ "H25\0"
  /* 1537 */ "VSL25\0"
  /* 1543 */ "R25\0"
  /* 1547 */ "S25\0"
  /* 1551 */ "V25\0"
  /* 1555 */ "DMRROW25\0"
  /* 1564 */ "X25\0"
  /* 1568 */ "VSRp25\0"
  /* 1575 */ "DMRROWp25\0"
  /* 1585 */ "DMRROW35\0"
  /* 1594 */ "VSX35\0"
  /* 1600 */ "DMRROW45\0"
  /* 1609 */ "VSX45\0"
  /* 1615 */ "DMRROW55\0"
  /* 1624 */ "VSX55\0"
  /* 1630 */ "UACC5\0"
  /* 1636 */ "WACC5\0"
  /* 1642 */ "VF5\0"
  /* 1646 */ "H5\0"
  /* 1649 */ "WACC_HI5\0"
  /* 1658 */ "VSL5\0"
  /* 1663 */ "CR5\0"
  /* 1667 */ "DMR5\0"
  /* 1672 */ "S5\0"
  /* 1675 */ "V5\0"
  /* 1678 */ "DMRROW5\0"
  /* 1686 */ "X5\0"
  /* 1689 */ "G8p5\0"
  /* 1694 */ "VSRp5\0"
  /* 1700 */ "DMRROWp5\0"
  /* 1709 */ "VF16\0"
  /* 1714 */ "H16\0"
  /* 1718 */ "VSL16\0"
  /* 1724 */ "R16\0"
  /* 1728 */ "S16\0"
  /* 1732 */ "V16\0"
  /* 1736 */ "DMRROW16\0"
  /* 1745 */ "X16\0"
  /* 1749 */ "VSRp16\0"
  /* 1756 */ "DMRROWp16\0"
  /* 1766 */ "Fpair16\0"
  /* 1774 */ "VF26\0"
  /* 1779 */ "H26\0"
  /* 1783 */ "VSL26\0"
  /* 1789 */ "R26\0"
  /* 1793 */ "S26\0"
  /* 1797 */ "V26\0"
  /* 1801 */ "DMRROW26\0"
  /* 1810 */ "X26\0"
  /* 1814 */ "VSRp26\0"
  /* 1821 */ "DMRROWp26\0"
  /* 1831 */ "Fpair26\0"
  /* 1839 */ "DMRROW36\0"
  /* 1848 */ "VSX36\0"
  /* 1854 */ "DMRROW46\0"
  /* 1863 */ "VSX46\0"
  /* 1869 */ "DMRROW56\0"
  /* 1878 */ "VSX56\0"
  /* 1884 */ "UACC6\0"
  /* 1890 */ "WACC6\0"
  /* 1896 */ "VF6\0"
  /* 1900 */ "H6\0"
  /* 1903 */ "WACC_HI6\0"
  /* 1912 */ "VSL6\0"
  /* 1917 */ "CR6\0"
  /* 1921 */ "DMR6\0"
  /* 1926 */ "S6\0"
  /* 1929 */ "V6\0"
  /* 1932 */ "DMRROW6\0"
  /* 1940 */ "X6\0"
  /* 1943 */ "G8p6\0"
  /* 1948 */ "VSRp6\0"
  /* 1954 */ "DMRROWp6\0"
  /* 1963 */ "Fpair6\0"
  /* 1970 */ "VF17\0"
  /* 1975 */ "H17\0"
  /* 1979 */ "VSL17\0"
  /* 1985 */ "R17\0"
  /* 1989 */ "S17\0"
  /* 1993 */ "V17\0"
  /* 1997 */ "DMRROW17\0"
  /* 2006 */ "X17\0"
  /* 2010 */ "VSRp17\0"
  /* 2017 */ "DMRROWp17\0"
  /* 2027 */ "VF27\0"
  /* 2032 */ "H27\0"
  /* 2036 */ "VSL27\0"
  /* 2042 */ "R27\0"
  /* 2046 */ "S27\0"
  /* 2050 */ "V27\0"
  /* 2054 */ "DMRROW27\0"
  /* 2063 */ "X27\0"
  /* 2067 */ "VSRp27\0"
  /* 2074 */ "DMRROWp27\0"
  /* 2084 */ "DMRROW37\0"
  /* 2093 */ "VSX37\0"
  /* 2099 */ "DMRROW47\0"
  /* 2108 */ "VSX47\0"
  /* 2114 */ "DMRROW57\0"
  /* 2123 */ "VSX57\0"
  /* 2129 */ "UACC7\0"
  /* 2135 */ "WACC7\0"
  /* 2141 */ "VF7\0"
  /* 2145 */ "H7\0"
  /* 2148 */ "WACC_HI7\0"
  /* 2157 */ "VSL7\0"
  /* 2162 */ "CR7\0"
  /* 2166 */ "DMR7\0"
  /* 2171 */ "S7\0"
  /* 2174 */ "V7\0"
  /* 2177 */ "DMRROW7\0"
  /* 2185 */ "X7\0"
  /* 2188 */ "G8p7\0"
  /* 2193 */ "VSRp7\0"
  /* 2199 */ "DMRROWp7\0"
  /* 2208 */ "VF18\0"
  /* 2213 */ "H18\0"
  /* 2217 */ "VSL18\0"
  /* 2223 */ "R18\0"
  /* 2227 */ "S18\0"
  /* 2231 */ "V18\0"
  /* 2235 */ "DMRROW18\0"
  /* 2244 */ "X18\0"
  /* 2248 */ "VSRp18\0"
  /* 2255 */ "DMRROWp18\0"
  /* 2265 */ "Fpair18\0"
  /* 2273 */ "VF28\0"
  /* 2278 */ "H28\0"
  /* 2282 */ "VSL28\0"
  /* 2288 */ "R28\0"
  /* 2292 */ "S28\0"
  /* 2296 */ "V28\0"
  /* 2300 */ "DMRROW28\0"
  /* 2309 */ "X28\0"
  /* 2313 */ "VSRp28\0"
  /* 2320 */ "DMRROWp28\0"
  /* 2330 */ "Fpair28\0"
  /* 2338 */ "DMRROW38\0"
  /* 2347 */ "VSX38\0"
  /* 2353 */ "DMRROW48\0"
  /* 2362 */ "VSX48\0"
  /* 2368 */ "DMRROW58\0"
  /* 2377 */ "VSX58\0"
  /* 2383 */ "VF8\0"
  /* 2387 */ "H8\0"
  /* 2390 */ "VSL8\0"
  /* 2395 */ "ZERO8\0"
  /* 2401 */ "BP8\0"
  /* 2405 */ "FP8\0"
  /* 2409 */ "LR8\0"
  /* 2413 */ "CTR8\0"
  /* 2418 */ "S8\0"
  /* 2421 */ "V8\0"
  /* 2424 */ "DMRROW8\0"
  /* 2432 */ "X8\0"
  /* 2435 */ "G8p8\0"
  /* 2440 */ "VSRp8\0"
  /* 2446 */ "DMRROWp8\0"
  /* 2455 */ "Fpair8\0"
  /* 2462 */ "VF19\0"
  /* 2467 */ "H19\0"
  /* 2471 */ "VSL19\0"
  /* 2477 */ "R19\0"
  /* 2481 */ "S19\0"
  /* 2485 */ "V19\0"
  /* 2489 */ "DMRROW19\0"
  /* 2498 */ "X19\0"
  /* 2502 */ "VSRp19\0"
  /* 2509 */ "DMRROWp19\0"
  /* 2519 */ "VF29\0"
  /* 2524 */ "H29\0"
  /* 2528 */ "VSL29\0"
  /* 2534 */ "R29\0"
  /* 2538 */ "S29\0"
  /* 2542 */ "V29\0"
  /* 2546 */ "DMRROW29\0"
  /* 2555 */ "X29\0"
  /* 2559 */ "VSRp29\0"
  /* 2566 */ "DMRROWp29\0"
  /* 2576 */ "DMRROW39\0"
  /* 2585 */ "VSX39\0"
  /* 2591 */ "DMRROW49\0"
  /* 2600 */ "VSX49\0"
  /* 2606 */ "DMRROW59\0"
  /* 2615 */ "VSX59\0"
  /* 2621 */ "VF9\0"
  /* 2625 */ "H9\0"
  /* 2628 */ "VSL9\0"
  /* 2633 */ "R9\0"
  /* 2636 */ "S9\0"
  /* 2639 */ "V9\0"
  /* 2642 */ "DMRROW9\0"
  /* 2650 */ "X9\0"
  /* 2653 */ "G8p9\0"
  /* 2658 */ "VSRp9\0"
  /* 2664 */ "DMRROWp9\0"
  /* 2673 */ "VRSAVE\0"
  /* 2680 */ "RM\0"
  /* 2683 */ "CR0UN\0"
  /* 2689 */ "CR1UN\0"
  /* 2695 */ "CR2UN\0"
  /* 2701 */ "CR3UN\0"
  /* 2707 */ "CR4UN\0"
  /* 2713 */ "CR5UN\0"
  /* 2719 */ "CR6UN\0"
  /* 2725 */ "CR7UN\0"
  /* 2731 */ "ZERO\0"
  /* 2736 */ "BP\0"
  /* 2739 */ "FP\0"
  /* 2742 */ "CR0EQ\0"
  /* 2748 */ "CR1EQ\0"
  /* 2754 */ "CR2EQ\0"
  /* 2760 */ "CR3EQ\0"
  /* 2766 */ "CR4EQ\0"
  /* 2772 */ "CR5EQ\0"
  /* 2778 */ "CR6EQ\0"
  /* 2784 */ "CR7EQ\0"
  /* 2790 */ "SPEFSCR\0"
  /* 2798 */ "XER\0"
  /* 2802 */ "LR\0"
  /* 2805 */ "CTR\0"
  /* 2809 */ "CR0GT\0"
  /* 2815 */ "CR1GT\0"
  /* 2821 */ "CR2GT\0"
  /* 2827 */ "CR3GT\0"
  /* 2833 */ "CR4GT\0"
  /* 2839 */ "CR5GT\0"
  /* 2845 */ "CR6GT\0"
  /* 2851 */ "CR7GT\0"
  /* 2857 */ "CR0LT\0"
  /* 2863 */ "CR1LT\0"
  /* 2869 */ "CR2LT\0"
  /* 2875 */ "CR3LT\0"
  /* 2881 */ "CR4LT\0"
  /* 2887 */ "CR5LT\0"
  /* 2893 */ "CR6LT\0"
  /* 2899 */ "CR7LT\0"
  /* 2905 */ "CARRY\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc PPCRegDesc[] = { // Descriptors
  { 4, 0, 0, 0, 0, 0 },
  { 2736, 1, 662, 1, 4096, 58 },
  { 2905, 1, 1, 1, 4097, 58 },
  { 2805, 1, 1, 1, 4098, 58 },
  { 2739, 1, 1338, 1, 4099, 58 },
  { 2802, 1, 1, 1, 4100, 58 },
  { 2680, 1, 1, 1, 4101, 58 },
  { 2790, 1, 1, 1, 4102, 58 },
  { 2673, 1, 1, 1, 4103, 58 },
  { 2798, 1, 1, 1, 4097, 58 },
  { 2731, 1, 1440, 1, 4104, 58 },
  { 247, 106, 1, 23, 2695177, 19 },
  { 561, 133, 1, 23, 2695181, 19 },
  { 842, 160, 1, 23, 2695185, 19 },
  { 1114, 187, 1, 23, 2695189, 19 },
  { 1380, 214, 1, 23, 2695193, 19 },
  { 1631, 241, 1, 23, 2695197, 19 },
  { 1885, 268, 1, 23, 2695201, 19 },
  { 2130, 295, 1, 23, 2695205, 19 },
  { 2401, 311, 1, 0, 4096, 1 },
  { 279, 664, 1, 13, 2695209, 11 },
  { 593, 664, 1, 13, 2695213, 11 },
  { 874, 664, 1, 13, 2695217, 11 },
  { 1146, 664, 1, 13, 2695221, 11 },
  { 1412, 664, 1, 13, 2695225, 11 },
  { 1663, 664, 1, 13, 2695229, 11 },
  { 1917, 664, 1, 13, 2695233, 11 },
  { 2162, 664, 1, 13, 2695237, 11 },
  { 2413, 1, 1, 1, 4098, 58 },
  { 283, 326, 1124, 41, 2678857, 29 },
  { 597, 370, 1041, 41, 2678865, 29 },
  { 878, 398, 1041, 41, 2678873, 29 },
  { 1150, 442, 958, 41, 2678881, 29 },
  { 1416, 470, 958, 41, 2678889, 29 },
  { 1667, 514, 875, 41, 2678897, 29 },
  { 1921, 542, 875, 41, 2678905, 29 },
  { 2166, 586, 832, 41, 2678913, 29 },
  { 294, 1, 1156, 1, 4169, 58 },
  { 608, 1, 1151, 1, 4170, 58 },
  { 889, 1, 1146, 1, 4171, 58 },
  { 1161, 1, 1141, 1, 4172, 58 },
  { 1427, 1, 1136, 1, 4173, 58 },
  { 1678, 1, 1131, 1, 4174, 58 },
  { 1932, 1, 1126, 1, 4175, 58 },
  { 2177, 1, 1121, 1, 4176, 58 },
  { 2424, 1, 1113, 1, 4177, 58 },
  { 2642, 1, 1108, 1, 4178, 58 },
  { 27, 1, 1103, 1, 4179, 58 },
  { 365, 1, 1098, 1, 4180, 58 },
  { 672, 1, 1073, 1, 4181, 58 },
  { 960, 1, 1068, 1, 4182, 58 },
  { 1225, 1, 1063, 1, 4183, 58 },
  { 1492, 1, 1058, 1, 4184, 58 },
  { 1736, 1, 1093, 1, 4185, 58 },
  { 1997, 1, 1088, 1, 4186, 58 },
  { 2235, 1, 1083, 1, 4187, 58 },
  { 2489, 1, 1078, 1, 4188, 58 },
  { 98, 1, 1053, 1, 4189, 58 },
  { 428, 1, 1048, 1, 4190, 58 },
  { 743, 1, 1043, 1, 4191, 58 },
  { 1023, 1, 1038, 1, 4192, 58 },
  { 1296, 1, 1030, 1, 4193, 58 },
  { 1555, 1, 1025, 1, 4194, 58 },
  { 1801, 1, 1020, 1, 4195, 58 },
  { 2054, 1, 1015, 1, 4196, 58 },
  { 2300, 1, 990, 1, 4197, 58 },
  { 2546, 1, 985, 1, 4198, 58 },
  { 163, 1, 980, 1, 4199, 58 },
  { 485, 1, 975, 1, 4200, 58 },
  { 781, 1, 1010, 1, 4201, 58 },
  { 1053, 1, 1005, 1, 4202, 58 },
  { 1334, 1, 1000, 1, 4203, 58 },
  { 1585, 1, 995, 1, 4204, 58 },
  { 1839, 1, 970, 1, 4205, 58 },
  { 2084, 1, 965, 1, 4206, 58 },
  { 2338, 1, 960, 1, 4207, 58 },
  { 2576, 1, 955, 1, 4208, 58 },
  { 201, 1, 947, 1, 4209, 58 },
  { 515, 1, 942, 1, 4210, 58 },
  { 796, 1, 937, 1, 4211, 58 },
  { 1068, 1, 932, 1, 4212, 58 },
  { 1349, 1, 907, 1, 4213, 58 },
  { 1600, 1, 902, 1, 4214, 58 },
  { 1854, 1, 897, 1, 4215, 58 },
  { 2099, 1, 892, 1, 4216, 58 },
  { 2353, 1, 927, 1, 4217, 58 },
  { 2591, 1, 922, 1, 4218, 58 },
  { 216, 1, 917, 1, 4219, 58 },
  { 530, 1, 912, 1, 4220, 58 },
  { 811, 1, 887, 1, 4221, 58 },
  { 1083, 1, 882, 1, 4222, 58 },
  { 1364, 1, 877, 1, 4223, 58 },
  { 1615, 1, 872, 1, 4224, 58 },
  { 1869, 1, 864, 1, 4225, 58 },
  { 2114, 1, 859, 1, 4226, 58 },
  { 2368, 1, 854, 1, 4227, 58 },
  { 2606, 1, 849, 1, 4228, 58 },
  { 231, 1, 844, 1, 4229, 58 },
  { 545, 1, 839, 1, 4230, 58 },
  { 826, 1, 834, 1, 4231, 58 },
  { 1098, 1, 829, 1, 4232, 58 },
  { 322, 313, 1152, 7, 1286217, 5 },
  { 636, 320, 1142, 7, 1286219, 5 },
  { 917, 323, 1132, 7, 1286221, 5 },
  { 1189, 338, 1122, 7, 1286223, 5 },
  { 1449, 341, 1109, 7, 1286225, 5 },
  { 1700, 348, 1099, 7, 1286227, 5 },
  { 1954, 351, 1069, 7, 1286229, 5 },
  { 2199, 382, 1059, 7, 1286231, 5 },
  { 2446, 385, 1089, 7, 1286233, 5 },
  { 2664, 392, 1079, 7, 1286235, 5 },
  { 53, 395, 1049, 7, 1286237, 5 },
  { 391, 410, 1039, 7, 1286239, 5 },
  { 698, 413, 1026, 7, 1286241, 5 },
  { 986, 420, 1016, 7, 1286243, 5 },
  { 1251, 423, 986, 7, 1286245, 5 },
  { 1518, 454, 976, 7, 1286247, 5 },
  { 1756, 457, 1006, 7, 1286249, 5 },
  { 2017, 464, 996, 7, 1286251, 5 },
  { 2255, 467, 966, 7, 1286253, 5 },
  { 2509, 482, 956, 7, 1286255, 5 },
  { 118, 485, 943, 7, 1286257, 5 },
  { 448, 492, 933, 7, 1286259, 5 },
  { 763, 495, 903, 7, 1286261, 5 },
  { 1043, 526, 893, 7, 1286263, 5 },
  { 1316, 529, 923, 7, 1286265, 5 },
  { 1575, 536, 913, 7, 1286267, 5 },
  { 1821, 539, 883, 7, 1286269, 5 },
  { 2074, 554, 873, 7, 1286271, 5 },
  { 2320, 557, 860, 7, 1286273, 5 },
  { 2566, 564, 850, 7, 1286275, 5 },
  { 183, 567, 840, 7, 1286277, 5 },
  { 505, 598, 830, 7, 1286279, 5 },
  { 310, 354, 1, 56, 2646089, 38 },
  { 624, 426, 1, 56, 2646105, 38 },
  { 905, 498, 1, 56, 2646121, 38 },
  { 1177, 570, 1, 56, 2646137, 38 },
  { 259, 1, 1332, 1, 4105, 58 },
  { 573, 1, 1326, 1, 4106, 58 },
  { 854, 1, 1320, 1, 4107, 58 },
  { 1126, 1, 1314, 1, 4108, 58 },
  { 1392, 1, 1314, 1, 4109, 58 },
  { 1643, 1, 1308, 1, 4110, 58 },
  { 1897, 1, 1299, 1, 4111, 58 },
  { 2142, 1, 1293, 1, 4112, 58 },
  { 2384, 1, 1293, 1, 4113, 58 },
  { 2622, 1, 1287, 1, 4114, 58 },
  { 1, 1, 1278, 1, 4115, 58 },
  { 339, 1, 1272, 1, 4116, 58 },
  { 646, 1, 1272, 1, 4117, 58 },
  { 934, 1, 1266, 1, 4118, 58 },
  { 1199, 1, 1257, 1, 4119, 58 },
  { 1466, 1, 1251, 1, 4120, 58 },
  { 1710, 1, 1251, 1, 4121, 58 },
  { 1971, 1, 1245, 1, 4122, 58 },
  { 2209, 1, 1236, 1, 4123, 58 },
  { 2463, 1, 1230, 1, 4124, 58 },
  { 72, 1, 1230, 1, 4125, 58 },
  { 402, 1, 1224, 1, 4126, 58 },
  { 717, 1, 1215, 1, 4127, 58 },
  { 997, 1, 1209, 1, 4128, 58 },
  { 1270, 1, 1209, 1, 4129, 58 },
  { 1529, 1, 1203, 1, 4130, 58 },
  { 1775, 1, 1194, 1, 4131, 58 },
  { 2028, 1, 1188, 1, 4132, 58 },
  { 2274, 1, 1188, 1, 4133, 58 },
  { 2520, 1, 1182, 1, 4134, 58 },
  { 137, 1, 1173, 1, 4135, 58 },
  { 459, 1, 1167, 1, 4136, 58 },
  { 2405, 306, 1, 0, 4099, 1 },
  { 331, 598, 1, 10, 1286153, 8 },
  { 926, 601, 1, 10, 1286155, 8 },
  { 1458, 604, 1, 10, 1286157, 8 },
  { 1963, 607, 1, 10, 1286159, 8 },
  { 2455, 610, 1, 10, 1286161, 8 },
  { 63, 613, 1, 10, 1286163, 8 },
  { 708, 616, 1, 10, 1286165, 8 },
  { 1261, 619, 1, 10, 1286167, 8 },
  { 1766, 622, 1, 10, 1286169, 8 },
  { 2265, 625, 1, 10, 1286171, 8 },
  { 128, 628, 1, 10, 1286173, 8 },
  { 773, 631, 1, 10, 1286175, 8 },
  { 1326, 634, 1, 10, 1286177, 8 },
  { 1831, 637, 1, 10, 1286179, 8 },
  { 2330, 640, 1, 10, 1286181, 8 },
  { 193, 643, 1, 10, 1286183, 8 },
  { 262, 1, 815, 1, 4233, 58 },
  { 576, 1, 815, 1, 4234, 58 },
  { 857, 1, 815, 1, 4235, 58 },
  { 1129, 1, 815, 1, 4236, 58 },
  { 1395, 1, 815, 1, 4237, 58 },
  { 1646, 1, 815, 1, 4238, 58 },
  { 1900, 1, 815, 1, 4239, 58 },
  { 2145, 1, 815, 1, 4240, 58 },
  { 2387, 1, 815, 1, 4241, 58 },
  { 2625, 1, 815, 1, 4242, 58 },
  { 5, 1, 815, 1, 4243, 58 },
  { 343, 1, 815, 1, 4244, 58 },
  { 650, 1, 815, 1, 4245, 58 },
  { 938, 1, 815, 1, 4246, 58 },
  { 1203, 1, 815, 1, 4247, 58 },
  { 1470, 1, 815, 1, 4248, 58 },
  { 1714, 1, 815, 1, 4249, 58 },
  { 1975, 1, 815, 1, 4250, 58 },
  { 2213, 1, 815, 1, 4251, 58 },
  { 2467, 1, 815, 1, 4252, 58 },
  { 76, 1, 815, 1, 4253, 58 },
  { 406, 1, 815, 1, 4254, 58 },
  { 721, 1, 815, 1, 4255, 58 },
  { 1001, 1, 815, 1, 4256, 58 },
  { 1274, 1, 815, 1, 4257, 58 },
  { 1533, 1, 815, 1, 4258, 58 },
  { 1779, 1, 815, 1, 4259, 58 },
  { 2032, 1, 815, 1, 4260, 58 },
  { 2278, 1, 815, 1, 4261, 58 },
  { 2524, 1, 815, 1, 4262, 58 },
  { 141, 1, 815, 1, 4263, 58 },
  { 463, 1, 815, 1, 4264, 58 },
  { 2409, 1, 1, 1, 4100, 58 },
  { 280, 1, 813, 1, 4265, 58 },
  { 594, 1, 809, 1, 4266, 58 },
  { 875, 1, 809, 1, 4267, 58 },
  { 1147, 1, 805, 1, 4268, 58 },
  { 1413, 1, 805, 1, 4269, 58 },
  { 1664, 1, 801, 1, 4270, 58 },
  { 1918, 1, 801, 1, 4271, 58 },
  { 2163, 1, 797, 1, 4272, 58 },
  { 2410, 1, 797, 1, 4273, 58 },
  { 2633, 1, 793, 1, 4274, 58 },
  { 15, 1, 793, 1, 4275, 58 },
  { 353, 1, 789, 1, 4276, 58 },
  { 660, 1, 789, 1, 4277, 58 },
  { 948, 1, 785, 1, 4278, 58 },
  { 1213, 1, 785, 1, 4279, 58 },
  { 1480, 1, 781, 1, 4280, 58 },
  { 1724, 1, 781, 1, 4281, 58 },
  { 1985, 1, 777, 1, 4282, 58 },
  { 2223, 1, 777, 1, 4283, 58 },
  { 2477, 1, 773, 1, 4284, 58 },
  { 86, 1, 773, 1, 4285, 58 },
  { 416, 1, 769, 1, 4286, 58 },
  { 731, 1, 769, 1, 4287, 58 },
  { 1011, 1, 765, 1, 4288, 58 },
  { 1284, 1, 765, 1, 4289, 58 },
  { 1543, 1, 761, 1, 4290, 58 },
  { 1789, 1, 761, 1, 4291, 58 },
  { 2042, 1, 757, 1, 4292, 58 },
  { 2288, 1, 757, 1, 4293, 58 },
  { 2534, 1, 753, 1, 4294, 58 },
  { 151, 1, 753, 1, 4295, 58 },
  { 473, 1, 749, 1, 4296, 58 },
  { 288, 308, 1, 2, 2752649, 0 },
  { 602, 308, 1, 2, 2752650, 0 },
  { 883, 308, 1, 2, 2752651, 0 },
  { 1155, 308, 1, 2, 2752652, 0 },
  { 1421, 308, 1, 2, 2752653, 0 },
  { 1672, 308, 1, 2, 2752654, 0 },
  { 1926, 308, 1, 2, 2752655, 0 },
  { 2171, 308, 1, 2, 2752656, 0 },
  { 2418, 308, 1, 2, 2752657, 0 },
  { 2636, 308, 1, 2, 2752658, 0 },
  { 19, 308, 1, 2, 2752659, 0 },
  { 357, 308, 1, 2, 2752660, 0 },
  { 664, 308, 1, 2, 2752661, 0 },
  { 952, 308, 1, 2, 2752662, 0 },
  { 1217, 308, 1, 2, 2752663, 0 },
  { 1484, 308, 1, 2, 2752664, 0 },
  { 1728, 308, 1, 2, 2752665, 0 },
  { 1989, 308, 1, 2, 2752666, 0 },
  { 2227, 308, 1, 2, 2752667, 0 },
  { 2481, 308, 1, 2, 2752668, 0 },
  { 90, 308, 1, 2, 2752669, 0 },
  { 420, 308, 1, 2, 2752670, 0 },
  { 735, 308, 1, 2, 2752671, 0 },
  { 1015, 308, 1, 2, 2752672, 0 },
  { 1288, 308, 1, 2, 2752673, 0 },
  { 1547, 308, 1, 2, 2752674, 0 },
  { 1793, 308, 1, 2, 2752675, 0 },
  { 2046, 308, 1, 2, 2752676, 0 },
  { 2292, 308, 1, 2, 2752677, 0 },
  { 2538, 308, 1, 2, 2752678, 0 },
  { 155, 308, 1, 2, 2752679, 0 },
  { 477, 308, 1, 2, 2752680, 0 },
  { 246, 95, 1, 23, 2695177, 19 },
  { 560, 122, 1, 23, 2695181, 19 },
  { 841, 149, 1, 23, 2695185, 19 },
  { 1113, 176, 1, 23, 2695189, 19 },
  { 1379, 203, 1, 23, 2695193, 19 },
  { 1630, 230, 1, 23, 2695197, 19 },
  { 1884, 257, 1, 23, 2695201, 19 },
  { 2129, 284, 1, 23, 2695205, 19 },
  { 291, 672, 1306, 5, 4297, 3 },
  { 605, 672, 1285, 5, 4298, 3 },
  { 886, 672, 1285, 5, 4299, 3 },
  { 1158, 672, 1264, 5, 4300, 3 },
  { 1424, 672, 1264, 5, 4301, 3 },
  { 1675, 672, 1243, 5, 4302, 3 },
  { 1929, 672, 1243, 5, 4303, 3 },
  { 2174, 672, 1222, 5, 4304, 3 },
  { 2421, 672, 1222, 5, 4305, 3 },
  { 2639, 672, 1201, 5, 4306, 3 },
  { 23, 672, 1201, 5, 4307, 3 },
  { 361, 672, 1180, 5, 4308, 3 },
  { 668, 672, 1180, 5, 4309, 3 },
  { 956, 672, 1165, 5, 4310, 3 },
  { 1221, 672, 1165, 5, 4311, 3 },
  { 1488, 672, 1124, 5, 4312, 3 },
  { 1732, 672, 1124, 5, 4313, 3 },
  { 1993, 672, 1041, 5, 4314, 3 },
  { 2231, 672, 1041, 5, 4315, 3 },
  { 2485, 672, 958, 5, 4316, 3 },
  { 94, 672, 958, 5, 4317, 3 },
  { 424, 672, 875, 5, 4318, 3 },
  { 739, 672, 875, 5, 4319, 3 },
  { 1019, 672, 832, 5, 4320, 3 },
  { 1292, 672, 832, 5, 4321, 3 },
  { 1551, 672, 827, 5, 4322, 3 },
  { 1797, 672, 827, 5, 4323, 3 },
  { 2050, 672, 824, 5, 4324, 3 },
  { 2296, 672, 824, 5, 4325, 3 },
  { 2542, 672, 821, 5, 4326, 3 },
  { 159, 672, 821, 5, 4327, 3 },
  { 481, 672, 818, 5, 4328, 3 },
  { 258, 1, 1305, 1, 4297, 58 },
  { 572, 1, 1284, 1, 4298, 58 },
  { 853, 1, 1284, 1, 4299, 58 },
  { 1125, 1, 1263, 1, 4300, 58 },
  { 1391, 1, 1263, 1, 4301, 58 },
  { 1642, 1, 1242, 1, 4302, 58 },
  { 1896, 1, 1242, 1, 4303, 58 },
  { 2141, 1, 1221, 1, 4304, 58 },
  { 2383, 1, 1221, 1, 4305, 58 },
  { 2621, 1, 1200, 1, 4306, 58 },
  { 0, 1, 1200, 1, 4307, 58 },
  { 338, 1, 1179, 1, 4308, 58 },
  { 645, 1, 1179, 1, 4309, 58 },
  { 933, 1, 1164, 1, 4310, 58 },
  { 1198, 1, 1164, 1, 4311, 58 },
  { 1465, 1, 1161, 1, 4312, 58 },
  { 1709, 1, 1161, 1, 4313, 58 },
  { 1970, 1, 1118, 1, 4314, 58 },
  { 2208, 1, 1118, 1, 4315, 58 },
  { 2462, 1, 1035, 1, 4316, 58 },
  { 71, 1, 1035, 1, 4317, 58 },
  { 401, 1, 952, 1, 4318, 58 },
  { 716, 1, 952, 1, 4319, 58 },
  { 996, 1, 869, 1, 4320, 58 },
  { 1269, 1, 869, 1, 4321, 58 },
  { 1528, 1, 826, 1, 4322, 58 },
  { 1774, 1, 826, 1, 4323, 58 },
  { 2027, 1, 823, 1, 4324, 58 },
  { 2273, 1, 823, 1, 4325, 58 },
  { 2519, 1, 820, 1, 4326, 58 },
  { 136, 1, 820, 1, 4327, 58 },
  { 458, 1, 817, 1, 4328, 58 },
  { 274, 93, 1436, 5, 4105, 3 },
  { 588, 93, 1432, 5, 4106, 3 },
  { 869, 93, 1428, 5, 4107, 3 },
  { 1141, 93, 1424, 5, 4108, 3 },
  { 1407, 93, 1424, 5, 4109, 3 },
  { 1658, 93, 1420, 5, 4110, 3 },
  { 1912, 93, 1416, 5, 4111, 3 },
  { 2157, 93, 1412, 5, 4112, 3 },
  { 2390, 93, 1412, 5, 4113, 3 },
  { 2628, 93, 1408, 5, 4114, 3 },
  { 9, 93, 1404, 5, 4115, 3 },
  { 347, 93, 1400, 5, 4116, 3 },
  { 654, 93, 1400, 5, 4117, 3 },
  { 942, 93, 1396, 5, 4118, 3 },
  { 1207, 93, 1392, 5, 4119, 3 },
  { 1474, 93, 1388, 5, 4120, 3 },
  { 1718, 93, 1388, 5, 4121, 3 },
  { 1979, 93, 1384, 5, 4122, 3 },
  { 2217, 93, 1380, 5, 4123, 3 },
  { 2471, 93, 1376, 5, 4124, 3 },
  { 80, 93, 1376, 5, 4125, 3 },
  { 410, 93, 1372, 5, 4126, 3 },
  { 725, 93, 1368, 5, 4127, 3 },
  { 1005, 93, 1364, 5, 4128, 3 },
  { 1278, 93, 1364, 5, 4129, 3 },
  { 1537, 93, 1360, 5, 4130, 3 },
  { 1783, 93, 1356, 5, 4131, 3 },
  { 2036, 93, 1352, 5, 4132, 3 },
  { 2282, 93, 1352, 5, 4133, 3 },
  { 2528, 93, 1348, 5, 4134, 3 },
  { 145, 93, 1344, 5, 4135, 3 },
  { 467, 93, 1340, 5, 4136, 3 },
  { 316, 90, 1433, 18, 1286153, 16 },
  { 630, 101, 1421, 18, 1286155, 16 },
  { 911, 117, 1421, 18, 1286157, 16 },
  { 1183, 128, 1409, 18, 1286159, 16 },
  { 1443, 144, 1409, 18, 1286161, 16 },
  { 1694, 155, 1397, 18, 1286163, 16 },
  { 1948, 171, 1397, 18, 1286165, 16 },
  { 2193, 182, 1385, 18, 1286167, 16 },
  { 2440, 198, 1385, 18, 1286169, 16 },
  { 2658, 209, 1373, 18, 1286171, 16 },
  { 46, 225, 1373, 18, 1286173, 16 },
  { 384, 236, 1361, 18, 1286175, 16 },
  { 691, 252, 1361, 18, 1286177, 16 },
  { 979, 263, 1349, 18, 1286179, 16 },
  { 1244, 279, 1349, 18, 1286181, 16 },
  { 1511, 290, 1341, 18, 1286183, 16 },
  { 1749, 669, 1, 18, 1286345, 16 },
  { 2010, 674, 1, 18, 1286347, 16 },
  { 2248, 679, 1, 18, 1286349, 16 },
  { 2502, 684, 1, 18, 1286351, 16 },
  { 111, 689, 1, 18, 1286353, 16 },
  { 441, 694, 1, 18, 1286355, 16 },
  { 756, 699, 1, 18, 1286357, 16 },
  { 1036, 704, 1, 18, 1286359, 16 },
  { 1309, 709, 1, 18, 1286361, 16 },
  { 1568, 714, 1, 18, 1286363, 16 },
  { 1814, 719, 1, 18, 1286365, 16 },
  { 2067, 724, 1, 18, 1286367, 16 },
  { 2313, 729, 1, 18, 1286369, 16 },
  { 2559, 734, 1, 18, 1286371, 16 },
  { 176, 739, 1, 18, 1286373, 16 },
  { 498, 744, 1, 18, 1286375, 16 },
  { 790, 1, 1, 1, 4329, 58 },
  { 1062, 1, 1, 1, 4330, 58 },
  { 1343, 1, 1, 1, 4331, 58 },
  { 1594, 1, 1, 1, 4332, 58 },
  { 1848, 1, 1, 1, 4333, 58 },
  { 2093, 1, 1, 1, 4334, 58 },
  { 2347, 1, 1, 1, 4335, 58 },
  { 2585, 1, 1, 1, 4336, 58 },
  { 210, 1, 1, 1, 4337, 58 },
  { 524, 1, 1, 1, 4338, 58 },
  { 805, 1, 1, 1, 4339, 58 },
  { 1077, 1, 1, 1, 4340, 58 },
  { 1358, 1, 1, 1, 4341, 58 },
  { 1609, 1, 1, 1, 4342, 58 },
  { 1863, 1, 1, 1, 4343, 58 },
  { 2108, 1, 1, 1, 4344, 58 },
  { 2362, 1, 1, 1, 4345, 58 },
  { 2600, 1, 1, 1, 4346, 58 },
  { 225, 1, 1, 1, 4347, 58 },
  { 539, 1, 1, 1, 4348, 58 },
  { 820, 1, 1, 1, 4349, 58 },
  { 1092, 1, 1, 1, 4350, 58 },
  { 1373, 1, 1, 1, 4351, 58 },
  { 1624, 1, 1, 1, 4352, 58 },
  { 1878, 1, 1, 1, 4353, 58 },
  { 2123, 1, 1, 1, 4354, 58 },
  { 2377, 1, 1, 1, 4355, 58 },
  { 2615, 1, 1, 1, 4356, 58 },
  { 240, 1, 1, 1, 4357, 58 },
  { 554, 1, 1, 1, 4358, 58 },
  { 835, 1, 1, 1, 4359, 58 },
  { 1107, 1, 1, 1, 4360, 58 },
  { 252, 316, 1143, 34, 2695241, 24 },
  { 566, 344, 1080, 34, 2695249, 24 },
  { 847, 388, 1080, 34, 2695257, 24 },
  { 1119, 416, 997, 34, 2695265, 24 },
  { 1385, 460, 997, 34, 2695273, 24 },
  { 1636, 488, 914, 34, 2695281, 24 },
  { 1890, 532, 914, 34, 2695289, 24 },
  { 2135, 560, 851, 34, 2695297, 24 },
  { 265, 334, 1123, 34, 2695245, 24 },
  { 579, 378, 1040, 34, 2695253, 24 },
  { 860, 406, 1040, 34, 2695261, 24 },
  { 1132, 450, 957, 34, 2695269, 24 },
  { 1398, 478, 957, 34, 2695277, 24 },
  { 1649, 522, 874, 34, 2695285, 24 },
  { 1903, 550, 874, 34, 2695293, 24 },
  { 2148, 594, 831, 34, 2695301, 24 },
  { 302, 13, 815, 0, 4265, 1 },
  { 616, 13, 811, 0, 4266, 1 },
  { 897, 13, 811, 0, 4267, 1 },
  { 1169, 13, 807, 0, 4268, 1 },
  { 1435, 13, 807, 0, 4269, 1 },
  { 1686, 13, 803, 0, 4270, 1 },
  { 1940, 13, 803, 0, 4271, 1 },
  { 2185, 13, 799, 0, 4272, 1 },
  { 2432, 13, 799, 0, 4273, 1 },
  { 2650, 13, 795, 0, 4274, 1 },
  { 36, 13, 795, 0, 4275, 1 },
  { 374, 13, 791, 0, 4276, 1 },
  { 681, 13, 791, 0, 4277, 1 },
  { 969, 13, 787, 0, 4278, 1 },
  { 1234, 13, 787, 0, 4279, 1 },
  { 1501, 13, 783, 0, 4280, 1 },
  { 1745, 13, 783, 0, 4281, 1 },
  { 2006, 13, 779, 0, 4282, 1 },
  { 2244, 13, 779, 0, 4283, 1 },
  { 2498, 13, 775, 0, 4284, 1 },
  { 107, 13, 775, 0, 4285, 1 },
  { 437, 13, 771, 0, 4286, 1 },
  { 752, 13, 771, 0, 4287, 1 },
  { 1032, 13, 767, 0, 4288, 1 },
  { 1305, 13, 767, 0, 4289, 1 },
  { 1564, 13, 763, 0, 4290, 1 },
  { 1810, 13, 763, 0, 4291, 1 },
  { 2063, 13, 759, 0, 4292, 1 },
  { 2309, 13, 759, 0, 4293, 1 },
  { 2555, 13, 755, 0, 4294, 1 },
  { 172, 13, 755, 0, 4295, 1 },
  { 494, 13, 751, 0, 4296, 1 },
  { 2395, 4, 1, 0, 4104, 1 },
  { 2742, 1, 8, 1, 4139, 58 },
  { 2748, 1, 8, 1, 4143, 58 },
  { 2754, 1, 8, 1, 4147, 58 },
  { 2760, 1, 8, 1, 4151, 58 },
  { 2766, 1, 8, 1, 4155, 58 },
  { 2772, 1, 8, 1, 4159, 58 },
  { 2778, 1, 8, 1, 4163, 58 },
  { 2784, 1, 8, 1, 4167, 58 },
  { 2809, 1, 6, 1, 4138, 58 },
  { 2815, 1, 6, 1, 4142, 58 },
  { 2821, 1, 6, 1, 4146, 58 },
  { 2827, 1, 6, 1, 4150, 58 },
  { 2833, 1, 6, 1, 4154, 58 },
  { 2839, 1, 6, 1, 4158, 58 },
  { 2845, 1, 6, 1, 4162, 58 },
  { 2851, 1, 6, 1, 4166, 58 },
  { 2857, 1, 2, 1, 4137, 58 },
  { 2863, 1, 2, 1, 4141, 58 },
  { 2869, 1, 2, 1, 4145, 58 },
  { 2875, 1, 2, 1, 4149, 58 },
  { 2881, 1, 2, 1, 4153, 58 },
  { 2887, 1, 2, 1, 4157, 58 },
  { 2893, 1, 2, 1, 4161, 58 },
  { 2899, 1, 2, 1, 4165, 58 },
  { 2683, 1, 0, 1, 4140, 58 },
  { 2689, 1, 0, 1, 4144, 58 },
  { 2695, 1, 0, 1, 4148, 58 },
  { 2701, 1, 0, 1, 4152, 58 },
  { 2707, 1, 0, 1, 4156, 58 },
  { 2713, 1, 0, 1, 4160, 58 },
  { 2719, 1, 0, 1, 4164, 58 },
  { 2725, 1, 0, 1, 4168, 58 },
  { 305, 10, 1, 87, 1286313, 55 },
  { 619, 15, 1, 87, 1286315, 55 },
  { 900, 20, 1, 87, 1286317, 55 },
  { 1172, 25, 1, 87, 1286319, 55 },
  { 1438, 30, 1, 87, 1286321, 55 },
  { 1689, 35, 1, 87, 1286323, 55 },
  { 1943, 40, 1, 87, 1286325, 55 },
  { 2188, 45, 1, 87, 1286327, 55 },
  { 2435, 50, 1, 87, 1286329, 55 },
  { 2653, 55, 1, 87, 1286331, 55 },
  { 40, 60, 1, 87, 1286333, 55 },
  { 378, 65, 1, 87, 1286335, 55 },
  { 685, 70, 1, 87, 1286337, 55 },
  { 973, 75, 1, 87, 1286339, 55 },
  { 1238, 80, 1, 87, 1286341, 55 },
  { 1505, 85, 1, 87, 1286343, 55 },
};

extern const MCPhysReg PPCRegUnitRoots[][2] = {
  { PPC::BP },
  { PPC::CARRY, PPC::XER },
  { PPC::CTR, PPC::CTR8 },
  { PPC::FP },
  { PPC::LR, PPC::LR8 },
  { PPC::RM },
  { PPC::SPEFSCR },
  { PPC::VRSAVE },
  { PPC::ZERO },
  { PPC::F0 },
  { PPC::F1 },
  { PPC::F2 },
  { PPC::F3 },
  { PPC::F4 },
  { PPC::F5 },
  { PPC::F6 },
  { PPC::F7 },
  { PPC::F8 },
  { PPC::F9 },
  { PPC::F10 },
  { PPC::F11 },
  { PPC::F12 },
  { PPC::F13 },
  { PPC::F14 },
  { PPC::F15 },
  { PPC::F16 },
  { PPC::F17 },
  { PPC::F18 },
  { PPC::F19 },
  { PPC::F20 },
  { PPC::F21 },
  { PPC::F22 },
  { PPC::F23 },
  { PPC::F24 },
  { PPC::F25 },
  { PPC::F26 },
  { PPC::F27 },
  { PPC::F28 },
  { PPC::F29 },
  { PPC::F30 },
  { PPC::F31 },
  { PPC::CR0LT },
  { PPC::CR0GT },
  { PPC::CR0EQ },
  { PPC::CR0UN },
  { PPC::CR1LT },
  { PPC::CR1GT },
  { PPC::CR1EQ },
  { PPC::CR1UN },
  { PPC::CR2LT },
  { PPC::CR2GT },
  { PPC::CR2EQ },
  { PPC::CR2UN },
  { PPC::CR3LT },
  { PPC::CR3GT },
  { PPC::CR3EQ },
  { PPC::CR3UN },
  { PPC::CR4LT },
  { PPC::CR4GT },
  { PPC::CR4EQ },
  { PPC::CR4UN },
  { PPC::CR5LT },
  { PPC::CR5GT },
  { PPC::CR5EQ },
  { PPC::CR5UN },
  { PPC::CR6LT },
  { PPC::CR6GT },
  { PPC::CR6EQ },
  { PPC::CR6UN },
  { PPC::CR7LT },
  { PPC::CR7GT },
  { PPC::CR7EQ },
  { PPC::CR7UN },
  { PPC::DMRROW0 },
  { PPC::DMRROW1 },
  { PPC::DMRROW2 },
  { PPC::DMRROW3 },
  { PPC::DMRROW4 },
  { PPC::DMRROW5 },
  { PPC::DMRROW6 },
  { PPC::DMRROW7 },
  { PPC::DMRROW8 },
  { PPC::DMRROW9 },
  { PPC::DMRROW10 },
  { PPC::DMRROW11 },
  { PPC::DMRROW12 },
  { PPC::DMRROW13 },
  { PPC::DMRROW14 },
  { PPC::DMRROW15 },
  { PPC::DMRROW16 },
  { PPC::DMRROW17 },
  { PPC::DMRROW18 },
  { PPC::DMRROW19 },
  { PPC::DMRROW20 },
  { PPC::DMRROW21 },
  { PPC::DMRROW22 },
  { PPC::DMRROW23 },
  { PPC::DMRROW24 },
  { PPC::DMRROW25 },
  { PPC::DMRROW26 },
  { PPC::DMRROW27 },
  { PPC::DMRROW28 },
  { PPC::DMRROW29 },
  { PPC::DMRROW30 },
  { PPC::DMRROW31 },
  { PPC::DMRROW32 },
  { PPC::DMRROW33 },
  { PPC::DMRROW34 },
  { PPC::DMRROW35 },
  { PPC::DMRROW36 },
  { PPC::DMRROW37 },
  { PPC::DMRROW38 },
  { PPC::DMRROW39 },
  { PPC::DMRROW40 },
  { PPC::DMRROW41 },
  { PPC::DMRROW42 },
  { PPC::DMRROW43 },
  { PPC::DMRROW44 },
  { PPC::DMRROW45 },
  { PPC::DMRROW46 },
  { PPC::DMRROW47 },
  { PPC::DMRROW48 },
  { PPC::DMRROW49 },
  { PPC::DMRROW50 },
  { PPC::DMRROW51 },
  { PPC::DMRROW52 },
  { PPC::DMRROW53 },
  { PPC::DMRROW54 },
  { PPC::DMRROW55 },
  { PPC::DMRROW56 },
  { PPC::DMRROW57 },
  { PPC::DMRROW58 },
  { PPC::DMRROW59 },
  { PPC::DMRROW60 },
  { PPC::DMRROW61 },
  { PPC::DMRROW62 },
  { PPC::DMRROW63 },
  { PPC::H0 },
  { PPC::H1 },
  { PPC::H2 },
  { PPC::H3 },
  { PPC::H4 },
  { PPC::H5 },
  { PPC::H6 },
  { PPC::H7 },
  { PPC::H8 },
  { PPC::H9 },
  { PPC::H10 },
  { PPC::H11 },
  { PPC::H12 },
  { PPC::H13 },
  { PPC::H14 },
  { PPC::H15 },
  { PPC::H16 },
  { PPC::H17 },
  { PPC::H18 },
  { PPC::H19 },
  { PPC::H20 },
  { PPC::H21 },
  { PPC::H22 },
  { PPC::H23 },
  { PPC::H24 },
  { PPC::H25 },
  { PPC::H26 },
  { PPC::H27 },
  { PPC::H28 },
  { PPC::H29 },
  { PPC::H30 },
  { PPC::H31 },
  { PPC::R0 },
  { PPC::R1 },
  { PPC::R2 },
  { PPC::R3 },
  { PPC::R4 },
  { PPC::R5 },
  { PPC::R6 },
  { PPC::R7 },
  { PPC::R8 },
  { PPC::R9 },
  { PPC::R10 },
  { PPC::R11 },
  { PPC::R12 },
  { PPC::R13 },
  { PPC::R14 },
  { PPC::R15 },
  { PPC::R16 },
  { PPC::R17 },
  { PPC::R18 },
  { PPC::R19 },
  { PPC::R20 },
  { PPC::R21 },
  { PPC::R22 },
  { PPC::R23 },
  { PPC::R24 },
  { PPC::R25 },
  { PPC::R26 },
  { PPC::R27 },
  { PPC::R28 },
  { PPC::R29 },
  { PPC::R30 },
  { PPC::R31 },
  { PPC::VF0 },
  { PPC::VF1 },
  { PPC::VF2 },
  { PPC::VF3 },
  { PPC::VF4 },
  { PPC::VF5 },
  { PPC::VF6 },
  { PPC::VF7 },
  { PPC::VF8 },
  { PPC::VF9 },
  { PPC::VF10 },
  { PPC::VF11 },
  { PPC::VF12 },
  { PPC::VF13 },
  { PPC::VF14 },
  { PPC::VF15 },
  { PPC::VF16 },
  { PPC::VF17 },
  { PPC::VF18 },
  { PPC::VF19 },
  { PPC::VF20 },
  { PPC::VF21 },
  { PPC::VF22 },
  { PPC::VF23 },
  { PPC::VF24 },
  { PPC::VF25 },
  { PPC::VF26 },
  { PPC::VF27 },
  { PPC::VF28 },
  { PPC::VF29 },
  { PPC::VF30 },
  { PPC::VF31 },
  { PPC::VSX32 },
  { PPC::VSX33 },
  { PPC::VSX34 },
  { PPC::VSX35 },
  { PPC::VSX36 },
  { PPC::VSX37 },
  { PPC::VSX38 },
  { PPC::VSX39 },
  { PPC::VSX40 },
  { PPC::VSX41 },
  { PPC::VSX42 },
  { PPC::VSX43 },
  { PPC::VSX44 },
  { PPC::VSX45 },
  { PPC::VSX46 },
  { PPC::VSX47 },
  { PPC::VSX48 },
  { PPC::VSX49 },
  { PPC::VSX50 },
  { PPC::VSX51 },
  { PPC::VSX52 },
  { PPC::VSX53 },
  { PPC::VSX54 },
  { PPC::VSX55 },
  { PPC::VSX56 },
  { PPC::VSX57 },
  { PPC::VSX58 },
  { PPC::VSX59 },
  { PPC::VSX60 },
  { PPC::VSX61 },
  { PPC::VSX62 },
  { PPC::VSX63 },
};

namespace {     // Register classes...
  // VSSRC Register Class...
  const MCPhysReg VSSRC[] = {
    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20, 
  };

  // VSSRC Bit set.
  const uint8_t VSSRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // GPRC Register Class...
  const MCPhysReg GPRC[] = {
    PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, 
  };

  // GPRC Bit set.
  const uint8_t GPRCBits[] = {
    0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // GPRC_NOR0 Register Class...
  const MCPhysReg GPRC_NOR0[] = {
    PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, 
  };

  // GPRC_NOR0 Bit set.
  const uint8_t GPRC_NOR0Bits[] = {
    0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07, 
  };

  // GPRC_and_GPRC_NOR0 Register Class...
  const MCPhysReg GPRC_and_GPRC_NOR0[] = {
    PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, 
  };

  // GPRC_and_GPRC_NOR0 Bit set.
  const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
    0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07, 
  };

  // CRBITRC Register Class...
  const MCPhysReg CRBITRC[] = {
    PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 
  };

  // CRBITRC Bit set.
  const uint8_t CRBITRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // F4RC Register Class...
  const MCPhysReg F4RC[] = {
    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, 
  };

  // F4RC Bit set.
  const uint8_t F4RCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // GPRC32 Register Class...
  const MCPhysReg GPRC32[] = {
    PPC::H2, PPC::H3, PPC::H4, PPC::H5, PPC::H6, PPC::H7, PPC::H8, PPC::H9, PPC::H10, PPC::H11, PPC::H12, PPC::H30, PPC::H29, PPC::H28, PPC::H27, PPC::H26, PPC::H25, PPC::H24, PPC::H23, PPC::H22, PPC::H21, PPC::H20, PPC::H19, PPC::H18, PPC::H17, PPC::H16, PPC::H15, PPC::H14, PPC::H13, PPC::H31, PPC::H0, PPC::H1, 
  };

  // GPRC32 Bit set.
  const uint8_t GPRC32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // CRRC Register Class...
  const MCPhysReg CRRC[] = {
    PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, PPC::CR2, PPC::CR3, PPC::CR4, 
  };

  // CRRC Bit set.
  const uint8_t CRRCBits[] = {
    0x00, 0x00, 0xf0, 0x0f, 
  };

  // CARRYRC Register Class...
  const MCPhysReg CARRYRC[] = {
    PPC::CARRY, PPC::XER, 
  };

  // CARRYRC Bit set.
  const uint8_t CARRYRCBits[] = {
    0x04, 0x02, 
  };

  // CTRRC Register Class...
  const MCPhysReg CTRRC[] = {
    PPC::CTR, 
  };

  // CTRRC Bit set.
  const uint8_t CTRRCBits[] = {
    0x08, 
  };

  // LRRC Register Class...
  const MCPhysReg LRRC[] = {
    PPC::LR, 
  };

  // LRRC Bit set.
  const uint8_t LRRCBits[] = {
    0x20, 
  };

  // VRSAVERC Register Class...
  const MCPhysReg VRSAVERC[] = {
    PPC::VRSAVE, 
  };

  // VRSAVERC Bit set.
  const uint8_t VRSAVERCBits[] = {
    0x00, 0x01, 
  };

  // SPILLTOVSRRC Register Class...
  const MCPhysReg SPILLTOVSRRC[] = {
    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 
  };

  // SPILLTOVSRRC Bit set.
  const uint8_t SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // VSFRC Register Class...
  const MCPhysReg VSFRC[] = {
    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20, 
  };

  // VSFRC Bit set.
  const uint8_t VSFRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // G8RC Register Class...
  const MCPhysReg G8RC[] = {
    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, 
  };

  // G8RC Bit set.
  const uint8_t G8RCBits[] = {
    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // G8RC_NOX0 Register Class...
  const MCPhysReg G8RC_NOX0[] = {
    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, 
  };

  // G8RC_NOX0 Bit set.
  const uint8_t G8RC_NOX0Bits[] = {
    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // SPILLTOVSRRC_and_VSFRC Register Class...
  const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 
  };

  // SPILLTOVSRRC_and_VSFRC Bit set.
  const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 
  };

  // G8RC_and_G8RC_NOX0 Register Class...
  const MCPhysReg G8RC_and_G8RC_NOX0[] = {
    PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, 
  };

  // G8RC_and_G8RC_NOX0 Bit set.
  const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
    0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07, 
  };

  // F8RC Register Class...
  const MCPhysReg F8RC[] = {
    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F31, PPC::F30, PPC::F29, PPC::F28, PPC::F27, PPC::F26, PPC::F25, PPC::F24, PPC::F23, PPC::F22, PPC::F21, PPC::F20, PPC::F19, PPC::F18, PPC::F17, PPC::F16, PPC::F15, PPC::F14, 
  };

  // F8RC Bit set.
  const uint8_t F8RCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 
  };

  // SPERC Register Class...
  const MCPhysReg SPERC[] = {
    PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S0, PPC::S1, 
  };

  // SPERC Bit set.
  const uint8_t SPERCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // VFRC Register Class...
  const MCPhysReg VFRC[] = {
    PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, PPC::VF31, PPC::VF30, PPC::VF29, PPC::VF28, PPC::VF27, PPC::VF26, PPC::VF25, PPC::VF24, PPC::VF23, PPC::VF22, PPC::VF21, PPC::VF20, 
  };

  // VFRC Bit set.
  const uint8_t VFRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // SPERC_with_sub_32_in_GPRC_NOR0 Register Class...
  const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
    PPC::S2, PPC::S3, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S11, PPC::S12, PPC::S30, PPC::S29, PPC::S28, PPC::S27, PPC::S26, PPC::S25, PPC::S24, PPC::S23, PPC::S22, PPC::S21, PPC::S20, PPC::S19, PPC::S18, PPC::S17, PPC::S16, PPC::S15, PPC::S14, PPC::S13, PPC::S31, PPC::S1, 
  };

  // SPERC_with_sub_32_in_GPRC_NOR0 Bit set.
  const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07, 
  };

  // SPILLTOVSRRC_and_VFRC Register Class...
  const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
    PPC::VF2, PPC::VF3, PPC::VF4, PPC::VF5, PPC::VF0, PPC::VF1, PPC::VF6, PPC::VF7, PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11, PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15, PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19, 
  };

  // SPILLTOVSRRC_and_VFRC Bit set.
  const uint8_t SPILLTOVSRRC_and_VFRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 
  };

  // SPILLTOVSRRC_and_F4RC Register Class...
  const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
    PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, 
  };

  // SPILLTOVSRRC_and_F4RC Bit set.
  const uint8_t SPILLTOVSRRC_and_F4RCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 
  };

  // CTRRC8 Register Class...
  const MCPhysReg CTRRC8[] = {
    PPC::CTR8, 
  };

  // CTRRC8 Bit set.
  const uint8_t CTRRC8Bits[] = {
    0x00, 0x00, 0x00, 0x10, 
  };

  // LR8RC Register Class...
  const MCPhysReg LR8RC[] = {
    PPC::LR8, 
  };

  // LR8RC Bit set.
  const uint8_t LR8RCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // DMRROWRC Register Class...
  const MCPhysReg DMRROWRC[] = {
    PPC::DMRROW0, PPC::DMRROW1, PPC::DMRROW2, PPC::DMRROW3, PPC::DMRROW4, PPC::DMRROW5, PPC::DMRROW6, PPC::DMRROW7, PPC::DMRROW8, PPC::DMRROW9, PPC::DMRROW10, PPC::DMRROW11, PPC::DMRROW12, PPC::DMRROW13, PPC::DMRROW14, PPC::DMRROW15, PPC::DMRROW16, PPC::DMRROW17, PPC::DMRROW18, PPC::DMRROW19, PPC::DMRROW20, PPC::DMRROW21, PPC::DMRROW22, PPC::DMRROW23, PPC::DMRROW24, PPC::DMRROW25, PPC::DMRROW26, PPC::DMRROW27, PPC::DMRROW28, PPC::DMRROW29, PPC::DMRROW30, PPC::DMRROW31, PPC::DMRROW32, PPC::DMRROW33, PPC::DMRROW34, PPC::DMRROW35, PPC::DMRROW36, PPC::DMRROW37, PPC::DMRROW38, PPC::DMRROW39, PPC::DMRROW40, PPC::DMRROW41, PPC::DMRROW42, PPC::DMRROW43, PPC::DMRROW44, PPC::DMRROW45, PPC::DMRROW46, PPC::DMRROW47, PPC::DMRROW48, PPC::DMRROW49, PPC::DMRROW50, PPC::DMRROW51, PPC::DMRROW52, PPC::DMRROW53, PPC::DMRROW54, PPC::DMRROW55, PPC::DMRROW56, PPC::DMRROW57, PPC::DMRROW58, PPC::DMRROW59, PPC::DMRROW60, PPC::DMRROW61, PPC::DMRROW62, PPC::DMRROW63, 
  };

  // DMRROWRC Bit set.
  const uint8_t DMRROWRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f, 
  };

  // VSRC Register Class...
  const MCPhysReg VSRC[] = {
    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20, 
  };

  // VSRC Bit set.
  const uint8_t VSRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // VSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 
  };

  // VSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
  };

  // VRRC Register Class...
  const MCPhysReg VRRC[] = {
    PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V31, PPC::V30, PPC::V29, PPC::V28, PPC::V27, PPC::V26, PPC::V25, PPC::V24, PPC::V23, PPC::V22, PPC::V21, PPC::V20, 
  };

  // VRRC Bit set.
  const uint8_t VRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // VSLRC Register Class...
  const MCPhysReg VSLRC[] = {
    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL31, PPC::VSL30, PPC::VSL29, PPC::VSL28, PPC::VSL27, PPC::VSL26, PPC::VSL25, PPC::VSL24, PPC::VSL23, PPC::VSL22, PPC::VSL21, PPC::VSL20, PPC::VSL19, PPC::VSL18, PPC::VSL17, PPC::VSL16, PPC::VSL15, PPC::VSL14, 
  };

  // VSLRC Bit set.
  const uint8_t VSLRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // VRRC_with_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
    PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V0, PPC::V1, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 
  };

  // VRRC_with_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 
  };

  // FpRC Register Class...
  const MCPhysReg FpRC[] = {
    PPC::Fpair0, PPC::Fpair2, PPC::Fpair4, PPC::Fpair6, PPC::Fpair8, PPC::Fpair10, PPC::Fpair12, PPC::Fpair14, PPC::Fpair16, PPC::Fpair18, PPC::Fpair20, PPC::Fpair22, PPC::Fpair24, PPC::Fpair26, PPC::Fpair28, PPC::Fpair30, 
  };

  // FpRC Bit set.
  const uint8_t FpRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
  };

  // G8pRC Register Class...
  const MCPhysReg G8pRC[] = {
    PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0, 
  };

  // G8pRC Bit set.
  const uint8_t G8pRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
  };

  // G8pRC_with_sub_32_in_GPRC_NOR0 Register Class...
  const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = {
    PPC::G8p1, PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, 
  };

  // G8pRC_with_sub_32_in_GPRC_NOR0 Bit set.
  const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
  };

  // VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
    PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, 
  };

  // VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01, 
  };

  // FpRC_with_sub_fp0_in_SPILLTOVSRRC Register Class...
  const MCPhysReg FpRC_with_sub_fp0_in_SPILLTOVSRRC[] = {
    PPC::Fpair0, PPC::Fpair2, PPC::Fpair4, PPC::Fpair6, PPC::Fpair8, PPC::Fpair10, PPC::Fpair12, 
  };

  // FpRC_with_sub_fp0_in_SPILLTOVSRRC Bit set.
  const uint8_t FpRC_with_sub_fp0_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01, 
  };

  // DMRROWpRC Register Class...
  const MCPhysReg DMRROWpRC[] = {
    PPC::DMRROWp0, PPC::DMRROWp1, PPC::DMRROWp2, PPC::DMRROWp3, PPC::DMRROWp4, PPC::DMRROWp5, PPC::DMRROWp6, PPC::DMRROWp7, PPC::DMRROWp8, PPC::DMRROWp9, PPC::DMRROWp10, PPC::DMRROWp11, PPC::DMRROWp12, PPC::DMRROWp13, PPC::DMRROWp14, PPC::DMRROWp15, PPC::DMRROWp16, PPC::DMRROWp17, PPC::DMRROWp18, PPC::DMRROWp19, PPC::DMRROWp20, PPC::DMRROWp21, PPC::DMRROWp22, PPC::DMRROWp23, PPC::DMRROWp24, PPC::DMRROWp25, PPC::DMRROWp26, PPC::DMRROWp27, PPC::DMRROWp28, PPC::DMRROWp29, PPC::DMRROWp30, PPC::DMRROWp31, 
  };

  // DMRROWpRC Bit set.
  const uint8_t DMRROWpRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f, 
  };

  // VSRpRC Register Class...
  const MCPhysReg VSRpRC[] = {
    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7, 
  };

  // VSRpRC Bit set.
  const uint8_t VSRpRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 
  };

  // VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = {
    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, 
  };

  // VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xf8, 0x1f, 
  };

  // VSRpRC_with_sub_64_in_F4RC Register Class...
  const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = {
    PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp15, PPC::VSRp14, PPC::VSRp13, PPC::VSRp12, PPC::VSRp11, PPC::VSRp10, PPC::VSRp9, PPC::VSRp8, PPC::VSRp7, 
  };

  // VSRpRC_with_sub_64_in_F4RC Bit set.
  const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 
  };

  // VSRpRC_with_sub_64_in_VFRC Register Class...
  const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = {
    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp31, PPC::VSRp30, PPC::VSRp29, PPC::VSRp28, PPC::VSRp27, PPC::VSRp26, 
  };

  // VSRpRC_with_sub_64_in_VFRC Bit set.
  const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 
  };

  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class...
  const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = {
    PPC::VSRp17, PPC::VSRp18, PPC::VSRp16, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, 
  };

  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set.
  const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f, 
  };

  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class...
  const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = {
    PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, 
  };

  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set.
  const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 
  };

  // ACCRC Register Class...
  const MCPhysReg ACCRC[] = {
    PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3, PPC::ACC4, PPC::ACC5, PPC::ACC6, PPC::ACC7, 
  };

  // ACCRC Bit set.
  const uint8_t ACCRCBits[] = {
    0x00, 0xf8, 0x07, 
  };

  // UACCRC Register Class...
  const MCPhysReg UACCRC[] = {
    PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3, PPC::UACC4, PPC::UACC5, PPC::UACC6, PPC::UACC7, 
  };

  // UACCRC Bit set.
  const uint8_t UACCRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // WACCRC Register Class...
  const MCPhysReg WACCRC[] = {
    PPC::WACC0, PPC::WACC1, PPC::WACC2, PPC::WACC3, PPC::WACC4, PPC::WACC5, PPC::WACC6, PPC::WACC7, 
  };

  // WACCRC Bit set.
  const uint8_t WACCRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // WACC_HIRC Register Class...
  const MCPhysReg WACC_HIRC[] = {
    PPC::WACC_HI0, PPC::WACC_HI1, PPC::WACC_HI2, PPC::WACC_HI3, PPC::WACC_HI4, PPC::WACC_HI5, PPC::WACC_HI6, PPC::WACC_HI7, 
  };

  // WACC_HIRC Bit set.
  const uint8_t WACC_HIRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07, 
  };

  // ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
    PPC::ACC0, PPC::ACC1, PPC::ACC2, PPC::ACC3, 
  };

  // ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x78, 
  };

  // UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
    PPC::UACC0, PPC::UACC1, PPC::UACC2, PPC::UACC3, 
  };

  // UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78, 
  };

  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
    PPC::ACC0, PPC::ACC1, PPC::ACC2, 
  };

  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x38, 
  };

  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
  const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
    PPC::UACC0, PPC::UACC1, PPC::UACC2, 
  };

  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
  const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // DMRRC Register Class...
  const MCPhysReg DMRRC[] = {
    PPC::DMR0, PPC::DMR1, PPC::DMR2, PPC::DMR3, PPC::DMR4, PPC::DMR5, PPC::DMR6, PPC::DMR7, 
  };

  // DMRRC Bit set.
  const uint8_t DMRRCBits[] = {
    0x00, 0x00, 0x00, 0xe0, 0x1f, 
  };

  // DMRpRC Register Class...
  const MCPhysReg DMRpRC[] = {
    PPC::DMRp0, PPC::DMRp1, PPC::DMRp2, PPC::DMRp3, 
  };

  // DMRpRC Bit set.
  const uint8_t DMRpRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char PPCRegClassStrings[] = {
  /* 0 */ "GPRC_and_GPRC_NOR0\0"
  /* 19 */ "SPERC_with_sub_32_in_GPRC_NOR0\0"
  /* 50 */ "G8pRC_with_sub_32_in_GPRC_NOR0\0"
  /* 81 */ "G8RC_and_G8RC_NOX0\0"
  /* 100 */ "GPRC32\0"
  /* 107 */ "CTRRC8\0"
  /* 114 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC\0"
  /* 158 */ "VSRpRC_with_sub_64_in_F4RC\0"
  /* 185 */ "F8RC\0"
  /* 190 */ "G8RC\0"
  /* 195 */ "LR8RC\0"
  /* 201 */ "UACCRC\0"
  /* 208 */ "WACCRC\0"
  /* 215 */ "SPERC\0"
  /* 221 */ "VRSAVERC\0"
  /* 230 */ "SPILLTOVSRRC_and_VSFRC\0"
  /* 253 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC\0"
  /* 297 */ "VSRpRC_with_sub_64_in_VFRC\0"
  /* 324 */ "WACC_HIRC\0"
  /* 334 */ "VSLRC\0"
  /* 340 */ "GPRC\0"
  /* 345 */ "CRRC\0"
  /* 350 */ "LRRC\0"
  /* 355 */ "DMRRC\0"
  /* 361 */ "FpRC_with_sub_fp0_in_SPILLTOVSRRC\0"
  /* 395 */ "UACCRC_with_sub_64_in_SPILLTOVSRRC\0"
  /* 430 */ "VSLRC_with_sub_64_in_SPILLTOVSRRC\0"
  /* 464 */ "VRRC_with_sub_64_in_SPILLTOVSRRC\0"
  /* 497 */ "VSRC_with_sub_64_in_SPILLTOVSRRC\0"
  /* 530 */ "VSRpRC_with_sub_64_in_SPILLTOVSRRC\0"
  /* 565 */ "UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC\0"
  /* 615 */ "CTRRC\0"
  /* 621 */ "VRRC\0"
  /* 626 */ "VSSRC\0"
  /* 632 */ "VSRC\0"
  /* 637 */ "CRBITRC\0"
  /* 645 */ "DMRROWRC\0"
  /* 654 */ "CARRYRC\0"
  /* 662 */ "G8pRC\0"
  /* 668 */ "FpRC\0"
  /* 673 */ "DMRpRC\0"
  /* 680 */ "VSRpRC\0"
  /* 687 */ "DMRROWpRC\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass PPCMCRegisterClasses[] = {
  { VSSRC, VSSRCBits, 626, 64, sizeof(VSSRCBits), PPC::VSSRCRegClassID, 32, 1, true },
  { GPRC, GPRCBits, 340, 34, sizeof(GPRCBits), PPC::GPRCRegClassID, 32, 1, true },
  { GPRC_NOR0, GPRC_NOR0Bits, 9, 34, sizeof(GPRC_NOR0Bits), PPC::GPRC_NOR0RegClassID, 32, 1, true },
  { GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, 0, 33, sizeof(GPRC_and_GPRC_NOR0Bits), PPC::GPRC_and_GPRC_NOR0RegClassID, 32, 1, true },
  { CRBITRC, CRBITRCBits, 637, 32, sizeof(CRBITRCBits), PPC::CRBITRCRegClassID, 32, 1, true },
  { F4RC, F4RCBits, 153, 32, sizeof(F4RCBits), PPC::F4RCRegClassID, 32, 1, true },
  { GPRC32, GPRC32Bits, 100, 32, sizeof(GPRC32Bits), PPC::GPRC32RegClassID, 32, 1, false },
  { CRRC, CRRCBits, 345, 8, sizeof(CRRCBits), PPC::CRRCRegClassID, 32, 1, true },
  { CARRYRC, CARRYRCBits, 654, 2, sizeof(CARRYRCBits), PPC::CARRYRCRegClassID, 32, -1, true },
  { CTRRC, CTRRCBits, 615, 1, sizeof(CTRRCBits), PPC::CTRRCRegClassID, 32, 1, false },
  { LRRC, LRRCBits, 350, 1, sizeof(LRRCBits), PPC::LRRCRegClassID, 32, 1, false },
  { VRSAVERC, VRSAVERCBits, 221, 1, sizeof(VRSAVERCBits), PPC::VRSAVERCRegClassID, 32, 1, true },
  { SPILLTOVSRRC, SPILLTOVSRRCBits, 382, 68, sizeof(SPILLTOVSRRCBits), PPC::SPILLTOVSRRCRegClassID, 64, 1, true },
  { VSFRC, VSFRCBits, 247, 64, sizeof(VSFRCBits), PPC::VSFRCRegClassID, 64, 1, true },
  { G8RC, G8RCBits, 190, 34, sizeof(G8RCBits), PPC::G8RCRegClassID, 64, 1, true },
  { G8RC_NOX0, G8RC_NOX0Bits, 90, 34, sizeof(G8RC_NOX0Bits), PPC::G8RC_NOX0RegClassID, 64, 1, true },
  { SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, 230, 34, sizeof(SPILLTOVSRRC_and_VSFRCBits), PPC::SPILLTOVSRRC_and_VSFRCRegClassID, 64, 1, true },
  { G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, 81, 33, sizeof(G8RC_and_G8RC_NOX0Bits), PPC::G8RC_and_G8RC_NOX0RegClassID, 64, 1, true },
  { F8RC, F8RCBits, 185, 32, sizeof(F8RCBits), PPC::F8RCRegClassID, 64, 1, true },
  { SPERC, SPERCBits, 215, 32, sizeof(SPERCBits), PPC::SPERCRegClassID, 64, 1, true },
  { VFRC, VFRCBits, 292, 32, sizeof(VFRCBits), PPC::VFRCRegClassID, 64, 1, true },
  { SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, 19, 31, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits), PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClassID, 64, 1, true },
  { SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, 275, 20, sizeof(SPILLTOVSRRC_and_VFRCBits), PPC::SPILLTOVSRRC_and_VFRCRegClassID, 64, 1, true },
  { SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, 136, 14, sizeof(SPILLTOVSRRC_and_F4RCBits), PPC::SPILLTOVSRRC_and_F4RCRegClassID, 64, 1, true },
  { CTRRC8, CTRRC8Bits, 107, 1, sizeof(CTRRC8Bits), PPC::CTRRC8RegClassID, 64, 1, false },
  { LR8RC, LR8RCBits, 195, 1, sizeof(LR8RCBits), PPC::LR8RCRegClassID, 64, 1, false },
  { DMRROWRC, DMRROWRCBits, 645, 64, sizeof(DMRROWRCBits), PPC::DMRROWRCRegClassID, 128, 1, true },
  { VSRC, VSRCBits, 632, 64, sizeof(VSRCBits), PPC::VSRCRegClassID, 128, 1, true },
  { VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, 497, 34, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
  { VRRC, VRRCBits, 621, 32, sizeof(VRRCBits), PPC::VRRCRegClassID, 128, 1, true },
  { VSLRC, VSLRCBits, 334, 32, sizeof(VSLRCBits), PPC::VSLRCRegClassID, 128, 1, true },
  { VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, 464, 20, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
  { FpRC, FpRCBits, 668, 16, sizeof(FpRCBits), PPC::FpRCRegClassID, 128, 1, true },
  { G8pRC, G8pRCBits, 662, 16, sizeof(G8pRCBits), PPC::G8pRCRegClassID, 128, 1, true },
  { G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, 50, 15, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits), PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID, 128, 1, true },
  { VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, 430, 14, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 128, 1, true },
  { FpRC_with_sub_fp0_in_SPILLTOVSRRC, FpRC_with_sub_fp0_in_SPILLTOVSRRCBits, 361, 7, sizeof(FpRC_with_sub_fp0_in_SPILLTOVSRRCBits), PPC::FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID, 128, 1, true },
  { DMRROWpRC, DMRROWpRCBits, 687, 32, sizeof(DMRROWpRCBits), PPC::DMRROWpRCRegClassID, 256, 1, true },
  { VSRpRC, VSRpRCBits, 680, 32, sizeof(VSRpRCBits), PPC::VSRpRCRegClassID, 256, 1, true },
  { VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, 530, 17, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 256, 1, true },
  { VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, 158, 16, sizeof(VSRpRC_with_sub_64_in_F4RCBits), PPC::VSRpRC_with_sub_64_in_F4RCRegClassID, 256, 1, true },
  { VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, 297, 16, sizeof(VSRpRC_with_sub_64_in_VFRCBits), PPC::VSRpRC_with_sub_64_in_VFRCRegClassID, 256, 1, true },
  { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, 253, 10, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID, 256, 1, true },
  { VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, 114, 7, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits), PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID, 256, 1, true },
  { ACCRC, ACCRCBits, 202, 8, sizeof(ACCRCBits), PPC::ACCRCRegClassID, 512, 1, true },
  { UACCRC, UACCRCBits, 201, 8, sizeof(UACCRCBits), PPC::UACCRCRegClassID, 512, 1, true },
  { WACCRC, WACCRCBits, 208, 8, sizeof(WACCRCBits), PPC::WACCRCRegClassID, 512, 1, true },
  { WACC_HIRC, WACC_HIRCBits, 324, 8, sizeof(WACC_HIRCBits), PPC::WACC_HIRCRegClassID, 512, 1, true },
  { ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, 396, 4, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
  { UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, 395, 4, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
  { ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 566, 3, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
  { UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, 565, 3, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits), PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID, 512, 1, true },
  { DMRRC, DMRRCBits, 355, 8, sizeof(DMRRCBits), PPC::DMRRCRegClassID, 1024, 1, true },
  { DMRpRC, DMRpRCBits, 673, 4, sizeof(DMRpRCBits), PPC::DMRpRCRegClassID, 2048, 1, true },
};

// PPC Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[] = {
  { 0U, PPC::X0 },
  { 1U, PPC::X1 },
  { 2U, PPC::X2 },
  { 3U, PPC::X3 },
  { 4U, PPC::X4 },
  { 5U, PPC::X5 },
  { 6U, PPC::X6 },
  { 7U, PPC::X7 },
  { 8U, PPC::X8 },
  { 9U, PPC::X9 },
  { 10U, PPC::X10 },
  { 11U, PPC::X11 },
  { 12U, PPC::X12 },
  { 13U, PPC::X13 },
  { 14U, PPC::X14 },
  { 15U, PPC::X15 },
  { 16U, PPC::X16 },
  { 17U, PPC::X17 },
  { 18U, PPC::X18 },
  { 19U, PPC::X19 },
  { 20U, PPC::X20 },
  { 21U, PPC::X21 },
  { 22U, PPC::X22 },
  { 23U, PPC::X23 },
  { 24U, PPC::X24 },
  { 25U, PPC::X25 },
  { 26U, PPC::X26 },
  { 27U, PPC::X27 },
  { 28U, PPC::X28 },
  { 29U, PPC::X29 },
  { 30U, PPC::X30 },
  { 31U, PPC::X31 },
  { 32U, PPC::F0 },
  { 33U, PPC::F1 },
  { 34U, PPC::F2 },
  { 35U, PPC::F3 },
  { 36U, PPC::F4 },
  { 37U, PPC::F5 },
  { 38U, PPC::F6 },
  { 39U, PPC::F7 },
  { 40U, PPC::F8 },
  { 41U, PPC::F9 },
  { 42U, PPC::F10 },
  { 43U, PPC::F11 },
  { 44U, PPC::F12 },
  { 45U, PPC::F13 },
  { 46U, PPC::F14 },
  { 47U, PPC::F15 },
  { 48U, PPC::F16 },
  { 49U, PPC::F17 },
  { 50U, PPC::F18 },
  { 51U, PPC::F19 },
  { 52U, PPC::F20 },
  { 53U, PPC::F21 },
  { 54U, PPC::F22 },
  { 55U, PPC::F23 },
  { 56U, PPC::F24 },
  { 57U, PPC::F25 },
  { 58U, PPC::F26 },
  { 59U, PPC::F27 },
  { 60U, PPC::F28 },
  { 61U, PPC::F29 },
  { 62U, PPC::F30 },
  { 63U, PPC::F31 },
  { 65U, PPC::LR8 },
  { 66U, PPC::CTR8 },
  { 68U, PPC::CR0 },
  { 69U, PPC::CR1 },
  { 70U, PPC::CR2 },
  { 71U, PPC::CR3 },
  { 72U, PPC::CR4 },
  { 73U, PPC::CR5 },
  { 74U, PPC::CR6 },
  { 75U, PPC::CR7 },
  { 76U, PPC::XER },
  { 77U, PPC::VF0 },
  { 78U, PPC::VF1 },
  { 79U, PPC::VF2 },
  { 80U, PPC::VF3 },
  { 81U, PPC::VF4 },
  { 82U, PPC::VF5 },
  { 83U, PPC::VF6 },
  { 84U, PPC::VF7 },
  { 85U, PPC::VF8 },
  { 86U, PPC::VF9 },
  { 87U, PPC::VF10 },
  { 88U, PPC::VF11 },
  { 89U, PPC::VF12 },
  { 90U, PPC::VF13 },
  { 91U, PPC::VF14 },
  { 92U, PPC::VF15 },
  { 93U, PPC::VF16 },
  { 94U, PPC::VF17 },
  { 95U, PPC::VF18 },
  { 96U, PPC::VF19 },
  { 97U, PPC::VF20 },
  { 98U, PPC::VF21 },
  { 99U, PPC::VF22 },
  { 100U, PPC::VF23 },
  { 101U, PPC::VF24 },
  { 102U, PPC::VF25 },
  { 103U, PPC::VF26 },
  { 104U, PPC::VF27 },
  { 105U, PPC::VF28 },
  { 106U, PPC::VF29 },
  { 107U, PPC::VF30 },
  { 108U, PPC::VF31 },
  { 109U, PPC::VRSAVE },
  { 612U, PPC::SPEFSCR },
  { 1200U, PPC::S0 },
  { 1201U, PPC::S1 },
  { 1202U, PPC::S2 },
  { 1203U, PPC::S3 },
  { 1204U, PPC::S4 },
  { 1205U, PPC::S5 },
  { 1206U, PPC::S6 },
  { 1207U, PPC::S7 },
  { 1208U, PPC::S8 },
  { 1209U, PPC::S9 },
  { 1210U, PPC::S10 },
  { 1211U, PPC::S11 },
  { 1212U, PPC::S12 },
  { 1213U, PPC::S13 },
  { 1214U, PPC::S14 },
  { 1215U, PPC::S15 },
  { 1216U, PPC::S16 },
  { 1217U, PPC::S17 },
  { 1218U, PPC::S18 },
  { 1219U, PPC::S19 },
  { 1220U, PPC::S20 },
  { 1221U, PPC::S21 },
  { 1222U, PPC::S22 },
  { 1223U, PPC::S23 },
  { 1224U, PPC::S24 },
  { 1225U, PPC::S25 },
  { 1226U, PPC::S26 },
  { 1227U, PPC::S27 },
  { 1228U, PPC::S28 },
  { 1229U, PPC::S29 },
  { 1230U, PPC::S30 },
  { 1231U, PPC::S31 },
};
extern const unsigned PPCDwarfFlavour0Dwarf2LSize = std::size(PPCDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[] = {
  { 0U, PPC::R0 },
  { 1U, PPC::R1 },
  { 2U, PPC::R2 },
  { 3U, PPC::R3 },
  { 4U, PPC::R4 },
  { 5U, PPC::R5 },
  { 6U, PPC::R6 },
  { 7U, PPC::R7 },
  { 8U, PPC::R8 },
  { 9U, PPC::R9 },
  { 10U, PPC::R10 },
  { 11U, PPC::R11 },
  { 12U, PPC::R12 },
  { 13U, PPC::R13 },
  { 14U, PPC::R14 },
  { 15U, PPC::R15 },
  { 16U, PPC::R16 },
  { 17U, PPC::R17 },
  { 18U, PPC::R18 },
  { 19U, PPC::R19 },
  { 20U, PPC::R20 },
  { 21U, PPC::R21 },
  { 22U, PPC::R22 },
  { 23U, PPC::R23 },
  { 24U, PPC::R24 },
  { 25U, PPC::R25 },
  { 26U, PPC::R26 },
  { 27U, PPC::R27 },
  { 28U, PPC::R28 },
  { 29U, PPC::R29 },
  { 30U, PPC::R30 },
  { 31U, PPC::R31 },
  { 32U, PPC::F0 },
  { 33U, PPC::F1 },
  { 34U, PPC::F2 },
  { 35U, PPC::F3 },
  { 36U, PPC::F4 },
  { 37U, PPC::F5 },
  { 38U, PPC::F6 },
  { 39U, PPC::F7 },
  { 40U, PPC::F8 },
  { 41U, PPC::F9 },
  { 42U, PPC::F10 },
  { 43U, PPC::F11 },
  { 44U, PPC::F12 },
  { 45U, PPC::F13 },
  { 46U, PPC::F14 },
  { 47U, PPC::F15 },
  { 48U, PPC::F16 },
  { 49U, PPC::F17 },
  { 50U, PPC::F18 },
  { 51U, PPC::F19 },
  { 52U, PPC::F20 },
  { 53U, PPC::F21 },
  { 54U, PPC::F22 },
  { 55U, PPC::F23 },
  { 56U, PPC::F24 },
  { 57U, PPC::F25 },
  { 58U, PPC::F26 },
  { 59U, PPC::F27 },
  { 60U, PPC::F28 },
  { 61U, PPC::F29 },
  { 62U, PPC::F30 },
  { 63U, PPC::F31 },
  { 65U, PPC::LR },
  { 66U, PPC::CTR },
  { 68U, PPC::CR0 },
  { 69U, PPC::CR1 },
  { 70U, PPC::CR2 },
  { 71U, PPC::CR3 },
  { 72U, PPC::CR4 },
  { 73U, PPC::CR5 },
  { 74U, PPC::CR6 },
  { 75U, PPC::CR7 },
  { 77U, PPC::VF0 },
  { 78U, PPC::VF1 },
  { 79U, PPC::VF2 },
  { 80U, PPC::VF3 },
  { 81U, PPC::VF4 },
  { 82U, PPC::VF5 },
  { 83U, PPC::VF6 },
  { 84U, PPC::VF7 },
  { 85U, PPC::VF8 },
  { 86U, PPC::VF9 },
  { 87U, PPC::VF10 },
  { 88U, PPC::VF11 },
  { 89U, PPC::VF12 },
  { 90U, PPC::VF13 },
  { 91U, PPC::VF14 },
  { 92U, PPC::VF15 },
  { 93U, PPC::VF16 },
  { 94U, PPC::VF17 },
  { 95U, PPC::VF18 },
  { 96U, PPC::VF19 },
  { 97U, PPC::VF20 },
  { 98U, PPC::VF21 },
  { 99U, PPC::VF22 },
  { 100U, PPC::VF23 },
  { 101U, PPC::VF24 },
  { 102U, PPC::VF25 },
  { 103U, PPC::VF26 },
  { 104U, PPC::VF27 },
  { 105U, PPC::VF28 },
  { 106U, PPC::VF29 },
  { 107U, PPC::VF30 },
  { 108U, PPC::VF31 },
  { 112U, PPC::SPEFSCR },
  { 1200U, PPC::S0 },
  { 1201U, PPC::S1 },
  { 1202U, PPC::S2 },
  { 1203U, PPC::S3 },
  { 1204U, PPC::S4 },
  { 1205U, PPC::S5 },
  { 1206U, PPC::S6 },
  { 1207U, PPC::S7 },
  { 1208U, PPC::S8 },
  { 1209U, PPC::S9 },
  { 1210U, PPC::S10 },
  { 1211U, PPC::S11 },
  { 1212U, PPC::S12 },
  { 1213U, PPC::S13 },
  { 1214U, PPC::S14 },
  { 1215U, PPC::S15 },
  { 1216U, PPC::S16 },
  { 1217U, PPC::S17 },
  { 1218U, PPC::S18 },
  { 1219U, PPC::S19 },
  { 1220U, PPC::S20 },
  { 1221U, PPC::S21 },
  { 1222U, PPC::S22 },
  { 1223U, PPC::S23 },
  { 1224U, PPC::S24 },
  { 1225U, PPC::S25 },
  { 1226U, PPC::S26 },
  { 1227U, PPC::S27 },
  { 1228U, PPC::S28 },
  { 1229U, PPC::S29 },
  { 1230U, PPC::S30 },
  { 1231U, PPC::S31 },
};
extern const unsigned PPCDwarfFlavour1Dwarf2LSize = std::size(PPCDwarfFlavour1Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[] = {
  { 0U, PPC::X0 },
  { 1U, PPC::X1 },
  { 2U, PPC::X2 },
  { 3U, PPC::X3 },
  { 4U, PPC::X4 },
  { 5U, PPC::X5 },
  { 6U, PPC::X6 },
  { 7U, PPC::X7 },
  { 8U, PPC::X8 },
  { 9U, PPC::X9 },
  { 10U, PPC::X10 },
  { 11U, PPC::X11 },
  { 12U, PPC::X12 },
  { 13U, PPC::X13 },
  { 14U, PPC::X14 },
  { 15U, PPC::X15 },
  { 16U, PPC::X16 },
  { 17U, PPC::X17 },
  { 18U, PPC::X18 },
  { 19U, PPC::X19 },
  { 20U, PPC::X20 },
  { 21U, PPC::X21 },
  { 22U, PPC::X22 },
  { 23U, PPC::X23 },
  { 24U, PPC::X24 },
  { 25U, PPC::X25 },
  { 26U, PPC::X26 },
  { 27U, PPC::X27 },
  { 28U, PPC::X28 },
  { 29U, PPC::X29 },
  { 30U, PPC::X30 },
  { 31U, PPC::X31 },
  { 32U, PPC::F0 },
  { 33U, PPC::F1 },
  { 34U, PPC::F2 },
  { 35U, PPC::F3 },
  { 36U, PPC::F4 },
  { 37U, PPC::F5 },
  { 38U, PPC::F6 },
  { 39U, PPC::F7 },
  { 40U, PPC::F8 },
  { 41U, PPC::F9 },
  { 42U, PPC::F10 },
  { 43U, PPC::F11 },
  { 44U, PPC::F12 },
  { 45U, PPC::F13 },
  { 46U, PPC::F14 },
  { 47U, PPC::F15 },
  { 48U, PPC::F16 },
  { 49U, PPC::F17 },
  { 50U, PPC::F18 },
  { 51U, PPC::F19 },
  { 52U, PPC::F20 },
  { 53U, PPC::F21 },
  { 54U, PPC::F22 },
  { 55U, PPC::F23 },
  { 56U, PPC::F24 },
  { 57U, PPC::F25 },
  { 58U, PPC::F26 },
  { 59U, PPC::F27 },
  { 60U, PPC::F28 },
  { 61U, PPC::F29 },
  { 62U, PPC::F30 },
  { 63U, PPC::F31 },
  { 65U, PPC::LR8 },
  { 66U, PPC::CTR8 },
  { 68U, PPC::CR0 },
  { 69U, PPC::CR1 },
  { 70U, PPC::CR2 },
  { 71U, PPC::CR3 },
  { 72U, PPC::CR4 },
  { 73U, PPC::CR5 },
  { 74U, PPC::CR6 },
  { 75U, PPC::CR7 },
  { 76U, PPC::XER },
  { 77U, PPC::VF0 },
  { 78U, PPC::VF1 },
  { 79U, PPC::VF2 },
  { 80U, PPC::VF3 },
  { 81U, PPC::VF4 },
  { 82U, PPC::VF5 },
  { 83U, PPC::VF6 },
  { 84U, PPC::VF7 },
  { 85U, PPC::VF8 },
  { 86U, PPC::VF9 },
  { 87U, PPC::VF10 },
  { 88U, PPC::VF11 },
  { 89U, PPC::VF12 },
  { 90U, PPC::VF13 },
  { 91U, PPC::VF14 },
  { 92U, PPC::VF15 },
  { 93U, PPC::VF16 },
  { 94U, PPC::VF17 },
  { 95U, PPC::VF18 },
  { 96U, PPC::VF19 },
  { 97U, PPC::VF20 },
  { 98U, PPC::VF21 },
  { 99U, PPC::VF22 },
  { 100U, PPC::VF23 },
  { 101U, PPC::VF24 },
  { 102U, PPC::VF25 },
  { 103U, PPC::VF26 },
  { 104U, PPC::VF27 },
  { 105U, PPC::VF28 },
  { 106U, PPC::VF29 },
  { 107U, PPC::VF30 },
  { 108U, PPC::VF31 },
  { 109U, PPC::VRSAVE },
  { 612U, PPC::SPEFSCR },
  { 1200U, PPC::S0 },
  { 1201U, PPC::S1 },
  { 1202U, PPC::S2 },
  { 1203U, PPC::S3 },
  { 1204U, PPC::S4 },
  { 1205U, PPC::S5 },
  { 1206U, PPC::S6 },
  { 1207U, PPC::S7 },
  { 1208U, PPC::S8 },
  { 1209U, PPC::S9 },
  { 1210U, PPC::S10 },
  { 1211U, PPC::S11 },
  { 1212U, PPC::S12 },
  { 1213U, PPC::S13 },
  { 1214U, PPC::S14 },
  { 1215U, PPC::S15 },
  { 1216U, PPC::S16 },
  { 1217U, PPC::S17 },
  { 1218U, PPC::S18 },
  { 1219U, PPC::S19 },
  { 1220U, PPC::S20 },
  { 1221U, PPC::S21 },
  { 1222U, PPC::S22 },
  { 1223U, PPC::S23 },
  { 1224U, PPC::S24 },
  { 1225U, PPC::S25 },
  { 1226U, PPC::S26 },
  { 1227U, PPC::S27 },
  { 1228U, PPC::S28 },
  { 1229U, PPC::S29 },
  { 1230U, PPC::S30 },
  { 1231U, PPC::S31 },
};
extern const unsigned PPCEHFlavour0Dwarf2LSize = std::size(PPCEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[] = {
  { 0U, PPC::R0 },
  { 1U, PPC::R1 },
  { 2U, PPC::R2 },
  { 3U, PPC::R3 },
  { 4U, PPC::R4 },
  { 5U, PPC::R5 },
  { 6U, PPC::R6 },
  { 7U, PPC::R7 },
  { 8U, PPC::R8 },
  { 9U, PPC::R9 },
  { 10U, PPC::R10 },
  { 11U, PPC::R11 },
  { 12U, PPC::R12 },
  { 13U, PPC::R13 },
  { 14U, PPC::R14 },
  { 15U, PPC::R15 },
  { 16U, PPC::R16 },
  { 17U, PPC::R17 },
  { 18U, PPC::R18 },
  { 19U, PPC::R19 },
  { 20U, PPC::R20 },
  { 21U, PPC::R21 },
  { 22U, PPC::R22 },
  { 23U, PPC::R23 },
  { 24U, PPC::R24 },
  { 25U, PPC::R25 },
  { 26U, PPC::R26 },
  { 27U, PPC::R27 },
  { 28U, PPC::R28 },
  { 29U, PPC::R29 },
  { 30U, PPC::R30 },
  { 31U, PPC::R31 },
  { 32U, PPC::F0 },
  { 33U, PPC::F1 },
  { 34U, PPC::F2 },
  { 35U, PPC::F3 },
  { 36U, PPC::F4 },
  { 37U, PPC::F5 },
  { 38U, PPC::F6 },
  { 39U, PPC::F7 },
  { 40U, PPC::F8 },
  { 41U, PPC::F9 },
  { 42U, PPC::F10 },
  { 43U, PPC::F11 },
  { 44U, PPC::F12 },
  { 45U, PPC::F13 },
  { 46U, PPC::F14 },
  { 47U, PPC::F15 },
  { 48U, PPC::F16 },
  { 49U, PPC::F17 },
  { 50U, PPC::F18 },
  { 51U, PPC::F19 },
  { 52U, PPC::F20 },
  { 53U, PPC::F21 },
  { 54U, PPC::F22 },
  { 55U, PPC::F23 },
  { 56U, PPC::F24 },
  { 57U, PPC::F25 },
  { 58U, PPC::F26 },
  { 59U, PPC::F27 },
  { 60U, PPC::F28 },
  { 61U, PPC::F29 },
  { 62U, PPC::F30 },
  { 63U, PPC::F31 },
  { 65U, PPC::LR },
  { 66U, PPC::CTR },
  { 68U, PPC::CR0 },
  { 69U, PPC::CR1 },
  { 70U, PPC::CR2 },
  { 71U, PPC::CR3 },
  { 72U, PPC::CR4 },
  { 73U, PPC::CR5 },
  { 74U, PPC::CR6 },
  { 75U, PPC::CR7 },
  { 77U, PPC::VF0 },
  { 78U, PPC::VF1 },
  { 79U, PPC::VF2 },
  { 80U, PPC::VF3 },
  { 81U, PPC::VF4 },
  { 82U, PPC::VF5 },
  { 83U, PPC::VF6 },
  { 84U, PPC::VF7 },
  { 85U, PPC::VF8 },
  { 86U, PPC::VF9 },
  { 87U, PPC::VF10 },
  { 88U, PPC::VF11 },
  { 89U, PPC::VF12 },
  { 90U, PPC::VF13 },
  { 91U, PPC::VF14 },
  { 92U, PPC::VF15 },
  { 93U, PPC::VF16 },
  { 94U, PPC::VF17 },
  { 95U, PPC::VF18 },
  { 96U, PPC::VF19 },
  { 97U, PPC::VF20 },
  { 98U, PPC::VF21 },
  { 99U, PPC::VF22 },
  { 100U, PPC::VF23 },
  { 101U, PPC::VF24 },
  { 102U, PPC::VF25 },
  { 103U, PPC::VF26 },
  { 104U, PPC::VF27 },
  { 105U, PPC::VF28 },
  { 106U, PPC::VF29 },
  { 107U, PPC::VF30 },
  { 108U, PPC::VF31 },
  { 112U, PPC::SPEFSCR },
  { 1200U, PPC::S0 },
  { 1201U, PPC::S1 },
  { 1202U, PPC::S2 },
  { 1203U, PPC::S3 },
  { 1204U, PPC::S4 },
  { 1205U, PPC::S5 },
  { 1206U, PPC::S6 },
  { 1207U, PPC::S7 },
  { 1208U, PPC::S8 },
  { 1209U, PPC::S9 },
  { 1210U, PPC::S10 },
  { 1211U, PPC::S11 },
  { 1212U, PPC::S12 },
  { 1213U, PPC::S13 },
  { 1214U, PPC::S14 },
  { 1215U, PPC::S15 },
  { 1216U, PPC::S16 },
  { 1217U, PPC::S17 },
  { 1218U, PPC::S18 },
  { 1219U, PPC::S19 },
  { 1220U, PPC::S20 },
  { 1221U, PPC::S21 },
  { 1222U, PPC::S22 },
  { 1223U, PPC::S23 },
  { 1224U, PPC::S24 },
  { 1225U, PPC::S25 },
  { 1226U, PPC::S26 },
  { 1227U, PPC::S27 },
  { 1228U, PPC::S28 },
  { 1229U, PPC::S29 },
  { 1230U, PPC::S30 },
  { 1231U, PPC::S31 },
};
extern const unsigned PPCEHFlavour1Dwarf2LSize = std::size(PPCEHFlavour1Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[] = {
  { PPC::CARRY, 76U },
  { PPC::CTR, -2U },
  { PPC::LR, -2U },
  { PPC::SPEFSCR, 612U },
  { PPC::VRSAVE, 109U },
  { PPC::XER, 76U },
  { PPC::ZERO, -2U },
  { PPC::CR0, 68U },
  { PPC::CR1, 69U },
  { PPC::CR2, 70U },
  { PPC::CR3, 71U },
  { PPC::CR4, 72U },
  { PPC::CR5, 73U },
  { PPC::CR6, 74U },
  { PPC::CR7, 75U },
  { PPC::CTR8, 66U },
  { PPC::F0, 32U },
  { PPC::F1, 33U },
  { PPC::F2, 34U },
  { PPC::F3, 35U },
  { PPC::F4, 36U },
  { PPC::F5, 37U },
  { PPC::F6, 38U },
  { PPC::F7, 39U },
  { PPC::F8, 40U },
  { PPC::F9, 41U },
  { PPC::F10, 42U },
  { PPC::F11, 43U },
  { PPC::F12, 44U },
  { PPC::F13, 45U },
  { PPC::F14, 46U },
  { PPC::F15, 47U },
  { PPC::F16, 48U },
  { PPC::F17, 49U },
  { PPC::F18, 50U },
  { PPC::F19, 51U },
  { PPC::F20, 52U },
  { PPC::F21, 53U },
  { PPC::F22, 54U },
  { PPC::F23, 55U },
  { PPC::F24, 56U },
  { PPC::F25, 57U },
  { PPC::F26, 58U },
  { PPC::F27, 59U },
  { PPC::F28, 60U },
  { PPC::F29, 61U },
  { PPC::F30, 62U },
  { PPC::F31, 63U },
  { PPC::LR8, 65U },
  { PPC::R0, -2U },
  { PPC::R1, -2U },
  { PPC::R2, -2U },
  { PPC::R3, -2U },
  { PPC::R4, -2U },
  { PPC::R5, -2U },
  { PPC::R6, -2U },
  { PPC::R7, -2U },
  { PPC::R8, -2U },
  { PPC::R9, -2U },
  { PPC::R10, -2U },
  { PPC::R11, -2U },
  { PPC::R12, -2U },
  { PPC::R13, -2U },
  { PPC::R14, -2U },
  { PPC::R15, -2U },
  { PPC::R16, -2U },
  { PPC::R17, -2U },
  { PPC::R18, -2U },
  { PPC::R19, -2U },
  { PPC::R20, -2U },
  { PPC::R21, -2U },
  { PPC::R22, -2U },
  { PPC::R23, -2U },
  { PPC::R24, -2U },
  { PPC::R25, -2U },
  { PPC::R26, -2U },
  { PPC::R27, -2U },
  { PPC::R28, -2U },
  { PPC::R29, -2U },
  { PPC::R30, -2U },
  { PPC::R31, -2U },
  { PPC::S0, 1200U },
  { PPC::S1, 1201U },
  { PPC::S2, 1202U },
  { PPC::S3, 1203U },
  { PPC::S4, 1204U },
  { PPC::S5, 1205U },
  { PPC::S6, 1206U },
  { PPC::S7, 1207U },
  { PPC::S8, 1208U },
  { PPC::S9, 1209U },
  { PPC::S10, 1210U },
  { PPC::S11, 1211U },
  { PPC::S12, 1212U },
  { PPC::S13, 1213U },
  { PPC::S14, 1214U },
  { PPC::S15, 1215U },
  { PPC::S16, 1216U },
  { PPC::S17, 1217U },
  { PPC::S18, 1218U },
  { PPC::S19, 1219U },
  { PPC::S20, 1220U },
  { PPC::S21, 1221U },
  { PPC::S22, 1222U },
  { PPC::S23, 1223U },
  { PPC::S24, 1224U },
  { PPC::S25, 1225U },
  { PPC::S26, 1226U },
  { PPC::S27, 1227U },
  { PPC::S28, 1228U },
  { PPC::S29, 1229U },
  { PPC::S30, 1230U },
  { PPC::S31, 1231U },
  { PPC::V0, 77U },
  { PPC::V1, 78U },
  { PPC::V2, 79U },
  { PPC::V3, 80U },
  { PPC::V4, 81U },
  { PPC::V5, 82U },
  { PPC::V6, 83U },
  { PPC::V7, 84U },
  { PPC::V8, 85U },
  { PPC::V9, 86U },
  { PPC::V10, 87U },
  { PPC::V11, 88U },
  { PPC::V12, 89U },
  { PPC::V13, 90U },
  { PPC::V14, 91U },
  { PPC::V15, 92U },
  { PPC::V16, 93U },
  { PPC::V17, 94U },
  { PPC::V18, 95U },
  { PPC::V19, 96U },
  { PPC::V20, 97U },
  { PPC::V21, 98U },
  { PPC::V22, 99U },
  { PPC::V23, 100U },
  { PPC::V24, 101U },
  { PPC::V25, 102U },
  { PPC::V26, 103U },
  { PPC::V27, 104U },
  { PPC::V28, 105U },
  { PPC::V29, 106U },
  { PPC::V30, 107U },
  { PPC::V31, 108U },
  { PPC::VF0, 77U },
  { PPC::VF1, 78U },
  { PPC::VF2, 79U },
  { PPC::VF3, 80U },
  { PPC::VF4, 81U },
  { PPC::VF5, 82U },
  { PPC::VF6, 83U },
  { PPC::VF7, 84U },
  { PPC::VF8, 85U },
  { PPC::VF9, 86U },
  { PPC::VF10, 87U },
  { PPC::VF11, 88U },
  { PPC::VF12, 89U },
  { PPC::VF13, 90U },
  { PPC::VF14, 91U },
  { PPC::VF15, 92U },
  { PPC::VF16, 93U },
  { PPC::VF17, 94U },
  { PPC::VF18, 95U },
  { PPC::VF19, 96U },
  { PPC::VF20, 97U },
  { PPC::VF21, 98U },
  { PPC::VF22, 99U },
  { PPC::VF23, 100U },
  { PPC::VF24, 101U },
  { PPC::VF25, 102U },
  { PPC::VF26, 103U },
  { PPC::VF27, 104U },
  { PPC::VF28, 105U },
  { PPC::VF29, 106U },
  { PPC::VF30, 107U },
  { PPC::VF31, 108U },
  { PPC::VSL0, 32U },
  { PPC::VSL1, 33U },
  { PPC::VSL2, 34U },
  { PPC::VSL3, 35U },
  { PPC::VSL4, 36U },
  { PPC::VSL5, 37U },
  { PPC::VSL6, 38U },
  { PPC::VSL7, 39U },
  { PPC::VSL8, 40U },
  { PPC::VSL9, 41U },
  { PPC::VSL10, 42U },
  { PPC::VSL11, 43U },
  { PPC::VSL12, 44U },
  { PPC::VSL13, 45U },
  { PPC::VSL14, 46U },
  { PPC::VSL15, 47U },
  { PPC::VSL16, 48U },
  { PPC::VSL17, 49U },
  { PPC::VSL18, 50U },
  { PPC::VSL19, 51U },
  { PPC::VSL20, 52U },
  { PPC::VSL21, 53U },
  { PPC::VSL22, 54U },
  { PPC::VSL23, 55U },
  { PPC::VSL24, 56U },
  { PPC::VSL25, 57U },
  { PPC::VSL26, 58U },
  { PPC::VSL27, 59U },
  { PPC::VSL28, 60U },
  { PPC::VSL29, 61U },
  { PPC::VSL30, 62U },
  { PPC::VSL31, 63U },
  { PPC::X0, 0U },
  { PPC::X1, 1U },
  { PPC::X2, 2U },
  { PPC::X3, 3U },
  { PPC::X4, 4U },
  { PPC::X5, 5U },
  { PPC::X6, 6U },
  { PPC::X7, 7U },
  { PPC::X8, 8U },
  { PPC::X9, 9U },
  { PPC::X10, 10U },
  { PPC::X11, 11U },
  { PPC::X12, 12U },
  { PPC::X13, 13U },
  { PPC::X14, 14U },
  { PPC::X15, 15U },
  { PPC::X16, 16U },
  { PPC::X17, 17U },
  { PPC::X18, 18U },
  { PPC::X19, 19U },
  { PPC::X20, 20U },
  { PPC::X21, 21U },
  { PPC::X22, 22U },
  { PPC::X23, 23U },
  { PPC::X24, 24U },
  { PPC::X25, 25U },
  { PPC::X26, 26U },
  { PPC::X27, 27U },
  { PPC::X28, 28U },
  { PPC::X29, 29U },
  { PPC::X30, 30U },
  { PPC::X31, 31U },
  { PPC::ZERO8, 0U },
};
extern const unsigned PPCDwarfFlavour0L2DwarfSize = std::size(PPCDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[] = {
  { PPC::CTR, 66U },
  { PPC::LR, 65U },
  { PPC::SPEFSCR, 112U },
  { PPC::ZERO, 0U },
  { PPC::CR0, 68U },
  { PPC::CR1, 69U },
  { PPC::CR2, 70U },
  { PPC::CR3, 71U },
  { PPC::CR4, 72U },
  { PPC::CR5, 73U },
  { PPC::CR6, 74U },
  { PPC::CR7, 75U },
  { PPC::CTR8, -2U },
  { PPC::F0, 32U },
  { PPC::F1, 33U },
  { PPC::F2, 34U },
  { PPC::F3, 35U },
  { PPC::F4, 36U },
  { PPC::F5, 37U },
  { PPC::F6, 38U },
  { PPC::F7, 39U },
  { PPC::F8, 40U },
  { PPC::F9, 41U },
  { PPC::F10, 42U },
  { PPC::F11, 43U },
  { PPC::F12, 44U },
  { PPC::F13, 45U },
  { PPC::F14, 46U },
  { PPC::F15, 47U },
  { PPC::F16, 48U },
  { PPC::F17, 49U },
  { PPC::F18, 50U },
  { PPC::F19, 51U },
  { PPC::F20, 52U },
  { PPC::F21, 53U },
  { PPC::F22, 54U },
  { PPC::F23, 55U },
  { PPC::F24, 56U },
  { PPC::F25, 57U },
  { PPC::F26, 58U },
  { PPC::F27, 59U },
  { PPC::F28, 60U },
  { PPC::F29, 61U },
  { PPC::F30, 62U },
  { PPC::F31, 63U },
  { PPC::LR8, -2U },
  { PPC::R0, 0U },
  { PPC::R1, 1U },
  { PPC::R2, 2U },
  { PPC::R3, 3U },
  { PPC::R4, 4U },
  { PPC::R5, 5U },
  { PPC::R6, 6U },
  { PPC::R7, 7U },
  { PPC::R8, 8U },
  { PPC::R9, 9U },
  { PPC::R10, 10U },
  { PPC::R11, 11U },
  { PPC::R12, 12U },
  { PPC::R13, 13U },
  { PPC::R14, 14U },
  { PPC::R15, 15U },
  { PPC::R16, 16U },
  { PPC::R17, 17U },
  { PPC::R18, 18U },
  { PPC::R19, 19U },
  { PPC::R20, 20U },
  { PPC::R21, 21U },
  { PPC::R22, 22U },
  { PPC::R23, 23U },
  { PPC::R24, 24U },
  { PPC::R25, 25U },
  { PPC::R26, 26U },
  { PPC::R27, 27U },
  { PPC::R28, 28U },
  { PPC::R29, 29U },
  { PPC::R30, 30U },
  { PPC::R31, 31U },
  { PPC::S0, 1200U },
  { PPC::S1, 1201U },
  { PPC::S2, 1202U },
  { PPC::S3, 1203U },
  { PPC::S4, 1204U },
  { PPC::S5, 1205U },
  { PPC::S6, 1206U },
  { PPC::S7, 1207U },
  { PPC::S8, 1208U },
  { PPC::S9, 1209U },
  { PPC::S10, 1210U },
  { PPC::S11, 1211U },
  { PPC::S12, 1212U },
  { PPC::S13, 1213U },
  { PPC::S14, 1214U },
  { PPC::S15, 1215U },
  { PPC::S16, 1216U },
  { PPC::S17, 1217U },
  { PPC::S18, 1218U },
  { PPC::S19, 1219U },
  { PPC::S20, 1220U },
  { PPC::S21, 1221U },
  { PPC::S22, 1222U },
  { PPC::S23, 1223U },
  { PPC::S24, 1224U },
  { PPC::S25, 1225U },
  { PPC::S26, 1226U },
  { PPC::S27, 1227U },
  { PPC::S28, 1228U },
  { PPC::S29, 1229U },
  { PPC::S30, 1230U },
  { PPC::S31, 1231U },
  { PPC::V0, 77U },
  { PPC::V1, 78U },
  { PPC::V2, 79U },
  { PPC::V3, 80U },
  { PPC::V4, 81U },
  { PPC::V5, 82U },
  { PPC::V6, 83U },
  { PPC::V7, 84U },
  { PPC::V8, 85U },
  { PPC::V9, 86U },
  { PPC::V10, 87U },
  { PPC::V11, 88U },
  { PPC::V12, 89U },
  { PPC::V13, 90U },
  { PPC::V14, 91U },
  { PPC::V15, 92U },
  { PPC::V16, 93U },
  { PPC::V17, 94U },
  { PPC::V18, 95U },
  { PPC::V19, 96U },
  { PPC::V20, 97U },
  { PPC::V21, 98U },
  { PPC::V22, 99U },
  { PPC::V23, 100U },
  { PPC::V24, 101U },
  { PPC::V25, 102U },
  { PPC::V26, 103U },
  { PPC::V27, 104U },
  { PPC::V28, 105U },
  { PPC::V29, 106U },
  { PPC::V30, 107U },
  { PPC::V31, 108U },
  { PPC::VF0, 77U },
  { PPC::VF1, 78U },
  { PPC::VF2, 79U },
  { PPC::VF3, 80U },
  { PPC::VF4, 81U },
  { PPC::VF5, 82U },
  { PPC::VF6, 83U },
  { PPC::VF7, 84U },
  { PPC::VF8, 85U },
  { PPC::VF9, 86U },
  { PPC::VF10, 87U },
  { PPC::VF11, 88U },
  { PPC::VF12, 89U },
  { PPC::VF13, 90U },
  { PPC::VF14, 91U },
  { PPC::VF15, 92U },
  { PPC::VF16, 93U },
  { PPC::VF17, 94U },
  { PPC::VF18, 95U },
  { PPC::VF19, 96U },
  { PPC::VF20, 97U },
  { PPC::VF21, 98U },
  { PPC::VF22, 99U },
  { PPC::VF23, 100U },
  { PPC::VF24, 101U },
  { PPC::VF25, 102U },
  { PPC::VF26, 103U },
  { PPC::VF27, 104U },
  { PPC::VF28, 105U },
  { PPC::VF29, 106U },
  { PPC::VF30, 107U },
  { PPC::VF31, 108U },
  { PPC::VSL0, 32U },
  { PPC::VSL1, 33U },
  { PPC::VSL2, 34U },
  { PPC::VSL3, 35U },
  { PPC::VSL4, 36U },
  { PPC::VSL5, 37U },
  { PPC::VSL6, 38U },
  { PPC::VSL7, 39U },
  { PPC::VSL8, 40U },
  { PPC::VSL9, 41U },
  { PPC::VSL10, 42U },
  { PPC::VSL11, 43U },
  { PPC::VSL12, 44U },
  { PPC::VSL13, 45U },
  { PPC::VSL14, 46U },
  { PPC::VSL15, 47U },
  { PPC::VSL16, 48U },
  { PPC::VSL17, 49U },
  { PPC::VSL18, 50U },
  { PPC::VSL19, 51U },
  { PPC::VSL20, 52U },
  { PPC::VSL21, 53U },
  { PPC::VSL22, 54U },
  { PPC::VSL23, 55U },
  { PPC::VSL24, 56U },
  { PPC::VSL25, 57U },
  { PPC::VSL26, 58U },
  { PPC::VSL27, 59U },
  { PPC::VSL28, 60U },
  { PPC::VSL29, 61U },
  { PPC::VSL30, 62U },
  { PPC::VSL31, 63U },
  { PPC::X0, -2U },
  { PPC::X1, -2U },
  { PPC::X2, -2U },
  { PPC::X3, -2U },
  { PPC::X4, -2U },
  { PPC::X5, -2U },
  { PPC::X6, -2U },
  { PPC::X7, -2U },
  { PPC::X8, -2U },
  { PPC::X9, -2U },
  { PPC::X10, -2U },
  { PPC::X11, -2U },
  { PPC::X12, -2U },
  { PPC::X13, -2U },
  { PPC::X14, -2U },
  { PPC::X15, -2U },
  { PPC::X16, -2U },
  { PPC::X17, -2U },
  { PPC::X18, -2U },
  { PPC::X19, -2U },
  { PPC::X20, -2U },
  { PPC::X21, -2U },
  { PPC::X22, -2U },
  { PPC::X23, -2U },
  { PPC::X24, -2U },
  { PPC::X25, -2U },
  { PPC::X26, -2U },
  { PPC::X27, -2U },
  { PPC::X28, -2U },
  { PPC::X29, -2U },
  { PPC::X30, -2U },
  { PPC::X31, -2U },
  { PPC::ZERO8, -2U },
};
extern const unsigned PPCDwarfFlavour1L2DwarfSize = std::size(PPCDwarfFlavour1L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[] = {
  { PPC::CARRY, 76U },
  { PPC::CTR, -2U },
  { PPC::LR, -2U },
  { PPC::SPEFSCR, 612U },
  { PPC::VRSAVE, 109U },
  { PPC::XER, 76U },
  { PPC::ZERO, -2U },
  { PPC::CR0, 68U },
  { PPC::CR1, 69U },
  { PPC::CR2, 70U },
  { PPC::CR3, 71U },
  { PPC::CR4, 72U },
  { PPC::CR5, 73U },
  { PPC::CR6, 74U },
  { PPC::CR7, 75U },
  { PPC::CTR8, 66U },
  { PPC::F0, 32U },
  { PPC::F1, 33U },
  { PPC::F2, 34U },
  { PPC::F3, 35U },
  { PPC::F4, 36U },
  { PPC::F5, 37U },
  { PPC::F6, 38U },
  { PPC::F7, 39U },
  { PPC::F8, 40U },
  { PPC::F9, 41U },
  { PPC::F10, 42U },
  { PPC::F11, 43U },
  { PPC::F12, 44U },
  { PPC::F13, 45U },
  { PPC::F14, 46U },
  { PPC::F15, 47U },
  { PPC::F16, 48U },
  { PPC::F17, 49U },
  { PPC::F18, 50U },
  { PPC::F19, 51U },
  { PPC::F20, 52U },
  { PPC::F21, 53U },
  { PPC::F22, 54U },
  { PPC::F23, 55U },
  { PPC::F24, 56U },
  { PPC::F25, 57U },
  { PPC::F26, 58U },
  { PPC::F27, 59U },
  { PPC::F28, 60U },
  { PPC::F29, 61U },
  { PPC::F30, 62U },
  { PPC::F31, 63U },
  { PPC::LR8, 65U },
  { PPC::R0, -2U },
  { PPC::R1, -2U },
  { PPC::R2, -2U },
  { PPC::R3, -2U },
  { PPC::R4, -2U },
  { PPC::R5, -2U },
  { PPC::R6, -2U },
  { PPC::R7, -2U },
  { PPC::R8, -2U },
  { PPC::R9, -2U },
  { PPC::R10, -2U },
  { PPC::R11, -2U },
  { PPC::R12, -2U },
  { PPC::R13, -2U },
  { PPC::R14, -2U },
  { PPC::R15, -2U },
  { PPC::R16, -2U },
  { PPC::R17, -2U },
  { PPC::R18, -2U },
  { PPC::R19, -2U },
  { PPC::R20, -2U },
  { PPC::R21, -2U },
  { PPC::R22, -2U },
  { PPC::R23, -2U },
  { PPC::R24, -2U },
  { PPC::R25, -2U },
  { PPC::R26, -2U },
  { PPC::R27, -2U },
  { PPC::R28, -2U },
  { PPC::R29, -2U },
  { PPC::R30, -2U },
  { PPC::R31, -2U },
  { PPC::S0, 1200U },
  { PPC::S1, 1201U },
  { PPC::S2, 1202U },
  { PPC::S3, 1203U },
  { PPC::S4, 1204U },
  { PPC::S5, 1205U },
  { PPC::S6, 1206U },
  { PPC::S7, 1207U },
  { PPC::S8, 1208U },
  { PPC::S9, 1209U },
  { PPC::S10, 1210U },
  { PPC::S11, 1211U },
  { PPC::S12, 1212U },
  { PPC::S13, 1213U },
  { PPC::S14, 1214U },
  { PPC::S15, 1215U },
  { PPC::S16, 1216U },
  { PPC::S17, 1217U },
  { PPC::S18, 1218U },
  { PPC::S19, 1219U },
  { PPC::S20, 1220U },
  { PPC::S21, 1221U },
  { PPC::S22, 1222U },
  { PPC::S23, 1223U },
  { PPC::S24, 1224U },
  { PPC::S25, 1225U },
  { PPC::S26, 1226U },
  { PPC::S27, 1227U },
  { PPC::S28, 1228U },
  { PPC::S29, 1229U },
  { PPC::S30, 1230U },
  { PPC::S31, 1231U },
  { PPC::V0, 77U },
  { PPC::V1, 78U },
  { PPC::V2, 79U },
  { PPC::V3, 80U },
  { PPC::V4, 81U },
  { PPC::V5, 82U },
  { PPC::V6, 83U },
  { PPC::V7, 84U },
  { PPC::V8, 85U },
  { PPC::V9, 86U },
  { PPC::V10, 87U },
  { PPC::V11, 88U },
  { PPC::V12, 89U },
  { PPC::V13, 90U },
  { PPC::V14, 91U },
  { PPC::V15, 92U },
  { PPC::V16, 93U },
  { PPC::V17, 94U },
  { PPC::V18, 95U },
  { PPC::V19, 96U },
  { PPC::V20, 97U },
  { PPC::V21, 98U },
  { PPC::V22, 99U },
  { PPC::V23, 100U },
  { PPC::V24, 101U },
  { PPC::V25, 102U },
  { PPC::V26, 103U },
  { PPC::V27, 104U },
  { PPC::V28, 105U },
  { PPC::V29, 106U },
  { PPC::V30, 107U },
  { PPC::V31, 108U },
  { PPC::VF0, 77U },
  { PPC::VF1, 78U },
  { PPC::VF2, 79U },
  { PPC::VF3, 80U },
  { PPC::VF4, 81U },
  { PPC::VF5, 82U },
  { PPC::VF6, 83U },
  { PPC::VF7, 84U },
  { PPC::VF8, 85U },
  { PPC::VF9, 86U },
  { PPC::VF10, 87U },
  { PPC::VF11, 88U },
  { PPC::VF12, 89U },
  { PPC::VF13, 90U },
  { PPC::VF14, 91U },
  { PPC::VF15, 92U },
  { PPC::VF16, 93U },
  { PPC::VF17, 94U },
  { PPC::VF18, 95U },
  { PPC::VF19, 96U },
  { PPC::VF20, 97U },
  { PPC::VF21, 98U },
  { PPC::VF22, 99U },
  { PPC::VF23, 100U },
  { PPC::VF24, 101U },
  { PPC::VF25, 102U },
  { PPC::VF26, 103U },
  { PPC::VF27, 104U },
  { PPC::VF28, 105U },
  { PPC::VF29, 106U },
  { PPC::VF30, 107U },
  { PPC::VF31, 108U },
  { PPC::VSL0, 32U },
  { PPC::VSL1, 33U },
  { PPC::VSL2, 34U },
  { PPC::VSL3, 35U },
  { PPC::VSL4, 36U },
  { PPC::VSL5, 37U },
  { PPC::VSL6, 38U },
  { PPC::VSL7, 39U },
  { PPC::VSL8, 40U },
  { PPC::VSL9, 41U },
  { PPC::VSL10, 42U },
  { PPC::VSL11, 43U },
  { PPC::VSL12, 44U },
  { PPC::VSL13, 45U },
  { PPC::VSL14, 46U },
  { PPC::VSL15, 47U },
  { PPC::VSL16, 48U },
  { PPC::VSL17, 49U },
  { PPC::VSL18, 50U },
  { PPC::VSL19, 51U },
  { PPC::VSL20, 52U },
  { PPC::VSL21, 53U },
  { PPC::VSL22, 54U },
  { PPC::VSL23, 55U },
  { PPC::VSL24, 56U },
  { PPC::VSL25, 57U },
  { PPC::VSL26, 58U },
  { PPC::VSL27, 59U },
  { PPC::VSL28, 60U },
  { PPC::VSL29, 61U },
  { PPC::VSL30, 62U },
  { PPC::VSL31, 63U },
  { PPC::X0, 0U },
  { PPC::X1, 1U },
  { PPC::X2, 2U },
  { PPC::X3, 3U },
  { PPC::X4, 4U },
  { PPC::X5, 5U },
  { PPC::X6, 6U },
  { PPC::X7, 7U },
  { PPC::X8, 8U },
  { PPC::X9, 9U },
  { PPC::X10, 10U },
  { PPC::X11, 11U },
  { PPC::X12, 12U },
  { PPC::X13, 13U },
  { PPC::X14, 14U },
  { PPC::X15, 15U },
  { PPC::X16, 16U },
  { PPC::X17, 17U },
  { PPC::X18, 18U },
  { PPC::X19, 19U },
  { PPC::X20, 20U },
  { PPC::X21, 21U },
  { PPC::X22, 22U },
  { PPC::X23, 23U },
  { PPC::X24, 24U },
  { PPC::X25, 25U },
  { PPC::X26, 26U },
  { PPC::X27, 27U },
  { PPC::X28, 28U },
  { PPC::X29, 29U },
  { PPC::X30, 30U },
  { PPC::X31, 31U },
  { PPC::ZERO8, 0U },
};
extern const unsigned PPCEHFlavour0L2DwarfSize = std::size(PPCEHFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[] = {
  { PPC::CTR, 66U },
  { PPC::LR, 65U },
  { PPC::SPEFSCR, 112U },
  { PPC::ZERO, 0U },
  { PPC::CR0, 68U },
  { PPC::CR1, 69U },
  { PPC::CR2, 70U },
  { PPC::CR3, 71U },
  { PPC::CR4, 72U },
  { PPC::CR5, 73U },
  { PPC::CR6, 74U },
  { PPC::CR7, 75U },
  { PPC::CTR8, -2U },
  { PPC::F0, 32U },
  { PPC::F1, 33U },
  { PPC::F2, 34U },
  { PPC::F3, 35U },
  { PPC::F4, 36U },
  { PPC::F5, 37U },
  { PPC::F6, 38U },
  { PPC::F7, 39U },
  { PPC::F8, 40U },
  { PPC::F9, 41U },
  { PPC::F10, 42U },
  { PPC::F11, 43U },
  { PPC::F12, 44U },
  { PPC::F13, 45U },
  { PPC::F14, 46U },
  { PPC::F15, 47U },
  { PPC::F16, 48U },
  { PPC::F17, 49U },
  { PPC::F18, 50U },
  { PPC::F19, 51U },
  { PPC::F20, 52U },
  { PPC::F21, 53U },
  { PPC::F22, 54U },
  { PPC::F23, 55U },
  { PPC::F24, 56U },
  { PPC::F25, 57U },
  { PPC::F26, 58U },
  { PPC::F27, 59U },
  { PPC::F28, 60U },
  { PPC::F29, 61U },
  { PPC::F30, 62U },
  { PPC::F31, 63U },
  { PPC::LR8, -2U },
  { PPC::R0, 0U },
  { PPC::R1, 1U },
  { PPC::R2, 2U },
  { PPC::R3, 3U },
  { PPC::R4, 4U },
  { PPC::R5, 5U },
  { PPC::R6, 6U },
  { PPC::R7, 7U },
  { PPC::R8, 8U },
  { PPC::R9, 9U },
  { PPC::R10, 10U },
  { PPC::R11, 11U },
  { PPC::R12, 12U },
  { PPC::R13, 13U },
  { PPC::R14, 14U },
  { PPC::R15, 15U },
  { PPC::R16, 16U },
  { PPC::R17, 17U },
  { PPC::R18, 18U },
  { PPC::R19, 19U },
  { PPC::R20, 20U },
  { PPC::R21, 21U },
  { PPC::R22, 22U },
  { PPC::R23, 23U },
  { PPC::R24, 24U },
  { PPC::R25, 25U },
  { PPC::R26, 26U },
  { PPC::R27, 27U },
  { PPC::R28, 28U },
  { PPC::R29, 29U },
  { PPC::R30, 30U },
  { PPC::R31, 31U },
  { PPC::S0, 1200U },
  { PPC::S1, 1201U },
  { PPC::S2, 1202U },
  { PPC::S3, 1203U },
  { PPC::S4, 1204U },
  { PPC::S5, 1205U },
  { PPC::S6, 1206U },
  { PPC::S7, 1207U },
  { PPC::S8, 1208U },
  { PPC::S9, 1209U },
  { PPC::S10, 1210U },
  { PPC::S11, 1211U },
  { PPC::S12, 1212U },
  { PPC::S13, 1213U },
  { PPC::S14, 1214U },
  { PPC::S15, 1215U },
  { PPC::S16, 1216U },
  { PPC::S17, 1217U },
  { PPC::S18, 1218U },
  { PPC::S19, 1219U },
  { PPC::S20, 1220U },
  { PPC::S21, 1221U },
  { PPC::S22, 1222U },
  { PPC::S23, 1223U },
  { PPC::S24, 1224U },
  { PPC::S25, 1225U },
  { PPC::S26, 1226U },
  { PPC::S27, 1227U },
  { PPC::S28, 1228U },
  { PPC::S29, 1229U },
  { PPC::S30, 1230U },
  { PPC::S31, 1231U },
  { PPC::V0, 77U },
  { PPC::V1, 78U },
  { PPC::V2, 79U },
  { PPC::V3, 80U },
  { PPC::V4, 81U },
  { PPC::V5, 82U },
  { PPC::V6, 83U },
  { PPC::V7, 84U },
  { PPC::V8, 85U },
  { PPC::V9, 86U },
  { PPC::V10, 87U },
  { PPC::V11, 88U },
  { PPC::V12, 89U },
  { PPC::V13, 90U },
  { PPC::V14, 91U },
  { PPC::V15, 92U },
  { PPC::V16, 93U },
  { PPC::V17, 94U },
  { PPC::V18, 95U },
  { PPC::V19, 96U },
  { PPC::V20, 97U },
  { PPC::V21, 98U },
  { PPC::V22, 99U },
  { PPC::V23, 100U },
  { PPC::V24, 101U },
  { PPC::V25, 102U },
  { PPC::V26, 103U },
  { PPC::V27, 104U },
  { PPC::V28, 105U },
  { PPC::V29, 106U },
  { PPC::V30, 107U },
  { PPC::V31, 108U },
  { PPC::VF0, 77U },
  { PPC::VF1, 78U },
  { PPC::VF2, 79U },
  { PPC::VF3, 80U },
  { PPC::VF4, 81U },
  { PPC::VF5, 82U },
  { PPC::VF6, 83U },
  { PPC::VF7, 84U },
  { PPC::VF8, 85U },
  { PPC::VF9, 86U },
  { PPC::VF10, 87U },
  { PPC::VF11, 88U },
  { PPC::VF12, 89U },
  { PPC::VF13, 90U },
  { PPC::VF14, 91U },
  { PPC::VF15, 92U },
  { PPC::VF16, 93U },
  { PPC::VF17, 94U },
  { PPC::VF18, 95U },
  { PPC::VF19, 96U },
  { PPC::VF20, 97U },
  { PPC::VF21, 98U },
  { PPC::VF22, 99U },
  { PPC::VF23, 100U },
  { PPC::VF24, 101U },
  { PPC::VF25, 102U },
  { PPC::VF26, 103U },
  { PPC::VF27, 104U },
  { PPC::VF28, 105U },
  { PPC::VF29, 106U },
  { PPC::VF30, 107U },
  { PPC::VF31, 108U },
  { PPC::VSL0, 32U },
  { PPC::VSL1, 33U },
  { PPC::VSL2, 34U },
  { PPC::VSL3, 35U },
  { PPC::VSL4, 36U },
  { PPC::VSL5, 37U },
  { PPC::VSL6, 38U },
  { PPC::VSL7, 39U },
  { PPC::VSL8, 40U },
  { PPC::VSL9, 41U },
  { PPC::VSL10, 42U },
  { PPC::VSL11, 43U },
  { PPC::VSL12, 44U },
  { PPC::VSL13, 45U },
  { PPC::VSL14, 46U },
  { PPC::VSL15, 47U },
  { PPC::VSL16, 48U },
  { PPC::VSL17, 49U },
  { PPC::VSL18, 50U },
  { PPC::VSL19, 51U },
  { PPC::VSL20, 52U },
  { PPC::VSL21, 53U },
  { PPC::VSL22, 54U },
  { PPC::VSL23, 55U },
  { PPC::VSL24, 56U },
  { PPC::VSL25, 57U },
  { PPC::VSL26, 58U },
  { PPC::VSL27, 59U },
  { PPC::VSL28, 60U },
  { PPC::VSL29, 61U },
  { PPC::VSL30, 62U },
  { PPC::VSL31, 63U },
  { PPC::X0, -2U },
  { PPC::X1, -2U },
  { PPC::X2, -2U },
  { PPC::X3, -2U },
  { PPC::X4, -2U },
  { PPC::X5, -2U },
  { PPC::X6, -2U },
  { PPC::X7, -2U },
  { PPC::X8, -2U },
  { PPC::X9, -2U },
  { PPC::X10, -2U },
  { PPC::X11, -2U },
  { PPC::X12, -2U },
  { PPC::X13, -2U },
  { PPC::X14, -2U },
  { PPC::X15, -2U },
  { PPC::X16, -2U },
  { PPC::X17, -2U },
  { PPC::X18, -2U },
  { PPC::X19, -2U },
  { PPC::X20, -2U },
  { PPC::X21, -2U },
  { PPC::X22, -2U },
  { PPC::X23, -2U },
  { PPC::X24, -2U },
  { PPC::X25, -2U },
  { PPC::X26, -2U },
  { PPC::X27, -2U },
  { PPC::X28, -2U },
  { PPC::X29, -2U },
  { PPC::X30, -2U },
  { PPC::X31, -2U },
  { PPC::ZERO8, -2U },
};
extern const unsigned PPCEHFlavour1L2DwarfSize = std::size(PPCEHFlavour1L2Dwarf);

extern const uint16_t PPCRegEncodingTable[] = {
  0,
  0,
  1,
  9,
  0,
  8,
  0,
  512,
  256,
  1,
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  9,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  32,
  33,
  34,
  35,
  36,
  37,
  38,
  39,
  40,
  41,
  42,
  43,
  44,
  45,
  46,
  47,
  48,
  49,
  50,
  51,
  52,
  53,
  54,
  55,
  56,
  57,
  58,
  59,
  60,
  61,
  62,
  63,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  31,
  8,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  32,
  33,
  34,
  35,
  36,
  37,
  38,
  39,
  40,
  41,
  42,
  43,
  44,
  45,
  46,
  47,
  48,
  49,
  50,
  51,
  52,
  53,
  54,
  55,
  56,
  57,
  58,
  59,
  60,
  61,
  62,
  63,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  32,
  33,
  34,
  35,
  36,
  37,
  38,
  39,
  40,
  41,
  42,
  43,
  44,
  45,
  46,
  47,
  48,
  49,
  50,
  51,
  52,
  53,
  54,
  55,
  56,
  57,
  58,
  59,
  60,
  61,
  62,
  63,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  2,
  6,
  10,
  14,
  18,
  22,
  26,
  30,
  1,
  5,
  9,
  13,
  17,
  21,
  25,
  29,
  0,
  4,
  8,
  12,
  16,
  20,
  24,
  28,
  3,
  7,
  11,
  15,
  19,
  23,
  27,
  31,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
};
static inline void InitPPCMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(PPCRegDesc, 548, RA, PC, PPCMCRegisterClasses, 54, PPCRegUnitRoots, 265, PPCRegDiffLists, PPCLaneMaskLists, PPCRegStrings, PPCRegClassStrings, PPCSubRegIdxLists, 52,
PPCSubRegIdxRanges, PPCRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
    break;
  case 1:
    RI->mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
    break;
  case 1:
    RI->mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
    break;
  case 1:
    RI->mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
    break;
  case 1:
    RI->mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class PPCFrameLowering;

struct PPCGenRegisterInfo : public TargetRegisterInfo {
  explicit PPCGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const PPCFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace PPC { // Register classes
  extern const TargetRegisterClass VSSRCRegClass;
  extern const TargetRegisterClass GPRCRegClass;
  extern const TargetRegisterClass GPRC_NOR0RegClass;
  extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass;
  extern const TargetRegisterClass CRBITRCRegClass;
  extern const TargetRegisterClass F4RCRegClass;
  extern const TargetRegisterClass GPRC32RegClass;
  extern const TargetRegisterClass CRRCRegClass;
  extern const TargetRegisterClass CARRYRCRegClass;
  extern const TargetRegisterClass CTRRCRegClass;
  extern const TargetRegisterClass LRRCRegClass;
  extern const TargetRegisterClass VRSAVERCRegClass;
  extern const TargetRegisterClass SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass VSFRCRegClass;
  extern const TargetRegisterClass G8RCRegClass;
  extern const TargetRegisterClass G8RC_NOX0RegClass;
  extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass;
  extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass;
  extern const TargetRegisterClass F8RCRegClass;
  extern const TargetRegisterClass SPERCRegClass;
  extern const TargetRegisterClass VFRCRegClass;
  extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass;
  extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass;
  extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass;
  extern const TargetRegisterClass CTRRC8RegClass;
  extern const TargetRegisterClass LR8RCRegClass;
  extern const TargetRegisterClass DMRROWRCRegClass;
  extern const TargetRegisterClass VSRCRegClass;
  extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass VRRCRegClass;
  extern const TargetRegisterClass VSLRCRegClass;
  extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass FpRCRegClass;
  extern const TargetRegisterClass G8pRCRegClass;
  extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass;
  extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass DMRROWpRCRegClass;
  extern const TargetRegisterClass VSRpRCRegClass;
  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass;
  extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass;
  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass;
  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass;
  extern const TargetRegisterClass ACCRCRegClass;
  extern const TargetRegisterClass UACCRCRegClass;
  extern const TargetRegisterClass WACCRCRegClass;
  extern const TargetRegisterClass WACC_HIRCRegClass;
  extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass;
  extern const TargetRegisterClass DMRRCRegClass;
  extern const TargetRegisterClass DMRpRCRegClass;
} // end namespace PPC

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass PPCMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i1, MVT::Other,
  /* 2 */ MVT::i32, MVT::Other,
  /* 4 */ MVT::i64, MVT::Other,
  /* 6 */ MVT::i128, MVT::Other,
  /* 8 */ MVT::i32, MVT::f32, MVT::Other,
  /* 11 */ MVT::i64, MVT::f64, MVT::Other,
  /* 14 */ MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64, MVT::v1i128, MVT::v4f32, MVT::v2f64, MVT::f128, MVT::Other,
  /* 23 */ MVT::ppcf128, MVT::Other,
  /* 25 */ MVT::v128i1, MVT::Other,
  /* 27 */ MVT::v256i1, MVT::Other,
  /* 29 */ MVT::v512i1, MVT::Other,
  /* 31 */ MVT::v1024i1, MVT::Other,
  /* 33 */ MVT::v2048i1, MVT::Other,
  /* 35 */ MVT::v4i32, MVT::v4f32, MVT::v2f64, MVT::v2i64, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_32", "sub_32_hi_phony", "sub_64", "sub_dmr0", "sub_dmr1", "sub_dmrrow0", "sub_dmrrow1", "sub_dmrrowp0", "sub_dmrrowp1", "sub_eq", "sub_fp0", "sub_fp1", "sub_gp8_x0", "sub_gp8_x1", "sub_gt", "sub_lt", "sub_pair0", "sub_pair1", "sub_un", "sub_vsx0", "sub_vsx1", "sub_wacc_hi", "sub_wacc_lo", "sub_vsx1_then_sub_64", "sub_pair1_then_sub_64", "sub_pair1_then_sub_vsx0", "sub_pair1_then_sub_vsx1", "sub_pair1_then_sub_vsx1_then_sub_64", "sub_dmrrowp1_then_sub_dmrrow0", "sub_dmrrowp1_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrow1", "sub_wacc_hi_then_sub_dmrrowp0", "sub_wacc_hi_then_sub_dmrrowp1", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrow1", "sub_dmr1_then_sub_dmrrowp0", "sub_dmr1_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi", "sub_dmr1_then_sub_wacc_lo", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0", "sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1", "sub_gp8_x1_then_sub_32", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_32
  LaneBitmask(0x0000000000000002), // sub_32_hi_phony
  LaneBitmask(0x0000000000000004), // sub_64
  LaneBitmask(0x00000000000FC018), // sub_dmr0
  LaneBitmask(0x000000000FF00000), // sub_dmr1
  LaneBitmask(0x0000000000000008), // sub_dmrrow0
  LaneBitmask(0x0000000000000010), // sub_dmrrow1
  LaneBitmask(0x0000000000000018), // sub_dmrrowp0
  LaneBitmask(0x000000000000C000), // sub_dmrrowp1
  LaneBitmask(0x0000000000000020), // sub_eq
  LaneBitmask(0x0000000000000040), // sub_fp0
  LaneBitmask(0x0000000000000080), // sub_fp1
  LaneBitmask(0x0000000000000001), // sub_gp8_x0
  LaneBitmask(0x0000000010000000), // sub_gp8_x1
  LaneBitmask(0x0000000000000100), // sub_gt
  LaneBitmask(0x0000000000000200), // sub_lt
  LaneBitmask(0x0000000000000804), // sub_pair0
  LaneBitmask(0x0000000000003000), // sub_pair1
  LaneBitmask(0x0000000000000400), // sub_un
  LaneBitmask(0x0000000000000004), // sub_vsx0
  LaneBitmask(0x0000000000000800), // sub_vsx1
  LaneBitmask(0x00000000000F0000), // sub_wacc_hi
  LaneBitmask(0x000000000000C018), // sub_wacc_lo
  LaneBitmask(0x0000000000000800), // sub_vsx1_then_sub_64
  LaneBitmask(0x0000000000001000), // sub_pair1_then_sub_64
  LaneBitmask(0x0000000000001000), // sub_pair1_then_sub_vsx0
  LaneBitmask(0x0000000000002000), // sub_pair1_then_sub_vsx1
  LaneBitmask(0x0000000000002000), // sub_pair1_then_sub_vsx1_then_sub_64
  LaneBitmask(0x0000000000004000), // sub_dmrrowp1_then_sub_dmrrow0
  LaneBitmask(0x0000000000008000), // sub_dmrrowp1_then_sub_dmrrow1
  LaneBitmask(0x0000000000010000), // sub_wacc_hi_then_sub_dmrrow0
  LaneBitmask(0x0000000000020000), // sub_wacc_hi_then_sub_dmrrow1
  LaneBitmask(0x0000000000030000), // sub_wacc_hi_then_sub_dmrrowp0
  LaneBitmask(0x00000000000C0000), // sub_wacc_hi_then_sub_dmrrowp1
  LaneBitmask(0x0000000000040000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
  LaneBitmask(0x0000000000080000), // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
  LaneBitmask(0x0000000000100000), // sub_dmr1_then_sub_dmrrow0
  LaneBitmask(0x0000000000200000), // sub_dmr1_then_sub_dmrrow1
  LaneBitmask(0x0000000000300000), // sub_dmr1_then_sub_dmrrowp0
  LaneBitmask(0x0000000000C00000), // sub_dmr1_then_sub_dmrrowp1
  LaneBitmask(0x000000000F000000), // sub_dmr1_then_sub_wacc_hi
  LaneBitmask(0x0000000000F00000), // sub_dmr1_then_sub_wacc_lo
  LaneBitmask(0x0000000000400000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
  LaneBitmask(0x0000000000800000), // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
  LaneBitmask(0x0000000001000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
  LaneBitmask(0x0000000002000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
  LaneBitmask(0x0000000003000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
  LaneBitmask(0x000000000C000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
  LaneBitmask(0x0000000004000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
  LaneBitmask(0x0000000008000000), // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
  LaneBitmask(0x0000000010000000), // sub_gp8_x1_then_sub_32
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 32, 32, 32, /*VTLists+*/9 },    // VSSRC
  { 32, 32, 32, /*VTLists+*/8 },    // GPRC
  { 32, 32, 32, /*VTLists+*/8 },    // GPRC_NOR0
  { 32, 32, 32, /*VTLists+*/8 },    // GPRC_and_GPRC_NOR0
  { 32, 32, 32, /*VTLists+*/0 },    // CRBITRC
  { 32, 32, 32, /*VTLists+*/9 },    // F4RC
  { 32, 32, 32, /*VTLists+*/8 },    // GPRC32
  { 32, 32, 32, /*VTLists+*/2 },    // CRRC
  { 32, 32, 32, /*VTLists+*/2 },    // CARRYRC
  { 32, 32, 32, /*VTLists+*/2 },    // CTRRC
  { 32, 32, 32, /*VTLists+*/2 },    // LRRC
  { 32, 32, 32, /*VTLists+*/2 },    // VRSAVERC
  { 64, 64, 64, /*VTLists+*/11 },    // SPILLTOVSRRC
  { 64, 64, 64, /*VTLists+*/12 },    // VSFRC
  { 64, 64, 64, /*VTLists+*/4 },    // G8RC
  { 64, 64, 64, /*VTLists+*/4 },    // G8RC_NOX0
  { 64, 64, 64, /*VTLists+*/12 },    // SPILLTOVSRRC_and_VSFRC
  { 64, 64, 64, /*VTLists+*/4 },    // G8RC_and_G8RC_NOX0
  { 64, 64, 64, /*VTLists+*/12 },    // F8RC
  { 64, 64, 64, /*VTLists+*/12 },    // SPERC
  { 64, 64, 64, /*VTLists+*/12 },    // VFRC
  { 64, 64, 64, /*VTLists+*/12 },    // SPERC_with_sub_32_in_GPRC_NOR0
  { 64, 64, 64, /*VTLists+*/12 },    // SPILLTOVSRRC_and_VFRC
  { 64, 64, 64, /*VTLists+*/12 },    // SPILLTOVSRRC_and_F4RC
  { 64, 64, 64, /*VTLists+*/4 },    // CTRRC8
  { 64, 64, 64, /*VTLists+*/4 },    // LR8RC
  { 128, 128, 128, /*VTLists+*/25 },    // DMRROWRC
  { 128, 128, 128, /*VTLists+*/35 },    // VSRC
  { 128, 128, 128, /*VTLists+*/35 },    // VSRC_with_sub_64_in_SPILLTOVSRRC
  { 128, 128, 128, /*VTLists+*/14 },    // VRRC
  { 128, 128, 128, /*VTLists+*/35 },    // VSLRC
  { 128, 128, 128, /*VTLists+*/14 },    // VRRC_with_sub_64_in_SPILLTOVSRRC
  { 128, 128, 128, /*VTLists+*/23 },    // FpRC
  { 128, 128, 128, /*VTLists+*/6 },    // G8pRC
  { 128, 128, 128, /*VTLists+*/6 },    // G8pRC_with_sub_32_in_GPRC_NOR0
  { 128, 128, 128, /*VTLists+*/35 },    // VSLRC_with_sub_64_in_SPILLTOVSRRC
  { 128, 128, 128, /*VTLists+*/23 },    // FpRC_with_sub_fp0_in_SPILLTOVSRRC
  { 256, 256, 128, /*VTLists+*/27 },    // DMRROWpRC
  { 256, 256, 128, /*VTLists+*/27 },    // VSRpRC
  { 256, 256, 128, /*VTLists+*/27 },    // VSRpRC_with_sub_64_in_SPILLTOVSRRC
  { 256, 256, 128, /*VTLists+*/27 },    // VSRpRC_with_sub_64_in_F4RC
  { 256, 256, 128, /*VTLists+*/27 },    // VSRpRC_with_sub_64_in_VFRC
  { 256, 256, 128, /*VTLists+*/27 },    // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
  { 256, 256, 128, /*VTLists+*/27 },    // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
  { 512, 512, 128, /*VTLists+*/29 },    // ACCRC
  { 512, 512, 128, /*VTLists+*/29 },    // UACCRC
  { 512, 512, 128, /*VTLists+*/29 },    // WACCRC
  { 512, 512, 128, /*VTLists+*/29 },    // WACC_HIRC
  { 512, 512, 128, /*VTLists+*/29 },    // ACCRC_with_sub_64_in_SPILLTOVSRRC
  { 512, 512, 128, /*VTLists+*/29 },    // UACCRC_with_sub_64_in_SPILLTOVSRRC
  { 512, 512, 128, /*VTLists+*/29 },    // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
  { 512, 512, 128, /*VTLists+*/29 },    // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
  { 1024, 1024, 128, /*VTLists+*/31 },    // DMRRC
  { 2048, 2048, 128, /*VTLists+*/33 },    // DMRpRC
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t VSSRCSubClassMask[] = {
  0x00d52021, 0x00000000, 
  0xf8000000, 0x000f3fc8, // sub_64
  0x00000000, 0x00000011, // sub_fp0
  0x00000000, 0x00000011, // sub_fp1
  0x00000000, 0x000f3fc0, // sub_vsx1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t GPRCSubClassMask[] = {
  0x0000000a, 0x00000000, 
  0x002a4000, 0x00000006, // sub_32
  0x00000000, 0x00000006, // sub_gp8_x1_then_sub_32
};

static const uint32_t GPRC_NOR0SubClassMask[] = {
  0x0000000c, 0x00000000, 
  0x00228000, 0x00000004, // sub_32
  0x00000000, 0x00000006, // sub_gp8_x1_then_sub_32
};

static const uint32_t GPRC_and_GPRC_NOR0SubClassMask[] = {
  0x00000008, 0x00000000, 
  0x00220000, 0x00000004, // sub_32
  0x00000000, 0x00000006, // sub_gp8_x1_then_sub_32
};

static const uint32_t CRBITRCSubClassMask[] = {
  0x00000010, 0x00000000, 
  0x00000080, 0x00000000, // sub_eq
  0x00000080, 0x00000000, // sub_gt
  0x00000080, 0x00000000, // sub_lt
  0x00000080, 0x00000000, // sub_un
};

static const uint32_t F4RCSubClassMask[] = {
  0x00840020, 0x00000000, 
  0x40000000, 0x000f3908, // sub_64
  0x00000000, 0x00000011, // sub_fp0
  0x00000000, 0x00000011, // sub_fp1
  0x00000000, 0x000f3900, // sub_vsx1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t GPRC32SubClassMask[] = {
  0x00000040, 0x00000000, 
};

static const uint32_t CRRCSubClassMask[] = {
  0x00000080, 0x00000000, 
};

static const uint32_t CARRYRCSubClassMask[] = {
  0x00000100, 0x00000000, 
};

static const uint32_t CTRRCSubClassMask[] = {
  0x00000200, 0x00000000, 
};

static const uint32_t LRRCSubClassMask[] = {
  0x00000400, 0x00000000, 
};

static const uint32_t VRSAVERCSubClassMask[] = {
  0x00000800, 0x00000000, 
};

static const uint32_t SPILLTOVSRRCSubClassMask[] = {
  0x00c35000, 0x00000000, 
  0x90000000, 0x000f0c88, // sub_64
  0x00000000, 0x00000010, // sub_fp0
  0x00000000, 0x00000010, // sub_fp1
  0x00000000, 0x00000006, // sub_gp8_x0
  0x00000000, 0x00000006, // sub_gp8_x1
  0x00000000, 0x000f0c80, // sub_vsx1_then_sub_64
  0x00000000, 0x000c0000, // sub_pair1_then_sub_64
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t VSFRCSubClassMask[] = {
  0x00d52000, 0x00000000, 
  0xf8000000, 0x000f3fc8, // sub_64
  0x00000000, 0x00000011, // sub_fp0
  0x00000000, 0x00000011, // sub_fp1
  0x00000000, 0x000f3fc0, // sub_vsx1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t G8RCSubClassMask[] = {
  0x00024000, 0x00000000, 
  0x00000000, 0x00000006, // sub_gp8_x0
  0x00000000, 0x00000006, // sub_gp8_x1
};

static const uint32_t G8RC_NOX0SubClassMask[] = {
  0x00028000, 0x00000000, 
  0x00000000, 0x00000004, // sub_gp8_x0
  0x00000000, 0x00000006, // sub_gp8_x1
};

static const uint32_t SPILLTOVSRRC_and_VSFRCSubClassMask[] = {
  0x00c10000, 0x00000000, 
  0x90000000, 0x000f0c88, // sub_64
  0x00000000, 0x00000010, // sub_fp0
  0x00000000, 0x00000010, // sub_fp1
  0x00000000, 0x000f0c80, // sub_vsx1_then_sub_64
  0x00000000, 0x000c0000, // sub_pair1_then_sub_64
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t G8RC_and_G8RC_NOX0SubClassMask[] = {
  0x00020000, 0x00000000, 
  0x00000000, 0x00000004, // sub_gp8_x0
  0x00000000, 0x00000006, // sub_gp8_x1
};

static const uint32_t F8RCSubClassMask[] = {
  0x00840000, 0x00000000, 
  0x40000000, 0x000f3908, // sub_64
  0x00000000, 0x00000011, // sub_fp0
  0x00000000, 0x00000011, // sub_fp1
  0x00000000, 0x000f3900, // sub_vsx1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_64
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t SPERCSubClassMask[] = {
  0x00280000, 0x00000000, 
};

static const uint32_t VFRCSubClassMask[] = {
  0x00500000, 0x00000000, 
  0xa0000000, 0x00000600, // sub_64
  0x00000000, 0x00000600, // sub_vsx1_then_sub_64
};

static const uint32_t SPERC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
  0x00200000, 0x00000000, 
};

static const uint32_t SPILLTOVSRRC_and_VFRCSubClassMask[] = {
  0x00400000, 0x00000000, 
  0x80000000, 0x00000400, // sub_64
  0x00000000, 0x00000400, // sub_vsx1_then_sub_64
};

static const uint32_t SPILLTOVSRRC_and_F4RCSubClassMask[] = {
  0x00800000, 0x00000000, 
  0x00000000, 0x000f0808, // sub_64
  0x00000000, 0x00000010, // sub_fp0
  0x00000000, 0x00000010, // sub_fp1
  0x00000000, 0x000f0800, // sub_vsx1_then_sub_64
  0x00000000, 0x000c0000, // sub_pair1_then_sub_64
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx1_then_sub_64
};

static const uint32_t CTRRC8SubClassMask[] = {
  0x01000000, 0x00000000, 
};

static const uint32_t LR8RCSubClassMask[] = {
  0x02000000, 0x00000000, 
};

static const uint32_t DMRROWRCSubClassMask[] = {
  0x04000000, 0x00000000, 
  0x00000000, 0x0030c020, // sub_dmrrow0
  0x00000000, 0x0030c020, // sub_dmrrow1
  0x00000000, 0x0030c000, // sub_dmrrowp1_then_sub_dmrrow0
  0x00000000, 0x0030c000, // sub_dmrrowp1_then_sub_dmrrow1
  0x00000000, 0x00300000, // sub_wacc_hi_then_sub_dmrrow0
  0x00000000, 0x00300000, // sub_wacc_hi_then_sub_dmrrow1
  0x00000000, 0x00300000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
  0x00000000, 0x00300000, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
  0x00000000, 0x00200000, // sub_dmr1_then_sub_dmrrow0
  0x00000000, 0x00200000, // sub_dmr1_then_sub_dmrrow1
  0x00000000, 0x00200000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
  0x00000000, 0x00200000, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
};

static const uint32_t VSRCSubClassMask[] = {
  0xf8000000, 0x00000008, 
  0x00000000, 0x000f3fc0, // sub_vsx0
  0x00000000, 0x000f3fc0, // sub_vsx1
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx0
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx1
};

static const uint32_t VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x90000000, 0x00000008, 
  0x00000000, 0x000f0c80, // sub_vsx0
  0x00000000, 0x000f0c80, // sub_vsx1
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx0
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx1
};

static const uint32_t VRRCSubClassMask[] = {
  0xa0000000, 0x00000000, 
  0x00000000, 0x00000600, // sub_vsx0
  0x00000000, 0x00000600, // sub_vsx1
};

static const uint32_t VSLRCSubClassMask[] = {
  0x40000000, 0x00000008, 
  0x00000000, 0x000f3900, // sub_vsx0
  0x00000000, 0x000f3900, // sub_vsx1
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx0
  0x00000000, 0x000f3000, // sub_pair1_then_sub_vsx1
};

static const uint32_t VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x80000000, 0x00000000, 
  0x00000000, 0x00000400, // sub_vsx0
  0x00000000, 0x00000400, // sub_vsx1
};

static const uint32_t FpRCSubClassMask[] = {
  0x00000000, 0x00000011, 
};

static const uint32_t G8pRCSubClassMask[] = {
  0x00000000, 0x00000006, 
};

static const uint32_t G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask[] = {
  0x00000000, 0x00000004, 
};

static const uint32_t VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x00000008, 
  0x00000000, 0x000f0800, // sub_vsx0
  0x00000000, 0x000f0800, // sub_vsx1
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx0
  0x00000000, 0x000c0000, // sub_pair1_then_sub_vsx1
};

static const uint32_t FpRC_with_sub_fp0_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x00000010, 
};

static const uint32_t DMRROWpRCSubClassMask[] = {
  0x00000000, 0x00000020, 
  0x00000000, 0x0030c000, // sub_dmrrowp0
  0x00000000, 0x0030c000, // sub_dmrrowp1
  0x00000000, 0x00300000, // sub_wacc_hi_then_sub_dmrrowp0
  0x00000000, 0x00300000, // sub_wacc_hi_then_sub_dmrrowp1
  0x00000000, 0x00200000, // sub_dmr1_then_sub_dmrrowp0
  0x00000000, 0x00200000, // sub_dmr1_then_sub_dmrrowp1
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
};

static const uint32_t VSRpRCSubClassMask[] = {
  0x00000000, 0x00000fc0, 
  0x00000000, 0x000f3000, // sub_pair0
  0x00000000, 0x000f3000, // sub_pair1
};

static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x00000c80, 
  0x00000000, 0x000f0000, // sub_pair0
  0x00000000, 0x000c0000, // sub_pair1
};

static const uint32_t VSRpRC_with_sub_64_in_F4RCSubClassMask[] = {
  0x00000000, 0x00000900, 
  0x00000000, 0x000f3000, // sub_pair0
  0x00000000, 0x000f3000, // sub_pair1
};

static const uint32_t VSRpRC_with_sub_64_in_VFRCSubClassMask[] = {
  0x00000000, 0x00000600, 
};

static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask[] = {
  0x00000000, 0x00000400, 
};

static const uint32_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask[] = {
  0x00000000, 0x00000800, 
  0x00000000, 0x000f0000, // sub_pair0
  0x00000000, 0x000c0000, // sub_pair1
};

static const uint32_t ACCRCSubClassMask[] = {
  0x00000000, 0x00051000, 
};

static const uint32_t UACCRCSubClassMask[] = {
  0x00000000, 0x000a2000, 
};

static const uint32_t WACCRCSubClassMask[] = {
  0x00000000, 0x00004000, 
  0x00000000, 0x00300000, // sub_wacc_lo
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_lo
};

static const uint32_t WACC_HIRCSubClassMask[] = {
  0x00000000, 0x00008000, 
  0x00000000, 0x00300000, // sub_wacc_hi
  0x00000000, 0x00200000, // sub_dmr1_then_sub_wacc_hi
};

static const uint32_t ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x00050000, 
};

static const uint32_t UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x000a0000, 
};

static const uint32_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x00040000, 
};

static const uint32_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask[] = {
  0x00000000, 0x00080000, 
};

static const uint32_t DMRRCSubClassMask[] = {
  0x00000000, 0x00100000, 
  0x00000000, 0x00200000, // sub_dmr0
  0x00000000, 0x00200000, // sub_dmr1
};

static const uint32_t DMRpRCSubClassMask[] = {
  0x00000000, 0x00200000, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 4, 5, 0,
  /* 3 */ 13, 14, 0,
  /* 6 */ 17, 18, 0,
  /* 9 */ 10, 15, 16, 19, 0,
  /* 14 */ 20, 21, 0,
  /* 17 */ 3, 24, 0,
  /* 20 */ 20, 21, 26, 27, 0,
  /* 25 */ 3, 11, 12, 24, 25, 28, 0,
  /* 32 */ 3, 11, 12, 13, 14, 24, 25, 28, 0,
  /* 41 */ 22, 41, 0,
  /* 44 */ 23, 42, 0,
  /* 47 */ 8, 9, 33, 34, 39, 40, 47, 48, 0,
  /* 56 */ 6, 7, 29, 30, 31, 32, 35, 36, 37, 38, 43, 44, 45, 46, 49, 50, 0,
  /* 73 */ 1, 51, 0,
};

static const TargetRegisterClass *const GPRC_and_GPRC_NOR0Superclasses[] = {
  &PPC::GPRCRegClass,
  &PPC::GPRC_NOR0RegClass,
  nullptr
};

static const TargetRegisterClass *const F4RCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSFRCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  nullptr
};

static const TargetRegisterClass *const G8RCSuperclasses[] = {
  &PPC::SPILLTOVSRRCRegClass,
  nullptr
};

static const TargetRegisterClass *const SPILLTOVSRRC_and_VSFRCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  &PPC::SPILLTOVSRRCRegClass,
  &PPC::VSFRCRegClass,
  nullptr
};

static const TargetRegisterClass *const G8RC_and_G8RC_NOX0Superclasses[] = {
  &PPC::SPILLTOVSRRCRegClass,
  &PPC::G8RCRegClass,
  &PPC::G8RC_NOX0RegClass,
  nullptr
};

static const TargetRegisterClass *const F8RCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  &PPC::F4RCRegClass,
  &PPC::VSFRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VFRCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  &PPC::VSFRCRegClass,
  nullptr
};

static const TargetRegisterClass *const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
  &PPC::SPERCRegClass,
  nullptr
};

static const TargetRegisterClass *const SPILLTOVSRRC_and_VFRCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  &PPC::SPILLTOVSRRCRegClass,
  &PPC::VSFRCRegClass,
  &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
  &PPC::VFRCRegClass,
  nullptr
};

static const TargetRegisterClass *const SPILLTOVSRRC_and_F4RCSuperclasses[] = {
  &PPC::VSSRCRegClass,
  &PPC::F4RCRegClass,
  &PPC::SPILLTOVSRRCRegClass,
  &PPC::VSFRCRegClass,
  &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
  &PPC::F8RCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::VSRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VRRCSuperclasses[] = {
  &PPC::VSRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSLRCSuperclasses[] = {
  &PPC::VSRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::VSRCRegClass,
  &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
  &PPC::VRRCRegClass,
  nullptr
};

static const TargetRegisterClass *const G8pRC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
  &PPC::G8pRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::VSRCRegClass,
  &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
  &PPC::VSLRCRegClass,
  nullptr
};

static const TargetRegisterClass *const FpRC_with_sub_fp0_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::FpRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::VSRpRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSRpRC_with_sub_64_in_F4RCSuperclasses[] = {
  &PPC::VSRpRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSRpRC_with_sub_64_in_VFRCSuperclasses[] = {
  &PPC::VSRpRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses[] = {
  &PPC::VSRpRCRegClass,
  &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
  &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
  nullptr
};

static const TargetRegisterClass *const VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses[] = {
  &PPC::VSRpRCRegClass,
  &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
  &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
  nullptr
};

static const TargetRegisterClass *const ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::ACCRCRegClass,
  nullptr
};

static const TargetRegisterClass *const UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::UACCRCRegClass,
  nullptr
};

static const TargetRegisterClass *const ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::ACCRCRegClass,
  &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
  nullptr
};

static const TargetRegisterClass *const UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
  &PPC::UACCRCRegClass,
  &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
  nullptr
};


static inline unsigned GPRCAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> GPRCGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R0, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R0, PPC::R1, PPC::FP, PPC::BP };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1),
    ArrayRef(AltOrder2)
  };
  const unsigned Select = GPRCAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO, PPC::R2 };
  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP, PPC::ZERO };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1),
    ArrayRef(AltOrder2)
  };
  const unsigned Select = GPRC_NOR0AltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned GPRC_and_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> GPRC_and_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R31, PPC::R1, PPC::FP, PPC::BP, PPC::R2 };
  static const MCPhysReg AltOrder2[] = { PPC::R2, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::R31, PPC::R30, PPC::R29, PPC::R28, PPC::R27, PPC::R26, PPC::R25, PPC::R24, PPC::R23, PPC::R22, PPC::R21, PPC::R20, PPC::R19, PPC::R18, PPC::R17, PPC::R16, PPC::R15, PPC::R14, PPC::R13, PPC::R1, PPC::FP, PPC::BP };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1),
    ArrayRef(AltOrder2)
  };
  const unsigned Select = GPRC_and_GPRC_NOR0AltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned CRBITRCAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
           MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
  }

static ArrayRef<MCPhysReg> CRBITRCGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN, PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRBITRCRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = CRBITRCAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned CRRCAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
           MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
  }

static ArrayRef<MCPhysReg> CRRCGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7 };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::CRRCRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = CRRCAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned G8RCAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> G8RCGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
  static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X0, PPC::X1, PPC::FP8, PPC::BP8 };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1),
    ArrayRef(AltOrder2)
  };
  const unsigned Select = G8RCAltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8, PPC::X2 };
  static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::ZERO8 };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1),
    ArrayRef(AltOrder2)
  };
  const unsigned Select = G8RC_NOX0AltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned G8RC_and_G8RC_NOX0AltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().getGPRAllocationOrderIdx();
  }

static ArrayRef<MCPhysReg> G8RC_and_G8RC_NOX0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X31, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8, PPC::X2 };
  static const MCPhysReg AltOrder2[] = { PPC::X2, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::X31, PPC::X30, PPC::X29, PPC::X28, PPC::X27, PPC::X26, PPC::X25, PPC::X24, PPC::X23, PPC::X22, PPC::X21, PPC::X20, PPC::X19, PPC::X18, PPC::X17, PPC::X16, PPC::X15, PPC::X14, PPC::X13, PPC::X1, PPC::FP8, PPC::BP8 };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_and_G8RC_NOX0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1),
    ArrayRef(AltOrder2)
  };
  const unsigned Select = G8RC_and_G8RC_NOX0AltOrderSelect(MF);
  assert(Select < 3);
  return Order[Select];
}

static inline unsigned G8pRCAltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
  }

static ArrayRef<MCPhysReg> G8pRCGetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p0, PPC::G8p1 };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRCRegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = G8pRCAltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

static inline unsigned G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(const MachineFunction &MF) {
    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
  }

static ArrayRef<MCPhysReg> G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder(const MachineFunction &MF) {
  static const MCPhysReg AltOrder1[] = { PPC::G8p2, PPC::G8p3, PPC::G8p4, PPC::G8p5, PPC::G8p14, PPC::G8p13, PPC::G8p12, PPC::G8p11, PPC::G8p10, PPC::G8p9, PPC::G8p8, PPC::G8p7, PPC::G8p15, PPC::G8p6, PPC::G8p1 };
  const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClassID];
  const ArrayRef<MCPhysReg> Order[] = {
    ArrayRef(MCR.begin(), MCR.getNumRegs()),
    ArrayRef(AltOrder1)
  };
  const unsigned Select = G8pRC_with_sub_32_in_GPRC_NOR0AltOrderSelect(MF);
  assert(Select < 2);
  return Order[Select];
}

namespace PPC {   // Register class instances
  extern const TargetRegisterClass VSSRCRegClass = {
    &PPCMCRegisterClasses[VSSRCRegClassID],
    VSSRCSubClassMask,
    SuperRegIdxSeqs + 25,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRCRegClass = {
    &PPCMCRegisterClasses[GPRCRegClassID],
    GPRCSubClassMask,
    SuperRegIdxSeqs + 73,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    GPRCGetRawAllocationOrder
  };

  extern const TargetRegisterClass GPRC_NOR0RegClass = {
    &PPCMCRegisterClasses[GPRC_NOR0RegClassID],
    GPRC_NOR0SubClassMask,
    SuperRegIdxSeqs + 73,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    GPRC_NOR0GetRawAllocationOrder
  };

  extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = {
    &PPCMCRegisterClasses[GPRC_and_GPRC_NOR0RegClassID],
    GPRC_and_GPRC_NOR0SubClassMask,
    SuperRegIdxSeqs + 73,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRC_and_GPRC_NOR0Superclasses,
    GPRC_and_GPRC_NOR0GetRawAllocationOrder
  };

  extern const TargetRegisterClass CRBITRCRegClass = {
    &PPCMCRegisterClasses[CRBITRCRegClassID],
    CRBITRCSubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    CRBITRCGetRawAllocationOrder
  };

  extern const TargetRegisterClass F4RCRegClass = {
    &PPCMCRegisterClasses[F4RCRegClassID],
    F4RCSubClassMask,
    SuperRegIdxSeqs + 25,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    F4RCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRC32RegClass = {
    &PPCMCRegisterClasses[GPRC32RegClassID],
    GPRC32SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CRRCRegClass = {
    &PPCMCRegisterClasses[CRRCRegClassID],
    CRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000720),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    CRRCGetRawAllocationOrder
  };

  extern const TargetRegisterClass CARRYRCRegClass = {
    &PPCMCRegisterClasses[CARRYRCRegClassID],
    CARRYRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CTRRCRegClass = {
    &PPCMCRegisterClasses[CTRRCRegClassID],
    CTRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LRRCRegClass = {
    &PPCMCRegisterClasses[LRRCRegClassID],
    LRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRSAVERCRegClass = {
    &PPCMCRegisterClasses[VRSAVERCRegClassID],
    VRSAVERCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[SPILLTOVSRRCRegClassID],
    SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 32,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VSFRCRegClass = {
    &PPCMCRegisterClasses[VSFRCRegClassID],
    VSFRCSubClassMask,
    SuperRegIdxSeqs + 25,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSFRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass G8RCRegClass = {
    &PPCMCRegisterClasses[G8RCRegClassID],
    G8RCSubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    G8RCSuperclasses,
    G8RCGetRawAllocationOrder
  };

  extern const TargetRegisterClass G8RC_NOX0RegClass = {
    &PPCMCRegisterClasses[G8RC_NOX0RegClassID],
    G8RC_NOX0SubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    G8RC_NOX0GetRawAllocationOrder
  };

  extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = {
    &PPCMCRegisterClasses[SPILLTOVSRRC_and_VSFRCRegClassID],
    SPILLTOVSRRC_and_VSFRCSubClassMask,
    SuperRegIdxSeqs + 25,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SPILLTOVSRRC_and_VSFRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = {
    &PPCMCRegisterClasses[G8RC_and_G8RC_NOX0RegClassID],
    G8RC_and_G8RC_NOX0SubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    G8RC_and_G8RC_NOX0Superclasses,
    G8RC_and_G8RC_NOX0GetRawAllocationOrder
  };

  extern const TargetRegisterClass F8RCRegClass = {
    &PPCMCRegisterClasses[F8RCRegClassID],
    F8RCSubClassMask,
    SuperRegIdxSeqs + 25,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    F8RCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass SPERCRegClass = {
    &PPCMCRegisterClasses[SPERCRegClassID],
    SPERCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VFRCRegClass = {
    &PPCMCRegisterClasses[VFRCRegClassID],
    VFRCSubClassMask,
    SuperRegIdxSeqs + 17,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VFRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = {
    &PPCMCRegisterClasses[SPERC_with_sub_32_in_GPRC_NOR0RegClassID],
    SPERC_with_sub_32_in_GPRC_NOR0SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    SPERC_with_sub_32_in_GPRC_NOR0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = {
    &PPCMCRegisterClasses[SPILLTOVSRRC_and_VFRCRegClassID],
    SPILLTOVSRRC_and_VFRCSubClassMask,
    SuperRegIdxSeqs + 17,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SPILLTOVSRRC_and_VFRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = {
    &PPCMCRegisterClasses[SPILLTOVSRRC_and_F4RCRegClassID],
    SPILLTOVSRRC_and_F4RCSubClassMask,
    SuperRegIdxSeqs + 25,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SPILLTOVSRRC_and_F4RCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass CTRRC8RegClass = {
    &PPCMCRegisterClasses[CTRRC8RegClassID],
    CTRRC8SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LR8RCRegClass = {
    &PPCMCRegisterClasses[LR8RCRegClassID],
    LR8RCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DMRROWRCRegClass = {
    &PPCMCRegisterClasses[DMRROWRCRegClassID],
    DMRROWRCSubClassMask,
    SuperRegIdxSeqs + 56,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VSRCRegClass = {
    &PPCMCRegisterClasses[VSRCRegClassID],
    VSRCSubClassMask,
    SuperRegIdxSeqs + 20,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
    VSRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 20,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VRRCRegClass = {
    &PPCMCRegisterClasses[VRRCRegClassID],
    VRRCSubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VSLRCRegClass = {
    &PPCMCRegisterClasses[VSLRCRegClassID],
    VSLRCSubClassMask,
    SuperRegIdxSeqs + 20,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSLRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
    VRRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 14,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FpRCRegClass = {
    &PPCMCRegisterClasses[FpRCRegClassID],
    FpRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000000000000C0),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass G8pRCRegClass = {
    &PPCMCRegisterClasses[G8pRCRegClassID],
    G8pRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000010000001),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    G8pRCGetRawAllocationOrder
  };

  extern const TargetRegisterClass G8pRC_with_sub_32_in_GPRC_NOR0RegClass = {
    &PPCMCRegisterClasses[G8pRC_with_sub_32_in_GPRC_NOR0RegClassID],
    G8pRC_with_sub_32_in_GPRC_NOR0SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000010000001),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    G8pRC_with_sub_32_in_GPRC_NOR0Superclasses,
    G8pRC_with_sub_32_in_GPRC_NOR0GetRawAllocationOrder
  };

  extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
    VSLRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 20,
    LaneBitmask(0x0000000000000004),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID],
    FpRC_with_sub_fp0_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x00000000000000C0),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FpRC_with_sub_fp0_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DMRROWpRCRegClass = {
    &PPCMCRegisterClasses[DMRROWpRCRegClassID],
    DMRROWpRCSubClassMask,
    SuperRegIdxSeqs + 47,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VSRpRCRegClass = {
    &PPCMCRegisterClasses[VSRpRCRegClassID],
    VSRpRCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000804),
    2,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
    VSRpRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000804),
    2,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSRpRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VSRpRC_with_sub_64_in_F4RCRegClass = {
    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_F4RCRegClassID],
    VSRpRC_with_sub_64_in_F4RCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000804),
    2,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSRpRC_with_sub_64_in_F4RCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VSRpRC_with_sub_64_in_VFRCRegClass = {
    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_VFRCRegClassID],
    VSRpRC_with_sub_64_in_VFRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000804),
    2,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSRpRC_with_sub_64_in_VFRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass = {
    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID],
    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000804),
    2,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass = {
    &PPCMCRegisterClasses[VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID],
    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000804),
    2,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass ACCRCRegClass = {
    &PPCMCRegisterClasses[ACCRCRegClassID],
    ACCRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000003804),
    31,
    true,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass UACCRCRegClass = {
    &PPCMCRegisterClasses[UACCRCRegClassID],
    UACCRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000003804),
    4,
    true,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass WACCRCRegClass = {
    &PPCMCRegisterClasses[WACCRCRegClassID],
    WACCRCSubClassMask,
    SuperRegIdxSeqs + 44,
    LaneBitmask(0x000000000000C018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass WACC_HIRCRegClass = {
    &PPCMCRegisterClasses[WACC_HIRCRegClassID],
    WACC_HIRCSubClassMask,
    SuperRegIdxSeqs + 41,
    LaneBitmask(0x000000000000C018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
    ACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000003804),
    31,
    true,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    ACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID],
    UACCRC_with_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000003804),
    4,
    true,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    UACCRC_with_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
    ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000003804),
    31,
    true,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass = {
    &PPCMCRegisterClasses[UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID],
    UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000003804),
    4,
    true,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass DMRRCRegClass = {
    &PPCMCRegisterClasses[DMRRCRegClassID],
    DMRRCSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x00000000000FC018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DMRpRCRegClass = {
    &PPCMCRegisterClasses[DMRpRCRegClassID],
    DMRpRCSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x000000000FFFC018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

} // end namespace PPC

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &PPC::VSSRCRegClass,
    &PPC::GPRCRegClass,
    &PPC::GPRC_NOR0RegClass,
    &PPC::GPRC_and_GPRC_NOR0RegClass,
    &PPC::CRBITRCRegClass,
    &PPC::F4RCRegClass,
    &PPC::GPRC32RegClass,
    &PPC::CRRCRegClass,
    &PPC::CARRYRCRegClass,
    &PPC::CTRRCRegClass,
    &PPC::LRRCRegClass,
    &PPC::VRSAVERCRegClass,
    &PPC::SPILLTOVSRRCRegClass,
    &PPC::VSFRCRegClass,
    &PPC::G8RCRegClass,
    &PPC::G8RC_NOX0RegClass,
    &PPC::SPILLTOVSRRC_and_VSFRCRegClass,
    &PPC::G8RC_and_G8RC_NOX0RegClass,
    &PPC::F8RCRegClass,
    &PPC::SPERCRegClass,
    &PPC::VFRCRegClass,
    &PPC::SPERC_with_sub_32_in_GPRC_NOR0RegClass,
    &PPC::SPILLTOVSRRC_and_VFRCRegClass,
    &PPC::SPILLTOVSRRC_and_F4RCRegClass,
    &PPC::CTRRC8RegClass,
    &PPC::LR8RCRegClass,
    &PPC::DMRROWRCRegClass,
    &PPC::VSRCRegClass,
    &PPC::VSRC_with_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::VRRCRegClass,
    &PPC::VSLRCRegClass,
    &PPC::VRRC_with_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::FpRCRegClass,
    &PPC::G8pRCRegClass,
    &PPC::G8pRC_with_sub_32_in_GPRC_NOR0RegClass,
    &PPC::VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClass,
    &PPC::DMRROWpRCRegClass,
    &PPC::VSRpRCRegClass,
    &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::VSRpRC_with_sub_64_in_F4RCRegClass,
    &PPC::VSRpRC_with_sub_64_in_VFRCRegClass,
    &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClass,
    &PPC::VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClass,
    &PPC::ACCRCRegClass,
    &PPC::UACCRCRegClass,
    &PPC::WACCRCRegClass,
    &PPC::WACC_HIRCRegClass,
    &PPC::ACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::UACCRC_with_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClass,
    &PPC::DMRRCRegClass,
    &PPC::DMRpRCRegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, false, true, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc PPCRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned PPCGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[51] = {
    0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 2, 3, 0, 0, 0, 1, 3, 0, 0, 0, 0, 0, 3, 4, 0, 0, 0, 0, 1, 5, 6, 1, 0, 0, 0, 0, 6, 7, 0, 0, 0, 
  };
  static const uint8_t Rows[8][51] = {
    { PPC::sub_32, 0, PPC::sub_64, 0, 0, PPC::sub_dmrrow0, PPC::sub_dmrrow1, PPC::sub_dmrrowp0, PPC::sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_vsx0, PPC::sub_vsx1, PPC::sub_wacc_hi, PPC::sub_wacc_lo, PPC::sub_vsx1_then_sub_64, 0, 0, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { PPC::sub_gp8_x1_then_sub_32, 0, PPC::sub_pair1_then_sub_64, 0, 0, PPC::sub_dmr1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_pair1_then_sub_vsx0, PPC::sub_pair1_then_sub_vsx1, PPC::sub_dmr1_then_sub_wacc_hi, PPC::sub_dmr1_then_sub_wacc_lo, PPC::sub_pair1_then_sub_vsx1_then_sub_64, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, PPC::sub_vsx1_then_sub_64, 0, 0, PPC::sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, PPC::sub_pair1_then_sub_vsx1_then_sub_64, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrow1, PPC::sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, 0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, 0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, PPC::sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
  };

  --IdxA; assert(IdxA < 51); (void) IdxA;
  --IdxB; assert(IdxB < 51);
  return Rows[RowMap[IdxA]][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0x0000000000000018), 17 }, { LaneBitmask(0x00000000000FC000),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 9
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 11
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 11 }, { LaneBitmask::getNone(), 0 },   // Sequence 13
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 15
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 17
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 19
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 28 }, { LaneBitmask::getNone(), 0 },   // Sequence 21
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 23
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 25
    { LaneBitmask(0x0000000000000004), 10 }, { LaneBitmask(0x0000000000000800),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 27
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 },   // Sequence 30
    { LaneBitmask(0x0000000000000018), 13 }, { LaneBitmask(0x000000000000C000),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 32
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 35
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 13 }, { LaneBitmask::getNone(), 0 },   // Sequence 37
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 14 }, { LaneBitmask::getNone(), 0 },   // Sequence 39
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 15 }, { LaneBitmask::getNone(), 0 },   // Sequence 41
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 16 }, { LaneBitmask::getNone(), 0 },   // Sequence 43
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 17 }, { LaneBitmask::getNone(), 0 },   // Sequence 45
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 18 }, { LaneBitmask::getNone(), 0 },   // Sequence 47
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 19 }, { LaneBitmask::getNone(), 0 },   // Sequence 49
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 20 }, { LaneBitmask::getNone(), 0 },   // Sequence 51
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 21 }, { LaneBitmask::getNone(), 0 },   // Sequence 53
    { LaneBitmask(0x0000000000000018), 21 }, { LaneBitmask(0x000000000000C000), 12 }, { LaneBitmask::getNone(), 0 },   // Sequence 55
    { LaneBitmask(0x0000000000000018), 17 }, { LaneBitmask(0x000000000000C000),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 58
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 22 }, { LaneBitmask::getNone(), 0 },   // Sequence 61
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 23 }, { LaneBitmask::getNone(), 0 },   // Sequence 63
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 24 }, { LaneBitmask::getNone(), 0 },   // Sequence 65
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 25 }, { LaneBitmask::getNone(), 0 },   // Sequence 67
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 26 }, { LaneBitmask::getNone(), 0 },   // Sequence 69
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 27 }, { LaneBitmask::getNone(), 0 }  // Sequence 71
  };
  static const uint8_t CompositeSequences[] = {
    0, // to sub_32
    2, // to sub_32_hi_phony
    4, // to sub_64
    0, // to sub_dmr0
    6, // to sub_dmr1
    9, // to sub_dmrrow0
    11, // to sub_dmrrow1
    0, // to sub_dmrrowp0
    13, // to sub_dmrrowp1
    15, // to sub_eq
    17, // to sub_fp0
    19, // to sub_fp1
    0, // to sub_gp8_x0
    21, // to sub_gp8_x1
    23, // to sub_gt
    25, // to sub_lt
    0, // to sub_pair0
    27, // to sub_pair1
    30, // to sub_un
    0, // to sub_vsx0
    25, // to sub_vsx1
    32, // to sub_wacc_hi
    0, // to sub_wacc_lo
    13, // to sub_vsx1_then_sub_64
    35, // to sub_pair1_then_sub_64
    30, // to sub_pair1_then_sub_vsx0
    13, // to sub_pair1_then_sub_vsx1
    37, // to sub_pair1_then_sub_vsx1_then_sub_64
    39, // to sub_dmrrowp1_then_sub_dmrrow0
    41, // to sub_dmrrowp1_then_sub_dmrrow1
    43, // to sub_wacc_hi_then_sub_dmrrow0
    45, // to sub_wacc_hi_then_sub_dmrrow1
    37, // to sub_wacc_hi_then_sub_dmrrowp0
    41, // to sub_wacc_hi_then_sub_dmrrowp1
    47, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
    49, // to sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
    51, // to sub_dmr1_then_sub_dmrrow0
    53, // to sub_dmr1_then_sub_dmrrow1
    45, // to sub_dmr1_then_sub_dmrrowp0
    49, // to sub_dmr1_then_sub_dmrrowp1
    55, // to sub_dmr1_then_sub_wacc_hi
    58, // to sub_dmr1_then_sub_wacc_lo
    61, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
    63, // to sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
    65, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
    67, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
    53, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
    63, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
    69, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
    71, // to sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
    21 // to sub_gp8_x1_then_sub_32
  };

LaneBitmask PPCGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 51 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask PPCGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 51 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[54][51] = {
    { // VSSRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // GPRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // GPRC_NOR0
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // GPRC_and_GPRC_NOR0
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // CRBITRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // F4RC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // GPRC32
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // CRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      8,  // sub_eq -> CRRC
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      8,  // sub_gt -> CRRC
      8,  // sub_lt -> CRRC
      0,  // sub_pair0
      0,  // sub_pair1
      8,  // sub_un -> CRRC
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // CARRYRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // CTRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // LRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VRSAVERC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC
      15, // sub_32 -> G8RC
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSFRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // G8RC
      15, // sub_32 -> G8RC
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // G8RC_NOX0
      16, // sub_32 -> G8RC_NOX0
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC_and_VSFRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // G8RC_and_G8RC_NOX0
      18, // sub_32 -> G8RC_and_G8RC_NOX0
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // F8RC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // SPERC
      20, // sub_32 -> SPERC
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VFRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // SPERC_with_sub_32_in_GPRC_NOR0
      22, // sub_32 -> SPERC_with_sub_32_in_GPRC_NOR0
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC_and_VFRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC_and_F4RC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // CTRRC8
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // LR8RC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // DMRROWRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      28, // sub_64 -> VSRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      29, // sub_64 -> VSRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      30, // sub_64 -> VRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSLRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      31, // sub_64 -> VSLRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VRRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      32, // sub_64 -> VRRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // FpRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      33, // sub_fp0 -> FpRC
      33, // sub_fp1 -> FpRC
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // G8pRC
      34, // sub_32 -> G8pRC
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      34, // sub_gp8_x0 -> G8pRC
      34, // sub_gp8_x1 -> G8pRC
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      34, // sub_gp8_x1_then_sub_32 -> G8pRC
    },
    { // G8pRC_with_sub_32_in_GPRC_NOR0
      35, // sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      35, // sub_gp8_x0 -> G8pRC_with_sub_32_in_GPRC_NOR0
      35, // sub_gp8_x1 -> G8pRC_with_sub_32_in_GPRC_NOR0
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      35, // sub_gp8_x1_then_sub_32 -> G8pRC_with_sub_32_in_GPRC_NOR0
    },
    { // VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      36, // sub_64 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // FpRC_with_sub_fp0_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      37, // sub_fp0 -> FpRC_with_sub_fp0_in_SPILLTOVSRRC
      37, // sub_fp1 -> FpRC_with_sub_fp0_in_SPILLTOVSRRC
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // DMRROWpRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      38, // sub_dmrrow0 -> DMRROWpRC
      38, // sub_dmrrow1 -> DMRROWpRC
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRpRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      39, // sub_64 -> VSRpRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      39, // sub_vsx0 -> VSRpRC
      39, // sub_vsx1 -> VSRpRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      39, // sub_vsx1_then_sub_64 -> VSRpRC
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      40, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      40, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
      40, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      40, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_F4RC
      0,  // sub_32
      0,  // sub_32_hi_phony
      41, // sub_64 -> VSRpRC_with_sub_64_in_F4RC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      41, // sub_vsx0 -> VSRpRC_with_sub_64_in_F4RC
      41, // sub_vsx1 -> VSRpRC_with_sub_64_in_F4RC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      41, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_F4RC
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_VFRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      42, // sub_64 -> VSRpRC_with_sub_64_in_VFRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      42, // sub_vsx0 -> VSRpRC_with_sub_64_in_VFRC
      42, // sub_vsx1 -> VSRpRC_with_sub_64_in_VFRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      42, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_VFRC
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      43, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      43, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
      43, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      43, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // sub_32
      0,  // sub_32_hi_phony
      44, // sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      44, // sub_vsx0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      44, // sub_vsx1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      44, // sub_vsx1_then_sub_64 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // ACCRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      45, // sub_64 -> ACCRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      45, // sub_pair0 -> ACCRC
      45, // sub_pair1 -> ACCRC
      0,  // sub_un
      45, // sub_vsx0 -> ACCRC
      45, // sub_vsx1 -> ACCRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      45, // sub_vsx1_then_sub_64 -> ACCRC
      45, // sub_pair1_then_sub_64 -> ACCRC
      45, // sub_pair1_then_sub_vsx0 -> ACCRC
      45, // sub_pair1_then_sub_vsx1 -> ACCRC
      45, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // UACCRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      46, // sub_64 -> UACCRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      46, // sub_pair0 -> UACCRC
      46, // sub_pair1 -> UACCRC
      0,  // sub_un
      46, // sub_vsx0 -> UACCRC
      46, // sub_vsx1 -> UACCRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      46, // sub_vsx1_then_sub_64 -> UACCRC
      46, // sub_pair1_then_sub_64 -> UACCRC
      46, // sub_pair1_then_sub_vsx0 -> UACCRC
      46, // sub_pair1_then_sub_vsx1 -> UACCRC
      46, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // WACCRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      47, // sub_dmrrow0 -> WACCRC
      47, // sub_dmrrow1 -> WACCRC
      47, // sub_dmrrowp0 -> WACCRC
      47, // sub_dmrrowp1 -> WACCRC
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      47, // sub_dmrrowp1_then_sub_dmrrow0 -> WACCRC
      47, // sub_dmrrowp1_then_sub_dmrrow1 -> WACCRC
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // WACC_HIRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      48, // sub_dmrrow0 -> WACC_HIRC
      48, // sub_dmrrow1 -> WACC_HIRC
      48, // sub_dmrrowp0 -> WACC_HIRC
      48, // sub_dmrrowp1 -> WACC_HIRC
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      48, // sub_dmrrowp1_then_sub_dmrrow0 -> WACC_HIRC
      48, // sub_dmrrowp1_then_sub_dmrrow1 -> WACC_HIRC
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // ACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      49, // sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      49, // sub_pair0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      49, // sub_pair1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_un
      49, // sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      49, // sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      49, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      49, // sub_pair1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      49, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      49, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      49, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // UACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      50, // sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      50, // sub_pair0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      50, // sub_pair1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_un
      50, // sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      50, // sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      50, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      50, // sub_pair1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      50, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      50, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      50, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      51, // sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      51, // sub_pair0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      51, // sub_pair1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_un
      51, // sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      51, // sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      51, // sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      51, // sub_pair1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      51, // sub_pair1_then_sub_vsx0 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      51, // sub_pair1_then_sub_vsx1 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      51, // sub_pair1_then_sub_vsx1_then_sub_64 -> ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      52, // sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmr0
      0,  // sub_dmr1
      0,  // sub_dmrrow0
      0,  // sub_dmrrow1
      0,  // sub_dmrrowp0
      0,  // sub_dmrrowp1
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      52, // sub_pair0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      52, // sub_pair1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_un
      52, // sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      52, // sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_wacc_hi
      0,  // sub_wacc_lo
      52, // sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      52, // sub_pair1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      52, // sub_pair1_then_sub_vsx0 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      52, // sub_pair1_then_sub_vsx1 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      52, // sub_pair1_then_sub_vsx1_then_sub_64 -> UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // DMRRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      0,  // sub_dmr0
      0,  // sub_dmr1
      53, // sub_dmrrow0 -> DMRRC
      53, // sub_dmrrow1 -> DMRRC
      53, // sub_dmrrowp0 -> DMRRC
      53, // sub_dmrrowp1 -> DMRRC
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      53, // sub_wacc_hi -> DMRRC
      53, // sub_wacc_lo -> DMRRC
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      53, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
      53, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
      53, // sub_wacc_hi_then_sub_dmrrow0 -> DMRRC
      53, // sub_wacc_hi_then_sub_dmrrow1 -> DMRRC
      53, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRRC
      53, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRRC
      53, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRRC
      53, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRRC
      0,  // sub_dmr1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi
      0,  // sub_dmr1_then_sub_wacc_lo
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // sub_gp8_x1_then_sub_32
    },
    { // DMRpRC
      0,  // sub_32
      0,  // sub_32_hi_phony
      0,  // sub_64
      54, // sub_dmr0 -> DMRpRC
      54, // sub_dmr1 -> DMRpRC
      54, // sub_dmrrow0 -> DMRpRC
      54, // sub_dmrrow1 -> DMRpRC
      54, // sub_dmrrowp0 -> DMRpRC
      54, // sub_dmrrowp1 -> DMRpRC
      0,  // sub_eq
      0,  // sub_fp0
      0,  // sub_fp1
      0,  // sub_gp8_x0
      0,  // sub_gp8_x1
      0,  // sub_gt
      0,  // sub_lt
      0,  // sub_pair0
      0,  // sub_pair1
      0,  // sub_un
      0,  // sub_vsx0
      0,  // sub_vsx1
      54, // sub_wacc_hi -> DMRpRC
      54, // sub_wacc_lo -> DMRpRC
      0,  // sub_vsx1_then_sub_64
      0,  // sub_pair1_then_sub_64
      0,  // sub_pair1_then_sub_vsx0
      0,  // sub_pair1_then_sub_vsx1
      0,  // sub_pair1_then_sub_vsx1_then_sub_64
      54, // sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
      54, // sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
      54, // sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
      54, // sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
      54, // sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
      54, // sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
      54, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
      54, // sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
      54, // sub_dmr1_then_sub_dmrrow0 -> DMRpRC
      54, // sub_dmr1_then_sub_dmrrow1 -> DMRpRC
      54, // sub_dmr1_then_sub_dmrrowp0 -> DMRpRC
      54, // sub_dmr1_then_sub_dmrrowp1 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_lo -> DMRpRC
      54, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
      54, // sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRpRC
      54, // sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRpRC
      0,  // sub_gp8_x1_then_sub_32
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 51 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *PPCGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[54][51] = {
    { // VSSRC
      0,  // VSSRC:sub_32
      0,  // VSSRC:sub_32_hi_phony
      0,  // VSSRC:sub_64
      0,  // VSSRC:sub_dmr0
      0,  // VSSRC:sub_dmr1
      0,  // VSSRC:sub_dmrrow0
      0,  // VSSRC:sub_dmrrow1
      0,  // VSSRC:sub_dmrrowp0
      0,  // VSSRC:sub_dmrrowp1
      0,  // VSSRC:sub_eq
      0,  // VSSRC:sub_fp0
      0,  // VSSRC:sub_fp1
      0,  // VSSRC:sub_gp8_x0
      0,  // VSSRC:sub_gp8_x1
      0,  // VSSRC:sub_gt
      0,  // VSSRC:sub_lt
      0,  // VSSRC:sub_pair0
      0,  // VSSRC:sub_pair1
      0,  // VSSRC:sub_un
      0,  // VSSRC:sub_vsx0
      0,  // VSSRC:sub_vsx1
      0,  // VSSRC:sub_wacc_hi
      0,  // VSSRC:sub_wacc_lo
      0,  // VSSRC:sub_vsx1_then_sub_64
      0,  // VSSRC:sub_pair1_then_sub_64
      0,  // VSSRC:sub_pair1_then_sub_vsx0
      0,  // VSSRC:sub_pair1_then_sub_vsx1
      0,  // VSSRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSSRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSSRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSSRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSSRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSSRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSSRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSSRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSSRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSSRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSSRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSSRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSSRC:sub_gp8_x1_then_sub_32
    },
    { // GPRC
      0,  // GPRC:sub_32
      0,  // GPRC:sub_32_hi_phony
      0,  // GPRC:sub_64
      0,  // GPRC:sub_dmr0
      0,  // GPRC:sub_dmr1
      0,  // GPRC:sub_dmrrow0
      0,  // GPRC:sub_dmrrow1
      0,  // GPRC:sub_dmrrowp0
      0,  // GPRC:sub_dmrrowp1
      0,  // GPRC:sub_eq
      0,  // GPRC:sub_fp0
      0,  // GPRC:sub_fp1
      0,  // GPRC:sub_gp8_x0
      0,  // GPRC:sub_gp8_x1
      0,  // GPRC:sub_gt
      0,  // GPRC:sub_lt
      0,  // GPRC:sub_pair0
      0,  // GPRC:sub_pair1
      0,  // GPRC:sub_un
      0,  // GPRC:sub_vsx0
      0,  // GPRC:sub_vsx1
      0,  // GPRC:sub_wacc_hi
      0,  // GPRC:sub_wacc_lo
      0,  // GPRC:sub_vsx1_then_sub_64
      0,  // GPRC:sub_pair1_then_sub_64
      0,  // GPRC:sub_pair1_then_sub_vsx0
      0,  // GPRC:sub_pair1_then_sub_vsx1
      0,  // GPRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // GPRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC:sub_dmr1_then_sub_dmrrow0
      0,  // GPRC:sub_dmr1_then_sub_dmrrow1
      0,  // GPRC:sub_dmr1_then_sub_dmrrowp0
      0,  // GPRC:sub_dmr1_then_sub_dmrrowp1
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi
      0,  // GPRC:sub_dmr1_then_sub_wacc_lo
      0,  // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC:sub_gp8_x1_then_sub_32
    },
    { // GPRC_NOR0
      0,  // GPRC_NOR0:sub_32
      0,  // GPRC_NOR0:sub_32_hi_phony
      0,  // GPRC_NOR0:sub_64
      0,  // GPRC_NOR0:sub_dmr0
      0,  // GPRC_NOR0:sub_dmr1
      0,  // GPRC_NOR0:sub_dmrrow0
      0,  // GPRC_NOR0:sub_dmrrow1
      0,  // GPRC_NOR0:sub_dmrrowp0
      0,  // GPRC_NOR0:sub_dmrrowp1
      0,  // GPRC_NOR0:sub_eq
      0,  // GPRC_NOR0:sub_fp0
      0,  // GPRC_NOR0:sub_fp1
      0,  // GPRC_NOR0:sub_gp8_x0
      0,  // GPRC_NOR0:sub_gp8_x1
      0,  // GPRC_NOR0:sub_gt
      0,  // GPRC_NOR0:sub_lt
      0,  // GPRC_NOR0:sub_pair0
      0,  // GPRC_NOR0:sub_pair1
      0,  // GPRC_NOR0:sub_un
      0,  // GPRC_NOR0:sub_vsx0
      0,  // GPRC_NOR0:sub_vsx1
      0,  // GPRC_NOR0:sub_wacc_hi
      0,  // GPRC_NOR0:sub_wacc_lo
      0,  // GPRC_NOR0:sub_vsx1_then_sub_64
      0,  // GPRC_NOR0:sub_pair1_then_sub_64
      0,  // GPRC_NOR0:sub_pair1_then_sub_vsx0
      0,  // GPRC_NOR0:sub_pair1_then_sub_vsx1
      0,  // GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
      0,  // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
      0,  // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_NOR0:sub_gp8_x1_then_sub_32
    },
    { // GPRC_and_GPRC_NOR0
      0,  // GPRC_and_GPRC_NOR0:sub_32
      0,  // GPRC_and_GPRC_NOR0:sub_32_hi_phony
      0,  // GPRC_and_GPRC_NOR0:sub_64
      0,  // GPRC_and_GPRC_NOR0:sub_dmr0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1
      0,  // GPRC_and_GPRC_NOR0:sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_dmrrowp0
      0,  // GPRC_and_GPRC_NOR0:sub_dmrrowp1
      0,  // GPRC_and_GPRC_NOR0:sub_eq
      0,  // GPRC_and_GPRC_NOR0:sub_fp0
      0,  // GPRC_and_GPRC_NOR0:sub_fp1
      0,  // GPRC_and_GPRC_NOR0:sub_gp8_x0
      0,  // GPRC_and_GPRC_NOR0:sub_gp8_x1
      0,  // GPRC_and_GPRC_NOR0:sub_gt
      0,  // GPRC_and_GPRC_NOR0:sub_lt
      0,  // GPRC_and_GPRC_NOR0:sub_pair0
      0,  // GPRC_and_GPRC_NOR0:sub_pair1
      0,  // GPRC_and_GPRC_NOR0:sub_un
      0,  // GPRC_and_GPRC_NOR0:sub_vsx0
      0,  // GPRC_and_GPRC_NOR0:sub_vsx1
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_lo
      0,  // GPRC_and_GPRC_NOR0:sub_vsx1_then_sub_64
      0,  // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_64
      0,  // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx0
      0,  // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1
      0,  // GPRC_and_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC_and_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC_and_GPRC_NOR0:sub_gp8_x1_then_sub_32
    },
    { // CRBITRC
      0,  // CRBITRC:sub_32
      0,  // CRBITRC:sub_32_hi_phony
      0,  // CRBITRC:sub_64
      0,  // CRBITRC:sub_dmr0
      0,  // CRBITRC:sub_dmr1
      0,  // CRBITRC:sub_dmrrow0
      0,  // CRBITRC:sub_dmrrow1
      0,  // CRBITRC:sub_dmrrowp0
      0,  // CRBITRC:sub_dmrrowp1
      0,  // CRBITRC:sub_eq
      0,  // CRBITRC:sub_fp0
      0,  // CRBITRC:sub_fp1
      0,  // CRBITRC:sub_gp8_x0
      0,  // CRBITRC:sub_gp8_x1
      0,  // CRBITRC:sub_gt
      0,  // CRBITRC:sub_lt
      0,  // CRBITRC:sub_pair0
      0,  // CRBITRC:sub_pair1
      0,  // CRBITRC:sub_un
      0,  // CRBITRC:sub_vsx0
      0,  // CRBITRC:sub_vsx1
      0,  // CRBITRC:sub_wacc_hi
      0,  // CRBITRC:sub_wacc_lo
      0,  // CRBITRC:sub_vsx1_then_sub_64
      0,  // CRBITRC:sub_pair1_then_sub_64
      0,  // CRBITRC:sub_pair1_then_sub_vsx0
      0,  // CRBITRC:sub_pair1_then_sub_vsx1
      0,  // CRBITRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // CRBITRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRBITRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRBITRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // CRBITRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // CRBITRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRBITRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRBITRC:sub_dmr1_then_sub_dmrrow0
      0,  // CRBITRC:sub_dmr1_then_sub_dmrrow1
      0,  // CRBITRC:sub_dmr1_then_sub_dmrrowp0
      0,  // CRBITRC:sub_dmr1_then_sub_dmrrowp1
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_lo
      0,  // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRBITRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRBITRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRBITRC:sub_gp8_x1_then_sub_32
    },
    { // F4RC
      0,  // F4RC:sub_32
      0,  // F4RC:sub_32_hi_phony
      0,  // F4RC:sub_64
      0,  // F4RC:sub_dmr0
      0,  // F4RC:sub_dmr1
      0,  // F4RC:sub_dmrrow0
      0,  // F4RC:sub_dmrrow1
      0,  // F4RC:sub_dmrrowp0
      0,  // F4RC:sub_dmrrowp1
      0,  // F4RC:sub_eq
      0,  // F4RC:sub_fp0
      0,  // F4RC:sub_fp1
      0,  // F4RC:sub_gp8_x0
      0,  // F4RC:sub_gp8_x1
      0,  // F4RC:sub_gt
      0,  // F4RC:sub_lt
      0,  // F4RC:sub_pair0
      0,  // F4RC:sub_pair1
      0,  // F4RC:sub_un
      0,  // F4RC:sub_vsx0
      0,  // F4RC:sub_vsx1
      0,  // F4RC:sub_wacc_hi
      0,  // F4RC:sub_wacc_lo
      0,  // F4RC:sub_vsx1_then_sub_64
      0,  // F4RC:sub_pair1_then_sub_64
      0,  // F4RC:sub_pair1_then_sub_vsx0
      0,  // F4RC:sub_pair1_then_sub_vsx1
      0,  // F4RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // F4RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // F4RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // F4RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // F4RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // F4RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // F4RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // F4RC:sub_dmr1_then_sub_dmrrow0
      0,  // F4RC:sub_dmr1_then_sub_dmrrow1
      0,  // F4RC:sub_dmr1_then_sub_dmrrowp0
      0,  // F4RC:sub_dmr1_then_sub_dmrrowp1
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi
      0,  // F4RC:sub_dmr1_then_sub_wacc_lo
      0,  // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // F4RC:sub_gp8_x1_then_sub_32
    },
    { // GPRC32
      0,  // GPRC32:sub_32
      0,  // GPRC32:sub_32_hi_phony
      0,  // GPRC32:sub_64
      0,  // GPRC32:sub_dmr0
      0,  // GPRC32:sub_dmr1
      0,  // GPRC32:sub_dmrrow0
      0,  // GPRC32:sub_dmrrow1
      0,  // GPRC32:sub_dmrrowp0
      0,  // GPRC32:sub_dmrrowp1
      0,  // GPRC32:sub_eq
      0,  // GPRC32:sub_fp0
      0,  // GPRC32:sub_fp1
      0,  // GPRC32:sub_gp8_x0
      0,  // GPRC32:sub_gp8_x1
      0,  // GPRC32:sub_gt
      0,  // GPRC32:sub_lt
      0,  // GPRC32:sub_pair0
      0,  // GPRC32:sub_pair1
      0,  // GPRC32:sub_un
      0,  // GPRC32:sub_vsx0
      0,  // GPRC32:sub_vsx1
      0,  // GPRC32:sub_wacc_hi
      0,  // GPRC32:sub_wacc_lo
      0,  // GPRC32:sub_vsx1_then_sub_64
      0,  // GPRC32:sub_pair1_then_sub_64
      0,  // GPRC32:sub_pair1_then_sub_vsx0
      0,  // GPRC32:sub_pair1_then_sub_vsx1
      0,  // GPRC32:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // GPRC32:sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC32:sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC32:sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC32:sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC32:sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC32:sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC32:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC32:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC32:sub_dmr1_then_sub_dmrrow0
      0,  // GPRC32:sub_dmr1_then_sub_dmrrow1
      0,  // GPRC32:sub_dmr1_then_sub_dmrrowp0
      0,  // GPRC32:sub_dmr1_then_sub_dmrrowp1
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi
      0,  // GPRC32:sub_dmr1_then_sub_wacc_lo
      0,  // GPRC32:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC32:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // GPRC32:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // GPRC32:sub_gp8_x1_then_sub_32
    },
    { // CRRC
      0,  // CRRC:sub_32
      0,  // CRRC:sub_32_hi_phony
      0,  // CRRC:sub_64
      0,  // CRRC:sub_dmr0
      0,  // CRRC:sub_dmr1
      0,  // CRRC:sub_dmrrow0
      0,  // CRRC:sub_dmrrow1
      0,  // CRRC:sub_dmrrowp0
      0,  // CRRC:sub_dmrrowp1
      5,  // CRRC:sub_eq -> CRBITRC
      0,  // CRRC:sub_fp0
      0,  // CRRC:sub_fp1
      0,  // CRRC:sub_gp8_x0
      0,  // CRRC:sub_gp8_x1
      5,  // CRRC:sub_gt -> CRBITRC
      5,  // CRRC:sub_lt -> CRBITRC
      0,  // CRRC:sub_pair0
      0,  // CRRC:sub_pair1
      5,  // CRRC:sub_un -> CRBITRC
      0,  // CRRC:sub_vsx0
      0,  // CRRC:sub_vsx1
      0,  // CRRC:sub_wacc_hi
      0,  // CRRC:sub_wacc_lo
      0,  // CRRC:sub_vsx1_then_sub_64
      0,  // CRRC:sub_pair1_then_sub_64
      0,  // CRRC:sub_pair1_then_sub_vsx0
      0,  // CRRC:sub_pair1_then_sub_vsx1
      0,  // CRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // CRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // CRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // CRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // CRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRRC:sub_dmr1_then_sub_dmrrow0
      0,  // CRRC:sub_dmr1_then_sub_dmrrow1
      0,  // CRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // CRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi
      0,  // CRRC:sub_dmr1_then_sub_wacc_lo
      0,  // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CRRC:sub_gp8_x1_then_sub_32
    },
    { // CARRYRC
      0,  // CARRYRC:sub_32
      0,  // CARRYRC:sub_32_hi_phony
      0,  // CARRYRC:sub_64
      0,  // CARRYRC:sub_dmr0
      0,  // CARRYRC:sub_dmr1
      0,  // CARRYRC:sub_dmrrow0
      0,  // CARRYRC:sub_dmrrow1
      0,  // CARRYRC:sub_dmrrowp0
      0,  // CARRYRC:sub_dmrrowp1
      0,  // CARRYRC:sub_eq
      0,  // CARRYRC:sub_fp0
      0,  // CARRYRC:sub_fp1
      0,  // CARRYRC:sub_gp8_x0
      0,  // CARRYRC:sub_gp8_x1
      0,  // CARRYRC:sub_gt
      0,  // CARRYRC:sub_lt
      0,  // CARRYRC:sub_pair0
      0,  // CARRYRC:sub_pair1
      0,  // CARRYRC:sub_un
      0,  // CARRYRC:sub_vsx0
      0,  // CARRYRC:sub_vsx1
      0,  // CARRYRC:sub_wacc_hi
      0,  // CARRYRC:sub_wacc_lo
      0,  // CARRYRC:sub_vsx1_then_sub_64
      0,  // CARRYRC:sub_pair1_then_sub_64
      0,  // CARRYRC:sub_pair1_then_sub_vsx0
      0,  // CARRYRC:sub_pair1_then_sub_vsx1
      0,  // CARRYRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // CARRYRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // CARRYRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // CARRYRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // CARRYRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // CARRYRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CARRYRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CARRYRC:sub_dmr1_then_sub_dmrrow0
      0,  // CARRYRC:sub_dmr1_then_sub_dmrrow1
      0,  // CARRYRC:sub_dmr1_then_sub_dmrrowp0
      0,  // CARRYRC:sub_dmr1_then_sub_dmrrowp1
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_lo
      0,  // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CARRYRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CARRYRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CARRYRC:sub_gp8_x1_then_sub_32
    },
    { // CTRRC
      0,  // CTRRC:sub_32
      0,  // CTRRC:sub_32_hi_phony
      0,  // CTRRC:sub_64
      0,  // CTRRC:sub_dmr0
      0,  // CTRRC:sub_dmr1
      0,  // CTRRC:sub_dmrrow0
      0,  // CTRRC:sub_dmrrow1
      0,  // CTRRC:sub_dmrrowp0
      0,  // CTRRC:sub_dmrrowp1
      0,  // CTRRC:sub_eq
      0,  // CTRRC:sub_fp0
      0,  // CTRRC:sub_fp1
      0,  // CTRRC:sub_gp8_x0
      0,  // CTRRC:sub_gp8_x1
      0,  // CTRRC:sub_gt
      0,  // CTRRC:sub_lt
      0,  // CTRRC:sub_pair0
      0,  // CTRRC:sub_pair1
      0,  // CTRRC:sub_un
      0,  // CTRRC:sub_vsx0
      0,  // CTRRC:sub_vsx1
      0,  // CTRRC:sub_wacc_hi
      0,  // CTRRC:sub_wacc_lo
      0,  // CTRRC:sub_vsx1_then_sub_64
      0,  // CTRRC:sub_pair1_then_sub_64
      0,  // CTRRC:sub_pair1_then_sub_vsx0
      0,  // CTRRC:sub_pair1_then_sub_vsx1
      0,  // CTRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // CTRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // CTRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // CTRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // CTRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC:sub_dmr1_then_sub_dmrrow0
      0,  // CTRRC:sub_dmr1_then_sub_dmrrow1
      0,  // CTRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // CTRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi
      0,  // CTRRC:sub_dmr1_then_sub_wacc_lo
      0,  // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC:sub_gp8_x1_then_sub_32
    },
    { // LRRC
      0,  // LRRC:sub_32
      0,  // LRRC:sub_32_hi_phony
      0,  // LRRC:sub_64
      0,  // LRRC:sub_dmr0
      0,  // LRRC:sub_dmr1
      0,  // LRRC:sub_dmrrow0
      0,  // LRRC:sub_dmrrow1
      0,  // LRRC:sub_dmrrowp0
      0,  // LRRC:sub_dmrrowp1
      0,  // LRRC:sub_eq
      0,  // LRRC:sub_fp0
      0,  // LRRC:sub_fp1
      0,  // LRRC:sub_gp8_x0
      0,  // LRRC:sub_gp8_x1
      0,  // LRRC:sub_gt
      0,  // LRRC:sub_lt
      0,  // LRRC:sub_pair0
      0,  // LRRC:sub_pair1
      0,  // LRRC:sub_un
      0,  // LRRC:sub_vsx0
      0,  // LRRC:sub_vsx1
      0,  // LRRC:sub_wacc_hi
      0,  // LRRC:sub_wacc_lo
      0,  // LRRC:sub_vsx1_then_sub_64
      0,  // LRRC:sub_pair1_then_sub_64
      0,  // LRRC:sub_pair1_then_sub_vsx0
      0,  // LRRC:sub_pair1_then_sub_vsx1
      0,  // LRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // LRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // LRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // LRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // LRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // LRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // LRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // LRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // LRRC:sub_dmr1_then_sub_dmrrow0
      0,  // LRRC:sub_dmr1_then_sub_dmrrow1
      0,  // LRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // LRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi
      0,  // LRRC:sub_dmr1_then_sub_wacc_lo
      0,  // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // LRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // LRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // LRRC:sub_gp8_x1_then_sub_32
    },
    { // VRSAVERC
      0,  // VRSAVERC:sub_32
      0,  // VRSAVERC:sub_32_hi_phony
      0,  // VRSAVERC:sub_64
      0,  // VRSAVERC:sub_dmr0
      0,  // VRSAVERC:sub_dmr1
      0,  // VRSAVERC:sub_dmrrow0
      0,  // VRSAVERC:sub_dmrrow1
      0,  // VRSAVERC:sub_dmrrowp0
      0,  // VRSAVERC:sub_dmrrowp1
      0,  // VRSAVERC:sub_eq
      0,  // VRSAVERC:sub_fp0
      0,  // VRSAVERC:sub_fp1
      0,  // VRSAVERC:sub_gp8_x0
      0,  // VRSAVERC:sub_gp8_x1
      0,  // VRSAVERC:sub_gt
      0,  // VRSAVERC:sub_lt
      0,  // VRSAVERC:sub_pair0
      0,  // VRSAVERC:sub_pair1
      0,  // VRSAVERC:sub_un
      0,  // VRSAVERC:sub_vsx0
      0,  // VRSAVERC:sub_vsx1
      0,  // VRSAVERC:sub_wacc_hi
      0,  // VRSAVERC:sub_wacc_lo
      0,  // VRSAVERC:sub_vsx1_then_sub_64
      0,  // VRSAVERC:sub_pair1_then_sub_64
      0,  // VRSAVERC:sub_pair1_then_sub_vsx0
      0,  // VRSAVERC:sub_pair1_then_sub_vsx1
      0,  // VRSAVERC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRSAVERC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRSAVERC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VRSAVERC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRSAVERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRSAVERC:sub_dmr1_then_sub_dmrrow0
      0,  // VRSAVERC:sub_dmr1_then_sub_dmrrow1
      0,  // VRSAVERC:sub_dmr1_then_sub_dmrrowp0
      0,  // VRSAVERC:sub_dmr1_then_sub_dmrrowp1
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_lo
      0,  // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRSAVERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRSAVERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRSAVERC:sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC
      2,  // SPILLTOVSRRC:sub_32 -> GPRC
      0,  // SPILLTOVSRRC:sub_32_hi_phony
      0,  // SPILLTOVSRRC:sub_64
      0,  // SPILLTOVSRRC:sub_dmr0
      0,  // SPILLTOVSRRC:sub_dmr1
      0,  // SPILLTOVSRRC:sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_dmrrowp0
      0,  // SPILLTOVSRRC:sub_dmrrowp1
      0,  // SPILLTOVSRRC:sub_eq
      0,  // SPILLTOVSRRC:sub_fp0
      0,  // SPILLTOVSRRC:sub_fp1
      0,  // SPILLTOVSRRC:sub_gp8_x0
      0,  // SPILLTOVSRRC:sub_gp8_x1
      0,  // SPILLTOVSRRC:sub_gt
      0,  // SPILLTOVSRRC:sub_lt
      0,  // SPILLTOVSRRC:sub_pair0
      0,  // SPILLTOVSRRC:sub_pair1
      0,  // SPILLTOVSRRC:sub_un
      0,  // SPILLTOVSRRC:sub_vsx0
      0,  // SPILLTOVSRRC:sub_vsx1
      0,  // SPILLTOVSRRC:sub_wacc_hi
      0,  // SPILLTOVSRRC:sub_wacc_lo
      0,  // SPILLTOVSRRC:sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC:sub_pair1_then_sub_64
      0,  // SPILLTOVSRRC:sub_pair1_then_sub_vsx0
      0,  // SPILLTOVSRRC:sub_pair1_then_sub_vsx1
      0,  // SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // VSFRC
      0,  // VSFRC:sub_32
      0,  // VSFRC:sub_32_hi_phony
      0,  // VSFRC:sub_64
      0,  // VSFRC:sub_dmr0
      0,  // VSFRC:sub_dmr1
      0,  // VSFRC:sub_dmrrow0
      0,  // VSFRC:sub_dmrrow1
      0,  // VSFRC:sub_dmrrowp0
      0,  // VSFRC:sub_dmrrowp1
      0,  // VSFRC:sub_eq
      0,  // VSFRC:sub_fp0
      0,  // VSFRC:sub_fp1
      0,  // VSFRC:sub_gp8_x0
      0,  // VSFRC:sub_gp8_x1
      0,  // VSFRC:sub_gt
      0,  // VSFRC:sub_lt
      0,  // VSFRC:sub_pair0
      0,  // VSFRC:sub_pair1
      0,  // VSFRC:sub_un
      0,  // VSFRC:sub_vsx0
      0,  // VSFRC:sub_vsx1
      0,  // VSFRC:sub_wacc_hi
      0,  // VSFRC:sub_wacc_lo
      0,  // VSFRC:sub_vsx1_then_sub_64
      0,  // VSFRC:sub_pair1_then_sub_64
      0,  // VSFRC:sub_pair1_then_sub_vsx0
      0,  // VSFRC:sub_pair1_then_sub_vsx1
      0,  // VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSFRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSFRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSFRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSFRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSFRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSFRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSFRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSFRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSFRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSFRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSFRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSFRC:sub_gp8_x1_then_sub_32
    },
    { // G8RC
      2,  // G8RC:sub_32 -> GPRC
      0,  // G8RC:sub_32_hi_phony
      0,  // G8RC:sub_64
      0,  // G8RC:sub_dmr0
      0,  // G8RC:sub_dmr1
      0,  // G8RC:sub_dmrrow0
      0,  // G8RC:sub_dmrrow1
      0,  // G8RC:sub_dmrrowp0
      0,  // G8RC:sub_dmrrowp1
      0,  // G8RC:sub_eq
      0,  // G8RC:sub_fp0
      0,  // G8RC:sub_fp1
      0,  // G8RC:sub_gp8_x0
      0,  // G8RC:sub_gp8_x1
      0,  // G8RC:sub_gt
      0,  // G8RC:sub_lt
      0,  // G8RC:sub_pair0
      0,  // G8RC:sub_pair1
      0,  // G8RC:sub_un
      0,  // G8RC:sub_vsx0
      0,  // G8RC:sub_vsx1
      0,  // G8RC:sub_wacc_hi
      0,  // G8RC:sub_wacc_lo
      0,  // G8RC:sub_vsx1_then_sub_64
      0,  // G8RC:sub_pair1_then_sub_64
      0,  // G8RC:sub_pair1_then_sub_vsx0
      0,  // G8RC:sub_pair1_then_sub_vsx1
      0,  // G8RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // G8RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // G8RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // G8RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC:sub_dmr1_then_sub_dmrrow0
      0,  // G8RC:sub_dmr1_then_sub_dmrrow1
      0,  // G8RC:sub_dmr1_then_sub_dmrrowp0
      0,  // G8RC:sub_dmr1_then_sub_dmrrowp1
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi
      0,  // G8RC:sub_dmr1_then_sub_wacc_lo
      0,  // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC:sub_gp8_x1_then_sub_32
    },
    { // G8RC_NOX0
      3,  // G8RC_NOX0:sub_32 -> GPRC_NOR0
      0,  // G8RC_NOX0:sub_32_hi_phony
      0,  // G8RC_NOX0:sub_64
      0,  // G8RC_NOX0:sub_dmr0
      0,  // G8RC_NOX0:sub_dmr1
      0,  // G8RC_NOX0:sub_dmrrow0
      0,  // G8RC_NOX0:sub_dmrrow1
      0,  // G8RC_NOX0:sub_dmrrowp0
      0,  // G8RC_NOX0:sub_dmrrowp1
      0,  // G8RC_NOX0:sub_eq
      0,  // G8RC_NOX0:sub_fp0
      0,  // G8RC_NOX0:sub_fp1
      0,  // G8RC_NOX0:sub_gp8_x0
      0,  // G8RC_NOX0:sub_gp8_x1
      0,  // G8RC_NOX0:sub_gt
      0,  // G8RC_NOX0:sub_lt
      0,  // G8RC_NOX0:sub_pair0
      0,  // G8RC_NOX0:sub_pair1
      0,  // G8RC_NOX0:sub_un
      0,  // G8RC_NOX0:sub_vsx0
      0,  // G8RC_NOX0:sub_vsx1
      0,  // G8RC_NOX0:sub_wacc_hi
      0,  // G8RC_NOX0:sub_wacc_lo
      0,  // G8RC_NOX0:sub_vsx1_then_sub_64
      0,  // G8RC_NOX0:sub_pair1_then_sub_64
      0,  // G8RC_NOX0:sub_pair1_then_sub_vsx0
      0,  // G8RC_NOX0:sub_pair1_then_sub_vsx1
      0,  // G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
      0,  // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
      0,  // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_NOX0:sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC_and_VSFRC
      0,  // SPILLTOVSRRC_and_VSFRC:sub_32
      0,  // SPILLTOVSRRC_and_VSFRC:sub_32_hi_phony
      0,  // SPILLTOVSRRC_and_VSFRC:sub_64
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_eq
      0,  // SPILLTOVSRRC_and_VSFRC:sub_fp0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_fp1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_gp8_x0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_gt
      0,  // SPILLTOVSRRC_and_VSFRC:sub_lt
      0,  // SPILLTOVSRRC_and_VSFRC:sub_pair0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_pair1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_un
      0,  // SPILLTOVSRRC_and_VSFRC:sub_vsx0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_vsx1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_lo
      0,  // SPILLTOVSRRC_and_VSFRC:sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_64
      0,  // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_lo
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VSFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VSFRC:sub_gp8_x1_then_sub_32
    },
    { // G8RC_and_G8RC_NOX0
      4,  // G8RC_and_G8RC_NOX0:sub_32 -> GPRC_and_GPRC_NOR0
      0,  // G8RC_and_G8RC_NOX0:sub_32_hi_phony
      0,  // G8RC_and_G8RC_NOX0:sub_64
      0,  // G8RC_and_G8RC_NOX0:sub_dmr0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1
      0,  // G8RC_and_G8RC_NOX0:sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_dmrrowp0
      0,  // G8RC_and_G8RC_NOX0:sub_dmrrowp1
      0,  // G8RC_and_G8RC_NOX0:sub_eq
      0,  // G8RC_and_G8RC_NOX0:sub_fp0
      0,  // G8RC_and_G8RC_NOX0:sub_fp1
      0,  // G8RC_and_G8RC_NOX0:sub_gp8_x0
      0,  // G8RC_and_G8RC_NOX0:sub_gp8_x1
      0,  // G8RC_and_G8RC_NOX0:sub_gt
      0,  // G8RC_and_G8RC_NOX0:sub_lt
      0,  // G8RC_and_G8RC_NOX0:sub_pair0
      0,  // G8RC_and_G8RC_NOX0:sub_pair1
      0,  // G8RC_and_G8RC_NOX0:sub_un
      0,  // G8RC_and_G8RC_NOX0:sub_vsx0
      0,  // G8RC_and_G8RC_NOX0:sub_vsx1
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_lo
      0,  // G8RC_and_G8RC_NOX0:sub_vsx1_then_sub_64
      0,  // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_64
      0,  // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx0
      0,  // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1
      0,  // G8RC_and_G8RC_NOX0:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_lo
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8RC_and_G8RC_NOX0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8RC_and_G8RC_NOX0:sub_gp8_x1_then_sub_32
    },
    { // F8RC
      0,  // F8RC:sub_32
      0,  // F8RC:sub_32_hi_phony
      0,  // F8RC:sub_64
      0,  // F8RC:sub_dmr0
      0,  // F8RC:sub_dmr1
      0,  // F8RC:sub_dmrrow0
      0,  // F8RC:sub_dmrrow1
      0,  // F8RC:sub_dmrrowp0
      0,  // F8RC:sub_dmrrowp1
      0,  // F8RC:sub_eq
      0,  // F8RC:sub_fp0
      0,  // F8RC:sub_fp1
      0,  // F8RC:sub_gp8_x0
      0,  // F8RC:sub_gp8_x1
      0,  // F8RC:sub_gt
      0,  // F8RC:sub_lt
      0,  // F8RC:sub_pair0
      0,  // F8RC:sub_pair1
      0,  // F8RC:sub_un
      0,  // F8RC:sub_vsx0
      0,  // F8RC:sub_vsx1
      0,  // F8RC:sub_wacc_hi
      0,  // F8RC:sub_wacc_lo
      0,  // F8RC:sub_vsx1_then_sub_64
      0,  // F8RC:sub_pair1_then_sub_64
      0,  // F8RC:sub_pair1_then_sub_vsx0
      0,  // F8RC:sub_pair1_then_sub_vsx1
      0,  // F8RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // F8RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // F8RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // F8RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // F8RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // F8RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // F8RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // F8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // F8RC:sub_dmr1_then_sub_dmrrow0
      0,  // F8RC:sub_dmr1_then_sub_dmrrow1
      0,  // F8RC:sub_dmr1_then_sub_dmrrowp0
      0,  // F8RC:sub_dmr1_then_sub_dmrrowp1
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi
      0,  // F8RC:sub_dmr1_then_sub_wacc_lo
      0,  // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // F8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // F8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // F8RC:sub_gp8_x1_then_sub_32
    },
    { // SPERC
      2,  // SPERC:sub_32 -> GPRC
      0,  // SPERC:sub_32_hi_phony
      0,  // SPERC:sub_64
      0,  // SPERC:sub_dmr0
      0,  // SPERC:sub_dmr1
      0,  // SPERC:sub_dmrrow0
      0,  // SPERC:sub_dmrrow1
      0,  // SPERC:sub_dmrrowp0
      0,  // SPERC:sub_dmrrowp1
      0,  // SPERC:sub_eq
      0,  // SPERC:sub_fp0
      0,  // SPERC:sub_fp1
      0,  // SPERC:sub_gp8_x0
      0,  // SPERC:sub_gp8_x1
      0,  // SPERC:sub_gt
      0,  // SPERC:sub_lt
      0,  // SPERC:sub_pair0
      0,  // SPERC:sub_pair1
      0,  // SPERC:sub_un
      0,  // SPERC:sub_vsx0
      0,  // SPERC:sub_vsx1
      0,  // SPERC:sub_wacc_hi
      0,  // SPERC:sub_wacc_lo
      0,  // SPERC:sub_vsx1_then_sub_64
      0,  // SPERC:sub_pair1_then_sub_64
      0,  // SPERC:sub_pair1_then_sub_vsx0
      0,  // SPERC:sub_pair1_then_sub_vsx1
      0,  // SPERC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // SPERC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC:sub_wacc_hi_then_sub_dmrrow0
      0,  // SPERC:sub_wacc_hi_then_sub_dmrrow1
      0,  // SPERC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPERC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC:sub_dmr1_then_sub_dmrrow0
      0,  // SPERC:sub_dmr1_then_sub_dmrrow1
      0,  // SPERC:sub_dmr1_then_sub_dmrrowp0
      0,  // SPERC:sub_dmr1_then_sub_dmrrowp1
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi
      0,  // SPERC:sub_dmr1_then_sub_wacc_lo
      0,  // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC:sub_gp8_x1_then_sub_32
    },
    { // VFRC
      0,  // VFRC:sub_32
      0,  // VFRC:sub_32_hi_phony
      0,  // VFRC:sub_64
      0,  // VFRC:sub_dmr0
      0,  // VFRC:sub_dmr1
      0,  // VFRC:sub_dmrrow0
      0,  // VFRC:sub_dmrrow1
      0,  // VFRC:sub_dmrrowp0
      0,  // VFRC:sub_dmrrowp1
      0,  // VFRC:sub_eq
      0,  // VFRC:sub_fp0
      0,  // VFRC:sub_fp1
      0,  // VFRC:sub_gp8_x0
      0,  // VFRC:sub_gp8_x1
      0,  // VFRC:sub_gt
      0,  // VFRC:sub_lt
      0,  // VFRC:sub_pair0
      0,  // VFRC:sub_pair1
      0,  // VFRC:sub_un
      0,  // VFRC:sub_vsx0
      0,  // VFRC:sub_vsx1
      0,  // VFRC:sub_wacc_hi
      0,  // VFRC:sub_wacc_lo
      0,  // VFRC:sub_vsx1_then_sub_64
      0,  // VFRC:sub_pair1_then_sub_64
      0,  // VFRC:sub_pair1_then_sub_vsx0
      0,  // VFRC:sub_pair1_then_sub_vsx1
      0,  // VFRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VFRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VFRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VFRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VFRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VFRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VFRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VFRC:sub_dmr1_then_sub_dmrrow0
      0,  // VFRC:sub_dmr1_then_sub_dmrrow1
      0,  // VFRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VFRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi
      0,  // VFRC:sub_dmr1_then_sub_wacc_lo
      0,  // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VFRC:sub_gp8_x1_then_sub_32
    },
    { // SPERC_with_sub_32_in_GPRC_NOR0
      4,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_32_hi_phony
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_64
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_eq
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_fp0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_fp1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_gt
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_lt
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_un
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPERC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC_and_VFRC
      0,  // SPILLTOVSRRC_and_VFRC:sub_32
      0,  // SPILLTOVSRRC_and_VFRC:sub_32_hi_phony
      0,  // SPILLTOVSRRC_and_VFRC:sub_64
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VFRC:sub_eq
      0,  // SPILLTOVSRRC_and_VFRC:sub_fp0
      0,  // SPILLTOVSRRC_and_VFRC:sub_fp1
      0,  // SPILLTOVSRRC_and_VFRC:sub_gp8_x0
      0,  // SPILLTOVSRRC_and_VFRC:sub_gp8_x1
      0,  // SPILLTOVSRRC_and_VFRC:sub_gt
      0,  // SPILLTOVSRRC_and_VFRC:sub_lt
      0,  // SPILLTOVSRRC_and_VFRC:sub_pair0
      0,  // SPILLTOVSRRC_and_VFRC:sub_pair1
      0,  // SPILLTOVSRRC_and_VFRC:sub_un
      0,  // SPILLTOVSRRC_and_VFRC:sub_vsx0
      0,  // SPILLTOVSRRC_and_VFRC:sub_vsx1
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_lo
      0,  // SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
      0,  // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
      0,  // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
      0,  // SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
    },
    { // SPILLTOVSRRC_and_F4RC
      0,  // SPILLTOVSRRC_and_F4RC:sub_32
      0,  // SPILLTOVSRRC_and_F4RC:sub_32_hi_phony
      0,  // SPILLTOVSRRC_and_F4RC:sub_64
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_F4RC:sub_eq
      0,  // SPILLTOVSRRC_and_F4RC:sub_fp0
      0,  // SPILLTOVSRRC_and_F4RC:sub_fp1
      0,  // SPILLTOVSRRC_and_F4RC:sub_gp8_x0
      0,  // SPILLTOVSRRC_and_F4RC:sub_gp8_x1
      0,  // SPILLTOVSRRC_and_F4RC:sub_gt
      0,  // SPILLTOVSRRC_and_F4RC:sub_lt
      0,  // SPILLTOVSRRC_and_F4RC:sub_pair0
      0,  // SPILLTOVSRRC_and_F4RC:sub_pair1
      0,  // SPILLTOVSRRC_and_F4RC:sub_un
      0,  // SPILLTOVSRRC_and_F4RC:sub_vsx0
      0,  // SPILLTOVSRRC_and_F4RC:sub_vsx1
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_lo
      0,  // SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
      0,  // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
      0,  // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
      0,  // SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
    },
    { // CTRRC8
      0,  // CTRRC8:sub_32
      0,  // CTRRC8:sub_32_hi_phony
      0,  // CTRRC8:sub_64
      0,  // CTRRC8:sub_dmr0
      0,  // CTRRC8:sub_dmr1
      0,  // CTRRC8:sub_dmrrow0
      0,  // CTRRC8:sub_dmrrow1
      0,  // CTRRC8:sub_dmrrowp0
      0,  // CTRRC8:sub_dmrrowp1
      0,  // CTRRC8:sub_eq
      0,  // CTRRC8:sub_fp0
      0,  // CTRRC8:sub_fp1
      0,  // CTRRC8:sub_gp8_x0
      0,  // CTRRC8:sub_gp8_x1
      0,  // CTRRC8:sub_gt
      0,  // CTRRC8:sub_lt
      0,  // CTRRC8:sub_pair0
      0,  // CTRRC8:sub_pair1
      0,  // CTRRC8:sub_un
      0,  // CTRRC8:sub_vsx0
      0,  // CTRRC8:sub_vsx1
      0,  // CTRRC8:sub_wacc_hi
      0,  // CTRRC8:sub_wacc_lo
      0,  // CTRRC8:sub_vsx1_then_sub_64
      0,  // CTRRC8:sub_pair1_then_sub_64
      0,  // CTRRC8:sub_pair1_then_sub_vsx0
      0,  // CTRRC8:sub_pair1_then_sub_vsx1
      0,  // CTRRC8:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // CTRRC8:sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC8:sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC8:sub_wacc_hi_then_sub_dmrrow0
      0,  // CTRRC8:sub_wacc_hi_then_sub_dmrrow1
      0,  // CTRRC8:sub_wacc_hi_then_sub_dmrrowp0
      0,  // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1
      0,  // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC8:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC8:sub_dmr1_then_sub_dmrrow0
      0,  // CTRRC8:sub_dmr1_then_sub_dmrrow1
      0,  // CTRRC8:sub_dmr1_then_sub_dmrrowp0
      0,  // CTRRC8:sub_dmr1_then_sub_dmrrowp1
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_lo
      0,  // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC8:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // CTRRC8:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // CTRRC8:sub_gp8_x1_then_sub_32
    },
    { // LR8RC
      0,  // LR8RC:sub_32
      0,  // LR8RC:sub_32_hi_phony
      0,  // LR8RC:sub_64
      0,  // LR8RC:sub_dmr0
      0,  // LR8RC:sub_dmr1
      0,  // LR8RC:sub_dmrrow0
      0,  // LR8RC:sub_dmrrow1
      0,  // LR8RC:sub_dmrrowp0
      0,  // LR8RC:sub_dmrrowp1
      0,  // LR8RC:sub_eq
      0,  // LR8RC:sub_fp0
      0,  // LR8RC:sub_fp1
      0,  // LR8RC:sub_gp8_x0
      0,  // LR8RC:sub_gp8_x1
      0,  // LR8RC:sub_gt
      0,  // LR8RC:sub_lt
      0,  // LR8RC:sub_pair0
      0,  // LR8RC:sub_pair1
      0,  // LR8RC:sub_un
      0,  // LR8RC:sub_vsx0
      0,  // LR8RC:sub_vsx1
      0,  // LR8RC:sub_wacc_hi
      0,  // LR8RC:sub_wacc_lo
      0,  // LR8RC:sub_vsx1_then_sub_64
      0,  // LR8RC:sub_pair1_then_sub_64
      0,  // LR8RC:sub_pair1_then_sub_vsx0
      0,  // LR8RC:sub_pair1_then_sub_vsx1
      0,  // LR8RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // LR8RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // LR8RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // LR8RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // LR8RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // LR8RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // LR8RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // LR8RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // LR8RC:sub_dmr1_then_sub_dmrrow0
      0,  // LR8RC:sub_dmr1_then_sub_dmrrow1
      0,  // LR8RC:sub_dmr1_then_sub_dmrrowp0
      0,  // LR8RC:sub_dmr1_then_sub_dmrrowp1
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi
      0,  // LR8RC:sub_dmr1_then_sub_wacc_lo
      0,  // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // LR8RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // LR8RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // LR8RC:sub_gp8_x1_then_sub_32
    },
    { // DMRROWRC
      0,  // DMRROWRC:sub_32
      0,  // DMRROWRC:sub_32_hi_phony
      0,  // DMRROWRC:sub_64
      0,  // DMRROWRC:sub_dmr0
      0,  // DMRROWRC:sub_dmr1
      0,  // DMRROWRC:sub_dmrrow0
      0,  // DMRROWRC:sub_dmrrow1
      0,  // DMRROWRC:sub_dmrrowp0
      0,  // DMRROWRC:sub_dmrrowp1
      0,  // DMRROWRC:sub_eq
      0,  // DMRROWRC:sub_fp0
      0,  // DMRROWRC:sub_fp1
      0,  // DMRROWRC:sub_gp8_x0
      0,  // DMRROWRC:sub_gp8_x1
      0,  // DMRROWRC:sub_gt
      0,  // DMRROWRC:sub_lt
      0,  // DMRROWRC:sub_pair0
      0,  // DMRROWRC:sub_pair1
      0,  // DMRROWRC:sub_un
      0,  // DMRROWRC:sub_vsx0
      0,  // DMRROWRC:sub_vsx1
      0,  // DMRROWRC:sub_wacc_hi
      0,  // DMRROWRC:sub_wacc_lo
      0,  // DMRROWRC:sub_vsx1_then_sub_64
      0,  // DMRROWRC:sub_pair1_then_sub_64
      0,  // DMRROWRC:sub_pair1_then_sub_vsx0
      0,  // DMRROWRC:sub_pair1_then_sub_vsx1
      0,  // DMRROWRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // DMRROWRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWRC:sub_dmr1_then_sub_dmrrow0
      0,  // DMRROWRC:sub_dmr1_then_sub_dmrrow1
      0,  // DMRROWRC:sub_dmr1_then_sub_dmrrowp0
      0,  // DMRROWRC:sub_dmr1_then_sub_dmrrowp1
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_lo
      0,  // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWRC:sub_gp8_x1_then_sub_32
    },
    { // VSRC
      0,  // VSRC:sub_32
      0,  // VSRC:sub_32_hi_phony
      1,  // VSRC:sub_64 -> VSSRC
      0,  // VSRC:sub_dmr0
      0,  // VSRC:sub_dmr1
      0,  // VSRC:sub_dmrrow0
      0,  // VSRC:sub_dmrrow1
      0,  // VSRC:sub_dmrrowp0
      0,  // VSRC:sub_dmrrowp1
      0,  // VSRC:sub_eq
      0,  // VSRC:sub_fp0
      0,  // VSRC:sub_fp1
      0,  // VSRC:sub_gp8_x0
      0,  // VSRC:sub_gp8_x1
      0,  // VSRC:sub_gt
      0,  // VSRC:sub_lt
      0,  // VSRC:sub_pair0
      0,  // VSRC:sub_pair1
      0,  // VSRC:sub_un
      0,  // VSRC:sub_vsx0
      0,  // VSRC:sub_vsx1
      0,  // VSRC:sub_wacc_hi
      0,  // VSRC:sub_wacc_lo
      0,  // VSRC:sub_vsx1_then_sub_64
      0,  // VSRC:sub_pair1_then_sub_64
      0,  // VSRC:sub_pair1_then_sub_vsx0
      0,  // VSRC:sub_pair1_then_sub_vsx1
      0,  // VSRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC:sub_gp8_x1_then_sub_32
    },
    { // VSRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      17, // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_un
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // VRRC
      0,  // VRRC:sub_32
      0,  // VRRC:sub_32_hi_phony
      21, // VRRC:sub_64 -> VFRC
      0,  // VRRC:sub_dmr0
      0,  // VRRC:sub_dmr1
      0,  // VRRC:sub_dmrrow0
      0,  // VRRC:sub_dmrrow1
      0,  // VRRC:sub_dmrrowp0
      0,  // VRRC:sub_dmrrowp1
      0,  // VRRC:sub_eq
      0,  // VRRC:sub_fp0
      0,  // VRRC:sub_fp1
      0,  // VRRC:sub_gp8_x0
      0,  // VRRC:sub_gp8_x1
      0,  // VRRC:sub_gt
      0,  // VRRC:sub_lt
      0,  // VRRC:sub_pair0
      0,  // VRRC:sub_pair1
      0,  // VRRC:sub_un
      0,  // VRRC:sub_vsx0
      0,  // VRRC:sub_vsx1
      0,  // VRRC:sub_wacc_hi
      0,  // VRRC:sub_wacc_lo
      0,  // VRRC:sub_vsx1_then_sub_64
      0,  // VRRC:sub_pair1_then_sub_64
      0,  // VRRC:sub_pair1_then_sub_vsx0
      0,  // VRRC:sub_pair1_then_sub_vsx1
      0,  // VRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC:sub_dmr1_then_sub_dmrrow0
      0,  // VRRC:sub_dmr1_then_sub_dmrrow1
      0,  // VRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi
      0,  // VRRC:sub_dmr1_then_sub_wacc_lo
      0,  // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC:sub_gp8_x1_then_sub_32
    },
    { // VSLRC
      0,  // VSLRC:sub_32
      0,  // VSLRC:sub_32_hi_phony
      6,  // VSLRC:sub_64 -> F4RC
      0,  // VSLRC:sub_dmr0
      0,  // VSLRC:sub_dmr1
      0,  // VSLRC:sub_dmrrow0
      0,  // VSLRC:sub_dmrrow1
      0,  // VSLRC:sub_dmrrowp0
      0,  // VSLRC:sub_dmrrowp1
      0,  // VSLRC:sub_eq
      0,  // VSLRC:sub_fp0
      0,  // VSLRC:sub_fp1
      0,  // VSLRC:sub_gp8_x0
      0,  // VSLRC:sub_gp8_x1
      0,  // VSLRC:sub_gt
      0,  // VSLRC:sub_lt
      0,  // VSLRC:sub_pair0
      0,  // VSLRC:sub_pair1
      0,  // VSLRC:sub_un
      0,  // VSLRC:sub_vsx0
      0,  // VSLRC:sub_vsx1
      0,  // VSLRC:sub_wacc_hi
      0,  // VSLRC:sub_wacc_lo
      0,  // VSLRC:sub_vsx1_then_sub_64
      0,  // VSLRC:sub_pair1_then_sub_64
      0,  // VSLRC:sub_pair1_then_sub_vsx0
      0,  // VSLRC:sub_pair1_then_sub_vsx1
      0,  // VSLRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSLRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSLRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSLRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSLRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSLRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSLRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSLRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSLRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC:sub_gp8_x1_then_sub_32
    },
    { // VRRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      23, // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VFRC
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_un
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VRRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // FpRC
      0,  // FpRC:sub_32
      0,  // FpRC:sub_32_hi_phony
      0,  // FpRC:sub_64
      0,  // FpRC:sub_dmr0
      0,  // FpRC:sub_dmr1
      0,  // FpRC:sub_dmrrow0
      0,  // FpRC:sub_dmrrow1
      0,  // FpRC:sub_dmrrowp0
      0,  // FpRC:sub_dmrrowp1
      0,  // FpRC:sub_eq
      19, // FpRC:sub_fp0 -> F8RC
      19, // FpRC:sub_fp1 -> F8RC
      0,  // FpRC:sub_gp8_x0
      0,  // FpRC:sub_gp8_x1
      0,  // FpRC:sub_gt
      0,  // FpRC:sub_lt
      0,  // FpRC:sub_pair0
      0,  // FpRC:sub_pair1
      0,  // FpRC:sub_un
      0,  // FpRC:sub_vsx0
      0,  // FpRC:sub_vsx1
      0,  // FpRC:sub_wacc_hi
      0,  // FpRC:sub_wacc_lo
      0,  // FpRC:sub_vsx1_then_sub_64
      0,  // FpRC:sub_pair1_then_sub_64
      0,  // FpRC:sub_pair1_then_sub_vsx0
      0,  // FpRC:sub_pair1_then_sub_vsx1
      0,  // FpRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // FpRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // FpRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // FpRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // FpRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // FpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC:sub_dmr1_then_sub_dmrrow0
      0,  // FpRC:sub_dmr1_then_sub_dmrrow1
      0,  // FpRC:sub_dmr1_then_sub_dmrrowp0
      0,  // FpRC:sub_dmr1_then_sub_dmrrowp1
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi
      0,  // FpRC:sub_dmr1_then_sub_wacc_lo
      0,  // FpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC:sub_gp8_x1_then_sub_32
    },
    { // G8pRC
      2,  // G8pRC:sub_32 -> GPRC
      0,  // G8pRC:sub_32_hi_phony
      0,  // G8pRC:sub_64
      0,  // G8pRC:sub_dmr0
      0,  // G8pRC:sub_dmr1
      0,  // G8pRC:sub_dmrrow0
      0,  // G8pRC:sub_dmrrow1
      0,  // G8pRC:sub_dmrrowp0
      0,  // G8pRC:sub_dmrrowp1
      0,  // G8pRC:sub_eq
      0,  // G8pRC:sub_fp0
      0,  // G8pRC:sub_fp1
      15, // G8pRC:sub_gp8_x0 -> G8RC
      18, // G8pRC:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
      0,  // G8pRC:sub_gt
      0,  // G8pRC:sub_lt
      0,  // G8pRC:sub_pair0
      0,  // G8pRC:sub_pair1
      0,  // G8pRC:sub_un
      0,  // G8pRC:sub_vsx0
      0,  // G8pRC:sub_vsx1
      0,  // G8pRC:sub_wacc_hi
      0,  // G8pRC:sub_wacc_lo
      0,  // G8pRC:sub_vsx1_then_sub_64
      0,  // G8pRC:sub_pair1_then_sub_64
      0,  // G8pRC:sub_pair1_then_sub_vsx0
      0,  // G8pRC:sub_pair1_then_sub_vsx1
      0,  // G8pRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // G8pRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8pRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // G8pRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // G8pRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8pRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8pRC:sub_dmr1_then_sub_dmrrow0
      0,  // G8pRC:sub_dmr1_then_sub_dmrrow1
      0,  // G8pRC:sub_dmr1_then_sub_dmrrowp0
      0,  // G8pRC:sub_dmr1_then_sub_dmrrowp1
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi
      0,  // G8pRC:sub_dmr1_then_sub_wacc_lo
      0,  // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      4,  // G8pRC:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
    },
    { // G8pRC_with_sub_32_in_GPRC_NOR0
      4,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32 -> GPRC_and_GPRC_NOR0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_32_hi_phony
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_64
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_eq
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_fp0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_fp1
      18, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x0 -> G8RC_and_G8RC_NOX0
      18, // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1 -> G8RC_and_G8RC_NOX0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gt
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_lt
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_un
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_lo
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_vsx1_then_sub_64
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_64
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_lo
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      4,  // G8pRC_with_sub_32_in_GPRC_NOR0:sub_gp8_x1_then_sub_32 -> GPRC_and_GPRC_NOR0
    },
    { // VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      24, // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_un
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSLRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // FpRC_with_sub_fp0_in_SPILLTOVSRRC
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_32
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_32_hi_phony
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_64
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_eq
      24, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_fp0 -> SPILLTOVSRRC_and_F4RC
      24, // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_fp1 -> SPILLTOVSRRC_and_F4RC
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gt
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_lt
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_un
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_lo
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_vsx1_then_sub_64
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_64
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // FpRC_with_sub_fp0_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // DMRROWpRC
      0,  // DMRROWpRC:sub_32
      0,  // DMRROWpRC:sub_32_hi_phony
      0,  // DMRROWpRC:sub_64
      0,  // DMRROWpRC:sub_dmr0
      0,  // DMRROWpRC:sub_dmr1
      27, // DMRROWpRC:sub_dmrrow0 -> DMRROWRC
      27, // DMRROWpRC:sub_dmrrow1 -> DMRROWRC
      0,  // DMRROWpRC:sub_dmrrowp0
      0,  // DMRROWpRC:sub_dmrrowp1
      0,  // DMRROWpRC:sub_eq
      0,  // DMRROWpRC:sub_fp0
      0,  // DMRROWpRC:sub_fp1
      0,  // DMRROWpRC:sub_gp8_x0
      0,  // DMRROWpRC:sub_gp8_x1
      0,  // DMRROWpRC:sub_gt
      0,  // DMRROWpRC:sub_lt
      0,  // DMRROWpRC:sub_pair0
      0,  // DMRROWpRC:sub_pair1
      0,  // DMRROWpRC:sub_un
      0,  // DMRROWpRC:sub_vsx0
      0,  // DMRROWpRC:sub_vsx1
      0,  // DMRROWpRC:sub_wacc_hi
      0,  // DMRROWpRC:sub_wacc_lo
      0,  // DMRROWpRC:sub_vsx1_then_sub_64
      0,  // DMRROWpRC:sub_pair1_then_sub_64
      0,  // DMRROWpRC:sub_pair1_then_sub_vsx0
      0,  // DMRROWpRC:sub_pair1_then_sub_vsx1
      0,  // DMRROWpRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_dmr1_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_dmr1_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_dmr1_then_sub_dmrrowp0
      0,  // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_lo
      0,  // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRROWpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRROWpRC:sub_gp8_x1_then_sub_32
    },
    { // VSRpRC
      0,  // VSRpRC:sub_32
      0,  // VSRpRC:sub_32_hi_phony
      14, // VSRpRC:sub_64 -> VSFRC
      0,  // VSRpRC:sub_dmr0
      0,  // VSRpRC:sub_dmr1
      0,  // VSRpRC:sub_dmrrow0
      0,  // VSRpRC:sub_dmrrow1
      0,  // VSRpRC:sub_dmrrowp0
      0,  // VSRpRC:sub_dmrrowp1
      0,  // VSRpRC:sub_eq
      0,  // VSRpRC:sub_fp0
      0,  // VSRpRC:sub_fp1
      0,  // VSRpRC:sub_gp8_x0
      0,  // VSRpRC:sub_gp8_x1
      0,  // VSRpRC:sub_gt
      0,  // VSRpRC:sub_lt
      0,  // VSRpRC:sub_pair0
      0,  // VSRpRC:sub_pair1
      0,  // VSRpRC:sub_un
      28, // VSRpRC:sub_vsx0 -> VSRC
      28, // VSRpRC:sub_vsx1 -> VSRC
      0,  // VSRpRC:sub_wacc_hi
      0,  // VSRpRC:sub_wacc_lo
      14, // VSRpRC:sub_vsx1_then_sub_64 -> VSFRC
      0,  // VSRpRC:sub_pair1_then_sub_64
      0,  // VSRpRC:sub_pair1_then_sub_vsx0
      0,  // VSRpRC:sub_pair1_then_sub_vsx1
      0,  // VSRpRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRpRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRpRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRpRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRpRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC:sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      17, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_VSFRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_un
      29, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSRC_with_sub_64_in_SPILLTOVSRRC
      29, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      17, // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VSFRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_F4RC
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_32
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_32_hi_phony
      19, // VSRpRC_with_sub_64_in_F4RC:sub_64 -> F8RC
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_eq
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_fp0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_fp1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_gt
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_lt
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_pair0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_pair1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_un
      31, // VSRpRC_with_sub_64_in_F4RC:sub_vsx0 -> VSLRC
      31, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1 -> VSLRC
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_lo
      19, // VSRpRC_with_sub_64_in_F4RC:sub_vsx1_then_sub_64 -> F8RC
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_F4RC:sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_VFRC
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_32
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_32_hi_phony
      21, // VSRpRC_with_sub_64_in_VFRC:sub_64 -> VFRC
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_eq
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_fp0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_fp1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_gt
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_lt
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_pair0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_pair1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_un
      30, // VSRpRC_with_sub_64_in_VFRC:sub_vsx0 -> VRRC
      30, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1 -> VRRC
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_lo
      21, // VSRpRC_with_sub_64_in_VFRC:sub_vsx1_then_sub_64 -> VFRC
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_VFRC:sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_32_hi_phony
      23, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_64 -> SPILLTOVSRRC_and_VFRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_eq
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_fp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_fp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gt
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_lt
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_un
      32, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx0 -> VRRC_with_sub_64_in_SPILLTOVSRRC
      32, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1 -> VRRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_lo
      23, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_VFRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC:sub_gp8_x1_then_sub_32
    },
    { // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_32_hi_phony
      24, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_eq
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_fp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_fp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gt
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_lt
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_un
      36, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_lo
      24, // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_pair1_then_sub_vsx1_then_sub_64
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_lo
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC:sub_gp8_x1_then_sub_32
    },
    { // ACCRC
      0,  // ACCRC:sub_32
      0,  // ACCRC:sub_32_hi_phony
      19, // ACCRC:sub_64 -> F8RC
      0,  // ACCRC:sub_dmr0
      0,  // ACCRC:sub_dmr1
      0,  // ACCRC:sub_dmrrow0
      0,  // ACCRC:sub_dmrrow1
      0,  // ACCRC:sub_dmrrowp0
      0,  // ACCRC:sub_dmrrowp1
      0,  // ACCRC:sub_eq
      0,  // ACCRC:sub_fp0
      0,  // ACCRC:sub_fp1
      0,  // ACCRC:sub_gp8_x0
      0,  // ACCRC:sub_gp8_x1
      0,  // ACCRC:sub_gt
      0,  // ACCRC:sub_lt
      41, // ACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
      41, // ACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
      0,  // ACCRC:sub_un
      31, // ACCRC:sub_vsx0 -> VSLRC
      31, // ACCRC:sub_vsx1 -> VSLRC
      0,  // ACCRC:sub_wacc_hi
      0,  // ACCRC:sub_wacc_lo
      19, // ACCRC:sub_vsx1_then_sub_64 -> F8RC
      19, // ACCRC:sub_pair1_then_sub_64 -> F8RC
      31, // ACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
      31, // ACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
      19, // ACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
      0,  // ACCRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // ACCRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // ACCRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // ACCRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC:sub_dmr1_then_sub_dmrrow0
      0,  // ACCRC:sub_dmr1_then_sub_dmrrow1
      0,  // ACCRC:sub_dmr1_then_sub_dmrrowp0
      0,  // ACCRC:sub_dmr1_then_sub_dmrrowp1
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi
      0,  // ACCRC:sub_dmr1_then_sub_wacc_lo
      0,  // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC:sub_gp8_x1_then_sub_32
    },
    { // UACCRC
      0,  // UACCRC:sub_32
      0,  // UACCRC:sub_32_hi_phony
      19, // UACCRC:sub_64 -> F8RC
      0,  // UACCRC:sub_dmr0
      0,  // UACCRC:sub_dmr1
      0,  // UACCRC:sub_dmrrow0
      0,  // UACCRC:sub_dmrrow1
      0,  // UACCRC:sub_dmrrowp0
      0,  // UACCRC:sub_dmrrowp1
      0,  // UACCRC:sub_eq
      0,  // UACCRC:sub_fp0
      0,  // UACCRC:sub_fp1
      0,  // UACCRC:sub_gp8_x0
      0,  // UACCRC:sub_gp8_x1
      0,  // UACCRC:sub_gt
      0,  // UACCRC:sub_lt
      41, // UACCRC:sub_pair0 -> VSRpRC_with_sub_64_in_F4RC
      41, // UACCRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
      0,  // UACCRC:sub_un
      31, // UACCRC:sub_vsx0 -> VSLRC
      31, // UACCRC:sub_vsx1 -> VSLRC
      0,  // UACCRC:sub_wacc_hi
      0,  // UACCRC:sub_wacc_lo
      19, // UACCRC:sub_vsx1_then_sub_64 -> F8RC
      19, // UACCRC:sub_pair1_then_sub_64 -> F8RC
      31, // UACCRC:sub_pair1_then_sub_vsx0 -> VSLRC
      31, // UACCRC:sub_pair1_then_sub_vsx1 -> VSLRC
      19, // UACCRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
      0,  // UACCRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // UACCRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // UACCRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // UACCRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC:sub_dmr1_then_sub_dmrrow0
      0,  // UACCRC:sub_dmr1_then_sub_dmrrow1
      0,  // UACCRC:sub_dmr1_then_sub_dmrrowp0
      0,  // UACCRC:sub_dmr1_then_sub_dmrrowp1
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi
      0,  // UACCRC:sub_dmr1_then_sub_wacc_lo
      0,  // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC:sub_gp8_x1_then_sub_32
    },
    { // WACCRC
      0,  // WACCRC:sub_32
      0,  // WACCRC:sub_32_hi_phony
      0,  // WACCRC:sub_64
      0,  // WACCRC:sub_dmr0
      0,  // WACCRC:sub_dmr1
      27, // WACCRC:sub_dmrrow0 -> DMRROWRC
      27, // WACCRC:sub_dmrrow1 -> DMRROWRC
      38, // WACCRC:sub_dmrrowp0 -> DMRROWpRC
      38, // WACCRC:sub_dmrrowp1 -> DMRROWpRC
      0,  // WACCRC:sub_eq
      0,  // WACCRC:sub_fp0
      0,  // WACCRC:sub_fp1
      0,  // WACCRC:sub_gp8_x0
      0,  // WACCRC:sub_gp8_x1
      0,  // WACCRC:sub_gt
      0,  // WACCRC:sub_lt
      0,  // WACCRC:sub_pair0
      0,  // WACCRC:sub_pair1
      0,  // WACCRC:sub_un
      0,  // WACCRC:sub_vsx0
      0,  // WACCRC:sub_vsx1
      0,  // WACCRC:sub_wacc_hi
      0,  // WACCRC:sub_wacc_lo
      0,  // WACCRC:sub_vsx1_then_sub_64
      0,  // WACCRC:sub_pair1_then_sub_64
      0,  // WACCRC:sub_pair1_then_sub_vsx0
      0,  // WACCRC:sub_pair1_then_sub_vsx1
      0,  // WACCRC:sub_pair1_then_sub_vsx1_then_sub_64
      27, // WACCRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // WACCRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      0,  // WACCRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // WACCRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // WACCRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // WACCRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // WACCRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // WACCRC:sub_dmr1_then_sub_dmrrow0
      0,  // WACCRC:sub_dmr1_then_sub_dmrrow1
      0,  // WACCRC:sub_dmr1_then_sub_dmrrowp0
      0,  // WACCRC:sub_dmr1_then_sub_dmrrowp1
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi
      0,  // WACCRC:sub_dmr1_then_sub_wacc_lo
      0,  // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // WACCRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // WACCRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // WACCRC:sub_gp8_x1_then_sub_32
    },
    { // WACC_HIRC
      0,  // WACC_HIRC:sub_32
      0,  // WACC_HIRC:sub_32_hi_phony
      0,  // WACC_HIRC:sub_64
      0,  // WACC_HIRC:sub_dmr0
      0,  // WACC_HIRC:sub_dmr1
      27, // WACC_HIRC:sub_dmrrow0 -> DMRROWRC
      27, // WACC_HIRC:sub_dmrrow1 -> DMRROWRC
      38, // WACC_HIRC:sub_dmrrowp0 -> DMRROWpRC
      38, // WACC_HIRC:sub_dmrrowp1 -> DMRROWpRC
      0,  // WACC_HIRC:sub_eq
      0,  // WACC_HIRC:sub_fp0
      0,  // WACC_HIRC:sub_fp1
      0,  // WACC_HIRC:sub_gp8_x0
      0,  // WACC_HIRC:sub_gp8_x1
      0,  // WACC_HIRC:sub_gt
      0,  // WACC_HIRC:sub_lt
      0,  // WACC_HIRC:sub_pair0
      0,  // WACC_HIRC:sub_pair1
      0,  // WACC_HIRC:sub_un
      0,  // WACC_HIRC:sub_vsx0
      0,  // WACC_HIRC:sub_vsx1
      0,  // WACC_HIRC:sub_wacc_hi
      0,  // WACC_HIRC:sub_wacc_lo
      0,  // WACC_HIRC:sub_vsx1_then_sub_64
      0,  // WACC_HIRC:sub_pair1_then_sub_64
      0,  // WACC_HIRC:sub_pair1_then_sub_vsx0
      0,  // WACC_HIRC:sub_pair1_then_sub_vsx1
      0,  // WACC_HIRC:sub_pair1_then_sub_vsx1_then_sub_64
      27, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // WACC_HIRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      0,  // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // WACC_HIRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // WACC_HIRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // WACC_HIRC:sub_dmr1_then_sub_dmrrow0
      0,  // WACC_HIRC:sub_dmr1_then_sub_dmrrow1
      0,  // WACC_HIRC:sub_dmr1_then_sub_dmrrowp0
      0,  // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_lo
      0,  // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // WACC_HIRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // WACC_HIRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // WACC_HIRC:sub_gp8_x1_then_sub_32
    },
    { // ACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      24, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
      44, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      41, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
      36, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      24, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      19, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
      31, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
      31, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
      19, // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // UACCRC_with_sub_64_in_SPILLTOVSRRC
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      24, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_lt
      44, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      41, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_F4RC
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_un
      36, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      24, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      19, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> F8RC
      31, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC
      31, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC
      19, // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> F8RC
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      24, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
      44, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      44, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
      36, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      24, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      24, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      36, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      24, // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_32_hi_phony
      24, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_eq
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_fp1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gt
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_lt
      44, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair0 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      44, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1 -> VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_un
      36, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_lo
      24, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      24, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      36, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx0 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      36, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1 -> VSLRC_with_sub_64_in_SPILLTOVSRRC
      24, // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_pair1_then_sub_vsx1_then_sub_64 -> SPILLTOVSRRC_and_F4RC
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_lo
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC:sub_gp8_x1_then_sub_32
    },
    { // DMRRC
      0,  // DMRRC:sub_32
      0,  // DMRRC:sub_32_hi_phony
      0,  // DMRRC:sub_64
      0,  // DMRRC:sub_dmr0
      0,  // DMRRC:sub_dmr1
      27, // DMRRC:sub_dmrrow0 -> DMRROWRC
      27, // DMRRC:sub_dmrrow1 -> DMRROWRC
      38, // DMRRC:sub_dmrrowp0 -> DMRROWpRC
      38, // DMRRC:sub_dmrrowp1 -> DMRROWpRC
      0,  // DMRRC:sub_eq
      0,  // DMRRC:sub_fp0
      0,  // DMRRC:sub_fp1
      0,  // DMRRC:sub_gp8_x0
      0,  // DMRRC:sub_gp8_x1
      0,  // DMRRC:sub_gt
      0,  // DMRRC:sub_lt
      0,  // DMRRC:sub_pair0
      0,  // DMRRC:sub_pair1
      0,  // DMRRC:sub_un
      0,  // DMRRC:sub_vsx0
      0,  // DMRRC:sub_vsx1
      48, // DMRRC:sub_wacc_hi -> WACC_HIRC
      47, // DMRRC:sub_wacc_lo -> WACCRC
      0,  // DMRRC:sub_vsx1_then_sub_64
      0,  // DMRRC:sub_pair1_then_sub_64
      0,  // DMRRC:sub_pair1_then_sub_vsx0
      0,  // DMRRC:sub_pair1_then_sub_vsx1
      0,  // DMRRC:sub_pair1_then_sub_vsx1_then_sub_64
      27, // DMRRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      27, // DMRRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
      38, // DMRRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
      38, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
      27, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      0,  // DMRRC:sub_dmr1_then_sub_dmrrow0
      0,  // DMRRC:sub_dmr1_then_sub_dmrrow1
      0,  // DMRRC:sub_dmr1_then_sub_dmrrowp0
      0,  // DMRRC:sub_dmr1_then_sub_dmrrowp1
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi
      0,  // DMRRC:sub_dmr1_then_sub_wacc_lo
      0,  // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0
      0,  // DMRRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1
      0,  // DMRRC:sub_gp8_x1_then_sub_32
    },
    { // DMRpRC
      0,  // DMRpRC:sub_32
      0,  // DMRpRC:sub_32_hi_phony
      0,  // DMRpRC:sub_64
      53, // DMRpRC:sub_dmr0 -> DMRRC
      53, // DMRpRC:sub_dmr1 -> DMRRC
      27, // DMRpRC:sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_dmrrow1 -> DMRROWRC
      38, // DMRpRC:sub_dmrrowp0 -> DMRROWpRC
      38, // DMRpRC:sub_dmrrowp1 -> DMRROWpRC
      0,  // DMRpRC:sub_eq
      0,  // DMRpRC:sub_fp0
      0,  // DMRpRC:sub_fp1
      0,  // DMRpRC:sub_gp8_x0
      0,  // DMRpRC:sub_gp8_x1
      0,  // DMRpRC:sub_gt
      0,  // DMRpRC:sub_lt
      0,  // DMRpRC:sub_pair0
      0,  // DMRpRC:sub_pair1
      0,  // DMRpRC:sub_un
      0,  // DMRpRC:sub_vsx0
      0,  // DMRpRC:sub_vsx1
      48, // DMRpRC:sub_wacc_hi -> WACC_HIRC
      47, // DMRpRC:sub_wacc_lo -> WACCRC
      0,  // DMRpRC:sub_vsx1_then_sub_64
      0,  // DMRpRC:sub_pair1_then_sub_64
      0,  // DMRpRC:sub_pair1_then_sub_vsx0
      0,  // DMRpRC:sub_pair1_then_sub_vsx1
      0,  // DMRpRC:sub_pair1_then_sub_vsx1_then_sub_64
      27, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      27, // DMRpRC:sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
      38, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
      38, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
      27, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      27, // DMRpRC:sub_dmr1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_dmr1_then_sub_dmrrow1 -> DMRROWRC
      38, // DMRpRC:sub_dmr1_then_sub_dmrrowp0 -> DMRROWpRC
      38, // DMRpRC:sub_dmr1_then_sub_dmrrowp1 -> DMRROWpRC
      48, // DMRpRC:sub_dmr1_then_sub_wacc_hi -> WACC_HIRC
      47, // DMRpRC:sub_dmr1_then_sub_wacc_lo -> WACCRC
      27, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      27, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1 -> DMRROWRC
      38, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0 -> DMRROWpRC
      38, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1 -> DMRROWpRC
      27, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0 -> DMRROWRC
      27, // DMRpRC:sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1 -> DMRROWRC
      0,  // DMRpRC:sub_gp8_x1_then_sub_32
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 51 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &PPCGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 64},    // VSSRC
    {1, 34},    // GPRC
    {1, 34},    // GPRC_NOR0
    {1, 33},    // GPRC_and_GPRC_NOR0
    {1, 32},    // CRBITRC
    {1, 32},    // F4RC
    {0, 0},   // GPRC32
    {4, 32},    // CRRC
    {1, 1},   // CARRYRC
    {0, 0},   // CTRRC
    {0, 0},   // LRRC
    {1, 1},   // VRSAVERC
    {1, 68},    // SPILLTOVSRRC
    {1, 64},    // VSFRC
    {1, 34},    // G8RC
    {1, 34},    // G8RC_NOX0
    {1, 34},    // SPILLTOVSRRC_and_VSFRC
    {1, 33},    // G8RC_and_G8RC_NOX0
    {1, 32},    // F8RC
    {1, 32},    // SPERC
    {1, 32},    // VFRC
    {1, 31},    // SPERC_with_sub_32_in_GPRC_NOR0
    {1, 20},    // SPILLTOVSRRC_and_VFRC
    {1, 14},    // SPILLTOVSRRC_and_F4RC
    {0, 0},   // CTRRC8
    {0, 0},   // LR8RC
    {1, 64},    // DMRROWRC
    {1, 64},    // VSRC
    {1, 34},    // VSRC_with_sub_64_in_SPILLTOVSRRC
    {1, 32},    // VRRC
    {1, 32},    // VSLRC
    {1, 20},    // VRRC_with_sub_64_in_SPILLTOVSRRC
    {2, 32},    // FpRC
    {2, 32},    // G8pRC
    {2, 30},    // G8pRC_with_sub_32_in_GPRC_NOR0
    {1, 14},    // VSLRC_with_sub_64_in_SPILLTOVSRRC
    {2, 14},    // FpRC_with_sub_fp0_in_SPILLTOVSRRC
    {2, 64},    // DMRROWpRC
    {2, 64},    // VSRpRC
    {2, 34},    // VSRpRC_with_sub_64_in_SPILLTOVSRRC
    {2, 32},    // VSRpRC_with_sub_64_in_F4RC
    {2, 32},    // VSRpRC_with_sub_64_in_VFRC
    {2, 20},    // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC
    {2, 14},    // VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC
    {4, 32},    // ACCRC
    {4, 32},    // UACCRC
    {4, 32},    // WACCRC
    {4, 32},    // WACC_HIRC
    {4, 16},    // ACCRC_with_sub_64_in_SPILLTOVSRRC
    {4, 16},    // UACCRC_with_sub_64_in_SPILLTOVSRRC
    {4, 12},    // ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
    {4, 12},    // UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC
    {8, 64},    // DMRRC
    {16, 64},   // DMRpRC
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned PPCGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 265 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned PPCGenRegisterInfo::getNumRegPressureSets() const {
  return 20;
}

// Get the name of this register unit pressure set.
const char *PPCGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "CARRYRC",
    "VRSAVERC",
    "SPILLTOVSRRC_and_F4RC",
    "SPILLTOVSRRC_and_VFRC",
    "CRBITRC",
    "F4RC",
    "VFRC",
    "WACCRC",
    "WACC_HIRC",
    "GPRC",
    "SPILLTOVSRRC_and_VSFRC",
    "SPILLTOVSRRC_and_VSFRC_with_VFRC",
    "F4RC_with_SPILLTOVSRRC_and_VSFRC",
    "VSSRC",
    "DMRROWRC",
    "SPILLTOVSRRC",
    "SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC",
    "SPILLTOVSRRC_with_VFRC",
    "F4RC_with_SPILLTOVSRRC",
    "VSSRC_with_SPILLTOVSRRC",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned PPCGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,    // 0: CARRYRC
    1,    // 1: VRSAVERC
    16,   // 2: SPILLTOVSRRC_and_F4RC
    20,   // 3: SPILLTOVSRRC_and_VFRC
    32,   // 4: CRBITRC
    32,   // 5: F4RC
    32,   // 6: VFRC
    32,   // 7: WACCRC
    32,   // 8: WACC_HIRC
    35,   // 9: GPRC
    36,   // 10: SPILLTOVSRRC_and_VSFRC
    46,   // 11: SPILLTOVSRRC_and_VSFRC_with_VFRC
    52,   // 12: F4RC_with_SPILLTOVSRRC_and_VSFRC
    64,   // 13: VSSRC
    64,   // 14: DMRROWRC
    69,   // 15: SPILLTOVSRRC
    70,   // 16: SPILLTOVSRRC_with_SPILLTOVSRRC_and_F4RC
    80,   // 17: SPILLTOVSRRC_with_VFRC
    86,   // 18: F4RC_with_SPILLTOVSRRC
    98,   // 19: VSSRC_with_SPILLTOVSRRC
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 0, -1,
  /* 2 */ 1, -1,
  /* 4 */ 4, -1,
  /* 6 */ 7, 14, -1,
  /* 9 */ 8, 14, -1,
  /* 12 */ 9, 15, -1,
  /* 15 */ 13, 19, -1,
  /* 18 */ 6, 11, 13, 17, 19, -1,
  /* 24 */ 5, 12, 13, 18, 19, -1,
  /* 30 */ 2, 5, 10, 12, 13, 16, 18, 19, -1,
  /* 39 */ 9, 15, 16, 17, 18, 19, -1,
  /* 46 */ 2, 5, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
  /* 58 */ 3, 6, 10, 11, 12, 13, 15, 16, 17, 18, 19, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *PPCGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    15,39,12,39,4,24,1,4,0,1,1,2,40,15,39,12,48,39,24,39,18,39,58,46,1,1,7,15,48,18,24,58,24,39,39,46,46,7,15,48,24,18,58,46,24,24,6,9,30,30,46,46,7,7,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *PPCGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 265 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    39,0,1,39,1,1,1,2,12,46,46,46,46,46,46,46,46,46,46,46,46,46,46,30,30,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,24,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,6,6,6,6,9,9,9,9,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,39,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,58,18,18,18,18,18,18,18,18,18,18,18,18,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc PPCRegDesc[];
extern const int16_t PPCRegDiffLists[];
extern const LaneBitmask PPCLaneMaskLists[];
extern const char PPCRegStrings[];
extern const char PPCRegClassStrings[];
extern const MCPhysReg PPCRegUnitRoots[][2];
extern const uint16_t PPCSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[];
extern const uint16_t PPCRegEncodingTable[];
// PPC Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0Dwarf2L[];
extern const unsigned PPCDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1Dwarf2L[];
extern const unsigned PPCDwarfFlavour1Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0Dwarf2L[];
extern const unsigned PPCEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1Dwarf2L[];
extern const unsigned PPCEHFlavour1Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour0L2Dwarf[];
extern const unsigned PPCDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCDwarfFlavour1L2Dwarf[];
extern const unsigned PPCDwarfFlavour1L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour0L2Dwarf[];
extern const unsigned PPCEHFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair PPCEHFlavour1L2Dwarf[];
extern const unsigned PPCEHFlavour1L2DwarfSize;

PPCGenRegisterInfo::
PPCGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&PPCRegInfoDesc, RegisterClasses, RegisterClasses+54,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFE0000002), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(PPCRegDesc, 548, RA, PC,
                     PPCMCRegisterClasses, 54,
                     PPCRegUnitRoots,
                     265,
                     PPCRegDiffLists,
                     PPCLaneMaskLists,
                     PPCRegStrings,
                     PPCRegClassStrings,
                     PPCSubRegIdxLists,
                     52,
                     PPCSubRegIdxRanges,
                     PPCRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(PPCDwarfFlavour0Dwarf2L, PPCDwarfFlavour0Dwarf2LSize, false);
    break;
  case 1:
    mapDwarfRegsToLLVMRegs(PPCDwarfFlavour1Dwarf2L, PPCDwarfFlavour1Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(PPCEHFlavour0Dwarf2L, PPCEHFlavour0Dwarf2LSize, true);
    break;
  case 1:
    mapDwarfRegsToLLVMRegs(PPCEHFlavour1Dwarf2L, PPCEHFlavour1Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(PPCDwarfFlavour0L2Dwarf, PPCDwarfFlavour0L2DwarfSize, false);
    break;
  case 1:
    mapLLVMRegsToDwarfRegs(PPCDwarfFlavour1L2Dwarf, PPCDwarfFlavour1L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(PPCEHFlavour0L2Dwarf, PPCEHFlavour0L2DwarfSize, true);
    break;
  case 1:
    mapLLVMRegsToDwarfRegs(PPCEHFlavour1L2Dwarf, PPCEHFlavour1L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_64_AllRegs_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const uint32_t CSR_64_AllRegs_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, 0 };
static const uint32_t CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0x007ffff8, 0x007ffff8, 0x00000000, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_AIX_Dflt_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 0 };
static const uint32_t CSR_64_AllRegs_AIX_Dflt_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0x007fffff, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_Altivec_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_64_AllRegs_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0x00000007, 0x00000000, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_VSRP_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_64_AllRegs_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_64_AllRegs_VSX_SaveList[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 0 };
static const uint32_t CSR_64_AllRegs_VSX_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xc8000000, 0x07fffe3f, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x3fc80000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_AIX32_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
static const uint32_t CSR_AIX32_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07ffff00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_AIX32_Altivec_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_AIX32_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07ffff00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_AIX32_VSRP_SaveList[] = { PPC::R13, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_AIX32_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07ffff00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_AIX64_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
static const uint32_t CSR_AIX64_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_AIX64_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_AIX64_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_ALL_VSRP_SaveList[] = { PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp17, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_ALL_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x00000000, 0x00000000, 0x00000000, 0xfffffff8, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000007, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Altivec_SaveList[] = { PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_Altivec_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_PPC64_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
static const uint32_t CSR_PPC64_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_PPC64_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_PPC64_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_PPC64_R2_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::X2, 0 };
static const uint32_t CSR_PPC64_R2_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x20000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_PPC64_R2_Altivec_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
static const uint32_t CSR_PPC64_R2_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SPE_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
static const uint32_t CSR_SPE_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffff00, 0x03fffe00, 0x03fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SPE_NO_S30_31_SaveList[] = { PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
static const uint32_t CSR_SPE_NO_S30_31_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ffff00, 0x01fffe00, 0x01fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_SVR32_ColdCC_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
static const uint32_t CSR_SVR32_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR32_ColdCC_Altivec_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_SVR32_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR32_ColdCC_Common_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const uint32_t CSR_SVR32_ColdCC_Common_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR32_ColdCC_SPE_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::S4, PPC::S5, PPC::S6, PPC::S7, PPC::S8, PPC::S9, PPC::S10, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, PPC::S31, 0 };
static const uint32_t CSR_SVR32_ColdCC_SPE_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc0000000, 0x83ffff1f, 0x87fffe3f, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR32_ColdCC_VSRP_SaveList[] = { PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR32_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0xffffffff, 0xffefffff, 0x00000007, 0x00000000, 0xfff80000, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR64_ColdCC_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
static const uint32_t CSR_SVR64_ColdCC_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR64_ColdCC_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_SVR64_ColdCC_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR64_ColdCC_R2_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::X2, 0 };
static const uint32_t CSR_SVR64_ColdCC_R2_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0xa0000000, 0x07fffe3f, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR64_ColdCC_R2_Altivec_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::V0, PPC::V1, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8, PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::X2, 0 };
static const uint32_t CSR_SVR64_ColdCC_R2_Altivec_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffa00, 0x000001ff, 0xa0000000, 0x07fffe3f, 0x00000000, 0xffffffd8, 0xffffffdf, 0x00000007, 0x00000000, 0x00000000, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR64_ColdCC_R2_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
static const uint32_t CSR_SVR64_ColdCC_R2_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0xa0000000, 0x07fffe3f, 0x00000000, 0xffffff98, 0xffffff9f, 0xffffffff, 0xffefffff, 0x00000007, 0x3fa00000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR64_ColdCC_VSRP_SaveList[] = { PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F0, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7, PPC::VSRp0, PPC::VSRp1, PPC::VSRp2, PPC::VSRp3, PPC::VSRp4, PPC::VSRp5, PPC::VSRp6, PPC::VSRp7, PPC::VSRp8, PPC::VSRp9, PPC::VSRp10, PPC::VSRp11, PPC::VSRp12, PPC::VSRp13, PPC::VSRp14, PPC::VSRp15, PPC::VSRp16, PPC::VSRp18, PPC::VSRp19, PPC::VSRp20, PPC::VSRp21, PPC::VSRp22, PPC::VSRp23, PPC::VSRp24, PPC::VSRp25, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR64_ColdCC_VSRP_RegMask[] = { 0x0ff00400, 0x00000000, 0x00000000, 0x00000000, 0xfffffe00, 0x000001ff, 0x80000000, 0x07fffe3f, 0x00000000, 0xffffff98, 0xffffff9f, 0xffffffff, 0xffefffff, 0x00000007, 0x3f800000, 0xfffffffe, 0x000fffff, 0x00000000, };
static const MCPhysReg CSR_SVR432_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, 0 };
static const uint32_t CSR_SVR432_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR432_Altivec_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, 0 };
static const uint32_t CSR_SVR432_Altivec_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR432_COMM_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, 0 };
static const uint32_t CSR_SVR432_COMM_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x07fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR432_SPE_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, PPC::S30, 0 };
static const uint32_t CSR_SVR432_SPE_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x01ffff00, 0x07fffe00, 0x03fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR432_SPE_NO_S30_31_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::S14, PPC::S15, PPC::S16, PPC::S17, PPC::S18, PPC::S19, PPC::S20, PPC::S21, PPC::S22, PPC::S23, PPC::S24, PPC::S25, PPC::S26, PPC::S27, PPC::S28, PPC::S29, 0 };
static const uint32_t CSR_SVR432_SPE_NO_S30_31_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00ffff00, 0x07fffe00, 0x01fffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR432_VSRP_SaveList[] = { PPC::R14, PPC::R15, PPC::R16, PPC::R17, PPC::R18, PPC::R19, PPC::R20, PPC::R21, PPC::R22, PPC::R23, PPC::R24, PPC::R25, PPC::R26, PPC::R27, PPC::R28, PPC::R29, PPC::R30, PPC::R31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR432_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1c80000, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR464_R2_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, PPC::X2, 0 };
static const uint32_t CSR_SVR464_R2_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x20000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00200000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_SVR464_VSRP_SaveList[] = { PPC::X14, PPC::X15, PPC::X16, PPC::X17, PPC::X18, PPC::X19, PPC::X20, PPC::X21, PPC::X22, PPC::X23, PPC::X24, PPC::X25, PPC::X26, PPC::X27, PPC::X28, PPC::X29, PPC::X30, PPC::X31, PPC::F14, PPC::F15, PPC::F16, PPC::F17, PPC::F18, PPC::F19, PPC::F20, PPC::F21, PPC::F22, PPC::F23, PPC::F24, PPC::F25, PPC::F26, PPC::F27, PPC::F28, PPC::F29, PPC::F30, PPC::F31, PPC::CR2, PPC::CR3, PPC::CR4, PPC::V20, PPC::V21, PPC::V22, PPC::V23, PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31, PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_SVR464_VSRP_RegMask[] = { 0x01c00400, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0x000001ff, 0x00000000, 0x07fffe00, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0xc1cffffe, 0x0001c1c1, 0x00000000, };
static const MCPhysReg CSR_VSRP_SaveList[] = { PPC::VSRp26, PPC::VSRp27, PPC::VSRp28, PPC::VSRp29, PPC::VSRp30, PPC::VSRp31, 0 };
static const uint32_t CSR_VSRP_RegMask[] = { 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff800000, 0xff800007, 0x00000007, 0xe0000000, 0x00000007, 0x00000000, 0x00080000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> PPCGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_64_AllRegs_RegMask,
    CSR_64_AllRegs_AIX_Dflt_Altivec_RegMask,
    CSR_64_AllRegs_AIX_Dflt_VSX_RegMask,
    CSR_64_AllRegs_Altivec_RegMask,
    CSR_64_AllRegs_VSRP_RegMask,
    CSR_64_AllRegs_VSX_RegMask,
    CSR_AIX32_RegMask,
    CSR_AIX32_Altivec_RegMask,
    CSR_AIX32_VSRP_RegMask,
    CSR_AIX64_R2_VSRP_RegMask,
    CSR_AIX64_VSRP_RegMask,
    CSR_ALL_VSRP_RegMask,
    CSR_Altivec_RegMask,
    CSR_NoRegs_RegMask,
    CSR_PPC64_RegMask,
    CSR_PPC64_Altivec_RegMask,
    CSR_PPC64_R2_RegMask,
    CSR_PPC64_R2_Altivec_RegMask,
    CSR_SPE_RegMask,
    CSR_SPE_NO_S30_31_RegMask,
    CSR_SVR32_ColdCC_RegMask,
    CSR_SVR32_ColdCC_Altivec_RegMask,
    CSR_SVR32_ColdCC_Common_RegMask,
    CSR_SVR32_ColdCC_SPE_RegMask,
    CSR_SVR32_ColdCC_VSRP_RegMask,
    CSR_SVR64_ColdCC_RegMask,
    CSR_SVR64_ColdCC_Altivec_RegMask,
    CSR_SVR64_ColdCC_R2_RegMask,
    CSR_SVR64_ColdCC_R2_Altivec_RegMask,
    CSR_SVR64_ColdCC_R2_VSRP_RegMask,
    CSR_SVR64_ColdCC_VSRP_RegMask,
    CSR_SVR432_RegMask,
    CSR_SVR432_Altivec_RegMask,
    CSR_SVR432_COMM_RegMask,
    CSR_SVR432_SPE_RegMask,
    CSR_SVR432_SPE_NO_S30_31_RegMask,
    CSR_SVR432_VSRP_RegMask,
    CSR_SVR464_R2_VSRP_RegMask,
    CSR_SVR464_VSRP_RegMask,
    CSR_VSRP_RegMask,
  };
  return ArrayRef(Masks);
}

bool PPCGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool PPCGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool PPCGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool PPCGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      PhysReg == PPC::ZERO ||
      PhysReg == PPC::ZERO8 ||
      false;
}

ArrayRef<const char *> PPCGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR_64_AllRegs",
    "CSR_64_AllRegs_AIX_Dflt_Altivec",
    "CSR_64_AllRegs_AIX_Dflt_VSX",
    "CSR_64_AllRegs_Altivec",
    "CSR_64_AllRegs_VSRP",
    "CSR_64_AllRegs_VSX",
    "CSR_AIX32",
    "CSR_AIX32_Altivec",
    "CSR_AIX32_VSRP",
    "CSR_AIX64_R2_VSRP",
    "CSR_AIX64_VSRP",
    "CSR_ALL_VSRP",
    "CSR_Altivec",
    "CSR_NoRegs",
    "CSR_PPC64",
    "CSR_PPC64_Altivec",
    "CSR_PPC64_R2",
    "CSR_PPC64_R2_Altivec",
    "CSR_SPE",
    "CSR_SPE_NO_S30_31",
    "CSR_SVR32_ColdCC",
    "CSR_SVR32_ColdCC_Altivec",
    "CSR_SVR32_ColdCC_Common",
    "CSR_SVR32_ColdCC_SPE",
    "CSR_SVR32_ColdCC_VSRP",
    "CSR_SVR64_ColdCC",
    "CSR_SVR64_ColdCC_Altivec",
    "CSR_SVR64_ColdCC_R2",
    "CSR_SVR64_ColdCC_R2_Altivec",
    "CSR_SVR64_ColdCC_R2_VSRP",
    "CSR_SVR64_ColdCC_VSRP",
    "CSR_SVR432",
    "CSR_SVR432_Altivec",
    "CSR_SVR432_COMM",
    "CSR_SVR432_SPE",
    "CSR_SVR432_SPE_NO_S30_31",
    "CSR_SVR432_VSRP",
    "CSR_SVR464_R2_VSRP",
    "CSR_SVR464_VSRP",
    "CSR_VSRP",
  };
  return ArrayRef(Names);
}

const PPCFrameLowering *
PPCGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const PPCFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31