Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc
Line
Count
Source (jump to first uncovered line)
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Compress instruction Source Fragment                                       *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|* From: RISCV.td                                                             *|
7
|*                                                                            *|
8
\*===----------------------------------------------------------------------===*/
9
10
11
#ifdef GEN_COMPRESS_INSTR
12
#undef GEN_COMPRESS_INSTR
13
14
static bool RISCVValidateMCOperandForCompress(const MCOperand &MCOp,
15
                  const MCSubtargetInfo &STI,
16
0
                  unsigned PredicateIndex) {
17
0
  switch (PredicateIndex) {
18
0
  default:
19
0
    llvm_unreachable("Unknown MCOperandPredicate kind");
20
0
    break;
21
0
  case 1: {
22
  // uimm10_lsb00nonzero
23
  
24
0
    int64_t Imm;
25
0
    if (!MCOp.evaluateAsConstantImm(Imm))
26
0
      return false;
27
0
    return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
28
  
29
0
  }
30
0
  case 2: {
31
  // simm6nonzero
32
  
33
0
    int64_t Imm;
34
0
    if (MCOp.evaluateAsConstantImm(Imm))
35
0
      return (Imm != 0) && isInt<6>(Imm);
36
0
    return MCOp.isBareSymbolRef();
37
  
38
0
  }
39
0
  case 3: {
40
  // simm6
41
  
42
0
    int64_t Imm;
43
0
    if (MCOp.evaluateAsConstantImm(Imm))
44
0
      return isInt<6>(Imm);
45
0
    return MCOp.isBareSymbolRef();
46
  
47
0
  }
48
0
  case 4: {
49
  // simm10_lsb0000nonzero
50
  
51
0
    int64_t Imm;
52
0
    if (!MCOp.evaluateAsConstantImm(Imm))
53
0
      return false;
54
0
    return isShiftedInt<6, 4>(Imm) && (Imm != 0);
55
  
56
0
  }
57
0
  case 5: {
58
  // simm9_lsb0
59
  
60
0
    int64_t Imm;
61
0
    if (MCOp.evaluateAsConstantImm(Imm))
62
0
      return isShiftedInt<8, 1>(Imm);
63
0
    return MCOp.isBareSymbolRef();
64
65
  
66
0
  }
67
0
  case 6: {
68
  // uimm8_lsb000
69
  
70
0
    int64_t Imm;
71
0
    if (!MCOp.evaluateAsConstantImm(Imm))
72
0
      return false;
73
0
    return isShiftedUInt<5, 3>(Imm);
74
  
75
0
  }
76
0
  case 7: {
77
  // uimm9_lsb000
78
  
79
0
    int64_t Imm;
80
0
    if (!MCOp.evaluateAsConstantImm(Imm))
81
0
      return false;
82
0
    return isShiftedUInt<6, 3>(Imm);
83
  
84
0
  }
85
0
  case 8: {
86
  // uimm7_lsb00
87
  
88
0
    int64_t Imm;
89
0
    if (!MCOp.evaluateAsConstantImm(Imm))
90
0
      return false;
91
0
    return isShiftedUInt<5, 2>(Imm);
92
  
93
0
  }
94
0
  case 9: {
95
  // uimm8_lsb00
96
  
97
0
    int64_t Imm;
98
0
    if (!MCOp.evaluateAsConstantImm(Imm))
99
0
      return false;
100
0
    return isShiftedUInt<6, 2>(Imm);
101
  
102
0
  }
103
0
  case 10: {
104
  // simm12_lsb0
105
  
106
0
    int64_t Imm;
107
0
    if (MCOp.evaluateAsConstantImm(Imm))
108
0
      return isShiftedInt<11, 1>(Imm);
109
0
    return MCOp.isBareSymbolRef();
110
  
111
0
  }
112
0
  case 11: {
113
  // uimm2
114
  
115
0
    int64_t Imm;
116
0
    if (!MCOp.evaluateAsConstantImm(Imm))
117
0
      return false;
118
0
    return isUInt<2>(Imm);
119
  
120
0
  }
121
0
  case 12: {
122
  // uimm2_lsb0
123
  
124
0
    int64_t Imm;
125
0
    if (!MCOp.evaluateAsConstantImm(Imm))
126
0
      return false;
127
0
    return isShiftedUInt<1, 1>(Imm);
128
  
129
0
  }
130
0
  case 13: {
131
  // c_lui_imm
132
  
133
0
    int64_t Imm;
134
0
    if (MCOp.evaluateAsConstantImm(Imm))
135
0
      return (Imm != 0) && (isUInt<5>(Imm) ||
136
0
             (Imm >= 0xfffe0 && Imm <= 0xfffff));
137
0
    return MCOp.isBareSymbolRef();
138
  
139
0
  }
140
0
  case 14: {
141
  // uimmlog2xlennonzero
142
  
143
0
    int64_t Imm;
144
0
    if (!MCOp.evaluateAsConstantImm(Imm))
145
0
      return false;
146
0
    if (STI.getTargetTriple().isArch64Bit())
147
0
      return  isUInt<6>(Imm) && (Imm != 0);
148
0
    return isUInt<5>(Imm) && (Imm != 0);
149
  
150
0
  }
151
0
  }
152
0
}
153
154
static bool compressInst(MCInst &OutInst,
155
                         const MCInst &MI,
156
860k
                         const MCSubtargetInfo &STI) {
157
860k
  switch (MI.getOpcode()) {
158
101k
    default: return false;
159
13.3k
    case RISCV::ADD: {
160
13.3k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
161
13.3k
      (MI.getOperand(1).isReg()) &&
162
13.3k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
163
13.3k
      (MI.getOperand(0).isReg()) &&
164
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
165
13.3k
      (MI.getOperand(2).isReg()) &&
166
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) {
167
      // c.mv $rs1, $rs2
168
0
      OutInst.setOpcode(RISCV::C_MV);
169
      // Operand: rs1
170
0
      OutInst.addOperand(MI.getOperand(0));
171
      // Operand: rs2
172
0
      OutInst.addOperand(MI.getOperand(2));
173
0
      OutInst.setLoc(MI.getLoc());
174
0
      return true;
175
0
    } // if
176
13.3k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
177
13.3k
      (MI.getOperand(2).isReg()) &&
178
13.3k
      (MI.getOperand(2).getReg() == RISCV::X0) &&
179
13.3k
      (MI.getOperand(0).isReg()) &&
180
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
181
13.3k
      (MI.getOperand(1).isReg()) &&
182
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
183
      // c.mv $rs1, $rs2
184
0
      OutInst.setOpcode(RISCV::C_MV);
185
      // Operand: rs1
186
0
      OutInst.addOperand(MI.getOperand(0));
187
      // Operand: rs2
188
0
      OutInst.addOperand(MI.getOperand(1));
189
0
      OutInst.setLoc(MI.getLoc());
190
0
      return true;
191
0
    } // if
192
13.3k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
193
13.3k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
194
13.3k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
195
13.3k
      (MI.getOperand(1).isReg()) &&
196
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
197
13.3k
      (MI.getOperand(2).isReg()) &&
198
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) {
199
      // c.add  $rs1, $rs2
200
0
      OutInst.setOpcode(RISCV::C_ADD);
201
      // Operand: rs1_wb
202
0
      OutInst.addOperand(MI.getOperand(1));
203
      // Operand: rs1
204
0
      OutInst.addOperand(MI.getOperand(1));
205
      // Operand: rs2
206
0
      OutInst.addOperand(MI.getOperand(2));
207
0
      OutInst.setLoc(MI.getLoc());
208
0
      return true;
209
0
    } // if
210
13.3k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
211
13.3k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
212
13.3k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
213
13.3k
      (MI.getOperand(2).isReg()) &&
214
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg())) &&
215
13.3k
      (MI.getOperand(1).isReg()) &&
216
13.3k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
217
      // c.add  $rs1, $rs2
218
0
      OutInst.setOpcode(RISCV::C_ADD);
219
      // Operand: rs1_wb
220
0
      OutInst.addOperand(MI.getOperand(2));
221
      // Operand: rs1
222
0
      OutInst.addOperand(MI.getOperand(2));
223
      // Operand: rs2
224
0
      OutInst.addOperand(MI.getOperand(1));
225
0
      OutInst.setLoc(MI.getLoc());
226
0
      return true;
227
0
    } // if
228
13.3k
      break;
229
13.3k
    } // case ADD
230
136k
    case RISCV::ADDI: {
231
136k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
232
136k
      (MI.getOperand(0).isReg()) &&
233
136k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
234
136k
      (MI.getOperand(1).isReg()) &&
235
136k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
236
136k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 1)) {
237
      // c.addi4spn $rd, $rs1, $imm
238
0
      OutInst.setOpcode(RISCV::C_ADDI4SPN);
239
      // Operand: rd
240
0
      OutInst.addOperand(MI.getOperand(0));
241
      // Operand: rs1
242
0
      OutInst.addOperand(MI.getOperand(1));
243
      // Operand: imm
244
0
      OutInst.addOperand(MI.getOperand(2));
245
0
      OutInst.setLoc(MI.getLoc());
246
0
      return true;
247
0
    } // if
248
136k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
249
136k
      (MI.getOperand(0).isReg()) &&
250
136k
      (MI.getOperand(0).getReg() == RISCV::X0) &&
251
136k
      (MI.getOperand(1).isReg()) &&
252
136k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
253
136k
      (MI.getOperand(2).isImm()) &&
254
136k
      (MI.getOperand(2).getImm() == 0)) {
255
      // c.nop
256
0
      OutInst.setOpcode(RISCV::C_NOP);
257
0
      OutInst.setLoc(MI.getLoc());
258
0
      return true;
259
0
    } // if
260
136k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
261
136k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
262
136k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
263
136k
      (MI.getOperand(1).isReg()) &&
264
136k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
265
136k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 2)) {
266
      // c.addi $rd, $imm
267
0
      OutInst.setOpcode(RISCV::C_ADDI);
268
      // Operand: rd_wb
269
0
      OutInst.addOperand(MI.getOperand(1));
270
      // Operand: rd
271
0
      OutInst.addOperand(MI.getOperand(1));
272
      // Operand: imm
273
0
      OutInst.addOperand(MI.getOperand(2));
274
0
      OutInst.setLoc(MI.getLoc());
275
0
      return true;
276
0
    } // if
277
136k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
278
136k
      (MI.getOperand(1).isReg()) &&
279
136k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
280
136k
      (MI.getOperand(0).isReg()) &&
281
136k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
282
136k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) {
283
      // c.li $rd, $imm
284
0
      OutInst.setOpcode(RISCV::C_LI);
285
      // Operand: rd
286
0
      OutInst.addOperand(MI.getOperand(0));
287
      // Operand: imm
288
0
      OutInst.addOperand(MI.getOperand(2));
289
0
      OutInst.setLoc(MI.getLoc());
290
0
      return true;
291
0
    } // if
292
136k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
293
136k
      (MI.getOperand(0).isReg()) &&
294
136k
      (MI.getOperand(0).getReg() == RISCV::X2) &&
295
136k
      (MI.getOperand(1).isReg()) &&
296
136k
      (MI.getOperand(1).getReg() == RISCV::X2) &&
297
136k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 4)) {
298
      // c.addi16sp $rd, $imm
299
0
      OutInst.setOpcode(RISCV::C_ADDI16SP);
300
      // Operand: rd_wb
301
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X2));
302
      // Operand: rd
303
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X2));
304
      // Operand: imm
305
0
      OutInst.addOperand(MI.getOperand(2));
306
0
      OutInst.setLoc(MI.getLoc());
307
0
      return true;
308
0
    } // if
309
136k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
310
136k
      (MI.getOperand(2).isImm()) &&
311
136k
      (MI.getOperand(2).getImm() == 0) &&
312
136k
      (MI.getOperand(0).isReg()) &&
313
136k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
314
136k
      (MI.getOperand(1).isReg()) &&
315
136k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
316
      // c.mv $rs1, $rs2
317
0
      OutInst.setOpcode(RISCV::C_MV);
318
      // Operand: rs1
319
0
      OutInst.addOperand(MI.getOperand(0));
320
      // Operand: rs2
321
0
      OutInst.addOperand(MI.getOperand(1));
322
0
      OutInst.setLoc(MI.getLoc());
323
0
      return true;
324
0
    } // if
325
136k
      break;
326
136k
    } // case ADDI
327
136k
    case RISCV::ADDIW: {
328
4.51k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
329
4.51k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
330
4.51k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
331
4.51k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
332
4.51k
      (MI.getOperand(1).isReg()) &&
333
4.51k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
334
4.51k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) {
335
      // c.addiw  $rd, $imm
336
0
      OutInst.setOpcode(RISCV::C_ADDIW);
337
      // Operand: rd_wb
338
0
      OutInst.addOperand(MI.getOperand(1));
339
      // Operand: rd
340
0
      OutInst.addOperand(MI.getOperand(1));
341
      // Operand: imm
342
0
      OutInst.addOperand(MI.getOperand(2));
343
0
      OutInst.setLoc(MI.getLoc());
344
0
      return true;
345
0
    } // if
346
4.51k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
347
4.51k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
348
4.51k
      (MI.getOperand(1).isReg()) &&
349
4.51k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
350
4.51k
      (MI.getOperand(0).isReg()) &&
351
4.51k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
352
4.51k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) {
353
      // c.li $rd, $imm
354
0
      OutInst.setOpcode(RISCV::C_LI);
355
      // Operand: rd
356
0
      OutInst.addOperand(MI.getOperand(0));
357
      // Operand: imm
358
0
      OutInst.addOperand(MI.getOperand(2));
359
0
      OutInst.setLoc(MI.getLoc());
360
0
      return true;
361
0
    } // if
362
4.51k
      break;
363
4.51k
    } // case ADDIW
364
4.51k
    case RISCV::ADDW: {
365
139
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
366
139
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
367
139
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
368
139
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
369
139
      (MI.getOperand(1).isReg()) &&
370
139
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
371
139
      (MI.getOperand(2).isReg()) &&
372
139
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
373
      // c.addw $rd, $rs2
374
0
      OutInst.setOpcode(RISCV::C_ADDW);
375
      // Operand: rd_wb
376
0
      OutInst.addOperand(MI.getOperand(1));
377
      // Operand: rd
378
0
      OutInst.addOperand(MI.getOperand(1));
379
      // Operand: rs2
380
0
      OutInst.addOperand(MI.getOperand(2));
381
0
      OutInst.setLoc(MI.getLoc());
382
0
      return true;
383
0
    } // if
384
139
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
385
139
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
386
139
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
387
139
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
388
139
      (MI.getOperand(2).isReg()) &&
389
139
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
390
139
      (MI.getOperand(1).isReg()) &&
391
139
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
392
      // c.addw $rd, $rs2
393
0
      OutInst.setOpcode(RISCV::C_ADDW);
394
      // Operand: rd_wb
395
0
      OutInst.addOperand(MI.getOperand(2));
396
      // Operand: rd
397
0
      OutInst.addOperand(MI.getOperand(2));
398
      // Operand: rs2
399
0
      OutInst.addOperand(MI.getOperand(1));
400
0
      OutInst.setLoc(MI.getLoc());
401
0
      return true;
402
0
    } // if
403
139
      break;
404
139
    } // case ADDW
405
139
    case RISCV::ADD_UW: {
406
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
407
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
408
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
409
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
410
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
411
0
      (MI.getOperand(2).isReg()) &&
412
0
      (MI.getOperand(2).getReg() == RISCV::X0) &&
413
0
      (MI.getOperand(1).isReg()) &&
414
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
415
      // c.zext.w $rd
416
0
      OutInst.setOpcode(RISCV::C_ZEXT_W);
417
      // Operand: rd_wb
418
0
      OutInst.addOperand(MI.getOperand(1));
419
      // Operand: rd
420
0
      OutInst.addOperand(MI.getOperand(1));
421
0
      OutInst.setLoc(MI.getLoc());
422
0
      return true;
423
0
    } // if
424
0
      break;
425
0
    } // case ADD_UW
426
8.37k
    case RISCV::AND: {
427
8.37k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
428
8.37k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
429
8.37k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
430
8.37k
      (MI.getOperand(1).isReg()) &&
431
8.37k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
432
8.37k
      (MI.getOperand(2).isReg()) &&
433
8.37k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
434
      // c.and  $rd, $rs2
435
0
      OutInst.setOpcode(RISCV::C_AND);
436
      // Operand: rd_wb
437
0
      OutInst.addOperand(MI.getOperand(1));
438
      // Operand: rd
439
0
      OutInst.addOperand(MI.getOperand(1));
440
      // Operand: rs2
441
0
      OutInst.addOperand(MI.getOperand(2));
442
0
      OutInst.setLoc(MI.getLoc());
443
0
      return true;
444
0
    } // if
445
8.37k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
446
8.37k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
447
8.37k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
448
8.37k
      (MI.getOperand(2).isReg()) &&
449
8.37k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
450
8.37k
      (MI.getOperand(1).isReg()) &&
451
8.37k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
452
      // c.and  $rd, $rs2
453
0
      OutInst.setOpcode(RISCV::C_AND);
454
      // Operand: rd_wb
455
0
      OutInst.addOperand(MI.getOperand(2));
456
      // Operand: rd
457
0
      OutInst.addOperand(MI.getOperand(2));
458
      // Operand: rs2
459
0
      OutInst.addOperand(MI.getOperand(1));
460
0
      OutInst.setLoc(MI.getLoc());
461
0
      return true;
462
0
    } // if
463
8.37k
      break;
464
8.37k
    } // case AND
465
18.0k
    case RISCV::ANDI: {
466
18.0k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
467
18.0k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
468
18.0k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
469
18.0k
      (MI.getOperand(1).isReg()) &&
470
18.0k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
471
18.0k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 3)) {
472
      // c.andi $rs1, $imm
473
0
      OutInst.setOpcode(RISCV::C_ANDI);
474
      // Operand: rs1_wb
475
0
      OutInst.addOperand(MI.getOperand(1));
476
      // Operand: rs1
477
0
      OutInst.addOperand(MI.getOperand(1));
478
      // Operand: imm
479
0
      OutInst.addOperand(MI.getOperand(2));
480
0
      OutInst.setLoc(MI.getLoc());
481
0
      return true;
482
0
    } // if
483
18.0k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
484
18.0k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
485
18.0k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
486
18.0k
      (MI.getOperand(2).isImm()) &&
487
18.0k
      (MI.getOperand(2).getImm() == 255) &&
488
18.0k
      (MI.getOperand(1).isReg()) &&
489
18.0k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
490
      // c.zext.b $rd
491
0
      OutInst.setOpcode(RISCV::C_ZEXT_B);
492
      // Operand: rd_wb
493
0
      OutInst.addOperand(MI.getOperand(1));
494
      // Operand: rd
495
0
      OutInst.addOperand(MI.getOperand(1));
496
0
      OutInst.setLoc(MI.getLoc());
497
0
      return true;
498
0
    } // if
499
18.0k
      break;
500
18.0k
    } // case ANDI
501
18.0k
    case RISCV::BEQ: {
502
169
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
503
169
      (MI.getOperand(1).isReg()) &&
504
169
      (MI.getOperand(1).getReg() == RISCV::X0) &&
505
169
      (MI.getOperand(0).isReg()) &&
506
169
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
507
169
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 5)) {
508
      // c.beqz $rs1, $imm
509
0
      OutInst.setOpcode(RISCV::C_BEQZ);
510
      // Operand: rs1
511
0
      OutInst.addOperand(MI.getOperand(0));
512
      // Operand: imm
513
0
      OutInst.addOperand(MI.getOperand(2));
514
0
      OutInst.setLoc(MI.getLoc());
515
0
      return true;
516
0
    } // if
517
169
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
518
169
      (MI.getOperand(0).isReg()) &&
519
169
      (MI.getOperand(0).getReg() == RISCV::X0) &&
520
169
      (MI.getOperand(1).isReg()) &&
521
169
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
522
169
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 5)) {
523
      // c.beqz $rs1, $imm
524
0
      OutInst.setOpcode(RISCV::C_BEQZ);
525
      // Operand: rs1
526
0
      OutInst.addOperand(MI.getOperand(1));
527
      // Operand: imm
528
0
      OutInst.addOperand(MI.getOperand(2));
529
0
      OutInst.setLoc(MI.getLoc());
530
0
      return true;
531
0
    } // if
532
169
      break;
533
169
    } // case BEQ
534
2.13k
    case RISCV::BNE: {
535
2.13k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
536
2.13k
      (MI.getOperand(1).isReg()) &&
537
2.13k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
538
2.13k
      (MI.getOperand(0).isReg()) &&
539
2.13k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
540
2.13k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 5)) {
541
      // c.bnez $rs1, $imm
542
0
      OutInst.setOpcode(RISCV::C_BNEZ);
543
      // Operand: rs1
544
0
      OutInst.addOperand(MI.getOperand(0));
545
      // Operand: imm
546
0
      OutInst.addOperand(MI.getOperand(2));
547
0
      OutInst.setLoc(MI.getLoc());
548
0
      return true;
549
0
    } // if
550
2.13k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
551
2.13k
      (MI.getOperand(0).isReg()) &&
552
2.13k
      (MI.getOperand(0).getReg() == RISCV::X0) &&
553
2.13k
      (MI.getOperand(1).isReg()) &&
554
2.13k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
555
2.13k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 5)) {
556
      // c.bnez $rs1, $imm
557
0
      OutInst.setOpcode(RISCV::C_BNEZ);
558
      // Operand: rs1
559
0
      OutInst.addOperand(MI.getOperand(1));
560
      // Operand: imm
561
0
      OutInst.addOperand(MI.getOperand(2));
562
0
      OutInst.setLoc(MI.getLoc());
563
0
      return true;
564
0
    } // if
565
2.13k
      break;
566
2.13k
    } // case BNE
567
2.13k
    case RISCV::EBREAK: {
568
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
569
      // c.ebreak
570
0
      OutInst.setOpcode(RISCV::C_EBREAK);
571
0
      OutInst.setLoc(MI.getLoc());
572
0
      return true;
573
0
    } // if
574
0
      break;
575
0
    } // case EBREAK
576
0
    case RISCV::FLD: {
577
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
578
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
579
0
      (MI.getOperand(0).isReg()) &&
580
0
      (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) &&
581
0
      (MI.getOperand(1).isReg()) &&
582
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
583
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) {
584
      // c.fld  $rd, ${imm}(${rs1})
585
0
      OutInst.setOpcode(RISCV::C_FLD);
586
      // Operand: rd
587
0
      OutInst.addOperand(MI.getOperand(0));
588
      // Operand: rs1
589
0
      OutInst.addOperand(MI.getOperand(1));
590
      // Operand: imm
591
0
      OutInst.addOperand(MI.getOperand(2));
592
0
      OutInst.setLoc(MI.getLoc());
593
0
      return true;
594
0
    } // if
595
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
596
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
597
0
      (MI.getOperand(0).isReg()) &&
598
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
599
0
      (MI.getOperand(1).isReg()) &&
600
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
601
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) {
602
      // c.fldsp  $rd, ${imm}(${rs1})
603
0
      OutInst.setOpcode(RISCV::C_FLDSP);
604
      // Operand: rd
605
0
      OutInst.addOperand(MI.getOperand(0));
606
      // Operand: rs1
607
0
      OutInst.addOperand(MI.getOperand(1));
608
      // Operand: imm
609
0
      OutInst.addOperand(MI.getOperand(2));
610
0
      OutInst.setLoc(MI.getLoc());
611
0
      return true;
612
0
    } // if
613
0
      break;
614
0
    } // case FLD
615
0
    case RISCV::FLW: {
616
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
617
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
618
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
619
0
      (MI.getOperand(0).isReg()) &&
620
0
      (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) &&
621
0
      (MI.getOperand(1).isReg()) &&
622
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
623
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) {
624
      // c.flw  $rd, ${imm}(${rs1})
625
0
      OutInst.setOpcode(RISCV::C_FLW);
626
      // Operand: rd
627
0
      OutInst.addOperand(MI.getOperand(0));
628
      // Operand: rs1
629
0
      OutInst.addOperand(MI.getOperand(1));
630
      // Operand: imm
631
0
      OutInst.addOperand(MI.getOperand(2));
632
0
      OutInst.setLoc(MI.getLoc());
633
0
      return true;
634
0
    } // if
635
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
636
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
637
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
638
0
      (MI.getOperand(0).isReg()) &&
639
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
640
0
      (MI.getOperand(1).isReg()) &&
641
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
642
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) {
643
      // c.flwsp  $rd, ${imm}(${rs1})
644
0
      OutInst.setOpcode(RISCV::C_FLWSP);
645
      // Operand: rd
646
0
      OutInst.addOperand(MI.getOperand(0));
647
      // Operand: rs1
648
0
      OutInst.addOperand(MI.getOperand(1));
649
      // Operand: imm
650
0
      OutInst.addOperand(MI.getOperand(2));
651
0
      OutInst.setLoc(MI.getLoc());
652
0
      return true;
653
0
    } // if
654
0
      break;
655
0
    } // case FLW
656
0
    case RISCV::FSD: {
657
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
658
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
659
0
      (MI.getOperand(0).isReg()) &&
660
0
      (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) &&
661
0
      (MI.getOperand(1).isReg()) &&
662
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
663
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) {
664
      // c.fsd  $rs2, ${imm}(${rs1})
665
0
      OutInst.setOpcode(RISCV::C_FSD);
666
      // Operand: rs2
667
0
      OutInst.addOperand(MI.getOperand(0));
668
      // Operand: rs1
669
0
      OutInst.addOperand(MI.getOperand(1));
670
      // Operand: imm
671
0
      OutInst.addOperand(MI.getOperand(2));
672
0
      OutInst.setLoc(MI.getLoc());
673
0
      return true;
674
0
    } // if
675
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
676
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
677
0
      (MI.getOperand(0).isReg()) &&
678
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
679
0
      (MI.getOperand(1).isReg()) &&
680
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
681
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) {
682
      // c.fsdsp  $rs2, ${imm}(${rs1})
683
0
      OutInst.setOpcode(RISCV::C_FSDSP);
684
      // Operand: rs2
685
0
      OutInst.addOperand(MI.getOperand(0));
686
      // Operand: rs1
687
0
      OutInst.addOperand(MI.getOperand(1));
688
      // Operand: imm
689
0
      OutInst.addOperand(MI.getOperand(2));
690
0
      OutInst.setLoc(MI.getLoc());
691
0
      return true;
692
0
    } // if
693
0
      break;
694
0
    } // case FSD
695
0
    case RISCV::FSW: {
696
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
697
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
698
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
699
0
      (MI.getOperand(0).isReg()) &&
700
0
      (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) &&
701
0
      (MI.getOperand(1).isReg()) &&
702
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
703
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) {
704
      // c.fsw  $rs2, ${imm}(${rs1})
705
0
      OutInst.setOpcode(RISCV::C_FSW);
706
      // Operand: rs2
707
0
      OutInst.addOperand(MI.getOperand(0));
708
      // Operand: rs1
709
0
      OutInst.addOperand(MI.getOperand(1));
710
      // Operand: imm
711
0
      OutInst.addOperand(MI.getOperand(2));
712
0
      OutInst.setLoc(MI.getLoc());
713
0
      return true;
714
0
    } // if
715
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
716
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
717
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
718
0
      (MI.getOperand(0).isReg()) &&
719
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
720
0
      (MI.getOperand(1).isReg()) &&
721
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
722
0
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) {
723
      // c.fswsp  $rs2, ${imm}(${rs1})
724
0
      OutInst.setOpcode(RISCV::C_FSWSP);
725
      // Operand: rs2
726
0
      OutInst.addOperand(MI.getOperand(0));
727
      // Operand: rs1
728
0
      OutInst.addOperand(MI.getOperand(1));
729
      // Operand: imm
730
0
      OutInst.addOperand(MI.getOperand(2));
731
0
      OutInst.setLoc(MI.getLoc());
732
0
      return true;
733
0
    } // if
734
0
      break;
735
0
    } // case FSW
736
59
    case RISCV::JAL: {
737
59
    if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
738
59
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
739
59
      (MI.getOperand(0).isReg()) &&
740
59
      (MI.getOperand(0).getReg() == RISCV::X1) &&
741
59
      RISCVValidateMCOperandForCompress(MI.getOperand(1), STI, 10)) {
742
      // c.jal  $offset
743
0
      OutInst.setOpcode(RISCV::C_JAL);
744
      // Operand: offset
745
0
      OutInst.addOperand(MI.getOperand(1));
746
0
      OutInst.setLoc(MI.getLoc());
747
0
      return true;
748
0
    } // if
749
59
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
750
59
      (MI.getOperand(0).isReg()) &&
751
59
      (MI.getOperand(0).getReg() == RISCV::X0) &&
752
59
      RISCVValidateMCOperandForCompress(MI.getOperand(1), STI, 10)) {
753
      // c.j  $offset
754
0
      OutInst.setOpcode(RISCV::C_J);
755
      // Operand: offset
756
0
      OutInst.addOperand(MI.getOperand(1));
757
0
      OutInst.setLoc(MI.getLoc());
758
0
      return true;
759
0
    } // if
760
59
      break;
761
59
    } // case JAL
762
6.16k
    case RISCV::JALR: {
763
6.16k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
764
6.16k
      (MI.getOperand(0).isReg()) &&
765
6.16k
      (MI.getOperand(0).getReg() == RISCV::X0) &&
766
6.16k
      (MI.getOperand(2).isImm()) &&
767
6.16k
      (MI.getOperand(2).getImm() == 0) &&
768
6.16k
      (MI.getOperand(1).isReg()) &&
769
6.16k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
770
      // c.jr $rs1
771
0
      OutInst.setOpcode(RISCV::C_JR);
772
      // Operand: rs1
773
0
      OutInst.addOperand(MI.getOperand(1));
774
0
      OutInst.setLoc(MI.getLoc());
775
0
      return true;
776
0
    } // if
777
6.16k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
778
6.16k
      (MI.getOperand(0).isReg()) &&
779
6.16k
      (MI.getOperand(0).getReg() == RISCV::X1) &&
780
6.16k
      (MI.getOperand(2).isImm()) &&
781
6.16k
      (MI.getOperand(2).getImm() == 0) &&
782
6.16k
      (MI.getOperand(1).isReg()) &&
783
6.16k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
784
      // c.jalr $rs1
785
0
      OutInst.setOpcode(RISCV::C_JALR);
786
      // Operand: rs1
787
0
      OutInst.addOperand(MI.getOperand(1));
788
0
      OutInst.setLoc(MI.getLoc());
789
0
      return true;
790
0
    } // if
791
6.16k
      break;
792
6.16k
    } // case JALR
793
14.4k
    case RISCV::LBU: {
794
14.4k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
795
14.4k
      (MI.getOperand(0).isReg()) &&
796
14.4k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
797
14.4k
      (MI.getOperand(1).isReg()) &&
798
14.4k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
799
14.4k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 11)) {
800
      // c.lbu  $rd, ${imm}(${rs1})
801
0
      OutInst.setOpcode(RISCV::C_LBU);
802
      // Operand: rd
803
0
      OutInst.addOperand(MI.getOperand(0));
804
      // Operand: rs1
805
0
      OutInst.addOperand(MI.getOperand(1));
806
      // Operand: imm
807
0
      OutInst.addOperand(MI.getOperand(2));
808
0
      OutInst.setLoc(MI.getLoc());
809
0
      return true;
810
0
    } // if
811
14.4k
      break;
812
14.4k
    } // case LBU
813
128k
    case RISCV::LD: {
814
128k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
815
128k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
816
128k
      (MI.getOperand(0).isReg()) &&
817
128k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
818
128k
      (MI.getOperand(1).isReg()) &&
819
128k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
820
128k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) {
821
      // c.ld $rd, ${imm}(${rs1})
822
0
      OutInst.setOpcode(RISCV::C_LD);
823
      // Operand: rd
824
0
      OutInst.addOperand(MI.getOperand(0));
825
      // Operand: rs1
826
0
      OutInst.addOperand(MI.getOperand(1));
827
      // Operand: imm
828
0
      OutInst.addOperand(MI.getOperand(2));
829
0
      OutInst.setLoc(MI.getLoc());
830
0
      return true;
831
0
    } // if
832
128k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
833
128k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
834
128k
      (MI.getOperand(0).isReg()) &&
835
128k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
836
128k
      (MI.getOperand(1).isReg()) &&
837
128k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
838
128k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) {
839
      // c.ldsp $rd, ${imm}(${rs1})
840
0
      OutInst.setOpcode(RISCV::C_LDSP);
841
      // Operand: rd
842
0
      OutInst.addOperand(MI.getOperand(0));
843
      // Operand: rs1
844
0
      OutInst.addOperand(MI.getOperand(1));
845
      // Operand: imm
846
0
      OutInst.addOperand(MI.getOperand(2));
847
0
      OutInst.setLoc(MI.getLoc());
848
0
      return true;
849
0
    } // if
850
128k
      break;
851
128k
    } // case LD
852
128k
    case RISCV::LH: {
853
6.18k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
854
6.18k
      (MI.getOperand(0).isReg()) &&
855
6.18k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
856
6.18k
      (MI.getOperand(1).isReg()) &&
857
6.18k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
858
6.18k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 12)) {
859
      // c.lh $rd, ${imm}(${rs1})
860
0
      OutInst.setOpcode(RISCV::C_LH);
861
      // Operand: rd
862
0
      OutInst.addOperand(MI.getOperand(0));
863
      // Operand: rs1
864
0
      OutInst.addOperand(MI.getOperand(1));
865
      // Operand: imm
866
0
      OutInst.addOperand(MI.getOperand(2));
867
0
      OutInst.setLoc(MI.getLoc());
868
0
      return true;
869
0
    } // if
870
6.18k
      break;
871
6.18k
    } // case LH
872
6.18k
    case RISCV::LHU: {
873
4.98k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
874
4.98k
      (MI.getOperand(0).isReg()) &&
875
4.98k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
876
4.98k
      (MI.getOperand(1).isReg()) &&
877
4.98k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
878
4.98k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 12)) {
879
      // c.lhu  $rd, ${imm}(${rs1})
880
0
      OutInst.setOpcode(RISCV::C_LHU);
881
      // Operand: rd
882
0
      OutInst.addOperand(MI.getOperand(0));
883
      // Operand: rs1
884
0
      OutInst.addOperand(MI.getOperand(1));
885
      // Operand: imm
886
0
      OutInst.addOperand(MI.getOperand(2));
887
0
      OutInst.setLoc(MI.getLoc());
888
0
      return true;
889
0
    } // if
890
4.98k
      break;
891
4.98k
    } // case LHU
892
79.0k
    case RISCV::LUI: {
893
79.0k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
894
79.0k
      (MI.getOperand(0).isReg()) &&
895
79.0k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(0).getReg())) &&
896
79.0k
      RISCVValidateMCOperandForCompress(MI.getOperand(1), STI, 13)) {
897
      // c.lui  $rd, $imm
898
0
      OutInst.setOpcode(RISCV::C_LUI);
899
      // Operand: rd
900
0
      OutInst.addOperand(MI.getOperand(0));
901
      // Operand: imm
902
0
      OutInst.addOperand(MI.getOperand(1));
903
0
      OutInst.setLoc(MI.getLoc());
904
0
      return true;
905
0
    } // if
906
79.0k
      break;
907
79.0k
    } // case LUI
908
79.0k
    case RISCV::LW: {
909
17.7k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
910
17.7k
      (MI.getOperand(0).isReg()) &&
911
17.7k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
912
17.7k
      (MI.getOperand(1).isReg()) &&
913
17.7k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
914
17.7k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) {
915
      // c.lw $rd, ${imm}(${rs1})
916
0
      OutInst.setOpcode(RISCV::C_LW);
917
      // Operand: rd
918
0
      OutInst.addOperand(MI.getOperand(0));
919
      // Operand: rs1
920
0
      OutInst.addOperand(MI.getOperand(1));
921
      // Operand: imm
922
0
      OutInst.addOperand(MI.getOperand(2));
923
0
      OutInst.setLoc(MI.getLoc());
924
0
      return true;
925
0
    } // if
926
17.7k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
927
17.7k
      (MI.getOperand(0).isReg()) &&
928
17.7k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
929
17.7k
      (MI.getOperand(1).isReg()) &&
930
17.7k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
931
17.7k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) {
932
      // c.lwsp $rd, ${imm}(${rs1})
933
0
      OutInst.setOpcode(RISCV::C_LWSP);
934
      // Operand: rd
935
0
      OutInst.addOperand(MI.getOperand(0));
936
      // Operand: rs1
937
0
      OutInst.addOperand(MI.getOperand(1));
938
      // Operand: imm
939
0
      OutInst.addOperand(MI.getOperand(2));
940
0
      OutInst.setLoc(MI.getLoc());
941
0
      return true;
942
0
    } // if
943
17.7k
      break;
944
17.7k
    } // case LW
945
17.7k
    case RISCV::MUL: {
946
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
947
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtM] || STI.getFeatureBits()[RISCV::FeatureStdExtZmmul]) &&
948
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
949
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
950
0
      (MI.getOperand(1).isReg()) &&
951
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
952
0
      (MI.getOperand(2).isReg()) &&
953
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
954
      // c.mul  $rd, $rs2
955
0
      OutInst.setOpcode(RISCV::C_MUL);
956
      // Operand: rd_wb
957
0
      OutInst.addOperand(MI.getOperand(1));
958
      // Operand: rd
959
0
      OutInst.addOperand(MI.getOperand(1));
960
      // Operand: rs2
961
0
      OutInst.addOperand(MI.getOperand(2));
962
0
      OutInst.setLoc(MI.getLoc());
963
0
      return true;
964
0
    } // if
965
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
966
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtM] || STI.getFeatureBits()[RISCV::FeatureStdExtZmmul]) &&
967
0
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
968
0
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
969
0
      (MI.getOperand(2).isReg()) &&
970
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
971
0
      (MI.getOperand(1).isReg()) &&
972
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
973
      // c.mul  $rd, $rs2
974
0
      OutInst.setOpcode(RISCV::C_MUL);
975
      // Operand: rd_wb
976
0
      OutInst.addOperand(MI.getOperand(2));
977
      // Operand: rd
978
0
      OutInst.addOperand(MI.getOperand(2));
979
      // Operand: rs2
980
0
      OutInst.addOperand(MI.getOperand(1));
981
0
      OutInst.setLoc(MI.getLoc());
982
0
      return true;
983
0
    } // if
984
0
      break;
985
0
    } // case MUL
986
13.2k
    case RISCV::OR: {
987
13.2k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
988
13.2k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
989
13.2k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
990
13.2k
      (MI.getOperand(1).isReg()) &&
991
13.2k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
992
13.2k
      (MI.getOperand(2).isReg()) &&
993
13.2k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
994
      // c.or $rd, $rs2
995
0
      OutInst.setOpcode(RISCV::C_OR);
996
      // Operand: rd_wb
997
0
      OutInst.addOperand(MI.getOperand(1));
998
      // Operand: rd
999
0
      OutInst.addOperand(MI.getOperand(1));
1000
      // Operand: rs2
1001
0
      OutInst.addOperand(MI.getOperand(2));
1002
0
      OutInst.setLoc(MI.getLoc());
1003
0
      return true;
1004
0
    } // if
1005
13.2k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1006
13.2k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
1007
13.2k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
1008
13.2k
      (MI.getOperand(2).isReg()) &&
1009
13.2k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
1010
13.2k
      (MI.getOperand(1).isReg()) &&
1011
13.2k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1012
      // c.or $rd, $rs2
1013
0
      OutInst.setOpcode(RISCV::C_OR);
1014
      // Operand: rd_wb
1015
0
      OutInst.addOperand(MI.getOperand(2));
1016
      // Operand: rd
1017
0
      OutInst.addOperand(MI.getOperand(2));
1018
      // Operand: rs2
1019
0
      OutInst.addOperand(MI.getOperand(1));
1020
0
      OutInst.setLoc(MI.getLoc());
1021
0
      return true;
1022
0
    } // if
1023
13.2k
      break;
1024
13.2k
    } // case OR
1025
70.7k
    case RISCV::SB: {
1026
70.7k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1027
70.7k
      (MI.getOperand(0).isReg()) &&
1028
70.7k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
1029
70.7k
      (MI.getOperand(1).isReg()) &&
1030
70.7k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1031
70.7k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 11)) {
1032
      // c.sb $rs2, ${imm}(${rs1})
1033
0
      OutInst.setOpcode(RISCV::C_SB);
1034
      // Operand: rs2
1035
0
      OutInst.addOperand(MI.getOperand(0));
1036
      // Operand: rs1
1037
0
      OutInst.addOperand(MI.getOperand(1));
1038
      // Operand: imm
1039
0
      OutInst.addOperand(MI.getOperand(2));
1040
0
      OutInst.setLoc(MI.getLoc());
1041
0
      return true;
1042
0
    } // if
1043
70.7k
      break;
1044
70.7k
    } // case SB
1045
136k
    case RISCV::SD: {
1046
136k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1047
136k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1048
136k
      (MI.getOperand(0).isReg()) &&
1049
136k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
1050
136k
      (MI.getOperand(1).isReg()) &&
1051
136k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1052
136k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 6)) {
1053
      // c.sd $rs2, ${imm}(${rs1})
1054
0
      OutInst.setOpcode(RISCV::C_SD);
1055
      // Operand: rs2
1056
0
      OutInst.addOperand(MI.getOperand(0));
1057
      // Operand: rs1
1058
0
      OutInst.addOperand(MI.getOperand(1));
1059
      // Operand: imm
1060
0
      OutInst.addOperand(MI.getOperand(2));
1061
0
      OutInst.setLoc(MI.getLoc());
1062
0
      return true;
1063
0
    } // if
1064
136k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1065
136k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1066
136k
      (MI.getOperand(0).isReg()) &&
1067
136k
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1068
136k
      (MI.getOperand(1).isReg()) &&
1069
136k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
1070
136k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 7)) {
1071
      // c.sdsp $rs2, ${imm}(${rs1})
1072
0
      OutInst.setOpcode(RISCV::C_SDSP);
1073
      // Operand: rs2
1074
0
      OutInst.addOperand(MI.getOperand(0));
1075
      // Operand: rs1
1076
0
      OutInst.addOperand(MI.getOperand(1));
1077
      // Operand: imm
1078
0
      OutInst.addOperand(MI.getOperand(2));
1079
0
      OutInst.setLoc(MI.getLoc());
1080
0
      return true;
1081
0
    } // if
1082
136k
      break;
1083
136k
    } // case SD
1084
136k
    case RISCV::SEXT_B: {
1085
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1086
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1087
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1088
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1089
0
      (MI.getOperand(1).isReg()) &&
1090
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1091
      // c.sext.b $rd
1092
0
      OutInst.setOpcode(RISCV::C_SEXT_B);
1093
      // Operand: rd_wb
1094
0
      OutInst.addOperand(MI.getOperand(1));
1095
      // Operand: rd
1096
0
      OutInst.addOperand(MI.getOperand(1));
1097
0
      OutInst.setLoc(MI.getLoc());
1098
0
      return true;
1099
0
    } // if
1100
0
      break;
1101
0
    } // case SEXT_B
1102
0
    case RISCV::SEXT_H: {
1103
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1104
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1105
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1106
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1107
0
      (MI.getOperand(1).isReg()) &&
1108
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1109
      // c.sext.h $rd
1110
0
      OutInst.setOpcode(RISCV::C_SEXT_H);
1111
      // Operand: rd_wb
1112
0
      OutInst.addOperand(MI.getOperand(1));
1113
      // Operand: rd
1114
0
      OutInst.addOperand(MI.getOperand(1));
1115
0
      OutInst.setLoc(MI.getLoc());
1116
0
      return true;
1117
0
    } // if
1118
0
      break;
1119
0
    } // case SEXT_H
1120
7.80k
    case RISCV::SH: {
1121
7.80k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1122
7.80k
      (MI.getOperand(0).isReg()) &&
1123
7.80k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
1124
7.80k
      (MI.getOperand(1).isReg()) &&
1125
7.80k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1126
7.80k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 12)) {
1127
      // c.sh $rs2, ${imm}(${rs1})
1128
0
      OutInst.setOpcode(RISCV::C_SH);
1129
      // Operand: rs2
1130
0
      OutInst.addOperand(MI.getOperand(0));
1131
      // Operand: rs1
1132
0
      OutInst.addOperand(MI.getOperand(1));
1133
      // Operand: imm
1134
0
      OutInst.addOperand(MI.getOperand(2));
1135
0
      OutInst.setLoc(MI.getLoc());
1136
0
      return true;
1137
0
    } // if
1138
7.80k
      break;
1139
7.80k
    } // case SH
1140
25.4k
    case RISCV::SLLI: {
1141
25.4k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1142
25.4k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1143
25.4k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1144
25.4k
      (MI.getOperand(1).isReg()) &&
1145
25.4k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
1146
25.4k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 14)) {
1147
      // c.slli $rd, $imm
1148
0
      OutInst.setOpcode(RISCV::C_SLLI);
1149
      // Operand: rd_wb
1150
0
      OutInst.addOperand(MI.getOperand(1));
1151
      // Operand: rd
1152
0
      OutInst.addOperand(MI.getOperand(1));
1153
      // Operand: imm
1154
0
      OutInst.addOperand(MI.getOperand(2));
1155
0
      OutInst.setLoc(MI.getLoc());
1156
0
      return true;
1157
0
    } // if
1158
25.4k
      break;
1159
25.4k
    } // case SLLI
1160
25.4k
    case RISCV::SRAI: {
1161
4.38k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1162
4.38k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1163
4.38k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1164
4.38k
      (MI.getOperand(1).isReg()) &&
1165
4.38k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1166
4.38k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 14)) {
1167
      // c.srai $rs1, $imm
1168
0
      OutInst.setOpcode(RISCV::C_SRAI);
1169
      // Operand: rs1_wb
1170
0
      OutInst.addOperand(MI.getOperand(1));
1171
      // Operand: rs1
1172
0
      OutInst.addOperand(MI.getOperand(1));
1173
      // Operand: imm
1174
0
      OutInst.addOperand(MI.getOperand(2));
1175
0
      OutInst.setLoc(MI.getLoc());
1176
0
      return true;
1177
0
    } // if
1178
4.38k
      break;
1179
4.38k
    } // case SRAI
1180
6.99k
    case RISCV::SRLI: {
1181
6.99k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1182
6.99k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1183
6.99k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1184
6.99k
      (MI.getOperand(1).isReg()) &&
1185
6.99k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1186
6.99k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 14)) {
1187
      // c.srli $rs1, $imm
1188
0
      OutInst.setOpcode(RISCV::C_SRLI);
1189
      // Operand: rs1_wb
1190
0
      OutInst.addOperand(MI.getOperand(1));
1191
      // Operand: rs1
1192
0
      OutInst.addOperand(MI.getOperand(1));
1193
      // Operand: imm
1194
0
      OutInst.addOperand(MI.getOperand(2));
1195
0
      OutInst.setLoc(MI.getLoc());
1196
0
      return true;
1197
0
    } // if
1198
6.99k
      break;
1199
6.99k
    } // case SRLI
1200
6.99k
    case RISCV::SSPOPCHK: {
1201
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
1202
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
1203
0
      (MI.getOperand(0).isReg()) &&
1204
0
      (MI.getOperand(0).getReg() == RISCV::X5)) {
1205
      // c.sspopchk $rs1
1206
0
      OutInst.setOpcode(RISCV::C_SSPOPCHK);
1207
      // Operand: rs1
1208
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X5));
1209
0
      OutInst.setLoc(MI.getLoc());
1210
0
      return true;
1211
0
    } // if
1212
0
      break;
1213
0
    } // case SSPOPCHK
1214
0
    case RISCV::SSPUSH: {
1215
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
1216
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
1217
0
      (MI.getOperand(0).isReg()) &&
1218
0
      (MI.getOperand(0).getReg() == RISCV::X1)) {
1219
      // c.sspush $rs1
1220
0
      OutInst.setOpcode(RISCV::C_SSPUSH);
1221
      // Operand: rs1
1222
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X1));
1223
0
      OutInst.setLoc(MI.getLoc());
1224
0
      return true;
1225
0
    } // if
1226
0
      break;
1227
0
    } // case SSPUSH
1228
6.16k
    case RISCV::SUB: {
1229
6.16k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1230
6.16k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1231
6.16k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1232
6.16k
      (MI.getOperand(1).isReg()) &&
1233
6.16k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1234
6.16k
      (MI.getOperand(2).isReg()) &&
1235
6.16k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
1236
      // c.sub  $rd, $rs2
1237
0
      OutInst.setOpcode(RISCV::C_SUB);
1238
      // Operand: rd_wb
1239
0
      OutInst.addOperand(MI.getOperand(1));
1240
      // Operand: rd
1241
0
      OutInst.addOperand(MI.getOperand(1));
1242
      // Operand: rs2
1243
0
      OutInst.addOperand(MI.getOperand(2));
1244
0
      OutInst.setLoc(MI.getLoc());
1245
0
      return true;
1246
0
    } // if
1247
6.16k
      break;
1248
6.16k
    } // case SUB
1249
6.16k
    case RISCV::SUBW: {
1250
2.75k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1251
2.75k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1252
2.75k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1253
2.75k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1254
2.75k
      (MI.getOperand(1).isReg()) &&
1255
2.75k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1256
2.75k
      (MI.getOperand(2).isReg()) &&
1257
2.75k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
1258
      // c.subw $rd, $rs2
1259
0
      OutInst.setOpcode(RISCV::C_SUBW);
1260
      // Operand: rd_wb
1261
0
      OutInst.addOperand(MI.getOperand(1));
1262
      // Operand: rd
1263
0
      OutInst.addOperand(MI.getOperand(1));
1264
      // Operand: rs2
1265
0
      OutInst.addOperand(MI.getOperand(2));
1266
0
      OutInst.setLoc(MI.getLoc());
1267
0
      return true;
1268
0
    } // if
1269
2.75k
      break;
1270
2.75k
    } // case SUBW
1271
22.6k
    case RISCV::SW: {
1272
22.6k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1273
22.6k
      (MI.getOperand(0).isReg()) &&
1274
22.6k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
1275
22.6k
      (MI.getOperand(1).isReg()) &&
1276
22.6k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1277
22.6k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 8)) {
1278
      // c.sw $rs2, ${imm}(${rs1})
1279
0
      OutInst.setOpcode(RISCV::C_SW);
1280
      // Operand: rs2
1281
0
      OutInst.addOperand(MI.getOperand(0));
1282
      // Operand: rs1
1283
0
      OutInst.addOperand(MI.getOperand(1));
1284
      // Operand: imm
1285
0
      OutInst.addOperand(MI.getOperand(2));
1286
0
      OutInst.setLoc(MI.getLoc());
1287
0
      return true;
1288
0
    } // if
1289
22.6k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1290
22.6k
      (MI.getOperand(0).isReg()) &&
1291
22.6k
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1292
22.6k
      (MI.getOperand(1).isReg()) &&
1293
22.6k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
1294
22.6k
      RISCVValidateMCOperandForCompress(MI.getOperand(2), STI, 9)) {
1295
      // c.swsp $rs2, ${imm}(${rs1})
1296
0
      OutInst.setOpcode(RISCV::C_SWSP);
1297
      // Operand: rs2
1298
0
      OutInst.addOperand(MI.getOperand(0));
1299
      // Operand: rs1
1300
0
      OutInst.addOperand(MI.getOperand(1));
1301
      // Operand: imm
1302
0
      OutInst.addOperand(MI.getOperand(2));
1303
0
      OutInst.setLoc(MI.getLoc());
1304
0
      return true;
1305
0
    } // if
1306
22.6k
      break;
1307
22.6k
    } // case SW
1308
22.6k
    case RISCV::UNIMP: {
1309
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
1310
      // c.unimp
1311
0
      OutInst.setOpcode(RISCV::C_UNIMP);
1312
0
      OutInst.setLoc(MI.getLoc());
1313
0
      return true;
1314
0
    } // if
1315
0
      break;
1316
0
    } // case UNIMP
1317
6.87k
    case RISCV::XOR: {
1318
6.87k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1319
6.87k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1320
6.87k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1321
6.87k
      (MI.getOperand(1).isReg()) &&
1322
6.87k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
1323
6.87k
      (MI.getOperand(2).isReg()) &&
1324
6.87k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
1325
      // c.xor  $rd, $rs2
1326
0
      OutInst.setOpcode(RISCV::C_XOR);
1327
      // Operand: rd_wb
1328
0
      OutInst.addOperand(MI.getOperand(1));
1329
      // Operand: rd
1330
0
      OutInst.addOperand(MI.getOperand(1));
1331
      // Operand: rs2
1332
0
      OutInst.addOperand(MI.getOperand(2));
1333
0
      OutInst.setLoc(MI.getLoc());
1334
0
      return true;
1335
0
    } // if
1336
6.87k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1337
6.87k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
1338
6.87k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
1339
6.87k
      (MI.getOperand(2).isReg()) &&
1340
6.87k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
1341
6.87k
      (MI.getOperand(1).isReg()) &&
1342
6.87k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1343
      // c.xor  $rd, $rs2
1344
0
      OutInst.setOpcode(RISCV::C_XOR);
1345
      // Operand: rd_wb
1346
0
      OutInst.addOperand(MI.getOperand(2));
1347
      // Operand: rd
1348
0
      OutInst.addOperand(MI.getOperand(2));
1349
      // Operand: rs2
1350
0
      OutInst.addOperand(MI.getOperand(1));
1351
0
      OutInst.setLoc(MI.getLoc());
1352
0
      return true;
1353
0
    } // if
1354
6.87k
      break;
1355
6.87k
    } // case XOR
1356
14.7k
    case RISCV::XORI: {
1357
14.7k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1358
14.7k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1359
14.7k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1360
14.7k
      (MI.getOperand(2).isImm()) &&
1361
14.7k
      (MI.getOperand(2).getImm() == -1) &&
1362
14.7k
      (MI.getOperand(1).isReg()) &&
1363
14.7k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1364
      // c.not  $rd
1365
0
      OutInst.setOpcode(RISCV::C_NOT);
1366
      // Operand: rd_wb
1367
0
      OutInst.addOperand(MI.getOperand(1));
1368
      // Operand: rd
1369
0
      OutInst.addOperand(MI.getOperand(1));
1370
0
      OutInst.setLoc(MI.getLoc());
1371
0
      return true;
1372
0
    } // if
1373
14.7k
      break;
1374
14.7k
    } // case XORI
1375
14.7k
    case RISCV::ZEXT_H_RV32: {
1376
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1377
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1378
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1379
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1380
0
      (MI.getOperand(1).isReg()) &&
1381
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1382
      // c.zext.h $rd
1383
0
      OutInst.setOpcode(RISCV::C_ZEXT_H);
1384
      // Operand: rd_wb
1385
0
      OutInst.addOperand(MI.getOperand(1));
1386
      // Operand: rd
1387
0
      OutInst.addOperand(MI.getOperand(1));
1388
0
      OutInst.setLoc(MI.getLoc());
1389
0
      return true;
1390
0
    } // if
1391
0
      break;
1392
0
    } // case ZEXT_H_RV32
1393
0
    case RISCV::ZEXT_H_RV64: {
1394
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
1395
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1396
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
1397
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
1398
0
      (MI.getOperand(1).isReg()) &&
1399
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
1400
      // c.zext.h $rd
1401
0
      OutInst.setOpcode(RISCV::C_ZEXT_H);
1402
      // Operand: rd_wb
1403
0
      OutInst.addOperand(MI.getOperand(1));
1404
      // Operand: rd
1405
0
      OutInst.addOperand(MI.getOperand(1));
1406
0
      OutInst.setLoc(MI.getLoc());
1407
0
      return true;
1408
0
    } // if
1409
1410
0
    } // case ZEXT_H_RV64
1411
860k
  } // switch
1412
759k
  return false;
1413
860k
}
1414
1415
#endif //GEN_COMPRESS_INSTR
1416
1417
#ifdef GEN_UNCOMPRESS_INSTR
1418
#undef GEN_UNCOMPRESS_INSTR
1419
1420
static bool RISCVValidateMCOperandForUncompress(const MCOperand &MCOp,
1421
                  const MCSubtargetInfo &STI,
1422
0
                  unsigned PredicateIndex) {
1423
0
  switch (PredicateIndex) {
1424
0
  default:
1425
0
    llvm_unreachable("Unknown MCOperandPredicate kind");
1426
0
    break;
1427
0
  case 1: {
1428
  // simm12
1429
  
1430
0
    int64_t Imm;
1431
0
    if (MCOp.evaluateAsConstantImm(Imm))
1432
0
      return isInt<12>(Imm);
1433
0
    return MCOp.isBareSymbolRef();
1434
  
1435
0
  }
1436
0
  case 2: {
1437
  // simm13_lsb0
1438
  
1439
0
    int64_t Imm;
1440
0
    if (MCOp.evaluateAsConstantImm(Imm))
1441
0
      return isShiftedInt<12, 1>(Imm);
1442
0
    return MCOp.isBareSymbolRef();
1443
  
1444
0
  }
1445
0
  case 3: {
1446
  // simm21_lsb0_jal
1447
  
1448
0
    int64_t Imm;
1449
0
    if (MCOp.evaluateAsConstantImm(Imm))
1450
0
      return isShiftedInt<20, 1>(Imm);
1451
0
    return MCOp.isBareSymbolRef();
1452
  
1453
0
  }
1454
0
  case 4: {
1455
  // uimm20_lui
1456
  
1457
0
    int64_t Imm;
1458
0
    if (MCOp.evaluateAsConstantImm(Imm))
1459
0
      return isUInt<20>(Imm);
1460
0
    return MCOp.isBareSymbolRef();
1461
  
1462
0
  }
1463
0
  case 5: {
1464
  // uimmlog2xlen
1465
  
1466
0
    int64_t Imm;
1467
0
    if (!MCOp.evaluateAsConstantImm(Imm))
1468
0
      return false;
1469
0
    if (STI.getTargetTriple().isArch64Bit())
1470
0
      return isUInt<6>(Imm);
1471
0
    return isUInt<5>(Imm);
1472
  
1473
0
  }
1474
0
  }
1475
0
}
1476
1477
static bool uncompressInst(MCInst &OutInst,
1478
                           const MCInst &MI,
1479
0
                           const MCSubtargetInfo &STI) {
1480
0
  switch (MI.getOpcode()) {
1481
0
    default: return false;
1482
0
    case RISCV::C_ADD: {
1483
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1484
0
      (MI.getOperand(0).isReg()) &&
1485
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1486
0
      (MI.getOperand(0).isReg()) &&
1487
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1488
0
      (MI.getOperand(2).isReg()) &&
1489
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
1490
      // add  $rd, $rs1, $rs2
1491
0
      OutInst.setOpcode(RISCV::ADD);
1492
      // Operand: rd
1493
0
      OutInst.addOperand(MI.getOperand(0));
1494
      // Operand: rs1
1495
0
      OutInst.addOperand(MI.getOperand(0));
1496
      // Operand: rs2
1497
0
      OutInst.addOperand(MI.getOperand(2));
1498
0
      OutInst.setLoc(MI.getLoc());
1499
0
      return true;
1500
0
    } // if
1501
0
      break;
1502
0
    } // case C_ADD
1503
0
    case RISCV::C_ADDI: {
1504
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1505
0
      (MI.getOperand(0).isReg()) &&
1506
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1507
0
      (MI.getOperand(0).isReg()) &&
1508
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1509
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1510
      // addi $rd, $rs1, $imm12
1511
0
      OutInst.setOpcode(RISCV::ADDI);
1512
      // Operand: rd
1513
0
      OutInst.addOperand(MI.getOperand(0));
1514
      // Operand: rs1
1515
0
      OutInst.addOperand(MI.getOperand(0));
1516
      // Operand: imm12
1517
0
      OutInst.addOperand(MI.getOperand(2));
1518
0
      OutInst.setLoc(MI.getLoc());
1519
0
      return true;
1520
0
    } // if
1521
0
      break;
1522
0
    } // case C_ADDI
1523
0
    case RISCV::C_ADDI16SP: {
1524
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1525
0
      (MI.getOperand(0).isReg()) &&
1526
0
      (MI.getOperand(0).getReg() == RISCV::X2) &&
1527
0
      (MI.getOperand(1).isReg()) &&
1528
0
      (MI.getOperand(1).getReg() == RISCV::X2) &&
1529
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1530
      // addi $rd, $rs1, $imm12
1531
0
      OutInst.setOpcode(RISCV::ADDI);
1532
      // Operand: rd
1533
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X2));
1534
      // Operand: rs1
1535
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X2));
1536
      // Operand: imm12
1537
0
      OutInst.addOperand(MI.getOperand(2));
1538
0
      OutInst.setLoc(MI.getLoc());
1539
0
      return true;
1540
0
    } // if
1541
0
      break;
1542
0
    } // case C_ADDI16SP
1543
0
    case RISCV::C_ADDI4SPN: {
1544
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1545
0
      (MI.getOperand(0).isReg()) &&
1546
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1547
0
      (MI.getOperand(1).isReg()) &&
1548
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1549
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1550
      // addi $rd, $rs1, $imm12
1551
0
      OutInst.setOpcode(RISCV::ADDI);
1552
      // Operand: rd
1553
0
      OutInst.addOperand(MI.getOperand(0));
1554
      // Operand: rs1
1555
0
      OutInst.addOperand(MI.getOperand(1));
1556
      // Operand: imm12
1557
0
      OutInst.addOperand(MI.getOperand(2));
1558
0
      OutInst.setLoc(MI.getLoc());
1559
0
      return true;
1560
0
    } // if
1561
0
      break;
1562
0
    } // case C_ADDI4SPN
1563
0
    case RISCV::C_ADDIW: {
1564
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1565
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1566
0
      (MI.getOperand(0).isReg()) &&
1567
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1568
0
      (MI.getOperand(0).isReg()) &&
1569
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1570
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1571
      // addiw  $rd, $rs1, $imm12
1572
0
      OutInst.setOpcode(RISCV::ADDIW);
1573
      // Operand: rd
1574
0
      OutInst.addOperand(MI.getOperand(0));
1575
      // Operand: rs1
1576
0
      OutInst.addOperand(MI.getOperand(0));
1577
      // Operand: imm12
1578
0
      OutInst.addOperand(MI.getOperand(2));
1579
0
      OutInst.setLoc(MI.getLoc());
1580
0
      return true;
1581
0
    } // if
1582
0
      break;
1583
0
    } // case C_ADDIW
1584
0
    case RISCV::C_ADDW: {
1585
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1586
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1587
0
      (MI.getOperand(0).isReg()) &&
1588
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1589
0
      (MI.getOperand(0).isReg()) &&
1590
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1591
0
      (MI.getOperand(2).isReg()) &&
1592
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
1593
      // addw $rd, $rs1, $rs2
1594
0
      OutInst.setOpcode(RISCV::ADDW);
1595
      // Operand: rd
1596
0
      OutInst.addOperand(MI.getOperand(0));
1597
      // Operand: rs1
1598
0
      OutInst.addOperand(MI.getOperand(0));
1599
      // Operand: rs2
1600
0
      OutInst.addOperand(MI.getOperand(2));
1601
0
      OutInst.setLoc(MI.getLoc());
1602
0
      return true;
1603
0
    } // if
1604
0
      break;
1605
0
    } // case C_ADDW
1606
0
    case RISCV::C_AND: {
1607
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1608
0
      (MI.getOperand(0).isReg()) &&
1609
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1610
0
      (MI.getOperand(0).isReg()) &&
1611
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1612
0
      (MI.getOperand(2).isReg()) &&
1613
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
1614
      // and  $rd, $rs1, $rs2
1615
0
      OutInst.setOpcode(RISCV::AND);
1616
      // Operand: rd
1617
0
      OutInst.addOperand(MI.getOperand(0));
1618
      // Operand: rs1
1619
0
      OutInst.addOperand(MI.getOperand(0));
1620
      // Operand: rs2
1621
0
      OutInst.addOperand(MI.getOperand(2));
1622
0
      OutInst.setLoc(MI.getLoc());
1623
0
      return true;
1624
0
    } // if
1625
0
      break;
1626
0
    } // case C_AND
1627
0
    case RISCV::C_ANDI: {
1628
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1629
0
      (MI.getOperand(0).isReg()) &&
1630
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1631
0
      (MI.getOperand(0).isReg()) &&
1632
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1633
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1634
      // andi $rd, $rs1, $imm12
1635
0
      OutInst.setOpcode(RISCV::ANDI);
1636
      // Operand: rd
1637
0
      OutInst.addOperand(MI.getOperand(0));
1638
      // Operand: rs1
1639
0
      OutInst.addOperand(MI.getOperand(0));
1640
      // Operand: imm12
1641
0
      OutInst.addOperand(MI.getOperand(2));
1642
0
      OutInst.setLoc(MI.getLoc());
1643
0
      return true;
1644
0
    } // if
1645
0
      break;
1646
0
    } // case C_ANDI
1647
0
    case RISCV::C_BEQZ: {
1648
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1649
0
      (MI.getOperand(0).isReg()) &&
1650
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1651
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 2)) {
1652
      // beq  $rs1, $rs2, $imm12
1653
0
      OutInst.setOpcode(RISCV::BEQ);
1654
      // Operand: rs1
1655
0
      OutInst.addOperand(MI.getOperand(0));
1656
      // Operand: rs2
1657
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
1658
      // Operand: imm12
1659
0
      OutInst.addOperand(MI.getOperand(1));
1660
0
      OutInst.setLoc(MI.getLoc());
1661
0
      return true;
1662
0
    } // if
1663
0
      break;
1664
0
    } // case C_BEQZ
1665
0
    case RISCV::C_BNEZ: {
1666
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1667
0
      (MI.getOperand(0).isReg()) &&
1668
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1669
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 2)) {
1670
      // bne  $rs1, $rs2, $imm12
1671
0
      OutInst.setOpcode(RISCV::BNE);
1672
      // Operand: rs1
1673
0
      OutInst.addOperand(MI.getOperand(0));
1674
      // Operand: rs2
1675
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
1676
      // Operand: imm12
1677
0
      OutInst.addOperand(MI.getOperand(1));
1678
0
      OutInst.setLoc(MI.getLoc());
1679
0
      return true;
1680
0
    } // if
1681
0
      break;
1682
0
    } // case C_BNEZ
1683
0
    case RISCV::C_EBREAK: {
1684
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
1685
      // ebreak
1686
0
      OutInst.setOpcode(RISCV::EBREAK);
1687
0
      OutInst.setLoc(MI.getLoc());
1688
0
      return true;
1689
0
    } // if
1690
0
      break;
1691
0
    } // case C_EBREAK
1692
0
    case RISCV::C_FLD: {
1693
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1694
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1695
0
      (MI.getOperand(0).isReg()) &&
1696
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
1697
0
      (MI.getOperand(1).isReg()) &&
1698
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1699
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1700
      // fld  $rd, ${imm12}(${rs1})
1701
0
      OutInst.setOpcode(RISCV::FLD);
1702
      // Operand: rd
1703
0
      OutInst.addOperand(MI.getOperand(0));
1704
      // Operand: rs1
1705
0
      OutInst.addOperand(MI.getOperand(1));
1706
      // Operand: imm12
1707
0
      OutInst.addOperand(MI.getOperand(2));
1708
0
      OutInst.setLoc(MI.getLoc());
1709
0
      return true;
1710
0
    } // if
1711
0
      break;
1712
0
    } // case C_FLD
1713
0
    case RISCV::C_FLDSP: {
1714
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1715
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1716
0
      (MI.getOperand(0).isReg()) &&
1717
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
1718
0
      (MI.getOperand(1).isReg()) &&
1719
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1720
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1721
      // fld  $rd, ${imm12}(${rs1})
1722
0
      OutInst.setOpcode(RISCV::FLD);
1723
      // Operand: rd
1724
0
      OutInst.addOperand(MI.getOperand(0));
1725
      // Operand: rs1
1726
0
      OutInst.addOperand(MI.getOperand(1));
1727
      // Operand: imm12
1728
0
      OutInst.addOperand(MI.getOperand(2));
1729
0
      OutInst.setLoc(MI.getLoc());
1730
0
      return true;
1731
0
    } // if
1732
0
      break;
1733
0
    } // case C_FLDSP
1734
0
    case RISCV::C_FLW: {
1735
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1736
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1737
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1738
0
      (MI.getOperand(0).isReg()) &&
1739
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
1740
0
      (MI.getOperand(1).isReg()) &&
1741
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1742
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1743
      // flw  $rd, ${imm12}(${rs1})
1744
0
      OutInst.setOpcode(RISCV::FLW);
1745
      // Operand: rd
1746
0
      OutInst.addOperand(MI.getOperand(0));
1747
      // Operand: rs1
1748
0
      OutInst.addOperand(MI.getOperand(1));
1749
      // Operand: imm12
1750
0
      OutInst.addOperand(MI.getOperand(2));
1751
0
      OutInst.setLoc(MI.getLoc());
1752
0
      return true;
1753
0
    } // if
1754
0
      break;
1755
0
    } // case C_FLW
1756
0
    case RISCV::C_FLWSP: {
1757
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1758
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1759
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1760
0
      (MI.getOperand(0).isReg()) &&
1761
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
1762
0
      (MI.getOperand(1).isReg()) &&
1763
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1764
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1765
      // flw  $rd, ${imm12}(${rs1})
1766
0
      OutInst.setOpcode(RISCV::FLW);
1767
      // Operand: rd
1768
0
      OutInst.addOperand(MI.getOperand(0));
1769
      // Operand: rs1
1770
0
      OutInst.addOperand(MI.getOperand(1));
1771
      // Operand: imm12
1772
0
      OutInst.addOperand(MI.getOperand(2));
1773
0
      OutInst.setLoc(MI.getLoc());
1774
0
      return true;
1775
0
    } // if
1776
0
      break;
1777
0
    } // case C_FLWSP
1778
0
    case RISCV::C_FSD: {
1779
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1780
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1781
0
      (MI.getOperand(0).isReg()) &&
1782
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
1783
0
      (MI.getOperand(1).isReg()) &&
1784
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1785
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1786
      // fsd  $rs2, ${imm12}(${rs1})
1787
0
      OutInst.setOpcode(RISCV::FSD);
1788
      // Operand: rs2
1789
0
      OutInst.addOperand(MI.getOperand(0));
1790
      // Operand: rs1
1791
0
      OutInst.addOperand(MI.getOperand(1));
1792
      // Operand: imm12
1793
0
      OutInst.addOperand(MI.getOperand(2));
1794
0
      OutInst.setLoc(MI.getLoc());
1795
0
      return true;
1796
0
    } // if
1797
0
      break;
1798
0
    } // case C_FSD
1799
0
    case RISCV::C_FSDSP: {
1800
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
1801
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
1802
0
      (MI.getOperand(0).isReg()) &&
1803
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
1804
0
      (MI.getOperand(1).isReg()) &&
1805
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1806
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1807
      // fsd  $rs2, ${imm12}(${rs1})
1808
0
      OutInst.setOpcode(RISCV::FSD);
1809
      // Operand: rs2
1810
0
      OutInst.addOperand(MI.getOperand(0));
1811
      // Operand: rs1
1812
0
      OutInst.addOperand(MI.getOperand(1));
1813
      // Operand: imm12
1814
0
      OutInst.addOperand(MI.getOperand(2));
1815
0
      OutInst.setLoc(MI.getLoc());
1816
0
      return true;
1817
0
    } // if
1818
0
      break;
1819
0
    } // case C_FSDSP
1820
0
    case RISCV::C_FSW: {
1821
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1822
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1823
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1824
0
      (MI.getOperand(0).isReg()) &&
1825
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
1826
0
      (MI.getOperand(1).isReg()) &&
1827
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1828
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1829
      // fsw  $rs2, ${imm12}(${rs1})
1830
0
      OutInst.setOpcode(RISCV::FSW);
1831
      // Operand: rs2
1832
0
      OutInst.addOperand(MI.getOperand(0));
1833
      // Operand: rs1
1834
0
      OutInst.addOperand(MI.getOperand(1));
1835
      // Operand: imm12
1836
0
      OutInst.addOperand(MI.getOperand(2));
1837
0
      OutInst.setLoc(MI.getLoc());
1838
0
      return true;
1839
0
    } // if
1840
0
      break;
1841
0
    } // case C_FSW
1842
0
    case RISCV::C_FSWSP: {
1843
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
1844
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
1845
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
1846
0
      (MI.getOperand(0).isReg()) &&
1847
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
1848
0
      (MI.getOperand(1).isReg()) &&
1849
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1850
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1851
      // fsw  $rs2, ${imm12}(${rs1})
1852
0
      OutInst.setOpcode(RISCV::FSW);
1853
      // Operand: rs2
1854
0
      OutInst.addOperand(MI.getOperand(0));
1855
      // Operand: rs1
1856
0
      OutInst.addOperand(MI.getOperand(1));
1857
      // Operand: imm12
1858
0
      OutInst.addOperand(MI.getOperand(2));
1859
0
      OutInst.setLoc(MI.getLoc());
1860
0
      return true;
1861
0
    } // if
1862
0
      break;
1863
0
    } // case C_FSWSP
1864
0
    case RISCV::C_J: {
1865
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1866
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(0), STI, 3)) {
1867
      // jal  $rd, $imm20
1868
0
      OutInst.setOpcode(RISCV::JAL);
1869
      // Operand: rd
1870
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
1871
      // Operand: imm20
1872
0
      OutInst.addOperand(MI.getOperand(0));
1873
0
      OutInst.setLoc(MI.getLoc());
1874
0
      return true;
1875
0
    } // if
1876
0
      break;
1877
0
    } // case C_J
1878
0
    case RISCV::C_JAL: {
1879
0
    if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
1880
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1881
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(0), STI, 3)) {
1882
      // jal  $rd, $imm20
1883
0
      OutInst.setOpcode(RISCV::JAL);
1884
      // Operand: rd
1885
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X1));
1886
      // Operand: imm20
1887
0
      OutInst.addOperand(MI.getOperand(0));
1888
0
      OutInst.setLoc(MI.getLoc());
1889
0
      return true;
1890
0
    } // if
1891
0
      break;
1892
0
    } // case C_JAL
1893
0
    case RISCV::C_JALR: {
1894
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1895
0
      (MI.getOperand(0).isReg()) &&
1896
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1897
0
      RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) {
1898
      // jalr $rd, ${imm12}(${rs1})
1899
0
      OutInst.setOpcode(RISCV::JALR);
1900
      // Operand: rd
1901
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X1));
1902
      // Operand: rs1
1903
0
      OutInst.addOperand(MI.getOperand(0));
1904
      // Operand: imm12
1905
0
      OutInst.addOperand(MCOperand::createImm(0));
1906
0
      OutInst.setLoc(MI.getLoc());
1907
0
      return true;
1908
0
    } // if
1909
0
      break;
1910
0
    } // case C_JALR
1911
0
    case RISCV::C_JR: {
1912
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1913
0
      (MI.getOperand(0).isReg()) &&
1914
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1915
0
      RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) {
1916
      // jalr $rd, ${imm12}(${rs1})
1917
0
      OutInst.setOpcode(RISCV::JALR);
1918
      // Operand: rd
1919
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
1920
      // Operand: rs1
1921
0
      OutInst.addOperand(MI.getOperand(0));
1922
      // Operand: imm12
1923
0
      OutInst.addOperand(MCOperand::createImm(0));
1924
0
      OutInst.setLoc(MI.getLoc());
1925
0
      return true;
1926
0
    } // if
1927
0
      break;
1928
0
    } // case C_JR
1929
0
    case RISCV::C_LBU: {
1930
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1931
0
      (MI.getOperand(0).isReg()) &&
1932
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1933
0
      (MI.getOperand(1).isReg()) &&
1934
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1935
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1936
      // lbu  $rd, ${imm12}(${rs1})
1937
0
      OutInst.setOpcode(RISCV::LBU);
1938
      // Operand: rd
1939
0
      OutInst.addOperand(MI.getOperand(0));
1940
      // Operand: rs1
1941
0
      OutInst.addOperand(MI.getOperand(1));
1942
      // Operand: imm12
1943
0
      OutInst.addOperand(MI.getOperand(2));
1944
0
      OutInst.setLoc(MI.getLoc());
1945
0
      return true;
1946
0
    } // if
1947
0
      break;
1948
0
    } // case C_LBU
1949
0
    case RISCV::C_LD: {
1950
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1951
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1952
0
      (MI.getOperand(0).isReg()) &&
1953
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1954
0
      (MI.getOperand(1).isReg()) &&
1955
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1956
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1957
      // ld $rd, ${imm12}(${rs1})
1958
0
      OutInst.setOpcode(RISCV::LD);
1959
      // Operand: rd
1960
0
      OutInst.addOperand(MI.getOperand(0));
1961
      // Operand: rs1
1962
0
      OutInst.addOperand(MI.getOperand(1));
1963
      // Operand: imm12
1964
0
      OutInst.addOperand(MI.getOperand(2));
1965
0
      OutInst.setLoc(MI.getLoc());
1966
0
      return true;
1967
0
    } // if
1968
0
      break;
1969
0
    } // case C_LD
1970
0
    case RISCV::C_LDSP: {
1971
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
1972
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
1973
0
      (MI.getOperand(0).isReg()) &&
1974
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1975
0
      (MI.getOperand(1).isReg()) &&
1976
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1977
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1978
      // ld $rd, ${imm12}(${rs1})
1979
0
      OutInst.setOpcode(RISCV::LD);
1980
      // Operand: rd
1981
0
      OutInst.addOperand(MI.getOperand(0));
1982
      // Operand: rs1
1983
0
      OutInst.addOperand(MI.getOperand(1));
1984
      // Operand: imm12
1985
0
      OutInst.addOperand(MI.getOperand(2));
1986
0
      OutInst.setLoc(MI.getLoc());
1987
0
      return true;
1988
0
    } // if
1989
0
      break;
1990
0
    } // case C_LDSP
1991
0
    case RISCV::C_LH: {
1992
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
1993
0
      (MI.getOperand(0).isReg()) &&
1994
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
1995
0
      (MI.getOperand(1).isReg()) &&
1996
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
1997
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
1998
      // lh $rd, ${imm12}(${rs1})
1999
0
      OutInst.setOpcode(RISCV::LH);
2000
      // Operand: rd
2001
0
      OutInst.addOperand(MI.getOperand(0));
2002
      // Operand: rs1
2003
0
      OutInst.addOperand(MI.getOperand(1));
2004
      // Operand: imm12
2005
0
      OutInst.addOperand(MI.getOperand(2));
2006
0
      OutInst.setLoc(MI.getLoc());
2007
0
      return true;
2008
0
    } // if
2009
0
      break;
2010
0
    } // case C_LH
2011
0
    case RISCV::C_LHU: {
2012
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2013
0
      (MI.getOperand(0).isReg()) &&
2014
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2015
0
      (MI.getOperand(1).isReg()) &&
2016
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2017
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2018
      // lhu  $rd, ${imm12}(${rs1})
2019
0
      OutInst.setOpcode(RISCV::LHU);
2020
      // Operand: rd
2021
0
      OutInst.addOperand(MI.getOperand(0));
2022
      // Operand: rs1
2023
0
      OutInst.addOperand(MI.getOperand(1));
2024
      // Operand: imm12
2025
0
      OutInst.addOperand(MI.getOperand(2));
2026
0
      OutInst.setLoc(MI.getLoc());
2027
0
      return true;
2028
0
    } // if
2029
0
      break;
2030
0
    } // case C_LHU
2031
0
    case RISCV::C_LI: {
2032
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2033
0
      (MI.getOperand(0).isReg()) &&
2034
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2035
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 1)) {
2036
      // addi $rd, $rs1, $imm12
2037
0
      OutInst.setOpcode(RISCV::ADDI);
2038
      // Operand: rd
2039
0
      OutInst.addOperand(MI.getOperand(0));
2040
      // Operand: rs1
2041
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
2042
      // Operand: imm12
2043
0
      OutInst.addOperand(MI.getOperand(1));
2044
0
      OutInst.setLoc(MI.getLoc());
2045
0
      return true;
2046
0
    } // if
2047
0
      break;
2048
0
    } // case C_LI
2049
0
    case RISCV::C_LUI: {
2050
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2051
0
      (MI.getOperand(0).isReg()) &&
2052
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2053
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(1), STI, 4)) {
2054
      // lui  $rd, $imm20
2055
0
      OutInst.setOpcode(RISCV::LUI);
2056
      // Operand: rd
2057
0
      OutInst.addOperand(MI.getOperand(0));
2058
      // Operand: imm20
2059
0
      OutInst.addOperand(MI.getOperand(1));
2060
0
      OutInst.setLoc(MI.getLoc());
2061
0
      return true;
2062
0
    } // if
2063
0
      break;
2064
0
    } // case C_LUI
2065
0
    case RISCV::C_LW: {
2066
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2067
0
      (MI.getOperand(0).isReg()) &&
2068
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2069
0
      (MI.getOperand(1).isReg()) &&
2070
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2071
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2072
      // lw $rd, ${imm12}(${rs1})
2073
0
      OutInst.setOpcode(RISCV::LW);
2074
      // Operand: rd
2075
0
      OutInst.addOperand(MI.getOperand(0));
2076
      // Operand: rs1
2077
0
      OutInst.addOperand(MI.getOperand(1));
2078
      // Operand: imm12
2079
0
      OutInst.addOperand(MI.getOperand(2));
2080
0
      OutInst.setLoc(MI.getLoc());
2081
0
      return true;
2082
0
    } // if
2083
0
      break;
2084
0
    } // case C_LW
2085
0
    case RISCV::C_LWSP: {
2086
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2087
0
      (MI.getOperand(0).isReg()) &&
2088
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2089
0
      (MI.getOperand(1).isReg()) &&
2090
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2091
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2092
      // lw $rd, ${imm12}(${rs1})
2093
0
      OutInst.setOpcode(RISCV::LW);
2094
      // Operand: rd
2095
0
      OutInst.addOperand(MI.getOperand(0));
2096
      // Operand: rs1
2097
0
      OutInst.addOperand(MI.getOperand(1));
2098
      // Operand: imm12
2099
0
      OutInst.addOperand(MI.getOperand(2));
2100
0
      OutInst.setLoc(MI.getLoc());
2101
0
      return true;
2102
0
    } // if
2103
0
      break;
2104
0
    } // case C_LWSP
2105
0
    case RISCV::C_MUL: {
2106
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2107
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtM] || STI.getFeatureBits()[RISCV::FeatureStdExtZmmul]) &&
2108
0
      (MI.getOperand(0).isReg()) &&
2109
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2110
0
      (MI.getOperand(0).isReg()) &&
2111
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2112
0
      (MI.getOperand(2).isReg()) &&
2113
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
2114
      // mul  $rd, $rs1, $rs2
2115
0
      OutInst.setOpcode(RISCV::MUL);
2116
      // Operand: rd
2117
0
      OutInst.addOperand(MI.getOperand(0));
2118
      // Operand: rs1
2119
0
      OutInst.addOperand(MI.getOperand(0));
2120
      // Operand: rs2
2121
0
      OutInst.addOperand(MI.getOperand(2));
2122
0
      OutInst.setLoc(MI.getLoc());
2123
0
      return true;
2124
0
    } // if
2125
0
      break;
2126
0
    } // case C_MUL
2127
0
    case RISCV::C_MV: {
2128
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2129
0
      (MI.getOperand(0).isReg()) &&
2130
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2131
0
      (MI.getOperand(1).isReg()) &&
2132
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2133
0
      RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) {
2134
      // addi $rd, $rs1, $imm12
2135
0
      OutInst.setOpcode(RISCV::ADDI);
2136
      // Operand: rd
2137
0
      OutInst.addOperand(MI.getOperand(0));
2138
      // Operand: rs1
2139
0
      OutInst.addOperand(MI.getOperand(1));
2140
      // Operand: imm12
2141
0
      OutInst.addOperand(MCOperand::createImm(0));
2142
0
      OutInst.setLoc(MI.getLoc());
2143
0
      return true;
2144
0
    } // if
2145
0
      break;
2146
0
    } // case C_MV
2147
0
    case RISCV::C_NOP: {
2148
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2149
0
      RISCVValidateMCOperandForUncompress(MCOperand::createImm(0), STI, 1)) {
2150
      // addi $rd, $rs1, $imm12
2151
0
      OutInst.setOpcode(RISCV::ADDI);
2152
      // Operand: rd
2153
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
2154
      // Operand: rs1
2155
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
2156
      // Operand: imm12
2157
0
      OutInst.addOperand(MCOperand::createImm(0));
2158
0
      OutInst.setLoc(MI.getLoc());
2159
0
      return true;
2160
0
    } // if
2161
0
      break;
2162
0
    } // case C_NOP
2163
0
    case RISCV::C_NOT: {
2164
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2165
0
      (MI.getOperand(0).isReg()) &&
2166
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2167
0
      (MI.getOperand(0).isReg()) &&
2168
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2169
0
      RISCVValidateMCOperandForUncompress(MCOperand::createImm(-1), STI, 1)) {
2170
      // xori $rd, $rs1, $imm12
2171
0
      OutInst.setOpcode(RISCV::XORI);
2172
      // Operand: rd
2173
0
      OutInst.addOperand(MI.getOperand(0));
2174
      // Operand: rs1
2175
0
      OutInst.addOperand(MI.getOperand(0));
2176
      // Operand: imm12
2177
0
      OutInst.addOperand(MCOperand::createImm(-1));
2178
0
      OutInst.setLoc(MI.getLoc());
2179
0
      return true;
2180
0
    } // if
2181
0
      break;
2182
0
    } // case C_NOT
2183
0
    case RISCV::C_OR: {
2184
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2185
0
      (MI.getOperand(0).isReg()) &&
2186
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2187
0
      (MI.getOperand(0).isReg()) &&
2188
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2189
0
      (MI.getOperand(2).isReg()) &&
2190
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
2191
      // or $rd, $rs1, $rs2
2192
0
      OutInst.setOpcode(RISCV::OR);
2193
      // Operand: rd
2194
0
      OutInst.addOperand(MI.getOperand(0));
2195
      // Operand: rs1
2196
0
      OutInst.addOperand(MI.getOperand(0));
2197
      // Operand: rs2
2198
0
      OutInst.addOperand(MI.getOperand(2));
2199
0
      OutInst.setLoc(MI.getLoc());
2200
0
      return true;
2201
0
    } // if
2202
0
      break;
2203
0
    } // case C_OR
2204
0
    case RISCV::C_SB: {
2205
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2206
0
      (MI.getOperand(0).isReg()) &&
2207
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2208
0
      (MI.getOperand(1).isReg()) &&
2209
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2210
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2211
      // sb $rs2, ${imm12}(${rs1})
2212
0
      OutInst.setOpcode(RISCV::SB);
2213
      // Operand: rs2
2214
0
      OutInst.addOperand(MI.getOperand(0));
2215
      // Operand: rs1
2216
0
      OutInst.addOperand(MI.getOperand(1));
2217
      // Operand: imm12
2218
0
      OutInst.addOperand(MI.getOperand(2));
2219
0
      OutInst.setLoc(MI.getLoc());
2220
0
      return true;
2221
0
    } // if
2222
0
      break;
2223
0
    } // case C_SB
2224
0
    case RISCV::C_SD: {
2225
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2226
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2227
0
      (MI.getOperand(0).isReg()) &&
2228
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2229
0
      (MI.getOperand(1).isReg()) &&
2230
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2231
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2232
      // sd $rs2, ${imm12}(${rs1})
2233
0
      OutInst.setOpcode(RISCV::SD);
2234
      // Operand: rs2
2235
0
      OutInst.addOperand(MI.getOperand(0));
2236
      // Operand: rs1
2237
0
      OutInst.addOperand(MI.getOperand(1));
2238
      // Operand: imm12
2239
0
      OutInst.addOperand(MI.getOperand(2));
2240
0
      OutInst.setLoc(MI.getLoc());
2241
0
      return true;
2242
0
    } // if
2243
0
      break;
2244
0
    } // case C_SD
2245
0
    case RISCV::C_SDSP: {
2246
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2247
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2248
0
      (MI.getOperand(0).isReg()) &&
2249
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2250
0
      (MI.getOperand(1).isReg()) &&
2251
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2252
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2253
      // sd $rs2, ${imm12}(${rs1})
2254
0
      OutInst.setOpcode(RISCV::SD);
2255
      // Operand: rs2
2256
0
      OutInst.addOperand(MI.getOperand(0));
2257
      // Operand: rs1
2258
0
      OutInst.addOperand(MI.getOperand(1));
2259
      // Operand: imm12
2260
0
      OutInst.addOperand(MI.getOperand(2));
2261
0
      OutInst.setLoc(MI.getLoc());
2262
0
      return true;
2263
0
    } // if
2264
0
      break;
2265
0
    } // case C_SDSP
2266
0
    case RISCV::C_SEXT_B: {
2267
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2268
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2269
0
      (MI.getOperand(0).isReg()) &&
2270
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2271
0
      (MI.getOperand(0).isReg()) &&
2272
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg()))) {
2273
      // sext.b $rd, $rs1
2274
0
      OutInst.setOpcode(RISCV::SEXT_B);
2275
      // Operand: rd
2276
0
      OutInst.addOperand(MI.getOperand(0));
2277
      // Operand: rs1
2278
0
      OutInst.addOperand(MI.getOperand(0));
2279
0
      OutInst.setLoc(MI.getLoc());
2280
0
      return true;
2281
0
    } // if
2282
0
      break;
2283
0
    } // case C_SEXT_B
2284
0
    case RISCV::C_SEXT_H: {
2285
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2286
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2287
0
      (MI.getOperand(0).isReg()) &&
2288
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2289
0
      (MI.getOperand(0).isReg()) &&
2290
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg()))) {
2291
      // sext.h $rd, $rs1
2292
0
      OutInst.setOpcode(RISCV::SEXT_H);
2293
      // Operand: rd
2294
0
      OutInst.addOperand(MI.getOperand(0));
2295
      // Operand: rs1
2296
0
      OutInst.addOperand(MI.getOperand(0));
2297
0
      OutInst.setLoc(MI.getLoc());
2298
0
      return true;
2299
0
    } // if
2300
0
      break;
2301
0
    } // case C_SEXT_H
2302
0
    case RISCV::C_SH: {
2303
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2304
0
      (MI.getOperand(0).isReg()) &&
2305
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2306
0
      (MI.getOperand(1).isReg()) &&
2307
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2308
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2309
      // sh $rs2, ${imm12}(${rs1})
2310
0
      OutInst.setOpcode(RISCV::SH);
2311
      // Operand: rs2
2312
0
      OutInst.addOperand(MI.getOperand(0));
2313
      // Operand: rs1
2314
0
      OutInst.addOperand(MI.getOperand(1));
2315
      // Operand: imm12
2316
0
      OutInst.addOperand(MI.getOperand(2));
2317
0
      OutInst.setLoc(MI.getLoc());
2318
0
      return true;
2319
0
    } // if
2320
0
      break;
2321
0
    } // case C_SH
2322
0
    case RISCV::C_SLLI: {
2323
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2324
0
      (MI.getOperand(0).isReg()) &&
2325
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2326
0
      (MI.getOperand(0).isReg()) &&
2327
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2328
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 5)) {
2329
      // slli $rd, $rs1, $shamt
2330
0
      OutInst.setOpcode(RISCV::SLLI);
2331
      // Operand: rd
2332
0
      OutInst.addOperand(MI.getOperand(0));
2333
      // Operand: rs1
2334
0
      OutInst.addOperand(MI.getOperand(0));
2335
      // Operand: shamt
2336
0
      OutInst.addOperand(MI.getOperand(2));
2337
0
      OutInst.setLoc(MI.getLoc());
2338
0
      return true;
2339
0
    } // if
2340
0
      break;
2341
0
    } // case C_SLLI
2342
0
    case RISCV::C_SRAI: {
2343
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2344
0
      (MI.getOperand(0).isReg()) &&
2345
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2346
0
      (MI.getOperand(0).isReg()) &&
2347
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2348
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 5)) {
2349
      // srai $rd, $rs1, $shamt
2350
0
      OutInst.setOpcode(RISCV::SRAI);
2351
      // Operand: rd
2352
0
      OutInst.addOperand(MI.getOperand(0));
2353
      // Operand: rs1
2354
0
      OutInst.addOperand(MI.getOperand(0));
2355
      // Operand: shamt
2356
0
      OutInst.addOperand(MI.getOperand(2));
2357
0
      OutInst.setLoc(MI.getLoc());
2358
0
      return true;
2359
0
    } // if
2360
0
      break;
2361
0
    } // case C_SRAI
2362
0
    case RISCV::C_SRLI: {
2363
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2364
0
      (MI.getOperand(0).isReg()) &&
2365
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2366
0
      (MI.getOperand(0).isReg()) &&
2367
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2368
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 5)) {
2369
      // srli $rd, $rs1, $shamt
2370
0
      OutInst.setOpcode(RISCV::SRLI);
2371
      // Operand: rd
2372
0
      OutInst.addOperand(MI.getOperand(0));
2373
      // Operand: rs1
2374
0
      OutInst.addOperand(MI.getOperand(0));
2375
      // Operand: shamt
2376
0
      OutInst.addOperand(MI.getOperand(2));
2377
0
      OutInst.setLoc(MI.getLoc());
2378
0
      return true;
2379
0
    } // if
2380
0
      break;
2381
0
    } // case C_SRLI
2382
0
    case RISCV::C_SSPOPCHK: {
2383
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2384
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
2385
0
      (MI.getOperand(0).isReg()) &&
2386
0
      (MI.getOperand(0).getReg() == RISCV::X5)) {
2387
      // sspopchk $rs1
2388
0
      OutInst.setOpcode(RISCV::SSPOPCHK);
2389
      // Operand: rs1
2390
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X5));
2391
0
      OutInst.setLoc(MI.getLoc());
2392
0
      return true;
2393
0
    } // if
2394
0
      break;
2395
0
    } // case C_SSPOPCHK
2396
0
    case RISCV::C_SSPUSH: {
2397
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
2398
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
2399
0
      (MI.getOperand(0).isReg()) &&
2400
0
      (MI.getOperand(0).getReg() == RISCV::X1)) {
2401
      // sspush $rs2
2402
0
      OutInst.setOpcode(RISCV::SSPUSH);
2403
      // Operand: rs2
2404
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X1));
2405
0
      OutInst.setLoc(MI.getLoc());
2406
0
      return true;
2407
0
    } // if
2408
0
      break;
2409
0
    } // case C_SSPUSH
2410
0
    case RISCV::C_SUB: {
2411
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2412
0
      (MI.getOperand(0).isReg()) &&
2413
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2414
0
      (MI.getOperand(0).isReg()) &&
2415
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2416
0
      (MI.getOperand(2).isReg()) &&
2417
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
2418
      // sub  $rd, $rs1, $rs2
2419
0
      OutInst.setOpcode(RISCV::SUB);
2420
      // Operand: rd
2421
0
      OutInst.addOperand(MI.getOperand(0));
2422
      // Operand: rs1
2423
0
      OutInst.addOperand(MI.getOperand(0));
2424
      // Operand: rs2
2425
0
      OutInst.addOperand(MI.getOperand(2));
2426
0
      OutInst.setLoc(MI.getLoc());
2427
0
      return true;
2428
0
    } // if
2429
0
      break;
2430
0
    } // case C_SUB
2431
0
    case RISCV::C_SUBW: {
2432
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2433
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2434
0
      (MI.getOperand(0).isReg()) &&
2435
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2436
0
      (MI.getOperand(0).isReg()) &&
2437
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2438
0
      (MI.getOperand(2).isReg()) &&
2439
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
2440
      // subw $rd, $rs1, $rs2
2441
0
      OutInst.setOpcode(RISCV::SUBW);
2442
      // Operand: rd
2443
0
      OutInst.addOperand(MI.getOperand(0));
2444
      // Operand: rs1
2445
0
      OutInst.addOperand(MI.getOperand(0));
2446
      // Operand: rs2
2447
0
      OutInst.addOperand(MI.getOperand(2));
2448
0
      OutInst.setLoc(MI.getLoc());
2449
0
      return true;
2450
0
    } // if
2451
0
      break;
2452
0
    } // case C_SUBW
2453
0
    case RISCV::C_SW: {
2454
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2455
0
      (MI.getOperand(0).isReg()) &&
2456
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2457
0
      (MI.getOperand(1).isReg()) &&
2458
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2459
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2460
      // sw $rs2, ${imm12}(${rs1})
2461
0
      OutInst.setOpcode(RISCV::SW);
2462
      // Operand: rs2
2463
0
      OutInst.addOperand(MI.getOperand(0));
2464
      // Operand: rs1
2465
0
      OutInst.addOperand(MI.getOperand(1));
2466
      // Operand: imm12
2467
0
      OutInst.addOperand(MI.getOperand(2));
2468
0
      OutInst.setLoc(MI.getLoc());
2469
0
      return true;
2470
0
    } // if
2471
0
      break;
2472
0
    } // case C_SW
2473
0
    case RISCV::C_SWSP: {
2474
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2475
0
      (MI.getOperand(0).isReg()) &&
2476
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2477
0
      (MI.getOperand(1).isReg()) &&
2478
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(1).getReg())) &&
2479
0
      RISCVValidateMCOperandForUncompress(MI.getOperand(2), STI, 1)) {
2480
      // sw $rs2, ${imm12}(${rs1})
2481
0
      OutInst.setOpcode(RISCV::SW);
2482
      // Operand: rs2
2483
0
      OutInst.addOperand(MI.getOperand(0));
2484
      // Operand: rs1
2485
0
      OutInst.addOperand(MI.getOperand(1));
2486
      // Operand: imm12
2487
0
      OutInst.addOperand(MI.getOperand(2));
2488
0
      OutInst.setLoc(MI.getLoc());
2489
0
      return true;
2490
0
    } // if
2491
0
      break;
2492
0
    } // case C_SWSP
2493
0
    case RISCV::C_UNIMP: {
2494
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
2495
      // unimp
2496
0
      OutInst.setOpcode(RISCV::UNIMP);
2497
0
      OutInst.setLoc(MI.getLoc());
2498
0
      return true;
2499
0
    } // if
2500
0
      break;
2501
0
    } // case C_UNIMP
2502
0
    case RISCV::C_XOR: {
2503
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2504
0
      (MI.getOperand(0).isReg()) &&
2505
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2506
0
      (MI.getOperand(0).isReg()) &&
2507
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2508
0
      (MI.getOperand(2).isReg()) &&
2509
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(2).getReg()))) {
2510
      // xor  $rd, $rs1, $rs2
2511
0
      OutInst.setOpcode(RISCV::XOR);
2512
      // Operand: rd
2513
0
      OutInst.addOperand(MI.getOperand(0));
2514
      // Operand: rs1
2515
0
      OutInst.addOperand(MI.getOperand(0));
2516
      // Operand: rs2
2517
0
      OutInst.addOperand(MI.getOperand(2));
2518
0
      OutInst.setLoc(MI.getLoc());
2519
0
      return true;
2520
0
    } // if
2521
0
      break;
2522
0
    } // case C_XOR
2523
0
    case RISCV::C_ZEXT_B: {
2524
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2525
0
      (MI.getOperand(0).isReg()) &&
2526
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2527
0
      (MI.getOperand(0).isReg()) &&
2528
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2529
0
      RISCVValidateMCOperandForUncompress(MCOperand::createImm(255), STI, 1)) {
2530
      // andi $rd, $rs1, $imm12
2531
0
      OutInst.setOpcode(RISCV::ANDI);
2532
      // Operand: rd
2533
0
      OutInst.addOperand(MI.getOperand(0));
2534
      // Operand: rs1
2535
0
      OutInst.addOperand(MI.getOperand(0));
2536
      // Operand: imm12
2537
0
      OutInst.addOperand(MCOperand::createImm(255));
2538
0
      OutInst.setLoc(MI.getLoc());
2539
0
      return true;
2540
0
    } // if
2541
0
      break;
2542
0
    } // case C_ZEXT_B
2543
0
    case RISCV::C_ZEXT_H: {
2544
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2545
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2546
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
2547
0
      (MI.getOperand(0).isReg()) &&
2548
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2549
0
      (MI.getOperand(0).isReg()) &&
2550
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg()))) {
2551
      // zext.h $rd, $rs1
2552
0
      OutInst.setOpcode(RISCV::ZEXT_H_RV32);
2553
      // Operand: rd
2554
0
      OutInst.addOperand(MI.getOperand(0));
2555
      // Operand: rs1
2556
0
      OutInst.addOperand(MI.getOperand(0));
2557
0
      OutInst.setLoc(MI.getLoc());
2558
0
      return true;
2559
0
    } // if
2560
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2561
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
2562
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2563
0
      (MI.getOperand(0).isReg()) &&
2564
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2565
0
      (MI.getOperand(0).isReg()) &&
2566
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg()))) {
2567
      // zext.h $rd, $rs1
2568
0
      OutInst.setOpcode(RISCV::ZEXT_H_RV64);
2569
      // Operand: rd
2570
0
      OutInst.addOperand(MI.getOperand(0));
2571
      // Operand: rs1
2572
0
      OutInst.addOperand(MI.getOperand(0));
2573
0
      OutInst.setLoc(MI.getLoc());
2574
0
      return true;
2575
0
    } // if
2576
0
      break;
2577
0
    } // case C_ZEXT_H
2578
0
    case RISCV::C_ZEXT_W: {
2579
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2580
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2581
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2582
0
      (MI.getOperand(0).isReg()) &&
2583
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
2584
0
      (MI.getOperand(0).isReg()) &&
2585
0
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg()))) {
2586
      // add.uw $rd, $rs1, $rs2
2587
0
      OutInst.setOpcode(RISCV::ADD_UW);
2588
      // Operand: rd
2589
0
      OutInst.addOperand(MI.getOperand(0));
2590
      // Operand: rs1
2591
0
      OutInst.addOperand(MI.getOperand(0));
2592
      // Operand: rs2
2593
0
      OutInst.addOperand(MCOperand::createReg(RISCV::X0));
2594
0
      OutInst.setLoc(MI.getLoc());
2595
0
      return true;
2596
0
    } // if
2597
2598
0
    } // case C_ZEXT_W
2599
0
  } // switch
2600
0
  return false;
2601
0
}
2602
2603
#endif //GEN_UNCOMPRESS_INSTR
2604
2605
2606
#ifdef GEN_CHECK_COMPRESS_INSTR
2607
#undef GEN_CHECK_COMPRESS_INSTR
2608
2609
static bool RISCVValidateMachineOperand(const MachineOperand &MO,
2610
                  const RISCVSubtarget *Subtarget,
2611
0
                  unsigned PredicateIndex) {
2612
0
  int64_t Imm = MO.getImm();
2613
0
  switch (PredicateIndex) {
2614
0
  default:
2615
0
    llvm_unreachable("Unknown ImmLeaf Predicate kind");
2616
0
    break;
2617
0
  case 1: {
2618
  // simm6nonzero
2619
0
  return (Imm != 0) && isInt<6>(Imm);
2620
0
  }
2621
0
  case 2: {
2622
  // simm10_lsb0000nonzero
2623
0
  return (Imm != 0) && isShiftedInt<6, 4>(Imm);
2624
0
  }
2625
0
  case 3: {
2626
  // uimm10_lsb00nonzero
2627
0
  return isShiftedUInt<8, 2>(Imm) && (Imm != 0);
2628
0
  }
2629
0
  case 4: {
2630
  // simm6
2631
0
  return isInt<6>(Imm);
2632
0
  }
2633
0
  case 5: {
2634
  // simm9_lsb0
2635
0
  return isShiftedInt<8, 1>(Imm);
2636
0
  }
2637
0
  case 6: {
2638
  // uimm8_lsb000
2639
0
  return isShiftedUInt<5, 3>(Imm);
2640
0
  }
2641
0
  case 7: {
2642
  // uimm9_lsb000
2643
0
  return isShiftedUInt<6, 3>(Imm);
2644
0
  }
2645
0
  case 8: {
2646
  // uimm7_lsb00
2647
0
  return isShiftedUInt<5, 2>(Imm);
2648
0
  }
2649
0
  case 9: {
2650
  // uimm8_lsb00
2651
0
  return isShiftedUInt<6, 2>(Imm);
2652
0
  }
2653
0
  case 10: {
2654
  // simm12_lsb0
2655
0
  return isShiftedInt<11, 1>(Imm);
2656
0
  }
2657
0
  case 11: {
2658
  // uimm2
2659
0
  return isUInt<2>(Imm);
2660
0
  }
2661
0
  case 12: {
2662
  // uimm2_lsb0
2663
0
  return isShiftedUInt<1, 1>(Imm);
2664
0
  }
2665
0
  case 13: {
2666
  // c_lui_imm
2667
0
  return (Imm != 0) &&
2668
0
                                 (isUInt<5>(Imm) ||
2669
0
                                  (Imm >= 0xfffe0 && Imm <= 0xfffff));
2670
0
  }
2671
0
  case 14: {
2672
  // uimmlog2xlennonzero
2673
  
2674
0
  if (Subtarget->is64Bit())
2675
0
    return isUInt<6>(Imm) && (Imm != 0);
2676
0
  return isUInt<5>(Imm) && (Imm != 0);
2677
2678
0
  }
2679
0
  }
2680
0
}
2681
2682
static bool isCompressibleInst(const MachineInstr &MI,
2683
7.64M
                               const RISCVSubtarget &STI) {
2684
7.64M
  switch (MI.getOpcode()) {
2685
1.57M
    default: return false;
2686
122k
    case RISCV::ADD: {
2687
122k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2688
122k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2689
122k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2690
122k
      (MI.getOperand(1).isReg()) &&
2691
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
2692
122k
      (MI.getOperand(2).isReg()) &&
2693
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) {
2694
      // c.add  $rs1, $rs2
2695
      // Operand: rs1_wb
2696
      // Operand: rs1
2697
      // Operand: rs2
2698
0
      return true;
2699
0
    } // if
2700
122k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2701
122k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
2702
122k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
2703
122k
      (MI.getOperand(2).isReg()) &&
2704
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg())) &&
2705
122k
      (MI.getOperand(1).isReg()) &&
2706
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
2707
      // c.add  $rs1, $rs2
2708
      // Operand: rs1_wb
2709
      // Operand: rs1
2710
      // Operand: rs2
2711
0
      return true;
2712
0
    } // if
2713
122k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2714
122k
      (MI.getOperand(1).isReg()) &&
2715
122k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
2716
122k
      (MI.getOperand(0).isReg()) &&
2717
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
2718
122k
      (MI.getOperand(2).isReg()) &&
2719
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(2).getReg()))) {
2720
      // c.mv $rs1, $rs2
2721
      // Operand: rs1
2722
      // Operand: rs2
2723
0
      return true;
2724
0
    } // if
2725
122k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2726
122k
      (MI.getOperand(2).isReg()) &&
2727
122k
      (MI.getOperand(2).getReg() == RISCV::X0) &&
2728
122k
      (MI.getOperand(0).isReg()) &&
2729
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
2730
122k
      (MI.getOperand(1).isReg()) &&
2731
122k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
2732
      // c.mv $rs1, $rs2
2733
      // Operand: rs1
2734
      // Operand: rs2
2735
0
      return true;
2736
0
    } // if
2737
122k
      break;
2738
122k
    } // case ADD
2739
935k
    case RISCV::ADDI: {
2740
935k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2741
935k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2742
935k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2743
935k
      (MI.getOperand(1).isReg()) &&
2744
935k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
2745
935k
      MI.getOperand(2).isImm() &&
2746
935k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 1)) {
2747
      // c.addi $rd, $imm
2748
      // Operand: rd_wb
2749
      // Operand: rd
2750
      // Operand: imm
2751
0
      return true;
2752
0
    } // if
2753
935k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2754
935k
      (MI.getOperand(0).isReg()) &&
2755
935k
      (MI.getOperand(0).getReg() == RISCV::X2) &&
2756
935k
      (MI.getOperand(1).isReg()) &&
2757
935k
      (MI.getOperand(1).getReg() == RISCV::X2) &&
2758
935k
      MI.getOperand(2).isImm() &&
2759
935k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 2)) {
2760
      // c.addi16sp $rd, $imm
2761
      // Operand: rd_wb
2762
      // Operand: rd
2763
      // Operand: imm
2764
0
      return true;
2765
0
    } // if
2766
935k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2767
935k
      (MI.getOperand(0).isReg()) &&
2768
935k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
2769
935k
      (MI.getOperand(1).isReg()) &&
2770
935k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
2771
935k
      MI.getOperand(2).isImm() &&
2772
935k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 3)) {
2773
      // c.addi4spn $rd, $rs1, $imm
2774
      // Operand: rd
2775
      // Operand: rs1
2776
      // Operand: imm
2777
0
      return true;
2778
0
    } // if
2779
935k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2780
935k
      (MI.getOperand(1).isReg()) &&
2781
935k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
2782
935k
      (MI.getOperand(0).isReg()) &&
2783
935k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
2784
935k
      MI.getOperand(2).isImm() &&
2785
935k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
2786
      // c.li $rd, $imm
2787
      // Operand: rd
2788
      // Operand: imm
2789
0
      return true;
2790
0
    } // if
2791
935k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2792
935k
      (MI.getOperand(2).isImm()) &&
2793
935k
      (MI.getOperand(2).getImm() == 0) &&
2794
935k
      (MI.getOperand(0).isReg()) &&
2795
935k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
2796
935k
      (MI.getOperand(1).isReg()) &&
2797
935k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
2798
      // c.mv $rs1, $rs2
2799
      // Operand: rs1
2800
      // Operand: rs2
2801
0
      return true;
2802
0
    } // if
2803
935k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2804
935k
      (MI.getOperand(0).isReg()) &&
2805
935k
      (MI.getOperand(0).getReg() == RISCV::X0) &&
2806
935k
      (MI.getOperand(1).isReg()) &&
2807
935k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
2808
935k
      (MI.getOperand(2).isImm()) &&
2809
935k
      (MI.getOperand(2).getImm() == 0)) {
2810
      // c.nop
2811
0
      return true;
2812
0
    } // if
2813
935k
      break;
2814
935k
    } // case ADDI
2815
935k
    case RISCV::ADDIW: {
2816
40.7k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2817
40.7k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2818
40.7k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2819
40.7k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2820
40.7k
      (MI.getOperand(1).isReg()) &&
2821
40.7k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
2822
40.7k
      MI.getOperand(2).isImm() &&
2823
40.7k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
2824
      // c.addiw  $rd, $imm
2825
      // Operand: rd_wb
2826
      // Operand: rd
2827
      // Operand: imm
2828
0
      return true;
2829
0
    } // if
2830
40.7k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2831
40.7k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2832
40.7k
      (MI.getOperand(1).isReg()) &&
2833
40.7k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
2834
40.7k
      (MI.getOperand(0).isReg()) &&
2835
40.7k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
2836
40.7k
      MI.getOperand(2).isImm() &&
2837
40.7k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
2838
      // c.li $rd, $imm
2839
      // Operand: rd
2840
      // Operand: imm
2841
0
      return true;
2842
0
    } // if
2843
40.7k
      break;
2844
40.7k
    } // case ADDIW
2845
40.7k
    case RISCV::ADDW: {
2846
1.25k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2847
1.25k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2848
1.25k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2849
1.25k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2850
1.25k
      (MI.getOperand(1).isReg()) &&
2851
1.25k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
2852
1.25k
      (MI.getOperand(2).isReg()) &&
2853
1.25k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
2854
      // c.addw $rd, $rs2
2855
      // Operand: rd_wb
2856
      // Operand: rd
2857
      // Operand: rs2
2858
0
      return true;
2859
0
    } // if
2860
1.25k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2861
1.25k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2862
1.25k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
2863
1.25k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
2864
1.25k
      (MI.getOperand(2).isReg()) &&
2865
1.25k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
2866
1.25k
      (MI.getOperand(1).isReg()) &&
2867
1.25k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
2868
      // c.addw $rd, $rs2
2869
      // Operand: rd_wb
2870
      // Operand: rd
2871
      // Operand: rs2
2872
0
      return true;
2873
0
    } // if
2874
1.25k
      break;
2875
1.25k
    } // case ADDW
2876
1.25k
    case RISCV::ADD_UW: {
2877
0
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
2878
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZba] &&
2879
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2880
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2881
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2882
0
      (MI.getOperand(2).isReg()) &&
2883
0
      (MI.getOperand(2).getReg() == RISCV::X0) &&
2884
0
      (MI.getOperand(1).isReg()) &&
2885
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
2886
      // c.zext.w $rd
2887
      // Operand: rd_wb
2888
      // Operand: rd
2889
0
      return true;
2890
0
    } // if
2891
0
      break;
2892
0
    } // case ADD_UW
2893
76.5k
    case RISCV::AND: {
2894
76.5k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2895
76.5k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2896
76.5k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2897
76.5k
      (MI.getOperand(1).isReg()) &&
2898
76.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
2899
76.5k
      (MI.getOperand(2).isReg()) &&
2900
76.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
2901
      // c.and  $rd, $rs2
2902
      // Operand: rd_wb
2903
      // Operand: rd
2904
      // Operand: rs2
2905
0
      return true;
2906
0
    } // if
2907
76.5k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2908
76.5k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
2909
76.5k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
2910
76.5k
      (MI.getOperand(2).isReg()) &&
2911
76.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
2912
76.5k
      (MI.getOperand(1).isReg()) &&
2913
76.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
2914
      // c.and  $rd, $rs2
2915
      // Operand: rd_wb
2916
      // Operand: rd
2917
      // Operand: rs2
2918
0
      return true;
2919
0
    } // if
2920
76.5k
      break;
2921
76.5k
    } // case AND
2922
164k
    case RISCV::ANDI: {
2923
164k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2924
164k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2925
164k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2926
164k
      (MI.getOperand(1).isReg()) &&
2927
164k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
2928
164k
      MI.getOperand(2).isImm() &&
2929
164k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 4)) {
2930
      // c.andi $rs1, $imm
2931
      // Operand: rs1_wb
2932
      // Operand: rs1
2933
      // Operand: imm
2934
0
      return true;
2935
0
    } // if
2936
164k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
2937
164k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
2938
164k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
2939
164k
      (MI.getOperand(2).isImm()) &&
2940
164k
      (MI.getOperand(2).getImm() == 255) &&
2941
164k
      (MI.getOperand(1).isReg()) &&
2942
164k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
2943
      // c.zext.b $rd
2944
      // Operand: rd_wb
2945
      // Operand: rd
2946
0
      return true;
2947
0
    } // if
2948
164k
      break;
2949
164k
    } // case ANDI
2950
164k
    case RISCV::BEQ: {
2951
1.49k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2952
1.49k
      (MI.getOperand(1).isReg()) &&
2953
1.49k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
2954
1.49k
      (MI.getOperand(0).isReg()) &&
2955
1.49k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
2956
1.49k
      MI.getOperand(2).isImm() &&
2957
1.49k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
2958
      // c.beqz $rs1, $imm
2959
      // Operand: rs1
2960
      // Operand: imm
2961
0
      return true;
2962
0
    } // if
2963
1.49k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2964
1.49k
      (MI.getOperand(0).isReg()) &&
2965
1.49k
      (MI.getOperand(0).getReg() == RISCV::X0) &&
2966
1.49k
      (MI.getOperand(1).isReg()) &&
2967
1.49k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
2968
1.49k
      MI.getOperand(2).isImm() &&
2969
1.49k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
2970
      // c.beqz $rs1, $imm
2971
      // Operand: rs1
2972
      // Operand: imm
2973
0
      return true;
2974
0
    } // if
2975
1.49k
      break;
2976
1.49k
    } // case BEQ
2977
19.2k
    case RISCV::BNE: {
2978
19.2k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2979
19.2k
      (MI.getOperand(1).isReg()) &&
2980
19.2k
      (MI.getOperand(1).getReg() == RISCV::X0) &&
2981
19.2k
      (MI.getOperand(0).isReg()) &&
2982
19.2k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
2983
19.2k
      MI.getOperand(2).isImm() &&
2984
19.2k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
2985
      // c.bnez $rs1, $imm
2986
      // Operand: rs1
2987
      // Operand: imm
2988
0
      return true;
2989
0
    } // if
2990
19.2k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
2991
19.2k
      (MI.getOperand(0).isReg()) &&
2992
19.2k
      (MI.getOperand(0).getReg() == RISCV::X0) &&
2993
19.2k
      (MI.getOperand(1).isReg()) &&
2994
19.2k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
2995
19.2k
      MI.getOperand(2).isImm() &&
2996
19.2k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 5)) {
2997
      // c.bnez $rs1, $imm
2998
      // Operand: rs1
2999
      // Operand: imm
3000
0
      return true;
3001
0
    } // if
3002
19.2k
      break;
3003
19.2k
    } // case BNE
3004
19.2k
    case RISCV::EBREAK: {
3005
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
3006
      // c.ebreak
3007
0
      return true;
3008
0
    } // if
3009
0
      break;
3010
0
    } // case EBREAK
3011
0
    case RISCV::FLD: {
3012
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3013
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3014
0
      (MI.getOperand(0).isReg()) &&
3015
0
      (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) &&
3016
0
      (MI.getOperand(1).isReg()) &&
3017
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3018
0
      MI.getOperand(2).isImm() &&
3019
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3020
      // c.fld  $rd, ${imm}(${rs1})
3021
      // Operand: rd
3022
      // Operand: rs1
3023
      // Operand: imm
3024
0
      return true;
3025
0
    } // if
3026
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3027
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3028
0
      (MI.getOperand(0).isReg()) &&
3029
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
3030
0
      (MI.getOperand(1).isReg()) &&
3031
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3032
0
      MI.getOperand(2).isImm() &&
3033
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3034
      // c.fldsp  $rd, ${imm}(${rs1})
3035
      // Operand: rd
3036
      // Operand: rs1
3037
      // Operand: imm
3038
0
      return true;
3039
0
    } // if
3040
0
      break;
3041
0
    } // case FLD
3042
0
    case RISCV::FLW: {
3043
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3044
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3045
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3046
0
      (MI.getOperand(0).isReg()) &&
3047
0
      (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) &&
3048
0
      (MI.getOperand(1).isReg()) &&
3049
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3050
0
      MI.getOperand(2).isImm() &&
3051
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3052
      // c.flw  $rd, ${imm}(${rs1})
3053
      // Operand: rd
3054
      // Operand: rs1
3055
      // Operand: imm
3056
0
      return true;
3057
0
    } // if
3058
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3059
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3060
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3061
0
      (MI.getOperand(0).isReg()) &&
3062
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
3063
0
      (MI.getOperand(1).isReg()) &&
3064
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3065
0
      MI.getOperand(2).isImm() &&
3066
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3067
      // c.flwsp  $rd, ${imm}(${rs1})
3068
      // Operand: rd
3069
      // Operand: rs1
3070
      // Operand: imm
3071
0
      return true;
3072
0
    } // if
3073
0
      break;
3074
0
    } // case FLW
3075
0
    case RISCV::FSD: {
3076
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3077
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3078
0
      (MI.getOperand(0).isReg()) &&
3079
0
      (RISCVMCRegisterClasses[RISCV::FPR64CRegClassID].contains(MI.getOperand(0).getReg())) &&
3080
0
      (MI.getOperand(1).isReg()) &&
3081
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3082
0
      MI.getOperand(2).isImm() &&
3083
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3084
      // c.fsd  $rs2, ${imm}(${rs1})
3085
      // Operand: rs2
3086
      // Operand: rs1
3087
      // Operand: imm
3088
0
      return true;
3089
0
    } // if
3090
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtD] &&
3091
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZcd]) &&
3092
0
      (MI.getOperand(0).isReg()) &&
3093
0
      (RISCVMCRegisterClasses[RISCV::FPR64RegClassID].contains(MI.getOperand(0).getReg())) &&
3094
0
      (MI.getOperand(1).isReg()) &&
3095
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3096
0
      MI.getOperand(2).isImm() &&
3097
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3098
      // c.fsdsp  $rs2, ${imm}(${rs1})
3099
      // Operand: rs2
3100
      // Operand: rs1
3101
      // Operand: imm
3102
0
      return true;
3103
0
    } // if
3104
0
      break;
3105
0
    } // case FSD
3106
0
    case RISCV::FSW: {
3107
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3108
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3109
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3110
0
      (MI.getOperand(0).isReg()) &&
3111
0
      (RISCVMCRegisterClasses[RISCV::FPR32CRegClassID].contains(MI.getOperand(0).getReg())) &&
3112
0
      (MI.getOperand(1).isReg()) &&
3113
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3114
0
      MI.getOperand(2).isImm() &&
3115
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3116
      // c.fsw  $rs2, ${imm}(${rs1})
3117
      // Operand: rs2
3118
      // Operand: rs1
3119
      // Operand: imm
3120
0
      return true;
3121
0
    } // if
3122
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtF] &&
3123
0
      !STI.getFeatureBits()[RISCV::Feature64Bit] &&
3124
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZce] || STI.getFeatureBits()[RISCV::FeatureStdExtZcf]) &&
3125
0
      (MI.getOperand(0).isReg()) &&
3126
0
      (RISCVMCRegisterClasses[RISCV::FPR32RegClassID].contains(MI.getOperand(0).getReg())) &&
3127
0
      (MI.getOperand(1).isReg()) &&
3128
0
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3129
0
      MI.getOperand(2).isImm() &&
3130
0
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3131
      // c.fswsp  $rs2, ${imm}(${rs1})
3132
      // Operand: rs2
3133
      // Operand: rs1
3134
      // Operand: imm
3135
0
      return true;
3136
0
    } // if
3137
0
      break;
3138
0
    } // case FSW
3139
0
    case RISCV::JAL: {
3140
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3141
0
      (MI.getOperand(0).isReg()) &&
3142
0
      (MI.getOperand(0).getReg() == RISCV::X0) &&
3143
0
      MI.getOperand(1).isImm() &&
3144
0
      RISCVValidateMachineOperand(MI.getOperand(1), &STI, 10)) {
3145
      // c.j  $offset
3146
      // Operand: offset
3147
0
      return true;
3148
0
    } // if
3149
0
    if (!STI.getFeatureBits()[RISCV::Feature64Bit] &&
3150
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3151
0
      (MI.getOperand(0).isReg()) &&
3152
0
      (MI.getOperand(0).getReg() == RISCV::X1) &&
3153
0
      MI.getOperand(1).isImm() &&
3154
0
      RISCVValidateMachineOperand(MI.getOperand(1), &STI, 10)) {
3155
      // c.jal  $offset
3156
      // Operand: offset
3157
0
      return true;
3158
0
    } // if
3159
0
      break;
3160
0
    } // case JAL
3161
0
    case RISCV::JALR: {
3162
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3163
0
      (MI.getOperand(0).isReg()) &&
3164
0
      (MI.getOperand(0).getReg() == RISCV::X1) &&
3165
0
      (MI.getOperand(2).isImm()) &&
3166
0
      (MI.getOperand(2).getImm() == 0) &&
3167
0
      (MI.getOperand(1).isReg()) &&
3168
0
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3169
      // c.jalr $rs1
3170
      // Operand: rs1
3171
0
      return true;
3172
0
    } // if
3173
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3174
0
      (MI.getOperand(0).isReg()) &&
3175
0
      (MI.getOperand(0).getReg() == RISCV::X0) &&
3176
0
      (MI.getOperand(2).isImm()) &&
3177
0
      (MI.getOperand(2).getImm() == 0) &&
3178
0
      (MI.getOperand(1).isReg()) &&
3179
0
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg()))) {
3180
      // c.jr $rs1
3181
      // Operand: rs1
3182
0
      return true;
3183
0
    } // if
3184
0
      break;
3185
0
    } // case JALR
3186
132k
    case RISCV::LBU: {
3187
132k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3188
132k
      (MI.getOperand(0).isReg()) &&
3189
132k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3190
132k
      (MI.getOperand(1).isReg()) &&
3191
132k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3192
132k
      MI.getOperand(2).isImm() &&
3193
132k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11)) {
3194
      // c.lbu  $rd, ${imm}(${rs1})
3195
      // Operand: rd
3196
      // Operand: rs1
3197
      // Operand: imm
3198
0
      return true;
3199
0
    } // if
3200
132k
      break;
3201
132k
    } // case LBU
3202
938k
    case RISCV::LD: {
3203
938k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3204
938k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3205
938k
      (MI.getOperand(0).isReg()) &&
3206
938k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3207
938k
      (MI.getOperand(1).isReg()) &&
3208
938k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3209
938k
      MI.getOperand(2).isImm() &&
3210
938k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3211
      // c.ld $rd, ${imm}(${rs1})
3212
      // Operand: rd
3213
      // Operand: rs1
3214
      // Operand: imm
3215
0
      return true;
3216
0
    } // if
3217
938k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3218
938k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3219
938k
      (MI.getOperand(0).isReg()) &&
3220
938k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3221
938k
      (MI.getOperand(1).isReg()) &&
3222
938k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3223
938k
      MI.getOperand(2).isImm() &&
3224
938k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3225
      // c.ldsp $rd, ${imm}(${rs1})
3226
      // Operand: rd
3227
      // Operand: rs1
3228
      // Operand: imm
3229
0
      return true;
3230
0
    } // if
3231
938k
      break;
3232
938k
    } // case LD
3233
938k
    case RISCV::LH: {
3234
55.9k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3235
55.9k
      (MI.getOperand(0).isReg()) &&
3236
55.9k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3237
55.9k
      (MI.getOperand(1).isReg()) &&
3238
55.9k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3239
55.9k
      MI.getOperand(2).isImm() &&
3240
55.9k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) {
3241
      // c.lh $rd, ${imm}(${rs1})
3242
      // Operand: rd
3243
      // Operand: rs1
3244
      // Operand: imm
3245
0
      return true;
3246
0
    } // if
3247
55.9k
      break;
3248
55.9k
    } // case LH
3249
55.9k
    case RISCV::LHU: {
3250
45.5k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3251
45.5k
      (MI.getOperand(0).isReg()) &&
3252
45.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3253
45.5k
      (MI.getOperand(1).isReg()) &&
3254
45.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3255
45.5k
      MI.getOperand(2).isImm() &&
3256
45.5k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) {
3257
      // c.lhu  $rd, ${imm}(${rs1})
3258
      // Operand: rd
3259
      // Operand: rs1
3260
      // Operand: imm
3261
0
      return true;
3262
0
    } // if
3263
45.5k
      break;
3264
45.5k
    } // case LHU
3265
701k
    case RISCV::LUI: {
3266
701k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3267
701k
      (MI.getOperand(0).isReg()) &&
3268
701k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0X2RegClassID].contains(MI.getOperand(0).getReg())) &&
3269
701k
      MI.getOperand(1).isImm() &&
3270
701k
      RISCVValidateMachineOperand(MI.getOperand(1), &STI, 13)) {
3271
      // c.lui  $rd, $imm
3272
      // Operand: rd
3273
      // Operand: imm
3274
0
      return true;
3275
0
    } // if
3276
701k
      break;
3277
701k
    } // case LUI
3278
701k
    case RISCV::LW: {
3279
162k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3280
162k
      (MI.getOperand(0).isReg()) &&
3281
162k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3282
162k
      (MI.getOperand(1).isReg()) &&
3283
162k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3284
162k
      MI.getOperand(2).isImm() &&
3285
162k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3286
      // c.lw $rd, ${imm}(${rs1})
3287
      // Operand: rd
3288
      // Operand: rs1
3289
      // Operand: imm
3290
0
      return true;
3291
0
    } // if
3292
162k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3293
162k
      (MI.getOperand(0).isReg()) &&
3294
162k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(0).getReg())) &&
3295
162k
      (MI.getOperand(1).isReg()) &&
3296
162k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3297
162k
      MI.getOperand(2).isImm() &&
3298
162k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3299
      // c.lwsp $rd, ${imm}(${rs1})
3300
      // Operand: rd
3301
      // Operand: rs1
3302
      // Operand: imm
3303
0
      return true;
3304
0
    } // if
3305
162k
      break;
3306
162k
    } // case LW
3307
162k
    case RISCV::MUL: {
3308
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3309
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtM] || STI.getFeatureBits()[RISCV::FeatureStdExtZmmul]) &&
3310
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3311
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3312
0
      (MI.getOperand(1).isReg()) &&
3313
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3314
0
      (MI.getOperand(2).isReg()) &&
3315
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3316
      // c.mul  $rd, $rs2
3317
      // Operand: rd_wb
3318
      // Operand: rd
3319
      // Operand: rs2
3320
0
      return true;
3321
0
    } // if
3322
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3323
0
      (STI.getFeatureBits()[RISCV::FeatureStdExtM] || STI.getFeatureBits()[RISCV::FeatureStdExtZmmul]) &&
3324
0
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3325
0
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
3326
0
      (MI.getOperand(2).isReg()) &&
3327
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3328
0
      (MI.getOperand(1).isReg()) &&
3329
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3330
      // c.mul  $rd, $rs2
3331
      // Operand: rd_wb
3332
      // Operand: rd
3333
      // Operand: rs2
3334
0
      return true;
3335
0
    } // if
3336
0
      break;
3337
0
    } // case MUL
3338
120k
    case RISCV::OR: {
3339
120k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3340
120k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3341
120k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3342
120k
      (MI.getOperand(1).isReg()) &&
3343
120k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3344
120k
      (MI.getOperand(2).isReg()) &&
3345
120k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3346
      // c.or $rd, $rs2
3347
      // Operand: rd_wb
3348
      // Operand: rd
3349
      // Operand: rs2
3350
0
      return true;
3351
0
    } // if
3352
120k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3353
120k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3354
120k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
3355
120k
      (MI.getOperand(2).isReg()) &&
3356
120k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3357
120k
      (MI.getOperand(1).isReg()) &&
3358
120k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3359
      // c.or $rd, $rs2
3360
      // Operand: rd_wb
3361
      // Operand: rd
3362
      // Operand: rs2
3363
0
      return true;
3364
0
    } // if
3365
120k
      break;
3366
120k
    } // case OR
3367
651k
    case RISCV::SB: {
3368
651k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3369
651k
      (MI.getOperand(0).isReg()) &&
3370
651k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3371
651k
      (MI.getOperand(1).isReg()) &&
3372
651k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3373
651k
      MI.getOperand(2).isImm() &&
3374
651k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 11)) {
3375
      // c.sb $rs2, ${imm}(${rs1})
3376
      // Operand: rs2
3377
      // Operand: rs1
3378
      // Operand: imm
3379
0
      return true;
3380
0
    } // if
3381
651k
      break;
3382
651k
    } // case SB
3383
1.00M
    case RISCV::SD: {
3384
1.00M
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3385
1.00M
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3386
1.00M
      (MI.getOperand(0).isReg()) &&
3387
1.00M
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3388
1.00M
      (MI.getOperand(1).isReg()) &&
3389
1.00M
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3390
1.00M
      MI.getOperand(2).isImm() &&
3391
1.00M
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 6)) {
3392
      // c.sd $rs2, ${imm}(${rs1})
3393
      // Operand: rs2
3394
      // Operand: rs1
3395
      // Operand: imm
3396
0
      return true;
3397
0
    } // if
3398
1.00M
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3399
1.00M
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3400
1.00M
      (MI.getOperand(0).isReg()) &&
3401
1.00M
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
3402
1.00M
      (MI.getOperand(1).isReg()) &&
3403
1.00M
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3404
1.00M
      MI.getOperand(2).isImm() &&
3405
1.00M
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 7)) {
3406
      // c.sdsp $rs2, ${imm}(${rs1})
3407
      // Operand: rs2
3408
      // Operand: rs1
3409
      // Operand: imm
3410
0
      return true;
3411
0
    } // if
3412
1.00M
      break;
3413
1.00M
    } // case SD
3414
1.00M
    case RISCV::SEXT_B: {
3415
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3416
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3417
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3418
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3419
0
      (MI.getOperand(1).isReg()) &&
3420
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3421
      // c.sext.b $rd
3422
      // Operand: rd_wb
3423
      // Operand: rd
3424
0
      return true;
3425
0
    } // if
3426
0
      break;
3427
0
    } // case SEXT_B
3428
0
    case RISCV::SEXT_H: {
3429
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3430
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3431
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3432
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3433
0
      (MI.getOperand(1).isReg()) &&
3434
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3435
      // c.sext.h $rd
3436
      // Operand: rd_wb
3437
      // Operand: rd
3438
0
      return true;
3439
0
    } // if
3440
0
      break;
3441
0
    } // case SEXT_H
3442
71.5k
    case RISCV::SH: {
3443
71.5k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3444
71.5k
      (MI.getOperand(0).isReg()) &&
3445
71.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3446
71.5k
      (MI.getOperand(1).isReg()) &&
3447
71.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3448
71.5k
      MI.getOperand(2).isImm() &&
3449
71.5k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 12)) {
3450
      // c.sh $rs2, ${imm}(${rs1})
3451
      // Operand: rs2
3452
      // Operand: rs1
3453
      // Operand: imm
3454
0
      return true;
3455
0
    } // if
3456
71.5k
      break;
3457
71.5k
    } // case SH
3458
229k
    case RISCV::SLLI: {
3459
229k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3460
229k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3461
229k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3462
229k
      (MI.getOperand(1).isReg()) &&
3463
229k
      (RISCVMCRegisterClasses[RISCV::GPRNoX0RegClassID].contains(MI.getOperand(1).getReg())) &&
3464
229k
      MI.getOperand(2).isImm() &&
3465
229k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14)) {
3466
      // c.slli $rd, $imm
3467
      // Operand: rd_wb
3468
      // Operand: rd
3469
      // Operand: imm
3470
0
      return true;
3471
0
    } // if
3472
229k
      break;
3473
229k
    } // case SLLI
3474
229k
    case RISCV::SRAI: {
3475
39.5k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3476
39.5k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3477
39.5k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3478
39.5k
      (MI.getOperand(1).isReg()) &&
3479
39.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3480
39.5k
      MI.getOperand(2).isImm() &&
3481
39.5k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14)) {
3482
      // c.srai $rs1, $imm
3483
      // Operand: rs1_wb
3484
      // Operand: rs1
3485
      // Operand: imm
3486
0
      return true;
3487
0
    } // if
3488
39.5k
      break;
3489
39.5k
    } // case SRAI
3490
63.3k
    case RISCV::SRLI: {
3491
63.3k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3492
63.3k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3493
63.3k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3494
63.3k
      (MI.getOperand(1).isReg()) &&
3495
63.3k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3496
63.3k
      MI.getOperand(2).isImm() &&
3497
63.3k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 14)) {
3498
      // c.srli $rs1, $imm
3499
      // Operand: rs1_wb
3500
      // Operand: rs1
3501
      // Operand: imm
3502
0
      return true;
3503
0
    } // if
3504
63.3k
      break;
3505
63.3k
    } // case SRLI
3506
63.3k
    case RISCV::SSPOPCHK: {
3507
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
3508
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
3509
0
      (MI.getOperand(0).isReg()) &&
3510
0
      (MI.getOperand(0).getReg() == RISCV::X5)) {
3511
      // c.sspopchk $rs1
3512
      // Operand: rs1
3513
0
      return true;
3514
0
    } // if
3515
0
      break;
3516
0
    } // case SSPOPCHK
3517
0
    case RISCV::SSPUSH: {
3518
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcmop] &&
3519
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZicfiss] &&
3520
0
      (MI.getOperand(0).isReg()) &&
3521
0
      (MI.getOperand(0).getReg() == RISCV::X1)) {
3522
      // c.sspush $rs1
3523
      // Operand: rs1
3524
0
      return true;
3525
0
    } // if
3526
0
      break;
3527
0
    } // case SSPUSH
3528
56.3k
    case RISCV::SUB: {
3529
56.3k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3530
56.3k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3531
56.3k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3532
56.3k
      (MI.getOperand(1).isReg()) &&
3533
56.3k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3534
56.3k
      (MI.getOperand(2).isReg()) &&
3535
56.3k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3536
      // c.sub  $rd, $rs2
3537
      // Operand: rd_wb
3538
      // Operand: rd
3539
      // Operand: rs2
3540
0
      return true;
3541
0
    } // if
3542
56.3k
      break;
3543
56.3k
    } // case SUB
3544
56.3k
    case RISCV::SUBW: {
3545
24.8k
    if (STI.getFeatureBits()[RISCV::Feature64Bit] &&
3546
24.8k
      (STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3547
24.8k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3548
24.8k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3549
24.8k
      (MI.getOperand(1).isReg()) &&
3550
24.8k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3551
24.8k
      (MI.getOperand(2).isReg()) &&
3552
24.8k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3553
      // c.subw $rd, $rs2
3554
      // Operand: rd_wb
3555
      // Operand: rd
3556
      // Operand: rs2
3557
0
      return true;
3558
0
    } // if
3559
24.8k
      break;
3560
24.8k
    } // case SUBW
3561
207k
    case RISCV::SW: {
3562
207k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3563
207k
      (MI.getOperand(0).isReg()) &&
3564
207k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(0).getReg())) &&
3565
207k
      (MI.getOperand(1).isReg()) &&
3566
207k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3567
207k
      MI.getOperand(2).isImm() &&
3568
207k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 8)) {
3569
      // c.sw $rs2, ${imm}(${rs1})
3570
      // Operand: rs2
3571
      // Operand: rs1
3572
      // Operand: imm
3573
0
      return true;
3574
0
    } // if
3575
207k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3576
207k
      (MI.getOperand(0).isReg()) &&
3577
207k
      (RISCVMCRegisterClasses[RISCV::GPRRegClassID].contains(MI.getOperand(0).getReg())) &&
3578
207k
      (MI.getOperand(1).isReg()) &&
3579
207k
      (RISCVMCRegisterClasses[RISCV::SPRegClassID].contains(MI.getOperand(1).getReg())) &&
3580
207k
      MI.getOperand(2).isImm() &&
3581
207k
      RISCVValidateMachineOperand(MI.getOperand(2), &STI, 9)) {
3582
      // c.swsp $rs2, ${imm}(${rs1})
3583
      // Operand: rs2
3584
      // Operand: rs1
3585
      // Operand: imm
3586
0
      return true;
3587
0
    } // if
3588
207k
      break;
3589
207k
    } // case SW
3590
207k
    case RISCV::UNIMP: {
3591
0
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca])) {
3592
      // c.unimp
3593
0
      return true;
3594
0
    } // if
3595
0
      break;
3596
0
    } // case UNIMP
3597
62.5k
    case RISCV::XOR: {
3598
62.5k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3599
62.5k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3600
62.5k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3601
62.5k
      (MI.getOperand(1).isReg()) &&
3602
62.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg())) &&
3603
62.5k
      (MI.getOperand(2).isReg()) &&
3604
62.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg()))) {
3605
      // c.xor  $rd, $rs2
3606
      // Operand: rd_wb
3607
      // Operand: rd
3608
      // Operand: rs2
3609
0
      return true;
3610
0
    } // if
3611
62.5k
    if ((STI.getFeatureBits()[RISCV::FeatureStdExtC] || STI.getFeatureBits()[RISCV::FeatureStdExtZca]) &&
3612
62.5k
      (MI.getOperand(2).isReg()) && (MI.getOperand(0).isReg()) &&
3613
62.5k
      (MI.getOperand(2).getReg() ==  MI.getOperand(0).getReg()) &&
3614
62.5k
      (MI.getOperand(2).isReg()) &&
3615
62.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(2).getReg())) &&
3616
62.5k
      (MI.getOperand(1).isReg()) &&
3617
62.5k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3618
      // c.xor  $rd, $rs2
3619
      // Operand: rd_wb
3620
      // Operand: rd
3621
      // Operand: rs2
3622
0
      return true;
3623
0
    } // if
3624
62.5k
      break;
3625
62.5k
    } // case XOR
3626
133k
    case RISCV::XORI: {
3627
133k
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3628
133k
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3629
133k
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3630
133k
      (MI.getOperand(2).isImm()) &&
3631
133k
      (MI.getOperand(2).getImm() == -1) &&
3632
133k
      (MI.getOperand(1).isReg()) &&
3633
133k
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3634
      // c.not  $rd
3635
      // Operand: rd_wb
3636
      // Operand: rd
3637
0
      return true;
3638
0
    } // if
3639
133k
      break;
3640
133k
    } // case XORI
3641
133k
    case RISCV::ZEXT_H_RV32: {
3642
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3643
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3644
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3645
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3646
0
      (MI.getOperand(1).isReg()) &&
3647
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3648
      // c.zext.h $rd
3649
      // Operand: rd_wb
3650
      // Operand: rd
3651
0
      return true;
3652
0
    } // if
3653
0
      break;
3654
0
    } // case ZEXT_H_RV32
3655
0
    case RISCV::ZEXT_H_RV64: {
3656
0
    if (STI.getFeatureBits()[RISCV::FeatureStdExtZbb] &&
3657
0
      STI.getFeatureBits()[RISCV::FeatureStdExtZcb] &&
3658
0
      (MI.getOperand(1).isReg()) && (MI.getOperand(0).isReg()) &&
3659
0
      (MI.getOperand(1).getReg() ==  MI.getOperand(0).getReg()) &&
3660
0
      (MI.getOperand(1).isReg()) &&
3661
0
      (RISCVMCRegisterClasses[RISCV::GPRCRegClassID].contains(MI.getOperand(1).getReg()))) {
3662
      // c.zext.h $rd
3663
      // Operand: rd_wb
3664
      // Operand: rd
3665
0
      return true;
3666
0
    } // if
3667
3668
0
    } // case ZEXT_H_RV64
3669
7.64M
  } // switch
3670
6.06M
  return false;
3671
7.64M
}
3672
3673
#endif //GEN_CHECK_COMPRESS_INSTR
3674