/src/build/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(0), |
297 | 0 | UINT64_C(0), |
298 | 0 | UINT64_C(0), |
299 | 0 | UINT64_C(0), |
300 | 0 | UINT64_C(0), |
301 | 0 | UINT64_C(0), |
302 | 0 | UINT64_C(0), |
303 | 0 | UINT64_C(0), |
304 | 0 | UINT64_C(0), |
305 | 0 | UINT64_C(0), |
306 | 0 | UINT64_C(0), |
307 | 0 | UINT64_C(0), |
308 | 0 | UINT64_C(0), |
309 | 0 | UINT64_C(0), |
310 | 0 | UINT64_C(0), |
311 | 0 | UINT64_C(0), |
312 | 0 | UINT64_C(0), |
313 | 0 | UINT64_C(0), |
314 | 0 | UINT64_C(0), |
315 | 0 | UINT64_C(0), |
316 | 0 | UINT64_C(0), |
317 | 0 | UINT64_C(0), |
318 | 0 | UINT64_C(0), |
319 | 0 | UINT64_C(0), |
320 | 0 | UINT64_C(0), |
321 | 0 | UINT64_C(0), |
322 | 0 | UINT64_C(0), |
323 | 0 | UINT64_C(0), |
324 | 0 | UINT64_C(0), |
325 | 0 | UINT64_C(0), |
326 | 0 | UINT64_C(0), |
327 | 0 | UINT64_C(0), |
328 | 0 | UINT64_C(0), |
329 | 0 | UINT64_C(0), |
330 | 0 | UINT64_C(0), |
331 | 0 | UINT64_C(0), |
332 | 0 | UINT64_C(0), |
333 | 0 | UINT64_C(0), |
334 | 0 | UINT64_C(0), |
335 | 0 | UINT64_C(0), |
336 | 0 | UINT64_C(0), |
337 | 0 | UINT64_C(0), |
338 | 0 | UINT64_C(0), |
339 | 0 | UINT64_C(0), |
340 | 0 | UINT64_C(0), |
341 | 0 | UINT64_C(0), |
342 | 0 | UINT64_C(0), |
343 | 0 | UINT64_C(0), |
344 | 0 | UINT64_C(0), |
345 | 0 | UINT64_C(0), |
346 | 0 | UINT64_C(0), |
347 | 0 | UINT64_C(0), |
348 | 0 | UINT64_C(0), |
349 | 0 | UINT64_C(0), |
350 | 0 | UINT64_C(0), |
351 | 0 | UINT64_C(0), |
352 | 0 | UINT64_C(0), |
353 | 0 | UINT64_C(0), |
354 | 0 | UINT64_C(0), |
355 | 0 | UINT64_C(0), |
356 | 0 | UINT64_C(0), |
357 | 0 | UINT64_C(0), |
358 | 0 | UINT64_C(0), |
359 | 0 | UINT64_C(0), |
360 | 0 | UINT64_C(0), |
361 | 0 | UINT64_C(0), |
362 | 0 | UINT64_C(0), |
363 | 0 | UINT64_C(0), |
364 | 0 | UINT64_C(0), |
365 | 0 | UINT64_C(0), |
366 | 0 | UINT64_C(0), |
367 | 0 | UINT64_C(0), |
368 | 0 | UINT64_C(0), |
369 | 0 | UINT64_C(0), |
370 | 0 | UINT64_C(0), |
371 | 0 | UINT64_C(0), |
372 | 0 | UINT64_C(0), |
373 | 0 | UINT64_C(0), |
374 | 0 | UINT64_C(0), |
375 | 0 | UINT64_C(0), |
376 | 0 | UINT64_C(0), |
377 | 0 | UINT64_C(0), |
378 | 0 | UINT64_C(0), |
379 | 0 | UINT64_C(0), |
380 | 0 | UINT64_C(0), |
381 | 0 | UINT64_C(0), |
382 | 0 | UINT64_C(0), |
383 | 0 | UINT64_C(0), |
384 | 0 | UINT64_C(0), |
385 | 0 | UINT64_C(0), |
386 | 0 | UINT64_C(0), |
387 | 0 | UINT64_C(0), |
388 | 0 | UINT64_C(0), |
389 | 0 | UINT64_C(0), |
390 | 0 | UINT64_C(0), |
391 | 0 | UINT64_C(0), |
392 | 0 | UINT64_C(0), |
393 | 0 | UINT64_C(0), |
394 | 0 | UINT64_C(0), |
395 | 0 | UINT64_C(0), |
396 | 0 | UINT64_C(0), |
397 | 0 | UINT64_C(0), |
398 | 0 | UINT64_C(0), |
399 | 0 | UINT64_C(0), |
400 | 0 | UINT64_C(0), |
401 | 0 | UINT64_C(0), |
402 | 0 | UINT64_C(0), |
403 | 0 | UINT64_C(0), |
404 | 0 | UINT64_C(0), |
405 | 0 | UINT64_C(0), |
406 | 0 | UINT64_C(0), |
407 | 0 | UINT64_C(0), |
408 | 0 | UINT64_C(0), |
409 | 0 | UINT64_C(0), |
410 | 0 | UINT64_C(0), |
411 | 0 | UINT64_C(0), |
412 | 0 | UINT64_C(0), |
413 | 0 | UINT64_C(0), |
414 | 0 | UINT64_C(0), |
415 | 0 | UINT64_C(0), |
416 | 0 | UINT64_C(0), |
417 | 0 | UINT64_C(0), |
418 | 0 | UINT64_C(0), |
419 | 0 | UINT64_C(0), |
420 | 0 | UINT64_C(0), |
421 | 0 | UINT64_C(0), |
422 | 0 | UINT64_C(0), |
423 | 0 | UINT64_C(0), |
424 | 0 | UINT64_C(0), |
425 | 0 | UINT64_C(0), |
426 | 0 | UINT64_C(0), |
427 | 0 | UINT64_C(0), |
428 | 0 | UINT64_C(0), |
429 | 0 | UINT64_C(0), |
430 | 0 | UINT64_C(0), |
431 | 0 | UINT64_C(0), |
432 | 0 | UINT64_C(0), |
433 | 0 | UINT64_C(0), |
434 | 0 | UINT64_C(0), |
435 | 0 | UINT64_C(0), |
436 | 0 | UINT64_C(0), |
437 | 0 | UINT64_C(0), |
438 | 0 | UINT64_C(0), |
439 | 0 | UINT64_C(0), |
440 | 0 | UINT64_C(0), |
441 | 0 | UINT64_C(0), |
442 | 0 | UINT64_C(0), |
443 | 0 | UINT64_C(0), |
444 | 0 | UINT64_C(0), |
445 | 0 | UINT64_C(0), |
446 | 0 | UINT64_C(0), |
447 | 0 | UINT64_C(0), |
448 | 0 | UINT64_C(0), |
449 | 0 | UINT64_C(0), |
450 | 0 | UINT64_C(0), |
451 | 0 | UINT64_C(0), |
452 | 0 | UINT64_C(0), |
453 | 0 | UINT64_C(0), |
454 | 0 | UINT64_C(0), |
455 | 0 | UINT64_C(0), |
456 | 0 | UINT64_C(0), |
457 | 0 | UINT64_C(0), |
458 | 0 | UINT64_C(0), |
459 | 0 | UINT64_C(0), |
460 | 0 | UINT64_C(0), |
461 | 0 | UINT64_C(0), |
462 | 0 | UINT64_C(0), |
463 | 0 | UINT64_C(0), |
464 | 0 | UINT64_C(0), |
465 | 0 | UINT64_C(0), |
466 | 0 | UINT64_C(0), |
467 | 0 | UINT64_C(0), |
468 | 0 | UINT64_C(0), |
469 | 0 | UINT64_C(0), |
470 | 0 | UINT64_C(0), |
471 | 0 | UINT64_C(0), |
472 | 0 | UINT64_C(0), |
473 | 0 | UINT64_C(0), |
474 | 0 | UINT64_C(0), |
475 | 0 | UINT64_C(0), |
476 | 0 | UINT64_C(0), |
477 | 0 | UINT64_C(0), |
478 | 0 | UINT64_C(0), |
479 | 0 | UINT64_C(0), |
480 | 0 | UINT64_C(0), |
481 | 0 | UINT64_C(0), |
482 | 0 | UINT64_C(0), |
483 | 0 | UINT64_C(0), |
484 | 0 | UINT64_C(0), |
485 | 0 | UINT64_C(0), |
486 | 0 | UINT64_C(0), |
487 | 0 | UINT64_C(0), |
488 | 0 | UINT64_C(0), |
489 | 0 | UINT64_C(0), |
490 | 0 | UINT64_C(0), |
491 | 0 | UINT64_C(0), |
492 | 0 | UINT64_C(0), |
493 | 0 | UINT64_C(0), |
494 | 0 | UINT64_C(0), |
495 | 0 | UINT64_C(0), |
496 | 0 | UINT64_C(0), |
497 | 0 | UINT64_C(0), |
498 | 0 | UINT64_C(0), |
499 | 0 | UINT64_C(0), |
500 | 0 | UINT64_C(0), |
501 | 0 | UINT64_C(0), |
502 | 0 | UINT64_C(0), |
503 | 0 | UINT64_C(0), |
504 | 0 | UINT64_C(0), |
505 | 0 | UINT64_C(0), |
506 | 0 | UINT64_C(0), |
507 | 0 | UINT64_C(0), |
508 | 0 | UINT64_C(0), |
509 | 0 | UINT64_C(0), |
510 | 0 | UINT64_C(0), |
511 | 0 | UINT64_C(0), |
512 | 0 | UINT64_C(0), |
513 | 0 | UINT64_C(0), |
514 | 0 | UINT64_C(0), |
515 | 0 | UINT64_C(0), |
516 | 0 | UINT64_C(0), |
517 | 0 | UINT64_C(0), |
518 | 0 | UINT64_C(0), |
519 | 0 | UINT64_C(0), |
520 | 0 | UINT64_C(0), |
521 | 0 | UINT64_C(0), |
522 | 0 | UINT64_C(0), |
523 | 0 | UINT64_C(0), |
524 | 0 | UINT64_C(0), |
525 | 0 | UINT64_C(0), |
526 | 0 | UINT64_C(0), |
527 | 0 | UINT64_C(0), |
528 | 0 | UINT64_C(0), |
529 | 0 | UINT64_C(0), |
530 | 0 | UINT64_C(0), |
531 | 0 | UINT64_C(0), |
532 | 0 | UINT64_C(0), |
533 | 0 | UINT64_C(0), |
534 | 0 | UINT64_C(0), |
535 | 0 | UINT64_C(0), |
536 | 0 | UINT64_C(0), |
537 | 0 | UINT64_C(0), |
538 | 0 | UINT64_C(0), |
539 | 0 | UINT64_C(0), |
540 | 0 | UINT64_C(0), |
541 | 0 | UINT64_C(0), |
542 | 0 | UINT64_C(0), |
543 | 0 | UINT64_C(0), |
544 | 0 | UINT64_C(0), |
545 | 0 | UINT64_C(0), |
546 | 0 | UINT64_C(0), |
547 | 0 | UINT64_C(0), |
548 | 0 | UINT64_C(0), |
549 | 0 | UINT64_C(0), |
550 | 0 | UINT64_C(0), |
551 | 0 | UINT64_C(0), |
552 | 0 | UINT64_C(0), |
553 | 0 | UINT64_C(0), |
554 | 0 | UINT64_C(0), |
555 | 0 | UINT64_C(0), |
556 | 0 | UINT64_C(0), |
557 | 0 | UINT64_C(0), |
558 | 0 | UINT64_C(0), |
559 | 0 | UINT64_C(0), |
560 | 0 | UINT64_C(0), |
561 | 0 | UINT64_C(0), |
562 | 0 | UINT64_C(0), |
563 | 0 | UINT64_C(0), |
564 | 0 | UINT64_C(0), |
565 | 0 | UINT64_C(0), |
566 | 0 | UINT64_C(0), |
567 | 0 | UINT64_C(0), |
568 | 0 | UINT64_C(0), |
569 | 0 | UINT64_C(0), |
570 | 0 | UINT64_C(0), |
571 | 0 | UINT64_C(0), |
572 | 0 | UINT64_C(0), |
573 | 0 | UINT64_C(0), |
574 | 0 | UINT64_C(0), |
575 | 0 | UINT64_C(0), |
576 | 0 | UINT64_C(0), |
577 | 0 | UINT64_C(0), |
578 | 0 | UINT64_C(0), |
579 | 0 | UINT64_C(0), |
580 | 0 | UINT64_C(0), |
581 | 0 | UINT64_C(0), |
582 | 0 | UINT64_C(0), |
583 | 0 | UINT64_C(0), |
584 | 0 | UINT64_C(0), |
585 | 0 | UINT64_C(0), |
586 | 0 | UINT64_C(0), |
587 | 0 | UINT64_C(0), |
588 | 0 | UINT64_C(0), |
589 | 0 | UINT64_C(0), |
590 | 0 | UINT64_C(0), |
591 | 0 | UINT64_C(0), |
592 | 0 | UINT64_C(0), |
593 | 0 | UINT64_C(0), |
594 | 0 | UINT64_C(0), |
595 | 0 | UINT64_C(0), |
596 | 0 | UINT64_C(0), |
597 | 0 | UINT64_C(0), |
598 | 0 | UINT64_C(0), |
599 | 0 | UINT64_C(0), |
600 | 0 | UINT64_C(0), |
601 | 0 | UINT64_C(0), |
602 | 0 | UINT64_C(0), |
603 | 0 | UINT64_C(0), |
604 | 0 | UINT64_C(0), |
605 | 0 | UINT64_C(0), |
606 | 0 | UINT64_C(0), |
607 | 0 | UINT64_C(0), |
608 | 0 | UINT64_C(0), |
609 | 0 | UINT64_C(0), |
610 | 0 | UINT64_C(0), |
611 | 0 | UINT64_C(0), |
612 | 0 | UINT64_C(0), |
613 | 0 | UINT64_C(0), |
614 | 0 | UINT64_C(0), |
615 | 0 | UINT64_C(0), |
616 | 0 | UINT64_C(0), |
617 | 0 | UINT64_C(0), |
618 | 0 | UINT64_C(0), |
619 | 0 | UINT64_C(0), |
620 | 0 | UINT64_C(0), |
621 | 0 | UINT64_C(0), |
622 | 0 | UINT64_C(0), |
623 | 0 | UINT64_C(0), |
624 | 0 | UINT64_C(0), |
625 | 0 | UINT64_C(0), |
626 | 0 | UINT64_C(0), |
627 | 0 | UINT64_C(0), |
628 | 0 | UINT64_C(0), |
629 | 0 | UINT64_C(0), |
630 | 0 | UINT64_C(0), |
631 | 0 | UINT64_C(0), |
632 | 0 | UINT64_C(0), |
633 | 0 | UINT64_C(0), |
634 | 0 | UINT64_C(0), |
635 | 0 | UINT64_C(0), |
636 | 0 | UINT64_C(0), |
637 | 0 | UINT64_C(0), |
638 | 0 | UINT64_C(0), |
639 | 0 | UINT64_C(0), |
640 | 0 | UINT64_C(0), |
641 | 0 | UINT64_C(0), |
642 | 0 | UINT64_C(0), |
643 | 0 | UINT64_C(0), |
644 | 0 | UINT64_C(0), |
645 | 0 | UINT64_C(0), |
646 | 0 | UINT64_C(0), |
647 | 0 | UINT64_C(0), |
648 | 0 | UINT64_C(0), |
649 | 0 | UINT64_C(0), |
650 | 0 | UINT64_C(0), |
651 | 0 | UINT64_C(0), |
652 | 0 | UINT64_C(0), |
653 | 0 | UINT64_C(0), |
654 | 0 | UINT64_C(0), |
655 | 0 | UINT64_C(0), |
656 | 0 | UINT64_C(0), |
657 | 0 | UINT64_C(0), |
658 | 0 | UINT64_C(0), |
659 | 0 | UINT64_C(0), |
660 | 0 | UINT64_C(0), |
661 | 0 | UINT64_C(0), |
662 | 0 | UINT64_C(0), |
663 | 0 | UINT64_C(0), |
664 | 0 | UINT64_C(0), |
665 | 0 | UINT64_C(0), |
666 | 0 | UINT64_C(0), |
667 | 0 | UINT64_C(0), |
668 | 0 | UINT64_C(0), |
669 | 0 | UINT64_C(0), |
670 | 0 | UINT64_C(0), |
671 | 0 | UINT64_C(0), |
672 | 0 | UINT64_C(0), |
673 | 0 | UINT64_C(0), |
674 | 0 | UINT64_C(0), |
675 | 0 | UINT64_C(0), |
676 | 0 | UINT64_C(0), |
677 | 0 | UINT64_C(0), |
678 | 0 | UINT64_C(0), |
679 | 0 | UINT64_C(0), |
680 | 0 | UINT64_C(0), |
681 | 0 | UINT64_C(0), |
682 | 0 | UINT64_C(0), |
683 | 0 | UINT64_C(0), |
684 | 0 | UINT64_C(0), |
685 | 0 | UINT64_C(0), |
686 | 0 | UINT64_C(0), |
687 | 0 | UINT64_C(0), |
688 | 0 | UINT64_C(0), |
689 | 0 | UINT64_C(0), |
690 | 0 | UINT64_C(0), |
691 | 0 | UINT64_C(0), |
692 | 0 | UINT64_C(0), |
693 | 0 | UINT64_C(0), |
694 | 0 | UINT64_C(0), |
695 | 0 | UINT64_C(0), |
696 | 0 | UINT64_C(0), |
697 | 0 | UINT64_C(0), |
698 | 0 | UINT64_C(0), |
699 | 0 | UINT64_C(0), |
700 | 0 | UINT64_C(0), |
701 | 0 | UINT64_C(0), |
702 | 0 | UINT64_C(0), |
703 | 0 | UINT64_C(0), |
704 | 0 | UINT64_C(0), |
705 | 0 | UINT64_C(0), |
706 | 0 | UINT64_C(0), |
707 | 0 | UINT64_C(0), |
708 | 0 | UINT64_C(0), |
709 | 0 | UINT64_C(0), |
710 | 0 | UINT64_C(0), |
711 | 0 | UINT64_C(0), |
712 | 0 | UINT64_C(0), |
713 | 0 | UINT64_C(0), |
714 | 0 | UINT64_C(0), |
715 | 0 | UINT64_C(0), |
716 | 0 | UINT64_C(0), |
717 | 0 | UINT64_C(0), |
718 | 0 | UINT64_C(0), |
719 | 0 | UINT64_C(0), |
720 | 0 | UINT64_C(0), |
721 | 0 | UINT64_C(0), |
722 | 0 | UINT64_C(0), |
723 | 0 | UINT64_C(0), |
724 | 0 | UINT64_C(0), |
725 | 0 | UINT64_C(0), |
726 | 0 | UINT64_C(0), |
727 | 0 | UINT64_C(0), |
728 | 0 | UINT64_C(0), |
729 | 0 | UINT64_C(0), |
730 | 0 | UINT64_C(0), |
731 | 0 | UINT64_C(0), |
732 | 0 | UINT64_C(0), |
733 | 0 | UINT64_C(0), |
734 | 0 | UINT64_C(0), |
735 | 0 | UINT64_C(0), |
736 | 0 | UINT64_C(0), |
737 | 0 | UINT64_C(0), |
738 | 0 | UINT64_C(0), |
739 | 0 | UINT64_C(0), |
740 | 0 | UINT64_C(0), |
741 | 0 | UINT64_C(0), |
742 | 0 | UINT64_C(0), |
743 | 0 | UINT64_C(0), |
744 | 0 | UINT64_C(0), |
745 | 0 | UINT64_C(0), |
746 | 0 | UINT64_C(0), |
747 | 0 | UINT64_C(0), |
748 | 0 | UINT64_C(0), |
749 | 0 | UINT64_C(0), |
750 | 0 | UINT64_C(0), |
751 | 0 | UINT64_C(0), |
752 | 0 | UINT64_C(0), |
753 | 0 | UINT64_C(0), |
754 | 0 | UINT64_C(0), |
755 | 0 | UINT64_C(0), |
756 | 0 | UINT64_C(0), |
757 | 0 | UINT64_C(0), |
758 | 0 | UINT64_C(0), |
759 | 0 | UINT64_C(0), |
760 | 0 | UINT64_C(0), |
761 | 0 | UINT64_C(0), |
762 | 0 | UINT64_C(0), |
763 | 0 | UINT64_C(0), |
764 | 0 | UINT64_C(0), |
765 | 0 | UINT64_C(0), |
766 | 0 | UINT64_C(0), |
767 | 0 | UINT64_C(0), |
768 | 0 | UINT64_C(0), |
769 | 0 | UINT64_C(0), |
770 | 0 | UINT64_C(0), |
771 | 0 | UINT64_C(0), |
772 | 0 | UINT64_C(0), |
773 | 0 | UINT64_C(0), |
774 | 0 | UINT64_C(0), |
775 | 0 | UINT64_C(0), |
776 | 0 | UINT64_C(0), |
777 | 0 | UINT64_C(0), |
778 | 0 | UINT64_C(0), |
779 | 0 | UINT64_C(0), |
780 | 0 | UINT64_C(0), |
781 | 0 | UINT64_C(0), |
782 | 0 | UINT64_C(0), |
783 | 0 | UINT64_C(0), |
784 | 0 | UINT64_C(0), |
785 | 0 | UINT64_C(0), |
786 | 0 | UINT64_C(0), |
787 | 0 | UINT64_C(0), |
788 | 0 | UINT64_C(0), |
789 | 0 | UINT64_C(0), |
790 | 0 | UINT64_C(0), |
791 | 0 | UINT64_C(0), |
792 | 0 | UINT64_C(0), |
793 | 0 | UINT64_C(0), |
794 | 0 | UINT64_C(0), |
795 | 0 | UINT64_C(0), |
796 | 0 | UINT64_C(0), |
797 | 0 | UINT64_C(0), |
798 | 0 | UINT64_C(0), |
799 | 0 | UINT64_C(0), |
800 | 0 | UINT64_C(0), |
801 | 0 | UINT64_C(0), |
802 | 0 | UINT64_C(0), |
803 | 0 | UINT64_C(0), |
804 | 0 | UINT64_C(0), |
805 | 0 | UINT64_C(0), |
806 | 0 | UINT64_C(0), |
807 | 0 | UINT64_C(0), |
808 | 0 | UINT64_C(0), |
809 | 0 | UINT64_C(0), |
810 | 0 | UINT64_C(0), |
811 | 0 | UINT64_C(0), |
812 | 0 | UINT64_C(0), |
813 | 0 | UINT64_C(0), |
814 | 0 | UINT64_C(0), |
815 | 0 | UINT64_C(0), |
816 | 0 | UINT64_C(0), |
817 | 0 | UINT64_C(0), |
818 | 0 | UINT64_C(0), |
819 | 0 | UINT64_C(0), |
820 | 0 | UINT64_C(0), |
821 | 0 | UINT64_C(0), |
822 | 0 | UINT64_C(0), |
823 | 0 | UINT64_C(0), |
824 | 0 | UINT64_C(0), |
825 | 0 | UINT64_C(0), |
826 | 0 | UINT64_C(0), |
827 | 0 | UINT64_C(0), |
828 | 0 | UINT64_C(0), |
829 | 0 | UINT64_C(0), |
830 | 0 | UINT64_C(0), |
831 | 0 | UINT64_C(0), |
832 | 0 | UINT64_C(0), |
833 | 0 | UINT64_C(0), |
834 | 0 | UINT64_C(0), |
835 | 0 | UINT64_C(0), |
836 | 0 | UINT64_C(0), |
837 | 0 | UINT64_C(0), |
838 | 0 | UINT64_C(0), |
839 | 0 | UINT64_C(0), |
840 | 0 | UINT64_C(0), |
841 | 0 | UINT64_C(0), |
842 | 0 | UINT64_C(0), |
843 | 0 | UINT64_C(0), |
844 | 0 | UINT64_C(0), |
845 | 0 | UINT64_C(0), |
846 | 0 | UINT64_C(0), |
847 | 0 | UINT64_C(0), |
848 | 0 | UINT64_C(0), |
849 | 0 | UINT64_C(0), |
850 | 0 | UINT64_C(0), |
851 | 0 | UINT64_C(0), |
852 | 0 | UINT64_C(0), |
853 | 0 | UINT64_C(0), |
854 | 0 | UINT64_C(0), |
855 | 0 | UINT64_C(0), |
856 | 0 | UINT64_C(0), |
857 | 0 | UINT64_C(0), |
858 | 0 | UINT64_C(0), |
859 | 0 | UINT64_C(0), |
860 | 0 | UINT64_C(0), |
861 | 0 | UINT64_C(0), |
862 | 0 | UINT64_C(0), |
863 | 0 | UINT64_C(0), |
864 | 0 | UINT64_C(0), |
865 | 0 | UINT64_C(0), |
866 | 0 | UINT64_C(0), |
867 | 0 | UINT64_C(0), |
868 | 0 | UINT64_C(0), |
869 | 0 | UINT64_C(0), |
870 | 0 | UINT64_C(0), |
871 | 0 | UINT64_C(0), |
872 | 0 | UINT64_C(0), |
873 | 0 | UINT64_C(0), |
874 | 0 | UINT64_C(0), |
875 | 0 | UINT64_C(0), |
876 | 0 | UINT64_C(0), |
877 | 0 | UINT64_C(0), |
878 | 0 | UINT64_C(0), |
879 | 0 | UINT64_C(0), |
880 | 0 | UINT64_C(0), |
881 | 0 | UINT64_C(0), |
882 | 0 | UINT64_C(0), |
883 | 0 | UINT64_C(0), |
884 | 0 | UINT64_C(0), |
885 | 0 | UINT64_C(0), |
886 | 0 | UINT64_C(0), |
887 | 0 | UINT64_C(0), |
888 | 0 | UINT64_C(0), |
889 | 0 | UINT64_C(0), |
890 | 0 | UINT64_C(0), |
891 | 0 | UINT64_C(0), |
892 | 0 | UINT64_C(0), |
893 | 0 | UINT64_C(0), |
894 | 0 | UINT64_C(0), |
895 | 0 | UINT64_C(0), |
896 | 0 | UINT64_C(0), |
897 | 0 | UINT64_C(0), |
898 | 0 | UINT64_C(0), |
899 | 0 | UINT64_C(0), |
900 | 0 | UINT64_C(0), |
901 | 0 | UINT64_C(0), |
902 | 0 | UINT64_C(0), |
903 | 0 | UINT64_C(0), |
904 | 0 | UINT64_C(0), |
905 | 0 | UINT64_C(0), |
906 | 0 | UINT64_C(0), |
907 | 0 | UINT64_C(0), |
908 | 0 | UINT64_C(0), |
909 | 0 | UINT64_C(0), |
910 | 0 | UINT64_C(0), |
911 | 0 | UINT64_C(0), |
912 | 0 | UINT64_C(0), |
913 | 0 | UINT64_C(0), |
914 | 0 | UINT64_C(0), |
915 | 0 | UINT64_C(0), |
916 | 0 | UINT64_C(0), |
917 | 0 | UINT64_C(0), |
918 | 0 | UINT64_C(0), |
919 | 0 | UINT64_C(0), |
920 | 0 | UINT64_C(0), |
921 | 0 | UINT64_C(0), |
922 | 0 | UINT64_C(0), |
923 | 0 | UINT64_C(0), |
924 | 0 | UINT64_C(0), |
925 | 0 | UINT64_C(0), |
926 | 0 | UINT64_C(0), |
927 | 0 | UINT64_C(0), |
928 | 0 | UINT64_C(0), |
929 | 0 | UINT64_C(0), |
930 | 0 | UINT64_C(0), |
931 | 0 | UINT64_C(0), |
932 | 0 | UINT64_C(0), |
933 | 0 | UINT64_C(0), |
934 | 0 | UINT64_C(0), |
935 | 0 | UINT64_C(0), |
936 | 0 | UINT64_C(0), |
937 | 0 | UINT64_C(0), |
938 | 0 | UINT64_C(0), |
939 | 0 | UINT64_C(0), |
940 | 0 | UINT64_C(0), |
941 | 0 | UINT64_C(0), |
942 | 0 | UINT64_C(0), |
943 | 0 | UINT64_C(0), |
944 | 0 | UINT64_C(0), |
945 | 0 | UINT64_C(0), |
946 | 0 | UINT64_C(0), |
947 | 0 | UINT64_C(0), |
948 | 0 | UINT64_C(0), |
949 | 0 | UINT64_C(0), |
950 | 0 | UINT64_C(0), |
951 | 0 | UINT64_C(0), |
952 | 0 | UINT64_C(0), |
953 | 0 | UINT64_C(0), |
954 | 0 | UINT64_C(0), |
955 | 0 | UINT64_C(0), |
956 | 0 | UINT64_C(0), |
957 | 0 | UINT64_C(0), |
958 | 0 | UINT64_C(0), |
959 | 0 | UINT64_C(0), |
960 | 0 | UINT64_C(0), |
961 | 0 | UINT64_C(0), |
962 | 0 | UINT64_C(0), |
963 | 0 | UINT64_C(0), |
964 | 0 | UINT64_C(0), |
965 | 0 | UINT64_C(0), |
966 | 0 | UINT64_C(0), |
967 | 0 | UINT64_C(0), |
968 | 0 | UINT64_C(0), |
969 | 0 | UINT64_C(0), |
970 | 0 | UINT64_C(0), |
971 | 0 | UINT64_C(0), |
972 | 0 | UINT64_C(0), |
973 | 0 | UINT64_C(0), |
974 | 0 | UINT64_C(0), |
975 | 0 | UINT64_C(0), |
976 | 0 | UINT64_C(0), |
977 | 0 | UINT64_C(0), |
978 | 0 | UINT64_C(0), |
979 | 0 | UINT64_C(0), |
980 | 0 | UINT64_C(0), |
981 | 0 | UINT64_C(0), |
982 | 0 | UINT64_C(0), |
983 | 0 | UINT64_C(0), |
984 | 0 | UINT64_C(0), |
985 | 0 | UINT64_C(0), |
986 | 0 | UINT64_C(0), |
987 | 0 | UINT64_C(0), |
988 | 0 | UINT64_C(0), |
989 | 0 | UINT64_C(0), |
990 | 0 | UINT64_C(0), |
991 | 0 | UINT64_C(0), |
992 | 0 | UINT64_C(0), |
993 | 0 | UINT64_C(0), |
994 | 0 | UINT64_C(0), |
995 | 0 | UINT64_C(0), |
996 | 0 | UINT64_C(0), |
997 | 0 | UINT64_C(0), |
998 | 0 | UINT64_C(0), |
999 | 0 | UINT64_C(0), |
1000 | 0 | UINT64_C(0), |
1001 | 0 | UINT64_C(0), |
1002 | 0 | UINT64_C(0), |
1003 | 0 | UINT64_C(0), |
1004 | 0 | UINT64_C(0), |
1005 | 0 | UINT64_C(0), |
1006 | 0 | UINT64_C(0), |
1007 | 0 | UINT64_C(0), |
1008 | 0 | UINT64_C(0), |
1009 | 0 | UINT64_C(0), |
1010 | 0 | UINT64_C(0), |
1011 | 0 | UINT64_C(0), |
1012 | 0 | UINT64_C(0), |
1013 | 0 | UINT64_C(0), |
1014 | 0 | UINT64_C(0), |
1015 | 0 | UINT64_C(0), |
1016 | 0 | UINT64_C(0), |
1017 | 0 | UINT64_C(0), |
1018 | 0 | UINT64_C(0), |
1019 | 0 | UINT64_C(0), |
1020 | 0 | UINT64_C(0), |
1021 | 0 | UINT64_C(0), |
1022 | 0 | UINT64_C(0), |
1023 | 0 | UINT64_C(0), |
1024 | 0 | UINT64_C(0), |
1025 | 0 | UINT64_C(0), |
1026 | 0 | UINT64_C(0), |
1027 | 0 | UINT64_C(0), |
1028 | 0 | UINT64_C(0), |
1029 | 0 | UINT64_C(0), |
1030 | 0 | UINT64_C(0), |
1031 | 0 | UINT64_C(0), |
1032 | 0 | UINT64_C(0), |
1033 | 0 | UINT64_C(0), |
1034 | 0 | UINT64_C(0), |
1035 | 0 | UINT64_C(0), |
1036 | 0 | UINT64_C(0), |
1037 | 0 | UINT64_C(0), |
1038 | 0 | UINT64_C(0), |
1039 | 0 | UINT64_C(0), |
1040 | 0 | UINT64_C(0), |
1041 | 0 | UINT64_C(0), |
1042 | 0 | UINT64_C(0), |
1043 | 0 | UINT64_C(0), |
1044 | 0 | UINT64_C(0), |
1045 | 0 | UINT64_C(0), |
1046 | 0 | UINT64_C(0), |
1047 | 0 | UINT64_C(0), |
1048 | 0 | UINT64_C(0), |
1049 | 0 | UINT64_C(0), |
1050 | 0 | UINT64_C(0), |
1051 | 0 | UINT64_C(0), |
1052 | 0 | UINT64_C(0), |
1053 | 0 | UINT64_C(0), |
1054 | 0 | UINT64_C(0), |
1055 | 0 | UINT64_C(0), |
1056 | 0 | UINT64_C(0), |
1057 | 0 | UINT64_C(0), |
1058 | 0 | UINT64_C(0), |
1059 | 0 | UINT64_C(0), |
1060 | 0 | UINT64_C(0), |
1061 | 0 | UINT64_C(0), |
1062 | 0 | UINT64_C(0), |
1063 | 0 | UINT64_C(0), |
1064 | 0 | UINT64_C(0), |
1065 | 0 | UINT64_C(0), |
1066 | 0 | UINT64_C(0), |
1067 | 0 | UINT64_C(0), |
1068 | 0 | UINT64_C(0), |
1069 | 0 | UINT64_C(0), |
1070 | 0 | UINT64_C(0), |
1071 | 0 | UINT64_C(0), |
1072 | 0 | UINT64_C(0), |
1073 | 0 | UINT64_C(0), |
1074 | 0 | UINT64_C(0), |
1075 | 0 | UINT64_C(0), |
1076 | 0 | UINT64_C(0), |
1077 | 0 | UINT64_C(0), |
1078 | 0 | UINT64_C(0), |
1079 | 0 | UINT64_C(0), |
1080 | 0 | UINT64_C(0), |
1081 | 0 | UINT64_C(0), |
1082 | 0 | UINT64_C(0), |
1083 | 0 | UINT64_C(0), |
1084 | 0 | UINT64_C(0), |
1085 | 0 | UINT64_C(0), |
1086 | 0 | UINT64_C(0), |
1087 | 0 | UINT64_C(0), |
1088 | 0 | UINT64_C(0), |
1089 | 0 | UINT64_C(0), |
1090 | 0 | UINT64_C(0), |
1091 | 0 | UINT64_C(0), |
1092 | 0 | UINT64_C(0), |
1093 | 0 | UINT64_C(0), |
1094 | 0 | UINT64_C(0), |
1095 | 0 | UINT64_C(0), |
1096 | 0 | UINT64_C(0), |
1097 | 0 | UINT64_C(0), |
1098 | 0 | UINT64_C(0), |
1099 | 0 | UINT64_C(0), |
1100 | 0 | UINT64_C(0), |
1101 | 0 | UINT64_C(0), |
1102 | 0 | UINT64_C(0), |
1103 | 0 | UINT64_C(0), |
1104 | 0 | UINT64_C(0), |
1105 | 0 | UINT64_C(0), |
1106 | 0 | UINT64_C(0), |
1107 | 0 | UINT64_C(0), |
1108 | 0 | UINT64_C(0), |
1109 | 0 | UINT64_C(0), |
1110 | 0 | UINT64_C(0), |
1111 | 0 | UINT64_C(0), |
1112 | 0 | UINT64_C(0), |
1113 | 0 | UINT64_C(0), |
1114 | 0 | UINT64_C(0), |
1115 | 0 | UINT64_C(0), |
1116 | 0 | UINT64_C(0), |
1117 | 0 | UINT64_C(0), |
1118 | 0 | UINT64_C(0), |
1119 | 0 | UINT64_C(0), |
1120 | 0 | UINT64_C(0), |
1121 | 0 | UINT64_C(0), |
1122 | 0 | UINT64_C(0), |
1123 | 0 | UINT64_C(0), |
1124 | 0 | UINT64_C(0), |
1125 | 0 | UINT64_C(0), |
1126 | 0 | UINT64_C(0), |
1127 | 0 | UINT64_C(0), |
1128 | 0 | UINT64_C(0), |
1129 | 0 | UINT64_C(0), |
1130 | 0 | UINT64_C(0), |
1131 | 0 | UINT64_C(0), |
1132 | 0 | UINT64_C(0), |
1133 | 0 | UINT64_C(0), |
1134 | 0 | UINT64_C(0), |
1135 | 0 | UINT64_C(0), |
1136 | 0 | UINT64_C(0), |
1137 | 0 | UINT64_C(0), |
1138 | 0 | UINT64_C(0), |
1139 | 0 | UINT64_C(0), |
1140 | 0 | UINT64_C(0), |
1141 | 0 | UINT64_C(0), |
1142 | 0 | UINT64_C(0), |
1143 | 0 | UINT64_C(0), |
1144 | 0 | UINT64_C(0), |
1145 | 0 | UINT64_C(0), |
1146 | 0 | UINT64_C(0), |
1147 | 0 | UINT64_C(0), |
1148 | 0 | UINT64_C(0), |
1149 | 0 | UINT64_C(0), |
1150 | 0 | UINT64_C(0), |
1151 | 0 | UINT64_C(0), |
1152 | 0 | UINT64_C(0), |
1153 | 0 | UINT64_C(0), |
1154 | 0 | UINT64_C(0), |
1155 | 0 | UINT64_C(0), |
1156 | 0 | UINT64_C(0), |
1157 | 0 | UINT64_C(0), |
1158 | 0 | UINT64_C(0), |
1159 | 0 | UINT64_C(0), |
1160 | 0 | UINT64_C(0), |
1161 | 0 | UINT64_C(0), |
1162 | 0 | UINT64_C(0), |
1163 | 0 | UINT64_C(0), |
1164 | 0 | UINT64_C(0), |
1165 | 0 | UINT64_C(0), |
1166 | 0 | UINT64_C(0), |
1167 | 0 | UINT64_C(0), |
1168 | 0 | UINT64_C(0), |
1169 | 0 | UINT64_C(0), |
1170 | 0 | UINT64_C(0), |
1171 | 0 | UINT64_C(0), |
1172 | 0 | UINT64_C(0), |
1173 | 0 | UINT64_C(0), |
1174 | 0 | UINT64_C(0), |
1175 | 0 | UINT64_C(0), |
1176 | 0 | UINT64_C(0), |
1177 | 0 | UINT64_C(0), |
1178 | 0 | UINT64_C(0), |
1179 | 0 | UINT64_C(0), |
1180 | 0 | UINT64_C(0), |
1181 | 0 | UINT64_C(0), |
1182 | 0 | UINT64_C(0), |
1183 | 0 | UINT64_C(0), |
1184 | 0 | UINT64_C(0), |
1185 | 0 | UINT64_C(0), |
1186 | 0 | UINT64_C(0), |
1187 | 0 | UINT64_C(0), |
1188 | 0 | UINT64_C(0), |
1189 | 0 | UINT64_C(0), |
1190 | 0 | UINT64_C(0), |
1191 | 0 | UINT64_C(0), |
1192 | 0 | UINT64_C(0), |
1193 | 0 | UINT64_C(0), |
1194 | 0 | UINT64_C(0), |
1195 | 0 | UINT64_C(0), |
1196 | 0 | UINT64_C(0), |
1197 | 0 | UINT64_C(0), |
1198 | 0 | UINT64_C(0), |
1199 | 0 | UINT64_C(0), |
1200 | 0 | UINT64_C(0), |
1201 | 0 | UINT64_C(0), |
1202 | 0 | UINT64_C(0), |
1203 | 0 | UINT64_C(0), |
1204 | 0 | UINT64_C(0), |
1205 | 0 | UINT64_C(0), |
1206 | 0 | UINT64_C(0), |
1207 | 0 | UINT64_C(0), |
1208 | 0 | UINT64_C(0), |
1209 | 0 | UINT64_C(0), |
1210 | 0 | UINT64_C(0), |
1211 | 0 | UINT64_C(0), |
1212 | 0 | UINT64_C(0), |
1213 | 0 | UINT64_C(0), |
1214 | 0 | UINT64_C(0), |
1215 | 0 | UINT64_C(0), |
1216 | 0 | UINT64_C(0), |
1217 | 0 | UINT64_C(0), |
1218 | 0 | UINT64_C(0), |
1219 | 0 | UINT64_C(0), |
1220 | 0 | UINT64_C(0), |
1221 | 0 | UINT64_C(0), |
1222 | 0 | UINT64_C(0), |
1223 | 0 | UINT64_C(0), |
1224 | 0 | UINT64_C(0), |
1225 | 0 | UINT64_C(0), |
1226 | 0 | UINT64_C(0), |
1227 | 0 | UINT64_C(0), |
1228 | 0 | UINT64_C(0), |
1229 | 0 | UINT64_C(0), |
1230 | 0 | UINT64_C(0), |
1231 | 0 | UINT64_C(0), |
1232 | 0 | UINT64_C(0), |
1233 | 0 | UINT64_C(0), |
1234 | 0 | UINT64_C(0), |
1235 | 0 | UINT64_C(0), |
1236 | 0 | UINT64_C(0), |
1237 | 0 | UINT64_C(0), |
1238 | 0 | UINT64_C(0), |
1239 | 0 | UINT64_C(0), |
1240 | 0 | UINT64_C(0), |
1241 | 0 | UINT64_C(0), |
1242 | 0 | UINT64_C(0), |
1243 | 0 | UINT64_C(0), |
1244 | 0 | UINT64_C(0), |
1245 | 0 | UINT64_C(0), |
1246 | 0 | UINT64_C(0), |
1247 | 0 | UINT64_C(0), |
1248 | 0 | UINT64_C(0), |
1249 | 0 | UINT64_C(0), |
1250 | 0 | UINT64_C(0), |
1251 | 0 | UINT64_C(0), |
1252 | 0 | UINT64_C(0), |
1253 | 0 | UINT64_C(0), |
1254 | 0 | UINT64_C(0), |
1255 | 0 | UINT64_C(0), |
1256 | 0 | UINT64_C(0), |
1257 | 0 | UINT64_C(0), |
1258 | 0 | UINT64_C(0), |
1259 | 0 | UINT64_C(0), |
1260 | 0 | UINT64_C(0), |
1261 | 0 | UINT64_C(0), |
1262 | 0 | UINT64_C(0), |
1263 | 0 | UINT64_C(0), |
1264 | 0 | UINT64_C(0), |
1265 | 0 | UINT64_C(0), |
1266 | 0 | UINT64_C(0), |
1267 | 0 | UINT64_C(0), |
1268 | 0 | UINT64_C(0), |
1269 | 0 | UINT64_C(0), |
1270 | 0 | UINT64_C(0), |
1271 | 0 | UINT64_C(0), |
1272 | 0 | UINT64_C(0), |
1273 | 0 | UINT64_C(0), |
1274 | 0 | UINT64_C(0), |
1275 | 0 | UINT64_C(0), |
1276 | 0 | UINT64_C(0), |
1277 | 0 | UINT64_C(0), |
1278 | 0 | UINT64_C(0), |
1279 | 0 | UINT64_C(0), |
1280 | 0 | UINT64_C(0), |
1281 | 0 | UINT64_C(0), |
1282 | 0 | UINT64_C(0), |
1283 | 0 | UINT64_C(0), |
1284 | 0 | UINT64_C(0), |
1285 | 0 | UINT64_C(0), |
1286 | 0 | UINT64_C(0), |
1287 | 0 | UINT64_C(0), |
1288 | 0 | UINT64_C(0), |
1289 | 0 | UINT64_C(0), |
1290 | 0 | UINT64_C(0), |
1291 | 0 | UINT64_C(0), |
1292 | 0 | UINT64_C(0), |
1293 | 0 | UINT64_C(0), |
1294 | 0 | UINT64_C(0), |
1295 | 0 | UINT64_C(0), |
1296 | 0 | UINT64_C(0), |
1297 | 0 | UINT64_C(0), |
1298 | 0 | UINT64_C(0), |
1299 | 0 | UINT64_C(0), |
1300 | 0 | UINT64_C(0), |
1301 | 0 | UINT64_C(0), |
1302 | 0 | UINT64_C(0), |
1303 | 0 | UINT64_C(0), |
1304 | 0 | UINT64_C(0), |
1305 | 0 | UINT64_C(0), |
1306 | 0 | UINT64_C(0), |
1307 | 0 | UINT64_C(0), |
1308 | 0 | UINT64_C(0), |
1309 | 0 | UINT64_C(0), |
1310 | 0 | UINT64_C(0), |
1311 | 0 | UINT64_C(0), |
1312 | 0 | UINT64_C(0), |
1313 | 0 | UINT64_C(0), |
1314 | 0 | UINT64_C(0), |
1315 | 0 | UINT64_C(0), |
1316 | 0 | UINT64_C(0), |
1317 | 0 | UINT64_C(0), |
1318 | 0 | UINT64_C(0), |
1319 | 0 | UINT64_C(0), |
1320 | 0 | UINT64_C(0), |
1321 | 0 | UINT64_C(0), |
1322 | 0 | UINT64_C(0), |
1323 | 0 | UINT64_C(0), |
1324 | 0 | UINT64_C(0), |
1325 | 0 | UINT64_C(0), |
1326 | 0 | UINT64_C(0), |
1327 | 0 | UINT64_C(0), |
1328 | 0 | UINT64_C(0), |
1329 | 0 | UINT64_C(0), |
1330 | 0 | UINT64_C(0), |
1331 | 0 | UINT64_C(0), |
1332 | 0 | UINT64_C(0), |
1333 | 0 | UINT64_C(0), |
1334 | 0 | UINT64_C(0), |
1335 | 0 | UINT64_C(0), |
1336 | 0 | UINT64_C(0), |
1337 | 0 | UINT64_C(0), |
1338 | 0 | UINT64_C(0), |
1339 | 0 | UINT64_C(0), |
1340 | 0 | UINT64_C(0), |
1341 | 0 | UINT64_C(0), |
1342 | 0 | UINT64_C(0), |
1343 | 0 | UINT64_C(0), |
1344 | 0 | UINT64_C(0), |
1345 | 0 | UINT64_C(0), |
1346 | 0 | UINT64_C(0), |
1347 | 0 | UINT64_C(0), |
1348 | 0 | UINT64_C(0), |
1349 | 0 | UINT64_C(0), |
1350 | 0 | UINT64_C(0), |
1351 | 0 | UINT64_C(0), |
1352 | 0 | UINT64_C(0), |
1353 | 0 | UINT64_C(0), |
1354 | 0 | UINT64_C(0), |
1355 | 0 | UINT64_C(0), |
1356 | 0 | UINT64_C(0), |
1357 | 0 | UINT64_C(0), |
1358 | 0 | UINT64_C(0), |
1359 | 0 | UINT64_C(0), |
1360 | 0 | UINT64_C(0), |
1361 | 0 | UINT64_C(0), |
1362 | 0 | UINT64_C(0), |
1363 | 0 | UINT64_C(0), |
1364 | 0 | UINT64_C(0), |
1365 | 0 | UINT64_C(0), |
1366 | 0 | UINT64_C(0), |
1367 | 0 | UINT64_C(0), |
1368 | 0 | UINT64_C(0), |
1369 | 0 | UINT64_C(0), |
1370 | 0 | UINT64_C(0), |
1371 | 0 | UINT64_C(0), |
1372 | 0 | UINT64_C(0), |
1373 | 0 | UINT64_C(0), |
1374 | 0 | UINT64_C(0), |
1375 | 0 | UINT64_C(0), |
1376 | 0 | UINT64_C(0), |
1377 | 0 | UINT64_C(0), |
1378 | 0 | UINT64_C(0), |
1379 | 0 | UINT64_C(0), |
1380 | 0 | UINT64_C(0), |
1381 | 0 | UINT64_C(0), |
1382 | 0 | UINT64_C(0), |
1383 | 0 | UINT64_C(0), |
1384 | 0 | UINT64_C(0), |
1385 | 0 | UINT64_C(0), |
1386 | 0 | UINT64_C(0), |
1387 | 0 | UINT64_C(0), |
1388 | 0 | UINT64_C(0), |
1389 | 0 | UINT64_C(0), |
1390 | 0 | UINT64_C(0), |
1391 | 0 | UINT64_C(0), |
1392 | 0 | UINT64_C(0), |
1393 | 0 | UINT64_C(0), |
1394 | 0 | UINT64_C(0), |
1395 | 0 | UINT64_C(0), |
1396 | 0 | UINT64_C(0), |
1397 | 0 | UINT64_C(0), |
1398 | 0 | UINT64_C(0), |
1399 | 0 | UINT64_C(0), |
1400 | 0 | UINT64_C(0), |
1401 | 0 | UINT64_C(0), |
1402 | 0 | UINT64_C(0), |
1403 | 0 | UINT64_C(0), |
1404 | 0 | UINT64_C(0), |
1405 | 0 | UINT64_C(0), |
1406 | 0 | UINT64_C(0), |
1407 | 0 | UINT64_C(0), |
1408 | 0 | UINT64_C(0), |
1409 | 0 | UINT64_C(0), |
1410 | 0 | UINT64_C(0), |
1411 | 0 | UINT64_C(0), |
1412 | 0 | UINT64_C(0), |
1413 | 0 | UINT64_C(0), |
1414 | 0 | UINT64_C(0), |
1415 | 0 | UINT64_C(0), |
1416 | 0 | UINT64_C(0), |
1417 | 0 | UINT64_C(0), |
1418 | 0 | UINT64_C(0), |
1419 | 0 | UINT64_C(0), |
1420 | 0 | UINT64_C(0), |
1421 | 0 | UINT64_C(0), |
1422 | 0 | UINT64_C(0), |
1423 | 0 | UINT64_C(0), |
1424 | 0 | UINT64_C(0), |
1425 | 0 | UINT64_C(0), |
1426 | 0 | UINT64_C(0), |
1427 | 0 | UINT64_C(0), |
1428 | 0 | UINT64_C(0), |
1429 | 0 | UINT64_C(0), |
1430 | 0 | UINT64_C(0), |
1431 | 0 | UINT64_C(0), |
1432 | 0 | UINT64_C(0), |
1433 | 0 | UINT64_C(0), |
1434 | 0 | UINT64_C(0), |
1435 | 0 | UINT64_C(0), |
1436 | 0 | UINT64_C(0), |
1437 | 0 | UINT64_C(0), |
1438 | 0 | UINT64_C(0), |
1439 | 0 | UINT64_C(0), |
1440 | 0 | UINT64_C(0), |
1441 | 0 | UINT64_C(0), |
1442 | 0 | UINT64_C(0), |
1443 | 0 | UINT64_C(0), |
1444 | 0 | UINT64_C(0), |
1445 | 0 | UINT64_C(0), |
1446 | 0 | UINT64_C(0), |
1447 | 0 | UINT64_C(0), |
1448 | 0 | UINT64_C(0), |
1449 | 0 | UINT64_C(0), |
1450 | 0 | UINT64_C(0), |
1451 | 0 | UINT64_C(0), |
1452 | 0 | UINT64_C(0), |
1453 | 0 | UINT64_C(0), |
1454 | 0 | UINT64_C(0), |
1455 | 0 | UINT64_C(0), |
1456 | 0 | UINT64_C(0), |
1457 | 0 | UINT64_C(0), |
1458 | 0 | UINT64_C(0), |
1459 | 0 | UINT64_C(0), |
1460 | 0 | UINT64_C(0), |
1461 | 0 | UINT64_C(0), |
1462 | 0 | UINT64_C(0), |
1463 | 0 | UINT64_C(0), |
1464 | 0 | UINT64_C(0), |
1465 | 0 | UINT64_C(0), |
1466 | 0 | UINT64_C(0), |
1467 | 0 | UINT64_C(0), |
1468 | 0 | UINT64_C(0), |
1469 | 0 | UINT64_C(0), |
1470 | 0 | UINT64_C(0), |
1471 | 0 | UINT64_C(0), |
1472 | 0 | UINT64_C(0), |
1473 | 0 | UINT64_C(0), |
1474 | 0 | UINT64_C(0), |
1475 | 0 | UINT64_C(0), |
1476 | 0 | UINT64_C(0), |
1477 | 0 | UINT64_C(0), |
1478 | 0 | UINT64_C(0), |
1479 | 0 | UINT64_C(0), |
1480 | 0 | UINT64_C(0), |
1481 | 0 | UINT64_C(0), |
1482 | 0 | UINT64_C(0), |
1483 | 0 | UINT64_C(0), |
1484 | 0 | UINT64_C(0), |
1485 | 0 | UINT64_C(0), |
1486 | 0 | UINT64_C(0), |
1487 | 0 | UINT64_C(0), |
1488 | 0 | UINT64_C(0), |
1489 | 0 | UINT64_C(0), |
1490 | 0 | UINT64_C(0), |
1491 | 0 | UINT64_C(0), |
1492 | 0 | UINT64_C(0), |
1493 | 0 | UINT64_C(0), |
1494 | 0 | UINT64_C(0), |
1495 | 0 | UINT64_C(0), |
1496 | 0 | UINT64_C(0), |
1497 | 0 | UINT64_C(0), |
1498 | 0 | UINT64_C(0), |
1499 | 0 | UINT64_C(0), |
1500 | 0 | UINT64_C(0), |
1501 | 0 | UINT64_C(0), |
1502 | 0 | UINT64_C(0), |
1503 | 0 | UINT64_C(0), |
1504 | 0 | UINT64_C(0), |
1505 | 0 | UINT64_C(0), |
1506 | 0 | UINT64_C(0), |
1507 | 0 | UINT64_C(0), |
1508 | 0 | UINT64_C(0), |
1509 | 0 | UINT64_C(0), |
1510 | 0 | UINT64_C(0), |
1511 | 0 | UINT64_C(0), |
1512 | 0 | UINT64_C(0), |
1513 | 0 | UINT64_C(0), |
1514 | 0 | UINT64_C(0), |
1515 | 0 | UINT64_C(0), |
1516 | 0 | UINT64_C(0), |
1517 | 0 | UINT64_C(0), |
1518 | 0 | UINT64_C(0), |
1519 | 0 | UINT64_C(0), |
1520 | 0 | UINT64_C(0), |
1521 | 0 | UINT64_C(0), |
1522 | 0 | UINT64_C(0), |
1523 | 0 | UINT64_C(0), |
1524 | 0 | UINT64_C(0), |
1525 | 0 | UINT64_C(0), |
1526 | 0 | UINT64_C(0), |
1527 | 0 | UINT64_C(0), |
1528 | 0 | UINT64_C(0), |
1529 | 0 | UINT64_C(0), |
1530 | 0 | UINT64_C(0), |
1531 | 0 | UINT64_C(0), |
1532 | 0 | UINT64_C(0), |
1533 | 0 | UINT64_C(0), |
1534 | 0 | UINT64_C(0), |
1535 | 0 | UINT64_C(0), |
1536 | 0 | UINT64_C(0), |
1537 | 0 | UINT64_C(0), |
1538 | 0 | UINT64_C(0), |
1539 | 0 | UINT64_C(0), |
1540 | 0 | UINT64_C(0), |
1541 | 0 | UINT64_C(0), |
1542 | 0 | UINT64_C(0), |
1543 | 0 | UINT64_C(0), |
1544 | 0 | UINT64_C(0), |
1545 | 0 | UINT64_C(0), |
1546 | 0 | UINT64_C(0), |
1547 | 0 | UINT64_C(0), |
1548 | 0 | UINT64_C(0), |
1549 | 0 | UINT64_C(0), |
1550 | 0 | UINT64_C(0), |
1551 | 0 | UINT64_C(0), |
1552 | 0 | UINT64_C(0), |
1553 | 0 | UINT64_C(0), |
1554 | 0 | UINT64_C(0), |
1555 | 0 | UINT64_C(0), |
1556 | 0 | UINT64_C(0), |
1557 | 0 | UINT64_C(0), |
1558 | 0 | UINT64_C(0), |
1559 | 0 | UINT64_C(0), |
1560 | 0 | UINT64_C(0), |
1561 | 0 | UINT64_C(0), |
1562 | 0 | UINT64_C(0), |
1563 | 0 | UINT64_C(0), |
1564 | 0 | UINT64_C(0), |
1565 | 0 | UINT64_C(0), |
1566 | 0 | UINT64_C(0), |
1567 | 0 | UINT64_C(0), |
1568 | 0 | UINT64_C(0), |
1569 | 0 | UINT64_C(0), |
1570 | 0 | UINT64_C(0), |
1571 | 0 | UINT64_C(0), |
1572 | 0 | UINT64_C(0), |
1573 | 0 | UINT64_C(0), |
1574 | 0 | UINT64_C(0), |
1575 | 0 | UINT64_C(0), |
1576 | 0 | UINT64_C(0), |
1577 | 0 | UINT64_C(0), |
1578 | 0 | UINT64_C(0), |
1579 | 0 | UINT64_C(0), |
1580 | 0 | UINT64_C(0), |
1581 | 0 | UINT64_C(0), |
1582 | 0 | UINT64_C(0), |
1583 | 0 | UINT64_C(0), |
1584 | 0 | UINT64_C(0), |
1585 | 0 | UINT64_C(0), |
1586 | 0 | UINT64_C(0), |
1587 | 0 | UINT64_C(0), |
1588 | 0 | UINT64_C(0), |
1589 | 0 | UINT64_C(0), |
1590 | 0 | UINT64_C(0), |
1591 | 0 | UINT64_C(0), |
1592 | 0 | UINT64_C(0), |
1593 | 0 | UINT64_C(0), |
1594 | 0 | UINT64_C(0), |
1595 | 0 | UINT64_C(0), |
1596 | 0 | UINT64_C(0), |
1597 | 0 | UINT64_C(0), |
1598 | 0 | UINT64_C(0), |
1599 | 0 | UINT64_C(0), |
1600 | 0 | UINT64_C(0), |
1601 | 0 | UINT64_C(0), |
1602 | 0 | UINT64_C(0), |
1603 | 0 | UINT64_C(0), |
1604 | 0 | UINT64_C(0), |
1605 | 0 | UINT64_C(0), |
1606 | 0 | UINT64_C(0), |
1607 | 0 | UINT64_C(0), |
1608 | 0 | UINT64_C(0), |
1609 | 0 | UINT64_C(0), |
1610 | 0 | UINT64_C(0), |
1611 | 0 | UINT64_C(0), |
1612 | 0 | UINT64_C(0), |
1613 | 0 | UINT64_C(0), |
1614 | 0 | UINT64_C(0), |
1615 | 0 | UINT64_C(0), |
1616 | 0 | UINT64_C(0), |
1617 | 0 | UINT64_C(0), |
1618 | 0 | UINT64_C(0), |
1619 | 0 | UINT64_C(0), |
1620 | 0 | UINT64_C(0), |
1621 | 0 | UINT64_C(0), |
1622 | 0 | UINT64_C(0), |
1623 | 0 | UINT64_C(0), |
1624 | 0 | UINT64_C(0), |
1625 | 0 | UINT64_C(0), |
1626 | 0 | UINT64_C(0), |
1627 | 0 | UINT64_C(0), |
1628 | 0 | UINT64_C(0), |
1629 | 0 | UINT64_C(0), |
1630 | 0 | UINT64_C(0), |
1631 | 0 | UINT64_C(0), |
1632 | 0 | UINT64_C(0), |
1633 | 0 | UINT64_C(0), |
1634 | 0 | UINT64_C(0), |
1635 | 0 | UINT64_C(0), |
1636 | 0 | UINT64_C(0), |
1637 | 0 | UINT64_C(0), |
1638 | 0 | UINT64_C(0), |
1639 | 0 | UINT64_C(0), |
1640 | 0 | UINT64_C(0), |
1641 | 0 | UINT64_C(0), |
1642 | 0 | UINT64_C(0), |
1643 | 0 | UINT64_C(0), |
1644 | 0 | UINT64_C(0), |
1645 | 0 | UINT64_C(0), |
1646 | 0 | UINT64_C(0), |
1647 | 0 | UINT64_C(0), |
1648 | 0 | UINT64_C(0), |
1649 | 0 | UINT64_C(0), |
1650 | 0 | UINT64_C(0), |
1651 | 0 | UINT64_C(0), |
1652 | 0 | UINT64_C(0), |
1653 | 0 | UINT64_C(0), |
1654 | 0 | UINT64_C(0), |
1655 | 0 | UINT64_C(0), |
1656 | 0 | UINT64_C(0), |
1657 | 0 | UINT64_C(0), |
1658 | 0 | UINT64_C(0), |
1659 | 0 | UINT64_C(0), |
1660 | 0 | UINT64_C(0), |
1661 | 0 | UINT64_C(0), |
1662 | 0 | UINT64_C(0), |
1663 | 0 | UINT64_C(0), |
1664 | 0 | UINT64_C(0), |
1665 | 0 | UINT64_C(0), |
1666 | 0 | UINT64_C(0), |
1667 | 0 | UINT64_C(0), |
1668 | 0 | UINT64_C(0), |
1669 | 0 | UINT64_C(0), |
1670 | 0 | UINT64_C(0), |
1671 | 0 | UINT64_C(0), |
1672 | 0 | UINT64_C(0), |
1673 | 0 | UINT64_C(0), |
1674 | 0 | UINT64_C(0), |
1675 | 0 | UINT64_C(0), |
1676 | 0 | UINT64_C(0), |
1677 | 0 | UINT64_C(0), |
1678 | 0 | UINT64_C(0), |
1679 | 0 | UINT64_C(0), |
1680 | 0 | UINT64_C(0), |
1681 | 0 | UINT64_C(0), |
1682 | 0 | UINT64_C(0), |
1683 | 0 | UINT64_C(0), |
1684 | 0 | UINT64_C(0), |
1685 | 0 | UINT64_C(0), |
1686 | 0 | UINT64_C(0), |
1687 | 0 | UINT64_C(0), |
1688 | 0 | UINT64_C(0), |
1689 | 0 | UINT64_C(0), |
1690 | 0 | UINT64_C(0), |
1691 | 0 | UINT64_C(0), |
1692 | 0 | UINT64_C(0), |
1693 | 0 | UINT64_C(0), |
1694 | 0 | UINT64_C(0), |
1695 | 0 | UINT64_C(0), |
1696 | 0 | UINT64_C(0), |
1697 | 0 | UINT64_C(0), |
1698 | 0 | UINT64_C(0), |
1699 | 0 | UINT64_C(0), |
1700 | 0 | UINT64_C(0), |
1701 | 0 | UINT64_C(0), |
1702 | 0 | UINT64_C(0), |
1703 | 0 | UINT64_C(0), |
1704 | 0 | UINT64_C(0), |
1705 | 0 | UINT64_C(0), |
1706 | 0 | UINT64_C(0), |
1707 | 0 | UINT64_C(0), |
1708 | 0 | UINT64_C(0), |
1709 | 0 | UINT64_C(0), |
1710 | 0 | UINT64_C(0), |
1711 | 0 | UINT64_C(0), |
1712 | 0 | UINT64_C(0), |
1713 | 0 | UINT64_C(0), |
1714 | 0 | UINT64_C(0), |
1715 | 0 | UINT64_C(0), |
1716 | 0 | UINT64_C(0), |
1717 | 0 | UINT64_C(0), |
1718 | 0 | UINT64_C(0), |
1719 | 0 | UINT64_C(0), |
1720 | 0 | UINT64_C(0), |
1721 | 0 | UINT64_C(0), |
1722 | 0 | UINT64_C(0), |
1723 | 0 | UINT64_C(0), |
1724 | 0 | UINT64_C(0), |
1725 | 0 | UINT64_C(0), |
1726 | 0 | UINT64_C(0), |
1727 | 0 | UINT64_C(0), |
1728 | 0 | UINT64_C(0), |
1729 | 0 | UINT64_C(0), |
1730 | 0 | UINT64_C(0), |
1731 | 0 | UINT64_C(0), |
1732 | 0 | UINT64_C(0), |
1733 | 0 | UINT64_C(0), |
1734 | 0 | UINT64_C(0), |
1735 | 0 | UINT64_C(0), |
1736 | 0 | UINT64_C(0), |
1737 | 0 | UINT64_C(0), |
1738 | 0 | UINT64_C(0), |
1739 | 0 | UINT64_C(0), |
1740 | 0 | UINT64_C(0), |
1741 | 0 | UINT64_C(0), |
1742 | 0 | UINT64_C(0), |
1743 | 0 | UINT64_C(0), |
1744 | 0 | UINT64_C(0), |
1745 | 0 | UINT64_C(0), |
1746 | 0 | UINT64_C(0), |
1747 | 0 | UINT64_C(0), |
1748 | 0 | UINT64_C(0), |
1749 | 0 | UINT64_C(0), |
1750 | 0 | UINT64_C(0), |
1751 | 0 | UINT64_C(0), |
1752 | 0 | UINT64_C(0), |
1753 | 0 | UINT64_C(0), |
1754 | 0 | UINT64_C(0), |
1755 | 0 | UINT64_C(0), |
1756 | 0 | UINT64_C(0), |
1757 | 0 | UINT64_C(0), |
1758 | 0 | UINT64_C(0), |
1759 | 0 | UINT64_C(0), |
1760 | 0 | UINT64_C(0), |
1761 | 0 | UINT64_C(0), |
1762 | 0 | UINT64_C(0), |
1763 | 0 | UINT64_C(0), |
1764 | 0 | UINT64_C(0), |
1765 | 0 | UINT64_C(0), |
1766 | 0 | UINT64_C(0), |
1767 | 0 | UINT64_C(0), |
1768 | 0 | UINT64_C(0), |
1769 | 0 | UINT64_C(0), |
1770 | 0 | UINT64_C(0), |
1771 | 0 | UINT64_C(0), |
1772 | 0 | UINT64_C(0), |
1773 | 0 | UINT64_C(0), |
1774 | 0 | UINT64_C(0), |
1775 | 0 | UINT64_C(0), |
1776 | 0 | UINT64_C(0), |
1777 | 0 | UINT64_C(0), |
1778 | 0 | UINT64_C(0), |
1779 | 0 | UINT64_C(0), |
1780 | 0 | UINT64_C(0), |
1781 | 0 | UINT64_C(0), |
1782 | 0 | UINT64_C(0), |
1783 | 0 | UINT64_C(0), |
1784 | 0 | UINT64_C(0), |
1785 | 0 | UINT64_C(0), |
1786 | 0 | UINT64_C(0), |
1787 | 0 | UINT64_C(0), |
1788 | 0 | UINT64_C(0), |
1789 | 0 | UINT64_C(0), |
1790 | 0 | UINT64_C(0), |
1791 | 0 | UINT64_C(0), |
1792 | 0 | UINT64_C(0), |
1793 | 0 | UINT64_C(0), |
1794 | 0 | UINT64_C(0), |
1795 | 0 | UINT64_C(0), |
1796 | 0 | UINT64_C(0), |
1797 | 0 | UINT64_C(0), |
1798 | 0 | UINT64_C(0), |
1799 | 0 | UINT64_C(0), |
1800 | 0 | UINT64_C(0), |
1801 | 0 | UINT64_C(0), |
1802 | 0 | UINT64_C(0), |
1803 | 0 | UINT64_C(0), |
1804 | 0 | UINT64_C(0), |
1805 | 0 | UINT64_C(0), |
1806 | 0 | UINT64_C(0), |
1807 | 0 | UINT64_C(0), |
1808 | 0 | UINT64_C(0), |
1809 | 0 | UINT64_C(0), |
1810 | 0 | UINT64_C(0), |
1811 | 0 | UINT64_C(0), |
1812 | 0 | UINT64_C(0), |
1813 | 0 | UINT64_C(0), |
1814 | 0 | UINT64_C(0), |
1815 | 0 | UINT64_C(0), |
1816 | 0 | UINT64_C(0), |
1817 | 0 | UINT64_C(0), |
1818 | 0 | UINT64_C(0), |
1819 | 0 | UINT64_C(0), |
1820 | 0 | UINT64_C(0), |
1821 | 0 | UINT64_C(0), |
1822 | 0 | UINT64_C(0), |
1823 | 0 | UINT64_C(0), |
1824 | 0 | UINT64_C(0), |
1825 | 0 | UINT64_C(0), |
1826 | 0 | UINT64_C(0), |
1827 | 0 | UINT64_C(0), |
1828 | 0 | UINT64_C(0), |
1829 | 0 | UINT64_C(0), |
1830 | 0 | UINT64_C(0), |
1831 | 0 | UINT64_C(0), |
1832 | 0 | UINT64_C(0), |
1833 | 0 | UINT64_C(0), |
1834 | 0 | UINT64_C(0), |
1835 | 0 | UINT64_C(0), |
1836 | 0 | UINT64_C(0), |
1837 | 0 | UINT64_C(0), |
1838 | 0 | UINT64_C(0), |
1839 | 0 | UINT64_C(0), |
1840 | 0 | UINT64_C(0), |
1841 | 0 | UINT64_C(0), |
1842 | 0 | UINT64_C(0), |
1843 | 0 | UINT64_C(0), |
1844 | 0 | UINT64_C(0), |
1845 | 0 | UINT64_C(0), |
1846 | 0 | UINT64_C(0), |
1847 | 0 | UINT64_C(0), |
1848 | 0 | UINT64_C(0), |
1849 | 0 | UINT64_C(0), |
1850 | 0 | UINT64_C(0), |
1851 | 0 | UINT64_C(0), |
1852 | 0 | UINT64_C(0), |
1853 | 0 | UINT64_C(0), |
1854 | 0 | UINT64_C(0), |
1855 | 0 | UINT64_C(0), |
1856 | 0 | UINT64_C(0), |
1857 | 0 | UINT64_C(0), |
1858 | 0 | UINT64_C(0), |
1859 | 0 | UINT64_C(0), |
1860 | 0 | UINT64_C(0), |
1861 | 0 | UINT64_C(0), |
1862 | 0 | UINT64_C(0), |
1863 | 0 | UINT64_C(0), |
1864 | 0 | UINT64_C(0), |
1865 | 0 | UINT64_C(0), |
1866 | 0 | UINT64_C(0), |
1867 | 0 | UINT64_C(0), |
1868 | 0 | UINT64_C(0), |
1869 | 0 | UINT64_C(0), |
1870 | 0 | UINT64_C(0), |
1871 | 0 | UINT64_C(0), |
1872 | 0 | UINT64_C(0), |
1873 | 0 | UINT64_C(0), |
1874 | 0 | UINT64_C(0), |
1875 | 0 | UINT64_C(0), |
1876 | 0 | UINT64_C(0), |
1877 | 0 | UINT64_C(0), |
1878 | 0 | UINT64_C(0), |
1879 | 0 | UINT64_C(0), |
1880 | 0 | UINT64_C(0), |
1881 | 0 | UINT64_C(0), |
1882 | 0 | UINT64_C(0), |
1883 | 0 | UINT64_C(0), |
1884 | 0 | UINT64_C(0), |
1885 | 0 | UINT64_C(0), |
1886 | 0 | UINT64_C(0), |
1887 | 0 | UINT64_C(0), |
1888 | 0 | UINT64_C(0), |
1889 | 0 | UINT64_C(0), |
1890 | 0 | UINT64_C(0), |
1891 | 0 | UINT64_C(0), |
1892 | 0 | UINT64_C(0), |
1893 | 0 | UINT64_C(0), |
1894 | 0 | UINT64_C(0), |
1895 | 0 | UINT64_C(0), |
1896 | 0 | UINT64_C(0), |
1897 | 0 | UINT64_C(0), |
1898 | 0 | UINT64_C(0), |
1899 | 0 | UINT64_C(0), |
1900 | 0 | UINT64_C(0), |
1901 | 0 | UINT64_C(0), |
1902 | 0 | UINT64_C(0), |
1903 | 0 | UINT64_C(0), |
1904 | 0 | UINT64_C(0), |
1905 | 0 | UINT64_C(0), |
1906 | 0 | UINT64_C(0), |
1907 | 0 | UINT64_C(0), |
1908 | 0 | UINT64_C(0), |
1909 | 0 | UINT64_C(0), |
1910 | 0 | UINT64_C(0), |
1911 | 0 | UINT64_C(0), |
1912 | 0 | UINT64_C(0), |
1913 | 0 | UINT64_C(0), |
1914 | 0 | UINT64_C(0), |
1915 | 0 | UINT64_C(0), |
1916 | 0 | UINT64_C(0), |
1917 | 0 | UINT64_C(0), |
1918 | 0 | UINT64_C(0), |
1919 | 0 | UINT64_C(0), |
1920 | 0 | UINT64_C(0), |
1921 | 0 | UINT64_C(0), |
1922 | 0 | UINT64_C(0), |
1923 | 0 | UINT64_C(0), |
1924 | 0 | UINT64_C(0), |
1925 | 0 | UINT64_C(0), |
1926 | 0 | UINT64_C(0), |
1927 | 0 | UINT64_C(0), |
1928 | 0 | UINT64_C(0), |
1929 | 0 | UINT64_C(0), |
1930 | 0 | UINT64_C(0), |
1931 | 0 | UINT64_C(0), |
1932 | 0 | UINT64_C(0), |
1933 | 0 | UINT64_C(0), |
1934 | 0 | UINT64_C(0), |
1935 | 0 | UINT64_C(0), |
1936 | 0 | UINT64_C(0), |
1937 | 0 | UINT64_C(0), |
1938 | 0 | UINT64_C(0), |
1939 | 0 | UINT64_C(0), |
1940 | 0 | UINT64_C(0), |
1941 | 0 | UINT64_C(0), |
1942 | 0 | UINT64_C(0), |
1943 | 0 | UINT64_C(0), |
1944 | 0 | UINT64_C(0), |
1945 | 0 | UINT64_C(0), |
1946 | 0 | UINT64_C(0), |
1947 | 0 | UINT64_C(0), |
1948 | 0 | UINT64_C(0), |
1949 | 0 | UINT64_C(0), |
1950 | 0 | UINT64_C(0), |
1951 | 0 | UINT64_C(0), |
1952 | 0 | UINT64_C(0), |
1953 | 0 | UINT64_C(0), |
1954 | 0 | UINT64_C(0), |
1955 | 0 | UINT64_C(0), |
1956 | 0 | UINT64_C(0), |
1957 | 0 | UINT64_C(0), |
1958 | 0 | UINT64_C(0), |
1959 | 0 | UINT64_C(0), |
1960 | 0 | UINT64_C(0), |
1961 | 0 | UINT64_C(0), |
1962 | 0 | UINT64_C(0), |
1963 | 0 | UINT64_C(0), |
1964 | 0 | UINT64_C(0), |
1965 | 0 | UINT64_C(0), |
1966 | 0 | UINT64_C(0), |
1967 | 0 | UINT64_C(0), |
1968 | 0 | UINT64_C(0), |
1969 | 0 | UINT64_C(0), |
1970 | 0 | UINT64_C(0), |
1971 | 0 | UINT64_C(0), |
1972 | 0 | UINT64_C(0), |
1973 | 0 | UINT64_C(0), |
1974 | 0 | UINT64_C(0), |
1975 | 0 | UINT64_C(0), |
1976 | 0 | UINT64_C(0), |
1977 | 0 | UINT64_C(0), |
1978 | 0 | UINT64_C(0), |
1979 | 0 | UINT64_C(0), |
1980 | 0 | UINT64_C(0), |
1981 | 0 | UINT64_C(0), |
1982 | 0 | UINT64_C(0), |
1983 | 0 | UINT64_C(0), |
1984 | 0 | UINT64_C(0), |
1985 | 0 | UINT64_C(0), |
1986 | 0 | UINT64_C(0), |
1987 | 0 | UINT64_C(0), |
1988 | 0 | UINT64_C(0), |
1989 | 0 | UINT64_C(0), |
1990 | 0 | UINT64_C(0), |
1991 | 0 | UINT64_C(0), |
1992 | 0 | UINT64_C(0), |
1993 | 0 | UINT64_C(0), |
1994 | 0 | UINT64_C(0), |
1995 | 0 | UINT64_C(0), |
1996 | 0 | UINT64_C(0), |
1997 | 0 | UINT64_C(0), |
1998 | 0 | UINT64_C(0), |
1999 | 0 | UINT64_C(0), |
2000 | 0 | UINT64_C(0), |
2001 | 0 | UINT64_C(0), |
2002 | 0 | UINT64_C(0), |
2003 | 0 | UINT64_C(0), |
2004 | 0 | UINT64_C(0), |
2005 | 0 | UINT64_C(0), |
2006 | 0 | UINT64_C(0), |
2007 | 0 | UINT64_C(0), |
2008 | 0 | UINT64_C(0), |
2009 | 0 | UINT64_C(0), |
2010 | 0 | UINT64_C(0), |
2011 | 0 | UINT64_C(0), |
2012 | 0 | UINT64_C(0), |
2013 | 0 | UINT64_C(0), |
2014 | 0 | UINT64_C(0), |
2015 | 0 | UINT64_C(0), |
2016 | 0 | UINT64_C(0), |
2017 | 0 | UINT64_C(0), |
2018 | 0 | UINT64_C(0), |
2019 | 0 | UINT64_C(0), |
2020 | 0 | UINT64_C(0), |
2021 | 0 | UINT64_C(0), |
2022 | 0 | UINT64_C(0), |
2023 | 0 | UINT64_C(0), |
2024 | 0 | UINT64_C(0), |
2025 | 0 | UINT64_C(0), |
2026 | 0 | UINT64_C(0), |
2027 | 0 | UINT64_C(0), |
2028 | 0 | UINT64_C(0), |
2029 | 0 | UINT64_C(0), |
2030 | 0 | UINT64_C(0), |
2031 | 0 | UINT64_C(0), |
2032 | 0 | UINT64_C(0), |
2033 | 0 | UINT64_C(0), |
2034 | 0 | UINT64_C(0), |
2035 | 0 | UINT64_C(0), |
2036 | 0 | UINT64_C(0), |
2037 | 0 | UINT64_C(0), |
2038 | 0 | UINT64_C(0), |
2039 | 0 | UINT64_C(0), |
2040 | 0 | UINT64_C(0), |
2041 | 0 | UINT64_C(0), |
2042 | 0 | UINT64_C(0), |
2043 | 0 | UINT64_C(0), |
2044 | 0 | UINT64_C(0), |
2045 | 0 | UINT64_C(0), |
2046 | 0 | UINT64_C(0), |
2047 | 0 | UINT64_C(0), |
2048 | 0 | UINT64_C(0), |
2049 | 0 | UINT64_C(0), |
2050 | 0 | UINT64_C(0), |
2051 | 0 | UINT64_C(0), |
2052 | 0 | UINT64_C(0), |
2053 | 0 | UINT64_C(0), |
2054 | 0 | UINT64_C(0), |
2055 | 0 | UINT64_C(0), |
2056 | 0 | UINT64_C(0), |
2057 | 0 | UINT64_C(0), |
2058 | 0 | UINT64_C(0), |
2059 | 0 | UINT64_C(0), |
2060 | 0 | UINT64_C(0), |
2061 | 0 | UINT64_C(0), |
2062 | 0 | UINT64_C(0), |
2063 | 0 | UINT64_C(0), |
2064 | 0 | UINT64_C(0), |
2065 | 0 | UINT64_C(0), |
2066 | 0 | UINT64_C(0), |
2067 | 0 | UINT64_C(0), |
2068 | 0 | UINT64_C(0), |
2069 | 0 | UINT64_C(0), |
2070 | 0 | UINT64_C(0), |
2071 | 0 | UINT64_C(0), |
2072 | 0 | UINT64_C(0), |
2073 | 0 | UINT64_C(0), |
2074 | 0 | UINT64_C(0), |
2075 | 0 | UINT64_C(0), |
2076 | 0 | UINT64_C(0), |
2077 | 0 | UINT64_C(0), |
2078 | 0 | UINT64_C(0), |
2079 | 0 | UINT64_C(0), |
2080 | 0 | UINT64_C(0), |
2081 | 0 | UINT64_C(0), |
2082 | 0 | UINT64_C(0), |
2083 | 0 | UINT64_C(0), |
2084 | 0 | UINT64_C(0), |
2085 | 0 | UINT64_C(0), |
2086 | 0 | UINT64_C(0), |
2087 | 0 | UINT64_C(0), |
2088 | 0 | UINT64_C(0), |
2089 | 0 | UINT64_C(0), |
2090 | 0 | UINT64_C(0), |
2091 | 0 | UINT64_C(0), |
2092 | 0 | UINT64_C(0), |
2093 | 0 | UINT64_C(0), |
2094 | 0 | UINT64_C(0), |
2095 | 0 | UINT64_C(0), |
2096 | 0 | UINT64_C(0), |
2097 | 0 | UINT64_C(0), |
2098 | 0 | UINT64_C(0), |
2099 | 0 | UINT64_C(0), |
2100 | 0 | UINT64_C(0), |
2101 | 0 | UINT64_C(0), |
2102 | 0 | UINT64_C(0), |
2103 | 0 | UINT64_C(0), |
2104 | 0 | UINT64_C(0), |
2105 | 0 | UINT64_C(0), |
2106 | 0 | UINT64_C(0), |
2107 | 0 | UINT64_C(0), |
2108 | 0 | UINT64_C(0), |
2109 | 0 | UINT64_C(0), |
2110 | 0 | UINT64_C(0), |
2111 | 0 | UINT64_C(0), |
2112 | 0 | UINT64_C(0), |
2113 | 0 | UINT64_C(0), |
2114 | 0 | UINT64_C(0), |
2115 | 0 | UINT64_C(0), |
2116 | 0 | UINT64_C(0), |
2117 | 0 | UINT64_C(0), |
2118 | 0 | UINT64_C(0), |
2119 | 0 | UINT64_C(0), |
2120 | 0 | UINT64_C(0), |
2121 | 0 | UINT64_C(0), |
2122 | 0 | UINT64_C(0), |
2123 | 0 | UINT64_C(0), |
2124 | 0 | UINT64_C(0), |
2125 | 0 | UINT64_C(0), |
2126 | 0 | UINT64_C(0), |
2127 | 0 | UINT64_C(0), |
2128 | 0 | UINT64_C(0), |
2129 | 0 | UINT64_C(0), |
2130 | 0 | UINT64_C(0), |
2131 | 0 | UINT64_C(0), |
2132 | 0 | UINT64_C(0), |
2133 | 0 | UINT64_C(0), |
2134 | 0 | UINT64_C(0), |
2135 | 0 | UINT64_C(0), |
2136 | 0 | UINT64_C(0), |
2137 | 0 | UINT64_C(0), |
2138 | 0 | UINT64_C(0), |
2139 | 0 | UINT64_C(0), |
2140 | 0 | UINT64_C(0), |
2141 | 0 | UINT64_C(0), |
2142 | 0 | UINT64_C(0), |
2143 | 0 | UINT64_C(0), |
2144 | 0 | UINT64_C(0), |
2145 | 0 | UINT64_C(0), |
2146 | 0 | UINT64_C(0), |
2147 | 0 | UINT64_C(0), |
2148 | 0 | UINT64_C(0), |
2149 | 0 | UINT64_C(0), |
2150 | 0 | UINT64_C(0), |
2151 | 0 | UINT64_C(0), |
2152 | 0 | UINT64_C(0), |
2153 | 0 | UINT64_C(0), |
2154 | 0 | UINT64_C(0), |
2155 | 0 | UINT64_C(0), |
2156 | 0 | UINT64_C(0), |
2157 | 0 | UINT64_C(0), |
2158 | 0 | UINT64_C(0), |
2159 | 0 | UINT64_C(0), |
2160 | 0 | UINT64_C(0), |
2161 | 0 | UINT64_C(0), |
2162 | 0 | UINT64_C(0), |
2163 | 0 | UINT64_C(0), |
2164 | 0 | UINT64_C(0), |
2165 | 0 | UINT64_C(0), |
2166 | 0 | UINT64_C(0), |
2167 | 0 | UINT64_C(0), |
2168 | 0 | UINT64_C(0), |
2169 | 0 | UINT64_C(0), |
2170 | 0 | UINT64_C(0), |
2171 | 0 | UINT64_C(0), |
2172 | 0 | UINT64_C(0), |
2173 | 0 | UINT64_C(0), |
2174 | 0 | UINT64_C(0), |
2175 | 0 | UINT64_C(0), |
2176 | 0 | UINT64_C(0), |
2177 | 0 | UINT64_C(0), |
2178 | 0 | UINT64_C(0), |
2179 | 0 | UINT64_C(0), |
2180 | 0 | UINT64_C(0), |
2181 | 0 | UINT64_C(0), |
2182 | 0 | UINT64_C(0), |
2183 | 0 | UINT64_C(0), |
2184 | 0 | UINT64_C(0), |
2185 | 0 | UINT64_C(0), |
2186 | 0 | UINT64_C(0), |
2187 | 0 | UINT64_C(0), |
2188 | 0 | UINT64_C(0), |
2189 | 0 | UINT64_C(0), |
2190 | 0 | UINT64_C(0), |
2191 | 0 | UINT64_C(0), |
2192 | 0 | UINT64_C(0), |
2193 | 0 | UINT64_C(0), |
2194 | 0 | UINT64_C(0), |
2195 | 0 | UINT64_C(0), |
2196 | 0 | UINT64_C(0), |
2197 | 0 | UINT64_C(0), |
2198 | 0 | UINT64_C(0), |
2199 | 0 | UINT64_C(0), |
2200 | 0 | UINT64_C(0), |
2201 | 0 | UINT64_C(0), |
2202 | 0 | UINT64_C(0), |
2203 | 0 | UINT64_C(0), |
2204 | 0 | UINT64_C(0), |
2205 | 0 | UINT64_C(0), |
2206 | 0 | UINT64_C(0), |
2207 | 0 | UINT64_C(0), |
2208 | 0 | UINT64_C(0), |
2209 | 0 | UINT64_C(0), |
2210 | 0 | UINT64_C(0), |
2211 | 0 | UINT64_C(0), |
2212 | 0 | UINT64_C(0), |
2213 | 0 | UINT64_C(0), |
2214 | 0 | UINT64_C(0), |
2215 | 0 | UINT64_C(0), |
2216 | 0 | UINT64_C(0), |
2217 | 0 | UINT64_C(0), |
2218 | 0 | UINT64_C(0), |
2219 | 0 | UINT64_C(0), |
2220 | 0 | UINT64_C(0), |
2221 | 0 | UINT64_C(0), |
2222 | 0 | UINT64_C(0), |
2223 | 0 | UINT64_C(0), |
2224 | 0 | UINT64_C(0), |
2225 | 0 | UINT64_C(0), |
2226 | 0 | UINT64_C(0), |
2227 | 0 | UINT64_C(0), |
2228 | 0 | UINT64_C(0), |
2229 | 0 | UINT64_C(0), |
2230 | 0 | UINT64_C(0), |
2231 | 0 | UINT64_C(0), |
2232 | 0 | UINT64_C(0), |
2233 | 0 | UINT64_C(0), |
2234 | 0 | UINT64_C(0), |
2235 | 0 | UINT64_C(0), |
2236 | 0 | UINT64_C(0), |
2237 | 0 | UINT64_C(0), |
2238 | 0 | UINT64_C(0), |
2239 | 0 | UINT64_C(0), |
2240 | 0 | UINT64_C(0), |
2241 | 0 | UINT64_C(0), |
2242 | 0 | UINT64_C(0), |
2243 | 0 | UINT64_C(0), |
2244 | 0 | UINT64_C(0), |
2245 | 0 | UINT64_C(0), |
2246 | 0 | UINT64_C(0), |
2247 | 0 | UINT64_C(0), |
2248 | 0 | UINT64_C(0), |
2249 | 0 | UINT64_C(0), |
2250 | 0 | UINT64_C(0), |
2251 | 0 | UINT64_C(0), |
2252 | 0 | UINT64_C(0), |
2253 | 0 | UINT64_C(0), |
2254 | 0 | UINT64_C(0), |
2255 | 0 | UINT64_C(0), |
2256 | 0 | UINT64_C(0), |
2257 | 0 | UINT64_C(0), |
2258 | 0 | UINT64_C(0), |
2259 | 0 | UINT64_C(0), |
2260 | 0 | UINT64_C(0), |
2261 | 0 | UINT64_C(0), |
2262 | 0 | UINT64_C(0), |
2263 | 0 | UINT64_C(0), |
2264 | 0 | UINT64_C(0), |
2265 | 0 | UINT64_C(0), |
2266 | 0 | UINT64_C(0), |
2267 | 0 | UINT64_C(0), |
2268 | 0 | UINT64_C(0), |
2269 | 0 | UINT64_C(0), |
2270 | 0 | UINT64_C(0), |
2271 | 0 | UINT64_C(0), |
2272 | 0 | UINT64_C(0), |
2273 | 0 | UINT64_C(0), |
2274 | 0 | UINT64_C(0), |
2275 | 0 | UINT64_C(0), |
2276 | 0 | UINT64_C(0), |
2277 | 0 | UINT64_C(0), |
2278 | 0 | UINT64_C(0), |
2279 | 0 | UINT64_C(0), |
2280 | 0 | UINT64_C(0), |
2281 | 0 | UINT64_C(0), |
2282 | 0 | UINT64_C(0), |
2283 | 0 | UINT64_C(0), |
2284 | 0 | UINT64_C(0), |
2285 | 0 | UINT64_C(0), |
2286 | 0 | UINT64_C(0), |
2287 | 0 | UINT64_C(0), |
2288 | 0 | UINT64_C(0), |
2289 | 0 | UINT64_C(0), |
2290 | 0 | UINT64_C(0), |
2291 | 0 | UINT64_C(0), |
2292 | 0 | UINT64_C(0), |
2293 | 0 | UINT64_C(0), |
2294 | 0 | UINT64_C(0), |
2295 | 0 | UINT64_C(0), |
2296 | 0 | UINT64_C(0), |
2297 | 0 | UINT64_C(0), |
2298 | 0 | UINT64_C(0), |
2299 | 0 | UINT64_C(0), |
2300 | 0 | UINT64_C(0), |
2301 | 0 | UINT64_C(0), |
2302 | 0 | UINT64_C(0), |
2303 | 0 | UINT64_C(0), |
2304 | 0 | UINT64_C(0), |
2305 | 0 | UINT64_C(0), |
2306 | 0 | UINT64_C(0), |
2307 | 0 | UINT64_C(0), |
2308 | 0 | UINT64_C(0), |
2309 | 0 | UINT64_C(0), |
2310 | 0 | UINT64_C(0), |
2311 | 0 | UINT64_C(0), |
2312 | 0 | UINT64_C(0), |
2313 | 0 | UINT64_C(0), |
2314 | 0 | UINT64_C(0), |
2315 | 0 | UINT64_C(0), |
2316 | 0 | UINT64_C(0), |
2317 | 0 | UINT64_C(0), |
2318 | 0 | UINT64_C(0), |
2319 | 0 | UINT64_C(0), |
2320 | 0 | UINT64_C(0), |
2321 | 0 | UINT64_C(0), |
2322 | 0 | UINT64_C(0), |
2323 | 0 | UINT64_C(0), |
2324 | 0 | UINT64_C(0), |
2325 | 0 | UINT64_C(0), |
2326 | 0 | UINT64_C(0), |
2327 | 0 | UINT64_C(0), |
2328 | 0 | UINT64_C(0), |
2329 | 0 | UINT64_C(0), |
2330 | 0 | UINT64_C(0), |
2331 | 0 | UINT64_C(0), |
2332 | 0 | UINT64_C(0), |
2333 | 0 | UINT64_C(0), |
2334 | 0 | UINT64_C(0), |
2335 | 0 | UINT64_C(0), |
2336 | 0 | UINT64_C(0), |
2337 | 0 | UINT64_C(0), |
2338 | 0 | UINT64_C(0), |
2339 | 0 | UINT64_C(0), |
2340 | 0 | UINT64_C(0), |
2341 | 0 | UINT64_C(0), |
2342 | 0 | UINT64_C(0), |
2343 | 0 | UINT64_C(0), |
2344 | 0 | UINT64_C(0), |
2345 | 0 | UINT64_C(0), |
2346 | 0 | UINT64_C(0), |
2347 | 0 | UINT64_C(0), |
2348 | 0 | UINT64_C(0), |
2349 | 0 | UINT64_C(0), |
2350 | 0 | UINT64_C(0), |
2351 | 0 | UINT64_C(0), |
2352 | 0 | UINT64_C(0), |
2353 | 0 | UINT64_C(0), |
2354 | 0 | UINT64_C(0), |
2355 | 0 | UINT64_C(0), |
2356 | 0 | UINT64_C(0), |
2357 | 0 | UINT64_C(0), |
2358 | 0 | UINT64_C(0), |
2359 | 0 | UINT64_C(0), |
2360 | 0 | UINT64_C(0), |
2361 | 0 | UINT64_C(0), |
2362 | 0 | UINT64_C(0), |
2363 | 0 | UINT64_C(0), |
2364 | 0 | UINT64_C(0), |
2365 | 0 | UINT64_C(0), |
2366 | 0 | UINT64_C(0), |
2367 | 0 | UINT64_C(0), |
2368 | 0 | UINT64_C(0), |
2369 | 0 | UINT64_C(0), |
2370 | 0 | UINT64_C(0), |
2371 | 0 | UINT64_C(0), |
2372 | 0 | UINT64_C(0), |
2373 | 0 | UINT64_C(0), |
2374 | 0 | UINT64_C(0), |
2375 | 0 | UINT64_C(0), |
2376 | 0 | UINT64_C(0), |
2377 | 0 | UINT64_C(0), |
2378 | 0 | UINT64_C(0), |
2379 | 0 | UINT64_C(0), |
2380 | 0 | UINT64_C(0), |
2381 | 0 | UINT64_C(0), |
2382 | 0 | UINT64_C(0), |
2383 | 0 | UINT64_C(0), |
2384 | 0 | UINT64_C(0), |
2385 | 0 | UINT64_C(0), |
2386 | 0 | UINT64_C(0), |
2387 | 0 | UINT64_C(0), |
2388 | 0 | UINT64_C(0), |
2389 | 0 | UINT64_C(0), |
2390 | 0 | UINT64_C(0), |
2391 | 0 | UINT64_C(0), |
2392 | 0 | UINT64_C(0), |
2393 | 0 | UINT64_C(0), |
2394 | 0 | UINT64_C(0), |
2395 | 0 | UINT64_C(0), |
2396 | 0 | UINT64_C(0), |
2397 | 0 | UINT64_C(0), |
2398 | 0 | UINT64_C(0), |
2399 | 0 | UINT64_C(0), |
2400 | 0 | UINT64_C(0), |
2401 | 0 | UINT64_C(0), |
2402 | 0 | UINT64_C(0), |
2403 | 0 | UINT64_C(0), |
2404 | 0 | UINT64_C(0), |
2405 | 0 | UINT64_C(0), |
2406 | 0 | UINT64_C(0), |
2407 | 0 | UINT64_C(0), |
2408 | 0 | UINT64_C(0), |
2409 | 0 | UINT64_C(0), |
2410 | 0 | UINT64_C(0), |
2411 | 0 | UINT64_C(0), |
2412 | 0 | UINT64_C(0), |
2413 | 0 | UINT64_C(0), |
2414 | 0 | UINT64_C(0), |
2415 | 0 | UINT64_C(0), |
2416 | 0 | UINT64_C(0), |
2417 | 0 | UINT64_C(0), |
2418 | 0 | UINT64_C(0), |
2419 | 0 | UINT64_C(0), |
2420 | 0 | UINT64_C(0), |
2421 | 0 | UINT64_C(0), |
2422 | 0 | UINT64_C(0), |
2423 | 0 | UINT64_C(0), |
2424 | 0 | UINT64_C(0), |
2425 | 0 | UINT64_C(0), |
2426 | 0 | UINT64_C(0), |
2427 | 0 | UINT64_C(0), |
2428 | 0 | UINT64_C(0), |
2429 | 0 | UINT64_C(0), |
2430 | 0 | UINT64_C(0), |
2431 | 0 | UINT64_C(0), |
2432 | 0 | UINT64_C(0), |
2433 | 0 | UINT64_C(0), |
2434 | 0 | UINT64_C(0), |
2435 | 0 | UINT64_C(0), |
2436 | 0 | UINT64_C(0), |
2437 | 0 | UINT64_C(0), |
2438 | 0 | UINT64_C(0), |
2439 | 0 | UINT64_C(0), |
2440 | 0 | UINT64_C(0), |
2441 | 0 | UINT64_C(0), |
2442 | 0 | UINT64_C(0), |
2443 | 0 | UINT64_C(0), |
2444 | 0 | UINT64_C(0), |
2445 | 0 | UINT64_C(0), |
2446 | 0 | UINT64_C(0), |
2447 | 0 | UINT64_C(0), |
2448 | 0 | UINT64_C(0), |
2449 | 0 | UINT64_C(0), |
2450 | 0 | UINT64_C(0), |
2451 | 0 | UINT64_C(0), |
2452 | 0 | UINT64_C(0), |
2453 | 0 | UINT64_C(0), |
2454 | 0 | UINT64_C(0), |
2455 | 0 | UINT64_C(0), |
2456 | 0 | UINT64_C(0), |
2457 | 0 | UINT64_C(0), |
2458 | 0 | UINT64_C(0), |
2459 | 0 | UINT64_C(0), |
2460 | 0 | UINT64_C(0), |
2461 | 0 | UINT64_C(0), |
2462 | 0 | UINT64_C(0), |
2463 | 0 | UINT64_C(0), |
2464 | 0 | UINT64_C(0), |
2465 | 0 | UINT64_C(0), |
2466 | 0 | UINT64_C(0), |
2467 | 0 | UINT64_C(0), |
2468 | 0 | UINT64_C(0), |
2469 | 0 | UINT64_C(0), |
2470 | 0 | UINT64_C(0), |
2471 | 0 | UINT64_C(0), |
2472 | 0 | UINT64_C(0), |
2473 | 0 | UINT64_C(0), |
2474 | 0 | UINT64_C(0), |
2475 | 0 | UINT64_C(0), |
2476 | 0 | UINT64_C(0), |
2477 | 0 | UINT64_C(0), |
2478 | 0 | UINT64_C(0), |
2479 | 0 | UINT64_C(0), |
2480 | 0 | UINT64_C(0), |
2481 | 0 | UINT64_C(0), |
2482 | 0 | UINT64_C(0), |
2483 | 0 | UINT64_C(0), |
2484 | 0 | UINT64_C(0), |
2485 | 0 | UINT64_C(0), |
2486 | 0 | UINT64_C(0), |
2487 | 0 | UINT64_C(0), |
2488 | 0 | UINT64_C(0), |
2489 | 0 | UINT64_C(0), |
2490 | 0 | UINT64_C(0), |
2491 | 0 | UINT64_C(0), |
2492 | 0 | UINT64_C(0), |
2493 | 0 | UINT64_C(0), |
2494 | 0 | UINT64_C(0), |
2495 | 0 | UINT64_C(0), |
2496 | 0 | UINT64_C(0), |
2497 | 0 | UINT64_C(0), |
2498 | 0 | UINT64_C(0), |
2499 | 0 | UINT64_C(0), |
2500 | 0 | UINT64_C(0), |
2501 | 0 | UINT64_C(0), |
2502 | 0 | UINT64_C(0), |
2503 | 0 | UINT64_C(0), |
2504 | 0 | UINT64_C(0), |
2505 | 0 | UINT64_C(0), |
2506 | 0 | UINT64_C(0), |
2507 | 0 | UINT64_C(0), |
2508 | 0 | UINT64_C(0), |
2509 | 0 | UINT64_C(0), |
2510 | 0 | UINT64_C(0), |
2511 | 0 | UINT64_C(0), |
2512 | 0 | UINT64_C(0), |
2513 | 0 | UINT64_C(0), |
2514 | 0 | UINT64_C(0), |
2515 | 0 | UINT64_C(0), |
2516 | 0 | UINT64_C(0), |
2517 | 0 | UINT64_C(0), |
2518 | 0 | UINT64_C(0), |
2519 | 0 | UINT64_C(0), |
2520 | 0 | UINT64_C(0), |
2521 | 0 | UINT64_C(0), |
2522 | 0 | UINT64_C(0), |
2523 | 0 | UINT64_C(0), |
2524 | 0 | UINT64_C(0), |
2525 | 0 | UINT64_C(0), |
2526 | 0 | UINT64_C(0), |
2527 | 0 | UINT64_C(0), |
2528 | 0 | UINT64_C(0), |
2529 | 0 | UINT64_C(0), |
2530 | 0 | UINT64_C(0), |
2531 | 0 | UINT64_C(0), |
2532 | 0 | UINT64_C(0), |
2533 | 0 | UINT64_C(0), |
2534 | 0 | UINT64_C(0), |
2535 | 0 | UINT64_C(0), |
2536 | 0 | UINT64_C(0), |
2537 | 0 | UINT64_C(0), |
2538 | 0 | UINT64_C(0), |
2539 | 0 | UINT64_C(0), |
2540 | 0 | UINT64_C(0), |
2541 | 0 | UINT64_C(0), |
2542 | 0 | UINT64_C(0), |
2543 | 0 | UINT64_C(0), |
2544 | 0 | UINT64_C(0), |
2545 | 0 | UINT64_C(0), |
2546 | 0 | UINT64_C(0), |
2547 | 0 | UINT64_C(0), |
2548 | 0 | UINT64_C(0), |
2549 | 0 | UINT64_C(0), |
2550 | 0 | UINT64_C(0), |
2551 | 0 | UINT64_C(0), |
2552 | 0 | UINT64_C(0), |
2553 | 0 | UINT64_C(0), |
2554 | 0 | UINT64_C(0), |
2555 | 0 | UINT64_C(0), |
2556 | 0 | UINT64_C(0), |
2557 | 0 | UINT64_C(0), |
2558 | 0 | UINT64_C(0), |
2559 | 0 | UINT64_C(0), |
2560 | 0 | UINT64_C(0), |
2561 | 0 | UINT64_C(0), |
2562 | 0 | UINT64_C(0), |
2563 | 0 | UINT64_C(0), |
2564 | 0 | UINT64_C(0), |
2565 | 0 | UINT64_C(0), |
2566 | 0 | UINT64_C(0), |
2567 | 0 | UINT64_C(0), |
2568 | 0 | UINT64_C(0), |
2569 | 0 | UINT64_C(0), |
2570 | 0 | UINT64_C(0), |
2571 | 0 | UINT64_C(0), |
2572 | 0 | UINT64_C(0), |
2573 | 0 | UINT64_C(0), |
2574 | 0 | UINT64_C(0), |
2575 | 0 | UINT64_C(0), |
2576 | 0 | UINT64_C(0), |
2577 | 0 | UINT64_C(0), |
2578 | 0 | UINT64_C(0), |
2579 | 0 | UINT64_C(0), |
2580 | 0 | UINT64_C(0), |
2581 | 0 | UINT64_C(0), |
2582 | 0 | UINT64_C(0), |
2583 | 0 | UINT64_C(0), |
2584 | 0 | UINT64_C(0), |
2585 | 0 | UINT64_C(0), |
2586 | 0 | UINT64_C(0), |
2587 | 0 | UINT64_C(0), |
2588 | 0 | UINT64_C(0), |
2589 | 0 | UINT64_C(0), |
2590 | 0 | UINT64_C(0), |
2591 | 0 | UINT64_C(0), |
2592 | 0 | UINT64_C(0), |
2593 | 0 | UINT64_C(0), |
2594 | 0 | UINT64_C(0), |
2595 | 0 | UINT64_C(0), |
2596 | 0 | UINT64_C(0), |
2597 | 0 | UINT64_C(0), |
2598 | 0 | UINT64_C(0), |
2599 | 0 | UINT64_C(0), |
2600 | 0 | UINT64_C(0), |
2601 | 0 | UINT64_C(0), |
2602 | 0 | UINT64_C(0), |
2603 | 0 | UINT64_C(0), |
2604 | 0 | UINT64_C(0), |
2605 | 0 | UINT64_C(0), |
2606 | 0 | UINT64_C(0), |
2607 | 0 | UINT64_C(0), |
2608 | 0 | UINT64_C(0), |
2609 | 0 | UINT64_C(0), |
2610 | 0 | UINT64_C(0), |
2611 | 0 | UINT64_C(0), |
2612 | 0 | UINT64_C(0), |
2613 | 0 | UINT64_C(0), |
2614 | 0 | UINT64_C(0), |
2615 | 0 | UINT64_C(0), |
2616 | 0 | UINT64_C(0), |
2617 | 0 | UINT64_C(0), |
2618 | 0 | UINT64_C(0), |
2619 | 0 | UINT64_C(0), |
2620 | 0 | UINT64_C(0), |
2621 | 0 | UINT64_C(0), |
2622 | 0 | UINT64_C(0), |
2623 | 0 | UINT64_C(0), |
2624 | 0 | UINT64_C(0), |
2625 | 0 | UINT64_C(0), |
2626 | 0 | UINT64_C(0), |
2627 | 0 | UINT64_C(0), |
2628 | 0 | UINT64_C(0), |
2629 | 0 | UINT64_C(0), |
2630 | 0 | UINT64_C(0), |
2631 | 0 | UINT64_C(0), |
2632 | 0 | UINT64_C(0), |
2633 | 0 | UINT64_C(0), |
2634 | 0 | UINT64_C(0), |
2635 | 0 | UINT64_C(0), |
2636 | 0 | UINT64_C(0), |
2637 | 0 | UINT64_C(0), |
2638 | 0 | UINT64_C(0), |
2639 | 0 | UINT64_C(0), |
2640 | 0 | UINT64_C(0), |
2641 | 0 | UINT64_C(0), |
2642 | 0 | UINT64_C(0), |
2643 | 0 | UINT64_C(0), |
2644 | 0 | UINT64_C(0), |
2645 | 0 | UINT64_C(0), |
2646 | 0 | UINT64_C(0), |
2647 | 0 | UINT64_C(0), |
2648 | 0 | UINT64_C(0), |
2649 | 0 | UINT64_C(0), |
2650 | 0 | UINT64_C(0), |
2651 | 0 | UINT64_C(0), |
2652 | 0 | UINT64_C(0), |
2653 | 0 | UINT64_C(0), |
2654 | 0 | UINT64_C(0), |
2655 | 0 | UINT64_C(0), |
2656 | 0 | UINT64_C(0), |
2657 | 0 | UINT64_C(0), |
2658 | 0 | UINT64_C(0), |
2659 | 0 | UINT64_C(0), |
2660 | 0 | UINT64_C(0), |
2661 | 0 | UINT64_C(0), |
2662 | 0 | UINT64_C(0), |
2663 | 0 | UINT64_C(0), |
2664 | 0 | UINT64_C(0), |
2665 | 0 | UINT64_C(0), |
2666 | 0 | UINT64_C(0), |
2667 | 0 | UINT64_C(0), |
2668 | 0 | UINT64_C(0), |
2669 | 0 | UINT64_C(0), |
2670 | 0 | UINT64_C(0), |
2671 | 0 | UINT64_C(0), |
2672 | 0 | UINT64_C(0), |
2673 | 0 | UINT64_C(0), |
2674 | 0 | UINT64_C(0), |
2675 | 0 | UINT64_C(0), |
2676 | 0 | UINT64_C(0), |
2677 | 0 | UINT64_C(0), |
2678 | 0 | UINT64_C(0), |
2679 | 0 | UINT64_C(0), |
2680 | 0 | UINT64_C(0), |
2681 | 0 | UINT64_C(0), |
2682 | 0 | UINT64_C(0), |
2683 | 0 | UINT64_C(0), |
2684 | 0 | UINT64_C(0), |
2685 | 0 | UINT64_C(0), |
2686 | 0 | UINT64_C(0), |
2687 | 0 | UINT64_C(0), |
2688 | 0 | UINT64_C(0), |
2689 | 0 | UINT64_C(0), |
2690 | 0 | UINT64_C(0), |
2691 | 0 | UINT64_C(0), |
2692 | 0 | UINT64_C(0), |
2693 | 0 | UINT64_C(0), |
2694 | 0 | UINT64_C(0), |
2695 | 0 | UINT64_C(0), |
2696 | 0 | UINT64_C(0), |
2697 | 0 | UINT64_C(0), |
2698 | 0 | UINT64_C(0), |
2699 | 0 | UINT64_C(0), |
2700 | 0 | UINT64_C(0), |
2701 | 0 | UINT64_C(0), |
2702 | 0 | UINT64_C(0), |
2703 | 0 | UINT64_C(0), |
2704 | 0 | UINT64_C(0), |
2705 | 0 | UINT64_C(0), |
2706 | 0 | UINT64_C(0), |
2707 | 0 | UINT64_C(0), |
2708 | 0 | UINT64_C(0), |
2709 | 0 | UINT64_C(0), |
2710 | 0 | UINT64_C(0), |
2711 | 0 | UINT64_C(0), |
2712 | 0 | UINT64_C(0), |
2713 | 0 | UINT64_C(0), |
2714 | 0 | UINT64_C(0), |
2715 | 0 | UINT64_C(0), |
2716 | 0 | UINT64_C(0), |
2717 | 0 | UINT64_C(0), |
2718 | 0 | UINT64_C(0), |
2719 | 0 | UINT64_C(0), |
2720 | 0 | UINT64_C(0), |
2721 | 0 | UINT64_C(0), |
2722 | 0 | UINT64_C(0), |
2723 | 0 | UINT64_C(0), |
2724 | 0 | UINT64_C(0), |
2725 | 0 | UINT64_C(0), |
2726 | 0 | UINT64_C(0), |
2727 | 0 | UINT64_C(0), |
2728 | 0 | UINT64_C(0), |
2729 | 0 | UINT64_C(0), |
2730 | 0 | UINT64_C(0), |
2731 | 0 | UINT64_C(0), |
2732 | 0 | UINT64_C(0), |
2733 | 0 | UINT64_C(0), |
2734 | 0 | UINT64_C(0), |
2735 | 0 | UINT64_C(0), |
2736 | 0 | UINT64_C(0), |
2737 | 0 | UINT64_C(0), |
2738 | 0 | UINT64_C(0), |
2739 | 0 | UINT64_C(0), |
2740 | 0 | UINT64_C(0), |
2741 | 0 | UINT64_C(0), |
2742 | 0 | UINT64_C(0), |
2743 | 0 | UINT64_C(0), |
2744 | 0 | UINT64_C(0), |
2745 | 0 | UINT64_C(0), |
2746 | 0 | UINT64_C(0), |
2747 | 0 | UINT64_C(0), |
2748 | 0 | UINT64_C(0), |
2749 | 0 | UINT64_C(0), |
2750 | 0 | UINT64_C(0), |
2751 | 0 | UINT64_C(0), |
2752 | 0 | UINT64_C(0), |
2753 | 0 | UINT64_C(0), |
2754 | 0 | UINT64_C(0), |
2755 | 0 | UINT64_C(0), |
2756 | 0 | UINT64_C(0), |
2757 | 0 | UINT64_C(0), |
2758 | 0 | UINT64_C(0), |
2759 | 0 | UINT64_C(0), |
2760 | 0 | UINT64_C(0), |
2761 | 0 | UINT64_C(0), |
2762 | 0 | UINT64_C(0), |
2763 | 0 | UINT64_C(0), |
2764 | 0 | UINT64_C(0), |
2765 | 0 | UINT64_C(0), |
2766 | 0 | UINT64_C(0), |
2767 | 0 | UINT64_C(0), |
2768 | 0 | UINT64_C(0), |
2769 | 0 | UINT64_C(0), |
2770 | 0 | UINT64_C(0), |
2771 | 0 | UINT64_C(0), |
2772 | 0 | UINT64_C(0), |
2773 | 0 | UINT64_C(0), |
2774 | 0 | UINT64_C(0), |
2775 | 0 | UINT64_C(0), |
2776 | 0 | UINT64_C(0), |
2777 | 0 | UINT64_C(0), |
2778 | 0 | UINT64_C(0), |
2779 | 0 | UINT64_C(0), |
2780 | 0 | UINT64_C(0), |
2781 | 0 | UINT64_C(0), |
2782 | 0 | UINT64_C(0), |
2783 | 0 | UINT64_C(0), |
2784 | 0 | UINT64_C(0), |
2785 | 0 | UINT64_C(0), |
2786 | 0 | UINT64_C(0), |
2787 | 0 | UINT64_C(0), |
2788 | 0 | UINT64_C(0), |
2789 | 0 | UINT64_C(0), |
2790 | 0 | UINT64_C(0), |
2791 | 0 | UINT64_C(0), |
2792 | 0 | UINT64_C(0), |
2793 | 0 | UINT64_C(0), |
2794 | 0 | UINT64_C(0), |
2795 | 0 | UINT64_C(0), |
2796 | 0 | UINT64_C(0), |
2797 | 0 | UINT64_C(0), |
2798 | 0 | UINT64_C(0), |
2799 | 0 | UINT64_C(0), |
2800 | 0 | UINT64_C(0), |
2801 | 0 | UINT64_C(0), |
2802 | 0 | UINT64_C(0), |
2803 | 0 | UINT64_C(0), |
2804 | 0 | UINT64_C(0), |
2805 | 0 | UINT64_C(0), |
2806 | 0 | UINT64_C(0), |
2807 | 0 | UINT64_C(0), |
2808 | 0 | UINT64_C(0), |
2809 | 0 | UINT64_C(0), |
2810 | 0 | UINT64_C(0), |
2811 | 0 | UINT64_C(0), |
2812 | 0 | UINT64_C(0), |
2813 | 0 | UINT64_C(0), |
2814 | 0 | UINT64_C(0), |
2815 | 0 | UINT64_C(0), |
2816 | 0 | UINT64_C(0), |
2817 | 0 | UINT64_C(0), |
2818 | 0 | UINT64_C(0), |
2819 | 0 | UINT64_C(0), |
2820 | 0 | UINT64_C(0), |
2821 | 0 | UINT64_C(0), |
2822 | 0 | UINT64_C(0), |
2823 | 0 | UINT64_C(0), |
2824 | 0 | UINT64_C(0), |
2825 | 0 | UINT64_C(0), |
2826 | 0 | UINT64_C(0), |
2827 | 0 | UINT64_C(0), |
2828 | 0 | UINT64_C(0), |
2829 | 0 | UINT64_C(0), |
2830 | 0 | UINT64_C(0), |
2831 | 0 | UINT64_C(0), |
2832 | 0 | UINT64_C(0), |
2833 | 0 | UINT64_C(0), |
2834 | 0 | UINT64_C(0), |
2835 | 0 | UINT64_C(0), |
2836 | 0 | UINT64_C(0), |
2837 | 0 | UINT64_C(0), |
2838 | 0 | UINT64_C(0), |
2839 | 0 | UINT64_C(0), |
2840 | 0 | UINT64_C(0), |
2841 | 0 | UINT64_C(0), |
2842 | 0 | UINT64_C(0), |
2843 | 0 | UINT64_C(0), |
2844 | 0 | UINT64_C(0), |
2845 | 0 | UINT64_C(0), |
2846 | 0 | UINT64_C(0), |
2847 | 0 | UINT64_C(0), |
2848 | 0 | UINT64_C(0), |
2849 | 0 | UINT64_C(0), |
2850 | 0 | UINT64_C(0), |
2851 | 0 | UINT64_C(0), |
2852 | 0 | UINT64_C(0), |
2853 | 0 | UINT64_C(0), |
2854 | 0 | UINT64_C(0), |
2855 | 0 | UINT64_C(0), |
2856 | 0 | UINT64_C(0), |
2857 | 0 | UINT64_C(0), |
2858 | 0 | UINT64_C(0), |
2859 | 0 | UINT64_C(0), |
2860 | 0 | UINT64_C(0), |
2861 | 0 | UINT64_C(0), |
2862 | 0 | UINT64_C(0), |
2863 | 0 | UINT64_C(0), |
2864 | 0 | UINT64_C(0), |
2865 | 0 | UINT64_C(0), |
2866 | 0 | UINT64_C(0), |
2867 | 0 | UINT64_C(0), |
2868 | 0 | UINT64_C(0), |
2869 | 0 | UINT64_C(0), |
2870 | 0 | UINT64_C(0), |
2871 | 0 | UINT64_C(0), |
2872 | 0 | UINT64_C(0), |
2873 | 0 | UINT64_C(0), |
2874 | 0 | UINT64_C(0), |
2875 | 0 | UINT64_C(0), |
2876 | 0 | UINT64_C(0), |
2877 | 0 | UINT64_C(0), |
2878 | 0 | UINT64_C(0), |
2879 | 0 | UINT64_C(0), |
2880 | 0 | UINT64_C(0), |
2881 | 0 | UINT64_C(0), |
2882 | 0 | UINT64_C(0), |
2883 | 0 | UINT64_C(0), |
2884 | 0 | UINT64_C(0), |
2885 | 0 | UINT64_C(0), |
2886 | 0 | UINT64_C(0), |
2887 | 0 | UINT64_C(0), |
2888 | 0 | UINT64_C(0), |
2889 | 0 | UINT64_C(0), |
2890 | 0 | UINT64_C(0), |
2891 | 0 | UINT64_C(0), |
2892 | 0 | UINT64_C(0), |
2893 | 0 | UINT64_C(0), |
2894 | 0 | UINT64_C(0), |
2895 | 0 | UINT64_C(0), |
2896 | 0 | UINT64_C(0), |
2897 | 0 | UINT64_C(0), |
2898 | 0 | UINT64_C(0), |
2899 | 0 | UINT64_C(0), |
2900 | 0 | UINT64_C(0), |
2901 | 0 | UINT64_C(0), |
2902 | 0 | UINT64_C(0), |
2903 | 0 | UINT64_C(0), |
2904 | 0 | UINT64_C(0), |
2905 | 0 | UINT64_C(0), |
2906 | 0 | UINT64_C(0), |
2907 | 0 | UINT64_C(0), |
2908 | 0 | UINT64_C(0), |
2909 | 0 | UINT64_C(0), |
2910 | 0 | UINT64_C(0), |
2911 | 0 | UINT64_C(0), |
2912 | 0 | UINT64_C(0), |
2913 | 0 | UINT64_C(0), |
2914 | 0 | UINT64_C(0), |
2915 | 0 | UINT64_C(0), |
2916 | 0 | UINT64_C(0), |
2917 | 0 | UINT64_C(0), |
2918 | 0 | UINT64_C(0), |
2919 | 0 | UINT64_C(0), |
2920 | 0 | UINT64_C(0), |
2921 | 0 | UINT64_C(0), |
2922 | 0 | UINT64_C(0), |
2923 | 0 | UINT64_C(0), |
2924 | 0 | UINT64_C(0), |
2925 | 0 | UINT64_C(0), |
2926 | 0 | UINT64_C(0), |
2927 | 0 | UINT64_C(0), |
2928 | 0 | UINT64_C(0), |
2929 | 0 | UINT64_C(0), |
2930 | 0 | UINT64_C(0), |
2931 | 0 | UINT64_C(0), |
2932 | 0 | UINT64_C(0), |
2933 | 0 | UINT64_C(0), |
2934 | 0 | UINT64_C(0), |
2935 | 0 | UINT64_C(0), |
2936 | 0 | UINT64_C(0), |
2937 | 0 | UINT64_C(0), |
2938 | 0 | UINT64_C(0), |
2939 | 0 | UINT64_C(0), |
2940 | 0 | UINT64_C(0), |
2941 | 0 | UINT64_C(0), |
2942 | 0 | UINT64_C(0), |
2943 | 0 | UINT64_C(0), |
2944 | 0 | UINT64_C(0), |
2945 | 0 | UINT64_C(0), |
2946 | 0 | UINT64_C(0), |
2947 | 0 | UINT64_C(0), |
2948 | 0 | UINT64_C(0), |
2949 | 0 | UINT64_C(0), |
2950 | 0 | UINT64_C(0), |
2951 | 0 | UINT64_C(0), |
2952 | 0 | UINT64_C(0), |
2953 | 0 | UINT64_C(0), |
2954 | 0 | UINT64_C(0), |
2955 | 0 | UINT64_C(0), |
2956 | 0 | UINT64_C(0), |
2957 | 0 | UINT64_C(0), |
2958 | 0 | UINT64_C(0), |
2959 | 0 | UINT64_C(0), |
2960 | 0 | UINT64_C(0), |
2961 | 0 | UINT64_C(0), |
2962 | 0 | UINT64_C(0), |
2963 | 0 | UINT64_C(0), |
2964 | 0 | UINT64_C(0), |
2965 | 0 | UINT64_C(0), |
2966 | 0 | UINT64_C(0), |
2967 | 0 | UINT64_C(0), |
2968 | 0 | UINT64_C(0), |
2969 | 0 | UINT64_C(0), |
2970 | 0 | UINT64_C(0), |
2971 | 0 | UINT64_C(0), |
2972 | 0 | UINT64_C(0), |
2973 | 0 | UINT64_C(0), |
2974 | 0 | UINT64_C(0), |
2975 | 0 | UINT64_C(0), |
2976 | 0 | UINT64_C(0), |
2977 | 0 | UINT64_C(0), |
2978 | 0 | UINT64_C(0), |
2979 | 0 | UINT64_C(0), |
2980 | 0 | UINT64_C(0), |
2981 | 0 | UINT64_C(0), |
2982 | 0 | UINT64_C(0), |
2983 | 0 | UINT64_C(0), |
2984 | 0 | UINT64_C(0), |
2985 | 0 | UINT64_C(0), |
2986 | 0 | UINT64_C(0), |
2987 | 0 | UINT64_C(0), |
2988 | 0 | UINT64_C(0), |
2989 | 0 | UINT64_C(0), |
2990 | 0 | UINT64_C(0), |
2991 | 0 | UINT64_C(0), |
2992 | 0 | UINT64_C(0), |
2993 | 0 | UINT64_C(0), |
2994 | 0 | UINT64_C(0), |
2995 | 0 | UINT64_C(0), |
2996 | 0 | UINT64_C(0), |
2997 | 0 | UINT64_C(0), |
2998 | 0 | UINT64_C(0), |
2999 | 0 | UINT64_C(0), |
3000 | 0 | UINT64_C(0), |
3001 | 0 | UINT64_C(0), |
3002 | 0 | UINT64_C(0), |
3003 | 0 | UINT64_C(0), |
3004 | 0 | UINT64_C(0), |
3005 | 0 | UINT64_C(0), |
3006 | 0 | UINT64_C(0), |
3007 | 0 | UINT64_C(0), |
3008 | 0 | UINT64_C(0), |
3009 | 0 | UINT64_C(0), |
3010 | 0 | UINT64_C(0), |
3011 | 0 | UINT64_C(0), |
3012 | 0 | UINT64_C(0), |
3013 | 0 | UINT64_C(0), |
3014 | 0 | UINT64_C(0), |
3015 | 0 | UINT64_C(0), |
3016 | 0 | UINT64_C(0), |
3017 | 0 | UINT64_C(0), |
3018 | 0 | UINT64_C(0), |
3019 | 0 | UINT64_C(0), |
3020 | 0 | UINT64_C(0), |
3021 | 0 | UINT64_C(0), |
3022 | 0 | UINT64_C(0), |
3023 | 0 | UINT64_C(0), |
3024 | 0 | UINT64_C(0), |
3025 | 0 | UINT64_C(0), |
3026 | 0 | UINT64_C(0), |
3027 | 0 | UINT64_C(0), |
3028 | 0 | UINT64_C(0), |
3029 | 0 | UINT64_C(0), |
3030 | 0 | UINT64_C(0), |
3031 | 0 | UINT64_C(0), |
3032 | 0 | UINT64_C(0), |
3033 | 0 | UINT64_C(0), |
3034 | 0 | UINT64_C(0), |
3035 | 0 | UINT64_C(0), |
3036 | 0 | UINT64_C(0), |
3037 | 0 | UINT64_C(0), |
3038 | 0 | UINT64_C(0), |
3039 | 0 | UINT64_C(0), |
3040 | 0 | UINT64_C(0), |
3041 | 0 | UINT64_C(0), |
3042 | 0 | UINT64_C(0), |
3043 | 0 | UINT64_C(0), |
3044 | 0 | UINT64_C(0), |
3045 | 0 | UINT64_C(0), |
3046 | 0 | UINT64_C(0), |
3047 | 0 | UINT64_C(0), |
3048 | 0 | UINT64_C(0), |
3049 | 0 | UINT64_C(0), |
3050 | 0 | UINT64_C(0), |
3051 | 0 | UINT64_C(0), |
3052 | 0 | UINT64_C(0), |
3053 | 0 | UINT64_C(0), |
3054 | 0 | UINT64_C(0), |
3055 | 0 | UINT64_C(0), |
3056 | 0 | UINT64_C(0), |
3057 | 0 | UINT64_C(0), |
3058 | 0 | UINT64_C(0), |
3059 | 0 | UINT64_C(0), |
3060 | 0 | UINT64_C(0), |
3061 | 0 | UINT64_C(0), |
3062 | 0 | UINT64_C(0), |
3063 | 0 | UINT64_C(0), |
3064 | 0 | UINT64_C(0), |
3065 | 0 | UINT64_C(0), |
3066 | 0 | UINT64_C(0), |
3067 | 0 | UINT64_C(0), |
3068 | 0 | UINT64_C(0), |
3069 | 0 | UINT64_C(0), |
3070 | 0 | UINT64_C(0), |
3071 | 0 | UINT64_C(0), |
3072 | 0 | UINT64_C(0), |
3073 | 0 | UINT64_C(0), |
3074 | 0 | UINT64_C(0), |
3075 | 0 | UINT64_C(0), |
3076 | 0 | UINT64_C(0), |
3077 | 0 | UINT64_C(0), |
3078 | 0 | UINT64_C(0), |
3079 | 0 | UINT64_C(0), |
3080 | 0 | UINT64_C(0), |
3081 | 0 | UINT64_C(0), |
3082 | 0 | UINT64_C(0), |
3083 | 0 | UINT64_C(0), |
3084 | 0 | UINT64_C(0), |
3085 | 0 | UINT64_C(0), |
3086 | 0 | UINT64_C(0), |
3087 | 0 | UINT64_C(0), |
3088 | 0 | UINT64_C(0), |
3089 | 0 | UINT64_C(0), |
3090 | 0 | UINT64_C(0), |
3091 | 0 | UINT64_C(0), |
3092 | 0 | UINT64_C(0), |
3093 | 0 | UINT64_C(0), |
3094 | 0 | UINT64_C(0), |
3095 | 0 | UINT64_C(0), |
3096 | 0 | UINT64_C(0), |
3097 | 0 | UINT64_C(0), |
3098 | 0 | UINT64_C(0), |
3099 | 0 | UINT64_C(0), |
3100 | 0 | UINT64_C(0), |
3101 | 0 | UINT64_C(0), |
3102 | 0 | UINT64_C(0), |
3103 | 0 | UINT64_C(0), |
3104 | 0 | UINT64_C(0), |
3105 | 0 | UINT64_C(0), |
3106 | 0 | UINT64_C(0), |
3107 | 0 | UINT64_C(0), |
3108 | 0 | UINT64_C(0), |
3109 | 0 | UINT64_C(0), |
3110 | 0 | UINT64_C(0), |
3111 | 0 | UINT64_C(0), |
3112 | 0 | UINT64_C(0), |
3113 | 0 | UINT64_C(0), |
3114 | 0 | UINT64_C(0), |
3115 | 0 | UINT64_C(0), |
3116 | 0 | UINT64_C(0), |
3117 | 0 | UINT64_C(0), |
3118 | 0 | UINT64_C(0), |
3119 | 0 | UINT64_C(0), |
3120 | 0 | UINT64_C(0), |
3121 | 0 | UINT64_C(0), |
3122 | 0 | UINT64_C(0), |
3123 | 0 | UINT64_C(0), |
3124 | 0 | UINT64_C(0), |
3125 | 0 | UINT64_C(0), |
3126 | 0 | UINT64_C(0), |
3127 | 0 | UINT64_C(0), |
3128 | 0 | UINT64_C(0), |
3129 | 0 | UINT64_C(0), |
3130 | 0 | UINT64_C(0), |
3131 | 0 | UINT64_C(0), |
3132 | 0 | UINT64_C(0), |
3133 | 0 | UINT64_C(0), |
3134 | 0 | UINT64_C(0), |
3135 | 0 | UINT64_C(0), |
3136 | 0 | UINT64_C(0), |
3137 | 0 | UINT64_C(0), |
3138 | 0 | UINT64_C(0), |
3139 | 0 | UINT64_C(0), |
3140 | 0 | UINT64_C(0), |
3141 | 0 | UINT64_C(0), |
3142 | 0 | UINT64_C(0), |
3143 | 0 | UINT64_C(0), |
3144 | 0 | UINT64_C(0), |
3145 | 0 | UINT64_C(0), |
3146 | 0 | UINT64_C(0), |
3147 | 0 | UINT64_C(0), |
3148 | 0 | UINT64_C(0), |
3149 | 0 | UINT64_C(0), |
3150 | 0 | UINT64_C(0), |
3151 | 0 | UINT64_C(0), |
3152 | 0 | UINT64_C(0), |
3153 | 0 | UINT64_C(0), |
3154 | 0 | UINT64_C(0), |
3155 | 0 | UINT64_C(0), |
3156 | 0 | UINT64_C(0), |
3157 | 0 | UINT64_C(0), |
3158 | 0 | UINT64_C(0), |
3159 | 0 | UINT64_C(0), |
3160 | 0 | UINT64_C(0), |
3161 | 0 | UINT64_C(0), |
3162 | 0 | UINT64_C(0), |
3163 | 0 | UINT64_C(0), |
3164 | 0 | UINT64_C(0), |
3165 | 0 | UINT64_C(0), |
3166 | 0 | UINT64_C(0), |
3167 | 0 | UINT64_C(0), |
3168 | 0 | UINT64_C(0), |
3169 | 0 | UINT64_C(0), |
3170 | 0 | UINT64_C(0), |
3171 | 0 | UINT64_C(0), |
3172 | 0 | UINT64_C(0), |
3173 | 0 | UINT64_C(0), |
3174 | 0 | UINT64_C(0), |
3175 | 0 | UINT64_C(0), |
3176 | 0 | UINT64_C(0), |
3177 | 0 | UINT64_C(0), |
3178 | 0 | UINT64_C(0), |
3179 | 0 | UINT64_C(0), |
3180 | 0 | UINT64_C(0), |
3181 | 0 | UINT64_C(0), |
3182 | 0 | UINT64_C(0), |
3183 | 0 | UINT64_C(0), |
3184 | 0 | UINT64_C(0), |
3185 | 0 | UINT64_C(0), |
3186 | 0 | UINT64_C(0), |
3187 | 0 | UINT64_C(0), |
3188 | 0 | UINT64_C(0), |
3189 | 0 | UINT64_C(0), |
3190 | 0 | UINT64_C(0), |
3191 | 0 | UINT64_C(0), |
3192 | 0 | UINT64_C(0), |
3193 | 0 | UINT64_C(0), |
3194 | 0 | UINT64_C(0), |
3195 | 0 | UINT64_C(0), |
3196 | 0 | UINT64_C(0), |
3197 | 0 | UINT64_C(0), |
3198 | 0 | UINT64_C(0), |
3199 | 0 | UINT64_C(0), |
3200 | 0 | UINT64_C(0), |
3201 | 0 | UINT64_C(0), |
3202 | 0 | UINT64_C(0), |
3203 | 0 | UINT64_C(0), |
3204 | 0 | UINT64_C(0), |
3205 | 0 | UINT64_C(0), |
3206 | 0 | UINT64_C(0), |
3207 | 0 | UINT64_C(0), |
3208 | 0 | UINT64_C(0), |
3209 | 0 | UINT64_C(0), |
3210 | 0 | UINT64_C(0), |
3211 | 0 | UINT64_C(0), |
3212 | 0 | UINT64_C(0), |
3213 | 0 | UINT64_C(0), |
3214 | 0 | UINT64_C(0), |
3215 | 0 | UINT64_C(0), |
3216 | 0 | UINT64_C(0), |
3217 | 0 | UINT64_C(0), |
3218 | 0 | UINT64_C(0), |
3219 | 0 | UINT64_C(0), |
3220 | 0 | UINT64_C(0), |
3221 | 0 | UINT64_C(0), |
3222 | 0 | UINT64_C(0), |
3223 | 0 | UINT64_C(0), |
3224 | 0 | UINT64_C(0), |
3225 | 0 | UINT64_C(0), |
3226 | 0 | UINT64_C(0), |
3227 | 0 | UINT64_C(0), |
3228 | 0 | UINT64_C(0), |
3229 | 0 | UINT64_C(0), |
3230 | 0 | UINT64_C(0), |
3231 | 0 | UINT64_C(0), |
3232 | 0 | UINT64_C(0), |
3233 | 0 | UINT64_C(0), |
3234 | 0 | UINT64_C(0), |
3235 | 0 | UINT64_C(0), |
3236 | 0 | UINT64_C(0), |
3237 | 0 | UINT64_C(0), |
3238 | 0 | UINT64_C(0), |
3239 | 0 | UINT64_C(0), |
3240 | 0 | UINT64_C(0), |
3241 | 0 | UINT64_C(0), |
3242 | 0 | UINT64_C(0), |
3243 | 0 | UINT64_C(0), |
3244 | 0 | UINT64_C(0), |
3245 | 0 | UINT64_C(0), |
3246 | 0 | UINT64_C(0), |
3247 | 0 | UINT64_C(0), |
3248 | 0 | UINT64_C(0), |
3249 | 0 | UINT64_C(0), |
3250 | 0 | UINT64_C(0), |
3251 | 0 | UINT64_C(0), |
3252 | 0 | UINT64_C(0), |
3253 | 0 | UINT64_C(0), |
3254 | 0 | UINT64_C(0), |
3255 | 0 | UINT64_C(0), |
3256 | 0 | UINT64_C(0), |
3257 | 0 | UINT64_C(0), |
3258 | 0 | UINT64_C(0), |
3259 | 0 | UINT64_C(0), |
3260 | 0 | UINT64_C(0), |
3261 | 0 | UINT64_C(0), |
3262 | 0 | UINT64_C(0), |
3263 | 0 | UINT64_C(0), |
3264 | 0 | UINT64_C(0), |
3265 | 0 | UINT64_C(0), |
3266 | 0 | UINT64_C(0), |
3267 | 0 | UINT64_C(0), |
3268 | 0 | UINT64_C(0), |
3269 | 0 | UINT64_C(0), |
3270 | 0 | UINT64_C(0), |
3271 | 0 | UINT64_C(0), |
3272 | 0 | UINT64_C(0), |
3273 | 0 | UINT64_C(0), |
3274 | 0 | UINT64_C(0), |
3275 | 0 | UINT64_C(0), |
3276 | 0 | UINT64_C(0), |
3277 | 0 | UINT64_C(0), |
3278 | 0 | UINT64_C(0), |
3279 | 0 | UINT64_C(0), |
3280 | 0 | UINT64_C(0), |
3281 | 0 | UINT64_C(0), |
3282 | 0 | UINT64_C(0), |
3283 | 0 | UINT64_C(0), |
3284 | 0 | UINT64_C(0), |
3285 | 0 | UINT64_C(0), |
3286 | 0 | UINT64_C(0), |
3287 | 0 | UINT64_C(0), |
3288 | 0 | UINT64_C(0), |
3289 | 0 | UINT64_C(0), |
3290 | 0 | UINT64_C(0), |
3291 | 0 | UINT64_C(0), |
3292 | 0 | UINT64_C(0), |
3293 | 0 | UINT64_C(0), |
3294 | 0 | UINT64_C(0), |
3295 | 0 | UINT64_C(0), |
3296 | 0 | UINT64_C(0), |
3297 | 0 | UINT64_C(0), |
3298 | 0 | UINT64_C(0), |
3299 | 0 | UINT64_C(0), |
3300 | 0 | UINT64_C(0), |
3301 | 0 | UINT64_C(0), |
3302 | 0 | UINT64_C(0), |
3303 | 0 | UINT64_C(0), |
3304 | 0 | UINT64_C(0), |
3305 | 0 | UINT64_C(0), |
3306 | 0 | UINT64_C(0), |
3307 | 0 | UINT64_C(0), |
3308 | 0 | UINT64_C(0), |
3309 | 0 | UINT64_C(0), |
3310 | 0 | UINT64_C(0), |
3311 | 0 | UINT64_C(0), |
3312 | 0 | UINT64_C(0), |
3313 | 0 | UINT64_C(0), |
3314 | 0 | UINT64_C(0), |
3315 | 0 | UINT64_C(0), |
3316 | 0 | UINT64_C(0), |
3317 | 0 | UINT64_C(0), |
3318 | 0 | UINT64_C(0), |
3319 | 0 | UINT64_C(0), |
3320 | 0 | UINT64_C(0), |
3321 | 0 | UINT64_C(0), |
3322 | 0 | UINT64_C(0), |
3323 | 0 | UINT64_C(0), |
3324 | 0 | UINT64_C(0), |
3325 | 0 | UINT64_C(0), |
3326 | 0 | UINT64_C(0), |
3327 | 0 | UINT64_C(0), |
3328 | 0 | UINT64_C(0), |
3329 | 0 | UINT64_C(0), |
3330 | 0 | UINT64_C(0), |
3331 | 0 | UINT64_C(0), |
3332 | 0 | UINT64_C(0), |
3333 | 0 | UINT64_C(0), |
3334 | 0 | UINT64_C(0), |
3335 | 0 | UINT64_C(0), |
3336 | 0 | UINT64_C(0), |
3337 | 0 | UINT64_C(0), |
3338 | 0 | UINT64_C(0), |
3339 | 0 | UINT64_C(0), |
3340 | 0 | UINT64_C(0), |
3341 | 0 | UINT64_C(0), |
3342 | 0 | UINT64_C(0), |
3343 | 0 | UINT64_C(0), |
3344 | 0 | UINT64_C(0), |
3345 | 0 | UINT64_C(0), |
3346 | 0 | UINT64_C(0), |
3347 | 0 | UINT64_C(0), |
3348 | 0 | UINT64_C(0), |
3349 | 0 | UINT64_C(0), |
3350 | 0 | UINT64_C(0), |
3351 | 0 | UINT64_C(0), |
3352 | 0 | UINT64_C(0), |
3353 | 0 | UINT64_C(0), |
3354 | 0 | UINT64_C(0), |
3355 | 0 | UINT64_C(0), |
3356 | 0 | UINT64_C(0), |
3357 | 0 | UINT64_C(0), |
3358 | 0 | UINT64_C(0), |
3359 | 0 | UINT64_C(0), |
3360 | 0 | UINT64_C(0), |
3361 | 0 | UINT64_C(0), |
3362 | 0 | UINT64_C(0), |
3363 | 0 | UINT64_C(0), |
3364 | 0 | UINT64_C(0), |
3365 | 0 | UINT64_C(0), |
3366 | 0 | UINT64_C(0), |
3367 | 0 | UINT64_C(0), |
3368 | 0 | UINT64_C(0), |
3369 | 0 | UINT64_C(0), |
3370 | 0 | UINT64_C(0), |
3371 | 0 | UINT64_C(0), |
3372 | 0 | UINT64_C(0), |
3373 | 0 | UINT64_C(0), |
3374 | 0 | UINT64_C(0), |
3375 | 0 | UINT64_C(0), |
3376 | 0 | UINT64_C(0), |
3377 | 0 | UINT64_C(0), |
3378 | 0 | UINT64_C(0), |
3379 | 0 | UINT64_C(0), |
3380 | 0 | UINT64_C(0), |
3381 | 0 | UINT64_C(0), |
3382 | 0 | UINT64_C(0), |
3383 | 0 | UINT64_C(0), |
3384 | 0 | UINT64_C(0), |
3385 | 0 | UINT64_C(0), |
3386 | 0 | UINT64_C(0), |
3387 | 0 | UINT64_C(0), |
3388 | 0 | UINT64_C(0), |
3389 | 0 | UINT64_C(0), |
3390 | 0 | UINT64_C(0), |
3391 | 0 | UINT64_C(0), |
3392 | 0 | UINT64_C(0), |
3393 | 0 | UINT64_C(0), |
3394 | 0 | UINT64_C(0), |
3395 | 0 | UINT64_C(0), |
3396 | 0 | UINT64_C(0), |
3397 | 0 | UINT64_C(0), |
3398 | 0 | UINT64_C(0), |
3399 | 0 | UINT64_C(0), |
3400 | 0 | UINT64_C(0), |
3401 | 0 | UINT64_C(0), |
3402 | 0 | UINT64_C(0), |
3403 | 0 | UINT64_C(0), |
3404 | 0 | UINT64_C(0), |
3405 | 0 | UINT64_C(0), |
3406 | 0 | UINT64_C(0), |
3407 | 0 | UINT64_C(0), |
3408 | 0 | UINT64_C(0), |
3409 | 0 | UINT64_C(0), |
3410 | 0 | UINT64_C(0), |
3411 | 0 | UINT64_C(0), |
3412 | 0 | UINT64_C(0), |
3413 | 0 | UINT64_C(0), |
3414 | 0 | UINT64_C(0), |
3415 | 0 | UINT64_C(0), |
3416 | 0 | UINT64_C(0), |
3417 | 0 | UINT64_C(0), |
3418 | 0 | UINT64_C(0), |
3419 | 0 | UINT64_C(0), |
3420 | 0 | UINT64_C(0), |
3421 | 0 | UINT64_C(0), |
3422 | 0 | UINT64_C(0), |
3423 | 0 | UINT64_C(0), |
3424 | 0 | UINT64_C(0), |
3425 | 0 | UINT64_C(0), |
3426 | 0 | UINT64_C(0), |
3427 | 0 | UINT64_C(0), |
3428 | 0 | UINT64_C(0), |
3429 | 0 | UINT64_C(0), |
3430 | 0 | UINT64_C(0), |
3431 | 0 | UINT64_C(0), |
3432 | 0 | UINT64_C(0), |
3433 | 0 | UINT64_C(0), |
3434 | 0 | UINT64_C(0), |
3435 | 0 | UINT64_C(0), |
3436 | 0 | UINT64_C(0), |
3437 | 0 | UINT64_C(0), |
3438 | 0 | UINT64_C(0), |
3439 | 0 | UINT64_C(0), |
3440 | 0 | UINT64_C(0), |
3441 | 0 | UINT64_C(0), |
3442 | 0 | UINT64_C(0), |
3443 | 0 | UINT64_C(0), |
3444 | 0 | UINT64_C(0), |
3445 | 0 | UINT64_C(0), |
3446 | 0 | UINT64_C(0), |
3447 | 0 | UINT64_C(0), |
3448 | 0 | UINT64_C(0), |
3449 | 0 | UINT64_C(0), |
3450 | 0 | UINT64_C(0), |
3451 | 0 | UINT64_C(0), |
3452 | 0 | UINT64_C(0), |
3453 | 0 | UINT64_C(0), |
3454 | 0 | UINT64_C(0), |
3455 | 0 | UINT64_C(0), |
3456 | 0 | UINT64_C(0), |
3457 | 0 | UINT64_C(0), |
3458 | 0 | UINT64_C(0), |
3459 | 0 | UINT64_C(0), |
3460 | 0 | UINT64_C(0), |
3461 | 0 | UINT64_C(0), |
3462 | 0 | UINT64_C(0), |
3463 | 0 | UINT64_C(0), |
3464 | 0 | UINT64_C(0), |
3465 | 0 | UINT64_C(0), |
3466 | 0 | UINT64_C(0), |
3467 | 0 | UINT64_C(0), |
3468 | 0 | UINT64_C(0), |
3469 | 0 | UINT64_C(0), |
3470 | 0 | UINT64_C(0), |
3471 | 0 | UINT64_C(0), |
3472 | 0 | UINT64_C(0), |
3473 | 0 | UINT64_C(0), |
3474 | 0 | UINT64_C(0), |
3475 | 0 | UINT64_C(0), |
3476 | 0 | UINT64_C(0), |
3477 | 0 | UINT64_C(0), |
3478 | 0 | UINT64_C(0), |
3479 | 0 | UINT64_C(0), |
3480 | 0 | UINT64_C(0), |
3481 | 0 | UINT64_C(0), |
3482 | 0 | UINT64_C(0), |
3483 | 0 | UINT64_C(0), |
3484 | 0 | UINT64_C(0), |
3485 | 0 | UINT64_C(0), |
3486 | 0 | UINT64_C(0), |
3487 | 0 | UINT64_C(0), |
3488 | 0 | UINT64_C(0), |
3489 | 0 | UINT64_C(0), |
3490 | 0 | UINT64_C(0), |
3491 | 0 | UINT64_C(0), |
3492 | 0 | UINT64_C(0), |
3493 | 0 | UINT64_C(0), |
3494 | 0 | UINT64_C(0), |
3495 | 0 | UINT64_C(0), |
3496 | 0 | UINT64_C(0), |
3497 | 0 | UINT64_C(0), |
3498 | 0 | UINT64_C(0), |
3499 | 0 | UINT64_C(0), |
3500 | 0 | UINT64_C(0), |
3501 | 0 | UINT64_C(0), |
3502 | 0 | UINT64_C(0), |
3503 | 0 | UINT64_C(0), |
3504 | 0 | UINT64_C(0), |
3505 | 0 | UINT64_C(0), |
3506 | 0 | UINT64_C(0), |
3507 | 0 | UINT64_C(0), |
3508 | 0 | UINT64_C(0), |
3509 | 0 | UINT64_C(0), |
3510 | 0 | UINT64_C(0), |
3511 | 0 | UINT64_C(0), |
3512 | 0 | UINT64_C(0), |
3513 | 0 | UINT64_C(0), |
3514 | 0 | UINT64_C(0), |
3515 | 0 | UINT64_C(0), |
3516 | 0 | UINT64_C(0), |
3517 | 0 | UINT64_C(0), |
3518 | 0 | UINT64_C(0), |
3519 | 0 | UINT64_C(0), |
3520 | 0 | UINT64_C(0), |
3521 | 0 | UINT64_C(0), |
3522 | 0 | UINT64_C(0), |
3523 | 0 | UINT64_C(0), |
3524 | 0 | UINT64_C(0), |
3525 | 0 | UINT64_C(0), |
3526 | 0 | UINT64_C(0), |
3527 | 0 | UINT64_C(0), |
3528 | 0 | UINT64_C(0), |
3529 | 0 | UINT64_C(0), |
3530 | 0 | UINT64_C(0), |
3531 | 0 | UINT64_C(0), |
3532 | 0 | UINT64_C(0), |
3533 | 0 | UINT64_C(0), |
3534 | 0 | UINT64_C(0), |
3535 | 0 | UINT64_C(0), |
3536 | 0 | UINT64_C(0), |
3537 | 0 | UINT64_C(0), |
3538 | 0 | UINT64_C(0), |
3539 | 0 | UINT64_C(0), |
3540 | 0 | UINT64_C(0), |
3541 | 0 | UINT64_C(0), |
3542 | 0 | UINT64_C(0), |
3543 | 0 | UINT64_C(0), |
3544 | 0 | UINT64_C(0), |
3545 | 0 | UINT64_C(0), |
3546 | 0 | UINT64_C(0), |
3547 | 0 | UINT64_C(0), |
3548 | 0 | UINT64_C(0), |
3549 | 0 | UINT64_C(0), |
3550 | 0 | UINT64_C(0), |
3551 | 0 | UINT64_C(0), |
3552 | 0 | UINT64_C(0), |
3553 | 0 | UINT64_C(0), |
3554 | 0 | UINT64_C(0), |
3555 | 0 | UINT64_C(0), |
3556 | 0 | UINT64_C(0), |
3557 | 0 | UINT64_C(0), |
3558 | 0 | UINT64_C(0), |
3559 | 0 | UINT64_C(0), |
3560 | 0 | UINT64_C(0), |
3561 | 0 | UINT64_C(0), |
3562 | 0 | UINT64_C(0), |
3563 | 0 | UINT64_C(0), |
3564 | 0 | UINT64_C(0), |
3565 | 0 | UINT64_C(0), |
3566 | 0 | UINT64_C(0), |
3567 | 0 | UINT64_C(0), |
3568 | 0 | UINT64_C(0), |
3569 | 0 | UINT64_C(0), |
3570 | 0 | UINT64_C(0), |
3571 | 0 | UINT64_C(0), |
3572 | 0 | UINT64_C(0), |
3573 | 0 | UINT64_C(0), |
3574 | 0 | UINT64_C(0), |
3575 | 0 | UINT64_C(0), |
3576 | 0 | UINT64_C(0), |
3577 | 0 | UINT64_C(0), |
3578 | 0 | UINT64_C(0), |
3579 | 0 | UINT64_C(0), |
3580 | 0 | UINT64_C(0), |
3581 | 0 | UINT64_C(0), |
3582 | 0 | UINT64_C(0), |
3583 | 0 | UINT64_C(0), |
3584 | 0 | UINT64_C(0), |
3585 | 0 | UINT64_C(0), |
3586 | 0 | UINT64_C(0), |
3587 | 0 | UINT64_C(0), |
3588 | 0 | UINT64_C(0), |
3589 | 0 | UINT64_C(0), |
3590 | 0 | UINT64_C(0), |
3591 | 0 | UINT64_C(0), |
3592 | 0 | UINT64_C(0), |
3593 | 0 | UINT64_C(0), |
3594 | 0 | UINT64_C(0), |
3595 | 0 | UINT64_C(0), |
3596 | 0 | UINT64_C(0), |
3597 | 0 | UINT64_C(0), |
3598 | 0 | UINT64_C(0), |
3599 | 0 | UINT64_C(0), |
3600 | 0 | UINT64_C(0), |
3601 | 0 | UINT64_C(0), |
3602 | 0 | UINT64_C(0), |
3603 | 0 | UINT64_C(0), |
3604 | 0 | UINT64_C(0), |
3605 | 0 | UINT64_C(0), |
3606 | 0 | UINT64_C(0), |
3607 | 0 | UINT64_C(0), |
3608 | 0 | UINT64_C(0), |
3609 | 0 | UINT64_C(0), |
3610 | 0 | UINT64_C(0), |
3611 | 0 | UINT64_C(0), |
3612 | 0 | UINT64_C(0), |
3613 | 0 | UINT64_C(0), |
3614 | 0 | UINT64_C(0), |
3615 | 0 | UINT64_C(0), |
3616 | 0 | UINT64_C(0), |
3617 | 0 | UINT64_C(0), |
3618 | 0 | UINT64_C(0), |
3619 | 0 | UINT64_C(0), |
3620 | 0 | UINT64_C(0), |
3621 | 0 | UINT64_C(0), |
3622 | 0 | UINT64_C(0), |
3623 | 0 | UINT64_C(0), |
3624 | 0 | UINT64_C(0), |
3625 | 0 | UINT64_C(0), |
3626 | 0 | UINT64_C(0), |
3627 | 0 | UINT64_C(0), |
3628 | 0 | UINT64_C(0), |
3629 | 0 | UINT64_C(0), |
3630 | 0 | UINT64_C(0), |
3631 | 0 | UINT64_C(0), |
3632 | 0 | UINT64_C(0), |
3633 | 0 | UINT64_C(0), |
3634 | 0 | UINT64_C(0), |
3635 | 0 | UINT64_C(0), |
3636 | 0 | UINT64_C(0), |
3637 | 0 | UINT64_C(0), |
3638 | 0 | UINT64_C(0), |
3639 | 0 | UINT64_C(0), |
3640 | 0 | UINT64_C(0), |
3641 | 0 | UINT64_C(0), |
3642 | 0 | UINT64_C(0), |
3643 | 0 | UINT64_C(0), |
3644 | 0 | UINT64_C(0), |
3645 | 0 | UINT64_C(0), |
3646 | 0 | UINT64_C(0), |
3647 | 0 | UINT64_C(0), |
3648 | 0 | UINT64_C(0), |
3649 | 0 | UINT64_C(0), |
3650 | 0 | UINT64_C(0), |
3651 | 0 | UINT64_C(0), |
3652 | 0 | UINT64_C(0), |
3653 | 0 | UINT64_C(0), |
3654 | 0 | UINT64_C(0), |
3655 | 0 | UINT64_C(0), |
3656 | 0 | UINT64_C(0), |
3657 | 0 | UINT64_C(0), |
3658 | 0 | UINT64_C(0), |
3659 | 0 | UINT64_C(0), |
3660 | 0 | UINT64_C(0), |
3661 | 0 | UINT64_C(0), |
3662 | 0 | UINT64_C(0), |
3663 | 0 | UINT64_C(0), |
3664 | 0 | UINT64_C(0), |
3665 | 0 | UINT64_C(0), |
3666 | 0 | UINT64_C(0), |
3667 | 0 | UINT64_C(0), |
3668 | 0 | UINT64_C(0), |
3669 | 0 | UINT64_C(0), |
3670 | 0 | UINT64_C(0), |
3671 | 0 | UINT64_C(0), |
3672 | 0 | UINT64_C(0), |
3673 | 0 | UINT64_C(0), |
3674 | 0 | UINT64_C(0), |
3675 | 0 | UINT64_C(0), |
3676 | 0 | UINT64_C(0), |
3677 | 0 | UINT64_C(0), |
3678 | 0 | UINT64_C(0), |
3679 | 0 | UINT64_C(0), |
3680 | 0 | UINT64_C(0), |
3681 | 0 | UINT64_C(0), |
3682 | 0 | UINT64_C(0), |
3683 | 0 | UINT64_C(0), |
3684 | 0 | UINT64_C(0), |
3685 | 0 | UINT64_C(0), |
3686 | 0 | UINT64_C(0), |
3687 | 0 | UINT64_C(0), |
3688 | 0 | UINT64_C(0), |
3689 | 0 | UINT64_C(0), |
3690 | 0 | UINT64_C(0), |
3691 | 0 | UINT64_C(0), |
3692 | 0 | UINT64_C(0), |
3693 | 0 | UINT64_C(0), |
3694 | 0 | UINT64_C(0), |
3695 | 0 | UINT64_C(0), |
3696 | 0 | UINT64_C(0), |
3697 | 0 | UINT64_C(0), |
3698 | 0 | UINT64_C(0), |
3699 | 0 | UINT64_C(0), |
3700 | 0 | UINT64_C(0), |
3701 | 0 | UINT64_C(0), |
3702 | 0 | UINT64_C(0), |
3703 | 0 | UINT64_C(0), |
3704 | 0 | UINT64_C(0), |
3705 | 0 | UINT64_C(0), |
3706 | 0 | UINT64_C(0), |
3707 | 0 | UINT64_C(0), |
3708 | 0 | UINT64_C(0), |
3709 | 0 | UINT64_C(0), |
3710 | 0 | UINT64_C(0), |
3711 | 0 | UINT64_C(0), |
3712 | 0 | UINT64_C(0), |
3713 | 0 | UINT64_C(0), |
3714 | 0 | UINT64_C(0), |
3715 | 0 | UINT64_C(0), |
3716 | 0 | UINT64_C(0), |
3717 | 0 | UINT64_C(0), |
3718 | 0 | UINT64_C(0), |
3719 | 0 | UINT64_C(0), |
3720 | 0 | UINT64_C(0), |
3721 | 0 | UINT64_C(0), |
3722 | 0 | UINT64_C(0), |
3723 | 0 | UINT64_C(0), |
3724 | 0 | UINT64_C(0), |
3725 | 0 | UINT64_C(0), |
3726 | 0 | UINT64_C(0), |
3727 | 0 | UINT64_C(0), |
3728 | 0 | UINT64_C(0), |
3729 | 0 | UINT64_C(0), |
3730 | 0 | UINT64_C(0), |
3731 | 0 | UINT64_C(0), |
3732 | 0 | UINT64_C(0), |
3733 | 0 | UINT64_C(0), |
3734 | 0 | UINT64_C(0), |
3735 | 0 | UINT64_C(0), |
3736 | 0 | UINT64_C(0), |
3737 | 0 | UINT64_C(0), |
3738 | 0 | UINT64_C(0), |
3739 | 0 | UINT64_C(0), |
3740 | 0 | UINT64_C(0), |
3741 | 0 | UINT64_C(0), |
3742 | 0 | UINT64_C(0), |
3743 | 0 | UINT64_C(0), |
3744 | 0 | UINT64_C(0), |
3745 | 0 | UINT64_C(0), |
3746 | 0 | UINT64_C(0), |
3747 | 0 | UINT64_C(0), |
3748 | 0 | UINT64_C(0), |
3749 | 0 | UINT64_C(0), |
3750 | 0 | UINT64_C(0), |
3751 | 0 | UINT64_C(0), |
3752 | 0 | UINT64_C(0), |
3753 | 0 | UINT64_C(0), |
3754 | 0 | UINT64_C(0), |
3755 | 0 | UINT64_C(0), |
3756 | 0 | UINT64_C(0), |
3757 | 0 | UINT64_C(0), |
3758 | 0 | UINT64_C(0), |
3759 | 0 | UINT64_C(0), |
3760 | 0 | UINT64_C(0), |
3761 | 0 | UINT64_C(0), |
3762 | 0 | UINT64_C(0), |
3763 | 0 | UINT64_C(0), |
3764 | 0 | UINT64_C(0), |
3765 | 0 | UINT64_C(0), |
3766 | 0 | UINT64_C(0), |
3767 | 0 | UINT64_C(0), |
3768 | 0 | UINT64_C(0), |
3769 | 0 | UINT64_C(0), |
3770 | 0 | UINT64_C(0), |
3771 | 0 | UINT64_C(0), |
3772 | 0 | UINT64_C(0), |
3773 | 0 | UINT64_C(0), |
3774 | 0 | UINT64_C(0), |
3775 | 0 | UINT64_C(0), |
3776 | 0 | UINT64_C(0), |
3777 | 0 | UINT64_C(0), |
3778 | 0 | UINT64_C(0), |
3779 | 0 | UINT64_C(0), |
3780 | 0 | UINT64_C(0), |
3781 | 0 | UINT64_C(0), |
3782 | 0 | UINT64_C(0), |
3783 | 0 | UINT64_C(0), |
3784 | 0 | UINT64_C(0), |
3785 | 0 | UINT64_C(0), |
3786 | 0 | UINT64_C(0), |
3787 | 0 | UINT64_C(0), |
3788 | 0 | UINT64_C(0), |
3789 | 0 | UINT64_C(0), |
3790 | 0 | UINT64_C(0), |
3791 | 0 | UINT64_C(0), |
3792 | 0 | UINT64_C(0), |
3793 | 0 | UINT64_C(0), |
3794 | 0 | UINT64_C(0), |
3795 | 0 | UINT64_C(0), |
3796 | 0 | UINT64_C(0), |
3797 | 0 | UINT64_C(0), |
3798 | 0 | UINT64_C(0), |
3799 | 0 | UINT64_C(0), |
3800 | 0 | UINT64_C(0), |
3801 | 0 | UINT64_C(0), |
3802 | 0 | UINT64_C(0), |
3803 | 0 | UINT64_C(0), |
3804 | 0 | UINT64_C(0), |
3805 | 0 | UINT64_C(0), |
3806 | 0 | UINT64_C(0), |
3807 | 0 | UINT64_C(0), |
3808 | 0 | UINT64_C(0), |
3809 | 0 | UINT64_C(0), |
3810 | 0 | UINT64_C(0), |
3811 | 0 | UINT64_C(0), |
3812 | 0 | UINT64_C(0), |
3813 | 0 | UINT64_C(0), |
3814 | 0 | UINT64_C(0), |
3815 | 0 | UINT64_C(0), |
3816 | 0 | UINT64_C(0), |
3817 | 0 | UINT64_C(0), |
3818 | 0 | UINT64_C(0), |
3819 | 0 | UINT64_C(0), |
3820 | 0 | UINT64_C(0), |
3821 | 0 | UINT64_C(0), |
3822 | 0 | UINT64_C(0), |
3823 | 0 | UINT64_C(0), |
3824 | 0 | UINT64_C(0), |
3825 | 0 | UINT64_C(0), |
3826 | 0 | UINT64_C(0), |
3827 | 0 | UINT64_C(0), |
3828 | 0 | UINT64_C(0), |
3829 | 0 | UINT64_C(0), |
3830 | 0 | UINT64_C(0), |
3831 | 0 | UINT64_C(0), |
3832 | 0 | UINT64_C(0), |
3833 | 0 | UINT64_C(0), |
3834 | 0 | UINT64_C(0), |
3835 | 0 | UINT64_C(0), |
3836 | 0 | UINT64_C(0), |
3837 | 0 | UINT64_C(0), |
3838 | 0 | UINT64_C(0), |
3839 | 0 | UINT64_C(0), |
3840 | 0 | UINT64_C(0), |
3841 | 0 | UINT64_C(0), |
3842 | 0 | UINT64_C(0), |
3843 | 0 | UINT64_C(0), |
3844 | 0 | UINT64_C(0), |
3845 | 0 | UINT64_C(0), |
3846 | 0 | UINT64_C(0), |
3847 | 0 | UINT64_C(0), |
3848 | 0 | UINT64_C(0), |
3849 | 0 | UINT64_C(0), |
3850 | 0 | UINT64_C(0), |
3851 | 0 | UINT64_C(0), |
3852 | 0 | UINT64_C(0), |
3853 | 0 | UINT64_C(0), |
3854 | 0 | UINT64_C(0), |
3855 | 0 | UINT64_C(0), |
3856 | 0 | UINT64_C(0), |
3857 | 0 | UINT64_C(0), |
3858 | 0 | UINT64_C(0), |
3859 | 0 | UINT64_C(0), |
3860 | 0 | UINT64_C(0), |
3861 | 0 | UINT64_C(0), |
3862 | 0 | UINT64_C(0), |
3863 | 0 | UINT64_C(0), |
3864 | 0 | UINT64_C(0), |
3865 | 0 | UINT64_C(0), |
3866 | 0 | UINT64_C(0), |
3867 | 0 | UINT64_C(0), |
3868 | 0 | UINT64_C(0), |
3869 | 0 | UINT64_C(0), |
3870 | 0 | UINT64_C(0), |
3871 | 0 | UINT64_C(0), |
3872 | 0 | UINT64_C(0), |
3873 | 0 | UINT64_C(0), |
3874 | 0 | UINT64_C(0), |
3875 | 0 | UINT64_C(0), |
3876 | 0 | UINT64_C(0), |
3877 | 0 | UINT64_C(0), |
3878 | 0 | UINT64_C(0), |
3879 | 0 | UINT64_C(0), |
3880 | 0 | UINT64_C(0), |
3881 | 0 | UINT64_C(0), |
3882 | 0 | UINT64_C(0), |
3883 | 0 | UINT64_C(0), |
3884 | 0 | UINT64_C(0), |
3885 | 0 | UINT64_C(0), |
3886 | 0 | UINT64_C(0), |
3887 | 0 | UINT64_C(0), |
3888 | 0 | UINT64_C(0), |
3889 | 0 | UINT64_C(0), |
3890 | 0 | UINT64_C(0), |
3891 | 0 | UINT64_C(0), |
3892 | 0 | UINT64_C(0), |
3893 | 0 | UINT64_C(0), |
3894 | 0 | UINT64_C(0), |
3895 | 0 | UINT64_C(0), |
3896 | 0 | UINT64_C(0), |
3897 | 0 | UINT64_C(0), |
3898 | 0 | UINT64_C(0), |
3899 | 0 | UINT64_C(0), |
3900 | 0 | UINT64_C(0), |
3901 | 0 | UINT64_C(0), |
3902 | 0 | UINT64_C(0), |
3903 | 0 | UINT64_C(0), |
3904 | 0 | UINT64_C(0), |
3905 | 0 | UINT64_C(0), |
3906 | 0 | UINT64_C(0), |
3907 | 0 | UINT64_C(0), |
3908 | 0 | UINT64_C(0), |
3909 | 0 | UINT64_C(0), |
3910 | 0 | UINT64_C(0), |
3911 | 0 | UINT64_C(0), |
3912 | 0 | UINT64_C(0), |
3913 | 0 | UINT64_C(0), |
3914 | 0 | UINT64_C(0), |
3915 | 0 | UINT64_C(0), |
3916 | 0 | UINT64_C(0), |
3917 | 0 | UINT64_C(0), |
3918 | 0 | UINT64_C(0), |
3919 | 0 | UINT64_C(0), |
3920 | 0 | UINT64_C(0), |
3921 | 0 | UINT64_C(0), |
3922 | 0 | UINT64_C(0), |
3923 | 0 | UINT64_C(0), |
3924 | 0 | UINT64_C(0), |
3925 | 0 | UINT64_C(0), |
3926 | 0 | UINT64_C(0), |
3927 | 0 | UINT64_C(0), |
3928 | 0 | UINT64_C(0), |
3929 | 0 | UINT64_C(0), |
3930 | 0 | UINT64_C(0), |
3931 | 0 | UINT64_C(0), |
3932 | 0 | UINT64_C(0), |
3933 | 0 | UINT64_C(0), |
3934 | 0 | UINT64_C(0), |
3935 | 0 | UINT64_C(0), |
3936 | 0 | UINT64_C(0), |
3937 | 0 | UINT64_C(0), |
3938 | 0 | UINT64_C(0), |
3939 | 0 | UINT64_C(0), |
3940 | 0 | UINT64_C(0), |
3941 | 0 | UINT64_C(0), |
3942 | 0 | UINT64_C(0), |
3943 | 0 | UINT64_C(0), |
3944 | 0 | UINT64_C(0), |
3945 | 0 | UINT64_C(0), |
3946 | 0 | UINT64_C(0), |
3947 | 0 | UINT64_C(0), |
3948 | 0 | UINT64_C(0), |
3949 | 0 | UINT64_C(0), |
3950 | 0 | UINT64_C(0), |
3951 | 0 | UINT64_C(0), |
3952 | 0 | UINT64_C(0), |
3953 | 0 | UINT64_C(0), |
3954 | 0 | UINT64_C(0), |
3955 | 0 | UINT64_C(0), |
3956 | 0 | UINT64_C(0), |
3957 | 0 | UINT64_C(0), |
3958 | 0 | UINT64_C(0), |
3959 | 0 | UINT64_C(0), |
3960 | 0 | UINT64_C(0), |
3961 | 0 | UINT64_C(0), |
3962 | 0 | UINT64_C(0), |
3963 | 0 | UINT64_C(0), |
3964 | 0 | UINT64_C(0), |
3965 | 0 | UINT64_C(0), |
3966 | 0 | UINT64_C(0), |
3967 | 0 | UINT64_C(0), |
3968 | 0 | UINT64_C(0), |
3969 | 0 | UINT64_C(0), |
3970 | 0 | UINT64_C(0), |
3971 | 0 | UINT64_C(0), |
3972 | 0 | UINT64_C(0), |
3973 | 0 | UINT64_C(0), |
3974 | 0 | UINT64_C(0), |
3975 | 0 | UINT64_C(0), |
3976 | 0 | UINT64_C(0), |
3977 | 0 | UINT64_C(0), |
3978 | 0 | UINT64_C(0), |
3979 | 0 | UINT64_C(0), |
3980 | 0 | UINT64_C(0), |
3981 | 0 | UINT64_C(0), |
3982 | 0 | UINT64_C(0), |
3983 | 0 | UINT64_C(0), |
3984 | 0 | UINT64_C(0), |
3985 | 0 | UINT64_C(0), |
3986 | 0 | UINT64_C(0), |
3987 | 0 | UINT64_C(0), |
3988 | 0 | UINT64_C(0), |
3989 | 0 | UINT64_C(0), |
3990 | 0 | UINT64_C(0), |
3991 | 0 | UINT64_C(0), |
3992 | 0 | UINT64_C(0), |
3993 | 0 | UINT64_C(0), |
3994 | 0 | UINT64_C(0), |
3995 | 0 | UINT64_C(0), |
3996 | 0 | UINT64_C(0), |
3997 | 0 | UINT64_C(0), |
3998 | 0 | UINT64_C(0), |
3999 | 0 | UINT64_C(0), |
4000 | 0 | UINT64_C(0), |
4001 | 0 | UINT64_C(0), |
4002 | 0 | UINT64_C(0), |
4003 | 0 | UINT64_C(0), |
4004 | 0 | UINT64_C(0), |
4005 | 0 | UINT64_C(0), |
4006 | 0 | UINT64_C(0), |
4007 | 0 | UINT64_C(0), |
4008 | 0 | UINT64_C(0), |
4009 | 0 | UINT64_C(0), |
4010 | 0 | UINT64_C(0), |
4011 | 0 | UINT64_C(0), |
4012 | 0 | UINT64_C(0), |
4013 | 0 | UINT64_C(0), |
4014 | 0 | UINT64_C(0), |
4015 | 0 | UINT64_C(0), |
4016 | 0 | UINT64_C(0), |
4017 | 0 | UINT64_C(0), |
4018 | 0 | UINT64_C(0), |
4019 | 0 | UINT64_C(0), |
4020 | 0 | UINT64_C(0), |
4021 | 0 | UINT64_C(0), |
4022 | 0 | UINT64_C(0), |
4023 | 0 | UINT64_C(0), |
4024 | 0 | UINT64_C(0), |
4025 | 0 | UINT64_C(0), |
4026 | 0 | UINT64_C(0), |
4027 | 0 | UINT64_C(0), |
4028 | 0 | UINT64_C(0), |
4029 | 0 | UINT64_C(0), |
4030 | 0 | UINT64_C(0), |
4031 | 0 | UINT64_C(0), |
4032 | 0 | UINT64_C(0), |
4033 | 0 | UINT64_C(0), |
4034 | 0 | UINT64_C(0), |
4035 | 0 | UINT64_C(0), |
4036 | 0 | UINT64_C(0), |
4037 | 0 | UINT64_C(0), |
4038 | 0 | UINT64_C(0), |
4039 | 0 | UINT64_C(0), |
4040 | 0 | UINT64_C(0), |
4041 | 0 | UINT64_C(0), |
4042 | 0 | UINT64_C(0), |
4043 | 0 | UINT64_C(0), |
4044 | 0 | UINT64_C(0), |
4045 | 0 | UINT64_C(0), |
4046 | 0 | UINT64_C(0), |
4047 | 0 | UINT64_C(0), |
4048 | 0 | UINT64_C(0), |
4049 | 0 | UINT64_C(0), |
4050 | 0 | UINT64_C(0), |
4051 | 0 | UINT64_C(0), |
4052 | 0 | UINT64_C(0), |
4053 | 0 | UINT64_C(0), |
4054 | 0 | UINT64_C(0), |
4055 | 0 | UINT64_C(0), |
4056 | 0 | UINT64_C(0), |
4057 | 0 | UINT64_C(0), |
4058 | 0 | UINT64_C(0), |
4059 | 0 | UINT64_C(0), |
4060 | 0 | UINT64_C(0), |
4061 | 0 | UINT64_C(0), |
4062 | 0 | UINT64_C(0), |
4063 | 0 | UINT64_C(0), |
4064 | 0 | UINT64_C(0), |
4065 | 0 | UINT64_C(0), |
4066 | 0 | UINT64_C(0), |
4067 | 0 | UINT64_C(0), |
4068 | 0 | UINT64_C(0), |
4069 | 0 | UINT64_C(0), |
4070 | 0 | UINT64_C(0), |
4071 | 0 | UINT64_C(0), |
4072 | 0 | UINT64_C(0), |
4073 | 0 | UINT64_C(0), |
4074 | 0 | UINT64_C(0), |
4075 | 0 | UINT64_C(0), |
4076 | 0 | UINT64_C(0), |
4077 | 0 | UINT64_C(0), |
4078 | 0 | UINT64_C(0), |
4079 | 0 | UINT64_C(0), |
4080 | 0 | UINT64_C(0), |
4081 | 0 | UINT64_C(0), |
4082 | 0 | UINT64_C(0), |
4083 | 0 | UINT64_C(0), |
4084 | 0 | UINT64_C(0), |
4085 | 0 | UINT64_C(0), |
4086 | 0 | UINT64_C(0), |
4087 | 0 | UINT64_C(0), |
4088 | 0 | UINT64_C(0), |
4089 | 0 | UINT64_C(0), |
4090 | 0 | UINT64_C(0), |
4091 | 0 | UINT64_C(0), |
4092 | 0 | UINT64_C(0), |
4093 | 0 | UINT64_C(0), |
4094 | 0 | UINT64_C(0), |
4095 | 0 | UINT64_C(0), |
4096 | 0 | UINT64_C(0), |
4097 | 0 | UINT64_C(0), |
4098 | 0 | UINT64_C(0), |
4099 | 0 | UINT64_C(0), |
4100 | 0 | UINT64_C(0), |
4101 | 0 | UINT64_C(0), |
4102 | 0 | UINT64_C(0), |
4103 | 0 | UINT64_C(0), |
4104 | 0 | UINT64_C(0), |
4105 | 0 | UINT64_C(0), |
4106 | 0 | UINT64_C(0), |
4107 | 0 | UINT64_C(0), |
4108 | 0 | UINT64_C(0), |
4109 | 0 | UINT64_C(0), |
4110 | 0 | UINT64_C(0), |
4111 | 0 | UINT64_C(0), |
4112 | 0 | UINT64_C(0), |
4113 | 0 | UINT64_C(0), |
4114 | 0 | UINT64_C(0), |
4115 | 0 | UINT64_C(0), |
4116 | 0 | UINT64_C(0), |
4117 | 0 | UINT64_C(0), |
4118 | 0 | UINT64_C(0), |
4119 | 0 | UINT64_C(0), |
4120 | 0 | UINT64_C(0), |
4121 | 0 | UINT64_C(0), |
4122 | 0 | UINT64_C(0), |
4123 | 0 | UINT64_C(0), |
4124 | 0 | UINT64_C(0), |
4125 | 0 | UINT64_C(0), |
4126 | 0 | UINT64_C(0), |
4127 | 0 | UINT64_C(0), |
4128 | 0 | UINT64_C(0), |
4129 | 0 | UINT64_C(0), |
4130 | 0 | UINT64_C(0), |
4131 | 0 | UINT64_C(0), |
4132 | 0 | UINT64_C(0), |
4133 | 0 | UINT64_C(0), |
4134 | 0 | UINT64_C(0), |
4135 | 0 | UINT64_C(0), |
4136 | 0 | UINT64_C(0), |
4137 | 0 | UINT64_C(0), |
4138 | 0 | UINT64_C(0), |
4139 | 0 | UINT64_C(0), |
4140 | 0 | UINT64_C(0), |
4141 | 0 | UINT64_C(0), |
4142 | 0 | UINT64_C(0), |
4143 | 0 | UINT64_C(0), |
4144 | 0 | UINT64_C(0), |
4145 | 0 | UINT64_C(0), |
4146 | 0 | UINT64_C(0), |
4147 | 0 | UINT64_C(0), |
4148 | 0 | UINT64_C(0), |
4149 | 0 | UINT64_C(0), |
4150 | 0 | UINT64_C(0), |
4151 | 0 | UINT64_C(0), |
4152 | 0 | UINT64_C(0), |
4153 | 0 | UINT64_C(0), |
4154 | 0 | UINT64_C(0), |
4155 | 0 | UINT64_C(0), |
4156 | 0 | UINT64_C(0), |
4157 | 0 | UINT64_C(0), |
4158 | 0 | UINT64_C(0), |
4159 | 0 | UINT64_C(0), |
4160 | 0 | UINT64_C(0), |
4161 | 0 | UINT64_C(0), |
4162 | 0 | UINT64_C(0), |
4163 | 0 | UINT64_C(0), |
4164 | 0 | UINT64_C(0), |
4165 | 0 | UINT64_C(0), |
4166 | 0 | UINT64_C(0), |
4167 | 0 | UINT64_C(0), |
4168 | 0 | UINT64_C(0), |
4169 | 0 | UINT64_C(0), |
4170 | 0 | UINT64_C(0), |
4171 | 0 | UINT64_C(0), |
4172 | 0 | UINT64_C(0), |
4173 | 0 | UINT64_C(0), |
4174 | 0 | UINT64_C(0), |
4175 | 0 | UINT64_C(0), |
4176 | 0 | UINT64_C(0), |
4177 | 0 | UINT64_C(0), |
4178 | 0 | UINT64_C(0), |
4179 | 0 | UINT64_C(0), |
4180 | 0 | UINT64_C(0), |
4181 | 0 | UINT64_C(0), |
4182 | 0 | UINT64_C(0), |
4183 | 0 | UINT64_C(0), |
4184 | 0 | UINT64_C(0), |
4185 | 0 | UINT64_C(0), |
4186 | 0 | UINT64_C(0), |
4187 | 0 | UINT64_C(0), |
4188 | 0 | UINT64_C(0), |
4189 | 0 | UINT64_C(0), |
4190 | 0 | UINT64_C(0), |
4191 | 0 | UINT64_C(0), |
4192 | 0 | UINT64_C(0), |
4193 | 0 | UINT64_C(0), |
4194 | 0 | UINT64_C(0), |
4195 | 0 | UINT64_C(0), |
4196 | 0 | UINT64_C(0), |
4197 | 0 | UINT64_C(0), |
4198 | 0 | UINT64_C(0), |
4199 | 0 | UINT64_C(0), |
4200 | 0 | UINT64_C(0), |
4201 | 0 | UINT64_C(0), |
4202 | 0 | UINT64_C(0), |
4203 | 0 | UINT64_C(0), |
4204 | 0 | UINT64_C(0), |
4205 | 0 | UINT64_C(0), |
4206 | 0 | UINT64_C(0), |
4207 | 0 | UINT64_C(0), |
4208 | 0 | UINT64_C(0), |
4209 | 0 | UINT64_C(0), |
4210 | 0 | UINT64_C(0), |
4211 | 0 | UINT64_C(0), |
4212 | 0 | UINT64_C(0), |
4213 | 0 | UINT64_C(0), |
4214 | 0 | UINT64_C(0), |
4215 | 0 | UINT64_C(0), |
4216 | 0 | UINT64_C(0), |
4217 | 0 | UINT64_C(0), |
4218 | 0 | UINT64_C(0), |
4219 | 0 | UINT64_C(0), |
4220 | 0 | UINT64_C(0), |
4221 | 0 | UINT64_C(0), |
4222 | 0 | UINT64_C(0), |
4223 | 0 | UINT64_C(0), |
4224 | 0 | UINT64_C(0), |
4225 | 0 | UINT64_C(0), |
4226 | 0 | UINT64_C(0), |
4227 | 0 | UINT64_C(0), |
4228 | 0 | UINT64_C(0), |
4229 | 0 | UINT64_C(0), |
4230 | 0 | UINT64_C(0), |
4231 | 0 | UINT64_C(0), |
4232 | 0 | UINT64_C(0), |
4233 | 0 | UINT64_C(0), |
4234 | 0 | UINT64_C(0), |
4235 | 0 | UINT64_C(0), |
4236 | 0 | UINT64_C(0), |
4237 | 0 | UINT64_C(0), |
4238 | 0 | UINT64_C(0), |
4239 | 0 | UINT64_C(0), |
4240 | 0 | UINT64_C(0), |
4241 | 0 | UINT64_C(0), |
4242 | 0 | UINT64_C(0), |
4243 | 0 | UINT64_C(0), |
4244 | 0 | UINT64_C(0), |
4245 | 0 | UINT64_C(0), |
4246 | 0 | UINT64_C(0), |
4247 | 0 | UINT64_C(0), |
4248 | 0 | UINT64_C(0), |
4249 | 0 | UINT64_C(0), |
4250 | 0 | UINT64_C(0), |
4251 | 0 | UINT64_C(0), |
4252 | 0 | UINT64_C(0), |
4253 | 0 | UINT64_C(0), |
4254 | 0 | UINT64_C(0), |
4255 | 0 | UINT64_C(0), |
4256 | 0 | UINT64_C(0), |
4257 | 0 | UINT64_C(0), |
4258 | 0 | UINT64_C(0), |
4259 | 0 | UINT64_C(0), |
4260 | 0 | UINT64_C(0), |
4261 | 0 | UINT64_C(0), |
4262 | 0 | UINT64_C(0), |
4263 | 0 | UINT64_C(0), |
4264 | 0 | UINT64_C(0), |
4265 | 0 | UINT64_C(0), |
4266 | 0 | UINT64_C(0), |
4267 | 0 | UINT64_C(0), |
4268 | 0 | UINT64_C(0), |
4269 | 0 | UINT64_C(0), |
4270 | 0 | UINT64_C(0), |
4271 | 0 | UINT64_C(0), |
4272 | 0 | UINT64_C(0), |
4273 | 0 | UINT64_C(0), |
4274 | 0 | UINT64_C(0), |
4275 | 0 | UINT64_C(0), |
4276 | 0 | UINT64_C(0), |
4277 | 0 | UINT64_C(0), |
4278 | 0 | UINT64_C(0), |
4279 | 0 | UINT64_C(0), |
4280 | 0 | UINT64_C(0), |
4281 | 0 | UINT64_C(0), |
4282 | 0 | UINT64_C(0), |
4283 | 0 | UINT64_C(0), |
4284 | 0 | UINT64_C(0), |
4285 | 0 | UINT64_C(0), |
4286 | 0 | UINT64_C(0), |
4287 | 0 | UINT64_C(0), |
4288 | 0 | UINT64_C(0), |
4289 | 0 | UINT64_C(0), |
4290 | 0 | UINT64_C(0), |
4291 | 0 | UINT64_C(0), |
4292 | 0 | UINT64_C(0), |
4293 | 0 | UINT64_C(0), |
4294 | 0 | UINT64_C(0), |
4295 | 0 | UINT64_C(0), |
4296 | 0 | UINT64_C(0), |
4297 | 0 | UINT64_C(0), |
4298 | 0 | UINT64_C(0), |
4299 | 0 | UINT64_C(0), |
4300 | 0 | UINT64_C(0), |
4301 | 0 | UINT64_C(0), |
4302 | 0 | UINT64_C(0), |
4303 | 0 | UINT64_C(0), |
4304 | 0 | UINT64_C(0), |
4305 | 0 | UINT64_C(0), |
4306 | 0 | UINT64_C(0), |
4307 | 0 | UINT64_C(0), |
4308 | 0 | UINT64_C(0), |
4309 | 0 | UINT64_C(0), |
4310 | 0 | UINT64_C(0), |
4311 | 0 | UINT64_C(0), |
4312 | 0 | UINT64_C(0), |
4313 | 0 | UINT64_C(0), |
4314 | 0 | UINT64_C(0), |
4315 | 0 | UINT64_C(0), |
4316 | 0 | UINT64_C(0), |
4317 | 0 | UINT64_C(0), |
4318 | 0 | UINT64_C(0), |
4319 | 0 | UINT64_C(0), |
4320 | 0 | UINT64_C(0), |
4321 | 0 | UINT64_C(0), |
4322 | 0 | UINT64_C(0), |
4323 | 0 | UINT64_C(0), |
4324 | 0 | UINT64_C(0), |
4325 | 0 | UINT64_C(0), |
4326 | 0 | UINT64_C(0), |
4327 | 0 | UINT64_C(0), |
4328 | 0 | UINT64_C(0), |
4329 | 0 | UINT64_C(0), |
4330 | 0 | UINT64_C(0), |
4331 | 0 | UINT64_C(0), |
4332 | 0 | UINT64_C(0), |
4333 | 0 | UINT64_C(0), |
4334 | 0 | UINT64_C(0), |
4335 | 0 | UINT64_C(0), |
4336 | 0 | UINT64_C(0), |
4337 | 0 | UINT64_C(0), |
4338 | 0 | UINT64_C(0), |
4339 | 0 | UINT64_C(0), |
4340 | 0 | UINT64_C(0), |
4341 | 0 | UINT64_C(0), |
4342 | 0 | UINT64_C(0), |
4343 | 0 | UINT64_C(0), |
4344 | 0 | UINT64_C(0), |
4345 | 0 | UINT64_C(0), |
4346 | 0 | UINT64_C(0), |
4347 | 0 | UINT64_C(0), |
4348 | 0 | UINT64_C(0), |
4349 | 0 | UINT64_C(0), |
4350 | 0 | UINT64_C(0), |
4351 | 0 | UINT64_C(0), |
4352 | 0 | UINT64_C(0), |
4353 | 0 | UINT64_C(0), |
4354 | 0 | UINT64_C(0), |
4355 | 0 | UINT64_C(0), |
4356 | 0 | UINT64_C(0), |
4357 | 0 | UINT64_C(0), |
4358 | 0 | UINT64_C(0), |
4359 | 0 | UINT64_C(0), |
4360 | 0 | UINT64_C(0), |
4361 | 0 | UINT64_C(0), |
4362 | 0 | UINT64_C(0), |
4363 | 0 | UINT64_C(0), |
4364 | 0 | UINT64_C(0), |
4365 | 0 | UINT64_C(0), |
4366 | 0 | UINT64_C(0), |
4367 | 0 | UINT64_C(0), |
4368 | 0 | UINT64_C(0), |
4369 | 0 | UINT64_C(0), |
4370 | 0 | UINT64_C(0), |
4371 | 0 | UINT64_C(0), |
4372 | 0 | UINT64_C(0), |
4373 | 0 | UINT64_C(0), |
4374 | 0 | UINT64_C(0), |
4375 | 0 | UINT64_C(0), |
4376 | 0 | UINT64_C(0), |
4377 | 0 | UINT64_C(0), |
4378 | 0 | UINT64_C(0), |
4379 | 0 | UINT64_C(0), |
4380 | 0 | UINT64_C(0), |
4381 | 0 | UINT64_C(0), |
4382 | 0 | UINT64_C(0), |
4383 | 0 | UINT64_C(0), |
4384 | 0 | UINT64_C(0), |
4385 | 0 | UINT64_C(0), |
4386 | 0 | UINT64_C(0), |
4387 | 0 | UINT64_C(0), |
4388 | 0 | UINT64_C(0), |
4389 | 0 | UINT64_C(0), |
4390 | 0 | UINT64_C(0), |
4391 | 0 | UINT64_C(0), |
4392 | 0 | UINT64_C(0), |
4393 | 0 | UINT64_C(0), |
4394 | 0 | UINT64_C(0), |
4395 | 0 | UINT64_C(0), |
4396 | 0 | UINT64_C(0), |
4397 | 0 | UINT64_C(0), |
4398 | 0 | UINT64_C(0), |
4399 | 0 | UINT64_C(0), |
4400 | 0 | UINT64_C(0), |
4401 | 0 | UINT64_C(0), |
4402 | 0 | UINT64_C(0), |
4403 | 0 | UINT64_C(0), |
4404 | 0 | UINT64_C(0), |
4405 | 0 | UINT64_C(0), |
4406 | 0 | UINT64_C(0), |
4407 | 0 | UINT64_C(0), |
4408 | 0 | UINT64_C(0), |
4409 | 0 | UINT64_C(0), |
4410 | 0 | UINT64_C(0), |
4411 | 0 | UINT64_C(0), |
4412 | 0 | UINT64_C(0), |
4413 | 0 | UINT64_C(0), |
4414 | 0 | UINT64_C(0), |
4415 | 0 | UINT64_C(0), |
4416 | 0 | UINT64_C(0), |
4417 | 0 | UINT64_C(0), |
4418 | 0 | UINT64_C(0), |
4419 | 0 | UINT64_C(0), |
4420 | 0 | UINT64_C(0), |
4421 | 0 | UINT64_C(0), |
4422 | 0 | UINT64_C(0), |
4423 | 0 | UINT64_C(0), |
4424 | 0 | UINT64_C(0), |
4425 | 0 | UINT64_C(0), |
4426 | 0 | UINT64_C(0), |
4427 | 0 | UINT64_C(0), |
4428 | 0 | UINT64_C(0), |
4429 | 0 | UINT64_C(0), |
4430 | 0 | UINT64_C(0), |
4431 | 0 | UINT64_C(0), |
4432 | 0 | UINT64_C(0), |
4433 | 0 | UINT64_C(0), |
4434 | 0 | UINT64_C(0), |
4435 | 0 | UINT64_C(0), |
4436 | 0 | UINT64_C(0), |
4437 | 0 | UINT64_C(0), |
4438 | 0 | UINT64_C(0), |
4439 | 0 | UINT64_C(0), |
4440 | 0 | UINT64_C(0), |
4441 | 0 | UINT64_C(0), |
4442 | 0 | UINT64_C(0), |
4443 | 0 | UINT64_C(0), |
4444 | 0 | UINT64_C(0), |
4445 | 0 | UINT64_C(0), |
4446 | 0 | UINT64_C(0), |
4447 | 0 | UINT64_C(0), |
4448 | 0 | UINT64_C(0), |
4449 | 0 | UINT64_C(0), |
4450 | 0 | UINT64_C(0), |
4451 | 0 | UINT64_C(0), |
4452 | 0 | UINT64_C(0), |
4453 | 0 | UINT64_C(0), |
4454 | 0 | UINT64_C(0), |
4455 | 0 | UINT64_C(0), |
4456 | 0 | UINT64_C(0), |
4457 | 0 | UINT64_C(0), |
4458 | 0 | UINT64_C(0), |
4459 | 0 | UINT64_C(0), |
4460 | 0 | UINT64_C(0), |
4461 | 0 | UINT64_C(0), |
4462 | 0 | UINT64_C(0), |
4463 | 0 | UINT64_C(0), |
4464 | 0 | UINT64_C(0), |
4465 | 0 | UINT64_C(0), |
4466 | 0 | UINT64_C(0), |
4467 | 0 | UINT64_C(0), |
4468 | 0 | UINT64_C(0), |
4469 | 0 | UINT64_C(0), |
4470 | 0 | UINT64_C(0), |
4471 | 0 | UINT64_C(0), |
4472 | 0 | UINT64_C(0), |
4473 | 0 | UINT64_C(0), |
4474 | 0 | UINT64_C(0), |
4475 | 0 | UINT64_C(0), |
4476 | 0 | UINT64_C(0), |
4477 | 0 | UINT64_C(0), |
4478 | 0 | UINT64_C(0), |
4479 | 0 | UINT64_C(0), |
4480 | 0 | UINT64_C(0), |
4481 | 0 | UINT64_C(0), |
4482 | 0 | UINT64_C(0), |
4483 | 0 | UINT64_C(0), |
4484 | 0 | UINT64_C(0), |
4485 | 0 | UINT64_C(0), |
4486 | 0 | UINT64_C(0), |
4487 | 0 | UINT64_C(0), |
4488 | 0 | UINT64_C(0), |
4489 | 0 | UINT64_C(0), |
4490 | 0 | UINT64_C(0), |
4491 | 0 | UINT64_C(0), |
4492 | 0 | UINT64_C(0), |
4493 | 0 | UINT64_C(0), |
4494 | 0 | UINT64_C(0), |
4495 | 0 | UINT64_C(0), |
4496 | 0 | UINT64_C(0), |
4497 | 0 | UINT64_C(0), |
4498 | 0 | UINT64_C(0), |
4499 | 0 | UINT64_C(0), |
4500 | 0 | UINT64_C(0), |
4501 | 0 | UINT64_C(0), |
4502 | 0 | UINT64_C(0), |
4503 | 0 | UINT64_C(0), |
4504 | 0 | UINT64_C(0), |
4505 | 0 | UINT64_C(0), |
4506 | 0 | UINT64_C(0), |
4507 | 0 | UINT64_C(0), |
4508 | 0 | UINT64_C(0), |
4509 | 0 | UINT64_C(0), |
4510 | 0 | UINT64_C(0), |
4511 | 0 | UINT64_C(0), |
4512 | 0 | UINT64_C(0), |
4513 | 0 | UINT64_C(0), |
4514 | 0 | UINT64_C(0), |
4515 | 0 | UINT64_C(0), |
4516 | 0 | UINT64_C(0), |
4517 | 0 | UINT64_C(0), |
4518 | 0 | UINT64_C(0), |
4519 | 0 | UINT64_C(0), |
4520 | 0 | UINT64_C(0), |
4521 | 0 | UINT64_C(0), |
4522 | 0 | UINT64_C(0), |
4523 | 0 | UINT64_C(0), |
4524 | 0 | UINT64_C(0), |
4525 | 0 | UINT64_C(0), |
4526 | 0 | UINT64_C(0), |
4527 | 0 | UINT64_C(0), |
4528 | 0 | UINT64_C(0), |
4529 | 0 | UINT64_C(0), |
4530 | 0 | UINT64_C(0), |
4531 | 0 | UINT64_C(0), |
4532 | 0 | UINT64_C(0), |
4533 | 0 | UINT64_C(0), |
4534 | 0 | UINT64_C(0), |
4535 | 0 | UINT64_C(0), |
4536 | 0 | UINT64_C(0), |
4537 | 0 | UINT64_C(0), |
4538 | 0 | UINT64_C(0), |
4539 | 0 | UINT64_C(0), |
4540 | 0 | UINT64_C(0), |
4541 | 0 | UINT64_C(0), |
4542 | 0 | UINT64_C(0), |
4543 | 0 | UINT64_C(0), |
4544 | 0 | UINT64_C(0), |
4545 | 0 | UINT64_C(0), |
4546 | 0 | UINT64_C(0), |
4547 | 0 | UINT64_C(0), |
4548 | 0 | UINT64_C(0), |
4549 | 0 | UINT64_C(0), |
4550 | 0 | UINT64_C(0), |
4551 | 0 | UINT64_C(0), |
4552 | 0 | UINT64_C(0), |
4553 | 0 | UINT64_C(0), |
4554 | 0 | UINT64_C(0), |
4555 | 0 | UINT64_C(0), |
4556 | 0 | UINT64_C(0), |
4557 | 0 | UINT64_C(0), |
4558 | 0 | UINT64_C(0), |
4559 | 0 | UINT64_C(0), |
4560 | 0 | UINT64_C(0), |
4561 | 0 | UINT64_C(0), |
4562 | 0 | UINT64_C(0), |
4563 | 0 | UINT64_C(0), |
4564 | 0 | UINT64_C(0), |
4565 | 0 | UINT64_C(0), |
4566 | 0 | UINT64_C(0), |
4567 | 0 | UINT64_C(0), |
4568 | 0 | UINT64_C(0), |
4569 | 0 | UINT64_C(0), |
4570 | 0 | UINT64_C(0), |
4571 | 0 | UINT64_C(0), |
4572 | 0 | UINT64_C(0), |
4573 | 0 | UINT64_C(0), |
4574 | 0 | UINT64_C(0), |
4575 | 0 | UINT64_C(0), |
4576 | 0 | UINT64_C(0), |
4577 | 0 | UINT64_C(0), |
4578 | 0 | UINT64_C(0), |
4579 | 0 | UINT64_C(0), |
4580 | 0 | UINT64_C(0), |
4581 | 0 | UINT64_C(0), |
4582 | 0 | UINT64_C(0), |
4583 | 0 | UINT64_C(0), |
4584 | 0 | UINT64_C(0), |
4585 | 0 | UINT64_C(0), |
4586 | 0 | UINT64_C(0), |
4587 | 0 | UINT64_C(0), |
4588 | 0 | UINT64_C(0), |
4589 | 0 | UINT64_C(0), |
4590 | 0 | UINT64_C(0), |
4591 | 0 | UINT64_C(0), |
4592 | 0 | UINT64_C(0), |
4593 | 0 | UINT64_C(0), |
4594 | 0 | UINT64_C(0), |
4595 | 0 | UINT64_C(0), |
4596 | 0 | UINT64_C(0), |
4597 | 0 | UINT64_C(0), |
4598 | 0 | UINT64_C(0), |
4599 | 0 | UINT64_C(0), |
4600 | 0 | UINT64_C(0), |
4601 | 0 | UINT64_C(0), |
4602 | 0 | UINT64_C(0), |
4603 | 0 | UINT64_C(0), |
4604 | 0 | UINT64_C(0), |
4605 | 0 | UINT64_C(0), |
4606 | 0 | UINT64_C(0), |
4607 | 0 | UINT64_C(0), |
4608 | 0 | UINT64_C(0), |
4609 | 0 | UINT64_C(0), |
4610 | 0 | UINT64_C(0), |
4611 | 0 | UINT64_C(0), |
4612 | 0 | UINT64_C(0), |
4613 | 0 | UINT64_C(0), |
4614 | 0 | UINT64_C(0), |
4615 | 0 | UINT64_C(0), |
4616 | 0 | UINT64_C(0), |
4617 | 0 | UINT64_C(0), |
4618 | 0 | UINT64_C(0), |
4619 | 0 | UINT64_C(0), |
4620 | 0 | UINT64_C(0), |
4621 | 0 | UINT64_C(0), |
4622 | 0 | UINT64_C(0), |
4623 | 0 | UINT64_C(0), |
4624 | 0 | UINT64_C(0), |
4625 | 0 | UINT64_C(0), |
4626 | 0 | UINT64_C(0), |
4627 | 0 | UINT64_C(0), |
4628 | 0 | UINT64_C(0), |
4629 | 0 | UINT64_C(0), |
4630 | 0 | UINT64_C(0), |
4631 | 0 | UINT64_C(0), |
4632 | 0 | UINT64_C(0), |
4633 | 0 | UINT64_C(0), |
4634 | 0 | UINT64_C(0), |
4635 | 0 | UINT64_C(0), |
4636 | 0 | UINT64_C(0), |
4637 | 0 | UINT64_C(0), |
4638 | 0 | UINT64_C(0), |
4639 | 0 | UINT64_C(0), |
4640 | 0 | UINT64_C(0), |
4641 | 0 | UINT64_C(0), |
4642 | 0 | UINT64_C(0), |
4643 | 0 | UINT64_C(0), |
4644 | 0 | UINT64_C(0), |
4645 | 0 | UINT64_C(0), |
4646 | 0 | UINT64_C(0), |
4647 | 0 | UINT64_C(0), |
4648 | 0 | UINT64_C(0), |
4649 | 0 | UINT64_C(0), |
4650 | 0 | UINT64_C(0), |
4651 | 0 | UINT64_C(0), |
4652 | 0 | UINT64_C(0), |
4653 | 0 | UINT64_C(0), |
4654 | 0 | UINT64_C(0), |
4655 | 0 | UINT64_C(0), |
4656 | 0 | UINT64_C(0), |
4657 | 0 | UINT64_C(0), |
4658 | 0 | UINT64_C(0), |
4659 | 0 | UINT64_C(0), |
4660 | 0 | UINT64_C(0), |
4661 | 0 | UINT64_C(0), |
4662 | 0 | UINT64_C(0), |
4663 | 0 | UINT64_C(0), |
4664 | 0 | UINT64_C(0), |
4665 | 0 | UINT64_C(0), |
4666 | 0 | UINT64_C(0), |
4667 | 0 | UINT64_C(0), |
4668 | 0 | UINT64_C(0), |
4669 | 0 | UINT64_C(0), |
4670 | 0 | UINT64_C(0), |
4671 | 0 | UINT64_C(0), |
4672 | 0 | UINT64_C(0), |
4673 | 0 | UINT64_C(0), |
4674 | 0 | UINT64_C(0), |
4675 | 0 | UINT64_C(0), |
4676 | 0 | UINT64_C(0), |
4677 | 0 | UINT64_C(0), |
4678 | 0 | UINT64_C(0), |
4679 | 0 | UINT64_C(0), |
4680 | 0 | UINT64_C(0), |
4681 | 0 | UINT64_C(0), |
4682 | 0 | UINT64_C(0), |
4683 | 0 | UINT64_C(0), |
4684 | 0 | UINT64_C(0), |
4685 | 0 | UINT64_C(0), |
4686 | 0 | UINT64_C(0), |
4687 | 0 | UINT64_C(0), |
4688 | 0 | UINT64_C(0), |
4689 | 0 | UINT64_C(0), |
4690 | 0 | UINT64_C(0), |
4691 | 0 | UINT64_C(0), |
4692 | 0 | UINT64_C(0), |
4693 | 0 | UINT64_C(0), |
4694 | 0 | UINT64_C(0), |
4695 | 0 | UINT64_C(0), |
4696 | 0 | UINT64_C(0), |
4697 | 0 | UINT64_C(0), |
4698 | 0 | UINT64_C(0), |
4699 | 0 | UINT64_C(0), |
4700 | 0 | UINT64_C(0), |
4701 | 0 | UINT64_C(0), |
4702 | 0 | UINT64_C(0), |
4703 | 0 | UINT64_C(0), |
4704 | 0 | UINT64_C(0), |
4705 | 0 | UINT64_C(0), |
4706 | 0 | UINT64_C(0), |
4707 | 0 | UINT64_C(0), |
4708 | 0 | UINT64_C(0), |
4709 | 0 | UINT64_C(0), |
4710 | 0 | UINT64_C(0), |
4711 | 0 | UINT64_C(0), |
4712 | 0 | UINT64_C(0), |
4713 | 0 | UINT64_C(0), |
4714 | 0 | UINT64_C(0), |
4715 | 0 | UINT64_C(0), |
4716 | 0 | UINT64_C(0), |
4717 | 0 | UINT64_C(0), |
4718 | 0 | UINT64_C(0), |
4719 | 0 | UINT64_C(0), |
4720 | 0 | UINT64_C(0), |
4721 | 0 | UINT64_C(0), |
4722 | 0 | UINT64_C(0), |
4723 | 0 | UINT64_C(0), |
4724 | 0 | UINT64_C(0), |
4725 | 0 | UINT64_C(0), |
4726 | 0 | UINT64_C(0), |
4727 | 0 | UINT64_C(0), |
4728 | 0 | UINT64_C(0), |
4729 | 0 | UINT64_C(0), |
4730 | 0 | UINT64_C(0), |
4731 | 0 | UINT64_C(0), |
4732 | 0 | UINT64_C(0), |
4733 | 0 | UINT64_C(0), |
4734 | 0 | UINT64_C(0), |
4735 | 0 | UINT64_C(0), |
4736 | 0 | UINT64_C(0), |
4737 | 0 | UINT64_C(0), |
4738 | 0 | UINT64_C(0), |
4739 | 0 | UINT64_C(0), |
4740 | 0 | UINT64_C(0), |
4741 | 0 | UINT64_C(0), |
4742 | 0 | UINT64_C(0), |
4743 | 0 | UINT64_C(0), |
4744 | 0 | UINT64_C(0), |
4745 | 0 | UINT64_C(0), |
4746 | 0 | UINT64_C(0), |
4747 | 0 | UINT64_C(0), |
4748 | 0 | UINT64_C(0), |
4749 | 0 | UINT64_C(0), |
4750 | 0 | UINT64_C(0), |
4751 | 0 | UINT64_C(0), |
4752 | 0 | UINT64_C(0), |
4753 | 0 | UINT64_C(0), |
4754 | 0 | UINT64_C(0), |
4755 | 0 | UINT64_C(0), |
4756 | 0 | UINT64_C(0), |
4757 | 0 | UINT64_C(0), |
4758 | 0 | UINT64_C(0), |
4759 | 0 | UINT64_C(0), |
4760 | 0 | UINT64_C(0), |
4761 | 0 | UINT64_C(0), |
4762 | 0 | UINT64_C(0), |
4763 | 0 | UINT64_C(0), |
4764 | 0 | UINT64_C(0), |
4765 | 0 | UINT64_C(0), |
4766 | 0 | UINT64_C(0), |
4767 | 0 | UINT64_C(0), |
4768 | 0 | UINT64_C(0), |
4769 | 0 | UINT64_C(0), |
4770 | 0 | UINT64_C(0), |
4771 | 0 | UINT64_C(0), |
4772 | 0 | UINT64_C(0), |
4773 | 0 | UINT64_C(0), |
4774 | 0 | UINT64_C(0), |
4775 | 0 | UINT64_C(0), |
4776 | 0 | UINT64_C(0), |
4777 | 0 | UINT64_C(0), |
4778 | 0 | UINT64_C(0), |
4779 | 0 | UINT64_C(0), |
4780 | 0 | UINT64_C(0), |
4781 | 0 | UINT64_C(0), |
4782 | 0 | UINT64_C(0), |
4783 | 0 | UINT64_C(0), |
4784 | 0 | UINT64_C(0), |
4785 | 0 | UINT64_C(0), |
4786 | 0 | UINT64_C(0), |
4787 | 0 | UINT64_C(0), |
4788 | 0 | UINT64_C(0), |
4789 | 0 | UINT64_C(0), |
4790 | 0 | UINT64_C(0), |
4791 | 0 | UINT64_C(0), |
4792 | 0 | UINT64_C(0), |
4793 | 0 | UINT64_C(0), |
4794 | 0 | UINT64_C(0), |
4795 | 0 | UINT64_C(0), |
4796 | 0 | UINT64_C(0), |
4797 | 0 | UINT64_C(0), |
4798 | 0 | UINT64_C(0), |
4799 | 0 | UINT64_C(0), |
4800 | 0 | UINT64_C(0), |
4801 | 0 | UINT64_C(0), |
4802 | 0 | UINT64_C(0), |
4803 | 0 | UINT64_C(0), |
4804 | 0 | UINT64_C(0), |
4805 | 0 | UINT64_C(0), |
4806 | 0 | UINT64_C(0), |
4807 | 0 | UINT64_C(0), |
4808 | 0 | UINT64_C(0), |
4809 | 0 | UINT64_C(0), |
4810 | 0 | UINT64_C(0), |
4811 | 0 | UINT64_C(0), |
4812 | 0 | UINT64_C(0), |
4813 | 0 | UINT64_C(0), |
4814 | 0 | UINT64_C(0), |
4815 | 0 | UINT64_C(0), |
4816 | 0 | UINT64_C(0), |
4817 | 0 | UINT64_C(0), |
4818 | 0 | UINT64_C(0), |
4819 | 0 | UINT64_C(0), |
4820 | 0 | UINT64_C(0), |
4821 | 0 | UINT64_C(0), |
4822 | 0 | UINT64_C(0), |
4823 | 0 | UINT64_C(0), |
4824 | 0 | UINT64_C(0), |
4825 | 0 | UINT64_C(0), |
4826 | 0 | UINT64_C(0), |
4827 | 0 | UINT64_C(0), |
4828 | 0 | UINT64_C(0), |
4829 | 0 | UINT64_C(0), |
4830 | 0 | UINT64_C(0), |
4831 | 0 | UINT64_C(0), |
4832 | 0 | UINT64_C(0), |
4833 | 0 | UINT64_C(0), |
4834 | 0 | UINT64_C(0), |
4835 | 0 | UINT64_C(0), |
4836 | 0 | UINT64_C(0), |
4837 | 0 | UINT64_C(0), |
4838 | 0 | UINT64_C(0), |
4839 | 0 | UINT64_C(0), |
4840 | 0 | UINT64_C(0), |
4841 | 0 | UINT64_C(0), |
4842 | 0 | UINT64_C(0), |
4843 | 0 | UINT64_C(0), |
4844 | 0 | UINT64_C(0), |
4845 | 0 | UINT64_C(0), |
4846 | 0 | UINT64_C(0), |
4847 | 0 | UINT64_C(0), |
4848 | 0 | UINT64_C(0), |
4849 | 0 | UINT64_C(0), |
4850 | 0 | UINT64_C(0), |
4851 | 0 | UINT64_C(0), |
4852 | 0 | UINT64_C(0), |
4853 | 0 | UINT64_C(0), |
4854 | 0 | UINT64_C(0), |
4855 | 0 | UINT64_C(0), |
4856 | 0 | UINT64_C(0), |
4857 | 0 | UINT64_C(0), |
4858 | 0 | UINT64_C(0), |
4859 | 0 | UINT64_C(0), |
4860 | 0 | UINT64_C(0), |
4861 | 0 | UINT64_C(0), |
4862 | 0 | UINT64_C(0), |
4863 | 0 | UINT64_C(0), |
4864 | 0 | UINT64_C(0), |
4865 | 0 | UINT64_C(0), |
4866 | 0 | UINT64_C(0), |
4867 | 0 | UINT64_C(0), |
4868 | 0 | UINT64_C(0), |
4869 | 0 | UINT64_C(0), |
4870 | 0 | UINT64_C(0), |
4871 | 0 | UINT64_C(0), |
4872 | 0 | UINT64_C(0), |
4873 | 0 | UINT64_C(0), |
4874 | 0 | UINT64_C(0), |
4875 | 0 | UINT64_C(0), |
4876 | 0 | UINT64_C(0), |
4877 | 0 | UINT64_C(0), |
4878 | 0 | UINT64_C(0), |
4879 | 0 | UINT64_C(0), |
4880 | 0 | UINT64_C(0), |
4881 | 0 | UINT64_C(0), |
4882 | 0 | UINT64_C(0), |
4883 | 0 | UINT64_C(0), |
4884 | 0 | UINT64_C(0), |
4885 | 0 | UINT64_C(0), |
4886 | 0 | UINT64_C(0), |
4887 | 0 | UINT64_C(0), |
4888 | 0 | UINT64_C(0), |
4889 | 0 | UINT64_C(0), |
4890 | 0 | UINT64_C(0), |
4891 | 0 | UINT64_C(0), |
4892 | 0 | UINT64_C(0), |
4893 | 0 | UINT64_C(0), |
4894 | 0 | UINT64_C(0), |
4895 | 0 | UINT64_C(0), |
4896 | 0 | UINT64_C(0), |
4897 | 0 | UINT64_C(0), |
4898 | 0 | UINT64_C(0), |
4899 | 0 | UINT64_C(0), |
4900 | 0 | UINT64_C(0), |
4901 | 0 | UINT64_C(0), |
4902 | 0 | UINT64_C(0), |
4903 | 0 | UINT64_C(0), |
4904 | 0 | UINT64_C(0), |
4905 | 0 | UINT64_C(0), |
4906 | 0 | UINT64_C(0), |
4907 | 0 | UINT64_C(0), |
4908 | 0 | UINT64_C(0), |
4909 | 0 | UINT64_C(0), |
4910 | 0 | UINT64_C(0), |
4911 | 0 | UINT64_C(0), |
4912 | 0 | UINT64_C(0), |
4913 | 0 | UINT64_C(0), |
4914 | 0 | UINT64_C(0), |
4915 | 0 | UINT64_C(0), |
4916 | 0 | UINT64_C(0), |
4917 | 0 | UINT64_C(0), |
4918 | 0 | UINT64_C(0), |
4919 | 0 | UINT64_C(0), |
4920 | 0 | UINT64_C(0), |
4921 | 0 | UINT64_C(0), |
4922 | 0 | UINT64_C(0), |
4923 | 0 | UINT64_C(0), |
4924 | 0 | UINT64_C(0), |
4925 | 0 | UINT64_C(0), |
4926 | 0 | UINT64_C(0), |
4927 | 0 | UINT64_C(0), |
4928 | 0 | UINT64_C(0), |
4929 | 0 | UINT64_C(0), |
4930 | 0 | UINT64_C(0), |
4931 | 0 | UINT64_C(0), |
4932 | 0 | UINT64_C(0), |
4933 | 0 | UINT64_C(0), |
4934 | 0 | UINT64_C(0), |
4935 | 0 | UINT64_C(0), |
4936 | 0 | UINT64_C(0), |
4937 | 0 | UINT64_C(0), |
4938 | 0 | UINT64_C(0), |
4939 | 0 | UINT64_C(0), |
4940 | 0 | UINT64_C(0), |
4941 | 0 | UINT64_C(0), |
4942 | 0 | UINT64_C(0), |
4943 | 0 | UINT64_C(0), |
4944 | 0 | UINT64_C(0), |
4945 | 0 | UINT64_C(0), |
4946 | 0 | UINT64_C(0), |
4947 | 0 | UINT64_C(0), |
4948 | 0 | UINT64_C(0), |
4949 | 0 | UINT64_C(0), |
4950 | 0 | UINT64_C(0), |
4951 | 0 | UINT64_C(0), |
4952 | 0 | UINT64_C(0), |
4953 | 0 | UINT64_C(0), |
4954 | 0 | UINT64_C(0), |
4955 | 0 | UINT64_C(0), |
4956 | 0 | UINT64_C(0), |
4957 | 0 | UINT64_C(0), |
4958 | 0 | UINT64_C(0), |
4959 | 0 | UINT64_C(0), |
4960 | 0 | UINT64_C(0), |
4961 | 0 | UINT64_C(0), |
4962 | 0 | UINT64_C(0), |
4963 | 0 | UINT64_C(0), |
4964 | 0 | UINT64_C(0), |
4965 | 0 | UINT64_C(0), |
4966 | 0 | UINT64_C(0), |
4967 | 0 | UINT64_C(0), |
4968 | 0 | UINT64_C(0), |
4969 | 0 | UINT64_C(0), |
4970 | 0 | UINT64_C(0), |
4971 | 0 | UINT64_C(0), |
4972 | 0 | UINT64_C(0), |
4973 | 0 | UINT64_C(0), |
4974 | 0 | UINT64_C(0), |
4975 | 0 | UINT64_C(0), |
4976 | 0 | UINT64_C(0), |
4977 | 0 | UINT64_C(0), |
4978 | 0 | UINT64_C(0), |
4979 | 0 | UINT64_C(0), |
4980 | 0 | UINT64_C(0), |
4981 | 0 | UINT64_C(0), |
4982 | 0 | UINT64_C(0), |
4983 | 0 | UINT64_C(0), |
4984 | 0 | UINT64_C(0), |
4985 | 0 | UINT64_C(0), |
4986 | 0 | UINT64_C(0), |
4987 | 0 | UINT64_C(0), |
4988 | 0 | UINT64_C(0), |
4989 | 0 | UINT64_C(0), |
4990 | 0 | UINT64_C(0), |
4991 | 0 | UINT64_C(0), |
4992 | 0 | UINT64_C(0), |
4993 | 0 | UINT64_C(0), |
4994 | 0 | UINT64_C(0), |
4995 | 0 | UINT64_C(0), |
4996 | 0 | UINT64_C(0), |
4997 | 0 | UINT64_C(0), |
4998 | 0 | UINT64_C(0), |
4999 | 0 | UINT64_C(0), |
5000 | 0 | UINT64_C(0), |
5001 | 0 | UINT64_C(0), |
5002 | 0 | UINT64_C(0), |
5003 | 0 | UINT64_C(0), |
5004 | 0 | UINT64_C(0), |
5005 | 0 | UINT64_C(0), |
5006 | 0 | UINT64_C(0), |
5007 | 0 | UINT64_C(0), |
5008 | 0 | UINT64_C(0), |
5009 | 0 | UINT64_C(0), |
5010 | 0 | UINT64_C(0), |
5011 | 0 | UINT64_C(0), |
5012 | 0 | UINT64_C(0), |
5013 | 0 | UINT64_C(0), |
5014 | 0 | UINT64_C(0), |
5015 | 0 | UINT64_C(0), |
5016 | 0 | UINT64_C(0), |
5017 | 0 | UINT64_C(0), |
5018 | 0 | UINT64_C(0), |
5019 | 0 | UINT64_C(0), |
5020 | 0 | UINT64_C(0), |
5021 | 0 | UINT64_C(0), |
5022 | 0 | UINT64_C(0), |
5023 | 0 | UINT64_C(0), |
5024 | 0 | UINT64_C(0), |
5025 | 0 | UINT64_C(0), |
5026 | 0 | UINT64_C(0), |
5027 | 0 | UINT64_C(0), |
5028 | 0 | UINT64_C(0), |
5029 | 0 | UINT64_C(0), |
5030 | 0 | UINT64_C(0), |
5031 | 0 | UINT64_C(0), |
5032 | 0 | UINT64_C(0), |
5033 | 0 | UINT64_C(0), |
5034 | 0 | UINT64_C(0), |
5035 | 0 | UINT64_C(0), |
5036 | 0 | UINT64_C(0), |
5037 | 0 | UINT64_C(0), |
5038 | 0 | UINT64_C(0), |
5039 | 0 | UINT64_C(0), |
5040 | 0 | UINT64_C(0), |
5041 | 0 | UINT64_C(0), |
5042 | 0 | UINT64_C(0), |
5043 | 0 | UINT64_C(0), |
5044 | 0 | UINT64_C(0), |
5045 | 0 | UINT64_C(0), |
5046 | 0 | UINT64_C(0), |
5047 | 0 | UINT64_C(0), |
5048 | 0 | UINT64_C(0), |
5049 | 0 | UINT64_C(0), |
5050 | 0 | UINT64_C(0), |
5051 | 0 | UINT64_C(0), |
5052 | 0 | UINT64_C(0), |
5053 | 0 | UINT64_C(0), |
5054 | 0 | UINT64_C(0), |
5055 | 0 | UINT64_C(0), |
5056 | 0 | UINT64_C(0), |
5057 | 0 | UINT64_C(0), |
5058 | 0 | UINT64_C(0), |
5059 | 0 | UINT64_C(0), |
5060 | 0 | UINT64_C(0), |
5061 | 0 | UINT64_C(0), |
5062 | 0 | UINT64_C(0), |
5063 | 0 | UINT64_C(0), |
5064 | 0 | UINT64_C(0), |
5065 | 0 | UINT64_C(0), |
5066 | 0 | UINT64_C(0), |
5067 | 0 | UINT64_C(0), |
5068 | 0 | UINT64_C(0), |
5069 | 0 | UINT64_C(0), |
5070 | 0 | UINT64_C(0), |
5071 | 0 | UINT64_C(0), |
5072 | 0 | UINT64_C(0), |
5073 | 0 | UINT64_C(0), |
5074 | 0 | UINT64_C(0), |
5075 | 0 | UINT64_C(0), |
5076 | 0 | UINT64_C(0), |
5077 | 0 | UINT64_C(0), |
5078 | 0 | UINT64_C(0), |
5079 | 0 | UINT64_C(0), |
5080 | 0 | UINT64_C(0), |
5081 | 0 | UINT64_C(0), |
5082 | 0 | UINT64_C(0), |
5083 | 0 | UINT64_C(0), |
5084 | 0 | UINT64_C(0), |
5085 | 0 | UINT64_C(0), |
5086 | 0 | UINT64_C(0), |
5087 | 0 | UINT64_C(0), |
5088 | 0 | UINT64_C(0), |
5089 | 0 | UINT64_C(0), |
5090 | 0 | UINT64_C(0), |
5091 | 0 | UINT64_C(0), |
5092 | 0 | UINT64_C(0), |
5093 | 0 | UINT64_C(0), |
5094 | 0 | UINT64_C(0), |
5095 | 0 | UINT64_C(0), |
5096 | 0 | UINT64_C(0), |
5097 | 0 | UINT64_C(0), |
5098 | 0 | UINT64_C(0), |
5099 | 0 | UINT64_C(0), |
5100 | 0 | UINT64_C(0), |
5101 | 0 | UINT64_C(0), |
5102 | 0 | UINT64_C(0), |
5103 | 0 | UINT64_C(0), |
5104 | 0 | UINT64_C(0), |
5105 | 0 | UINT64_C(0), |
5106 | 0 | UINT64_C(0), |
5107 | 0 | UINT64_C(0), |
5108 | 0 | UINT64_C(0), |
5109 | 0 | UINT64_C(0), |
5110 | 0 | UINT64_C(0), |
5111 | 0 | UINT64_C(0), |
5112 | 0 | UINT64_C(0), |
5113 | 0 | UINT64_C(0), |
5114 | 0 | UINT64_C(0), |
5115 | 0 | UINT64_C(0), |
5116 | 0 | UINT64_C(0), |
5117 | 0 | UINT64_C(0), |
5118 | 0 | UINT64_C(0), |
5119 | 0 | UINT64_C(0), |
5120 | 0 | UINT64_C(0), |
5121 | 0 | UINT64_C(0), |
5122 | 0 | UINT64_C(0), |
5123 | 0 | UINT64_C(0), |
5124 | 0 | UINT64_C(0), |
5125 | 0 | UINT64_C(0), |
5126 | 0 | UINT64_C(0), |
5127 | 0 | UINT64_C(0), |
5128 | 0 | UINT64_C(0), |
5129 | 0 | UINT64_C(0), |
5130 | 0 | UINT64_C(0), |
5131 | 0 | UINT64_C(0), |
5132 | 0 | UINT64_C(0), |
5133 | 0 | UINT64_C(0), |
5134 | 0 | UINT64_C(0), |
5135 | 0 | UINT64_C(0), |
5136 | 0 | UINT64_C(0), |
5137 | 0 | UINT64_C(0), |
5138 | 0 | UINT64_C(0), |
5139 | 0 | UINT64_C(0), |
5140 | 0 | UINT64_C(0), |
5141 | 0 | UINT64_C(0), |
5142 | 0 | UINT64_C(0), |
5143 | 0 | UINT64_C(0), |
5144 | 0 | UINT64_C(0), |
5145 | 0 | UINT64_C(0), |
5146 | 0 | UINT64_C(0), |
5147 | 0 | UINT64_C(0), |
5148 | 0 | UINT64_C(0), |
5149 | 0 | UINT64_C(0), |
5150 | 0 | UINT64_C(0), |
5151 | 0 | UINT64_C(0), |
5152 | 0 | UINT64_C(0), |
5153 | 0 | UINT64_C(0), |
5154 | 0 | UINT64_C(0), |
5155 | 0 | UINT64_C(0), |
5156 | 0 | UINT64_C(0), |
5157 | 0 | UINT64_C(0), |
5158 | 0 | UINT64_C(0), |
5159 | 0 | UINT64_C(0), |
5160 | 0 | UINT64_C(0), |
5161 | 0 | UINT64_C(0), |
5162 | 0 | UINT64_C(0), |
5163 | 0 | UINT64_C(0), |
5164 | 0 | UINT64_C(0), |
5165 | 0 | UINT64_C(0), |
5166 | 0 | UINT64_C(0), |
5167 | 0 | UINT64_C(0), |
5168 | 0 | UINT64_C(0), |
5169 | 0 | UINT64_C(0), |
5170 | 0 | UINT64_C(0), |
5171 | 0 | UINT64_C(0), |
5172 | 0 | UINT64_C(0), |
5173 | 0 | UINT64_C(0), |
5174 | 0 | UINT64_C(0), |
5175 | 0 | UINT64_C(0), |
5176 | 0 | UINT64_C(0), |
5177 | 0 | UINT64_C(0), |
5178 | 0 | UINT64_C(0), |
5179 | 0 | UINT64_C(0), |
5180 | 0 | UINT64_C(0), |
5181 | 0 | UINT64_C(0), |
5182 | 0 | UINT64_C(0), |
5183 | 0 | UINT64_C(0), |
5184 | 0 | UINT64_C(0), |
5185 | 0 | UINT64_C(0), |
5186 | 0 | UINT64_C(0), |
5187 | 0 | UINT64_C(0), |
5188 | 0 | UINT64_C(0), |
5189 | 0 | UINT64_C(0), |
5190 | 0 | UINT64_C(0), |
5191 | 0 | UINT64_C(0), |
5192 | 0 | UINT64_C(0), |
5193 | 0 | UINT64_C(0), |
5194 | 0 | UINT64_C(0), |
5195 | 0 | UINT64_C(0), |
5196 | 0 | UINT64_C(0), |
5197 | 0 | UINT64_C(0), |
5198 | 0 | UINT64_C(0), |
5199 | 0 | UINT64_C(0), |
5200 | 0 | UINT64_C(0), |
5201 | 0 | UINT64_C(0), |
5202 | 0 | UINT64_C(0), |
5203 | 0 | UINT64_C(0), |
5204 | 0 | UINT64_C(0), |
5205 | 0 | UINT64_C(0), |
5206 | 0 | UINT64_C(0), |
5207 | 0 | UINT64_C(0), |
5208 | 0 | UINT64_C(0), |
5209 | 0 | UINT64_C(0), |
5210 | 0 | UINT64_C(0), |
5211 | 0 | UINT64_C(0), |
5212 | 0 | UINT64_C(0), |
5213 | 0 | UINT64_C(0), |
5214 | 0 | UINT64_C(0), |
5215 | 0 | UINT64_C(0), |
5216 | 0 | UINT64_C(0), |
5217 | 0 | UINT64_C(0), |
5218 | 0 | UINT64_C(0), |
5219 | 0 | UINT64_C(0), |
5220 | 0 | UINT64_C(0), |
5221 | 0 | UINT64_C(0), |
5222 | 0 | UINT64_C(0), |
5223 | 0 | UINT64_C(0), |
5224 | 0 | UINT64_C(0), |
5225 | 0 | UINT64_C(0), |
5226 | 0 | UINT64_C(0), |
5227 | 0 | UINT64_C(0), |
5228 | 0 | UINT64_C(0), |
5229 | 0 | UINT64_C(0), |
5230 | 0 | UINT64_C(0), |
5231 | 0 | UINT64_C(0), |
5232 | 0 | UINT64_C(0), |
5233 | 0 | UINT64_C(0), |
5234 | 0 | UINT64_C(0), |
5235 | 0 | UINT64_C(0), |
5236 | 0 | UINT64_C(0), |
5237 | 0 | UINT64_C(0), |
5238 | 0 | UINT64_C(0), |
5239 | 0 | UINT64_C(0), |
5240 | 0 | UINT64_C(0), |
5241 | 0 | UINT64_C(0), |
5242 | 0 | UINT64_C(0), |
5243 | 0 | UINT64_C(0), |
5244 | 0 | UINT64_C(0), |
5245 | 0 | UINT64_C(0), |
5246 | 0 | UINT64_C(0), |
5247 | 0 | UINT64_C(0), |
5248 | 0 | UINT64_C(0), |
5249 | 0 | UINT64_C(0), |
5250 | 0 | UINT64_C(0), |
5251 | 0 | UINT64_C(0), |
5252 | 0 | UINT64_C(0), |
5253 | 0 | UINT64_C(0), |
5254 | 0 | UINT64_C(0), |
5255 | 0 | UINT64_C(0), |
5256 | 0 | UINT64_C(0), |
5257 | 0 | UINT64_C(0), |
5258 | 0 | UINT64_C(0), |
5259 | 0 | UINT64_C(0), |
5260 | 0 | UINT64_C(0), |
5261 | 0 | UINT64_C(0), |
5262 | 0 | UINT64_C(0), |
5263 | 0 | UINT64_C(0), |
5264 | 0 | UINT64_C(0), |
5265 | 0 | UINT64_C(0), |
5266 | 0 | UINT64_C(0), |
5267 | 0 | UINT64_C(0), |
5268 | 0 | UINT64_C(0), |
5269 | 0 | UINT64_C(0), |
5270 | 0 | UINT64_C(0), |
5271 | 0 | UINT64_C(0), |
5272 | 0 | UINT64_C(0), |
5273 | 0 | UINT64_C(0), |
5274 | 0 | UINT64_C(0), |
5275 | 0 | UINT64_C(0), |
5276 | 0 | UINT64_C(0), |
5277 | 0 | UINT64_C(0), |
5278 | 0 | UINT64_C(0), |
5279 | 0 | UINT64_C(0), |
5280 | 0 | UINT64_C(0), |
5281 | 0 | UINT64_C(0), |
5282 | 0 | UINT64_C(0), |
5283 | 0 | UINT64_C(0), |
5284 | 0 | UINT64_C(0), |
5285 | 0 | UINT64_C(0), |
5286 | 0 | UINT64_C(0), |
5287 | 0 | UINT64_C(0), |
5288 | 0 | UINT64_C(0), |
5289 | 0 | UINT64_C(0), |
5290 | 0 | UINT64_C(0), |
5291 | 0 | UINT64_C(0), |
5292 | 0 | UINT64_C(0), |
5293 | 0 | UINT64_C(0), |
5294 | 0 | UINT64_C(0), |
5295 | 0 | UINT64_C(0), |
5296 | 0 | UINT64_C(0), |
5297 | 0 | UINT64_C(0), |
5298 | 0 | UINT64_C(0), |
5299 | 0 | UINT64_C(0), |
5300 | 0 | UINT64_C(0), |
5301 | 0 | UINT64_C(0), |
5302 | 0 | UINT64_C(0), |
5303 | 0 | UINT64_C(0), |
5304 | 0 | UINT64_C(0), |
5305 | 0 | UINT64_C(0), |
5306 | 0 | UINT64_C(0), |
5307 | 0 | UINT64_C(0), |
5308 | 0 | UINT64_C(0), |
5309 | 0 | UINT64_C(0), |
5310 | 0 | UINT64_C(0), |
5311 | 0 | UINT64_C(0), |
5312 | 0 | UINT64_C(0), |
5313 | 0 | UINT64_C(0), |
5314 | 0 | UINT64_C(0), |
5315 | 0 | UINT64_C(0), |
5316 | 0 | UINT64_C(0), |
5317 | 0 | UINT64_C(0), |
5318 | 0 | UINT64_C(0), |
5319 | 0 | UINT64_C(0), |
5320 | 0 | UINT64_C(0), |
5321 | 0 | UINT64_C(0), |
5322 | 0 | UINT64_C(0), |
5323 | 0 | UINT64_C(0), |
5324 | 0 | UINT64_C(0), |
5325 | 0 | UINT64_C(0), |
5326 | 0 | UINT64_C(0), |
5327 | 0 | UINT64_C(0), |
5328 | 0 | UINT64_C(0), |
5329 | 0 | UINT64_C(0), |
5330 | 0 | UINT64_C(0), |
5331 | 0 | UINT64_C(0), |
5332 | 0 | UINT64_C(0), |
5333 | 0 | UINT64_C(0), |
5334 | 0 | UINT64_C(0), |
5335 | 0 | UINT64_C(0), |
5336 | 0 | UINT64_C(0), |
5337 | 0 | UINT64_C(0), |
5338 | 0 | UINT64_C(0), |
5339 | 0 | UINT64_C(0), |
5340 | 0 | UINT64_C(0), |
5341 | 0 | UINT64_C(0), |
5342 | 0 | UINT64_C(0), |
5343 | 0 | UINT64_C(0), |
5344 | 0 | UINT64_C(0), |
5345 | 0 | UINT64_C(0), |
5346 | 0 | UINT64_C(0), |
5347 | 0 | UINT64_C(0), |
5348 | 0 | UINT64_C(0), |
5349 | 0 | UINT64_C(0), |
5350 | 0 | UINT64_C(0), |
5351 | 0 | UINT64_C(0), |
5352 | 0 | UINT64_C(0), |
5353 | 0 | UINT64_C(0), |
5354 | 0 | UINT64_C(0), |
5355 | 0 | UINT64_C(0), |
5356 | 0 | UINT64_C(0), |
5357 | 0 | UINT64_C(0), |
5358 | 0 | UINT64_C(0), |
5359 | 0 | UINT64_C(0), |
5360 | 0 | UINT64_C(0), |
5361 | 0 | UINT64_C(0), |
5362 | 0 | UINT64_C(0), |
5363 | 0 | UINT64_C(0), |
5364 | 0 | UINT64_C(0), |
5365 | 0 | UINT64_C(0), |
5366 | 0 | UINT64_C(0), |
5367 | 0 | UINT64_C(0), |
5368 | 0 | UINT64_C(0), |
5369 | 0 | UINT64_C(0), |
5370 | 0 | UINT64_C(0), |
5371 | 0 | UINT64_C(0), |
5372 | 0 | UINT64_C(0), |
5373 | 0 | UINT64_C(0), |
5374 | 0 | UINT64_C(0), |
5375 | 0 | UINT64_C(0), |
5376 | 0 | UINT64_C(0), |
5377 | 0 | UINT64_C(0), |
5378 | 0 | UINT64_C(0), |
5379 | 0 | UINT64_C(0), |
5380 | 0 | UINT64_C(0), |
5381 | 0 | UINT64_C(0), |
5382 | 0 | UINT64_C(0), |
5383 | 0 | UINT64_C(0), |
5384 | 0 | UINT64_C(0), |
5385 | 0 | UINT64_C(0), |
5386 | 0 | UINT64_C(0), |
5387 | 0 | UINT64_C(0), |
5388 | 0 | UINT64_C(0), |
5389 | 0 | UINT64_C(0), |
5390 | 0 | UINT64_C(0), |
5391 | 0 | UINT64_C(0), |
5392 | 0 | UINT64_C(0), |
5393 | 0 | UINT64_C(0), |
5394 | 0 | UINT64_C(0), |
5395 | 0 | UINT64_C(0), |
5396 | 0 | UINT64_C(0), |
5397 | 0 | UINT64_C(0), |
5398 | 0 | UINT64_C(0), |
5399 | 0 | UINT64_C(0), |
5400 | 0 | UINT64_C(0), |
5401 | 0 | UINT64_C(0), |
5402 | 0 | UINT64_C(0), |
5403 | 0 | UINT64_C(0), |
5404 | 0 | UINT64_C(0), |
5405 | 0 | UINT64_C(0), |
5406 | 0 | UINT64_C(0), |
5407 | 0 | UINT64_C(0), |
5408 | 0 | UINT64_C(0), |
5409 | 0 | UINT64_C(0), |
5410 | 0 | UINT64_C(0), |
5411 | 0 | UINT64_C(0), |
5412 | 0 | UINT64_C(0), |
5413 | 0 | UINT64_C(0), |
5414 | 0 | UINT64_C(0), |
5415 | 0 | UINT64_C(0), |
5416 | 0 | UINT64_C(0), |
5417 | 0 | UINT64_C(0), |
5418 | 0 | UINT64_C(0), |
5419 | 0 | UINT64_C(0), |
5420 | 0 | UINT64_C(0), |
5421 | 0 | UINT64_C(0), |
5422 | 0 | UINT64_C(0), |
5423 | 0 | UINT64_C(0), |
5424 | 0 | UINT64_C(0), |
5425 | 0 | UINT64_C(0), |
5426 | 0 | UINT64_C(0), |
5427 | 0 | UINT64_C(0), |
5428 | 0 | UINT64_C(0), |
5429 | 0 | UINT64_C(0), |
5430 | 0 | UINT64_C(0), |
5431 | 0 | UINT64_C(0), |
5432 | 0 | UINT64_C(0), |
5433 | 0 | UINT64_C(0), |
5434 | 0 | UINT64_C(0), |
5435 | 0 | UINT64_C(0), |
5436 | 0 | UINT64_C(0), |
5437 | 0 | UINT64_C(0), |
5438 | 0 | UINT64_C(0), |
5439 | 0 | UINT64_C(0), |
5440 | 0 | UINT64_C(0), |
5441 | 0 | UINT64_C(0), |
5442 | 0 | UINT64_C(0), |
5443 | 0 | UINT64_C(0), |
5444 | 0 | UINT64_C(0), |
5445 | 0 | UINT64_C(0), |
5446 | 0 | UINT64_C(0), |
5447 | 0 | UINT64_C(0), |
5448 | 0 | UINT64_C(0), |
5449 | 0 | UINT64_C(0), |
5450 | 0 | UINT64_C(0), |
5451 | 0 | UINT64_C(0), |
5452 | 0 | UINT64_C(0), |
5453 | 0 | UINT64_C(0), |
5454 | 0 | UINT64_C(0), |
5455 | 0 | UINT64_C(0), |
5456 | 0 | UINT64_C(0), |
5457 | 0 | UINT64_C(0), |
5458 | 0 | UINT64_C(0), |
5459 | 0 | UINT64_C(0), |
5460 | 0 | UINT64_C(0), |
5461 | 0 | UINT64_C(0), |
5462 | 0 | UINT64_C(0), |
5463 | 0 | UINT64_C(0), |
5464 | 0 | UINT64_C(0), |
5465 | 0 | UINT64_C(0), |
5466 | 0 | UINT64_C(0), |
5467 | 0 | UINT64_C(0), |
5468 | 0 | UINT64_C(0), |
5469 | 0 | UINT64_C(0), |
5470 | 0 | UINT64_C(0), |
5471 | 0 | UINT64_C(0), |
5472 | 0 | UINT64_C(0), |
5473 | 0 | UINT64_C(0), |
5474 | 0 | UINT64_C(0), |
5475 | 0 | UINT64_C(0), |
5476 | 0 | UINT64_C(0), |
5477 | 0 | UINT64_C(0), |
5478 | 0 | UINT64_C(0), |
5479 | 0 | UINT64_C(0), |
5480 | 0 | UINT64_C(0), |
5481 | 0 | UINT64_C(0), |
5482 | 0 | UINT64_C(0), |
5483 | 0 | UINT64_C(0), |
5484 | 0 | UINT64_C(0), |
5485 | 0 | UINT64_C(0), |
5486 | 0 | UINT64_C(0), |
5487 | 0 | UINT64_C(0), |
5488 | 0 | UINT64_C(0), |
5489 | 0 | UINT64_C(0), |
5490 | 0 | UINT64_C(0), |
5491 | 0 | UINT64_C(0), |
5492 | 0 | UINT64_C(0), |
5493 | 0 | UINT64_C(0), |
5494 | 0 | UINT64_C(0), |
5495 | 0 | UINT64_C(0), |
5496 | 0 | UINT64_C(0), |
5497 | 0 | UINT64_C(0), |
5498 | 0 | UINT64_C(0), |
5499 | 0 | UINT64_C(0), |
5500 | 0 | UINT64_C(0), |
5501 | 0 | UINT64_C(0), |
5502 | 0 | UINT64_C(0), |
5503 | 0 | UINT64_C(0), |
5504 | 0 | UINT64_C(0), |
5505 | 0 | UINT64_C(0), |
5506 | 0 | UINT64_C(0), |
5507 | 0 | UINT64_C(0), |
5508 | 0 | UINT64_C(0), |
5509 | 0 | UINT64_C(0), |
5510 | 0 | UINT64_C(0), |
5511 | 0 | UINT64_C(0), |
5512 | 0 | UINT64_C(0), |
5513 | 0 | UINT64_C(0), |
5514 | 0 | UINT64_C(0), |
5515 | 0 | UINT64_C(0), |
5516 | 0 | UINT64_C(0), |
5517 | 0 | UINT64_C(0), |
5518 | 0 | UINT64_C(0), |
5519 | 0 | UINT64_C(0), |
5520 | 0 | UINT64_C(0), |
5521 | 0 | UINT64_C(0), |
5522 | 0 | UINT64_C(0), |
5523 | 0 | UINT64_C(0), |
5524 | 0 | UINT64_C(0), |
5525 | 0 | UINT64_C(0), |
5526 | 0 | UINT64_C(0), |
5527 | 0 | UINT64_C(0), |
5528 | 0 | UINT64_C(0), |
5529 | 0 | UINT64_C(0), |
5530 | 0 | UINT64_C(0), |
5531 | 0 | UINT64_C(0), |
5532 | 0 | UINT64_C(0), |
5533 | 0 | UINT64_C(0), |
5534 | 0 | UINT64_C(0), |
5535 | 0 | UINT64_C(0), |
5536 | 0 | UINT64_C(0), |
5537 | 0 | UINT64_C(0), |
5538 | 0 | UINT64_C(0), |
5539 | 0 | UINT64_C(0), |
5540 | 0 | UINT64_C(0), |
5541 | 0 | UINT64_C(0), |
5542 | 0 | UINT64_C(0), |
5543 | 0 | UINT64_C(0), |
5544 | 0 | UINT64_C(0), |
5545 | 0 | UINT64_C(0), |
5546 | 0 | UINT64_C(0), |
5547 | 0 | UINT64_C(0), |
5548 | 0 | UINT64_C(0), |
5549 | 0 | UINT64_C(0), |
5550 | 0 | UINT64_C(0), |
5551 | 0 | UINT64_C(0), |
5552 | 0 | UINT64_C(0), |
5553 | 0 | UINT64_C(0), |
5554 | 0 | UINT64_C(0), |
5555 | 0 | UINT64_C(0), |
5556 | 0 | UINT64_C(0), |
5557 | 0 | UINT64_C(0), |
5558 | 0 | UINT64_C(0), |
5559 | 0 | UINT64_C(0), |
5560 | 0 | UINT64_C(0), |
5561 | 0 | UINT64_C(0), |
5562 | 0 | UINT64_C(0), |
5563 | 0 | UINT64_C(0), |
5564 | 0 | UINT64_C(0), |
5565 | 0 | UINT64_C(0), |
5566 | 0 | UINT64_C(0), |
5567 | 0 | UINT64_C(0), |
5568 | 0 | UINT64_C(0), |
5569 | 0 | UINT64_C(0), |
5570 | 0 | UINT64_C(0), |
5571 | 0 | UINT64_C(0), |
5572 | 0 | UINT64_C(0), |
5573 | 0 | UINT64_C(0), |
5574 | 0 | UINT64_C(0), |
5575 | 0 | UINT64_C(0), |
5576 | 0 | UINT64_C(0), |
5577 | 0 | UINT64_C(0), |
5578 | 0 | UINT64_C(0), |
5579 | 0 | UINT64_C(0), |
5580 | 0 | UINT64_C(0), |
5581 | 0 | UINT64_C(0), |
5582 | 0 | UINT64_C(0), |
5583 | 0 | UINT64_C(0), |
5584 | 0 | UINT64_C(0), |
5585 | 0 | UINT64_C(0), |
5586 | 0 | UINT64_C(0), |
5587 | 0 | UINT64_C(0), |
5588 | 0 | UINT64_C(0), |
5589 | 0 | UINT64_C(0), |
5590 | 0 | UINT64_C(0), |
5591 | 0 | UINT64_C(0), |
5592 | 0 | UINT64_C(0), |
5593 | 0 | UINT64_C(0), |
5594 | 0 | UINT64_C(0), |
5595 | 0 | UINT64_C(0), |
5596 | 0 | UINT64_C(0), |
5597 | 0 | UINT64_C(0), |
5598 | 0 | UINT64_C(0), |
5599 | 0 | UINT64_C(0), |
5600 | 0 | UINT64_C(0), |
5601 | 0 | UINT64_C(0), |
5602 | 0 | UINT64_C(0), |
5603 | 0 | UINT64_C(0), |
5604 | 0 | UINT64_C(0), |
5605 | 0 | UINT64_C(0), |
5606 | 0 | UINT64_C(0), |
5607 | 0 | UINT64_C(0), |
5608 | 0 | UINT64_C(0), |
5609 | 0 | UINT64_C(0), |
5610 | 0 | UINT64_C(0), |
5611 | 0 | UINT64_C(0), |
5612 | 0 | UINT64_C(0), |
5613 | 0 | UINT64_C(0), |
5614 | 0 | UINT64_C(0), |
5615 | 0 | UINT64_C(0), |
5616 | 0 | UINT64_C(0), |
5617 | 0 | UINT64_C(0), |
5618 | 0 | UINT64_C(0), |
5619 | 0 | UINT64_C(0), |
5620 | 0 | UINT64_C(0), |
5621 | 0 | UINT64_C(0), |
5622 | 0 | UINT64_C(0), |
5623 | 0 | UINT64_C(0), |
5624 | 0 | UINT64_C(0), |
5625 | 0 | UINT64_C(0), |
5626 | 0 | UINT64_C(0), |
5627 | 0 | UINT64_C(0), |
5628 | 0 | UINT64_C(0), |
5629 | 0 | UINT64_C(0), |
5630 | 0 | UINT64_C(0), |
5631 | 0 | UINT64_C(0), |
5632 | 0 | UINT64_C(0), |
5633 | 0 | UINT64_C(0), |
5634 | 0 | UINT64_C(0), |
5635 | 0 | UINT64_C(0), |
5636 | 0 | UINT64_C(0), |
5637 | 0 | UINT64_C(0), |
5638 | 0 | UINT64_C(0), |
5639 | 0 | UINT64_C(0), |
5640 | 0 | UINT64_C(0), |
5641 | 0 | UINT64_C(0), |
5642 | 0 | UINT64_C(0), |
5643 | 0 | UINT64_C(0), |
5644 | 0 | UINT64_C(0), |
5645 | 0 | UINT64_C(0), |
5646 | 0 | UINT64_C(0), |
5647 | 0 | UINT64_C(0), |
5648 | 0 | UINT64_C(0), |
5649 | 0 | UINT64_C(0), |
5650 | 0 | UINT64_C(0), |
5651 | 0 | UINT64_C(0), |
5652 | 0 | UINT64_C(0), |
5653 | 0 | UINT64_C(0), |
5654 | 0 | UINT64_C(0), |
5655 | 0 | UINT64_C(0), |
5656 | 0 | UINT64_C(0), |
5657 | 0 | UINT64_C(0), |
5658 | 0 | UINT64_C(0), |
5659 | 0 | UINT64_C(0), |
5660 | 0 | UINT64_C(0), |
5661 | 0 | UINT64_C(0), |
5662 | 0 | UINT64_C(0), |
5663 | 0 | UINT64_C(0), |
5664 | 0 | UINT64_C(0), |
5665 | 0 | UINT64_C(0), |
5666 | 0 | UINT64_C(0), |
5667 | 0 | UINT64_C(0), |
5668 | 0 | UINT64_C(0), |
5669 | 0 | UINT64_C(0), |
5670 | 0 | UINT64_C(0), |
5671 | 0 | UINT64_C(0), |
5672 | 0 | UINT64_C(0), |
5673 | 0 | UINT64_C(0), |
5674 | 0 | UINT64_C(0), |
5675 | 0 | UINT64_C(0), |
5676 | 0 | UINT64_C(0), |
5677 | 0 | UINT64_C(0), |
5678 | 0 | UINT64_C(0), |
5679 | 0 | UINT64_C(0), |
5680 | 0 | UINT64_C(0), |
5681 | 0 | UINT64_C(0), |
5682 | 0 | UINT64_C(0), |
5683 | 0 | UINT64_C(0), |
5684 | 0 | UINT64_C(0), |
5685 | 0 | UINT64_C(0), |
5686 | 0 | UINT64_C(0), |
5687 | 0 | UINT64_C(0), |
5688 | 0 | UINT64_C(0), |
5689 | 0 | UINT64_C(0), |
5690 | 0 | UINT64_C(0), |
5691 | 0 | UINT64_C(0), |
5692 | 0 | UINT64_C(0), |
5693 | 0 | UINT64_C(0), |
5694 | 0 | UINT64_C(0), |
5695 | 0 | UINT64_C(0), |
5696 | 0 | UINT64_C(0), |
5697 | 0 | UINT64_C(0), |
5698 | 0 | UINT64_C(0), |
5699 | 0 | UINT64_C(0), |
5700 | 0 | UINT64_C(0), |
5701 | 0 | UINT64_C(0), |
5702 | 0 | UINT64_C(0), |
5703 | 0 | UINT64_C(0), |
5704 | 0 | UINT64_C(0), |
5705 | 0 | UINT64_C(0), |
5706 | 0 | UINT64_C(0), |
5707 | 0 | UINT64_C(0), |
5708 | 0 | UINT64_C(0), |
5709 | 0 | UINT64_C(0), |
5710 | 0 | UINT64_C(0), |
5711 | 0 | UINT64_C(0), |
5712 | 0 | UINT64_C(0), |
5713 | 0 | UINT64_C(0), |
5714 | 0 | UINT64_C(0), |
5715 | 0 | UINT64_C(0), |
5716 | 0 | UINT64_C(0), |
5717 | 0 | UINT64_C(0), |
5718 | 0 | UINT64_C(0), |
5719 | 0 | UINT64_C(0), |
5720 | 0 | UINT64_C(0), |
5721 | 0 | UINT64_C(0), |
5722 | 0 | UINT64_C(0), |
5723 | 0 | UINT64_C(0), |
5724 | 0 | UINT64_C(0), |
5725 | 0 | UINT64_C(0), |
5726 | 0 | UINT64_C(0), |
5727 | 0 | UINT64_C(0), |
5728 | 0 | UINT64_C(0), |
5729 | 0 | UINT64_C(0), |
5730 | 0 | UINT64_C(0), |
5731 | 0 | UINT64_C(0), |
5732 | 0 | UINT64_C(0), |
5733 | 0 | UINT64_C(0), |
5734 | 0 | UINT64_C(0), |
5735 | 0 | UINT64_C(0), |
5736 | 0 | UINT64_C(0), |
5737 | 0 | UINT64_C(0), |
5738 | 0 | UINT64_C(0), |
5739 | 0 | UINT64_C(0), |
5740 | 0 | UINT64_C(0), |
5741 | 0 | UINT64_C(0), |
5742 | 0 | UINT64_C(0), |
5743 | 0 | UINT64_C(0), |
5744 | 0 | UINT64_C(0), |
5745 | 0 | UINT64_C(0), |
5746 | 0 | UINT64_C(0), |
5747 | 0 | UINT64_C(0), |
5748 | 0 | UINT64_C(0), |
5749 | 0 | UINT64_C(0), |
5750 | 0 | UINT64_C(0), |
5751 | 0 | UINT64_C(0), |
5752 | 0 | UINT64_C(0), |
5753 | 0 | UINT64_C(0), |
5754 | 0 | UINT64_C(0), |
5755 | 0 | UINT64_C(0), |
5756 | 0 | UINT64_C(0), |
5757 | 0 | UINT64_C(0), |
5758 | 0 | UINT64_C(0), |
5759 | 0 | UINT64_C(0), |
5760 | 0 | UINT64_C(0), |
5761 | 0 | UINT64_C(0), |
5762 | 0 | UINT64_C(0), |
5763 | 0 | UINT64_C(0), |
5764 | 0 | UINT64_C(0), |
5765 | 0 | UINT64_C(0), |
5766 | 0 | UINT64_C(0), |
5767 | 0 | UINT64_C(0), |
5768 | 0 | UINT64_C(0), |
5769 | 0 | UINT64_C(0), |
5770 | 0 | UINT64_C(0), |
5771 | 0 | UINT64_C(0), |
5772 | 0 | UINT64_C(0), |
5773 | 0 | UINT64_C(0), |
5774 | 0 | UINT64_C(0), |
5775 | 0 | UINT64_C(0), |
5776 | 0 | UINT64_C(0), |
5777 | 0 | UINT64_C(0), |
5778 | 0 | UINT64_C(0), |
5779 | 0 | UINT64_C(0), |
5780 | 0 | UINT64_C(0), |
5781 | 0 | UINT64_C(0), |
5782 | 0 | UINT64_C(0), |
5783 | 0 | UINT64_C(0), |
5784 | 0 | UINT64_C(0), |
5785 | 0 | UINT64_C(0), |
5786 | 0 | UINT64_C(0), |
5787 | 0 | UINT64_C(0), |
5788 | 0 | UINT64_C(0), |
5789 | 0 | UINT64_C(0), |
5790 | 0 | UINT64_C(0), |
5791 | 0 | UINT64_C(0), |
5792 | 0 | UINT64_C(0), |
5793 | 0 | UINT64_C(0), |
5794 | 0 | UINT64_C(0), |
5795 | 0 | UINT64_C(0), |
5796 | 0 | UINT64_C(0), |
5797 | 0 | UINT64_C(0), |
5798 | 0 | UINT64_C(0), |
5799 | 0 | UINT64_C(0), |
5800 | 0 | UINT64_C(0), |
5801 | 0 | UINT64_C(0), |
5802 | 0 | UINT64_C(0), |
5803 | 0 | UINT64_C(0), |
5804 | 0 | UINT64_C(0), |
5805 | 0 | UINT64_C(0), |
5806 | 0 | UINT64_C(0), |
5807 | 0 | UINT64_C(0), |
5808 | 0 | UINT64_C(0), |
5809 | 0 | UINT64_C(0), |
5810 | 0 | UINT64_C(0), |
5811 | 0 | UINT64_C(0), |
5812 | 0 | UINT64_C(0), |
5813 | 0 | UINT64_C(0), |
5814 | 0 | UINT64_C(0), |
5815 | 0 | UINT64_C(0), |
5816 | 0 | UINT64_C(0), |
5817 | 0 | UINT64_C(0), |
5818 | 0 | UINT64_C(0), |
5819 | 0 | UINT64_C(0), |
5820 | 0 | UINT64_C(0), |
5821 | 0 | UINT64_C(0), |
5822 | 0 | UINT64_C(0), |
5823 | 0 | UINT64_C(0), |
5824 | 0 | UINT64_C(0), |
5825 | 0 | UINT64_C(0), |
5826 | 0 | UINT64_C(0), |
5827 | 0 | UINT64_C(0), |
5828 | 0 | UINT64_C(0), |
5829 | 0 | UINT64_C(0), |
5830 | 0 | UINT64_C(0), |
5831 | 0 | UINT64_C(0), |
5832 | 0 | UINT64_C(0), |
5833 | 0 | UINT64_C(0), |
5834 | 0 | UINT64_C(0), |
5835 | 0 | UINT64_C(0), |
5836 | 0 | UINT64_C(0), |
5837 | 0 | UINT64_C(0), |
5838 | 0 | UINT64_C(0), |
5839 | 0 | UINT64_C(0), |
5840 | 0 | UINT64_C(0), |
5841 | 0 | UINT64_C(0), |
5842 | 0 | UINT64_C(0), |
5843 | 0 | UINT64_C(0), |
5844 | 0 | UINT64_C(0), |
5845 | 0 | UINT64_C(0), |
5846 | 0 | UINT64_C(0), |
5847 | 0 | UINT64_C(0), |
5848 | 0 | UINT64_C(0), |
5849 | 0 | UINT64_C(0), |
5850 | 0 | UINT64_C(0), |
5851 | 0 | UINT64_C(0), |
5852 | 0 | UINT64_C(0), |
5853 | 0 | UINT64_C(0), |
5854 | 0 | UINT64_C(0), |
5855 | 0 | UINT64_C(0), |
5856 | 0 | UINT64_C(0), |
5857 | 0 | UINT64_C(0), |
5858 | 0 | UINT64_C(0), |
5859 | 0 | UINT64_C(0), |
5860 | 0 | UINT64_C(0), |
5861 | 0 | UINT64_C(0), |
5862 | 0 | UINT64_C(0), |
5863 | 0 | UINT64_C(0), |
5864 | 0 | UINT64_C(0), |
5865 | 0 | UINT64_C(0), |
5866 | 0 | UINT64_C(0), |
5867 | 0 | UINT64_C(0), |
5868 | 0 | UINT64_C(0), |
5869 | 0 | UINT64_C(0), |
5870 | 0 | UINT64_C(0), |
5871 | 0 | UINT64_C(0), |
5872 | 0 | UINT64_C(0), |
5873 | 0 | UINT64_C(0), |
5874 | 0 | UINT64_C(0), |
5875 | 0 | UINT64_C(0), |
5876 | 0 | UINT64_C(0), |
5877 | 0 | UINT64_C(0), |
5878 | 0 | UINT64_C(0), |
5879 | 0 | UINT64_C(0), |
5880 | 0 | UINT64_C(0), |
5881 | 0 | UINT64_C(0), |
5882 | 0 | UINT64_C(0), |
5883 | 0 | UINT64_C(0), |
5884 | 0 | UINT64_C(0), |
5885 | 0 | UINT64_C(0), |
5886 | 0 | UINT64_C(0), |
5887 | 0 | UINT64_C(0), |
5888 | 0 | UINT64_C(0), |
5889 | 0 | UINT64_C(0), |
5890 | 0 | UINT64_C(0), |
5891 | 0 | UINT64_C(0), |
5892 | 0 | UINT64_C(0), |
5893 | 0 | UINT64_C(0), |
5894 | 0 | UINT64_C(0), |
5895 | 0 | UINT64_C(0), |
5896 | 0 | UINT64_C(0), |
5897 | 0 | UINT64_C(0), |
5898 | 0 | UINT64_C(0), |
5899 | 0 | UINT64_C(0), |
5900 | 0 | UINT64_C(0), |
5901 | 0 | UINT64_C(0), |
5902 | 0 | UINT64_C(0), |
5903 | 0 | UINT64_C(0), |
5904 | 0 | UINT64_C(0), |
5905 | 0 | UINT64_C(0), |
5906 | 0 | UINT64_C(0), |
5907 | 0 | UINT64_C(0), |
5908 | 0 | UINT64_C(0), |
5909 | 0 | UINT64_C(0), |
5910 | 0 | UINT64_C(0), |
5911 | 0 | UINT64_C(0), |
5912 | 0 | UINT64_C(0), |
5913 | 0 | UINT64_C(0), |
5914 | 0 | UINT64_C(0), |
5915 | 0 | UINT64_C(0), |
5916 | 0 | UINT64_C(0), |
5917 | 0 | UINT64_C(0), |
5918 | 0 | UINT64_C(0), |
5919 | 0 | UINT64_C(0), |
5920 | 0 | UINT64_C(0), |
5921 | 0 | UINT64_C(0), |
5922 | 0 | UINT64_C(0), |
5923 | 0 | UINT64_C(0), |
5924 | 0 | UINT64_C(0), |
5925 | 0 | UINT64_C(0), |
5926 | 0 | UINT64_C(0), |
5927 | 0 | UINT64_C(0), |
5928 | 0 | UINT64_C(0), |
5929 | 0 | UINT64_C(0), |
5930 | 0 | UINT64_C(0), |
5931 | 0 | UINT64_C(0), |
5932 | 0 | UINT64_C(0), |
5933 | 0 | UINT64_C(0), |
5934 | 0 | UINT64_C(0), |
5935 | 0 | UINT64_C(0), |
5936 | 0 | UINT64_C(0), |
5937 | 0 | UINT64_C(0), |
5938 | 0 | UINT64_C(0), |
5939 | 0 | UINT64_C(0), |
5940 | 0 | UINT64_C(0), |
5941 | 0 | UINT64_C(0), |
5942 | 0 | UINT64_C(0), |
5943 | 0 | UINT64_C(0), |
5944 | 0 | UINT64_C(0), |
5945 | 0 | UINT64_C(0), |
5946 | 0 | UINT64_C(0), |
5947 | 0 | UINT64_C(0), |
5948 | 0 | UINT64_C(0), |
5949 | 0 | UINT64_C(0), |
5950 | 0 | UINT64_C(0), |
5951 | 0 | UINT64_C(0), |
5952 | 0 | UINT64_C(0), |
5953 | 0 | UINT64_C(0), |
5954 | 0 | UINT64_C(0), |
5955 | 0 | UINT64_C(0), |
5956 | 0 | UINT64_C(0), |
5957 | 0 | UINT64_C(0), |
5958 | 0 | UINT64_C(0), |
5959 | 0 | UINT64_C(0), |
5960 | 0 | UINT64_C(0), |
5961 | 0 | UINT64_C(0), |
5962 | 0 | UINT64_C(0), |
5963 | 0 | UINT64_C(0), |
5964 | 0 | UINT64_C(0), |
5965 | 0 | UINT64_C(0), |
5966 | 0 | UINT64_C(0), |
5967 | 0 | UINT64_C(0), |
5968 | 0 | UINT64_C(0), |
5969 | 0 | UINT64_C(0), |
5970 | 0 | UINT64_C(0), |
5971 | 0 | UINT64_C(0), |
5972 | 0 | UINT64_C(0), |
5973 | 0 | UINT64_C(0), |
5974 | 0 | UINT64_C(0), |
5975 | 0 | UINT64_C(0), |
5976 | 0 | UINT64_C(0), |
5977 | 0 | UINT64_C(0), |
5978 | 0 | UINT64_C(0), |
5979 | 0 | UINT64_C(0), |
5980 | 0 | UINT64_C(0), |
5981 | 0 | UINT64_C(0), |
5982 | 0 | UINT64_C(0), |
5983 | 0 | UINT64_C(0), |
5984 | 0 | UINT64_C(0), |
5985 | 0 | UINT64_C(0), |
5986 | 0 | UINT64_C(0), |
5987 | 0 | UINT64_C(0), |
5988 | 0 | UINT64_C(0), |
5989 | 0 | UINT64_C(0), |
5990 | 0 | UINT64_C(0), |
5991 | 0 | UINT64_C(0), |
5992 | 0 | UINT64_C(0), |
5993 | 0 | UINT64_C(0), |
5994 | 0 | UINT64_C(0), |
5995 | 0 | UINT64_C(0), |
5996 | 0 | UINT64_C(0), |
5997 | 0 | UINT64_C(0), |
5998 | 0 | UINT64_C(0), |
5999 | 0 | UINT64_C(0), |
6000 | 0 | UINT64_C(0), |
6001 | 0 | UINT64_C(0), |
6002 | 0 | UINT64_C(0), |
6003 | 0 | UINT64_C(0), |
6004 | 0 | UINT64_C(0), |
6005 | 0 | UINT64_C(0), |
6006 | 0 | UINT64_C(0), |
6007 | 0 | UINT64_C(0), |
6008 | 0 | UINT64_C(0), |
6009 | 0 | UINT64_C(0), |
6010 | 0 | UINT64_C(0), |
6011 | 0 | UINT64_C(0), |
6012 | 0 | UINT64_C(0), |
6013 | 0 | UINT64_C(0), |
6014 | 0 | UINT64_C(0), |
6015 | 0 | UINT64_C(0), |
6016 | 0 | UINT64_C(0), |
6017 | 0 | UINT64_C(0), |
6018 | 0 | UINT64_C(0), |
6019 | 0 | UINT64_C(0), |
6020 | 0 | UINT64_C(0), |
6021 | 0 | UINT64_C(0), |
6022 | 0 | UINT64_C(0), |
6023 | 0 | UINT64_C(0), |
6024 | 0 | UINT64_C(0), |
6025 | 0 | UINT64_C(0), |
6026 | 0 | UINT64_C(0), |
6027 | 0 | UINT64_C(0), |
6028 | 0 | UINT64_C(0), |
6029 | 0 | UINT64_C(0), |
6030 | 0 | UINT64_C(0), |
6031 | 0 | UINT64_C(0), |
6032 | 0 | UINT64_C(0), |
6033 | 0 | UINT64_C(0), |
6034 | 0 | UINT64_C(0), |
6035 | 0 | UINT64_C(0), |
6036 | 0 | UINT64_C(0), |
6037 | 0 | UINT64_C(0), |
6038 | 0 | UINT64_C(0), |
6039 | 0 | UINT64_C(0), |
6040 | 0 | UINT64_C(0), |
6041 | 0 | UINT64_C(0), |
6042 | 0 | UINT64_C(0), |
6043 | 0 | UINT64_C(0), |
6044 | 0 | UINT64_C(0), |
6045 | 0 | UINT64_C(0), |
6046 | 0 | UINT64_C(0), |
6047 | 0 | UINT64_C(0), |
6048 | 0 | UINT64_C(0), |
6049 | 0 | UINT64_C(0), |
6050 | 0 | UINT64_C(0), |
6051 | 0 | UINT64_C(0), |
6052 | 0 | UINT64_C(0), |
6053 | 0 | UINT64_C(0), |
6054 | 0 | UINT64_C(0), |
6055 | 0 | UINT64_C(0), |
6056 | 0 | UINT64_C(0), |
6057 | 0 | UINT64_C(0), |
6058 | 0 | UINT64_C(0), |
6059 | 0 | UINT64_C(0), |
6060 | 0 | UINT64_C(0), |
6061 | 0 | UINT64_C(0), |
6062 | 0 | UINT64_C(0), |
6063 | 0 | UINT64_C(0), |
6064 | 0 | UINT64_C(0), |
6065 | 0 | UINT64_C(0), |
6066 | 0 | UINT64_C(0), |
6067 | 0 | UINT64_C(0), |
6068 | 0 | UINT64_C(0), |
6069 | 0 | UINT64_C(0), |
6070 | 0 | UINT64_C(0), |
6071 | 0 | UINT64_C(0), |
6072 | 0 | UINT64_C(0), |
6073 | 0 | UINT64_C(0), |
6074 | 0 | UINT64_C(0), |
6075 | 0 | UINT64_C(0), |
6076 | 0 | UINT64_C(0), |
6077 | 0 | UINT64_C(0), |
6078 | 0 | UINT64_C(0), |
6079 | 0 | UINT64_C(0), |
6080 | 0 | UINT64_C(0), |
6081 | 0 | UINT64_C(0), |
6082 | 0 | UINT64_C(0), |
6083 | 0 | UINT64_C(0), |
6084 | 0 | UINT64_C(0), |
6085 | 0 | UINT64_C(0), |
6086 | 0 | UINT64_C(0), |
6087 | 0 | UINT64_C(0), |
6088 | 0 | UINT64_C(0), |
6089 | 0 | UINT64_C(0), |
6090 | 0 | UINT64_C(0), |
6091 | 0 | UINT64_C(0), |
6092 | 0 | UINT64_C(0), |
6093 | 0 | UINT64_C(0), |
6094 | 0 | UINT64_C(0), |
6095 | 0 | UINT64_C(0), |
6096 | 0 | UINT64_C(0), |
6097 | 0 | UINT64_C(0), |
6098 | 0 | UINT64_C(0), |
6099 | 0 | UINT64_C(0), |
6100 | 0 | UINT64_C(0), |
6101 | 0 | UINT64_C(0), |
6102 | 0 | UINT64_C(0), |
6103 | 0 | UINT64_C(0), |
6104 | 0 | UINT64_C(0), |
6105 | 0 | UINT64_C(0), |
6106 | 0 | UINT64_C(0), |
6107 | 0 | UINT64_C(0), |
6108 | 0 | UINT64_C(0), |
6109 | 0 | UINT64_C(0), |
6110 | 0 | UINT64_C(0), |
6111 | 0 | UINT64_C(0), |
6112 | 0 | UINT64_C(0), |
6113 | 0 | UINT64_C(0), |
6114 | 0 | UINT64_C(0), |
6115 | 0 | UINT64_C(0), |
6116 | 0 | UINT64_C(0), |
6117 | 0 | UINT64_C(0), |
6118 | 0 | UINT64_C(0), |
6119 | 0 | UINT64_C(0), |
6120 | 0 | UINT64_C(0), |
6121 | 0 | UINT64_C(0), |
6122 | 0 | UINT64_C(0), |
6123 | 0 | UINT64_C(0), |
6124 | 0 | UINT64_C(0), |
6125 | 0 | UINT64_C(0), |
6126 | 0 | UINT64_C(0), |
6127 | 0 | UINT64_C(0), |
6128 | 0 | UINT64_C(0), |
6129 | 0 | UINT64_C(0), |
6130 | 0 | UINT64_C(0), |
6131 | 0 | UINT64_C(0), |
6132 | 0 | UINT64_C(0), |
6133 | 0 | UINT64_C(0), |
6134 | 0 | UINT64_C(0), |
6135 | 0 | UINT64_C(0), |
6136 | 0 | UINT64_C(0), |
6137 | 0 | UINT64_C(0), |
6138 | 0 | UINT64_C(0), |
6139 | 0 | UINT64_C(0), |
6140 | 0 | UINT64_C(0), |
6141 | 0 | UINT64_C(0), |
6142 | 0 | UINT64_C(0), |
6143 | 0 | UINT64_C(0), |
6144 | 0 | UINT64_C(0), |
6145 | 0 | UINT64_C(0), |
6146 | 0 | UINT64_C(0), |
6147 | 0 | UINT64_C(0), |
6148 | 0 | UINT64_C(0), |
6149 | 0 | UINT64_C(0), |
6150 | 0 | UINT64_C(0), |
6151 | 0 | UINT64_C(0), |
6152 | 0 | UINT64_C(0), |
6153 | 0 | UINT64_C(0), |
6154 | 0 | UINT64_C(0), |
6155 | 0 | UINT64_C(0), |
6156 | 0 | UINT64_C(0), |
6157 | 0 | UINT64_C(0), |
6158 | 0 | UINT64_C(0), |
6159 | 0 | UINT64_C(0), |
6160 | 0 | UINT64_C(0), |
6161 | 0 | UINT64_C(0), |
6162 | 0 | UINT64_C(0), |
6163 | 0 | UINT64_C(0), |
6164 | 0 | UINT64_C(0), |
6165 | 0 | UINT64_C(0), |
6166 | 0 | UINT64_C(0), |
6167 | 0 | UINT64_C(0), |
6168 | 0 | UINT64_C(0), |
6169 | 0 | UINT64_C(0), |
6170 | 0 | UINT64_C(0), |
6171 | 0 | UINT64_C(0), |
6172 | 0 | UINT64_C(0), |
6173 | 0 | UINT64_C(0), |
6174 | 0 | UINT64_C(0), |
6175 | 0 | UINT64_C(0), |
6176 | 0 | UINT64_C(0), |
6177 | 0 | UINT64_C(0), |
6178 | 0 | UINT64_C(0), |
6179 | 0 | UINT64_C(0), |
6180 | 0 | UINT64_C(0), |
6181 | 0 | UINT64_C(0), |
6182 | 0 | UINT64_C(0), |
6183 | 0 | UINT64_C(0), |
6184 | 0 | UINT64_C(0), |
6185 | 0 | UINT64_C(0), |
6186 | 0 | UINT64_C(0), |
6187 | 0 | UINT64_C(0), |
6188 | 0 | UINT64_C(0), |
6189 | 0 | UINT64_C(0), |
6190 | 0 | UINT64_C(0), |
6191 | 0 | UINT64_C(0), |
6192 | 0 | UINT64_C(0), |
6193 | 0 | UINT64_C(0), |
6194 | 0 | UINT64_C(0), |
6195 | 0 | UINT64_C(0), |
6196 | 0 | UINT64_C(0), |
6197 | 0 | UINT64_C(0), |
6198 | 0 | UINT64_C(0), |
6199 | 0 | UINT64_C(0), |
6200 | 0 | UINT64_C(0), |
6201 | 0 | UINT64_C(0), |
6202 | 0 | UINT64_C(0), |
6203 | 0 | UINT64_C(0), |
6204 | 0 | UINT64_C(0), |
6205 | 0 | UINT64_C(0), |
6206 | 0 | UINT64_C(0), |
6207 | 0 | UINT64_C(0), |
6208 | 0 | UINT64_C(0), |
6209 | 0 | UINT64_C(0), |
6210 | 0 | UINT64_C(0), |
6211 | 0 | UINT64_C(0), |
6212 | 0 | UINT64_C(0), |
6213 | 0 | UINT64_C(0), |
6214 | 0 | UINT64_C(0), |
6215 | 0 | UINT64_C(0), |
6216 | 0 | UINT64_C(0), |
6217 | 0 | UINT64_C(0), |
6218 | 0 | UINT64_C(0), |
6219 | 0 | UINT64_C(0), |
6220 | 0 | UINT64_C(0), |
6221 | 0 | UINT64_C(0), |
6222 | 0 | UINT64_C(0), |
6223 | 0 | UINT64_C(0), |
6224 | 0 | UINT64_C(0), |
6225 | 0 | UINT64_C(0), |
6226 | 0 | UINT64_C(0), |
6227 | 0 | UINT64_C(0), |
6228 | 0 | UINT64_C(0), |
6229 | 0 | UINT64_C(0), |
6230 | 0 | UINT64_C(0), |
6231 | 0 | UINT64_C(0), |
6232 | 0 | UINT64_C(0), |
6233 | 0 | UINT64_C(0), |
6234 | 0 | UINT64_C(0), |
6235 | 0 | UINT64_C(0), |
6236 | 0 | UINT64_C(0), |
6237 | 0 | UINT64_C(0), |
6238 | 0 | UINT64_C(0), |
6239 | 0 | UINT64_C(0), |
6240 | 0 | UINT64_C(0), |
6241 | 0 | UINT64_C(0), |
6242 | 0 | UINT64_C(0), |
6243 | 0 | UINT64_C(0), |
6244 | 0 | UINT64_C(0), |
6245 | 0 | UINT64_C(0), |
6246 | 0 | UINT64_C(0), |
6247 | 0 | UINT64_C(0), |
6248 | 0 | UINT64_C(0), |
6249 | 0 | UINT64_C(0), |
6250 | 0 | UINT64_C(0), |
6251 | 0 | UINT64_C(0), |
6252 | 0 | UINT64_C(0), |
6253 | 0 | UINT64_C(0), |
6254 | 0 | UINT64_C(0), |
6255 | 0 | UINT64_C(0), |
6256 | 0 | UINT64_C(0), |
6257 | 0 | UINT64_C(0), |
6258 | 0 | UINT64_C(0), |
6259 | 0 | UINT64_C(0), |
6260 | 0 | UINT64_C(0), |
6261 | 0 | UINT64_C(0), |
6262 | 0 | UINT64_C(0), |
6263 | 0 | UINT64_C(0), |
6264 | 0 | UINT64_C(0), |
6265 | 0 | UINT64_C(0), |
6266 | 0 | UINT64_C(0), |
6267 | 0 | UINT64_C(0), |
6268 | 0 | UINT64_C(0), |
6269 | 0 | UINT64_C(0), |
6270 | 0 | UINT64_C(0), |
6271 | 0 | UINT64_C(0), |
6272 | 0 | UINT64_C(0), |
6273 | 0 | UINT64_C(0), |
6274 | 0 | UINT64_C(0), |
6275 | 0 | UINT64_C(0), |
6276 | 0 | UINT64_C(0), |
6277 | 0 | UINT64_C(0), |
6278 | 0 | UINT64_C(0), |
6279 | 0 | UINT64_C(0), |
6280 | 0 | UINT64_C(0), |
6281 | 0 | UINT64_C(0), |
6282 | 0 | UINT64_C(0), |
6283 | 0 | UINT64_C(0), |
6284 | 0 | UINT64_C(0), |
6285 | 0 | UINT64_C(0), |
6286 | 0 | UINT64_C(0), |
6287 | 0 | UINT64_C(0), |
6288 | 0 | UINT64_C(0), |
6289 | 0 | UINT64_C(0), |
6290 | 0 | UINT64_C(0), |
6291 | 0 | UINT64_C(0), |
6292 | 0 | UINT64_C(0), |
6293 | 0 | UINT64_C(0), |
6294 | 0 | UINT64_C(0), |
6295 | 0 | UINT64_C(0), |
6296 | 0 | UINT64_C(0), |
6297 | 0 | UINT64_C(0), |
6298 | 0 | UINT64_C(0), |
6299 | 0 | UINT64_C(0), |
6300 | 0 | UINT64_C(0), |
6301 | 0 | UINT64_C(0), |
6302 | 0 | UINT64_C(0), |
6303 | 0 | UINT64_C(0), |
6304 | 0 | UINT64_C(0), |
6305 | 0 | UINT64_C(0), |
6306 | 0 | UINT64_C(0), |
6307 | 0 | UINT64_C(0), |
6308 | 0 | UINT64_C(0), |
6309 | 0 | UINT64_C(0), |
6310 | 0 | UINT64_C(0), |
6311 | 0 | UINT64_C(0), |
6312 | 0 | UINT64_C(0), |
6313 | 0 | UINT64_C(0), |
6314 | 0 | UINT64_C(0), |
6315 | 0 | UINT64_C(0), |
6316 | 0 | UINT64_C(0), |
6317 | 0 | UINT64_C(0), |
6318 | 0 | UINT64_C(0), |
6319 | 0 | UINT64_C(0), |
6320 | 0 | UINT64_C(0), |
6321 | 0 | UINT64_C(0), |
6322 | 0 | UINT64_C(0), |
6323 | 0 | UINT64_C(0), |
6324 | 0 | UINT64_C(0), |
6325 | 0 | UINT64_C(0), |
6326 | 0 | UINT64_C(0), |
6327 | 0 | UINT64_C(0), |
6328 | 0 | UINT64_C(0), |
6329 | 0 | UINT64_C(0), |
6330 | 0 | UINT64_C(0), |
6331 | 0 | UINT64_C(0), |
6332 | 0 | UINT64_C(0), |
6333 | 0 | UINT64_C(0), |
6334 | 0 | UINT64_C(0), |
6335 | 0 | UINT64_C(0), |
6336 | 0 | UINT64_C(0), |
6337 | 0 | UINT64_C(0), |
6338 | 0 | UINT64_C(0), |
6339 | 0 | UINT64_C(0), |
6340 | 0 | UINT64_C(0), |
6341 | 0 | UINT64_C(0), |
6342 | 0 | UINT64_C(0), |
6343 | 0 | UINT64_C(0), |
6344 | 0 | UINT64_C(0), |
6345 | 0 | UINT64_C(0), |
6346 | 0 | UINT64_C(0), |
6347 | 0 | UINT64_C(0), |
6348 | 0 | UINT64_C(0), |
6349 | 0 | UINT64_C(0), |
6350 | 0 | UINT64_C(0), |
6351 | 0 | UINT64_C(0), |
6352 | 0 | UINT64_C(0), |
6353 | 0 | UINT64_C(0), |
6354 | 0 | UINT64_C(0), |
6355 | 0 | UINT64_C(0), |
6356 | 0 | UINT64_C(0), |
6357 | 0 | UINT64_C(0), |
6358 | 0 | UINT64_C(0), |
6359 | 0 | UINT64_C(0), |
6360 | 0 | UINT64_C(0), |
6361 | 0 | UINT64_C(0), |
6362 | 0 | UINT64_C(0), |
6363 | 0 | UINT64_C(0), |
6364 | 0 | UINT64_C(0), |
6365 | 0 | UINT64_C(0), |
6366 | 0 | UINT64_C(0), |
6367 | 0 | UINT64_C(0), |
6368 | 0 | UINT64_C(0), |
6369 | 0 | UINT64_C(0), |
6370 | 0 | UINT64_C(0), |
6371 | 0 | UINT64_C(0), |
6372 | 0 | UINT64_C(0), |
6373 | 0 | UINT64_C(0), |
6374 | 0 | UINT64_C(0), |
6375 | 0 | UINT64_C(0), |
6376 | 0 | UINT64_C(0), |
6377 | 0 | UINT64_C(0), |
6378 | 0 | UINT64_C(0), |
6379 | 0 | UINT64_C(0), |
6380 | 0 | UINT64_C(0), |
6381 | 0 | UINT64_C(0), |
6382 | 0 | UINT64_C(0), |
6383 | 0 | UINT64_C(0), |
6384 | 0 | UINT64_C(0), |
6385 | 0 | UINT64_C(0), |
6386 | 0 | UINT64_C(0), |
6387 | 0 | UINT64_C(0), |
6388 | 0 | UINT64_C(0), |
6389 | 0 | UINT64_C(0), |
6390 | 0 | UINT64_C(0), |
6391 | 0 | UINT64_C(0), |
6392 | 0 | UINT64_C(0), |
6393 | 0 | UINT64_C(0), |
6394 | 0 | UINT64_C(0), |
6395 | 0 | UINT64_C(0), |
6396 | 0 | UINT64_C(0), |
6397 | 0 | UINT64_C(0), |
6398 | 0 | UINT64_C(0), |
6399 | 0 | UINT64_C(0), |
6400 | 0 | UINT64_C(0), |
6401 | 0 | UINT64_C(0), |
6402 | 0 | UINT64_C(0), |
6403 | 0 | UINT64_C(0), |
6404 | 0 | UINT64_C(0), |
6405 | 0 | UINT64_C(0), |
6406 | 0 | UINT64_C(0), |
6407 | 0 | UINT64_C(0), |
6408 | 0 | UINT64_C(0), |
6409 | 0 | UINT64_C(0), |
6410 | 0 | UINT64_C(0), |
6411 | 0 | UINT64_C(0), |
6412 | 0 | UINT64_C(0), |
6413 | 0 | UINT64_C(0), |
6414 | 0 | UINT64_C(0), |
6415 | 0 | UINT64_C(0), |
6416 | 0 | UINT64_C(0), |
6417 | 0 | UINT64_C(0), |
6418 | 0 | UINT64_C(0), |
6419 | 0 | UINT64_C(0), |
6420 | 0 | UINT64_C(0), |
6421 | 0 | UINT64_C(0), |
6422 | 0 | UINT64_C(0), |
6423 | 0 | UINT64_C(0), |
6424 | 0 | UINT64_C(0), |
6425 | 0 | UINT64_C(0), |
6426 | 0 | UINT64_C(0), |
6427 | 0 | UINT64_C(0), |
6428 | 0 | UINT64_C(0), |
6429 | 0 | UINT64_C(0), |
6430 | 0 | UINT64_C(0), |
6431 | 0 | UINT64_C(0), |
6432 | 0 | UINT64_C(0), |
6433 | 0 | UINT64_C(0), |
6434 | 0 | UINT64_C(0), |
6435 | 0 | UINT64_C(0), |
6436 | 0 | UINT64_C(0), |
6437 | 0 | UINT64_C(0), |
6438 | 0 | UINT64_C(0), |
6439 | 0 | UINT64_C(0), |
6440 | 0 | UINT64_C(0), |
6441 | 0 | UINT64_C(0), |
6442 | 0 | UINT64_C(0), |
6443 | 0 | UINT64_C(0), |
6444 | 0 | UINT64_C(0), |
6445 | 0 | UINT64_C(0), |
6446 | 0 | UINT64_C(0), |
6447 | 0 | UINT64_C(0), |
6448 | 0 | UINT64_C(0), |
6449 | 0 | UINT64_C(0), |
6450 | 0 | UINT64_C(0), |
6451 | 0 | UINT64_C(0), |
6452 | 0 | UINT64_C(0), |
6453 | 0 | UINT64_C(0), |
6454 | 0 | UINT64_C(0), |
6455 | 0 | UINT64_C(0), |
6456 | 0 | UINT64_C(0), |
6457 | 0 | UINT64_C(0), |
6458 | 0 | UINT64_C(0), |
6459 | 0 | UINT64_C(0), |
6460 | 0 | UINT64_C(0), |
6461 | 0 | UINT64_C(0), |
6462 | 0 | UINT64_C(0), |
6463 | 0 | UINT64_C(0), |
6464 | 0 | UINT64_C(0), |
6465 | 0 | UINT64_C(0), |
6466 | 0 | UINT64_C(0), |
6467 | 0 | UINT64_C(0), |
6468 | 0 | UINT64_C(0), |
6469 | 0 | UINT64_C(0), |
6470 | 0 | UINT64_C(0), |
6471 | 0 | UINT64_C(0), |
6472 | 0 | UINT64_C(0), |
6473 | 0 | UINT64_C(0), |
6474 | 0 | UINT64_C(0), |
6475 | 0 | UINT64_C(0), |
6476 | 0 | UINT64_C(0), |
6477 | 0 | UINT64_C(0), |
6478 | 0 | UINT64_C(0), |
6479 | 0 | UINT64_C(0), |
6480 | 0 | UINT64_C(0), |
6481 | 0 | UINT64_C(0), |
6482 | 0 | UINT64_C(0), |
6483 | 0 | UINT64_C(0), |
6484 | 0 | UINT64_C(0), |
6485 | 0 | UINT64_C(0), |
6486 | 0 | UINT64_C(0), |
6487 | 0 | UINT64_C(0), |
6488 | 0 | UINT64_C(0), |
6489 | 0 | UINT64_C(0), |
6490 | 0 | UINT64_C(0), |
6491 | 0 | UINT64_C(0), |
6492 | 0 | UINT64_C(0), |
6493 | 0 | UINT64_C(0), |
6494 | 0 | UINT64_C(0), |
6495 | 0 | UINT64_C(0), |
6496 | 0 | UINT64_C(0), |
6497 | 0 | UINT64_C(0), |
6498 | 0 | UINT64_C(0), |
6499 | 0 | UINT64_C(0), |
6500 | 0 | UINT64_C(0), |
6501 | 0 | UINT64_C(0), |
6502 | 0 | UINT64_C(0), |
6503 | 0 | UINT64_C(0), |
6504 | 0 | UINT64_C(0), |
6505 | 0 | UINT64_C(0), |
6506 | 0 | UINT64_C(0), |
6507 | 0 | UINT64_C(0), |
6508 | 0 | UINT64_C(0), |
6509 | 0 | UINT64_C(0), |
6510 | 0 | UINT64_C(0), |
6511 | 0 | UINT64_C(0), |
6512 | 0 | UINT64_C(0), |
6513 | 0 | UINT64_C(0), |
6514 | 0 | UINT64_C(0), |
6515 | 0 | UINT64_C(0), |
6516 | 0 | UINT64_C(0), |
6517 | 0 | UINT64_C(0), |
6518 | 0 | UINT64_C(0), |
6519 | 0 | UINT64_C(0), |
6520 | 0 | UINT64_C(0), |
6521 | 0 | UINT64_C(0), |
6522 | 0 | UINT64_C(0), |
6523 | 0 | UINT64_C(0), |
6524 | 0 | UINT64_C(0), |
6525 | 0 | UINT64_C(0), |
6526 | 0 | UINT64_C(0), |
6527 | 0 | UINT64_C(0), |
6528 | 0 | UINT64_C(0), |
6529 | 0 | UINT64_C(0), |
6530 | 0 | UINT64_C(0), |
6531 | 0 | UINT64_C(0), |
6532 | 0 | UINT64_C(0), |
6533 | 0 | UINT64_C(0), |
6534 | 0 | UINT64_C(0), |
6535 | 0 | UINT64_C(0), |
6536 | 0 | UINT64_C(0), |
6537 | 0 | UINT64_C(0), |
6538 | 0 | UINT64_C(0), |
6539 | 0 | UINT64_C(0), |
6540 | 0 | UINT64_C(0), |
6541 | 0 | UINT64_C(0), |
6542 | 0 | UINT64_C(0), |
6543 | 0 | UINT64_C(0), |
6544 | 0 | UINT64_C(0), |
6545 | 0 | UINT64_C(0), |
6546 | 0 | UINT64_C(0), |
6547 | 0 | UINT64_C(0), |
6548 | 0 | UINT64_C(0), |
6549 | 0 | UINT64_C(0), |
6550 | 0 | UINT64_C(0), |
6551 | 0 | UINT64_C(0), |
6552 | 0 | UINT64_C(0), |
6553 | 0 | UINT64_C(0), |
6554 | 0 | UINT64_C(0), |
6555 | 0 | UINT64_C(0), |
6556 | 0 | UINT64_C(0), |
6557 | 0 | UINT64_C(0), |
6558 | 0 | UINT64_C(0), |
6559 | 0 | UINT64_C(0), |
6560 | 0 | UINT64_C(0), |
6561 | 0 | UINT64_C(0), |
6562 | 0 | UINT64_C(0), |
6563 | 0 | UINT64_C(0), |
6564 | 0 | UINT64_C(0), |
6565 | 0 | UINT64_C(0), |
6566 | 0 | UINT64_C(0), |
6567 | 0 | UINT64_C(0), |
6568 | 0 | UINT64_C(0), |
6569 | 0 | UINT64_C(0), |
6570 | 0 | UINT64_C(0), |
6571 | 0 | UINT64_C(0), |
6572 | 0 | UINT64_C(0), |
6573 | 0 | UINT64_C(0), |
6574 | 0 | UINT64_C(0), |
6575 | 0 | UINT64_C(0), |
6576 | 0 | UINT64_C(0), |
6577 | 0 | UINT64_C(0), |
6578 | 0 | UINT64_C(0), |
6579 | 0 | UINT64_C(0), |
6580 | 0 | UINT64_C(0), |
6581 | 0 | UINT64_C(0), |
6582 | 0 | UINT64_C(0), |
6583 | 0 | UINT64_C(0), |
6584 | 0 | UINT64_C(0), |
6585 | 0 | UINT64_C(0), |
6586 | 0 | UINT64_C(0), |
6587 | 0 | UINT64_C(0), |
6588 | 0 | UINT64_C(0), |
6589 | 0 | UINT64_C(0), |
6590 | 0 | UINT64_C(0), |
6591 | 0 | UINT64_C(0), |
6592 | 0 | UINT64_C(0), |
6593 | 0 | UINT64_C(0), |
6594 | 0 | UINT64_C(0), |
6595 | 0 | UINT64_C(0), |
6596 | 0 | UINT64_C(0), |
6597 | 0 | UINT64_C(0), |
6598 | 0 | UINT64_C(0), |
6599 | 0 | UINT64_C(0), |
6600 | 0 | UINT64_C(0), |
6601 | 0 | UINT64_C(0), |
6602 | 0 | UINT64_C(0), |
6603 | 0 | UINT64_C(0), |
6604 | 0 | UINT64_C(0), |
6605 | 0 | UINT64_C(0), |
6606 | 0 | UINT64_C(0), |
6607 | 0 | UINT64_C(0), |
6608 | 0 | UINT64_C(0), |
6609 | 0 | UINT64_C(0), |
6610 | 0 | UINT64_C(0), |
6611 | 0 | UINT64_C(0), |
6612 | 0 | UINT64_C(0), |
6613 | 0 | UINT64_C(0), |
6614 | 0 | UINT64_C(0), |
6615 | 0 | UINT64_C(0), |
6616 | 0 | UINT64_C(0), |
6617 | 0 | UINT64_C(0), |
6618 | 0 | UINT64_C(0), |
6619 | 0 | UINT64_C(0), |
6620 | 0 | UINT64_C(0), |
6621 | 0 | UINT64_C(0), |
6622 | 0 | UINT64_C(0), |
6623 | 0 | UINT64_C(0), |
6624 | 0 | UINT64_C(0), |
6625 | 0 | UINT64_C(0), |
6626 | 0 | UINT64_C(0), |
6627 | 0 | UINT64_C(0), |
6628 | 0 | UINT64_C(0), |
6629 | 0 | UINT64_C(0), |
6630 | 0 | UINT64_C(0), |
6631 | 0 | UINT64_C(0), |
6632 | 0 | UINT64_C(0), |
6633 | 0 | UINT64_C(0), |
6634 | 0 | UINT64_C(0), |
6635 | 0 | UINT64_C(0), |
6636 | 0 | UINT64_C(0), |
6637 | 0 | UINT64_C(0), |
6638 | 0 | UINT64_C(0), |
6639 | 0 | UINT64_C(0), |
6640 | 0 | UINT64_C(0), |
6641 | 0 | UINT64_C(0), |
6642 | 0 | UINT64_C(0), |
6643 | 0 | UINT64_C(0), |
6644 | 0 | UINT64_C(0), |
6645 | 0 | UINT64_C(0), |
6646 | 0 | UINT64_C(0), |
6647 | 0 | UINT64_C(0), |
6648 | 0 | UINT64_C(0), |
6649 | 0 | UINT64_C(0), |
6650 | 0 | UINT64_C(0), |
6651 | 0 | UINT64_C(0), |
6652 | 0 | UINT64_C(0), |
6653 | 0 | UINT64_C(0), |
6654 | 0 | UINT64_C(0), |
6655 | 0 | UINT64_C(0), |
6656 | 0 | UINT64_C(0), |
6657 | 0 | UINT64_C(0), |
6658 | 0 | UINT64_C(0), |
6659 | 0 | UINT64_C(0), |
6660 | 0 | UINT64_C(0), |
6661 | 0 | UINT64_C(0), |
6662 | 0 | UINT64_C(0), |
6663 | 0 | UINT64_C(0), |
6664 | 0 | UINT64_C(0), |
6665 | 0 | UINT64_C(0), |
6666 | 0 | UINT64_C(0), |
6667 | 0 | UINT64_C(0), |
6668 | 0 | UINT64_C(0), |
6669 | 0 | UINT64_C(0), |
6670 | 0 | UINT64_C(0), |
6671 | 0 | UINT64_C(0), |
6672 | 0 | UINT64_C(0), |
6673 | 0 | UINT64_C(0), |
6674 | 0 | UINT64_C(0), |
6675 | 0 | UINT64_C(0), |
6676 | 0 | UINT64_C(0), |
6677 | 0 | UINT64_C(0), |
6678 | 0 | UINT64_C(0), |
6679 | 0 | UINT64_C(0), |
6680 | 0 | UINT64_C(0), |
6681 | 0 | UINT64_C(0), |
6682 | 0 | UINT64_C(0), |
6683 | 0 | UINT64_C(0), |
6684 | 0 | UINT64_C(0), |
6685 | 0 | UINT64_C(0), |
6686 | 0 | UINT64_C(0), |
6687 | 0 | UINT64_C(0), |
6688 | 0 | UINT64_C(0), |
6689 | 0 | UINT64_C(0), |
6690 | 0 | UINT64_C(0), |
6691 | 0 | UINT64_C(0), |
6692 | 0 | UINT64_C(0), |
6693 | 0 | UINT64_C(0), |
6694 | 0 | UINT64_C(0), |
6695 | 0 | UINT64_C(0), |
6696 | 0 | UINT64_C(0), |
6697 | 0 | UINT64_C(0), |
6698 | 0 | UINT64_C(0), |
6699 | 0 | UINT64_C(0), |
6700 | 0 | UINT64_C(0), |
6701 | 0 | UINT64_C(0), |
6702 | 0 | UINT64_C(0), |
6703 | 0 | UINT64_C(0), |
6704 | 0 | UINT64_C(0), |
6705 | 0 | UINT64_C(0), |
6706 | 0 | UINT64_C(0), |
6707 | 0 | UINT64_C(0), |
6708 | 0 | UINT64_C(0), |
6709 | 0 | UINT64_C(0), |
6710 | 0 | UINT64_C(0), |
6711 | 0 | UINT64_C(0), |
6712 | 0 | UINT64_C(0), |
6713 | 0 | UINT64_C(0), |
6714 | 0 | UINT64_C(0), |
6715 | 0 | UINT64_C(0), |
6716 | 0 | UINT64_C(0), |
6717 | 0 | UINT64_C(0), |
6718 | 0 | UINT64_C(0), |
6719 | 0 | UINT64_C(0), |
6720 | 0 | UINT64_C(0), |
6721 | 0 | UINT64_C(0), |
6722 | 0 | UINT64_C(0), |
6723 | 0 | UINT64_C(0), |
6724 | 0 | UINT64_C(0), |
6725 | 0 | UINT64_C(0), |
6726 | 0 | UINT64_C(0), |
6727 | 0 | UINT64_C(0), |
6728 | 0 | UINT64_C(0), |
6729 | 0 | UINT64_C(0), |
6730 | 0 | UINT64_C(0), |
6731 | 0 | UINT64_C(0), |
6732 | 0 | UINT64_C(0), |
6733 | 0 | UINT64_C(0), |
6734 | 0 | UINT64_C(0), |
6735 | 0 | UINT64_C(0), |
6736 | 0 | UINT64_C(0), |
6737 | 0 | UINT64_C(0), |
6738 | 0 | UINT64_C(0), |
6739 | 0 | UINT64_C(0), |
6740 | 0 | UINT64_C(0), |
6741 | 0 | UINT64_C(0), |
6742 | 0 | UINT64_C(0), |
6743 | 0 | UINT64_C(0), |
6744 | 0 | UINT64_C(0), |
6745 | 0 | UINT64_C(0), |
6746 | 0 | UINT64_C(0), |
6747 | 0 | UINT64_C(0), |
6748 | 0 | UINT64_C(0), |
6749 | 0 | UINT64_C(0), |
6750 | 0 | UINT64_C(0), |
6751 | 0 | UINT64_C(0), |
6752 | 0 | UINT64_C(0), |
6753 | 0 | UINT64_C(0), |
6754 | 0 | UINT64_C(0), |
6755 | 0 | UINT64_C(0), |
6756 | 0 | UINT64_C(0), |
6757 | 0 | UINT64_C(0), |
6758 | 0 | UINT64_C(0), |
6759 | 0 | UINT64_C(0), |
6760 | 0 | UINT64_C(0), |
6761 | 0 | UINT64_C(0), |
6762 | 0 | UINT64_C(0), |
6763 | 0 | UINT64_C(0), |
6764 | 0 | UINT64_C(0), |
6765 | 0 | UINT64_C(0), |
6766 | 0 | UINT64_C(0), |
6767 | 0 | UINT64_C(0), |
6768 | 0 | UINT64_C(0), |
6769 | 0 | UINT64_C(0), |
6770 | 0 | UINT64_C(0), |
6771 | 0 | UINT64_C(0), |
6772 | 0 | UINT64_C(0), |
6773 | 0 | UINT64_C(0), |
6774 | 0 | UINT64_C(0), |
6775 | 0 | UINT64_C(0), |
6776 | 0 | UINT64_C(0), |
6777 | 0 | UINT64_C(0), |
6778 | 0 | UINT64_C(0), |
6779 | 0 | UINT64_C(0), |
6780 | 0 | UINT64_C(0), |
6781 | 0 | UINT64_C(0), |
6782 | 0 | UINT64_C(0), |
6783 | 0 | UINT64_C(0), |
6784 | 0 | UINT64_C(0), |
6785 | 0 | UINT64_C(0), |
6786 | 0 | UINT64_C(0), |
6787 | 0 | UINT64_C(0), |
6788 | 0 | UINT64_C(0), |
6789 | 0 | UINT64_C(0), |
6790 | 0 | UINT64_C(0), |
6791 | 0 | UINT64_C(0), |
6792 | 0 | UINT64_C(0), |
6793 | 0 | UINT64_C(0), |
6794 | 0 | UINT64_C(0), |
6795 | 0 | UINT64_C(0), |
6796 | 0 | UINT64_C(0), |
6797 | 0 | UINT64_C(0), |
6798 | 0 | UINT64_C(0), |
6799 | 0 | UINT64_C(0), |
6800 | 0 | UINT64_C(0), |
6801 | 0 | UINT64_C(0), |
6802 | 0 | UINT64_C(0), |
6803 | 0 | UINT64_C(0), |
6804 | 0 | UINT64_C(0), |
6805 | 0 | UINT64_C(0), |
6806 | 0 | UINT64_C(0), |
6807 | 0 | UINT64_C(0), |
6808 | 0 | UINT64_C(0), |
6809 | 0 | UINT64_C(0), |
6810 | 0 | UINT64_C(0), |
6811 | 0 | UINT64_C(0), |
6812 | 0 | UINT64_C(0), |
6813 | 0 | UINT64_C(0), |
6814 | 0 | UINT64_C(0), |
6815 | 0 | UINT64_C(0), |
6816 | 0 | UINT64_C(0), |
6817 | 0 | UINT64_C(0), |
6818 | 0 | UINT64_C(0), |
6819 | 0 | UINT64_C(0), |
6820 | 0 | UINT64_C(0), |
6821 | 0 | UINT64_C(0), |
6822 | 0 | UINT64_C(0), |
6823 | 0 | UINT64_C(0), |
6824 | 0 | UINT64_C(0), |
6825 | 0 | UINT64_C(0), |
6826 | 0 | UINT64_C(0), |
6827 | 0 | UINT64_C(0), |
6828 | 0 | UINT64_C(0), |
6829 | 0 | UINT64_C(0), |
6830 | 0 | UINT64_C(0), |
6831 | 0 | UINT64_C(0), |
6832 | 0 | UINT64_C(0), |
6833 | 0 | UINT64_C(0), |
6834 | 0 | UINT64_C(0), |
6835 | 0 | UINT64_C(0), |
6836 | 0 | UINT64_C(0), |
6837 | 0 | UINT64_C(0), |
6838 | 0 | UINT64_C(0), |
6839 | 0 | UINT64_C(0), |
6840 | 0 | UINT64_C(0), |
6841 | 0 | UINT64_C(0), |
6842 | 0 | UINT64_C(0), |
6843 | 0 | UINT64_C(0), |
6844 | 0 | UINT64_C(0), |
6845 | 0 | UINT64_C(0), |
6846 | 0 | UINT64_C(0), |
6847 | 0 | UINT64_C(0), |
6848 | 0 | UINT64_C(0), |
6849 | 0 | UINT64_C(0), |
6850 | 0 | UINT64_C(0), |
6851 | 0 | UINT64_C(0), |
6852 | 0 | UINT64_C(0), |
6853 | 0 | UINT64_C(0), |
6854 | 0 | UINT64_C(0), |
6855 | 0 | UINT64_C(0), |
6856 | 0 | UINT64_C(0), |
6857 | 0 | UINT64_C(0), |
6858 | 0 | UINT64_C(0), |
6859 | 0 | UINT64_C(0), |
6860 | 0 | UINT64_C(0), |
6861 | 0 | UINT64_C(0), |
6862 | 0 | UINT64_C(0), |
6863 | 0 | UINT64_C(0), |
6864 | 0 | UINT64_C(0), |
6865 | 0 | UINT64_C(0), |
6866 | 0 | UINT64_C(0), |
6867 | 0 | UINT64_C(0), |
6868 | 0 | UINT64_C(0), |
6869 | 0 | UINT64_C(0), |
6870 | 0 | UINT64_C(0), |
6871 | 0 | UINT64_C(0), |
6872 | 0 | UINT64_C(0), |
6873 | 0 | UINT64_C(0), |
6874 | 0 | UINT64_C(0), |
6875 | 0 | UINT64_C(0), |
6876 | 0 | UINT64_C(0), |
6877 | 0 | UINT64_C(0), |
6878 | 0 | UINT64_C(0), |
6879 | 0 | UINT64_C(0), |
6880 | 0 | UINT64_C(0), |
6881 | 0 | UINT64_C(0), |
6882 | 0 | UINT64_C(0), |
6883 | 0 | UINT64_C(0), |
6884 | 0 | UINT64_C(0), |
6885 | 0 | UINT64_C(0), |
6886 | 0 | UINT64_C(0), |
6887 | 0 | UINT64_C(0), |
6888 | 0 | UINT64_C(0), |
6889 | 0 | UINT64_C(0), |
6890 | 0 | UINT64_C(0), |
6891 | 0 | UINT64_C(0), |
6892 | 0 | UINT64_C(0), |
6893 | 0 | UINT64_C(0), |
6894 | 0 | UINT64_C(0), |
6895 | 0 | UINT64_C(0), |
6896 | 0 | UINT64_C(0), |
6897 | 0 | UINT64_C(0), |
6898 | 0 | UINT64_C(0), |
6899 | 0 | UINT64_C(0), |
6900 | 0 | UINT64_C(0), |
6901 | 0 | UINT64_C(0), |
6902 | 0 | UINT64_C(0), |
6903 | 0 | UINT64_C(0), |
6904 | 0 | UINT64_C(0), |
6905 | 0 | UINT64_C(0), |
6906 | 0 | UINT64_C(0), |
6907 | 0 | UINT64_C(0), |
6908 | 0 | UINT64_C(0), |
6909 | 0 | UINT64_C(0), |
6910 | 0 | UINT64_C(0), |
6911 | 0 | UINT64_C(0), |
6912 | 0 | UINT64_C(0), |
6913 | 0 | UINT64_C(0), |
6914 | 0 | UINT64_C(0), |
6915 | 0 | UINT64_C(0), |
6916 | 0 | UINT64_C(0), |
6917 | 0 | UINT64_C(0), |
6918 | 0 | UINT64_C(0), |
6919 | 0 | UINT64_C(0), |
6920 | 0 | UINT64_C(0), |
6921 | 0 | UINT64_C(0), |
6922 | 0 | UINT64_C(0), |
6923 | 0 | UINT64_C(0), |
6924 | 0 | UINT64_C(0), |
6925 | 0 | UINT64_C(0), |
6926 | 0 | UINT64_C(0), |
6927 | 0 | UINT64_C(0), |
6928 | 0 | UINT64_C(0), |
6929 | 0 | UINT64_C(0), |
6930 | 0 | UINT64_C(0), |
6931 | 0 | UINT64_C(0), |
6932 | 0 | UINT64_C(0), |
6933 | 0 | UINT64_C(0), |
6934 | 0 | UINT64_C(0), |
6935 | 0 | UINT64_C(0), |
6936 | 0 | UINT64_C(0), |
6937 | 0 | UINT64_C(0), |
6938 | 0 | UINT64_C(0), |
6939 | 0 | UINT64_C(0), |
6940 | 0 | UINT64_C(0), |
6941 | 0 | UINT64_C(0), |
6942 | 0 | UINT64_C(0), |
6943 | 0 | UINT64_C(0), |
6944 | 0 | UINT64_C(0), |
6945 | 0 | UINT64_C(0), |
6946 | 0 | UINT64_C(0), |
6947 | 0 | UINT64_C(0), |
6948 | 0 | UINT64_C(0), |
6949 | 0 | UINT64_C(0), |
6950 | 0 | UINT64_C(0), |
6951 | 0 | UINT64_C(0), |
6952 | 0 | UINT64_C(0), |
6953 | 0 | UINT64_C(0), |
6954 | 0 | UINT64_C(0), |
6955 | 0 | UINT64_C(0), |
6956 | 0 | UINT64_C(0), |
6957 | 0 | UINT64_C(0), |
6958 | 0 | UINT64_C(0), |
6959 | 0 | UINT64_C(0), |
6960 | 0 | UINT64_C(0), |
6961 | 0 | UINT64_C(0), |
6962 | 0 | UINT64_C(0), |
6963 | 0 | UINT64_C(0), |
6964 | 0 | UINT64_C(0), |
6965 | 0 | UINT64_C(0), |
6966 | 0 | UINT64_C(0), |
6967 | 0 | UINT64_C(0), |
6968 | 0 | UINT64_C(0), |
6969 | 0 | UINT64_C(0), |
6970 | 0 | UINT64_C(0), |
6971 | 0 | UINT64_C(0), |
6972 | 0 | UINT64_C(0), |
6973 | 0 | UINT64_C(0), |
6974 | 0 | UINT64_C(0), |
6975 | 0 | UINT64_C(0), |
6976 | 0 | UINT64_C(0), |
6977 | 0 | UINT64_C(0), |
6978 | 0 | UINT64_C(0), |
6979 | 0 | UINT64_C(0), |
6980 | 0 | UINT64_C(0), |
6981 | 0 | UINT64_C(0), |
6982 | 0 | UINT64_C(0), |
6983 | 0 | UINT64_C(0), |
6984 | 0 | UINT64_C(0), |
6985 | 0 | UINT64_C(0), |
6986 | 0 | UINT64_C(0), |
6987 | 0 | UINT64_C(0), |
6988 | 0 | UINT64_C(0), |
6989 | 0 | UINT64_C(0), |
6990 | 0 | UINT64_C(0), |
6991 | 0 | UINT64_C(0), |
6992 | 0 | UINT64_C(0), |
6993 | 0 | UINT64_C(0), |
6994 | 0 | UINT64_C(0), |
6995 | 0 | UINT64_C(0), |
6996 | 0 | UINT64_C(0), |
6997 | 0 | UINT64_C(0), |
6998 | 0 | UINT64_C(0), |
6999 | 0 | UINT64_C(0), |
7000 | 0 | UINT64_C(0), |
7001 | 0 | UINT64_C(0), |
7002 | 0 | UINT64_C(0), |
7003 | 0 | UINT64_C(0), |
7004 | 0 | UINT64_C(0), |
7005 | 0 | UINT64_C(0), |
7006 | 0 | UINT64_C(0), |
7007 | 0 | UINT64_C(0), |
7008 | 0 | UINT64_C(0), |
7009 | 0 | UINT64_C(0), |
7010 | 0 | UINT64_C(0), |
7011 | 0 | UINT64_C(0), |
7012 | 0 | UINT64_C(0), |
7013 | 0 | UINT64_C(0), |
7014 | 0 | UINT64_C(0), |
7015 | 0 | UINT64_C(0), |
7016 | 0 | UINT64_C(0), |
7017 | 0 | UINT64_C(0), |
7018 | 0 | UINT64_C(0), |
7019 | 0 | UINT64_C(0), |
7020 | 0 | UINT64_C(0), |
7021 | 0 | UINT64_C(0), |
7022 | 0 | UINT64_C(0), |
7023 | 0 | UINT64_C(0), |
7024 | 0 | UINT64_C(0), |
7025 | 0 | UINT64_C(0), |
7026 | 0 | UINT64_C(0), |
7027 | 0 | UINT64_C(0), |
7028 | 0 | UINT64_C(0), |
7029 | 0 | UINT64_C(0), |
7030 | 0 | UINT64_C(0), |
7031 | 0 | UINT64_C(0), |
7032 | 0 | UINT64_C(0), |
7033 | 0 | UINT64_C(0), |
7034 | 0 | UINT64_C(0), |
7035 | 0 | UINT64_C(0), |
7036 | 0 | UINT64_C(0), |
7037 | 0 | UINT64_C(0), |
7038 | 0 | UINT64_C(0), |
7039 | 0 | UINT64_C(0), |
7040 | 0 | UINT64_C(0), |
7041 | 0 | UINT64_C(0), |
7042 | 0 | UINT64_C(0), |
7043 | 0 | UINT64_C(0), |
7044 | 0 | UINT64_C(0), |
7045 | 0 | UINT64_C(0), |
7046 | 0 | UINT64_C(0), |
7047 | 0 | UINT64_C(0), |
7048 | 0 | UINT64_C(0), |
7049 | 0 | UINT64_C(0), |
7050 | 0 | UINT64_C(0), |
7051 | 0 | UINT64_C(0), |
7052 | 0 | UINT64_C(0), |
7053 | 0 | UINT64_C(0), |
7054 | 0 | UINT64_C(0), |
7055 | 0 | UINT64_C(0), |
7056 | 0 | UINT64_C(0), |
7057 | 0 | UINT64_C(0), |
7058 | 0 | UINT64_C(0), |
7059 | 0 | UINT64_C(0), |
7060 | 0 | UINT64_C(0), |
7061 | 0 | UINT64_C(0), |
7062 | 0 | UINT64_C(0), |
7063 | 0 | UINT64_C(0), |
7064 | 0 | UINT64_C(0), |
7065 | 0 | UINT64_C(0), |
7066 | 0 | UINT64_C(0), |
7067 | 0 | UINT64_C(0), |
7068 | 0 | UINT64_C(0), |
7069 | 0 | UINT64_C(0), |
7070 | 0 | UINT64_C(0), |
7071 | 0 | UINT64_C(0), |
7072 | 0 | UINT64_C(0), |
7073 | 0 | UINT64_C(0), |
7074 | 0 | UINT64_C(0), |
7075 | 0 | UINT64_C(0), |
7076 | 0 | UINT64_C(0), |
7077 | 0 | UINT64_C(0), |
7078 | 0 | UINT64_C(0), |
7079 | 0 | UINT64_C(0), |
7080 | 0 | UINT64_C(0), |
7081 | 0 | UINT64_C(0), |
7082 | 0 | UINT64_C(0), |
7083 | 0 | UINT64_C(0), |
7084 | 0 | UINT64_C(0), |
7085 | 0 | UINT64_C(0), |
7086 | 0 | UINT64_C(0), |
7087 | 0 | UINT64_C(0), |
7088 | 0 | UINT64_C(0), |
7089 | 0 | UINT64_C(0), |
7090 | 0 | UINT64_C(0), |
7091 | 0 | UINT64_C(0), |
7092 | 0 | UINT64_C(0), |
7093 | 0 | UINT64_C(0), |
7094 | 0 | UINT64_C(0), |
7095 | 0 | UINT64_C(0), |
7096 | 0 | UINT64_C(0), |
7097 | 0 | UINT64_C(0), |
7098 | 0 | UINT64_C(0), |
7099 | 0 | UINT64_C(0), |
7100 | 0 | UINT64_C(0), |
7101 | 0 | UINT64_C(0), |
7102 | 0 | UINT64_C(0), |
7103 | 0 | UINT64_C(0), |
7104 | 0 | UINT64_C(0), |
7105 | 0 | UINT64_C(0), |
7106 | 0 | UINT64_C(0), |
7107 | 0 | UINT64_C(0), |
7108 | 0 | UINT64_C(0), |
7109 | 0 | UINT64_C(0), |
7110 | 0 | UINT64_C(0), |
7111 | 0 | UINT64_C(0), |
7112 | 0 | UINT64_C(0), |
7113 | 0 | UINT64_C(0), |
7114 | 0 | UINT64_C(0), |
7115 | 0 | UINT64_C(0), |
7116 | 0 | UINT64_C(0), |
7117 | 0 | UINT64_C(0), |
7118 | 0 | UINT64_C(0), |
7119 | 0 | UINT64_C(0), |
7120 | 0 | UINT64_C(0), |
7121 | 0 | UINT64_C(0), |
7122 | 0 | UINT64_C(0), |
7123 | 0 | UINT64_C(0), |
7124 | 0 | UINT64_C(0), |
7125 | 0 | UINT64_C(0), |
7126 | 0 | UINT64_C(0), |
7127 | 0 | UINT64_C(0), |
7128 | 0 | UINT64_C(0), |
7129 | 0 | UINT64_C(0), |
7130 | 0 | UINT64_C(0), |
7131 | 0 | UINT64_C(0), |
7132 | 0 | UINT64_C(0), |
7133 | 0 | UINT64_C(0), |
7134 | 0 | UINT64_C(0), |
7135 | 0 | UINT64_C(0), |
7136 | 0 | UINT64_C(0), |
7137 | 0 | UINT64_C(0), |
7138 | 0 | UINT64_C(0), |
7139 | 0 | UINT64_C(0), |
7140 | 0 | UINT64_C(0), |
7141 | 0 | UINT64_C(0), |
7142 | 0 | UINT64_C(0), |
7143 | 0 | UINT64_C(0), |
7144 | 0 | UINT64_C(0), |
7145 | 0 | UINT64_C(0), |
7146 | 0 | UINT64_C(0), |
7147 | 0 | UINT64_C(0), |
7148 | 0 | UINT64_C(0), |
7149 | 0 | UINT64_C(0), |
7150 | 0 | UINT64_C(0), |
7151 | 0 | UINT64_C(0), |
7152 | 0 | UINT64_C(0), |
7153 | 0 | UINT64_C(0), |
7154 | 0 | UINT64_C(0), |
7155 | 0 | UINT64_C(0), |
7156 | 0 | UINT64_C(0), |
7157 | 0 | UINT64_C(0), |
7158 | 0 | UINT64_C(0), |
7159 | 0 | UINT64_C(0), |
7160 | 0 | UINT64_C(0), |
7161 | 0 | UINT64_C(0), |
7162 | 0 | UINT64_C(0), |
7163 | 0 | UINT64_C(0), |
7164 | 0 | UINT64_C(0), |
7165 | 0 | UINT64_C(0), |
7166 | 0 | UINT64_C(0), |
7167 | 0 | UINT64_C(0), |
7168 | 0 | UINT64_C(0), |
7169 | 0 | UINT64_C(0), |
7170 | 0 | UINT64_C(0), |
7171 | 0 | UINT64_C(0), |
7172 | 0 | UINT64_C(0), |
7173 | 0 | UINT64_C(0), |
7174 | 0 | UINT64_C(0), |
7175 | 0 | UINT64_C(0), |
7176 | 0 | UINT64_C(0), |
7177 | 0 | UINT64_C(0), |
7178 | 0 | UINT64_C(0), |
7179 | 0 | UINT64_C(0), |
7180 | 0 | UINT64_C(0), |
7181 | 0 | UINT64_C(0), |
7182 | 0 | UINT64_C(0), |
7183 | 0 | UINT64_C(0), |
7184 | 0 | UINT64_C(0), |
7185 | 0 | UINT64_C(0), |
7186 | 0 | UINT64_C(0), |
7187 | 0 | UINT64_C(0), |
7188 | 0 | UINT64_C(0), |
7189 | 0 | UINT64_C(0), |
7190 | 0 | UINT64_C(0), |
7191 | 0 | UINT64_C(0), |
7192 | 0 | UINT64_C(0), |
7193 | 0 | UINT64_C(0), |
7194 | 0 | UINT64_C(0), |
7195 | 0 | UINT64_C(0), |
7196 | 0 | UINT64_C(0), |
7197 | 0 | UINT64_C(0), |
7198 | 0 | UINT64_C(0), |
7199 | 0 | UINT64_C(0), |
7200 | 0 | UINT64_C(0), |
7201 | 0 | UINT64_C(0), |
7202 | 0 | UINT64_C(0), |
7203 | 0 | UINT64_C(0), |
7204 | 0 | UINT64_C(0), |
7205 | 0 | UINT64_C(0), |
7206 | 0 | UINT64_C(0), |
7207 | 0 | UINT64_C(0), |
7208 | 0 | UINT64_C(0), |
7209 | 0 | UINT64_C(0), |
7210 | 0 | UINT64_C(0), |
7211 | 0 | UINT64_C(0), |
7212 | 0 | UINT64_C(0), |
7213 | 0 | UINT64_C(0), |
7214 | 0 | UINT64_C(0), |
7215 | 0 | UINT64_C(0), |
7216 | 0 | UINT64_C(0), |
7217 | 0 | UINT64_C(0), |
7218 | 0 | UINT64_C(0), |
7219 | 0 | UINT64_C(0), |
7220 | 0 | UINT64_C(0), |
7221 | 0 | UINT64_C(0), |
7222 | 0 | UINT64_C(0), |
7223 | 0 | UINT64_C(0), |
7224 | 0 | UINT64_C(0), |
7225 | 0 | UINT64_C(0), |
7226 | 0 | UINT64_C(0), |
7227 | 0 | UINT64_C(0), |
7228 | 0 | UINT64_C(0), |
7229 | 0 | UINT64_C(0), |
7230 | 0 | UINT64_C(0), |
7231 | 0 | UINT64_C(0), |
7232 | 0 | UINT64_C(0), |
7233 | 0 | UINT64_C(0), |
7234 | 0 | UINT64_C(0), |
7235 | 0 | UINT64_C(0), |
7236 | 0 | UINT64_C(0), |
7237 | 0 | UINT64_C(0), |
7238 | 0 | UINT64_C(0), |
7239 | 0 | UINT64_C(0), |
7240 | 0 | UINT64_C(0), |
7241 | 0 | UINT64_C(0), |
7242 | 0 | UINT64_C(0), |
7243 | 0 | UINT64_C(0), |
7244 | 0 | UINT64_C(0), |
7245 | 0 | UINT64_C(0), |
7246 | 0 | UINT64_C(0), |
7247 | 0 | UINT64_C(0), |
7248 | 0 | UINT64_C(0), |
7249 | 0 | UINT64_C(0), |
7250 | 0 | UINT64_C(0), |
7251 | 0 | UINT64_C(0), |
7252 | 0 | UINT64_C(0), |
7253 | 0 | UINT64_C(0), |
7254 | 0 | UINT64_C(0), |
7255 | 0 | UINT64_C(0), |
7256 | 0 | UINT64_C(0), |
7257 | 0 | UINT64_C(0), |
7258 | 0 | UINT64_C(0), |
7259 | 0 | UINT64_C(0), |
7260 | 0 | UINT64_C(0), |
7261 | 0 | UINT64_C(0), |
7262 | 0 | UINT64_C(0), |
7263 | 0 | UINT64_C(0), |
7264 | 0 | UINT64_C(0), |
7265 | 0 | UINT64_C(0), |
7266 | 0 | UINT64_C(0), |
7267 | 0 | UINT64_C(0), |
7268 | 0 | UINT64_C(0), |
7269 | 0 | UINT64_C(0), |
7270 | 0 | UINT64_C(0), |
7271 | 0 | UINT64_C(0), |
7272 | 0 | UINT64_C(0), |
7273 | 0 | UINT64_C(0), |
7274 | 0 | UINT64_C(0), |
7275 | 0 | UINT64_C(0), |
7276 | 0 | UINT64_C(0), |
7277 | 0 | UINT64_C(0), |
7278 | 0 | UINT64_C(0), |
7279 | 0 | UINT64_C(0), |
7280 | 0 | UINT64_C(0), |
7281 | 0 | UINT64_C(0), |
7282 | 0 | UINT64_C(0), |
7283 | 0 | UINT64_C(0), |
7284 | 0 | UINT64_C(0), |
7285 | 0 | UINT64_C(0), |
7286 | 0 | UINT64_C(0), |
7287 | 0 | UINT64_C(0), |
7288 | 0 | UINT64_C(0), |
7289 | 0 | UINT64_C(0), |
7290 | 0 | UINT64_C(0), |
7291 | 0 | UINT64_C(0), |
7292 | 0 | UINT64_C(0), |
7293 | 0 | UINT64_C(0), |
7294 | 0 | UINT64_C(0), |
7295 | 0 | UINT64_C(0), |
7296 | 0 | UINT64_C(0), |
7297 | 0 | UINT64_C(0), |
7298 | 0 | UINT64_C(0), |
7299 | 0 | UINT64_C(0), |
7300 | 0 | UINT64_C(0), |
7301 | 0 | UINT64_C(0), |
7302 | 0 | UINT64_C(0), |
7303 | 0 | UINT64_C(0), |
7304 | 0 | UINT64_C(0), |
7305 | 0 | UINT64_C(0), |
7306 | 0 | UINT64_C(0), |
7307 | 0 | UINT64_C(0), |
7308 | 0 | UINT64_C(0), |
7309 | 0 | UINT64_C(0), |
7310 | 0 | UINT64_C(0), |
7311 | 0 | UINT64_C(0), |
7312 | 0 | UINT64_C(0), |
7313 | 0 | UINT64_C(0), |
7314 | 0 | UINT64_C(0), |
7315 | 0 | UINT64_C(0), |
7316 | 0 | UINT64_C(0), |
7317 | 0 | UINT64_C(0), |
7318 | 0 | UINT64_C(0), |
7319 | 0 | UINT64_C(0), |
7320 | 0 | UINT64_C(0), |
7321 | 0 | UINT64_C(0), |
7322 | 0 | UINT64_C(0), |
7323 | 0 | UINT64_C(0), |
7324 | 0 | UINT64_C(0), |
7325 | 0 | UINT64_C(0), |
7326 | 0 | UINT64_C(0), |
7327 | 0 | UINT64_C(0), |
7328 | 0 | UINT64_C(0), |
7329 | 0 | UINT64_C(0), |
7330 | 0 | UINT64_C(0), |
7331 | 0 | UINT64_C(0), |
7332 | 0 | UINT64_C(0), |
7333 | 0 | UINT64_C(0), |
7334 | 0 | UINT64_C(0), |
7335 | 0 | UINT64_C(0), |
7336 | 0 | UINT64_C(0), |
7337 | 0 | UINT64_C(0), |
7338 | 0 | UINT64_C(0), |
7339 | 0 | UINT64_C(0), |
7340 | 0 | UINT64_C(0), |
7341 | 0 | UINT64_C(0), |
7342 | 0 | UINT64_C(0), |
7343 | 0 | UINT64_C(0), |
7344 | 0 | UINT64_C(0), |
7345 | 0 | UINT64_C(0), |
7346 | 0 | UINT64_C(0), |
7347 | 0 | UINT64_C(0), |
7348 | 0 | UINT64_C(0), |
7349 | 0 | UINT64_C(0), |
7350 | 0 | UINT64_C(0), |
7351 | 0 | UINT64_C(0), |
7352 | 0 | UINT64_C(0), |
7353 | 0 | UINT64_C(0), |
7354 | 0 | UINT64_C(0), |
7355 | 0 | UINT64_C(0), |
7356 | 0 | UINT64_C(0), |
7357 | 0 | UINT64_C(0), |
7358 | 0 | UINT64_C(0), |
7359 | 0 | UINT64_C(0), |
7360 | 0 | UINT64_C(0), |
7361 | 0 | UINT64_C(0), |
7362 | 0 | UINT64_C(0), |
7363 | 0 | UINT64_C(0), |
7364 | 0 | UINT64_C(0), |
7365 | 0 | UINT64_C(0), |
7366 | 0 | UINT64_C(0), |
7367 | 0 | UINT64_C(0), |
7368 | 0 | UINT64_C(0), |
7369 | 0 | UINT64_C(0), |
7370 | 0 | UINT64_C(0), |
7371 | 0 | UINT64_C(0), |
7372 | 0 | UINT64_C(0), |
7373 | 0 | UINT64_C(0), |
7374 | 0 | UINT64_C(0), |
7375 | 0 | UINT64_C(0), |
7376 | 0 | UINT64_C(0), |
7377 | 0 | UINT64_C(0), |
7378 | 0 | UINT64_C(0), |
7379 | 0 | UINT64_C(0), |
7380 | 0 | UINT64_C(0), |
7381 | 0 | UINT64_C(0), |
7382 | 0 | UINT64_C(0), |
7383 | 0 | UINT64_C(0), |
7384 | 0 | UINT64_C(0), |
7385 | 0 | UINT64_C(0), |
7386 | 0 | UINT64_C(0), |
7387 | 0 | UINT64_C(0), |
7388 | 0 | UINT64_C(0), |
7389 | 0 | UINT64_C(0), |
7390 | 0 | UINT64_C(0), |
7391 | 0 | UINT64_C(0), |
7392 | 0 | UINT64_C(0), |
7393 | 0 | UINT64_C(0), |
7394 | 0 | UINT64_C(0), |
7395 | 0 | UINT64_C(0), |
7396 | 0 | UINT64_C(0), |
7397 | 0 | UINT64_C(0), |
7398 | 0 | UINT64_C(0), |
7399 | 0 | UINT64_C(0), |
7400 | 0 | UINT64_C(0), |
7401 | 0 | UINT64_C(0), |
7402 | 0 | UINT64_C(0), |
7403 | 0 | UINT64_C(0), |
7404 | 0 | UINT64_C(0), |
7405 | 0 | UINT64_C(0), |
7406 | 0 | UINT64_C(0), |
7407 | 0 | UINT64_C(0), |
7408 | 0 | UINT64_C(0), |
7409 | 0 | UINT64_C(0), |
7410 | 0 | UINT64_C(0), |
7411 | 0 | UINT64_C(0), |
7412 | 0 | UINT64_C(0), |
7413 | 0 | UINT64_C(0), |
7414 | 0 | UINT64_C(0), |
7415 | 0 | UINT64_C(0), |
7416 | 0 | UINT64_C(0), |
7417 | 0 | UINT64_C(0), |
7418 | 0 | UINT64_C(0), |
7419 | 0 | UINT64_C(0), |
7420 | 0 | UINT64_C(0), |
7421 | 0 | UINT64_C(0), |
7422 | 0 | UINT64_C(0), |
7423 | 0 | UINT64_C(0), |
7424 | 0 | UINT64_C(0), |
7425 | 0 | UINT64_C(0), |
7426 | 0 | UINT64_C(0), |
7427 | 0 | UINT64_C(0), |
7428 | 0 | UINT64_C(0), |
7429 | 0 | UINT64_C(0), |
7430 | 0 | UINT64_C(0), |
7431 | 0 | UINT64_C(0), |
7432 | 0 | UINT64_C(0), |
7433 | 0 | UINT64_C(0), |
7434 | 0 | UINT64_C(0), |
7435 | 0 | UINT64_C(0), |
7436 | 0 | UINT64_C(0), |
7437 | 0 | UINT64_C(0), |
7438 | 0 | UINT64_C(0), |
7439 | 0 | UINT64_C(0), |
7440 | 0 | UINT64_C(0), |
7441 | 0 | UINT64_C(0), |
7442 | 0 | UINT64_C(0), |
7443 | 0 | UINT64_C(0), |
7444 | 0 | UINT64_C(0), |
7445 | 0 | UINT64_C(0), |
7446 | 0 | UINT64_C(0), |
7447 | 0 | UINT64_C(0), |
7448 | 0 | UINT64_C(0), |
7449 | 0 | UINT64_C(0), |
7450 | 0 | UINT64_C(0), |
7451 | 0 | UINT64_C(0), |
7452 | 0 | UINT64_C(0), |
7453 | 0 | UINT64_C(0), |
7454 | 0 | UINT64_C(0), |
7455 | 0 | UINT64_C(0), |
7456 | 0 | UINT64_C(0), |
7457 | 0 | UINT64_C(0), |
7458 | 0 | UINT64_C(0), |
7459 | 0 | UINT64_C(0), |
7460 | 0 | UINT64_C(0), |
7461 | 0 | UINT64_C(0), |
7462 | 0 | UINT64_C(0), |
7463 | 0 | UINT64_C(0), |
7464 | 0 | UINT64_C(0), |
7465 | 0 | UINT64_C(0), |
7466 | 0 | UINT64_C(0), |
7467 | 0 | UINT64_C(0), |
7468 | 0 | UINT64_C(0), |
7469 | 0 | UINT64_C(0), |
7470 | 0 | UINT64_C(0), |
7471 | 0 | UINT64_C(0), |
7472 | 0 | UINT64_C(0), |
7473 | 0 | UINT64_C(0), |
7474 | 0 | UINT64_C(0), |
7475 | 0 | UINT64_C(0), |
7476 | 0 | UINT64_C(0), |
7477 | 0 | UINT64_C(0), |
7478 | 0 | UINT64_C(0), |
7479 | 0 | UINT64_C(0), |
7480 | 0 | UINT64_C(0), |
7481 | 0 | UINT64_C(0), |
7482 | 0 | UINT64_C(0), |
7483 | 0 | UINT64_C(0), |
7484 | 0 | UINT64_C(0), |
7485 | 0 | UINT64_C(0), |
7486 | 0 | UINT64_C(0), |
7487 | 0 | UINT64_C(0), |
7488 | 0 | UINT64_C(0), |
7489 | 0 | UINT64_C(0), |
7490 | 0 | UINT64_C(0), |
7491 | 0 | UINT64_C(0), |
7492 | 0 | UINT64_C(0), |
7493 | 0 | UINT64_C(0), |
7494 | 0 | UINT64_C(0), |
7495 | 0 | UINT64_C(0), |
7496 | 0 | UINT64_C(0), |
7497 | 0 | UINT64_C(0), |
7498 | 0 | UINT64_C(0), |
7499 | 0 | UINT64_C(0), |
7500 | 0 | UINT64_C(0), |
7501 | 0 | UINT64_C(0), |
7502 | 0 | UINT64_C(0), |
7503 | 0 | UINT64_C(0), |
7504 | 0 | UINT64_C(0), |
7505 | 0 | UINT64_C(0), |
7506 | 0 | UINT64_C(0), |
7507 | 0 | UINT64_C(0), |
7508 | 0 | UINT64_C(0), |
7509 | 0 | UINT64_C(0), |
7510 | 0 | UINT64_C(0), |
7511 | 0 | UINT64_C(0), |
7512 | 0 | UINT64_C(0), |
7513 | 0 | UINT64_C(0), |
7514 | 0 | UINT64_C(0), |
7515 | 0 | UINT64_C(0), |
7516 | 0 | UINT64_C(0), |
7517 | 0 | UINT64_C(0), |
7518 | 0 | UINT64_C(0), |
7519 | 0 | UINT64_C(0), |
7520 | 0 | UINT64_C(0), |
7521 | 0 | UINT64_C(0), |
7522 | 0 | UINT64_C(0), |
7523 | 0 | UINT64_C(0), |
7524 | 0 | UINT64_C(0), |
7525 | 0 | UINT64_C(0), |
7526 | 0 | UINT64_C(0), |
7527 | 0 | UINT64_C(0), |
7528 | 0 | UINT64_C(0), |
7529 | 0 | UINT64_C(0), |
7530 | 0 | UINT64_C(0), |
7531 | 0 | UINT64_C(0), |
7532 | 0 | UINT64_C(0), |
7533 | 0 | UINT64_C(0), |
7534 | 0 | UINT64_C(0), |
7535 | 0 | UINT64_C(0), |
7536 | 0 | UINT64_C(0), |
7537 | 0 | UINT64_C(0), |
7538 | 0 | UINT64_C(0), |
7539 | 0 | UINT64_C(0), |
7540 | 0 | UINT64_C(0), |
7541 | 0 | UINT64_C(0), |
7542 | 0 | UINT64_C(0), |
7543 | 0 | UINT64_C(0), |
7544 | 0 | UINT64_C(0), |
7545 | 0 | UINT64_C(0), |
7546 | 0 | UINT64_C(0), |
7547 | 0 | UINT64_C(0), |
7548 | 0 | UINT64_C(0), |
7549 | 0 | UINT64_C(0), |
7550 | 0 | UINT64_C(0), |
7551 | 0 | UINT64_C(0), |
7552 | 0 | UINT64_C(0), |
7553 | 0 | UINT64_C(0), |
7554 | 0 | UINT64_C(0), |
7555 | 0 | UINT64_C(0), |
7556 | 0 | UINT64_C(0), |
7557 | 0 | UINT64_C(0), |
7558 | 0 | UINT64_C(0), |
7559 | 0 | UINT64_C(0), |
7560 | 0 | UINT64_C(0), |
7561 | 0 | UINT64_C(0), |
7562 | 0 | UINT64_C(0), |
7563 | 0 | UINT64_C(0), |
7564 | 0 | UINT64_C(0), |
7565 | 0 | UINT64_C(0), |
7566 | 0 | UINT64_C(0), |
7567 | 0 | UINT64_C(0), |
7568 | 0 | UINT64_C(0), |
7569 | 0 | UINT64_C(0), |
7570 | 0 | UINT64_C(0), |
7571 | 0 | UINT64_C(0), |
7572 | 0 | UINT64_C(0), |
7573 | 0 | UINT64_C(0), |
7574 | 0 | UINT64_C(0), |
7575 | 0 | UINT64_C(0), |
7576 | 0 | UINT64_C(0), |
7577 | 0 | UINT64_C(0), |
7578 | 0 | UINT64_C(0), |
7579 | 0 | UINT64_C(0), |
7580 | 0 | UINT64_C(0), |
7581 | 0 | UINT64_C(0), |
7582 | 0 | UINT64_C(0), |
7583 | 0 | UINT64_C(0), |
7584 | 0 | UINT64_C(0), |
7585 | 0 | UINT64_C(0), |
7586 | 0 | UINT64_C(0), |
7587 | 0 | UINT64_C(0), |
7588 | 0 | UINT64_C(0), |
7589 | 0 | UINT64_C(0), |
7590 | 0 | UINT64_C(0), |
7591 | 0 | UINT64_C(0), |
7592 | 0 | UINT64_C(0), |
7593 | 0 | UINT64_C(0), |
7594 | 0 | UINT64_C(0), |
7595 | 0 | UINT64_C(0), |
7596 | 0 | UINT64_C(0), |
7597 | 0 | UINT64_C(0), |
7598 | 0 | UINT64_C(0), |
7599 | 0 | UINT64_C(0), |
7600 | 0 | UINT64_C(0), |
7601 | 0 | UINT64_C(0), |
7602 | 0 | UINT64_C(0), |
7603 | 0 | UINT64_C(0), |
7604 | 0 | UINT64_C(0), |
7605 | 0 | UINT64_C(0), |
7606 | 0 | UINT64_C(0), |
7607 | 0 | UINT64_C(0), |
7608 | 0 | UINT64_C(0), |
7609 | 0 | UINT64_C(0), |
7610 | 0 | UINT64_C(0), |
7611 | 0 | UINT64_C(0), |
7612 | 0 | UINT64_C(0), |
7613 | 0 | UINT64_C(0), |
7614 | 0 | UINT64_C(0), |
7615 | 0 | UINT64_C(0), |
7616 | 0 | UINT64_C(0), |
7617 | 0 | UINT64_C(0), |
7618 | 0 | UINT64_C(0), |
7619 | 0 | UINT64_C(0), |
7620 | 0 | UINT64_C(0), |
7621 | 0 | UINT64_C(0), |
7622 | 0 | UINT64_C(0), |
7623 | 0 | UINT64_C(0), |
7624 | 0 | UINT64_C(0), |
7625 | 0 | UINT64_C(0), |
7626 | 0 | UINT64_C(0), |
7627 | 0 | UINT64_C(0), |
7628 | 0 | UINT64_C(0), |
7629 | 0 | UINT64_C(0), |
7630 | 0 | UINT64_C(0), |
7631 | 0 | UINT64_C(0), |
7632 | 0 | UINT64_C(0), |
7633 | 0 | UINT64_C(0), |
7634 | 0 | UINT64_C(0), |
7635 | 0 | UINT64_C(0), |
7636 | 0 | UINT64_C(0), |
7637 | 0 | UINT64_C(0), |
7638 | 0 | UINT64_C(0), |
7639 | 0 | UINT64_C(0), |
7640 | 0 | UINT64_C(0), |
7641 | 0 | UINT64_C(0), |
7642 | 0 | UINT64_C(0), |
7643 | 0 | UINT64_C(0), |
7644 | 0 | UINT64_C(0), |
7645 | 0 | UINT64_C(0), |
7646 | 0 | UINT64_C(0), |
7647 | 0 | UINT64_C(0), |
7648 | 0 | UINT64_C(0), |
7649 | 0 | UINT64_C(0), |
7650 | 0 | UINT64_C(0), |
7651 | 0 | UINT64_C(0), |
7652 | 0 | UINT64_C(0), |
7653 | 0 | UINT64_C(0), |
7654 | 0 | UINT64_C(0), |
7655 | 0 | UINT64_C(0), |
7656 | 0 | UINT64_C(0), |
7657 | 0 | UINT64_C(0), |
7658 | 0 | UINT64_C(0), |
7659 | 0 | UINT64_C(0), |
7660 | 0 | UINT64_C(0), |
7661 | 0 | UINT64_C(0), |
7662 | 0 | UINT64_C(0), |
7663 | 0 | UINT64_C(0), |
7664 | 0 | UINT64_C(0), |
7665 | 0 | UINT64_C(0), |
7666 | 0 | UINT64_C(0), |
7667 | 0 | UINT64_C(0), |
7668 | 0 | UINT64_C(0), |
7669 | 0 | UINT64_C(0), |
7670 | 0 | UINT64_C(0), |
7671 | 0 | UINT64_C(0), |
7672 | 0 | UINT64_C(0), |
7673 | 0 | UINT64_C(0), |
7674 | 0 | UINT64_C(0), |
7675 | 0 | UINT64_C(0), |
7676 | 0 | UINT64_C(0), |
7677 | 0 | UINT64_C(0), |
7678 | 0 | UINT64_C(0), |
7679 | 0 | UINT64_C(0), |
7680 | 0 | UINT64_C(0), |
7681 | 0 | UINT64_C(0), |
7682 | 0 | UINT64_C(0), |
7683 | 0 | UINT64_C(0), |
7684 | 0 | UINT64_C(0), |
7685 | 0 | UINT64_C(0), |
7686 | 0 | UINT64_C(0), |
7687 | 0 | UINT64_C(0), |
7688 | 0 | UINT64_C(0), |
7689 | 0 | UINT64_C(0), |
7690 | 0 | UINT64_C(0), |
7691 | 0 | UINT64_C(0), |
7692 | 0 | UINT64_C(0), |
7693 | 0 | UINT64_C(0), |
7694 | 0 | UINT64_C(0), |
7695 | 0 | UINT64_C(0), |
7696 | 0 | UINT64_C(0), |
7697 | 0 | UINT64_C(0), |
7698 | 0 | UINT64_C(0), |
7699 | 0 | UINT64_C(0), |
7700 | 0 | UINT64_C(0), |
7701 | 0 | UINT64_C(0), |
7702 | 0 | UINT64_C(0), |
7703 | 0 | UINT64_C(0), |
7704 | 0 | UINT64_C(0), |
7705 | 0 | UINT64_C(0), |
7706 | 0 | UINT64_C(0), |
7707 | 0 | UINT64_C(0), |
7708 | 0 | UINT64_C(0), |
7709 | 0 | UINT64_C(0), |
7710 | 0 | UINT64_C(0), |
7711 | 0 | UINT64_C(0), |
7712 | 0 | UINT64_C(0), |
7713 | 0 | UINT64_C(0), |
7714 | 0 | UINT64_C(0), |
7715 | 0 | UINT64_C(0), |
7716 | 0 | UINT64_C(0), |
7717 | 0 | UINT64_C(0), |
7718 | 0 | UINT64_C(0), |
7719 | 0 | UINT64_C(0), |
7720 | 0 | UINT64_C(0), |
7721 | 0 | UINT64_C(0), |
7722 | 0 | UINT64_C(0), |
7723 | 0 | UINT64_C(0), |
7724 | 0 | UINT64_C(0), |
7725 | 0 | UINT64_C(0), |
7726 | 0 | UINT64_C(0), |
7727 | 0 | UINT64_C(0), |
7728 | 0 | UINT64_C(0), |
7729 | 0 | UINT64_C(0), |
7730 | 0 | UINT64_C(0), |
7731 | 0 | UINT64_C(0), |
7732 | 0 | UINT64_C(0), |
7733 | 0 | UINT64_C(0), |
7734 | 0 | UINT64_C(0), |
7735 | 0 | UINT64_C(0), |
7736 | 0 | UINT64_C(0), |
7737 | 0 | UINT64_C(0), |
7738 | 0 | UINT64_C(0), |
7739 | 0 | UINT64_C(0), |
7740 | 0 | UINT64_C(0), |
7741 | 0 | UINT64_C(0), |
7742 | 0 | UINT64_C(0), |
7743 | 0 | UINT64_C(0), |
7744 | 0 | UINT64_C(0), |
7745 | 0 | UINT64_C(0), |
7746 | 0 | UINT64_C(0), |
7747 | 0 | UINT64_C(0), |
7748 | 0 | UINT64_C(0), |
7749 | 0 | UINT64_C(0), |
7750 | 0 | UINT64_C(0), |
7751 | 0 | UINT64_C(0), |
7752 | 0 | UINT64_C(0), |
7753 | 0 | UINT64_C(0), |
7754 | 0 | UINT64_C(0), |
7755 | 0 | UINT64_C(0), |
7756 | 0 | UINT64_C(0), |
7757 | 0 | UINT64_C(0), |
7758 | 0 | UINT64_C(0), |
7759 | 0 | UINT64_C(0), |
7760 | 0 | UINT64_C(0), |
7761 | 0 | UINT64_C(0), |
7762 | 0 | UINT64_C(0), |
7763 | 0 | UINT64_C(0), |
7764 | 0 | UINT64_C(0), |
7765 | 0 | UINT64_C(0), |
7766 | 0 | UINT64_C(0), |
7767 | 0 | UINT64_C(0), |
7768 | 0 | UINT64_C(0), |
7769 | 0 | UINT64_C(0), |
7770 | 0 | UINT64_C(0), |
7771 | 0 | UINT64_C(0), |
7772 | 0 | UINT64_C(0), |
7773 | 0 | UINT64_C(0), |
7774 | 0 | UINT64_C(0), |
7775 | 0 | UINT64_C(0), |
7776 | 0 | UINT64_C(0), |
7777 | 0 | UINT64_C(0), |
7778 | 0 | UINT64_C(0), |
7779 | 0 | UINT64_C(0), |
7780 | 0 | UINT64_C(0), |
7781 | 0 | UINT64_C(0), |
7782 | 0 | UINT64_C(0), |
7783 | 0 | UINT64_C(0), |
7784 | 0 | UINT64_C(0), |
7785 | 0 | UINT64_C(0), |
7786 | 0 | UINT64_C(0), |
7787 | 0 | UINT64_C(0), |
7788 | 0 | UINT64_C(0), |
7789 | 0 | UINT64_C(0), |
7790 | 0 | UINT64_C(0), |
7791 | 0 | UINT64_C(0), |
7792 | 0 | UINT64_C(0), |
7793 | 0 | UINT64_C(0), |
7794 | 0 | UINT64_C(0), |
7795 | 0 | UINT64_C(0), |
7796 | 0 | UINT64_C(0), |
7797 | 0 | UINT64_C(0), |
7798 | 0 | UINT64_C(0), |
7799 | 0 | UINT64_C(0), |
7800 | 0 | UINT64_C(0), |
7801 | 0 | UINT64_C(0), |
7802 | 0 | UINT64_C(0), |
7803 | 0 | UINT64_C(0), |
7804 | 0 | UINT64_C(0), |
7805 | 0 | UINT64_C(0), |
7806 | 0 | UINT64_C(0), |
7807 | 0 | UINT64_C(0), |
7808 | 0 | UINT64_C(0), |
7809 | 0 | UINT64_C(0), |
7810 | 0 | UINT64_C(0), |
7811 | 0 | UINT64_C(0), |
7812 | 0 | UINT64_C(0), |
7813 | 0 | UINT64_C(0), |
7814 | 0 | UINT64_C(0), |
7815 | 0 | UINT64_C(0), |
7816 | 0 | UINT64_C(0), |
7817 | 0 | UINT64_C(0), |
7818 | 0 | UINT64_C(0), |
7819 | 0 | UINT64_C(0), |
7820 | 0 | UINT64_C(0), |
7821 | 0 | UINT64_C(0), |
7822 | 0 | UINT64_C(0), |
7823 | 0 | UINT64_C(0), |
7824 | 0 | UINT64_C(0), |
7825 | 0 | UINT64_C(0), |
7826 | 0 | UINT64_C(0), |
7827 | 0 | UINT64_C(0), |
7828 | 0 | UINT64_C(0), |
7829 | 0 | UINT64_C(0), |
7830 | 0 | UINT64_C(0), |
7831 | 0 | UINT64_C(0), |
7832 | 0 | UINT64_C(0), |
7833 | 0 | UINT64_C(0), |
7834 | 0 | UINT64_C(0), |
7835 | 0 | UINT64_C(0), |
7836 | 0 | UINT64_C(0), |
7837 | 0 | UINT64_C(0), |
7838 | 0 | UINT64_C(0), |
7839 | 0 | UINT64_C(0), |
7840 | 0 | UINT64_C(0), |
7841 | 0 | UINT64_C(0), |
7842 | 0 | UINT64_C(0), |
7843 | 0 | UINT64_C(0), |
7844 | 0 | UINT64_C(0), |
7845 | 0 | UINT64_C(0), |
7846 | 0 | UINT64_C(0), |
7847 | 0 | UINT64_C(0), |
7848 | 0 | UINT64_C(0), |
7849 | 0 | UINT64_C(0), |
7850 | 0 | UINT64_C(0), |
7851 | 0 | UINT64_C(0), |
7852 | 0 | UINT64_C(0), |
7853 | 0 | UINT64_C(0), |
7854 | 0 | UINT64_C(0), |
7855 | 0 | UINT64_C(0), |
7856 | 0 | UINT64_C(0), |
7857 | 0 | UINT64_C(0), |
7858 | 0 | UINT64_C(0), |
7859 | 0 | UINT64_C(0), |
7860 | 0 | UINT64_C(0), |
7861 | 0 | UINT64_C(0), |
7862 | 0 | UINT64_C(0), |
7863 | 0 | UINT64_C(0), |
7864 | 0 | UINT64_C(0), |
7865 | 0 | UINT64_C(0), |
7866 | 0 | UINT64_C(0), |
7867 | 0 | UINT64_C(0), |
7868 | 0 | UINT64_C(0), |
7869 | 0 | UINT64_C(0), |
7870 | 0 | UINT64_C(0), |
7871 | 0 | UINT64_C(0), |
7872 | 0 | UINT64_C(0), |
7873 | 0 | UINT64_C(0), |
7874 | 0 | UINT64_C(0), |
7875 | 0 | UINT64_C(0), |
7876 | 0 | UINT64_C(0), |
7877 | 0 | UINT64_C(0), |
7878 | 0 | UINT64_C(0), |
7879 | 0 | UINT64_C(0), |
7880 | 0 | UINT64_C(0), |
7881 | 0 | UINT64_C(0), |
7882 | 0 | UINT64_C(0), |
7883 | 0 | UINT64_C(0), |
7884 | 0 | UINT64_C(0), |
7885 | 0 | UINT64_C(0), |
7886 | 0 | UINT64_C(0), |
7887 | 0 | UINT64_C(0), |
7888 | 0 | UINT64_C(0), |
7889 | 0 | UINT64_C(0), |
7890 | 0 | UINT64_C(0), |
7891 | 0 | UINT64_C(0), |
7892 | 0 | UINT64_C(0), |
7893 | 0 | UINT64_C(0), |
7894 | 0 | UINT64_C(0), |
7895 | 0 | UINT64_C(0), |
7896 | 0 | UINT64_C(0), |
7897 | 0 | UINT64_C(0), |
7898 | 0 | UINT64_C(0), |
7899 | 0 | UINT64_C(0), |
7900 | 0 | UINT64_C(0), |
7901 | 0 | UINT64_C(0), |
7902 | 0 | UINT64_C(0), |
7903 | 0 | UINT64_C(0), |
7904 | 0 | UINT64_C(0), |
7905 | 0 | UINT64_C(0), |
7906 | 0 | UINT64_C(0), |
7907 | 0 | UINT64_C(0), |
7908 | 0 | UINT64_C(0), |
7909 | 0 | UINT64_C(0), |
7910 | 0 | UINT64_C(0), |
7911 | 0 | UINT64_C(0), |
7912 | 0 | UINT64_C(0), |
7913 | 0 | UINT64_C(0), |
7914 | 0 | UINT64_C(0), |
7915 | 0 | UINT64_C(0), |
7916 | 0 | UINT64_C(0), |
7917 | 0 | UINT64_C(0), |
7918 | 0 | UINT64_C(0), |
7919 | 0 | UINT64_C(0), |
7920 | 0 | UINT64_C(0), |
7921 | 0 | UINT64_C(0), |
7922 | 0 | UINT64_C(0), |
7923 | 0 | UINT64_C(0), |
7924 | 0 | UINT64_C(0), |
7925 | 0 | UINT64_C(0), |
7926 | 0 | UINT64_C(0), |
7927 | 0 | UINT64_C(0), |
7928 | 0 | UINT64_C(0), |
7929 | 0 | UINT64_C(0), |
7930 | 0 | UINT64_C(0), |
7931 | 0 | UINT64_C(0), |
7932 | 0 | UINT64_C(0), |
7933 | 0 | UINT64_C(0), |
7934 | 0 | UINT64_C(0), |
7935 | 0 | UINT64_C(0), |
7936 | 0 | UINT64_C(0), |
7937 | 0 | UINT64_C(0), |
7938 | 0 | UINT64_C(0), |
7939 | 0 | UINT64_C(0), |
7940 | 0 | UINT64_C(0), |
7941 | 0 | UINT64_C(0), |
7942 | 0 | UINT64_C(0), |
7943 | 0 | UINT64_C(0), |
7944 | 0 | UINT64_C(0), |
7945 | 0 | UINT64_C(0), |
7946 | 0 | UINT64_C(0), |
7947 | 0 | UINT64_C(0), |
7948 | 0 | UINT64_C(0), |
7949 | 0 | UINT64_C(0), |
7950 | 0 | UINT64_C(0), |
7951 | 0 | UINT64_C(0), |
7952 | 0 | UINT64_C(0), |
7953 | 0 | UINT64_C(0), |
7954 | 0 | UINT64_C(0), |
7955 | 0 | UINT64_C(0), |
7956 | 0 | UINT64_C(0), |
7957 | 0 | UINT64_C(0), |
7958 | 0 | UINT64_C(0), |
7959 | 0 | UINT64_C(0), |
7960 | 0 | UINT64_C(0), |
7961 | 0 | UINT64_C(0), |
7962 | 0 | UINT64_C(0), |
7963 | 0 | UINT64_C(0), |
7964 | 0 | UINT64_C(0), |
7965 | 0 | UINT64_C(0), |
7966 | 0 | UINT64_C(0), |
7967 | 0 | UINT64_C(0), |
7968 | 0 | UINT64_C(0), |
7969 | 0 | UINT64_C(0), |
7970 | 0 | UINT64_C(0), |
7971 | 0 | UINT64_C(0), |
7972 | 0 | UINT64_C(0), |
7973 | 0 | UINT64_C(0), |
7974 | 0 | UINT64_C(0), |
7975 | 0 | UINT64_C(0), |
7976 | 0 | UINT64_C(0), |
7977 | 0 | UINT64_C(0), |
7978 | 0 | UINT64_C(0), |
7979 | 0 | UINT64_C(0), |
7980 | 0 | UINT64_C(0), |
7981 | 0 | UINT64_C(0), |
7982 | 0 | UINT64_C(0), |
7983 | 0 | UINT64_C(0), |
7984 | 0 | UINT64_C(0), |
7985 | 0 | UINT64_C(0), |
7986 | 0 | UINT64_C(0), |
7987 | 0 | UINT64_C(0), |
7988 | 0 | UINT64_C(0), |
7989 | 0 | UINT64_C(0), |
7990 | 0 | UINT64_C(0), |
7991 | 0 | UINT64_C(0), |
7992 | 0 | UINT64_C(0), |
7993 | 0 | UINT64_C(0), |
7994 | 0 | UINT64_C(0), |
7995 | 0 | UINT64_C(0), |
7996 | 0 | UINT64_C(0), |
7997 | 0 | UINT64_C(0), |
7998 | 0 | UINT64_C(0), |
7999 | 0 | UINT64_C(0), |
8000 | 0 | UINT64_C(0), |
8001 | 0 | UINT64_C(0), |
8002 | 0 | UINT64_C(0), |
8003 | 0 | UINT64_C(0), |
8004 | 0 | UINT64_C(0), |
8005 | 0 | UINT64_C(0), |
8006 | 0 | UINT64_C(0), |
8007 | 0 | UINT64_C(0), |
8008 | 0 | UINT64_C(0), |
8009 | 0 | UINT64_C(0), |
8010 | 0 | UINT64_C(0), |
8011 | 0 | UINT64_C(0), |
8012 | 0 | UINT64_C(0), |
8013 | 0 | UINT64_C(0), |
8014 | 0 | UINT64_C(0), |
8015 | 0 | UINT64_C(0), |
8016 | 0 | UINT64_C(0), |
8017 | 0 | UINT64_C(0), |
8018 | 0 | UINT64_C(0), |
8019 | 0 | UINT64_C(0), |
8020 | 0 | UINT64_C(0), |
8021 | 0 | UINT64_C(0), |
8022 | 0 | UINT64_C(0), |
8023 | 0 | UINT64_C(0), |
8024 | 0 | UINT64_C(0), |
8025 | 0 | UINT64_C(0), |
8026 | 0 | UINT64_C(0), |
8027 | 0 | UINT64_C(0), |
8028 | 0 | UINT64_C(0), |
8029 | 0 | UINT64_C(0), |
8030 | 0 | UINT64_C(0), |
8031 | 0 | UINT64_C(0), |
8032 | 0 | UINT64_C(0), |
8033 | 0 | UINT64_C(0), |
8034 | 0 | UINT64_C(0), |
8035 | 0 | UINT64_C(0), |
8036 | 0 | UINT64_C(0), |
8037 | 0 | UINT64_C(0), |
8038 | 0 | UINT64_C(0), |
8039 | 0 | UINT64_C(0), |
8040 | 0 | UINT64_C(0), |
8041 | 0 | UINT64_C(0), |
8042 | 0 | UINT64_C(0), |
8043 | 0 | UINT64_C(0), |
8044 | 0 | UINT64_C(0), |
8045 | 0 | UINT64_C(0), |
8046 | 0 | UINT64_C(0), |
8047 | 0 | UINT64_C(0), |
8048 | 0 | UINT64_C(0), |
8049 | 0 | UINT64_C(0), |
8050 | 0 | UINT64_C(0), |
8051 | 0 | UINT64_C(0), |
8052 | 0 | UINT64_C(0), |
8053 | 0 | UINT64_C(0), |
8054 | 0 | UINT64_C(0), |
8055 | 0 | UINT64_C(0), |
8056 | 0 | UINT64_C(0), |
8057 | 0 | UINT64_C(0), |
8058 | 0 | UINT64_C(0), |
8059 | 0 | UINT64_C(0), |
8060 | 0 | UINT64_C(0), |
8061 | 0 | UINT64_C(0), |
8062 | 0 | UINT64_C(0), |
8063 | 0 | UINT64_C(0), |
8064 | 0 | UINT64_C(0), |
8065 | 0 | UINT64_C(0), |
8066 | 0 | UINT64_C(0), |
8067 | 0 | UINT64_C(0), |
8068 | 0 | UINT64_C(0), |
8069 | 0 | UINT64_C(0), |
8070 | 0 | UINT64_C(0), |
8071 | 0 | UINT64_C(0), |
8072 | 0 | UINT64_C(0), |
8073 | 0 | UINT64_C(0), |
8074 | 0 | UINT64_C(0), |
8075 | 0 | UINT64_C(0), |
8076 | 0 | UINT64_C(0), |
8077 | 0 | UINT64_C(0), |
8078 | 0 | UINT64_C(0), |
8079 | 0 | UINT64_C(0), |
8080 | 0 | UINT64_C(0), |
8081 | 0 | UINT64_C(0), |
8082 | 0 | UINT64_C(0), |
8083 | 0 | UINT64_C(0), |
8084 | 0 | UINT64_C(0), |
8085 | 0 | UINT64_C(0), |
8086 | 0 | UINT64_C(0), |
8087 | 0 | UINT64_C(0), |
8088 | 0 | UINT64_C(0), |
8089 | 0 | UINT64_C(0), |
8090 | 0 | UINT64_C(0), |
8091 | 0 | UINT64_C(0), |
8092 | 0 | UINT64_C(0), |
8093 | 0 | UINT64_C(0), |
8094 | 0 | UINT64_C(0), |
8095 | 0 | UINT64_C(0), |
8096 | 0 | UINT64_C(0), |
8097 | 0 | UINT64_C(0), |
8098 | 0 | UINT64_C(0), |
8099 | 0 | UINT64_C(0), |
8100 | 0 | UINT64_C(0), |
8101 | 0 | UINT64_C(0), |
8102 | 0 | UINT64_C(0), |
8103 | 0 | UINT64_C(0), |
8104 | 0 | UINT64_C(0), |
8105 | 0 | UINT64_C(0), |
8106 | 0 | UINT64_C(0), |
8107 | 0 | UINT64_C(0), |
8108 | 0 | UINT64_C(0), |
8109 | 0 | UINT64_C(0), |
8110 | 0 | UINT64_C(0), |
8111 | 0 | UINT64_C(0), |
8112 | 0 | UINT64_C(0), |
8113 | 0 | UINT64_C(0), |
8114 | 0 | UINT64_C(0), |
8115 | 0 | UINT64_C(0), |
8116 | 0 | UINT64_C(0), |
8117 | 0 | UINT64_C(0), |
8118 | 0 | UINT64_C(0), |
8119 | 0 | UINT64_C(0), |
8120 | 0 | UINT64_C(0), |
8121 | 0 | UINT64_C(0), |
8122 | 0 | UINT64_C(0), |
8123 | 0 | UINT64_C(0), |
8124 | 0 | UINT64_C(0), |
8125 | 0 | UINT64_C(0), |
8126 | 0 | UINT64_C(0), |
8127 | 0 | UINT64_C(0), |
8128 | 0 | UINT64_C(0), |
8129 | 0 | UINT64_C(0), |
8130 | 0 | UINT64_C(0), |
8131 | 0 | UINT64_C(0), |
8132 | 0 | UINT64_C(0), |
8133 | 0 | UINT64_C(0), |
8134 | 0 | UINT64_C(0), |
8135 | 0 | UINT64_C(0), |
8136 | 0 | UINT64_C(0), |
8137 | 0 | UINT64_C(0), |
8138 | 0 | UINT64_C(0), |
8139 | 0 | UINT64_C(0), |
8140 | 0 | UINT64_C(0), |
8141 | 0 | UINT64_C(0), |
8142 | 0 | UINT64_C(0), |
8143 | 0 | UINT64_C(0), |
8144 | 0 | UINT64_C(0), |
8145 | 0 | UINT64_C(0), |
8146 | 0 | UINT64_C(0), |
8147 | 0 | UINT64_C(0), |
8148 | 0 | UINT64_C(0), |
8149 | 0 | UINT64_C(0), |
8150 | 0 | UINT64_C(0), |
8151 | 0 | UINT64_C(0), |
8152 | 0 | UINT64_C(0), |
8153 | 0 | UINT64_C(0), |
8154 | 0 | UINT64_C(0), |
8155 | 0 | UINT64_C(0), |
8156 | 0 | UINT64_C(0), |
8157 | 0 | UINT64_C(0), |
8158 | 0 | UINT64_C(0), |
8159 | 0 | UINT64_C(0), |
8160 | 0 | UINT64_C(0), |
8161 | 0 | UINT64_C(0), |
8162 | 0 | UINT64_C(0), |
8163 | 0 | UINT64_C(0), |
8164 | 0 | UINT64_C(0), |
8165 | 0 | UINT64_C(0), |
8166 | 0 | UINT64_C(0), |
8167 | 0 | UINT64_C(0), |
8168 | 0 | UINT64_C(0), |
8169 | 0 | UINT64_C(0), |
8170 | 0 | UINT64_C(0), |
8171 | 0 | UINT64_C(0), |
8172 | 0 | UINT64_C(0), |
8173 | 0 | UINT64_C(0), |
8174 | 0 | UINT64_C(0), |
8175 | 0 | UINT64_C(0), |
8176 | 0 | UINT64_C(0), |
8177 | 0 | UINT64_C(0), |
8178 | 0 | UINT64_C(0), |
8179 | 0 | UINT64_C(0), |
8180 | 0 | UINT64_C(0), |
8181 | 0 | UINT64_C(0), |
8182 | 0 | UINT64_C(0), |
8183 | 0 | UINT64_C(0), |
8184 | 0 | UINT64_C(0), |
8185 | 0 | UINT64_C(0), |
8186 | 0 | UINT64_C(0), |
8187 | 0 | UINT64_C(0), |
8188 | 0 | UINT64_C(0), |
8189 | 0 | UINT64_C(0), |
8190 | 0 | UINT64_C(0), |
8191 | 0 | UINT64_C(0), |
8192 | 0 | UINT64_C(0), |
8193 | 0 | UINT64_C(0), |
8194 | 0 | UINT64_C(0), |
8195 | 0 | UINT64_C(0), |
8196 | 0 | UINT64_C(0), |
8197 | 0 | UINT64_C(0), |
8198 | 0 | UINT64_C(0), |
8199 | 0 | UINT64_C(0), |
8200 | 0 | UINT64_C(0), |
8201 | 0 | UINT64_C(0), |
8202 | 0 | UINT64_C(0), |
8203 | 0 | UINT64_C(0), |
8204 | 0 | UINT64_C(0), |
8205 | 0 | UINT64_C(0), |
8206 | 0 | UINT64_C(0), |
8207 | 0 | UINT64_C(0), |
8208 | 0 | UINT64_C(0), |
8209 | 0 | UINT64_C(0), |
8210 | 0 | UINT64_C(0), |
8211 | 0 | UINT64_C(0), |
8212 | 0 | UINT64_C(0), |
8213 | 0 | UINT64_C(0), |
8214 | 0 | UINT64_C(0), |
8215 | 0 | UINT64_C(0), |
8216 | 0 | UINT64_C(0), |
8217 | 0 | UINT64_C(0), |
8218 | 0 | UINT64_C(0), |
8219 | 0 | UINT64_C(0), |
8220 | 0 | UINT64_C(0), |
8221 | 0 | UINT64_C(0), |
8222 | 0 | UINT64_C(0), |
8223 | 0 | UINT64_C(0), |
8224 | 0 | UINT64_C(0), |
8225 | 0 | UINT64_C(0), |
8226 | 0 | UINT64_C(0), |
8227 | 0 | UINT64_C(0), |
8228 | 0 | UINT64_C(0), |
8229 | 0 | UINT64_C(0), |
8230 | 0 | UINT64_C(0), |
8231 | 0 | UINT64_C(0), |
8232 | 0 | UINT64_C(0), |
8233 | 0 | UINT64_C(0), |
8234 | 0 | UINT64_C(0), |
8235 | 0 | UINT64_C(0), |
8236 | 0 | UINT64_C(0), |
8237 | 0 | UINT64_C(0), |
8238 | 0 | UINT64_C(0), |
8239 | 0 | UINT64_C(0), |
8240 | 0 | UINT64_C(0), |
8241 | 0 | UINT64_C(0), |
8242 | 0 | UINT64_C(0), |
8243 | 0 | UINT64_C(0), |
8244 | 0 | UINT64_C(0), |
8245 | 0 | UINT64_C(0), |
8246 | 0 | UINT64_C(0), |
8247 | 0 | UINT64_C(0), |
8248 | 0 | UINT64_C(0), |
8249 | 0 | UINT64_C(0), |
8250 | 0 | UINT64_C(0), |
8251 | 0 | UINT64_C(0), |
8252 | 0 | UINT64_C(0), |
8253 | 0 | UINT64_C(0), |
8254 | 0 | UINT64_C(0), |
8255 | 0 | UINT64_C(0), |
8256 | 0 | UINT64_C(0), |
8257 | 0 | UINT64_C(0), |
8258 | 0 | UINT64_C(0), |
8259 | 0 | UINT64_C(0), |
8260 | 0 | UINT64_C(0), |
8261 | 0 | UINT64_C(0), |
8262 | 0 | UINT64_C(0), |
8263 | 0 | UINT64_C(0), |
8264 | 0 | UINT64_C(0), |
8265 | 0 | UINT64_C(0), |
8266 | 0 | UINT64_C(0), |
8267 | 0 | UINT64_C(0), |
8268 | 0 | UINT64_C(0), |
8269 | 0 | UINT64_C(0), |
8270 | 0 | UINT64_C(0), |
8271 | 0 | UINT64_C(0), |
8272 | 0 | UINT64_C(0), |
8273 | 0 | UINT64_C(0), |
8274 | 0 | UINT64_C(0), |
8275 | 0 | UINT64_C(0), |
8276 | 0 | UINT64_C(0), |
8277 | 0 | UINT64_C(0), |
8278 | 0 | UINT64_C(0), |
8279 | 0 | UINT64_C(0), |
8280 | 0 | UINT64_C(0), |
8281 | 0 | UINT64_C(0), |
8282 | 0 | UINT64_C(0), |
8283 | 0 | UINT64_C(0), |
8284 | 0 | UINT64_C(0), |
8285 | 0 | UINT64_C(0), |
8286 | 0 | UINT64_C(0), |
8287 | 0 | UINT64_C(0), |
8288 | 0 | UINT64_C(0), |
8289 | 0 | UINT64_C(0), |
8290 | 0 | UINT64_C(0), |
8291 | 0 | UINT64_C(0), |
8292 | 0 | UINT64_C(0), |
8293 | 0 | UINT64_C(0), |
8294 | 0 | UINT64_C(0), |
8295 | 0 | UINT64_C(0), |
8296 | 0 | UINT64_C(0), |
8297 | 0 | UINT64_C(0), |
8298 | 0 | UINT64_C(0), |
8299 | 0 | UINT64_C(0), |
8300 | 0 | UINT64_C(0), |
8301 | 0 | UINT64_C(0), |
8302 | 0 | UINT64_C(0), |
8303 | 0 | UINT64_C(0), |
8304 | 0 | UINT64_C(0), |
8305 | 0 | UINT64_C(0), |
8306 | 0 | UINT64_C(0), |
8307 | 0 | UINT64_C(0), |
8308 | 0 | UINT64_C(0), |
8309 | 0 | UINT64_C(0), |
8310 | 0 | UINT64_C(0), |
8311 | 0 | UINT64_C(0), |
8312 | 0 | UINT64_C(0), |
8313 | 0 | UINT64_C(0), |
8314 | 0 | UINT64_C(0), |
8315 | 0 | UINT64_C(0), |
8316 | 0 | UINT64_C(0), |
8317 | 0 | UINT64_C(0), |
8318 | 0 | UINT64_C(0), |
8319 | 0 | UINT64_C(0), |
8320 | 0 | UINT64_C(0), |
8321 | 0 | UINT64_C(0), |
8322 | 0 | UINT64_C(0), |
8323 | 0 | UINT64_C(0), |
8324 | 0 | UINT64_C(0), |
8325 | 0 | UINT64_C(0), |
8326 | 0 | UINT64_C(0), |
8327 | 0 | UINT64_C(0), |
8328 | 0 | UINT64_C(0), |
8329 | 0 | UINT64_C(0), |
8330 | 0 | UINT64_C(0), |
8331 | 0 | UINT64_C(0), |
8332 | 0 | UINT64_C(0), |
8333 | 0 | UINT64_C(0), |
8334 | 0 | UINT64_C(0), |
8335 | 0 | UINT64_C(0), |
8336 | 0 | UINT64_C(0), |
8337 | 0 | UINT64_C(0), |
8338 | 0 | UINT64_C(0), |
8339 | 0 | UINT64_C(0), |
8340 | 0 | UINT64_C(0), |
8341 | 0 | UINT64_C(0), |
8342 | 0 | UINT64_C(0), |
8343 | 0 | UINT64_C(0), |
8344 | 0 | UINT64_C(0), |
8345 | 0 | UINT64_C(0), |
8346 | 0 | UINT64_C(0), |
8347 | 0 | UINT64_C(0), |
8348 | 0 | UINT64_C(0), |
8349 | 0 | UINT64_C(0), |
8350 | 0 | UINT64_C(0), |
8351 | 0 | UINT64_C(0), |
8352 | 0 | UINT64_C(0), |
8353 | 0 | UINT64_C(0), |
8354 | 0 | UINT64_C(0), |
8355 | 0 | UINT64_C(0), |
8356 | 0 | UINT64_C(0), |
8357 | 0 | UINT64_C(0), |
8358 | 0 | UINT64_C(0), |
8359 | 0 | UINT64_C(0), |
8360 | 0 | UINT64_C(0), |
8361 | 0 | UINT64_C(0), |
8362 | 0 | UINT64_C(0), |
8363 | 0 | UINT64_C(0), |
8364 | 0 | UINT64_C(0), |
8365 | 0 | UINT64_C(0), |
8366 | 0 | UINT64_C(0), |
8367 | 0 | UINT64_C(0), |
8368 | 0 | UINT64_C(0), |
8369 | 0 | UINT64_C(0), |
8370 | 0 | UINT64_C(0), |
8371 | 0 | UINT64_C(0), |
8372 | 0 | UINT64_C(0), |
8373 | 0 | UINT64_C(0), |
8374 | 0 | UINT64_C(0), |
8375 | 0 | UINT64_C(0), |
8376 | 0 | UINT64_C(0), |
8377 | 0 | UINT64_C(0), |
8378 | 0 | UINT64_C(0), |
8379 | 0 | UINT64_C(0), |
8380 | 0 | UINT64_C(0), |
8381 | 0 | UINT64_C(0), |
8382 | 0 | UINT64_C(0), |
8383 | 0 | UINT64_C(0), |
8384 | 0 | UINT64_C(0), |
8385 | 0 | UINT64_C(0), |
8386 | 0 | UINT64_C(0), |
8387 | 0 | UINT64_C(0), |
8388 | 0 | UINT64_C(0), |
8389 | 0 | UINT64_C(0), |
8390 | 0 | UINT64_C(0), |
8391 | 0 | UINT64_C(0), |
8392 | 0 | UINT64_C(0), |
8393 | 0 | UINT64_C(0), |
8394 | 0 | UINT64_C(0), |
8395 | 0 | UINT64_C(0), |
8396 | 0 | UINT64_C(0), |
8397 | 0 | UINT64_C(0), |
8398 | 0 | UINT64_C(0), |
8399 | 0 | UINT64_C(0), |
8400 | 0 | UINT64_C(0), |
8401 | 0 | UINT64_C(0), |
8402 | 0 | UINT64_C(0), |
8403 | 0 | UINT64_C(0), |
8404 | 0 | UINT64_C(0), |
8405 | 0 | UINT64_C(0), |
8406 | 0 | UINT64_C(0), |
8407 | 0 | UINT64_C(0), |
8408 | 0 | UINT64_C(0), |
8409 | 0 | UINT64_C(0), |
8410 | 0 | UINT64_C(0), |
8411 | 0 | UINT64_C(0), |
8412 | 0 | UINT64_C(0), |
8413 | 0 | UINT64_C(0), |
8414 | 0 | UINT64_C(0), |
8415 | 0 | UINT64_C(0), |
8416 | 0 | UINT64_C(0), |
8417 | 0 | UINT64_C(0), |
8418 | 0 | UINT64_C(0), |
8419 | 0 | UINT64_C(0), |
8420 | 0 | UINT64_C(0), |
8421 | 0 | UINT64_C(0), |
8422 | 0 | UINT64_C(0), |
8423 | 0 | UINT64_C(0), |
8424 | 0 | UINT64_C(0), |
8425 | 0 | UINT64_C(0), |
8426 | 0 | UINT64_C(0), |
8427 | 0 | UINT64_C(0), |
8428 | 0 | UINT64_C(0), |
8429 | 0 | UINT64_C(0), |
8430 | 0 | UINT64_C(0), |
8431 | 0 | UINT64_C(0), |
8432 | 0 | UINT64_C(0), |
8433 | 0 | UINT64_C(0), |
8434 | 0 | UINT64_C(0), |
8435 | 0 | UINT64_C(0), |
8436 | 0 | UINT64_C(0), |
8437 | 0 | UINT64_C(0), |
8438 | 0 | UINT64_C(0), |
8439 | 0 | UINT64_C(0), |
8440 | 0 | UINT64_C(0), |
8441 | 0 | UINT64_C(0), |
8442 | 0 | UINT64_C(0), |
8443 | 0 | UINT64_C(0), |
8444 | 0 | UINT64_C(0), |
8445 | 0 | UINT64_C(0), |
8446 | 0 | UINT64_C(0), |
8447 | 0 | UINT64_C(0), |
8448 | 0 | UINT64_C(0), |
8449 | 0 | UINT64_C(0), |
8450 | 0 | UINT64_C(0), |
8451 | 0 | UINT64_C(0), |
8452 | 0 | UINT64_C(0), |
8453 | 0 | UINT64_C(0), |
8454 | 0 | UINT64_C(0), |
8455 | 0 | UINT64_C(0), |
8456 | 0 | UINT64_C(0), |
8457 | 0 | UINT64_C(0), |
8458 | 0 | UINT64_C(0), |
8459 | 0 | UINT64_C(0), |
8460 | 0 | UINT64_C(0), |
8461 | 0 | UINT64_C(0), |
8462 | 0 | UINT64_C(0), |
8463 | 0 | UINT64_C(0), |
8464 | 0 | UINT64_C(0), |
8465 | 0 | UINT64_C(0), |
8466 | 0 | UINT64_C(0), |
8467 | 0 | UINT64_C(0), |
8468 | 0 | UINT64_C(0), |
8469 | 0 | UINT64_C(0), |
8470 | 0 | UINT64_C(0), |
8471 | 0 | UINT64_C(0), |
8472 | 0 | UINT64_C(0), |
8473 | 0 | UINT64_C(0), |
8474 | 0 | UINT64_C(0), |
8475 | 0 | UINT64_C(0), |
8476 | 0 | UINT64_C(0), |
8477 | 0 | UINT64_C(0), |
8478 | 0 | UINT64_C(0), |
8479 | 0 | UINT64_C(0), |
8480 | 0 | UINT64_C(0), |
8481 | 0 | UINT64_C(0), |
8482 | 0 | UINT64_C(0), |
8483 | 0 | UINT64_C(0), |
8484 | 0 | UINT64_C(0), |
8485 | 0 | UINT64_C(0), |
8486 | 0 | UINT64_C(0), |
8487 | 0 | UINT64_C(0), |
8488 | 0 | UINT64_C(0), |
8489 | 0 | UINT64_C(0), |
8490 | 0 | UINT64_C(0), |
8491 | 0 | UINT64_C(0), |
8492 | 0 | UINT64_C(0), |
8493 | 0 | UINT64_C(0), |
8494 | 0 | UINT64_C(0), |
8495 | 0 | UINT64_C(0), |
8496 | 0 | UINT64_C(0), |
8497 | 0 | UINT64_C(0), |
8498 | 0 | UINT64_C(0), |
8499 | 0 | UINT64_C(0), |
8500 | 0 | UINT64_C(0), |
8501 | 0 | UINT64_C(0), |
8502 | 0 | UINT64_C(0), |
8503 | 0 | UINT64_C(0), |
8504 | 0 | UINT64_C(0), |
8505 | 0 | UINT64_C(0), |
8506 | 0 | UINT64_C(0), |
8507 | 0 | UINT64_C(0), |
8508 | 0 | UINT64_C(0), |
8509 | 0 | UINT64_C(0), |
8510 | 0 | UINT64_C(0), |
8511 | 0 | UINT64_C(0), |
8512 | 0 | UINT64_C(0), |
8513 | 0 | UINT64_C(0), |
8514 | 0 | UINT64_C(0), |
8515 | 0 | UINT64_C(0), |
8516 | 0 | UINT64_C(0), |
8517 | 0 | UINT64_C(0), |
8518 | 0 | UINT64_C(0), |
8519 | 0 | UINT64_C(0), |
8520 | 0 | UINT64_C(0), |
8521 | 0 | UINT64_C(0), |
8522 | 0 | UINT64_C(0), |
8523 | 0 | UINT64_C(0), |
8524 | 0 | UINT64_C(0), |
8525 | 0 | UINT64_C(0), |
8526 | 0 | UINT64_C(0), |
8527 | 0 | UINT64_C(0), |
8528 | 0 | UINT64_C(0), |
8529 | 0 | UINT64_C(0), |
8530 | 0 | UINT64_C(0), |
8531 | 0 | UINT64_C(0), |
8532 | 0 | UINT64_C(0), |
8533 | 0 | UINT64_C(0), |
8534 | 0 | UINT64_C(0), |
8535 | 0 | UINT64_C(0), |
8536 | 0 | UINT64_C(0), |
8537 | 0 | UINT64_C(0), |
8538 | 0 | UINT64_C(0), |
8539 | 0 | UINT64_C(0), |
8540 | 0 | UINT64_C(0), |
8541 | 0 | UINT64_C(0), |
8542 | 0 | UINT64_C(0), |
8543 | 0 | UINT64_C(0), |
8544 | 0 | UINT64_C(0), |
8545 | 0 | UINT64_C(0), |
8546 | 0 | UINT64_C(0), |
8547 | 0 | UINT64_C(0), |
8548 | 0 | UINT64_C(0), |
8549 | 0 | UINT64_C(0), |
8550 | 0 | UINT64_C(0), |
8551 | 0 | UINT64_C(0), |
8552 | 0 | UINT64_C(0), |
8553 | 0 | UINT64_C(0), |
8554 | 0 | UINT64_C(0), |
8555 | 0 | UINT64_C(0), |
8556 | 0 | UINT64_C(0), |
8557 | 0 | UINT64_C(0), |
8558 | 0 | UINT64_C(0), |
8559 | 0 | UINT64_C(0), |
8560 | 0 | UINT64_C(0), |
8561 | 0 | UINT64_C(0), |
8562 | 0 | UINT64_C(0), |
8563 | 0 | UINT64_C(0), |
8564 | 0 | UINT64_C(0), |
8565 | 0 | UINT64_C(0), |
8566 | 0 | UINT64_C(0), |
8567 | 0 | UINT64_C(0), |
8568 | 0 | UINT64_C(0), |
8569 | 0 | UINT64_C(0), |
8570 | 0 | UINT64_C(0), |
8571 | 0 | UINT64_C(0), |
8572 | 0 | UINT64_C(0), |
8573 | 0 | UINT64_C(0), |
8574 | 0 | UINT64_C(0), |
8575 | 0 | UINT64_C(0), |
8576 | 0 | UINT64_C(0), |
8577 | 0 | UINT64_C(0), |
8578 | 0 | UINT64_C(0), |
8579 | 0 | UINT64_C(0), |
8580 | 0 | UINT64_C(0), |
8581 | 0 | UINT64_C(0), |
8582 | 0 | UINT64_C(0), |
8583 | 0 | UINT64_C(0), |
8584 | 0 | UINT64_C(0), |
8585 | 0 | UINT64_C(0), |
8586 | 0 | UINT64_C(0), |
8587 | 0 | UINT64_C(0), |
8588 | 0 | UINT64_C(0), |
8589 | 0 | UINT64_C(0), |
8590 | 0 | UINT64_C(0), |
8591 | 0 | UINT64_C(0), |
8592 | 0 | UINT64_C(0), |
8593 | 0 | UINT64_C(0), |
8594 | 0 | UINT64_C(0), |
8595 | 0 | UINT64_C(0), |
8596 | 0 | UINT64_C(0), |
8597 | 0 | UINT64_C(0), |
8598 | 0 | UINT64_C(0), |
8599 | 0 | UINT64_C(0), |
8600 | 0 | UINT64_C(0), |
8601 | 0 | UINT64_C(0), |
8602 | 0 | UINT64_C(0), |
8603 | 0 | UINT64_C(0), |
8604 | 0 | UINT64_C(0), |
8605 | 0 | UINT64_C(0), |
8606 | 0 | UINT64_C(0), |
8607 | 0 | UINT64_C(0), |
8608 | 0 | UINT64_C(0), |
8609 | 0 | UINT64_C(0), |
8610 | 0 | UINT64_C(0), |
8611 | 0 | UINT64_C(0), |
8612 | 0 | UINT64_C(0), |
8613 | 0 | UINT64_C(0), |
8614 | 0 | UINT64_C(0), |
8615 | 0 | UINT64_C(0), |
8616 | 0 | UINT64_C(0), |
8617 | 0 | UINT64_C(0), |
8618 | 0 | UINT64_C(0), |
8619 | 0 | UINT64_C(0), |
8620 | 0 | UINT64_C(0), |
8621 | 0 | UINT64_C(0), |
8622 | 0 | UINT64_C(0), |
8623 | 0 | UINT64_C(0), |
8624 | 0 | UINT64_C(0), |
8625 | 0 | UINT64_C(0), |
8626 | 0 | UINT64_C(0), |
8627 | 0 | UINT64_C(0), |
8628 | 0 | UINT64_C(0), |
8629 | 0 | UINT64_C(0), |
8630 | 0 | UINT64_C(0), |
8631 | 0 | UINT64_C(0), |
8632 | 0 | UINT64_C(0), |
8633 | 0 | UINT64_C(0), |
8634 | 0 | UINT64_C(0), |
8635 | 0 | UINT64_C(0), |
8636 | 0 | UINT64_C(0), |
8637 | 0 | UINT64_C(0), |
8638 | 0 | UINT64_C(0), |
8639 | 0 | UINT64_C(0), |
8640 | 0 | UINT64_C(0), |
8641 | 0 | UINT64_C(0), |
8642 | 0 | UINT64_C(0), |
8643 | 0 | UINT64_C(0), |
8644 | 0 | UINT64_C(0), |
8645 | 0 | UINT64_C(0), |
8646 | 0 | UINT64_C(0), |
8647 | 0 | UINT64_C(0), |
8648 | 0 | UINT64_C(0), |
8649 | 0 | UINT64_C(0), |
8650 | 0 | UINT64_C(0), |
8651 | 0 | UINT64_C(0), |
8652 | 0 | UINT64_C(0), |
8653 | 0 | UINT64_C(0), |
8654 | 0 | UINT64_C(0), |
8655 | 0 | UINT64_C(0), |
8656 | 0 | UINT64_C(0), |
8657 | 0 | UINT64_C(0), |
8658 | 0 | UINT64_C(0), |
8659 | 0 | UINT64_C(0), |
8660 | 0 | UINT64_C(0), |
8661 | 0 | UINT64_C(0), |
8662 | 0 | UINT64_C(0), |
8663 | 0 | UINT64_C(0), |
8664 | 0 | UINT64_C(0), |
8665 | 0 | UINT64_C(0), |
8666 | 0 | UINT64_C(0), |
8667 | 0 | UINT64_C(0), |
8668 | 0 | UINT64_C(0), |
8669 | 0 | UINT64_C(0), |
8670 | 0 | UINT64_C(0), |
8671 | 0 | UINT64_C(0), |
8672 | 0 | UINT64_C(0), |
8673 | 0 | UINT64_C(0), |
8674 | 0 | UINT64_C(0), |
8675 | 0 | UINT64_C(0), |
8676 | 0 | UINT64_C(0), |
8677 | 0 | UINT64_C(0), |
8678 | 0 | UINT64_C(0), |
8679 | 0 | UINT64_C(0), |
8680 | 0 | UINT64_C(0), |
8681 | 0 | UINT64_C(0), |
8682 | 0 | UINT64_C(0), |
8683 | 0 | UINT64_C(0), |
8684 | 0 | UINT64_C(0), |
8685 | 0 | UINT64_C(0), |
8686 | 0 | UINT64_C(0), |
8687 | 0 | UINT64_C(0), |
8688 | 0 | UINT64_C(0), |
8689 | 0 | UINT64_C(0), |
8690 | 0 | UINT64_C(0), |
8691 | 0 | UINT64_C(0), |
8692 | 0 | UINT64_C(0), |
8693 | 0 | UINT64_C(0), |
8694 | 0 | UINT64_C(0), |
8695 | 0 | UINT64_C(0), |
8696 | 0 | UINT64_C(0), |
8697 | 0 | UINT64_C(0), |
8698 | 0 | UINT64_C(0), |
8699 | 0 | UINT64_C(0), |
8700 | 0 | UINT64_C(0), |
8701 | 0 | UINT64_C(0), |
8702 | 0 | UINT64_C(0), |
8703 | 0 | UINT64_C(0), |
8704 | 0 | UINT64_C(0), |
8705 | 0 | UINT64_C(0), |
8706 | 0 | UINT64_C(0), |
8707 | 0 | UINT64_C(0), |
8708 | 0 | UINT64_C(0), |
8709 | 0 | UINT64_C(0), |
8710 | 0 | UINT64_C(0), |
8711 | 0 | UINT64_C(0), |
8712 | 0 | UINT64_C(0), |
8713 | 0 | UINT64_C(0), |
8714 | 0 | UINT64_C(0), |
8715 | 0 | UINT64_C(0), |
8716 | 0 | UINT64_C(0), |
8717 | 0 | UINT64_C(0), |
8718 | 0 | UINT64_C(0), |
8719 | 0 | UINT64_C(0), |
8720 | 0 | UINT64_C(0), |
8721 | 0 | UINT64_C(0), |
8722 | 0 | UINT64_C(0), |
8723 | 0 | UINT64_C(0), |
8724 | 0 | UINT64_C(0), |
8725 | 0 | UINT64_C(0), |
8726 | 0 | UINT64_C(0), |
8727 | 0 | UINT64_C(0), |
8728 | 0 | UINT64_C(0), |
8729 | 0 | UINT64_C(0), |
8730 | 0 | UINT64_C(0), |
8731 | 0 | UINT64_C(0), |
8732 | 0 | UINT64_C(0), |
8733 | 0 | UINT64_C(0), |
8734 | 0 | UINT64_C(0), |
8735 | 0 | UINT64_C(0), |
8736 | 0 | UINT64_C(0), |
8737 | 0 | UINT64_C(0), |
8738 | 0 | UINT64_C(0), |
8739 | 0 | UINT64_C(0), |
8740 | 0 | UINT64_C(0), |
8741 | 0 | UINT64_C(0), |
8742 | 0 | UINT64_C(0), |
8743 | 0 | UINT64_C(0), |
8744 | 0 | UINT64_C(0), |
8745 | 0 | UINT64_C(0), |
8746 | 0 | UINT64_C(0), |
8747 | 0 | UINT64_C(0), |
8748 | 0 | UINT64_C(0), |
8749 | 0 | UINT64_C(0), |
8750 | 0 | UINT64_C(0), |
8751 | 0 | UINT64_C(0), |
8752 | 0 | UINT64_C(0), |
8753 | 0 | UINT64_C(0), |
8754 | 0 | UINT64_C(0), |
8755 | 0 | UINT64_C(0), |
8756 | 0 | UINT64_C(0), |
8757 | 0 | UINT64_C(0), |
8758 | 0 | UINT64_C(0), |
8759 | 0 | UINT64_C(0), |
8760 | 0 | UINT64_C(0), |
8761 | 0 | UINT64_C(0), |
8762 | 0 | UINT64_C(0), |
8763 | 0 | UINT64_C(0), |
8764 | 0 | UINT64_C(0), |
8765 | 0 | UINT64_C(0), |
8766 | 0 | UINT64_C(0), |
8767 | 0 | UINT64_C(0), |
8768 | 0 | UINT64_C(0), |
8769 | 0 | UINT64_C(0), |
8770 | 0 | UINT64_C(0), |
8771 | 0 | UINT64_C(0), |
8772 | 0 | UINT64_C(0), |
8773 | 0 | UINT64_C(0), |
8774 | 0 | UINT64_C(0), |
8775 | 0 | UINT64_C(0), |
8776 | 0 | UINT64_C(0), |
8777 | 0 | UINT64_C(0), |
8778 | 0 | UINT64_C(0), |
8779 | 0 | UINT64_C(0), |
8780 | 0 | UINT64_C(0), |
8781 | 0 | UINT64_C(0), |
8782 | 0 | UINT64_C(0), |
8783 | 0 | UINT64_C(0), |
8784 | 0 | UINT64_C(0), |
8785 | 0 | UINT64_C(0), |
8786 | 0 | UINT64_C(0), |
8787 | 0 | UINT64_C(0), |
8788 | 0 | UINT64_C(0), |
8789 | 0 | UINT64_C(0), |
8790 | 0 | UINT64_C(0), |
8791 | 0 | UINT64_C(0), |
8792 | 0 | UINT64_C(0), |
8793 | 0 | UINT64_C(0), |
8794 | 0 | UINT64_C(0), |
8795 | 0 | UINT64_C(0), |
8796 | 0 | UINT64_C(0), |
8797 | 0 | UINT64_C(0), |
8798 | 0 | UINT64_C(0), |
8799 | 0 | UINT64_C(0), |
8800 | 0 | UINT64_C(0), |
8801 | 0 | UINT64_C(0), |
8802 | 0 | UINT64_C(0), |
8803 | 0 | UINT64_C(0), |
8804 | 0 | UINT64_C(0), |
8805 | 0 | UINT64_C(0), |
8806 | 0 | UINT64_C(0), |
8807 | 0 | UINT64_C(0), |
8808 | 0 | UINT64_C(0), |
8809 | 0 | UINT64_C(0), |
8810 | 0 | UINT64_C(0), |
8811 | 0 | UINT64_C(0), |
8812 | 0 | UINT64_C(0), |
8813 | 0 | UINT64_C(0), |
8814 | 0 | UINT64_C(0), |
8815 | 0 | UINT64_C(0), |
8816 | 0 | UINT64_C(0), |
8817 | 0 | UINT64_C(0), |
8818 | 0 | UINT64_C(0), |
8819 | 0 | UINT64_C(0), |
8820 | 0 | UINT64_C(0), |
8821 | 0 | UINT64_C(0), |
8822 | 0 | UINT64_C(0), |
8823 | 0 | UINT64_C(0), |
8824 | 0 | UINT64_C(0), |
8825 | 0 | UINT64_C(0), |
8826 | 0 | UINT64_C(0), |
8827 | 0 | UINT64_C(0), |
8828 | 0 | UINT64_C(0), |
8829 | 0 | UINT64_C(0), |
8830 | 0 | UINT64_C(0), |
8831 | 0 | UINT64_C(0), |
8832 | 0 | UINT64_C(0), |
8833 | 0 | UINT64_C(0), |
8834 | 0 | UINT64_C(0), |
8835 | 0 | UINT64_C(0), |
8836 | 0 | UINT64_C(0), |
8837 | 0 | UINT64_C(0), |
8838 | 0 | UINT64_C(0), |
8839 | 0 | UINT64_C(0), |
8840 | 0 | UINT64_C(0), |
8841 | 0 | UINT64_C(0), |
8842 | 0 | UINT64_C(0), |
8843 | 0 | UINT64_C(0), |
8844 | 0 | UINT64_C(0), |
8845 | 0 | UINT64_C(0), |
8846 | 0 | UINT64_C(0), |
8847 | 0 | UINT64_C(0), |
8848 | 0 | UINT64_C(0), |
8849 | 0 | UINT64_C(0), |
8850 | 0 | UINT64_C(0), |
8851 | 0 | UINT64_C(0), |
8852 | 0 | UINT64_C(0), |
8853 | 0 | UINT64_C(0), |
8854 | 0 | UINT64_C(0), |
8855 | 0 | UINT64_C(0), |
8856 | 0 | UINT64_C(0), |
8857 | 0 | UINT64_C(0), |
8858 | 0 | UINT64_C(0), |
8859 | 0 | UINT64_C(0), |
8860 | 0 | UINT64_C(0), |
8861 | 0 | UINT64_C(0), |
8862 | 0 | UINT64_C(0), |
8863 | 0 | UINT64_C(0), |
8864 | 0 | UINT64_C(0), |
8865 | 0 | UINT64_C(0), |
8866 | 0 | UINT64_C(0), |
8867 | 0 | UINT64_C(0), |
8868 | 0 | UINT64_C(0), |
8869 | 0 | UINT64_C(0), |
8870 | 0 | UINT64_C(0), |
8871 | 0 | UINT64_C(0), |
8872 | 0 | UINT64_C(0), |
8873 | 0 | UINT64_C(0), |
8874 | 0 | UINT64_C(0), |
8875 | 0 | UINT64_C(0), |
8876 | 0 | UINT64_C(0), |
8877 | 0 | UINT64_C(0), |
8878 | 0 | UINT64_C(0), |
8879 | 0 | UINT64_C(0), |
8880 | 0 | UINT64_C(0), |
8881 | 0 | UINT64_C(0), |
8882 | 0 | UINT64_C(0), |
8883 | 0 | UINT64_C(0), |
8884 | 0 | UINT64_C(0), |
8885 | 0 | UINT64_C(0), |
8886 | 0 | UINT64_C(0), |
8887 | 0 | UINT64_C(0), |
8888 | 0 | UINT64_C(0), |
8889 | 0 | UINT64_C(0), |
8890 | 0 | UINT64_C(0), |
8891 | 0 | UINT64_C(0), |
8892 | 0 | UINT64_C(0), |
8893 | 0 | UINT64_C(0), |
8894 | 0 | UINT64_C(0), |
8895 | 0 | UINT64_C(0), |
8896 | 0 | UINT64_C(0), |
8897 | 0 | UINT64_C(0), |
8898 | 0 | UINT64_C(0), |
8899 | 0 | UINT64_C(0), |
8900 | 0 | UINT64_C(0), |
8901 | 0 | UINT64_C(0), |
8902 | 0 | UINT64_C(0), |
8903 | 0 | UINT64_C(0), |
8904 | 0 | UINT64_C(0), |
8905 | 0 | UINT64_C(0), |
8906 | 0 | UINT64_C(0), |
8907 | 0 | UINT64_C(0), |
8908 | 0 | UINT64_C(0), |
8909 | 0 | UINT64_C(0), |
8910 | 0 | UINT64_C(0), |
8911 | 0 | UINT64_C(0), |
8912 | 0 | UINT64_C(0), |
8913 | 0 | UINT64_C(0), |
8914 | 0 | UINT64_C(0), |
8915 | 0 | UINT64_C(0), |
8916 | 0 | UINT64_C(0), |
8917 | 0 | UINT64_C(0), |
8918 | 0 | UINT64_C(0), |
8919 | 0 | UINT64_C(0), |
8920 | 0 | UINT64_C(0), |
8921 | 0 | UINT64_C(0), |
8922 | 0 | UINT64_C(0), |
8923 | 0 | UINT64_C(0), |
8924 | 0 | UINT64_C(0), |
8925 | 0 | UINT64_C(0), |
8926 | 0 | UINT64_C(0), |
8927 | 0 | UINT64_C(0), |
8928 | 0 | UINT64_C(0), |
8929 | 0 | UINT64_C(0), |
8930 | 0 | UINT64_C(0), |
8931 | 0 | UINT64_C(0), |
8932 | 0 | UINT64_C(0), |
8933 | 0 | UINT64_C(0), |
8934 | 0 | UINT64_C(0), |
8935 | 0 | UINT64_C(0), |
8936 | 0 | UINT64_C(0), |
8937 | 0 | UINT64_C(0), |
8938 | 0 | UINT64_C(0), |
8939 | 0 | UINT64_C(0), |
8940 | 0 | UINT64_C(0), |
8941 | 0 | UINT64_C(0), |
8942 | 0 | UINT64_C(0), |
8943 | 0 | UINT64_C(0), |
8944 | 0 | UINT64_C(0), |
8945 | 0 | UINT64_C(0), |
8946 | 0 | UINT64_C(0), |
8947 | 0 | UINT64_C(0), |
8948 | 0 | UINT64_C(0), |
8949 | 0 | UINT64_C(0), |
8950 | 0 | UINT64_C(0), |
8951 | 0 | UINT64_C(0), |
8952 | 0 | UINT64_C(0), |
8953 | 0 | UINT64_C(0), |
8954 | 0 | UINT64_C(0), |
8955 | 0 | UINT64_C(0), |
8956 | 0 | UINT64_C(0), |
8957 | 0 | UINT64_C(0), |
8958 | 0 | UINT64_C(0), |
8959 | 0 | UINT64_C(0), |
8960 | 0 | UINT64_C(0), |
8961 | 0 | UINT64_C(0), |
8962 | 0 | UINT64_C(0), |
8963 | 0 | UINT64_C(0), |
8964 | 0 | UINT64_C(0), |
8965 | 0 | UINT64_C(0), |
8966 | 0 | UINT64_C(0), |
8967 | 0 | UINT64_C(0), |
8968 | 0 | UINT64_C(0), |
8969 | 0 | UINT64_C(0), |
8970 | 0 | UINT64_C(0), |
8971 | 0 | UINT64_C(0), |
8972 | 0 | UINT64_C(0), |
8973 | 0 | UINT64_C(0), |
8974 | 0 | UINT64_C(0), |
8975 | 0 | UINT64_C(0), |
8976 | 0 | UINT64_C(0), |
8977 | 0 | UINT64_C(0), |
8978 | 0 | UINT64_C(0), |
8979 | 0 | UINT64_C(0), |
8980 | 0 | UINT64_C(0), |
8981 | 0 | UINT64_C(0), |
8982 | 0 | UINT64_C(0), |
8983 | 0 | UINT64_C(0), |
8984 | 0 | UINT64_C(0), |
8985 | 0 | UINT64_C(0), |
8986 | 0 | UINT64_C(0), |
8987 | 0 | UINT64_C(0), |
8988 | 0 | UINT64_C(0), |
8989 | 0 | UINT64_C(0), |
8990 | 0 | UINT64_C(0), |
8991 | 0 | UINT64_C(0), |
8992 | 0 | UINT64_C(0), |
8993 | 0 | UINT64_C(0), |
8994 | 0 | UINT64_C(0), |
8995 | 0 | UINT64_C(0), |
8996 | 0 | UINT64_C(0), |
8997 | 0 | UINT64_C(0), |
8998 | 0 | UINT64_C(0), |
8999 | 0 | UINT64_C(0), |
9000 | 0 | UINT64_C(0), |
9001 | 0 | UINT64_C(0), |
9002 | 0 | UINT64_C(0), |
9003 | 0 | UINT64_C(0), |
9004 | 0 | UINT64_C(0), |
9005 | 0 | UINT64_C(0), |
9006 | 0 | UINT64_C(0), |
9007 | 0 | UINT64_C(0), |
9008 | 0 | UINT64_C(0), |
9009 | 0 | UINT64_C(0), |
9010 | 0 | UINT64_C(0), |
9011 | 0 | UINT64_C(0), |
9012 | 0 | UINT64_C(0), |
9013 | 0 | UINT64_C(0), |
9014 | 0 | UINT64_C(0), |
9015 | 0 | UINT64_C(0), |
9016 | 0 | UINT64_C(0), |
9017 | 0 | UINT64_C(0), |
9018 | 0 | UINT64_C(0), |
9019 | 0 | UINT64_C(0), |
9020 | 0 | UINT64_C(0), |
9021 | 0 | UINT64_C(0), |
9022 | 0 | UINT64_C(0), |
9023 | 0 | UINT64_C(0), |
9024 | 0 | UINT64_C(0), |
9025 | 0 | UINT64_C(0), |
9026 | 0 | UINT64_C(0), |
9027 | 0 | UINT64_C(0), |
9028 | 0 | UINT64_C(0), |
9029 | 0 | UINT64_C(0), |
9030 | 0 | UINT64_C(0), |
9031 | 0 | UINT64_C(0), |
9032 | 0 | UINT64_C(0), |
9033 | 0 | UINT64_C(0), |
9034 | 0 | UINT64_C(0), |
9035 | 0 | UINT64_C(0), |
9036 | 0 | UINT64_C(0), |
9037 | 0 | UINT64_C(0), |
9038 | 0 | UINT64_C(0), |
9039 | 0 | UINT64_C(0), |
9040 | 0 | UINT64_C(0), |
9041 | 0 | UINT64_C(0), |
9042 | 0 | UINT64_C(0), |
9043 | 0 | UINT64_C(0), |
9044 | 0 | UINT64_C(0), |
9045 | 0 | UINT64_C(0), |
9046 | 0 | UINT64_C(0), |
9047 | 0 | UINT64_C(0), |
9048 | 0 | UINT64_C(0), |
9049 | 0 | UINT64_C(0), |
9050 | 0 | UINT64_C(0), |
9051 | 0 | UINT64_C(0), |
9052 | 0 | UINT64_C(0), |
9053 | 0 | UINT64_C(0), |
9054 | 0 | UINT64_C(0), |
9055 | 0 | UINT64_C(0), |
9056 | 0 | UINT64_C(0), |
9057 | 0 | UINT64_C(0), |
9058 | 0 | UINT64_C(0), |
9059 | 0 | UINT64_C(0), |
9060 | 0 | UINT64_C(0), |
9061 | 0 | UINT64_C(0), |
9062 | 0 | UINT64_C(0), |
9063 | 0 | UINT64_C(0), |
9064 | 0 | UINT64_C(0), |
9065 | 0 | UINT64_C(0), |
9066 | 0 | UINT64_C(0), |
9067 | 0 | UINT64_C(0), |
9068 | 0 | UINT64_C(0), |
9069 | 0 | UINT64_C(0), |
9070 | 0 | UINT64_C(0), |
9071 | 0 | UINT64_C(0), |
9072 | 0 | UINT64_C(0), |
9073 | 0 | UINT64_C(0), |
9074 | 0 | UINT64_C(0), |
9075 | 0 | UINT64_C(0), |
9076 | 0 | UINT64_C(0), |
9077 | 0 | UINT64_C(0), |
9078 | 0 | UINT64_C(0), |
9079 | 0 | UINT64_C(0), |
9080 | 0 | UINT64_C(0), |
9081 | 0 | UINT64_C(0), |
9082 | 0 | UINT64_C(0), |
9083 | 0 | UINT64_C(0), |
9084 | 0 | UINT64_C(0), |
9085 | 0 | UINT64_C(0), |
9086 | 0 | UINT64_C(0), |
9087 | 0 | UINT64_C(0), |
9088 | 0 | UINT64_C(0), |
9089 | 0 | UINT64_C(0), |
9090 | 0 | UINT64_C(0), |
9091 | 0 | UINT64_C(0), |
9092 | 0 | UINT64_C(0), |
9093 | 0 | UINT64_C(0), |
9094 | 0 | UINT64_C(0), |
9095 | 0 | UINT64_C(0), |
9096 | 0 | UINT64_C(0), |
9097 | 0 | UINT64_C(0), |
9098 | 0 | UINT64_C(0), |
9099 | 0 | UINT64_C(0), |
9100 | 0 | UINT64_C(0), |
9101 | 0 | UINT64_C(0), |
9102 | 0 | UINT64_C(0), |
9103 | 0 | UINT64_C(0), |
9104 | 0 | UINT64_C(0), |
9105 | 0 | UINT64_C(0), |
9106 | 0 | UINT64_C(0), |
9107 | 0 | UINT64_C(0), |
9108 | 0 | UINT64_C(0), |
9109 | 0 | UINT64_C(0), |
9110 | 0 | UINT64_C(0), |
9111 | 0 | UINT64_C(0), |
9112 | 0 | UINT64_C(0), |
9113 | 0 | UINT64_C(0), |
9114 | 0 | UINT64_C(0), |
9115 | 0 | UINT64_C(0), |
9116 | 0 | UINT64_C(0), |
9117 | 0 | UINT64_C(0), |
9118 | 0 | UINT64_C(0), |
9119 | 0 | UINT64_C(0), |
9120 | 0 | UINT64_C(0), |
9121 | 0 | UINT64_C(0), |
9122 | 0 | UINT64_C(0), |
9123 | 0 | UINT64_C(0), |
9124 | 0 | UINT64_C(0), |
9125 | 0 | UINT64_C(0), |
9126 | 0 | UINT64_C(0), |
9127 | 0 | UINT64_C(0), |
9128 | 0 | UINT64_C(0), |
9129 | 0 | UINT64_C(0), |
9130 | 0 | UINT64_C(0), |
9131 | 0 | UINT64_C(0), |
9132 | 0 | UINT64_C(0), |
9133 | 0 | UINT64_C(0), |
9134 | 0 | UINT64_C(0), |
9135 | 0 | UINT64_C(0), |
9136 | 0 | UINT64_C(0), |
9137 | 0 | UINT64_C(0), |
9138 | 0 | UINT64_C(0), |
9139 | 0 | UINT64_C(0), |
9140 | 0 | UINT64_C(0), |
9141 | 0 | UINT64_C(0), |
9142 | 0 | UINT64_C(0), |
9143 | 0 | UINT64_C(0), |
9144 | 0 | UINT64_C(0), |
9145 | 0 | UINT64_C(0), |
9146 | 0 | UINT64_C(0), |
9147 | 0 | UINT64_C(0), |
9148 | 0 | UINT64_C(0), |
9149 | 0 | UINT64_C(0), |
9150 | 0 | UINT64_C(0), |
9151 | 0 | UINT64_C(0), |
9152 | 0 | UINT64_C(0), |
9153 | 0 | UINT64_C(0), |
9154 | 0 | UINT64_C(0), |
9155 | 0 | UINT64_C(0), |
9156 | 0 | UINT64_C(0), |
9157 | 0 | UINT64_C(0), |
9158 | 0 | UINT64_C(0), |
9159 | 0 | UINT64_C(0), |
9160 | 0 | UINT64_C(0), |
9161 | 0 | UINT64_C(0), |
9162 | 0 | UINT64_C(0), |
9163 | 0 | UINT64_C(0), |
9164 | 0 | UINT64_C(0), |
9165 | 0 | UINT64_C(0), |
9166 | 0 | UINT64_C(0), |
9167 | 0 | UINT64_C(0), |
9168 | 0 | UINT64_C(0), |
9169 | 0 | UINT64_C(0), |
9170 | 0 | UINT64_C(0), |
9171 | 0 | UINT64_C(0), |
9172 | 0 | UINT64_C(0), |
9173 | 0 | UINT64_C(0), |
9174 | 0 | UINT64_C(0), |
9175 | 0 | UINT64_C(0), |
9176 | 0 | UINT64_C(0), |
9177 | 0 | UINT64_C(0), |
9178 | 0 | UINT64_C(0), |
9179 | 0 | UINT64_C(0), |
9180 | 0 | UINT64_C(0), |
9181 | 0 | UINT64_C(0), |
9182 | 0 | UINT64_C(0), |
9183 | 0 | UINT64_C(0), |
9184 | 0 | UINT64_C(0), |
9185 | 0 | UINT64_C(0), |
9186 | 0 | UINT64_C(0), |
9187 | 0 | UINT64_C(0), |
9188 | 0 | UINT64_C(0), |
9189 | 0 | UINT64_C(0), |
9190 | 0 | UINT64_C(0), |
9191 | 0 | UINT64_C(0), |
9192 | 0 | UINT64_C(0), |
9193 | 0 | UINT64_C(0), |
9194 | 0 | UINT64_C(0), |
9195 | 0 | UINT64_C(0), |
9196 | 0 | UINT64_C(0), |
9197 | 0 | UINT64_C(0), |
9198 | 0 | UINT64_C(0), |
9199 | 0 | UINT64_C(0), |
9200 | 0 | UINT64_C(0), |
9201 | 0 | UINT64_C(0), |
9202 | 0 | UINT64_C(0), |
9203 | 0 | UINT64_C(0), |
9204 | 0 | UINT64_C(0), |
9205 | 0 | UINT64_C(0), |
9206 | 0 | UINT64_C(0), |
9207 | 0 | UINT64_C(0), |
9208 | 0 | UINT64_C(0), |
9209 | 0 | UINT64_C(0), |
9210 | 0 | UINT64_C(0), |
9211 | 0 | UINT64_C(0), |
9212 | 0 | UINT64_C(0), |
9213 | 0 | UINT64_C(0), |
9214 | 0 | UINT64_C(0), |
9215 | 0 | UINT64_C(0), |
9216 | 0 | UINT64_C(0), |
9217 | 0 | UINT64_C(0), |
9218 | 0 | UINT64_C(0), |
9219 | 0 | UINT64_C(0), |
9220 | 0 | UINT64_C(0), |
9221 | 0 | UINT64_C(0), |
9222 | 0 | UINT64_C(0), |
9223 | 0 | UINT64_C(0), |
9224 | 0 | UINT64_C(0), |
9225 | 0 | UINT64_C(0), |
9226 | 0 | UINT64_C(0), |
9227 | 0 | UINT64_C(0), |
9228 | 0 | UINT64_C(0), |
9229 | 0 | UINT64_C(0), |
9230 | 0 | UINT64_C(0), |
9231 | 0 | UINT64_C(0), |
9232 | 0 | UINT64_C(0), |
9233 | 0 | UINT64_C(0), |
9234 | 0 | UINT64_C(0), |
9235 | 0 | UINT64_C(0), |
9236 | 0 | UINT64_C(0), |
9237 | 0 | UINT64_C(0), |
9238 | 0 | UINT64_C(0), |
9239 | 0 | UINT64_C(0), |
9240 | 0 | UINT64_C(0), |
9241 | 0 | UINT64_C(0), |
9242 | 0 | UINT64_C(0), |
9243 | 0 | UINT64_C(0), |
9244 | 0 | UINT64_C(0), |
9245 | 0 | UINT64_C(0), |
9246 | 0 | UINT64_C(0), |
9247 | 0 | UINT64_C(0), |
9248 | 0 | UINT64_C(0), |
9249 | 0 | UINT64_C(0), |
9250 | 0 | UINT64_C(0), |
9251 | 0 | UINT64_C(0), |
9252 | 0 | UINT64_C(0), |
9253 | 0 | UINT64_C(0), |
9254 | 0 | UINT64_C(0), |
9255 | 0 | UINT64_C(0), |
9256 | 0 | UINT64_C(0), |
9257 | 0 | UINT64_C(0), |
9258 | 0 | UINT64_C(0), |
9259 | 0 | UINT64_C(0), |
9260 | 0 | UINT64_C(0), |
9261 | 0 | UINT64_C(0), |
9262 | 0 | UINT64_C(0), |
9263 | 0 | UINT64_C(0), |
9264 | 0 | UINT64_C(0), |
9265 | 0 | UINT64_C(0), |
9266 | 0 | UINT64_C(0), |
9267 | 0 | UINT64_C(0), |
9268 | 0 | UINT64_C(0), |
9269 | 0 | UINT64_C(0), |
9270 | 0 | UINT64_C(0), |
9271 | 0 | UINT64_C(0), |
9272 | 0 | UINT64_C(0), |
9273 | 0 | UINT64_C(0), |
9274 | 0 | UINT64_C(0), |
9275 | 0 | UINT64_C(0), |
9276 | 0 | UINT64_C(0), |
9277 | 0 | UINT64_C(0), |
9278 | 0 | UINT64_C(0), |
9279 | 0 | UINT64_C(0), |
9280 | 0 | UINT64_C(0), |
9281 | 0 | UINT64_C(0), |
9282 | 0 | UINT64_C(0), |
9283 | 0 | UINT64_C(0), |
9284 | 0 | UINT64_C(0), |
9285 | 0 | UINT64_C(0), |
9286 | 0 | UINT64_C(0), |
9287 | 0 | UINT64_C(0), |
9288 | 0 | UINT64_C(0), |
9289 | 0 | UINT64_C(0), |
9290 | 0 | UINT64_C(0), |
9291 | 0 | UINT64_C(0), |
9292 | 0 | UINT64_C(0), |
9293 | 0 | UINT64_C(0), |
9294 | 0 | UINT64_C(0), |
9295 | 0 | UINT64_C(0), |
9296 | 0 | UINT64_C(0), |
9297 | 0 | UINT64_C(0), |
9298 | 0 | UINT64_C(0), |
9299 | 0 | UINT64_C(0), |
9300 | 0 | UINT64_C(0), |
9301 | 0 | UINT64_C(0), |
9302 | 0 | UINT64_C(0), |
9303 | 0 | UINT64_C(0), |
9304 | 0 | UINT64_C(0), |
9305 | 0 | UINT64_C(0), |
9306 | 0 | UINT64_C(0), |
9307 | 0 | UINT64_C(0), |
9308 | 0 | UINT64_C(0), |
9309 | 0 | UINT64_C(0), |
9310 | 0 | UINT64_C(0), |
9311 | 0 | UINT64_C(0), |
9312 | 0 | UINT64_C(0), |
9313 | 0 | UINT64_C(0), |
9314 | 0 | UINT64_C(0), |
9315 | 0 | UINT64_C(0), |
9316 | 0 | UINT64_C(0), |
9317 | 0 | UINT64_C(0), |
9318 | 0 | UINT64_C(0), |
9319 | 0 | UINT64_C(0), |
9320 | 0 | UINT64_C(0), |
9321 | 0 | UINT64_C(0), |
9322 | 0 | UINT64_C(0), |
9323 | 0 | UINT64_C(0), |
9324 | 0 | UINT64_C(0), |
9325 | 0 | UINT64_C(0), |
9326 | 0 | UINT64_C(0), |
9327 | 0 | UINT64_C(0), |
9328 | 0 | UINT64_C(0), |
9329 | 0 | UINT64_C(0), |
9330 | 0 | UINT64_C(0), |
9331 | 0 | UINT64_C(0), |
9332 | 0 | UINT64_C(0), |
9333 | 0 | UINT64_C(0), |
9334 | 0 | UINT64_C(0), |
9335 | 0 | UINT64_C(0), |
9336 | 0 | UINT64_C(0), |
9337 | 0 | UINT64_C(0), |
9338 | 0 | UINT64_C(0), |
9339 | 0 | UINT64_C(0), |
9340 | 0 | UINT64_C(0), |
9341 | 0 | UINT64_C(0), |
9342 | 0 | UINT64_C(0), |
9343 | 0 | UINT64_C(0), |
9344 | 0 | UINT64_C(0), |
9345 | 0 | UINT64_C(0), |
9346 | 0 | UINT64_C(0), |
9347 | 0 | UINT64_C(0), |
9348 | 0 | UINT64_C(0), |
9349 | 0 | UINT64_C(0), |
9350 | 0 | UINT64_C(0), |
9351 | 0 | UINT64_C(0), |
9352 | 0 | UINT64_C(0), |
9353 | 0 | UINT64_C(0), |
9354 | 0 | UINT64_C(0), |
9355 | 0 | UINT64_C(0), |
9356 | 0 | UINT64_C(0), |
9357 | 0 | UINT64_C(0), |
9358 | 0 | UINT64_C(0), |
9359 | 0 | UINT64_C(0), |
9360 | 0 | UINT64_C(0), |
9361 | 0 | UINT64_C(0), |
9362 | 0 | UINT64_C(0), |
9363 | 0 | UINT64_C(0), |
9364 | 0 | UINT64_C(0), |
9365 | 0 | UINT64_C(0), |
9366 | 0 | UINT64_C(0), |
9367 | 0 | UINT64_C(0), |
9368 | 0 | UINT64_C(0), |
9369 | 0 | UINT64_C(0), |
9370 | 0 | UINT64_C(0), |
9371 | 0 | UINT64_C(0), |
9372 | 0 | UINT64_C(0), |
9373 | 0 | UINT64_C(0), |
9374 | 0 | UINT64_C(0), |
9375 | 0 | UINT64_C(0), |
9376 | 0 | UINT64_C(0), |
9377 | 0 | UINT64_C(0), |
9378 | 0 | UINT64_C(0), |
9379 | 0 | UINT64_C(0), |
9380 | 0 | UINT64_C(0), |
9381 | 0 | UINT64_C(0), |
9382 | 0 | UINT64_C(0), |
9383 | 0 | UINT64_C(0), |
9384 | 0 | UINT64_C(0), |
9385 | 0 | UINT64_C(0), |
9386 | 0 | UINT64_C(0), |
9387 | 0 | UINT64_C(0), |
9388 | 0 | UINT64_C(0), |
9389 | 0 | UINT64_C(0), |
9390 | 0 | UINT64_C(0), |
9391 | 0 | UINT64_C(0), |
9392 | 0 | UINT64_C(0), |
9393 | 0 | UINT64_C(0), |
9394 | 0 | UINT64_C(0), |
9395 | 0 | UINT64_C(0), |
9396 | 0 | UINT64_C(0), |
9397 | 0 | UINT64_C(0), |
9398 | 0 | UINT64_C(0), |
9399 | 0 | UINT64_C(0), |
9400 | 0 | UINT64_C(0), |
9401 | 0 | UINT64_C(0), |
9402 | 0 | UINT64_C(0), |
9403 | 0 | UINT64_C(0), |
9404 | 0 | UINT64_C(0), |
9405 | 0 | UINT64_C(0), |
9406 | 0 | UINT64_C(0), |
9407 | 0 | UINT64_C(0), |
9408 | 0 | UINT64_C(0), |
9409 | 0 | UINT64_C(0), |
9410 | 0 | UINT64_C(0), |
9411 | 0 | UINT64_C(0), |
9412 | 0 | UINT64_C(0), |
9413 | 0 | UINT64_C(0), |
9414 | 0 | UINT64_C(0), |
9415 | 0 | UINT64_C(0), |
9416 | 0 | UINT64_C(0), |
9417 | 0 | UINT64_C(0), |
9418 | 0 | UINT64_C(0), |
9419 | 0 | UINT64_C(0), |
9420 | 0 | UINT64_C(0), |
9421 | 0 | UINT64_C(0), |
9422 | 0 | UINT64_C(0), |
9423 | 0 | UINT64_C(0), |
9424 | 0 | UINT64_C(0), |
9425 | 0 | UINT64_C(0), |
9426 | 0 | UINT64_C(0), |
9427 | 0 | UINT64_C(0), |
9428 | 0 | UINT64_C(0), |
9429 | 0 | UINT64_C(0), |
9430 | 0 | UINT64_C(0), |
9431 | 0 | UINT64_C(0), |
9432 | 0 | UINT64_C(0), |
9433 | 0 | UINT64_C(0), |
9434 | 0 | UINT64_C(0), |
9435 | 0 | UINT64_C(0), |
9436 | 0 | UINT64_C(0), |
9437 | 0 | UINT64_C(0), |
9438 | 0 | UINT64_C(0), |
9439 | 0 | UINT64_C(0), |
9440 | 0 | UINT64_C(0), |
9441 | 0 | UINT64_C(0), |
9442 | 0 | UINT64_C(0), |
9443 | 0 | UINT64_C(0), |
9444 | 0 | UINT64_C(0), |
9445 | 0 | UINT64_C(0), |
9446 | 0 | UINT64_C(0), |
9447 | 0 | UINT64_C(0), |
9448 | 0 | UINT64_C(0), |
9449 | 0 | UINT64_C(0), |
9450 | 0 | UINT64_C(0), |
9451 | 0 | UINT64_C(0), |
9452 | 0 | UINT64_C(0), |
9453 | 0 | UINT64_C(0), |
9454 | 0 | UINT64_C(0), |
9455 | 0 | UINT64_C(0), |
9456 | 0 | UINT64_C(0), |
9457 | 0 | UINT64_C(0), |
9458 | 0 | UINT64_C(0), |
9459 | 0 | UINT64_C(0), |
9460 | 0 | UINT64_C(0), |
9461 | 0 | UINT64_C(0), |
9462 | 0 | UINT64_C(0), |
9463 | 0 | UINT64_C(0), |
9464 | 0 | UINT64_C(0), |
9465 | 0 | UINT64_C(0), |
9466 | 0 | UINT64_C(0), |
9467 | 0 | UINT64_C(0), |
9468 | 0 | UINT64_C(0), |
9469 | 0 | UINT64_C(0), |
9470 | 0 | UINT64_C(0), |
9471 | 0 | UINT64_C(0), |
9472 | 0 | UINT64_C(0), |
9473 | 0 | UINT64_C(0), |
9474 | 0 | UINT64_C(0), |
9475 | 0 | UINT64_C(0), |
9476 | 0 | UINT64_C(0), |
9477 | 0 | UINT64_C(0), |
9478 | 0 | UINT64_C(0), |
9479 | 0 | UINT64_C(0), |
9480 | 0 | UINT64_C(0), |
9481 | 0 | UINT64_C(0), |
9482 | 0 | UINT64_C(0), |
9483 | 0 | UINT64_C(0), |
9484 | 0 | UINT64_C(0), |
9485 | 0 | UINT64_C(0), |
9486 | 0 | UINT64_C(0), |
9487 | 0 | UINT64_C(0), |
9488 | 0 | UINT64_C(0), |
9489 | 0 | UINT64_C(0), |
9490 | 0 | UINT64_C(0), |
9491 | 0 | UINT64_C(0), |
9492 | 0 | UINT64_C(0), |
9493 | 0 | UINT64_C(0), |
9494 | 0 | UINT64_C(0), |
9495 | 0 | UINT64_C(0), |
9496 | 0 | UINT64_C(0), |
9497 | 0 | UINT64_C(0), |
9498 | 0 | UINT64_C(0), |
9499 | 0 | UINT64_C(0), |
9500 | 0 | UINT64_C(0), |
9501 | 0 | UINT64_C(0), |
9502 | 0 | UINT64_C(0), |
9503 | 0 | UINT64_C(0), |
9504 | 0 | UINT64_C(0), |
9505 | 0 | UINT64_C(0), |
9506 | 0 | UINT64_C(0), |
9507 | 0 | UINT64_C(0), |
9508 | 0 | UINT64_C(0), |
9509 | 0 | UINT64_C(0), |
9510 | 0 | UINT64_C(0), |
9511 | 0 | UINT64_C(0), |
9512 | 0 | UINT64_C(0), |
9513 | 0 | UINT64_C(0), |
9514 | 0 | UINT64_C(0), |
9515 | 0 | UINT64_C(0), |
9516 | 0 | UINT64_C(0), |
9517 | 0 | UINT64_C(0), |
9518 | 0 | UINT64_C(0), |
9519 | 0 | UINT64_C(0), |
9520 | 0 | UINT64_C(0), |
9521 | 0 | UINT64_C(0), |
9522 | 0 | UINT64_C(0), |
9523 | 0 | UINT64_C(0), |
9524 | 0 | UINT64_C(0), |
9525 | 0 | UINT64_C(0), |
9526 | 0 | UINT64_C(0), |
9527 | 0 | UINT64_C(0), |
9528 | 0 | UINT64_C(0), |
9529 | 0 | UINT64_C(0), |
9530 | 0 | UINT64_C(0), |
9531 | 0 | UINT64_C(0), |
9532 | 0 | UINT64_C(0), |
9533 | 0 | UINT64_C(0), |
9534 | 0 | UINT64_C(0), |
9535 | 0 | UINT64_C(0), |
9536 | 0 | UINT64_C(0), |
9537 | 0 | UINT64_C(0), |
9538 | 0 | UINT64_C(0), |
9539 | 0 | UINT64_C(0), |
9540 | 0 | UINT64_C(0), |
9541 | 0 | UINT64_C(0), |
9542 | 0 | UINT64_C(0), |
9543 | 0 | UINT64_C(0), |
9544 | 0 | UINT64_C(0), |
9545 | 0 | UINT64_C(0), |
9546 | 0 | UINT64_C(0), |
9547 | 0 | UINT64_C(0), |
9548 | 0 | UINT64_C(0), |
9549 | 0 | UINT64_C(0), |
9550 | 0 | UINT64_C(0), |
9551 | 0 | UINT64_C(0), |
9552 | 0 | UINT64_C(0), |
9553 | 0 | UINT64_C(0), |
9554 | 0 | UINT64_C(0), |
9555 | 0 | UINT64_C(0), |
9556 | 0 | UINT64_C(0), |
9557 | 0 | UINT64_C(0), |
9558 | 0 | UINT64_C(0), |
9559 | 0 | UINT64_C(0), |
9560 | 0 | UINT64_C(0), |
9561 | 0 | UINT64_C(0), |
9562 | 0 | UINT64_C(0), |
9563 | 0 | UINT64_C(0), |
9564 | 0 | UINT64_C(0), |
9565 | 0 | UINT64_C(0), |
9566 | 0 | UINT64_C(0), |
9567 | 0 | UINT64_C(0), |
9568 | 0 | UINT64_C(0), |
9569 | 0 | UINT64_C(0), |
9570 | 0 | UINT64_C(0), |
9571 | 0 | UINT64_C(0), |
9572 | 0 | UINT64_C(0), |
9573 | 0 | UINT64_C(0), |
9574 | 0 | UINT64_C(0), |
9575 | 0 | UINT64_C(0), |
9576 | 0 | UINT64_C(0), |
9577 | 0 | UINT64_C(0), |
9578 | 0 | UINT64_C(0), |
9579 | 0 | UINT64_C(0), |
9580 | 0 | UINT64_C(0), |
9581 | 0 | UINT64_C(0), |
9582 | 0 | UINT64_C(0), |
9583 | 0 | UINT64_C(0), |
9584 | 0 | UINT64_C(0), |
9585 | 0 | UINT64_C(0), |
9586 | 0 | UINT64_C(0), |
9587 | 0 | UINT64_C(0), |
9588 | 0 | UINT64_C(0), |
9589 | 0 | UINT64_C(0), |
9590 | 0 | UINT64_C(0), |
9591 | 0 | UINT64_C(0), |
9592 | 0 | UINT64_C(0), |
9593 | 0 | UINT64_C(0), |
9594 | 0 | UINT64_C(0), |
9595 | 0 | UINT64_C(0), |
9596 | 0 | UINT64_C(0), |
9597 | 0 | UINT64_C(0), |
9598 | 0 | UINT64_C(0), |
9599 | 0 | UINT64_C(0), |
9600 | 0 | UINT64_C(0), |
9601 | 0 | UINT64_C(0), |
9602 | 0 | UINT64_C(0), |
9603 | 0 | UINT64_C(0), |
9604 | 0 | UINT64_C(0), |
9605 | 0 | UINT64_C(0), |
9606 | 0 | UINT64_C(0), |
9607 | 0 | UINT64_C(0), |
9608 | 0 | UINT64_C(0), |
9609 | 0 | UINT64_C(0), |
9610 | 0 | UINT64_C(0), |
9611 | 0 | UINT64_C(0), |
9612 | 0 | UINT64_C(0), |
9613 | 0 | UINT64_C(0), |
9614 | 0 | UINT64_C(0), |
9615 | 0 | UINT64_C(0), |
9616 | 0 | UINT64_C(0), |
9617 | 0 | UINT64_C(0), |
9618 | 0 | UINT64_C(0), |
9619 | 0 | UINT64_C(0), |
9620 | 0 | UINT64_C(0), |
9621 | 0 | UINT64_C(0), |
9622 | 0 | UINT64_C(0), |
9623 | 0 | UINT64_C(0), |
9624 | 0 | UINT64_C(0), |
9625 | 0 | UINT64_C(0), |
9626 | 0 | UINT64_C(0), |
9627 | 0 | UINT64_C(0), |
9628 | 0 | UINT64_C(0), |
9629 | 0 | UINT64_C(0), |
9630 | 0 | UINT64_C(0), |
9631 | 0 | UINT64_C(0), |
9632 | 0 | UINT64_C(0), |
9633 | 0 | UINT64_C(0), |
9634 | 0 | UINT64_C(0), |
9635 | 0 | UINT64_C(0), |
9636 | 0 | UINT64_C(0), |
9637 | 0 | UINT64_C(0), |
9638 | 0 | UINT64_C(0), |
9639 | 0 | UINT64_C(0), |
9640 | 0 | UINT64_C(0), |
9641 | 0 | UINT64_C(0), |
9642 | 0 | UINT64_C(0), |
9643 | 0 | UINT64_C(0), |
9644 | 0 | UINT64_C(0), |
9645 | 0 | UINT64_C(0), |
9646 | 0 | UINT64_C(0), |
9647 | 0 | UINT64_C(0), |
9648 | 0 | UINT64_C(0), |
9649 | 0 | UINT64_C(0), |
9650 | 0 | UINT64_C(0), |
9651 | 0 | UINT64_C(0), |
9652 | 0 | UINT64_C(0), |
9653 | 0 | UINT64_C(0), |
9654 | 0 | UINT64_C(0), |
9655 | 0 | UINT64_C(0), |
9656 | 0 | UINT64_C(0), |
9657 | 0 | UINT64_C(0), |
9658 | 0 | UINT64_C(0), |
9659 | 0 | UINT64_C(0), |
9660 | 0 | UINT64_C(0), |
9661 | 0 | UINT64_C(0), |
9662 | 0 | UINT64_C(0), |
9663 | 0 | UINT64_C(0), |
9664 | 0 | UINT64_C(0), |
9665 | 0 | UINT64_C(0), |
9666 | 0 | UINT64_C(0), |
9667 | 0 | UINT64_C(0), |
9668 | 0 | UINT64_C(0), |
9669 | 0 | UINT64_C(0), |
9670 | 0 | UINT64_C(0), |
9671 | 0 | UINT64_C(0), |
9672 | 0 | UINT64_C(0), |
9673 | 0 | UINT64_C(0), |
9674 | 0 | UINT64_C(0), |
9675 | 0 | UINT64_C(0), |
9676 | 0 | UINT64_C(0), |
9677 | 0 | UINT64_C(0), |
9678 | 0 | UINT64_C(0), |
9679 | 0 | UINT64_C(0), |
9680 | 0 | UINT64_C(0), |
9681 | 0 | UINT64_C(0), |
9682 | 0 | UINT64_C(0), |
9683 | 0 | UINT64_C(0), |
9684 | 0 | UINT64_C(0), |
9685 | 0 | UINT64_C(0), |
9686 | 0 | UINT64_C(0), |
9687 | 0 | UINT64_C(0), |
9688 | 0 | UINT64_C(0), |
9689 | 0 | UINT64_C(0), |
9690 | 0 | UINT64_C(0), |
9691 | 0 | UINT64_C(0), |
9692 | 0 | UINT64_C(0), |
9693 | 0 | UINT64_C(0), |
9694 | 0 | UINT64_C(0), |
9695 | 0 | UINT64_C(0), |
9696 | 0 | UINT64_C(0), |
9697 | 0 | UINT64_C(0), |
9698 | 0 | UINT64_C(0), |
9699 | 0 | UINT64_C(0), |
9700 | 0 | UINT64_C(0), |
9701 | 0 | UINT64_C(0), |
9702 | 0 | UINT64_C(0), |
9703 | 0 | UINT64_C(0), |
9704 | 0 | UINT64_C(0), |
9705 | 0 | UINT64_C(0), |
9706 | 0 | UINT64_C(0), |
9707 | 0 | UINT64_C(0), |
9708 | 0 | UINT64_C(0), |
9709 | 0 | UINT64_C(0), |
9710 | 0 | UINT64_C(0), |
9711 | 0 | UINT64_C(0), |
9712 | 0 | UINT64_C(0), |
9713 | 0 | UINT64_C(0), |
9714 | 0 | UINT64_C(0), |
9715 | 0 | UINT64_C(0), |
9716 | 0 | UINT64_C(0), |
9717 | 0 | UINT64_C(0), |
9718 | 0 | UINT64_C(0), |
9719 | 0 | UINT64_C(0), |
9720 | 0 | UINT64_C(0), |
9721 | 0 | UINT64_C(0), |
9722 | 0 | UINT64_C(0), |
9723 | 0 | UINT64_C(0), |
9724 | 0 | UINT64_C(0), |
9725 | 0 | UINT64_C(0), |
9726 | 0 | UINT64_C(0), |
9727 | 0 | UINT64_C(0), |
9728 | 0 | UINT64_C(0), |
9729 | 0 | UINT64_C(0), |
9730 | 0 | UINT64_C(0), |
9731 | 0 | UINT64_C(0), |
9732 | 0 | UINT64_C(0), |
9733 | 0 | UINT64_C(0), |
9734 | 0 | UINT64_C(0), |
9735 | 0 | UINT64_C(0), |
9736 | 0 | UINT64_C(0), |
9737 | 0 | UINT64_C(0), |
9738 | 0 | UINT64_C(0), |
9739 | 0 | UINT64_C(0), |
9740 | 0 | UINT64_C(0), |
9741 | 0 | UINT64_C(0), |
9742 | 0 | UINT64_C(0), |
9743 | 0 | UINT64_C(0), |
9744 | 0 | UINT64_C(0), |
9745 | 0 | UINT64_C(0), |
9746 | 0 | UINT64_C(0), |
9747 | 0 | UINT64_C(0), |
9748 | 0 | UINT64_C(0), |
9749 | 0 | UINT64_C(0), |
9750 | 0 | UINT64_C(0), |
9751 | 0 | UINT64_C(0), |
9752 | 0 | UINT64_C(0), |
9753 | 0 | UINT64_C(0), |
9754 | 0 | UINT64_C(0), |
9755 | 0 | UINT64_C(0), |
9756 | 0 | UINT64_C(0), |
9757 | 0 | UINT64_C(0), |
9758 | 0 | UINT64_C(0), |
9759 | 0 | UINT64_C(0), |
9760 | 0 | UINT64_C(0), |
9761 | 0 | UINT64_C(0), |
9762 | 0 | UINT64_C(0), |
9763 | 0 | UINT64_C(0), |
9764 | 0 | UINT64_C(0), |
9765 | 0 | UINT64_C(0), |
9766 | 0 | UINT64_C(0), |
9767 | 0 | UINT64_C(0), |
9768 | 0 | UINT64_C(0), |
9769 | 0 | UINT64_C(0), |
9770 | 0 | UINT64_C(0), |
9771 | 0 | UINT64_C(0), |
9772 | 0 | UINT64_C(0), |
9773 | 0 | UINT64_C(0), |
9774 | 0 | UINT64_C(0), |
9775 | 0 | UINT64_C(0), |
9776 | 0 | UINT64_C(0), |
9777 | 0 | UINT64_C(0), |
9778 | 0 | UINT64_C(0), |
9779 | 0 | UINT64_C(0), |
9780 | 0 | UINT64_C(0), |
9781 | 0 | UINT64_C(0), |
9782 | 0 | UINT64_C(0), |
9783 | 0 | UINT64_C(0), |
9784 | 0 | UINT64_C(0), |
9785 | 0 | UINT64_C(0), |
9786 | 0 | UINT64_C(0), |
9787 | 0 | UINT64_C(0), |
9788 | 0 | UINT64_C(0), |
9789 | 0 | UINT64_C(0), |
9790 | 0 | UINT64_C(0), |
9791 | 0 | UINT64_C(0), |
9792 | 0 | UINT64_C(0), |
9793 | 0 | UINT64_C(0), |
9794 | 0 | UINT64_C(0), |
9795 | 0 | UINT64_C(0), |
9796 | 0 | UINT64_C(0), |
9797 | 0 | UINT64_C(0), |
9798 | 0 | UINT64_C(0), |
9799 | 0 | UINT64_C(0), |
9800 | 0 | UINT64_C(0), |
9801 | 0 | UINT64_C(0), |
9802 | 0 | UINT64_C(0), |
9803 | 0 | UINT64_C(0), |
9804 | 0 | UINT64_C(0), |
9805 | 0 | UINT64_C(0), |
9806 | 0 | UINT64_C(0), |
9807 | 0 | UINT64_C(0), |
9808 | 0 | UINT64_C(0), |
9809 | 0 | UINT64_C(0), |
9810 | 0 | UINT64_C(0), |
9811 | 0 | UINT64_C(0), |
9812 | 0 | UINT64_C(0), |
9813 | 0 | UINT64_C(0), |
9814 | 0 | UINT64_C(0), |
9815 | 0 | UINT64_C(0), |
9816 | 0 | UINT64_C(0), |
9817 | 0 | UINT64_C(0), |
9818 | 0 | UINT64_C(0), |
9819 | 0 | UINT64_C(0), |
9820 | 0 | UINT64_C(0), |
9821 | 0 | UINT64_C(0), |
9822 | 0 | UINT64_C(0), |
9823 | 0 | UINT64_C(0), |
9824 | 0 | UINT64_C(0), |
9825 | 0 | UINT64_C(0), |
9826 | 0 | UINT64_C(0), |
9827 | 0 | UINT64_C(0), |
9828 | 0 | UINT64_C(0), |
9829 | 0 | UINT64_C(0), |
9830 | 0 | UINT64_C(0), |
9831 | 0 | UINT64_C(0), |
9832 | 0 | UINT64_C(0), |
9833 | 0 | UINT64_C(0), |
9834 | 0 | UINT64_C(0), |
9835 | 0 | UINT64_C(0), |
9836 | 0 | UINT64_C(0), |
9837 | 0 | UINT64_C(0), |
9838 | 0 | UINT64_C(0), |
9839 | 0 | UINT64_C(0), |
9840 | 0 | UINT64_C(0), |
9841 | 0 | UINT64_C(0), |
9842 | 0 | UINT64_C(0), |
9843 | 0 | UINT64_C(0), |
9844 | 0 | UINT64_C(0), |
9845 | 0 | UINT64_C(0), |
9846 | 0 | UINT64_C(0), |
9847 | 0 | UINT64_C(0), |
9848 | 0 | UINT64_C(0), |
9849 | 0 | UINT64_C(0), |
9850 | 0 | UINT64_C(0), |
9851 | 0 | UINT64_C(0), |
9852 | 0 | UINT64_C(0), |
9853 | 0 | UINT64_C(0), |
9854 | 0 | UINT64_C(0), |
9855 | 0 | UINT64_C(0), |
9856 | 0 | UINT64_C(0), |
9857 | 0 | UINT64_C(0), |
9858 | 0 | UINT64_C(0), |
9859 | 0 | UINT64_C(0), |
9860 | 0 | UINT64_C(0), |
9861 | 0 | UINT64_C(0), |
9862 | 0 | UINT64_C(0), |
9863 | 0 | UINT64_C(0), |
9864 | 0 | UINT64_C(0), |
9865 | 0 | UINT64_C(0), |
9866 | 0 | UINT64_C(0), |
9867 | 0 | UINT64_C(0), |
9868 | 0 | UINT64_C(0), |
9869 | 0 | UINT64_C(0), |
9870 | 0 | UINT64_C(0), |
9871 | 0 | UINT64_C(0), |
9872 | 0 | UINT64_C(0), |
9873 | 0 | UINT64_C(0), |
9874 | 0 | UINT64_C(0), |
9875 | 0 | UINT64_C(0), |
9876 | 0 | UINT64_C(0), |
9877 | 0 | UINT64_C(0), |
9878 | 0 | UINT64_C(0), |
9879 | 0 | UINT64_C(0), |
9880 | 0 | UINT64_C(0), |
9881 | 0 | UINT64_C(0), |
9882 | 0 | UINT64_C(0), |
9883 | 0 | UINT64_C(0), |
9884 | 0 | UINT64_C(0), |
9885 | 0 | UINT64_C(0), |
9886 | 0 | UINT64_C(0), |
9887 | 0 | UINT64_C(0), |
9888 | 0 | UINT64_C(0), |
9889 | 0 | UINT64_C(0), |
9890 | 0 | UINT64_C(0), |
9891 | 0 | UINT64_C(0), |
9892 | 0 | UINT64_C(0), |
9893 | 0 | UINT64_C(0), |
9894 | 0 | UINT64_C(0), |
9895 | 0 | UINT64_C(0), |
9896 | 0 | UINT64_C(0), |
9897 | 0 | UINT64_C(0), |
9898 | 0 | UINT64_C(0), |
9899 | 0 | UINT64_C(0), |
9900 | 0 | UINT64_C(0), |
9901 | 0 | UINT64_C(0), |
9902 | 0 | UINT64_C(0), |
9903 | 0 | UINT64_C(0), |
9904 | 0 | UINT64_C(0), |
9905 | 0 | UINT64_C(0), |
9906 | 0 | UINT64_C(0), |
9907 | 0 | UINT64_C(0), |
9908 | 0 | UINT64_C(0), |
9909 | 0 | UINT64_C(0), |
9910 | 0 | UINT64_C(0), |
9911 | 0 | UINT64_C(0), |
9912 | 0 | UINT64_C(0), |
9913 | 0 | UINT64_C(0), |
9914 | 0 | UINT64_C(0), |
9915 | 0 | UINT64_C(0), |
9916 | 0 | UINT64_C(0), |
9917 | 0 | UINT64_C(0), |
9918 | 0 | UINT64_C(0), |
9919 | 0 | UINT64_C(0), |
9920 | 0 | UINT64_C(0), |
9921 | 0 | UINT64_C(0), |
9922 | 0 | UINT64_C(0), |
9923 | 0 | UINT64_C(0), |
9924 | 0 | UINT64_C(0), |
9925 | 0 | UINT64_C(0), |
9926 | 0 | UINT64_C(0), |
9927 | 0 | UINT64_C(0), |
9928 | 0 | UINT64_C(0), |
9929 | 0 | UINT64_C(0), |
9930 | 0 | UINT64_C(0), |
9931 | 0 | UINT64_C(0), |
9932 | 0 | UINT64_C(0), |
9933 | 0 | UINT64_C(0), |
9934 | 0 | UINT64_C(0), |
9935 | 0 | UINT64_C(0), |
9936 | 0 | UINT64_C(0), |
9937 | 0 | UINT64_C(0), |
9938 | 0 | UINT64_C(0), |
9939 | 0 | UINT64_C(0), |
9940 | 0 | UINT64_C(0), |
9941 | 0 | UINT64_C(0), |
9942 | 0 | UINT64_C(0), |
9943 | 0 | UINT64_C(0), |
9944 | 0 | UINT64_C(0), |
9945 | 0 | UINT64_C(0), |
9946 | 0 | UINT64_C(0), |
9947 | 0 | UINT64_C(0), |
9948 | 0 | UINT64_C(0), |
9949 | 0 | UINT64_C(0), |
9950 | 0 | UINT64_C(0), |
9951 | 0 | UINT64_C(0), |
9952 | 0 | UINT64_C(0), |
9953 | 0 | UINT64_C(0), |
9954 | 0 | UINT64_C(0), |
9955 | 0 | UINT64_C(0), |
9956 | 0 | UINT64_C(0), |
9957 | 0 | UINT64_C(0), |
9958 | 0 | UINT64_C(0), |
9959 | 0 | UINT64_C(0), |
9960 | 0 | UINT64_C(0), |
9961 | 0 | UINT64_C(0), |
9962 | 0 | UINT64_C(0), |
9963 | 0 | UINT64_C(0), |
9964 | 0 | UINT64_C(0), |
9965 | 0 | UINT64_C(0), |
9966 | 0 | UINT64_C(0), |
9967 | 0 | UINT64_C(0), |
9968 | 0 | UINT64_C(0), |
9969 | 0 | UINT64_C(0), |
9970 | 0 | UINT64_C(0), |
9971 | 0 | UINT64_C(0), |
9972 | 0 | UINT64_C(0), |
9973 | 0 | UINT64_C(0), |
9974 | 0 | UINT64_C(0), |
9975 | 0 | UINT64_C(0), |
9976 | 0 | UINT64_C(0), |
9977 | 0 | UINT64_C(0), |
9978 | 0 | UINT64_C(0), |
9979 | 0 | UINT64_C(0), |
9980 | 0 | UINT64_C(0), |
9981 | 0 | UINT64_C(0), |
9982 | 0 | UINT64_C(0), |
9983 | 0 | UINT64_C(0), |
9984 | 0 | UINT64_C(0), |
9985 | 0 | UINT64_C(0), |
9986 | 0 | UINT64_C(0), |
9987 | 0 | UINT64_C(0), |
9988 | 0 | UINT64_C(0), |
9989 | 0 | UINT64_C(0), |
9990 | 0 | UINT64_C(0), |
9991 | 0 | UINT64_C(0), |
9992 | 0 | UINT64_C(0), |
9993 | 0 | UINT64_C(0), |
9994 | 0 | UINT64_C(0), |
9995 | 0 | UINT64_C(0), |
9996 | 0 | UINT64_C(0), |
9997 | 0 | UINT64_C(0), |
9998 | 0 | UINT64_C(0), |
9999 | 0 | UINT64_C(0), |
10000 | 0 | UINT64_C(0), |
10001 | 0 | UINT64_C(0), |
10002 | 0 | UINT64_C(0), |
10003 | 0 | UINT64_C(0), |
10004 | 0 | UINT64_C(0), |
10005 | 0 | UINT64_C(0), |
10006 | 0 | UINT64_C(0), |
10007 | 0 | UINT64_C(0), |
10008 | 0 | UINT64_C(0), |
10009 | 0 | UINT64_C(0), |
10010 | 0 | UINT64_C(0), |
10011 | 0 | UINT64_C(0), |
10012 | 0 | UINT64_C(0), |
10013 | 0 | UINT64_C(0), |
10014 | 0 | UINT64_C(0), |
10015 | 0 | UINT64_C(0), |
10016 | 0 | UINT64_C(0), |
10017 | 0 | UINT64_C(0), |
10018 | 0 | UINT64_C(0), |
10019 | 0 | UINT64_C(0), |
10020 | 0 | UINT64_C(0), |
10021 | 0 | UINT64_C(0), |
10022 | 0 | UINT64_C(0), |
10023 | 0 | UINT64_C(0), |
10024 | 0 | UINT64_C(0), |
10025 | 0 | UINT64_C(0), |
10026 | 0 | UINT64_C(0), |
10027 | 0 | UINT64_C(0), |
10028 | 0 | UINT64_C(0), |
10029 | 0 | UINT64_C(0), |
10030 | 0 | UINT64_C(0), |
10031 | 0 | UINT64_C(0), |
10032 | 0 | UINT64_C(0), |
10033 | 0 | UINT64_C(0), |
10034 | 0 | UINT64_C(0), |
10035 | 0 | UINT64_C(0), |
10036 | 0 | UINT64_C(0), |
10037 | 0 | UINT64_C(0), |
10038 | 0 | UINT64_C(0), |
10039 | 0 | UINT64_C(0), |
10040 | 0 | UINT64_C(0), |
10041 | 0 | UINT64_C(0), |
10042 | 0 | UINT64_C(0), |
10043 | 0 | UINT64_C(0), |
10044 | 0 | UINT64_C(0), |
10045 | 0 | UINT64_C(0), |
10046 | 0 | UINT64_C(0), |
10047 | 0 | UINT64_C(0), |
10048 | 0 | UINT64_C(0), |
10049 | 0 | UINT64_C(0), |
10050 | 0 | UINT64_C(0), |
10051 | 0 | UINT64_C(0), |
10052 | 0 | UINT64_C(0), |
10053 | 0 | UINT64_C(0), |
10054 | 0 | UINT64_C(0), |
10055 | 0 | UINT64_C(0), |
10056 | 0 | UINT64_C(0), |
10057 | 0 | UINT64_C(0), |
10058 | 0 | UINT64_C(0), |
10059 | 0 | UINT64_C(0), |
10060 | 0 | UINT64_C(0), |
10061 | 0 | UINT64_C(0), |
10062 | 0 | UINT64_C(0), |
10063 | 0 | UINT64_C(0), |
10064 | 0 | UINT64_C(0), |
10065 | 0 | UINT64_C(0), |
10066 | 0 | UINT64_C(0), |
10067 | 0 | UINT64_C(0), |
10068 | 0 | UINT64_C(0), |
10069 | 0 | UINT64_C(0), |
10070 | 0 | UINT64_C(0), |
10071 | 0 | UINT64_C(0), |
10072 | 0 | UINT64_C(0), |
10073 | 0 | UINT64_C(0), |
10074 | 0 | UINT64_C(0), |
10075 | 0 | UINT64_C(0), |
10076 | 0 | UINT64_C(0), |
10077 | 0 | UINT64_C(0), |
10078 | 0 | UINT64_C(0), |
10079 | 0 | UINT64_C(0), |
10080 | 0 | UINT64_C(0), |
10081 | 0 | UINT64_C(0), |
10082 | 0 | UINT64_C(0), |
10083 | 0 | UINT64_C(0), |
10084 | 0 | UINT64_C(0), |
10085 | 0 | UINT64_C(0), |
10086 | 0 | UINT64_C(0), |
10087 | 0 | UINT64_C(0), |
10088 | 0 | UINT64_C(0), |
10089 | 0 | UINT64_C(0), |
10090 | 0 | UINT64_C(0), |
10091 | 0 | UINT64_C(0), |
10092 | 0 | UINT64_C(0), |
10093 | 0 | UINT64_C(0), |
10094 | 0 | UINT64_C(0), |
10095 | 0 | UINT64_C(0), |
10096 | 0 | UINT64_C(0), |
10097 | 0 | UINT64_C(0), |
10098 | 0 | UINT64_C(0), |
10099 | 0 | UINT64_C(0), |
10100 | 0 | UINT64_C(0), |
10101 | 0 | UINT64_C(0), |
10102 | 0 | UINT64_C(0), |
10103 | 0 | UINT64_C(0), |
10104 | 0 | UINT64_C(0), |
10105 | 0 | UINT64_C(0), |
10106 | 0 | UINT64_C(0), |
10107 | 0 | UINT64_C(0), |
10108 | 0 | UINT64_C(0), |
10109 | 0 | UINT64_C(0), |
10110 | 0 | UINT64_C(0), |
10111 | 0 | UINT64_C(0), |
10112 | 0 | UINT64_C(0), |
10113 | 0 | UINT64_C(0), |
10114 | 0 | UINT64_C(0), |
10115 | 0 | UINT64_C(0), |
10116 | 0 | UINT64_C(0), |
10117 | 0 | UINT64_C(0), |
10118 | 0 | UINT64_C(0), |
10119 | 0 | UINT64_C(0), |
10120 | 0 | UINT64_C(0), |
10121 | 0 | UINT64_C(0), |
10122 | 0 | UINT64_C(0), |
10123 | 0 | UINT64_C(0), |
10124 | 0 | UINT64_C(0), |
10125 | 0 | UINT64_C(0), |
10126 | 0 | UINT64_C(0), |
10127 | 0 | UINT64_C(0), |
10128 | 0 | UINT64_C(0), |
10129 | 0 | UINT64_C(0), |
10130 | 0 | UINT64_C(0), |
10131 | 0 | UINT64_C(0), |
10132 | 0 | UINT64_C(0), |
10133 | 0 | UINT64_C(0), |
10134 | 0 | UINT64_C(0), |
10135 | 0 | UINT64_C(0), |
10136 | 0 | UINT64_C(0), |
10137 | 0 | UINT64_C(0), |
10138 | 0 | UINT64_C(0), |
10139 | 0 | UINT64_C(0), |
10140 | 0 | UINT64_C(0), |
10141 | 0 | UINT64_C(0), |
10142 | 0 | UINT64_C(0), |
10143 | 0 | UINT64_C(0), |
10144 | 0 | UINT64_C(0), |
10145 | 0 | UINT64_C(0), |
10146 | 0 | UINT64_C(0), |
10147 | 0 | UINT64_C(0), |
10148 | 0 | UINT64_C(0), |
10149 | 0 | UINT64_C(0), |
10150 | 0 | UINT64_C(0), |
10151 | 0 | UINT64_C(0), |
10152 | 0 | UINT64_C(0), |
10153 | 0 | UINT64_C(0), |
10154 | 0 | UINT64_C(0), |
10155 | 0 | UINT64_C(0), |
10156 | 0 | UINT64_C(0), |
10157 | 0 | UINT64_C(0), |
10158 | 0 | UINT64_C(0), |
10159 | 0 | UINT64_C(0), |
10160 | 0 | UINT64_C(0), |
10161 | 0 | UINT64_C(0), |
10162 | 0 | UINT64_C(0), |
10163 | 0 | UINT64_C(0), |
10164 | 0 | UINT64_C(0), |
10165 | 0 | UINT64_C(0), |
10166 | 0 | UINT64_C(0), |
10167 | 0 | UINT64_C(0), |
10168 | 0 | UINT64_C(0), |
10169 | 0 | UINT64_C(0), |
10170 | 0 | UINT64_C(0), |
10171 | 0 | UINT64_C(0), |
10172 | 0 | UINT64_C(0), |
10173 | 0 | UINT64_C(0), |
10174 | 0 | UINT64_C(0), |
10175 | 0 | UINT64_C(0), |
10176 | 0 | UINT64_C(0), |
10177 | 0 | UINT64_C(0), |
10178 | 0 | UINT64_C(0), |
10179 | 0 | UINT64_C(0), |
10180 | 0 | UINT64_C(0), |
10181 | 0 | UINT64_C(0), |
10182 | 0 | UINT64_C(0), |
10183 | 0 | UINT64_C(0), |
10184 | 0 | UINT64_C(0), |
10185 | 0 | UINT64_C(0), |
10186 | 0 | UINT64_C(0), |
10187 | 0 | UINT64_C(0), |
10188 | 0 | UINT64_C(0), |
10189 | 0 | UINT64_C(0), |
10190 | 0 | UINT64_C(0), |
10191 | 0 | UINT64_C(0), |
10192 | 0 | UINT64_C(0), |
10193 | 0 | UINT64_C(0), |
10194 | 0 | UINT64_C(0), |
10195 | 0 | UINT64_C(0), |
10196 | 0 | UINT64_C(0), |
10197 | 0 | UINT64_C(0), |
10198 | 0 | UINT64_C(0), |
10199 | 0 | UINT64_C(0), |
10200 | 0 | UINT64_C(0), |
10201 | 0 | UINT64_C(0), |
10202 | 0 | UINT64_C(0), |
10203 | 0 | UINT64_C(0), |
10204 | 0 | UINT64_C(0), |
10205 | 0 | UINT64_C(0), |
10206 | 0 | UINT64_C(0), |
10207 | 0 | UINT64_C(0), |
10208 | 0 | UINT64_C(0), |
10209 | 0 | UINT64_C(0), |
10210 | 0 | UINT64_C(0), |
10211 | 0 | UINT64_C(0), |
10212 | 0 | UINT64_C(0), |
10213 | 0 | UINT64_C(0), |
10214 | 0 | UINT64_C(0), |
10215 | 0 | UINT64_C(0), |
10216 | 0 | UINT64_C(0), |
10217 | 0 | UINT64_C(0), |
10218 | 0 | UINT64_C(0), |
10219 | 0 | UINT64_C(0), |
10220 | 0 | UINT64_C(0), |
10221 | 0 | UINT64_C(0), |
10222 | 0 | UINT64_C(0), |
10223 | 0 | UINT64_C(0), |
10224 | 0 | UINT64_C(0), |
10225 | 0 | UINT64_C(0), |
10226 | 0 | UINT64_C(0), |
10227 | 0 | UINT64_C(0), |
10228 | 0 | UINT64_C(0), |
10229 | 0 | UINT64_C(0), |
10230 | 0 | UINT64_C(0), |
10231 | 0 | UINT64_C(0), |
10232 | 0 | UINT64_C(0), |
10233 | 0 | UINT64_C(0), |
10234 | 0 | UINT64_C(0), |
10235 | 0 | UINT64_C(0), |
10236 | 0 | UINT64_C(0), |
10237 | 0 | UINT64_C(0), |
10238 | 0 | UINT64_C(0), |
10239 | 0 | UINT64_C(0), |
10240 | 0 | UINT64_C(0), |
10241 | 0 | UINT64_C(0), |
10242 | 0 | UINT64_C(0), |
10243 | 0 | UINT64_C(0), |
10244 | 0 | UINT64_C(0), |
10245 | 0 | UINT64_C(0), |
10246 | 0 | UINT64_C(0), |
10247 | 0 | UINT64_C(0), |
10248 | 0 | UINT64_C(0), |
10249 | 0 | UINT64_C(0), |
10250 | 0 | UINT64_C(0), |
10251 | 0 | UINT64_C(0), |
10252 | 0 | UINT64_C(0), |
10253 | 0 | UINT64_C(0), |
10254 | 0 | UINT64_C(0), |
10255 | 0 | UINT64_C(0), |
10256 | 0 | UINT64_C(0), |
10257 | 0 | UINT64_C(0), |
10258 | 0 | UINT64_C(0), |
10259 | 0 | UINT64_C(0), |
10260 | 0 | UINT64_C(0), |
10261 | 0 | UINT64_C(0), |
10262 | 0 | UINT64_C(0), |
10263 | 0 | UINT64_C(0), |
10264 | 0 | UINT64_C(0), |
10265 | 0 | UINT64_C(0), |
10266 | 0 | UINT64_C(0), |
10267 | 0 | UINT64_C(0), |
10268 | 0 | UINT64_C(0), |
10269 | 0 | UINT64_C(0), |
10270 | 0 | UINT64_C(0), |
10271 | 0 | UINT64_C(0), |
10272 | 0 | UINT64_C(0), |
10273 | 0 | UINT64_C(0), |
10274 | 0 | UINT64_C(0), |
10275 | 0 | UINT64_C(0), |
10276 | 0 | UINT64_C(0), |
10277 | 0 | UINT64_C(0), |
10278 | 0 | UINT64_C(0), |
10279 | 0 | UINT64_C(0), |
10280 | 0 | UINT64_C(0), |
10281 | 0 | UINT64_C(0), |
10282 | 0 | UINT64_C(0), |
10283 | 0 | UINT64_C(0), |
10284 | 0 | UINT64_C(0), |
10285 | 0 | UINT64_C(0), |
10286 | 0 | UINT64_C(0), |
10287 | 0 | UINT64_C(0), |
10288 | 0 | UINT64_C(0), |
10289 | 0 | UINT64_C(0), |
10290 | 0 | UINT64_C(0), |
10291 | 0 | UINT64_C(0), |
10292 | 0 | UINT64_C(0), |
10293 | 0 | UINT64_C(0), |
10294 | 0 | UINT64_C(0), |
10295 | 0 | UINT64_C(0), |
10296 | 0 | UINT64_C(0), |
10297 | 0 | UINT64_C(0), |
10298 | 0 | UINT64_C(0), |
10299 | 0 | UINT64_C(0), |
10300 | 0 | UINT64_C(0), |
10301 | 0 | UINT64_C(0), |
10302 | 0 | UINT64_C(0), |
10303 | 0 | UINT64_C(0), |
10304 | 0 | UINT64_C(0), |
10305 | 0 | UINT64_C(0), |
10306 | 0 | UINT64_C(0), |
10307 | 0 | UINT64_C(0), |
10308 | 0 | UINT64_C(0), |
10309 | 0 | UINT64_C(0), |
10310 | 0 | UINT64_C(0), |
10311 | 0 | UINT64_C(0), |
10312 | 0 | UINT64_C(0), |
10313 | 0 | UINT64_C(0), |
10314 | 0 | UINT64_C(0), |
10315 | 0 | UINT64_C(0), |
10316 | 0 | UINT64_C(0), |
10317 | 0 | UINT64_C(0), |
10318 | 0 | UINT64_C(0), |
10319 | 0 | UINT64_C(0), |
10320 | 0 | UINT64_C(0), |
10321 | 0 | UINT64_C(0), |
10322 | 0 | UINT64_C(0), |
10323 | 0 | UINT64_C(0), |
10324 | 0 | UINT64_C(0), |
10325 | 0 | UINT64_C(0), |
10326 | 0 | UINT64_C(0), |
10327 | 0 | UINT64_C(0), |
10328 | 0 | UINT64_C(0), |
10329 | 0 | UINT64_C(0), |
10330 | 0 | UINT64_C(0), |
10331 | 0 | UINT64_C(0), |
10332 | 0 | UINT64_C(0), |
10333 | 0 | UINT64_C(0), |
10334 | 0 | UINT64_C(0), |
10335 | 0 | UINT64_C(0), |
10336 | 0 | UINT64_C(0), |
10337 | 0 | UINT64_C(0), |
10338 | 0 | UINT64_C(0), |
10339 | 0 | UINT64_C(0), |
10340 | 0 | UINT64_C(0), |
10341 | 0 | UINT64_C(0), |
10342 | 0 | UINT64_C(0), |
10343 | 0 | UINT64_C(0), |
10344 | 0 | UINT64_C(0), |
10345 | 0 | UINT64_C(0), |
10346 | 0 | UINT64_C(0), |
10347 | 0 | UINT64_C(0), |
10348 | 0 | UINT64_C(0), |
10349 | 0 | UINT64_C(0), |
10350 | 0 | UINT64_C(0), |
10351 | 0 | UINT64_C(0), |
10352 | 0 | UINT64_C(0), |
10353 | 0 | UINT64_C(0), |
10354 | 0 | UINT64_C(0), |
10355 | 0 | UINT64_C(0), |
10356 | 0 | UINT64_C(0), |
10357 | 0 | UINT64_C(0), |
10358 | 0 | UINT64_C(0), |
10359 | 0 | UINT64_C(0), |
10360 | 0 | UINT64_C(0), |
10361 | 0 | UINT64_C(0), |
10362 | 0 | UINT64_C(0), |
10363 | 0 | UINT64_C(0), |
10364 | 0 | UINT64_C(0), |
10365 | 0 | UINT64_C(0), |
10366 | 0 | UINT64_C(0), |
10367 | 0 | UINT64_C(0), |
10368 | 0 | UINT64_C(0), |
10369 | 0 | UINT64_C(0), |
10370 | 0 | UINT64_C(0), |
10371 | 0 | UINT64_C(0), |
10372 | 0 | UINT64_C(0), |
10373 | 0 | UINT64_C(0), |
10374 | 0 | UINT64_C(0), |
10375 | 0 | UINT64_C(0), |
10376 | 0 | UINT64_C(0), |
10377 | 0 | UINT64_C(0), |
10378 | 0 | UINT64_C(0), |
10379 | 0 | UINT64_C(0), |
10380 | 0 | UINT64_C(0), |
10381 | 0 | UINT64_C(0), |
10382 | 0 | UINT64_C(0), |
10383 | 0 | UINT64_C(0), |
10384 | 0 | UINT64_C(0), |
10385 | 0 | UINT64_C(0), |
10386 | 0 | UINT64_C(0), |
10387 | 0 | UINT64_C(0), |
10388 | 0 | UINT64_C(0), |
10389 | 0 | UINT64_C(0), |
10390 | 0 | UINT64_C(0), |
10391 | 0 | UINT64_C(0), |
10392 | 0 | UINT64_C(0), |
10393 | 0 | UINT64_C(0), |
10394 | 0 | UINT64_C(0), |
10395 | 0 | UINT64_C(0), |
10396 | 0 | UINT64_C(0), |
10397 | 0 | UINT64_C(0), |
10398 | 0 | UINT64_C(0), |
10399 | 0 | UINT64_C(0), |
10400 | 0 | UINT64_C(0), |
10401 | 0 | UINT64_C(0), |
10402 | 0 | UINT64_C(0), |
10403 | 0 | UINT64_C(0), |
10404 | 0 | UINT64_C(0), |
10405 | 0 | UINT64_C(0), |
10406 | 0 | UINT64_C(0), |
10407 | 0 | UINT64_C(0), |
10408 | 0 | UINT64_C(0), |
10409 | 0 | UINT64_C(0), |
10410 | 0 | UINT64_C(0), |
10411 | 0 | UINT64_C(0), |
10412 | 0 | UINT64_C(0), |
10413 | 0 | UINT64_C(0), |
10414 | 0 | UINT64_C(0), |
10415 | 0 | UINT64_C(0), |
10416 | 0 | UINT64_C(0), |
10417 | 0 | UINT64_C(0), |
10418 | 0 | UINT64_C(0), |
10419 | 0 | UINT64_C(0), |
10420 | 0 | UINT64_C(0), |
10421 | 0 | UINT64_C(0), |
10422 | 0 | UINT64_C(0), |
10423 | 0 | UINT64_C(0), |
10424 | 0 | UINT64_C(0), |
10425 | 0 | UINT64_C(0), |
10426 | 0 | UINT64_C(0), |
10427 | 0 | UINT64_C(0), |
10428 | 0 | UINT64_C(0), |
10429 | 0 | UINT64_C(0), |
10430 | 0 | UINT64_C(0), |
10431 | 0 | UINT64_C(0), |
10432 | 0 | UINT64_C(0), |
10433 | 0 | UINT64_C(0), |
10434 | 0 | UINT64_C(0), |
10435 | 0 | UINT64_C(0), |
10436 | 0 | UINT64_C(0), |
10437 | 0 | UINT64_C(0), |
10438 | 0 | UINT64_C(0), |
10439 | 0 | UINT64_C(0), |
10440 | 0 | UINT64_C(0), |
10441 | 0 | UINT64_C(0), |
10442 | 0 | UINT64_C(0), |
10443 | 0 | UINT64_C(0), |
10444 | 0 | UINT64_C(0), |
10445 | 0 | UINT64_C(0), |
10446 | 0 | UINT64_C(0), |
10447 | 0 | UINT64_C(0), |
10448 | 0 | UINT64_C(0), |
10449 | 0 | UINT64_C(0), |
10450 | 0 | UINT64_C(0), |
10451 | 0 | UINT64_C(0), |
10452 | 0 | UINT64_C(0), |
10453 | 0 | UINT64_C(0), |
10454 | 0 | UINT64_C(0), |
10455 | 0 | UINT64_C(0), |
10456 | 0 | UINT64_C(0), |
10457 | 0 | UINT64_C(0), |
10458 | 0 | UINT64_C(0), |
10459 | 0 | UINT64_C(0), |
10460 | 0 | UINT64_C(0), |
10461 | 0 | UINT64_C(0), |
10462 | 0 | UINT64_C(0), |
10463 | 0 | UINT64_C(0), |
10464 | 0 | UINT64_C(0), |
10465 | 0 | UINT64_C(0), |
10466 | 0 | UINT64_C(0), |
10467 | 0 | UINT64_C(0), |
10468 | 0 | UINT64_C(0), |
10469 | 0 | UINT64_C(0), |
10470 | 0 | UINT64_C(0), |
10471 | 0 | UINT64_C(0), |
10472 | 0 | UINT64_C(0), |
10473 | 0 | UINT64_C(0), |
10474 | 0 | UINT64_C(0), |
10475 | 0 | UINT64_C(0), |
10476 | 0 | UINT64_C(0), |
10477 | 0 | UINT64_C(0), |
10478 | 0 | UINT64_C(0), |
10479 | 0 | UINT64_C(0), |
10480 | 0 | UINT64_C(0), |
10481 | 0 | UINT64_C(0), |
10482 | 0 | UINT64_C(0), |
10483 | 0 | UINT64_C(0), |
10484 | 0 | UINT64_C(0), |
10485 | 0 | UINT64_C(0), |
10486 | 0 | UINT64_C(0), |
10487 | 0 | UINT64_C(0), |
10488 | 0 | UINT64_C(0), |
10489 | 0 | UINT64_C(0), |
10490 | 0 | UINT64_C(0), |
10491 | 0 | UINT64_C(0), |
10492 | 0 | UINT64_C(0), |
10493 | 0 | UINT64_C(0), |
10494 | 0 | UINT64_C(0), |
10495 | 0 | UINT64_C(0), |
10496 | 0 | UINT64_C(0), |
10497 | 0 | UINT64_C(0), |
10498 | 0 | UINT64_C(0), |
10499 | 0 | UINT64_C(0), |
10500 | 0 | UINT64_C(0), |
10501 | 0 | UINT64_C(0), |
10502 | 0 | UINT64_C(0), |
10503 | 0 | UINT64_C(0), |
10504 | 0 | UINT64_C(0), |
10505 | 0 | UINT64_C(0), |
10506 | 0 | UINT64_C(0), |
10507 | 0 | UINT64_C(0), |
10508 | 0 | UINT64_C(0), |
10509 | 0 | UINT64_C(0), |
10510 | 0 | UINT64_C(0), |
10511 | 0 | UINT64_C(0), |
10512 | 0 | UINT64_C(0), |
10513 | 0 | UINT64_C(0), |
10514 | 0 | UINT64_C(0), |
10515 | 0 | UINT64_C(0), |
10516 | 0 | UINT64_C(0), |
10517 | 0 | UINT64_C(0), |
10518 | 0 | UINT64_C(0), |
10519 | 0 | UINT64_C(0), |
10520 | 0 | UINT64_C(0), |
10521 | 0 | UINT64_C(0), |
10522 | 0 | UINT64_C(0), |
10523 | 0 | UINT64_C(0), |
10524 | 0 | UINT64_C(0), |
10525 | 0 | UINT64_C(0), |
10526 | 0 | UINT64_C(0), |
10527 | 0 | UINT64_C(0), |
10528 | 0 | UINT64_C(0), |
10529 | 0 | UINT64_C(0), |
10530 | 0 | UINT64_C(0), |
10531 | 0 | UINT64_C(0), |
10532 | 0 | UINT64_C(0), |
10533 | 0 | UINT64_C(0), |
10534 | 0 | UINT64_C(0), |
10535 | 0 | UINT64_C(0), |
10536 | 0 | UINT64_C(0), |
10537 | 0 | UINT64_C(0), |
10538 | 0 | UINT64_C(0), |
10539 | 0 | UINT64_C(0), |
10540 | 0 | UINT64_C(0), |
10541 | 0 | UINT64_C(0), |
10542 | 0 | UINT64_C(0), |
10543 | 0 | UINT64_C(0), |
10544 | 0 | UINT64_C(0), |
10545 | 0 | UINT64_C(0), |
10546 | 0 | UINT64_C(0), |
10547 | 0 | UINT64_C(0), |
10548 | 0 | UINT64_C(0), |
10549 | 0 | UINT64_C(0), |
10550 | 0 | UINT64_C(0), |
10551 | 0 | UINT64_C(0), |
10552 | 0 | UINT64_C(0), |
10553 | 0 | UINT64_C(0), |
10554 | 0 | UINT64_C(0), |
10555 | 0 | UINT64_C(0), |
10556 | 0 | UINT64_C(0), |
10557 | 0 | UINT64_C(0), |
10558 | 0 | UINT64_C(0), |
10559 | 0 | UINT64_C(0), |
10560 | 0 | UINT64_C(0), |
10561 | 0 | UINT64_C(0), |
10562 | 0 | UINT64_C(0), |
10563 | 0 | UINT64_C(0), |
10564 | 0 | UINT64_C(0), |
10565 | 0 | UINT64_C(0), |
10566 | 0 | UINT64_C(0), |
10567 | 0 | UINT64_C(0), |
10568 | 0 | UINT64_C(0), |
10569 | 0 | UINT64_C(0), |
10570 | 0 | UINT64_C(0), |
10571 | 0 | UINT64_C(0), |
10572 | 0 | UINT64_C(0), |
10573 | 0 | UINT64_C(0), |
10574 | 0 | UINT64_C(0), |
10575 | 0 | UINT64_C(0), |
10576 | 0 | UINT64_C(0), |
10577 | 0 | UINT64_C(0), |
10578 | 0 | UINT64_C(0), |
10579 | 0 | UINT64_C(0), |
10580 | 0 | UINT64_C(0), |
10581 | 0 | UINT64_C(0), |
10582 | 0 | UINT64_C(0), |
10583 | 0 | UINT64_C(0), |
10584 | 0 | UINT64_C(0), |
10585 | 0 | UINT64_C(0), |
10586 | 0 | UINT64_C(0), |
10587 | 0 | UINT64_C(0), |
10588 | 0 | UINT64_C(0), |
10589 | 0 | UINT64_C(0), |
10590 | 0 | UINT64_C(0), |
10591 | 0 | UINT64_C(0), |
10592 | 0 | UINT64_C(0), |
10593 | 0 | UINT64_C(0), |
10594 | 0 | UINT64_C(0), |
10595 | 0 | UINT64_C(0), |
10596 | 0 | UINT64_C(0), |
10597 | 0 | UINT64_C(0), |
10598 | 0 | UINT64_C(0), |
10599 | 0 | UINT64_C(0), |
10600 | 0 | UINT64_C(0), |
10601 | 0 | UINT64_C(0), |
10602 | 0 | UINT64_C(0), |
10603 | 0 | UINT64_C(0), |
10604 | 0 | UINT64_C(0), |
10605 | 0 | UINT64_C(0), |
10606 | 0 | UINT64_C(0), |
10607 | 0 | UINT64_C(0), |
10608 | 0 | UINT64_C(0), |
10609 | 0 | UINT64_C(0), |
10610 | 0 | UINT64_C(0), |
10611 | 0 | UINT64_C(0), |
10612 | 0 | UINT64_C(0), |
10613 | 0 | UINT64_C(0), |
10614 | 0 | UINT64_C(0), |
10615 | 0 | UINT64_C(0), |
10616 | 0 | UINT64_C(0), |
10617 | 0 | UINT64_C(0), |
10618 | 0 | UINT64_C(0), |
10619 | 0 | UINT64_C(0), |
10620 | 0 | UINT64_C(0), |
10621 | 0 | UINT64_C(0), |
10622 | 0 | UINT64_C(0), |
10623 | 0 | UINT64_C(0), |
10624 | 0 | UINT64_C(0), |
10625 | 0 | UINT64_C(0), |
10626 | 0 | UINT64_C(0), |
10627 | 0 | UINT64_C(0), |
10628 | 0 | UINT64_C(0), |
10629 | 0 | UINT64_C(0), |
10630 | 0 | UINT64_C(0), |
10631 | 0 | UINT64_C(0), |
10632 | 0 | UINT64_C(0), |
10633 | 0 | UINT64_C(0), |
10634 | 0 | UINT64_C(0), |
10635 | 0 | UINT64_C(0), |
10636 | 0 | UINT64_C(0), |
10637 | 0 | UINT64_C(0), |
10638 | 0 | UINT64_C(0), |
10639 | 0 | UINT64_C(0), |
10640 | 0 | UINT64_C(0), |
10641 | 0 | UINT64_C(0), |
10642 | 0 | UINT64_C(0), |
10643 | 0 | UINT64_C(0), |
10644 | 0 | UINT64_C(0), |
10645 | 0 | UINT64_C(0), |
10646 | 0 | UINT64_C(0), |
10647 | 0 | UINT64_C(0), |
10648 | 0 | UINT64_C(0), |
10649 | 0 | UINT64_C(0), |
10650 | 0 | UINT64_C(0), |
10651 | 0 | UINT64_C(0), |
10652 | 0 | UINT64_C(0), |
10653 | 0 | UINT64_C(0), |
10654 | 0 | UINT64_C(0), |
10655 | 0 | UINT64_C(0), |
10656 | 0 | UINT64_C(0), |
10657 | 0 | UINT64_C(0), |
10658 | 0 | UINT64_C(0), |
10659 | 0 | UINT64_C(0), |
10660 | 0 | UINT64_C(0), |
10661 | 0 | UINT64_C(0), |
10662 | 0 | UINT64_C(0), |
10663 | 0 | UINT64_C(0), |
10664 | 0 | UINT64_C(0), |
10665 | 0 | UINT64_C(0), |
10666 | 0 | UINT64_C(0), |
10667 | 0 | UINT64_C(0), |
10668 | 0 | UINT64_C(0), |
10669 | 0 | UINT64_C(0), |
10670 | 0 | UINT64_C(0), |
10671 | 0 | UINT64_C(0), |
10672 | 0 | UINT64_C(0), |
10673 | 0 | UINT64_C(0), |
10674 | 0 | UINT64_C(0), |
10675 | 0 | UINT64_C(0), |
10676 | 0 | UINT64_C(0), |
10677 | 0 | UINT64_C(0), |
10678 | 0 | UINT64_C(0), |
10679 | 0 | UINT64_C(0), |
10680 | 0 | UINT64_C(0), |
10681 | 0 | UINT64_C(0), |
10682 | 0 | UINT64_C(0), |
10683 | 0 | UINT64_C(0), |
10684 | 0 | UINT64_C(0), |
10685 | 0 | UINT64_C(0), |
10686 | 0 | UINT64_C(0), |
10687 | 0 | UINT64_C(0), |
10688 | 0 | UINT64_C(0), |
10689 | 0 | UINT64_C(0), |
10690 | 0 | UINT64_C(0), |
10691 | 0 | UINT64_C(0), |
10692 | 0 | UINT64_C(0), |
10693 | 0 | UINT64_C(0), |
10694 | 0 | UINT64_C(0), |
10695 | 0 | UINT64_C(0), |
10696 | 0 | UINT64_C(0), |
10697 | 0 | UINT64_C(0), |
10698 | 0 | UINT64_C(0), |
10699 | 0 | UINT64_C(0), |
10700 | 0 | UINT64_C(0), |
10701 | 0 | UINT64_C(0), |
10702 | 0 | UINT64_C(0), |
10703 | 0 | UINT64_C(0), |
10704 | 0 | UINT64_C(0), |
10705 | 0 | UINT64_C(0), |
10706 | 0 | UINT64_C(0), |
10707 | 0 | UINT64_C(0), |
10708 | 0 | UINT64_C(0), |
10709 | 0 | UINT64_C(0), |
10710 | 0 | UINT64_C(0), |
10711 | 0 | UINT64_C(0), |
10712 | 0 | UINT64_C(0), |
10713 | 0 | UINT64_C(0), |
10714 | 0 | UINT64_C(0), |
10715 | 0 | UINT64_C(0), |
10716 | 0 | UINT64_C(0), |
10717 | 0 | UINT64_C(0), |
10718 | 0 | UINT64_C(0), |
10719 | 0 | UINT64_C(0), |
10720 | 0 | UINT64_C(0), |
10721 | 0 | UINT64_C(0), |
10722 | 0 | UINT64_C(0), |
10723 | 0 | UINT64_C(0), |
10724 | 0 | UINT64_C(0), |
10725 | 0 | UINT64_C(0), |
10726 | 0 | UINT64_C(0), |
10727 | 0 | UINT64_C(0), |
10728 | 0 | UINT64_C(0), |
10729 | 0 | UINT64_C(0), |
10730 | 0 | UINT64_C(0), |
10731 | 0 | UINT64_C(0), |
10732 | 0 | UINT64_C(0), |
10733 | 0 | UINT64_C(0), |
10734 | 0 | UINT64_C(0), |
10735 | 0 | UINT64_C(0), |
10736 | 0 | UINT64_C(0), |
10737 | 0 | UINT64_C(0), |
10738 | 0 | UINT64_C(0), |
10739 | 0 | UINT64_C(0), |
10740 | 0 | UINT64_C(0), |
10741 | 0 | UINT64_C(0), |
10742 | 0 | UINT64_C(0), |
10743 | 0 | UINT64_C(0), |
10744 | 0 | UINT64_C(0), |
10745 | 0 | UINT64_C(0), |
10746 | 0 | UINT64_C(0), |
10747 | 0 | UINT64_C(0), |
10748 | 0 | UINT64_C(0), |
10749 | 0 | UINT64_C(0), |
10750 | 0 | UINT64_C(0), |
10751 | 0 | UINT64_C(0), |
10752 | 0 | UINT64_C(0), |
10753 | 0 | UINT64_C(0), |
10754 | 0 | UINT64_C(0), |
10755 | 0 | UINT64_C(0), |
10756 | 0 | UINT64_C(0), |
10757 | 0 | UINT64_C(0), |
10758 | 0 | UINT64_C(0), |
10759 | 0 | UINT64_C(0), |
10760 | 0 | UINT64_C(0), |
10761 | 0 | UINT64_C(0), |
10762 | 0 | UINT64_C(0), |
10763 | 0 | UINT64_C(0), |
10764 | 0 | UINT64_C(0), |
10765 | 0 | UINT64_C(0), |
10766 | 0 | UINT64_C(0), |
10767 | 0 | UINT64_C(0), |
10768 | 0 | UINT64_C(0), |
10769 | 0 | UINT64_C(0), |
10770 | 0 | UINT64_C(0), |
10771 | 0 | UINT64_C(0), |
10772 | 0 | UINT64_C(0), |
10773 | 0 | UINT64_C(0), |
10774 | 0 | UINT64_C(0), |
10775 | 0 | UINT64_C(0), |
10776 | 0 | UINT64_C(0), |
10777 | 0 | UINT64_C(0), |
10778 | 0 | UINT64_C(0), |
10779 | 0 | UINT64_C(0), |
10780 | 0 | UINT64_C(0), |
10781 | 0 | UINT64_C(0), |
10782 | 0 | UINT64_C(0), |
10783 | 0 | UINT64_C(0), |
10784 | 0 | UINT64_C(0), |
10785 | 0 | UINT64_C(0), |
10786 | 0 | UINT64_C(0), |
10787 | 0 | UINT64_C(0), |
10788 | 0 | UINT64_C(0), |
10789 | 0 | UINT64_C(0), |
10790 | 0 | UINT64_C(0), |
10791 | 0 | UINT64_C(0), |
10792 | 0 | UINT64_C(0), |
10793 | 0 | UINT64_C(0), |
10794 | 0 | UINT64_C(0), |
10795 | 0 | UINT64_C(0), |
10796 | 0 | UINT64_C(0), |
10797 | 0 | UINT64_C(0), |
10798 | 0 | UINT64_C(0), |
10799 | 0 | UINT64_C(0), |
10800 | 0 | UINT64_C(0), |
10801 | 0 | UINT64_C(0), |
10802 | 0 | UINT64_C(0), |
10803 | 0 | UINT64_C(0), |
10804 | 0 | UINT64_C(0), |
10805 | 0 | UINT64_C(0), |
10806 | 0 | UINT64_C(0), |
10807 | 0 | UINT64_C(0), |
10808 | 0 | UINT64_C(0), |
10809 | 0 | UINT64_C(0), |
10810 | 0 | UINT64_C(0), |
10811 | 0 | UINT64_C(0), |
10812 | 0 | UINT64_C(0), |
10813 | 0 | UINT64_C(0), |
10814 | 0 | UINT64_C(0), |
10815 | 0 | UINT64_C(0), |
10816 | 0 | UINT64_C(0), |
10817 | 0 | UINT64_C(0), |
10818 | 0 | UINT64_C(0), |
10819 | 0 | UINT64_C(0), |
10820 | 0 | UINT64_C(0), |
10821 | 0 | UINT64_C(0), |
10822 | 0 | UINT64_C(0), |
10823 | 0 | UINT64_C(0), |
10824 | 0 | UINT64_C(0), |
10825 | 0 | UINT64_C(0), |
10826 | 0 | UINT64_C(0), |
10827 | 0 | UINT64_C(0), |
10828 | 0 | UINT64_C(0), |
10829 | 0 | UINT64_C(0), |
10830 | 0 | UINT64_C(0), |
10831 | 0 | UINT64_C(0), |
10832 | 0 | UINT64_C(0), |
10833 | 0 | UINT64_C(0), |
10834 | 0 | UINT64_C(0), |
10835 | 0 | UINT64_C(0), |
10836 | 0 | UINT64_C(0), |
10837 | 0 | UINT64_C(0), |
10838 | 0 | UINT64_C(0), |
10839 | 0 | UINT64_C(0), |
10840 | 0 | UINT64_C(0), |
10841 | 0 | UINT64_C(0), |
10842 | 0 | UINT64_C(0), |
10843 | 0 | UINT64_C(0), |
10844 | 0 | UINT64_C(0), |
10845 | 0 | UINT64_C(0), |
10846 | 0 | UINT64_C(0), |
10847 | 0 | UINT64_C(0), |
10848 | 0 | UINT64_C(0), |
10849 | 0 | UINT64_C(0), |
10850 | 0 | UINT64_C(0), |
10851 | 0 | UINT64_C(0), |
10852 | 0 | UINT64_C(0), |
10853 | 0 | UINT64_C(0), |
10854 | 0 | UINT64_C(0), |
10855 | 0 | UINT64_C(0), |
10856 | 0 | UINT64_C(0), |
10857 | 0 | UINT64_C(0), |
10858 | 0 | UINT64_C(0), |
10859 | 0 | UINT64_C(0), |
10860 | 0 | UINT64_C(0), |
10861 | 0 | UINT64_C(0), |
10862 | 0 | UINT64_C(0), |
10863 | 0 | UINT64_C(0), |
10864 | 0 | UINT64_C(0), |
10865 | 0 | UINT64_C(0), |
10866 | 0 | UINT64_C(0), |
10867 | 0 | UINT64_C(0), |
10868 | 0 | UINT64_C(0), |
10869 | 0 | UINT64_C(0), |
10870 | 0 | UINT64_C(0), |
10871 | 0 | UINT64_C(0), |
10872 | 0 | UINT64_C(0), |
10873 | 0 | UINT64_C(0), |
10874 | 0 | UINT64_C(0), |
10875 | 0 | UINT64_C(0), |
10876 | 0 | UINT64_C(0), |
10877 | 0 | UINT64_C(0), |
10878 | 0 | UINT64_C(0), |
10879 | 0 | UINT64_C(0), |
10880 | 0 | UINT64_C(0), |
10881 | 0 | UINT64_C(0), |
10882 | 0 | UINT64_C(0), |
10883 | 0 | UINT64_C(0), |
10884 | 0 | UINT64_C(0), |
10885 | 0 | UINT64_C(0), |
10886 | 0 | UINT64_C(0), |
10887 | 0 | UINT64_C(0), |
10888 | 0 | UINT64_C(0), |
10889 | 0 | UINT64_C(0), |
10890 | 0 | UINT64_C(0), |
10891 | 0 | UINT64_C(0), |
10892 | 0 | UINT64_C(0), |
10893 | 0 | UINT64_C(0), |
10894 | 0 | UINT64_C(0), |
10895 | 0 | UINT64_C(0), |
10896 | 0 | UINT64_C(0), |
10897 | 0 | UINT64_C(0), |
10898 | 0 | UINT64_C(0), |
10899 | 0 | UINT64_C(0), |
10900 | 0 | UINT64_C(0), |
10901 | 0 | UINT64_C(0), |
10902 | 0 | UINT64_C(0), |
10903 | 0 | UINT64_C(0), |
10904 | 0 | UINT64_C(0), |
10905 | 0 | UINT64_C(0), |
10906 | 0 | UINT64_C(0), |
10907 | 0 | UINT64_C(0), |
10908 | 0 | UINT64_C(0), |
10909 | 0 | UINT64_C(0), |
10910 | 0 | UINT64_C(0), |
10911 | 0 | UINT64_C(0), |
10912 | 0 | UINT64_C(0), |
10913 | 0 | UINT64_C(0), |
10914 | 0 | UINT64_C(0), |
10915 | 0 | UINT64_C(0), |
10916 | 0 | UINT64_C(0), |
10917 | 0 | UINT64_C(0), |
10918 | 0 | UINT64_C(0), |
10919 | 0 | UINT64_C(0), |
10920 | 0 | UINT64_C(0), |
10921 | 0 | UINT64_C(0), |
10922 | 0 | UINT64_C(0), |
10923 | 0 | UINT64_C(0), |
10924 | 0 | UINT64_C(0), |
10925 | 0 | UINT64_C(0), |
10926 | 0 | UINT64_C(0), |
10927 | 0 | UINT64_C(0), |
10928 | 0 | UINT64_C(0), |
10929 | 0 | UINT64_C(0), |
10930 | 0 | UINT64_C(0), |
10931 | 0 | UINT64_C(0), |
10932 | 0 | UINT64_C(0), |
10933 | 0 | UINT64_C(0), |
10934 | 0 | UINT64_C(0), |
10935 | 0 | UINT64_C(0), |
10936 | 0 | UINT64_C(0), |
10937 | 0 | UINT64_C(0), |
10938 | 0 | UINT64_C(0), |
10939 | 0 | UINT64_C(0), |
10940 | 0 | UINT64_C(0), |
10941 | 0 | UINT64_C(0), |
10942 | 0 | UINT64_C(0), |
10943 | 0 | UINT64_C(0), |
10944 | 0 | UINT64_C(0), |
10945 | 0 | UINT64_C(0), |
10946 | 0 | UINT64_C(0), |
10947 | 0 | UINT64_C(0), |
10948 | 0 | UINT64_C(0), |
10949 | 0 | UINT64_C(0), |
10950 | 0 | UINT64_C(0), |
10951 | 0 | UINT64_C(0), |
10952 | 0 | UINT64_C(0), |
10953 | 0 | UINT64_C(0), |
10954 | 0 | UINT64_C(0), |
10955 | 0 | UINT64_C(0), |
10956 | 0 | UINT64_C(0), |
10957 | 0 | UINT64_C(0), |
10958 | 0 | UINT64_C(0), |
10959 | 0 | UINT64_C(0), |
10960 | 0 | UINT64_C(0), |
10961 | 0 | UINT64_C(0), |
10962 | 0 | UINT64_C(0), |
10963 | 0 | UINT64_C(0), |
10964 | 0 | UINT64_C(0), |
10965 | 0 | UINT64_C(0), |
10966 | 0 | UINT64_C(0), |
10967 | 0 | UINT64_C(0), |
10968 | 0 | UINT64_C(0), |
10969 | 0 | UINT64_C(0), |
10970 | 0 | UINT64_C(0), |
10971 | 0 | UINT64_C(0), |
10972 | 0 | UINT64_C(0), |
10973 | 0 | UINT64_C(0), |
10974 | 0 | UINT64_C(0), |
10975 | 0 | UINT64_C(0), |
10976 | 0 | UINT64_C(0), |
10977 | 0 | UINT64_C(0), |
10978 | 0 | UINT64_C(0), |
10979 | 0 | UINT64_C(0), |
10980 | 0 | UINT64_C(0), |
10981 | 0 | UINT64_C(0), |
10982 | 0 | UINT64_C(0), |
10983 | 0 | UINT64_C(0), |
10984 | 0 | UINT64_C(0), |
10985 | 0 | UINT64_C(0), |
10986 | 0 | UINT64_C(0), |
10987 | 0 | UINT64_C(0), |
10988 | 0 | UINT64_C(0), |
10989 | 0 | UINT64_C(0), |
10990 | 0 | UINT64_C(0), |
10991 | 0 | UINT64_C(0), |
10992 | 0 | UINT64_C(0), |
10993 | 0 | UINT64_C(0), |
10994 | 0 | UINT64_C(0), |
10995 | 0 | UINT64_C(0), |
10996 | 0 | UINT64_C(0), |
10997 | 0 | UINT64_C(0), |
10998 | 0 | UINT64_C(0), |
10999 | 0 | UINT64_C(0), |
11000 | 0 | UINT64_C(0), |
11001 | 0 | UINT64_C(0), |
11002 | 0 | UINT64_C(0), |
11003 | 0 | UINT64_C(0), |
11004 | 0 | UINT64_C(0), |
11005 | 0 | UINT64_C(0), |
11006 | 0 | UINT64_C(0), |
11007 | 0 | UINT64_C(0), |
11008 | 0 | UINT64_C(0), |
11009 | 0 | UINT64_C(0), |
11010 | 0 | UINT64_C(0), |
11011 | 0 | UINT64_C(0), |
11012 | 0 | UINT64_C(0), |
11013 | 0 | UINT64_C(0), |
11014 | 0 | UINT64_C(0), |
11015 | 0 | UINT64_C(0), |
11016 | 0 | UINT64_C(0), |
11017 | 0 | UINT64_C(0), |
11018 | 0 | UINT64_C(0), |
11019 | 0 | UINT64_C(0), |
11020 | 0 | UINT64_C(0), |
11021 | 0 | UINT64_C(0), |
11022 | 0 | UINT64_C(0), |
11023 | 0 | UINT64_C(0), |
11024 | 0 | UINT64_C(0), |
11025 | 0 | UINT64_C(0), |
11026 | 0 | UINT64_C(0), |
11027 | 0 | UINT64_C(0), |
11028 | 0 | UINT64_C(0), |
11029 | 0 | UINT64_C(0), |
11030 | 0 | UINT64_C(0), |
11031 | 0 | UINT64_C(0), |
11032 | 0 | UINT64_C(0), |
11033 | 0 | UINT64_C(0), |
11034 | 0 | UINT64_C(0), |
11035 | 0 | UINT64_C(0), |
11036 | 0 | UINT64_C(0), |
11037 | 0 | UINT64_C(0), |
11038 | 0 | UINT64_C(0), |
11039 | 0 | UINT64_C(0), |
11040 | 0 | UINT64_C(0), |
11041 | 0 | UINT64_C(0), |
11042 | 0 | UINT64_C(0), |
11043 | 0 | UINT64_C(0), |
11044 | 0 | UINT64_C(0), |
11045 | 0 | UINT64_C(0), |
11046 | 0 | UINT64_C(0), |
11047 | 0 | UINT64_C(0), |
11048 | 0 | UINT64_C(0), |
11049 | 0 | UINT64_C(0), |
11050 | 0 | UINT64_C(0), |
11051 | 0 | UINT64_C(0), |
11052 | 0 | UINT64_C(0), |
11053 | 0 | UINT64_C(0), |
11054 | 0 | UINT64_C(0), |
11055 | 0 | UINT64_C(0), |
11056 | 0 | UINT64_C(0), |
11057 | 0 | UINT64_C(0), |
11058 | 0 | UINT64_C(0), |
11059 | 0 | UINT64_C(0), |
11060 | 0 | UINT64_C(0), |
11061 | 0 | UINT64_C(0), |
11062 | 0 | UINT64_C(0), |
11063 | 0 | UINT64_C(0), |
11064 | 0 | UINT64_C(0), |
11065 | 0 | UINT64_C(0), |
11066 | 0 | UINT64_C(0), |
11067 | 0 | UINT64_C(0), |
11068 | 0 | UINT64_C(0), |
11069 | 0 | UINT64_C(0), |
11070 | 0 | UINT64_C(0), |
11071 | 0 | UINT64_C(0), |
11072 | 0 | UINT64_C(0), |
11073 | 0 | UINT64_C(0), |
11074 | 0 | UINT64_C(0), |
11075 | 0 | UINT64_C(0), |
11076 | 0 | UINT64_C(0), |
11077 | 0 | UINT64_C(0), |
11078 | 0 | UINT64_C(0), |
11079 | 0 | UINT64_C(0), |
11080 | 0 | UINT64_C(0), |
11081 | 0 | UINT64_C(0), |
11082 | 0 | UINT64_C(0), |
11083 | 0 | UINT64_C(0), |
11084 | 0 | UINT64_C(0), |
11085 | 0 | UINT64_C(0), |
11086 | 0 | UINT64_C(0), |
11087 | 0 | UINT64_C(0), |
11088 | 0 | UINT64_C(0), |
11089 | 0 | UINT64_C(0), |
11090 | 0 | UINT64_C(0), |
11091 | 0 | UINT64_C(0), |
11092 | 0 | UINT64_C(0), |
11093 | 0 | UINT64_C(0), |
11094 | 0 | UINT64_C(0), |
11095 | 0 | UINT64_C(0), |
11096 | 0 | UINT64_C(0), |
11097 | 0 | UINT64_C(0), |
11098 | 0 | UINT64_C(0), |
11099 | 0 | UINT64_C(0), |
11100 | 0 | UINT64_C(0), |
11101 | 0 | UINT64_C(0), |
11102 | 0 | UINT64_C(0), |
11103 | 0 | UINT64_C(0), |
11104 | 0 | UINT64_C(0), |
11105 | 0 | UINT64_C(0), |
11106 | 0 | UINT64_C(0), |
11107 | 0 | UINT64_C(0), |
11108 | 0 | UINT64_C(0), |
11109 | 0 | UINT64_C(0), |
11110 | 0 | UINT64_C(0), |
11111 | 0 | UINT64_C(0), |
11112 | 0 | UINT64_C(0), |
11113 | 0 | UINT64_C(0), |
11114 | 0 | UINT64_C(0), |
11115 | 0 | UINT64_C(0), |
11116 | 0 | UINT64_C(0), |
11117 | 0 | UINT64_C(0), |
11118 | 0 | UINT64_C(0), |
11119 | 0 | UINT64_C(0), |
11120 | 0 | UINT64_C(0), |
11121 | 0 | UINT64_C(0), |
11122 | 0 | UINT64_C(0), |
11123 | 0 | UINT64_C(0), |
11124 | 0 | UINT64_C(0), |
11125 | 0 | UINT64_C(0), |
11126 | 0 | UINT64_C(0), |
11127 | 0 | UINT64_C(0), |
11128 | 0 | UINT64_C(0), |
11129 | 0 | UINT64_C(0), |
11130 | 0 | UINT64_C(0), |
11131 | 0 | UINT64_C(0), |
11132 | 0 | UINT64_C(0), |
11133 | 0 | UINT64_C(0), |
11134 | 0 | UINT64_C(0), |
11135 | 0 | UINT64_C(0), |
11136 | 0 | UINT64_C(0), |
11137 | 0 | UINT64_C(0), |
11138 | 0 | UINT64_C(0), |
11139 | 0 | UINT64_C(0), |
11140 | 0 | UINT64_C(0), |
11141 | 0 | UINT64_C(0), |
11142 | 0 | UINT64_C(0), |
11143 | 0 | UINT64_C(0), |
11144 | 0 | UINT64_C(0), |
11145 | 0 | UINT64_C(0), |
11146 | 0 | UINT64_C(0), |
11147 | 0 | UINT64_C(0), |
11148 | 0 | UINT64_C(0), |
11149 | 0 | UINT64_C(0), |
11150 | 0 | UINT64_C(0), |
11151 | 0 | UINT64_C(0), |
11152 | 0 | UINT64_C(0), |
11153 | 0 | UINT64_C(0), |
11154 | 0 | UINT64_C(0), |
11155 | 0 | UINT64_C(0), |
11156 | 0 | UINT64_C(0), |
11157 | 0 | UINT64_C(0), |
11158 | 0 | UINT64_C(0), |
11159 | 0 | UINT64_C(0), |
11160 | 0 | UINT64_C(0), |
11161 | 0 | UINT64_C(0), |
11162 | 0 | UINT64_C(0), |
11163 | 0 | UINT64_C(0), |
11164 | 0 | UINT64_C(0), |
11165 | 0 | UINT64_C(0), |
11166 | 0 | UINT64_C(0), |
11167 | 0 | UINT64_C(0), |
11168 | 0 | UINT64_C(0), |
11169 | 0 | UINT64_C(0), |
11170 | 0 | UINT64_C(0), |
11171 | 0 | UINT64_C(0), |
11172 | 0 | UINT64_C(0), |
11173 | 0 | UINT64_C(0), |
11174 | 0 | UINT64_C(0), |
11175 | 0 | UINT64_C(0), |
11176 | 0 | UINT64_C(0), |
11177 | 0 | UINT64_C(0), |
11178 | 0 | UINT64_C(0), |
11179 | 0 | UINT64_C(0), |
11180 | 0 | UINT64_C(0), |
11181 | 0 | UINT64_C(0), |
11182 | 0 | UINT64_C(0), |
11183 | 0 | UINT64_C(0), |
11184 | 0 | UINT64_C(0), |
11185 | 0 | UINT64_C(0), |
11186 | 0 | UINT64_C(0), |
11187 | 0 | UINT64_C(0), |
11188 | 0 | UINT64_C(0), |
11189 | 0 | UINT64_C(0), |
11190 | 0 | UINT64_C(0), |
11191 | 0 | UINT64_C(0), |
11192 | 0 | UINT64_C(0), |
11193 | 0 | UINT64_C(0), |
11194 | 0 | UINT64_C(0), |
11195 | 0 | UINT64_C(0), |
11196 | 0 | UINT64_C(0), |
11197 | 0 | UINT64_C(0), |
11198 | 0 | UINT64_C(0), |
11199 | 0 | UINT64_C(0), |
11200 | 0 | UINT64_C(0), |
11201 | 0 | UINT64_C(0), |
11202 | 0 | UINT64_C(0), |
11203 | 0 | UINT64_C(0), |
11204 | 0 | UINT64_C(0), |
11205 | 0 | UINT64_C(0), |
11206 | 0 | UINT64_C(0), |
11207 | 0 | UINT64_C(0), |
11208 | 0 | UINT64_C(0), |
11209 | 0 | UINT64_C(0), |
11210 | 0 | UINT64_C(0), |
11211 | 0 | UINT64_C(0), |
11212 | 0 | UINT64_C(0), |
11213 | 0 | UINT64_C(0), |
11214 | 0 | UINT64_C(0), |
11215 | 0 | UINT64_C(0), |
11216 | 0 | UINT64_C(0), |
11217 | 0 | UINT64_C(0), |
11218 | 0 | UINT64_C(0), |
11219 | 0 | UINT64_C(0), |
11220 | 0 | UINT64_C(0), |
11221 | 0 | UINT64_C(0), |
11222 | 0 | UINT64_C(0), |
11223 | 0 | UINT64_C(0), |
11224 | 0 | UINT64_C(0), |
11225 | 0 | UINT64_C(0), |
11226 | 0 | UINT64_C(0), |
11227 | 0 | UINT64_C(0), |
11228 | 0 | UINT64_C(0), |
11229 | 0 | UINT64_C(0), |
11230 | 0 | UINT64_C(0), |
11231 | 0 | UINT64_C(0), |
11232 | 0 | UINT64_C(0), |
11233 | 0 | UINT64_C(0), |
11234 | 0 | UINT64_C(0), |
11235 | 0 | UINT64_C(0), |
11236 | 0 | UINT64_C(0), |
11237 | 0 | UINT64_C(0), |
11238 | 0 | UINT64_C(0), |
11239 | 0 | UINT64_C(0), |
11240 | 0 | UINT64_C(0), |
11241 | 0 | UINT64_C(0), |
11242 | 0 | UINT64_C(0), |
11243 | 0 | UINT64_C(0), |
11244 | 0 | UINT64_C(0), |
11245 | 0 | UINT64_C(0), |
11246 | 0 | UINT64_C(0), |
11247 | 0 | UINT64_C(0), |
11248 | 0 | UINT64_C(0), |
11249 | 0 | UINT64_C(0), |
11250 | 0 | UINT64_C(0), |
11251 | 0 | UINT64_C(0), |
11252 | 0 | UINT64_C(0), |
11253 | 0 | UINT64_C(0), |
11254 | 0 | UINT64_C(0), |
11255 | 0 | UINT64_C(0), |
11256 | 0 | UINT64_C(0), |
11257 | 0 | UINT64_C(0), |
11258 | 0 | UINT64_C(0), |
11259 | 0 | UINT64_C(0), |
11260 | 0 | UINT64_C(0), |
11261 | 0 | UINT64_C(0), |
11262 | 0 | UINT64_C(0), |
11263 | 0 | UINT64_C(0), |
11264 | 0 | UINT64_C(0), |
11265 | 0 | UINT64_C(0), |
11266 | 0 | UINT64_C(0), |
11267 | 0 | UINT64_C(0), |
11268 | 0 | UINT64_C(0), |
11269 | 0 | UINT64_C(0), |
11270 | 0 | UINT64_C(0), |
11271 | 0 | UINT64_C(0), |
11272 | 0 | UINT64_C(0), |
11273 | 0 | UINT64_C(0), |
11274 | 0 | UINT64_C(0), |
11275 | 0 | UINT64_C(0), |
11276 | 0 | UINT64_C(0), |
11277 | 0 | UINT64_C(0), |
11278 | 0 | UINT64_C(0), |
11279 | 0 | UINT64_C(0), |
11280 | 0 | UINT64_C(0), |
11281 | 0 | UINT64_C(0), |
11282 | 0 | UINT64_C(0), |
11283 | 0 | UINT64_C(0), |
11284 | 0 | UINT64_C(0), |
11285 | 0 | UINT64_C(0), |
11286 | 0 | UINT64_C(51), // ADD |
11287 | 0 | UINT64_C(19), // ADDI |
11288 | 0 | UINT64_C(27), // ADDIW |
11289 | 0 | UINT64_C(59), // ADDW |
11290 | 0 | UINT64_C(134217787), // ADD_UW |
11291 | 0 | UINT64_C(704643123), // AES32DSI |
11292 | 0 | UINT64_C(771751987), // AES32DSMI |
11293 | 0 | UINT64_C(570425395), // AES32ESI |
11294 | 0 | UINT64_C(637534259), // AES32ESMI |
11295 | 0 | UINT64_C(973078579), // AES64DS |
11296 | 0 | UINT64_C(1040187443), // AES64DSM |
11297 | 0 | UINT64_C(838860851), // AES64ES |
11298 | 0 | UINT64_C(905969715), // AES64ESM |
11299 | 0 | UINT64_C(805310483), // AES64IM |
11300 | 0 | UINT64_C(822087699), // AES64KS1I |
11301 | 0 | UINT64_C(2113929267), // AES64KS2 |
11302 | 0 | UINT64_C(12335), // AMOADD_D |
11303 | 0 | UINT64_C(67121199), // AMOADD_D_AQ |
11304 | 0 | UINT64_C(100675631), // AMOADD_D_AQ_RL |
11305 | 0 | UINT64_C(33566767), // AMOADD_D_RL |
11306 | 0 | UINT64_C(8239), // AMOADD_W |
11307 | 0 | UINT64_C(67117103), // AMOADD_W_AQ |
11308 | 0 | UINT64_C(100671535), // AMOADD_W_AQ_RL |
11309 | 0 | UINT64_C(33562671), // AMOADD_W_RL |
11310 | 0 | UINT64_C(1610625071), // AMOAND_D |
11311 | 0 | UINT64_C(1677733935), // AMOAND_D_AQ |
11312 | 0 | UINT64_C(1711288367), // AMOAND_D_AQ_RL |
11313 | 0 | UINT64_C(1644179503), // AMOAND_D_RL |
11314 | 0 | UINT64_C(1610620975), // AMOAND_W |
11315 | 0 | UINT64_C(1677729839), // AMOAND_W_AQ |
11316 | 0 | UINT64_C(1711284271), // AMOAND_W_AQ_RL |
11317 | 0 | UINT64_C(1644175407), // AMOAND_W_RL |
11318 | 0 | UINT64_C(671100975), // AMOCAS_D_RV32 |
11319 | 0 | UINT64_C(738209839), // AMOCAS_D_RV32_AQ |
11320 | 0 | UINT64_C(771764271), // AMOCAS_D_RV32_AQ_RL |
11321 | 0 | UINT64_C(704655407), // AMOCAS_D_RV32_RL |
11322 | 0 | UINT64_C(671100975), // AMOCAS_D_RV64 |
11323 | 0 | UINT64_C(738209839), // AMOCAS_D_RV64_AQ |
11324 | 0 | UINT64_C(771764271), // AMOCAS_D_RV64_AQ_RL |
11325 | 0 | UINT64_C(704655407), // AMOCAS_D_RV64_RL |
11326 | 0 | UINT64_C(671105071), // AMOCAS_Q |
11327 | 0 | UINT64_C(738213935), // AMOCAS_Q_AQ |
11328 | 0 | UINT64_C(771768367), // AMOCAS_Q_AQ_RL |
11329 | 0 | UINT64_C(704659503), // AMOCAS_Q_RL |
11330 | 0 | UINT64_C(671096879), // AMOCAS_W |
11331 | 0 | UINT64_C(738205743), // AMOCAS_W_AQ |
11332 | 0 | UINT64_C(771760175), // AMOCAS_W_AQ_RL |
11333 | 0 | UINT64_C(704651311), // AMOCAS_W_RL |
11334 | 0 | UINT64_C(3758108719), // AMOMAXU_D |
11335 | 0 | UINT64_C(3825217583), // AMOMAXU_D_AQ |
11336 | 0 | UINT64_C(3858772015), // AMOMAXU_D_AQ_RL |
11337 | 0 | UINT64_C(3791663151), // AMOMAXU_D_RL |
11338 | 0 | UINT64_C(3758104623), // AMOMAXU_W |
11339 | 0 | UINT64_C(3825213487), // AMOMAXU_W_AQ |
11340 | 0 | UINT64_C(3858767919), // AMOMAXU_W_AQ_RL |
11341 | 0 | UINT64_C(3791659055), // AMOMAXU_W_RL |
11342 | 0 | UINT64_C(2684366895), // AMOMAX_D |
11343 | 0 | UINT64_C(2751475759), // AMOMAX_D_AQ |
11344 | 0 | UINT64_C(2785030191), // AMOMAX_D_AQ_RL |
11345 | 0 | UINT64_C(2717921327), // AMOMAX_D_RL |
11346 | 0 | UINT64_C(2684362799), // AMOMAX_W |
11347 | 0 | UINT64_C(2751471663), // AMOMAX_W_AQ |
11348 | 0 | UINT64_C(2785026095), // AMOMAX_W_AQ_RL |
11349 | 0 | UINT64_C(2717917231), // AMOMAX_W_RL |
11350 | 0 | UINT64_C(3221237807), // AMOMINU_D |
11351 | 0 | UINT64_C(3288346671), // AMOMINU_D_AQ |
11352 | 0 | UINT64_C(3321901103), // AMOMINU_D_AQ_RL |
11353 | 0 | UINT64_C(3254792239), // AMOMINU_D_RL |
11354 | 0 | UINT64_C(3221233711), // AMOMINU_W |
11355 | 0 | UINT64_C(3288342575), // AMOMINU_W_AQ |
11356 | 0 | UINT64_C(3321897007), // AMOMINU_W_AQ_RL |
11357 | 0 | UINT64_C(3254788143), // AMOMINU_W_RL |
11358 | 0 | UINT64_C(2147495983), // AMOMIN_D |
11359 | 0 | UINT64_C(2214604847), // AMOMIN_D_AQ |
11360 | 0 | UINT64_C(2248159279), // AMOMIN_D_AQ_RL |
11361 | 0 | UINT64_C(2181050415), // AMOMIN_D_RL |
11362 | 0 | UINT64_C(2147491887), // AMOMIN_W |
11363 | 0 | UINT64_C(2214600751), // AMOMIN_W_AQ |
11364 | 0 | UINT64_C(2248155183), // AMOMIN_W_AQ_RL |
11365 | 0 | UINT64_C(2181046319), // AMOMIN_W_RL |
11366 | 0 | UINT64_C(1073754159), // AMOOR_D |
11367 | 0 | UINT64_C(1140863023), // AMOOR_D_AQ |
11368 | 0 | UINT64_C(1174417455), // AMOOR_D_AQ_RL |
11369 | 0 | UINT64_C(1107308591), // AMOOR_D_RL |
11370 | 0 | UINT64_C(1073750063), // AMOOR_W |
11371 | 0 | UINT64_C(1140858927), // AMOOR_W_AQ |
11372 | 0 | UINT64_C(1174413359), // AMOOR_W_AQ_RL |
11373 | 0 | UINT64_C(1107304495), // AMOOR_W_RL |
11374 | 0 | UINT64_C(134230063), // AMOSWAP_D |
11375 | 0 | UINT64_C(201338927), // AMOSWAP_D_AQ |
11376 | 0 | UINT64_C(234893359), // AMOSWAP_D_AQ_RL |
11377 | 0 | UINT64_C(167784495), // AMOSWAP_D_RL |
11378 | 0 | UINT64_C(134225967), // AMOSWAP_W |
11379 | 0 | UINT64_C(201334831), // AMOSWAP_W_AQ |
11380 | 0 | UINT64_C(234889263), // AMOSWAP_W_AQ_RL |
11381 | 0 | UINT64_C(167780399), // AMOSWAP_W_RL |
11382 | 0 | UINT64_C(536883247), // AMOXOR_D |
11383 | 0 | UINT64_C(603992111), // AMOXOR_D_AQ |
11384 | 0 | UINT64_C(637546543), // AMOXOR_D_AQ_RL |
11385 | 0 | UINT64_C(570437679), // AMOXOR_D_RL |
11386 | 0 | UINT64_C(536879151), // AMOXOR_W |
11387 | 0 | UINT64_C(603988015), // AMOXOR_W_AQ |
11388 | 0 | UINT64_C(637542447), // AMOXOR_W_AQ_RL |
11389 | 0 | UINT64_C(570433583), // AMOXOR_W_RL |
11390 | 0 | UINT64_C(28723), // AND |
11391 | 0 | UINT64_C(28691), // ANDI |
11392 | 0 | UINT64_C(1073770547), // ANDN |
11393 | 0 | UINT64_C(23), // AUIPC |
11394 | 0 | UINT64_C(1207963699), // BCLR |
11395 | 0 | UINT64_C(1207963667), // BCLRI |
11396 | 0 | UINT64_C(99), // BEQ |
11397 | 0 | UINT64_C(1207980083), // BEXT |
11398 | 0 | UINT64_C(1207980051), // BEXTI |
11399 | 0 | UINT64_C(20579), // BGE |
11400 | 0 | UINT64_C(28771), // BGEU |
11401 | 0 | UINT64_C(1744834611), // BINV |
11402 | 0 | UINT64_C(1744834579), // BINVI |
11403 | 0 | UINT64_C(16483), // BLT |
11404 | 0 | UINT64_C(24675), // BLTU |
11405 | 0 | UINT64_C(4195), // BNE |
11406 | 0 | UINT64_C(1752190995), // BREV8 |
11407 | 0 | UINT64_C(671092787), // BSET |
11408 | 0 | UINT64_C(671092755), // BSETI |
11409 | 0 | UINT64_C(1056783), // CBO_CLEAN |
11410 | 0 | UINT64_C(2105359), // CBO_FLUSH |
11411 | 0 | UINT64_C(8207), // CBO_INVAL |
11412 | 0 | UINT64_C(4202511), // CBO_ZERO |
11413 | 0 | UINT64_C(167776307), // CLMUL |
11414 | 0 | UINT64_C(167784499), // CLMULH |
11415 | 0 | UINT64_C(167780403), // CLMULR |
11416 | 0 | UINT64_C(1610616851), // CLZ |
11417 | 0 | UINT64_C(1610616859), // CLZW |
11418 | 0 | UINT64_C(24705), // CMOP1 |
11419 | 0 | UINT64_C(25985), // CMOP11 |
11420 | 0 | UINT64_C(26241), // CMOP13 |
11421 | 0 | UINT64_C(26497), // CMOP15 |
11422 | 0 | UINT64_C(24961), // CMOP3 |
11423 | 0 | UINT64_C(25217), // CMOP5 |
11424 | 0 | UINT64_C(25473), // CMOP7 |
11425 | 0 | UINT64_C(25729), // CMOP9 |
11426 | 0 | UINT64_C(40962), // CM_JALT |
11427 | 0 | UINT64_C(40962), // CM_JT |
11428 | 0 | UINT64_C(44130), // CM_MVA01S |
11429 | 0 | UINT64_C(44066), // CM_MVSA01 |
11430 | 0 | UINT64_C(47618), // CM_POP |
11431 | 0 | UINT64_C(48642), // CM_POPRET |
11432 | 0 | UINT64_C(48130), // CM_POPRETZ |
11433 | 0 | UINT64_C(47106), // CM_PUSH |
11434 | 0 | UINT64_C(1612714003), // CPOP |
11435 | 0 | UINT64_C(1612714011), // CPOPW |
11436 | 0 | UINT64_C(12403), // CSRRC |
11437 | 0 | UINT64_C(28787), // CSRRCI |
11438 | 0 | UINT64_C(8307), // CSRRS |
11439 | 0 | UINT64_C(24691), // CSRRSI |
11440 | 0 | UINT64_C(4211), // CSRRW |
11441 | 0 | UINT64_C(20595), // CSRRWI |
11442 | 0 | UINT64_C(1611665427), // CTZ |
11443 | 0 | UINT64_C(1611665435), // CTZW |
11444 | 0 | UINT64_C(1342189611), // CV_ABS |
11445 | 0 | UINT64_C(1879052411), // CV_ABS_B |
11446 | 0 | UINT64_C(1879048315), // CV_ABS_H |
11447 | 0 | UINT64_C(8283), // CV_ADDN |
11448 | 0 | UINT64_C(2147495979), // CV_ADDNR |
11449 | 0 | UINT64_C(2147491931), // CV_ADDRN |
11450 | 0 | UINT64_C(2214604843), // CV_ADDRNR |
11451 | 0 | UINT64_C(1073750107), // CV_ADDUN |
11452 | 0 | UINT64_C(2181050411), // CV_ADDUNR |
11453 | 0 | UINT64_C(3221233755), // CV_ADDURN |
11454 | 0 | UINT64_C(2248159275), // CV_ADDURNR |
11455 | 0 | UINT64_C(4219), // CV_ADD_B |
11456 | 0 | UINT64_C(1811947643), // CV_ADD_DIV2 |
11457 | 0 | UINT64_C(1811955835), // CV_ADD_DIV4 |
11458 | 0 | UINT64_C(1811964027), // CV_ADD_DIV8 |
11459 | 0 | UINT64_C(123), // CV_ADD_H |
11460 | 0 | UINT64_C(28795), // CV_ADD_SCI_B |
11461 | 0 | UINT64_C(24699), // CV_ADD_SCI_H |
11462 | 0 | UINT64_C(20603), // CV_ADD_SC_B |
11463 | 0 | UINT64_C(16507), // CV_ADD_SC_H |
11464 | 0 | UINT64_C(1744834683), // CV_AND_B |
11465 | 0 | UINT64_C(1744830587), // CV_AND_H |
11466 | 0 | UINT64_C(1744859259), // CV_AND_SCI_B |
11467 | 0 | UINT64_C(1744855163), // CV_AND_SCI_H |
11468 | 0 | UINT64_C(1744851067), // CV_AND_SC_B |
11469 | 0 | UINT64_C(1744846971), // CV_AND_SC_H |
11470 | 0 | UINT64_C(402657403), // CV_AVGU_B |
11471 | 0 | UINT64_C(402653307), // CV_AVGU_H |
11472 | 0 | UINT64_C(402681979), // CV_AVGU_SCI_B |
11473 | 0 | UINT64_C(402677883), // CV_AVGU_SCI_H |
11474 | 0 | UINT64_C(402673787), // CV_AVGU_SC_B |
11475 | 0 | UINT64_C(402669691), // CV_AVGU_SC_H |
11476 | 0 | UINT64_C(268439675), // CV_AVG_B |
11477 | 0 | UINT64_C(268435579), // CV_AVG_H |
11478 | 0 | UINT64_C(268464251), // CV_AVG_SCI_B |
11479 | 0 | UINT64_C(268460155), // CV_AVG_SCI_H |
11480 | 0 | UINT64_C(268456059), // CV_AVG_SC_B |
11481 | 0 | UINT64_C(268451963), // CV_AVG_SC_H |
11482 | 0 | UINT64_C(4187), // CV_BCLR |
11483 | 0 | UINT64_C(939536427), // CV_BCLRR |
11484 | 0 | UINT64_C(24587), // CV_BEQIMM |
11485 | 0 | UINT64_C(3221229659), // CV_BITREV |
11486 | 0 | UINT64_C(28683), // CV_BNEIMM |
11487 | 0 | UINT64_C(1073746011), // CV_BSET |
11488 | 0 | UINT64_C(973090859), // CV_BSETR |
11489 | 0 | UINT64_C(1174417451), // CV_CLB |
11490 | 0 | UINT64_C(1879060523), // CV_CLIP |
11491 | 0 | UINT64_C(1946169387), // CV_CLIPR |
11492 | 0 | UINT64_C(1912614955), // CV_CLIPU |
11493 | 0 | UINT64_C(1979723819), // CV_CLIPUR |
11494 | 0 | UINT64_C(67113083), // CV_CMPEQ_B |
11495 | 0 | UINT64_C(67108987), // CV_CMPEQ_H |
11496 | 0 | UINT64_C(67137659), // CV_CMPEQ_SCI_B |
11497 | 0 | UINT64_C(67133563), // CV_CMPEQ_SCI_H |
11498 | 0 | UINT64_C(67129467), // CV_CMPEQ_SC_B |
11499 | 0 | UINT64_C(67125371), // CV_CMPEQ_SC_H |
11500 | 0 | UINT64_C(1006637179), // CV_CMPGEU_B |
11501 | 0 | UINT64_C(1006633083), // CV_CMPGEU_H |
11502 | 0 | UINT64_C(1006661755), // CV_CMPGEU_SCI_B |
11503 | 0 | UINT64_C(1006657659), // CV_CMPGEU_SCI_H |
11504 | 0 | UINT64_C(1006653563), // CV_CMPGEU_SC_B |
11505 | 0 | UINT64_C(1006649467), // CV_CMPGEU_SC_H |
11506 | 0 | UINT64_C(469766267), // CV_CMPGE_B |
11507 | 0 | UINT64_C(469762171), // CV_CMPGE_H |
11508 | 0 | UINT64_C(469790843), // CV_CMPGE_SCI_B |
11509 | 0 | UINT64_C(469786747), // CV_CMPGE_SCI_H |
11510 | 0 | UINT64_C(469782651), // CV_CMPGE_SC_B |
11511 | 0 | UINT64_C(469778555), // CV_CMPGE_SC_H |
11512 | 0 | UINT64_C(872419451), // CV_CMPGTU_B |
11513 | 0 | UINT64_C(872415355), // CV_CMPGTU_H |
11514 | 0 | UINT64_C(872444027), // CV_CMPGTU_SCI_B |
11515 | 0 | UINT64_C(872439931), // CV_CMPGTU_SCI_H |
11516 | 0 | UINT64_C(872435835), // CV_CMPGTU_SC_B |
11517 | 0 | UINT64_C(872431739), // CV_CMPGTU_SC_H |
11518 | 0 | UINT64_C(335548539), // CV_CMPGT_B |
11519 | 0 | UINT64_C(335544443), // CV_CMPGT_H |
11520 | 0 | UINT64_C(335573115), // CV_CMPGT_SCI_B |
11521 | 0 | UINT64_C(335569019), // CV_CMPGT_SCI_H |
11522 | 0 | UINT64_C(335564923), // CV_CMPGT_SC_B |
11523 | 0 | UINT64_C(335560827), // CV_CMPGT_SC_H |
11524 | 0 | UINT64_C(1275072635), // CV_CMPLEU_B |
11525 | 0 | UINT64_C(1275068539), // CV_CMPLEU_H |
11526 | 0 | UINT64_C(1275097211), // CV_CMPLEU_SCI_B |
11527 | 0 | UINT64_C(1275093115), // CV_CMPLEU_SCI_H |
11528 | 0 | UINT64_C(1275089019), // CV_CMPLEU_SC_B |
11529 | 0 | UINT64_C(1275084923), // CV_CMPLEU_SC_H |
11530 | 0 | UINT64_C(738201723), // CV_CMPLE_B |
11531 | 0 | UINT64_C(738197627), // CV_CMPLE_H |
11532 | 0 | UINT64_C(738226299), // CV_CMPLE_SCI_B |
11533 | 0 | UINT64_C(738222203), // CV_CMPLE_SCI_H |
11534 | 0 | UINT64_C(738218107), // CV_CMPLE_SC_B |
11535 | 0 | UINT64_C(738214011), // CV_CMPLE_SC_H |
11536 | 0 | UINT64_C(1140854907), // CV_CMPLTU_B |
11537 | 0 | UINT64_C(1140850811), // CV_CMPLTU_H |
11538 | 0 | UINT64_C(1140879483), // CV_CMPLTU_SCI_B |
11539 | 0 | UINT64_C(1140875387), // CV_CMPLTU_SCI_H |
11540 | 0 | UINT64_C(1140871291), // CV_CMPLTU_SC_B |
11541 | 0 | UINT64_C(1140867195), // CV_CMPLTU_SC_H |
11542 | 0 | UINT64_C(603983995), // CV_CMPLT_B |
11543 | 0 | UINT64_C(603979899), // CV_CMPLT_H |
11544 | 0 | UINT64_C(604008571), // CV_CMPLT_SCI_B |
11545 | 0 | UINT64_C(604004475), // CV_CMPLT_SCI_H |
11546 | 0 | UINT64_C(604000379), // CV_CMPLT_SC_B |
11547 | 0 | UINT64_C(603996283), // CV_CMPLT_SC_H |
11548 | 0 | UINT64_C(201330811), // CV_CMPNE_B |
11549 | 0 | UINT64_C(201326715), // CV_CMPNE_H |
11550 | 0 | UINT64_C(201355387), // CV_CMPNE_SCI_B |
11551 | 0 | UINT64_C(201351291), // CV_CMPNE_SCI_H |
11552 | 0 | UINT64_C(201347195), // CV_CMPNE_SC_B |
11553 | 0 | UINT64_C(201343099), // CV_CMPNE_SC_H |
11554 | 0 | UINT64_C(1207971883), // CV_CNT |
11555 | 0 | UINT64_C(1543503995), // CV_CPLXCONJ |
11556 | 0 | UINT64_C(1442840699), // CV_CPLXMUL_I |
11557 | 0 | UINT64_C(1442848891), // CV_CPLXMUL_I_DIV2 |
11558 | 0 | UINT64_C(1442857083), // CV_CPLXMUL_I_DIV4 |
11559 | 0 | UINT64_C(1442865275), // CV_CPLXMUL_I_DIV8 |
11560 | 0 | UINT64_C(1409286267), // CV_CPLXMUL_R |
11561 | 0 | UINT64_C(1409294459), // CV_CPLXMUL_R_DIV2 |
11562 | 0 | UINT64_C(1409302651), // CV_CPLXMUL_R_DIV4 |
11563 | 0 | UINT64_C(1409310843), // CV_CPLXMUL_R_DIV8 |
11564 | 0 | UINT64_C(2415923323), // CV_DOTSP_B |
11565 | 0 | UINT64_C(2415919227), // CV_DOTSP_H |
11566 | 0 | UINT64_C(2415947899), // CV_DOTSP_SCI_B |
11567 | 0 | UINT64_C(2415943803), // CV_DOTSP_SCI_H |
11568 | 0 | UINT64_C(2415939707), // CV_DOTSP_SC_B |
11569 | 0 | UINT64_C(2415935611), // CV_DOTSP_SC_H |
11570 | 0 | UINT64_C(2147487867), // CV_DOTUP_B |
11571 | 0 | UINT64_C(2147483771), // CV_DOTUP_H |
11572 | 0 | UINT64_C(2147512443), // CV_DOTUP_SCI_B |
11573 | 0 | UINT64_C(2147508347), // CV_DOTUP_SCI_H |
11574 | 0 | UINT64_C(2147504251), // CV_DOTUP_SC_B |
11575 | 0 | UINT64_C(2147500155), // CV_DOTUP_SC_H |
11576 | 0 | UINT64_C(2281705595), // CV_DOTUSP_B |
11577 | 0 | UINT64_C(2281701499), // CV_DOTUSP_H |
11578 | 0 | UINT64_C(2281730171), // CV_DOTUSP_SCI_B |
11579 | 0 | UINT64_C(2281726075), // CV_DOTUSP_SCI_H |
11580 | 0 | UINT64_C(2281721979), // CV_DOTUSP_SC_B |
11581 | 0 | UINT64_C(2281717883), // CV_DOTUSP_SC_H |
11582 | 0 | UINT64_C(12299), // CV_ELW |
11583 | 0 | UINT64_C(1677733931), // CV_EXTBS |
11584 | 0 | UINT64_C(1711288363), // CV_EXTBZ |
11585 | 0 | UINT64_C(1610625067), // CV_EXTHS |
11586 | 0 | UINT64_C(1644179499), // CV_EXTHZ |
11587 | 0 | UINT64_C(91), // CV_EXTRACT |
11588 | 0 | UINT64_C(805318699), // CV_EXTRACTR |
11589 | 0 | UINT64_C(1073741915), // CV_EXTRACTU |
11590 | 0 | UINT64_C(838873131), // CV_EXTRACTUR |
11591 | 0 | UINT64_C(3087020155), // CV_EXTRACTU_B |
11592 | 0 | UINT64_C(3087016059), // CV_EXTRACTU_H |
11593 | 0 | UINT64_C(3087011963), // CV_EXTRACT_B |
11594 | 0 | UINT64_C(3087007867), // CV_EXTRACT_H |
11595 | 0 | UINT64_C(1107308587), // CV_FF1 |
11596 | 0 | UINT64_C(1140863019), // CV_FL1 |
11597 | 0 | UINT64_C(2147483739), // CV_INSERT |
11598 | 0 | UINT64_C(872427563), // CV_INSERTR |
11599 | 0 | UINT64_C(3087028347), // CV_INSERT_B |
11600 | 0 | UINT64_C(3087024251), // CV_INSERT_H |
11601 | 0 | UINT64_C(16395), // CV_LBU_ri_inc |
11602 | 0 | UINT64_C(402665515), // CV_LBU_rr |
11603 | 0 | UINT64_C(268447787), // CV_LBU_rr_inc |
11604 | 0 | UINT64_C(11), // CV_LB_ri_inc |
11605 | 0 | UINT64_C(134230059), // CV_LB_rr |
11606 | 0 | UINT64_C(12331), // CV_LB_rr_inc |
11607 | 0 | UINT64_C(20491), // CV_LHU_ri_inc |
11608 | 0 | UINT64_C(436219947), // CV_LHU_rr |
11609 | 0 | UINT64_C(302002219), // CV_LHU_rr_inc |
11610 | 0 | UINT64_C(4107), // CV_LH_ri_inc |
11611 | 0 | UINT64_C(167784491), // CV_LH_rr |
11612 | 0 | UINT64_C(33566763), // CV_LH_rr_inc |
11613 | 0 | UINT64_C(8203), // CV_LW_ri_inc |
11614 | 0 | UINT64_C(201338923), // CV_LW_rr |
11615 | 0 | UINT64_C(67121195), // CV_LW_rr_inc |
11616 | 0 | UINT64_C(2415931435), // CV_MAC |
11617 | 0 | UINT64_C(1073766491), // CV_MACHHSN |
11618 | 0 | UINT64_C(3221250139), // CV_MACHHSRN |
11619 | 0 | UINT64_C(1073770587), // CV_MACHHUN |
11620 | 0 | UINT64_C(3221254235), // CV_MACHHURN |
11621 | 0 | UINT64_C(24667), // CV_MACSN |
11622 | 0 | UINT64_C(2147508315), // CV_MACSRN |
11623 | 0 | UINT64_C(28763), // CV_MACUN |
11624 | 0 | UINT64_C(2147512411), // CV_MACURN |
11625 | 0 | UINT64_C(1509961771), // CV_MAX |
11626 | 0 | UINT64_C(1543516203), // CV_MAXU |
11627 | 0 | UINT64_C(939528315), // CV_MAXU_B |
11628 | 0 | UINT64_C(939524219), // CV_MAXU_H |
11629 | 0 | UINT64_C(939552891), // CV_MAXU_SCI_B |
11630 | 0 | UINT64_C(939548795), // CV_MAXU_SCI_H |
11631 | 0 | UINT64_C(939544699), // CV_MAXU_SC_B |
11632 | 0 | UINT64_C(939540603), // CV_MAXU_SC_H |
11633 | 0 | UINT64_C(805310587), // CV_MAX_B |
11634 | 0 | UINT64_C(805306491), // CV_MAX_H |
11635 | 0 | UINT64_C(805335163), // CV_MAX_SCI_B |
11636 | 0 | UINT64_C(805331067), // CV_MAX_SCI_H |
11637 | 0 | UINT64_C(805326971), // CV_MAX_SC_B |
11638 | 0 | UINT64_C(805322875), // CV_MAX_SC_H |
11639 | 0 | UINT64_C(1442852907), // CV_MIN |
11640 | 0 | UINT64_C(1476407339), // CV_MINU |
11641 | 0 | UINT64_C(671092859), // CV_MINU_B |
11642 | 0 | UINT64_C(671088763), // CV_MINU_H |
11643 | 0 | UINT64_C(671117435), // CV_MINU_SCI_B |
11644 | 0 | UINT64_C(671113339), // CV_MINU_SCI_H |
11645 | 0 | UINT64_C(671109243), // CV_MINU_SC_B |
11646 | 0 | UINT64_C(671105147), // CV_MINU_SC_H |
11647 | 0 | UINT64_C(536875131), // CV_MIN_B |
11648 | 0 | UINT64_C(536871035), // CV_MIN_H |
11649 | 0 | UINT64_C(536899707), // CV_MIN_SCI_B |
11650 | 0 | UINT64_C(536895611), // CV_MIN_SCI_H |
11651 | 0 | UINT64_C(536891515), // CV_MIN_SC_B |
11652 | 0 | UINT64_C(536887419), // CV_MIN_SC_H |
11653 | 0 | UINT64_C(2449485867), // CV_MSU |
11654 | 0 | UINT64_C(1073758299), // CV_MULHHSN |
11655 | 0 | UINT64_C(3221241947), // CV_MULHHSRN |
11656 | 0 | UINT64_C(1073762395), // CV_MULHHUN |
11657 | 0 | UINT64_C(3221246043), // CV_MULHHURN |
11658 | 0 | UINT64_C(16475), // CV_MULSN |
11659 | 0 | UINT64_C(2147500123), // CV_MULSRN |
11660 | 0 | UINT64_C(20571), // CV_MULUN |
11661 | 0 | UINT64_C(2147504219), // CV_MULURN |
11662 | 0 | UINT64_C(1476399227), // CV_OR_B |
11663 | 0 | UINT64_C(1476395131), // CV_OR_H |
11664 | 0 | UINT64_C(1476423803), // CV_OR_SCI_B |
11665 | 0 | UINT64_C(1476419707), // CV_OR_SCI_H |
11666 | 0 | UINT64_C(1476415611), // CV_OR_SC_B |
11667 | 0 | UINT64_C(1476411515), // CV_OR_SC_H |
11668 | 0 | UINT64_C(4026531963), // CV_PACK |
11669 | 0 | UINT64_C(4194308219), // CV_PACKHI_B |
11670 | 0 | UINT64_C(4160753787), // CV_PACKLO_B |
11671 | 0 | UINT64_C(4060086395), // CV_PACK_H |
11672 | 0 | UINT64_C(1073754155), // CV_ROR |
11673 | 0 | UINT64_C(43), // CV_SB_ri_inc |
11674 | 0 | UINT64_C(671100971), // CV_SB_rr |
11675 | 0 | UINT64_C(536883243), // CV_SB_rr_inc |
11676 | 0 | UINT64_C(2818576507), // CV_SDOTSP_B |
11677 | 0 | UINT64_C(2818572411), // CV_SDOTSP_H |
11678 | 0 | UINT64_C(2818601083), // CV_SDOTSP_SCI_B |
11679 | 0 | UINT64_C(2818596987), // CV_SDOTSP_SCI_H |
11680 | 0 | UINT64_C(2818592891), // CV_SDOTSP_SC_B |
11681 | 0 | UINT64_C(2818588795), // CV_SDOTSP_SC_H |
11682 | 0 | UINT64_C(2550141051), // CV_SDOTUP_B |
11683 | 0 | UINT64_C(2550136955), // CV_SDOTUP_H |
11684 | 0 | UINT64_C(2550165627), // CV_SDOTUP_SCI_B |
11685 | 0 | UINT64_C(2550161531), // CV_SDOTUP_SCI_H |
11686 | 0 | UINT64_C(2550157435), // CV_SDOTUP_SC_B |
11687 | 0 | UINT64_C(2550153339), // CV_SDOTUP_SC_H |
11688 | 0 | UINT64_C(2684358779), // CV_SDOTUSP_B |
11689 | 0 | UINT64_C(2684354683), // CV_SDOTUSP_H |
11690 | 0 | UINT64_C(2684383355), // CV_SDOTUSP_SCI_B |
11691 | 0 | UINT64_C(2684379259), // CV_SDOTUSP_SCI_H |
11692 | 0 | UINT64_C(2684375163), // CV_SDOTUSP_SC_B |
11693 | 0 | UINT64_C(2684371067), // CV_SDOTUSP_SC_H |
11694 | 0 | UINT64_C(3758100603), // CV_SHUFFLE2_B |
11695 | 0 | UINT64_C(3758096507), // CV_SHUFFLE2_H |
11696 | 0 | UINT64_C(3221254267), // CV_SHUFFLEI0_SCI_B |
11697 | 0 | UINT64_C(3355471995), // CV_SHUFFLEI1_SCI_B |
11698 | 0 | UINT64_C(3489689723), // CV_SHUFFLEI2_SCI_B |
11699 | 0 | UINT64_C(3623907451), // CV_SHUFFLEI3_SCI_B |
11700 | 0 | UINT64_C(3221229691), // CV_SHUFFLE_B |
11701 | 0 | UINT64_C(3221225595), // CV_SHUFFLE_H |
11702 | 0 | UINT64_C(3221250171), // CV_SHUFFLE_SCI_H |
11703 | 0 | UINT64_C(4139), // CV_SH_ri_inc |
11704 | 0 | UINT64_C(704655403), // CV_SH_rr |
11705 | 0 | UINT64_C(570437675), // CV_SH_rr_inc |
11706 | 0 | UINT64_C(1375744043), // CV_SLET |
11707 | 0 | UINT64_C(1409298475), // CV_SLETU |
11708 | 0 | UINT64_C(1342181499), // CV_SLL_B |
11709 | 0 | UINT64_C(1342177403), // CV_SLL_H |
11710 | 0 | UINT64_C(1342206075), // CV_SLL_SCI_B |
11711 | 0 | UINT64_C(1342201979), // CV_SLL_SCI_H |
11712 | 0 | UINT64_C(1342197883), // CV_SLL_SC_B |
11713 | 0 | UINT64_C(1342193787), // CV_SLL_SC_H |
11714 | 0 | UINT64_C(1207963771), // CV_SRA_B |
11715 | 0 | UINT64_C(1207959675), // CV_SRA_H |
11716 | 0 | UINT64_C(1207988347), // CV_SRA_SCI_B |
11717 | 0 | UINT64_C(1207984251), // CV_SRA_SCI_H |
11718 | 0 | UINT64_C(1207980155), // CV_SRA_SC_B |
11719 | 0 | UINT64_C(1207976059), // CV_SRA_SC_H |
11720 | 0 | UINT64_C(1073746043), // CV_SRL_B |
11721 | 0 | UINT64_C(1073741947), // CV_SRL_H |
11722 | 0 | UINT64_C(1073770619), // CV_SRL_SCI_B |
11723 | 0 | UINT64_C(1073766523), // CV_SRL_SCI_H |
11724 | 0 | UINT64_C(1073762427), // CV_SRL_SC_B |
11725 | 0 | UINT64_C(1073758331), // CV_SRL_SC_H |
11726 | 0 | UINT64_C(12379), // CV_SUBN |
11727 | 0 | UINT64_C(2281713707), // CV_SUBNR |
11728 | 0 | UINT64_C(2147496027), // CV_SUBRN |
11729 | 0 | UINT64_C(2348822571), // CV_SUBRNR |
11730 | 0 | UINT64_C(1677721723), // CV_SUBROTMJ |
11731 | 0 | UINT64_C(1677729915), // CV_SUBROTMJ_DIV2 |
11732 | 0 | UINT64_C(1677738107), // CV_SUBROTMJ_DIV4 |
11733 | 0 | UINT64_C(1677746299), // CV_SUBROTMJ_DIV8 |
11734 | 0 | UINT64_C(1073754203), // CV_SUBUN |
11735 | 0 | UINT64_C(2315268139), // CV_SUBUNR |
11736 | 0 | UINT64_C(3221237851), // CV_SUBURN |
11737 | 0 | UINT64_C(2382377003), // CV_SUBURNR |
11738 | 0 | UINT64_C(134221947), // CV_SUB_B |
11739 | 0 | UINT64_C(1946165371), // CV_SUB_DIV2 |
11740 | 0 | UINT64_C(1946173563), // CV_SUB_DIV4 |
11741 | 0 | UINT64_C(1946181755), // CV_SUB_DIV8 |
11742 | 0 | UINT64_C(134217851), // CV_SUB_H |
11743 | 0 | UINT64_C(134246523), // CV_SUB_SCI_B |
11744 | 0 | UINT64_C(134242427), // CV_SUB_SCI_H |
11745 | 0 | UINT64_C(134238331), // CV_SUB_SC_B |
11746 | 0 | UINT64_C(134234235), // CV_SUB_SC_H |
11747 | 0 | UINT64_C(8235), // CV_SW_ri_inc |
11748 | 0 | UINT64_C(738209835), // CV_SW_rr |
11749 | 0 | UINT64_C(603992107), // CV_SW_rr_inc |
11750 | 0 | UINT64_C(1610616955), // CV_XOR_B |
11751 | 0 | UINT64_C(1610612859), // CV_XOR_H |
11752 | 0 | UINT64_C(1610641531), // CV_XOR_SCI_B |
11753 | 0 | UINT64_C(1610637435), // CV_XOR_SCI_H |
11754 | 0 | UINT64_C(1610633339), // CV_XOR_SC_B |
11755 | 0 | UINT64_C(1610629243), // CV_XOR_SC_H |
11756 | 0 | UINT64_C(234901555), // CZERO_EQZ |
11757 | 0 | UINT64_C(234909747), // CZERO_NEZ |
11758 | 0 | UINT64_C(36866), // C_ADD |
11759 | 0 | UINT64_C(1), // C_ADDI |
11760 | 0 | UINT64_C(24833), // C_ADDI16SP |
11761 | 0 | UINT64_C(0), // C_ADDI4SPN |
11762 | 0 | UINT64_C(8193), // C_ADDIW |
11763 | 0 | UINT64_C(1), // C_ADDI_HINT_IMM_ZERO |
11764 | 0 | UINT64_C(1), // C_ADDI_NOP |
11765 | 0 | UINT64_C(39969), // C_ADDW |
11766 | 0 | UINT64_C(36866), // C_ADD_HINT |
11767 | 0 | UINT64_C(35937), // C_AND |
11768 | 0 | UINT64_C(34817), // C_ANDI |
11769 | 0 | UINT64_C(49153), // C_BEQZ |
11770 | 0 | UINT64_C(57345), // C_BNEZ |
11771 | 0 | UINT64_C(36866), // C_EBREAK |
11772 | 0 | UINT64_C(8192), // C_FLD |
11773 | 0 | UINT64_C(8194), // C_FLDSP |
11774 | 0 | UINT64_C(24576), // C_FLW |
11775 | 0 | UINT64_C(24578), // C_FLWSP |
11776 | 0 | UINT64_C(40960), // C_FSD |
11777 | 0 | UINT64_C(40962), // C_FSDSP |
11778 | 0 | UINT64_C(57344), // C_FSW |
11779 | 0 | UINT64_C(57346), // C_FSWSP |
11780 | 0 | UINT64_C(40961), // C_J |
11781 | 0 | UINT64_C(8193), // C_JAL |
11782 | 0 | UINT64_C(36866), // C_JALR |
11783 | 0 | UINT64_C(32770), // C_JR |
11784 | 0 | UINT64_C(32768), // C_LBU |
11785 | 0 | UINT64_C(24576), // C_LD |
11786 | 0 | UINT64_C(24578), // C_LDSP |
11787 | 0 | UINT64_C(33856), // C_LH |
11788 | 0 | UINT64_C(33792), // C_LHU |
11789 | 0 | UINT64_C(16385), // C_LI |
11790 | 0 | UINT64_C(16385), // C_LI_HINT |
11791 | 0 | UINT64_C(24577), // C_LUI |
11792 | 0 | UINT64_C(24577), // C_LUI_HINT |
11793 | 0 | UINT64_C(16384), // C_LW |
11794 | 0 | UINT64_C(16386), // C_LWSP |
11795 | 0 | UINT64_C(40001), // C_MUL |
11796 | 0 | UINT64_C(32770), // C_MV |
11797 | 0 | UINT64_C(32770), // C_MV_HINT |
11798 | 0 | UINT64_C(1), // C_NOP |
11799 | 0 | UINT64_C(1), // C_NOP_HINT |
11800 | 0 | UINT64_C(40053), // C_NOT |
11801 | 0 | UINT64_C(35905), // C_OR |
11802 | 0 | UINT64_C(34816), // C_SB |
11803 | 0 | UINT64_C(57344), // C_SD |
11804 | 0 | UINT64_C(57346), // C_SDSP |
11805 | 0 | UINT64_C(40037), // C_SEXT_B |
11806 | 0 | UINT64_C(40045), // C_SEXT_H |
11807 | 0 | UINT64_C(35840), // C_SH |
11808 | 0 | UINT64_C(2), // C_SLLI |
11809 | 0 | UINT64_C(2), // C_SLLI64_HINT |
11810 | 0 | UINT64_C(2), // C_SLLI_HINT |
11811 | 0 | UINT64_C(33793), // C_SRAI |
11812 | 0 | UINT64_C(33793), // C_SRAI64_HINT |
11813 | 0 | UINT64_C(32769), // C_SRLI |
11814 | 0 | UINT64_C(32769), // C_SRLI64_HINT |
11815 | 0 | UINT64_C(25217), // C_SSPOPCHK |
11816 | 0 | UINT64_C(24705), // C_SSPUSH |
11817 | 0 | UINT64_C(35841), // C_SUB |
11818 | 0 | UINT64_C(39937), // C_SUBW |
11819 | 0 | UINT64_C(49152), // C_SW |
11820 | 0 | UINT64_C(49154), // C_SWSP |
11821 | 0 | UINT64_C(0), // C_UNIMP |
11822 | 0 | UINT64_C(35873), // C_XOR |
11823 | 0 | UINT64_C(40033), // C_ZEXT_B |
11824 | 0 | UINT64_C(40041), // C_ZEXT_H |
11825 | 0 | UINT64_C(40049), // C_ZEXT_W |
11826 | 0 | UINT64_C(33570867), // DIV |
11827 | 0 | UINT64_C(33574963), // DIVU |
11828 | 0 | UINT64_C(33574971), // DIVUW |
11829 | 0 | UINT64_C(33570875), // DIVW |
11830 | 0 | UINT64_C(2065694835), // DRET |
11831 | 0 | UINT64_C(1048691), // EBREAK |
11832 | 0 | UINT64_C(115), // ECALL |
11833 | 0 | UINT64_C(33554515), // FADD_D |
11834 | 0 | UINT64_C(33554515), // FADD_D_IN32X |
11835 | 0 | UINT64_C(33554515), // FADD_D_INX |
11836 | 0 | UINT64_C(67108947), // FADD_H |
11837 | 0 | UINT64_C(67108947), // FADD_H_INX |
11838 | 0 | UINT64_C(83), // FADD_S |
11839 | 0 | UINT64_C(83), // FADD_S_INX |
11840 | 0 | UINT64_C(3791654995), // FCLASS_D |
11841 | 0 | UINT64_C(3791654995), // FCLASS_D_IN32X |
11842 | 0 | UINT64_C(3791654995), // FCLASS_D_INX |
11843 | 0 | UINT64_C(3825209427), // FCLASS_H |
11844 | 0 | UINT64_C(3825209427), // FCLASS_H_INX |
11845 | 0 | UINT64_C(3758100563), // FCLASS_S |
11846 | 0 | UINT64_C(3758100563), // FCLASS_S_INX |
11847 | 0 | UINT64_C(3263168595), // FCVTMOD_W_D |
11848 | 0 | UINT64_C(1149239379), // FCVT_BF16_S |
11849 | 0 | UINT64_C(1109393491), // FCVT_D_H |
11850 | 0 | UINT64_C(1109393491), // FCVT_D_H_IN32X |
11851 | 0 | UINT64_C(1109393491), // FCVT_D_H_INX |
11852 | 0 | UINT64_C(3525312595), // FCVT_D_L |
11853 | 0 | UINT64_C(3526361171), // FCVT_D_LU |
11854 | 0 | UINT64_C(3526361171), // FCVT_D_LU_INX |
11855 | 0 | UINT64_C(3525312595), // FCVT_D_L_INX |
11856 | 0 | UINT64_C(1107296339), // FCVT_D_S |
11857 | 0 | UINT64_C(1107296339), // FCVT_D_S_IN32X |
11858 | 0 | UINT64_C(1107296339), // FCVT_D_S_INX |
11859 | 0 | UINT64_C(3523215443), // FCVT_D_W |
11860 | 0 | UINT64_C(3524264019), // FCVT_D_WU |
11861 | 0 | UINT64_C(3524264019), // FCVT_D_WU_IN32X |
11862 | 0 | UINT64_C(3524264019), // FCVT_D_WU_INX |
11863 | 0 | UINT64_C(3523215443), // FCVT_D_W_IN32X |
11864 | 0 | UINT64_C(3523215443), // FCVT_D_W_INX |
11865 | 0 | UINT64_C(1141899347), // FCVT_H_D |
11866 | 0 | UINT64_C(1141899347), // FCVT_H_D_IN32X |
11867 | 0 | UINT64_C(1141899347), // FCVT_H_D_INX |
11868 | 0 | UINT64_C(3558867027), // FCVT_H_L |
11869 | 0 | UINT64_C(3559915603), // FCVT_H_LU |
11870 | 0 | UINT64_C(3559915603), // FCVT_H_LU_INX |
11871 | 0 | UINT64_C(3558867027), // FCVT_H_L_INX |
11872 | 0 | UINT64_C(1140850771), // FCVT_H_S |
11873 | 0 | UINT64_C(1140850771), // FCVT_H_S_INX |
11874 | 0 | UINT64_C(3556769875), // FCVT_H_W |
11875 | 0 | UINT64_C(3557818451), // FCVT_H_WU |
11876 | 0 | UINT64_C(3557818451), // FCVT_H_WU_INX |
11877 | 0 | UINT64_C(3556769875), // FCVT_H_W_INX |
11878 | 0 | UINT64_C(3257925715), // FCVT_LU_D |
11879 | 0 | UINT64_C(3257925715), // FCVT_LU_D_INX |
11880 | 0 | UINT64_C(3291480147), // FCVT_LU_H |
11881 | 0 | UINT64_C(3291480147), // FCVT_LU_H_INX |
11882 | 0 | UINT64_C(3224371283), // FCVT_LU_S |
11883 | 0 | UINT64_C(3224371283), // FCVT_LU_S_INX |
11884 | 0 | UINT64_C(3256877139), // FCVT_L_D |
11885 | 0 | UINT64_C(3256877139), // FCVT_L_D_INX |
11886 | 0 | UINT64_C(3290431571), // FCVT_L_H |
11887 | 0 | UINT64_C(3290431571), // FCVT_L_H_INX |
11888 | 0 | UINT64_C(3223322707), // FCVT_L_S |
11889 | 0 | UINT64_C(3223322707), // FCVT_L_S_INX |
11890 | 0 | UINT64_C(1080033363), // FCVT_S_BF16 |
11891 | 0 | UINT64_C(1074790483), // FCVT_S_D |
11892 | 0 | UINT64_C(1074790483), // FCVT_S_D_IN32X |
11893 | 0 | UINT64_C(1074790483), // FCVT_S_D_INX |
11894 | 0 | UINT64_C(1075839059), // FCVT_S_H |
11895 | 0 | UINT64_C(1075839059), // FCVT_S_H_INX |
11896 | 0 | UINT64_C(3491758163), // FCVT_S_L |
11897 | 0 | UINT64_C(3492806739), // FCVT_S_LU |
11898 | 0 | UINT64_C(3492806739), // FCVT_S_LU_INX |
11899 | 0 | UINT64_C(3491758163), // FCVT_S_L_INX |
11900 | 0 | UINT64_C(3489661011), // FCVT_S_W |
11901 | 0 | UINT64_C(3490709587), // FCVT_S_WU |
11902 | 0 | UINT64_C(3490709587), // FCVT_S_WU_INX |
11903 | 0 | UINT64_C(3489661011), // FCVT_S_W_INX |
11904 | 0 | UINT64_C(3255828563), // FCVT_WU_D |
11905 | 0 | UINT64_C(3255828563), // FCVT_WU_D_IN32X |
11906 | 0 | UINT64_C(3255828563), // FCVT_WU_D_INX |
11907 | 0 | UINT64_C(3289382995), // FCVT_WU_H |
11908 | 0 | UINT64_C(3289382995), // FCVT_WU_H_INX |
11909 | 0 | UINT64_C(3222274131), // FCVT_WU_S |
11910 | 0 | UINT64_C(3222274131), // FCVT_WU_S_INX |
11911 | 0 | UINT64_C(3254779987), // FCVT_W_D |
11912 | 0 | UINT64_C(3254779987), // FCVT_W_D_IN32X |
11913 | 0 | UINT64_C(3254779987), // FCVT_W_D_INX |
11914 | 0 | UINT64_C(3288334419), // FCVT_W_H |
11915 | 0 | UINT64_C(3288334419), // FCVT_W_H_INX |
11916 | 0 | UINT64_C(3221225555), // FCVT_W_S |
11917 | 0 | UINT64_C(3221225555), // FCVT_W_S_INX |
11918 | 0 | UINT64_C(436207699), // FDIV_D |
11919 | 0 | UINT64_C(436207699), // FDIV_D_IN32X |
11920 | 0 | UINT64_C(436207699), // FDIV_D_INX |
11921 | 0 | UINT64_C(469762131), // FDIV_H |
11922 | 0 | UINT64_C(469762131), // FDIV_H_INX |
11923 | 0 | UINT64_C(402653267), // FDIV_S |
11924 | 0 | UINT64_C(402653267), // FDIV_S_INX |
11925 | 0 | UINT64_C(15), // FENCE |
11926 | 0 | UINT64_C(4111), // FENCE_I |
11927 | 0 | UINT64_C(2200961039), // FENCE_TSO |
11928 | 0 | UINT64_C(2717917267), // FEQ_D |
11929 | 0 | UINT64_C(2717917267), // FEQ_D_IN32X |
11930 | 0 | UINT64_C(2717917267), // FEQ_D_INX |
11931 | 0 | UINT64_C(2751471699), // FEQ_H |
11932 | 0 | UINT64_C(2751471699), // FEQ_H_INX |
11933 | 0 | UINT64_C(2684362835), // FEQ_S |
11934 | 0 | UINT64_C(2684362835), // FEQ_S_INX |
11935 | 0 | UINT64_C(12295), // FLD |
11936 | 0 | UINT64_C(2717925459), // FLEQ_D |
11937 | 0 | UINT64_C(2751479891), // FLEQ_H |
11938 | 0 | UINT64_C(2684371027), // FLEQ_S |
11939 | 0 | UINT64_C(2717909075), // FLE_D |
11940 | 0 | UINT64_C(2717909075), // FLE_D_IN32X |
11941 | 0 | UINT64_C(2717909075), // FLE_D_INX |
11942 | 0 | UINT64_C(2751463507), // FLE_H |
11943 | 0 | UINT64_C(2751463507), // FLE_H_INX |
11944 | 0 | UINT64_C(2684354643), // FLE_S |
11945 | 0 | UINT64_C(2684354643), // FLE_S_INX |
11946 | 0 | UINT64_C(4103), // FLH |
11947 | 0 | UINT64_C(4061134931), // FLI_D |
11948 | 0 | UINT64_C(4094689363), // FLI_H |
11949 | 0 | UINT64_C(4027580499), // FLI_S |
11950 | 0 | UINT64_C(2717929555), // FLTQ_D |
11951 | 0 | UINT64_C(2751483987), // FLTQ_H |
11952 | 0 | UINT64_C(2684375123), // FLTQ_S |
11953 | 0 | UINT64_C(2717913171), // FLT_D |
11954 | 0 | UINT64_C(2717913171), // FLT_D_IN32X |
11955 | 0 | UINT64_C(2717913171), // FLT_D_INX |
11956 | 0 | UINT64_C(2751467603), // FLT_H |
11957 | 0 | UINT64_C(2751467603), // FLT_H_INX |
11958 | 0 | UINT64_C(2684358739), // FLT_S |
11959 | 0 | UINT64_C(2684358739), // FLT_S_INX |
11960 | 0 | UINT64_C(8199), // FLW |
11961 | 0 | UINT64_C(33554499), // FMADD_D |
11962 | 0 | UINT64_C(33554499), // FMADD_D_IN32X |
11963 | 0 | UINT64_C(33554499), // FMADD_D_INX |
11964 | 0 | UINT64_C(67108931), // FMADD_H |
11965 | 0 | UINT64_C(67108931), // FMADD_H_INX |
11966 | 0 | UINT64_C(67), // FMADD_S |
11967 | 0 | UINT64_C(67), // FMADD_S_INX |
11968 | 0 | UINT64_C(704655443), // FMAXM_D |
11969 | 0 | UINT64_C(738209875), // FMAXM_H |
11970 | 0 | UINT64_C(671101011), // FMAXM_S |
11971 | 0 | UINT64_C(704647251), // FMAX_D |
11972 | 0 | UINT64_C(704647251), // FMAX_D_IN32X |
11973 | 0 | UINT64_C(704647251), // FMAX_D_INX |
11974 | 0 | UINT64_C(738201683), // FMAX_H |
11975 | 0 | UINT64_C(738201683), // FMAX_H_INX |
11976 | 0 | UINT64_C(671092819), // FMAX_S |
11977 | 0 | UINT64_C(671092819), // FMAX_S_INX |
11978 | 0 | UINT64_C(704651347), // FMINM_D |
11979 | 0 | UINT64_C(738205779), // FMINM_H |
11980 | 0 | UINT64_C(671096915), // FMINM_S |
11981 | 0 | UINT64_C(704643155), // FMIN_D |
11982 | 0 | UINT64_C(704643155), // FMIN_D_IN32X |
11983 | 0 | UINT64_C(704643155), // FMIN_D_INX |
11984 | 0 | UINT64_C(738197587), // FMIN_H |
11985 | 0 | UINT64_C(738197587), // FMIN_H_INX |
11986 | 0 | UINT64_C(671088723), // FMIN_S |
11987 | 0 | UINT64_C(671088723), // FMIN_S_INX |
11988 | 0 | UINT64_C(33554503), // FMSUB_D |
11989 | 0 | UINT64_C(33554503), // FMSUB_D_IN32X |
11990 | 0 | UINT64_C(33554503), // FMSUB_D_INX |
11991 | 0 | UINT64_C(67108935), // FMSUB_H |
11992 | 0 | UINT64_C(67108935), // FMSUB_H_INX |
11993 | 0 | UINT64_C(71), // FMSUB_S |
11994 | 0 | UINT64_C(71), // FMSUB_S_INX |
11995 | 0 | UINT64_C(301989971), // FMUL_D |
11996 | 0 | UINT64_C(301989971), // FMUL_D_IN32X |
11997 | 0 | UINT64_C(301989971), // FMUL_D_INX |
11998 | 0 | UINT64_C(335544403), // FMUL_H |
11999 | 0 | UINT64_C(335544403), // FMUL_H_INX |
12000 | 0 | UINT64_C(268435539), // FMUL_S |
12001 | 0 | UINT64_C(268435539), // FMUL_S_INX |
12002 | 0 | UINT64_C(3792699475), // FMVH_X_D |
12003 | 0 | UINT64_C(2986344531), // FMVP_D_X |
12004 | 0 | UINT64_C(4060086355), // FMV_D_X |
12005 | 0 | UINT64_C(4093640787), // FMV_H_X |
12006 | 0 | UINT64_C(4026531923), // FMV_W_X |
12007 | 0 | UINT64_C(3791650899), // FMV_X_D |
12008 | 0 | UINT64_C(3825205331), // FMV_X_H |
12009 | 0 | UINT64_C(3758096467), // FMV_X_W |
12010 | 0 | UINT64_C(3758096467), // FMV_X_W_FPR64 |
12011 | 0 | UINT64_C(33554511), // FNMADD_D |
12012 | 0 | UINT64_C(33554511), // FNMADD_D_IN32X |
12013 | 0 | UINT64_C(33554511), // FNMADD_D_INX |
12014 | 0 | UINT64_C(67108943), // FNMADD_H |
12015 | 0 | UINT64_C(67108943), // FNMADD_H_INX |
12016 | 0 | UINT64_C(79), // FNMADD_S |
12017 | 0 | UINT64_C(79), // FNMADD_S_INX |
12018 | 0 | UINT64_C(33554507), // FNMSUB_D |
12019 | 0 | UINT64_C(33554507), // FNMSUB_D_IN32X |
12020 | 0 | UINT64_C(33554507), // FNMSUB_D_INX |
12021 | 0 | UINT64_C(67108939), // FNMSUB_H |
12022 | 0 | UINT64_C(67108939), // FNMSUB_H_INX |
12023 | 0 | UINT64_C(75), // FNMSUB_S |
12024 | 0 | UINT64_C(75), // FNMSUB_S_INX |
12025 | 0 | UINT64_C(1112539219), // FROUNDNX_D |
12026 | 0 | UINT64_C(1146093651), // FROUNDNX_H |
12027 | 0 | UINT64_C(1078984787), // FROUNDNX_S |
12028 | 0 | UINT64_C(1111490643), // FROUND_D |
12029 | 0 | UINT64_C(1145045075), // FROUND_H |
12030 | 0 | UINT64_C(1077936211), // FROUND_S |
12031 | 0 | UINT64_C(12327), // FSD |
12032 | 0 | UINT64_C(570429523), // FSGNJN_D |
12033 | 0 | UINT64_C(570429523), // FSGNJN_D_IN32X |
12034 | 0 | UINT64_C(570429523), // FSGNJN_D_INX |
12035 | 0 | UINT64_C(603983955), // FSGNJN_H |
12036 | 0 | UINT64_C(603983955), // FSGNJN_H_INX |
12037 | 0 | UINT64_C(536875091), // FSGNJN_S |
12038 | 0 | UINT64_C(536875091), // FSGNJN_S_INX |
12039 | 0 | UINT64_C(570433619), // FSGNJX_D |
12040 | 0 | UINT64_C(570433619), // FSGNJX_D_IN32X |
12041 | 0 | UINT64_C(570433619), // FSGNJX_D_INX |
12042 | 0 | UINT64_C(603988051), // FSGNJX_H |
12043 | 0 | UINT64_C(603988051), // FSGNJX_H_INX |
12044 | 0 | UINT64_C(536879187), // FSGNJX_S |
12045 | 0 | UINT64_C(536879187), // FSGNJX_S_INX |
12046 | 0 | UINT64_C(570425427), // FSGNJ_D |
12047 | 0 | UINT64_C(570425427), // FSGNJ_D_IN32X |
12048 | 0 | UINT64_C(570425427), // FSGNJ_D_INX |
12049 | 0 | UINT64_C(603979859), // FSGNJ_H |
12050 | 0 | UINT64_C(603979859), // FSGNJ_H_INX |
12051 | 0 | UINT64_C(536870995), // FSGNJ_S |
12052 | 0 | UINT64_C(536870995), // FSGNJ_S_INX |
12053 | 0 | UINT64_C(4135), // FSH |
12054 | 0 | UINT64_C(1509949523), // FSQRT_D |
12055 | 0 | UINT64_C(1509949523), // FSQRT_D_IN32X |
12056 | 0 | UINT64_C(1509949523), // FSQRT_D_INX |
12057 | 0 | UINT64_C(1543503955), // FSQRT_H |
12058 | 0 | UINT64_C(1543503955), // FSQRT_H_INX |
12059 | 0 | UINT64_C(1476395091), // FSQRT_S |
12060 | 0 | UINT64_C(1476395091), // FSQRT_S_INX |
12061 | 0 | UINT64_C(167772243), // FSUB_D |
12062 | 0 | UINT64_C(167772243), // FSUB_D_IN32X |
12063 | 0 | UINT64_C(167772243), // FSUB_D_INX |
12064 | 0 | UINT64_C(201326675), // FSUB_H |
12065 | 0 | UINT64_C(201326675), // FSUB_H_INX |
12066 | 0 | UINT64_C(134217811), // FSUB_S |
12067 | 0 | UINT64_C(134217811), // FSUB_S_INX |
12068 | 0 | UINT64_C(8231), // FSW |
12069 | 0 | UINT64_C(1644167283), // HFENCE_GVMA |
12070 | 0 | UINT64_C(570425459), // HFENCE_VVMA |
12071 | 0 | UINT64_C(1711276147), // HINVAL_GVMA |
12072 | 0 | UINT64_C(637534323), // HINVAL_VVMA |
12073 | 0 | UINT64_C(1680883827), // HLVX_HU |
12074 | 0 | UINT64_C(1747992691), // HLVX_WU |
12075 | 0 | UINT64_C(1610629235), // HLV_B |
12076 | 0 | UINT64_C(1611677811), // HLV_BU |
12077 | 0 | UINT64_C(1811955827), // HLV_D |
12078 | 0 | UINT64_C(1677738099), // HLV_H |
12079 | 0 | UINT64_C(1678786675), // HLV_HU |
12080 | 0 | UINT64_C(1744846963), // HLV_W |
12081 | 0 | UINT64_C(1745895539), // HLV_WU |
12082 | 0 | UINT64_C(1644183667), // HSV_B |
12083 | 0 | UINT64_C(1845510259), // HSV_D |
12084 | 0 | UINT64_C(1711292531), // HSV_H |
12085 | 0 | UINT64_C(1778401395), // HSV_W |
12086 | 0 | UINT64_C(0), // InsnB |
12087 | 0 | UINT64_C(0), // InsnCA |
12088 | 0 | UINT64_C(0), // InsnCB |
12089 | 0 | UINT64_C(0), // InsnCI |
12090 | 0 | UINT64_C(0), // InsnCIW |
12091 | 0 | UINT64_C(0), // InsnCJ |
12092 | 0 | UINT64_C(0), // InsnCL |
12093 | 0 | UINT64_C(0), // InsnCR |
12094 | 0 | UINT64_C(0), // InsnCS |
12095 | 0 | UINT64_C(0), // InsnCSS |
12096 | 0 | UINT64_C(0), // InsnI |
12097 | 0 | UINT64_C(0), // InsnI_Mem |
12098 | 0 | UINT64_C(0), // InsnJ |
12099 | 0 | UINT64_C(0), // InsnR |
12100 | 0 | UINT64_C(0), // InsnR4 |
12101 | 0 | UINT64_C(0), // InsnS |
12102 | 0 | UINT64_C(0), // InsnU |
12103 | 0 | UINT64_C(111), // JAL |
12104 | 0 | UINT64_C(103), // JALR |
12105 | 0 | UINT64_C(3), // LB |
12106 | 0 | UINT64_C(16387), // LBU |
12107 | 0 | UINT64_C(12291), // LD |
12108 | 0 | UINT64_C(4099), // LH |
12109 | 0 | UINT64_C(20483), // LHU |
12110 | 0 | UINT64_C(268447791), // LR_D |
12111 | 0 | UINT64_C(335556655), // LR_D_AQ |
12112 | 0 | UINT64_C(369111087), // LR_D_AQ_RL |
12113 | 0 | UINT64_C(302002223), // LR_D_RL |
12114 | 0 | UINT64_C(268443695), // LR_W |
12115 | 0 | UINT64_C(335552559), // LR_W_AQ |
12116 | 0 | UINT64_C(369106991), // LR_W_AQ_RL |
12117 | 0 | UINT64_C(301998127), // LR_W_RL |
12118 | 0 | UINT64_C(55), // LUI |
12119 | 0 | UINT64_C(8195), // LW |
12120 | 0 | UINT64_C(24579), // LWU |
12121 | 0 | UINT64_C(167796787), // MAX |
12122 | 0 | UINT64_C(167800883), // MAXU |
12123 | 0 | UINT64_C(167788595), // MIN |
12124 | 0 | UINT64_C(167792691), // MINU |
12125 | 0 | UINT64_C(2176860275), // MOPR0 |
12126 | 0 | UINT64_C(2177908851), // MOPR1 |
12127 | 0 | UINT64_C(2313175155), // MOPR10 |
12128 | 0 | UINT64_C(2314223731), // MOPR11 |
12129 | 0 | UINT64_C(2378186867), // MOPR12 |
12130 | 0 | UINT64_C(2379235443), // MOPR13 |
12131 | 0 | UINT64_C(2380284019), // MOPR14 |
12132 | 0 | UINT64_C(2381332595), // MOPR15 |
12133 | 0 | UINT64_C(3250602099), // MOPR16 |
12134 | 0 | UINT64_C(3251650675), // MOPR17 |
12135 | 0 | UINT64_C(3252699251), // MOPR18 |
12136 | 0 | UINT64_C(3253747827), // MOPR19 |
12137 | 0 | UINT64_C(2178957427), // MOPR2 |
12138 | 0 | UINT64_C(3317710963), // MOPR20 |
12139 | 0 | UINT64_C(3318759539), // MOPR21 |
12140 | 0 | UINT64_C(3319808115), // MOPR22 |
12141 | 0 | UINT64_C(3320856691), // MOPR23 |
12142 | 0 | UINT64_C(3384819827), // MOPR24 |
12143 | 0 | UINT64_C(3385868403), // MOPR25 |
12144 | 0 | UINT64_C(3386916979), // MOPR26 |
12145 | 0 | UINT64_C(3387965555), // MOPR27 |
12146 | 0 | UINT64_C(3451928691), // MOPR28 |
12147 | 0 | UINT64_C(3452977267), // MOPR29 |
12148 | 0 | UINT64_C(2180006003), // MOPR3 |
12149 | 0 | UINT64_C(3454025843), // MOPR30 |
12150 | 0 | UINT64_C(3455074419), // MOPR31 |
12151 | 0 | UINT64_C(2243969139), // MOPR4 |
12152 | 0 | UINT64_C(2245017715), // MOPR5 |
12153 | 0 | UINT64_C(2246066291), // MOPR6 |
12154 | 0 | UINT64_C(2247114867), // MOPR7 |
12155 | 0 | UINT64_C(2311078003), // MOPR8 |
12156 | 0 | UINT64_C(2312126579), // MOPR9 |
12157 | 0 | UINT64_C(2181054579), // MOPRR0 |
12158 | 0 | UINT64_C(2248163443), // MOPRR1 |
12159 | 0 | UINT64_C(2315272307), // MOPRR2 |
12160 | 0 | UINT64_C(2382381171), // MOPRR3 |
12161 | 0 | UINT64_C(3254796403), // MOPRR4 |
12162 | 0 | UINT64_C(3321905267), // MOPRR5 |
12163 | 0 | UINT64_C(3389014131), // MOPRR6 |
12164 | 0 | UINT64_C(3456122995), // MOPRR7 |
12165 | 0 | UINT64_C(807403635), // MRET |
12166 | 0 | UINT64_C(33554483), // MUL |
12167 | 0 | UINT64_C(33558579), // MULH |
12168 | 0 | UINT64_C(33562675), // MULHSU |
12169 | 0 | UINT64_C(33566771), // MULHU |
12170 | 0 | UINT64_C(33554491), // MULW |
12171 | 0 | UINT64_C(24627), // OR |
12172 | 0 | UINT64_C(678449171), // ORC_B |
12173 | 0 | UINT64_C(24595), // ORI |
12174 | 0 | UINT64_C(1073766451), // ORN |
12175 | 0 | UINT64_C(134234163), // PACK |
12176 | 0 | UINT64_C(134246451), // PACKH |
12177 | 0 | UINT64_C(134234171), // PACKW |
12178 | 0 | UINT64_C(24595), // PREFETCH_I |
12179 | 0 | UINT64_C(1073171), // PREFETCH_R |
12180 | 0 | UINT64_C(3170323), // PREFETCH_W |
12181 | 0 | UINT64_C(33579059), // REM |
12182 | 0 | UINT64_C(33583155), // REMU |
12183 | 0 | UINT64_C(33583163), // REMUW |
12184 | 0 | UINT64_C(33579067), // REMW |
12185 | 0 | UINT64_C(1770016787), // REV8_RV32 |
12186 | 0 | UINT64_C(1803571219), // REV8_RV64 |
12187 | 0 | UINT64_C(1610616883), // ROL |
12188 | 0 | UINT64_C(1610616891), // ROLW |
12189 | 0 | UINT64_C(1610633267), // ROR |
12190 | 0 | UINT64_C(1610633235), // RORI |
12191 | 0 | UINT64_C(1610633243), // RORIW |
12192 | 0 | UINT64_C(1610633275), // RORW |
12193 | 0 | UINT64_C(35), // SB |
12194 | 0 | UINT64_C(402665519), // SC_D |
12195 | 0 | UINT64_C(469774383), // SC_D_AQ |
12196 | 0 | UINT64_C(503328815), // SC_D_AQ_RL |
12197 | 0 | UINT64_C(436219951), // SC_D_RL |
12198 | 0 | UINT64_C(402661423), // SC_W |
12199 | 0 | UINT64_C(469770287), // SC_W_AQ |
12200 | 0 | UINT64_C(503324719), // SC_W_AQ_RL |
12201 | 0 | UINT64_C(436215855), // SC_W_RL |
12202 | 0 | UINT64_C(12323), // SD |
12203 | 0 | UINT64_C(1614811155), // SEXT_B |
12204 | 0 | UINT64_C(1615859731), // SEXT_H |
12205 | 0 | UINT64_C(403701875), // SFENCE_INVAL_IR |
12206 | 0 | UINT64_C(301990003), // SFENCE_VMA |
12207 | 0 | UINT64_C(402653299), // SFENCE_W_INVAL |
12208 | 0 | UINT64_C(4131), // SH |
12209 | 0 | UINT64_C(536879155), // SH1ADD |
12210 | 0 | UINT64_C(536879163), // SH1ADD_UW |
12211 | 0 | UINT64_C(536887347), // SH2ADD |
12212 | 0 | UINT64_C(536887355), // SH2ADD_UW |
12213 | 0 | UINT64_C(536895539), // SH3ADD |
12214 | 0 | UINT64_C(536895547), // SH3ADD_UW |
12215 | 0 | UINT64_C(270536723), // SHA256SIG0 |
12216 | 0 | UINT64_C(271585299), // SHA256SIG1 |
12217 | 0 | UINT64_C(268439571), // SHA256SUM0 |
12218 | 0 | UINT64_C(269488147), // SHA256SUM1 |
12219 | 0 | UINT64_C(274731027), // SHA512SIG0 |
12220 | 0 | UINT64_C(1543503923), // SHA512SIG0H |
12221 | 0 | UINT64_C(1409286195), // SHA512SIG0L |
12222 | 0 | UINT64_C(275779603), // SHA512SIG1 |
12223 | 0 | UINT64_C(1577058355), // SHA512SIG1H |
12224 | 0 | UINT64_C(1442840627), // SHA512SIG1L |
12225 | 0 | UINT64_C(272633875), // SHA512SUM0 |
12226 | 0 | UINT64_C(1342177331), // SHA512SUM0R |
12227 | 0 | UINT64_C(273682451), // SHA512SUM1 |
12228 | 0 | UINT64_C(1375731763), // SHA512SUM1R |
12229 | 0 | UINT64_C(369098867), // SINVAL_VMA |
12230 | 0 | UINT64_C(4147), // SLL |
12231 | 0 | UINT64_C(4115), // SLLI |
12232 | 0 | UINT64_C(4123), // SLLIW |
12233 | 0 | UINT64_C(134221851), // SLLI_UW |
12234 | 0 | UINT64_C(4155), // SLLW |
12235 | 0 | UINT64_C(8243), // SLT |
12236 | 0 | UINT64_C(8211), // SLTI |
12237 | 0 | UINT64_C(12307), // SLTIU |
12238 | 0 | UINT64_C(12339), // SLTU |
12239 | 0 | UINT64_C(276828179), // SM3P0 |
12240 | 0 | UINT64_C(277876755), // SM3P1 |
12241 | 0 | UINT64_C(805306419), // SM4ED |
12242 | 0 | UINT64_C(872415283), // SM4KS |
12243 | 0 | UINT64_C(1073762355), // SRA |
12244 | 0 | UINT64_C(1073762323), // SRAI |
12245 | 0 | UINT64_C(1073762331), // SRAIW |
12246 | 0 | UINT64_C(1073762363), // SRAW |
12247 | 0 | UINT64_C(270532723), // SRET |
12248 | 0 | UINT64_C(20531), // SRL |
12249 | 0 | UINT64_C(20499), // SRLI |
12250 | 0 | UINT64_C(20507), // SRLIW |
12251 | 0 | UINT64_C(20539), // SRLW |
12252 | 0 | UINT64_C(1207971887), // SSAMOSWAP_D |
12253 | 0 | UINT64_C(1275080751), // SSAMOSWAP_D_AQ |
12254 | 0 | UINT64_C(1308635183), // SSAMOSWAP_D_AQ_RL |
12255 | 0 | UINT64_C(1241526319), // SSAMOSWAP_D_RL |
12256 | 0 | UINT64_C(1207967791), // SSAMOSWAP_W |
12257 | 0 | UINT64_C(1275076655), // SSAMOSWAP_W_AQ |
12258 | 0 | UINT64_C(1308631087), // SSAMOSWAP_W_AQ_RL |
12259 | 0 | UINT64_C(1241522223), // SSAMOSWAP_W_RL |
12260 | 0 | UINT64_C(3451928691), // SSPOPCHK |
12261 | 0 | UINT64_C(3456122995), // SSPUSH |
12262 | 0 | UINT64_C(3451928691), // SSRDP |
12263 | 0 | UINT64_C(1073741875), // SUB |
12264 | 0 | UINT64_C(1073741883), // SUBW |
12265 | 0 | UINT64_C(8227), // SW |
12266 | 0 | UINT64_C(2415943691), // THVdotVMAQASU_VV |
12267 | 0 | UINT64_C(2483052555), // THVdotVMAQASU_VX |
12268 | 0 | UINT64_C(2617270283), // THVdotVMAQAUS_VX |
12269 | 0 | UINT64_C(2281725963), // THVdotVMAQAU_VV |
12270 | 0 | UINT64_C(2348834827), // THVdotVMAQAU_VX |
12271 | 0 | UINT64_C(2147508235), // THVdotVMAQA_VV |
12272 | 0 | UINT64_C(2214617099), // THVdotVMAQA_VX |
12273 | 0 | UINT64_C(4107), // TH_ADDSL |
12274 | 0 | UINT64_C(1048587), // TH_DCACHE_CALL |
12275 | 0 | UINT64_C(3145739), // TH_DCACHE_CIALL |
12276 | 0 | UINT64_C(45088779), // TH_DCACHE_CIPA |
12277 | 0 | UINT64_C(36700171), // TH_DCACHE_CISW |
12278 | 0 | UINT64_C(40894475), // TH_DCACHE_CIVA |
12279 | 0 | UINT64_C(42991627), // TH_DCACHE_CPA |
12280 | 0 | UINT64_C(41943051), // TH_DCACHE_CPAL1 |
12281 | 0 | UINT64_C(34603019), // TH_DCACHE_CSW |
12282 | 0 | UINT64_C(38797323), // TH_DCACHE_CVA |
12283 | 0 | UINT64_C(37748747), // TH_DCACHE_CVAL1 |
12284 | 0 | UINT64_C(2097163), // TH_DCACHE_IALL |
12285 | 0 | UINT64_C(44040203), // TH_DCACHE_IPA |
12286 | 0 | UINT64_C(35651595), // TH_DCACHE_ISW |
12287 | 0 | UINT64_C(39845899), // TH_DCACHE_IVA |
12288 | 0 | UINT64_C(8203), // TH_EXT |
12289 | 0 | UINT64_C(12299), // TH_EXTU |
12290 | 0 | UINT64_C(2214596619), // TH_FF0 |
12291 | 0 | UINT64_C(2248151051), // TH_FF1 |
12292 | 0 | UINT64_C(1610637323), // TH_FLRD |
12293 | 0 | UINT64_C(1073766411), // TH_FLRW |
12294 | 0 | UINT64_C(1879072779), // TH_FLURD |
12295 | 0 | UINT64_C(1342201867), // TH_FLURW |
12296 | 0 | UINT64_C(1610641419), // TH_FSRD |
12297 | 0 | UINT64_C(1073770507), // TH_FSRW |
12298 | 0 | UINT64_C(1879076875), // TH_FSURD |
12299 | 0 | UINT64_C(1342205963), // TH_FSURW |
12300 | 0 | UINT64_C(16777227), // TH_ICACHE_IALL |
12301 | 0 | UINT64_C(17825803), // TH_ICACHE_IALLS |
12302 | 0 | UINT64_C(58720267), // TH_ICACHE_IPA |
12303 | 0 | UINT64_C(50331659), // TH_ICACHE_IVA |
12304 | 0 | UINT64_C(22020107), // TH_L2CACHE_CALL |
12305 | 0 | UINT64_C(24117259), // TH_L2CACHE_CIALL |
12306 | 0 | UINT64_C(23068683), // TH_L2CACHE_IALL |
12307 | 0 | UINT64_C(402669579), // TH_LBIA |
12308 | 0 | UINT64_C(134234123), // TH_LBIB |
12309 | 0 | UINT64_C(2550153227), // TH_LBUIA |
12310 | 0 | UINT64_C(2281717771), // TH_LBUIB |
12311 | 0 | UINT64_C(4160765963), // TH_LDD |
12312 | 0 | UINT64_C(2013282315), // TH_LDIA |
12313 | 0 | UINT64_C(1744846859), // TH_LDIB |
12314 | 0 | UINT64_C(939540491), // TH_LHIA |
12315 | 0 | UINT64_C(671105035), // TH_LHIB |
12316 | 0 | UINT64_C(3087024139), // TH_LHUIA |
12317 | 0 | UINT64_C(2818588683), // TH_LHUIB |
12318 | 0 | UINT64_C(16395), // TH_LRB |
12319 | 0 | UINT64_C(2147500043), // TH_LRBU |
12320 | 0 | UINT64_C(1610629131), // TH_LRD |
12321 | 0 | UINT64_C(536887307), // TH_LRH |
12322 | 0 | UINT64_C(2684370955), // TH_LRHU |
12323 | 0 | UINT64_C(1073758219), // TH_LRW |
12324 | 0 | UINT64_C(3221241867), // TH_LRWU |
12325 | 0 | UINT64_C(268451851), // TH_LURB |
12326 | 0 | UINT64_C(2415935499), // TH_LURBU |
12327 | 0 | UINT64_C(1879064587), // TH_LURD |
12328 | 0 | UINT64_C(805322763), // TH_LURH |
12329 | 0 | UINT64_C(2952806411), // TH_LURHU |
12330 | 0 | UINT64_C(1342193675), // TH_LURW |
12331 | 0 | UINT64_C(3489677323), // TH_LURWU |
12332 | 0 | UINT64_C(3758112779), // TH_LWD |
12333 | 0 | UINT64_C(1476411403), // TH_LWIA |
12334 | 0 | UINT64_C(1207975947), // TH_LWIB |
12335 | 0 | UINT64_C(4026548235), // TH_LWUD |
12336 | 0 | UINT64_C(3623895051), // TH_LWUIA |
12337 | 0 | UINT64_C(3355459595), // TH_LWUIB |
12338 | 0 | UINT64_C(536875019), // TH_MULA |
12339 | 0 | UINT64_C(671092747), // TH_MULAH |
12340 | 0 | UINT64_C(603983883), // TH_MULAW |
12341 | 0 | UINT64_C(570429451), // TH_MULS |
12342 | 0 | UINT64_C(704647179), // TH_MULSH |
12343 | 0 | UINT64_C(637538315), // TH_MULSW |
12344 | 0 | UINT64_C(1073745931), // TH_MVEQZ |
12345 | 0 | UINT64_C(1107300363), // TH_MVNEZ |
12346 | 0 | UINT64_C(2181042187), // TH_REV |
12347 | 0 | UINT64_C(2415923211), // TH_REVW |
12348 | 0 | UINT64_C(402673675), // TH_SBIA |
12349 | 0 | UINT64_C(134238219), // TH_SBIB |
12350 | 0 | UINT64_C(4160770059), // TH_SDD |
12351 | 0 | UINT64_C(2013286411), // TH_SDIA |
12352 | 0 | UINT64_C(1744850955), // TH_SDIB |
12353 | 0 | UINT64_C(67108875), // TH_SFENCE_VMAS |
12354 | 0 | UINT64_C(939544587), // TH_SHIA |
12355 | 0 | UINT64_C(671109131), // TH_SHIB |
12356 | 0 | UINT64_C(20491), // TH_SRB |
12357 | 0 | UINT64_C(1610633227), // TH_SRD |
12358 | 0 | UINT64_C(536891403), // TH_SRH |
12359 | 0 | UINT64_C(268439563), // TH_SRRI |
12360 | 0 | UINT64_C(335548427), // TH_SRRIW |
12361 | 0 | UINT64_C(1073762315), // TH_SRW |
12362 | 0 | UINT64_C(268455947), // TH_SURB |
12363 | 0 | UINT64_C(1879068683), // TH_SURD |
12364 | 0 | UINT64_C(805326859), // TH_SURH |
12365 | 0 | UINT64_C(1342197771), // TH_SURW |
12366 | 0 | UINT64_C(3758116875), // TH_SWD |
12367 | 0 | UINT64_C(1476415499), // TH_SWIA |
12368 | 0 | UINT64_C(1207980043), // TH_SWIB |
12369 | 0 | UINT64_C(25165835), // TH_SYNC |
12370 | 0 | UINT64_C(27262987), // TH_SYNC_I |
12371 | 0 | UINT64_C(28311563), // TH_SYNC_IS |
12372 | 0 | UINT64_C(26214411), // TH_SYNC_S |
12373 | 0 | UINT64_C(2281705483), // TH_TST |
12374 | 0 | UINT64_C(2147487755), // TH_TSTNBZ |
12375 | 0 | UINT64_C(3221229683), // UNIMP |
12376 | 0 | UINT64_C(149966867), // UNZIP_RV32 |
12377 | 0 | UINT64_C(536879191), // VAADDU_VV |
12378 | 0 | UINT64_C(536895575), // VAADDU_VX |
12379 | 0 | UINT64_C(603988055), // VAADD_VV |
12380 | 0 | UINT64_C(604004439), // VAADD_VX |
12381 | 0 | UINT64_C(1073754199), // VADC_VIM |
12382 | 0 | UINT64_C(1073741911), // VADC_VVM |
12383 | 0 | UINT64_C(1073758295), // VADC_VXM |
12384 | 0 | UINT64_C(12375), // VADD_VI |
12385 | 0 | UINT64_C(87), // VADD_VV |
12386 | 0 | UINT64_C(16471), // VADD_VX |
12387 | 0 | UINT64_C(2785058935), // VAESDF_VS |
12388 | 0 | UINT64_C(2717950071), // VAESDF_VV |
12389 | 0 | UINT64_C(2785026167), // VAESDM_VS |
12390 | 0 | UINT64_C(2717917303), // VAESDM_VV |
12391 | 0 | UINT64_C(2785124471), // VAESEF_VS |
12392 | 0 | UINT64_C(2718015607), // VAESEF_VV |
12393 | 0 | UINT64_C(2785091703), // VAESEM_VS |
12394 | 0 | UINT64_C(2717982839), // VAESEM_VV |
12395 | 0 | UINT64_C(2315264119), // VAESKF1_VI |
12396 | 0 | UINT64_C(2852135031), // VAESKF2_VI |
12397 | 0 | UINT64_C(2785255543), // VAESZ_VS |
12398 | 0 | UINT64_C(67108951), // VANDN_VV |
12399 | 0 | UINT64_C(67125335), // VANDN_VX |
12400 | 0 | UINT64_C(603992151), // VAND_VI |
12401 | 0 | UINT64_C(603979863), // VAND_VV |
12402 | 0 | UINT64_C(603996247), // VAND_VX |
12403 | 0 | UINT64_C(671096919), // VASUBU_VV |
12404 | 0 | UINT64_C(671113303), // VASUBU_VX |
12405 | 0 | UINT64_C(738205783), // VASUB_VV |
12406 | 0 | UINT64_C(738222167), // VASUB_VX |
12407 | 0 | UINT64_C(1208229975), // VBREV8_V |
12408 | 0 | UINT64_C(1208295511), // VBREV_V |
12409 | 0 | UINT64_C(872423511), // VCLMULH_VV |
12410 | 0 | UINT64_C(872439895), // VCLMULH_VX |
12411 | 0 | UINT64_C(805314647), // VCLMUL_VV |
12412 | 0 | UINT64_C(805331031), // VCLMUL_VX |
12413 | 0 | UINT64_C(1208361047), // VCLZ_V |
12414 | 0 | UINT64_C(1577066583), // VCOMPRESS_VM |
12415 | 0 | UINT64_C(1074274391), // VCPOP_M |
12416 | 0 | UINT64_C(1208426583), // VCPOP_V |
12417 | 0 | UINT64_C(1208393815), // VCTZ_V |
12418 | 0 | UINT64_C(704663643), // VC_FV |
12419 | 0 | UINT64_C(2852147291), // VC_FVV |
12420 | 0 | UINT64_C(4194324571), // VC_FVW |
12421 | 0 | UINT64_C(33566811), // VC_I |
12422 | 0 | UINT64_C(570437723), // VC_IV |
12423 | 0 | UINT64_C(2717921371), // VC_IVV |
12424 | 0 | UINT64_C(4060098651), // VC_IVW |
12425 | 0 | UINT64_C(570425435), // VC_VV |
12426 | 0 | UINT64_C(2717909083), // VC_VVV |
12427 | 0 | UINT64_C(4060086363), // VC_VVW |
12428 | 0 | UINT64_C(671109211), // VC_V_FV |
12429 | 0 | UINT64_C(2818592859), // VC_V_FVV |
12430 | 0 | UINT64_C(4160770139), // VC_V_FVW |
12431 | 0 | UINT64_C(12379), // VC_V_I |
12432 | 0 | UINT64_C(536883291), // VC_V_IV |
12433 | 0 | UINT64_C(2684366939), // VC_V_IVV |
12434 | 0 | UINT64_C(4026544219), // VC_V_IVW |
12435 | 0 | UINT64_C(536871003), // VC_V_VV |
12436 | 0 | UINT64_C(2684354651), // VC_V_VVV |
12437 | 0 | UINT64_C(4026531931), // VC_V_VVW |
12438 | 0 | UINT64_C(16475), // VC_V_X |
12439 | 0 | UINT64_C(536887387), // VC_V_XV |
12440 | 0 | UINT64_C(2684371035), // VC_V_XVV |
12441 | 0 | UINT64_C(4026548315), // VC_V_XVW |
12442 | 0 | UINT64_C(33570907), // VC_X |
12443 | 0 | UINT64_C(570441819), // VC_XV |
12444 | 0 | UINT64_C(2717925467), // VC_XVV |
12445 | 0 | UINT64_C(4060102747), // VC_XVW |
12446 | 0 | UINT64_C(2147491927), // VDIVU_VV |
12447 | 0 | UINT64_C(2147508311), // VDIVU_VX |
12448 | 0 | UINT64_C(2214600791), // VDIV_VV |
12449 | 0 | UINT64_C(2214617175), // VDIV_VX |
12450 | 0 | UINT64_C(20567), // VFADD_VF |
12451 | 0 | UINT64_C(4183), // VFADD_VV |
12452 | 0 | UINT64_C(1275596887), // VFCLASS_V |
12453 | 0 | UINT64_C(1208029271), // VFCVT_F_XU_V |
12454 | 0 | UINT64_C(1208062039), // VFCVT_F_X_V |
12455 | 0 | UINT64_C(1208160343), // VFCVT_RTZ_XU_F_V |
12456 | 0 | UINT64_C(1208193111), // VFCVT_RTZ_X_F_V |
12457 | 0 | UINT64_C(1207963735), // VFCVT_XU_F_V |
12458 | 0 | UINT64_C(1207996503), // VFCVT_X_F_V |
12459 | 0 | UINT64_C(2147504215), // VFDIV_VF |
12460 | 0 | UINT64_C(2147487831), // VFDIV_VV |
12461 | 0 | UINT64_C(1074307159), // VFIRST_M |
12462 | 0 | UINT64_C(2952810583), // VFMACC_VF |
12463 | 0 | UINT64_C(2952794199), // VFMACC_VV |
12464 | 0 | UINT64_C(2684375127), // VFMADD_VF |
12465 | 0 | UINT64_C(2684358743), // VFMADD_VV |
12466 | 0 | UINT64_C(402673751), // VFMAX_VF |
12467 | 0 | UINT64_C(402657367), // VFMAX_VV |
12468 | 0 | UINT64_C(1543524439), // VFMERGE_VFM |
12469 | 0 | UINT64_C(268456023), // VFMIN_VF |
12470 | 0 | UINT64_C(268439639), // VFMIN_VV |
12471 | 0 | UINT64_C(3087028311), // VFMSAC_VF |
12472 | 0 | UINT64_C(3087011927), // VFMSAC_VV |
12473 | 0 | UINT64_C(2818592855), // VFMSUB_VF |
12474 | 0 | UINT64_C(2818576471), // VFMSUB_VV |
12475 | 0 | UINT64_C(2415939671), // VFMUL_VF |
12476 | 0 | UINT64_C(2415923287), // VFMUL_VV |
12477 | 0 | UINT64_C(1107300439), // VFMV_F_S |
12478 | 0 | UINT64_C(1107316823), // VFMV_S_F |
12479 | 0 | UINT64_C(1577078871), // VFMV_V_F |
12480 | 0 | UINT64_C(1208914007), // VFNCVTBF16_F_F_W |
12481 | 0 | UINT64_C(1208619095), // VFNCVT_F_F_W |
12482 | 0 | UINT64_C(1208553559), // VFNCVT_F_XU_W |
12483 | 0 | UINT64_C(1208586327), // VFNCVT_F_X_W |
12484 | 0 | UINT64_C(1208651863), // VFNCVT_ROD_F_F_W |
12485 | 0 | UINT64_C(1208684631), // VFNCVT_RTZ_XU_F_W |
12486 | 0 | UINT64_C(1208717399), // VFNCVT_RTZ_X_F_W |
12487 | 0 | UINT64_C(1208488023), // VFNCVT_XU_F_W |
12488 | 0 | UINT64_C(1208520791), // VFNCVT_X_F_W |
12489 | 0 | UINT64_C(3019919447), // VFNMACC_VF |
12490 | 0 | UINT64_C(3019903063), // VFNMACC_VV |
12491 | 0 | UINT64_C(2751483991), // VFNMADD_VF |
12492 | 0 | UINT64_C(2751467607), // VFNMADD_VV |
12493 | 0 | UINT64_C(3154137175), // VFNMSAC_VF |
12494 | 0 | UINT64_C(3154120791), // VFNMSAC_VV |
12495 | 0 | UINT64_C(2885701719), // VFNMSUB_VF |
12496 | 0 | UINT64_C(2885685335), // VFNMSUB_VV |
12497 | 0 | UINT64_C(2281721947), // VFNRCLIP_XU_F_QF |
12498 | 0 | UINT64_C(2348830811), // VFNRCLIP_X_F_QF |
12499 | 0 | UINT64_C(2214613079), // VFRDIV_VF |
12500 | 0 | UINT64_C(1275236439), // VFREC7_V |
12501 | 0 | UINT64_C(469766231), // VFREDMAX_VS |
12502 | 0 | UINT64_C(335548503), // VFREDMIN_VS |
12503 | 0 | UINT64_C(201330775), // VFREDOSUM_VS |
12504 | 0 | UINT64_C(67113047), // VFREDUSUM_VS |
12505 | 0 | UINT64_C(1275203671), // VFRSQRT7_V |
12506 | 0 | UINT64_C(2617266263), // VFRSUB_VF |
12507 | 0 | UINT64_C(604000343), // VFSGNJN_VF |
12508 | 0 | UINT64_C(603983959), // VFSGNJN_VV |
12509 | 0 | UINT64_C(671109207), // VFSGNJX_VF |
12510 | 0 | UINT64_C(671092823), // VFSGNJX_VV |
12511 | 0 | UINT64_C(536891479), // VFSGNJ_VF |
12512 | 0 | UINT64_C(536875095), // VFSGNJ_VV |
12513 | 0 | UINT64_C(1006653527), // VFSLIDE1DOWN_VF |
12514 | 0 | UINT64_C(939544663), // VFSLIDE1UP_VF |
12515 | 0 | UINT64_C(1275072599), // VFSQRT_V |
12516 | 0 | UINT64_C(134238295), // VFSUB_VF |
12517 | 0 | UINT64_C(134221911), // VFSUB_VV |
12518 | 0 | UINT64_C(3221246039), // VFWADD_VF |
12519 | 0 | UINT64_C(3221229655), // VFWADD_VV |
12520 | 0 | UINT64_C(3489681495), // VFWADD_WF |
12521 | 0 | UINT64_C(3489665111), // VFWADD_WV |
12522 | 0 | UINT64_C(1208389719), // VFWCVTBF16_F_F_V |
12523 | 0 | UINT64_C(1208356951), // VFWCVT_F_F_V |
12524 | 0 | UINT64_C(1208291415), // VFWCVT_F_XU_V |
12525 | 0 | UINT64_C(1208324183), // VFWCVT_F_X_V |
12526 | 0 | UINT64_C(1208422487), // VFWCVT_RTZ_XU_F_V |
12527 | 0 | UINT64_C(1208455255), // VFWCVT_RTZ_X_F_V |
12528 | 0 | UINT64_C(1208225879), // VFWCVT_XU_F_V |
12529 | 0 | UINT64_C(1208258647), // VFWCVT_X_F_V |
12530 | 0 | UINT64_C(3959443543), // VFWMACCBF16_VF |
12531 | 0 | UINT64_C(3959427159), // VFWMACCBF16_VV |
12532 | 0 | UINT64_C(4060090459), // VFWMACC_4x4x4 |
12533 | 0 | UINT64_C(4026552407), // VFWMACC_VF |
12534 | 0 | UINT64_C(4026536023), // VFWMACC_VV |
12535 | 0 | UINT64_C(4160770135), // VFWMSAC_VF |
12536 | 0 | UINT64_C(4160753751), // VFWMSAC_VV |
12537 | 0 | UINT64_C(3758116951), // VFWMUL_VF |
12538 | 0 | UINT64_C(3758100567), // VFWMUL_VV |
12539 | 0 | UINT64_C(4093661271), // VFWNMACC_VF |
12540 | 0 | UINT64_C(4093644887), // VFWNMACC_VV |
12541 | 0 | UINT64_C(4227878999), // VFWNMSAC_VF |
12542 | 0 | UINT64_C(4227862615), // VFWNMSAC_VV |
12543 | 0 | UINT64_C(3422556247), // VFWREDOSUM_VS |
12544 | 0 | UINT64_C(3288338519), // VFWREDUSUM_VS |
12545 | 0 | UINT64_C(3355463767), // VFWSUB_VF |
12546 | 0 | UINT64_C(3355447383), // VFWSUB_VV |
12547 | 0 | UINT64_C(3623899223), // VFWSUB_WF |
12548 | 0 | UINT64_C(3623882839), // VFWSUB_WV |
12549 | 0 | UINT64_C(2986352759), // VGHSH_VV |
12550 | 0 | UINT64_C(2718474359), // VGMUL_VV |
12551 | 0 | UINT64_C(1342742615), // VID_V |
12552 | 0 | UINT64_C(1342709847), // VIOTA_M |
12553 | 0 | UINT64_C(41963527), // VL1RE16_V |
12554 | 0 | UINT64_C(41967623), // VL1RE32_V |
12555 | 0 | UINT64_C(41971719), // VL1RE64_V |
12556 | 0 | UINT64_C(41943047), // VL1RE8_V |
12557 | 0 | UINT64_C(578834439), // VL2RE16_V |
12558 | 0 | UINT64_C(578838535), // VL2RE32_V |
12559 | 0 | UINT64_C(578842631), // VL2RE64_V |
12560 | 0 | UINT64_C(578813959), // VL2RE8_V |
12561 | 0 | UINT64_C(1652576263), // VL4RE16_V |
12562 | 0 | UINT64_C(1652580359), // VL4RE32_V |
12563 | 0 | UINT64_C(1652584455), // VL4RE64_V |
12564 | 0 | UINT64_C(1652555783), // VL4RE8_V |
12565 | 0 | UINT64_C(3800059911), // VL8RE16_V |
12566 | 0 | UINT64_C(3800064007), // VL8RE32_V |
12567 | 0 | UINT64_C(3800068103), // VL8RE64_V |
12568 | 0 | UINT64_C(3800039431), // VL8RE8_V |
12569 | 0 | UINT64_C(16797703), // VLE16FF_V |
12570 | 0 | UINT64_C(20487), // VLE16_V |
12571 | 0 | UINT64_C(16801799), // VLE32FF_V |
12572 | 0 | UINT64_C(24583), // VLE32_V |
12573 | 0 | UINT64_C(16805895), // VLE64FF_V |
12574 | 0 | UINT64_C(28679), // VLE64_V |
12575 | 0 | UINT64_C(16777223), // VLE8FF_V |
12576 | 0 | UINT64_C(7), // VLE8_V |
12577 | 0 | UINT64_C(45088775), // VLM_V |
12578 | 0 | UINT64_C(201347079), // VLOXEI16_V |
12579 | 0 | UINT64_C(201351175), // VLOXEI32_V |
12580 | 0 | UINT64_C(201355271), // VLOXEI64_V |
12581 | 0 | UINT64_C(201326599), // VLOXEI8_V |
12582 | 0 | UINT64_C(738217991), // VLOXSEG2EI16_V |
12583 | 0 | UINT64_C(738222087), // VLOXSEG2EI32_V |
12584 | 0 | UINT64_C(738226183), // VLOXSEG2EI64_V |
12585 | 0 | UINT64_C(738197511), // VLOXSEG2EI8_V |
12586 | 0 | UINT64_C(1275088903), // VLOXSEG3EI16_V |
12587 | 0 | UINT64_C(1275092999), // VLOXSEG3EI32_V |
12588 | 0 | UINT64_C(1275097095), // VLOXSEG3EI64_V |
12589 | 0 | UINT64_C(1275068423), // VLOXSEG3EI8_V |
12590 | 0 | UINT64_C(1811959815), // VLOXSEG4EI16_V |
12591 | 0 | UINT64_C(1811963911), // VLOXSEG4EI32_V |
12592 | 0 | UINT64_C(1811968007), // VLOXSEG4EI64_V |
12593 | 0 | UINT64_C(1811939335), // VLOXSEG4EI8_V |
12594 | 0 | UINT64_C(2348830727), // VLOXSEG5EI16_V |
12595 | 0 | UINT64_C(2348834823), // VLOXSEG5EI32_V |
12596 | 0 | UINT64_C(2348838919), // VLOXSEG5EI64_V |
12597 | 0 | UINT64_C(2348810247), // VLOXSEG5EI8_V |
12598 | 0 | UINT64_C(2885701639), // VLOXSEG6EI16_V |
12599 | 0 | UINT64_C(2885705735), // VLOXSEG6EI32_V |
12600 | 0 | UINT64_C(2885709831), // VLOXSEG6EI64_V |
12601 | 0 | UINT64_C(2885681159), // VLOXSEG6EI8_V |
12602 | 0 | UINT64_C(3422572551), // VLOXSEG7EI16_V |
12603 | 0 | UINT64_C(3422576647), // VLOXSEG7EI32_V |
12604 | 0 | UINT64_C(3422580743), // VLOXSEG7EI64_V |
12605 | 0 | UINT64_C(3422552071), // VLOXSEG7EI8_V |
12606 | 0 | UINT64_C(3959443463), // VLOXSEG8EI16_V |
12607 | 0 | UINT64_C(3959447559), // VLOXSEG8EI32_V |
12608 | 0 | UINT64_C(3959451655), // VLOXSEG8EI64_V |
12609 | 0 | UINT64_C(3959422983), // VLOXSEG8EI8_V |
12610 | 0 | UINT64_C(134238215), // VLSE16_V |
12611 | 0 | UINT64_C(134242311), // VLSE32_V |
12612 | 0 | UINT64_C(134246407), // VLSE64_V |
12613 | 0 | UINT64_C(134217735), // VLSE8_V |
12614 | 0 | UINT64_C(553668615), // VLSEG2E16FF_V |
12615 | 0 | UINT64_C(536891399), // VLSEG2E16_V |
12616 | 0 | UINT64_C(553672711), // VLSEG2E32FF_V |
12617 | 0 | UINT64_C(536895495), // VLSEG2E32_V |
12618 | 0 | UINT64_C(553676807), // VLSEG2E64FF_V |
12619 | 0 | UINT64_C(536899591), // VLSEG2E64_V |
12620 | 0 | UINT64_C(553648135), // VLSEG2E8FF_V |
12621 | 0 | UINT64_C(536870919), // VLSEG2E8_V |
12622 | 0 | UINT64_C(1090539527), // VLSEG3E16FF_V |
12623 | 0 | UINT64_C(1073762311), // VLSEG3E16_V |
12624 | 0 | UINT64_C(1090543623), // VLSEG3E32FF_V |
12625 | 0 | UINT64_C(1073766407), // VLSEG3E32_V |
12626 | 0 | UINT64_C(1090547719), // VLSEG3E64FF_V |
12627 | 0 | UINT64_C(1073770503), // VLSEG3E64_V |
12628 | 0 | UINT64_C(1090519047), // VLSEG3E8FF_V |
12629 | 0 | UINT64_C(1073741831), // VLSEG3E8_V |
12630 | 0 | UINT64_C(1627410439), // VLSEG4E16FF_V |
12631 | 0 | UINT64_C(1610633223), // VLSEG4E16_V |
12632 | 0 | UINT64_C(1627414535), // VLSEG4E32FF_V |
12633 | 0 | UINT64_C(1610637319), // VLSEG4E32_V |
12634 | 0 | UINT64_C(1627418631), // VLSEG4E64FF_V |
12635 | 0 | UINT64_C(1610641415), // VLSEG4E64_V |
12636 | 0 | UINT64_C(1627389959), // VLSEG4E8FF_V |
12637 | 0 | UINT64_C(1610612743), // VLSEG4E8_V |
12638 | 0 | UINT64_C(2164281351), // VLSEG5E16FF_V |
12639 | 0 | UINT64_C(2147504135), // VLSEG5E16_V |
12640 | 0 | UINT64_C(2164285447), // VLSEG5E32FF_V |
12641 | 0 | UINT64_C(2147508231), // VLSEG5E32_V |
12642 | 0 | UINT64_C(2164289543), // VLSEG5E64FF_V |
12643 | 0 | UINT64_C(2147512327), // VLSEG5E64_V |
12644 | 0 | UINT64_C(2164260871), // VLSEG5E8FF_V |
12645 | 0 | UINT64_C(2147483655), // VLSEG5E8_V |
12646 | 0 | UINT64_C(2701152263), // VLSEG6E16FF_V |
12647 | 0 | UINT64_C(2684375047), // VLSEG6E16_V |
12648 | 0 | UINT64_C(2701156359), // VLSEG6E32FF_V |
12649 | 0 | UINT64_C(2684379143), // VLSEG6E32_V |
12650 | 0 | UINT64_C(2701160455), // VLSEG6E64FF_V |
12651 | 0 | UINT64_C(2684383239), // VLSEG6E64_V |
12652 | 0 | UINT64_C(2701131783), // VLSEG6E8FF_V |
12653 | 0 | UINT64_C(2684354567), // VLSEG6E8_V |
12654 | 0 | UINT64_C(3238023175), // VLSEG7E16FF_V |
12655 | 0 | UINT64_C(3221245959), // VLSEG7E16_V |
12656 | 0 | UINT64_C(3238027271), // VLSEG7E32FF_V |
12657 | 0 | UINT64_C(3221250055), // VLSEG7E32_V |
12658 | 0 | UINT64_C(3238031367), // VLSEG7E64FF_V |
12659 | 0 | UINT64_C(3221254151), // VLSEG7E64_V |
12660 | 0 | UINT64_C(3238002695), // VLSEG7E8FF_V |
12661 | 0 | UINT64_C(3221225479), // VLSEG7E8_V |
12662 | 0 | UINT64_C(3774894087), // VLSEG8E16FF_V |
12663 | 0 | UINT64_C(3758116871), // VLSEG8E16_V |
12664 | 0 | UINT64_C(3774898183), // VLSEG8E32FF_V |
12665 | 0 | UINT64_C(3758120967), // VLSEG8E32_V |
12666 | 0 | UINT64_C(3774902279), // VLSEG8E64FF_V |
12667 | 0 | UINT64_C(3758125063), // VLSEG8E64_V |
12668 | 0 | UINT64_C(3774873607), // VLSEG8E8FF_V |
12669 | 0 | UINT64_C(3758096391), // VLSEG8E8_V |
12670 | 0 | UINT64_C(671109127), // VLSSEG2E16_V |
12671 | 0 | UINT64_C(671113223), // VLSSEG2E32_V |
12672 | 0 | UINT64_C(671117319), // VLSSEG2E64_V |
12673 | 0 | UINT64_C(671088647), // VLSSEG2E8_V |
12674 | 0 | UINT64_C(1207980039), // VLSSEG3E16_V |
12675 | 0 | UINT64_C(1207984135), // VLSSEG3E32_V |
12676 | 0 | UINT64_C(1207988231), // VLSSEG3E64_V |
12677 | 0 | UINT64_C(1207959559), // VLSSEG3E8_V |
12678 | 0 | UINT64_C(1744850951), // VLSSEG4E16_V |
12679 | 0 | UINT64_C(1744855047), // VLSSEG4E32_V |
12680 | 0 | UINT64_C(1744859143), // VLSSEG4E64_V |
12681 | 0 | UINT64_C(1744830471), // VLSSEG4E8_V |
12682 | 0 | UINT64_C(2281721863), // VLSSEG5E16_V |
12683 | 0 | UINT64_C(2281725959), // VLSSEG5E32_V |
12684 | 0 | UINT64_C(2281730055), // VLSSEG5E64_V |
12685 | 0 | UINT64_C(2281701383), // VLSSEG5E8_V |
12686 | 0 | UINT64_C(2818592775), // VLSSEG6E16_V |
12687 | 0 | UINT64_C(2818596871), // VLSSEG6E32_V |
12688 | 0 | UINT64_C(2818600967), // VLSSEG6E64_V |
12689 | 0 | UINT64_C(2818572295), // VLSSEG6E8_V |
12690 | 0 | UINT64_C(3355463687), // VLSSEG7E16_V |
12691 | 0 | UINT64_C(3355467783), // VLSSEG7E32_V |
12692 | 0 | UINT64_C(3355471879), // VLSSEG7E64_V |
12693 | 0 | UINT64_C(3355443207), // VLSSEG7E8_V |
12694 | 0 | UINT64_C(3892334599), // VLSSEG8E16_V |
12695 | 0 | UINT64_C(3892338695), // VLSSEG8E32_V |
12696 | 0 | UINT64_C(3892342791), // VLSSEG8E64_V |
12697 | 0 | UINT64_C(3892314119), // VLSSEG8E8_V |
12698 | 0 | UINT64_C(67129351), // VLUXEI16_V |
12699 | 0 | UINT64_C(67133447), // VLUXEI32_V |
12700 | 0 | UINT64_C(67137543), // VLUXEI64_V |
12701 | 0 | UINT64_C(67108871), // VLUXEI8_V |
12702 | 0 | UINT64_C(604000263), // VLUXSEG2EI16_V |
12703 | 0 | UINT64_C(604004359), // VLUXSEG2EI32_V |
12704 | 0 | UINT64_C(604008455), // VLUXSEG2EI64_V |
12705 | 0 | UINT64_C(603979783), // VLUXSEG2EI8_V |
12706 | 0 | UINT64_C(1140871175), // VLUXSEG3EI16_V |
12707 | 0 | UINT64_C(1140875271), // VLUXSEG3EI32_V |
12708 | 0 | UINT64_C(1140879367), // VLUXSEG3EI64_V |
12709 | 0 | UINT64_C(1140850695), // VLUXSEG3EI8_V |
12710 | 0 | UINT64_C(1677742087), // VLUXSEG4EI16_V |
12711 | 0 | UINT64_C(1677746183), // VLUXSEG4EI32_V |
12712 | 0 | UINT64_C(1677750279), // VLUXSEG4EI64_V |
12713 | 0 | UINT64_C(1677721607), // VLUXSEG4EI8_V |
12714 | 0 | UINT64_C(2214612999), // VLUXSEG5EI16_V |
12715 | 0 | UINT64_C(2214617095), // VLUXSEG5EI32_V |
12716 | 0 | UINT64_C(2214621191), // VLUXSEG5EI64_V |
12717 | 0 | UINT64_C(2214592519), // VLUXSEG5EI8_V |
12718 | 0 | UINT64_C(2751483911), // VLUXSEG6EI16_V |
12719 | 0 | UINT64_C(2751488007), // VLUXSEG6EI32_V |
12720 | 0 | UINT64_C(2751492103), // VLUXSEG6EI64_V |
12721 | 0 | UINT64_C(2751463431), // VLUXSEG6EI8_V |
12722 | 0 | UINT64_C(3288354823), // VLUXSEG7EI16_V |
12723 | 0 | UINT64_C(3288358919), // VLUXSEG7EI32_V |
12724 | 0 | UINT64_C(3288363015), // VLUXSEG7EI64_V |
12725 | 0 | UINT64_C(3288334343), // VLUXSEG7EI8_V |
12726 | 0 | UINT64_C(3825225735), // VLUXSEG8EI16_V |
12727 | 0 | UINT64_C(3825229831), // VLUXSEG8EI32_V |
12728 | 0 | UINT64_C(3825233927), // VLUXSEG8EI64_V |
12729 | 0 | UINT64_C(3825205255), // VLUXSEG8EI8_V |
12730 | 0 | UINT64_C(3019907159), // VMACC_VV |
12731 | 0 | UINT64_C(3019923543), // VMACC_VX |
12732 | 0 | UINT64_C(1174417495), // VMADC_VI |
12733 | 0 | UINT64_C(1140863063), // VMADC_VIM |
12734 | 0 | UINT64_C(1174405207), // VMADC_VV |
12735 | 0 | UINT64_C(1140850775), // VMADC_VVM |
12736 | 0 | UINT64_C(1174421591), // VMADC_VX |
12737 | 0 | UINT64_C(1140867159), // VMADC_VXM |
12738 | 0 | UINT64_C(2751471703), // VMADD_VV |
12739 | 0 | UINT64_C(2751488087), // VMADD_VX |
12740 | 0 | UINT64_C(1644175447), // VMANDN_MM |
12741 | 0 | UINT64_C(1711284311), // VMAND_MM |
12742 | 0 | UINT64_C(402653271), // VMAXU_VV |
12743 | 0 | UINT64_C(402669655), // VMAXU_VX |
12744 | 0 | UINT64_C(469762135), // VMAX_VV |
12745 | 0 | UINT64_C(469778519), // VMAX_VX |
12746 | 0 | UINT64_C(1543516247), // VMERGE_VIM |
12747 | 0 | UINT64_C(1543503959), // VMERGE_VVM |
12748 | 0 | UINT64_C(1543520343), // VMERGE_VXM |
12749 | 0 | UINT64_C(1610633303), // VMFEQ_VF |
12750 | 0 | UINT64_C(1610616919), // VMFEQ_VV |
12751 | 0 | UINT64_C(2080395351), // VMFGE_VF |
12752 | 0 | UINT64_C(1946177623), // VMFGT_VF |
12753 | 0 | UINT64_C(1677742167), // VMFLE_VF |
12754 | 0 | UINT64_C(1677725783), // VMFLE_VV |
12755 | 0 | UINT64_C(1811959895), // VMFLT_VF |
12756 | 0 | UINT64_C(1811943511), // VMFLT_VV |
12757 | 0 | UINT64_C(1879068759), // VMFNE_VF |
12758 | 0 | UINT64_C(1879052375), // VMFNE_VV |
12759 | 0 | UINT64_C(268435543), // VMINU_VV |
12760 | 0 | UINT64_C(268451927), // VMINU_VX |
12761 | 0 | UINT64_C(335544407), // VMIN_VV |
12762 | 0 | UINT64_C(335560791), // VMIN_VX |
12763 | 0 | UINT64_C(1979719767), // VMNAND_MM |
12764 | 0 | UINT64_C(2046828631), // VMNOR_MM |
12765 | 0 | UINT64_C(1912610903), // VMORN_MM |
12766 | 0 | UINT64_C(1778393175), // VMOR_MM |
12767 | 0 | UINT64_C(1308622935), // VMSBC_VV |
12768 | 0 | UINT64_C(1275068503), // VMSBC_VVM |
12769 | 0 | UINT64_C(1308639319), // VMSBC_VX |
12770 | 0 | UINT64_C(1275084887), // VMSBC_VXM |
12771 | 0 | UINT64_C(1342218327), // VMSBF_M |
12772 | 0 | UINT64_C(1610625111), // VMSEQ_VI |
12773 | 0 | UINT64_C(1610612823), // VMSEQ_VV |
12774 | 0 | UINT64_C(1610629207), // VMSEQ_VX |
12775 | 0 | UINT64_C(2013278295), // VMSGTU_VI |
12776 | 0 | UINT64_C(2013282391), // VMSGTU_VX |
12777 | 0 | UINT64_C(2080387159), // VMSGT_VI |
12778 | 0 | UINT64_C(2080391255), // VMSGT_VX |
12779 | 0 | UINT64_C(1342283863), // VMSIF_M |
12780 | 0 | UINT64_C(1879060567), // VMSLEU_VI |
12781 | 0 | UINT64_C(1879048279), // VMSLEU_VV |
12782 | 0 | UINT64_C(1879064663), // VMSLEU_VX |
12783 | 0 | UINT64_C(1946169431), // VMSLE_VI |
12784 | 0 | UINT64_C(1946157143), // VMSLE_VV |
12785 | 0 | UINT64_C(1946173527), // VMSLE_VX |
12786 | 0 | UINT64_C(1744830551), // VMSLTU_VV |
12787 | 0 | UINT64_C(1744846935), // VMSLTU_VX |
12788 | 0 | UINT64_C(1811939415), // VMSLT_VV |
12789 | 0 | UINT64_C(1811955799), // VMSLT_VX |
12790 | 0 | UINT64_C(1677733975), // VMSNE_VI |
12791 | 0 | UINT64_C(1677721687), // VMSNE_VV |
12792 | 0 | UINT64_C(1677738071), // VMSNE_VX |
12793 | 0 | UINT64_C(1342251095), // VMSOF_M |
12794 | 0 | UINT64_C(2550145111), // VMULHSU_VV |
12795 | 0 | UINT64_C(2550161495), // VMULHSU_VX |
12796 | 0 | UINT64_C(2415927383), // VMULHU_VV |
12797 | 0 | UINT64_C(2415943767), // VMULHU_VX |
12798 | 0 | UINT64_C(2617253975), // VMULH_VV |
12799 | 0 | UINT64_C(2617270359), // VMULH_VX |
12800 | 0 | UINT64_C(2483036247), // VMUL_VV |
12801 | 0 | UINT64_C(2483052631), // VMUL_VX |
12802 | 0 | UINT64_C(2650812503), // VMV1R_V |
12803 | 0 | UINT64_C(2650845271), // VMV2R_V |
12804 | 0 | UINT64_C(2650910807), // VMV4R_V |
12805 | 0 | UINT64_C(2651041879), // VMV8R_V |
12806 | 0 | UINT64_C(1107320919), // VMV_S_X |
12807 | 0 | UINT64_C(1577070679), // VMV_V_I |
12808 | 0 | UINT64_C(1577058391), // VMV_V_V |
12809 | 0 | UINT64_C(1577074775), // VMV_V_X |
12810 | 0 | UINT64_C(1107304535), // VMV_X_S |
12811 | 0 | UINT64_C(2113937495), // VMXNOR_MM |
12812 | 0 | UINT64_C(1845502039), // VMXOR_MM |
12813 | 0 | UINT64_C(3087020119), // VNCLIPU_WI |
12814 | 0 | UINT64_C(3087007831), // VNCLIPU_WV |
12815 | 0 | UINT64_C(3087024215), // VNCLIPU_WX |
12816 | 0 | UINT64_C(3154128983), // VNCLIP_WI |
12817 | 0 | UINT64_C(3154116695), // VNCLIP_WV |
12818 | 0 | UINT64_C(3154133079), // VNCLIP_WX |
12819 | 0 | UINT64_C(3154124887), // VNMSAC_VV |
12820 | 0 | UINT64_C(3154141271), // VNMSAC_VX |
12821 | 0 | UINT64_C(2885689431), // VNMSUB_VV |
12822 | 0 | UINT64_C(2885705815), // VNMSUB_VX |
12823 | 0 | UINT64_C(3019911255), // VNSRA_WI |
12824 | 0 | UINT64_C(3019898967), // VNSRA_WV |
12825 | 0 | UINT64_C(3019915351), // VNSRA_WX |
12826 | 0 | UINT64_C(2952802391), // VNSRL_WI |
12827 | 0 | UINT64_C(2952790103), // VNSRL_WV |
12828 | 0 | UINT64_C(2952806487), // VNSRL_WX |
12829 | 0 | UINT64_C(671101015), // VOR_VI |
12830 | 0 | UINT64_C(671088727), // VOR_VV |
12831 | 0 | UINT64_C(671105111), // VOR_VX |
12832 | 0 | UINT64_C(3187679323), // VQMACCSU_2x8x2 |
12833 | 0 | UINT64_C(4261421147), // VQMACCSU_4x8x4 |
12834 | 0 | UINT64_C(3120570459), // VQMACCUS_2x8x2 |
12835 | 0 | UINT64_C(4194312283), // VQMACCUS_4x8x4 |
12836 | 0 | UINT64_C(2986352731), // VQMACCU_2x8x2 |
12837 | 0 | UINT64_C(4060094555), // VQMACCU_4x8x4 |
12838 | 0 | UINT64_C(3053461595), // VQMACC_2x8x2 |
12839 | 0 | UINT64_C(4127203419), // VQMACC_4x8x4 |
12840 | 0 | UINT64_C(67117143), // VREDAND_VS |
12841 | 0 | UINT64_C(402661463), // VREDMAXU_VS |
12842 | 0 | UINT64_C(469770327), // VREDMAX_VS |
12843 | 0 | UINT64_C(268443735), // VREDMINU_VS |
12844 | 0 | UINT64_C(335552599), // VREDMIN_VS |
12845 | 0 | UINT64_C(134226007), // VREDOR_VS |
12846 | 0 | UINT64_C(8279), // VREDSUM_VS |
12847 | 0 | UINT64_C(201334871), // VREDXOR_VS |
12848 | 0 | UINT64_C(2281709655), // VREMU_VV |
12849 | 0 | UINT64_C(2281726039), // VREMU_VX |
12850 | 0 | UINT64_C(2348818519), // VREM_VV |
12851 | 0 | UINT64_C(2348834903), // VREM_VX |
12852 | 0 | UINT64_C(1208262743), // VREV8_V |
12853 | 0 | UINT64_C(939524183), // VRGATHEREI16_VV |
12854 | 0 | UINT64_C(805318743), // VRGATHER_VI |
12855 | 0 | UINT64_C(805306455), // VRGATHER_VV |
12856 | 0 | UINT64_C(805322839), // VRGATHER_VX |
12857 | 0 | UINT64_C(1409286231), // VROL_VV |
12858 | 0 | UINT64_C(1409302615), // VROL_VX |
12859 | 0 | UINT64_C(1342189655), // VROR_VI |
12860 | 0 | UINT64_C(1342177367), // VROR_VV |
12861 | 0 | UINT64_C(1342193751), // VROR_VX |
12862 | 0 | UINT64_C(201338967), // VRSUB_VI |
12863 | 0 | UINT64_C(201343063), // VRSUB_VX |
12864 | 0 | UINT64_C(41943079), // VS1R_V |
12865 | 0 | UINT64_C(578813991), // VS2R_V |
12866 | 0 | UINT64_C(1652555815), // VS4R_V |
12867 | 0 | UINT64_C(3800039463), // VS8R_V |
12868 | 0 | UINT64_C(2147496023), // VSADDU_VI |
12869 | 0 | UINT64_C(2147483735), // VSADDU_VV |
12870 | 0 | UINT64_C(2147500119), // VSADDU_VX |
12871 | 0 | UINT64_C(2214604887), // VSADD_VI |
12872 | 0 | UINT64_C(2214592599), // VSADD_VV |
12873 | 0 | UINT64_C(2214608983), // VSADD_VX |
12874 | 0 | UINT64_C(1207959639), // VSBC_VVM |
12875 | 0 | UINT64_C(1207976023), // VSBC_VXM |
12876 | 0 | UINT64_C(20519), // VSE16_V |
12877 | 0 | UINT64_C(24615), // VSE32_V |
12878 | 0 | UINT64_C(28711), // VSE64_V |
12879 | 0 | UINT64_C(39), // VSE8_V |
12880 | 0 | UINT64_C(3221254231), // VSETIVLI |
12881 | 0 | UINT64_C(2147512407), // VSETVL |
12882 | 0 | UINT64_C(28759), // VSETVLI |
12883 | 0 | UINT64_C(1208197207), // VSEXT_VF2 |
12884 | 0 | UINT64_C(1208131671), // VSEXT_VF4 |
12885 | 0 | UINT64_C(1208066135), // VSEXT_VF8 |
12886 | 0 | UINT64_C(3120570487), // VSHA2CH_VV |
12887 | 0 | UINT64_C(3187679351), // VSHA2CL_VV |
12888 | 0 | UINT64_C(3053461623), // VSHA2MS_VV |
12889 | 0 | UINT64_C(1006657623), // VSLIDE1DOWN_VX |
12890 | 0 | UINT64_C(939548759), // VSLIDE1UP_VX |
12891 | 0 | UINT64_C(1006645335), // VSLIDEDOWN_VI |
12892 | 0 | UINT64_C(1006649431), // VSLIDEDOWN_VX |
12893 | 0 | UINT64_C(939536471), // VSLIDEUP_VI |
12894 | 0 | UINT64_C(939540567), // VSLIDEUP_VX |
12895 | 0 | UINT64_C(2483040343), // VSLL_VI |
12896 | 0 | UINT64_C(2483028055), // VSLL_VV |
12897 | 0 | UINT64_C(2483044439), // VSLL_VX |
12898 | 0 | UINT64_C(2919243895), // VSM3C_VI |
12899 | 0 | UINT64_C(2181046391), // VSM3ME_VV |
12900 | 0 | UINT64_C(2248155255), // VSM4K_VI |
12901 | 0 | UINT64_C(2785550455), // VSM4R_VS |
12902 | 0 | UINT64_C(2718441591), // VSM4R_VV |
12903 | 0 | UINT64_C(2617245783), // VSMUL_VV |
12904 | 0 | UINT64_C(2617262167), // VSMUL_VX |
12905 | 0 | UINT64_C(45088807), // VSM_V |
12906 | 0 | UINT64_C(201347111), // VSOXEI16_V |
12907 | 0 | UINT64_C(201351207), // VSOXEI32_V |
12908 | 0 | UINT64_C(201355303), // VSOXEI64_V |
12909 | 0 | UINT64_C(201326631), // VSOXEI8_V |
12910 | 0 | UINT64_C(738218023), // VSOXSEG2EI16_V |
12911 | 0 | UINT64_C(738222119), // VSOXSEG2EI32_V |
12912 | 0 | UINT64_C(738226215), // VSOXSEG2EI64_V |
12913 | 0 | UINT64_C(738197543), // VSOXSEG2EI8_V |
12914 | 0 | UINT64_C(1275088935), // VSOXSEG3EI16_V |
12915 | 0 | UINT64_C(1275093031), // VSOXSEG3EI32_V |
12916 | 0 | UINT64_C(1275097127), // VSOXSEG3EI64_V |
12917 | 0 | UINT64_C(1275068455), // VSOXSEG3EI8_V |
12918 | 0 | UINT64_C(1811959847), // VSOXSEG4EI16_V |
12919 | 0 | UINT64_C(1811963943), // VSOXSEG4EI32_V |
12920 | 0 | UINT64_C(1811968039), // VSOXSEG4EI64_V |
12921 | 0 | UINT64_C(1811939367), // VSOXSEG4EI8_V |
12922 | 0 | UINT64_C(2348830759), // VSOXSEG5EI16_V |
12923 | 0 | UINT64_C(2348834855), // VSOXSEG5EI32_V |
12924 | 0 | UINT64_C(2348838951), // VSOXSEG5EI64_V |
12925 | 0 | UINT64_C(2348810279), // VSOXSEG5EI8_V |
12926 | 0 | UINT64_C(2885701671), // VSOXSEG6EI16_V |
12927 | 0 | UINT64_C(2885705767), // VSOXSEG6EI32_V |
12928 | 0 | UINT64_C(2885709863), // VSOXSEG6EI64_V |
12929 | 0 | UINT64_C(2885681191), // VSOXSEG6EI8_V |
12930 | 0 | UINT64_C(3422572583), // VSOXSEG7EI16_V |
12931 | 0 | UINT64_C(3422576679), // VSOXSEG7EI32_V |
12932 | 0 | UINT64_C(3422580775), // VSOXSEG7EI64_V |
12933 | 0 | UINT64_C(3422552103), // VSOXSEG7EI8_V |
12934 | 0 | UINT64_C(3959443495), // VSOXSEG8EI16_V |
12935 | 0 | UINT64_C(3959447591), // VSOXSEG8EI32_V |
12936 | 0 | UINT64_C(3959451687), // VSOXSEG8EI64_V |
12937 | 0 | UINT64_C(3959423015), // VSOXSEG8EI8_V |
12938 | 0 | UINT64_C(2751475799), // VSRA_VI |
12939 | 0 | UINT64_C(2751463511), // VSRA_VV |
12940 | 0 | UINT64_C(2751479895), // VSRA_VX |
12941 | 0 | UINT64_C(2684366935), // VSRL_VI |
12942 | 0 | UINT64_C(2684354647), // VSRL_VV |
12943 | 0 | UINT64_C(2684371031), // VSRL_VX |
12944 | 0 | UINT64_C(134238247), // VSSE16_V |
12945 | 0 | UINT64_C(134242343), // VSSE32_V |
12946 | 0 | UINT64_C(134246439), // VSSE64_V |
12947 | 0 | UINT64_C(134217767), // VSSE8_V |
12948 | 0 | UINT64_C(536891431), // VSSEG2E16_V |
12949 | 0 | UINT64_C(536895527), // VSSEG2E32_V |
12950 | 0 | UINT64_C(536899623), // VSSEG2E64_V |
12951 | 0 | UINT64_C(536870951), // VSSEG2E8_V |
12952 | 0 | UINT64_C(1073762343), // VSSEG3E16_V |
12953 | 0 | UINT64_C(1073766439), // VSSEG3E32_V |
12954 | 0 | UINT64_C(1073770535), // VSSEG3E64_V |
12955 | 0 | UINT64_C(1073741863), // VSSEG3E8_V |
12956 | 0 | UINT64_C(1610633255), // VSSEG4E16_V |
12957 | 0 | UINT64_C(1610637351), // VSSEG4E32_V |
12958 | 0 | UINT64_C(1610641447), // VSSEG4E64_V |
12959 | 0 | UINT64_C(1610612775), // VSSEG4E8_V |
12960 | 0 | UINT64_C(2147504167), // VSSEG5E16_V |
12961 | 0 | UINT64_C(2147508263), // VSSEG5E32_V |
12962 | 0 | UINT64_C(2147512359), // VSSEG5E64_V |
12963 | 0 | UINT64_C(2147483687), // VSSEG5E8_V |
12964 | 0 | UINT64_C(2684375079), // VSSEG6E16_V |
12965 | 0 | UINT64_C(2684379175), // VSSEG6E32_V |
12966 | 0 | UINT64_C(2684383271), // VSSEG6E64_V |
12967 | 0 | UINT64_C(2684354599), // VSSEG6E8_V |
12968 | 0 | UINT64_C(3221245991), // VSSEG7E16_V |
12969 | 0 | UINT64_C(3221250087), // VSSEG7E32_V |
12970 | 0 | UINT64_C(3221254183), // VSSEG7E64_V |
12971 | 0 | UINT64_C(3221225511), // VSSEG7E8_V |
12972 | 0 | UINT64_C(3758116903), // VSSEG8E16_V |
12973 | 0 | UINT64_C(3758120999), // VSSEG8E32_V |
12974 | 0 | UINT64_C(3758125095), // VSSEG8E64_V |
12975 | 0 | UINT64_C(3758096423), // VSSEG8E8_V |
12976 | 0 | UINT64_C(2885693527), // VSSRA_VI |
12977 | 0 | UINT64_C(2885681239), // VSSRA_VV |
12978 | 0 | UINT64_C(2885697623), // VSSRA_VX |
12979 | 0 | UINT64_C(2818584663), // VSSRL_VI |
12980 | 0 | UINT64_C(2818572375), // VSSRL_VV |
12981 | 0 | UINT64_C(2818588759), // VSSRL_VX |
12982 | 0 | UINT64_C(671109159), // VSSSEG2E16_V |
12983 | 0 | UINT64_C(671113255), // VSSSEG2E32_V |
12984 | 0 | UINT64_C(671117351), // VSSSEG2E64_V |
12985 | 0 | UINT64_C(671088679), // VSSSEG2E8_V |
12986 | 0 | UINT64_C(1207980071), // VSSSEG3E16_V |
12987 | 0 | UINT64_C(1207984167), // VSSSEG3E32_V |
12988 | 0 | UINT64_C(1207988263), // VSSSEG3E64_V |
12989 | 0 | UINT64_C(1207959591), // VSSSEG3E8_V |
12990 | 0 | UINT64_C(1744850983), // VSSSEG4E16_V |
12991 | 0 | UINT64_C(1744855079), // VSSSEG4E32_V |
12992 | 0 | UINT64_C(1744859175), // VSSSEG4E64_V |
12993 | 0 | UINT64_C(1744830503), // VSSSEG4E8_V |
12994 | 0 | UINT64_C(2281721895), // VSSSEG5E16_V |
12995 | 0 | UINT64_C(2281725991), // VSSSEG5E32_V |
12996 | 0 | UINT64_C(2281730087), // VSSSEG5E64_V |
12997 | 0 | UINT64_C(2281701415), // VSSSEG5E8_V |
12998 | 0 | UINT64_C(2818592807), // VSSSEG6E16_V |
12999 | 0 | UINT64_C(2818596903), // VSSSEG6E32_V |
13000 | 0 | UINT64_C(2818600999), // VSSSEG6E64_V |
13001 | 0 | UINT64_C(2818572327), // VSSSEG6E8_V |
13002 | 0 | UINT64_C(3355463719), // VSSSEG7E16_V |
13003 | 0 | UINT64_C(3355467815), // VSSSEG7E32_V |
13004 | 0 | UINT64_C(3355471911), // VSSSEG7E64_V |
13005 | 0 | UINT64_C(3355443239), // VSSSEG7E8_V |
13006 | 0 | UINT64_C(3892334631), // VSSSEG8E16_V |
13007 | 0 | UINT64_C(3892338727), // VSSSEG8E32_V |
13008 | 0 | UINT64_C(3892342823), // VSSSEG8E64_V |
13009 | 0 | UINT64_C(3892314151), // VSSSEG8E8_V |
13010 | 0 | UINT64_C(2281701463), // VSSUBU_VV |
13011 | 0 | UINT64_C(2281717847), // VSSUBU_VX |
13012 | 0 | UINT64_C(2348810327), // VSSUB_VV |
13013 | 0 | UINT64_C(2348826711), // VSSUB_VX |
13014 | 0 | UINT64_C(134217815), // VSUB_VV |
13015 | 0 | UINT64_C(134234199), // VSUB_VX |
13016 | 0 | UINT64_C(67129383), // VSUXEI16_V |
13017 | 0 | UINT64_C(67133479), // VSUXEI32_V |
13018 | 0 | UINT64_C(67137575), // VSUXEI64_V |
13019 | 0 | UINT64_C(67108903), // VSUXEI8_V |
13020 | 0 | UINT64_C(604000295), // VSUXSEG2EI16_V |
13021 | 0 | UINT64_C(604004391), // VSUXSEG2EI32_V |
13022 | 0 | UINT64_C(604008487), // VSUXSEG2EI64_V |
13023 | 0 | UINT64_C(603979815), // VSUXSEG2EI8_V |
13024 | 0 | UINT64_C(1140871207), // VSUXSEG3EI16_V |
13025 | 0 | UINT64_C(1140875303), // VSUXSEG3EI32_V |
13026 | 0 | UINT64_C(1140879399), // VSUXSEG3EI64_V |
13027 | 0 | UINT64_C(1140850727), // VSUXSEG3EI8_V |
13028 | 0 | UINT64_C(1677742119), // VSUXSEG4EI16_V |
13029 | 0 | UINT64_C(1677746215), // VSUXSEG4EI32_V |
13030 | 0 | UINT64_C(1677750311), // VSUXSEG4EI64_V |
13031 | 0 | UINT64_C(1677721639), // VSUXSEG4EI8_V |
13032 | 0 | UINT64_C(2214613031), // VSUXSEG5EI16_V |
13033 | 0 | UINT64_C(2214617127), // VSUXSEG5EI32_V |
13034 | 0 | UINT64_C(2214621223), // VSUXSEG5EI64_V |
13035 | 0 | UINT64_C(2214592551), // VSUXSEG5EI8_V |
13036 | 0 | UINT64_C(2751483943), // VSUXSEG6EI16_V |
13037 | 0 | UINT64_C(2751488039), // VSUXSEG6EI32_V |
13038 | 0 | UINT64_C(2751492135), // VSUXSEG6EI64_V |
13039 | 0 | UINT64_C(2751463463), // VSUXSEG6EI8_V |
13040 | 0 | UINT64_C(3288354855), // VSUXSEG7EI16_V |
13041 | 0 | UINT64_C(3288358951), // VSUXSEG7EI32_V |
13042 | 0 | UINT64_C(3288363047), // VSUXSEG7EI64_V |
13043 | 0 | UINT64_C(3288334375), // VSUXSEG7EI8_V |
13044 | 0 | UINT64_C(3825225767), // VSUXSEG8EI16_V |
13045 | 0 | UINT64_C(3825229863), // VSUXSEG8EI32_V |
13046 | 0 | UINT64_C(3825233959), // VSUXSEG8EI64_V |
13047 | 0 | UINT64_C(3825205287), // VSUXSEG8EI8_V |
13048 | 0 | UINT64_C(24699), // VT_MASKC |
13049 | 0 | UINT64_C(28795), // VT_MASKCN |
13050 | 0 | UINT64_C(3221233751), // VWADDU_VV |
13051 | 0 | UINT64_C(3221250135), // VWADDU_VX |
13052 | 0 | UINT64_C(3489669207), // VWADDU_WV |
13053 | 0 | UINT64_C(3489685591), // VWADDU_WX |
13054 | 0 | UINT64_C(3288342615), // VWADD_VV |
13055 | 0 | UINT64_C(3288358999), // VWADD_VX |
13056 | 0 | UINT64_C(3556778071), // VWADD_WV |
13057 | 0 | UINT64_C(3556794455), // VWADD_WX |
13058 | 0 | UINT64_C(4227866711), // VWMACCSU_VV |
13059 | 0 | UINT64_C(4227883095), // VWMACCSU_VX |
13060 | 0 | UINT64_C(4160774231), // VWMACCUS_VX |
13061 | 0 | UINT64_C(4026540119), // VWMACCU_VV |
13062 | 0 | UINT64_C(4026556503), // VWMACCU_VX |
13063 | 0 | UINT64_C(4093648983), // VWMACC_VV |
13064 | 0 | UINT64_C(4093665367), // VWMACC_VX |
13065 | 0 | UINT64_C(3892322391), // VWMULSU_VV |
13066 | 0 | UINT64_C(3892338775), // VWMULSU_VX |
13067 | 0 | UINT64_C(3758104663), // VWMULU_VV |
13068 | 0 | UINT64_C(3758121047), // VWMULU_VX |
13069 | 0 | UINT64_C(3959431255), // VWMUL_VV |
13070 | 0 | UINT64_C(3959447639), // VWMUL_VX |
13071 | 0 | UINT64_C(3221225559), // VWREDSUMU_VS |
13072 | 0 | UINT64_C(3288334423), // VWREDSUM_VS |
13073 | 0 | UINT64_C(3556782167), // VWSLL_VI |
13074 | 0 | UINT64_C(3556769879), // VWSLL_VV |
13075 | 0 | UINT64_C(3556786263), // VWSLL_VX |
13076 | 0 | UINT64_C(3355451479), // VWSUBU_VV |
13077 | 0 | UINT64_C(3355467863), // VWSUBU_VX |
13078 | 0 | UINT64_C(3623886935), // VWSUBU_WV |
13079 | 0 | UINT64_C(3623903319), // VWSUBU_WX |
13080 | 0 | UINT64_C(3422560343), // VWSUB_VV |
13081 | 0 | UINT64_C(3422576727), // VWSUB_VX |
13082 | 0 | UINT64_C(3690995799), // VWSUB_WV |
13083 | 0 | UINT64_C(3691012183), // VWSUB_WX |
13084 | 0 | UINT64_C(738209879), // VXOR_VI |
13085 | 0 | UINT64_C(738197591), // VXOR_VV |
13086 | 0 | UINT64_C(738213975), // VXOR_VX |
13087 | 0 | UINT64_C(1208164439), // VZEXT_VF2 |
13088 | 0 | UINT64_C(1208098903), // VZEXT_VF4 |
13089 | 0 | UINT64_C(1208033367), // VZEXT_VF8 |
13090 | 0 | UINT64_C(273678451), // WFI |
13091 | 0 | UINT64_C(13631603), // WRS_NTO |
13092 | 0 | UINT64_C(30408819), // WRS_STO |
13093 | 0 | UINT64_C(1073758259), // XNOR |
13094 | 0 | UINT64_C(16435), // XOR |
13095 | 0 | UINT64_C(16403), // XORI |
13096 | 0 | UINT64_C(671096883), // XPERM4 |
13097 | 0 | UINT64_C(671105075), // XPERM8 |
13098 | 0 | UINT64_C(134234163), // ZEXT_H_RV32 |
13099 | 0 | UINT64_C(134234171), // ZEXT_H_RV64 |
13100 | 0 | UINT64_C(149950483), // ZIP_RV32 |
13101 | 0 | UINT64_C(0) |
13102 | 0 | }; |
13103 | 0 | const unsigned opcode = MI.getOpcode(); |
13104 | 0 | uint64_t Value = InstBits[opcode]; |
13105 | 0 | uint64_t op = 0; |
13106 | 0 | (void)op; // suppress warning |
13107 | 0 | switch (opcode) { |
13108 | 0 | case RISCV::CMOP1: |
13109 | 0 | case RISCV::CMOP3: |
13110 | 0 | case RISCV::CMOP5: |
13111 | 0 | case RISCV::CMOP7: |
13112 | 0 | case RISCV::CMOP9: |
13113 | 0 | case RISCV::CMOP11: |
13114 | 0 | case RISCV::CMOP13: |
13115 | 0 | case RISCV::CMOP15: |
13116 | 0 | case RISCV::C_EBREAK: |
13117 | 0 | case RISCV::C_NOP: |
13118 | 0 | case RISCV::C_SSPOPCHK: |
13119 | 0 | case RISCV::C_SSPUSH: |
13120 | 0 | case RISCV::C_UNIMP: |
13121 | 0 | case RISCV::DRET: |
13122 | 0 | case RISCV::EBREAK: |
13123 | 0 | case RISCV::ECALL: |
13124 | 0 | case RISCV::FENCE_I: |
13125 | 0 | case RISCV::FENCE_TSO: |
13126 | 0 | case RISCV::MRET: |
13127 | 0 | case RISCV::SFENCE_INVAL_IR: |
13128 | 0 | case RISCV::SFENCE_W_INVAL: |
13129 | 0 | case RISCV::SRET: |
13130 | 0 | case RISCV::TH_DCACHE_CALL: |
13131 | 0 | case RISCV::TH_DCACHE_CIALL: |
13132 | 0 | case RISCV::TH_DCACHE_IALL: |
13133 | 0 | case RISCV::TH_ICACHE_IALL: |
13134 | 0 | case RISCV::TH_ICACHE_IALLS: |
13135 | 0 | case RISCV::TH_L2CACHE_CALL: |
13136 | 0 | case RISCV::TH_L2CACHE_CIALL: |
13137 | 0 | case RISCV::TH_L2CACHE_IALL: |
13138 | 0 | case RISCV::TH_SYNC: |
13139 | 0 | case RISCV::TH_SYNC_I: |
13140 | 0 | case RISCV::TH_SYNC_IS: |
13141 | 0 | case RISCV::TH_SYNC_S: |
13142 | 0 | case RISCV::UNIMP: |
13143 | 0 | case RISCV::WFI: |
13144 | 0 | case RISCV::WRS_NTO: |
13145 | 0 | case RISCV::WRS_STO: { |
13146 | 0 | break; |
13147 | 0 | } |
13148 | 0 | case RISCV::C_NOP_HINT: { |
13149 | | // op: imm |
13150 | 0 | op = getImmOpValue(MI, 0, Fixups, STI); |
13151 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13152 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13153 | 0 | break; |
13154 | 0 | } |
13155 | 0 | case RISCV::C_LI_HINT: |
13156 | 0 | case RISCV::C_LUI_HINT: { |
13157 | | // op: imm |
13158 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
13159 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13160 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13161 | 0 | break; |
13162 | 0 | } |
13163 | 0 | case RISCV::C_LI: |
13164 | 0 | case RISCV::C_LUI: { |
13165 | | // op: imm |
13166 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
13167 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13168 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13169 | | // op: rd |
13170 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13171 | 0 | op &= UINT64_C(31); |
13172 | 0 | op <<= 7; |
13173 | 0 | Value |= op; |
13174 | 0 | break; |
13175 | 0 | } |
13176 | 0 | case RISCV::VMV_V_I: { |
13177 | | // op: imm |
13178 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
13179 | 0 | op &= UINT64_C(31); |
13180 | 0 | op <<= 15; |
13181 | 0 | Value |= op; |
13182 | | // op: vd |
13183 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13184 | 0 | op &= UINT64_C(31); |
13185 | 0 | op <<= 7; |
13186 | 0 | Value |= op; |
13187 | 0 | break; |
13188 | 0 | } |
13189 | 0 | case RISCV::C_FLDSP: |
13190 | 0 | case RISCV::C_LDSP: { |
13191 | | // op: imm |
13192 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13193 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13194 | 0 | Value |= (op & UINT64_C(24)) << 2; |
13195 | 0 | Value |= (op & UINT64_C(448)) >> 4; |
13196 | | // op: rd |
13197 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13198 | 0 | op &= UINT64_C(31); |
13199 | 0 | op <<= 7; |
13200 | 0 | Value |= op; |
13201 | 0 | break; |
13202 | 0 | } |
13203 | 0 | case RISCV::C_FLWSP: |
13204 | 0 | case RISCV::C_LWSP: { |
13205 | | // op: imm |
13206 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13207 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13208 | 0 | Value |= (op & UINT64_C(28)) << 2; |
13209 | 0 | Value |= (op & UINT64_C(192)) >> 4; |
13210 | | // op: rd |
13211 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13212 | 0 | op &= UINT64_C(31); |
13213 | 0 | op <<= 7; |
13214 | 0 | Value |= op; |
13215 | 0 | break; |
13216 | 0 | } |
13217 | 0 | case RISCV::C_ADDI: |
13218 | 0 | case RISCV::C_ADDIW: { |
13219 | | // op: imm |
13220 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13221 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13222 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13223 | | // op: rd |
13224 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13225 | 0 | op &= UINT64_C(31); |
13226 | 0 | op <<= 7; |
13227 | 0 | Value |= op; |
13228 | 0 | break; |
13229 | 0 | } |
13230 | 0 | case RISCV::C_ANDI: { |
13231 | | // op: imm |
13232 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13233 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13234 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13235 | | // op: rs1 |
13236 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13237 | 0 | op &= UINT64_C(7); |
13238 | 0 | op <<= 7; |
13239 | 0 | Value |= op; |
13240 | 0 | break; |
13241 | 0 | } |
13242 | 0 | case RISCV::C_ADDI4SPN: { |
13243 | | // op: imm |
13244 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13245 | 0 | Value |= (op & UINT64_C(48)) << 7; |
13246 | 0 | Value |= (op & UINT64_C(960)) << 1; |
13247 | 0 | Value |= (op & UINT64_C(4)) << 4; |
13248 | 0 | Value |= (op & UINT64_C(8)) << 2; |
13249 | | // op: rd |
13250 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13251 | 0 | op &= UINT64_C(7); |
13252 | 0 | op <<= 2; |
13253 | 0 | Value |= op; |
13254 | 0 | break; |
13255 | 0 | } |
13256 | 0 | case RISCV::C_ADDI16SP: { |
13257 | | // op: imm |
13258 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13259 | 0 | Value |= (op & UINT64_C(512)) << 3; |
13260 | 0 | Value |= (op & UINT64_C(16)) << 2; |
13261 | 0 | Value |= (op & UINT64_C(64)) >> 1; |
13262 | 0 | Value |= (op & UINT64_C(384)) >> 4; |
13263 | 0 | Value |= (op & UINT64_C(32)) >> 3; |
13264 | 0 | break; |
13265 | 0 | } |
13266 | 0 | case RISCV::C_FSDSP: |
13267 | 0 | case RISCV::C_SDSP: { |
13268 | | // op: imm |
13269 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13270 | 0 | Value |= (op & UINT64_C(56)) << 7; |
13271 | 0 | Value |= (op & UINT64_C(448)) << 1; |
13272 | | // op: rs2 |
13273 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13274 | 0 | op &= UINT64_C(31); |
13275 | 0 | op <<= 2; |
13276 | 0 | Value |= op; |
13277 | 0 | break; |
13278 | 0 | } |
13279 | 0 | case RISCV::C_FSWSP: |
13280 | 0 | case RISCV::C_SWSP: { |
13281 | | // op: imm |
13282 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13283 | 0 | Value |= (op & UINT64_C(60)) << 7; |
13284 | 0 | Value |= (op & UINT64_C(192)) << 1; |
13285 | | // op: rs2 |
13286 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13287 | 0 | op &= UINT64_C(31); |
13288 | 0 | op <<= 2; |
13289 | 0 | Value |= op; |
13290 | 0 | break; |
13291 | 0 | } |
13292 | 0 | case RISCV::C_BEQZ: |
13293 | 0 | case RISCV::C_BNEZ: { |
13294 | | // op: imm |
13295 | 0 | op = getImmOpValueAsr1(MI, 1, Fixups, STI); |
13296 | 0 | Value |= (op & UINT64_C(128)) << 5; |
13297 | 0 | Value |= (op & UINT64_C(12)) << 8; |
13298 | 0 | Value |= (op & UINT64_C(96)); |
13299 | 0 | Value |= (op & UINT64_C(3)) << 3; |
13300 | 0 | Value |= (op & UINT64_C(16)) >> 2; |
13301 | | // op: rs1 |
13302 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13303 | 0 | op &= UINT64_C(7); |
13304 | 0 | op <<= 7; |
13305 | 0 | Value |= op; |
13306 | 0 | break; |
13307 | 0 | } |
13308 | 0 | case RISCV::C_SLLI_HINT: { |
13309 | | // op: imm |
13310 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13311 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13312 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13313 | 0 | break; |
13314 | 0 | } |
13315 | 0 | case RISCV::C_SLLI: { |
13316 | | // op: imm |
13317 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13318 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13319 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13320 | | // op: rd |
13321 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13322 | 0 | op &= UINT64_C(31); |
13323 | 0 | op <<= 7; |
13324 | 0 | Value |= op; |
13325 | 0 | break; |
13326 | 0 | } |
13327 | 0 | case RISCV::C_SRAI: |
13328 | 0 | case RISCV::C_SRLI: { |
13329 | | // op: imm |
13330 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13331 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13332 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13333 | | // op: rs1 |
13334 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13335 | 0 | op &= UINT64_C(7); |
13336 | 0 | op <<= 7; |
13337 | 0 | Value |= op; |
13338 | 0 | break; |
13339 | 0 | } |
13340 | 0 | case RISCV::C_ADDI_NOP: { |
13341 | | // op: imm |
13342 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13343 | 0 | op &= UINT64_C(32); |
13344 | 0 | op <<= 7; |
13345 | 0 | Value |= op; |
13346 | | // op: rd |
13347 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13348 | 0 | op &= UINT64_C(31); |
13349 | 0 | op <<= 7; |
13350 | 0 | Value |= op; |
13351 | 0 | break; |
13352 | 0 | } |
13353 | 0 | case RISCV::PREFETCH_I: |
13354 | 0 | case RISCV::PREFETCH_R: |
13355 | 0 | case RISCV::PREFETCH_W: { |
13356 | | // op: imm12 |
13357 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
13358 | 0 | op &= UINT64_C(4064); |
13359 | 0 | op <<= 20; |
13360 | 0 | Value |= op; |
13361 | | // op: rs1 |
13362 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13363 | 0 | op &= UINT64_C(31); |
13364 | 0 | op <<= 15; |
13365 | 0 | Value |= op; |
13366 | 0 | break; |
13367 | 0 | } |
13368 | 0 | case RISCV::FSD: |
13369 | 0 | case RISCV::FSH: |
13370 | 0 | case RISCV::FSW: |
13371 | 0 | case RISCV::SB: |
13372 | 0 | case RISCV::SD: |
13373 | 0 | case RISCV::SH: |
13374 | 0 | case RISCV::SW: { |
13375 | | // op: imm12 |
13376 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13377 | 0 | Value |= (op & UINT64_C(4064)) << 20; |
13378 | 0 | Value |= (op & UINT64_C(31)) << 7; |
13379 | | // op: rs2 |
13380 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13381 | 0 | op &= UINT64_C(31); |
13382 | 0 | op <<= 20; |
13383 | 0 | Value |= op; |
13384 | | // op: rs1 |
13385 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13386 | 0 | op &= UINT64_C(31); |
13387 | 0 | op <<= 15; |
13388 | 0 | Value |= op; |
13389 | 0 | break; |
13390 | 0 | } |
13391 | 0 | case RISCV::CV_SB_ri_inc: |
13392 | 0 | case RISCV::CV_SH_ri_inc: |
13393 | 0 | case RISCV::CV_SW_ri_inc: { |
13394 | | // op: imm12 |
13395 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
13396 | 0 | Value |= (op & UINT64_C(4064)) << 20; |
13397 | 0 | Value |= (op & UINT64_C(31)) << 7; |
13398 | | // op: rs2 |
13399 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13400 | 0 | op &= UINT64_C(31); |
13401 | 0 | op <<= 20; |
13402 | 0 | Value |= op; |
13403 | | // op: rs1 |
13404 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13405 | 0 | op &= UINT64_C(31); |
13406 | 0 | op <<= 15; |
13407 | 0 | Value |= op; |
13408 | 0 | break; |
13409 | 0 | } |
13410 | 0 | case RISCV::CV_BEQIMM: |
13411 | 0 | case RISCV::CV_BNEIMM: { |
13412 | | // op: imm12 |
13413 | 0 | op = getImmOpValueAsr1(MI, 2, Fixups, STI); |
13414 | 0 | Value |= (op & UINT64_C(2048)) << 20; |
13415 | 0 | Value |= (op & UINT64_C(1008)) << 21; |
13416 | 0 | Value |= (op & UINT64_C(15)) << 8; |
13417 | 0 | Value |= (op & UINT64_C(1024)) >> 3; |
13418 | | // op: rs1 |
13419 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13420 | 0 | op &= UINT64_C(31); |
13421 | 0 | op <<= 15; |
13422 | 0 | Value |= op; |
13423 | | // op: imm5 |
13424 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
13425 | 0 | op &= UINT64_C(31); |
13426 | 0 | op <<= 20; |
13427 | 0 | Value |= op; |
13428 | 0 | break; |
13429 | 0 | } |
13430 | 0 | case RISCV::BEQ: |
13431 | 0 | case RISCV::BGE: |
13432 | 0 | case RISCV::BGEU: |
13433 | 0 | case RISCV::BLT: |
13434 | 0 | case RISCV::BLTU: |
13435 | 0 | case RISCV::BNE: { |
13436 | | // op: imm12 |
13437 | 0 | op = getImmOpValueAsr1(MI, 2, Fixups, STI); |
13438 | 0 | Value |= (op & UINT64_C(2048)) << 20; |
13439 | 0 | Value |= (op & UINT64_C(1008)) << 21; |
13440 | 0 | Value |= (op & UINT64_C(15)) << 8; |
13441 | 0 | Value |= (op & UINT64_C(1024)) >> 3; |
13442 | | // op: rs2 |
13443 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13444 | 0 | op &= UINT64_C(31); |
13445 | 0 | op <<= 20; |
13446 | 0 | Value |= op; |
13447 | | // op: rs1 |
13448 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13449 | 0 | op &= UINT64_C(31); |
13450 | 0 | op <<= 15; |
13451 | 0 | Value |= op; |
13452 | 0 | break; |
13453 | 0 | } |
13454 | 0 | case RISCV::AUIPC: |
13455 | 0 | case RISCV::LUI: { |
13456 | | // op: imm20 |
13457 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
13458 | 0 | op &= UINT64_C(1048575); |
13459 | 0 | op <<= 12; |
13460 | 0 | Value |= op; |
13461 | | // op: rd |
13462 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13463 | 0 | op &= UINT64_C(31); |
13464 | 0 | op <<= 7; |
13465 | 0 | Value |= op; |
13466 | 0 | break; |
13467 | 0 | } |
13468 | 0 | case RISCV::JAL: { |
13469 | | // op: imm20 |
13470 | 0 | op = getImmOpValueAsr1(MI, 1, Fixups, STI); |
13471 | 0 | Value |= (op & UINT64_C(524288)) << 12; |
13472 | 0 | Value |= (op & UINT64_C(1023)) << 21; |
13473 | 0 | Value |= (op & UINT64_C(1024)) << 10; |
13474 | 0 | Value |= (op & UINT64_C(522240)) << 1; |
13475 | | // op: rd |
13476 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13477 | 0 | op &= UINT64_C(31); |
13478 | 0 | op <<= 7; |
13479 | 0 | Value |= op; |
13480 | 0 | break; |
13481 | 0 | } |
13482 | 0 | case RISCV::CM_JALT: { |
13483 | | // op: index |
13484 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13485 | 0 | op &= UINT64_C(255); |
13486 | 0 | op <<= 2; |
13487 | 0 | Value |= op; |
13488 | 0 | break; |
13489 | 0 | } |
13490 | 0 | case RISCV::CM_JT: { |
13491 | | // op: index |
13492 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13493 | 0 | op &= UINT64_C(31); |
13494 | 0 | op <<= 2; |
13495 | 0 | Value |= op; |
13496 | 0 | break; |
13497 | 0 | } |
13498 | 0 | case RISCV::C_J: |
13499 | 0 | case RISCV::C_JAL: { |
13500 | | // op: offset |
13501 | 0 | op = getImmOpValueAsr1(MI, 0, Fixups, STI); |
13502 | 0 | Value |= (op & UINT64_C(1024)) << 2; |
13503 | 0 | Value |= (op & UINT64_C(8)) << 8; |
13504 | 0 | Value |= (op & UINT64_C(384)) << 2; |
13505 | 0 | Value |= (op & UINT64_C(512)) >> 1; |
13506 | 0 | Value |= (op & UINT64_C(32)) << 2; |
13507 | 0 | Value |= (op & UINT64_C(64)); |
13508 | 0 | Value |= (op & UINT64_C(7)) << 3; |
13509 | 0 | Value |= (op & UINT64_C(16)) >> 2; |
13510 | 0 | break; |
13511 | 0 | } |
13512 | 0 | case RISCV::InsnS: { |
13513 | | // op: opcode |
13514 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13515 | 0 | op &= UINT64_C(127); |
13516 | 0 | Value |= op; |
13517 | | // op: funct3 |
13518 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13519 | 0 | op &= UINT64_C(7); |
13520 | 0 | op <<= 12; |
13521 | 0 | Value |= op; |
13522 | | // op: imm12 |
13523 | 0 | op = getImmOpValue(MI, 4, Fixups, STI); |
13524 | 0 | Value |= (op & UINT64_C(4064)) << 20; |
13525 | 0 | Value |= (op & UINT64_C(31)) << 7; |
13526 | | // op: rs2 |
13527 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13528 | 0 | op &= UINT64_C(31); |
13529 | 0 | op <<= 20; |
13530 | 0 | Value |= op; |
13531 | | // op: rs1 |
13532 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13533 | 0 | op &= UINT64_C(31); |
13534 | 0 | op <<= 15; |
13535 | 0 | Value |= op; |
13536 | 0 | break; |
13537 | 0 | } |
13538 | 0 | case RISCV::InsnB: { |
13539 | | // op: opcode |
13540 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13541 | 0 | op &= UINT64_C(127); |
13542 | 0 | Value |= op; |
13543 | | // op: funct3 |
13544 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13545 | 0 | op &= UINT64_C(7); |
13546 | 0 | op <<= 12; |
13547 | 0 | Value |= op; |
13548 | | // op: imm12 |
13549 | 0 | op = getImmOpValueAsr1(MI, 4, Fixups, STI); |
13550 | 0 | Value |= (op & UINT64_C(2048)) << 20; |
13551 | 0 | Value |= (op & UINT64_C(1008)) << 21; |
13552 | 0 | Value |= (op & UINT64_C(15)) << 8; |
13553 | 0 | Value |= (op & UINT64_C(1024)) >> 3; |
13554 | | // op: rs2 |
13555 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13556 | 0 | op &= UINT64_C(31); |
13557 | 0 | op <<= 20; |
13558 | 0 | Value |= op; |
13559 | | // op: rs1 |
13560 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13561 | 0 | op &= UINT64_C(31); |
13562 | 0 | op <<= 15; |
13563 | 0 | Value |= op; |
13564 | 0 | break; |
13565 | 0 | } |
13566 | 0 | case RISCV::InsnCJ: { |
13567 | | // op: opcode |
13568 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13569 | 0 | op &= UINT64_C(3); |
13570 | 0 | Value |= op; |
13571 | | // op: funct3 |
13572 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13573 | 0 | op &= UINT64_C(7); |
13574 | 0 | op <<= 13; |
13575 | 0 | Value |= op; |
13576 | | // op: imm11 |
13577 | 0 | op = getImmOpValueAsr1(MI, 2, Fixups, STI); |
13578 | 0 | Value |= (op & UINT64_C(1024)) << 2; |
13579 | 0 | Value |= (op & UINT64_C(8)) << 8; |
13580 | 0 | Value |= (op & UINT64_C(384)) << 2; |
13581 | 0 | Value |= (op & UINT64_C(512)) >> 1; |
13582 | 0 | Value |= (op & UINT64_C(32)) << 2; |
13583 | 0 | Value |= (op & UINT64_C(64)); |
13584 | 0 | Value |= (op & UINT64_C(7)) << 3; |
13585 | 0 | Value |= (op & UINT64_C(16)) >> 2; |
13586 | 0 | break; |
13587 | 0 | } |
13588 | 0 | case RISCV::InsnCS: { |
13589 | | // op: opcode |
13590 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13591 | 0 | op &= UINT64_C(3); |
13592 | 0 | Value |= op; |
13593 | | // op: funct3 |
13594 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13595 | 0 | op &= UINT64_C(7); |
13596 | 0 | op <<= 13; |
13597 | 0 | Value |= op; |
13598 | | // op: imm5 |
13599 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
13600 | 0 | Value |= (op & UINT64_C(28)) << 8; |
13601 | 0 | Value |= (op & UINT64_C(3)) << 5; |
13602 | | // op: rs2 |
13603 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13604 | 0 | op &= UINT64_C(7); |
13605 | 0 | op <<= 2; |
13606 | 0 | Value |= op; |
13607 | | // op: rs1 |
13608 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13609 | 0 | op &= UINT64_C(7); |
13610 | 0 | op <<= 7; |
13611 | 0 | Value |= op; |
13612 | 0 | break; |
13613 | 0 | } |
13614 | 0 | case RISCV::InsnCSS: { |
13615 | | // op: opcode |
13616 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13617 | 0 | op &= UINT64_C(3); |
13618 | 0 | Value |= op; |
13619 | | // op: funct3 |
13620 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13621 | 0 | op &= UINT64_C(7); |
13622 | 0 | op <<= 13; |
13623 | 0 | Value |= op; |
13624 | | // op: imm6 |
13625 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13626 | 0 | op &= UINT64_C(63); |
13627 | 0 | op <<= 7; |
13628 | 0 | Value |= op; |
13629 | | // op: rs2 |
13630 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13631 | 0 | op &= UINT64_C(31); |
13632 | 0 | op <<= 2; |
13633 | 0 | Value |= op; |
13634 | 0 | break; |
13635 | 0 | } |
13636 | 0 | case RISCV::InsnCB: { |
13637 | | // op: opcode |
13638 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13639 | 0 | op &= UINT64_C(3); |
13640 | 0 | Value |= op; |
13641 | | // op: funct3 |
13642 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13643 | 0 | op &= UINT64_C(7); |
13644 | 0 | op <<= 13; |
13645 | 0 | Value |= op; |
13646 | | // op: imm8 |
13647 | 0 | op = getImmOpValueAsr1(MI, 3, Fixups, STI); |
13648 | 0 | Value |= (op & UINT64_C(128)) << 5; |
13649 | 0 | Value |= (op & UINT64_C(12)) << 8; |
13650 | 0 | Value |= (op & UINT64_C(96)); |
13651 | 0 | Value |= (op & UINT64_C(3)) << 3; |
13652 | 0 | Value |= (op & UINT64_C(16)) >> 2; |
13653 | | // op: rs1 |
13654 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13655 | 0 | op &= UINT64_C(7); |
13656 | 0 | op <<= 7; |
13657 | 0 | Value |= op; |
13658 | 0 | break; |
13659 | 0 | } |
13660 | 0 | case RISCV::InsnR4: { |
13661 | | // op: opcode |
13662 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13663 | 0 | op &= UINT64_C(127); |
13664 | 0 | Value |= op; |
13665 | | // op: funct2 |
13666 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13667 | 0 | op &= UINT64_C(3); |
13668 | 0 | op <<= 25; |
13669 | 0 | Value |= op; |
13670 | | // op: funct3 |
13671 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13672 | 0 | op &= UINT64_C(7); |
13673 | 0 | op <<= 12; |
13674 | 0 | Value |= op; |
13675 | | // op: rs3 |
13676 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
13677 | 0 | op &= UINT64_C(31); |
13678 | 0 | op <<= 27; |
13679 | 0 | Value |= op; |
13680 | | // op: rs2 |
13681 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
13682 | 0 | op &= UINT64_C(31); |
13683 | 0 | op <<= 20; |
13684 | 0 | Value |= op; |
13685 | | // op: rs1 |
13686 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
13687 | 0 | op &= UINT64_C(31); |
13688 | 0 | op <<= 15; |
13689 | 0 | Value |= op; |
13690 | | // op: rd |
13691 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13692 | 0 | op &= UINT64_C(31); |
13693 | 0 | op <<= 7; |
13694 | 0 | Value |= op; |
13695 | 0 | break; |
13696 | 0 | } |
13697 | 0 | case RISCV::InsnI: |
13698 | 0 | case RISCV::InsnI_Mem: { |
13699 | | // op: opcode |
13700 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13701 | 0 | op &= UINT64_C(127); |
13702 | 0 | Value |= op; |
13703 | | // op: funct3 |
13704 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13705 | 0 | op &= UINT64_C(7); |
13706 | 0 | op <<= 12; |
13707 | 0 | Value |= op; |
13708 | | // op: imm12 |
13709 | 0 | op = getImmOpValue(MI, 4, Fixups, STI); |
13710 | 0 | op &= UINT64_C(4095); |
13711 | 0 | op <<= 20; |
13712 | 0 | Value |= op; |
13713 | | // op: rs1 |
13714 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13715 | 0 | op &= UINT64_C(31); |
13716 | 0 | op <<= 15; |
13717 | 0 | Value |= op; |
13718 | | // op: rd |
13719 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13720 | 0 | op &= UINT64_C(31); |
13721 | 0 | op <<= 7; |
13722 | 0 | Value |= op; |
13723 | 0 | break; |
13724 | 0 | } |
13725 | 0 | case RISCV::InsnR: { |
13726 | | // op: opcode |
13727 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13728 | 0 | op &= UINT64_C(127); |
13729 | 0 | Value |= op; |
13730 | | // op: funct7 |
13731 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13732 | 0 | op &= UINT64_C(127); |
13733 | 0 | op <<= 25; |
13734 | 0 | Value |= op; |
13735 | | // op: funct3 |
13736 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13737 | 0 | op &= UINT64_C(7); |
13738 | 0 | op <<= 12; |
13739 | 0 | Value |= op; |
13740 | | // op: rs2 |
13741 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
13742 | 0 | op &= UINT64_C(31); |
13743 | 0 | op <<= 20; |
13744 | 0 | Value |= op; |
13745 | | // op: rs1 |
13746 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
13747 | 0 | op &= UINT64_C(31); |
13748 | 0 | op <<= 15; |
13749 | 0 | Value |= op; |
13750 | | // op: rd |
13751 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13752 | 0 | op &= UINT64_C(31); |
13753 | 0 | op <<= 7; |
13754 | 0 | Value |= op; |
13755 | 0 | break; |
13756 | 0 | } |
13757 | 0 | case RISCV::InsnU: { |
13758 | | // op: opcode |
13759 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13760 | 0 | op &= UINT64_C(127); |
13761 | 0 | Value |= op; |
13762 | | // op: imm20 |
13763 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13764 | 0 | op &= UINT64_C(1048575); |
13765 | 0 | op <<= 12; |
13766 | 0 | Value |= op; |
13767 | | // op: rd |
13768 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13769 | 0 | op &= UINT64_C(31); |
13770 | 0 | op <<= 7; |
13771 | 0 | Value |= op; |
13772 | 0 | break; |
13773 | 0 | } |
13774 | 0 | case RISCV::InsnJ: { |
13775 | | // op: opcode |
13776 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13777 | 0 | op &= UINT64_C(127); |
13778 | 0 | Value |= op; |
13779 | | // op: imm20 |
13780 | 0 | op = getImmOpValueAsr1(MI, 2, Fixups, STI); |
13781 | 0 | op &= UINT64_C(1048575); |
13782 | 0 | op <<= 12; |
13783 | 0 | Value |= op; |
13784 | | // op: rd |
13785 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13786 | 0 | op &= UINT64_C(31); |
13787 | 0 | op <<= 7; |
13788 | 0 | Value |= op; |
13789 | 0 | break; |
13790 | 0 | } |
13791 | 0 | case RISCV::InsnCL: { |
13792 | | // op: opcode |
13793 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13794 | 0 | op &= UINT64_C(3); |
13795 | 0 | Value |= op; |
13796 | | // op: funct3 |
13797 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13798 | 0 | op &= UINT64_C(7); |
13799 | 0 | op <<= 13; |
13800 | 0 | Value |= op; |
13801 | | // op: imm5 |
13802 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
13803 | 0 | Value |= (op & UINT64_C(28)) << 8; |
13804 | 0 | Value |= (op & UINT64_C(3)) << 5; |
13805 | | // op: rd |
13806 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13807 | 0 | op &= UINT64_C(7); |
13808 | 0 | op <<= 2; |
13809 | 0 | Value |= op; |
13810 | | // op: rs1 |
13811 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13812 | 0 | op &= UINT64_C(7); |
13813 | 0 | op <<= 7; |
13814 | 0 | Value |= op; |
13815 | 0 | break; |
13816 | 0 | } |
13817 | 0 | case RISCV::InsnCI: { |
13818 | | // op: opcode |
13819 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13820 | 0 | op &= UINT64_C(3); |
13821 | 0 | Value |= op; |
13822 | | // op: funct3 |
13823 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13824 | 0 | op &= UINT64_C(7); |
13825 | 0 | op <<= 13; |
13826 | 0 | Value |= op; |
13827 | | // op: imm6 |
13828 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
13829 | 0 | Value |= (op & UINT64_C(32)) << 7; |
13830 | 0 | Value |= (op & UINT64_C(31)) << 2; |
13831 | | // op: rd |
13832 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13833 | 0 | op &= UINT64_C(31); |
13834 | 0 | op <<= 7; |
13835 | 0 | Value |= op; |
13836 | 0 | break; |
13837 | 0 | } |
13838 | 0 | case RISCV::InsnCIW: { |
13839 | | // op: opcode |
13840 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13841 | 0 | op &= UINT64_C(3); |
13842 | 0 | Value |= op; |
13843 | | // op: funct3 |
13844 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13845 | 0 | op &= UINT64_C(7); |
13846 | 0 | op <<= 13; |
13847 | 0 | Value |= op; |
13848 | | // op: imm8 |
13849 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13850 | 0 | op &= UINT64_C(255); |
13851 | 0 | op <<= 5; |
13852 | 0 | Value |= op; |
13853 | | // op: rd |
13854 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13855 | 0 | op &= UINT64_C(7); |
13856 | 0 | op <<= 2; |
13857 | 0 | Value |= op; |
13858 | 0 | break; |
13859 | 0 | } |
13860 | 0 | case RISCV::InsnCR: { |
13861 | | // op: opcode |
13862 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13863 | 0 | op &= UINT64_C(3); |
13864 | 0 | Value |= op; |
13865 | | // op: funct4 |
13866 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13867 | 0 | op &= UINT64_C(15); |
13868 | 0 | op <<= 12; |
13869 | 0 | Value |= op; |
13870 | | // op: rs2 |
13871 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13872 | 0 | op &= UINT64_C(31); |
13873 | 0 | op <<= 2; |
13874 | 0 | Value |= op; |
13875 | | // op: rd |
13876 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13877 | 0 | op &= UINT64_C(31); |
13878 | 0 | op <<= 7; |
13879 | 0 | Value |= op; |
13880 | 0 | break; |
13881 | 0 | } |
13882 | 0 | case RISCV::InsnCA: { |
13883 | | // op: opcode |
13884 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13885 | 0 | op &= UINT64_C(3); |
13886 | 0 | Value |= op; |
13887 | | // op: funct6 |
13888 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
13889 | 0 | op &= UINT64_C(63); |
13890 | 0 | op <<= 10; |
13891 | 0 | Value |= op; |
13892 | | // op: funct2 |
13893 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
13894 | 0 | op &= UINT64_C(3); |
13895 | 0 | op <<= 5; |
13896 | 0 | Value |= op; |
13897 | | // op: rd |
13898 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13899 | 0 | op &= UINT64_C(7); |
13900 | 0 | op <<= 7; |
13901 | 0 | Value |= op; |
13902 | | // op: rs2 |
13903 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
13904 | 0 | op &= UINT64_C(7); |
13905 | 0 | op <<= 2; |
13906 | 0 | Value |= op; |
13907 | 0 | break; |
13908 | 0 | } |
13909 | 0 | case RISCV::FENCE: { |
13910 | | // op: pred |
13911 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13912 | 0 | op &= UINT64_C(15); |
13913 | 0 | op <<= 24; |
13914 | 0 | Value |= op; |
13915 | | // op: succ |
13916 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13917 | 0 | op &= UINT64_C(15); |
13918 | 0 | op <<= 20; |
13919 | 0 | Value |= op; |
13920 | 0 | break; |
13921 | 0 | } |
13922 | 0 | case RISCV::SSRDP: { |
13923 | | // op: rd |
13924 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13925 | 0 | op &= UINT64_C(31); |
13926 | 0 | op <<= 7; |
13927 | 0 | Value |= op; |
13928 | 0 | break; |
13929 | 0 | } |
13930 | 0 | case RISCV::CV_LBU_rr: |
13931 | 0 | case RISCV::CV_LB_rr: |
13932 | 0 | case RISCV::CV_LHU_rr: |
13933 | 0 | case RISCV::CV_LH_rr: |
13934 | 0 | case RISCV::CV_LW_rr: { |
13935 | | // op: rd |
13936 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13937 | 0 | op &= UINT64_C(31); |
13938 | 0 | op <<= 7; |
13939 | 0 | Value |= op; |
13940 | | // op: cvrr |
13941 | 0 | op = getRegReg(MI, 1, Fixups, STI); |
13942 | 0 | Value |= (op & UINT64_C(31)) << 20; |
13943 | 0 | Value |= (op & UINT64_C(992)) << 10; |
13944 | 0 | break; |
13945 | 0 | } |
13946 | 0 | case RISCV::FLI_D: |
13947 | 0 | case RISCV::FLI_H: |
13948 | 0 | case RISCV::FLI_S: { |
13949 | | // op: rd |
13950 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13951 | 0 | op &= UINT64_C(31); |
13952 | 0 | op <<= 7; |
13953 | 0 | Value |= op; |
13954 | | // op: imm |
13955 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13956 | 0 | op &= UINT64_C(31); |
13957 | 0 | op <<= 15; |
13958 | 0 | Value |= op; |
13959 | 0 | break; |
13960 | 0 | } |
13961 | 0 | case RISCV::C_FLD: |
13962 | 0 | case RISCV::C_LD: { |
13963 | | // op: rd |
13964 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13965 | 0 | op &= UINT64_C(7); |
13966 | 0 | op <<= 2; |
13967 | 0 | Value |= op; |
13968 | | // op: rs1 |
13969 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13970 | 0 | op &= UINT64_C(7); |
13971 | 0 | op <<= 7; |
13972 | 0 | Value |= op; |
13973 | | // op: imm |
13974 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13975 | 0 | Value |= (op & UINT64_C(56)) << 7; |
13976 | 0 | Value |= (op & UINT64_C(192)) >> 1; |
13977 | 0 | break; |
13978 | 0 | } |
13979 | 0 | case RISCV::C_FLW: |
13980 | 0 | case RISCV::C_LW: { |
13981 | | // op: rd |
13982 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
13983 | 0 | op &= UINT64_C(7); |
13984 | 0 | op <<= 2; |
13985 | 0 | Value |= op; |
13986 | | // op: rs1 |
13987 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
13988 | 0 | op &= UINT64_C(7); |
13989 | 0 | op <<= 7; |
13990 | 0 | Value |= op; |
13991 | | // op: imm |
13992 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
13993 | 0 | Value |= (op & UINT64_C(56)) << 7; |
13994 | 0 | Value |= (op & UINT64_C(4)) << 4; |
13995 | 0 | Value |= (op & UINT64_C(64)) >> 1; |
13996 | 0 | break; |
13997 | 0 | } |
13998 | 0 | case RISCV::C_LH: |
13999 | 0 | case RISCV::C_LHU: { |
14000 | | // op: rd |
14001 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14002 | 0 | op &= UINT64_C(7); |
14003 | 0 | op <<= 2; |
14004 | 0 | Value |= op; |
14005 | | // op: rs1 |
14006 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14007 | 0 | op &= UINT64_C(7); |
14008 | 0 | op <<= 7; |
14009 | 0 | Value |= op; |
14010 | | // op: imm |
14011 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
14012 | 0 | op &= UINT64_C(2); |
14013 | 0 | op <<= 4; |
14014 | 0 | Value |= op; |
14015 | 0 | break; |
14016 | 0 | } |
14017 | 0 | case RISCV::C_LBU: { |
14018 | | // op: rd |
14019 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14020 | 0 | op &= UINT64_C(7); |
14021 | 0 | op <<= 2; |
14022 | 0 | Value |= op; |
14023 | | // op: rs1 |
14024 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14025 | 0 | op &= UINT64_C(7); |
14026 | 0 | op <<= 7; |
14027 | 0 | Value |= op; |
14028 | | // op: imm |
14029 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14030 | 0 | Value |= (op & UINT64_C(1)) << 6; |
14031 | 0 | Value |= (op & UINT64_C(2)) << 4; |
14032 | 0 | break; |
14033 | 0 | } |
14034 | 0 | case RISCV::C_ADDI_HINT_IMM_ZERO: |
14035 | 0 | case RISCV::C_SLLI64_HINT: { |
14036 | | // op: rd |
14037 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14038 | 0 | op &= UINT64_C(31); |
14039 | 0 | op <<= 7; |
14040 | 0 | Value |= op; |
14041 | 0 | break; |
14042 | 0 | } |
14043 | 0 | case RISCV::C_NOT: |
14044 | 0 | case RISCV::C_SEXT_B: |
14045 | 0 | case RISCV::C_SEXT_H: |
14046 | 0 | case RISCV::C_SRAI64_HINT: |
14047 | 0 | case RISCV::C_SRLI64_HINT: |
14048 | 0 | case RISCV::C_ZEXT_B: |
14049 | 0 | case RISCV::C_ZEXT_H: |
14050 | 0 | case RISCV::C_ZEXT_W: { |
14051 | | // op: rd |
14052 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14053 | 0 | op &= UINT64_C(7); |
14054 | 0 | op <<= 7; |
14055 | 0 | Value |= op; |
14056 | 0 | break; |
14057 | 0 | } |
14058 | 0 | case RISCV::CM_POP: |
14059 | 0 | case RISCV::CM_POPRET: |
14060 | 0 | case RISCV::CM_POPRETZ: |
14061 | 0 | case RISCV::CM_PUSH: { |
14062 | | // op: rlist |
14063 | 0 | op = getRlistOpValue(MI, 0, Fixups, STI); |
14064 | 0 | op &= UINT64_C(15); |
14065 | 0 | op <<= 4; |
14066 | 0 | Value |= op; |
14067 | | // op: spimm |
14068 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14069 | 0 | op &= UINT64_C(48); |
14070 | 0 | op >>= 2; |
14071 | 0 | Value |= op; |
14072 | 0 | break; |
14073 | 0 | } |
14074 | 0 | case RISCV::CBO_CLEAN: |
14075 | 0 | case RISCV::CBO_FLUSH: |
14076 | 0 | case RISCV::CBO_INVAL: |
14077 | 0 | case RISCV::CBO_ZERO: |
14078 | 0 | case RISCV::SSPOPCHK: |
14079 | 0 | case RISCV::TH_DCACHE_CIPA: |
14080 | 0 | case RISCV::TH_DCACHE_CISW: |
14081 | 0 | case RISCV::TH_DCACHE_CIVA: |
14082 | 0 | case RISCV::TH_DCACHE_CPA: |
14083 | 0 | case RISCV::TH_DCACHE_CPAL1: |
14084 | 0 | case RISCV::TH_DCACHE_CSW: |
14085 | 0 | case RISCV::TH_DCACHE_CVA: |
14086 | 0 | case RISCV::TH_DCACHE_CVAL1: |
14087 | 0 | case RISCV::TH_DCACHE_IPA: |
14088 | 0 | case RISCV::TH_DCACHE_ISW: |
14089 | 0 | case RISCV::TH_DCACHE_IVA: |
14090 | 0 | case RISCV::TH_ICACHE_IPA: |
14091 | 0 | case RISCV::TH_ICACHE_IVA: { |
14092 | | // op: rs1 |
14093 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14094 | 0 | op &= UINT64_C(31); |
14095 | 0 | op <<= 15; |
14096 | 0 | Value |= op; |
14097 | 0 | break; |
14098 | 0 | } |
14099 | 0 | case RISCV::C_JALR: |
14100 | 0 | case RISCV::C_JR: { |
14101 | | // op: rs1 |
14102 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14103 | 0 | op &= UINT64_C(31); |
14104 | 0 | op <<= 7; |
14105 | 0 | Value |= op; |
14106 | 0 | break; |
14107 | 0 | } |
14108 | 0 | case RISCV::C_MV: { |
14109 | | // op: rs1 |
14110 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14111 | 0 | op &= UINT64_C(31); |
14112 | 0 | op <<= 7; |
14113 | 0 | Value |= op; |
14114 | | // op: rs2 |
14115 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14116 | 0 | op &= UINT64_C(31); |
14117 | 0 | op <<= 2; |
14118 | 0 | Value |= op; |
14119 | 0 | break; |
14120 | 0 | } |
14121 | 0 | case RISCV::FCVTMOD_W_D: |
14122 | 0 | case RISCV::FCVT_BF16_S: |
14123 | 0 | case RISCV::FCVT_D_H: |
14124 | 0 | case RISCV::FCVT_D_H_IN32X: |
14125 | 0 | case RISCV::FCVT_D_H_INX: |
14126 | 0 | case RISCV::FCVT_D_L: |
14127 | 0 | case RISCV::FCVT_D_LU: |
14128 | 0 | case RISCV::FCVT_D_LU_INX: |
14129 | 0 | case RISCV::FCVT_D_L_INX: |
14130 | 0 | case RISCV::FCVT_D_S: |
14131 | 0 | case RISCV::FCVT_D_S_IN32X: |
14132 | 0 | case RISCV::FCVT_D_S_INX: |
14133 | 0 | case RISCV::FCVT_D_W: |
14134 | 0 | case RISCV::FCVT_D_WU: |
14135 | 0 | case RISCV::FCVT_D_WU_IN32X: |
14136 | 0 | case RISCV::FCVT_D_WU_INX: |
14137 | 0 | case RISCV::FCVT_D_W_IN32X: |
14138 | 0 | case RISCV::FCVT_D_W_INX: |
14139 | 0 | case RISCV::FCVT_H_D: |
14140 | 0 | case RISCV::FCVT_H_D_IN32X: |
14141 | 0 | case RISCV::FCVT_H_D_INX: |
14142 | 0 | case RISCV::FCVT_H_L: |
14143 | 0 | case RISCV::FCVT_H_LU: |
14144 | 0 | case RISCV::FCVT_H_LU_INX: |
14145 | 0 | case RISCV::FCVT_H_L_INX: |
14146 | 0 | case RISCV::FCVT_H_S: |
14147 | 0 | case RISCV::FCVT_H_S_INX: |
14148 | 0 | case RISCV::FCVT_H_W: |
14149 | 0 | case RISCV::FCVT_H_WU: |
14150 | 0 | case RISCV::FCVT_H_WU_INX: |
14151 | 0 | case RISCV::FCVT_H_W_INX: |
14152 | 0 | case RISCV::FCVT_LU_D: |
14153 | 0 | case RISCV::FCVT_LU_D_INX: |
14154 | 0 | case RISCV::FCVT_LU_H: |
14155 | 0 | case RISCV::FCVT_LU_H_INX: |
14156 | 0 | case RISCV::FCVT_LU_S: |
14157 | 0 | case RISCV::FCVT_LU_S_INX: |
14158 | 0 | case RISCV::FCVT_L_D: |
14159 | 0 | case RISCV::FCVT_L_D_INX: |
14160 | 0 | case RISCV::FCVT_L_H: |
14161 | 0 | case RISCV::FCVT_L_H_INX: |
14162 | 0 | case RISCV::FCVT_L_S: |
14163 | 0 | case RISCV::FCVT_L_S_INX: |
14164 | 0 | case RISCV::FCVT_S_BF16: |
14165 | 0 | case RISCV::FCVT_S_D: |
14166 | 0 | case RISCV::FCVT_S_D_IN32X: |
14167 | 0 | case RISCV::FCVT_S_D_INX: |
14168 | 0 | case RISCV::FCVT_S_H: |
14169 | 0 | case RISCV::FCVT_S_H_INX: |
14170 | 0 | case RISCV::FCVT_S_L: |
14171 | 0 | case RISCV::FCVT_S_LU: |
14172 | 0 | case RISCV::FCVT_S_LU_INX: |
14173 | 0 | case RISCV::FCVT_S_L_INX: |
14174 | 0 | case RISCV::FCVT_S_W: |
14175 | 0 | case RISCV::FCVT_S_WU: |
14176 | 0 | case RISCV::FCVT_S_WU_INX: |
14177 | 0 | case RISCV::FCVT_S_W_INX: |
14178 | 0 | case RISCV::FCVT_WU_D: |
14179 | 0 | case RISCV::FCVT_WU_D_IN32X: |
14180 | 0 | case RISCV::FCVT_WU_D_INX: |
14181 | 0 | case RISCV::FCVT_WU_H: |
14182 | 0 | case RISCV::FCVT_WU_H_INX: |
14183 | 0 | case RISCV::FCVT_WU_S: |
14184 | 0 | case RISCV::FCVT_WU_S_INX: |
14185 | 0 | case RISCV::FCVT_W_D: |
14186 | 0 | case RISCV::FCVT_W_D_IN32X: |
14187 | 0 | case RISCV::FCVT_W_D_INX: |
14188 | 0 | case RISCV::FCVT_W_H: |
14189 | 0 | case RISCV::FCVT_W_H_INX: |
14190 | 0 | case RISCV::FCVT_W_S: |
14191 | 0 | case RISCV::FCVT_W_S_INX: |
14192 | 0 | case RISCV::FROUNDNX_D: |
14193 | 0 | case RISCV::FROUNDNX_H: |
14194 | 0 | case RISCV::FROUNDNX_S: |
14195 | 0 | case RISCV::FROUND_D: |
14196 | 0 | case RISCV::FROUND_H: |
14197 | 0 | case RISCV::FROUND_S: |
14198 | 0 | case RISCV::FSQRT_D: |
14199 | 0 | case RISCV::FSQRT_D_IN32X: |
14200 | 0 | case RISCV::FSQRT_D_INX: |
14201 | 0 | case RISCV::FSQRT_H: |
14202 | 0 | case RISCV::FSQRT_H_INX: |
14203 | 0 | case RISCV::FSQRT_S: |
14204 | 0 | case RISCV::FSQRT_S_INX: { |
14205 | | // op: rs1 |
14206 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14207 | 0 | op &= UINT64_C(31); |
14208 | 0 | op <<= 15; |
14209 | 0 | Value |= op; |
14210 | | // op: frm |
14211 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14212 | 0 | op &= UINT64_C(7); |
14213 | 0 | op <<= 12; |
14214 | 0 | Value |= op; |
14215 | | // op: rd |
14216 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14217 | 0 | op &= UINT64_C(31); |
14218 | 0 | op <<= 7; |
14219 | 0 | Value |= op; |
14220 | 0 | break; |
14221 | 0 | } |
14222 | 0 | case RISCV::AES64IM: |
14223 | 0 | case RISCV::BREV8: |
14224 | 0 | case RISCV::CLZ: |
14225 | 0 | case RISCV::CLZW: |
14226 | 0 | case RISCV::CPOP: |
14227 | 0 | case RISCV::CPOPW: |
14228 | 0 | case RISCV::CTZ: |
14229 | 0 | case RISCV::CTZW: |
14230 | 0 | case RISCV::CV_ABS: |
14231 | 0 | case RISCV::CV_ABS_B: |
14232 | 0 | case RISCV::CV_ABS_H: |
14233 | 0 | case RISCV::CV_CLB: |
14234 | 0 | case RISCV::CV_CNT: |
14235 | 0 | case RISCV::CV_CPLXCONJ: |
14236 | 0 | case RISCV::CV_EXTBS: |
14237 | 0 | case RISCV::CV_EXTBZ: |
14238 | 0 | case RISCV::CV_EXTHS: |
14239 | 0 | case RISCV::CV_EXTHZ: |
14240 | 0 | case RISCV::CV_FF1: |
14241 | 0 | case RISCV::CV_FL1: |
14242 | 0 | case RISCV::FCLASS_D: |
14243 | 0 | case RISCV::FCLASS_D_IN32X: |
14244 | 0 | case RISCV::FCLASS_D_INX: |
14245 | 0 | case RISCV::FCLASS_H: |
14246 | 0 | case RISCV::FCLASS_H_INX: |
14247 | 0 | case RISCV::FCLASS_S: |
14248 | 0 | case RISCV::FCLASS_S_INX: |
14249 | 0 | case RISCV::FMVH_X_D: |
14250 | 0 | case RISCV::FMV_D_X: |
14251 | 0 | case RISCV::FMV_H_X: |
14252 | 0 | case RISCV::FMV_W_X: |
14253 | 0 | case RISCV::FMV_X_D: |
14254 | 0 | case RISCV::FMV_X_H: |
14255 | 0 | case RISCV::FMV_X_W: |
14256 | 0 | case RISCV::FMV_X_W_FPR64: |
14257 | 0 | case RISCV::HLVX_HU: |
14258 | 0 | case RISCV::HLVX_WU: |
14259 | 0 | case RISCV::HLV_B: |
14260 | 0 | case RISCV::HLV_BU: |
14261 | 0 | case RISCV::HLV_D: |
14262 | 0 | case RISCV::HLV_H: |
14263 | 0 | case RISCV::HLV_HU: |
14264 | 0 | case RISCV::HLV_W: |
14265 | 0 | case RISCV::HLV_WU: |
14266 | 0 | case RISCV::LR_D: |
14267 | 0 | case RISCV::LR_D_AQ: |
14268 | 0 | case RISCV::LR_D_AQ_RL: |
14269 | 0 | case RISCV::LR_D_RL: |
14270 | 0 | case RISCV::LR_W: |
14271 | 0 | case RISCV::LR_W_AQ: |
14272 | 0 | case RISCV::LR_W_AQ_RL: |
14273 | 0 | case RISCV::LR_W_RL: |
14274 | 0 | case RISCV::MOPR0: |
14275 | 0 | case RISCV::MOPR1: |
14276 | 0 | case RISCV::MOPR2: |
14277 | 0 | case RISCV::MOPR3: |
14278 | 0 | case RISCV::MOPR4: |
14279 | 0 | case RISCV::MOPR5: |
14280 | 0 | case RISCV::MOPR6: |
14281 | 0 | case RISCV::MOPR7: |
14282 | 0 | case RISCV::MOPR8: |
14283 | 0 | case RISCV::MOPR9: |
14284 | 0 | case RISCV::MOPR10: |
14285 | 0 | case RISCV::MOPR11: |
14286 | 0 | case RISCV::MOPR12: |
14287 | 0 | case RISCV::MOPR13: |
14288 | 0 | case RISCV::MOPR14: |
14289 | 0 | case RISCV::MOPR15: |
14290 | 0 | case RISCV::MOPR16: |
14291 | 0 | case RISCV::MOPR17: |
14292 | 0 | case RISCV::MOPR18: |
14293 | 0 | case RISCV::MOPR19: |
14294 | 0 | case RISCV::MOPR20: |
14295 | 0 | case RISCV::MOPR21: |
14296 | 0 | case RISCV::MOPR22: |
14297 | 0 | case RISCV::MOPR23: |
14298 | 0 | case RISCV::MOPR24: |
14299 | 0 | case RISCV::MOPR25: |
14300 | 0 | case RISCV::MOPR26: |
14301 | 0 | case RISCV::MOPR27: |
14302 | 0 | case RISCV::MOPR28: |
14303 | 0 | case RISCV::MOPR29: |
14304 | 0 | case RISCV::MOPR30: |
14305 | 0 | case RISCV::MOPR31: |
14306 | 0 | case RISCV::ORC_B: |
14307 | 0 | case RISCV::REV8_RV32: |
14308 | 0 | case RISCV::REV8_RV64: |
14309 | 0 | case RISCV::SEXT_B: |
14310 | 0 | case RISCV::SEXT_H: |
14311 | 0 | case RISCV::SHA256SIG0: |
14312 | 0 | case RISCV::SHA256SIG1: |
14313 | 0 | case RISCV::SHA256SUM0: |
14314 | 0 | case RISCV::SHA256SUM1: |
14315 | 0 | case RISCV::SHA512SIG0: |
14316 | 0 | case RISCV::SHA512SIG1: |
14317 | 0 | case RISCV::SHA512SUM0: |
14318 | 0 | case RISCV::SHA512SUM1: |
14319 | 0 | case RISCV::SM3P0: |
14320 | 0 | case RISCV::SM3P1: |
14321 | 0 | case RISCV::TH_FF0: |
14322 | 0 | case RISCV::TH_FF1: |
14323 | 0 | case RISCV::TH_REV: |
14324 | 0 | case RISCV::TH_REVW: |
14325 | 0 | case RISCV::TH_TSTNBZ: |
14326 | 0 | case RISCV::UNZIP_RV32: |
14327 | 0 | case RISCV::ZEXT_H_RV32: |
14328 | 0 | case RISCV::ZEXT_H_RV64: |
14329 | 0 | case RISCV::ZIP_RV32: { |
14330 | | // op: rs1 |
14331 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14332 | 0 | op &= UINT64_C(31); |
14333 | 0 | op <<= 15; |
14334 | 0 | Value |= op; |
14335 | | // op: rd |
14336 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14337 | 0 | op &= UINT64_C(31); |
14338 | 0 | op <<= 7; |
14339 | 0 | Value |= op; |
14340 | 0 | break; |
14341 | 0 | } |
14342 | 0 | case RISCV::ADDI: |
14343 | 0 | case RISCV::ADDIW: |
14344 | 0 | case RISCV::ANDI: |
14345 | 0 | case RISCV::CV_ELW: |
14346 | 0 | case RISCV::FLD: |
14347 | 0 | case RISCV::FLH: |
14348 | 0 | case RISCV::FLW: |
14349 | 0 | case RISCV::JALR: |
14350 | 0 | case RISCV::LB: |
14351 | 0 | case RISCV::LBU: |
14352 | 0 | case RISCV::LD: |
14353 | 0 | case RISCV::LH: |
14354 | 0 | case RISCV::LHU: |
14355 | 0 | case RISCV::LW: |
14356 | 0 | case RISCV::LWU: |
14357 | 0 | case RISCV::ORI: |
14358 | 0 | case RISCV::SLTI: |
14359 | 0 | case RISCV::SLTIU: |
14360 | 0 | case RISCV::XORI: { |
14361 | | // op: rs1 |
14362 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14363 | 0 | op &= UINT64_C(31); |
14364 | 0 | op <<= 15; |
14365 | 0 | Value |= op; |
14366 | | // op: rd |
14367 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14368 | 0 | op &= UINT64_C(31); |
14369 | 0 | op <<= 7; |
14370 | 0 | Value |= op; |
14371 | | // op: imm12 |
14372 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
14373 | 0 | op &= UINT64_C(4095); |
14374 | 0 | op <<= 20; |
14375 | 0 | Value |= op; |
14376 | 0 | break; |
14377 | 0 | } |
14378 | 0 | case RISCV::CV_CLIP: |
14379 | 0 | case RISCV::CV_CLIPU: { |
14380 | | // op: rs1 |
14381 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14382 | 0 | op &= UINT64_C(31); |
14383 | 0 | op <<= 15; |
14384 | 0 | Value |= op; |
14385 | | // op: rd |
14386 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14387 | 0 | op &= UINT64_C(31); |
14388 | 0 | op <<= 7; |
14389 | 0 | Value |= op; |
14390 | | // op: imm5 |
14391 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14392 | 0 | op &= UINT64_C(31); |
14393 | 0 | op <<= 20; |
14394 | 0 | Value |= op; |
14395 | 0 | break; |
14396 | 0 | } |
14397 | 0 | case RISCV::CV_ADD_SCI_B: |
14398 | 0 | case RISCV::CV_ADD_SCI_H: |
14399 | 0 | case RISCV::CV_AND_SCI_B: |
14400 | 0 | case RISCV::CV_AND_SCI_H: |
14401 | 0 | case RISCV::CV_AVG_SCI_B: |
14402 | 0 | case RISCV::CV_AVG_SCI_H: |
14403 | 0 | case RISCV::CV_CMPEQ_SCI_B: |
14404 | 0 | case RISCV::CV_CMPEQ_SCI_H: |
14405 | 0 | case RISCV::CV_CMPGE_SCI_B: |
14406 | 0 | case RISCV::CV_CMPGE_SCI_H: |
14407 | 0 | case RISCV::CV_CMPGT_SCI_B: |
14408 | 0 | case RISCV::CV_CMPGT_SCI_H: |
14409 | 0 | case RISCV::CV_CMPLE_SCI_B: |
14410 | 0 | case RISCV::CV_CMPLE_SCI_H: |
14411 | 0 | case RISCV::CV_CMPLT_SCI_B: |
14412 | 0 | case RISCV::CV_CMPLT_SCI_H: |
14413 | 0 | case RISCV::CV_CMPNE_SCI_B: |
14414 | 0 | case RISCV::CV_CMPNE_SCI_H: |
14415 | 0 | case RISCV::CV_DOTSP_SCI_B: |
14416 | 0 | case RISCV::CV_DOTSP_SCI_H: |
14417 | 0 | case RISCV::CV_DOTUSP_SCI_B: |
14418 | 0 | case RISCV::CV_DOTUSP_SCI_H: |
14419 | 0 | case RISCV::CV_MAX_SCI_B: |
14420 | 0 | case RISCV::CV_MAX_SCI_H: |
14421 | 0 | case RISCV::CV_MIN_SCI_B: |
14422 | 0 | case RISCV::CV_MIN_SCI_H: |
14423 | 0 | case RISCV::CV_OR_SCI_B: |
14424 | 0 | case RISCV::CV_OR_SCI_H: |
14425 | 0 | case RISCV::CV_SUB_SCI_B: |
14426 | 0 | case RISCV::CV_SUB_SCI_H: |
14427 | 0 | case RISCV::CV_XOR_SCI_B: |
14428 | 0 | case RISCV::CV_XOR_SCI_H: { |
14429 | | // op: rs1 |
14430 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14431 | 0 | op &= UINT64_C(31); |
14432 | 0 | op <<= 15; |
14433 | 0 | Value |= op; |
14434 | | // op: rd |
14435 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14436 | 0 | op &= UINT64_C(31); |
14437 | 0 | op <<= 7; |
14438 | 0 | Value |= op; |
14439 | | // op: imm6 |
14440 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
14441 | 0 | Value |= (op & UINT64_C(1)) << 25; |
14442 | 0 | Value |= (op & UINT64_C(62)) << 19; |
14443 | 0 | break; |
14444 | 0 | } |
14445 | 0 | case RISCV::CV_AVGU_SCI_B: |
14446 | 0 | case RISCV::CV_AVGU_SCI_H: |
14447 | 0 | case RISCV::CV_CMPGEU_SCI_B: |
14448 | 0 | case RISCV::CV_CMPGEU_SCI_H: |
14449 | 0 | case RISCV::CV_CMPGTU_SCI_B: |
14450 | 0 | case RISCV::CV_CMPGTU_SCI_H: |
14451 | 0 | case RISCV::CV_CMPLEU_SCI_B: |
14452 | 0 | case RISCV::CV_CMPLEU_SCI_H: |
14453 | 0 | case RISCV::CV_CMPLTU_SCI_B: |
14454 | 0 | case RISCV::CV_CMPLTU_SCI_H: |
14455 | 0 | case RISCV::CV_DOTUP_SCI_B: |
14456 | 0 | case RISCV::CV_DOTUP_SCI_H: |
14457 | 0 | case RISCV::CV_EXTRACTU_B: |
14458 | 0 | case RISCV::CV_EXTRACTU_H: |
14459 | 0 | case RISCV::CV_EXTRACT_B: |
14460 | 0 | case RISCV::CV_EXTRACT_H: |
14461 | 0 | case RISCV::CV_MAXU_SCI_B: |
14462 | 0 | case RISCV::CV_MAXU_SCI_H: |
14463 | 0 | case RISCV::CV_MINU_SCI_B: |
14464 | 0 | case RISCV::CV_MINU_SCI_H: |
14465 | 0 | case RISCV::CV_SHUFFLEI0_SCI_B: |
14466 | 0 | case RISCV::CV_SHUFFLEI1_SCI_B: |
14467 | 0 | case RISCV::CV_SHUFFLEI2_SCI_B: |
14468 | 0 | case RISCV::CV_SHUFFLEI3_SCI_B: |
14469 | 0 | case RISCV::CV_SHUFFLE_SCI_H: |
14470 | 0 | case RISCV::CV_SLL_SCI_B: |
14471 | 0 | case RISCV::CV_SLL_SCI_H: |
14472 | 0 | case RISCV::CV_SRA_SCI_B: |
14473 | 0 | case RISCV::CV_SRA_SCI_H: |
14474 | 0 | case RISCV::CV_SRL_SCI_B: |
14475 | 0 | case RISCV::CV_SRL_SCI_H: { |
14476 | | // op: rs1 |
14477 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14478 | 0 | op &= UINT64_C(31); |
14479 | 0 | op <<= 15; |
14480 | 0 | Value |= op; |
14481 | | // op: rd |
14482 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14483 | 0 | op &= UINT64_C(31); |
14484 | 0 | op <<= 7; |
14485 | 0 | Value |= op; |
14486 | | // op: imm6 |
14487 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14488 | 0 | Value |= (op & UINT64_C(1)) << 25; |
14489 | 0 | Value |= (op & UINT64_C(62)) << 19; |
14490 | 0 | break; |
14491 | 0 | } |
14492 | 0 | case RISCV::CV_BCLR: |
14493 | 0 | case RISCV::CV_BITREV: |
14494 | 0 | case RISCV::CV_BSET: |
14495 | 0 | case RISCV::CV_EXTRACT: |
14496 | 0 | case RISCV::CV_EXTRACTU: { |
14497 | | // op: rs1 |
14498 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14499 | 0 | op &= UINT64_C(31); |
14500 | 0 | op <<= 15; |
14501 | 0 | Value |= op; |
14502 | | // op: rd |
14503 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14504 | 0 | op &= UINT64_C(31); |
14505 | 0 | op <<= 7; |
14506 | 0 | Value |= op; |
14507 | | // op: is3 |
14508 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14509 | 0 | op &= UINT64_C(31); |
14510 | 0 | op <<= 25; |
14511 | 0 | Value |= op; |
14512 | | // op: is2 |
14513 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
14514 | 0 | op &= UINT64_C(31); |
14515 | 0 | op <<= 20; |
14516 | 0 | Value |= op; |
14517 | 0 | break; |
14518 | 0 | } |
14519 | 0 | case RISCV::TH_EXT: |
14520 | 0 | case RISCV::TH_EXTU: { |
14521 | | // op: rs1 |
14522 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14523 | 0 | op &= UINT64_C(31); |
14524 | 0 | op <<= 15; |
14525 | 0 | Value |= op; |
14526 | | // op: rd |
14527 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14528 | 0 | op &= UINT64_C(31); |
14529 | 0 | op <<= 7; |
14530 | 0 | Value |= op; |
14531 | | // op: msb |
14532 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14533 | 0 | op &= UINT64_C(63); |
14534 | 0 | op <<= 26; |
14535 | 0 | Value |= op; |
14536 | | // op: lsb |
14537 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
14538 | 0 | op &= UINT64_C(63); |
14539 | 0 | op <<= 20; |
14540 | 0 | Value |= op; |
14541 | 0 | break; |
14542 | 0 | } |
14543 | 0 | case RISCV::AES64KS1I: { |
14544 | | // op: rs1 |
14545 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14546 | 0 | op &= UINT64_C(31); |
14547 | 0 | op <<= 15; |
14548 | 0 | Value |= op; |
14549 | | // op: rd |
14550 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14551 | 0 | op &= UINT64_C(31); |
14552 | 0 | op <<= 7; |
14553 | 0 | Value |= op; |
14554 | | // op: rnum |
14555 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
14556 | 0 | op &= UINT64_C(15); |
14557 | 0 | op <<= 20; |
14558 | 0 | Value |= op; |
14559 | 0 | break; |
14560 | 0 | } |
14561 | 0 | case RISCV::RORIW: |
14562 | 0 | case RISCV::SLLIW: |
14563 | 0 | case RISCV::SRAIW: |
14564 | 0 | case RISCV::SRLIW: |
14565 | 0 | case RISCV::TH_SRRIW: { |
14566 | | // op: rs1 |
14567 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14568 | 0 | op &= UINT64_C(31); |
14569 | 0 | op <<= 15; |
14570 | 0 | Value |= op; |
14571 | | // op: rd |
14572 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14573 | 0 | op &= UINT64_C(31); |
14574 | 0 | op <<= 7; |
14575 | 0 | Value |= op; |
14576 | | // op: shamt |
14577 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14578 | 0 | op &= UINT64_C(31); |
14579 | 0 | op <<= 20; |
14580 | 0 | Value |= op; |
14581 | 0 | break; |
14582 | 0 | } |
14583 | 0 | case RISCV::BCLRI: |
14584 | 0 | case RISCV::BEXTI: |
14585 | 0 | case RISCV::BINVI: |
14586 | 0 | case RISCV::BSETI: |
14587 | 0 | case RISCV::RORI: |
14588 | 0 | case RISCV::SLLI: |
14589 | 0 | case RISCV::SLLI_UW: |
14590 | 0 | case RISCV::SRAI: |
14591 | 0 | case RISCV::SRLI: |
14592 | 0 | case RISCV::TH_SRRI: |
14593 | 0 | case RISCV::TH_TST: { |
14594 | | // op: rs1 |
14595 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14596 | 0 | op &= UINT64_C(31); |
14597 | 0 | op <<= 15; |
14598 | 0 | Value |= op; |
14599 | | // op: rd |
14600 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14601 | 0 | op &= UINT64_C(31); |
14602 | 0 | op <<= 7; |
14603 | 0 | Value |= op; |
14604 | | // op: shamt |
14605 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14606 | 0 | op &= UINT64_C(63); |
14607 | 0 | op <<= 20; |
14608 | 0 | Value |= op; |
14609 | 0 | break; |
14610 | 0 | } |
14611 | 0 | case RISCV::VSETVLI: { |
14612 | | // op: rs1 |
14613 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14614 | 0 | op &= UINT64_C(31); |
14615 | 0 | op <<= 15; |
14616 | 0 | Value |= op; |
14617 | | // op: rd |
14618 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14619 | 0 | op &= UINT64_C(31); |
14620 | 0 | op <<= 7; |
14621 | 0 | Value |= op; |
14622 | | // op: vtypei |
14623 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14624 | 0 | op &= UINT64_C(2047); |
14625 | 0 | op <<= 20; |
14626 | 0 | Value |= op; |
14627 | 0 | break; |
14628 | 0 | } |
14629 | 0 | case RISCV::VFMV_V_F: |
14630 | 0 | case RISCV::VL1RE8_V: |
14631 | 0 | case RISCV::VL1RE16_V: |
14632 | 0 | case RISCV::VL1RE32_V: |
14633 | 0 | case RISCV::VL1RE64_V: |
14634 | 0 | case RISCV::VL2RE8_V: |
14635 | 0 | case RISCV::VL2RE16_V: |
14636 | 0 | case RISCV::VL2RE32_V: |
14637 | 0 | case RISCV::VL2RE64_V: |
14638 | 0 | case RISCV::VL4RE8_V: |
14639 | 0 | case RISCV::VL4RE16_V: |
14640 | 0 | case RISCV::VL4RE32_V: |
14641 | 0 | case RISCV::VL4RE64_V: |
14642 | 0 | case RISCV::VL8RE8_V: |
14643 | 0 | case RISCV::VL8RE16_V: |
14644 | 0 | case RISCV::VL8RE32_V: |
14645 | 0 | case RISCV::VL8RE64_V: |
14646 | 0 | case RISCV::VLM_V: |
14647 | 0 | case RISCV::VMV_V_X: { |
14648 | | // op: rs1 |
14649 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14650 | 0 | op &= UINT64_C(31); |
14651 | 0 | op <<= 15; |
14652 | 0 | Value |= op; |
14653 | | // op: vd |
14654 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14655 | 0 | op &= UINT64_C(31); |
14656 | 0 | op <<= 7; |
14657 | 0 | Value |= op; |
14658 | 0 | break; |
14659 | 0 | } |
14660 | 0 | case RISCV::VLE8FF_V: |
14661 | 0 | case RISCV::VLE8_V: |
14662 | 0 | case RISCV::VLE16FF_V: |
14663 | 0 | case RISCV::VLE16_V: |
14664 | 0 | case RISCV::VLE32FF_V: |
14665 | 0 | case RISCV::VLE32_V: |
14666 | 0 | case RISCV::VLE64FF_V: |
14667 | 0 | case RISCV::VLE64_V: |
14668 | 0 | case RISCV::VLSEG2E8FF_V: |
14669 | 0 | case RISCV::VLSEG2E8_V: |
14670 | 0 | case RISCV::VLSEG2E16FF_V: |
14671 | 0 | case RISCV::VLSEG2E16_V: |
14672 | 0 | case RISCV::VLSEG2E32FF_V: |
14673 | 0 | case RISCV::VLSEG2E32_V: |
14674 | 0 | case RISCV::VLSEG2E64FF_V: |
14675 | 0 | case RISCV::VLSEG2E64_V: |
14676 | 0 | case RISCV::VLSEG3E8FF_V: |
14677 | 0 | case RISCV::VLSEG3E8_V: |
14678 | 0 | case RISCV::VLSEG3E16FF_V: |
14679 | 0 | case RISCV::VLSEG3E16_V: |
14680 | 0 | case RISCV::VLSEG3E32FF_V: |
14681 | 0 | case RISCV::VLSEG3E32_V: |
14682 | 0 | case RISCV::VLSEG3E64FF_V: |
14683 | 0 | case RISCV::VLSEG3E64_V: |
14684 | 0 | case RISCV::VLSEG4E8FF_V: |
14685 | 0 | case RISCV::VLSEG4E8_V: |
14686 | 0 | case RISCV::VLSEG4E16FF_V: |
14687 | 0 | case RISCV::VLSEG4E16_V: |
14688 | 0 | case RISCV::VLSEG4E32FF_V: |
14689 | 0 | case RISCV::VLSEG4E32_V: |
14690 | 0 | case RISCV::VLSEG4E64FF_V: |
14691 | 0 | case RISCV::VLSEG4E64_V: |
14692 | 0 | case RISCV::VLSEG5E8FF_V: |
14693 | 0 | case RISCV::VLSEG5E8_V: |
14694 | 0 | case RISCV::VLSEG5E16FF_V: |
14695 | 0 | case RISCV::VLSEG5E16_V: |
14696 | 0 | case RISCV::VLSEG5E32FF_V: |
14697 | 0 | case RISCV::VLSEG5E32_V: |
14698 | 0 | case RISCV::VLSEG5E64FF_V: |
14699 | 0 | case RISCV::VLSEG5E64_V: |
14700 | 0 | case RISCV::VLSEG6E8FF_V: |
14701 | 0 | case RISCV::VLSEG6E8_V: |
14702 | 0 | case RISCV::VLSEG6E16FF_V: |
14703 | 0 | case RISCV::VLSEG6E16_V: |
14704 | 0 | case RISCV::VLSEG6E32FF_V: |
14705 | 0 | case RISCV::VLSEG6E32_V: |
14706 | 0 | case RISCV::VLSEG6E64FF_V: |
14707 | 0 | case RISCV::VLSEG6E64_V: |
14708 | 0 | case RISCV::VLSEG7E8FF_V: |
14709 | 0 | case RISCV::VLSEG7E8_V: |
14710 | 0 | case RISCV::VLSEG7E16FF_V: |
14711 | 0 | case RISCV::VLSEG7E16_V: |
14712 | 0 | case RISCV::VLSEG7E32FF_V: |
14713 | 0 | case RISCV::VLSEG7E32_V: |
14714 | 0 | case RISCV::VLSEG7E64FF_V: |
14715 | 0 | case RISCV::VLSEG7E64_V: |
14716 | 0 | case RISCV::VLSEG8E8FF_V: |
14717 | 0 | case RISCV::VLSEG8E8_V: |
14718 | 0 | case RISCV::VLSEG8E16FF_V: |
14719 | 0 | case RISCV::VLSEG8E16_V: |
14720 | 0 | case RISCV::VLSEG8E32FF_V: |
14721 | 0 | case RISCV::VLSEG8E32_V: |
14722 | 0 | case RISCV::VLSEG8E64FF_V: |
14723 | 0 | case RISCV::VLSEG8E64_V: { |
14724 | | // op: rs1 |
14725 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14726 | 0 | op &= UINT64_C(31); |
14727 | 0 | op <<= 15; |
14728 | 0 | Value |= op; |
14729 | | // op: vd |
14730 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14731 | 0 | op &= UINT64_C(31); |
14732 | 0 | op <<= 7; |
14733 | 0 | Value |= op; |
14734 | | // op: vm |
14735 | 0 | op = getVMaskReg(MI, 2, Fixups, STI); |
14736 | 0 | op &= UINT64_C(1); |
14737 | 0 | op <<= 25; |
14738 | 0 | Value |= op; |
14739 | 0 | break; |
14740 | 0 | } |
14741 | 0 | case RISCV::VS1R_V: |
14742 | 0 | case RISCV::VS2R_V: |
14743 | 0 | case RISCV::VS4R_V: |
14744 | 0 | case RISCV::VS8R_V: |
14745 | 0 | case RISCV::VSM_V: { |
14746 | | // op: rs1 |
14747 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14748 | 0 | op &= UINT64_C(31); |
14749 | 0 | op <<= 15; |
14750 | 0 | Value |= op; |
14751 | | // op: vs3 |
14752 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14753 | 0 | op &= UINT64_C(31); |
14754 | 0 | op <<= 7; |
14755 | 0 | Value |= op; |
14756 | 0 | break; |
14757 | 0 | } |
14758 | 0 | case RISCV::VSE8_V: |
14759 | 0 | case RISCV::VSE16_V: |
14760 | 0 | case RISCV::VSE32_V: |
14761 | 0 | case RISCV::VSE64_V: |
14762 | 0 | case RISCV::VSSEG2E8_V: |
14763 | 0 | case RISCV::VSSEG2E16_V: |
14764 | 0 | case RISCV::VSSEG2E32_V: |
14765 | 0 | case RISCV::VSSEG2E64_V: |
14766 | 0 | case RISCV::VSSEG3E8_V: |
14767 | 0 | case RISCV::VSSEG3E16_V: |
14768 | 0 | case RISCV::VSSEG3E32_V: |
14769 | 0 | case RISCV::VSSEG3E64_V: |
14770 | 0 | case RISCV::VSSEG4E8_V: |
14771 | 0 | case RISCV::VSSEG4E16_V: |
14772 | 0 | case RISCV::VSSEG4E32_V: |
14773 | 0 | case RISCV::VSSEG4E64_V: |
14774 | 0 | case RISCV::VSSEG5E8_V: |
14775 | 0 | case RISCV::VSSEG5E16_V: |
14776 | 0 | case RISCV::VSSEG5E32_V: |
14777 | 0 | case RISCV::VSSEG5E64_V: |
14778 | 0 | case RISCV::VSSEG6E8_V: |
14779 | 0 | case RISCV::VSSEG6E16_V: |
14780 | 0 | case RISCV::VSSEG6E32_V: |
14781 | 0 | case RISCV::VSSEG6E64_V: |
14782 | 0 | case RISCV::VSSEG7E8_V: |
14783 | 0 | case RISCV::VSSEG7E16_V: |
14784 | 0 | case RISCV::VSSEG7E32_V: |
14785 | 0 | case RISCV::VSSEG7E64_V: |
14786 | 0 | case RISCV::VSSEG8E8_V: |
14787 | 0 | case RISCV::VSSEG8E16_V: |
14788 | 0 | case RISCV::VSSEG8E32_V: |
14789 | 0 | case RISCV::VSSEG8E64_V: { |
14790 | | // op: rs1 |
14791 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14792 | 0 | op &= UINT64_C(31); |
14793 | 0 | op <<= 15; |
14794 | 0 | Value |= op; |
14795 | | // op: vs3 |
14796 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14797 | 0 | op &= UINT64_C(31); |
14798 | 0 | op <<= 7; |
14799 | 0 | Value |= op; |
14800 | | // op: vm |
14801 | 0 | op = getVMaskReg(MI, 2, Fixups, STI); |
14802 | 0 | op &= UINT64_C(1); |
14803 | 0 | op <<= 25; |
14804 | 0 | Value |= op; |
14805 | 0 | break; |
14806 | 0 | } |
14807 | 0 | case RISCV::C_ADD: { |
14808 | | // op: rs1 |
14809 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14810 | 0 | op &= UINT64_C(31); |
14811 | 0 | op <<= 7; |
14812 | 0 | Value |= op; |
14813 | | // op: rs2 |
14814 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14815 | 0 | op &= UINT64_C(31); |
14816 | 0 | op <<= 2; |
14817 | 0 | Value |= op; |
14818 | 0 | break; |
14819 | 0 | } |
14820 | 0 | case RISCV::CV_LBU_ri_inc: |
14821 | 0 | case RISCV::CV_LB_ri_inc: |
14822 | 0 | case RISCV::CV_LHU_ri_inc: |
14823 | 0 | case RISCV::CV_LH_ri_inc: |
14824 | 0 | case RISCV::CV_LW_ri_inc: { |
14825 | | // op: rs1 |
14826 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14827 | 0 | op &= UINT64_C(31); |
14828 | 0 | op <<= 15; |
14829 | 0 | Value |= op; |
14830 | | // op: rd |
14831 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14832 | 0 | op &= UINT64_C(31); |
14833 | 0 | op <<= 7; |
14834 | 0 | Value |= op; |
14835 | | // op: imm12 |
14836 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
14837 | 0 | op &= UINT64_C(4095); |
14838 | 0 | op <<= 20; |
14839 | 0 | Value |= op; |
14840 | 0 | break; |
14841 | 0 | } |
14842 | 0 | case RISCV::CSRRC: |
14843 | 0 | case RISCV::CSRRCI: |
14844 | 0 | case RISCV::CSRRS: |
14845 | 0 | case RISCV::CSRRSI: |
14846 | 0 | case RISCV::CSRRW: |
14847 | 0 | case RISCV::CSRRWI: { |
14848 | | // op: rs1 |
14849 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14850 | 0 | op &= UINT64_C(31); |
14851 | 0 | op <<= 15; |
14852 | 0 | Value |= op; |
14853 | | // op: rd |
14854 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14855 | 0 | op &= UINT64_C(31); |
14856 | 0 | op <<= 7; |
14857 | 0 | Value |= op; |
14858 | | // op: imm12 |
14859 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14860 | 0 | op &= UINT64_C(4095); |
14861 | 0 | op <<= 20; |
14862 | 0 | Value |= op; |
14863 | 0 | break; |
14864 | 0 | } |
14865 | 0 | case RISCV::TH_LBIA: |
14866 | 0 | case RISCV::TH_LBIB: |
14867 | 0 | case RISCV::TH_LBUIA: |
14868 | 0 | case RISCV::TH_LBUIB: |
14869 | 0 | case RISCV::TH_LDIA: |
14870 | 0 | case RISCV::TH_LDIB: |
14871 | 0 | case RISCV::TH_LHIA: |
14872 | 0 | case RISCV::TH_LHIB: |
14873 | 0 | case RISCV::TH_LHUIA: |
14874 | 0 | case RISCV::TH_LHUIB: |
14875 | 0 | case RISCV::TH_LWIA: |
14876 | 0 | case RISCV::TH_LWIB: |
14877 | 0 | case RISCV::TH_LWUIA: |
14878 | 0 | case RISCV::TH_LWUIB: { |
14879 | | // op: rs1 |
14880 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14881 | 0 | op &= UINT64_C(31); |
14882 | 0 | op <<= 15; |
14883 | 0 | Value |= op; |
14884 | | // op: rd |
14885 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
14886 | 0 | op &= UINT64_C(31); |
14887 | 0 | op <<= 7; |
14888 | 0 | Value |= op; |
14889 | | // op: simm5 |
14890 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
14891 | 0 | op &= UINT64_C(31); |
14892 | 0 | op <<= 20; |
14893 | 0 | Value |= op; |
14894 | | // op: uimm2 |
14895 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
14896 | 0 | op &= UINT64_C(3); |
14897 | 0 | op <<= 25; |
14898 | 0 | Value |= op; |
14899 | 0 | break; |
14900 | 0 | } |
14901 | 0 | case RISCV::CV_SDOTSP_SCI_B: |
14902 | 0 | case RISCV::CV_SDOTSP_SCI_H: |
14903 | 0 | case RISCV::CV_SDOTUSP_SCI_B: |
14904 | 0 | case RISCV::CV_SDOTUSP_SCI_H: { |
14905 | | // op: rs1 |
14906 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14907 | 0 | op &= UINT64_C(31); |
14908 | 0 | op <<= 15; |
14909 | 0 | Value |= op; |
14910 | | // op: rd |
14911 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14912 | 0 | op &= UINT64_C(31); |
14913 | 0 | op <<= 7; |
14914 | 0 | Value |= op; |
14915 | | // op: imm6 |
14916 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
14917 | 0 | Value |= (op & UINT64_C(1)) << 25; |
14918 | 0 | Value |= (op & UINT64_C(62)) << 19; |
14919 | 0 | break; |
14920 | 0 | } |
14921 | 0 | case RISCV::CV_INSERT_B: |
14922 | 0 | case RISCV::CV_INSERT_H: |
14923 | 0 | case RISCV::CV_SDOTUP_SCI_B: |
14924 | 0 | case RISCV::CV_SDOTUP_SCI_H: { |
14925 | | // op: rs1 |
14926 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14927 | 0 | op &= UINT64_C(31); |
14928 | 0 | op <<= 15; |
14929 | 0 | Value |= op; |
14930 | | // op: rd |
14931 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14932 | 0 | op &= UINT64_C(31); |
14933 | 0 | op <<= 7; |
14934 | 0 | Value |= op; |
14935 | | // op: imm6 |
14936 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
14937 | 0 | Value |= (op & UINT64_C(1)) << 25; |
14938 | 0 | Value |= (op & UINT64_C(62)) << 19; |
14939 | 0 | break; |
14940 | 0 | } |
14941 | 0 | case RISCV::CV_INSERT: { |
14942 | | // op: rs1 |
14943 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14944 | 0 | op &= UINT64_C(31); |
14945 | 0 | op <<= 15; |
14946 | 0 | Value |= op; |
14947 | | // op: rd |
14948 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14949 | 0 | op &= UINT64_C(31); |
14950 | 0 | op <<= 7; |
14951 | 0 | Value |= op; |
14952 | | // op: is3 |
14953 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
14954 | 0 | op &= UINT64_C(31); |
14955 | 0 | op <<= 25; |
14956 | 0 | Value |= op; |
14957 | | // op: is2 |
14958 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
14959 | 0 | op &= UINT64_C(31); |
14960 | 0 | op <<= 20; |
14961 | 0 | Value |= op; |
14962 | 0 | break; |
14963 | 0 | } |
14964 | 0 | case RISCV::TH_SBIA: |
14965 | 0 | case RISCV::TH_SBIB: |
14966 | 0 | case RISCV::TH_SDIA: |
14967 | 0 | case RISCV::TH_SDIB: |
14968 | 0 | case RISCV::TH_SHIA: |
14969 | 0 | case RISCV::TH_SHIB: |
14970 | 0 | case RISCV::TH_SWIA: |
14971 | 0 | case RISCV::TH_SWIB: { |
14972 | | // op: rs1 |
14973 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14974 | 0 | op &= UINT64_C(31); |
14975 | 0 | op <<= 15; |
14976 | 0 | Value |= op; |
14977 | | // op: rd |
14978 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
14979 | 0 | op &= UINT64_C(31); |
14980 | 0 | op <<= 7; |
14981 | 0 | Value |= op; |
14982 | | // op: simm5 |
14983 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
14984 | 0 | op &= UINT64_C(31); |
14985 | 0 | op <<= 20; |
14986 | 0 | Value |= op; |
14987 | | // op: uimm2 |
14988 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
14989 | 0 | op &= UINT64_C(3); |
14990 | 0 | op <<= 25; |
14991 | 0 | Value |= op; |
14992 | 0 | break; |
14993 | 0 | } |
14994 | 0 | case RISCV::VFMV_S_F: |
14995 | 0 | case RISCV::VMV_S_X: { |
14996 | | // op: rs1 |
14997 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
14998 | 0 | op &= UINT64_C(31); |
14999 | 0 | op <<= 15; |
15000 | 0 | Value |= op; |
15001 | | // op: vd |
15002 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15003 | 0 | op &= UINT64_C(31); |
15004 | 0 | op <<= 7; |
15005 | 0 | Value |= op; |
15006 | 0 | break; |
15007 | 0 | } |
15008 | 0 | case RISCV::SSPUSH: { |
15009 | | // op: rs2 |
15010 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15011 | 0 | op &= UINT64_C(31); |
15012 | 0 | op <<= 20; |
15013 | 0 | Value |= op; |
15014 | 0 | break; |
15015 | 0 | } |
15016 | 0 | case RISCV::CV_SB_rr: |
15017 | 0 | case RISCV::CV_SH_rr: |
15018 | 0 | case RISCV::CV_SW_rr: { |
15019 | | // op: rs2 |
15020 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15021 | 0 | op &= UINT64_C(31); |
15022 | 0 | op <<= 20; |
15023 | 0 | Value |= op; |
15024 | | // op: cvrr |
15025 | 0 | op = getRegReg(MI, 1, Fixups, STI); |
15026 | 0 | Value |= (op & UINT64_C(992)) << 10; |
15027 | 0 | Value |= (op & UINT64_C(31)) << 7; |
15028 | 0 | break; |
15029 | 0 | } |
15030 | 0 | case RISCV::HSV_B: |
15031 | 0 | case RISCV::HSV_D: |
15032 | 0 | case RISCV::HSV_H: |
15033 | 0 | case RISCV::HSV_W: { |
15034 | | // op: rs2 |
15035 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15036 | 0 | op &= UINT64_C(31); |
15037 | 0 | op <<= 20; |
15038 | 0 | Value |= op; |
15039 | | // op: rs1 |
15040 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15041 | 0 | op &= UINT64_C(31); |
15042 | 0 | op <<= 15; |
15043 | 0 | Value |= op; |
15044 | 0 | break; |
15045 | 0 | } |
15046 | 0 | case RISCV::C_FSD: |
15047 | 0 | case RISCV::C_SD: { |
15048 | | // op: rs2 |
15049 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15050 | 0 | op &= UINT64_C(7); |
15051 | 0 | op <<= 2; |
15052 | 0 | Value |= op; |
15053 | | // op: rs1 |
15054 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15055 | 0 | op &= UINT64_C(7); |
15056 | 0 | op <<= 7; |
15057 | 0 | Value |= op; |
15058 | | // op: imm |
15059 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
15060 | 0 | Value |= (op & UINT64_C(56)) << 7; |
15061 | 0 | Value |= (op & UINT64_C(192)) >> 1; |
15062 | 0 | break; |
15063 | 0 | } |
15064 | 0 | case RISCV::C_FSW: |
15065 | 0 | case RISCV::C_SW: { |
15066 | | // op: rs2 |
15067 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15068 | 0 | op &= UINT64_C(7); |
15069 | 0 | op <<= 2; |
15070 | 0 | Value |= op; |
15071 | | // op: rs1 |
15072 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15073 | 0 | op &= UINT64_C(7); |
15074 | 0 | op <<= 7; |
15075 | 0 | Value |= op; |
15076 | | // op: imm |
15077 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
15078 | 0 | Value |= (op & UINT64_C(56)) << 7; |
15079 | 0 | Value |= (op & UINT64_C(4)) << 4; |
15080 | 0 | Value |= (op & UINT64_C(64)) >> 1; |
15081 | 0 | break; |
15082 | 0 | } |
15083 | 0 | case RISCV::C_SH: { |
15084 | | // op: rs2 |
15085 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15086 | 0 | op &= UINT64_C(7); |
15087 | 0 | op <<= 2; |
15088 | 0 | Value |= op; |
15089 | | // op: rs1 |
15090 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15091 | 0 | op &= UINT64_C(7); |
15092 | 0 | op <<= 7; |
15093 | 0 | Value |= op; |
15094 | | // op: imm |
15095 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
15096 | 0 | op &= UINT64_C(2); |
15097 | 0 | op <<= 4; |
15098 | 0 | Value |= op; |
15099 | 0 | break; |
15100 | 0 | } |
15101 | 0 | case RISCV::C_SB: { |
15102 | | // op: rs2 |
15103 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15104 | 0 | op &= UINT64_C(7); |
15105 | 0 | op <<= 2; |
15106 | 0 | Value |= op; |
15107 | | // op: rs1 |
15108 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15109 | 0 | op &= UINT64_C(7); |
15110 | 0 | op <<= 7; |
15111 | 0 | Value |= op; |
15112 | | // op: imm |
15113 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15114 | 0 | Value |= (op & UINT64_C(1)) << 6; |
15115 | 0 | Value |= (op & UINT64_C(2)) << 4; |
15116 | 0 | break; |
15117 | 0 | } |
15118 | 0 | case RISCV::VC_I: { |
15119 | | // op: rs2 |
15120 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15121 | 0 | op &= UINT64_C(31); |
15122 | 0 | op <<= 20; |
15123 | 0 | Value |= op; |
15124 | | // op: rs1 |
15125 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
15126 | 0 | op &= UINT64_C(31); |
15127 | 0 | op <<= 15; |
15128 | 0 | Value |= op; |
15129 | | // op: rd |
15130 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15131 | 0 | op &= UINT64_C(31); |
15132 | 0 | op <<= 7; |
15133 | 0 | Value |= op; |
15134 | | // op: funct6_lo2 |
15135 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15136 | 0 | op &= UINT64_C(3); |
15137 | 0 | op <<= 26; |
15138 | 0 | Value |= op; |
15139 | 0 | break; |
15140 | 0 | } |
15141 | 0 | case RISCV::HFENCE_GVMA: |
15142 | 0 | case RISCV::HFENCE_VVMA: |
15143 | 0 | case RISCV::HINVAL_GVMA: |
15144 | 0 | case RISCV::HINVAL_VVMA: |
15145 | 0 | case RISCV::SFENCE_VMA: |
15146 | 0 | case RISCV::SINVAL_VMA: |
15147 | 0 | case RISCV::TH_SFENCE_VMAS: { |
15148 | | // op: rs2 |
15149 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15150 | 0 | op &= UINT64_C(31); |
15151 | 0 | op <<= 20; |
15152 | 0 | Value |= op; |
15153 | | // op: rs1 |
15154 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15155 | 0 | op &= UINT64_C(31); |
15156 | 0 | op <<= 15; |
15157 | 0 | Value |= op; |
15158 | 0 | break; |
15159 | 0 | } |
15160 | 0 | case RISCV::TH_LDD: |
15161 | 0 | case RISCV::TH_LWD: |
15162 | 0 | case RISCV::TH_LWUD: |
15163 | 0 | case RISCV::TH_SDD: |
15164 | 0 | case RISCV::TH_SWD: { |
15165 | | // op: rs2 |
15166 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15167 | 0 | op &= UINT64_C(31); |
15168 | 0 | op <<= 20; |
15169 | 0 | Value |= op; |
15170 | | // op: rs1 |
15171 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15172 | 0 | op &= UINT64_C(31); |
15173 | 0 | op <<= 15; |
15174 | 0 | Value |= op; |
15175 | | // op: rd |
15176 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15177 | 0 | op &= UINT64_C(31); |
15178 | 0 | op <<= 7; |
15179 | 0 | Value |= op; |
15180 | | // op: uimm2 |
15181 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15182 | 0 | op &= UINT64_C(3); |
15183 | 0 | op <<= 25; |
15184 | 0 | Value |= op; |
15185 | 0 | break; |
15186 | 0 | } |
15187 | 0 | case RISCV::VC_X: { |
15188 | | // op: rs2 |
15189 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15190 | 0 | op &= UINT64_C(31); |
15191 | 0 | op <<= 20; |
15192 | 0 | Value |= op; |
15193 | | // op: rs1 |
15194 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15195 | 0 | op &= UINT64_C(31); |
15196 | 0 | op <<= 15; |
15197 | 0 | Value |= op; |
15198 | | // op: rd |
15199 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15200 | 0 | op &= UINT64_C(31); |
15201 | 0 | op <<= 7; |
15202 | 0 | Value |= op; |
15203 | | // op: funct6_lo2 |
15204 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15205 | 0 | op &= UINT64_C(3); |
15206 | 0 | op <<= 26; |
15207 | 0 | Value |= op; |
15208 | 0 | break; |
15209 | 0 | } |
15210 | 0 | case RISCV::C_MV_HINT: { |
15211 | | // op: rs2 |
15212 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15213 | 0 | op &= UINT64_C(31); |
15214 | 0 | op <<= 2; |
15215 | 0 | Value |= op; |
15216 | 0 | break; |
15217 | 0 | } |
15218 | 0 | case RISCV::CM_MVA01S: |
15219 | 0 | case RISCV::CM_MVSA01: { |
15220 | | // op: rs2 |
15221 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15222 | 0 | op &= UINT64_C(7); |
15223 | 0 | op <<= 2; |
15224 | 0 | Value |= op; |
15225 | | // op: rs1 |
15226 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15227 | 0 | op &= UINT64_C(7); |
15228 | 0 | op <<= 7; |
15229 | 0 | Value |= op; |
15230 | 0 | break; |
15231 | 0 | } |
15232 | 0 | case RISCV::VC_V_I: |
15233 | 0 | case RISCV::VC_V_IV: { |
15234 | | // op: rs2 |
15235 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15236 | 0 | op &= UINT64_C(31); |
15237 | 0 | op <<= 20; |
15238 | 0 | Value |= op; |
15239 | | // op: rs1 |
15240 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
15241 | 0 | op &= UINT64_C(31); |
15242 | 0 | op <<= 15; |
15243 | 0 | Value |= op; |
15244 | | // op: rd |
15245 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15246 | 0 | op &= UINT64_C(31); |
15247 | 0 | op <<= 7; |
15248 | 0 | Value |= op; |
15249 | | // op: funct6_lo2 |
15250 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15251 | 0 | op &= UINT64_C(3); |
15252 | 0 | op <<= 26; |
15253 | 0 | Value |= op; |
15254 | 0 | break; |
15255 | 0 | } |
15256 | 0 | case RISCV::VC_IV: |
15257 | 0 | case RISCV::VC_IVV: |
15258 | 0 | case RISCV::VC_IVW: { |
15259 | | // op: rs2 |
15260 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15261 | 0 | op &= UINT64_C(31); |
15262 | 0 | op <<= 20; |
15263 | 0 | Value |= op; |
15264 | | // op: rs1 |
15265 | 0 | op = getImmOpValue(MI, 3, Fixups, STI); |
15266 | 0 | op &= UINT64_C(31); |
15267 | 0 | op <<= 15; |
15268 | 0 | Value |= op; |
15269 | | // op: rd |
15270 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15271 | 0 | op &= UINT64_C(31); |
15272 | 0 | op <<= 7; |
15273 | 0 | Value |= op; |
15274 | | // op: funct6_lo2 |
15275 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15276 | 0 | op &= UINT64_C(3); |
15277 | 0 | op <<= 26; |
15278 | 0 | Value |= op; |
15279 | 0 | break; |
15280 | 0 | } |
15281 | 0 | case RISCV::FADD_D: |
15282 | 0 | case RISCV::FADD_D_IN32X: |
15283 | 0 | case RISCV::FADD_D_INX: |
15284 | 0 | case RISCV::FADD_H: |
15285 | 0 | case RISCV::FADD_H_INX: |
15286 | 0 | case RISCV::FADD_S: |
15287 | 0 | case RISCV::FADD_S_INX: |
15288 | 0 | case RISCV::FDIV_D: |
15289 | 0 | case RISCV::FDIV_D_IN32X: |
15290 | 0 | case RISCV::FDIV_D_INX: |
15291 | 0 | case RISCV::FDIV_H: |
15292 | 0 | case RISCV::FDIV_H_INX: |
15293 | 0 | case RISCV::FDIV_S: |
15294 | 0 | case RISCV::FDIV_S_INX: |
15295 | 0 | case RISCV::FMUL_D: |
15296 | 0 | case RISCV::FMUL_D_IN32X: |
15297 | 0 | case RISCV::FMUL_D_INX: |
15298 | 0 | case RISCV::FMUL_H: |
15299 | 0 | case RISCV::FMUL_H_INX: |
15300 | 0 | case RISCV::FMUL_S: |
15301 | 0 | case RISCV::FMUL_S_INX: |
15302 | 0 | case RISCV::FSUB_D: |
15303 | 0 | case RISCV::FSUB_D_IN32X: |
15304 | 0 | case RISCV::FSUB_D_INX: |
15305 | 0 | case RISCV::FSUB_H: |
15306 | 0 | case RISCV::FSUB_H_INX: |
15307 | 0 | case RISCV::FSUB_S: |
15308 | 0 | case RISCV::FSUB_S_INX: { |
15309 | | // op: rs2 |
15310 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15311 | 0 | op &= UINT64_C(31); |
15312 | 0 | op <<= 20; |
15313 | 0 | Value |= op; |
15314 | | // op: rs1 |
15315 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15316 | 0 | op &= UINT64_C(31); |
15317 | 0 | op <<= 15; |
15318 | 0 | Value |= op; |
15319 | | // op: frm |
15320 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15321 | 0 | op &= UINT64_C(7); |
15322 | 0 | op <<= 12; |
15323 | 0 | Value |= op; |
15324 | | // op: rd |
15325 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15326 | 0 | op &= UINT64_C(31); |
15327 | 0 | op <<= 7; |
15328 | 0 | Value |= op; |
15329 | 0 | break; |
15330 | 0 | } |
15331 | 0 | case RISCV::ADD: |
15332 | 0 | case RISCV::ADDW: |
15333 | 0 | case RISCV::ADD_UW: |
15334 | 0 | case RISCV::AES64DS: |
15335 | 0 | case RISCV::AES64DSM: |
15336 | 0 | case RISCV::AES64ES: |
15337 | 0 | case RISCV::AES64ESM: |
15338 | 0 | case RISCV::AES64KS2: |
15339 | 0 | case RISCV::AMOADD_D: |
15340 | 0 | case RISCV::AMOADD_D_AQ: |
15341 | 0 | case RISCV::AMOADD_D_AQ_RL: |
15342 | 0 | case RISCV::AMOADD_D_RL: |
15343 | 0 | case RISCV::AMOADD_W: |
15344 | 0 | case RISCV::AMOADD_W_AQ: |
15345 | 0 | case RISCV::AMOADD_W_AQ_RL: |
15346 | 0 | case RISCV::AMOADD_W_RL: |
15347 | 0 | case RISCV::AMOAND_D: |
15348 | 0 | case RISCV::AMOAND_D_AQ: |
15349 | 0 | case RISCV::AMOAND_D_AQ_RL: |
15350 | 0 | case RISCV::AMOAND_D_RL: |
15351 | 0 | case RISCV::AMOAND_W: |
15352 | 0 | case RISCV::AMOAND_W_AQ: |
15353 | 0 | case RISCV::AMOAND_W_AQ_RL: |
15354 | 0 | case RISCV::AMOAND_W_RL: |
15355 | 0 | case RISCV::AMOMAXU_D: |
15356 | 0 | case RISCV::AMOMAXU_D_AQ: |
15357 | 0 | case RISCV::AMOMAXU_D_AQ_RL: |
15358 | 0 | case RISCV::AMOMAXU_D_RL: |
15359 | 0 | case RISCV::AMOMAXU_W: |
15360 | 0 | case RISCV::AMOMAXU_W_AQ: |
15361 | 0 | case RISCV::AMOMAXU_W_AQ_RL: |
15362 | 0 | case RISCV::AMOMAXU_W_RL: |
15363 | 0 | case RISCV::AMOMAX_D: |
15364 | 0 | case RISCV::AMOMAX_D_AQ: |
15365 | 0 | case RISCV::AMOMAX_D_AQ_RL: |
15366 | 0 | case RISCV::AMOMAX_D_RL: |
15367 | 0 | case RISCV::AMOMAX_W: |
15368 | 0 | case RISCV::AMOMAX_W_AQ: |
15369 | 0 | case RISCV::AMOMAX_W_AQ_RL: |
15370 | 0 | case RISCV::AMOMAX_W_RL: |
15371 | 0 | case RISCV::AMOMINU_D: |
15372 | 0 | case RISCV::AMOMINU_D_AQ: |
15373 | 0 | case RISCV::AMOMINU_D_AQ_RL: |
15374 | 0 | case RISCV::AMOMINU_D_RL: |
15375 | 0 | case RISCV::AMOMINU_W: |
15376 | 0 | case RISCV::AMOMINU_W_AQ: |
15377 | 0 | case RISCV::AMOMINU_W_AQ_RL: |
15378 | 0 | case RISCV::AMOMINU_W_RL: |
15379 | 0 | case RISCV::AMOMIN_D: |
15380 | 0 | case RISCV::AMOMIN_D_AQ: |
15381 | 0 | case RISCV::AMOMIN_D_AQ_RL: |
15382 | 0 | case RISCV::AMOMIN_D_RL: |
15383 | 0 | case RISCV::AMOMIN_W: |
15384 | 0 | case RISCV::AMOMIN_W_AQ: |
15385 | 0 | case RISCV::AMOMIN_W_AQ_RL: |
15386 | 0 | case RISCV::AMOMIN_W_RL: |
15387 | 0 | case RISCV::AMOOR_D: |
15388 | 0 | case RISCV::AMOOR_D_AQ: |
15389 | 0 | case RISCV::AMOOR_D_AQ_RL: |
15390 | 0 | case RISCV::AMOOR_D_RL: |
15391 | 0 | case RISCV::AMOOR_W: |
15392 | 0 | case RISCV::AMOOR_W_AQ: |
15393 | 0 | case RISCV::AMOOR_W_AQ_RL: |
15394 | 0 | case RISCV::AMOOR_W_RL: |
15395 | 0 | case RISCV::AMOSWAP_D: |
15396 | 0 | case RISCV::AMOSWAP_D_AQ: |
15397 | 0 | case RISCV::AMOSWAP_D_AQ_RL: |
15398 | 0 | case RISCV::AMOSWAP_D_RL: |
15399 | 0 | case RISCV::AMOSWAP_W: |
15400 | 0 | case RISCV::AMOSWAP_W_AQ: |
15401 | 0 | case RISCV::AMOSWAP_W_AQ_RL: |
15402 | 0 | case RISCV::AMOSWAP_W_RL: |
15403 | 0 | case RISCV::AMOXOR_D: |
15404 | 0 | case RISCV::AMOXOR_D_AQ: |
15405 | 0 | case RISCV::AMOXOR_D_AQ_RL: |
15406 | 0 | case RISCV::AMOXOR_D_RL: |
15407 | 0 | case RISCV::AMOXOR_W: |
15408 | 0 | case RISCV::AMOXOR_W_AQ: |
15409 | 0 | case RISCV::AMOXOR_W_AQ_RL: |
15410 | 0 | case RISCV::AMOXOR_W_RL: |
15411 | 0 | case RISCV::AND: |
15412 | 0 | case RISCV::ANDN: |
15413 | 0 | case RISCV::BCLR: |
15414 | 0 | case RISCV::BEXT: |
15415 | 0 | case RISCV::BINV: |
15416 | 0 | case RISCV::BSET: |
15417 | 0 | case RISCV::CLMUL: |
15418 | 0 | case RISCV::CLMULH: |
15419 | 0 | case RISCV::CLMULR: |
15420 | 0 | case RISCV::CV_ADD_B: |
15421 | 0 | case RISCV::CV_ADD_DIV2: |
15422 | 0 | case RISCV::CV_ADD_DIV4: |
15423 | 0 | case RISCV::CV_ADD_DIV8: |
15424 | 0 | case RISCV::CV_ADD_H: |
15425 | 0 | case RISCV::CV_ADD_SC_B: |
15426 | 0 | case RISCV::CV_ADD_SC_H: |
15427 | 0 | case RISCV::CV_AND_B: |
15428 | 0 | case RISCV::CV_AND_H: |
15429 | 0 | case RISCV::CV_AND_SC_B: |
15430 | 0 | case RISCV::CV_AND_SC_H: |
15431 | 0 | case RISCV::CV_AVGU_B: |
15432 | 0 | case RISCV::CV_AVGU_H: |
15433 | 0 | case RISCV::CV_AVGU_SC_B: |
15434 | 0 | case RISCV::CV_AVGU_SC_H: |
15435 | 0 | case RISCV::CV_AVG_B: |
15436 | 0 | case RISCV::CV_AVG_H: |
15437 | 0 | case RISCV::CV_AVG_SC_B: |
15438 | 0 | case RISCV::CV_AVG_SC_H: |
15439 | 0 | case RISCV::CV_BCLRR: |
15440 | 0 | case RISCV::CV_BSETR: |
15441 | 0 | case RISCV::CV_CLIPR: |
15442 | 0 | case RISCV::CV_CLIPUR: |
15443 | 0 | case RISCV::CV_CMPEQ_B: |
15444 | 0 | case RISCV::CV_CMPEQ_H: |
15445 | 0 | case RISCV::CV_CMPEQ_SC_B: |
15446 | 0 | case RISCV::CV_CMPEQ_SC_H: |
15447 | 0 | case RISCV::CV_CMPGEU_B: |
15448 | 0 | case RISCV::CV_CMPGEU_H: |
15449 | 0 | case RISCV::CV_CMPGEU_SC_B: |
15450 | 0 | case RISCV::CV_CMPGEU_SC_H: |
15451 | 0 | case RISCV::CV_CMPGE_B: |
15452 | 0 | case RISCV::CV_CMPGE_H: |
15453 | 0 | case RISCV::CV_CMPGE_SC_B: |
15454 | 0 | case RISCV::CV_CMPGE_SC_H: |
15455 | 0 | case RISCV::CV_CMPGTU_B: |
15456 | 0 | case RISCV::CV_CMPGTU_H: |
15457 | 0 | case RISCV::CV_CMPGTU_SC_B: |
15458 | 0 | case RISCV::CV_CMPGTU_SC_H: |
15459 | 0 | case RISCV::CV_CMPGT_B: |
15460 | 0 | case RISCV::CV_CMPGT_H: |
15461 | 0 | case RISCV::CV_CMPGT_SC_B: |
15462 | 0 | case RISCV::CV_CMPGT_SC_H: |
15463 | 0 | case RISCV::CV_CMPLEU_B: |
15464 | 0 | case RISCV::CV_CMPLEU_H: |
15465 | 0 | case RISCV::CV_CMPLEU_SC_B: |
15466 | 0 | case RISCV::CV_CMPLEU_SC_H: |
15467 | 0 | case RISCV::CV_CMPLE_B: |
15468 | 0 | case RISCV::CV_CMPLE_H: |
15469 | 0 | case RISCV::CV_CMPLE_SC_B: |
15470 | 0 | case RISCV::CV_CMPLE_SC_H: |
15471 | 0 | case RISCV::CV_CMPLTU_B: |
15472 | 0 | case RISCV::CV_CMPLTU_H: |
15473 | 0 | case RISCV::CV_CMPLTU_SC_B: |
15474 | 0 | case RISCV::CV_CMPLTU_SC_H: |
15475 | 0 | case RISCV::CV_CMPLT_B: |
15476 | 0 | case RISCV::CV_CMPLT_H: |
15477 | 0 | case RISCV::CV_CMPLT_SC_B: |
15478 | 0 | case RISCV::CV_CMPLT_SC_H: |
15479 | 0 | case RISCV::CV_CMPNE_B: |
15480 | 0 | case RISCV::CV_CMPNE_H: |
15481 | 0 | case RISCV::CV_CMPNE_SC_B: |
15482 | 0 | case RISCV::CV_CMPNE_SC_H: |
15483 | 0 | case RISCV::CV_DOTSP_B: |
15484 | 0 | case RISCV::CV_DOTSP_H: |
15485 | 0 | case RISCV::CV_DOTSP_SC_B: |
15486 | 0 | case RISCV::CV_DOTSP_SC_H: |
15487 | 0 | case RISCV::CV_DOTUP_B: |
15488 | 0 | case RISCV::CV_DOTUP_H: |
15489 | 0 | case RISCV::CV_DOTUP_SC_B: |
15490 | 0 | case RISCV::CV_DOTUP_SC_H: |
15491 | 0 | case RISCV::CV_DOTUSP_B: |
15492 | 0 | case RISCV::CV_DOTUSP_H: |
15493 | 0 | case RISCV::CV_DOTUSP_SC_B: |
15494 | 0 | case RISCV::CV_DOTUSP_SC_H: |
15495 | 0 | case RISCV::CV_EXTRACTR: |
15496 | 0 | case RISCV::CV_EXTRACTUR: |
15497 | 0 | case RISCV::CV_MAX: |
15498 | 0 | case RISCV::CV_MAXU: |
15499 | 0 | case RISCV::CV_MAXU_B: |
15500 | 0 | case RISCV::CV_MAXU_H: |
15501 | 0 | case RISCV::CV_MAXU_SC_B: |
15502 | 0 | case RISCV::CV_MAXU_SC_H: |
15503 | 0 | case RISCV::CV_MAX_B: |
15504 | 0 | case RISCV::CV_MAX_H: |
15505 | 0 | case RISCV::CV_MAX_SC_B: |
15506 | 0 | case RISCV::CV_MAX_SC_H: |
15507 | 0 | case RISCV::CV_MIN: |
15508 | 0 | case RISCV::CV_MINU: |
15509 | 0 | case RISCV::CV_MINU_B: |
15510 | 0 | case RISCV::CV_MINU_H: |
15511 | 0 | case RISCV::CV_MINU_SC_B: |
15512 | 0 | case RISCV::CV_MINU_SC_H: |
15513 | 0 | case RISCV::CV_MIN_B: |
15514 | 0 | case RISCV::CV_MIN_H: |
15515 | 0 | case RISCV::CV_MIN_SC_B: |
15516 | 0 | case RISCV::CV_MIN_SC_H: |
15517 | 0 | case RISCV::CV_OR_B: |
15518 | 0 | case RISCV::CV_OR_H: |
15519 | 0 | case RISCV::CV_OR_SC_B: |
15520 | 0 | case RISCV::CV_OR_SC_H: |
15521 | 0 | case RISCV::CV_PACK: |
15522 | 0 | case RISCV::CV_PACK_H: |
15523 | 0 | case RISCV::CV_ROR: |
15524 | 0 | case RISCV::CV_SHUFFLE_B: |
15525 | 0 | case RISCV::CV_SHUFFLE_H: |
15526 | 0 | case RISCV::CV_SLET: |
15527 | 0 | case RISCV::CV_SLETU: |
15528 | 0 | case RISCV::CV_SLL_B: |
15529 | 0 | case RISCV::CV_SLL_H: |
15530 | 0 | case RISCV::CV_SLL_SC_B: |
15531 | 0 | case RISCV::CV_SLL_SC_H: |
15532 | 0 | case RISCV::CV_SRA_B: |
15533 | 0 | case RISCV::CV_SRA_H: |
15534 | 0 | case RISCV::CV_SRA_SC_B: |
15535 | 0 | case RISCV::CV_SRA_SC_H: |
15536 | 0 | case RISCV::CV_SRL_B: |
15537 | 0 | case RISCV::CV_SRL_H: |
15538 | 0 | case RISCV::CV_SRL_SC_B: |
15539 | 0 | case RISCV::CV_SRL_SC_H: |
15540 | 0 | case RISCV::CV_SUBROTMJ: |
15541 | 0 | case RISCV::CV_SUBROTMJ_DIV2: |
15542 | 0 | case RISCV::CV_SUBROTMJ_DIV4: |
15543 | 0 | case RISCV::CV_SUBROTMJ_DIV8: |
15544 | 0 | case RISCV::CV_SUB_B: |
15545 | 0 | case RISCV::CV_SUB_DIV2: |
15546 | 0 | case RISCV::CV_SUB_DIV4: |
15547 | 0 | case RISCV::CV_SUB_DIV8: |
15548 | 0 | case RISCV::CV_SUB_H: |
15549 | 0 | case RISCV::CV_SUB_SC_B: |
15550 | 0 | case RISCV::CV_SUB_SC_H: |
15551 | 0 | case RISCV::CV_XOR_B: |
15552 | 0 | case RISCV::CV_XOR_H: |
15553 | 0 | case RISCV::CV_XOR_SC_B: |
15554 | 0 | case RISCV::CV_XOR_SC_H: |
15555 | 0 | case RISCV::CZERO_EQZ: |
15556 | 0 | case RISCV::CZERO_NEZ: |
15557 | 0 | case RISCV::DIV: |
15558 | 0 | case RISCV::DIVU: |
15559 | 0 | case RISCV::DIVUW: |
15560 | 0 | case RISCV::DIVW: |
15561 | 0 | case RISCV::FEQ_D: |
15562 | 0 | case RISCV::FEQ_D_IN32X: |
15563 | 0 | case RISCV::FEQ_D_INX: |
15564 | 0 | case RISCV::FEQ_H: |
15565 | 0 | case RISCV::FEQ_H_INX: |
15566 | 0 | case RISCV::FEQ_S: |
15567 | 0 | case RISCV::FEQ_S_INX: |
15568 | 0 | case RISCV::FLEQ_D: |
15569 | 0 | case RISCV::FLEQ_H: |
15570 | 0 | case RISCV::FLEQ_S: |
15571 | 0 | case RISCV::FLE_D: |
15572 | 0 | case RISCV::FLE_D_IN32X: |
15573 | 0 | case RISCV::FLE_D_INX: |
15574 | 0 | case RISCV::FLE_H: |
15575 | 0 | case RISCV::FLE_H_INX: |
15576 | 0 | case RISCV::FLE_S: |
15577 | 0 | case RISCV::FLE_S_INX: |
15578 | 0 | case RISCV::FLTQ_D: |
15579 | 0 | case RISCV::FLTQ_H: |
15580 | 0 | case RISCV::FLTQ_S: |
15581 | 0 | case RISCV::FLT_D: |
15582 | 0 | case RISCV::FLT_D_IN32X: |
15583 | 0 | case RISCV::FLT_D_INX: |
15584 | 0 | case RISCV::FLT_H: |
15585 | 0 | case RISCV::FLT_H_INX: |
15586 | 0 | case RISCV::FLT_S: |
15587 | 0 | case RISCV::FLT_S_INX: |
15588 | 0 | case RISCV::FMAXM_D: |
15589 | 0 | case RISCV::FMAXM_H: |
15590 | 0 | case RISCV::FMAXM_S: |
15591 | 0 | case RISCV::FMAX_D: |
15592 | 0 | case RISCV::FMAX_D_IN32X: |
15593 | 0 | case RISCV::FMAX_D_INX: |
15594 | 0 | case RISCV::FMAX_H: |
15595 | 0 | case RISCV::FMAX_H_INX: |
15596 | 0 | case RISCV::FMAX_S: |
15597 | 0 | case RISCV::FMAX_S_INX: |
15598 | 0 | case RISCV::FMINM_D: |
15599 | 0 | case RISCV::FMINM_H: |
15600 | 0 | case RISCV::FMINM_S: |
15601 | 0 | case RISCV::FMIN_D: |
15602 | 0 | case RISCV::FMIN_D_IN32X: |
15603 | 0 | case RISCV::FMIN_D_INX: |
15604 | 0 | case RISCV::FMIN_H: |
15605 | 0 | case RISCV::FMIN_H_INX: |
15606 | 0 | case RISCV::FMIN_S: |
15607 | 0 | case RISCV::FMIN_S_INX: |
15608 | 0 | case RISCV::FMVP_D_X: |
15609 | 0 | case RISCV::FSGNJN_D: |
15610 | 0 | case RISCV::FSGNJN_D_IN32X: |
15611 | 0 | case RISCV::FSGNJN_D_INX: |
15612 | 0 | case RISCV::FSGNJN_H: |
15613 | 0 | case RISCV::FSGNJN_H_INX: |
15614 | 0 | case RISCV::FSGNJN_S: |
15615 | 0 | case RISCV::FSGNJN_S_INX: |
15616 | 0 | case RISCV::FSGNJX_D: |
15617 | 0 | case RISCV::FSGNJX_D_IN32X: |
15618 | 0 | case RISCV::FSGNJX_D_INX: |
15619 | 0 | case RISCV::FSGNJX_H: |
15620 | 0 | case RISCV::FSGNJX_H_INX: |
15621 | 0 | case RISCV::FSGNJX_S: |
15622 | 0 | case RISCV::FSGNJX_S_INX: |
15623 | 0 | case RISCV::FSGNJ_D: |
15624 | 0 | case RISCV::FSGNJ_D_IN32X: |
15625 | 0 | case RISCV::FSGNJ_D_INX: |
15626 | 0 | case RISCV::FSGNJ_H: |
15627 | 0 | case RISCV::FSGNJ_H_INX: |
15628 | 0 | case RISCV::FSGNJ_S: |
15629 | 0 | case RISCV::FSGNJ_S_INX: |
15630 | 0 | case RISCV::MAX: |
15631 | 0 | case RISCV::MAXU: |
15632 | 0 | case RISCV::MIN: |
15633 | 0 | case RISCV::MINU: |
15634 | 0 | case RISCV::MOPRR0: |
15635 | 0 | case RISCV::MOPRR1: |
15636 | 0 | case RISCV::MOPRR2: |
15637 | 0 | case RISCV::MOPRR3: |
15638 | 0 | case RISCV::MOPRR4: |
15639 | 0 | case RISCV::MOPRR5: |
15640 | 0 | case RISCV::MOPRR6: |
15641 | 0 | case RISCV::MOPRR7: |
15642 | 0 | case RISCV::MUL: |
15643 | 0 | case RISCV::MULH: |
15644 | 0 | case RISCV::MULHSU: |
15645 | 0 | case RISCV::MULHU: |
15646 | 0 | case RISCV::MULW: |
15647 | 0 | case RISCV::OR: |
15648 | 0 | case RISCV::ORN: |
15649 | 0 | case RISCV::PACK: |
15650 | 0 | case RISCV::PACKH: |
15651 | 0 | case RISCV::PACKW: |
15652 | 0 | case RISCV::REM: |
15653 | 0 | case RISCV::REMU: |
15654 | 0 | case RISCV::REMUW: |
15655 | 0 | case RISCV::REMW: |
15656 | 0 | case RISCV::ROL: |
15657 | 0 | case RISCV::ROLW: |
15658 | 0 | case RISCV::ROR: |
15659 | 0 | case RISCV::RORW: |
15660 | 0 | case RISCV::SC_D: |
15661 | 0 | case RISCV::SC_D_AQ: |
15662 | 0 | case RISCV::SC_D_AQ_RL: |
15663 | 0 | case RISCV::SC_D_RL: |
15664 | 0 | case RISCV::SC_W: |
15665 | 0 | case RISCV::SC_W_AQ: |
15666 | 0 | case RISCV::SC_W_AQ_RL: |
15667 | 0 | case RISCV::SC_W_RL: |
15668 | 0 | case RISCV::SH1ADD: |
15669 | 0 | case RISCV::SH1ADD_UW: |
15670 | 0 | case RISCV::SH2ADD: |
15671 | 0 | case RISCV::SH2ADD_UW: |
15672 | 0 | case RISCV::SH3ADD: |
15673 | 0 | case RISCV::SH3ADD_UW: |
15674 | 0 | case RISCV::SHA512SIG0H: |
15675 | 0 | case RISCV::SHA512SIG0L: |
15676 | 0 | case RISCV::SHA512SIG1H: |
15677 | 0 | case RISCV::SHA512SIG1L: |
15678 | 0 | case RISCV::SHA512SUM0R: |
15679 | 0 | case RISCV::SHA512SUM1R: |
15680 | 0 | case RISCV::SLL: |
15681 | 0 | case RISCV::SLLW: |
15682 | 0 | case RISCV::SLT: |
15683 | 0 | case RISCV::SLTU: |
15684 | 0 | case RISCV::SRA: |
15685 | 0 | case RISCV::SRAW: |
15686 | 0 | case RISCV::SRL: |
15687 | 0 | case RISCV::SRLW: |
15688 | 0 | case RISCV::SSAMOSWAP_D: |
15689 | 0 | case RISCV::SSAMOSWAP_D_AQ: |
15690 | 0 | case RISCV::SSAMOSWAP_D_AQ_RL: |
15691 | 0 | case RISCV::SSAMOSWAP_D_RL: |
15692 | 0 | case RISCV::SSAMOSWAP_W: |
15693 | 0 | case RISCV::SSAMOSWAP_W_AQ: |
15694 | 0 | case RISCV::SSAMOSWAP_W_AQ_RL: |
15695 | 0 | case RISCV::SSAMOSWAP_W_RL: |
15696 | 0 | case RISCV::SUB: |
15697 | 0 | case RISCV::SUBW: |
15698 | 0 | case RISCV::VFWMACC_4x4x4: |
15699 | 0 | case RISCV::VQMACCSU_2x8x2: |
15700 | 0 | case RISCV::VQMACCSU_4x8x4: |
15701 | 0 | case RISCV::VQMACCUS_2x8x2: |
15702 | 0 | case RISCV::VQMACCUS_4x8x4: |
15703 | 0 | case RISCV::VQMACCU_2x8x2: |
15704 | 0 | case RISCV::VQMACCU_4x8x4: |
15705 | 0 | case RISCV::VQMACC_2x8x2: |
15706 | 0 | case RISCV::VQMACC_4x8x4: |
15707 | 0 | case RISCV::VSETVL: |
15708 | 0 | case RISCV::VT_MASKC: |
15709 | 0 | case RISCV::VT_MASKCN: |
15710 | 0 | case RISCV::XNOR: |
15711 | 0 | case RISCV::XOR: |
15712 | 0 | case RISCV::XPERM4: |
15713 | 0 | case RISCV::XPERM8: { |
15714 | | // op: rs2 |
15715 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15716 | 0 | op &= UINT64_C(31); |
15717 | 0 | op <<= 20; |
15718 | 0 | Value |= op; |
15719 | | // op: rs1 |
15720 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15721 | 0 | op &= UINT64_C(31); |
15722 | 0 | op <<= 15; |
15723 | 0 | Value |= op; |
15724 | | // op: rd |
15725 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15726 | 0 | op &= UINT64_C(31); |
15727 | 0 | op <<= 7; |
15728 | 0 | Value |= op; |
15729 | 0 | break; |
15730 | 0 | } |
15731 | 0 | case RISCV::AES32DSI: |
15732 | 0 | case RISCV::AES32DSMI: |
15733 | 0 | case RISCV::AES32ESI: |
15734 | 0 | case RISCV::AES32ESMI: |
15735 | 0 | case RISCV::SM4ED: |
15736 | 0 | case RISCV::SM4KS: { |
15737 | | // op: rs2 |
15738 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15739 | 0 | op &= UINT64_C(31); |
15740 | 0 | op <<= 20; |
15741 | 0 | Value |= op; |
15742 | | // op: rs1 |
15743 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15744 | 0 | op &= UINT64_C(31); |
15745 | 0 | op <<= 15; |
15746 | 0 | Value |= op; |
15747 | | // op: rd |
15748 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15749 | 0 | op &= UINT64_C(31); |
15750 | 0 | op <<= 7; |
15751 | 0 | Value |= op; |
15752 | | // op: bs |
15753 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15754 | 0 | op &= UINT64_C(3); |
15755 | 0 | op <<= 30; |
15756 | 0 | Value |= op; |
15757 | 0 | break; |
15758 | 0 | } |
15759 | 0 | case RISCV::CV_ADDN: |
15760 | 0 | case RISCV::CV_ADDRN: |
15761 | 0 | case RISCV::CV_ADDUN: |
15762 | 0 | case RISCV::CV_ADDURN: |
15763 | 0 | case RISCV::CV_MULHHSN: |
15764 | 0 | case RISCV::CV_MULHHSRN: |
15765 | 0 | case RISCV::CV_MULHHUN: |
15766 | 0 | case RISCV::CV_MULHHURN: |
15767 | 0 | case RISCV::CV_MULSN: |
15768 | 0 | case RISCV::CV_MULSRN: |
15769 | 0 | case RISCV::CV_MULUN: |
15770 | 0 | case RISCV::CV_MULURN: |
15771 | 0 | case RISCV::CV_SUBN: |
15772 | 0 | case RISCV::CV_SUBRN: |
15773 | 0 | case RISCV::CV_SUBUN: |
15774 | 0 | case RISCV::CV_SUBURN: { |
15775 | | // op: rs2 |
15776 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15777 | 0 | op &= UINT64_C(31); |
15778 | 0 | op <<= 20; |
15779 | 0 | Value |= op; |
15780 | | // op: rs1 |
15781 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15782 | 0 | op &= UINT64_C(31); |
15783 | 0 | op <<= 15; |
15784 | 0 | Value |= op; |
15785 | | // op: rd |
15786 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15787 | 0 | op &= UINT64_C(31); |
15788 | 0 | op <<= 7; |
15789 | 0 | Value |= op; |
15790 | | // op: imm5 |
15791 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15792 | 0 | op &= UINT64_C(31); |
15793 | 0 | op <<= 25; |
15794 | 0 | Value |= op; |
15795 | 0 | break; |
15796 | 0 | } |
15797 | 0 | case RISCV::TH_ADDSL: |
15798 | 0 | case RISCV::TH_FLRD: |
15799 | 0 | case RISCV::TH_FLRW: |
15800 | 0 | case RISCV::TH_FLURD: |
15801 | 0 | case RISCV::TH_FLURW: |
15802 | 0 | case RISCV::TH_FSRD: |
15803 | 0 | case RISCV::TH_FSRW: |
15804 | 0 | case RISCV::TH_FSURD: |
15805 | 0 | case RISCV::TH_FSURW: |
15806 | 0 | case RISCV::TH_LRB: |
15807 | 0 | case RISCV::TH_LRBU: |
15808 | 0 | case RISCV::TH_LRD: |
15809 | 0 | case RISCV::TH_LRH: |
15810 | 0 | case RISCV::TH_LRHU: |
15811 | 0 | case RISCV::TH_LRW: |
15812 | 0 | case RISCV::TH_LRWU: |
15813 | 0 | case RISCV::TH_LURB: |
15814 | 0 | case RISCV::TH_LURBU: |
15815 | 0 | case RISCV::TH_LURD: |
15816 | 0 | case RISCV::TH_LURH: |
15817 | 0 | case RISCV::TH_LURHU: |
15818 | 0 | case RISCV::TH_LURW: |
15819 | 0 | case RISCV::TH_LURWU: |
15820 | 0 | case RISCV::TH_SRB: |
15821 | 0 | case RISCV::TH_SRD: |
15822 | 0 | case RISCV::TH_SRH: |
15823 | 0 | case RISCV::TH_SRW: |
15824 | 0 | case RISCV::TH_SURB: |
15825 | 0 | case RISCV::TH_SURD: |
15826 | 0 | case RISCV::TH_SURH: |
15827 | 0 | case RISCV::TH_SURW: { |
15828 | | // op: rs2 |
15829 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15830 | 0 | op &= UINT64_C(31); |
15831 | 0 | op <<= 20; |
15832 | 0 | Value |= op; |
15833 | | // op: rs1 |
15834 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15835 | 0 | op &= UINT64_C(31); |
15836 | 0 | op <<= 15; |
15837 | 0 | Value |= op; |
15838 | | // op: rd |
15839 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15840 | 0 | op &= UINT64_C(31); |
15841 | 0 | op <<= 7; |
15842 | 0 | Value |= op; |
15843 | | // op: uimm2 |
15844 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15845 | 0 | op &= UINT64_C(3); |
15846 | 0 | op <<= 25; |
15847 | 0 | Value |= op; |
15848 | 0 | break; |
15849 | 0 | } |
15850 | 0 | case RISCV::VLSE8_V: |
15851 | 0 | case RISCV::VLSE16_V: |
15852 | 0 | case RISCV::VLSE32_V: |
15853 | 0 | case RISCV::VLSE64_V: |
15854 | 0 | case RISCV::VLSSEG2E8_V: |
15855 | 0 | case RISCV::VLSSEG2E16_V: |
15856 | 0 | case RISCV::VLSSEG2E32_V: |
15857 | 0 | case RISCV::VLSSEG2E64_V: |
15858 | 0 | case RISCV::VLSSEG3E8_V: |
15859 | 0 | case RISCV::VLSSEG3E16_V: |
15860 | 0 | case RISCV::VLSSEG3E32_V: |
15861 | 0 | case RISCV::VLSSEG3E64_V: |
15862 | 0 | case RISCV::VLSSEG4E8_V: |
15863 | 0 | case RISCV::VLSSEG4E16_V: |
15864 | 0 | case RISCV::VLSSEG4E32_V: |
15865 | 0 | case RISCV::VLSSEG4E64_V: |
15866 | 0 | case RISCV::VLSSEG5E8_V: |
15867 | 0 | case RISCV::VLSSEG5E16_V: |
15868 | 0 | case RISCV::VLSSEG5E32_V: |
15869 | 0 | case RISCV::VLSSEG5E64_V: |
15870 | 0 | case RISCV::VLSSEG6E8_V: |
15871 | 0 | case RISCV::VLSSEG6E16_V: |
15872 | 0 | case RISCV::VLSSEG6E32_V: |
15873 | 0 | case RISCV::VLSSEG6E64_V: |
15874 | 0 | case RISCV::VLSSEG7E8_V: |
15875 | 0 | case RISCV::VLSSEG7E16_V: |
15876 | 0 | case RISCV::VLSSEG7E32_V: |
15877 | 0 | case RISCV::VLSSEG7E64_V: |
15878 | 0 | case RISCV::VLSSEG8E8_V: |
15879 | 0 | case RISCV::VLSSEG8E16_V: |
15880 | 0 | case RISCV::VLSSEG8E32_V: |
15881 | 0 | case RISCV::VLSSEG8E64_V: { |
15882 | | // op: rs2 |
15883 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15884 | 0 | op &= UINT64_C(31); |
15885 | 0 | op <<= 20; |
15886 | 0 | Value |= op; |
15887 | | // op: rs1 |
15888 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15889 | 0 | op &= UINT64_C(31); |
15890 | 0 | op <<= 15; |
15891 | 0 | Value |= op; |
15892 | | // op: vd |
15893 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15894 | 0 | op &= UINT64_C(31); |
15895 | 0 | op <<= 7; |
15896 | 0 | Value |= op; |
15897 | | // op: vm |
15898 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
15899 | 0 | op &= UINT64_C(1); |
15900 | 0 | op <<= 25; |
15901 | 0 | Value |= op; |
15902 | 0 | break; |
15903 | 0 | } |
15904 | 0 | case RISCV::VSSE8_V: |
15905 | 0 | case RISCV::VSSE16_V: |
15906 | 0 | case RISCV::VSSE32_V: |
15907 | 0 | case RISCV::VSSE64_V: |
15908 | 0 | case RISCV::VSSSEG2E8_V: |
15909 | 0 | case RISCV::VSSSEG2E16_V: |
15910 | 0 | case RISCV::VSSSEG2E32_V: |
15911 | 0 | case RISCV::VSSSEG2E64_V: |
15912 | 0 | case RISCV::VSSSEG3E8_V: |
15913 | 0 | case RISCV::VSSSEG3E16_V: |
15914 | 0 | case RISCV::VSSSEG3E32_V: |
15915 | 0 | case RISCV::VSSSEG3E64_V: |
15916 | 0 | case RISCV::VSSSEG4E8_V: |
15917 | 0 | case RISCV::VSSSEG4E16_V: |
15918 | 0 | case RISCV::VSSSEG4E32_V: |
15919 | 0 | case RISCV::VSSSEG4E64_V: |
15920 | 0 | case RISCV::VSSSEG5E8_V: |
15921 | 0 | case RISCV::VSSSEG5E16_V: |
15922 | 0 | case RISCV::VSSSEG5E32_V: |
15923 | 0 | case RISCV::VSSSEG5E64_V: |
15924 | 0 | case RISCV::VSSSEG6E8_V: |
15925 | 0 | case RISCV::VSSSEG6E16_V: |
15926 | 0 | case RISCV::VSSSEG6E32_V: |
15927 | 0 | case RISCV::VSSSEG6E64_V: |
15928 | 0 | case RISCV::VSSSEG7E8_V: |
15929 | 0 | case RISCV::VSSSEG7E16_V: |
15930 | 0 | case RISCV::VSSSEG7E32_V: |
15931 | 0 | case RISCV::VSSSEG7E64_V: |
15932 | 0 | case RISCV::VSSSEG8E8_V: |
15933 | 0 | case RISCV::VSSSEG8E16_V: |
15934 | 0 | case RISCV::VSSSEG8E32_V: |
15935 | 0 | case RISCV::VSSSEG8E64_V: { |
15936 | | // op: rs2 |
15937 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15938 | 0 | op &= UINT64_C(31); |
15939 | 0 | op <<= 20; |
15940 | 0 | Value |= op; |
15941 | | // op: rs1 |
15942 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15943 | 0 | op &= UINT64_C(31); |
15944 | 0 | op <<= 15; |
15945 | 0 | Value |= op; |
15946 | | // op: vs3 |
15947 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15948 | 0 | op &= UINT64_C(31); |
15949 | 0 | op <<= 7; |
15950 | 0 | Value |= op; |
15951 | | // op: vm |
15952 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
15953 | 0 | op &= UINT64_C(1); |
15954 | 0 | op <<= 25; |
15955 | 0 | Value |= op; |
15956 | 0 | break; |
15957 | 0 | } |
15958 | 0 | case RISCV::VC_V_FV: { |
15959 | | // op: rs2 |
15960 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15961 | 0 | op &= UINT64_C(31); |
15962 | 0 | op <<= 20; |
15963 | 0 | Value |= op; |
15964 | | // op: rs1 |
15965 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15966 | 0 | op &= UINT64_C(31); |
15967 | 0 | op <<= 15; |
15968 | 0 | Value |= op; |
15969 | | // op: rd |
15970 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15971 | 0 | op &= UINT64_C(31); |
15972 | 0 | op <<= 7; |
15973 | 0 | Value |= op; |
15974 | | // op: funct6_lo1 |
15975 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
15976 | 0 | op &= UINT64_C(1); |
15977 | 0 | op <<= 26; |
15978 | 0 | Value |= op; |
15979 | 0 | break; |
15980 | 0 | } |
15981 | 0 | case RISCV::VC_V_VV: |
15982 | 0 | case RISCV::VC_V_X: |
15983 | 0 | case RISCV::VC_V_XV: { |
15984 | | // op: rs2 |
15985 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
15986 | 0 | op &= UINT64_C(31); |
15987 | 0 | op <<= 20; |
15988 | 0 | Value |= op; |
15989 | | // op: rs1 |
15990 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
15991 | 0 | op &= UINT64_C(31); |
15992 | 0 | op <<= 15; |
15993 | 0 | Value |= op; |
15994 | | // op: rd |
15995 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
15996 | 0 | op &= UINT64_C(31); |
15997 | 0 | op <<= 7; |
15998 | 0 | Value |= op; |
15999 | | // op: funct6_lo2 |
16000 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16001 | 0 | op &= UINT64_C(3); |
16002 | 0 | op <<= 26; |
16003 | 0 | Value |= op; |
16004 | 0 | break; |
16005 | 0 | } |
16006 | 0 | case RISCV::VC_FV: |
16007 | 0 | case RISCV::VC_FVV: |
16008 | 0 | case RISCV::VC_FVW: { |
16009 | | // op: rs2 |
16010 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16011 | 0 | op &= UINT64_C(31); |
16012 | 0 | op <<= 20; |
16013 | 0 | Value |= op; |
16014 | | // op: rs1 |
16015 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16016 | 0 | op &= UINT64_C(31); |
16017 | 0 | op <<= 15; |
16018 | 0 | Value |= op; |
16019 | | // op: rd |
16020 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16021 | 0 | op &= UINT64_C(31); |
16022 | 0 | op <<= 7; |
16023 | 0 | Value |= op; |
16024 | | // op: funct6_lo1 |
16025 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16026 | 0 | op &= UINT64_C(1); |
16027 | 0 | op <<= 26; |
16028 | 0 | Value |= op; |
16029 | 0 | break; |
16030 | 0 | } |
16031 | 0 | case RISCV::VC_VV: |
16032 | 0 | case RISCV::VC_VVV: |
16033 | 0 | case RISCV::VC_VVW: |
16034 | 0 | case RISCV::VC_XV: |
16035 | 0 | case RISCV::VC_XVV: |
16036 | 0 | case RISCV::VC_XVW: { |
16037 | | // op: rs2 |
16038 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16039 | 0 | op &= UINT64_C(31); |
16040 | 0 | op <<= 20; |
16041 | 0 | Value |= op; |
16042 | | // op: rs1 |
16043 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16044 | 0 | op &= UINT64_C(31); |
16045 | 0 | op <<= 15; |
16046 | 0 | Value |= op; |
16047 | | // op: rd |
16048 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16049 | 0 | op &= UINT64_C(31); |
16050 | 0 | op <<= 7; |
16051 | 0 | Value |= op; |
16052 | | // op: funct6_lo2 |
16053 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16054 | 0 | op &= UINT64_C(3); |
16055 | 0 | op <<= 26; |
16056 | 0 | Value |= op; |
16057 | 0 | break; |
16058 | 0 | } |
16059 | 0 | case RISCV::C_ADD_HINT: { |
16060 | | // op: rs2 |
16061 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16062 | 0 | op &= UINT64_C(31); |
16063 | 0 | op <<= 2; |
16064 | 0 | Value |= op; |
16065 | 0 | break; |
16066 | 0 | } |
16067 | 0 | case RISCV::C_ADDW: |
16068 | 0 | case RISCV::C_AND: |
16069 | 0 | case RISCV::C_MUL: |
16070 | 0 | case RISCV::C_OR: |
16071 | 0 | case RISCV::C_SUB: |
16072 | 0 | case RISCV::C_SUBW: |
16073 | 0 | case RISCV::C_XOR: { |
16074 | | // op: rs2 |
16075 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16076 | 0 | op &= UINT64_C(7); |
16077 | 0 | op <<= 2; |
16078 | 0 | Value |= op; |
16079 | | // op: rd |
16080 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16081 | 0 | op &= UINT64_C(7); |
16082 | 0 | op <<= 7; |
16083 | 0 | Value |= op; |
16084 | 0 | break; |
16085 | 0 | } |
16086 | 0 | case RISCV::VC_V_IVV: |
16087 | 0 | case RISCV::VC_V_IVW: { |
16088 | | // op: rs2 |
16089 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16090 | 0 | op &= UINT64_C(31); |
16091 | 0 | op <<= 20; |
16092 | 0 | Value |= op; |
16093 | | // op: rs1 |
16094 | 0 | op = getImmOpValue(MI, 4, Fixups, STI); |
16095 | 0 | op &= UINT64_C(31); |
16096 | 0 | op <<= 15; |
16097 | 0 | Value |= op; |
16098 | | // op: rd |
16099 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16100 | 0 | op &= UINT64_C(31); |
16101 | 0 | op <<= 7; |
16102 | 0 | Value |= op; |
16103 | | // op: funct6_lo2 |
16104 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16105 | 0 | op &= UINT64_C(3); |
16106 | 0 | op <<= 26; |
16107 | 0 | Value |= op; |
16108 | 0 | break; |
16109 | 0 | } |
16110 | 0 | case RISCV::CV_LBU_rr_inc: |
16111 | 0 | case RISCV::CV_LB_rr_inc: |
16112 | 0 | case RISCV::CV_LHU_rr_inc: |
16113 | 0 | case RISCV::CV_LH_rr_inc: |
16114 | 0 | case RISCV::CV_LW_rr_inc: { |
16115 | | // op: rs2 |
16116 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16117 | 0 | op &= UINT64_C(31); |
16118 | 0 | op <<= 20; |
16119 | 0 | Value |= op; |
16120 | | // op: rs1 |
16121 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16122 | 0 | op &= UINT64_C(31); |
16123 | 0 | op <<= 15; |
16124 | 0 | Value |= op; |
16125 | | // op: rd |
16126 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16127 | 0 | op &= UINT64_C(31); |
16128 | 0 | op <<= 7; |
16129 | 0 | Value |= op; |
16130 | 0 | break; |
16131 | 0 | } |
16132 | 0 | case RISCV::AMOCAS_D_RV32: |
16133 | 0 | case RISCV::AMOCAS_D_RV32_AQ: |
16134 | 0 | case RISCV::AMOCAS_D_RV32_AQ_RL: |
16135 | 0 | case RISCV::AMOCAS_D_RV32_RL: |
16136 | 0 | case RISCV::AMOCAS_D_RV64: |
16137 | 0 | case RISCV::AMOCAS_D_RV64_AQ: |
16138 | 0 | case RISCV::AMOCAS_D_RV64_AQ_RL: |
16139 | 0 | case RISCV::AMOCAS_D_RV64_RL: |
16140 | 0 | case RISCV::AMOCAS_Q: |
16141 | 0 | case RISCV::AMOCAS_Q_AQ: |
16142 | 0 | case RISCV::AMOCAS_Q_AQ_RL: |
16143 | 0 | case RISCV::AMOCAS_Q_RL: |
16144 | 0 | case RISCV::AMOCAS_W: |
16145 | 0 | case RISCV::AMOCAS_W_AQ: |
16146 | 0 | case RISCV::AMOCAS_W_AQ_RL: |
16147 | 0 | case RISCV::AMOCAS_W_RL: |
16148 | 0 | case RISCV::CV_ADDNR: |
16149 | 0 | case RISCV::CV_ADDRNR: |
16150 | 0 | case RISCV::CV_ADDUNR: |
16151 | 0 | case RISCV::CV_ADDURNR: |
16152 | 0 | case RISCV::CV_CPLXMUL_I: |
16153 | 0 | case RISCV::CV_CPLXMUL_I_DIV2: |
16154 | 0 | case RISCV::CV_CPLXMUL_I_DIV4: |
16155 | 0 | case RISCV::CV_CPLXMUL_I_DIV8: |
16156 | 0 | case RISCV::CV_CPLXMUL_R: |
16157 | 0 | case RISCV::CV_CPLXMUL_R_DIV2: |
16158 | 0 | case RISCV::CV_CPLXMUL_R_DIV4: |
16159 | 0 | case RISCV::CV_CPLXMUL_R_DIV8: |
16160 | 0 | case RISCV::CV_INSERTR: |
16161 | 0 | case RISCV::CV_MAC: |
16162 | 0 | case RISCV::CV_MSU: |
16163 | 0 | case RISCV::CV_PACKHI_B: |
16164 | 0 | case RISCV::CV_PACKLO_B: |
16165 | 0 | case RISCV::CV_SDOTSP_B: |
16166 | 0 | case RISCV::CV_SDOTSP_H: |
16167 | 0 | case RISCV::CV_SDOTSP_SC_B: |
16168 | 0 | case RISCV::CV_SDOTSP_SC_H: |
16169 | 0 | case RISCV::CV_SDOTUP_B: |
16170 | 0 | case RISCV::CV_SDOTUP_H: |
16171 | 0 | case RISCV::CV_SDOTUP_SC_B: |
16172 | 0 | case RISCV::CV_SDOTUP_SC_H: |
16173 | 0 | case RISCV::CV_SDOTUSP_B: |
16174 | 0 | case RISCV::CV_SDOTUSP_H: |
16175 | 0 | case RISCV::CV_SDOTUSP_SC_B: |
16176 | 0 | case RISCV::CV_SDOTUSP_SC_H: |
16177 | 0 | case RISCV::CV_SHUFFLE2_B: |
16178 | 0 | case RISCV::CV_SHUFFLE2_H: |
16179 | 0 | case RISCV::CV_SUBNR: |
16180 | 0 | case RISCV::CV_SUBRNR: |
16181 | 0 | case RISCV::CV_SUBUNR: |
16182 | 0 | case RISCV::CV_SUBURNR: |
16183 | 0 | case RISCV::TH_MULA: |
16184 | 0 | case RISCV::TH_MULAH: |
16185 | 0 | case RISCV::TH_MULAW: |
16186 | 0 | case RISCV::TH_MULS: |
16187 | 0 | case RISCV::TH_MULSH: |
16188 | 0 | case RISCV::TH_MULSW: |
16189 | 0 | case RISCV::TH_MVEQZ: |
16190 | 0 | case RISCV::TH_MVNEZ: { |
16191 | | // op: rs2 |
16192 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16193 | 0 | op &= UINT64_C(31); |
16194 | 0 | op <<= 20; |
16195 | 0 | Value |= op; |
16196 | | // op: rs1 |
16197 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16198 | 0 | op &= UINT64_C(31); |
16199 | 0 | op <<= 15; |
16200 | 0 | Value |= op; |
16201 | | // op: rd |
16202 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16203 | 0 | op &= UINT64_C(31); |
16204 | 0 | op <<= 7; |
16205 | 0 | Value |= op; |
16206 | 0 | break; |
16207 | 0 | } |
16208 | 0 | case RISCV::CV_MACHHSN: |
16209 | 0 | case RISCV::CV_MACHHSRN: |
16210 | 0 | case RISCV::CV_MACHHUN: |
16211 | 0 | case RISCV::CV_MACHHURN: |
16212 | 0 | case RISCV::CV_MACSN: |
16213 | 0 | case RISCV::CV_MACSRN: |
16214 | 0 | case RISCV::CV_MACUN: |
16215 | 0 | case RISCV::CV_MACURN: { |
16216 | | // op: rs2 |
16217 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16218 | 0 | op &= UINT64_C(31); |
16219 | 0 | op <<= 20; |
16220 | 0 | Value |= op; |
16221 | | // op: rs1 |
16222 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16223 | 0 | op &= UINT64_C(31); |
16224 | 0 | op <<= 15; |
16225 | 0 | Value |= op; |
16226 | | // op: rd |
16227 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16228 | 0 | op &= UINT64_C(31); |
16229 | 0 | op <<= 7; |
16230 | 0 | Value |= op; |
16231 | | // op: imm5 |
16232 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
16233 | 0 | op &= UINT64_C(31); |
16234 | 0 | op <<= 25; |
16235 | 0 | Value |= op; |
16236 | 0 | break; |
16237 | 0 | } |
16238 | 0 | case RISCV::VC_V_FVV: |
16239 | 0 | case RISCV::VC_V_FVW: { |
16240 | | // op: rs2 |
16241 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16242 | 0 | op &= UINT64_C(31); |
16243 | 0 | op <<= 20; |
16244 | 0 | Value |= op; |
16245 | | // op: rs1 |
16246 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
16247 | 0 | op &= UINT64_C(31); |
16248 | 0 | op <<= 15; |
16249 | 0 | Value |= op; |
16250 | | // op: rd |
16251 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16252 | 0 | op &= UINT64_C(31); |
16253 | 0 | op <<= 7; |
16254 | 0 | Value |= op; |
16255 | | // op: funct6_lo1 |
16256 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16257 | 0 | op &= UINT64_C(1); |
16258 | 0 | op <<= 26; |
16259 | 0 | Value |= op; |
16260 | 0 | break; |
16261 | 0 | } |
16262 | 0 | case RISCV::VC_V_VVV: |
16263 | 0 | case RISCV::VC_V_VVW: |
16264 | 0 | case RISCV::VC_V_XVV: |
16265 | 0 | case RISCV::VC_V_XVW: { |
16266 | | // op: rs2 |
16267 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16268 | 0 | op &= UINT64_C(31); |
16269 | 0 | op <<= 20; |
16270 | 0 | Value |= op; |
16271 | | // op: rs1 |
16272 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
16273 | 0 | op &= UINT64_C(31); |
16274 | 0 | op <<= 15; |
16275 | 0 | Value |= op; |
16276 | | // op: rd |
16277 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16278 | 0 | op &= UINT64_C(31); |
16279 | 0 | op <<= 7; |
16280 | 0 | Value |= op; |
16281 | | // op: funct6_lo2 |
16282 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16283 | 0 | op &= UINT64_C(3); |
16284 | 0 | op <<= 26; |
16285 | 0 | Value |= op; |
16286 | 0 | break; |
16287 | 0 | } |
16288 | 0 | case RISCV::FMADD_D: |
16289 | 0 | case RISCV::FMADD_D_IN32X: |
16290 | 0 | case RISCV::FMADD_D_INX: |
16291 | 0 | case RISCV::FMADD_H: |
16292 | 0 | case RISCV::FMADD_H_INX: |
16293 | 0 | case RISCV::FMADD_S: |
16294 | 0 | case RISCV::FMADD_S_INX: |
16295 | 0 | case RISCV::FMSUB_D: |
16296 | 0 | case RISCV::FMSUB_D_IN32X: |
16297 | 0 | case RISCV::FMSUB_D_INX: |
16298 | 0 | case RISCV::FMSUB_H: |
16299 | 0 | case RISCV::FMSUB_H_INX: |
16300 | 0 | case RISCV::FMSUB_S: |
16301 | 0 | case RISCV::FMSUB_S_INX: |
16302 | 0 | case RISCV::FNMADD_D: |
16303 | 0 | case RISCV::FNMADD_D_IN32X: |
16304 | 0 | case RISCV::FNMADD_D_INX: |
16305 | 0 | case RISCV::FNMADD_H: |
16306 | 0 | case RISCV::FNMADD_H_INX: |
16307 | 0 | case RISCV::FNMADD_S: |
16308 | 0 | case RISCV::FNMADD_S_INX: |
16309 | 0 | case RISCV::FNMSUB_D: |
16310 | 0 | case RISCV::FNMSUB_D_IN32X: |
16311 | 0 | case RISCV::FNMSUB_D_INX: |
16312 | 0 | case RISCV::FNMSUB_H: |
16313 | 0 | case RISCV::FNMSUB_H_INX: |
16314 | 0 | case RISCV::FNMSUB_S: |
16315 | 0 | case RISCV::FNMSUB_S_INX: { |
16316 | | // op: rs3 |
16317 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16318 | 0 | op &= UINT64_C(31); |
16319 | 0 | op <<= 27; |
16320 | 0 | Value |= op; |
16321 | | // op: rs2 |
16322 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16323 | 0 | op &= UINT64_C(31); |
16324 | 0 | op <<= 20; |
16325 | 0 | Value |= op; |
16326 | | // op: rs1 |
16327 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16328 | 0 | op &= UINT64_C(31); |
16329 | 0 | op <<= 15; |
16330 | 0 | Value |= op; |
16331 | | // op: frm |
16332 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
16333 | 0 | op &= UINT64_C(7); |
16334 | 0 | op <<= 12; |
16335 | 0 | Value |= op; |
16336 | | // op: rd |
16337 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16338 | 0 | op &= UINT64_C(31); |
16339 | 0 | op <<= 7; |
16340 | 0 | Value |= op; |
16341 | 0 | break; |
16342 | 0 | } |
16343 | 0 | case RISCV::CV_SB_rr_inc: |
16344 | 0 | case RISCV::CV_SH_rr_inc: |
16345 | 0 | case RISCV::CV_SW_rr_inc: { |
16346 | | // op: rs3 |
16347 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
16348 | 0 | op &= UINT64_C(31); |
16349 | 0 | op <<= 7; |
16350 | 0 | Value |= op; |
16351 | | // op: rs2 |
16352 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16353 | 0 | op &= UINT64_C(31); |
16354 | 0 | op <<= 20; |
16355 | 0 | Value |= op; |
16356 | | // op: rs1 |
16357 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16358 | 0 | op &= UINT64_C(31); |
16359 | 0 | op <<= 15; |
16360 | 0 | Value |= op; |
16361 | 0 | break; |
16362 | 0 | } |
16363 | 0 | case RISCV::VSETIVLI: { |
16364 | | // op: uimm |
16365 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16366 | 0 | op &= UINT64_C(31); |
16367 | 0 | op <<= 15; |
16368 | 0 | Value |= op; |
16369 | | // op: rd |
16370 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16371 | 0 | op &= UINT64_C(31); |
16372 | 0 | op <<= 7; |
16373 | 0 | Value |= op; |
16374 | | // op: vtypei |
16375 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16376 | 0 | op &= UINT64_C(1023); |
16377 | 0 | op <<= 20; |
16378 | 0 | Value |= op; |
16379 | 0 | break; |
16380 | 0 | } |
16381 | 0 | case RISCV::VID_V: { |
16382 | | // op: vd |
16383 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16384 | 0 | op &= UINT64_C(31); |
16385 | 0 | op <<= 7; |
16386 | 0 | Value |= op; |
16387 | | // op: vm |
16388 | 0 | op = getVMaskReg(MI, 1, Fixups, STI); |
16389 | 0 | op &= UINT64_C(1); |
16390 | 0 | op <<= 25; |
16391 | 0 | Value |= op; |
16392 | 0 | break; |
16393 | 0 | } |
16394 | 0 | case RISCV::VMV_V_V: { |
16395 | | // op: vs1 |
16396 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16397 | 0 | op &= UINT64_C(31); |
16398 | 0 | op <<= 15; |
16399 | 0 | Value |= op; |
16400 | | // op: vd |
16401 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16402 | 0 | op &= UINT64_C(31); |
16403 | 0 | op <<= 7; |
16404 | 0 | Value |= op; |
16405 | 0 | break; |
16406 | 0 | } |
16407 | 0 | case RISCV::VADC_VIM: |
16408 | 0 | case RISCV::VMADC_VI: |
16409 | 0 | case RISCV::VMADC_VIM: |
16410 | 0 | case RISCV::VMERGE_VIM: { |
16411 | | // op: vs2 |
16412 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16413 | 0 | op &= UINT64_C(31); |
16414 | 0 | op <<= 20; |
16415 | 0 | Value |= op; |
16416 | | // op: imm |
16417 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
16418 | 0 | op &= UINT64_C(31); |
16419 | 0 | op <<= 15; |
16420 | 0 | Value |= op; |
16421 | | // op: vd |
16422 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16423 | 0 | op &= UINT64_C(31); |
16424 | 0 | op <<= 7; |
16425 | 0 | Value |= op; |
16426 | 0 | break; |
16427 | 0 | } |
16428 | 0 | case RISCV::VADD_VI: |
16429 | 0 | case RISCV::VAND_VI: |
16430 | 0 | case RISCV::VMSEQ_VI: |
16431 | 0 | case RISCV::VMSGTU_VI: |
16432 | 0 | case RISCV::VMSGT_VI: |
16433 | 0 | case RISCV::VMSLEU_VI: |
16434 | 0 | case RISCV::VMSLE_VI: |
16435 | 0 | case RISCV::VMSNE_VI: |
16436 | 0 | case RISCV::VOR_VI: |
16437 | 0 | case RISCV::VRSUB_VI: |
16438 | 0 | case RISCV::VSADDU_VI: |
16439 | 0 | case RISCV::VSADD_VI: |
16440 | 0 | case RISCV::VXOR_VI: { |
16441 | | // op: vs2 |
16442 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16443 | 0 | op &= UINT64_C(31); |
16444 | 0 | op <<= 20; |
16445 | 0 | Value |= op; |
16446 | | // op: imm |
16447 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
16448 | 0 | op &= UINT64_C(31); |
16449 | 0 | op <<= 15; |
16450 | 0 | Value |= op; |
16451 | | // op: vd |
16452 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16453 | 0 | op &= UINT64_C(31); |
16454 | 0 | op <<= 7; |
16455 | 0 | Value |= op; |
16456 | | // op: vm |
16457 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
16458 | 0 | op &= UINT64_C(1); |
16459 | 0 | op <<= 25; |
16460 | 0 | Value |= op; |
16461 | 0 | break; |
16462 | 0 | } |
16463 | 0 | case RISCV::VROR_VI: { |
16464 | | // op: vs2 |
16465 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16466 | 0 | op &= UINT64_C(31); |
16467 | 0 | op <<= 20; |
16468 | 0 | Value |= op; |
16469 | | // op: imm |
16470 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16471 | 0 | Value |= (op & UINT64_C(32)) << 21; |
16472 | 0 | Value |= (op & UINT64_C(31)) << 15; |
16473 | | // op: vd |
16474 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16475 | 0 | op &= UINT64_C(31); |
16476 | 0 | op <<= 7; |
16477 | 0 | Value |= op; |
16478 | | // op: vm |
16479 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
16480 | 0 | op &= UINT64_C(1); |
16481 | 0 | op <<= 25; |
16482 | 0 | Value |= op; |
16483 | 0 | break; |
16484 | 0 | } |
16485 | 0 | case RISCV::VAESKF1_VI: |
16486 | 0 | case RISCV::VAESKF2_VI: |
16487 | 0 | case RISCV::VSM3C_VI: |
16488 | 0 | case RISCV::VSM4K_VI: { |
16489 | | // op: vs2 |
16490 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16491 | 0 | op &= UINT64_C(31); |
16492 | 0 | op <<= 20; |
16493 | 0 | Value |= op; |
16494 | | // op: imm |
16495 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16496 | 0 | op &= UINT64_C(31); |
16497 | 0 | op <<= 15; |
16498 | 0 | Value |= op; |
16499 | | // op: vd |
16500 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16501 | 0 | op &= UINT64_C(31); |
16502 | 0 | op <<= 7; |
16503 | 0 | Value |= op; |
16504 | 0 | break; |
16505 | 0 | } |
16506 | 0 | case RISCV::VNCLIPU_WI: |
16507 | 0 | case RISCV::VNCLIP_WI: |
16508 | 0 | case RISCV::VNSRA_WI: |
16509 | 0 | case RISCV::VNSRL_WI: |
16510 | 0 | case RISCV::VRGATHER_VI: |
16511 | 0 | case RISCV::VSLIDEDOWN_VI: |
16512 | 0 | case RISCV::VSLIDEUP_VI: |
16513 | 0 | case RISCV::VSLL_VI: |
16514 | 0 | case RISCV::VSRA_VI: |
16515 | 0 | case RISCV::VSRL_VI: |
16516 | 0 | case RISCV::VSSRA_VI: |
16517 | 0 | case RISCV::VSSRL_VI: |
16518 | 0 | case RISCV::VWSLL_VI: { |
16519 | | // op: vs2 |
16520 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16521 | 0 | op &= UINT64_C(31); |
16522 | 0 | op <<= 20; |
16523 | 0 | Value |= op; |
16524 | | // op: imm |
16525 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16526 | 0 | op &= UINT64_C(31); |
16527 | 0 | op <<= 15; |
16528 | 0 | Value |= op; |
16529 | | // op: vd |
16530 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16531 | 0 | op &= UINT64_C(31); |
16532 | 0 | op <<= 7; |
16533 | 0 | Value |= op; |
16534 | | // op: vm |
16535 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
16536 | 0 | op &= UINT64_C(1); |
16537 | 0 | op <<= 25; |
16538 | 0 | Value |= op; |
16539 | 0 | break; |
16540 | 0 | } |
16541 | 0 | case RISCV::VADC_VXM: |
16542 | 0 | case RISCV::VFMERGE_VFM: |
16543 | 0 | case RISCV::VMADC_VX: |
16544 | 0 | case RISCV::VMADC_VXM: |
16545 | 0 | case RISCV::VMERGE_VXM: |
16546 | 0 | case RISCV::VMSBC_VX: |
16547 | 0 | case RISCV::VMSBC_VXM: |
16548 | 0 | case RISCV::VSBC_VXM: { |
16549 | | // op: vs2 |
16550 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16551 | 0 | op &= UINT64_C(31); |
16552 | 0 | op <<= 20; |
16553 | 0 | Value |= op; |
16554 | | // op: rs1 |
16555 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16556 | 0 | op &= UINT64_C(31); |
16557 | 0 | op <<= 15; |
16558 | 0 | Value |= op; |
16559 | | // op: vd |
16560 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16561 | 0 | op &= UINT64_C(31); |
16562 | 0 | op <<= 7; |
16563 | 0 | Value |= op; |
16564 | 0 | break; |
16565 | 0 | } |
16566 | 0 | case RISCV::VAADDU_VX: |
16567 | 0 | case RISCV::VAADD_VX: |
16568 | 0 | case RISCV::VADD_VX: |
16569 | 0 | case RISCV::VANDN_VX: |
16570 | 0 | case RISCV::VAND_VX: |
16571 | 0 | case RISCV::VASUBU_VX: |
16572 | 0 | case RISCV::VASUB_VX: |
16573 | 0 | case RISCV::VCLMULH_VX: |
16574 | 0 | case RISCV::VCLMUL_VX: |
16575 | 0 | case RISCV::VDIVU_VX: |
16576 | 0 | case RISCV::VDIV_VX: |
16577 | 0 | case RISCV::VFADD_VF: |
16578 | 0 | case RISCV::VFDIV_VF: |
16579 | 0 | case RISCV::VFMAX_VF: |
16580 | 0 | case RISCV::VFMIN_VF: |
16581 | 0 | case RISCV::VFMUL_VF: |
16582 | 0 | case RISCV::VFNRCLIP_XU_F_QF: |
16583 | 0 | case RISCV::VFNRCLIP_X_F_QF: |
16584 | 0 | case RISCV::VFRDIV_VF: |
16585 | 0 | case RISCV::VFRSUB_VF: |
16586 | 0 | case RISCV::VFSGNJN_VF: |
16587 | 0 | case RISCV::VFSGNJX_VF: |
16588 | 0 | case RISCV::VFSGNJ_VF: |
16589 | 0 | case RISCV::VFSLIDE1DOWN_VF: |
16590 | 0 | case RISCV::VFSLIDE1UP_VF: |
16591 | 0 | case RISCV::VFSUB_VF: |
16592 | 0 | case RISCV::VFWADD_VF: |
16593 | 0 | case RISCV::VFWADD_WF: |
16594 | 0 | case RISCV::VFWMUL_VF: |
16595 | 0 | case RISCV::VFWSUB_VF: |
16596 | 0 | case RISCV::VFWSUB_WF: |
16597 | 0 | case RISCV::VMAXU_VX: |
16598 | 0 | case RISCV::VMAX_VX: |
16599 | 0 | case RISCV::VMFEQ_VF: |
16600 | 0 | case RISCV::VMFGE_VF: |
16601 | 0 | case RISCV::VMFGT_VF: |
16602 | 0 | case RISCV::VMFLE_VF: |
16603 | 0 | case RISCV::VMFLT_VF: |
16604 | 0 | case RISCV::VMFNE_VF: |
16605 | 0 | case RISCV::VMINU_VX: |
16606 | 0 | case RISCV::VMIN_VX: |
16607 | 0 | case RISCV::VMSEQ_VX: |
16608 | 0 | case RISCV::VMSGTU_VX: |
16609 | 0 | case RISCV::VMSGT_VX: |
16610 | 0 | case RISCV::VMSLEU_VX: |
16611 | 0 | case RISCV::VMSLE_VX: |
16612 | 0 | case RISCV::VMSLTU_VX: |
16613 | 0 | case RISCV::VMSLT_VX: |
16614 | 0 | case RISCV::VMSNE_VX: |
16615 | 0 | case RISCV::VMULHSU_VX: |
16616 | 0 | case RISCV::VMULHU_VX: |
16617 | 0 | case RISCV::VMULH_VX: |
16618 | 0 | case RISCV::VMUL_VX: |
16619 | 0 | case RISCV::VNCLIPU_WX: |
16620 | 0 | case RISCV::VNCLIP_WX: |
16621 | 0 | case RISCV::VNSRA_WX: |
16622 | 0 | case RISCV::VNSRL_WX: |
16623 | 0 | case RISCV::VOR_VX: |
16624 | 0 | case RISCV::VREMU_VX: |
16625 | 0 | case RISCV::VREM_VX: |
16626 | 0 | case RISCV::VRGATHER_VX: |
16627 | 0 | case RISCV::VROL_VX: |
16628 | 0 | case RISCV::VROR_VX: |
16629 | 0 | case RISCV::VRSUB_VX: |
16630 | 0 | case RISCV::VSADDU_VX: |
16631 | 0 | case RISCV::VSADD_VX: |
16632 | 0 | case RISCV::VSLIDE1DOWN_VX: |
16633 | 0 | case RISCV::VSLIDE1UP_VX: |
16634 | 0 | case RISCV::VSLIDEDOWN_VX: |
16635 | 0 | case RISCV::VSLIDEUP_VX: |
16636 | 0 | case RISCV::VSLL_VX: |
16637 | 0 | case RISCV::VSMUL_VX: |
16638 | 0 | case RISCV::VSRA_VX: |
16639 | 0 | case RISCV::VSRL_VX: |
16640 | 0 | case RISCV::VSSRA_VX: |
16641 | 0 | case RISCV::VSSRL_VX: |
16642 | 0 | case RISCV::VSSUBU_VX: |
16643 | 0 | case RISCV::VSSUB_VX: |
16644 | 0 | case RISCV::VSUB_VX: |
16645 | 0 | case RISCV::VWADDU_VX: |
16646 | 0 | case RISCV::VWADDU_WX: |
16647 | 0 | case RISCV::VWADD_VX: |
16648 | 0 | case RISCV::VWADD_WX: |
16649 | 0 | case RISCV::VWMULSU_VX: |
16650 | 0 | case RISCV::VWMULU_VX: |
16651 | 0 | case RISCV::VWMUL_VX: |
16652 | 0 | case RISCV::VWSLL_VX: |
16653 | 0 | case RISCV::VWSUBU_VX: |
16654 | 0 | case RISCV::VWSUBU_WX: |
16655 | 0 | case RISCV::VWSUB_VX: |
16656 | 0 | case RISCV::VWSUB_WX: |
16657 | 0 | case RISCV::VXOR_VX: { |
16658 | | // op: vs2 |
16659 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16660 | 0 | op &= UINT64_C(31); |
16661 | 0 | op <<= 20; |
16662 | 0 | Value |= op; |
16663 | | // op: rs1 |
16664 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16665 | 0 | op &= UINT64_C(31); |
16666 | 0 | op <<= 15; |
16667 | 0 | Value |= op; |
16668 | | // op: vd |
16669 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16670 | 0 | op &= UINT64_C(31); |
16671 | 0 | op <<= 7; |
16672 | 0 | Value |= op; |
16673 | | // op: vm |
16674 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
16675 | 0 | op &= UINT64_C(1); |
16676 | 0 | op <<= 25; |
16677 | 0 | Value |= op; |
16678 | 0 | break; |
16679 | 0 | } |
16680 | 0 | case RISCV::VAESDF_VS: |
16681 | 0 | case RISCV::VAESDF_VV: |
16682 | 0 | case RISCV::VAESDM_VS: |
16683 | 0 | case RISCV::VAESDM_VV: |
16684 | 0 | case RISCV::VAESEF_VS: |
16685 | 0 | case RISCV::VAESEF_VV: |
16686 | 0 | case RISCV::VAESEM_VS: |
16687 | 0 | case RISCV::VAESEM_VV: |
16688 | 0 | case RISCV::VAESZ_VS: |
16689 | 0 | case RISCV::VFMV_F_S: |
16690 | 0 | case RISCV::VGMUL_VV: |
16691 | 0 | case RISCV::VMV1R_V: |
16692 | 0 | case RISCV::VMV2R_V: |
16693 | 0 | case RISCV::VMV4R_V: |
16694 | 0 | case RISCV::VMV8R_V: |
16695 | 0 | case RISCV::VMV_X_S: |
16696 | 0 | case RISCV::VSM4R_VS: |
16697 | 0 | case RISCV::VSM4R_VV: { |
16698 | | // op: vs2 |
16699 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16700 | 0 | op &= UINT64_C(31); |
16701 | 0 | op <<= 20; |
16702 | 0 | Value |= op; |
16703 | | // op: vd |
16704 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16705 | 0 | op &= UINT64_C(31); |
16706 | 0 | op <<= 7; |
16707 | 0 | Value |= op; |
16708 | 0 | break; |
16709 | 0 | } |
16710 | 0 | case RISCV::VBREV8_V: |
16711 | 0 | case RISCV::VBREV_V: |
16712 | 0 | case RISCV::VCLZ_V: |
16713 | 0 | case RISCV::VCPOP_M: |
16714 | 0 | case RISCV::VCPOP_V: |
16715 | 0 | case RISCV::VCTZ_V: |
16716 | 0 | case RISCV::VFCLASS_V: |
16717 | 0 | case RISCV::VFCVT_F_XU_V: |
16718 | 0 | case RISCV::VFCVT_F_X_V: |
16719 | 0 | case RISCV::VFCVT_RTZ_XU_F_V: |
16720 | 0 | case RISCV::VFCVT_RTZ_X_F_V: |
16721 | 0 | case RISCV::VFCVT_XU_F_V: |
16722 | 0 | case RISCV::VFCVT_X_F_V: |
16723 | 0 | case RISCV::VFIRST_M: |
16724 | 0 | case RISCV::VFNCVTBF16_F_F_W: |
16725 | 0 | case RISCV::VFNCVT_F_F_W: |
16726 | 0 | case RISCV::VFNCVT_F_XU_W: |
16727 | 0 | case RISCV::VFNCVT_F_X_W: |
16728 | 0 | case RISCV::VFNCVT_ROD_F_F_W: |
16729 | 0 | case RISCV::VFNCVT_RTZ_XU_F_W: |
16730 | 0 | case RISCV::VFNCVT_RTZ_X_F_W: |
16731 | 0 | case RISCV::VFNCVT_XU_F_W: |
16732 | 0 | case RISCV::VFNCVT_X_F_W: |
16733 | 0 | case RISCV::VFREC7_V: |
16734 | 0 | case RISCV::VFRSQRT7_V: |
16735 | 0 | case RISCV::VFSQRT_V: |
16736 | 0 | case RISCV::VFWCVTBF16_F_F_V: |
16737 | 0 | case RISCV::VFWCVT_F_F_V: |
16738 | 0 | case RISCV::VFWCVT_F_XU_V: |
16739 | 0 | case RISCV::VFWCVT_F_X_V: |
16740 | 0 | case RISCV::VFWCVT_RTZ_XU_F_V: |
16741 | 0 | case RISCV::VFWCVT_RTZ_X_F_V: |
16742 | 0 | case RISCV::VFWCVT_XU_F_V: |
16743 | 0 | case RISCV::VFWCVT_X_F_V: |
16744 | 0 | case RISCV::VIOTA_M: |
16745 | 0 | case RISCV::VMSBF_M: |
16746 | 0 | case RISCV::VMSIF_M: |
16747 | 0 | case RISCV::VMSOF_M: |
16748 | 0 | case RISCV::VREV8_V: |
16749 | 0 | case RISCV::VSEXT_VF2: |
16750 | 0 | case RISCV::VSEXT_VF4: |
16751 | 0 | case RISCV::VSEXT_VF8: |
16752 | 0 | case RISCV::VZEXT_VF2: |
16753 | 0 | case RISCV::VZEXT_VF4: |
16754 | 0 | case RISCV::VZEXT_VF8: { |
16755 | | // op: vs2 |
16756 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16757 | 0 | op &= UINT64_C(31); |
16758 | 0 | op <<= 20; |
16759 | 0 | Value |= op; |
16760 | | // op: vd |
16761 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16762 | 0 | op &= UINT64_C(31); |
16763 | 0 | op <<= 7; |
16764 | 0 | Value |= op; |
16765 | | // op: vm |
16766 | 0 | op = getVMaskReg(MI, 2, Fixups, STI); |
16767 | 0 | op &= UINT64_C(1); |
16768 | 0 | op <<= 25; |
16769 | 0 | Value |= op; |
16770 | 0 | break; |
16771 | 0 | } |
16772 | 0 | case RISCV::VADC_VVM: |
16773 | 0 | case RISCV::VCOMPRESS_VM: |
16774 | 0 | case RISCV::VGHSH_VV: |
16775 | 0 | case RISCV::VMADC_VV: |
16776 | 0 | case RISCV::VMADC_VVM: |
16777 | 0 | case RISCV::VMANDN_MM: |
16778 | 0 | case RISCV::VMAND_MM: |
16779 | 0 | case RISCV::VMERGE_VVM: |
16780 | 0 | case RISCV::VMNAND_MM: |
16781 | 0 | case RISCV::VMNOR_MM: |
16782 | 0 | case RISCV::VMORN_MM: |
16783 | 0 | case RISCV::VMOR_MM: |
16784 | 0 | case RISCV::VMSBC_VV: |
16785 | 0 | case RISCV::VMSBC_VVM: |
16786 | 0 | case RISCV::VMXNOR_MM: |
16787 | 0 | case RISCV::VMXOR_MM: |
16788 | 0 | case RISCV::VSBC_VVM: |
16789 | 0 | case RISCV::VSHA2CH_VV: |
16790 | 0 | case RISCV::VSHA2CL_VV: |
16791 | 0 | case RISCV::VSHA2MS_VV: |
16792 | 0 | case RISCV::VSM3ME_VV: { |
16793 | | // op: vs2 |
16794 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16795 | 0 | op &= UINT64_C(31); |
16796 | 0 | op <<= 20; |
16797 | 0 | Value |= op; |
16798 | | // op: vs1 |
16799 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16800 | 0 | op &= UINT64_C(31); |
16801 | 0 | op <<= 15; |
16802 | 0 | Value |= op; |
16803 | | // op: vd |
16804 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16805 | 0 | op &= UINT64_C(31); |
16806 | 0 | op <<= 7; |
16807 | 0 | Value |= op; |
16808 | 0 | break; |
16809 | 0 | } |
16810 | 0 | case RISCV::VAADDU_VV: |
16811 | 0 | case RISCV::VAADD_VV: |
16812 | 0 | case RISCV::VADD_VV: |
16813 | 0 | case RISCV::VANDN_VV: |
16814 | 0 | case RISCV::VAND_VV: |
16815 | 0 | case RISCV::VASUBU_VV: |
16816 | 0 | case RISCV::VASUB_VV: |
16817 | 0 | case RISCV::VCLMULH_VV: |
16818 | 0 | case RISCV::VCLMUL_VV: |
16819 | 0 | case RISCV::VDIVU_VV: |
16820 | 0 | case RISCV::VDIV_VV: |
16821 | 0 | case RISCV::VFADD_VV: |
16822 | 0 | case RISCV::VFDIV_VV: |
16823 | 0 | case RISCV::VFMAX_VV: |
16824 | 0 | case RISCV::VFMIN_VV: |
16825 | 0 | case RISCV::VFMUL_VV: |
16826 | 0 | case RISCV::VFREDMAX_VS: |
16827 | 0 | case RISCV::VFREDMIN_VS: |
16828 | 0 | case RISCV::VFREDOSUM_VS: |
16829 | 0 | case RISCV::VFREDUSUM_VS: |
16830 | 0 | case RISCV::VFSGNJN_VV: |
16831 | 0 | case RISCV::VFSGNJX_VV: |
16832 | 0 | case RISCV::VFSGNJ_VV: |
16833 | 0 | case RISCV::VFSUB_VV: |
16834 | 0 | case RISCV::VFWADD_VV: |
16835 | 0 | case RISCV::VFWADD_WV: |
16836 | 0 | case RISCV::VFWMUL_VV: |
16837 | 0 | case RISCV::VFWREDOSUM_VS: |
16838 | 0 | case RISCV::VFWREDUSUM_VS: |
16839 | 0 | case RISCV::VFWSUB_VV: |
16840 | 0 | case RISCV::VFWSUB_WV: |
16841 | 0 | case RISCV::VMAXU_VV: |
16842 | 0 | case RISCV::VMAX_VV: |
16843 | 0 | case RISCV::VMFEQ_VV: |
16844 | 0 | case RISCV::VMFLE_VV: |
16845 | 0 | case RISCV::VMFLT_VV: |
16846 | 0 | case RISCV::VMFNE_VV: |
16847 | 0 | case RISCV::VMINU_VV: |
16848 | 0 | case RISCV::VMIN_VV: |
16849 | 0 | case RISCV::VMSEQ_VV: |
16850 | 0 | case RISCV::VMSLEU_VV: |
16851 | 0 | case RISCV::VMSLE_VV: |
16852 | 0 | case RISCV::VMSLTU_VV: |
16853 | 0 | case RISCV::VMSLT_VV: |
16854 | 0 | case RISCV::VMSNE_VV: |
16855 | 0 | case RISCV::VMULHSU_VV: |
16856 | 0 | case RISCV::VMULHU_VV: |
16857 | 0 | case RISCV::VMULH_VV: |
16858 | 0 | case RISCV::VMUL_VV: |
16859 | 0 | case RISCV::VNCLIPU_WV: |
16860 | 0 | case RISCV::VNCLIP_WV: |
16861 | 0 | case RISCV::VNSRA_WV: |
16862 | 0 | case RISCV::VNSRL_WV: |
16863 | 0 | case RISCV::VOR_VV: |
16864 | 0 | case RISCV::VREDAND_VS: |
16865 | 0 | case RISCV::VREDMAXU_VS: |
16866 | 0 | case RISCV::VREDMAX_VS: |
16867 | 0 | case RISCV::VREDMINU_VS: |
16868 | 0 | case RISCV::VREDMIN_VS: |
16869 | 0 | case RISCV::VREDOR_VS: |
16870 | 0 | case RISCV::VREDSUM_VS: |
16871 | 0 | case RISCV::VREDXOR_VS: |
16872 | 0 | case RISCV::VREMU_VV: |
16873 | 0 | case RISCV::VREM_VV: |
16874 | 0 | case RISCV::VRGATHEREI16_VV: |
16875 | 0 | case RISCV::VRGATHER_VV: |
16876 | 0 | case RISCV::VROL_VV: |
16877 | 0 | case RISCV::VROR_VV: |
16878 | 0 | case RISCV::VSADDU_VV: |
16879 | 0 | case RISCV::VSADD_VV: |
16880 | 0 | case RISCV::VSLL_VV: |
16881 | 0 | case RISCV::VSMUL_VV: |
16882 | 0 | case RISCV::VSRA_VV: |
16883 | 0 | case RISCV::VSRL_VV: |
16884 | 0 | case RISCV::VSSRA_VV: |
16885 | 0 | case RISCV::VSSRL_VV: |
16886 | 0 | case RISCV::VSSUBU_VV: |
16887 | 0 | case RISCV::VSSUB_VV: |
16888 | 0 | case RISCV::VSUB_VV: |
16889 | 0 | case RISCV::VWADDU_VV: |
16890 | 0 | case RISCV::VWADDU_WV: |
16891 | 0 | case RISCV::VWADD_VV: |
16892 | 0 | case RISCV::VWADD_WV: |
16893 | 0 | case RISCV::VWMULSU_VV: |
16894 | 0 | case RISCV::VWMULU_VV: |
16895 | 0 | case RISCV::VWMUL_VV: |
16896 | 0 | case RISCV::VWREDSUMU_VS: |
16897 | 0 | case RISCV::VWREDSUM_VS: |
16898 | 0 | case RISCV::VWSLL_VV: |
16899 | 0 | case RISCV::VWSUBU_VV: |
16900 | 0 | case RISCV::VWSUBU_WV: |
16901 | 0 | case RISCV::VWSUB_VV: |
16902 | 0 | case RISCV::VWSUB_WV: |
16903 | 0 | case RISCV::VXOR_VV: { |
16904 | | // op: vs2 |
16905 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16906 | 0 | op &= UINT64_C(31); |
16907 | 0 | op <<= 20; |
16908 | 0 | Value |= op; |
16909 | | // op: vs1 |
16910 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16911 | 0 | op &= UINT64_C(31); |
16912 | 0 | op <<= 15; |
16913 | 0 | Value |= op; |
16914 | | // op: vd |
16915 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
16916 | 0 | op &= UINT64_C(31); |
16917 | 0 | op <<= 7; |
16918 | 0 | Value |= op; |
16919 | | // op: vm |
16920 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
16921 | 0 | op &= UINT64_C(1); |
16922 | 0 | op <<= 25; |
16923 | 0 | Value |= op; |
16924 | 0 | break; |
16925 | 0 | } |
16926 | 0 | case RISCV::VLOXEI8_V: |
16927 | 0 | case RISCV::VLOXEI16_V: |
16928 | 0 | case RISCV::VLOXEI32_V: |
16929 | 0 | case RISCV::VLOXEI64_V: |
16930 | 0 | case RISCV::VLOXSEG2EI8_V: |
16931 | 0 | case RISCV::VLOXSEG2EI16_V: |
16932 | 0 | case RISCV::VLOXSEG2EI32_V: |
16933 | 0 | case RISCV::VLOXSEG2EI64_V: |
16934 | 0 | case RISCV::VLOXSEG3EI8_V: |
16935 | 0 | case RISCV::VLOXSEG3EI16_V: |
16936 | 0 | case RISCV::VLOXSEG3EI32_V: |
16937 | 0 | case RISCV::VLOXSEG3EI64_V: |
16938 | 0 | case RISCV::VLOXSEG4EI8_V: |
16939 | 0 | case RISCV::VLOXSEG4EI16_V: |
16940 | 0 | case RISCV::VLOXSEG4EI32_V: |
16941 | 0 | case RISCV::VLOXSEG4EI64_V: |
16942 | 0 | case RISCV::VLOXSEG5EI8_V: |
16943 | 0 | case RISCV::VLOXSEG5EI16_V: |
16944 | 0 | case RISCV::VLOXSEG5EI32_V: |
16945 | 0 | case RISCV::VLOXSEG5EI64_V: |
16946 | 0 | case RISCV::VLOXSEG6EI8_V: |
16947 | 0 | case RISCV::VLOXSEG6EI16_V: |
16948 | 0 | case RISCV::VLOXSEG6EI32_V: |
16949 | 0 | case RISCV::VLOXSEG6EI64_V: |
16950 | 0 | case RISCV::VLOXSEG7EI8_V: |
16951 | 0 | case RISCV::VLOXSEG7EI16_V: |
16952 | 0 | case RISCV::VLOXSEG7EI32_V: |
16953 | 0 | case RISCV::VLOXSEG7EI64_V: |
16954 | 0 | case RISCV::VLOXSEG8EI8_V: |
16955 | 0 | case RISCV::VLOXSEG8EI16_V: |
16956 | 0 | case RISCV::VLOXSEG8EI32_V: |
16957 | 0 | case RISCV::VLOXSEG8EI64_V: |
16958 | 0 | case RISCV::VLUXEI8_V: |
16959 | 0 | case RISCV::VLUXEI16_V: |
16960 | 0 | case RISCV::VLUXEI32_V: |
16961 | 0 | case RISCV::VLUXEI64_V: |
16962 | 0 | case RISCV::VLUXSEG2EI8_V: |
16963 | 0 | case RISCV::VLUXSEG2EI16_V: |
16964 | 0 | case RISCV::VLUXSEG2EI32_V: |
16965 | 0 | case RISCV::VLUXSEG2EI64_V: |
16966 | 0 | case RISCV::VLUXSEG3EI8_V: |
16967 | 0 | case RISCV::VLUXSEG3EI16_V: |
16968 | 0 | case RISCV::VLUXSEG3EI32_V: |
16969 | 0 | case RISCV::VLUXSEG3EI64_V: |
16970 | 0 | case RISCV::VLUXSEG4EI8_V: |
16971 | 0 | case RISCV::VLUXSEG4EI16_V: |
16972 | 0 | case RISCV::VLUXSEG4EI32_V: |
16973 | 0 | case RISCV::VLUXSEG4EI64_V: |
16974 | 0 | case RISCV::VLUXSEG5EI8_V: |
16975 | 0 | case RISCV::VLUXSEG5EI16_V: |
16976 | 0 | case RISCV::VLUXSEG5EI32_V: |
16977 | 0 | case RISCV::VLUXSEG5EI64_V: |
16978 | 0 | case RISCV::VLUXSEG6EI8_V: |
16979 | 0 | case RISCV::VLUXSEG6EI16_V: |
16980 | 0 | case RISCV::VLUXSEG6EI32_V: |
16981 | 0 | case RISCV::VLUXSEG6EI64_V: |
16982 | 0 | case RISCV::VLUXSEG7EI8_V: |
16983 | 0 | case RISCV::VLUXSEG7EI16_V: |
16984 | 0 | case RISCV::VLUXSEG7EI32_V: |
16985 | 0 | case RISCV::VLUXSEG7EI64_V: |
16986 | 0 | case RISCV::VLUXSEG8EI8_V: |
16987 | 0 | case RISCV::VLUXSEG8EI16_V: |
16988 | 0 | case RISCV::VLUXSEG8EI32_V: |
16989 | 0 | case RISCV::VLUXSEG8EI64_V: { |
16990 | | // op: vs2 |
16991 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
16992 | 0 | op &= UINT64_C(31); |
16993 | 0 | op <<= 20; |
16994 | 0 | Value |= op; |
16995 | | // op: rs1 |
16996 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
16997 | 0 | op &= UINT64_C(31); |
16998 | 0 | op <<= 15; |
16999 | 0 | Value |= op; |
17000 | | // op: vd |
17001 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
17002 | 0 | op &= UINT64_C(31); |
17003 | 0 | op <<= 7; |
17004 | 0 | Value |= op; |
17005 | | // op: vm |
17006 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
17007 | 0 | op &= UINT64_C(1); |
17008 | 0 | op <<= 25; |
17009 | 0 | Value |= op; |
17010 | 0 | break; |
17011 | 0 | } |
17012 | 0 | case RISCV::VSOXEI8_V: |
17013 | 0 | case RISCV::VSOXEI16_V: |
17014 | 0 | case RISCV::VSOXEI32_V: |
17015 | 0 | case RISCV::VSOXEI64_V: |
17016 | 0 | case RISCV::VSOXSEG2EI8_V: |
17017 | 0 | case RISCV::VSOXSEG2EI16_V: |
17018 | 0 | case RISCV::VSOXSEG2EI32_V: |
17019 | 0 | case RISCV::VSOXSEG2EI64_V: |
17020 | 0 | case RISCV::VSOXSEG3EI8_V: |
17021 | 0 | case RISCV::VSOXSEG3EI16_V: |
17022 | 0 | case RISCV::VSOXSEG3EI32_V: |
17023 | 0 | case RISCV::VSOXSEG3EI64_V: |
17024 | 0 | case RISCV::VSOXSEG4EI8_V: |
17025 | 0 | case RISCV::VSOXSEG4EI16_V: |
17026 | 0 | case RISCV::VSOXSEG4EI32_V: |
17027 | 0 | case RISCV::VSOXSEG4EI64_V: |
17028 | 0 | case RISCV::VSOXSEG5EI8_V: |
17029 | 0 | case RISCV::VSOXSEG5EI16_V: |
17030 | 0 | case RISCV::VSOXSEG5EI32_V: |
17031 | 0 | case RISCV::VSOXSEG5EI64_V: |
17032 | 0 | case RISCV::VSOXSEG6EI8_V: |
17033 | 0 | case RISCV::VSOXSEG6EI16_V: |
17034 | 0 | case RISCV::VSOXSEG6EI32_V: |
17035 | 0 | case RISCV::VSOXSEG6EI64_V: |
17036 | 0 | case RISCV::VSOXSEG7EI8_V: |
17037 | 0 | case RISCV::VSOXSEG7EI16_V: |
17038 | 0 | case RISCV::VSOXSEG7EI32_V: |
17039 | 0 | case RISCV::VSOXSEG7EI64_V: |
17040 | 0 | case RISCV::VSOXSEG8EI8_V: |
17041 | 0 | case RISCV::VSOXSEG8EI16_V: |
17042 | 0 | case RISCV::VSOXSEG8EI32_V: |
17043 | 0 | case RISCV::VSOXSEG8EI64_V: |
17044 | 0 | case RISCV::VSUXEI8_V: |
17045 | 0 | case RISCV::VSUXEI16_V: |
17046 | 0 | case RISCV::VSUXEI32_V: |
17047 | 0 | case RISCV::VSUXEI64_V: |
17048 | 0 | case RISCV::VSUXSEG2EI8_V: |
17049 | 0 | case RISCV::VSUXSEG2EI16_V: |
17050 | 0 | case RISCV::VSUXSEG2EI32_V: |
17051 | 0 | case RISCV::VSUXSEG2EI64_V: |
17052 | 0 | case RISCV::VSUXSEG3EI8_V: |
17053 | 0 | case RISCV::VSUXSEG3EI16_V: |
17054 | 0 | case RISCV::VSUXSEG3EI32_V: |
17055 | 0 | case RISCV::VSUXSEG3EI64_V: |
17056 | 0 | case RISCV::VSUXSEG4EI8_V: |
17057 | 0 | case RISCV::VSUXSEG4EI16_V: |
17058 | 0 | case RISCV::VSUXSEG4EI32_V: |
17059 | 0 | case RISCV::VSUXSEG4EI64_V: |
17060 | 0 | case RISCV::VSUXSEG5EI8_V: |
17061 | 0 | case RISCV::VSUXSEG5EI16_V: |
17062 | 0 | case RISCV::VSUXSEG5EI32_V: |
17063 | 0 | case RISCV::VSUXSEG5EI64_V: |
17064 | 0 | case RISCV::VSUXSEG6EI8_V: |
17065 | 0 | case RISCV::VSUXSEG6EI16_V: |
17066 | 0 | case RISCV::VSUXSEG6EI32_V: |
17067 | 0 | case RISCV::VSUXSEG6EI64_V: |
17068 | 0 | case RISCV::VSUXSEG7EI8_V: |
17069 | 0 | case RISCV::VSUXSEG7EI16_V: |
17070 | 0 | case RISCV::VSUXSEG7EI32_V: |
17071 | 0 | case RISCV::VSUXSEG7EI64_V: |
17072 | 0 | case RISCV::VSUXSEG8EI8_V: |
17073 | 0 | case RISCV::VSUXSEG8EI16_V: |
17074 | 0 | case RISCV::VSUXSEG8EI32_V: |
17075 | 0 | case RISCV::VSUXSEG8EI64_V: { |
17076 | | // op: vs2 |
17077 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
17078 | 0 | op &= UINT64_C(31); |
17079 | 0 | op <<= 20; |
17080 | 0 | Value |= op; |
17081 | | // op: rs1 |
17082 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
17083 | 0 | op &= UINT64_C(31); |
17084 | 0 | op <<= 15; |
17085 | 0 | Value |= op; |
17086 | | // op: vs3 |
17087 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
17088 | 0 | op &= UINT64_C(31); |
17089 | 0 | op <<= 7; |
17090 | 0 | Value |= op; |
17091 | | // op: vm |
17092 | 0 | op = getVMaskReg(MI, 3, Fixups, STI); |
17093 | 0 | op &= UINT64_C(1); |
17094 | 0 | op <<= 25; |
17095 | 0 | Value |= op; |
17096 | 0 | break; |
17097 | 0 | } |
17098 | 0 | case RISCV::THVdotVMAQASU_VX: |
17099 | 0 | case RISCV::THVdotVMAQAUS_VX: |
17100 | 0 | case RISCV::THVdotVMAQAU_VX: |
17101 | 0 | case RISCV::THVdotVMAQA_VX: |
17102 | 0 | case RISCV::VFMACC_VF: |
17103 | 0 | case RISCV::VFMADD_VF: |
17104 | 0 | case RISCV::VFMSAC_VF: |
17105 | 0 | case RISCV::VFMSUB_VF: |
17106 | 0 | case RISCV::VFNMACC_VF: |
17107 | 0 | case RISCV::VFNMADD_VF: |
17108 | 0 | case RISCV::VFNMSAC_VF: |
17109 | 0 | case RISCV::VFNMSUB_VF: |
17110 | 0 | case RISCV::VFWMACCBF16_VF: |
17111 | 0 | case RISCV::VFWMACC_VF: |
17112 | 0 | case RISCV::VFWMSAC_VF: |
17113 | 0 | case RISCV::VFWNMACC_VF: |
17114 | 0 | case RISCV::VFWNMSAC_VF: |
17115 | 0 | case RISCV::VMACC_VX: |
17116 | 0 | case RISCV::VMADD_VX: |
17117 | 0 | case RISCV::VNMSAC_VX: |
17118 | 0 | case RISCV::VNMSUB_VX: |
17119 | 0 | case RISCV::VWMACCSU_VX: |
17120 | 0 | case RISCV::VWMACCUS_VX: |
17121 | 0 | case RISCV::VWMACCU_VX: |
17122 | 0 | case RISCV::VWMACC_VX: { |
17123 | | // op: vs2 |
17124 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
17125 | 0 | op &= UINT64_C(31); |
17126 | 0 | op <<= 20; |
17127 | 0 | Value |= op; |
17128 | | // op: rs1 |
17129 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
17130 | 0 | op &= UINT64_C(31); |
17131 | 0 | op <<= 15; |
17132 | 0 | Value |= op; |
17133 | | // op: vd |
17134 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
17135 | 0 | op &= UINT64_C(31); |
17136 | 0 | op <<= 7; |
17137 | 0 | Value |= op; |
17138 | | // op: vm |
17139 | 0 | op = getVMaskReg(MI, 4, Fixups, STI); |
17140 | 0 | op &= UINT64_C(1); |
17141 | 0 | op <<= 25; |
17142 | 0 | Value |= op; |
17143 | 0 | break; |
17144 | 0 | } |
17145 | 0 | case RISCV::THVdotVMAQASU_VV: |
17146 | 0 | case RISCV::THVdotVMAQAU_VV: |
17147 | 0 | case RISCV::THVdotVMAQA_VV: |
17148 | 0 | case RISCV::VFMACC_VV: |
17149 | 0 | case RISCV::VFMADD_VV: |
17150 | 0 | case RISCV::VFMSAC_VV: |
17151 | 0 | case RISCV::VFMSUB_VV: |
17152 | 0 | case RISCV::VFNMACC_VV: |
17153 | 0 | case RISCV::VFNMADD_VV: |
17154 | 0 | case RISCV::VFNMSAC_VV: |
17155 | 0 | case RISCV::VFNMSUB_VV: |
17156 | 0 | case RISCV::VFWMACCBF16_VV: |
17157 | 0 | case RISCV::VFWMACC_VV: |
17158 | 0 | case RISCV::VFWMSAC_VV: |
17159 | 0 | case RISCV::VFWNMACC_VV: |
17160 | 0 | case RISCV::VFWNMSAC_VV: |
17161 | 0 | case RISCV::VMACC_VV: |
17162 | 0 | case RISCV::VMADD_VV: |
17163 | 0 | case RISCV::VNMSAC_VV: |
17164 | 0 | case RISCV::VNMSUB_VV: |
17165 | 0 | case RISCV::VWMACCSU_VV: |
17166 | 0 | case RISCV::VWMACCU_VV: |
17167 | 0 | case RISCV::VWMACC_VV: { |
17168 | | // op: vs2 |
17169 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
17170 | 0 | op &= UINT64_C(31); |
17171 | 0 | op <<= 20; |
17172 | 0 | Value |= op; |
17173 | | // op: vs1 |
17174 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
17175 | 0 | op &= UINT64_C(31); |
17176 | 0 | op <<= 15; |
17177 | 0 | Value |= op; |
17178 | | // op: vd |
17179 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
17180 | 0 | op &= UINT64_C(31); |
17181 | 0 | op <<= 7; |
17182 | 0 | Value |= op; |
17183 | | // op: vm |
17184 | 0 | op = getVMaskReg(MI, 4, Fixups, STI); |
17185 | 0 | op &= UINT64_C(1); |
17186 | 0 | op <<= 25; |
17187 | 0 | Value |= op; |
17188 | 0 | break; |
17189 | 0 | } |
17190 | 0 | default: |
17191 | 0 | std::string msg; |
17192 | 0 | raw_string_ostream Msg(msg); |
17193 | 0 | Msg << "Not supported instr: " << MI; |
17194 | 0 | report_fatal_error(Msg.str().c_str()); |
17195 | 0 | } |
17196 | 0 | return Value; |
17197 | 0 | } |
17198 | | |
17199 | | #ifdef GET_OPERAND_BIT_OFFSET |
17200 | | #undef GET_OPERAND_BIT_OFFSET |
17201 | | |
17202 | | uint32_t RISCVMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
17203 | | unsigned OpNum, |
17204 | | const MCSubtargetInfo &STI) const { |
17205 | | switch (MI.getOpcode()) { |
17206 | | case RISCV::CMOP1: |
17207 | | case RISCV::CMOP3: |
17208 | | case RISCV::CMOP5: |
17209 | | case RISCV::CMOP7: |
17210 | | case RISCV::CMOP9: |
17211 | | case RISCV::CMOP11: |
17212 | | case RISCV::CMOP13: |
17213 | | case RISCV::CMOP15: |
17214 | | case RISCV::C_EBREAK: |
17215 | | case RISCV::C_NOP: |
17216 | | case RISCV::C_SSPOPCHK: |
17217 | | case RISCV::C_SSPUSH: |
17218 | | case RISCV::C_UNIMP: |
17219 | | case RISCV::DRET: |
17220 | | case RISCV::EBREAK: |
17221 | | case RISCV::ECALL: |
17222 | | case RISCV::FENCE_I: |
17223 | | case RISCV::FENCE_TSO: |
17224 | | case RISCV::MRET: |
17225 | | case RISCV::SFENCE_INVAL_IR: |
17226 | | case RISCV::SFENCE_W_INVAL: |
17227 | | case RISCV::SRET: |
17228 | | case RISCV::TH_DCACHE_CALL: |
17229 | | case RISCV::TH_DCACHE_CIALL: |
17230 | | case RISCV::TH_DCACHE_IALL: |
17231 | | case RISCV::TH_ICACHE_IALL: |
17232 | | case RISCV::TH_ICACHE_IALLS: |
17233 | | case RISCV::TH_L2CACHE_CALL: |
17234 | | case RISCV::TH_L2CACHE_CIALL: |
17235 | | case RISCV::TH_L2CACHE_IALL: |
17236 | | case RISCV::TH_SYNC: |
17237 | | case RISCV::TH_SYNC_I: |
17238 | | case RISCV::TH_SYNC_IS: |
17239 | | case RISCV::TH_SYNC_S: |
17240 | | case RISCV::UNIMP: |
17241 | | case RISCV::WFI: |
17242 | | case RISCV::WRS_NTO: |
17243 | | case RISCV::WRS_STO: { |
17244 | | break; |
17245 | | } |
17246 | | case RISCV::C_NOP_HINT: { |
17247 | | switch (OpNum) { |
17248 | | case 0: |
17249 | | // op: imm |
17250 | | return 2; |
17251 | | } |
17252 | | break; |
17253 | | } |
17254 | | case RISCV::CM_JALT: |
17255 | | case RISCV::CM_JT: { |
17256 | | switch (OpNum) { |
17257 | | case 0: |
17258 | | // op: index |
17259 | | return 2; |
17260 | | } |
17261 | | break; |
17262 | | } |
17263 | | case RISCV::C_J: |
17264 | | case RISCV::C_JAL: { |
17265 | | switch (OpNum) { |
17266 | | case 0: |
17267 | | // op: offset |
17268 | | return 2; |
17269 | | } |
17270 | | break; |
17271 | | } |
17272 | | case RISCV::InsnS: { |
17273 | | switch (OpNum) { |
17274 | | case 0: |
17275 | | // op: opcode |
17276 | | return 0; |
17277 | | case 1: |
17278 | | // op: funct3 |
17279 | | return 12; |
17280 | | case 4: |
17281 | | // op: imm12 |
17282 | | return 7; |
17283 | | case 2: |
17284 | | // op: rs2 |
17285 | | return 20; |
17286 | | case 3: |
17287 | | // op: rs1 |
17288 | | return 15; |
17289 | | } |
17290 | | break; |
17291 | | } |
17292 | | case RISCV::InsnB: { |
17293 | | switch (OpNum) { |
17294 | | case 0: |
17295 | | // op: opcode |
17296 | | return 0; |
17297 | | case 1: |
17298 | | // op: funct3 |
17299 | | return 12; |
17300 | | case 4: |
17301 | | // op: imm12 |
17302 | | return 7; |
17303 | | case 3: |
17304 | | // op: rs2 |
17305 | | return 20; |
17306 | | case 2: |
17307 | | // op: rs1 |
17308 | | return 15; |
17309 | | } |
17310 | | break; |
17311 | | } |
17312 | | case RISCV::InsnCJ: { |
17313 | | switch (OpNum) { |
17314 | | case 0: |
17315 | | // op: opcode |
17316 | | return 0; |
17317 | | case 1: |
17318 | | // op: funct3 |
17319 | | return 13; |
17320 | | case 2: |
17321 | | // op: imm11 |
17322 | | return 2; |
17323 | | } |
17324 | | break; |
17325 | | } |
17326 | | case RISCV::InsnCSS: { |
17327 | | switch (OpNum) { |
17328 | | case 0: |
17329 | | // op: opcode |
17330 | | return 0; |
17331 | | case 1: |
17332 | | // op: funct3 |
17333 | | return 13; |
17334 | | case 3: |
17335 | | // op: imm6 |
17336 | | return 7; |
17337 | | case 2: |
17338 | | // op: rs2 |
17339 | | return 2; |
17340 | | } |
17341 | | break; |
17342 | | } |
17343 | | case RISCV::InsnCB: { |
17344 | | switch (OpNum) { |
17345 | | case 0: |
17346 | | // op: opcode |
17347 | | return 0; |
17348 | | case 1: |
17349 | | // op: funct3 |
17350 | | return 13; |
17351 | | case 3: |
17352 | | // op: imm8 |
17353 | | return 2; |
17354 | | case 2: |
17355 | | // op: rs1 |
17356 | | return 7; |
17357 | | } |
17358 | | break; |
17359 | | } |
17360 | | case RISCV::InsnCS: { |
17361 | | switch (OpNum) { |
17362 | | case 0: |
17363 | | // op: opcode |
17364 | | return 0; |
17365 | | case 1: |
17366 | | // op: funct3 |
17367 | | return 13; |
17368 | | case 4: |
17369 | | // op: imm5 |
17370 | | return 5; |
17371 | | case 2: |
17372 | | // op: rs2 |
17373 | | return 2; |
17374 | | case 3: |
17375 | | // op: rs1 |
17376 | | return 7; |
17377 | | } |
17378 | | break; |
17379 | | } |
17380 | | case RISCV::FENCE: { |
17381 | | switch (OpNum) { |
17382 | | case 0: |
17383 | | // op: pred |
17384 | | return 24; |
17385 | | case 1: |
17386 | | // op: succ |
17387 | | return 20; |
17388 | | } |
17389 | | break; |
17390 | | } |
17391 | | case RISCV::C_FLD: |
17392 | | case RISCV::C_FLW: |
17393 | | case RISCV::C_LBU: |
17394 | | case RISCV::C_LD: |
17395 | | case RISCV::C_LH: |
17396 | | case RISCV::C_LHU: |
17397 | | case RISCV::C_LW: { |
17398 | | switch (OpNum) { |
17399 | | case 0: |
17400 | | // op: rd |
17401 | | return 2; |
17402 | | case 1: |
17403 | | // op: rs1 |
17404 | | return 7; |
17405 | | case 2: |
17406 | | // op: imm |
17407 | | return 5; |
17408 | | } |
17409 | | break; |
17410 | | } |
17411 | | case RISCV::CV_LBU_rr: |
17412 | | case RISCV::CV_LB_rr: |
17413 | | case RISCV::CV_LHU_rr: |
17414 | | case RISCV::CV_LH_rr: |
17415 | | case RISCV::CV_LW_rr: { |
17416 | | switch (OpNum) { |
17417 | | case 0: |
17418 | | // op: rd |
17419 | | return 7; |
17420 | | case 1: |
17421 | | // op: cvrr |
17422 | | return 15; |
17423 | | } |
17424 | | break; |
17425 | | } |
17426 | | case RISCV::FLI_D: |
17427 | | case RISCV::FLI_H: |
17428 | | case RISCV::FLI_S: { |
17429 | | switch (OpNum) { |
17430 | | case 0: |
17431 | | // op: rd |
17432 | | return 7; |
17433 | | case 1: |
17434 | | // op: imm |
17435 | | return 15; |
17436 | | } |
17437 | | break; |
17438 | | } |
17439 | | case RISCV::SSRDP: { |
17440 | | switch (OpNum) { |
17441 | | case 0: |
17442 | | // op: rd |
17443 | | return 7; |
17444 | | } |
17445 | | break; |
17446 | | } |
17447 | | case RISCV::CM_POP: |
17448 | | case RISCV::CM_POPRET: |
17449 | | case RISCV::CM_POPRETZ: |
17450 | | case RISCV::CM_PUSH: { |
17451 | | switch (OpNum) { |
17452 | | case 0: |
17453 | | // op: rlist |
17454 | | return 4; |
17455 | | case 1: |
17456 | | // op: spimm |
17457 | | return 2; |
17458 | | } |
17459 | | break; |
17460 | | } |
17461 | | case RISCV::CBO_CLEAN: |
17462 | | case RISCV::CBO_FLUSH: |
17463 | | case RISCV::CBO_INVAL: |
17464 | | case RISCV::CBO_ZERO: |
17465 | | case RISCV::SSPOPCHK: |
17466 | | case RISCV::TH_DCACHE_CIPA: |
17467 | | case RISCV::TH_DCACHE_CISW: |
17468 | | case RISCV::TH_DCACHE_CIVA: |
17469 | | case RISCV::TH_DCACHE_CPA: |
17470 | | case RISCV::TH_DCACHE_CPAL1: |
17471 | | case RISCV::TH_DCACHE_CSW: |
17472 | | case RISCV::TH_DCACHE_CVA: |
17473 | | case RISCV::TH_DCACHE_CVAL1: |
17474 | | case RISCV::TH_DCACHE_IPA: |
17475 | | case RISCV::TH_DCACHE_ISW: |
17476 | | case RISCV::TH_DCACHE_IVA: |
17477 | | case RISCV::TH_ICACHE_IPA: |
17478 | | case RISCV::TH_ICACHE_IVA: { |
17479 | | switch (OpNum) { |
17480 | | case 0: |
17481 | | // op: rs1 |
17482 | | return 15; |
17483 | | } |
17484 | | break; |
17485 | | } |
17486 | | case RISCV::C_MV: { |
17487 | | switch (OpNum) { |
17488 | | case 0: |
17489 | | // op: rs1 |
17490 | | return 7; |
17491 | | case 1: |
17492 | | // op: rs2 |
17493 | | return 2; |
17494 | | } |
17495 | | break; |
17496 | | } |
17497 | | case RISCV::C_JALR: |
17498 | | case RISCV::C_JR: { |
17499 | | switch (OpNum) { |
17500 | | case 0: |
17501 | | // op: rs1 |
17502 | | return 7; |
17503 | | } |
17504 | | break; |
17505 | | } |
17506 | | case RISCV::CV_SB_rr: |
17507 | | case RISCV::CV_SH_rr: |
17508 | | case RISCV::CV_SW_rr: { |
17509 | | switch (OpNum) { |
17510 | | case 0: |
17511 | | // op: rs2 |
17512 | | return 20; |
17513 | | case 1: |
17514 | | // op: cvrr |
17515 | | return 7; |
17516 | | } |
17517 | | break; |
17518 | | } |
17519 | | case RISCV::HSV_B: |
17520 | | case RISCV::HSV_D: |
17521 | | case RISCV::HSV_H: |
17522 | | case RISCV::HSV_W: { |
17523 | | switch (OpNum) { |
17524 | | case 0: |
17525 | | // op: rs2 |
17526 | | return 20; |
17527 | | case 1: |
17528 | | // op: rs1 |
17529 | | return 15; |
17530 | | } |
17531 | | break; |
17532 | | } |
17533 | | case RISCV::SSPUSH: { |
17534 | | switch (OpNum) { |
17535 | | case 0: |
17536 | | // op: rs2 |
17537 | | return 20; |
17538 | | } |
17539 | | break; |
17540 | | } |
17541 | | case RISCV::C_FSD: |
17542 | | case RISCV::C_FSW: |
17543 | | case RISCV::C_SB: |
17544 | | case RISCV::C_SD: |
17545 | | case RISCV::C_SH: |
17546 | | case RISCV::C_SW: { |
17547 | | switch (OpNum) { |
17548 | | case 0: |
17549 | | // op: rs2 |
17550 | | return 2; |
17551 | | case 1: |
17552 | | // op: rs1 |
17553 | | return 7; |
17554 | | case 2: |
17555 | | // op: imm |
17556 | | return 5; |
17557 | | } |
17558 | | break; |
17559 | | } |
17560 | | case RISCV::VID_V: { |
17561 | | switch (OpNum) { |
17562 | | case 0: |
17563 | | // op: vd |
17564 | | return 7; |
17565 | | case 1: |
17566 | | // op: vm |
17567 | | return 25; |
17568 | | } |
17569 | | break; |
17570 | | } |
17571 | | case RISCV::VMV_V_I: { |
17572 | | switch (OpNum) { |
17573 | | case 1: |
17574 | | // op: imm |
17575 | | return 15; |
17576 | | case 0: |
17577 | | // op: vd |
17578 | | return 7; |
17579 | | } |
17580 | | break; |
17581 | | } |
17582 | | case RISCV::C_LI: |
17583 | | case RISCV::C_LUI: { |
17584 | | switch (OpNum) { |
17585 | | case 1: |
17586 | | // op: imm |
17587 | | return 2; |
17588 | | case 0: |
17589 | | // op: rd |
17590 | | return 7; |
17591 | | } |
17592 | | break; |
17593 | | } |
17594 | | case RISCV::C_BEQZ: |
17595 | | case RISCV::C_BNEZ: { |
17596 | | switch (OpNum) { |
17597 | | case 1: |
17598 | | // op: imm |
17599 | | return 2; |
17600 | | case 0: |
17601 | | // op: rs1 |
17602 | | return 7; |
17603 | | } |
17604 | | break; |
17605 | | } |
17606 | | case RISCV::C_LI_HINT: |
17607 | | case RISCV::C_LUI_HINT: { |
17608 | | switch (OpNum) { |
17609 | | case 1: |
17610 | | // op: imm |
17611 | | return 2; |
17612 | | } |
17613 | | break; |
17614 | | } |
17615 | | case RISCV::PREFETCH_I: |
17616 | | case RISCV::PREFETCH_R: |
17617 | | case RISCV::PREFETCH_W: { |
17618 | | switch (OpNum) { |
17619 | | case 1: |
17620 | | // op: imm12 |
17621 | | return 25; |
17622 | | case 0: |
17623 | | // op: rs1 |
17624 | | return 15; |
17625 | | } |
17626 | | break; |
17627 | | } |
17628 | | case RISCV::AUIPC: |
17629 | | case RISCV::JAL: |
17630 | | case RISCV::LUI: { |
17631 | | switch (OpNum) { |
17632 | | case 1: |
17633 | | // op: imm20 |
17634 | | return 12; |
17635 | | case 0: |
17636 | | // op: rd |
17637 | | return 7; |
17638 | | } |
17639 | | break; |
17640 | | } |
17641 | | case RISCV::InsnI: |
17642 | | case RISCV::InsnI_Mem: { |
17643 | | switch (OpNum) { |
17644 | | case 1: |
17645 | | // op: opcode |
17646 | | return 0; |
17647 | | case 2: |
17648 | | // op: funct3 |
17649 | | return 12; |
17650 | | case 4: |
17651 | | // op: imm12 |
17652 | | return 20; |
17653 | | case 3: |
17654 | | // op: rs1 |
17655 | | return 15; |
17656 | | case 0: |
17657 | | // op: rd |
17658 | | return 7; |
17659 | | } |
17660 | | break; |
17661 | | } |
17662 | | case RISCV::InsnCI: { |
17663 | | switch (OpNum) { |
17664 | | case 1: |
17665 | | // op: opcode |
17666 | | return 0; |
17667 | | case 2: |
17668 | | // op: funct3 |
17669 | | return 13; |
17670 | | case 3: |
17671 | | // op: imm6 |
17672 | | return 2; |
17673 | | case 0: |
17674 | | // op: rd |
17675 | | return 7; |
17676 | | } |
17677 | | break; |
17678 | | } |
17679 | | case RISCV::InsnCIW: { |
17680 | | switch (OpNum) { |
17681 | | case 1: |
17682 | | // op: opcode |
17683 | | return 0; |
17684 | | case 2: |
17685 | | // op: funct3 |
17686 | | return 13; |
17687 | | case 3: |
17688 | | // op: imm8 |
17689 | | return 5; |
17690 | | case 0: |
17691 | | // op: rd |
17692 | | return 2; |
17693 | | } |
17694 | | break; |
17695 | | } |
17696 | | case RISCV::InsnCL: { |
17697 | | switch (OpNum) { |
17698 | | case 1: |
17699 | | // op: opcode |
17700 | | return 0; |
17701 | | case 2: |
17702 | | // op: funct3 |
17703 | | return 13; |
17704 | | case 4: |
17705 | | // op: imm5 |
17706 | | return 5; |
17707 | | case 0: |
17708 | | // op: rd |
17709 | | return 2; |
17710 | | case 3: |
17711 | | // op: rs1 |
17712 | | return 7; |
17713 | | } |
17714 | | break; |
17715 | | } |
17716 | | case RISCV::InsnCR: { |
17717 | | switch (OpNum) { |
17718 | | case 1: |
17719 | | // op: opcode |
17720 | | return 0; |
17721 | | case 2: |
17722 | | // op: funct4 |
17723 | | return 12; |
17724 | | case 3: |
17725 | | // op: rs2 |
17726 | | return 2; |
17727 | | case 0: |
17728 | | // op: rd |
17729 | | return 7; |
17730 | | } |
17731 | | break; |
17732 | | } |
17733 | | case RISCV::InsnCA: { |
17734 | | switch (OpNum) { |
17735 | | case 1: |
17736 | | // op: opcode |
17737 | | return 0; |
17738 | | case 2: |
17739 | | // op: funct6 |
17740 | | return 10; |
17741 | | case 3: |
17742 | | // op: funct2 |
17743 | | return 5; |
17744 | | case 0: |
17745 | | // op: rd |
17746 | | return 7; |
17747 | | case 4: |
17748 | | // op: rs2 |
17749 | | return 2; |
17750 | | } |
17751 | | break; |
17752 | | } |
17753 | | case RISCV::InsnJ: |
17754 | | case RISCV::InsnU: { |
17755 | | switch (OpNum) { |
17756 | | case 1: |
17757 | | // op: opcode |
17758 | | return 0; |
17759 | | case 2: |
17760 | | // op: imm20 |
17761 | | return 12; |
17762 | | case 0: |
17763 | | // op: rd |
17764 | | return 7; |
17765 | | } |
17766 | | break; |
17767 | | } |
17768 | | case RISCV::InsnR4: { |
17769 | | switch (OpNum) { |
17770 | | case 1: |
17771 | | // op: opcode |
17772 | | return 0; |
17773 | | case 3: |
17774 | | // op: funct2 |
17775 | | return 25; |
17776 | | case 2: |
17777 | | // op: funct3 |
17778 | | return 12; |
17779 | | case 6: |
17780 | | // op: rs3 |
17781 | | return 27; |
17782 | | case 5: |
17783 | | // op: rs2 |
17784 | | return 20; |
17785 | | case 4: |
17786 | | // op: rs1 |
17787 | | return 15; |
17788 | | case 0: |
17789 | | // op: rd |
17790 | | return 7; |
17791 | | } |
17792 | | break; |
17793 | | } |
17794 | | case RISCV::InsnR: { |
17795 | | switch (OpNum) { |
17796 | | case 1: |
17797 | | // op: opcode |
17798 | | return 0; |
17799 | | case 3: |
17800 | | // op: funct7 |
17801 | | return 25; |
17802 | | case 2: |
17803 | | // op: funct3 |
17804 | | return 12; |
17805 | | case 5: |
17806 | | // op: rs2 |
17807 | | return 20; |
17808 | | case 4: |
17809 | | // op: rs1 |
17810 | | return 15; |
17811 | | case 0: |
17812 | | // op: rd |
17813 | | return 7; |
17814 | | } |
17815 | | break; |
17816 | | } |
17817 | | case RISCV::C_ADDI_HINT_IMM_ZERO: |
17818 | | case RISCV::C_NOT: |
17819 | | case RISCV::C_SEXT_B: |
17820 | | case RISCV::C_SEXT_H: |
17821 | | case RISCV::C_SLLI64_HINT: |
17822 | | case RISCV::C_SRAI64_HINT: |
17823 | | case RISCV::C_SRLI64_HINT: |
17824 | | case RISCV::C_ZEXT_B: |
17825 | | case RISCV::C_ZEXT_H: |
17826 | | case RISCV::C_ZEXT_W: { |
17827 | | switch (OpNum) { |
17828 | | case 1: |
17829 | | // op: rd |
17830 | | return 7; |
17831 | | } |
17832 | | break; |
17833 | | } |
17834 | | case RISCV::ADDI: |
17835 | | case RISCV::ADDIW: |
17836 | | case RISCV::ANDI: |
17837 | | case RISCV::CV_ELW: |
17838 | | case RISCV::FLD: |
17839 | | case RISCV::FLH: |
17840 | | case RISCV::FLW: |
17841 | | case RISCV::JALR: |
17842 | | case RISCV::LB: |
17843 | | case RISCV::LBU: |
17844 | | case RISCV::LD: |
17845 | | case RISCV::LH: |
17846 | | case RISCV::LHU: |
17847 | | case RISCV::LW: |
17848 | | case RISCV::LWU: |
17849 | | case RISCV::ORI: |
17850 | | case RISCV::SLTI: |
17851 | | case RISCV::SLTIU: |
17852 | | case RISCV::XORI: { |
17853 | | switch (OpNum) { |
17854 | | case 1: |
17855 | | // op: rs1 |
17856 | | return 15; |
17857 | | case 0: |
17858 | | // op: rd |
17859 | | return 7; |
17860 | | case 2: |
17861 | | // op: imm12 |
17862 | | return 20; |
17863 | | } |
17864 | | break; |
17865 | | } |
17866 | | case RISCV::CV_CLIP: |
17867 | | case RISCV::CV_CLIPU: { |
17868 | | switch (OpNum) { |
17869 | | case 1: |
17870 | | // op: rs1 |
17871 | | return 15; |
17872 | | case 0: |
17873 | | // op: rd |
17874 | | return 7; |
17875 | | case 2: |
17876 | | // op: imm5 |
17877 | | return 20; |
17878 | | } |
17879 | | break; |
17880 | | } |
17881 | | case RISCV::CV_ADD_SCI_B: |
17882 | | case RISCV::CV_ADD_SCI_H: |
17883 | | case RISCV::CV_AND_SCI_B: |
17884 | | case RISCV::CV_AND_SCI_H: |
17885 | | case RISCV::CV_AVGU_SCI_B: |
17886 | | case RISCV::CV_AVGU_SCI_H: |
17887 | | case RISCV::CV_AVG_SCI_B: |
17888 | | case RISCV::CV_AVG_SCI_H: |
17889 | | case RISCV::CV_CMPEQ_SCI_B: |
17890 | | case RISCV::CV_CMPEQ_SCI_H: |
17891 | | case RISCV::CV_CMPGEU_SCI_B: |
17892 | | case RISCV::CV_CMPGEU_SCI_H: |
17893 | | case RISCV::CV_CMPGE_SCI_B: |
17894 | | case RISCV::CV_CMPGE_SCI_H: |
17895 | | case RISCV::CV_CMPGTU_SCI_B: |
17896 | | case RISCV::CV_CMPGTU_SCI_H: |
17897 | | case RISCV::CV_CMPGT_SCI_B: |
17898 | | case RISCV::CV_CMPGT_SCI_H: |
17899 | | case RISCV::CV_CMPLEU_SCI_B: |
17900 | | case RISCV::CV_CMPLEU_SCI_H: |
17901 | | case RISCV::CV_CMPLE_SCI_B: |
17902 | | case RISCV::CV_CMPLE_SCI_H: |
17903 | | case RISCV::CV_CMPLTU_SCI_B: |
17904 | | case RISCV::CV_CMPLTU_SCI_H: |
17905 | | case RISCV::CV_CMPLT_SCI_B: |
17906 | | case RISCV::CV_CMPLT_SCI_H: |
17907 | | case RISCV::CV_CMPNE_SCI_B: |
17908 | | case RISCV::CV_CMPNE_SCI_H: |
17909 | | case RISCV::CV_DOTSP_SCI_B: |
17910 | | case RISCV::CV_DOTSP_SCI_H: |
17911 | | case RISCV::CV_DOTUP_SCI_B: |
17912 | | case RISCV::CV_DOTUP_SCI_H: |
17913 | | case RISCV::CV_DOTUSP_SCI_B: |
17914 | | case RISCV::CV_DOTUSP_SCI_H: |
17915 | | case RISCV::CV_EXTRACTU_B: |
17916 | | case RISCV::CV_EXTRACTU_H: |
17917 | | case RISCV::CV_EXTRACT_B: |
17918 | | case RISCV::CV_EXTRACT_H: |
17919 | | case RISCV::CV_MAXU_SCI_B: |
17920 | | case RISCV::CV_MAXU_SCI_H: |
17921 | | case RISCV::CV_MAX_SCI_B: |
17922 | | case RISCV::CV_MAX_SCI_H: |
17923 | | case RISCV::CV_MINU_SCI_B: |
17924 | | case RISCV::CV_MINU_SCI_H: |
17925 | | case RISCV::CV_MIN_SCI_B: |
17926 | | case RISCV::CV_MIN_SCI_H: |
17927 | | case RISCV::CV_OR_SCI_B: |
17928 | | case RISCV::CV_OR_SCI_H: |
17929 | | case RISCV::CV_SHUFFLEI0_SCI_B: |
17930 | | case RISCV::CV_SHUFFLEI1_SCI_B: |
17931 | | case RISCV::CV_SHUFFLEI2_SCI_B: |
17932 | | case RISCV::CV_SHUFFLEI3_SCI_B: |
17933 | | case RISCV::CV_SHUFFLE_SCI_H: |
17934 | | case RISCV::CV_SLL_SCI_B: |
17935 | | case RISCV::CV_SLL_SCI_H: |
17936 | | case RISCV::CV_SRA_SCI_B: |
17937 | | case RISCV::CV_SRA_SCI_H: |
17938 | | case RISCV::CV_SRL_SCI_B: |
17939 | | case RISCV::CV_SRL_SCI_H: |
17940 | | case RISCV::CV_SUB_SCI_B: |
17941 | | case RISCV::CV_SUB_SCI_H: |
17942 | | case RISCV::CV_XOR_SCI_B: |
17943 | | case RISCV::CV_XOR_SCI_H: { |
17944 | | switch (OpNum) { |
17945 | | case 1: |
17946 | | // op: rs1 |
17947 | | return 15; |
17948 | | case 0: |
17949 | | // op: rd |
17950 | | return 7; |
17951 | | case 2: |
17952 | | // op: imm6 |
17953 | | return 20; |
17954 | | } |
17955 | | break; |
17956 | | } |
17957 | | case RISCV::CV_BCLR: |
17958 | | case RISCV::CV_BITREV: |
17959 | | case RISCV::CV_BSET: |
17960 | | case RISCV::CV_EXTRACT: |
17961 | | case RISCV::CV_EXTRACTU: { |
17962 | | switch (OpNum) { |
17963 | | case 1: |
17964 | | // op: rs1 |
17965 | | return 15; |
17966 | | case 0: |
17967 | | // op: rd |
17968 | | return 7; |
17969 | | case 2: |
17970 | | // op: is3 |
17971 | | return 25; |
17972 | | case 3: |
17973 | | // op: is2 |
17974 | | return 20; |
17975 | | } |
17976 | | break; |
17977 | | } |
17978 | | case RISCV::TH_EXT: |
17979 | | case RISCV::TH_EXTU: { |
17980 | | switch (OpNum) { |
17981 | | case 1: |
17982 | | // op: rs1 |
17983 | | return 15; |
17984 | | case 0: |
17985 | | // op: rd |
17986 | | return 7; |
17987 | | case 2: |
17988 | | // op: msb |
17989 | | return 26; |
17990 | | case 3: |
17991 | | // op: lsb |
17992 | | return 20; |
17993 | | } |
17994 | | break; |
17995 | | } |
17996 | | case RISCV::AES64KS1I: { |
17997 | | switch (OpNum) { |
17998 | | case 1: |
17999 | | // op: rs1 |
18000 | | return 15; |
18001 | | case 0: |
18002 | | // op: rd |
18003 | | return 7; |
18004 | | case 2: |
18005 | | // op: rnum |
18006 | | return 20; |
18007 | | } |
18008 | | break; |
18009 | | } |
18010 | | case RISCV::BCLRI: |
18011 | | case RISCV::BEXTI: |
18012 | | case RISCV::BINVI: |
18013 | | case RISCV::BSETI: |
18014 | | case RISCV::RORI: |
18015 | | case RISCV::RORIW: |
18016 | | case RISCV::SLLI: |
18017 | | case RISCV::SLLIW: |
18018 | | case RISCV::SLLI_UW: |
18019 | | case RISCV::SRAI: |
18020 | | case RISCV::SRAIW: |
18021 | | case RISCV::SRLI: |
18022 | | case RISCV::SRLIW: |
18023 | | case RISCV::TH_SRRI: |
18024 | | case RISCV::TH_SRRIW: |
18025 | | case RISCV::TH_TST: { |
18026 | | switch (OpNum) { |
18027 | | case 1: |
18028 | | // op: rs1 |
18029 | | return 15; |
18030 | | case 0: |
18031 | | // op: rd |
18032 | | return 7; |
18033 | | case 2: |
18034 | | // op: shamt |
18035 | | return 20; |
18036 | | } |
18037 | | break; |
18038 | | } |
18039 | | case RISCV::VSETVLI: { |
18040 | | switch (OpNum) { |
18041 | | case 1: |
18042 | | // op: rs1 |
18043 | | return 15; |
18044 | | case 0: |
18045 | | // op: rd |
18046 | | return 7; |
18047 | | case 2: |
18048 | | // op: vtypei |
18049 | | return 20; |
18050 | | } |
18051 | | break; |
18052 | | } |
18053 | | case RISCV::AES64IM: |
18054 | | case RISCV::BREV8: |
18055 | | case RISCV::CLZ: |
18056 | | case RISCV::CLZW: |
18057 | | case RISCV::CPOP: |
18058 | | case RISCV::CPOPW: |
18059 | | case RISCV::CTZ: |
18060 | | case RISCV::CTZW: |
18061 | | case RISCV::CV_ABS: |
18062 | | case RISCV::CV_ABS_B: |
18063 | | case RISCV::CV_ABS_H: |
18064 | | case RISCV::CV_CLB: |
18065 | | case RISCV::CV_CNT: |
18066 | | case RISCV::CV_CPLXCONJ: |
18067 | | case RISCV::CV_EXTBS: |
18068 | | case RISCV::CV_EXTBZ: |
18069 | | case RISCV::CV_EXTHS: |
18070 | | case RISCV::CV_EXTHZ: |
18071 | | case RISCV::CV_FF1: |
18072 | | case RISCV::CV_FL1: |
18073 | | case RISCV::FCLASS_D: |
18074 | | case RISCV::FCLASS_D_IN32X: |
18075 | | case RISCV::FCLASS_D_INX: |
18076 | | case RISCV::FCLASS_H: |
18077 | | case RISCV::FCLASS_H_INX: |
18078 | | case RISCV::FCLASS_S: |
18079 | | case RISCV::FCLASS_S_INX: |
18080 | | case RISCV::FMVH_X_D: |
18081 | | case RISCV::FMV_D_X: |
18082 | | case RISCV::FMV_H_X: |
18083 | | case RISCV::FMV_W_X: |
18084 | | case RISCV::FMV_X_D: |
18085 | | case RISCV::FMV_X_H: |
18086 | | case RISCV::FMV_X_W: |
18087 | | case RISCV::FMV_X_W_FPR64: |
18088 | | case RISCV::HLVX_HU: |
18089 | | case RISCV::HLVX_WU: |
18090 | | case RISCV::HLV_B: |
18091 | | case RISCV::HLV_BU: |
18092 | | case RISCV::HLV_D: |
18093 | | case RISCV::HLV_H: |
18094 | | case RISCV::HLV_HU: |
18095 | | case RISCV::HLV_W: |
18096 | | case RISCV::HLV_WU: |
18097 | | case RISCV::LR_D: |
18098 | | case RISCV::LR_D_AQ: |
18099 | | case RISCV::LR_D_AQ_RL: |
18100 | | case RISCV::LR_D_RL: |
18101 | | case RISCV::LR_W: |
18102 | | case RISCV::LR_W_AQ: |
18103 | | case RISCV::LR_W_AQ_RL: |
18104 | | case RISCV::LR_W_RL: |
18105 | | case RISCV::MOPR0: |
18106 | | case RISCV::MOPR1: |
18107 | | case RISCV::MOPR2: |
18108 | | case RISCV::MOPR3: |
18109 | | case RISCV::MOPR4: |
18110 | | case RISCV::MOPR5: |
18111 | | case RISCV::MOPR6: |
18112 | | case RISCV::MOPR7: |
18113 | | case RISCV::MOPR8: |
18114 | | case RISCV::MOPR9: |
18115 | | case RISCV::MOPR10: |
18116 | | case RISCV::MOPR11: |
18117 | | case RISCV::MOPR12: |
18118 | | case RISCV::MOPR13: |
18119 | | case RISCV::MOPR14: |
18120 | | case RISCV::MOPR15: |
18121 | | case RISCV::MOPR16: |
18122 | | case RISCV::MOPR17: |
18123 | | case RISCV::MOPR18: |
18124 | | case RISCV::MOPR19: |
18125 | | case RISCV::MOPR20: |
18126 | | case RISCV::MOPR21: |
18127 | | case RISCV::MOPR22: |
18128 | | case RISCV::MOPR23: |
18129 | | case RISCV::MOPR24: |
18130 | | case RISCV::MOPR25: |
18131 | | case RISCV::MOPR26: |
18132 | | case RISCV::MOPR27: |
18133 | | case RISCV::MOPR28: |
18134 | | case RISCV::MOPR29: |
18135 | | case RISCV::MOPR30: |
18136 | | case RISCV::MOPR31: |
18137 | | case RISCV::ORC_B: |
18138 | | case RISCV::REV8_RV32: |
18139 | | case RISCV::REV8_RV64: |
18140 | | case RISCV::SEXT_B: |
18141 | | case RISCV::SEXT_H: |
18142 | | case RISCV::SHA256SIG0: |
18143 | | case RISCV::SHA256SIG1: |
18144 | | case RISCV::SHA256SUM0: |
18145 | | case RISCV::SHA256SUM1: |
18146 | | case RISCV::SHA512SIG0: |
18147 | | case RISCV::SHA512SIG1: |
18148 | | case RISCV::SHA512SUM0: |
18149 | | case RISCV::SHA512SUM1: |
18150 | | case RISCV::SM3P0: |
18151 | | case RISCV::SM3P1: |
18152 | | case RISCV::TH_FF0: |
18153 | | case RISCV::TH_FF1: |
18154 | | case RISCV::TH_REV: |
18155 | | case RISCV::TH_REVW: |
18156 | | case RISCV::TH_TSTNBZ: |
18157 | | case RISCV::UNZIP_RV32: |
18158 | | case RISCV::ZEXT_H_RV32: |
18159 | | case RISCV::ZEXT_H_RV64: |
18160 | | case RISCV::ZIP_RV32: { |
18161 | | switch (OpNum) { |
18162 | | case 1: |
18163 | | // op: rs1 |
18164 | | return 15; |
18165 | | case 0: |
18166 | | // op: rd |
18167 | | return 7; |
18168 | | } |
18169 | | break; |
18170 | | } |
18171 | | case RISCV::VLE8FF_V: |
18172 | | case RISCV::VLE8_V: |
18173 | | case RISCV::VLE16FF_V: |
18174 | | case RISCV::VLE16_V: |
18175 | | case RISCV::VLE32FF_V: |
18176 | | case RISCV::VLE32_V: |
18177 | | case RISCV::VLE64FF_V: |
18178 | | case RISCV::VLE64_V: |
18179 | | case RISCV::VLSEG2E8FF_V: |
18180 | | case RISCV::VLSEG2E8_V: |
18181 | | case RISCV::VLSEG2E16FF_V: |
18182 | | case RISCV::VLSEG2E16_V: |
18183 | | case RISCV::VLSEG2E32FF_V: |
18184 | | case RISCV::VLSEG2E32_V: |
18185 | | case RISCV::VLSEG2E64FF_V: |
18186 | | case RISCV::VLSEG2E64_V: |
18187 | | case RISCV::VLSEG3E8FF_V: |
18188 | | case RISCV::VLSEG3E8_V: |
18189 | | case RISCV::VLSEG3E16FF_V: |
18190 | | case RISCV::VLSEG3E16_V: |
18191 | | case RISCV::VLSEG3E32FF_V: |
18192 | | case RISCV::VLSEG3E32_V: |
18193 | | case RISCV::VLSEG3E64FF_V: |
18194 | | case RISCV::VLSEG3E64_V: |
18195 | | case RISCV::VLSEG4E8FF_V: |
18196 | | case RISCV::VLSEG4E8_V: |
18197 | | case RISCV::VLSEG4E16FF_V: |
18198 | | case RISCV::VLSEG4E16_V: |
18199 | | case RISCV::VLSEG4E32FF_V: |
18200 | | case RISCV::VLSEG4E32_V: |
18201 | | case RISCV::VLSEG4E64FF_V: |
18202 | | case RISCV::VLSEG4E64_V: |
18203 | | case RISCV::VLSEG5E8FF_V: |
18204 | | case RISCV::VLSEG5E8_V: |
18205 | | case RISCV::VLSEG5E16FF_V: |
18206 | | case RISCV::VLSEG5E16_V: |
18207 | | case RISCV::VLSEG5E32FF_V: |
18208 | | case RISCV::VLSEG5E32_V: |
18209 | | case RISCV::VLSEG5E64FF_V: |
18210 | | case RISCV::VLSEG5E64_V: |
18211 | | case RISCV::VLSEG6E8FF_V: |
18212 | | case RISCV::VLSEG6E8_V: |
18213 | | case RISCV::VLSEG6E16FF_V: |
18214 | | case RISCV::VLSEG6E16_V: |
18215 | | case RISCV::VLSEG6E32FF_V: |
18216 | | case RISCV::VLSEG6E32_V: |
18217 | | case RISCV::VLSEG6E64FF_V: |
18218 | | case RISCV::VLSEG6E64_V: |
18219 | | case RISCV::VLSEG7E8FF_V: |
18220 | | case RISCV::VLSEG7E8_V: |
18221 | | case RISCV::VLSEG7E16FF_V: |
18222 | | case RISCV::VLSEG7E16_V: |
18223 | | case RISCV::VLSEG7E32FF_V: |
18224 | | case RISCV::VLSEG7E32_V: |
18225 | | case RISCV::VLSEG7E64FF_V: |
18226 | | case RISCV::VLSEG7E64_V: |
18227 | | case RISCV::VLSEG8E8FF_V: |
18228 | | case RISCV::VLSEG8E8_V: |
18229 | | case RISCV::VLSEG8E16FF_V: |
18230 | | case RISCV::VLSEG8E16_V: |
18231 | | case RISCV::VLSEG8E32FF_V: |
18232 | | case RISCV::VLSEG8E32_V: |
18233 | | case RISCV::VLSEG8E64FF_V: |
18234 | | case RISCV::VLSEG8E64_V: { |
18235 | | switch (OpNum) { |
18236 | | case 1: |
18237 | | // op: rs1 |
18238 | | return 15; |
18239 | | case 0: |
18240 | | // op: vd |
18241 | | return 7; |
18242 | | case 2: |
18243 | | // op: vm |
18244 | | return 25; |
18245 | | } |
18246 | | break; |
18247 | | } |
18248 | | case RISCV::VFMV_V_F: |
18249 | | case RISCV::VL1RE8_V: |
18250 | | case RISCV::VL1RE16_V: |
18251 | | case RISCV::VL1RE32_V: |
18252 | | case RISCV::VL1RE64_V: |
18253 | | case RISCV::VL2RE8_V: |
18254 | | case RISCV::VL2RE16_V: |
18255 | | case RISCV::VL2RE32_V: |
18256 | | case RISCV::VL2RE64_V: |
18257 | | case RISCV::VL4RE8_V: |
18258 | | case RISCV::VL4RE16_V: |
18259 | | case RISCV::VL4RE32_V: |
18260 | | case RISCV::VL4RE64_V: |
18261 | | case RISCV::VL8RE8_V: |
18262 | | case RISCV::VL8RE16_V: |
18263 | | case RISCV::VL8RE32_V: |
18264 | | case RISCV::VL8RE64_V: |
18265 | | case RISCV::VLM_V: |
18266 | | case RISCV::VMV_V_X: { |
18267 | | switch (OpNum) { |
18268 | | case 1: |
18269 | | // op: rs1 |
18270 | | return 15; |
18271 | | case 0: |
18272 | | // op: vd |
18273 | | return 7; |
18274 | | } |
18275 | | break; |
18276 | | } |
18277 | | case RISCV::VSE8_V: |
18278 | | case RISCV::VSE16_V: |
18279 | | case RISCV::VSE32_V: |
18280 | | case RISCV::VSE64_V: |
18281 | | case RISCV::VSSEG2E8_V: |
18282 | | case RISCV::VSSEG2E16_V: |
18283 | | case RISCV::VSSEG2E32_V: |
18284 | | case RISCV::VSSEG2E64_V: |
18285 | | case RISCV::VSSEG3E8_V: |
18286 | | case RISCV::VSSEG3E16_V: |
18287 | | case RISCV::VSSEG3E32_V: |
18288 | | case RISCV::VSSEG3E64_V: |
18289 | | case RISCV::VSSEG4E8_V: |
18290 | | case RISCV::VSSEG4E16_V: |
18291 | | case RISCV::VSSEG4E32_V: |
18292 | | case RISCV::VSSEG4E64_V: |
18293 | | case RISCV::VSSEG5E8_V: |
18294 | | case RISCV::VSSEG5E16_V: |
18295 | | case RISCV::VSSEG5E32_V: |
18296 | | case RISCV::VSSEG5E64_V: |
18297 | | case RISCV::VSSEG6E8_V: |
18298 | | case RISCV::VSSEG6E16_V: |
18299 | | case RISCV::VSSEG6E32_V: |
18300 | | case RISCV::VSSEG6E64_V: |
18301 | | case RISCV::VSSEG7E8_V: |
18302 | | case RISCV::VSSEG7E16_V: |
18303 | | case RISCV::VSSEG7E32_V: |
18304 | | case RISCV::VSSEG7E64_V: |
18305 | | case RISCV::VSSEG8E8_V: |
18306 | | case RISCV::VSSEG8E16_V: |
18307 | | case RISCV::VSSEG8E32_V: |
18308 | | case RISCV::VSSEG8E64_V: { |
18309 | | switch (OpNum) { |
18310 | | case 1: |
18311 | | // op: rs1 |
18312 | | return 15; |
18313 | | case 0: |
18314 | | // op: vs3 |
18315 | | return 7; |
18316 | | case 2: |
18317 | | // op: vm |
18318 | | return 25; |
18319 | | } |
18320 | | break; |
18321 | | } |
18322 | | case RISCV::VS1R_V: |
18323 | | case RISCV::VS2R_V: |
18324 | | case RISCV::VS4R_V: |
18325 | | case RISCV::VS8R_V: |
18326 | | case RISCV::VSM_V: { |
18327 | | switch (OpNum) { |
18328 | | case 1: |
18329 | | // op: rs1 |
18330 | | return 15; |
18331 | | case 0: |
18332 | | // op: vs3 |
18333 | | return 7; |
18334 | | } |
18335 | | break; |
18336 | | } |
18337 | | case RISCV::FCVTMOD_W_D: |
18338 | | case RISCV::FCVT_BF16_S: |
18339 | | case RISCV::FCVT_D_H: |
18340 | | case RISCV::FCVT_D_H_IN32X: |
18341 | | case RISCV::FCVT_D_H_INX: |
18342 | | case RISCV::FCVT_D_L: |
18343 | | case RISCV::FCVT_D_LU: |
18344 | | case RISCV::FCVT_D_LU_INX: |
18345 | | case RISCV::FCVT_D_L_INX: |
18346 | | case RISCV::FCVT_D_S: |
18347 | | case RISCV::FCVT_D_S_IN32X: |
18348 | | case RISCV::FCVT_D_S_INX: |
18349 | | case RISCV::FCVT_D_W: |
18350 | | case RISCV::FCVT_D_WU: |
18351 | | case RISCV::FCVT_D_WU_IN32X: |
18352 | | case RISCV::FCVT_D_WU_INX: |
18353 | | case RISCV::FCVT_D_W_IN32X: |
18354 | | case RISCV::FCVT_D_W_INX: |
18355 | | case RISCV::FCVT_H_D: |
18356 | | case RISCV::FCVT_H_D_IN32X: |
18357 | | case RISCV::FCVT_H_D_INX: |
18358 | | case RISCV::FCVT_H_L: |
18359 | | case RISCV::FCVT_H_LU: |
18360 | | case RISCV::FCVT_H_LU_INX: |
18361 | | case RISCV::FCVT_H_L_INX: |
18362 | | case RISCV::FCVT_H_S: |
18363 | | case RISCV::FCVT_H_S_INX: |
18364 | | case RISCV::FCVT_H_W: |
18365 | | case RISCV::FCVT_H_WU: |
18366 | | case RISCV::FCVT_H_WU_INX: |
18367 | | case RISCV::FCVT_H_W_INX: |
18368 | | case RISCV::FCVT_LU_D: |
18369 | | case RISCV::FCVT_LU_D_INX: |
18370 | | case RISCV::FCVT_LU_H: |
18371 | | case RISCV::FCVT_LU_H_INX: |
18372 | | case RISCV::FCVT_LU_S: |
18373 | | case RISCV::FCVT_LU_S_INX: |
18374 | | case RISCV::FCVT_L_D: |
18375 | | case RISCV::FCVT_L_D_INX: |
18376 | | case RISCV::FCVT_L_H: |
18377 | | case RISCV::FCVT_L_H_INX: |
18378 | | case RISCV::FCVT_L_S: |
18379 | | case RISCV::FCVT_L_S_INX: |
18380 | | case RISCV::FCVT_S_BF16: |
18381 | | case RISCV::FCVT_S_D: |
18382 | | case RISCV::FCVT_S_D_IN32X: |
18383 | | case RISCV::FCVT_S_D_INX: |
18384 | | case RISCV::FCVT_S_H: |
18385 | | case RISCV::FCVT_S_H_INX: |
18386 | | case RISCV::FCVT_S_L: |
18387 | | case RISCV::FCVT_S_LU: |
18388 | | case RISCV::FCVT_S_LU_INX: |
18389 | | case RISCV::FCVT_S_L_INX: |
18390 | | case RISCV::FCVT_S_W: |
18391 | | case RISCV::FCVT_S_WU: |
18392 | | case RISCV::FCVT_S_WU_INX: |
18393 | | case RISCV::FCVT_S_W_INX: |
18394 | | case RISCV::FCVT_WU_D: |
18395 | | case RISCV::FCVT_WU_D_IN32X: |
18396 | | case RISCV::FCVT_WU_D_INX: |
18397 | | case RISCV::FCVT_WU_H: |
18398 | | case RISCV::FCVT_WU_H_INX: |
18399 | | case RISCV::FCVT_WU_S: |
18400 | | case RISCV::FCVT_WU_S_INX: |
18401 | | case RISCV::FCVT_W_D: |
18402 | | case RISCV::FCVT_W_D_IN32X: |
18403 | | case RISCV::FCVT_W_D_INX: |
18404 | | case RISCV::FCVT_W_H: |
18405 | | case RISCV::FCVT_W_H_INX: |
18406 | | case RISCV::FCVT_W_S: |
18407 | | case RISCV::FCVT_W_S_INX: |
18408 | | case RISCV::FROUNDNX_D: |
18409 | | case RISCV::FROUNDNX_H: |
18410 | | case RISCV::FROUNDNX_S: |
18411 | | case RISCV::FROUND_D: |
18412 | | case RISCV::FROUND_H: |
18413 | | case RISCV::FROUND_S: |
18414 | | case RISCV::FSQRT_D: |
18415 | | case RISCV::FSQRT_D_IN32X: |
18416 | | case RISCV::FSQRT_D_INX: |
18417 | | case RISCV::FSQRT_H: |
18418 | | case RISCV::FSQRT_H_INX: |
18419 | | case RISCV::FSQRT_S: |
18420 | | case RISCV::FSQRT_S_INX: { |
18421 | | switch (OpNum) { |
18422 | | case 1: |
18423 | | // op: rs1 |
18424 | | return 15; |
18425 | | case 2: |
18426 | | // op: frm |
18427 | | return 12; |
18428 | | case 0: |
18429 | | // op: rd |
18430 | | return 7; |
18431 | | } |
18432 | | break; |
18433 | | } |
18434 | | case RISCV::C_ADD: { |
18435 | | switch (OpNum) { |
18436 | | case 1: |
18437 | | // op: rs1 |
18438 | | return 7; |
18439 | | case 2: |
18440 | | // op: rs2 |
18441 | | return 2; |
18442 | | } |
18443 | | break; |
18444 | | } |
18445 | | case RISCV::HFENCE_GVMA: |
18446 | | case RISCV::HFENCE_VVMA: |
18447 | | case RISCV::HINVAL_GVMA: |
18448 | | case RISCV::HINVAL_VVMA: |
18449 | | case RISCV::SFENCE_VMA: |
18450 | | case RISCV::SINVAL_VMA: |
18451 | | case RISCV::TH_SFENCE_VMAS: { |
18452 | | switch (OpNum) { |
18453 | | case 1: |
18454 | | // op: rs2 |
18455 | | return 20; |
18456 | | case 0: |
18457 | | // op: rs1 |
18458 | | return 15; |
18459 | | } |
18460 | | break; |
18461 | | } |
18462 | | case RISCV::TH_LDD: |
18463 | | case RISCV::TH_LWD: |
18464 | | case RISCV::TH_LWUD: |
18465 | | case RISCV::TH_SDD: |
18466 | | case RISCV::TH_SWD: { |
18467 | | switch (OpNum) { |
18468 | | case 1: |
18469 | | // op: rs2 |
18470 | | return 20; |
18471 | | case 2: |
18472 | | // op: rs1 |
18473 | | return 15; |
18474 | | case 0: |
18475 | | // op: rd |
18476 | | return 7; |
18477 | | case 3: |
18478 | | // op: uimm2 |
18479 | | return 25; |
18480 | | } |
18481 | | break; |
18482 | | } |
18483 | | case RISCV::VC_I: |
18484 | | case RISCV::VC_X: { |
18485 | | switch (OpNum) { |
18486 | | case 1: |
18487 | | // op: rs2 |
18488 | | return 20; |
18489 | | case 3: |
18490 | | // op: rs1 |
18491 | | return 15; |
18492 | | case 2: |
18493 | | // op: rd |
18494 | | return 7; |
18495 | | case 0: |
18496 | | // op: funct6_lo2 |
18497 | | return 26; |
18498 | | } |
18499 | | break; |
18500 | | } |
18501 | | case RISCV::CM_MVA01S: |
18502 | | case RISCV::CM_MVSA01: { |
18503 | | switch (OpNum) { |
18504 | | case 1: |
18505 | | // op: rs2 |
18506 | | return 2; |
18507 | | case 0: |
18508 | | // op: rs1 |
18509 | | return 7; |
18510 | | } |
18511 | | break; |
18512 | | } |
18513 | | case RISCV::C_MV_HINT: { |
18514 | | switch (OpNum) { |
18515 | | case 1: |
18516 | | // op: rs2 |
18517 | | return 2; |
18518 | | } |
18519 | | break; |
18520 | | } |
18521 | | case RISCV::VSETIVLI: { |
18522 | | switch (OpNum) { |
18523 | | case 1: |
18524 | | // op: uimm |
18525 | | return 15; |
18526 | | case 0: |
18527 | | // op: rd |
18528 | | return 7; |
18529 | | case 2: |
18530 | | // op: vtypei |
18531 | | return 20; |
18532 | | } |
18533 | | break; |
18534 | | } |
18535 | | case RISCV::VMV_V_V: { |
18536 | | switch (OpNum) { |
18537 | | case 1: |
18538 | | // op: vs1 |
18539 | | return 15; |
18540 | | case 0: |
18541 | | // op: vd |
18542 | | return 7; |
18543 | | } |
18544 | | break; |
18545 | | } |
18546 | | case RISCV::VBREV8_V: |
18547 | | case RISCV::VBREV_V: |
18548 | | case RISCV::VCLZ_V: |
18549 | | case RISCV::VCPOP_M: |
18550 | | case RISCV::VCPOP_V: |
18551 | | case RISCV::VCTZ_V: |
18552 | | case RISCV::VFCLASS_V: |
18553 | | case RISCV::VFCVT_F_XU_V: |
18554 | | case RISCV::VFCVT_F_X_V: |
18555 | | case RISCV::VFCVT_RTZ_XU_F_V: |
18556 | | case RISCV::VFCVT_RTZ_X_F_V: |
18557 | | case RISCV::VFCVT_XU_F_V: |
18558 | | case RISCV::VFCVT_X_F_V: |
18559 | | case RISCV::VFIRST_M: |
18560 | | case RISCV::VFNCVTBF16_F_F_W: |
18561 | | case RISCV::VFNCVT_F_F_W: |
18562 | | case RISCV::VFNCVT_F_XU_W: |
18563 | | case RISCV::VFNCVT_F_X_W: |
18564 | | case RISCV::VFNCVT_ROD_F_F_W: |
18565 | | case RISCV::VFNCVT_RTZ_XU_F_W: |
18566 | | case RISCV::VFNCVT_RTZ_X_F_W: |
18567 | | case RISCV::VFNCVT_XU_F_W: |
18568 | | case RISCV::VFNCVT_X_F_W: |
18569 | | case RISCV::VFREC7_V: |
18570 | | case RISCV::VFRSQRT7_V: |
18571 | | case RISCV::VFSQRT_V: |
18572 | | case RISCV::VFWCVTBF16_F_F_V: |
18573 | | case RISCV::VFWCVT_F_F_V: |
18574 | | case RISCV::VFWCVT_F_XU_V: |
18575 | | case RISCV::VFWCVT_F_X_V: |
18576 | | case RISCV::VFWCVT_RTZ_XU_F_V: |
18577 | | case RISCV::VFWCVT_RTZ_X_F_V: |
18578 | | case RISCV::VFWCVT_XU_F_V: |
18579 | | case RISCV::VFWCVT_X_F_V: |
18580 | | case RISCV::VIOTA_M: |
18581 | | case RISCV::VMSBF_M: |
18582 | | case RISCV::VMSIF_M: |
18583 | | case RISCV::VMSOF_M: |
18584 | | case RISCV::VREV8_V: |
18585 | | case RISCV::VSEXT_VF2: |
18586 | | case RISCV::VSEXT_VF4: |
18587 | | case RISCV::VSEXT_VF8: |
18588 | | case RISCV::VZEXT_VF2: |
18589 | | case RISCV::VZEXT_VF4: |
18590 | | case RISCV::VZEXT_VF8: { |
18591 | | switch (OpNum) { |
18592 | | case 1: |
18593 | | // op: vs2 |
18594 | | return 20; |
18595 | | case 0: |
18596 | | // op: vd |
18597 | | return 7; |
18598 | | case 2: |
18599 | | // op: vm |
18600 | | return 25; |
18601 | | } |
18602 | | break; |
18603 | | } |
18604 | | case RISCV::VAESDF_VS: |
18605 | | case RISCV::VAESDF_VV: |
18606 | | case RISCV::VAESDM_VS: |
18607 | | case RISCV::VAESDM_VV: |
18608 | | case RISCV::VAESEF_VS: |
18609 | | case RISCV::VAESEF_VV: |
18610 | | case RISCV::VAESEM_VS: |
18611 | | case RISCV::VAESEM_VV: |
18612 | | case RISCV::VAESZ_VS: |
18613 | | case RISCV::VFMV_F_S: |
18614 | | case RISCV::VGMUL_VV: |
18615 | | case RISCV::VMV1R_V: |
18616 | | case RISCV::VMV2R_V: |
18617 | | case RISCV::VMV4R_V: |
18618 | | case RISCV::VMV8R_V: |
18619 | | case RISCV::VMV_X_S: |
18620 | | case RISCV::VSM4R_VS: |
18621 | | case RISCV::VSM4R_VV: { |
18622 | | switch (OpNum) { |
18623 | | case 1: |
18624 | | // op: vs2 |
18625 | | return 20; |
18626 | | case 0: |
18627 | | // op: vd |
18628 | | return 7; |
18629 | | } |
18630 | | break; |
18631 | | } |
18632 | | case RISCV::VADD_VI: |
18633 | | case RISCV::VAND_VI: |
18634 | | case RISCV::VMSEQ_VI: |
18635 | | case RISCV::VMSGTU_VI: |
18636 | | case RISCV::VMSGT_VI: |
18637 | | case RISCV::VMSLEU_VI: |
18638 | | case RISCV::VMSLE_VI: |
18639 | | case RISCV::VMSNE_VI: |
18640 | | case RISCV::VNCLIPU_WI: |
18641 | | case RISCV::VNCLIP_WI: |
18642 | | case RISCV::VNSRA_WI: |
18643 | | case RISCV::VNSRL_WI: |
18644 | | case RISCV::VOR_VI: |
18645 | | case RISCV::VRGATHER_VI: |
18646 | | case RISCV::VROR_VI: |
18647 | | case RISCV::VRSUB_VI: |
18648 | | case RISCV::VSADDU_VI: |
18649 | | case RISCV::VSADD_VI: |
18650 | | case RISCV::VSLIDEDOWN_VI: |
18651 | | case RISCV::VSLIDEUP_VI: |
18652 | | case RISCV::VSLL_VI: |
18653 | | case RISCV::VSRA_VI: |
18654 | | case RISCV::VSRL_VI: |
18655 | | case RISCV::VSSRA_VI: |
18656 | | case RISCV::VSSRL_VI: |
18657 | | case RISCV::VWSLL_VI: |
18658 | | case RISCV::VXOR_VI: { |
18659 | | switch (OpNum) { |
18660 | | case 1: |
18661 | | // op: vs2 |
18662 | | return 20; |
18663 | | case 2: |
18664 | | // op: imm |
18665 | | return 15; |
18666 | | case 0: |
18667 | | // op: vd |
18668 | | return 7; |
18669 | | case 3: |
18670 | | // op: vm |
18671 | | return 25; |
18672 | | } |
18673 | | break; |
18674 | | } |
18675 | | case RISCV::VADC_VIM: |
18676 | | case RISCV::VAESKF1_VI: |
18677 | | case RISCV::VAESKF2_VI: |
18678 | | case RISCV::VMADC_VI: |
18679 | | case RISCV::VMADC_VIM: |
18680 | | case RISCV::VMERGE_VIM: |
18681 | | case RISCV::VSM3C_VI: |
18682 | | case RISCV::VSM4K_VI: { |
18683 | | switch (OpNum) { |
18684 | | case 1: |
18685 | | // op: vs2 |
18686 | | return 20; |
18687 | | case 2: |
18688 | | // op: imm |
18689 | | return 15; |
18690 | | case 0: |
18691 | | // op: vd |
18692 | | return 7; |
18693 | | } |
18694 | | break; |
18695 | | } |
18696 | | case RISCV::VAADDU_VX: |
18697 | | case RISCV::VAADD_VX: |
18698 | | case RISCV::VADD_VX: |
18699 | | case RISCV::VANDN_VX: |
18700 | | case RISCV::VAND_VX: |
18701 | | case RISCV::VASUBU_VX: |
18702 | | case RISCV::VASUB_VX: |
18703 | | case RISCV::VCLMULH_VX: |
18704 | | case RISCV::VCLMUL_VX: |
18705 | | case RISCV::VDIVU_VX: |
18706 | | case RISCV::VDIV_VX: |
18707 | | case RISCV::VFADD_VF: |
18708 | | case RISCV::VFDIV_VF: |
18709 | | case RISCV::VFMAX_VF: |
18710 | | case RISCV::VFMIN_VF: |
18711 | | case RISCV::VFMUL_VF: |
18712 | | case RISCV::VFNRCLIP_XU_F_QF: |
18713 | | case RISCV::VFNRCLIP_X_F_QF: |
18714 | | case RISCV::VFRDIV_VF: |
18715 | | case RISCV::VFRSUB_VF: |
18716 | | case RISCV::VFSGNJN_VF: |
18717 | | case RISCV::VFSGNJX_VF: |
18718 | | case RISCV::VFSGNJ_VF: |
18719 | | case RISCV::VFSLIDE1DOWN_VF: |
18720 | | case RISCV::VFSLIDE1UP_VF: |
18721 | | case RISCV::VFSUB_VF: |
18722 | | case RISCV::VFWADD_VF: |
18723 | | case RISCV::VFWADD_WF: |
18724 | | case RISCV::VFWMUL_VF: |
18725 | | case RISCV::VFWSUB_VF: |
18726 | | case RISCV::VFWSUB_WF: |
18727 | | case RISCV::VMAXU_VX: |
18728 | | case RISCV::VMAX_VX: |
18729 | | case RISCV::VMFEQ_VF: |
18730 | | case RISCV::VMFGE_VF: |
18731 | | case RISCV::VMFGT_VF: |
18732 | | case RISCV::VMFLE_VF: |
18733 | | case RISCV::VMFLT_VF: |
18734 | | case RISCV::VMFNE_VF: |
18735 | | case RISCV::VMINU_VX: |
18736 | | case RISCV::VMIN_VX: |
18737 | | case RISCV::VMSEQ_VX: |
18738 | | case RISCV::VMSGTU_VX: |
18739 | | case RISCV::VMSGT_VX: |
18740 | | case RISCV::VMSLEU_VX: |
18741 | | case RISCV::VMSLE_VX: |
18742 | | case RISCV::VMSLTU_VX: |
18743 | | case RISCV::VMSLT_VX: |
18744 | | case RISCV::VMSNE_VX: |
18745 | | case RISCV::VMULHSU_VX: |
18746 | | case RISCV::VMULHU_VX: |
18747 | | case RISCV::VMULH_VX: |
18748 | | case RISCV::VMUL_VX: |
18749 | | case RISCV::VNCLIPU_WX: |
18750 | | case RISCV::VNCLIP_WX: |
18751 | | case RISCV::VNSRA_WX: |
18752 | | case RISCV::VNSRL_WX: |
18753 | | case RISCV::VOR_VX: |
18754 | | case RISCV::VREMU_VX: |
18755 | | case RISCV::VREM_VX: |
18756 | | case RISCV::VRGATHER_VX: |
18757 | | case RISCV::VROL_VX: |
18758 | | case RISCV::VROR_VX: |
18759 | | case RISCV::VRSUB_VX: |
18760 | | case RISCV::VSADDU_VX: |
18761 | | case RISCV::VSADD_VX: |
18762 | | case RISCV::VSLIDE1DOWN_VX: |
18763 | | case RISCV::VSLIDE1UP_VX: |
18764 | | case RISCV::VSLIDEDOWN_VX: |
18765 | | case RISCV::VSLIDEUP_VX: |
18766 | | case RISCV::VSLL_VX: |
18767 | | case RISCV::VSMUL_VX: |
18768 | | case RISCV::VSRA_VX: |
18769 | | case RISCV::VSRL_VX: |
18770 | | case RISCV::VSSRA_VX: |
18771 | | case RISCV::VSSRL_VX: |
18772 | | case RISCV::VSSUBU_VX: |
18773 | | case RISCV::VSSUB_VX: |
18774 | | case RISCV::VSUB_VX: |
18775 | | case RISCV::VWADDU_VX: |
18776 | | case RISCV::VWADDU_WX: |
18777 | | case RISCV::VWADD_VX: |
18778 | | case RISCV::VWADD_WX: |
18779 | | case RISCV::VWMULSU_VX: |
18780 | | case RISCV::VWMULU_VX: |
18781 | | case RISCV::VWMUL_VX: |
18782 | | case RISCV::VWSLL_VX: |
18783 | | case RISCV::VWSUBU_VX: |
18784 | | case RISCV::VWSUBU_WX: |
18785 | | case RISCV::VWSUB_VX: |
18786 | | case RISCV::VWSUB_WX: |
18787 | | case RISCV::VXOR_VX: { |
18788 | | switch (OpNum) { |
18789 | | case 1: |
18790 | | // op: vs2 |
18791 | | return 20; |
18792 | | case 2: |
18793 | | // op: rs1 |
18794 | | return 15; |
18795 | | case 0: |
18796 | | // op: vd |
18797 | | return 7; |
18798 | | case 3: |
18799 | | // op: vm |
18800 | | return 25; |
18801 | | } |
18802 | | break; |
18803 | | } |
18804 | | case RISCV::VADC_VXM: |
18805 | | case RISCV::VFMERGE_VFM: |
18806 | | case RISCV::VMADC_VX: |
18807 | | case RISCV::VMADC_VXM: |
18808 | | case RISCV::VMERGE_VXM: |
18809 | | case RISCV::VMSBC_VX: |
18810 | | case RISCV::VMSBC_VXM: |
18811 | | case RISCV::VSBC_VXM: { |
18812 | | switch (OpNum) { |
18813 | | case 1: |
18814 | | // op: vs2 |
18815 | | return 20; |
18816 | | case 2: |
18817 | | // op: rs1 |
18818 | | return 15; |
18819 | | case 0: |
18820 | | // op: vd |
18821 | | return 7; |
18822 | | } |
18823 | | break; |
18824 | | } |
18825 | | case RISCV::VAADDU_VV: |
18826 | | case RISCV::VAADD_VV: |
18827 | | case RISCV::VADD_VV: |
18828 | | case RISCV::VANDN_VV: |
18829 | | case RISCV::VAND_VV: |
18830 | | case RISCV::VASUBU_VV: |
18831 | | case RISCV::VASUB_VV: |
18832 | | case RISCV::VCLMULH_VV: |
18833 | | case RISCV::VCLMUL_VV: |
18834 | | case RISCV::VDIVU_VV: |
18835 | | case RISCV::VDIV_VV: |
18836 | | case RISCV::VFADD_VV: |
18837 | | case RISCV::VFDIV_VV: |
18838 | | case RISCV::VFMAX_VV: |
18839 | | case RISCV::VFMIN_VV: |
18840 | | case RISCV::VFMUL_VV: |
18841 | | case RISCV::VFREDMAX_VS: |
18842 | | case RISCV::VFREDMIN_VS: |
18843 | | case RISCV::VFREDOSUM_VS: |
18844 | | case RISCV::VFREDUSUM_VS: |
18845 | | case RISCV::VFSGNJN_VV: |
18846 | | case RISCV::VFSGNJX_VV: |
18847 | | case RISCV::VFSGNJ_VV: |
18848 | | case RISCV::VFSUB_VV: |
18849 | | case RISCV::VFWADD_VV: |
18850 | | case RISCV::VFWADD_WV: |
18851 | | case RISCV::VFWMUL_VV: |
18852 | | case RISCV::VFWREDOSUM_VS: |
18853 | | case RISCV::VFWREDUSUM_VS: |
18854 | | case RISCV::VFWSUB_VV: |
18855 | | case RISCV::VFWSUB_WV: |
18856 | | case RISCV::VMAXU_VV: |
18857 | | case RISCV::VMAX_VV: |
18858 | | case RISCV::VMFEQ_VV: |
18859 | | case RISCV::VMFLE_VV: |
18860 | | case RISCV::VMFLT_VV: |
18861 | | case RISCV::VMFNE_VV: |
18862 | | case RISCV::VMINU_VV: |
18863 | | case RISCV::VMIN_VV: |
18864 | | case RISCV::VMSEQ_VV: |
18865 | | case RISCV::VMSLEU_VV: |
18866 | | case RISCV::VMSLE_VV: |
18867 | | case RISCV::VMSLTU_VV: |
18868 | | case RISCV::VMSLT_VV: |
18869 | | case RISCV::VMSNE_VV: |
18870 | | case RISCV::VMULHSU_VV: |
18871 | | case RISCV::VMULHU_VV: |
18872 | | case RISCV::VMULH_VV: |
18873 | | case RISCV::VMUL_VV: |
18874 | | case RISCV::VNCLIPU_WV: |
18875 | | case RISCV::VNCLIP_WV: |
18876 | | case RISCV::VNSRA_WV: |
18877 | | case RISCV::VNSRL_WV: |
18878 | | case RISCV::VOR_VV: |
18879 | | case RISCV::VREDAND_VS: |
18880 | | case RISCV::VREDMAXU_VS: |
18881 | | case RISCV::VREDMAX_VS: |
18882 | | case RISCV::VREDMINU_VS: |
18883 | | case RISCV::VREDMIN_VS: |
18884 | | case RISCV::VREDOR_VS: |
18885 | | case RISCV::VREDSUM_VS: |
18886 | | case RISCV::VREDXOR_VS: |
18887 | | case RISCV::VREMU_VV: |
18888 | | case RISCV::VREM_VV: |
18889 | | case RISCV::VRGATHEREI16_VV: |
18890 | | case RISCV::VRGATHER_VV: |
18891 | | case RISCV::VROL_VV: |
18892 | | case RISCV::VROR_VV: |
18893 | | case RISCV::VSADDU_VV: |
18894 | | case RISCV::VSADD_VV: |
18895 | | case RISCV::VSLL_VV: |
18896 | | case RISCV::VSMUL_VV: |
18897 | | case RISCV::VSRA_VV: |
18898 | | case RISCV::VSRL_VV: |
18899 | | case RISCV::VSSRA_VV: |
18900 | | case RISCV::VSSRL_VV: |
18901 | | case RISCV::VSSUBU_VV: |
18902 | | case RISCV::VSSUB_VV: |
18903 | | case RISCV::VSUB_VV: |
18904 | | case RISCV::VWADDU_VV: |
18905 | | case RISCV::VWADDU_WV: |
18906 | | case RISCV::VWADD_VV: |
18907 | | case RISCV::VWADD_WV: |
18908 | | case RISCV::VWMULSU_VV: |
18909 | | case RISCV::VWMULU_VV: |
18910 | | case RISCV::VWMUL_VV: |
18911 | | case RISCV::VWREDSUMU_VS: |
18912 | | case RISCV::VWREDSUM_VS: |
18913 | | case RISCV::VWSLL_VV: |
18914 | | case RISCV::VWSUBU_VV: |
18915 | | case RISCV::VWSUBU_WV: |
18916 | | case RISCV::VWSUB_VV: |
18917 | | case RISCV::VWSUB_WV: |
18918 | | case RISCV::VXOR_VV: { |
18919 | | switch (OpNum) { |
18920 | | case 1: |
18921 | | // op: vs2 |
18922 | | return 20; |
18923 | | case 2: |
18924 | | // op: vs1 |
18925 | | return 15; |
18926 | | case 0: |
18927 | | // op: vd |
18928 | | return 7; |
18929 | | case 3: |
18930 | | // op: vm |
18931 | | return 25; |
18932 | | } |
18933 | | break; |
18934 | | } |
18935 | | case RISCV::VADC_VVM: |
18936 | | case RISCV::VCOMPRESS_VM: |
18937 | | case RISCV::VGHSH_VV: |
18938 | | case RISCV::VMADC_VV: |
18939 | | case RISCV::VMADC_VVM: |
18940 | | case RISCV::VMANDN_MM: |
18941 | | case RISCV::VMAND_MM: |
18942 | | case RISCV::VMERGE_VVM: |
18943 | | case RISCV::VMNAND_MM: |
18944 | | case RISCV::VMNOR_MM: |
18945 | | case RISCV::VMORN_MM: |
18946 | | case RISCV::VMOR_MM: |
18947 | | case RISCV::VMSBC_VV: |
18948 | | case RISCV::VMSBC_VVM: |
18949 | | case RISCV::VMXNOR_MM: |
18950 | | case RISCV::VMXOR_MM: |
18951 | | case RISCV::VSBC_VVM: |
18952 | | case RISCV::VSHA2CH_VV: |
18953 | | case RISCV::VSHA2CL_VV: |
18954 | | case RISCV::VSHA2MS_VV: |
18955 | | case RISCV::VSM3ME_VV: { |
18956 | | switch (OpNum) { |
18957 | | case 1: |
18958 | | // op: vs2 |
18959 | | return 20; |
18960 | | case 2: |
18961 | | // op: vs1 |
18962 | | return 15; |
18963 | | case 0: |
18964 | | // op: vd |
18965 | | return 7; |
18966 | | } |
18967 | | break; |
18968 | | } |
18969 | | case RISCV::C_ADDI_NOP: { |
18970 | | switch (OpNum) { |
18971 | | case 2: |
18972 | | // op: imm |
18973 | | return 12; |
18974 | | case 1: |
18975 | | // op: rd |
18976 | | return 7; |
18977 | | } |
18978 | | break; |
18979 | | } |
18980 | | case RISCV::C_FLDSP: |
18981 | | case RISCV::C_FLWSP: |
18982 | | case RISCV::C_LDSP: |
18983 | | case RISCV::C_LWSP: { |
18984 | | switch (OpNum) { |
18985 | | case 2: |
18986 | | // op: imm |
18987 | | return 2; |
18988 | | case 0: |
18989 | | // op: rd |
18990 | | return 7; |
18991 | | } |
18992 | | break; |
18993 | | } |
18994 | | case RISCV::C_ADDI: |
18995 | | case RISCV::C_ADDIW: |
18996 | | case RISCV::C_SLLI: { |
18997 | | switch (OpNum) { |
18998 | | case 2: |
18999 | | // op: imm |
19000 | | return 2; |
19001 | | case 1: |
19002 | | // op: rd |
19003 | | return 7; |
19004 | | } |
19005 | | break; |
19006 | | } |
19007 | | case RISCV::C_ANDI: |
19008 | | case RISCV::C_SRAI: |
19009 | | case RISCV::C_SRLI: { |
19010 | | switch (OpNum) { |
19011 | | case 2: |
19012 | | // op: imm |
19013 | | return 2; |
19014 | | case 1: |
19015 | | // op: rs1 |
19016 | | return 7; |
19017 | | } |
19018 | | break; |
19019 | | } |
19020 | | case RISCV::C_ADDI16SP: |
19021 | | case RISCV::C_SLLI_HINT: { |
19022 | | switch (OpNum) { |
19023 | | case 2: |
19024 | | // op: imm |
19025 | | return 2; |
19026 | | } |
19027 | | break; |
19028 | | } |
19029 | | case RISCV::C_ADDI4SPN: { |
19030 | | switch (OpNum) { |
19031 | | case 2: |
19032 | | // op: imm |
19033 | | return 5; |
19034 | | case 0: |
19035 | | // op: rd |
19036 | | return 2; |
19037 | | } |
19038 | | break; |
19039 | | } |
19040 | | case RISCV::C_FSDSP: |
19041 | | case RISCV::C_FSWSP: |
19042 | | case RISCV::C_SDSP: |
19043 | | case RISCV::C_SWSP: { |
19044 | | switch (OpNum) { |
19045 | | case 2: |
19046 | | // op: imm |
19047 | | return 7; |
19048 | | case 0: |
19049 | | // op: rs2 |
19050 | | return 2; |
19051 | | } |
19052 | | break; |
19053 | | } |
19054 | | case RISCV::CV_BEQIMM: |
19055 | | case RISCV::CV_BNEIMM: { |
19056 | | switch (OpNum) { |
19057 | | case 2: |
19058 | | // op: imm12 |
19059 | | return 7; |
19060 | | case 0: |
19061 | | // op: rs1 |
19062 | | return 15; |
19063 | | case 1: |
19064 | | // op: imm5 |
19065 | | return 20; |
19066 | | } |
19067 | | break; |
19068 | | } |
19069 | | case RISCV::FSD: |
19070 | | case RISCV::FSH: |
19071 | | case RISCV::FSW: |
19072 | | case RISCV::SB: |
19073 | | case RISCV::SD: |
19074 | | case RISCV::SH: |
19075 | | case RISCV::SW: { |
19076 | | switch (OpNum) { |
19077 | | case 2: |
19078 | | // op: imm12 |
19079 | | return 7; |
19080 | | case 0: |
19081 | | // op: rs2 |
19082 | | return 20; |
19083 | | case 1: |
19084 | | // op: rs1 |
19085 | | return 15; |
19086 | | } |
19087 | | break; |
19088 | | } |
19089 | | case RISCV::BEQ: |
19090 | | case RISCV::BGE: |
19091 | | case RISCV::BGEU: |
19092 | | case RISCV::BLT: |
19093 | | case RISCV::BLTU: |
19094 | | case RISCV::BNE: { |
19095 | | switch (OpNum) { |
19096 | | case 2: |
19097 | | // op: imm12 |
19098 | | return 7; |
19099 | | case 1: |
19100 | | // op: rs2 |
19101 | | return 20; |
19102 | | case 0: |
19103 | | // op: rs1 |
19104 | | return 15; |
19105 | | } |
19106 | | break; |
19107 | | } |
19108 | | case RISCV::CSRRC: |
19109 | | case RISCV::CSRRCI: |
19110 | | case RISCV::CSRRS: |
19111 | | case RISCV::CSRRSI: |
19112 | | case RISCV::CSRRW: |
19113 | | case RISCV::CSRRWI: { |
19114 | | switch (OpNum) { |
19115 | | case 2: |
19116 | | // op: rs1 |
19117 | | return 15; |
19118 | | case 0: |
19119 | | // op: rd |
19120 | | return 7; |
19121 | | case 1: |
19122 | | // op: imm12 |
19123 | | return 20; |
19124 | | } |
19125 | | break; |
19126 | | } |
19127 | | case RISCV::CV_LBU_ri_inc: |
19128 | | case RISCV::CV_LB_ri_inc: |
19129 | | case RISCV::CV_LHU_ri_inc: |
19130 | | case RISCV::CV_LH_ri_inc: |
19131 | | case RISCV::CV_LW_ri_inc: { |
19132 | | switch (OpNum) { |
19133 | | case 2: |
19134 | | // op: rs1 |
19135 | | return 15; |
19136 | | case 0: |
19137 | | // op: rd |
19138 | | return 7; |
19139 | | case 3: |
19140 | | // op: imm12 |
19141 | | return 20; |
19142 | | } |
19143 | | break; |
19144 | | } |
19145 | | case RISCV::TH_LBIA: |
19146 | | case RISCV::TH_LBIB: |
19147 | | case RISCV::TH_LBUIA: |
19148 | | case RISCV::TH_LBUIB: |
19149 | | case RISCV::TH_LDIA: |
19150 | | case RISCV::TH_LDIB: |
19151 | | case RISCV::TH_LHIA: |
19152 | | case RISCV::TH_LHIB: |
19153 | | case RISCV::TH_LHUIA: |
19154 | | case RISCV::TH_LHUIB: |
19155 | | case RISCV::TH_LWIA: |
19156 | | case RISCV::TH_LWIB: |
19157 | | case RISCV::TH_LWUIA: |
19158 | | case RISCV::TH_LWUIB: { |
19159 | | switch (OpNum) { |
19160 | | case 2: |
19161 | | // op: rs1 |
19162 | | return 15; |
19163 | | case 0: |
19164 | | // op: rd |
19165 | | return 7; |
19166 | | case 3: |
19167 | | // op: simm5 |
19168 | | return 20; |
19169 | | case 4: |
19170 | | // op: uimm2 |
19171 | | return 25; |
19172 | | } |
19173 | | break; |
19174 | | } |
19175 | | case RISCV::CV_INSERT_B: |
19176 | | case RISCV::CV_INSERT_H: |
19177 | | case RISCV::CV_SDOTSP_SCI_B: |
19178 | | case RISCV::CV_SDOTSP_SCI_H: |
19179 | | case RISCV::CV_SDOTUP_SCI_B: |
19180 | | case RISCV::CV_SDOTUP_SCI_H: |
19181 | | case RISCV::CV_SDOTUSP_SCI_B: |
19182 | | case RISCV::CV_SDOTUSP_SCI_H: { |
19183 | | switch (OpNum) { |
19184 | | case 2: |
19185 | | // op: rs1 |
19186 | | return 15; |
19187 | | case 1: |
19188 | | // op: rd |
19189 | | return 7; |
19190 | | case 3: |
19191 | | // op: imm6 |
19192 | | return 20; |
19193 | | } |
19194 | | break; |
19195 | | } |
19196 | | case RISCV::CV_INSERT: { |
19197 | | switch (OpNum) { |
19198 | | case 2: |
19199 | | // op: rs1 |
19200 | | return 15; |
19201 | | case 1: |
19202 | | // op: rd |
19203 | | return 7; |
19204 | | case 3: |
19205 | | // op: is3 |
19206 | | return 25; |
19207 | | case 4: |
19208 | | // op: is2 |
19209 | | return 20; |
19210 | | } |
19211 | | break; |
19212 | | } |
19213 | | case RISCV::TH_SBIA: |
19214 | | case RISCV::TH_SBIB: |
19215 | | case RISCV::TH_SDIA: |
19216 | | case RISCV::TH_SDIB: |
19217 | | case RISCV::TH_SHIA: |
19218 | | case RISCV::TH_SHIB: |
19219 | | case RISCV::TH_SWIA: |
19220 | | case RISCV::TH_SWIB: { |
19221 | | switch (OpNum) { |
19222 | | case 2: |
19223 | | // op: rs1 |
19224 | | return 15; |
19225 | | case 1: |
19226 | | // op: rd |
19227 | | return 7; |
19228 | | case 3: |
19229 | | // op: simm5 |
19230 | | return 20; |
19231 | | case 4: |
19232 | | // op: uimm2 |
19233 | | return 25; |
19234 | | } |
19235 | | break; |
19236 | | } |
19237 | | case RISCV::VFMV_S_F: |
19238 | | case RISCV::VMV_S_X: { |
19239 | | switch (OpNum) { |
19240 | | case 2: |
19241 | | // op: rs1 |
19242 | | return 15; |
19243 | | case 1: |
19244 | | // op: vd |
19245 | | return 7; |
19246 | | } |
19247 | | break; |
19248 | | } |
19249 | | case RISCV::AES32DSI: |
19250 | | case RISCV::AES32DSMI: |
19251 | | case RISCV::AES32ESI: |
19252 | | case RISCV::AES32ESMI: |
19253 | | case RISCV::SM4ED: |
19254 | | case RISCV::SM4KS: { |
19255 | | switch (OpNum) { |
19256 | | case 2: |
19257 | | // op: rs2 |
19258 | | return 20; |
19259 | | case 1: |
19260 | | // op: rs1 |
19261 | | return 15; |
19262 | | case 0: |
19263 | | // op: rd |
19264 | | return 7; |
19265 | | case 3: |
19266 | | // op: bs |
19267 | | return 30; |
19268 | | } |
19269 | | break; |
19270 | | } |
19271 | | case RISCV::CV_ADDN: |
19272 | | case RISCV::CV_ADDRN: |
19273 | | case RISCV::CV_ADDUN: |
19274 | | case RISCV::CV_ADDURN: |
19275 | | case RISCV::CV_MULHHSN: |
19276 | | case RISCV::CV_MULHHSRN: |
19277 | | case RISCV::CV_MULHHUN: |
19278 | | case RISCV::CV_MULHHURN: |
19279 | | case RISCV::CV_MULSN: |
19280 | | case RISCV::CV_MULSRN: |
19281 | | case RISCV::CV_MULUN: |
19282 | | case RISCV::CV_MULURN: |
19283 | | case RISCV::CV_SUBN: |
19284 | | case RISCV::CV_SUBRN: |
19285 | | case RISCV::CV_SUBUN: |
19286 | | case RISCV::CV_SUBURN: { |
19287 | | switch (OpNum) { |
19288 | | case 2: |
19289 | | // op: rs2 |
19290 | | return 20; |
19291 | | case 1: |
19292 | | // op: rs1 |
19293 | | return 15; |
19294 | | case 0: |
19295 | | // op: rd |
19296 | | return 7; |
19297 | | case 3: |
19298 | | // op: imm5 |
19299 | | return 25; |
19300 | | } |
19301 | | break; |
19302 | | } |
19303 | | case RISCV::TH_ADDSL: |
19304 | | case RISCV::TH_FLRD: |
19305 | | case RISCV::TH_FLRW: |
19306 | | case RISCV::TH_FLURD: |
19307 | | case RISCV::TH_FLURW: |
19308 | | case RISCV::TH_FSRD: |
19309 | | case RISCV::TH_FSRW: |
19310 | | case RISCV::TH_FSURD: |
19311 | | case RISCV::TH_FSURW: |
19312 | | case RISCV::TH_LRB: |
19313 | | case RISCV::TH_LRBU: |
19314 | | case RISCV::TH_LRD: |
19315 | | case RISCV::TH_LRH: |
19316 | | case RISCV::TH_LRHU: |
19317 | | case RISCV::TH_LRW: |
19318 | | case RISCV::TH_LRWU: |
19319 | | case RISCV::TH_LURB: |
19320 | | case RISCV::TH_LURBU: |
19321 | | case RISCV::TH_LURD: |
19322 | | case RISCV::TH_LURH: |
19323 | | case RISCV::TH_LURHU: |
19324 | | case RISCV::TH_LURW: |
19325 | | case RISCV::TH_LURWU: |
19326 | | case RISCV::TH_SRB: |
19327 | | case RISCV::TH_SRD: |
19328 | | case RISCV::TH_SRH: |
19329 | | case RISCV::TH_SRW: |
19330 | | case RISCV::TH_SURB: |
19331 | | case RISCV::TH_SURD: |
19332 | | case RISCV::TH_SURH: |
19333 | | case RISCV::TH_SURW: { |
19334 | | switch (OpNum) { |
19335 | | case 2: |
19336 | | // op: rs2 |
19337 | | return 20; |
19338 | | case 1: |
19339 | | // op: rs1 |
19340 | | return 15; |
19341 | | case 0: |
19342 | | // op: rd |
19343 | | return 7; |
19344 | | case 3: |
19345 | | // op: uimm2 |
19346 | | return 25; |
19347 | | } |
19348 | | break; |
19349 | | } |
19350 | | case RISCV::ADD: |
19351 | | case RISCV::ADDW: |
19352 | | case RISCV::ADD_UW: |
19353 | | case RISCV::AES64DS: |
19354 | | case RISCV::AES64DSM: |
19355 | | case RISCV::AES64ES: |
19356 | | case RISCV::AES64ESM: |
19357 | | case RISCV::AES64KS2: |
19358 | | case RISCV::AMOADD_D: |
19359 | | case RISCV::AMOADD_D_AQ: |
19360 | | case RISCV::AMOADD_D_AQ_RL: |
19361 | | case RISCV::AMOADD_D_RL: |
19362 | | case RISCV::AMOADD_W: |
19363 | | case RISCV::AMOADD_W_AQ: |
19364 | | case RISCV::AMOADD_W_AQ_RL: |
19365 | | case RISCV::AMOADD_W_RL: |
19366 | | case RISCV::AMOAND_D: |
19367 | | case RISCV::AMOAND_D_AQ: |
19368 | | case RISCV::AMOAND_D_AQ_RL: |
19369 | | case RISCV::AMOAND_D_RL: |
19370 | | case RISCV::AMOAND_W: |
19371 | | case RISCV::AMOAND_W_AQ: |
19372 | | case RISCV::AMOAND_W_AQ_RL: |
19373 | | case RISCV::AMOAND_W_RL: |
19374 | | case RISCV::AMOMAXU_D: |
19375 | | case RISCV::AMOMAXU_D_AQ: |
19376 | | case RISCV::AMOMAXU_D_AQ_RL: |
19377 | | case RISCV::AMOMAXU_D_RL: |
19378 | | case RISCV::AMOMAXU_W: |
19379 | | case RISCV::AMOMAXU_W_AQ: |
19380 | | case RISCV::AMOMAXU_W_AQ_RL: |
19381 | | case RISCV::AMOMAXU_W_RL: |
19382 | | case RISCV::AMOMAX_D: |
19383 | | case RISCV::AMOMAX_D_AQ: |
19384 | | case RISCV::AMOMAX_D_AQ_RL: |
19385 | | case RISCV::AMOMAX_D_RL: |
19386 | | case RISCV::AMOMAX_W: |
19387 | | case RISCV::AMOMAX_W_AQ: |
19388 | | case RISCV::AMOMAX_W_AQ_RL: |
19389 | | case RISCV::AMOMAX_W_RL: |
19390 | | case RISCV::AMOMINU_D: |
19391 | | case RISCV::AMOMINU_D_AQ: |
19392 | | case RISCV::AMOMINU_D_AQ_RL: |
19393 | | case RISCV::AMOMINU_D_RL: |
19394 | | case RISCV::AMOMINU_W: |
19395 | | case RISCV::AMOMINU_W_AQ: |
19396 | | case RISCV::AMOMINU_W_AQ_RL: |
19397 | | case RISCV::AMOMINU_W_RL: |
19398 | | case RISCV::AMOMIN_D: |
19399 | | case RISCV::AMOMIN_D_AQ: |
19400 | | case RISCV::AMOMIN_D_AQ_RL: |
19401 | | case RISCV::AMOMIN_D_RL: |
19402 | | case RISCV::AMOMIN_W: |
19403 | | case RISCV::AMOMIN_W_AQ: |
19404 | | case RISCV::AMOMIN_W_AQ_RL: |
19405 | | case RISCV::AMOMIN_W_RL: |
19406 | | case RISCV::AMOOR_D: |
19407 | | case RISCV::AMOOR_D_AQ: |
19408 | | case RISCV::AMOOR_D_AQ_RL: |
19409 | | case RISCV::AMOOR_D_RL: |
19410 | | case RISCV::AMOOR_W: |
19411 | | case RISCV::AMOOR_W_AQ: |
19412 | | case RISCV::AMOOR_W_AQ_RL: |
19413 | | case RISCV::AMOOR_W_RL: |
19414 | | case RISCV::AMOSWAP_D: |
19415 | | case RISCV::AMOSWAP_D_AQ: |
19416 | | case RISCV::AMOSWAP_D_AQ_RL: |
19417 | | case RISCV::AMOSWAP_D_RL: |
19418 | | case RISCV::AMOSWAP_W: |
19419 | | case RISCV::AMOSWAP_W_AQ: |
19420 | | case RISCV::AMOSWAP_W_AQ_RL: |
19421 | | case RISCV::AMOSWAP_W_RL: |
19422 | | case RISCV::AMOXOR_D: |
19423 | | case RISCV::AMOXOR_D_AQ: |
19424 | | case RISCV::AMOXOR_D_AQ_RL: |
19425 | | case RISCV::AMOXOR_D_RL: |
19426 | | case RISCV::AMOXOR_W: |
19427 | | case RISCV::AMOXOR_W_AQ: |
19428 | | case RISCV::AMOXOR_W_AQ_RL: |
19429 | | case RISCV::AMOXOR_W_RL: |
19430 | | case RISCV::AND: |
19431 | | case RISCV::ANDN: |
19432 | | case RISCV::BCLR: |
19433 | | case RISCV::BEXT: |
19434 | | case RISCV::BINV: |
19435 | | case RISCV::BSET: |
19436 | | case RISCV::CLMUL: |
19437 | | case RISCV::CLMULH: |
19438 | | case RISCV::CLMULR: |
19439 | | case RISCV::CV_ADD_B: |
19440 | | case RISCV::CV_ADD_DIV2: |
19441 | | case RISCV::CV_ADD_DIV4: |
19442 | | case RISCV::CV_ADD_DIV8: |
19443 | | case RISCV::CV_ADD_H: |
19444 | | case RISCV::CV_ADD_SC_B: |
19445 | | case RISCV::CV_ADD_SC_H: |
19446 | | case RISCV::CV_AND_B: |
19447 | | case RISCV::CV_AND_H: |
19448 | | case RISCV::CV_AND_SC_B: |
19449 | | case RISCV::CV_AND_SC_H: |
19450 | | case RISCV::CV_AVGU_B: |
19451 | | case RISCV::CV_AVGU_H: |
19452 | | case RISCV::CV_AVGU_SC_B: |
19453 | | case RISCV::CV_AVGU_SC_H: |
19454 | | case RISCV::CV_AVG_B: |
19455 | | case RISCV::CV_AVG_H: |
19456 | | case RISCV::CV_AVG_SC_B: |
19457 | | case RISCV::CV_AVG_SC_H: |
19458 | | case RISCV::CV_BCLRR: |
19459 | | case RISCV::CV_BSETR: |
19460 | | case RISCV::CV_CLIPR: |
19461 | | case RISCV::CV_CLIPUR: |
19462 | | case RISCV::CV_CMPEQ_B: |
19463 | | case RISCV::CV_CMPEQ_H: |
19464 | | case RISCV::CV_CMPEQ_SC_B: |
19465 | | case RISCV::CV_CMPEQ_SC_H: |
19466 | | case RISCV::CV_CMPGEU_B: |
19467 | | case RISCV::CV_CMPGEU_H: |
19468 | | case RISCV::CV_CMPGEU_SC_B: |
19469 | | case RISCV::CV_CMPGEU_SC_H: |
19470 | | case RISCV::CV_CMPGE_B: |
19471 | | case RISCV::CV_CMPGE_H: |
19472 | | case RISCV::CV_CMPGE_SC_B: |
19473 | | case RISCV::CV_CMPGE_SC_H: |
19474 | | case RISCV::CV_CMPGTU_B: |
19475 | | case RISCV::CV_CMPGTU_H: |
19476 | | case RISCV::CV_CMPGTU_SC_B: |
19477 | | case RISCV::CV_CMPGTU_SC_H: |
19478 | | case RISCV::CV_CMPGT_B: |
19479 | | case RISCV::CV_CMPGT_H: |
19480 | | case RISCV::CV_CMPGT_SC_B: |
19481 | | case RISCV::CV_CMPGT_SC_H: |
19482 | | case RISCV::CV_CMPLEU_B: |
19483 | | case RISCV::CV_CMPLEU_H: |
19484 | | case RISCV::CV_CMPLEU_SC_B: |
19485 | | case RISCV::CV_CMPLEU_SC_H: |
19486 | | case RISCV::CV_CMPLE_B: |
19487 | | case RISCV::CV_CMPLE_H: |
19488 | | case RISCV::CV_CMPLE_SC_B: |
19489 | | case RISCV::CV_CMPLE_SC_H: |
19490 | | case RISCV::CV_CMPLTU_B: |
19491 | | case RISCV::CV_CMPLTU_H: |
19492 | | case RISCV::CV_CMPLTU_SC_B: |
19493 | | case RISCV::CV_CMPLTU_SC_H: |
19494 | | case RISCV::CV_CMPLT_B: |
19495 | | case RISCV::CV_CMPLT_H: |
19496 | | case RISCV::CV_CMPLT_SC_B: |
19497 | | case RISCV::CV_CMPLT_SC_H: |
19498 | | case RISCV::CV_CMPNE_B: |
19499 | | case RISCV::CV_CMPNE_H: |
19500 | | case RISCV::CV_CMPNE_SC_B: |
19501 | | case RISCV::CV_CMPNE_SC_H: |
19502 | | case RISCV::CV_DOTSP_B: |
19503 | | case RISCV::CV_DOTSP_H: |
19504 | | case RISCV::CV_DOTSP_SC_B: |
19505 | | case RISCV::CV_DOTSP_SC_H: |
19506 | | case RISCV::CV_DOTUP_B: |
19507 | | case RISCV::CV_DOTUP_H: |
19508 | | case RISCV::CV_DOTUP_SC_B: |
19509 | | case RISCV::CV_DOTUP_SC_H: |
19510 | | case RISCV::CV_DOTUSP_B: |
19511 | | case RISCV::CV_DOTUSP_H: |
19512 | | case RISCV::CV_DOTUSP_SC_B: |
19513 | | case RISCV::CV_DOTUSP_SC_H: |
19514 | | case RISCV::CV_EXTRACTR: |
19515 | | case RISCV::CV_EXTRACTUR: |
19516 | | case RISCV::CV_MAX: |
19517 | | case RISCV::CV_MAXU: |
19518 | | case RISCV::CV_MAXU_B: |
19519 | | case RISCV::CV_MAXU_H: |
19520 | | case RISCV::CV_MAXU_SC_B: |
19521 | | case RISCV::CV_MAXU_SC_H: |
19522 | | case RISCV::CV_MAX_B: |
19523 | | case RISCV::CV_MAX_H: |
19524 | | case RISCV::CV_MAX_SC_B: |
19525 | | case RISCV::CV_MAX_SC_H: |
19526 | | case RISCV::CV_MIN: |
19527 | | case RISCV::CV_MINU: |
19528 | | case RISCV::CV_MINU_B: |
19529 | | case RISCV::CV_MINU_H: |
19530 | | case RISCV::CV_MINU_SC_B: |
19531 | | case RISCV::CV_MINU_SC_H: |
19532 | | case RISCV::CV_MIN_B: |
19533 | | case RISCV::CV_MIN_H: |
19534 | | case RISCV::CV_MIN_SC_B: |
19535 | | case RISCV::CV_MIN_SC_H: |
19536 | | case RISCV::CV_OR_B: |
19537 | | case RISCV::CV_OR_H: |
19538 | | case RISCV::CV_OR_SC_B: |
19539 | | case RISCV::CV_OR_SC_H: |
19540 | | case RISCV::CV_PACK: |
19541 | | case RISCV::CV_PACK_H: |
19542 | | case RISCV::CV_ROR: |
19543 | | case RISCV::CV_SHUFFLE_B: |
19544 | | case RISCV::CV_SHUFFLE_H: |
19545 | | case RISCV::CV_SLET: |
19546 | | case RISCV::CV_SLETU: |
19547 | | case RISCV::CV_SLL_B: |
19548 | | case RISCV::CV_SLL_H: |
19549 | | case RISCV::CV_SLL_SC_B: |
19550 | | case RISCV::CV_SLL_SC_H: |
19551 | | case RISCV::CV_SRA_B: |
19552 | | case RISCV::CV_SRA_H: |
19553 | | case RISCV::CV_SRA_SC_B: |
19554 | | case RISCV::CV_SRA_SC_H: |
19555 | | case RISCV::CV_SRL_B: |
19556 | | case RISCV::CV_SRL_H: |
19557 | | case RISCV::CV_SRL_SC_B: |
19558 | | case RISCV::CV_SRL_SC_H: |
19559 | | case RISCV::CV_SUBROTMJ: |
19560 | | case RISCV::CV_SUBROTMJ_DIV2: |
19561 | | case RISCV::CV_SUBROTMJ_DIV4: |
19562 | | case RISCV::CV_SUBROTMJ_DIV8: |
19563 | | case RISCV::CV_SUB_B: |
19564 | | case RISCV::CV_SUB_DIV2: |
19565 | | case RISCV::CV_SUB_DIV4: |
19566 | | case RISCV::CV_SUB_DIV8: |
19567 | | case RISCV::CV_SUB_H: |
19568 | | case RISCV::CV_SUB_SC_B: |
19569 | | case RISCV::CV_SUB_SC_H: |
19570 | | case RISCV::CV_XOR_B: |
19571 | | case RISCV::CV_XOR_H: |
19572 | | case RISCV::CV_XOR_SC_B: |
19573 | | case RISCV::CV_XOR_SC_H: |
19574 | | case RISCV::CZERO_EQZ: |
19575 | | case RISCV::CZERO_NEZ: |
19576 | | case RISCV::DIV: |
19577 | | case RISCV::DIVU: |
19578 | | case RISCV::DIVUW: |
19579 | | case RISCV::DIVW: |
19580 | | case RISCV::FEQ_D: |
19581 | | case RISCV::FEQ_D_IN32X: |
19582 | | case RISCV::FEQ_D_INX: |
19583 | | case RISCV::FEQ_H: |
19584 | | case RISCV::FEQ_H_INX: |
19585 | | case RISCV::FEQ_S: |
19586 | | case RISCV::FEQ_S_INX: |
19587 | | case RISCV::FLEQ_D: |
19588 | | case RISCV::FLEQ_H: |
19589 | | case RISCV::FLEQ_S: |
19590 | | case RISCV::FLE_D: |
19591 | | case RISCV::FLE_D_IN32X: |
19592 | | case RISCV::FLE_D_INX: |
19593 | | case RISCV::FLE_H: |
19594 | | case RISCV::FLE_H_INX: |
19595 | | case RISCV::FLE_S: |
19596 | | case RISCV::FLE_S_INX: |
19597 | | case RISCV::FLTQ_D: |
19598 | | case RISCV::FLTQ_H: |
19599 | | case RISCV::FLTQ_S: |
19600 | | case RISCV::FLT_D: |
19601 | | case RISCV::FLT_D_IN32X: |
19602 | | case RISCV::FLT_D_INX: |
19603 | | case RISCV::FLT_H: |
19604 | | case RISCV::FLT_H_INX: |
19605 | | case RISCV::FLT_S: |
19606 | | case RISCV::FLT_S_INX: |
19607 | | case RISCV::FMAXM_D: |
19608 | | case RISCV::FMAXM_H: |
19609 | | case RISCV::FMAXM_S: |
19610 | | case RISCV::FMAX_D: |
19611 | | case RISCV::FMAX_D_IN32X: |
19612 | | case RISCV::FMAX_D_INX: |
19613 | | case RISCV::FMAX_H: |
19614 | | case RISCV::FMAX_H_INX: |
19615 | | case RISCV::FMAX_S: |
19616 | | case RISCV::FMAX_S_INX: |
19617 | | case RISCV::FMINM_D: |
19618 | | case RISCV::FMINM_H: |
19619 | | case RISCV::FMINM_S: |
19620 | | case RISCV::FMIN_D: |
19621 | | case RISCV::FMIN_D_IN32X: |
19622 | | case RISCV::FMIN_D_INX: |
19623 | | case RISCV::FMIN_H: |
19624 | | case RISCV::FMIN_H_INX: |
19625 | | case RISCV::FMIN_S: |
19626 | | case RISCV::FMIN_S_INX: |
19627 | | case RISCV::FMVP_D_X: |
19628 | | case RISCV::FSGNJN_D: |
19629 | | case RISCV::FSGNJN_D_IN32X: |
19630 | | case RISCV::FSGNJN_D_INX: |
19631 | | case RISCV::FSGNJN_H: |
19632 | | case RISCV::FSGNJN_H_INX: |
19633 | | case RISCV::FSGNJN_S: |
19634 | | case RISCV::FSGNJN_S_INX: |
19635 | | case RISCV::FSGNJX_D: |
19636 | | case RISCV::FSGNJX_D_IN32X: |
19637 | | case RISCV::FSGNJX_D_INX: |
19638 | | case RISCV::FSGNJX_H: |
19639 | | case RISCV::FSGNJX_H_INX: |
19640 | | case RISCV::FSGNJX_S: |
19641 | | case RISCV::FSGNJX_S_INX: |
19642 | | case RISCV::FSGNJ_D: |
19643 | | case RISCV::FSGNJ_D_IN32X: |
19644 | | case RISCV::FSGNJ_D_INX: |
19645 | | case RISCV::FSGNJ_H: |
19646 | | case RISCV::FSGNJ_H_INX: |
19647 | | case RISCV::FSGNJ_S: |
19648 | | case RISCV::FSGNJ_S_INX: |
19649 | | case RISCV::MAX: |
19650 | | case RISCV::MAXU: |
19651 | | case RISCV::MIN: |
19652 | | case RISCV::MINU: |
19653 | | case RISCV::MOPRR0: |
19654 | | case RISCV::MOPRR1: |
19655 | | case RISCV::MOPRR2: |
19656 | | case RISCV::MOPRR3: |
19657 | | case RISCV::MOPRR4: |
19658 | | case RISCV::MOPRR5: |
19659 | | case RISCV::MOPRR6: |
19660 | | case RISCV::MOPRR7: |
19661 | | case RISCV::MUL: |
19662 | | case RISCV::MULH: |
19663 | | case RISCV::MULHSU: |
19664 | | case RISCV::MULHU: |
19665 | | case RISCV::MULW: |
19666 | | case RISCV::OR: |
19667 | | case RISCV::ORN: |
19668 | | case RISCV::PACK: |
19669 | | case RISCV::PACKH: |
19670 | | case RISCV::PACKW: |
19671 | | case RISCV::REM: |
19672 | | case RISCV::REMU: |
19673 | | case RISCV::REMUW: |
19674 | | case RISCV::REMW: |
19675 | | case RISCV::ROL: |
19676 | | case RISCV::ROLW: |
19677 | | case RISCV::ROR: |
19678 | | case RISCV::RORW: |
19679 | | case RISCV::SC_D: |
19680 | | case RISCV::SC_D_AQ: |
19681 | | case RISCV::SC_D_AQ_RL: |
19682 | | case RISCV::SC_D_RL: |
19683 | | case RISCV::SC_W: |
19684 | | case RISCV::SC_W_AQ: |
19685 | | case RISCV::SC_W_AQ_RL: |
19686 | | case RISCV::SC_W_RL: |
19687 | | case RISCV::SH1ADD: |
19688 | | case RISCV::SH1ADD_UW: |
19689 | | case RISCV::SH2ADD: |
19690 | | case RISCV::SH2ADD_UW: |
19691 | | case RISCV::SH3ADD: |
19692 | | case RISCV::SH3ADD_UW: |
19693 | | case RISCV::SHA512SIG0H: |
19694 | | case RISCV::SHA512SIG0L: |
19695 | | case RISCV::SHA512SIG1H: |
19696 | | case RISCV::SHA512SIG1L: |
19697 | | case RISCV::SHA512SUM0R: |
19698 | | case RISCV::SHA512SUM1R: |
19699 | | case RISCV::SLL: |
19700 | | case RISCV::SLLW: |
19701 | | case RISCV::SLT: |
19702 | | case RISCV::SLTU: |
19703 | | case RISCV::SRA: |
19704 | | case RISCV::SRAW: |
19705 | | case RISCV::SRL: |
19706 | | case RISCV::SRLW: |
19707 | | case RISCV::SSAMOSWAP_D: |
19708 | | case RISCV::SSAMOSWAP_D_AQ: |
19709 | | case RISCV::SSAMOSWAP_D_AQ_RL: |
19710 | | case RISCV::SSAMOSWAP_D_RL: |
19711 | | case RISCV::SSAMOSWAP_W: |
19712 | | case RISCV::SSAMOSWAP_W_AQ: |
19713 | | case RISCV::SSAMOSWAP_W_AQ_RL: |
19714 | | case RISCV::SSAMOSWAP_W_RL: |
19715 | | case RISCV::SUB: |
19716 | | case RISCV::SUBW: |
19717 | | case RISCV::VFWMACC_4x4x4: |
19718 | | case RISCV::VQMACCSU_2x8x2: |
19719 | | case RISCV::VQMACCSU_4x8x4: |
19720 | | case RISCV::VQMACCUS_2x8x2: |
19721 | | case RISCV::VQMACCUS_4x8x4: |
19722 | | case RISCV::VQMACCU_2x8x2: |
19723 | | case RISCV::VQMACCU_4x8x4: |
19724 | | case RISCV::VQMACC_2x8x2: |
19725 | | case RISCV::VQMACC_4x8x4: |
19726 | | case RISCV::VSETVL: |
19727 | | case RISCV::VT_MASKC: |
19728 | | case RISCV::VT_MASKCN: |
19729 | | case RISCV::XNOR: |
19730 | | case RISCV::XOR: |
19731 | | case RISCV::XPERM4: |
19732 | | case RISCV::XPERM8: { |
19733 | | switch (OpNum) { |
19734 | | case 2: |
19735 | | // op: rs2 |
19736 | | return 20; |
19737 | | case 1: |
19738 | | // op: rs1 |
19739 | | return 15; |
19740 | | case 0: |
19741 | | // op: rd |
19742 | | return 7; |
19743 | | } |
19744 | | break; |
19745 | | } |
19746 | | case RISCV::VLSE8_V: |
19747 | | case RISCV::VLSE16_V: |
19748 | | case RISCV::VLSE32_V: |
19749 | | case RISCV::VLSE64_V: |
19750 | | case RISCV::VLSSEG2E8_V: |
19751 | | case RISCV::VLSSEG2E16_V: |
19752 | | case RISCV::VLSSEG2E32_V: |
19753 | | case RISCV::VLSSEG2E64_V: |
19754 | | case RISCV::VLSSEG3E8_V: |
19755 | | case RISCV::VLSSEG3E16_V: |
19756 | | case RISCV::VLSSEG3E32_V: |
19757 | | case RISCV::VLSSEG3E64_V: |
19758 | | case RISCV::VLSSEG4E8_V: |
19759 | | case RISCV::VLSSEG4E16_V: |
19760 | | case RISCV::VLSSEG4E32_V: |
19761 | | case RISCV::VLSSEG4E64_V: |
19762 | | case RISCV::VLSSEG5E8_V: |
19763 | | case RISCV::VLSSEG5E16_V: |
19764 | | case RISCV::VLSSEG5E32_V: |
19765 | | case RISCV::VLSSEG5E64_V: |
19766 | | case RISCV::VLSSEG6E8_V: |
19767 | | case RISCV::VLSSEG6E16_V: |
19768 | | case RISCV::VLSSEG6E32_V: |
19769 | | case RISCV::VLSSEG6E64_V: |
19770 | | case RISCV::VLSSEG7E8_V: |
19771 | | case RISCV::VLSSEG7E16_V: |
19772 | | case RISCV::VLSSEG7E32_V: |
19773 | | case RISCV::VLSSEG7E64_V: |
19774 | | case RISCV::VLSSEG8E8_V: |
19775 | | case RISCV::VLSSEG8E16_V: |
19776 | | case RISCV::VLSSEG8E32_V: |
19777 | | case RISCV::VLSSEG8E64_V: { |
19778 | | switch (OpNum) { |
19779 | | case 2: |
19780 | | // op: rs2 |
19781 | | return 20; |
19782 | | case 1: |
19783 | | // op: rs1 |
19784 | | return 15; |
19785 | | case 0: |
19786 | | // op: vd |
19787 | | return 7; |
19788 | | case 3: |
19789 | | // op: vm |
19790 | | return 25; |
19791 | | } |
19792 | | break; |
19793 | | } |
19794 | | case RISCV::VSSE8_V: |
19795 | | case RISCV::VSSE16_V: |
19796 | | case RISCV::VSSE32_V: |
19797 | | case RISCV::VSSE64_V: |
19798 | | case RISCV::VSSSEG2E8_V: |
19799 | | case RISCV::VSSSEG2E16_V: |
19800 | | case RISCV::VSSSEG2E32_V: |
19801 | | case RISCV::VSSSEG2E64_V: |
19802 | | case RISCV::VSSSEG3E8_V: |
19803 | | case RISCV::VSSSEG3E16_V: |
19804 | | case RISCV::VSSSEG3E32_V: |
19805 | | case RISCV::VSSSEG3E64_V: |
19806 | | case RISCV::VSSSEG4E8_V: |
19807 | | case RISCV::VSSSEG4E16_V: |
19808 | | case RISCV::VSSSEG4E32_V: |
19809 | | case RISCV::VSSSEG4E64_V: |
19810 | | case RISCV::VSSSEG5E8_V: |
19811 | | case RISCV::VSSSEG5E16_V: |
19812 | | case RISCV::VSSSEG5E32_V: |
19813 | | case RISCV::VSSSEG5E64_V: |
19814 | | case RISCV::VSSSEG6E8_V: |
19815 | | case RISCV::VSSSEG6E16_V: |
19816 | | case RISCV::VSSSEG6E32_V: |
19817 | | case RISCV::VSSSEG6E64_V: |
19818 | | case RISCV::VSSSEG7E8_V: |
19819 | | case RISCV::VSSSEG7E16_V: |
19820 | | case RISCV::VSSSEG7E32_V: |
19821 | | case RISCV::VSSSEG7E64_V: |
19822 | | case RISCV::VSSSEG8E8_V: |
19823 | | case RISCV::VSSSEG8E16_V: |
19824 | | case RISCV::VSSSEG8E32_V: |
19825 | | case RISCV::VSSSEG8E64_V: { |
19826 | | switch (OpNum) { |
19827 | | case 2: |
19828 | | // op: rs2 |
19829 | | return 20; |
19830 | | case 1: |
19831 | | // op: rs1 |
19832 | | return 15; |
19833 | | case 0: |
19834 | | // op: vs3 |
19835 | | return 7; |
19836 | | case 3: |
19837 | | // op: vm |
19838 | | return 25; |
19839 | | } |
19840 | | break; |
19841 | | } |
19842 | | case RISCV::FADD_D: |
19843 | | case RISCV::FADD_D_IN32X: |
19844 | | case RISCV::FADD_D_INX: |
19845 | | case RISCV::FADD_H: |
19846 | | case RISCV::FADD_H_INX: |
19847 | | case RISCV::FADD_S: |
19848 | | case RISCV::FADD_S_INX: |
19849 | | case RISCV::FDIV_D: |
19850 | | case RISCV::FDIV_D_IN32X: |
19851 | | case RISCV::FDIV_D_INX: |
19852 | | case RISCV::FDIV_H: |
19853 | | case RISCV::FDIV_H_INX: |
19854 | | case RISCV::FDIV_S: |
19855 | | case RISCV::FDIV_S_INX: |
19856 | | case RISCV::FMUL_D: |
19857 | | case RISCV::FMUL_D_IN32X: |
19858 | | case RISCV::FMUL_D_INX: |
19859 | | case RISCV::FMUL_H: |
19860 | | case RISCV::FMUL_H_INX: |
19861 | | case RISCV::FMUL_S: |
19862 | | case RISCV::FMUL_S_INX: |
19863 | | case RISCV::FSUB_D: |
19864 | | case RISCV::FSUB_D_IN32X: |
19865 | | case RISCV::FSUB_D_INX: |
19866 | | case RISCV::FSUB_H: |
19867 | | case RISCV::FSUB_H_INX: |
19868 | | case RISCV::FSUB_S: |
19869 | | case RISCV::FSUB_S_INX: { |
19870 | | switch (OpNum) { |
19871 | | case 2: |
19872 | | // op: rs2 |
19873 | | return 20; |
19874 | | case 1: |
19875 | | // op: rs1 |
19876 | | return 15; |
19877 | | case 3: |
19878 | | // op: frm |
19879 | | return 12; |
19880 | | case 0: |
19881 | | // op: rd |
19882 | | return 7; |
19883 | | } |
19884 | | break; |
19885 | | } |
19886 | | case RISCV::VC_V_FV: { |
19887 | | switch (OpNum) { |
19888 | | case 2: |
19889 | | // op: rs2 |
19890 | | return 20; |
19891 | | case 3: |
19892 | | // op: rs1 |
19893 | | return 15; |
19894 | | case 0: |
19895 | | // op: rd |
19896 | | return 7; |
19897 | | case 1: |
19898 | | // op: funct6_lo1 |
19899 | | return 26; |
19900 | | } |
19901 | | break; |
19902 | | } |
19903 | | case RISCV::VC_V_I: |
19904 | | case RISCV::VC_V_IV: |
19905 | | case RISCV::VC_V_VV: |
19906 | | case RISCV::VC_V_X: |
19907 | | case RISCV::VC_V_XV: { |
19908 | | switch (OpNum) { |
19909 | | case 2: |
19910 | | // op: rs2 |
19911 | | return 20; |
19912 | | case 3: |
19913 | | // op: rs1 |
19914 | | return 15; |
19915 | | case 0: |
19916 | | // op: rd |
19917 | | return 7; |
19918 | | case 1: |
19919 | | // op: funct6_lo2 |
19920 | | return 26; |
19921 | | } |
19922 | | break; |
19923 | | } |
19924 | | case RISCV::VC_FV: |
19925 | | case RISCV::VC_FVV: |
19926 | | case RISCV::VC_FVW: { |
19927 | | switch (OpNum) { |
19928 | | case 2: |
19929 | | // op: rs2 |
19930 | | return 20; |
19931 | | case 3: |
19932 | | // op: rs1 |
19933 | | return 15; |
19934 | | case 1: |
19935 | | // op: rd |
19936 | | return 7; |
19937 | | case 0: |
19938 | | // op: funct6_lo1 |
19939 | | return 26; |
19940 | | } |
19941 | | break; |
19942 | | } |
19943 | | case RISCV::VC_IV: |
19944 | | case RISCV::VC_IVV: |
19945 | | case RISCV::VC_IVW: |
19946 | | case RISCV::VC_VV: |
19947 | | case RISCV::VC_VVV: |
19948 | | case RISCV::VC_VVW: |
19949 | | case RISCV::VC_XV: |
19950 | | case RISCV::VC_XVV: |
19951 | | case RISCV::VC_XVW: { |
19952 | | switch (OpNum) { |
19953 | | case 2: |
19954 | | // op: rs2 |
19955 | | return 20; |
19956 | | case 3: |
19957 | | // op: rs1 |
19958 | | return 15; |
19959 | | case 1: |
19960 | | // op: rd |
19961 | | return 7; |
19962 | | case 0: |
19963 | | // op: funct6_lo2 |
19964 | | return 26; |
19965 | | } |
19966 | | break; |
19967 | | } |
19968 | | case RISCV::C_ADDW: |
19969 | | case RISCV::C_AND: |
19970 | | case RISCV::C_MUL: |
19971 | | case RISCV::C_OR: |
19972 | | case RISCV::C_SUB: |
19973 | | case RISCV::C_SUBW: |
19974 | | case RISCV::C_XOR: { |
19975 | | switch (OpNum) { |
19976 | | case 2: |
19977 | | // op: rs2 |
19978 | | return 2; |
19979 | | case 1: |
19980 | | // op: rd |
19981 | | return 7; |
19982 | | } |
19983 | | break; |
19984 | | } |
19985 | | case RISCV::C_ADD_HINT: { |
19986 | | switch (OpNum) { |
19987 | | case 2: |
19988 | | // op: rs2 |
19989 | | return 2; |
19990 | | } |
19991 | | break; |
19992 | | } |
19993 | | case RISCV::VLOXEI8_V: |
19994 | | case RISCV::VLOXEI16_V: |
19995 | | case RISCV::VLOXEI32_V: |
19996 | | case RISCV::VLOXEI64_V: |
19997 | | case RISCV::VLOXSEG2EI8_V: |
19998 | | case RISCV::VLOXSEG2EI16_V: |
19999 | | case RISCV::VLOXSEG2EI32_V: |
20000 | | case RISCV::VLOXSEG2EI64_V: |
20001 | | case RISCV::VLOXSEG3EI8_V: |
20002 | | case RISCV::VLOXSEG3EI16_V: |
20003 | | case RISCV::VLOXSEG3EI32_V: |
20004 | | case RISCV::VLOXSEG3EI64_V: |
20005 | | case RISCV::VLOXSEG4EI8_V: |
20006 | | case RISCV::VLOXSEG4EI16_V: |
20007 | | case RISCV::VLOXSEG4EI32_V: |
20008 | | case RISCV::VLOXSEG4EI64_V: |
20009 | | case RISCV::VLOXSEG5EI8_V: |
20010 | | case RISCV::VLOXSEG5EI16_V: |
20011 | | case RISCV::VLOXSEG5EI32_V: |
20012 | | case RISCV::VLOXSEG5EI64_V: |
20013 | | case RISCV::VLOXSEG6EI8_V: |
20014 | | case RISCV::VLOXSEG6EI16_V: |
20015 | | case RISCV::VLOXSEG6EI32_V: |
20016 | | case RISCV::VLOXSEG6EI64_V: |
20017 | | case RISCV::VLOXSEG7EI8_V: |
20018 | | case RISCV::VLOXSEG7EI16_V: |
20019 | | case RISCV::VLOXSEG7EI32_V: |
20020 | | case RISCV::VLOXSEG7EI64_V: |
20021 | | case RISCV::VLOXSEG8EI8_V: |
20022 | | case RISCV::VLOXSEG8EI16_V: |
20023 | | case RISCV::VLOXSEG8EI32_V: |
20024 | | case RISCV::VLOXSEG8EI64_V: |
20025 | | case RISCV::VLUXEI8_V: |
20026 | | case RISCV::VLUXEI16_V: |
20027 | | case RISCV::VLUXEI32_V: |
20028 | | case RISCV::VLUXEI64_V: |
20029 | | case RISCV::VLUXSEG2EI8_V: |
20030 | | case RISCV::VLUXSEG2EI16_V: |
20031 | | case RISCV::VLUXSEG2EI32_V: |
20032 | | case RISCV::VLUXSEG2EI64_V: |
20033 | | case RISCV::VLUXSEG3EI8_V: |
20034 | | case RISCV::VLUXSEG3EI16_V: |
20035 | | case RISCV::VLUXSEG3EI32_V: |
20036 | | case RISCV::VLUXSEG3EI64_V: |
20037 | | case RISCV::VLUXSEG4EI8_V: |
20038 | | case RISCV::VLUXSEG4EI16_V: |
20039 | | case RISCV::VLUXSEG4EI32_V: |
20040 | | case RISCV::VLUXSEG4EI64_V: |
20041 | | case RISCV::VLUXSEG5EI8_V: |
20042 | | case RISCV::VLUXSEG5EI16_V: |
20043 | | case RISCV::VLUXSEG5EI32_V: |
20044 | | case RISCV::VLUXSEG5EI64_V: |
20045 | | case RISCV::VLUXSEG6EI8_V: |
20046 | | case RISCV::VLUXSEG6EI16_V: |
20047 | | case RISCV::VLUXSEG6EI32_V: |
20048 | | case RISCV::VLUXSEG6EI64_V: |
20049 | | case RISCV::VLUXSEG7EI8_V: |
20050 | | case RISCV::VLUXSEG7EI16_V: |
20051 | | case RISCV::VLUXSEG7EI32_V: |
20052 | | case RISCV::VLUXSEG7EI64_V: |
20053 | | case RISCV::VLUXSEG8EI8_V: |
20054 | | case RISCV::VLUXSEG8EI16_V: |
20055 | | case RISCV::VLUXSEG8EI32_V: |
20056 | | case RISCV::VLUXSEG8EI64_V: { |
20057 | | switch (OpNum) { |
20058 | | case 2: |
20059 | | // op: vs2 |
20060 | | return 20; |
20061 | | case 1: |
20062 | | // op: rs1 |
20063 | | return 15; |
20064 | | case 0: |
20065 | | // op: vd |
20066 | | return 7; |
20067 | | case 3: |
20068 | | // op: vm |
20069 | | return 25; |
20070 | | } |
20071 | | break; |
20072 | | } |
20073 | | case RISCV::VSOXEI8_V: |
20074 | | case RISCV::VSOXEI16_V: |
20075 | | case RISCV::VSOXEI32_V: |
20076 | | case RISCV::VSOXEI64_V: |
20077 | | case RISCV::VSOXSEG2EI8_V: |
20078 | | case RISCV::VSOXSEG2EI16_V: |
20079 | | case RISCV::VSOXSEG2EI32_V: |
20080 | | case RISCV::VSOXSEG2EI64_V: |
20081 | | case RISCV::VSOXSEG3EI8_V: |
20082 | | case RISCV::VSOXSEG3EI16_V: |
20083 | | case RISCV::VSOXSEG3EI32_V: |
20084 | | case RISCV::VSOXSEG3EI64_V: |
20085 | | case RISCV::VSOXSEG4EI8_V: |
20086 | | case RISCV::VSOXSEG4EI16_V: |
20087 | | case RISCV::VSOXSEG4EI32_V: |
20088 | | case RISCV::VSOXSEG4EI64_V: |
20089 | | case RISCV::VSOXSEG5EI8_V: |
20090 | | case RISCV::VSOXSEG5EI16_V: |
20091 | | case RISCV::VSOXSEG5EI32_V: |
20092 | | case RISCV::VSOXSEG5EI64_V: |
20093 | | case RISCV::VSOXSEG6EI8_V: |
20094 | | case RISCV::VSOXSEG6EI16_V: |
20095 | | case RISCV::VSOXSEG6EI32_V: |
20096 | | case RISCV::VSOXSEG6EI64_V: |
20097 | | case RISCV::VSOXSEG7EI8_V: |
20098 | | case RISCV::VSOXSEG7EI16_V: |
20099 | | case RISCV::VSOXSEG7EI32_V: |
20100 | | case RISCV::VSOXSEG7EI64_V: |
20101 | | case RISCV::VSOXSEG8EI8_V: |
20102 | | case RISCV::VSOXSEG8EI16_V: |
20103 | | case RISCV::VSOXSEG8EI32_V: |
20104 | | case RISCV::VSOXSEG8EI64_V: |
20105 | | case RISCV::VSUXEI8_V: |
20106 | | case RISCV::VSUXEI16_V: |
20107 | | case RISCV::VSUXEI32_V: |
20108 | | case RISCV::VSUXEI64_V: |
20109 | | case RISCV::VSUXSEG2EI8_V: |
20110 | | case RISCV::VSUXSEG2EI16_V: |
20111 | | case RISCV::VSUXSEG2EI32_V: |
20112 | | case RISCV::VSUXSEG2EI64_V: |
20113 | | case RISCV::VSUXSEG3EI8_V: |
20114 | | case RISCV::VSUXSEG3EI16_V: |
20115 | | case RISCV::VSUXSEG3EI32_V: |
20116 | | case RISCV::VSUXSEG3EI64_V: |
20117 | | case RISCV::VSUXSEG4EI8_V: |
20118 | | case RISCV::VSUXSEG4EI16_V: |
20119 | | case RISCV::VSUXSEG4EI32_V: |
20120 | | case RISCV::VSUXSEG4EI64_V: |
20121 | | case RISCV::VSUXSEG5EI8_V: |
20122 | | case RISCV::VSUXSEG5EI16_V: |
20123 | | case RISCV::VSUXSEG5EI32_V: |
20124 | | case RISCV::VSUXSEG5EI64_V: |
20125 | | case RISCV::VSUXSEG6EI8_V: |
20126 | | case RISCV::VSUXSEG6EI16_V: |
20127 | | case RISCV::VSUXSEG6EI32_V: |
20128 | | case RISCV::VSUXSEG6EI64_V: |
20129 | | case RISCV::VSUXSEG7EI8_V: |
20130 | | case RISCV::VSUXSEG7EI16_V: |
20131 | | case RISCV::VSUXSEG7EI32_V: |
20132 | | case RISCV::VSUXSEG7EI64_V: |
20133 | | case RISCV::VSUXSEG8EI8_V: |
20134 | | case RISCV::VSUXSEG8EI16_V: |
20135 | | case RISCV::VSUXSEG8EI32_V: |
20136 | | case RISCV::VSUXSEG8EI64_V: { |
20137 | | switch (OpNum) { |
20138 | | case 2: |
20139 | | // op: vs2 |
20140 | | return 20; |
20141 | | case 1: |
20142 | | // op: rs1 |
20143 | | return 15; |
20144 | | case 0: |
20145 | | // op: vs3 |
20146 | | return 7; |
20147 | | case 3: |
20148 | | // op: vm |
20149 | | return 25; |
20150 | | } |
20151 | | break; |
20152 | | } |
20153 | | case RISCV::CV_SB_ri_inc: |
20154 | | case RISCV::CV_SH_ri_inc: |
20155 | | case RISCV::CV_SW_ri_inc: { |
20156 | | switch (OpNum) { |
20157 | | case 3: |
20158 | | // op: imm12 |
20159 | | return 7; |
20160 | | case 1: |
20161 | | // op: rs2 |
20162 | | return 20; |
20163 | | case 2: |
20164 | | // op: rs1 |
20165 | | return 15; |
20166 | | } |
20167 | | break; |
20168 | | } |
20169 | | case RISCV::CV_LBU_rr_inc: |
20170 | | case RISCV::CV_LB_rr_inc: |
20171 | | case RISCV::CV_LHU_rr_inc: |
20172 | | case RISCV::CV_LH_rr_inc: |
20173 | | case RISCV::CV_LW_rr_inc: { |
20174 | | switch (OpNum) { |
20175 | | case 3: |
20176 | | // op: rs2 |
20177 | | return 20; |
20178 | | case 2: |
20179 | | // op: rs1 |
20180 | | return 15; |
20181 | | case 0: |
20182 | | // op: rd |
20183 | | return 7; |
20184 | | } |
20185 | | break; |
20186 | | } |
20187 | | case RISCV::CV_MACHHSN: |
20188 | | case RISCV::CV_MACHHSRN: |
20189 | | case RISCV::CV_MACHHUN: |
20190 | | case RISCV::CV_MACHHURN: |
20191 | | case RISCV::CV_MACSN: |
20192 | | case RISCV::CV_MACSRN: |
20193 | | case RISCV::CV_MACUN: |
20194 | | case RISCV::CV_MACURN: { |
20195 | | switch (OpNum) { |
20196 | | case 3: |
20197 | | // op: rs2 |
20198 | | return 20; |
20199 | | case 2: |
20200 | | // op: rs1 |
20201 | | return 15; |
20202 | | case 1: |
20203 | | // op: rd |
20204 | | return 7; |
20205 | | case 4: |
20206 | | // op: imm5 |
20207 | | return 25; |
20208 | | } |
20209 | | break; |
20210 | | } |
20211 | | case RISCV::AMOCAS_D_RV32: |
20212 | | case RISCV::AMOCAS_D_RV32_AQ: |
20213 | | case RISCV::AMOCAS_D_RV32_AQ_RL: |
20214 | | case RISCV::AMOCAS_D_RV32_RL: |
20215 | | case RISCV::AMOCAS_D_RV64: |
20216 | | case RISCV::AMOCAS_D_RV64_AQ: |
20217 | | case RISCV::AMOCAS_D_RV64_AQ_RL: |
20218 | | case RISCV::AMOCAS_D_RV64_RL: |
20219 | | case RISCV::AMOCAS_Q: |
20220 | | case RISCV::AMOCAS_Q_AQ: |
20221 | | case RISCV::AMOCAS_Q_AQ_RL: |
20222 | | case RISCV::AMOCAS_Q_RL: |
20223 | | case RISCV::AMOCAS_W: |
20224 | | case RISCV::AMOCAS_W_AQ: |
20225 | | case RISCV::AMOCAS_W_AQ_RL: |
20226 | | case RISCV::AMOCAS_W_RL: |
20227 | | case RISCV::CV_ADDNR: |
20228 | | case RISCV::CV_ADDRNR: |
20229 | | case RISCV::CV_ADDUNR: |
20230 | | case RISCV::CV_ADDURNR: |
20231 | | case RISCV::CV_CPLXMUL_I: |
20232 | | case RISCV::CV_CPLXMUL_I_DIV2: |
20233 | | case RISCV::CV_CPLXMUL_I_DIV4: |
20234 | | case RISCV::CV_CPLXMUL_I_DIV8: |
20235 | | case RISCV::CV_CPLXMUL_R: |
20236 | | case RISCV::CV_CPLXMUL_R_DIV2: |
20237 | | case RISCV::CV_CPLXMUL_R_DIV4: |
20238 | | case RISCV::CV_CPLXMUL_R_DIV8: |
20239 | | case RISCV::CV_INSERTR: |
20240 | | case RISCV::CV_MAC: |
20241 | | case RISCV::CV_MSU: |
20242 | | case RISCV::CV_PACKHI_B: |
20243 | | case RISCV::CV_PACKLO_B: |
20244 | | case RISCV::CV_SDOTSP_B: |
20245 | | case RISCV::CV_SDOTSP_H: |
20246 | | case RISCV::CV_SDOTSP_SC_B: |
20247 | | case RISCV::CV_SDOTSP_SC_H: |
20248 | | case RISCV::CV_SDOTUP_B: |
20249 | | case RISCV::CV_SDOTUP_H: |
20250 | | case RISCV::CV_SDOTUP_SC_B: |
20251 | | case RISCV::CV_SDOTUP_SC_H: |
20252 | | case RISCV::CV_SDOTUSP_B: |
20253 | | case RISCV::CV_SDOTUSP_H: |
20254 | | case RISCV::CV_SDOTUSP_SC_B: |
20255 | | case RISCV::CV_SDOTUSP_SC_H: |
20256 | | case RISCV::CV_SHUFFLE2_B: |
20257 | | case RISCV::CV_SHUFFLE2_H: |
20258 | | case RISCV::CV_SUBNR: |
20259 | | case RISCV::CV_SUBRNR: |
20260 | | case RISCV::CV_SUBUNR: |
20261 | | case RISCV::CV_SUBURNR: |
20262 | | case RISCV::TH_MULA: |
20263 | | case RISCV::TH_MULAH: |
20264 | | case RISCV::TH_MULAW: |
20265 | | case RISCV::TH_MULS: |
20266 | | case RISCV::TH_MULSH: |
20267 | | case RISCV::TH_MULSW: |
20268 | | case RISCV::TH_MVEQZ: |
20269 | | case RISCV::TH_MVNEZ: { |
20270 | | switch (OpNum) { |
20271 | | case 3: |
20272 | | // op: rs2 |
20273 | | return 20; |
20274 | | case 2: |
20275 | | // op: rs1 |
20276 | | return 15; |
20277 | | case 1: |
20278 | | // op: rd |
20279 | | return 7; |
20280 | | } |
20281 | | break; |
20282 | | } |
20283 | | case RISCV::VC_V_FVV: |
20284 | | case RISCV::VC_V_FVW: { |
20285 | | switch (OpNum) { |
20286 | | case 3: |
20287 | | // op: rs2 |
20288 | | return 20; |
20289 | | case 4: |
20290 | | // op: rs1 |
20291 | | return 15; |
20292 | | case 2: |
20293 | | // op: rd |
20294 | | return 7; |
20295 | | case 1: |
20296 | | // op: funct6_lo1 |
20297 | | return 26; |
20298 | | } |
20299 | | break; |
20300 | | } |
20301 | | case RISCV::VC_V_IVV: |
20302 | | case RISCV::VC_V_IVW: |
20303 | | case RISCV::VC_V_VVV: |
20304 | | case RISCV::VC_V_VVW: |
20305 | | case RISCV::VC_V_XVV: |
20306 | | case RISCV::VC_V_XVW: { |
20307 | | switch (OpNum) { |
20308 | | case 3: |
20309 | | // op: rs2 |
20310 | | return 20; |
20311 | | case 4: |
20312 | | // op: rs1 |
20313 | | return 15; |
20314 | | case 2: |
20315 | | // op: rd |
20316 | | return 7; |
20317 | | case 1: |
20318 | | // op: funct6_lo2 |
20319 | | return 26; |
20320 | | } |
20321 | | break; |
20322 | | } |
20323 | | case RISCV::FMADD_D: |
20324 | | case RISCV::FMADD_D_IN32X: |
20325 | | case RISCV::FMADD_D_INX: |
20326 | | case RISCV::FMADD_H: |
20327 | | case RISCV::FMADD_H_INX: |
20328 | | case RISCV::FMADD_S: |
20329 | | case RISCV::FMADD_S_INX: |
20330 | | case RISCV::FMSUB_D: |
20331 | | case RISCV::FMSUB_D_IN32X: |
20332 | | case RISCV::FMSUB_D_INX: |
20333 | | case RISCV::FMSUB_H: |
20334 | | case RISCV::FMSUB_H_INX: |
20335 | | case RISCV::FMSUB_S: |
20336 | | case RISCV::FMSUB_S_INX: |
20337 | | case RISCV::FNMADD_D: |
20338 | | case RISCV::FNMADD_D_IN32X: |
20339 | | case RISCV::FNMADD_D_INX: |
20340 | | case RISCV::FNMADD_H: |
20341 | | case RISCV::FNMADD_H_INX: |
20342 | | case RISCV::FNMADD_S: |
20343 | | case RISCV::FNMADD_S_INX: |
20344 | | case RISCV::FNMSUB_D: |
20345 | | case RISCV::FNMSUB_D_IN32X: |
20346 | | case RISCV::FNMSUB_D_INX: |
20347 | | case RISCV::FNMSUB_H: |
20348 | | case RISCV::FNMSUB_H_INX: |
20349 | | case RISCV::FNMSUB_S: |
20350 | | case RISCV::FNMSUB_S_INX: { |
20351 | | switch (OpNum) { |
20352 | | case 3: |
20353 | | // op: rs3 |
20354 | | return 27; |
20355 | | case 2: |
20356 | | // op: rs2 |
20357 | | return 20; |
20358 | | case 1: |
20359 | | // op: rs1 |
20360 | | return 15; |
20361 | | case 4: |
20362 | | // op: frm |
20363 | | return 12; |
20364 | | case 0: |
20365 | | // op: rd |
20366 | | return 7; |
20367 | | } |
20368 | | break; |
20369 | | } |
20370 | | case RISCV::CV_SB_rr_inc: |
20371 | | case RISCV::CV_SH_rr_inc: |
20372 | | case RISCV::CV_SW_rr_inc: { |
20373 | | switch (OpNum) { |
20374 | | case 3: |
20375 | | // op: rs3 |
20376 | | return 7; |
20377 | | case 1: |
20378 | | // op: rs2 |
20379 | | return 20; |
20380 | | case 2: |
20381 | | // op: rs1 |
20382 | | return 15; |
20383 | | } |
20384 | | break; |
20385 | | } |
20386 | | case RISCV::THVdotVMAQASU_VX: |
20387 | | case RISCV::THVdotVMAQAUS_VX: |
20388 | | case RISCV::THVdotVMAQAU_VX: |
20389 | | case RISCV::THVdotVMAQA_VX: |
20390 | | case RISCV::VFMACC_VF: |
20391 | | case RISCV::VFMADD_VF: |
20392 | | case RISCV::VFMSAC_VF: |
20393 | | case RISCV::VFMSUB_VF: |
20394 | | case RISCV::VFNMACC_VF: |
20395 | | case RISCV::VFNMADD_VF: |
20396 | | case RISCV::VFNMSAC_VF: |
20397 | | case RISCV::VFNMSUB_VF: |
20398 | | case RISCV::VFWMACCBF16_VF: |
20399 | | case RISCV::VFWMACC_VF: |
20400 | | case RISCV::VFWMSAC_VF: |
20401 | | case RISCV::VFWNMACC_VF: |
20402 | | case RISCV::VFWNMSAC_VF: |
20403 | | case RISCV::VMACC_VX: |
20404 | | case RISCV::VMADD_VX: |
20405 | | case RISCV::VNMSAC_VX: |
20406 | | case RISCV::VNMSUB_VX: |
20407 | | case RISCV::VWMACCSU_VX: |
20408 | | case RISCV::VWMACCUS_VX: |
20409 | | case RISCV::VWMACCU_VX: |
20410 | | case RISCV::VWMACC_VX: { |
20411 | | switch (OpNum) { |
20412 | | case 3: |
20413 | | // op: vs2 |
20414 | | return 20; |
20415 | | case 2: |
20416 | | // op: rs1 |
20417 | | return 15; |
20418 | | case 1: |
20419 | | // op: vd |
20420 | | return 7; |
20421 | | case 4: |
20422 | | // op: vm |
20423 | | return 25; |
20424 | | } |
20425 | | break; |
20426 | | } |
20427 | | case RISCV::THVdotVMAQASU_VV: |
20428 | | case RISCV::THVdotVMAQAU_VV: |
20429 | | case RISCV::THVdotVMAQA_VV: |
20430 | | case RISCV::VFMACC_VV: |
20431 | | case RISCV::VFMADD_VV: |
20432 | | case RISCV::VFMSAC_VV: |
20433 | | case RISCV::VFMSUB_VV: |
20434 | | case RISCV::VFNMACC_VV: |
20435 | | case RISCV::VFNMADD_VV: |
20436 | | case RISCV::VFNMSAC_VV: |
20437 | | case RISCV::VFNMSUB_VV: |
20438 | | case RISCV::VFWMACCBF16_VV: |
20439 | | case RISCV::VFWMACC_VV: |
20440 | | case RISCV::VFWMSAC_VV: |
20441 | | case RISCV::VFWNMACC_VV: |
20442 | | case RISCV::VFWNMSAC_VV: |
20443 | | case RISCV::VMACC_VV: |
20444 | | case RISCV::VMADD_VV: |
20445 | | case RISCV::VNMSAC_VV: |
20446 | | case RISCV::VNMSUB_VV: |
20447 | | case RISCV::VWMACCSU_VV: |
20448 | | case RISCV::VWMACCU_VV: |
20449 | | case RISCV::VWMACC_VV: { |
20450 | | switch (OpNum) { |
20451 | | case 3: |
20452 | | // op: vs2 |
20453 | | return 20; |
20454 | | case 2: |
20455 | | // op: vs1 |
20456 | | return 15; |
20457 | | case 1: |
20458 | | // op: vd |
20459 | | return 7; |
20460 | | case 4: |
20461 | | // op: vm |
20462 | | return 25; |
20463 | | } |
20464 | | break; |
20465 | | } |
20466 | | } |
20467 | | std::string msg; |
20468 | | raw_string_ostream Msg(msg); |
20469 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
20470 | | report_fatal_error(Msg.str().c_str()); |
20471 | | } |
20472 | | |
20473 | | #endif // GET_OPERAND_BIT_OFFSET |
20474 | | |