/src/build/lib/Target/RISCV/RISCVGenMCPseudoLowering.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Pseudo-instruction MC lowering Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | bool RISCVAsmPrinter:: |
10 | | emitPseudoExpansionLowering(MCStreamer &OutStreamer, |
11 | 860k | const MachineInstr *MI) { |
12 | 860k | switch (MI->getOpcode()) { |
13 | 854k | default: return false; |
14 | 59 | case RISCV::PseudoBR: { |
15 | 59 | MCInst TmpInst; |
16 | 59 | MCOperand MCOp; |
17 | 59 | TmpInst.setOpcode(RISCV::JAL); |
18 | | // Operand: rd |
19 | 59 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
20 | | // Operand: imm20 |
21 | 59 | lowerOperand(MI->getOperand(0), MCOp); |
22 | 59 | TmpInst.addOperand(MCOp); |
23 | 59 | EmitToStreamer(OutStreamer, TmpInst); |
24 | 59 | break; |
25 | 0 | } |
26 | 0 | case RISCV::PseudoBRIND: { |
27 | 0 | MCInst TmpInst; |
28 | 0 | MCOperand MCOp; |
29 | 0 | TmpInst.setOpcode(RISCV::JALR); |
30 | | // Operand: rd |
31 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
32 | | // Operand: rs1 |
33 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
34 | 0 | TmpInst.addOperand(MCOp); |
35 | | // Operand: imm12 |
36 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
37 | 0 | TmpInst.addOperand(MCOp); |
38 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
39 | 0 | break; |
40 | 0 | } |
41 | 0 | case RISCV::PseudoCALLIndirect: { |
42 | 0 | MCInst TmpInst; |
43 | 0 | MCOperand MCOp; |
44 | 0 | TmpInst.setOpcode(RISCV::JALR); |
45 | | // Operand: rd |
46 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X1)); |
47 | | // Operand: rs1 |
48 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
49 | 0 | TmpInst.addOperand(MCOp); |
50 | | // Operand: imm12 |
51 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
52 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
53 | 0 | break; |
54 | 0 | } |
55 | 6.16k | case RISCV::PseudoRET: { |
56 | 6.16k | MCInst TmpInst; |
57 | 6.16k | MCOperand MCOp; |
58 | 6.16k | TmpInst.setOpcode(RISCV::JALR); |
59 | | // Operand: rd |
60 | 6.16k | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
61 | | // Operand: rs1 |
62 | 6.16k | TmpInst.addOperand(MCOperand::createReg(RISCV::X1)); |
63 | | // Operand: imm12 |
64 | 6.16k | TmpInst.addOperand(MCOperand::createImm(0)); |
65 | 6.16k | EmitToStreamer(OutStreamer, TmpInst); |
66 | 6.16k | break; |
67 | 0 | } |
68 | 0 | case RISCV::PseudoReadVL: { |
69 | 0 | MCInst TmpInst; |
70 | 0 | MCOperand MCOp; |
71 | 0 | TmpInst.setOpcode(RISCV::CSRRS); |
72 | | // Operand: rd |
73 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
74 | 0 | TmpInst.addOperand(MCOp); |
75 | | // Operand: imm12 |
76 | 0 | TmpInst.addOperand(MCOperand::createImm(3104)); |
77 | | // Operand: rs1 |
78 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
79 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
80 | 0 | break; |
81 | 0 | } |
82 | 0 | case RISCV::PseudoReadVLENB: { |
83 | 0 | MCInst TmpInst; |
84 | 0 | MCOperand MCOp; |
85 | 0 | TmpInst.setOpcode(RISCV::CSRRS); |
86 | | // Operand: rd |
87 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
88 | 0 | TmpInst.addOperand(MCOp); |
89 | | // Operand: imm12 |
90 | 0 | TmpInst.addOperand(MCOperand::createImm(3106)); |
91 | | // Operand: rs1 |
92 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
93 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
94 | 0 | break; |
95 | 0 | } |
96 | 0 | case RISCV::PseudoTAILIndirect: { |
97 | 0 | MCInst TmpInst; |
98 | 0 | MCOperand MCOp; |
99 | 0 | TmpInst.setOpcode(RISCV::JALR); |
100 | | // Operand: rd |
101 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
102 | | // Operand: rs1 |
103 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
104 | 0 | TmpInst.addOperand(MCOp); |
105 | | // Operand: imm12 |
106 | 0 | TmpInst.addOperand(MCOperand::createImm(0)); |
107 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
108 | 0 | break; |
109 | 0 | } |
110 | 0 | case RISCV::ReadFFLAGS: { |
111 | 0 | MCInst TmpInst; |
112 | 0 | MCOperand MCOp; |
113 | 0 | TmpInst.setOpcode(RISCV::CSRRS); |
114 | | // Operand: rd |
115 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
116 | 0 | TmpInst.addOperand(MCOp); |
117 | | // Operand: imm12 |
118 | 0 | TmpInst.addOperand(MCOperand::createImm(1)); |
119 | | // Operand: rs1 |
120 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
121 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
122 | 0 | break; |
123 | 0 | } |
124 | 0 | case RISCV::ReadFRM: { |
125 | 0 | MCInst TmpInst; |
126 | 0 | MCOperand MCOp; |
127 | 0 | TmpInst.setOpcode(RISCV::CSRRS); |
128 | | // Operand: rd |
129 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
130 | 0 | TmpInst.addOperand(MCOp); |
131 | | // Operand: imm12 |
132 | 0 | TmpInst.addOperand(MCOperand::createImm(2)); |
133 | | // Operand: rs1 |
134 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
135 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
136 | 0 | break; |
137 | 0 | } |
138 | 0 | case RISCV::SwapFRMImm: { |
139 | 0 | MCInst TmpInst; |
140 | 0 | MCOperand MCOp; |
141 | 0 | TmpInst.setOpcode(RISCV::CSRRWI); |
142 | | // Operand: rd |
143 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
144 | 0 | TmpInst.addOperand(MCOp); |
145 | | // Operand: imm12 |
146 | 0 | TmpInst.addOperand(MCOperand::createImm(2)); |
147 | | // Operand: rs1 |
148 | 0 | lowerOperand(MI->getOperand(1), MCOp); |
149 | 0 | TmpInst.addOperand(MCOp); |
150 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
151 | 0 | break; |
152 | 0 | } |
153 | 0 | case RISCV::WriteFFLAGS: { |
154 | 0 | MCInst TmpInst; |
155 | 0 | MCOperand MCOp; |
156 | 0 | TmpInst.setOpcode(RISCV::CSRRW); |
157 | | // Operand: rd |
158 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
159 | | // Operand: imm12 |
160 | 0 | TmpInst.addOperand(MCOperand::createImm(1)); |
161 | | // Operand: rs1 |
162 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
163 | 0 | TmpInst.addOperand(MCOp); |
164 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
165 | 0 | break; |
166 | 0 | } |
167 | 0 | case RISCV::WriteFRM: { |
168 | 0 | MCInst TmpInst; |
169 | 0 | MCOperand MCOp; |
170 | 0 | TmpInst.setOpcode(RISCV::CSRRW); |
171 | | // Operand: rd |
172 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
173 | | // Operand: imm12 |
174 | 0 | TmpInst.addOperand(MCOperand::createImm(2)); |
175 | | // Operand: rs1 |
176 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
177 | 0 | TmpInst.addOperand(MCOp); |
178 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
179 | 0 | break; |
180 | 0 | } |
181 | 0 | case RISCV::WriteFRMImm: { |
182 | 0 | MCInst TmpInst; |
183 | 0 | MCOperand MCOp; |
184 | 0 | TmpInst.setOpcode(RISCV::CSRRWI); |
185 | | // Operand: rd |
186 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
187 | | // Operand: imm12 |
188 | 0 | TmpInst.addOperand(MCOperand::createImm(2)); |
189 | | // Operand: rs1 |
190 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
191 | 0 | TmpInst.addOperand(MCOp); |
192 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
193 | 0 | break; |
194 | 0 | } |
195 | 0 | case RISCV::WriteVXRMImm: { |
196 | 0 | MCInst TmpInst; |
197 | 0 | MCOperand MCOp; |
198 | 0 | TmpInst.setOpcode(RISCV::CSRRWI); |
199 | | // Operand: rd |
200 | 0 | TmpInst.addOperand(MCOperand::createReg(RISCV::X0)); |
201 | | // Operand: imm12 |
202 | 0 | TmpInst.addOperand(MCOperand::createImm(10)); |
203 | | // Operand: rs1 |
204 | 0 | lowerOperand(MI->getOperand(0), MCOp); |
205 | 0 | TmpInst.addOperand(MCOp); |
206 | 0 | EmitToStreamer(OutStreamer, TmpInst); |
207 | 0 | break; |
208 | 0 | } |
209 | 860k | } |
210 | 6.21k | return true; |
211 | 860k | } |
212 | | |