Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/RISCV/RISCVGenRegisterBank.inc
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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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|*                                                                            *|
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|* Register Bank Source Fragments                                             *|
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|*                                                                            *|
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|* Automatically generated file, do not edit!                                 *|
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|*                                                                            *|
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\*===----------------------------------------------------------------------===*/
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#ifdef GET_REGBANK_DECLARATIONS
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#undef GET_REGBANK_DECLARATIONS
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namespace llvm {
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namespace RISCV {
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enum : unsigned {
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  InvalidRegBankID = ~0u,
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  FPRBRegBankID = 0,
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  GPRBRegBankID = 1,
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  VRBRegBankID = 2,
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  NumRegisterBanks,
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};
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} // end namespace RISCV
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} // end namespace llvm
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#endif // GET_REGBANK_DECLARATIONS
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#ifdef GET_TARGET_REGBANK_CLASS
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#undef GET_TARGET_REGBANK_CLASS
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private:
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  static const RegisterBank *RegBanks[];
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  static const unsigned Sizes[];
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protected:
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  RISCVGenRegisterBankInfo(unsigned HwMode = 0);
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#endif // GET_TARGET_REGBANK_CLASS
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#ifdef GET_TARGET_REGBANK_IMPL
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#undef GET_TARGET_REGBANK_IMPL
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namespace llvm {
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namespace RISCV {
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const uint32_t FPRBRegBankCoverageData[] = {
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    // 0-31
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    (1u << (RISCV::FPR64RegClassID - 0)) |
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    (1u << (RISCV::FPR16RegClassID - 0)) |
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    (1u << (RISCV::FPR32RegClassID - 0)) |
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    (1u << (RISCV::FPR64CRegClassID - 0)) |
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    (1u << (RISCV::FPR32CRegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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    // 64-95
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    0,
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};
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const uint32_t GPRBRegBankCoverageData[] = {
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    // 0-31
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    (1u << (RISCV::GPRRegClassID - 0)) |
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    (1u << (RISCV::GPRF16RegClassID - 0)) |
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    (1u << (RISCV::GPRF32RegClassID - 0)) |
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    (1u << (RISCV::GPRNoX0RegClassID - 0)) |
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    (1u << (RISCV::GPRNoX0X2RegClassID - 0)) |
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    (1u << (RISCV::GPRJALRRegClassID - 0)) |
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    (1u << (RISCV::GPRTCRegClassID - 0)) |
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    (1u << (RISCV::GPRC_and_GPRTCRegClassID - 0)) |
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    (1u << (RISCV::GPRCRegClassID - 0)) |
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    (1u << (RISCV::GPRC_and_SR07RegClassID - 0)) |
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    (1u << (RISCV::SR07RegClassID - 0)) |
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    (1u << (RISCV::GPRX1X5RegClassID - 0)) |
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    (1u << (RISCV::GPRX1RegClassID - 0)) |
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    (1u << (RISCV::GPRX5RegClassID - 0)) |
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    (1u << (RISCV::SPRegClassID - 0)) |
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    (1u << (RISCV::GPRX0RegClassID - 0)) |
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    0,
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    // 32-63
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    0,
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    // 64-95
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    0,
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};
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const uint32_t VRBRegBankCoverageData[] = {
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    // 0-31
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    (1u << (RISCV::VMRegClassID - 0)) |
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    (1u << (RISCV::VRRegClassID - 0)) |
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    (1u << (RISCV::VRNoV0RegClassID - 0)) |
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    0,
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    // 32-63
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    (1u << (RISCV::VRM2RegClassID - 32)) |
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    (1u << (RISCV::VRM2NoV0RegClassID - 32)) |
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    (1u << (RISCV::VRM4RegClassID - 32)) |
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    (1u << (RISCV::VRM4NoV0RegClassID - 32)) |
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    (1u << (RISCV::VMV0RegClassID - 32)) |
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    (1u << (RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID - 32)) |
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    (1u << (RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID - 32)) |
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    0,
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    // 64-95
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    (1u << (RISCV::VRM8RegClassID - 64)) |
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    (1u << (RISCV::VRM8NoV0RegClassID - 64)) |
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    (1u << (RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID - 64)) |
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    0,
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};
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constexpr RegisterBank FPRBRegBank(/* ID */ RISCV::FPRBRegBankID, /* Name */ "FPRB", /* CoveredRegClasses */ FPRBRegBankCoverageData, /* NumRegClasses */ 81);
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constexpr RegisterBank GPRBRegBank(/* ID */ RISCV::GPRBRegBankID, /* Name */ "GPRB", /* CoveredRegClasses */ GPRBRegBankCoverageData, /* NumRegClasses */ 81);
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constexpr RegisterBank VRBRegBank(/* ID */ RISCV::VRBRegBankID, /* Name */ "VRB", /* CoveredRegClasses */ VRBRegBankCoverageData, /* NumRegClasses */ 81);
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} // end namespace RISCV
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const RegisterBank *RISCVGenRegisterBankInfo::RegBanks[] = {
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    &RISCV::FPRBRegBank,
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    &RISCV::GPRBRegBank,
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    &RISCV::VRBRegBank,
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};
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const unsigned RISCVGenRegisterBankInfo::Sizes[] = {
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    // Mode = 0 (Default)
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    64,
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    32,
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    512,
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    // Mode = 1 (RV64)
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    64,
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    64,
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    512,
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};
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RISCVGenRegisterBankInfo::RISCVGenRegisterBankInfo(unsigned HwMode)
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    : RegisterBankInfo(RegBanks, RISCV::NumRegisterBanks, Sizes, HwMode) {
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  // Assert that RegBank indices match their ID's
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#ifndef NDEBUG
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  for (auto RB : enumerate(RegBanks))
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    assert(RB.index() == RB.value()->getID() && "Index != ID");
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#endif // NDEBUG
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1
}
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} // end namespace llvm
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#endif // GET_TARGET_REGBANK_IMPL