/src/build/lib/Target/RISCV/RISCVGenRegisterInfo.inc

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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass RISCVMCRegisterClasses[];

namespace RISCV {
enum {
  NoRegister,
  FFLAGS = 1,
  FRM = 2,
  SSP = 3,
  VL = 4,
  VLENB = 5,
  VTYPE = 6,
  VXRM = 7,
  VXSAT = 8,
  DUMMY_REG_PAIR_WITH_X0 = 9,
  V0 = 10,
  V1 = 11,
  V2 = 12,
  V3 = 13,
  V4 = 14,
  V5 = 15,
  V6 = 16,
  V7 = 17,
  V8 = 18,
  V9 = 19,
  V10 = 20,
  V11 = 21,
  V12 = 22,
  V13 = 23,
  V14 = 24,
  V15 = 25,
  V16 = 26,
  V17 = 27,
  V18 = 28,
  V19 = 29,
  V20 = 30,
  V21 = 31,
  V22 = 32,
  V23 = 33,
  V24 = 34,
  V25 = 35,
  V26 = 36,
  V27 = 37,
  V28 = 38,
  V29 = 39,
  V30 = 40,
  V31 = 41,
  X0 = 42,
  X1 = 43,
  X2 = 44,
  X3 = 45,
  X4 = 46,
  X5 = 47,
  X6 = 48,
  X7 = 49,
  X8 = 50,
  X9 = 51,
  X10 = 52,
  X11 = 53,
  X12 = 54,
  X13 = 55,
  X14 = 56,
  X15 = 57,
  X16 = 58,
  X17 = 59,
  X18 = 60,
  X19 = 61,
  X20 = 62,
  X21 = 63,
  X22 = 64,
  X23 = 65,
  X24 = 66,
  X25 = 67,
  X26 = 68,
  X27 = 69,
  X28 = 70,
  X29 = 71,
  X30 = 72,
  X31 = 73,
  F0_D = 74,
  F1_D = 75,
  F2_D = 76,
  F3_D = 77,
  F4_D = 78,
  F5_D = 79,
  F6_D = 80,
  F7_D = 81,
  F8_D = 82,
  F9_D = 83,
  F10_D = 84,
  F11_D = 85,
  F12_D = 86,
  F13_D = 87,
  F14_D = 88,
  F15_D = 89,
  F16_D = 90,
  F17_D = 91,
  F18_D = 92,
  F19_D = 93,
  F20_D = 94,
  F21_D = 95,
  F22_D = 96,
  F23_D = 97,
  F24_D = 98,
  F25_D = 99,
  F26_D = 100,
  F27_D = 101,
  F28_D = 102,
  F29_D = 103,
  F30_D = 104,
  F31_D = 105,
  F0_F = 106,
  F1_F = 107,
  F2_F = 108,
  F3_F = 109,
  F4_F = 110,
  F5_F = 111,
  F6_F = 112,
  F7_F = 113,
  F8_F = 114,
  F9_F = 115,
  F10_F = 116,
  F11_F = 117,
  F12_F = 118,
  F13_F = 119,
  F14_F = 120,
  F15_F = 121,
  F16_F = 122,
  F17_F = 123,
  F18_F = 124,
  F19_F = 125,
  F20_F = 126,
  F21_F = 127,
  F22_F = 128,
  F23_F = 129,
  F24_F = 130,
  F25_F = 131,
  F26_F = 132,
  F27_F = 133,
  F28_F = 134,
  F29_F = 135,
  F30_F = 136,
  F31_F = 137,
  F0_H = 138,
  F1_H = 139,
  F2_H = 140,
  F3_H = 141,
  F4_H = 142,
  F5_H = 143,
  F6_H = 144,
  F7_H = 145,
  F8_H = 146,
  F9_H = 147,
  F10_H = 148,
  F11_H = 149,
  F12_H = 150,
  F13_H = 151,
  F14_H = 152,
  F15_H = 153,
  F16_H = 154,
  F17_H = 155,
  F18_H = 156,
  F19_H = 157,
  F20_H = 158,
  F21_H = 159,
  F22_H = 160,
  F23_H = 161,
  F24_H = 162,
  F25_H = 163,
  F26_H = 164,
  F27_H = 165,
  F28_H = 166,
  F29_H = 167,
  F30_H = 168,
  F31_H = 169,
  X0_Pair = 170,
  V0M2 = 171,
  V0M4 = 172,
  V0M8 = 173,
  V2M2 = 174,
  V4M2 = 175,
  V4M4 = 176,
  V6M2 = 177,
  V8M2 = 178,
  V8M4 = 179,
  V8M8 = 180,
  V10M2 = 181,
  V12M2 = 182,
  V12M4 = 183,
  V14M2 = 184,
  V16M2 = 185,
  V16M4 = 186,
  V16M8 = 187,
  V18M2 = 188,
  V20M2 = 189,
  V20M4 = 190,
  V22M2 = 191,
  V24M2 = 192,
  V24M4 = 193,
  V24M8 = 194,
  V26M2 = 195,
  V28M2 = 196,
  V28M4 = 197,
  V30M2 = 198,
  X2_X3 = 199,
  X4_X5 = 200,
  X6_X7 = 201,
  X8_X9 = 202,
  X10_X11 = 203,
  X12_X13 = 204,
  X14_X15 = 205,
  X16_X17 = 206,
  X18_X19 = 207,
  X20_X21 = 208,
  X22_X23 = 209,
  X24_X25 = 210,
  X26_X27 = 211,
  X28_X29 = 212,
  X30_X31 = 213,
  V1_V2 = 214,
  V2_V3 = 215,
  V3_V4 = 216,
  V4_V5 = 217,
  V5_V6 = 218,
  V6_V7 = 219,
  V7_V8 = 220,
  V8_V9 = 221,
  V9_V10 = 222,
  V10_V11 = 223,
  V11_V12 = 224,
  V12_V13 = 225,
  V13_V14 = 226,
  V14_V15 = 227,
  V15_V16 = 228,
  V16_V17 = 229,
  V17_V18 = 230,
  V18_V19 = 231,
  V19_V20 = 232,
  V20_V21 = 233,
  V21_V22 = 234,
  V22_V23 = 235,
  V23_V24 = 236,
  V24_V25 = 237,
  V25_V26 = 238,
  V26_V27 = 239,
  V27_V28 = 240,
  V28_V29 = 241,
  V29_V30 = 242,
  V30_V31 = 243,
  V0_V1 = 244,
  V2M2_V4M2 = 245,
  V4M2_V6M2 = 246,
  V6M2_V8M2 = 247,
  V8M2_V10M2 = 248,
  V10M2_V12M2 = 249,
  V12M2_V14M2 = 250,
  V14M2_V16M2 = 251,
  V16M2_V18M2 = 252,
  V18M2_V20M2 = 253,
  V20M2_V22M2 = 254,
  V22M2_V24M2 = 255,
  V24M2_V26M2 = 256,
  V26M2_V28M2 = 257,
  V28M2_V30M2 = 258,
  V0M2_V2M2 = 259,
  V4M4_V8M4 = 260,
  V8M4_V12M4 = 261,
  V12M4_V16M4 = 262,
  V16M4_V20M4 = 263,
  V20M4_V24M4 = 264,
  V24M4_V28M4 = 265,
  V0M4_V4M4 = 266,
  V1_V2_V3 = 267,
  V2_V3_V4 = 268,
  V3_V4_V5 = 269,
  V4_V5_V6 = 270,
  V5_V6_V7 = 271,
  V6_V7_V8 = 272,
  V7_V8_V9 = 273,
  V8_V9_V10 = 274,
  V9_V10_V11 = 275,
  V10_V11_V12 = 276,
  V11_V12_V13 = 277,
  V12_V13_V14 = 278,
  V13_V14_V15 = 279,
  V14_V15_V16 = 280,
  V15_V16_V17 = 281,
  V16_V17_V18 = 282,
  V17_V18_V19 = 283,
  V18_V19_V20 = 284,
  V19_V20_V21 = 285,
  V20_V21_V22 = 286,
  V21_V22_V23 = 287,
  V22_V23_V24 = 288,
  V23_V24_V25 = 289,
  V24_V25_V26 = 290,
  V25_V26_V27 = 291,
  V26_V27_V28 = 292,
  V27_V28_V29 = 293,
  V28_V29_V30 = 294,
  V29_V30_V31 = 295,
  V0_V1_V2 = 296,
  V2M2_V4M2_V6M2 = 297,
  V4M2_V6M2_V8M2 = 298,
  V6M2_V8M2_V10M2 = 299,
  V8M2_V10M2_V12M2 = 300,
  V10M2_V12M2_V14M2 = 301,
  V12M2_V14M2_V16M2 = 302,
  V14M2_V16M2_V18M2 = 303,
  V16M2_V18M2_V20M2 = 304,
  V18M2_V20M2_V22M2 = 305,
  V20M2_V22M2_V24M2 = 306,
  V22M2_V24M2_V26M2 = 307,
  V24M2_V26M2_V28M2 = 308,
  V26M2_V28M2_V30M2 = 309,
  V0M2_V2M2_V4M2 = 310,
  V1_V2_V3_V4 = 311,
  V2_V3_V4_V5 = 312,
  V3_V4_V5_V6 = 313,
  V4_V5_V6_V7 = 314,
  V5_V6_V7_V8 = 315,
  V6_V7_V8_V9 = 316,
  V7_V8_V9_V10 = 317,
  V8_V9_V10_V11 = 318,
  V9_V10_V11_V12 = 319,
  V10_V11_V12_V13 = 320,
  V11_V12_V13_V14 = 321,
  V12_V13_V14_V15 = 322,
  V13_V14_V15_V16 = 323,
  V14_V15_V16_V17 = 324,
  V15_V16_V17_V18 = 325,
  V16_V17_V18_V19 = 326,
  V17_V18_V19_V20 = 327,
  V18_V19_V20_V21 = 328,
  V19_V20_V21_V22 = 329,
  V20_V21_V22_V23 = 330,
  V21_V22_V23_V24 = 331,
  V22_V23_V24_V25 = 332,
  V23_V24_V25_V26 = 333,
  V24_V25_V26_V27 = 334,
  V25_V26_V27_V28 = 335,
  V26_V27_V28_V29 = 336,
  V27_V28_V29_V30 = 337,
  V28_V29_V30_V31 = 338,
  V0_V1_V2_V3 = 339,
  V2M2_V4M2_V6M2_V8M2 = 340,
  V4M2_V6M2_V8M2_V10M2 = 341,
  V6M2_V8M2_V10M2_V12M2 = 342,
  V8M2_V10M2_V12M2_V14M2 = 343,
  V10M2_V12M2_V14M2_V16M2 = 344,
  V12M2_V14M2_V16M2_V18M2 = 345,
  V14M2_V16M2_V18M2_V20M2 = 346,
  V16M2_V18M2_V20M2_V22M2 = 347,
  V18M2_V20M2_V22M2_V24M2 = 348,
  V20M2_V22M2_V24M2_V26M2 = 349,
  V22M2_V24M2_V26M2_V28M2 = 350,
  V24M2_V26M2_V28M2_V30M2 = 351,
  V0M2_V2M2_V4M2_V6M2 = 352,
  V1_V2_V3_V4_V5 = 353,
  V2_V3_V4_V5_V6 = 354,
  V3_V4_V5_V6_V7 = 355,
  V4_V5_V6_V7_V8 = 356,
  V5_V6_V7_V8_V9 = 357,
  V6_V7_V8_V9_V10 = 358,
  V7_V8_V9_V10_V11 = 359,
  V8_V9_V10_V11_V12 = 360,
  V9_V10_V11_V12_V13 = 361,
  V10_V11_V12_V13_V14 = 362,
  V11_V12_V13_V14_V15 = 363,
  V12_V13_V14_V15_V16 = 364,
  V13_V14_V15_V16_V17 = 365,
  V14_V15_V16_V17_V18 = 366,
  V15_V16_V17_V18_V19 = 367,
  V16_V17_V18_V19_V20 = 368,
  V17_V18_V19_V20_V21 = 369,
  V18_V19_V20_V21_V22 = 370,
  V19_V20_V21_V22_V23 = 371,
  V20_V21_V22_V23_V24 = 372,
  V21_V22_V23_V24_V25 = 373,
  V22_V23_V24_V25_V26 = 374,
  V23_V24_V25_V26_V27 = 375,
  V24_V25_V26_V27_V28 = 376,
  V25_V26_V27_V28_V29 = 377,
  V26_V27_V28_V29_V30 = 378,
  V27_V28_V29_V30_V31 = 379,
  V0_V1_V2_V3_V4 = 380,
  V1_V2_V3_V4_V5_V6 = 381,
  V2_V3_V4_V5_V6_V7 = 382,
  V3_V4_V5_V6_V7_V8 = 383,
  V4_V5_V6_V7_V8_V9 = 384,
  V5_V6_V7_V8_V9_V10 = 385,
  V6_V7_V8_V9_V10_V11 = 386,
  V7_V8_V9_V10_V11_V12 = 387,
  V8_V9_V10_V11_V12_V13 = 388,
  V9_V10_V11_V12_V13_V14 = 389,
  V10_V11_V12_V13_V14_V15 = 390,
  V11_V12_V13_V14_V15_V16 = 391,
  V12_V13_V14_V15_V16_V17 = 392,
  V13_V14_V15_V16_V17_V18 = 393,
  V14_V15_V16_V17_V18_V19 = 394,
  V15_V16_V17_V18_V19_V20 = 395,
  V16_V17_V18_V19_V20_V21 = 396,
  V17_V18_V19_V20_V21_V22 = 397,
  V18_V19_V20_V21_V22_V23 = 398,
  V19_V20_V21_V22_V23_V24 = 399,
  V20_V21_V22_V23_V24_V25 = 400,
  V21_V22_V23_V24_V25_V26 = 401,
  V22_V23_V24_V25_V26_V27 = 402,
  V23_V24_V25_V26_V27_V28 = 403,
  V24_V25_V26_V27_V28_V29 = 404,
  V25_V26_V27_V28_V29_V30 = 405,
  V26_V27_V28_V29_V30_V31 = 406,
  V0_V1_V2_V3_V4_V5 = 407,
  V1_V2_V3_V4_V5_V6_V7 = 408,
  V2_V3_V4_V5_V6_V7_V8 = 409,
  V3_V4_V5_V6_V7_V8_V9 = 410,
  V4_V5_V6_V7_V8_V9_V10 = 411,
  V5_V6_V7_V8_V9_V10_V11 = 412,
  V6_V7_V8_V9_V10_V11_V12 = 413,
  V7_V8_V9_V10_V11_V12_V13 = 414,
  V8_V9_V10_V11_V12_V13_V14 = 415,
  V9_V10_V11_V12_V13_V14_V15 = 416,
  V10_V11_V12_V13_V14_V15_V16 = 417,
  V11_V12_V13_V14_V15_V16_V17 = 418,
  V12_V13_V14_V15_V16_V17_V18 = 419,
  V13_V14_V15_V16_V17_V18_V19 = 420,
  V14_V15_V16_V17_V18_V19_V20 = 421,
  V15_V16_V17_V18_V19_V20_V21 = 422,
  V16_V17_V18_V19_V20_V21_V22 = 423,
  V17_V18_V19_V20_V21_V22_V23 = 424,
  V18_V19_V20_V21_V22_V23_V24 = 425,
  V19_V20_V21_V22_V23_V24_V25 = 426,
  V20_V21_V22_V23_V24_V25_V26 = 427,
  V21_V22_V23_V24_V25_V26_V27 = 428,
  V22_V23_V24_V25_V26_V27_V28 = 429,
  V23_V24_V25_V26_V27_V28_V29 = 430,
  V24_V25_V26_V27_V28_V29_V30 = 431,
  V25_V26_V27_V28_V29_V30_V31 = 432,
  V0_V1_V2_V3_V4_V5_V6 = 433,
  V1_V2_V3_V4_V5_V6_V7_V8 = 434,
  V2_V3_V4_V5_V6_V7_V8_V9 = 435,
  V3_V4_V5_V6_V7_V8_V9_V10 = 436,
  V4_V5_V6_V7_V8_V9_V10_V11 = 437,
  V5_V6_V7_V8_V9_V10_V11_V12 = 438,
  V6_V7_V8_V9_V10_V11_V12_V13 = 439,
  V7_V8_V9_V10_V11_V12_V13_V14 = 440,
  V8_V9_V10_V11_V12_V13_V14_V15 = 441,
  V9_V10_V11_V12_V13_V14_V15_V16 = 442,
  V10_V11_V12_V13_V14_V15_V16_V17 = 443,
  V11_V12_V13_V14_V15_V16_V17_V18 = 444,
  V12_V13_V14_V15_V16_V17_V18_V19 = 445,
  V13_V14_V15_V16_V17_V18_V19_V20 = 446,
  V14_V15_V16_V17_V18_V19_V20_V21 = 447,
  V15_V16_V17_V18_V19_V20_V21_V22 = 448,
  V16_V17_V18_V19_V20_V21_V22_V23 = 449,
  V17_V18_V19_V20_V21_V22_V23_V24 = 450,
  V18_V19_V20_V21_V22_V23_V24_V25 = 451,
  V19_V20_V21_V22_V23_V24_V25_V26 = 452,
  V20_V21_V22_V23_V24_V25_V26_V27 = 453,
  V21_V22_V23_V24_V25_V26_V27_V28 = 454,
  V22_V23_V24_V25_V26_V27_V28_V29 = 455,
  V23_V24_V25_V26_V27_V28_V29_V30 = 456,
  V24_V25_V26_V27_V28_V29_V30_V31 = 457,
  V0_V1_V2_V3_V4_V5_V6_V7 = 458,
  NUM_TARGET_REGS // 459
};
} // end namespace RISCV

// Register classes

namespace RISCV {
enum {
  FPR16RegClassID = 0,
  GPRAllRegClassID = 1,
  FPR32RegClassID = 2,
  GPRRegClassID = 3,
  GPRF16RegClassID = 4,
  GPRF32RegClassID = 5,
  GPRNoX0RegClassID = 6,
  GPRNoX0X2RegClassID = 7,
  GPRJALRRegClassID = 8,
  GPRTCRegClassID = 9,
  FPR32CRegClassID = 10,
  GPRCRegClassID = 11,
  SR07RegClassID = 12,
  GPRC_and_GPRTCRegClassID = 13,
  VCSRRegClassID = 14,
  GPRC_and_SR07RegClassID = 15,
  GPRX1X5RegClassID = 16,
  GPRX0RegClassID = 17,
  GPRX1RegClassID = 18,
  GPRX5RegClassID = 19,
  SPRegClassID = 20,
  FPR64RegClassID = 21,
  VMRegClassID = 22,
  VRRegClassID = 23,
  VRNoV0RegClassID = 24,
  GPRPairRegClassID = 25,
  GPRPair_with_sub_gpr_even_in_GPRNoX0RegClassID = 26,
  GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID = 27,
  GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID = 28,
  FPR64CRegClassID = 29,
  GPRPair_with_sub_gpr_even_in_GPRTCRegClassID = 30,
  GPRPair_with_sub_gpr_even_in_GPRCRegClassID = 31,
  GPRPair_with_sub_gpr_even_in_SR07RegClassID = 32,
  GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID = 33,
  GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID = 34,
  GPRPair_with_sub_gpr_even_in_GPRX0RegClassID = 35,
  GPRPair_with_sub_gpr_even_in_SPRegClassID = 36,
  GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID = 37,
  VMV0RegClassID = 38,
  VRN2M1RegClassID = 39,
  VRN2M1NoV0RegClassID = 40,
  VRM2RegClassID = 41,
  VRM2NoV0RegClassID = 42,
  VRM2_with_sub_vrm1_0_in_VMV0RegClassID = 43,
  VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID = 44,
  VRN3M1RegClassID = 45,
  VRN3M1NoV0RegClassID = 46,
  VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID = 47,
  VRN4M1RegClassID = 48,
  VRN4M1NoV0RegClassID = 49,
  VRN2M2RegClassID = 50,
  VRN2M2NoV0RegClassID = 51,
  VRM4RegClassID = 52,
  VRM4NoV0RegClassID = 53,
  VRM4_with_sub_vrm1_0_in_VMV0RegClassID = 54,
  VRN2M2_with_sub_vrm1_0_in_VMV0RegClassID = 55,
  VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID = 56,
  VRN5M1RegClassID = 57,
  VRN5M1NoV0RegClassID = 58,
  VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID = 59,
  VRN6M1RegClassID = 60,
  VRN6M1NoV0RegClassID = 61,
  VRN3M2RegClassID = 62,
  VRN3M2NoV0RegClassID = 63,
  VRN3M2_with_sub_vrm1_0_in_VMV0RegClassID = 64,
  VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID = 65,
  VRN7M1RegClassID = 66,
  VRN7M1NoV0RegClassID = 67,
  VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID = 68,
  VRN8M1RegClassID = 69,
  VRN8M1NoV0RegClassID = 70,
  VRN4M2RegClassID = 71,
  VRN4M2NoV0RegClassID = 72,
  VRN2M4RegClassID = 73,
  VRN2M4NoV0RegClassID = 74,
  VRM8RegClassID = 75,
  VRM8NoV0RegClassID = 76,
  VRM8_with_sub_vrm1_0_in_VMV0RegClassID = 77,
  VRN2M4_with_sub_vrm1_0_in_VMV0RegClassID = 78,
  VRN4M2_with_sub_vrm1_0_in_VMV0RegClassID = 79,
  VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID = 80,

};
} // end namespace RISCV


// Register alternate name indices

namespace RISCV {
enum {
  ABIRegAltName,  // 0
  NoRegAltName, // 1
  NUM_TARGET_REG_ALT_NAMES = 2
};
} // end namespace RISCV


// Subregister indices

namespace RISCV {
enum : uint16_t {
  NoSubRegister,
  sub_16, // 1
  sub_32, // 2
  sub_gpr_even, // 3
  sub_gpr_odd,  // 4
  sub_vrm1_0, // 5
  sub_vrm1_1, // 6
  sub_vrm1_2, // 7
  sub_vrm1_3, // 8
  sub_vrm1_4, // 9
  sub_vrm1_5, // 10
  sub_vrm1_6, // 11
  sub_vrm1_7, // 12
  sub_vrm2_0, // 13
  sub_vrm2_1, // 14
  sub_vrm2_2, // 15
  sub_vrm2_3, // 16
  sub_vrm4_0, // 17
  sub_vrm4_1, // 18
  sub_vrm1_0_sub_vrm1_1,  // 19
  sub_vrm1_0_sub_vrm1_1_sub_vrm1_2, // 20
  sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3,  // 21
  sub_vrm1_1_sub_vrm1_2,  // 22
  sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, // 23
  sub_vrm1_2_sub_vrm1_3,  // 24
  sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 25
  sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5,  // 26
  sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 27
  sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7,  // 28
  sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4,  // 29
  sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 30
  sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6,  // 31
  sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 32
  sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, // 33
  sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5,  // 34
  sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 35
  sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7,  // 36
  sub_vrm1_3_sub_vrm1_4,  // 37
  sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, // 38
  sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6,  // 39
  sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 40
  sub_vrm1_4_sub_vrm1_5,  // 41
  sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, // 42
  sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7,  // 43
  sub_vrm1_5_sub_vrm1_6,  // 44
  sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, // 45
  sub_vrm1_6_sub_vrm1_7,  // 46
  sub_vrm2_0_sub_vrm2_1,  // 47
  sub_vrm2_0_sub_vrm2_1_sub_vrm2_2, // 48
  sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3,  // 49
  sub_vrm2_1_sub_vrm2_2,  // 50
  sub_vrm2_1_sub_vrm2_2_sub_vrm2_3, // 51
  sub_vrm2_2_sub_vrm2_3,  // 52
  NUM_TARGET_SUBREGS
};
} // end namespace RISCV

// Register pressure sets enum.
namespace RISCV {
enum RegisterPressureSets {
  GPRC_and_SR07 = 0,
  GPRX0 = 1,
  SP = 2,
  GPRX1 = 3,
  FPR32C = 4,
  GPRC = 5,
  SR07 = 6,
  VMV0 = 7,
  GPRC_with_SR07 = 8,
  GPRTC = 9,
  VRM8NoV0 = 10,
  FPR16 = 11,
  VM = 12,
  GPR = 13,
};
} // end namespace RISCV

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t RISCVRegDiffLists[] = {
  /* 0 */ -105, 0,
  /* 2 */ -103, 0,
  /* 4 */ -101, 0,
  /* 6 */ -99, 0,
  /* 8 */ -97, 0,
  /* 10 */ -95, 0,
  /* 12 */ 25, -106, -86, 0,
  /* 16 */ 157, -1, -3, 49, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0,
  /* 31 */ 161, 1, 1, 71, 52, 43, -80, 121, 27, 26, 25, -148, 42, -86, 0,
  /* 46 */ -1, -3, 64, 51, 42, -86, 0,
  /* 53 */ 1, 1, 86, 51, 42, -86, 0,
  /* 60 */ -104, -85, 0,
  /* 63 */ -102, -84, 0,
  /* 66 */ -100, -83, 0,
  /* 69 */ -98, -82, 0,
  /* 72 */ -96, -81, 0,
  /* 75 */ -370, 1, 1, 1, 1, 230, 52, 43, -125, 53, -52, 96, -43, -52, 0,
  /* 90 */ -342, 1, 1, 1, 1, 199, 53, 44, -96, 53, -52, 96, -43, -52, 0,
  /* 105 */ -88, -161, 1, 163, -162, 1, 231, 52, 43, -125, 53, -52, 0,
  /* 118 */ -397, 1, 1, 1, 1, 1, 229, 52, 43, -125, 53, -52, 165, -69, 42, -85, 44, -96, 53, -52, 0,
  /* 139 */ -370, 1, 1, 1, 1, 1, 198, 53, 44, -96, 53, -52, 137, -41, 42, -85, 44, -96, 53, -52, 0,
  /* 160 */ -423, 1, 1, 1, 1, 1, 1, 228, 52, 43, -125, 53, -52, 165, 27, -96, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0,
  /* 188 */ -397, 1, 1, 1, 1, 1, 1, 197, 53, 44, -96, 53, -52, 137, 28, -69, 42, 28, -113, 44, 42, -138, 53, 44, -96, 53, -52, 0,
  /* 216 */ -448, 1, 1, 1, 1, 1, 1, 1, 227, 52, 43, -125, 53, -52, 165, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0,
  /* 252 */ -423, 1, 1, 1, 1, 1, 1, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, -96, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 0,
  /* 288 */ -71, -162, 1, 162, -161, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 301 */ -71, -161, 1, 162, -161, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 314 */ -70, -160, 1, 162, -161, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 327 */ -70, -161, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 340 */ -68, -161, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 353 */ -68, -160, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 366 */ -67, -159, 1, 161, -160, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 379 */ -67, -160, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 392 */ -65, -160, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 405 */ -65, -159, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 418 */ -64, -158, 1, 160, -159, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 431 */ -64, -159, 1, 159, -158, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 444 */ -62, -159, 1, 159, -158, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 457 */ -62, -158, 1, 159, -158, 1, 200, 53, 44, -96, 53, -52, 0,
  /* 470 */ -329, 1, 1, 1, 231, 52, -82, 53, -52, 0,
  /* 480 */ -300, 1, 1, 1, 200, 53, -52, 53, -52, 0,
  /* 490 */ -94, -1, -161, 1, 163, -162, 1, 163, -1, -161, 1, 162, -161, 1, 227, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, 42, -107, 52, -51, 0,
  /* 539 */ -72, -1, -158, 1, 160, -159, 1, 160, -1, -158, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, 43, -94, 52, -51, 0,
  /* 588 */ -74, -1, -159, 1, 160, -159, 1, 160, -1, -158, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, 43, -94, 52, -51, 0,
  /* 637 */ -77, -1, -159, 1, 161, -160, 1, 161, -1, -159, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, 43, -94, 52, -51, 0,
  /* 686 */ -79, -1, -160, 1, 161, -160, 1, 161, -1, -159, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, 43, -94, 52, -51, 0,
  /* 735 */ -82, -1, -160, 1, 162, -161, 1, 162, -1, -160, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, 43, -94, 52, -51, 0,
  /* 784 */ -84, -1, -161, 1, 162, -161, 1, 162, -1, -160, 1, 162, -161, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, 43, -94, 52, -51, 0,
  /* 833 */ -181, -161, 1, 163, -162, 1, 162, -161, 1, 162, -161, 1, 227, 52, 43, -125, 53, -52, 165, 27, 26, 25, -147, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 40, 51, -65, 52, -51, 0,
  /* 879 */ -159, -158, 1, 160, -159, 1, 159, -158, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 13, 52, -51, 52, -51, 0,
  /* 925 */ -159, -159, 1, 159, -158, 1, 160, -159, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 14, 52, -51, 52, -51, 0,
  /* 971 */ -160, -159, 1, 160, -159, 1, 159, -158, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 15, 52, -51, 52, -51, 0,
  /* 1017 */ -160, -160, 1, 160, -159, 1, 160, -159, 1, 159, -158, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 16, 52, -51, 52, -51, 0,
  /* 1063 */ -162, -159, 1, 161, -160, 1, 160, -159, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 17, 52, -51, 52, -51, 0,
  /* 1109 */ -162, -160, 1, 160, -159, 1, 161, -160, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 18, 52, -51, 52, -51, 0,
  /* 1155 */ -163, -160, 1, 161, -160, 1, 160, -159, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 19, 52, -51, 52, -51, 0,
  /* 1201 */ -163, -161, 1, 161, -160, 1, 161, -160, 1, 160, -159, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 20, 52, -51, 52, -51, 0,
  /* 1247 */ -165, -160, 1, 162, -161, 1, 161, -160, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 21, 52, -51, 52, -51, 0,
  /* 1293 */ -165, -161, 1, 161, -160, 1, 162, -161, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 22, 52, -51, 52, -51, 0,
  /* 1339 */ -166, -161, 1, 162, -161, 1, 161, -160, 1, 162, -161, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 23, 52, -51, 52, -51, 0,
  /* 1385 */ -166, -162, 1, 162, -161, 1, 162, -161, 1, 161, -160, 1, 196, 53, 44, -96, 53, -52, 137, 28, 27, 26, -122, 42, 28, 27, -140, 44, 42, 28, -166, 53, 44, 42, -138, 53, 44, -96, 53, -52, 24, 52, -51, 52, -51, 0,
  /* 1431 */ -128, -33, 0,
  /* 1434 */ -32, -32, 0,
  /* 1437 */ -286, 1, 1, 232, -30, 0,
  /* 1443 */ -139, -161, 1, 163, -162, 1, 162, -161, 1, 229, 52, 43, -125, 53, -52, 165, 27, -96, 42, -85, 44, -96, 53, -52, 42, -14, 0,
  /* 1470 */ -234, 1, 0,
  /* 1473 */ -203, 1, 0,
  /* 1476 */ -1, -161, 1, 163, -162, 1, 0,
  /* 1483 */ -1, -1, -161, 1, 163, -162, 1, 163, -1, -161, 1, 162, -161, 1, 0,
  /* 1498 */ -1, -160, 1, 162, -161, 1, 0,
  /* 1505 */ -1, -1, -160, 1, 162, -161, 1, 162, -1, -160, 1, 161, -160, 1, 0,
  /* 1520 */ -1, -159, 1, 161, -160, 1, 0,
  /* 1527 */ -1, -1, -159, 1, 161, -160, 1, 161, -1, -159, 1, 160, -159, 1, 0,
  /* 1542 */ -1, -158, 1, 160, -159, 1, 0,
  /* 1549 */ -1, -1, -158, 1, 160, -159, 1, 160, -1, -158, 1, 159, -158, 1, 0,
  /* 1564 */ -155, 1, 0,
  /* 1567 */ -154, 1, 0,
  /* 1570 */ -153, 1, 0,
  /* 1573 */ -152, 1, 0,
  /* 1576 */ -151, 1, 0,
  /* 1579 */ -150, 1, 0,
  /* 1582 */ -149, 1, 0,
  /* 1585 */ -148, 1, 0,
  /* 1588 */ -147, 1, 0,
  /* 1591 */ -146, 1, 0,
  /* 1594 */ -145, 1, 0,
  /* 1597 */ -144, 1, 0,
  /* 1600 */ -143, 1, 0,
  /* 1603 */ -142, 1, 0,
  /* 1606 */ -141, 1, 0,
  /* 1609 */ 1, 1, 1, 1, 1, 1, 1, 0,
  /* 1617 */ -114, -159, 1, 159, -158, 1, 159, -158, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 14, 1, 0,
  /* 1644 */ -116, -158, 1, 160, -159, 1, 159, -158, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 15, 1, 0,
  /* 1671 */ -116, -159, 1, 159, -158, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 16, 1, 0,
  /* 1698 */ -117, -159, 1, 160, -159, 1, 159, -158, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 17, 1, 0,
  /* 1725 */ -117, -160, 1, 160, -159, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 18, 1, 0,
  /* 1752 */ -119, -159, 1, 161, -160, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 19, 1, 0,
  /* 1779 */ -119, -160, 1, 160, -159, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 20, 1, 0,
  /* 1806 */ -120, -160, 1, 161, -160, 1, 160, -159, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 21, 1, 0,
  /* 1833 */ -120, -161, 1, 161, -160, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 22, 1, 0,
  /* 1860 */ -122, -160, 1, 162, -161, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 23, 1, 0,
  /* 1887 */ -122, -161, 1, 161, -160, 1, 162, -161, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 24, 1, 0,
  /* 1914 */ -123, -161, 1, 162, -161, 1, 161, -160, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 25, 1, 0,
  /* 1941 */ -123, -162, 1, 162, -161, 1, 162, -161, 1, 198, 53, 44, -96, 53, -52, 137, 28, -69, 42, -85, 44, -96, 53, -52, 26, 1, 0,
  /* 1968 */ 1, 70, 1, 0,
  /* 1972 */ 1, 75, 1, 0,
  /* 1976 */ -3, 76, 1, 0,
  /* 1980 */ 1, 80, 1, 0,
  /* 1984 */ -3, 81, 1, 0,
  /* 1988 */ -256, 1, 1, 201, 1, 0,
  /* 1994 */ 161, -2, 1, 42, 1, 51, 1, 43, -70, 28, 44, -71, 68, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 92, 2, 2, 2, 0,
  /* 2044 */ 160, -1, -3, 46, 1, 51, 43, -68, 26, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0,
  /* 2094 */ 160, 1, 1, 40, 1, 51, 1, 43, -69, 27, 44, -70, 67, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 122, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0,
  /* 2144 */ 52, 1, 43, -69, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 47, 26, 1, 25, -97, 92, 2, 2, 2, 0,
  /* 2179 */ 160, -1, -3, 46, 1, 51, 1, 43, -72, 30, 44, -73, 70, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 94, 2, 2, 2, 0,
  /* 2229 */ 160, 1, -3, 44, 1, 51, 1, 43, -71, 29, 44, -72, 69, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 125, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0,
  /* 2279 */ 160, -2, 1, 43, 1, 51, 43, -70, 28, 1, 43, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0,
  /* 2329 */ 52, 1, 43, -71, 70, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 49, 26, 1, 25, -99, 94, 2, 2, 2, 0,
  /* 2364 */ 159, 1, 1, 41, 1, 51, 43, -69, 27, 1, 43, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 2, 0,
  /* 2414 */ 52, 1, 43, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 2, 0,
  /* 2450 */ 160, -2, 1, 43, 1, 51, 1, 43, -74, 32, 44, -75, 72, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 96, 2, 2, 2, 0,
  /* 2500 */ 159, 1, 1, 41, 1, 51, 1, 43, -73, 31, 44, -74, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 128, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0,
  /* 2550 */ 159, -1, -3, 47, 1, 51, 43, -72, 30, 1, 43, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0,
  /* 2600 */ 52, 1, 43, -73, 72, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 51, 26, 1, 25, -101, 96, 2, 2, 2, 0,
  /* 2635 */ 159, 1, -3, 45, 1, 51, 43, -71, 29, 1, 43, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 2, 0,
  /* 2685 */ 52, 1, 43, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 2, 0,
  /* 2721 */ 159, -1, -3, 47, 1, 51, 1, 43, -76, 34, 44, -77, 74, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 98, 2, 2, 2, 0,
  /* 2771 */ 159, 1, -3, 45, 1, 51, 1, 43, -75, 33, 44, -76, 73, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 131, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0,
  /* 2821 */ 159, -2, 1, 44, 1, 51, 43, -74, 32, 1, 43, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0,
  /* 2871 */ 52, 1, 43, -75, 74, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 53, 26, 1, 25, -103, 98, 2, 2, 2, 0,
  /* 2906 */ 158, 1, 1, 42, 1, 51, 43, -73, 31, 1, 43, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 2, 0,
  /* 2956 */ 52, 1, 43, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 2, 0,
  /* 2992 */ 158, 1, 1, 42, 1, 51, 1, 43, -77, 35, 44, -78, 75, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 134, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0,
  /* 3042 */ 158, -1, -3, 48, 1, 51, 43, -76, 34, 1, 43, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0,
  /* 3092 */ 52, 1, 43, -77, 76, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 55, 26, 1, 25, -105, 100, 2, 2, 2, 0,
  /* 3127 */ 158, 1, -3, 46, 1, 51, 43, -75, 33, 1, 43, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 2, 0,
  /* 3177 */ 52, 1, 43, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 2, 0,
  /* 3213 */ 161, -1, -3, 45, 1, 51, 1, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0,
  /* 3262 */ 52, 43, -68, 26, 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0,
  /* 3301 */ 44, -69, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 123, 26, 1, 25, -95, 73, 26, -97, 92, 2, 2, 0,
  /* 3329 */ 52, 43, -70, 28, 44, -71, 110, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0,
  /* 3368 */ 44, -71, 70, 41, 1, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 126, 26, 1, 25, -97, 75, 26, -99, 94, 2, 2, 0,
  /* 3396 */ 52, 43, -69, 27, 44, -70, 109, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 100, 28, 27, 26, -141, 43, -82, 149, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0,
  /* 3435 */ 43, -69, 110, 27, -67, 41, 27, 26, -52, 27, 26, 25, -139, 1, 42, -81, 150, 25, -95, 47, 26, 1, 25, -97, 94, 2, 2, 0,
  /* 3463 */ 44, -70, 69, 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 94, 2, 2, 0,
  /* 3492 */ 41, 27, 26, -52, 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 94, 2, 2, 0,
  /* 3511 */ 52, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0,
  /* 3546 */ 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0,
  /* 3575 */ 160, 1, -3, 44, 1, 51, 43, -67, 25, 1, 43, -68, 69, 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 2, 0,
  /* 3621 */ 41, 1, 27, 1, 26, 1, 25, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 2, 0,
  /* 3640 */ 52, 43, -72, 30, 44, -73, 112, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0,
  /* 3679 */ 44, -73, 72, 41, 1, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 129, 26, 1, 25, -99, 77, 26, -101, 96, 2, 2, 0,
  /* 3707 */ 52, 43, -71, 29, 44, -72, 111, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 103, 28, 27, 26, -143, 43, -83, 152, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0,
  /* 3746 */ 43, -71, 112, 27, -67, 41, 27, 26, -52, 27, 26, 25, -141, 1, 42, -82, 153, 25, -97, 49, 26, 1, 25, -99, 96, 2, 2, 0,
  /* 3774 */ 44, -72, 71, 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 96, 2, 2, 0,
  /* 3803 */ 41, 27, 26, -52, 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 96, 2, 2, 0,
  /* 3822 */ 43, -70, 111, 27, 26, 25, -138, 42, -81, 59, 41, 1, 27, 1, 26, 1, 25, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 2, 0,
  /* 3851 */ 52, 43, -74, 32, 44, -75, 114, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0,
  /* 3890 */ 44, -75, 74, 41, 1, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 132, 26, 1, 25, -101, 79, 26, -103, 98, 2, 2, 0,
  /* 3918 */ 52, 43, -73, 31, 44, -74, 113, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 106, 28, 27, 26, -145, 43, -84, 155, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0,
  /* 3957 */ 43, -73, 114, 27, -67, 41, 27, 26, -52, 27, 26, 25, -143, 1, 42, -83, 156, 25, -99, 51, 26, 1, 25, -101, 98, 2, 2, 0,
  /* 3985 */ 44, -74, 73, 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 98, 2, 2, 0,
  /* 4014 */ 41, 27, 26, -52, 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 98, 2, 2, 0,
  /* 4033 */ 43, -72, 113, 27, 26, 25, -140, 42, -82, 62, 41, 1, 27, 1, 26, 1, 25, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 2, 0,
  /* 4062 */ 52, 43, -76, 34, 44, -77, 116, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0,
  /* 4101 */ 44, -77, 76, 41, 1, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 135, 26, 1, 25, -103, 81, 26, -105, 100, 2, 2, 0,
  /* 4129 */ 52, 43, -75, 33, 44, -76, 115, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 109, 28, 27, 26, -147, 43, -85, 158, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0,
  /* 4168 */ 43, -75, 116, 27, -67, 41, 27, 26, -52, 27, 26, 25, -145, 1, 42, -84, 159, 25, -101, 53, 26, 1, 25, -103, 100, 2, 2, 0,
  /* 4196 */ 44, -76, 75, 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 100, 2, 2, 0,
  /* 4225 */ 41, 27, 26, -52, 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 100, 2, 2, 0,
  /* 4244 */ 43, -74, 115, 27, 26, 25, -142, 42, -83, 65, 41, 1, 27, 1, 26, 1, 25, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 2, 0,
  /* 4273 */ 157, 1, 1, 43, 1, 51, 43, -77, 35, 1, 43, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4322 */ 52, 43, -77, 35, 44, -78, 117, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 112, 28, 27, 26, -149, 43, -86, 161, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4361 */ 43, -77, 118, 27, -67, 41, 27, 26, -52, 27, 26, 25, -147, 1, 42, -85, 162, 25, -103, 55, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4389 */ 159, -2, 1, 44, 1, 51, 1, 43, -78, 36, 44, -79, 76, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4435 */ 52, 1, 43, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4470 */ 44, -78, 77, 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4499 */ 41, 27, 26, -52, 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 102, 2, 2, 0,
  /* 4518 */ 43, -76, 117, 27, 26, 25, -144, 42, -84, 68, 41, 1, 27, 1, 26, 1, 25, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 2, 0,
  /* 4547 */ -1, -3, 73, 1, 51, 1, 42, -81, 37, 55, -86, 74, 2, 0,
  /* 4561 */ 1, 1, 67, 1, 50, 1, 42, -81, 40, 43, -82, 79, 2, 0,
  /* 4575 */ 1, -3, 69, 1, 50, 1, 42, -82, 41, 43, -83, 80, 2, 0,
  /* 4589 */ 51, 1, 42, -81, 80, 2, 0,
  /* 4596 */ 1, 1, 64, 1, 50, 1, 42, -83, 42, 43, -84, 81, 2, 0,
  /* 4610 */ -2, 1, 68, 1, 50, 42, -81, 40, 1, 42, -82, 81, 2, 0,
  /* 4624 */ 51, 1, 42, -82, 81, 2, 0,
  /* 4631 */ 1, -3, 66, 1, 50, 1, 42, -84, 43, 43, -85, 82, 2, 0,
  /* 4645 */ -1, -3, 70, 1, 50, 42, -82, 41, 1, 42, -83, 82, 2, 0,
  /* 4659 */ 51, 1, 42, -83, 82, 2, 0,
  /* 4666 */ 1, 1, 61, 1, 50, 1, 42, -85, 44, 43, -86, 83, 2, 0,
  /* 4680 */ -2, 1, 65, 1, 50, 42, -83, 42, 1, 42, -84, 83, 2, 0,
  /* 4694 */ 51, 1, 42, -84, 83, 2, 0,
  /* 4701 */ -1, -3, 67, 1, 50, 42, -84, 43, 1, 42, -85, 84, 2, 0,
  /* 4715 */ 51, 1, 42, -85, 84, 2, 0,
  /* 4722 */ -69, 110, 27, -26, 27, 26, -25, 26, 25, -139, 1, 42, -81, 150, 25, -95, 73, 26, -97, 94, 2, 0,
  /* 4744 */ 27, 26, -25, 26, 25, -138, 42, -81, 153, 26, -97, 94, 2, 0,
  /* 4758 */ 44, -68, 110, 28, 27, 26, -139, 43, -81, 53, 41, 27, 52, -78, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4786 */ -68, 110, 28, 27, 26, -139, 43, -81, 95, 27, 26, 50, -161, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4809 */ 161, 1, -3, 43, 1, 51, 1, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 51, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4852 */ 161, -2, 1, 42, 1, 52, 1, 43, -67, 22, 72, -80, 52, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4888 */ 52, 1, 43, -67, 66, 69, -27, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4916 */ 52, 43, -67, 25, 44, -68, 110, 28, 27, 26, -139, 43, -81, 93, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4951 */ 43, -67, 108, 54, -94, 41, 27, 52, -78, 27, 26, 50, -148, -13, 55, -86, 117, 26, 1, 25, -95, 94, 2, 0,
  /* 4975 */ 28, 27, 26, -139, 43, -81, 123, 26, 1, 25, -95, 94, 2, 0,
  /* 4989 */ -71, 112, 27, -26, 27, 26, -25, 26, 25, -141, 1, 42, -82, 153, 25, -97, 75, 26, -99, 96, 2, 0,
  /* 5011 */ 27, 26, -25, 26, 25, -140, 42, -82, 156, 26, -99, 96, 2, 0,
  /* 5025 */ -70, 111, 27, 26, 25, -138, 42, -81, 100, 28, 27, 26, -141, 43, -82, 126, 26, 1, 25, -97, 96, 2, 0,
  /* 5048 */ 27, 26, 25, -138, 42, -81, 127, 26, 1, 25, -97, 96, 2, 0,
  /* 5062 */ 27, 1, 26, 1, 25, -139, 43, -81, 150, 25, -95, 96, 2, 0,
  /* 5076 */ -73, 114, 27, -26, 27, 26, -25, 26, 25, -143, 1, 42, -83, 156, 25, -99, 77, 26, -101, 98, 2, 0,
  /* 5098 */ 27, 26, -25, 26, 25, -142, 42, -83, 159, 26, -101, 98, 2, 0,
  /* 5112 */ -72, 113, 27, 26, 25, -140, 42, -82, 103, 28, 27, 26, -143, 43, -83, 129, 26, 1, 25, -99, 98, 2, 0,
  /* 5135 */ 27, 26, 25, -140, 42, -82, 130, 26, 1, 25, -99, 98, 2, 0,
  /* 5149 */ 27, 1, 26, 1, 25, -141, 43, -82, 153, 25, -97, 98, 2, 0,
  /* 5163 */ -75, 116, 27, -26, 27, 26, -25, 26, 25, -145, 1, 42, -84, 159, 25, -101, 79, 26, -103, 100, 2, 0,
  /* 5185 */ 27, 26, -25, 26, 25, -144, 42, -84, 162, 26, -103, 100, 2, 0,
  /* 5199 */ -74, 115, 27, 26, 25, -142, 42, -83, 106, 28, 27, 26, -145, 43, -84, 132, 26, 1, 25, -101, 100, 2, 0,
  /* 5222 */ 27, 26, 25, -142, 42, -83, 133, 26, 1, 25, -101, 100, 2, 0,
  /* 5236 */ 27, 1, 26, 1, 25, -143, 43, -83, 156, 25, -99, 100, 2, 0,
  /* 5250 */ -77, 118, 27, -26, 27, 26, -25, 26, 25, -147, 1, 42, -85, 162, 25, -103, 81, 26, -105, 102, 2, 0,
  /* 5272 */ 27, 26, -25, 26, 25, -146, 42, -85, 165, 26, -105, 102, 2, 0,
  /* 5286 */ -76, 117, 27, 26, 25, -144, 42, -84, 109, 28, 27, 26, -147, 43, -85, 135, 26, 1, 25, -103, 102, 2, 0,
  /* 5309 */ 27, 26, 25, -144, 42, -84, 136, 26, 1, 25, -103, 102, 2, 0,
  /* 5323 */ 27, 1, 26, 1, 25, -145, 43, -84, 159, 25, -101, 102, 2, 0,
  /* 5337 */ 52, 43, -78, 36, 44, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5372 */ 44, -79, 78, 41, 1, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5396 */ 158, -2, 1, 45, 1, 51, 43, -78, 36, 1, 43, -79, 118, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5439 */ 158, 1, -3, 46, 1, 51, 1, 43, -79, 37, 44, -80, 77, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5475 */ 52, 1, 43, -79, 78, 41, 1, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5503 */ 43, -78, 119, 27, 26, 25, -146, 42, -85, 71, 41, 1, 27, 1, 26, 1, 25, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5531 */ -78, 119, 27, 26, 25, -146, 42, -85, 112, 28, 27, 26, -149, 43, -86, 138, 26, 1, 25, -105, 104, 2, 0,
  /* 5554 */ 27, 26, 25, -146, 42, -85, 139, 26, 1, 25, -105, 104, 2, 0,
  /* 5568 */ 27, 1, 26, 1, 25, -147, 43, -85, 162, 25, -103, 104, 2, 0,
  /* 5582 */ 26, 1, 25, -96, -81, 176, 2, 0,
  /* 5590 */ 26, 1, 25, -98, -82, 179, 2, 0,
  /* 5598 */ 26, 1, 25, -100, -83, 182, 2, 0,
  /* 5606 */ 26, 1, 25, -102, -84, 185, 2, 0,
  /* 5614 */ 26, 1, 25, -104, -85, 188, 2, 0,
  /* 5622 */ -3, 87, 6, 0,
  /* 5626 */ 32, 32, 0,
  /* 5629 */ 33, 0,
  /* 5631 */ -3, 71, 0,
  /* 5634 */ 1, -3, 72, 1, 52, 43, -81, 50, -13, 55, -86, 74, 0,
  /* 5647 */ -2, 1, 72, 14, 51, -13, 55, -86, 74, 0,
  /* 5657 */ 65, -13, 55, -86, 74, 0,
  /* 5663 */ 52, 43, -81, 37, 55, -86, 74, 0,
  /* 5671 */ 43, -81, 80, 0,
  /* 5675 */ 51, 42, -81, 40, 43, -82, 81, 0,
  /* 5683 */ 51, 42, -82, 41, 43, -83, 82, 0,
  /* 5691 */ 42, -81, 82, 0,
  /* 5695 */ 51, 42, -83, 42, 43, -84, 83, 0,
  /* 5703 */ 42, -82, 83, 0,
  /* 5707 */ 51, 42, -84, 43, 43, -85, 84, 0,
  /* 5715 */ 42, -83, 84, 0,
  /* 5719 */ -2, 1, 62, 1, 50, 42, -85, 44, 1, 42, -86, 85, 0,
  /* 5732 */ 1, -3, 63, 1, 50, 1, 42, -86, 85, 0,
  /* 5742 */ 51, 1, 42, -86, 85, 0,
  /* 5748 */ 51, 42, -85, 44, 43, -86, 85, 0,
  /* 5756 */ 42, -84, 85, 0,
  /* 5760 */ 42, -85, 86, 0,
  /* 5764 */ 1, 93, 0,
  /* 5767 */ 27, 52, -51, 26, 50, -161, 55, -86, 143, 26, -95, 94, 0,
  /* 5780 */ 162, -2, 1, 41, 1, 53, 44, -67, 51, -29, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
  /* 5811 */ 53, 44, -67, 22, 72, -80, 52, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
  /* 5836 */ 44, -67, 66, 69, -27, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
  /* 5857 */ -67, 108, 54, -53, 27, 52, -51, 26, 50, -148, -13, 55, -86, 143, 26, -95, 94, 0,
  /* 5875 */ 26, 25, -138, 42, -81, 153, 26, -97, 96, 0,
  /* 5885 */ 27, 26, -139, 43, -81, 150, 25, -95, 96, 0,
  /* 5895 */ 26, 25, -140, 42, -82, 156, 26, -99, 98, 0,
  /* 5905 */ 27, 26, -141, 43, -82, 153, 25, -97, 98, 0,
  /* 5915 */ 26, 25, -142, 42, -83, 159, 26, -101, 100, 0,
  /* 5925 */ 27, 26, -143, 43, -83, 156, 25, -99, 100, 0,
  /* 5935 */ 26, 25, -144, 42, -84, 162, 26, -103, 102, 0,
  /* 5945 */ 27, 26, -145, 43, -84, 159, 25, -101, 102, 0,
  /* 5955 */ 26, 25, -146, 42, -85, 165, 26, -105, 104, 0,
  /* 5965 */ 27, 26, -147, 43, -85, 162, 25, -103, 104, 0,
  /* 5975 */ -79, 120, 27, -26, 27, 26, -25, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
  /* 5993 */ 157, 1, -3, 47, 1, 51, 43, -79, 37, 1, 43, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
  /* 6024 */ 52, 43, -79, 37, 44, -80, 119, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
  /* 6049 */ 43, -79, 120, 27, -67, 41, 27, 26, -52, 27, 26, 25, -149, 1, 42, -86, 165, 25, -105, 106, 0,
  /* 6070 */ 27, 1, 26, 1, 25, -149, 43, -86, 165, 25, -105, 106, 0,
  /* 6083 */ 27, 26, -149, 43, -86, 165, 25, -105, 106, 0,
  /* 6093 */ 128, 0,
  /* 6095 */ 140, 0,
  /* 6097 */ 141, 0,
  /* 6099 */ 142, 0,
  /* 6101 */ 143, 0,
  /* 6103 */ 144, 0,
  /* 6105 */ 145, 0,
  /* 6107 */ 146, 0,
  /* 6109 */ 147, 0,
  /* 6111 */ 148, 0,
  /* 6113 */ 149, 0,
  /* 6115 */ 150, 0,
  /* 6117 */ 151, 0,
  /* 6119 */ 152, 0,
  /* 6121 */ 153, 0,
  /* 6123 */ 154, 0,
  /* 6125 */ 155, 0,
  /* 6127 */ 161, 0,
  /* 6129 */ 52, -25, 50, -106, -86, 168, 0,
  /* 6136 */ 160, 1, 1, 41, 30, 52, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0,
  /* 6158 */ 82, -29, 72, -80, 52, 69, -27, 54, -26, 52, -25, 50, -148, 42, -86, 168, 0,
  /* 6175 */ 26, -96, -81, 176, 0,
  /* 6180 */ 25, -96, -81, 178, 0,
  /* 6185 */ 26, -98, -82, 179, 0,
  /* 6190 */ 25, -98, -82, 181, 0,
  /* 6195 */ 26, -100, -83, 182, 0,
  /* 6200 */ 25, -100, -83, 184, 0,
  /* 6205 */ 26, -102, -84, 185, 0,
  /* 6210 */ 25, -102, -84, 187, 0,
  /* 6215 */ 26, -104, -85, 188, 0,
  /* 6220 */ 25, -104, -85, 190, 0,
  /* 6225 */ 26, 1, 25, -106, -86, 191, 0,
  /* 6232 */ 26, -106, -86, 191, 0,
  /* 6237 */ 27, 26, -25, 26, 25, -148, 42, -86, 191, 0,
  /* 6247 */ 158, -1, -3, 48, 1, 51, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0,
  /* 6269 */ 52, 1, 43, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0,
  /* 6286 */ 44, -80, 79, 41, 27, 26, -52, 27, 26, 25, -148, 42, -86, 191, 0,
};

extern const LaneBitmask RISCVLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask::getAll(),
  /* 2 */ LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
  /* 5 */ LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask::getAll(),
  /* 8 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask::getAll(),
  /* 11 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask::getAll(),
  /* 15 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask::getAll(),
  /* 20 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask::getAll(),
  /* 26 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask::getAll(),
  /* 33 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask::getAll(),
  /* 41 */ LaneBitmask(0x0000000000000008), LaneBitmask(0x0000000000000010), LaneBitmask(0x0000000000000020), LaneBitmask(0x0000000000000040), LaneBitmask(0x0000000000000080), LaneBitmask(0x0000000000000100), LaneBitmask(0x0000000000000200), LaneBitmask(0x0000000000000400), LaneBitmask::getAll(),
  /* 50 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t RISCVSubRegIdxLists[] = {
  /* 0 */ 2, 1, 0,
  /* 3 */ 3, 4, 0,
  /* 6 */ 5, 6, 0,
  /* 9 */ 13, 5, 6, 14, 7, 8, 0,
  /* 16 */ 17, 13, 5, 6, 14, 7, 8, 18, 15, 9, 10, 16, 11, 12, 0,
  /* 31 */ 5, 6, 7, 19, 22, 0,
  /* 37 */ 5, 6, 7, 8, 19, 20, 22, 23, 24, 0,
  /* 47 */ 13, 5, 6, 14, 7, 8, 19, 20, 21, 22, 23, 24, 0,
  /* 60 */ 5, 6, 7, 8, 9, 19, 20, 21, 22, 23, 24, 29, 33, 37, 0,
  /* 75 */ 5, 6, 7, 8, 9, 10, 19, 20, 21, 22, 23, 24, 25, 29, 30, 33, 34, 37, 38, 41, 0,
  /* 96 */ 5, 6, 7, 8, 9, 10, 11, 19, 20, 21, 22, 23, 24, 25, 26, 29, 30, 31, 33, 34, 35, 37, 38, 39, 41, 42, 44, 0,
  /* 124 */ 5, 6, 7, 8, 9, 10, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 0,
  /* 160 */ 13, 5, 6, 14, 7, 8, 15, 9, 10, 19, 20, 21, 22, 23, 24, 25, 26, 29, 30, 33, 34, 37, 38, 41, 47, 50, 0,
  /* 187 */ 13, 5, 6, 14, 7, 8, 15, 9, 10, 16, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 50, 51, 52, 0,
  /* 233 */ 17, 13, 5, 6, 14, 7, 8, 18, 15, 9, 10, 16, 11, 12, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 16 },  // sub_16
  { 0, 32 },  // sub_32
  { 0, 65535 }, // sub_gpr_even
  { 65535, 65535 }, // sub_gpr_odd
  { 0, 64 },  // sub_vrm1_0
  { 64, 64 }, // sub_vrm1_1
  { 128, 64 },  // sub_vrm1_2
  { 192, 64 },  // sub_vrm1_3
  { 256, 64 },  // sub_vrm1_4
  { 320, 64 },  // sub_vrm1_5
  { 384, 64 },  // sub_vrm1_6
  { 448, 64 },  // sub_vrm1_7
  { 0, 128 }, // sub_vrm2_0
  { 128, 128 }, // sub_vrm2_1
  { 256, 128 }, // sub_vrm2_2
  { 384, 128 }, // sub_vrm2_3
  { 0, 256 }, // sub_vrm4_0
  { 256, 256 }, // sub_vrm4_1
  { 0, 128 }, // sub_vrm1_0_sub_vrm1_1
  { 0, 192 }, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
  { 0, 256 }, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  { 64, 128 },  // sub_vrm1_1_sub_vrm1_2
  { 64, 192 },  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  { 128, 128 }, // sub_vrm1_2_sub_vrm1_3
  { 0, 320 }, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  { 0, 384 }, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  { 0, 448 }, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  { 0, 512 }, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  { 64, 256 },  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  { 64, 320 },  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  { 64, 384 },  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  { 64, 448 },  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  { 128, 192 }, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  { 128, 256 }, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  { 128, 320 }, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  { 128, 384 }, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  { 192, 128 }, // sub_vrm1_3_sub_vrm1_4
  { 192, 192 }, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  { 192, 256 }, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  { 192, 320 }, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  { 256, 128 }, // sub_vrm1_4_sub_vrm1_5
  { 256, 192 }, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  { 256, 256 }, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  { 320, 128 }, // sub_vrm1_5_sub_vrm1_6
  { 320, 192 }, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  { 384, 128 }, // sub_vrm1_6_sub_vrm1_7
  { 0, 256 }, // sub_vrm2_0_sub_vrm2_1
  { 0, 384 }, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
  { 0, 512 }, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
  { 128, 256 }, // sub_vrm2_1_sub_vrm2_2
  { 128, 384 }, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
  { 256, 256 }, // sub_vrm2_2_sub_vrm2_3
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char RISCVRegStrings[] = {
  /* 0 */ "V3_V4_V5_V6_V7_V8_V9_V10\0"
  /* 25 */ "X10\0"
  /* 29 */ "V13_V14_V15_V16_V17_V18_V19_V20\0"
  /* 61 */ "X20\0"
  /* 65 */ "V23_V24_V25_V26_V27_V28_V29_V30\0"
  /* 97 */ "X30\0"
  /* 101 */ "V0\0"
  /* 104 */ "DUMMY_REG_PAIR_WITH_X0\0"
  /* 127 */ "V4_V5_V6_V7_V8_V9_V10_V11\0"
  /* 153 */ "X10_X11\0"
  /* 161 */ "V14_V15_V16_V17_V18_V19_V20_V21\0"
  /* 193 */ "X20_X21\0"
  /* 201 */ "V24_V25_V26_V27_V28_V29_V30_V31\0"
  /* 233 */ "X30_X31\0"
  /* 241 */ "V0_V1\0"
  /* 247 */ "X1\0"
  /* 250 */ "V5_V6_V7_V8_V9_V10_V11_V12\0"
  /* 277 */ "X12\0"
  /* 281 */ "V15_V16_V17_V18_V19_V20_V21_V22\0"
  /* 313 */ "X22\0"
  /* 317 */ "V4M2_V6M2_V8M2_V10M2\0"
  /* 338 */ "V14M2_V16M2_V18M2_V20M2\0"
  /* 362 */ "V24M2_V26M2_V28M2_V30M2\0"
  /* 386 */ "V0M2\0"
  /* 391 */ "V6M2_V8M2_V10M2_V12M2\0"
  /* 413 */ "V16M2_V18M2_V20M2_V22M2\0"
  /* 437 */ "V0M2_V2M2\0"
  /* 447 */ "V8M2_V10M2_V12M2_V14M2\0"
  /* 470 */ "V18M2_V20M2_V22M2_V24M2\0"
  /* 494 */ "V0M2_V2M2_V4M2\0"
  /* 509 */ "V10M2_V12M2_V14M2_V16M2\0"
  /* 533 */ "V20M2_V22M2_V24M2_V26M2\0"
  /* 557 */ "V0M2_V2M2_V4M2_V6M2\0"
  /* 577 */ "V12M2_V14M2_V16M2_V18M2\0"
  /* 601 */ "V22M2_V24M2_V26M2_V28M2\0"
  /* 625 */ "V2M2_V4M2_V6M2_V8M2\0"
  /* 645 */ "V0_V1_V2\0"
  /* 654 */ "X2\0"
  /* 657 */ "V6_V7_V8_V9_V10_V11_V12_V13\0"
  /* 685 */ "X12_X13\0"
  /* 693 */ "V16_V17_V18_V19_V20_V21_V22_V23\0"
  /* 725 */ "X22_X23\0"
  /* 733 */ "V0_V1_V2_V3\0"
  /* 745 */ "X2_X3\0"
  /* 751 */ "V7_V8_V9_V10_V11_V12_V13_V14\0"
  /* 780 */ "X14\0"
  /* 784 */ "V17_V18_V19_V20_V21_V22_V23_V24\0"
  /* 816 */ "X24\0"
  /* 820 */ "V16M4_V20M4\0"
  /* 832 */ "V0M4\0"
  /* 837 */ "V8M4_V12M4\0"
  /* 848 */ "V20M4_V24M4\0"
  /* 860 */ "V0M4_V4M4\0"
  /* 870 */ "V12M4_V16M4\0"
  /* 882 */ "V24M4_V28M4\0"
  /* 894 */ "V4M4_V8M4\0"
  /* 904 */ "V0_V1_V2_V3_V4\0"
  /* 919 */ "X4\0"
  /* 922 */ "V8_V9_V10_V11_V12_V13_V14_V15\0"
  /* 952 */ "X14_X15\0"
  /* 960 */ "V18_V19_V20_V21_V22_V23_V24_V25\0"
  /* 992 */ "X24_X25\0"
  /* 1000 */ "V0_V1_V2_V3_V4_V5\0"
  /* 1018 */ "X4_X5\0"
  /* 1024 */ "V9_V10_V11_V12_V13_V14_V15_V16\0"
  /* 1055 */ "X16\0"
  /* 1059 */ "V19_V20_V21_V22_V23_V24_V25_V26\0"
  /* 1091 */ "X26\0"
  /* 1095 */ "V0_V1_V2_V3_V4_V5_V6\0"
  /* 1116 */ "X6\0"
  /* 1119 */ "V10_V11_V12_V13_V14_V15_V16_V17\0"
  /* 1151 */ "X16_X17\0"
  /* 1159 */ "V20_V21_V22_V23_V24_V25_V26_V27\0"
  /* 1191 */ "X26_X27\0"
  /* 1199 */ "V0_V1_V2_V3_V4_V5_V6_V7\0"
  /* 1223 */ "X6_X7\0"
  /* 1229 */ "V11_V12_V13_V14_V15_V16_V17_V18\0"
  /* 1261 */ "X18\0"
  /* 1265 */ "V21_V22_V23_V24_V25_V26_V27_V28\0"
  /* 1297 */ "X28\0"
  /* 1301 */ "V0M8\0"
  /* 1306 */ "V24M8\0"
  /* 1312 */ "V16M8\0"
  /* 1318 */ "V8M8\0"
  /* 1323 */ "V1_V2_V3_V4_V5_V6_V7_V8\0"
  /* 1347 */ "X8\0"
  /* 1350 */ "V12_V13_V14_V15_V16_V17_V18_V19\0"
  /* 1382 */ "X18_X19\0"
  /* 1390 */ "V22_V23_V24_V25_V26_V27_V28_V29\0"
  /* 1422 */ "X28_X29\0"
  /* 1430 */ "V2_V3_V4_V5_V6_V7_V8_V9\0"
  /* 1454 */ "X8_X9\0"
  /* 1460 */ "VLENB\0"
  /* 1466 */ "F10_D\0"
  /* 1472 */ "F20_D\0"
  /* 1478 */ "F30_D\0"
  /* 1484 */ "F0_D\0"
  /* 1489 */ "F11_D\0"
  /* 1495 */ "F21_D\0"
  /* 1501 */ "F31_D\0"
  /* 1507 */ "F1_D\0"
  /* 1512 */ "F12_D\0"
  /* 1518 */ "F22_D\0"
  /* 1524 */ "F2_D\0"
  /* 1529 */ "F13_D\0"
  /* 1535 */ "F23_D\0"
  /* 1541 */ "F3_D\0"
  /* 1546 */ "F14_D\0"
  /* 1552 */ "F24_D\0"
  /* 1558 */ "F4_D\0"
  /* 1563 */ "F15_D\0"
  /* 1569 */ "F25_D\0"
  /* 1575 */ "F5_D\0"
  /* 1580 */ "F16_D\0"
  /* 1586 */ "F26_D\0"
  /* 1592 */ "F6_D\0"
  /* 1597 */ "F17_D\0"
  /* 1603 */ "F27_D\0"
  /* 1609 */ "F7_D\0"
  /* 1614 */ "F18_D\0"
  /* 1620 */ "F28_D\0"
  /* 1626 */ "F8_D\0"
  /* 1631 */ "F19_D\0"
  /* 1637 */ "F29_D\0"
  /* 1643 */ "F9_D\0"
  /* 1648 */ "VTYPE\0"
  /* 1654 */ "F10_F\0"
  /* 1660 */ "F20_F\0"
  /* 1666 */ "F30_F\0"
  /* 1672 */ "F0_F\0"
  /* 1677 */ "F11_F\0"
  /* 1683 */ "F21_F\0"
  /* 1689 */ "F31_F\0"
  /* 1695 */ "F1_F\0"
  /* 1700 */ "F12_F\0"
  /* 1706 */ "F22_F\0"
  /* 1712 */ "F2_F\0"
  /* 1717 */ "F13_F\0"
  /* 1723 */ "F23_F\0"
  /* 1729 */ "F3_F\0"
  /* 1734 */ "F14_F\0"
  /* 1740 */ "F24_F\0"
  /* 1746 */ "F4_F\0"
  /* 1751 */ "F15_F\0"
  /* 1757 */ "F25_F\0"
  /* 1763 */ "F5_F\0"
  /* 1768 */ "F16_F\0"
  /* 1774 */ "F26_F\0"
  /* 1780 */ "F6_F\0"
  /* 1785 */ "F17_F\0"
  /* 1791 */ "F27_F\0"
  /* 1797 */ "F7_F\0"
  /* 1802 */ "F18_F\0"
  /* 1808 */ "F28_F\0"
  /* 1814 */ "F8_F\0"
  /* 1819 */ "F19_F\0"
  /* 1825 */ "F29_F\0"
  /* 1831 */ "F9_F\0"
  /* 1836 */ "F10_H\0"
  /* 1842 */ "F20_H\0"
  /* 1848 */ "F30_H\0"
  /* 1854 */ "F0_H\0"
  /* 1859 */ "F11_H\0"
  /* 1865 */ "F21_H\0"
  /* 1871 */ "F31_H\0"
  /* 1877 */ "F1_H\0"
  /* 1882 */ "F12_H\0"
  /* 1888 */ "F22_H\0"
  /* 1894 */ "F2_H\0"
  /* 1899 */ "F13_H\0"
  /* 1905 */ "F23_H\0"
  /* 1911 */ "F3_H\0"
  /* 1916 */ "F14_H\0"
  /* 1922 */ "F24_H\0"
  /* 1928 */ "F4_H\0"
  /* 1933 */ "F15_H\0"
  /* 1939 */ "F25_H\0"
  /* 1945 */ "F5_H\0"
  /* 1950 */ "F16_H\0"
  /* 1956 */ "F26_H\0"
  /* 1962 */ "F6_H\0"
  /* 1967 */ "F17_H\0"
  /* 1973 */ "F27_H\0"
  /* 1979 */ "F7_H\0"
  /* 1984 */ "F18_H\0"
  /* 1990 */ "F28_H\0"
  /* 1996 */ "F8_H\0"
  /* 2001 */ "F19_H\0"
  /* 2007 */ "F29_H\0"
  /* 2013 */ "F9_H\0"
  /* 2018 */ "VL\0"
  /* 2021 */ "FRM\0"
  /* 2025 */ "VXRM\0"
  /* 2030 */ "SSP\0"
  /* 2034 */ "FFLAGS\0"
  /* 2041 */ "VXSAT\0"
  /* 2047 */ "X0_Pair\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc RISCVRegDesc[] = { // Descriptors
  { 24, 0, 0, 0, 0, 0 },
  { 2034, 1, 1, 2, 4096, 50 },
  { 2021, 1, 1, 2, 4097, 50 },
  { 2030, 1, 1, 2, 4098, 50 },
  { 2018, 1, 1, 2, 4099, 50 },
  { 1460, 1, 1, 2, 4100, 50 },
  { 1648, 1, 1, 2, 4101, 50 },
  { 2025, 1, 1, 2, 4102, 50 },
  { 2041, 1, 1, 2, 4103, 50 },
  { 104, 1, 6127, 2, 4104, 50 },
  { 101, 1, 31, 2, 4105, 50 },
  { 244, 1, 6136, 2, 4106, 50 },
  { 651, 1, 5780, 2, 4107, 50 },
  { 742, 1, 4852, 2, 4108, 50 },
  { 916, 1, 4809, 2, 4109, 50 },
  { 1015, 1, 3575, 2, 4110, 50 },
  { 1113, 1, 3213, 2, 4111, 50 },
  { 1220, 1, 2044, 2, 4112, 50 },
  { 1344, 1, 2094, 2, 4113, 50 },
  { 1451, 1, 2364, 2, 4114, 50 },
  { 21, 1, 1994, 2, 4115, 50 },
  { 149, 1, 2279, 2, 4116, 50 },
  { 273, 1, 2229, 2, 4117, 50 },
  { 681, 1, 2635, 2, 4118, 50 },
  { 776, 1, 2179, 2, 4119, 50 },
  { 948, 1, 2550, 2, 4120, 50 },
  { 1051, 1, 2500, 2, 4121, 50 },
  { 1147, 1, 2906, 2, 4122, 50 },
  { 1257, 1, 2450, 2, 4123, 50 },
  { 1378, 1, 2821, 2, 4124, 50 },
  { 57, 1, 2771, 2, 4125, 50 },
  { 189, 1, 3127, 2, 4126, 50 },
  { 309, 1, 2721, 2, 4127, 50 },
  { 721, 1, 3042, 2, 4128, 50 },
  { 812, 1, 2992, 2, 4129, 50 },
  { 988, 1, 4273, 2, 4130, 50 },
  { 1087, 1, 4389, 2, 4131, 50 },
  { 1187, 1, 5396, 2, 4132, 50 },
  { 1293, 1, 5439, 2, 4133, 50 },
  { 1418, 1, 5993, 2, 4134, 50 },
  { 93, 1, 6247, 2, 4135, 50 },
  { 229, 1, 16, 2, 4136, 50 },
  { 124, 1, 6093, 2, 4137, 50 },
  { 247, 1, 1, 2, 4138, 50 },
  { 654, 1, 6125, 2, 4139, 50 },
  { 748, 1, 6123, 2, 4140, 50 },
  { 919, 1, 6123, 2, 4141, 50 },
  { 1021, 1, 6121, 2, 4142, 50 },
  { 1116, 1, 6121, 2, 4143, 50 },
  { 1226, 1, 6119, 2, 4144, 50 },
  { 1347, 1, 6119, 2, 4145, 50 },
  { 1457, 1, 6117, 2, 4146, 50 },
  { 25, 1, 6117, 2, 4147, 50 },
  { 157, 1, 6115, 2, 4148, 50 },
  { 277, 1, 6115, 2, 4149, 50 },
  { 689, 1, 6113, 2, 4150, 50 },
  { 780, 1, 6113, 2, 4151, 50 },
  { 956, 1, 6111, 2, 4152, 50 },
  { 1055, 1, 6111, 2, 4153, 50 },
  { 1155, 1, 6109, 2, 4154, 50 },
  { 1261, 1, 6109, 2, 4155, 50 },
  { 1386, 1, 6107, 2, 4156, 50 },
  { 61, 1, 6107, 2, 4157, 50 },
  { 197, 1, 6105, 2, 4158, 50 },
  { 313, 1, 6105, 2, 4159, 50 },
  { 729, 1, 6103, 2, 4160, 50 },
  { 816, 1, 6103, 2, 4161, 50 },
  { 996, 1, 6101, 2, 4162, 50 },
  { 1091, 1, 6101, 2, 4163, 50 },
  { 1195, 1, 6099, 2, 4164, 50 },
  { 1297, 1, 6099, 2, 4165, 50 },
  { 1426, 1, 6097, 2, 4166, 50 },
  { 97, 1, 6097, 2, 4167, 50 },
  { 237, 1, 6095, 2, 4168, 50 },
  { 1484, 5626, 1, 0, 4169, 0 },
  { 1507, 5626, 1, 0, 4170, 0 },
  { 1524, 5626, 1, 0, 4171, 0 },
  { 1541, 5626, 1, 0, 4172, 0 },
  { 1558, 5626, 1, 0, 4173, 0 },
  { 1575, 5626, 1, 0, 4174, 0 },
  { 1592, 5626, 1, 0, 4175, 0 },
  { 1609, 5626, 1, 0, 4176, 0 },
  { 1626, 5626, 1, 0, 4177, 0 },
  { 1643, 5626, 1, 0, 4178, 0 },
  { 1466, 5626, 1, 0, 4179, 0 },
  { 1489, 5626, 1, 0, 4180, 0 },
  { 1512, 5626, 1, 0, 4181, 0 },
  { 1529, 5626, 1, 0, 4182, 0 },
  { 1546, 5626, 1, 0, 4183, 0 },
  { 1563, 5626, 1, 0, 4184, 0 },
  { 1580, 5626, 1, 0, 4185, 0 },
  { 1597, 5626, 1, 0, 4186, 0 },
  { 1614, 5626, 1, 0, 4187, 0 },
  { 1631, 5626, 1, 0, 4188, 0 },
  { 1472, 5626, 1, 0, 4189, 0 },
  { 1495, 5626, 1, 0, 4190, 0 },
  { 1518, 5626, 1, 0, 4191, 0 },
  { 1535, 5626, 1, 0, 4192, 0 },
  { 1552, 5626, 1, 0, 4193, 0 },
  { 1569, 5626, 1, 0, 4194, 0 },
  { 1586, 5626, 1, 0, 4195, 0 },
  { 1603, 5626, 1, 0, 4196, 0 },
  { 1620, 5626, 1, 0, 4197, 0 },
  { 1637, 5626, 1, 0, 4198, 0 },
  { 1478, 5626, 1, 0, 4199, 0 },
  { 1501, 5626, 1, 0, 4200, 0 },
  { 1672, 5627, 1435, 1, 4169, 0 },
  { 1695, 5627, 1435, 1, 4170, 0 },
  { 1712, 5627, 1435, 1, 4171, 0 },
  { 1729, 5627, 1435, 1, 4172, 0 },
  { 1746, 5627, 1435, 1, 4173, 0 },
  { 1763, 5627, 1435, 1, 4174, 0 },
  { 1780, 5627, 1435, 1, 4175, 0 },
  { 1797, 5627, 1435, 1, 4176, 0 },
  { 1814, 5627, 1435, 1, 4177, 0 },
  { 1831, 5627, 1435, 1, 4178, 0 },
  { 1654, 5627, 1435, 1, 4179, 0 },
  { 1677, 5627, 1435, 1, 4180, 0 },
  { 1700, 5627, 1435, 1, 4181, 0 },
  { 1717, 5627, 1435, 1, 4182, 0 },
  { 1734, 5627, 1435, 1, 4183, 0 },
  { 1751, 5627, 1435, 1, 4184, 0 },
  { 1768, 5627, 1435, 1, 4185, 0 },
  { 1785, 5627, 1435, 1, 4186, 0 },
  { 1802, 5627, 1435, 1, 4187, 0 },
  { 1819, 5627, 1435, 1, 4188, 0 },
  { 1660, 5627, 1435, 1, 4189, 0 },
  { 1683, 5627, 1435, 1, 4190, 0 },
  { 1706, 5627, 1435, 1, 4191, 0 },
  { 1723, 5627, 1435, 1, 4192, 0 },
  { 1740, 5627, 1435, 1, 4193, 0 },
  { 1757, 5627, 1435, 1, 4194, 0 },
  { 1774, 5627, 1435, 1, 4195, 0 },
  { 1791, 5627, 1435, 1, 4196, 0 },
  { 1808, 5627, 1435, 1, 4197, 0 },
  { 1825, 5627, 1435, 1, 4198, 0 },
  { 1666, 5627, 1435, 1, 4199, 0 },
  { 1689, 5627, 1435, 1, 4200, 0 },
  { 1854, 1, 1434, 2, 4169, 50 },
  { 1877, 1, 1434, 2, 4170, 50 },
  { 1894, 1, 1434, 2, 4171, 50 },
  { 1911, 1, 1434, 2, 4172, 50 },
  { 1928, 1, 1434, 2, 4173, 50 },
  { 1945, 1, 1434, 2, 4174, 50 },
  { 1962, 1, 1434, 2, 4175, 50 },
  { 1979, 1, 1434, 2, 4176, 50 },
  { 1996, 1, 1434, 2, 4177, 50 },
  { 2013, 1, 1434, 2, 4178, 50 },
  { 1836, 1, 1434, 2, 4179, 50 },
  { 1859, 1, 1434, 2, 4180, 50 },
  { 1882, 1, 1434, 2, 4181, 50 },
  { 1899, 1, 1434, 2, 4182, 50 },
  { 1916, 1, 1434, 2, 4183, 50 },
  { 1933, 1, 1434, 2, 4184, 50 },
  { 1950, 1, 1434, 2, 4185, 50 },
  { 1967, 1, 1434, 2, 4186, 50 },
  { 1984, 1, 1434, 2, 4187, 50 },
  { 2001, 1, 1434, 2, 4188, 50 },
  { 1842, 1, 1434, 2, 4189, 50 },
  { 1865, 1, 1434, 2, 4190, 50 },
  { 1888, 1, 1434, 2, 4191, 50 },
  { 1905, 1, 1434, 2, 4192, 50 },
  { 1922, 1, 1434, 2, 4193, 50 },
  { 1939, 1, 1434, 2, 4194, 50 },
  { 1956, 1, 1434, 2, 4195, 50 },
  { 1973, 1, 1434, 2, 4196, 50 },
  { 1990, 1, 1434, 2, 4197, 50 },
  { 2007, 1, 1434, 2, 4198, 50 },
  { 1848, 1, 1434, 2, 4199, 50 },
  { 1871, 1, 1434, 2, 4200, 50 },
  { 2047, 1431, 1, 3, 23056392, 2 },
  { 386, 1495, 53, 6, 6025225, 8 },
  { 832, 1476, 5764, 9, 6606857, 15 },
  { 1301, 1483, 1, 16, 6590473, 41 },
  { 442, 1480, 5647, 6, 6025227, 8 },
  { 504, 1495, 5634, 6, 6025229, 8 },
  { 865, 1491, 5622, 9, 6606861, 15 },
  { 572, 1495, 4547, 6, 6025231, 8 },
  { 640, 1517, 4561, 6, 6025233, 8 },
  { 899, 1498, 1980, 9, 6606865, 15 },
  { 1318, 1505, 1, 16, 6590481, 41 },
  { 332, 1495, 4610, 6, 6025235, 8 },
  { 407, 1517, 4575, 6, 6025237, 8 },
  { 842, 1513, 1984, 9, 6606869, 15 },
  { 464, 1517, 4645, 6, 6025239, 8 },
  { 527, 1539, 4596, 6, 6025241, 8 },
  { 876, 1520, 1972, 9, 6606873, 15 },
  { 1312, 1527, 1, 16, 6590489, 41 },
  { 595, 1517, 4680, 6, 6025243, 8 },
  { 356, 1539, 4631, 6, 6025245, 8 },
  { 826, 1535, 1976, 9, 6606877, 15 },
  { 431, 1539, 4701, 6, 6025247, 8 },
  { 488, 1561, 4666, 6, 6025249, 8 },
  { 854, 1542, 1968, 9, 6606881, 15 },
  { 1306, 1549, 1, 16, 6590497, 41 },
  { 551, 1539, 5719, 6, 6025251, 8 },
  { 619, 1561, 5732, 6, 6025253, 8 },
  { 888, 1557, 5631, 9, 6606885, 15 },
  { 380, 1561, 46, 6, 6025255, 8 },
  { 745, 1564, 1, 3, 6025259, 5 },
  { 1018, 1567, 1, 3, 6025261, 5 },
  { 1223, 1570, 1, 3, 6025263, 5 },
  { 1454, 1573, 1, 3, 6025265, 5 },
  { 153, 1576, 1, 3, 6025267, 5 },
  { 685, 1579, 1, 3, 6025269, 5 },
  { 952, 1582, 1, 3, 6025271, 5 },
  { 1151, 1585, 1, 3, 6025273, 5 },
  { 1382, 1588, 1, 3, 6025275, 5 },
  { 193, 1591, 1, 3, 6025277, 5 },
  { 725, 1594, 1, 3, 6025279, 5 },
  { 992, 1597, 1, 3, 6025281, 5 },
  { 1191, 1600, 1, 3, 6025283, 5 },
  { 1422, 1603, 1, 3, 6025285, 5 },
  { 233, 1606, 1, 3, 6025287, 5 },
  { 648, 1473, 6158, 6, 6025226, 8 },
  { 739, 1473, 5811, 6, 6025227, 8 },
  { 913, 1473, 4888, 6, 6025228, 8 },
  { 1012, 1473, 4916, 6, 6025229, 8 },
  { 1110, 1473, 3511, 6, 6025230, 8 },
  { 1217, 1473, 3262, 6, 6025231, 8 },
  { 1341, 1473, 2144, 6, 6025232, 8 },
  { 1448, 1473, 3396, 6, 6025233, 8 },
  { 18, 1473, 2414, 6, 6025234, 8 },
  { 145, 1473, 3329, 6, 6025235, 8 },
  { 269, 1473, 2329, 6, 6025236, 8 },
  { 677, 1473, 3707, 6, 6025237, 8 },
  { 772, 1473, 2685, 6, 6025238, 8 },
  { 944, 1473, 3640, 6, 6025239, 8 },
  { 1047, 1473, 2600, 6, 6025240, 8 },
  { 1143, 1473, 3918, 6, 6025241, 8 },
  { 1253, 1473, 2956, 6, 6025242, 8 },
  { 1374, 1473, 3851, 6, 6025243, 8 },
  { 53, 1473, 2871, 6, 6025244, 8 },
  { 185, 1473, 4129, 6, 6025245, 8 },
  { 305, 1473, 3177, 6, 6025246, 8 },
  { 717, 1473, 4062, 6, 6025247, 8 },
  { 808, 1473, 3092, 6, 6025248, 8 },
  { 984, 1473, 4322, 6, 6025249, 8 },
  { 1083, 1473, 4435, 6, 6025250, 8 },
  { 1183, 1473, 5337, 6, 6025251, 8 },
  { 1289, 1473, 5475, 6, 6025252, 8 },
  { 1414, 1473, 6024, 6, 6025253, 8 },
  { 89, 1473, 6269, 6, 6025254, 8 },
  { 225, 1473, 20, 6, 6025255, 8 },
  { 241, 1470, 20, 6, 6025225, 8 },
  { 499, 288, 5657, 47, 6606859, 15 },
  { 567, 301, 5663, 47, 6606861, 15 },
  { 635, 327, 4589, 47, 6606863, 15 },
  { 327, 314, 5675, 47, 6606865, 15 },
  { 401, 340, 4624, 47, 6606867, 15 },
  { 458, 353, 5683, 47, 6606869, 15 },
  { 521, 379, 4659, 47, 6606871, 15 },
  { 589, 366, 5695, 47, 6606873, 15 },
  { 350, 392, 4694, 47, 6606875, 15 },
  { 425, 405, 5707, 47, 6606877, 15 },
  { 482, 431, 4715, 47, 6606879, 15 },
  { 545, 418, 5748, 47, 6606881, 15 },
  { 613, 444, 5742, 47, 6606883, 15 },
  { 374, 457, 49, 47, 6606885, 15 },
  { 437, 105, 49, 47, 6606857, 15 },
  { 894, 784, 1, 233, 6590477, 41 },
  { 837, 735, 1, 233, 6590481, 41 },
  { 870, 686, 1, 233, 6590485, 41 },
  { 820, 637, 1, 233, 6590489, 41 },
  { 848, 588, 1, 233, 6590493, 41 },
  { 882, 539, 1, 233, 6590497, 41 },
  { 860, 490, 1, 233, 6590473, 41 },
  { 736, 1988, 6143, 31, 6610954, 11 },
  { 910, 1988, 5836, 31, 6610955, 11 },
  { 1009, 1988, 4951, 31, 6610956, 11 },
  { 1107, 1988, 4758, 31, 6610957, 11 },
  { 1214, 1988, 3546, 31, 6610958, 11 },
  { 1338, 1988, 3301, 31, 6610959, 11 },
  { 1445, 1988, 3435, 31, 6610960, 11 },
  { 15, 1988, 3463, 31, 6610961, 11 },
  { 142, 1988, 3822, 31, 6610962, 11 },
  { 265, 1988, 3368, 31, 6610963, 11 },
  { 673, 1988, 3746, 31, 6610964, 11 },
  { 768, 1988, 3774, 31, 6610965, 11 },
  { 940, 1988, 4033, 31, 6610966, 11 },
  { 1043, 1988, 3679, 31, 6610967, 11 },
  { 1139, 1988, 3957, 31, 6610968, 11 },
  { 1249, 1988, 3985, 31, 6610969, 11 },
  { 1370, 1988, 4244, 31, 6610970, 11 },
  { 49, 1988, 3890, 31, 6610971, 11 },
  { 181, 1988, 4168, 31, 6610972, 11 },
  { 301, 1988, 4196, 31, 6610973, 11 },
  { 713, 1988, 4518, 31, 6610974, 11 },
  { 804, 1988, 4101, 31, 6610975, 11 },
  { 980, 1988, 4361, 31, 6610976, 11 },
  { 1079, 1988, 4470, 31, 6610977, 11 },
  { 1179, 1988, 5503, 31, 6610978, 11 },
  { 1285, 1988, 5372, 31, 6610979, 11 },
  { 1410, 1988, 6049, 31, 6610980, 11 },
  { 85, 1988, 6286, 31, 6610981, 11 },
  { 221, 1988, 21, 31, 6610982, 11 },
  { 645, 1437, 21, 31, 6610953, 11 },
  { 562, 1941, 5643, 160, 6598667, 26 },
  { 630, 1914, 5671, 160, 6598669, 26 },
  { 322, 1887, 5691, 160, 6598671, 26 },
  { 396, 1860, 5679, 160, 6598673, 26 },
  { 452, 1833, 5703, 160, 6598675, 26 },
  { 515, 1806, 5687, 160, 6598677, 26 },
  { 583, 1779, 5715, 160, 6598679, 26 },
  { 344, 1752, 5699, 160, 6598681, 26 },
  { 419, 1725, 5756, 160, 6598683, 26 },
  { 476, 1698, 5711, 160, 6598685, 26 },
  { 539, 1671, 5760, 160, 6598687, 26 },
  { 607, 1644, 5752, 160, 6598689, 26 },
  { 368, 1617, 28, 160, 6598691, 26 },
  { 494, 1443, 28, 160, 6598665, 26 },
  { 907, 480, 6146, 37, 6606858, 15 },
  { 1006, 480, 5857, 37, 6606859, 15 },
  { 1104, 480, 4768, 37, 6606860, 15 },
  { 1211, 480, 4786, 37, 6606861, 15 },
  { 1335, 480, 3621, 37, 6606862, 15 },
  { 1442, 480, 4722, 37, 6606863, 15 },
  { 12, 480, 3492, 37, 6606864, 15 },
  { 139, 480, 5025, 37, 6606865, 15 },
  { 262, 480, 3832, 37, 6606866, 15 },
  { 669, 480, 4989, 37, 6606867, 15 },
  { 764, 480, 3803, 37, 6606868, 15 },
  { 936, 480, 5112, 37, 6606869, 15 },
  { 1039, 480, 4043, 37, 6606870, 15 },
  { 1135, 480, 5076, 37, 6606871, 15 },
  { 1245, 480, 4014, 37, 6606872, 15 },
  { 1366, 480, 5199, 37, 6606873, 15 },
  { 45, 480, 4254, 37, 6606874, 15 },
  { 177, 480, 5163, 37, 6606875, 15 },
  { 297, 480, 4225, 37, 6606876, 15 },
  { 709, 480, 5286, 37, 6606877, 15 },
  { 800, 480, 4528, 37, 6606878, 15 },
  { 976, 480, 5250, 37, 6606879, 15 },
  { 1075, 480, 4499, 37, 6606880, 15 },
  { 1175, 480, 5531, 37, 6606881, 15 },
  { 1281, 480, 5513, 37, 6606882, 15 },
  { 1406, 480, 5975, 37, 6606883, 15 },
  { 81, 480, 6257, 37, 6606884, 15 },
  { 217, 480, 22, 37, 6606885, 15 },
  { 733, 470, 22, 37, 6606857, 15 },
  { 625, 1385, 1, 187, 6590475, 41 },
  { 317, 1339, 73, 187, 6590477, 41 },
  { 391, 1293, 1, 187, 6590479, 41 },
  { 447, 1247, 70, 187, 6590481, 41 },
  { 509, 1201, 1, 187, 6590483, 41 },
  { 577, 1155, 67, 187, 6590485, 41 },
  { 338, 1109, 1, 187, 6590487, 41 },
  { 413, 1063, 64, 187, 6590489, 41 },
  { 470, 1017, 1, 187, 6590491, 41 },
  { 533, 971, 61, 187, 6590493, 41 },
  { 601, 925, 1, 187, 6590495, 41 },
  { 362, 879, 14, 187, 6590497, 41 },
  { 557, 833, 14, 187, 6590473, 41 },
  { 1003, 90, 6148, 60, 6602762, 20 },
  { 1101, 90, 5767, 60, 6602763, 20 },
  { 1208, 90, 4772, 60, 6602764, 20 },
  { 1332, 90, 4975, 60, 6602765, 20 },
  { 1439, 90, 5062, 60, 6602766, 20 },
  { 9, 90, 4744, 60, 6602767, 20 },
  { 136, 90, 5048, 60, 6602768, 20 },
  { 259, 90, 5034, 60, 6602769, 20 },
  { 666, 90, 5149, 60, 6602770, 20 },
  { 760, 90, 5011, 60, 6602771, 20 },
  { 932, 90, 5135, 60, 6602772, 20 },
  { 1035, 90, 5121, 60, 6602773, 20 },
  { 1131, 90, 5236, 60, 6602774, 20 },
  { 1241, 90, 5098, 60, 6602775, 20 },
  { 1362, 90, 5222, 60, 6602776, 20 },
  { 41, 90, 5208, 60, 6602777, 20 },
  { 173, 90, 5323, 60, 6602778, 20 },
  { 293, 90, 5185, 60, 6602779, 20 },
  { 705, 90, 5309, 60, 6602780, 20 },
  { 796, 90, 5295, 60, 6602781, 20 },
  { 972, 90, 5568, 60, 6602782, 20 },
  { 1071, 90, 5272, 60, 6602783, 20 },
  { 1171, 90, 5554, 60, 6602784, 20 },
  { 1277, 90, 5540, 60, 6602785, 20 },
  { 1402, 90, 6070, 60, 6602786, 20 },
  { 77, 90, 6237, 60, 6602787, 20 },
  { 213, 90, 24, 60, 6602788, 20 },
  { 904, 75, 24, 60, 6602761, 20 },
  { 1098, 139, 6129, 75, 6598666, 26 },
  { 1205, 139, 5770, 75, 6598667, 26 },
  { 1329, 139, 4779, 75, 6598668, 26 },
  { 1436, 139, 5885, 75, 6598669, 26 },
  { 6, 139, 5582, 75, 6598670, 26 },
  { 133, 139, 5875, 75, 6598671, 26 },
  { 256, 139, 5041, 75, 6598672, 26 },
  { 663, 139, 5905, 75, 6598673, 26 },
  { 757, 139, 5590, 75, 6598674, 26 },
  { 928, 139, 5895, 75, 6598675, 26 },
  { 1031, 139, 5128, 75, 6598676, 26 },
  { 1127, 139, 5925, 75, 6598677, 26 },
  { 1237, 139, 5598, 75, 6598678, 26 },
  { 1358, 139, 5915, 75, 6598679, 26 },
  { 37, 139, 5215, 75, 6598680, 26 },
  { 169, 139, 5945, 75, 6598681, 26 },
  { 289, 139, 5606, 75, 6598682, 26 },
  { 701, 139, 5935, 75, 6598683, 26 },
  { 792, 139, 5302, 75, 6598684, 26 },
  { 968, 139, 5965, 75, 6598685, 26 },
  { 1067, 139, 5614, 75, 6598686, 26 },
  { 1167, 139, 5955, 75, 6598687, 26 },
  { 1273, 139, 5365, 75, 6598688, 26 },
  { 1398, 139, 6083, 75, 6598689, 26 },
  { 73, 139, 6225, 75, 6598690, 26 },
  { 209, 139, 25, 75, 6598691, 26 },
  { 1000, 118, 25, 75, 6598665, 26 },
  { 1202, 188, 6131, 96, 6594570, 33 },
  { 1326, 188, 5776, 96, 6594571, 33 },
  { 1433, 188, 5891, 96, 6594572, 33 },
  { 3, 188, 6175, 96, 6594573, 33 },
  { 130, 188, 6180, 96, 6594574, 33 },
  { 253, 188, 5881, 96, 6594575, 33 },
  { 660, 188, 5911, 96, 6594576, 33 },
  { 754, 188, 6185, 96, 6594577, 33 },
  { 925, 188, 6190, 96, 6594578, 33 },
  { 1027, 188, 5901, 96, 6594579, 33 },
  { 1123, 188, 5931, 96, 6594580, 33 },
  { 1233, 188, 6195, 96, 6594581, 33 },
  { 1354, 188, 6200, 96, 6594582, 33 },
  { 33, 188, 5921, 96, 6594583, 33 },
  { 165, 188, 5951, 96, 6594584, 33 },
  { 285, 188, 6205, 96, 6594585, 33 },
  { 697, 188, 6210, 96, 6594586, 33 },
  { 788, 188, 5941, 96, 6594587, 33 },
  { 964, 188, 5971, 96, 6594588, 33 },
  { 1063, 188, 6215, 96, 6594589, 33 },
  { 1163, 188, 6220, 96, 6594590, 33 },
  { 1269, 188, 5961, 96, 6594591, 33 },
  { 1394, 188, 5989, 96, 6594592, 33 },
  { 69, 188, 6232, 96, 6594593, 33 },
  { 205, 188, 12, 96, 6594594, 33 },
  { 1095, 160, 12, 96, 6594569, 33 },
  { 1323, 252, 1, 124, 6590474, 41 },
  { 1430, 252, 10, 124, 6590475, 41 },
  { 0, 252, 1, 124, 6590476, 41 },
  { 127, 252, 72, 124, 6590477, 41 },
  { 250, 252, 1, 124, 6590478, 41 },
  { 657, 252, 8, 124, 6590479, 41 },
  { 751, 252, 1, 124, 6590480, 41 },
  { 922, 252, 69, 124, 6590481, 41 },
  { 1024, 252, 1, 124, 6590482, 41 },
  { 1119, 252, 6, 124, 6590483, 41 },
  { 1229, 252, 1, 124, 6590484, 41 },
  { 1350, 252, 66, 124, 6590485, 41 },
  { 29, 252, 1, 124, 6590486, 41 },
  { 161, 252, 4, 124, 6590487, 41 },
  { 281, 252, 1, 124, 6590488, 41 },
  { 693, 252, 63, 124, 6590489, 41 },
  { 784, 252, 1, 124, 6590490, 41 },
  { 960, 252, 2, 124, 6590491, 41 },
  { 1059, 252, 1, 124, 6590492, 41 },
  { 1159, 252, 60, 124, 6590493, 41 },
  { 1265, 252, 1, 124, 6590494, 41 },
  { 1390, 252, 0, 124, 6590495, 41 },
  { 65, 252, 1, 124, 6590496, 41 },
  { 201, 252, 13, 124, 6590497, 41 },
  { 1199, 216, 13, 124, 6590473, 41 },
};

extern const MCPhysReg RISCVRegUnitRoots[][2] = {
  { RISCV::FFLAGS },
  { RISCV::FRM },
  { RISCV::SSP },
  { RISCV::VL },
  { RISCV::VLENB },
  { RISCV::VTYPE },
  { RISCV::VXRM },
  { RISCV::VXSAT },
  { RISCV::DUMMY_REG_PAIR_WITH_X0 },
  { RISCV::V0 },
  { RISCV::V1 },
  { RISCV::V2 },
  { RISCV::V3 },
  { RISCV::V4 },
  { RISCV::V5 },
  { RISCV::V6 },
  { RISCV::V7 },
  { RISCV::V8 },
  { RISCV::V9 },
  { RISCV::V10 },
  { RISCV::V11 },
  { RISCV::V12 },
  { RISCV::V13 },
  { RISCV::V14 },
  { RISCV::V15 },
  { RISCV::V16 },
  { RISCV::V17 },
  { RISCV::V18 },
  { RISCV::V19 },
  { RISCV::V20 },
  { RISCV::V21 },
  { RISCV::V22 },
  { RISCV::V23 },
  { RISCV::V24 },
  { RISCV::V25 },
  { RISCV::V26 },
  { RISCV::V27 },
  { RISCV::V28 },
  { RISCV::V29 },
  { RISCV::V30 },
  { RISCV::V31 },
  { RISCV::X0 },
  { RISCV::X1 },
  { RISCV::X2 },
  { RISCV::X3 },
  { RISCV::X4 },
  { RISCV::X5 },
  { RISCV::X6 },
  { RISCV::X7 },
  { RISCV::X8 },
  { RISCV::X9 },
  { RISCV::X10 },
  { RISCV::X11 },
  { RISCV::X12 },
  { RISCV::X13 },
  { RISCV::X14 },
  { RISCV::X15 },
  { RISCV::X16 },
  { RISCV::X17 },
  { RISCV::X18 },
  { RISCV::X19 },
  { RISCV::X20 },
  { RISCV::X21 },
  { RISCV::X22 },
  { RISCV::X23 },
  { RISCV::X24 },
  { RISCV::X25 },
  { RISCV::X26 },
  { RISCV::X27 },
  { RISCV::X28 },
  { RISCV::X29 },
  { RISCV::X30 },
  { RISCV::X31 },
  { RISCV::F0_H },
  { RISCV::F1_H },
  { RISCV::F2_H },
  { RISCV::F3_H },
  { RISCV::F4_H },
  { RISCV::F5_H },
  { RISCV::F6_H },
  { RISCV::F7_H },
  { RISCV::F8_H },
  { RISCV::F9_H },
  { RISCV::F10_H },
  { RISCV::F11_H },
  { RISCV::F12_H },
  { RISCV::F13_H },
  { RISCV::F14_H },
  { RISCV::F15_H },
  { RISCV::F16_H },
  { RISCV::F17_H },
  { RISCV::F18_H },
  { RISCV::F19_H },
  { RISCV::F20_H },
  { RISCV::F21_H },
  { RISCV::F22_H },
  { RISCV::F23_H },
  { RISCV::F24_H },
  { RISCV::F25_H },
  { RISCV::F26_H },
  { RISCV::F27_H },
  { RISCV::F28_H },
  { RISCV::F29_H },
  { RISCV::F30_H },
  { RISCV::F31_H },
};

namespace {     // Register classes...
  // FPR16 Register Class...
  const MCPhysReg FPR16[] = {
    RISCV::F15_H, RISCV::F14_H, RISCV::F13_H, RISCV::F12_H, RISCV::F11_H, RISCV::F10_H, RISCV::F0_H, RISCV::F1_H, RISCV::F2_H, RISCV::F3_H, RISCV::F4_H, RISCV::F5_H, RISCV::F6_H, RISCV::F7_H, RISCV::F16_H, RISCV::F17_H, RISCV::F28_H, RISCV::F29_H, RISCV::F30_H, RISCV::F31_H, RISCV::F8_H, RISCV::F9_H, RISCV::F18_H, RISCV::F19_H, RISCV::F20_H, RISCV::F21_H, RISCV::F22_H, RISCV::F23_H, RISCV::F24_H, RISCV::F25_H, RISCV::F26_H, RISCV::F27_H, 
  };

  // FPR16 Bit set.
  const uint8_t FPR16Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRAll Register Class...
  const MCPhysReg GPRAll[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, RISCV::DUMMY_REG_PAIR_WITH_X0, 
  };

  // GPRAll Bit set.
  const uint8_t GPRAllBits[] = {
    0x00, 0x02, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // FPR32 Register Class...
  const MCPhysReg FPR32[] = {
    RISCV::F15_F, RISCV::F14_F, RISCV::F13_F, RISCV::F12_F, RISCV::F11_F, RISCV::F10_F, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F16_F, RISCV::F17_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 
  };

  // FPR32 Bit set.
  const uint8_t FPR32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPR Register Class...
  const MCPhysReg GPR[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, 
  };

  // GPR Bit set.
  const uint8_t GPRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRF16 Register Class...
  const MCPhysReg GPRF16[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, 
  };

  // GPRF16 Bit set.
  const uint8_t GPRF16Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRF32 Register Class...
  const MCPhysReg GPRF32[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X0, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, 
  };

  // GPRF32 Bit set.
  const uint8_t GPRF32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRNoX0 Register Class...
  const MCPhysReg GPRNoX0[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X2, RISCV::X3, RISCV::X4, 
  };

  // GPRNoX0 Bit set.
  const uint8_t GPRNoX0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRNoX0X2 Register Class...
  const MCPhysReg GPRNoX0X2[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X1, RISCV::X3, RISCV::X4, 
  };

  // GPRNoX0X2 Bit set.
  const uint8_t GPRNoX0X2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRJALR Register Class...
  const MCPhysReg GPRJALR[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X6, RISCV::X7, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, 
  };

  // GPRJALR Bit set.
  const uint8_t GPRJALRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRTC Register Class...
  const MCPhysReg GPRTC[] = {
    RISCV::X6, RISCV::X7, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 
  };

  // GPRTC Bit set.
  const uint8_t GPRTCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf3, 0x0f, 0xc0, 0x03, 
  };

  // FPR32C Register Class...
  const MCPhysReg FPR32C[] = {
    RISCV::F15_F, RISCV::F14_F, RISCV::F13_F, RISCV::F12_F, RISCV::F11_F, RISCV::F10_F, RISCV::F8_F, RISCV::F9_F, 
  };

  // FPR32C Bit set.
  const uint8_t FPR32CBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // GPRC Register Class...
  const MCPhysReg GPRC[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X8, RISCV::X9, 
  };

  // GPRC Bit set.
  const uint8_t GPRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // SR07 Register Class...
  const MCPhysReg SR07[] = {
    RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, 
  };

  // SR07 Bit set.
  const uint8_t SR07Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0xf0, 0x03, 
  };

  // GPRC_and_GPRTC Register Class...
  const MCPhysReg GPRC_and_GPRTC[] = {
    RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, 
  };

  // GPRC_and_GPRTC Bit set.
  const uint8_t GPRC_and_GPRTCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
  };

  // VCSR Register Class...
  const MCPhysReg VCSR[] = {
    RISCV::VTYPE, RISCV::VL, RISCV::VLENB, 
  };

  // VCSR Bit set.
  const uint8_t VCSRBits[] = {
    0x70, 
  };

  // GPRC_and_SR07 Register Class...
  const MCPhysReg GPRC_and_SR07[] = {
    RISCV::X8, RISCV::X9, 
  };

  // GPRC_and_SR07 Bit set.
  const uint8_t GPRC_and_SR07Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 
  };

  // GPRX1X5 Register Class...
  const MCPhysReg GPRX1X5[] = {
    RISCV::X1, RISCV::X5, 
  };

  // GPRX1X5 Bit set.
  const uint8_t GPRX1X5Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x88, 
  };

  // GPRX0 Register Class...
  const MCPhysReg GPRX0[] = {
    RISCV::X0, 
  };

  // GPRX0 Bit set.
  const uint8_t GPRX0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // GPRX1 Register Class...
  const MCPhysReg GPRX1[] = {
    RISCV::X1, 
  };

  // GPRX1 Bit set.
  const uint8_t GPRX1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // GPRX5 Register Class...
  const MCPhysReg GPRX5[] = {
    RISCV::X5, 
  };

  // GPRX5 Bit set.
  const uint8_t GPRX5Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
  };

  // SP Register Class...
  const MCPhysReg SP[] = {
    RISCV::X2, 
  };

  // SP Bit set.
  const uint8_t SPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // FPR64 Register Class...
  const MCPhysReg FPR64[] = {
    RISCV::F15_D, RISCV::F14_D, RISCV::F13_D, RISCV::F12_D, RISCV::F11_D, RISCV::F10_D, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F16_D, RISCV::F17_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 
  };

  // FPR64 Bit set.
  const uint8_t FPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // VM Register Class...
  const MCPhysReg VM[] = {
    RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V0, RISCV::V1, RISCV::V2, RISCV::V3, RISCV::V4, RISCV::V5, RISCV::V6, RISCV::V7, 
  };

  // VM Bit set.
  const uint8_t VMBits[] = {
    0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // VR Register Class...
  const MCPhysReg VR[] = {
    RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V0, RISCV::V1, RISCV::V2, RISCV::V3, RISCV::V4, RISCV::V5, RISCV::V6, RISCV::V7, 
  };

  // VR Bit set.
  const uint8_t VRBits[] = {
    0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // VRNoV0 Register Class...
  const MCPhysReg VRNoV0[] = {
    RISCV::V8, RISCV::V9, RISCV::V10, RISCV::V11, RISCV::V12, RISCV::V13, RISCV::V14, RISCV::V15, RISCV::V16, RISCV::V17, RISCV::V18, RISCV::V19, RISCV::V20, RISCV::V21, RISCV::V22, RISCV::V23, RISCV::V24, RISCV::V25, RISCV::V26, RISCV::V27, RISCV::V28, RISCV::V29, RISCV::V30, RISCV::V31, RISCV::V1, RISCV::V2, RISCV::V3, RISCV::V4, RISCV::V5, RISCV::V6, RISCV::V7, 
  };

  // VRNoV0 Bit set.
  const uint8_t VRNoV0Bits[] = {
    0x00, 0xf8, 0xff, 0xff, 0xff, 0x03, 
  };

  // GPRPair Register Class...
  const MCPhysReg GPRPair[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X0_Pair, RISCV::X2_X3, RISCV::X4_X5, 
  };

  // GPRPair Bit set.
  const uint8_t GPRPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x80, 0xff, 0x3f, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRNoX0 Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX0[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X2_X3, RISCV::X4_X5, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRNoX0 Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2 Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRNoX0X2[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, RISCV::X4_X5, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2 Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x3f, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRJALR Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRJALR[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, RISCV::X24_X25, RISCV::X26_X27, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRJALR Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRJALRBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
  };

  // FPR64C Register Class...
  const MCPhysReg FPR64C[] = {
    RISCV::F15_D, RISCV::F14_D, RISCV::F13_D, RISCV::F12_D, RISCV::F11_D, RISCV::F10_D, RISCV::F8_D, RISCV::F9_D, 
  };

  // FPR64C Bit set.
  const uint8_t FPR64CBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRTC Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRTC[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X16_X17, RISCV::X6_X7, RISCV::X28_X29, RISCV::X30_X31, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRTC Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRTCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7a, 0x30, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRC Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, RISCV::X8_X9, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRC Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // GPRPair_with_sub_gpr_even_in_SR07 Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_SR07[] = {
    RISCV::X8_X9, RISCV::X18_X19, RISCV::X20_X21, RISCV::X22_X23, 
  };

  // GPRPair_with_sub_gpr_even_in_SR07 Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_SR07Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x03, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC[] = {
    RISCV::X10_X11, RISCV::X12_X13, RISCV::X14_X15, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07 Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRC_and_SR07[] = {
    RISCV::X8_X9, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07 Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRX0 Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_GPRX0[] = {
    RISCV::X0_Pair, 
  };

  // GPRPair_with_sub_gpr_even_in_GPRX0 Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_GPRX0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // GPRPair_with_sub_gpr_even_in_SP Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_even_in_SP[] = {
    RISCV::X2_X3, 
  };

  // GPRPair_with_sub_gpr_even_in_SP Bit set.
  const uint8_t GPRPair_with_sub_gpr_even_in_SPBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
  };

  // GPRPair_with_sub_gpr_odd_in_GPRX1X5 Register Class...
  const MCPhysReg GPRPair_with_sub_gpr_odd_in_GPRX1X5[] = {
    RISCV::X4_X5, 
  };

  // GPRPair_with_sub_gpr_odd_in_GPRX1X5 Bit set.
  const uint8_t GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
  };

  // VMV0 Register Class...
  const MCPhysReg VMV0[] = {
    RISCV::V0, 
  };

  // VMV0 Bit set.
  const uint8_t VMV0Bits[] = {
    0x00, 0x04, 
  };

  // VRN2M1 Register Class...
  const MCPhysReg VRN2M1[] = {
    RISCV::V8_V9, RISCV::V9_V10, RISCV::V10_V11, RISCV::V11_V12, RISCV::V12_V13, RISCV::V13_V14, RISCV::V14_V15, RISCV::V15_V16, RISCV::V16_V17, RISCV::V17_V18, RISCV::V18_V19, RISCV::V19_V20, RISCV::V20_V21, RISCV::V21_V22, RISCV::V22_V23, RISCV::V23_V24, RISCV::V24_V25, RISCV::V25_V26, RISCV::V26_V27, RISCV::V27_V28, RISCV::V28_V29, RISCV::V29_V30, RISCV::V30_V31, RISCV::V1_V2, RISCV::V2_V3, RISCV::V3_V4, RISCV::V4_V5, RISCV::V5_V6, RISCV::V6_V7, RISCV::V7_V8, RISCV::V0_V1, 
  };

  // VRN2M1 Bit set.
  const uint8_t VRN2M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x1f, 
  };

  // VRN2M1NoV0 Register Class...
  const MCPhysReg VRN2M1NoV0[] = {
    RISCV::V8_V9, RISCV::V9_V10, RISCV::V10_V11, RISCV::V11_V12, RISCV::V12_V13, RISCV::V13_V14, RISCV::V14_V15, RISCV::V15_V16, RISCV::V16_V17, RISCV::V17_V18, RISCV::V18_V19, RISCV::V19_V20, RISCV::V20_V21, RISCV::V21_V22, RISCV::V22_V23, RISCV::V23_V24, RISCV::V24_V25, RISCV::V25_V26, RISCV::V26_V27, RISCV::V27_V28, RISCV::V28_V29, RISCV::V29_V30, RISCV::V30_V31, RISCV::V1_V2, RISCV::V2_V3, RISCV::V3_V4, RISCV::V4_V5, RISCV::V5_V6, RISCV::V6_V7, RISCV::V7_V8, 
  };

  // VRN2M1NoV0 Bit set.
  const uint8_t VRN2M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // VRM2 Register Class...
  const MCPhysReg VRM2[] = {
    RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2, RISCV::V24M2, RISCV::V26M2, RISCV::V28M2, RISCV::V30M2, RISCV::V0M2, RISCV::V2M2, RISCV::V4M2, RISCV::V6M2, 
  };

  // VRM2 Bit set.
  const uint8_t VRM2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc8, 0x66, 0xb3, 0x59, 
  };

  // VRM2NoV0 Register Class...
  const MCPhysReg VRM2NoV0[] = {
    RISCV::V8M2, RISCV::V10M2, RISCV::V12M2, RISCV::V14M2, RISCV::V16M2, RISCV::V18M2, RISCV::V20M2, RISCV::V22M2, RISCV::V24M2, RISCV::V26M2, RISCV::V28M2, RISCV::V30M2, RISCV::V2M2, RISCV::V4M2, RISCV::V6M2, 
  };

  // VRM2NoV0 Bit set.
  const uint8_t VRM2NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x66, 0xb3, 0x59, 
  };

  // VRM2_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRM2_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M2, 
  };

  // VRM2_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRM2_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // VRN2M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN2M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1, 
  };

  // VRN2M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN2M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // VRN3M1 Register Class...
  const MCPhysReg VRN3M1[] = {
    RISCV::V8_V9_V10, RISCV::V9_V10_V11, RISCV::V10_V11_V12, RISCV::V11_V12_V13, RISCV::V12_V13_V14, RISCV::V13_V14_V15, RISCV::V14_V15_V16, RISCV::V15_V16_V17, RISCV::V16_V17_V18, RISCV::V17_V18_V19, RISCV::V18_V19_V20, RISCV::V19_V20_V21, RISCV::V20_V21_V22, RISCV::V21_V22_V23, RISCV::V22_V23_V24, RISCV::V23_V24_V25, RISCV::V24_V25_V26, RISCV::V25_V26_V27, RISCV::V26_V27_V28, RISCV::V27_V28_V29, RISCV::V28_V29_V30, RISCV::V29_V30_V31, RISCV::V1_V2_V3, RISCV::V2_V3_V4, RISCV::V3_V4_V5, RISCV::V4_V5_V6, RISCV::V5_V6_V7, RISCV::V6_V7_V8, RISCV::V7_V8_V9, RISCV::V0_V1_V2, 
  };

  // VRN3M1 Bit set.
  const uint8_t VRN3M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x01, 
  };

  // VRN3M1NoV0 Register Class...
  const MCPhysReg VRN3M1NoV0[] = {
    RISCV::V8_V9_V10, RISCV::V9_V10_V11, RISCV::V10_V11_V12, RISCV::V11_V12_V13, RISCV::V12_V13_V14, RISCV::V13_V14_V15, RISCV::V14_V15_V16, RISCV::V15_V16_V17, RISCV::V16_V17_V18, RISCV::V17_V18_V19, RISCV::V18_V19_V20, RISCV::V19_V20_V21, RISCV::V20_V21_V22, RISCV::V21_V22_V23, RISCV::V22_V23_V24, RISCV::V23_V24_V25, RISCV::V24_V25_V26, RISCV::V25_V26_V27, RISCV::V26_V27_V28, RISCV::V27_V28_V29, RISCV::V28_V29_V30, RISCV::V29_V30_V31, RISCV::V1_V2_V3, RISCV::V2_V3_V4, RISCV::V3_V4_V5, RISCV::V4_V5_V6, RISCV::V5_V6_V7, RISCV::V6_V7_V8, RISCV::V7_V8_V9, 
  };

  // VRN3M1NoV0 Bit set.
  const uint8_t VRN3M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 
  };

  // VRN3M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN3M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1_V2, 
  };

  // VRN3M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN3M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
  };

  // VRN4M1 Register Class...
  const MCPhysReg VRN4M1[] = {
    RISCV::V8_V9_V10_V11, RISCV::V9_V10_V11_V12, RISCV::V10_V11_V12_V13, RISCV::V11_V12_V13_V14, RISCV::V12_V13_V14_V15, RISCV::V13_V14_V15_V16, RISCV::V14_V15_V16_V17, RISCV::V15_V16_V17_V18, RISCV::V16_V17_V18_V19, RISCV::V17_V18_V19_V20, RISCV::V18_V19_V20_V21, RISCV::V19_V20_V21_V22, RISCV::V20_V21_V22_V23, RISCV::V21_V22_V23_V24, RISCV::V22_V23_V24_V25, RISCV::V23_V24_V25_V26, RISCV::V24_V25_V26_V27, RISCV::V25_V26_V27_V28, RISCV::V26_V27_V28_V29, RISCV::V27_V28_V29_V30, RISCV::V28_V29_V30_V31, RISCV::V1_V2_V3_V4, RISCV::V2_V3_V4_V5, RISCV::V3_V4_V5_V6, RISCV::V4_V5_V6_V7, RISCV::V5_V6_V7_V8, RISCV::V6_V7_V8_V9, RISCV::V7_V8_V9_V10, RISCV::V0_V1_V2_V3, 
  };

  // VRN4M1 Bit set.
  const uint8_t VRN4M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
  };

  // VRN4M1NoV0 Register Class...
  const MCPhysReg VRN4M1NoV0[] = {
    RISCV::V8_V9_V10_V11, RISCV::V9_V10_V11_V12, RISCV::V10_V11_V12_V13, RISCV::V11_V12_V13_V14, RISCV::V12_V13_V14_V15, RISCV::V13_V14_V15_V16, RISCV::V14_V15_V16_V17, RISCV::V15_V16_V17_V18, RISCV::V16_V17_V18_V19, RISCV::V17_V18_V19_V20, RISCV::V18_V19_V20_V21, RISCV::V19_V20_V21_V22, RISCV::V20_V21_V22_V23, RISCV::V21_V22_V23_V24, RISCV::V22_V23_V24_V25, RISCV::V23_V24_V25_V26, RISCV::V24_V25_V26_V27, RISCV::V25_V26_V27_V28, RISCV::V26_V27_V28_V29, RISCV::V27_V28_V29_V30, RISCV::V28_V29_V30_V31, RISCV::V1_V2_V3_V4, RISCV::V2_V3_V4_V5, RISCV::V3_V4_V5_V6, RISCV::V4_V5_V6_V7, RISCV::V5_V6_V7_V8, RISCV::V6_V7_V8_V9, RISCV::V7_V8_V9_V10, 
  };

  // VRN4M1NoV0 Bit set.
  const uint8_t VRN4M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x07, 
  };

  // VRN2M2 Register Class...
  const MCPhysReg VRN2M2[] = {
    RISCV::V8M2_V10M2, RISCV::V10M2_V12M2, RISCV::V12M2_V14M2, RISCV::V14M2_V16M2, RISCV::V16M2_V18M2, RISCV::V18M2_V20M2, RISCV::V20M2_V22M2, RISCV::V22M2_V24M2, RISCV::V24M2_V26M2, RISCV::V26M2_V28M2, RISCV::V28M2_V30M2, RISCV::V2M2_V4M2, RISCV::V4M2_V6M2, RISCV::V6M2_V8M2, RISCV::V0M2_V2M2, 
  };

  // VRN2M2 Bit set.
  const uint8_t VRN2M2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f, 
  };

  // VRN2M2NoV0 Register Class...
  const MCPhysReg VRN2M2NoV0[] = {
    RISCV::V8M2_V10M2, RISCV::V10M2_V12M2, RISCV::V12M2_V14M2, RISCV::V14M2_V16M2, RISCV::V16M2_V18M2, RISCV::V18M2_V20M2, RISCV::V20M2_V22M2, RISCV::V22M2_V24M2, RISCV::V24M2_V26M2, RISCV::V26M2_V28M2, RISCV::V28M2_V30M2, RISCV::V2M2_V4M2, RISCV::V4M2_V6M2, RISCV::V6M2_V8M2, 
  };

  // VRN2M2NoV0 Bit set.
  const uint8_t VRN2M2NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07, 
  };

  // VRM4 Register Class...
  const MCPhysReg VRM4[] = {
    RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4, RISCV::V24M4, RISCV::V28M4, RISCV::V0M4, RISCV::V4M4, 
  };

  // VRM4 Bit set.
  const uint8_t VRM4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x89, 0x44, 0x22, 
  };

  // VRM4NoV0 Register Class...
  const MCPhysReg VRM4NoV0[] = {
    RISCV::V8M4, RISCV::V12M4, RISCV::V16M4, RISCV::V20M4, RISCV::V24M4, RISCV::V28M4, RISCV::V4M4, 
  };

  // VRM4NoV0 Bit set.
  const uint8_t VRM4NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x89, 0x44, 0x22, 
  };

  // VRM4_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRM4_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M4, 
  };

  // VRM4_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRM4_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // VRN2M2_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN2M2_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M2_V2M2, 
  };

  // VRN2M2_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN2M2_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // VRN4M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN4M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1_V2_V3, 
  };

  // VRN4M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN4M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 
  };

  // VRN5M1 Register Class...
  const MCPhysReg VRN5M1[] = {
    RISCV::V8_V9_V10_V11_V12, RISCV::V9_V10_V11_V12_V13, RISCV::V10_V11_V12_V13_V14, RISCV::V11_V12_V13_V14_V15, RISCV::V12_V13_V14_V15_V16, RISCV::V13_V14_V15_V16_V17, RISCV::V14_V15_V16_V17_V18, RISCV::V15_V16_V17_V18_V19, RISCV::V16_V17_V18_V19_V20, RISCV::V17_V18_V19_V20_V21, RISCV::V18_V19_V20_V21_V22, RISCV::V19_V20_V21_V22_V23, RISCV::V20_V21_V22_V23_V24, RISCV::V21_V22_V23_V24_V25, RISCV::V22_V23_V24_V25_V26, RISCV::V23_V24_V25_V26_V27, RISCV::V24_V25_V26_V27_V28, RISCV::V25_V26_V27_V28_V29, RISCV::V26_V27_V28_V29_V30, RISCV::V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5, RISCV::V2_V3_V4_V5_V6, RISCV::V3_V4_V5_V6_V7, RISCV::V4_V5_V6_V7_V8, RISCV::V5_V6_V7_V8_V9, RISCV::V6_V7_V8_V9_V10, RISCV::V7_V8_V9_V10_V11, RISCV::V0_V1_V2_V3_V4, 
  };

  // VRN5M1 Bit set.
  const uint8_t VRN5M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x1f, 
  };

  // VRN5M1NoV0 Register Class...
  const MCPhysReg VRN5M1NoV0[] = {
    RISCV::V8_V9_V10_V11_V12, RISCV::V9_V10_V11_V12_V13, RISCV::V10_V11_V12_V13_V14, RISCV::V11_V12_V13_V14_V15, RISCV::V12_V13_V14_V15_V16, RISCV::V13_V14_V15_V16_V17, RISCV::V14_V15_V16_V17_V18, RISCV::V15_V16_V17_V18_V19, RISCV::V16_V17_V18_V19_V20, RISCV::V17_V18_V19_V20_V21, RISCV::V18_V19_V20_V21_V22, RISCV::V19_V20_V21_V22_V23, RISCV::V20_V21_V22_V23_V24, RISCV::V21_V22_V23_V24_V25, RISCV::V22_V23_V24_V25_V26, RISCV::V23_V24_V25_V26_V27, RISCV::V24_V25_V26_V27_V28, RISCV::V25_V26_V27_V28_V29, RISCV::V26_V27_V28_V29_V30, RISCV::V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5, RISCV::V2_V3_V4_V5_V6, RISCV::V3_V4_V5_V6_V7, RISCV::V4_V5_V6_V7_V8, RISCV::V5_V6_V7_V8_V9, RISCV::V6_V7_V8_V9_V10, RISCV::V7_V8_V9_V10_V11, 
  };

  // VRN5M1NoV0 Bit set.
  const uint8_t VRN5M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0x0f, 
  };

  // VRN5M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN5M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1_V2_V3_V4, 
  };

  // VRN5M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN5M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 
  };

  // VRN6M1 Register Class...
  const MCPhysReg VRN6M1[] = {
    RISCV::V8_V9_V10_V11_V12_V13, RISCV::V9_V10_V11_V12_V13_V14, RISCV::V10_V11_V12_V13_V14_V15, RISCV::V11_V12_V13_V14_V15_V16, RISCV::V12_V13_V14_V15_V16_V17, RISCV::V13_V14_V15_V16_V17_V18, RISCV::V14_V15_V16_V17_V18_V19, RISCV::V15_V16_V17_V18_V19_V20, RISCV::V16_V17_V18_V19_V20_V21, RISCV::V17_V18_V19_V20_V21_V22, RISCV::V18_V19_V20_V21_V22_V23, RISCV::V19_V20_V21_V22_V23_V24, RISCV::V20_V21_V22_V23_V24_V25, RISCV::V21_V22_V23_V24_V25_V26, RISCV::V22_V23_V24_V25_V26_V27, RISCV::V23_V24_V25_V26_V27_V28, RISCV::V24_V25_V26_V27_V28_V29, RISCV::V25_V26_V27_V28_V29_V30, RISCV::V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6, RISCV::V2_V3_V4_V5_V6_V7, RISCV::V3_V4_V5_V6_V7_V8, RISCV::V4_V5_V6_V7_V8_V9, RISCV::V5_V6_V7_V8_V9_V10, RISCV::V6_V7_V8_V9_V10_V11, RISCV::V7_V8_V9_V10_V11_V12, RISCV::V0_V1_V2_V3_V4_V5, 
  };

  // VRN6M1 Bit set.
  const uint8_t VRN6M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 
  };

  // VRN6M1NoV0 Register Class...
  const MCPhysReg VRN6M1NoV0[] = {
    RISCV::V8_V9_V10_V11_V12_V13, RISCV::V9_V10_V11_V12_V13_V14, RISCV::V10_V11_V12_V13_V14_V15, RISCV::V11_V12_V13_V14_V15_V16, RISCV::V12_V13_V14_V15_V16_V17, RISCV::V13_V14_V15_V16_V17_V18, RISCV::V14_V15_V16_V17_V18_V19, RISCV::V15_V16_V17_V18_V19_V20, RISCV::V16_V17_V18_V19_V20_V21, RISCV::V17_V18_V19_V20_V21_V22, RISCV::V18_V19_V20_V21_V22_V23, RISCV::V19_V20_V21_V22_V23_V24, RISCV::V20_V21_V22_V23_V24_V25, RISCV::V21_V22_V23_V24_V25_V26, RISCV::V22_V23_V24_V25_V26_V27, RISCV::V23_V24_V25_V26_V27_V28, RISCV::V24_V25_V26_V27_V28_V29, RISCV::V25_V26_V27_V28_V29_V30, RISCV::V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6, RISCV::V2_V3_V4_V5_V6_V7, RISCV::V3_V4_V5_V6_V7_V8, RISCV::V4_V5_V6_V7_V8_V9, RISCV::V5_V6_V7_V8_V9_V10, RISCV::V6_V7_V8_V9_V10_V11, RISCV::V7_V8_V9_V10_V11_V12, 
  };

  // VRN6M1NoV0 Bit set.
  const uint8_t VRN6M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0x7f, 
  };

  // VRN3M2 Register Class...
  const MCPhysReg VRN3M2[] = {
    RISCV::V8M2_V10M2_V12M2, RISCV::V10M2_V12M2_V14M2, RISCV::V12M2_V14M2_V16M2, RISCV::V14M2_V16M2_V18M2, RISCV::V16M2_V18M2_V20M2, RISCV::V18M2_V20M2_V22M2, RISCV::V20M2_V22M2_V24M2, RISCV::V22M2_V24M2_V26M2, RISCV::V24M2_V26M2_V28M2, RISCV::V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2, RISCV::V4M2_V6M2_V8M2, RISCV::V6M2_V8M2_V10M2, RISCV::V0M2_V2M2_V4M2, 
  };

  // VRN3M2 Bit set.
  const uint8_t VRN3M2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 
  };

  // VRN3M2NoV0 Register Class...
  const MCPhysReg VRN3M2NoV0[] = {
    RISCV::V8M2_V10M2_V12M2, RISCV::V10M2_V12M2_V14M2, RISCV::V12M2_V14M2_V16M2, RISCV::V14M2_V16M2_V18M2, RISCV::V16M2_V18M2_V20M2, RISCV::V18M2_V20M2_V22M2, RISCV::V20M2_V22M2_V24M2, RISCV::V22M2_V24M2_V26M2, RISCV::V24M2_V26M2_V28M2, RISCV::V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2, RISCV::V4M2_V6M2_V8M2, RISCV::V6M2_V8M2_V10M2, 
  };

  // VRN3M2NoV0 Bit set.
  const uint8_t VRN3M2NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f, 
  };

  // VRN3M2_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN3M2_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M2_V2M2_V4M2, 
  };

  // VRN3M2_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN3M2_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 
  };

  // VRN6M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN6M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1_V2_V3_V4_V5, 
  };

  // VRN6M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN6M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 
  };

  // VRN7M1 Register Class...
  const MCPhysReg VRN7M1[] = {
    RISCV::V8_V9_V10_V11_V12_V13_V14, RISCV::V9_V10_V11_V12_V13_V14_V15, RISCV::V10_V11_V12_V13_V14_V15_V16, RISCV::V11_V12_V13_V14_V15_V16_V17, RISCV::V12_V13_V14_V15_V16_V17_V18, RISCV::V13_V14_V15_V16_V17_V18_V19, RISCV::V14_V15_V16_V17_V18_V19_V20, RISCV::V15_V16_V17_V18_V19_V20_V21, RISCV::V16_V17_V18_V19_V20_V21_V22, RISCV::V17_V18_V19_V20_V21_V22_V23, RISCV::V18_V19_V20_V21_V22_V23_V24, RISCV::V19_V20_V21_V22_V23_V24_V25, RISCV::V20_V21_V22_V23_V24_V25_V26, RISCV::V21_V22_V23_V24_V25_V26_V27, RISCV::V22_V23_V24_V25_V26_V27_V28, RISCV::V23_V24_V25_V26_V27_V28_V29, RISCV::V24_V25_V26_V27_V28_V29_V30, RISCV::V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7, RISCV::V2_V3_V4_V5_V6_V7_V8, RISCV::V3_V4_V5_V6_V7_V8_V9, RISCV::V4_V5_V6_V7_V8_V9_V10, RISCV::V5_V6_V7_V8_V9_V10_V11, RISCV::V6_V7_V8_V9_V10_V11_V12, RISCV::V7_V8_V9_V10_V11_V12_V13, RISCV::V0_V1_V2_V3_V4_V5_V6, 
  };

  // VRN7M1 Bit set.
  const uint8_t VRN7M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x03, 
  };

  // VRN7M1NoV0 Register Class...
  const MCPhysReg VRN7M1NoV0[] = {
    RISCV::V8_V9_V10_V11_V12_V13_V14, RISCV::V9_V10_V11_V12_V13_V14_V15, RISCV::V10_V11_V12_V13_V14_V15_V16, RISCV::V11_V12_V13_V14_V15_V16_V17, RISCV::V12_V13_V14_V15_V16_V17_V18, RISCV::V13_V14_V15_V16_V17_V18_V19, RISCV::V14_V15_V16_V17_V18_V19_V20, RISCV::V15_V16_V17_V18_V19_V20_V21, RISCV::V16_V17_V18_V19_V20_V21_V22, RISCV::V17_V18_V19_V20_V21_V22_V23, RISCV::V18_V19_V20_V21_V22_V23_V24, RISCV::V19_V20_V21_V22_V23_V24_V25, RISCV::V20_V21_V22_V23_V24_V25_V26, RISCV::V21_V22_V23_V24_V25_V26_V27, RISCV::V22_V23_V24_V25_V26_V27_V28, RISCV::V23_V24_V25_V26_V27_V28_V29, RISCV::V24_V25_V26_V27_V28_V29_V30, RISCV::V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7, RISCV::V2_V3_V4_V5_V6_V7_V8, RISCV::V3_V4_V5_V6_V7_V8_V9, RISCV::V4_V5_V6_V7_V8_V9_V10, RISCV::V5_V6_V7_V8_V9_V10_V11, RISCV::V6_V7_V8_V9_V10_V11_V12, RISCV::V7_V8_V9_V10_V11_V12_V13, 
  };

  // VRN7M1NoV0 Bit set.
  const uint8_t VRN7M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x01, 
  };

  // VRN7M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN7M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1_V2_V3_V4_V5_V6, 
  };

  // VRN7M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN7M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 
  };

  // VRN8M1 Register Class...
  const MCPhysReg VRN8M1[] = {
    RISCV::V8_V9_V10_V11_V12_V13_V14_V15, RISCV::V9_V10_V11_V12_V13_V14_V15_V16, RISCV::V10_V11_V12_V13_V14_V15_V16_V17, RISCV::V11_V12_V13_V14_V15_V16_V17_V18, RISCV::V12_V13_V14_V15_V16_V17_V18_V19, RISCV::V13_V14_V15_V16_V17_V18_V19_V20, RISCV::V14_V15_V16_V17_V18_V19_V20_V21, RISCV::V15_V16_V17_V18_V19_V20_V21_V22, RISCV::V16_V17_V18_V19_V20_V21_V22_V23, RISCV::V17_V18_V19_V20_V21_V22_V23_V24, RISCV::V18_V19_V20_V21_V22_V23_V24_V25, RISCV::V19_V20_V21_V22_V23_V24_V25_V26, RISCV::V20_V21_V22_V23_V24_V25_V26_V27, RISCV::V21_V22_V23_V24_V25_V26_V27_V28, RISCV::V22_V23_V24_V25_V26_V27_V28_V29, RISCV::V23_V24_V25_V26_V27_V28_V29_V30, RISCV::V24_V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7_V8, RISCV::V2_V3_V4_V5_V6_V7_V8_V9, RISCV::V3_V4_V5_V6_V7_V8_V9_V10, RISCV::V4_V5_V6_V7_V8_V9_V10_V11, RISCV::V5_V6_V7_V8_V9_V10_V11_V12, RISCV::V6_V7_V8_V9_V10_V11_V12_V13, RISCV::V7_V8_V9_V10_V11_V12_V13_V14, RISCV::V0_V1_V2_V3_V4_V5_V6_V7, 
  };

  // VRN8M1 Bit set.
  const uint8_t VRN8M1Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x07, 
  };

  // VRN8M1NoV0 Register Class...
  const MCPhysReg VRN8M1NoV0[] = {
    RISCV::V8_V9_V10_V11_V12_V13_V14_V15, RISCV::V9_V10_V11_V12_V13_V14_V15_V16, RISCV::V10_V11_V12_V13_V14_V15_V16_V17, RISCV::V11_V12_V13_V14_V15_V16_V17_V18, RISCV::V12_V13_V14_V15_V16_V17_V18_V19, RISCV::V13_V14_V15_V16_V17_V18_V19_V20, RISCV::V14_V15_V16_V17_V18_V19_V20_V21, RISCV::V15_V16_V17_V18_V19_V20_V21_V22, RISCV::V16_V17_V18_V19_V20_V21_V22_V23, RISCV::V17_V18_V19_V20_V21_V22_V23_V24, RISCV::V18_V19_V20_V21_V22_V23_V24_V25, RISCV::V19_V20_V21_V22_V23_V24_V25_V26, RISCV::V20_V21_V22_V23_V24_V25_V26_V27, RISCV::V21_V22_V23_V24_V25_V26_V27_V28, RISCV::V22_V23_V24_V25_V26_V27_V28_V29, RISCV::V23_V24_V25_V26_V27_V28_V29_V30, RISCV::V24_V25_V26_V27_V28_V29_V30_V31, RISCV::V1_V2_V3_V4_V5_V6_V7_V8, RISCV::V2_V3_V4_V5_V6_V7_V8_V9, RISCV::V3_V4_V5_V6_V7_V8_V9_V10, RISCV::V4_V5_V6_V7_V8_V9_V10_V11, RISCV::V5_V6_V7_V8_V9_V10_V11_V12, RISCV::V6_V7_V8_V9_V10_V11_V12_V13, RISCV::V7_V8_V9_V10_V11_V12_V13_V14, 
  };

  // VRN8M1NoV0 Bit set.
  const uint8_t VRN8M1NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0x03, 
  };

  // VRN4M2 Register Class...
  const MCPhysReg VRN4M2[] = {
    RISCV::V8M2_V10M2_V12M2_V14M2, RISCV::V10M2_V12M2_V14M2_V16M2, RISCV::V12M2_V14M2_V16M2_V18M2, RISCV::V14M2_V16M2_V18M2_V20M2, RISCV::V16M2_V18M2_V20M2_V22M2, RISCV::V18M2_V20M2_V22M2_V24M2, RISCV::V20M2_V22M2_V24M2_V26M2, RISCV::V22M2_V24M2_V26M2_V28M2, RISCV::V24M2_V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2_V8M2, RISCV::V4M2_V6M2_V8M2_V10M2, RISCV::V6M2_V8M2_V10M2_V12M2, RISCV::V0M2_V2M2_V4M2_V6M2, 
  };

  // VRN4M2 Bit set.
  const uint8_t VRN4M2Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
  };

  // VRN4M2NoV0 Register Class...
  const MCPhysReg VRN4M2NoV0[] = {
    RISCV::V8M2_V10M2_V12M2_V14M2, RISCV::V10M2_V12M2_V14M2_V16M2, RISCV::V12M2_V14M2_V16M2_V18M2, RISCV::V14M2_V16M2_V18M2_V20M2, RISCV::V16M2_V18M2_V20M2_V22M2, RISCV::V18M2_V20M2_V22M2_V24M2, RISCV::V20M2_V22M2_V24M2_V26M2, RISCV::V22M2_V24M2_V26M2_V28M2, RISCV::V24M2_V26M2_V28M2_V30M2, RISCV::V2M2_V4M2_V6M2_V8M2, RISCV::V4M2_V6M2_V8M2_V10M2, RISCV::V6M2_V8M2_V10M2_V12M2, 
  };

  // VRN4M2NoV0 Bit set.
  const uint8_t VRN4M2NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 
  };

  // VRN2M4 Register Class...
  const MCPhysReg VRN2M4[] = {
    RISCV::V8M4_V12M4, RISCV::V12M4_V16M4, RISCV::V16M4_V20M4, RISCV::V20M4_V24M4, RISCV::V24M4_V28M4, RISCV::V4M4_V8M4, RISCV::V0M4_V4M4, 
  };

  // VRN2M4 Bit set.
  const uint8_t VRN2M4Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 
  };

  // VRN2M4NoV0 Register Class...
  const MCPhysReg VRN2M4NoV0[] = {
    RISCV::V8M4_V12M4, RISCV::V12M4_V16M4, RISCV::V16M4_V20M4, RISCV::V20M4_V24M4, RISCV::V24M4_V28M4, RISCV::V4M4_V8M4, 
  };

  // VRN2M4NoV0 Bit set.
  const uint8_t VRN2M4NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x03, 
  };

  // VRM8 Register Class...
  const MCPhysReg VRM8[] = {
    RISCV::V8M8, RISCV::V16M8, RISCV::V24M8, RISCV::V0M8, 
  };

  // VRM8 Bit set.
  const uint8_t VRM8Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x10, 0x08, 0x04, 
  };

  // VRM8NoV0 Register Class...
  const MCPhysReg VRM8NoV0[] = {
    RISCV::V8M8, RISCV::V16M8, RISCV::V24M8, 
  };

  // VRM8NoV0 Bit set.
  const uint8_t VRM8NoV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x08, 0x04, 
  };

  // VRM8_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRM8_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M8, 
  };

  // VRM8_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRM8_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 
  };

  // VRN2M4_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN2M4_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M4_V4M4, 
  };

  // VRN2M4_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN2M4_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

  // VRN4M2_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN4M2_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0M2_V2M2_V4M2_V6M2, 
  };

  // VRN4M2_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN4M2_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 
  };

  // VRN8M1_with_sub_vrm1_0_in_VMV0 Register Class...
  const MCPhysReg VRN8M1_with_sub_vrm1_0_in_VMV0[] = {
    RISCV::V0_V1_V2_V3_V4_V5_V6_V7, 
  };

  // VRN8M1_with_sub_vrm1_0_in_VMV0 Bit set.
  const uint8_t VRN8M1_with_sub_vrm1_0_in_VMV0Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char RISCVRegClassStrings[] = {
  /* 0 */ "VRN2M1_with_sub_vrm1_0_in_VMV0\0"
  /* 31 */ "VRN3M1_with_sub_vrm1_0_in_VMV0\0"
  /* 62 */ "VRN4M1_with_sub_vrm1_0_in_VMV0\0"
  /* 93 */ "VRN5M1_with_sub_vrm1_0_in_VMV0\0"
  /* 124 */ "VRN6M1_with_sub_vrm1_0_in_VMV0\0"
  /* 155 */ "VRN7M1_with_sub_vrm1_0_in_VMV0\0"
  /* 186 */ "VRN8M1_with_sub_vrm1_0_in_VMV0\0"
  /* 217 */ "VRN2M2_with_sub_vrm1_0_in_VMV0\0"
  /* 248 */ "VRN3M2_with_sub_vrm1_0_in_VMV0\0"
  /* 279 */ "VRN4M2_with_sub_vrm1_0_in_VMV0\0"
  /* 310 */ "VRM2_with_sub_vrm1_0_in_VMV0\0"
  /* 339 */ "VRN2M4_with_sub_vrm1_0_in_VMV0\0"
  /* 370 */ "VRM4_with_sub_vrm1_0_in_VMV0\0"
  /* 399 */ "VRM8_with_sub_vrm1_0_in_VMV0\0"
  /* 428 */ "VRN2M1NoV0\0"
  /* 439 */ "VRN3M1NoV0\0"
  /* 450 */ "VRN4M1NoV0\0"
  /* 461 */ "VRN5M1NoV0\0"
  /* 472 */ "VRN6M1NoV0\0"
  /* 483 */ "VRN7M1NoV0\0"
  /* 494 */ "VRN8M1NoV0\0"
  /* 505 */ "VRN2M2NoV0\0"
  /* 516 */ "VRN3M2NoV0\0"
  /* 527 */ "VRN4M2NoV0\0"
  /* 538 */ "VRM2NoV0\0"
  /* 547 */ "VRN2M4NoV0\0"
  /* 558 */ "VRM4NoV0\0"
  /* 567 */ "VRM8NoV0\0"
  /* 576 */ "VRNoV0\0"
  /* 583 */ "GPRPair_with_sub_gpr_even_in_GPRX0\0"
  /* 618 */ "GPRPair_with_sub_gpr_even_in_GPRNoX0\0"
  /* 655 */ "VRN2M1\0"
  /* 662 */ "VRN3M1\0"
  /* 669 */ "VRN4M1\0"
  /* 676 */ "VRN5M1\0"
  /* 683 */ "VRN6M1\0"
  /* 690 */ "VRN7M1\0"
  /* 697 */ "VRN8M1\0"
  /* 704 */ "GPRX1\0"
  /* 710 */ "GPRF32\0"
  /* 717 */ "FPR32\0"
  /* 723 */ "VRN2M2\0"
  /* 730 */ "VRN3M2\0"
  /* 737 */ "VRN4M2\0"
  /* 744 */ "VRM2\0"
  /* 749 */ "GPRPair_with_sub_gpr_even_in_GPRNoX0X2\0"
  /* 788 */ "FPR64\0"
  /* 794 */ "VRN2M4\0"
  /* 801 */ "VRM4\0"
  /* 806 */ "GPRPair_with_sub_gpr_odd_in_GPRX1X5\0"
  /* 842 */ "GPRX5\0"
  /* 848 */ "GPRF16\0"
  /* 855 */ "FPR16\0"
  /* 861 */ "GPRPair_with_sub_gpr_even_in_GPRC_and_SR07\0"
  /* 904 */ "GPRPair_with_sub_gpr_even_in_SR07\0"
  /* 938 */ "VRM8\0"
  /* 943 */ "FPR32C\0"
  /* 950 */ "FPR64C\0"
  /* 957 */ "GPRPair_with_sub_gpr_even_in_GPRC\0"
  /* 991 */ "GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC\0"
  /* 1035 */ "GPRPair_with_sub_gpr_even_in_GPRTC\0"
  /* 1070 */ "VM\0"
  /* 1073 */ "GPRPair_with_sub_gpr_even_in_SP\0"
  /* 1105 */ "GPRPair_with_sub_gpr_even_in_GPRJALR\0"
  /* 1142 */ "GPR\0"
  /* 1146 */ "VCSR\0"
  /* 1151 */ "VR\0"
  /* 1154 */ "GPRAll\0"
  /* 1161 */ "GPRPair\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass RISCVMCRegisterClasses[] = {
  { FPR16, FPR16Bits, 855, 32, sizeof(FPR16Bits), RISCV::FPR16RegClassID, 16, 1, true },
  { GPRAll, GPRAllBits, 1154, 33, sizeof(GPRAllBits), RISCV::GPRAllRegClassID, 0, 1, true },
  { FPR32, FPR32Bits, 717, 32, sizeof(FPR32Bits), RISCV::FPR32RegClassID, 32, 1, true },
  { GPR, GPRBits, 1142, 32, sizeof(GPRBits), RISCV::GPRRegClassID, 0, 1, true },
  { GPRF16, GPRF16Bits, 848, 32, sizeof(GPRF16Bits), RISCV::GPRF16RegClassID, 0, 1, true },
  { GPRF32, GPRF32Bits, 710, 32, sizeof(GPRF32Bits), RISCV::GPRF32RegClassID, 0, 1, true },
  { GPRNoX0, GPRNoX0Bits, 647, 31, sizeof(GPRNoX0Bits), RISCV::GPRNoX0RegClassID, 0, 1, true },
  { GPRNoX0X2, GPRNoX0X2Bits, 778, 30, sizeof(GPRNoX0X2Bits), RISCV::GPRNoX0X2RegClassID, 0, 1, true },
  { GPRJALR, GPRJALRBits, 1134, 26, sizeof(GPRJALRBits), RISCV::GPRJALRRegClassID, 0, 1, true },
  { GPRTC, GPRTCBits, 1029, 14, sizeof(GPRTCBits), RISCV::GPRTCRegClassID, 0, 1, true },
  { FPR32C, FPR32CBits, 943, 8, sizeof(FPR32CBits), RISCV::FPR32CRegClassID, 32, 1, true },
  { GPRC, GPRCBits, 986, 8, sizeof(GPRCBits), RISCV::GPRCRegClassID, 0, 1, true },
  { SR07, SR07Bits, 899, 8, sizeof(SR07Bits), RISCV::SR07RegClassID, 0, 1, true },
  { GPRC_and_GPRTC, GPRC_and_GPRTCBits, 1020, 6, sizeof(GPRC_and_GPRTCBits), RISCV::GPRC_and_GPRTCRegClassID, 0, 1, true },
  { VCSR, VCSRBits, 1146, 3, sizeof(VCSRBits), RISCV::VCSRRegClassID, 0, 1, false },
  { GPRC_and_SR07, GPRC_and_SR07Bits, 890, 2, sizeof(GPRC_and_SR07Bits), RISCV::GPRC_and_SR07RegClassID, 0, 1, true },
  { GPRX1X5, GPRX1X5Bits, 834, 2, sizeof(GPRX1X5Bits), RISCV::GPRX1X5RegClassID, 0, 1, true },
  { GPRX0, GPRX0Bits, 612, 1, sizeof(GPRX0Bits), RISCV::GPRX0RegClassID, 0, 1, true },
  { GPRX1, GPRX1Bits, 704, 1, sizeof(GPRX1Bits), RISCV::GPRX1RegClassID, 0, 1, true },
  { GPRX5, GPRX5Bits, 842, 1, sizeof(GPRX5Bits), RISCV::GPRX5RegClassID, 0, 1, true },
  { SP, SPBits, 1102, 1, sizeof(SPBits), RISCV::SPRegClassID, 0, 1, true },
  { FPR64, FPR64Bits, 788, 32, sizeof(FPR64Bits), RISCV::FPR64RegClassID, 64, 1, true },
  { VM, VMBits, 1070, 32, sizeof(VMBits), RISCV::VMRegClassID, 64, 1, true },
  { VR, VRBits, 1151, 32, sizeof(VRBits), RISCV::VRRegClassID, 64, 1, true },
  { VRNoV0, VRNoV0Bits, 576, 31, sizeof(VRNoV0Bits), RISCV::VRNoV0RegClassID, 64, 1, true },
  { GPRPair, GPRPairBits, 1161, 16, sizeof(GPRPairBits), RISCV::GPRPairRegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRNoX0, GPRPair_with_sub_gpr_even_in_GPRNoX0Bits, 618, 15, sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX0Bits), RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRNoX0X2, GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits, 749, 14, sizeof(GPRPair_with_sub_gpr_even_in_GPRNoX0X2Bits), RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRJALR, GPRPair_with_sub_gpr_even_in_GPRJALRBits, 1105, 13, sizeof(GPRPair_with_sub_gpr_even_in_GPRJALRBits), RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID, 0, 1, true },
  { FPR64C, FPR64CBits, 950, 8, sizeof(FPR64CBits), RISCV::FPR64CRegClassID, 64, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRTC, GPRPair_with_sub_gpr_even_in_GPRTCBits, 1035, 7, sizeof(GPRPair_with_sub_gpr_even_in_GPRTCBits), RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRC, GPRPair_with_sub_gpr_even_in_GPRCBits, 957, 4, sizeof(GPRPair_with_sub_gpr_even_in_GPRCBits), RISCV::GPRPair_with_sub_gpr_even_in_GPRCRegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_SR07, GPRPair_with_sub_gpr_even_in_SR07Bits, 904, 4, sizeof(GPRPair_with_sub_gpr_even_in_SR07Bits), RISCV::GPRPair_with_sub_gpr_even_in_SR07RegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC, GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits, 991, 3, sizeof(GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCBits), RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRC_and_SR07, GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits, 861, 1, sizeof(GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Bits), RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_GPRX0, GPRPair_with_sub_gpr_even_in_GPRX0Bits, 583, 1, sizeof(GPRPair_with_sub_gpr_even_in_GPRX0Bits), RISCV::GPRPair_with_sub_gpr_even_in_GPRX0RegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_even_in_SP, GPRPair_with_sub_gpr_even_in_SPBits, 1073, 1, sizeof(GPRPair_with_sub_gpr_even_in_SPBits), RISCV::GPRPair_with_sub_gpr_even_in_SPRegClassID, 0, 1, true },
  { GPRPair_with_sub_gpr_odd_in_GPRX1X5, GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits, 806, 1, sizeof(GPRPair_with_sub_gpr_odd_in_GPRX1X5Bits), RISCV::GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID, 0, 1, true },
  { VMV0, VMV0Bits, 26, 1, sizeof(VMV0Bits), RISCV::VMV0RegClassID, 64, 1, true },
  { VRN2M1, VRN2M1Bits, 655, 31, sizeof(VRN2M1Bits), RISCV::VRN2M1RegClassID, 128, 1, true },
  { VRN2M1NoV0, VRN2M1NoV0Bits, 428, 30, sizeof(VRN2M1NoV0Bits), RISCV::VRN2M1NoV0RegClassID, 128, 1, true },
  { VRM2, VRM2Bits, 744, 16, sizeof(VRM2Bits), RISCV::VRM2RegClassID, 128, 1, true },
  { VRM2NoV0, VRM2NoV0Bits, 538, 15, sizeof(VRM2NoV0Bits), RISCV::VRM2NoV0RegClassID, 128, 1, true },
  { VRM2_with_sub_vrm1_0_in_VMV0, VRM2_with_sub_vrm1_0_in_VMV0Bits, 310, 1, sizeof(VRM2_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClassID, 128, 1, true },
  { VRN2M1_with_sub_vrm1_0_in_VMV0, VRN2M1_with_sub_vrm1_0_in_VMV0Bits, 0, 1, sizeof(VRN2M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID, 128, 1, true },
  { VRN3M1, VRN3M1Bits, 662, 30, sizeof(VRN3M1Bits), RISCV::VRN3M1RegClassID, 192, 1, true },
  { VRN3M1NoV0, VRN3M1NoV0Bits, 439, 29, sizeof(VRN3M1NoV0Bits), RISCV::VRN3M1NoV0RegClassID, 192, 1, true },
  { VRN3M1_with_sub_vrm1_0_in_VMV0, VRN3M1_with_sub_vrm1_0_in_VMV0Bits, 31, 1, sizeof(VRN3M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID, 192, 1, true },
  { VRN4M1, VRN4M1Bits, 669, 29, sizeof(VRN4M1Bits), RISCV::VRN4M1RegClassID, 256, 1, true },
  { VRN4M1NoV0, VRN4M1NoV0Bits, 450, 28, sizeof(VRN4M1NoV0Bits), RISCV::VRN4M1NoV0RegClassID, 256, 1, true },
  { VRN2M2, VRN2M2Bits, 723, 15, sizeof(VRN2M2Bits), RISCV::VRN2M2RegClassID, 256, 1, true },
  { VRN2M2NoV0, VRN2M2NoV0Bits, 505, 14, sizeof(VRN2M2NoV0Bits), RISCV::VRN2M2NoV0RegClassID, 256, 1, true },
  { VRM4, VRM4Bits, 801, 8, sizeof(VRM4Bits), RISCV::VRM4RegClassID, 256, 1, true },
  { VRM4NoV0, VRM4NoV0Bits, 558, 7, sizeof(VRM4NoV0Bits), RISCV::VRM4NoV0RegClassID, 256, 1, true },
  { VRM4_with_sub_vrm1_0_in_VMV0, VRM4_with_sub_vrm1_0_in_VMV0Bits, 370, 1, sizeof(VRM4_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClassID, 256, 1, true },
  { VRN2M2_with_sub_vrm1_0_in_VMV0, VRN2M2_with_sub_vrm1_0_in_VMV0Bits, 217, 1, sizeof(VRN2M2_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN2M2_with_sub_vrm1_0_in_VMV0RegClassID, 256, 1, true },
  { VRN4M1_with_sub_vrm1_0_in_VMV0, VRN4M1_with_sub_vrm1_0_in_VMV0Bits, 62, 1, sizeof(VRN4M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID, 256, 1, true },
  { VRN5M1, VRN5M1Bits, 676, 28, sizeof(VRN5M1Bits), RISCV::VRN5M1RegClassID, 320, 1, true },
  { VRN5M1NoV0, VRN5M1NoV0Bits, 461, 27, sizeof(VRN5M1NoV0Bits), RISCV::VRN5M1NoV0RegClassID, 320, 1, true },
  { VRN5M1_with_sub_vrm1_0_in_VMV0, VRN5M1_with_sub_vrm1_0_in_VMV0Bits, 93, 1, sizeof(VRN5M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID, 320, 1, true },
  { VRN6M1, VRN6M1Bits, 683, 27, sizeof(VRN6M1Bits), RISCV::VRN6M1RegClassID, 384, 1, true },
  { VRN6M1NoV0, VRN6M1NoV0Bits, 472, 26, sizeof(VRN6M1NoV0Bits), RISCV::VRN6M1NoV0RegClassID, 384, 1, true },
  { VRN3M2, VRN3M2Bits, 730, 14, sizeof(VRN3M2Bits), RISCV::VRN3M2RegClassID, 384, 1, true },
  { VRN3M2NoV0, VRN3M2NoV0Bits, 516, 13, sizeof(VRN3M2NoV0Bits), RISCV::VRN3M2NoV0RegClassID, 384, 1, true },
  { VRN3M2_with_sub_vrm1_0_in_VMV0, VRN3M2_with_sub_vrm1_0_in_VMV0Bits, 248, 1, sizeof(VRN3M2_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN3M2_with_sub_vrm1_0_in_VMV0RegClassID, 384, 1, true },
  { VRN6M1_with_sub_vrm1_0_in_VMV0, VRN6M1_with_sub_vrm1_0_in_VMV0Bits, 124, 1, sizeof(VRN6M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID, 384, 1, true },
  { VRN7M1, VRN7M1Bits, 690, 26, sizeof(VRN7M1Bits), RISCV::VRN7M1RegClassID, 448, 1, true },
  { VRN7M1NoV0, VRN7M1NoV0Bits, 483, 25, sizeof(VRN7M1NoV0Bits), RISCV::VRN7M1NoV0RegClassID, 448, 1, true },
  { VRN7M1_with_sub_vrm1_0_in_VMV0, VRN7M1_with_sub_vrm1_0_in_VMV0Bits, 155, 1, sizeof(VRN7M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID, 448, 1, true },
  { VRN8M1, VRN8M1Bits, 697, 25, sizeof(VRN8M1Bits), RISCV::VRN8M1RegClassID, 512, 1, true },
  { VRN8M1NoV0, VRN8M1NoV0Bits, 494, 24, sizeof(VRN8M1NoV0Bits), RISCV::VRN8M1NoV0RegClassID, 512, 1, true },
  { VRN4M2, VRN4M2Bits, 737, 13, sizeof(VRN4M2Bits), RISCV::VRN4M2RegClassID, 512, 1, true },
  { VRN4M2NoV0, VRN4M2NoV0Bits, 527, 12, sizeof(VRN4M2NoV0Bits), RISCV::VRN4M2NoV0RegClassID, 512, 1, true },
  { VRN2M4, VRN2M4Bits, 794, 7, sizeof(VRN2M4Bits), RISCV::VRN2M4RegClassID, 512, 1, true },
  { VRN2M4NoV0, VRN2M4NoV0Bits, 547, 6, sizeof(VRN2M4NoV0Bits), RISCV::VRN2M4NoV0RegClassID, 512, 1, true },
  { VRM8, VRM8Bits, 938, 4, sizeof(VRM8Bits), RISCV::VRM8RegClassID, 512, 1, true },
  { VRM8NoV0, VRM8NoV0Bits, 567, 3, sizeof(VRM8NoV0Bits), RISCV::VRM8NoV0RegClassID, 512, 1, true },
  { VRM8_with_sub_vrm1_0_in_VMV0, VRM8_with_sub_vrm1_0_in_VMV0Bits, 399, 1, sizeof(VRM8_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClassID, 512, 1, true },
  { VRN2M4_with_sub_vrm1_0_in_VMV0, VRN2M4_with_sub_vrm1_0_in_VMV0Bits, 339, 1, sizeof(VRN2M4_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN2M4_with_sub_vrm1_0_in_VMV0RegClassID, 512, 1, true },
  { VRN4M2_with_sub_vrm1_0_in_VMV0, VRN4M2_with_sub_vrm1_0_in_VMV0Bits, 279, 1, sizeof(VRN4M2_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN4M2_with_sub_vrm1_0_in_VMV0RegClassID, 512, 1, true },
  { VRN8M1_with_sub_vrm1_0_in_VMV0, VRN8M1_with_sub_vrm1_0_in_VMV0Bits, 186, 1, sizeof(VRN8M1_with_sub_vrm1_0_in_VMV0Bits), RISCV::VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID, 512, 1, true },
};

// RISCV Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[] = {
  { 0U, RISCV::X0 },
  { 1U, RISCV::X1 },
  { 2U, RISCV::X2 },
  { 3U, RISCV::X3 },
  { 4U, RISCV::X4 },
  { 5U, RISCV::X5 },
  { 6U, RISCV::X6 },
  { 7U, RISCV::X7 },
  { 8U, RISCV::X8 },
  { 9U, RISCV::X9 },
  { 10U, RISCV::X10 },
  { 11U, RISCV::X11 },
  { 12U, RISCV::X12 },
  { 13U, RISCV::X13 },
  { 14U, RISCV::X14 },
  { 15U, RISCV::X15 },
  { 16U, RISCV::X16 },
  { 17U, RISCV::X17 },
  { 18U, RISCV::X18 },
  { 19U, RISCV::X19 },
  { 20U, RISCV::X20 },
  { 21U, RISCV::X21 },
  { 22U, RISCV::X22 },
  { 23U, RISCV::X23 },
  { 24U, RISCV::X24 },
  { 25U, RISCV::X25 },
  { 26U, RISCV::X26 },
  { 27U, RISCV::X27 },
  { 28U, RISCV::X28 },
  { 29U, RISCV::X29 },
  { 30U, RISCV::X30 },
  { 31U, RISCV::X31 },
  { 32U, RISCV::F0_H },
  { 33U, RISCV::F1_H },
  { 34U, RISCV::F2_H },
  { 35U, RISCV::F3_H },
  { 36U, RISCV::F4_H },
  { 37U, RISCV::F5_H },
  { 38U, RISCV::F6_H },
  { 39U, RISCV::F7_H },
  { 40U, RISCV::F8_H },
  { 41U, RISCV::F9_H },
  { 42U, RISCV::F10_H },
  { 43U, RISCV::F11_H },
  { 44U, RISCV::F12_H },
  { 45U, RISCV::F13_H },
  { 46U, RISCV::F14_H },
  { 47U, RISCV::F15_H },
  { 48U, RISCV::F16_H },
  { 49U, RISCV::F17_H },
  { 50U, RISCV::F18_H },
  { 51U, RISCV::F19_H },
  { 52U, RISCV::F20_H },
  { 53U, RISCV::F21_H },
  { 54U, RISCV::F22_H },
  { 55U, RISCV::F23_H },
  { 56U, RISCV::F24_H },
  { 57U, RISCV::F25_H },
  { 58U, RISCV::F26_H },
  { 59U, RISCV::F27_H },
  { 60U, RISCV::F28_H },
  { 61U, RISCV::F29_H },
  { 62U, RISCV::F30_H },
  { 63U, RISCV::F31_H },
  { 96U, RISCV::V0 },
  { 97U, RISCV::V1 },
  { 98U, RISCV::V2 },
  { 99U, RISCV::V3 },
  { 100U, RISCV::V4 },
  { 101U, RISCV::V5 },
  { 102U, RISCV::V6 },
  { 103U, RISCV::V7 },
  { 104U, RISCV::V8 },
  { 105U, RISCV::V9 },
  { 106U, RISCV::V10 },
  { 107U, RISCV::V11 },
  { 108U, RISCV::V12 },
  { 109U, RISCV::V13 },
  { 110U, RISCV::V14 },
  { 111U, RISCV::V15 },
  { 112U, RISCV::V16 },
  { 113U, RISCV::V17 },
  { 114U, RISCV::V18 },
  { 115U, RISCV::V19 },
  { 116U, RISCV::V20 },
  { 117U, RISCV::V21 },
  { 118U, RISCV::V22 },
  { 119U, RISCV::V23 },
  { 120U, RISCV::V24 },
  { 121U, RISCV::V25 },
  { 122U, RISCV::V26 },
  { 123U, RISCV::V27 },
  { 124U, RISCV::V28 },
  { 125U, RISCV::V29 },
  { 126U, RISCV::V30 },
  { 127U, RISCV::V31 },
  { 7202U, RISCV::VLENB },
};
extern const unsigned RISCVDwarfFlavour0Dwarf2LSize = std::size(RISCVDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[] = {
  { 0U, RISCV::X0 },
  { 1U, RISCV::X1 },
  { 2U, RISCV::X2 },
  { 3U, RISCV::X3 },
  { 4U, RISCV::X4 },
  { 5U, RISCV::X5 },
  { 6U, RISCV::X6 },
  { 7U, RISCV::X7 },
  { 8U, RISCV::X8 },
  { 9U, RISCV::X9 },
  { 10U, RISCV::X10 },
  { 11U, RISCV::X11 },
  { 12U, RISCV::X12 },
  { 13U, RISCV::X13 },
  { 14U, RISCV::X14 },
  { 15U, RISCV::X15 },
  { 16U, RISCV::X16 },
  { 17U, RISCV::X17 },
  { 18U, RISCV::X18 },
  { 19U, RISCV::X19 },
  { 20U, RISCV::X20 },
  { 21U, RISCV::X21 },
  { 22U, RISCV::X22 },
  { 23U, RISCV::X23 },
  { 24U, RISCV::X24 },
  { 25U, RISCV::X25 },
  { 26U, RISCV::X26 },
  { 27U, RISCV::X27 },
  { 28U, RISCV::X28 },
  { 29U, RISCV::X29 },
  { 30U, RISCV::X30 },
  { 31U, RISCV::X31 },
  { 32U, RISCV::F0_H },
  { 33U, RISCV::F1_H },
  { 34U, RISCV::F2_H },
  { 35U, RISCV::F3_H },
  { 36U, RISCV::F4_H },
  { 37U, RISCV::F5_H },
  { 38U, RISCV::F6_H },
  { 39U, RISCV::F7_H },
  { 40U, RISCV::F8_H },
  { 41U, RISCV::F9_H },
  { 42U, RISCV::F10_H },
  { 43U, RISCV::F11_H },
  { 44U, RISCV::F12_H },
  { 45U, RISCV::F13_H },
  { 46U, RISCV::F14_H },
  { 47U, RISCV::F15_H },
  { 48U, RISCV::F16_H },
  { 49U, RISCV::F17_H },
  { 50U, RISCV::F18_H },
  { 51U, RISCV::F19_H },
  { 52U, RISCV::F20_H },
  { 53U, RISCV::F21_H },
  { 54U, RISCV::F22_H },
  { 55U, RISCV::F23_H },
  { 56U, RISCV::F24_H },
  { 57U, RISCV::F25_H },
  { 58U, RISCV::F26_H },
  { 59U, RISCV::F27_H },
  { 60U, RISCV::F28_H },
  { 61U, RISCV::F29_H },
  { 62U, RISCV::F30_H },
  { 63U, RISCV::F31_H },
  { 96U, RISCV::V0 },
  { 97U, RISCV::V1 },
  { 98U, RISCV::V2 },
  { 99U, RISCV::V3 },
  { 100U, RISCV::V4 },
  { 101U, RISCV::V5 },
  { 102U, RISCV::V6 },
  { 103U, RISCV::V7 },
  { 104U, RISCV::V8 },
  { 105U, RISCV::V9 },
  { 106U, RISCV::V10 },
  { 107U, RISCV::V11 },
  { 108U, RISCV::V12 },
  { 109U, RISCV::V13 },
  { 110U, RISCV::V14 },
  { 111U, RISCV::V15 },
  { 112U, RISCV::V16 },
  { 113U, RISCV::V17 },
  { 114U, RISCV::V18 },
  { 115U, RISCV::V19 },
  { 116U, RISCV::V20 },
  { 117U, RISCV::V21 },
  { 118U, RISCV::V22 },
  { 119U, RISCV::V23 },
  { 120U, RISCV::V24 },
  { 121U, RISCV::V25 },
  { 122U, RISCV::V26 },
  { 123U, RISCV::V27 },
  { 124U, RISCV::V28 },
  { 125U, RISCV::V29 },
  { 126U, RISCV::V30 },
  { 127U, RISCV::V31 },
  { 7202U, RISCV::VLENB },
};
extern const unsigned RISCVEHFlavour0Dwarf2LSize = std::size(RISCVEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[] = {
  { RISCV::VLENB, 7202U },
  { RISCV::V0, 96U },
  { RISCV::V1, 97U },
  { RISCV::V2, 98U },
  { RISCV::V3, 99U },
  { RISCV::V4, 100U },
  { RISCV::V5, 101U },
  { RISCV::V6, 102U },
  { RISCV::V7, 103U },
  { RISCV::V8, 104U },
  { RISCV::V9, 105U },
  { RISCV::V10, 106U },
  { RISCV::V11, 107U },
  { RISCV::V12, 108U },
  { RISCV::V13, 109U },
  { RISCV::V14, 110U },
  { RISCV::V15, 111U },
  { RISCV::V16, 112U },
  { RISCV::V17, 113U },
  { RISCV::V18, 114U },
  { RISCV::V19, 115U },
  { RISCV::V20, 116U },
  { RISCV::V21, 117U },
  { RISCV::V22, 118U },
  { RISCV::V23, 119U },
  { RISCV::V24, 120U },
  { RISCV::V25, 121U },
  { RISCV::V26, 122U },
  { RISCV::V27, 123U },
  { RISCV::V28, 124U },
  { RISCV::V29, 125U },
  { RISCV::V30, 126U },
  { RISCV::V31, 127U },
  { RISCV::X0, 0U },
  { RISCV::X1, 1U },
  { RISCV::X2, 2U },
  { RISCV::X3, 3U },
  { RISCV::X4, 4U },
  { RISCV::X5, 5U },
  { RISCV::X6, 6U },
  { RISCV::X7, 7U },
  { RISCV::X8, 8U },
  { RISCV::X9, 9U },
  { RISCV::X10, 10U },
  { RISCV::X11, 11U },
  { RISCV::X12, 12U },
  { RISCV::X13, 13U },
  { RISCV::X14, 14U },
  { RISCV::X15, 15U },
  { RISCV::X16, 16U },
  { RISCV::X17, 17U },
  { RISCV::X18, 18U },
  { RISCV::X19, 19U },
  { RISCV::X20, 20U },
  { RISCV::X21, 21U },
  { RISCV::X22, 22U },
  { RISCV::X23, 23U },
  { RISCV::X24, 24U },
  { RISCV::X25, 25U },
  { RISCV::X26, 26U },
  { RISCV::X27, 27U },
  { RISCV::X28, 28U },
  { RISCV::X29, 29U },
  { RISCV::X30, 30U },
  { RISCV::X31, 31U },
  { RISCV::F0_D, 32U },
  { RISCV::F1_D, 33U },
  { RISCV::F2_D, 34U },
  { RISCV::F3_D, 35U },
  { RISCV::F4_D, 36U },
  { RISCV::F5_D, 37U },
  { RISCV::F6_D, 38U },
  { RISCV::F7_D, 39U },
  { RISCV::F8_D, 40U },
  { RISCV::F9_D, 41U },
  { RISCV::F10_D, 42U },
  { RISCV::F11_D, 43U },
  { RISCV::F12_D, 44U },
  { RISCV::F13_D, 45U },
  { RISCV::F14_D, 46U },
  { RISCV::F15_D, 47U },
  { RISCV::F16_D, 48U },
  { RISCV::F17_D, 49U },
  { RISCV::F18_D, 50U },
  { RISCV::F19_D, 51U },
  { RISCV::F20_D, 52U },
  { RISCV::F21_D, 53U },
  { RISCV::F22_D, 54U },
  { RISCV::F23_D, 55U },
  { RISCV::F24_D, 56U },
  { RISCV::F25_D, 57U },
  { RISCV::F26_D, 58U },
  { RISCV::F27_D, 59U },
  { RISCV::F28_D, 60U },
  { RISCV::F29_D, 61U },
  { RISCV::F30_D, 62U },
  { RISCV::F31_D, 63U },
  { RISCV::F0_F, 32U },
  { RISCV::F1_F, 33U },
  { RISCV::F2_F, 34U },
  { RISCV::F3_F, 35U },
  { RISCV::F4_F, 36U },
  { RISCV::F5_F, 37U },
  { RISCV::F6_F, 38U },
  { RISCV::F7_F, 39U },
  { RISCV::F8_F, 40U },
  { RISCV::F9_F, 41U },
  { RISCV::F10_F, 42U },
  { RISCV::F11_F, 43U },
  { RISCV::F12_F, 44U },
  { RISCV::F13_F, 45U },
  { RISCV::F14_F, 46U },
  { RISCV::F15_F, 47U },
  { RISCV::F16_F, 48U },
  { RISCV::F17_F, 49U },
  { RISCV::F18_F, 50U },
  { RISCV::F19_F, 51U },
  { RISCV::F20_F, 52U },
  { RISCV::F21_F, 53U },
  { RISCV::F22_F, 54U },
  { RISCV::F23_F, 55U },
  { RISCV::F24_F, 56U },
  { RISCV::F25_F, 57U },
  { RISCV::F26_F, 58U },
  { RISCV::F27_F, 59U },
  { RISCV::F28_F, 60U },
  { RISCV::F29_F, 61U },
  { RISCV::F30_F, 62U },
  { RISCV::F31_F, 63U },
  { RISCV::F0_H, 32U },
  { RISCV::F1_H, 33U },
  { RISCV::F2_H, 34U },
  { RISCV::F3_H, 35U },
  { RISCV::F4_H, 36U },
  { RISCV::F5_H, 37U },
  { RISCV::F6_H, 38U },
  { RISCV::F7_H, 39U },
  { RISCV::F8_H, 40U },
  { RISCV::F9_H, 41U },
  { RISCV::F10_H, 42U },
  { RISCV::F11_H, 43U },
  { RISCV::F12_H, 44U },
  { RISCV::F13_H, 45U },
  { RISCV::F14_H, 46U },
  { RISCV::F15_H, 47U },
  { RISCV::F16_H, 48U },
  { RISCV::F17_H, 49U },
  { RISCV::F18_H, 50U },
  { RISCV::F19_H, 51U },
  { RISCV::F20_H, 52U },
  { RISCV::F21_H, 53U },
  { RISCV::F22_H, 54U },
  { RISCV::F23_H, 55U },
  { RISCV::F24_H, 56U },
  { RISCV::F25_H, 57U },
  { RISCV::F26_H, 58U },
  { RISCV::F27_H, 59U },
  { RISCV::F28_H, 60U },
  { RISCV::F29_H, 61U },
  { RISCV::F30_H, 62U },
  { RISCV::F31_H, 63U },
  { RISCV::V0M2, 96U },
  { RISCV::V0M4, 96U },
  { RISCV::V0M8, 96U },
  { RISCV::V2M2, 98U },
  { RISCV::V4M2, 100U },
  { RISCV::V4M4, 100U },
  { RISCV::V6M2, 102U },
  { RISCV::V8M2, 104U },
  { RISCV::V8M4, 104U },
  { RISCV::V8M8, 104U },
  { RISCV::V10M2, 106U },
  { RISCV::V12M2, 108U },
  { RISCV::V12M4, 108U },
  { RISCV::V14M2, 110U },
  { RISCV::V16M2, 112U },
  { RISCV::V16M4, 112U },
  { RISCV::V16M8, 112U },
  { RISCV::V18M2, 114U },
  { RISCV::V20M2, 116U },
  { RISCV::V20M4, 116U },
  { RISCV::V22M2, 118U },
  { RISCV::V24M2, 120U },
  { RISCV::V24M4, 120U },
  { RISCV::V24M8, 120U },
  { RISCV::V26M2, 122U },
  { RISCV::V28M2, 124U },
  { RISCV::V28M4, 124U },
  { RISCV::V30M2, 126U },
};
extern const unsigned RISCVDwarfFlavour0L2DwarfSize = std::size(RISCVDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[] = {
  { RISCV::VLENB, 7202U },
  { RISCV::V0, 96U },
  { RISCV::V1, 97U },
  { RISCV::V2, 98U },
  { RISCV::V3, 99U },
  { RISCV::V4, 100U },
  { RISCV::V5, 101U },
  { RISCV::V6, 102U },
  { RISCV::V7, 103U },
  { RISCV::V8, 104U },
  { RISCV::V9, 105U },
  { RISCV::V10, 106U },
  { RISCV::V11, 107U },
  { RISCV::V12, 108U },
  { RISCV::V13, 109U },
  { RISCV::V14, 110U },
  { RISCV::V15, 111U },
  { RISCV::V16, 112U },
  { RISCV::V17, 113U },
  { RISCV::V18, 114U },
  { RISCV::V19, 115U },
  { RISCV::V20, 116U },
  { RISCV::V21, 117U },
  { RISCV::V22, 118U },
  { RISCV::V23, 119U },
  { RISCV::V24, 120U },
  { RISCV::V25, 121U },
  { RISCV::V26, 122U },
  { RISCV::V27, 123U },
  { RISCV::V28, 124U },
  { RISCV::V29, 125U },
  { RISCV::V30, 126U },
  { RISCV::V31, 127U },
  { RISCV::X0, 0U },
  { RISCV::X1, 1U },
  { RISCV::X2, 2U },
  { RISCV::X3, 3U },
  { RISCV::X4, 4U },
  { RISCV::X5, 5U },
  { RISCV::X6, 6U },
  { RISCV::X7, 7U },
  { RISCV::X8, 8U },
  { RISCV::X9, 9U },
  { RISCV::X10, 10U },
  { RISCV::X11, 11U },
  { RISCV::X12, 12U },
  { RISCV::X13, 13U },
  { RISCV::X14, 14U },
  { RISCV::X15, 15U },
  { RISCV::X16, 16U },
  { RISCV::X17, 17U },
  { RISCV::X18, 18U },
  { RISCV::X19, 19U },
  { RISCV::X20, 20U },
  { RISCV::X21, 21U },
  { RISCV::X22, 22U },
  { RISCV::X23, 23U },
  { RISCV::X24, 24U },
  { RISCV::X25, 25U },
  { RISCV::X26, 26U },
  { RISCV::X27, 27U },
  { RISCV::X28, 28U },
  { RISCV::X29, 29U },
  { RISCV::X30, 30U },
  { RISCV::X31, 31U },
  { RISCV::F0_D, 32U },
  { RISCV::F1_D, 33U },
  { RISCV::F2_D, 34U },
  { RISCV::F3_D, 35U },
  { RISCV::F4_D, 36U },
  { RISCV::F5_D, 37U },
  { RISCV::F6_D, 38U },
  { RISCV::F7_D, 39U },
  { RISCV::F8_D, 40U },
  { RISCV::F9_D, 41U },
  { RISCV::F10_D, 42U },
  { RISCV::F11_D, 43U },
  { RISCV::F12_D, 44U },
  { RISCV::F13_D, 45U },
  { RISCV::F14_D, 46U },
  { RISCV::F15_D, 47U },
  { RISCV::F16_D, 48U },
  { RISCV::F17_D, 49U },
  { RISCV::F18_D, 50U },
  { RISCV::F19_D, 51U },
  { RISCV::F20_D, 52U },
  { RISCV::F21_D, 53U },
  { RISCV::F22_D, 54U },
  { RISCV::F23_D, 55U },
  { RISCV::F24_D, 56U },
  { RISCV::F25_D, 57U },
  { RISCV::F26_D, 58U },
  { RISCV::F27_D, 59U },
  { RISCV::F28_D, 60U },
  { RISCV::F29_D, 61U },
  { RISCV::F30_D, 62U },
  { RISCV::F31_D, 63U },
  { RISCV::F0_F, 32U },
  { RISCV::F1_F, 33U },
  { RISCV::F2_F, 34U },
  { RISCV::F3_F, 35U },
  { RISCV::F4_F, 36U },
  { RISCV::F5_F, 37U },
  { RISCV::F6_F, 38U },
  { RISCV::F7_F, 39U },
  { RISCV::F8_F, 40U },
  { RISCV::F9_F, 41U },
  { RISCV::F10_F, 42U },
  { RISCV::F11_F, 43U },
  { RISCV::F12_F, 44U },
  { RISCV::F13_F, 45U },
  { RISCV::F14_F, 46U },
  { RISCV::F15_F, 47U },
  { RISCV::F16_F, 48U },
  { RISCV::F17_F, 49U },
  { RISCV::F18_F, 50U },
  { RISCV::F19_F, 51U },
  { RISCV::F20_F, 52U },
  { RISCV::F21_F, 53U },
  { RISCV::F22_F, 54U },
  { RISCV::F23_F, 55U },
  { RISCV::F24_F, 56U },
  { RISCV::F25_F, 57U },
  { RISCV::F26_F, 58U },
  { RISCV::F27_F, 59U },
  { RISCV::F28_F, 60U },
  { RISCV::F29_F, 61U },
  { RISCV::F30_F, 62U },
  { RISCV::F31_F, 63U },
  { RISCV::F0_H, 32U },
  { RISCV::F1_H, 33U },
  { RISCV::F2_H, 34U },
  { RISCV::F3_H, 35U },
  { RISCV::F4_H, 36U },
  { RISCV::F5_H, 37U },
  { RISCV::F6_H, 38U },
  { RISCV::F7_H, 39U },
  { RISCV::F8_H, 40U },
  { RISCV::F9_H, 41U },
  { RISCV::F10_H, 42U },
  { RISCV::F11_H, 43U },
  { RISCV::F12_H, 44U },
  { RISCV::F13_H, 45U },
  { RISCV::F14_H, 46U },
  { RISCV::F15_H, 47U },
  { RISCV::F16_H, 48U },
  { RISCV::F17_H, 49U },
  { RISCV::F18_H, 50U },
  { RISCV::F19_H, 51U },
  { RISCV::F20_H, 52U },
  { RISCV::F21_H, 53U },
  { RISCV::F22_H, 54U },
  { RISCV::F23_H, 55U },
  { RISCV::F24_H, 56U },
  { RISCV::F25_H, 57U },
  { RISCV::F26_H, 58U },
  { RISCV::F27_H, 59U },
  { RISCV::F28_H, 60U },
  { RISCV::F29_H, 61U },
  { RISCV::F30_H, 62U },
  { RISCV::F31_H, 63U },
  { RISCV::V0M2, 96U },
  { RISCV::V0M4, 96U },
  { RISCV::V0M8, 96U },
  { RISCV::V2M2, 98U },
  { RISCV::V4M2, 100U },
  { RISCV::V4M4, 100U },
  { RISCV::V6M2, 102U },
  { RISCV::V8M2, 104U },
  { RISCV::V8M4, 104U },
  { RISCV::V8M8, 104U },
  { RISCV::V10M2, 106U },
  { RISCV::V12M2, 108U },
  { RISCV::V12M4, 108U },
  { RISCV::V14M2, 110U },
  { RISCV::V16M2, 112U },
  { RISCV::V16M4, 112U },
  { RISCV::V16M8, 112U },
  { RISCV::V18M2, 114U },
  { RISCV::V20M2, 116U },
  { RISCV::V20M4, 116U },
  { RISCV::V22M2, 118U },
  { RISCV::V24M2, 120U },
  { RISCV::V24M4, 120U },
  { RISCV::V24M8, 120U },
  { RISCV::V26M2, 122U },
  { RISCV::V28M2, 124U },
  { RISCV::V28M4, 124U },
  { RISCV::V30M2, 126U },
};
extern const unsigned RISCVEHFlavour0L2DwarfSize = std::size(RISCVEHFlavour0L2Dwarf);

extern const uint16_t RISCVRegEncodingTable[] = {
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  0,
  0,
  0,
  2,
  4,
  4,
  6,
  8,
  8,
  8,
  10,
  12,
  12,
  14,
  16,
  16,
  16,
  18,
  20,
  20,
  22,
  24,
  24,
  24,
  26,
  28,
  28,
  30,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  0,
  4,
  8,
  12,
  16,
  20,
  24,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  0,
};
static inline void InitRISCVMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(RISCVRegDesc, 459, RA, PC, RISCVMCRegisterClasses, 81, RISCVRegUnitRoots, 105, RISCVRegDiffLists, RISCVLaneMaskLists, RISCVRegStrings, RISCVRegClassStrings, RISCVSubRegIdxLists, 53,
RISCVSubRegIdxRanges, RISCVRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(RISCVDwarfFlavour0L2Dwarf, RISCVDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(RISCVEHFlavour0L2Dwarf, RISCVEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class RISCVFrameLowering;

struct RISCVGenRegisterInfo : public TargetRegisterInfo {
  explicit RISCVGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const RISCVFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace RISCV { // Register classes
  extern const TargetRegisterClass FPR16RegClass;
  extern const TargetRegisterClass GPRAllRegClass;
  extern const TargetRegisterClass FPR32RegClass;
  extern const TargetRegisterClass GPRRegClass;
  extern const TargetRegisterClass GPRF16RegClass;
  extern const TargetRegisterClass GPRF32RegClass;
  extern const TargetRegisterClass GPRNoX0RegClass;
  extern const TargetRegisterClass GPRNoX0X2RegClass;
  extern const TargetRegisterClass GPRJALRRegClass;
  extern const TargetRegisterClass GPRTCRegClass;
  extern const TargetRegisterClass FPR32CRegClass;
  extern const TargetRegisterClass GPRCRegClass;
  extern const TargetRegisterClass SR07RegClass;
  extern const TargetRegisterClass GPRC_and_GPRTCRegClass;
  extern const TargetRegisterClass VCSRRegClass;
  extern const TargetRegisterClass GPRC_and_SR07RegClass;
  extern const TargetRegisterClass GPRX1X5RegClass;
  extern const TargetRegisterClass GPRX0RegClass;
  extern const TargetRegisterClass GPRX1RegClass;
  extern const TargetRegisterClass GPRX5RegClass;
  extern const TargetRegisterClass SPRegClass;
  extern const TargetRegisterClass FPR64RegClass;
  extern const TargetRegisterClass VMRegClass;
  extern const TargetRegisterClass VRRegClass;
  extern const TargetRegisterClass VRNoV0RegClass;
  extern const TargetRegisterClass GPRPairRegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRJALRRegClass;
  extern const TargetRegisterClass FPR64CRegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRTCRegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRCRegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_SR07RegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRX0RegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_SPRegClass;
  extern const TargetRegisterClass GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClass;
  extern const TargetRegisterClass VMV0RegClass;
  extern const TargetRegisterClass VRN2M1RegClass;
  extern const TargetRegisterClass VRN2M1NoV0RegClass;
  extern const TargetRegisterClass VRM2RegClass;
  extern const TargetRegisterClass VRM2NoV0RegClass;
  extern const TargetRegisterClass VRM2_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN2M1_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN3M1RegClass;
  extern const TargetRegisterClass VRN3M1NoV0RegClass;
  extern const TargetRegisterClass VRN3M1_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN4M1RegClass;
  extern const TargetRegisterClass VRN4M1NoV0RegClass;
  extern const TargetRegisterClass VRN2M2RegClass;
  extern const TargetRegisterClass VRN2M2NoV0RegClass;
  extern const TargetRegisterClass VRM4RegClass;
  extern const TargetRegisterClass VRM4NoV0RegClass;
  extern const TargetRegisterClass VRM4_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN2M2_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN4M1_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN5M1RegClass;
  extern const TargetRegisterClass VRN5M1NoV0RegClass;
  extern const TargetRegisterClass VRN5M1_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN6M1RegClass;
  extern const TargetRegisterClass VRN6M1NoV0RegClass;
  extern const TargetRegisterClass VRN3M2RegClass;
  extern const TargetRegisterClass VRN3M2NoV0RegClass;
  extern const TargetRegisterClass VRN3M2_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN6M1_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN7M1RegClass;
  extern const TargetRegisterClass VRN7M1NoV0RegClass;
  extern const TargetRegisterClass VRN7M1_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN8M1RegClass;
  extern const TargetRegisterClass VRN8M1NoV0RegClass;
  extern const TargetRegisterClass VRN4M2RegClass;
  extern const TargetRegisterClass VRN4M2NoV0RegClass;
  extern const TargetRegisterClass VRN2M4RegClass;
  extern const TargetRegisterClass VRN2M4NoV0RegClass;
  extern const TargetRegisterClass VRM8RegClass;
  extern const TargetRegisterClass VRM8NoV0RegClass;
  extern const TargetRegisterClass VRM8_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN2M4_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN4M2_with_sub_vrm1_0_in_VMV0RegClass;
  extern const TargetRegisterClass VRN8M1_with_sub_vrm1_0_in_VMV0RegClass;
} // end namespace RISCV

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass RISCVMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i32, MVT::i32, MVT::Other,
  /* 3 */ MVT::i64, MVT::f64, MVT::i32, MVT::Other,
  /* 7 */ MVT::i64, MVT::Other,
  /* 9 */ MVT::f16, MVT::bf16, MVT::Other,
  /* 12 */ MVT::f16, MVT::Other,
  /* 14 */ MVT::f32, MVT::Other,
  /* 16 */ MVT::f64, MVT::Other,
  /* 18 */ MVT::nxv8i8, MVT::nxv4i16, MVT::nxv2i32, MVT::nxv1i64, MVT::nxv4bf16, MVT::nxv4f16, MVT::nxv2f32, MVT::nxv1f64, MVT::nxv4i8, MVT::nxv2i8, MVT::nxv1i8, MVT::nxv2i16, MVT::nxv1i16, MVT::nxv1i32, MVT::nxv1f16, MVT::nxv2f16, MVT::nxv1bf16, MVT::nxv2bf16, MVT::nxv1f32, MVT::nxv64i1, MVT::nxv32i1, MVT::nxv16i1, MVT::nxv8i1, MVT::nxv4i1, MVT::nxv2i1, MVT::nxv1i1, MVT::Other,
  /* 45 */ MVT::nxv16i8, MVT::nxv8i16, MVT::nxv4i32, MVT::nxv2i64, MVT::nxv8f16, MVT::nxv8bf16, MVT::nxv4f32, MVT::nxv2f64, MVT::Other,
  /* 54 */ MVT::nxv32i8, MVT::nxv16i16, MVT::nxv8i32, MVT::nxv4i64, MVT::nxv16f16, MVT::nxv16bf16, MVT::nxv8f32, MVT::nxv4f64, MVT::Other,
  /* 63 */ MVT::nxv64i8, MVT::nxv32i16, MVT::nxv16i32, MVT::nxv8i64, MVT::nxv32f16, MVT::nxv32bf16, MVT::nxv16f32, MVT::nxv8f64, MVT::Other,
  /* 72 */ MVT::Untyped, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_16", "sub_32", "sub_gpr_even", "sub_gpr_odd", "sub_vrm1_0", "sub_vrm1_1", "sub_vrm1_2", "sub_vrm1_3", "sub_vrm1_4", "sub_vrm1_5", "sub_vrm1_6", "sub_vrm1_7", "sub_vrm2_0", "sub_vrm2_1", "sub_vrm2_2", "sub_vrm2_3", "sub_vrm4_0", "sub_vrm4_1", "sub_vrm1_0_sub_vrm1_1", "sub_vrm1_0_sub_vrm1_1_sub_vrm1_2", "sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3", "sub_vrm1_1_sub_vrm1_2", "sub_vrm1_1_sub_vrm1_2_sub_vrm1_3", "sub_vrm1_2_sub_vrm1_3", "sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4", "sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5", "sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6", "sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7", "sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4", "sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5", "sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6", "sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7", "sub_vrm1_2_sub_vrm1_3_sub_vrm1_4", "sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5", "sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6", "sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7", "sub_vrm1_3_sub_vrm1_4", "sub_vrm1_3_sub_vrm1_4_sub_vrm1_5", "sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6", "sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7", "sub_vrm1_4_sub_vrm1_5", "sub_vrm1_4_sub_vrm1_5_sub_vrm1_6", "sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7", "sub_vrm1_5_sub_vrm1_6", "sub_vrm1_5_sub_vrm1_6_sub_vrm1_7", "sub_vrm1_6_sub_vrm1_7", "sub_vrm2_0_sub_vrm2_1", "sub_vrm2_0_sub_vrm2_1_sub_vrm2_2", "sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3", "sub_vrm2_1_sub_vrm2_2", "sub_vrm2_1_sub_vrm2_2_sub_vrm2_3", "sub_vrm2_2_sub_vrm2_3", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_16
  LaneBitmask(0x0000000000000001), // sub_32
  LaneBitmask(0x0000000000000002), // sub_gpr_even
  LaneBitmask(0x0000000000000004), // sub_gpr_odd
  LaneBitmask(0x0000000000000008), // sub_vrm1_0
  LaneBitmask(0x0000000000000010), // sub_vrm1_1
  LaneBitmask(0x0000000000000020), // sub_vrm1_2
  LaneBitmask(0x0000000000000040), // sub_vrm1_3
  LaneBitmask(0x0000000000000080), // sub_vrm1_4
  LaneBitmask(0x0000000000000100), // sub_vrm1_5
  LaneBitmask(0x0000000000000200), // sub_vrm1_6
  LaneBitmask(0x0000000000000400), // sub_vrm1_7
  LaneBitmask(0x0000000000000018), // sub_vrm2_0
  LaneBitmask(0x0000000000000060), // sub_vrm2_1
  LaneBitmask(0x0000000000000180), // sub_vrm2_2
  LaneBitmask(0x0000000000000600), // sub_vrm2_3
  LaneBitmask(0x0000000000000078), // sub_vrm4_0
  LaneBitmask(0x0000000000000780), // sub_vrm4_1
  LaneBitmask(0x0000000000000018), // sub_vrm1_0_sub_vrm1_1
  LaneBitmask(0x0000000000000038), // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
  LaneBitmask(0x0000000000000078), // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  LaneBitmask(0x0000000000000030), // sub_vrm1_1_sub_vrm1_2
  LaneBitmask(0x0000000000000070), // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  LaneBitmask(0x0000000000000060), // sub_vrm1_2_sub_vrm1_3
  LaneBitmask(0x00000000000000F8), // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  LaneBitmask(0x00000000000001F8), // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  LaneBitmask(0x00000000000003F8), // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  LaneBitmask(0x00000000000007F8), // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x00000000000000F0), // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  LaneBitmask(0x00000000000001F0), // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  LaneBitmask(0x00000000000003F0), // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  LaneBitmask(0x00000000000007F0), // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x00000000000000E0), // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  LaneBitmask(0x00000000000001E0), // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  LaneBitmask(0x00000000000003E0), // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  LaneBitmask(0x00000000000007E0), // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x00000000000000C0), // sub_vrm1_3_sub_vrm1_4
  LaneBitmask(0x00000000000001C0), // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  LaneBitmask(0x00000000000003C0), // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  LaneBitmask(0x00000000000007C0), // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x0000000000000180), // sub_vrm1_4_sub_vrm1_5
  LaneBitmask(0x0000000000000380), // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  LaneBitmask(0x0000000000000780), // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x0000000000000300), // sub_vrm1_5_sub_vrm1_6
  LaneBitmask(0x0000000000000700), // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x0000000000000600), // sub_vrm1_6_sub_vrm1_7
  LaneBitmask(0x0000000000000078), // sub_vrm2_0_sub_vrm2_1
  LaneBitmask(0x00000000000001F8), // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
  LaneBitmask(0x00000000000007F8), // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
  LaneBitmask(0x00000000000001E0), // sub_vrm2_1_sub_vrm2_2
  LaneBitmask(0x00000000000007E0), // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
  LaneBitmask(0x0000000000000780), // sub_vrm2_2_sub_vrm2_3
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 16, 16, 16, /*VTLists+*/9 },    // FPR16
  { 32, 32, 32, /*VTLists+*/0 },    // GPRAll
  { 32, 32, 32, /*VTLists+*/14 },    // FPR32
  { 32, 32, 32, /*VTLists+*/0 },    // GPR
  { 32, 32, 32, /*VTLists+*/12 },    // GPRF16
  { 32, 32, 32, /*VTLists+*/14 },    // GPRF32
  { 32, 32, 32, /*VTLists+*/0 },    // GPRNoX0
  { 32, 32, 32, /*VTLists+*/0 },    // GPRNoX0X2
  { 32, 32, 32, /*VTLists+*/0 },    // GPRJALR
  { 32, 32, 32, /*VTLists+*/0 },    // GPRTC
  { 32, 32, 32, /*VTLists+*/14 },    // FPR32C
  { 32, 32, 32, /*VTLists+*/0 },    // GPRC
  { 32, 32, 32, /*VTLists+*/0 },    // SR07
  { 32, 32, 32, /*VTLists+*/0 },    // GPRC_and_GPRTC
  { 32, 32, 32, /*VTLists+*/1 },    // VCSR
  { 32, 32, 32, /*VTLists+*/0 },    // GPRC_and_SR07
  { 32, 32, 32, /*VTLists+*/0 },    // GPRX1X5
  { 32, 32, 32, /*VTLists+*/0 },    // GPRX0
  { 32, 32, 32, /*VTLists+*/0 },    // GPRX1
  { 32, 32, 32, /*VTLists+*/0 },    // GPRX5
  { 32, 32, 32, /*VTLists+*/0 },    // SP
  { 64, 64, 64, /*VTLists+*/16 },    // FPR64
  { 64, 64, 64, /*VTLists+*/37 },    // VM
  { 64, 64, 64, /*VTLists+*/18 },    // VR
  { 64, 64, 64, /*VTLists+*/18 },    // VRNoV0
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRNoX0
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRNoX0X2
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRJALR
  { 64, 64, 64, /*VTLists+*/16 },    // FPR64C
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRTC
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRC
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_SR07
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRX0
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_SP
  { 64, 64, 64, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_odd_in_GPRX1X5
  { 64, 64, 64, /*VTLists+*/37 },    // VMV0
  { 128, 128, 64, /*VTLists+*/72 },    // VRN2M1
  { 128, 128, 64, /*VTLists+*/72 },    // VRN2M1NoV0
  { 128, 128, 64, /*VTLists+*/45 },    // VRM2
  { 128, 128, 64, /*VTLists+*/45 },    // VRM2NoV0
  { 128, 128, 64, /*VTLists+*/45 },    // VRM2_with_sub_vrm1_0_in_VMV0
  { 128, 128, 64, /*VTLists+*/72 },    // VRN2M1_with_sub_vrm1_0_in_VMV0
  { 192, 192, 64, /*VTLists+*/72 },    // VRN3M1
  { 192, 192, 64, /*VTLists+*/72 },    // VRN3M1NoV0
  { 192, 192, 64, /*VTLists+*/72 },    // VRN3M1_with_sub_vrm1_0_in_VMV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN4M1
  { 256, 256, 64, /*VTLists+*/72 },    // VRN4M1NoV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN2M2
  { 256, 256, 64, /*VTLists+*/72 },    // VRN2M2NoV0
  { 256, 256, 64, /*VTLists+*/54 },    // VRM4
  { 256, 256, 64, /*VTLists+*/54 },    // VRM4NoV0
  { 256, 256, 64, /*VTLists+*/54 },    // VRM4_with_sub_vrm1_0_in_VMV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN2M2_with_sub_vrm1_0_in_VMV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN4M1_with_sub_vrm1_0_in_VMV0
  { 320, 320, 64, /*VTLists+*/72 },    // VRN5M1
  { 320, 320, 64, /*VTLists+*/72 },    // VRN5M1NoV0
  { 320, 320, 64, /*VTLists+*/72 },    // VRN5M1_with_sub_vrm1_0_in_VMV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN6M1
  { 384, 384, 64, /*VTLists+*/72 },    // VRN6M1NoV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN3M2
  { 384, 384, 64, /*VTLists+*/72 },    // VRN3M2NoV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN3M2_with_sub_vrm1_0_in_VMV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN6M1_with_sub_vrm1_0_in_VMV0
  { 448, 448, 64, /*VTLists+*/72 },    // VRN7M1
  { 448, 448, 64, /*VTLists+*/72 },    // VRN7M1NoV0
  { 448, 448, 64, /*VTLists+*/72 },    // VRN7M1_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN8M1
  { 512, 512, 64, /*VTLists+*/72 },    // VRN8M1NoV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN4M2
  { 512, 512, 64, /*VTLists+*/72 },    // VRN4M2NoV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN2M4
  { 512, 512, 64, /*VTLists+*/72 },    // VRN2M4NoV0
  { 512, 512, 64, /*VTLists+*/63 },    // VRM8
  { 512, 512, 64, /*VTLists+*/63 },    // VRM8NoV0
  { 512, 512, 64, /*VTLists+*/63 },    // VRM8_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN2M4_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN4M2_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN8M1_with_sub_vrm1_0_in_VMV0
  // Mode = 1 (RV64)
  { 16, 16, 16, /*VTLists+*/9 },    // FPR16
  { 64, 64, 64, /*VTLists+*/3 },    // GPRAll
  { 32, 32, 32, /*VTLists+*/14 },    // FPR32
  { 64, 64, 64, /*VTLists+*/3 },    // GPR
  { 64, 64, 64, /*VTLists+*/12 },    // GPRF16
  { 64, 64, 64, /*VTLists+*/14 },    // GPRF32
  { 64, 64, 64, /*VTLists+*/3 },    // GPRNoX0
  { 64, 64, 64, /*VTLists+*/3 },    // GPRNoX0X2
  { 64, 64, 64, /*VTLists+*/3 },    // GPRJALR
  { 64, 64, 64, /*VTLists+*/3 },    // GPRTC
  { 32, 32, 32, /*VTLists+*/14 },    // FPR32C
  { 64, 64, 64, /*VTLists+*/3 },    // GPRC
  { 64, 64, 64, /*VTLists+*/3 },    // SR07
  { 64, 64, 64, /*VTLists+*/3 },    // GPRC_and_GPRTC
  { 64, 64, 64, /*VTLists+*/7 },    // VCSR
  { 64, 64, 64, /*VTLists+*/3 },    // GPRC_and_SR07
  { 64, 64, 64, /*VTLists+*/3 },    // GPRX1X5
  { 64, 64, 64, /*VTLists+*/3 },    // GPRX0
  { 64, 64, 64, /*VTLists+*/3 },    // GPRX1
  { 64, 64, 64, /*VTLists+*/3 },    // GPRX5
  { 64, 64, 64, /*VTLists+*/3 },    // SP
  { 64, 64, 64, /*VTLists+*/16 },    // FPR64
  { 64, 64, 64, /*VTLists+*/37 },    // VM
  { 64, 64, 64, /*VTLists+*/18 },    // VR
  { 64, 64, 64, /*VTLists+*/18 },    // VRNoV0
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRNoX0
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRNoX0X2
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRJALR
  { 64, 64, 64, /*VTLists+*/16 },    // FPR64C
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRTC
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRC
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_SR07
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_GPRX0
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_even_in_SP
  { 128, 128, 128, /*VTLists+*/16 },    // GPRPair_with_sub_gpr_odd_in_GPRX1X5
  { 64, 64, 64, /*VTLists+*/37 },    // VMV0
  { 128, 128, 64, /*VTLists+*/72 },    // VRN2M1
  { 128, 128, 64, /*VTLists+*/72 },    // VRN2M1NoV0
  { 128, 128, 64, /*VTLists+*/45 },    // VRM2
  { 128, 128, 64, /*VTLists+*/45 },    // VRM2NoV0
  { 128, 128, 64, /*VTLists+*/45 },    // VRM2_with_sub_vrm1_0_in_VMV0
  { 128, 128, 64, /*VTLists+*/72 },    // VRN2M1_with_sub_vrm1_0_in_VMV0
  { 192, 192, 64, /*VTLists+*/72 },    // VRN3M1
  { 192, 192, 64, /*VTLists+*/72 },    // VRN3M1NoV0
  { 192, 192, 64, /*VTLists+*/72 },    // VRN3M1_with_sub_vrm1_0_in_VMV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN4M1
  { 256, 256, 64, /*VTLists+*/72 },    // VRN4M1NoV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN2M2
  { 256, 256, 64, /*VTLists+*/72 },    // VRN2M2NoV0
  { 256, 256, 64, /*VTLists+*/54 },    // VRM4
  { 256, 256, 64, /*VTLists+*/54 },    // VRM4NoV0
  { 256, 256, 64, /*VTLists+*/54 },    // VRM4_with_sub_vrm1_0_in_VMV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN2M2_with_sub_vrm1_0_in_VMV0
  { 256, 256, 64, /*VTLists+*/72 },    // VRN4M1_with_sub_vrm1_0_in_VMV0
  { 320, 320, 64, /*VTLists+*/72 },    // VRN5M1
  { 320, 320, 64, /*VTLists+*/72 },    // VRN5M1NoV0
  { 320, 320, 64, /*VTLists+*/72 },    // VRN5M1_with_sub_vrm1_0_in_VMV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN6M1
  { 384, 384, 64, /*VTLists+*/72 },    // VRN6M1NoV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN3M2
  { 384, 384, 64, /*VTLists+*/72 },    // VRN3M2NoV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN3M2_with_sub_vrm1_0_in_VMV0
  { 384, 384, 64, /*VTLists+*/72 },    // VRN6M1_with_sub_vrm1_0_in_VMV0
  { 448, 448, 64, /*VTLists+*/72 },    // VRN7M1
  { 448, 448, 64, /*VTLists+*/72 },    // VRN7M1NoV0
  { 448, 448, 64, /*VTLists+*/72 },    // VRN7M1_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN8M1
  { 512, 512, 64, /*VTLists+*/72 },    // VRN8M1NoV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN4M2
  { 512, 512, 64, /*VTLists+*/72 },    // VRN4M2NoV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN2M4
  { 512, 512, 64, /*VTLists+*/72 },    // VRN2M4NoV0
  { 512, 512, 64, /*VTLists+*/63 },    // VRM8
  { 512, 512, 64, /*VTLists+*/63 },    // VRM8NoV0
  { 512, 512, 64, /*VTLists+*/63 },    // VRM8_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN2M4_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN4M2_with_sub_vrm1_0_in_VMV0
  { 512, 512, 64, /*VTLists+*/72 },    // VRN8M1_with_sub_vrm1_0_in_VMV0
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t FPR16SubClassMask[] = {
  0x00000001, 0x00000000, 0x00000000, 
  0x20200404, 0x00000000, 0x00000000, // sub_16
};

static const uint32_t GPRAllSubClassMask[] = {
  0x001fbbfa, 0x00000000, 0x00000000, 
  0xde000000, 0x0000003f, 0x00000000, // sub_gpr_even
  0xde000000, 0x0000003f, 0x00000000, // sub_gpr_odd
};

static const uint32_t FPR32SubClassMask[] = {
  0x00000404, 0x00000000, 0x00000000, 
  0x20200000, 0x00000000, 0x00000000, // sub_32
};

static const uint32_t GPRSubClassMask[] = {
  0x001fbbf8, 0x00000000, 0x00000000, 
  0xde000000, 0x0000003f, 0x00000000, // sub_gpr_even
  0xdc000000, 0x00000037, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRF16SubClassMask[] = {
  0x001fbbf8, 0x00000000, 0x00000000, 
  0xde000000, 0x0000003f, 0x00000000, // sub_gpr_even
  0xdc000000, 0x00000037, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRF32SubClassMask[] = {
  0x001fbbf8, 0x00000000, 0x00000000, 
  0xde000000, 0x0000003f, 0x00000000, // sub_gpr_even
  0xdc000000, 0x00000037, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRNoX0SubClassMask[] = {
  0x001dbbc0, 0x00000000, 0x00000000, 
  0xdc000000, 0x00000037, 0x00000000, // sub_gpr_even
  0xdc000000, 0x00000037, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRNoX0X2SubClassMask[] = {
  0x000dbb80, 0x00000000, 0x00000000, 
  0xd8000000, 0x00000027, 0x00000000, // sub_gpr_even
  0xdc000000, 0x00000037, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRJALRSubClassMask[] = {
  0x0000bb00, 0x00000000, 0x00000000, 
  0xd0000000, 0x00000007, 0x00000000, // sub_gpr_even
  0xd0000000, 0x00000007, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRTCSubClassMask[] = {
  0x00002200, 0x00000000, 0x00000000, 
  0x40000000, 0x00000002, 0x00000000, // sub_gpr_even
  0x40000000, 0x00000002, 0x00000000, // sub_gpr_odd
};

static const uint32_t FPR32CSubClassMask[] = {
  0x00000400, 0x00000000, 0x00000000, 
  0x20000000, 0x00000000, 0x00000000, // sub_32
};

static const uint32_t GPRCSubClassMask[] = {
  0x0000a800, 0x00000000, 0x00000000, 
  0x80000000, 0x00000006, 0x00000000, // sub_gpr_even
  0x80000000, 0x00000006, 0x00000000, // sub_gpr_odd
};

static const uint32_t SR07SubClassMask[] = {
  0x00009000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000005, 0x00000000, // sub_gpr_even
  0x00000000, 0x00000005, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRC_and_GPRTCSubClassMask[] = {
  0x00002000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000002, 0x00000000, // sub_gpr_even
  0x00000000, 0x00000002, 0x00000000, // sub_gpr_odd
};

static const uint32_t VCSRSubClassMask[] = {
  0x00004000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRC_and_SR07SubClassMask[] = {
  0x00008000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000004, 0x00000000, // sub_gpr_even
  0x00000000, 0x00000004, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRX1X5SubClassMask[] = {
  0x000d0000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000020, 0x00000000, // sub_gpr_odd
};

static const uint32_t GPRX0SubClassMask[] = {
  0x00020000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000008, 0x00000000, // sub_gpr_even
};

static const uint32_t GPRX1SubClassMask[] = {
  0x00040000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRX5SubClassMask[] = {
  0x00080000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000020, 0x00000000, // sub_gpr_odd
};

static const uint32_t SPSubClassMask[] = {
  0x00100000, 0x00000000, 0x00000000, 
  0x00000000, 0x00000010, 0x00000000, // sub_gpr_even
};

static const uint32_t FPR64SubClassMask[] = {
  0x20200000, 0x00000000, 0x00000000, 
};

static const uint32_t VMSubClassMask[] = {
  0x01c00000, 0x00000040, 0x00000000, 
  0x00000000, 0xffffff80, 0x0001ffff, // sub_vrm1_0
  0x00000000, 0xffffff80, 0x0001ffff, // sub_vrm1_1
  0x00000000, 0xffffe000, 0x0001ffff, // sub_vrm1_2
  0x00000000, 0xffff0000, 0x0001ffff, // sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001ffff, // sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001ffff, // sub_vrm1_5
  0x00000000, 0x00000000, 0x0001fffc, // sub_vrm1_6
  0x00000000, 0x00000000, 0x0001ffe0, // sub_vrm1_7
};

static const uint32_t VRSubClassMask[] = {
  0x01c00000, 0x00000040, 0x00000000, 
  0x00000000, 0xffffff80, 0x0001ffff, // sub_vrm1_0
  0x00000000, 0xffffff80, 0x0001ffff, // sub_vrm1_1
  0x00000000, 0xffffe000, 0x0001ffff, // sub_vrm1_2
  0x00000000, 0xffff0000, 0x0001ffff, // sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001ffff, // sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001ffff, // sub_vrm1_5
  0x00000000, 0x00000000, 0x0001fffc, // sub_vrm1_6
  0x00000000, 0x00000000, 0x0001ffe0, // sub_vrm1_7
};

static const uint32_t VRNoV0SubClassMask[] = {
  0x01000000, 0x00000000, 0x00000000, 
  0x00000000, 0xa42a4500, 0x00001548, // sub_vrm1_0
  0x00000000, 0xffffff80, 0x0001ffff, // sub_vrm1_1
  0x00000000, 0xffffe000, 0x0001ffff, // sub_vrm1_2
  0x00000000, 0xffff0000, 0x0001ffff, // sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001ffff, // sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001ffff, // sub_vrm1_5
  0x00000000, 0x00000000, 0x0001fffc, // sub_vrm1_6
  0x00000000, 0x00000000, 0x0001ffe0, // sub_vrm1_7
};

static const uint32_t GPRPairSubClassMask[] = {
  0xde000000, 0x0000003f, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRNoX0SubClassMask[] = {
  0xdc000000, 0x00000037, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRNoX0X2SubClassMask[] = {
  0xd8000000, 0x00000027, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRJALRSubClassMask[] = {
  0xd0000000, 0x00000007, 0x00000000, 
};

static const uint32_t FPR64CSubClassMask[] = {
  0x20000000, 0x00000000, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRTCSubClassMask[] = {
  0x40000000, 0x00000002, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRCSubClassMask[] = {
  0x80000000, 0x00000006, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_SR07SubClassMask[] = {
  0x00000000, 0x00000005, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCSubClassMask[] = {
  0x00000000, 0x00000002, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRC_and_SR07SubClassMask[] = {
  0x00000000, 0x00000004, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_GPRX0SubClassMask[] = {
  0x00000000, 0x00000008, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_even_in_SPSubClassMask[] = {
  0x00000000, 0x00000010, 0x00000000, 
};

static const uint32_t GPRPair_with_sub_gpr_odd_in_GPRX1X5SubClassMask[] = {
  0x00000000, 0x00000020, 0x00000000, 
};

static const uint32_t VMV0SubClassMask[] = {
  0x00000000, 0x00000040, 0x00000000, 
  0x00000000, 0x09c09800, 0x0001e013, // sub_vrm1_0
};

static const uint32_t VRN2M1SubClassMask[] = {
  0x00000000, 0x00001180, 0x00000000, 
  0x00000000, 0xff8fe000, 0x0001c7ff, // sub_vrm1_0_sub_vrm1_1
  0x00000000, 0xff8fe000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2
  0x00000000, 0xff8f0000, 0x0001c7ff, // sub_vrm1_2_sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001c7ff, // sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN2M1NoV0SubClassMask[] = {
  0x00000000, 0x00000100, 0x00000000, 
  0x00000000, 0xa40a4000, 0x00000548, // sub_vrm1_0_sub_vrm1_1
  0x00000000, 0xff8fe000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2
  0x00000000, 0xff8f0000, 0x0001c7ff, // sub_vrm1_2_sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001c7ff, // sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRM2SubClassMask[] = {
  0x00000000, 0x00000e00, 0x00000000, 
  0x00000000, 0xc0fc0000, 0x0000ff81, // sub_vrm2_0
  0x00000000, 0xc0fc0000, 0x0000ff81, // sub_vrm2_1
  0x00000000, 0xc0000000, 0x0000ff81, // sub_vrm2_2
  0x00000000, 0x00000000, 0x0000ff80, // sub_vrm2_3
};

static const uint32_t VRM2NoV0SubClassMask[] = {
  0x00000000, 0x00000400, 0x00000000, 
  0x00000000, 0x80280000, 0x00001500, // sub_vrm2_0
  0x00000000, 0xc0fc0000, 0x0000ff81, // sub_vrm2_1
  0x00000000, 0xc0000000, 0x0000ff81, // sub_vrm2_2
  0x00000000, 0x00000000, 0x0000ff80, // sub_vrm2_3
};

static const uint32_t VRM2_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000800, 0x00000000, 
  0x00000000, 0x00c00000, 0x0000e001, // sub_vrm2_0
};

static const uint32_t VRN2M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00001000, 0x00000000, 
  0x00000000, 0x09808000, 0x0001c013, // sub_vrm1_0_sub_vrm1_1
};

static const uint32_t VRN3M1SubClassMask[] = {
  0x00000000, 0x0000e000, 0x00000000, 
  0x00000000, 0xff8f0000, 0x0001c7ff, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
  0x00000000, 0xff8f0000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001c7ff, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN3M1NoV0SubClassMask[] = {
  0x00000000, 0x00004000, 0x00000000, 
  0x00000000, 0xa40a0000, 0x00000548, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
  0x00000000, 0xff8f0000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001c7ff, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN3M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00008000, 0x00000000, 
  0x00000000, 0x09800000, 0x0001c013, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
};

static const uint32_t VRN4M1SubClassMask[] = {
  0x00000000, 0x01030000, 0x00000000, 
  0x00000000, 0xfe8c0000, 0x0001c7ff, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN4M1NoV0SubClassMask[] = {
  0x00000000, 0x00020000, 0x00000000, 
  0x00000000, 0xa4080000, 0x00000548, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
  0x00000000, 0xfe000000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN2M2SubClassMask[] = {
  0x00000000, 0x008c0000, 0x00000000, 
  0x00000000, 0xc0000000, 0x0000c781, // sub_vrm2_0_sub_vrm2_1
  0x00000000, 0xc0000000, 0x0000c781, // sub_vrm2_1_sub_vrm2_2
  0x00000000, 0x00000000, 0x0000c780, // sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRN2M2NoV0SubClassMask[] = {
  0x00000000, 0x00080000, 0x00000000, 
  0x00000000, 0x80000000, 0x00000500, // sub_vrm2_0_sub_vrm2_1
  0x00000000, 0xc0000000, 0x0000c781, // sub_vrm2_1_sub_vrm2_2
  0x00000000, 0x00000000, 0x0000c780, // sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRM4SubClassMask[] = {
  0x00000000, 0x00700000, 0x00000000, 
  0x00000000, 0x00000000, 0x00007e00, // sub_vrm4_0
  0x00000000, 0x00000000, 0x00007e00, // sub_vrm4_1
};

static const uint32_t VRM4NoV0SubClassMask[] = {
  0x00000000, 0x00200000, 0x00000000, 
  0x00000000, 0x00000000, 0x00001400, // sub_vrm4_0
  0x00000000, 0x00000000, 0x00007e00, // sub_vrm4_1
};

static const uint32_t VRM4_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00400000, 0x00000000, 
  0x00000000, 0x00000000, 0x00006000, // sub_vrm4_0
};

static const uint32_t VRN2M2_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00800000, 0x00000000, 
  0x00000000, 0x00000000, 0x0000c001, // sub_vrm2_0_sub_vrm2_1
};

static const uint32_t VRN4M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x01000000, 0x00000000, 
  0x00000000, 0x08800000, 0x0001c013, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
};

static const uint32_t VRN5M1SubClassMask[] = {
  0x00000000, 0x0e000000, 0x00000000, 
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN5M1NoV0SubClassMask[] = {
  0x00000000, 0x04000000, 0x00000000, 
  0x00000000, 0xa0000000, 0x00000548, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
  0x00000000, 0xf0000000, 0x0001c7ff, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN5M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x08000000, 0x00000000, 
  0x00000000, 0x00000000, 0x0001c013, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
};

static const uint32_t VRN6M1SubClassMask[] = {
  0x00000000, 0x30000000, 0x00000002, 
  0x00000000, 0xc0000000, 0x0001c7fd, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN6M1NoV0SubClassMask[] = {
  0x00000000, 0x20000000, 0x00000000, 
  0x00000000, 0x80000000, 0x00000548, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
  0x00000000, 0x00000000, 0x0001c7fc, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN3M2SubClassMask[] = {
  0x00000000, 0xc0000000, 0x00000001, 
  0x00000000, 0x00000000, 0x0000c780, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
  0x00000000, 0x00000000, 0x0000c780, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRN3M2NoV0SubClassMask[] = {
  0x00000000, 0x80000000, 0x00000000, 
  0x00000000, 0x00000000, 0x00000500, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
  0x00000000, 0x00000000, 0x0000c780, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRN3M2_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000001, 
  0x00000000, 0x00000000, 0x0000c000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
};

static const uint32_t VRN6M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000002, 
  0x00000000, 0x00000000, 0x0001c011, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
};

static const uint32_t VRN7M1SubClassMask[] = {
  0x00000000, 0x00000000, 0x0000001c, 
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN7M1NoV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000008, 
  0x00000000, 0x00000000, 0x00000540, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
  0x00000000, 0x00000000, 0x0001c7e0, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN7M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000010, 
  0x00000000, 0x00000000, 0x0001c000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
};

static const uint32_t VRN8M1SubClassMask[] = {
  0x00000000, 0x00000000, 0x00010060, 
  0x00000000, 0x00000000, 0x0000c780, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN8M1NoV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000040, 
  0x00000000, 0x00000000, 0x00000500, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint32_t VRN4M2SubClassMask[] = {
  0x00000000, 0x00000000, 0x00008180, 
  0x00000000, 0x00000000, 0x00004600, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRN4M2NoV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000100, 
  0x00000000, 0x00000000, 0x00000400, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRN2M4SubClassMask[] = {
  0x00000000, 0x00000000, 0x00004600, 
};

static const uint32_t VRN2M4NoV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00000400, 
};

static const uint32_t VRM8SubClassMask[] = {
  0x00000000, 0x00000000, 0x00003800, 
};

static const uint32_t VRM8NoV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00001000, 
};

static const uint32_t VRM8_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00002000, 
};

static const uint32_t VRN2M4_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00004000, 
};

static const uint32_t VRN4M2_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00008000, 
  0x00000000, 0x00000000, 0x00004000, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
};

static const uint32_t VRN8M1_with_sub_vrm1_0_in_VMV0SubClassMask[] = {
  0x00000000, 0x00000000, 0x00010000, 
  0x00000000, 0x00000000, 0x0000c000, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 0,
  /* 2 */ 2, 0,
  /* 4 */ 3, 0,
  /* 6 */ 3, 4, 0,
  /* 9 */ 5, 0,
  /* 11 */ 5, 6, 7, 8, 9, 10, 11, 12, 0,
  /* 20 */ 13, 0,
  /* 22 */ 13, 14, 15, 16, 0,
  /* 27 */ 17, 0,
  /* 29 */ 17, 18, 0,
  /* 32 */ 19, 0,
  /* 34 */ 20, 0,
  /* 36 */ 21, 0,
  /* 38 */ 25, 0,
  /* 40 */ 26, 0,
  /* 42 */ 27, 0,
  /* 44 */ 28, 0,
  /* 46 */ 27, 32, 0,
  /* 49 */ 26, 31, 36, 0,
  /* 53 */ 25, 30, 35, 40, 0,
  /* 58 */ 21, 29, 34, 39, 43, 0,
  /* 64 */ 20, 23, 33, 38, 42, 45, 0,
  /* 71 */ 19, 22, 24, 37, 41, 44, 46, 0,
  /* 79 */ 47, 0,
  /* 81 */ 48, 0,
  /* 83 */ 49, 0,
  /* 85 */ 48, 51, 0,
  /* 88 */ 47, 50, 52, 0,
};

static const TargetRegisterClass *const GPRSuperclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRF16Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRF32Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRNoX0Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRNoX0X2Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRJALRSuperclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRTCSuperclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRJALRRegClass,
  nullptr
};

static const TargetRegisterClass *const FPR32CSuperclasses[] = {
  &RISCV::FPR32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRCSuperclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRJALRRegClass,
  nullptr
};

static const TargetRegisterClass *const SR07Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRJALRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRC_and_GPRTCSuperclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRJALRRegClass,
  &RISCV::GPRTCRegClass,
  &RISCV::GPRCRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRC_and_SR07Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRJALRRegClass,
  &RISCV::GPRCRegClass,
  &RISCV::SR07RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRX1X5Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRX0Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRX1Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRX1X5RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRX5Superclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  &RISCV::GPRNoX0X2RegClass,
  &RISCV::GPRX1X5RegClass,
  nullptr
};

static const TargetRegisterClass *const SPSuperclasses[] = {
  &RISCV::GPRAllRegClass,
  &RISCV::GPRRegClass,
  &RISCV::GPRF16RegClass,
  &RISCV::GPRF32RegClass,
  &RISCV::GPRNoX0RegClass,
  nullptr
};

static const TargetRegisterClass *const VMSuperclasses[] = {
  &RISCV::VRRegClass,
  nullptr
};

static const TargetRegisterClass *const VRSuperclasses[] = {
  &RISCV::VMRegClass,
  nullptr
};

static const TargetRegisterClass *const VRNoV0Superclasses[] = {
  &RISCV::VMRegClass,
  &RISCV::VRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRNoX0Superclasses[] = {
  &RISCV::GPRPairRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRNoX0X2Superclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRJALRSuperclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  nullptr
};

static const TargetRegisterClass *const FPR64CSuperclasses[] = {
  &RISCV::FPR64RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRTCSuperclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRCSuperclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_SR07Superclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCSuperclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRCRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Superclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRCRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_SR07RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_GPRX0Superclasses[] = {
  &RISCV::GPRPairRegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_even_in_SPSuperclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  nullptr
};

static const TargetRegisterClass *const GPRPair_with_sub_gpr_odd_in_GPRX1X5Superclasses[] = {
  &RISCV::GPRPairRegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
  &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
  nullptr
};

static const TargetRegisterClass *const VMV0Superclasses[] = {
  &RISCV::VMRegClass,
  &RISCV::VRRegClass,
  nullptr
};

static const TargetRegisterClass *const VRN2M1NoV0Superclasses[] = {
  &RISCV::VRN2M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRM2NoV0Superclasses[] = {
  &RISCV::VRM2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRM2_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRM2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN2M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN2M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN3M1NoV0Superclasses[] = {
  &RISCV::VRN3M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN3M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN3M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN4M1NoV0Superclasses[] = {
  &RISCV::VRN4M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN2M2NoV0Superclasses[] = {
  &RISCV::VRN2M2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRM4NoV0Superclasses[] = {
  &RISCV::VRM4RegClass,
  nullptr
};

static const TargetRegisterClass *const VRM4_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRM4RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN2M2_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN2M2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN4M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN4M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN5M1NoV0Superclasses[] = {
  &RISCV::VRN5M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN5M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN5M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN6M1NoV0Superclasses[] = {
  &RISCV::VRN6M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN3M2NoV0Superclasses[] = {
  &RISCV::VRN3M2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN3M2_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN3M2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN6M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN6M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN7M1NoV0Superclasses[] = {
  &RISCV::VRN7M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN7M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN7M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN8M1NoV0Superclasses[] = {
  &RISCV::VRN8M1RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN4M2NoV0Superclasses[] = {
  &RISCV::VRN4M2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN2M4NoV0Superclasses[] = {
  &RISCV::VRN2M4RegClass,
  nullptr
};

static const TargetRegisterClass *const VRM8NoV0Superclasses[] = {
  &RISCV::VRM8RegClass,
  nullptr
};

static const TargetRegisterClass *const VRM8_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRM8RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN2M4_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN2M4RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN4M2_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN4M2RegClass,
  nullptr
};

static const TargetRegisterClass *const VRN8M1_with_sub_vrm1_0_in_VMV0Superclasses[] = {
  &RISCV::VRN8M1RegClass,
  nullptr
};


namespace RISCV {   // Register class instances
  extern const TargetRegisterClass FPR16RegClass = {
    &RISCVMCRegisterClasses[FPR16RegClassID],
    FPR16SubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRAllRegClass = {
    &RISCVMCRegisterClasses[GPRAllRegClassID],
    GPRAllSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FPR32RegClass = {
    &RISCVMCRegisterClasses[FPR32RegClassID],
    FPR32SubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRRegClass = {
    &RISCVMCRegisterClasses[GPRRegClassID],
    GPRSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRF16RegClass = {
    &RISCVMCRegisterClasses[GPRF16RegClassID],
    GPRF16SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRF16Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRF32RegClass = {
    &RISCVMCRegisterClasses[GPRF32RegClassID],
    GPRF32SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRF32Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRNoX0RegClass = {
    &RISCVMCRegisterClasses[GPRNoX0RegClassID],
    GPRNoX0SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRNoX0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRNoX0X2RegClass = {
    &RISCVMCRegisterClasses[GPRNoX0X2RegClassID],
    GPRNoX0X2SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRNoX0X2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRJALRRegClass = {
    &RISCVMCRegisterClasses[GPRJALRRegClassID],
    GPRJALRSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRJALRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRTCRegClass = {
    &RISCVMCRegisterClasses[GPRTCRegClassID],
    GPRTCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRTCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FPR32CRegClass = {
    &RISCVMCRegisterClasses[FPR32CRegClassID],
    FPR32CSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FPR32CSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRCRegClass = {
    &RISCVMCRegisterClasses[GPRCRegClassID],
    GPRCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass SR07RegClass = {
    &RISCVMCRegisterClasses[SR07RegClassID],
    SR07SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SR07Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRC_and_GPRTCRegClass = {
    &RISCVMCRegisterClasses[GPRC_and_GPRTCRegClassID],
    GPRC_and_GPRTCSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRC_and_GPRTCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VCSRRegClass = {
    &RISCVMCRegisterClasses[VCSRRegClassID],
    VCSRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRC_and_SR07RegClass = {
    &RISCVMCRegisterClasses[GPRC_and_SR07RegClassID],
    GPRC_and_SR07SubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRC_and_SR07Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRX1X5RegClass = {
    &RISCVMCRegisterClasses[GPRX1X5RegClassID],
    GPRX1X5SubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRX1X5Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRX0RegClass = {
    &RISCVMCRegisterClasses[GPRX0RegClassID],
    GPRX0SubClassMask,
    SuperRegIdxSeqs + 4,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRX0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRX1RegClass = {
    &RISCVMCRegisterClasses[GPRX1RegClassID],
    GPRX1SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRX1Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRX5RegClass = {
    &RISCVMCRegisterClasses[GPRX5RegClassID],
    GPRX5SubClassMask,
    SuperRegIdxSeqs + 7,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    GPRX5Superclasses,
    nullptr
  };

  extern const TargetRegisterClass SPRegClass = {
    &RISCVMCRegisterClasses[SPRegClassID],
    SPSubClassMask,
    SuperRegIdxSeqs + 4,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    SPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FPR64RegClass = {
    &RISCVMCRegisterClasses[FPR64RegClassID],
    FPR64SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VMRegClass = {
    &RISCVMCRegisterClasses[VMRegClassID],
    VMSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VMSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VRRegClass = {
    &RISCVMCRegisterClasses[VRRegClassID],
    VRSubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass VRNoV0RegClass = {
    &RISCVMCRegisterClasses[VRNoV0RegClassID],
    VRNoV0SubClassMask,
    SuperRegIdxSeqs + 11,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRNoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPairRegClass = {
    &RISCVMCRegisterClasses[GPRPairRegClassID],
    GPRPairSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRNoX0RegClassID],
    GPRPair_with_sub_gpr_even_in_GPRNoX0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRNoX0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClassID],
    GPRPair_with_sub_gpr_even_in_GPRNoX0X2SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRNoX0X2Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRJALRRegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRJALRRegClassID],
    GPRPair_with_sub_gpr_even_in_GPRJALRSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRJALRSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass FPR64CRegClass = {
    &RISCVMCRegisterClasses[FPR64CRegClassID],
    FPR64CSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    FPR64CSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRTCRegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRTCRegClassID],
    GPRPair_with_sub_gpr_even_in_GPRTCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRTCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRCRegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRCRegClassID],
    GPRPair_with_sub_gpr_even_in_GPRCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_SR07RegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_SR07RegClassID],
    GPRPair_with_sub_gpr_even_in_SR07SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_SR07Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClassID],
    GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClassID],
    GPRPair_with_sub_gpr_even_in_GPRC_and_SR07SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRC_and_SR07Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_GPRX0RegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_GPRX0RegClassID],
    GPRPair_with_sub_gpr_even_in_GPRX0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_GPRX0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_even_in_SPRegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_even_in_SPRegClassID],
    GPRPair_with_sub_gpr_even_in_SPSubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_even_in_SPSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClass = {
    &RISCVMCRegisterClasses[GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClassID],
    GPRPair_with_sub_gpr_odd_in_GPRX1X5SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x0000000000000006),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    GPRPair_with_sub_gpr_odd_in_GPRX1X5Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VMV0RegClass = {
    &RISCVMCRegisterClasses[VMV0RegClassID],
    VMV0SubClassMask,
    SuperRegIdxSeqs + 9,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M1RegClass = {
    &RISCVMCRegisterClasses[VRN2M1RegClassID],
    VRN2M1SubClassMask,
    SuperRegIdxSeqs + 71,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN2M1NoV0RegClassID],
    VRN2M1NoV0SubClassMask,
    SuperRegIdxSeqs + 71,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN2M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRM2RegClass = {
    &RISCVMCRegisterClasses[VRM2RegClassID],
    VRM2SubClassMask,
    SuperRegIdxSeqs + 22,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRM2NoV0RegClass = {
    &RISCVMCRegisterClasses[VRM2NoV0RegClassID],
    VRM2NoV0SubClassMask,
    SuperRegIdxSeqs + 22,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRM2NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRM2_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRM2_with_sub_vrm1_0_in_VMV0RegClassID],
    VRM2_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 20,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRM2_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN2M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN2M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 32,
    LaneBitmask(0x0000000000000018),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN2M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN3M1RegClass = {
    &RISCVMCRegisterClasses[VRN3M1RegClassID],
    VRN3M1SubClassMask,
    SuperRegIdxSeqs + 64,
    LaneBitmask(0x0000000000000038),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN3M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN3M1NoV0RegClassID],
    VRN3M1NoV0SubClassMask,
    SuperRegIdxSeqs + 64,
    LaneBitmask(0x0000000000000038),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN3M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN3M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN3M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN3M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 34,
    LaneBitmask(0x0000000000000038),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN3M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN4M1RegClass = {
    &RISCVMCRegisterClasses[VRN4M1RegClassID],
    VRN4M1SubClassMask,
    SuperRegIdxSeqs + 58,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN4M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN4M1NoV0RegClassID],
    VRN4M1NoV0SubClassMask,
    SuperRegIdxSeqs + 58,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN4M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M2RegClass = {
    &RISCVMCRegisterClasses[VRN2M2RegClassID],
    VRN2M2SubClassMask,
    SuperRegIdxSeqs + 88,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M2NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN2M2NoV0RegClassID],
    VRN2M2NoV0SubClassMask,
    SuperRegIdxSeqs + 88,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN2M2NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRM4RegClass = {
    &RISCVMCRegisterClasses[VRM4RegClassID],
    VRM4SubClassMask,
    SuperRegIdxSeqs + 29,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRM4NoV0RegClass = {
    &RISCVMCRegisterClasses[VRM4NoV0RegClassID],
    VRM4NoV0SubClassMask,
    SuperRegIdxSeqs + 29,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRM4NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRM4_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRM4_with_sub_vrm1_0_in_VMV0RegClassID],
    VRM4_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 27,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRM4_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M2_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN2M2_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN2M2_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 79,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN2M2_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN4M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN4M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN4M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 36,
    LaneBitmask(0x0000000000000078),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN4M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN5M1RegClass = {
    &RISCVMCRegisterClasses[VRN5M1RegClassID],
    VRN5M1SubClassMask,
    SuperRegIdxSeqs + 53,
    LaneBitmask(0x00000000000000F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN5M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN5M1NoV0RegClassID],
    VRN5M1NoV0SubClassMask,
    SuperRegIdxSeqs + 53,
    LaneBitmask(0x00000000000000F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN5M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN5M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN5M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN5M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 38,
    LaneBitmask(0x00000000000000F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN5M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN6M1RegClass = {
    &RISCVMCRegisterClasses[VRN6M1RegClassID],
    VRN6M1SubClassMask,
    SuperRegIdxSeqs + 49,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN6M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN6M1NoV0RegClassID],
    VRN6M1NoV0SubClassMask,
    SuperRegIdxSeqs + 49,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN6M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN3M2RegClass = {
    &RISCVMCRegisterClasses[VRN3M2RegClassID],
    VRN3M2SubClassMask,
    SuperRegIdxSeqs + 85,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN3M2NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN3M2NoV0RegClassID],
    VRN3M2NoV0SubClassMask,
    SuperRegIdxSeqs + 85,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN3M2NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN3M2_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN3M2_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN3M2_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 81,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN3M2_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN6M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN6M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN6M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 40,
    LaneBitmask(0x00000000000001F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN6M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN7M1RegClass = {
    &RISCVMCRegisterClasses[VRN7M1RegClassID],
    VRN7M1SubClassMask,
    SuperRegIdxSeqs + 46,
    LaneBitmask(0x00000000000003F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN7M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN7M1NoV0RegClassID],
    VRN7M1NoV0SubClassMask,
    SuperRegIdxSeqs + 46,
    LaneBitmask(0x00000000000003F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN7M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN7M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN7M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN7M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 42,
    LaneBitmask(0x00000000000003F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN7M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN8M1RegClass = {
    &RISCVMCRegisterClasses[VRN8M1RegClassID],
    VRN8M1SubClassMask,
    SuperRegIdxSeqs + 44,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN8M1NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN8M1NoV0RegClassID],
    VRN8M1NoV0SubClassMask,
    SuperRegIdxSeqs + 44,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN8M1NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN4M2RegClass = {
    &RISCVMCRegisterClasses[VRN4M2RegClassID],
    VRN4M2SubClassMask,
    SuperRegIdxSeqs + 83,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN4M2NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN4M2NoV0RegClassID],
    VRN4M2NoV0SubClassMask,
    SuperRegIdxSeqs + 83,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN4M2NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M4RegClass = {
    &RISCVMCRegisterClasses[VRN2M4RegClassID],
    VRN2M4SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M4NoV0RegClass = {
    &RISCVMCRegisterClasses[VRN2M4NoV0RegClassID],
    VRN2M4NoV0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN2M4NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRM8RegClass = {
    &RISCVMCRegisterClasses[VRM8RegClassID],
    VRM8SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass VRM8NoV0RegClass = {
    &RISCVMCRegisterClasses[VRM8NoV0RegClassID],
    VRM8NoV0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRM8NoV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRM8_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRM8_with_sub_vrm1_0_in_VMV0RegClassID],
    VRM8_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    VRM8_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN2M4_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN2M4_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN2M4_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 1,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN2M4_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN4M2_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN4M2_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN4M2_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 83,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN4M2_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

  extern const TargetRegisterClass VRN8M1_with_sub_vrm1_0_in_VMV0RegClass = {
    &RISCVMCRegisterClasses[VRN8M1_with_sub_vrm1_0_in_VMV0RegClassID],
    VRN8M1_with_sub_vrm1_0_in_VMV0SubClassMask,
    SuperRegIdxSeqs + 44,
    LaneBitmask(0x00000000000007F8),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    VRN8M1_with_sub_vrm1_0_in_VMV0Superclasses,
    nullptr
  };

} // end namespace RISCV

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &RISCV::FPR16RegClass,
    &RISCV::GPRAllRegClass,
    &RISCV::FPR32RegClass,
    &RISCV::GPRRegClass,
    &RISCV::GPRF16RegClass,
    &RISCV::GPRF32RegClass,
    &RISCV::GPRNoX0RegClass,
    &RISCV::GPRNoX0X2RegClass,
    &RISCV::GPRJALRRegClass,
    &RISCV::GPRTCRegClass,
    &RISCV::FPR32CRegClass,
    &RISCV::GPRCRegClass,
    &RISCV::SR07RegClass,
    &RISCV::GPRC_and_GPRTCRegClass,
    &RISCV::VCSRRegClass,
    &RISCV::GPRC_and_SR07RegClass,
    &RISCV::GPRX1X5RegClass,
    &RISCV::GPRX0RegClass,
    &RISCV::GPRX1RegClass,
    &RISCV::GPRX5RegClass,
    &RISCV::SPRegClass,
    &RISCV::FPR64RegClass,
    &RISCV::VMRegClass,
    &RISCV::VRRegClass,
    &RISCV::VRNoV0RegClass,
    &RISCV::GPRPairRegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0RegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRNoX0X2RegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRJALRRegClass,
    &RISCV::FPR64CRegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRTCRegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRCRegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_SR07RegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTCRegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRC_and_SR07RegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_GPRX0RegClass,
    &RISCV::GPRPair_with_sub_gpr_even_in_SPRegClass,
    &RISCV::GPRPair_with_sub_gpr_odd_in_GPRX1X5RegClass,
    &RISCV::VMV0RegClass,
    &RISCV::VRN2M1RegClass,
    &RISCV::VRN2M1NoV0RegClass,
    &RISCV::VRM2RegClass,
    &RISCV::VRM2NoV0RegClass,
    &RISCV::VRM2_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN2M1_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN3M1RegClass,
    &RISCV::VRN3M1NoV0RegClass,
    &RISCV::VRN3M1_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN4M1RegClass,
    &RISCV::VRN4M1NoV0RegClass,
    &RISCV::VRN2M2RegClass,
    &RISCV::VRN2M2NoV0RegClass,
    &RISCV::VRM4RegClass,
    &RISCV::VRM4NoV0RegClass,
    &RISCV::VRM4_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN2M2_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN4M1_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN5M1RegClass,
    &RISCV::VRN5M1NoV0RegClass,
    &RISCV::VRN5M1_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN6M1RegClass,
    &RISCV::VRN6M1NoV0RegClass,
    &RISCV::VRN3M2RegClass,
    &RISCV::VRN3M2NoV0RegClass,
    &RISCV::VRN3M2_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN6M1_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN7M1RegClass,
    &RISCV::VRN7M1NoV0RegClass,
    &RISCV::VRN7M1_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN8M1RegClass,
    &RISCV::VRN8M1NoV0RegClass,
    &RISCV::VRN4M2RegClass,
    &RISCV::VRN4M2NoV0RegClass,
    &RISCV::VRN2M4RegClass,
    &RISCV::VRN2M4NoV0RegClass,
    &RISCV::VRM8RegClass,
    &RISCV::VRM8NoV0RegClass,
    &RISCV::VRM8_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN2M4_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN4M2_with_sub_vrm1_0_in_VMV0RegClass,
    &RISCV::VRN8M1_with_sub_vrm1_0_in_VMV0RegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc RISCVRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 2, InAllocatableClassTable};

unsigned RISCVGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[52] = {
    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 0, 2, 0, 0, 0, 4, 4, 1, 0, 0, 0, 0, 4, 4, 4, 4, 1, 1, 1, 1, 5, 5, 5, 5, 2, 2, 2, 6, 6, 3, 0, 0, 0, 1, 1, 2, 
  };
  static const uint8_t Rows[7][52] = {
    { RISCV::sub_16, 0, 0, 0, RISCV::sub_vrm1_0, RISCV::sub_vrm1_1, RISCV::sub_vrm1_2, RISCV::sub_vrm1_3, RISCV::sub_vrm1_4, RISCV::sub_vrm1_5, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, RISCV::sub_vrm2_0, RISCV::sub_vrm2_1, RISCV::sub_vrm2_2, RISCV::sub_vrm2_3, 0, 0, RISCV::sub_vrm1_0_sub_vrm1_1, RISCV::sub_vrm1_0_sub_vrm1_1_sub_vrm1_2, RISCV::sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, RISCV::sub_vrm1_1_sub_vrm1_2, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, RISCV::sub_vrm1_2_sub_vrm1_3, RISCV::sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm2_0_sub_vrm2_1, RISCV::sub_vrm2_0_sub_vrm2_1_sub_vrm2_2, 0, RISCV::sub_vrm2_1_sub_vrm2_2, RISCV::sub_vrm2_1_sub_vrm2_2_sub_vrm2_3, RISCV::sub_vrm2_2_sub_vrm2_3, },
    { 0, 0, 0, 0, RISCV::sub_vrm1_2, RISCV::sub_vrm1_3, RISCV::sub_vrm1_4, RISCV::sub_vrm1_5, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, 0, 0, RISCV::sub_vrm2_1, RISCV::sub_vrm2_2, RISCV::sub_vrm2_3, 0, 0, 0, RISCV::sub_vrm1_2_sub_vrm1_3, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, 0, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, 0, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, 0, RISCV::sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, 0, RISCV::sub_vrm1_6_sub_vrm1_7, 0, 0, 0, 0, 0, RISCV::sub_vrm2_1_sub_vrm2_2, 0, 0, RISCV::sub_vrm2_2_sub_vrm2_3, 0, 0, },
    { 0, 0, 0, 0, RISCV::sub_vrm1_4, RISCV::sub_vrm1_5, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, 0, 0, 0, 0, RISCV::sub_vrm2_2, RISCV::sub_vrm2_3, 0, 0, 0, 0, RISCV::sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, RISCV::sub_vrm1_6_sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, RISCV::sub_vrm1_1, RISCV::sub_vrm1_2, RISCV::sub_vrm1_3, RISCV::sub_vrm1_4, RISCV::sub_vrm1_5, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, RISCV::sub_vrm1_1_sub_vrm1_2, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_2_sub_vrm1_3, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, 0, 0, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, RISCV::sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, RISCV::sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, RISCV::sub_vrm1_6_sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, RISCV::sub_vrm1_3, RISCV::sub_vrm1_4, RISCV::sub_vrm1_5, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, RISCV::sub_vrm1_3_sub_vrm1_4, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_4_sub_vrm1_5, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6, RISCV::sub_vrm1_5_sub_vrm1_6, 0, 0, 0, 0, RISCV::sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, 0, 0, RISCV::sub_vrm1_5_sub_vrm1_6_sub_vrm1_7, 0, 0, 0, RISCV::sub_vrm1_6_sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
    { 0, 0, 0, 0, RISCV::sub_vrm1_5, RISCV::sub_vrm1_6, RISCV::sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, RISCV::sub_vrm1_5_sub_vrm1_6, 0, 0, RISCV::sub_vrm1_6_sub_vrm1_7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
  };

  --IdxA; assert(IdxA < 52); (void) IdxA;
  --IdxB; assert(IdxB < 52);
  return Rows[RowMap[IdxA]][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 },   // Sequence 6
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  4 }, { LaneBitmask::getNone(), 0 },   // Sequence 8
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  5 }, { LaneBitmask::getNone(), 0 },   // Sequence 10
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  6 }, { LaneBitmask::getNone(), 0 },   // Sequence 12
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  7 }, { LaneBitmask::getNone(), 0 },   // Sequence 14
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  8 }, { LaneBitmask::getNone(), 0 },   // Sequence 16
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  9 }, { LaneBitmask::getNone(), 0 },   // Sequence 18
    { LaneBitmask(0xFFFFFFFFFFFFFFFF), 10 }, { LaneBitmask::getNone(), 0 }  // Sequence 20
  };
  static const uint8_t CompositeSequences[] = {
    0, // to sub_16
    0, // to sub_32
    2, // to sub_gpr_even
    4, // to sub_gpr_odd
    6, // to sub_vrm1_0
    8, // to sub_vrm1_1
    10, // to sub_vrm1_2
    12, // to sub_vrm1_3
    14, // to sub_vrm1_4
    16, // to sub_vrm1_5
    18, // to sub_vrm1_6
    20, // to sub_vrm1_7
    0, // to sub_vrm2_0
    4, // to sub_vrm2_1
    8, // to sub_vrm2_2
    12, // to sub_vrm2_3
    0, // to sub_vrm4_0
    8, // to sub_vrm4_1
    0, // to sub_vrm1_0_sub_vrm1_1
    0, // to sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
    0, // to sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
    2, // to sub_vrm1_1_sub_vrm1_2
    2, // to sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
    4, // to sub_vrm1_2_sub_vrm1_3
    0, // to sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
    0, // to sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
    0, // to sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
    0, // to sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
    2, // to sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
    2, // to sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
    2, // to sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
    2, // to sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
    4, // to sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
    4, // to sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
    4, // to sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
    4, // to sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
    6, // to sub_vrm1_3_sub_vrm1_4
    6, // to sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
    6, // to sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
    6, // to sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
    8, // to sub_vrm1_4_sub_vrm1_5
    8, // to sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
    8, // to sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
    10, // to sub_vrm1_5_sub_vrm1_6
    10, // to sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
    12, // to sub_vrm1_6_sub_vrm1_7
    0, // to sub_vrm2_0_sub_vrm2_1
    0, // to sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
    0, // to sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
    4, // to sub_vrm2_1_sub_vrm2_2
    4, // to sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
    8 // to sub_vrm2_2_sub_vrm2_3
  };

LaneBitmask RISCVGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 52 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask RISCVGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 52 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *RISCVGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[81][52] = {
    { // FPR16
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRAll
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // FPR32
      3,  // sub_16 -> FPR32
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPR
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRF16
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRF32
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRNoX0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRNoX0X2
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRJALR
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRTC
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // FPR32C
      11, // sub_16 -> FPR32C
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRC
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // SR07
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRC_and_GPRTC
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VCSR
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRC_and_SR07
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX1X5
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX5
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // SP
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // FPR64
      22, // sub_16 -> FPR64
      22, // sub_32 -> FPR64
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VM
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VR
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRNoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair
      0,  // sub_16
      0,  // sub_32
      26, // sub_gpr_even -> GPRPair
      26, // sub_gpr_odd -> GPRPair
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRNoX0
      0,  // sub_16
      0,  // sub_32
      27, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRNoX0
      27, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRNoX0
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRNoX0X2
      0,  // sub_16
      0,  // sub_32
      28, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRNoX0X2
      28, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRNoX0X2
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRJALR
      0,  // sub_16
      0,  // sub_32
      29, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRJALR
      29, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRJALR
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // FPR64C
      30, // sub_16 -> FPR64C
      30, // sub_32 -> FPR64C
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRTC
      0,  // sub_16
      0,  // sub_32
      31, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRTC
      31, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRTC
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRC
      0,  // sub_16
      0,  // sub_32
      32, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRC
      32, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRC
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_SR07
      0,  // sub_16
      0,  // sub_32
      33, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_SR07
      33, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_SR07
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
      0,  // sub_16
      0,  // sub_32
      34, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
      34, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
      0,  // sub_16
      0,  // sub_32
      35, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
      35, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRX0
      0,  // sub_16
      0,  // sub_32
      36, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_GPRX0
      36, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_GPRX0
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_SP
      0,  // sub_16
      0,  // sub_32
      37, // sub_gpr_even -> GPRPair_with_sub_gpr_even_in_SP
      37, // sub_gpr_odd -> GPRPair_with_sub_gpr_even_in_SP
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_odd_in_GPRX1X5
      0,  // sub_16
      0,  // sub_32
      38, // sub_gpr_even -> GPRPair_with_sub_gpr_odd_in_GPRX1X5
      38, // sub_gpr_odd -> GPRPair_with_sub_gpr_odd_in_GPRX1X5
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      0,  // sub_vrm1_0
      0,  // sub_vrm1_1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      40, // sub_vrm1_0 -> VRN2M1
      40, // sub_vrm1_1 -> VRN2M1
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      41, // sub_vrm1_0 -> VRN2M1NoV0
      41, // sub_vrm1_1 -> VRN2M1NoV0
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM2
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      42, // sub_vrm1_0 -> VRM2
      42, // sub_vrm1_1 -> VRM2
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM2NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      43, // sub_vrm1_0 -> VRM2NoV0
      43, // sub_vrm1_1 -> VRM2NoV0
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM2_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      44, // sub_vrm1_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      44, // sub_vrm1_1 -> VRM2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      45, // sub_vrm1_0 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      45, // sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_2
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      46, // sub_vrm1_0 -> VRN3M1
      46, // sub_vrm1_1 -> VRN3M1
      46, // sub_vrm1_2 -> VRN3M1
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      46, // sub_vrm1_0_sub_vrm1_1 -> VRN3M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      46, // sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      47, // sub_vrm1_0 -> VRN3M1NoV0
      47, // sub_vrm1_1 -> VRN3M1NoV0
      47, // sub_vrm1_2 -> VRN3M1NoV0
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      47, // sub_vrm1_0_sub_vrm1_1 -> VRN3M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      47, // sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      48, // sub_vrm1_0 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      48, // sub_vrm1_1 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      48, // sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_3
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      48, // sub_vrm1_0_sub_vrm1_1 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      48, // sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      49, // sub_vrm1_0 -> VRN4M1
      49, // sub_vrm1_1 -> VRN4M1
      49, // sub_vrm1_2 -> VRN4M1
      49, // sub_vrm1_3 -> VRN4M1
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      49, // sub_vrm1_0_sub_vrm1_1 -> VRN4M1
      49, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN4M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      49, // sub_vrm1_1_sub_vrm1_2 -> VRN4M1
      49, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      49, // sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      50, // sub_vrm1_0 -> VRN4M1NoV0
      50, // sub_vrm1_1 -> VRN4M1NoV0
      50, // sub_vrm1_2 -> VRN4M1NoV0
      50, // sub_vrm1_3 -> VRN4M1NoV0
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      50, // sub_vrm1_0_sub_vrm1_1 -> VRN4M1NoV0
      50, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN4M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      50, // sub_vrm1_1_sub_vrm1_2 -> VRN4M1NoV0
      50, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      50, // sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M2
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      51, // sub_vrm1_0 -> VRN2M2
      51, // sub_vrm1_1 -> VRN2M2
      51, // sub_vrm1_2 -> VRN2M2
      51, // sub_vrm1_3 -> VRN2M2
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      51, // sub_vrm2_0 -> VRN2M2
      51, // sub_vrm2_1 -> VRN2M2
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      51, // sub_vrm1_0_sub_vrm1_1 -> VRN2M2
      51, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN2M2
      51, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M2
      51, // sub_vrm1_1_sub_vrm1_2 -> VRN2M2
      51, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M2
      51, // sub_vrm1_2_sub_vrm1_3 -> VRN2M2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M2NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      52, // sub_vrm1_0 -> VRN2M2NoV0
      52, // sub_vrm1_1 -> VRN2M2NoV0
      52, // sub_vrm1_2 -> VRN2M2NoV0
      52, // sub_vrm1_3 -> VRN2M2NoV0
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      52, // sub_vrm2_0 -> VRN2M2NoV0
      52, // sub_vrm2_1 -> VRN2M2NoV0
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      52, // sub_vrm1_0_sub_vrm1_1 -> VRN2M2NoV0
      52, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN2M2NoV0
      52, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M2NoV0
      52, // sub_vrm1_1_sub_vrm1_2 -> VRN2M2NoV0
      52, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M2NoV0
      52, // sub_vrm1_2_sub_vrm1_3 -> VRN2M2NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM4
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      53, // sub_vrm1_0 -> VRM4
      53, // sub_vrm1_1 -> VRM4
      53, // sub_vrm1_2 -> VRM4
      53, // sub_vrm1_3 -> VRM4
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      53, // sub_vrm2_0 -> VRM4
      53, // sub_vrm2_1 -> VRM4
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM4NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      54, // sub_vrm1_0 -> VRM4NoV0
      54, // sub_vrm1_1 -> VRM4NoV0
      54, // sub_vrm1_2 -> VRM4NoV0
      54, // sub_vrm1_3 -> VRM4NoV0
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      54, // sub_vrm2_0 -> VRM4NoV0
      54, // sub_vrm2_1 -> VRM4NoV0
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM4_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      55, // sub_vrm1_0 -> VRM4_with_sub_vrm1_0_in_VMV0
      55, // sub_vrm1_1 -> VRM4_with_sub_vrm1_0_in_VMV0
      55, // sub_vrm1_2 -> VRM4_with_sub_vrm1_0_in_VMV0
      55, // sub_vrm1_3 -> VRM4_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      55, // sub_vrm2_0 -> VRM4_with_sub_vrm1_0_in_VMV0
      55, // sub_vrm2_1 -> VRM4_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      56, // sub_vrm1_0 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_1 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_2 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_3 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      56, // sub_vrm2_0 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm2_1 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      56, // sub_vrm1_0_sub_vrm1_1 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_1_sub_vrm1_2 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      56, // sub_vrm1_2_sub_vrm1_3 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      57, // sub_vrm1_0 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      57, // sub_vrm1_1 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      57, // sub_vrm1_2 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      57, // sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_4
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      57, // sub_vrm1_0_sub_vrm1_1 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      57, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      57, // sub_vrm1_1_sub_vrm1_2 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      57, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      57, // sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN5M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      58, // sub_vrm1_0 -> VRN5M1
      58, // sub_vrm1_1 -> VRN5M1
      58, // sub_vrm1_2 -> VRN5M1
      58, // sub_vrm1_3 -> VRN5M1
      58, // sub_vrm1_4 -> VRN5M1
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      58, // sub_vrm1_0_sub_vrm1_1 -> VRN5M1
      58, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN5M1
      58, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN5M1
      58, // sub_vrm1_1_sub_vrm1_2 -> VRN5M1
      58, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN5M1
      58, // sub_vrm1_2_sub_vrm1_3 -> VRN5M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      58, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      58, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      58, // sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN5M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      59, // sub_vrm1_0 -> VRN5M1NoV0
      59, // sub_vrm1_1 -> VRN5M1NoV0
      59, // sub_vrm1_2 -> VRN5M1NoV0
      59, // sub_vrm1_3 -> VRN5M1NoV0
      59, // sub_vrm1_4 -> VRN5M1NoV0
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      59, // sub_vrm1_0_sub_vrm1_1 -> VRN5M1NoV0
      59, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN5M1NoV0
      59, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN5M1NoV0
      59, // sub_vrm1_1_sub_vrm1_2 -> VRN5M1NoV0
      59, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN5M1NoV0
      59, // sub_vrm1_2_sub_vrm1_3 -> VRN5M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      59, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      59, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      59, // sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      60, // sub_vrm1_0 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_1 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_2 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_3 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_5
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      60, // sub_vrm1_0_sub_vrm1_1 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_1_sub_vrm1_2 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      60, // sub_vrm1_2_sub_vrm1_3 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      60, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      60, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      60, // sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN6M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      61, // sub_vrm1_0 -> VRN6M1
      61, // sub_vrm1_1 -> VRN6M1
      61, // sub_vrm1_2 -> VRN6M1
      61, // sub_vrm1_3 -> VRN6M1
      61, // sub_vrm1_4 -> VRN6M1
      61, // sub_vrm1_5 -> VRN6M1
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      61, // sub_vrm1_0_sub_vrm1_1 -> VRN6M1
      61, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN6M1
      61, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN6M1
      61, // sub_vrm1_1_sub_vrm1_2 -> VRN6M1
      61, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN6M1
      61, // sub_vrm1_2_sub_vrm1_3 -> VRN6M1
      61, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      61, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1
      61, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      61, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1
      61, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      61, // sub_vrm1_3_sub_vrm1_4 -> VRN6M1
      61, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      61, // sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN6M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      62, // sub_vrm1_0 -> VRN6M1NoV0
      62, // sub_vrm1_1 -> VRN6M1NoV0
      62, // sub_vrm1_2 -> VRN6M1NoV0
      62, // sub_vrm1_3 -> VRN6M1NoV0
      62, // sub_vrm1_4 -> VRN6M1NoV0
      62, // sub_vrm1_5 -> VRN6M1NoV0
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      62, // sub_vrm1_0_sub_vrm1_1 -> VRN6M1NoV0
      62, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN6M1NoV0
      62, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN6M1NoV0
      62, // sub_vrm1_1_sub_vrm1_2 -> VRN6M1NoV0
      62, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN6M1NoV0
      62, // sub_vrm1_2_sub_vrm1_3 -> VRN6M1NoV0
      62, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      62, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1NoV0
      62, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      62, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1NoV0
      62, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      62, // sub_vrm1_3_sub_vrm1_4 -> VRN6M1NoV0
      62, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      62, // sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M2
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      63, // sub_vrm1_0 -> VRN3M2
      63, // sub_vrm1_1 -> VRN3M2
      63, // sub_vrm1_2 -> VRN3M2
      63, // sub_vrm1_3 -> VRN3M2
      63, // sub_vrm1_4 -> VRN3M2
      63, // sub_vrm1_5 -> VRN3M2
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      63, // sub_vrm2_0 -> VRN3M2
      63, // sub_vrm2_1 -> VRN3M2
      63, // sub_vrm2_2 -> VRN3M2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      63, // sub_vrm1_0_sub_vrm1_1 -> VRN3M2
      63, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M2
      63, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M2
      63, // sub_vrm1_1_sub_vrm1_2 -> VRN3M2
      63, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M2
      63, // sub_vrm1_2_sub_vrm1_3 -> VRN3M2
      63, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2
      63, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      63, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2
      63, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      63, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2
      63, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      63, // sub_vrm1_3_sub_vrm1_4 -> VRN3M2
      63, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      63, // sub_vrm1_4_sub_vrm1_5 -> VRN3M2
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      63, // sub_vrm2_0_sub_vrm2_1 -> VRN3M2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      63, // sub_vrm2_1_sub_vrm2_2 -> VRN3M2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M2NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      64, // sub_vrm1_0 -> VRN3M2NoV0
      64, // sub_vrm1_1 -> VRN3M2NoV0
      64, // sub_vrm1_2 -> VRN3M2NoV0
      64, // sub_vrm1_3 -> VRN3M2NoV0
      64, // sub_vrm1_4 -> VRN3M2NoV0
      64, // sub_vrm1_5 -> VRN3M2NoV0
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      64, // sub_vrm2_0 -> VRN3M2NoV0
      64, // sub_vrm2_1 -> VRN3M2NoV0
      64, // sub_vrm2_2 -> VRN3M2NoV0
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      64, // sub_vrm1_0_sub_vrm1_1 -> VRN3M2NoV0
      64, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M2NoV0
      64, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M2NoV0
      64, // sub_vrm1_1_sub_vrm1_2 -> VRN3M2NoV0
      64, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M2NoV0
      64, // sub_vrm1_2_sub_vrm1_3 -> VRN3M2NoV0
      64, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2NoV0
      64, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      64, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2NoV0
      64, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2NoV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      64, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2NoV0
      64, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2NoV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      64, // sub_vrm1_3_sub_vrm1_4 -> VRN3M2NoV0
      64, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2NoV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      64, // sub_vrm1_4_sub_vrm1_5 -> VRN3M2NoV0
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      64, // sub_vrm2_0_sub_vrm2_1 -> VRN3M2NoV0
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      64, // sub_vrm2_1_sub_vrm2_2 -> VRN3M2NoV0
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      65, // sub_vrm1_0 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_1 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_3 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_4 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_5 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      65, // sub_vrm2_0 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm2_1 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm2_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      65, // sub_vrm1_0_sub_vrm1_1 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_1_sub_vrm1_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_2_sub_vrm1_3 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      65, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      65, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      65, // sub_vrm1_3_sub_vrm1_4 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      65, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      65, // sub_vrm1_4_sub_vrm1_5 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      65, // sub_vrm2_0_sub_vrm2_1 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      65, // sub_vrm2_1_sub_vrm2_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      66, // sub_vrm1_0 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_1 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_2 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_3 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_4 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_6
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      66, // sub_vrm1_0_sub_vrm1_1 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_1_sub_vrm1_2 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_2_sub_vrm1_3 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      66, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      66, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      66, // sub_vrm1_3_sub_vrm1_4 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      66, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      66, // sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN7M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      67, // sub_vrm1_0 -> VRN7M1
      67, // sub_vrm1_1 -> VRN7M1
      67, // sub_vrm1_2 -> VRN7M1
      67, // sub_vrm1_3 -> VRN7M1
      67, // sub_vrm1_4 -> VRN7M1
      67, // sub_vrm1_5 -> VRN7M1
      67, // sub_vrm1_6 -> VRN7M1
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      67, // sub_vrm1_0_sub_vrm1_1 -> VRN7M1
      67, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN7M1
      67, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN7M1
      67, // sub_vrm1_1_sub_vrm1_2 -> VRN7M1
      67, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN7M1
      67, // sub_vrm1_2_sub_vrm1_3 -> VRN7M1
      67, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1
      67, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      67, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1
      67, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1
      67, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      67, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1
      67, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1
      67, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      67, // sub_vrm1_3_sub_vrm1_4 -> VRN7M1
      67, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1
      67, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      67, // sub_vrm1_4_sub_vrm1_5 -> VRN7M1
      67, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      67, // sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN7M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      68, // sub_vrm1_0 -> VRN7M1NoV0
      68, // sub_vrm1_1 -> VRN7M1NoV0
      68, // sub_vrm1_2 -> VRN7M1NoV0
      68, // sub_vrm1_3 -> VRN7M1NoV0
      68, // sub_vrm1_4 -> VRN7M1NoV0
      68, // sub_vrm1_5 -> VRN7M1NoV0
      68, // sub_vrm1_6 -> VRN7M1NoV0
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      68, // sub_vrm1_0_sub_vrm1_1 -> VRN7M1NoV0
      68, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN7M1NoV0
      68, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN7M1NoV0
      68, // sub_vrm1_1_sub_vrm1_2 -> VRN7M1NoV0
      68, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN7M1NoV0
      68, // sub_vrm1_2_sub_vrm1_3 -> VRN7M1NoV0
      68, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1NoV0
      68, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      68, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1NoV0
      68, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1NoV0
      68, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      68, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1NoV0
      68, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1NoV0
      68, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      68, // sub_vrm1_3_sub_vrm1_4 -> VRN7M1NoV0
      68, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1NoV0
      68, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      68, // sub_vrm1_4_sub_vrm1_5 -> VRN7M1NoV0
      68, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      68, // sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      69, // sub_vrm1_0 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_1 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_2 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_3 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_4 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_5 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_7
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      69, // sub_vrm1_0_sub_vrm1_1 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_1_sub_vrm1_2 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_2_sub_vrm1_3 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      69, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      69, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      69, // sub_vrm1_3_sub_vrm1_4 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      69, // sub_vrm1_4_sub_vrm1_5 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      69, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      69, // sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN8M1
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      70, // sub_vrm1_0 -> VRN8M1
      70, // sub_vrm1_1 -> VRN8M1
      70, // sub_vrm1_2 -> VRN8M1
      70, // sub_vrm1_3 -> VRN8M1
      70, // sub_vrm1_4 -> VRN8M1
      70, // sub_vrm1_5 -> VRN8M1
      70, // sub_vrm1_6 -> VRN8M1
      70, // sub_vrm1_7 -> VRN8M1
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      70, // sub_vrm1_0_sub_vrm1_1 -> VRN8M1
      70, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN8M1
      70, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN8M1
      70, // sub_vrm1_1_sub_vrm1_2 -> VRN8M1
      70, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN8M1
      70, // sub_vrm1_2_sub_vrm1_3 -> VRN8M1
      70, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1
      70, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1
      70, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      70, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1
      70, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1
      70, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1
      70, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      70, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1
      70, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1
      70, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1
      70, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      70, // sub_vrm1_3_sub_vrm1_4 -> VRN8M1
      70, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1
      70, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1
      70, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      70, // sub_vrm1_4_sub_vrm1_5 -> VRN8M1
      70, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1
      70, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      70, // sub_vrm1_5_sub_vrm1_6 -> VRN8M1
      70, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      70, // sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN8M1NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      71, // sub_vrm1_0 -> VRN8M1NoV0
      71, // sub_vrm1_1 -> VRN8M1NoV0
      71, // sub_vrm1_2 -> VRN8M1NoV0
      71, // sub_vrm1_3 -> VRN8M1NoV0
      71, // sub_vrm1_4 -> VRN8M1NoV0
      71, // sub_vrm1_5 -> VRN8M1NoV0
      71, // sub_vrm1_6 -> VRN8M1NoV0
      71, // sub_vrm1_7 -> VRN8M1NoV0
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      71, // sub_vrm1_0_sub_vrm1_1 -> VRN8M1NoV0
      71, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN8M1NoV0
      71, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN8M1NoV0
      71, // sub_vrm1_1_sub_vrm1_2 -> VRN8M1NoV0
      71, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN8M1NoV0
      71, // sub_vrm1_2_sub_vrm1_3 -> VRN8M1NoV0
      71, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1NoV0
      71, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1NoV0
      71, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1NoV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      71, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1NoV0
      71, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1NoV0
      71, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1NoV0
      71, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      71, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1NoV0
      71, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1NoV0
      71, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1NoV0
      71, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      71, // sub_vrm1_3_sub_vrm1_4 -> VRN8M1NoV0
      71, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1NoV0
      71, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1NoV0
      71, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      71, // sub_vrm1_4_sub_vrm1_5 -> VRN8M1NoV0
      71, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1NoV0
      71, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      71, // sub_vrm1_5_sub_vrm1_6 -> VRN8M1NoV0
      71, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      71, // sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M2
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      72, // sub_vrm1_0 -> VRN4M2
      72, // sub_vrm1_1 -> VRN4M2
      72, // sub_vrm1_2 -> VRN4M2
      72, // sub_vrm1_3 -> VRN4M2
      72, // sub_vrm1_4 -> VRN4M2
      72, // sub_vrm1_5 -> VRN4M2
      72, // sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_7 -> VRN4M2
      72, // sub_vrm2_0 -> VRN4M2
      72, // sub_vrm2_1 -> VRN4M2
      72, // sub_vrm2_2 -> VRN4M2
      72, // sub_vrm2_3 -> VRN4M2
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      72, // sub_vrm1_0_sub_vrm1_1 -> VRN4M2
      72, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN4M2
      72, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M2
      72, // sub_vrm1_1_sub_vrm1_2 -> VRN4M2
      72, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M2
      72, // sub_vrm1_2_sub_vrm1_3 -> VRN4M2
      72, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2
      72, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2
      72, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2
      72, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2
      72, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2
      72, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2
      72, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm1_3_sub_vrm1_4 -> VRN4M2
      72, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2
      72, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm1_4_sub_vrm1_5 -> VRN4M2
      72, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm1_5_sub_vrm1_6 -> VRN4M2
      72, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm1_6_sub_vrm1_7 -> VRN4M2
      72, // sub_vrm2_0_sub_vrm2_1 -> VRN4M2
      72, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN4M2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      72, // sub_vrm2_1_sub_vrm2_2 -> VRN4M2
      72, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN4M2
      72, // sub_vrm2_2_sub_vrm2_3 -> VRN4M2
    },
    { // VRN4M2NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      73, // sub_vrm1_0 -> VRN4M2NoV0
      73, // sub_vrm1_1 -> VRN4M2NoV0
      73, // sub_vrm1_2 -> VRN4M2NoV0
      73, // sub_vrm1_3 -> VRN4M2NoV0
      73, // sub_vrm1_4 -> VRN4M2NoV0
      73, // sub_vrm1_5 -> VRN4M2NoV0
      73, // sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm2_0 -> VRN4M2NoV0
      73, // sub_vrm2_1 -> VRN4M2NoV0
      73, // sub_vrm2_2 -> VRN4M2NoV0
      73, // sub_vrm2_3 -> VRN4M2NoV0
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      73, // sub_vrm1_0_sub_vrm1_1 -> VRN4M2NoV0
      73, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN4M2NoV0
      73, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M2NoV0
      73, // sub_vrm1_1_sub_vrm1_2 -> VRN4M2NoV0
      73, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M2NoV0
      73, // sub_vrm1_2_sub_vrm1_3 -> VRN4M2NoV0
      73, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2NoV0
      73, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2NoV0
      73, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2NoV0
      73, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2NoV0
      73, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2NoV0
      73, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2NoV0
      73, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm1_3_sub_vrm1_4 -> VRN4M2NoV0
      73, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2NoV0
      73, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm1_4_sub_vrm1_5 -> VRN4M2NoV0
      73, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm1_5_sub_vrm1_6 -> VRN4M2NoV0
      73, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm1_6_sub_vrm1_7 -> VRN4M2NoV0
      73, // sub_vrm2_0_sub_vrm2_1 -> VRN4M2NoV0
      73, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN4M2NoV0
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      73, // sub_vrm2_1_sub_vrm2_2 -> VRN4M2NoV0
      73, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN4M2NoV0
      73, // sub_vrm2_2_sub_vrm2_3 -> VRN4M2NoV0
    },
    { // VRN2M4
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      74, // sub_vrm1_0 -> VRN2M4
      74, // sub_vrm1_1 -> VRN2M4
      74, // sub_vrm1_2 -> VRN2M4
      74, // sub_vrm1_3 -> VRN2M4
      74, // sub_vrm1_4 -> VRN2M4
      74, // sub_vrm1_5 -> VRN2M4
      74, // sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_7 -> VRN2M4
      74, // sub_vrm2_0 -> VRN2M4
      74, // sub_vrm2_1 -> VRN2M4
      74, // sub_vrm2_2 -> VRN2M4
      74, // sub_vrm2_3 -> VRN2M4
      74, // sub_vrm4_0 -> VRN2M4
      74, // sub_vrm4_1 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M4
      74, // sub_vrm1_1_sub_vrm1_2 -> VRN2M4
      74, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M4
      74, // sub_vrm1_2_sub_vrm1_3 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4
      74, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4
      74, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4
      74, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4
      74, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm1_3_sub_vrm1_4 -> VRN2M4
      74, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4
      74, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm1_4_sub_vrm1_5 -> VRN2M4
      74, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm1_5_sub_vrm1_6 -> VRN2M4
      74, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm1_6_sub_vrm1_7 -> VRN2M4
      74, // sub_vrm2_0_sub_vrm2_1 -> VRN2M4
      74, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN2M4
      74, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN2M4
      74, // sub_vrm2_1_sub_vrm2_2 -> VRN2M4
      74, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN2M4
      74, // sub_vrm2_2_sub_vrm2_3 -> VRN2M4
    },
    { // VRN2M4NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      75, // sub_vrm1_0 -> VRN2M4NoV0
      75, // sub_vrm1_1 -> VRN2M4NoV0
      75, // sub_vrm1_2 -> VRN2M4NoV0
      75, // sub_vrm1_3 -> VRN2M4NoV0
      75, // sub_vrm1_4 -> VRN2M4NoV0
      75, // sub_vrm1_5 -> VRN2M4NoV0
      75, // sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm2_0 -> VRN2M4NoV0
      75, // sub_vrm2_1 -> VRN2M4NoV0
      75, // sub_vrm2_2 -> VRN2M4NoV0
      75, // sub_vrm2_3 -> VRN2M4NoV0
      75, // sub_vrm4_0 -> VRN2M4NoV0
      75, // sub_vrm4_1 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M4NoV0
      75, // sub_vrm1_1_sub_vrm1_2 -> VRN2M4NoV0
      75, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M4NoV0
      75, // sub_vrm1_2_sub_vrm1_3 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4NoV0
      75, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4NoV0
      75, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4NoV0
      75, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4NoV0
      75, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm1_3_sub_vrm1_4 -> VRN2M4NoV0
      75, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4NoV0
      75, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm1_4_sub_vrm1_5 -> VRN2M4NoV0
      75, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm1_5_sub_vrm1_6 -> VRN2M4NoV0
      75, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm1_6_sub_vrm1_7 -> VRN2M4NoV0
      75, // sub_vrm2_0_sub_vrm2_1 -> VRN2M4NoV0
      75, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN2M4NoV0
      75, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN2M4NoV0
      75, // sub_vrm2_1_sub_vrm2_2 -> VRN2M4NoV0
      75, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN2M4NoV0
      75, // sub_vrm2_2_sub_vrm2_3 -> VRN2M4NoV0
    },
    { // VRM8
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      76, // sub_vrm1_0 -> VRM8
      76, // sub_vrm1_1 -> VRM8
      76, // sub_vrm1_2 -> VRM8
      76, // sub_vrm1_3 -> VRM8
      76, // sub_vrm1_4 -> VRM8
      76, // sub_vrm1_5 -> VRM8
      76, // sub_vrm1_6 -> VRM8
      76, // sub_vrm1_7 -> VRM8
      76, // sub_vrm2_0 -> VRM8
      76, // sub_vrm2_1 -> VRM8
      76, // sub_vrm2_2 -> VRM8
      76, // sub_vrm2_3 -> VRM8
      76, // sub_vrm4_0 -> VRM8
      76, // sub_vrm4_1 -> VRM8
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM8NoV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      77, // sub_vrm1_0 -> VRM8NoV0
      77, // sub_vrm1_1 -> VRM8NoV0
      77, // sub_vrm1_2 -> VRM8NoV0
      77, // sub_vrm1_3 -> VRM8NoV0
      77, // sub_vrm1_4 -> VRM8NoV0
      77, // sub_vrm1_5 -> VRM8NoV0
      77, // sub_vrm1_6 -> VRM8NoV0
      77, // sub_vrm1_7 -> VRM8NoV0
      77, // sub_vrm2_0 -> VRM8NoV0
      77, // sub_vrm2_1 -> VRM8NoV0
      77, // sub_vrm2_2 -> VRM8NoV0
      77, // sub_vrm2_3 -> VRM8NoV0
      77, // sub_vrm4_0 -> VRM8NoV0
      77, // sub_vrm4_1 -> VRM8NoV0
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRM8_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      78, // sub_vrm1_0 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_1 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_2 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_3 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_4 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_5 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_6 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm1_7 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm2_0 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm2_1 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm2_2 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm2_3 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm4_0 -> VRM8_with_sub_vrm1_0_in_VMV0
      78, // sub_vrm4_1 -> VRM8_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_1_sub_vrm1_2
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_2_sub_vrm1_3
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_3_sub_vrm1_4
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_4_sub_vrm1_5
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_5_sub_vrm1_6
      0,  // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm1_6_sub_vrm1_7
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M4_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      79, // sub_vrm1_0 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_2 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_4 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_5 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_0 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_1 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_2 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm4_0 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm4_1 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1_sub_vrm1_2 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_2_sub_vrm1_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_3_sub_vrm1_4 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_4_sub_vrm1_5 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_5_sub_vrm1_6 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm1_6_sub_vrm1_7 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_0_sub_vrm2_1 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_1_sub_vrm2_2 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
      79, // sub_vrm2_2_sub_vrm2_3 -> VRN2M4_with_sub_vrm1_0_in_VMV0
    },
    { // VRN4M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      80, // sub_vrm1_0 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_2 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_4 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_5 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_0 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_1 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_2 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      80, // sub_vrm1_0_sub_vrm1_1 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1_sub_vrm1_2 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_2_sub_vrm1_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_3_sub_vrm1_4 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_4_sub_vrm1_5 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_5_sub_vrm1_6 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm1_6_sub_vrm1_7 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_0_sub_vrm2_1 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      80, // sub_vrm2_1_sub_vrm2_2 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      80, // sub_vrm2_2_sub_vrm2_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
    },
    { // VRN8M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_16
      0,  // sub_32
      0,  // sub_gpr_even
      0,  // sub_gpr_odd
      81, // sub_vrm1_0 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_1 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_2 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_3 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_4 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_5 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_0
      0,  // sub_vrm2_1
      0,  // sub_vrm2_2
      0,  // sub_vrm2_3
      0,  // sub_vrm4_0
      0,  // sub_vrm4_1
      81, // sub_vrm1_0_sub_vrm1_1 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_1_sub_vrm1_2 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_2_sub_vrm1_3 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      81, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_3_sub_vrm1_4 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_4_sub_vrm1_5 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_5_sub_vrm1_6 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      81, // sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      0,  // sub_vrm2_0_sub_vrm2_1
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_1_sub_vrm2_2
      0,  // sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // sub_vrm2_2_sub_vrm2_3
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 52 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *RISCVGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[81][52] = {
    { // FPR16
      0,  // FPR16:sub_16
      0,  // FPR16:sub_32
      0,  // FPR16:sub_gpr_even
      0,  // FPR16:sub_gpr_odd
      0,  // FPR16:sub_vrm1_0
      0,  // FPR16:sub_vrm1_1
      0,  // FPR16:sub_vrm1_2
      0,  // FPR16:sub_vrm1_3
      0,  // FPR16:sub_vrm1_4
      0,  // FPR16:sub_vrm1_5
      0,  // FPR16:sub_vrm1_6
      0,  // FPR16:sub_vrm1_7
      0,  // FPR16:sub_vrm2_0
      0,  // FPR16:sub_vrm2_1
      0,  // FPR16:sub_vrm2_2
      0,  // FPR16:sub_vrm2_3
      0,  // FPR16:sub_vrm4_0
      0,  // FPR16:sub_vrm4_1
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR16:sub_vrm1_1_sub_vrm1_2
      0,  // FPR16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR16:sub_vrm1_2_sub_vrm1_3
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm1_3_sub_vrm1_4
      0,  // FPR16:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR16:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR16:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm1_4_sub_vrm1_5
      0,  // FPR16:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR16:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm1_5_sub_vrm1_6
      0,  // FPR16:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm1_6_sub_vrm1_7
      0,  // FPR16:sub_vrm2_0_sub_vrm2_1
      0,  // FPR16:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // FPR16:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR16:sub_vrm2_1_sub_vrm2_2
      0,  // FPR16:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR16:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRAll
      0,  // GPRAll:sub_16
      0,  // GPRAll:sub_32
      0,  // GPRAll:sub_gpr_even
      0,  // GPRAll:sub_gpr_odd
      0,  // GPRAll:sub_vrm1_0
      0,  // GPRAll:sub_vrm1_1
      0,  // GPRAll:sub_vrm1_2
      0,  // GPRAll:sub_vrm1_3
      0,  // GPRAll:sub_vrm1_4
      0,  // GPRAll:sub_vrm1_5
      0,  // GPRAll:sub_vrm1_6
      0,  // GPRAll:sub_vrm1_7
      0,  // GPRAll:sub_vrm2_0
      0,  // GPRAll:sub_vrm2_1
      0,  // GPRAll:sub_vrm2_2
      0,  // GPRAll:sub_vrm2_3
      0,  // GPRAll:sub_vrm4_0
      0,  // GPRAll:sub_vrm4_1
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRAll:sub_vrm1_1_sub_vrm1_2
      0,  // GPRAll:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRAll:sub_vrm1_2_sub_vrm1_3
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRAll:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRAll:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRAll:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRAll:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRAll:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRAll:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRAll:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm1_3_sub_vrm1_4
      0,  // GPRAll:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRAll:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRAll:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm1_4_sub_vrm1_5
      0,  // GPRAll:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRAll:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm1_5_sub_vrm1_6
      0,  // GPRAll:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm1_6_sub_vrm1_7
      0,  // GPRAll:sub_vrm2_0_sub_vrm2_1
      0,  // GPRAll:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRAll:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRAll:sub_vrm2_1_sub_vrm2_2
      0,  // GPRAll:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRAll:sub_vrm2_2_sub_vrm2_3
    },
    { // FPR32
      1,  // FPR32:sub_16 -> FPR16
      0,  // FPR32:sub_32
      0,  // FPR32:sub_gpr_even
      0,  // FPR32:sub_gpr_odd
      0,  // FPR32:sub_vrm1_0
      0,  // FPR32:sub_vrm1_1
      0,  // FPR32:sub_vrm1_2
      0,  // FPR32:sub_vrm1_3
      0,  // FPR32:sub_vrm1_4
      0,  // FPR32:sub_vrm1_5
      0,  // FPR32:sub_vrm1_6
      0,  // FPR32:sub_vrm1_7
      0,  // FPR32:sub_vrm2_0
      0,  // FPR32:sub_vrm2_1
      0,  // FPR32:sub_vrm2_2
      0,  // FPR32:sub_vrm2_3
      0,  // FPR32:sub_vrm4_0
      0,  // FPR32:sub_vrm4_1
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR32:sub_vrm1_1_sub_vrm1_2
      0,  // FPR32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR32:sub_vrm1_2_sub_vrm1_3
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm1_3_sub_vrm1_4
      0,  // FPR32:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm1_4_sub_vrm1_5
      0,  // FPR32:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm1_5_sub_vrm1_6
      0,  // FPR32:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm1_6_sub_vrm1_7
      0,  // FPR32:sub_vrm2_0_sub_vrm2_1
      0,  // FPR32:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // FPR32:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR32:sub_vrm2_1_sub_vrm2_2
      0,  // FPR32:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR32:sub_vrm2_2_sub_vrm2_3
    },
    { // GPR
      0,  // GPR:sub_16
      0,  // GPR:sub_32
      0,  // GPR:sub_gpr_even
      0,  // GPR:sub_gpr_odd
      0,  // GPR:sub_vrm1_0
      0,  // GPR:sub_vrm1_1
      0,  // GPR:sub_vrm1_2
      0,  // GPR:sub_vrm1_3
      0,  // GPR:sub_vrm1_4
      0,  // GPR:sub_vrm1_5
      0,  // GPR:sub_vrm1_6
      0,  // GPR:sub_vrm1_7
      0,  // GPR:sub_vrm2_0
      0,  // GPR:sub_vrm2_1
      0,  // GPR:sub_vrm2_2
      0,  // GPR:sub_vrm2_3
      0,  // GPR:sub_vrm4_0
      0,  // GPR:sub_vrm4_1
      0,  // GPR:sub_vrm1_0_sub_vrm1_1
      0,  // GPR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPR:sub_vrm1_1_sub_vrm1_2
      0,  // GPR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPR:sub_vrm1_2_sub_vrm1_3
      0,  // GPR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm1_3_sub_vrm1_4
      0,  // GPR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm1_4_sub_vrm1_5
      0,  // GPR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm1_5_sub_vrm1_6
      0,  // GPR:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm1_6_sub_vrm1_7
      0,  // GPR:sub_vrm2_0_sub_vrm2_1
      0,  // GPR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPR:sub_vrm2_1_sub_vrm2_2
      0,  // GPR:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPR:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRF16
      0,  // GPRF16:sub_16
      0,  // GPRF16:sub_32
      0,  // GPRF16:sub_gpr_even
      0,  // GPRF16:sub_gpr_odd
      0,  // GPRF16:sub_vrm1_0
      0,  // GPRF16:sub_vrm1_1
      0,  // GPRF16:sub_vrm1_2
      0,  // GPRF16:sub_vrm1_3
      0,  // GPRF16:sub_vrm1_4
      0,  // GPRF16:sub_vrm1_5
      0,  // GPRF16:sub_vrm1_6
      0,  // GPRF16:sub_vrm1_7
      0,  // GPRF16:sub_vrm2_0
      0,  // GPRF16:sub_vrm2_1
      0,  // GPRF16:sub_vrm2_2
      0,  // GPRF16:sub_vrm2_3
      0,  // GPRF16:sub_vrm4_0
      0,  // GPRF16:sub_vrm4_1
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRF16:sub_vrm1_1_sub_vrm1_2
      0,  // GPRF16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRF16:sub_vrm1_2_sub_vrm1_3
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF16:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRF16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF16:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRF16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF16:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm1_3_sub_vrm1_4
      0,  // GPRF16:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF16:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF16:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm1_4_sub_vrm1_5
      0,  // GPRF16:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF16:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm1_5_sub_vrm1_6
      0,  // GPRF16:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm1_6_sub_vrm1_7
      0,  // GPRF16:sub_vrm2_0_sub_vrm2_1
      0,  // GPRF16:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRF16:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRF16:sub_vrm2_1_sub_vrm2_2
      0,  // GPRF16:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRF16:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRF32
      0,  // GPRF32:sub_16
      0,  // GPRF32:sub_32
      0,  // GPRF32:sub_gpr_even
      0,  // GPRF32:sub_gpr_odd
      0,  // GPRF32:sub_vrm1_0
      0,  // GPRF32:sub_vrm1_1
      0,  // GPRF32:sub_vrm1_2
      0,  // GPRF32:sub_vrm1_3
      0,  // GPRF32:sub_vrm1_4
      0,  // GPRF32:sub_vrm1_5
      0,  // GPRF32:sub_vrm1_6
      0,  // GPRF32:sub_vrm1_7
      0,  // GPRF32:sub_vrm2_0
      0,  // GPRF32:sub_vrm2_1
      0,  // GPRF32:sub_vrm2_2
      0,  // GPRF32:sub_vrm2_3
      0,  // GPRF32:sub_vrm4_0
      0,  // GPRF32:sub_vrm4_1
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRF32:sub_vrm1_1_sub_vrm1_2
      0,  // GPRF32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRF32:sub_vrm1_2_sub_vrm1_3
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF32:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRF32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF32:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRF32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF32:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm1_3_sub_vrm1_4
      0,  // GPRF32:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRF32:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF32:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm1_4_sub_vrm1_5
      0,  // GPRF32:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRF32:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm1_5_sub_vrm1_6
      0,  // GPRF32:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm1_6_sub_vrm1_7
      0,  // GPRF32:sub_vrm2_0_sub_vrm2_1
      0,  // GPRF32:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRF32:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRF32:sub_vrm2_1_sub_vrm2_2
      0,  // GPRF32:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRF32:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRNoX0
      0,  // GPRNoX0:sub_16
      0,  // GPRNoX0:sub_32
      0,  // GPRNoX0:sub_gpr_even
      0,  // GPRNoX0:sub_gpr_odd
      0,  // GPRNoX0:sub_vrm1_0
      0,  // GPRNoX0:sub_vrm1_1
      0,  // GPRNoX0:sub_vrm1_2
      0,  // GPRNoX0:sub_vrm1_3
      0,  // GPRNoX0:sub_vrm1_4
      0,  // GPRNoX0:sub_vrm1_5
      0,  // GPRNoX0:sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_7
      0,  // GPRNoX0:sub_vrm2_0
      0,  // GPRNoX0:sub_vrm2_1
      0,  // GPRNoX0:sub_vrm2_2
      0,  // GPRNoX0:sub_vrm2_3
      0,  // GPRNoX0:sub_vrm4_0
      0,  // GPRNoX0:sub_vrm4_1
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRNoX0:sub_vrm1_1_sub_vrm1_2
      0,  // GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRNoX0:sub_vrm1_2_sub_vrm1_3
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0:sub_vrm2_0_sub_vrm2_1
      0,  // GPRNoX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRNoX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRNoX0:sub_vrm2_1_sub_vrm2_2
      0,  // GPRNoX0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRNoX0:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRNoX0X2
      0,  // GPRNoX0X2:sub_16
      0,  // GPRNoX0X2:sub_32
      0,  // GPRNoX0X2:sub_gpr_even
      0,  // GPRNoX0X2:sub_gpr_odd
      0,  // GPRNoX0X2:sub_vrm1_0
      0,  // GPRNoX0X2:sub_vrm1_1
      0,  // GPRNoX0X2:sub_vrm1_2
      0,  // GPRNoX0X2:sub_vrm1_3
      0,  // GPRNoX0X2:sub_vrm1_4
      0,  // GPRNoX0X2:sub_vrm1_5
      0,  // GPRNoX0X2:sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm2_0
      0,  // GPRNoX0X2:sub_vrm2_1
      0,  // GPRNoX0X2:sub_vrm2_2
      0,  // GPRNoX0X2:sub_vrm2_3
      0,  // GPRNoX0X2:sub_vrm4_0
      0,  // GPRNoX0X2:sub_vrm4_1
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRNoX0X2:sub_vrm1_1_sub_vrm1_2
      0,  // GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRNoX0X2:sub_vrm1_2_sub_vrm1_3
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm1_3_sub_vrm1_4
      0,  // GPRNoX0X2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0X2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm1_4_sub_vrm1_5
      0,  // GPRNoX0X2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm1_5_sub_vrm1_6
      0,  // GPRNoX0X2:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm1_6_sub_vrm1_7
      0,  // GPRNoX0X2:sub_vrm2_0_sub_vrm2_1
      0,  // GPRNoX0X2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRNoX0X2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRNoX0X2:sub_vrm2_1_sub_vrm2_2
      0,  // GPRNoX0X2:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRNoX0X2:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRJALR
      0,  // GPRJALR:sub_16
      0,  // GPRJALR:sub_32
      0,  // GPRJALR:sub_gpr_even
      0,  // GPRJALR:sub_gpr_odd
      0,  // GPRJALR:sub_vrm1_0
      0,  // GPRJALR:sub_vrm1_1
      0,  // GPRJALR:sub_vrm1_2
      0,  // GPRJALR:sub_vrm1_3
      0,  // GPRJALR:sub_vrm1_4
      0,  // GPRJALR:sub_vrm1_5
      0,  // GPRJALR:sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_7
      0,  // GPRJALR:sub_vrm2_0
      0,  // GPRJALR:sub_vrm2_1
      0,  // GPRJALR:sub_vrm2_2
      0,  // GPRJALR:sub_vrm2_3
      0,  // GPRJALR:sub_vrm4_0
      0,  // GPRJALR:sub_vrm4_1
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRJALR:sub_vrm1_1_sub_vrm1_2
      0,  // GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRJALR:sub_vrm1_2_sub_vrm1_3
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm1_3_sub_vrm1_4
      0,  // GPRJALR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRJALR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm1_4_sub_vrm1_5
      0,  // GPRJALR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm1_5_sub_vrm1_6
      0,  // GPRJALR:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm1_6_sub_vrm1_7
      0,  // GPRJALR:sub_vrm2_0_sub_vrm2_1
      0,  // GPRJALR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRJALR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRJALR:sub_vrm2_1_sub_vrm2_2
      0,  // GPRJALR:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRJALR:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRTC
      0,  // GPRTC:sub_16
      0,  // GPRTC:sub_32
      0,  // GPRTC:sub_gpr_even
      0,  // GPRTC:sub_gpr_odd
      0,  // GPRTC:sub_vrm1_0
      0,  // GPRTC:sub_vrm1_1
      0,  // GPRTC:sub_vrm1_2
      0,  // GPRTC:sub_vrm1_3
      0,  // GPRTC:sub_vrm1_4
      0,  // GPRTC:sub_vrm1_5
      0,  // GPRTC:sub_vrm1_6
      0,  // GPRTC:sub_vrm1_7
      0,  // GPRTC:sub_vrm2_0
      0,  // GPRTC:sub_vrm2_1
      0,  // GPRTC:sub_vrm2_2
      0,  // GPRTC:sub_vrm2_3
      0,  // GPRTC:sub_vrm4_0
      0,  // GPRTC:sub_vrm4_1
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRTC:sub_vrm1_1_sub_vrm1_2
      0,  // GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRTC:sub_vrm1_2_sub_vrm1_3
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm1_3_sub_vrm1_4
      0,  // GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm1_4_sub_vrm1_5
      0,  // GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm1_5_sub_vrm1_6
      0,  // GPRTC:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm1_6_sub_vrm1_7
      0,  // GPRTC:sub_vrm2_0_sub_vrm2_1
      0,  // GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRTC:sub_vrm2_1_sub_vrm2_2
      0,  // GPRTC:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRTC:sub_vrm2_2_sub_vrm2_3
    },
    { // FPR32C
      1,  // FPR32C:sub_16 -> FPR16
      0,  // FPR32C:sub_32
      0,  // FPR32C:sub_gpr_even
      0,  // FPR32C:sub_gpr_odd
      0,  // FPR32C:sub_vrm1_0
      0,  // FPR32C:sub_vrm1_1
      0,  // FPR32C:sub_vrm1_2
      0,  // FPR32C:sub_vrm1_3
      0,  // FPR32C:sub_vrm1_4
      0,  // FPR32C:sub_vrm1_5
      0,  // FPR32C:sub_vrm1_6
      0,  // FPR32C:sub_vrm1_7
      0,  // FPR32C:sub_vrm2_0
      0,  // FPR32C:sub_vrm2_1
      0,  // FPR32C:sub_vrm2_2
      0,  // FPR32C:sub_vrm2_3
      0,  // FPR32C:sub_vrm4_0
      0,  // FPR32C:sub_vrm4_1
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR32C:sub_vrm1_1_sub_vrm1_2
      0,  // FPR32C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR32C:sub_vrm1_2_sub_vrm1_3
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR32C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR32C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm1_3_sub_vrm1_4
      0,  // FPR32C:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR32C:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32C:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm1_4_sub_vrm1_5
      0,  // FPR32C:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR32C:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm1_5_sub_vrm1_6
      0,  // FPR32C:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm1_6_sub_vrm1_7
      0,  // FPR32C:sub_vrm2_0_sub_vrm2_1
      0,  // FPR32C:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // FPR32C:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR32C:sub_vrm2_1_sub_vrm2_2
      0,  // FPR32C:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR32C:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRC
      0,  // GPRC:sub_16
      0,  // GPRC:sub_32
      0,  // GPRC:sub_gpr_even
      0,  // GPRC:sub_gpr_odd
      0,  // GPRC:sub_vrm1_0
      0,  // GPRC:sub_vrm1_1
      0,  // GPRC:sub_vrm1_2
      0,  // GPRC:sub_vrm1_3
      0,  // GPRC:sub_vrm1_4
      0,  // GPRC:sub_vrm1_5
      0,  // GPRC:sub_vrm1_6
      0,  // GPRC:sub_vrm1_7
      0,  // GPRC:sub_vrm2_0
      0,  // GPRC:sub_vrm2_1
      0,  // GPRC:sub_vrm2_2
      0,  // GPRC:sub_vrm2_3
      0,  // GPRC:sub_vrm4_0
      0,  // GPRC:sub_vrm4_1
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRC:sub_vrm1_1_sub_vrm1_2
      0,  // GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRC:sub_vrm1_2_sub_vrm1_3
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm1_3_sub_vrm1_4
      0,  // GPRC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm1_4_sub_vrm1_5
      0,  // GPRC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm1_5_sub_vrm1_6
      0,  // GPRC:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm1_6_sub_vrm1_7
      0,  // GPRC:sub_vrm2_0_sub_vrm2_1
      0,  // GPRC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRC:sub_vrm2_1_sub_vrm2_2
      0,  // GPRC:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRC:sub_vrm2_2_sub_vrm2_3
    },
    { // SR07
      0,  // SR07:sub_16
      0,  // SR07:sub_32
      0,  // SR07:sub_gpr_even
      0,  // SR07:sub_gpr_odd
      0,  // SR07:sub_vrm1_0
      0,  // SR07:sub_vrm1_1
      0,  // SR07:sub_vrm1_2
      0,  // SR07:sub_vrm1_3
      0,  // SR07:sub_vrm1_4
      0,  // SR07:sub_vrm1_5
      0,  // SR07:sub_vrm1_6
      0,  // SR07:sub_vrm1_7
      0,  // SR07:sub_vrm2_0
      0,  // SR07:sub_vrm2_1
      0,  // SR07:sub_vrm2_2
      0,  // SR07:sub_vrm2_3
      0,  // SR07:sub_vrm4_0
      0,  // SR07:sub_vrm4_1
      0,  // SR07:sub_vrm1_0_sub_vrm1_1
      0,  // SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // SR07:sub_vrm1_1_sub_vrm1_2
      0,  // SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // SR07:sub_vrm1_2_sub_vrm1_3
      0,  // SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm1_3_sub_vrm1_4
      0,  // SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm1_4_sub_vrm1_5
      0,  // SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm1_5_sub_vrm1_6
      0,  // SR07:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm1_6_sub_vrm1_7
      0,  // SR07:sub_vrm2_0_sub_vrm2_1
      0,  // SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // SR07:sub_vrm2_1_sub_vrm2_2
      0,  // SR07:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // SR07:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRC_and_GPRTC
      0,  // GPRC_and_GPRTC:sub_16
      0,  // GPRC_and_GPRTC:sub_32
      0,  // GPRC_and_GPRTC:sub_gpr_even
      0,  // GPRC_and_GPRTC:sub_gpr_odd
      0,  // GPRC_and_GPRTC:sub_vrm1_0
      0,  // GPRC_and_GPRTC:sub_vrm1_1
      0,  // GPRC_and_GPRTC:sub_vrm1_2
      0,  // GPRC_and_GPRTC:sub_vrm1_3
      0,  // GPRC_and_GPRTC:sub_vrm1_4
      0,  // GPRC_and_GPRTC:sub_vrm1_5
      0,  // GPRC_and_GPRTC:sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm2_0
      0,  // GPRC_and_GPRTC:sub_vrm2_1
      0,  // GPRC_and_GPRTC:sub_vrm2_2
      0,  // GPRC_and_GPRTC:sub_vrm2_3
      0,  // GPRC_and_GPRTC:sub_vrm4_0
      0,  // GPRC_and_GPRTC:sub_vrm4_1
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2
      0,  // GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_GPRTC:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_GPRTC:sub_vrm2_0_sub_vrm2_1
      0,  // GPRC_and_GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRC_and_GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRC_and_GPRTC:sub_vrm2_1_sub_vrm2_2
      0,  // GPRC_and_GPRTC:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRC_and_GPRTC:sub_vrm2_2_sub_vrm2_3
    },
    { // VCSR
      0,  // VCSR:sub_16
      0,  // VCSR:sub_32
      0,  // VCSR:sub_gpr_even
      0,  // VCSR:sub_gpr_odd
      0,  // VCSR:sub_vrm1_0
      0,  // VCSR:sub_vrm1_1
      0,  // VCSR:sub_vrm1_2
      0,  // VCSR:sub_vrm1_3
      0,  // VCSR:sub_vrm1_4
      0,  // VCSR:sub_vrm1_5
      0,  // VCSR:sub_vrm1_6
      0,  // VCSR:sub_vrm1_7
      0,  // VCSR:sub_vrm2_0
      0,  // VCSR:sub_vrm2_1
      0,  // VCSR:sub_vrm2_2
      0,  // VCSR:sub_vrm2_3
      0,  // VCSR:sub_vrm4_0
      0,  // VCSR:sub_vrm4_1
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VCSR:sub_vrm1_1_sub_vrm1_2
      0,  // VCSR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VCSR:sub_vrm1_2_sub_vrm1_3
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VCSR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VCSR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VCSR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VCSR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VCSR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VCSR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VCSR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm1_3_sub_vrm1_4
      0,  // VCSR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VCSR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VCSR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm1_4_sub_vrm1_5
      0,  // VCSR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VCSR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm1_5_sub_vrm1_6
      0,  // VCSR:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm1_6_sub_vrm1_7
      0,  // VCSR:sub_vrm2_0_sub_vrm2_1
      0,  // VCSR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VCSR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VCSR:sub_vrm2_1_sub_vrm2_2
      0,  // VCSR:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VCSR:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRC_and_SR07
      0,  // GPRC_and_SR07:sub_16
      0,  // GPRC_and_SR07:sub_32
      0,  // GPRC_and_SR07:sub_gpr_even
      0,  // GPRC_and_SR07:sub_gpr_odd
      0,  // GPRC_and_SR07:sub_vrm1_0
      0,  // GPRC_and_SR07:sub_vrm1_1
      0,  // GPRC_and_SR07:sub_vrm1_2
      0,  // GPRC_and_SR07:sub_vrm1_3
      0,  // GPRC_and_SR07:sub_vrm1_4
      0,  // GPRC_and_SR07:sub_vrm1_5
      0,  // GPRC_and_SR07:sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm2_0
      0,  // GPRC_and_SR07:sub_vrm2_1
      0,  // GPRC_and_SR07:sub_vrm2_2
      0,  // GPRC_and_SR07:sub_vrm2_3
      0,  // GPRC_and_SR07:sub_vrm4_0
      0,  // GPRC_and_SR07:sub_vrm4_1
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2
      0,  // GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4
      0,  // GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm1_4_sub_vrm1_5
      0,  // GPRC_and_SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm1_5_sub_vrm1_6
      0,  // GPRC_and_SR07:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm1_6_sub_vrm1_7
      0,  // GPRC_and_SR07:sub_vrm2_0_sub_vrm2_1
      0,  // GPRC_and_SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRC_and_SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRC_and_SR07:sub_vrm2_1_sub_vrm2_2
      0,  // GPRC_and_SR07:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRC_and_SR07:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX1X5
      0,  // GPRX1X5:sub_16
      0,  // GPRX1X5:sub_32
      0,  // GPRX1X5:sub_gpr_even
      0,  // GPRX1X5:sub_gpr_odd
      0,  // GPRX1X5:sub_vrm1_0
      0,  // GPRX1X5:sub_vrm1_1
      0,  // GPRX1X5:sub_vrm1_2
      0,  // GPRX1X5:sub_vrm1_3
      0,  // GPRX1X5:sub_vrm1_4
      0,  // GPRX1X5:sub_vrm1_5
      0,  // GPRX1X5:sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_7
      0,  // GPRX1X5:sub_vrm2_0
      0,  // GPRX1X5:sub_vrm2_1
      0,  // GPRX1X5:sub_vrm2_2
      0,  // GPRX1X5:sub_vrm2_3
      0,  // GPRX1X5:sub_vrm4_0
      0,  // GPRX1X5:sub_vrm4_1
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX1X5:sub_vrm1_1_sub_vrm1_2
      0,  // GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX1X5:sub_vrm1_2_sub_vrm1_3
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1X5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1X5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1X5:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1X5:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1X5:sub_vrm2_0_sub_vrm2_1
      0,  // GPRX1X5:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRX1X5:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX1X5:sub_vrm2_1_sub_vrm2_2
      0,  // GPRX1X5:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX1X5:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX0
      0,  // GPRX0:sub_16
      0,  // GPRX0:sub_32
      0,  // GPRX0:sub_gpr_even
      0,  // GPRX0:sub_gpr_odd
      0,  // GPRX0:sub_vrm1_0
      0,  // GPRX0:sub_vrm1_1
      0,  // GPRX0:sub_vrm1_2
      0,  // GPRX0:sub_vrm1_3
      0,  // GPRX0:sub_vrm1_4
      0,  // GPRX0:sub_vrm1_5
      0,  // GPRX0:sub_vrm1_6
      0,  // GPRX0:sub_vrm1_7
      0,  // GPRX0:sub_vrm2_0
      0,  // GPRX0:sub_vrm2_1
      0,  // GPRX0:sub_vrm2_2
      0,  // GPRX0:sub_vrm2_3
      0,  // GPRX0:sub_vrm4_0
      0,  // GPRX0:sub_vrm4_1
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX0:sub_vrm1_1_sub_vrm1_2
      0,  // GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX0:sub_vrm1_2_sub_vrm1_3
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm1_3_sub_vrm1_4
      0,  // GPRX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm1_4_sub_vrm1_5
      0,  // GPRX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm1_5_sub_vrm1_6
      0,  // GPRX0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm1_6_sub_vrm1_7
      0,  // GPRX0:sub_vrm2_0_sub_vrm2_1
      0,  // GPRX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX0:sub_vrm2_1_sub_vrm2_2
      0,  // GPRX0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX0:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX1
      0,  // GPRX1:sub_16
      0,  // GPRX1:sub_32
      0,  // GPRX1:sub_gpr_even
      0,  // GPRX1:sub_gpr_odd
      0,  // GPRX1:sub_vrm1_0
      0,  // GPRX1:sub_vrm1_1
      0,  // GPRX1:sub_vrm1_2
      0,  // GPRX1:sub_vrm1_3
      0,  // GPRX1:sub_vrm1_4
      0,  // GPRX1:sub_vrm1_5
      0,  // GPRX1:sub_vrm1_6
      0,  // GPRX1:sub_vrm1_7
      0,  // GPRX1:sub_vrm2_0
      0,  // GPRX1:sub_vrm2_1
      0,  // GPRX1:sub_vrm2_2
      0,  // GPRX1:sub_vrm2_3
      0,  // GPRX1:sub_vrm4_0
      0,  // GPRX1:sub_vrm4_1
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX1:sub_vrm1_1_sub_vrm1_2
      0,  // GPRX1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX1:sub_vrm1_2_sub_vrm1_3
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm1_3_sub_vrm1_4
      0,  // GPRX1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm1_4_sub_vrm1_5
      0,  // GPRX1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm1_5_sub_vrm1_6
      0,  // GPRX1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm1_6_sub_vrm1_7
      0,  // GPRX1:sub_vrm2_0_sub_vrm2_1
      0,  // GPRX1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRX1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX1:sub_vrm2_1_sub_vrm2_2
      0,  // GPRX1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX1:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRX5
      0,  // GPRX5:sub_16
      0,  // GPRX5:sub_32
      0,  // GPRX5:sub_gpr_even
      0,  // GPRX5:sub_gpr_odd
      0,  // GPRX5:sub_vrm1_0
      0,  // GPRX5:sub_vrm1_1
      0,  // GPRX5:sub_vrm1_2
      0,  // GPRX5:sub_vrm1_3
      0,  // GPRX5:sub_vrm1_4
      0,  // GPRX5:sub_vrm1_5
      0,  // GPRX5:sub_vrm1_6
      0,  // GPRX5:sub_vrm1_7
      0,  // GPRX5:sub_vrm2_0
      0,  // GPRX5:sub_vrm2_1
      0,  // GPRX5:sub_vrm2_2
      0,  // GPRX5:sub_vrm2_3
      0,  // GPRX5:sub_vrm4_0
      0,  // GPRX5:sub_vrm4_1
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX5:sub_vrm1_1_sub_vrm1_2
      0,  // GPRX5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRX5:sub_vrm1_2_sub_vrm1_3
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRX5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm1_3_sub_vrm1_4
      0,  // GPRX5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRX5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm1_4_sub_vrm1_5
      0,  // GPRX5:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRX5:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm1_5_sub_vrm1_6
      0,  // GPRX5:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm1_6_sub_vrm1_7
      0,  // GPRX5:sub_vrm2_0_sub_vrm2_1
      0,  // GPRX5:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRX5:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX5:sub_vrm2_1_sub_vrm2_2
      0,  // GPRX5:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRX5:sub_vrm2_2_sub_vrm2_3
    },
    { // SP
      0,  // SP:sub_16
      0,  // SP:sub_32
      0,  // SP:sub_gpr_even
      0,  // SP:sub_gpr_odd
      0,  // SP:sub_vrm1_0
      0,  // SP:sub_vrm1_1
      0,  // SP:sub_vrm1_2
      0,  // SP:sub_vrm1_3
      0,  // SP:sub_vrm1_4
      0,  // SP:sub_vrm1_5
      0,  // SP:sub_vrm1_6
      0,  // SP:sub_vrm1_7
      0,  // SP:sub_vrm2_0
      0,  // SP:sub_vrm2_1
      0,  // SP:sub_vrm2_2
      0,  // SP:sub_vrm2_3
      0,  // SP:sub_vrm4_0
      0,  // SP:sub_vrm4_1
      0,  // SP:sub_vrm1_0_sub_vrm1_1
      0,  // SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // SP:sub_vrm1_1_sub_vrm1_2
      0,  // SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // SP:sub_vrm1_2_sub_vrm1_3
      0,  // SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm1_3_sub_vrm1_4
      0,  // SP:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // SP:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SP:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm1_4_sub_vrm1_5
      0,  // SP:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // SP:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm1_5_sub_vrm1_6
      0,  // SP:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm1_6_sub_vrm1_7
      0,  // SP:sub_vrm2_0_sub_vrm2_1
      0,  // SP:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // SP:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // SP:sub_vrm2_1_sub_vrm2_2
      0,  // SP:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // SP:sub_vrm2_2_sub_vrm2_3
    },
    { // FPR64
      1,  // FPR64:sub_16 -> FPR16
      3,  // FPR64:sub_32 -> FPR32
      0,  // FPR64:sub_gpr_even
      0,  // FPR64:sub_gpr_odd
      0,  // FPR64:sub_vrm1_0
      0,  // FPR64:sub_vrm1_1
      0,  // FPR64:sub_vrm1_2
      0,  // FPR64:sub_vrm1_3
      0,  // FPR64:sub_vrm1_4
      0,  // FPR64:sub_vrm1_5
      0,  // FPR64:sub_vrm1_6
      0,  // FPR64:sub_vrm1_7
      0,  // FPR64:sub_vrm2_0
      0,  // FPR64:sub_vrm2_1
      0,  // FPR64:sub_vrm2_2
      0,  // FPR64:sub_vrm2_3
      0,  // FPR64:sub_vrm4_0
      0,  // FPR64:sub_vrm4_1
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR64:sub_vrm1_1_sub_vrm1_2
      0,  // FPR64:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR64:sub_vrm1_2_sub_vrm1_3
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR64:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR64:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm1_3_sub_vrm1_4
      0,  // FPR64:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm1_4_sub_vrm1_5
      0,  // FPR64:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm1_5_sub_vrm1_6
      0,  // FPR64:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm1_6_sub_vrm1_7
      0,  // FPR64:sub_vrm2_0_sub_vrm2_1
      0,  // FPR64:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // FPR64:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR64:sub_vrm2_1_sub_vrm2_2
      0,  // FPR64:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR64:sub_vrm2_2_sub_vrm2_3
    },
    { // VM
      0,  // VM:sub_16
      0,  // VM:sub_32
      0,  // VM:sub_gpr_even
      0,  // VM:sub_gpr_odd
      0,  // VM:sub_vrm1_0
      0,  // VM:sub_vrm1_1
      0,  // VM:sub_vrm1_2
      0,  // VM:sub_vrm1_3
      0,  // VM:sub_vrm1_4
      0,  // VM:sub_vrm1_5
      0,  // VM:sub_vrm1_6
      0,  // VM:sub_vrm1_7
      0,  // VM:sub_vrm2_0
      0,  // VM:sub_vrm2_1
      0,  // VM:sub_vrm2_2
      0,  // VM:sub_vrm2_3
      0,  // VM:sub_vrm4_0
      0,  // VM:sub_vrm4_1
      0,  // VM:sub_vrm1_0_sub_vrm1_1
      0,  // VM:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VM:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VM:sub_vrm1_1_sub_vrm1_2
      0,  // VM:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VM:sub_vrm1_2_sub_vrm1_3
      0,  // VM:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VM:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VM:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VM:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VM:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VM:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VM:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VM:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VM:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VM:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm1_3_sub_vrm1_4
      0,  // VM:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VM:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VM:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm1_4_sub_vrm1_5
      0,  // VM:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VM:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm1_5_sub_vrm1_6
      0,  // VM:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm1_6_sub_vrm1_7
      0,  // VM:sub_vrm2_0_sub_vrm2_1
      0,  // VM:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VM:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VM:sub_vrm2_1_sub_vrm2_2
      0,  // VM:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VM:sub_vrm2_2_sub_vrm2_3
    },
    { // VR
      0,  // VR:sub_16
      0,  // VR:sub_32
      0,  // VR:sub_gpr_even
      0,  // VR:sub_gpr_odd
      0,  // VR:sub_vrm1_0
      0,  // VR:sub_vrm1_1
      0,  // VR:sub_vrm1_2
      0,  // VR:sub_vrm1_3
      0,  // VR:sub_vrm1_4
      0,  // VR:sub_vrm1_5
      0,  // VR:sub_vrm1_6
      0,  // VR:sub_vrm1_7
      0,  // VR:sub_vrm2_0
      0,  // VR:sub_vrm2_1
      0,  // VR:sub_vrm2_2
      0,  // VR:sub_vrm2_3
      0,  // VR:sub_vrm4_0
      0,  // VR:sub_vrm4_1
      0,  // VR:sub_vrm1_0_sub_vrm1_1
      0,  // VR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VR:sub_vrm1_1_sub_vrm1_2
      0,  // VR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VR:sub_vrm1_2_sub_vrm1_3
      0,  // VR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm1_3_sub_vrm1_4
      0,  // VR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm1_4_sub_vrm1_5
      0,  // VR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm1_5_sub_vrm1_6
      0,  // VR:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm1_6_sub_vrm1_7
      0,  // VR:sub_vrm2_0_sub_vrm2_1
      0,  // VR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VR:sub_vrm2_1_sub_vrm2_2
      0,  // VR:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VR:sub_vrm2_2_sub_vrm2_3
    },
    { // VRNoV0
      0,  // VRNoV0:sub_16
      0,  // VRNoV0:sub_32
      0,  // VRNoV0:sub_gpr_even
      0,  // VRNoV0:sub_gpr_odd
      0,  // VRNoV0:sub_vrm1_0
      0,  // VRNoV0:sub_vrm1_1
      0,  // VRNoV0:sub_vrm1_2
      0,  // VRNoV0:sub_vrm1_3
      0,  // VRNoV0:sub_vrm1_4
      0,  // VRNoV0:sub_vrm1_5
      0,  // VRNoV0:sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_7
      0,  // VRNoV0:sub_vrm2_0
      0,  // VRNoV0:sub_vrm2_1
      0,  // VRNoV0:sub_vrm2_2
      0,  // VRNoV0:sub_vrm2_3
      0,  // VRNoV0:sub_vrm4_0
      0,  // VRNoV0:sub_vrm4_1
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRNoV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRNoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRNoV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRNoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRNoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRNoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRNoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRNoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRNoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRNoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRNoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRNoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRNoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRNoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRNoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRNoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRNoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair
      0,  // GPRPair:sub_16
      0,  // GPRPair:sub_32
      6,  // GPRPair:sub_gpr_even -> GPRF32
      2,  // GPRPair:sub_gpr_odd -> GPRAll
      0,  // GPRPair:sub_vrm1_0
      0,  // GPRPair:sub_vrm1_1
      0,  // GPRPair:sub_vrm1_2
      0,  // GPRPair:sub_vrm1_3
      0,  // GPRPair:sub_vrm1_4
      0,  // GPRPair:sub_vrm1_5
      0,  // GPRPair:sub_vrm1_6
      0,  // GPRPair:sub_vrm1_7
      0,  // GPRPair:sub_vrm2_0
      0,  // GPRPair:sub_vrm2_1
      0,  // GPRPair:sub_vrm2_2
      0,  // GPRPair:sub_vrm2_3
      0,  // GPRPair:sub_vrm4_0
      0,  // GPRPair:sub_vrm4_1
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRNoX0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_32
      7,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_gpr_even -> GPRNoX0
      8,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_gpr_odd -> GPRNoX0X2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRNoX0X2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_32
      8,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_gpr_even -> GPRNoX0X2
      8,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_gpr_odd -> GPRNoX0X2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRNoX0X2:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRJALR
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_32
      9,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_gpr_even -> GPRJALR
      9,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_gpr_odd -> GPRJALR
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRJALR:sub_vrm2_2_sub_vrm2_3
    },
    { // FPR64C
      1,  // FPR64C:sub_16 -> FPR16
      11, // FPR64C:sub_32 -> FPR32C
      0,  // FPR64C:sub_gpr_even
      0,  // FPR64C:sub_gpr_odd
      0,  // FPR64C:sub_vrm1_0
      0,  // FPR64C:sub_vrm1_1
      0,  // FPR64C:sub_vrm1_2
      0,  // FPR64C:sub_vrm1_3
      0,  // FPR64C:sub_vrm1_4
      0,  // FPR64C:sub_vrm1_5
      0,  // FPR64C:sub_vrm1_6
      0,  // FPR64C:sub_vrm1_7
      0,  // FPR64C:sub_vrm2_0
      0,  // FPR64C:sub_vrm2_1
      0,  // FPR64C:sub_vrm2_2
      0,  // FPR64C:sub_vrm2_3
      0,  // FPR64C:sub_vrm4_0
      0,  // FPR64C:sub_vrm4_1
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR64C:sub_vrm1_1_sub_vrm1_2
      0,  // FPR64C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // FPR64C:sub_vrm1_2_sub_vrm1_3
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64C:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR64C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64C:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // FPR64C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64C:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm1_3_sub_vrm1_4
      0,  // FPR64C:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // FPR64C:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64C:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm1_4_sub_vrm1_5
      0,  // FPR64C:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // FPR64C:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm1_5_sub_vrm1_6
      0,  // FPR64C:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm1_6_sub_vrm1_7
      0,  // FPR64C:sub_vrm2_0_sub_vrm2_1
      0,  // FPR64C:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // FPR64C:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR64C:sub_vrm2_1_sub_vrm2_2
      0,  // FPR64C:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // FPR64C:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRTC
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_32
      10, // GPRPair_with_sub_gpr_even_in_GPRTC:sub_gpr_even -> GPRTC
      10, // GPRPair_with_sub_gpr_even_in_GPRTC:sub_gpr_odd -> GPRTC
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRTC:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRC
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_32
      12, // GPRPair_with_sub_gpr_even_in_GPRC:sub_gpr_even -> GPRC
      12, // GPRPair_with_sub_gpr_even_in_GPRC:sub_gpr_odd -> GPRC
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_SR07
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_32
      13, // GPRPair_with_sub_gpr_even_in_SR07:sub_gpr_even -> SR07
      13, // GPRPair_with_sub_gpr_even_in_SR07:sub_gpr_odd -> SR07
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_SR07:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_32
      14, // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_gpr_even -> GPRC_and_GPRTC
      14, // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_gpr_odd -> GPRC_and_GPRTC
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_32
      16, // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_gpr_even -> GPRC_and_SR07
      16, // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_gpr_odd -> GPRC_and_SR07
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_GPRX0
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_32
      18, // GPRPair_with_sub_gpr_even_in_GPRX0:sub_gpr_even -> GPRX0
      2,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_gpr_odd -> GPRAll
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_GPRX0:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_even_in_SP
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_16
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_32
      21, // GPRPair_with_sub_gpr_even_in_SP:sub_gpr_even -> SP
      8,  // GPRPair_with_sub_gpr_even_in_SP:sub_gpr_odd -> GPRNoX0X2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_even_in_SP:sub_vrm2_2_sub_vrm2_3
    },
    { // GPRPair_with_sub_gpr_odd_in_GPRX1X5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_16
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_32
      8,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_gpr_even -> GPRNoX0X2
      20, // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_gpr_odd -> GPRX5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_0
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm4_0
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm4_1
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1_sub_vrm1_2
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_2_sub_vrm1_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_3_sub_vrm1_4
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_4_sub_vrm1_5
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_5_sub_vrm1_6
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm1_6_sub_vrm1_7
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_0_sub_vrm2_1
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_1_sub_vrm2_2
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // GPRPair_with_sub_gpr_odd_in_GPRX1X5:sub_vrm2_2_sub_vrm2_3
    },
    { // VMV0
      0,  // VMV0:sub_16
      0,  // VMV0:sub_32
      0,  // VMV0:sub_gpr_even
      0,  // VMV0:sub_gpr_odd
      0,  // VMV0:sub_vrm1_0
      0,  // VMV0:sub_vrm1_1
      0,  // VMV0:sub_vrm1_2
      0,  // VMV0:sub_vrm1_3
      0,  // VMV0:sub_vrm1_4
      0,  // VMV0:sub_vrm1_5
      0,  // VMV0:sub_vrm1_6
      0,  // VMV0:sub_vrm1_7
      0,  // VMV0:sub_vrm2_0
      0,  // VMV0:sub_vrm2_1
      0,  // VMV0:sub_vrm2_2
      0,  // VMV0:sub_vrm2_3
      0,  // VMV0:sub_vrm4_0
      0,  // VMV0:sub_vrm4_1
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VMV0:sub_vrm1_1_sub_vrm1_2
      0,  // VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VMV0:sub_vrm1_2_sub_vrm1_3
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M1
      0,  // VRN2M1:sub_16
      0,  // VRN2M1:sub_32
      0,  // VRN2M1:sub_gpr_even
      0,  // VRN2M1:sub_gpr_odd
      24, // VRN2M1:sub_vrm1_0 -> VR
      25, // VRN2M1:sub_vrm1_1 -> VRNoV0
      0,  // VRN2M1:sub_vrm1_2
      0,  // VRN2M1:sub_vrm1_3
      0,  // VRN2M1:sub_vrm1_4
      0,  // VRN2M1:sub_vrm1_5
      0,  // VRN2M1:sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_7
      0,  // VRN2M1:sub_vrm2_0
      0,  // VRN2M1:sub_vrm2_1
      0,  // VRN2M1:sub_vrm2_2
      0,  // VRN2M1:sub_vrm2_3
      0,  // VRN2M1:sub_vrm4_0
      0,  // VRN2M1:sub_vrm4_1
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1:sub_vrm1_1_sub_vrm1_2
      0,  // VRN2M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1:sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN2M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M1NoV0
      0,  // VRN2M1NoV0:sub_16
      0,  // VRN2M1NoV0:sub_32
      0,  // VRN2M1NoV0:sub_gpr_even
      0,  // VRN2M1NoV0:sub_gpr_odd
      25, // VRN2M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN2M1NoV0:sub_vrm1_1 -> VRNoV0
      0,  // VRN2M1NoV0:sub_vrm1_2
      0,  // VRN2M1NoV0:sub_vrm1_3
      0,  // VRN2M1NoV0:sub_vrm1_4
      0,  // VRN2M1NoV0:sub_vrm1_5
      0,  // VRN2M1NoV0:sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm2_0
      0,  // VRN2M1NoV0:sub_vrm2_1
      0,  // VRN2M1NoV0:sub_vrm2_2
      0,  // VRN2M1NoV0:sub_vrm2_3
      0,  // VRN2M1NoV0:sub_vrm4_0
      0,  // VRN2M1NoV0:sub_vrm4_1
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1NoV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRN2M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1NoV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN2M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM2
      0,  // VRM2:sub_16
      0,  // VRM2:sub_32
      0,  // VRM2:sub_gpr_even
      0,  // VRM2:sub_gpr_odd
      24, // VRM2:sub_vrm1_0 -> VR
      25, // VRM2:sub_vrm1_1 -> VRNoV0
      0,  // VRM2:sub_vrm1_2
      0,  // VRM2:sub_vrm1_3
      0,  // VRM2:sub_vrm1_4
      0,  // VRM2:sub_vrm1_5
      0,  // VRM2:sub_vrm1_6
      0,  // VRM2:sub_vrm1_7
      0,  // VRM2:sub_vrm2_0
      0,  // VRM2:sub_vrm2_1
      0,  // VRM2:sub_vrm2_2
      0,  // VRM2:sub_vrm2_3
      0,  // VRM2:sub_vrm4_0
      0,  // VRM2:sub_vrm4_1
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM2:sub_vrm1_1_sub_vrm1_2
      0,  // VRM2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM2:sub_vrm1_2_sub_vrm1_3
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm1_3_sub_vrm1_4
      0,  // VRM2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm1_4_sub_vrm1_5
      0,  // VRM2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm1_5_sub_vrm1_6
      0,  // VRM2:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm1_6_sub_vrm1_7
      0,  // VRM2:sub_vrm2_0_sub_vrm2_1
      0,  // VRM2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM2:sub_vrm2_1_sub_vrm2_2
      0,  // VRM2:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM2:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM2NoV0
      0,  // VRM2NoV0:sub_16
      0,  // VRM2NoV0:sub_32
      0,  // VRM2NoV0:sub_gpr_even
      0,  // VRM2NoV0:sub_gpr_odd
      25, // VRM2NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRM2NoV0:sub_vrm1_1 -> VRNoV0
      0,  // VRM2NoV0:sub_vrm1_2
      0,  // VRM2NoV0:sub_vrm1_3
      0,  // VRM2NoV0:sub_vrm1_4
      0,  // VRM2NoV0:sub_vrm1_5
      0,  // VRM2NoV0:sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm2_0
      0,  // VRM2NoV0:sub_vrm2_1
      0,  // VRM2NoV0:sub_vrm2_2
      0,  // VRM2NoV0:sub_vrm2_3
      0,  // VRM2NoV0:sub_vrm4_0
      0,  // VRM2NoV0:sub_vrm4_1
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM2NoV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRM2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM2NoV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRM2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRM2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRM2NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRM2NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRM2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM2NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRM2NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM2NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM2_with_sub_vrm1_0_in_VMV0
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M1
      0,  // VRN3M1:sub_16
      0,  // VRN3M1:sub_32
      0,  // VRN3M1:sub_gpr_even
      0,  // VRN3M1:sub_gpr_odd
      24, // VRN3M1:sub_vrm1_0 -> VR
      25, // VRN3M1:sub_vrm1_1 -> VRNoV0
      25, // VRN3M1:sub_vrm1_2 -> VRNoV0
      0,  // VRN3M1:sub_vrm1_3
      0,  // VRN3M1:sub_vrm1_4
      0,  // VRN3M1:sub_vrm1_5
      0,  // VRN3M1:sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_7
      0,  // VRN3M1:sub_vrm2_0
      0,  // VRN3M1:sub_vrm2_1
      0,  // VRN3M1:sub_vrm2_2
      0,  // VRN3M1:sub_vrm2_3
      0,  // VRN3M1:sub_vrm4_0
      0,  // VRN3M1:sub_vrm4_1
      40, // VRN3M1:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      0,  // VRN3M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRN3M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      41, // VRN3M1:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      0,  // VRN3M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN3M1:sub_vrm1_2_sub_vrm1_3
      0,  // VRN3M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN3M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M1NoV0
      0,  // VRN3M1NoV0:sub_16
      0,  // VRN3M1NoV0:sub_32
      0,  // VRN3M1NoV0:sub_gpr_even
      0,  // VRN3M1NoV0:sub_gpr_odd
      25, // VRN3M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN3M1NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN3M1NoV0:sub_vrm1_2 -> VRNoV0
      0,  // VRN3M1NoV0:sub_vrm1_3
      0,  // VRN3M1NoV0:sub_vrm1_4
      0,  // VRN3M1NoV0:sub_vrm1_5
      0,  // VRN3M1NoV0:sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm2_0
      0,  // VRN3M1NoV0:sub_vrm2_1
      0,  // VRN3M1NoV0:sub_vrm2_2
      0,  // VRN3M1NoV0:sub_vrm2_3
      0,  // VRN3M1NoV0:sub_vrm4_0
      0,  // VRN3M1NoV0:sub_vrm4_1
      41, // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      0,  // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      41, // VRN3M1NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      0,  // VRN3M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN3M1NoV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN3M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      41, // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M1
      0,  // VRN4M1:sub_16
      0,  // VRN4M1:sub_32
      0,  // VRN4M1:sub_gpr_even
      0,  // VRN4M1:sub_gpr_odd
      24, // VRN4M1:sub_vrm1_0 -> VR
      25, // VRN4M1:sub_vrm1_1 -> VRNoV0
      25, // VRN4M1:sub_vrm1_2 -> VRNoV0
      25, // VRN4M1:sub_vrm1_3 -> VRNoV0
      0,  // VRN4M1:sub_vrm1_4
      0,  // VRN4M1:sub_vrm1_5
      0,  // VRN4M1:sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_7
      0,  // VRN4M1:sub_vrm2_0
      0,  // VRN4M1:sub_vrm2_1
      0,  // VRN4M1:sub_vrm2_2
      0,  // VRN4M1:sub_vrm2_3
      0,  // VRN4M1:sub_vrm4_0
      0,  // VRN4M1:sub_vrm4_1
      40, // VRN4M1:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN4M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      0,  // VRN4M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      41, // VRN4M1:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN4M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN4M1:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN4M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN4M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN4M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN4M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN4M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN4M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M1NoV0
      0,  // VRN4M1NoV0:sub_16
      0,  // VRN4M1NoV0:sub_32
      0,  // VRN4M1NoV0:sub_gpr_even
      0,  // VRN4M1NoV0:sub_gpr_odd
      25, // VRN4M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN4M1NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN4M1NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN4M1NoV0:sub_vrm1_3 -> VRNoV0
      0,  // VRN4M1NoV0:sub_vrm1_4
      0,  // VRN4M1NoV0:sub_vrm1_5
      0,  // VRN4M1NoV0:sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm2_0
      0,  // VRN4M1NoV0:sub_vrm2_1
      0,  // VRN4M1NoV0:sub_vrm2_2
      0,  // VRN4M1NoV0:sub_vrm2_3
      0,  // VRN4M1NoV0:sub_vrm4_0
      0,  // VRN4M1NoV0:sub_vrm4_1
      41, // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      0,  // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      41, // VRN4M1NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN4M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN4M1NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN4M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN4M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN4M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN4M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN4M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M2
      0,  // VRN2M2:sub_16
      0,  // VRN2M2:sub_32
      0,  // VRN2M2:sub_gpr_even
      0,  // VRN2M2:sub_gpr_odd
      24, // VRN2M2:sub_vrm1_0 -> VR
      25, // VRN2M2:sub_vrm1_1 -> VRNoV0
      25, // VRN2M2:sub_vrm1_2 -> VRNoV0
      25, // VRN2M2:sub_vrm1_3 -> VRNoV0
      0,  // VRN2M2:sub_vrm1_4
      0,  // VRN2M2:sub_vrm1_5
      0,  // VRN2M2:sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_7
      42, // VRN2M2:sub_vrm2_0 -> VRM2
      43, // VRN2M2:sub_vrm2_1 -> VRM2NoV0
      0,  // VRN2M2:sub_vrm2_2
      0,  // VRN2M2:sub_vrm2_3
      0,  // VRN2M2:sub_vrm4_0
      0,  // VRN2M2:sub_vrm4_1
      40, // VRN2M2:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN2M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN2M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN2M2:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN2M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN2M2:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN2M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2:sub_vrm2_0_sub_vrm2_1
      0,  // VRN2M2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M2:sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M2:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M2:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M2NoV0
      0,  // VRN2M2NoV0:sub_16
      0,  // VRN2M2NoV0:sub_32
      0,  // VRN2M2NoV0:sub_gpr_even
      0,  // VRN2M2NoV0:sub_gpr_odd
      25, // VRN2M2NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN2M2NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN2M2NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN2M2NoV0:sub_vrm1_3 -> VRNoV0
      0,  // VRN2M2NoV0:sub_vrm1_4
      0,  // VRN2M2NoV0:sub_vrm1_5
      0,  // VRN2M2NoV0:sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_7
      43, // VRN2M2NoV0:sub_vrm2_0 -> VRM2NoV0
      43, // VRN2M2NoV0:sub_vrm2_1 -> VRM2NoV0
      0,  // VRN2M2NoV0:sub_vrm2_2
      0,  // VRN2M2NoV0:sub_vrm2_3
      0,  // VRN2M2NoV0:sub_vrm4_0
      0,  // VRN2M2NoV0:sub_vrm4_1
      41, // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN2M2NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN2M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN2M2NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN2M2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M2NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M2NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M2NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM4
      0,  // VRM4:sub_16
      0,  // VRM4:sub_32
      0,  // VRM4:sub_gpr_even
      0,  // VRM4:sub_gpr_odd
      24, // VRM4:sub_vrm1_0 -> VR
      25, // VRM4:sub_vrm1_1 -> VRNoV0
      25, // VRM4:sub_vrm1_2 -> VRNoV0
      25, // VRM4:sub_vrm1_3 -> VRNoV0
      0,  // VRM4:sub_vrm1_4
      0,  // VRM4:sub_vrm1_5
      0,  // VRM4:sub_vrm1_6
      0,  // VRM4:sub_vrm1_7
      42, // VRM4:sub_vrm2_0 -> VRM2
      43, // VRM4:sub_vrm2_1 -> VRM2NoV0
      0,  // VRM4:sub_vrm2_2
      0,  // VRM4:sub_vrm2_3
      0,  // VRM4:sub_vrm4_0
      0,  // VRM4:sub_vrm4_1
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM4:sub_vrm1_1_sub_vrm1_2
      0,  // VRM4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM4:sub_vrm1_2_sub_vrm1_3
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm1_3_sub_vrm1_4
      0,  // VRM4:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm1_4_sub_vrm1_5
      0,  // VRM4:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm1_5_sub_vrm1_6
      0,  // VRM4:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm1_6_sub_vrm1_7
      0,  // VRM4:sub_vrm2_0_sub_vrm2_1
      0,  // VRM4:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM4:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM4:sub_vrm2_1_sub_vrm2_2
      0,  // VRM4:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM4:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM4NoV0
      0,  // VRM4NoV0:sub_16
      0,  // VRM4NoV0:sub_32
      0,  // VRM4NoV0:sub_gpr_even
      0,  // VRM4NoV0:sub_gpr_odd
      25, // VRM4NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRM4NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRM4NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRM4NoV0:sub_vrm1_3 -> VRNoV0
      0,  // VRM4NoV0:sub_vrm1_4
      0,  // VRM4NoV0:sub_vrm1_5
      0,  // VRM4NoV0:sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_7
      43, // VRM4NoV0:sub_vrm2_0 -> VRM2NoV0
      43, // VRM4NoV0:sub_vrm2_1 -> VRM2NoV0
      0,  // VRM4NoV0:sub_vrm2_2
      0,  // VRM4NoV0:sub_vrm2_3
      0,  // VRM4NoV0:sub_vrm4_0
      0,  // VRM4NoV0:sub_vrm4_1
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM4NoV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRM4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM4NoV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRM4NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRM4NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRM4NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRM4NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRM4NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM4NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM4NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRM4NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM4NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM4_with_sub_vrm1_0_in_VMV0
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      44, // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      43, // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_1 -> VRM2NoV0
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM4_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M2_with_sub_vrm1_0_in_VMV0
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      44, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      43, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1 -> VRM2NoV0
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN2M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      41, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN4M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN5M1
      0,  // VRN5M1:sub_16
      0,  // VRN5M1:sub_32
      0,  // VRN5M1:sub_gpr_even
      0,  // VRN5M1:sub_gpr_odd
      24, // VRN5M1:sub_vrm1_0 -> VR
      25, // VRN5M1:sub_vrm1_1 -> VRNoV0
      25, // VRN5M1:sub_vrm1_2 -> VRNoV0
      25, // VRN5M1:sub_vrm1_3 -> VRNoV0
      25, // VRN5M1:sub_vrm1_4 -> VRNoV0
      0,  // VRN5M1:sub_vrm1_5
      0,  // VRN5M1:sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_7
      0,  // VRN5M1:sub_vrm2_0
      0,  // VRN5M1:sub_vrm2_1
      0,  // VRN5M1:sub_vrm2_2
      0,  // VRN5M1:sub_vrm2_3
      0,  // VRN5M1:sub_vrm4_0
      0,  // VRN5M1:sub_vrm4_1
      40, // VRN5M1:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN5M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN5M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN5M1:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN5M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN5M1:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN5M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN5M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN5M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      0,  // VRN5M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN5M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      0,  // VRN5M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN5M1:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      0,  // VRN5M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1:sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1:sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1:sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN5M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN5M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN5M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN5M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN5M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN5M1NoV0
      0,  // VRN5M1NoV0:sub_16
      0,  // VRN5M1NoV0:sub_32
      0,  // VRN5M1NoV0:sub_gpr_even
      0,  // VRN5M1NoV0:sub_gpr_odd
      25, // VRN5M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN5M1NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN5M1NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN5M1NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN5M1NoV0:sub_vrm1_4 -> VRNoV0
      0,  // VRN5M1NoV0:sub_vrm1_5
      0,  // VRN5M1NoV0:sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_7
      0,  // VRN5M1NoV0:sub_vrm2_0
      0,  // VRN5M1NoV0:sub_vrm2_1
      0,  // VRN5M1NoV0:sub_vrm2_2
      0,  // VRN5M1NoV0:sub_vrm2_3
      0,  // VRN5M1NoV0:sub_vrm4_0
      0,  // VRN5M1NoV0:sub_vrm4_1
      41, // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN5M1NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN5M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN5M1NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN5M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      0,  // VRN5M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN5M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      0,  // VRN5M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN5M1NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      0,  // VRN5M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN5M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN5M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN5M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN5M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN5M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN5M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN6M1
      0,  // VRN6M1:sub_16
      0,  // VRN6M1:sub_32
      0,  // VRN6M1:sub_gpr_even
      0,  // VRN6M1:sub_gpr_odd
      24, // VRN6M1:sub_vrm1_0 -> VR
      25, // VRN6M1:sub_vrm1_1 -> VRNoV0
      25, // VRN6M1:sub_vrm1_2 -> VRNoV0
      25, // VRN6M1:sub_vrm1_3 -> VRNoV0
      25, // VRN6M1:sub_vrm1_4 -> VRNoV0
      25, // VRN6M1:sub_vrm1_5 -> VRNoV0
      0,  // VRN6M1:sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_7
      0,  // VRN6M1:sub_vrm2_0
      0,  // VRN6M1:sub_vrm2_1
      0,  // VRN6M1:sub_vrm2_2
      0,  // VRN6M1:sub_vrm2_3
      0,  // VRN6M1:sub_vrm4_0
      0,  // VRN6M1:sub_vrm4_1
      40, // VRN6M1:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN6M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN6M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN6M1:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN6M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN6M1:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      58, // VRN6M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      0,  // VRN6M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN6M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN6M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN6M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      0,  // VRN6M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN6M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN6M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      0,  // VRN6M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN6M1:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN6M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      0,  // VRN6M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN6M1:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      0,  // VRN6M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1:sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1:sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN6M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN6M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN6M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN6M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN6M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN6M1NoV0
      0,  // VRN6M1NoV0:sub_16
      0,  // VRN6M1NoV0:sub_32
      0,  // VRN6M1NoV0:sub_gpr_even
      0,  // VRN6M1NoV0:sub_gpr_odd
      25, // VRN6M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN6M1NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN6M1NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN6M1NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN6M1NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRN6M1NoV0:sub_vrm1_5 -> VRNoV0
      0,  // VRN6M1NoV0:sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_7
      0,  // VRN6M1NoV0:sub_vrm2_0
      0,  // VRN6M1NoV0:sub_vrm2_1
      0,  // VRN6M1NoV0:sub_vrm2_2
      0,  // VRN6M1NoV0:sub_vrm2_3
      0,  // VRN6M1NoV0:sub_vrm4_0
      0,  // VRN6M1NoV0:sub_vrm4_1
      41, // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN6M1NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN6M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN6M1NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      59, // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      0,  // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN6M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN6M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      0,  // VRN6M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN6M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN6M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      0,  // VRN6M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN6M1NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN6M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      0,  // VRN6M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN6M1NoV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      0,  // VRN6M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN6M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN6M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN6M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN6M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN6M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M2
      0,  // VRN3M2:sub_16
      0,  // VRN3M2:sub_32
      0,  // VRN3M2:sub_gpr_even
      0,  // VRN3M2:sub_gpr_odd
      24, // VRN3M2:sub_vrm1_0 -> VR
      25, // VRN3M2:sub_vrm1_1 -> VRNoV0
      25, // VRN3M2:sub_vrm1_2 -> VRNoV0
      25, // VRN3M2:sub_vrm1_3 -> VRNoV0
      25, // VRN3M2:sub_vrm1_4 -> VRNoV0
      25, // VRN3M2:sub_vrm1_5 -> VRNoV0
      0,  // VRN3M2:sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_7
      42, // VRN3M2:sub_vrm2_0 -> VRM2
      43, // VRN3M2:sub_vrm2_1 -> VRM2NoV0
      43, // VRN3M2:sub_vrm2_2 -> VRM2NoV0
      0,  // VRN3M2:sub_vrm2_3
      0,  // VRN3M2:sub_vrm4_0
      0,  // VRN3M2:sub_vrm4_1
      40, // VRN3M2:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN3M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN3M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN3M2:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN3M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN3M2:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      58, // VRN3M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      61, // VRN3M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      0,  // VRN3M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN3M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN3M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      0,  // VRN3M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN3M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN3M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      0,  // VRN3M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN3M2:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN3M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      0,  // VRN3M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN3M2:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      0,  // VRN3M2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M2:sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M2:sub_vrm1_6_sub_vrm1_7
      51, // VRN3M2:sub_vrm2_0_sub_vrm2_1 -> VRN2M2
      0,  // VRN3M2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      52, // VRN3M2:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      0,  // VRN3M2:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M2:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M2NoV0
      0,  // VRN3M2NoV0:sub_16
      0,  // VRN3M2NoV0:sub_32
      0,  // VRN3M2NoV0:sub_gpr_even
      0,  // VRN3M2NoV0:sub_gpr_odd
      25, // VRN3M2NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN3M2NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN3M2NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN3M2NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN3M2NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRN3M2NoV0:sub_vrm1_5 -> VRNoV0
      0,  // VRN3M2NoV0:sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_7
      43, // VRN3M2NoV0:sub_vrm2_0 -> VRM2NoV0
      43, // VRN3M2NoV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRN3M2NoV0:sub_vrm2_2 -> VRM2NoV0
      0,  // VRN3M2NoV0:sub_vrm2_3
      0,  // VRN3M2NoV0:sub_vrm4_0
      0,  // VRN3M2NoV0:sub_vrm4_1
      41, // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN3M2NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN3M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN3M2NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      59, // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      62, // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      0,  // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN3M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN3M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      0,  // VRN3M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN3M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN3M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      0,  // VRN3M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN3M2NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN3M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      0,  // VRN3M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN3M2NoV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      0,  // VRN3M2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M2NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M2NoV0:sub_vrm1_6_sub_vrm1_7
      52, // VRN3M2NoV0:sub_vrm2_0_sub_vrm2_1 -> VRN2M2NoV0
      0,  // VRN3M2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      52, // VRN3M2NoV0:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      0,  // VRN3M2NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M2NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      44, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      43, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2 -> VRM2NoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      60, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      66, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      56, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      52, // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN3M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      60, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN6M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN7M1
      0,  // VRN7M1:sub_16
      0,  // VRN7M1:sub_32
      0,  // VRN7M1:sub_gpr_even
      0,  // VRN7M1:sub_gpr_odd
      24, // VRN7M1:sub_vrm1_0 -> VR
      25, // VRN7M1:sub_vrm1_1 -> VRNoV0
      25, // VRN7M1:sub_vrm1_2 -> VRNoV0
      25, // VRN7M1:sub_vrm1_3 -> VRNoV0
      25, // VRN7M1:sub_vrm1_4 -> VRNoV0
      25, // VRN7M1:sub_vrm1_5 -> VRNoV0
      25, // VRN7M1:sub_vrm1_6 -> VRNoV0
      0,  // VRN7M1:sub_vrm1_7
      0,  // VRN7M1:sub_vrm2_0
      0,  // VRN7M1:sub_vrm2_1
      0,  // VRN7M1:sub_vrm2_2
      0,  // VRN7M1:sub_vrm2_3
      0,  // VRN7M1:sub_vrm4_0
      0,  // VRN7M1:sub_vrm4_1
      40, // VRN7M1:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN7M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN7M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN7M1:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN7M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN7M1:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      58, // VRN7M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      61, // VRN7M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      0,  // VRN7M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN7M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN7M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN7M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN7M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      0,  // VRN7M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN7M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN7M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN7M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      0,  // VRN7M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN7M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN7M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      0,  // VRN7M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN7M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      0,  // VRN7M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      0,  // VRN7M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN7M1:sub_vrm1_6_sub_vrm1_7
      0,  // VRN7M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN7M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN7M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN7M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN7M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN7M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN7M1NoV0
      0,  // VRN7M1NoV0:sub_16
      0,  // VRN7M1NoV0:sub_32
      0,  // VRN7M1NoV0:sub_gpr_even
      0,  // VRN7M1NoV0:sub_gpr_odd
      25, // VRN7M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN7M1NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN7M1NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN7M1NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN7M1NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRN7M1NoV0:sub_vrm1_5 -> VRNoV0
      25, // VRN7M1NoV0:sub_vrm1_6 -> VRNoV0
      0,  // VRN7M1NoV0:sub_vrm1_7
      0,  // VRN7M1NoV0:sub_vrm2_0
      0,  // VRN7M1NoV0:sub_vrm2_1
      0,  // VRN7M1NoV0:sub_vrm2_2
      0,  // VRN7M1NoV0:sub_vrm2_3
      0,  // VRN7M1NoV0:sub_vrm4_0
      0,  // VRN7M1NoV0:sub_vrm4_1
      41, // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN7M1NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN7M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN7M1NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      59, // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      62, // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      0,  // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN7M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN7M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN7M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN7M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      0,  // VRN7M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN7M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN7M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN7M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      0,  // VRN7M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN7M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN7M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      0,  // VRN7M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1NoV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN7M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      0,  // VRN7M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1NoV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      0,  // VRN7M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN7M1NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN7M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN7M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN7M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN7M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN7M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN7M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      25, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6 -> VRNoV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      60, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      66, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      47, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      41, // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN7M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN8M1
      0,  // VRN8M1:sub_16
      0,  // VRN8M1:sub_32
      0,  // VRN8M1:sub_gpr_even
      0,  // VRN8M1:sub_gpr_odd
      24, // VRN8M1:sub_vrm1_0 -> VR
      25, // VRN8M1:sub_vrm1_1 -> VRNoV0
      25, // VRN8M1:sub_vrm1_2 -> VRNoV0
      25, // VRN8M1:sub_vrm1_3 -> VRNoV0
      25, // VRN8M1:sub_vrm1_4 -> VRNoV0
      25, // VRN8M1:sub_vrm1_5 -> VRNoV0
      25, // VRN8M1:sub_vrm1_6 -> VRNoV0
      25, // VRN8M1:sub_vrm1_7 -> VRNoV0
      0,  // VRN8M1:sub_vrm2_0
      0,  // VRN8M1:sub_vrm2_1
      0,  // VRN8M1:sub_vrm2_2
      0,  // VRN8M1:sub_vrm2_3
      0,  // VRN8M1:sub_vrm4_0
      0,  // VRN8M1:sub_vrm4_1
      40, // VRN8M1:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN8M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN8M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN8M1:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN8M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN8M1:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      58, // VRN8M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      61, // VRN8M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      67, // VRN8M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      0,  // VRN8M1:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN8M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN8M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN8M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN8M1:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN8M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN8M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN8M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN8M1:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN8M1:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN8M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN8M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN8M1:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN8M1:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN8M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN8M1:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN8M1:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN8M1:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN8M1:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      0,  // VRN8M1:sub_vrm2_0_sub_vrm2_1
      0,  // VRN8M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN8M1:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN8M1:sub_vrm2_1_sub_vrm2_2
      0,  // VRN8M1:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN8M1:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN8M1NoV0
      0,  // VRN8M1NoV0:sub_16
      0,  // VRN8M1NoV0:sub_32
      0,  // VRN8M1NoV0:sub_gpr_even
      0,  // VRN8M1NoV0:sub_gpr_odd
      25, // VRN8M1NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_5 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_6 -> VRNoV0
      25, // VRN8M1NoV0:sub_vrm1_7 -> VRNoV0
      0,  // VRN8M1NoV0:sub_vrm2_0
      0,  // VRN8M1NoV0:sub_vrm2_1
      0,  // VRN8M1NoV0:sub_vrm2_2
      0,  // VRN8M1NoV0:sub_vrm2_3
      0,  // VRN8M1NoV0:sub_vrm4_0
      0,  // VRN8M1NoV0:sub_vrm4_1
      41, // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN8M1NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN8M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN8M1NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      59, // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      62, // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      68, // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      0,  // VRN8M1NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN8M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN8M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN8M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN8M1NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN8M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN8M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN8M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN8M1NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN8M1NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN8M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN8M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN8M1NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN8M1NoV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN8M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN8M1NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN8M1NoV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN8M1NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN8M1NoV0:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      0,  // VRN8M1NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN8M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN8M1NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN8M1NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN8M1NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN8M1NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN4M2
      0,  // VRN4M2:sub_16
      0,  // VRN4M2:sub_32
      0,  // VRN4M2:sub_gpr_even
      0,  // VRN4M2:sub_gpr_odd
      24, // VRN4M2:sub_vrm1_0 -> VR
      25, // VRN4M2:sub_vrm1_1 -> VRNoV0
      25, // VRN4M2:sub_vrm1_2 -> VRNoV0
      25, // VRN4M2:sub_vrm1_3 -> VRNoV0
      25, // VRN4M2:sub_vrm1_4 -> VRNoV0
      25, // VRN4M2:sub_vrm1_5 -> VRNoV0
      25, // VRN4M2:sub_vrm1_6 -> VRNoV0
      25, // VRN4M2:sub_vrm1_7 -> VRNoV0
      42, // VRN4M2:sub_vrm2_0 -> VRM2
      43, // VRN4M2:sub_vrm2_1 -> VRM2NoV0
      43, // VRN4M2:sub_vrm2_2 -> VRM2NoV0
      43, // VRN4M2:sub_vrm2_3 -> VRM2NoV0
      0,  // VRN4M2:sub_vrm4_0
      0,  // VRN4M2:sub_vrm4_1
      40, // VRN4M2:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN4M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN4M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN4M2:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN4M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN4M2:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      58, // VRN4M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      61, // VRN4M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      67, // VRN4M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      70, // VRN4M2:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      50, // VRN4M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN4M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN4M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN4M2:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN4M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN4M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN4M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN4M2:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN4M2:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN4M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN4M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN4M2:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN4M2:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN4M2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN4M2:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN4M2:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN4M2:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN4M2:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      51, // VRN4M2:sub_vrm2_0_sub_vrm2_1 -> VRN2M2
      63, // VRN4M2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN3M2
      0,  // VRN4M2:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      52, // VRN4M2:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      64, // VRN4M2:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN3M2NoV0
      52, // VRN4M2:sub_vrm2_2_sub_vrm2_3 -> VRN2M2NoV0
    },
    { // VRN4M2NoV0
      0,  // VRN4M2NoV0:sub_16
      0,  // VRN4M2NoV0:sub_32
      0,  // VRN4M2NoV0:sub_gpr_even
      0,  // VRN4M2NoV0:sub_gpr_odd
      25, // VRN4M2NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_5 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_6 -> VRNoV0
      25, // VRN4M2NoV0:sub_vrm1_7 -> VRNoV0
      43, // VRN4M2NoV0:sub_vrm2_0 -> VRM2NoV0
      43, // VRN4M2NoV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRN4M2NoV0:sub_vrm2_2 -> VRM2NoV0
      43, // VRN4M2NoV0:sub_vrm2_3 -> VRM2NoV0
      0,  // VRN4M2NoV0:sub_vrm4_0
      0,  // VRN4M2NoV0:sub_vrm4_1
      41, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN4M2NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN4M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN4M2NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      59, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      62, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      68, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      71, // VRN4M2NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      50, // VRN4M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN4M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN4M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN4M2NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN4M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN4M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN4M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN4M2NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN4M2NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN4M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN4M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN4M2NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN4M2NoV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN4M2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN4M2NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN4M2NoV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN4M2NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN4M2NoV0:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      52, // VRN4M2NoV0:sub_vrm2_0_sub_vrm2_1 -> VRN2M2NoV0
      64, // VRN4M2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN3M2NoV0
      0,  // VRN4M2NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      52, // VRN4M2NoV0:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      64, // VRN4M2NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN3M2NoV0
      52, // VRN4M2NoV0:sub_vrm2_2_sub_vrm2_3 -> VRN2M2NoV0
    },
    { // VRN2M4
      0,  // VRN2M4:sub_16
      0,  // VRN2M4:sub_32
      0,  // VRN2M4:sub_gpr_even
      0,  // VRN2M4:sub_gpr_odd
      24, // VRN2M4:sub_vrm1_0 -> VR
      25, // VRN2M4:sub_vrm1_1 -> VRNoV0
      25, // VRN2M4:sub_vrm1_2 -> VRNoV0
      25, // VRN2M4:sub_vrm1_3 -> VRNoV0
      25, // VRN2M4:sub_vrm1_4 -> VRNoV0
      25, // VRN2M4:sub_vrm1_5 -> VRNoV0
      25, // VRN2M4:sub_vrm1_6 -> VRNoV0
      25, // VRN2M4:sub_vrm1_7 -> VRNoV0
      42, // VRN2M4:sub_vrm2_0 -> VRM2
      43, // VRN2M4:sub_vrm2_1 -> VRM2NoV0
      43, // VRN2M4:sub_vrm2_2 -> VRM2NoV0
      43, // VRN2M4:sub_vrm2_3 -> VRM2NoV0
      53, // VRN2M4:sub_vrm4_0 -> VRM4
      54, // VRN2M4:sub_vrm4_1 -> VRM4NoV0
      40, // VRN2M4:sub_vrm1_0_sub_vrm1_1 -> VRN2M1
      46, // VRN2M4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1
      49, // VRN2M4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1
      41, // VRN2M4:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN2M4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN2M4:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      58, // VRN2M4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1
      61, // VRN2M4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1
      67, // VRN2M4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1
      70, // VRN2M4:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1
      50, // VRN2M4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN2M4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN2M4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN2M4:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN2M4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN2M4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN2M4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN2M4:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN2M4:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN2M4:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN2M4:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN2M4:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN2M4:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN2M4:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN2M4:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN2M4:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN2M4:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN2M4:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      51, // VRN2M4:sub_vrm2_0_sub_vrm2_1 -> VRN2M2
      63, // VRN2M4:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN3M2
      72, // VRN2M4:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN4M2
      52, // VRN2M4:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      64, // VRN2M4:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN3M2NoV0
      52, // VRN2M4:sub_vrm2_2_sub_vrm2_3 -> VRN2M2NoV0
    },
    { // VRN2M4NoV0
      0,  // VRN2M4NoV0:sub_16
      0,  // VRN2M4NoV0:sub_32
      0,  // VRN2M4NoV0:sub_gpr_even
      0,  // VRN2M4NoV0:sub_gpr_odd
      25, // VRN2M4NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_5 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_6 -> VRNoV0
      25, // VRN2M4NoV0:sub_vrm1_7 -> VRNoV0
      43, // VRN2M4NoV0:sub_vrm2_0 -> VRM2NoV0
      43, // VRN2M4NoV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRN2M4NoV0:sub_vrm2_2 -> VRM2NoV0
      43, // VRN2M4NoV0:sub_vrm2_3 -> VRM2NoV0
      54, // VRN2M4NoV0:sub_vrm4_0 -> VRM4NoV0
      54, // VRN2M4NoV0:sub_vrm4_1 -> VRM4NoV0
      41, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1NoV0
      47, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1NoV0
      50, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1NoV0
      41, // VRN2M4NoV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN2M4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN2M4NoV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      59, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1NoV0
      62, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1NoV0
      68, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1NoV0
      71, // VRN2M4NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1NoV0
      50, // VRN2M4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN2M4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN2M4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN2M4NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN2M4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN2M4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN2M4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN2M4NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN2M4NoV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN2M4NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN2M4NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN2M4NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN2M4NoV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN2M4NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN2M4NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN2M4NoV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN2M4NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN2M4NoV0:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      52, // VRN2M4NoV0:sub_vrm2_0_sub_vrm2_1 -> VRN2M2NoV0
      64, // VRN2M4NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN3M2NoV0
      73, // VRN2M4NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN4M2NoV0
      52, // VRN2M4NoV0:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      64, // VRN2M4NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN3M2NoV0
      52, // VRN2M4NoV0:sub_vrm2_2_sub_vrm2_3 -> VRN2M2NoV0
    },
    { // VRM8
      0,  // VRM8:sub_16
      0,  // VRM8:sub_32
      0,  // VRM8:sub_gpr_even
      0,  // VRM8:sub_gpr_odd
      24, // VRM8:sub_vrm1_0 -> VR
      25, // VRM8:sub_vrm1_1 -> VRNoV0
      25, // VRM8:sub_vrm1_2 -> VRNoV0
      25, // VRM8:sub_vrm1_3 -> VRNoV0
      25, // VRM8:sub_vrm1_4 -> VRNoV0
      25, // VRM8:sub_vrm1_5 -> VRNoV0
      25, // VRM8:sub_vrm1_6 -> VRNoV0
      25, // VRM8:sub_vrm1_7 -> VRNoV0
      42, // VRM8:sub_vrm2_0 -> VRM2
      43, // VRM8:sub_vrm2_1 -> VRM2NoV0
      43, // VRM8:sub_vrm2_2 -> VRM2NoV0
      43, // VRM8:sub_vrm2_3 -> VRM2NoV0
      53, // VRM8:sub_vrm4_0 -> VRM4
      54, // VRM8:sub_vrm4_1 -> VRM4NoV0
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM8:sub_vrm1_1_sub_vrm1_2
      0,  // VRM8:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM8:sub_vrm1_2_sub_vrm1_3
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm1_3_sub_vrm1_4
      0,  // VRM8:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm1_4_sub_vrm1_5
      0,  // VRM8:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm1_5_sub_vrm1_6
      0,  // VRM8:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm1_6_sub_vrm1_7
      0,  // VRM8:sub_vrm2_0_sub_vrm2_1
      0,  // VRM8:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM8:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM8:sub_vrm2_1_sub_vrm2_2
      0,  // VRM8:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM8:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM8NoV0
      0,  // VRM8NoV0:sub_16
      0,  // VRM8NoV0:sub_32
      0,  // VRM8NoV0:sub_gpr_even
      0,  // VRM8NoV0:sub_gpr_odd
      25, // VRM8NoV0:sub_vrm1_0 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_1 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_2 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_3 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_4 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_5 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_6 -> VRNoV0
      25, // VRM8NoV0:sub_vrm1_7 -> VRNoV0
      43, // VRM8NoV0:sub_vrm2_0 -> VRM2NoV0
      43, // VRM8NoV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRM8NoV0:sub_vrm2_2 -> VRM2NoV0
      43, // VRM8NoV0:sub_vrm2_3 -> VRM2NoV0
      54, // VRM8NoV0:sub_vrm4_0 -> VRM4NoV0
      54, // VRM8NoV0:sub_vrm4_1 -> VRM4NoV0
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM8NoV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRM8NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM8NoV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8NoV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8NoV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8NoV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRM8NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8NoV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRM8NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8NoV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRM8NoV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRM8NoV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRM8NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM8NoV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM8NoV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRM8NoV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM8NoV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRM8_with_sub_vrm1_0_in_VMV0
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_6 -> VRNoV0
      25, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_7 -> VRNoV0
      44, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      43, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_2 -> VRM2NoV0
      43, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_3 -> VRM2NoV0
      55, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm4_0 -> VRM4_with_sub_vrm1_0_in_VMV0
      54, // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm4_1 -> VRM4NoV0
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRM8_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
    { // VRN2M4_with_sub_vrm1_0_in_VMV0
      0,  // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_6 -> VRNoV0
      25, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_7 -> VRNoV0
      44, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      43, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_2 -> VRM2NoV0
      43, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_3 -> VRM2NoV0
      55, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm4_0 -> VRM4_with_sub_vrm1_0_in_VMV0
      54, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm4_1 -> VRM4NoV0
      45, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      60, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      66, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      69, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      81, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      50, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      56, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      65, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      80, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN4M2_with_sub_vrm1_0_in_VMV0
      52, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      64, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN3M2NoV0
      52, // VRN2M4_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3 -> VRN2M2NoV0
    },
    { // VRN4M2_with_sub_vrm1_0_in_VMV0
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6 -> VRNoV0
      25, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_7 -> VRNoV0
      44, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0 -> VRM2_with_sub_vrm1_0_in_VMV0
      43, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1 -> VRM2NoV0
      43, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2 -> VRM2NoV0
      43, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_3 -> VRM2NoV0
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      60, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      66, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      69, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      81, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN8M1_with_sub_vrm1_0_in_VMV0
      50, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      56, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1 -> VRN2M2_with_sub_vrm1_0_in_VMV0
      65, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2 -> VRN3M2_with_sub_vrm1_0_in_VMV0
      0,  // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      52, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2 -> VRN2M2NoV0
      64, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3 -> VRN3M2NoV0
      52, // VRN4M2_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3 -> VRN2M2NoV0
    },
    { // VRN8M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_16
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_32
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_gpr_even
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_gpr_odd
      39, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0 -> VMV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1 -> VRNoV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2 -> VRNoV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3 -> VRNoV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4 -> VRNoV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5 -> VRNoV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6 -> VRNoV0
      25, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_7 -> VRNoV0
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_3
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_0
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm4_1
      45, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1 -> VRN2M1_with_sub_vrm1_0_in_VMV0
      48, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2 -> VRN3M1_with_sub_vrm1_0_in_VMV0
      57, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN4M1_with_sub_vrm1_0_in_VMV0
      41, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2 -> VRN2M1NoV0
      47, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3 -> VRN3M1NoV0
      41, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3 -> VRN2M1NoV0
      60, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN5M1_with_sub_vrm1_0_in_VMV0
      66, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN6M1_with_sub_vrm1_0_in_VMV0
      69, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN7M1_with_sub_vrm1_0_in_VMV0
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7
      50, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN4M1NoV0
      59, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN5M1NoV0
      62, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN6M1NoV0
      68, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN7M1NoV0
      47, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4 -> VRN3M1NoV0
      50, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN4M1NoV0
      59, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN5M1NoV0
      62, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN6M1NoV0
      41, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4 -> VRN2M1NoV0
      47, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5 -> VRN3M1NoV0
      50, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN4M1NoV0
      59, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_3_sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN5M1NoV0
      41, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5 -> VRN2M1NoV0
      47, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6 -> VRN3M1NoV0
      50, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_4_sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN4M1NoV0
      41, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6 -> VRN2M1NoV0
      47, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_5_sub_vrm1_6_sub_vrm1_7 -> VRN3M1NoV0
      41, // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm1_6_sub_vrm1_7 -> VRN2M1NoV0
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_0_sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_1_sub_vrm2_2_sub_vrm2_3
      0,  // VRN8M1_with_sub_vrm1_0_in_VMV0:sub_vrm2_2_sub_vrm2_3
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 52 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &RISCVGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 32},    // FPR16
    {1, 33},    // GPRAll
    {1, 32},    // FPR32
    {1, 32},    // GPR
    {1, 32},    // GPRF16
    {1, 32},    // GPRF32
    {1, 31},    // GPRNoX0
    {1, 30},    // GPRNoX0X2
    {1, 26},    // GPRJALR
    {1, 14},    // GPRTC
    {1, 8},   // FPR32C
    {1, 8},   // GPRC
    {1, 8},   // SR07
    {1, 6},   // GPRC_and_GPRTC
    {0, 0},   // VCSR
    {1, 2},   // GPRC_and_SR07
    {1, 2},   // GPRX1X5
    {1, 1},   // GPRX0
    {1, 1},   // GPRX1
    {1, 1},   // GPRX5
    {1, 1},   // SP
    {1, 32},    // FPR64
    {1, 32},    // VM
    {1, 32},    // VR
    {1, 31},    // VRNoV0
    {2, 32},    // GPRPair
    {2, 30},    // GPRPair_with_sub_gpr_even_in_GPRNoX0
    {2, 28},    // GPRPair_with_sub_gpr_even_in_GPRNoX0X2
    {2, 26},    // GPRPair_with_sub_gpr_even_in_GPRJALR
    {1, 8},   // FPR64C
    {2, 14},    // GPRPair_with_sub_gpr_even_in_GPRTC
    {2, 8},   // GPRPair_with_sub_gpr_even_in_GPRC
    {2, 8},   // GPRPair_with_sub_gpr_even_in_SR07
    {2, 6},   // GPRPair_with_sub_gpr_even_in_GPRC_and_GPRTC
    {2, 2},   // GPRPair_with_sub_gpr_even_in_GPRC_and_SR07
    {2, 2},   // GPRPair_with_sub_gpr_even_in_GPRX0
    {2, 2},   // GPRPair_with_sub_gpr_even_in_SP
    {2, 2},   // GPRPair_with_sub_gpr_odd_in_GPRX1X5
    {1, 1},   // VMV0
    {2, 32},    // VRN2M1
    {2, 31},    // VRN2M1NoV0
    {2, 32},    // VRM2
    {2, 30},    // VRM2NoV0
    {2, 2},   // VRM2_with_sub_vrm1_0_in_VMV0
    {2, 2},   // VRN2M1_with_sub_vrm1_0_in_VMV0
    {3, 32},    // VRN3M1
    {3, 31},    // VRN3M1NoV0
    {3, 3},   // VRN3M1_with_sub_vrm1_0_in_VMV0
    {4, 32},    // VRN4M1
    {4, 31},    // VRN4M1NoV0
    {4, 32},    // VRN2M2
    {4, 30},    // VRN2M2NoV0
    {4, 32},    // VRM4
    {4, 28},    // VRM4NoV0
    {4, 4},   // VRM4_with_sub_vrm1_0_in_VMV0
    {4, 4},   // VRN2M2_with_sub_vrm1_0_in_VMV0
    {4, 4},   // VRN4M1_with_sub_vrm1_0_in_VMV0
    {5, 32},    // VRN5M1
    {5, 31},    // VRN5M1NoV0
    {5, 5},   // VRN5M1_with_sub_vrm1_0_in_VMV0
    {6, 32},    // VRN6M1
    {6, 31},    // VRN6M1NoV0
    {6, 32},    // VRN3M2
    {6, 30},    // VRN3M2NoV0
    {6, 6},   // VRN3M2_with_sub_vrm1_0_in_VMV0
    {6, 6},   // VRN6M1_with_sub_vrm1_0_in_VMV0
    {7, 32},    // VRN7M1
    {7, 31},    // VRN7M1NoV0
    {7, 7},   // VRN7M1_with_sub_vrm1_0_in_VMV0
    {8, 32},    // VRN8M1
    {8, 31},    // VRN8M1NoV0
    {8, 32},    // VRN4M2
    {8, 30},    // VRN4M2NoV0
    {8, 32},    // VRN2M4
    {8, 28},    // VRN2M4NoV0
    {8, 32},    // VRM8
    {8, 24},    // VRM8NoV0
    {8, 8},   // VRM8_with_sub_vrm1_0_in_VMV0
    {8, 8},   // VRN2M4_with_sub_vrm1_0_in_VMV0
    {8, 8},   // VRN4M2_with_sub_vrm1_0_in_VMV0
    {8, 8},   // VRN8M1_with_sub_vrm1_0_in_VMV0
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned RISCVGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 105 && "invalid register unit");
  // All register units have unit weight.
  return 1;
}


// Get the number of dimensions of register pressure.
unsigned RISCVGenRegisterInfo::getNumRegPressureSets() const {
  return 14;
}

// Get the name of this register unit pressure set.
const char *RISCVGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "GPRC_and_SR07",
    "GPRX0",
    "SP",
    "GPRX1",
    "FPR32C",
    "GPRC",
    "SR07",
    "VMV0",
    "GPRC_with_SR07",
    "GPRTC",
    "VRM8NoV0",
    "FPR16",
    "VM",
    "GPR",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned RISCVGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    2,    // 0: GPRC_and_SR07
    2,    // 1: GPRX0
    2,    // 2: SP
    3,    // 3: GPRX1
    8,    // 4: FPR32C
    8,    // 5: GPRC
    8,    // 6: SR07
    8,    // 7: VMV0
    14,   // 8: GPRC_with_SR07
    16,   // 9: GPRTC
    24,   // 10: VRM8NoV0
    32,   // 11: FPR16
    32,   // 12: VM
    33,   // 13: GPR
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 4, 11, -1,
  /* 3 */ 7, 12, -1,
  /* 6 */ 10, 12, -1,
  /* 9 */ 1, 13, -1,
  /* 12 */ 2, 13, -1,
  /* 15 */ 3, 13, -1,
  /* 18 */ 6, 8, 13, -1,
  /* 22 */ 5, 8, 9, 13, -1,
  /* 27 */ 0, 5, 6, 8, 9, 13, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *RISCVGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    1,10,1,10,10,10,10,10,10,24,0,22,18,22,2,27,15,9,15,15,12,1,4,4,4,10,10,10,10,0,24,22,18,22,27,9,12,15,3,4,4,4,4,3,3,4,4,3,4,4,4,4,4,4,3,3,3,4,4,3,4,4,4,4,3,3,4,4,3,4,4,4,4,4,4,4,6,3,3,3,3,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *RISCVGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 105 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    2,2,2,2,2,2,2,2,9,3,3,3,3,3,3,3,3,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,9,15,12,12,15,15,24,24,27,27,22,22,22,22,22,22,24,24,18,18,18,18,18,18,10,10,10,10,24,24,24,24,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc RISCVRegDesc[];
extern const int16_t RISCVRegDiffLists[];
extern const LaneBitmask RISCVLaneMaskLists[];
extern const char RISCVRegStrings[];
extern const char RISCVRegClassStrings[];
extern const MCPhysReg RISCVRegUnitRoots[][2];
extern const uint16_t RISCVSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits RISCVSubRegIdxRanges[];
extern const uint16_t RISCVRegEncodingTable[];
// RISCV Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0Dwarf2L[];
extern const unsigned RISCVDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0Dwarf2L[];
extern const unsigned RISCVEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair RISCVDwarfFlavour0L2Dwarf[];
extern const unsigned RISCVDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair RISCVEHFlavour0L2Dwarf[];
extern const unsigned RISCVEHFlavour0L2DwarfSize;

RISCVGenRegisterInfo::
RISCVGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&RISCVRegInfoDesc, RegisterClasses, RegisterClasses+81,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFF806), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(RISCVRegDesc, 459, RA, PC,
                     RISCVMCRegisterClasses, 81,
                     RISCVRegUnitRoots,
                     105,
                     RISCVRegDiffLists,
                     RISCVLaneMaskLists,
                     RISCVRegStrings,
                     RISCVRegClassStrings,
                     RISCVSubRegIdxLists,
                     53,
                     RISCVSubRegIdxRanges,
                     RISCVRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(RISCVDwarfFlavour0Dwarf2L, RISCVDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(RISCVEHFlavour0Dwarf2L, RISCVEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(RISCVDwarfFlavour0L2Dwarf, RISCVDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(RISCVEHFlavour0L2Dwarf, RISCVEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_ILP32D_LP64D_SaveList[] = { RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_D, RISCV::F9_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, 0 };
static const uint32_t CSR_ILP32D_LP64D_RegMask[] = { 0x00000020, 0xf00c0c00, 0xf00c003f, 0xf00c003f, 0xf00c003f, 0x0000003f, 0x000f8400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_ILP32E_LP64E_SaveList[] = { RISCV::X1, RISCV::X8, RISCV::X9, 0 };
static const uint32_t CSR_ILP32E_LP64E_RegMask[] = { 0x00000020, 0x000c0c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_ILP32F_LP64F_SaveList[] = { RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::F8_F, RISCV::F9_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, 0 };
static const uint32_t CSR_ILP32F_LP64F_RegMask[] = { 0x00000020, 0xf00c0c00, 0x0000003f, 0xf00c0000, 0xf00c003f, 0x0000003f, 0x000f8400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_ILP32_LP64_SaveList[] = { RISCV::X1, RISCV::X8, RISCV::X9, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, 0 };
static const uint32_t CSR_ILP32_LP64_RegMask[] = { 0x00000020, 0xf00c0c00, 0x0000003f, 0x00000000, 0x00000000, 0x00000000, 0x000f8400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Interrupt_SaveList[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, 0 };
static const uint32_t CSR_Interrupt_RegMask[] = { 0x00000020, 0xffff8c00, 0x000003ff, 0x00000000, 0x00000000, 0x00000000, 0x003ffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_Interrupt_RVE_SaveList[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, 0 };
static const uint32_t CSR_Interrupt_RVE_RegMask[] = { 0x00000020, 0x03ff8c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00003e00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_NoRegs_SaveList[] = { 0 };
static const uint32_t CSR_NoRegs_RegMask[] = { 0x00000020, 0x00000400, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_XLEN_F32_Interrupt_SaveList[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F8_F, RISCV::F9_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, 0 };
static const uint32_t CSR_XLEN_F32_Interrupt_RegMask[] = { 0x00000020, 0xffff8c00, 0x000003ff, 0xfffffc00, 0xffffffff, 0x000003ff, 0x003ffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_XLEN_F32_Interrupt_RVE_SaveList[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::F0_F, RISCV::F1_F, RISCV::F2_F, RISCV::F3_F, RISCV::F4_F, RISCV::F5_F, RISCV::F6_F, RISCV::F7_F, RISCV::F8_F, RISCV::F9_F, RISCV::F10_F, RISCV::F11_F, RISCV::F12_F, RISCV::F13_F, RISCV::F14_F, RISCV::F15_F, RISCV::F16_F, RISCV::F17_F, RISCV::F18_F, RISCV::F19_F, RISCV::F20_F, RISCV::F21_F, RISCV::F22_F, RISCV::F23_F, RISCV::F24_F, RISCV::F25_F, RISCV::F26_F, RISCV::F27_F, RISCV::F28_F, RISCV::F29_F, RISCV::F30_F, RISCV::F31_F, 0 };
static const uint32_t CSR_XLEN_F32_Interrupt_RVE_RegMask[] = { 0x00000020, 0x03ff8c00, 0x00000000, 0xfffffc00, 0xffffffff, 0x000003ff, 0x00003e00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_XLEN_F64_Interrupt_SaveList[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X18, RISCV::X19, RISCV::X20, RISCV::X21, RISCV::X22, RISCV::X23, RISCV::X24, RISCV::X25, RISCV::X26, RISCV::X27, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F8_D, RISCV::F9_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, 0 };
static const uint32_t CSR_XLEN_F64_Interrupt_RegMask[] = { 0x00000020, 0xffff8c00, 0xffffffff, 0xffffffff, 0xffffffff, 0x000003ff, 0x003ffe00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };
static const MCPhysReg CSR_XLEN_F64_Interrupt_RVE_SaveList[] = { RISCV::X1, RISCV::X5, RISCV::X6, RISCV::X7, RISCV::X8, RISCV::X9, RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15, RISCV::F0_D, RISCV::F1_D, RISCV::F2_D, RISCV::F3_D, RISCV::F4_D, RISCV::F5_D, RISCV::F6_D, RISCV::F7_D, RISCV::F8_D, RISCV::F9_D, RISCV::F10_D, RISCV::F11_D, RISCV::F12_D, RISCV::F13_D, RISCV::F14_D, RISCV::F15_D, RISCV::F16_D, RISCV::F17_D, RISCV::F18_D, RISCV::F19_D, RISCV::F20_D, RISCV::F21_D, RISCV::F22_D, RISCV::F23_D, RISCV::F24_D, RISCV::F25_D, RISCV::F26_D, RISCV::F27_D, RISCV::F28_D, RISCV::F29_D, RISCV::F30_D, RISCV::F31_D, 0 };
static const uint32_t CSR_XLEN_F64_Interrupt_RVE_RegMask[] = { 0x00000020, 0x03ff8c00, 0xfffffc00, 0xffffffff, 0xffffffff, 0x000003ff, 0x00003e00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, };


ArrayRef<const uint32_t *> RISCVGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_ILP32D_LP64D_RegMask,
    CSR_ILP32E_LP64E_RegMask,
    CSR_ILP32F_LP64F_RegMask,
    CSR_ILP32_LP64_RegMask,
    CSR_Interrupt_RegMask,
    CSR_Interrupt_RVE_RegMask,
    CSR_NoRegs_RegMask,
    CSR_XLEN_F32_Interrupt_RegMask,
    CSR_XLEN_F32_Interrupt_RVE_RegMask,
    CSR_XLEN_F64_Interrupt_RegMask,
    CSR_XLEN_F64_Interrupt_RVE_RegMask,
  };
  return ArrayRef(Masks);
}

bool RISCVGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool RISCVGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool RISCVGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool RISCVGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      PhysReg == RISCV::VLENB ||
      PhysReg == RISCV::X0 ||
      false;
}

ArrayRef<const char *> RISCVGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR_ILP32D_LP64D",
    "CSR_ILP32E_LP64E",
    "CSR_ILP32F_LP64F",
    "CSR_ILP32_LP64",
    "CSR_Interrupt",
    "CSR_Interrupt_RVE",
    "CSR_NoRegs",
    "CSR_XLEN_F32_Interrupt",
    "CSR_XLEN_F32_Interrupt_RVE",
    "CSR_XLEN_F64_Interrupt",
    "CSR_XLEN_F64_Interrupt_RVE",
  };
  return ArrayRef(Names);
}

const RISCVFrameLowering *
RISCVGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const RISCVFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31