/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\

|*                                                                            *|

|* Subtarget Enumeration Source Fragment                                      *|

|*                                                                            *|

|* Automatically generated file, do not edit!                                 *|

|*                                                                            *|

\*===----------------------------------------------------------------------===*/

#ifdef GET_SUBTARGETINFO_ENUM

#undef GET_SUBTARGETINFO_ENUM

namespace llvm {

namespace RISCV {

enum {

  Experimental = 0,

  Feature32Bit = 1,

  Feature64Bit = 2,

  FeatureFastUnalignedAccess = 3,

  FeatureForcedAtomics = 4,

  FeatureNoRVCHints = 5,

  FeaturePostRAScheduler = 6,

  FeatureRVE = 7,

  FeatureRelax = 8,

  FeatureReserveX1 = 9,

  FeatureReserveX2 = 10,

  FeatureReserveX3 = 11,

  FeatureReserveX4 = 12,

  FeatureReserveX5 = 13,

  FeatureReserveX6 = 14,

  FeatureReserveX7 = 15,

  FeatureReserveX8 = 16,

  FeatureReserveX9 = 17,

  FeatureReserveX10 = 18,

  FeatureReserveX11 = 19,

  FeatureReserveX12 = 20,

  FeatureReserveX13 = 21,

  FeatureReserveX14 = 22,

  FeatureReserveX15 = 23,

  FeatureReserveX16 = 24,

  FeatureReserveX17 = 25,

  FeatureReserveX18 = 26,

  FeatureReserveX19 = 27,

  FeatureReserveX20 = 28,

  FeatureReserveX21 = 29,

  FeatureReserveX22 = 30,

  FeatureReserveX23 = 31,

  FeatureReserveX24 = 32,

  FeatureReserveX25 = 33,

  FeatureReserveX26 = 34,

  FeatureReserveX27 = 35,

  FeatureReserveX28 = 36,

  FeatureReserveX29 = 37,

  FeatureReserveX30 = 38,

  FeatureReserveX31 = 39,

  FeatureSaveRestore = 40,

  FeatureStdExtA = 41,

  FeatureStdExtC = 42,

  FeatureStdExtD = 43,

  FeatureStdExtF = 44,

  FeatureStdExtH = 45,

  FeatureStdExtI = 46,

  FeatureStdExtM = 47,

  FeatureStdExtSmaia = 48,

  FeatureStdExtSsaia = 49,

  FeatureStdExtSvinval = 50,

  FeatureStdExtSvnapot = 51,

  FeatureStdExtSvpbmt = 52,

  FeatureStdExtV = 53,

  FeatureStdExtZacas = 54,

  FeatureStdExtZawrs = 55,

  FeatureStdExtZba = 56,

  FeatureStdExtZbb = 57,

  FeatureStdExtZbc = 58,

  FeatureStdExtZbkb = 59,

  FeatureStdExtZbkc = 60,

  FeatureStdExtZbkx = 61,

  FeatureStdExtZbs = 62,

  FeatureStdExtZca = 63,

  FeatureStdExtZcb = 64,

  FeatureStdExtZcd = 65,

  FeatureStdExtZce = 66,

  FeatureStdExtZcf = 67,

  FeatureStdExtZcmop = 68,

  FeatureStdExtZcmp = 69,

  FeatureStdExtZcmt = 70,

  FeatureStdExtZdinx = 71,

  FeatureStdExtZfa = 72,

  FeatureStdExtZfbfmin = 73,

  FeatureStdExtZfh = 74,

  FeatureStdExtZfhmin = 75,

  FeatureStdExtZfinx = 76,

  FeatureStdExtZhinx = 77,

  FeatureStdExtZhinxmin = 78,

  FeatureStdExtZicbom = 79,

  FeatureStdExtZicbop = 80,

  FeatureStdExtZicboz = 81,

  FeatureStdExtZicfilp = 82,

  FeatureStdExtZicfiss = 83,

  FeatureStdExtZicntr = 84,

  FeatureStdExtZicond = 85,

  FeatureStdExtZicsr = 86,

  FeatureStdExtZifencei = 87,

  FeatureStdExtZihintntl = 88,

  FeatureStdExtZihintpause = 89,

  FeatureStdExtZihpm = 90,

  FeatureStdExtZimop = 91,

  FeatureStdExtZk = 92,

  FeatureStdExtZkn = 93,

  FeatureStdExtZknd = 94,

  FeatureStdExtZkne = 95,

  FeatureStdExtZknh = 96,

  FeatureStdExtZkr = 97,

  FeatureStdExtZks = 98,

  FeatureStdExtZksed = 99,

  FeatureStdExtZksh = 100,

  FeatureStdExtZkt = 101,

  FeatureStdExtZmmul = 102,

  FeatureStdExtZtso = 103,

  FeatureStdExtZvbb = 104,

  FeatureStdExtZvbc = 105,

  FeatureStdExtZve32f = 106,

  FeatureStdExtZve32x = 107,

  FeatureStdExtZve64d = 108,

  FeatureStdExtZve64f = 109,

  FeatureStdExtZve64x = 110,

  FeatureStdExtZvfbfmin = 111,

  FeatureStdExtZvfbfwma = 112,

  FeatureStdExtZvfh = 113,

  FeatureStdExtZvfhmin = 114,

  FeatureStdExtZvkb = 115,

  FeatureStdExtZvkg = 116,

  FeatureStdExtZvkn = 117,

  FeatureStdExtZvknc = 118,

  FeatureStdExtZvkned = 119,

  FeatureStdExtZvkng = 120,

  FeatureStdExtZvknha = 121,

  FeatureStdExtZvknhb = 122,

  FeatureStdExtZvks = 123,

  FeatureStdExtZvksc = 124,

  FeatureStdExtZvksed = 125,

  FeatureStdExtZvksg = 126,

  FeatureStdExtZvksh = 127,

  FeatureStdExtZvkt = 128,

  FeatureStdExtZvl32b = 129,

  FeatureStdExtZvl64b = 130,

  FeatureStdExtZvl128b = 131,

  FeatureStdExtZvl256b = 132,

  FeatureStdExtZvl512b = 133,

  FeatureStdExtZvl1024b = 134,

  FeatureStdExtZvl2048b = 135,

  FeatureStdExtZvl4096b = 136,

  FeatureStdExtZvl8192b = 137,

  FeatureStdExtZvl16384b = 138,

  FeatureStdExtZvl32768b = 139,

  FeatureStdExtZvl65536b = 140,

  FeatureTaggedGlobals = 141,

  FeatureTrailingSeqCstFence = 142,

  FeatureVendorXCValu = 143,

  FeatureVendorXCVbi = 144,

  FeatureVendorXCVbitmanip = 145,

  FeatureVendorXCVelw = 146,

  FeatureVendorXCVmac = 147,

  FeatureVendorXCVmem = 148,

  FeatureVendorXCVsimd = 149,

  FeatureVendorXSfvcp = 150,

  FeatureVendorXSfvfnrclipxfqf = 151,

  FeatureVendorXSfvfwmaccqqq = 152,

  FeatureVendorXSfvqmaccdod = 153,

  FeatureVendorXSfvqmaccqoq = 154,

  FeatureVendorXTHeadBa = 155,

  FeatureVendorXTHeadBb = 156,

  FeatureVendorXTHeadBs = 157,

  FeatureVendorXTHeadCmo = 158,

  FeatureVendorXTHeadCondMov = 159,

  FeatureVendorXTHeadFMemIdx = 160,

  FeatureVendorXTHeadMac = 161,

  FeatureVendorXTHeadMemIdx = 162,

  FeatureVendorXTHeadMemPair = 163,

  FeatureVendorXTHeadSync = 164,

  FeatureVendorXTHeadVdot = 165,

  FeatureVendorXVentanaCondOps = 166,

  TuneAUIPCADDIFusion = 167,

  TuneConditionalCompressedMoveFusion = 168,

  TuneDLenFactor2 = 169,

  TuneLDADDFusion = 170,

  TuneLUIADDIFusion = 171,

  TuneNoDefaultUnroll = 172,

  TuneNoOptimizedZeroStrideLoad = 173,

  TuneShiftedZExtWFusion = 174,

  TuneShortForwardBranchOpt = 175,

  TuneSiFive7 = 176,

  TuneVentanaVeyron = 177,

  TuneZExtHFusion = 178,

  TuneZExtWFusion = 179,

  NumSubtargetFeatures = 180

};

} // end namespace RISCV

} // end namespace llvm

#endif // GET_SUBTARGETINFO_ENUM

#ifdef GET_SUBTARGETINFO_MACRO

GET_SUBTARGETINFO_MACRO(AllowTaggedGlobals, false, allowTaggedGlobals)

GET_SUBTARGETINFO_MACRO(DLenFactor2, false, dLenFactor2)

GET_SUBTARGETINFO_MACRO(EnableDefaultUnroll, true, enableDefaultUnroll)

GET_SUBTARGETINFO_MACRO(EnableLinkerRelax, false, enableLinkerRelax)

GET_SUBTARGETINFO_MACRO(EnableRVCHintInstrs, true, enableRVCHintInstrs)

GET_SUBTARGETINFO_MACRO(EnableSaveRestore, false, enableSaveRestore)

GET_SUBTARGETINFO_MACRO(EnableSeqCstTrailingFence, false, enableSeqCstTrailingFence)

GET_SUBTARGETINFO_MACRO(HasAUIPCADDIFusion, false, hasAUIPCADDIFusion)

GET_SUBTARGETINFO_MACRO(HasConditionalCompressedMoveFusion, false, hasConditionalCompressedMoveFusion)

GET_SUBTARGETINFO_MACRO(HasExperimental, false, hasExperimental)

GET_SUBTARGETINFO_MACRO(HasFastUnalignedAccess, false, hasFastUnalignedAccess)

GET_SUBTARGETINFO_MACRO(HasForcedAtomics, false, hasForcedAtomics)

GET_SUBTARGETINFO_MACRO(HasLDADDFusion, false, hasLDADDFusion)

GET_SUBTARGETINFO_MACRO(HasLUIADDIFusion, false, hasLUIADDIFusion)

GET_SUBTARGETINFO_MACRO(HasOptimizedZeroStrideLoad, true, hasOptimizedZeroStrideLoad)

GET_SUBTARGETINFO_MACRO(HasShiftedZExtWFusion, false, hasShiftedZExtWFusion)

GET_SUBTARGETINFO_MACRO(HasShortForwardBranchOpt, false, hasShortForwardBranchOpt)

GET_SUBTARGETINFO_MACRO(HasStdExtA, false, hasStdExtA)

GET_SUBTARGETINFO_MACRO(HasStdExtC, false, hasStdExtC)

GET_SUBTARGETINFO_MACRO(HasStdExtD, false, hasStdExtD)

GET_SUBTARGETINFO_MACRO(HasStdExtF, false, hasStdExtF)

GET_SUBTARGETINFO_MACRO(HasStdExtH, false, hasStdExtH)

GET_SUBTARGETINFO_MACRO(HasStdExtI, false, hasStdExtI)

GET_SUBTARGETINFO_MACRO(HasStdExtM, false, hasStdExtM)

GET_SUBTARGETINFO_MACRO(HasStdExtSmaia, false, hasStdExtSmaia)

GET_SUBTARGETINFO_MACRO(HasStdExtSsaia, false, hasStdExtSsaia)

GET_SUBTARGETINFO_MACRO(HasStdExtSvinval, false, hasStdExtSvinval)

GET_SUBTARGETINFO_MACRO(HasStdExtSvnapot, false, hasStdExtSvnapot)

GET_SUBTARGETINFO_MACRO(HasStdExtSvpbmt, false, hasStdExtSvpbmt)

GET_SUBTARGETINFO_MACRO(HasStdExtV, false, hasStdExtV)

GET_SUBTARGETINFO_MACRO(HasStdExtZacas, false, hasStdExtZacas)

GET_SUBTARGETINFO_MACRO(HasStdExtZawrs, false, hasStdExtZawrs)

GET_SUBTARGETINFO_MACRO(HasStdExtZba, false, hasStdExtZba)

GET_SUBTARGETINFO_MACRO(HasStdExtZbb, false, hasStdExtZbb)

GET_SUBTARGETINFO_MACRO(HasStdExtZbc, false, hasStdExtZbc)

GET_SUBTARGETINFO_MACRO(HasStdExtZbkb, false, hasStdExtZbkb)

GET_SUBTARGETINFO_MACRO(HasStdExtZbkc, false, hasStdExtZbkc)

GET_SUBTARGETINFO_MACRO(HasStdExtZbkx, false, hasStdExtZbkx)

GET_SUBTARGETINFO_MACRO(HasStdExtZbs, false, hasStdExtZbs)

GET_SUBTARGETINFO_MACRO(HasStdExtZca, false, hasStdExtZca)

GET_SUBTARGETINFO_MACRO(HasStdExtZcb, false, hasStdExtZcb)

GET_SUBTARGETINFO_MACRO(HasStdExtZcd, false, hasStdExtZcd)

GET_SUBTARGETINFO_MACRO(HasStdExtZce, false, hasStdExtZce)

GET_SUBTARGETINFO_MACRO(HasStdExtZcf, false, hasStdExtZcf)

GET_SUBTARGETINFO_MACRO(HasStdExtZcmop, false, hasStdExtZcmop)

GET_SUBTARGETINFO_MACRO(HasStdExtZcmp, false, hasStdExtZcmp)

GET_SUBTARGETINFO_MACRO(HasStdExtZcmt, false, hasStdExtZcmt)

GET_SUBTARGETINFO_MACRO(HasStdExtZdinx, false, hasStdExtZdinx)

GET_SUBTARGETINFO_MACRO(HasStdExtZfa, false, hasStdExtZfa)

GET_SUBTARGETINFO_MACRO(HasStdExtZfbfmin, false, hasStdExtZfbfmin)

GET_SUBTARGETINFO_MACRO(HasStdExtZfh, false, hasStdExtZfh)

GET_SUBTARGETINFO_MACRO(HasStdExtZfhmin, false, hasStdExtZfhmin)

GET_SUBTARGETINFO_MACRO(HasStdExtZfinx, false, hasStdExtZfinx)

GET_SUBTARGETINFO_MACRO(HasStdExtZhinx, false, hasStdExtZhinx)

GET_SUBTARGETINFO_MACRO(HasStdExtZhinxmin, false, hasStdExtZhinxmin)

GET_SUBTARGETINFO_MACRO(HasStdExtZicbom, false, hasStdExtZicbom)

GET_SUBTARGETINFO_MACRO(HasStdExtZicbop, false, hasStdExtZicbop)

GET_SUBTARGETINFO_MACRO(HasStdExtZicboz, false, hasStdExtZicboz)

GET_SUBTARGETINFO_MACRO(HasStdExtZicfilp, false, hasStdExtZicfilp)

GET_SUBTARGETINFO_MACRO(HasStdExtZicfiss, false, hasStdExtZicfiss)

GET_SUBTARGETINFO_MACRO(HasStdExtZicntr, false, hasStdExtZicntr)

GET_SUBTARGETINFO_MACRO(HasStdExtZicond, false, hasStdExtZicond)

GET_SUBTARGETINFO_MACRO(HasStdExtZicsr, false, hasStdExtZicsr)

GET_SUBTARGETINFO_MACRO(HasStdExtZifencei, false, hasStdExtZifencei)

GET_SUBTARGETINFO_MACRO(HasStdExtZihintntl, false, hasStdExtZihintntl)

GET_SUBTARGETINFO_MACRO(HasStdExtZihintpause, false, hasStdExtZihintpause)

GET_SUBTARGETINFO_MACRO(HasStdExtZihpm, false, hasStdExtZihpm)

GET_SUBTARGETINFO_MACRO(HasStdExtZimop, false, hasStdExtZimop)

GET_SUBTARGETINFO_MACRO(HasStdExtZk, false, hasStdExtZk)

GET_SUBTARGETINFO_MACRO(HasStdExtZkn, false, hasStdExtZkn)

GET_SUBTARGETINFO_MACRO(HasStdExtZknd, false, hasStdExtZknd)

GET_SUBTARGETINFO_MACRO(HasStdExtZkne, false, hasStdExtZkne)

GET_SUBTARGETINFO_MACRO(HasStdExtZknh, false, hasStdExtZknh)

GET_SUBTARGETINFO_MACRO(HasStdExtZkr, false, hasStdExtZkr)

GET_SUBTARGETINFO_MACRO(HasStdExtZks, false, hasStdExtZks)

GET_SUBTARGETINFO_MACRO(HasStdExtZksed, false, hasStdExtZksed)

GET_SUBTARGETINFO_MACRO(HasStdExtZksh, false, hasStdExtZksh)

GET_SUBTARGETINFO_MACRO(HasStdExtZkt, false, hasStdExtZkt)

GET_SUBTARGETINFO_MACRO(HasStdExtZmmul, false, hasStdExtZmmul)

GET_SUBTARGETINFO_MACRO(HasStdExtZtso, false, hasStdExtZtso)

GET_SUBTARGETINFO_MACRO(HasStdExtZvbb, false, hasStdExtZvbb)

GET_SUBTARGETINFO_MACRO(HasStdExtZvbc, false, hasStdExtZvbc)

GET_SUBTARGETINFO_MACRO(HasStdExtZve32f, false, hasStdExtZve32f)

GET_SUBTARGETINFO_MACRO(HasStdExtZve32x, false, hasStdExtZve32x)

GET_SUBTARGETINFO_MACRO(HasStdExtZve64d, false, hasStdExtZve64d)

GET_SUBTARGETINFO_MACRO(HasStdExtZve64f, false, hasStdExtZve64f)

GET_SUBTARGETINFO_MACRO(HasStdExtZve64x, false, hasStdExtZve64x)

GET_SUBTARGETINFO_MACRO(HasStdExtZvfbfmin, false, hasStdExtZvfbfmin)

GET_SUBTARGETINFO_MACRO(HasStdExtZvfbfwma, false, hasStdExtZvfbfwma)

GET_SUBTARGETINFO_MACRO(HasStdExtZvfh, false, hasStdExtZvfh)

GET_SUBTARGETINFO_MACRO(HasStdExtZvfhmin, false, hasStdExtZvfhmin)

GET_SUBTARGETINFO_MACRO(HasStdExtZvkb, false, hasStdExtZvkb)

GET_SUBTARGETINFO_MACRO(HasStdExtZvkg, false, hasStdExtZvkg)

GET_SUBTARGETINFO_MACRO(HasStdExtZvkn, false, hasStdExtZvkn)

GET_SUBTARGETINFO_MACRO(HasStdExtZvknc, false, hasStdExtZvknc)

GET_SUBTARGETINFO_MACRO(HasStdExtZvkned, false, hasStdExtZvkned)

GET_SUBTARGETINFO_MACRO(HasStdExtZvkng, false, hasStdExtZvkng)

GET_SUBTARGETINFO_MACRO(HasStdExtZvknha, false, hasStdExtZvknha)

GET_SUBTARGETINFO_MACRO(HasStdExtZvknhb, false, hasStdExtZvknhb)

GET_SUBTARGETINFO_MACRO(HasStdExtZvks, false, hasStdExtZvks)

GET_SUBTARGETINFO_MACRO(HasStdExtZvksc, false, hasStdExtZvksc)

GET_SUBTARGETINFO_MACRO(HasStdExtZvksed, false, hasStdExtZvksed)

GET_SUBTARGETINFO_MACRO(HasStdExtZvksg, false, hasStdExtZvksg)

GET_SUBTARGETINFO_MACRO(HasStdExtZvksh, false, hasStdExtZvksh)

GET_SUBTARGETINFO_MACRO(HasStdExtZvkt, false, hasStdExtZvkt)

GET_SUBTARGETINFO_MACRO(HasVendorXCValu, false, hasVendorXCValu)

GET_SUBTARGETINFO_MACRO(HasVendorXCVbi, false, hasVendorXCVbi)

GET_SUBTARGETINFO_MACRO(HasVendorXCVbitmanip, false, hasVendorXCVbitmanip)

GET_SUBTARGETINFO_MACRO(HasVendorXCVelw, false, hasVendorXCVelw)

GET_SUBTARGETINFO_MACRO(HasVendorXCVmac, false, hasVendorXCVmac)

GET_SUBTARGETINFO_MACRO(HasVendorXCVmem, false, hasVendorXCVmem)

GET_SUBTARGETINFO_MACRO(HasVendorXCvsimd, false, hasVendorXCvsimd)

GET_SUBTARGETINFO_MACRO(HasVendorXSfvcp, false, hasVendorXSfvcp)

GET_SUBTARGETINFO_MACRO(HasVendorXSfvfnrclipxfqf, false, hasVendorXSfvfnrclipxfqf)

GET_SUBTARGETINFO_MACRO(HasVendorXSfvfwmaccqqq, false, hasVendorXSfvfwmaccqqq)

GET_SUBTARGETINFO_MACRO(HasVendorXSfvqmaccdod, false, hasVendorXSfvqmaccdod)

GET_SUBTARGETINFO_MACRO(HasVendorXSfvqmaccqoq, false, hasVendorXSfvqmaccqoq)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadBa, false, hasVendorXTHeadBa)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadBb, false, hasVendorXTHeadBb)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadBs, false, hasVendorXTHeadBs)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadCmo, false, hasVendorXTHeadCmo)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadCondMov, false, hasVendorXTHeadCondMov)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadFMemIdx, false, hasVendorXTHeadFMemIdx)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadMac, false, hasVendorXTHeadMac)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadMemIdx, false, hasVendorXTHeadMemIdx)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadMemPair, false, hasVendorXTHeadMemPair)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadSync, false, hasVendorXTHeadSync)

GET_SUBTARGETINFO_MACRO(HasVendorXTHeadVdot, false, hasVendorXTHeadVdot)

GET_SUBTARGETINFO_MACRO(HasVendorXVentanaCondOps, false, hasVendorXVentanaCondOps)

GET_SUBTARGETINFO_MACRO(HasZExtHFusion, false, hasZExtHFusion)

GET_SUBTARGETINFO_MACRO(HasZExtWFusion, false, hasZExtWFusion)

GET_SUBTARGETINFO_MACRO(IsRV32, false, isRV32)

GET_SUBTARGETINFO_MACRO(IsRV64, false, isRV64)

GET_SUBTARGETINFO_MACRO(IsRVE, false, isRVE)

GET_SUBTARGETINFO_MACRO(UsePostRAScheduler, false, usePostRAScheduler)

#undef GET_SUBTARGETINFO_MACRO

#endif // GET_SUBTARGETINFO_MACRO

#ifdef GET_SUBTARGETINFO_MC_DESC

#undef GET_SUBTARGETINFO_MC_DESC

namespace llvm {

// Sorted (by key) array of values for CPU features.

extern const llvm::SubtargetFeatureKV RISCVFeatureKV[] = {

  { "32bit", "Implements RV32", RISCV::Feature32Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "64bit", "Implements RV64", RISCV::Feature64Bit, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "a", "'A' (Atomic Instructions)", RISCV::FeatureStdExtA, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "auipc-addi-fusion", "Enable AUIPC+ADDI macrofusion", RISCV::TuneAUIPCADDIFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "c", "'C' (Compressed Instructions)", RISCV::FeatureStdExtC, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "conditional-cmv-fusion", "Enable branch+c.mv fusion", RISCV::TuneConditionalCompressedMoveFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "d", "'D' (Double-Precision Floating-Point)", RISCV::FeatureStdExtD, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "dlen-factor-2", "Vector unit DLEN(data path width) is half of VLEN", RISCV::TuneDLenFactor2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "e", "Implements RV{32,64}E (provides 16 rather than 32 GPRs)", RISCV::FeatureRVE, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental", "Experimental intrinsics", RISCV::Experimental, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zacas", "'Zacas' (Atomic Compare-And-Swap Instructions)", RISCV::FeatureStdExtZacas, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zcmop", "'Zcmop' (Compressed May-Be-Operations)", RISCV::FeatureStdExtZcmop, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zfbfmin", "'Zfbfmin' (Scalar BF16 Converts)", RISCV::FeatureStdExtZfbfmin, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zicfilp", "'Zicfilp' (Landing pad)", RISCV::FeatureStdExtZicfilp, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zicfiss", "'Zicfiss' (Shadow stack)", RISCV::FeatureStdExtZicfiss, { { { 0x0ULL, 0x8400000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zicond", "'Zicond' (Integer Conditional Operations)", RISCV::FeatureStdExtZicond, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zimop", "'Zimop' (May-Be-Operations)", RISCV::FeatureStdExtZimop, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-ztso", "'Ztso' (Memory Model - Total Store Order)", RISCV::FeatureStdExtZtso, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zvfbfmin", "'Zvbfmin' (Vector BF16 Converts)", RISCV::FeatureStdExtZvfbfmin, { { { 0x0ULL, 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "experimental-zvfbfwma", "'Zvfbfwma' (Vector BF16 widening mul-add)", RISCV::FeatureStdExtZvfbfwma, { { { 0x0ULL, 0x800000000200ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "f", "'F' (Single-Precision Floating-Point)", RISCV::FeatureStdExtF, { { { 0x0ULL, 0x400000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "fast-unaligned-access", "Has reasonably performant unaligned loads and stores (both scalar and vector)", RISCV::FeatureFastUnalignedAccess, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "forced-atomics", "Assume that lock-free native-width atomics are available", RISCV::FeatureForcedAtomics, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "h", "'H' (Hypervisor)", RISCV::FeatureStdExtH, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "i", "'I' (Base Integer Instruction Set)", RISCV::FeatureStdExtI, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ld-add-fusion", "Enable LD+ADD macrofusion.", RISCV::TuneLDADDFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "lui-addi-fusion", "Enable LUI+ADDI macrofusion", RISCV::TuneLUIADDIFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "m", "'M' (Integer Multiplication and Division)", RISCV::FeatureStdExtM, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "no-default-unroll", "Disable default unroll preference.", RISCV::TuneNoDefaultUnroll, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "no-optimized-zero-stride-load", "Hasn't optimized (perform fewer memory operations)zero-stride vector load", RISCV::TuneNoOptimizedZeroStrideLoad, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "no-rvc-hints", "Disable RVC Hint Instructions.", RISCV::FeatureNoRVCHints, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "relax", "Enable Linker relaxation.", RISCV::FeatureRelax, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x1", "Reserve X1", RISCV::FeatureReserveX1, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x10", "Reserve X10", RISCV::FeatureReserveX10, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x11", "Reserve X11", RISCV::FeatureReserveX11, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x12", "Reserve X12", RISCV::FeatureReserveX12, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x13", "Reserve X13", RISCV::FeatureReserveX13, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x14", "Reserve X14", RISCV::FeatureReserveX14, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x15", "Reserve X15", RISCV::FeatureReserveX15, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x16", "Reserve X16", RISCV::FeatureReserveX16, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x17", "Reserve X17", RISCV::FeatureReserveX17, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x18", "Reserve X18", RISCV::FeatureReserveX18, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x19", "Reserve X19", RISCV::FeatureReserveX19, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x2", "Reserve X2", RISCV::FeatureReserveX2, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x20", "Reserve X20", RISCV::FeatureReserveX20, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x21", "Reserve X21", RISCV::FeatureReserveX21, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x22", "Reserve X22", RISCV::FeatureReserveX22, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x23", "Reserve X23", RISCV::FeatureReserveX23, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x24", "Reserve X24", RISCV::FeatureReserveX24, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x25", "Reserve X25", RISCV::FeatureReserveX25, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x26", "Reserve X26", RISCV::FeatureReserveX26, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x27", "Reserve X27", RISCV::FeatureReserveX27, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x28", "Reserve X28", RISCV::FeatureReserveX28, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x29", "Reserve X29", RISCV::FeatureReserveX29, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x3", "Reserve X3", RISCV::FeatureReserveX3, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x30", "Reserve X30", RISCV::FeatureReserveX30, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x31", "Reserve X31", RISCV::FeatureReserveX31, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x4", "Reserve X4", RISCV::FeatureReserveX4, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x5", "Reserve X5", RISCV::FeatureReserveX5, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x6", "Reserve X6", RISCV::FeatureReserveX6, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x7", "Reserve X7", RISCV::FeatureReserveX7, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x8", "Reserve X8", RISCV::FeatureReserveX8, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "reserve-x9", "Reserve X9", RISCV::FeatureReserveX9, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "save-restore", "Enable save/restore.", RISCV::FeatureSaveRestore, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "seq-cst-trailing-fence", "Enable trailing fence for seq-cst store.", RISCV::FeatureTrailingSeqCstFence, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "shifted-zextw-fusion", "Enable SLLI+SRLI to be fused when computing (shifted) zero extension of word", RISCV::TuneShiftedZExtWFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "short-forward-branch-opt", "Enable short forward branch optimization", RISCV::TuneShortForwardBranchOpt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "sifive7", "SiFive 7-Series processors", RISCV::TuneSiFive7, { { { 0x0ULL, 0x0ULL, 0x900000000000ULL, 0x0ULL, 0x0ULL, } } } },

  { "smaia", "'Smaia' (Advanced Interrupt Architecture Machine Level)", RISCV::FeatureStdExtSmaia, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "ssaia", "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)", RISCV::FeatureStdExtSsaia, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "svinval", "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)", RISCV::FeatureStdExtSvinval, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "svnapot", "'Svnapot' (NAPOT Translation Contiguity)", RISCV::FeatureStdExtSvnapot, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "svpbmt", "'Svpbmt' (Page-Based Memory Types)", RISCV::FeatureStdExtSvpbmt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "tagged-globals", "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", RISCV::FeatureTaggedGlobals, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "use-postra-scheduler", "Schedule again after register allocation", RISCV::FeaturePostRAScheduler, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "v", "'V' (Vector Extension for Application Processors)", RISCV::FeatureStdExtV, { { { 0x0ULL, 0x100000000000ULL, 0x8ULL, 0x0ULL, 0x0ULL, } } } },

  { "ventana-veyron", "Ventana Veyron-Series processors", RISCV::TuneVentanaVeyron, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvalu", "'XCValu' (CORE-V ALU Operations)", RISCV::FeatureVendorXCValu, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvbi", "'XCVbi' (CORE-V Immediate Branching)", RISCV::FeatureVendorXCVbi, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvbitmanip", "'XCVbitmanip' (CORE-V Bit Manipulation)", RISCV::FeatureVendorXCVbitmanip, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvelw", "'XCVelw' (CORE-V Event Load Word)", RISCV::FeatureVendorXCVelw, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvmac", "'XCVmac' (CORE-V Multiply-Accumulate)", RISCV::FeatureVendorXCVmac, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvmem", "'XCVmem' (CORE-V Post-incrementing Load & Store)", RISCV::FeatureVendorXCVmem, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xcvsimd", "'XCVsimd' (CORE-V SIMD ALU)", RISCV::FeatureVendorXCVsimd, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xsfvcp", "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)", RISCV::FeatureVendorXSfvcp, { { { 0x0ULL, 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xsfvfnrclipxfqf", "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)", RISCV::FeatureVendorXSfvfnrclipxfqf, { { { 0x0ULL, 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xsfvfwmaccqqq", "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", RISCV::FeatureVendorXSfvfwmaccqqq, { { { 0x0ULL, 0x840000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xsfvqmaccdod", "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))", RISCV::FeatureVendorXSfvqmaccdod, { { { 0x0ULL, 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xsfvqmaccqoq", "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))", RISCV::FeatureVendorXSfvqmaccqoq, { { { 0x0ULL, 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadba", "'xtheadba' (T-Head address calculation instructions)", RISCV::FeatureVendorXTHeadBa, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadbb", "'xtheadbb' (T-Head basic bit-manipulation instructions)", RISCV::FeatureVendorXTHeadBb, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadbs", "'xtheadbs' (T-Head single-bit instructions)", RISCV::FeatureVendorXTHeadBs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadcmo", "'xtheadcmo' (T-Head cache management instructions)", RISCV::FeatureVendorXTHeadCmo, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadcondmov", "'xtheadcondmov' (T-Head conditional move instructions)", RISCV::FeatureVendorXTHeadCondMov, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadfmemidx", "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)", RISCV::FeatureVendorXTHeadFMemIdx, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadmac", "'xtheadmac' (T-Head Multiply-Accumulate Instructions)", RISCV::FeatureVendorXTHeadMac, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadmemidx", "'xtheadmemidx' (T-Head Indexed Memory Operations)", RISCV::FeatureVendorXTHeadMemIdx, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadmempair", "'xtheadmempair' (T-Head two-GPR Memory Operations)", RISCV::FeatureVendorXTHeadMemPair, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadsync", "'xtheadsync' (T-Head multicore synchronization instructions)", RISCV::FeatureVendorXTHeadSync, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xtheadvdot", "'xtheadvdot' (T-Head Vector Extensions for Dot)", RISCV::FeatureVendorXTHeadVdot, { { { 0x20000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "xventanacondops", "'XVentanaCondOps' (Ventana Conditional Ops)", RISCV::FeatureVendorXVentanaCondOps, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zawrs", "'Zawrs' (Wait on Reservation Set)", RISCV::FeatureStdExtZawrs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zba", "'Zba' (Address Generation Instructions)", RISCV::FeatureStdExtZba, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zbb", "'Zbb' (Basic Bit-Manipulation)", RISCV::FeatureStdExtZbb, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zbc", "'Zbc' (Carry-Less Multiplication)", RISCV::FeatureStdExtZbc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zbkb", "'Zbkb' (Bitmanip instructions for Cryptography)", RISCV::FeatureStdExtZbkb, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zbkc", "'Zbkc' (Carry-less multiply instructions for Cryptography)", RISCV::FeatureStdExtZbkc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zbkx", "'Zbkx' (Crossbar permutation instructions)", RISCV::FeatureStdExtZbkx, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zbs", "'Zbs' (Single-Bit Instructions)", RISCV::FeatureStdExtZbs, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zca", "'Zca' (part of the C extension, excluding compressed floating point loads/stores)", RISCV::FeatureStdExtZca, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zcb", "'Zcb' (Compressed basic bit manipulation instructions)", RISCV::FeatureStdExtZcb, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zcd", "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", RISCV::FeatureStdExtZcd, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zce", "'Zce' (Compressed extensions for microcontrollers)", RISCV::FeatureStdExtZce, { { { 0x8000000000000000ULL, 0x61ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zcf", "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", RISCV::FeatureStdExtZcf, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zcmp", "'Zcmp' (sequenced instuctions for code-size reduction)", RISCV::FeatureStdExtZcmp, { { { 0x8000000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zcmt", "'Zcmt' (table jump instuctions for code-size reduction)", RISCV::FeatureStdExtZcmt, { { { 0x8000000000000000ULL, 0x400000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zdinx", "'Zdinx' (Double in Integer)", RISCV::FeatureStdExtZdinx, { { { 0x0ULL, 0x1000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zexth-fusion", "Enable SLLI+SRLI to be fused to zero extension of halfword", RISCV::TuneZExtHFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zextw-fusion", "Enable SLLI+SRLI to be fused to zero extension of word", RISCV::TuneZExtWFusion, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zfa", "'Zfa' (Additional Floating-Point)", RISCV::FeatureStdExtZfa, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zfh", "'Zfh' (Half-Precision Floating-Point)", RISCV::FeatureStdExtZfh, { { { 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zfhmin", "'Zfhmin' (Half-Precision Floating-Point Minimal)", RISCV::FeatureStdExtZfhmin, { { { 0x100000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zfinx", "'Zfinx' (Float in Integer)", RISCV::FeatureStdExtZfinx, { { { 0x0ULL, 0x400000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zhinx", "'Zhinx' (Half Float in Integer)", RISCV::FeatureStdExtZhinx, { { { 0x0ULL, 0x4000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zhinxmin", "'Zhinxmin' (Half Float in Integer Minimal)", RISCV::FeatureStdExtZhinxmin, { { { 0x0ULL, 0x1000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zicbom", "'Zicbom' (Cache-Block Management Instructions)", RISCV::FeatureStdExtZicbom, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zicbop", "'Zicbop' (Cache-Block Prefetch Instructions)", RISCV::FeatureStdExtZicbop, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zicboz", "'Zicboz' (Cache-Block Zero Instructions)", RISCV::FeatureStdExtZicboz, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zicntr", "'Zicntr' (Base Counters and Timers)", RISCV::FeatureStdExtZicntr, { { { 0x0ULL, 0x400000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zicsr", "'zicsr' (CSRs)", RISCV::FeatureStdExtZicsr, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zifencei", "'Zifencei' (fence.i)", RISCV::FeatureStdExtZifencei, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zihintntl", "'Zihintntl' (Non-Temporal Locality Hints)", RISCV::FeatureStdExtZihintntl, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zihintpause", "'Zihintpause' (Pause Hint)", RISCV::FeatureStdExtZihintpause, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zihpm", "'Zihpm' (Hardware Performance Counters)", RISCV::FeatureStdExtZihpm, { { { 0x0ULL, 0x400000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zk", "'Zk' (Standard scalar cryptography extension)", RISCV::FeatureStdExtZk, { { { 0x0ULL, 0x2220000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zkn", "'Zkn' (NIST Algorithm Suite)", RISCV::FeatureStdExtZkn, { { { 0x3800000000000000ULL, 0x1c0000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zknd", "'Zknd' (NIST Suite: AES Decryption)", RISCV::FeatureStdExtZknd, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zkne", "'Zkne' (NIST Suite: AES Encryption)", RISCV::FeatureStdExtZkne, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zknh", "'Zknh' (NIST Suite: Hash Function Instructions)", RISCV::FeatureStdExtZknh, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zkr", "'Zkr' (Entropy Source Extension)", RISCV::FeatureStdExtZkr, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zks", "'Zks' (ShangMi Algorithm Suite)", RISCV::FeatureStdExtZks, { { { 0x3800000000000000ULL, 0x1800000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zksed", "'Zksed' (ShangMi Suite: SM4 Block Cipher Instructions)", RISCV::FeatureStdExtZksed, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zksh", "'Zksh' (ShangMi Suite: SM3 Hash Function Instructions)", RISCV::FeatureStdExtZksh, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zkt", "'Zkt' (Data Independent Execution Latency)", RISCV::FeatureStdExtZkt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zmmul", "'Zmmul' (Integer Multiplication)", RISCV::FeatureStdExtZmmul, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvbb", "'Zvbb' (Vector basic bit-manipulation instructions)", RISCV::FeatureStdExtZvbb, { { { 0x0ULL, 0x8000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvbc", "'Zvbc' (Vector Carryless Multiplication)", RISCV::FeatureStdExtZvbc, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zve32f", "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)", RISCV::FeatureStdExtZve32f, { { { 0x100000000000ULL, 0x80000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zve32x", "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)", RISCV::FeatureStdExtZve32x, { { { 0x0ULL, 0x400000ULL, 0x2ULL, 0x0ULL, 0x0ULL, } } } },

  { "zve64d", "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)", RISCV::FeatureStdExtZve64d, { { { 0x80000000000ULL, 0x200000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zve64f", "'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension)", RISCV::FeatureStdExtZve64f, { { { 0x0ULL, 0x440000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zve64x", "'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW)", RISCV::FeatureStdExtZve64x, { { { 0x0ULL, 0x80000000000ULL, 0x4ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvfh", "'Zvfh' (Vector Half-Precision Floating-Point)", RISCV::FeatureStdExtZvfh, { { { 0x0ULL, 0x4000000000800ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvfhmin", "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)", RISCV::FeatureStdExtZvfhmin, { { { 0x0ULL, 0x40000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvkb", "'Zvkb' (Vector Bit-manipulation used in Cryptography)", RISCV::FeatureStdExtZvkb, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvkg", "'Zvkg' (Vector GCM instructions for Cryptography)", RISCV::FeatureStdExtZvkg, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvkn", "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')", RISCV::FeatureStdExtZvkn, { { { 0x0ULL, 0x488000000000000ULL, 0x1ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvknc", "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')", RISCV::FeatureStdExtZvknc, { { { 0x0ULL, 0x20020000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvkned", "'Zvkned' (Vector AES Encryption & Decryption (Single Round))", RISCV::FeatureStdExtZvkned, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvkng", "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')", RISCV::FeatureStdExtZvkng, { { { 0x0ULL, 0x30000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvknha", "'Zvknha' (Vector SHA-2 (SHA-256 only))", RISCV::FeatureStdExtZvknha, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvknhb", "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", RISCV::FeatureStdExtZvknhb, { { { 0x0ULL, 0x400000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvks", "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')", RISCV::FeatureStdExtZvks, { { { 0x0ULL, 0xa008000000000000ULL, 0x1ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvksc", "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')", RISCV::FeatureStdExtZvksc, { { { 0x0ULL, 0x800020000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvksed", "'Zvksed' (SM4 Block Cipher Instructions)", RISCV::FeatureStdExtZvksed, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvksg", "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')", RISCV::FeatureStdExtZvksg, { { { 0x0ULL, 0x810000000000000ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvksh", "'Zvksh' (SM3 Hash Function Instructions)", RISCV::FeatureStdExtZvksh, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvkt", "'Zvkt' (Vector Data-Independent Execution Latency)", RISCV::FeatureStdExtZvkt, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl1024b", "'Zvl' (Minimum Vector Length) 1024", RISCV::FeatureStdExtZvl1024b, { { { 0x0ULL, 0x0ULL, 0x20ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl128b", "'Zvl' (Minimum Vector Length) 128", RISCV::FeatureStdExtZvl128b, { { { 0x0ULL, 0x0ULL, 0x4ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl16384b", "'Zvl' (Minimum Vector Length) 16384", RISCV::FeatureStdExtZvl16384b, { { { 0x0ULL, 0x0ULL, 0x200ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl2048b", "'Zvl' (Minimum Vector Length) 2048", RISCV::FeatureStdExtZvl2048b, { { { 0x0ULL, 0x0ULL, 0x40ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl256b", "'Zvl' (Minimum Vector Length) 256", RISCV::FeatureStdExtZvl256b, { { { 0x0ULL, 0x0ULL, 0x8ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl32768b", "'Zvl' (Minimum Vector Length) 32768", RISCV::FeatureStdExtZvl32768b, { { { 0x0ULL, 0x0ULL, 0x400ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl32b", "'Zvl' (Minimum Vector Length) 32", RISCV::FeatureStdExtZvl32b, { { { 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl4096b", "'Zvl' (Minimum Vector Length) 4096", RISCV::FeatureStdExtZvl4096b, { { { 0x0ULL, 0x0ULL, 0x80ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl512b", "'Zvl' (Minimum Vector Length) 512", RISCV::FeatureStdExtZvl512b, { { { 0x0ULL, 0x0ULL, 0x10ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl64b", "'Zvl' (Minimum Vector Length) 64", RISCV::FeatureStdExtZvl64b, { { { 0x0ULL, 0x0ULL, 0x2ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl65536b", "'Zvl' (Minimum Vector Length) 65536", RISCV::FeatureStdExtZvl65536b, { { { 0x0ULL, 0x0ULL, 0x800ULL, 0x0ULL, 0x0ULL, } } } },

  { "zvl8192b", "'Zvl' (Minimum Vector Length) 8192", RISCV::FeatureStdExtZvl8192b, { { { 0x0ULL, 0x0ULL, 0x100ULL, 0x0ULL, 0x0ULL, } } } },

};

#ifdef DBGFIELD

#error "<target>GenSubtargetInfo.inc requires a DBGFIELD macro"

#endif

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

#define DBGFIELD(x) x,

#else

#define DBGFIELD(x)

#endif

// ===============================================================

// Data tables for the new per-operand machine model.

// {ProcResourceIdx, ReleaseAtCycle, AcquireAtCycle}

extern const llvm::MCWriteProcResEntry RISCVWriteProcResTable[] = {

  { 0,  0,  0 }, // Invalid

  { 1,  1,   0}, // #1

  { 2,  1,   0}, // #2

  { 7,  1,   0}, // #3

  { 6,  1,   0}, // #4

  { 5, 33,   0}, // #5

  { 5, 34,   0}, // #6

  { 3,  1,   0}, // #7

  { 4, 20,   0}, // #8

  { 4, 25,   0}, // #9

  { 7,  2,   0}, // #10

  { 4,  2,   0}, // #11

  { 5,  1,   0}, // #12

  { 3,  1,   0}, // #13

  { 4,  2,   0}, // #14

  { 5,  1,   0}, // #15

  { 4,  1,   0}, // #16

  { 4,  1,   0}, // #17

  { 5,  1,   0}, // #18

  { 6,  3,   1}, // #19

  { 7,  1,   0}, // #20

  { 6,  5,   1}, // #21

  { 7,  1,   0}, // #22

  { 6,  9,   1}, // #23

  { 7,  1,   0}, // #24

  { 6, 17,   1}, // #25

  { 7,  1,   0}, // #26

  { 6,  2,   1}, // #27

  { 7,  1,   0}, // #28

  { 6, 33,   1}, // #29

  { 7,  1,   0}, // #30

  { 6, 65,   1}, // #31

  { 7,  1,   0}, // #32

  { 6, 129,   1}, // #33

  { 7,  1,   0}, // #34

  { 6, 257,   1}, // #35

  { 7,  1,   0}, // #36

  { 6, 513,   1}, // #37

  { 7,  1,   0}, // #38

  { 6, 121,   1}, // #39

  { 7,  1,   0}, // #40

  { 6, 113,   1}, // #41

  { 7,  1,   0}, // #42

  { 6, 115,   1}, // #43

  { 7,  1,   0}, // #44

  { 6, 241,   1}, // #45

  { 7,  1,   0}, // #46

  { 6, 225,   1}, // #47

  { 7,  1,   0}, // #48

  { 6, 229,   1}, // #49

  { 7,  1,   0}, // #50

  { 6, 481,   1}, // #51

  { 7,  1,   0}, // #52

  { 6, 449,   1}, // #53

  { 7,  1,   0}, // #54

  { 6, 457,   1}, // #55

  { 7,  1,   0}, // #56

  { 6, 961,   1}, // #57

  { 7,  1,   0}, // #58

  { 6, 897,   1}, // #59

  { 7,  1,   0}, // #60

  { 6, 913,   1}, // #61

  { 7,  1,   0}, // #62

  { 6, 1921,   1}, // #63

  { 7,  1,   0}, // #64

  { 6, 61,   1}, // #65

  { 7,  1,   0}, // #66

  { 6, 57,   1}, // #67

  { 7,  1,   0}, // #68

  { 6, 31,   1}, // #69

  { 7,  1,   0}, // #70

  { 6, 43,   1}, // #71

  { 7,  1,   0}, // #72

  { 6, 38,   1}, // #73

  { 7,  1,   0}, // #74

  { 6, 45,   1}, // #75

  { 7,  1,   0}, // #76

  { 6, 40,   1}, // #77

  { 7,  1,   0}, // #78

  { 6, 35,   1}, // #79

  { 7,  1,   0}, // #80

  { 6, 49,   1}, // #81

  { 7,  1,   0}, // #82

  { 6, 44,   1}, // #83

  { 7,  1,   0}, // #84

  { 6, 39,   1}, // #85

  { 7,  1,   0}, // #86

  { 6, 52,   1}, // #87

  { 7,  1,   0}, // #88

  { 6, 47,   1}, // #89

  { 7,  1,   0}, // #90

  { 6, 42,   1}, // #91

  { 7,  1,   0}, // #92

  { 6, 37,   1}, // #93

  { 7,  1,   0}, // #94

  { 6, 193,   1}, // #95

  { 7,  1,   0}, // #96

  { 6, 97,   1}, // #97

  { 7,  1,   0}, // #98

  { 6, 385,   1}, // #99

  { 7,  1,   0}, // #100

  { 6, 769,   1}, // #101

  { 7,  1,   0}, // #102

  { 6, 1537,   1}, // #103

  { 7,  1,   0}, // #104

  { 7,  1,   0}, // #105

  { 8,  3,   1}, // #106

  { 7,  1,   0}, // #107

  { 8,  5,   1}, // #108

  { 7,  1,   0}, // #109

  { 8,  9,   1}, // #110

  { 7,  1,   0}, // #111

  { 8, 17,   1}, // #112

  { 7,  1,   0}, // #113

  { 8,  2,   1}, // #114

  { 7,  1,   0}, // #115

  { 8, 33,   1}, // #116

  { 7,  1,   0}, // #117

  { 8, 65,   1}, // #118

  { 7,  1,   0}, // #119

  { 8, 129,   1}, // #120

  { 7,  1,   0}, // #121

  { 8, 257,   1}, // #122

  { 7,  1,   0}, // #123

  { 8, 513,   1}, // #124

  { 6, 48,   1}, // #125

  { 7,  1,   0}, // #126

  { 6, 50,   1}, // #127

  { 7,  1,   0}, // #128

  { 6, 54,   1}, // #129

  { 7,  1,   0}, // #130

  { 6, 62,   1}, // #131

  { 7,  1,   0}, // #132

  { 7,  1,   0}, // #133

  { 9,  3,   1}, // #134

  { 7,  1,   0}, // #135

  { 9,  5,   1}, // #136

  { 7,  1,   0}, // #137

  { 9,  9,   1}, // #138

  { 7,  1,   0}, // #139

  { 9, 17,   1}, // #140

  { 7,  1,   0}, // #141

  { 9,  2,   1}, // #142

  { 3,  1,   0}, // #143

  { 4,  1,   0}, // #144

  { 7,  1,   0}, // #145

  { 9, 33,   1}, // #146

  { 7,  1,   0}, // #147

  { 9, 65,   1}, // #148

  { 7,  1,   0}, // #149

  { 9, 129,   1}, // #150

  { 7,  1,   0}, // #151

  { 9, 257,   1}, // #152

  { 7,  1,   0}, // #153

  { 9, 513,   1}, // #154

  { 2, 65,   0}, // #155

  { 4,  1,   0}, // #156

  { 5,  1,   0}, // #157

  { 2, 33,   0}, // #158

  { 4,  1,   0}, // #159

  { 5,  1,   0}, // #160

  { 1, 55,   0}, // #161

  { 4,  1,   0}, // #162

  { 5,  1,   0}, // #163

  { 1, 13,   0}, // #164

  { 4,  1,   0}, // #165

  { 5,  1,   0}, // #166

  { 1, 26,   0}, // #167

  { 4,  1,   0}, // #168

  { 5,  1,   0}, // #169

  { 3,  2,   0}, // #170

  { 4,  2,   0}, // #171

  { 4,  1,   0}, // #172

  { 7,  2,   0}, // #173

  { 8,  1,   0}, // #174

  { 6,  1,   0}, // #175

  { 7,  1,   0}, // #176

  { 5,  1,   0}, // #177

  { 7,  1,   0}, // #178

  { 9,  1,   0}, // #179

  { 1, 34,   0}, // #180

  { 6,  1,   0}, // #181

  { 7,  1,   0}, // #182

  { 1, 19,   0}, // #183

  { 6,  1,   0}, // #184

  { 7,  1,   0}, // #185

  { 2,  1,   0}, // #186

  { 3, 32,   0}, // #187

  { 2,  1,   0}, // #188

  { 3, 18,   0}, // #189

  { 2,  1,   0}, // #190

  { 3, 17,   0}, // #191

  { 8,  2,   0}, // #192

  { 9,  2,   0}, // #193

  { 4,  1,   0}, // #194

  { 5,  1,   0}, // #195

  { 7,  2,   0}, // #196

  { 3, 33,   0}, // #197

  { 4,  4,   0} // #198

}; // RISCVWriteProcResTable

// {Cycles, WriteResourceID}

extern const llvm::MCWriteLatencyEntry RISCVWriteLatencyTable[] = {

  { 0,  0}, // Invalid

  { 1, 152}, // #1 WriteIALU

  { 1,  0}, // #2 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WorstCase_WriteVSOXSEG2e64_WorstCase_WriteVSOXSEG2e8_WorstCase_WriteVSOXSEG3e16_WorstCase_WriteVSOXSEG3e32_WorstCase_WriteVSOXSEG3e64_WorstCase_WriteVSOXSEG3e8_WorstCase_WriteVSOXSEG4e16_WorstCase_WriteVSOXSEG4e32_WorstCase_WriteVSOXSEG4e64_WorstCase_WriteVSOXSEG4e8_WorstCase_WriteVSOXSEG5e16_WorstCase_WriteVSOXSEG5e32_WorstCase_WriteVSOXSEG5e64_WorstCase_WriteVSOXSEG5e8_WorstCase_WriteVSOXSEG6e16_WorstCase_WriteVSOXSEG6e32_WorstCase_WriteVSOXSEG6e64_WorstCase_WriteVSOXSEG6e8_WorstCase_WriteVSOXSEG7e16_WorstCase_WriteVSOXSEG7e32_WorstCase_WriteVSOXSEG7e64_WorstCase_WriteVSOXSEG7e8_WorstCase_WriteVSOXSEG8e16_WorstCase_WriteVSOXSEG8e32_WorstCase_WriteVSOXSEG8e64_WorstCase_WriteVSOXSEG8e8_WorstCase_WriteVSTS16_WorstCase_WriteVSTS32_WorstCase_WriteVSTS64_WorstCase_WriteVSTS8_WorstCase_WriteVSSEG2e16_WorstCase_WriteVSSEG2e32_WorstCase_WriteVSSEG2e64_WorstCase_WriteVSSEG2e8_WorstCase_WriteVSSEG3e16_WorstCase_WriteVSSEG3e32_WorstCase_WriteVSSEG3e64_WorstCase_WriteVSSEG3e8_WorstCase_WriteVSSEG4e16_WorstCase_WriteVSSEG4e32_WorstCase_WriteVSSEG4e64_WorstCase_WriteVSSEG4e8_WorstCase_WriteVSSEG5e16_WorstCase_WriteVSSEG5e32_WorstCase_WriteVSSEG5e64_WorstCase_WriteVSSEG5e8_WorstCase_WriteVSSEG6e16_WorstCase_WriteVSSEG6e32_WorstCase_WriteVSSEG6e64_WorstCase_WriteVSSEG6e8_WorstCase_WriteVSSEG7e16_WorstCase_WriteVSSEG7e32_WorstCase_WriteVSSEG7e64_WorstCase_WriteVSSEG7e8_WorstCase_WriteVSSEG8e16_WorstCase_WriteVSSEG8e32_WorstCase_WriteVSSEG8e64_WorstCase_WriteVSSEG8e8_WorstCase_WriteVSSSEG2e16_WorstCase_WriteVSSSEG2e32_WorstCase_WriteVSSSEG2e64_WorstCase_WriteVSSSEG2e8_WorstCase_WriteVSSSEG3e16_WorstCase_WriteVSSSEG3e32_WorstCase_WriteVSSSEG3e64_WorstCase_WriteVSSSEG3e8_WorstCase_WriteVSSSEG4e16_WorstCase_WriteVSSSEG4e32_WorstCase_WriteVSSSEG4e64_WorstCase_WriteVSSSEG4e8_WorstCase_WriteVSSSEG5e16_WorstCase_WriteVSSSEG5e32_WorstCase_WriteVSSSEG5e64_WorstCase_WriteVSSSEG5e8_WorstCase_WriteVSSSEG6e16_WorstCase_WriteVSSSEG6e32_WorstCase_WriteVSSSEG6e64_WorstCase_WriteVSSSEG6e8_WorstCase_WriteVSSSEG7e16_WorstCase_WriteVSSSEG7e32_WorstCase_WriteVSSSEG7e64_WorstCase_WriteVSSSEG7e8_WorstCase_WriteVSSSEG8e16_WorstCase_WriteVSSSEG8e32_WorstCase_WriteVSSSEG8e64_WorstCase_WriteVSSSEG8e8_WorstCase_WriteVSTUX16_WorstCase_WriteVSTUX32_WorstCase_WriteVSTUX64_WorstCase_WriteVSTUX8_WorstCase_WriteVSUXSEG2e16_WorstCase_WriteVSUXSEG2e32_WorstCase_WriteVSUXSEG2e64_WorstCase_WriteVSUXSEG2e8_WorstCase_WriteVSUXSEG3e16_WorstCase_WriteVSUXSEG3e32_WorstCase_WriteVSUXSEG3e64_WorstCase_WriteVSUXSEG3e8_WorstCase_WriteVSUXSEG4e16_WorstCase_WriteVSUXSEG4e32_WorstCase_WriteVSUXSEG4e64_WorstCase_WriteVSUXSEG4e8_WorstCase_WriteVSUXSEG5e16_WorstCase_WriteVSUXSEG5e32_WorstCase_WriteVSUXSEG5e64_WorstCase_WriteVSUXSEG5e8_WorstCase_WriteVSUXSEG6e16_WorstCase_WriteVSUXSEG6e32_WorstCase_WriteVSUXSEG6e64_WorstCase_WriteVSUXSEG6e8_WorstCase_WriteVSUXSEG7e16_WorstCase_WriteVSUXSEG7e32_WorstCase_WriteVSUXSEG7e64_WorstCase_WriteVSUXSEG7e8_WorstCase_WriteVSUXSEG8e16_WorstCase_WriteVSUXSEG8e32_WorstCase_WriteVSUXSEG8e64_WorstCase_WriteVSUXSEG8e8_WorstCase

  { 1, 153}, // #3 WriteIALU32

  { 2,  0}, // #4 WriteAtomicD_WriteAtomicW_WriteFLD64_WriteFLD32_WriteFClass64_WriteFClass32_WriteFCvtF64ToI32_WriteFCvtI64ToF64_WriteFCvtF32ToF64_WriteFCvtI32ToF64_WriteFCvtF64ToI64_WriteFCvtF32ToI64_WriteFCvtF64ToF32_WriteFCvtI64ToF32_WriteFCvtI32ToF32_WriteFCvtF32ToI32_WriteFCmp64_WriteFCmp32_WriteFMovF64ToI64_WriteFMovI64ToF64_WriteFMovI32ToF32_WriteFMovF32ToI32_WriteAtomicLDD_WriteAtomicLDW_WriteFLD16_WriteFClass16_WriteFCvtF32ToF16_WriteFCvtF16ToF64_WriteFCvtF64ToF16_WriteFCvtI64ToF16_WriteFCvtI32ToF16_WriteFCvtF16ToI64_WriteFCvtF16ToF32_WriteFCvtF16ToI32_WriteFCmp16_WriteFMinMax64_WriteFMinMax16_WriteFMinMax32_WriteFMovI16ToF16_WriteFMovF16ToI16_WriteFSGNJ64_WriteFSGNJ16_WriteFSGNJ32_P400WriteCMOV_WriteSTB_WriteSTD_WriteSTH_WriteSTW

  { 3, 161}, // #5 WriteLDB

  { 2, 162}, // #6 WriteLDD

  { 3, 163}, // #7 WriteLDH

  { 2, 164}, // #8 WriteLDW

  { 4, 156}, // #9 WriteIMul

  { 1, 182}, // #10 WriteShiftImm

  {33, 154}, // #11 WriteIDiv

  {34, 155}, // #12 WriteIDiv32

  { 6,  0}, // #13 WriteFAdd64_WriteFMinMax64_WriteFSGNJ64_WriteFLD64_WriteFLD32_WriteFLD16

  { 4,  0}, // #14 WriteFAdd32_WriteFMinMax32_WriteFSGNJ32_WriteVICALUI_M1_WriteVICALUI_M2_WriteVICALUI_M4_WriteVICALUI_M8_WriteVICALUI_MF2_WriteVICALUI_MF4_WriteVICALUI_MF8_WriteVICALUV_M1_WriteVICALUV_M2_WriteVICALUV_M4_WriteVICALUV_M8_WriteVICALUV_MF2_WriteVICALUV_MF4_WriteVICALUV_MF8_WriteVICALUX_M1_WriteVICALUX_M2_WriteVICALUX_M4_WriteVICALUX_M8_WriteVICALUX_MF2_WriteVICALUX_MF4_WriteVICALUX_MF8_WriteVIALUI_M1_WriteVIALUI_M2_WriteVIALUI_M4_WriteVIALUI_M8_WriteVIALUI_MF2_WriteVIALUI_MF4_WriteVIALUI_MF8_WriteVIALUV_M1_WriteVIALUV_M2_WriteVIALUV_M4_WriteVIALUV_M8_WriteVIALUV_MF2_WriteVIALUV_MF4_WriteVIALUV_MF8_WriteVIALUX_M1_WriteVIALUX_M2_WriteVIALUX_M4_WriteVIALUX_M8_WriteVIALUX_MF2_WriteVIALUX_MF4_WriteVIALUX_MF8_WriteVMPopV_MF8_WriteVMPopV_M2_WriteVMPopV_MF4_WriteVMPopV_M4_WriteVMPopV_MF2_WriteVMPopV_M8_WriteVMPopV_M1_WriteVFClassV_M1_WriteVFClassV_M2_WriteVFClassV_M4_WriteVFClassV_M8_WriteVFClassV_MF2_WriteVFClassV_MF4_WriteVMFFSV_MF8_WriteVMFFSV_M2_WriteVMFFSV_MF4_WriteVMFFSV_M4_WriteVMFFSV_MF2_WriteVMFFSV_M8_WriteVMFFSV_M1_WriteVFMinMaxF_M1_WriteVFMinMaxF_M2_WriteVFMinMaxF_M4_WriteVFMinMaxF_M8_WriteVFMinMaxF_MF2_WriteVFMinMaxF_MF4_WriteVFMinMaxV_M1_WriteVFMinMaxV_M2_WriteVFMinMaxV_M4_WriteVFMinMaxV_M8_WriteVFMinMaxV_MF2_WriteVFMinMaxV_MF4_WriteVFMergeV_M1_WriteVFMergeV_M2_WriteVFMergeV_M4_WriteVFMergeV_M8_WriteVFMergeV_MF2_WriteVFMergeV_MF4_WriteVFMovVF_WriteVFMovFV_WriteVFMovV_M1_WriteVFMovV_M2_WriteVFMovV_M4_WriteVFMovV_M8_WriteVFMovV_MF2_WriteVFMovV_MF4_WriteVFSgnjF_M1_WriteVFSgnjF_M2_WriteVFSgnjF_M4_WriteVFSgnjF_M8_WriteVFSgnjF_MF2_WriteVFSgnjF_MF4_WriteVFSgnjV_M1_WriteVFSgnjV_M2_WriteVFSgnjV_M4_WriteVFSgnjV_M8_WriteVFSgnjV_MF2_WriteVFSgnjV_MF4_WriteVFSlide1F_M1_WriteVFSlide1F_M2_WriteVFSlide1F_M4_WriteVFSlide1F_M8_WriteVFSlide1F_MF2_WriteVFSlide1F_MF4_WriteVMIdxV_M1_WriteVMIdxV_M2_WriteVMIdxV_M4_WriteVMIdxV_M8_WriteVMIdxV_MF2_WriteVMIdxV_MF4_WriteVMIdxV_MF8_WriteVMIotV_M1_WriteVMIotV_M2_WriteVMIotV_M4_WriteVMIotV_M8_WriteVMIotV_MF2_WriteVMIotV_MF4_WriteVMIotV_MF8_WriteVLDFF_M1_WriteVLDFF_M2_WriteVLDFF_M4_WriteVLDFF_M8_WriteVLDFF_MF2_WriteVLDFF_MF4_WriteVLDE_M1_WriteVLDE_M2_WriteVLDE_M4_WriteVLDE_M8_WriteVLDE_MF2_WriteVLDE_MF4_WriteVLDFF_MF8_WriteVLDE_MF8_WriteVLDM_MF8_WriteVLDM_M2_WriteVLDM_MF4_WriteVLDM_M4_WriteVLDM_MF2_WriteVLDM_M8_WriteVLDM_M1_WriteVLSEGFF2e16_MF4_WriteVLSEG2e16_MF4_WriteVLSEGFF2e8_MF4_WriteVLSEGFF2e8_MF8_WriteVLSEG2e8_MF4_WriteVLSEG2e8_MF8_WriteVIMulAddV_M1_WriteVIMulAddV_M2_WriteVIMulAddV_M4_WriteVIMulAddV_M8_WriteVIMulAddV_MF2_WriteVIMulAddV_MF4_WriteVIMulAddV_MF8_WriteVIMulAddX_M1_WriteVIMulAddX_M2_WriteVIMulAddX_M4_WriteVIMulAddX_M8_WriteVIMulAddX_MF2_WriteVIMulAddX_MF4_WriteVIMulAddX_MF8_WriteVMALUV_M1_WriteVMALUV_M2_WriteVMALUV_M4_WriteVMALUV_M8_WriteVMALUV_MF2_WriteVMALUV_MF4_WriteVMALUV_MF8_WriteVIMinMaxV_M1_WriteVIMinMaxV_M2_WriteVIMinMaxV_M4_WriteVIMinMaxV_M8_WriteVIMinMaxV_MF2_WriteVIMinMaxV_MF4_WriteVIMinMaxV_MF8_WriteVIMinMaxX_M1_WriteVIMinMaxX_M2_WriteVIMinMaxX_M4_WriteVIMinMaxX_M8_WriteVIMinMaxX_MF2_WriteVIMinMaxX_MF4_WriteVIMinMaxX_MF8_WriteVIMergeI_M1_WriteVIMergeI_M2_WriteVIMergeI_M4_WriteVIMergeI_M8_WriteVIMergeI_MF2_WriteVIMergeI_MF4_WriteVIMergeI_MF8_WriteVIMergeV_M1_WriteVIMergeV_M2_WriteVIMergeV_M4_WriteVIMergeV_M8_WriteVIMergeV_MF2_WriteVIMergeV_MF4_WriteVIMergeV_MF8_WriteVIMergeX_M1_WriteVIMergeX_M2_WriteVIMergeX_M4_WriteVIMergeX_M8_WriteVIMergeX_MF2_WriteVIMergeX_MF4_WriteVIMergeX_MF8_WriteVFCmpF_MF2_WriteVFCmpF_MF4_WriteVFCmpV_MF2_WriteVFCmpV_MF4_WriteVMSFSV_MF8_WriteVMSFSV_M2_WriteVMSFSV_MF4_WriteVMSFSV_M4_WriteVMSFSV_MF2_WriteVMSFSV_M8_WriteVMSFSV_M1_WriteVICmpI_MF2_WriteVICmpI_MF4_WriteVICmpI_MF8_WriteVICmpV_MF2_WriteVICmpV_MF4_WriteVICmpV_MF8_WriteVICmpX_MF2_WriteVICmpX_MF4_WriteVICmpX_MF8_WriteVIMulV_M1_WriteVIMulV_M2_WriteVIMulV_M4_WriteVIMulV_M8_WriteVIMulV_MF2_WriteVIMulV_MF4_WriteVIMulV_MF8_WriteVIMulX_M1_WriteVIMulX_M2_WriteVIMulX_M4_WriteVIMulX_M8_WriteVIMulX_MF2_WriteVIMulX_MF4_WriteVIMulX_MF8_WriteVIMovXV_WriteVIMovI_M1_WriteVIMovI_M2_WriteVIMovI_M4_WriteVIMovI_M8_WriteVIMovI_MF2_WriteVIMovI_MF4_WriteVIMovI_MF8_WriteVIMovV_M1_WriteVIMovV_M2_WriteVIMovV_M4_WriteVIMovV_M8_WriteVIMovV_MF2_WriteVIMovV_MF4_WriteVIMovV_MF8_WriteVIMovX_M1_WriteVIMovX_M2_WriteVIMovX_M4_WriteVIMovX_M8_WriteVIMovX_MF2_WriteVIMovX_MF4_WriteVIMovX_MF8_WriteVIMovVX_WriteVExtV_M1_WriteVExtV_M2_WriteVExtV_M4_WriteVExtV_M8_WriteVExtV_MF2_WriteVExtV_MF4_WriteVISlide1X_M1_WriteVISlide1X_M2_WriteVISlide1X_M4_WriteVISlide1X_M8_WriteVISlide1X_MF2_WriteVISlide1X_MF4_WriteVISlide1X_MF8_WriteVISlideI_M1_WriteVISlideI_M2_WriteVISlideI_M4_WriteVISlideI_M8_WriteVISlideI_MF2_WriteVISlideI_MF4_WriteVISlideI_MF8_WriteVISlideX_M1_WriteVISlideX_M2_WriteVISlideX_M4_WriteVISlideX_M8_WriteVISlideX_MF2_WriteVISlideX_MF4_WriteVISlideX_MF8_WriteVShiftI_M1_WriteVShiftI_M2_WriteVShiftI_M4_WriteVShiftI_M8_WriteVShiftI_MF2_WriteVShiftI_MF4_WriteVShiftI_MF8_WriteVShiftV_M1_WriteVShiftV_M2_WriteVShiftV_M4_WriteVShiftV_M8_WriteVShiftV_MF2_WriteVShiftV_MF4_WriteVShiftV_MF8_WriteVShiftX_M1_WriteVShiftX_M2_WriteVShiftX_M4_WriteVShiftX_M8_WriteVShiftX_MF2_WriteVShiftX_MF4_WriteVShiftX_MF8_WriteVICALUI_WorstCase_WriteVICALUV_WorstCase_WriteVICALUX_WorstCase_WriteVIALUI_WorstCase_WriteVIALUV_WorstCase_WriteVIALUX_WorstCase_WriteVMPopV_WorstCase_WriteVFClassV_WorstCase_WriteVMFFSV_WorstCase_WriteVFMinMaxF_WorstCase_WriteVFMinMaxV_WorstCase_WriteVFMergeV_WorstCase_WriteVFMovV_WorstCase_WriteVFSgnjF_WorstCase_WriteVFSgnjV_WorstCase_WriteVFSlide1F_WorstCase_WriteVMIdxV_WorstCase_WriteVMIotV_WorstCase_WriteVLD1R_WriteVLD2R_WriteVLD4R_WriteVLD8R_WriteVLDFF_WorstCase_WriteVLDE_WorstCase_WriteVLDM_WorstCase_WriteVIMulAddV_WorstCase_WriteVIMulAddX_WorstCase_WriteVMALUV_WorstCase_WriteVIMinMaxV_WorstCase_WriteVIMinMaxX_WorstCase_WriteVIMergeI_WorstCase_WriteVIMergeV_WorstCase_WriteVIMergeX_WorstCase_WriteVMSFSV_WorstCase_WriteVIMulV_WorstCase_WriteVIMulX_WorstCase_WriteVMov1V_WriteVMov2V_WriteVMov4V_WriteVMov8V_WriteVIMovI_WorstCase_WriteVIMovV_WorstCase_WriteVIMovX_WorstCase_WriteVExtV_WorstCase_WriteVISlide1X_WorstCase_WriteVISlideI_WorstCase_WriteVISlideX_WorstCase_WriteVShiftI_WorstCase_WriteVShiftV_WorstCase_WriteVShiftX_WorstCase_SiFive7WriteVLDS16_M1_Pred_SiFive7WriteVLDS16_M2_Pred_SiFive7WriteVLDS16_M4_Pred_SiFive7WriteVLDS16_M8_Pred_SiFive7WriteVLDS16_MF2_Pred_SiFive7WriteVLDS16_MF4_Pred_SiFive7WriteVLDS32_M1_Pred_SiFive7WriteVLDS32_M2_Pred_SiFive7WriteVLDS32_M4_Pred_SiFive7WriteVLDS32_M8_Pred_SiFive7WriteVLDS32_MF2_Pred_SiFive7WriteVLDS64_M1_Pred_SiFive7WriteVLDS64_M2_Pred_SiFive7WriteVLDS64_M4_Pred_SiFive7WriteVLDS64_M8_Pred_SiFive7WriteVLDS8_M1_Pred_SiFive7WriteVLDS8_M2_Pred_SiFive7WriteVLDS8_M4_Pred_SiFive7WriteVLDS8_M8_Pred_SiFive7WriteVLDS8_MF2_Pred_SiFive7WriteVLDS8_MF4_Pred_SiFive7WriteVLDS8_MF8_Pred_WriteFAdd64_WriteFAdd16_WriteFMA64_WriteFMA16_WriteFMA32_WriteFMul64_WriteFMul16_WriteFMul32

  {20,  0}, // #15 WriteFDiv64_WriteFDiv32_WriteFSqrt32

  { 7,  0}, // #16 WriteFMA64_WriteFMul64_WriteVLSEGFF2e16_M1_WriteVLSEG2e16_M1_WriteVLSEGFF2e32_M1_WriteVLSEG2e32_M1_WriteVLSEGFF2e64_M1_WriteVLSEG2e64_M1_WriteVLSEGFF2e8_M1_WriteVLSEG2e8_M1_WriteVFCmpF_M2_WriteVFCmpV_M2_WriteVICmpI_M2_WriteVICmpV_M2_WriteVICmpX_M2_WriteFAdd64

  { 5,  0}, // #17 WriteFMA32_WriteFMul32_WriteVLSEGFF2e16_MF2_WriteVLSEG2e16_MF2_WriteVLSEGFF2e32_MF2_WriteVLSEG2e32_MF2_WriteVLSEGFF2e8_MF2_WriteVLSEG2e8_MF2_WriteVFCmpF_M1_WriteVFCmpV_M1_WriteVICmpI_M1_WriteVICmpV_M1_WriteVICmpX_M1_WriteFAdd16_WriteFAdd32_WriteFMA16_WriteFMul16

  {25,  0}, // #18 WriteFSqrt64

  { 4, 157}, // #19 WriteIMul32

  { 1, 184}, // #20 WriteShiftReg

  { 1, 183}, // #21 WriteShiftImm32

  { 1, 185}, // #22 WriteShiftReg32

  { 2, 162}, // #23 WriteLDD

  { 2, 162}, // #24 WriteLDD

  { 2, 164}, // #25 WriteLDW

  { 2, 164}, // #26 WriteLDW

  { 1,  0}, // #27 WriteSTD_WriteSTW

  { 1,  0}, // #28 WriteSTD_WriteSTW

  { 3, 152}, // #29 WriteIALU

  { 3,  0}, // #30 WriteJalr_WriteRdVLENB_WriteVSETIVLI_WriteVSETVLI_WriteAtomicD_WriteAtomicW_WriteJmp_WriteFClass64_WriteFClass16_WriteFClass32_WriteFCvtF64ToI32_WriteFCvtF32ToF16_WriteFCvtF16ToF64_WriteFCvtI64ToF64_WriteFCvtF32ToF64_WriteFCvtI32ToF64_WriteFCvtF64ToF16_WriteFCvtI64ToF16_WriteFCvtI32ToF16_WriteFCvtF64ToI64_WriteFCvtF16ToI64_WriteFCvtF32ToI64_WriteFCvtF64ToF32_WriteFCvtF16ToF32_WriteFCvtI64ToF32_WriteFCvtI32ToF32_WriteFCvtF16ToI32_WriteFCvtF32ToI32_WriteFCmp64_WriteFCmp16_WriteFCmp32_WriteFMinMax64_WriteFMinMax16_WriteFMinMax32_WriteFMovF64ToI64_WriteFMovI64ToF64_WriteFMovI16ToF16_WriteFMovI32ToF32_WriteFMovF16ToI16_WriteFMovF32ToI32_WriteFSGNJ64_WriteFSGNJ16_WriteFSGNJ32_WriteAtomicLDD_WriteAtomicLDW_WriteAtomicSTD_WriteAtomicSTW

  { 3, 175}, // #31 WriteSFB

  { 8,  0}, // #32 WriteVAALUV_M1_WriteVAALUV_M2_WriteVAALUV_M4_WriteVAALUV_M8_WriteVAALUV_MF2_WriteVAALUV_MF4_WriteVAALUV_MF8_WriteVAALUX_M1_WriteVAALUX_M2_WriteVAALUX_M4_WriteVAALUX_M8_WriteVAALUX_MF2_WriteVAALUX_MF4_WriteVAALUX_MF8_WriteVFALUF_M1_WriteVFALUF_M2_WriteVFALUF_M4_WriteVFALUF_M8_WriteVFALUF_MF2_WriteVFALUF_MF4_WriteVFALUV_M1_WriteVFALUV_M2_WriteVFALUV_M4_WriteVFALUV_M8_WriteVFALUV_MF2_WriteVFALUV_MF4_WriteVFCvtIToFV_M1_WriteVFCvtIToFV_M2_WriteVFCvtIToFV_M4_WriteVFCvtIToFV_M8_WriteVFCvtIToFV_MF2_WriteVFCvtIToFV_MF4_WriteVFCvtFToIV_M1_WriteVFCvtFToIV_M2_WriteVFCvtFToIV_M4_WriteVFCvtFToIV_M8_WriteVFCvtFToIV_MF2_WriteVFCvtFToIV_MF4_WriteVFMulAddF_M1_WriteVFMulAddF_M2_WriteVFMulAddF_M4_WriteVFMulAddF_M8_WriteVFMulAddF_MF2_WriteVFMulAddF_MF4_WriteVFMulAddV_M1_WriteVFMulAddV_M2_WriteVFMulAddV_M4_WriteVFMulAddV_M8_WriteVFMulAddV_MF2_WriteVFMulAddV_MF4_WriteVFMulF_M1_WriteVFMulF_M2_WriteVFMulF_M4_WriteVFMulF_M8_WriteVFMulF_MF2_WriteVFMulF_MF4_WriteVFMulV_M1_WriteVFMulV_M2_WriteVFMulV_M4_WriteVFMulV_M8_WriteVFMulV_MF2_WriteVFMulV_MF4_WriteVFNCvtFToFV_M1_WriteVFNCvtFToFV_M2_WriteVFNCvtFToFV_M4_WriteVFNCvtFToFV_MF2_WriteVFNCvtFToFV_MF4_WriteVFNCvtIToFV_M1_WriteVFNCvtIToFV_M2_WriteVFNCvtIToFV_M4_WriteVFNCvtIToFV_MF2_WriteVFNCvtIToFV_MF4_WriteVFNCvtFToIV_M1_WriteVFNCvtFToIV_M2_WriteVFNCvtFToIV_M4_WriteVFNCvtFToIV_MF2_WriteVFNCvtFToIV_MF4_WriteVFNCvtFToIV_MF8_WriteVFRecpV_M1_WriteVFRecpV_M2_WriteVFRecpV_M4_WriteVFRecpV_M8_WriteVFRecpV_MF2_WriteVFRecpV_MF4_WriteVFWALUF_M1_WriteVFWALUF_M2_WriteVFWALUF_M4_WriteVFWALUF_MF2_WriteVFWALUF_MF4_WriteVFWALUV_M1_WriteVFWALUV_M2_WriteVFWALUV_M4_WriteVFWALUV_MF2_WriteVFWALUV_MF4_WriteVFWCvtFToFV_M1_WriteVFWCvtFToFV_M2_WriteVFWCvtFToFV_M4_WriteVFWCvtFToFV_MF2_WriteVFWCvtFToFV_MF4_WriteVFWCvtIToFV_M1_WriteVFWCvtIToFV_M2_WriteVFWCvtIToFV_M4_WriteVFWCvtIToFV_MF2_WriteVFWCvtIToFV_MF4_WriteVFWCvtIToFV_MF8_WriteVFWCvtFToIV_M1_WriteVFWCvtFToIV_M2_WriteVFWCvtFToIV_M4_WriteVFWCvtFToIV_MF2_WriteVFWCvtFToIV_MF4_WriteVFWMulAddF_M1_WriteVFWMulAddF_M2_WriteVFWMulAddF_M4_WriteVFWMulAddF_MF2_WriteVFWMulAddF_MF4_WriteVFWMulAddV_M1_WriteVFWMulAddV_M2_WriteVFWMulAddV_M4_WriteVFWMulAddV_MF2_WriteVFWMulAddV_MF4_WriteVFWMulF_M1_WriteVFWMulF_M2_WriteVFWMulF_M4_WriteVFWMulF_MF2_WriteVFWMulF_MF4_WriteVFWMulV_M1_WriteVFWMulV_M2_WriteVFWMulV_M4_WriteVFWMulV_MF2_WriteVFWMulV_MF4_WriteVNClipI_M1_WriteVNClipI_M2_WriteVNClipI_M4_WriteVNClipI_MF2_WriteVNClipI_MF4_WriteVNClipI_MF8_WriteVNClipV_M1_WriteVNClipV_M2_WriteVNClipV_M4_WriteVNClipV_MF2_WriteVNClipV_MF4_WriteVNClipV_MF8_WriteVNClipX_M1_WriteVNClipX_M2_WriteVNClipX_M4_WriteVNClipX_MF2_WriteVNClipX_MF4_WriteVNClipX_MF8_WriteVNShiftI_M1_WriteVNShiftI_M2_WriteVNShiftI_M4_WriteVNShiftI_MF2_WriteVNShiftI_MF4_WriteVNShiftI_MF8_WriteVNShiftV_M1_WriteVNShiftV_M2_WriteVNShiftV_M4_WriteVNShiftV_MF2_WriteVNShiftV_MF4_WriteVNShiftV_MF8_WriteVNShiftX_M1_WriteVNShiftX_M2_WriteVNShiftX_M4_WriteVNShiftX_MF2_WriteVNShiftX_MF4_WriteVNShiftX_MF8_WriteVRGatherVI_M1_WriteVRGatherVI_M2_WriteVRGatherVI_M4_WriteVRGatherVI_M8_WriteVRGatherVI_MF2_WriteVRGatherVI_MF4_WriteVRGatherVI_MF8_WriteVRGatherVX_M1_WriteVRGatherVX_M2_WriteVRGatherVX_M4_WriteVRGatherVX_M8_WriteVRGatherVX_MF2_WriteVRGatherVX_MF4_WriteVRGatherVX_MF8_WriteVSALUI_M1_WriteVSALUI_M2_WriteVSALUI_M4_WriteVSALUI_M8_WriteVSALUI_MF2_WriteVSALUI_MF4_WriteVSALUI_MF8_WriteVSALUV_M1_WriteVSALUV_M2_WriteVSALUV_M4_WriteVSALUV_M8_WriteVSALUV_MF2_WriteVSALUV_MF4_WriteVSALUV_MF8_WriteVSALUX_M1_WriteVSALUX_M2_WriteVSALUX_M4_WriteVSALUX_M8_WriteVSALUX_MF2_WriteVSALUX_MF4_WriteVSALUX_MF8_WriteVSMulV_M1_WriteVSMulV_M2_WriteVSMulV_M4_WriteVSMulV_M8_WriteVSMulV_MF2_WriteVSMulV_MF4_WriteVSMulV_MF8_WriteVSMulX_M1_WriteVSMulX_M2_WriteVSMulX_M4_WriteVSMulX_M8_WriteVSMulX_MF2_WriteVSMulX_MF4_WriteVSMulX_MF8_WriteVSShiftI_M1_WriteVSShiftI_M2_WriteVSShiftI_M4_WriteVSShiftI_M8_WriteVSShiftI_MF2_WriteVSShiftI_MF4_WriteVSShiftI_MF8_WriteVSShiftV_M1_WriteVSShiftV_M2_WriteVSShiftV_M4_WriteVSShiftV_M8_WriteVSShiftV_MF2_WriteVSShiftV_MF4_WriteVSShiftV_MF8_WriteVSShiftX_M1_WriteVSShiftX_M2_WriteVSShiftX_M4_WriteVSShiftX_M8_WriteVSShiftX_MF2_WriteVSShiftX_MF4_WriteVSShiftX_MF8_WriteVIWALUV_M1_WriteVIWALUV_M2_WriteVIWALUV_M4_WriteVIWALUV_MF2_WriteVIWALUV_MF4_WriteVIWALUV_MF8_WriteVIWALUX_M1_WriteVIWALUX_M2_WriteVIWALUX_M4_WriteVIWALUX_MF2_WriteVIWALUX_MF4_WriteVIWALUX_MF8_WriteVIWMulAddV_M1_WriteVIWMulAddV_M2_WriteVIWMulAddV_M4_WriteVIWMulAddV_MF2_WriteVIWMulAddV_MF4_WriteVIWMulAddV_MF8_WriteVIWMulAddX_M1_WriteVIWMulAddX_M2_WriteVIWMulAddX_M4_WriteVIWMulAddX_MF2_WriteVIWMulAddX_MF4_WriteVIWMulAddX_MF8_WriteVIWMulV_M1_WriteVIWMulV_M2_WriteVIWMulV_M4_WriteVIWMulV_MF2_WriteVIWMulV_MF4_WriteVIWMulV_MF8_WriteVIWMulX_M1_WriteVIWMulX_M2_WriteVIWMulX_M4_WriteVIWMulX_MF2_WriteVIWMulX_MF4_WriteVIWMulX_MF8_WriteVAALUV_WorstCase_WriteVAALUX_WorstCase_WriteVFALUF_WorstCase_WriteVFALUV_WorstCase_WriteVFCvtIToFV_WorstCase_WriteVFCvtFToIV_WorstCase_WriteVFMulAddF_WorstCase_WriteVFMulAddV_WorstCase_WriteVFMulF_WorstCase_WriteVFMulV_WorstCase_WriteVFNCvtFToFV_WorstCase_WriteVFNCvtIToFV_WorstCase_WriteVFNCvtFToIV_WorstCase_WriteVFRecpV_WorstCase_WriteVFWALUF_WorstCase_WriteVFWALUV_WorstCase_WriteVFWCvtFToFV_WorstCase_WriteVFWCvtIToFV_WorstCase_WriteVFWCvtFToIV_WorstCase_WriteVFWMulAddF_WorstCase_WriteVFWMulAddV_WorstCase_WriteVFWMulF_WorstCase_WriteVFWMulV_WorstCase_WriteVNClipI_WorstCase_WriteVNClipV_WorstCase_WriteVNClipX_WorstCase_WriteVNShiftI_WorstCase_WriteVNShiftV_WorstCase_WriteVNShiftX_WorstCase_WriteVRGatherVI_WorstCase_WriteVRGatherVX_WorstCase_WriteVSALUI_WorstCase_WriteVSALUV_WorstCase_WriteVSALUX_WorstCase_WriteVSMulV_WorstCase_WriteVSMulX_WorstCase_WriteVSShiftI_WorstCase_WriteVSShiftV_WorstCase_WriteVSShiftX_WorstCase_WriteVIWALUV_WorstCase_WriteVIWALUX_WorstCase_WriteVIWMulAddV_WorstCase_WriteVIWMulAddX_WorstCase_WriteVIWMulV_WorstCase_WriteVIWMulX_WorstCase

  {35,  0}, // #33 WriteVCompressV_M1_E16_WriteVCompressV_M2_E32_WriteVCompressV_M4_E64_WriteVCompressV_MF2_E8_WriteVLDOX16_M1_WriteVLDOX32_M2_WriteVLDOX64_M4_WriteVLDOX8_MF2_WriteVLOXSEG2e16_M1_WriteVLOXSEG2e32_M2_WriteVLOXSEG2e64_M4_WriteVLOXSEG2e8_MF2_WriteVLOXSEG3e16_M1_WriteVLOXSEG3e32_M2_WriteVLOXSEG3e8_MF2_WriteVLOXSEG4e16_M1_WriteVLOXSEG4e32_M2_WriteVLOXSEG4e8_MF2_WriteVLOXSEG5e16_M1_WriteVLOXSEG5e8_MF2_WriteVLOXSEG6e16_M1_WriteVLOXSEG6e8_MF2_WriteVLOXSEG7e16_M1_WriteVLOXSEG7e8_MF2_WriteVLOXSEG8e16_M1_WriteVLOXSEG8e8_MF2_WriteVLSEGFF3e16_M1_WriteVLSEG3e16_M1_WriteVLSEGFF3e32_M2_WriteVLSEG3e32_M2_WriteVLSEGFF3e8_MF2_WriteVLSEG3e8_MF2_WriteVLSEGFF4e16_M1_WriteVLSEG4e16_M1_WriteVLSEGFF4e32_M2_WriteVLSEG4e32_M2_WriteVLSEGFF4e8_MF2_WriteVLSEG4e8_MF2_WriteVLSEGFF5e16_M1_WriteVLSEG5e16_M1_WriteVLSEGFF5e8_MF2_WriteVLSEG5e8_MF2_WriteVLSEGFF6e16_M1_WriteVLSEG6e16_M1_WriteVLSEGFF6e8_MF2_WriteVLSEG6e8_MF2_WriteVLSEGFF7e16_M1_WriteVLSEG7e16_M1_WriteVLSEGFF7e8_MF2_WriteVLSEG7e8_MF2_WriteVLSEGFF8e16_M1_WriteVLSEG8e16_M1_WriteVLSEGFF8e8_MF2_WriteVLSEG8e8_MF2_WriteVLSSEG2e16_M1_WriteVLSSEG2e32_M2_WriteVLSSEG2e64_M4_WriteVLSSEG2e8_MF2_WriteVLSSEG3e16_M1_WriteVLSSEG3e32_M2_WriteVLSSEG3e8_MF2_WriteVLSSEG4e16_M1_WriteVLSSEG4e32_M2_WriteVLSSEG4e8_MF2_WriteVLSSEG5e16_M1_WriteVLSSEG5e8_MF2_WriteVLSSEG6e16_M1_WriteVLSSEG6e8_MF2_WriteVLSSEG7e16_M1_WriteVLSSEG7e8_MF2_WriteVLSSEG8e16_M1_WriteVLSSEG8e8_MF2_WriteVLDUX16_M1_WriteVLDUX32_M2_WriteVLDUX64_M4_WriteVLDUX8_MF2_WriteVLUXSEG2e16_M1_WriteVLUXSEG2e32_M2_WriteVLUXSEG2e64_M4_WriteVLUXSEG2e8_MF2_WriteVLUXSEG3e16_M1_WriteVLUXSEG3e32_M2_WriteVLUXSEG3e8_MF2_WriteVLUXSEG4e16_M1_WriteVLUXSEG4e32_M2_WriteVLUXSEG4e8_MF2_WriteVLUXSEG5e16_M1_WriteVLUXSEG5e8_MF2_WriteVLUXSEG6e16_M1_WriteVLUXSEG6e8_MF2_WriteVLUXSEG7e16_M1_WriteVLUXSEG7e8_MF2_WriteVLUXSEG8e16_M1_WriteVLUXSEG8e8_MF2_WriteVRGatherVV_M1_E16_WriteVRGatherVV_M2_E32_WriteVRGatherVV_M4_E64_WriteVRGatherVV_MF2_E8_WriteVLSEGFF2e16_WorstCase_WriteVLSEG2e16_WorstCase_WriteVLSEGFF2e32_WorstCase_WriteVLSEG2e32_WorstCase_WriteVLSEGFF2e64_WorstCase_WriteVLSEG2e64_WorstCase_WriteVLSEGFF2e8_WorstCase_WriteVLSEG2e8_WorstCase_SiFive7WriteVLDS16_M1_NoPred_SiFive7WriteVLDS32_M2_NoPred_SiFive7WriteVLDS64_M4_NoPred_SiFive7WriteVLDS8_MF2_NoPred

  {19,  0}, // #34 WriteVCompressV_M1_E32_WriteVCompressV_M2_E64_WriteVCompressV_MF2_E16_WriteVCompressV_MF4_E8_WriteVLDOX32_M1_WriteVLDOX64_M2_WriteVLDOX16_MF2_WriteVLDOX8_MF4_WriteVLOXSEG2e32_M1_WriteVLOXSEG2e64_M2_WriteVLOXSEG2e16_MF2_WriteVLOXSEG2e8_MF4_WriteVLOXSEG3e32_M1_WriteVLOXSEG3e64_M2_WriteVLOXSEG3e16_MF2_WriteVLOXSEG3e8_MF4_WriteVLOXSEG4e32_M1_WriteVLOXSEG4e64_M2_WriteVLOXSEG4e16_MF2_WriteVLOXSEG4e8_MF4_WriteVLOXSEG5e32_M1_WriteVLOXSEG5e16_MF2_WriteVLOXSEG5e8_MF4_WriteVLOXSEG5e64_M1_WriteVLOXSEG6e32_M1_WriteVLOXSEG6e16_MF2_WriteVLOXSEG6e8_MF4_WriteVLOXSEG6e64_M1_WriteVLOXSEG7e32_M1_WriteVLOXSEG7e16_MF2_WriteVLOXSEG7e8_MF4_WriteVLOXSEG7e64_M1_WriteVLOXSEG8e32_M1_WriteVLOXSEG8e16_MF2_WriteVLOXSEG8e8_MF4_WriteVLOXSEG8e64_M1_WriteVLSEGFF2e16_M4_WriteVLSEG2e16_M4_WriteVLSEGFF2e32_M4_WriteVLSEG2e32_M4_WriteVLSEGFF2e64_M4_WriteVLSEG2e64_M4_WriteVLSEGFF2e8_M4_WriteVLSEG2e8_M4_WriteVLSEGFF3e16_MF2_WriteVLSEG3e16_MF2_WriteVLSEGFF3e32_M1_WriteVLSEG3e32_M1_WriteVLSEGFF3e64_M2_WriteVLSEG3e64_M2_WriteVLSEGFF3e8_MF4_WriteVLSEG3e8_MF4_WriteVLSEGFF4e16_MF2_WriteVLSEG4e16_MF2_WriteVLSEGFF4e32_M1_WriteVLSEG4e32_M1_WriteVLSEGFF4e64_M2_WriteVLSEG4e64_M2_WriteVLSEGFF4e8_MF4_WriteVLSEG4e8_MF4_WriteVLSEGFF5e16_MF2_WriteVLSEG5e16_MF2_WriteVLSEGFF5e32_M1_WriteVLSEG5e32_M1_WriteVLSEGFF5e64_M1_WriteVLSEG5e64_M1_WriteVLSEGFF5e8_MF4_WriteVLSEG5e8_MF4_WriteVLSEGFF6e16_MF2_WriteVLSEG6e16_MF2_WriteVLSEGFF6e32_M1_WriteVLSEG6e32_M1_WriteVLSEGFF6e64_M1_WriteVLSEG6e64_M1_WriteVLSEGFF6e8_MF4_WriteVLSEG6e8_MF4_WriteVLSEGFF7e16_MF2_WriteVLSEG7e16_MF2_WriteVLSEGFF7e32_M1_WriteVLSEG7e32_M1_WriteVLSEGFF7e64_M1_WriteVLSEG7e64_M1_WriteVLSEGFF7e8_MF4_WriteVLSEG7e8_MF4_WriteVLSEGFF8e16_MF2_WriteVLSEG8e16_MF2_WriteVLSEGFF8e32_M1_WriteVLSEG8e32_M1_WriteVLSEGFF8e64_M1_WriteVLSEG8e64_M1_WriteVLSEGFF8e8_MF4_WriteVLSEG8e8_MF4_WriteVLSSEG2e16_MF2_WriteVLSSEG2e32_M1_WriteVLSSEG2e64_M2_WriteVLSSEG2e8_MF4_WriteVLSSEG3e16_MF2_WriteVLSSEG3e32_M1_WriteVLSSEG3e64_M2_WriteVLSSEG3e8_MF4_WriteVLSSEG4e16_MF2_WriteVLSSEG4e32_M1_WriteVLSSEG4e64_M2_WriteVLSSEG4e8_MF4_WriteVLSSEG5e16_MF2_WriteVLSSEG5e32_M1_WriteVLSSEG5e64_M1_WriteVLSSEG5e8_MF4_WriteVLSSEG6e16_MF2_WriteVLSSEG6e32_M1_WriteVLSSEG6e64_M1_WriteVLSSEG6e8_MF4_WriteVLSSEG7e16_MF2_WriteVLSSEG7e32_M1_WriteVLSSEG7e64_M1_WriteVLSSEG7e8_MF4_WriteVLSSEG8e16_MF2_WriteVLSSEG8e32_M1_WriteVLSSEG8e64_M1_WriteVLSSEG8e8_MF4_WriteVLDUX32_M1_WriteVLDUX64_M2_WriteVLDUX16_MF2_WriteVLDUX8_MF4_WriteVLUXSEG2e32_M1_WriteVLUXSEG2e64_M2_WriteVLUXSEG2e16_MF2_WriteVLUXSEG2e8_MF4_WriteVLUXSEG3e32_M1_WriteVLUXSEG3e64_M2_WriteVLUXSEG3e16_MF2_WriteVLUXSEG3e8_MF4_WriteVLUXSEG4e32_M1_WriteVLUXSEG4e64_M2_WriteVLUXSEG4e16_MF2_WriteVLUXSEG4e8_MF4_WriteVLUXSEG5e32_M1_WriteVLUXSEG5e16_MF2_WriteVLUXSEG5e8_MF4_WriteVLUXSEG5e64_M1_WriteVLUXSEG6e32_M1_WriteVLUXSEG6e16_MF2_WriteVLUXSEG6e8_MF4_WriteVLUXSEG6e64_M1_WriteVLUXSEG7e32_M1_WriteVLUXSEG7e16_MF2_WriteVLUXSEG7e8_MF4_WriteVLUXSEG7e64_M1_WriteVLUXSEG8e32_M1_WriteVLUXSEG8e16_MF2_WriteVLUXSEG8e8_MF4_WriteVLUXSEG8e64_M1_WriteVFCmpF_M8_WriteVFCmpV_M8_WriteVICmpI_M8_WriteVICmpV_M8_WriteVICmpX_M8_WriteVRGatherVV_M1_E32_WriteVRGatherVV_M2_E64_WriteVRGatherVV_MF2_E16_WriteVRGatherVV_MF4_E8_WriteVFCmpF_WorstCase_WriteVFCmpV_WorstCase_WriteVICmpI_WorstCase_WriteVICmpV_WorstCase_WriteVICmpX_WorstCase_SiFive7WriteVLDS16_MF2_NoPred_SiFive7WriteVLDS32_M1_NoPred_SiFive7WriteVLDS64_M2_NoPred_SiFive7WriteVLDS8_MF4_NoPred_WriteFDiv16_WriteFDiv32

  {11,  0}, // #35 WriteVCompressV_M1_E64_WriteVCompressV_MF2_E32_WriteVCompressV_MF4_E16_WriteVCompressV_MF8_E8_WriteVLDOX64_M1_WriteVLDOX32_MF2_WriteVLDOX16_MF4_WriteVLDOX8_MF8_WriteVLOXSEG2e64_M1_WriteVLOXSEG2e32_MF2_WriteVLOXSEG2e16_MF4_WriteVLOXSEG2e8_MF8_WriteVLOXSEG3e64_M1_WriteVLOXSEG3e32_MF2_WriteVLOXSEG3e16_MF4_WriteVLOXSEG3e8_MF8_WriteVLOXSEG4e64_M1_WriteVLOXSEG4e32_MF2_WriteVLOXSEG4e16_MF4_WriteVLOXSEG4e8_MF8_WriteVLOXSEG5e32_MF2_WriteVLOXSEG5e16_MF4_WriteVLOXSEG5e8_MF8_WriteVLOXSEG6e32_MF2_WriteVLOXSEG6e16_MF4_WriteVLOXSEG6e8_MF8_WriteVLOXSEG7e32_MF2_WriteVLOXSEG7e16_MF4_WriteVLOXSEG7e8_MF8_WriteVLOXSEG8e32_MF2_WriteVLOXSEG8e16_MF4_WriteVLOXSEG8e8_MF8_WriteVLSEGFF2e16_M2_WriteVLSEG2e16_M2_WriteVLSEGFF2e32_M2_WriteVLSEG2e32_M2_WriteVLSEGFF2e64_M2_WriteVLSEG2e64_M2_WriteVLSEGFF2e8_M2_WriteVLSEG2e8_M2_WriteVLSEGFF3e16_MF4_WriteVLSEG3e16_MF4_WriteVLSEGFF3e32_MF2_WriteVLSEG3e32_MF2_WriteVLSEGFF3e64_M1_WriteVLSEG3e64_M1_WriteVLSEGFF3e8_MF8_WriteVLSEG3e8_MF8_WriteVLSEGFF4e16_MF4_WriteVLSEG4e16_MF4_WriteVLSEGFF4e32_MF2_WriteVLSEG4e32_MF2_WriteVLSEGFF4e64_M1_WriteVLSEG4e64_M1_WriteVLSEGFF4e8_MF8_WriteVLSEG4e8_MF8_WriteVLSEGFF5e16_MF4_WriteVLSEG5e16_MF4_WriteVLSEGFF5e32_MF2_WriteVLSEG5e32_MF2_WriteVLSEGFF5e8_MF8_WriteVLSEG5e8_MF8_WriteVLSEGFF6e16_MF4_WriteVLSEG6e16_MF4_WriteVLSEGFF6e32_MF2_WriteVLSEG6e32_MF2_WriteVLSEGFF6e8_MF8_WriteVLSEG6e8_MF8_WriteVLSEGFF7e16_MF4_WriteVLSEG7e16_MF4_WriteVLSEGFF7e32_MF2_WriteVLSEG7e32_MF2_WriteVLSEGFF7e8_MF8_WriteVLSEG7e8_MF8_WriteVLSEGFF8e16_MF4_WriteVLSEG8e16_MF4_WriteVLSEGFF8e32_MF2_WriteVLSEG8e32_MF2_WriteVLSEGFF8e8_MF8_WriteVLSEG8e8_MF8_WriteVLSSEG2e16_MF4_WriteVLSSEG2e32_MF2_WriteVLSSEG2e64_M1_WriteVLSSEG2e8_MF8_WriteVLSSEG3e16_MF4_WriteVLSSEG3e32_MF2_WriteVLSSEG3e64_M1_WriteVLSSEG3e8_MF8_WriteVLSSEG4e16_MF4_WriteVLSSEG4e32_MF2_WriteVLSSEG4e64_M1_WriteVLSSEG4e8_MF8_WriteVLSSEG5e16_MF4_WriteVLSSEG5e32_MF2_WriteVLSSEG5e8_MF8_WriteVLSSEG6e16_MF4_WriteVLSSEG6e32_MF2_WriteVLSSEG6e8_MF8_WriteVLSSEG7e16_MF4_WriteVLSSEG7e32_MF2_WriteVLSSEG7e8_MF8_WriteVLSSEG8e16_MF4_WriteVLSSEG8e32_MF2_WriteVLSSEG8e8_MF8_WriteVLDUX64_M1_WriteVLDUX32_MF2_WriteVLDUX16_MF4_WriteVLDUX8_MF8_WriteVLUXSEG2e64_M1_WriteVLUXSEG2e32_MF2_WriteVLUXSEG2e16_MF4_WriteVLUXSEG2e8_MF8_WriteVLUXSEG3e64_M1_WriteVLUXSEG3e32_MF2_WriteVLUXSEG3e16_MF4_WriteVLUXSEG3e8_MF8_WriteVLUXSEG4e64_M1_WriteVLUXSEG4e32_MF2_WriteVLUXSEG4e16_MF4_WriteVLUXSEG4e8_MF8_WriteVLUXSEG5e32_MF2_WriteVLUXSEG5e16_MF4_WriteVLUXSEG5e8_MF8_WriteVLUXSEG6e32_MF2_WriteVLUXSEG6e16_MF4_WriteVLUXSEG6e8_MF8_WriteVLUXSEG7e32_MF2_WriteVLUXSEG7e16_MF4_WriteVLUXSEG7e8_MF8_WriteVLUXSEG8e32_MF2_WriteVLUXSEG8e16_MF4_WriteVLUXSEG8e8_MF8_WriteVFCmpF_M4_WriteVFCmpV_M4_WriteVICmpI_M4_WriteVICmpV_M4_WriteVICmpX_M4_WriteVRGatherVV_M1_E64_WriteVRGatherVV_MF2_E32_WriteVRGatherVV_MF4_E16_WriteVRGatherVV_MF8_E8_SiFive7WriteVLDS16_MF4_NoPred_SiFive7WriteVLDS32_MF2_NoPred_SiFive7WriteVLDS64_M1_NoPred_SiFive7WriteVLDS8_MF8_NoPred

  {67,  0}, // #36 WriteVCompressV_M1_E8_WriteVCompressV_M2_E16_WriteVCompressV_M4_E32_WriteVCompressV_M8_E64_WriteVLDOX8_M1_WriteVLDOX16_M2_WriteVLDOX32_M4_WriteVLDOX64_M8_WriteVLOXSEG2e8_M1_WriteVLOXSEG2e16_M2_WriteVLOXSEG2e32_M4_WriteVLOXSEG3e8_M1_WriteVLOXSEG3e16_M2_WriteVLOXSEG4e8_M1_WriteVLOXSEG4e16_M2_WriteVLOXSEG5e8_M1_WriteVLOXSEG6e8_M1_WriteVLOXSEG7e8_M1_WriteVLOXSEG8e8_M1_WriteVLSEGFF3e16_M2_WriteVLSEG3e16_M2_WriteVLSEGFF3e8_M1_WriteVLSEG3e8_M1_WriteVLSEGFF4e16_M2_WriteVLSEG4e16_M2_WriteVLSEGFF4e8_M1_WriteVLSEG4e8_M1_WriteVLSEGFF5e8_M1_WriteVLSEG5e8_M1_WriteVLSEGFF6e8_M1_WriteVLSEG6e8_M1_WriteVLSEGFF7e8_M1_WriteVLSEG7e8_M1_WriteVLSEGFF8e8_M1_WriteVLSEG8e8_M1_WriteVLSSEG2e16_M2_WriteVLSSEG2e32_M4_WriteVLSSEG2e8_M1_WriteVLSSEG3e16_M2_WriteVLSSEG3e8_M1_WriteVLSSEG4e16_M2_WriteVLSSEG4e8_M1_WriteVLSSEG5e8_M1_WriteVLSSEG6e8_M1_WriteVLSSEG7e8_M1_WriteVLSSEG8e8_M1_WriteVLDUX8_M1_WriteVLDUX16_M2_WriteVLDUX32_M4_WriteVLDUX64_M8_WriteVLUXSEG2e8_M1_WriteVLUXSEG2e16_M2_WriteVLUXSEG2e32_M4_WriteVLUXSEG3e8_M1_WriteVLUXSEG3e16_M2_WriteVLUXSEG4e8_M1_WriteVLUXSEG4e16_M2_WriteVLUXSEG5e8_M1_WriteVLUXSEG6e8_M1_WriteVLUXSEG7e8_M1_WriteVLUXSEG8e8_M1_WriteVRGatherVV_M1_E8_WriteVRGatherVV_M2_E16_WriteVRGatherVV_M4_E32_WriteVRGatherVV_M8_E64_WriteVLDOX64_WorstCase_WriteVLOXSEG2e64_WorstCase_WriteVLOXSEG3e64_WorstCase_WriteVLOXSEG4e64_WorstCase_WriteVLSEGFF3e64_WorstCase_WriteVLSEG3e64_WorstCase_WriteVLSEGFF4e64_WorstCase_WriteVLSEG4e64_WorstCase_WriteVLSSEG2e64_WorstCase_WriteVLSSEG3e64_WorstCase_WriteVLSSEG4e64_WorstCase_WriteVLDUX64_WorstCase_WriteVLUXSEG2e64_WorstCase_WriteVLUXSEG3e64_WorstCase_WriteVLUXSEG4e64_WorstCase_SiFive7WriteVLDS16_M2_NoPred_SiFive7WriteVLDS32_M4_NoPred_SiFive7WriteVLDS64_M8_NoPred_SiFive7WriteVLDS8_M1_NoPred

  {131,  0}, // #37 WriteVCompressV_M2_E8_WriteVCompressV_M4_E16_WriteVCompressV_M8_E32_WriteVLDOX8_M2_WriteVLDOX16_M4_WriteVLDOX32_M8_WriteVLOXSEG2e8_M2_WriteVLOXSEG2e16_M4_WriteVLOXSEG3e8_M2_WriteVLOXSEG4e8_M2_WriteVLSEGFF3e8_M2_WriteVLSEG3e8_M2_WriteVLSEGFF4e8_M2_WriteVLSEG4e8_M2_WriteVLSSEG2e16_M4_WriteVLSSEG2e8_M2_WriteVLSSEG3e8_M2_WriteVLSSEG4e8_M2_WriteVLDUX8_M2_WriteVLDUX16_M4_WriteVLDUX32_M8_WriteVLUXSEG2e8_M2_WriteVLUXSEG2e16_M4_WriteVLUXSEG3e8_M2_WriteVLUXSEG4e8_M2_WriteVRGatherVV_M2_E8_WriteVRGatherVV_M4_E16_WriteVRGatherVV_M8_E32_WriteVLDOX32_WorstCase_WriteVLOXSEG2e32_WorstCase_WriteVLOXSEG3e32_WorstCase_WriteVLOXSEG4e32_WorstCase_WriteVLOXSEG5e32_WorstCase_WriteVLOXSEG5e64_WorstCase_WriteVLOXSEG6e32_WorstCase_WriteVLOXSEG6e64_WorstCase_WriteVLOXSEG7e32_WorstCase_WriteVLOXSEG7e64_WorstCase_WriteVLOXSEG8e32_WorstCase_WriteVLOXSEG8e64_WorstCase_WriteVLSEGFF3e32_WorstCase_WriteVLSEG3e32_WorstCase_WriteVLSEGFF4e32_WorstCase_WriteVLSEG4e32_WorstCase_WriteVLSEGFF5e32_WorstCase_WriteVLSEG5e32_WorstCase_WriteVLSEGFF5e64_WorstCase_WriteVLSEG5e64_WorstCase_WriteVLSEGFF6e32_WorstCase_WriteVLSEG6e32_WorstCase_WriteVLSEGFF6e64_WorstCase_WriteVLSEG6e64_WorstCase_WriteVLSEGFF7e32_WorstCase_WriteVLSEG7e32_WorstCase_WriteVLSEGFF7e64_WorstCase_WriteVLSEG7e64_WorstCase_WriteVLSEGFF8e32_WorstCase_WriteVLSEG8e32_WorstCase_WriteVLSEGFF8e64_WorstCase_WriteVLSEG8e64_WorstCase_WriteVLSSEG2e32_WorstCase_WriteVLSSEG3e32_WorstCase_WriteVLSSEG4e32_WorstCase_WriteVLSSEG5e32_WorstCase_WriteVLSSEG5e64_WorstCase_WriteVLSSEG6e32_WorstCase_WriteVLSSEG6e64_WorstCase_WriteVLSSEG7e32_WorstCase_WriteVLSSEG7e64_WorstCase_WriteVLSSEG8e32_WorstCase_WriteVLSSEG8e64_WorstCase_WriteVLDUX32_WorstCase_WriteVLUXSEG2e32_WorstCase_WriteVLUXSEG3e32_WorstCase_WriteVLUXSEG4e32_WorstCase_WriteVLUXSEG5e32_WorstCase_WriteVLUXSEG5e64_WorstCase_WriteVLUXSEG6e32_WorstCase_WriteVLUXSEG6e64_WorstCase_WriteVLUXSEG7e32_WorstCase_WriteVLUXSEG7e64_WorstCase_WriteVLUXSEG8e32_WorstCase_WriteVLUXSEG8e64_WorstCase_SiFive7WriteVLDS16_M4_NoPred_SiFive7WriteVLDS32_M8_NoPred_SiFive7WriteVLDS8_M2_NoPred

  {259,  0}, // #38 WriteVCompressV_M4_E8_WriteVCompressV_M8_E16_WriteVLDOX8_M4_WriteVLDOX16_M8_WriteVLOXSEG2e8_M4_WriteVLSSEG2e8_M4_WriteVLDUX8_M4_WriteVLDUX16_M8_WriteVLUXSEG2e8_M4_WriteVRGatherVV_M4_E8_WriteVRGatherVV_M8_E16_WriteVLDOX16_WorstCase_WriteVLOXSEG2e16_WorstCase_WriteVLOXSEG3e16_WorstCase_WriteVLOXSEG4e16_WorstCase_WriteVLOXSEG5e16_WorstCase_WriteVLOXSEG6e16_WorstCase_WriteVLOXSEG7e16_WorstCase_WriteVLOXSEG8e16_WorstCase_WriteVLSEGFF3e16_WorstCase_WriteVLSEG3e16_WorstCase_WriteVLSEGFF4e16_WorstCase_WriteVLSEG4e16_WorstCase_WriteVLSEGFF5e16_WorstCase_WriteVLSEG5e16_WorstCase_WriteVLSEGFF6e16_WorstCase_WriteVLSEG6e16_WorstCase_WriteVLSEGFF7e16_WorstCase_WriteVLSEG7e16_WorstCase_WriteVLSEGFF8e16_WorstCase_WriteVLSEG8e16_WorstCase_WriteVLSSEG2e16_WorstCase_WriteVLSSEG3e16_WorstCase_WriteVLSSEG4e16_WorstCase_WriteVLSSEG5e16_WorstCase_WriteVLSSEG6e16_WorstCase_WriteVLSSEG7e16_WorstCase_WriteVLSSEG8e16_WorstCase_WriteVLDUX16_WorstCase_WriteVLUXSEG2e16_WorstCase_WriteVLUXSEG3e16_WorstCase_WriteVLUXSEG4e16_WorstCase_WriteVLUXSEG5e16_WorstCase_WriteVLUXSEG6e16_WorstCase_WriteVLUXSEG7e16_WorstCase_WriteVLUXSEG8e16_WorstCase_SiFive7WriteVLDS16_M8_NoPred_SiFive7WriteVLDS8_M4_NoPred

  {515,  0}, // #39 WriteVCompressV_M8_E8_WriteVLDOX8_M8_WriteVLDUX8_M8_WriteVRGatherVV_M8_E8_WriteVCompressV_WorstCase_WriteVLDOX8_WorstCase_WriteVLOXSEG2e8_WorstCase_WriteVLOXSEG3e8_WorstCase_WriteVLOXSEG4e8_WorstCase_WriteVLOXSEG5e8_WorstCase_WriteVLOXSEG6e8_WorstCase_WriteVLOXSEG7e8_WorstCase_WriteVLOXSEG8e8_WorstCase_WriteVLSEGFF3e8_WorstCase_WriteVLSEG3e8_WorstCase_WriteVLSEGFF4e8_WorstCase_WriteVLSEG4e8_WorstCase_WriteVLSEGFF5e8_WorstCase_WriteVLSEG5e8_WorstCase_WriteVLSEGFF6e8_WorstCase_WriteVLSEG6e8_WorstCase_WriteVLSEGFF7e8_WorstCase_WriteVLSEG7e8_WorstCase_WriteVLSEGFF8e8_WorstCase_WriteVLSEG8e8_WorstCase_WriteVLSSEG2e8_WorstCase_WriteVLSSEG3e8_WorstCase_WriteVLSSEG4e8_WorstCase_WriteVLSSEG5e8_WorstCase_WriteVLSSEG6e8_WorstCase_WriteVLSSEG7e8_WorstCase_WriteVLSSEG8e8_WorstCase_WriteVLDUX8_WorstCase_WriteVLUXSEG2e8_WorstCase_WriteVLUXSEG3e8_WorstCase_WriteVLUXSEG4e8_WorstCase_WriteVLUXSEG5e8_WorstCase_WriteVLUXSEG6e8_WorstCase_WriteVLUXSEG7e8_WorstCase_WriteVLUXSEG8e8_WorstCase_WriteVRGatherVV_WorstCase_SiFive7WriteVLDS8_M8_NoPred

  {120,  0}, // #40 WriteVIDivV_M1_E16_WriteVIDivV_MF2_E8_WriteVIDivX_M1_E16_WriteVIDivX_MF2_E8_WriteVFDivF_M1_E16_WriteVFDivV_M1_E16_WriteVFSqrtV_M1_E16

  {112,  0}, // #41 WriteVIDivV_M1_E32_WriteVIDivX_M1_E32_WriteVFDivF_M1_E32_WriteVFDivV_M1_E32_WriteVFSqrtV_M1_E32

  {114,  0}, // #42 WriteVIDivV_M1_E64_WriteVIDivX_M1_E64_WriteVFDivF_M1_E64_WriteVFDivV_M1_E64_WriteVFSqrtV_M1_E64

  {240,  0}, // #43 WriteVIDivV_M1_E8_WriteVIDivV_M2_E16_WriteVIDivX_M1_E8_WriteVIDivX_M2_E16_WriteVFDivF_M2_E16_WriteVFDivV_M2_E16_WriteVFSqrtV_M2_E16

  {224,  0}, // #44 WriteVIDivV_M2_E32_WriteVIDivX_M2_E32_WriteVFDivF_M2_E32_WriteVFDivV_M2_E32_WriteVFSqrtV_M2_E32

  {228,  0}, // #45 WriteVIDivV_M2_E64_WriteVIDivX_M2_E64_WriteVFDivF_M2_E64_WriteVFDivV_M2_E64_WriteVFSqrtV_M2_E64

  {480,  0}, // #46 WriteVIDivV_M2_E8_WriteVIDivV_M4_E16_WriteVIDivX_M2_E8_WriteVIDivX_M4_E16_WriteVFDivF_M4_E16_WriteVFDivV_M4_E16_WriteVFSqrtV_M4_E16

  {448,  0}, // #47 WriteVIDivV_M4_E32_WriteVIDivX_M4_E32_WriteVFDivF_M4_E32_WriteVFDivV_M4_E32_WriteVFSqrtV_M4_E32

  {456,  0}, // #48 WriteVIDivV_M4_E64_WriteVIDivX_M4_E64_WriteVFDivF_M4_E64_WriteVFDivV_M4_E64_WriteVFSqrtV_M4_E64

  {960,  0}, // #49 WriteVIDivV_M4_E8_WriteVIDivV_M8_E16_WriteVIDivX_M4_E8_WriteVIDivX_M8_E16_WriteVFDivF_M8_E16_WriteVFDivV_M8_E16_WriteVFSqrtV_M8_E16_WriteVFDivF_WorstCase_WriteVFDivV_WorstCase_WriteVFSqrtV_WorstCase

  {896,  0}, // #50 WriteVIDivV_M8_E32_WriteVIDivX_M8_E32_WriteVFDivF_M8_E32_WriteVFDivV_M8_E32_WriteVFSqrtV_M8_E32

  {912,  0}, // #51 WriteVIDivV_M8_E64_WriteVIDivX_M8_E64_WriteVFDivF_M8_E64_WriteVFDivV_M8_E64_WriteVFSqrtV_M8_E64

  {1920,  0}, // #52 WriteVIDivV_M8_E8_WriteVIDivX_M8_E8_WriteVIDivV_WorstCase_WriteVIDivX_WorstCase

  {60,  0}, // #53 WriteVIDivV_MF2_E16_WriteVIDivV_MF4_E8_WriteVIDivX_MF2_E16_WriteVIDivX_MF4_E8_WriteVFDivF_MF2_E16_WriteVFDivV_MF2_E16_WriteVFSqrtV_MF2_E16

  {56,  0}, // #54 WriteVIDivV_MF2_E32_WriteVIDivX_MF2_E32_WriteVFDivF_MF2_E32_WriteVFDivV_MF2_E32_WriteVFRedMinMaxV_From_M8_E16_WriteVFRedV_From_M8_E16_WriteVFSqrtV_MF2_E32_WriteVFWRedV_From_M8_E16_WriteVIRedV_From_M8_E16_WriteVIRedMinMaxV_From_M8_E16_WriteVIWRedV_From_M8_E16_WriteFDiv64_WriteFSqrt64_WriteVFRedMinMaxV_From_WorstCase_WriteVFRedV_From_WorstCase_WriteVFWRedV_From_WorstCase

  {30,  0}, // #55 WriteVIDivV_MF4_E16_WriteVIDivV_MF8_E8_WriteVIDivX_MF4_E16_WriteVIDivX_MF8_E8_WriteVFDivF_MF4_E16_WriteVFDivV_MF4_E16_WriteVFSqrtV_MF4_E16

  {42,  0}, // #56 WriteVFRedMinMaxV_From_M1_E16_WriteVFRedV_From_M1_E16_WriteVFWRedV_From_M1_E16_WriteVIRedV_From_M1_E16_WriteVIRedMinMaxV_From_M1_E16_WriteVIWRedV_From_M1_E16

  {37,  0}, // #57 WriteVFRedMinMaxV_From_M1_E32_WriteVFRedV_From_M1_E32_WriteVFWRedV_From_M1_E32_WriteVIRedV_From_M1_E32_WriteVIRedMinMaxV_From_M1_E32_WriteVIWRedV_From_M1_E32

  {32,  0}, // #58 WriteVFRedMinMaxV_From_M1_E64_WriteVFRedV_From_M1_E64_WriteVIRedV_From_M1_E64_WriteVIRedMinMaxV_From_M1_E64

  {44,  0}, // #59 WriteVFRedMinMaxV_From_M2_E16_WriteVFRedV_From_M2_E16_WriteVFWRedV_From_M2_E16_WriteVIRedV_From_M2_E16_WriteVIRedMinMaxV_From_M2_E16_WriteVIWRedV_From_M2_E16

  {39,  0}, // #60 WriteVFRedMinMaxV_From_M2_E32_WriteVFRedV_From_M2_E32_WriteVFWRedV_From_M2_E32_WriteVIRedV_From_M2_E32_WriteVIRedMinMaxV_From_M2_E32_WriteVIWRedV_From_M2_E32

  {34,  0}, // #61 WriteVFRedMinMaxV_From_M2_E64_WriteVFRedV_From_M2_E64_WriteVIRedV_From_M2_E64_WriteVIRedMinMaxV_From_M2_E64

  {48,  0}, // #62 WriteVFRedMinMaxV_From_M4_E16_WriteVFRedOV_From_M1_E64_WriteVFRedOV_From_MF2_E32_WriteVFRedOV_From_MF4_E16_WriteVFRedV_From_M4_E16_WriteVFWRedOV_From_MF2_E32_WriteVFWRedOV_From_MF4_E16_WriteVFWRedV_From_M4_E16_WriteVIRedV_From_M4_E16_WriteVIRedMinMaxV_From_M4_E16_WriteVIWRedV_From_M4_E16

  {43,  0}, // #63 WriteVFRedMinMaxV_From_M4_E32_WriteVFRedV_From_M4_E32_WriteVFWRedV_From_M4_E32_WriteVIRedV_From_M4_E32_WriteVIRedMinMaxV_From_M4_E32_WriteVIWRedV_From_M4_E32

  {38,  0}, // #64 WriteVFRedMinMaxV_From_M4_E64_WriteVFRedV_From_M4_E64_WriteVIRedV_From_M4_E64_WriteVIRedMinMaxV_From_M4_E64

  {51,  0}, // #65 WriteVFRedMinMaxV_From_M8_E32_WriteVFRedV_From_M8_E32_WriteVFWRedV_From_M8_E32_WriteVIRedV_From_M8_E32_WriteVIRedMinMaxV_From_M8_E32_WriteVIWRedV_From_M8_E32

  {46,  0}, // #66 WriteVFRedMinMaxV_From_M8_E64_WriteVFRedV_From_M8_E64_WriteVIRedV_From_M8_E64_WriteVIRedV_From_MF2_E8_WriteVIRedV_From_MF4_E8_WriteVIRedV_From_MF8_E8_WriteVIRedMinMaxV_From_M8_E64_WriteVIRedMinMaxV_From_MF2_E8_WriteVIRedMinMaxV_From_MF4_E8_WriteVIRedMinMaxV_From_MF8_E8_WriteVIWRedV_From_MF2_E8_WriteVIWRedV_From_MF4_E8_WriteVIWRedV_From_MF8_E8

  {41,  0}, // #67 WriteVFRedMinMaxV_From_MF2_E16_WriteVFRedMinMaxV_From_MF4_E16_WriteVFRedV_From_MF2_E16_WriteVFRedV_From_MF4_E16_WriteVFWRedV_From_MF2_E16_WriteVFWRedV_From_MF4_E16_WriteVIRedV_From_MF2_E16_WriteVIRedV_From_MF4_E16_WriteVIRedMinMaxV_From_MF2_E16_WriteVIRedMinMaxV_From_MF4_E16_WriteVIWRedV_From_MF2_E16_WriteVIWRedV_From_MF4_E16

  {36,  0}, // #68 WriteVFRedMinMaxV_From_MF2_E32_WriteVFRedV_From_MF2_E32_WriteVFWRedV_From_MF2_E32_WriteVIRedV_From_MF2_E32_WriteVIRedMinMaxV_From_MF2_E32_WriteVIWRedV_From_MF2_E32

  {192,  0}, // #69 WriteVFRedOV_From_M1_E16_WriteVFRedOV_From_M2_E32_WriteVFRedOV_From_M4_E64_WriteVFWRedOV_From_M1_E16_WriteVFWRedOV_From_M2_E32

  {96,  0}, // #70 WriteVFRedOV_From_M1_E32_WriteVFRedOV_From_M2_E64_WriteVFRedOV_From_MF2_E16_WriteVFWRedOV_From_M1_E32_WriteVFWRedOV_From_MF2_E16

  {384,  0}, // #71 WriteVFRedOV_From_M2_E16_WriteVFRedOV_From_M4_E32_WriteVFRedOV_From_M8_E64_WriteVFWRedOV_From_M2_E16_WriteVFWRedOV_From_M4_E32

  {768,  0}, // #72 WriteVFRedOV_From_M4_E16_WriteVFRedOV_From_M8_E32_WriteVFWRedOV_From_M4_E16_WriteVFWRedOV_From_M8_E32

  {1536,  0}, // #73 WriteVFRedOV_From_M8_E16_WriteVFWRedOV_From_M8_E16_WriteVFRedOV_From_WorstCase_WriteVFWRedOV_From_WorstCase

  {47,  0}, // #74 WriteVIRedV_From_M1_E8_WriteVIRedMinMaxV_From_M1_E8_WriteVIWRedV_From_M1_E8

  {49,  0}, // #75 WriteVIRedV_From_M2_E8_WriteVIRedMinMaxV_From_M2_E8_WriteVIWRedV_From_M2_E8

  {53,  0}, // #76 WriteVIRedV_From_M4_E8_WriteVIRedMinMaxV_From_M4_E8_WriteVIWRedV_From_M4_E8

  {61,  0}, // #77 WriteVIRedV_From_M8_E8_WriteVIRedMinMaxV_From_M8_E8_WriteVIWRedV_From_M8_E8_WriteVIRedV_From_WorstCase_WriteVIRedMinMaxV_From_WorstCase_WriteVIWRedV_From_WorstCase

  { 3, 153}, // #78 WriteIALU32

  { 3, 186}, // #79 WriteSingleBit

  { 3, 187}, // #80 WriteSingleBitImm

  { 3, 78}, // #81 WriteBEXT

  { 3, 79}, // #82 WriteBEXTI

  { 3, 82}, // #83 WriteCLZ

  { 3, 83}, // #84 WriteCLZ32

  { 3, 84}, // #85 WriteCPOP

  { 3, 85}, // #86 WriteCPOP32

  { 3, 87}, // #87 WriteCTZ

  { 3, 88}, // #88 WriteCTZ32

  { 3, 162}, // #89 WriteLDD

  { 3, 164}, // #90 WriteLDW

  { 3, 156}, // #91 WriteIMul

  { 3, 182}, // #92 WriteShiftImm

  {66, 154}, // #93 WriteIDiv

  {14,  0}, // #94 WriteFDiv16_WriteFSqrt16

  {27,  0}, // #95 WriteFDiv32_WriteFSqrt32

  { 3, 157}, // #96 WriteIMul32

  { 3, 166}, // #97 WriteORCB

  { 3, 169}, // #98 WriteREV8

  { 3, 173}, // #99 WriteRotateReg

  { 3, 174}, // #100 WriteRotateReg32

  { 3, 171}, // #101 WriteRotateImm

  { 3, 172}, // #102 WriteRotateImm32

  { 3, 176}, // #103 WriteSHXADD

  { 3, 177}, // #104 WriteSHXADD32

  { 3, 184}, // #105 WriteShiftReg

  { 3, 183}, // #106 WriteShiftImm32

  { 3, 185}, // #107 WriteShiftReg32

  { 3, 162}, // #108 WriteLDD

  { 3, 162}, // #109 WriteLDD

  { 3, 164}, // #110 WriteLDW

  { 3, 164}, // #111 WriteLDW

  { 1, 186}, // #112 WriteSingleBit

  { 1, 187}, // #113 WriteSingleBitImm

  { 1, 78}, // #114 WriteBEXT

  { 1, 79}, // #115 WriteBEXTI

  { 1, 82}, // #116 WriteCLZ

  { 1, 83}, // #117 WriteCLZ32

  { 1, 87}, // #118 WriteCTZ

  { 1, 88}, // #119 WriteCTZ32

  { 4, 161}, // #120 WriteLDB

  { 4, 162}, // #121 WriteLDD

  { 4, 163}, // #122 WriteLDH

  { 4, 164}, // #123 WriteLDW

  {35, 154}, // #124 WriteIDiv

  {20, 155}, // #125 WriteIDiv32

  {33,  0}, // #126 WriteFDiv64_WriteFSqrt64

  {18,  0}, // #127 WriteFSqrt16_WriteFSqrt32

  { 1, 166}, // #128 WriteORCB

  { 1, 169}, // #129 WriteREV8

  { 1, 173}, // #130 WriteRotateReg

  { 1, 174}, // #131 WriteRotateReg32

  { 1, 171}, // #132 WriteRotateImm

  { 1, 172}, // #133 WriteRotateImm32

  { 1, 176}, // #134 WriteSHXADD

  { 1, 177}, // #135 WriteSHXADD32

  { 4, 162}, // #136 WriteLDD

  { 4, 162}, // #137 WriteLDD

  { 4, 164}, // #138 WriteLDW

  { 4, 164}, // #139 WriteLDW

  { 2, 161}, // #140 WriteLDB

  { 2, 163}, // #141 WriteLDH

  { 1, 156}, // #142 WriteIMul

  {33, 155}, // #143 WriteIDiv32

  { 1, 157}, // #144 WriteIMul32

  { 2,  0}, // #145 WriteSTD_WriteSTW

  { 2,  0} // #146 WriteSTD_WriteSTW

}; // RISCVWriteLatencyTable

// {UseIdx, WriteResourceID, Cycles}

extern const llvm::MCReadAdvanceEntry RISCVReadAdvanceTable[] = {

  {0,  0,  0}, // Invalid

  {0,  0,  0}, // #1

  {1,  0,  0}, // #2

  {0,  0,  0}, // #3

  {1,  0,  0}, // #4

  {2,  0,  0}, // #5

  {0, 78,  2}, // #6

  {0, 79,  2}, // #7

  {0, 82,  2}, // #8

  {0, 83,  2}, // #9

  {0, 84,  2}, // #10

  {0, 85,  2}, // #11

  {0, 87,  2}, // #12

  {0, 88,  2}, // #13

  {0, 152,  2}, // #14

  {0, 153,  2}, // #15

  {0, 154,  2}, // #16

  {0, 155,  2}, // #17

  {0, 156,  2}, // #18

  {0, 157,  2}, // #19

  {0, 161,  2}, // #20

  {0, 162,  2}, // #21

  {0, 163,  2}, // #22

  {0, 164,  2}, // #23

  {0, 166,  2}, // #24

  {0, 169,  2}, // #25

  {0, 171,  2}, // #26

  {0, 172,  2}, // #27

  {0, 173,  2}, // #28

  {0, 174,  2}, // #29

  {0, 175,  2}, // #30

  {0, 176,  2}, // #31

  {0, 177,  2}, // #32

  {0, 182,  2}, // #33

  {0, 183,  2}, // #34

  {0, 184,  2}, // #35

  {0, 185,  2}, // #36

  {0, 186,  2}, // #37

  {0, 187,  2}, // #38

  {0, 78,  0}, // #39

  {0, 79,  0}, // #40

  {0, 82,  0}, // #41

  {0, 83,  0}, // #42

  {0, 84,  0}, // #43

  {0, 85,  0}, // #44

  {0, 87,  0}, // #45

  {0, 88,  0}, // #46

  {0, 152,  0}, // #47

  {0, 153,  0}, // #48

  {0, 154,  0}, // #49

  {0, 155,  0}, // #50

  {0, 156,  0}, // #51

  {0, 157,  0}, // #52

  {0, 161,  0}, // #53

  {0, 162,  0}, // #54

  {0, 163,  0}, // #55

  {0, 164,  0}, // #56

  {0, 166,  0}, // #57

  {0, 169,  0}, // #58

  {0, 171,  0}, // #59

  {0, 172,  0}, // #60

  {0, 173,  0}, // #61

  {0, 174,  0}, // #62

  {0, 175,  0}, // #63

  {0, 176,  0}, // #64

  {0, 177,  0}, // #65

  {0, 182,  0}, // #66

  {0, 183,  0}, // #67

  {0, 184,  0}, // #68

  {0, 185,  0}, // #69

  {0, 186,  0}, // #70

  {0, 187,  0}, // #71

  {1, 78,  0}, // #72

  {1, 79,  0}, // #73

  {1, 82,  0}, // #74

  {1, 83,  0}, // #75

  {1, 84,  0}, // #76

  {1, 85,  0}, // #77

  {1, 87,  0}, // #78

  {1, 88,  0}, // #79

  {1, 152,  0}, // #80

  {1, 153,  0}, // #81

  {1, 154,  0}, // #82

  {1, 155,  0}, // #83

  {1, 156,  0}, // #84

  {1, 157,  0}, // #85

  {1, 161,  0}, // #86

  {1, 162,  0}, // #87

  {1, 163,  0}, // #88

  {1, 164,  0}, // #89

  {1, 166,  0}, // #90

  {1, 169,  0}, // #91

  {1, 171,  0}, // #92

  {1, 172,  0}, // #93

  {1, 173,  0}, // #94

  {1, 174,  0}, // #95

  {1, 175,  0}, // #96

  {1, 176,  0}, // #97

  {1, 177,  0}, // #98

  {1, 182,  0}, // #99

  {1, 183,  0}, // #100

  {1, 184,  0}, // #101

  {1, 185,  0}, // #102

  {1, 186,  0}, // #103

  {1, 187,  0}, // #104

  {2, 78,  0}, // #105

  {2, 79,  0}, // #106

  {2, 82,  0}, // #107

  {2, 83,  0}, // #108

  {2, 84,  0}, // #109

  {2, 85,  0}, // #110

  {2, 87,  0}, // #111

  {2, 88,  0}, // #112

  {2, 152,  0}, // #113

  {2, 153,  0}, // #114

  {2, 154,  0}, // #115

  {2, 155,  0}, // #116

  {2, 156,  0}, // #117

  {2, 157,  0}, // #118

  {2, 161,  0}, // #119

  {2, 162,  0}, // #120

  {2, 163,  0}, // #121

  {2, 164,  0}, // #122

  {2, 166,  0}, // #123

  {2, 169,  0}, // #124

  {2, 171,  0}, // #125

  {2, 172,  0}, // #126

  {2, 173,  0}, // #127

  {2, 174,  0}, // #128

  {2, 175,  0}, // #129

  {2, 176,  0}, // #130

  {2, 177,  0}, // #131

  {2, 182,  0}, // #132

  {2, 183,  0}, // #133

  {2, 184,  0}, // #134

  {2, 185,  0}, // #135

  {2, 186,  0}, // #136

  {2, 187,  0}, // #137

  {3, 78,  0}, // #138

  {3, 79,  0}, // #139

  {3, 82,  0}, // #140

  {3, 83,  0}, // #141

  {3, 84,  0}, // #142

  {3, 85,  0}, // #143

  {3, 87,  0}, // #144

  {3, 88,  0}, // #145

  {3, 152,  0}, // #146

  {3, 153,  0}, // #147

  {3, 154,  0}, // #148

  {3, 155,  0}, // #149

  {3, 156,  0}, // #150

  {3, 157,  0}, // #151

  {3, 161,  0}, // #152

  {3, 162,  0}, // #153

  {3, 163,  0}, // #154

  {3, 164,  0}, // #155

  {3, 166,  0}, // #156

  {3, 169,  0}, // #157

  {3, 171,  0}, // #158

  {3, 172,  0}, // #159

  {3, 173,  0}, // #160

  {3, 174,  0}, // #161

  {3, 175,  0}, // #162

  {3, 176,  0}, // #163

  {3, 177,  0}, // #164

  {3, 182,  0}, // #165

  {3, 183,  0}, // #166

  {3, 184,  0}, // #167

  {3, 185,  0}, // #168

  {3, 186,  0}, // #169

  {3, 187,  0}, // #170

  {4, 78,  0}, // #171

  {4, 79,  0}, // #172

  {4, 82,  0}, // #173

  {4, 83,  0}, // #174

  {4, 84,  0}, // #175

  {4, 85,  0}, // #176

  {4, 87,  0}, // #177

  {4, 88,  0}, // #178

  {4, 152,  0}, // #179

  {4, 153,  0}, // #180

  {4, 154,  0}, // #181

  {4, 155,  0}, // #182

  {4, 156,  0}, // #183

  {4, 157,  0}, // #184

  {4, 161,  0}, // #185

  {4, 162,  0}, // #186

  {4, 163,  0}, // #187

  {4, 164,  0}, // #188

  {4, 166,  0}, // #189

  {4, 169,  0}, // #190

  {4, 171,  0}, // #191

  {4, 172,  0}, // #192

  {4, 173,  0}, // #193

  {4, 174,  0}, // #194

  {4, 175,  0}, // #195

  {4, 176,  0}, // #196

  {4, 177,  0}, // #197

  {4, 182,  0}, // #198

  {4, 183,  0}, // #199

  {4, 184,  0}, // #200

  {4, 185,  0}, // #201

  {4, 186,  0}, // #202

  {4, 187,  0}, // #203

  {0,  0,  0}, // #204

  {1,  0,  0}, // #205

  {2,  0,  0}, // #206

  {3,  0,  0}, // #207

  {0,  0,  0}, // #208

  {1,  0,  0}, // #209

  {2,  0,  0}, // #210

  {3,  0,  0}, // #211

  {4,  0,  0}, // #212

  {0,  0,  2}, // #213

  {0, 78,  2}, // #214

  {0, 79,  2}, // #215

  {0, 82,  2}, // #216

  {0, 83,  2}, // #217

  {0, 84,  2}, // #218

  {0, 85,  2}, // #219

  {0, 87,  2}, // #220

  {0, 88,  2}, // #221

  {0, 152,  2}, // #222

  {0, 153,  2}, // #223

  {0, 154,  2}, // #224

  {0, 155,  2}, // #225

  {0, 156,  2}, // #226

  {0, 157,  2}, // #227

  {0, 161,  2}, // #228

  {0, 162,  2}, // #229

  {0, 163,  2}, // #230

  {0, 164,  2}, // #231

  {0, 166,  2}, // #232

  {0, 169,  2}, // #233

  {0, 171,  2}, // #234

  {0, 172,  2}, // #235

  {0, 173,  2}, // #236

  {0, 174,  2}, // #237

  {0, 175,  2}, // #238

  {0, 176,  2}, // #239

  {0, 177,  2}, // #240