/src/build/lib/Target/Sparc/SparcGenAsmWriter.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Assembly Writer Source Fragment                                            *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|* From: Sparc.td                                                             *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

/// getMnemonic - This method is automatically generated by tablegen
/// from the instruction set description.
std::pair<const char *, uint64_t> SparcInstPrinter::getMnemonic(const MCInst *MI) {

#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
  static const char AsmStrs[] = {
  /* 0 */ "fcmpd %fcc0, \0"
  /* 14 */ "fcmpq %fcc0, \0"
  /* 28 */ "fcmps %fcc0, \0"
  /* 42 */ "rd %wim, \0"
  /* 52 */ "rdpr %fq, \0"
  /* 63 */ "rd %tbr, \0"
  /* 73 */ "rd %psr, \0"
  /* 83 */ "fsrc1 \0"
  /* 90 */ "fandnot1 \0"
  /* 100 */ "fnot1 \0"
  /* 107 */ "fornot1 \0"
  /* 116 */ "fsra32 \0"
  /* 124 */ "fpsub32 \0"
  /* 133 */ "fpadd32 \0"
  /* 142 */ "edge32 \0"
  /* 150 */ "fcmple32 \0"
  /* 160 */ "fcmpne32 \0"
  /* 170 */ "fpack32 \0"
  /* 179 */ "cmask32 \0"
  /* 188 */ "fsll32 \0"
  /* 196 */ "fsrl32 \0"
  /* 204 */ "fcmpeq32 \0"
  /* 214 */ "fslas32 \0"
  /* 223 */ "fcmpgt32 \0"
  /* 233 */ "array32 \0"
  /* 242 */ "fsrc2 \0"
  /* 249 */ "fandnot2 \0"
  /* 259 */ "fnot2 \0"
  /* 266 */ "fornot2 \0"
  /* 275 */ "fpadd64 \0"
  /* 284 */ "fsra16 \0"
  /* 292 */ "fpsub16 \0"
  /* 301 */ "fpadd16 \0"
  /* 310 */ "edge16 \0"
  /* 318 */ "fcmple16 \0"
  /* 328 */ "fcmpne16 \0"
  /* 338 */ "fpack16 \0"
  /* 347 */ "cmask16 \0"
  /* 356 */ "fsll16 \0"
  /* 364 */ "fsrl16 \0"
  /* 372 */ "fchksm16 \0"
  /* 382 */ "fmean16 \0"
  /* 391 */ "fcmpeq16 \0"
  /* 401 */ "fslas16 \0"
  /* 410 */ "fcmpgt16 \0"
  /* 420 */ "fmul8x16 \0"
  /* 430 */ "fmuld8ulx16 \0"
  /* 443 */ "fmul8ulx16 \0"
  /* 455 */ "fmuld8sux16 \0"
  /* 468 */ "fmul8sux16 \0"
  /* 480 */ "array16 \0"
  /* 489 */ "edge8 \0"
  /* 496 */ "cmask8 \0"
  /* 504 */ "array8 \0"
  /* 512 */ "!ADJCALLSTACKDOWN \0"
  /* 531 */ "!ADJCALLSTACKUP \0"
  /* 548 */ "fpsub32S \0"
  /* 558 */ "fpsub16S \0"
  /* 568 */ "stba \0"
  /* 574 */ "stda \0"
  /* 580 */ "stha \0"
  /* 586 */ "stqa \0"
  /* 592 */ "sra \0"
  /* 597 */ "faligndata \0"
  /* 609 */ "sta \0"
  /* 614 */ "stxa \0"
  /* 620 */ "stb \0"
  /* 625 */ "sub \0"
  /* 630 */ "smac \0"
  /* 636 */ "umac \0"
  /* 642 */ "tsubcc \0"
  /* 650 */ "addxccc \0"
  /* 659 */ "taddcc \0"
  /* 667 */ "andcc \0"
  /* 674 */ "smulcc \0"
  /* 682 */ "umulcc \0"
  /* 690 */ "andncc \0"
  /* 698 */ "orncc \0"
  /* 705 */ "xnorcc \0"
  /* 713 */ "xorcc \0"
  /* 720 */ "mulscc \0"
  /* 728 */ "sdivcc \0"
  /* 736 */ "udivcc \0"
  /* 744 */ "subxcc \0"
  /* 752 */ "addxcc \0"
  /* 760 */ "popc \0"
  /* 766 */ "addxc \0"
  /* 773 */ "fsubd \0"
  /* 780 */ "fhsubd \0"
  /* 788 */ "add \0"
  /* 793 */ "faddd \0"
  /* 800 */ "fhaddd \0"
  /* 808 */ "fnhaddd \0"
  /* 817 */ "fnaddd \0"
  /* 825 */ "fcmped \0"
  /* 833 */ "fnegd \0"
  /* 840 */ "fmuld \0"
  /* 847 */ "fsmuld \0"
  /* 855 */ "fand \0"
  /* 861 */ "fnand \0"
  /* 868 */ "fexpand \0"
  /* 877 */ "fitod \0"
  /* 884 */ "fqtod \0"
  /* 891 */ "fstod \0"
  /* 898 */ "fxtod \0"
  /* 905 */ "fcmpd \0"
  /* 912 */ "flcmpd \0"
  /* 920 */ "rd \0"
  /* 924 */ "fabsd \0"
  /* 931 */ "fsqrtd \0"
  /* 939 */ "std \0"
  /* 944 */ "fdivd \0"
  /* 951 */ "fmovd \0"
  /* 958 */ "fpmerge \0"
  /* 967 */ "bshuffle \0"
  /* 977 */ "fone \0"
  /* 983 */ "restore \0"
  /* 992 */ "save \0"
  /* 998 */ "flush \0"
  /* 1005 */ "sth \0"
  /* 1010 */ "sethi \0"
  /* 1017 */ "umulxhi \0"
  /* 1026 */ "xmulxhi \0"
  /* 1035 */ "fdtoi \0"
  /* 1042 */ "fqtoi \0"
  /* 1049 */ "fstoi \0"
  /* 1056 */ "bmask \0"
  /* 1063 */ "edge32l \0"
  /* 1072 */ "edge16l \0"
  /* 1081 */ "edge8l \0"
  /* 1089 */ "fmul8x16al \0"
  /* 1101 */ "call \0"
  /* 1107 */ "sll \0"
  /* 1112 */ "jmpl \0"
  /* 1118 */ "alignaddrl \0"
  /* 1130 */ "srl \0"
  /* 1135 */ "smul \0"
  /* 1141 */ "umul \0"
  /* 1147 */ "edge32n \0"
  /* 1156 */ "edge16n \0"
  /* 1165 */ "edge8n \0"
  /* 1173 */ "andn \0"
  /* 1179 */ "edge32ln \0"
  /* 1189 */ "edge16ln \0"
  /* 1199 */ "edge8ln \0"
  /* 1208 */ "orn \0"
  /* 1213 */ "pdistn \0"
  /* 1221 */ "fzero \0"
  /* 1228 */ "unimp \0"
  /* 1235 */ "jmp \0"
  /* 1240 */ "fsubq \0"
  /* 1247 */ "faddq \0"
  /* 1254 */ "fcmpeq \0"
  /* 1262 */ "fnegq \0"
  /* 1269 */ "fdmulq \0"
  /* 1277 */ "fmulq \0"
  /* 1284 */ "fdtoq \0"
  /* 1291 */ "fitoq \0"
  /* 1298 */ "fstoq \0"
  /* 1305 */ "fxtoq \0"
  /* 1312 */ "fcmpq \0"
  /* 1319 */ "fabsq \0"
  /* 1326 */ "fsqrtq \0"
  /* 1334 */ "stq \0"
  /* 1339 */ "fdivq \0"
  /* 1346 */ "fmovq \0"
  /* 1353 */ "membar \0"
  /* 1361 */ "alignaddr \0"
  /* 1372 */ "sir \0"
  /* 1377 */ "for \0"
  /* 1382 */ "fnor \0"
  /* 1388 */ "fxnor \0"
  /* 1395 */ "fxor \0"
  /* 1401 */ "rdpr \0"
  /* 1407 */ "wrpr \0"
  /* 1413 */ "pwr \0"
  /* 1418 */ "fsrc1s \0"
  /* 1426 */ "fandnot1s \0"
  /* 1437 */ "fnot1s \0"
  /* 1445 */ "fornot1s \0"
  /* 1455 */ "fpadd32s \0"
  /* 1465 */ "fsrc2s \0"
  /* 1473 */ "fandnot2s \0"
  /* 1484 */ "fnot2s \0"
  /* 1492 */ "fornot2s \0"
  /* 1502 */ "fpadd16s \0"
  /* 1512 */ "fsubs \0"
  /* 1519 */ "fhsubs \0"
  /* 1527 */ "fadds \0"
  /* 1534 */ "fhadds \0"
  /* 1542 */ "fnhadds \0"
  /* 1551 */ "fnadds \0"
  /* 1559 */ "fands \0"
  /* 1566 */ "fnands \0"
  /* 1574 */ "fones \0"
  /* 1581 */ "fcmpes \0"
  /* 1589 */ "fnegs \0"
  /* 1596 */ "fmuls \0"
  /* 1603 */ "fzeros \0"
  /* 1611 */ "fdtos \0"
  /* 1618 */ "fitos \0"
  /* 1625 */ "fqtos \0"
  /* 1632 */ "fxtos \0"
  /* 1639 */ "fcmps \0"
  /* 1646 */ "flcmps \0"
  /* 1654 */ "fors \0"
  /* 1660 */ "fnors \0"
  /* 1667 */ "fxnors \0"
  /* 1675 */ "fxors \0"
  /* 1682 */ "fabss \0"
  /* 1689 */ "fsqrts \0"
  /* 1697 */ "fdivs \0"
  /* 1704 */ "fmovs \0"
  /* 1711 */ "set \0"
  /* 1716 */ "lzcnt \0"
  /* 1723 */ "pdist \0"
  /* 1730 */ "rett \0"
  /* 1736 */ "fmul8x16au \0"
  /* 1748 */ "sdiv \0"
  /* 1754 */ "udiv \0"
  /* 1760 */ "tsubcctv \0"
  /* 1770 */ "taddcctv \0"
  /* 1780 */ "movstosw \0"
  /* 1790 */ "movstouw \0"
  /* 1800 */ "srax \0"
  /* 1806 */ "subx \0"
  /* 1812 */ "addx \0"
  /* 1818 */ "fpackfix \0"
  /* 1828 */ "sllx \0"
  /* 1834 */ "srlx \0"
  /* 1840 */ "xmulx \0"
  /* 1847 */ "fdtox \0"
  /* 1854 */ "movdtox \0"
  /* 1863 */ "fqtox \0"
  /* 1870 */ "fstox \0"
  /* 1877 */ "setx \0"
  /* 1883 */ "stx \0"
  /* 1888 */ "sdivx \0"
  /* 1895 */ "udivx \0"
  /* 1902 */ "; SELECT_CC_DFP_FCC PSEUDO!\0"
  /* 1930 */ "; SELECT_CC_QFP_FCC PSEUDO!\0"
  /* 1958 */ "; SELECT_CC_FP_FCC PSEUDO!\0"
  /* 1985 */ "; SELECT_CC_Int_FCC PSEUDO!\0"
  /* 2013 */ "; SELECT_CC_DFP_ICC PSEUDO!\0"
  /* 2041 */ "; SELECT_CC_QFP_ICC PSEUDO!\0"
  /* 2069 */ "; SELECT_CC_FP_ICC PSEUDO!\0"
  /* 2096 */ "; SELECT_CC_Int_ICC PSEUDO!\0"
  /* 2124 */ "; SELECT_CC_DFP_XCC PSEUDO!\0"
  /* 2152 */ "; SELECT_CC_QFP_XCC PSEUDO!\0"
  /* 2180 */ "; SELECT_CC_FP_XCC PSEUDO!\0"
  /* 2207 */ "; SELECT_CC_Int_XCC PSEUDO!\0"
  /* 2235 */ "jmp %i7+\0"
  /* 2244 */ "jmp %o7+\0"
  /* 2253 */ "# XRay Function Patchable RET.\0"
  /* 2284 */ "# XRay Typed Event Log.\0"
  /* 2308 */ "# XRay Custom Event Log.\0"
  /* 2333 */ "# XRay Function Enter.\0"
  /* 2356 */ "# XRay Tail Call Exit.\0"
  /* 2379 */ "# XRay Function Exit.\0"
  /* 2401 */ "flush %g0\0"
  /* 2411 */ "ta 1\0"
  /* 2416 */ "ta 3\0"
  /* 2421 */ "ta 5\0"
  /* 2426 */ "LIFETIME_END\0"
  /* 2439 */ "PSEUDO_PROBE\0"
  /* 2452 */ "BUNDLE\0"
  /* 2459 */ "DBG_VALUE\0"
  /* 2469 */ "DBG_INSTR_REF\0"
  /* 2483 */ "DBG_PHI\0"
  /* 2491 */ "DBG_LABEL\0"
  /* 2501 */ "LIFETIME_START\0"
  /* 2516 */ "DBG_VALUE_LIST\0"
  /* 2531 */ "std %cq, [\0"
  /* 2542 */ "std %fq, [\0"
  /* 2553 */ "st %csr, [\0"
  /* 2564 */ "st %fsr, [\0"
  /* 2575 */ "stx %fsr, [\0"
  /* 2587 */ "ldsba [\0"
  /* 2595 */ "lduba [\0"
  /* 2603 */ "ldstuba [\0"
  /* 2613 */ "ldda [\0"
  /* 2620 */ "lda [\0"
  /* 2626 */ "ldsha [\0"
  /* 2634 */ "lduha [\0"
  /* 2642 */ "swapa [\0"
  /* 2650 */ "ldqa [\0"
  /* 2657 */ "casa [\0"
  /* 2664 */ "ldswa [\0"
  /* 2672 */ "ldxa [\0"
  /* 2679 */ "casxa [\0"
  /* 2687 */ "ldsb [\0"
  /* 2694 */ "ldub [\0"
  /* 2701 */ "ldstub [\0"
  /* 2710 */ "ldd [\0"
  /* 2716 */ "ld [\0"
  /* 2721 */ "prefetch [\0"
  /* 2732 */ "ldsh [\0"
  /* 2739 */ "lduh [\0"
  /* 2746 */ "swap [\0"
  /* 2753 */ "ldq [\0"
  /* 2759 */ "ldsw [\0"
  /* 2766 */ "ldx [\0"
  /* 2772 */ "cb\0"
  /* 2775 */ "fb\0"
  /* 2778 */ "restored\0"
  /* 2787 */ "saved\0"
  /* 2793 */ "fmovrd\0"
  /* 2800 */ "fmovd\0"
  /* 2806 */ "done\0"
  /* 2811 */ "# FEntry call\0"
  /* 2825 */ "siam\0"
  /* 2830 */ "shutdown\0"
  /* 2839 */ "nop\0"
  /* 2843 */ "fmovrq\0"
  /* 2850 */ "fmovq\0"
  /* 2856 */ "stbar\0"
  /* 2862 */ "br\0"
  /* 2865 */ "movr\0"
  /* 2870 */ "fmovrs\0"
  /* 2877 */ "fmovs\0"
  /* 2883 */ "t\0"
  /* 2885 */ "mov\0"
  /* 2889 */ "flushw\0"
  /* 2896 */ "retry\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

  static const uint32_t OpInfo0[] = {
    0U, // PHI
    0U, // INLINEASM
    0U, // INLINEASM_BR
    0U, // CFI_INSTRUCTION
    0U, // EH_LABEL
    0U, // GC_LABEL
    0U, // ANNOTATION_LABEL
    0U, // KILL
    0U, // EXTRACT_SUBREG
    0U, // INSERT_SUBREG
    0U, // IMPLICIT_DEF
    0U, // SUBREG_TO_REG
    0U, // COPY_TO_REGCLASS
    2460U,  // DBG_VALUE
    2517U,  // DBG_VALUE_LIST
    2470U,  // DBG_INSTR_REF
    2484U,  // DBG_PHI
    2492U,  // DBG_LABEL
    0U, // REG_SEQUENCE
    0U, // COPY
    2453U,  // BUNDLE
    2502U,  // LIFETIME_START
    2427U,  // LIFETIME_END
    2440U,  // PSEUDO_PROBE
    0U, // ARITH_FENCE
    0U, // STACKMAP
    2812U,  // FENTRY_CALL
    0U, // PATCHPOINT
    0U, // LOAD_STACK_GUARD
    0U, // PREALLOCATED_SETUP
    0U, // PREALLOCATED_ARG
    0U, // STATEPOINT
    0U, // LOCAL_ESCAPE
    0U, // FAULTING_OP
    0U, // PATCHABLE_OP
    2334U,  // PATCHABLE_FUNCTION_ENTER
    2254U,  // PATCHABLE_RET
    2380U,  // PATCHABLE_FUNCTION_EXIT
    2357U,  // PATCHABLE_TAIL_CALL
    2309U,  // PATCHABLE_EVENT_CALL
    2285U,  // PATCHABLE_TYPED_EVENT_CALL
    0U, // ICALL_BRANCH_FUNNEL
    0U, // MEMBARRIER
    0U, // JUMP_TABLE_DEBUG_INFO
    0U, // G_ASSERT_SEXT
    0U, // G_ASSERT_ZEXT
    0U, // G_ASSERT_ALIGN
    0U, // G_ADD
    0U, // G_SUB
    0U, // G_MUL
    0U, // G_SDIV
    0U, // G_UDIV
    0U, // G_SREM
    0U, // G_UREM
    0U, // G_SDIVREM
    0U, // G_UDIVREM
    0U, // G_AND
    0U, // G_OR
    0U, // G_XOR
    0U, // G_IMPLICIT_DEF
    0U, // G_PHI
    0U, // G_FRAME_INDEX
    0U, // G_GLOBAL_VALUE
    0U, // G_CONSTANT_POOL
    0U, // G_EXTRACT
    0U, // G_UNMERGE_VALUES
    0U, // G_INSERT
    0U, // G_MERGE_VALUES
    0U, // G_BUILD_VECTOR
    0U, // G_BUILD_VECTOR_TRUNC
    0U, // G_CONCAT_VECTORS
    0U, // G_PTRTOINT
    0U, // G_INTTOPTR
    0U, // G_BITCAST
    0U, // G_FREEZE
    0U, // G_CONSTANT_FOLD_BARRIER
    0U, // G_INTRINSIC_FPTRUNC_ROUND
    0U, // G_INTRINSIC_TRUNC
    0U, // G_INTRINSIC_ROUND
    0U, // G_INTRINSIC_LRINT
    0U, // G_INTRINSIC_ROUNDEVEN
    0U, // G_READCYCLECOUNTER
    0U, // G_LOAD
    0U, // G_SEXTLOAD
    0U, // G_ZEXTLOAD
    0U, // G_INDEXED_LOAD
    0U, // G_INDEXED_SEXTLOAD
    0U, // G_INDEXED_ZEXTLOAD
    0U, // G_STORE
    0U, // G_INDEXED_STORE
    0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
    0U, // G_ATOMIC_CMPXCHG
    0U, // G_ATOMICRMW_XCHG
    0U, // G_ATOMICRMW_ADD
    0U, // G_ATOMICRMW_SUB
    0U, // G_ATOMICRMW_AND
    0U, // G_ATOMICRMW_NAND
    0U, // G_ATOMICRMW_OR
    0U, // G_ATOMICRMW_XOR
    0U, // G_ATOMICRMW_MAX
    0U, // G_ATOMICRMW_MIN
    0U, // G_ATOMICRMW_UMAX
    0U, // G_ATOMICRMW_UMIN
    0U, // G_ATOMICRMW_FADD
    0U, // G_ATOMICRMW_FSUB
    0U, // G_ATOMICRMW_FMAX
    0U, // G_ATOMICRMW_FMIN
    0U, // G_ATOMICRMW_UINC_WRAP
    0U, // G_ATOMICRMW_UDEC_WRAP
    0U, // G_FENCE
    0U, // G_PREFETCH
    0U, // G_BRCOND
    0U, // G_BRINDIRECT
    0U, // G_INVOKE_REGION_START
    0U, // G_INTRINSIC
    0U, // G_INTRINSIC_W_SIDE_EFFECTS
    0U, // G_INTRINSIC_CONVERGENT
    0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
    0U, // G_ANYEXT
    0U, // G_TRUNC
    0U, // G_CONSTANT
    0U, // G_FCONSTANT
    0U, // G_VASTART
    0U, // G_VAARG
    0U, // G_SEXT
    0U, // G_SEXT_INREG
    0U, // G_ZEXT
    0U, // G_SHL
    0U, // G_LSHR
    0U, // G_ASHR
    0U, // G_FSHL
    0U, // G_FSHR
    0U, // G_ROTR
    0U, // G_ROTL
    0U, // G_ICMP
    0U, // G_FCMP
    0U, // G_SELECT
    0U, // G_UADDO
    0U, // G_UADDE
    0U, // G_USUBO
    0U, // G_USUBE
    0U, // G_SADDO
    0U, // G_SADDE
    0U, // G_SSUBO
    0U, // G_SSUBE
    0U, // G_UMULO
    0U, // G_SMULO
    0U, // G_UMULH
    0U, // G_SMULH
    0U, // G_UADDSAT
    0U, // G_SADDSAT
    0U, // G_USUBSAT
    0U, // G_SSUBSAT
    0U, // G_USHLSAT
    0U, // G_SSHLSAT
    0U, // G_SMULFIX
    0U, // G_UMULFIX
    0U, // G_SMULFIXSAT
    0U, // G_UMULFIXSAT
    0U, // G_SDIVFIX
    0U, // G_UDIVFIX
    0U, // G_SDIVFIXSAT
    0U, // G_UDIVFIXSAT
    0U, // G_FADD
    0U, // G_FSUB
    0U, // G_FMUL
    0U, // G_FMA
    0U, // G_FMAD
    0U, // G_FDIV
    0U, // G_FREM
    0U, // G_FPOW
    0U, // G_FPOWI
    0U, // G_FEXP
    0U, // G_FEXP2
    0U, // G_FEXP10
    0U, // G_FLOG
    0U, // G_FLOG2
    0U, // G_FLOG10
    0U, // G_FLDEXP
    0U, // G_FFREXP
    0U, // G_FNEG
    0U, // G_FPEXT
    0U, // G_FPTRUNC
    0U, // G_FPTOSI
    0U, // G_FPTOUI
    0U, // G_SITOFP
    0U, // G_UITOFP
    0U, // G_FABS
    0U, // G_FCOPYSIGN
    0U, // G_IS_FPCLASS
    0U, // G_FCANONICALIZE
    0U, // G_FMINNUM
    0U, // G_FMAXNUM
    0U, // G_FMINNUM_IEEE
    0U, // G_FMAXNUM_IEEE
    0U, // G_FMINIMUM
    0U, // G_FMAXIMUM
    0U, // G_GET_FPENV
    0U, // G_SET_FPENV
    0U, // G_RESET_FPENV
    0U, // G_GET_FPMODE
    0U, // G_SET_FPMODE
    0U, // G_RESET_FPMODE
    0U, // G_PTR_ADD
    0U, // G_PTRMASK
    0U, // G_SMIN
    0U, // G_SMAX
    0U, // G_UMIN
    0U, // G_UMAX
    0U, // G_ABS
    0U, // G_LROUND
    0U, // G_LLROUND
    0U, // G_BR
    0U, // G_BRJT
    0U, // G_INSERT_VECTOR_ELT
    0U, // G_EXTRACT_VECTOR_ELT
    0U, // G_SHUFFLE_VECTOR
    0U, // G_CTTZ
    0U, // G_CTTZ_ZERO_UNDEF
    0U, // G_CTLZ
    0U, // G_CTLZ_ZERO_UNDEF
    0U, // G_CTPOP
    0U, // G_BSWAP
    0U, // G_BITREVERSE
    0U, // G_FCEIL
    0U, // G_FCOS
    0U, // G_FSIN
    0U, // G_FSQRT
    0U, // G_FFLOOR
    0U, // G_FRINT
    0U, // G_FNEARBYINT
    0U, // G_ADDRSPACE_CAST
    0U, // G_BLOCK_ADDR
    0U, // G_JUMP_TABLE
    0U, // G_DYN_STACKALLOC
    0U, // G_STACKSAVE
    0U, // G_STACKRESTORE
    0U, // G_STRICT_FADD
    0U, // G_STRICT_FSUB
    0U, // G_STRICT_FMUL
    0U, // G_STRICT_FDIV
    0U, // G_STRICT_FREM
    0U, // G_STRICT_FMA
    0U, // G_STRICT_FSQRT
    0U, // G_STRICT_FLDEXP
    0U, // G_READ_REGISTER
    0U, // G_WRITE_REGISTER
    0U, // G_MEMCPY
    0U, // G_MEMCPY_INLINE
    0U, // G_MEMMOVE
    0U, // G_MEMSET
    0U, // G_BZERO
    0U, // G_VECREDUCE_SEQ_FADD
    0U, // G_VECREDUCE_SEQ_FMUL
    0U, // G_VECREDUCE_FADD
    0U, // G_VECREDUCE_FMUL
    0U, // G_VECREDUCE_FMAX
    0U, // G_VECREDUCE_FMIN
    0U, // G_VECREDUCE_FMAXIMUM
    0U, // G_VECREDUCE_FMINIMUM
    0U, // G_VECREDUCE_ADD
    0U, // G_VECREDUCE_MUL
    0U, // G_VECREDUCE_AND
    0U, // G_VECREDUCE_OR
    0U, // G_VECREDUCE_XOR
    0U, // G_VECREDUCE_SMAX
    0U, // G_VECREDUCE_SMIN
    0U, // G_VECREDUCE_UMAX
    0U, // G_VECREDUCE_UMIN
    0U, // G_SBFX
    0U, // G_UBFX
    4609U,  // ADJCALLSTACKDOWN
    70164U, // ADJCALLSTACKUP
    8206U,  // GETPCX
    1903U,  // SELECT_CC_DFP_FCC
    2014U,  // SELECT_CC_DFP_ICC
    2125U,  // SELECT_CC_DFP_XCC
    1959U,  // SELECT_CC_FP_FCC
    2070U,  // SELECT_CC_FP_ICC
    2181U,  // SELECT_CC_FP_XCC
    1986U,  // SELECT_CC_Int_FCC
    2097U,  // SELECT_CC_Int_ICC
    2208U,  // SELECT_CC_Int_XCC
    1931U,  // SELECT_CC_QFP_FCC
    2042U,  // SELECT_CC_QFP_ICC
    2153U,  // SELECT_CC_QFP_XCC
    2111152U, // SET
    20985686U,  // SETX
    20984469U,  // ADDCCri
    20984469U,  // ADDCCrr
    20985621U,  // ADDCri
    20985621U,  // ADDCrr
    20984561U,  // ADDEri
    20984561U,  // ADDErr
    20984575U,  // ADDXC
    20984459U,  // ADDXCCC
    20984597U,  // ADDri
    20984597U,  // ADDrr
    20985170U,  // ALIGNADDR
    20984927U,  // ALIGNADDRL
    20984476U,  // ANDCCri
    20984476U,  // ANDCCrr
    20984499U,  // ANDNCCri
    20984499U,  // ANDNCCrr
    20984982U,  // ANDNri
    20984982U,  // ANDNrr
    20984665U,  // ANDri
    20984665U,  // ANDrr
    20984289U,  // ARRAY16
    20984042U,  // ARRAY32
    20984313U,  // ARRAY8
    70203U, // BA
    2247382U, // BCOND
    2312918U, // BCONDA
    87252U, // BINDri
    87252U, // BINDrr
    20984865U,  // BMASK
    21121752U,  // BPFCC
    21187288U,  // BPFCCA
    281304U,  // BPFCCANT
    346840U,  // BPFCCNT
    2509526U, // BPICC
    477910U,  // BPICCA
    543446U,  // BPICCANT
    608982U,  // BPICCNT
    21121839U,  // BPR
    21187375U,  // BPRA
    281391U,  // BPRANT
    346927U,  // BPRNT
    2771670U, // BPXCC
    740054U,  // BPXCCA
    805590U,  // BPXCCANT
    871126U,  // BPXCCNT
    20984776U,  // BSHUFFLE
    70734U, // CALL
    87118U, // CALLri
    87118U, // CALLrr
    21903970U,  // CASAri
    7289442U, // CASArr
    21903992U,  // CASXAri
    7289464U, // CASXArr
    2247381U, // CBCOND
    2312917U, // CBCONDA
    69980U, // CMASK16
    69812U, // CMASK32
    70129U, // CMASK8
    2807U,  // DONE
    20984119U,  // EDGE16
    20984881U,  // EDGE16L
    20984998U,  // EDGE16LN
    20984965U,  // EDGE16N
    20983951U,  // EDGE32
    20984872U,  // EDGE32L
    20984988U,  // EDGE32LN
    20984956U,  // EDGE32N
    20984298U,  // EDGE8
    20984890U,  // EDGE8L
    20985008U,  // EDGE8LN
    20984974U,  // EDGE8N
    2110365U, // FABSD
    2110760U, // FABSQ
    2111123U, // FABSS
    20984602U,  // FADDD
    20985056U,  // FADDQ
    20985336U,  // FADDS
    20984406U,  // FALIGNADATA
    20984664U,  // FAND
    20983899U,  // FANDNOT1
    20985235U,  // FANDNOT1S
    20984058U,  // FANDNOT2
    20985282U,  // FANDNOT2S
    20985368U,  // FANDS
    2247384U, // FBCOND
    2312920U, // FBCONDA
    1067736U, // FBCONDA_V9
    3230424U, // FBCOND_V9
    20984181U,  // FCHKSM16
    5002U,  // FCMPD
    4097U,  // FCMPD_V9
    20984200U,  // FCMPEQ16
    20984013U,  // FCMPEQ32
    20984219U,  // FCMPGT16
    20984032U,  // FCMPGT32
    20984127U,  // FCMPLE16
    20983959U,  // FCMPLE32
    20984137U,  // FCMPNE16
    20983969U,  // FCMPNE32
    5409U,  // FCMPQ
    4111U,  // FCMPQ_V9
    5736U,  // FCMPS
    4125U,  // FCMPS_V9
    20984753U,  // FDIVD
    20985148U,  // FDIVQ
    20985506U,  // FDIVS
    20985078U,  // FDMULQ
    2110476U, // FDTOI
    2110725U, // FDTOQ
    2111052U, // FDTOS
    2111288U, // FDTOX
    2110309U, // FEXPAND
    20984609U,  // FHADDD
    20985343U,  // FHADDS
    20984589U,  // FHSUBD
    20985328U,  // FHSUBS
    2110318U, // FITOD
    2110732U, // FITOQ
    2111059U, // FITOS
    150999953U, // FLCMPD
    151000687U, // FLCMPS
    2402U,  // FLUSH
    2890U,  // FLUSHW
    87015U, // FLUSHri
    87015U, // FLUSHrr
    20984191U,  // FMEAN16
    2110392U, // FMOVD
    17918705U,  // FMOVD_FCC
    17197809U,  // FMOVD_ICC
    17459953U,  // FMOVD_XCC
    2110787U, // FMOVQ
    17918755U,  // FMOVQ_FCC
    17197859U,  // FMOVQ_ICC
    17460003U,  // FMOVQ_XCC
    31466U, // FMOVRD
    31516U, // FMOVRQ
    31543U, // FMOVRS
    2111145U, // FMOVS
    17918782U,  // FMOVS_FCC
    17197886U,  // FMOVS_ICC
    17460030U,  // FMOVS_XCC
    20984277U,  // FMUL8SUX16
    20984252U,  // FMUL8ULX16
    20984229U,  // FMUL8X16
    20984898U,  // FMUL8X16AL
    20985545U,  // FMUL8X16AU
    20984649U,  // FMULD
    20984264U,  // FMULD8SUX16
    20984239U,  // FMULD8ULX16
    20985086U,  // FMULQ
    20985405U,  // FMULS
    20984626U,  // FNADDD
    20985360U,  // FNADDS
    20984670U,  // FNAND
    20985375U,  // FNANDS
    2110274U, // FNEGD
    2110703U, // FNEGQ
    2111030U, // FNEGS
    20984617U,  // FNHADDD
    20985351U,  // FNHADDS
    20984617U,  // FNMULD
    20985351U,  // FNMULS
    20985191U,  // FNOR
    20985469U,  // FNORS
    2109541U, // FNOT1
    2110878U, // FNOT1S
    2109700U, // FNOT2
    2110925U, // FNOT2S
    20985351U,  // FNSMULD
    70610U, // FONE
    71207U, // FONES
    20985186U,  // FOR
    20983916U,  // FORNOT1
    20985254U,  // FORNOT1S
    20984075U,  // FORNOT2
    20985301U,  // FORNOT2S
    20985463U,  // FORS
    2109779U, // FPACK16
    20983979U,  // FPACK32
    2111259U, // FPACKFIX
    20984110U,  // FPADD16
    20985311U,  // FPADD16S
    20983942U,  // FPADD32
    20985264U,  // FPADD32S
    20984084U,  // FPADD64
    20984767U,  // FPMERGE
    20984101U,  // FPSUB16
    20984367U,  // FPSUB16S
    20983933U,  // FPSUB32
    20984357U,  // FPSUB32S
    2110325U, // FQTOD
    2110483U, // FQTOI
    2111066U, // FQTOS
    2111304U, // FQTOX
    20984210U,  // FSLAS16
    20984023U,  // FSLAS32
    20984165U,  // FSLL16
    20983997U,  // FSLL32
    20984656U,  // FSMULD
    2110372U, // FSQRTD
    2110767U, // FSQRTQ
    2111130U, // FSQRTS
    20984093U,  // FSRA16
    20983925U,  // FSRA32
    2109524U, // FSRC1
    2110859U, // FSRC1S
    2109683U, // FSRC2
    2110906U, // FSRC2S
    20984173U,  // FSRL16
    20984005U,  // FSRL32
    2110332U, // FSTOD
    2110490U, // FSTOI
    2110739U, // FSTOQ
    2111311U, // FSTOX
    20984582U,  // FSUBD
    20985049U,  // FSUBQ
    20985321U,  // FSUBS
    20985197U,  // FXNOR
    20985476U,  // FXNORS
    20985204U,  // FXOR
    20985484U,  // FXORS
    2110339U, // FXTOD
    2110746U, // FXTOQ
    2111073U, // FXTOS
    70854U, // FZERO
    71236U, // FZEROS
    288525007U, // GDOP_LDXrr
    288524957U, // GDOP_LDrr
    2131033U, // JMPLri
    2131033U, // JMPLrr
    3050045U, // LDAri
    26184253U,  // LDArr
    1268381U, // LDCSRri
    1268381U, // LDCSRrr
    3312285U, // LDCri
    3312285U, // LDCrr
    3050038U, // LDDAri
    26184246U,  // LDDArr
    3312279U, // LDDCri
    3312279U, // LDDCrr
    3050038U, // LDDFAri
    26184246U,  // LDDFArr
    3312279U, // LDDFri
    3312279U, // LDDFrr
    3312279U, // LDDri
    3312279U, // LDDrr
    3050045U, // LDFAri
    26184253U,  // LDFArr
    1333917U, // LDFSRri
    1333917U, // LDFSRrr
    3312285U, // LDFri
    3312285U, // LDFrr
    3050075U, // LDQFAri
    26184283U,  // LDQFArr
    3312322U, // LDQFri
    3312322U, // LDQFrr
    3050012U, // LDSBAri
    26184220U,  // LDSBArr
    3312256U, // LDSBri
    3312256U, // LDSBrr
    3050051U, // LDSHAri
    26184259U,  // LDSHArr
    3312301U, // LDSHri
    3312301U, // LDSHrr
    3050028U, // LDSTUBAri
    26184236U,  // LDSTUBArr
    3312270U, // LDSTUBri
    3312270U, // LDSTUBrr
    3050089U, // LDSWAri
    26184297U,  // LDSWArr
    3312328U, // LDSWri
    3312328U, // LDSWrr
    3050020U, // LDUBAri
    26184228U,  // LDUBArr
    3312263U, // LDUBri
    3312263U, // LDUBrr
    3050059U, // LDUHAri
    26184267U,  // LDUHArr
    3312308U, // LDUHri
    3312308U, // LDUHrr
    3050097U, // LDXAri
    26184305U,  // LDXArr
    1333967U, // LDXFSRri
    1333967U, // LDXFSRrr
    3312335U, // LDXri
    3312335U, // LDXrr
    3312285U, // LDri
    3312285U, // LDrr
    2111157U, // LZCNT
    38218U, // MEMBARi
    2111295U, // MOVDTOX
    17918790U,  // MOVFCCri
    17918790U,  // MOVFCCrr
    17197894U,  // MOVICCri
    17197894U,  // MOVICCrr
    31538U, // MOVRri
    31538U, // MOVRrr
    2111221U, // MOVSTOSW
    2111231U, // MOVSTOUW
    2111295U, // MOVWTOS
    17460038U,  // MOVXCCri
    17460038U,  // MOVXCCrr
    2111295U, // MOVXTOD
    20984529U,  // MULSCCri
    20984529U,  // MULSCCrr
    20985650U,  // MULXri
    20985650U,  // MULXrr
    2840U,  // NOP
    20984516U,  // ORCCri
    20984516U,  // ORCCrr
    20984507U,  // ORNCCri
    20984507U,  // ORNCCrr
    20985017U,  // ORNri
    20985017U,  // ORNrr
    20985187U,  // ORri
    20985187U,  // ORrr
    20985532U,  // PDIST
    20985022U,  // PDISTN
    2110201U, // POPCrr
    5397154U, // PREFETCHi
    5397154U, // PREFETCHr
    33559942U,  // PWRPSRri
    33559942U,  // PWRPSRrr
    2110361U, // RDASR
    69685U, // RDFQ
    2110842U, // RDPR
    69706U, // RDPSR
    69696U, // RDTBR
    69675U, // RDWIM
    2779U,  // RESTORED
    20984792U,  // RESTOREri
    20984792U,  // RESTORErr
    71868U, // RET
    71877U, // RETL
    2897U,  // RETRY
    87747U, // RETTri
    87747U, // RETTrr
    2788U,  // SAVED
    20984801U,  // SAVEri
    20984801U,  // SAVErr
    20984537U,  // SDIVCCri
    20984537U,  // SDIVCCrr
    20985697U,  // SDIVXri
    20985697U,  // SDIVXrr
    20985557U,  // SDIVri
    20985557U,  // SDIVrr
    2110451U, // SETHIi
    2831U,  // SHUTDOWN
    2826U,  // SIAM
    71005U, // SIR
    20985637U,  // SLLXri
    20985637U,  // SLLXrr
    20984916U,  // SLLri
    20984916U,  // SLLrr
    20984439U,  // SMACri
    20984439U,  // SMACrr
    20984483U,  // SMULCCri
    20984483U,  // SMULCCrr
    20984944U,  // SMULri
    20984944U,  // SMULrr
    20985609U,  // SRAXri
    20985609U,  // SRAXrr
    20984401U,  // SRAri
    20984401U,  // SRArr
    20985643U,  // SRLXri
    20985643U,  // SRLXrr
    20984939U,  // SRLri
    20984939U,  // SRLrr
    1417826U, // STAri
    9413218U, // STArr
    2857U,  // STBAR
    1417785U, // STBAri
    9413177U, // STBArr
    1483373U, // STBri
    1483373U, // STBrr
    1464826U, // STCSRri
    1464826U, // STCSRrr
    1484479U, // STCri
    1484479U, // STCrr
    1417791U, // STDAri
    9413183U, // STDArr
    1464804U, // STDCQri
    1464804U, // STDCQrr
    1483692U, // STDCri
    1483692U, // STDCrr
    1417791U, // STDFAri
    9413183U, // STDFArr
    1464815U, // STDFQri
    1464815U, // STDFQrr
    1483692U, // STDFri
    1483692U, // STDFrr
    1483692U, // STDri
    1483692U, // STDrr
    1417826U, // STFAri
    9413218U, // STFArr
    1464837U, // STFSRri
    1464837U, // STFSRrr
    1484479U, // STFri
    1484479U, // STFrr
    1417797U, // STHAri
    9413189U, // STHArr
    1483758U, // STHri
    1483758U, // STHrr
    1417803U, // STQFAri
    9413195U, // STQFArr
    1484087U, // STQFri
    1484087U, // STQFrr
    1417831U, // STXAri
    9413223U, // STXArr
    1464848U, // STXFSRri
    1464848U, // STXFSRrr
    1484636U, // STXri
    1484636U, // STXrr
    1484479U, // STri
    1484479U, // STrr
    20984452U,  // SUBCCri
    20984452U,  // SUBCCrr
    20985615U,  // SUBCri
    20985615U,  // SUBCrr
    20984553U,  // SUBEri
    20984553U,  // SUBErr
    20984434U,  // SUBri
    20984434U,  // SUBrr
    3050067U, // SWAPAri
    26184275U,  // SWAPArr
    3312315U, // SWAPri
    3312315U, // SWAPrr
    2412U,  // TA1
    2417U,  // TA3
    2422U,  // TA5
    20985579U,  // TADDCCTVri
    20985579U,  // TADDCCTVrr
    20984468U,  // TADDCCri
    20984468U,  // TADDCCrr
    70734U, // TAIL_CALL
    87252U, // TAIL_CALLri
    52869956U,  // TICCri
    52869956U,  // TICCrr
    557855509U, // TLS_ADDrr
    5198U,  // TLS_CALL
    288525007U, // TLS_LDXrr
    288524957U, // TLS_LDrr
    52607812U,  // TRAPri
    52607812U,  // TRAPrr
    20985569U,  // TSUBCCTVri
    20985569U,  // TSUBCCTVrr
    20984451U,  // TSUBCCri
    20984451U,  // TSUBCCrr
    53132100U,  // TXCCri
    53132100U,  // TXCCrr
    20984545U,  // UDIVCCri
    20984545U,  // UDIVCCrr
    20985704U,  // UDIVXri
    20985704U,  // UDIVXrr
    20985563U,  // UDIVri
    20985563U,  // UDIVrr
    20984445U,  // UMACri
    20984445U,  // UMACrr
    20984491U,  // UMULCCri
    20984491U,  // UMULCCrr
    20984826U,  // UMULXHI
    20984950U,  // UMULri
    20984950U,  // UMULrr
    70861U, // UNIMP
    150999946U, // V9FCMPD
    150999866U, // V9FCMPED
    151000295U, // V9FCMPEQ
    151000622U, // V9FCMPES
    151000353U, // V9FCMPQ
    151000680U, // V9FCMPS
    31473U, // V9FMOVD_FCC
    31523U, // V9FMOVQ_FCC
    31550U, // V9FMOVS_FCC
    31558U, // V9MOVFCCri
    31558U, // V9MOVFCCrr
    20985223U,  // WRASRri
    20985223U,  // WRASRrr
    20985216U,  // WRPRri
    20985216U,  // WRPRrr
    33559943U,  // WRPSRri
    33559943U,  // WRPSRrr
    67114375U,  // WRTBRri
    67114375U,  // WRTBRrr
    83891591U,  // WRWIMri
    83891591U,  // WRWIMrr
    20985649U,  // XMULX
    20984835U,  // XMULXHI
    20984514U,  // XNORCCri
    20984514U,  // XNORCCrr
    20985198U,  // XNORri
    20985198U,  // XNORrr
    20984522U,  // XORCCri
    20984522U,  // XORCCrr
    20985205U,  // XORri
    20985205U,  // XORrr
  };

  // Emit the opcode for the instruction.
  uint32_t Bits = 0;
  Bits |= OpInfo0[MI->getOpcode()] << 0;
  if (Bits == 0)
    return {nullptr, Bits};
  return {AsmStrs+(Bits & 4095)-1, Bits};

}
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
LLVM_NO_PROFILE_INSTRUMENT_FUNCTION
void SparcInstPrinter::printInstruction(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &O) {
  O << "\t";

  auto MnemonicInfo = getMnemonic(MI);

  O << MnemonicInfo.first;

  uint32_t Bits = MnemonicInfo.second;
  assert(Bits != 0 && "Cannot print this instruction.");

  // Fragment 0 encoded into 4 bits for 12 unique commands.
  switch ((Bits >> 12) & 15) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
    return;
    break;
  case 1:
    // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
    printOperand(MI, 0, STI, O);
    break;
  case 2:
    // GETPCX
    printGetPCX(MI, 0, STI, O);
    return;
    break;
  case 3:
    // SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, AD...
    printOperand(MI, 1, STI, O);
    break;
  case 4:
    // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
    printCCOperand(MI, 1, STI, O);
    break;
  case 5:
    // BINDri, BINDrr, CALLri, CALLrr, FLUSHri, FLUSHrr, LDCSRri, LDCSRrr, LD...
    printMemOperand(MI, 0, STI, O);
    break;
  case 6:
    // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
    printCCOperand(MI, 3, STI, O);
    break;
  case 7:
    // FMOVRD, FMOVRQ, FMOVRS, MOVRri, MOVRrr, V9FMOVD_FCC, V9FMOVQ_FCC, V9FM...
    printCCOperand(MI, 4, STI, O);
    O << ' ';
    printOperand(MI, 1, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    O << ", ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 8:
    // GDOP_LDXrr, GDOP_LDrr, JMPLri, JMPLrr, LDAri, LDArr, LDCri, LDCrr, LDD...
    printMemOperand(MI, 1, STI, O);
    break;
  case 9:
    // MEMBARi
    printMembarTag(MI, 0, STI, O);
    return;
    break;
  case 10:
    // STAri, STArr, STBAri, STBArr, STBri, STBrr, STCri, STCrr, STDAri, STDA...
    printOperand(MI, 2, STI, O);
    O << ", [";
    printMemOperand(MI, 0, STI, O);
    break;
  case 11:
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
    printCCOperand(MI, 2, STI, O);
    break;
  }


  // Fragment 1 encoded into 5 bits for 23 unique commands.
  switch ((Bits >> 16) & 31) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ADJCALLSTACKDOWN, SET, SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri,...
    O << ", ";
    break;
  case 1:
    // ADJCALLSTACKUP, BA, BINDri, BINDrr, CALL, CALLri, CALLrr, CMASK16, CMA...
    return;
    break;
  case 2:
    // BCOND, BPFCC, BPR, CBCOND, FBCOND, TRAPri, TRAPrr
    O << ' ';
    break;
  case 3:
    // BCONDA, BPFCCA, BPRA, CBCONDA, FBCONDA
    O << ",a ";
    break;
  case 4:
    // BPFCCANT, BPRANT
    O << ",a,pn ";
    printOperand(MI, 2, STI, O);
    O << ", ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 5:
    // BPFCCNT, BPRNT
    O << ",pn ";
    printOperand(MI, 2, STI, O);
    O << ", ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 6:
    // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
    O << " %icc, ";
    break;
  case 7:
    // BPICCA
    O << ",a %icc, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 8:
    // BPICCANT
    O << ",a,pn %icc, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 9:
    // BPICCNT
    O << ",pn %icc, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 10:
    // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
    O << " %xcc, ";
    break;
  case 11:
    // BPXCCA
    O << ",a %xcc, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 12:
    // BPXCCANT
    O << ",a,pn %xcc, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 13:
    // BPXCCNT
    O << ",pn %xcc, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 14:
    // CASAri, CASXAri, LDAri, LDDAri, LDDFAri, LDFAri, LDQFAri, LDSBAri, LDS...
    O << "] %asi, ";
    break;
  case 15:
    // CASArr, CASXArr, LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDS...
    O << "] ";
    break;
  case 16:
    // FBCONDA_V9
    O << ",a %fcc0, ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 17:
    // FBCOND_V9, FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
    O << " %fcc0, ";
    break;
  case 18:
    // GDOP_LDXrr, GDOP_LDrr, LDCri, LDCrr, LDDCri, LDDCrr, LDDFri, LDDFrr, L...
    O << "], ";
    break;
  case 19:
    // LDCSRri, LDCSRrr
    O << "], %csr";
    return;
    break;
  case 20:
    // LDFSRri, LDFSRrr, LDXFSRri, LDXFSRrr
    O << "], %fsr";
    return;
    break;
  case 21:
    // STAri, STBAri, STDAri, STDFAri, STFAri, STHAri, STQFAri, STXAri
    O << "] %asi";
    return;
    break;
  case 22:
    // STBri, STBrr, STCSRri, STCSRrr, STCri, STCrr, STDCQri, STDCQrr, STDCri...
    O << ']';
    return;
    break;
  }


  // Fragment 2 encoded into 3 bits for 5 unique commands.
  switch ((Bits >> 21) & 7) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ADJCALLSTACKDOWN, FCMPD, FCMPD_V9, FCMPQ, FCMPQ_V9, FCMPS, FCMPS_V9, F...
    printOperand(MI, 1, STI, O);
    break;
  case 1:
    // SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, FABSD, FABSQ, FABSS...
    printOperand(MI, 0, STI, O);
    break;
  case 2:
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    printOperand(MI, 2, STI, O);
    break;
  case 3:
    // CASArr, CASXArr
    printASITag(MI, 4, STI, O);
    O << ", ";
    printOperand(MI, 2, STI, O);
    O << ", ";
    printOperand(MI, 0, STI, O);
    return;
    break;
  case 4:
    // LDArr, LDDArr, LDDFArr, LDFArr, LDQFArr, LDSBArr, LDSHArr, LDSTUBArr, ...
    printASITag(MI, 3, STI, O);
    break;
  }


  // Fragment 3 encoded into 3 bits for 6 unique commands.
  switch ((Bits >> 24) & 7) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // ADJCALLSTACKDOWN, SET, BCOND, BCONDA, BPICC, BPXCC, CBCOND, CBCONDA, F...
    return;
    break;
  case 1:
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    O << ", ";
    break;
  case 2:
    // PWRPSRri, PWRPSRrr, WRPSRri, WRPSRrr
    O << ", %psr";
    return;
    break;
  case 3:
    // TICCri, TICCrr, TRAPri, TRAPrr, TXCCri, TXCCrr
    O << " + ";
    printOperand(MI, 1, STI, O);
    return;
    break;
  case 4:
    // WRTBRri, WRTBRrr
    O << ", %tbr";
    return;
    break;
  case 5:
    // WRWIMri, WRWIMrr
    O << ", %wim";
    return;
    break;
  }


  // Fragment 4 encoded into 2 bits for 3 unique commands.
  switch ((Bits >> 27) & 3) {
  default: llvm_unreachable("Invalid command number.");
  case 0:
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    printOperand(MI, 0, STI, O);
    break;
  case 1:
    // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
    printOperand(MI, 2, STI, O);
    return;
    break;
  case 2:
    // GDOP_LDXrr, GDOP_LDrr, TLS_LDXrr, TLS_LDrr
    printOperand(MI, 3, STI, O);
    return;
    break;
  }


  // Fragment 5 encoded into 1 bits for 2 unique commands.
  if ((Bits >> 29) & 1) {
    // TLS_ADDrr
    O << ", ";
    printOperand(MI, 3, STI, O);
    return;
  } else {
    // SETX, ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC...
    return;
  }

}


/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description.  This returns the assembler name
/// for the specified register.
const char *SparcInstPrinter::
getRegisterName(MCRegister Reg, unsigned AltIdx) {
  unsigned RegNo = Reg.id();
  assert(RegNo && RegNo < 238 && "Invalid register number!");


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
  static const char AsmStrsNoRegAltName[] = {
  /* 0 */ "c10\0"
  /* 4 */ "f10\0"
  /* 8 */ "asr10\0"
  /* 14 */ "c20\0"
  /* 18 */ "f20\0"
  /* 22 */ "asr20\0"
  /* 28 */ "c30\0"
  /* 32 */ "f30\0"
  /* 36 */ "asr30\0"
  /* 42 */ "f40\0"
  /* 46 */ "f50\0"
  /* 50 */ "f60\0"
  /* 54 */ "fcc0\0"
  /* 59 */ "f0\0"
  /* 62 */ "g0\0"
  /* 65 */ "i0\0"
  /* 68 */ "l0\0"
  /* 71 */ "o0\0"
  /* 74 */ "c11\0"
  /* 78 */ "f11\0"
  /* 82 */ "asr11\0"
  /* 88 */ "c21\0"
  /* 92 */ "f21\0"
  /* 96 */ "asr21\0"
  /* 102 */ "c31\0"
  /* 106 */ "f31\0"
  /* 110 */ "asr31\0"
  /* 116 */ "fcc1\0"
  /* 121 */ "f1\0"
  /* 124 */ "g1\0"
  /* 127 */ "i1\0"
  /* 130 */ "l1\0"
  /* 133 */ "o1\0"
  /* 136 */ "asr1\0"
  /* 141 */ "c12\0"
  /* 145 */ "f12\0"
  /* 149 */ "asr12\0"
  /* 155 */ "c22\0"
  /* 159 */ "f22\0"
  /* 163 */ "asr22\0"
  /* 169 */ "f32\0"
  /* 173 */ "f42\0"
  /* 177 */ "f52\0"
  /* 181 */ "f62\0"
  /* 185 */ "fcc2\0"
  /* 190 */ "f2\0"
  /* 193 */ "g2\0"
  /* 196 */ "i2\0"
  /* 199 */ "l2\0"
  /* 202 */ "o2\0"
  /* 205 */ "asr2\0"
  /* 210 */ "c13\0"
  /* 214 */ "f13\0"
  /* 218 */ "asr13\0"
  /* 224 */ "c23\0"
  /* 228 */ "f23\0"
  /* 232 */ "asr23\0"
  /* 238 */ "fcc3\0"
  /* 243 */ "f3\0"
  /* 246 */ "g3\0"
  /* 249 */ "i3\0"
  /* 252 */ "l3\0"
  /* 255 */ "o3\0"
  /* 258 */ "asr3\0"
  /* 263 */ "c14\0"
  /* 267 */ "f14\0"
  /* 271 */ "asr14\0"
  /* 277 */ "c24\0"
  /* 281 */ "f24\0"
  /* 285 */ "asr24\0"
  /* 291 */ "f34\0"
  /* 295 */ "f44\0"
  /* 299 */ "f54\0"
  /* 303 */ "c4\0"
  /* 306 */ "f4\0"
  /* 309 */ "g4\0"
  /* 312 */ "i4\0"
  /* 315 */ "l4\0"
  /* 318 */ "o4\0"
  /* 321 */ "asr4\0"
  /* 326 */ "c15\0"
  /* 330 */ "f15\0"
  /* 334 */ "asr15\0"
  /* 340 */ "c25\0"
  /* 344 */ "f25\0"
  /* 348 */ "asr25\0"
  /* 354 */ "c5\0"
  /* 357 */ "f5\0"
  /* 360 */ "g5\0"
  /* 363 */ "i5\0"
  /* 366 */ "l5\0"
  /* 369 */ "o5\0"
  /* 372 */ "asr5\0"
  /* 377 */ "c16\0"
  /* 381 */ "f16\0"
  /* 385 */ "asr16\0"
  /* 391 */ "c26\0"
  /* 395 */ "f26\0"
  /* 399 */ "asr26\0"
  /* 405 */ "f36\0"
  /* 409 */ "f46\0"
  /* 413 */ "f56\0"
  /* 417 */ "c6\0"
  /* 420 */ "f6\0"
  /* 423 */ "g6\0"
  /* 426 */ "i6\0"
  /* 429 */ "l6\0"
  /* 432 */ "o6\0"
  /* 435 */ "asr6\0"
  /* 440 */ "c17\0"
  /* 444 */ "f17\0"
  /* 448 */ "asr17\0"
  /* 454 */ "c27\0"
  /* 458 */ "f27\0"
  /* 462 */ "asr27\0"
  /* 468 */ "c7\0"
  /* 471 */ "f7\0"
  /* 474 */ "g7\0"
  /* 477 */ "i7\0"
  /* 480 */ "l7\0"
  /* 483 */ "o7\0"
  /* 486 */ "asr7\0"
  /* 491 */ "c18\0"
  /* 495 */ "f18\0"
  /* 499 */ "asr18\0"
  /* 505 */ "c28\0"
  /* 509 */ "f28\0"
  /* 513 */ "asr28\0"
  /* 519 */ "f38\0"
  /* 523 */ "f48\0"
  /* 527 */ "f58\0"
  /* 531 */ "c8\0"
  /* 534 */ "f8\0"
  /* 537 */ "asr8\0"
  /* 542 */ "c19\0"
  /* 546 */ "f19\0"
  /* 550 */ "asr19\0"
  /* 556 */ "c29\0"
  /* 560 */ "f29\0"
  /* 564 */ "asr29\0"
  /* 570 */ "c9\0"
  /* 573 */ "f9\0"
  /* 576 */ "asr9\0"
  /* 581 */ "tba\0"
  /* 585 */ "icc\0"
  /* 589 */ "tnpc\0"
  /* 594 */ "tpc\0"
  /* 598 */ "canrestore\0"
  /* 609 */ "pstate\0"
  /* 616 */ "tstate\0"
  /* 623 */ "wstate\0"
  /* 630 */ "cansave\0"
  /* 638 */ "tick\0"
  /* 643 */ "gl\0"
  /* 646 */ "pil\0"
  /* 650 */ "tl\0"
  /* 653 */ "wim\0"
  /* 657 */ "cleanwin\0"
  /* 666 */ "otherwin\0"
  /* 675 */ "fp\0"
  /* 678 */ "sp\0"
  /* 681 */ "cwp\0"
  /* 685 */ "cq\0"
  /* 688 */ "fq\0"
  /* 691 */ "tbr\0"
  /* 695 */ "ver\0"
  /* 699 */ "csr\0"
  /* 703 */ "fsr\0"
  /* 707 */ "psr\0"
  /* 711 */ "tt\0"
  /* 714 */ "y\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

  static const uint16_t RegAsmOffsetNoRegAltName[] = {
    598, 630, 657, 685, 699, 681, 688, 703, 643, 585, 666, 646, 707, 609, 
    581, 691, 638, 650, 589, 594, 616, 711, 695, 653, 623, 714, 136, 205, 
    258, 321, 372, 435, 486, 537, 576, 8, 82, 149, 218, 271, 334, 385, 
    448, 499, 550, 22, 96, 163, 232, 285, 348, 399, 462, 513, 564, 36, 
    110, 56, 118, 187, 240, 303, 354, 417, 468, 531, 570, 0, 74, 141, 
    210, 263, 326, 377, 440, 491, 542, 14, 88, 155, 224, 277, 340, 391, 
    454, 505, 556, 28, 102, 59, 190, 306, 420, 534, 4, 145, 267, 381, 
    495, 18, 159, 281, 395, 509, 32, 169, 291, 405, 519, 42, 173, 295, 
    409, 523, 46, 177, 299, 413, 527, 50, 181, 59, 121, 190, 243, 306, 
    357, 420, 471, 534, 573, 4, 78, 145, 214, 267, 330, 381, 444, 495, 
    546, 18, 92, 159, 228, 281, 344, 395, 458, 509, 560, 32, 106, 54, 
    116, 185, 238, 62, 124, 193, 246, 309, 360, 423, 474, 65, 127, 196, 
    249, 312, 363, 675, 477, 68, 130, 199, 252, 315, 366, 429, 480, 71, 
    133, 202, 255, 318, 369, 678, 483, 59, 306, 534, 145, 381, 18, 281, 
    509, 169, 405, 42, 295, 523, 177, 413, 50, 56, 187, 303, 417, 531, 
    0, 141, 263, 377, 491, 14, 155, 277, 391, 505, 28, 62, 193, 309, 
    423, 65, 196, 312, 426, 68, 199, 315, 429, 71, 202, 318, 432, 
  };


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
  static const char AsmStrsRegNamesStateReg[] = {
  /* 0 */ "pc\0"
  /* 3 */ "asi\0"
  /* 7 */ "tick\0"
  /* 12 */ "ccr\0"
  /* 16 */ "fprs\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

  static const uint8_t RegAsmOffsetRegNamesStateReg[] = {
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 12, 
    3, 7, 0, 16, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 
  };

  switch(AltIdx) {
  default: llvm_unreachable("Invalid register alt name index!");
  case SP::NoRegAltName:
    assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
           "Invalid alt name index for register!");
    return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
  case SP::RegNamesStateReg:
    if (!*(AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1]))
      return getRegisterName(RegNo, SP::NoRegAltName);
    return AsmStrsRegNamesStateReg+RegAsmOffsetRegNamesStateReg[RegNo-1];
  }
}

#ifdef PRINT_ALIAS_INSTR
#undef PRINT_ALIAS_INSTR

bool SparcInstPrinter::printAliasInstr(const MCInst *MI, uint64_t Address, const MCSubtargetInfo &STI, raw_ostream &OS) {
  static const PatternsForOpcode OpToPatterns[] = {
    {SP::BCOND, 0, 16 },
    {SP::BCONDA, 16, 16 },
    {SP::BPFCCANT, 32, 16 },
    {SP::BPFCCNT, 48, 16 },
    {SP::BPICCANT, 64, 16 },
    {SP::BPICCNT, 80, 16 },
    {SP::BPRANT, 96, 6 },
    {SP::BPRNT, 102, 6 },
    {SP::BPXCCANT, 108, 16 },
    {SP::BPXCCNT, 124, 16 },
    {SP::CASArr, 140, 2 },
    {SP::CASXArr, 142, 2 },
    {SP::FMOVD_ICC, 144, 16 },
    {SP::FMOVD_XCC, 160, 16 },
    {SP::FMOVQ_ICC, 176, 16 },
    {SP::FMOVQ_XCC, 192, 16 },
    {SP::FMOVRD, 208, 6 },
    {SP::FMOVRQ, 214, 6 },
    {SP::FMOVRS, 220, 6 },
    {SP::FMOVS_ICC, 226, 16 },
    {SP::FMOVS_XCC, 242, 16 },
    {SP::MOVICCri, 258, 16 },
    {SP::MOVICCrr, 274, 16 },
    {SP::MOVRri, 290, 6 },
    {SP::MOVRrr, 296, 6 },
    {SP::MOVXCCri, 302, 16 },
    {SP::MOVXCCrr, 318, 16 },
    {SP::ORCCrr, 334, 1 },
    {SP::ORri, 335, 1 },
    {SP::ORrr, 336, 1 },
    {SP::RESTORErr, 337, 1 },
    {SP::RET, 338, 1 },
    {SP::RETL, 339, 1 },
    {SP::SAVErr, 340, 1 },
    {SP::SUBCCri, 341, 1 },
    {SP::SUBCCrr, 342, 1 },
    {SP::TICCri, 343, 32 },
    {SP::TICCrr, 375, 32 },
    {SP::TRAPri, 407, 32 },
    {SP::TRAPrr, 439, 32 },
    {SP::TXCCri, 471, 32 },
    {SP::TXCCrr, 503, 32 },
    {SP::V9FCMPD, 535, 1 },
    {SP::V9FCMPED, 536, 1 },
    {SP::V9FCMPEQ, 537, 1 },
    {SP::V9FCMPES, 538, 1 },
    {SP::V9FCMPQ, 539, 1 },
    {SP::V9FCMPS, 540, 1 },
    {SP::V9FMOVD_FCC, 541, 16 },
    {SP::V9FMOVQ_FCC, 557, 16 },
    {SP::V9FMOVS_FCC, 573, 16 },
    {SP::V9MOVFCCri, 589, 16 },
    {SP::V9MOVFCCrr, 605, 16 },
  };

  static const AliasPattern Patterns[] = {
    // SP::BCOND - 0
    {0, 0, 2, 2 },
    {6, 2, 2, 2 },
    {12, 4, 2, 2 },
    {19, 6, 2, 2 },
    {25, 8, 2, 2 },
    {31, 10, 2, 2 },
    {38, 12, 2, 2 },
    {45, 14, 2, 2 },
    {51, 16, 2, 2 },
    {58, 18, 2, 2 },
    {66, 20, 2, 2 },
    {73, 22, 2, 2 },
    {80, 24, 2, 2 },
    {88, 26, 2, 2 },
    {96, 28, 2, 2 },
    {103, 30, 2, 2 },
    // SP::BCONDA - 16
    {110, 32, 2, 2 },
    {118, 34, 2, 2 },
    {126, 36, 2, 2 },
    {135, 38, 2, 2 },
    {143, 40, 2, 2 },
    {151, 42, 2, 2 },
    {160, 44, 2, 2 },
    {169, 46, 2, 2 },
    {177, 48, 2, 2 },
    {186, 50, 2, 2 },
    {196, 52, 2, 2 },
    {205, 54, 2, 2 },
    {214, 56, 2, 2 },
    {224, 58, 2, 2 },
    {234, 60, 2, 2 },
    {243, 62, 2, 2 },
    // SP::BPFCCANT - 32
    {252, 64, 3, 4 },
    {268, 68, 3, 4 },
    {284, 72, 3, 4 },
    {300, 76, 3, 4 },
    {316, 80, 3, 4 },
    {333, 84, 3, 4 },
    {349, 88, 3, 4 },
    {366, 92, 3, 4 },
    {383, 96, 3, 4 },
    {400, 100, 3, 4 },
    {416, 104, 3, 4 },
    {433, 108, 3, 4 },
    {450, 112, 3, 4 },
    {468, 116, 3, 4 },
    {485, 120, 3, 4 },
    {503, 124, 3, 4 },
    // SP::BPFCCNT - 48
    {519, 128, 3, 4 },
    {533, 132, 3, 4 },
    {547, 136, 3, 4 },
    {561, 140, 3, 4 },
    {575, 144, 3, 4 },
    {590, 148, 3, 4 },
    {604, 152, 3, 4 },
    {619, 156, 3, 4 },
    {634, 160, 3, 4 },
    {649, 164, 3, 4 },
    {663, 168, 3, 4 },
    {678, 172, 3, 4 },
    {693, 176, 3, 4 },
    {709, 180, 3, 4 },
    {724, 184, 3, 4 },
    {740, 188, 3, 4 },
    // SP::BPICCANT - 64
    {754, 192, 2, 3 },
    {771, 195, 2, 3 },
    {788, 198, 2, 3 },
    {806, 201, 2, 3 },
    {823, 204, 2, 3 },
    {840, 207, 2, 3 },
    {858, 210, 2, 3 },
    {876, 213, 2, 3 },
    {893, 216, 2, 3 },
    {911, 219, 2, 3 },
    {930, 222, 2, 3 },
    {948, 225, 2, 3 },
    {966, 228, 2, 3 },
    {985, 231, 2, 3 },
    {1004, 234, 2, 3 },
    {1022, 237, 2, 3 },
    // SP::BPICCNT - 80
    {1040, 240, 2, 3 },
    {1055, 243, 2, 3 },
    {1070, 246, 2, 3 },
    {1086, 249, 2, 3 },
    {1101, 252, 2, 3 },
    {1116, 255, 2, 3 },
    {1132, 258, 2, 3 },
    {1148, 261, 2, 3 },
    {1163, 264, 2, 3 },
    {1179, 267, 2, 3 },
    {1196, 270, 2, 3 },
    {1212, 273, 2, 3 },
    {1228, 276, 2, 3 },
    {1245, 279, 2, 3 },
    {1262, 282, 2, 3 },
    {1278, 285, 2, 3 },
    // SP::BPRANT - 96
    {1294, 288, 3, 3 },
    {1310, 291, 3, 3 },
    {1328, 294, 3, 3 },
    {1345, 297, 3, 3 },
    {1362, 300, 3, 3 },
    {1379, 303, 3, 3 },
    // SP::BPRNT - 102
    {1397, 306, 3, 3 },
    {1411, 309, 3, 3 },
    {1427, 312, 3, 3 },
    {1442, 315, 3, 3 },
    {1457, 318, 3, 3 },
    {1472, 321, 3, 3 },
    // SP::BPXCCANT - 108
    {1488, 324, 2, 2 },
    {1505, 326, 2, 2 },
    {1522, 328, 2, 2 },
    {1540, 330, 2, 2 },
    {1557, 332, 2, 2 },
    {1574, 334, 2, 2 },
    {1592, 336, 2, 2 },
    {1610, 338, 2, 2 },
    {1627, 340, 2, 2 },
    {1645, 342, 2, 2 },
    {1664, 344, 2, 2 },
    {1682, 346, 2, 2 },
    {1700, 348, 2, 2 },
    {1719, 350, 2, 2 },
    {1738, 352, 2, 2 },
    {1756, 354, 2, 2 },
    // SP::BPXCCNT - 124
    {1774, 356, 2, 2 },
    {1789, 358, 2, 2 },
    {1804, 360, 2, 2 },
    {1820, 362, 2, 2 },
    {1835, 364, 2, 2 },
    {1850, 366, 2, 2 },
    {1866, 368, 2, 2 },
    {1882, 370, 2, 2 },
    {1897, 372, 2, 2 },
    {1913, 374, 2, 2 },
    {1930, 376, 2, 2 },
    {1946, 378, 2, 2 },
    {1962, 380, 2, 2 },
    {1979, 382, 2, 2 },
    {1996, 384, 2, 2 },
    {2012, 386, 2, 2 },
    // SP::CASArr - 140
    {2028, 388, 5, 6 },
    {2045, 394, 5, 6 },
    // SP::CASXArr - 142
    {2063, 400, 5, 6 },
    {2081, 406, 5, 6 },
    // SP::FMOVD_ICC - 144
    {2100, 412, 4, 5 },
    {2120, 417, 4, 5 },
    {2140, 422, 4, 5 },
    {2161, 427, 4, 5 },
    {2181, 432, 4, 5 },
    {2201, 437, 4, 5 },
    {2222, 442, 4, 5 },
    {2243, 447, 4, 5 },
    {2263, 452, 4, 5 },
    {2284, 457, 4, 5 },
    {2306, 462, 4, 5 },
    {2327, 467, 4, 5 },
    {2348, 472, 4, 5 },
    {2370, 477, 4, 5 },
    {2392, 482, 4, 5 },
    {2413, 487, 4, 5 },
    // SP::FMOVD_XCC - 160
    {2434, 492, 4, 4 },
    {2454, 496, 4, 4 },
    {2474, 500, 4, 4 },
    {2495, 504, 4, 4 },
    {2515, 508, 4, 4 },
    {2535, 512, 4, 4 },
    {2556, 516, 4, 4 },
    {2577, 520, 4, 4 },
    {2597, 524, 4, 4 },
    {2618, 528, 4, 4 },
    {2640, 532, 4, 4 },
    {2661, 536, 4, 4 },
    {2682, 540, 4, 4 },
    {2704, 544, 4, 4 },
    {2726, 548, 4, 4 },
    {2747, 552, 4, 4 },
    // SP::FMOVQ_ICC - 176
    {2768, 556, 4, 5 },
    {2788, 561, 4, 5 },
    {2808, 566, 4, 5 },
    {2829, 571, 4, 5 },
    {2849, 576, 4, 5 },
    {2869, 581, 4, 5 },
    {2890, 586, 4, 5 },
    {2911, 591, 4, 5 },
    {2931, 596, 4, 5 },
    {2952, 601, 4, 5 },
    {2974, 606, 4, 5 },
    {2995, 611, 4, 5 },
    {3016, 616, 4, 5 },
    {3038, 621, 4, 5 },
    {3060, 626, 4, 5 },
    {3081, 631, 4, 5 },
    // SP::FMOVQ_XCC - 192
    {3102, 636, 4, 4 },
    {3122, 640, 4, 4 },
    {3142, 644, 4, 4 },
    {3163, 648, 4, 4 },
    {3183, 652, 4, 4 },
    {3203, 656, 4, 4 },
    {3224, 660, 4, 4 },
    {3245, 664, 4, 4 },
    {3265, 668, 4, 4 },
    {3286, 672, 4, 4 },
    {3308, 676, 4, 4 },
    {3329, 680, 4, 4 },
    {3350, 684, 4, 4 },
    {3372, 688, 4, 4 },
    {3394, 692, 4, 4 },
    {3415, 696, 4, 4 },
    // SP::FMOVRD - 208
    {3436, 700, 5, 5 },
    {3455, 705, 5, 5 },
    {3476, 710, 5, 5 },
    {3496, 715, 5, 5 },
    {3516, 720, 5, 5 },
    {3536, 725, 5, 5 },
    // SP::FMOVRQ - 214
    {3557, 730, 5, 5 },
    {3576, 735, 5, 5 },
    {3597, 740, 5, 5 },
    {3617, 745, 5, 5 },
    {3637, 750, 5, 5 },
    {3657, 755, 5, 5 },
    // SP::FMOVRS - 220
    {3678, 760, 5, 5 },
    {3697, 765, 5, 5 },
    {3718, 770, 5, 5 },
    {3738, 775, 5, 5 },
    {3758, 780, 5, 5 },
    {3778, 785, 5, 5 },
    // SP::FMOVS_ICC - 226
    {3799, 790, 4, 5 },
    {3819, 795, 4, 5 },
    {3839, 800, 4, 5 },
    {3860, 805, 4, 5 },
    {3880, 810, 4, 5 },
    {3900, 815, 4, 5 },
    {3921, 820, 4, 5 },
    {3942, 825, 4, 5 },
    {3962, 830, 4, 5 },
    {3983, 835, 4, 5 },
    {4005, 840, 4, 5 },
    {4026, 845, 4, 5 },
    {4047, 850, 4, 5 },
    {4069, 855, 4, 5 },
    {4091, 860, 4, 5 },
    {4112, 865, 4, 5 },
    // SP::FMOVS_XCC - 242
    {4133, 870, 4, 4 },
    {4153, 874, 4, 4 },
    {4173, 878, 4, 4 },
    {4194, 882, 4, 4 },
    {4214, 886, 4, 4 },
    {4234, 890, 4, 4 },
    {4255, 894, 4, 4 },
    {4276, 898, 4, 4 },
    {4296, 902, 4, 4 },
    {4317, 906, 4, 4 },
    {4339, 910, 4, 4 },
    {4360, 914, 4, 4 },
    {4381, 918, 4, 4 },
    {4403, 922, 4, 4 },
    {4425, 926, 4, 4 },
    {4446, 930, 4, 4 },
    // SP::MOVICCri - 258
    {4467, 934, 4, 5 },
    {4485, 939, 4, 5 },
    {4503, 944, 4, 5 },
    {4522, 949, 4, 5 },
    {4540, 954, 4, 5 },
    {4558, 959, 4, 5 },
    {4577, 964, 4, 5 },
    {4596, 969, 4, 5 },
    {4614, 974, 4, 5 },
    {4633, 979, 4, 5 },
    {4653, 984, 4, 5 },
    {4672, 989, 4, 5 },
    {4691, 994, 4, 5 },
    {4711, 999, 4, 5 },
    {4731, 1004, 4, 5 },
    {4750, 1009, 4, 5 },
    // SP::MOVICCrr - 274
    {4467, 1014, 4, 5 },
    {4485, 1019, 4, 5 },
    {4503, 1024, 4, 5 },
    {4522, 1029, 4, 5 },
    {4540, 1034, 4, 5 },
    {4558, 1039, 4, 5 },
    {4577, 1044, 4, 5 },
    {4596, 1049, 4, 5 },
    {4614, 1054, 4, 5 },
    {4633, 1059, 4, 5 },
    {4653, 1064, 4, 5 },
    {4672, 1069, 4, 5 },
    {4691, 1074, 4, 5 },
    {4711, 1079, 4, 5 },
    {4731, 1084, 4, 5 },
    {4750, 1089, 4, 5 },
    // SP::MOVRri - 290
    {4769, 1094, 5, 5 },
    {4786, 1099, 5, 5 },
    {4805, 1104, 5, 5 },
    {4823, 1109, 5, 5 },
    {4841, 1114, 5, 5 },
    {4859, 1119, 5, 5 },
    // SP::MOVRrr - 296
    {4769, 1124, 5, 5 },
    {4786, 1129, 5, 5 },
    {4805, 1134, 5, 5 },
    {4823, 1139, 5, 5 },
    {4841, 1144, 5, 5 },
    {4859, 1149, 5, 5 },
    // SP::MOVXCCri - 302
    {4878, 1154, 4, 4 },
    {4896, 1158, 4, 4 },
    {4914, 1162, 4, 4 },
    {4933, 1166, 4, 4 },
    {4951, 1170, 4, 4 },
    {4969, 1174, 4, 4 },
    {4988, 1178, 4, 4 },
    {5007, 1182, 4, 4 },
    {5025, 1186, 4, 4 },
    {5044, 1190, 4, 4 },
    {5064, 1194, 4, 4 },
    {5083, 1198, 4, 4 },
    {5102, 1202, 4, 4 },
    {5122, 1206, 4, 4 },
    {5142, 1210, 4, 4 },
    {5161, 1214, 4, 4 },
    // SP::MOVXCCrr - 318
    {4878, 1218, 4, 4 },
    {4896, 1222, 4, 4 },
    {4914, 1226, 4, 4 },
    {4933, 1230, 4, 4 },
    {4951, 1234, 4, 4 },
    {4969, 1238, 4, 4 },
    {4988, 1242, 4, 4 },
    {5007, 1246, 4, 4 },
    {5025, 1250, 4, 4 },
    {5044, 1254, 4, 4 },
    {5064, 1258, 4, 4 },
    {5083, 1262, 4, 4 },
    {5102, 1266, 4, 4 },
    {5122, 1270, 4, 4 },
    {5142, 1274, 4, 4 },
    {5161, 1278, 4, 4 },
    // SP::ORCCrr - 334
    {5180, 1282, 3, 3 },
    // SP::ORri - 335
    {5187, 1285, 3, 2 },
    // SP::ORrr - 336
    {5187, 1287, 3, 3 },
    // SP::RESTORErr - 337
    {5198, 1290, 3, 3 },
    // SP::RET - 338
    {5206, 1293, 1, 1 },
    // SP::RETL - 339
    {5210, 1294, 1, 1 },
    // SP::SAVErr - 340
    {5215, 1295, 3, 3 },
    // SP::SUBCCri - 341
    {5220, 1298, 3, 2 },
    // SP::SUBCCrr - 342
    {5220, 1300, 3, 3 },
    // SP::TICCri - 343
    {5231, 1303, 3, 4 },
    {5243, 1307, 3, 4 },
    {5260, 1311, 3, 4 },
    {5272, 1315, 3, 4 },
    {5289, 1319, 3, 4 },
    {5302, 1323, 3, 4 },
    {5320, 1327, 3, 4 },
    {5332, 1331, 3, 4 },
    {5349, 1335, 3, 4 },
    {5361, 1339, 3, 4 },
    {5378, 1343, 3, 4 },
    {5391, 1347, 3, 4 },
    {5409, 1351, 3, 4 },
    {5422, 1355, 3, 4 },
    {5440, 1359, 3, 4 },
    {5452, 1363, 3, 4 },
    {5469, 1367, 3, 4 },
    {5482, 1371, 3, 4 },
    {5500, 1375, 3, 4 },
    {5514, 1379, 3, 4 },
    {5533, 1383, 3, 4 },
    {5546, 1387, 3, 4 },
    {5564, 1391, 3, 4 },
    {5577, 1395, 3, 4 },
    {5595, 1399, 3, 4 },
    {5609, 1403, 3, 4 },
    {5628, 1407, 3, 4 },
    {5642, 1411, 3, 4 },
    {5661, 1415, 3, 4 },
    {5674, 1419, 3, 4 },
    {5692, 1423, 3, 4 },
    {5705, 1427, 3, 4 },
    // SP::TICCrr - 375
    {5231, 1431, 3, 4 },
    {5243, 1435, 3, 4 },
    {5260, 1439, 3, 4 },
    {5272, 1443, 3, 4 },
    {5289, 1447, 3, 4 },
    {5302, 1451, 3, 4 },
    {5320, 1455, 3, 4 },
    {5332, 1459, 3, 4 },
    {5349, 1463, 3, 4 },
    {5361, 1467, 3, 4 },
    {5378, 1471, 3, 4 },
    {5391, 1475, 3, 4 },
    {5409, 1479, 3, 4 },
    {5422, 1483, 3, 4 },
    {5440, 1487, 3, 4 },
    {5452, 1491, 3, 4 },
    {5469, 1495, 3, 4 },
    {5482, 1499, 3, 4 },
    {5500, 1503, 3, 4 },
    {5514, 1507, 3, 4 },
    {5533, 1511, 3, 4 },
    {5546, 1515, 3, 4 },
    {5564, 1519, 3, 4 },
    {5577, 1523, 3, 4 },
    {5595, 1527, 3, 4 },
    {5609, 1531, 3, 4 },
    {5628, 1535, 3, 4 },
    {5642, 1539, 3, 4 },
    {5661, 1543, 3, 4 },
    {5674, 1547, 3, 4 },
    {5692, 1551, 3, 4 },
    {5705, 1555, 3, 4 },
    // SP::TRAPri - 407
    {5723, 1559, 3, 3 },
    {5729, 1562, 3, 3 },
    {5740, 1565, 3, 3 },
    {5746, 1568, 3, 3 },
    {5757, 1571, 3, 3 },
    {5764, 1574, 3, 3 },
    {5776, 1577, 3, 3 },
    {5782, 1580, 3, 3 },
    {5793, 1583, 3, 3 },
    {5799, 1586, 3, 3 },
    {5810, 1589, 3, 3 },
    {5817, 1592, 3, 3 },
    {5829, 1595, 3, 3 },
    {5836, 1598, 3, 3 },
    {5848, 1601, 3, 3 },
    {5854, 1604, 3, 3 },
    {5865, 1607, 3, 3 },
    {5872, 1610, 3, 3 },
    {5884, 1613, 3, 3 },
    {5892, 1616, 3, 3 },
    {5905, 1619, 3, 3 },
    {5912, 1622, 3, 3 },
    {5924, 1625, 3, 3 },
    {5931, 1628, 3, 3 },
    {5943, 1631, 3, 3 },
    {5951, 1634, 3, 3 },
    {5964, 1637, 3, 3 },
    {5972, 1640, 3, 3 },
    {5985, 1643, 3, 3 },
    {5992, 1646, 3, 3 },
    {6004, 1649, 3, 3 },
    {6011, 1652, 3, 3 },
    // SP::TRAPrr - 439
    {5723, 1655, 3, 3 },
    {5729, 1658, 3, 3 },
    {5740, 1661, 3, 3 },
    {5746, 1664, 3, 3 },
    {5757, 1667, 3, 3 },
    {5764, 1670, 3, 3 },
    {5776, 1673, 3, 3 },
    {5782, 1676, 3, 3 },
    {5793, 1679, 3, 3 },
    {5799, 1682, 3, 3 },
    {5810, 1685, 3, 3 },
    {5817, 1688, 3, 3 },
    {5829, 1691, 3, 3 },
    {5836, 1694, 3, 3 },
    {5848, 1697, 3, 3 },
    {5854, 1700, 3, 3 },
    {5865, 1703, 3, 3 },
    {5872, 1706, 3, 3 },
    {5884, 1709, 3, 3 },
    {5892, 1712, 3, 3 },
    {5905, 1715, 3, 3 },
    {5912, 1718, 3, 3 },
    {5924, 1721, 3, 3 },
    {5931, 1724, 3, 3 },
    {5943, 1727, 3, 3 },
    {5951, 1730, 3, 3 },
    {5964, 1733, 3, 3 },
    {5972, 1736, 3, 3 },
    {5985, 1739, 3, 3 },
    {5992, 1742, 3, 3 },
    {6004, 1745, 3, 3 },
    {6011, 1748, 3, 3 },
    // SP::TXCCri - 471
    {6023, 1751, 3, 4 },
    {6035, 1755, 3, 4 },
    {6052, 1759, 3, 4 },
    {6064, 1763, 3, 4 },
    {6081, 1767, 3, 4 },
    {6094, 1771, 3, 4 },
    {6112, 1775, 3, 4 },
    {6124, 1779, 3, 4 },
    {6141, 1783, 3, 4 },
    {6153, 1787, 3, 4 },
    {6170, 1791, 3, 4 },
    {6183, 1795, 3, 4 },
    {6201, 1799, 3, 4 },
    {6214, 1803, 3, 4 },
    {6232, 1807, 3, 4 },
    {6244, 1811, 3, 4 },
    {6261, 1815, 3, 4 },
    {6274, 1819, 3, 4 },
    {6292, 1823, 3, 4 },
    {6306, 1827, 3, 4 },
    {6325, 1831, 3, 4 },
    {6338, 1835, 3, 4 },
    {6356, 1839, 3, 4 },
    {6369, 1843, 3, 4 },
    {6387, 1847, 3, 4 },
    {6401, 1851, 3, 4 },
    {6420, 1855, 3, 4 },
    {6434, 1859, 3, 4 },
    {6453, 1863, 3, 4 },
    {6466, 1867, 3, 4 },
    {6484, 1871, 3, 4 },
    {6497, 1875, 3, 4 },
    // SP::TXCCrr - 503
    {6023, 1879, 3, 4 },
    {6035, 1883, 3, 4 },
    {6052, 1887, 3, 4 },
    {6064, 1891, 3, 4 },
    {6081, 1895, 3, 4 },
    {6094, 1899, 3, 4 },
    {6112, 1903, 3, 4 },
    {6124, 1907, 3, 4 },
    {6141, 1911, 3, 4 },
    {6153, 1915, 3, 4 },
    {6170, 1919, 3, 4 },
    {6183, 1923, 3, 4 },
    {6201, 1927, 3, 4 },
    {6214, 1931, 3, 4 },
    {6232, 1935, 3, 4 },
    {6244, 1939, 3, 4 },
    {6261, 1943, 3, 4 },
    {6274, 1947, 3, 4 },
    {6292, 1951, 3, 4 },
    {6306, 1955, 3, 4 },
    {6325, 1959, 3, 4 },
    {6338, 1963, 3, 4 },
    {6356, 1967, 3, 4 },
    {6369, 1971, 3, 4 },
    {6387, 1975, 3, 4 },
    {6401, 1979, 3, 4 },
    {6420, 1983, 3, 4 },
    {6434, 1987, 3, 4 },
    {6453, 1991, 3, 4 },
    {6466, 1995, 3, 4 },
    {6484, 1999, 3, 4 },
    {6497, 2003, 3, 4 },
    // SP::V9FCMPD - 535
    {6515, 2007, 3, 3 },
    // SP::V9FCMPED - 536
    {6528, 2010, 3, 3 },
    // SP::V9FCMPEQ - 537
    {6542, 2013, 3, 3 },
    // SP::V9FCMPES - 538
    {6556, 2016, 3, 3 },
    // SP::V9FCMPQ - 539
    {6570, 2019, 3, 3 },
    // SP::V9FCMPS - 540
    {6583, 2022, 3, 3 },
    // SP::V9FMOVD_FCC - 541
    {6596, 2025, 5, 6 },
    {6614, 2031, 5, 6 },
    {6632, 2037, 5, 6 },
    {6650, 2043, 5, 6 },
    {6668, 2049, 5, 6 },
    {6687, 2055, 5, 6 },
    {6705, 2061, 5, 6 },
    {6724, 2067, 5, 6 },
    {6743, 2073, 5, 6 },
    {6762, 2079, 5, 6 },
    {6780, 2085, 5, 6 },
    {6799, 2091, 5, 6 },
    {6818, 2097, 5, 6 },
    {6838, 2103, 5, 6 },
    {6857, 2109, 5, 6 },
    {6877, 2115, 5, 6 },
    // SP::V9FMOVQ_FCC - 557
    {6895, 2121, 5, 6 },
    {6913, 2127, 5, 6 },
    {6931, 2133, 5, 6 },
    {6949, 2139, 5, 6 },
    {6967, 2145, 5, 6 },
    {6986, 2151, 5, 6 },
    {7004, 2157, 5, 6 },
    {7023, 2163, 5, 6 },
    {7042, 2169, 5, 6 },
    {7061, 2175, 5, 6 },
    {7079, 2181, 5, 6 },
    {7098, 2187, 5, 6 },
    {7117, 2193, 5, 6 },
    {7137, 2199, 5, 6 },
    {7156, 2205, 5, 6 },
    {7176, 2211, 5, 6 },
    // SP::V9FMOVS_FCC - 573
    {7194, 2217, 5, 6 },
    {7212, 2223, 5, 6 },
    {7230, 2229, 5, 6 },
    {7248, 2235, 5, 6 },
    {7266, 2241, 5, 6 },
    {7285, 2247, 5, 6 },
    {7303, 2253, 5, 6 },
    {7322, 2259, 5, 6 },
    {7341, 2265, 5, 6 },
    {7360, 2271, 5, 6 },
    {7378, 2277, 5, 6 },
    {7397, 2283, 5, 6 },
    {7416, 2289, 5, 6 },
    {7436, 2295, 5, 6 },
    {7455, 2301, 5, 6 },
    {7475, 2307, 5, 6 },
    // SP::V9MOVFCCri - 589
    {7493, 2313, 5, 6 },
    {7509, 2319, 5, 6 },
    {7525, 2325, 5, 6 },
    {7541, 2331, 5, 6 },
    {7557, 2337, 5, 6 },
    {7574, 2343, 5, 6 },
    {7590, 2349, 5, 6 },
    {7607, 2355, 5, 6 },
    {7624, 2361, 5, 6 },
    {7641, 2367, 5, 6 },
    {7657, 2373, 5, 6 },
    {7674, 2379, 5, 6 },
    {7691, 2385, 5, 6 },
    {7709, 2391, 5, 6 },
    {7726, 2397, 5, 6 },
    {7744, 2403, 5, 6 },
    // SP::V9MOVFCCrr - 605
    {7493, 2409, 5, 6 },
    {7509, 2415, 5, 6 },
    {7525, 2421, 5, 6 },
    {7541, 2427, 5, 6 },
    {7557, 2433, 5, 6 },
    {7574, 2439, 5, 6 },
    {7590, 2445, 5, 6 },
    {7607, 2451, 5, 6 },
    {7624, 2457, 5, 6 },
    {7641, 2463, 5, 6 },
    {7657, 2469, 5, 6 },
    {7674, 2475, 5, 6 },
    {7691, 2481, 5, 6 },
    {7709, 2487, 5, 6 },
    {7726, 2493, 5, 6 },
    {7744, 2499, 5, 6 },
  };

  static const AliasPatternCond Conds[] = {
    // (BCOND brtarget:$imm, 8) - 0
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (BCOND brtarget:$imm, 0) - 2
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (BCOND brtarget:$imm, 9) - 4
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (BCOND brtarget:$imm, 1) - 6
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (BCOND brtarget:$imm, 10) - 8
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (BCOND brtarget:$imm, 2) - 10
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (BCOND brtarget:$imm, 11) - 12
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (BCOND brtarget:$imm, 3) - 14
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (BCOND brtarget:$imm, 12) - 16
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (BCOND brtarget:$imm, 4) - 18
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (BCOND brtarget:$imm, 13) - 20
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (BCOND brtarget:$imm, 5) - 22
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (BCOND brtarget:$imm, 14) - 24
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (BCOND brtarget:$imm, 6) - 26
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (BCOND brtarget:$imm, 15) - 28
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (BCOND brtarget:$imm, 7) - 30
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (BCONDA brtarget:$imm, 8) - 32
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (BCONDA brtarget:$imm, 0) - 34
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (BCONDA brtarget:$imm, 9) - 36
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (BCONDA brtarget:$imm, 1) - 38
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (BCONDA brtarget:$imm, 10) - 40
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (BCONDA brtarget:$imm, 2) - 42
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (BCONDA brtarget:$imm, 11) - 44
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (BCONDA brtarget:$imm, 3) - 46
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (BCONDA brtarget:$imm, 12) - 48
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (BCONDA brtarget:$imm, 4) - 50
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (BCONDA brtarget:$imm, 13) - 52
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (BCONDA brtarget:$imm, 5) - 54
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (BCONDA brtarget:$imm, 14) - 56
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (BCONDA brtarget:$imm, 6) - 58
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (BCONDA brtarget:$imm, 15) - 60
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (BCONDA brtarget:$imm, 7) - 62
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc) - 64
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc) - 68
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc) - 72
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc) - 76
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc) - 80
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc) - 84
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc) - 88
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc) - 92
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc) - 96
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc) - 100
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc) - 104
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc) - 108
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc) - 112
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc) - 116
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc) - 120
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc) - 124
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc) - 128
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc) - 132
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc) - 136
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc) - 140
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc) - 144
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc) - 148
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc) - 152
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc) - 156
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc) - 160
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc) - 164
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc) - 168
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc) - 172
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc) - 176
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc) - 180
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc) - 184
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc) - 188
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 8) - 192
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 0) - 195
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 9) - 198
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 1) - 201
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 10) - 204
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 2) - 207
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 11) - 210
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 3) - 213
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 12) - 216
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 4) - 219
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 13) - 222
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 5) - 225
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 14) - 228
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 6) - 231
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 15) - 234
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCANT brtarget:$imm, 7) - 237
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 8) - 240
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 0) - 243
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 9) - 246
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 1) - 249
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 10) - 252
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 2) - 255
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 11) - 258
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 3) - 261
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 12) - 264
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 4) - 267
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 13) - 270
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 5) - 273
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 14) - 276
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 6) - 279
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 15) - 282
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPICCNT brtarget:$imm, 7) - 285
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (BPRANT bprtarget16:$imm, 1, I64Regs:$rs1) - 288
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRANT bprtarget16:$imm, 2, I64Regs:$rs1) - 291
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRANT bprtarget16:$imm, 3, I64Regs:$rs1) - 294
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRANT bprtarget16:$imm, 5, I64Regs:$rs1) - 297
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRANT bprtarget16:$imm, 6, I64Regs:$rs1) - 300
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRANT bprtarget16:$imm, 7, I64Regs:$rs1) - 303
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRNT bprtarget16:$imm, 1, I64Regs:$rs1) - 306
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRNT bprtarget16:$imm, 2, I64Regs:$rs1) - 309
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRNT bprtarget16:$imm, 3, I64Regs:$rs1) - 312
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRNT bprtarget16:$imm, 5, I64Regs:$rs1) - 315
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRNT bprtarget16:$imm, 6, I64Regs:$rs1) - 318
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPRNT bprtarget16:$imm, 7, I64Regs:$rs1) - 321
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    // (BPXCCANT brtarget:$imm, 8) - 324
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (BPXCCANT brtarget:$imm, 0) - 326
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (BPXCCANT brtarget:$imm, 9) - 328
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (BPXCCANT brtarget:$imm, 1) - 330
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (BPXCCANT brtarget:$imm, 10) - 332
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (BPXCCANT brtarget:$imm, 2) - 334
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (BPXCCANT brtarget:$imm, 11) - 336
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (BPXCCANT brtarget:$imm, 3) - 338
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (BPXCCANT brtarget:$imm, 12) - 340
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (BPXCCANT brtarget:$imm, 4) - 342
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (BPXCCANT brtarget:$imm, 13) - 344
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (BPXCCANT brtarget:$imm, 5) - 346
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (BPXCCANT brtarget:$imm, 14) - 348
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (BPXCCANT brtarget:$imm, 6) - 350
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (BPXCCANT brtarget:$imm, 15) - 352
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (BPXCCANT brtarget:$imm, 7) - 354
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (BPXCCNT brtarget:$imm, 8) - 356
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (BPXCCNT brtarget:$imm, 0) - 358
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (BPXCCNT brtarget:$imm, 9) - 360
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (BPXCCNT brtarget:$imm, 1) - 362
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (BPXCCNT brtarget:$imm, 10) - 364
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (BPXCCNT brtarget:$imm, 2) - 366
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (BPXCCNT brtarget:$imm, 11) - 368
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (BPXCCNT brtarget:$imm, 3) - 370
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (BPXCCNT brtarget:$imm, 12) - 372
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (BPXCCNT brtarget:$imm, 4) - 374
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (BPXCCNT brtarget:$imm, 13) - 376
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (BPXCCNT brtarget:$imm, 5) - 378
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (BPXCCNT brtarget:$imm, 14) - 380
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (BPXCCNT brtarget:$imm, 6) - 382
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (BPXCCNT brtarget:$imm, 15) - 384
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (BPXCCNT brtarget:$imm, 7) - 386
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 128) - 388
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(128)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (CASArr IntRegs:$rd, IntRegs:$rs1, IntRegs:$rs2, 136) - 394
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(136)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 128) - 400
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(128)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (CASXArr I64Regs:$rd, I64Regs:$rs1, I64Regs:$rs2, 136) - 406
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(136)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8) - 412
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0) - 417
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9) - 422
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1) - 427
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10) - 432
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2) - 437
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11) - 442
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3) - 447
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12) - 452
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4) - 457
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13) - 462
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5) - 467
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14) - 472
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6) - 477
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15) - 482
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7) - 487
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8) - 492
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0) - 496
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9) - 500
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1) - 504
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10) - 508
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2) - 512
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11) - 516
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3) - 520
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12) - 524
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4) - 528
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13) - 532
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5) - 536
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14) - 540
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6) - 544
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15) - 548
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7) - 552
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8) - 556
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0) - 561
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9) - 566
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1) - 571
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10) - 576
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2) - 581
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11) - 586
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3) - 591
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12) - 596
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4) - 601
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13) - 606
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5) - 611
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14) - 616
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6) - 621
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15) - 626
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7) - 631
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8) - 636
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0) - 640
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9) - 644
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1) - 648
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10) - 652
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2) - 656
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11) - 660
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3) - 664
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12) - 668
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4) - 672
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13) - 676
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5) - 680
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14) - 684
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6) - 688
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15) - 692
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7) - 696
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 1) - 700
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 2) - 705
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 3) - 710
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 5) - 715
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 6) - 720
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (FMOVRD DFPRegs:$rd, I64Regs:$rs1, DFPRegs:$rs2, 7) - 725
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 1) - 730
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 2) - 735
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 3) - 740
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 5) - 745
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 6) - 750
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (FMOVRQ QFPRegs:$rd, I64Regs:$rs1, QFPRegs:$rs2, 7) - 755
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 1) - 760
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 2) - 765
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 3) - 770
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 5) - 775
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 6) - 780
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (FMOVRS FPRegs:$rd, I64Regs:$rs1, FPRegs:$rs2, 7) - 785
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8) - 790
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0) - 795
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9) - 800
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1) - 805
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10) - 810
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2) - 815
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11) - 820
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3) - 825
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12) - 830
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4) - 835
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13) - 840
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5) - 845
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14) - 850
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6) - 855
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15) - 860
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7) - 865
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8) - 870
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0) - 874
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9) - 878
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1) - 882
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10) - 886
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2) - 890
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11) - 894
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3) - 898
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12) - 902
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4) - 906
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13) - 910
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5) - 914
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14) - 918
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6) - 922
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15) - 926
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7) - 930
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8) - 934
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0) - 939
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9) - 944
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1) - 949
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10) - 954
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2) - 959
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11) - 964
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3) - 969
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12) - 974
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4) - 979
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13) - 984
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5) - 989
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14) - 994
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6) - 999
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15) - 1004
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7) - 1009
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1014
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1019
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1024
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1029
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1034
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1039
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1044
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1049
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1054
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1059
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1064
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1069
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1074
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1079
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1084
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1089
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 1) - 1094
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 2) - 1099
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 3) - 1104
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 5) - 1109
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 6) - 1114
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (MOVRri IntRegs:$rd, I64Regs:$rs1, i32imm:$simm10, 7) - 1119
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 1) - 1124
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 2) - 1129
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 3) - 1134
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 5) - 1139
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 6) - 1144
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (MOVRrr IntRegs:$rd, I64Regs:$rs1, IntRegs:$rs2, 7) - 1149
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::I64RegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8) - 1154
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0) - 1158
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9) - 1162
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1) - 1166
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10) - 1170
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2) - 1174
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11) - 1178
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3) - 1182
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12) - 1186
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4) - 1190
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13) - 1194
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5) - 1198
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14) - 1202
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6) - 1206
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15) - 1210
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7) - 1214
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8) - 1218
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0) - 1222
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9) - 1226
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1) - 1230
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10) - 1234
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2) - 1238
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11) - 1242
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3) - 1246
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12) - 1250
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4) - 1254
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13) - 1258
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5) - 1262
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14) - 1266
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6) - 1270
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15) - 1274
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7) - 1278
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (ORCCrr G0, IntRegs:$rs2, G0) - 1282
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Reg, Sparc::G0},
    // (ORri IntRegs:$rd, G0, simm13Op:$simm13) - 1285
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Reg, Sparc::G0},
    // (ORrr IntRegs:$rd, G0, IntRegs:$rs2) - 1287
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    // (RESTORErr G0, G0, G0) - 1290
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Reg, Sparc::G0},
    // (RET 8) - 1293
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (RETL 8) - 1294
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (SAVErr G0, G0, G0) - 1295
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Reg, Sparc::G0},
    // (SUBCCri G0, IntRegs:$rs1, simm13Op:$imm) - 1298
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    // (SUBCCrr G0, IntRegs:$rs1, IntRegs:$rs2) - 1300
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    // (TICCri G0, i32imm:$imm, 8) - 1303
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 8) - 1307
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 0) - 1311
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 0) - 1315
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 9) - 1319
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 9) - 1323
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 1) - 1327
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 1) - 1331
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 10) - 1335
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 10) - 1339
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 2) - 1343
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 2) - 1347
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 11) - 1351
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 11) - 1355
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 3) - 1359
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 3) - 1363
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 12) - 1367
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 12) - 1371
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 4) - 1375
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 4) - 1379
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 13) - 1383
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 13) - 1387
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 5) - 1391
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 5) - 1395
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 14) - 1399
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 14) - 1403
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 6) - 1407
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 6) - 1411
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 15) - 1415
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 15) - 1419
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri G0, i32imm:$imm, 7) - 1423
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCri IntRegs:$rs1, i32imm:$imm, 7) - 1427
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 8) - 1431
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1435
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 0) - 1439
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1443
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 9) - 1447
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1451
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 1) - 1455
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1459
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 10) - 1463
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1467
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 2) - 1471
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1475
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 11) - 1479
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1483
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 3) - 1487
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1491
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 12) - 1495
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1499
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 4) - 1503
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1507
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 13) - 1511
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1515
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 5) - 1519
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1523
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 14) - 1527
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1531
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 6) - 1535
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1539
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 15) - 1543
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1547
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr G0, IntRegs:$rs2, 7) - 1551
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TICCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1555
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TRAPri G0, i32imm:$imm, 8) - 1559
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 8) - 1562
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (TRAPri G0, i32imm:$imm, 0) - 1565
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 0) - 1568
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (TRAPri G0, i32imm:$imm, 9) - 1571
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 9) - 1574
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (TRAPri G0, i32imm:$imm, 1) - 1577
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 1) - 1580
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (TRAPri G0, i32imm:$imm, 10) - 1583
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 10) - 1586
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (TRAPri G0, i32imm:$imm, 2) - 1589
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 2) - 1592
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (TRAPri G0, i32imm:$imm, 11) - 1595
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 11) - 1598
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (TRAPri G0, i32imm:$imm, 3) - 1601
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 3) - 1604
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (TRAPri G0, i32imm:$imm, 12) - 1607
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 12) - 1610
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (TRAPri G0, i32imm:$imm, 4) - 1613
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 4) - 1616
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (TRAPri G0, i32imm:$imm, 13) - 1619
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 13) - 1622
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (TRAPri G0, i32imm:$imm, 5) - 1625
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 5) - 1628
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (TRAPri G0, i32imm:$imm, 14) - 1631
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 14) - 1634
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (TRAPri G0, i32imm:$imm, 6) - 1637
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 6) - 1640
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (TRAPri G0, i32imm:$imm, 15) - 1643
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 15) - 1646
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (TRAPri G0, i32imm:$imm, 7) - 1649
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (TRAPri IntRegs:$rs1, i32imm:$imm, 7) - 1652
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (TRAPrr G0, IntRegs:$rs1, 8) - 1655
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1658
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    // (TRAPrr G0, IntRegs:$rs1, 0) - 1661
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1664
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    // (TRAPrr G0, IntRegs:$rs1, 9) - 1667
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1670
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    // (TRAPrr G0, IntRegs:$rs1, 1) - 1673
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1676
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    // (TRAPrr G0, IntRegs:$rs1, 10) - 1679
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1682
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    // (TRAPrr G0, IntRegs:$rs1, 2) - 1685
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1688
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    // (TRAPrr G0, IntRegs:$rs1, 11) - 1691
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1694
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    // (TRAPrr G0, IntRegs:$rs1, 3) - 1697
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1700
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    // (TRAPrr G0, IntRegs:$rs1, 12) - 1703
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1706
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    // (TRAPrr G0, IntRegs:$rs1, 4) - 1709
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1712
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    // (TRAPrr G0, IntRegs:$rs1, 13) - 1715
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1718
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    // (TRAPrr G0, IntRegs:$rs1, 5) - 1721
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1724
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    // (TRAPrr G0, IntRegs:$rs1, 14) - 1727
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1730
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    // (TRAPrr G0, IntRegs:$rs1, 6) - 1733
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1736
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    // (TRAPrr G0, IntRegs:$rs1, 15) - 1739
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1742
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    // (TRAPrr G0, IntRegs:$rs1, 7) - 1745
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (TRAPrr IntRegs:$rs1, IntRegs:$rs2, 7) - 1748
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    // (TXCCri G0, i32imm:$imm, 8) - 1751
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 8) - 1755
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 0) - 1759
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 0) - 1763
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 9) - 1767
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 9) - 1771
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 1) - 1775
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 1) - 1779
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 10) - 1783
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 10) - 1787
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 2) - 1791
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 2) - 1795
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 11) - 1799
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 11) - 1803
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 3) - 1807
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 3) - 1811
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 12) - 1815
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 12) - 1819
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 4) - 1823
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 4) - 1827
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 13) - 1831
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 13) - 1835
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 5) - 1839
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 5) - 1843
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 14) - 1847
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 14) - 1851
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 6) - 1855
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 6) - 1859
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 15) - 1863
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 15) - 1867
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri G0, i32imm:$imm, 7) - 1871
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCri IntRegs:$rs1, i32imm:$imm, 7) - 1875
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 8) - 1879
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8) - 1883
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 0) - 1887
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0) - 1891
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 9) - 1895
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9) - 1899
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 1) - 1903
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1) - 1907
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 10) - 1911
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10) - 1915
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 2) - 1919
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2) - 1923
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 11) - 1927
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11) - 1931
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 3) - 1935
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3) - 1939
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 12) - 1943
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12) - 1947
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 4) - 1951
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4) - 1955
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 13) - 1959
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13) - 1963
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 5) - 1967
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5) - 1971
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 14) - 1975
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14) - 1979
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 6) - 1983
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6) - 1987
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 15) - 1991
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15) - 1995
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr G0, IntRegs:$rs2, 7) - 1999
    {AliasPatternCond::K_Reg, Sparc::G0},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7) - 2003
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2007
    {AliasPatternCond::K_Reg, Sparc::FCC0},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2) - 2010
    {AliasPatternCond::K_Reg, Sparc::FCC0},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2013
    {AliasPatternCond::K_Reg, Sparc::FCC0},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2016
    {AliasPatternCond::K_Reg, Sparc::FCC0},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2) - 2019
    {AliasPatternCond::K_Reg, Sparc::FCC0},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2) - 2022
    {AliasPatternCond::K_Reg, Sparc::FCC0},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8) - 2025
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0) - 2031
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7) - 2037
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6) - 2043
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5) - 2049
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4) - 2055
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3) - 2061
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2) - 2067
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1) - 2073
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9) - 2079
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10) - 2085
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11) - 2091
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12) - 2097
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13) - 2103
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14) - 2109
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15) - 2115
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::DFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8) - 2121
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0) - 2127
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7) - 2133
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6) - 2139
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5) - 2145
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4) - 2151
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3) - 2157
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2) - 2163
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1) - 2169
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9) - 2175
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10) - 2181
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11) - 2187
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12) - 2193
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13) - 2199
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14) - 2205
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15) - 2211
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::QFPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8) - 2217
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0) - 2223
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7) - 2229
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6) - 2235
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5) - 2241
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4) - 2247
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3) - 2253
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2) - 2259
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1) - 2265
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9) - 2271
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10) - 2277
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11) - 2283
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12) - 2289
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13) - 2295
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14) - 2301
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15) - 2307
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FPRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8) - 2313
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0) - 2319
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7) - 2325
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6) - 2331
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5) - 2337
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4) - 2343
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3) - 2349
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2) - 2355
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1) - 2361
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9) - 2367
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10) - 2373
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11) - 2379
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12) - 2385
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13) - 2391
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14) - 2397
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15) - 2403
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8) - 2409
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(8)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0) - 2415
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(0)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7) - 2421
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(7)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6) - 2427
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(6)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5) - 2433
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(5)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4) - 2439
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(4)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3) - 2445
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(3)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2) - 2451
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(2)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1) - 2457
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(1)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9) - 2463
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(9)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10) - 2469
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(10)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11) - 2475
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(11)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12) - 2481
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(12)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13) - 2487
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(13)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14) - 2493
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(14)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
    // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15) - 2499
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::FCCRegsRegClassID},
    {AliasPatternCond::K_RegClass, Sparc::IntRegsRegClassID},
    {AliasPatternCond::K_Ignore, 0},
    {AliasPatternCond::K_Imm, uint32_t(15)},
    {AliasPatternCond::K_Feature, Sparc::FeatureV9},
  };

  static const char AsmStrings[] =
    /* 0 */ "ba $\x01\0"
    /* 6 */ "bn $\x01\0"
    /* 12 */ "bne $\x01\0"
    /* 19 */ "be $\x01\0"
    /* 25 */ "bg $\x01\0"
    /* 31 */ "ble $\x01\0"
    /* 38 */ "bge $\x01\0"
    /* 45 */ "bl $\x01\0"
    /* 51 */ "bgu $\x01\0"
    /* 58 */ "bleu $\x01\0"
    /* 66 */ "bcc $\x01\0"
    /* 73 */ "bcs $\x01\0"
    /* 80 */ "bpos $\x01\0"
    /* 88 */ "bneg $\x01\0"
    /* 96 */ "bvc $\x01\0"
    /* 103 */ "bvs $\x01\0"
    /* 110 */ "ba,a $\x01\0"
    /* 118 */ "bn,a $\x01\0"
    /* 126 */ "bne,a $\x01\0"
    /* 135 */ "be,a $\x01\0"
    /* 143 */ "bg,a $\x01\0"
    /* 151 */ "ble,a $\x01\0"
    /* 160 */ "bge,a $\x01\0"
    /* 169 */ "bl,a $\x01\0"
    /* 177 */ "bgu,a $\x01\0"
    /* 186 */ "bleu,a $\x01\0"
    /* 196 */ "bcc,a $\x01\0"
    /* 205 */ "bcs,a $\x01\0"
    /* 214 */ "bpos,a $\x01\0"
    /* 224 */ "bneg,a $\x01\0"
    /* 234 */ "bvc,a $\x01\0"
    /* 243 */ "bvs,a $\x01\0"
    /* 252 */ "fba,a,pn $\x03, $\x01\0"
    /* 268 */ "fbn,a,pn $\x03, $\x01\0"
    /* 284 */ "fbu,a,pn $\x03, $\x01\0"
    /* 300 */ "fbg,a,pn $\x03, $\x01\0"
    /* 316 */ "fbug,a,pn $\x03, $\x01\0"
    /* 333 */ "fbl,a,pn $\x03, $\x01\0"
    /* 349 */ "fbul,a,pn $\x03, $\x01\0"
    /* 366 */ "fblg,a,pn $\x03, $\x01\0"
    /* 383 */ "fbne,a,pn $\x03, $\x01\0"
    /* 400 */ "fbe,a,pn $\x03, $\x01\0"
    /* 416 */ "fbue,a,pn $\x03, $\x01\0"
    /* 433 */ "fbge,a,pn $\x03, $\x01\0"
    /* 450 */ "fbuge,a,pn $\x03, $\x01\0"
    /* 468 */ "fble,a,pn $\x03, $\x01\0"
    /* 485 */ "fbule,a,pn $\x03, $\x01\0"
    /* 503 */ "fbo,a,pn $\x03, $\x01\0"
    /* 519 */ "fba,pn $\x03, $\x01\0"
    /* 533 */ "fbn,pn $\x03, $\x01\0"
    /* 547 */ "fbu,pn $\x03, $\x01\0"
    /* 561 */ "fbg,pn $\x03, $\x01\0"
    /* 575 */ "fbug,pn $\x03, $\x01\0"
    /* 590 */ "fbl,pn $\x03, $\x01\0"
    /* 604 */ "fbul,pn $\x03, $\x01\0"
    /* 619 */ "fblg,pn $\x03, $\x01\0"
    /* 634 */ "fbne,pn $\x03, $\x01\0"
    /* 649 */ "fbe,pn $\x03, $\x01\0"
    /* 663 */ "fbue,pn $\x03, $\x01\0"
    /* 678 */ "fbge,pn $\x03, $\x01\0"
    /* 693 */ "fbuge,pn $\x03, $\x01\0"
    /* 709 */ "fble,pn $\x03, $\x01\0"
    /* 724 */ "fbule,pn $\x03, $\x01\0"
    /* 740 */ "fbo,pn $\x03, $\x01\0"
    /* 754 */ "ba,a,pn %icc, $\x01\0"
    /* 771 */ "bn,a,pn %icc, $\x01\0"
    /* 788 */ "bne,a,pn %icc, $\x01\0"
    /* 806 */ "be,a,pn %icc, $\x01\0"
    /* 823 */ "bg,a,pn %icc, $\x01\0"
    /* 840 */ "ble,a,pn %icc, $\x01\0"
    /* 858 */ "bge,a,pn %icc, $\x01\0"
    /* 876 */ "bl,a,pn %icc, $\x01\0"
    /* 893 */ "bgu,a,pn %icc, $\x01\0"
    /* 911 */ "bleu,a,pn %icc, $\x01\0"
    /* 930 */ "bcc,a,pn %icc, $\x01\0"
    /* 948 */ "bcs,a,pn %icc, $\x01\0"
    /* 966 */ "bpos,a,pn %icc, $\x01\0"
    /* 985 */ "bneg,a,pn %icc, $\x01\0"
    /* 1004 */ "bvc,a,pn %icc, $\x01\0"
    /* 1022 */ "bvs,a,pn %icc, $\x01\0"
    /* 1040 */ "ba,pn %icc, $\x01\0"
    /* 1055 */ "bn,pn %icc, $\x01\0"
    /* 1070 */ "bne,pn %icc, $\x01\0"
    /* 1086 */ "be,pn %icc, $\x01\0"
    /* 1101 */ "bg,pn %icc, $\x01\0"
    /* 1116 */ "ble,pn %icc, $\x01\0"
    /* 1132 */ "bge,pn %icc, $\x01\0"
    /* 1148 */ "bl,pn %icc, $\x01\0"
    /* 1163 */ "bgu,pn %icc, $\x01\0"
    /* 1179 */ "bleu,pn %icc, $\x01\0"
    /* 1196 */ "bcc,pn %icc, $\x01\0"
    /* 1212 */ "bcs,pn %icc, $\x01\0"
    /* 1228 */ "bpos,pn %icc, $\x01\0"
    /* 1245 */ "bneg,pn %icc, $\x01\0"
    /* 1262 */ "bvc,pn %icc, $\x01\0"
    /* 1278 */ "bvs,pn %icc, $\x01\0"
    /* 1294 */ "brz,a,pn $\x03, $\x01\0"
    /* 1310 */ "brlez,a,pn $\x03, $\x01\0"
    /* 1328 */ "brlz,a,pn $\x03, $\x01\0"
    /* 1345 */ "brnz,a,pn $\x03, $\x01\0"
    /* 1362 */ "brgz,a,pn $\x03, $\x01\0"
    /* 1379 */ "brgez,a,pn $\x03, $\x01\0"
    /* 1397 */ "brz,pn $\x03, $\x01\0"
    /* 1411 */ "brlez,pn $\x03, $\x01\0"
    /* 1427 */ "brlz,pn $\x03, $\x01\0"
    /* 1442 */ "brnz,pn $\x03, $\x01\0"
    /* 1457 */ "brgz,pn $\x03, $\x01\0"
    /* 1472 */ "brgez,pn $\x03, $\x01\0"
    /* 1488 */ "ba,a,pn %xcc, $\x01\0"
    /* 1505 */ "bn,a,pn %xcc, $\x01\0"
    /* 1522 */ "bne,a,pn %xcc, $\x01\0"
    /* 1540 */ "be,a,pn %xcc, $\x01\0"
    /* 1557 */ "bg,a,pn %xcc, $\x01\0"
    /* 1574 */ "ble,a,pn %xcc, $\x01\0"
    /* 1592 */ "bge,a,pn %xcc, $\x01\0"
    /* 1610 */ "bl,a,pn %xcc, $\x01\0"
    /* 1627 */ "bgu,a,pn %xcc, $\x01\0"
    /* 1645 */ "bleu,a,pn %xcc, $\x01\0"
    /* 1664 */ "bcc,a,pn %xcc, $\x01\0"
    /* 1682 */ "bcs,a,pn %xcc, $\x01\0"
    /* 1700 */ "bpos,a,pn %xcc, $\x01\0"
    /* 1719 */ "bneg,a,pn %xcc, $\x01\0"
    /* 1738 */ "bvc,a,pn %xcc, $\x01\0"
    /* 1756 */ "bvs,a,pn %xcc, $\x01\0"
    /* 1774 */ "ba,pn %xcc, $\x01\0"
    /* 1789 */ "bn,pn %xcc, $\x01\0"
    /* 1804 */ "bne,pn %xcc, $\x01\0"
    /* 1820 */ "be,pn %xcc, $\x01\0"
    /* 1835 */ "bg,pn %xcc, $\x01\0"
    /* 1850 */ "ble,pn %xcc, $\x01\0"
    /* 1866 */ "bge,pn %xcc, $\x01\0"
    /* 1882 */ "bl,pn %xcc, $\x01\0"
    /* 1897 */ "bgu,pn %xcc, $\x01\0"
    /* 1913 */ "bleu,pn %xcc, $\x01\0"
    /* 1930 */ "bcc,pn %xcc, $\x01\0"
    /* 1946 */ "bcs,pn %xcc, $\x01\0"
    /* 1962 */ "bpos,pn %xcc, $\x01\0"
    /* 1979 */ "bneg,pn %xcc, $\x01\0"
    /* 1996 */ "bvc,pn %xcc, $\x01\0"
    /* 2012 */ "bvs,pn %xcc, $\x01\0"
    /* 2028 */ "cas [$\x02], $\x03, $\x01\0"
    /* 2045 */ "casl [$\x02], $\x03, $\x01\0"
    /* 2063 */ "casx [$\x02], $\x03, $\x01\0"
    /* 2081 */ "casxl [$\x02], $\x03, $\x01\0"
    /* 2100 */ "fmovda %icc, $\x02, $\x01\0"
    /* 2120 */ "fmovdn %icc, $\x02, $\x01\0"
    /* 2140 */ "fmovdne %icc, $\x02, $\x01\0"
    /* 2161 */ "fmovde %icc, $\x02, $\x01\0"
    /* 2181 */ "fmovdg %icc, $\x02, $\x01\0"
    /* 2201 */ "fmovdle %icc, $\x02, $\x01\0"
    /* 2222 */ "fmovdge %icc, $\x02, $\x01\0"
    /* 2243 */ "fmovdl %icc, $\x02, $\x01\0"
    /* 2263 */ "fmovdgu %icc, $\x02, $\x01\0"
    /* 2284 */ "fmovdleu %icc, $\x02, $\x01\0"
    /* 2306 */ "fmovdcc %icc, $\x02, $\x01\0"
    /* 2327 */ "fmovdcs %icc, $\x02, $\x01\0"
    /* 2348 */ "fmovdpos %icc, $\x02, $\x01\0"
    /* 2370 */ "fmovdneg %icc, $\x02, $\x01\0"
    /* 2392 */ "fmovdvc %icc, $\x02, $\x01\0"
    /* 2413 */ "fmovdvs %icc, $\x02, $\x01\0"
    /* 2434 */ "fmovda %xcc, $\x02, $\x01\0"
    /* 2454 */ "fmovdn %xcc, $\x02, $\x01\0"
    /* 2474 */ "fmovdne %xcc, $\x02, $\x01\0"
    /* 2495 */ "fmovde %xcc, $\x02, $\x01\0"
    /* 2515 */ "fmovdg %xcc, $\x02, $\x01\0"
    /* 2535 */ "fmovdle %xcc, $\x02, $\x01\0"
    /* 2556 */ "fmovdge %xcc, $\x02, $\x01\0"
    /* 2577 */ "fmovdl %xcc, $\x02, $\x01\0"
    /* 2597 */ "fmovdgu %xcc, $\x02, $\x01\0"
    /* 2618 */ "fmovdleu %xcc, $\x02, $\x01\0"
    /* 2640 */ "fmovdcc %xcc, $\x02, $\x01\0"
    /* 2661 */ "fmovdcs %xcc, $\x02, $\x01\0"
    /* 2682 */ "fmovdpos %xcc, $\x02, $\x01\0"
    /* 2704 */ "fmovdneg %xcc, $\x02, $\x01\0"
    /* 2726 */ "fmovdvc %xcc, $\x02, $\x01\0"
    /* 2747 */ "fmovdvs %xcc, $\x02, $\x01\0"
    /* 2768 */ "fmovqa %icc, $\x02, $\x01\0"
    /* 2788 */ "fmovqn %icc, $\x02, $\x01\0"
    /* 2808 */ "fmovqne %icc, $\x02, $\x01\0"
    /* 2829 */ "fmovqe %icc, $\x02, $\x01\0"
    /* 2849 */ "fmovqg %icc, $\x02, $\x01\0"
    /* 2869 */ "fmovqle %icc, $\x02, $\x01\0"
    /* 2890 */ "fmovqge %icc, $\x02, $\x01\0"
    /* 2911 */ "fmovql %icc, $\x02, $\x01\0"
    /* 2931 */ "fmovqgu %icc, $\x02, $\x01\0"
    /* 2952 */ "fmovqleu %icc, $\x02, $\x01\0"
    /* 2974 */ "fmovqcc %icc, $\x02, $\x01\0"
    /* 2995 */ "fmovqcs %icc, $\x02, $\x01\0"
    /* 3016 */ "fmovqpos %icc, $\x02, $\x01\0"
    /* 3038 */ "fmovqneg %icc, $\x02, $\x01\0"
    /* 3060 */ "fmovqvc %icc, $\x02, $\x01\0"
    /* 3081 */ "fmovqvs %icc, $\x02, $\x01\0"
    /* 3102 */ "fmovqa %xcc, $\x02, $\x01\0"
    /* 3122 */ "fmovqn %xcc, $\x02, $\x01\0"
    /* 3142 */ "fmovqne %xcc, $\x02, $\x01\0"
    /* 3163 */ "fmovqe %xcc, $\x02, $\x01\0"
    /* 3183 */ "fmovqg %xcc, $\x02, $\x01\0"
    /* 3203 */ "fmovqle %xcc, $\x02, $\x01\0"
    /* 3224 */ "fmovqge %xcc, $\x02, $\x01\0"
    /* 3245 */ "fmovql %xcc, $\x02, $\x01\0"
    /* 3265 */ "fmovqgu %xcc, $\x02, $\x01\0"
    /* 3286 */ "fmovqleu %xcc, $\x02, $\x01\0"
    /* 3308 */ "fmovqcc %xcc, $\x02, $\x01\0"
    /* 3329 */ "fmovqcs %xcc, $\x02, $\x01\0"
    /* 3350 */ "fmovqpos %xcc, $\x02, $\x01\0"
    /* 3372 */ "fmovqneg %xcc, $\x02, $\x01\0"
    /* 3394 */ "fmovqvc %xcc, $\x02, $\x01\0"
    /* 3415 */ "fmovqvs %xcc, $\x02, $\x01\0"
    /* 3436 */ "fmovrdz $\x02, $\x03, $\x01\0"
    /* 3455 */ "fmovrdlez $\x02, $\x03, $\x01\0"
    /* 3476 */ "fmovrdlz $\x02, $\x03, $\x01\0"
    /* 3496 */ "fmovrdnz $\x02, $\x03, $\x01\0"
    /* 3516 */ "fmovrdgz $\x02, $\x03, $\x01\0"
    /* 3536 */ "fmovrdgez $\x02, $\x03, $\x01\0"
    /* 3557 */ "fmovrqz $\x02, $\x03, $\x01\0"
    /* 3576 */ "fmovrqlez $\x02, $\x03, $\x01\0"
    /* 3597 */ "fmovrqlz $\x02, $\x03, $\x01\0"
    /* 3617 */ "fmovrqnz $\x02, $\x03, $\x01\0"
    /* 3637 */ "fmovrqgz $\x02, $\x03, $\x01\0"
    /* 3657 */ "fmovrqgez $\x02, $\x03, $\x01\0"
    /* 3678 */ "fmovrsz $\x02, $\x03, $\x01\0"
    /* 3697 */ "fmovrslez $\x02, $\x03, $\x01\0"
    /* 3718 */ "fmovrslz $\x02, $\x03, $\x01\0"
    /* 3738 */ "fmovrsnz $\x02, $\x03, $\x01\0"
    /* 3758 */ "fmovrsgz $\x02, $\x03, $\x01\0"
    /* 3778 */ "fmovrsgez $\x02, $\x03, $\x01\0"
    /* 3799 */ "fmovsa %icc, $\x02, $\x01\0"
    /* 3819 */ "fmovsn %icc, $\x02, $\x01\0"
    /* 3839 */ "fmovsne %icc, $\x02, $\x01\0"
    /* 3860 */ "fmovse %icc, $\x02, $\x01\0"
    /* 3880 */ "fmovsg %icc, $\x02, $\x01\0"
    /* 3900 */ "fmovsle %icc, $\x02, $\x01\0"
    /* 3921 */ "fmovsge %icc, $\x02, $\x01\0"
    /* 3942 */ "fmovsl %icc, $\x02, $\x01\0"
    /* 3962 */ "fmovsgu %icc, $\x02, $\x01\0"
    /* 3983 */ "fmovsleu %icc, $\x02, $\x01\0"
    /* 4005 */ "fmovscc %icc, $\x02, $\x01\0"
    /* 4026 */ "fmovscs %icc, $\x02, $\x01\0"
    /* 4047 */ "fmovspos %icc, $\x02, $\x01\0"
    /* 4069 */ "fmovsneg %icc, $\x02, $\x01\0"
    /* 4091 */ "fmovsvc %icc, $\x02, $\x01\0"
    /* 4112 */ "fmovsvs %icc, $\x02, $\x01\0"
    /* 4133 */ "fmovsa %xcc, $\x02, $\x01\0"
    /* 4153 */ "fmovsn %xcc, $\x02, $\x01\0"
    /* 4173 */ "fmovsne %xcc, $\x02, $\x01\0"
    /* 4194 */ "fmovse %xcc, $\x02, $\x01\0"
    /* 4214 */ "fmovsg %xcc, $\x02, $\x01\0"
    /* 4234 */ "fmovsle %xcc, $\x02, $\x01\0"
    /* 4255 */ "fmovsge %xcc, $\x02, $\x01\0"
    /* 4276 */ "fmovsl %xcc, $\x02, $\x01\0"
    /* 4296 */ "fmovsgu %xcc, $\x02, $\x01\0"
    /* 4317 */ "fmovsleu %xcc, $\x02, $\x01\0"
    /* 4339 */ "fmovscc %xcc, $\x02, $\x01\0"
    /* 4360 */ "fmovscs %xcc, $\x02, $\x01\0"
    /* 4381 */ "fmovspos %xcc, $\x02, $\x01\0"
    /* 4403 */ "fmovsneg %xcc, $\x02, $\x01\0"
    /* 4425 */ "fmovsvc %xcc, $\x02, $\x01\0"
    /* 4446 */ "fmovsvs %xcc, $\x02, $\x01\0"
    /* 4467 */ "mova %icc, $\x02, $\x01\0"
    /* 4485 */ "movn %icc, $\x02, $\x01\0"
    /* 4503 */ "movne %icc, $\x02, $\x01\0"
    /* 4522 */ "move %icc, $\x02, $\x01\0"
    /* 4540 */ "movg %icc, $\x02, $\x01\0"
    /* 4558 */ "movle %icc, $\x02, $\x01\0"
    /* 4577 */ "movge %icc, $\x02, $\x01\0"
    /* 4596 */ "movl %icc, $\x02, $\x01\0"
    /* 4614 */ "movgu %icc, $\x02, $\x01\0"
    /* 4633 */ "movleu %icc, $\x02, $\x01\0"
    /* 4653 */ "movcc %icc, $\x02, $\x01\0"
    /* 4672 */ "movcs %icc, $\x02, $\x01\0"
    /* 4691 */ "movpos %icc, $\x02, $\x01\0"
    /* 4711 */ "movneg %icc, $\x02, $\x01\0"
    /* 4731 */ "movvc %icc, $\x02, $\x01\0"
    /* 4750 */ "movvs %icc, $\x02, $\x01\0"
    /* 4769 */ "movrz $\x02, $\x03, $\x01\0"
    /* 4786 */ "movrlez $\x02, $\x03, $\x01\0"
    /* 4805 */ "movrlz $\x02, $\x03, $\x01\0"
    /* 4823 */ "movrnz $\x02, $\x03, $\x01\0"
    /* 4841 */ "movrgz $\x02, $\x03, $\x01\0"
    /* 4859 */ "movrgez $\x02, $\x03, $\x01\0"
    /* 4878 */ "mova %xcc, $\x02, $\x01\0"
    /* 4896 */ "movn %xcc, $\x02, $\x01\0"
    /* 4914 */ "movne %xcc, $\x02, $\x01\0"
    /* 4933 */ "move %xcc, $\x02, $\x01\0"
    /* 4951 */ "movg %xcc, $\x02, $\x01\0"
    /* 4969 */ "movle %xcc, $\x02, $\x01\0"
    /* 4988 */ "movge %xcc, $\x02, $\x01\0"
    /* 5007 */ "movl %xcc, $\x02, $\x01\0"
    /* 5025 */ "movgu %xcc, $\x02, $\x01\0"
    /* 5044 */ "movleu %xcc, $\x02, $\x01\0"
    /* 5064 */ "movcc %xcc, $\x02, $\x01\0"
    /* 5083 */ "movcs %xcc, $\x02, $\x01\0"
    /* 5102 */ "movpos %xcc, $\x02, $\x01\0"
    /* 5122 */ "movneg %xcc, $\x02, $\x01\0"
    /* 5142 */ "movvc %xcc, $\x02, $\x01\0"
    /* 5161 */ "movvs %xcc, $\x02, $\x01\0"
    /* 5180 */ "tst $\x02\0"
    /* 5187 */ "mov $\x03, $\x01\0"
    /* 5198 */ "restore\0"
    /* 5206 */ "ret\0"
    /* 5210 */ "retl\0"
    /* 5215 */ "save\0"
    /* 5220 */ "cmp $\x02, $\x03\0"
    /* 5231 */ "ta %icc, $\x02\0"
    /* 5243 */ "ta %icc, $\x01 + $\x02\0"
    /* 5260 */ "tn %icc, $\x02\0"
    /* 5272 */ "tn %icc, $\x01 + $\x02\0"
    /* 5289 */ "tne %icc, $\x02\0"
    /* 5302 */ "tne %icc, $\x01 + $\x02\0"
    /* 5320 */ "te %icc, $\x02\0"
    /* 5332 */ "te %icc, $\x01 + $\x02\0"
    /* 5349 */ "tg %icc, $\x02\0"
    /* 5361 */ "tg %icc, $\x01 + $\x02\0"
    /* 5378 */ "tle %icc, $\x02\0"
    /* 5391 */ "tle %icc, $\x01 + $\x02\0"
    /* 5409 */ "tge %icc, $\x02\0"
    /* 5422 */ "tge %icc, $\x01 + $\x02\0"
    /* 5440 */ "tl %icc, $\x02\0"
    /* 5452 */ "tl %icc, $\x01 + $\x02\0"
    /* 5469 */ "tgu %icc, $\x02\0"
    /* 5482 */ "tgu %icc, $\x01 + $\x02\0"
    /* 5500 */ "tleu %icc, $\x02\0"
    /* 5514 */ "tleu %icc, $\x01 + $\x02\0"
    /* 5533 */ "tcc %icc, $\x02\0"
    /* 5546 */ "tcc %icc, $\x01 + $\x02\0"
    /* 5564 */ "tcs %icc, $\x02\0"
    /* 5577 */ "tcs %icc, $\x01 + $\x02\0"
    /* 5595 */ "tpos %icc, $\x02\0"
    /* 5609 */ "tpos %icc, $\x01 + $\x02\0"
    /* 5628 */ "tneg %icc, $\x02\0"
    /* 5642 */ "tneg %icc, $\x01 + $\x02\0"
    /* 5661 */ "tvc %icc, $\x02\0"
    /* 5674 */ "tvc %icc, $\x01 + $\x02\0"
    /* 5692 */ "tvs %icc, $\x02\0"
    /* 5705 */ "tvs %icc, $\x01 + $\x02\0"
    /* 5723 */ "ta $\x02\0"
    /* 5729 */ "ta $\x01 + $\x02\0"
    /* 5740 */ "tn $\x02\0"
    /* 5746 */ "tn $\x01 + $\x02\0"
    /* 5757 */ "tne $\x02\0"
    /* 5764 */ "tne $\x01 + $\x02\0"
    /* 5776 */ "te $\x02\0"
    /* 5782 */ "te $\x01 + $\x02\0"
    /* 5793 */ "tg $\x02\0"
    /* 5799 */ "tg $\x01 + $\x02\0"
    /* 5810 */ "tle $\x02\0"
    /* 5817 */ "tle $\x01 + $\x02\0"
    /* 5829 */ "tge $\x02\0"
    /* 5836 */ "tge $\x01 + $\x02\0"
    /* 5848 */ "tl $\x02\0"
    /* 5854 */ "tl $\x01 + $\x02\0"
    /* 5865 */ "tgu $\x02\0"
    /* 5872 */ "tgu $\x01 + $\x02\0"
    /* 5884 */ "tleu $\x02\0"
    /* 5892 */ "tleu $\x01 + $\x02\0"
    /* 5905 */ "tcc $\x02\0"
    /* 5912 */ "tcc $\x01 + $\x02\0"
    /* 5924 */ "tcs $\x02\0"
    /* 5931 */ "tcs $\x01 + $\x02\0"
    /* 5943 */ "tpos $\x02\0"
    /* 5951 */ "tpos $\x01 + $\x02\0"
    /* 5964 */ "tneg $\x02\0"
    /* 5972 */ "tneg $\x01 + $\x02\0"
    /* 5985 */ "tvc $\x02\0"
    /* 5992 */ "tvc $\x01 + $\x02\0"
    /* 6004 */ "tvs $\x02\0"
    /* 6011 */ "tvs $\x01 + $\x02\0"
    /* 6023 */ "ta %xcc, $\x02\0"
    /* 6035 */ "ta %xcc, $\x01 + $\x02\0"
    /* 6052 */ "tn %xcc, $\x02\0"
    /* 6064 */ "tn %xcc, $\x01 + $\x02\0"
    /* 6081 */ "tne %xcc, $\x02\0"
    /* 6094 */ "tne %xcc, $\x01 + $\x02\0"
    /* 6112 */ "te %xcc, $\x02\0"
    /* 6124 */ "te %xcc, $\x01 + $\x02\0"
    /* 6141 */ "tg %xcc, $\x02\0"
    /* 6153 */ "tg %xcc, $\x01 + $\x02\0"
    /* 6170 */ "tle %xcc, $\x02\0"
    /* 6183 */ "tle %xcc, $\x01 + $\x02\0"
    /* 6201 */ "tge %xcc, $\x02\0"
    /* 6214 */ "tge %xcc, $\x01 + $\x02\0"
    /* 6232 */ "tl %xcc, $\x02\0"
    /* 6244 */ "tl %xcc, $\x01 + $\x02\0"
    /* 6261 */ "tgu %xcc, $\x02\0"
    /* 6274 */ "tgu %xcc, $\x01 + $\x02\0"
    /* 6292 */ "tleu %xcc, $\x02\0"
    /* 6306 */ "tleu %xcc, $\x01 + $\x02\0"
    /* 6325 */ "tcc %xcc, $\x02\0"
    /* 6338 */ "tcc %xcc, $\x01 + $\x02\0"
    /* 6356 */ "tcs %xcc, $\x02\0"
    /* 6369 */ "tcs %xcc, $\x01 + $\x02\0"
    /* 6387 */ "tpos %xcc, $\x02\0"
    /* 6401 */ "tpos %xcc, $\x01 + $\x02\0"
    /* 6420 */ "tneg %xcc, $\x02\0"
    /* 6434 */ "tneg %xcc, $\x01 + $\x02\0"
    /* 6453 */ "tvc %xcc, $\x02\0"
    /* 6466 */ "tvc %xcc, $\x01 + $\x02\0"
    /* 6484 */ "tvs %xcc, $\x02\0"
    /* 6497 */ "tvs %xcc, $\x01 + $\x02\0"
    /* 6515 */ "fcmpd $\x02, $\x03\0"
    /* 6528 */ "fcmped $\x02, $\x03\0"
    /* 6542 */ "fcmpeq $\x02, $\x03\0"
    /* 6556 */ "fcmpes $\x02, $\x03\0"
    /* 6570 */ "fcmpq $\x02, $\x03\0"
    /* 6583 */ "fcmps $\x02, $\x03\0"
    /* 6596 */ "fmovda $\x02, $\x03, $\x01\0"
    /* 6614 */ "fmovdn $\x02, $\x03, $\x01\0"
    /* 6632 */ "fmovdu $\x02, $\x03, $\x01\0"
    /* 6650 */ "fmovdg $\x02, $\x03, $\x01\0"
    /* 6668 */ "fmovdug $\x02, $\x03, $\x01\0"
    /* 6687 */ "fmovdl $\x02, $\x03, $\x01\0"
    /* 6705 */ "fmovdul $\x02, $\x03, $\x01\0"
    /* 6724 */ "fmovdlg $\x02, $\x03, $\x01\0"
    /* 6743 */ "fmovdne $\x02, $\x03, $\x01\0"
    /* 6762 */ "fmovde $\x02, $\x03, $\x01\0"
    /* 6780 */ "fmovdue $\x02, $\x03, $\x01\0"
    /* 6799 */ "fmovdge $\x02, $\x03, $\x01\0"
    /* 6818 */ "fmovduge $\x02, $\x03, $\x01\0"
    /* 6838 */ "fmovdle $\x02, $\x03, $\x01\0"
    /* 6857 */ "fmovdule $\x02, $\x03, $\x01\0"
    /* 6877 */ "fmovdo $\x02, $\x03, $\x01\0"
    /* 6895 */ "fmovqa $\x02, $\x03, $\x01\0"
    /* 6913 */ "fmovqn $\x02, $\x03, $\x01\0"
    /* 6931 */ "fmovqu $\x02, $\x03, $\x01\0"
    /* 6949 */ "fmovqg $\x02, $\x03, $\x01\0"
    /* 6967 */ "fmovqug $\x02, $\x03, $\x01\0"
    /* 6986 */ "fmovql $\x02, $\x03, $\x01\0"
    /* 7004 */ "fmovqul $\x02, $\x03, $\x01\0"
    /* 7023 */ "fmovqlg $\x02, $\x03, $\x01\0"
    /* 7042 */ "fmovqne $\x02, $\x03, $\x01\0"
    /* 7061 */ "fmovqe $\x02, $\x03, $\x01\0"
    /* 7079 */ "fmovque $\x02, $\x03, $\x01\0"
    /* 7098 */ "fmovqge $\x02, $\x03, $\x01\0"
    /* 7117 */ "fmovquge $\x02, $\x03, $\x01\0"
    /* 7137 */ "fmovqle $\x02, $\x03, $\x01\0"
    /* 7156 */ "fmovqule $\x02, $\x03, $\x01\0"
    /* 7176 */ "fmovqo $\x02, $\x03, $\x01\0"
    /* 7194 */ "fmovsa $\x02, $\x03, $\x01\0"
    /* 7212 */ "fmovsn $\x02, $\x03, $\x01\0"
    /* 7230 */ "fmovsu $\x02, $\x03, $\x01\0"
    /* 7248 */ "fmovsg $\x02, $\x03, $\x01\0"
    /* 7266 */ "fmovsug $\x02, $\x03, $\x01\0"
    /* 7285 */ "fmovsl $\x02, $\x03, $\x01\0"
    /* 7303 */ "fmovsul $\x02, $\x03, $\x01\0"
    /* 7322 */ "fmovslg $\x02, $\x03, $\x01\0"
    /* 7341 */ "fmovsne $\x02, $\x03, $\x01\0"
    /* 7360 */ "fmovse $\x02, $\x03, $\x01\0"
    /* 7378 */ "fmovsue $\x02, $\x03, $\x01\0"
    /* 7397 */ "fmovsge $\x02, $\x03, $\x01\0"
    /* 7416 */ "fmovsuge $\x02, $\x03, $\x01\0"
    /* 7436 */ "fmovsle $\x02, $\x03, $\x01\0"
    /* 7455 */ "fmovsule $\x02, $\x03, $\x01\0"
    /* 7475 */ "fmovso $\x02, $\x03, $\x01\0"
    /* 7493 */ "mova $\x02, $\x03, $\x01\0"
    /* 7509 */ "movn $\x02, $\x03, $\x01\0"
    /* 7525 */ "movu $\x02, $\x03, $\x01\0"
    /* 7541 */ "movg $\x02, $\x03, $\x01\0"
    /* 7557 */ "movug $\x02, $\x03, $\x01\0"
    /* 7574 */ "movl $\x02, $\x03, $\x01\0"
    /* 7590 */ "movul $\x02, $\x03, $\x01\0"
    /* 7607 */ "movlg $\x02, $\x03, $\x01\0"
    /* 7624 */ "movne $\x02, $\x03, $\x01\0"
    /* 7641 */ "move $\x02, $\x03, $\x01\0"
    /* 7657 */ "movue $\x02, $\x03, $\x01\0"
    /* 7674 */ "movge $\x02, $\x03, $\x01\0"
    /* 7691 */ "movuge $\x02, $\x03, $\x01\0"
    /* 7709 */ "movle $\x02, $\x03, $\x01\0"
    /* 7726 */ "movule $\x02, $\x03, $\x01\0"
    /* 7744 */ "movo $\x02, $\x03, $\x01\0"
  ;

#ifndef NDEBUG
  static struct SortCheck {
    SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
      assert(std::is_sorted(
                 OpToPatterns.begin(), OpToPatterns.end(),
                 [](const PatternsForOpcode &L, const PatternsForOpcode &R) {
                   return L.Opcode < R.Opcode;
                 }) &&
             "tablegen failed to sort opcode patterns");
    }
  } sortCheckVar(OpToPatterns);
#endif

  AliasMatchingData M {
    ArrayRef(OpToPatterns),
    ArrayRef(Patterns),
    ArrayRef(Conds),
    StringRef(AsmStrings, std::size(AsmStrings)),
    nullptr,
  };
  const char *AsmString = matchAliasPatterns(MI, &STI, M);
  if (!AsmString) return false;

  unsigned I = 0;
  while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
         AsmString[I] != '$' && AsmString[I] != '\0')
    ++I;
  OS << '\t' << StringRef(AsmString, I);
  if (AsmString[I] != '\0') {
    if (AsmString[I] == ' ' || AsmString[I] == '\t') {
      OS << '\t';
      ++I;
    }
    do {
      if (AsmString[I] == '$') {
        ++I;
        if (AsmString[I] == (char)0xff) {
          ++I;
          int OpIdx = AsmString[I++] - 1;
          int PrintMethodIdx = AsmString[I++] - 1;
          printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, STI, OS);
        } else
          printOperand(MI, unsigned(AsmString[I++]) - 1, STI, OS);
      } else {
        OS << AsmString[I++];
      }
    } while (AsmString[I] != '\0');
  }

  return true;
}

void SparcInstPrinter::printCustomAliasOperand(
         const MCInst *MI, uint64_t Address, unsigned OpIdx,
         unsigned PrintMethodIdx,
         const MCSubtargetInfo &STI,
         raw_ostream &OS) {
  llvm_unreachable("Unknown PrintMethod kind");
}

#endif // PRINT_ALIAS_INSTR

Coverage Report

Created: 2024-01-17 10:31