/src/build/lib/Target/Sparc/SparcGenCallingConv.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Calling Convention Implementation Fragment                                 *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifndef GET_CC_REGISTER_LISTS

static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State);


static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (ArgFlags.isSRet()) {
    if (CC_Sparc_Assign_SRet(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (LocVT == MVT::i32 ||
      LocVT == MVT::f32) {
    static const MCPhysReg RegList1[] = {
      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
    };
    if (unsigned Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (LocVT == MVT::v2i32) {
    if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  int64_t Offset2 = State.AllocateStack(4, Align(4));
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
  return false;

  return true; // CC didn't match.
}


static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (ArgFlags.isInReg()) {
    if (LocVT == MVT::i32 ||
        LocVT == MVT::f32) {
      if (CC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
        return false;
    }
  }

  if (LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (CC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
    return false;

  return true; // CC didn't match.
}


static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::i32) {
    static const MCPhysReg RegList1[] = {
      SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
    };
    if (unsigned Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f32) {
    static const MCPhysReg RegList2[] = {
      SP::F0, SP::F1, SP::F2, SP::F3
    };
    if (unsigned Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f64) {
    static const MCPhysReg RegList3[] = {
      SP::D0, SP::D1
    };
    if (unsigned Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v2i32) {
    if (CC_Sparc_Assign_Ret_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  return true; // CC didn't match.
}


static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::f32) {
    if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
      return false;
  }

  if (ArgFlags.isInReg()) {
    if (LocVT == MVT::i32 ||
        LocVT == MVT::f32) {
      if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
        return false;
    }
  }

  if (LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (RetCC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
    return false;

  return true; // CC didn't match.
}

#else

const MCRegister CC_Sparc32_ArgRegs[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
const MCRegister CC_Sparc64_ArgRegs[] = { 0 };
const MCRegister RetCC_Sparc32_ArgRegs[] = { SP::D0, SP::D1, SP::F0, SP::F1, SP::F2, SP::F3, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
const MCRegister RetCC_Sparc64_ArgRegs[] = { 0 };

#endif // CC_REGISTER_LIST

Line	Count	Source (jump to first uncovered line)
1		/===- TableGen'erated file -------------------------------------- C++ --===\
2		\|* *\|
3		\|* Calling Convention Implementation Fragment *\|
4		\|* *\|
5		\|* Automatically generated file, do not edit! *\|
6		\|* *\|
7		\===----------------------------------------------------------------------===/
8
9		#ifndef GET_CC_REGISTER_LISTS
10
11		static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
12		MVT LocVT, CCValAssign::LocInfo LocInfo,
13		ISD::ArgFlagsTy ArgFlags, CCState &State);
14		static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
15		MVT LocVT, CCValAssign::LocInfo LocInfo,
16		ISD::ArgFlagsTy ArgFlags, CCState &State);
17		static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
18		MVT LocVT, CCValAssign::LocInfo LocInfo,
19		ISD::ArgFlagsTy ArgFlags, CCState &State);
20		static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
21		MVT LocVT, CCValAssign::LocInfo LocInfo,
22		ISD::ArgFlagsTy ArgFlags, CCState &State);
23
24
25		static bool CC_Sparc32(unsigned ValNo, MVT ValVT,
26		MVT LocVT, CCValAssign::LocInfo LocInfo,
27	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
28
29	0	if (ArgFlags.isSRet()) {
30	0	if (CC_Sparc_Assign_SRet(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
31	0	return false;
32	0	}
33
34	0	if (LocVT == MVT::i32 \|\|
35	0	LocVT == MVT::f32) {
36	0	static const MCPhysReg RegList1[] = {
37	0	SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
38	0	};
39	0	if (unsigned Reg = State.AllocateReg(RegList1)) {
40	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
41	0	return false;
42	0	}
43	0	}
44
45	0	if (LocVT == MVT::f64) {
46	0	if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
47	0	return false;
48	0	}
49
50	0	if (LocVT == MVT::v2i32) {
51	0	if (CC_Sparc_Assign_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
52	0	return false;
53	0	}
54
55	0	int64_t Offset2 = State.AllocateStack(4, Align(4));
56	0	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
57	0	return false;
58
59	0	return true; // CC didn't match.
60	0	}
61
62
63		static bool CC_Sparc64(unsigned ValNo, MVT ValVT,
64		MVT LocVT, CCValAssign::LocInfo LocInfo,
65	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
66
67	0	if (ArgFlags.isInReg()) {
68	0	if (LocVT == MVT::i32 \|\|
69	0	LocVT == MVT::f32) {
70	0	if (CC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
71	0	return false;
72	0	}
73	0	}
74
75	0	if (LocVT == MVT::i32) {
76	0	LocVT = MVT::i64;
77	0	if (ArgFlags.isSExt())
78	0	LocInfo = CCValAssign::SExt;
79	0	else if (ArgFlags.isZExt())
80	0	LocInfo = CCValAssign::ZExt;
81	0	else
82	0	LocInfo = CCValAssign::AExt;
83	0	}
84
85	0	if (CC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
86	0	return false;
87
88	0	return true; // CC didn't match.
89	0	}
90
91
92		static bool RetCC_Sparc32(unsigned ValNo, MVT ValVT,
93		MVT LocVT, CCValAssign::LocInfo LocInfo,
94	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
95
96	0	if (LocVT == MVT::i32) {
97	0	static const MCPhysReg RegList1[] = {
98	0	SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
99	0	};
100	0	if (unsigned Reg = State.AllocateReg(RegList1)) {
101	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
102	0	return false;
103	0	}
104	0	}
105
106	0	if (LocVT == MVT::f32) {
107	0	static const MCPhysReg RegList2[] = {
108	0	SP::F0, SP::F1, SP::F2, SP::F3
109	0	};
110	0	if (unsigned Reg = State.AllocateReg(RegList2)) {
111	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
112	0	return false;
113	0	}
114	0	}
115
116	0	if (LocVT == MVT::f64) {
117	0	static const MCPhysReg RegList3[] = {
118	0	SP::D0, SP::D1
119	0	};
120	0	if (unsigned Reg = State.AllocateReg(RegList3)) {
121	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
122	0	return false;
123	0	}
124	0	}
125
126	0	if (LocVT == MVT::v2i32) {
127	0	if (CC_Sparc_Assign_Ret_Split_64(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
128	0	return false;
129	0	}
130
131	0	return true; // CC didn't match.
132	0	}
133
134
135		static bool RetCC_Sparc64(unsigned ValNo, MVT ValVT,
136		MVT LocVT, CCValAssign::LocInfo LocInfo,
137	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
138
139	0	if (LocVT == MVT::f32) {
140	0	if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
141	0	return false;
142	0	}
143
144	0	if (ArgFlags.isInReg()) {
145	0	if (LocVT == MVT::i32 \|\|
146	0	LocVT == MVT::f32) {
147	0	if (RetCC_Sparc64_Half(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
148	0	return false;
149	0	}
150	0	}
151
152	0	if (LocVT == MVT::i32) {
153	0	LocVT = MVT::i64;
154	0	if (ArgFlags.isSExt())
155	0	LocInfo = CCValAssign::SExt;
156	0	else if (ArgFlags.isZExt())
157	0	LocInfo = CCValAssign::ZExt;
158	0	else
159	0	LocInfo = CCValAssign::AExt;
160	0	}
161
162	0	if (RetCC_Sparc64_Full(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
163	0	return false;
164
165	0	return true; // CC didn't match.
166	0	}
167
168		#else
169
170		const MCRegister CC_Sparc32_ArgRegs[] = { SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
171		const MCRegister CC_Sparc64_ArgRegs[] = { 0 };
172		const MCRegister RetCC_Sparc32_ArgRegs[] = { SP::D0, SP::D1, SP::F0, SP::F1, SP::F2, SP::F3, SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 };
173		const MCRegister RetCC_Sparc64_ArgRegs[] = { 0 };
174
175		#endif // CC_REGISTER_LIST

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Created: 2024-01-17 10:31