Coverage Report

Created: 2024-01-17 10:31

/src/build/lib/Target/Sparc/SparcGenInstrInfo.inc
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1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values and Descriptors                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
#ifdef GET_INSTRINFO_ENUM
10
#undef GET_INSTRINFO_ENUM
11
namespace llvm {
12
13
namespace SP {
14
  enum {
15
    PHI = 0,
16
    INLINEASM = 1,
17
    INLINEASM_BR  = 2,
18
    CFI_INSTRUCTION = 3,
19
    EH_LABEL  = 4,
20
    GC_LABEL  = 5,
21
    ANNOTATION_LABEL  = 6,
22
    KILL  = 7,
23
    EXTRACT_SUBREG  = 8,
24
    INSERT_SUBREG = 9,
25
    IMPLICIT_DEF  = 10,
26
    SUBREG_TO_REG = 11,
27
    COPY_TO_REGCLASS  = 12,
28
    DBG_VALUE = 13,
29
    DBG_VALUE_LIST  = 14,
30
    DBG_INSTR_REF = 15,
31
    DBG_PHI = 16,
32
    DBG_LABEL = 17,
33
    REG_SEQUENCE  = 18,
34
    COPY  = 19,
35
    BUNDLE  = 20,
36
    LIFETIME_START  = 21,
37
    LIFETIME_END  = 22,
38
    PSEUDO_PROBE  = 23,
39
    ARITH_FENCE = 24,
40
    STACKMAP  = 25,
41
    FENTRY_CALL = 26,
42
    PATCHPOINT  = 27,
43
    LOAD_STACK_GUARD  = 28,
44
    PREALLOCATED_SETUP  = 29,
45
    PREALLOCATED_ARG  = 30,
46
    STATEPOINT  = 31,
47
    LOCAL_ESCAPE  = 32,
48
    FAULTING_OP = 33,
49
    PATCHABLE_OP  = 34,
50
    PATCHABLE_FUNCTION_ENTER  = 35,
51
    PATCHABLE_RET = 36,
52
    PATCHABLE_FUNCTION_EXIT = 37,
53
    PATCHABLE_TAIL_CALL = 38,
54
    PATCHABLE_EVENT_CALL  = 39,
55
    PATCHABLE_TYPED_EVENT_CALL  = 40,
56
    ICALL_BRANCH_FUNNEL = 41,
57
    MEMBARRIER  = 42,
58
    JUMP_TABLE_DEBUG_INFO = 43,
59
    G_ASSERT_SEXT = 44,
60
    G_ASSERT_ZEXT = 45,
61
    G_ASSERT_ALIGN  = 46,
62
    G_ADD = 47,
63
    G_SUB = 48,
64
    G_MUL = 49,
65
    G_SDIV  = 50,
66
    G_UDIV  = 51,
67
    G_SREM  = 52,
68
    G_UREM  = 53,
69
    G_SDIVREM = 54,
70
    G_UDIVREM = 55,
71
    G_AND = 56,
72
    G_OR  = 57,
73
    G_XOR = 58,
74
    G_IMPLICIT_DEF  = 59,
75
    G_PHI = 60,
76
    G_FRAME_INDEX = 61,
77
    G_GLOBAL_VALUE  = 62,
78
    G_CONSTANT_POOL = 63,
79
    G_EXTRACT = 64,
80
    G_UNMERGE_VALUES  = 65,
81
    G_INSERT  = 66,
82
    G_MERGE_VALUES  = 67,
83
    G_BUILD_VECTOR  = 68,
84
    G_BUILD_VECTOR_TRUNC  = 69,
85
    G_CONCAT_VECTORS  = 70,
86
    G_PTRTOINT  = 71,
87
    G_INTTOPTR  = 72,
88
    G_BITCAST = 73,
89
    G_FREEZE  = 74,
90
    G_CONSTANT_FOLD_BARRIER = 75,
91
    G_INTRINSIC_FPTRUNC_ROUND = 76,
92
    G_INTRINSIC_TRUNC = 77,
93
    G_INTRINSIC_ROUND = 78,
94
    G_INTRINSIC_LRINT = 79,
95
    G_INTRINSIC_ROUNDEVEN = 80,
96
    G_READCYCLECOUNTER  = 81,
97
    G_LOAD  = 82,
98
    G_SEXTLOAD  = 83,
99
    G_ZEXTLOAD  = 84,
100
    G_INDEXED_LOAD  = 85,
101
    G_INDEXED_SEXTLOAD  = 86,
102
    G_INDEXED_ZEXTLOAD  = 87,
103
    G_STORE = 88,
104
    G_INDEXED_STORE = 89,
105
    G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90,
106
    G_ATOMIC_CMPXCHG  = 91,
107
    G_ATOMICRMW_XCHG  = 92,
108
    G_ATOMICRMW_ADD = 93,
109
    G_ATOMICRMW_SUB = 94,
110
    G_ATOMICRMW_AND = 95,
111
    G_ATOMICRMW_NAND  = 96,
112
    G_ATOMICRMW_OR  = 97,
113
    G_ATOMICRMW_XOR = 98,
114
    G_ATOMICRMW_MAX = 99,
115
    G_ATOMICRMW_MIN = 100,
116
    G_ATOMICRMW_UMAX  = 101,
117
    G_ATOMICRMW_UMIN  = 102,
118
    G_ATOMICRMW_FADD  = 103,
119
    G_ATOMICRMW_FSUB  = 104,
120
    G_ATOMICRMW_FMAX  = 105,
121
    G_ATOMICRMW_FMIN  = 106,
122
    G_ATOMICRMW_UINC_WRAP = 107,
123
    G_ATOMICRMW_UDEC_WRAP = 108,
124
    G_FENCE = 109,
125
    G_PREFETCH  = 110,
126
    G_BRCOND  = 111,
127
    G_BRINDIRECT  = 112,
128
    G_INVOKE_REGION_START = 113,
129
    G_INTRINSIC = 114,
130
    G_INTRINSIC_W_SIDE_EFFECTS  = 115,
131
    G_INTRINSIC_CONVERGENT  = 116,
132
    G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117,
133
    G_ANYEXT  = 118,
134
    G_TRUNC = 119,
135
    G_CONSTANT  = 120,
136
    G_FCONSTANT = 121,
137
    G_VASTART = 122,
138
    G_VAARG = 123,
139
    G_SEXT  = 124,
140
    G_SEXT_INREG  = 125,
141
    G_ZEXT  = 126,
142
    G_SHL = 127,
143
    G_LSHR  = 128,
144
    G_ASHR  = 129,
145
    G_FSHL  = 130,
146
    G_FSHR  = 131,
147
    G_ROTR  = 132,
148
    G_ROTL  = 133,
149
    G_ICMP  = 134,
150
    G_FCMP  = 135,
151
    G_SELECT  = 136,
152
    G_UADDO = 137,
153
    G_UADDE = 138,
154
    G_USUBO = 139,
155
    G_USUBE = 140,
156
    G_SADDO = 141,
157
    G_SADDE = 142,
158
    G_SSUBO = 143,
159
    G_SSUBE = 144,
160
    G_UMULO = 145,
161
    G_SMULO = 146,
162
    G_UMULH = 147,
163
    G_SMULH = 148,
164
    G_UADDSAT = 149,
165
    G_SADDSAT = 150,
166
    G_USUBSAT = 151,
167
    G_SSUBSAT = 152,
168
    G_USHLSAT = 153,
169
    G_SSHLSAT = 154,
170
    G_SMULFIX = 155,
171
    G_UMULFIX = 156,
172
    G_SMULFIXSAT  = 157,
173
    G_UMULFIXSAT  = 158,
174
    G_SDIVFIX = 159,
175
    G_UDIVFIX = 160,
176
    G_SDIVFIXSAT  = 161,
177
    G_UDIVFIXSAT  = 162,
178
    G_FADD  = 163,
179
    G_FSUB  = 164,
180
    G_FMUL  = 165,
181
    G_FMA = 166,
182
    G_FMAD  = 167,
183
    G_FDIV  = 168,
184
    G_FREM  = 169,
185
    G_FPOW  = 170,
186
    G_FPOWI = 171,
187
    G_FEXP  = 172,
188
    G_FEXP2 = 173,
189
    G_FEXP10  = 174,
190
    G_FLOG  = 175,
191
    G_FLOG2 = 176,
192
    G_FLOG10  = 177,
193
    G_FLDEXP  = 178,
194
    G_FFREXP  = 179,
195
    G_FNEG  = 180,
196
    G_FPEXT = 181,
197
    G_FPTRUNC = 182,
198
    G_FPTOSI  = 183,
199
    G_FPTOUI  = 184,
200
    G_SITOFP  = 185,
201
    G_UITOFP  = 186,
202
    G_FABS  = 187,
203
    G_FCOPYSIGN = 188,
204
    G_IS_FPCLASS  = 189,
205
    G_FCANONICALIZE = 190,
206
    G_FMINNUM = 191,
207
    G_FMAXNUM = 192,
208
    G_FMINNUM_IEEE  = 193,
209
    G_FMAXNUM_IEEE  = 194,
210
    G_FMINIMUM  = 195,
211
    G_FMAXIMUM  = 196,
212
    G_GET_FPENV = 197,
213
    G_SET_FPENV = 198,
214
    G_RESET_FPENV = 199,
215
    G_GET_FPMODE  = 200,
216
    G_SET_FPMODE  = 201,
217
    G_RESET_FPMODE  = 202,
218
    G_PTR_ADD = 203,
219
    G_PTRMASK = 204,
220
    G_SMIN  = 205,
221
    G_SMAX  = 206,
222
    G_UMIN  = 207,
223
    G_UMAX  = 208,
224
    G_ABS = 209,
225
    G_LROUND  = 210,
226
    G_LLROUND = 211,
227
    G_BR  = 212,
228
    G_BRJT  = 213,
229
    G_INSERT_VECTOR_ELT = 214,
230
    G_EXTRACT_VECTOR_ELT  = 215,
231
    G_SHUFFLE_VECTOR  = 216,
232
    G_CTTZ  = 217,
233
    G_CTTZ_ZERO_UNDEF = 218,
234
    G_CTLZ  = 219,
235
    G_CTLZ_ZERO_UNDEF = 220,
236
    G_CTPOP = 221,
237
    G_BSWAP = 222,
238
    G_BITREVERSE  = 223,
239
    G_FCEIL = 224,
240
    G_FCOS  = 225,
241
    G_FSIN  = 226,
242
    G_FSQRT = 227,
243
    G_FFLOOR  = 228,
244
    G_FRINT = 229,
245
    G_FNEARBYINT  = 230,
246
    G_ADDRSPACE_CAST  = 231,
247
    G_BLOCK_ADDR  = 232,
248
    G_JUMP_TABLE  = 233,
249
    G_DYN_STACKALLOC  = 234,
250
    G_STACKSAVE = 235,
251
    G_STACKRESTORE  = 236,
252
    G_STRICT_FADD = 237,
253
    G_STRICT_FSUB = 238,
254
    G_STRICT_FMUL = 239,
255
    G_STRICT_FDIV = 240,
256
    G_STRICT_FREM = 241,
257
    G_STRICT_FMA  = 242,
258
    G_STRICT_FSQRT  = 243,
259
    G_STRICT_FLDEXP = 244,
260
    G_READ_REGISTER = 245,
261
    G_WRITE_REGISTER  = 246,
262
    G_MEMCPY  = 247,
263
    G_MEMCPY_INLINE = 248,
264
    G_MEMMOVE = 249,
265
    G_MEMSET  = 250,
266
    G_BZERO = 251,
267
    G_VECREDUCE_SEQ_FADD  = 252,
268
    G_VECREDUCE_SEQ_FMUL  = 253,
269
    G_VECREDUCE_FADD  = 254,
270
    G_VECREDUCE_FMUL  = 255,
271
    G_VECREDUCE_FMAX  = 256,
272
    G_VECREDUCE_FMIN  = 257,
273
    G_VECREDUCE_FMAXIMUM  = 258,
274
    G_VECREDUCE_FMINIMUM  = 259,
275
    G_VECREDUCE_ADD = 260,
276
    G_VECREDUCE_MUL = 261,
277
    G_VECREDUCE_AND = 262,
278
    G_VECREDUCE_OR  = 263,
279
    G_VECREDUCE_XOR = 264,
280
    G_VECREDUCE_SMAX  = 265,
281
    G_VECREDUCE_SMIN  = 266,
282
    G_VECREDUCE_UMAX  = 267,
283
    G_VECREDUCE_UMIN  = 268,
284
    G_SBFX  = 269,
285
    G_UBFX  = 270,
286
    ADJCALLSTACKDOWN  = 271,
287
    ADJCALLSTACKUP  = 272,
288
    GETPCX  = 273,
289
    SELECT_CC_DFP_FCC = 274,
290
    SELECT_CC_DFP_ICC = 275,
291
    SELECT_CC_DFP_XCC = 276,
292
    SELECT_CC_FP_FCC  = 277,
293
    SELECT_CC_FP_ICC  = 278,
294
    SELECT_CC_FP_XCC  = 279,
295
    SELECT_CC_Int_FCC = 280,
296
    SELECT_CC_Int_ICC = 281,
297
    SELECT_CC_Int_XCC = 282,
298
    SELECT_CC_QFP_FCC = 283,
299
    SELECT_CC_QFP_ICC = 284,
300
    SELECT_CC_QFP_XCC = 285,
301
    SET = 286,
302
    SETX  = 287,
303
    ADDCCri = 288,
304
    ADDCCrr = 289,
305
    ADDCri  = 290,
306
    ADDCrr  = 291,
307
    ADDEri  = 292,
308
    ADDErr  = 293,
309
    ADDXC = 294,
310
    ADDXCCC = 295,
311
    ADDri = 296,
312
    ADDrr = 297,
313
    ALIGNADDR = 298,
314
    ALIGNADDRL  = 299,
315
    ANDCCri = 300,
316
    ANDCCrr = 301,
317
    ANDNCCri  = 302,
318
    ANDNCCrr  = 303,
319
    ANDNri  = 304,
320
    ANDNrr  = 305,
321
    ANDri = 306,
322
    ANDrr = 307,
323
    ARRAY16 = 308,
324
    ARRAY32 = 309,
325
    ARRAY8  = 310,
326
    BA  = 311,
327
    BCOND = 312,
328
    BCONDA  = 313,
329
    BINDri  = 314,
330
    BINDrr  = 315,
331
    BMASK = 316,
332
    BPFCC = 317,
333
    BPFCCA  = 318,
334
    BPFCCANT  = 319,
335
    BPFCCNT = 320,
336
    BPICC = 321,
337
    BPICCA  = 322,
338
    BPICCANT  = 323,
339
    BPICCNT = 324,
340
    BPR = 325,
341
    BPRA  = 326,
342
    BPRANT  = 327,
343
    BPRNT = 328,
344
    BPXCC = 329,
345
    BPXCCA  = 330,
346
    BPXCCANT  = 331,
347
    BPXCCNT = 332,
348
    BSHUFFLE  = 333,
349
    CALL  = 334,
350
    CALLri  = 335,
351
    CALLrr  = 336,
352
    CASAri  = 337,
353
    CASArr  = 338,
354
    CASXAri = 339,
355
    CASXArr = 340,
356
    CBCOND  = 341,
357
    CBCONDA = 342,
358
    CMASK16 = 343,
359
    CMASK32 = 344,
360
    CMASK8  = 345,
361
    DONE  = 346,
362
    EDGE16  = 347,
363
    EDGE16L = 348,
364
    EDGE16LN  = 349,
365
    EDGE16N = 350,
366
    EDGE32  = 351,
367
    EDGE32L = 352,
368
    EDGE32LN  = 353,
369
    EDGE32N = 354,
370
    EDGE8 = 355,
371
    EDGE8L  = 356,
372
    EDGE8LN = 357,
373
    EDGE8N  = 358,
374
    FABSD = 359,
375
    FABSQ = 360,
376
    FABSS = 361,
377
    FADDD = 362,
378
    FADDQ = 363,
379
    FADDS = 364,
380
    FALIGNADATA = 365,
381
    FAND  = 366,
382
    FANDNOT1  = 367,
383
    FANDNOT1S = 368,
384
    FANDNOT2  = 369,
385
    FANDNOT2S = 370,
386
    FANDS = 371,
387
    FBCOND  = 372,
388
    FBCONDA = 373,
389
    FBCONDA_V9  = 374,
390
    FBCOND_V9 = 375,
391
    FCHKSM16  = 376,
392
    FCMPD = 377,
393
    FCMPD_V9  = 378,
394
    FCMPEQ16  = 379,
395
    FCMPEQ32  = 380,
396
    FCMPGT16  = 381,
397
    FCMPGT32  = 382,
398
    FCMPLE16  = 383,
399
    FCMPLE32  = 384,
400
    FCMPNE16  = 385,
401
    FCMPNE32  = 386,
402
    FCMPQ = 387,
403
    FCMPQ_V9  = 388,
404
    FCMPS = 389,
405
    FCMPS_V9  = 390,
406
    FDIVD = 391,
407
    FDIVQ = 392,
408
    FDIVS = 393,
409
    FDMULQ  = 394,
410
    FDTOI = 395,
411
    FDTOQ = 396,
412
    FDTOS = 397,
413
    FDTOX = 398,
414
    FEXPAND = 399,
415
    FHADDD  = 400,
416
    FHADDS  = 401,
417
    FHSUBD  = 402,
418
    FHSUBS  = 403,
419
    FITOD = 404,
420
    FITOQ = 405,
421
    FITOS = 406,
422
    FLCMPD  = 407,
423
    FLCMPS  = 408,
424
    FLUSH = 409,
425
    FLUSHW  = 410,
426
    FLUSHri = 411,
427
    FLUSHrr = 412,
428
    FMEAN16 = 413,
429
    FMOVD = 414,
430
    FMOVD_FCC = 415,
431
    FMOVD_ICC = 416,
432
    FMOVD_XCC = 417,
433
    FMOVQ = 418,
434
    FMOVQ_FCC = 419,
435
    FMOVQ_ICC = 420,
436
    FMOVQ_XCC = 421,
437
    FMOVRD  = 422,
438
    FMOVRQ  = 423,
439
    FMOVRS  = 424,
440
    FMOVS = 425,
441
    FMOVS_FCC = 426,
442
    FMOVS_ICC = 427,
443
    FMOVS_XCC = 428,
444
    FMUL8SUX16  = 429,
445
    FMUL8ULX16  = 430,
446
    FMUL8X16  = 431,
447
    FMUL8X16AL  = 432,
448
    FMUL8X16AU  = 433,
449
    FMULD = 434,
450
    FMULD8SUX16 = 435,
451
    FMULD8ULX16 = 436,
452
    FMULQ = 437,
453
    FMULS = 438,
454
    FNADDD  = 439,
455
    FNADDS  = 440,
456
    FNAND = 441,
457
    FNANDS  = 442,
458
    FNEGD = 443,
459
    FNEGQ = 444,
460
    FNEGS = 445,
461
    FNHADDD = 446,
462
    FNHADDS = 447,
463
    FNMULD  = 448,
464
    FNMULS  = 449,
465
    FNOR  = 450,
466
    FNORS = 451,
467
    FNOT1 = 452,
468
    FNOT1S  = 453,
469
    FNOT2 = 454,
470
    FNOT2S  = 455,
471
    FNSMULD = 456,
472
    FONE  = 457,
473
    FONES = 458,
474
    FOR = 459,
475
    FORNOT1 = 460,
476
    FORNOT1S  = 461,
477
    FORNOT2 = 462,
478
    FORNOT2S  = 463,
479
    FORS  = 464,
480
    FPACK16 = 465,
481
    FPACK32 = 466,
482
    FPACKFIX  = 467,
483
    FPADD16 = 468,
484
    FPADD16S  = 469,
485
    FPADD32 = 470,
486
    FPADD32S  = 471,
487
    FPADD64 = 472,
488
    FPMERGE = 473,
489
    FPSUB16 = 474,
490
    FPSUB16S  = 475,
491
    FPSUB32 = 476,
492
    FPSUB32S  = 477,
493
    FQTOD = 478,
494
    FQTOI = 479,
495
    FQTOS = 480,
496
    FQTOX = 481,
497
    FSLAS16 = 482,
498
    FSLAS32 = 483,
499
    FSLL16  = 484,
500
    FSLL32  = 485,
501
    FSMULD  = 486,
502
    FSQRTD  = 487,
503
    FSQRTQ  = 488,
504
    FSQRTS  = 489,
505
    FSRA16  = 490,
506
    FSRA32  = 491,
507
    FSRC1 = 492,
508
    FSRC1S  = 493,
509
    FSRC2 = 494,
510
    FSRC2S  = 495,
511
    FSRL16  = 496,
512
    FSRL32  = 497,
513
    FSTOD = 498,
514
    FSTOI = 499,
515
    FSTOQ = 500,
516
    FSTOX = 501,
517
    FSUBD = 502,
518
    FSUBQ = 503,
519
    FSUBS = 504,
520
    FXNOR = 505,
521
    FXNORS  = 506,
522
    FXOR  = 507,
523
    FXORS = 508,
524
    FXTOD = 509,
525
    FXTOQ = 510,
526
    FXTOS = 511,
527
    FZERO = 512,
528
    FZEROS  = 513,
529
    GDOP_LDXrr  = 514,
530
    GDOP_LDrr = 515,
531
    JMPLri  = 516,
532
    JMPLrr  = 517,
533
    LDAri = 518,
534
    LDArr = 519,
535
    LDCSRri = 520,
536
    LDCSRrr = 521,
537
    LDCri = 522,
538
    LDCrr = 523,
539
    LDDAri  = 524,
540
    LDDArr  = 525,
541
    LDDCri  = 526,
542
    LDDCrr  = 527,
543
    LDDFAri = 528,
544
    LDDFArr = 529,
545
    LDDFri  = 530,
546
    LDDFrr  = 531,
547
    LDDri = 532,
548
    LDDrr = 533,
549
    LDFAri  = 534,
550
    LDFArr  = 535,
551
    LDFSRri = 536,
552
    LDFSRrr = 537,
553
    LDFri = 538,
554
    LDFrr = 539,
555
    LDQFAri = 540,
556
    LDQFArr = 541,
557
    LDQFri  = 542,
558
    LDQFrr  = 543,
559
    LDSBAri = 544,
560
    LDSBArr = 545,
561
    LDSBri  = 546,
562
    LDSBrr  = 547,
563
    LDSHAri = 548,
564
    LDSHArr = 549,
565
    LDSHri  = 550,
566
    LDSHrr  = 551,
567
    LDSTUBAri = 552,
568
    LDSTUBArr = 553,
569
    LDSTUBri  = 554,
570
    LDSTUBrr  = 555,
571
    LDSWAri = 556,
572
    LDSWArr = 557,
573
    LDSWri  = 558,
574
    LDSWrr  = 559,
575
    LDUBAri = 560,
576
    LDUBArr = 561,
577
    LDUBri  = 562,
578
    LDUBrr  = 563,
579
    LDUHAri = 564,
580
    LDUHArr = 565,
581
    LDUHri  = 566,
582
    LDUHrr  = 567,
583
    LDXAri  = 568,
584
    LDXArr  = 569,
585
    LDXFSRri  = 570,
586
    LDXFSRrr  = 571,
587
    LDXri = 572,
588
    LDXrr = 573,
589
    LDri  = 574,
590
    LDrr  = 575,
591
    LZCNT = 576,
592
    MEMBARi = 577,
593
    MOVDTOX = 578,
594
    MOVFCCri  = 579,
595
    MOVFCCrr  = 580,
596
    MOVICCri  = 581,
597
    MOVICCrr  = 582,
598
    MOVRri  = 583,
599
    MOVRrr  = 584,
600
    MOVSTOSW  = 585,
601
    MOVSTOUW  = 586,
602
    MOVWTOS = 587,
603
    MOVXCCri  = 588,
604
    MOVXCCrr  = 589,
605
    MOVXTOD = 590,
606
    MULSCCri  = 591,
607
    MULSCCrr  = 592,
608
    MULXri  = 593,
609
    MULXrr  = 594,
610
    NOP = 595,
611
    ORCCri  = 596,
612
    ORCCrr  = 597,
613
    ORNCCri = 598,
614
    ORNCCrr = 599,
615
    ORNri = 600,
616
    ORNrr = 601,
617
    ORri  = 602,
618
    ORrr  = 603,
619
    PDIST = 604,
620
    PDISTN  = 605,
621
    POPCrr  = 606,
622
    PREFETCHi = 607,
623
    PREFETCHr = 608,
624
    PWRPSRri  = 609,
625
    PWRPSRrr  = 610,
626
    RDASR = 611,
627
    RDFQ  = 612,
628
    RDPR  = 613,
629
    RDPSR = 614,
630
    RDTBR = 615,
631
    RDWIM = 616,
632
    RESTORED  = 617,
633
    RESTOREri = 618,
634
    RESTORErr = 619,
635
    RET = 620,
636
    RETL  = 621,
637
    RETRY = 622,
638
    RETTri  = 623,
639
    RETTrr  = 624,
640
    SAVED = 625,
641
    SAVEri  = 626,
642
    SAVErr  = 627,
643
    SDIVCCri  = 628,
644
    SDIVCCrr  = 629,
645
    SDIVXri = 630,
646
    SDIVXrr = 631,
647
    SDIVri  = 632,
648
    SDIVrr  = 633,
649
    SETHIi  = 634,
650
    SHUTDOWN  = 635,
651
    SIAM  = 636,
652
    SIR = 637,
653
    SLLXri  = 638,
654
    SLLXrr  = 639,
655
    SLLri = 640,
656
    SLLrr = 641,
657
    SMACri  = 642,
658
    SMACrr  = 643,
659
    SMULCCri  = 644,
660
    SMULCCrr  = 645,
661
    SMULri  = 646,
662
    SMULrr  = 647,
663
    SRAXri  = 648,
664
    SRAXrr  = 649,
665
    SRAri = 650,
666
    SRArr = 651,
667
    SRLXri  = 652,
668
    SRLXrr  = 653,
669
    SRLri = 654,
670
    SRLrr = 655,
671
    STAri = 656,
672
    STArr = 657,
673
    STBAR = 658,
674
    STBAri  = 659,
675
    STBArr  = 660,
676
    STBri = 661,
677
    STBrr = 662,
678
    STCSRri = 663,
679
    STCSRrr = 664,
680
    STCri = 665,
681
    STCrr = 666,
682
    STDAri  = 667,
683
    STDArr  = 668,
684
    STDCQri = 669,
685
    STDCQrr = 670,
686
    STDCri  = 671,
687
    STDCrr  = 672,
688
    STDFAri = 673,
689
    STDFArr = 674,
690
    STDFQri = 675,
691
    STDFQrr = 676,
692
    STDFri  = 677,
693
    STDFrr  = 678,
694
    STDri = 679,
695
    STDrr = 680,
696
    STFAri  = 681,
697
    STFArr  = 682,
698
    STFSRri = 683,
699
    STFSRrr = 684,
700
    STFri = 685,
701
    STFrr = 686,
702
    STHAri  = 687,
703
    STHArr  = 688,
704
    STHri = 689,
705
    STHrr = 690,
706
    STQFAri = 691,
707
    STQFArr = 692,
708
    STQFri  = 693,
709
    STQFrr  = 694,
710
    STXAri  = 695,
711
    STXArr  = 696,
712
    STXFSRri  = 697,
713
    STXFSRrr  = 698,
714
    STXri = 699,
715
    STXrr = 700,
716
    STri  = 701,
717
    STrr  = 702,
718
    SUBCCri = 703,
719
    SUBCCrr = 704,
720
    SUBCri  = 705,
721
    SUBCrr  = 706,
722
    SUBEri  = 707,
723
    SUBErr  = 708,
724
    SUBri = 709,
725
    SUBrr = 710,
726
    SWAPAri = 711,
727
    SWAPArr = 712,
728
    SWAPri  = 713,
729
    SWAPrr  = 714,
730
    TA1 = 715,
731
    TA3 = 716,
732
    TA5 = 717,
733
    TADDCCTVri  = 718,
734
    TADDCCTVrr  = 719,
735
    TADDCCri  = 720,
736
    TADDCCrr  = 721,
737
    TAIL_CALL = 722,
738
    TAIL_CALLri = 723,
739
    TICCri  = 724,
740
    TICCrr  = 725,
741
    TLS_ADDrr = 726,
742
    TLS_CALL  = 727,
743
    TLS_LDXrr = 728,
744
    TLS_LDrr  = 729,
745
    TRAPri  = 730,
746
    TRAPrr  = 731,
747
    TSUBCCTVri  = 732,
748
    TSUBCCTVrr  = 733,
749
    TSUBCCri  = 734,
750
    TSUBCCrr  = 735,
751
    TXCCri  = 736,
752
    TXCCrr  = 737,
753
    UDIVCCri  = 738,
754
    UDIVCCrr  = 739,
755
    UDIVXri = 740,
756
    UDIVXrr = 741,
757
    UDIVri  = 742,
758
    UDIVrr  = 743,
759
    UMACri  = 744,
760
    UMACrr  = 745,
761
    UMULCCri  = 746,
762
    UMULCCrr  = 747,
763
    UMULXHI = 748,
764
    UMULri  = 749,
765
    UMULrr  = 750,
766
    UNIMP = 751,
767
    V9FCMPD = 752,
768
    V9FCMPED  = 753,
769
    V9FCMPEQ  = 754,
770
    V9FCMPES  = 755,
771
    V9FCMPQ = 756,
772
    V9FCMPS = 757,
773
    V9FMOVD_FCC = 758,
774
    V9FMOVQ_FCC = 759,
775
    V9FMOVS_FCC = 760,
776
    V9MOVFCCri  = 761,
777
    V9MOVFCCrr  = 762,
778
    WRASRri = 763,
779
    WRASRrr = 764,
780
    WRPRri  = 765,
781
    WRPRrr  = 766,
782
    WRPSRri = 767,
783
    WRPSRrr = 768,
784
    WRTBRri = 769,
785
    WRTBRrr = 770,
786
    WRWIMri = 771,
787
    WRWIMrr = 772,
788
    XMULX = 773,
789
    XMULXHI = 774,
790
    XNORCCri  = 775,
791
    XNORCCrr  = 776,
792
    XNORri  = 777,
793
    XNORrr  = 778,
794
    XORCCri = 779,
795
    XORCCrr = 780,
796
    XORri = 781,
797
    XORrr = 782,
798
    INSTRUCTION_LIST_END = 783
799
  };
800
801
} // end namespace SP
802
} // end namespace llvm
803
#endif // GET_INSTRINFO_ENUM
804
805
#ifdef GET_INSTRINFO_SCHED_ENUM
806
#undef GET_INSTRINFO_SCHED_ENUM
807
namespace llvm {
808
809
namespace SP {
810
namespace Sched {
811
  enum {
812
    NoInstrModel  = 0,
813
    IIC_iu_instr  = 1,
814
    IIC_fpu_normal_instr  = 2,
815
    IIC_jmp_or_call = 3,
816
    IIC_fpu_abs = 4,
817
    IIC_fpu_fast_instr  = 5,
818
    IIC_fpu_divd  = 6,
819
    IIC_fpu_divs  = 7,
820
    IIC_fpu_muld  = 8,
821
    IIC_fpu_muls  = 9,
822
    IIC_fpu_negs  = 10,
823
    IIC_fpu_sqrtd = 11,
824
    IIC_fpu_sqrts = 12,
825
    IIC_fpu_stod  = 13,
826
    IIC_ldd = 14,
827
    IIC_iu_or_fpu_instr = 15,
828
    IIC_iu_div  = 16,
829
    IIC_smac_umac = 17,
830
    IIC_iu_smul = 18,
831
    IIC_st  = 19,
832
    IIC_std = 20,
833
    IIC_iu_umul = 21,
834
    SCHED_LIST_END = 22
835
  };
836
} // end namespace Sched
837
} // end namespace SP
838
} // end namespace llvm
839
#endif // GET_INSTRINFO_SCHED_ENUM
840
841
#if defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
842
namespace llvm {
843
844
struct SparcInstrTable {
845
  MCInstrDesc Insts[783];
846
  static_assert(alignof(MCInstrDesc) >= alignof(MCOperandInfo), "Unwanted padding between Insts and OperandInfo");
847
  MCOperandInfo OperandInfo[528];
848
  static_assert(alignof(MCOperandInfo) >= alignof(MCPhysReg), "Unwanted padding between OperandInfo and ImplicitOps");
849
  MCPhysReg ImplicitOps[32];
850
};
851
852
} // end namespace llvm
853
#endif // defined(GET_INSTRINFO_MC_DESC) || defined(GET_INSTRINFO_CTOR_DTOR)
854
855
#ifdef GET_INSTRINFO_MC_DESC
856
#undef GET_INSTRINFO_MC_DESC
857
namespace llvm {
858
859
static_assert(sizeof(MCOperandInfo) % sizeof(MCPhysReg) == 0);
860
static constexpr unsigned SparcImpOpBase = sizeof SparcInstrTable::OperandInfo / (sizeof(MCPhysReg));
861
862
extern const SparcInstrTable SparcDescs = {
863
  {
864
    { 782,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #782 = XORrr
865
    { 781,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0, 0x0ULL },  // Inst #781 = XORri
866
    { 780,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #780 = XORCCrr
867
    { 779,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #779 = XORCCri
868
    { 778,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #778 = XNORrr
869
    { 777,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #777 = XNORri
870
    { 776,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #776 = XNORCCrr
871
    { 775,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #775 = XNORCCri
872
    { 774,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #774 = XMULXHI
873
    { 773,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #773 = XMULX
874
    { 772,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 18,  363,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #772 = WRWIMrr
875
    { 771,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 18,  156,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #771 = WRWIMri
876
    { 770,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 17,  363,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #770 = WRTBRrr
877
    { 769,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 17,  156,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #769 = WRTBRri
878
    { 768,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 15,  363,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #768 = WRPSRrr
879
    { 767,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 15,  156,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #767 = WRPSRri
880
    { 766,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 525,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #766 = WRPRrr
881
    { 765,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 522,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #765 = WRPRri
882
    { 764,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 519,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #764 = WRASRrr
883
    { 763,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 516,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #763 = WRASRri
884
    { 762,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 511,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #762 = V9MOVFCCrr
885
    { 761,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 506,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #761 = V9MOVFCCri
886
    { 760,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 501,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #760 = V9FMOVS_FCC
887
    { 759,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 496,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #759 = V9FMOVQ_FCC
888
    { 758,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 491,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #758 = V9FMOVD_FCC
889
    { 757,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 488,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #757 = V9FCMPS
890
    { 756,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 485,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #756 = V9FCMPQ
891
    { 755,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 488,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #755 = V9FCMPES
892
    { 754,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 485,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #754 = V9FCMPEQ
893
    { 753,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 226,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #753 = V9FCMPED
894
    { 752,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 226,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #752 = V9FCMPD
895
    { 751,  1,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #751 = UNIMP
896
    { 750,  3,  1,  4,  21, 0,  1,  SparcImpOpBase + 30,  164,  0, 0x0ULL },  // Inst #750 = UMULrr
897
    { 749,  3,  1,  4,  21, 0,  1,  SparcImpOpBase + 30,  161,  0, 0x0ULL },  // Inst #749 = UMULri
898
    { 748,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #748 = UMULXHI
899
    { 747,  3,  1,  4,  21, 0,  2,  SparcImpOpBase + 28,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #747 = UMULCCrr
900
    { 746,  3,  1,  4,  21, 0,  2,  SparcImpOpBase + 28,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #746 = UMULCCri
901
    { 745,  4,  1,  4,  17, 2,  2,  SparcImpOpBase + 24,  389,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #745 = UMACrr
902
    { 744,  4,  1,  4,  17, 2,  2,  SparcImpOpBase + 24,  385,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #744 = UMACri
903
    { 743,  3,  1,  4,  16, 1,  1,  SparcImpOpBase + 22,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #743 = UDIVrr
904
    { 742,  3,  1,  4,  16, 1,  1,  SparcImpOpBase + 22,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #742 = UDIVri
905
    { 741,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #741 = UDIVXrr
906
    { 740,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #740 = UDIVXri
907
    { 739,  3,  1,  4,  16, 1,  2,  SparcImpOpBase + 19,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #739 = UDIVCCrr
908
    { 738,  3,  1,  4,  16, 1,  2,  SparcImpOpBase + 19,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #738 = UDIVCCri
909
    { 737,  3,  0,  4,  0,  1,  0,  SparcImpOpBase + 4, 382,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #737 = TXCCrr
910
    { 736,  3,  0,  4,  0,  1,  0,  SparcImpOpBase + 4, 478,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #736 = TXCCri
911
    { 735,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #735 = TSUBCCrr
912
    { 734,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #734 = TSUBCCri
913
    { 733,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #733 = TSUBCCTVrr
914
    { 732,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #732 = TSUBCCTVri
915
    { 731,  3,  0,  4,  0,  1,  0,  SparcImpOpBase + 4, 382,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #731 = TRAPrr
916
    { 730,  3,  0,  4,  0,  1,  0,  SparcImpOpBase + 4, 478,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #730 = TRAPri
917
    { 729,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #729 = TLS_LDrr
918
    { 728,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #728 = TLS_LDXrr
919
    { 727,  2,  0,  4,  3,  1,  0,  SparcImpOpBase + 7, 13, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #727 = TLS_CALL
920
    { 726,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 481,  0, 0x0ULL },  // Inst #726 = TLS_ADDrr
921
    { 725,  3,  0,  4,  0,  1,  0,  SparcImpOpBase + 4, 382,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #725 = TICCrr
922
    { 724,  3,  0,  4,  0,  1,  0,  SparcImpOpBase + 4, 478,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #724 = TICCri
923
    { 723,  2,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #723 = TAIL_CALLri
924
    { 722,  1,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #722 = TAIL_CALL
925
    { 721,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #721 = TADDCCrr
926
    { 720,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #720 = TADDCCri
927
    { 719,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #719 = TADDCCTVrr
928
    { 718,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #718 = TADDCCTVri
929
    { 717,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #717 = TA5
930
    { 716,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #716 = TA3
931
    { 715,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #715 = TA1
932
    { 714,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 474,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #714 = SWAPrr
933
    { 713,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 465,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #713 = SWAPri
934
    { 712,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 469,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #712 = SWAPArr
935
    { 711,  4,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 465,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #711 = SWAPAri
936
    { 710,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #710 = SUBrr
937
    { 709,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0, 0x0ULL },  // Inst #709 = SUBri
938
    { 708,  3,  1,  4,  1,  1,  1,  SparcImpOpBase + 5, 164,  0, 0x0ULL },  // Inst #708 = SUBErr
939
    { 707,  3,  1,  4,  1,  1,  1,  SparcImpOpBase + 5, 161,  0, 0x0ULL },  // Inst #707 = SUBEri
940
    { 706,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #706 = SUBCrr
941
    { 705,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #705 = SUBCri
942
    { 704,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::HasPostISelHook), 0x0ULL },  // Inst #704 = SUBCCrr
943
    { 703,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::HasPostISelHook), 0x0ULL },  // Inst #703 = SUBCCri
944
    { 702,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 400,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #702 = STrr
945
    { 701,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 393,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #701 = STri
946
    { 700,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 462,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #700 = STXrr
947
    { 699,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 455,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #699 = STXri
948
    { 698,  2,  1,  4,  1,  0,  1,  SparcImpOpBase + 10,  170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #698 = STXFSRrr
949
    { 697,  2,  1,  4,  1,  0,  1,  SparcImpOpBase + 10,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #697 = STXFSRri
950
    { 696,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 458,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #696 = STXArr
951
    { 695,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 455,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #695 = STXAri
952
    { 694,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 452,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #694 = STQFrr
953
    { 693,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 445,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #693 = STQFri
954
    { 692,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 448,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #692 = STQFArr
955
    { 691,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 445,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #691 = STQFAri
956
    { 690,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 400,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #690 = STHrr
957
    { 689,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 393,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #689 = STHri
958
    { 688,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 396,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #688 = STHArr
959
    { 687,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 393,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #687 = STHAri
960
    { 686,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 442,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #686 = STFrr
961
    { 685,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 435,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #685 = STFri
962
    { 684,  2,  1,  4,  19, 0,  1,  SparcImpOpBase + 10,  170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #684 = STFSRrr
963
    { 683,  2,  1,  4,  19, 0,  1,  SparcImpOpBase + 10,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #683 = STFSRri
964
    { 682,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 438,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #682 = STFArr
965
    { 681,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 435,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #681 = STFAri
966
    { 680,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 432,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #680 = STDrr
967
    { 679,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 409,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #679 = STDri
968
    { 678,  3,  0,  4,  20, 0,  0,  SparcImpOpBase + 0, 429,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #678 = STDFrr
969
    { 677,  3,  0,  4,  20, 0,  0,  SparcImpOpBase + 0, 422,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #677 = STDFri
970
    { 676,  2,  1,  4,  20, 0,  1,  SparcImpOpBase + 16,  170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #676 = STDFQrr
971
    { 675,  2,  1,  4,  20, 0,  1,  SparcImpOpBase + 16,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #675 = STDFQri
972
    { 674,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 425,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #674 = STDFArr
973
    { 673,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 422,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #673 = STDFAri
974
    { 672,  3,  0,  4,  20, 0,  0,  SparcImpOpBase + 0, 419,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #672 = STDCrr
975
    { 671,  3,  0,  4,  20, 0,  0,  SparcImpOpBase + 0, 416,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #671 = STDCri
976
    { 670,  2,  1,  4,  20, 0,  1,  SparcImpOpBase + 31,  170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #670 = STDCQrr
977
    { 669,  2,  1,  4,  20, 0,  1,  SparcImpOpBase + 31,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #669 = STDCQri
978
    { 668,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 412,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #668 = STDArr
979
    { 667,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 409,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #667 = STDAri
980
    { 666,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 406,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #666 = STCrr
981
    { 665,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 403,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #665 = STCri
982
    { 664,  2,  1,  4,  19, 0,  1,  SparcImpOpBase + 9, 170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #664 = STCSRrr
983
    { 663,  2,  1,  4,  19, 0,  1,  SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #663 = STCSRri
984
    { 662,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 400,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #662 = STBrr
985
    { 661,  3,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 393,  0|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #661 = STBri
986
    { 660,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 396,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #660 = STBArr
987
    { 659,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 393,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #659 = STBAri
988
    { 658,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #658 = STBAR
989
    { 657,  4,  0,  4,  19, 0,  0,  SparcImpOpBase + 0, 396,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #657 = STArr
990
    { 656,  3,  0,  4,  19, 1,  0,  SparcImpOpBase + 8, 393,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #656 = STAri
991
    { 655,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #655 = SRLrr
992
    { 654,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 382,  0, 0x0ULL },  // Inst #654 = SRLri
993
    { 653,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 379,  0, 0x0ULL },  // Inst #653 = SRLXrr
994
    { 652,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 376,  0, 0x0ULL },  // Inst #652 = SRLXri
995
    { 651,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #651 = SRArr
996
    { 650,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 382,  0, 0x0ULL },  // Inst #650 = SRAri
997
    { 649,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 379,  0, 0x0ULL },  // Inst #649 = SRAXrr
998
    { 648,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 376,  0, 0x0ULL },  // Inst #648 = SRAXri
999
    { 647,  3,  1,  4,  18, 0,  1,  SparcImpOpBase + 30,  164,  0, 0x0ULL },  // Inst #647 = SMULrr
1000
    { 646,  3,  1,  4,  18, 0,  1,  SparcImpOpBase + 30,  161,  0, 0x0ULL },  // Inst #646 = SMULri
1001
    { 645,  3,  1,  4,  18, 0,  2,  SparcImpOpBase + 28,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #645 = SMULCCrr
1002
    { 644,  3,  1,  4,  18, 0,  2,  SparcImpOpBase + 28,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #644 = SMULCCri
1003
    { 643,  4,  1,  4,  17, 2,  2,  SparcImpOpBase + 24,  389,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #643 = SMACrr
1004
    { 642,  4,  1,  4,  17, 2,  2,  SparcImpOpBase + 24,  385,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #642 = SMACri
1005
    { 641,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #641 = SLLrr
1006
    { 640,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 382,  0, 0x0ULL },  // Inst #640 = SLLri
1007
    { 639,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 379,  0, 0x0ULL },  // Inst #639 = SLLXrr
1008
    { 638,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 376,  0, 0x0ULL },  // Inst #638 = SLLXri
1009
    { 637,  1,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #637 = SIR
1010
    { 636,  0,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #636 = SIAM
1011
    { 635,  0,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #635 = SHUTDOWN
1012
    { 634,  2,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 156,  0, 0x0ULL },  // Inst #634 = SETHIi
1013
    { 633,  3,  1,  4,  16, 1,  1,  SparcImpOpBase + 22,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #633 = SDIVrr
1014
    { 632,  3,  1,  4,  16, 1,  1,  SparcImpOpBase + 22,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #632 = SDIVri
1015
    { 631,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #631 = SDIVXrr
1016
    { 630,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #630 = SDIVXri
1017
    { 629,  3,  1,  4,  16, 1,  2,  SparcImpOpBase + 19,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #629 = SDIVCCrr
1018
    { 628,  3,  1,  4,  16, 1,  2,  SparcImpOpBase + 19,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #628 = SDIVCCri
1019
    { 627,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #627 = SAVErr
1020
    { 626,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #626 = SAVEri
1021
    { 625,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #625 = SAVED
1022
    { 624,  2,  0,  4,  3,  0,  0,  SparcImpOpBase + 0, 170,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #624 = RETTrr
1023
    { 623,  2,  0,  4,  3,  0,  0,  SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #623 = RETTri
1024
    { 622,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #622 = RETRY
1025
    { 621,  1,  0,  4,  3,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #621 = RETL
1026
    { 620,  1,  0,  4,  3,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #620 = RET
1027
    { 619,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #619 = RESTORErr
1028
    { 618,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #618 = RESTOREri
1029
    { 617,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #617 = RESTORED
1030
    { 616,  1,  1,  4,  1,  1,  0,  SparcImpOpBase + 18,  373,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #616 = RDWIM
1031
    { 615,  1,  1,  4,  1,  1,  0,  SparcImpOpBase + 17,  373,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #615 = RDTBR
1032
    { 614,  1,  1,  4,  1,  1,  0,  SparcImpOpBase + 15,  373,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #614 = RDPSR
1033
    { 613,  2,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 374,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #613 = RDPR
1034
    { 612,  1,  1,  4,  1,  1,  0,  SparcImpOpBase + 16,  373,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #612 = RDFQ
1035
    { 611,  2,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 371,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #611 = RDASR
1036
    { 610,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 15,  363,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #610 = PWRPSRrr
1037
    { 609,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 15,  156,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #609 = PWRPSRri
1038
    { 608,  3,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 368,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #608 = PREFETCHr
1039
    { 607,  3,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 365,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #607 = PREFETCHi
1040
    { 606,  2,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 363,  0, 0x0ULL },  // Inst #606 = POPCrr
1041
    { 605,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #605 = PDISTN
1042
    { 604,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #604 = PDIST
1043
    { 603,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #603 = ORrr
1044
    { 602,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0, 0x0ULL },  // Inst #602 = ORri
1045
    { 601,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #601 = ORNrr
1046
    { 600,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #600 = ORNri
1047
    { 599,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #599 = ORNCCrr
1048
    { 598,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #598 = ORNCCri
1049
    { 597,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #597 = ORCCrr
1050
    { 596,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #596 = ORCCri
1051
    { 595,  0,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #595 = NOP
1052
    { 594,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 167,  0, 0x0ULL },  // Inst #594 = MULXrr
1053
    { 593,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0, 0x0ULL },  // Inst #593 = MULXri
1054
    { 592,  3,  1,  4,  1,  2,  2,  SparcImpOpBase + 11,  164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #592 = MULSCCrr
1055
    { 591,  3,  1,  4,  1,  2,  2,  SparcImpOpBase + 11,  161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #591 = MULSCCri
1056
    { 590,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 361,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #590 = MOVXTOD
1057
    { 589,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 347,  0, 0x0ULL },  // Inst #589 = MOVXCCrr
1058
    { 588,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 343,  0, 0x0ULL },  // Inst #588 = MOVXCCri
1059
    { 587,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 361,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #587 = MOVWTOS
1060
    { 586,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 341,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #586 = MOVSTOUW
1061
    { 585,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 341,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #585 = MOVSTOSW
1062
    { 584,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 356,  0, 0x0ULL },  // Inst #584 = MOVRrr
1063
    { 583,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 351,  0, 0x0ULL },  // Inst #583 = MOVRri
1064
    { 582,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 347,  0, 0x0ULL },  // Inst #582 = MOVICCrr
1065
    { 581,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 343,  0, 0x0ULL },  // Inst #581 = MOVICCri
1066
    { 580,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 347,  0, 0x0ULL },  // Inst #580 = MOVFCCrr
1067
    { 579,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 343,  0, 0x0ULL },  // Inst #579 = MOVFCCri
1068
    { 578,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 341,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #578 = MOVDTOX
1069
    { 577,  1,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #577 = MEMBARi
1070
    { 576,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 339,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #576 = LZCNT
1071
    { 575,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #575 = LDrr
1072
    { 574,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #574 = LDri
1073
    { 573,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 336,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #573 = LDXrr
1074
    { 572,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 333,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #572 = LDXri
1075
    { 571,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 10,  170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #571 = LDXFSRrr
1076
    { 570,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 10,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #570 = LDXFSRri
1077
    { 569,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 267,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #569 = LDXArr
1078
    { 568,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 333,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #568 = LDXAri
1079
    { 567,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #567 = LDUHrr
1080
    { 566,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #566 = LDUHri
1081
    { 565,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #565 = LDUHArr
1082
    { 564,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #564 = LDUHAri
1083
    { 563,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #563 = LDUBrr
1084
    { 562,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #562 = LDUBri
1085
    { 561,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #561 = LDUBArr
1086
    { 560,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #560 = LDUBAri
1087
    { 559,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 336,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #559 = LDSWrr
1088
    { 558,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 333,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #558 = LDSWri
1089
    { 557,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 267,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #557 = LDSWArr
1090
    { 556,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 333,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #556 = LDSWAri
1091
    { 555,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #555 = LDSTUBrr
1092
    { 554,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #554 = LDSTUBri
1093
    { 553,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #553 = LDSTUBArr
1094
    { 552,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #552 = LDSTUBAri
1095
    { 551,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #551 = LDSHrr
1096
    { 550,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #550 = LDSHri
1097
    { 549,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #549 = LDSHArr
1098
    { 548,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #548 = LDSHAri
1099
    { 547,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #547 = LDSBrr
1100
    { 546,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #546 = LDSBri
1101
    { 545,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #545 = LDSBArr
1102
    { 544,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #544 = LDSBAri
1103
    { 543,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 330,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #543 = LDQFrr
1104
    { 542,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 323,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #542 = LDQFri
1105
    { 541,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 326,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #541 = LDQFArr
1106
    { 540,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 323,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #540 = LDQFAri
1107
    { 539,  3,  1,  4,  15, 0,  0,  SparcImpOpBase + 0, 320,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #539 = LDFrr
1108
    { 538,  3,  1,  4,  15, 0,  0,  SparcImpOpBase + 0, 313,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #538 = LDFri
1109
    { 537,  2,  0,  4,  15, 0,  1,  SparcImpOpBase + 10,  170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #537 = LDFSRrr
1110
    { 536,  2,  0,  4,  15, 0,  1,  SparcImpOpBase + 10,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #536 = LDFSRri
1111
    { 535,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 316,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #535 = LDFArr
1112
    { 534,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 313,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #534 = LDFAri
1113
    { 533,  3,  1,  4,  14, 0,  0,  SparcImpOpBase + 0, 310,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #533 = LDDrr
1114
    { 532,  3,  1,  4,  14, 0,  0,  SparcImpOpBase + 0, 287,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #532 = LDDri
1115
    { 531,  3,  1,  4,  14, 0,  0,  SparcImpOpBase + 0, 307,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #531 = LDDFrr
1116
    { 530,  3,  1,  4,  14, 0,  0,  SparcImpOpBase + 0, 300,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #530 = LDDFri
1117
    { 529,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 303,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #529 = LDDFArr
1118
    { 528,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 300,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #528 = LDDFAri
1119
    { 527,  3,  1,  4,  14, 0,  0,  SparcImpOpBase + 0, 297,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #527 = LDDCrr
1120
    { 526,  3,  1,  4,  14, 0,  0,  SparcImpOpBase + 0, 294,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #526 = LDDCri
1121
    { 525,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 290,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #525 = LDDArr
1122
    { 524,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 287,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #524 = LDDAri
1123
    { 523,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 284,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #523 = LDCrr
1124
    { 522,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 281,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #522 = LDCri
1125
    { 521,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 9, 170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #521 = LDCSRrr
1126
    { 520,  2,  0,  4,  1,  0,  1,  SparcImpOpBase + 9, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #520 = LDCSRri
1127
    { 519,  4,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #519 = LDArr
1128
    { 518,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 8, 275,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #518 = LDAri
1129
    { 517,  3,  1,  4,  3,  0,  0,  SparcImpOpBase + 0, 278,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #517 = JMPLrr
1130
    { 516,  3,  1,  4,  3,  0,  0,  SparcImpOpBase + 0, 275,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #516 = JMPLri
1131
    { 515,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 271,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #515 = GDOP_LDrr
1132
    { 514,  4,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 267,  0|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #514 = GDOP_LDXrr
1133
    { 513,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 258,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #513 = FZEROS
1134
    { 512,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 256,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #512 = FZERO
1135
    { 511,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 218,  0, 0x0ULL },  // Inst #511 = FXTOS
1136
    { 510,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 220,  0, 0x0ULL },  // Inst #510 = FXTOQ
1137
    { 509,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0, 0x0ULL },  // Inst #509 = FXTOD
1138
    { 508,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #508 = FXORS
1139
    { 507,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #507 = FXOR
1140
    { 506,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #506 = FXNORS
1141
    { 505,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #505 = FXNOR
1142
    { 504,  3,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #504 = FSUBS
1143
    { 503,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 206,  0, 0x0ULL },  // Inst #503 = FSUBQ
1144
    { 502,  3,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 178,  0, 0x0ULL },  // Inst #502 = FSUBD
1145
    { 501,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 222,  0, 0x0ULL },  // Inst #501 = FSTOX
1146
    { 500,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 224,  0, 0x0ULL },  // Inst #500 = FSTOQ
1147
    { 499,  2,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 204,  0, 0x0ULL },  // Inst #499 = FSTOI
1148
    { 498,  2,  1,  4,  13, 0,  0,  SparcImpOpBase + 0, 222,  0, 0x0ULL },  // Inst #498 = FSTOD
1149
    { 497,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #497 = FSRL32
1150
    { 496,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #496 = FSRL16
1151
    { 495,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 204,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #495 = FSRC2S
1152
    { 494,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #494 = FSRC2
1153
    { 493,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 204,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #493 = FSRC1S
1154
    { 492,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #492 = FSRC1
1155
    { 491,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #491 = FSRA32
1156
    { 490,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #490 = FSRA16
1157
    { 489,  2,  1,  4,  12, 0,  0,  SparcImpOpBase + 0, 204,  0, 0x0ULL },  // Inst #489 = FSQRTS
1158
    { 488,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #488 = FSQRTQ
1159
    { 487,  2,  1,  4,  11, 0,  0,  SparcImpOpBase + 0, 200,  0, 0x0ULL },  // Inst #487 = FSQRTD
1160
    { 486,  3,  1,  4,  8,  0,  0,  SparcImpOpBase + 0, 264,  0, 0x0ULL },  // Inst #486 = FSMULD
1161
    { 485,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #485 = FSLL32
1162
    { 484,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #484 = FSLL16
1163
    { 483,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #483 = FSLAS32
1164
    { 482,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #482 = FSLAS16
1165
    { 481,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 260,  0, 0x0ULL },  // Inst #481 = FQTOX
1166
    { 480,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 262,  0, 0x0ULL },  // Inst #480 = FQTOS
1167
    { 479,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 262,  0, 0x0ULL },  // Inst #479 = FQTOI
1168
    { 478,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 260,  0, 0x0ULL },  // Inst #478 = FQTOD
1169
    { 477,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #477 = FPSUB32S
1170
    { 476,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #476 = FPSUB32
1171
    { 475,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #475 = FPSUB16S
1172
    { 474,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #474 = FPSUB16
1173
    { 473,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #473 = FPMERGE
1174
    { 472,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #472 = FPADD64
1175
    { 471,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #471 = FPADD32S
1176
    { 470,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #470 = FPADD32
1177
    { 469,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #469 = FPADD16S
1178
    { 468,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #468 = FPADD16
1179
    { 467,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #467 = FPACKFIX
1180
    { 466,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #466 = FPACK32
1181
    { 465,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #465 = FPACK16
1182
    { 464,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #464 = FORS
1183
    { 463,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #463 = FORNOT2S
1184
    { 462,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #462 = FORNOT2
1185
    { 461,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #461 = FORNOT1S
1186
    { 460,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #460 = FORNOT1
1187
    { 459,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #459 = FOR
1188
    { 458,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 258,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #458 = FONES
1189
    { 457,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 256,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #457 = FONE
1190
    { 456,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #456 = FNSMULD
1191
    { 455,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 204,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #455 = FNOT2S
1192
    { 454,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #454 = FNOT2
1193
    { 453,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 204,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #453 = FNOT1S
1194
    { 452,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #452 = FNOT1
1195
    { 451,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #451 = FNORS
1196
    { 450,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #450 = FNOR
1197
    { 449,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #449 = FNMULS
1198
    { 448,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #448 = FNMULD
1199
    { 447,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #447 = FNHADDS
1200
    { 446,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #446 = FNHADDD
1201
    { 445,  2,  1,  4,  10, 0,  0,  SparcImpOpBase + 0, 204,  0, 0x0ULL },  // Inst #445 = FNEGS
1202
    { 444,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #444 = FNEGQ
1203
    { 443,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0, 0x0ULL },  // Inst #443 = FNEGD
1204
    { 442,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #442 = FNANDS
1205
    { 441,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #441 = FNAND
1206
    { 440,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #440 = FNADDS
1207
    { 439,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #439 = FNADDD
1208
    { 438,  3,  1,  4,  9,  0,  0,  SparcImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #438 = FMULS
1209
    { 437,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 206,  0, 0x0ULL },  // Inst #437 = FMULQ
1210
    { 436,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #436 = FMULD8ULX16
1211
    { 435,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #435 = FMULD8SUX16
1212
    { 434,  3,  1,  4,  8,  0,  0,  SparcImpOpBase + 0, 178,  0, 0x0ULL },  // Inst #434 = FMULD
1213
    { 433,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #433 = FMUL8X16AU
1214
    { 432,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #432 = FMUL8X16AL
1215
    { 431,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #431 = FMUL8X16
1216
    { 430,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #430 = FMUL8ULX16
1217
    { 429,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #429 = FMUL8SUX16
1218
    { 428,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 252,  0, 0x0ULL },  // Inst #428 = FMOVS_XCC
1219
    { 427,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 252,  0, 0x0ULL },  // Inst #427 = FMOVS_ICC
1220
    { 426,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 252,  0, 0x0ULL },  // Inst #426 = FMOVS_FCC
1221
    { 425,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 204,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #425 = FMOVS
1222
    { 424,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 247,  0, 0x0ULL },  // Inst #424 = FMOVRS
1223
    { 423,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 242,  0, 0x0ULL },  // Inst #423 = FMOVRQ
1224
    { 422,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 237,  0, 0x0ULL },  // Inst #422 = FMOVRD
1225
    { 421,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 233,  0, 0x0ULL },  // Inst #421 = FMOVQ_XCC
1226
    { 420,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 233,  0, 0x0ULL },  // Inst #420 = FMOVQ_ICC
1227
    { 419,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 233,  0, 0x0ULL },  // Inst #419 = FMOVQ_FCC
1228
    { 418,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 202,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #418 = FMOVQ
1229
    { 417,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 229,  0, 0x0ULL },  // Inst #417 = FMOVD_XCC
1230
    { 416,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 229,  0, 0x0ULL },  // Inst #416 = FMOVD_ICC
1231
    { 415,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 229,  0, 0x0ULL },  // Inst #415 = FMOVD_FCC
1232
    { 414,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #414 = FMOVD
1233
    { 413,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #413 = FMEAN16
1234
    { 412,  2,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 170,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #412 = FLUSHrr
1235
    { 411,  2,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #411 = FLUSHri
1236
    { 410,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #410 = FLUSHW
1237
    { 409,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #409 = FLUSH
1238
    { 408,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 226,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #408 = FLCMPS
1239
    { 407,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 226,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #407 = FLCMPD
1240
    { 406,  2,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 204,  0, 0x0ULL },  // Inst #406 = FITOS
1241
    { 405,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 224,  0, 0x0ULL },  // Inst #405 = FITOQ
1242
    { 404,  2,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 222,  0, 0x0ULL },  // Inst #404 = FITOD
1243
    { 403,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #403 = FHSUBS
1244
    { 402,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #402 = FHSUBD
1245
    { 401,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #401 = FHADDS
1246
    { 400,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #400 = FHADDD
1247
    { 399,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #399 = FEXPAND
1248
    { 398,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0, 0x0ULL },  // Inst #398 = FDTOX
1249
    { 397,  2,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 218,  0, 0x0ULL },  // Inst #397 = FDTOS
1250
    { 396,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 220,  0, 0x0ULL },  // Inst #396 = FDTOQ
1251
    { 395,  2,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 218,  0, 0x0ULL },  // Inst #395 = FDTOI
1252
    { 394,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 215,  0, 0x0ULL },  // Inst #394 = FDMULQ
1253
    { 393,  3,  1,  4,  7,  0,  0,  SparcImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #393 = FDIVS
1254
    { 392,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 206,  0, 0x0ULL },  // Inst #392 = FDIVQ
1255
    { 391,  3,  1,  4,  6,  0,  0,  SparcImpOpBase + 0, 178,  0, 0x0ULL },  // Inst #391 = FDIVD
1256
    { 390,  2,  0,  4,  5,  0,  1,  SparcImpOpBase + 3, 204,  0, 0x0ULL },  // Inst #390 = FCMPS_V9
1257
    { 389,  2,  0,  4,  5,  0,  1,  SparcImpOpBase + 3, 204,  0, 0x0ULL },  // Inst #389 = FCMPS
1258
    { 388,  2,  0,  4,  0,  0,  1,  SparcImpOpBase + 3, 202,  0, 0x0ULL },  // Inst #388 = FCMPQ_V9
1259
    { 387,  2,  0,  4,  0,  0,  1,  SparcImpOpBase + 3, 202,  0, 0x0ULL },  // Inst #387 = FCMPQ
1260
    { 386,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #386 = FCMPNE32
1261
    { 385,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #385 = FCMPNE16
1262
    { 384,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #384 = FCMPLE32
1263
    { 383,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #383 = FCMPLE16
1264
    { 382,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #382 = FCMPGT32
1265
    { 381,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #381 = FCMPGT16
1266
    { 380,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #380 = FCMPEQ32
1267
    { 379,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 212,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #379 = FCMPEQ16
1268
    { 378,  2,  0,  4,  5,  0,  1,  SparcImpOpBase + 3, 200,  0, 0x0ULL },  // Inst #378 = FCMPD_V9
1269
    { 377,  2,  0,  4,  5,  0,  1,  SparcImpOpBase + 3, 200,  0, 0x0ULL },  // Inst #377 = FCMPD
1270
    { 376,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #376 = FCHKSM16
1271
    { 375,  2,  0,  4,  2,  1,  0,  SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #375 = FBCOND_V9
1272
    { 374,  2,  0,  4,  2,  1,  0,  SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #374 = FBCONDA_V9
1273
    { 373,  2,  0,  4,  2,  1,  0,  SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #373 = FBCONDA
1274
    { 372,  2,  0,  4,  2,  1,  0,  SparcImpOpBase + 3, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #372 = FBCOND
1275
    { 371,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #371 = FANDS
1276
    { 370,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #370 = FANDNOT2S
1277
    { 369,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #369 = FANDNOT2
1278
    { 368,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 209,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #368 = FANDNOT1S
1279
    { 367,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #367 = FANDNOT1
1280
    { 366,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #366 = FAND
1281
    { 365,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #365 = FALIGNADATA
1282
    { 364,  3,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 209,  0, 0x0ULL },  // Inst #364 = FADDS
1283
    { 363,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 206,  0, 0x0ULL },  // Inst #363 = FADDQ
1284
    { 362,  3,  1,  4,  5,  0,  0,  SparcImpOpBase + 0, 178,  0, 0x0ULL },  // Inst #362 = FADDD
1285
    { 361,  2,  1,  4,  4,  0,  0,  SparcImpOpBase + 0, 204,  0, 0x0ULL },  // Inst #361 = FABSS
1286
    { 360,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 202,  0, 0x0ULL },  // Inst #360 = FABSQ
1287
    { 359,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 200,  0, 0x0ULL },  // Inst #359 = FABSD
1288
    { 358,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #358 = EDGE8N
1289
    { 357,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #357 = EDGE8LN
1290
    { 356,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #356 = EDGE8L
1291
    { 355,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #355 = EDGE8
1292
    { 354,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #354 = EDGE32N
1293
    { 353,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #353 = EDGE32LN
1294
    { 352,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #352 = EDGE32L
1295
    { 351,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #351 = EDGE32
1296
    { 350,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #350 = EDGE16N
1297
    { 349,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #349 = EDGE16LN
1298
    { 348,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #348 = EDGE16L
1299
    { 347,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #347 = EDGE16
1300
    { 346,  0,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #346 = DONE
1301
    { 345,  1,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 199,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #345 = CMASK8
1302
    { 344,  1,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 199,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #344 = CMASK32
1303
    { 343,  1,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 199,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #343 = CMASK16
1304
    { 342,  2,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #342 = CBCONDA
1305
    { 341,  2,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #341 = CBCOND
1306
    { 340,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 194,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #340 = CASXArr
1307
    { 339,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 8, 190,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #339 = CASXAri
1308
    { 338,  5,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 185,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #338 = CASArr
1309
    { 337,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 8, 181,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #337 = CASAri
1310
    { 336,  2,  0,  4,  3,  1,  0,  SparcImpOpBase + 7, 170,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #336 = CALLrr
1311
    { 335,  2,  0,  4,  3,  1,  0,  SparcImpOpBase + 7, 35, 0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #335 = CALLri
1312
    { 334,  1,  0,  4,  3,  1,  0,  SparcImpOpBase + 7, 0,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #334 = CALL
1313
    { 333,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 178,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #333 = BSHUFFLE
1314
    { 332,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #332 = BPXCCNT
1315
    { 331,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #331 = BPXCCANT
1316
    { 330,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #330 = BPXCCA
1317
    { 329,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #329 = BPXCC
1318
    { 328,  3,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 175,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #328 = BPRNT
1319
    { 327,  3,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 175,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #327 = BPRANT
1320
    { 326,  3,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 175,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #326 = BPRA
1321
    { 325,  3,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 175,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #325 = BPR
1322
    { 324,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #324 = BPICCNT
1323
    { 323,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #323 = BPICCANT
1324
    { 322,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #322 = BPICCA
1325
    { 321,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #321 = BPICC
1326
    { 320,  3,  0,  4,  2,  0,  0,  SparcImpOpBase + 0, 172,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #320 = BPFCCNT
1327
    { 319,  3,  0,  4,  2,  0,  0,  SparcImpOpBase + 0, 172,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #319 = BPFCCANT
1328
    { 318,  3,  0,  4,  2,  0,  0,  SparcImpOpBase + 0, 172,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #318 = BPFCCA
1329
    { 317,  3,  0,  4,  2,  0,  0,  SparcImpOpBase + 0, 172,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #317 = BPFCC
1330
    { 316,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #316 = BMASK
1331
    { 315,  2,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 170,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #315 = BINDrr
1332
    { 314,  2,  0,  4,  1,  0,  0,  SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #314 = BINDri
1333
    { 313,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #313 = BCONDA
1334
    { 312,  2,  0,  4,  1,  1,  0,  SparcImpOpBase + 4, 13, 0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #312 = BCOND
1335
    { 311,  1,  0,  4,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #311 = BA
1336
    { 310,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #310 = ARRAY8
1337
    { 309,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #309 = ARRAY32
1338
    { 308,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #308 = ARRAY16
1339
    { 307,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #307 = ANDrr
1340
    { 306,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0, 0x0ULL },  // Inst #306 = ANDri
1341
    { 305,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #305 = ANDNrr
1342
    { 304,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #304 = ANDNri
1343
    { 303,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #303 = ANDNCCrr
1344
    { 302,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #302 = ANDNCCri
1345
    { 301,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #301 = ANDCCrr
1346
    { 300,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #300 = ANDCCri
1347
    { 299,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #299 = ALIGNADDRL
1348
    { 298,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #298 = ALIGNADDR
1349
    { 297,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 164,  0, 0x0ULL },  // Inst #297 = ADDrr
1350
    { 296,  3,  1,  4,  1,  0,  0,  SparcImpOpBase + 0, 161,  0, 0x0ULL },  // Inst #296 = ADDri
1351
    { 295,  3,  1,  4,  0,  1,  1,  SparcImpOpBase + 5, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #295 = ADDXCCC
1352
    { 294,  3,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 167,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #294 = ADDXC
1353
    { 293,  3,  1,  4,  1,  1,  1,  SparcImpOpBase + 5, 164,  0, 0x0ULL },  // Inst #293 = ADDErr
1354
    { 292,  3,  1,  4,  1,  1,  1,  SparcImpOpBase + 5, 161,  0, 0x0ULL },  // Inst #292 = ADDEri
1355
    { 291,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 4, 164,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #291 = ADDCrr
1356
    { 290,  3,  1,  4,  1,  1,  0,  SparcImpOpBase + 4, 161,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #290 = ADDCri
1357
    { 289,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 164,  0, 0x0ULL },  // Inst #289 = ADDCCrr
1358
    { 288,  3,  1,  4,  1,  0,  1,  SparcImpOpBase + 4, 161,  0, 0x0ULL },  // Inst #288 = ADDCCri
1359
    { 287,  3,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 158,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #287 = SETX
1360
    { 286,  2,  1,  4,  0,  0,  0,  SparcImpOpBase + 0, 156,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #286 = SET
1361
    { 285,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 152,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #285 = SELECT_CC_QFP_XCC
1362
    { 284,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 152,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #284 = SELECT_CC_QFP_ICC
1363
    { 283,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 152,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #283 = SELECT_CC_QFP_FCC
1364
    { 282,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #282 = SELECT_CC_Int_XCC
1365
    { 281,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #281 = SELECT_CC_Int_ICC
1366
    { 280,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 148,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #280 = SELECT_CC_Int_FCC
1367
    { 279,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #279 = SELECT_CC_FP_XCC
1368
    { 278,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #278 = SELECT_CC_FP_ICC
1369
    { 277,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 144,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #277 = SELECT_CC_FP_FCC
1370
    { 276,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #276 = SELECT_CC_DFP_XCC
1371
    { 275,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 4, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #275 = SELECT_CC_DFP_ICC
1372
    { 274,  4,  1,  4,  0,  1,  0,  SparcImpOpBase + 3, 140,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL },  // Inst #274 = SELECT_CC_DFP_FCC
1373
    { 273,  1,  1,  4,  0,  0,  1,  SparcImpOpBase + 2, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #273 = GETPCX
1374
    { 272,  2,  0,  4,  0,  1,  1,  SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #272 = ADJCALLSTACKUP
1375
    { 271,  2,  0,  4,  0,  1,  1,  SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #271 = ADJCALLSTACKDOWN
1376
    { 270,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #270 = G_UBFX
1377
    { 269,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 136,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #269 = G_SBFX
1378
    { 268,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #268 = G_VECREDUCE_UMIN
1379
    { 267,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #267 = G_VECREDUCE_UMAX
1380
    { 266,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #266 = G_VECREDUCE_SMIN
1381
    { 265,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #265 = G_VECREDUCE_SMAX
1382
    { 264,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #264 = G_VECREDUCE_XOR
1383
    { 263,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #263 = G_VECREDUCE_OR
1384
    { 262,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #262 = G_VECREDUCE_AND
1385
    { 261,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #261 = G_VECREDUCE_MUL
1386
    { 260,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #260 = G_VECREDUCE_ADD
1387
    { 259,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #259 = G_VECREDUCE_FMINIMUM
1388
    { 258,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #258 = G_VECREDUCE_FMAXIMUM
1389
    { 257,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #257 = G_VECREDUCE_FMIN
1390
    { 256,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #256 = G_VECREDUCE_FMAX
1391
    { 255,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #255 = G_VECREDUCE_FMUL
1392
    { 254,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #254 = G_VECREDUCE_FADD
1393
    { 253,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #253 = G_VECREDUCE_SEQ_FMUL
1394
    { 252,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #252 = G_VECREDUCE_SEQ_FADD
1395
    { 251,  3,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #251 = G_BZERO
1396
    { 250,  4,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #250 = G_MEMSET
1397
    { 249,  4,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #249 = G_MEMMOVE
1398
    { 248,  3,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #248 = G_MEMCPY_INLINE
1399
    { 247,  4,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 132,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #247 = G_MEMCPY
1400
    { 246,  2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 130,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #246 = G_WRITE_REGISTER
1401
    { 245,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #245 = G_READ_REGISTER
1402
    { 244,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #244 = G_STRICT_FLDEXP
1403
    { 243,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #243 = G_STRICT_FSQRT
1404
    { 242,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #242 = G_STRICT_FMA
1405
    { 241,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #241 = G_STRICT_FREM
1406
    { 240,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #240 = G_STRICT_FDIV
1407
    { 239,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #239 = G_STRICT_FMUL
1408
    { 238,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #238 = G_STRICT_FSUB
1409
    { 237,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayRaiseFPException)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #237 = G_STRICT_FADD
1410
    { 236,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #236 = G_STACKRESTORE
1411
    { 235,  1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #235 = G_STACKSAVE
1412
    { 234,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #234 = G_DYN_STACKALLOC
1413
    { 233,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #233 = G_JUMP_TABLE
1414
    { 232,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #232 = G_BLOCK_ADDR
1415
    { 231,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #231 = G_ADDRSPACE_CAST
1416
    { 230,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #230 = G_FNEARBYINT
1417
    { 229,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #229 = G_FRINT
1418
    { 228,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #228 = G_FFLOOR
1419
    { 227,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #227 = G_FSQRT
1420
    { 226,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #226 = G_FSIN
1421
    { 225,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #225 = G_FCOS
1422
    { 224,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #224 = G_FCEIL
1423
    { 223,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #223 = G_BITREVERSE
1424
    { 222,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #222 = G_BSWAP
1425
    { 221,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #221 = G_CTPOP
1426
    { 220,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #220 = G_CTLZ_ZERO_UNDEF
1427
    { 219,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #219 = G_CTLZ
1428
    { 218,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #218 = G_CTTZ_ZERO_UNDEF
1429
    { 217,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #217 = G_CTTZ
1430
    { 216,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 126,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #216 = G_SHUFFLE_VECTOR
1431
    { 215,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 123,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #215 = G_EXTRACT_VECTOR_ELT
1432
    { 214,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 119,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #214 = G_INSERT_VECTOR_ELT
1433
    { 213,  3,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 116,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #213 = G_BRJT
1434
    { 212,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #212 = G_BR
1435
    { 211,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #211 = G_LLROUND
1436
    { 210,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #210 = G_LROUND
1437
    { 209,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #209 = G_ABS
1438
    { 208,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #208 = G_UMAX
1439
    { 207,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #207 = G_UMIN
1440
    { 206,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #206 = G_SMAX
1441
    { 205,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #205 = G_SMIN
1442
    { 204,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #204 = G_PTRMASK
1443
    { 203,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #203 = G_PTR_ADD
1444
    { 202,  0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #202 = G_RESET_FPMODE
1445
    { 201,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #201 = G_SET_FPMODE
1446
    { 200,  1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #200 = G_GET_FPMODE
1447
    { 199,  0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #199 = G_RESET_FPENV
1448
    { 198,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #198 = G_SET_FPENV
1449
    { 197,  1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #197 = G_GET_FPENV
1450
    { 196,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #196 = G_FMAXIMUM
1451
    { 195,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #195 = G_FMINIMUM
1452
    { 194,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #194 = G_FMAXNUM_IEEE
1453
    { 193,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #193 = G_FMINNUM_IEEE
1454
    { 192,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #192 = G_FMAXNUM
1455
    { 191,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #191 = G_FMINNUM
1456
    { 190,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #190 = G_FCANONICALIZE
1457
    { 189,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #189 = G_IS_FPCLASS
1458
    { 188,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #188 = G_FCOPYSIGN
1459
    { 187,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #187 = G_FABS
1460
    { 186,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #186 = G_UITOFP
1461
    { 185,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #185 = G_SITOFP
1462
    { 184,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #184 = G_FPTOUI
1463
    { 183,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #183 = G_FPTOSI
1464
    { 182,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #182 = G_FPTRUNC
1465
    { 181,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #181 = G_FPEXT
1466
    { 180,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #180 = G_FNEG
1467
    { 179,  3,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #179 = G_FFREXP
1468
    { 178,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #178 = G_FLDEXP
1469
    { 177,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #177 = G_FLOG10
1470
    { 176,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #176 = G_FLOG2
1471
    { 175,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #175 = G_FLOG
1472
    { 174,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #174 = G_FEXP10
1473
    { 173,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #173 = G_FEXP2
1474
    { 172,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #172 = G_FEXP
1475
    { 171,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #171 = G_FPOWI
1476
    { 170,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #170 = G_FPOW
1477
    { 169,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #169 = G_FREM
1478
    { 168,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #168 = G_FDIV
1479
    { 167,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #167 = G_FMAD
1480
    { 166,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #166 = G_FMA
1481
    { 165,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #165 = G_FMUL
1482
    { 164,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #164 = G_FSUB
1483
    { 163,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #163 = G_FADD
1484
    { 162,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #162 = G_UDIVFIXSAT
1485
    { 161,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #161 = G_SDIVFIXSAT
1486
    { 160,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #160 = G_UDIVFIX
1487
    { 159,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #159 = G_SDIVFIX
1488
    { 158,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #158 = G_UMULFIXSAT
1489
    { 157,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #157 = G_SMULFIXSAT
1490
    { 156,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #156 = G_UMULFIX
1491
    { 155,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 112,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #155 = G_SMULFIX
1492
    { 154,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #154 = G_SSHLSAT
1493
    { 153,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #153 = G_USHLSAT
1494
    { 152,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #152 = G_SSUBSAT
1495
    { 151,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #151 = G_USUBSAT
1496
    { 150,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #150 = G_SADDSAT
1497
    { 149,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #149 = G_UADDSAT
1498
    { 148,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #148 = G_SMULH
1499
    { 147,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #147 = G_UMULH
1500
    { 146,  4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #146 = G_SMULO
1501
    { 145,  4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #145 = G_UMULO
1502
    { 144,  5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #144 = G_SSUBE
1503
    { 143,  4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #143 = G_SSUBO
1504
    { 142,  5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #142 = G_SADDE
1505
    { 141,  4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #141 = G_SADDO
1506
    { 140,  5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #140 = G_USUBE
1507
    { 139,  4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #139 = G_USUBO
1508
    { 138,  5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 107,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #138 = G_UADDE
1509
    { 137,  4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #137 = G_UADDO
1510
    { 136,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #136 = G_SELECT
1511
    { 135,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #135 = G_FCMP
1512
    { 134,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 103,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #134 = G_ICMP
1513
    { 133,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #133 = G_ROTL
1514
    { 132,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #132 = G_ROTR
1515
    { 131,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #131 = G_FSHR
1516
    { 130,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 99, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #130 = G_FSHL
1517
    { 129,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #129 = G_ASHR
1518
    { 128,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #128 = G_LSHR
1519
    { 127,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 96, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #127 = G_SHL
1520
    { 126,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #126 = G_ZEXT
1521
    { 125,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #125 = G_SEXT_INREG
1522
    { 124,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #124 = G_SEXT
1523
    { 123,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 93, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #123 = G_VAARG
1524
    { 122,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #122 = G_VASTART
1525
    { 121,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #121 = G_FCONSTANT
1526
    { 120,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #120 = G_CONSTANT
1527
    { 119,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #119 = G_TRUNC
1528
    { 118,  2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #118 = G_ANYEXT
1529
    { 117,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #117 = G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
1530
    { 116,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::Convergent), 0x0ULL },  // Inst #116 = G_INTRINSIC_CONVERGENT
1531
    { 115,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #115 = G_INTRINSIC_W_SIDE_EFFECTS
1532
    { 114,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #114 = G_INTRINSIC
1533
    { 113,  0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #113 = G_INVOKE_REGION_START
1534
    { 112,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #112 = G_BRINDIRECT
1535
    { 111,  2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x0ULL },  // Inst #111 = G_BRCOND
1536
    { 110,  4,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 89, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #110 = G_PREFETCH
1537
    { 109,  2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #109 = G_FENCE
1538
    { 108,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #108 = G_ATOMICRMW_UDEC_WRAP
1539
    { 107,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #107 = G_ATOMICRMW_UINC_WRAP
1540
    { 106,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #106 = G_ATOMICRMW_FMIN
1541
    { 105,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #105 = G_ATOMICRMW_FMAX
1542
    { 104,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #104 = G_ATOMICRMW_FSUB
1543
    { 103,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #103 = G_ATOMICRMW_FADD
1544
    { 102,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #102 = G_ATOMICRMW_UMIN
1545
    { 101,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #101 = G_ATOMICRMW_UMAX
1546
    { 100,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #100 = G_ATOMICRMW_MIN
1547
    { 99, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #99 = G_ATOMICRMW_MAX
1548
    { 98, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #98 = G_ATOMICRMW_XOR
1549
    { 97, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #97 = G_ATOMICRMW_OR
1550
    { 96, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #96 = G_ATOMICRMW_NAND
1551
    { 95, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #95 = G_ATOMICRMW_AND
1552
    { 94, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #94 = G_ATOMICRMW_SUB
1553
    { 93, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #93 = G_ATOMICRMW_ADD
1554
    { 92, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 86, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #92 = G_ATOMICRMW_XCHG
1555
    { 91, 4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 82, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #91 = G_ATOMIC_CMPXCHG
1556
    { 90, 5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 77, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #90 = G_ATOMIC_CMPXCHG_WITH_SUCCESS
1557
    { 89, 5,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 72, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #89 = G_INDEXED_STORE
1558
    { 88, 2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL },  // Inst #88 = G_STORE
1559
    { 87, 5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #87 = G_INDEXED_ZEXTLOAD
1560
    { 86, 5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #86 = G_INDEXED_SEXTLOAD
1561
    { 85, 5,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 67, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #85 = G_INDEXED_LOAD
1562
    { 84, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #84 = G_ZEXTLOAD
1563
    { 83, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #83 = G_SEXTLOAD
1564
    { 82, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL },  // Inst #82 = G_LOAD
1565
    { 81, 1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #81 = G_READCYCLECOUNTER
1566
    { 80, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #80 = G_INTRINSIC_ROUNDEVEN
1567
    { 79, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #79 = G_INTRINSIC_LRINT
1568
    { 78, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #78 = G_INTRINSIC_ROUND
1569
    { 77, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #77 = G_INTRINSIC_TRUNC
1570
    { 76, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 64, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #76 = G_INTRINSIC_FPTRUNC_ROUND
1571
    { 75, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #75 = G_CONSTANT_FOLD_BARRIER
1572
    { 74, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 62, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #74 = G_FREEZE
1573
    { 73, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #73 = G_BITCAST
1574
    { 72, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #72 = G_INTTOPTR
1575
    { 71, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #71 = G_PTRTOINT
1576
    { 70, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #70 = G_CONCAT_VECTORS
1577
    { 69, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #69 = G_BUILD_VECTOR_TRUNC
1578
    { 68, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #68 = G_BUILD_VECTOR
1579
    { 67, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #67 = G_MERGE_VALUES
1580
    { 66, 4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 58, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #66 = G_INSERT
1581
    { 65, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 56, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #65 = G_UNMERGE_VALUES
1582
    { 64, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 53, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #64 = G_EXTRACT
1583
    { 63, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #63 = G_CONSTANT_POOL
1584
    { 62, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #62 = G_GLOBAL_VALUE
1585
    { 61, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 51, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #61 = G_FRAME_INDEX
1586
    { 60, 1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #60 = G_PHI
1587
    { 59, 1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 50, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #59 = G_IMPLICIT_DEF
1588
    { 58, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #58 = G_XOR
1589
    { 57, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #57 = G_OR
1590
    { 56, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #56 = G_AND
1591
    { 55, 4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #55 = G_UDIVREM
1592
    { 54, 4,  2,  0,  0,  0,  0,  SparcImpOpBase + 0, 46, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #54 = G_SDIVREM
1593
    { 53, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #53 = G_UREM
1594
    { 52, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #52 = G_SREM
1595
    { 51, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #51 = G_UDIV
1596
    { 50, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #50 = G_SDIV
1597
    { 49, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #49 = G_MUL
1598
    { 48, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #48 = G_SUB
1599
    { 47, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 43, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL },  // Inst #47 = G_ADD
1600
    { 46, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #46 = G_ASSERT_ALIGN
1601
    { 45, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #45 = G_ASSERT_ZEXT
1602
    { 44, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 40, 0|(1ULL<<MCID::PreISelOpcode)|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #44 = G_ASSERT_SEXT
1603
    { 43, 1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #43 = JUMP_TABLE_DEBUG_INFO
1604
    { 42, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #42 = MEMBARRIER
1605
    { 41, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #41 = ICALL_BRANCH_FUNNEL
1606
    { 40, 3,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 37, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #40 = PATCHABLE_TYPED_EVENT_CALL
1607
    { 39, 2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 35, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #39 = PATCHABLE_EVENT_CALL
1608
    { 38, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #38 = PATCHABLE_TAIL_CALL
1609
    { 37, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #37 = PATCHABLE_FUNCTION_EXIT
1610
    { 36, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #36 = PATCHABLE_RET
1611
    { 35, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #35 = PATCHABLE_FUNCTION_ENTER
1612
    { 34, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #34 = PATCHABLE_OP
1613
    { 33, 1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #33 = FAULTING_OP
1614
    { 32, 2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 33, 0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #32 = LOCAL_ESCAPE
1615
    { 31, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #31 = STATEPOINT
1616
    { 30, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 30, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #30 = PREALLOCATED_ARG
1617
    { 29, 1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #29 = PREALLOCATED_SETUP
1618
    { 28, 1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 29, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL },  // Inst #28 = LOAD_STACK_GUARD
1619
    { 27, 6,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 23, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #27 = PATCHPOINT
1620
    { 26, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #26 = FENTRY_CALL
1621
    { 25, 2,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 21, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #25 = STACKMAP
1622
    { 24, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 19, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #24 = ARITH_FENCE
1623
    { 23, 4,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 15, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #23 = PSEUDO_PROBE
1624
    { 22, 1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #22 = LIFETIME_END
1625
    { 21, 1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #21 = LIFETIME_START
1626
    { 20, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #20 = BUNDLE
1627
    { 19, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #19 = COPY
1628
    { 18, 2,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 13, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #18 = REG_SEQUENCE
1629
    { 17, 1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta), 0x0ULL },  // Inst #17 = DBG_LABEL
1630
    { 16, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #16 = DBG_PHI
1631
    { 15, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #15 = DBG_INSTR_REF
1632
    { 14, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #14 = DBG_VALUE_LIST
1633
    { 13, 0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #13 = DBG_VALUE
1634
    { 12, 3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #12 = COPY_TO_REGCLASS
1635
    { 11, 4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 9,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #11 = SUBREG_TO_REG
1636
    { 10, 1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL },  // Inst #10 = IMPLICIT_DEF
1637
    { 9,  4,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 5,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #9 = INSERT_SUBREG
1638
    { 8,  3,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 2,  0|(1ULL<<MCID::Pseudo), 0x0ULL },  // Inst #8 = EXTRACT_SUBREG
1639
    { 7,  0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #7 = KILL
1640
    { 6,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #6 = ANNOTATION_LABEL
1641
    { 5,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #5 = GC_LABEL
1642
    { 4,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #4 = EH_LABEL
1643
    { 3,  1,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Meta)|(1ULL<<MCID::NotDuplicable), 0x0ULL },  // Inst #3 = CFI_INSTRUCTION
1644
    { 2,  0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL },  // Inst #2 = INLINEASM_BR
1645
    { 1,  0,  0,  0,  0,  0,  0,  SparcImpOpBase + 0, 1,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #1 = INLINEASM
1646
    { 0,  1,  1,  0,  0,  0,  0,  SparcImpOpBase + 0, 0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL },  // Inst #0 = PHI
1647
  }, {
1648
    /* 0 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1649
    /* 1 */
1650
    /* 1 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1651
    /* 2 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1652
    /* 5 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1653
    /* 9 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1654
    /* 13 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1655
    /* 15 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1656
    /* 19 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, MCOI_TIED_TO(0) },
1657
    /* 21 */ { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1658
    /* 23 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1659
    /* 29 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1660
    /* 30 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1661
    /* 33 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1662
    /* 35 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1663
    /* 37 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1664
    /* 40 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1665
    /* 43 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1666
    /* 46 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1667
    /* 50 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1668
    /* 51 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1669
    /* 53 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1670
    /* 56 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1671
    /* 58 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1672
    /* 62 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1673
    /* 64 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1674
    /* 67 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1675
    /* 72 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1676
    /* 77 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1677
    /* 82 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1678
    /* 86 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1679
    /* 89 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1680
    /* 93 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1681
    /* 96 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1682
    /* 99 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1683
    /* 103 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1684
    /* 107 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1685
    /* 112 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1686
    /* 116 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1687
    /* 119 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1688
    /* 123 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 },
1689
    /* 126 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1690
    /* 130 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 },
1691
    /* 132 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_2, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_IMM_0, 0 },
1692
    /* 136 */ { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_0, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 }, { -1, 0, MCOI::OPERAND_GENERIC_1, 0 },
1693
    /* 140 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1694
    /* 144 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1695
    /* 148 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1696
    /* 152 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1697
    /* 156 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1698
    /* 158 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1699
    /* 161 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1700
    /* 164 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1701
    /* 167 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1702
    /* 170 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1703
    /* 172 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1704
    /* 175 */ { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1705
    /* 178 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1706
    /* 181 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1707
    /* 185 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1708
    /* 190 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1709
    /* 194 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1710
    /* 199 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1711
    /* 200 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1712
    /* 202 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1713
    /* 204 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1714
    /* 206 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1715
    /* 209 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1716
    /* 212 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1717
    /* 215 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1718
    /* 218 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1719
    /* 220 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1720
    /* 222 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1721
    /* 224 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1722
    /* 226 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1723
    /* 229 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1724
    /* 233 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1725
    /* 237 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1726
    /* 242 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1727
    /* 247 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1728
    /* 252 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1729
    /* 256 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1730
    /* 258 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1731
    /* 260 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1732
    /* 262 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1733
    /* 264 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1734
    /* 267 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1735
    /* 271 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1736
    /* 275 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1737
    /* 278 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1738
    /* 281 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1739
    /* 284 */ { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1740
    /* 287 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1741
    /* 290 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1742
    /* 294 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1743
    /* 297 */ { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1744
    /* 300 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1745
    /* 303 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1746
    /* 307 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1747
    /* 310 */ { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1748
    /* 313 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1749
    /* 316 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1750
    /* 320 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1751
    /* 323 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1752
    /* 326 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1753
    /* 330 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1754
    /* 333 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1755
    /* 336 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 },
1756
    /* 339 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1757
    /* 341 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1758
    /* 343 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1759
    /* 347 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1760
    /* 351 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1761
    /* 356 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1762
    /* 361 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1763
    /* 363 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1764
    /* 365 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1765
    /* 368 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1766
    /* 371 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1767
    /* 373 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1768
    /* 374 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1769
    /* 376 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1770
    /* 379 */ { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1771
    /* 382 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1772
    /* 385 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1773
    /* 389 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1774
    /* 393 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1775
    /* 396 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1776
    /* 400 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1777
    /* 403 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1778
    /* 406 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1779
    /* 409 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1780
    /* 412 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1781
    /* 416 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1782
    /* 419 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::CoprocPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1783
    /* 422 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1784
    /* 425 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1785
    /* 429 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1786
    /* 432 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1787
    /* 435 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1788
    /* 438 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1789
    /* 442 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1790
    /* 445 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1791
    /* 448 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1792
    /* 452 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1793
    /* 455 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1794
    /* 458 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1795
    /* 462 */ { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1796
    /* 465 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1797
    /* 469 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1798
    /* 474 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) },
1799
    /* 478 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1800
    /* 481 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1801
    /* 485 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1802
    /* 488 */ { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1803
    /* 491 */ { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1804
    /* 496 */ { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1805
    /* 501 */ { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1806
    /* 506 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1807
    /* 511 */ { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, MCOI_TIED_TO(0) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 },
1808
    /* 516 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1809
    /* 519 */ { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1810
    /* 522 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 },
1811
    /* 525 */ { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 },
1812
  }, {
1813
    /* 0 */
1814
    /* 0 */ SP::O6, SP::O6,
1815
    /* 2 */ SP::O7,
1816
    /* 3 */ SP::FCC0,
1817
    /* 4 */ SP::ICC,
1818
    /* 5 */ SP::ICC, SP::ICC,
1819
    /* 7 */ SP::O6,
1820
    /* 8 */ SP::ASR3,
1821
    /* 9 */ SP::CPSR,
1822
    /* 10 */ SP::FSR,
1823
    /* 11 */ SP::Y, SP::ICC, SP::Y, SP::ICC,
1824
    /* 15 */ SP::PSR,
1825
    /* 16 */ SP::FQ,
1826
    /* 17 */ SP::TBR,
1827
    /* 18 */ SP::WIM,
1828
    /* 19 */ SP::Y, SP::Y, SP::ICC,
1829
    /* 22 */ SP::Y, SP::Y,
1830
    /* 24 */ SP::Y, SP::ASR18, SP::Y, SP::ASR18,
1831
    /* 28 */ SP::Y, SP::ICC,
1832
    /* 30 */ SP::Y,
1833
    /* 31 */ SP::CPQ,
1834
  }
1835
};
1836
1837
1838
#ifdef __GNUC__
1839
#pragma GCC diagnostic push
1840
#pragma GCC diagnostic ignored "-Woverlength-strings"
1841
#endif
1842
extern const char SparcInstrNameData[] = {
1843
  /* 0 */ "G_FLOG10\0"
1844
  /* 9 */ "G_FEXP10\0"
1845
  /* 18 */ "TA1\0"
1846
  /* 22 */ "FSRC1\0"
1847
  /* 28 */ "FANDNOT1\0"
1848
  /* 37 */ "FNOT1\0"
1849
  /* 43 */ "FORNOT1\0"
1850
  /* 51 */ "FSRA32\0"
1851
  /* 58 */ "FPSUB32\0"
1852
  /* 66 */ "FPADD32\0"
1853
  /* 74 */ "EDGE32\0"
1854
  /* 81 */ "FCMPLE32\0"
1855
  /* 90 */ "FCMPNE32\0"
1856
  /* 99 */ "FPACK32\0"
1857
  /* 107 */ "CMASK32\0"
1858
  /* 115 */ "FSLL32\0"
1859
  /* 122 */ "FSRL32\0"
1860
  /* 129 */ "FCMPEQ32\0"
1861
  /* 138 */ "FSLAS32\0"
1862
  /* 146 */ "FCMPGT32\0"
1863
  /* 155 */ "ARRAY32\0"
1864
  /* 163 */ "FSRC2\0"
1865
  /* 169 */ "G_FLOG2\0"
1866
  /* 177 */ "G_FEXP2\0"
1867
  /* 185 */ "FANDNOT2\0"
1868
  /* 194 */ "FNOT2\0"
1869
  /* 200 */ "FORNOT2\0"
1870
  /* 208 */ "TA3\0"
1871
  /* 212 */ "FPADD64\0"
1872
  /* 220 */ "TA5\0"
1873
  /* 224 */ "FSRA16\0"
1874
  /* 231 */ "FPSUB16\0"
1875
  /* 239 */ "FPADD16\0"
1876
  /* 247 */ "EDGE16\0"
1877
  /* 254 */ "FCMPLE16\0"
1878
  /* 263 */ "FCMPNE16\0"
1879
  /* 272 */ "FPACK16\0"
1880
  /* 280 */ "CMASK16\0"
1881
  /* 288 */ "FSLL16\0"
1882
  /* 295 */ "FSRL16\0"
1883
  /* 302 */ "FCHKSM16\0"
1884
  /* 311 */ "FMEAN16\0"
1885
  /* 319 */ "FCMPEQ16\0"
1886
  /* 328 */ "FSLAS16\0"
1887
  /* 336 */ "FCMPGT16\0"
1888
  /* 345 */ "FMUL8X16\0"
1889
  /* 354 */ "FMULD8ULX16\0"
1890
  /* 366 */ "FMUL8ULX16\0"
1891
  /* 377 */ "FMULD8SUX16\0"
1892
  /* 389 */ "FMUL8SUX16\0"
1893
  /* 400 */ "ARRAY16\0"
1894
  /* 408 */ "EDGE8\0"
1895
  /* 414 */ "CMASK8\0"
1896
  /* 421 */ "ARRAY8\0"
1897
  /* 428 */ "FBCONDA_V9\0"
1898
  /* 439 */ "FBCOND_V9\0"
1899
  /* 449 */ "FCMPD_V9\0"
1900
  /* 458 */ "FCMPQ_V9\0"
1901
  /* 467 */ "FCMPS_V9\0"
1902
  /* 476 */ "BA\0"
1903
  /* 479 */ "BPFCCA\0"
1904
  /* 486 */ "BPICCA\0"
1905
  /* 493 */ "BPXCCA\0"
1906
  /* 500 */ "CBCONDA\0"
1907
  /* 508 */ "FBCONDA\0"
1908
  /* 516 */ "G_FMA\0"
1909
  /* 522 */ "G_STRICT_FMA\0"
1910
  /* 535 */ "BPRA\0"
1911
  /* 540 */ "FALIGNADATA\0"
1912
  /* 552 */ "G_FSUB\0"
1913
  /* 559 */ "G_STRICT_FSUB\0"
1914
  /* 573 */ "G_ATOMICRMW_FSUB\0"
1915
  /* 590 */ "G_SUB\0"
1916
  /* 596 */ "G_ATOMICRMW_SUB\0"
1917
  /* 612 */ "ADDXCCC\0"
1918
  /* 620 */ "BPFCC\0"
1919
  /* 626 */ "V9FMOVD_FCC\0"
1920
  /* 638 */ "SELECT_CC_DFP_FCC\0"
1921
  /* 656 */ "SELECT_CC_QFP_FCC\0"
1922
  /* 674 */ "SELECT_CC_FP_FCC\0"
1923
  /* 691 */ "V9FMOVQ_FCC\0"
1924
  /* 703 */ "V9FMOVS_FCC\0"
1925
  /* 715 */ "SELECT_CC_Int_FCC\0"
1926
  /* 733 */ "BPICC\0"
1927
  /* 739 */ "FMOVD_ICC\0"
1928
  /* 749 */ "SELECT_CC_DFP_ICC\0"
1929
  /* 767 */ "SELECT_CC_QFP_ICC\0"
1930
  /* 785 */ "SELECT_CC_FP_ICC\0"
1931
  /* 802 */ "FMOVQ_ICC\0"
1932
  /* 812 */ "FMOVS_ICC\0"
1933
  /* 822 */ "SELECT_CC_Int_ICC\0"
1934
  /* 840 */ "BPXCC\0"
1935
  /* 846 */ "FMOVD_XCC\0"
1936
  /* 856 */ "SELECT_CC_DFP_XCC\0"
1937
  /* 874 */ "SELECT_CC_QFP_XCC\0"
1938
  /* 892 */ "SELECT_CC_FP_XCC\0"
1939
  /* 909 */ "FMOVQ_XCC\0"
1940
  /* 919 */ "FMOVS_XCC\0"
1941
  /* 929 */ "SELECT_CC_Int_XCC\0"
1942
  /* 947 */ "G_INTRINSIC\0"
1943
  /* 959 */ "G_FPTRUNC\0"
1944
  /* 969 */ "G_INTRINSIC_TRUNC\0"
1945
  /* 987 */ "G_TRUNC\0"
1946
  /* 995 */ "G_BUILD_VECTOR_TRUNC\0"
1947
  /* 1016 */ "G_DYN_STACKALLOC\0"
1948
  /* 1033 */ "ADDXC\0"
1949
  /* 1039 */ "G_FMAD\0"
1950
  /* 1046 */ "G_INDEXED_SEXTLOAD\0"
1951
  /* 1065 */ "G_SEXTLOAD\0"
1952
  /* 1076 */ "G_INDEXED_ZEXTLOAD\0"
1953
  /* 1095 */ "G_ZEXTLOAD\0"
1954
  /* 1106 */ "G_INDEXED_LOAD\0"
1955
  /* 1121 */ "G_LOAD\0"
1956
  /* 1128 */ "FSUBD\0"
1957
  /* 1134 */ "FHSUBD\0"
1958
  /* 1141 */ "G_VECREDUCE_FADD\0"
1959
  /* 1158 */ "G_FADD\0"
1960
  /* 1165 */ "G_VECREDUCE_SEQ_FADD\0"
1961
  /* 1186 */ "G_STRICT_FADD\0"
1962
  /* 1200 */ "G_ATOMICRMW_FADD\0"
1963
  /* 1217 */ "G_VECREDUCE_ADD\0"
1964
  /* 1233 */ "G_ADD\0"
1965
  /* 1239 */ "G_PTR_ADD\0"
1966
  /* 1249 */ "G_ATOMICRMW_ADD\0"
1967
  /* 1265 */ "FADDD\0"
1968
  /* 1271 */ "FHADDD\0"
1969
  /* 1278 */ "FNHADDD\0"
1970
  /* 1286 */ "FNADDD\0"
1971
  /* 1293 */ "V9FCMPED\0"
1972
  /* 1302 */ "RESTORED\0"
1973
  /* 1311 */ "SAVED\0"
1974
  /* 1317 */ "FNEGD\0"
1975
  /* 1323 */ "FMULD\0"
1976
  /* 1329 */ "FNMULD\0"
1977
  /* 1336 */ "FSMULD\0"
1978
  /* 1343 */ "FNSMULD\0"
1979
  /* 1351 */ "FAND\0"
1980
  /* 1356 */ "FNAND\0"
1981
  /* 1362 */ "G_ATOMICRMW_NAND\0"
1982
  /* 1379 */ "FEXPAND\0"
1983
  /* 1387 */ "G_VECREDUCE_AND\0"
1984
  /* 1403 */ "G_AND\0"
1985
  /* 1409 */ "G_ATOMICRMW_AND\0"
1986
  /* 1425 */ "LIFETIME_END\0"
1987
  /* 1438 */ "CBCOND\0"
1988
  /* 1445 */ "FBCOND\0"
1989
  /* 1452 */ "G_BRCOND\0"
1990
  /* 1461 */ "G_LLROUND\0"
1991
  /* 1471 */ "G_LROUND\0"
1992
  /* 1480 */ "G_INTRINSIC_ROUND\0"
1993
  /* 1498 */ "G_INTRINSIC_FPTRUNC_ROUND\0"
1994
  /* 1524 */ "FITOD\0"
1995
  /* 1530 */ "FQTOD\0"
1996
  /* 1536 */ "FSTOD\0"
1997
  /* 1542 */ "FXTOD\0"
1998
  /* 1548 */ "MOVXTOD\0"
1999
  /* 1556 */ "V9FCMPD\0"
2000
  /* 1564 */ "FLCMPD\0"
2001
  /* 1571 */ "LOAD_STACK_GUARD\0"
2002
  /* 1588 */ "FMOVRD\0"
2003
  /* 1595 */ "FABSD\0"
2004
  /* 1601 */ "FSQRTD\0"
2005
  /* 1608 */ "FDIVD\0"
2006
  /* 1614 */ "FMOVD\0"
2007
  /* 1620 */ "PSEUDO_PROBE\0"
2008
  /* 1633 */ "G_SSUBE\0"
2009
  /* 1641 */ "G_USUBE\0"
2010
  /* 1649 */ "G_FENCE\0"
2011
  /* 1657 */ "ARITH_FENCE\0"
2012
  /* 1669 */ "REG_SEQUENCE\0"
2013
  /* 1682 */ "G_SADDE\0"
2014
  /* 1690 */ "G_UADDE\0"
2015
  /* 1698 */ "G_GET_FPMODE\0"
2016
  /* 1711 */ "G_RESET_FPMODE\0"
2017
  /* 1726 */ "G_SET_FPMODE\0"
2018
  /* 1739 */ "G_FMINNUM_IEEE\0"
2019
  /* 1754 */ "G_FMAXNUM_IEEE\0"
2020
  /* 1769 */ "FPMERGE\0"
2021
  /* 1777 */ "G_JUMP_TABLE\0"
2022
  /* 1790 */ "BUNDLE\0"
2023
  /* 1797 */ "BSHUFFLE\0"
2024
  /* 1806 */ "G_MEMCPY_INLINE\0"
2025
  /* 1822 */ "DONE\0"
2026
  /* 1827 */ "FONE\0"
2027
  /* 1832 */ "LOCAL_ESCAPE\0"
2028
  /* 1845 */ "G_STACKRESTORE\0"
2029
  /* 1860 */ "G_INDEXED_STORE\0"
2030
  /* 1876 */ "G_STORE\0"
2031
  /* 1884 */ "G_BITREVERSE\0"
2032
  /* 1897 */ "DBG_VALUE\0"
2033
  /* 1907 */ "G_GLOBAL_VALUE\0"
2034
  /* 1922 */ "G_STACKSAVE\0"
2035
  /* 1934 */ "G_MEMMOVE\0"
2036
  /* 1944 */ "G_FREEZE\0"
2037
  /* 1953 */ "G_FCANONICALIZE\0"
2038
  /* 1969 */ "G_CTLZ_ZERO_UNDEF\0"
2039
  /* 1987 */ "G_CTTZ_ZERO_UNDEF\0"
2040
  /* 2005 */ "G_IMPLICIT_DEF\0"
2041
  /* 2020 */ "DBG_INSTR_REF\0"
2042
  /* 2034 */ "G_FNEG\0"
2043
  /* 2041 */ "EXTRACT_SUBREG\0"
2044
  /* 2056 */ "INSERT_SUBREG\0"
2045
  /* 2070 */ "G_SEXT_INREG\0"
2046
  /* 2083 */ "SUBREG_TO_REG\0"
2047
  /* 2097 */ "G_ATOMIC_CMPXCHG\0"
2048
  /* 2114 */ "G_ATOMICRMW_XCHG\0"
2049
  /* 2131 */ "G_FLOG\0"
2050
  /* 2138 */ "G_VAARG\0"
2051
  /* 2146 */ "PREALLOCATED_ARG\0"
2052
  /* 2163 */ "G_PREFETCH\0"
2053
  /* 2174 */ "G_SMULH\0"
2054
  /* 2182 */ "G_UMULH\0"
2055
  /* 2190 */ "FLUSH\0"
2056
  /* 2196 */ "DBG_PHI\0"
2057
  /* 2204 */ "UMULXHI\0"
2058
  /* 2212 */ "XMULXHI\0"
2059
  /* 2220 */ "FDTOI\0"
2060
  /* 2226 */ "FQTOI\0"
2061
  /* 2232 */ "FSTOI\0"
2062
  /* 2238 */ "G_FPTOSI\0"
2063
  /* 2247 */ "G_FPTOUI\0"
2064
  /* 2256 */ "G_FPOWI\0"
2065
  /* 2264 */ "BMASK\0"
2066
  /* 2270 */ "G_PTRMASK\0"
2067
  /* 2280 */ "EDGE32L\0"
2068
  /* 2288 */ "EDGE16L\0"
2069
  /* 2296 */ "EDGE8L\0"
2070
  /* 2303 */ "FMUL8X16AL\0"
2071
  /* 2314 */ "GC_LABEL\0"
2072
  /* 2323 */ "DBG_LABEL\0"
2073
  /* 2333 */ "EH_LABEL\0"
2074
  /* 2342 */ "ANNOTATION_LABEL\0"
2075
  /* 2359 */ "ICALL_BRANCH_FUNNEL\0"
2076
  /* 2379 */ "G_FSHL\0"
2077
  /* 2386 */ "G_SHL\0"
2078
  /* 2392 */ "G_FCEIL\0"
2079
  /* 2400 */ "PATCHABLE_TAIL_CALL\0"
2080
  /* 2420 */ "TLS_CALL\0"
2081
  /* 2429 */ "PATCHABLE_TYPED_EVENT_CALL\0"
2082
  /* 2456 */ "PATCHABLE_EVENT_CALL\0"
2083
  /* 2477 */ "FENTRY_CALL\0"
2084
  /* 2489 */ "KILL\0"
2085
  /* 2494 */ "G_CONSTANT_POOL\0"
2086
  /* 2510 */ "ALIGNADDRL\0"
2087
  /* 2521 */ "RETL\0"
2088
  /* 2526 */ "G_ROTL\0"
2089
  /* 2533 */ "G_VECREDUCE_FMUL\0"
2090
  /* 2550 */ "G_FMUL\0"
2091
  /* 2557 */ "G_VECREDUCE_SEQ_FMUL\0"
2092
  /* 2578 */ "G_STRICT_FMUL\0"
2093
  /* 2592 */ "G_VECREDUCE_MUL\0"
2094
  /* 2608 */ "G_MUL\0"
2095
  /* 2614 */ "SIAM\0"
2096
  /* 2619 */ "G_FREM\0"
2097
  /* 2626 */ "G_STRICT_FREM\0"
2098
  /* 2640 */ "G_SREM\0"
2099
  /* 2647 */ "G_UREM\0"
2100
  /* 2654 */ "G_SDIVREM\0"
2101
  /* 2664 */ "G_UDIVREM\0"
2102
  /* 2674 */ "RDWIM\0"
2103
  /* 2680 */ "INLINEASM\0"
2104
  /* 2690 */ "G_VECREDUCE_FMINIMUM\0"
2105
  /* 2711 */ "G_FMINIMUM\0"
2106
  /* 2722 */ "G_VECREDUCE_FMAXIMUM\0"
2107
  /* 2743 */ "G_FMAXIMUM\0"
2108
  /* 2754 */ "G_FMINNUM\0"
2109
  /* 2764 */ "G_FMAXNUM\0"
2110
  /* 2774 */ "EDGE32N\0"
2111
  /* 2782 */ "EDGE16N\0"
2112
  /* 2790 */ "EDGE8N\0"
2113
  /* 2797 */ "G_INTRINSIC_ROUNDEVEN\0"
2114
  /* 2819 */ "G_ASSERT_ALIGN\0"
2115
  /* 2834 */ "G_FCOPYSIGN\0"
2116
  /* 2846 */ "G_VECREDUCE_FMIN\0"
2117
  /* 2863 */ "G_ATOMICRMW_FMIN\0"
2118
  /* 2880 */ "G_VECREDUCE_SMIN\0"
2119
  /* 2897 */ "G_SMIN\0"
2120
  /* 2904 */ "G_VECREDUCE_UMIN\0"
2121
  /* 2921 */ "G_UMIN\0"
2122
  /* 2928 */ "G_ATOMICRMW_UMIN\0"
2123
  /* 2945 */ "G_ATOMICRMW_MIN\0"
2124
  /* 2961 */ "G_FSIN\0"
2125
  /* 2968 */ "EDGE32LN\0"
2126
  /* 2977 */ "EDGE16LN\0"
2127
  /* 2986 */ "EDGE8LN\0"
2128
  /* 2994 */ "CFI_INSTRUCTION\0"
2129
  /* 3010 */ "PDISTN\0"
2130
  /* 3017 */ "ADJCALLSTACKDOWN\0"
2131
  /* 3034 */ "SHUTDOWN\0"
2132
  /* 3043 */ "G_SSUBO\0"
2133
  /* 3051 */ "G_USUBO\0"
2134
  /* 3059 */ "G_SADDO\0"
2135
  /* 3067 */ "G_UADDO\0"
2136
  /* 3075 */ "JUMP_TABLE_DEBUG_INFO\0"
2137
  /* 3097 */ "G_SMULO\0"
2138
  /* 3105 */ "G_UMULO\0"
2139
  /* 3113 */ "G_BZERO\0"
2140
  /* 3121 */ "FZERO\0"
2141
  /* 3127 */ "STACKMAP\0"
2142
  /* 3136 */ "G_ATOMICRMW_UDEC_WRAP\0"
2143
  /* 3158 */ "G_ATOMICRMW_UINC_WRAP\0"
2144
  /* 3180 */ "G_BSWAP\0"
2145
  /* 3188 */ "G_SITOFP\0"
2146
  /* 3197 */ "G_UITOFP\0"
2147
  /* 3206 */ "G_FCMP\0"
2148
  /* 3213 */ "G_ICMP\0"
2149
  /* 3220 */ "UNIMP\0"
2150
  /* 3226 */ "NOP\0"
2151
  /* 3230 */ "G_CTPOP\0"
2152
  /* 3238 */ "PATCHABLE_OP\0"
2153
  /* 3251 */ "FAULTING_OP\0"
2154
  /* 3263 */ "ADJCALLSTACKUP\0"
2155
  /* 3278 */ "PREALLOCATED_SETUP\0"
2156
  /* 3297 */ "G_FLDEXP\0"
2157
  /* 3306 */ "G_STRICT_FLDEXP\0"
2158
  /* 3322 */ "G_FEXP\0"
2159
  /* 3329 */ "G_FFREXP\0"
2160
  /* 3338 */ "FSUBQ\0"
2161
  /* 3344 */ "FADDQ\0"
2162
  /* 3350 */ "V9FCMPEQ\0"
2163
  /* 3359 */ "RDFQ\0"
2164
  /* 3364 */ "FNEGQ\0"
2165
  /* 3370 */ "FDMULQ\0"
2166
  /* 3377 */ "FMULQ\0"
2167
  /* 3383 */ "FDTOQ\0"
2168
  /* 3389 */ "FITOQ\0"
2169
  /* 3395 */ "FSTOQ\0"
2170
  /* 3401 */ "FXTOQ\0"
2171
  /* 3407 */ "V9FCMPQ\0"
2172
  /* 3415 */ "FMOVRQ\0"
2173
  /* 3422 */ "FABSQ\0"
2174
  /* 3428 */ "FSQRTQ\0"
2175
  /* 3435 */ "FDIVQ\0"
2176
  /* 3441 */ "FMOVQ\0"
2177
  /* 3447 */ "STBAR\0"
2178
  /* 3453 */ "RDTBR\0"
2179
  /* 3459 */ "G_BR\0"
2180
  /* 3464 */ "INLINEASM_BR\0"
2181
  /* 3477 */ "ALIGNADDR\0"
2182
  /* 3487 */ "G_BLOCK_ADDR\0"
2183
  /* 3500 */ "MEMBARRIER\0"
2184
  /* 3511 */ "G_CONSTANT_FOLD_BARRIER\0"
2185
  /* 3535 */ "PATCHABLE_FUNCTION_ENTER\0"
2186
  /* 3560 */ "G_READCYCLECOUNTER\0"
2187
  /* 3579 */ "G_READ_REGISTER\0"
2188
  /* 3595 */ "G_WRITE_REGISTER\0"
2189
  /* 3612 */ "G_ASHR\0"
2190
  /* 3619 */ "G_FSHR\0"
2191
  /* 3626 */ "G_LSHR\0"
2192
  /* 3633 */ "SIR\0"
2193
  /* 3637 */ "FOR\0"
2194
  /* 3641 */ "FNOR\0"
2195
  /* 3646 */ "FXNOR\0"
2196
  /* 3652 */ "G_FFLOOR\0"
2197
  /* 3661 */ "G_BUILD_VECTOR\0"
2198
  /* 3676 */ "G_SHUFFLE_VECTOR\0"
2199
  /* 3693 */ "FXOR\0"
2200
  /* 3698 */ "G_VECREDUCE_XOR\0"
2201
  /* 3714 */ "G_XOR\0"
2202
  /* 3720 */ "G_ATOMICRMW_XOR\0"
2203
  /* 3736 */ "G_VECREDUCE_OR\0"
2204
  /* 3751 */ "G_OR\0"
2205
  /* 3756 */ "G_ATOMICRMW_OR\0"
2206
  /* 3771 */ "BPR\0"
2207
  /* 3775 */ "RDPR\0"
2208
  /* 3780 */ "RDASR\0"
2209
  /* 3786 */ "RDPSR\0"
2210
  /* 3792 */ "G_ROTR\0"
2211
  /* 3799 */ "G_INTTOPTR\0"
2212
  /* 3810 */ "FSRC1S\0"
2213
  /* 3817 */ "FANDNOT1S\0"
2214
  /* 3827 */ "FNOT1S\0"
2215
  /* 3834 */ "FORNOT1S\0"
2216
  /* 3843 */ "FPSUB32S\0"
2217
  /* 3852 */ "FPADD32S\0"
2218
  /* 3861 */ "FSRC2S\0"
2219
  /* 3868 */ "FANDNOT2S\0"
2220
  /* 3878 */ "FNOT2S\0"
2221
  /* 3885 */ "FORNOT2S\0"
2222
  /* 3894 */ "FPSUB16S\0"
2223
  /* 3903 */ "FPADD16S\0"
2224
  /* 3912 */ "G_FABS\0"
2225
  /* 3919 */ "G_ABS\0"
2226
  /* 3925 */ "FSUBS\0"
2227
  /* 3931 */ "FHSUBS\0"
2228
  /* 3938 */ "FADDS\0"
2229
  /* 3944 */ "FHADDS\0"
2230
  /* 3951 */ "FNHADDS\0"
2231
  /* 3959 */ "FNADDS\0"
2232
  /* 3966 */ "FANDS\0"
2233
  /* 3972 */ "FNANDS\0"
2234
  /* 3979 */ "FONES\0"
2235
  /* 3985 */ "V9FCMPES\0"
2236
  /* 3994 */ "G_UNMERGE_VALUES\0"
2237
  /* 4011 */ "G_MERGE_VALUES\0"
2238
  /* 4026 */ "FNEGS\0"
2239
  /* 4032 */ "FMULS\0"
2240
  /* 4038 */ "FNMULS\0"
2241
  /* 4045 */ "G_FCOS\0"
2242
  /* 4052 */ "FZEROS\0"
2243
  /* 4059 */ "FDTOS\0"
2244
  /* 4065 */ "FITOS\0"
2245
  /* 4071 */ "FQTOS\0"
2246
  /* 4077 */ "MOVWTOS\0"
2247
  /* 4085 */ "FXTOS\0"
2248
  /* 4091 */ "V9FCMPS\0"
2249
  /* 4099 */ "FLCMPS\0"
2250
  /* 4106 */ "FORS\0"
2251
  /* 4111 */ "FNORS\0"
2252
  /* 4117 */ "FXNORS\0"
2253
  /* 4124 */ "G_CONCAT_VECTORS\0"
2254
  /* 4141 */ "FXORS\0"
2255
  /* 4147 */ "FMOVRS\0"
2256
  /* 4154 */ "COPY_TO_REGCLASS\0"
2257
  /* 4171 */ "G_IS_FPCLASS\0"
2258
  /* 4184 */ "FABSS\0"
2259
  /* 4190 */ "G_ATOMIC_CMPXCHG_WITH_SUCCESS\0"
2260
  /* 4220 */ "G_INTRINSIC_W_SIDE_EFFECTS\0"
2261
  /* 4247 */ "G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS\0"
2262
  /* 4285 */ "FSQRTS\0"
2263
  /* 4292 */ "FDIVS\0"
2264
  /* 4298 */ "FMOVS\0"
2265
  /* 4304 */ "G_SSUBSAT\0"
2266
  /* 4314 */ "G_USUBSAT\0"
2267
  /* 4324 */ "G_SADDSAT\0"
2268
  /* 4334 */ "G_UADDSAT\0"
2269
  /* 4344 */ "G_SSHLSAT\0"
2270
  /* 4354 */ "G_USHLSAT\0"
2271
  /* 4364 */ "G_SMULFIXSAT\0"
2272
  /* 4377 */ "G_UMULFIXSAT\0"
2273
  /* 4390 */ "G_SDIVFIXSAT\0"
2274
  /* 4403 */ "G_UDIVFIXSAT\0"
2275
  /* 4416 */ "G_EXTRACT\0"
2276
  /* 4426 */ "G_SELECT\0"
2277
  /* 4435 */ "G_BRINDIRECT\0"
2278
  /* 4448 */ "PATCHABLE_RET\0"
2279
  /* 4462 */ "G_MEMSET\0"
2280
  /* 4471 */ "PATCHABLE_FUNCTION_EXIT\0"
2281
  /* 4495 */ "G_BRJT\0"
2282
  /* 4502 */ "G_EXTRACT_VECTOR_ELT\0"
2283
  /* 4523 */ "G_INSERT_VECTOR_ELT\0"
2284
  /* 4543 */ "BPFCCANT\0"
2285
  /* 4552 */ "BPICCANT\0"
2286
  /* 4561 */ "BPXCCANT\0"
2287
  /* 4570 */ "BPRANT\0"
2288
  /* 4577 */ "G_FCONSTANT\0"
2289
  /* 4589 */ "G_CONSTANT\0"
2290
  /* 4600 */ "BPFCCNT\0"
2291
  /* 4608 */ "BPICCNT\0"
2292
  /* 4616 */ "BPXCCNT\0"
2293
  /* 4624 */ "LZCNT\0"
2294
  /* 4630 */ "G_INTRINSIC_CONVERGENT\0"
2295
  /* 4653 */ "STATEPOINT\0"
2296
  /* 4664 */ "PATCHPOINT\0"
2297
  /* 4675 */ "G_PTRTOINT\0"
2298
  /* 4686 */ "G_FRINT\0"
2299
  /* 4694 */ "G_INTRINSIC_LRINT\0"
2300
  /* 4712 */ "G_FNEARBYINT\0"
2301
  /* 4725 */ "BPRNT\0"
2302
  /* 4731 */ "G_VASTART\0"
2303
  /* 4741 */ "LIFETIME_START\0"
2304
  /* 4756 */ "G_INVOKE_REGION_START\0"
2305
  /* 4778 */ "G_INSERT\0"
2306
  /* 4787 */ "G_FSQRT\0"
2307
  /* 4795 */ "G_STRICT_FSQRT\0"
2308
  /* 4810 */ "G_BITCAST\0"
2309
  /* 4820 */ "G_ADDRSPACE_CAST\0"
2310
  /* 4837 */ "PDIST\0"
2311
  /* 4843 */ "DBG_VALUE_LIST\0"
2312
  /* 4858 */ "G_FPEXT\0"
2313
  /* 4866 */ "G_SEXT\0"
2314
  /* 4873 */ "G_ASSERT_SEXT\0"
2315
  /* 4887 */ "G_ANYEXT\0"
2316
  /* 4896 */ "G_ZEXT\0"
2317
  /* 4903 */ "G_ASSERT_ZEXT\0"
2318
  /* 4917 */ "FMUL8X16AU\0"
2319
  /* 4928 */ "G_FDIV\0"
2320
  /* 4935 */ "G_STRICT_FDIV\0"
2321
  /* 4949 */ "G_SDIV\0"
2322
  /* 4956 */ "G_UDIV\0"
2323
  /* 4963 */ "G_GET_FPENV\0"
2324
  /* 4975 */ "G_RESET_FPENV\0"
2325
  /* 4989 */ "G_SET_FPENV\0"
2326
  /* 5001 */ "FLUSHW\0"
2327
  /* 5008 */ "G_FPOW\0"
2328
  /* 5015 */ "MOVSTOSW\0"
2329
  /* 5024 */ "MOVSTOUW\0"
2330
  /* 5033 */ "G_VECREDUCE_FMAX\0"
2331
  /* 5050 */ "G_ATOMICRMW_FMAX\0"
2332
  /* 5067 */ "G_VECREDUCE_SMAX\0"
2333
  /* 5084 */ "G_SMAX\0"
2334
  /* 5091 */ "G_VECREDUCE_UMAX\0"
2335
  /* 5108 */ "G_UMAX\0"
2336
  /* 5115 */ "G_ATOMICRMW_UMAX\0"
2337
  /* 5132 */ "G_ATOMICRMW_MAX\0"
2338
  /* 5148 */ "GETPCX\0"
2339
  /* 5155 */ "G_FRAME_INDEX\0"
2340
  /* 5169 */ "G_SBFX\0"
2341
  /* 5176 */ "G_UBFX\0"
2342
  /* 5183 */ "FPACKFIX\0"
2343
  /* 5192 */ "G_SMULFIX\0"
2344
  /* 5202 */ "G_UMULFIX\0"
2345
  /* 5212 */ "G_SDIVFIX\0"
2346
  /* 5222 */ "G_UDIVFIX\0"
2347
  /* 5232 */ "XMULX\0"
2348
  /* 5238 */ "FDTOX\0"
2349
  /* 5244 */ "MOVDTOX\0"
2350
  /* 5252 */ "FQTOX\0"
2351
  /* 5258 */ "FSTOX\0"
2352
  /* 5264 */ "SETX\0"
2353
  /* 5269 */ "G_MEMCPY\0"
2354
  /* 5278 */ "COPY\0"
2355
  /* 5283 */ "RETRY\0"
2356
  /* 5289 */ "G_CTLZ\0"
2357
  /* 5296 */ "G_CTTZ\0"
2358
  /* 5303 */ "PREFETCHi\0"
2359
  /* 5313 */ "SETHIi\0"
2360
  /* 5320 */ "MEMBARi\0"
2361
  /* 5328 */ "LDSBAri\0"
2362
  /* 5336 */ "STBAri\0"
2363
  /* 5343 */ "LDUBAri\0"
2364
  /* 5351 */ "LDSTUBAri\0"
2365
  /* 5361 */ "LDDAri\0"
2366
  /* 5368 */ "LDAri\0"
2367
  /* 5374 */ "STDAri\0"
2368
  /* 5381 */ "LDDFAri\0"
2369
  /* 5389 */ "LDFAri\0"
2370
  /* 5396 */ "STDFAri\0"
2371
  /* 5404 */ "LDQFAri\0"
2372
  /* 5412 */ "STQFAri\0"
2373
  /* 5420 */ "STFAri\0"
2374
  /* 5427 */ "LDSHAri\0"
2375
  /* 5435 */ "STHAri\0"
2376
  /* 5442 */ "LDUHAri\0"
2377
  /* 5450 */ "SWAPAri\0"
2378
  /* 5458 */ "SRAri\0"
2379
  /* 5464 */ "CASAri\0"
2380
  /* 5471 */ "STAri\0"
2381
  /* 5477 */ "LDSWAri\0"
2382
  /* 5485 */ "LDXAri\0"
2383
  /* 5492 */ "CASXAri\0"
2384
  /* 5500 */ "STXAri\0"
2385
  /* 5507 */ "LDSBri\0"
2386
  /* 5514 */ "STBri\0"
2387
  /* 5520 */ "LDUBri\0"
2388
  /* 5527 */ "SUBri\0"
2389
  /* 5533 */ "LDSTUBri\0"
2390
  /* 5542 */ "SMACri\0"
2391
  /* 5549 */ "UMACri\0"
2392
  /* 5556 */ "SUBCri\0"
2393
  /* 5563 */ "TSUBCCri\0"
2394
  /* 5572 */ "TADDCCri\0"
2395
  /* 5581 */ "ANDCCri\0"
2396
  /* 5589 */ "V9MOVFCCri\0"
2397
  /* 5600 */ "TICCri\0"
2398
  /* 5607 */ "MOVICCri\0"
2399
  /* 5616 */ "SMULCCri\0"
2400
  /* 5625 */ "UMULCCri\0"
2401
  /* 5634 */ "ANDNCCri\0"
2402
  /* 5643 */ "ORNCCri\0"
2403
  /* 5651 */ "XNORCCri\0"
2404
  /* 5660 */ "XORCCri\0"
2405
  /* 5668 */ "MULSCCri\0"
2406
  /* 5677 */ "SDIVCCri\0"
2407
  /* 5686 */ "UDIVCCri\0"
2408
  /* 5695 */ "TXCCri\0"
2409
  /* 5702 */ "MOVXCCri\0"
2410
  /* 5711 */ "ADDCri\0"
2411
  /* 5718 */ "LDDCri\0"
2412
  /* 5725 */ "LDCri\0"
2413
  /* 5731 */ "STDCri\0"
2414
  /* 5738 */ "STCri\0"
2415
  /* 5744 */ "ADDri\0"
2416
  /* 5750 */ "LDDri\0"
2417
  /* 5756 */ "LDri\0"
2418
  /* 5761 */ "ANDri\0"
2419
  /* 5767 */ "BINDri\0"
2420
  /* 5774 */ "STDri\0"
2421
  /* 5780 */ "SUBEri\0"
2422
  /* 5787 */ "ADDEri\0"
2423
  /* 5794 */ "RESTOREri\0"
2424
  /* 5804 */ "SAVEri\0"
2425
  /* 5811 */ "LDDFri\0"
2426
  /* 5818 */ "LDFri\0"
2427
  /* 5824 */ "STDFri\0"
2428
  /* 5831 */ "LDQFri\0"
2429
  /* 5838 */ "STQFri\0"
2430
  /* 5845 */ "STFri\0"
2431
  /* 5851 */ "LDSHri\0"
2432
  /* 5858 */ "FLUSHri\0"
2433
  /* 5866 */ "STHri\0"
2434
  /* 5872 */ "LDUHri\0"
2435
  /* 5879 */ "TAIL_CALLri\0"
2436
  /* 5891 */ "SLLri\0"
2437
  /* 5897 */ "JMPLri\0"
2438
  /* 5904 */ "SRLri\0"
2439
  /* 5910 */ "SMULri\0"
2440
  /* 5917 */ "UMULri\0"
2441
  /* 5924 */ "WRWIMri\0"
2442
  /* 5932 */ "ANDNri\0"
2443
  /* 5939 */ "ORNri\0"
2444
  /* 5945 */ "TRAPri\0"
2445
  /* 5952 */ "SWAPri\0"
2446
  /* 5959 */ "STDCQri\0"
2447
  /* 5967 */ "STDFQri\0"
2448
  /* 5975 */ "WRTBRri\0"
2449
  /* 5983 */ "XNORri\0"
2450
  /* 5990 */ "XORri\0"
2451
  /* 5996 */ "WRPRri\0"
2452
  /* 6003 */ "WRASRri\0"
2453
  /* 6011 */ "LDCSRri\0"
2454
  /* 6019 */ "STCSRri\0"
2455
  /* 6027 */ "LDFSRri\0"
2456
  /* 6035 */ "STFSRri\0"
2457
  /* 6043 */ "LDXFSRri\0"
2458
  /* 6052 */ "STXFSRri\0"
2459
  /* 6061 */ "PWRPSRri\0"
2460
  /* 6070 */ "MOVRri\0"
2461
  /* 6077 */ "STri\0"
2462
  /* 6082 */ "RETTri\0"
2463
  /* 6089 */ "SDIVri\0"
2464
  /* 6096 */ "UDIVri\0"
2465
  /* 6103 */ "TSUBCCTVri\0"
2466
  /* 6114 */ "TADDCCTVri\0"
2467
  /* 6125 */ "LDSWri\0"
2468
  /* 6132 */ "SRAXri\0"
2469
  /* 6139 */ "LDXri\0"
2470
  /* 6145 */ "SLLXri\0"
2471
  /* 6152 */ "SRLXri\0"
2472
  /* 6159 */ "MULXri\0"
2473
  /* 6166 */ "STXri\0"
2474
  /* 6172 */ "SDIVXri\0"
2475
  /* 6180 */ "UDIVXri\0"
2476
  /* 6188 */ "PREFETCHr\0"
2477
  /* 6198 */ "LDSBArr\0"
2478
  /* 6206 */ "STBArr\0"
2479
  /* 6213 */ "LDUBArr\0"
2480
  /* 6221 */ "LDSTUBArr\0"
2481
  /* 6231 */ "LDDArr\0"
2482
  /* 6238 */ "LDArr\0"
2483
  /* 6244 */ "STDArr\0"
2484
  /* 6251 */ "LDDFArr\0"
2485
  /* 6259 */ "LDFArr\0"
2486
  /* 6266 */ "STDFArr\0"
2487
  /* 6274 */ "LDQFArr\0"
2488
  /* 6282 */ "STQFArr\0"
2489
  /* 6290 */ "STFArr\0"
2490
  /* 6297 */ "LDSHArr\0"
2491
  /* 6305 */ "STHArr\0"
2492
  /* 6312 */ "LDUHArr\0"
2493
  /* 6320 */ "SWAPArr\0"
2494
  /* 6328 */ "SRArr\0"
2495
  /* 6334 */ "CASArr\0"
2496
  /* 6341 */ "STArr\0"
2497
  /* 6347 */ "LDSWArr\0"
2498
  /* 6355 */ "LDXArr\0"
2499
  /* 6362 */ "CASXArr\0"
2500
  /* 6370 */ "STXArr\0"
2501
  /* 6377 */ "LDSBrr\0"
2502
  /* 6384 */ "STBrr\0"
2503
  /* 6390 */ "LDUBrr\0"
2504
  /* 6397 */ "SUBrr\0"
2505
  /* 6403 */ "LDSTUBrr\0"
2506
  /* 6412 */ "SMACrr\0"
2507
  /* 6419 */ "UMACrr\0"
2508
  /* 6426 */ "SUBCrr\0"
2509
  /* 6433 */ "TSUBCCrr\0"
2510
  /* 6442 */ "TADDCCrr\0"
2511
  /* 6451 */ "ANDCCrr\0"
2512
  /* 6459 */ "V9MOVFCCrr\0"
2513
  /* 6470 */ "TICCrr\0"
2514
  /* 6477 */ "MOVICCrr\0"
2515
  /* 6486 */ "SMULCCrr\0"
2516
  /* 6495 */ "UMULCCrr\0"
2517
  /* 6504 */ "ANDNCCrr\0"
2518
  /* 6513 */ "ORNCCrr\0"
2519
  /* 6521 */ "XNORCCrr\0"
2520
  /* 6530 */ "XORCCrr\0"
2521
  /* 6538 */ "MULSCCrr\0"
2522
  /* 6547 */ "SDIVCCrr\0"
2523
  /* 6556 */ "UDIVCCrr\0"
2524
  /* 6565 */ "TXCCrr\0"
2525
  /* 6572 */ "MOVXCCrr\0"
2526
  /* 6581 */ "ADDCrr\0"
2527
  /* 6588 */ "LDDCrr\0"
2528
  /* 6595 */ "LDCrr\0"
2529
  /* 6601 */ "STDCrr\0"
2530
  /* 6608 */ "POPCrr\0"
2531
  /* 6615 */ "STCrr\0"
2532
  /* 6621 */ "TLS_ADDrr\0"
2533
  /* 6631 */ "LDDrr\0"
2534
  /* 6637 */ "GDOP_LDrr\0"
2535
  /* 6647 */ "TLS_LDrr\0"
2536
  /* 6656 */ "ANDrr\0"
2537
  /* 6662 */ "BINDrr\0"
2538
  /* 6669 */ "STDrr\0"
2539
  /* 6675 */ "SUBErr\0"
2540
  /* 6682 */ "ADDErr\0"
2541
  /* 6689 */ "RESTORErr\0"
2542
  /* 6699 */ "SAVErr\0"
2543
  /* 6706 */ "LDDFrr\0"
2544
  /* 6713 */ "LDFrr\0"
2545
  /* 6719 */ "STDFrr\0"
2546
  /* 6726 */ "LDQFrr\0"
2547
  /* 6733 */ "STQFrr\0"
2548
  /* 6740 */ "STFrr\0"
2549
  /* 6746 */ "LDSHrr\0"
2550
  /* 6753 */ "FLUSHrr\0"
2551
  /* 6761 */ "STHrr\0"
2552
  /* 6767 */ "LDUHrr\0"
2553
  /* 6774 */ "CALLrr\0"
2554
  /* 6781 */ "SLLrr\0"
2555
  /* 6787 */ "JMPLrr\0"
2556
  /* 6794 */ "SRLrr\0"
2557
  /* 6800 */ "SMULrr\0"
2558
  /* 6807 */ "UMULrr\0"
2559
  /* 6814 */ "WRWIMrr\0"
2560
  /* 6822 */ "ANDNrr\0"
2561
  /* 6829 */ "ORNrr\0"
2562
  /* 6835 */ "TRAPrr\0"
2563
  /* 6842 */ "SWAPrr\0"
2564
  /* 6849 */ "STDCQrr\0"
2565
  /* 6857 */ "STDFQrr\0"
2566
  /* 6865 */ "WRTBRrr\0"
2567
  /* 6873 */ "XNORrr\0"
2568
  /* 6880 */ "XORrr\0"
2569
  /* 6886 */ "WRPRrr\0"
2570
  /* 6893 */ "WRASRrr\0"
2571
  /* 6901 */ "LDCSRrr\0"
2572
  /* 6909 */ "STCSRrr\0"
2573
  /* 6917 */ "LDFSRrr\0"
2574
  /* 6925 */ "STFSRrr\0"
2575
  /* 6933 */ "LDXFSRrr\0"
2576
  /* 6942 */ "STXFSRrr\0"
2577
  /* 6951 */ "PWRPSRrr\0"
2578
  /* 6960 */ "MOVRrr\0"
2579
  /* 6967 */ "STrr\0"
2580
  /* 6972 */ "RETTrr\0"
2581
  /* 6979 */ "SDIVrr\0"
2582
  /* 6986 */ "UDIVrr\0"
2583
  /* 6993 */ "TSUBCCTVrr\0"
2584
  /* 7004 */ "TADDCCTVrr\0"
2585
  /* 7015 */ "LDSWrr\0"
2586
  /* 7022 */ "SRAXrr\0"
2587
  /* 7029 */ "GDOP_LDXrr\0"
2588
  /* 7040 */ "TLS_LDXrr\0"
2589
  /* 7050 */ "SLLXrr\0"
2590
  /* 7057 */ "SRLXrr\0"
2591
  /* 7064 */ "MULXrr\0"
2592
  /* 7071 */ "STXrr\0"
2593
  /* 7077 */ "SDIVXrr\0"
2594
  /* 7085 */ "UDIVXrr\0"
2595
};
2596
#ifdef __GNUC__
2597
#pragma GCC diagnostic pop
2598
#endif
2599
2600
extern const unsigned SparcInstrNameIndices[] = {
2601
    2200U, 2680U, 3464U, 2994U, 2333U, 2314U, 2342U, 2489U, 
2602
    2041U, 2056U, 2007U, 2083U, 4154U, 1897U, 4843U, 2020U, 
2603
    2196U, 2323U, 1669U, 5278U, 1790U, 4741U, 1425U, 1620U, 
2604
    1657U, 3127U, 2477U, 4664U, 1571U, 3278U, 2146U, 4653U, 
2605
    1832U, 3251U, 3238U, 3535U, 4448U, 4471U, 2400U, 2456U, 
2606
    2429U, 2359U, 3500U, 3075U, 4873U, 4903U, 2819U, 1233U, 
2607
    590U, 2608U, 4949U, 4956U, 2640U, 2647U, 2654U, 2664U, 
2608
    1403U, 3751U, 3714U, 2005U, 2198U, 5155U, 1907U, 2494U, 
2609
    4416U, 3994U, 4778U, 4011U, 3661U, 995U, 4124U, 4675U, 
2610
    3799U, 4810U, 1944U, 3511U, 1498U, 969U, 1480U, 4694U, 
2611
    2797U, 3560U, 1121U, 1065U, 1095U, 1106U, 1046U, 1076U, 
2612
    1876U, 1860U, 4190U, 2097U, 2114U, 1249U, 596U, 1409U, 
2613
    1362U, 3756U, 3720U, 5132U, 2945U, 5115U, 2928U, 1200U, 
2614
    573U, 5050U, 2863U, 3158U, 3136U, 1649U, 2163U, 1452U, 
2615
    4435U, 4756U, 947U, 4220U, 4630U, 4247U, 4887U, 987U, 
2616
    4589U, 4577U, 4731U, 2138U, 4866U, 2070U, 4896U, 2386U, 
2617
    3626U, 3612U, 2379U, 3619U, 3792U, 2526U, 3213U, 3206U, 
2618
    4426U, 3067U, 1690U, 3051U, 1641U, 3059U, 1682U, 3043U, 
2619
    1633U, 3105U, 3097U, 2182U, 2174U, 4334U, 4324U, 4314U, 
2620
    4304U, 4354U, 4344U, 5192U, 5202U, 4364U, 4377U, 5212U, 
2621
    5222U, 4390U, 4403U, 1158U, 552U, 2550U, 516U, 1039U, 
2622
    4928U, 2619U, 5008U, 2256U, 3322U, 177U, 9U, 2131U, 
2623
    169U, 0U, 3297U, 3329U, 2034U, 4858U, 959U, 2238U, 
2624
    2247U, 3188U, 3197U, 3912U, 2834U, 4171U, 1953U, 2754U, 
2625
    2764U, 1739U, 1754U, 2711U, 2743U, 4963U, 4989U, 4975U, 
2626
    1698U, 1726U, 1711U, 1239U, 2270U, 2897U, 5084U, 2921U, 
2627
    5108U, 3919U, 1471U, 1461U, 3459U, 4495U, 4523U, 4502U, 
2628
    3676U, 5296U, 1987U, 5289U, 1969U, 3230U, 3180U, 1884U, 
2629
    2392U, 4045U, 2961U, 4787U, 3652U, 4686U, 4712U, 4820U, 
2630
    3487U, 1777U, 1016U, 1922U, 1845U, 1186U, 559U, 2578U, 
2631
    4935U, 2626U, 522U, 4795U, 3306U, 3579U, 3595U, 5269U, 
2632
    1806U, 1934U, 4462U, 3113U, 1165U, 2557U, 1141U, 2533U, 
2633
    5033U, 2846U, 2722U, 2690U, 1217U, 2592U, 1387U, 3736U, 
2634
    3698U, 5067U, 2880U, 5091U, 2904U, 5169U, 5176U, 3017U, 
2635
    3263U, 5148U, 638U, 749U, 856U, 674U, 785U, 892U, 
2636
    715U, 822U, 929U, 656U, 767U, 874U, 4467U, 5264U, 
2637
    5573U, 6443U, 5711U, 6581U, 5787U, 6682U, 1033U, 612U, 
2638
    5744U, 6625U, 3477U, 2510U, 5581U, 6451U, 5634U, 6504U, 
2639
    5932U, 6822U, 5761U, 6656U, 400U, 155U, 421U, 476U, 
2640
    1439U, 501U, 5767U, 6662U, 2264U, 620U, 479U, 4543U, 
2641
    4600U, 733U, 486U, 4552U, 4608U, 3771U, 535U, 4570U, 
2642
    4725U, 840U, 493U, 4561U, 4616U, 1797U, 2415U, 5884U, 
2643
    6774U, 5464U, 6334U, 5492U, 6362U, 1438U, 500U, 280U, 
2644
    107U, 414U, 1822U, 247U, 2288U, 2977U, 2782U, 74U, 
2645
    2280U, 2968U, 2774U, 408U, 2296U, 2986U, 2790U, 1595U, 
2646
    3422U, 4184U, 1265U, 3344U, 3938U, 540U, 1351U, 28U, 
2647
    3817U, 185U, 3868U, 3966U, 1445U, 508U, 428U, 439U, 
2648
    302U, 1558U, 449U, 319U, 129U, 336U, 146U, 254U, 
2649
    81U, 263U, 90U, 3409U, 458U, 4093U, 467U, 1608U, 
2650
    3435U, 4292U, 3370U, 2220U, 3383U, 4059U, 5238U, 1379U, 
2651
    1271U, 3944U, 1134U, 3931U, 1524U, 3389U, 4065U, 1564U, 
2652
    4099U, 2190U, 5001U, 5858U, 6753U, 311U, 1614U, 628U, 
2653
    739U, 846U, 3441U, 693U, 802U, 909U, 1588U, 3415U, 
2654
    4147U, 4298U, 705U, 812U, 919U, 389U, 366U, 345U, 
2655
    2303U, 4917U, 1323U, 377U, 354U, 3377U, 4032U, 1286U, 
2656
    3959U, 1356U, 3972U, 1317U, 3364U, 4026U, 1278U, 3951U, 
2657
    1329U, 4038U, 3641U, 4111U, 37U, 3827U, 194U, 3878U, 
2658
    1343U, 1827U, 3979U, 3637U, 43U, 3834U, 200U, 3885U, 
2659
    4106U, 272U, 99U, 5183U, 239U, 3903U, 66U, 3852U, 
2660
    212U, 1769U, 231U, 3894U, 58U, 3843U, 1530U, 2226U, 
2661
    4071U, 5252U, 328U, 138U, 288U, 115U, 1336U, 1601U, 
2662
    3428U, 4285U, 224U, 51U, 22U, 3810U, 163U, 3861U, 
2663
    295U, 122U, 1536U, 2232U, 3395U, 5258U, 1128U, 3338U, 
2664
    3925U, 3646U, 4117U, 3693U, 4141U, 1542U, 3401U, 4085U, 
2665
    3121U, 4052U, 7029U, 6637U, 5897U, 6787U, 5368U, 6238U, 
2666
    6011U, 6901U, 5725U, 6595U, 5361U, 6231U, 5718U, 6588U, 
2667
    5381U, 6251U, 5811U, 6706U, 5750U, 6631U, 5389U, 6259U, 
2668
    6027U, 6917U, 5818U, 6713U, 5404U, 6274U, 5831U, 6726U, 
2669
    5328U, 6198U, 5507U, 6377U, 5427U, 6297U, 5851U, 6746U, 
2670
    5351U, 6221U, 5533U, 6403U, 5477U, 6347U, 6125U, 7015U, 
2671
    5343U, 6213U, 5520U, 6390U, 5442U, 6312U, 5872U, 6767U, 
2672
    5485U, 6355U, 6043U, 6933U, 6139U, 7034U, 5756U, 6642U, 
2673
    4624U, 5320U, 5244U, 5591U, 6461U, 5607U, 6477U, 6070U, 
2674
    6960U, 5015U, 5024U, 4077U, 5702U, 6572U, 1548U, 5668U, 
2675
    6538U, 6159U, 7064U, 3226U, 5653U, 6523U, 5643U, 6513U, 
2676
    5939U, 6829U, 5985U, 6875U, 4837U, 3010U, 6608U, 5303U, 
2677
    6188U, 6061U, 6951U, 3780U, 3359U, 3775U, 3786U, 3453U, 
2678
    2674U, 1302U, 5794U, 6689U, 4458U, 2521U, 5283U, 6082U, 
2679
    6972U, 1311U, 5804U, 6699U, 5677U, 6547U, 6172U, 7077U, 
2680
    6089U, 6979U, 5313U, 3034U, 2614U, 3633U, 6145U, 7050U, 
2681
    5891U, 6781U, 5542U, 6412U, 5616U, 6486U, 5910U, 6800U, 
2682
    6132U, 7022U, 5458U, 6328U, 6152U, 7057U, 5904U, 6794U, 
2683
    5471U, 6341U, 3447U, 5336U, 6206U, 5514U, 6384U, 6019U, 
2684
    6909U, 5738U, 6615U, 5374U, 6244U, 5959U, 6849U, 5731U, 
2685
    6601U, 5396U, 6266U, 5967U, 6857U, 5824U, 6719U, 5774U, 
2686
    6669U, 5420U, 6290U, 6035U, 6925U, 5845U, 6740U, 5435U, 
2687
    6305U, 5866U, 6761U, 5412U, 6282U, 5838U, 6733U, 5500U, 
2688
    6370U, 6052U, 6942U, 6166U, 7071U, 6077U, 6967U, 5564U, 
2689
    6434U, 5556U, 6426U, 5780U, 6675U, 5527U, 6397U, 5450U, 
2690
    6320U, 5952U, 6842U, 18U, 208U, 220U, 6114U, 7004U, 
2691
    5572U, 6442U, 2410U, 5879U, 5600U, 6470U, 6621U, 2420U, 
2692
    7040U, 6647U, 5945U, 6835U, 6103U, 6993U, 5563U, 6433U, 
2693
    5695U, 6565U, 5686U, 6556U, 6180U, 7085U, 6096U, 6986U, 
2694
    5549U, 6419U, 5625U, 6495U, 2204U, 5917U, 6807U, 3220U, 
2695
    1556U, 1293U, 3350U, 3985U, 3407U, 4091U, 626U, 691U, 
2696
    703U, 5589U, 6459U, 6003U, 6893U, 5996U, 6886U, 6062U, 
2697
    6952U, 5975U, 6865U, 5924U, 6814U, 5232U, 2212U, 5651U, 
2698
    6521U, 5983U, 6873U, 5660U, 6530U, 5990U, 6880U, 
2699
};
2700
2701
0
static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
2702
0
  II->InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 783);
2703
0
}
2704
2705
} // end namespace llvm
2706
#endif // GET_INSTRINFO_MC_DESC
2707
2708
#ifdef GET_INSTRINFO_HEADER
2709
#undef GET_INSTRINFO_HEADER
2710
namespace llvm {
2711
struct SparcGenInstrInfo : public TargetInstrInfo {
2712
  explicit SparcGenInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u);
2713
  ~SparcGenInstrInfo() override = default;
2714
2715
};
2716
} // end namespace llvm
2717
#endif // GET_INSTRINFO_HEADER
2718
2719
#ifdef GET_INSTRINFO_HELPER_DECLS
2720
#undef GET_INSTRINFO_HELPER_DECLS
2721
2722
2723
#endif // GET_INSTRINFO_HELPER_DECLS
2724
2725
#ifdef GET_INSTRINFO_HELPERS
2726
#undef GET_INSTRINFO_HELPERS
2727
2728
#endif // GET_INSTRINFO_HELPERS
2729
2730
#ifdef GET_INSTRINFO_CTOR_DTOR
2731
#undef GET_INSTRINFO_CTOR_DTOR
2732
namespace llvm {
2733
extern const SparcInstrTable SparcDescs;
2734
extern const unsigned SparcInstrNameIndices[];
2735
extern const char SparcInstrNameData[];
2736
SparcGenInstrInfo::SparcGenInstrInfo(unsigned CFSetupOpcode, unsigned CFDestroyOpcode, unsigned CatchRetOpcode, unsigned ReturnOpcode)
2737
0
  : TargetInstrInfo(CFSetupOpcode, CFDestroyOpcode, CatchRetOpcode, ReturnOpcode) {
2738
0
  InitMCInstrInfo(SparcDescs.Insts, SparcInstrNameIndices, SparcInstrNameData, nullptr, nullptr, 783);
2739
0
}
2740
} // end namespace llvm
2741
#endif // GET_INSTRINFO_CTOR_DTOR
2742
2743
#ifdef GET_INSTRINFO_OPERAND_ENUM
2744
#undef GET_INSTRINFO_OPERAND_ENUM
2745
namespace llvm {
2746
namespace SP {
2747
namespace OpName {
2748
enum {
2749
  OPERAND_LAST
2750
};
2751
} // end namespace OpName
2752
} // end namespace SP
2753
} // end namespace llvm
2754
#endif //GET_INSTRINFO_OPERAND_ENUM
2755
2756
#ifdef GET_INSTRINFO_NAMED_OPS
2757
#undef GET_INSTRINFO_NAMED_OPS
2758
namespace llvm {
2759
namespace SP {
2760
LLVM_READONLY
2761
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
2762
  return -1;
2763
}
2764
} // end namespace SP
2765
} // end namespace llvm
2766
#endif //GET_INSTRINFO_NAMED_OPS
2767
2768
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
2769
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
2770
namespace llvm {
2771
namespace SP {
2772
namespace OpTypes {
2773
enum OperandType {
2774
  ASITag = 0,
2775
  CCOp = 1,
2776
  MEMri = 2,
2777
  MEMrr = 3,
2778
  MembarTag = 4,
2779
  RegCCOp = 5,
2780
  TailRelocSymGOTLoad = 6,
2781
  TailRelocSymTLSAdd = 7,
2782
  TailRelocSymTLSCall = 8,
2783
  TailRelocSymTLSLoad = 9,
2784
  bprtarget = 10,
2785
  bprtarget16 = 11,
2786
  brtarget = 12,
2787
  calltarget = 13,
2788
  f32imm = 14,
2789
  f64imm = 15,
2790
  getPCX = 16,
2791
  i1imm = 17,
2792
  i8imm = 18,
2793
  i16imm = 19,
2794
  i32imm = 20,
2795
  i64imm = 21,
2796
  ptype0 = 22,
2797
  ptype1 = 23,
2798
  ptype2 = 24,
2799
  ptype3 = 25,
2800
  ptype4 = 26,
2801
  ptype5 = 27,
2802
  shift_imm5 = 28,
2803
  shift_imm6 = 29,
2804
  simm13Op = 30,
2805
  type0 = 31,
2806
  type1 = 32,
2807
  type2 = 33,
2808
  type3 = 34,
2809
  type4 = 35,
2810
  type5 = 36,
2811
  untyped_imm_0 = 37,
2812
  ASRRegs = 38,
2813
  CoprocPair = 39,
2814
  CoprocRegs = 40,
2815
  DFPRegs = 41,
2816
  FCCRegs = 42,
2817
  FPRegs = 43,
2818
  I64Regs = 44,
2819
  IntPair = 45,
2820
  IntRegs = 46,
2821
  LowDFPRegs = 47,
2822
  LowQFPRegs = 48,
2823
  PRRegs = 49,
2824
  QFPRegs = 50,
2825
  OPERAND_TYPE_LIST_END
2826
};
2827
} // end namespace OpTypes
2828
} // end namespace SP
2829
} // end namespace llvm
2830
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
2831
2832
#ifdef GET_INSTRINFO_OPERAND_TYPE
2833
#undef GET_INSTRINFO_OPERAND_TYPE
2834
namespace llvm {
2835
namespace SP {
2836
LLVM_READONLY
2837
static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {
2838
  static const uint16_t Offsets[] = {
2839
    /* PHI */
2840
    0,
2841
    /* INLINEASM */
2842
    1,
2843
    /* INLINEASM_BR */
2844
    1,
2845
    /* CFI_INSTRUCTION */
2846
    1,
2847
    /* EH_LABEL */
2848
    2,
2849
    /* GC_LABEL */
2850
    3,
2851
    /* ANNOTATION_LABEL */
2852
    4,
2853
    /* KILL */
2854
    5,
2855
    /* EXTRACT_SUBREG */
2856
    5,
2857
    /* INSERT_SUBREG */
2858
    8,
2859
    /* IMPLICIT_DEF */
2860
    12,
2861
    /* SUBREG_TO_REG */
2862
    13,
2863
    /* COPY_TO_REGCLASS */
2864
    17,
2865
    /* DBG_VALUE */
2866
    20,
2867
    /* DBG_VALUE_LIST */
2868
    20,
2869
    /* DBG_INSTR_REF */
2870
    20,
2871
    /* DBG_PHI */
2872
    20,
2873
    /* DBG_LABEL */
2874
    20,
2875
    /* REG_SEQUENCE */
2876
    21,
2877
    /* COPY */
2878
    23,
2879
    /* BUNDLE */
2880
    25,
2881
    /* LIFETIME_START */
2882
    25,
2883
    /* LIFETIME_END */
2884
    26,
2885
    /* PSEUDO_PROBE */
2886
    27,
2887
    /* ARITH_FENCE */
2888
    31,
2889
    /* STACKMAP */
2890
    33,
2891
    /* FENTRY_CALL */
2892
    35,
2893
    /* PATCHPOINT */
2894
    35,
2895
    /* LOAD_STACK_GUARD */
2896
    41,
2897
    /* PREALLOCATED_SETUP */
2898
    42,
2899
    /* PREALLOCATED_ARG */
2900
    43,
2901
    /* STATEPOINT */
2902
    46,
2903
    /* LOCAL_ESCAPE */
2904
    46,
2905
    /* FAULTING_OP */
2906
    48,
2907
    /* PATCHABLE_OP */
2908
    49,
2909
    /* PATCHABLE_FUNCTION_ENTER */
2910
    49,
2911
    /* PATCHABLE_RET */
2912
    49,
2913
    /* PATCHABLE_FUNCTION_EXIT */
2914
    49,
2915
    /* PATCHABLE_TAIL_CALL */
2916
    49,
2917
    /* PATCHABLE_EVENT_CALL */
2918
    49,
2919
    /* PATCHABLE_TYPED_EVENT_CALL */
2920
    51,
2921
    /* ICALL_BRANCH_FUNNEL */
2922
    54,
2923
    /* MEMBARRIER */
2924
    54,
2925
    /* JUMP_TABLE_DEBUG_INFO */
2926
    54,
2927
    /* G_ASSERT_SEXT */
2928
    55,
2929
    /* G_ASSERT_ZEXT */
2930
    58,
2931
    /* G_ASSERT_ALIGN */
2932
    61,
2933
    /* G_ADD */
2934
    64,
2935
    /* G_SUB */
2936
    67,
2937
    /* G_MUL */
2938
    70,
2939
    /* G_SDIV */
2940
    73,
2941
    /* G_UDIV */
2942
    76,
2943
    /* G_SREM */
2944
    79,
2945
    /* G_UREM */
2946
    82,
2947
    /* G_SDIVREM */
2948
    85,
2949
    /* G_UDIVREM */
2950
    89,
2951
    /* G_AND */
2952
    93,
2953
    /* G_OR */
2954
    96,
2955
    /* G_XOR */
2956
    99,
2957
    /* G_IMPLICIT_DEF */
2958
    102,
2959
    /* G_PHI */
2960
    103,
2961
    /* G_FRAME_INDEX */
2962
    104,
2963
    /* G_GLOBAL_VALUE */
2964
    106,
2965
    /* G_CONSTANT_POOL */
2966
    108,
2967
    /* G_EXTRACT */
2968
    110,
2969
    /* G_UNMERGE_VALUES */
2970
    113,
2971
    /* G_INSERT */
2972
    115,
2973
    /* G_MERGE_VALUES */
2974
    119,
2975
    /* G_BUILD_VECTOR */
2976
    121,
2977
    /* G_BUILD_VECTOR_TRUNC */
2978
    123,
2979
    /* G_CONCAT_VECTORS */
2980
    125,
2981
    /* G_PTRTOINT */
2982
    127,
2983
    /* G_INTTOPTR */
2984
    129,
2985
    /* G_BITCAST */
2986
    131,
2987
    /* G_FREEZE */
2988
    133,
2989
    /* G_CONSTANT_FOLD_BARRIER */
2990
    135,
2991
    /* G_INTRINSIC_FPTRUNC_ROUND */
2992
    137,
2993
    /* G_INTRINSIC_TRUNC */
2994
    140,
2995
    /* G_INTRINSIC_ROUND */
2996
    142,
2997
    /* G_INTRINSIC_LRINT */
2998
    144,
2999
    /* G_INTRINSIC_ROUNDEVEN */
3000
    146,
3001
    /* G_READCYCLECOUNTER */
3002
    148,
3003
    /* G_LOAD */
3004
    149,
3005
    /* G_SEXTLOAD */
3006
    151,
3007
    /* G_ZEXTLOAD */
3008
    153,
3009
    /* G_INDEXED_LOAD */
3010
    155,
3011
    /* G_INDEXED_SEXTLOAD */
3012
    160,
3013
    /* G_INDEXED_ZEXTLOAD */
3014
    165,
3015
    /* G_STORE */
3016
    170,
3017
    /* G_INDEXED_STORE */
3018
    172,
3019
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
3020
    177,
3021
    /* G_ATOMIC_CMPXCHG */
3022
    182,
3023
    /* G_ATOMICRMW_XCHG */
3024
    186,
3025
    /* G_ATOMICRMW_ADD */
3026
    189,
3027
    /* G_ATOMICRMW_SUB */
3028
    192,
3029
    /* G_ATOMICRMW_AND */
3030
    195,
3031
    /* G_ATOMICRMW_NAND */
3032
    198,
3033
    /* G_ATOMICRMW_OR */
3034
    201,
3035
    /* G_ATOMICRMW_XOR */
3036
    204,
3037
    /* G_ATOMICRMW_MAX */
3038
    207,
3039
    /* G_ATOMICRMW_MIN */
3040
    210,
3041
    /* G_ATOMICRMW_UMAX */
3042
    213,
3043
    /* G_ATOMICRMW_UMIN */
3044
    216,
3045
    /* G_ATOMICRMW_FADD */
3046
    219,
3047
    /* G_ATOMICRMW_FSUB */
3048
    222,
3049
    /* G_ATOMICRMW_FMAX */
3050
    225,
3051
    /* G_ATOMICRMW_FMIN */
3052
    228,
3053
    /* G_ATOMICRMW_UINC_WRAP */
3054
    231,
3055
    /* G_ATOMICRMW_UDEC_WRAP */
3056
    234,
3057
    /* G_FENCE */
3058
    237,
3059
    /* G_PREFETCH */
3060
    239,
3061
    /* G_BRCOND */
3062
    243,
3063
    /* G_BRINDIRECT */
3064
    245,
3065
    /* G_INVOKE_REGION_START */
3066
    246,
3067
    /* G_INTRINSIC */
3068
    246,
3069
    /* G_INTRINSIC_W_SIDE_EFFECTS */
3070
    247,
3071
    /* G_INTRINSIC_CONVERGENT */
3072
    248,
3073
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
3074
    249,
3075
    /* G_ANYEXT */
3076
    250,
3077
    /* G_TRUNC */
3078
    252,
3079
    /* G_CONSTANT */
3080
    254,
3081
    /* G_FCONSTANT */
3082
    256,
3083
    /* G_VASTART */
3084
    258,
3085
    /* G_VAARG */
3086
    259,
3087
    /* G_SEXT */
3088
    262,
3089
    /* G_SEXT_INREG */
3090
    264,
3091
    /* G_ZEXT */
3092
    267,
3093
    /* G_SHL */
3094
    269,
3095
    /* G_LSHR */
3096
    272,
3097
    /* G_ASHR */
3098
    275,
3099
    /* G_FSHL */
3100
    278,
3101
    /* G_FSHR */
3102
    282,
3103
    /* G_ROTR */
3104
    286,
3105
    /* G_ROTL */
3106
    289,
3107
    /* G_ICMP */
3108
    292,
3109
    /* G_FCMP */
3110
    296,
3111
    /* G_SELECT */
3112
    300,
3113
    /* G_UADDO */
3114
    304,
3115
    /* G_UADDE */
3116
    308,
3117
    /* G_USUBO */
3118
    313,
3119
    /* G_USUBE */
3120
    317,
3121
    /* G_SADDO */
3122
    322,
3123
    /* G_SADDE */
3124
    326,
3125
    /* G_SSUBO */
3126
    331,
3127
    /* G_SSUBE */
3128
    335,
3129
    /* G_UMULO */
3130
    340,
3131
    /* G_SMULO */
3132
    344,
3133
    /* G_UMULH */
3134
    348,
3135
    /* G_SMULH */
3136
    351,
3137
    /* G_UADDSAT */
3138
    354,
3139
    /* G_SADDSAT */
3140
    357,
3141
    /* G_USUBSAT */
3142
    360,
3143
    /* G_SSUBSAT */
3144
    363,
3145
    /* G_USHLSAT */
3146
    366,
3147
    /* G_SSHLSAT */
3148
    369,
3149
    /* G_SMULFIX */
3150
    372,
3151
    /* G_UMULFIX */
3152
    376,
3153
    /* G_SMULFIXSAT */
3154
    380,
3155
    /* G_UMULFIXSAT */
3156
    384,
3157
    /* G_SDIVFIX */
3158
    388,
3159
    /* G_UDIVFIX */
3160
    392,
3161
    /* G_SDIVFIXSAT */
3162
    396,
3163
    /* G_UDIVFIXSAT */
3164
    400,
3165
    /* G_FADD */
3166
    404,
3167
    /* G_FSUB */
3168
    407,
3169
    /* G_FMUL */
3170
    410,
3171
    /* G_FMA */
3172
    413,
3173
    /* G_FMAD */
3174
    417,
3175
    /* G_FDIV */
3176
    421,
3177
    /* G_FREM */
3178
    424,
3179
    /* G_FPOW */
3180
    427,
3181
    /* G_FPOWI */
3182
    430,
3183
    /* G_FEXP */
3184
    433,
3185
    /* G_FEXP2 */
3186
    435,
3187
    /* G_FEXP10 */
3188
    437,
3189
    /* G_FLOG */
3190
    439,
3191
    /* G_FLOG2 */
3192
    441,
3193
    /* G_FLOG10 */
3194
    443,
3195
    /* G_FLDEXP */
3196
    445,
3197
    /* G_FFREXP */
3198
    448,
3199
    /* G_FNEG */
3200
    451,
3201
    /* G_FPEXT */
3202
    453,
3203
    /* G_FPTRUNC */
3204
    455,
3205
    /* G_FPTOSI */
3206
    457,
3207
    /* G_FPTOUI */
3208
    459,
3209
    /* G_SITOFP */
3210
    461,
3211
    /* G_UITOFP */
3212
    463,
3213
    /* G_FABS */
3214
    465,
3215
    /* G_FCOPYSIGN */
3216
    467,
3217
    /* G_IS_FPCLASS */
3218
    470,
3219
    /* G_FCANONICALIZE */
3220
    473,
3221
    /* G_FMINNUM */
3222
    475,
3223
    /* G_FMAXNUM */
3224
    478,
3225
    /* G_FMINNUM_IEEE */
3226
    481,
3227
    /* G_FMAXNUM_IEEE */
3228
    484,
3229
    /* G_FMINIMUM */
3230
    487,
3231
    /* G_FMAXIMUM */
3232
    490,
3233
    /* G_GET_FPENV */
3234
    493,
3235
    /* G_SET_FPENV */
3236
    494,
3237
    /* G_RESET_FPENV */
3238
    495,
3239
    /* G_GET_FPMODE */
3240
    495,
3241
    /* G_SET_FPMODE */
3242
    496,
3243
    /* G_RESET_FPMODE */
3244
    497,
3245
    /* G_PTR_ADD */
3246
    497,
3247
    /* G_PTRMASK */
3248
    500,
3249
    /* G_SMIN */
3250
    503,
3251
    /* G_SMAX */
3252
    506,
3253
    /* G_UMIN */
3254
    509,
3255
    /* G_UMAX */
3256
    512,
3257
    /* G_ABS */
3258
    515,
3259
    /* G_LROUND */
3260
    517,
3261
    /* G_LLROUND */
3262
    519,
3263
    /* G_BR */
3264
    521,
3265
    /* G_BRJT */
3266
    522,
3267
    /* G_INSERT_VECTOR_ELT */
3268
    525,
3269
    /* G_EXTRACT_VECTOR_ELT */
3270
    529,
3271
    /* G_SHUFFLE_VECTOR */
3272
    532,
3273
    /* G_CTTZ */
3274
    536,
3275
    /* G_CTTZ_ZERO_UNDEF */
3276
    538,
3277
    /* G_CTLZ */
3278
    540,
3279
    /* G_CTLZ_ZERO_UNDEF */
3280
    542,
3281
    /* G_CTPOP */
3282
    544,
3283
    /* G_BSWAP */
3284
    546,
3285
    /* G_BITREVERSE */
3286
    548,
3287
    /* G_FCEIL */
3288
    550,
3289
    /* G_FCOS */
3290
    552,
3291
    /* G_FSIN */
3292
    554,
3293
    /* G_FSQRT */
3294
    556,
3295
    /* G_FFLOOR */
3296
    558,
3297
    /* G_FRINT */
3298
    560,
3299
    /* G_FNEARBYINT */
3300
    562,
3301
    /* G_ADDRSPACE_CAST */
3302
    564,
3303
    /* G_BLOCK_ADDR */
3304
    566,
3305
    /* G_JUMP_TABLE */
3306
    568,
3307
    /* G_DYN_STACKALLOC */
3308
    570,
3309
    /* G_STACKSAVE */
3310
    573,
3311
    /* G_STACKRESTORE */
3312
    574,
3313
    /* G_STRICT_FADD */
3314
    575,
3315
    /* G_STRICT_FSUB */
3316
    578,
3317
    /* G_STRICT_FMUL */
3318
    581,
3319
    /* G_STRICT_FDIV */
3320
    584,
3321
    /* G_STRICT_FREM */
3322
    587,
3323
    /* G_STRICT_FMA */
3324
    590,
3325
    /* G_STRICT_FSQRT */
3326
    594,
3327
    /* G_STRICT_FLDEXP */
3328
    596,
3329
    /* G_READ_REGISTER */
3330
    599,
3331
    /* G_WRITE_REGISTER */
3332
    601,
3333
    /* G_MEMCPY */
3334
    603,
3335
    /* G_MEMCPY_INLINE */
3336
    607,
3337
    /* G_MEMMOVE */
3338
    610,
3339
    /* G_MEMSET */
3340
    614,
3341
    /* G_BZERO */
3342
    618,
3343
    /* G_VECREDUCE_SEQ_FADD */
3344
    621,
3345
    /* G_VECREDUCE_SEQ_FMUL */
3346
    624,
3347
    /* G_VECREDUCE_FADD */
3348
    627,
3349
    /* G_VECREDUCE_FMUL */
3350
    629,
3351
    /* G_VECREDUCE_FMAX */
3352
    631,
3353
    /* G_VECREDUCE_FMIN */
3354
    633,
3355
    /* G_VECREDUCE_FMAXIMUM */
3356
    635,
3357
    /* G_VECREDUCE_FMINIMUM */
3358
    637,
3359
    /* G_VECREDUCE_ADD */
3360
    639,
3361
    /* G_VECREDUCE_MUL */
3362
    641,
3363
    /* G_VECREDUCE_AND */
3364
    643,
3365
    /* G_VECREDUCE_OR */
3366
    645,
3367
    /* G_VECREDUCE_XOR */
3368
    647,
3369
    /* G_VECREDUCE_SMAX */
3370
    649,
3371
    /* G_VECREDUCE_SMIN */
3372
    651,
3373
    /* G_VECREDUCE_UMAX */
3374
    653,
3375
    /* G_VECREDUCE_UMIN */
3376
    655,
3377
    /* G_SBFX */
3378
    657,
3379
    /* G_UBFX */
3380
    661,
3381
    /* ADJCALLSTACKDOWN */
3382
    665,
3383
    /* ADJCALLSTACKUP */
3384
    667,
3385
    /* GETPCX */
3386
    669,
3387
    /* SELECT_CC_DFP_FCC */
3388
    670,
3389
    /* SELECT_CC_DFP_ICC */
3390
    674,
3391
    /* SELECT_CC_DFP_XCC */
3392
    678,
3393
    /* SELECT_CC_FP_FCC */
3394
    682,
3395
    /* SELECT_CC_FP_ICC */
3396
    686,
3397
    /* SELECT_CC_FP_XCC */
3398
    690,
3399
    /* SELECT_CC_Int_FCC */
3400
    694,
3401
    /* SELECT_CC_Int_ICC */
3402
    698,
3403
    /* SELECT_CC_Int_XCC */
3404
    702,
3405
    /* SELECT_CC_QFP_FCC */
3406
    706,
3407
    /* SELECT_CC_QFP_ICC */
3408
    710,
3409
    /* SELECT_CC_QFP_XCC */
3410
    714,
3411
    /* SET */
3412
    718,
3413
    /* SETX */
3414
    720,
3415
    /* ADDCCri */
3416
    723,
3417
    /* ADDCCrr */
3418
    726,
3419
    /* ADDCri */
3420
    729,
3421
    /* ADDCrr */
3422
    732,
3423
    /* ADDEri */
3424
    735,
3425
    /* ADDErr */
3426
    738,
3427
    /* ADDXC */
3428
    741,
3429
    /* ADDXCCC */
3430
    744,
3431
    /* ADDri */
3432
    747,
3433
    /* ADDrr */
3434
    750,
3435
    /* ALIGNADDR */
3436
    753,
3437
    /* ALIGNADDRL */
3438
    756,
3439
    /* ANDCCri */
3440
    759,
3441
    /* ANDCCrr */
3442
    762,
3443
    /* ANDNCCri */
3444
    765,
3445
    /* ANDNCCrr */
3446
    768,
3447
    /* ANDNri */
3448
    771,
3449
    /* ANDNrr */
3450
    774,
3451
    /* ANDri */
3452
    777,
3453
    /* ANDrr */
3454
    780,
3455
    /* ARRAY16 */
3456
    783,
3457
    /* ARRAY32 */
3458
    786,
3459
    /* ARRAY8 */
3460
    789,
3461
    /* BA */
3462
    792,
3463
    /* BCOND */
3464
    793,
3465
    /* BCONDA */
3466
    795,
3467
    /* BINDri */
3468
    797,
3469
    /* BINDrr */
3470
    799,
3471
    /* BMASK */
3472
    801,
3473
    /* BPFCC */
3474
    804,
3475
    /* BPFCCA */
3476
    807,
3477
    /* BPFCCANT */
3478
    810,
3479
    /* BPFCCNT */
3480
    813,
3481
    /* BPICC */
3482
    816,
3483
    /* BPICCA */
3484
    818,
3485
    /* BPICCANT */
3486
    820,
3487
    /* BPICCNT */
3488
    822,
3489
    /* BPR */
3490
    824,
3491
    /* BPRA */
3492
    827,
3493
    /* BPRANT */
3494
    830,
3495
    /* BPRNT */
3496
    833,
3497
    /* BPXCC */
3498
    836,
3499
    /* BPXCCA */
3500
    838,
3501
    /* BPXCCANT */
3502
    840,
3503
    /* BPXCCNT */
3504
    842,
3505
    /* BSHUFFLE */
3506
    844,
3507
    /* CALL */
3508
    847,
3509
    /* CALLri */
3510
    848,
3511
    /* CALLrr */
3512
    850,
3513
    /* CASAri */
3514
    852,
3515
    /* CASArr */
3516
    856,
3517
    /* CASXAri */
3518
    861,
3519
    /* CASXArr */
3520
    865,
3521
    /* CBCOND */
3522
    870,
3523
    /* CBCONDA */
3524
    872,
3525
    /* CMASK16 */
3526
    874,
3527
    /* CMASK32 */
3528
    875,
3529
    /* CMASK8 */
3530
    876,
3531
    /* DONE */
3532
    877,
3533
    /* EDGE16 */
3534
    877,
3535
    /* EDGE16L */
3536
    880,
3537
    /* EDGE16LN */
3538
    883,
3539
    /* EDGE16N */
3540
    886,
3541
    /* EDGE32 */
3542
    889,
3543
    /* EDGE32L */
3544
    892,
3545
    /* EDGE32LN */
3546
    895,
3547
    /* EDGE32N */
3548
    898,
3549
    /* EDGE8 */
3550
    901,
3551
    /* EDGE8L */
3552
    904,
3553
    /* EDGE8LN */
3554
    907,
3555
    /* EDGE8N */
3556
    910,
3557
    /* FABSD */
3558
    913,
3559
    /* FABSQ */
3560
    915,
3561
    /* FABSS */
3562
    917,
3563
    /* FADDD */
3564
    919,
3565
    /* FADDQ */
3566
    922,
3567
    /* FADDS */
3568
    925,
3569
    /* FALIGNADATA */
3570
    928,
3571
    /* FAND */
3572
    931,
3573
    /* FANDNOT1 */
3574
    934,
3575
    /* FANDNOT1S */
3576
    937,
3577
    /* FANDNOT2 */
3578
    940,
3579
    /* FANDNOT2S */
3580
    943,
3581
    /* FANDS */
3582
    946,
3583
    /* FBCOND */
3584
    949,
3585
    /* FBCONDA */
3586
    951,
3587
    /* FBCONDA_V9 */
3588
    953,
3589
    /* FBCOND_V9 */
3590
    955,
3591
    /* FCHKSM16 */
3592
    957,
3593
    /* FCMPD */
3594
    960,
3595
    /* FCMPD_V9 */
3596
    962,
3597
    /* FCMPEQ16 */
3598
    964,
3599
    /* FCMPEQ32 */
3600
    967,
3601
    /* FCMPGT16 */
3602
    970,
3603
    /* FCMPGT32 */
3604
    973,
3605
    /* FCMPLE16 */
3606
    976,
3607
    /* FCMPLE32 */
3608
    979,
3609
    /* FCMPNE16 */
3610
    982,
3611
    /* FCMPNE32 */
3612
    985,
3613
    /* FCMPQ */
3614
    988,
3615
    /* FCMPQ_V9 */
3616
    990,
3617
    /* FCMPS */
3618
    992,
3619
    /* FCMPS_V9 */
3620
    994,
3621
    /* FDIVD */
3622
    996,
3623
    /* FDIVQ */
3624
    999,
3625
    /* FDIVS */
3626
    1002,
3627
    /* FDMULQ */
3628
    1005,
3629
    /* FDTOI */
3630
    1008,
3631
    /* FDTOQ */
3632
    1010,
3633
    /* FDTOS */
3634
    1012,
3635
    /* FDTOX */
3636
    1014,
3637
    /* FEXPAND */
3638
    1016,
3639
    /* FHADDD */
3640
    1018,
3641
    /* FHADDS */
3642
    1021,
3643
    /* FHSUBD */
3644
    1024,
3645
    /* FHSUBS */
3646
    1027,
3647
    /* FITOD */
3648
    1030,
3649
    /* FITOQ */
3650
    1032,
3651
    /* FITOS */
3652
    1034,
3653
    /* FLCMPD */
3654
    1036,
3655
    /* FLCMPS */
3656
    1039,
3657
    /* FLUSH */
3658
    1042,
3659
    /* FLUSHW */
3660
    1042,
3661
    /* FLUSHri */
3662
    1042,
3663
    /* FLUSHrr */
3664
    1044,
3665
    /* FMEAN16 */
3666
    1046,
3667
    /* FMOVD */
3668
    1049,
3669
    /* FMOVD_FCC */
3670
    1051,
3671
    /* FMOVD_ICC */
3672
    1055,
3673
    /* FMOVD_XCC */
3674
    1059,
3675
    /* FMOVQ */
3676
    1063,
3677
    /* FMOVQ_FCC */
3678
    1065,
3679
    /* FMOVQ_ICC */
3680
    1069,
3681
    /* FMOVQ_XCC */
3682
    1073,
3683
    /* FMOVRD */
3684
    1077,
3685
    /* FMOVRQ */
3686
    1082,
3687
    /* FMOVRS */
3688
    1087,
3689
    /* FMOVS */
3690
    1092,
3691
    /* FMOVS_FCC */
3692
    1094,
3693
    /* FMOVS_ICC */
3694
    1098,
3695
    /* FMOVS_XCC */
3696
    1102,
3697
    /* FMUL8SUX16 */
3698
    1106,
3699
    /* FMUL8ULX16 */
3700
    1109,
3701
    /* FMUL8X16 */
3702
    1112,
3703
    /* FMUL8X16AL */
3704
    1115,
3705
    /* FMUL8X16AU */
3706
    1118,
3707
    /* FMULD */
3708
    1121,
3709
    /* FMULD8SUX16 */
3710
    1124,
3711
    /* FMULD8ULX16 */
3712
    1127,
3713
    /* FMULQ */
3714
    1130,
3715
    /* FMULS */
3716
    1133,
3717
    /* FNADDD */
3718
    1136,
3719
    /* FNADDS */
3720
    1139,
3721
    /* FNAND */
3722
    1142,
3723
    /* FNANDS */
3724
    1145,
3725
    /* FNEGD */
3726
    1148,
3727
    /* FNEGQ */
3728
    1150,
3729
    /* FNEGS */
3730
    1152,
3731
    /* FNHADDD */
3732
    1154,
3733
    /* FNHADDS */
3734
    1157,
3735
    /* FNMULD */
3736
    1160,
3737
    /* FNMULS */
3738
    1163,
3739
    /* FNOR */
3740
    1166,
3741
    /* FNORS */
3742
    1169,
3743
    /* FNOT1 */
3744
    1172,
3745
    /* FNOT1S */
3746
    1174,
3747
    /* FNOT2 */
3748
    1176,
3749
    /* FNOT2S */
3750
    1178,
3751
    /* FNSMULD */
3752
    1180,
3753
    /* FONE */
3754
    1183,
3755
    /* FONES */
3756
    1185,
3757
    /* FOR */
3758
    1187,
3759
    /* FORNOT1 */
3760
    1190,
3761
    /* FORNOT1S */
3762
    1193,
3763
    /* FORNOT2 */
3764
    1196,
3765
    /* FORNOT2S */
3766
    1199,
3767
    /* FORS */
3768
    1202,
3769
    /* FPACK16 */
3770
    1205,
3771
    /* FPACK32 */
3772
    1207,
3773
    /* FPACKFIX */
3774
    1210,
3775
    /* FPADD16 */
3776
    1212,
3777
    /* FPADD16S */
3778
    1215,
3779
    /* FPADD32 */
3780
    1218,
3781
    /* FPADD32S */
3782
    1221,
3783
    /* FPADD64 */
3784
    1224,
3785
    /* FPMERGE */
3786
    1227,
3787
    /* FPSUB16 */
3788
    1230,
3789
    /* FPSUB16S */
3790
    1233,
3791
    /* FPSUB32 */
3792
    1236,
3793
    /* FPSUB32S */
3794
    1239,
3795
    /* FQTOD */
3796
    1242,
3797
    /* FQTOI */
3798
    1244,
3799
    /* FQTOS */
3800
    1246,
3801
    /* FQTOX */
3802
    1248,
3803
    /* FSLAS16 */
3804
    1250,
3805
    /* FSLAS32 */
3806
    1253,
3807
    /* FSLL16 */
3808
    1256,
3809
    /* FSLL32 */
3810
    1259,
3811
    /* FSMULD */
3812
    1262,
3813
    /* FSQRTD */
3814
    1265,
3815
    /* FSQRTQ */
3816
    1267,
3817
    /* FSQRTS */
3818
    1269,
3819
    /* FSRA16 */
3820
    1271,
3821
    /* FSRA32 */
3822
    1274,
3823
    /* FSRC1 */
3824
    1277,
3825
    /* FSRC1S */
3826
    1279,
3827
    /* FSRC2 */
3828
    1281,
3829
    /* FSRC2S */
3830
    1283,
3831
    /* FSRL16 */
3832
    1285,
3833
    /* FSRL32 */
3834
    1288,
3835
    /* FSTOD */
3836
    1291,
3837
    /* FSTOI */
3838
    1293,
3839
    /* FSTOQ */
3840
    1295,
3841
    /* FSTOX */
3842
    1297,
3843
    /* FSUBD */
3844
    1299,
3845
    /* FSUBQ */
3846
    1302,
3847
    /* FSUBS */
3848
    1305,
3849
    /* FXNOR */
3850
    1308,
3851
    /* FXNORS */
3852
    1311,
3853
    /* FXOR */
3854
    1314,
3855
    /* FXORS */
3856
    1317,
3857
    /* FXTOD */
3858
    1320,
3859
    /* FXTOQ */
3860
    1322,
3861
    /* FXTOS */
3862
    1324,
3863
    /* FZERO */
3864
    1326,
3865
    /* FZEROS */
3866
    1328,
3867
    /* GDOP_LDXrr */
3868
    1330,
3869
    /* GDOP_LDrr */
3870
    1334,
3871
    /* JMPLri */
3872
    1338,
3873
    /* JMPLrr */
3874
    1341,
3875
    /* LDAri */
3876
    1344,
3877
    /* LDArr */
3878
    1347,
3879
    /* LDCSRri */
3880
    1351,
3881
    /* LDCSRrr */
3882
    1353,
3883
    /* LDCri */
3884
    1355,
3885
    /* LDCrr */
3886
    1358,
3887
    /* LDDAri */
3888
    1361,
3889
    /* LDDArr */
3890
    1364,
3891
    /* LDDCri */
3892
    1368,
3893
    /* LDDCrr */
3894
    1371,
3895
    /* LDDFAri */
3896
    1374,
3897
    /* LDDFArr */
3898
    1377,
3899
    /* LDDFri */
3900
    1381,
3901
    /* LDDFrr */
3902
    1384,
3903
    /* LDDri */
3904
    1387,
3905
    /* LDDrr */
3906
    1390,
3907
    /* LDFAri */
3908
    1393,
3909
    /* LDFArr */
3910
    1396,
3911
    /* LDFSRri */
3912
    1400,
3913
    /* LDFSRrr */
3914
    1402,
3915
    /* LDFri */
3916
    1404,
3917
    /* LDFrr */
3918
    1407,
3919
    /* LDQFAri */
3920
    1410,
3921
    /* LDQFArr */
3922
    1413,
3923
    /* LDQFri */
3924
    1417,
3925
    /* LDQFrr */
3926
    1420,
3927
    /* LDSBAri */
3928
    1423,
3929
    /* LDSBArr */
3930
    1426,
3931
    /* LDSBri */
3932
    1430,
3933
    /* LDSBrr */
3934
    1433,
3935
    /* LDSHAri */
3936
    1436,
3937
    /* LDSHArr */
3938
    1439,
3939
    /* LDSHri */
3940
    1443,
3941
    /* LDSHrr */
3942
    1446,
3943
    /* LDSTUBAri */
3944
    1449,
3945
    /* LDSTUBArr */
3946
    1452,
3947
    /* LDSTUBri */
3948
    1456,
3949
    /* LDSTUBrr */
3950
    1459,
3951
    /* LDSWAri */
3952
    1462,
3953
    /* LDSWArr */
3954
    1465,
3955
    /* LDSWri */
3956
    1469,
3957
    /* LDSWrr */
3958
    1472,
3959
    /* LDUBAri */
3960
    1475,
3961
    /* LDUBArr */
3962
    1478,
3963
    /* LDUBri */
3964
    1482,
3965
    /* LDUBrr */
3966
    1485,
3967
    /* LDUHAri */
3968
    1488,
3969
    /* LDUHArr */
3970
    1491,
3971
    /* LDUHri */
3972
    1495,
3973
    /* LDUHrr */
3974
    1498,
3975
    /* LDXAri */
3976
    1501,
3977
    /* LDXArr */
3978
    1504,
3979
    /* LDXFSRri */
3980
    1508,
3981
    /* LDXFSRrr */
3982
    1510,
3983
    /* LDXri */
3984
    1512,
3985
    /* LDXrr */
3986
    1515,
3987
    /* LDri */
3988
    1518,
3989
    /* LDrr */
3990
    1521,
3991
    /* LZCNT */
3992
    1524,
3993
    /* MEMBARi */
3994
    1526,
3995
    /* MOVDTOX */
3996
    1527,
3997
    /* MOVFCCri */
3998
    1529,
3999
    /* MOVFCCrr */
4000
    1533,
4001
    /* MOVICCri */
4002
    1537,
4003
    /* MOVICCrr */
4004
    1541,
4005
    /* MOVRri */
4006
    1545,
4007
    /* MOVRrr */
4008
    1550,
4009
    /* MOVSTOSW */
4010
    1555,
4011
    /* MOVSTOUW */
4012
    1557,
4013
    /* MOVWTOS */
4014
    1559,
4015
    /* MOVXCCri */
4016
    1561,
4017
    /* MOVXCCrr */
4018
    1565,
4019
    /* MOVXTOD */
4020
    1569,
4021
    /* MULSCCri */
4022
    1571,
4023
    /* MULSCCrr */
4024
    1574,
4025
    /* MULXri */
4026
    1577,
4027
    /* MULXrr */
4028
    1580,
4029
    /* NOP */
4030
    1583,
4031
    /* ORCCri */
4032
    1583,
4033
    /* ORCCrr */
4034
    1586,
4035
    /* ORNCCri */
4036
    1589,
4037
    /* ORNCCrr */
4038
    1592,
4039
    /* ORNri */
4040
    1595,
4041
    /* ORNrr */
4042
    1598,
4043
    /* ORri */
4044
    1601,
4045
    /* ORrr */
4046
    1604,
4047
    /* PDIST */
4048
    1607,
4049
    /* PDISTN */
4050
    1610,
4051
    /* POPCrr */
4052
    1613,
4053
    /* PREFETCHi */
4054
    1615,
4055
    /* PREFETCHr */
4056
    1618,
4057
    /* PWRPSRri */
4058
    1621,
4059
    /* PWRPSRrr */
4060
    1623,
4061
    /* RDASR */
4062
    1625,
4063
    /* RDFQ */
4064
    1627,
4065
    /* RDPR */
4066
    1628,
4067
    /* RDPSR */
4068
    1630,
4069
    /* RDTBR */
4070
    1631,
4071
    /* RDWIM */
4072
    1632,
4073
    /* RESTORED */
4074
    1633,
4075
    /* RESTOREri */
4076
    1633,
4077
    /* RESTORErr */
4078
    1636,
4079
    /* RET */
4080
    1639,
4081
    /* RETL */
4082
    1640,
4083
    /* RETRY */
4084
    1641,
4085
    /* RETTri */
4086
    1641,
4087
    /* RETTrr */
4088
    1643,
4089
    /* SAVED */
4090
    1645,
4091
    /* SAVEri */
4092
    1645,
4093
    /* SAVErr */
4094
    1648,
4095
    /* SDIVCCri */
4096
    1651,
4097
    /* SDIVCCrr */
4098
    1654,
4099
    /* SDIVXri */
4100
    1657,
4101
    /* SDIVXrr */
4102
    1660,
4103
    /* SDIVri */
4104
    1663,
4105
    /* SDIVrr */
4106
    1666,
4107
    /* SETHIi */
4108
    1669,
4109
    /* SHUTDOWN */
4110
    1671,
4111
    /* SIAM */
4112
    1671,
4113
    /* SIR */
4114
    1671,
4115
    /* SLLXri */
4116
    1672,
4117
    /* SLLXrr */
4118
    1675,
4119
    /* SLLri */
4120
    1678,
4121
    /* SLLrr */
4122
    1681,
4123
    /* SMACri */
4124
    1684,
4125
    /* SMACrr */
4126
    1688,
4127
    /* SMULCCri */
4128
    1692,
4129
    /* SMULCCrr */
4130
    1695,
4131
    /* SMULri */
4132
    1698,
4133
    /* SMULrr */
4134
    1701,
4135
    /* SRAXri */
4136
    1704,
4137
    /* SRAXrr */
4138
    1707,
4139
    /* SRAri */
4140
    1710,
4141
    /* SRArr */
4142
    1713,
4143
    /* SRLXri */
4144
    1716,
4145
    /* SRLXrr */
4146
    1719,
4147
    /* SRLri */
4148
    1722,
4149
    /* SRLrr */
4150
    1725,
4151
    /* STAri */
4152
    1728,
4153
    /* STArr */
4154
    1731,
4155
    /* STBAR */
4156
    1735,
4157
    /* STBAri */
4158
    1735,
4159
    /* STBArr */
4160
    1738,
4161
    /* STBri */
4162
    1742,
4163
    /* STBrr */
4164
    1745,
4165
    /* STCSRri */
4166
    1748,
4167
    /* STCSRrr */
4168
    1750,
4169
    /* STCri */
4170
    1752,
4171
    /* STCrr */
4172
    1755,
4173
    /* STDAri */
4174
    1758,
4175
    /* STDArr */
4176
    1761,
4177
    /* STDCQri */
4178
    1765,
4179
    /* STDCQrr */
4180
    1767,
4181
    /* STDCri */
4182
    1769,
4183
    /* STDCrr */
4184
    1772,
4185
    /* STDFAri */
4186
    1775,
4187
    /* STDFArr */
4188
    1778,
4189
    /* STDFQri */
4190
    1782,
4191
    /* STDFQrr */
4192
    1784,
4193
    /* STDFri */
4194
    1786,
4195
    /* STDFrr */
4196
    1789,
4197
    /* STDri */
4198
    1792,
4199
    /* STDrr */
4200
    1795,
4201
    /* STFAri */
4202
    1798,
4203
    /* STFArr */
4204
    1801,
4205
    /* STFSRri */
4206
    1805,
4207
    /* STFSRrr */
4208
    1807,
4209
    /* STFri */
4210
    1809,
4211
    /* STFrr */
4212
    1812,
4213
    /* STHAri */
4214
    1815,
4215
    /* STHArr */
4216
    1818,
4217
    /* STHri */
4218
    1822,
4219
    /* STHrr */
4220
    1825,
4221
    /* STQFAri */
4222
    1828,
4223
    /* STQFArr */
4224
    1831,
4225
    /* STQFri */
4226
    1835,
4227
    /* STQFrr */
4228
    1838,
4229
    /* STXAri */
4230
    1841,
4231
    /* STXArr */
4232
    1844,
4233
    /* STXFSRri */
4234
    1848,
4235
    /* STXFSRrr */
4236
    1850,
4237
    /* STXri */
4238
    1852,
4239
    /* STXrr */
4240
    1855,
4241
    /* STri */
4242
    1858,
4243
    /* STrr */
4244
    1861,
4245
    /* SUBCCri */
4246
    1864,
4247
    /* SUBCCrr */
4248
    1867,
4249
    /* SUBCri */
4250
    1870,
4251
    /* SUBCrr */
4252
    1873,
4253
    /* SUBEri */
4254
    1876,
4255
    /* SUBErr */
4256
    1879,
4257
    /* SUBri */
4258
    1882,
4259
    /* SUBrr */
4260
    1885,
4261
    /* SWAPAri */
4262
    1888,
4263
    /* SWAPArr */
4264
    1892,
4265
    /* SWAPri */
4266
    1897,
4267
    /* SWAPrr */
4268
    1901,
4269
    /* TA1 */
4270
    1905,
4271
    /* TA3 */
4272
    1905,
4273
    /* TA5 */
4274
    1905,
4275
    /* TADDCCTVri */
4276
    1905,
4277
    /* TADDCCTVrr */
4278
    1908,
4279
    /* TADDCCri */
4280
    1911,
4281
    /* TADDCCrr */
4282
    1914,
4283
    /* TAIL_CALL */
4284
    1917,
4285
    /* TAIL_CALLri */
4286
    1918,
4287
    /* TICCri */
4288
    1920,
4289
    /* TICCrr */
4290
    1923,
4291
    /* TLS_ADDrr */
4292
    1926,
4293
    /* TLS_CALL */
4294
    1930,
4295
    /* TLS_LDXrr */
4296
    1932,
4297
    /* TLS_LDrr */
4298
    1936,
4299
    /* TRAPri */
4300
    1940,
4301
    /* TRAPrr */
4302
    1943,
4303
    /* TSUBCCTVri */
4304
    1946,
4305
    /* TSUBCCTVrr */
4306
    1949,
4307
    /* TSUBCCri */
4308
    1952,
4309
    /* TSUBCCrr */
4310
    1955,
4311
    /* TXCCri */
4312
    1958,
4313
    /* TXCCrr */
4314
    1961,
4315
    /* UDIVCCri */
4316
    1964,
4317
    /* UDIVCCrr */
4318
    1967,
4319
    /* UDIVXri */
4320
    1970,
4321
    /* UDIVXrr */
4322
    1973,
4323
    /* UDIVri */
4324
    1976,
4325
    /* UDIVrr */
4326
    1979,
4327
    /* UMACri */
4328
    1982,
4329
    /* UMACrr */
4330
    1986,
4331
    /* UMULCCri */
4332
    1990,
4333
    /* UMULCCrr */
4334
    1993,
4335
    /* UMULXHI */
4336
    1996,
4337
    /* UMULri */
4338
    1999,
4339
    /* UMULrr */
4340
    2002,
4341
    /* UNIMP */
4342
    2005,
4343
    /* V9FCMPD */
4344
    2006,
4345
    /* V9FCMPED */
4346
    2009,
4347
    /* V9FCMPEQ */
4348
    2012,
4349
    /* V9FCMPES */
4350
    2015,
4351
    /* V9FCMPQ */
4352
    2018,
4353
    /* V9FCMPS */
4354
    2021,
4355
    /* V9FMOVD_FCC */
4356
    2024,
4357
    /* V9FMOVQ_FCC */
4358
    2029,
4359
    /* V9FMOVS_FCC */
4360
    2034,
4361
    /* V9MOVFCCri */
4362
    2039,
4363
    /* V9MOVFCCrr */
4364
    2044,
4365
    /* WRASRri */
4366
    2049,
4367
    /* WRASRrr */
4368
    2052,
4369
    /* WRPRri */
4370
    2055,
4371
    /* WRPRrr */
4372
    2058,
4373
    /* WRPSRri */
4374
    2061,
4375
    /* WRPSRrr */
4376
    2063,
4377
    /* WRTBRri */
4378
    2065,
4379
    /* WRTBRrr */
4380
    2067,
4381
    /* WRWIMri */
4382
    2069,
4383
    /* WRWIMrr */
4384
    2071,
4385
    /* XMULX */
4386
    2073,
4387
    /* XMULXHI */
4388
    2076,
4389
    /* XNORCCri */
4390
    2079,
4391
    /* XNORCCrr */
4392
    2082,
4393
    /* XNORri */
4394
    2085,
4395
    /* XNORrr */
4396
    2088,
4397
    /* XORCCri */
4398
    2091,
4399
    /* XORCCrr */
4400
    2094,
4401
    /* XORri */
4402
    2097,
4403
    /* XORrr */
4404
    2100,
4405
  };
4406
4407
  using namespace OpTypes;
4408
  static const int8_t OpcodeOperandTypes[] = {
4409
    
4410
    /* PHI */
4411
    -1, 
4412
    /* INLINEASM */
4413
    /* INLINEASM_BR */
4414
    /* CFI_INSTRUCTION */
4415
    i32imm, 
4416
    /* EH_LABEL */
4417
    i32imm, 
4418
    /* GC_LABEL */
4419
    i32imm, 
4420
    /* ANNOTATION_LABEL */
4421
    i32imm, 
4422
    /* KILL */
4423
    /* EXTRACT_SUBREG */
4424
    -1, -1, i32imm, 
4425
    /* INSERT_SUBREG */
4426
    -1, -1, -1, i32imm, 
4427
    /* IMPLICIT_DEF */
4428
    -1, 
4429
    /* SUBREG_TO_REG */
4430
    -1, -1, -1, i32imm, 
4431
    /* COPY_TO_REGCLASS */
4432
    -1, -1, i32imm, 
4433
    /* DBG_VALUE */
4434
    /* DBG_VALUE_LIST */
4435
    /* DBG_INSTR_REF */
4436
    /* DBG_PHI */
4437
    /* DBG_LABEL */
4438
    -1, 
4439
    /* REG_SEQUENCE */
4440
    -1, -1, 
4441
    /* COPY */
4442
    -1, -1, 
4443
    /* BUNDLE */
4444
    /* LIFETIME_START */
4445
    i32imm, 
4446
    /* LIFETIME_END */
4447
    i32imm, 
4448
    /* PSEUDO_PROBE */
4449
    i64imm, i64imm, i8imm, i32imm, 
4450
    /* ARITH_FENCE */
4451
    -1, -1, 
4452
    /* STACKMAP */
4453
    i64imm, i32imm, 
4454
    /* FENTRY_CALL */
4455
    /* PATCHPOINT */
4456
    -1, i64imm, i32imm, -1, i32imm, i32imm, 
4457
    /* LOAD_STACK_GUARD */
4458
    -1, 
4459
    /* PREALLOCATED_SETUP */
4460
    i32imm, 
4461
    /* PREALLOCATED_ARG */
4462
    -1, i32imm, i32imm, 
4463
    /* STATEPOINT */
4464
    /* LOCAL_ESCAPE */
4465
    -1, i32imm, 
4466
    /* FAULTING_OP */
4467
    -1, 
4468
    /* PATCHABLE_OP */
4469
    /* PATCHABLE_FUNCTION_ENTER */
4470
    /* PATCHABLE_RET */
4471
    /* PATCHABLE_FUNCTION_EXIT */
4472
    /* PATCHABLE_TAIL_CALL */
4473
    /* PATCHABLE_EVENT_CALL */
4474
    -1, -1, 
4475
    /* PATCHABLE_TYPED_EVENT_CALL */
4476
    -1, -1, -1, 
4477
    /* ICALL_BRANCH_FUNNEL */
4478
    /* MEMBARRIER */
4479
    /* JUMP_TABLE_DEBUG_INFO */
4480
    i64imm, 
4481
    /* G_ASSERT_SEXT */
4482
    type0, type0, untyped_imm_0, 
4483
    /* G_ASSERT_ZEXT */
4484
    type0, type0, untyped_imm_0, 
4485
    /* G_ASSERT_ALIGN */
4486
    type0, type0, untyped_imm_0, 
4487
    /* G_ADD */
4488
    type0, type0, type0, 
4489
    /* G_SUB */
4490
    type0, type0, type0, 
4491
    /* G_MUL */
4492
    type0, type0, type0, 
4493
    /* G_SDIV */
4494
    type0, type0, type0, 
4495
    /* G_UDIV */
4496
    type0, type0, type0, 
4497
    /* G_SREM */
4498
    type0, type0, type0, 
4499
    /* G_UREM */
4500
    type0, type0, type0, 
4501
    /* G_SDIVREM */
4502
    type0, type0, type0, type0, 
4503
    /* G_UDIVREM */
4504
    type0, type0, type0, type0, 
4505
    /* G_AND */
4506
    type0, type0, type0, 
4507
    /* G_OR */
4508
    type0, type0, type0, 
4509
    /* G_XOR */
4510
    type0, type0, type0, 
4511
    /* G_IMPLICIT_DEF */
4512
    type0, 
4513
    /* G_PHI */
4514
    type0, 
4515
    /* G_FRAME_INDEX */
4516
    type0, -1, 
4517
    /* G_GLOBAL_VALUE */
4518
    type0, -1, 
4519
    /* G_CONSTANT_POOL */
4520
    type0, -1, 
4521
    /* G_EXTRACT */
4522
    type0, type1, untyped_imm_0, 
4523
    /* G_UNMERGE_VALUES */
4524
    type0, type1, 
4525
    /* G_INSERT */
4526
    type0, type0, type1, untyped_imm_0, 
4527
    /* G_MERGE_VALUES */
4528
    type0, type1, 
4529
    /* G_BUILD_VECTOR */
4530
    type0, type1, 
4531
    /* G_BUILD_VECTOR_TRUNC */
4532
    type0, type1, 
4533
    /* G_CONCAT_VECTORS */
4534
    type0, type1, 
4535
    /* G_PTRTOINT */
4536
    type0, type1, 
4537
    /* G_INTTOPTR */
4538
    type0, type1, 
4539
    /* G_BITCAST */
4540
    type0, type1, 
4541
    /* G_FREEZE */
4542
    type0, type0, 
4543
    /* G_CONSTANT_FOLD_BARRIER */
4544
    type0, type0, 
4545
    /* G_INTRINSIC_FPTRUNC_ROUND */
4546
    type0, type1, i32imm, 
4547
    /* G_INTRINSIC_TRUNC */
4548
    type0, type0, 
4549
    /* G_INTRINSIC_ROUND */
4550
    type0, type0, 
4551
    /* G_INTRINSIC_LRINT */
4552
    type0, type1, 
4553
    /* G_INTRINSIC_ROUNDEVEN */
4554
    type0, type0, 
4555
    /* G_READCYCLECOUNTER */
4556
    type0, 
4557
    /* G_LOAD */
4558
    type0, ptype1, 
4559
    /* G_SEXTLOAD */
4560
    type0, ptype1, 
4561
    /* G_ZEXTLOAD */
4562
    type0, ptype1, 
4563
    /* G_INDEXED_LOAD */
4564
    type0, ptype1, ptype1, type2, -1, 
4565
    /* G_INDEXED_SEXTLOAD */
4566
    type0, ptype1, ptype1, type2, -1, 
4567
    /* G_INDEXED_ZEXTLOAD */
4568
    type0, ptype1, ptype1, type2, -1, 
4569
    /* G_STORE */
4570
    type0, ptype1, 
4571
    /* G_INDEXED_STORE */
4572
    ptype0, type1, ptype0, ptype2, -1, 
4573
    /* G_ATOMIC_CMPXCHG_WITH_SUCCESS */
4574
    type0, type1, type2, type0, type0, 
4575
    /* G_ATOMIC_CMPXCHG */
4576
    type0, ptype1, type0, type0, 
4577
    /* G_ATOMICRMW_XCHG */
4578
    type0, ptype1, type0, 
4579
    /* G_ATOMICRMW_ADD */
4580
    type0, ptype1, type0, 
4581
    /* G_ATOMICRMW_SUB */
4582
    type0, ptype1, type0, 
4583
    /* G_ATOMICRMW_AND */
4584
    type0, ptype1, type0, 
4585
    /* G_ATOMICRMW_NAND */
4586
    type0, ptype1, type0, 
4587
    /* G_ATOMICRMW_OR */
4588
    type0, ptype1, type0, 
4589
    /* G_ATOMICRMW_XOR */
4590
    type0, ptype1, type0, 
4591
    /* G_ATOMICRMW_MAX */
4592
    type0, ptype1, type0, 
4593
    /* G_ATOMICRMW_MIN */
4594
    type0, ptype1, type0, 
4595
    /* G_ATOMICRMW_UMAX */
4596
    type0, ptype1, type0, 
4597
    /* G_ATOMICRMW_UMIN */
4598
    type0, ptype1, type0, 
4599
    /* G_ATOMICRMW_FADD */
4600
    type0, ptype1, type0, 
4601
    /* G_ATOMICRMW_FSUB */
4602
    type0, ptype1, type0, 
4603
    /* G_ATOMICRMW_FMAX */
4604
    type0, ptype1, type0, 
4605
    /* G_ATOMICRMW_FMIN */
4606
    type0, ptype1, type0, 
4607
    /* G_ATOMICRMW_UINC_WRAP */
4608
    type0, ptype1, type0, 
4609
    /* G_ATOMICRMW_UDEC_WRAP */
4610
    type0, ptype1, type0, 
4611
    /* G_FENCE */
4612
    i32imm, i32imm, 
4613
    /* G_PREFETCH */
4614
    ptype0, i32imm, i32imm, i32imm, 
4615
    /* G_BRCOND */
4616
    type0, -1, 
4617
    /* G_BRINDIRECT */
4618
    type0, 
4619
    /* G_INVOKE_REGION_START */
4620
    /* G_INTRINSIC */
4621
    -1, 
4622
    /* G_INTRINSIC_W_SIDE_EFFECTS */
4623
    -1, 
4624
    /* G_INTRINSIC_CONVERGENT */
4625
    -1, 
4626
    /* G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS */
4627
    -1, 
4628
    /* G_ANYEXT */
4629
    type0, type1, 
4630
    /* G_TRUNC */
4631
    type0, type1, 
4632
    /* G_CONSTANT */
4633
    type0, -1, 
4634
    /* G_FCONSTANT */
4635
    type0, -1, 
4636
    /* G_VASTART */
4637
    type0, 
4638
    /* G_VAARG */
4639
    type0, type1, -1, 
4640
    /* G_SEXT */
4641
    type0, type1, 
4642
    /* G_SEXT_INREG */
4643
    type0, type0, untyped_imm_0, 
4644
    /* G_ZEXT */
4645
    type0, type1, 
4646
    /* G_SHL */
4647
    type0, type0, type1, 
4648
    /* G_LSHR */
4649
    type0, type0, type1, 
4650
    /* G_ASHR */
4651
    type0, type0, type1, 
4652
    /* G_FSHL */
4653
    type0, type0, type0, type1, 
4654
    /* G_FSHR */
4655
    type0, type0, type0, type1, 
4656
    /* G_ROTR */
4657
    type0, type0, type1, 
4658
    /* G_ROTL */
4659
    type0, type0, type1, 
4660
    /* G_ICMP */
4661
    type0, -1, type1, type1, 
4662
    /* G_FCMP */
4663
    type0, -1, type1, type1, 
4664
    /* G_SELECT */
4665
    type0, type1, type0, type0, 
4666
    /* G_UADDO */
4667
    type0, type1, type0, type0, 
4668
    /* G_UADDE */
4669
    type0, type1, type0, type0, type1, 
4670
    /* G_USUBO */
4671
    type0, type1, type0, type0, 
4672
    /* G_USUBE */
4673
    type0, type1, type0, type0, type1, 
4674
    /* G_SADDO */
4675
    type0, type1, type0, type0, 
4676
    /* G_SADDE */
4677
    type0, type1, type0, type0, type1, 
4678
    /* G_SSUBO */
4679
    type0, type1, type0, type0, 
4680
    /* G_SSUBE */
4681
    type0, type1, type0, type0, type1, 
4682
    /* G_UMULO */
4683
    type0, type1, type0, type0, 
4684
    /* G_SMULO */
4685
    type0, type1, type0, type0, 
4686
    /* G_UMULH */
4687
    type0, type0, type0, 
4688
    /* G_SMULH */
4689
    type0, type0, type0, 
4690
    /* G_UADDSAT */
4691
    type0, type0, type0, 
4692
    /* G_SADDSAT */
4693
    type0, type0, type0, 
4694
    /* G_USUBSAT */
4695
    type0, type0, type0, 
4696
    /* G_SSUBSAT */
4697
    type0, type0, type0, 
4698
    /* G_USHLSAT */
4699
    type0, type0, type1, 
4700
    /* G_SSHLSAT */
4701
    type0, type0, type1, 
4702
    /* G_SMULFIX */
4703
    type0, type0, type0, untyped_imm_0, 
4704
    /* G_UMULFIX */
4705
    type0, type0, type0, untyped_imm_0, 
4706
    /* G_SMULFIXSAT */
4707
    type0, type0, type0, untyped_imm_0, 
4708
    /* G_UMULFIXSAT */
4709
    type0, type0, type0, untyped_imm_0, 
4710
    /* G_SDIVFIX */
4711
    type0, type0, type0, untyped_imm_0, 
4712
    /* G_UDIVFIX */
4713
    type0, type0, type0, untyped_imm_0, 
4714
    /* G_SDIVFIXSAT */
4715
    type0, type0, type0, untyped_imm_0, 
4716
    /* G_UDIVFIXSAT */
4717
    type0, type0, type0, untyped_imm_0, 
4718
    /* G_FADD */
4719
    type0, type0, type0, 
4720
    /* G_FSUB */
4721
    type0, type0, type0, 
4722
    /* G_FMUL */
4723
    type0, type0, type0, 
4724
    /* G_FMA */
4725
    type0, type0, type0, type0, 
4726
    /* G_FMAD */
4727
    type0, type0, type0, type0, 
4728
    /* G_FDIV */
4729
    type0, type0, type0, 
4730
    /* G_FREM */
4731
    type0, type0, type0, 
4732
    /* G_FPOW */
4733
    type0, type0, type0, 
4734
    /* G_FPOWI */
4735
    type0, type0, type1, 
4736
    /* G_FEXP */
4737
    type0, type0, 
4738
    /* G_FEXP2 */
4739
    type0, type0, 
4740
    /* G_FEXP10 */
4741
    type0, type0, 
4742
    /* G_FLOG */
4743
    type0, type0, 
4744
    /* G_FLOG2 */
4745
    type0, type0, 
4746
    /* G_FLOG10 */
4747
    type0, type0, 
4748
    /* G_FLDEXP */
4749
    type0, type0, type1, 
4750
    /* G_FFREXP */
4751
    type0, type1, type0, 
4752
    /* G_FNEG */
4753
    type0, type0, 
4754
    /* G_FPEXT */
4755
    type0, type1, 
4756
    /* G_FPTRUNC */
4757
    type0, type1, 
4758
    /* G_FPTOSI */
4759
    type0, type1, 
4760
    /* G_FPTOUI */
4761
    type0, type1, 
4762
    /* G_SITOFP */
4763
    type0, type1, 
4764
    /* G_UITOFP */
4765
    type0, type1, 
4766
    /* G_FABS */
4767
    type0, type0, 
4768
    /* G_FCOPYSIGN */
4769
    type0, type0, type1, 
4770
    /* G_IS_FPCLASS */
4771
    type0, type1, -1, 
4772
    /* G_FCANONICALIZE */
4773
    type0, type0, 
4774
    /* G_FMINNUM */
4775
    type0, type0, type0, 
4776
    /* G_FMAXNUM */
4777
    type0, type0, type0, 
4778
    /* G_FMINNUM_IEEE */
4779
    type0, type0, type0, 
4780
    /* G_FMAXNUM_IEEE */
4781
    type0, type0, type0, 
4782
    /* G_FMINIMUM */
4783
    type0, type0, type0, 
4784
    /* G_FMAXIMUM */
4785
    type0, type0, type0, 
4786
    /* G_GET_FPENV */
4787
    type0, 
4788
    /* G_SET_FPENV */
4789
    type0, 
4790
    /* G_RESET_FPENV */
4791
    /* G_GET_FPMODE */
4792
    type0, 
4793
    /* G_SET_FPMODE */
4794
    type0, 
4795
    /* G_RESET_FPMODE */
4796
    /* G_PTR_ADD */
4797
    ptype0, ptype0, type1, 
4798
    /* G_PTRMASK */
4799
    ptype0, ptype0, type1, 
4800
    /* G_SMIN */
4801
    type0, type0, type0, 
4802
    /* G_SMAX */
4803
    type0, type0, type0, 
4804
    /* G_UMIN */
4805
    type0, type0, type0, 
4806
    /* G_UMAX */
4807
    type0, type0, type0, 
4808
    /* G_ABS */
4809
    type0, type0, 
4810
    /* G_LROUND */
4811
    type0, type1, 
4812
    /* G_LLROUND */
4813
    type0, type1, 
4814
    /* G_BR */
4815
    -1, 
4816
    /* G_BRJT */
4817
    ptype0, -1, type1, 
4818
    /* G_INSERT_VECTOR_ELT */
4819
    type0, type0, type1, type2, 
4820
    /* G_EXTRACT_VECTOR_ELT */
4821
    type0, type1, type2, 
4822
    /* G_SHUFFLE_VECTOR */
4823
    type0, type1, type1, -1, 
4824
    /* G_CTTZ */
4825
    type0, type1, 
4826
    /* G_CTTZ_ZERO_UNDEF */
4827
    type0, type1, 
4828
    /* G_CTLZ */
4829
    type0, type1, 
4830
    /* G_CTLZ_ZERO_UNDEF */
4831
    type0, type1, 
4832
    /* G_CTPOP */
4833
    type0, type1, 
4834
    /* G_BSWAP */
4835
    type0, type0, 
4836
    /* G_BITREVERSE */
4837
    type0, type0, 
4838
    /* G_FCEIL */
4839
    type0, type0, 
4840
    /* G_FCOS */
4841
    type0, type0, 
4842
    /* G_FSIN */
4843
    type0, type0, 
4844
    /* G_FSQRT */
4845
    type0, type0, 
4846
    /* G_FFLOOR */
4847
    type0, type0, 
4848
    /* G_FRINT */
4849
    type0, type0, 
4850
    /* G_FNEARBYINT */
4851
    type0, type0, 
4852
    /* G_ADDRSPACE_CAST */
4853
    type0, type1, 
4854
    /* G_BLOCK_ADDR */
4855
    type0, -1, 
4856
    /* G_JUMP_TABLE */
4857
    type0, -1, 
4858
    /* G_DYN_STACKALLOC */
4859
    ptype0, type1, i32imm, 
4860
    /* G_STACKSAVE */
4861
    ptype0, 
4862
    /* G_STACKRESTORE */
4863
    ptype0, 
4864
    /* G_STRICT_FADD */
4865
    type0, type0, type0, 
4866
    /* G_STRICT_FSUB */
4867
    type0, type0, type0, 
4868
    /* G_STRICT_FMUL */
4869
    type0, type0, type0, 
4870
    /* G_STRICT_FDIV */
4871
    type0, type0, type0, 
4872
    /* G_STRICT_FREM */
4873
    type0, type0, type0, 
4874
    /* G_STRICT_FMA */
4875
    type0, type0, type0, type0, 
4876
    /* G_STRICT_FSQRT */
4877
    type0, type0, 
4878
    /* G_STRICT_FLDEXP */
4879
    type0, type0, type1, 
4880
    /* G_READ_REGISTER */
4881
    type0, -1, 
4882
    /* G_WRITE_REGISTER */
4883
    -1, type0, 
4884
    /* G_MEMCPY */
4885
    ptype0, ptype1, type2, untyped_imm_0, 
4886
    /* G_MEMCPY_INLINE */
4887
    ptype0, ptype1, type2, 
4888
    /* G_MEMMOVE */
4889
    ptype0, ptype1, type2, untyped_imm_0, 
4890
    /* G_MEMSET */
4891
    ptype0, type1, type2, untyped_imm_0, 
4892
    /* G_BZERO */
4893
    ptype0, type1, untyped_imm_0, 
4894
    /* G_VECREDUCE_SEQ_FADD */
4895
    type0, type1, type2, 
4896
    /* G_VECREDUCE_SEQ_FMUL */
4897
    type0, type1, type2, 
4898
    /* G_VECREDUCE_FADD */
4899
    type0, type1, 
4900
    /* G_VECREDUCE_FMUL */
4901
    type0, type1, 
4902
    /* G_VECREDUCE_FMAX */
4903
    type0, type1, 
4904
    /* G_VECREDUCE_FMIN */
4905
    type0, type1, 
4906
    /* G_VECREDUCE_FMAXIMUM */
4907
    type0, type1, 
4908
    /* G_VECREDUCE_FMINIMUM */
4909
    type0, type1, 
4910
    /* G_VECREDUCE_ADD */
4911
    type0, type1, 
4912
    /* G_VECREDUCE_MUL */
4913
    type0, type1, 
4914
    /* G_VECREDUCE_AND */
4915
    type0, type1, 
4916
    /* G_VECREDUCE_OR */
4917
    type0, type1, 
4918
    /* G_VECREDUCE_XOR */
4919
    type0, type1, 
4920
    /* G_VECREDUCE_SMAX */
4921
    type0, type1, 
4922
    /* G_VECREDUCE_SMIN */
4923
    type0, type1, 
4924
    /* G_VECREDUCE_UMAX */
4925
    type0, type1, 
4926
    /* G_VECREDUCE_UMIN */
4927
    type0, type1, 
4928
    /* G_SBFX */
4929
    type0, type0, type1, type1, 
4930
    /* G_UBFX */
4931
    type0, type0, type1, type1, 
4932
    /* ADJCALLSTACKDOWN */
4933
    i32imm, i32imm, 
4934
    /* ADJCALLSTACKUP */
4935
    i32imm, i32imm, 
4936
    /* GETPCX */
4937
    getPCX, 
4938
    /* SELECT_CC_DFP_FCC */
4939
    DFPRegs, DFPRegs, DFPRegs, i32imm, 
4940
    /* SELECT_CC_DFP_ICC */
4941
    DFPRegs, DFPRegs, DFPRegs, i32imm, 
4942
    /* SELECT_CC_DFP_XCC */
4943
    DFPRegs, DFPRegs, DFPRegs, i32imm, 
4944
    /* SELECT_CC_FP_FCC */
4945
    FPRegs, FPRegs, FPRegs, i32imm, 
4946
    /* SELECT_CC_FP_ICC */
4947
    FPRegs, FPRegs, FPRegs, i32imm, 
4948
    /* SELECT_CC_FP_XCC */
4949
    FPRegs, FPRegs, FPRegs, i32imm, 
4950
    /* SELECT_CC_Int_FCC */
4951
    IntRegs, IntRegs, IntRegs, i32imm, 
4952
    /* SELECT_CC_Int_ICC */
4953
    IntRegs, IntRegs, IntRegs, i32imm, 
4954
    /* SELECT_CC_Int_XCC */
4955
    IntRegs, IntRegs, IntRegs, i32imm, 
4956
    /* SELECT_CC_QFP_FCC */
4957
    QFPRegs, QFPRegs, QFPRegs, i32imm, 
4958
    /* SELECT_CC_QFP_ICC */
4959
    QFPRegs, QFPRegs, QFPRegs, i32imm, 
4960
    /* SELECT_CC_QFP_XCC */
4961
    QFPRegs, QFPRegs, QFPRegs, i32imm, 
4962
    /* SET */
4963
    IntRegs, i32imm, 
4964
    /* SETX */
4965
    I64Regs, i64imm, I64Regs, 
4966
    /* ADDCCri */
4967
    IntRegs, IntRegs, simm13Op, 
4968
    /* ADDCCrr */
4969
    IntRegs, IntRegs, IntRegs, 
4970
    /* ADDCri */
4971
    IntRegs, IntRegs, simm13Op, 
4972
    /* ADDCrr */
4973
    IntRegs, IntRegs, IntRegs, 
4974
    /* ADDEri */
4975
    IntRegs, IntRegs, simm13Op, 
4976
    /* ADDErr */
4977
    IntRegs, IntRegs, IntRegs, 
4978
    /* ADDXC */
4979
    I64Regs, I64Regs, I64Regs, 
4980
    /* ADDXCCC */
4981
    I64Regs, I64Regs, I64Regs, 
4982
    /* ADDri */
4983
    IntRegs, IntRegs, simm13Op, 
4984
    /* ADDrr */
4985
    IntRegs, IntRegs, IntRegs, 
4986
    /* ALIGNADDR */
4987
    I64Regs, I64Regs, I64Regs, 
4988
    /* ALIGNADDRL */
4989
    I64Regs, I64Regs, I64Regs, 
4990
    /* ANDCCri */
4991
    IntRegs, IntRegs, simm13Op, 
4992
    /* ANDCCrr */
4993
    IntRegs, IntRegs, IntRegs, 
4994
    /* ANDNCCri */
4995
    IntRegs, IntRegs, simm13Op, 
4996
    /* ANDNCCrr */
4997
    IntRegs, IntRegs, IntRegs, 
4998
    /* ANDNri */
4999
    IntRegs, IntRegs, simm13Op, 
5000
    /* ANDNrr */
5001
    IntRegs, IntRegs, IntRegs, 
5002
    /* ANDri */
5003
    IntRegs, IntRegs, simm13Op, 
5004
    /* ANDrr */
5005
    IntRegs, IntRegs, IntRegs, 
5006
    /* ARRAY16 */
5007
    I64Regs, I64Regs, I64Regs, 
5008
    /* ARRAY32 */
5009
    I64Regs, I64Regs, I64Regs, 
5010
    /* ARRAY8 */
5011
    I64Regs, I64Regs, I64Regs, 
5012
    /* BA */
5013
    brtarget, 
5014
    /* BCOND */
5015
    brtarget, CCOp, 
5016
    /* BCONDA */
5017
    brtarget, CCOp, 
5018
    /* BINDri */
5019
    -1, i32imm, 
5020
    /* BINDrr */
5021
    -1, -1, 
5022
    /* BMASK */
5023
    I64Regs, I64Regs, I64Regs, 
5024
    /* BPFCC */
5025
    bprtarget, CCOp, FCCRegs, 
5026
    /* BPFCCA */
5027
    bprtarget, CCOp, FCCRegs, 
5028
    /* BPFCCANT */
5029
    bprtarget, CCOp, FCCRegs, 
5030
    /* BPFCCNT */
5031
    bprtarget, CCOp, FCCRegs, 
5032
    /* BPICC */
5033
    bprtarget, CCOp, 
5034
    /* BPICCA */
5035
    bprtarget, CCOp, 
5036
    /* BPICCANT */
5037
    bprtarget, CCOp, 
5038
    /* BPICCNT */
5039
    bprtarget, CCOp, 
5040
    /* BPR */
5041
    bprtarget16, RegCCOp, I64Regs, 
5042
    /* BPRA */
5043
    bprtarget16, RegCCOp, I64Regs, 
5044
    /* BPRANT */
5045
    bprtarget16, RegCCOp, I64Regs, 
5046
    /* BPRNT */
5047
    bprtarget16, RegCCOp, I64Regs, 
5048
    /* BPXCC */
5049
    bprtarget, CCOp, 
5050
    /* BPXCCA */
5051
    bprtarget, CCOp, 
5052
    /* BPXCCANT */
5053
    bprtarget, CCOp, 
5054
    /* BPXCCNT */
5055
    bprtarget, CCOp, 
5056
    /* BSHUFFLE */
5057
    DFPRegs, DFPRegs, DFPRegs, 
5058
    /* CALL */
5059
    calltarget, 
5060
    /* CALLri */
5061
    -1, i32imm, 
5062
    /* CALLrr */
5063
    -1, -1, 
5064
    /* CASAri */
5065
    IntRegs, IntRegs, IntRegs, IntRegs, 
5066
    /* CASArr */
5067
    IntRegs, IntRegs, IntRegs, IntRegs, ASITag, 
5068
    /* CASXAri */
5069
    I64Regs, I64Regs, I64Regs, I64Regs, 
5070
    /* CASXArr */
5071
    I64Regs, I64Regs, I64Regs, I64Regs, ASITag, 
5072
    /* CBCOND */
5073
    brtarget, CCOp, 
5074
    /* CBCONDA */
5075
    brtarget, CCOp, 
5076
    /* CMASK16 */
5077
    I64Regs, 
5078
    /* CMASK32 */
5079
    I64Regs, 
5080
    /* CMASK8 */
5081
    I64Regs, 
5082
    /* DONE */
5083
    /* EDGE16 */
5084
    I64Regs, I64Regs, I64Regs, 
5085
    /* EDGE16L */
5086
    I64Regs, I64Regs, I64Regs, 
5087
    /* EDGE16LN */
5088
    I64Regs, I64Regs, I64Regs, 
5089
    /* EDGE16N */
5090
    I64Regs, I64Regs, I64Regs, 
5091
    /* EDGE32 */
5092
    I64Regs, I64Regs, I64Regs, 
5093
    /* EDGE32L */
5094
    I64Regs, I64Regs, I64Regs, 
5095
    /* EDGE32LN */
5096
    I64Regs, I64Regs, I64Regs, 
5097
    /* EDGE32N */
5098
    I64Regs, I64Regs, I64Regs, 
5099
    /* EDGE8 */
5100
    I64Regs, I64Regs, I64Regs, 
5101
    /* EDGE8L */
5102
    I64Regs, I64Regs, I64Regs, 
5103
    /* EDGE8LN */
5104
    I64Regs, I64Regs, I64Regs, 
5105
    /* EDGE8N */
5106
    I64Regs, I64Regs, I64Regs, 
5107
    /* FABSD */
5108
    DFPRegs, DFPRegs, 
5109
    /* FABSQ */
5110
    QFPRegs, QFPRegs, 
5111
    /* FABSS */
5112
    FPRegs, FPRegs, 
5113
    /* FADDD */
5114
    DFPRegs, DFPRegs, DFPRegs, 
5115
    /* FADDQ */
5116
    QFPRegs, QFPRegs, QFPRegs, 
5117
    /* FADDS */
5118
    FPRegs, FPRegs, FPRegs, 
5119
    /* FALIGNADATA */
5120
    DFPRegs, DFPRegs, DFPRegs, 
5121
    /* FAND */
5122
    DFPRegs, DFPRegs, DFPRegs, 
5123
    /* FANDNOT1 */
5124
    DFPRegs, DFPRegs, DFPRegs, 
5125
    /* FANDNOT1S */
5126
    FPRegs, FPRegs, FPRegs, 
5127
    /* FANDNOT2 */
5128
    DFPRegs, DFPRegs, DFPRegs, 
5129
    /* FANDNOT2S */
5130
    FPRegs, FPRegs, FPRegs, 
5131
    /* FANDS */
5132
    FPRegs, FPRegs, FPRegs, 
5133
    /* FBCOND */
5134
    brtarget, CCOp, 
5135
    /* FBCONDA */
5136
    brtarget, CCOp, 
5137
    /* FBCONDA_V9 */
5138
    bprtarget, CCOp, 
5139
    /* FBCOND_V9 */
5140
    bprtarget, CCOp, 
5141
    /* FCHKSM16 */
5142
    DFPRegs, DFPRegs, DFPRegs, 
5143
    /* FCMPD */
5144
    DFPRegs, DFPRegs, 
5145
    /* FCMPD_V9 */
5146
    DFPRegs, DFPRegs, 
5147
    /* FCMPEQ16 */
5148
    I64Regs, DFPRegs, DFPRegs, 
5149
    /* FCMPEQ32 */
5150
    I64Regs, DFPRegs, DFPRegs, 
5151
    /* FCMPGT16 */
5152
    I64Regs, DFPRegs, DFPRegs, 
5153
    /* FCMPGT32 */
5154
    I64Regs, DFPRegs, DFPRegs, 
5155
    /* FCMPLE16 */
5156
    I64Regs, DFPRegs, DFPRegs, 
5157
    /* FCMPLE32 */
5158
    I64Regs, DFPRegs, DFPRegs, 
5159
    /* FCMPNE16 */
5160
    I64Regs, DFPRegs, DFPRegs, 
5161
    /* FCMPNE32 */
5162
    I64Regs, DFPRegs, DFPRegs, 
5163
    /* FCMPQ */
5164
    QFPRegs, QFPRegs, 
5165
    /* FCMPQ_V9 */
5166
    QFPRegs, QFPRegs, 
5167
    /* FCMPS */
5168
    FPRegs, FPRegs, 
5169
    /* FCMPS_V9 */
5170
    FPRegs, FPRegs, 
5171
    /* FDIVD */
5172
    DFPRegs, DFPRegs, DFPRegs, 
5173
    /* FDIVQ */
5174
    QFPRegs, QFPRegs, QFPRegs, 
5175
    /* FDIVS */
5176
    FPRegs, FPRegs, FPRegs, 
5177
    /* FDMULQ */
5178
    QFPRegs, DFPRegs, DFPRegs, 
5179
    /* FDTOI */
5180
    FPRegs, DFPRegs, 
5181
    /* FDTOQ */
5182
    QFPRegs, DFPRegs, 
5183
    /* FDTOS */
5184
    FPRegs, DFPRegs, 
5185
    /* FDTOX */
5186
    DFPRegs, DFPRegs, 
5187
    /* FEXPAND */
5188
    DFPRegs, DFPRegs, 
5189
    /* FHADDD */
5190
    DFPRegs, DFPRegs, DFPRegs, 
5191
    /* FHADDS */
5192
    DFPRegs, DFPRegs, DFPRegs, 
5193
    /* FHSUBD */
5194
    DFPRegs, DFPRegs, DFPRegs, 
5195
    /* FHSUBS */
5196
    DFPRegs, DFPRegs, DFPRegs, 
5197
    /* FITOD */
5198
    DFPRegs, FPRegs, 
5199
    /* FITOQ */
5200
    QFPRegs, FPRegs, 
5201
    /* FITOS */
5202
    FPRegs, FPRegs, 
5203
    /* FLCMPD */
5204
    FCCRegs, DFPRegs, DFPRegs, 
5205
    /* FLCMPS */
5206
    FCCRegs, DFPRegs, DFPRegs, 
5207
    /* FLUSH */
5208
    /* FLUSHW */
5209
    /* FLUSHri */
5210
    -1, i32imm, 
5211
    /* FLUSHrr */
5212
    -1, -1, 
5213
    /* FMEAN16 */
5214
    DFPRegs, DFPRegs, DFPRegs, 
5215
    /* FMOVD */
5216
    DFPRegs, DFPRegs, 
5217
    /* FMOVD_FCC */
5218
    DFPRegs, DFPRegs, DFPRegs, CCOp, 
5219
    /* FMOVD_ICC */
5220
    DFPRegs, DFPRegs, DFPRegs, CCOp, 
5221
    /* FMOVD_XCC */
5222
    DFPRegs, DFPRegs, DFPRegs, CCOp, 
5223
    /* FMOVQ */
5224
    QFPRegs, QFPRegs, 
5225
    /* FMOVQ_FCC */
5226
    QFPRegs, QFPRegs, QFPRegs, CCOp, 
5227
    /* FMOVQ_ICC */
5228
    QFPRegs, QFPRegs, QFPRegs, CCOp, 
5229
    /* FMOVQ_XCC */
5230
    QFPRegs, QFPRegs, QFPRegs, CCOp, 
5231
    /* FMOVRD */
5232
    DFPRegs, I64Regs, DFPRegs, DFPRegs, RegCCOp, 
5233
    /* FMOVRQ */
5234
    QFPRegs, I64Regs, QFPRegs, QFPRegs, RegCCOp, 
5235
    /* FMOVRS */
5236
    FPRegs, I64Regs, FPRegs, FPRegs, RegCCOp, 
5237
    /* FMOVS */
5238
    FPRegs, FPRegs, 
5239
    /* FMOVS_FCC */
5240
    FPRegs, FPRegs, FPRegs, CCOp, 
5241
    /* FMOVS_ICC */
5242
    FPRegs, FPRegs, FPRegs, CCOp, 
5243
    /* FMOVS_XCC */
5244
    FPRegs, FPRegs, FPRegs, CCOp, 
5245
    /* FMUL8SUX16 */
5246
    DFPRegs, DFPRegs, DFPRegs, 
5247
    /* FMUL8ULX16 */
5248
    DFPRegs, DFPRegs, DFPRegs, 
5249
    /* FMUL8X16 */
5250
    DFPRegs, DFPRegs, DFPRegs, 
5251
    /* FMUL8X16AL */
5252
    DFPRegs, DFPRegs, DFPRegs, 
5253
    /* FMUL8X16AU */
5254
    DFPRegs, DFPRegs, DFPRegs, 
5255
    /* FMULD */
5256
    DFPRegs, DFPRegs, DFPRegs, 
5257
    /* FMULD8SUX16 */
5258
    DFPRegs, DFPRegs, DFPRegs, 
5259
    /* FMULD8ULX16 */
5260
    DFPRegs, DFPRegs, DFPRegs, 
5261
    /* FMULQ */
5262
    QFPRegs, QFPRegs, QFPRegs, 
5263
    /* FMULS */
5264
    FPRegs, FPRegs, FPRegs, 
5265
    /* FNADDD */
5266
    DFPRegs, DFPRegs, DFPRegs, 
5267
    /* FNADDS */
5268
    DFPRegs, DFPRegs, DFPRegs, 
5269
    /* FNAND */
5270
    DFPRegs, DFPRegs, DFPRegs, 
5271
    /* FNANDS */
5272
    FPRegs, FPRegs, FPRegs, 
5273
    /* FNEGD */
5274
    DFPRegs, DFPRegs, 
5275
    /* FNEGQ */
5276
    QFPRegs, QFPRegs, 
5277
    /* FNEGS */
5278
    FPRegs, FPRegs, 
5279
    /* FNHADDD */
5280
    DFPRegs, DFPRegs, DFPRegs, 
5281
    /* FNHADDS */
5282
    DFPRegs, DFPRegs, DFPRegs, 
5283
    /* FNMULD */
5284
    DFPRegs, DFPRegs, DFPRegs, 
5285
    /* FNMULS */
5286
    DFPRegs, DFPRegs, DFPRegs, 
5287
    /* FNOR */
5288
    DFPRegs, DFPRegs, DFPRegs, 
5289
    /* FNORS */
5290
    FPRegs, FPRegs, FPRegs, 
5291
    /* FNOT1 */
5292
    DFPRegs, DFPRegs, 
5293
    /* FNOT1S */
5294
    FPRegs, FPRegs, 
5295
    /* FNOT2 */
5296
    DFPRegs, DFPRegs, 
5297
    /* FNOT2S */
5298
    FPRegs, FPRegs, 
5299
    /* FNSMULD */
5300
    DFPRegs, DFPRegs, DFPRegs, 
5301
    /* FONE */
5302
    DFPRegs, DFPRegs, 
5303
    /* FONES */
5304
    FPRegs, FPRegs, 
5305
    /* FOR */
5306
    DFPRegs, DFPRegs, DFPRegs, 
5307
    /* FORNOT1 */
5308
    DFPRegs, DFPRegs, DFPRegs, 
5309
    /* FORNOT1S */
5310
    FPRegs, FPRegs, FPRegs, 
5311
    /* FORNOT2 */
5312
    DFPRegs, DFPRegs, DFPRegs, 
5313
    /* FORNOT2S */
5314
    FPRegs, FPRegs, FPRegs, 
5315
    /* FORS */
5316
    FPRegs, FPRegs, FPRegs, 
5317
    /* FPACK16 */
5318
    DFPRegs, DFPRegs, 
5319
    /* FPACK32 */
5320
    DFPRegs, DFPRegs, DFPRegs, 
5321
    /* FPACKFIX */
5322
    DFPRegs, DFPRegs, 
5323
    /* FPADD16 */
5324
    DFPRegs, DFPRegs, DFPRegs, 
5325
    /* FPADD16S */
5326
    DFPRegs, DFPRegs, DFPRegs, 
5327
    /* FPADD32 */
5328
    DFPRegs, DFPRegs, DFPRegs, 
5329
    /* FPADD32S */
5330
    DFPRegs, DFPRegs, DFPRegs, 
5331
    /* FPADD64 */
5332
    DFPRegs, DFPRegs, DFPRegs, 
5333
    /* FPMERGE */
5334
    DFPRegs, DFPRegs, DFPRegs, 
5335
    /* FPSUB16 */
5336
    DFPRegs, DFPRegs, DFPRegs, 
5337
    /* FPSUB16S */
5338
    DFPRegs, DFPRegs, DFPRegs, 
5339
    /* FPSUB32 */
5340
    DFPRegs, DFPRegs, DFPRegs, 
5341
    /* FPSUB32S */
5342
    DFPRegs, DFPRegs, DFPRegs, 
5343
    /* FQTOD */
5344
    DFPRegs, QFPRegs, 
5345
    /* FQTOI */
5346
    FPRegs, QFPRegs, 
5347
    /* FQTOS */
5348
    FPRegs, QFPRegs, 
5349
    /* FQTOX */
5350
    DFPRegs, QFPRegs, 
5351
    /* FSLAS16 */
5352
    DFPRegs, DFPRegs, DFPRegs, 
5353
    /* FSLAS32 */
5354
    DFPRegs, DFPRegs, DFPRegs, 
5355
    /* FSLL16 */
5356
    DFPRegs, DFPRegs, DFPRegs, 
5357
    /* FSLL32 */
5358
    DFPRegs, DFPRegs, DFPRegs, 
5359
    /* FSMULD */
5360
    DFPRegs, FPRegs, FPRegs, 
5361
    /* FSQRTD */
5362
    DFPRegs, DFPRegs, 
5363
    /* FSQRTQ */
5364
    QFPRegs, QFPRegs, 
5365
    /* FSQRTS */
5366
    FPRegs, FPRegs, 
5367
    /* FSRA16 */
5368
    DFPRegs, DFPRegs, DFPRegs, 
5369
    /* FSRA32 */
5370
    DFPRegs, DFPRegs, DFPRegs, 
5371
    /* FSRC1 */
5372
    DFPRegs, DFPRegs, 
5373
    /* FSRC1S */
5374
    FPRegs, FPRegs, 
5375
    /* FSRC2 */
5376
    DFPRegs, DFPRegs, 
5377
    /* FSRC2S */
5378
    FPRegs, FPRegs, 
5379
    /* FSRL16 */
5380
    DFPRegs, DFPRegs, DFPRegs, 
5381
    /* FSRL32 */
5382
    DFPRegs, DFPRegs, DFPRegs, 
5383
    /* FSTOD */
5384
    DFPRegs, FPRegs, 
5385
    /* FSTOI */
5386
    FPRegs, FPRegs, 
5387
    /* FSTOQ */
5388
    QFPRegs, FPRegs, 
5389
    /* FSTOX */
5390
    DFPRegs, FPRegs, 
5391
    /* FSUBD */
5392
    DFPRegs, DFPRegs, DFPRegs, 
5393
    /* FSUBQ */
5394
    QFPRegs, QFPRegs, QFPRegs, 
5395
    /* FSUBS */
5396
    FPRegs, FPRegs, FPRegs, 
5397
    /* FXNOR */
5398
    DFPRegs, DFPRegs, DFPRegs, 
5399
    /* FXNORS */
5400
    FPRegs, FPRegs, FPRegs, 
5401
    /* FXOR */
5402
    DFPRegs, DFPRegs, DFPRegs, 
5403
    /* FXORS */
5404
    FPRegs, FPRegs, FPRegs, 
5405
    /* FXTOD */
5406
    DFPRegs, DFPRegs, 
5407
    /* FXTOQ */
5408
    QFPRegs, DFPRegs, 
5409
    /* FXTOS */
5410
    FPRegs, DFPRegs, 
5411
    /* FZERO */
5412
    DFPRegs, DFPRegs, 
5413
    /* FZEROS */
5414
    FPRegs, FPRegs, 
5415
    /* GDOP_LDXrr */
5416
    I64Regs, -1, -1, TailRelocSymGOTLoad, 
5417
    /* GDOP_LDrr */
5418
    IntRegs, -1, -1, TailRelocSymGOTLoad, 
5419
    /* JMPLri */
5420
    IntRegs, -1, i32imm, 
5421
    /* JMPLrr */
5422
    IntRegs, -1, -1, 
5423
    /* LDAri */
5424
    IntRegs, -1, i32imm, 
5425
    /* LDArr */
5426
    IntRegs, -1, -1, ASITag, 
5427
    /* LDCSRri */
5428
    -1, i32imm, 
5429
    /* LDCSRrr */
5430
    -1, -1, 
5431
    /* LDCri */
5432
    CoprocRegs, -1, i32imm, 
5433
    /* LDCrr */
5434
    CoprocRegs, -1, -1, 
5435
    /* LDDAri */
5436
    IntPair, -1, i32imm, 
5437
    /* LDDArr */
5438
    IntPair, -1, -1, ASITag, 
5439
    /* LDDCri */
5440
    CoprocPair, -1, i32imm, 
5441
    /* LDDCrr */
5442
    CoprocPair, -1, -1, 
5443
    /* LDDFAri */
5444
    DFPRegs, -1, i32imm, 
5445
    /* LDDFArr */
5446
    DFPRegs, -1, -1, ASITag, 
5447
    /* LDDFri */
5448
    DFPRegs, -1, i32imm, 
5449
    /* LDDFrr */
5450
    DFPRegs, -1, -1, 
5451
    /* LDDri */
5452
    IntPair, -1, i32imm, 
5453
    /* LDDrr */
5454
    IntPair, -1, -1, 
5455
    /* LDFAri */
5456
    FPRegs, -1, i32imm, 
5457
    /* LDFArr */
5458
    FPRegs, -1, -1, ASITag, 
5459
    /* LDFSRri */
5460
    -1, i32imm, 
5461
    /* LDFSRrr */
5462
    -1, -1, 
5463
    /* LDFri */
5464
    FPRegs, -1, i32imm, 
5465
    /* LDFrr */
5466
    FPRegs, -1, -1, 
5467
    /* LDQFAri */
5468
    QFPRegs, -1, i32imm, 
5469
    /* LDQFArr */
5470
    QFPRegs, -1, -1, ASITag, 
5471
    /* LDQFri */
5472
    QFPRegs, -1, i32imm, 
5473
    /* LDQFrr */
5474
    QFPRegs, -1, -1, 
5475
    /* LDSBAri */
5476
    IntRegs, -1, i32imm, 
5477
    /* LDSBArr */
5478
    IntRegs, -1, -1, ASITag, 
5479
    /* LDSBri */
5480
    IntRegs, -1, i32imm, 
5481
    /* LDSBrr */
5482
    IntRegs, -1, -1, 
5483
    /* LDSHAri */
5484
    IntRegs, -1, i32imm, 
5485
    /* LDSHArr */
5486
    IntRegs, -1, -1, ASITag, 
5487
    /* LDSHri */
5488
    IntRegs, -1, i32imm, 
5489
    /* LDSHrr */
5490
    IntRegs, -1, -1, 
5491
    /* LDSTUBAri */
5492
    IntRegs, -1, i32imm, 
5493
    /* LDSTUBArr */
5494
    IntRegs, -1, -1, ASITag, 
5495
    /* LDSTUBri */
5496
    IntRegs, -1, i32imm, 
5497
    /* LDSTUBrr */
5498
    IntRegs, -1, -1, 
5499
    /* LDSWAri */
5500
    I64Regs, -1, i32imm, 
5501
    /* LDSWArr */
5502
    I64Regs, -1, -1, ASITag, 
5503
    /* LDSWri */
5504
    I64Regs, -1, i32imm, 
5505
    /* LDSWrr */
5506
    I64Regs, -1, -1, 
5507
    /* LDUBAri */
5508
    IntRegs, -1, i32imm, 
5509
    /* LDUBArr */
5510
    IntRegs, -1, -1, ASITag, 
5511
    /* LDUBri */
5512
    IntRegs, -1, i32imm, 
5513
    /* LDUBrr */
5514
    IntRegs, -1, -1, 
5515
    /* LDUHAri */
5516
    IntRegs, -1, i32imm, 
5517
    /* LDUHArr */
5518
    IntRegs, -1, -1, ASITag, 
5519
    /* LDUHri */
5520
    IntRegs, -1, i32imm, 
5521
    /* LDUHrr */
5522
    IntRegs, -1, -1, 
5523
    /* LDXAri */
5524
    I64Regs, -1, i32imm, 
5525
    /* LDXArr */
5526
    I64Regs, -1, -1, ASITag, 
5527
    /* LDXFSRri */
5528
    -1, i32imm, 
5529
    /* LDXFSRrr */
5530
    -1, -1, 
5531
    /* LDXri */
5532
    I64Regs, -1, i32imm, 
5533
    /* LDXrr */
5534
    I64Regs, -1, -1, 
5535
    /* LDri */
5536
    IntRegs, -1, i32imm, 
5537
    /* LDrr */
5538
    IntRegs, -1, -1, 
5539
    /* LZCNT */
5540
    I64Regs, I64Regs, 
5541
    /* MEMBARi */
5542
    MembarTag, 
5543
    /* MOVDTOX */
5544
    I64Regs, DFPRegs, 
5545
    /* MOVFCCri */
5546
    IntRegs, i32imm, IntRegs, CCOp, 
5547
    /* MOVFCCrr */
5548
    IntRegs, IntRegs, IntRegs, CCOp, 
5549
    /* MOVICCri */
5550
    IntRegs, i32imm, IntRegs, CCOp, 
5551
    /* MOVICCrr */
5552
    IntRegs, IntRegs, IntRegs, CCOp, 
5553
    /* MOVRri */
5554
    IntRegs, I64Regs, i32imm, IntRegs, RegCCOp, 
5555
    /* MOVRrr */
5556
    IntRegs, I64Regs, IntRegs, IntRegs, RegCCOp, 
5557
    /* MOVSTOSW */
5558
    I64Regs, DFPRegs, 
5559
    /* MOVSTOUW */
5560
    I64Regs, DFPRegs, 
5561
    /* MOVWTOS */
5562
    DFPRegs, I64Regs, 
5563
    /* MOVXCCri */
5564
    IntRegs, i32imm, IntRegs, CCOp, 
5565
    /* MOVXCCrr */
5566
    IntRegs, IntRegs, IntRegs, CCOp, 
5567
    /* MOVXTOD */
5568
    DFPRegs, I64Regs, 
5569
    /* MULSCCri */
5570
    IntRegs, IntRegs, simm13Op, 
5571
    /* MULSCCrr */
5572
    IntRegs, IntRegs, IntRegs, 
5573
    /* MULXri */
5574
    IntRegs, IntRegs, i64imm, 
5575
    /* MULXrr */
5576
    I64Regs, I64Regs, I64Regs, 
5577
    /* NOP */
5578
    /* ORCCri */
5579
    IntRegs, IntRegs, simm13Op, 
5580
    /* ORCCrr */
5581
    IntRegs, IntRegs, IntRegs, 
5582
    /* ORNCCri */
5583
    IntRegs, IntRegs, simm13Op, 
5584
    /* ORNCCrr */
5585
    IntRegs, IntRegs, IntRegs, 
5586
    /* ORNri */
5587
    IntRegs, IntRegs, simm13Op, 
5588
    /* ORNrr */
5589
    IntRegs, IntRegs, IntRegs, 
5590
    /* ORri */
5591
    IntRegs, IntRegs, simm13Op, 
5592
    /* ORrr */
5593
    IntRegs, IntRegs, IntRegs, 
5594
    /* PDIST */
5595
    DFPRegs, DFPRegs, DFPRegs, 
5596
    /* PDISTN */
5597
    DFPRegs, DFPRegs, DFPRegs, 
5598
    /* POPCrr */
5599
    IntRegs, IntRegs, 
5600
    /* PREFETCHi */
5601
    -1, i32imm, shift_imm5, 
5602
    /* PREFETCHr */
5603
    -1, -1, shift_imm5, 
5604
    /* PWRPSRri */
5605
    IntRegs, simm13Op, 
5606
    /* PWRPSRrr */
5607
    IntRegs, IntRegs, 
5608
    /* RDASR */
5609
    IntRegs, ASRRegs, 
5610
    /* RDFQ */
5611
    IntRegs, 
5612
    /* RDPR */
5613
    IntRegs, PRRegs, 
5614
    /* RDPSR */
5615
    IntRegs, 
5616
    /* RDTBR */
5617
    IntRegs, 
5618
    /* RDWIM */
5619
    IntRegs, 
5620
    /* RESTORED */
5621
    /* RESTOREri */
5622
    IntRegs, IntRegs, simm13Op, 
5623
    /* RESTORErr */
5624
    IntRegs, IntRegs, IntRegs, 
5625
    /* RET */
5626
    i32imm, 
5627
    /* RETL */
5628
    i32imm, 
5629
    /* RETRY */
5630
    /* RETTri */
5631
    -1, i32imm, 
5632
    /* RETTrr */
5633
    -1, -1, 
5634
    /* SAVED */
5635
    /* SAVEri */
5636
    IntRegs, IntRegs, simm13Op, 
5637
    /* SAVErr */
5638
    IntRegs, IntRegs, IntRegs, 
5639
    /* SDIVCCri */
5640
    IntRegs, IntRegs, simm13Op, 
5641
    /* SDIVCCrr */
5642
    IntRegs, IntRegs, IntRegs, 
5643
    /* SDIVXri */
5644
    IntRegs, IntRegs, i64imm, 
5645
    /* SDIVXrr */
5646
    I64Regs, I64Regs, I64Regs, 
5647
    /* SDIVri */
5648
    IntRegs, IntRegs, simm13Op, 
5649
    /* SDIVrr */
5650
    IntRegs, IntRegs, IntRegs, 
5651
    /* SETHIi */
5652
    IntRegs, i32imm, 
5653
    /* SHUTDOWN */
5654
    /* SIAM */
5655
    /* SIR */
5656
    simm13Op, 
5657
    /* SLLXri */
5658
    I64Regs, I64Regs, shift_imm6, 
5659
    /* SLLXrr */
5660
    I64Regs, I64Regs, IntRegs, 
5661
    /* SLLri */
5662
    IntRegs, IntRegs, shift_imm5, 
5663
    /* SLLrr */
5664
    IntRegs, IntRegs, IntRegs, 
5665
    /* SMACri */
5666
    IntRegs, IntRegs, simm13Op, ASRRegs, 
5667
    /* SMACrr */
5668
    IntRegs, IntRegs, IntRegs, ASRRegs, 
5669
    /* SMULCCri */
5670
    IntRegs, IntRegs, simm13Op, 
5671
    /* SMULCCrr */
5672
    IntRegs, IntRegs, IntRegs, 
5673
    /* SMULri */
5674
    IntRegs, IntRegs, simm13Op, 
5675
    /* SMULrr */
5676
    IntRegs, IntRegs, IntRegs, 
5677
    /* SRAXri */
5678
    I64Regs, I64Regs, shift_imm6, 
5679
    /* SRAXrr */
5680
    I64Regs, I64Regs, IntRegs, 
5681
    /* SRAri */
5682
    IntRegs, IntRegs, shift_imm5, 
5683
    /* SRArr */
5684
    IntRegs, IntRegs, IntRegs, 
5685
    /* SRLXri */
5686
    I64Regs, I64Regs, shift_imm6, 
5687
    /* SRLXrr */
5688
    I64Regs, I64Regs, IntRegs, 
5689
    /* SRLri */
5690
    IntRegs, IntRegs, shift_imm5, 
5691
    /* SRLrr */
5692
    IntRegs, IntRegs, IntRegs, 
5693
    /* STAri */
5694
    -1, i32imm, IntRegs, 
5695
    /* STArr */
5696
    -1, -1, IntRegs, ASITag, 
5697
    /* STBAR */
5698
    /* STBAri */
5699
    -1, i32imm, IntRegs, 
5700
    /* STBArr */
5701
    -1, -1, IntRegs, ASITag, 
5702
    /* STBri */
5703
    -1, i32imm, IntRegs, 
5704
    /* STBrr */
5705
    -1, -1, IntRegs, 
5706
    /* STCSRri */
5707
    -1, i32imm, 
5708
    /* STCSRrr */
5709
    -1, -1, 
5710
    /* STCri */
5711
    -1, i32imm, CoprocRegs, 
5712
    /* STCrr */
5713
    -1, -1, CoprocRegs, 
5714
    /* STDAri */
5715
    -1, i32imm, IntPair, 
5716
    /* STDArr */
5717
    -1, -1, IntPair, ASITag, 
5718
    /* STDCQri */
5719
    -1, i32imm, 
5720
    /* STDCQrr */
5721
    -1, -1, 
5722
    /* STDCri */
5723
    -1, i32imm, CoprocPair, 
5724
    /* STDCrr */
5725
    -1, -1, CoprocPair, 
5726
    /* STDFAri */
5727
    -1, i32imm, DFPRegs, 
5728
    /* STDFArr */
5729
    -1, -1, DFPRegs, ASITag, 
5730
    /* STDFQri */
5731
    -1, i32imm, 
5732
    /* STDFQrr */
5733
    -1, -1, 
5734
    /* STDFri */
5735
    -1, i32imm, DFPRegs, 
5736
    /* STDFrr */
5737
    -1, -1, DFPRegs, 
5738
    /* STDri */
5739
    -1, i32imm, IntPair, 
5740
    /* STDrr */
5741
    -1, -1, IntPair, 
5742
    /* STFAri */
5743
    -1, i32imm, FPRegs, 
5744
    /* STFArr */
5745
    -1, -1, FPRegs, ASITag, 
5746
    /* STFSRri */
5747
    -1, i32imm, 
5748
    /* STFSRrr */
5749
    -1, -1, 
5750
    /* STFri */
5751
    -1, i32imm, FPRegs, 
5752
    /* STFrr */
5753
    -1, -1, FPRegs, 
5754
    /* STHAri */
5755
    -1, i32imm, IntRegs, 
5756
    /* STHArr */
5757
    -1, -1, IntRegs, ASITag, 
5758
    /* STHri */
5759
    -1, i32imm, IntRegs, 
5760
    /* STHrr */
5761
    -1, -1, IntRegs, 
5762
    /* STQFAri */
5763
    -1, i32imm, QFPRegs, 
5764
    /* STQFArr */
5765
    -1, -1, QFPRegs, ASITag, 
5766
    /* STQFri */
5767
    -1, i32imm, QFPRegs, 
5768
    /* STQFrr */
5769
    -1, -1, QFPRegs, 
5770
    /* STXAri */
5771
    -1, i32imm, I64Regs, 
5772
    /* STXArr */
5773
    -1, -1, I64Regs, ASITag, 
5774
    /* STXFSRri */
5775
    -1, i32imm, 
5776
    /* STXFSRrr */
5777
    -1, -1, 
5778
    /* STXri */
5779
    -1, i32imm, I64Regs, 
5780
    /* STXrr */
5781
    -1, -1, I64Regs, 
5782
    /* STri */
5783
    -1, i32imm, IntRegs, 
5784
    /* STrr */
5785
    -1, -1, IntRegs, 
5786
    /* SUBCCri */
5787
    IntRegs, IntRegs, simm13Op, 
5788
    /* SUBCCrr */
5789
    IntRegs, IntRegs, IntRegs, 
5790
    /* SUBCri */
5791
    IntRegs, IntRegs, simm13Op, 
5792
    /* SUBCrr */
5793
    IntRegs, IntRegs, IntRegs, 
5794
    /* SUBEri */
5795
    IntRegs, IntRegs, simm13Op, 
5796
    /* SUBErr */
5797
    IntRegs, IntRegs, IntRegs, 
5798
    /* SUBri */
5799
    IntRegs, IntRegs, simm13Op, 
5800
    /* SUBrr */
5801
    IntRegs, IntRegs, IntRegs, 
5802
    /* SWAPAri */
5803
    IntRegs, -1, i32imm, IntRegs, 
5804
    /* SWAPArr */
5805
    IntRegs, -1, -1, ASITag, IntRegs, 
5806
    /* SWAPri */
5807
    IntRegs, -1, i32imm, IntRegs, 
5808
    /* SWAPrr */
5809
    IntRegs, -1, -1, IntRegs, 
5810
    /* TA1 */
5811
    /* TA3 */
5812
    /* TA5 */
5813
    /* TADDCCTVri */
5814
    IntRegs, IntRegs, simm13Op, 
5815
    /* TADDCCTVrr */
5816
    IntRegs, IntRegs, IntRegs, 
5817
    /* TADDCCri */
5818
    IntRegs, IntRegs, simm13Op, 
5819
    /* TADDCCrr */
5820
    IntRegs, IntRegs, IntRegs, 
5821
    /* TAIL_CALL */
5822
    calltarget, 
5823
    /* TAIL_CALLri */
5824
    -1, i32imm, 
5825
    /* TICCri */
5826
    IntRegs, i32imm, CCOp, 
5827
    /* TICCrr */
5828
    IntRegs, IntRegs, CCOp, 
5829
    /* TLS_ADDrr */
5830
    IntRegs, IntRegs, IntRegs, TailRelocSymTLSAdd, 
5831
    /* TLS_CALL */
5832
    calltarget, TailRelocSymTLSCall, 
5833
    /* TLS_LDXrr */
5834
    IntRegs, -1, -1, TailRelocSymTLSLoad, 
5835
    /* TLS_LDrr */
5836
    IntRegs, -1, -1, TailRelocSymTLSLoad, 
5837
    /* TRAPri */
5838
    IntRegs, i32imm, CCOp, 
5839
    /* TRAPrr */
5840
    IntRegs, IntRegs, CCOp, 
5841
    /* TSUBCCTVri */
5842
    IntRegs, IntRegs, simm13Op, 
5843
    /* TSUBCCTVrr */
5844
    IntRegs, IntRegs, IntRegs, 
5845
    /* TSUBCCri */
5846
    IntRegs, IntRegs, simm13Op, 
5847
    /* TSUBCCrr */
5848
    IntRegs, IntRegs, IntRegs, 
5849
    /* TXCCri */
5850
    IntRegs, i32imm, CCOp, 
5851
    /* TXCCrr */
5852
    IntRegs, IntRegs, CCOp, 
5853
    /* UDIVCCri */
5854
    IntRegs, IntRegs, simm13Op, 
5855
    /* UDIVCCrr */
5856
    IntRegs, IntRegs, IntRegs, 
5857
    /* UDIVXri */
5858
    IntRegs, IntRegs, i64imm, 
5859
    /* UDIVXrr */
5860
    I64Regs, I64Regs, I64Regs, 
5861
    /* UDIVri */
5862
    IntRegs, IntRegs, simm13Op, 
5863
    /* UDIVrr */
5864
    IntRegs, IntRegs, IntRegs, 
5865
    /* UMACri */
5866
    IntRegs, IntRegs, simm13Op, ASRRegs, 
5867
    /* UMACrr */
5868
    IntRegs, IntRegs, IntRegs, ASRRegs, 
5869
    /* UMULCCri */
5870
    IntRegs, IntRegs, simm13Op, 
5871
    /* UMULCCrr */
5872
    IntRegs, IntRegs, IntRegs, 
5873
    /* UMULXHI */
5874
    I64Regs, I64Regs, I64Regs, 
5875
    /* UMULri */
5876
    IntRegs, IntRegs, simm13Op, 
5877
    /* UMULrr */
5878
    IntRegs, IntRegs, IntRegs, 
5879
    /* UNIMP */
5880
    i32imm, 
5881
    /* V9FCMPD */
5882
    FCCRegs, DFPRegs, DFPRegs, 
5883
    /* V9FCMPED */
5884
    FCCRegs, DFPRegs, DFPRegs, 
5885
    /* V9FCMPEQ */
5886
    FCCRegs, QFPRegs, QFPRegs, 
5887
    /* V9FCMPES */
5888
    FCCRegs, FPRegs, FPRegs, 
5889
    /* V9FCMPQ */
5890
    FCCRegs, QFPRegs, QFPRegs, 
5891
    /* V9FCMPS */
5892
    FCCRegs, FPRegs, FPRegs, 
5893
    /* V9FMOVD_FCC */
5894
    DFPRegs, FCCRegs, DFPRegs, DFPRegs, CCOp, 
5895
    /* V9FMOVQ_FCC */
5896
    QFPRegs, FCCRegs, QFPRegs, QFPRegs, CCOp, 
5897
    /* V9FMOVS_FCC */
5898
    FPRegs, FCCRegs, FPRegs, FPRegs, CCOp, 
5899
    /* V9MOVFCCri */
5900
    IntRegs, FCCRegs, i32imm, IntRegs, CCOp, 
5901
    /* V9MOVFCCrr */
5902
    IntRegs, FCCRegs, IntRegs, IntRegs, CCOp, 
5903
    /* WRASRri */
5904
    ASRRegs, IntRegs, simm13Op, 
5905
    /* WRASRrr */
5906
    ASRRegs, IntRegs, IntRegs, 
5907
    /* WRPRri */
5908
    PRRegs, IntRegs, simm13Op, 
5909
    /* WRPRrr */
5910
    PRRegs, IntRegs, IntRegs, 
5911
    /* WRPSRri */
5912
    IntRegs, simm13Op, 
5913
    /* WRPSRrr */
5914
    IntRegs, IntRegs, 
5915
    /* WRTBRri */
5916
    IntRegs, simm13Op, 
5917
    /* WRTBRrr */
5918
    IntRegs, IntRegs, 
5919
    /* WRWIMri */
5920
    IntRegs, simm13Op, 
5921
    /* WRWIMrr */
5922
    IntRegs, IntRegs, 
5923
    /* XMULX */
5924
    I64Regs, I64Regs, I64Regs, 
5925
    /* XMULXHI */
5926
    I64Regs, I64Regs, I64Regs, 
5927
    /* XNORCCri */
5928
    IntRegs, IntRegs, simm13Op, 
5929
    /* XNORCCrr */
5930
    IntRegs, IntRegs, IntRegs, 
5931
    /* XNORri */
5932
    IntRegs, IntRegs, simm13Op, 
5933
    /* XNORrr */
5934
    IntRegs, IntRegs, IntRegs, 
5935
    /* XORCCri */
5936
    IntRegs, IntRegs, simm13Op, 
5937
    /* XORCCrr */
5938
    IntRegs, IntRegs, IntRegs, 
5939
    /* XORri */
5940
    IntRegs, IntRegs, simm13Op, 
5941
    /* XORrr */
5942
    IntRegs, IntRegs, IntRegs, 
5943
  };
5944
  return OpcodeOperandTypes[Offsets[Opcode] + OpIdx];
5945
}
5946
} // end namespace SP
5947
} // end namespace llvm
5948
#endif // GET_INSTRINFO_OPERAND_TYPE
5949
5950
#ifdef GET_INSTRINFO_MEM_OPERAND_SIZE
5951
#undef GET_INSTRINFO_MEM_OPERAND_SIZE
5952
namespace llvm {
5953
namespace SP {
5954
LLVM_READONLY
5955
static int getMemOperandSize(int OpType) {
5956
  switch (OpType) {
5957
  default: return 0;
5958
  }
5959
}
5960
} // end namespace SP
5961
} // end namespace llvm
5962
#endif // GET_INSTRINFO_MEM_OPERAND_SIZE
5963
5964
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
5965
#undef GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
5966
namespace llvm {
5967
namespace Sparc {
5968
LLVM_READONLY static unsigned
5969
getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {
5970
  return LogicalOpIdx;
5971
}
5972
LLVM_READONLY static inline unsigned
5973
getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {
5974
  auto S = 0U;
5975
  for (auto i = 0U; i < LogicalOpIdx; ++i)
5976
    S += getLogicalOperandSize(Opcode, i);
5977
  return S;
5978
}
5979
} // end namespace Sparc
5980
} // end namespace llvm
5981
#endif // GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP
5982
5983
#ifdef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
5984
#undef GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
5985
namespace llvm {
5986
namespace Sparc {
5987
LLVM_READONLY static int
5988
getLogicalOperandType(uint16_t Opcode, uint16_t LogicalOpIdx) {
5989
  return -1;
5990
}
5991
} // end namespace Sparc
5992
} // end namespace llvm
5993
#endif // GET_INSTRINFO_LOGICAL_OPERAND_TYPE_MAP
5994
5995
#ifdef GET_INSTRINFO_MC_HELPER_DECLS
5996
#undef GET_INSTRINFO_MC_HELPER_DECLS
5997
5998
namespace llvm {
5999
class MCInst;
6000
class FeatureBitset;
6001
6002
namespace Sparc_MC {
6003
6004
void verifyInstructionPredicates(unsigned Opcode, const FeatureBitset &Features);
6005
6006
} // end namespace Sparc_MC
6007
} // end namespace llvm
6008
6009
#endif // GET_INSTRINFO_MC_HELPER_DECLS
6010
6011
#ifdef GET_INSTRINFO_MC_HELPERS
6012
#undef GET_INSTRINFO_MC_HELPERS
6013
6014
namespace llvm {
6015
namespace Sparc_MC {
6016
6017
} // end namespace Sparc_MC
6018
} // end namespace llvm
6019
6020
#endif // GET_GENISTRINFO_MC_HELPERS
6021
6022
#if (defined(ENABLE_INSTR_PREDICATE_VERIFIER) && !defined(NDEBUG)) ||\
6023
    defined(GET_AVAILABLE_OPCODE_CHECKER)
6024
#define GET_COMPUTE_FEATURES
6025
#endif
6026
#ifdef GET_COMPUTE_FEATURES
6027
#undef GET_COMPUTE_FEATURES
6028
namespace llvm {
6029
namespace Sparc_MC {
6030
6031
// Bits for subtarget features that participate in instruction matching.
6032
enum SubtargetFeatureBits : uint8_t {
6033
  Feature_UseSoftMulDivBit = 6,
6034
  Feature_HasV9Bit = 2,
6035
  Feature_HasVISBit = 3,
6036
  Feature_HasVIS2Bit = 4,
6037
  Feature_HasVIS3Bit = 5,
6038
  Feature_HasCASABit = 0,
6039
  Feature_HasPWRPSRBit = 1,
6040
};
6041
6042
0
inline FeatureBitset computeAvailableFeatures(const FeatureBitset &FB) {
6043
0
  FeatureBitset Features;
6044
0
  if (FB[Sparc::FeatureSoftMulDiv])
6045
0
    Features.set(Feature_UseSoftMulDivBit);
6046
0
  if (FB[Sparc::FeatureV9])
6047
0
    Features.set(Feature_HasV9Bit);
6048
0
  if (FB[Sparc::FeatureVIS])
6049
0
    Features.set(Feature_HasVISBit);
6050
0
  if (FB[Sparc::FeatureVIS2])
6051
0
    Features.set(Feature_HasVIS2Bit);
6052
0
  if (FB[Sparc::FeatureVIS3])
6053
0
    Features.set(Feature_HasVIS3Bit);
6054
0
  if (FB[Sparc::LeonCASA] || FB[Sparc::FeatureV9])
6055
0
    Features.set(Feature_HasCASABit);
6056
0
  if (FB[Sparc::FeaturePWRPSR])
6057
0
    Features.set(Feature_HasPWRPSRBit);
6058
0
  return Features;
6059
0
}
6060
6061
0
inline FeatureBitset computeRequiredFeatures(unsigned Opcode) {
6062
0
  enum : uint8_t {
6063
0
    CEFBS_None,
6064
0
    CEFBS_HasCASA,
6065
0
    CEFBS_HasPWRPSR,
6066
0
    CEFBS_HasV9,
6067
0
    CEFBS_HasVIS,
6068
0
    CEFBS_HasVIS2,
6069
0
    CEFBS_HasVIS3,
6070
0
  };
6071
6072
0
  static constexpr FeatureBitset FeatureBitsets[] = {
6073
0
    {}, // CEFBS_None
6074
0
    {Feature_HasCASABit, },
6075
0
    {Feature_HasPWRPSRBit, },
6076
0
    {Feature_HasV9Bit, },
6077
0
    {Feature_HasVISBit, },
6078
0
    {Feature_HasVIS2Bit, },
6079
0
    {Feature_HasVIS3Bit, },
6080
0
  };
6081
0
  static constexpr uint8_t RequiredFeaturesRefs[] = {
6082
0
    CEFBS_None, // PHI = 0
6083
0
    CEFBS_None, // INLINEASM = 1
6084
0
    CEFBS_None, // INLINEASM_BR = 2
6085
0
    CEFBS_None, // CFI_INSTRUCTION = 3
6086
0
    CEFBS_None, // EH_LABEL = 4
6087
0
    CEFBS_None, // GC_LABEL = 5
6088
0
    CEFBS_None, // ANNOTATION_LABEL = 6
6089
0
    CEFBS_None, // KILL = 7
6090
0
    CEFBS_None, // EXTRACT_SUBREG = 8
6091
0
    CEFBS_None, // INSERT_SUBREG = 9
6092
0
    CEFBS_None, // IMPLICIT_DEF = 10
6093
0
    CEFBS_None, // SUBREG_TO_REG = 11
6094
0
    CEFBS_None, // COPY_TO_REGCLASS = 12
6095
0
    CEFBS_None, // DBG_VALUE = 13
6096
0
    CEFBS_None, // DBG_VALUE_LIST = 14
6097
0
    CEFBS_None, // DBG_INSTR_REF = 15
6098
0
    CEFBS_None, // DBG_PHI = 16
6099
0
    CEFBS_None, // DBG_LABEL = 17
6100
0
    CEFBS_None, // REG_SEQUENCE = 18
6101
0
    CEFBS_None, // COPY = 19
6102
0
    CEFBS_None, // BUNDLE = 20
6103
0
    CEFBS_None, // LIFETIME_START = 21
6104
0
    CEFBS_None, // LIFETIME_END = 22
6105
0
    CEFBS_None, // PSEUDO_PROBE = 23
6106
0
    CEFBS_None, // ARITH_FENCE = 24
6107
0
    CEFBS_None, // STACKMAP = 25
6108
0
    CEFBS_None, // FENTRY_CALL = 26
6109
0
    CEFBS_None, // PATCHPOINT = 27
6110
0
    CEFBS_None, // LOAD_STACK_GUARD = 28
6111
0
    CEFBS_None, // PREALLOCATED_SETUP = 29
6112
0
    CEFBS_None, // PREALLOCATED_ARG = 30
6113
0
    CEFBS_None, // STATEPOINT = 31
6114
0
    CEFBS_None, // LOCAL_ESCAPE = 32
6115
0
    CEFBS_None, // FAULTING_OP = 33
6116
0
    CEFBS_None, // PATCHABLE_OP = 34
6117
0
    CEFBS_None, // PATCHABLE_FUNCTION_ENTER = 35
6118
0
    CEFBS_None, // PATCHABLE_RET = 36
6119
0
    CEFBS_None, // PATCHABLE_FUNCTION_EXIT = 37
6120
0
    CEFBS_None, // PATCHABLE_TAIL_CALL = 38
6121
0
    CEFBS_None, // PATCHABLE_EVENT_CALL = 39
6122
0
    CEFBS_None, // PATCHABLE_TYPED_EVENT_CALL = 40
6123
0
    CEFBS_None, // ICALL_BRANCH_FUNNEL = 41
6124
0
    CEFBS_None, // MEMBARRIER = 42
6125
0
    CEFBS_None, // JUMP_TABLE_DEBUG_INFO = 43
6126
0
    CEFBS_None, // G_ASSERT_SEXT = 44
6127
0
    CEFBS_None, // G_ASSERT_ZEXT = 45
6128
0
    CEFBS_None, // G_ASSERT_ALIGN = 46
6129
0
    CEFBS_None, // G_ADD = 47
6130
0
    CEFBS_None, // G_SUB = 48
6131
0
    CEFBS_None, // G_MUL = 49
6132
0
    CEFBS_None, // G_SDIV = 50
6133
0
    CEFBS_None, // G_UDIV = 51
6134
0
    CEFBS_None, // G_SREM = 52
6135
0
    CEFBS_None, // G_UREM = 53
6136
0
    CEFBS_None, // G_SDIVREM = 54
6137
0
    CEFBS_None, // G_UDIVREM = 55
6138
0
    CEFBS_None, // G_AND = 56
6139
0
    CEFBS_None, // G_OR = 57
6140
0
    CEFBS_None, // G_XOR = 58
6141
0
    CEFBS_None, // G_IMPLICIT_DEF = 59
6142
0
    CEFBS_None, // G_PHI = 60
6143
0
    CEFBS_None, // G_FRAME_INDEX = 61
6144
0
    CEFBS_None, // G_GLOBAL_VALUE = 62
6145
0
    CEFBS_None, // G_CONSTANT_POOL = 63
6146
0
    CEFBS_None, // G_EXTRACT = 64
6147
0
    CEFBS_None, // G_UNMERGE_VALUES = 65
6148
0
    CEFBS_None, // G_INSERT = 66
6149
0
    CEFBS_None, // G_MERGE_VALUES = 67
6150
0
    CEFBS_None, // G_BUILD_VECTOR = 68
6151
0
    CEFBS_None, // G_BUILD_VECTOR_TRUNC = 69
6152
0
    CEFBS_None, // G_CONCAT_VECTORS = 70
6153
0
    CEFBS_None, // G_PTRTOINT = 71
6154
0
    CEFBS_None, // G_INTTOPTR = 72
6155
0
    CEFBS_None, // G_BITCAST = 73
6156
0
    CEFBS_None, // G_FREEZE = 74
6157
0
    CEFBS_None, // G_CONSTANT_FOLD_BARRIER = 75
6158
0
    CEFBS_None, // G_INTRINSIC_FPTRUNC_ROUND = 76
6159
0
    CEFBS_None, // G_INTRINSIC_TRUNC = 77
6160
0
    CEFBS_None, // G_INTRINSIC_ROUND = 78
6161
0
    CEFBS_None, // G_INTRINSIC_LRINT = 79
6162
0
    CEFBS_None, // G_INTRINSIC_ROUNDEVEN = 80
6163
0
    CEFBS_None, // G_READCYCLECOUNTER = 81
6164
0
    CEFBS_None, // G_LOAD = 82
6165
0
    CEFBS_None, // G_SEXTLOAD = 83
6166
0
    CEFBS_None, // G_ZEXTLOAD = 84
6167
0
    CEFBS_None, // G_INDEXED_LOAD = 85
6168
0
    CEFBS_None, // G_INDEXED_SEXTLOAD = 86
6169
0
    CEFBS_None, // G_INDEXED_ZEXTLOAD = 87
6170
0
    CEFBS_None, // G_STORE = 88
6171
0
    CEFBS_None, // G_INDEXED_STORE = 89
6172
0
    CEFBS_None, // G_ATOMIC_CMPXCHG_WITH_SUCCESS = 90
6173
0
    CEFBS_None, // G_ATOMIC_CMPXCHG = 91
6174
0
    CEFBS_None, // G_ATOMICRMW_XCHG = 92
6175
0
    CEFBS_None, // G_ATOMICRMW_ADD = 93
6176
0
    CEFBS_None, // G_ATOMICRMW_SUB = 94
6177
0
    CEFBS_None, // G_ATOMICRMW_AND = 95
6178
0
    CEFBS_None, // G_ATOMICRMW_NAND = 96
6179
0
    CEFBS_None, // G_ATOMICRMW_OR = 97
6180
0
    CEFBS_None, // G_ATOMICRMW_XOR = 98
6181
0
    CEFBS_None, // G_ATOMICRMW_MAX = 99
6182
0
    CEFBS_None, // G_ATOMICRMW_MIN = 100
6183
0
    CEFBS_None, // G_ATOMICRMW_UMAX = 101
6184
0
    CEFBS_None, // G_ATOMICRMW_UMIN = 102
6185
0
    CEFBS_None, // G_ATOMICRMW_FADD = 103
6186
0
    CEFBS_None, // G_ATOMICRMW_FSUB = 104
6187
0
    CEFBS_None, // G_ATOMICRMW_FMAX = 105
6188
0
    CEFBS_None, // G_ATOMICRMW_FMIN = 106
6189
0
    CEFBS_None, // G_ATOMICRMW_UINC_WRAP = 107
6190
0
    CEFBS_None, // G_ATOMICRMW_UDEC_WRAP = 108
6191
0
    CEFBS_None, // G_FENCE = 109
6192
0
    CEFBS_None, // G_PREFETCH = 110
6193
0
    CEFBS_None, // G_BRCOND = 111
6194
0
    CEFBS_None, // G_BRINDIRECT = 112
6195
0
    CEFBS_None, // G_INVOKE_REGION_START = 113
6196
0
    CEFBS_None, // G_INTRINSIC = 114
6197
0
    CEFBS_None, // G_INTRINSIC_W_SIDE_EFFECTS = 115
6198
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT = 116
6199
0
    CEFBS_None, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS = 117
6200
0
    CEFBS_None, // G_ANYEXT = 118
6201
0
    CEFBS_None, // G_TRUNC = 119
6202
0
    CEFBS_None, // G_CONSTANT = 120
6203
0
    CEFBS_None, // G_FCONSTANT = 121
6204
0
    CEFBS_None, // G_VASTART = 122
6205
0
    CEFBS_None, // G_VAARG = 123
6206
0
    CEFBS_None, // G_SEXT = 124
6207
0
    CEFBS_None, // G_SEXT_INREG = 125
6208
0
    CEFBS_None, // G_ZEXT = 126
6209
0
    CEFBS_None, // G_SHL = 127
6210
0
    CEFBS_None, // G_LSHR = 128
6211
0
    CEFBS_None, // G_ASHR = 129
6212
0
    CEFBS_None, // G_FSHL = 130
6213
0
    CEFBS_None, // G_FSHR = 131
6214
0
    CEFBS_None, // G_ROTR = 132
6215
0
    CEFBS_None, // G_ROTL = 133
6216
0
    CEFBS_None, // G_ICMP = 134
6217
0
    CEFBS_None, // G_FCMP = 135
6218
0
    CEFBS_None, // G_SELECT = 136
6219
0
    CEFBS_None, // G_UADDO = 137
6220
0
    CEFBS_None, // G_UADDE = 138
6221
0
    CEFBS_None, // G_USUBO = 139
6222
0
    CEFBS_None, // G_USUBE = 140
6223
0
    CEFBS_None, // G_SADDO = 141
6224
0
    CEFBS_None, // G_SADDE = 142
6225
0
    CEFBS_None, // G_SSUBO = 143
6226
0
    CEFBS_None, // G_SSUBE = 144
6227
0
    CEFBS_None, // G_UMULO = 145
6228
0
    CEFBS_None, // G_SMULO = 146
6229
0
    CEFBS_None, // G_UMULH = 147
6230
0
    CEFBS_None, // G_SMULH = 148
6231
0
    CEFBS_None, // G_UADDSAT = 149
6232
0
    CEFBS_None, // G_SADDSAT = 150
6233
0
    CEFBS_None, // G_USUBSAT = 151
6234
0
    CEFBS_None, // G_SSUBSAT = 152
6235
0
    CEFBS_None, // G_USHLSAT = 153
6236
0
    CEFBS_None, // G_SSHLSAT = 154
6237
0
    CEFBS_None, // G_SMULFIX = 155
6238
0
    CEFBS_None, // G_UMULFIX = 156
6239
0
    CEFBS_None, // G_SMULFIXSAT = 157
6240
0
    CEFBS_None, // G_UMULFIXSAT = 158
6241
0
    CEFBS_None, // G_SDIVFIX = 159
6242
0
    CEFBS_None, // G_UDIVFIX = 160
6243
0
    CEFBS_None, // G_SDIVFIXSAT = 161
6244
0
    CEFBS_None, // G_UDIVFIXSAT = 162
6245
0
    CEFBS_None, // G_FADD = 163
6246
0
    CEFBS_None, // G_FSUB = 164
6247
0
    CEFBS_None, // G_FMUL = 165
6248
0
    CEFBS_None, // G_FMA = 166
6249
0
    CEFBS_None, // G_FMAD = 167
6250
0
    CEFBS_None, // G_FDIV = 168
6251
0
    CEFBS_None, // G_FREM = 169
6252
0
    CEFBS_None, // G_FPOW = 170
6253
0
    CEFBS_None, // G_FPOWI = 171
6254
0
    CEFBS_None, // G_FEXP = 172
6255
0
    CEFBS_None, // G_FEXP2 = 173
6256
0
    CEFBS_None, // G_FEXP10 = 174
6257
0
    CEFBS_None, // G_FLOG = 175
6258
0
    CEFBS_None, // G_FLOG2 = 176
6259
0
    CEFBS_None, // G_FLOG10 = 177
6260
0
    CEFBS_None, // G_FLDEXP = 178
6261
0
    CEFBS_None, // G_FFREXP = 179
6262
0
    CEFBS_None, // G_FNEG = 180
6263
0
    CEFBS_None, // G_FPEXT = 181
6264
0
    CEFBS_None, // G_FPTRUNC = 182
6265
0
    CEFBS_None, // G_FPTOSI = 183
6266
0
    CEFBS_None, // G_FPTOUI = 184
6267
0
    CEFBS_None, // G_SITOFP = 185
6268
0
    CEFBS_None, // G_UITOFP = 186
6269
0
    CEFBS_None, // G_FABS = 187
6270
0
    CEFBS_None, // G_FCOPYSIGN = 188
6271
0
    CEFBS_None, // G_IS_FPCLASS = 189
6272
0
    CEFBS_None, // G_FCANONICALIZE = 190
6273
0
    CEFBS_None, // G_FMINNUM = 191
6274
0
    CEFBS_None, // G_FMAXNUM = 192
6275
0
    CEFBS_None, // G_FMINNUM_IEEE = 193
6276
0
    CEFBS_None, // G_FMAXNUM_IEEE = 194
6277
0
    CEFBS_None, // G_FMINIMUM = 195
6278
0
    CEFBS_None, // G_FMAXIMUM = 196
6279
0
    CEFBS_None, // G_GET_FPENV = 197
6280
0
    CEFBS_None, // G_SET_FPENV = 198
6281
0
    CEFBS_None, // G_RESET_FPENV = 199
6282
0
    CEFBS_None, // G_GET_FPMODE = 200
6283
0
    CEFBS_None, // G_SET_FPMODE = 201
6284
0
    CEFBS_None, // G_RESET_FPMODE = 202
6285
0
    CEFBS_None, // G_PTR_ADD = 203
6286
0
    CEFBS_None, // G_PTRMASK = 204
6287
0
    CEFBS_None, // G_SMIN = 205
6288
0
    CEFBS_None, // G_SMAX = 206
6289
0
    CEFBS_None, // G_UMIN = 207
6290
0
    CEFBS_None, // G_UMAX = 208
6291
0
    CEFBS_None, // G_ABS = 209
6292
0
    CEFBS_None, // G_LROUND = 210
6293
0
    CEFBS_None, // G_LLROUND = 211
6294
0
    CEFBS_None, // G_BR = 212
6295
0
    CEFBS_None, // G_BRJT = 213
6296
0
    CEFBS_None, // G_INSERT_VECTOR_ELT = 214
6297
0
    CEFBS_None, // G_EXTRACT_VECTOR_ELT = 215
6298
0
    CEFBS_None, // G_SHUFFLE_VECTOR = 216
6299
0
    CEFBS_None, // G_CTTZ = 217
6300
0
    CEFBS_None, // G_CTTZ_ZERO_UNDEF = 218
6301
0
    CEFBS_None, // G_CTLZ = 219
6302
0
    CEFBS_None, // G_CTLZ_ZERO_UNDEF = 220
6303
0
    CEFBS_None, // G_CTPOP = 221
6304
0
    CEFBS_None, // G_BSWAP = 222
6305
0
    CEFBS_None, // G_BITREVERSE = 223
6306
0
    CEFBS_None, // G_FCEIL = 224
6307
0
    CEFBS_None, // G_FCOS = 225
6308
0
    CEFBS_None, // G_FSIN = 226
6309
0
    CEFBS_None, // G_FSQRT = 227
6310
0
    CEFBS_None, // G_FFLOOR = 228
6311
0
    CEFBS_None, // G_FRINT = 229
6312
0
    CEFBS_None, // G_FNEARBYINT = 230
6313
0
    CEFBS_None, // G_ADDRSPACE_CAST = 231
6314
0
    CEFBS_None, // G_BLOCK_ADDR = 232
6315
0
    CEFBS_None, // G_JUMP_TABLE = 233
6316
0
    CEFBS_None, // G_DYN_STACKALLOC = 234
6317
0
    CEFBS_None, // G_STACKSAVE = 235
6318
0
    CEFBS_None, // G_STACKRESTORE = 236
6319
0
    CEFBS_None, // G_STRICT_FADD = 237
6320
0
    CEFBS_None, // G_STRICT_FSUB = 238
6321
0
    CEFBS_None, // G_STRICT_FMUL = 239
6322
0
    CEFBS_None, // G_STRICT_FDIV = 240
6323
0
    CEFBS_None, // G_STRICT_FREM = 241
6324
0
    CEFBS_None, // G_STRICT_FMA = 242
6325
0
    CEFBS_None, // G_STRICT_FSQRT = 243
6326
0
    CEFBS_None, // G_STRICT_FLDEXP = 244
6327
0
    CEFBS_None, // G_READ_REGISTER = 245
6328
0
    CEFBS_None, // G_WRITE_REGISTER = 246
6329
0
    CEFBS_None, // G_MEMCPY = 247
6330
0
    CEFBS_None, // G_MEMCPY_INLINE = 248
6331
0
    CEFBS_None, // G_MEMMOVE = 249
6332
0
    CEFBS_None, // G_MEMSET = 250
6333
0
    CEFBS_None, // G_BZERO = 251
6334
0
    CEFBS_None, // G_VECREDUCE_SEQ_FADD = 252
6335
0
    CEFBS_None, // G_VECREDUCE_SEQ_FMUL = 253
6336
0
    CEFBS_None, // G_VECREDUCE_FADD = 254
6337
0
    CEFBS_None, // G_VECREDUCE_FMUL = 255
6338
0
    CEFBS_None, // G_VECREDUCE_FMAX = 256
6339
0
    CEFBS_None, // G_VECREDUCE_FMIN = 257
6340
0
    CEFBS_None, // G_VECREDUCE_FMAXIMUM = 258
6341
0
    CEFBS_None, // G_VECREDUCE_FMINIMUM = 259
6342
0
    CEFBS_None, // G_VECREDUCE_ADD = 260
6343
0
    CEFBS_None, // G_VECREDUCE_MUL = 261
6344
0
    CEFBS_None, // G_VECREDUCE_AND = 262
6345
0
    CEFBS_None, // G_VECREDUCE_OR = 263
6346
0
    CEFBS_None, // G_VECREDUCE_XOR = 264
6347
0
    CEFBS_None, // G_VECREDUCE_SMAX = 265
6348
0
    CEFBS_None, // G_VECREDUCE_SMIN = 266
6349
0
    CEFBS_None, // G_VECREDUCE_UMAX = 267
6350
0
    CEFBS_None, // G_VECREDUCE_UMIN = 268
6351
0
    CEFBS_None, // G_SBFX = 269
6352
0
    CEFBS_None, // G_UBFX = 270
6353
0
    CEFBS_None, // ADJCALLSTACKDOWN = 271
6354
0
    CEFBS_None, // ADJCALLSTACKUP = 272
6355
0
    CEFBS_None, // GETPCX = 273
6356
0
    CEFBS_None, // SELECT_CC_DFP_FCC = 274
6357
0
    CEFBS_None, // SELECT_CC_DFP_ICC = 275
6358
0
    CEFBS_None, // SELECT_CC_DFP_XCC = 276
6359
0
    CEFBS_None, // SELECT_CC_FP_FCC = 277
6360
0
    CEFBS_None, // SELECT_CC_FP_ICC = 278
6361
0
    CEFBS_None, // SELECT_CC_FP_XCC = 279
6362
0
    CEFBS_None, // SELECT_CC_Int_FCC = 280
6363
0
    CEFBS_None, // SELECT_CC_Int_ICC = 281
6364
0
    CEFBS_None, // SELECT_CC_Int_XCC = 282
6365
0
    CEFBS_None, // SELECT_CC_QFP_FCC = 283
6366
0
    CEFBS_None, // SELECT_CC_QFP_ICC = 284
6367
0
    CEFBS_None, // SELECT_CC_QFP_XCC = 285
6368
0
    CEFBS_None, // SET = 286
6369
0
    CEFBS_HasV9, // SETX = 287
6370
0
    CEFBS_None, // ADDCCri = 288
6371
0
    CEFBS_None, // ADDCCrr = 289
6372
0
    CEFBS_None, // ADDCri = 290
6373
0
    CEFBS_None, // ADDCrr = 291
6374
0
    CEFBS_None, // ADDEri = 292
6375
0
    CEFBS_None, // ADDErr = 293
6376
0
    CEFBS_HasVIS3, // ADDXC = 294
6377
0
    CEFBS_HasVIS3, // ADDXCCC = 295
6378
0
    CEFBS_None, // ADDri = 296
6379
0
    CEFBS_None, // ADDrr = 297
6380
0
    CEFBS_HasVIS, // ALIGNADDR = 298
6381
0
    CEFBS_HasVIS, // ALIGNADDRL = 299
6382
0
    CEFBS_None, // ANDCCri = 300
6383
0
    CEFBS_None, // ANDCCrr = 301
6384
0
    CEFBS_None, // ANDNCCri = 302
6385
0
    CEFBS_None, // ANDNCCrr = 303
6386
0
    CEFBS_None, // ANDNri = 304
6387
0
    CEFBS_None, // ANDNrr = 305
6388
0
    CEFBS_None, // ANDri = 306
6389
0
    CEFBS_None, // ANDrr = 307
6390
0
    CEFBS_HasVIS, // ARRAY16 = 308
6391
0
    CEFBS_HasVIS, // ARRAY32 = 309
6392
0
    CEFBS_HasVIS, // ARRAY8 = 310
6393
0
    CEFBS_None, // BA = 311
6394
0
    CEFBS_None, // BCOND = 312
6395
0
    CEFBS_None, // BCONDA = 313
6396
0
    CEFBS_None, // BINDri = 314
6397
0
    CEFBS_None, // BINDrr = 315
6398
0
    CEFBS_HasVIS2, // BMASK = 316
6399
0
    CEFBS_HasV9, // BPFCC = 317
6400
0
    CEFBS_HasV9, // BPFCCA = 318
6401
0
    CEFBS_HasV9, // BPFCCANT = 319
6402
0
    CEFBS_HasV9, // BPFCCNT = 320
6403
0
    CEFBS_HasV9, // BPICC = 321
6404
0
    CEFBS_HasV9, // BPICCA = 322
6405
0
    CEFBS_HasV9, // BPICCANT = 323
6406
0
    CEFBS_HasV9, // BPICCNT = 324
6407
0
    CEFBS_None, // BPR = 325
6408
0
    CEFBS_None, // BPRA = 326
6409
0
    CEFBS_None, // BPRANT = 327
6410
0
    CEFBS_None, // BPRNT = 328
6411
0
    CEFBS_None, // BPXCC = 329
6412
0
    CEFBS_None, // BPXCCA = 330
6413
0
    CEFBS_None, // BPXCCANT = 331
6414
0
    CEFBS_None, // BPXCCNT = 332
6415
0
    CEFBS_HasVIS2, // BSHUFFLE = 333
6416
0
    CEFBS_None, // CALL = 334
6417
0
    CEFBS_None, // CALLri = 335
6418
0
    CEFBS_None, // CALLrr = 336
6419
0
    CEFBS_HasV9, // CASAri = 337
6420
0
    CEFBS_HasCASA, // CASArr = 338
6421
0
    CEFBS_HasV9, // CASXAri = 339
6422
0
    CEFBS_HasV9, // CASXArr = 340
6423
0
    CEFBS_None, // CBCOND = 341
6424
0
    CEFBS_None, // CBCONDA = 342
6425
0
    CEFBS_HasVIS3, // CMASK16 = 343
6426
0
    CEFBS_HasVIS3, // CMASK32 = 344
6427
0
    CEFBS_HasVIS3, // CMASK8 = 345
6428
0
    CEFBS_HasV9, // DONE = 346
6429
0
    CEFBS_HasVIS, // EDGE16 = 347
6430
0
    CEFBS_HasVIS, // EDGE16L = 348
6431
0
    CEFBS_HasVIS2, // EDGE16LN = 349
6432
0
    CEFBS_HasVIS2, // EDGE16N = 350
6433
0
    CEFBS_HasVIS, // EDGE32 = 351
6434
0
    CEFBS_HasVIS, // EDGE32L = 352
6435
0
    CEFBS_HasVIS2, // EDGE32LN = 353
6436
0
    CEFBS_HasVIS2, // EDGE32N = 354
6437
0
    CEFBS_HasVIS, // EDGE8 = 355
6438
0
    CEFBS_HasVIS, // EDGE8L = 356
6439
0
    CEFBS_HasVIS2, // EDGE8LN = 357
6440
0
    CEFBS_HasVIS2, // EDGE8N = 358
6441
0
    CEFBS_HasV9, // FABSD = 359
6442
0
    CEFBS_HasV9, // FABSQ = 360
6443
0
    CEFBS_None, // FABSS = 361
6444
0
    CEFBS_None, // FADDD = 362
6445
0
    CEFBS_None, // FADDQ = 363
6446
0
    CEFBS_None, // FADDS = 364
6447
0
    CEFBS_HasVIS, // FALIGNADATA = 365
6448
0
    CEFBS_HasVIS, // FAND = 366
6449
0
    CEFBS_HasVIS, // FANDNOT1 = 367
6450
0
    CEFBS_HasVIS, // FANDNOT1S = 368
6451
0
    CEFBS_HasVIS, // FANDNOT2 = 369
6452
0
    CEFBS_HasVIS, // FANDNOT2S = 370
6453
0
    CEFBS_HasVIS, // FANDS = 371
6454
0
    CEFBS_None, // FBCOND = 372
6455
0
    CEFBS_None, // FBCONDA = 373
6456
0
    CEFBS_HasV9, // FBCONDA_V9 = 374
6457
0
    CEFBS_HasV9, // FBCOND_V9 = 375
6458
0
    CEFBS_HasVIS3, // FCHKSM16 = 376
6459
0
    CEFBS_None, // FCMPD = 377
6460
0
    CEFBS_HasV9, // FCMPD_V9 = 378
6461
0
    CEFBS_HasVIS, // FCMPEQ16 = 379
6462
0
    CEFBS_HasVIS, // FCMPEQ32 = 380
6463
0
    CEFBS_HasVIS, // FCMPGT16 = 381
6464
0
    CEFBS_HasVIS, // FCMPGT32 = 382
6465
0
    CEFBS_HasVIS, // FCMPLE16 = 383
6466
0
    CEFBS_HasVIS, // FCMPLE32 = 384
6467
0
    CEFBS_HasVIS, // FCMPNE16 = 385
6468
0
    CEFBS_HasVIS, // FCMPNE32 = 386
6469
0
    CEFBS_None, // FCMPQ = 387
6470
0
    CEFBS_HasV9, // FCMPQ_V9 = 388
6471
0
    CEFBS_None, // FCMPS = 389
6472
0
    CEFBS_HasV9, // FCMPS_V9 = 390
6473
0
    CEFBS_None, // FDIVD = 391
6474
0
    CEFBS_None, // FDIVQ = 392
6475
0
    CEFBS_None, // FDIVS = 393
6476
0
    CEFBS_None, // FDMULQ = 394
6477
0
    CEFBS_None, // FDTOI = 395
6478
0
    CEFBS_None, // FDTOQ = 396
6479
0
    CEFBS_None, // FDTOS = 397
6480
0
    CEFBS_None, // FDTOX = 398
6481
0
    CEFBS_HasVIS, // FEXPAND = 399
6482
0
    CEFBS_HasVIS3, // FHADDD = 400
6483
0
    CEFBS_HasVIS3, // FHADDS = 401
6484
0
    CEFBS_HasVIS3, // FHSUBD = 402
6485
0
    CEFBS_HasVIS3, // FHSUBS = 403
6486
0
    CEFBS_None, // FITOD = 404
6487
0
    CEFBS_None, // FITOQ = 405
6488
0
    CEFBS_None, // FITOS = 406
6489
0
    CEFBS_HasVIS3, // FLCMPD = 407
6490
0
    CEFBS_HasVIS3, // FLCMPS = 408
6491
0
    CEFBS_None, // FLUSH = 409
6492
0
    CEFBS_HasV9, // FLUSHW = 410
6493
0
    CEFBS_None, // FLUSHri = 411
6494
0
    CEFBS_None, // FLUSHrr = 412
6495
0
    CEFBS_HasVIS3, // FMEAN16 = 413
6496
0
    CEFBS_HasV9, // FMOVD = 414
6497
0
    CEFBS_HasV9, // FMOVD_FCC = 415
6498
0
    CEFBS_HasV9, // FMOVD_ICC = 416
6499
0
    CEFBS_None, // FMOVD_XCC = 417
6500
0
    CEFBS_HasV9, // FMOVQ = 418
6501
0
    CEFBS_HasV9, // FMOVQ_FCC = 419
6502
0
    CEFBS_HasV9, // FMOVQ_ICC = 420
6503
0
    CEFBS_None, // FMOVQ_XCC = 421
6504
0
    CEFBS_None, // FMOVRD = 422
6505
0
    CEFBS_None, // FMOVRQ = 423
6506
0
    CEFBS_None, // FMOVRS = 424
6507
0
    CEFBS_None, // FMOVS = 425
6508
0
    CEFBS_HasV9, // FMOVS_FCC = 426
6509
0
    CEFBS_HasV9, // FMOVS_ICC = 427
6510
0
    CEFBS_None, // FMOVS_XCC = 428
6511
0
    CEFBS_HasVIS, // FMUL8SUX16 = 429
6512
0
    CEFBS_HasVIS, // FMUL8ULX16 = 430
6513
0
    CEFBS_HasVIS, // FMUL8X16 = 431
6514
0
    CEFBS_HasVIS, // FMUL8X16AL = 432
6515
0
    CEFBS_HasVIS, // FMUL8X16AU = 433
6516
0
    CEFBS_None, // FMULD = 434
6517
0
    CEFBS_HasVIS, // FMULD8SUX16 = 435
6518
0
    CEFBS_HasVIS, // FMULD8ULX16 = 436
6519
0
    CEFBS_None, // FMULQ = 437
6520
0
    CEFBS_None, // FMULS = 438
6521
0
    CEFBS_HasVIS3, // FNADDD = 439
6522
0
    CEFBS_HasVIS3, // FNADDS = 440
6523
0
    CEFBS_HasVIS, // FNAND = 441
6524
0
    CEFBS_HasVIS, // FNANDS = 442
6525
0
    CEFBS_HasV9, // FNEGD = 443
6526
0
    CEFBS_HasV9, // FNEGQ = 444
6527
0
    CEFBS_None, // FNEGS = 445
6528
0
    CEFBS_HasVIS3, // FNHADDD = 446
6529
0
    CEFBS_HasVIS3, // FNHADDS = 447
6530
0
    CEFBS_HasVIS3, // FNMULD = 448
6531
0
    CEFBS_HasVIS3, // FNMULS = 449
6532
0
    CEFBS_HasVIS, // FNOR = 450
6533
0
    CEFBS_HasVIS, // FNORS = 451
6534
0
    CEFBS_HasVIS, // FNOT1 = 452
6535
0
    CEFBS_HasVIS, // FNOT1S = 453
6536
0
    CEFBS_HasVIS, // FNOT2 = 454
6537
0
    CEFBS_HasVIS, // FNOT2S = 455
6538
0
    CEFBS_HasVIS3, // FNSMULD = 456
6539
0
    CEFBS_HasVIS, // FONE = 457
6540
0
    CEFBS_HasVIS, // FONES = 458
6541
0
    CEFBS_HasVIS, // FOR = 459
6542
0
    CEFBS_HasVIS, // FORNOT1 = 460
6543
0
    CEFBS_HasVIS, // FORNOT1S = 461
6544
0
    CEFBS_HasVIS, // FORNOT2 = 462
6545
0
    CEFBS_HasVIS, // FORNOT2S = 463
6546
0
    CEFBS_HasVIS, // FORS = 464
6547
0
    CEFBS_HasVIS, // FPACK16 = 465
6548
0
    CEFBS_HasVIS, // FPACK32 = 466
6549
0
    CEFBS_HasVIS, // FPACKFIX = 467
6550
0
    CEFBS_HasVIS, // FPADD16 = 468
6551
0
    CEFBS_HasVIS, // FPADD16S = 469
6552
0
    CEFBS_HasVIS, // FPADD32 = 470
6553
0
    CEFBS_HasVIS, // FPADD32S = 471
6554
0
    CEFBS_HasVIS3, // FPADD64 = 472
6555
0
    CEFBS_HasVIS, // FPMERGE = 473
6556
0
    CEFBS_HasVIS, // FPSUB16 = 474
6557
0
    CEFBS_HasVIS, // FPSUB16S = 475
6558
0
    CEFBS_HasVIS, // FPSUB32 = 476
6559
0
    CEFBS_HasVIS, // FPSUB32S = 477
6560
0
    CEFBS_None, // FQTOD = 478
6561
0
    CEFBS_None, // FQTOI = 479
6562
0
    CEFBS_None, // FQTOS = 480
6563
0
    CEFBS_None, // FQTOX = 481
6564
0
    CEFBS_HasVIS3, // FSLAS16 = 482
6565
0
    CEFBS_HasVIS3, // FSLAS32 = 483
6566
0
    CEFBS_HasVIS3, // FSLL16 = 484
6567
0
    CEFBS_HasVIS3, // FSLL32 = 485
6568
0
    CEFBS_None, // FSMULD = 486
6569
0
    CEFBS_None, // FSQRTD = 487
6570
0
    CEFBS_None, // FSQRTQ = 488
6571
0
    CEFBS_None, // FSQRTS = 489
6572
0
    CEFBS_HasVIS3, // FSRA16 = 490
6573
0
    CEFBS_HasVIS3, // FSRA32 = 491
6574
0
    CEFBS_HasVIS, // FSRC1 = 492
6575
0
    CEFBS_HasVIS, // FSRC1S = 493
6576
0
    CEFBS_HasVIS, // FSRC2 = 494
6577
0
    CEFBS_HasVIS, // FSRC2S = 495
6578
0
    CEFBS_HasVIS3, // FSRL16 = 496
6579
0
    CEFBS_HasVIS3, // FSRL32 = 497
6580
0
    CEFBS_None, // FSTOD = 498
6581
0
    CEFBS_None, // FSTOI = 499
6582
0
    CEFBS_None, // FSTOQ = 500
6583
0
    CEFBS_None, // FSTOX = 501
6584
0
    CEFBS_None, // FSUBD = 502
6585
0
    CEFBS_None, // FSUBQ = 503
6586
0
    CEFBS_None, // FSUBS = 504
6587
0
    CEFBS_HasVIS, // FXNOR = 505
6588
0
    CEFBS_HasVIS, // FXNORS = 506
6589
0
    CEFBS_HasVIS, // FXOR = 507
6590
0
    CEFBS_HasVIS, // FXORS = 508
6591
0
    CEFBS_None, // FXTOD = 509
6592
0
    CEFBS_None, // FXTOQ = 510
6593
0
    CEFBS_None, // FXTOS = 511
6594
0
    CEFBS_HasVIS, // FZERO = 512
6595
0
    CEFBS_HasVIS, // FZEROS = 513
6596
0
    CEFBS_None, // GDOP_LDXrr = 514
6597
0
    CEFBS_None, // GDOP_LDrr = 515
6598
0
    CEFBS_None, // JMPLri = 516
6599
0
    CEFBS_None, // JMPLrr = 517
6600
0
    CEFBS_HasV9, // LDAri = 518
6601
0
    CEFBS_None, // LDArr = 519
6602
0
    CEFBS_None, // LDCSRri = 520
6603
0
    CEFBS_None, // LDCSRrr = 521
6604
0
    CEFBS_None, // LDCri = 522
6605
0
    CEFBS_None, // LDCrr = 523
6606
0
    CEFBS_HasV9, // LDDAri = 524
6607
0
    CEFBS_None, // LDDArr = 525
6608
0
    CEFBS_None, // LDDCri = 526
6609
0
    CEFBS_None, // LDDCrr = 527
6610
0
    CEFBS_HasV9, // LDDFAri = 528
6611
0
    CEFBS_HasV9, // LDDFArr = 529
6612
0
    CEFBS_None, // LDDFri = 530
6613
0
    CEFBS_None, // LDDFrr = 531
6614
0
    CEFBS_None, // LDDri = 532
6615
0
    CEFBS_None, // LDDrr = 533
6616
0
    CEFBS_HasV9, // LDFAri = 534
6617
0
    CEFBS_HasV9, // LDFArr = 535
6618
0
    CEFBS_None, // LDFSRri = 536
6619
0
    CEFBS_None, // LDFSRrr = 537
6620
0
    CEFBS_None, // LDFri = 538
6621
0
    CEFBS_None, // LDFrr = 539
6622
0
    CEFBS_HasV9, // LDQFAri = 540
6623
0
    CEFBS_HasV9, // LDQFArr = 541
6624
0
    CEFBS_HasV9, // LDQFri = 542
6625
0
    CEFBS_HasV9, // LDQFrr = 543
6626
0
    CEFBS_HasV9, // LDSBAri = 544
6627
0
    CEFBS_None, // LDSBArr = 545
6628
0
    CEFBS_None, // LDSBri = 546
6629
0
    CEFBS_None, // LDSBrr = 547
6630
0
    CEFBS_HasV9, // LDSHAri = 548
6631
0
    CEFBS_None, // LDSHArr = 549
6632
0
    CEFBS_None, // LDSHri = 550
6633
0
    CEFBS_None, // LDSHrr = 551
6634
0
    CEFBS_HasV9, // LDSTUBAri = 552
6635
0
    CEFBS_None, // LDSTUBArr = 553
6636
0
    CEFBS_None, // LDSTUBri = 554
6637
0
    CEFBS_None, // LDSTUBrr = 555
6638
0
    CEFBS_None, // LDSWAri = 556
6639
0
    CEFBS_None, // LDSWArr = 557
6640
0
    CEFBS_None, // LDSWri = 558
6641
0
    CEFBS_None, // LDSWrr = 559
6642
0
    CEFBS_HasV9, // LDUBAri = 560
6643
0
    CEFBS_None, // LDUBArr = 561
6644
0
    CEFBS_None, // LDUBri = 562
6645
0
    CEFBS_None, // LDUBrr = 563
6646
0
    CEFBS_HasV9, // LDUHAri = 564
6647
0
    CEFBS_None, // LDUHArr = 565
6648
0
    CEFBS_None, // LDUHri = 566
6649
0
    CEFBS_None, // LDUHrr = 567
6650
0
    CEFBS_None, // LDXAri = 568
6651
0
    CEFBS_None, // LDXArr = 569
6652
0
    CEFBS_HasV9, // LDXFSRri = 570
6653
0
    CEFBS_HasV9, // LDXFSRrr = 571
6654
0
    CEFBS_None, // LDXri = 572
6655
0
    CEFBS_None, // LDXrr = 573
6656
0
    CEFBS_None, // LDri = 574
6657
0
    CEFBS_None, // LDrr = 575
6658
0
    CEFBS_HasVIS3, // LZCNT = 576
6659
0
    CEFBS_HasV9, // MEMBARi = 577
6660
0
    CEFBS_HasVIS3, // MOVDTOX = 578
6661
0
    CEFBS_HasV9, // MOVFCCri = 579
6662
0
    CEFBS_HasV9, // MOVFCCrr = 580
6663
0
    CEFBS_HasV9, // MOVICCri = 581
6664
0
    CEFBS_HasV9, // MOVICCrr = 582
6665
0
    CEFBS_None, // MOVRri = 583
6666
0
    CEFBS_None, // MOVRrr = 584
6667
0
    CEFBS_HasVIS3, // MOVSTOSW = 585
6668
0
    CEFBS_HasVIS3, // MOVSTOUW = 586
6669
0
    CEFBS_HasVIS3, // MOVWTOS = 587
6670
0
    CEFBS_None, // MOVXCCri = 588
6671
0
    CEFBS_None, // MOVXCCrr = 589
6672
0
    CEFBS_HasVIS3, // MOVXTOD = 590
6673
0
    CEFBS_None, // MULSCCri = 591
6674
0
    CEFBS_None, // MULSCCrr = 592
6675
0
    CEFBS_None, // MULXri = 593
6676
0
    CEFBS_None, // MULXrr = 594
6677
0
    CEFBS_None, // NOP = 595
6678
0
    CEFBS_None, // ORCCri = 596
6679
0
    CEFBS_None, // ORCCrr = 597
6680
0
    CEFBS_None, // ORNCCri = 598
6681
0
    CEFBS_None, // ORNCCrr = 599
6682
0
    CEFBS_None, // ORNri = 600
6683
0
    CEFBS_None, // ORNrr = 601
6684
0
    CEFBS_None, // ORri = 602
6685
0
    CEFBS_None, // ORrr = 603
6686
0
    CEFBS_HasVIS, // PDIST = 604
6687
0
    CEFBS_HasVIS3, // PDISTN = 605
6688
0
    CEFBS_HasV9, // POPCrr = 606
6689
0
    CEFBS_HasV9, // PREFETCHi = 607
6690
0
    CEFBS_HasV9, // PREFETCHr = 608
6691
0
    CEFBS_HasPWRPSR, // PWRPSRri = 609
6692
0
    CEFBS_HasPWRPSR, // PWRPSRrr = 610
6693
0
    CEFBS_None, // RDASR = 611
6694
0
    CEFBS_HasV9, // RDFQ = 612
6695
0
    CEFBS_HasV9, // RDPR = 613
6696
0
    CEFBS_None, // RDPSR = 614
6697
0
    CEFBS_None, // RDTBR = 615
6698
0
    CEFBS_None, // RDWIM = 616
6699
0
    CEFBS_HasV9, // RESTORED = 617
6700
0
    CEFBS_None, // RESTOREri = 618
6701
0
    CEFBS_None, // RESTORErr = 619
6702
0
    CEFBS_None, // RET = 620
6703
0
    CEFBS_None, // RETL = 621
6704
0
    CEFBS_HasV9, // RETRY = 622
6705
0
    CEFBS_None, // RETTri = 623
6706
0
    CEFBS_None, // RETTrr = 624
6707
0
    CEFBS_HasV9, // SAVED = 625
6708
0
    CEFBS_None, // SAVEri = 626
6709
0
    CEFBS_None, // SAVErr = 627
6710
0
    CEFBS_None, // SDIVCCri = 628
6711
0
    CEFBS_None, // SDIVCCrr = 629
6712
0
    CEFBS_None, // SDIVXri = 630
6713
0
    CEFBS_None, // SDIVXrr = 631
6714
0
    CEFBS_None, // SDIVri = 632
6715
0
    CEFBS_None, // SDIVrr = 633
6716
0
    CEFBS_None, // SETHIi = 634
6717
0
    CEFBS_HasVIS, // SHUTDOWN = 635
6718
0
    CEFBS_HasVIS2, // SIAM = 636
6719
0
    CEFBS_HasV9, // SIR = 637
6720
0
    CEFBS_None, // SLLXri = 638
6721
0
    CEFBS_None, // SLLXrr = 639
6722
0
    CEFBS_None, // SLLri = 640
6723
0
    CEFBS_None, // SLLrr = 641
6724
0
    CEFBS_None, // SMACri = 642
6725
0
    CEFBS_None, // SMACrr = 643
6726
0
    CEFBS_None, // SMULCCri = 644
6727
0
    CEFBS_None, // SMULCCrr = 645
6728
0
    CEFBS_None, // SMULri = 646
6729
0
    CEFBS_None, // SMULrr = 647
6730
0
    CEFBS_None, // SRAXri = 648
6731
0
    CEFBS_None, // SRAXrr = 649
6732
0
    CEFBS_None, // SRAri = 650
6733
0
    CEFBS_None, // SRArr = 651
6734
0
    CEFBS_None, // SRLXri = 652
6735
0
    CEFBS_None, // SRLXrr = 653
6736
0
    CEFBS_None, // SRLri = 654
6737
0
    CEFBS_None, // SRLrr = 655
6738
0
    CEFBS_HasV9, // STAri = 656
6739
0
    CEFBS_None, // STArr = 657
6740
0
    CEFBS_None, // STBAR = 658
6741
0
    CEFBS_HasV9, // STBAri = 659
6742
0
    CEFBS_None, // STBArr = 660
6743
0
    CEFBS_None, // STBri = 661
6744
0
    CEFBS_None, // STBrr = 662
6745
0
    CEFBS_None, // STCSRri = 663
6746
0
    CEFBS_None, // STCSRrr = 664
6747
0
    CEFBS_None, // STCri = 665
6748
0
    CEFBS_None, // STCrr = 666
6749
0
    CEFBS_HasV9, // STDAri = 667
6750
0
    CEFBS_None, // STDArr = 668
6751
0
    CEFBS_None, // STDCQri = 669
6752
0
    CEFBS_None, // STDCQrr = 670
6753
0
    CEFBS_None, // STDCri = 671
6754
0
    CEFBS_None, // STDCrr = 672
6755
0
    CEFBS_HasV9, // STDFAri = 673
6756
0
    CEFBS_HasV9, // STDFArr = 674
6757
0
    CEFBS_None, // STDFQri = 675
6758
0
    CEFBS_None, // STDFQrr = 676
6759
0
    CEFBS_None, // STDFri = 677
6760
0
    CEFBS_None, // STDFrr = 678
6761
0
    CEFBS_None, // STDri = 679
6762
0
    CEFBS_None, // STDrr = 680
6763
0
    CEFBS_HasV9, // STFAri = 681
6764
0
    CEFBS_HasV9, // STFArr = 682
6765
0
    CEFBS_None, // STFSRri = 683
6766
0
    CEFBS_None, // STFSRrr = 684
6767
0
    CEFBS_None, // STFri = 685
6768
0
    CEFBS_None, // STFrr = 686
6769
0
    CEFBS_HasV9, // STHAri = 687
6770
0
    CEFBS_None, // STHArr = 688
6771
0
    CEFBS_None, // STHri = 689
6772
0
    CEFBS_None, // STHrr = 690
6773
0
    CEFBS_HasV9, // STQFAri = 691
6774
0
    CEFBS_HasV9, // STQFArr = 692
6775
0
    CEFBS_HasV9, // STQFri = 693
6776
0
    CEFBS_HasV9, // STQFrr = 694
6777
0
    CEFBS_None, // STXAri = 695
6778
0
    CEFBS_None, // STXArr = 696
6779
0
    CEFBS_HasV9, // STXFSRri = 697
6780
0
    CEFBS_HasV9, // STXFSRrr = 698
6781
0
    CEFBS_None, // STXri = 699
6782
0
    CEFBS_None, // STXrr = 700
6783
0
    CEFBS_None, // STri = 701
6784
0
    CEFBS_None, // STrr = 702
6785
0
    CEFBS_None, // SUBCCri = 703
6786
0
    CEFBS_None, // SUBCCrr = 704
6787
0
    CEFBS_None, // SUBCri = 705
6788
0
    CEFBS_None, // SUBCrr = 706
6789
0
    CEFBS_None, // SUBEri = 707
6790
0
    CEFBS_None, // SUBErr = 708
6791
0
    CEFBS_None, // SUBri = 709
6792
0
    CEFBS_None, // SUBrr = 710
6793
0
    CEFBS_HasV9, // SWAPAri = 711
6794
0
    CEFBS_None, // SWAPArr = 712
6795
0
    CEFBS_None, // SWAPri = 713
6796
0
    CEFBS_None, // SWAPrr = 714
6797
0
    CEFBS_None, // TA1 = 715
6798
0
    CEFBS_None, // TA3 = 716
6799
0
    CEFBS_None, // TA5 = 717
6800
0
    CEFBS_None, // TADDCCTVri = 718
6801
0
    CEFBS_None, // TADDCCTVrr = 719
6802
0
    CEFBS_None, // TADDCCri = 720
6803
0
    CEFBS_None, // TADDCCrr = 721
6804
0
    CEFBS_None, // TAIL_CALL = 722
6805
0
    CEFBS_None, // TAIL_CALLri = 723
6806
0
    CEFBS_HasV9, // TICCri = 724
6807
0
    CEFBS_HasV9, // TICCrr = 725
6808
0
    CEFBS_None, // TLS_ADDrr = 726
6809
0
    CEFBS_None, // TLS_CALL = 727
6810
0
    CEFBS_None, // TLS_LDXrr = 728
6811
0
    CEFBS_None, // TLS_LDrr = 729
6812
0
    CEFBS_None, // TRAPri = 730
6813
0
    CEFBS_None, // TRAPrr = 731
6814
0
    CEFBS_None, // TSUBCCTVri = 732
6815
0
    CEFBS_None, // TSUBCCTVrr = 733
6816
0
    CEFBS_None, // TSUBCCri = 734
6817
0
    CEFBS_None, // TSUBCCrr = 735
6818
0
    CEFBS_None, // TXCCri = 736
6819
0
    CEFBS_None, // TXCCrr = 737
6820
0
    CEFBS_None, // UDIVCCri = 738
6821
0
    CEFBS_None, // UDIVCCrr = 739
6822
0
    CEFBS_None, // UDIVXri = 740
6823
0
    CEFBS_None, // UDIVXrr = 741
6824
0
    CEFBS_None, // UDIVri = 742
6825
0
    CEFBS_None, // UDIVrr = 743
6826
0
    CEFBS_None, // UMACri = 744
6827
0
    CEFBS_None, // UMACrr = 745
6828
0
    CEFBS_None, // UMULCCri = 746
6829
0
    CEFBS_None, // UMULCCrr = 747
6830
0
    CEFBS_HasVIS3, // UMULXHI = 748
6831
0
    CEFBS_None, // UMULri = 749
6832
0
    CEFBS_None, // UMULrr = 750
6833
0
    CEFBS_None, // UNIMP = 751
6834
0
    CEFBS_None, // V9FCMPD = 752
6835
0
    CEFBS_None, // V9FCMPED = 753
6836
0
    CEFBS_None, // V9FCMPEQ = 754
6837
0
    CEFBS_None, // V9FCMPES = 755
6838
0
    CEFBS_None, // V9FCMPQ = 756
6839
0
    CEFBS_None, // V9FCMPS = 757
6840
0
    CEFBS_HasV9, // V9FMOVD_FCC = 758
6841
0
    CEFBS_HasV9, // V9FMOVQ_FCC = 759
6842
0
    CEFBS_HasV9, // V9FMOVS_FCC = 760
6843
0
    CEFBS_HasV9, // V9MOVFCCri = 761
6844
0
    CEFBS_HasV9, // V9MOVFCCrr = 762
6845
0
    CEFBS_None, // WRASRri = 763
6846
0
    CEFBS_None, // WRASRrr = 764
6847
0
    CEFBS_HasV9, // WRPRri = 765
6848
0
    CEFBS_HasV9, // WRPRrr = 766
6849
0
    CEFBS_None, // WRPSRri = 767
6850
0
    CEFBS_None, // WRPSRrr = 768
6851
0
    CEFBS_None, // WRTBRri = 769
6852
0
    CEFBS_None, // WRTBRrr = 770
6853
0
    CEFBS_None, // WRWIMri = 771
6854
0
    CEFBS_None, // WRWIMrr = 772
6855
0
    CEFBS_HasVIS3, // XMULX = 773
6856
0
    CEFBS_HasVIS3, // XMULXHI = 774
6857
0
    CEFBS_None, // XNORCCri = 775
6858
0
    CEFBS_None, // XNORCCrr = 776
6859
0
    CEFBS_None, // XNORri = 777
6860
0
    CEFBS_None, // XNORrr = 778
6861
0
    CEFBS_None, // XORCCri = 779
6862
0
    CEFBS_None, // XORCCrr = 780
6863
0
    CEFBS_None, // XORri = 781
6864
0
    CEFBS_None, // XORrr = 782
6865
0
  };
6866
6867
0
  assert(Opcode < 783);
6868
0
  return FeatureBitsets[RequiredFeaturesRefs[Opcode]];
6869
0
}
6870
6871
} // end namespace Sparc_MC
6872
} // end namespace llvm
6873
#endif // GET_COMPUTE_FEATURES
6874
6875
#ifdef GET_AVAILABLE_OPCODE_CHECKER
6876
#undef GET_AVAILABLE_OPCODE_CHECKER
6877
namespace llvm {
6878
namespace Sparc_MC {
6879
bool isOpcodeAvailable(unsigned Opcode, const FeatureBitset &Features) {
6880
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
6881
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
6882
  FeatureBitset MissingFeatures =
6883
      (AvailableFeatures & RequiredFeatures) ^
6884
      RequiredFeatures;
6885
  return !MissingFeatures.any();
6886
}
6887
} // end namespace Sparc_MC
6888
} // end namespace llvm
6889
#endif // GET_AVAILABLE_OPCODE_CHECKER
6890
6891
#ifdef ENABLE_INSTR_PREDICATE_VERIFIER
6892
#undef ENABLE_INSTR_PREDICATE_VERIFIER
6893
#include <sstream>
6894
6895
namespace llvm {
6896
namespace Sparc_MC {
6897
6898
#ifndef NDEBUG
6899
static const char *SubtargetFeatureNames[] = {
6900
  "Feature_HasCASA",
6901
  "Feature_HasPWRPSR",
6902
  "Feature_HasV9",
6903
  "Feature_HasVIS",
6904
  "Feature_HasVIS2",
6905
  "Feature_HasVIS3",
6906
  "Feature_UseSoftMulDiv",
6907
  nullptr
6908
};
6909
6910
#endif // NDEBUG
6911
6912
void verifyInstructionPredicates(
6913
0
    unsigned Opcode, const FeatureBitset &Features) {
6914
0
#ifndef NDEBUG
6915
0
  FeatureBitset AvailableFeatures = computeAvailableFeatures(Features);
6916
0
  FeatureBitset RequiredFeatures = computeRequiredFeatures(Opcode);
6917
0
  FeatureBitset MissingFeatures =
6918
0
      (AvailableFeatures & RequiredFeatures) ^
6919
0
      RequiredFeatures;
6920
0
  if (MissingFeatures.any()) {
6921
0
    std::ostringstream Msg;
6922
0
    Msg << "Attempting to emit " << &SparcInstrNameData[SparcInstrNameIndices[Opcode]]
6923
0
        << " instruction but the ";
6924
0
    for (unsigned i = 0, e = MissingFeatures.size(); i != e; ++i)
6925
0
      if (MissingFeatures.test(i))
6926
0
        Msg << SubtargetFeatureNames[i] << " ";
6927
0
    Msg << "predicate(s) are not met";
6928
0
    report_fatal_error(Msg.str().c_str());
6929
0
  }
6930
0
#endif // NDEBUG
6931
0
}
6932
} // end namespace Sparc_MC
6933
} // end namespace llvm
6934
#endif // ENABLE_INSTR_PREDICATE_VERIFIER
6935