/src/build/lib/Target/Sparc/SparcGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(0), |
297 | 0 | UINT64_C(0), |
298 | 0 | UINT64_C(0), |
299 | 0 | UINT64_C(0), |
300 | 0 | UINT64_C(0), |
301 | 0 | UINT64_C(2155880448), // ADDCCri |
302 | 0 | UINT64_C(2155872256), // ADDCCrr |
303 | 0 | UINT64_C(2151686144), // ADDCri |
304 | 0 | UINT64_C(2151677952), // ADDCrr |
305 | 0 | UINT64_C(2160074752), // ADDEri |
306 | 0 | UINT64_C(2160066560), // ADDErr |
307 | 0 | UINT64_C(2175795744), // ADDXC |
308 | 0 | UINT64_C(2175795808), // ADDXCCC |
309 | 0 | UINT64_C(2147491840), // ADDri |
310 | 0 | UINT64_C(2147483648), // ADDrr |
311 | 0 | UINT64_C(2175795968), // ALIGNADDR |
312 | 0 | UINT64_C(2175796032), // ALIGNADDRL |
313 | 0 | UINT64_C(2156404736), // ANDCCri |
314 | 0 | UINT64_C(2156396544), // ANDCCrr |
315 | 0 | UINT64_C(2158501888), // ANDNCCri |
316 | 0 | UINT64_C(2158493696), // ANDNCCrr |
317 | 0 | UINT64_C(2150113280), // ANDNri |
318 | 0 | UINT64_C(2150105088), // ANDNrr |
319 | 0 | UINT64_C(2148016128), // ANDri |
320 | 0 | UINT64_C(2148007936), // ANDrr |
321 | 0 | UINT64_C(2175795776), // ARRAY16 |
322 | 0 | UINT64_C(2175795840), // ARRAY32 |
323 | 0 | UINT64_C(2175795712), // ARRAY8 |
324 | 0 | UINT64_C(276824064), // BA |
325 | 0 | UINT64_C(8388608), // BCOND |
326 | 0 | UINT64_C(545259520), // BCONDA |
327 | 0 | UINT64_C(2176851968), // BINDri |
328 | 0 | UINT64_C(2176843776), // BINDrr |
329 | 0 | UINT64_C(2175796000), // BMASK |
330 | 0 | UINT64_C(21495808), // BPFCC |
331 | 0 | UINT64_C(558366720), // BPFCCA |
332 | 0 | UINT64_C(557842432), // BPFCCANT |
333 | 0 | UINT64_C(20971520), // BPFCCNT |
334 | 0 | UINT64_C(4718592), // BPICC |
335 | 0 | UINT64_C(541589504), // BPICCA |
336 | 0 | UINT64_C(541065216), // BPICCANT |
337 | 0 | UINT64_C(4194304), // BPICCNT |
338 | 0 | UINT64_C(13107200), // BPR |
339 | 0 | UINT64_C(549978112), // BPRA |
340 | 0 | UINT64_C(549453824), // BPRANT |
341 | 0 | UINT64_C(12582912), // BPRNT |
342 | 0 | UINT64_C(6815744), // BPXCC |
343 | 0 | UINT64_C(543686656), // BPXCCA |
344 | 0 | UINT64_C(543162368), // BPXCCANT |
345 | 0 | UINT64_C(6291456), // BPXCCNT |
346 | 0 | UINT64_C(2175796096), // BSHUFFLE |
347 | 0 | UINT64_C(1073741824), // CALL |
348 | 0 | UINT64_C(2680168448), // CALLri |
349 | 0 | UINT64_C(2680160256), // CALLrr |
350 | 0 | UINT64_C(3252690944), // CASAri |
351 | 0 | UINT64_C(3252682752), // CASArr |
352 | 0 | UINT64_C(3253739520), // CASXAri |
353 | 0 | UINT64_C(3253731328), // CASXArr |
354 | 0 | UINT64_C(29360128), // CBCOND |
355 | 0 | UINT64_C(566231040), // CBCONDA |
356 | 0 | UINT64_C(2175796128), // CMASK16 |
357 | 0 | UINT64_C(2175796192), // CMASK32 |
358 | 0 | UINT64_C(2175796064), // CMASK8 |
359 | 0 | UINT64_C(2179989504), // DONE |
360 | 0 | UINT64_C(2175795328), // EDGE16 |
361 | 0 | UINT64_C(2175795392), // EDGE16L |
362 | 0 | UINT64_C(2175795424), // EDGE16LN |
363 | 0 | UINT64_C(2175795360), // EDGE16N |
364 | 0 | UINT64_C(2175795456), // EDGE32 |
365 | 0 | UINT64_C(2175795520), // EDGE32L |
366 | 0 | UINT64_C(2175795552), // EDGE32LN |
367 | 0 | UINT64_C(2175795488), // EDGE32N |
368 | 0 | UINT64_C(2175795200), // EDGE8 |
369 | 0 | UINT64_C(2175795264), // EDGE8L |
370 | 0 | UINT64_C(2175795296), // EDGE8LN |
371 | 0 | UINT64_C(2175795232), // EDGE8N |
372 | 0 | UINT64_C(2174746944), // FABSD |
373 | 0 | UINT64_C(2174746976), // FABSQ |
374 | 0 | UINT64_C(2174746912), // FABSS |
375 | 0 | UINT64_C(2174748736), // FADDD |
376 | 0 | UINT64_C(2174748768), // FADDQ |
377 | 0 | UINT64_C(2174748704), // FADDS |
378 | 0 | UINT64_C(2175797504), // FALIGNADATA |
379 | 0 | UINT64_C(2175798784), // FAND |
380 | 0 | UINT64_C(2175798528), // FANDNOT1 |
381 | 0 | UINT64_C(2175798560), // FANDNOT1S |
382 | 0 | UINT64_C(2175798400), // FANDNOT2 |
383 | 0 | UINT64_C(2175798432), // FANDNOT2S |
384 | 0 | UINT64_C(2175798816), // FANDS |
385 | 0 | UINT64_C(25165824), // FBCOND |
386 | 0 | UINT64_C(562036736), // FBCONDA |
387 | 0 | UINT64_C(558366720), // FBCONDA_V9 |
388 | 0 | UINT64_C(21495808), // FBCOND_V9 |
389 | 0 | UINT64_C(2175797376), // FCHKSM16 |
390 | 0 | UINT64_C(2175273536), // FCMPD |
391 | 0 | UINT64_C(2175273536), // FCMPD_V9 |
392 | 0 | UINT64_C(2175796544), // FCMPEQ16 |
393 | 0 | UINT64_C(2175796672), // FCMPEQ32 |
394 | 0 | UINT64_C(2175796480), // FCMPGT16 |
395 | 0 | UINT64_C(2175796608), // FCMPGT32 |
396 | 0 | UINT64_C(2175796224), // FCMPLE16 |
397 | 0 | UINT64_C(2175796352), // FCMPLE32 |
398 | 0 | UINT64_C(2175796288), // FCMPNE16 |
399 | 0 | UINT64_C(2175796416), // FCMPNE32 |
400 | 0 | UINT64_C(2175273568), // FCMPQ |
401 | 0 | UINT64_C(2175273568), // FCMPQ_V9 |
402 | 0 | UINT64_C(2175273504), // FCMPS |
403 | 0 | UINT64_C(2175273504), // FCMPS_V9 |
404 | 0 | UINT64_C(2174749120), // FDIVD |
405 | 0 | UINT64_C(2174749152), // FDIVQ |
406 | 0 | UINT64_C(2174749088), // FDIVS |
407 | 0 | UINT64_C(2174750144), // FDMULQ |
408 | 0 | UINT64_C(2174753344), // FDTOI |
409 | 0 | UINT64_C(2174753216), // FDTOQ |
410 | 0 | UINT64_C(2174752960), // FDTOS |
411 | 0 | UINT64_C(2174750784), // FDTOX |
412 | 0 | UINT64_C(2175797664), // FEXPAND |
413 | 0 | UINT64_C(2174749760), // FHADDD |
414 | 0 | UINT64_C(2174749728), // FHADDS |
415 | 0 | UINT64_C(2174749888), // FHSUBD |
416 | 0 | UINT64_C(2174749856), // FHSUBS |
417 | 0 | UINT64_C(2174753024), // FITOD |
418 | 0 | UINT64_C(2174753152), // FITOQ |
419 | 0 | UINT64_C(2174752896), // FITOS |
420 | 0 | UINT64_C(2175806016), // FLCMPD |
421 | 0 | UINT64_C(2175805984), // FLCMPS |
422 | 0 | UINT64_C(2178416640), // FLUSH |
423 | 0 | UINT64_C(2170028032), // FLUSHW |
424 | 0 | UINT64_C(2178424832), // FLUSHri |
425 | 0 | UINT64_C(2178416640), // FLUSHrr |
426 | 0 | UINT64_C(2175797248), // FMEAN16 |
427 | 0 | UINT64_C(2174746688), // FMOVD |
428 | 0 | UINT64_C(2175270976), // FMOVD_FCC |
429 | 0 | UINT64_C(2175279168), // FMOVD_ICC |
430 | 0 | UINT64_C(2175283264), // FMOVD_XCC |
431 | 0 | UINT64_C(2174746720), // FMOVQ |
432 | 0 | UINT64_C(2175271008), // FMOVQ_FCC |
433 | 0 | UINT64_C(2175279200), // FMOVQ_ICC |
434 | 0 | UINT64_C(2175283296), // FMOVQ_XCC |
435 | 0 | UINT64_C(2175271104), // FMOVRD |
436 | 0 | UINT64_C(2175271136), // FMOVRQ |
437 | 0 | UINT64_C(2175271072), // FMOVRS |
438 | 0 | UINT64_C(2174746656), // FMOVS |
439 | 0 | UINT64_C(2175270944), // FMOVS_FCC |
440 | 0 | UINT64_C(2175279136), // FMOVS_ICC |
441 | 0 | UINT64_C(2175283232), // FMOVS_XCC |
442 | 0 | UINT64_C(2175796928), // FMUL8SUX16 |
443 | 0 | UINT64_C(2175796960), // FMUL8ULX16 |
444 | 0 | UINT64_C(2175796768), // FMUL8X16 |
445 | 0 | UINT64_C(2175796896), // FMUL8X16AL |
446 | 0 | UINT64_C(2175796832), // FMUL8X16AU |
447 | 0 | UINT64_C(2174748992), // FMULD |
448 | 0 | UINT64_C(2175796992), // FMULD8SUX16 |
449 | 0 | UINT64_C(2175797024), // FMULD8ULX16 |
450 | 0 | UINT64_C(2174749024), // FMULQ |
451 | 0 | UINT64_C(2174748960), // FMULS |
452 | 0 | UINT64_C(2174749248), // FNADDD |
453 | 0 | UINT64_C(2174749216), // FNADDS |
454 | 0 | UINT64_C(2175798720), // FNAND |
455 | 0 | UINT64_C(2175798752), // FNANDS |
456 | 0 | UINT64_C(2174746816), // FNEGD |
457 | 0 | UINT64_C(2174746848), // FNEGQ |
458 | 0 | UINT64_C(2174746784), // FNEGS |
459 | 0 | UINT64_C(2174750272), // FNHADDD |
460 | 0 | UINT64_C(2174750240), // FNHADDS |
461 | 0 | UINT64_C(2174749504), // FNMULD |
462 | 0 | UINT64_C(2174749472), // FNMULS |
463 | 0 | UINT64_C(2175798336), // FNOR |
464 | 0 | UINT64_C(2175798368), // FNORS |
465 | 0 | UINT64_C(2175798592), // FNOT1 |
466 | 0 | UINT64_C(2175798624), // FNOT1S |
467 | 0 | UINT64_C(2175798464), // FNOT2 |
468 | 0 | UINT64_C(2175798496), // FNOT2S |
469 | 0 | UINT64_C(2174750496), // FNSMULD |
470 | 0 | UINT64_C(2175799232), // FONE |
471 | 0 | UINT64_C(2175799264), // FONES |
472 | 0 | UINT64_C(2175799168), // FOR |
473 | 0 | UINT64_C(2175799104), // FORNOT1 |
474 | 0 | UINT64_C(2175799136), // FORNOT1S |
475 | 0 | UINT64_C(2175798976), // FORNOT2 |
476 | 0 | UINT64_C(2175799008), // FORNOT2S |
477 | 0 | UINT64_C(2175799200), // FORS |
478 | 0 | UINT64_C(2175797088), // FPACK16 |
479 | 0 | UINT64_C(2175797056), // FPACK32 |
480 | 0 | UINT64_C(2175797152), // FPACKFIX |
481 | 0 | UINT64_C(2175797760), // FPADD16 |
482 | 0 | UINT64_C(2175797792), // FPADD16S |
483 | 0 | UINT64_C(2175797824), // FPADD32 |
484 | 0 | UINT64_C(2175797856), // FPADD32S |
485 | 0 | UINT64_C(2175797312), // FPADD64 |
486 | 0 | UINT64_C(2175797600), // FPMERGE |
487 | 0 | UINT64_C(2175797888), // FPSUB16 |
488 | 0 | UINT64_C(2175797920), // FPSUB16S |
489 | 0 | UINT64_C(2175797952), // FPSUB32 |
490 | 0 | UINT64_C(2175797984), // FPSUB32S |
491 | 0 | UINT64_C(2174753120), // FQTOD |
492 | 0 | UINT64_C(2174753376), // FQTOI |
493 | 0 | UINT64_C(2174752992), // FQTOS |
494 | 0 | UINT64_C(2174750816), // FQTOX |
495 | 0 | UINT64_C(2175796512), // FSLAS16 |
496 | 0 | UINT64_C(2175796640), // FSLAS32 |
497 | 0 | UINT64_C(2175796256), // FSLL16 |
498 | 0 | UINT64_C(2175796384), // FSLL32 |
499 | 0 | UINT64_C(2174749984), // FSMULD |
500 | 0 | UINT64_C(2174747968), // FSQRTD |
501 | 0 | UINT64_C(2174748000), // FSQRTQ |
502 | 0 | UINT64_C(2174747936), // FSQRTS |
503 | 0 | UINT64_C(2175796576), // FSRA16 |
504 | 0 | UINT64_C(2175796704), // FSRA32 |
505 | 0 | UINT64_C(2175798912), // FSRC1 |
506 | 0 | UINT64_C(2175798944), // FSRC1S |
507 | 0 | UINT64_C(2175799040), // FSRC2 |
508 | 0 | UINT64_C(2175799072), // FSRC2S |
509 | 0 | UINT64_C(2175796320), // FSRL16 |
510 | 0 | UINT64_C(2175796448), // FSRL32 |
511 | 0 | UINT64_C(2174753056), // FSTOD |
512 | 0 | UINT64_C(2174753312), // FSTOI |
513 | 0 | UINT64_C(2174753184), // FSTOQ |
514 | 0 | UINT64_C(2174750752), // FSTOX |
515 | 0 | UINT64_C(2174748864), // FSUBD |
516 | 0 | UINT64_C(2174748896), // FSUBQ |
517 | 0 | UINT64_C(2174748832), // FSUBS |
518 | 0 | UINT64_C(2175798848), // FXNOR |
519 | 0 | UINT64_C(2175798880), // FXNORS |
520 | 0 | UINT64_C(2175798656), // FXOR |
521 | 0 | UINT64_C(2175798688), // FXORS |
522 | 0 | UINT64_C(2174750976), // FXTOD |
523 | 0 | UINT64_C(2174751104), // FXTOQ |
524 | 0 | UINT64_C(2174750848), // FXTOS |
525 | 0 | UINT64_C(2175798272), // FZERO |
526 | 0 | UINT64_C(2175798304), // FZEROS |
527 | 0 | UINT64_C(3226992640), // GDOP_LDXrr |
528 | 0 | UINT64_C(3221225472), // GDOP_LDrr |
529 | 0 | UINT64_C(2176851968), // JMPLri |
530 | 0 | UINT64_C(2176843776), // JMPLrr |
531 | 0 | UINT64_C(3229622272), // LDAri |
532 | 0 | UINT64_C(3229614080), // LDArr |
533 | 0 | UINT64_C(3246923776), // LDCSRri |
534 | 0 | UINT64_C(3246915584), // LDCSRrr |
535 | 0 | UINT64_C(3246399488), // LDCri |
536 | 0 | UINT64_C(3246391296), // LDCrr |
537 | 0 | UINT64_C(3231195136), // LDDAri |
538 | 0 | UINT64_C(3231186944), // LDDArr |
539 | 0 | UINT64_C(3247972352), // LDDCri |
540 | 0 | UINT64_C(3247964160), // LDDCrr |
541 | 0 | UINT64_C(3247972352), // LDDFAri |
542 | 0 | UINT64_C(3247964160), // LDDFArr |
543 | 0 | UINT64_C(3239583744), // LDDFri |
544 | 0 | UINT64_C(3239575552), // LDDFrr |
545 | 0 | UINT64_C(3222806528), // LDDri |
546 | 0 | UINT64_C(3222798336), // LDDrr |
547 | 0 | UINT64_C(3246399488), // LDFAri |
548 | 0 | UINT64_C(3246391296), // LDFArr |
549 | 0 | UINT64_C(3238535168), // LDFSRri |
550 | 0 | UINT64_C(3238526976), // LDFSRrr |
551 | 0 | UINT64_C(3238010880), // LDFri |
552 | 0 | UINT64_C(3238002688), // LDFrr |
553 | 0 | UINT64_C(3247448064), // LDQFAri |
554 | 0 | UINT64_C(3247439872), // LDQFArr |
555 | 0 | UINT64_C(3239059456), // LDQFri |
556 | 0 | UINT64_C(3239051264), // LDQFrr |
557 | 0 | UINT64_C(3234340864), // LDSBAri |
558 | 0 | UINT64_C(3234332672), // LDSBArr |
559 | 0 | UINT64_C(3225952256), // LDSBri |
560 | 0 | UINT64_C(3225944064), // LDSBrr |
561 | 0 | UINT64_C(3234865152), // LDSHAri |
562 | 0 | UINT64_C(3234856960), // LDSHArr |
563 | 0 | UINT64_C(3226476544), // LDSHri |
564 | 0 | UINT64_C(3226468352), // LDSHrr |
565 | 0 | UINT64_C(3236438016), // LDSTUBAri |
566 | 0 | UINT64_C(3236429824), // LDSTUBArr |
567 | 0 | UINT64_C(3228049408), // LDSTUBri |
568 | 0 | UINT64_C(3228041216), // LDSTUBrr |
569 | 0 | UINT64_C(3233816576), // LDSWAri |
570 | 0 | UINT64_C(3233808384), // LDSWArr |
571 | 0 | UINT64_C(3225427968), // LDSWri |
572 | 0 | UINT64_C(3225419776), // LDSWrr |
573 | 0 | UINT64_C(3230146560), // LDUBAri |
574 | 0 | UINT64_C(3230138368), // LDUBArr |
575 | 0 | UINT64_C(3221757952), // LDUBri |
576 | 0 | UINT64_C(3221749760), // LDUBrr |
577 | 0 | UINT64_C(3230670848), // LDUHAri |
578 | 0 | UINT64_C(3230662656), // LDUHArr |
579 | 0 | UINT64_C(3222282240), // LDUHri |
580 | 0 | UINT64_C(3222274048), // LDUHrr |
581 | 0 | UINT64_C(3235389440), // LDXAri |
582 | 0 | UINT64_C(3235381248), // LDXArr |
583 | 0 | UINT64_C(3272089600), // LDXFSRri |
584 | 0 | UINT64_C(3272081408), // LDXFSRrr |
585 | 0 | UINT64_C(3227000832), // LDXri |
586 | 0 | UINT64_C(3226992640), // LDXrr |
587 | 0 | UINT64_C(3221233664), // LDri |
588 | 0 | UINT64_C(3221225472), // LDrr |
589 | 0 | UINT64_C(2175795936), // LZCNT |
590 | 0 | UINT64_C(2168709120), // MEMBARi |
591 | 0 | UINT64_C(2175803904), // MOVDTOX |
592 | 0 | UINT64_C(2170560512), // MOVFCCri |
593 | 0 | UINT64_C(2170552320), // MOVFCCrr |
594 | 0 | UINT64_C(2170822656), // MOVICCri |
595 | 0 | UINT64_C(2170814464), // MOVICCrr |
596 | 0 | UINT64_C(2172133376), // MOVRri |
597 | 0 | UINT64_C(2172125184), // MOVRrr |
598 | 0 | UINT64_C(2175804000), // MOVSTOSW |
599 | 0 | UINT64_C(2175803936), // MOVSTOUW |
600 | 0 | UINT64_C(2175804192), // MOVWTOS |
601 | 0 | UINT64_C(2170826752), // MOVXCCri |
602 | 0 | UINT64_C(2170818560), // MOVXCCrr |
603 | 0 | UINT64_C(2175804160), // MOVXTOD |
604 | 0 | UINT64_C(2166366208), // MULSCCri |
605 | 0 | UINT64_C(2166358016), // MULSCCrr |
606 | 0 | UINT64_C(2152210432), // MULXri |
607 | 0 | UINT64_C(2152202240), // MULXrr |
608 | 0 | UINT64_C(16777216), // NOP |
609 | 0 | UINT64_C(2156929024), // ORCCri |
610 | 0 | UINT64_C(2156920832), // ORCCrr |
611 | 0 | UINT64_C(2159026176), // ORNCCri |
612 | 0 | UINT64_C(2159017984), // ORNCCrr |
613 | 0 | UINT64_C(2150637568), // ORNri |
614 | 0 | UINT64_C(2150629376), // ORNrr |
615 | 0 | UINT64_C(2148540416), // ORri |
616 | 0 | UINT64_C(2148532224), // ORrr |
617 | 0 | UINT64_C(2175797184), // PDIST |
618 | 0 | UINT64_C(2175797216), // PDISTN |
619 | 0 | UINT64_C(2171600896), // POPCrr |
620 | 0 | UINT64_C(3244826624), // PREFETCHi |
621 | 0 | UINT64_C(3244818432), // PREFETCHr |
622 | 0 | UINT64_C(2206736384), // PWRPSRri |
623 | 0 | UINT64_C(2206728192), // PWRPSRrr |
624 | 0 | UINT64_C(2168455168), // RDASR |
625 | 0 | UINT64_C(2169749504), // RDFQ |
626 | 0 | UINT64_C(2169503744), // RDPR |
627 | 0 | UINT64_C(2168979456), // RDPSR |
628 | 0 | UINT64_C(2170028032), // RDTBR |
629 | 0 | UINT64_C(2169503744), // RDWIM |
630 | 0 | UINT64_C(2206728192), // RESTORED |
631 | 0 | UINT64_C(2179473408), // RESTOREri |
632 | 0 | UINT64_C(2179465216), // RESTORErr |
633 | 0 | UINT64_C(2177359872), // RET |
634 | 0 | UINT64_C(2177097728), // RETL |
635 | 0 | UINT64_C(2213543936), // RETRY |
636 | 0 | UINT64_C(2177376256), // RETTri |
637 | 0 | UINT64_C(2177368064), // RETTrr |
638 | 0 | UINT64_C(2173173760), // SAVED |
639 | 0 | UINT64_C(2178949120), // SAVEri |
640 | 0 | UINT64_C(2178940928), // SAVErr |
641 | 0 | UINT64_C(2163744768), // SDIVCCri |
642 | 0 | UINT64_C(2163736576), // SDIVCCrr |
643 | 0 | UINT64_C(2171084800), // SDIVXri |
644 | 0 | UINT64_C(2171076608), // SDIVXrr |
645 | 0 | UINT64_C(2155356160), // SDIVri |
646 | 0 | UINT64_C(2155347968), // SDIVrr |
647 | 0 | UINT64_C(16777216), // SETHIi |
648 | 0 | UINT64_C(2175799296), // SHUTDOWN |
649 | 0 | UINT64_C(2175799328), // SIAM |
650 | 0 | UINT64_C(2675974144), // SIR |
651 | 0 | UINT64_C(2166894592), // SLLXri |
652 | 0 | UINT64_C(2166886400), // SLLXrr |
653 | 0 | UINT64_C(2166890496), // SLLri |
654 | 0 | UINT64_C(2166882304), // SLLrr |
655 | 0 | UINT64_C(2180521984), // SMACri |
656 | 0 | UINT64_C(2180513792), // SMACrr |
657 | 0 | UINT64_C(2161647616), // SMULCCri |
658 | 0 | UINT64_C(2161639424), // SMULCCrr |
659 | 0 | UINT64_C(2153259008), // SMULri |
660 | 0 | UINT64_C(2153250816), // SMULrr |
661 | 0 | UINT64_C(2167943168), // SRAXri |
662 | 0 | UINT64_C(2167934976), // SRAXrr |
663 | 0 | UINT64_C(2167939072), // SRAri |
664 | 0 | UINT64_C(2167930880), // SRArr |
665 | 0 | UINT64_C(2167418880), // SRLXri |
666 | 0 | UINT64_C(2167410688), // SRLXrr |
667 | 0 | UINT64_C(2167414784), // SRLri |
668 | 0 | UINT64_C(2167406592), // SRLrr |
669 | 0 | UINT64_C(3231719424), // STAri |
670 | 0 | UINT64_C(3231711232), // STArr |
671 | 0 | UINT64_C(2168700928), // STBAR |
672 | 0 | UINT64_C(3232243712), // STBAri |
673 | 0 | UINT64_C(3232235520), // STBArr |
674 | 0 | UINT64_C(3223855104), // STBri |
675 | 0 | UINT64_C(3223846912), // STBrr |
676 | 0 | UINT64_C(3249020928), // STCSRri |
677 | 0 | UINT64_C(3249012736), // STCSRrr |
678 | 0 | UINT64_C(3248496640), // STCri |
679 | 0 | UINT64_C(3248488448), // STCrr |
680 | 0 | UINT64_C(3233292288), // STDAri |
681 | 0 | UINT64_C(3233284096), // STDArr |
682 | 0 | UINT64_C(3249545216), // STDCQri |
683 | 0 | UINT64_C(3249537024), // STDCQrr |
684 | 0 | UINT64_C(3250069504), // STDCri |
685 | 0 | UINT64_C(3250061312), // STDCrr |
686 | 0 | UINT64_C(3250069504), // STDFAri |
687 | 0 | UINT64_C(3250061312), // STDFArr |
688 | 0 | UINT64_C(3241156608), // STDFQri |
689 | 0 | UINT64_C(3241148416), // STDFQrr |
690 | 0 | UINT64_C(3241680896), // STDFri |
691 | 0 | UINT64_C(3241672704), // STDFrr |
692 | 0 | UINT64_C(3224903680), // STDri |
693 | 0 | UINT64_C(3224895488), // STDrr |
694 | 0 | UINT64_C(3248496640), // STFAri |
695 | 0 | UINT64_C(3248488448), // STFArr |
696 | 0 | UINT64_C(3240632320), // STFSRri |
697 | 0 | UINT64_C(3240624128), // STFSRrr |
698 | 0 | UINT64_C(3240108032), // STFri |
699 | 0 | UINT64_C(3240099840), // STFrr |
700 | 0 | UINT64_C(3232768000), // STHAri |
701 | 0 | UINT64_C(3232759808), // STHArr |
702 | 0 | UINT64_C(3224379392), // STHri |
703 | 0 | UINT64_C(3224371200), // STHrr |
704 | 0 | UINT64_C(3249545216), // STQFAri |
705 | 0 | UINT64_C(3249537024), // STQFArr |
706 | 0 | UINT64_C(3241156608), // STQFri |
707 | 0 | UINT64_C(3241148416), // STQFrr |
708 | 0 | UINT64_C(3236962304), // STXAri |
709 | 0 | UINT64_C(3236954112), // STXArr |
710 | 0 | UINT64_C(3274186752), // STXFSRri |
711 | 0 | UINT64_C(3274178560), // STXFSRrr |
712 | 0 | UINT64_C(3228573696), // STXri |
713 | 0 | UINT64_C(3228565504), // STXrr |
714 | 0 | UINT64_C(3223330816), // STri |
715 | 0 | UINT64_C(3223322624), // STrr |
716 | 0 | UINT64_C(2157977600), // SUBCCri |
717 | 0 | UINT64_C(2157969408), // SUBCCrr |
718 | 0 | UINT64_C(2153783296), // SUBCri |
719 | 0 | UINT64_C(2153775104), // SUBCrr |
720 | 0 | UINT64_C(2162171904), // SUBEri |
721 | 0 | UINT64_C(2162163712), // SUBErr |
722 | 0 | UINT64_C(2149588992), // SUBri |
723 | 0 | UINT64_C(2149580800), // SUBrr |
724 | 0 | UINT64_C(3237486592), // SWAPAri |
725 | 0 | UINT64_C(3237478400), // SWAPArr |
726 | 0 | UINT64_C(3229097984), // SWAPri |
727 | 0 | UINT64_C(3229089792), // SWAPrr |
728 | 0 | UINT64_C(2446336001), // TA1 |
729 | 0 | UINT64_C(2446336003), // TA3 |
730 | 0 | UINT64_C(2446336005), // TA5 |
731 | 0 | UINT64_C(2165317632), // TADDCCTVri |
732 | 0 | UINT64_C(2165309440), // TADDCCTVrr |
733 | 0 | UINT64_C(2164269056), // TADDCCri |
734 | 0 | UINT64_C(2164260864), // TADDCCrr |
735 | 0 | UINT64_C(1073741824), // TAIL_CALL |
736 | 0 | UINT64_C(2176851968), // TAIL_CALLri |
737 | 0 | UINT64_C(2177900544), // TICCri |
738 | 0 | UINT64_C(2177892352), // TICCrr |
739 | 0 | UINT64_C(2147483648), // TLS_ADDrr |
740 | 0 | UINT64_C(1073741824), // TLS_CALL |
741 | 0 | UINT64_C(3226992640), // TLS_LDXrr |
742 | 0 | UINT64_C(3221225472), // TLS_LDrr |
743 | 0 | UINT64_C(2177900544), // TRAPri |
744 | 0 | UINT64_C(2177892352), // TRAPrr |
745 | 0 | UINT64_C(2165841920), // TSUBCCTVri |
746 | 0 | UINT64_C(2165833728), // TSUBCCTVrr |
747 | 0 | UINT64_C(2164793344), // TSUBCCri |
748 | 0 | UINT64_C(2164785152), // TSUBCCrr |
749 | 0 | UINT64_C(2177904640), // TXCCri |
750 | 0 | UINT64_C(2177896448), // TXCCrr |
751 | 0 | UINT64_C(2163220480), // UDIVCCri |
752 | 0 | UINT64_C(2163212288), // UDIVCCrr |
753 | 0 | UINT64_C(2154307584), // UDIVXri |
754 | 0 | UINT64_C(2154299392), // UDIVXrr |
755 | 0 | UINT64_C(2154831872), // UDIVri |
756 | 0 | UINT64_C(2154823680), // UDIVrr |
757 | 0 | UINT64_C(2179997696), // UMACri |
758 | 0 | UINT64_C(2179989504), // UMACrr |
759 | 0 | UINT64_C(2161123328), // UMULCCri |
760 | 0 | UINT64_C(2161115136), // UMULCCrr |
761 | 0 | UINT64_C(2175795904), // UMULXHI |
762 | 0 | UINT64_C(2152734720), // UMULri |
763 | 0 | UINT64_C(2152726528), // UMULrr |
764 | 0 | UINT64_C(0), // UNIMP |
765 | 0 | UINT64_C(2175273536), // V9FCMPD |
766 | 0 | UINT64_C(2175273664), // V9FCMPED |
767 | 0 | UINT64_C(2175273696), // V9FCMPEQ |
768 | 0 | UINT64_C(2175273632), // V9FCMPES |
769 | 0 | UINT64_C(2175273568), // V9FCMPQ |
770 | 0 | UINT64_C(2175273504), // V9FCMPS |
771 | 0 | UINT64_C(2175270976), // V9FMOVD_FCC |
772 | 0 | UINT64_C(2175271008), // V9FMOVQ_FCC |
773 | 0 | UINT64_C(2175270944), // V9FMOVS_FCC |
774 | 0 | UINT64_C(2170560512), // V9MOVFCCri |
775 | 0 | UINT64_C(2170552320), // V9MOVFCCrr |
776 | 0 | UINT64_C(2172657664), // WRASRri |
777 | 0 | UINT64_C(2172649472), // WRASRrr |
778 | 0 | UINT64_C(2173706240), // WRPRri |
779 | 0 | UINT64_C(2173698048), // WRPRrr |
780 | 0 | UINT64_C(2173181952), // WRPSRri |
781 | 0 | UINT64_C(2173173760), // WRPSRrr |
782 | 0 | UINT64_C(2174230528), // WRTBRri |
783 | 0 | UINT64_C(2174222336), // WRTBRrr |
784 | 0 | UINT64_C(2173706240), // WRWIMri |
785 | 0 | UINT64_C(2173698048), // WRWIMrr |
786 | 0 | UINT64_C(2175804064), // XMULX |
787 | 0 | UINT64_C(2175804128), // XMULXHI |
788 | 0 | UINT64_C(2159550464), // XNORCCri |
789 | 0 | UINT64_C(2159542272), // XNORCCrr |
790 | 0 | UINT64_C(2151161856), // XNORri |
791 | 0 | UINT64_C(2151153664), // XNORrr |
792 | 0 | UINT64_C(2157453312), // XORCCri |
793 | 0 | UINT64_C(2157445120), // XORCCrr |
794 | 0 | UINT64_C(2149064704), // XORri |
795 | 0 | UINT64_C(2149056512), // XORrr |
796 | 0 | UINT64_C(0) |
797 | 0 | }; |
798 | 0 | const unsigned opcode = MI.getOpcode(); |
799 | 0 | uint64_t Value = InstBits[opcode]; |
800 | 0 | uint64_t op = 0; |
801 | 0 | (void)op; // suppress warning |
802 | 0 | switch (opcode) { |
803 | 0 | case SP::DONE: |
804 | 0 | case SP::FLUSH: |
805 | 0 | case SP::FLUSHW: |
806 | 0 | case SP::NOP: |
807 | 0 | case SP::RESTORED: |
808 | 0 | case SP::RETRY: |
809 | 0 | case SP::SAVED: |
810 | 0 | case SP::SHUTDOWN: |
811 | 0 | case SP::SIAM: |
812 | 0 | case SP::STBAR: |
813 | 0 | case SP::TA1: |
814 | 0 | case SP::TA3: |
815 | 0 | case SP::TA5: { |
816 | 0 | break; |
817 | 0 | } |
818 | 0 | case SP::BPFCC: |
819 | 0 | case SP::BPFCCA: |
820 | 0 | case SP::BPFCCANT: |
821 | 0 | case SP::BPFCCNT: { |
822 | | // op: cc |
823 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
824 | 0 | op &= UINT64_C(3); |
825 | 0 | op <<= 20; |
826 | 0 | Value |= op; |
827 | | // op: cond |
828 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
829 | 0 | op &= UINT64_C(15); |
830 | 0 | op <<= 25; |
831 | 0 | Value |= op; |
832 | | // op: imm19 |
833 | 0 | op = getBranchPredTargetOpValue(MI, 0, Fixups, STI); |
834 | 0 | op &= UINT64_C(524287); |
835 | 0 | Value |= op; |
836 | 0 | break; |
837 | 0 | } |
838 | 0 | case SP::BPICC: |
839 | 0 | case SP::BPICCA: |
840 | 0 | case SP::BPICCANT: |
841 | 0 | case SP::BPICCNT: |
842 | 0 | case SP::BPXCC: |
843 | 0 | case SP::BPXCCA: |
844 | 0 | case SP::BPXCCANT: |
845 | 0 | case SP::BPXCCNT: |
846 | 0 | case SP::FBCONDA_V9: |
847 | 0 | case SP::FBCOND_V9: { |
848 | | // op: cond |
849 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
850 | 0 | op &= UINT64_C(15); |
851 | 0 | op <<= 25; |
852 | 0 | Value |= op; |
853 | | // op: imm19 |
854 | 0 | op = getBranchPredTargetOpValue(MI, 0, Fixups, STI); |
855 | 0 | op &= UINT64_C(524287); |
856 | 0 | Value |= op; |
857 | 0 | break; |
858 | 0 | } |
859 | 0 | case SP::CALL: |
860 | 0 | case SP::TAIL_CALL: |
861 | 0 | case SP::TLS_CALL: { |
862 | | // op: disp |
863 | 0 | op = getCallTargetOpValue(MI, 0, Fixups, STI); |
864 | 0 | op &= UINT64_C(1073741823); |
865 | 0 | Value |= op; |
866 | 0 | break; |
867 | 0 | } |
868 | 0 | case SP::BPR: |
869 | 0 | case SP::BPRA: |
870 | 0 | case SP::BPRANT: |
871 | 0 | case SP::BPRNT: { |
872 | | // op: imm16 |
873 | 0 | op = getBranchOnRegTargetOpValue(MI, 0, Fixups, STI); |
874 | 0 | Value |= (op & UINT64_C(49152)) << 6; |
875 | 0 | Value |= (op & UINT64_C(16383)); |
876 | | // op: rs1 |
877 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
878 | 0 | op &= UINT64_C(31); |
879 | 0 | op <<= 14; |
880 | 0 | Value |= op; |
881 | | // op: rcond |
882 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
883 | 0 | op &= UINT64_C(7); |
884 | 0 | op <<= 25; |
885 | 0 | Value |= op; |
886 | 0 | break; |
887 | 0 | } |
888 | 0 | case SP::BA: { |
889 | | // op: imm22 |
890 | 0 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
891 | 0 | op &= UINT64_C(4194303); |
892 | 0 | Value |= op; |
893 | 0 | break; |
894 | 0 | } |
895 | 0 | case SP::BCOND: |
896 | 0 | case SP::BCONDA: |
897 | 0 | case SP::CBCOND: |
898 | 0 | case SP::CBCONDA: |
899 | 0 | case SP::FBCOND: |
900 | 0 | case SP::FBCONDA: { |
901 | | // op: imm22 |
902 | 0 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
903 | 0 | op &= UINT64_C(4194303); |
904 | 0 | Value |= op; |
905 | | // op: cond |
906 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
907 | 0 | op &= UINT64_C(15); |
908 | 0 | op <<= 25; |
909 | 0 | Value |= op; |
910 | 0 | break; |
911 | 0 | } |
912 | 0 | case SP::UNIMP: { |
913 | | // op: imm22 |
914 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
915 | 0 | op &= UINT64_C(4194303); |
916 | 0 | Value |= op; |
917 | 0 | break; |
918 | 0 | } |
919 | 0 | case SP::SETHIi: { |
920 | | // op: imm22 |
921 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
922 | 0 | op &= UINT64_C(4194303); |
923 | 0 | Value |= op; |
924 | | // op: rd |
925 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
926 | 0 | op &= UINT64_C(31); |
927 | 0 | op <<= 25; |
928 | 0 | Value |= op; |
929 | 0 | break; |
930 | 0 | } |
931 | 0 | case SP::FONE: |
932 | 0 | case SP::FONES: |
933 | 0 | case SP::FZERO: |
934 | 0 | case SP::FZEROS: |
935 | 0 | case SP::RDFQ: |
936 | 0 | case SP::RDPSR: |
937 | 0 | case SP::RDTBR: |
938 | 0 | case SP::RDWIM: { |
939 | | // op: rd |
940 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
941 | 0 | op &= UINT64_C(31); |
942 | 0 | op <<= 25; |
943 | 0 | Value |= op; |
944 | 0 | break; |
945 | 0 | } |
946 | 0 | case SP::V9MOVFCCrr: { |
947 | | // op: rd |
948 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
949 | 0 | op &= UINT64_C(31); |
950 | 0 | op <<= 25; |
951 | 0 | Value |= op; |
952 | | // op: cc |
953 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
954 | 0 | op &= UINT64_C(3); |
955 | 0 | op <<= 11; |
956 | 0 | Value |= op; |
957 | | // op: cond |
958 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
959 | 0 | op &= UINT64_C(15); |
960 | 0 | op <<= 14; |
961 | 0 | Value |= op; |
962 | | // op: rs2 |
963 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
964 | 0 | op &= UINT64_C(31); |
965 | 0 | Value |= op; |
966 | 0 | break; |
967 | 0 | } |
968 | 0 | case SP::V9MOVFCCri: { |
969 | | // op: rd |
970 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
971 | 0 | op &= UINT64_C(31); |
972 | 0 | op <<= 25; |
973 | 0 | Value |= op; |
974 | | // op: cc |
975 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
976 | 0 | op &= UINT64_C(3); |
977 | 0 | op <<= 11; |
978 | 0 | Value |= op; |
979 | | // op: cond |
980 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
981 | 0 | op &= UINT64_C(15); |
982 | 0 | op <<= 14; |
983 | 0 | Value |= op; |
984 | | // op: simm11 |
985 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
986 | 0 | op &= UINT64_C(2047); |
987 | 0 | Value |= op; |
988 | 0 | break; |
989 | 0 | } |
990 | 0 | case SP::FMOVD_FCC: |
991 | 0 | case SP::FMOVD_ICC: |
992 | 0 | case SP::FMOVD_XCC: |
993 | 0 | case SP::FMOVQ_FCC: |
994 | 0 | case SP::FMOVQ_ICC: |
995 | 0 | case SP::FMOVQ_XCC: |
996 | 0 | case SP::FMOVS_FCC: |
997 | 0 | case SP::FMOVS_ICC: |
998 | 0 | case SP::FMOVS_XCC: |
999 | 0 | case SP::MOVFCCrr: |
1000 | 0 | case SP::MOVICCrr: |
1001 | 0 | case SP::MOVXCCrr: { |
1002 | | // op: rd |
1003 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1004 | 0 | op &= UINT64_C(31); |
1005 | 0 | op <<= 25; |
1006 | 0 | Value |= op; |
1007 | | // op: cond |
1008 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1009 | 0 | op &= UINT64_C(15); |
1010 | 0 | op <<= 14; |
1011 | 0 | Value |= op; |
1012 | | // op: rs2 |
1013 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1014 | 0 | op &= UINT64_C(31); |
1015 | 0 | Value |= op; |
1016 | 0 | break; |
1017 | 0 | } |
1018 | 0 | case SP::MOVFCCri: |
1019 | 0 | case SP::MOVICCri: |
1020 | 0 | case SP::MOVXCCri: { |
1021 | | // op: rd |
1022 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1023 | 0 | op &= UINT64_C(31); |
1024 | 0 | op <<= 25; |
1025 | 0 | Value |= op; |
1026 | | // op: cond |
1027 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1028 | 0 | op &= UINT64_C(15); |
1029 | 0 | op <<= 14; |
1030 | 0 | Value |= op; |
1031 | | // op: simm11 |
1032 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1033 | 0 | op &= UINT64_C(2047); |
1034 | 0 | Value |= op; |
1035 | 0 | break; |
1036 | 0 | } |
1037 | 0 | case SP::V9FMOVD_FCC: |
1038 | 0 | case SP::V9FMOVQ_FCC: |
1039 | 0 | case SP::V9FMOVS_FCC: { |
1040 | | // op: rd |
1041 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1042 | 0 | op &= UINT64_C(31); |
1043 | 0 | op <<= 25; |
1044 | 0 | Value |= op; |
1045 | | // op: cond |
1046 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1047 | 0 | op &= UINT64_C(15); |
1048 | 0 | op <<= 14; |
1049 | 0 | Value |= op; |
1050 | | // op: opf_cc |
1051 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1052 | 0 | op &= UINT64_C(3); |
1053 | 0 | op <<= 11; |
1054 | 0 | Value |= op; |
1055 | | // op: rs2 |
1056 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1057 | 0 | op &= UINT64_C(31); |
1058 | 0 | Value |= op; |
1059 | 0 | break; |
1060 | 0 | } |
1061 | 0 | case SP::FNOT1: |
1062 | 0 | case SP::FNOT1S: |
1063 | 0 | case SP::FSRC1: |
1064 | 0 | case SP::FSRC1S: |
1065 | 0 | case SP::RDASR: |
1066 | 0 | case SP::RDPR: { |
1067 | | // op: rd |
1068 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1069 | 0 | op &= UINT64_C(31); |
1070 | 0 | op <<= 25; |
1071 | 0 | Value |= op; |
1072 | | // op: rs1 |
1073 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1074 | 0 | op &= UINT64_C(31); |
1075 | 0 | op <<= 14; |
1076 | 0 | Value |= op; |
1077 | 0 | break; |
1078 | 0 | } |
1079 | 0 | case SP::LDArr: |
1080 | 0 | case SP::LDDArr: |
1081 | 0 | case SP::LDDFArr: |
1082 | 0 | case SP::LDFArr: |
1083 | 0 | case SP::LDQFArr: |
1084 | 0 | case SP::LDSBArr: |
1085 | 0 | case SP::LDSHArr: |
1086 | 0 | case SP::LDSTUBArr: |
1087 | 0 | case SP::LDSWArr: |
1088 | 0 | case SP::LDUBArr: |
1089 | 0 | case SP::LDUHArr: |
1090 | 0 | case SP::LDXArr: |
1091 | 0 | case SP::SWAPArr: { |
1092 | | // op: rd |
1093 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1094 | 0 | op &= UINT64_C(31); |
1095 | 0 | op <<= 25; |
1096 | 0 | Value |= op; |
1097 | | // op: rs1 |
1098 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1099 | 0 | op &= UINT64_C(31); |
1100 | 0 | op <<= 14; |
1101 | 0 | Value |= op; |
1102 | | // op: asi |
1103 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1104 | 0 | op &= UINT64_C(255); |
1105 | 0 | op <<= 5; |
1106 | 0 | Value |= op; |
1107 | | // op: rs2 |
1108 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1109 | 0 | op &= UINT64_C(31); |
1110 | 0 | Value |= op; |
1111 | 0 | break; |
1112 | 0 | } |
1113 | 0 | case SP::CASArr: |
1114 | 0 | case SP::CASXArr: { |
1115 | | // op: rd |
1116 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1117 | 0 | op &= UINT64_C(31); |
1118 | 0 | op <<= 25; |
1119 | 0 | Value |= op; |
1120 | | // op: rs1 |
1121 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1122 | 0 | op &= UINT64_C(31); |
1123 | 0 | op <<= 14; |
1124 | 0 | Value |= op; |
1125 | | // op: asi |
1126 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1127 | 0 | op &= UINT64_C(255); |
1128 | 0 | op <<= 5; |
1129 | 0 | Value |= op; |
1130 | | // op: rs2 |
1131 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1132 | 0 | op &= UINT64_C(31); |
1133 | 0 | Value |= op; |
1134 | 0 | break; |
1135 | 0 | } |
1136 | 0 | case SP::ADDCCrr: |
1137 | 0 | case SP::ADDCrr: |
1138 | 0 | case SP::ADDErr: |
1139 | 0 | case SP::ADDXC: |
1140 | 0 | case SP::ADDXCCC: |
1141 | 0 | case SP::ADDrr: |
1142 | 0 | case SP::ALIGNADDR: |
1143 | 0 | case SP::ALIGNADDRL: |
1144 | 0 | case SP::ANDCCrr: |
1145 | 0 | case SP::ANDNCCrr: |
1146 | 0 | case SP::ANDNrr: |
1147 | 0 | case SP::ANDrr: |
1148 | 0 | case SP::ARRAY8: |
1149 | 0 | case SP::ARRAY16: |
1150 | 0 | case SP::ARRAY32: |
1151 | 0 | case SP::BMASK: |
1152 | 0 | case SP::BSHUFFLE: |
1153 | 0 | case SP::CASAri: |
1154 | 0 | case SP::CASXAri: |
1155 | 0 | case SP::EDGE8: |
1156 | 0 | case SP::EDGE8L: |
1157 | 0 | case SP::EDGE8LN: |
1158 | 0 | case SP::EDGE8N: |
1159 | 0 | case SP::EDGE16: |
1160 | 0 | case SP::EDGE16L: |
1161 | 0 | case SP::EDGE16LN: |
1162 | 0 | case SP::EDGE16N: |
1163 | 0 | case SP::EDGE32: |
1164 | 0 | case SP::EDGE32L: |
1165 | 0 | case SP::EDGE32LN: |
1166 | 0 | case SP::EDGE32N: |
1167 | 0 | case SP::FADDD: |
1168 | 0 | case SP::FADDQ: |
1169 | 0 | case SP::FADDS: |
1170 | 0 | case SP::FALIGNADATA: |
1171 | 0 | case SP::FAND: |
1172 | 0 | case SP::FANDNOT1: |
1173 | 0 | case SP::FANDNOT1S: |
1174 | 0 | case SP::FANDNOT2: |
1175 | 0 | case SP::FANDNOT2S: |
1176 | 0 | case SP::FANDS: |
1177 | 0 | case SP::FCHKSM16: |
1178 | 0 | case SP::FCMPEQ16: |
1179 | 0 | case SP::FCMPEQ32: |
1180 | 0 | case SP::FCMPGT16: |
1181 | 0 | case SP::FCMPGT32: |
1182 | 0 | case SP::FCMPLE16: |
1183 | 0 | case SP::FCMPLE32: |
1184 | 0 | case SP::FCMPNE16: |
1185 | 0 | case SP::FCMPNE32: |
1186 | 0 | case SP::FDIVD: |
1187 | 0 | case SP::FDIVQ: |
1188 | 0 | case SP::FDIVS: |
1189 | 0 | case SP::FDMULQ: |
1190 | 0 | case SP::FHADDD: |
1191 | 0 | case SP::FHADDS: |
1192 | 0 | case SP::FHSUBD: |
1193 | 0 | case SP::FHSUBS: |
1194 | 0 | case SP::FLCMPD: |
1195 | 0 | case SP::FLCMPS: |
1196 | 0 | case SP::FMEAN16: |
1197 | 0 | case SP::FMUL8SUX16: |
1198 | 0 | case SP::FMUL8ULX16: |
1199 | 0 | case SP::FMUL8X16: |
1200 | 0 | case SP::FMUL8X16AL: |
1201 | 0 | case SP::FMUL8X16AU: |
1202 | 0 | case SP::FMULD: |
1203 | 0 | case SP::FMULD8SUX16: |
1204 | 0 | case SP::FMULD8ULX16: |
1205 | 0 | case SP::FMULQ: |
1206 | 0 | case SP::FMULS: |
1207 | 0 | case SP::FNADDD: |
1208 | 0 | case SP::FNADDS: |
1209 | 0 | case SP::FNAND: |
1210 | 0 | case SP::FNANDS: |
1211 | 0 | case SP::FNHADDD: |
1212 | 0 | case SP::FNHADDS: |
1213 | 0 | case SP::FNMULD: |
1214 | 0 | case SP::FNMULS: |
1215 | 0 | case SP::FNOR: |
1216 | 0 | case SP::FNORS: |
1217 | 0 | case SP::FNSMULD: |
1218 | 0 | case SP::FOR: |
1219 | 0 | case SP::FORNOT1: |
1220 | 0 | case SP::FORNOT1S: |
1221 | 0 | case SP::FORNOT2: |
1222 | 0 | case SP::FORNOT2S: |
1223 | 0 | case SP::FORS: |
1224 | 0 | case SP::FPACK32: |
1225 | 0 | case SP::FPADD16: |
1226 | 0 | case SP::FPADD16S: |
1227 | 0 | case SP::FPADD32: |
1228 | 0 | case SP::FPADD32S: |
1229 | 0 | case SP::FPADD64: |
1230 | 0 | case SP::FPMERGE: |
1231 | 0 | case SP::FPSUB16: |
1232 | 0 | case SP::FPSUB16S: |
1233 | 0 | case SP::FPSUB32: |
1234 | 0 | case SP::FPSUB32S: |
1235 | 0 | case SP::FSLAS16: |
1236 | 0 | case SP::FSLAS32: |
1237 | 0 | case SP::FSLL16: |
1238 | 0 | case SP::FSLL32: |
1239 | 0 | case SP::FSMULD: |
1240 | 0 | case SP::FSRA16: |
1241 | 0 | case SP::FSRA32: |
1242 | 0 | case SP::FSRL16: |
1243 | 0 | case SP::FSRL32: |
1244 | 0 | case SP::FSUBD: |
1245 | 0 | case SP::FSUBQ: |
1246 | 0 | case SP::FSUBS: |
1247 | 0 | case SP::FXNOR: |
1248 | 0 | case SP::FXNORS: |
1249 | 0 | case SP::FXOR: |
1250 | 0 | case SP::FXORS: |
1251 | 0 | case SP::GDOP_LDXrr: |
1252 | 0 | case SP::GDOP_LDrr: |
1253 | 0 | case SP::JMPLrr: |
1254 | 0 | case SP::LDCrr: |
1255 | 0 | case SP::LDDCrr: |
1256 | 0 | case SP::LDDFrr: |
1257 | 0 | case SP::LDDrr: |
1258 | 0 | case SP::LDFrr: |
1259 | 0 | case SP::LDQFrr: |
1260 | 0 | case SP::LDSBrr: |
1261 | 0 | case SP::LDSHrr: |
1262 | 0 | case SP::LDSTUBrr: |
1263 | 0 | case SP::LDSWrr: |
1264 | 0 | case SP::LDUBrr: |
1265 | 0 | case SP::LDUHrr: |
1266 | 0 | case SP::LDXrr: |
1267 | 0 | case SP::LDrr: |
1268 | 0 | case SP::MULSCCrr: |
1269 | 0 | case SP::MULXrr: |
1270 | 0 | case SP::ORCCrr: |
1271 | 0 | case SP::ORNCCrr: |
1272 | 0 | case SP::ORNrr: |
1273 | 0 | case SP::ORrr: |
1274 | 0 | case SP::PDIST: |
1275 | 0 | case SP::PDISTN: |
1276 | 0 | case SP::RESTORErr: |
1277 | 0 | case SP::SAVErr: |
1278 | 0 | case SP::SDIVCCrr: |
1279 | 0 | case SP::SDIVXrr: |
1280 | 0 | case SP::SDIVrr: |
1281 | 0 | case SP::SLLXrr: |
1282 | 0 | case SP::SLLrr: |
1283 | 0 | case SP::SMACrr: |
1284 | 0 | case SP::SMULCCrr: |
1285 | 0 | case SP::SMULrr: |
1286 | 0 | case SP::SRAXrr: |
1287 | 0 | case SP::SRArr: |
1288 | 0 | case SP::SRLXrr: |
1289 | 0 | case SP::SRLrr: |
1290 | 0 | case SP::SUBCCrr: |
1291 | 0 | case SP::SUBCrr: |
1292 | 0 | case SP::SUBErr: |
1293 | 0 | case SP::SUBrr: |
1294 | 0 | case SP::SWAPrr: |
1295 | 0 | case SP::TADDCCTVrr: |
1296 | 0 | case SP::TADDCCrr: |
1297 | 0 | case SP::TLS_ADDrr: |
1298 | 0 | case SP::TLS_LDXrr: |
1299 | 0 | case SP::TLS_LDrr: |
1300 | 0 | case SP::TSUBCCTVrr: |
1301 | 0 | case SP::TSUBCCrr: |
1302 | 0 | case SP::UDIVCCrr: |
1303 | 0 | case SP::UDIVXrr: |
1304 | 0 | case SP::UDIVrr: |
1305 | 0 | case SP::UMACrr: |
1306 | 0 | case SP::UMULCCrr: |
1307 | 0 | case SP::UMULXHI: |
1308 | 0 | case SP::UMULrr: |
1309 | 0 | case SP::V9FCMPD: |
1310 | 0 | case SP::V9FCMPED: |
1311 | 0 | case SP::V9FCMPEQ: |
1312 | 0 | case SP::V9FCMPES: |
1313 | 0 | case SP::V9FCMPQ: |
1314 | 0 | case SP::V9FCMPS: |
1315 | 0 | case SP::WRASRrr: |
1316 | 0 | case SP::WRPRrr: |
1317 | 0 | case SP::XMULX: |
1318 | 0 | case SP::XMULXHI: |
1319 | 0 | case SP::XNORCCrr: |
1320 | 0 | case SP::XNORrr: |
1321 | 0 | case SP::XORCCrr: |
1322 | 0 | case SP::XORrr: { |
1323 | | // op: rd |
1324 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1325 | 0 | op &= UINT64_C(31); |
1326 | 0 | op <<= 25; |
1327 | 0 | Value |= op; |
1328 | | // op: rs1 |
1329 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1330 | 0 | op &= UINT64_C(31); |
1331 | 0 | op <<= 14; |
1332 | 0 | Value |= op; |
1333 | | // op: rs2 |
1334 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1335 | 0 | op &= UINT64_C(31); |
1336 | 0 | Value |= op; |
1337 | 0 | break; |
1338 | 0 | } |
1339 | 0 | case SP::FMOVRD: |
1340 | 0 | case SP::FMOVRQ: |
1341 | 0 | case SP::FMOVRS: |
1342 | 0 | case SP::MOVRrr: { |
1343 | | // op: rd |
1344 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1345 | 0 | op &= UINT64_C(31); |
1346 | 0 | op <<= 25; |
1347 | 0 | Value |= op; |
1348 | | // op: rs1 |
1349 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1350 | 0 | op &= UINT64_C(31); |
1351 | 0 | op <<= 14; |
1352 | 0 | Value |= op; |
1353 | | // op: rs2 |
1354 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1355 | 0 | op &= UINT64_C(31); |
1356 | 0 | Value |= op; |
1357 | | // op: rcond |
1358 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1359 | 0 | op &= UINT64_C(7); |
1360 | 0 | op <<= 10; |
1361 | 0 | Value |= op; |
1362 | 0 | break; |
1363 | 0 | } |
1364 | 0 | case SP::SLLXri: |
1365 | 0 | case SP::SLLri: |
1366 | 0 | case SP::SRAXri: |
1367 | 0 | case SP::SRAri: |
1368 | 0 | case SP::SRLXri: |
1369 | 0 | case SP::SRLri: { |
1370 | | // op: rd |
1371 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1372 | 0 | op &= UINT64_C(31); |
1373 | 0 | op <<= 25; |
1374 | 0 | Value |= op; |
1375 | | // op: rs1 |
1376 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1377 | 0 | op &= UINT64_C(31); |
1378 | 0 | op <<= 14; |
1379 | 0 | Value |= op; |
1380 | | // op: shcnt |
1381 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1382 | 0 | op &= UINT64_C(63); |
1383 | 0 | Value |= op; |
1384 | 0 | break; |
1385 | 0 | } |
1386 | 0 | case SP::MOVRri: { |
1387 | | // op: rd |
1388 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1389 | 0 | op &= UINT64_C(31); |
1390 | 0 | op <<= 25; |
1391 | 0 | Value |= op; |
1392 | | // op: rs1 |
1393 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1394 | 0 | op &= UINT64_C(31); |
1395 | 0 | op <<= 14; |
1396 | 0 | Value |= op; |
1397 | | // op: simm10 |
1398 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1399 | 0 | op &= UINT64_C(1023); |
1400 | 0 | Value |= op; |
1401 | | // op: rcond |
1402 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1403 | 0 | op &= UINT64_C(7); |
1404 | 0 | op <<= 10; |
1405 | 0 | Value |= op; |
1406 | 0 | break; |
1407 | 0 | } |
1408 | 0 | case SP::JMPLri: |
1409 | 0 | case SP::LDAri: |
1410 | 0 | case SP::LDCri: |
1411 | 0 | case SP::LDDAri: |
1412 | 0 | case SP::LDDCri: |
1413 | 0 | case SP::LDDFAri: |
1414 | 0 | case SP::LDDFri: |
1415 | 0 | case SP::LDDri: |
1416 | 0 | case SP::LDFAri: |
1417 | 0 | case SP::LDFri: |
1418 | 0 | case SP::LDQFAri: |
1419 | 0 | case SP::LDQFri: |
1420 | 0 | case SP::LDSBAri: |
1421 | 0 | case SP::LDSBri: |
1422 | 0 | case SP::LDSHAri: |
1423 | 0 | case SP::LDSHri: |
1424 | 0 | case SP::LDSTUBAri: |
1425 | 0 | case SP::LDSTUBri: |
1426 | 0 | case SP::LDSWAri: |
1427 | 0 | case SP::LDSWri: |
1428 | 0 | case SP::LDUBAri: |
1429 | 0 | case SP::LDUBri: |
1430 | 0 | case SP::LDUHAri: |
1431 | 0 | case SP::LDUHri: |
1432 | 0 | case SP::LDXAri: |
1433 | 0 | case SP::LDXri: |
1434 | 0 | case SP::LDri: |
1435 | 0 | case SP::MULXri: |
1436 | 0 | case SP::SDIVXri: |
1437 | 0 | case SP::SWAPAri: |
1438 | 0 | case SP::SWAPri: |
1439 | 0 | case SP::UDIVXri: { |
1440 | | // op: rd |
1441 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1442 | 0 | op &= UINT64_C(31); |
1443 | 0 | op <<= 25; |
1444 | 0 | Value |= op; |
1445 | | // op: rs1 |
1446 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1447 | 0 | op &= UINT64_C(31); |
1448 | 0 | op <<= 14; |
1449 | 0 | Value |= op; |
1450 | | // op: simm13 |
1451 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1452 | 0 | op &= UINT64_C(8191); |
1453 | 0 | Value |= op; |
1454 | 0 | break; |
1455 | 0 | } |
1456 | 0 | case SP::ADDCCri: |
1457 | 0 | case SP::ADDCri: |
1458 | 0 | case SP::ADDEri: |
1459 | 0 | case SP::ADDri: |
1460 | 0 | case SP::ANDCCri: |
1461 | 0 | case SP::ANDNCCri: |
1462 | 0 | case SP::ANDNri: |
1463 | 0 | case SP::ANDri: |
1464 | 0 | case SP::MULSCCri: |
1465 | 0 | case SP::ORCCri: |
1466 | 0 | case SP::ORNCCri: |
1467 | 0 | case SP::ORNri: |
1468 | 0 | case SP::ORri: |
1469 | 0 | case SP::RESTOREri: |
1470 | 0 | case SP::SAVEri: |
1471 | 0 | case SP::SDIVCCri: |
1472 | 0 | case SP::SDIVri: |
1473 | 0 | case SP::SMACri: |
1474 | 0 | case SP::SMULCCri: |
1475 | 0 | case SP::SMULri: |
1476 | 0 | case SP::SUBCCri: |
1477 | 0 | case SP::SUBCri: |
1478 | 0 | case SP::SUBEri: |
1479 | 0 | case SP::SUBri: |
1480 | 0 | case SP::TADDCCTVri: |
1481 | 0 | case SP::TADDCCri: |
1482 | 0 | case SP::TSUBCCTVri: |
1483 | 0 | case SP::TSUBCCri: |
1484 | 0 | case SP::UDIVCCri: |
1485 | 0 | case SP::UDIVri: |
1486 | 0 | case SP::UMACri: |
1487 | 0 | case SP::UMULCCri: |
1488 | 0 | case SP::UMULri: |
1489 | 0 | case SP::WRASRri: |
1490 | 0 | case SP::WRPRri: |
1491 | 0 | case SP::XNORCCri: |
1492 | 0 | case SP::XNORri: |
1493 | 0 | case SP::XORCCri: |
1494 | 0 | case SP::XORri: { |
1495 | | // op: rd |
1496 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1497 | 0 | op &= UINT64_C(31); |
1498 | 0 | op <<= 25; |
1499 | 0 | Value |= op; |
1500 | | // op: rs1 |
1501 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1502 | 0 | op &= UINT64_C(31); |
1503 | 0 | op <<= 14; |
1504 | 0 | Value |= op; |
1505 | | // op: simm13 |
1506 | 0 | op = getSImm13OpValue(MI, 2, Fixups, STI); |
1507 | 0 | op &= UINT64_C(8191); |
1508 | 0 | Value |= op; |
1509 | 0 | break; |
1510 | 0 | } |
1511 | 0 | case SP::FABSD: |
1512 | 0 | case SP::FABSQ: |
1513 | 0 | case SP::FABSS: |
1514 | 0 | case SP::FDTOI: |
1515 | 0 | case SP::FDTOQ: |
1516 | 0 | case SP::FDTOS: |
1517 | 0 | case SP::FDTOX: |
1518 | 0 | case SP::FEXPAND: |
1519 | 0 | case SP::FITOD: |
1520 | 0 | case SP::FITOQ: |
1521 | 0 | case SP::FITOS: |
1522 | 0 | case SP::FMOVD: |
1523 | 0 | case SP::FMOVQ: |
1524 | 0 | case SP::FMOVS: |
1525 | 0 | case SP::FNEGD: |
1526 | 0 | case SP::FNEGQ: |
1527 | 0 | case SP::FNEGS: |
1528 | 0 | case SP::FNOT2: |
1529 | 0 | case SP::FNOT2S: |
1530 | 0 | case SP::FPACK16: |
1531 | 0 | case SP::FPACKFIX: |
1532 | 0 | case SP::FQTOD: |
1533 | 0 | case SP::FQTOI: |
1534 | 0 | case SP::FQTOS: |
1535 | 0 | case SP::FQTOX: |
1536 | 0 | case SP::FSQRTD: |
1537 | 0 | case SP::FSQRTQ: |
1538 | 0 | case SP::FSQRTS: |
1539 | 0 | case SP::FSRC2: |
1540 | 0 | case SP::FSRC2S: |
1541 | 0 | case SP::FSTOD: |
1542 | 0 | case SP::FSTOI: |
1543 | 0 | case SP::FSTOQ: |
1544 | 0 | case SP::FSTOX: |
1545 | 0 | case SP::FXTOD: |
1546 | 0 | case SP::FXTOQ: |
1547 | 0 | case SP::FXTOS: |
1548 | 0 | case SP::LZCNT: |
1549 | 0 | case SP::MOVDTOX: |
1550 | 0 | case SP::MOVSTOSW: |
1551 | 0 | case SP::MOVSTOUW: |
1552 | 0 | case SP::MOVWTOS: |
1553 | 0 | case SP::MOVXTOD: |
1554 | 0 | case SP::POPCrr: { |
1555 | | // op: rd |
1556 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1557 | 0 | op &= UINT64_C(31); |
1558 | 0 | op <<= 25; |
1559 | 0 | Value |= op; |
1560 | | // op: rs2 |
1561 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1562 | 0 | op &= UINT64_C(31); |
1563 | 0 | Value |= op; |
1564 | 0 | break; |
1565 | 0 | } |
1566 | 0 | case SP::STArr: |
1567 | 0 | case SP::STBArr: |
1568 | 0 | case SP::STDArr: |
1569 | 0 | case SP::STDFArr: |
1570 | 0 | case SP::STFArr: |
1571 | 0 | case SP::STHArr: |
1572 | 0 | case SP::STQFArr: |
1573 | 0 | case SP::STXArr: { |
1574 | | // op: rd |
1575 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1576 | 0 | op &= UINT64_C(31); |
1577 | 0 | op <<= 25; |
1578 | 0 | Value |= op; |
1579 | | // op: rs1 |
1580 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1581 | 0 | op &= UINT64_C(31); |
1582 | 0 | op <<= 14; |
1583 | 0 | Value |= op; |
1584 | | // op: asi |
1585 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1586 | 0 | op &= UINT64_C(255); |
1587 | 0 | op <<= 5; |
1588 | 0 | Value |= op; |
1589 | | // op: rs2 |
1590 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1591 | 0 | op &= UINT64_C(31); |
1592 | 0 | Value |= op; |
1593 | 0 | break; |
1594 | 0 | } |
1595 | 0 | case SP::PREFETCHr: |
1596 | 0 | case SP::STBrr: |
1597 | 0 | case SP::STCrr: |
1598 | 0 | case SP::STDCrr: |
1599 | 0 | case SP::STDFrr: |
1600 | 0 | case SP::STDrr: |
1601 | 0 | case SP::STFrr: |
1602 | 0 | case SP::STHrr: |
1603 | 0 | case SP::STQFrr: |
1604 | 0 | case SP::STXrr: |
1605 | 0 | case SP::STrr: { |
1606 | | // op: rd |
1607 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1608 | 0 | op &= UINT64_C(31); |
1609 | 0 | op <<= 25; |
1610 | 0 | Value |= op; |
1611 | | // op: rs1 |
1612 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1613 | 0 | op &= UINT64_C(31); |
1614 | 0 | op <<= 14; |
1615 | 0 | Value |= op; |
1616 | | // op: rs2 |
1617 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1618 | 0 | op &= UINT64_C(31); |
1619 | 0 | Value |= op; |
1620 | 0 | break; |
1621 | 0 | } |
1622 | 0 | case SP::PREFETCHi: |
1623 | 0 | case SP::STAri: |
1624 | 0 | case SP::STBAri: |
1625 | 0 | case SP::STBri: |
1626 | 0 | case SP::STCri: |
1627 | 0 | case SP::STDAri: |
1628 | 0 | case SP::STDCri: |
1629 | 0 | case SP::STDFAri: |
1630 | 0 | case SP::STDFri: |
1631 | 0 | case SP::STDri: |
1632 | 0 | case SP::STFAri: |
1633 | 0 | case SP::STFri: |
1634 | 0 | case SP::STHAri: |
1635 | 0 | case SP::STHri: |
1636 | 0 | case SP::STQFAri: |
1637 | 0 | case SP::STQFri: |
1638 | 0 | case SP::STXAri: |
1639 | 0 | case SP::STXri: |
1640 | 0 | case SP::STri: { |
1641 | | // op: rd |
1642 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1643 | 0 | op &= UINT64_C(31); |
1644 | 0 | op <<= 25; |
1645 | 0 | Value |= op; |
1646 | | // op: rs1 |
1647 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1648 | 0 | op &= UINT64_C(31); |
1649 | 0 | op <<= 14; |
1650 | 0 | Value |= op; |
1651 | | // op: simm13 |
1652 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1653 | 0 | op &= UINT64_C(8191); |
1654 | 0 | Value |= op; |
1655 | 0 | break; |
1656 | 0 | } |
1657 | 0 | case SP::TICCri: |
1658 | 0 | case SP::TRAPri: |
1659 | 0 | case SP::TXCCri: { |
1660 | | // op: rs1 |
1661 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1662 | 0 | op &= UINT64_C(31); |
1663 | 0 | op <<= 14; |
1664 | 0 | Value |= op; |
1665 | | // op: cond |
1666 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1667 | 0 | op &= UINT64_C(15); |
1668 | 0 | op <<= 25; |
1669 | 0 | Value |= op; |
1670 | | // op: imm |
1671 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1672 | 0 | op &= UINT64_C(255); |
1673 | 0 | Value |= op; |
1674 | 0 | break; |
1675 | 0 | } |
1676 | 0 | case SP::TICCrr: |
1677 | 0 | case SP::TRAPrr: |
1678 | 0 | case SP::TXCCrr: { |
1679 | | // op: rs1 |
1680 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1681 | 0 | op &= UINT64_C(31); |
1682 | 0 | op <<= 14; |
1683 | 0 | Value |= op; |
1684 | | // op: cond |
1685 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1686 | 0 | op &= UINT64_C(15); |
1687 | 0 | op <<= 25; |
1688 | 0 | Value |= op; |
1689 | | // op: rs2 |
1690 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1691 | 0 | op &= UINT64_C(31); |
1692 | 0 | Value |= op; |
1693 | 0 | break; |
1694 | 0 | } |
1695 | 0 | case SP::BINDrr: |
1696 | 0 | case SP::CALLrr: |
1697 | 0 | case SP::FCMPD: |
1698 | 0 | case SP::FCMPD_V9: |
1699 | 0 | case SP::FCMPQ: |
1700 | 0 | case SP::FCMPQ_V9: |
1701 | 0 | case SP::FCMPS: |
1702 | 0 | case SP::FCMPS_V9: |
1703 | 0 | case SP::FLUSHrr: |
1704 | 0 | case SP::LDCSRrr: |
1705 | 0 | case SP::LDFSRrr: |
1706 | 0 | case SP::LDXFSRrr: |
1707 | 0 | case SP::PWRPSRrr: |
1708 | 0 | case SP::RETTrr: |
1709 | 0 | case SP::STCSRrr: |
1710 | 0 | case SP::STDCQrr: |
1711 | 0 | case SP::STDFQrr: |
1712 | 0 | case SP::STFSRrr: |
1713 | 0 | case SP::STXFSRrr: |
1714 | 0 | case SP::WRPSRrr: |
1715 | 0 | case SP::WRTBRrr: |
1716 | 0 | case SP::WRWIMrr: { |
1717 | | // op: rs1 |
1718 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1719 | 0 | op &= UINT64_C(31); |
1720 | 0 | op <<= 14; |
1721 | 0 | Value |= op; |
1722 | | // op: rs2 |
1723 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1724 | 0 | op &= UINT64_C(31); |
1725 | 0 | Value |= op; |
1726 | 0 | break; |
1727 | 0 | } |
1728 | 0 | case SP::BINDri: |
1729 | 0 | case SP::CALLri: |
1730 | 0 | case SP::FLUSHri: |
1731 | 0 | case SP::LDCSRri: |
1732 | 0 | case SP::LDFSRri: |
1733 | 0 | case SP::LDXFSRri: |
1734 | 0 | case SP::RETTri: |
1735 | 0 | case SP::STCSRri: |
1736 | 0 | case SP::STDCQri: |
1737 | 0 | case SP::STDFQri: |
1738 | 0 | case SP::STFSRri: |
1739 | 0 | case SP::STXFSRri: |
1740 | 0 | case SP::TAIL_CALLri: { |
1741 | | // op: rs1 |
1742 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1743 | 0 | op &= UINT64_C(31); |
1744 | 0 | op <<= 14; |
1745 | 0 | Value |= op; |
1746 | | // op: simm13 |
1747 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1748 | 0 | op &= UINT64_C(8191); |
1749 | 0 | Value |= op; |
1750 | 0 | break; |
1751 | 0 | } |
1752 | 0 | case SP::PWRPSRri: |
1753 | 0 | case SP::WRPSRri: |
1754 | 0 | case SP::WRTBRri: |
1755 | 0 | case SP::WRWIMri: { |
1756 | | // op: rs1 |
1757 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1758 | 0 | op &= UINT64_C(31); |
1759 | 0 | op <<= 14; |
1760 | 0 | Value |= op; |
1761 | | // op: simm13 |
1762 | 0 | op = getSImm13OpValue(MI, 1, Fixups, STI); |
1763 | 0 | op &= UINT64_C(8191); |
1764 | 0 | Value |= op; |
1765 | 0 | break; |
1766 | 0 | } |
1767 | 0 | case SP::CMASK8: |
1768 | 0 | case SP::CMASK16: |
1769 | 0 | case SP::CMASK32: { |
1770 | | // op: rs2 |
1771 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1772 | 0 | op &= UINT64_C(31); |
1773 | 0 | Value |= op; |
1774 | 0 | break; |
1775 | 0 | } |
1776 | 0 | case SP::MEMBARi: |
1777 | 0 | case SP::RET: |
1778 | 0 | case SP::RETL: { |
1779 | | // op: simm13 |
1780 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1781 | 0 | op &= UINT64_C(8191); |
1782 | 0 | Value |= op; |
1783 | 0 | break; |
1784 | 0 | } |
1785 | 0 | case SP::SIR: { |
1786 | | // op: simm13 |
1787 | 0 | op = getSImm13OpValue(MI, 0, Fixups, STI); |
1788 | 0 | op &= UINT64_C(8191); |
1789 | 0 | Value |= op; |
1790 | 0 | break; |
1791 | 0 | } |
1792 | 0 | default: |
1793 | 0 | std::string msg; |
1794 | 0 | raw_string_ostream Msg(msg); |
1795 | 0 | Msg << "Not supported instr: " << MI; |
1796 | 0 | report_fatal_error(Msg.str().c_str()); |
1797 | 0 | } |
1798 | 0 | return Value; |
1799 | 0 | } |
1800 | | |
1801 | | #ifdef GET_OPERAND_BIT_OFFSET |
1802 | | #undef GET_OPERAND_BIT_OFFSET |
1803 | | |
1804 | | uint32_t SparcMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
1805 | | unsigned OpNum, |
1806 | | const MCSubtargetInfo &STI) const { |
1807 | | switch (MI.getOpcode()) { |
1808 | | case SP::DONE: |
1809 | | case SP::FLUSH: |
1810 | | case SP::FLUSHW: |
1811 | | case SP::NOP: |
1812 | | case SP::RESTORED: |
1813 | | case SP::RETRY: |
1814 | | case SP::SAVED: |
1815 | | case SP::SHUTDOWN: |
1816 | | case SP::SIAM: |
1817 | | case SP::STBAR: |
1818 | | case SP::TA1: |
1819 | | case SP::TA3: |
1820 | | case SP::TA5: { |
1821 | | break; |
1822 | | } |
1823 | | case SP::CALL: |
1824 | | case SP::TAIL_CALL: |
1825 | | case SP::TLS_CALL: { |
1826 | | switch (OpNum) { |
1827 | | case 0: |
1828 | | // op: disp |
1829 | | return 0; |
1830 | | } |
1831 | | break; |
1832 | | } |
1833 | | case SP::BPR: |
1834 | | case SP::BPRA: |
1835 | | case SP::BPRANT: |
1836 | | case SP::BPRNT: { |
1837 | | switch (OpNum) { |
1838 | | case 0: |
1839 | | // op: imm16 |
1840 | | return 0; |
1841 | | case 2: |
1842 | | // op: rs1 |
1843 | | return 14; |
1844 | | case 1: |
1845 | | // op: rcond |
1846 | | return 25; |
1847 | | } |
1848 | | break; |
1849 | | } |
1850 | | case SP::BCOND: |
1851 | | case SP::BCONDA: |
1852 | | case SP::CBCOND: |
1853 | | case SP::CBCONDA: |
1854 | | case SP::FBCOND: |
1855 | | case SP::FBCONDA: { |
1856 | | switch (OpNum) { |
1857 | | case 0: |
1858 | | // op: imm22 |
1859 | | return 0; |
1860 | | case 1: |
1861 | | // op: cond |
1862 | | return 25; |
1863 | | } |
1864 | | break; |
1865 | | } |
1866 | | case SP::BA: |
1867 | | case SP::UNIMP: { |
1868 | | switch (OpNum) { |
1869 | | case 0: |
1870 | | // op: imm22 |
1871 | | return 0; |
1872 | | } |
1873 | | break; |
1874 | | } |
1875 | | case SP::V9MOVFCCrr: { |
1876 | | switch (OpNum) { |
1877 | | case 0: |
1878 | | // op: rd |
1879 | | return 25; |
1880 | | case 1: |
1881 | | // op: cc |
1882 | | return 11; |
1883 | | case 4: |
1884 | | // op: cond |
1885 | | return 14; |
1886 | | case 2: |
1887 | | // op: rs2 |
1888 | | return 0; |
1889 | | } |
1890 | | break; |
1891 | | } |
1892 | | case SP::V9MOVFCCri: { |
1893 | | switch (OpNum) { |
1894 | | case 0: |
1895 | | // op: rd |
1896 | | return 25; |
1897 | | case 1: |
1898 | | // op: cc |
1899 | | return 11; |
1900 | | case 4: |
1901 | | // op: cond |
1902 | | return 14; |
1903 | | case 2: |
1904 | | // op: simm11 |
1905 | | return 0; |
1906 | | } |
1907 | | break; |
1908 | | } |
1909 | | case SP::FMOVRD: |
1910 | | case SP::FMOVRQ: |
1911 | | case SP::FMOVRS: |
1912 | | case SP::MOVRrr: { |
1913 | | switch (OpNum) { |
1914 | | case 0: |
1915 | | // op: rd |
1916 | | return 25; |
1917 | | case 1: |
1918 | | // op: rs1 |
1919 | | return 14; |
1920 | | case 2: |
1921 | | // op: rs2 |
1922 | | return 0; |
1923 | | case 4: |
1924 | | // op: rcond |
1925 | | return 10; |
1926 | | } |
1927 | | break; |
1928 | | } |
1929 | | case SP::ADDCCrr: |
1930 | | case SP::ADDCrr: |
1931 | | case SP::ADDErr: |
1932 | | case SP::ADDXC: |
1933 | | case SP::ADDXCCC: |
1934 | | case SP::ADDrr: |
1935 | | case SP::ALIGNADDR: |
1936 | | case SP::ALIGNADDRL: |
1937 | | case SP::ANDCCrr: |
1938 | | case SP::ANDNCCrr: |
1939 | | case SP::ANDNrr: |
1940 | | case SP::ANDrr: |
1941 | | case SP::ARRAY8: |
1942 | | case SP::ARRAY16: |
1943 | | case SP::ARRAY32: |
1944 | | case SP::BMASK: |
1945 | | case SP::BSHUFFLE: |
1946 | | case SP::CASAri: |
1947 | | case SP::CASXAri: |
1948 | | case SP::EDGE8: |
1949 | | case SP::EDGE8L: |
1950 | | case SP::EDGE8LN: |
1951 | | case SP::EDGE8N: |
1952 | | case SP::EDGE16: |
1953 | | case SP::EDGE16L: |
1954 | | case SP::EDGE16LN: |
1955 | | case SP::EDGE16N: |
1956 | | case SP::EDGE32: |
1957 | | case SP::EDGE32L: |
1958 | | case SP::EDGE32LN: |
1959 | | case SP::EDGE32N: |
1960 | | case SP::FADDD: |
1961 | | case SP::FADDQ: |
1962 | | case SP::FADDS: |
1963 | | case SP::FALIGNADATA: |
1964 | | case SP::FAND: |
1965 | | case SP::FANDNOT1: |
1966 | | case SP::FANDNOT1S: |
1967 | | case SP::FANDNOT2: |
1968 | | case SP::FANDNOT2S: |
1969 | | case SP::FANDS: |
1970 | | case SP::FCHKSM16: |
1971 | | case SP::FCMPEQ16: |
1972 | | case SP::FCMPEQ32: |
1973 | | case SP::FCMPGT16: |
1974 | | case SP::FCMPGT32: |
1975 | | case SP::FCMPLE16: |
1976 | | case SP::FCMPLE32: |
1977 | | case SP::FCMPNE16: |
1978 | | case SP::FCMPNE32: |
1979 | | case SP::FDIVD: |
1980 | | case SP::FDIVQ: |
1981 | | case SP::FDIVS: |
1982 | | case SP::FDMULQ: |
1983 | | case SP::FHADDD: |
1984 | | case SP::FHADDS: |
1985 | | case SP::FHSUBD: |
1986 | | case SP::FHSUBS: |
1987 | | case SP::FLCMPD: |
1988 | | case SP::FLCMPS: |
1989 | | case SP::FMEAN16: |
1990 | | case SP::FMUL8SUX16: |
1991 | | case SP::FMUL8ULX16: |
1992 | | case SP::FMUL8X16: |
1993 | | case SP::FMUL8X16AL: |
1994 | | case SP::FMUL8X16AU: |
1995 | | case SP::FMULD: |
1996 | | case SP::FMULD8SUX16: |
1997 | | case SP::FMULD8ULX16: |
1998 | | case SP::FMULQ: |
1999 | | case SP::FMULS: |
2000 | | case SP::FNADDD: |
2001 | | case SP::FNADDS: |
2002 | | case SP::FNAND: |
2003 | | case SP::FNANDS: |
2004 | | case SP::FNHADDD: |
2005 | | case SP::FNHADDS: |
2006 | | case SP::FNMULD: |
2007 | | case SP::FNMULS: |
2008 | | case SP::FNOR: |
2009 | | case SP::FNORS: |
2010 | | case SP::FNSMULD: |
2011 | | case SP::FOR: |
2012 | | case SP::FORNOT1: |
2013 | | case SP::FORNOT1S: |
2014 | | case SP::FORNOT2: |
2015 | | case SP::FORNOT2S: |
2016 | | case SP::FORS: |
2017 | | case SP::FPACK32: |
2018 | | case SP::FPADD16: |
2019 | | case SP::FPADD16S: |
2020 | | case SP::FPADD32: |
2021 | | case SP::FPADD32S: |
2022 | | case SP::FPADD64: |
2023 | | case SP::FPMERGE: |
2024 | | case SP::FPSUB16: |
2025 | | case SP::FPSUB16S: |
2026 | | case SP::FPSUB32: |
2027 | | case SP::FPSUB32S: |
2028 | | case SP::FSLAS16: |
2029 | | case SP::FSLAS32: |
2030 | | case SP::FSLL16: |
2031 | | case SP::FSLL32: |
2032 | | case SP::FSMULD: |
2033 | | case SP::FSRA16: |
2034 | | case SP::FSRA32: |
2035 | | case SP::FSRL16: |
2036 | | case SP::FSRL32: |
2037 | | case SP::FSUBD: |
2038 | | case SP::FSUBQ: |
2039 | | case SP::FSUBS: |
2040 | | case SP::FXNOR: |
2041 | | case SP::FXNORS: |
2042 | | case SP::FXOR: |
2043 | | case SP::FXORS: |
2044 | | case SP::GDOP_LDXrr: |
2045 | | case SP::GDOP_LDrr: |
2046 | | case SP::JMPLrr: |
2047 | | case SP::LDCrr: |
2048 | | case SP::LDDCrr: |
2049 | | case SP::LDDFrr: |
2050 | | case SP::LDDrr: |
2051 | | case SP::LDFrr: |
2052 | | case SP::LDQFrr: |
2053 | | case SP::LDSBrr: |
2054 | | case SP::LDSHrr: |
2055 | | case SP::LDSTUBrr: |
2056 | | case SP::LDSWrr: |
2057 | | case SP::LDUBrr: |
2058 | | case SP::LDUHrr: |
2059 | | case SP::LDXrr: |
2060 | | case SP::LDrr: |
2061 | | case SP::MULSCCrr: |
2062 | | case SP::MULXrr: |
2063 | | case SP::ORCCrr: |
2064 | | case SP::ORNCCrr: |
2065 | | case SP::ORNrr: |
2066 | | case SP::ORrr: |
2067 | | case SP::PDIST: |
2068 | | case SP::PDISTN: |
2069 | | case SP::RESTORErr: |
2070 | | case SP::SAVErr: |
2071 | | case SP::SDIVCCrr: |
2072 | | case SP::SDIVXrr: |
2073 | | case SP::SDIVrr: |
2074 | | case SP::SLLXrr: |
2075 | | case SP::SLLrr: |
2076 | | case SP::SMACrr: |
2077 | | case SP::SMULCCrr: |
2078 | | case SP::SMULrr: |
2079 | | case SP::SRAXrr: |
2080 | | case SP::SRArr: |
2081 | | case SP::SRLXrr: |
2082 | | case SP::SRLrr: |
2083 | | case SP::SUBCCrr: |
2084 | | case SP::SUBCrr: |
2085 | | case SP::SUBErr: |
2086 | | case SP::SUBrr: |
2087 | | case SP::SWAPrr: |
2088 | | case SP::TADDCCTVrr: |
2089 | | case SP::TADDCCrr: |
2090 | | case SP::TLS_ADDrr: |
2091 | | case SP::TLS_LDXrr: |
2092 | | case SP::TLS_LDrr: |
2093 | | case SP::TSUBCCTVrr: |
2094 | | case SP::TSUBCCrr: |
2095 | | case SP::UDIVCCrr: |
2096 | | case SP::UDIVXrr: |
2097 | | case SP::UDIVrr: |
2098 | | case SP::UMACrr: |
2099 | | case SP::UMULCCrr: |
2100 | | case SP::UMULXHI: |
2101 | | case SP::UMULrr: |
2102 | | case SP::V9FCMPD: |
2103 | | case SP::V9FCMPED: |
2104 | | case SP::V9FCMPEQ: |
2105 | | case SP::V9FCMPES: |
2106 | | case SP::V9FCMPQ: |
2107 | | case SP::V9FCMPS: |
2108 | | case SP::WRASRrr: |
2109 | | case SP::WRPRrr: |
2110 | | case SP::XMULX: |
2111 | | case SP::XMULXHI: |
2112 | | case SP::XNORCCrr: |
2113 | | case SP::XNORrr: |
2114 | | case SP::XORCCrr: |
2115 | | case SP::XORrr: { |
2116 | | switch (OpNum) { |
2117 | | case 0: |
2118 | | // op: rd |
2119 | | return 25; |
2120 | | case 1: |
2121 | | // op: rs1 |
2122 | | return 14; |
2123 | | case 2: |
2124 | | // op: rs2 |
2125 | | return 0; |
2126 | | } |
2127 | | break; |
2128 | | } |
2129 | | case SP::SLLXri: |
2130 | | case SP::SLLri: |
2131 | | case SP::SRAXri: |
2132 | | case SP::SRAri: |
2133 | | case SP::SRLXri: |
2134 | | case SP::SRLri: { |
2135 | | switch (OpNum) { |
2136 | | case 0: |
2137 | | // op: rd |
2138 | | return 25; |
2139 | | case 1: |
2140 | | // op: rs1 |
2141 | | return 14; |
2142 | | case 2: |
2143 | | // op: shcnt |
2144 | | return 0; |
2145 | | } |
2146 | | break; |
2147 | | } |
2148 | | case SP::MOVRri: { |
2149 | | switch (OpNum) { |
2150 | | case 0: |
2151 | | // op: rd |
2152 | | return 25; |
2153 | | case 1: |
2154 | | // op: rs1 |
2155 | | return 14; |
2156 | | case 2: |
2157 | | // op: simm10 |
2158 | | return 0; |
2159 | | case 4: |
2160 | | // op: rcond |
2161 | | return 10; |
2162 | | } |
2163 | | break; |
2164 | | } |
2165 | | case SP::ADDCCri: |
2166 | | case SP::ADDCri: |
2167 | | case SP::ADDEri: |
2168 | | case SP::ADDri: |
2169 | | case SP::ANDCCri: |
2170 | | case SP::ANDNCCri: |
2171 | | case SP::ANDNri: |
2172 | | case SP::ANDri: |
2173 | | case SP::JMPLri: |
2174 | | case SP::LDAri: |
2175 | | case SP::LDCri: |
2176 | | case SP::LDDAri: |
2177 | | case SP::LDDCri: |
2178 | | case SP::LDDFAri: |
2179 | | case SP::LDDFri: |
2180 | | case SP::LDDri: |
2181 | | case SP::LDFAri: |
2182 | | case SP::LDFri: |
2183 | | case SP::LDQFAri: |
2184 | | case SP::LDQFri: |
2185 | | case SP::LDSBAri: |
2186 | | case SP::LDSBri: |
2187 | | case SP::LDSHAri: |
2188 | | case SP::LDSHri: |
2189 | | case SP::LDSTUBAri: |
2190 | | case SP::LDSTUBri: |
2191 | | case SP::LDSWAri: |
2192 | | case SP::LDSWri: |
2193 | | case SP::LDUBAri: |
2194 | | case SP::LDUBri: |
2195 | | case SP::LDUHAri: |
2196 | | case SP::LDUHri: |
2197 | | case SP::LDXAri: |
2198 | | case SP::LDXri: |
2199 | | case SP::LDri: |
2200 | | case SP::MULSCCri: |
2201 | | case SP::MULXri: |
2202 | | case SP::ORCCri: |
2203 | | case SP::ORNCCri: |
2204 | | case SP::ORNri: |
2205 | | case SP::ORri: |
2206 | | case SP::RESTOREri: |
2207 | | case SP::SAVEri: |
2208 | | case SP::SDIVCCri: |
2209 | | case SP::SDIVXri: |
2210 | | case SP::SDIVri: |
2211 | | case SP::SMACri: |
2212 | | case SP::SMULCCri: |
2213 | | case SP::SMULri: |
2214 | | case SP::SUBCCri: |
2215 | | case SP::SUBCri: |
2216 | | case SP::SUBEri: |
2217 | | case SP::SUBri: |
2218 | | case SP::SWAPAri: |
2219 | | case SP::SWAPri: |
2220 | | case SP::TADDCCTVri: |
2221 | | case SP::TADDCCri: |
2222 | | case SP::TSUBCCTVri: |
2223 | | case SP::TSUBCCri: |
2224 | | case SP::UDIVCCri: |
2225 | | case SP::UDIVXri: |
2226 | | case SP::UDIVri: |
2227 | | case SP::UMACri: |
2228 | | case SP::UMULCCri: |
2229 | | case SP::UMULri: |
2230 | | case SP::WRASRri: |
2231 | | case SP::WRPRri: |
2232 | | case SP::XNORCCri: |
2233 | | case SP::XNORri: |
2234 | | case SP::XORCCri: |
2235 | | case SP::XORri: { |
2236 | | switch (OpNum) { |
2237 | | case 0: |
2238 | | // op: rd |
2239 | | return 25; |
2240 | | case 1: |
2241 | | // op: rs1 |
2242 | | return 14; |
2243 | | case 2: |
2244 | | // op: simm13 |
2245 | | return 0; |
2246 | | } |
2247 | | break; |
2248 | | } |
2249 | | case SP::LDArr: |
2250 | | case SP::LDDArr: |
2251 | | case SP::LDDFArr: |
2252 | | case SP::LDFArr: |
2253 | | case SP::LDQFArr: |
2254 | | case SP::LDSBArr: |
2255 | | case SP::LDSHArr: |
2256 | | case SP::LDSTUBArr: |
2257 | | case SP::LDSWArr: |
2258 | | case SP::LDUBArr: |
2259 | | case SP::LDUHArr: |
2260 | | case SP::LDXArr: |
2261 | | case SP::SWAPArr: { |
2262 | | switch (OpNum) { |
2263 | | case 0: |
2264 | | // op: rd |
2265 | | return 25; |
2266 | | case 1: |
2267 | | // op: rs1 |
2268 | | return 14; |
2269 | | case 3: |
2270 | | // op: asi |
2271 | | return 5; |
2272 | | case 2: |
2273 | | // op: rs2 |
2274 | | return 0; |
2275 | | } |
2276 | | break; |
2277 | | } |
2278 | | case SP::CASArr: |
2279 | | case SP::CASXArr: { |
2280 | | switch (OpNum) { |
2281 | | case 0: |
2282 | | // op: rd |
2283 | | return 25; |
2284 | | case 1: |
2285 | | // op: rs1 |
2286 | | return 14; |
2287 | | case 4: |
2288 | | // op: asi |
2289 | | return 5; |
2290 | | case 2: |
2291 | | // op: rs2 |
2292 | | return 0; |
2293 | | } |
2294 | | break; |
2295 | | } |
2296 | | case SP::FNOT1: |
2297 | | case SP::FNOT1S: |
2298 | | case SP::FSRC1: |
2299 | | case SP::FSRC1S: |
2300 | | case SP::RDASR: |
2301 | | case SP::RDPR: { |
2302 | | switch (OpNum) { |
2303 | | case 0: |
2304 | | // op: rd |
2305 | | return 25; |
2306 | | case 1: |
2307 | | // op: rs1 |
2308 | | return 14; |
2309 | | } |
2310 | | break; |
2311 | | } |
2312 | | case SP::FABSD: |
2313 | | case SP::FABSQ: |
2314 | | case SP::FABSS: |
2315 | | case SP::FDTOI: |
2316 | | case SP::FDTOQ: |
2317 | | case SP::FDTOS: |
2318 | | case SP::FDTOX: |
2319 | | case SP::FEXPAND: |
2320 | | case SP::FITOD: |
2321 | | case SP::FITOQ: |
2322 | | case SP::FITOS: |
2323 | | case SP::FMOVD: |
2324 | | case SP::FMOVQ: |
2325 | | case SP::FMOVS: |
2326 | | case SP::FNEGD: |
2327 | | case SP::FNEGQ: |
2328 | | case SP::FNEGS: |
2329 | | case SP::FNOT2: |
2330 | | case SP::FNOT2S: |
2331 | | case SP::FPACK16: |
2332 | | case SP::FPACKFIX: |
2333 | | case SP::FQTOD: |
2334 | | case SP::FQTOI: |
2335 | | case SP::FQTOS: |
2336 | | case SP::FQTOX: |
2337 | | case SP::FSQRTD: |
2338 | | case SP::FSQRTQ: |
2339 | | case SP::FSQRTS: |
2340 | | case SP::FSRC2: |
2341 | | case SP::FSRC2S: |
2342 | | case SP::FSTOD: |
2343 | | case SP::FSTOI: |
2344 | | case SP::FSTOQ: |
2345 | | case SP::FSTOX: |
2346 | | case SP::FXTOD: |
2347 | | case SP::FXTOQ: |
2348 | | case SP::FXTOS: |
2349 | | case SP::LZCNT: |
2350 | | case SP::MOVDTOX: |
2351 | | case SP::MOVSTOSW: |
2352 | | case SP::MOVSTOUW: |
2353 | | case SP::MOVWTOS: |
2354 | | case SP::MOVXTOD: |
2355 | | case SP::POPCrr: { |
2356 | | switch (OpNum) { |
2357 | | case 0: |
2358 | | // op: rd |
2359 | | return 25; |
2360 | | case 1: |
2361 | | // op: rs2 |
2362 | | return 0; |
2363 | | } |
2364 | | break; |
2365 | | } |
2366 | | case SP::FMOVD_FCC: |
2367 | | case SP::FMOVD_ICC: |
2368 | | case SP::FMOVD_XCC: |
2369 | | case SP::FMOVQ_FCC: |
2370 | | case SP::FMOVQ_ICC: |
2371 | | case SP::FMOVQ_XCC: |
2372 | | case SP::FMOVS_FCC: |
2373 | | case SP::FMOVS_ICC: |
2374 | | case SP::FMOVS_XCC: |
2375 | | case SP::MOVFCCrr: |
2376 | | case SP::MOVICCrr: |
2377 | | case SP::MOVXCCrr: { |
2378 | | switch (OpNum) { |
2379 | | case 0: |
2380 | | // op: rd |
2381 | | return 25; |
2382 | | case 3: |
2383 | | // op: cond |
2384 | | return 14; |
2385 | | case 1: |
2386 | | // op: rs2 |
2387 | | return 0; |
2388 | | } |
2389 | | break; |
2390 | | } |
2391 | | case SP::MOVFCCri: |
2392 | | case SP::MOVICCri: |
2393 | | case SP::MOVXCCri: { |
2394 | | switch (OpNum) { |
2395 | | case 0: |
2396 | | // op: rd |
2397 | | return 25; |
2398 | | case 3: |
2399 | | // op: cond |
2400 | | return 14; |
2401 | | case 1: |
2402 | | // op: simm11 |
2403 | | return 0; |
2404 | | } |
2405 | | break; |
2406 | | } |
2407 | | case SP::V9FMOVD_FCC: |
2408 | | case SP::V9FMOVQ_FCC: |
2409 | | case SP::V9FMOVS_FCC: { |
2410 | | switch (OpNum) { |
2411 | | case 0: |
2412 | | // op: rd |
2413 | | return 25; |
2414 | | case 4: |
2415 | | // op: cond |
2416 | | return 14; |
2417 | | case 1: |
2418 | | // op: opf_cc |
2419 | | return 11; |
2420 | | case 2: |
2421 | | // op: rs2 |
2422 | | return 0; |
2423 | | } |
2424 | | break; |
2425 | | } |
2426 | | case SP::FONE: |
2427 | | case SP::FONES: |
2428 | | case SP::FZERO: |
2429 | | case SP::FZEROS: |
2430 | | case SP::RDFQ: |
2431 | | case SP::RDPSR: |
2432 | | case SP::RDTBR: |
2433 | | case SP::RDWIM: { |
2434 | | switch (OpNum) { |
2435 | | case 0: |
2436 | | // op: rd |
2437 | | return 25; |
2438 | | } |
2439 | | break; |
2440 | | } |
2441 | | case SP::BINDrr: |
2442 | | case SP::CALLrr: |
2443 | | case SP::FCMPD: |
2444 | | case SP::FCMPD_V9: |
2445 | | case SP::FCMPQ: |
2446 | | case SP::FCMPQ_V9: |
2447 | | case SP::FCMPS: |
2448 | | case SP::FCMPS_V9: |
2449 | | case SP::FLUSHrr: |
2450 | | case SP::LDCSRrr: |
2451 | | case SP::LDFSRrr: |
2452 | | case SP::LDXFSRrr: |
2453 | | case SP::PWRPSRrr: |
2454 | | case SP::RETTrr: |
2455 | | case SP::STCSRrr: |
2456 | | case SP::STDCQrr: |
2457 | | case SP::STDFQrr: |
2458 | | case SP::STFSRrr: |
2459 | | case SP::STXFSRrr: |
2460 | | case SP::WRPSRrr: |
2461 | | case SP::WRTBRrr: |
2462 | | case SP::WRWIMrr: { |
2463 | | switch (OpNum) { |
2464 | | case 0: |
2465 | | // op: rs1 |
2466 | | return 14; |
2467 | | case 1: |
2468 | | // op: rs2 |
2469 | | return 0; |
2470 | | } |
2471 | | break; |
2472 | | } |
2473 | | case SP::BINDri: |
2474 | | case SP::CALLri: |
2475 | | case SP::FLUSHri: |
2476 | | case SP::LDCSRri: |
2477 | | case SP::LDFSRri: |
2478 | | case SP::LDXFSRri: |
2479 | | case SP::PWRPSRri: |
2480 | | case SP::RETTri: |
2481 | | case SP::STCSRri: |
2482 | | case SP::STDCQri: |
2483 | | case SP::STDFQri: |
2484 | | case SP::STFSRri: |
2485 | | case SP::STXFSRri: |
2486 | | case SP::TAIL_CALLri: |
2487 | | case SP::WRPSRri: |
2488 | | case SP::WRTBRri: |
2489 | | case SP::WRWIMri: { |
2490 | | switch (OpNum) { |
2491 | | case 0: |
2492 | | // op: rs1 |
2493 | | return 14; |
2494 | | case 1: |
2495 | | // op: simm13 |
2496 | | return 0; |
2497 | | } |
2498 | | break; |
2499 | | } |
2500 | | case SP::TICCri: |
2501 | | case SP::TRAPri: |
2502 | | case SP::TXCCri: { |
2503 | | switch (OpNum) { |
2504 | | case 0: |
2505 | | // op: rs1 |
2506 | | return 14; |
2507 | | case 2: |
2508 | | // op: cond |
2509 | | return 25; |
2510 | | case 1: |
2511 | | // op: imm |
2512 | | return 0; |
2513 | | } |
2514 | | break; |
2515 | | } |
2516 | | case SP::TICCrr: |
2517 | | case SP::TRAPrr: |
2518 | | case SP::TXCCrr: { |
2519 | | switch (OpNum) { |
2520 | | case 0: |
2521 | | // op: rs1 |
2522 | | return 14; |
2523 | | case 2: |
2524 | | // op: cond |
2525 | | return 25; |
2526 | | case 1: |
2527 | | // op: rs2 |
2528 | | return 0; |
2529 | | } |
2530 | | break; |
2531 | | } |
2532 | | case SP::CMASK8: |
2533 | | case SP::CMASK16: |
2534 | | case SP::CMASK32: { |
2535 | | switch (OpNum) { |
2536 | | case 0: |
2537 | | // op: rs2 |
2538 | | return 0; |
2539 | | } |
2540 | | break; |
2541 | | } |
2542 | | case SP::MEMBARi: |
2543 | | case SP::RET: |
2544 | | case SP::RETL: |
2545 | | case SP::SIR: { |
2546 | | switch (OpNum) { |
2547 | | case 0: |
2548 | | // op: simm13 |
2549 | | return 0; |
2550 | | } |
2551 | | break; |
2552 | | } |
2553 | | case SP::BPICC: |
2554 | | case SP::BPICCA: |
2555 | | case SP::BPICCANT: |
2556 | | case SP::BPICCNT: |
2557 | | case SP::BPXCC: |
2558 | | case SP::BPXCCA: |
2559 | | case SP::BPXCCANT: |
2560 | | case SP::BPXCCNT: |
2561 | | case SP::FBCONDA_V9: |
2562 | | case SP::FBCOND_V9: { |
2563 | | switch (OpNum) { |
2564 | | case 1: |
2565 | | // op: cond |
2566 | | return 25; |
2567 | | case 0: |
2568 | | // op: imm19 |
2569 | | return 0; |
2570 | | } |
2571 | | break; |
2572 | | } |
2573 | | case SP::SETHIi: { |
2574 | | switch (OpNum) { |
2575 | | case 1: |
2576 | | // op: imm22 |
2577 | | return 0; |
2578 | | case 0: |
2579 | | // op: rd |
2580 | | return 25; |
2581 | | } |
2582 | | break; |
2583 | | } |
2584 | | case SP::BPFCC: |
2585 | | case SP::BPFCCA: |
2586 | | case SP::BPFCCANT: |
2587 | | case SP::BPFCCNT: { |
2588 | | switch (OpNum) { |
2589 | | case 2: |
2590 | | // op: cc |
2591 | | return 20; |
2592 | | case 1: |
2593 | | // op: cond |
2594 | | return 25; |
2595 | | case 0: |
2596 | | // op: imm19 |
2597 | | return 0; |
2598 | | } |
2599 | | break; |
2600 | | } |
2601 | | case SP::PREFETCHr: |
2602 | | case SP::STBrr: |
2603 | | case SP::STCrr: |
2604 | | case SP::STDCrr: |
2605 | | case SP::STDFrr: |
2606 | | case SP::STDrr: |
2607 | | case SP::STFrr: |
2608 | | case SP::STHrr: |
2609 | | case SP::STQFrr: |
2610 | | case SP::STXrr: |
2611 | | case SP::STrr: { |
2612 | | switch (OpNum) { |
2613 | | case 2: |
2614 | | // op: rd |
2615 | | return 25; |
2616 | | case 0: |
2617 | | // op: rs1 |
2618 | | return 14; |
2619 | | case 1: |
2620 | | // op: rs2 |
2621 | | return 0; |
2622 | | } |
2623 | | break; |
2624 | | } |
2625 | | case SP::PREFETCHi: |
2626 | | case SP::STAri: |
2627 | | case SP::STBAri: |
2628 | | case SP::STBri: |
2629 | | case SP::STCri: |
2630 | | case SP::STDAri: |
2631 | | case SP::STDCri: |
2632 | | case SP::STDFAri: |
2633 | | case SP::STDFri: |
2634 | | case SP::STDri: |
2635 | | case SP::STFAri: |
2636 | | case SP::STFri: |
2637 | | case SP::STHAri: |
2638 | | case SP::STHri: |
2639 | | case SP::STQFAri: |
2640 | | case SP::STQFri: |
2641 | | case SP::STXAri: |
2642 | | case SP::STXri: |
2643 | | case SP::STri: { |
2644 | | switch (OpNum) { |
2645 | | case 2: |
2646 | | // op: rd |
2647 | | return 25; |
2648 | | case 0: |
2649 | | // op: rs1 |
2650 | | return 14; |
2651 | | case 1: |
2652 | | // op: simm13 |
2653 | | return 0; |
2654 | | } |
2655 | | break; |
2656 | | } |
2657 | | case SP::STArr: |
2658 | | case SP::STBArr: |
2659 | | case SP::STDArr: |
2660 | | case SP::STDFArr: |
2661 | | case SP::STFArr: |
2662 | | case SP::STHArr: |
2663 | | case SP::STQFArr: |
2664 | | case SP::STXArr: { |
2665 | | switch (OpNum) { |
2666 | | case 2: |
2667 | | // op: rd |
2668 | | return 25; |
2669 | | case 0: |
2670 | | // op: rs1 |
2671 | | return 14; |
2672 | | case 3: |
2673 | | // op: asi |
2674 | | return 5; |
2675 | | case 1: |
2676 | | // op: rs2 |
2677 | | return 0; |
2678 | | } |
2679 | | break; |
2680 | | } |
2681 | | } |
2682 | | std::string msg; |
2683 | | raw_string_ostream Msg(msg); |
2684 | | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
2685 | | report_fatal_error(Msg.str().c_str()); |
2686 | | } |
2687 | | |
2688 | | #endif // GET_OPERAND_BIT_OFFSET |
2689 | | |