/src/build/lib/Target/Sparc/SparcGenRegisterInfo.inc

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/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM

namespace llvm {

class MCRegisterClass;
extern const MCRegisterClass SparcMCRegisterClasses[];

namespace SP {
enum {
  NoRegister,
  CANRESTORE = 1,
  CANSAVE = 2,
  CLEANWIN = 3,
  CPQ = 4,
  CPSR = 5,
  CWP = 6,
  FQ = 7,
  FSR = 8,
  GL = 9,
  ICC = 10,
  OTHERWIN = 11,
  PIL = 12,
  PSR = 13,
  PSTATE = 14,
  TBA = 15,
  TBR = 16,
  TICK = 17,
  TL = 18,
  TNPC = 19,
  TPC = 20,
  TSTATE = 21,
  TT = 22,
  VER = 23,
  WIM = 24,
  WSTATE = 25,
  Y = 26,
  ASR1 = 27,
  ASR2 = 28,
  ASR3 = 29,
  ASR4 = 30,
  ASR5 = 31,
  ASR6 = 32,
  ASR7 = 33,
  ASR8 = 34,
  ASR9 = 35,
  ASR10 = 36,
  ASR11 = 37,
  ASR12 = 38,
  ASR13 = 39,
  ASR14 = 40,
  ASR15 = 41,
  ASR16 = 42,
  ASR17 = 43,
  ASR18 = 44,
  ASR19 = 45,
  ASR20 = 46,
  ASR21 = 47,
  ASR22 = 48,
  ASR23 = 49,
  ASR24 = 50,
  ASR25 = 51,
  ASR26 = 52,
  ASR27 = 53,
  ASR28 = 54,
  ASR29 = 55,
  ASR30 = 56,
  ASR31 = 57,
  C0 = 58,
  C1 = 59,
  C2 = 60,
  C3 = 61,
  C4 = 62,
  C5 = 63,
  C6 = 64,
  C7 = 65,
  C8 = 66,
  C9 = 67,
  C10 = 68,
  C11 = 69,
  C12 = 70,
  C13 = 71,
  C14 = 72,
  C15 = 73,
  C16 = 74,
  C17 = 75,
  C18 = 76,
  C19 = 77,
  C20 = 78,
  C21 = 79,
  C22 = 80,
  C23 = 81,
  C24 = 82,
  C25 = 83,
  C26 = 84,
  C27 = 85,
  C28 = 86,
  C29 = 87,
  C30 = 88,
  C31 = 89,
  D0 = 90,
  D1 = 91,
  D2 = 92,
  D3 = 93,
  D4 = 94,
  D5 = 95,
  D6 = 96,
  D7 = 97,
  D8 = 98,
  D9 = 99,
  D10 = 100,
  D11 = 101,
  D12 = 102,
  D13 = 103,
  D14 = 104,
  D15 = 105,
  D16 = 106,
  D17 = 107,
  D18 = 108,
  D19 = 109,
  D20 = 110,
  D21 = 111,
  D22 = 112,
  D23 = 113,
  D24 = 114,
  D25 = 115,
  D26 = 116,
  D27 = 117,
  D28 = 118,
  D29 = 119,
  D30 = 120,
  D31 = 121,
  F0 = 122,
  F1 = 123,
  F2 = 124,
  F3 = 125,
  F4 = 126,
  F5 = 127,
  F6 = 128,
  F7 = 129,
  F8 = 130,
  F9 = 131,
  F10 = 132,
  F11 = 133,
  F12 = 134,
  F13 = 135,
  F14 = 136,
  F15 = 137,
  F16 = 138,
  F17 = 139,
  F18 = 140,
  F19 = 141,
  F20 = 142,
  F21 = 143,
  F22 = 144,
  F23 = 145,
  F24 = 146,
  F25 = 147,
  F26 = 148,
  F27 = 149,
  F28 = 150,
  F29 = 151,
  F30 = 152,
  F31 = 153,
  FCC0 = 154,
  FCC1 = 155,
  FCC2 = 156,
  FCC3 = 157,
  G0 = 158,
  G1 = 159,
  G2 = 160,
  G3 = 161,
  G4 = 162,
  G5 = 163,
  G6 = 164,
  G7 = 165,
  I0 = 166,
  I1 = 167,
  I2 = 168,
  I3 = 169,
  I4 = 170,
  I5 = 171,
  I6 = 172,
  I7 = 173,
  L0 = 174,
  L1 = 175,
  L2 = 176,
  L3 = 177,
  L4 = 178,
  L5 = 179,
  L6 = 180,
  L7 = 181,
  O0 = 182,
  O1 = 183,
  O2 = 184,
  O3 = 185,
  O4 = 186,
  O5 = 187,
  O6 = 188,
  O7 = 189,
  Q0 = 190,
  Q1 = 191,
  Q2 = 192,
  Q3 = 193,
  Q4 = 194,
  Q5 = 195,
  Q6 = 196,
  Q7 = 197,
  Q8 = 198,
  Q9 = 199,
  Q10 = 200,
  Q11 = 201,
  Q12 = 202,
  Q13 = 203,
  Q14 = 204,
  Q15 = 205,
  C0_C1 = 206,
  C2_C3 = 207,
  C4_C5 = 208,
  C6_C7 = 209,
  C8_C9 = 210,
  C10_C11 = 211,
  C12_C13 = 212,
  C14_C15 = 213,
  C16_C17 = 214,
  C18_C19 = 215,
  C20_C21 = 216,
  C22_C23 = 217,
  C24_C25 = 218,
  C26_C27 = 219,
  C28_C29 = 220,
  C30_C31 = 221,
  G0_G1 = 222,
  G2_G3 = 223,
  G4_G5 = 224,
  G6_G7 = 225,
  I0_I1 = 226,
  I2_I3 = 227,
  I4_I5 = 228,
  I6_I7 = 229,
  L0_L1 = 230,
  L2_L3 = 231,
  L4_L5 = 232,
  L6_L7 = 233,
  O0_O1 = 234,
  O2_O3 = 235,
  O4_O5 = 236,
  O6_O7 = 237,
  NUM_TARGET_REGS // 238
};
} // end namespace SP

// Register classes

namespace SP {
enum {
  FCCRegsRegClassID = 0,
  ASRRegsRegClassID = 1,
  CoprocRegsRegClassID = 2,
  FPRegsRegClassID = 3,
  IntRegsRegClassID = 4,
  DFPRegsRegClassID = 5,
  I64RegsRegClassID = 6,
  PRRegsRegClassID = 7,
  CoprocPairRegClassID = 8,
  IntPairRegClassID = 9,
  LowDFPRegsRegClassID = 10,
  PRRegs_and_ASRRegsRegClassID = 11,
  QFPRegsRegClassID = 12,
  LowQFPRegsRegClassID = 13,

};
} // end namespace SP


// Register alternate name indices

namespace SP {
enum {
  NoRegAltName, // 0
  RegNamesStateReg, // 1
  NUM_TARGET_REG_ALT_NAMES = 2
};
} // end namespace SP


// Subregister indices

namespace SP {
enum : uint16_t {
  NoSubRegister,
  sub_even, // 1
  sub_even64, // 2
  sub_odd,  // 3
  sub_odd64,  // 4
  sub_odd64_then_sub_even,  // 5
  sub_odd64_then_sub_odd, // 6
  NUM_TARGET_SUBREGS
};
} // end namespace SP

// Register pressure sets enum.
namespace SP {
enum RegisterPressureSets {
  PRRegs_and_ASRRegs = 0,
  FCCRegs = 1,
  PRRegs = 2,
  FPRegs = 3,
  IntRegs = 4,
  DFPRegs = 5,
};
} // end namespace SP

} // end namespace llvm

#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC

namespace llvm {

extern const int16_t SparcRegDiffLists[] = {
  /* 0 */ -148, 1, 0,
  /* 3 */ -147, 1, 0,
  /* 6 */ -146, 1, 0,
  /* 9 */ -145, 1, 0,
  /* 12 */ -144, 1, 0,
  /* 15 */ -143, 1, 0,
  /* 18 */ -142, 1, 0,
  /* 21 */ -141, 1, 0,
  /* 24 */ -140, 1, 0,
  /* 27 */ -139, 1, 0,
  /* 30 */ -138, 1, 0,
  /* 33 */ -137, 1, 0,
  /* 36 */ -136, 1, 0,
  /* 39 */ -135, 1, 0,
  /* 42 */ -134, 1, 0,
  /* 45 */ -133, 1, 0,
  /* 48 */ -92, 1, 0,
  /* 51 */ -91, 1, 0,
  /* 54 */ -90, 1, 0,
  /* 57 */ -89, 1, 0,
  /* 60 */ -88, 1, 0,
  /* 63 */ -87, 1, 0,
  /* 66 */ -86, 1, 0,
  /* 69 */ -85, 1, 0,
  /* 72 */ -64, 1, 0,
  /* 75 */ -63, 1, 0,
  /* 78 */ -62, 1, 0,
  /* 81 */ -61, 1, 0,
  /* 84 */ -60, 1, 0,
  /* 87 */ -59, 1, 0,
  /* 90 */ -58, 1, 0,
  /* 93 */ -57, 1, 0,
  /* 96 */ -56, 1, 0,
  /* 99 */ -55, 1, 0,
  /* 102 */ -54, 1, 0,
  /* 105 */ -53, 1, 0,
  /* 108 */ -52, 1, 0,
  /* 111 */ -51, 1, 0,
  /* 114 */ -50, 1, 0,
  /* 117 */ -49, 1, 0,
  /* 120 */ 1, 1, 1, 0,
  /* 124 */ 32, 1, 0,
  /* 127 */ -100, 32, 1, -32, 33, 1, 0,
  /* 134 */ 34, 1, 0,
  /* 137 */ -99, 34, 1, -34, 35, 1, 0,
  /* 144 */ 36, 1, 0,
  /* 147 */ -98, 36, 1, -36, 37, 1, 0,
  /* 154 */ 38, 1, 0,
  /* 157 */ -97, 38, 1, -38, 39, 1, 0,
  /* 164 */ 40, 1, 0,
  /* 167 */ -96, 40, 1, -40, 41, 1, 0,
  /* 174 */ 42, 1, 0,
  /* 177 */ -95, 42, 1, -42, 43, 1, 0,
  /* 184 */ 44, 1, 0,
  /* 187 */ -94, 44, 1, -44, 45, 1, 0,
  /* 194 */ 46, 1, 0,
  /* 197 */ -93, 46, 1, -46, 47, 1, 0,
  /* 204 */ 48, 0,
  /* 206 */ 49, 0,
  /* 208 */ 50, 0,
  /* 210 */ 51, 0,
  /* 212 */ 52, 0,
  /* 214 */ 53, 0,
  /* 216 */ 54, 0,
  /* 218 */ 55, 0,
  /* 220 */ 56, 0,
  /* 222 */ 57, 0,
  /* 224 */ 58, 0,
  /* 226 */ 59, 0,
  /* 228 */ 60, 0,
  /* 230 */ 61, 0,
  /* 232 */ 62, 0,
  /* 234 */ 63, 0,
  /* 236 */ 64, 0,
  /* 238 */ 84, 0,
  /* 240 */ 85, 0,
  /* 242 */ 86, 0,
  /* 244 */ 87, 0,
  /* 246 */ 88, 0,
  /* 248 */ 89, 0,
  /* 250 */ 90, 0,
  /* 252 */ 91, 0,
  /* 254 */ -48, 92, 0,
  /* 257 */ -47, 92, 0,
  /* 260 */ -47, 93, 0,
  /* 263 */ -46, 93, 0,
  /* 266 */ -45, 93, 0,
  /* 269 */ -45, 94, 0,
  /* 272 */ -44, 94, 0,
  /* 275 */ -43, 94, 0,
  /* 278 */ -43, 95, 0,
  /* 281 */ -42, 95, 0,
  /* 284 */ -41, 95, 0,
  /* 287 */ -41, 96, 0,
  /* 290 */ -40, 96, 0,
  /* 293 */ -39, 96, 0,
  /* 296 */ -39, 97, 0,
  /* 299 */ -38, 97, 0,
  /* 302 */ -37, 97, 0,
  /* 305 */ -37, 98, 0,
  /* 308 */ -36, 98, 0,
  /* 311 */ -35, 98, 0,
  /* 314 */ -35, 99, 0,
  /* 317 */ -34, 99, 0,
  /* 320 */ -33, 99, 0,
  /* 323 */ -33, 100, 0,
  /* 326 */ -32, 100, 0,
  /* 329 */ 132, 0,
  /* 331 */ 133, 0,
  /* 333 */ 134, 0,
  /* 335 */ 135, 0,
  /* 337 */ 136, 0,
  /* 339 */ 137, 0,
  /* 341 */ 138, 0,
  /* 343 */ 139, 0,
  /* 345 */ 140, 0,
  /* 347 */ 141, 0,
  /* 349 */ 142, 0,
  /* 351 */ 143, 0,
  /* 353 */ 144, 0,
  /* 355 */ 145, 0,
  /* 357 */ 146, 0,
  /* 359 */ 147, 0,
  /* 361 */ 148, 0,
};

extern const LaneBitmask SparcLaneMaskLists[] = {
  /* 0 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask::getAll(),
  /* 3 */ LaneBitmask(0x0000000000000001), LaneBitmask(0x0000000000000002), LaneBitmask(0x0000000000000004), LaneBitmask(0x0000000000000008), LaneBitmask::getAll(),
  /* 8 */ LaneBitmask(0x0000000000000003), LaneBitmask(0x000000000000000C), LaneBitmask::getAll(),
  /* 11 */ LaneBitmask(0xFFFFFFFFFFFFFFFF), LaneBitmask::getAll(),
};

extern const uint16_t SparcSubRegIdxLists[] = {
  /* 0 */ 1, 3, 0,
  /* 3 */ 2, 4, 0,
  /* 6 */ 2, 1, 3, 4, 5, 6, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 32 },  // sub_even
  { 0, 64 },  // sub_even64
  { 32, 32 }, // sub_odd
  { 64, 64 }, // sub_odd64
  { 64, 32 }, // sub_odd64_then_sub_even
  { 96, 32 }, // sub_odd64_then_sub_odd
};


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char SparcRegStrings[] = {
  /* 0 */ "C10\0"
  /* 4 */ "D10\0"
  /* 8 */ "F10\0"
  /* 12 */ "Q10\0"
  /* 16 */ "ASR10\0"
  /* 22 */ "C20\0"
  /* 26 */ "D20\0"
  /* 30 */ "F20\0"
  /* 34 */ "ASR20\0"
  /* 40 */ "C30\0"
  /* 44 */ "D30\0"
  /* 48 */ "F30\0"
  /* 52 */ "ASR30\0"
  /* 58 */ "FCC0\0"
  /* 63 */ "D0\0"
  /* 66 */ "F0\0"
  /* 69 */ "G0\0"
  /* 72 */ "I0\0"
  /* 75 */ "L0\0"
  /* 78 */ "O0\0"
  /* 81 */ "Q0\0"
  /* 84 */ "C10_C11\0"
  /* 92 */ "D11\0"
  /* 96 */ "F11\0"
  /* 100 */ "Q11\0"
  /* 104 */ "ASR11\0"
  /* 110 */ "C20_C21\0"
  /* 118 */ "D21\0"
  /* 122 */ "F21\0"
  /* 126 */ "ASR21\0"
  /* 132 */ "C30_C31\0"
  /* 140 */ "D31\0"
  /* 144 */ "F31\0"
  /* 148 */ "ASR31\0"
  /* 154 */ "FCC1\0"
  /* 159 */ "C0_C1\0"
  /* 165 */ "D1\0"
  /* 168 */ "F1\0"
  /* 171 */ "G0_G1\0"
  /* 177 */ "I0_I1\0"
  /* 183 */ "L0_L1\0"
  /* 189 */ "O0_O1\0"
  /* 195 */ "Q1\0"
  /* 198 */ "ASR1\0"
  /* 203 */ "C12\0"
  /* 207 */ "D12\0"
  /* 211 */ "F12\0"
  /* 215 */ "Q12\0"
  /* 219 */ "ASR12\0"
  /* 225 */ "C22\0"
  /* 229 */ "D22\0"
  /* 233 */ "F22\0"
  /* 237 */ "ASR22\0"
  /* 243 */ "FCC2\0"
  /* 248 */ "D2\0"
  /* 251 */ "F2\0"
  /* 254 */ "G2\0"
  /* 257 */ "I2\0"
  /* 260 */ "L2\0"
  /* 263 */ "O2\0"
  /* 266 */ "Q2\0"
  /* 269 */ "ASR2\0"
  /* 274 */ "C12_C13\0"
  /* 282 */ "D13\0"
  /* 286 */ "F13\0"
  /* 290 */ "Q13\0"
  /* 294 */ "ASR13\0"
  /* 300 */ "C22_C23\0"
  /* 308 */ "D23\0"
  /* 312 */ "F23\0"
  /* 316 */ "ASR23\0"
  /* 322 */ "FCC3\0"
  /* 327 */ "C2_C3\0"
  /* 333 */ "D3\0"
  /* 336 */ "F3\0"
  /* 339 */ "G2_G3\0"
  /* 345 */ "I2_I3\0"
  /* 351 */ "L2_L3\0"
  /* 357 */ "O2_O3\0"
  /* 363 */ "Q3\0"
  /* 366 */ "ASR3\0"
  /* 371 */ "C14\0"
  /* 375 */ "D14\0"
  /* 379 */ "F14\0"
  /* 383 */ "Q14\0"
  /* 387 */ "ASR14\0"
  /* 393 */ "C24\0"
  /* 397 */ "D24\0"
  /* 401 */ "F24\0"
  /* 405 */ "ASR24\0"
  /* 411 */ "C4\0"
  /* 414 */ "D4\0"
  /* 417 */ "F4\0"
  /* 420 */ "G4\0"
  /* 423 */ "I4\0"
  /* 426 */ "L4\0"
  /* 429 */ "O4\0"
  /* 432 */ "Q4\0"
  /* 435 */ "ASR4\0"
  /* 440 */ "C14_C15\0"
  /* 448 */ "D15\0"
  /* 452 */ "F15\0"
  /* 456 */ "Q15\0"
  /* 460 */ "ASR15\0"
  /* 466 */ "C24_C25\0"
  /* 474 */ "D25\0"
  /* 478 */ "F25\0"
  /* 482 */ "ASR25\0"
  /* 488 */ "C4_C5\0"
  /* 494 */ "D5\0"
  /* 497 */ "F5\0"
  /* 500 */ "G4_G5\0"
  /* 506 */ "I4_I5\0"
  /* 512 */ "L4_L5\0"
  /* 518 */ "O4_O5\0"
  /* 524 */ "Q5\0"
  /* 527 */ "ASR5\0"
  /* 532 */ "C16\0"
  /* 536 */ "D16\0"
  /* 540 */ "F16\0"
  /* 544 */ "ASR16\0"
  /* 550 */ "C26\0"
  /* 554 */ "D26\0"
  /* 558 */ "F26\0"
  /* 562 */ "ASR26\0"
  /* 568 */ "C6\0"
  /* 571 */ "D6\0"
  /* 574 */ "F6\0"
  /* 577 */ "G6\0"
  /* 580 */ "I6\0"
  /* 583 */ "L6\0"
  /* 586 */ "O6\0"
  /* 589 */ "Q6\0"
  /* 592 */ "ASR6\0"
  /* 597 */ "C16_C17\0"
  /* 605 */ "D17\0"
  /* 609 */ "F17\0"
  /* 613 */ "ASR17\0"
  /* 619 */ "C26_C27\0"
  /* 627 */ "D27\0"
  /* 631 */ "F27\0"
  /* 635 */ "ASR27\0"
  /* 641 */ "C6_C7\0"
  /* 647 */ "D7\0"
  /* 650 */ "F7\0"
  /* 653 */ "G6_G7\0"
  /* 659 */ "I6_I7\0"
  /* 665 */ "L6_L7\0"
  /* 671 */ "O6_O7\0"
  /* 677 */ "Q7\0"
  /* 680 */ "ASR7\0"
  /* 685 */ "C18\0"
  /* 689 */ "D18\0"
  /* 693 */ "F18\0"
  /* 697 */ "ASR18\0"
  /* 703 */ "C28\0"
  /* 707 */ "D28\0"
  /* 711 */ "F28\0"
  /* 715 */ "ASR28\0"
  /* 721 */ "C8\0"
  /* 724 */ "D8\0"
  /* 727 */ "F8\0"
  /* 730 */ "Q8\0"
  /* 733 */ "ASR8\0"
  /* 738 */ "C18_C19\0"
  /* 746 */ "D19\0"
  /* 750 */ "F19\0"
  /* 754 */ "ASR19\0"
  /* 760 */ "C28_C29\0"
  /* 768 */ "D29\0"
  /* 772 */ "F29\0"
  /* 776 */ "ASR29\0"
  /* 782 */ "C8_C9\0"
  /* 788 */ "D9\0"
  /* 791 */ "F9\0"
  /* 794 */ "Q9\0"
  /* 797 */ "ASR9\0"
  /* 802 */ "TBA\0"
  /* 806 */ "ICC\0"
  /* 810 */ "TNPC\0"
  /* 815 */ "TPC\0"
  /* 819 */ "CANRESTORE\0"
  /* 830 */ "PSTATE\0"
  /* 837 */ "TSTATE\0"
  /* 844 */ "WSTATE\0"
  /* 851 */ "CANSAVE\0"
  /* 859 */ "TICK\0"
  /* 864 */ "GL\0"
  /* 867 */ "PIL\0"
  /* 871 */ "TL\0"
  /* 874 */ "WIM\0"
  /* 878 */ "CLEANWIN\0"
  /* 887 */ "OTHERWIN\0"
  /* 896 */ "CWP\0"
  /* 900 */ "FQ\0"
  /* 903 */ "CPQ\0"
  /* 907 */ "TBR\0"
  /* 911 */ "VER\0"
  /* 915 */ "FSR\0"
  /* 919 */ "CPSR\0"
  /* 924 */ "TT\0"
  /* 927 */ "Y\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterDesc SparcRegDesc[] = { // Descriptors
  { 3, 0, 0, 0, 0, 0 },
  { 819, 2, 2, 2, 8192, 11 },
  { 851, 2, 2, 2, 8193, 11 },
  { 878, 2, 2, 2, 8194, 11 },
  { 903, 2, 2, 2, 8195, 11 },
  { 919, 2, 2, 2, 8196, 11 },
  { 896, 2, 2, 2, 8197, 11 },
  { 900, 2, 2, 2, 8198, 11 },
  { 915, 2, 2, 2, 8199, 11 },
  { 864, 2, 2, 2, 8200, 11 },
  { 806, 2, 2, 2, 8201, 11 },
  { 887, 2, 2, 2, 8202, 11 },
  { 867, 2, 2, 2, 8203, 11 },
  { 920, 2, 2, 2, 8204, 11 },
  { 830, 2, 2, 2, 8205, 11 },
  { 802, 2, 2, 2, 8206, 11 },
  { 907, 2, 2, 2, 8207, 11 },
  { 859, 2, 2, 2, 8208, 11 },
  { 871, 2, 2, 2, 8209, 11 },
  { 810, 2, 2, 2, 8210, 11 },
  { 815, 2, 2, 2, 8211, 11 },
  { 837, 2, 2, 2, 8212, 11 },
  { 924, 2, 2, 2, 8213, 11 },
  { 911, 2, 2, 2, 8214, 11 },
  { 874, 2, 2, 2, 8215, 11 },
  { 844, 2, 2, 2, 8216, 11 },
  { 927, 2, 2, 2, 8217, 11 },
  { 198, 2, 2, 2, 8218, 11 },
  { 269, 2, 2, 2, 8219, 11 },
  { 366, 2, 2, 2, 8220, 11 },
  { 435, 2, 2, 2, 8221, 11 },
  { 527, 2, 2, 2, 8222, 11 },
  { 592, 2, 2, 2, 8223, 11 },
  { 680, 2, 2, 2, 8224, 11 },
  { 733, 2, 2, 2, 8225, 11 },
  { 797, 2, 2, 2, 8226, 11 },
  { 16, 2, 2, 2, 8227, 11 },
  { 104, 2, 2, 2, 8228, 11 },
  { 219, 2, 2, 2, 8229, 11 },
  { 294, 2, 2, 2, 8230, 11 },
  { 387, 2, 2, 2, 8231, 11 },
  { 460, 2, 2, 2, 8232, 11 },
  { 544, 2, 2, 2, 8233, 11 },
  { 613, 2, 2, 2, 8234, 11 },
  { 697, 2, 2, 2, 8235, 11 },
  { 754, 2, 2, 2, 8236, 11 },
  { 34, 2, 2, 2, 8237, 11 },
  { 126, 2, 2, 2, 8238, 11 },
  { 237, 2, 2, 2, 8239, 11 },
  { 316, 2, 2, 2, 8240, 11 },
  { 405, 2, 2, 2, 8241, 11 },
  { 482, 2, 2, 2, 8242, 11 },
  { 562, 2, 2, 2, 8243, 11 },
  { 635, 2, 2, 2, 8244, 11 },
  { 715, 2, 2, 2, 8245, 11 },
  { 776, 2, 2, 2, 8246, 11 },
  { 52, 2, 2, 2, 8247, 11 },
  { 148, 2, 2, 2, 8248, 11 },
  { 60, 2, 361, 2, 8249, 11 },
  { 156, 2, 359, 2, 8250, 11 },
  { 245, 2, 359, 2, 8251, 11 },
  { 324, 2, 357, 2, 8252, 11 },
  { 411, 2, 357, 2, 8253, 11 },
  { 491, 2, 355, 2, 8254, 11 },
  { 568, 2, 355, 2, 8255, 11 },
  { 644, 2, 353, 2, 8256, 11 },
  { 721, 2, 353, 2, 8257, 11 },
  { 785, 2, 351, 2, 8258, 11 },
  { 0, 2, 351, 2, 8259, 11 },
  { 88, 2, 349, 2, 8260, 11 },
  { 203, 2, 349, 2, 8261, 11 },
  { 278, 2, 347, 2, 8262, 11 },
  { 371, 2, 347, 2, 8263, 11 },
  { 444, 2, 345, 2, 8264, 11 },
  { 532, 2, 345, 2, 8265, 11 },
  { 601, 2, 343, 2, 8266, 11 },
  { 685, 2, 343, 2, 8267, 11 },
  { 742, 2, 341, 2, 8268, 11 },
  { 22, 2, 341, 2, 8269, 11 },
  { 114, 2, 339, 2, 8270, 11 },
  { 225, 2, 339, 2, 8271, 11 },
  { 304, 2, 337, 2, 8272, 11 },
  { 393, 2, 337, 2, 8273, 11 },
  { 470, 2, 335, 2, 8274, 11 },
  { 550, 2, 335, 2, 8275, 11 },
  { 623, 2, 333, 2, 8276, 11 },
  { 703, 2, 333, 2, 8277, 11 },
  { 764, 2, 331, 2, 8278, 11 },
  { 40, 2, 331, 2, 8279, 11 },
  { 136, 2, 329, 2, 8280, 11 },
  { 63, 124, 324, 0, 4185, 0 },
  { 165, 131, 315, 0, 4187, 0 },
  { 248, 134, 315, 0, 4189, 0 },
  { 333, 141, 306, 0, 4191, 0 },
  { 414, 144, 306, 0, 4193, 0 },
  { 494, 151, 297, 0, 4195, 0 },
  { 571, 154, 297, 0, 4197, 0 },
  { 647, 161, 288, 0, 4199, 0 },
  { 724, 164, 288, 0, 4201, 0 },
  { 788, 171, 279, 0, 4203, 0 },
  { 4, 174, 279, 0, 4205, 0 },
  { 92, 181, 270, 0, 4207, 0 },
  { 207, 184, 270, 0, 4209, 0 },
  { 282, 191, 261, 0, 4211, 0 },
  { 375, 194, 261, 0, 4213, 0 },
  { 448, 201, 255, 0, 4215, 0 },
  { 536, 2, 255, 2, 8313, 11 },
  { 605, 2, 252, 2, 8314, 11 },
  { 689, 2, 252, 2, 8315, 11 },
  { 746, 2, 250, 2, 8316, 11 },
  { 26, 2, 250, 2, 8317, 11 },
  { 118, 2, 248, 2, 8318, 11 },
  { 229, 2, 248, 2, 8319, 11 },
  { 308, 2, 246, 2, 8320, 11 },
  { 397, 2, 246, 2, 8321, 11 },
  { 474, 2, 244, 2, 8322, 11 },
  { 554, 2, 244, 2, 8323, 11 },
  { 627, 2, 242, 2, 8324, 11 },
  { 707, 2, 242, 2, 8325, 11 },
  { 768, 2, 240, 2, 8326, 11 },
  { 44, 2, 240, 2, 8327, 11 },
  { 140, 2, 238, 2, 8328, 11 },
  { 66, 2, 326, 2, 8281, 11 },
  { 168, 2, 323, 2, 8282, 11 },
  { 251, 2, 320, 2, 8283, 11 },
  { 336, 2, 317, 2, 8284, 11 },
  { 417, 2, 317, 2, 8285, 11 },
  { 497, 2, 314, 2, 8286, 11 },
  { 574, 2, 311, 2, 8287, 11 },
  { 650, 2, 308, 2, 8288, 11 },
  { 727, 2, 308, 2, 8289, 11 },
  { 791, 2, 305, 2, 8290, 11 },
  { 8, 2, 302, 2, 8291, 11 },
  { 96, 2, 299, 2, 8292, 11 },
  { 211, 2, 299, 2, 8293, 11 },
  { 286, 2, 296, 2, 8294, 11 },
  { 379, 2, 293, 2, 8295, 11 },
  { 452, 2, 290, 2, 8296, 11 },
  { 540, 2, 290, 2, 8297, 11 },
  { 609, 2, 287, 2, 8298, 11 },
  { 693, 2, 284, 2, 8299, 11 },
  { 750, 2, 281, 2, 8300, 11 },
  { 30, 2, 281, 2, 8301, 11 },
  { 122, 2, 278, 2, 8302, 11 },
  { 233, 2, 275, 2, 8303, 11 },
  { 312, 2, 272, 2, 8304, 11 },
  { 401, 2, 272, 2, 8305, 11 },
  { 478, 2, 269, 2, 8306, 11 },
  { 558, 2, 266, 2, 8307, 11 },
  { 631, 2, 263, 2, 8308, 11 },
  { 711, 2, 263, 2, 8309, 11 },
  { 772, 2, 260, 2, 8310, 11 },
  { 48, 2, 257, 2, 8311, 11 },
  { 144, 2, 254, 2, 8312, 11 },
  { 58, 2, 2, 2, 8329, 11 },
  { 154, 2, 2, 2, 8330, 11 },
  { 243, 2, 2, 2, 8331, 11 },
  { 322, 2, 2, 2, 8332, 11 },
  { 69, 2, 236, 2, 8333, 11 },
  { 174, 2, 234, 2, 8334, 11 },
  { 254, 2, 234, 2, 8335, 11 },
  { 342, 2, 232, 2, 8336, 11 },
  { 420, 2, 232, 2, 8337, 11 },
  { 503, 2, 230, 2, 8338, 11 },
  { 577, 2, 230, 2, 8339, 11 },
  { 656, 2, 228, 2, 8340, 11 },
  { 72, 2, 228, 2, 8341, 11 },
  { 180, 2, 226, 2, 8342, 11 },
  { 257, 2, 226, 2, 8343, 11 },
  { 348, 2, 224, 2, 8344, 11 },
  { 423, 2, 224, 2, 8345, 11 },
  { 509, 2, 222, 2, 8346, 11 },
  { 580, 2, 222, 2, 8347, 11 },
  { 662, 2, 220, 2, 8348, 11 },
  { 75, 2, 220, 2, 8349, 11 },
  { 186, 2, 218, 2, 8350, 11 },
  { 260, 2, 218, 2, 8351, 11 },
  { 354, 2, 216, 2, 8352, 11 },
  { 426, 2, 216, 2, 8353, 11 },
  { 515, 2, 214, 2, 8354, 11 },
  { 583, 2, 214, 2, 8355, 11 },
  { 668, 2, 212, 2, 8356, 11 },
  { 78, 2, 212, 2, 8357, 11 },
  { 192, 2, 210, 2, 8358, 11 },
  { 263, 2, 210, 2, 8359, 11 },
  { 360, 2, 208, 2, 8360, 11 },
  { 429, 2, 208, 2, 8361, 11 },
  { 521, 2, 206, 2, 8362, 11 },
  { 586, 2, 206, 2, 8363, 11 },
  { 674, 2, 204, 2, 8364, 11 },
  { 81, 127, 2, 6, 491609, 3 },
  { 195, 137, 2, 6, 491613, 3 },
  { 266, 147, 2, 6, 491617, 3 },
  { 363, 157, 2, 6, 491621, 3 },
  { 432, 167, 2, 6, 491625, 3 },
  { 524, 177, 2, 6, 491629, 3 },
  { 589, 187, 2, 6, 491633, 3 },
  { 677, 197, 2, 6, 491637, 3 },
  { 730, 48, 2, 3, 4217, 8 },
  { 794, 51, 2, 3, 4219, 8 },
  { 12, 54, 2, 3, 4221, 8 },
  { 100, 57, 2, 3, 4223, 8 },
  { 215, 60, 2, 3, 4225, 8 },
  { 290, 63, 2, 3, 4227, 8 },
  { 383, 66, 2, 3, 4229, 8 },
  { 456, 69, 2, 3, 4231, 8 },
  { 159, 0, 2, 0, 4153, 0 },
  { 327, 3, 2, 0, 4155, 0 },
  { 488, 6, 2, 0, 4157, 0 },
  { 641, 9, 2, 0, 4159, 0 },
  { 782, 12, 2, 0, 4161, 0 },
  { 84, 15, 2, 0, 4163, 0 },
  { 274, 18, 2, 0, 4165, 0 },
  { 440, 21, 2, 0, 4167, 0 },
  { 597, 24, 2, 0, 4169, 0 },
  { 738, 27, 2, 0, 4171, 0 },
  { 110, 30, 2, 0, 4173, 0 },
  { 300, 33, 2, 0, 4175, 0 },
  { 466, 36, 2, 0, 4177, 0 },
  { 619, 39, 2, 0, 4179, 0 },
  { 760, 42, 2, 0, 4181, 0 },
  { 132, 45, 2, 0, 4183, 0 },
  { 171, 72, 2, 0, 4237, 0 },
  { 339, 75, 2, 0, 4239, 0 },
  { 500, 78, 2, 0, 4241, 0 },
  { 653, 81, 2, 0, 4243, 0 },
  { 177, 84, 2, 0, 4245, 0 },
  { 345, 87, 2, 0, 4247, 0 },
  { 506, 90, 2, 0, 4249, 0 },
  { 659, 93, 2, 0, 4251, 0 },
  { 183, 96, 2, 0, 4253, 0 },
  { 351, 99, 2, 0, 4255, 0 },
  { 512, 102, 2, 0, 4257, 0 },
  { 665, 105, 2, 0, 4259, 0 },
  { 189, 108, 2, 0, 4261, 0 },
  { 357, 111, 2, 0, 4263, 0 },
  { 518, 114, 2, 0, 4265, 0 },
  { 671, 117, 2, 0, 4267, 0 },
};

extern const MCPhysReg SparcRegUnitRoots[][2] = {
  { SP::CANRESTORE },
  { SP::CANSAVE },
  { SP::CLEANWIN },
  { SP::CPQ },
  { SP::CPSR },
  { SP::CWP },
  { SP::FQ },
  { SP::FSR },
  { SP::GL },
  { SP::ICC },
  { SP::OTHERWIN },
  { SP::PIL },
  { SP::PSR },
  { SP::PSTATE },
  { SP::TBA },
  { SP::TBR },
  { SP::TICK },
  { SP::TL },
  { SP::TNPC },
  { SP::TPC },
  { SP::TSTATE },
  { SP::TT },
  { SP::VER },
  { SP::WIM },
  { SP::WSTATE },
  { SP::Y },
  { SP::ASR1 },
  { SP::ASR2 },
  { SP::ASR3 },
  { SP::ASR4 },
  { SP::ASR5 },
  { SP::ASR6 },
  { SP::ASR7 },
  { SP::ASR8 },
  { SP::ASR9 },
  { SP::ASR10 },
  { SP::ASR11 },
  { SP::ASR12 },
  { SP::ASR13 },
  { SP::ASR14 },
  { SP::ASR15 },
  { SP::ASR16 },
  { SP::ASR17 },
  { SP::ASR18 },
  { SP::ASR19 },
  { SP::ASR20 },
  { SP::ASR21 },
  { SP::ASR22 },
  { SP::ASR23 },
  { SP::ASR24 },
  { SP::ASR25 },
  { SP::ASR26 },
  { SP::ASR27 },
  { SP::ASR28 },
  { SP::ASR29 },
  { SP::ASR30 },
  { SP::ASR31 },
  { SP::C0 },
  { SP::C1 },
  { SP::C2 },
  { SP::C3 },
  { SP::C4 },
  { SP::C5 },
  { SP::C6 },
  { SP::C7 },
  { SP::C8 },
  { SP::C9 },
  { SP::C10 },
  { SP::C11 },
  { SP::C12 },
  { SP::C13 },
  { SP::C14 },
  { SP::C15 },
  { SP::C16 },
  { SP::C17 },
  { SP::C18 },
  { SP::C19 },
  { SP::C20 },
  { SP::C21 },
  { SP::C22 },
  { SP::C23 },
  { SP::C24 },
  { SP::C25 },
  { SP::C26 },
  { SP::C27 },
  { SP::C28 },
  { SP::C29 },
  { SP::C30 },
  { SP::C31 },
  { SP::F0 },
  { SP::F1 },
  { SP::F2 },
  { SP::F3 },
  { SP::F4 },
  { SP::F5 },
  { SP::F6 },
  { SP::F7 },
  { SP::F8 },
  { SP::F9 },
  { SP::F10 },
  { SP::F11 },
  { SP::F12 },
  { SP::F13 },
  { SP::F14 },
  { SP::F15 },
  { SP::F16 },
  { SP::F17 },
  { SP::F18 },
  { SP::F19 },
  { SP::F20 },
  { SP::F21 },
  { SP::F22 },
  { SP::F23 },
  { SP::F24 },
  { SP::F25 },
  { SP::F26 },
  { SP::F27 },
  { SP::F28 },
  { SP::F29 },
  { SP::F30 },
  { SP::F31 },
  { SP::D16 },
  { SP::D17 },
  { SP::D18 },
  { SP::D19 },
  { SP::D20 },
  { SP::D21 },
  { SP::D22 },
  { SP::D23 },
  { SP::D24 },
  { SP::D25 },
  { SP::D26 },
  { SP::D27 },
  { SP::D28 },
  { SP::D29 },
  { SP::D30 },
  { SP::D31 },
  { SP::FCC0 },
  { SP::FCC1 },
  { SP::FCC2 },
  { SP::FCC3 },
  { SP::G0 },
  { SP::G1 },
  { SP::G2 },
  { SP::G3 },
  { SP::G4 },
  { SP::G5 },
  { SP::G6 },
  { SP::G7 },
  { SP::I0 },
  { SP::I1 },
  { SP::I2 },
  { SP::I3 },
  { SP::I4 },
  { SP::I5 },
  { SP::I6 },
  { SP::I7 },
  { SP::L0 },
  { SP::L1 },
  { SP::L2 },
  { SP::L3 },
  { SP::L4 },
  { SP::L5 },
  { SP::L6 },
  { SP::L7 },
  { SP::O0 },
  { SP::O1 },
  { SP::O2 },
  { SP::O3 },
  { SP::O4 },
  { SP::O5 },
  { SP::O6 },
  { SP::O7 },
};

namespace {     // Register classes...
  // FCCRegs Register Class...
  const MCPhysReg FCCRegs[] = {
    SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3, 
  };

  // FCCRegs Bit set.
  const uint8_t FCCRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 
  };

  // ASRRegs Register Class...
  const MCPhysReg ASRRegs[] = {
    SP::Y, SP::TICK, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31, 
  };

  // ASRRegs Bit set.
  const uint8_t ASRRegsBits[] = {
    0x00, 0x00, 0x02, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // CoprocRegs Register Class...
  const MCPhysReg CoprocRegs[] = {
    SP::C0, SP::C1, SP::C2, SP::C3, SP::C4, SP::C5, SP::C6, SP::C7, SP::C8, SP::C9, SP::C10, SP::C11, SP::C12, SP::C13, SP::C14, SP::C15, SP::C16, SP::C17, SP::C18, SP::C19, SP::C20, SP::C21, SP::C22, SP::C23, SP::C24, SP::C25, SP::C26, SP::C27, SP::C28, SP::C29, SP::C30, SP::C31, 
  };

  // CoprocRegs Bit set.
  const uint8_t CoprocRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // FPRegs Register Class...
  const MCPhysReg FPRegs[] = {
    SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31, 
  };

  // FPRegs Bit set.
  const uint8_t FPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // IntRegs Register Class...
  const MCPhysReg IntRegs[] = {
    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
  };

  // IntRegs Bit set.
  const uint8_t IntRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // DFPRegs Register Class...
  const MCPhysReg DFPRegs[] = {
    SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31, 
  };

  // DFPRegs Bit set.
  const uint8_t DFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03, 
  };

  // I64Regs Register Class...
  const MCPhysReg I64Regs[] = {
    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7, 
  };

  // I64Regs Bit set.
  const uint8_t I64RegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f, 
  };

  // PRRegs Register Class...
  const MCPhysReg PRRegs[] = {
    SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE, SP::GL, SP::VER, 
  };

  // PRRegs Bit set.
  const uint8_t PRRegsBits[] = {
    0x4e, 0xda, 0xfe, 0x02, 
  };

  // CoprocPair Register Class...
  const MCPhysReg CoprocPair[] = {
    SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7, SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15, SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23, SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31, 
  };

  // CoprocPair Bit set.
  const uint8_t CoprocPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // IntPair Register Class...
  const MCPhysReg IntPair[] = {
    SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7, 
  };

  // IntPair Bit set.
  const uint8_t IntPairBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // LowDFPRegs Register Class...
  const MCPhysReg LowDFPRegs[] = {
    SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, 
  };

  // LowDFPRegs Bit set.
  const uint8_t LowDFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03, 
  };

  // PRRegs_and_ASRRegs Register Class...
  const MCPhysReg PRRegs_and_ASRRegs[] = {
    SP::TICK, 
  };

  // PRRegs_and_ASRRegs Bit set.
  const uint8_t PRRegs_and_ASRRegsBits[] = {
    0x00, 0x00, 0x02, 
  };

  // QFPRegs Register Class...
  const MCPhysReg QFPRegs[] = {
    SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, SP::Q8, SP::Q9, SP::Q10, SP::Q11, SP::Q12, SP::Q13, SP::Q14, SP::Q15, 
  };

  // QFPRegs Bit set.
  const uint8_t QFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f, 
  };

  // LowQFPRegs Register Class...
  const MCPhysReg LowQFPRegs[] = {
    SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, 
  };

  // LowQFPRegs Bit set.
  const uint8_t LowQFPRegsBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f, 
  };

} // end anonymous namespace


#ifdef __GNUC__
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Woverlength-strings"
#endif
extern const char SparcRegClassStrings[] = {
  /* 0 */ "CoprocPair\0"
  /* 11 */ "IntPair\0"
  /* 19 */ "I64Regs\0"
  /* 27 */ "FCCRegs\0"
  /* 35 */ "LowDFPRegs\0"
  /* 46 */ "LowQFPRegs\0"
  /* 57 */ "PRRegs\0"
  /* 64 */ "PRRegs_and_ASRRegs\0"
  /* 83 */ "CoprocRegs\0"
  /* 94 */ "IntRegs\0"
};
#ifdef __GNUC__
#pragma GCC diagnostic pop
#endif

extern const MCRegisterClass SparcMCRegisterClasses[] = {
  { FCCRegs, FCCRegsBits, 27, 4, sizeof(FCCRegsBits), SP::FCCRegsRegClassID, 1, 1, true },
  { ASRRegs, ASRRegsBits, 75, 33, sizeof(ASRRegsBits), SP::ASRRegsRegClassID, 32, 1, false },
  { CoprocRegs, CoprocRegsBits, 83, 32, sizeof(CoprocRegsBits), SP::CoprocRegsRegClassID, 32, 1, false },
  { FPRegs, FPRegsBits, 39, 32, sizeof(FPRegsBits), SP::FPRegsRegClassID, 32, 1, true },
  { IntRegs, IntRegsBits, 94, 32, sizeof(IntRegsBits), SP::IntRegsRegClassID, 32, 1, true },
  { DFPRegs, DFPRegsBits, 38, 32, sizeof(DFPRegsBits), SP::DFPRegsRegClassID, 64, 1, true },
  { I64Regs, I64RegsBits, 19, 32, sizeof(I64RegsBits), SP::I64RegsRegClassID, 64, 1, true },
  { PRRegs, PRRegsBits, 57, 17, sizeof(PRRegsBits), SP::PRRegsRegClassID, 64, 1, true },
  { CoprocPair, CoprocPairBits, 0, 16, sizeof(CoprocPairBits), SP::CoprocPairRegClassID, 64, 1, false },
  { IntPair, IntPairBits, 11, 16, sizeof(IntPairBits), SP::IntPairRegClassID, 64, 1, true },
  { LowDFPRegs, LowDFPRegsBits, 35, 16, sizeof(LowDFPRegsBits), SP::LowDFPRegsRegClassID, 64, 1, true },
  { PRRegs_and_ASRRegs, PRRegs_and_ASRRegsBits, 64, 1, sizeof(PRRegs_and_ASRRegsBits), SP::PRRegs_and_ASRRegsRegClassID, 64, 1, true },
  { QFPRegs, QFPRegsBits, 49, 16, sizeof(QFPRegsBits), SP::QFPRegsRegClassID, 128, 1, true },
  { LowQFPRegs, LowQFPRegsBits, 46, 8, sizeof(LowQFPRegsBits), SP::LowQFPRegsRegClassID, 128, 1, true },
};

// SP Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
  { 0U, SP::G0 },
  { 1U, SP::G1 },
  { 2U, SP::G2 },
  { 3U, SP::G3 },
  { 4U, SP::G4 },
  { 5U, SP::G5 },
  { 6U, SP::G6 },
  { 7U, SP::G7 },
  { 8U, SP::O0 },
  { 9U, SP::O1 },
  { 10U, SP::O2 },
  { 11U, SP::O3 },
  { 12U, SP::O4 },
  { 13U, SP::O5 },
  { 14U, SP::O6 },
  { 15U, SP::O7 },
  { 16U, SP::L0 },
  { 17U, SP::L1 },
  { 18U, SP::L2 },
  { 19U, SP::L3 },
  { 20U, SP::L4 },
  { 21U, SP::L5 },
  { 22U, SP::L6 },
  { 23U, SP::L7 },
  { 24U, SP::I0 },
  { 25U, SP::I1 },
  { 26U, SP::I2 },
  { 27U, SP::I3 },
  { 28U, SP::I4 },
  { 29U, SP::I5 },
  { 30U, SP::I6 },
  { 31U, SP::I7 },
  { 32U, SP::F0 },
  { 33U, SP::F1 },
  { 34U, SP::F2 },
  { 35U, SP::F3 },
  { 36U, SP::F4 },
  { 37U, SP::F5 },
  { 38U, SP::F6 },
  { 39U, SP::F7 },
  { 40U, SP::F8 },
  { 41U, SP::F9 },
  { 42U, SP::F10 },
  { 43U, SP::F11 },
  { 44U, SP::F12 },
  { 45U, SP::F13 },
  { 46U, SP::F14 },
  { 47U, SP::F15 },
  { 48U, SP::F16 },
  { 49U, SP::F17 },
  { 50U, SP::F18 },
  { 51U, SP::F19 },
  { 52U, SP::F20 },
  { 53U, SP::F21 },
  { 54U, SP::F22 },
  { 55U, SP::F23 },
  { 56U, SP::F24 },
  { 57U, SP::F25 },
  { 58U, SP::F26 },
  { 59U, SP::F27 },
  { 60U, SP::F28 },
  { 61U, SP::F29 },
  { 62U, SP::F30 },
  { 63U, SP::F31 },
  { 64U, SP::Y },
  { 72U, SP::D0 },
  { 73U, SP::D1 },
  { 74U, SP::D2 },
  { 75U, SP::D3 },
  { 76U, SP::D4 },
  { 77U, SP::D5 },
  { 78U, SP::D6 },
  { 79U, SP::D7 },
  { 80U, SP::D8 },
  { 81U, SP::D9 },
  { 82U, SP::D10 },
  { 83U, SP::D11 },
  { 84U, SP::D12 },
  { 85U, SP::D13 },
  { 86U, SP::D14 },
  { 87U, SP::D15 },
};
extern const unsigned SPDwarfFlavour0Dwarf2LSize = std::size(SPDwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
  { 0U, SP::G0 },
  { 1U, SP::G1 },
  { 2U, SP::G2 },
  { 3U, SP::G3 },
  { 4U, SP::G4 },
  { 5U, SP::G5 },
  { 6U, SP::G6 },
  { 7U, SP::G7 },
  { 8U, SP::O0 },
  { 9U, SP::O1 },
  { 10U, SP::O2 },
  { 11U, SP::O3 },
  { 12U, SP::O4 },
  { 13U, SP::O5 },
  { 14U, SP::O6 },
  { 15U, SP::O7 },
  { 16U, SP::L0 },
  { 17U, SP::L1 },
  { 18U, SP::L2 },
  { 19U, SP::L3 },
  { 20U, SP::L4 },
  { 21U, SP::L5 },
  { 22U, SP::L6 },
  { 23U, SP::L7 },
  { 24U, SP::I0 },
  { 25U, SP::I1 },
  { 26U, SP::I2 },
  { 27U, SP::I3 },
  { 28U, SP::I4 },
  { 29U, SP::I5 },
  { 30U, SP::I6 },
  { 31U, SP::I7 },
  { 32U, SP::F0 },
  { 33U, SP::F1 },
  { 34U, SP::F2 },
  { 35U, SP::F3 },
  { 36U, SP::F4 },
  { 37U, SP::F5 },
  { 38U, SP::F6 },
  { 39U, SP::F7 },
  { 40U, SP::F8 },
  { 41U, SP::F9 },
  { 42U, SP::F10 },
  { 43U, SP::F11 },
  { 44U, SP::F12 },
  { 45U, SP::F13 },
  { 46U, SP::F14 },
  { 47U, SP::F15 },
  { 48U, SP::F16 },
  { 49U, SP::F17 },
  { 50U, SP::F18 },
  { 51U, SP::F19 },
  { 52U, SP::F20 },
  { 53U, SP::F21 },
  { 54U, SP::F22 },
  { 55U, SP::F23 },
  { 56U, SP::F24 },
  { 57U, SP::F25 },
  { 58U, SP::F26 },
  { 59U, SP::F27 },
  { 60U, SP::F28 },
  { 61U, SP::F29 },
  { 62U, SP::F30 },
  { 63U, SP::F31 },
  { 64U, SP::Y },
  { 72U, SP::D0 },
  { 73U, SP::D1 },
  { 74U, SP::D2 },
  { 75U, SP::D3 },
  { 76U, SP::D4 },
  { 77U, SP::D5 },
  { 78U, SP::D6 },
  { 79U, SP::D7 },
  { 80U, SP::D8 },
  { 81U, SP::D9 },
  { 82U, SP::D10 },
  { 83U, SP::D11 },
  { 84U, SP::D12 },
  { 85U, SP::D13 },
  { 86U, SP::D14 },
  { 87U, SP::D15 },
};
extern const unsigned SPEHFlavour0Dwarf2LSize = std::size(SPEHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
  { SP::Y, 64U },
  { SP::D0, 72U },
  { SP::D1, 73U },
  { SP::D2, 74U },
  { SP::D3, 75U },
  { SP::D4, 76U },
  { SP::D5, 77U },
  { SP::D6, 78U },
  { SP::D7, 79U },
  { SP::D8, 80U },
  { SP::D9, 81U },
  { SP::D10, 82U },
  { SP::D11, 83U },
  { SP::D12, 84U },
  { SP::D13, 85U },
  { SP::D14, 86U },
  { SP::D15, 87U },
  { SP::F0, 32U },
  { SP::F1, 33U },
  { SP::F2, 34U },
  { SP::F3, 35U },
  { SP::F4, 36U },
  { SP::F5, 37U },
  { SP::F6, 38U },
  { SP::F7, 39U },
  { SP::F8, 40U },
  { SP::F9, 41U },
  { SP::F10, 42U },
  { SP::F11, 43U },
  { SP::F12, 44U },
  { SP::F13, 45U },
  { SP::F14, 46U },
  { SP::F15, 47U },
  { SP::F16, 48U },
  { SP::F17, 49U },
  { SP::F18, 50U },
  { SP::F19, 51U },
  { SP::F20, 52U },
  { SP::F21, 53U },
  { SP::F22, 54U },
  { SP::F23, 55U },
  { SP::F24, 56U },
  { SP::F25, 57U },
  { SP::F26, 58U },
  { SP::F27, 59U },
  { SP::F28, 60U },
  { SP::F29, 61U },
  { SP::F30, 62U },
  { SP::F31, 63U },
  { SP::G0, 0U },
  { SP::G1, 1U },
  { SP::G2, 2U },
  { SP::G3, 3U },
  { SP::G4, 4U },
  { SP::G5, 5U },
  { SP::G6, 6U },
  { SP::G7, 7U },
  { SP::I0, 24U },
  { SP::I1, 25U },
  { SP::I2, 26U },
  { SP::I3, 27U },
  { SP::I4, 28U },
  { SP::I5, 29U },
  { SP::I6, 30U },
  { SP::I7, 31U },
  { SP::L0, 16U },
  { SP::L1, 17U },
  { SP::L2, 18U },
  { SP::L3, 19U },
  { SP::L4, 20U },
  { SP::L5, 21U },
  { SP::L6, 22U },
  { SP::L7, 23U },
  { SP::O0, 8U },
  { SP::O1, 9U },
  { SP::O2, 10U },
  { SP::O3, 11U },
  { SP::O4, 12U },
  { SP::O5, 13U },
  { SP::O6, 14U },
  { SP::O7, 15U },
};
extern const unsigned SPDwarfFlavour0L2DwarfSize = std::size(SPDwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
  { SP::Y, 64U },
  { SP::D0, 72U },
  { SP::D1, 73U },
  { SP::D2, 74U },
  { SP::D3, 75U },
  { SP::D4, 76U },
  { SP::D5, 77U },
  { SP::D6, 78U },
  { SP::D7, 79U },
  { SP::D8, 80U },
  { SP::D9, 81U },
  { SP::D10, 82U },
  { SP::D11, 83U },
  { SP::D12, 84U },
  { SP::D13, 85U },
  { SP::D14, 86U },
  { SP::D15, 87U },
  { SP::F0, 32U },
  { SP::F1, 33U },
  { SP::F2, 34U },
  { SP::F3, 35U },
  { SP::F4, 36U },
  { SP::F5, 37U },
  { SP::F6, 38U },
  { SP::F7, 39U },
  { SP::F8, 40U },
  { SP::F9, 41U },
  { SP::F10, 42U },
  { SP::F11, 43U },
  { SP::F12, 44U },
  { SP::F13, 45U },
  { SP::F14, 46U },
  { SP::F15, 47U },
  { SP::F16, 48U },
  { SP::F17, 49U },
  { SP::F18, 50U },
  { SP::F19, 51U },
  { SP::F20, 52U },
  { SP::F21, 53U },
  { SP::F22, 54U },
  { SP::F23, 55U },
  { SP::F24, 56U },
  { SP::F25, 57U },
  { SP::F26, 58U },
  { SP::F27, 59U },
  { SP::F28, 60U },
  { SP::F29, 61U },
  { SP::F30, 62U },
  { SP::F31, 63U },
  { SP::G0, 0U },
  { SP::G1, 1U },
  { SP::G2, 2U },
  { SP::G3, 3U },
  { SP::G4, 4U },
  { SP::G5, 5U },
  { SP::G6, 6U },
  { SP::G7, 7U },
  { SP::I0, 24U },
  { SP::I1, 25U },
  { SP::I2, 26U },
  { SP::I3, 27U },
  { SP::I4, 28U },
  { SP::I5, 29U },
  { SP::I6, 30U },
  { SP::I7, 31U },
  { SP::L0, 16U },
  { SP::L1, 17U },
  { SP::L2, 18U },
  { SP::L3, 19U },
  { SP::L4, 20U },
  { SP::L5, 21U },
  { SP::L6, 22U },
  { SP::L7, 23U },
  { SP::O0, 8U },
  { SP::O1, 9U },
  { SP::O2, 10U },
  { SP::O3, 11U },
  { SP::O4, 12U },
  { SP::O5, 13U },
  { SP::O6, 14U },
  { SP::O7, 15U },
};
extern const unsigned SPEHFlavour0L2DwarfSize = std::size(SPEHFlavour0L2Dwarf);

extern const uint16_t SparcRegEncodingTable[] = {
  0,
  11,
  10,
  12,
  0,
  0,
  9,
  0,
  0,
  16,
  0,
  13,
  8,
  0,
  6,
  5,
  0,
  4,
  7,
  1,
  0,
  2,
  3,
  31,
  0,
  14,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  1,
  3,
  5,
  7,
  9,
  11,
  13,
  15,
  17,
  19,
  21,
  23,
  25,
  27,
  29,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  0,
  4,
  8,
  12,
  16,
  20,
  24,
  28,
  1,
  5,
  9,
  13,
  17,
  21,
  25,
  29,
  0,
  2,
  4,
  6,
  8,
  10,
  12,
  14,
  16,
  18,
  20,
  22,
  24,
  26,
  28,
  30,
  0,
  2,
  4,
  6,
  24,
  26,
  28,
  30,
  16,
  18,
  20,
  22,
  8,
  10,
  12,
  14,
};
static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(SparcRegDesc, 238, RA, PC, SparcMCRegisterClasses, 14, SparcRegUnitRoots, 173, SparcRegDiffLists, SparcLaneMaskLists, SparcRegStrings, SparcRegClassStrings, SparcSubRegIdxLists, 7,
SparcSubRegIdxRanges, SparcRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
    break;
  }
}

} // end namespace llvm

#endif // GET_REGINFO_MC_DESC

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Register Information Header Fragment                                       *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_HEADER
#undef GET_REGINFO_HEADER

#include "llvm/CodeGen/TargetRegisterInfo.h"

namespace llvm {

class SparcFrameLowering;

struct SparcGenRegisterInfo : public TargetRegisterInfo {
  explicit SparcGenRegisterInfo(unsigned RA, unsigned D = 0, unsigned E = 0,
      unsigned PC = 0, unsigned HwMode = 0);
  unsigned composeSubRegIndicesImpl(unsigned, unsigned) const override;
  LaneBitmask composeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl(unsigned, LaneBitmask) const override;
  const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass *, unsigned) const override;
  const TargetRegisterClass *getSubRegisterClass(const TargetRegisterClass *, unsigned) const override;
  const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
  unsigned getRegUnitWeight(unsigned RegUnit) const override;
  unsigned getNumRegPressureSets() const override;
  const char *getRegPressureSetName(unsigned Idx) const override;
  unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const override;
  const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
  const int *getRegUnitPressureSets(unsigned RegUnit) const override;
  ArrayRef<const char *> getRegMaskNames() const override;
  ArrayRef<const uint32_t *> getRegMasks() const override;
  bool isGeneralPurposeRegister(const MachineFunction &, MCRegister) const override;
  bool isFixedRegister(const MachineFunction &, MCRegister) const override;
  bool isArgumentRegister(const MachineFunction &, MCRegister) const override;
  bool isConstantPhysReg(MCRegister PhysReg) const override final;
  /// Devirtualized TargetFrameLowering.
  static const SparcFrameLowering *getFrameLowering(
      const MachineFunction &MF);
};

namespace SP { // Register classes
  extern const TargetRegisterClass FCCRegsRegClass;
  extern const TargetRegisterClass ASRRegsRegClass;
  extern const TargetRegisterClass CoprocRegsRegClass;
  extern const TargetRegisterClass FPRegsRegClass;
  extern const TargetRegisterClass IntRegsRegClass;
  extern const TargetRegisterClass DFPRegsRegClass;
  extern const TargetRegisterClass I64RegsRegClass;
  extern const TargetRegisterClass PRRegsRegClass;
  extern const TargetRegisterClass CoprocPairRegClass;
  extern const TargetRegisterClass IntPairRegClass;
  extern const TargetRegisterClass LowDFPRegsRegClass;
  extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass;
  extern const TargetRegisterClass QFPRegsRegClass;
  extern const TargetRegisterClass LowQFPRegsRegClass;
} // end namespace SP

} // end namespace llvm

#endif // GET_REGINFO_HEADER

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register and Register Classes Information                           *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_TARGET_DESC
#undef GET_REGINFO_TARGET_DESC

namespace llvm {

extern const MCRegisterClass SparcMCRegisterClasses[];

static const MVT::SimpleValueType VTLists[] = {
  /* 0 */ MVT::i1, MVT::Other,
  /* 2 */ MVT::i32, MVT::Other,
  /* 4 */ MVT::i32, MVT::i64, MVT::Other,
  /* 7 */ MVT::f32, MVT::Other,
  /* 9 */ MVT::f64, MVT::Other,
  /* 11 */ MVT::f128, MVT::Other,
  /* 13 */ MVT::v2i32, MVT::Other,
};

static const char *SubRegIndexNameTable[] = { "sub_even", "sub_even64", "sub_odd", "sub_odd64", "sub_odd64_then_sub_even", "sub_odd64_then_sub_odd", "" };


static const LaneBitmask SubRegIndexLaneMaskTable[] = {
  LaneBitmask::getAll(),
  LaneBitmask(0x0000000000000001), // sub_even
  LaneBitmask(0x0000000000000003), // sub_even64
  LaneBitmask(0x0000000000000002), // sub_odd
  LaneBitmask(0x000000000000000C), // sub_odd64
  LaneBitmask(0x0000000000000004), // sub_odd64_then_sub_even
  LaneBitmask(0x0000000000000008), // sub_odd64_then_sub_odd
 };



static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
  // Mode = 0 (Default)
  { 1, 1, 1, /*VTLists+*/0 },    // FCCRegs
  { 32, 32, 32, /*VTLists+*/2 },    // ASRRegs
  { 32, 32, 32, /*VTLists+*/2 },    // CoprocRegs
  { 32, 32, 32, /*VTLists+*/7 },    // FPRegs
  { 32, 32, 32, /*VTLists+*/4 },    // IntRegs
  { 64, 64, 64, /*VTLists+*/9 },    // DFPRegs
  { 64, 64, 64, /*VTLists+*/5 },    // I64Regs
  { 64, 64, 64, /*VTLists+*/5 },    // PRRegs
  { 64, 64, 64, /*VTLists+*/13 },    // CoprocPair
  { 64, 64, 64, /*VTLists+*/13 },    // IntPair
  { 64, 64, 64, /*VTLists+*/9 },    // LowDFPRegs
  { 64, 64, 64, /*VTLists+*/5 },    // PRRegs_and_ASRRegs
  { 128, 128, 128, /*VTLists+*/11 },    // QFPRegs
  { 128, 128, 128, /*VTLists+*/11 },    // LowQFPRegs
};

static const TargetRegisterClass *const NullRegClasses[] = { nullptr };

static const uint32_t FCCRegsSubClassMask[] = {
  0x00000001, 
};

static const uint32_t ASRRegsSubClassMask[] = {
  0x00000802, 
};

static const uint32_t CoprocRegsSubClassMask[] = {
  0x00000004, 
  0x00000100, // sub_even
  0x00000100, // sub_odd
};

static const uint32_t FPRegsSubClassMask[] = {
  0x00000008, 
  0x00002400, // sub_even
  0x00002400, // sub_odd
  0x00002000, // sub_odd64_then_sub_even
  0x00002000, // sub_odd64_then_sub_odd
};

static const uint32_t IntRegsSubClassMask[] = {
  0x00000050, 
  0x00000200, // sub_even
  0x00000200, // sub_odd
};

static const uint32_t DFPRegsSubClassMask[] = {
  0x00000420, 
  0x00003000, // sub_even64
  0x00003000, // sub_odd64
};

static const uint32_t I64RegsSubClassMask[] = {
  0x00000040, 
  0x00000200, // sub_even
  0x00000200, // sub_odd
};

static const uint32_t PRRegsSubClassMask[] = {
  0x00000880, 
};

static const uint32_t CoprocPairSubClassMask[] = {
  0x00000100, 
};

static const uint32_t IntPairSubClassMask[] = {
  0x00000200, 
};

static const uint32_t LowDFPRegsSubClassMask[] = {
  0x00000400, 
  0x00002000, // sub_even64
  0x00002000, // sub_odd64
};

static const uint32_t PRRegs_and_ASRRegsSubClassMask[] = {
  0x00000800, 
};

static const uint32_t QFPRegsSubClassMask[] = {
  0x00003000, 
};

static const uint32_t LowQFPRegsSubClassMask[] = {
  0x00002000, 
};

static const uint16_t SuperRegIdxSeqs[] = {
  /* 0 */ 1, 3, 0,
  /* 3 */ 2, 4, 0,
  /* 6 */ 1, 3, 5, 6, 0,
};

static const TargetRegisterClass *const I64RegsSuperclasses[] = {
  &SP::IntRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const LowDFPRegsSuperclasses[] = {
  &SP::DFPRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const PRRegs_and_ASRRegsSuperclasses[] = {
  &SP::ASRRegsRegClass,
  &SP::PRRegsRegClass,
  nullptr
};

static const TargetRegisterClass *const LowQFPRegsSuperclasses[] = {
  &SP::QFPRegsRegClass,
  nullptr
};


namespace SP {   // Register class instances
  extern const TargetRegisterClass FCCRegsRegClass = {
    &SparcMCRegisterClasses[FCCRegsRegClassID],
    FCCRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass ASRRegsRegClass = {
    &SparcMCRegisterClasses[ASRRegsRegClassID],
    ASRRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CoprocRegsRegClass = {
    &SparcMCRegisterClasses[CoprocRegsRegClassID],
    CoprocRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass FPRegsRegClass = {
    &SparcMCRegisterClasses[FPRegsRegClassID],
    FPRegsSubClassMask,
    SuperRegIdxSeqs + 6,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass IntRegsRegClass = {
    &SparcMCRegisterClasses[IntRegsRegClassID],
    IntRegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass DFPRegsRegClass = {
    &SparcMCRegisterClasses[DFPRegsRegClassID],
    DFPRegsSubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass I64RegsRegClass = {
    &SparcMCRegisterClasses[I64RegsRegClassID],
    I64RegsSubClassMask,
    SuperRegIdxSeqs + 0,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    I64RegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass PRRegsRegClass = {
    &SparcMCRegisterClasses[PRRegsRegClassID],
    PRRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass CoprocPairRegClass = {
    &SparcMCRegisterClasses[CoprocPairRegClassID],
    CoprocPairSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass IntPairRegClass = {
    &SparcMCRegisterClasses[IntPairRegClassID],
    IntPairSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LowDFPRegsRegClass = {
    &SparcMCRegisterClasses[LowDFPRegsRegClassID],
    LowDFPRegsSubClassMask,
    SuperRegIdxSeqs + 3,
    LaneBitmask(0x0000000000000003),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    LowDFPRegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass PRRegs_and_ASRRegsRegClass = {
    &SparcMCRegisterClasses[PRRegs_and_ASRRegsRegClassID],
    PRRegs_and_ASRRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x0000000000000001),
    0,
    false,
    0x00, /* TSFlags */
    false, /* HasDisjunctSubRegs */
    false, /* CoveredBySubRegs */
    PRRegs_and_ASRRegsSuperclasses,
    nullptr
  };

  extern const TargetRegisterClass QFPRegsRegClass = {
    &SparcMCRegisterClasses[QFPRegsRegClassID],
    QFPRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x000000000000000F),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    NullRegClasses,
    nullptr
  };

  extern const TargetRegisterClass LowQFPRegsRegClass = {
    &SparcMCRegisterClasses[LowQFPRegsRegClassID],
    LowQFPRegsSubClassMask,
    SuperRegIdxSeqs + 2,
    LaneBitmask(0x000000000000000F),
    0,
    false,
    0x00, /* TSFlags */
    true, /* HasDisjunctSubRegs */
    true, /* CoveredBySubRegs */
    LowQFPRegsSuperclasses,
    nullptr
  };

} // end namespace SP

namespace {
  const TargetRegisterClass *const RegisterClasses[] = {
    &SP::FCCRegsRegClass,
    &SP::ASRRegsRegClass,
    &SP::CoprocRegsRegClass,
    &SP::FPRegsRegClass,
    &SP::IntRegsRegClass,
    &SP::DFPRegsRegClass,
    &SP::I64RegsRegClass,
    &SP::PRRegsRegClass,
    &SP::CoprocPairRegClass,
    &SP::IntPairRegClass,
    &SP::LowDFPRegsRegClass,
    &SP::PRRegs_and_ASRRegsRegClass,
    &SP::QFPRegsRegClass,
    &SP::LowQFPRegsRegClass,
  };
} // end anonymous namespace

static const uint8_t CostPerUseTable[] = { 
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };


static const bool InAllocatableClassTable[] = { 
false, true, true, true, false, false, true, false, false, true, false, true, true, false, true, true, false, true, true, true, true, true, true, true, false, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, false, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, };


static const TargetRegisterInfoDesc SparcRegInfoDesc = { // Extra Descriptors
CostPerUseTable, 1, InAllocatableClassTable};

unsigned SparcGenRegisterInfo::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {
  static const uint8_t RowMap[6] = {
    0, 0, 0, 1, 0, 0, 
  };
  static const uint8_t Rows[2][6] = {
    { SP::sub_even, 0, SP::sub_odd, 0, 0, 0, },
    { SP::sub_odd64_then_sub_even, 0, SP::sub_odd64_then_sub_odd, 0, 0, 0, },
  };

  --IdxA; assert(IdxA < 6); (void) IdxA;
  --IdxB; assert(IdxB < 6);
  return Rows[RowMap[IdxA]][IdxB];
}

  struct MaskRolOp {
    LaneBitmask Mask;
    uint8_t  RotateLeft;
  };
  static const MaskRolOp LaneMaskComposeSequences[] = {
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  0 }, { LaneBitmask::getNone(), 0 },   // Sequence 0
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  1 }, { LaneBitmask::getNone(), 0 },   // Sequence 2
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  2 }, { LaneBitmask::getNone(), 0 },   // Sequence 4
    { LaneBitmask(0xFFFFFFFFFFFFFFFF),  3 }, { LaneBitmask::getNone(), 0 }  // Sequence 6
  };
  static const uint8_t CompositeSequences[] = {
    0, // to sub_even
    0, // to sub_even64
    2, // to sub_odd
    4, // to sub_odd64
    4, // to sub_odd64_then_sub_even
    6 // to sub_odd64_then_sub_odd
  };

LaneBitmask SparcGenRegisterInfo::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask) const {
  --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger() & Ops->Mask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

LaneBitmask SparcGenRegisterInfo::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA,  LaneBitmask LaneMask) const {
  LaneMask &= getSubRegIndexLaneMask(IdxA);
  --IdxA; assert(IdxA < 6 && "Subregister index out of bounds");
  LaneBitmask Result;
  for (const MaskRolOp *Ops =
       &LaneMaskComposeSequences[CompositeSequences[IdxA]];
       Ops->Mask.any(); ++Ops) {
    LaneBitmask::Type M = LaneMask.getAsInteger();
    if (unsigned S = Ops->RotateLeft)
      Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - S)));
    else
      Result |= LaneBitmask(M);
  }
  return Result;
}

const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[14][6] = {
    { // FCCRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // ASRRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // CoprocRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // FPRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // IntRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // DFPRegs
      11, // sub_even -> LowDFPRegs
      0,  // sub_even64
      11, // sub_odd -> LowDFPRegs
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // I64Regs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // PRRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // CoprocPair
      9,  // sub_even -> CoprocPair
      0,  // sub_even64
      9,  // sub_odd -> CoprocPair
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // IntPair
      10, // sub_even -> IntPair
      0,  // sub_even64
      10, // sub_odd -> IntPair
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // LowDFPRegs
      11, // sub_even -> LowDFPRegs
      0,  // sub_even64
      11, // sub_odd -> LowDFPRegs
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // PRRegs_and_ASRRegs
      0,  // sub_even
      0,  // sub_even64
      0,  // sub_odd
      0,  // sub_odd64
      0,  // sub_odd64_then_sub_even
      0,  // sub_odd64_then_sub_odd
    },
    { // QFPRegs
      14, // sub_even -> LowQFPRegs
      13, // sub_even64 -> QFPRegs
      14, // sub_odd -> LowQFPRegs
      13, // sub_odd64 -> QFPRegs
      14, // sub_odd64_then_sub_even -> LowQFPRegs
      14, // sub_odd64_then_sub_odd -> LowQFPRegs
    },
    { // LowQFPRegs
      14, // sub_even -> LowQFPRegs
      14, // sub_even64 -> LowQFPRegs
      14, // sub_odd -> LowQFPRegs
      14, // sub_odd64 -> LowQFPRegs
      14, // sub_odd64_then_sub_even -> LowQFPRegs
      14, // sub_odd64_then_sub_odd -> LowQFPRegs
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 6 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

const TargetRegisterClass *SparcGenRegisterInfo::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx) const {
  static const uint8_t Table[14][6] = {
    { // FCCRegs
      0,  // FCCRegs:sub_even
      0,  // FCCRegs:sub_even64
      0,  // FCCRegs:sub_odd
      0,  // FCCRegs:sub_odd64
      0,  // FCCRegs:sub_odd64_then_sub_even
      0,  // FCCRegs:sub_odd64_then_sub_odd
    },
    { // ASRRegs
      0,  // ASRRegs:sub_even
      0,  // ASRRegs:sub_even64
      0,  // ASRRegs:sub_odd
      0,  // ASRRegs:sub_odd64
      0,  // ASRRegs:sub_odd64_then_sub_even
      0,  // ASRRegs:sub_odd64_then_sub_odd
    },
    { // CoprocRegs
      0,  // CoprocRegs:sub_even
      0,  // CoprocRegs:sub_even64
      0,  // CoprocRegs:sub_odd
      0,  // CoprocRegs:sub_odd64
      0,  // CoprocRegs:sub_odd64_then_sub_even
      0,  // CoprocRegs:sub_odd64_then_sub_odd
    },
    { // FPRegs
      0,  // FPRegs:sub_even
      0,  // FPRegs:sub_even64
      0,  // FPRegs:sub_odd
      0,  // FPRegs:sub_odd64
      0,  // FPRegs:sub_odd64_then_sub_even
      0,  // FPRegs:sub_odd64_then_sub_odd
    },
    { // IntRegs
      0,  // IntRegs:sub_even
      0,  // IntRegs:sub_even64
      0,  // IntRegs:sub_odd
      0,  // IntRegs:sub_odd64
      0,  // IntRegs:sub_odd64_then_sub_even
      0,  // IntRegs:sub_odd64_then_sub_odd
    },
    { // DFPRegs
      4,  // DFPRegs:sub_even -> FPRegs
      0,  // DFPRegs:sub_even64
      4,  // DFPRegs:sub_odd -> FPRegs
      0,  // DFPRegs:sub_odd64
      0,  // DFPRegs:sub_odd64_then_sub_even
      0,  // DFPRegs:sub_odd64_then_sub_odd
    },
    { // I64Regs
      0,  // I64Regs:sub_even
      0,  // I64Regs:sub_even64
      0,  // I64Regs:sub_odd
      0,  // I64Regs:sub_odd64
      0,  // I64Regs:sub_odd64_then_sub_even
      0,  // I64Regs:sub_odd64_then_sub_odd
    },
    { // PRRegs
      0,  // PRRegs:sub_even
      0,  // PRRegs:sub_even64
      0,  // PRRegs:sub_odd
      0,  // PRRegs:sub_odd64
      0,  // PRRegs:sub_odd64_then_sub_even
      0,  // PRRegs:sub_odd64_then_sub_odd
    },
    { // CoprocPair
      3,  // CoprocPair:sub_even -> CoprocRegs
      0,  // CoprocPair:sub_even64
      3,  // CoprocPair:sub_odd -> CoprocRegs
      0,  // CoprocPair:sub_odd64
      0,  // CoprocPair:sub_odd64_then_sub_even
      0,  // CoprocPair:sub_odd64_then_sub_odd
    },
    { // IntPair
      7,  // IntPair:sub_even -> I64Regs
      0,  // IntPair:sub_even64
      7,  // IntPair:sub_odd -> I64Regs
      0,  // IntPair:sub_odd64
      0,  // IntPair:sub_odd64_then_sub_even
      0,  // IntPair:sub_odd64_then_sub_odd
    },
    { // LowDFPRegs
      4,  // LowDFPRegs:sub_even -> FPRegs
      0,  // LowDFPRegs:sub_even64
      4,  // LowDFPRegs:sub_odd -> FPRegs
      0,  // LowDFPRegs:sub_odd64
      0,  // LowDFPRegs:sub_odd64_then_sub_even
      0,  // LowDFPRegs:sub_odd64_then_sub_odd
    },
    { // PRRegs_and_ASRRegs
      0,  // PRRegs_and_ASRRegs:sub_even
      0,  // PRRegs_and_ASRRegs:sub_even64
      0,  // PRRegs_and_ASRRegs:sub_odd
      0,  // PRRegs_and_ASRRegs:sub_odd64
      0,  // PRRegs_and_ASRRegs:sub_odd64_then_sub_even
      0,  // PRRegs_and_ASRRegs:sub_odd64_then_sub_odd
    },
    { // QFPRegs
      4,  // QFPRegs:sub_even -> FPRegs
      6,  // QFPRegs:sub_even64 -> DFPRegs
      4,  // QFPRegs:sub_odd -> FPRegs
      6,  // QFPRegs:sub_odd64 -> DFPRegs
      4,  // QFPRegs:sub_odd64_then_sub_even -> FPRegs
      4,  // QFPRegs:sub_odd64_then_sub_odd -> FPRegs
    },
    { // LowQFPRegs
      4,  // LowQFPRegs:sub_even -> FPRegs
      11, // LowQFPRegs:sub_even64 -> LowDFPRegs
      4,  // LowQFPRegs:sub_odd -> FPRegs
      11, // LowQFPRegs:sub_odd64 -> LowDFPRegs
      4,  // LowQFPRegs:sub_odd64_then_sub_even -> FPRegs
      4,  // LowQFPRegs:sub_odd64_then_sub_odd -> FPRegs
    },
  };
  assert(RC && "Missing regclass");
  if (!Idx) return RC;
  --Idx;
  assert(Idx < 6 && "Bad subreg");
  unsigned TV = Table[RC->getID()][Idx];
  return TV ? getRegClass(TV - 1) : nullptr;
}

/// Get the weight in units of pressure for this register class.
const RegClassWeight &SparcGenRegisterInfo::
getRegClassWeight(const TargetRegisterClass *RC) const {
  static const RegClassWeight RCWeightTable[] = {
    {1, 4},   // FCCRegs
    {1, 1},   // ASRRegs
    {0, 0},   // CoprocRegs
    {1, 32},    // FPRegs
    {1, 32},    // IntRegs
    {2, 64},    // DFPRegs
    {1, 32},    // I64Regs
    {1, 17},    // PRRegs
    {0, 0},   // CoprocPair
    {2, 32},    // IntPair
    {2, 32},    // LowDFPRegs
    {1, 1},   // PRRegs_and_ASRRegs
    {4, 64},    // QFPRegs
    {4, 32},    // LowQFPRegs
  };
  return RCWeightTable[RC->getID()];
}

/// Get the weight in units of pressure for this register unit.
unsigned SparcGenRegisterInfo::
getRegUnitWeight(unsigned RegUnit) const {
  assert(RegUnit < 173 && "invalid register unit");
  static const uint8_t RUWeightTable[] = {
    1, 1, 1, 0, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, };
  return RUWeightTable[RegUnit];
}


// Get the number of dimensions of register pressure.
unsigned SparcGenRegisterInfo::getNumRegPressureSets() const {
  return 6;
}

// Get the name of this register unit pressure set.
const char *SparcGenRegisterInfo::
getRegPressureSetName(unsigned Idx) const {
  static const char *PressureNameTable[] = {
    "PRRegs_and_ASRRegs",
    "FCCRegs",
    "PRRegs",
    "FPRegs",
    "IntRegs",
    "DFPRegs",
  };
  return PressureNameTable[Idx];
}

// Get the register unit pressure limit for this dimension.
// This limit must be adjusted dynamically for reserved registers.
unsigned SparcGenRegisterInfo::
getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const {
  static const uint8_t PressureLimitTable[] = {
    1,    // 0: PRRegs_and_ASRRegs
    4,    // 1: FCCRegs
    17,   // 2: PRRegs
    32,   // 3: FPRegs
    32,   // 4: IntRegs
    64,   // 5: DFPRegs
  };
  return PressureLimitTable[Idx];
}

/// Table of pressure sets per register class or unit.
static const int RCSetsTable[] = {
  /* 0 */ 1, -1,
  /* 2 */ 0, 2, -1,
  /* 5 */ 4, -1,
  /* 7 */ 3, 5, -1,
};

/// Get the dimensions of register pressure impacted by this register class.
/// Returns a -1 terminated array of pressure set IDs
const int *SparcGenRegisterInfo::
getRegClassPressureSets(const TargetRegisterClass *RC) const {
  static const uint8_t RCSetStartTable[] = {
    0,1,1,7,5,8,5,3,1,5,7,2,8,7,};
  return &RCSetsTable[RCSetStartTable[RC->getID()]];
}

/// Get the dimensions of register pressure impacted by this register unit.
/// Returns a -1 terminated array of pressure set IDs
const int *SparcGenRegisterInfo::
getRegUnitPressureSets(unsigned RegUnit) const {
  assert(RegUnit < 173 && "invalid register unit");
  static const uint8_t RUSetStartTable[] = {
    3,3,3,1,1,3,1,1,3,1,3,3,1,3,3,1,2,3,3,3,3,3,3,1,3,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,0,0,0,0,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,};
  return &RCSetsTable[RUSetStartTable[RegUnit]];
}

extern const MCRegisterDesc SparcRegDesc[];
extern const int16_t SparcRegDiffLists[];
extern const LaneBitmask SparcLaneMaskLists[];
extern const char SparcRegStrings[];
extern const char SparcRegClassStrings[];
extern const MCPhysReg SparcRegUnitRoots[][2];
extern const uint16_t SparcSubRegIdxLists[];
extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[];
extern const uint16_t SparcRegEncodingTable[];
// SP Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[];
extern const unsigned SPDwarfFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[];
extern const unsigned SPEHFlavour0Dwarf2LSize;

extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[];
extern const unsigned SPDwarfFlavour0L2DwarfSize;

extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[];
extern const unsigned SPEHFlavour0L2DwarfSize;

SparcGenRegisterInfo::
SparcGenRegisterInfo(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,
      unsigned PC, unsigned HwMode)
  : TargetRegisterInfo(&SparcRegInfoDesc, RegisterClasses, RegisterClasses+14,
             SubRegIndexNameTable, SubRegIndexLaneMaskTable,
             LaneBitmask(0xFFFFFFFFFFFFFFFF), RegClassInfos, VTLists, HwMode) {
  InitMCRegisterInfo(SparcRegDesc, 238, RA, PC,
                     SparcMCRegisterClasses, 14,
                     SparcRegUnitRoots,
                     173,
                     SparcRegDiffLists,
                     SparcLaneMaskLists,
                     SparcRegStrings,
                     SparcRegClassStrings,
                     SparcSubRegIdxLists,
                     7,
                     SparcSubRegIdxRanges,
                     SparcRegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
    break;
  }
}

static const MCPhysReg CSR_SaveList[] = { 0 };
static const uint32_t CSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x103fffc0, 0x00000000, 0x000003fc, };
static const MCPhysReg RTCSR_SaveList[] = { 0 };
static const uint32_t RTCSR_RegMask[] = { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x40000000, 0x00003000, 0x00000000, 0x00000020, };


ArrayRef<const uint32_t *> SparcGenRegisterInfo::getRegMasks() const {
  static const uint32_t *const Masks[] = {
    CSR_RegMask,
    RTCSR_RegMask,
  };
  return ArrayRef(Masks);
}

bool SparcGenRegisterInfo::
isGeneralPurposeRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool SparcGenRegisterInfo::
isFixedRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool SparcGenRegisterInfo::
isArgumentRegister(const MachineFunction &MF, MCRegister PhysReg) const {
  return
      false;
}

bool SparcGenRegisterInfo::
isConstantPhysReg(MCRegister PhysReg) const {
  return
      PhysReg == SP::G0 ||
      false;
}

ArrayRef<const char *> SparcGenRegisterInfo::getRegMaskNames() const {
  static const char *Names[] = {
    "CSR",
    "RTCSR",
  };
  return ArrayRef(Names);
}

const SparcFrameLowering *
SparcGenRegisterInfo::getFrameLowering(const MachineFunction &MF) {
  return static_cast<const SparcFrameLowering *>(
      MF.getSubtarget().getFrameLowering());
}

} // end namespace llvm

#endif // GET_REGINFO_TARGET_DESC


Coverage Report

Created: 2024-01-17 10:31