/src/build/lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t SystemZMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 0 | const MCSubtargetInfo &STI) const { |
12 | 0 | static const uint64_t InstBits[] = { |
13 | 0 | UINT64_C(0), |
14 | 0 | UINT64_C(0), |
15 | 0 | UINT64_C(0), |
16 | 0 | UINT64_C(0), |
17 | 0 | UINT64_C(0), |
18 | 0 | UINT64_C(0), |
19 | 0 | UINT64_C(0), |
20 | 0 | UINT64_C(0), |
21 | 0 | UINT64_C(0), |
22 | 0 | UINT64_C(0), |
23 | 0 | UINT64_C(0), |
24 | 0 | UINT64_C(0), |
25 | 0 | UINT64_C(0), |
26 | 0 | UINT64_C(0), |
27 | 0 | UINT64_C(0), |
28 | 0 | UINT64_C(0), |
29 | 0 | UINT64_C(0), |
30 | 0 | UINT64_C(0), |
31 | 0 | UINT64_C(0), |
32 | 0 | UINT64_C(0), |
33 | 0 | UINT64_C(0), |
34 | 0 | UINT64_C(0), |
35 | 0 | UINT64_C(0), |
36 | 0 | UINT64_C(0), |
37 | 0 | UINT64_C(0), |
38 | 0 | UINT64_C(0), |
39 | 0 | UINT64_C(0), |
40 | 0 | UINT64_C(0), |
41 | 0 | UINT64_C(0), |
42 | 0 | UINT64_C(0), |
43 | 0 | UINT64_C(0), |
44 | 0 | UINT64_C(0), |
45 | 0 | UINT64_C(0), |
46 | 0 | UINT64_C(0), |
47 | 0 | UINT64_C(0), |
48 | 0 | UINT64_C(0), |
49 | 0 | UINT64_C(0), |
50 | 0 | UINT64_C(0), |
51 | 0 | UINT64_C(0), |
52 | 0 | UINT64_C(0), |
53 | 0 | UINT64_C(0), |
54 | 0 | UINT64_C(0), |
55 | 0 | UINT64_C(0), |
56 | 0 | UINT64_C(0), |
57 | 0 | UINT64_C(0), |
58 | 0 | UINT64_C(0), |
59 | 0 | UINT64_C(0), |
60 | 0 | UINT64_C(0), |
61 | 0 | UINT64_C(0), |
62 | 0 | UINT64_C(0), |
63 | 0 | UINT64_C(0), |
64 | 0 | UINT64_C(0), |
65 | 0 | UINT64_C(0), |
66 | 0 | UINT64_C(0), |
67 | 0 | UINT64_C(0), |
68 | 0 | UINT64_C(0), |
69 | 0 | UINT64_C(0), |
70 | 0 | UINT64_C(0), |
71 | 0 | UINT64_C(0), |
72 | 0 | UINT64_C(0), |
73 | 0 | UINT64_C(0), |
74 | 0 | UINT64_C(0), |
75 | 0 | UINT64_C(0), |
76 | 0 | UINT64_C(0), |
77 | 0 | UINT64_C(0), |
78 | 0 | UINT64_C(0), |
79 | 0 | UINT64_C(0), |
80 | 0 | UINT64_C(0), |
81 | 0 | UINT64_C(0), |
82 | 0 | UINT64_C(0), |
83 | 0 | UINT64_C(0), |
84 | 0 | UINT64_C(0), |
85 | 0 | UINT64_C(0), |
86 | 0 | UINT64_C(0), |
87 | 0 | UINT64_C(0), |
88 | 0 | UINT64_C(0), |
89 | 0 | UINT64_C(0), |
90 | 0 | UINT64_C(0), |
91 | 0 | UINT64_C(0), |
92 | 0 | UINT64_C(0), |
93 | 0 | UINT64_C(0), |
94 | 0 | UINT64_C(0), |
95 | 0 | UINT64_C(0), |
96 | 0 | UINT64_C(0), |
97 | 0 | UINT64_C(0), |
98 | 0 | UINT64_C(0), |
99 | 0 | UINT64_C(0), |
100 | 0 | UINT64_C(0), |
101 | 0 | UINT64_C(0), |
102 | 0 | UINT64_C(0), |
103 | 0 | UINT64_C(0), |
104 | 0 | UINT64_C(0), |
105 | 0 | UINT64_C(0), |
106 | 0 | UINT64_C(0), |
107 | 0 | UINT64_C(0), |
108 | 0 | UINT64_C(0), |
109 | 0 | UINT64_C(0), |
110 | 0 | UINT64_C(0), |
111 | 0 | UINT64_C(0), |
112 | 0 | UINT64_C(0), |
113 | 0 | UINT64_C(0), |
114 | 0 | UINT64_C(0), |
115 | 0 | UINT64_C(0), |
116 | 0 | UINT64_C(0), |
117 | 0 | UINT64_C(0), |
118 | 0 | UINT64_C(0), |
119 | 0 | UINT64_C(0), |
120 | 0 | UINT64_C(0), |
121 | 0 | UINT64_C(0), |
122 | 0 | UINT64_C(0), |
123 | 0 | UINT64_C(0), |
124 | 0 | UINT64_C(0), |
125 | 0 | UINT64_C(0), |
126 | 0 | UINT64_C(0), |
127 | 0 | UINT64_C(0), |
128 | 0 | UINT64_C(0), |
129 | 0 | UINT64_C(0), |
130 | 0 | UINT64_C(0), |
131 | 0 | UINT64_C(0), |
132 | 0 | UINT64_C(0), |
133 | 0 | UINT64_C(0), |
134 | 0 | UINT64_C(0), |
135 | 0 | UINT64_C(0), |
136 | 0 | UINT64_C(0), |
137 | 0 | UINT64_C(0), |
138 | 0 | UINT64_C(0), |
139 | 0 | UINT64_C(0), |
140 | 0 | UINT64_C(0), |
141 | 0 | UINT64_C(0), |
142 | 0 | UINT64_C(0), |
143 | 0 | UINT64_C(0), |
144 | 0 | UINT64_C(0), |
145 | 0 | UINT64_C(0), |
146 | 0 | UINT64_C(0), |
147 | 0 | UINT64_C(0), |
148 | 0 | UINT64_C(0), |
149 | 0 | UINT64_C(0), |
150 | 0 | UINT64_C(0), |
151 | 0 | UINT64_C(0), |
152 | 0 | UINT64_C(0), |
153 | 0 | UINT64_C(0), |
154 | 0 | UINT64_C(0), |
155 | 0 | UINT64_C(0), |
156 | 0 | UINT64_C(0), |
157 | 0 | UINT64_C(0), |
158 | 0 | UINT64_C(0), |
159 | 0 | UINT64_C(0), |
160 | 0 | UINT64_C(0), |
161 | 0 | UINT64_C(0), |
162 | 0 | UINT64_C(0), |
163 | 0 | UINT64_C(0), |
164 | 0 | UINT64_C(0), |
165 | 0 | UINT64_C(0), |
166 | 0 | UINT64_C(0), |
167 | 0 | UINT64_C(0), |
168 | 0 | UINT64_C(0), |
169 | 0 | UINT64_C(0), |
170 | 0 | UINT64_C(0), |
171 | 0 | UINT64_C(0), |
172 | 0 | UINT64_C(0), |
173 | 0 | UINT64_C(0), |
174 | 0 | UINT64_C(0), |
175 | 0 | UINT64_C(0), |
176 | 0 | UINT64_C(0), |
177 | 0 | UINT64_C(0), |
178 | 0 | UINT64_C(0), |
179 | 0 | UINT64_C(0), |
180 | 0 | UINT64_C(0), |
181 | 0 | UINT64_C(0), |
182 | 0 | UINT64_C(0), |
183 | 0 | UINT64_C(0), |
184 | 0 | UINT64_C(0), |
185 | 0 | UINT64_C(0), |
186 | 0 | UINT64_C(0), |
187 | 0 | UINT64_C(0), |
188 | 0 | UINT64_C(0), |
189 | 0 | UINT64_C(0), |
190 | 0 | UINT64_C(0), |
191 | 0 | UINT64_C(0), |
192 | 0 | UINT64_C(0), |
193 | 0 | UINT64_C(0), |
194 | 0 | UINT64_C(0), |
195 | 0 | UINT64_C(0), |
196 | 0 | UINT64_C(0), |
197 | 0 | UINT64_C(0), |
198 | 0 | UINT64_C(0), |
199 | 0 | UINT64_C(0), |
200 | 0 | UINT64_C(0), |
201 | 0 | UINT64_C(0), |
202 | 0 | UINT64_C(0), |
203 | 0 | UINT64_C(0), |
204 | 0 | UINT64_C(0), |
205 | 0 | UINT64_C(0), |
206 | 0 | UINT64_C(0), |
207 | 0 | UINT64_C(0), |
208 | 0 | UINT64_C(0), |
209 | 0 | UINT64_C(0), |
210 | 0 | UINT64_C(0), |
211 | 0 | UINT64_C(0), |
212 | 0 | UINT64_C(0), |
213 | 0 | UINT64_C(0), |
214 | 0 | UINT64_C(0), |
215 | 0 | UINT64_C(0), |
216 | 0 | UINT64_C(0), |
217 | 0 | UINT64_C(0), |
218 | 0 | UINT64_C(0), |
219 | 0 | UINT64_C(0), |
220 | 0 | UINT64_C(0), |
221 | 0 | UINT64_C(0), |
222 | 0 | UINT64_C(0), |
223 | 0 | UINT64_C(0), |
224 | 0 | UINT64_C(0), |
225 | 0 | UINT64_C(0), |
226 | 0 | UINT64_C(0), |
227 | 0 | UINT64_C(0), |
228 | 0 | UINT64_C(0), |
229 | 0 | UINT64_C(0), |
230 | 0 | UINT64_C(0), |
231 | 0 | UINT64_C(0), |
232 | 0 | UINT64_C(0), |
233 | 0 | UINT64_C(0), |
234 | 0 | UINT64_C(0), |
235 | 0 | UINT64_C(0), |
236 | 0 | UINT64_C(0), |
237 | 0 | UINT64_C(0), |
238 | 0 | UINT64_C(0), |
239 | 0 | UINT64_C(0), |
240 | 0 | UINT64_C(0), |
241 | 0 | UINT64_C(0), |
242 | 0 | UINT64_C(0), |
243 | 0 | UINT64_C(0), |
244 | 0 | UINT64_C(0), |
245 | 0 | UINT64_C(0), |
246 | 0 | UINT64_C(0), |
247 | 0 | UINT64_C(0), |
248 | 0 | UINT64_C(0), |
249 | 0 | UINT64_C(0), |
250 | 0 | UINT64_C(0), |
251 | 0 | UINT64_C(0), |
252 | 0 | UINT64_C(0), |
253 | 0 | UINT64_C(0), |
254 | 0 | UINT64_C(0), |
255 | 0 | UINT64_C(0), |
256 | 0 | UINT64_C(0), |
257 | 0 | UINT64_C(0), |
258 | 0 | UINT64_C(0), |
259 | 0 | UINT64_C(0), |
260 | 0 | UINT64_C(0), |
261 | 0 | UINT64_C(0), |
262 | 0 | UINT64_C(0), |
263 | 0 | UINT64_C(0), |
264 | 0 | UINT64_C(0), |
265 | 0 | UINT64_C(0), |
266 | 0 | UINT64_C(0), |
267 | 0 | UINT64_C(0), |
268 | 0 | UINT64_C(0), |
269 | 0 | UINT64_C(0), |
270 | 0 | UINT64_C(0), |
271 | 0 | UINT64_C(0), |
272 | 0 | UINT64_C(0), |
273 | 0 | UINT64_C(0), |
274 | 0 | UINT64_C(0), |
275 | 0 | UINT64_C(0), |
276 | 0 | UINT64_C(0), |
277 | 0 | UINT64_C(0), |
278 | 0 | UINT64_C(0), |
279 | 0 | UINT64_C(0), |
280 | 0 | UINT64_C(0), |
281 | 0 | UINT64_C(0), |
282 | 0 | UINT64_C(0), |
283 | 0 | UINT64_C(0), |
284 | 0 | UINT64_C(0), |
285 | 0 | UINT64_C(0), |
286 | 0 | UINT64_C(0), |
287 | 0 | UINT64_C(0), |
288 | 0 | UINT64_C(0), |
289 | 0 | UINT64_C(0), |
290 | 0 | UINT64_C(0), |
291 | 0 | UINT64_C(0), |
292 | 0 | UINT64_C(0), |
293 | 0 | UINT64_C(0), |
294 | 0 | UINT64_C(0), |
295 | 0 | UINT64_C(0), |
296 | 0 | UINT64_C(0), |
297 | 0 | UINT64_C(0), |
298 | 0 | UINT64_C(0), |
299 | 0 | UINT64_C(0), |
300 | 0 | UINT64_C(0), |
301 | 0 | UINT64_C(0), |
302 | 0 | UINT64_C(0), |
303 | 0 | UINT64_C(0), |
304 | 0 | UINT64_C(0), |
305 | 0 | UINT64_C(0), |
306 | 0 | UINT64_C(0), |
307 | 0 | UINT64_C(0), |
308 | 0 | UINT64_C(0), |
309 | 0 | UINT64_C(0), |
310 | 0 | UINT64_C(0), |
311 | 0 | UINT64_C(0), |
312 | 0 | UINT64_C(0), |
313 | 0 | UINT64_C(0), |
314 | 0 | UINT64_C(0), |
315 | 0 | UINT64_C(0), |
316 | 0 | UINT64_C(0), |
317 | 0 | UINT64_C(0), |
318 | 0 | UINT64_C(0), |
319 | 0 | UINT64_C(0), |
320 | 0 | UINT64_C(0), |
321 | 0 | UINT64_C(0), |
322 | 0 | UINT64_C(0), |
323 | 0 | UINT64_C(0), |
324 | 0 | UINT64_C(0), |
325 | 0 | UINT64_C(0), |
326 | 0 | UINT64_C(0), |
327 | 0 | UINT64_C(0), |
328 | 0 | UINT64_C(0), |
329 | 0 | UINT64_C(0), |
330 | 0 | UINT64_C(0), |
331 | 0 | UINT64_C(0), |
332 | 0 | UINT64_C(0), |
333 | 0 | UINT64_C(0), |
334 | 0 | UINT64_C(0), |
335 | 0 | UINT64_C(0), |
336 | 0 | UINT64_C(0), |
337 | 0 | UINT64_C(0), |
338 | 0 | UINT64_C(0), |
339 | 0 | UINT64_C(0), |
340 | 0 | UINT64_C(0), |
341 | 0 | UINT64_C(0), |
342 | 0 | UINT64_C(0), |
343 | 0 | UINT64_C(0), |
344 | 0 | UINT64_C(0), |
345 | 0 | UINT64_C(0), |
346 | 0 | UINT64_C(0), |
347 | 0 | UINT64_C(0), |
348 | 0 | UINT64_C(0), |
349 | 0 | UINT64_C(0), |
350 | 0 | UINT64_C(0), |
351 | 0 | UINT64_C(0), |
352 | 0 | UINT64_C(0), |
353 | 0 | UINT64_C(0), |
354 | 0 | UINT64_C(0), |
355 | 0 | UINT64_C(0), |
356 | 0 | UINT64_C(0), |
357 | 0 | UINT64_C(0), |
358 | 0 | UINT64_C(0), |
359 | 0 | UINT64_C(0), |
360 | 0 | UINT64_C(0), |
361 | 0 | UINT64_C(0), |
362 | 0 | UINT64_C(0), |
363 | 0 | UINT64_C(0), |
364 | 0 | UINT64_C(0), |
365 | 0 | UINT64_C(0), |
366 | 0 | UINT64_C(0), |
367 | 0 | UINT64_C(0), |
368 | 0 | UINT64_C(0), |
369 | 0 | UINT64_C(0), |
370 | 0 | UINT64_C(0), |
371 | 0 | UINT64_C(0), |
372 | 0 | UINT64_C(0), |
373 | 0 | UINT64_C(0), |
374 | 0 | UINT64_C(0), |
375 | 0 | UINT64_C(0), |
376 | 0 | UINT64_C(0), |
377 | 0 | UINT64_C(0), |
378 | 0 | UINT64_C(0), |
379 | 0 | UINT64_C(0), |
380 | 0 | UINT64_C(0), |
381 | 0 | UINT64_C(0), |
382 | 0 | UINT64_C(0), |
383 | 0 | UINT64_C(0), |
384 | 0 | UINT64_C(0), |
385 | 0 | UINT64_C(0), |
386 | 0 | UINT64_C(0), |
387 | 0 | UINT64_C(0), |
388 | 0 | UINT64_C(0), |
389 | 0 | UINT64_C(0), |
390 | 0 | UINT64_C(0), |
391 | 0 | UINT64_C(0), |
392 | 0 | UINT64_C(0), |
393 | 0 | UINT64_C(0), |
394 | 0 | UINT64_C(0), |
395 | 0 | UINT64_C(0), |
396 | 0 | UINT64_C(0), |
397 | 0 | UINT64_C(0), |
398 | 0 | UINT64_C(0), |
399 | 0 | UINT64_C(0), |
400 | 0 | UINT64_C(0), |
401 | 0 | UINT64_C(0), |
402 | 0 | UINT64_C(0), |
403 | 0 | UINT64_C(0), |
404 | 0 | UINT64_C(0), |
405 | 0 | UINT64_C(0), |
406 | 0 | UINT64_C(0), |
407 | 0 | UINT64_C(0), |
408 | 0 | UINT64_C(0), |
409 | 0 | UINT64_C(0), |
410 | 0 | UINT64_C(0), |
411 | 0 | UINT64_C(0), |
412 | 0 | UINT64_C(0), |
413 | 0 | UINT64_C(0), |
414 | 0 | UINT64_C(0), |
415 | 0 | UINT64_C(0), |
416 | 0 | UINT64_C(0), |
417 | 0 | UINT64_C(0), |
418 | 0 | UINT64_C(0), |
419 | 0 | UINT64_C(0), |
420 | 0 | UINT64_C(0), |
421 | 0 | UINT64_C(0), |
422 | 0 | UINT64_C(0), |
423 | 0 | UINT64_C(0), |
424 | 0 | UINT64_C(0), |
425 | 0 | UINT64_C(0), |
426 | 0 | UINT64_C(0), |
427 | 0 | UINT64_C(0), |
428 | 0 | UINT64_C(0), |
429 | 0 | UINT64_C(0), |
430 | 0 | UINT64_C(0), |
431 | 0 | UINT64_C(0), |
432 | 0 | UINT64_C(0), |
433 | 0 | UINT64_C(0), |
434 | 0 | UINT64_C(0), |
435 | 0 | UINT64_C(0), |
436 | 0 | UINT64_C(0), |
437 | 0 | UINT64_C(0), |
438 | 0 | UINT64_C(0), |
439 | 0 | UINT64_C(0), |
440 | 0 | UINT64_C(0), |
441 | 0 | UINT64_C(0), |
442 | 0 | UINT64_C(0), |
443 | 0 | UINT64_C(0), |
444 | 0 | UINT64_C(0), |
445 | 0 | UINT64_C(0), |
446 | 0 | UINT64_C(0), |
447 | 0 | UINT64_C(0), |
448 | 0 | UINT64_C(0), |
449 | 0 | UINT64_C(0), |
450 | 0 | UINT64_C(0), |
451 | 0 | UINT64_C(0), |
452 | 0 | UINT64_C(0), |
453 | 0 | UINT64_C(0), |
454 | 0 | UINT64_C(0), |
455 | 0 | UINT64_C(0), |
456 | 0 | UINT64_C(0), |
457 | 0 | UINT64_C(0), |
458 | 0 | UINT64_C(0), |
459 | 0 | UINT64_C(0), |
460 | 0 | UINT64_C(0), |
461 | 0 | UINT64_C(0), |
462 | 0 | UINT64_C(0), |
463 | 0 | UINT64_C(0), |
464 | 0 | UINT64_C(0), |
465 | 0 | UINT64_C(0), |
466 | 0 | UINT64_C(0), |
467 | 0 | UINT64_C(0), |
468 | 0 | UINT64_C(0), |
469 | 0 | UINT64_C(0), |
470 | 0 | UINT64_C(0), |
471 | 0 | UINT64_C(0), |
472 | 0 | UINT64_C(0), |
473 | 0 | UINT64_C(0), |
474 | 0 | UINT64_C(0), |
475 | 0 | UINT64_C(0), |
476 | 0 | UINT64_C(0), |
477 | 0 | UINT64_C(0), |
478 | 0 | UINT64_C(0), |
479 | 0 | UINT64_C(0), |
480 | 0 | UINT64_C(0), |
481 | 0 | UINT64_C(0), |
482 | 0 | UINT64_C(0), |
483 | 0 | UINT64_C(0), |
484 | 0 | UINT64_C(0), |
485 | 0 | UINT64_C(0), |
486 | 0 | UINT64_C(0), |
487 | 0 | UINT64_C(0), |
488 | 0 | UINT64_C(0), |
489 | 0 | UINT64_C(0), |
490 | 0 | UINT64_C(0), |
491 | 0 | UINT64_C(0), |
492 | 0 | UINT64_C(0), |
493 | 0 | UINT64_C(0), |
494 | 0 | UINT64_C(0), |
495 | 0 | UINT64_C(0), |
496 | 0 | UINT64_C(0), |
497 | 0 | UINT64_C(0), |
498 | 0 | UINT64_C(0), |
499 | 0 | UINT64_C(0), |
500 | 0 | UINT64_C(0), |
501 | 0 | UINT64_C(0), |
502 | 0 | UINT64_C(0), |
503 | 0 | UINT64_C(0), |
504 | 0 | UINT64_C(0), |
505 | 0 | UINT64_C(0), |
506 | 0 | UINT64_C(1509949440), // A |
507 | 0 | UINT64_C(1778384896), // AD |
508 | 0 | UINT64_C(260584255782938), // ADB |
509 | 0 | UINT64_C(3004825600), // ADBR |
510 | 0 | UINT64_C(10752), // ADR |
511 | 0 | UINT64_C(3016884224), // ADTR |
512 | 0 | UINT64_C(3016884224), // ADTRA |
513 | 0 | UINT64_C(2046820352), // AE |
514 | 0 | UINT64_C(260584255782922), // AEB |
515 | 0 | UINT64_C(3003777024), // AEBR |
516 | 0 | UINT64_C(14848), // AER |
517 | 0 | UINT64_C(213343910494208), // AFI |
518 | 0 | UINT64_C(249589139505160), // AG |
519 | 0 | UINT64_C(249589139505176), // AGF |
520 | 0 | UINT64_C(213339615526912), // AGFI |
521 | 0 | UINT64_C(3105357824), // AGFR |
522 | 0 | UINT64_C(249589139505208), // AGH |
523 | 0 | UINT64_C(2802515968), // AGHI |
524 | 0 | UINT64_C(259484744155353), // AGHIK |
525 | 0 | UINT64_C(3104309248), // AGR |
526 | 0 | UINT64_C(3118989312), // AGRK |
527 | 0 | UINT64_C(258385232527482), // AGSI |
528 | 0 | UINT64_C(1241513984), // AH |
529 | 0 | UINT64_C(3116892160), // AHHHR |
530 | 0 | UINT64_C(3117940736), // AHHLR |
531 | 0 | UINT64_C(2802450432), // AHI |
532 | 0 | UINT64_C(259484744155352), // AHIK |
533 | 0 | UINT64_C(249589139505274), // AHY |
534 | 0 | UINT64_C(224334731804672), // AIH |
535 | 0 | UINT64_C(1577058304), // AL |
536 | 0 | UINT64_C(249589139505304), // ALC |
537 | 0 | UINT64_C(249589139505288), // ALCG |
538 | 0 | UINT64_C(3112697856), // ALCGR |
539 | 0 | UINT64_C(3113746432), // ALCR |
540 | 0 | UINT64_C(213352500428800), // ALFI |
541 | 0 | UINT64_C(249589139505162), // ALG |
542 | 0 | UINT64_C(249589139505178), // ALGF |
543 | 0 | UINT64_C(213348205461504), // ALGFI |
544 | 0 | UINT64_C(3105488896), // ALGFR |
545 | 0 | UINT64_C(259484744155355), // ALGHSIK |
546 | 0 | UINT64_C(3104440320), // ALGR |
547 | 0 | UINT64_C(3119120384), // ALGRK |
548 | 0 | UINT64_C(258385232527486), // ALGSI |
549 | 0 | UINT64_C(3117023232), // ALHHHR |
550 | 0 | UINT64_C(3118071808), // ALHHLR |
551 | 0 | UINT64_C(259484744155354), // ALHSIK |
552 | 0 | UINT64_C(7680), // ALR |
553 | 0 | UINT64_C(3120168960), // ALRK |
554 | 0 | UINT64_C(258385232527470), // ALSI |
555 | 0 | UINT64_C(224343321739264), // ALSIH |
556 | 0 | UINT64_C(224347616706560), // ALSIHN |
557 | 0 | UINT64_C(249589139505246), // ALY |
558 | 0 | UINT64_C(274877906944000), // AP |
559 | 0 | UINT64_C(6656), // AR |
560 | 0 | UINT64_C(3120037888), // ARK |
561 | 0 | UINT64_C(258385232527466), // ASI |
562 | 0 | UINT64_C(2113929216), // AU |
563 | 0 | UINT64_C(15872), // AUR |
564 | 0 | UINT64_C(1845493760), // AW |
565 | 0 | UINT64_C(11776), // AWR |
566 | 0 | UINT64_C(3007971328), // AXBR |
567 | 0 | UINT64_C(13824), // AXR |
568 | 0 | UINT64_C(3017408512), // AXTR |
569 | 0 | UINT64_C(3017408512), // AXTRA |
570 | 0 | UINT64_C(249589139505242), // AY |
571 | 0 | UINT64_C(1206910976), // B |
572 | 0 | UINT64_C(2990538752), // BAKR |
573 | 0 | UINT64_C(1157627904), // BAL |
574 | 0 | UINT64_C(1280), // BALR |
575 | 0 | UINT64_C(1291845632), // BAS |
576 | 0 | UINT64_C(3328), // BASR |
577 | 0 | UINT64_C(3072), // BASSM |
578 | 0 | UINT64_C(1199570944), // BAsmE |
579 | 0 | UINT64_C(1193279488), // BAsmH |
580 | 0 | UINT64_C(1201668096), // BAsmHE |
581 | 0 | UINT64_C(1195376640), // BAsmL |
582 | 0 | UINT64_C(1203765248), // BAsmLE |
583 | 0 | UINT64_C(1197473792), // BAsmLH |
584 | 0 | UINT64_C(1195376640), // BAsmM |
585 | 0 | UINT64_C(1198522368), // BAsmNE |
586 | 0 | UINT64_C(1204813824), // BAsmNH |
587 | 0 | UINT64_C(1196425216), // BAsmNHE |
588 | 0 | UINT64_C(1202716672), // BAsmNL |
589 | 0 | UINT64_C(1194328064), // BAsmNLE |
590 | 0 | UINT64_C(1200619520), // BAsmNLH |
591 | 0 | UINT64_C(1202716672), // BAsmNM |
592 | 0 | UINT64_C(1205862400), // BAsmNO |
593 | 0 | UINT64_C(1204813824), // BAsmNP |
594 | 0 | UINT64_C(1198522368), // BAsmNZ |
595 | 0 | UINT64_C(1192230912), // BAsmO |
596 | 0 | UINT64_C(1193279488), // BAsmP |
597 | 0 | UINT64_C(1199570944), // BAsmZ |
598 | 0 | UINT64_C(1191182336), // BC |
599 | 0 | UINT64_C(1191182336), // BCAsm |
600 | 0 | UINT64_C(1792), // BCR |
601 | 0 | UINT64_C(1792), // BCRAsm |
602 | 0 | UINT64_C(1174405120), // BCT |
603 | 0 | UINT64_C(249589139505222), // BCTG |
604 | 0 | UINT64_C(3108372480), // BCTGR |
605 | 0 | UINT64_C(1536), // BCTR |
606 | 0 | UINT64_C(250619931656263), // BI |
607 | 0 | UINT64_C(250138895319111), // BIAsmE |
608 | 0 | UINT64_C(249726578458695), // BIAsmH |
609 | 0 | UINT64_C(250276334272583), // BIAsmHE |
610 | 0 | UINT64_C(249864017412167), // BIAsmL |
611 | 0 | UINT64_C(250413773226055), // BIAsmLE |
612 | 0 | UINT64_C(250001456365639), // BIAsmLH |
613 | 0 | UINT64_C(249864017412167), // BIAsmM |
614 | 0 | UINT64_C(250070175842375), // BIAsmNE |
615 | 0 | UINT64_C(250482492702791), // BIAsmNH |
616 | 0 | UINT64_C(249932736888903), // BIAsmNHE |
617 | 0 | UINT64_C(250345053749319), // BIAsmNL |
618 | 0 | UINT64_C(249795297935431), // BIAsmNLE |
619 | 0 | UINT64_C(250207614795847), // BIAsmNLH |
620 | 0 | UINT64_C(250345053749319), // BIAsmNM |
621 | 0 | UINT64_C(250551212179527), // BIAsmNO |
622 | 0 | UINT64_C(250482492702791), // BIAsmNP |
623 | 0 | UINT64_C(250070175842375), // BIAsmNZ |
624 | 0 | UINT64_C(249657858981959), // BIAsmO |
625 | 0 | UINT64_C(249726578458695), // BIAsmP |
626 | 0 | UINT64_C(250138895319111), // BIAsmZ |
627 | 0 | UINT64_C(249589139505223), // BIC |
628 | 0 | UINT64_C(249589139505223), // BICAsm |
629 | 0 | UINT64_C(218802813927424), // BPP |
630 | 0 | UINT64_C(216603790671872), // BPRP |
631 | 0 | UINT64_C(2032), // BR |
632 | 0 | UINT64_C(2802122752), // BRAS |
633 | 0 | UINT64_C(211127707369472), // BRASL |
634 | 0 | UINT64_C(1920), // BRAsmE |
635 | 0 | UINT64_C(1824), // BRAsmH |
636 | 0 | UINT64_C(1952), // BRAsmHE |
637 | 0 | UINT64_C(1856), // BRAsmL |
638 | 0 | UINT64_C(1984), // BRAsmLE |
639 | 0 | UINT64_C(1888), // BRAsmLH |
640 | 0 | UINT64_C(1856), // BRAsmM |
641 | 0 | UINT64_C(1904), // BRAsmNE |
642 | 0 | UINT64_C(2000), // BRAsmNH |
643 | 0 | UINT64_C(1872), // BRAsmNHE |
644 | 0 | UINT64_C(1968), // BRAsmNL |
645 | 0 | UINT64_C(1840), // BRAsmNLE |
646 | 0 | UINT64_C(1936), // BRAsmNLH |
647 | 0 | UINT64_C(1968), // BRAsmNM |
648 | 0 | UINT64_C(2016), // BRAsmNO |
649 | 0 | UINT64_C(2000), // BRAsmNP |
650 | 0 | UINT64_C(1904), // BRAsmNZ |
651 | 0 | UINT64_C(1808), // BRAsmO |
652 | 0 | UINT64_C(1824), // BRAsmP |
653 | 0 | UINT64_C(1920), // BRAsmZ |
654 | 0 | UINT64_C(2802057216), // BRC |
655 | 0 | UINT64_C(2802057216), // BRCAsm |
656 | 0 | UINT64_C(211123412402176), // BRCL |
657 | 0 | UINT64_C(211123412402176), // BRCLAsm |
658 | 0 | UINT64_C(2802188288), // BRCT |
659 | 0 | UINT64_C(2802253824), // BRCTG |
660 | 0 | UINT64_C(224326141870080), // BRCTH |
661 | 0 | UINT64_C(2214592512), // BRXH |
662 | 0 | UINT64_C(259484744155204), // BRXHG |
663 | 0 | UINT64_C(2231369728), // BRXLE |
664 | 0 | UINT64_C(259484744155205), // BRXLG |
665 | 0 | UINT64_C(2992242688), // BSA |
666 | 0 | UINT64_C(2992111616), // BSG |
667 | 0 | UINT64_C(2816), // BSM |
668 | 0 | UINT64_C(2248146944), // BXH |
669 | 0 | UINT64_C(258385232527428), // BXHG |
670 | 0 | UINT64_C(2264924160), // BXLE |
671 | 0 | UINT64_C(258385232527429), // BXLEG |
672 | 0 | UINT64_C(1493172224), // C |
673 | 0 | UINT64_C(1761607680), // CD |
674 | 0 | UINT64_C(260584255782937), // CDB |
675 | 0 | UINT64_C(3004760064), // CDBR |
676 | 0 | UINT64_C(3012886528), // CDFBR |
677 | 0 | UINT64_C(3012886528), // CDFBRA |
678 | 0 | UINT64_C(3014983680), // CDFR |
679 | 0 | UINT64_C(3109093376), // CDFTR |
680 | 0 | UINT64_C(3013935104), // CDGBR |
681 | 0 | UINT64_C(3013935104), // CDGBRA |
682 | 0 | UINT64_C(3016032256), // CDGR |
683 | 0 | UINT64_C(3018915840), // CDGTR |
684 | 0 | UINT64_C(3018915840), // CDGTRA |
685 | 0 | UINT64_C(3012624384), // CDLFBR |
686 | 0 | UINT64_C(3109224448), // CDLFTR |
687 | 0 | UINT64_C(3013672960), // CDLGBR |
688 | 0 | UINT64_C(3109158912), // CDLGTR |
689 | 0 | UINT64_C(260584255783086), // CDPT |
690 | 0 | UINT64_C(10496), // CDR |
691 | 0 | UINT64_C(3137339392), // CDS |
692 | 0 | UINT64_C(258385232527422), // CDSG |
693 | 0 | UINT64_C(3019046912), // CDSTR |
694 | 0 | UINT64_C(258385232527409), // CDSY |
695 | 0 | UINT64_C(3018063872), // CDTR |
696 | 0 | UINT64_C(3018981376), // CDUTR |
697 | 0 | UINT64_C(260584255783082), // CDZT |
698 | 0 | UINT64_C(2030043136), // CE |
699 | 0 | UINT64_C(260584255782921), // CEB |
700 | 0 | UINT64_C(3003711488), // CEBR |
701 | 0 | UINT64_C(3019112448), // CEDTR |
702 | 0 | UINT64_C(3012820992), // CEFBR |
703 | 0 | UINT64_C(3012820992), // CEFBRA |
704 | 0 | UINT64_C(3014918144), // CEFR |
705 | 0 | UINT64_C(3013869568), // CEGBR |
706 | 0 | UINT64_C(3013869568), // CEGBRA |
707 | 0 | UINT64_C(3015966720), // CEGR |
708 | 0 | UINT64_C(3012558848), // CELFBR |
709 | 0 | UINT64_C(3013607424), // CELGBR |
710 | 0 | UINT64_C(14592), // CER |
711 | 0 | UINT64_C(3019636736), // CEXTR |
712 | 0 | UINT64_C(2988048384), // CFC |
713 | 0 | UINT64_C(3013148672), // CFDBR |
714 | 0 | UINT64_C(3013148672), // CFDBRA |
715 | 0 | UINT64_C(3015245824), // CFDR |
716 | 0 | UINT64_C(3108044800), // CFDTR |
717 | 0 | UINT64_C(3013083136), // CFEBR |
718 | 0 | UINT64_C(3013083136), // CFEBRA |
719 | 0 | UINT64_C(3015180288), // CFER |
720 | 0 | UINT64_C(213361090363392), // CFI |
721 | 0 | UINT64_C(3013214208), // CFXBR |
722 | 0 | UINT64_C(3013214208), // CFXBRA |
723 | 0 | UINT64_C(3015311360), // CFXR |
724 | 0 | UINT64_C(3108569088), // CFXTR |
725 | 0 | UINT64_C(249589139505184), // CG |
726 | 0 | UINT64_C(3014197248), // CGDBR |
727 | 0 | UINT64_C(3014197248), // CGDBRA |
728 | 0 | UINT64_C(3016294400), // CGDR |
729 | 0 | UINT64_C(3017867264), // CGDTR |
730 | 0 | UINT64_C(3017867264), // CGDTRA |
731 | 0 | UINT64_C(3014131712), // CGEBR |
732 | 0 | UINT64_C(3014131712), // CGEBRA |
733 | 0 | UINT64_C(3016228864), // CGER |
734 | 0 | UINT64_C(249589139505200), // CGF |
735 | 0 | UINT64_C(213356795396096), // CGFI |
736 | 0 | UINT64_C(3106930688), // CGFR |
737 | 0 | UINT64_C(217754841907200), // CGFRL |
738 | 0 | UINT64_C(249589139505204), // CGH |
739 | 0 | UINT64_C(2802778112), // CGHI |
740 | 0 | UINT64_C(217720482168832), // CGHRL |
741 | 0 | UINT64_C(252166119882752), // CGHSI |
742 | 0 | UINT64_C(259484744155388), // CGIB |
743 | 0 | UINT64_C(259484744155388), // CGIBAsm |
744 | 0 | UINT64_C(259519103893756), // CGIBAsmE |
745 | 0 | UINT64_C(259493334089980), // CGIBAsmH |
746 | 0 | UINT64_C(259527693828348), // CGIBAsmHE |
747 | 0 | UINT64_C(259501924024572), // CGIBAsmL |
748 | 0 | UINT64_C(259536283762940), // CGIBAsmLE |
749 | 0 | UINT64_C(259510513959164), // CGIBAsmLH |
750 | 0 | UINT64_C(259510513959164), // CGIBAsmNE |
751 | 0 | UINT64_C(259536283762940), // CGIBAsmNH |
752 | 0 | UINT64_C(259501924024572), // CGIBAsmNHE |
753 | 0 | UINT64_C(259527693828348), // CGIBAsmNL |
754 | 0 | UINT64_C(259493334089980), // CGIBAsmNLE |
755 | 0 | UINT64_C(259519103893756), // CGIBAsmNLH |
756 | 0 | UINT64_C(259484744155260), // CGIJ |
757 | 0 | UINT64_C(259484744155260), // CGIJAsm |
758 | 0 | UINT64_C(259519103893628), // CGIJAsmE |
759 | 0 | UINT64_C(259493334089852), // CGIJAsmH |
760 | 0 | UINT64_C(259527693828220), // CGIJAsmHE |
761 | 0 | UINT64_C(259501924024444), // CGIJAsmL |
762 | 0 | UINT64_C(259536283762812), // CGIJAsmLE |
763 | 0 | UINT64_C(259510513959036), // CGIJAsmLH |
764 | 0 | UINT64_C(259510513959036), // CGIJAsmNE |
765 | 0 | UINT64_C(259536283762812), // CGIJAsmNH |
766 | 0 | UINT64_C(259501924024444), // CGIJAsmNHE |
767 | 0 | UINT64_C(259527693828220), // CGIJAsmNL |
768 | 0 | UINT64_C(259493334089852), // CGIJAsmNLE |
769 | 0 | UINT64_C(259519103893628), // CGIJAsmNLH |
770 | 0 | UINT64_C(259484744155248), // CGIT |
771 | 0 | UINT64_C(259484744155248), // CGITAsm |
772 | 0 | UINT64_C(259484744188016), // CGITAsmE |
773 | 0 | UINT64_C(259484744163440), // CGITAsmH |
774 | 0 | UINT64_C(259484744196208), // CGITAsmHE |
775 | 0 | UINT64_C(259484744171632), // CGITAsmL |
776 | 0 | UINT64_C(259484744204400), // CGITAsmLE |
777 | 0 | UINT64_C(259484744179824), // CGITAsmLH |
778 | 0 | UINT64_C(259484744179824), // CGITAsmNE |
779 | 0 | UINT64_C(259484744204400), // CGITAsmNH |
780 | 0 | UINT64_C(259484744171632), // CGITAsmNHE |
781 | 0 | UINT64_C(259484744196208), // CGITAsmNL |
782 | 0 | UINT64_C(259484744163440), // CGITAsmNLE |
783 | 0 | UINT64_C(259484744188016), // CGITAsmNLH |
784 | 0 | UINT64_C(3105882112), // CGR |
785 | 0 | UINT64_C(259484744155364), // CGRB |
786 | 0 | UINT64_C(259484744155364), // CGRBAsm |
787 | 0 | UINT64_C(259484744188132), // CGRBAsmE |
788 | 0 | UINT64_C(259484744163556), // CGRBAsmH |
789 | 0 | UINT64_C(259484744196324), // CGRBAsmHE |
790 | 0 | UINT64_C(259484744171748), // CGRBAsmL |
791 | 0 | UINT64_C(259484744204516), // CGRBAsmLE |
792 | 0 | UINT64_C(259484744179940), // CGRBAsmLH |
793 | 0 | UINT64_C(259484744179940), // CGRBAsmNE |
794 | 0 | UINT64_C(259484744204516), // CGRBAsmNH |
795 | 0 | UINT64_C(259484744171748), // CGRBAsmNHE |
796 | 0 | UINT64_C(259484744196324), // CGRBAsmNL |
797 | 0 | UINT64_C(259484744163556), // CGRBAsmNLE |
798 | 0 | UINT64_C(259484744188132), // CGRBAsmNLH |
799 | 0 | UINT64_C(259484744155236), // CGRJ |
800 | 0 | UINT64_C(259484744155236), // CGRJAsm |
801 | 0 | UINT64_C(259484744188004), // CGRJAsmE |
802 | 0 | UINT64_C(259484744163428), // CGRJAsmH |
803 | 0 | UINT64_C(259484744196196), // CGRJAsmHE |
804 | 0 | UINT64_C(259484744171620), // CGRJAsmL |
805 | 0 | UINT64_C(259484744204388), // CGRJAsmLE |
806 | 0 | UINT64_C(259484744179812), // CGRJAsmLH |
807 | 0 | UINT64_C(259484744179812), // CGRJAsmNE |
808 | 0 | UINT64_C(259484744204388), // CGRJAsmNH |
809 | 0 | UINT64_C(259484744171620), // CGRJAsmNHE |
810 | 0 | UINT64_C(259484744196196), // CGRJAsmNL |
811 | 0 | UINT64_C(259484744163428), // CGRJAsmNLE |
812 | 0 | UINT64_C(259484744188004), // CGRJAsmNLH |
813 | 0 | UINT64_C(217737662038016), // CGRL |
814 | 0 | UINT64_C(3110076416), // CGRT |
815 | 0 | UINT64_C(3110076416), // CGRTAsm |
816 | 0 | UINT64_C(3110109184), // CGRTAsmE |
817 | 0 | UINT64_C(3110084608), // CGRTAsmH |
818 | 0 | UINT64_C(3110117376), // CGRTAsmHE |
819 | 0 | UINT64_C(3110092800), // CGRTAsmL |
820 | 0 | UINT64_C(3110125568), // CGRTAsmLE |
821 | 0 | UINT64_C(3110100992), // CGRTAsmLH |
822 | 0 | UINT64_C(3110100992), // CGRTAsmNE |
823 | 0 | UINT64_C(3110125568), // CGRTAsmNH |
824 | 0 | UINT64_C(3110092800), // CGRTAsmNHE |
825 | 0 | UINT64_C(3110117376), // CGRTAsmNL |
826 | 0 | UINT64_C(3110084608), // CGRTAsmNLE |
827 | 0 | UINT64_C(3110109184), // CGRTAsmNLH |
828 | 0 | UINT64_C(3014262784), // CGXBR |
829 | 0 | UINT64_C(3014262784), // CGXBRA |
830 | 0 | UINT64_C(3016359936), // CGXR |
831 | 0 | UINT64_C(3018391552), // CGXTR |
832 | 0 | UINT64_C(3018391552), // CGXTRA |
833 | 0 | UINT64_C(1224736768), // CH |
834 | 0 | UINT64_C(249589139505357), // CHF |
835 | 0 | UINT64_C(3117219840), // CHHR |
836 | 0 | UINT64_C(252148940013568), // CHHSI |
837 | 0 | UINT64_C(2802712576), // CHI |
838 | 0 | UINT64_C(3118268416), // CHLR |
839 | 0 | UINT64_C(217724777136128), // CHRL |
840 | 0 | UINT64_C(252183299751936), // CHSI |
841 | 0 | UINT64_C(249589139505273), // CHY |
842 | 0 | UINT64_C(259484744155390), // CIB |
843 | 0 | UINT64_C(259484744155390), // CIBAsm |
844 | 0 | UINT64_C(259519103893758), // CIBAsmE |
845 | 0 | UINT64_C(259493334089982), // CIBAsmH |
846 | 0 | UINT64_C(259527693828350), // CIBAsmHE |
847 | 0 | UINT64_C(259501924024574), // CIBAsmL |
848 | 0 | UINT64_C(259536283762942), // CIBAsmLE |
849 | 0 | UINT64_C(259510513959166), // CIBAsmLH |
850 | 0 | UINT64_C(259510513959166), // CIBAsmNE |
851 | 0 | UINT64_C(259536283762942), // CIBAsmNH |
852 | 0 | UINT64_C(259501924024574), // CIBAsmNHE |
853 | 0 | UINT64_C(259527693828350), // CIBAsmNL |
854 | 0 | UINT64_C(259493334089982), // CIBAsmNLE |
855 | 0 | UINT64_C(259519103893758), // CIBAsmNLH |
856 | 0 | UINT64_C(224356206641152), // CIH |
857 | 0 | UINT64_C(259484744155262), // CIJ |
858 | 0 | UINT64_C(259484744155262), // CIJAsm |
859 | 0 | UINT64_C(259519103893630), // CIJAsmE |
860 | 0 | UINT64_C(259493334089854), // CIJAsmH |
861 | 0 | UINT64_C(259527693828222), // CIJAsmHE |
862 | 0 | UINT64_C(259501924024446), // CIJAsmL |
863 | 0 | UINT64_C(259536283762814), // CIJAsmLE |
864 | 0 | UINT64_C(259510513959038), // CIJAsmLH |
865 | 0 | UINT64_C(259510513959038), // CIJAsmNE |
866 | 0 | UINT64_C(259536283762814), // CIJAsmNH |
867 | 0 | UINT64_C(259501924024446), // CIJAsmNHE |
868 | 0 | UINT64_C(259527693828222), // CIJAsmNL |
869 | 0 | UINT64_C(259493334089854), // CIJAsmNLE |
870 | 0 | UINT64_C(259519103893630), // CIJAsmNLH |
871 | 0 | UINT64_C(259484744155250), // CIT |
872 | 0 | UINT64_C(259484744155250), // CITAsm |
873 | 0 | UINT64_C(259484744188018), // CITAsmE |
874 | 0 | UINT64_C(259484744163442), // CITAsmH |
875 | 0 | UINT64_C(259484744196210), // CITAsmHE |
876 | 0 | UINT64_C(259484744171634), // CITAsmL |
877 | 0 | UINT64_C(259484744204402), // CITAsmLE |
878 | 0 | UINT64_C(259484744179826), // CITAsmLH |
879 | 0 | UINT64_C(259484744179826), // CITAsmNE |
880 | 0 | UINT64_C(259484744204402), // CITAsmNH |
881 | 0 | UINT64_C(259484744171634), // CITAsmNHE |
882 | 0 | UINT64_C(259484744196210), // CITAsmNL |
883 | 0 | UINT64_C(259484744163442), // CITAsmNLE |
884 | 0 | UINT64_C(259484744188018), // CITAsmNLH |
885 | 0 | UINT64_C(2990604288), // CKSM |
886 | 0 | UINT64_C(1426063360), // CL |
887 | 0 | UINT64_C(234195976716288), // CLC |
888 | 0 | UINT64_C(3840), // CLCL |
889 | 0 | UINT64_C(2835349504), // CLCLE |
890 | 0 | UINT64_C(258385232527503), // CLCLU |
891 | 0 | UINT64_C(3013410816), // CLFDBR |
892 | 0 | UINT64_C(3108175872), // CLFDTR |
893 | 0 | UINT64_C(3013345280), // CLFEBR |
894 | 0 | UINT64_C(252187594719232), // CLFHSI |
895 | 0 | UINT64_C(213369680297984), // CLFI |
896 | 0 | UINT64_C(259484744155251), // CLFIT |
897 | 0 | UINT64_C(259484744155251), // CLFITAsm |
898 | 0 | UINT64_C(259484744188019), // CLFITAsmE |
899 | 0 | UINT64_C(259484744163443), // CLFITAsmH |
900 | 0 | UINT64_C(259484744196211), // CLFITAsmHE |
901 | 0 | UINT64_C(259484744171635), // CLFITAsmL |
902 | 0 | UINT64_C(259484744204403), // CLFITAsmLE |
903 | 0 | UINT64_C(259484744179827), // CLFITAsmLH |
904 | 0 | UINT64_C(259484744179827), // CLFITAsmNE |
905 | 0 | UINT64_C(259484744204403), // CLFITAsmNH |
906 | 0 | UINT64_C(259484744171635), // CLFITAsmNHE |
907 | 0 | UINT64_C(259484744196211), // CLFITAsmNL |
908 | 0 | UINT64_C(259484744163443), // CLFITAsmNLE |
909 | 0 | UINT64_C(259484744188019), // CLFITAsmNLH |
910 | 0 | UINT64_C(3013476352), // CLFXBR |
911 | 0 | UINT64_C(3108700160), // CLFXTR |
912 | 0 | UINT64_C(249589139505185), // CLG |
913 | 0 | UINT64_C(3014459392), // CLGDBR |
914 | 0 | UINT64_C(3108110336), // CLGDTR |
915 | 0 | UINT64_C(3014393856), // CLGEBR |
916 | 0 | UINT64_C(249589139505201), // CLGF |
917 | 0 | UINT64_C(213365385330688), // CLGFI |
918 | 0 | UINT64_C(3106996224), // CLGFR |
919 | 0 | UINT64_C(217763431841792), // CLGFRL |
920 | 0 | UINT64_C(217729072103424), // CLGHRL |
921 | 0 | UINT64_C(252170414850048), // CLGHSI |
922 | 0 | UINT64_C(259484744155389), // CLGIB |
923 | 0 | UINT64_C(259484744155389), // CLGIBAsm |
924 | 0 | UINT64_C(259519103893757), // CLGIBAsmE |
925 | 0 | UINT64_C(259493334089981), // CLGIBAsmH |
926 | 0 | UINT64_C(259527693828349), // CLGIBAsmHE |
927 | 0 | UINT64_C(259501924024573), // CLGIBAsmL |
928 | 0 | UINT64_C(259536283762941), // CLGIBAsmLE |
929 | 0 | UINT64_C(259510513959165), // CLGIBAsmLH |
930 | 0 | UINT64_C(259510513959165), // CLGIBAsmNE |
931 | 0 | UINT64_C(259536283762941), // CLGIBAsmNH |
932 | 0 | UINT64_C(259501924024573), // CLGIBAsmNHE |
933 | 0 | UINT64_C(259527693828349), // CLGIBAsmNL |
934 | 0 | UINT64_C(259493334089981), // CLGIBAsmNLE |
935 | 0 | UINT64_C(259519103893757), // CLGIBAsmNLH |
936 | 0 | UINT64_C(259484744155261), // CLGIJ |
937 | 0 | UINT64_C(259484744155261), // CLGIJAsm |
938 | 0 | UINT64_C(259519103893629), // CLGIJAsmE |
939 | 0 | UINT64_C(259493334089853), // CLGIJAsmH |
940 | 0 | UINT64_C(259527693828221), // CLGIJAsmHE |
941 | 0 | UINT64_C(259501924024445), // CLGIJAsmL |
942 | 0 | UINT64_C(259536283762813), // CLGIJAsmLE |
943 | 0 | UINT64_C(259510513959037), // CLGIJAsmLH |
944 | 0 | UINT64_C(259510513959037), // CLGIJAsmNE |
945 | 0 | UINT64_C(259536283762813), // CLGIJAsmNH |
946 | 0 | UINT64_C(259501924024445), // CLGIJAsmNHE |
947 | 0 | UINT64_C(259527693828221), // CLGIJAsmNL |
948 | 0 | UINT64_C(259493334089853), // CLGIJAsmNLE |
949 | 0 | UINT64_C(259519103893629), // CLGIJAsmNLH |
950 | 0 | UINT64_C(259484744155249), // CLGIT |
951 | 0 | UINT64_C(259484744155249), // CLGITAsm |
952 | 0 | UINT64_C(259484744188017), // CLGITAsmE |
953 | 0 | UINT64_C(259484744163441), // CLGITAsmH |
954 | 0 | UINT64_C(259484744196209), // CLGITAsmHE |
955 | 0 | UINT64_C(259484744171633), // CLGITAsmL |
956 | 0 | UINT64_C(259484744204401), // CLGITAsmLE |
957 | 0 | UINT64_C(259484744179825), // CLGITAsmLH |
958 | 0 | UINT64_C(259484744179825), // CLGITAsmNE |
959 | 0 | UINT64_C(259484744204401), // CLGITAsmNH |
960 | 0 | UINT64_C(259484744171633), // CLGITAsmNHE |
961 | 0 | UINT64_C(259484744196209), // CLGITAsmNL |
962 | 0 | UINT64_C(259484744163441), // CLGITAsmNLE |
963 | 0 | UINT64_C(259484744188017), // CLGITAsmNLH |
964 | 0 | UINT64_C(3105947648), // CLGR |
965 | 0 | UINT64_C(259484744155365), // CLGRB |
966 | 0 | UINT64_C(259484744155365), // CLGRBAsm |
967 | 0 | UINT64_C(259484744188133), // CLGRBAsmE |
968 | 0 | UINT64_C(259484744163557), // CLGRBAsmH |
969 | 0 | UINT64_C(259484744196325), // CLGRBAsmHE |
970 | 0 | UINT64_C(259484744171749), // CLGRBAsmL |
971 | 0 | UINT64_C(259484744204517), // CLGRBAsmLE |
972 | 0 | UINT64_C(259484744179941), // CLGRBAsmLH |
973 | 0 | UINT64_C(259484744179941), // CLGRBAsmNE |
974 | 0 | UINT64_C(259484744204517), // CLGRBAsmNH |
975 | 0 | UINT64_C(259484744171749), // CLGRBAsmNHE |
976 | 0 | UINT64_C(259484744196325), // CLGRBAsmNL |
977 | 0 | UINT64_C(259484744163557), // CLGRBAsmNLE |
978 | 0 | UINT64_C(259484744188133), // CLGRBAsmNLH |
979 | 0 | UINT64_C(259484744155237), // CLGRJ |
980 | 0 | UINT64_C(259484744155237), // CLGRJAsm |
981 | 0 | UINT64_C(259484744188005), // CLGRJAsmE |
982 | 0 | UINT64_C(259484744163429), // CLGRJAsmH |
983 | 0 | UINT64_C(259484744196197), // CLGRJAsmHE |
984 | 0 | UINT64_C(259484744171621), // CLGRJAsmL |
985 | 0 | UINT64_C(259484744204389), // CLGRJAsmLE |
986 | 0 | UINT64_C(259484744179813), // CLGRJAsmLH |
987 | 0 | UINT64_C(259484744179813), // CLGRJAsmNE |
988 | 0 | UINT64_C(259484744204389), // CLGRJAsmNH |
989 | 0 | UINT64_C(259484744171621), // CLGRJAsmNHE |
990 | 0 | UINT64_C(259484744196197), // CLGRJAsmNL |
991 | 0 | UINT64_C(259484744163429), // CLGRJAsmNLE |
992 | 0 | UINT64_C(259484744188005), // CLGRJAsmNLH |
993 | 0 | UINT64_C(217746251972608), // CLGRL |
994 | 0 | UINT64_C(3110141952), // CLGRT |
995 | 0 | UINT64_C(3110141952), // CLGRTAsm |
996 | 0 | UINT64_C(3110174720), // CLGRTAsmE |
997 | 0 | UINT64_C(3110150144), // CLGRTAsmH |
998 | 0 | UINT64_C(3110182912), // CLGRTAsmHE |
999 | 0 | UINT64_C(3110158336), // CLGRTAsmL |
1000 | 0 | UINT64_C(3110191104), // CLGRTAsmLE |
1001 | 0 | UINT64_C(3110166528), // CLGRTAsmLH |
1002 | 0 | UINT64_C(3110166528), // CLGRTAsmNE |
1003 | 0 | UINT64_C(3110191104), // CLGRTAsmNH |
1004 | 0 | UINT64_C(3110158336), // CLGRTAsmNHE |
1005 | 0 | UINT64_C(3110182912), // CLGRTAsmNL |
1006 | 0 | UINT64_C(3110150144), // CLGRTAsmNLE |
1007 | 0 | UINT64_C(3110174720), // CLGRTAsmNLH |
1008 | 0 | UINT64_C(258385232527403), // CLGT |
1009 | 0 | UINT64_C(258385232527403), // CLGTAsm |
1010 | 0 | UINT64_C(258419592265771), // CLGTAsmE |
1011 | 0 | UINT64_C(258393822461995), // CLGTAsmH |
1012 | 0 | UINT64_C(258428182200363), // CLGTAsmHE |
1013 | 0 | UINT64_C(258402412396587), // CLGTAsmL |
1014 | 0 | UINT64_C(258436772134955), // CLGTAsmLE |
1015 | 0 | UINT64_C(258411002331179), // CLGTAsmLH |
1016 | 0 | UINT64_C(258411002331179), // CLGTAsmNE |
1017 | 0 | UINT64_C(258436772134955), // CLGTAsmNH |
1018 | 0 | UINT64_C(258402412396587), // CLGTAsmNHE |
1019 | 0 | UINT64_C(258428182200363), // CLGTAsmNL |
1020 | 0 | UINT64_C(258393822461995), // CLGTAsmNLE |
1021 | 0 | UINT64_C(258419592265771), // CLGTAsmNLH |
1022 | 0 | UINT64_C(3014524928), // CLGXBR |
1023 | 0 | UINT64_C(3108634624), // CLGXTR |
1024 | 0 | UINT64_C(249589139505359), // CLHF |
1025 | 0 | UINT64_C(3117350912), // CLHHR |
1026 | 0 | UINT64_C(252153234980864), // CLHHSI |
1027 | 0 | UINT64_C(3118399488), // CLHLR |
1028 | 0 | UINT64_C(217733367070720), // CLHRL |
1029 | 0 | UINT64_C(2499805184), // CLI |
1030 | 0 | UINT64_C(259484744155391), // CLIB |
1031 | 0 | UINT64_C(259484744155391), // CLIBAsm |
1032 | 0 | UINT64_C(259519103893759), // CLIBAsmE |
1033 | 0 | UINT64_C(259493334089983), // CLIBAsmH |
1034 | 0 | UINT64_C(259527693828351), // CLIBAsmHE |
1035 | 0 | UINT64_C(259501924024575), // CLIBAsmL |
1036 | 0 | UINT64_C(259536283762943), // CLIBAsmLE |
1037 | 0 | UINT64_C(259510513959167), // CLIBAsmLH |
1038 | 0 | UINT64_C(259510513959167), // CLIBAsmNE |
1039 | 0 | UINT64_C(259536283762943), // CLIBAsmNH |
1040 | 0 | UINT64_C(259501924024575), // CLIBAsmNHE |
1041 | 0 | UINT64_C(259527693828351), // CLIBAsmNL |
1042 | 0 | UINT64_C(259493334089983), // CLIBAsmNLE |
1043 | 0 | UINT64_C(259519103893759), // CLIBAsmNLH |
1044 | 0 | UINT64_C(224364796575744), // CLIH |
1045 | 0 | UINT64_C(259484744155263), // CLIJ |
1046 | 0 | UINT64_C(259484744155263), // CLIJAsm |
1047 | 0 | UINT64_C(259519103893631), // CLIJAsmE |
1048 | 0 | UINT64_C(259493334089855), // CLIJAsmH |
1049 | 0 | UINT64_C(259527693828223), // CLIJAsmHE |
1050 | 0 | UINT64_C(259501924024447), // CLIJAsmL |
1051 | 0 | UINT64_C(259536283762815), // CLIJAsmLE |
1052 | 0 | UINT64_C(259510513959039), // CLIJAsmLH |
1053 | 0 | UINT64_C(259510513959039), // CLIJAsmNE |
1054 | 0 | UINT64_C(259536283762815), // CLIJAsmNH |
1055 | 0 | UINT64_C(259501924024447), // CLIJAsmNHE |
1056 | 0 | UINT64_C(259527693828223), // CLIJAsmNL |
1057 | 0 | UINT64_C(259493334089855), // CLIJAsmNLE |
1058 | 0 | UINT64_C(259519103893631), // CLIJAsmNLH |
1059 | 0 | UINT64_C(258385232527445), // CLIY |
1060 | 0 | UINT64_C(3170893824), // CLM |
1061 | 0 | UINT64_C(258385232527392), // CLMH |
1062 | 0 | UINT64_C(258385232527393), // CLMY |
1063 | 0 | UINT64_C(5376), // CLR |
1064 | 0 | UINT64_C(259484744155383), // CLRB |
1065 | 0 | UINT64_C(259484744155383), // CLRBAsm |
1066 | 0 | UINT64_C(259484744188151), // CLRBAsmE |
1067 | 0 | UINT64_C(259484744163575), // CLRBAsmH |
1068 | 0 | UINT64_C(259484744196343), // CLRBAsmHE |
1069 | 0 | UINT64_C(259484744171767), // CLRBAsmL |
1070 | 0 | UINT64_C(259484744204535), // CLRBAsmLE |
1071 | 0 | UINT64_C(259484744179959), // CLRBAsmLH |
1072 | 0 | UINT64_C(259484744179959), // CLRBAsmNE |
1073 | 0 | UINT64_C(259484744204535), // CLRBAsmNH |
1074 | 0 | UINT64_C(259484744171767), // CLRBAsmNHE |
1075 | 0 | UINT64_C(259484744196343), // CLRBAsmNL |
1076 | 0 | UINT64_C(259484744163575), // CLRBAsmNLE |
1077 | 0 | UINT64_C(259484744188151), // CLRBAsmNLH |
1078 | 0 | UINT64_C(259484744155255), // CLRJ |
1079 | 0 | UINT64_C(259484744155255), // CLRJAsm |
1080 | 0 | UINT64_C(259484744188023), // CLRJAsmE |
1081 | 0 | UINT64_C(259484744163447), // CLRJAsmH |
1082 | 0 | UINT64_C(259484744196215), // CLRJAsmHE |
1083 | 0 | UINT64_C(259484744171639), // CLRJAsmL |
1084 | 0 | UINT64_C(259484744204407), // CLRJAsmLE |
1085 | 0 | UINT64_C(259484744179831), // CLRJAsmLH |
1086 | 0 | UINT64_C(259484744179831), // CLRJAsmNE |
1087 | 0 | UINT64_C(259484744204407), // CLRJAsmNH |
1088 | 0 | UINT64_C(259484744171639), // CLRJAsmNHE |
1089 | 0 | UINT64_C(259484744196215), // CLRJAsmNL |
1090 | 0 | UINT64_C(259484744163447), // CLRJAsmNLE |
1091 | 0 | UINT64_C(259484744188023), // CLRJAsmNLH |
1092 | 0 | UINT64_C(217767726809088), // CLRL |
1093 | 0 | UINT64_C(3111321600), // CLRT |
1094 | 0 | UINT64_C(3111321600), // CLRTAsm |
1095 | 0 | UINT64_C(3111354368), // CLRTAsmE |
1096 | 0 | UINT64_C(3111329792), // CLRTAsmH |
1097 | 0 | UINT64_C(3111362560), // CLRTAsmHE |
1098 | 0 | UINT64_C(3111337984), // CLRTAsmL |
1099 | 0 | UINT64_C(3111370752), // CLRTAsmLE |
1100 | 0 | UINT64_C(3111346176), // CLRTAsmLH |
1101 | 0 | UINT64_C(3111346176), // CLRTAsmNE |
1102 | 0 | UINT64_C(3111370752), // CLRTAsmNH |
1103 | 0 | UINT64_C(3111337984), // CLRTAsmNHE |
1104 | 0 | UINT64_C(3111362560), // CLRTAsmNL |
1105 | 0 | UINT64_C(3111329792), // CLRTAsmNLE |
1106 | 0 | UINT64_C(3111354368), // CLRTAsmNLH |
1107 | 0 | UINT64_C(2992439296), // CLST |
1108 | 0 | UINT64_C(258385232527395), // CLT |
1109 | 0 | UINT64_C(258385232527395), // CLTAsm |
1110 | 0 | UINT64_C(258419592265763), // CLTAsmE |
1111 | 0 | UINT64_C(258393822461987), // CLTAsmH |
1112 | 0 | UINT64_C(258428182200355), // CLTAsmHE |
1113 | 0 | UINT64_C(258402412396579), // CLTAsmL |
1114 | 0 | UINT64_C(258436772134947), // CLTAsmLE |
1115 | 0 | UINT64_C(258411002331171), // CLTAsmLH |
1116 | 0 | UINT64_C(258411002331171), // CLTAsmNE |
1117 | 0 | UINT64_C(258436772134947), // CLTAsmNH |
1118 | 0 | UINT64_C(258402412396579), // CLTAsmNHE |
1119 | 0 | UINT64_C(258428182200355), // CLTAsmNL |
1120 | 0 | UINT64_C(258393822461987), // CLTAsmNLE |
1121 | 0 | UINT64_C(258419592265763), // CLTAsmNLH |
1122 | 0 | UINT64_C(249589139505237), // CLY |
1123 | 0 | UINT64_C(2992832512), // CMPSC |
1124 | 0 | UINT64_C(273778395316224), // CP |
1125 | 0 | UINT64_C(260584255783084), // CPDT |
1126 | 0 | UINT64_C(3010592768), // CPSDRdd |
1127 | 0 | UINT64_C(3010592768), // CPSDRds |
1128 | 0 | UINT64_C(3010592768), // CPSDRsd |
1129 | 0 | UINT64_C(3010592768), // CPSDRss |
1130 | 0 | UINT64_C(260584255783085), // CPXT |
1131 | 0 | UINT64_C(2991390720), // CPYA |
1132 | 0 | UINT64_C(6400), // CR |
1133 | 0 | UINT64_C(259484744155382), // CRB |
1134 | 0 | UINT64_C(259484744155382), // CRBAsm |
1135 | 0 | UINT64_C(259484744188150), // CRBAsmE |
1136 | 0 | UINT64_C(259484744163574), // CRBAsmH |
1137 | 0 | UINT64_C(259484744196342), // CRBAsmHE |
1138 | 0 | UINT64_C(259484744171766), // CRBAsmL |
1139 | 0 | UINT64_C(259484744204534), // CRBAsmLE |
1140 | 0 | UINT64_C(259484744179958), // CRBAsmLH |
1141 | 0 | UINT64_C(259484744179958), // CRBAsmNE |
1142 | 0 | UINT64_C(259484744204534), // CRBAsmNH |
1143 | 0 | UINT64_C(259484744171766), // CRBAsmNHE |
1144 | 0 | UINT64_C(259484744196342), // CRBAsmNL |
1145 | 0 | UINT64_C(259484744163574), // CRBAsmNLE |
1146 | 0 | UINT64_C(259484744188150), // CRBAsmNLH |
1147 | 0 | UINT64_C(3113156608), // CRDTE |
1148 | 0 | UINT64_C(3113156608), // CRDTEOpt |
1149 | 0 | UINT64_C(259484744155254), // CRJ |
1150 | 0 | UINT64_C(259484744155254), // CRJAsm |
1151 | 0 | UINT64_C(259484744188022), // CRJAsmE |
1152 | 0 | UINT64_C(259484744163446), // CRJAsmH |
1153 | 0 | UINT64_C(259484744196214), // CRJAsmHE |
1154 | 0 | UINT64_C(259484744171638), // CRJAsmL |
1155 | 0 | UINT64_C(259484744204406), // CRJAsmLE |
1156 | 0 | UINT64_C(259484744179830), // CRJAsmLH |
1157 | 0 | UINT64_C(259484744179830), // CRJAsmNE |
1158 | 0 | UINT64_C(259484744204406), // CRJAsmNH |
1159 | 0 | UINT64_C(259484744171638), // CRJAsmNHE |
1160 | 0 | UINT64_C(259484744196214), // CRJAsmNL |
1161 | 0 | UINT64_C(259484744163446), // CRJAsmNLE |
1162 | 0 | UINT64_C(259484744188022), // CRJAsmNLH |
1163 | 0 | UINT64_C(217759136874496), // CRL |
1164 | 0 | UINT64_C(3111256064), // CRT |
1165 | 0 | UINT64_C(3111256064), // CRTAsm |
1166 | 0 | UINT64_C(3111288832), // CRTAsmE |
1167 | 0 | UINT64_C(3111264256), // CRTAsmH |
1168 | 0 | UINT64_C(3111297024), // CRTAsmHE |
1169 | 0 | UINT64_C(3111272448), // CRTAsmL |
1170 | 0 | UINT64_C(3111305216), // CRTAsmLE |
1171 | 0 | UINT64_C(3111280640), // CRTAsmLH |
1172 | 0 | UINT64_C(3111280640), // CRTAsmNE |
1173 | 0 | UINT64_C(3111305216), // CRTAsmNH |
1174 | 0 | UINT64_C(3111272448), // CRTAsmNHE |
1175 | 0 | UINT64_C(3111297024), // CRTAsmNL |
1176 | 0 | UINT64_C(3111264256), // CRTAsmNLE |
1177 | 0 | UINT64_C(3111288832), // CRTAsmNLH |
1178 | 0 | UINT64_C(3120562176), // CS |
1179 | 0 | UINT64_C(2989490176), // CSCH |
1180 | 0 | UINT64_C(3017998336), // CSDTR |
1181 | 0 | UINT64_C(258385232527408), // CSG |
1182 | 0 | UINT64_C(2991587328), // CSP |
1183 | 0 | UINT64_C(3112828928), // CSPG |
1184 | 0 | UINT64_C(219910915489792), // CSST |
1185 | 0 | UINT64_C(3018522624), // CSXTR |
1186 | 0 | UINT64_C(258385232527380), // CSY |
1187 | 0 | UINT64_C(2997288960), // CU12 |
1188 | 0 | UINT64_C(2997288960), // CU12Opt |
1189 | 0 | UINT64_C(3115319296), // CU14 |
1190 | 0 | UINT64_C(3115319296), // CU14Opt |
1191 | 0 | UINT64_C(2997223424), // CU21 |
1192 | 0 | UINT64_C(2997223424), // CU21Opt |
1193 | 0 | UINT64_C(3115384832), // CU24 |
1194 | 0 | UINT64_C(3115384832), // CU24Opt |
1195 | 0 | UINT64_C(3115450368), // CU41 |
1196 | 0 | UINT64_C(3115515904), // CU42 |
1197 | 0 | UINT64_C(3017932800), // CUDTR |
1198 | 0 | UINT64_C(2992046080), // CUSE |
1199 | 0 | UINT64_C(2997288960), // CUTFU |
1200 | 0 | UINT64_C(2997288960), // CUTFUOpt |
1201 | 0 | UINT64_C(2997223424), // CUUTF |
1202 | 0 | UINT64_C(2997223424), // CUUTFOpt |
1203 | 0 | UINT64_C(3018457088), // CUXTR |
1204 | 0 | UINT64_C(1325400064), // CVB |
1205 | 0 | UINT64_C(249589139505166), // CVBG |
1206 | 0 | UINT64_C(249589139505158), // CVBY |
1207 | 0 | UINT64_C(1308622848), // CVD |
1208 | 0 | UINT64_C(249589139505198), // CVDG |
1209 | 0 | UINT64_C(249589139505190), // CVDY |
1210 | 0 | UINT64_C(3007905792), // CXBR |
1211 | 0 | UINT64_C(3012952064), // CXFBR |
1212 | 0 | UINT64_C(3012952064), // CXFBRA |
1213 | 0 | UINT64_C(3015049216), // CXFR |
1214 | 0 | UINT64_C(3109617664), // CXFTR |
1215 | 0 | UINT64_C(3014000640), // CXGBR |
1216 | 0 | UINT64_C(3014000640), // CXGBRA |
1217 | 0 | UINT64_C(3016097792), // CXGR |
1218 | 0 | UINT64_C(3019440128), // CXGTR |
1219 | 0 | UINT64_C(3019440128), // CXGTRA |
1220 | 0 | UINT64_C(3012689920), // CXLFBR |
1221 | 0 | UINT64_C(3109748736), // CXLFTR |
1222 | 0 | UINT64_C(3013738496), // CXLGBR |
1223 | 0 | UINT64_C(3109683200), // CXLGTR |
1224 | 0 | UINT64_C(260584255783087), // CXPT |
1225 | 0 | UINT64_C(3010002944), // CXR |
1226 | 0 | UINT64_C(3019571200), // CXSTR |
1227 | 0 | UINT64_C(3018588160), // CXTR |
1228 | 0 | UINT64_C(3019505664), // CXUTR |
1229 | 0 | UINT64_C(260584255783083), // CXZT |
1230 | 0 | UINT64_C(249589139505241), // CY |
1231 | 0 | UINT64_C(260584255783080), // CZDT |
1232 | 0 | UINT64_C(260584255783081), // CZXT |
1233 | 0 | UINT64_C(1560281088), // D |
1234 | 0 | UINT64_C(1828716544), // DD |
1235 | 0 | UINT64_C(260584255782941), // DDB |
1236 | 0 | UINT64_C(3005022208), // DDBR |
1237 | 0 | UINT64_C(11520), // DDR |
1238 | 0 | UINT64_C(3016818688), // DDTR |
1239 | 0 | UINT64_C(3016818688), // DDTRA |
1240 | 0 | UINT64_C(2097152000), // DE |
1241 | 0 | UINT64_C(260584255782925), // DEB |
1242 | 0 | UINT64_C(3003973632), // DEBR |
1243 | 0 | UINT64_C(15616), // DER |
1244 | 0 | UINT64_C(3107520512), // DFLTCC |
1245 | 0 | UINT64_C(2197815296), // DIAG |
1246 | 0 | UINT64_C(3009085440), // DIDBR |
1247 | 0 | UINT64_C(3008561152), // DIEBR |
1248 | 0 | UINT64_C(249589139505303), // DL |
1249 | 0 | UINT64_C(249589139505287), // DLG |
1250 | 0 | UINT64_C(3112632320), // DLGR |
1251 | 0 | UINT64_C(3113680896), // DLR |
1252 | 0 | UINT64_C(278176441827328), // DP |
1253 | 0 | UINT64_C(7424), // DR |
1254 | 0 | UINT64_C(249589139505165), // DSG |
1255 | 0 | UINT64_C(249589139505181), // DSGF |
1256 | 0 | UINT64_C(3105685504), // DSGFR |
1257 | 0 | UINT64_C(3104636928), // DSGR |
1258 | 0 | UINT64_C(3008167936), // DXBR |
1259 | 0 | UINT64_C(2989293568), // DXR |
1260 | 0 | UINT64_C(3017342976), // DXTR |
1261 | 0 | UINT64_C(3017342976), // DXTRA |
1262 | 0 | UINT64_C(2991521792), // EAR |
1263 | 0 | UINT64_C(258385232527436), // ECAG |
1264 | 0 | UINT64_C(3001286656), // ECCTR |
1265 | 0 | UINT64_C(3001876480), // ECPGA |
1266 | 0 | UINT64_C(219906620522496), // ECTG |
1267 | 0 | UINT64_C(244091581366272), // ED |
1268 | 0 | UINT64_C(245191092994048), // EDMK |
1269 | 0 | UINT64_C(3018129408), // EEDTR |
1270 | 0 | UINT64_C(3018653696), // EEXTR |
1271 | 0 | UINT64_C(3012296704), // EFPC |
1272 | 0 | UINT64_C(3113877504), // EPAIR |
1273 | 0 | UINT64_C(2988834816), // EPAR |
1274 | 0 | UINT64_C(3001352192), // EPCTR |
1275 | 0 | UINT64_C(3113025536), // EPSW |
1276 | 0 | UINT64_C(2991128576), // EREG |
1277 | 0 | UINT64_C(3104702464), // EREGG |
1278 | 0 | UINT64_C(3113943040), // ESAIR |
1279 | 0 | UINT64_C(2988900352), // ESAR |
1280 | 0 | UINT64_C(3018260480), // ESDTR |
1281 | 0 | UINT64_C(3114074112), // ESEA |
1282 | 0 | UINT64_C(2991194112), // ESTA |
1283 | 0 | UINT64_C(3018784768), // ESXTR |
1284 | 0 | UINT64_C(3001810944), // ETND |
1285 | 0 | UINT64_C(1140850688), // EX |
1286 | 0 | UINT64_C(217703302299648), // EXRL |
1287 | 0 | UINT64_C(3009347584), // FIDBR |
1288 | 0 | UINT64_C(3009347584), // FIDBRA |
1289 | 0 | UINT64_C(3011444736), // FIDR |
1290 | 0 | UINT64_C(3017211904), // FIDTR |
1291 | 0 | UINT64_C(3008823296), // FIEBR |
1292 | 0 | UINT64_C(3008823296), // FIEBRA |
1293 | 0 | UINT64_C(3010920448), // FIER |
1294 | 0 | UINT64_C(3007774720), // FIXBR |
1295 | 0 | UINT64_C(3007774720), // FIXBRA |
1296 | 0 | UINT64_C(3009871872), // FIXR |
1297 | 0 | UINT64_C(3017736192), // FIXTR |
1298 | 0 | UINT64_C(3112370176), // FLOGR |
1299 | 0 | UINT64_C(9216), // HDR |
1300 | 0 | UINT64_C(13312), // HER |
1301 | 0 | UINT64_C(2989555712), // HSCH |
1302 | 0 | UINT64_C(2988703744), // IAC |
1303 | 0 | UINT64_C(1124073472), // IC |
1304 | 0 | UINT64_C(1124073472), // IC32 |
1305 | 0 | UINT64_C(249589139505267), // IC32Y |
1306 | 0 | UINT64_C(3204448256), // ICM |
1307 | 0 | UINT64_C(258385232527488), // ICMH |
1308 | 0 | UINT64_C(258385232527489), // ICMY |
1309 | 0 | UINT64_C(249589139505267), // ICY |
1310 | 0 | UINT64_C(3113091072), // IDTE |
1311 | 0 | UINT64_C(3113091072), // IDTEOpt |
1312 | 0 | UINT64_C(3019243520), // IEDTR |
1313 | 0 | UINT64_C(3019767808), // IEXTR |
1314 | 0 | UINT64_C(211140592271360), // IIHF |
1315 | 0 | UINT64_C(2768240640), // IIHH |
1316 | 0 | UINT64_C(2768306176), // IIHL |
1317 | 0 | UINT64_C(211144887238656), // IILF |
1318 | 0 | UINT64_C(2768371712), // IILH |
1319 | 0 | UINT64_C(2768437248), // IILL |
1320 | 0 | UINT64_C(2987065344), // IPK |
1321 | 0 | UINT64_C(2988572672), // IPM |
1322 | 0 | UINT64_C(2988507136), // IPTE |
1323 | 0 | UINT64_C(2988507136), // IPTEOpt |
1324 | 0 | UINT64_C(2988507136), // IPTEOptOpt |
1325 | 0 | UINT64_C(3115057152), // IRBM |
1326 | 0 | UINT64_C(2989031424), // ISKE |
1327 | 0 | UINT64_C(2988638208), // IVSK |
1328 | 0 | UINT64_C(0), // InsnE |
1329 | 0 | UINT64_C(0), // InsnRI |
1330 | 0 | UINT64_C(0), // InsnRIE |
1331 | 0 | UINT64_C(0), // InsnRIL |
1332 | 0 | UINT64_C(0), // InsnRILU |
1333 | 0 | UINT64_C(0), // InsnRIS |
1334 | 0 | UINT64_C(0), // InsnRR |
1335 | 0 | UINT64_C(0), // InsnRRE |
1336 | 0 | UINT64_C(0), // InsnRRF |
1337 | 0 | UINT64_C(0), // InsnRRS |
1338 | 0 | UINT64_C(0), // InsnRS |
1339 | 0 | UINT64_C(0), // InsnRSE |
1340 | 0 | UINT64_C(0), // InsnRSI |
1341 | 0 | UINT64_C(0), // InsnRSY |
1342 | 0 | UINT64_C(0), // InsnRX |
1343 | 0 | UINT64_C(0), // InsnRXE |
1344 | 0 | UINT64_C(0), // InsnRXF |
1345 | 0 | UINT64_C(0), // InsnRXY |
1346 | 0 | UINT64_C(0), // InsnS |
1347 | 0 | UINT64_C(0), // InsnSI |
1348 | 0 | UINT64_C(0), // InsnSIL |
1349 | 0 | UINT64_C(0), // InsnSIY |
1350 | 0 | UINT64_C(0), // InsnSS |
1351 | 0 | UINT64_C(0), // InsnSSE |
1352 | 0 | UINT64_C(0), // InsnSSF |
1353 | 0 | UINT64_C(0), // InsnVRI |
1354 | 0 | UINT64_C(0), // InsnVRR |
1355 | 0 | UINT64_C(0), // InsnVRS |
1356 | 0 | UINT64_C(0), // InsnVRV |
1357 | 0 | UINT64_C(0), // InsnVRX |
1358 | 0 | UINT64_C(0), // InsnVSI |
1359 | 0 | UINT64_C(2817785856), // J |
1360 | 0 | UINT64_C(2810445824), // JAsmE |
1361 | 0 | UINT64_C(2804154368), // JAsmH |
1362 | 0 | UINT64_C(2812542976), // JAsmHE |
1363 | 0 | UINT64_C(2806251520), // JAsmL |
1364 | 0 | UINT64_C(2814640128), // JAsmLE |
1365 | 0 | UINT64_C(2808348672), // JAsmLH |
1366 | 0 | UINT64_C(2806251520), // JAsmM |
1367 | 0 | UINT64_C(2809397248), // JAsmNE |
1368 | 0 | UINT64_C(2815688704), // JAsmNH |
1369 | 0 | UINT64_C(2807300096), // JAsmNHE |
1370 | 0 | UINT64_C(2813591552), // JAsmNL |
1371 | 0 | UINT64_C(2805202944), // JAsmNLE |
1372 | 0 | UINT64_C(2811494400), // JAsmNLH |
1373 | 0 | UINT64_C(2813591552), // JAsmNM |
1374 | 0 | UINT64_C(2816737280), // JAsmNO |
1375 | 0 | UINT64_C(2815688704), // JAsmNP |
1376 | 0 | UINT64_C(2809397248), // JAsmNZ |
1377 | 0 | UINT64_C(2803105792), // JAsmO |
1378 | 0 | UINT64_C(2804154368), // JAsmP |
1379 | 0 | UINT64_C(2810445824), // JAsmZ |
1380 | 0 | UINT64_C(212154204553216), // JG |
1381 | 0 | UINT64_C(211673168216064), // JGAsmE |
1382 | 0 | UINT64_C(211260851355648), // JGAsmH |
1383 | 0 | UINT64_C(211810607169536), // JGAsmHE |
1384 | 0 | UINT64_C(211398290309120), // JGAsmL |
1385 | 0 | UINT64_C(211948046123008), // JGAsmLE |
1386 | 0 | UINT64_C(211535729262592), // JGAsmLH |
1387 | 0 | UINT64_C(211398290309120), // JGAsmM |
1388 | 0 | UINT64_C(211604448739328), // JGAsmNE |
1389 | 0 | UINT64_C(212016765599744), // JGAsmNH |
1390 | 0 | UINT64_C(211467009785856), // JGAsmNHE |
1391 | 0 | UINT64_C(211879326646272), // JGAsmNL |
1392 | 0 | UINT64_C(211329570832384), // JGAsmNLE |
1393 | 0 | UINT64_C(211741887692800), // JGAsmNLH |
1394 | 0 | UINT64_C(211879326646272), // JGAsmNM |
1395 | 0 | UINT64_C(212085485076480), // JGAsmNO |
1396 | 0 | UINT64_C(212016765599744), // JGAsmNP |
1397 | 0 | UINT64_C(211604448739328), // JGAsmNZ |
1398 | 0 | UINT64_C(211192131878912), // JGAsmO |
1399 | 0 | UINT64_C(211260851355648), // JGAsmP |
1400 | 0 | UINT64_C(211673168216064), // JGAsmZ |
1401 | 0 | UINT64_C(260584255782936), // KDB |
1402 | 0 | UINT64_C(3004694528), // KDBR |
1403 | 0 | UINT64_C(3107586048), // KDSA |
1404 | 0 | UINT64_C(3017801728), // KDTR |
1405 | 0 | UINT64_C(260584255782920), // KEB |
1406 | 0 | UINT64_C(3003645952), // KEBR |
1407 | 0 | UINT64_C(3107848192), // KIMD |
1408 | 0 | UINT64_C(3107913728), // KLMD |
1409 | 0 | UINT64_C(3106799616), // KM |
1410 | 0 | UINT64_C(3106471936), // KMA |
1411 | 0 | UINT64_C(3105751040), // KMAC |
1412 | 0 | UINT64_C(3106865152), // KMC |
1413 | 0 | UINT64_C(3106734080), // KMCTR |
1414 | 0 | UINT64_C(3106537472), // KMF |
1415 | 0 | UINT64_C(3106603008), // KMO |
1416 | 0 | UINT64_C(3007840256), // KXBR |
1417 | 0 | UINT64_C(3018326016), // KXTR |
1418 | 0 | UINT64_C(1476395008), // L |
1419 | 0 | UINT64_C(1090519040), // LA |
1420 | 0 | UINT64_C(258385232527608), // LAA |
1421 | 0 | UINT64_C(258385232527592), // LAAG |
1422 | 0 | UINT64_C(258385232527610), // LAAL |
1423 | 0 | UINT64_C(258385232527594), // LAALG |
1424 | 0 | UINT64_C(1358954496), // LAE |
1425 | 0 | UINT64_C(249589139505269), // LAEY |
1426 | 0 | UINT64_C(2583691264), // LAM |
1427 | 0 | UINT64_C(258385232527514), // LAMY |
1428 | 0 | UINT64_C(258385232527604), // LAN |
1429 | 0 | UINT64_C(258385232527588), // LANG |
1430 | 0 | UINT64_C(258385232527606), // LAO |
1431 | 0 | UINT64_C(258385232527590), // LAOG |
1432 | 0 | UINT64_C(211106232532992), // LARL |
1433 | 0 | UINT64_C(251788162760704), // LASP |
1434 | 0 | UINT64_C(249589139505311), // LAT |
1435 | 0 | UINT64_C(258385232527607), // LAX |
1436 | 0 | UINT64_C(258385232527591), // LAXG |
1437 | 0 | UINT64_C(249589139505265), // LAY |
1438 | 0 | UINT64_C(249589139505270), // LB |
1439 | 0 | UINT64_C(2986344448), // LBEAR |
1440 | 0 | UINT64_C(249589139505344), // LBH |
1441 | 0 | UINT64_C(3106275328), // LBR |
1442 | 0 | UINT64_C(253987186016295), // LCBB |
1443 | 0 | UINT64_C(2994995200), // LCCTL |
1444 | 0 | UINT64_C(3004366848), // LCDBR |
1445 | 0 | UINT64_C(3010658304), // LCDFR |
1446 | 0 | UINT64_C(3010658304), // LCDFR_32 |
1447 | 0 | UINT64_C(8960), // LCDR |
1448 | 0 | UINT64_C(3003318272), // LCEBR |
1449 | 0 | UINT64_C(13056), // LCER |
1450 | 0 | UINT64_C(3105030144), // LCGFR |
1451 | 0 | UINT64_C(3103981568), // LCGR |
1452 | 0 | UINT64_C(4864), // LCR |
1453 | 0 | UINT64_C(3070230528), // LCTL |
1454 | 0 | UINT64_C(258385232527407), // LCTLG |
1455 | 0 | UINT64_C(3007512576), // LCXBR |
1456 | 0 | UINT64_C(3009609728), // LCXR |
1457 | 0 | UINT64_C(1744830464), // LD |
1458 | 0 | UINT64_C(260584255782948), // LDE |
1459 | 0 | UINT64_C(260584255782948), // LDE32 |
1460 | 0 | UINT64_C(260584255782916), // LDEB |
1461 | 0 | UINT64_C(3003383808), // LDEBR |
1462 | 0 | UINT64_C(3005480960), // LDER |
1463 | 0 | UINT64_C(3017015296), // LDETR |
1464 | 0 | UINT64_C(3015770112), // LDGR |
1465 | 0 | UINT64_C(10240), // LDR |
1466 | 0 | UINT64_C(10240), // LDR32 |
1467 | 0 | UINT64_C(3007643648), // LDXBR |
1468 | 0 | UINT64_C(3007643648), // LDXBRA |
1469 | 0 | UINT64_C(9472), // LDXR |
1470 | 0 | UINT64_C(3017605120), // LDXTR |
1471 | 0 | UINT64_C(260584255783013), // LDY |
1472 | 0 | UINT64_C(2013265920), // LE |
1473 | 0 | UINT64_C(3007578112), // LEDBR |
1474 | 0 | UINT64_C(3007578112), // LEDBRA |
1475 | 0 | UINT64_C(13568), // LEDR |
1476 | 0 | UINT64_C(3017080832), // LEDTR |
1477 | 0 | UINT64_C(14336), // LER |
1478 | 0 | UINT64_C(3007709184), // LEXBR |
1479 | 0 | UINT64_C(3007709184), // LEXBRA |
1480 | 0 | UINT64_C(3009806336), // LEXR |
1481 | 0 | UINT64_C(260584255783012), // LEY |
1482 | 0 | UINT64_C(2998730752), // LFAS |
1483 | 0 | UINT64_C(249589139505354), // LFH |
1484 | 0 | UINT64_C(249589139505352), // LFHAT |
1485 | 0 | UINT64_C(2996633600), // LFPC |
1486 | 0 | UINT64_C(249589139505156), // LG |
1487 | 0 | UINT64_C(249589139505285), // LGAT |
1488 | 0 | UINT64_C(249589139505271), // LGB |
1489 | 0 | UINT64_C(3104178176), // LGBR |
1490 | 0 | UINT64_C(3016556544), // LGDR |
1491 | 0 | UINT64_C(249589139505172), // LGF |
1492 | 0 | UINT64_C(211110527500288), // LGFI |
1493 | 0 | UINT64_C(3105095680), // LGFR |
1494 | 0 | UINT64_C(215555818651648), // LGFRL |
1495 | 0 | UINT64_C(249589139505228), // LGG |
1496 | 0 | UINT64_C(249589139505173), // LGH |
1497 | 0 | UINT64_C(2802384896), // LGHI |
1498 | 0 | UINT64_C(3104243712), // LGHR |
1499 | 0 | UINT64_C(215521458913280), // LGHRL |
1500 | 0 | UINT64_C(3104047104), // LGR |
1501 | 0 | UINT64_C(215538638782464), // LGRL |
1502 | 0 | UINT64_C(249589139505229), // LGSC |
1503 | 0 | UINT64_C(1207959552), // LH |
1504 | 0 | UINT64_C(249589139505348), // LHH |
1505 | 0 | UINT64_C(2802319360), // LHI |
1506 | 0 | UINT64_C(3106340864), // LHR |
1507 | 0 | UINT64_C(215525753880576), // LHRL |
1508 | 0 | UINT64_C(249589139505272), // LHY |
1509 | 0 | UINT64_C(249589139505300), // LLC |
1510 | 0 | UINT64_C(249589139505346), // LLCH |
1511 | 0 | UINT64_C(3113484288), // LLCR |
1512 | 0 | UINT64_C(249589139505296), // LLGC |
1513 | 0 | UINT64_C(3112435712), // LLGCR |
1514 | 0 | UINT64_C(249589139505174), // LLGF |
1515 | 0 | UINT64_C(249589139505309), // LLGFAT |
1516 | 0 | UINT64_C(3105226752), // LLGFR |
1517 | 0 | UINT64_C(215564408586240), // LLGFRL |
1518 | 0 | UINT64_C(249589139505224), // LLGFSG |
1519 | 0 | UINT64_C(249589139505297), // LLGH |
1520 | 0 | UINT64_C(3112501248), // LLGHR |
1521 | 0 | UINT64_C(215530048847872), // LLGHRL |
1522 | 0 | UINT64_C(249589139505175), // LLGT |
1523 | 0 | UINT64_C(249589139505308), // LLGTAT |
1524 | 0 | UINT64_C(3105292288), // LLGTR |
1525 | 0 | UINT64_C(249589139505301), // LLH |
1526 | 0 | UINT64_C(249589139505350), // LLHH |
1527 | 0 | UINT64_C(3113549824), // LLHR |
1528 | 0 | UINT64_C(215512868978688), // LLHRL |
1529 | 0 | UINT64_C(211166362075136), // LLIHF |
1530 | 0 | UINT64_C(2769027072), // LLIHH |
1531 | 0 | UINT64_C(2769092608), // LLIHL |
1532 | 0 | UINT64_C(211170657042432), // LLILF |
1533 | 0 | UINT64_C(2769158144), // LLILH |
1534 | 0 | UINT64_C(2769223680), // LLILL |
1535 | 0 | UINT64_C(249589139505210), // LLZRGF |
1536 | 0 | UINT64_C(2550136832), // LM |
1537 | 0 | UINT64_C(262783279038464), // LMD |
1538 | 0 | UINT64_C(258385232527364), // LMG |
1539 | 0 | UINT64_C(258385232527510), // LMH |
1540 | 0 | UINT64_C(258385232527512), // LMY |
1541 | 0 | UINT64_C(3004235776), // LNDBR |
1542 | 0 | UINT64_C(3010527232), // LNDFR |
1543 | 0 | UINT64_C(3010527232), // LNDFR_32 |
1544 | 0 | UINT64_C(8448), // LNDR |
1545 | 0 | UINT64_C(3003187200), // LNEBR |
1546 | 0 | UINT64_C(12544), // LNER |
1547 | 0 | UINT64_C(3104899072), // LNGFR |
1548 | 0 | UINT64_C(3103850496), // LNGR |
1549 | 0 | UINT64_C(4352), // LNR |
1550 | 0 | UINT64_C(3007381504), // LNXBR |
1551 | 0 | UINT64_C(3009478656), // LNXR |
1552 | 0 | UINT64_C(258385232527602), // LOC |
1553 | 0 | UINT64_C(258385232527602), // LOCAsm |
1554 | 0 | UINT64_C(258419592265970), // LOCAsmE |
1555 | 0 | UINT64_C(258393822462194), // LOCAsmH |
1556 | 0 | UINT64_C(258428182200562), // LOCAsmHE |
1557 | 0 | UINT64_C(258402412396786), // LOCAsmL |
1558 | 0 | UINT64_C(258436772135154), // LOCAsmLE |
1559 | 0 | UINT64_C(258411002331378), // LOCAsmLH |
1560 | 0 | UINT64_C(258402412396786), // LOCAsmM |
1561 | 0 | UINT64_C(258415297298674), // LOCAsmNE |
1562 | 0 | UINT64_C(258441067102450), // LOCAsmNH |
1563 | 0 | UINT64_C(258406707364082), // LOCAsmNHE |
1564 | 0 | UINT64_C(258432477167858), // LOCAsmNL |
1565 | 0 | UINT64_C(258398117429490), // LOCAsmNLE |
1566 | 0 | UINT64_C(258423887233266), // LOCAsmNLH |
1567 | 0 | UINT64_C(258432477167858), // LOCAsmNM |
1568 | 0 | UINT64_C(258445362069746), // LOCAsmNO |
1569 | 0 | UINT64_C(258441067102450), // LOCAsmNP |
1570 | 0 | UINT64_C(258415297298674), // LOCAsmNZ |
1571 | 0 | UINT64_C(258389527494898), // LOCAsmO |
1572 | 0 | UINT64_C(258393822462194), // LOCAsmP |
1573 | 0 | UINT64_C(258419592265970), // LOCAsmZ |
1574 | 0 | UINT64_C(258385232527584), // LOCFH |
1575 | 0 | UINT64_C(258385232527584), // LOCFHAsm |
1576 | 0 | UINT64_C(258419592265952), // LOCFHAsmE |
1577 | 0 | UINT64_C(258393822462176), // LOCFHAsmH |
1578 | 0 | UINT64_C(258428182200544), // LOCFHAsmHE |
1579 | 0 | UINT64_C(258402412396768), // LOCFHAsmL |
1580 | 0 | UINT64_C(258436772135136), // LOCFHAsmLE |
1581 | 0 | UINT64_C(258411002331360), // LOCFHAsmLH |
1582 | 0 | UINT64_C(258402412396768), // LOCFHAsmM |
1583 | 0 | UINT64_C(258415297298656), // LOCFHAsmNE |
1584 | 0 | UINT64_C(258441067102432), // LOCFHAsmNH |
1585 | 0 | UINT64_C(258406707364064), // LOCFHAsmNHE |
1586 | 0 | UINT64_C(258432477167840), // LOCFHAsmNL |
1587 | 0 | UINT64_C(258398117429472), // LOCFHAsmNLE |
1588 | 0 | UINT64_C(258423887233248), // LOCFHAsmNLH |
1589 | 0 | UINT64_C(258432477167840), // LOCFHAsmNM |
1590 | 0 | UINT64_C(258445362069728), // LOCFHAsmNO |
1591 | 0 | UINT64_C(258441067102432), // LOCFHAsmNP |
1592 | 0 | UINT64_C(258415297298656), // LOCFHAsmNZ |
1593 | 0 | UINT64_C(258389527494880), // LOCFHAsmO |
1594 | 0 | UINT64_C(258393822462176), // LOCFHAsmP |
1595 | 0 | UINT64_C(258419592265952), // LOCFHAsmZ |
1596 | 0 | UINT64_C(3118465024), // LOCFHR |
1597 | 0 | UINT64_C(3118465024), // LOCFHRAsm |
1598 | 0 | UINT64_C(3118497792), // LOCFHRAsmE |
1599 | 0 | UINT64_C(3118473216), // LOCFHRAsmH |
1600 | 0 | UINT64_C(3118505984), // LOCFHRAsmHE |
1601 | 0 | UINT64_C(3118481408), // LOCFHRAsmL |
1602 | 0 | UINT64_C(3118514176), // LOCFHRAsmLE |
1603 | 0 | UINT64_C(3118489600), // LOCFHRAsmLH |
1604 | 0 | UINT64_C(3118481408), // LOCFHRAsmM |
1605 | 0 | UINT64_C(3118493696), // LOCFHRAsmNE |
1606 | 0 | UINT64_C(3118518272), // LOCFHRAsmNH |
1607 | 0 | UINT64_C(3118485504), // LOCFHRAsmNHE |
1608 | 0 | UINT64_C(3118510080), // LOCFHRAsmNL |
1609 | 0 | UINT64_C(3118477312), // LOCFHRAsmNLE |
1610 | 0 | UINT64_C(3118501888), // LOCFHRAsmNLH |
1611 | 0 | UINT64_C(3118510080), // LOCFHRAsmNM |
1612 | 0 | UINT64_C(3118522368), // LOCFHRAsmNO |
1613 | 0 | UINT64_C(3118518272), // LOCFHRAsmNP |
1614 | 0 | UINT64_C(3118493696), // LOCFHRAsmNZ |
1615 | 0 | UINT64_C(3118469120), // LOCFHRAsmO |
1616 | 0 | UINT64_C(3118473216), // LOCFHRAsmP |
1617 | 0 | UINT64_C(3118497792), // LOCFHRAsmZ |
1618 | 0 | UINT64_C(258385232527586), // LOCG |
1619 | 0 | UINT64_C(258385232527586), // LOCGAsm |
1620 | 0 | UINT64_C(258419592265954), // LOCGAsmE |
1621 | 0 | UINT64_C(258393822462178), // LOCGAsmH |
1622 | 0 | UINT64_C(258428182200546), // LOCGAsmHE |
1623 | 0 | UINT64_C(258402412396770), // LOCGAsmL |
1624 | 0 | UINT64_C(258436772135138), // LOCGAsmLE |
1625 | 0 | UINT64_C(258411002331362), // LOCGAsmLH |
1626 | 0 | UINT64_C(258402412396770), // LOCGAsmM |
1627 | 0 | UINT64_C(258415297298658), // LOCGAsmNE |
1628 | 0 | UINT64_C(258441067102434), // LOCGAsmNH |
1629 | 0 | UINT64_C(258406707364066), // LOCGAsmNHE |
1630 | 0 | UINT64_C(258432477167842), // LOCGAsmNL |
1631 | 0 | UINT64_C(258398117429474), // LOCGAsmNLE |
1632 | 0 | UINT64_C(258423887233250), // LOCGAsmNLH |
1633 | 0 | UINT64_C(258432477167842), // LOCGAsmNM |
1634 | 0 | UINT64_C(258445362069730), // LOCGAsmNO |
1635 | 0 | UINT64_C(258441067102434), // LOCGAsmNP |
1636 | 0 | UINT64_C(258415297298658), // LOCGAsmNZ |
1637 | 0 | UINT64_C(258389527494882), // LOCGAsmO |
1638 | 0 | UINT64_C(258393822462178), // LOCGAsmP |
1639 | 0 | UINT64_C(258419592265954), // LOCGAsmZ |
1640 | 0 | UINT64_C(259484744155206), // LOCGHI |
1641 | 0 | UINT64_C(259484744155206), // LOCGHIAsm |
1642 | 0 | UINT64_C(259519103893574), // LOCGHIAsmE |
1643 | 0 | UINT64_C(259493334089798), // LOCGHIAsmH |
1644 | 0 | UINT64_C(259527693828166), // LOCGHIAsmHE |
1645 | 0 | UINT64_C(259501924024390), // LOCGHIAsmL |
1646 | 0 | UINT64_C(259536283762758), // LOCGHIAsmLE |
1647 | 0 | UINT64_C(259510513958982), // LOCGHIAsmLH |
1648 | 0 | UINT64_C(259501924024390), // LOCGHIAsmM |
1649 | 0 | UINT64_C(259514808926278), // LOCGHIAsmNE |
1650 | 0 | UINT64_C(259540578730054), // LOCGHIAsmNH |
1651 | 0 | UINT64_C(259506218991686), // LOCGHIAsmNHE |
1652 | 0 | UINT64_C(259531988795462), // LOCGHIAsmNL |
1653 | 0 | UINT64_C(259497629057094), // LOCGHIAsmNLE |
1654 | 0 | UINT64_C(259523398860870), // LOCGHIAsmNLH |
1655 | 0 | UINT64_C(259531988795462), // LOCGHIAsmNM |
1656 | 0 | UINT64_C(259544873697350), // LOCGHIAsmNO |
1657 | 0 | UINT64_C(259540578730054), // LOCGHIAsmNP |
1658 | 0 | UINT64_C(259514808926278), // LOCGHIAsmNZ |
1659 | 0 | UINT64_C(259489039122502), // LOCGHIAsmO |
1660 | 0 | UINT64_C(259493334089798), // LOCGHIAsmP |
1661 | 0 | UINT64_C(259519103893574), // LOCGHIAsmZ |
1662 | 0 | UINT64_C(3118596096), // LOCGR |
1663 | 0 | UINT64_C(3118596096), // LOCGRAsm |
1664 | 0 | UINT64_C(3118628864), // LOCGRAsmE |
1665 | 0 | UINT64_C(3118604288), // LOCGRAsmH |
1666 | 0 | UINT64_C(3118637056), // LOCGRAsmHE |
1667 | 0 | UINT64_C(3118612480), // LOCGRAsmL |
1668 | 0 | UINT64_C(3118645248), // LOCGRAsmLE |
1669 | 0 | UINT64_C(3118620672), // LOCGRAsmLH |
1670 | 0 | UINT64_C(3118612480), // LOCGRAsmM |
1671 | 0 | UINT64_C(3118624768), // LOCGRAsmNE |
1672 | 0 | UINT64_C(3118649344), // LOCGRAsmNH |
1673 | 0 | UINT64_C(3118616576), // LOCGRAsmNHE |
1674 | 0 | UINT64_C(3118641152), // LOCGRAsmNL |
1675 | 0 | UINT64_C(3118608384), // LOCGRAsmNLE |
1676 | 0 | UINT64_C(3118632960), // LOCGRAsmNLH |
1677 | 0 | UINT64_C(3118641152), // LOCGRAsmNM |
1678 | 0 | UINT64_C(3118653440), // LOCGRAsmNO |
1679 | 0 | UINT64_C(3118649344), // LOCGRAsmNP |
1680 | 0 | UINT64_C(3118624768), // LOCGRAsmNZ |
1681 | 0 | UINT64_C(3118600192), // LOCGRAsmO |
1682 | 0 | UINT64_C(3118604288), // LOCGRAsmP |
1683 | 0 | UINT64_C(3118628864), // LOCGRAsmZ |
1684 | 0 | UINT64_C(259484744155214), // LOCHHI |
1685 | 0 | UINT64_C(259484744155214), // LOCHHIAsm |
1686 | 0 | UINT64_C(259519103893582), // LOCHHIAsmE |
1687 | 0 | UINT64_C(259493334089806), // LOCHHIAsmH |
1688 | 0 | UINT64_C(259527693828174), // LOCHHIAsmHE |
1689 | 0 | UINT64_C(259501924024398), // LOCHHIAsmL |
1690 | 0 | UINT64_C(259536283762766), // LOCHHIAsmLE |
1691 | 0 | UINT64_C(259510513958990), // LOCHHIAsmLH |
1692 | 0 | UINT64_C(259501924024398), // LOCHHIAsmM |
1693 | 0 | UINT64_C(259514808926286), // LOCHHIAsmNE |
1694 | 0 | UINT64_C(259540578730062), // LOCHHIAsmNH |
1695 | 0 | UINT64_C(259506218991694), // LOCHHIAsmNHE |
1696 | 0 | UINT64_C(259531988795470), // LOCHHIAsmNL |
1697 | 0 | UINT64_C(259497629057102), // LOCHHIAsmNLE |
1698 | 0 | UINT64_C(259523398860878), // LOCHHIAsmNLH |
1699 | 0 | UINT64_C(259531988795470), // LOCHHIAsmNM |
1700 | 0 | UINT64_C(259544873697358), // LOCHHIAsmNO |
1701 | 0 | UINT64_C(259540578730062), // LOCHHIAsmNP |
1702 | 0 | UINT64_C(259514808926286), // LOCHHIAsmNZ |
1703 | 0 | UINT64_C(259489039122510), // LOCHHIAsmO |
1704 | 0 | UINT64_C(259493334089806), // LOCHHIAsmP |
1705 | 0 | UINT64_C(259519103893582), // LOCHHIAsmZ |
1706 | 0 | UINT64_C(259484744155202), // LOCHI |
1707 | 0 | UINT64_C(259484744155202), // LOCHIAsm |
1708 | 0 | UINT64_C(259519103893570), // LOCHIAsmE |
1709 | 0 | UINT64_C(259493334089794), // LOCHIAsmH |
1710 | 0 | UINT64_C(259527693828162), // LOCHIAsmHE |
1711 | 0 | UINT64_C(259501924024386), // LOCHIAsmL |
1712 | 0 | UINT64_C(259536283762754), // LOCHIAsmLE |
1713 | 0 | UINT64_C(259510513958978), // LOCHIAsmLH |
1714 | 0 | UINT64_C(259501924024386), // LOCHIAsmM |
1715 | 0 | UINT64_C(259514808926274), // LOCHIAsmNE |
1716 | 0 | UINT64_C(259540578730050), // LOCHIAsmNH |
1717 | 0 | UINT64_C(259506218991682), // LOCHIAsmNHE |
1718 | 0 | UINT64_C(259531988795458), // LOCHIAsmNL |
1719 | 0 | UINT64_C(259497629057090), // LOCHIAsmNLE |
1720 | 0 | UINT64_C(259523398860866), // LOCHIAsmNLH |
1721 | 0 | UINT64_C(259531988795458), // LOCHIAsmNM |
1722 | 0 | UINT64_C(259544873697346), // LOCHIAsmNO |
1723 | 0 | UINT64_C(259540578730050), // LOCHIAsmNP |
1724 | 0 | UINT64_C(259514808926274), // LOCHIAsmNZ |
1725 | 0 | UINT64_C(259489039122498), // LOCHIAsmO |
1726 | 0 | UINT64_C(259493334089794), // LOCHIAsmP |
1727 | 0 | UINT64_C(259519103893570), // LOCHIAsmZ |
1728 | 0 | UINT64_C(3119644672), // LOCR |
1729 | 0 | UINT64_C(3119644672), // LOCRAsm |
1730 | 0 | UINT64_C(3119677440), // LOCRAsmE |
1731 | 0 | UINT64_C(3119652864), // LOCRAsmH |
1732 | 0 | UINT64_C(3119685632), // LOCRAsmHE |
1733 | 0 | UINT64_C(3119661056), // LOCRAsmL |
1734 | 0 | UINT64_C(3119693824), // LOCRAsmLE |
1735 | 0 | UINT64_C(3119669248), // LOCRAsmLH |
1736 | 0 | UINT64_C(3119661056), // LOCRAsmM |
1737 | 0 | UINT64_C(3119673344), // LOCRAsmNE |
1738 | 0 | UINT64_C(3119697920), // LOCRAsmNH |
1739 | 0 | UINT64_C(3119665152), // LOCRAsmNHE |
1740 | 0 | UINT64_C(3119689728), // LOCRAsmNL |
1741 | 0 | UINT64_C(3119656960), // LOCRAsmNLE |
1742 | 0 | UINT64_C(3119681536), // LOCRAsmNLH |
1743 | 0 | UINT64_C(3119689728), // LOCRAsmNM |
1744 | 0 | UINT64_C(3119702016), // LOCRAsmNO |
1745 | 0 | UINT64_C(3119697920), // LOCRAsmNP |
1746 | 0 | UINT64_C(3119673344), // LOCRAsmNZ |
1747 | 0 | UINT64_C(3119648768), // LOCRAsmO |
1748 | 0 | UINT64_C(3119652864), // LOCRAsmP |
1749 | 0 | UINT64_C(3119677440), // LOCRAsmZ |
1750 | 0 | UINT64_C(2995060736), // LPCTL |
1751 | 0 | UINT64_C(219919505424384), // LPD |
1752 | 0 | UINT64_C(3004170240), // LPDBR |
1753 | 0 | UINT64_C(3010461696), // LPDFR |
1754 | 0 | UINT64_C(3010461696), // LPDFR_32 |
1755 | 0 | UINT64_C(219923800391680), // LPDG |
1756 | 0 | UINT64_C(8192), // LPDR |
1757 | 0 | UINT64_C(3003121664), // LPEBR |
1758 | 0 | UINT64_C(12288), // LPER |
1759 | 0 | UINT64_C(3104833536), // LPGFR |
1760 | 0 | UINT64_C(3103784960), // LPGR |
1761 | 0 | UINT64_C(2994733056), // LPP |
1762 | 0 | UINT64_C(249589139505295), // LPQ |
1763 | 0 | UINT64_C(4096), // LPR |
1764 | 0 | UINT64_C(2181038080), // LPSW |
1765 | 0 | UINT64_C(2998009856), // LPSWE |
1766 | 0 | UINT64_C(258385232527473), // LPSWEY |
1767 | 0 | UINT64_C(3114926080), // LPTEA |
1768 | 0 | UINT64_C(3007315968), // LPXBR |
1769 | 0 | UINT64_C(3009413120), // LPXR |
1770 | 0 | UINT64_C(6144), // LR |
1771 | 0 | UINT64_C(2969567232), // LRA |
1772 | 0 | UINT64_C(249589139505155), // LRAG |
1773 | 0 | UINT64_C(249589139505171), // LRAY |
1774 | 0 | UINT64_C(9472), // LRDR |
1775 | 0 | UINT64_C(13568), // LRER |
1776 | 0 | UINT64_C(215560113618944), // LRL |
1777 | 0 | UINT64_C(249589139505182), // LRV |
1778 | 0 | UINT64_C(249589139505167), // LRVG |
1779 | 0 | UINT64_C(3104768000), // LRVGR |
1780 | 0 | UINT64_C(249589139505183), // LRVH |
1781 | 0 | UINT64_C(3105816576), // LRVR |
1782 | 0 | UINT64_C(2995191808), // LSCTL |
1783 | 0 | UINT64_C(249589139505170), // LT |
1784 | 0 | UINT64_C(3004301312), // LTDBR |
1785 | 0 | UINT64_C(8704), // LTDR |
1786 | 0 | UINT64_C(3017146368), // LTDTR |
1787 | 0 | UINT64_C(3003252736), // LTEBR |
1788 | 0 | UINT64_C(12800), // LTER |
1789 | 0 | UINT64_C(249589139505154), // LTG |
1790 | 0 | UINT64_C(249589139505202), // LTGF |
1791 | 0 | UINT64_C(3104964608), // LTGFR |
1792 | 0 | UINT64_C(3103916032), // LTGR |
1793 | 0 | UINT64_C(4608), // LTR |
1794 | 0 | UINT64_C(3007447040), // LTXBR |
1795 | 0 | UINT64_C(3009544192), // LTXR |
1796 | 0 | UINT64_C(3017670656), // LTXTR |
1797 | 0 | UINT64_C(2991259648), // LURA |
1798 | 0 | UINT64_C(3104112640), // LURAG |
1799 | 0 | UINT64_C(260584255782949), // LXD |
1800 | 0 | UINT64_C(260584255782917), // LXDB |
1801 | 0 | UINT64_C(3003449344), // LXDBR |
1802 | 0 | UINT64_C(3005546496), // LXDR |
1803 | 0 | UINT64_C(3017539584), // LXDTR |
1804 | 0 | UINT64_C(260584255782950), // LXE |
1805 | 0 | UINT64_C(260584255782918), // LXEB |
1806 | 0 | UINT64_C(3003514880), // LXEBR |
1807 | 0 | UINT64_C(3005612032), // LXER |
1808 | 0 | UINT64_C(3009740800), // LXR |
1809 | 0 | UINT64_C(249589139505240), // LY |
1810 | 0 | UINT64_C(3010789376), // LZDR |
1811 | 0 | UINT64_C(3010723840), // LZER |
1812 | 0 | UINT64_C(249589139505211), // LZRF |
1813 | 0 | UINT64_C(249589139505194), // LZRG |
1814 | 0 | UINT64_C(3010854912), // LZXR |
1815 | 0 | UINT64_C(1543503872), // M |
1816 | 0 | UINT64_C(260584255782974), // MAD |
1817 | 0 | UINT64_C(260584255782942), // MADB |
1818 | 0 | UINT64_C(3005087744), // MADBR |
1819 | 0 | UINT64_C(3007184896), // MADR |
1820 | 0 | UINT64_C(260584255782958), // MAE |
1821 | 0 | UINT64_C(260584255782926), // MAEB |
1822 | 0 | UINT64_C(3004039168), // MAEBR |
1823 | 0 | UINT64_C(3006136320), // MAER |
1824 | 0 | UINT64_C(260584255782970), // MAY |
1825 | 0 | UINT64_C(260584255782972), // MAYH |
1826 | 0 | UINT64_C(3007053824), // MAYHR |
1827 | 0 | UINT64_C(260584255782968), // MAYL |
1828 | 0 | UINT64_C(3006791680), // MAYLR |
1829 | 0 | UINT64_C(3006922752), // MAYR |
1830 | 0 | UINT64_C(2936012800), // MC |
1831 | 0 | UINT64_C(1811939328), // MD |
1832 | 0 | UINT64_C(260584255782940), // MDB |
1833 | 0 | UINT64_C(3004956672), // MDBR |
1834 | 0 | UINT64_C(2080374784), // MDE |
1835 | 0 | UINT64_C(260584255782924), // MDEB |
1836 | 0 | UINT64_C(3003908096), // MDEBR |
1837 | 0 | UINT64_C(15360), // MDER |
1838 | 0 | UINT64_C(11264), // MDR |
1839 | 0 | UINT64_C(3016753152), // MDTR |
1840 | 0 | UINT64_C(3016753152), // MDTRA |
1841 | 0 | UINT64_C(2080374784), // ME |
1842 | 0 | UINT64_C(260584255782967), // MEE |
1843 | 0 | UINT64_C(260584255782935), // MEEB |
1844 | 0 | UINT64_C(3004628992), // MEEBR |
1845 | 0 | UINT64_C(3006726144), // MEER |
1846 | 0 | UINT64_C(15360), // MER |
1847 | 0 | UINT64_C(249589139505244), // MFY |
1848 | 0 | UINT64_C(249589139505284), // MG |
1849 | 0 | UINT64_C(249589139505212), // MGH |
1850 | 0 | UINT64_C(2802647040), // MGHI |
1851 | 0 | UINT64_C(3119251456), // MGRK |
1852 | 0 | UINT64_C(1275068416), // MH |
1853 | 0 | UINT64_C(2802581504), // MHI |
1854 | 0 | UINT64_C(249589139505276), // MHY |
1855 | 0 | UINT64_C(249589139505302), // ML |
1856 | 0 | UINT64_C(249589139505286), // MLG |
1857 | 0 | UINT64_C(3112566784), // MLGR |
1858 | 0 | UINT64_C(3113615360), // MLR |
1859 | 0 | UINT64_C(277076930199552), // MP |
1860 | 0 | UINT64_C(7168), // MR |
1861 | 0 | UINT64_C(1895825408), // MS |
1862 | 0 | UINT64_C(249589139505235), // MSC |
1863 | 0 | UINT64_C(2989621248), // MSCH |
1864 | 0 | UINT64_C(260584255782975), // MSD |
1865 | 0 | UINT64_C(260584255782943), // MSDB |
1866 | 0 | UINT64_C(3005153280), // MSDBR |
1867 | 0 | UINT64_C(3007250432), // MSDR |
1868 | 0 | UINT64_C(260584255782959), // MSE |
1869 | 0 | UINT64_C(260584255782927), // MSEB |
1870 | 0 | UINT64_C(3004104704), // MSEBR |
1871 | 0 | UINT64_C(3006201856), // MSER |
1872 | 0 | UINT64_C(213309550755840), // MSFI |
1873 | 0 | UINT64_C(249589139505164), // MSG |
1874 | 0 | UINT64_C(249589139505283), // MSGC |
1875 | 0 | UINT64_C(249589139505180), // MSGF |
1876 | 0 | UINT64_C(213305255788544), // MSGFI |
1877 | 0 | UINT64_C(3105619968), // MSGFR |
1878 | 0 | UINT64_C(3104571392), // MSGR |
1879 | 0 | UINT64_C(3119316992), // MSGRKC |
1880 | 0 | UINT64_C(2991718400), // MSR |
1881 | 0 | UINT64_C(3120365568), // MSRKC |
1882 | 0 | UINT64_C(2990997504), // MSTA |
1883 | 0 | UINT64_C(249589139505233), // MSY |
1884 | 0 | UINT64_C(230897441832960), // MVC |
1885 | 0 | UINT64_C(251852587270144), // MVCDK |
1886 | 0 | UINT64_C(255086697644032), // MVCIN |
1887 | 0 | UINT64_C(238594023227392), // MVCK |
1888 | 0 | UINT64_C(3584), // MVCL |
1889 | 0 | UINT64_C(2818572288), // MVCLE |
1890 | 0 | UINT64_C(258385232527502), // MVCLU |
1891 | 0 | UINT64_C(219902325555200), // MVCOS |
1892 | 0 | UINT64_C(239693534855168), // MVCP |
1893 | 0 | UINT64_C(251831112433664), // MVCRL |
1894 | 0 | UINT64_C(240793046482944), // MVCS |
1895 | 0 | UINT64_C(251848292302848), // MVCSK |
1896 | 0 | UINT64_C(252097400406016), // MVGHI |
1897 | 0 | UINT64_C(252080220536832), // MVHHI |
1898 | 0 | UINT64_C(252114580275200), // MVHI |
1899 | 0 | UINT64_C(2449473536), // MVI |
1900 | 0 | UINT64_C(258385232527442), // MVIY |
1901 | 0 | UINT64_C(229797930205184), // MVN |
1902 | 0 | UINT64_C(264982302294016), // MVO |
1903 | 0 | UINT64_C(2991849472), // MVPG |
1904 | 0 | UINT64_C(2991915008), // MVST |
1905 | 0 | UINT64_C(231996953460736), // MVZ |
1906 | 0 | UINT64_C(3008102400), // MXBR |
1907 | 0 | UINT64_C(1728053248), // MXD |
1908 | 0 | UINT64_C(260584255782919), // MXDB |
1909 | 0 | UINT64_C(3003580416), // MXDBR |
1910 | 0 | UINT64_C(9984), // MXDR |
1911 | 0 | UINT64_C(9728), // MXR |
1912 | 0 | UINT64_C(3017277440), // MXTR |
1913 | 0 | UINT64_C(3017277440), // MXTRA |
1914 | 0 | UINT64_C(260584255782971), // MY |
1915 | 0 | UINT64_C(260584255782973), // MYH |
1916 | 0 | UINT64_C(3007119360), // MYHR |
1917 | 0 | UINT64_C(260584255782969), // MYL |
1918 | 0 | UINT64_C(3006857216), // MYLR |
1919 | 0 | UINT64_C(3006988288), // MYR |
1920 | 0 | UINT64_C(1409286144), // N |
1921 | 0 | UINT64_C(233096465088512), // NC |
1922 | 0 | UINT64_C(3118792704), // NCGRK |
1923 | 0 | UINT64_C(3119841280), // NCRK |
1924 | 0 | UINT64_C(249589139505280), // NG |
1925 | 0 | UINT64_C(3112173568), // NGR |
1926 | 0 | UINT64_C(3118727168), // NGRK |
1927 | 0 | UINT64_C(2483027968), // NI |
1928 | 0 | UINT64_C(3002728448), // NIAI |
1929 | 0 | UINT64_C(211149182205952), // NIHF |
1930 | 0 | UINT64_C(2768502784), // NIHH |
1931 | 0 | UINT64_C(2768568320), // NIHL |
1932 | 0 | UINT64_C(211153477173248), // NILF |
1933 | 0 | UINT64_C(2768633856), // NILH |
1934 | 0 | UINT64_C(2768699392), // NILL |
1935 | 0 | UINT64_C(258385232527444), // NIY |
1936 | 0 | UINT64_C(3110338560), // NNGRK |
1937 | 0 | UINT64_C(3107651584), // NNPA |
1938 | 0 | UINT64_C(3111387136), // NNRK |
1939 | 0 | UINT64_C(3110469632), // NOGRK |
1940 | 0 | UINT64_C(1191182336), // NOP_bare |
1941 | 0 | UINT64_C(3111518208), // NORK |
1942 | 0 | UINT64_C(5120), // NR |
1943 | 0 | UINT64_C(3119775744), // NRK |
1944 | 0 | UINT64_C(249589139505189), // NTSTG |
1945 | 0 | UINT64_C(3110535168), // NXGRK |
1946 | 0 | UINT64_C(3111583744), // NXRK |
1947 | 0 | UINT64_C(249589139505236), // NY |
1948 | 0 | UINT64_C(1442840576), // O |
1949 | 0 | UINT64_C(235295488344064), // OC |
1950 | 0 | UINT64_C(3110404096), // OCGRK |
1951 | 0 | UINT64_C(3111452672), // OCRK |
1952 | 0 | UINT64_C(249589139505281), // OG |
1953 | 0 | UINT64_C(3112239104), // OGR |
1954 | 0 | UINT64_C(3118858240), // OGRK |
1955 | 0 | UINT64_C(2516582400), // OI |
1956 | 0 | UINT64_C(211157772140544), // OIHF |
1957 | 0 | UINT64_C(2768764928), // OIHH |
1958 | 0 | UINT64_C(2768830464), // OIHL |
1959 | 0 | UINT64_C(211162067107840), // OILF |
1960 | 0 | UINT64_C(2768896000), // OILH |
1961 | 0 | UINT64_C(2768961536), // OILL |
1962 | 0 | UINT64_C(258385232527446), // OIY |
1963 | 0 | UINT64_C(5632), // OR |
1964 | 0 | UINT64_C(3119906816), // ORK |
1965 | 0 | UINT64_C(249589139505238), // OY |
1966 | 0 | UINT64_C(266081813921792), // PACK |
1967 | 0 | UINT64_C(2991063040), // PALB |
1968 | 0 | UINT64_C(2987917312), // PC |
1969 | 0 | UINT64_C(3106668544), // PCC |
1970 | 0 | UINT64_C(3106406400), // PCKMO |
1971 | 0 | UINT64_C(249589139505206), // PFD |
1972 | 0 | UINT64_C(217711892234240), // PFDRL |
1973 | 0 | UINT64_C(3115253760), // PFMF |
1974 | 0 | UINT64_C(266), // PFPO |
1975 | 0 | UINT64_C(2989359104), // PGIN |
1976 | 0 | UINT64_C(2989424640), // PGOUT |
1977 | 0 | UINT64_C(256186209271808), // PKA |
1978 | 0 | UINT64_C(247390116249600), // PKU |
1979 | 0 | UINT64_C(261683767410688), // PLO |
1980 | 0 | UINT64_C(3118530560), // POPCNT |
1981 | 0 | UINT64_C(3118530560), // POPCNTOpt |
1982 | 0 | UINT64_C(3001548800), // PPA |
1983 | 0 | UINT64_C(3107717120), // PPNO |
1984 | 0 | UINT64_C(257), // PR |
1985 | 0 | UINT64_C(3107717120), // PRNO |
1986 | 0 | UINT64_C(2988965888), // PT |
1987 | 0 | UINT64_C(3114401792), // PTF |
1988 | 0 | UINT64_C(260), // PTFF |
1989 | 0 | UINT64_C(3114139648), // PTI |
1990 | 0 | UINT64_C(2987196416), // PTLB |
1991 | 0 | UINT64_C(3019177984), // QADTR |
1992 | 0 | UINT64_C(3019702272), // QAXTR |
1993 | 0 | UINT64_C(2995650560), // QCTRI |
1994 | 0 | UINT64_C(2995716096), // QPACI |
1995 | 0 | UINT64_C(2995126272), // QSI |
1996 | 0 | UINT64_C(2990211072), // RCHP |
1997 | 0 | UINT64_C(3112894464), // RDP |
1998 | 0 | UINT64_C(3112894464), // RDPOpt |
1999 | 0 | UINT64_C(259484744155221), // RISBG |
2000 | 0 | UINT64_C(259484744155221), // RISBG32 |
2001 | 0 | UINT64_C(259484744155225), // RISBGN |
2002 | 0 | UINT64_C(259484744155229), // RISBHG |
2003 | 0 | UINT64_C(259484744155217), // RISBLG |
2004 | 0 | UINT64_C(258385232527389), // RLL |
2005 | 0 | UINT64_C(258385232527388), // RLLG |
2006 | 0 | UINT64_C(259484744155220), // RNSBG |
2007 | 0 | UINT64_C(259484744155222), // ROSBG |
2008 | 0 | UINT64_C(2994143232), // RP |
2009 | 0 | UINT64_C(2989096960), // RRBE |
2010 | 0 | UINT64_C(3115188224), // RRBM |
2011 | 0 | UINT64_C(3019309056), // RRDTR |
2012 | 0 | UINT64_C(3019833344), // RRXTR |
2013 | 0 | UINT64_C(2990014464), // RSCH |
2014 | 0 | UINT64_C(259484744155223), // RXSBG |
2015 | 0 | UINT64_C(1526726656), // S |
2016 | 0 | UINT64_C(2987982848), // SAC |
2017 | 0 | UINT64_C(2994274304), // SACF |
2018 | 0 | UINT64_C(2989948928), // SAL |
2019 | 0 | UINT64_C(268), // SAM24 |
2020 | 0 | UINT64_C(269), // SAM31 |
2021 | 0 | UINT64_C(270), // SAM64 |
2022 | 0 | UINT64_C(2991456256), // SAR |
2023 | 0 | UINT64_C(3001024512), // SCCTR |
2024 | 0 | UINT64_C(2990276608), // SCHM |
2025 | 0 | UINT64_C(2986606592), // SCK |
2026 | 0 | UINT64_C(2986737664), // SCKC |
2027 | 0 | UINT64_C(263), // SCKPF |
2028 | 0 | UINT64_C(1795162112), // SD |
2029 | 0 | UINT64_C(260584255782939), // SDB |
2030 | 0 | UINT64_C(3004891136), // SDBR |
2031 | 0 | UINT64_C(11008), // SDR |
2032 | 0 | UINT64_C(3016949760), // SDTR |
2033 | 0 | UINT64_C(3016949760), // SDTRA |
2034 | 0 | UINT64_C(2063597568), // SE |
2035 | 0 | UINT64_C(260584255782923), // SEB |
2036 | 0 | UINT64_C(3003842560), // SEBR |
2037 | 0 | UINT64_C(3116367872), // SELFHR |
2038 | 0 | UINT64_C(3116367872), // SELFHRAsm |
2039 | 0 | UINT64_C(3116369920), // SELFHRAsmE |
2040 | 0 | UINT64_C(3116368384), // SELFHRAsmH |
2041 | 0 | UINT64_C(3116370432), // SELFHRAsmHE |
2042 | 0 | UINT64_C(3116368896), // SELFHRAsmL |
2043 | 0 | UINT64_C(3116370944), // SELFHRAsmLE |
2044 | 0 | UINT64_C(3116369408), // SELFHRAsmLH |
2045 | 0 | UINT64_C(3116368896), // SELFHRAsmM |
2046 | 0 | UINT64_C(3116369664), // SELFHRAsmNE |
2047 | 0 | UINT64_C(3116371200), // SELFHRAsmNH |
2048 | 0 | UINT64_C(3116369152), // SELFHRAsmNHE |
2049 | 0 | UINT64_C(3116370688), // SELFHRAsmNL |
2050 | 0 | UINT64_C(3116368640), // SELFHRAsmNLE |
2051 | 0 | UINT64_C(3116370176), // SELFHRAsmNLH |
2052 | 0 | UINT64_C(3116370688), // SELFHRAsmNM |
2053 | 0 | UINT64_C(3116371456), // SELFHRAsmNO |
2054 | 0 | UINT64_C(3116371200), // SELFHRAsmNP |
2055 | 0 | UINT64_C(3116369664), // SELFHRAsmNZ |
2056 | 0 | UINT64_C(3116368128), // SELFHRAsmO |
2057 | 0 | UINT64_C(3116368384), // SELFHRAsmP |
2058 | 0 | UINT64_C(3116369920), // SELFHRAsmZ |
2059 | 0 | UINT64_C(3118661632), // SELGR |
2060 | 0 | UINT64_C(3118661632), // SELGRAsm |
2061 | 0 | UINT64_C(3118663680), // SELGRAsmE |
2062 | 0 | UINT64_C(3118662144), // SELGRAsmH |
2063 | 0 | UINT64_C(3118664192), // SELGRAsmHE |
2064 | 0 | UINT64_C(3118662656), // SELGRAsmL |
2065 | 0 | UINT64_C(3118664704), // SELGRAsmLE |
2066 | 0 | UINT64_C(3118663168), // SELGRAsmLH |
2067 | 0 | UINT64_C(3118662656), // SELGRAsmM |
2068 | 0 | UINT64_C(3118663424), // SELGRAsmNE |
2069 | 0 | UINT64_C(3118664960), // SELGRAsmNH |
2070 | 0 | UINT64_C(3118662912), // SELGRAsmNHE |
2071 | 0 | UINT64_C(3118664448), // SELGRAsmNL |
2072 | 0 | UINT64_C(3118662400), // SELGRAsmNLE |
2073 | 0 | UINT64_C(3118663936), // SELGRAsmNLH |
2074 | 0 | UINT64_C(3118664448), // SELGRAsmNM |
2075 | 0 | UINT64_C(3118665216), // SELGRAsmNO |
2076 | 0 | UINT64_C(3118664960), // SELGRAsmNP |
2077 | 0 | UINT64_C(3118663424), // SELGRAsmNZ |
2078 | 0 | UINT64_C(3118661888), // SELGRAsmO |
2079 | 0 | UINT64_C(3118662144), // SELGRAsmP |
2080 | 0 | UINT64_C(3118663680), // SELGRAsmZ |
2081 | 0 | UINT64_C(3119513600), // SELR |
2082 | 0 | UINT64_C(3119513600), // SELRAsm |
2083 | 0 | UINT64_C(3119515648), // SELRAsmE |
2084 | 0 | UINT64_C(3119514112), // SELRAsmH |
2085 | 0 | UINT64_C(3119516160), // SELRAsmHE |
2086 | 0 | UINT64_C(3119514624), // SELRAsmL |
2087 | 0 | UINT64_C(3119516672), // SELRAsmLE |
2088 | 0 | UINT64_C(3119515136), // SELRAsmLH |
2089 | 0 | UINT64_C(3119514624), // SELRAsmM |
2090 | 0 | UINT64_C(3119515392), // SELRAsmNE |
2091 | 0 | UINT64_C(3119516928), // SELRAsmNH |
2092 | 0 | UINT64_C(3119514880), // SELRAsmNHE |
2093 | 0 | UINT64_C(3119516416), // SELRAsmNL |
2094 | 0 | UINT64_C(3119514368), // SELRAsmNLE |
2095 | 0 | UINT64_C(3119515904), // SELRAsmNLH |
2096 | 0 | UINT64_C(3119516416), // SELRAsmNM |
2097 | 0 | UINT64_C(3119517184), // SELRAsmNO |
2098 | 0 | UINT64_C(3119516928), // SELRAsmNP |
2099 | 0 | UINT64_C(3119515392), // SELRAsmNZ |
2100 | 0 | UINT64_C(3119513856), // SELRAsmO |
2101 | 0 | UINT64_C(3119514112), // SELRAsmP |
2102 | 0 | UINT64_C(3119515648), // SELRAsmZ |
2103 | 0 | UINT64_C(15104), // SER |
2104 | 0 | UINT64_C(3011837952), // SFASR |
2105 | 0 | UINT64_C(3011772416), // SFPC |
2106 | 0 | UINT64_C(249589139505161), // SG |
2107 | 0 | UINT64_C(249589139505177), // SGF |
2108 | 0 | UINT64_C(3105423360), // SGFR |
2109 | 0 | UINT64_C(249589139505209), // SGH |
2110 | 0 | UINT64_C(3104374784), // SGR |
2111 | 0 | UINT64_C(3119054848), // SGRK |
2112 | 0 | UINT64_C(1258291200), // SH |
2113 | 0 | UINT64_C(3116957696), // SHHHR |
2114 | 0 | UINT64_C(3118006272), // SHHLR |
2115 | 0 | UINT64_C(249589139505275), // SHY |
2116 | 0 | UINT64_C(2987655168), // SIE |
2117 | 0 | UINT64_C(2993946624), // SIGA |
2118 | 0 | UINT64_C(2919235584), // SIGP |
2119 | 0 | UINT64_C(1593835520), // SL |
2120 | 0 | UINT64_C(2332033024), // SLA |
2121 | 0 | UINT64_C(258385232527371), // SLAG |
2122 | 0 | UINT64_C(258385232527581), // SLAK |
2123 | 0 | UINT64_C(249589139505305), // SLB |
2124 | 0 | UINT64_C(249589139505289), // SLBG |
2125 | 0 | UINT64_C(3112763392), // SLBGR |
2126 | 0 | UINT64_C(3113811968), // SLBR |
2127 | 0 | UINT64_C(2399141888), // SLDA |
2128 | 0 | UINT64_C(2365587456), // SLDL |
2129 | 0 | UINT64_C(260584255782976), // SLDT |
2130 | 0 | UINT64_C(213326730625024), // SLFI |
2131 | 0 | UINT64_C(249589139505163), // SLG |
2132 | 0 | UINT64_C(249589139505179), // SLGF |
2133 | 0 | UINT64_C(213322435657728), // SLGFI |
2134 | 0 | UINT64_C(3105554432), // SLGFR |
2135 | 0 | UINT64_C(3104505856), // SLGR |
2136 | 0 | UINT64_C(3119185920), // SLGRK |
2137 | 0 | UINT64_C(3117088768), // SLHHHR |
2138 | 0 | UINT64_C(3118137344), // SLHHLR |
2139 | 0 | UINT64_C(2298478592), // SLL |
2140 | 0 | UINT64_C(258385232527373), // SLLG |
2141 | 0 | UINT64_C(258385232527583), // SLLK |
2142 | 0 | UINT64_C(7936), // SLR |
2143 | 0 | UINT64_C(3120234496), // SLRK |
2144 | 0 | UINT64_C(260584255782984), // SLXT |
2145 | 0 | UINT64_C(249589139505247), // SLY |
2146 | 0 | UINT64_C(3107454976), // SORTL |
2147 | 0 | UINT64_C(275977418571776), // SP |
2148 | 0 | UINT64_C(3001090048), // SPCTR |
2149 | 0 | UINT64_C(2986999808), // SPKA |
2150 | 0 | UINT64_C(1024), // SPM |
2151 | 0 | UINT64_C(2986868736), // SPT |
2152 | 0 | UINT64_C(2987393024), // SPX |
2153 | 0 | UINT64_C(260584255782965), // SQD |
2154 | 0 | UINT64_C(260584255782933), // SQDB |
2155 | 0 | UINT64_C(3004497920), // SQDBR |
2156 | 0 | UINT64_C(2990800896), // SQDR |
2157 | 0 | UINT64_C(260584255782964), // SQE |
2158 | 0 | UINT64_C(260584255782932), // SQEB |
2159 | 0 | UINT64_C(3004432384), // SQEBR |
2160 | 0 | UINT64_C(2990866432), // SQER |
2161 | 0 | UINT64_C(3004563456), // SQXBR |
2162 | 0 | UINT64_C(3006660608), // SQXR |
2163 | 0 | UINT64_C(6912), // SR |
2164 | 0 | UINT64_C(2315255808), // SRA |
2165 | 0 | UINT64_C(258385232527370), // SRAG |
2166 | 0 | UINT64_C(258385232527580), // SRAK |
2167 | 0 | UINT64_C(2382364672), // SRDA |
2168 | 0 | UINT64_C(2348810240), // SRDL |
2169 | 0 | UINT64_C(260584255782977), // SRDT |
2170 | 0 | UINT64_C(3120103424), // SRK |
2171 | 0 | UINT64_C(2281701376), // SRL |
2172 | 0 | UINT64_C(258385232527372), // SRLG |
2173 | 0 | UINT64_C(258385232527582), // SRLK |
2174 | 0 | UINT64_C(2996371456), // SRNM |
2175 | 0 | UINT64_C(2998403072), // SRNMB |
2176 | 0 | UINT64_C(2998468608), // SRNMT |
2177 | 0 | UINT64_C(263882790666240), // SRP |
2178 | 0 | UINT64_C(2992504832), // SRST |
2179 | 0 | UINT64_C(3116236800), // SRSTU |
2180 | 0 | UINT64_C(260584255782985), // SRXT |
2181 | 0 | UINT64_C(3114205184), // SSAIR |
2182 | 0 | UINT64_C(2988769280), // SSAR |
2183 | 0 | UINT64_C(2989686784), // SSCH |
2184 | 0 | UINT64_C(2989162496), // SSKE |
2185 | 0 | UINT64_C(2989162496), // SSKEOpt |
2186 | 0 | UINT64_C(2147483648), // SSM |
2187 | 0 | UINT64_C(1342177280), // ST |
2188 | 0 | UINT64_C(2600468480), // STAM |
2189 | 0 | UINT64_C(258385232527515), // STAMY |
2190 | 0 | UINT64_C(2987524096), // STAP |
2191 | 0 | UINT64_C(2986409984), // STBEAR |
2192 | 0 | UINT64_C(1107296256), // STC |
2193 | 0 | UINT64_C(249589139505347), // STCH |
2194 | 0 | UINT64_C(2986672128), // STCK |
2195 | 0 | UINT64_C(2986803200), // STCKC |
2196 | 0 | UINT64_C(2994208768), // STCKE |
2197 | 0 | UINT64_C(2994470912), // STCKF |
2198 | 0 | UINT64_C(3187671040), // STCM |
2199 | 0 | UINT64_C(258385232527404), // STCMH |
2200 | 0 | UINT64_C(258385232527405), // STCMY |
2201 | 0 | UINT64_C(2990145536), // STCPS |
2202 | 0 | UINT64_C(2990080000), // STCRW |
2203 | 0 | UINT64_C(258385232527397), // STCTG |
2204 | 0 | UINT64_C(3053453312), // STCTL |
2205 | 0 | UINT64_C(249589139505266), // STCY |
2206 | 0 | UINT64_C(1610612736), // STD |
2207 | 0 | UINT64_C(260584255783015), // STDY |
2208 | 0 | UINT64_C(1879048192), // STE |
2209 | 0 | UINT64_C(260584255783014), // STEY |
2210 | 0 | UINT64_C(249589139505355), // STFH |
2211 | 0 | UINT64_C(2997944320), // STFL |
2212 | 0 | UINT64_C(2997878784), // STFLE |
2213 | 0 | UINT64_C(2996568064), // STFPC |
2214 | 0 | UINT64_C(249589139505188), // STG |
2215 | 0 | UINT64_C(215551523684352), // STGRL |
2216 | 0 | UINT64_C(249589139505225), // STGSC |
2217 | 0 | UINT64_C(1073741824), // STH |
2218 | 0 | UINT64_C(249589139505351), // STHH |
2219 | 0 | UINT64_C(215534343815168), // STHRL |
2220 | 0 | UINT64_C(249589139505264), // STHY |
2221 | 0 | UINT64_C(2986475520), // STIDP |
2222 | 0 | UINT64_C(2415919104), // STM |
2223 | 0 | UINT64_C(258385232527396), // STMG |
2224 | 0 | UINT64_C(258385232527398), // STMH |
2225 | 0 | UINT64_C(258385232527504), // STMY |
2226 | 0 | UINT64_C(2885681152), // STNSM |
2227 | 0 | UINT64_C(258385232527603), // STOC |
2228 | 0 | UINT64_C(258385232527603), // STOCAsm |
2229 | 0 | UINT64_C(258419592265971), // STOCAsmE |
2230 | 0 | UINT64_C(258393822462195), // STOCAsmH |
2231 | 0 | UINT64_C(258428182200563), // STOCAsmHE |
2232 | 0 | UINT64_C(258402412396787), // STOCAsmL |
2233 | 0 | UINT64_C(258436772135155), // STOCAsmLE |
2234 | 0 | UINT64_C(258411002331379), // STOCAsmLH |
2235 | 0 | UINT64_C(258402412396787), // STOCAsmM |
2236 | 0 | UINT64_C(258415297298675), // STOCAsmNE |
2237 | 0 | UINT64_C(258441067102451), // STOCAsmNH |
2238 | 0 | UINT64_C(258406707364083), // STOCAsmNHE |
2239 | 0 | UINT64_C(258432477167859), // STOCAsmNL |
2240 | 0 | UINT64_C(258398117429491), // STOCAsmNLE |
2241 | 0 | UINT64_C(258423887233267), // STOCAsmNLH |
2242 | 0 | UINT64_C(258432477167859), // STOCAsmNM |
2243 | 0 | UINT64_C(258445362069747), // STOCAsmNO |
2244 | 0 | UINT64_C(258441067102451), // STOCAsmNP |
2245 | 0 | UINT64_C(258415297298675), // STOCAsmNZ |
2246 | 0 | UINT64_C(258389527494899), // STOCAsmO |
2247 | 0 | UINT64_C(258393822462195), // STOCAsmP |
2248 | 0 | UINT64_C(258419592265971), // STOCAsmZ |
2249 | 0 | UINT64_C(258385232527585), // STOCFH |
2250 | 0 | UINT64_C(258385232527585), // STOCFHAsm |
2251 | 0 | UINT64_C(258419592265953), // STOCFHAsmE |
2252 | 0 | UINT64_C(258393822462177), // STOCFHAsmH |
2253 | 0 | UINT64_C(258428182200545), // STOCFHAsmHE |
2254 | 0 | UINT64_C(258402412396769), // STOCFHAsmL |
2255 | 0 | UINT64_C(258436772135137), // STOCFHAsmLE |
2256 | 0 | UINT64_C(258411002331361), // STOCFHAsmLH |
2257 | 0 | UINT64_C(258402412396769), // STOCFHAsmM |
2258 | 0 | UINT64_C(258415297298657), // STOCFHAsmNE |
2259 | 0 | UINT64_C(258441067102433), // STOCFHAsmNH |
2260 | 0 | UINT64_C(258406707364065), // STOCFHAsmNHE |
2261 | 0 | UINT64_C(258432477167841), // STOCFHAsmNL |
2262 | 0 | UINT64_C(258398117429473), // STOCFHAsmNLE |
2263 | 0 | UINT64_C(258423887233249), // STOCFHAsmNLH |
2264 | 0 | UINT64_C(258432477167841), // STOCFHAsmNM |
2265 | 0 | UINT64_C(258445362069729), // STOCFHAsmNO |
2266 | 0 | UINT64_C(258441067102433), // STOCFHAsmNP |
2267 | 0 | UINT64_C(258415297298657), // STOCFHAsmNZ |
2268 | 0 | UINT64_C(258389527494881), // STOCFHAsmO |
2269 | 0 | UINT64_C(258393822462177), // STOCFHAsmP |
2270 | 0 | UINT64_C(258419592265953), // STOCFHAsmZ |
2271 | 0 | UINT64_C(258385232527587), // STOCG |
2272 | 0 | UINT64_C(258385232527587), // STOCGAsm |
2273 | 0 | UINT64_C(258419592265955), // STOCGAsmE |
2274 | 0 | UINT64_C(258393822462179), // STOCGAsmH |
2275 | 0 | UINT64_C(258428182200547), // STOCGAsmHE |
2276 | 0 | UINT64_C(258402412396771), // STOCGAsmL |
2277 | 0 | UINT64_C(258436772135139), // STOCGAsmLE |
2278 | 0 | UINT64_C(258411002331363), // STOCGAsmLH |
2279 | 0 | UINT64_C(258402412396771), // STOCGAsmM |
2280 | 0 | UINT64_C(258415297298659), // STOCGAsmNE |
2281 | 0 | UINT64_C(258441067102435), // STOCGAsmNH |
2282 | 0 | UINT64_C(258406707364067), // STOCGAsmNHE |
2283 | 0 | UINT64_C(258432477167843), // STOCGAsmNL |
2284 | 0 | UINT64_C(258398117429475), // STOCGAsmNLE |
2285 | 0 | UINT64_C(258423887233251), // STOCGAsmNLH |
2286 | 0 | UINT64_C(258432477167843), // STOCGAsmNM |
2287 | 0 | UINT64_C(258445362069731), // STOCGAsmNO |
2288 | 0 | UINT64_C(258441067102435), // STOCGAsmNP |
2289 | 0 | UINT64_C(258415297298659), // STOCGAsmNZ |
2290 | 0 | UINT64_C(258389527494883), // STOCGAsmO |
2291 | 0 | UINT64_C(258393822462179), // STOCGAsmP |
2292 | 0 | UINT64_C(258419592265955), // STOCGAsmZ |
2293 | 0 | UINT64_C(2902458368), // STOSM |
2294 | 0 | UINT64_C(249589139505294), // STPQ |
2295 | 0 | UINT64_C(2986934272), // STPT |
2296 | 0 | UINT64_C(2987458560), // STPX |
2297 | 0 | UINT64_C(251796752695296), // STRAG |
2298 | 0 | UINT64_C(215568703553536), // STRL |
2299 | 0 | UINT64_C(249589139505214), // STRV |
2300 | 0 | UINT64_C(249589139505199), // STRVG |
2301 | 0 | UINT64_C(249589139505215), // STRVH |
2302 | 0 | UINT64_C(2989752320), // STSCH |
2303 | 0 | UINT64_C(2994536448), // STSI |
2304 | 0 | UINT64_C(2990931968), // STURA |
2305 | 0 | UINT64_C(3106209792), // STURG |
2306 | 0 | UINT64_C(249589139505232), // STY |
2307 | 0 | UINT64_C(2130706432), // SU |
2308 | 0 | UINT64_C(16128), // SUR |
2309 | 0 | UINT64_C(2560), // SVC |
2310 | 0 | UINT64_C(1862270976), // SW |
2311 | 0 | UINT64_C(12032), // SWR |
2312 | 0 | UINT64_C(3008036864), // SXBR |
2313 | 0 | UINT64_C(14080), // SXR |
2314 | 0 | UINT64_C(3017474048), // SXTR |
2315 | 0 | UINT64_C(3017474048), // SXTRA |
2316 | 0 | UINT64_C(249589139505243), // SY |
2317 | 0 | UINT64_C(3002859520), // TABORT |
2318 | 0 | UINT64_C(267), // TAM |
2319 | 0 | UINT64_C(2991325184), // TAR |
2320 | 0 | UINT64_C(2989228032), // TB |
2321 | 0 | UINT64_C(3008430080), // TBDR |
2322 | 0 | UINT64_C(3008364544), // TBEDR |
2323 | 0 | UINT64_C(252200479621120), // TBEGIN |
2324 | 0 | UINT64_C(252204774588416), // TBEGINC |
2325 | 0 | UINT64_C(260584255782929), // TCDB |
2326 | 0 | UINT64_C(260584255782928), // TCEB |
2327 | 0 | UINT64_C(260584255782930), // TCXB |
2328 | 0 | UINT64_C(260584255782996), // TDCDT |
2329 | 0 | UINT64_C(260584255782992), // TDCET |
2330 | 0 | UINT64_C(260584255783000), // TDCXT |
2331 | 0 | UINT64_C(260584255782997), // TDGDT |
2332 | 0 | UINT64_C(260584255782993), // TDGET |
2333 | 0 | UINT64_C(260584255783001), // TDGXT |
2334 | 0 | UINT64_C(3002597376), // TEND |
2335 | 0 | UINT64_C(3008888832), // THDER |
2336 | 0 | UINT64_C(3008954368), // THDR |
2337 | 0 | UINT64_C(2432696320), // TM |
2338 | 0 | UINT64_C(2801926144), // TMHH |
2339 | 0 | UINT64_C(2801991680), // TMHL |
2340 | 0 | UINT64_C(2801795072), // TMLH |
2341 | 0 | UINT64_C(2801860608), // TMLL |
2342 | 0 | UINT64_C(258385232527441), // TMY |
2343 | 0 | UINT64_C(258385232527552), // TP |
2344 | 0 | UINT64_C(2989883392), // TPI |
2345 | 0 | UINT64_C(251792457728000), // TPROT |
2346 | 0 | UINT64_C(241892558110720), // TR |
2347 | 0 | UINT64_C(2566914048), // TRACE |
2348 | 0 | UINT64_C(258385232527375), // TRACG |
2349 | 0 | UINT64_C(511), // TRAP2 |
2350 | 0 | UINT64_C(3003056128), // TRAP4 |
2351 | 0 | UINT64_C(2997157888), // TRE |
2352 | 0 | UINT64_C(3113418752), // TROO |
2353 | 0 | UINT64_C(3113418752), // TROOOpt |
2354 | 0 | UINT64_C(3113353216), // TROT |
2355 | 0 | UINT64_C(3113353216), // TROTOpt |
2356 | 0 | UINT64_C(242992069738496), // TRT |
2357 | 0 | UINT64_C(3116302336), // TRTE |
2358 | 0 | UINT64_C(3116302336), // TRTEOpt |
2359 | 0 | UINT64_C(3113287680), // TRTO |
2360 | 0 | UINT64_C(3113287680), // TRTOOpt |
2361 | 0 | UINT64_C(228698418577408), // TRTR |
2362 | 0 | UINT64_C(3116171264), // TRTRE |
2363 | 0 | UINT64_C(3116171264), // TRTREOpt |
2364 | 0 | UINT64_C(3113222144), // TRTT |
2365 | 0 | UINT64_C(3113222144), // TRTTOpt |
2366 | 0 | UINT64_C(2466250752), // TS |
2367 | 0 | UINT64_C(2989817856), // TSCH |
2368 | 0 | UINT64_C(267181325549568), // UNPK |
2369 | 0 | UINT64_C(257285720899584), // UNPKA |
2370 | 0 | UINT64_C(248489627877376), // UNPKU |
2371 | 0 | UINT64_C(258), // UPT |
2372 | 0 | UINT64_C(253987186016499), // VA |
2373 | 0 | UINT64_C(253987186016499), // VAB |
2374 | 0 | UINT64_C(253987186016443), // VAC |
2375 | 0 | UINT64_C(253987186016497), // VACC |
2376 | 0 | UINT64_C(253987186016497), // VACCB |
2377 | 0 | UINT64_C(253987186016441), // VACCC |
2378 | 0 | UINT64_C(253987253125305), // VACCCQ |
2379 | 0 | UINT64_C(253987186024689), // VACCF |
2380 | 0 | UINT64_C(253987186028785), // VACCG |
2381 | 0 | UINT64_C(253987186020593), // VACCH |
2382 | 0 | UINT64_C(253987186032881), // VACCQ |
2383 | 0 | UINT64_C(253987253125307), // VACQ |
2384 | 0 | UINT64_C(253987186024691), // VAF |
2385 | 0 | UINT64_C(253987186028787), // VAG |
2386 | 0 | UINT64_C(253987186020595), // VAH |
2387 | 0 | UINT64_C(252887674388593), // VAP |
2388 | 0 | UINT64_C(253987186032883), // VAQ |
2389 | 0 | UINT64_C(253987186016498), // VAVG |
2390 | 0 | UINT64_C(253987186016498), // VAVGB |
2391 | 0 | UINT64_C(253987186024690), // VAVGF |
2392 | 0 | UINT64_C(253987186028786), // VAVGG |
2393 | 0 | UINT64_C(253987186020594), // VAVGH |
2394 | 0 | UINT64_C(253987186016496), // VAVGL |
2395 | 0 | UINT64_C(253987186016496), // VAVGLB |
2396 | 0 | UINT64_C(253987186024688), // VAVGLF |
2397 | 0 | UINT64_C(253987186028784), // VAVGLG |
2398 | 0 | UINT64_C(253987186020592), // VAVGLH |
2399 | 0 | UINT64_C(253987186016389), // VBPERM |
2400 | 0 | UINT64_C(253987186016451), // VCDG |
2401 | 0 | UINT64_C(253987186028739), // VCDGB |
2402 | 0 | UINT64_C(253987186016449), // VCDLG |
2403 | 0 | UINT64_C(253987186028737), // VCDLGB |
2404 | 0 | UINT64_C(253987186024643), // VCEFB |
2405 | 0 | UINT64_C(253987186024641), // VCELFB |
2406 | 0 | UINT64_C(253987186016504), // VCEQ |
2407 | 0 | UINT64_C(253987186016504), // VCEQB |
2408 | 0 | UINT64_C(253987187065080), // VCEQBS |
2409 | 0 | UINT64_C(253987186024696), // VCEQF |
2410 | 0 | UINT64_C(253987187073272), // VCEQFS |
2411 | 0 | UINT64_C(253987186028792), // VCEQG |
2412 | 0 | UINT64_C(253987187077368), // VCEQGS |
2413 | 0 | UINT64_C(253987186020600), // VCEQH |
2414 | 0 | UINT64_C(253987187069176), // VCEQHS |
2415 | 0 | UINT64_C(253987186024642), // VCFEB |
2416 | 0 | UINT64_C(252887674388573), // VCFN |
2417 | 0 | UINT64_C(253987186016449), // VCFPL |
2418 | 0 | UINT64_C(253987186016451), // VCFPS |
2419 | 0 | UINT64_C(253987186016450), // VCGD |
2420 | 0 | UINT64_C(253987186028738), // VCGDB |
2421 | 0 | UINT64_C(253987186016507), // VCH |
2422 | 0 | UINT64_C(253987186016507), // VCHB |
2423 | 0 | UINT64_C(253987187065083), // VCHBS |
2424 | 0 | UINT64_C(253987186024699), // VCHF |
2425 | 0 | UINT64_C(253987187073275), // VCHFS |
2426 | 0 | UINT64_C(253987186028795), // VCHG |
2427 | 0 | UINT64_C(253987187077371), // VCHGS |
2428 | 0 | UINT64_C(253987186020603), // VCHH |
2429 | 0 | UINT64_C(253987187069179), // VCHHS |
2430 | 0 | UINT64_C(253987186016505), // VCHL |
2431 | 0 | UINT64_C(253987186016505), // VCHLB |
2432 | 0 | UINT64_C(253987187065081), // VCHLBS |
2433 | 0 | UINT64_C(253987186024697), // VCHLF |
2434 | 0 | UINT64_C(253987187073273), // VCHLFS |
2435 | 0 | UINT64_C(253987186028793), // VCHLG |
2436 | 0 | UINT64_C(253987187077369), // VCHLGS |
2437 | 0 | UINT64_C(253987186020601), // VCHLH |
2438 | 0 | UINT64_C(253987187069177), // VCHLHS |
2439 | 0 | UINT64_C(253987186016358), // VCKSM |
2440 | 0 | UINT64_C(253987186024640), // VCLFEB |
2441 | 0 | UINT64_C(252887674388566), // VCLFNH |
2442 | 0 | UINT64_C(252887674388574), // VCLFNL |
2443 | 0 | UINT64_C(253987186016448), // VCLFP |
2444 | 0 | UINT64_C(253987186016448), // VCLGD |
2445 | 0 | UINT64_C(253987186028736), // VCLGDB |
2446 | 0 | UINT64_C(253987186016339), // VCLZ |
2447 | 0 | UINT64_C(253987186016339), // VCLZB |
2448 | 0 | UINT64_C(252887674388561), // VCLZDP |
2449 | 0 | UINT64_C(253987186024531), // VCLZF |
2450 | 0 | UINT64_C(253987186028627), // VCLZG |
2451 | 0 | UINT64_C(253987186020435), // VCLZH |
2452 | 0 | UINT64_C(252887674388565), // VCNF |
2453 | 0 | UINT64_C(252887674388599), // VCP |
2454 | 0 | UINT64_C(252887674388597), // VCRNF |
2455 | 0 | UINT64_C(253987186016450), // VCSFP |
2456 | 0 | UINT64_C(252887674388605), // VCSPH |
2457 | 0 | UINT64_C(253987186016338), // VCTZ |
2458 | 0 | UINT64_C(253987186016338), // VCTZB |
2459 | 0 | UINT64_C(253987186024530), // VCTZF |
2460 | 0 | UINT64_C(253987186028626), // VCTZG |
2461 | 0 | UINT64_C(253987186020434), // VCTZH |
2462 | 0 | UINT64_C(252887674388560), // VCVB |
2463 | 0 | UINT64_C(252887674388562), // VCVBG |
2464 | 0 | UINT64_C(252887674388562), // VCVBGOpt |
2465 | 0 | UINT64_C(252887674388560), // VCVBOpt |
2466 | 0 | UINT64_C(252887674388568), // VCVD |
2467 | 0 | UINT64_C(252887674388570), // VCVDG |
2468 | 0 | UINT64_C(252887674388602), // VDP |
2469 | 0 | UINT64_C(253987186016475), // VEC |
2470 | 0 | UINT64_C(253987186016475), // VECB |
2471 | 0 | UINT64_C(253987186024667), // VECF |
2472 | 0 | UINT64_C(253987186028763), // VECG |
2473 | 0 | UINT64_C(253987186020571), // VECH |
2474 | 0 | UINT64_C(253987186016473), // VECL |
2475 | 0 | UINT64_C(253987186016473), // VECLB |
2476 | 0 | UINT64_C(253987186024665), // VECLF |
2477 | 0 | UINT64_C(253987186028761), // VECLG |
2478 | 0 | UINT64_C(253987186020569), // VECLH |
2479 | 0 | UINT64_C(253987186016370), // VERIM |
2480 | 0 | UINT64_C(253987186016370), // VERIMB |
2481 | 0 | UINT64_C(253987186024562), // VERIMF |
2482 | 0 | UINT64_C(253987186028658), // VERIMG |
2483 | 0 | UINT64_C(253987186020466), // VERIMH |
2484 | 0 | UINT64_C(253987186016307), // VERLL |
2485 | 0 | UINT64_C(253987186016307), // VERLLB |
2486 | 0 | UINT64_C(253987186024499), // VERLLF |
2487 | 0 | UINT64_C(253987186028595), // VERLLG |
2488 | 0 | UINT64_C(253987186020403), // VERLLH |
2489 | 0 | UINT64_C(253987186016371), // VERLLV |
2490 | 0 | UINT64_C(253987186016371), // VERLLVB |
2491 | 0 | UINT64_C(253987186024563), // VERLLVF |
2492 | 0 | UINT64_C(253987186028659), // VERLLVG |
2493 | 0 | UINT64_C(253987186020467), // VERLLVH |
2494 | 0 | UINT64_C(253987186016304), // VESL |
2495 | 0 | UINT64_C(253987186016304), // VESLB |
2496 | 0 | UINT64_C(253987186024496), // VESLF |
2497 | 0 | UINT64_C(253987186028592), // VESLG |
2498 | 0 | UINT64_C(253987186020400), // VESLH |
2499 | 0 | UINT64_C(253987186016368), // VESLV |
2500 | 0 | UINT64_C(253987186016368), // VESLVB |
2501 | 0 | UINT64_C(253987186024560), // VESLVF |
2502 | 0 | UINT64_C(253987186028656), // VESLVG |
2503 | 0 | UINT64_C(253987186020464), // VESLVH |
2504 | 0 | UINT64_C(253987186016314), // VESRA |
2505 | 0 | UINT64_C(253987186016314), // VESRAB |
2506 | 0 | UINT64_C(253987186024506), // VESRAF |
2507 | 0 | UINT64_C(253987186028602), // VESRAG |
2508 | 0 | UINT64_C(253987186020410), // VESRAH |
2509 | 0 | UINT64_C(253987186016378), // VESRAV |
2510 | 0 | UINT64_C(253987186016378), // VESRAVB |
2511 | 0 | UINT64_C(253987186024570), // VESRAVF |
2512 | 0 | UINT64_C(253987186028666), // VESRAVG |
2513 | 0 | UINT64_C(253987186020474), // VESRAVH |
2514 | 0 | UINT64_C(253987186016312), // VESRL |
2515 | 0 | UINT64_C(253987186016312), // VESRLB |
2516 | 0 | UINT64_C(253987186024504), // VESRLF |
2517 | 0 | UINT64_C(253987186028600), // VESRLG |
2518 | 0 | UINT64_C(253987186020408), // VESRLH |
2519 | 0 | UINT64_C(253987186016376), // VESRLV |
2520 | 0 | UINT64_C(253987186016376), // VESRLVB |
2521 | 0 | UINT64_C(253987186024568), // VESRLVF |
2522 | 0 | UINT64_C(253987186028664), // VESRLVG |
2523 | 0 | UINT64_C(253987186020472), // VESRLVH |
2524 | 0 | UINT64_C(253987186016483), // VFA |
2525 | 0 | UINT64_C(253987186028771), // VFADB |
2526 | 0 | UINT64_C(253987186016386), // VFAE |
2527 | 0 | UINT64_C(253987186016386), // VFAEB |
2528 | 0 | UINT64_C(253987187064962), // VFAEBS |
2529 | 0 | UINT64_C(253987186024578), // VFAEF |
2530 | 0 | UINT64_C(253987187073154), // VFAEFS |
2531 | 0 | UINT64_C(253987186020482), // VFAEH |
2532 | 0 | UINT64_C(253987187069058), // VFAEHS |
2533 | 0 | UINT64_C(253987188113538), // VFAEZB |
2534 | 0 | UINT64_C(253987189162114), // VFAEZBS |
2535 | 0 | UINT64_C(253987188121730), // VFAEZF |
2536 | 0 | UINT64_C(253987189170306), // VFAEZFS |
2537 | 0 | UINT64_C(253987188117634), // VFAEZH |
2538 | 0 | UINT64_C(253987189166210), // VFAEZHS |
2539 | 0 | UINT64_C(253987186024675), // VFASB |
2540 | 0 | UINT64_C(253987186016488), // VFCE |
2541 | 0 | UINT64_C(253987186028776), // VFCEDB |
2542 | 0 | UINT64_C(253987187077352), // VFCEDBS |
2543 | 0 | UINT64_C(253987186024680), // VFCESB |
2544 | 0 | UINT64_C(253987187073256), // VFCESBS |
2545 | 0 | UINT64_C(253987186016491), // VFCH |
2546 | 0 | UINT64_C(253987186028779), // VFCHDB |
2547 | 0 | UINT64_C(253987187077355), // VFCHDBS |
2548 | 0 | UINT64_C(253987186016490), // VFCHE |
2549 | 0 | UINT64_C(253987186028778), // VFCHEDB |
2550 | 0 | UINT64_C(253987187077354), // VFCHEDBS |
2551 | 0 | UINT64_C(253987186024682), // VFCHESB |
2552 | 0 | UINT64_C(253987187073258), // VFCHESBS |
2553 | 0 | UINT64_C(253987186024683), // VFCHSB |
2554 | 0 | UINT64_C(253987187073259), // VFCHSBS |
2555 | 0 | UINT64_C(253987186016485), // VFD |
2556 | 0 | UINT64_C(253987186028773), // VFDDB |
2557 | 0 | UINT64_C(253987186024677), // VFDSB |
2558 | 0 | UINT64_C(253987186016384), // VFEE |
2559 | 0 | UINT64_C(253987186016384), // VFEEB |
2560 | 0 | UINT64_C(253987187064960), // VFEEBS |
2561 | 0 | UINT64_C(253987186024576), // VFEEF |
2562 | 0 | UINT64_C(253987187073152), // VFEEFS |
2563 | 0 | UINT64_C(253987186020480), // VFEEH |
2564 | 0 | UINT64_C(253987187069056), // VFEEHS |
2565 | 0 | UINT64_C(253987188113536), // VFEEZB |
2566 | 0 | UINT64_C(253987189162112), // VFEEZBS |
2567 | 0 | UINT64_C(253987188121728), // VFEEZF |
2568 | 0 | UINT64_C(253987189170304), // VFEEZFS |
2569 | 0 | UINT64_C(253987188117632), // VFEEZH |
2570 | 0 | UINT64_C(253987189166208), // VFEEZHS |
2571 | 0 | UINT64_C(253987186016385), // VFENE |
2572 | 0 | UINT64_C(253987186016385), // VFENEB |
2573 | 0 | UINT64_C(253987187064961), // VFENEBS |
2574 | 0 | UINT64_C(253987186024577), // VFENEF |
2575 | 0 | UINT64_C(253987187073153), // VFENEFS |
2576 | 0 | UINT64_C(253987186020481), // VFENEH |
2577 | 0 | UINT64_C(253987187069057), // VFENEHS |
2578 | 0 | UINT64_C(253987188113537), // VFENEZB |
2579 | 0 | UINT64_C(253987189162113), // VFENEZBS |
2580 | 0 | UINT64_C(253987188121729), // VFENEZF |
2581 | 0 | UINT64_C(253987189170305), // VFENEZFS |
2582 | 0 | UINT64_C(253987188117633), // VFENEZH |
2583 | 0 | UINT64_C(253987189166209), // VFENEZHS |
2584 | 0 | UINT64_C(253987186016455), // VFI |
2585 | 0 | UINT64_C(253987186028743), // VFIDB |
2586 | 0 | UINT64_C(253987186024647), // VFISB |
2587 | 0 | UINT64_C(253987186290920), // VFKEDB |
2588 | 0 | UINT64_C(253987187339496), // VFKEDBS |
2589 | 0 | UINT64_C(253987186286824), // VFKESB |
2590 | 0 | UINT64_C(253987187335400), // VFKESBS |
2591 | 0 | UINT64_C(253987186290923), // VFKHDB |
2592 | 0 | UINT64_C(253987187339499), // VFKHDBS |
2593 | 0 | UINT64_C(253987186290922), // VFKHEDB |
2594 | 0 | UINT64_C(253987187339498), // VFKHEDBS |
2595 | 0 | UINT64_C(253987186286826), // VFKHESB |
2596 | 0 | UINT64_C(253987187335402), // VFKHESBS |
2597 | 0 | UINT64_C(253987186286827), // VFKHSB |
2598 | 0 | UINT64_C(253987187335403), // VFKHSBS |
2599 | 0 | UINT64_C(253987186028748), // VFLCDB |
2600 | 0 | UINT64_C(253987186024652), // VFLCSB |
2601 | 0 | UINT64_C(253987186016452), // VFLL |
2602 | 0 | UINT64_C(253987186024644), // VFLLS |
2603 | 0 | UINT64_C(253987187077324), // VFLNDB |
2604 | 0 | UINT64_C(253987187073228), // VFLNSB |
2605 | 0 | UINT64_C(253987188125900), // VFLPDB |
2606 | 0 | UINT64_C(253987188121804), // VFLPSB |
2607 | 0 | UINT64_C(253987186016453), // VFLR |
2608 | 0 | UINT64_C(253987186028741), // VFLRD |
2609 | 0 | UINT64_C(253987186016487), // VFM |
2610 | 0 | UINT64_C(253987186016399), // VFMA |
2611 | 0 | UINT64_C(253987236348047), // VFMADB |
2612 | 0 | UINT64_C(253987219570831), // VFMASB |
2613 | 0 | UINT64_C(253987186016495), // VFMAX |
2614 | 0 | UINT64_C(253987186028783), // VFMAXDB |
2615 | 0 | UINT64_C(253987186024687), // VFMAXSB |
2616 | 0 | UINT64_C(253987186028775), // VFMDB |
2617 | 0 | UINT64_C(253987186016494), // VFMIN |
2618 | 0 | UINT64_C(253987186028782), // VFMINDB |
2619 | 0 | UINT64_C(253987186024686), // VFMINSB |
2620 | 0 | UINT64_C(253987186016398), // VFMS |
2621 | 0 | UINT64_C(253987186024679), // VFMSB |
2622 | 0 | UINT64_C(253987236348046), // VFMSDB |
2623 | 0 | UINT64_C(253987219570830), // VFMSSB |
2624 | 0 | UINT64_C(253987186016415), // VFNMA |
2625 | 0 | UINT64_C(253987236348063), // VFNMADB |
2626 | 0 | UINT64_C(253987219570847), // VFNMASB |
2627 | 0 | UINT64_C(253987186016414), // VFNMS |
2628 | 0 | UINT64_C(253987236348062), // VFNMSDB |
2629 | 0 | UINT64_C(253987219570846), // VFNMSSB |
2630 | 0 | UINT64_C(253987186016460), // VFPSO |
2631 | 0 | UINT64_C(253987186028748), // VFPSODB |
2632 | 0 | UINT64_C(253987186024652), // VFPSOSB |
2633 | 0 | UINT64_C(253987186016482), // VFS |
2634 | 0 | UINT64_C(253987186028770), // VFSDB |
2635 | 0 | UINT64_C(253987186016462), // VFSQ |
2636 | 0 | UINT64_C(253987186028750), // VFSQDB |
2637 | 0 | UINT64_C(253987186024654), // VFSQSB |
2638 | 0 | UINT64_C(253987186024674), // VFSSB |
2639 | 0 | UINT64_C(253987186016330), // VFTCI |
2640 | 0 | UINT64_C(253987186028618), // VFTCIDB |
2641 | 0 | UINT64_C(253987186024522), // VFTCISB |
2642 | 0 | UINT64_C(253987186016324), // VGBM |
2643 | 0 | UINT64_C(253987186016275), // VGEF |
2644 | 0 | UINT64_C(253987186016274), // VGEG |
2645 | 0 | UINT64_C(253987186016436), // VGFM |
2646 | 0 | UINT64_C(253987186016444), // VGFMA |
2647 | 0 | UINT64_C(253987186016444), // VGFMAB |
2648 | 0 | UINT64_C(253987219570876), // VGFMAF |
2649 | 0 | UINT64_C(253987236348092), // VGFMAG |
2650 | 0 | UINT64_C(253987202793660), // VGFMAH |
2651 | 0 | UINT64_C(253987186016436), // VGFMB |
2652 | 0 | UINT64_C(253987186024628), // VGFMF |
2653 | 0 | UINT64_C(253987186028724), // VGFMG |
2654 | 0 | UINT64_C(253987186020532), // VGFMH |
2655 | 0 | UINT64_C(253987186016326), // VGM |
2656 | 0 | UINT64_C(253987186016326), // VGMB |
2657 | 0 | UINT64_C(253987186024518), // VGMF |
2658 | 0 | UINT64_C(253987186028614), // VGMG |
2659 | 0 | UINT64_C(253987186020422), // VGMH |
2660 | 0 | UINT64_C(253987186016348), // VISTR |
2661 | 0 | UINT64_C(253987186016348), // VISTRB |
2662 | 0 | UINT64_C(253987187064924), // VISTRBS |
2663 | 0 | UINT64_C(253987186024540), // VISTRF |
2664 | 0 | UINT64_C(253987187073116), // VISTRFS |
2665 | 0 | UINT64_C(253987186020444), // VISTRH |
2666 | 0 | UINT64_C(253987187069020), // VISTRHS |
2667 | 0 | UINT64_C(253987186016262), // VL |
2668 | 0 | UINT64_C(253987186016262), // VLAlign |
2669 | 0 | UINT64_C(253987186016263), // VLBB |
2670 | 0 | UINT64_C(252887674388486), // VLBR |
2671 | 0 | UINT64_C(252887674396678), // VLBRF |
2672 | 0 | UINT64_C(252887674400774), // VLBRG |
2673 | 0 | UINT64_C(252887674392582), // VLBRH |
2674 | 0 | UINT64_C(252887674404870), // VLBRQ |
2675 | 0 | UINT64_C(252887674388485), // VLBRREP |
2676 | 0 | UINT64_C(252887674396677), // VLBRREPF |
2677 | 0 | UINT64_C(252887674400773), // VLBRREPG |
2678 | 0 | UINT64_C(252887674392581), // VLBRREPH |
2679 | 0 | UINT64_C(253987186016478), // VLC |
2680 | 0 | UINT64_C(253987186016478), // VLCB |
2681 | 0 | UINT64_C(253987186024670), // VLCF |
2682 | 0 | UINT64_C(253987186028766), // VLCG |
2683 | 0 | UINT64_C(253987186020574), // VLCH |
2684 | 0 | UINT64_C(253987186016452), // VLDE |
2685 | 0 | UINT64_C(253987186024644), // VLDEB |
2686 | 0 | UINT64_C(253987186016256), // VLEB |
2687 | 0 | UINT64_C(252887674388483), // VLEBRF |
2688 | 0 | UINT64_C(252887674388482), // VLEBRG |
2689 | 0 | UINT64_C(252887674388481), // VLEBRH |
2690 | 0 | UINT64_C(253987186016453), // VLED |
2691 | 0 | UINT64_C(253987186028741), // VLEDB |
2692 | 0 | UINT64_C(253987186016259), // VLEF |
2693 | 0 | UINT64_C(253987186016258), // VLEG |
2694 | 0 | UINT64_C(253987186016257), // VLEH |
2695 | 0 | UINT64_C(253987186016320), // VLEIB |
2696 | 0 | UINT64_C(253987186016323), // VLEIF |
2697 | 0 | UINT64_C(253987186016322), // VLEIG |
2698 | 0 | UINT64_C(253987186016321), // VLEIH |
2699 | 0 | UINT64_C(252887674388487), // VLER |
2700 | 0 | UINT64_C(252887674396679), // VLERF |
2701 | 0 | UINT64_C(252887674400775), // VLERG |
2702 | 0 | UINT64_C(252887674392583), // VLERH |
2703 | 0 | UINT64_C(253987186016289), // VLGV |
2704 | 0 | UINT64_C(253987186016289), // VLGVB |
2705 | 0 | UINT64_C(253987186024481), // VLGVF |
2706 | 0 | UINT64_C(253987186028577), // VLGVG |
2707 | 0 | UINT64_C(253987186020385), // VLGVH |
2708 | 0 | UINT64_C(252887674388553), // VLIP |
2709 | 0 | UINT64_C(253987186016311), // VLL |
2710 | 0 | UINT64_C(252887674388484), // VLLEBRZ |
2711 | 0 | UINT64_C(252887674413060), // VLLEBRZE |
2712 | 0 | UINT64_C(252887674396676), // VLLEBRZF |
2713 | 0 | UINT64_C(252887674400772), // VLLEBRZG |
2714 | 0 | UINT64_C(252887674392580), // VLLEBRZH |
2715 | 0 | UINT64_C(253987186016260), // VLLEZ |
2716 | 0 | UINT64_C(253987186016260), // VLLEZB |
2717 | 0 | UINT64_C(253987186024452), // VLLEZF |
2718 | 0 | UINT64_C(253987186028548), // VLLEZG |
2719 | 0 | UINT64_C(253987186020356), // VLLEZH |
2720 | 0 | UINT64_C(253987186040836), // VLLEZLF |
2721 | 0 | UINT64_C(253987186016310), // VLM |
2722 | 0 | UINT64_C(253987186016310), // VLMAlign |
2723 | 0 | UINT64_C(253987186016479), // VLP |
2724 | 0 | UINT64_C(253987186016479), // VLPB |
2725 | 0 | UINT64_C(253987186024671), // VLPF |
2726 | 0 | UINT64_C(253987186028767), // VLPG |
2727 | 0 | UINT64_C(253987186020575), // VLPH |
2728 | 0 | UINT64_C(253987186016342), // VLR |
2729 | 0 | UINT64_C(253987186016261), // VLREP |
2730 | 0 | UINT64_C(253987186016261), // VLREPB |
2731 | 0 | UINT64_C(253987186024453), // VLREPF |
2732 | 0 | UINT64_C(253987186028549), // VLREPG |
2733 | 0 | UINT64_C(253987186020357), // VLREPH |
2734 | 0 | UINT64_C(252887674388533), // VLRL |
2735 | 0 | UINT64_C(252887674388535), // VLRLR |
2736 | 0 | UINT64_C(253987186016290), // VLVG |
2737 | 0 | UINT64_C(253987186016290), // VLVGB |
2738 | 0 | UINT64_C(253987186024482), // VLVGF |
2739 | 0 | UINT64_C(253987186028578), // VLVGG |
2740 | 0 | UINT64_C(253987186020386), // VLVGH |
2741 | 0 | UINT64_C(253987186016354), // VLVGP |
2742 | 0 | UINT64_C(253987186016430), // VMAE |
2743 | 0 | UINT64_C(253987186016430), // VMAEB |
2744 | 0 | UINT64_C(253987219570862), // VMAEF |
2745 | 0 | UINT64_C(253987202793646), // VMAEH |
2746 | 0 | UINT64_C(253987186016427), // VMAH |
2747 | 0 | UINT64_C(253987186016427), // VMAHB |
2748 | 0 | UINT64_C(253987219570859), // VMAHF |
2749 | 0 | UINT64_C(253987202793643), // VMAHH |
2750 | 0 | UINT64_C(253987186016426), // VMAL |
2751 | 0 | UINT64_C(253987186016426), // VMALB |
2752 | 0 | UINT64_C(253987186016428), // VMALE |
2753 | 0 | UINT64_C(253987186016428), // VMALEB |
2754 | 0 | UINT64_C(253987219570860), // VMALEF |
2755 | 0 | UINT64_C(253987202793644), // VMALEH |
2756 | 0 | UINT64_C(253987219570858), // VMALF |
2757 | 0 | UINT64_C(253987186016425), // VMALH |
2758 | 0 | UINT64_C(253987186016425), // VMALHB |
2759 | 0 | UINT64_C(253987219570857), // VMALHF |
2760 | 0 | UINT64_C(253987202793641), // VMALHH |
2761 | 0 | UINT64_C(253987202793642), // VMALHW |
2762 | 0 | UINT64_C(253987186016429), // VMALO |
2763 | 0 | UINT64_C(253987186016429), // VMALOB |
2764 | 0 | UINT64_C(253987219570861), // VMALOF |
2765 | 0 | UINT64_C(253987202793645), // VMALOH |
2766 | 0 | UINT64_C(253987186016431), // VMAO |
2767 | 0 | UINT64_C(253987186016431), // VMAOB |
2768 | 0 | UINT64_C(253987219570863), // VMAOF |
2769 | 0 | UINT64_C(253987202793647), // VMAOH |
2770 | 0 | UINT64_C(253987186016422), // VME |
2771 | 0 | UINT64_C(253987186016422), // VMEB |
2772 | 0 | UINT64_C(253987186024614), // VMEF |
2773 | 0 | UINT64_C(253987186020518), // VMEH |
2774 | 0 | UINT64_C(253987186016419), // VMH |
2775 | 0 | UINT64_C(253987186016419), // VMHB |
2776 | 0 | UINT64_C(253987186024611), // VMHF |
2777 | 0 | UINT64_C(253987186020515), // VMHH |
2778 | 0 | UINT64_C(253987186016418), // VML |
2779 | 0 | UINT64_C(253987186016418), // VMLB |
2780 | 0 | UINT64_C(253987186016420), // VMLE |
2781 | 0 | UINT64_C(253987186016420), // VMLEB |
2782 | 0 | UINT64_C(253987186024612), // VMLEF |
2783 | 0 | UINT64_C(253987186020516), // VMLEH |
2784 | 0 | UINT64_C(253987186024610), // VMLF |
2785 | 0 | UINT64_C(253987186016417), // VMLH |
2786 | 0 | UINT64_C(253987186016417), // VMLHB |
2787 | 0 | UINT64_C(253987186024609), // VMLHF |
2788 | 0 | UINT64_C(253987186020513), // VMLHH |
2789 | 0 | UINT64_C(253987186020514), // VMLHW |
2790 | 0 | UINT64_C(253987186016421), // VMLO |
2791 | 0 | UINT64_C(253987186016421), // VMLOB |
2792 | 0 | UINT64_C(253987186024613), // VMLOF |
2793 | 0 | UINT64_C(253987186020517), // VMLOH |
2794 | 0 | UINT64_C(253987186016510), // VMN |
2795 | 0 | UINT64_C(253987186016510), // VMNB |
2796 | 0 | UINT64_C(253987186024702), // VMNF |
2797 | 0 | UINT64_C(253987186028798), // VMNG |
2798 | 0 | UINT64_C(253987186020606), // VMNH |
2799 | 0 | UINT64_C(253987186016508), // VMNL |
2800 | 0 | UINT64_C(253987186016508), // VMNLB |
2801 | 0 | UINT64_C(253987186024700), // VMNLF |
2802 | 0 | UINT64_C(253987186028796), // VMNLG |
2803 | 0 | UINT64_C(253987186020604), // VMNLH |
2804 | 0 | UINT64_C(253987186016423), // VMO |
2805 | 0 | UINT64_C(253987186016423), // VMOB |
2806 | 0 | UINT64_C(253987186024615), // VMOF |
2807 | 0 | UINT64_C(253987186020519), // VMOH |
2808 | 0 | UINT64_C(252887674388600), // VMP |
2809 | 0 | UINT64_C(253987186016353), // VMRH |
2810 | 0 | UINT64_C(253987186016353), // VMRHB |
2811 | 0 | UINT64_C(253987186024545), // VMRHF |
2812 | 0 | UINT64_C(253987186028641), // VMRHG |
2813 | 0 | UINT64_C(253987186020449), // VMRHH |
2814 | 0 | UINT64_C(253987186016352), // VMRL |
2815 | 0 | UINT64_C(253987186016352), // VMRLB |
2816 | 0 | UINT64_C(253987186024544), // VMRLF |
2817 | 0 | UINT64_C(253987186028640), // VMRLG |
2818 | 0 | UINT64_C(253987186020448), // VMRLH |
2819 | 0 | UINT64_C(253987186016440), // VMSL |
2820 | 0 | UINT64_C(253987236348088), // VMSLG |
2821 | 0 | UINT64_C(252887674388601), // VMSP |
2822 | 0 | UINT64_C(253987186016511), // VMX |
2823 | 0 | UINT64_C(253987186016511), // VMXB |
2824 | 0 | UINT64_C(253987186024703), // VMXF |
2825 | 0 | UINT64_C(253987186028799), // VMXG |
2826 | 0 | UINT64_C(253987186020607), // VMXH |
2827 | 0 | UINT64_C(253987186016509), // VMXL |
2828 | 0 | UINT64_C(253987186016509), // VMXLB |
2829 | 0 | UINT64_C(253987186024701), // VMXLF |
2830 | 0 | UINT64_C(253987186028797), // VMXLG |
2831 | 0 | UINT64_C(253987186020605), // VMXLH |
2832 | 0 | UINT64_C(253987186016360), // VN |
2833 | 0 | UINT64_C(253987186016361), // VNC |
2834 | 0 | UINT64_C(253987186016366), // VNN |
2835 | 0 | UINT64_C(253987186016363), // VNO |
2836 | 0 | UINT64_C(253987186016364), // VNX |
2837 | 0 | UINT64_C(253987186016362), // VO |
2838 | 0 | UINT64_C(253987186016367), // VOC |
2839 | 0 | UINT64_C(253991480918084), // VONE |
2840 | 0 | UINT64_C(253987186016388), // VPDI |
2841 | 0 | UINT64_C(253987186016396), // VPERM |
2842 | 0 | UINT64_C(253987186016404), // VPK |
2843 | 0 | UINT64_C(253987186024596), // VPKF |
2844 | 0 | UINT64_C(253987186028692), // VPKG |
2845 | 0 | UINT64_C(253987186020500), // VPKH |
2846 | 0 | UINT64_C(253987186016405), // VPKLS |
2847 | 0 | UINT64_C(253987186024597), // VPKLSF |
2848 | 0 | UINT64_C(253987187073173), // VPKLSFS |
2849 | 0 | UINT64_C(253987186028693), // VPKLSG |
2850 | 0 | UINT64_C(253987187077269), // VPKLSGS |
2851 | 0 | UINT64_C(253987186020501), // VPKLSH |
2852 | 0 | UINT64_C(253987187069077), // VPKLSHS |
2853 | 0 | UINT64_C(253987186016407), // VPKS |
2854 | 0 | UINT64_C(253987186024599), // VPKSF |
2855 | 0 | UINT64_C(253987187073175), // VPKSFS |
2856 | 0 | UINT64_C(253987186028695), // VPKSG |
2857 | 0 | UINT64_C(253987187077271), // VPKSGS |
2858 | 0 | UINT64_C(253987186020503), // VPKSH |
2859 | 0 | UINT64_C(253987187069079), // VPKSHS |
2860 | 0 | UINT64_C(252887674388532), // VPKZ |
2861 | 0 | UINT64_C(252887674388592), // VPKZR |
2862 | 0 | UINT64_C(253987186016336), // VPOPCT |
2863 | 0 | UINT64_C(253987186016336), // VPOPCTB |
2864 | 0 | UINT64_C(253987186024528), // VPOPCTF |
2865 | 0 | UINT64_C(253987186028624), // VPOPCTG |
2866 | 0 | UINT64_C(253987186020432), // VPOPCTH |
2867 | 0 | UINT64_C(252887674388571), // VPSOP |
2868 | 0 | UINT64_C(253987186016333), // VREP |
2869 | 0 | UINT64_C(253987186016333), // VREPB |
2870 | 0 | UINT64_C(253987186024525), // VREPF |
2871 | 0 | UINT64_C(253987186028621), // VREPG |
2872 | 0 | UINT64_C(253987186020429), // VREPH |
2873 | 0 | UINT64_C(253987186016325), // VREPI |
2874 | 0 | UINT64_C(253987186016325), // VREPIB |
2875 | 0 | UINT64_C(253987186024517), // VREPIF |
2876 | 0 | UINT64_C(253987186028613), // VREPIG |
2877 | 0 | UINT64_C(253987186020421), // VREPIH |
2878 | 0 | UINT64_C(252887674388603), // VRP |
2879 | 0 | UINT64_C(253987186016503), // VS |
2880 | 0 | UINT64_C(253987186016503), // VSB |
2881 | 0 | UINT64_C(253987186016445), // VSBCBI |
2882 | 0 | UINT64_C(253987253125309), // VSBCBIQ |
2883 | 0 | UINT64_C(253987186016447), // VSBI |
2884 | 0 | UINT64_C(253987253125311), // VSBIQ |
2885 | 0 | UINT64_C(253987186016501), // VSCBI |
2886 | 0 | UINT64_C(253987186016501), // VSCBIB |
2887 | 0 | UINT64_C(253987186024693), // VSCBIF |
2888 | 0 | UINT64_C(253987186028789), // VSCBIG |
2889 | 0 | UINT64_C(253987186020597), // VSCBIH |
2890 | 0 | UINT64_C(253987186032885), // VSCBIQ |
2891 | 0 | UINT64_C(253987186016283), // VSCEF |
2892 | 0 | UINT64_C(253987186016282), // VSCEG |
2893 | 0 | UINT64_C(252887674400884), // VSCHDP |
2894 | 0 | UINT64_C(252887674388596), // VSCHP |
2895 | 0 | UINT64_C(252887674396788), // VSCHSP |
2896 | 0 | UINT64_C(252887674404980), // VSCHXP |
2897 | 0 | UINT64_C(252887674388604), // VSCSHP |
2898 | 0 | UINT64_C(252887674388606), // VSDP |
2899 | 0 | UINT64_C(253987186016351), // VSEG |
2900 | 0 | UINT64_C(253987186016351), // VSEGB |
2901 | 0 | UINT64_C(253987186024543), // VSEGF |
2902 | 0 | UINT64_C(253987186020447), // VSEGH |
2903 | 0 | UINT64_C(253987186016397), // VSEL |
2904 | 0 | UINT64_C(253987186024695), // VSF |
2905 | 0 | UINT64_C(253987186028791), // VSG |
2906 | 0 | UINT64_C(253987186020599), // VSH |
2907 | 0 | UINT64_C(253987186016372), // VSL |
2908 | 0 | UINT64_C(253987186016373), // VSLB |
2909 | 0 | UINT64_C(253987186016390), // VSLD |
2910 | 0 | UINT64_C(253987186016375), // VSLDB |
2911 | 0 | UINT64_C(252887674388595), // VSP |
2912 | 0 | UINT64_C(253987186032887), // VSQ |
2913 | 0 | UINT64_C(253987186016382), // VSRA |
2914 | 0 | UINT64_C(253987186016383), // VSRAB |
2915 | 0 | UINT64_C(253987186016391), // VSRD |
2916 | 0 | UINT64_C(253987186016380), // VSRL |
2917 | 0 | UINT64_C(253987186016381), // VSRLB |
2918 | 0 | UINT64_C(252887674388569), // VSRP |
2919 | 0 | UINT64_C(252887674388594), // VSRPR |
2920 | 0 | UINT64_C(253987186016270), // VST |
2921 | 0 | UINT64_C(253987186016270), // VSTAlign |
2922 | 0 | UINT64_C(252887674388494), // VSTBR |
2923 | 0 | UINT64_C(252887674396686), // VSTBRF |
2924 | 0 | UINT64_C(252887674400782), // VSTBRG |
2925 | 0 | UINT64_C(252887674392590), // VSTBRH |
2926 | 0 | UINT64_C(252887674404878), // VSTBRQ |
2927 | 0 | UINT64_C(253987186016264), // VSTEB |
2928 | 0 | UINT64_C(252887674388491), // VSTEBRF |
2929 | 0 | UINT64_C(252887674388490), // VSTEBRG |
2930 | 0 | UINT64_C(252887674388489), // VSTEBRH |
2931 | 0 | UINT64_C(253987186016267), // VSTEF |
2932 | 0 | UINT64_C(253987186016266), // VSTEG |
2933 | 0 | UINT64_C(253987186016265), // VSTEH |
2934 | 0 | UINT64_C(252887674388495), // VSTER |
2935 | 0 | UINT64_C(252887674396687), // VSTERF |
2936 | 0 | UINT64_C(252887674400783), // VSTERG |
2937 | 0 | UINT64_C(252887674392591), // VSTERH |
2938 | 0 | UINT64_C(253987186016319), // VSTL |
2939 | 0 | UINT64_C(253987186016318), // VSTM |
2940 | 0 | UINT64_C(253987186016318), // VSTMAlign |
2941 | 0 | UINT64_C(253987186016394), // VSTRC |
2942 | 0 | UINT64_C(253987186016394), // VSTRCB |
2943 | 0 | UINT64_C(253987187064970), // VSTRCBS |
2944 | 0 | UINT64_C(253987219570826), // VSTRCF |
2945 | 0 | UINT64_C(253987220619402), // VSTRCFS |
2946 | 0 | UINT64_C(253987202793610), // VSTRCH |
2947 | 0 | UINT64_C(253987203842186), // VSTRCHS |
2948 | 0 | UINT64_C(253987188113546), // VSTRCZB |
2949 | 0 | UINT64_C(253987189162122), // VSTRCZBS |
2950 | 0 | UINT64_C(253987221667978), // VSTRCZF |
2951 | 0 | UINT64_C(253987222716554), // VSTRCZFS |
2952 | 0 | UINT64_C(253987204890762), // VSTRCZH |
2953 | 0 | UINT64_C(253987205939338), // VSTRCZHS |
2954 | 0 | UINT64_C(252887674388541), // VSTRL |
2955 | 0 | UINT64_C(252887674388543), // VSTRLR |
2956 | 0 | UINT64_C(253987186016395), // VSTRS |
2957 | 0 | UINT64_C(253987186016395), // VSTRSB |
2958 | 0 | UINT64_C(253987219570827), // VSTRSF |
2959 | 0 | UINT64_C(253987202793611), // VSTRSH |
2960 | 0 | UINT64_C(253987188113547), // VSTRSZB |
2961 | 0 | UINT64_C(253987221667979), // VSTRSZF |
2962 | 0 | UINT64_C(253987204890763), // VSTRSZH |
2963 | 0 | UINT64_C(253987186016356), // VSUM |
2964 | 0 | UINT64_C(253987186016356), // VSUMB |
2965 | 0 | UINT64_C(253987186016357), // VSUMG |
2966 | 0 | UINT64_C(253987186024549), // VSUMGF |
2967 | 0 | UINT64_C(253987186020453), // VSUMGH |
2968 | 0 | UINT64_C(253987186020452), // VSUMH |
2969 | 0 | UINT64_C(253987186016359), // VSUMQ |
2970 | 0 | UINT64_C(253987186024551), // VSUMQF |
2971 | 0 | UINT64_C(253987186028647), // VSUMQG |
2972 | 0 | UINT64_C(253987186016472), // VTM |
2973 | 0 | UINT64_C(252887674388575), // VTP |
2974 | 0 | UINT64_C(253987186016471), // VUPH |
2975 | 0 | UINT64_C(253987186016471), // VUPHB |
2976 | 0 | UINT64_C(253987186024663), // VUPHF |
2977 | 0 | UINT64_C(253987186020567), // VUPHH |
2978 | 0 | UINT64_C(252887674388540), // VUPKZ |
2979 | 0 | UINT64_C(252887674388564), // VUPKZH |
2980 | 0 | UINT64_C(252887674388572), // VUPKZL |
2981 | 0 | UINT64_C(253987186016470), // VUPL |
2982 | 0 | UINT64_C(253987186016470), // VUPLB |
2983 | 0 | UINT64_C(253987186024662), // VUPLF |
2984 | 0 | UINT64_C(253987186016469), // VUPLH |
2985 | 0 | UINT64_C(253987186016469), // VUPLHB |
2986 | 0 | UINT64_C(253987186024661), // VUPLHF |
2987 | 0 | UINT64_C(253987186020565), // VUPLHH |
2988 | 0 | UINT64_C(253987186020566), // VUPLHW |
2989 | 0 | UINT64_C(253987186016468), // VUPLL |
2990 | 0 | UINT64_C(253987186016468), // VUPLLB |
2991 | 0 | UINT64_C(253987186024660), // VUPLLF |
2992 | 0 | UINT64_C(253987186020564), // VUPLLH |
2993 | 0 | UINT64_C(253987186016365), // VX |
2994 | 0 | UINT64_C(253987186016324), // VZERO |
2995 | 0 | UINT64_C(253987186553027), // WCDGB |
2996 | 0 | UINT64_C(253987186553025), // WCDLGB |
2997 | 0 | UINT64_C(253987186548931), // WCEFB |
2998 | 0 | UINT64_C(253987186548929), // WCELFB |
2999 | 0 | UINT64_C(253987186548930), // WCFEB |
3000 | 0 | UINT64_C(253987186553026), // WCGDB |
3001 | 0 | UINT64_C(253987186548928), // WCLFEB |
3002 | 0 | UINT64_C(253987186553024), // WCLGDB |
3003 | 0 | UINT64_C(253987186553059), // WFADB |
3004 | 0 | UINT64_C(253987186548963), // WFASB |
3005 | 0 | UINT64_C(253987186557155), // WFAXB |
3006 | 0 | UINT64_C(253987186016459), // WFC |
3007 | 0 | UINT64_C(253987186028747), // WFCDB |
3008 | 0 | UINT64_C(253987186553064), // WFCEDB |
3009 | 0 | UINT64_C(253987187601640), // WFCEDBS |
3010 | 0 | UINT64_C(253987186548968), // WFCESB |
3011 | 0 | UINT64_C(253987187597544), // WFCESBS |
3012 | 0 | UINT64_C(253987186557160), // WFCEXB |
3013 | 0 | UINT64_C(253987187605736), // WFCEXBS |
3014 | 0 | UINT64_C(253987186553067), // WFCHDB |
3015 | 0 | UINT64_C(253987187601643), // WFCHDBS |
3016 | 0 | UINT64_C(253987186553066), // WFCHEDB |
3017 | 0 | UINT64_C(253987187601642), // WFCHEDBS |
3018 | 0 | UINT64_C(253987186548970), // WFCHESB |
3019 | 0 | UINT64_C(253987187597546), // WFCHESBS |
3020 | 0 | UINT64_C(253987186557162), // WFCHEXB |
3021 | 0 | UINT64_C(253987187605738), // WFCHEXBS |
3022 | 0 | UINT64_C(253987186548971), // WFCHSB |
3023 | 0 | UINT64_C(253987187597547), // WFCHSBS |
3024 | 0 | UINT64_C(253987186557163), // WFCHXB |
3025 | 0 | UINT64_C(253987187605739), // WFCHXBS |
3026 | 0 | UINT64_C(253987186024651), // WFCSB |
3027 | 0 | UINT64_C(253987186032843), // WFCXB |
3028 | 0 | UINT64_C(253987186553061), // WFDDB |
3029 | 0 | UINT64_C(253987186548965), // WFDSB |
3030 | 0 | UINT64_C(253987186557157), // WFDXB |
3031 | 0 | UINT64_C(253987186553031), // WFIDB |
3032 | 0 | UINT64_C(253987186548935), // WFISB |
3033 | 0 | UINT64_C(253987186557127), // WFIXB |
3034 | 0 | UINT64_C(253987186016458), // WFK |
3035 | 0 | UINT64_C(253987186028746), // WFKDB |
3036 | 0 | UINT64_C(253987186815208), // WFKEDB |
3037 | 0 | UINT64_C(253987187863784), // WFKEDBS |
3038 | 0 | UINT64_C(253987186811112), // WFKESB |
3039 | 0 | UINT64_C(253987187859688), // WFKESBS |
3040 | 0 | UINT64_C(253987186819304), // WFKEXB |
3041 | 0 | UINT64_C(253987187867880), // WFKEXBS |
3042 | 0 | UINT64_C(253987186815211), // WFKHDB |
3043 | 0 | UINT64_C(253987187863787), // WFKHDBS |
3044 | 0 | UINT64_C(253987186815210), // WFKHEDB |
3045 | 0 | UINT64_C(253987187863786), // WFKHEDBS |
3046 | 0 | UINT64_C(253987186811114), // WFKHESB |
3047 | 0 | UINT64_C(253987187859690), // WFKHESBS |
3048 | 0 | UINT64_C(253987186819306), // WFKHEXB |
3049 | 0 | UINT64_C(253987187867882), // WFKHEXBS |
3050 | 0 | UINT64_C(253987186811115), // WFKHSB |
3051 | 0 | UINT64_C(253987187859691), // WFKHSBS |
3052 | 0 | UINT64_C(253987186819307), // WFKHXB |
3053 | 0 | UINT64_C(253987187867883), // WFKHXBS |
3054 | 0 | UINT64_C(253987186024650), // WFKSB |
3055 | 0 | UINT64_C(253987186032842), // WFKXB |
3056 | 0 | UINT64_C(253987186553036), // WFLCDB |
3057 | 0 | UINT64_C(253987186548940), // WFLCSB |
3058 | 0 | UINT64_C(253987186557132), // WFLCXB |
3059 | 0 | UINT64_C(253987186553028), // WFLLD |
3060 | 0 | UINT64_C(253987186548932), // WFLLS |
3061 | 0 | UINT64_C(253987187601612), // WFLNDB |
3062 | 0 | UINT64_C(253987187597516), // WFLNSB |
3063 | 0 | UINT64_C(253987187605708), // WFLNXB |
3064 | 0 | UINT64_C(253987188650188), // WFLPDB |
3065 | 0 | UINT64_C(253987188646092), // WFLPSB |
3066 | 0 | UINT64_C(253987188654284), // WFLPXB |
3067 | 0 | UINT64_C(253987186553029), // WFLRD |
3068 | 0 | UINT64_C(253987186557125), // WFLRX |
3069 | 0 | UINT64_C(253987236872335), // WFMADB |
3070 | 0 | UINT64_C(253987220095119), // WFMASB |
3071 | 0 | UINT64_C(253987253649551), // WFMAXB |
3072 | 0 | UINT64_C(253987186553071), // WFMAXDB |
3073 | 0 | UINT64_C(253987186548975), // WFMAXSB |
3074 | 0 | UINT64_C(253987186557167), // WFMAXXB |
3075 | 0 | UINT64_C(253987186553063), // WFMDB |
3076 | 0 | UINT64_C(253987186553070), // WFMINDB |
3077 | 0 | UINT64_C(253987186548974), // WFMINSB |
3078 | 0 | UINT64_C(253987186557166), // WFMINXB |
3079 | 0 | UINT64_C(253987186548967), // WFMSB |
3080 | 0 | UINT64_C(253987236872334), // WFMSDB |
3081 | 0 | UINT64_C(253987220095118), // WFMSSB |
3082 | 0 | UINT64_C(253987253649550), // WFMSXB |
3083 | 0 | UINT64_C(253987186557159), // WFMXB |
3084 | 0 | UINT64_C(253987236872351), // WFNMADB |
3085 | 0 | UINT64_C(253987220095135), // WFNMASB |
3086 | 0 | UINT64_C(253987253649567), // WFNMAXB |
3087 | 0 | UINT64_C(253987236872350), // WFNMSDB |
3088 | 0 | UINT64_C(253987220095134), // WFNMSSB |
3089 | 0 | UINT64_C(253987253649566), // WFNMSXB |
3090 | 0 | UINT64_C(253987186553036), // WFPSODB |
3091 | 0 | UINT64_C(253987186548940), // WFPSOSB |
3092 | 0 | UINT64_C(253987186557132), // WFPSOXB |
3093 | 0 | UINT64_C(253987186553058), // WFSDB |
3094 | 0 | UINT64_C(253987186553038), // WFSQDB |
3095 | 0 | UINT64_C(253987186548942), // WFSQSB |
3096 | 0 | UINT64_C(253987186557134), // WFSQXB |
3097 | 0 | UINT64_C(253987186548962), // WFSSB |
3098 | 0 | UINT64_C(253987186557154), // WFSXB |
3099 | 0 | UINT64_C(253987186552906), // WFTCIDB |
3100 | 0 | UINT64_C(253987186548810), // WFTCISB |
3101 | 0 | UINT64_C(253987186557002), // WFTCIXB |
3102 | 0 | UINT64_C(253987186548932), // WLDEB |
3103 | 0 | UINT64_C(253987186553029), // WLEDB |
3104 | 0 | UINT64_C(1459617792), // X |
3105 | 0 | UINT64_C(236394999971840), // XC |
3106 | 0 | UINT64_C(249589139505282), // XG |
3107 | 0 | UINT64_C(3112304640), // XGR |
3108 | 0 | UINT64_C(3118923776), // XGRK |
3109 | 0 | UINT64_C(2533359616), // XI |
3110 | 0 | UINT64_C(211132002336768), // XIHF |
3111 | 0 | UINT64_C(211136297304064), // XILF |
3112 | 0 | UINT64_C(258385232527447), // XIY |
3113 | 0 | UINT64_C(5888), // XR |
3114 | 0 | UINT64_C(3119972352), // XRK |
3115 | 0 | UINT64_C(2994077696), // XSCH |
3116 | 0 | UINT64_C(249589139505239), // XY |
3117 | 0 | UINT64_C(272678883688448), // ZAP |
3118 | 0 | UINT64_C(0) |
3119 | 0 | }; |
3120 | 0 | const unsigned opcode = MI.getOpcode(); |
3121 | 0 | uint64_t Value = InstBits[opcode]; |
3122 | 0 | uint64_t op = 0; |
3123 | 0 | (void)op; // suppress warning |
3124 | 0 | switch (opcode) { |
3125 | 0 | case SystemZ::CSCH: |
3126 | 0 | case SystemZ::HSCH: |
3127 | 0 | case SystemZ::IPK: |
3128 | 0 | case SystemZ::NNPA: |
3129 | 0 | case SystemZ::NOP_bare: |
3130 | 0 | case SystemZ::PALB: |
3131 | 0 | case SystemZ::PCC: |
3132 | 0 | case SystemZ::PCKMO: |
3133 | 0 | case SystemZ::PFPO: |
3134 | 0 | case SystemZ::PR: |
3135 | 0 | case SystemZ::PTFF: |
3136 | 0 | case SystemZ::PTLB: |
3137 | 0 | case SystemZ::RCHP: |
3138 | 0 | case SystemZ::RSCH: |
3139 | 0 | case SystemZ::SAL: |
3140 | 0 | case SystemZ::SAM24: |
3141 | 0 | case SystemZ::SAM31: |
3142 | 0 | case SystemZ::SAM64: |
3143 | 0 | case SystemZ::SCHM: |
3144 | 0 | case SystemZ::SCKPF: |
3145 | 0 | case SystemZ::TAM: |
3146 | 0 | case SystemZ::TEND: |
3147 | 0 | case SystemZ::TRAP2: |
3148 | 0 | case SystemZ::UPT: |
3149 | 0 | case SystemZ::XSCH: { |
3150 | 0 | break; |
3151 | 0 | } |
3152 | 0 | case SystemZ::CLI: |
3153 | 0 | case SystemZ::MC: |
3154 | 0 | case SystemZ::MVI: |
3155 | 0 | case SystemZ::NI: |
3156 | 0 | case SystemZ::OI: |
3157 | 0 | case SystemZ::STNSM: |
3158 | 0 | case SystemZ::STOSM: |
3159 | 0 | case SystemZ::TM: |
3160 | 0 | case SystemZ::XI: { |
3161 | | // op: B1 |
3162 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3163 | 0 | op &= UINT64_C(15); |
3164 | 0 | op <<= 12; |
3165 | 0 | Value |= op; |
3166 | | // op: D1 |
3167 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3168 | 0 | op &= UINT64_C(4095); |
3169 | 0 | Value |= op; |
3170 | | // op: I2 |
3171 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
3172 | 0 | op &= UINT64_C(255); |
3173 | 0 | op <<= 16; |
3174 | 0 | Value |= op; |
3175 | 0 | break; |
3176 | 0 | } |
3177 | 0 | case SystemZ::LPSWEY: { |
3178 | | // op: B1 |
3179 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3180 | 0 | op &= UINT64_C(15); |
3181 | 0 | op <<= 28; |
3182 | 0 | Value |= op; |
3183 | | // op: D1 |
3184 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 1, Fixups, STI); |
3185 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
3186 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
3187 | 0 | break; |
3188 | 0 | } |
3189 | 0 | case SystemZ::AGSI: |
3190 | 0 | case SystemZ::ALGSI: |
3191 | 0 | case SystemZ::ALSI: |
3192 | 0 | case SystemZ::ASI: { |
3193 | | // op: B1 |
3194 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3195 | 0 | op &= UINT64_C(15); |
3196 | 0 | op <<= 28; |
3197 | 0 | Value |= op; |
3198 | | // op: D1 |
3199 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 1, Fixups, STI); |
3200 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
3201 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
3202 | | // op: I2 |
3203 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 2, Fixups, STI); |
3204 | 0 | op &= UINT64_C(255); |
3205 | 0 | op <<= 32; |
3206 | 0 | Value |= op; |
3207 | 0 | break; |
3208 | 0 | } |
3209 | 0 | case SystemZ::CLIY: |
3210 | 0 | case SystemZ::MVIY: |
3211 | 0 | case SystemZ::NIY: |
3212 | 0 | case SystemZ::OIY: |
3213 | 0 | case SystemZ::TMY: |
3214 | 0 | case SystemZ::XIY: { |
3215 | | // op: B1 |
3216 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3217 | 0 | op &= UINT64_C(15); |
3218 | 0 | op <<= 28; |
3219 | 0 | Value |= op; |
3220 | | // op: D1 |
3221 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 1, Fixups, STI); |
3222 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
3223 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
3224 | | // op: I2 |
3225 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
3226 | 0 | op &= UINT64_C(255); |
3227 | 0 | op <<= 32; |
3228 | 0 | Value |= op; |
3229 | 0 | break; |
3230 | 0 | } |
3231 | 0 | case SystemZ::LASP: |
3232 | 0 | case SystemZ::MVCDK: |
3233 | 0 | case SystemZ::MVCRL: |
3234 | 0 | case SystemZ::MVCSK: |
3235 | 0 | case SystemZ::STRAG: |
3236 | 0 | case SystemZ::TPROT: { |
3237 | | // op: B1 |
3238 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3239 | 0 | op &= UINT64_C(15); |
3240 | 0 | op <<= 28; |
3241 | 0 | Value |= op; |
3242 | | // op: D1 |
3243 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3244 | 0 | op &= UINT64_C(4095); |
3245 | 0 | op <<= 16; |
3246 | 0 | Value |= op; |
3247 | | // op: B2 |
3248 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3249 | 0 | op &= UINT64_C(15); |
3250 | 0 | op <<= 12; |
3251 | 0 | Value |= op; |
3252 | | // op: D2 |
3253 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
3254 | 0 | op &= UINT64_C(4095); |
3255 | 0 | Value |= op; |
3256 | 0 | break; |
3257 | 0 | } |
3258 | 0 | case SystemZ::PKA: |
3259 | 0 | case SystemZ::PKU: { |
3260 | | // op: B1 |
3261 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3262 | 0 | op &= UINT64_C(15); |
3263 | 0 | op <<= 28; |
3264 | 0 | Value |= op; |
3265 | | // op: D1 |
3266 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3267 | 0 | op &= UINT64_C(4095); |
3268 | 0 | op <<= 16; |
3269 | 0 | Value |= op; |
3270 | | // op: B2 |
3271 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3272 | 0 | op &= UINT64_C(15); |
3273 | 0 | op <<= 12; |
3274 | 0 | Value |= op; |
3275 | | // op: D2 |
3276 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
3277 | 0 | op &= UINT64_C(4095); |
3278 | 0 | Value |= op; |
3279 | | // op: L2 |
3280 | 0 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, 4, Fixups, STI); |
3281 | 0 | op &= UINT64_C(255); |
3282 | 0 | op <<= 32; |
3283 | 0 | Value |= op; |
3284 | 0 | break; |
3285 | 0 | } |
3286 | 0 | case SystemZ::CSST: |
3287 | 0 | case SystemZ::ECTG: |
3288 | 0 | case SystemZ::MVCOS: { |
3289 | | // op: B1 |
3290 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3291 | 0 | op &= UINT64_C(15); |
3292 | 0 | op <<= 28; |
3293 | 0 | Value |= op; |
3294 | | // op: D1 |
3295 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3296 | 0 | op &= UINT64_C(4095); |
3297 | 0 | op <<= 16; |
3298 | 0 | Value |= op; |
3299 | | // op: B2 |
3300 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3301 | 0 | op &= UINT64_C(15); |
3302 | 0 | op <<= 12; |
3303 | 0 | Value |= op; |
3304 | | // op: D2 |
3305 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
3306 | 0 | op &= UINT64_C(4095); |
3307 | 0 | Value |= op; |
3308 | | // op: R3 |
3309 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
3310 | 0 | op &= UINT64_C(15); |
3311 | 0 | op <<= 36; |
3312 | 0 | Value |= op; |
3313 | 0 | break; |
3314 | 0 | } |
3315 | 0 | case SystemZ::CGHSI: |
3316 | 0 | case SystemZ::CHHSI: |
3317 | 0 | case SystemZ::CHSI: |
3318 | 0 | case SystemZ::MVGHI: |
3319 | 0 | case SystemZ::MVHHI: |
3320 | 0 | case SystemZ::MVHI: { |
3321 | | // op: B1 |
3322 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3323 | 0 | op &= UINT64_C(15); |
3324 | 0 | op <<= 28; |
3325 | 0 | Value |= op; |
3326 | | // op: D1 |
3327 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3328 | 0 | op &= UINT64_C(4095); |
3329 | 0 | op <<= 16; |
3330 | 0 | Value |= op; |
3331 | | // op: I2 |
3332 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
3333 | 0 | op &= UINT64_C(65535); |
3334 | 0 | Value |= op; |
3335 | 0 | break; |
3336 | 0 | } |
3337 | 0 | case SystemZ::CLFHSI: |
3338 | 0 | case SystemZ::CLGHSI: |
3339 | 0 | case SystemZ::CLHHSI: |
3340 | 0 | case SystemZ::TBEGIN: |
3341 | 0 | case SystemZ::TBEGINC: { |
3342 | | // op: B1 |
3343 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3344 | 0 | op &= UINT64_C(15); |
3345 | 0 | op <<= 28; |
3346 | 0 | Value |= op; |
3347 | | // op: D1 |
3348 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3349 | 0 | op &= UINT64_C(4095); |
3350 | 0 | op <<= 16; |
3351 | 0 | Value |= op; |
3352 | | // op: I2 |
3353 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 2, Fixups, STI); |
3354 | 0 | op &= UINT64_C(65535); |
3355 | 0 | Value |= op; |
3356 | 0 | break; |
3357 | 0 | } |
3358 | 0 | case SystemZ::TP: { |
3359 | | // op: B1 |
3360 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3361 | 0 | op &= UINT64_C(15); |
3362 | 0 | op <<= 28; |
3363 | 0 | Value |= op; |
3364 | | // op: D1 |
3365 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3366 | 0 | op &= UINT64_C(4095); |
3367 | 0 | op <<= 16; |
3368 | 0 | Value |= op; |
3369 | | // op: L1 |
3370 | 0 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
3371 | 0 | op &= UINT64_C(15); |
3372 | 0 | op <<= 36; |
3373 | 0 | Value |= op; |
3374 | 0 | break; |
3375 | 0 | } |
3376 | 0 | case SystemZ::SRP: { |
3377 | | // op: B1 |
3378 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3379 | 0 | op &= UINT64_C(15); |
3380 | 0 | op <<= 28; |
3381 | 0 | Value |= op; |
3382 | | // op: D1 |
3383 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3384 | 0 | op &= UINT64_C(4095); |
3385 | 0 | op <<= 16; |
3386 | 0 | Value |= op; |
3387 | | // op: L1 |
3388 | 0 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
3389 | 0 | op &= UINT64_C(15); |
3390 | 0 | op <<= 36; |
3391 | 0 | Value |= op; |
3392 | | // op: B2 |
3393 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3394 | 0 | op &= UINT64_C(15); |
3395 | 0 | op <<= 12; |
3396 | 0 | Value |= op; |
3397 | | // op: D2 |
3398 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
3399 | 0 | op &= UINT64_C(4095); |
3400 | 0 | Value |= op; |
3401 | | // op: I3 |
3402 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
3403 | 0 | op &= UINT64_C(15); |
3404 | 0 | op <<= 32; |
3405 | 0 | Value |= op; |
3406 | 0 | break; |
3407 | 0 | } |
3408 | 0 | case SystemZ::AP: |
3409 | 0 | case SystemZ::CP: |
3410 | 0 | case SystemZ::DP: |
3411 | 0 | case SystemZ::MP: |
3412 | 0 | case SystemZ::MVO: |
3413 | 0 | case SystemZ::PACK: |
3414 | 0 | case SystemZ::SP: |
3415 | 0 | case SystemZ::UNPK: |
3416 | 0 | case SystemZ::ZAP: { |
3417 | | // op: B1 |
3418 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3419 | 0 | op &= UINT64_C(15); |
3420 | 0 | op <<= 28; |
3421 | 0 | Value |= op; |
3422 | | // op: D1 |
3423 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3424 | 0 | op &= UINT64_C(4095); |
3425 | 0 | op <<= 16; |
3426 | 0 | Value |= op; |
3427 | | // op: L1 |
3428 | 0 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
3429 | 0 | op &= UINT64_C(15); |
3430 | 0 | op <<= 36; |
3431 | 0 | Value |= op; |
3432 | | // op: B2 |
3433 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3434 | 0 | op &= UINT64_C(15); |
3435 | 0 | op <<= 12; |
3436 | 0 | Value |= op; |
3437 | | // op: D2 |
3438 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
3439 | 0 | op &= UINT64_C(4095); |
3440 | 0 | Value |= op; |
3441 | | // op: L2 |
3442 | 0 | op = getLenEncoding<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
3443 | 0 | op &= UINT64_C(15); |
3444 | 0 | op <<= 32; |
3445 | 0 | Value |= op; |
3446 | 0 | break; |
3447 | 0 | } |
3448 | 0 | case SystemZ::CLC: |
3449 | 0 | case SystemZ::ED: |
3450 | 0 | case SystemZ::EDMK: |
3451 | 0 | case SystemZ::MVC: |
3452 | 0 | case SystemZ::MVCIN: |
3453 | 0 | case SystemZ::MVN: |
3454 | 0 | case SystemZ::MVZ: |
3455 | 0 | case SystemZ::NC: |
3456 | 0 | case SystemZ::OC: |
3457 | 0 | case SystemZ::TR: |
3458 | 0 | case SystemZ::TRT: |
3459 | 0 | case SystemZ::TRTR: |
3460 | 0 | case SystemZ::UNPKA: |
3461 | 0 | case SystemZ::UNPKU: |
3462 | 0 | case SystemZ::XC: { |
3463 | | // op: B1 |
3464 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3465 | 0 | op &= UINT64_C(15); |
3466 | 0 | op <<= 28; |
3467 | 0 | Value |= op; |
3468 | | // op: D1 |
3469 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3470 | 0 | op &= UINT64_C(4095); |
3471 | 0 | op <<= 16; |
3472 | 0 | Value |= op; |
3473 | | // op: L1 |
3474 | 0 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
3475 | 0 | op &= UINT64_C(255); |
3476 | 0 | op <<= 32; |
3477 | 0 | Value |= op; |
3478 | | // op: B2 |
3479 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3480 | 0 | op &= UINT64_C(15); |
3481 | 0 | op <<= 12; |
3482 | 0 | Value |= op; |
3483 | | // op: D2 |
3484 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
3485 | 0 | op &= UINT64_C(4095); |
3486 | 0 | Value |= op; |
3487 | 0 | break; |
3488 | 0 | } |
3489 | 0 | case SystemZ::InsnSI: { |
3490 | | // op: B1 |
3491 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3492 | 0 | op &= UINT64_C(15); |
3493 | 0 | op <<= 12; |
3494 | 0 | Value |= op; |
3495 | | // op: D1 |
3496 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3497 | 0 | op &= UINT64_C(4095); |
3498 | 0 | Value |= op; |
3499 | | // op: I2 |
3500 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 3, Fixups, STI); |
3501 | 0 | op &= UINT64_C(255); |
3502 | 0 | op <<= 16; |
3503 | 0 | Value |= op; |
3504 | | // op: enc |
3505 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
3506 | 0 | op &= UINT64_C(4278190080); |
3507 | 0 | Value |= op; |
3508 | 0 | break; |
3509 | 0 | } |
3510 | 0 | case SystemZ::InsnSIY: { |
3511 | | // op: B1 |
3512 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3513 | 0 | op &= UINT64_C(15); |
3514 | 0 | op <<= 28; |
3515 | 0 | Value |= op; |
3516 | | // op: D1 |
3517 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
3518 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
3519 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
3520 | | // op: I2 |
3521 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
3522 | 0 | op &= UINT64_C(255); |
3523 | 0 | op <<= 32; |
3524 | 0 | Value |= op; |
3525 | | // op: enc |
3526 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
3527 | 0 | Value |= (op & UINT64_C(280375465082880)); |
3528 | 0 | Value |= (op & UINT64_C(255)); |
3529 | 0 | break; |
3530 | 0 | } |
3531 | 0 | case SystemZ::LPD: |
3532 | 0 | case SystemZ::LPDG: { |
3533 | | // op: B1 |
3534 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3535 | 0 | op &= UINT64_C(15); |
3536 | 0 | op <<= 28; |
3537 | 0 | Value |= op; |
3538 | | // op: D1 |
3539 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3540 | 0 | op &= UINT64_C(4095); |
3541 | 0 | op <<= 16; |
3542 | 0 | Value |= op; |
3543 | | // op: B2 |
3544 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3545 | 0 | op &= UINT64_C(15); |
3546 | 0 | op <<= 12; |
3547 | 0 | Value |= op; |
3548 | | // op: D2 |
3549 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
3550 | 0 | op &= UINT64_C(4095); |
3551 | 0 | Value |= op; |
3552 | | // op: R3 |
3553 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3554 | 0 | op &= UINT64_C(15); |
3555 | 0 | op <<= 36; |
3556 | 0 | Value |= op; |
3557 | 0 | break; |
3558 | 0 | } |
3559 | 0 | case SystemZ::InsnSSF: { |
3560 | | // op: B1 |
3561 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3562 | 0 | op &= UINT64_C(15); |
3563 | 0 | op <<= 28; |
3564 | 0 | Value |= op; |
3565 | | // op: D1 |
3566 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3567 | 0 | op &= UINT64_C(4095); |
3568 | 0 | op <<= 16; |
3569 | 0 | Value |= op; |
3570 | | // op: B2 |
3571 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3572 | 0 | op &= UINT64_C(15); |
3573 | 0 | op <<= 12; |
3574 | 0 | Value |= op; |
3575 | | // op: D2 |
3576 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
3577 | 0 | op &= UINT64_C(4095); |
3578 | 0 | Value |= op; |
3579 | | // op: R3 |
3580 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
3581 | 0 | op &= UINT64_C(15); |
3582 | 0 | op <<= 36; |
3583 | 0 | Value |= op; |
3584 | | // op: enc |
3585 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
3586 | 0 | Value |= (op & UINT64_C(280375465082880)); |
3587 | 0 | Value |= (op & UINT64_C(64424509440)); |
3588 | 0 | break; |
3589 | 0 | } |
3590 | 0 | case SystemZ::InsnSSE: { |
3591 | | // op: B1 |
3592 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3593 | 0 | op &= UINT64_C(15); |
3594 | 0 | op <<= 28; |
3595 | 0 | Value |= op; |
3596 | | // op: D1 |
3597 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3598 | 0 | op &= UINT64_C(4095); |
3599 | 0 | op <<= 16; |
3600 | 0 | Value |= op; |
3601 | | // op: B2 |
3602 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3603 | 0 | op &= UINT64_C(15); |
3604 | 0 | op <<= 12; |
3605 | 0 | Value |= op; |
3606 | | // op: D2 |
3607 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
3608 | 0 | op &= UINT64_C(4095); |
3609 | 0 | Value |= op; |
3610 | | // op: enc |
3611 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
3612 | 0 | op &= UINT64_C(281470681743360); |
3613 | 0 | Value |= op; |
3614 | 0 | break; |
3615 | 0 | } |
3616 | 0 | case SystemZ::InsnSIL: { |
3617 | | // op: B1 |
3618 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3619 | 0 | op &= UINT64_C(15); |
3620 | 0 | op <<= 28; |
3621 | 0 | Value |= op; |
3622 | | // op: D1 |
3623 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3624 | 0 | op &= UINT64_C(4095); |
3625 | 0 | op <<= 16; |
3626 | 0 | Value |= op; |
3627 | | // op: I2 |
3628 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 3, Fixups, STI); |
3629 | 0 | op &= UINT64_C(65535); |
3630 | 0 | Value |= op; |
3631 | | // op: enc |
3632 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
3633 | 0 | op &= UINT64_C(281470681743360); |
3634 | 0 | Value |= op; |
3635 | 0 | break; |
3636 | 0 | } |
3637 | 0 | case SystemZ::CFC: |
3638 | 0 | case SystemZ::LBEAR: |
3639 | 0 | case SystemZ::LCCTL: |
3640 | 0 | case SystemZ::LFAS: |
3641 | 0 | case SystemZ::LFPC: |
3642 | 0 | case SystemZ::LPCTL: |
3643 | 0 | case SystemZ::LPP: |
3644 | 0 | case SystemZ::LPSW: |
3645 | 0 | case SystemZ::LPSWE: |
3646 | 0 | case SystemZ::LSCTL: |
3647 | 0 | case SystemZ::MSCH: |
3648 | 0 | case SystemZ::PC: |
3649 | 0 | case SystemZ::QCTRI: |
3650 | 0 | case SystemZ::QPACI: |
3651 | 0 | case SystemZ::QSI: |
3652 | 0 | case SystemZ::RP: |
3653 | 0 | case SystemZ::SAC: |
3654 | 0 | case SystemZ::SACF: |
3655 | 0 | case SystemZ::SCK: |
3656 | 0 | case SystemZ::SCKC: |
3657 | 0 | case SystemZ::SIE: |
3658 | 0 | case SystemZ::SIGA: |
3659 | 0 | case SystemZ::SPKA: |
3660 | 0 | case SystemZ::SPT: |
3661 | 0 | case SystemZ::SPX: |
3662 | 0 | case SystemZ::SRNM: |
3663 | 0 | case SystemZ::SRNMB: |
3664 | 0 | case SystemZ::SRNMT: |
3665 | 0 | case SystemZ::SSCH: |
3666 | 0 | case SystemZ::SSM: |
3667 | 0 | case SystemZ::STAP: |
3668 | 0 | case SystemZ::STBEAR: |
3669 | 0 | case SystemZ::STCK: |
3670 | 0 | case SystemZ::STCKC: |
3671 | 0 | case SystemZ::STCKE: |
3672 | 0 | case SystemZ::STCKF: |
3673 | 0 | case SystemZ::STCPS: |
3674 | 0 | case SystemZ::STCRW: |
3675 | 0 | case SystemZ::STFL: |
3676 | 0 | case SystemZ::STFLE: |
3677 | 0 | case SystemZ::STFPC: |
3678 | 0 | case SystemZ::STIDP: |
3679 | 0 | case SystemZ::STPT: |
3680 | 0 | case SystemZ::STPX: |
3681 | 0 | case SystemZ::STSCH: |
3682 | 0 | case SystemZ::STSI: |
3683 | 0 | case SystemZ::TABORT: |
3684 | 0 | case SystemZ::TPI: |
3685 | 0 | case SystemZ::TRAP4: |
3686 | 0 | case SystemZ::TS: |
3687 | 0 | case SystemZ::TSCH: { |
3688 | | // op: B2 |
3689 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3690 | 0 | op &= UINT64_C(15); |
3691 | 0 | op <<= 12; |
3692 | 0 | Value |= op; |
3693 | | // op: D2 |
3694 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
3695 | 0 | op &= UINT64_C(4095); |
3696 | 0 | Value |= op; |
3697 | 0 | break; |
3698 | 0 | } |
3699 | 0 | case SystemZ::InsnS: { |
3700 | | // op: B2 |
3701 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3702 | 0 | op &= UINT64_C(15); |
3703 | 0 | op <<= 12; |
3704 | 0 | Value |= op; |
3705 | | // op: D2 |
3706 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3707 | 0 | op &= UINT64_C(4095); |
3708 | 0 | Value |= op; |
3709 | | // op: enc |
3710 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
3711 | 0 | op &= UINT64_C(4294901760); |
3712 | 0 | Value |= op; |
3713 | 0 | break; |
3714 | 0 | } |
3715 | 0 | case SystemZ::NIAI: { |
3716 | | // op: I1 |
3717 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3718 | 0 | op &= UINT64_C(15); |
3719 | 0 | op <<= 4; |
3720 | 0 | Value |= op; |
3721 | | // op: I2 |
3722 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 1, Fixups, STI); |
3723 | 0 | op &= UINT64_C(15); |
3724 | 0 | Value |= op; |
3725 | 0 | break; |
3726 | 0 | } |
3727 | 0 | case SystemZ::SVC: { |
3728 | | // op: I1 |
3729 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 0, Fixups, STI); |
3730 | 0 | op &= UINT64_C(255); |
3731 | 0 | Value |= op; |
3732 | 0 | break; |
3733 | 0 | } |
3734 | 0 | case SystemZ::BRCAsm: { |
3735 | | // op: M1 |
3736 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3737 | 0 | op &= UINT64_C(15); |
3738 | 0 | op <<= 20; |
3739 | 0 | Value |= op; |
3740 | | // op: RI2 |
3741 | 0 | op = getPC16DBLEncoding(MI, 1, Fixups, STI); |
3742 | 0 | op &= UINT64_C(65535); |
3743 | 0 | Value |= op; |
3744 | 0 | break; |
3745 | 0 | } |
3746 | 0 | case SystemZ::BCAsm: { |
3747 | | // op: M1 |
3748 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3749 | 0 | op &= UINT64_C(15); |
3750 | 0 | op <<= 20; |
3751 | 0 | Value |= op; |
3752 | | // op: X2 |
3753 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3754 | 0 | op &= UINT64_C(15); |
3755 | 0 | op <<= 16; |
3756 | 0 | Value |= op; |
3757 | | // op: B2 |
3758 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3759 | 0 | op &= UINT64_C(15); |
3760 | 0 | op <<= 12; |
3761 | 0 | Value |= op; |
3762 | | // op: D2 |
3763 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3764 | 0 | op &= UINT64_C(4095); |
3765 | 0 | Value |= op; |
3766 | 0 | break; |
3767 | 0 | } |
3768 | 0 | case SystemZ::BPRP: { |
3769 | | // op: M1 |
3770 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3771 | 0 | op &= UINT64_C(15); |
3772 | 0 | op <<= 36; |
3773 | 0 | Value |= op; |
3774 | | // op: RI2 |
3775 | 0 | op = getPC12DBLBPPEncoding(MI, 1, Fixups, STI); |
3776 | 0 | op &= UINT64_C(4095); |
3777 | 0 | op <<= 24; |
3778 | 0 | Value |= op; |
3779 | | // op: RI3 |
3780 | 0 | op = getPC24DBLBPPEncoding(MI, 2, Fixups, STI); |
3781 | 0 | op &= UINT64_C(16777215); |
3782 | 0 | Value |= op; |
3783 | 0 | break; |
3784 | 0 | } |
3785 | 0 | case SystemZ::BPP: { |
3786 | | // op: M1 |
3787 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3788 | 0 | op &= UINT64_C(15); |
3789 | 0 | op <<= 36; |
3790 | 0 | Value |= op; |
3791 | | // op: RI2 |
3792 | 0 | op = getPC16DBLBPPEncoding(MI, 1, Fixups, STI); |
3793 | 0 | op &= UINT64_C(65535); |
3794 | 0 | Value |= op; |
3795 | | // op: B3 |
3796 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3797 | 0 | op &= UINT64_C(15); |
3798 | 0 | op <<= 28; |
3799 | 0 | Value |= op; |
3800 | | // op: D3 |
3801 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
3802 | 0 | op &= UINT64_C(4095); |
3803 | 0 | op <<= 16; |
3804 | 0 | Value |= op; |
3805 | 0 | break; |
3806 | 0 | } |
3807 | 0 | case SystemZ::BRCLAsm: |
3808 | 0 | case SystemZ::PFDRL: { |
3809 | | // op: M1 |
3810 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3811 | 0 | op &= UINT64_C(15); |
3812 | 0 | op <<= 36; |
3813 | 0 | Value |= op; |
3814 | | // op: RI2 |
3815 | 0 | op = getPC32DBLEncoding(MI, 1, Fixups, STI); |
3816 | 0 | op &= UINT64_C(4294967295); |
3817 | 0 | Value |= op; |
3818 | 0 | break; |
3819 | 0 | } |
3820 | 0 | case SystemZ::BICAsm: |
3821 | 0 | case SystemZ::PFD: { |
3822 | | // op: M1 |
3823 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3824 | 0 | op &= UINT64_C(15); |
3825 | 0 | op <<= 36; |
3826 | 0 | Value |= op; |
3827 | | // op: X2 |
3828 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3829 | 0 | op &= UINT64_C(15); |
3830 | 0 | op <<= 32; |
3831 | 0 | Value |= op; |
3832 | | // op: B2 |
3833 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3834 | 0 | op &= UINT64_C(15); |
3835 | 0 | op <<= 28; |
3836 | 0 | Value |= op; |
3837 | | // op: D2 |
3838 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
3839 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
3840 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
3841 | 0 | break; |
3842 | 0 | } |
3843 | 0 | case SystemZ::BRC: { |
3844 | | // op: M1 |
3845 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3846 | 0 | op &= UINT64_C(15); |
3847 | 0 | op <<= 20; |
3848 | 0 | Value |= op; |
3849 | | // op: RI2 |
3850 | 0 | op = getPC16DBLEncoding(MI, 2, Fixups, STI); |
3851 | 0 | op &= UINT64_C(65535); |
3852 | 0 | Value |= op; |
3853 | 0 | break; |
3854 | 0 | } |
3855 | 0 | case SystemZ::BC: { |
3856 | | // op: M1 |
3857 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3858 | 0 | op &= UINT64_C(15); |
3859 | 0 | op <<= 20; |
3860 | 0 | Value |= op; |
3861 | | // op: X2 |
3862 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
3863 | 0 | op &= UINT64_C(15); |
3864 | 0 | op <<= 16; |
3865 | 0 | Value |= op; |
3866 | | // op: B2 |
3867 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3868 | 0 | op &= UINT64_C(15); |
3869 | 0 | op <<= 12; |
3870 | 0 | Value |= op; |
3871 | | // op: D2 |
3872 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
3873 | 0 | op &= UINT64_C(4095); |
3874 | 0 | Value |= op; |
3875 | 0 | break; |
3876 | 0 | } |
3877 | 0 | case SystemZ::BRCL: { |
3878 | | // op: M1 |
3879 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3880 | 0 | op &= UINT64_C(15); |
3881 | 0 | op <<= 36; |
3882 | 0 | Value |= op; |
3883 | | // op: RI2 |
3884 | 0 | op = getPC32DBLEncoding(MI, 2, Fixups, STI); |
3885 | 0 | op &= UINT64_C(4294967295); |
3886 | 0 | Value |= op; |
3887 | 0 | break; |
3888 | 0 | } |
3889 | 0 | case SystemZ::BIC: { |
3890 | | // op: M1 |
3891 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3892 | 0 | op &= UINT64_C(15); |
3893 | 0 | op <<= 36; |
3894 | 0 | Value |= op; |
3895 | | // op: X2 |
3896 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
3897 | 0 | op &= UINT64_C(15); |
3898 | 0 | op <<= 32; |
3899 | 0 | Value |= op; |
3900 | | // op: B2 |
3901 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3902 | 0 | op &= UINT64_C(15); |
3903 | 0 | op <<= 28; |
3904 | 0 | Value |= op; |
3905 | | // op: D2 |
3906 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
3907 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
3908 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
3909 | 0 | break; |
3910 | 0 | } |
3911 | 0 | case SystemZ::BCRAsm: { |
3912 | | // op: R1 |
3913 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 0, Fixups, STI); |
3914 | 0 | op &= UINT64_C(15); |
3915 | 0 | op <<= 4; |
3916 | 0 | Value |= op; |
3917 | | // op: R2 |
3918 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3919 | 0 | op &= UINT64_C(15); |
3920 | 0 | Value |= op; |
3921 | 0 | break; |
3922 | 0 | } |
3923 | 0 | case SystemZ::CDPT: |
3924 | 0 | case SystemZ::CDZT: |
3925 | 0 | case SystemZ::CPDT: |
3926 | 0 | case SystemZ::CPXT: |
3927 | 0 | case SystemZ::CXPT: |
3928 | 0 | case SystemZ::CXZT: |
3929 | 0 | case SystemZ::CZDT: |
3930 | 0 | case SystemZ::CZXT: { |
3931 | | // op: R1 |
3932 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3933 | 0 | op &= UINT64_C(15); |
3934 | 0 | op <<= 12; |
3935 | 0 | Value |= op; |
3936 | | // op: B2 |
3937 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3938 | 0 | op &= UINT64_C(15); |
3939 | 0 | op <<= 28; |
3940 | 0 | Value |= op; |
3941 | | // op: D2 |
3942 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
3943 | 0 | op &= UINT64_C(4095); |
3944 | 0 | op <<= 16; |
3945 | 0 | Value |= op; |
3946 | | // op: L2 |
3947 | 0 | op = getLenEncoding<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
3948 | 0 | op &= UINT64_C(255); |
3949 | 0 | op <<= 32; |
3950 | 0 | Value |= op; |
3951 | | // op: M3 |
3952 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
3953 | 0 | op &= UINT64_C(15); |
3954 | 0 | op <<= 8; |
3955 | 0 | Value |= op; |
3956 | 0 | break; |
3957 | 0 | } |
3958 | 0 | case SystemZ::MY: |
3959 | 0 | case SystemZ::MYH: |
3960 | 0 | case SystemZ::MYL: |
3961 | 0 | case SystemZ::SLDT: |
3962 | 0 | case SystemZ::SLXT: |
3963 | 0 | case SystemZ::SRDT: |
3964 | 0 | case SystemZ::SRXT: { |
3965 | | // op: R1 |
3966 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3967 | 0 | op &= UINT64_C(15); |
3968 | 0 | op <<= 12; |
3969 | 0 | Value |= op; |
3970 | | // op: R3 |
3971 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3972 | 0 | op &= UINT64_C(15); |
3973 | 0 | op <<= 36; |
3974 | 0 | Value |= op; |
3975 | | // op: X2 |
3976 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
3977 | 0 | op &= UINT64_C(15); |
3978 | 0 | op <<= 32; |
3979 | 0 | Value |= op; |
3980 | | // op: B2 |
3981 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3982 | 0 | op &= UINT64_C(15); |
3983 | 0 | op <<= 28; |
3984 | 0 | Value |= op; |
3985 | | // op: D2 |
3986 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
3987 | 0 | op &= UINT64_C(4095); |
3988 | 0 | op <<= 16; |
3989 | 0 | Value |= op; |
3990 | 0 | break; |
3991 | 0 | } |
3992 | 0 | case SystemZ::MYHR: |
3993 | 0 | case SystemZ::MYLR: |
3994 | 0 | case SystemZ::MYR: { |
3995 | | // op: R1 |
3996 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3997 | 0 | op &= UINT64_C(15); |
3998 | 0 | op <<= 12; |
3999 | 0 | Value |= op; |
4000 | | // op: R3 |
4001 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4002 | 0 | op &= UINT64_C(15); |
4003 | 0 | op <<= 4; |
4004 | 0 | Value |= op; |
4005 | | // op: R2 |
4006 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4007 | 0 | op &= UINT64_C(15); |
4008 | 0 | Value |= op; |
4009 | 0 | break; |
4010 | 0 | } |
4011 | 0 | case SystemZ::MAD: |
4012 | 0 | case SystemZ::MADB: |
4013 | 0 | case SystemZ::MAE: |
4014 | 0 | case SystemZ::MAEB: |
4015 | 0 | case SystemZ::MAY: |
4016 | 0 | case SystemZ::MAYH: |
4017 | 0 | case SystemZ::MAYL: |
4018 | 0 | case SystemZ::MSD: |
4019 | 0 | case SystemZ::MSDB: |
4020 | 0 | case SystemZ::MSE: |
4021 | 0 | case SystemZ::MSEB: { |
4022 | | // op: R1 |
4023 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4024 | 0 | op &= UINT64_C(15); |
4025 | 0 | op <<= 12; |
4026 | 0 | Value |= op; |
4027 | | // op: R3 |
4028 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4029 | 0 | op &= UINT64_C(15); |
4030 | 0 | op <<= 36; |
4031 | 0 | Value |= op; |
4032 | | // op: X2 |
4033 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
4034 | 0 | op &= UINT64_C(15); |
4035 | 0 | op <<= 32; |
4036 | 0 | Value |= op; |
4037 | | // op: B2 |
4038 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4039 | 0 | op &= UINT64_C(15); |
4040 | 0 | op <<= 28; |
4041 | 0 | Value |= op; |
4042 | | // op: D2 |
4043 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
4044 | 0 | op &= UINT64_C(4095); |
4045 | 0 | op <<= 16; |
4046 | 0 | Value |= op; |
4047 | 0 | break; |
4048 | 0 | } |
4049 | 0 | case SystemZ::MADBR: |
4050 | 0 | case SystemZ::MADR: |
4051 | 0 | case SystemZ::MAEBR: |
4052 | 0 | case SystemZ::MAER: |
4053 | 0 | case SystemZ::MAYHR: |
4054 | 0 | case SystemZ::MAYLR: |
4055 | 0 | case SystemZ::MAYR: |
4056 | 0 | case SystemZ::MSDBR: |
4057 | 0 | case SystemZ::MSDR: |
4058 | 0 | case SystemZ::MSEBR: |
4059 | 0 | case SystemZ::MSER: { |
4060 | | // op: R1 |
4061 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4062 | 0 | op &= UINT64_C(15); |
4063 | 0 | op <<= 12; |
4064 | 0 | Value |= op; |
4065 | | // op: R3 |
4066 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4067 | 0 | op &= UINT64_C(15); |
4068 | 0 | op <<= 4; |
4069 | 0 | Value |= op; |
4070 | | // op: R2 |
4071 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4072 | 0 | op &= UINT64_C(15); |
4073 | 0 | Value |= op; |
4074 | 0 | break; |
4075 | 0 | } |
4076 | 0 | case SystemZ::SLA: |
4077 | 0 | case SystemZ::SLDA: |
4078 | 0 | case SystemZ::SLDL: |
4079 | 0 | case SystemZ::SLL: |
4080 | 0 | case SystemZ::SRA: |
4081 | 0 | case SystemZ::SRDA: |
4082 | 0 | case SystemZ::SRDL: |
4083 | 0 | case SystemZ::SRL: { |
4084 | | // op: R1 |
4085 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4086 | 0 | op &= UINT64_C(15); |
4087 | 0 | op <<= 20; |
4088 | 0 | Value |= op; |
4089 | | // op: B2 |
4090 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4091 | 0 | op &= UINT64_C(15); |
4092 | 0 | op <<= 12; |
4093 | 0 | Value |= op; |
4094 | | // op: D2 |
4095 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4096 | 0 | op &= UINT64_C(4095); |
4097 | 0 | Value |= op; |
4098 | 0 | break; |
4099 | 0 | } |
4100 | 0 | case SystemZ::CGHI: |
4101 | 0 | case SystemZ::CHI: |
4102 | 0 | case SystemZ::LGHI: |
4103 | 0 | case SystemZ::LHI: { |
4104 | | // op: R1 |
4105 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4106 | 0 | op &= UINT64_C(15); |
4107 | 0 | op <<= 20; |
4108 | 0 | Value |= op; |
4109 | | // op: I2 |
4110 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 1, Fixups, STI); |
4111 | 0 | op &= UINT64_C(65535); |
4112 | 0 | Value |= op; |
4113 | 0 | break; |
4114 | 0 | } |
4115 | 0 | case SystemZ::AGHI: |
4116 | 0 | case SystemZ::AHI: |
4117 | 0 | case SystemZ::MGHI: |
4118 | 0 | case SystemZ::MHI: { |
4119 | | // op: R1 |
4120 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4121 | 0 | op &= UINT64_C(15); |
4122 | 0 | op <<= 20; |
4123 | 0 | Value |= op; |
4124 | | // op: I2 |
4125 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
4126 | 0 | op &= UINT64_C(65535); |
4127 | 0 | Value |= op; |
4128 | 0 | break; |
4129 | 0 | } |
4130 | 0 | case SystemZ::LLIHH: |
4131 | 0 | case SystemZ::LLIHL: |
4132 | 0 | case SystemZ::LLILH: |
4133 | 0 | case SystemZ::LLILL: |
4134 | 0 | case SystemZ::TMHH: |
4135 | 0 | case SystemZ::TMHL: |
4136 | 0 | case SystemZ::TMLH: |
4137 | 0 | case SystemZ::TMLL: { |
4138 | | // op: R1 |
4139 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4140 | 0 | op &= UINT64_C(15); |
4141 | 0 | op <<= 20; |
4142 | 0 | Value |= op; |
4143 | | // op: I2 |
4144 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 1, Fixups, STI); |
4145 | 0 | op &= UINT64_C(65535); |
4146 | 0 | Value |= op; |
4147 | 0 | break; |
4148 | 0 | } |
4149 | 0 | case SystemZ::IIHH: |
4150 | 0 | case SystemZ::IIHL: |
4151 | 0 | case SystemZ::IILH: |
4152 | 0 | case SystemZ::IILL: |
4153 | 0 | case SystemZ::NIHH: |
4154 | 0 | case SystemZ::NIHL: |
4155 | 0 | case SystemZ::NILH: |
4156 | 0 | case SystemZ::NILL: |
4157 | 0 | case SystemZ::OIHH: |
4158 | 0 | case SystemZ::OIHL: |
4159 | 0 | case SystemZ::OILH: |
4160 | 0 | case SystemZ::OILL: { |
4161 | | // op: R1 |
4162 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4163 | 0 | op &= UINT64_C(15); |
4164 | 0 | op <<= 20; |
4165 | 0 | Value |= op; |
4166 | | // op: I2 |
4167 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 2, Fixups, STI); |
4168 | 0 | op &= UINT64_C(65535); |
4169 | 0 | Value |= op; |
4170 | 0 | break; |
4171 | 0 | } |
4172 | 0 | case SystemZ::CLM: |
4173 | 0 | case SystemZ::STCM: { |
4174 | | // op: R1 |
4175 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4176 | 0 | op &= UINT64_C(15); |
4177 | 0 | op <<= 20; |
4178 | 0 | Value |= op; |
4179 | | // op: M3 |
4180 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 1, Fixups, STI); |
4181 | 0 | op &= UINT64_C(15); |
4182 | 0 | op <<= 16; |
4183 | 0 | Value |= op; |
4184 | | // op: B2 |
4185 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4186 | 0 | op &= UINT64_C(15); |
4187 | 0 | op <<= 12; |
4188 | 0 | Value |= op; |
4189 | | // op: D2 |
4190 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4191 | 0 | op &= UINT64_C(4095); |
4192 | 0 | Value |= op; |
4193 | 0 | break; |
4194 | 0 | } |
4195 | 0 | case SystemZ::ICM: { |
4196 | | // op: R1 |
4197 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4198 | 0 | op &= UINT64_C(15); |
4199 | 0 | op <<= 20; |
4200 | 0 | Value |= op; |
4201 | | // op: M3 |
4202 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
4203 | 0 | op &= UINT64_C(15); |
4204 | 0 | op <<= 16; |
4205 | 0 | Value |= op; |
4206 | | // op: B2 |
4207 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4208 | 0 | op &= UINT64_C(15); |
4209 | 0 | op <<= 12; |
4210 | 0 | Value |= op; |
4211 | | // op: D2 |
4212 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
4213 | 0 | op &= UINT64_C(4095); |
4214 | 0 | Value |= op; |
4215 | 0 | break; |
4216 | 0 | } |
4217 | 0 | case SystemZ::DIAG: |
4218 | 0 | case SystemZ::LAM: |
4219 | 0 | case SystemZ::LCTL: |
4220 | 0 | case SystemZ::LM: |
4221 | 0 | case SystemZ::SIGP: |
4222 | 0 | case SystemZ::STAM: |
4223 | 0 | case SystemZ::STCTL: |
4224 | 0 | case SystemZ::STM: |
4225 | 0 | case SystemZ::TRACE: { |
4226 | | // op: R1 |
4227 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4228 | 0 | op &= UINT64_C(15); |
4229 | 0 | op <<= 20; |
4230 | 0 | Value |= op; |
4231 | | // op: R3 |
4232 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4233 | 0 | op &= UINT64_C(15); |
4234 | 0 | op <<= 16; |
4235 | 0 | Value |= op; |
4236 | | // op: B2 |
4237 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4238 | 0 | op &= UINT64_C(15); |
4239 | 0 | op <<= 12; |
4240 | 0 | Value |= op; |
4241 | | // op: D2 |
4242 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4243 | 0 | op &= UINT64_C(4095); |
4244 | 0 | Value |= op; |
4245 | 0 | break; |
4246 | 0 | } |
4247 | 0 | case SystemZ::CLCLE: |
4248 | 0 | case SystemZ::MVCLE: { |
4249 | | // op: R1 |
4250 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4251 | 0 | op &= UINT64_C(15); |
4252 | 0 | op <<= 20; |
4253 | 0 | Value |= op; |
4254 | | // op: R3 |
4255 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4256 | 0 | op &= UINT64_C(15); |
4257 | 0 | op <<= 16; |
4258 | 0 | Value |= op; |
4259 | | // op: B2 |
4260 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4261 | 0 | op &= UINT64_C(15); |
4262 | 0 | op <<= 12; |
4263 | 0 | Value |= op; |
4264 | | // op: D2 |
4265 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 5, Fixups, STI); |
4266 | 0 | op &= UINT64_C(4095); |
4267 | 0 | Value |= op; |
4268 | 0 | break; |
4269 | 0 | } |
4270 | 0 | case SystemZ::BXH: |
4271 | 0 | case SystemZ::BXLE: |
4272 | 0 | case SystemZ::CDS: |
4273 | 0 | case SystemZ::CS: { |
4274 | | // op: R1 |
4275 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4276 | 0 | op &= UINT64_C(15); |
4277 | 0 | op <<= 20; |
4278 | 0 | Value |= op; |
4279 | | // op: R3 |
4280 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4281 | 0 | op &= UINT64_C(15); |
4282 | 0 | op <<= 16; |
4283 | 0 | Value |= op; |
4284 | | // op: B2 |
4285 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4286 | 0 | op &= UINT64_C(15); |
4287 | 0 | op <<= 12; |
4288 | 0 | Value |= op; |
4289 | | // op: D2 |
4290 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
4291 | 0 | op &= UINT64_C(4095); |
4292 | 0 | Value |= op; |
4293 | 0 | break; |
4294 | 0 | } |
4295 | 0 | case SystemZ::BRXH: |
4296 | 0 | case SystemZ::BRXLE: { |
4297 | | // op: R1 |
4298 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4299 | 0 | op &= UINT64_C(15); |
4300 | 0 | op <<= 20; |
4301 | 0 | Value |= op; |
4302 | | // op: R3 |
4303 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4304 | 0 | op &= UINT64_C(15); |
4305 | 0 | op <<= 16; |
4306 | 0 | Value |= op; |
4307 | | // op: RI2 |
4308 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
4309 | 0 | op &= UINT64_C(65535); |
4310 | 0 | Value |= op; |
4311 | 0 | break; |
4312 | 0 | } |
4313 | 0 | case SystemZ::BRCT: |
4314 | 0 | case SystemZ::BRCTG: { |
4315 | | // op: R1 |
4316 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4317 | 0 | op &= UINT64_C(15); |
4318 | 0 | op <<= 20; |
4319 | 0 | Value |= op; |
4320 | | // op: RI2 |
4321 | 0 | op = getPC16DBLEncoding(MI, 2, Fixups, STI); |
4322 | 0 | op &= UINT64_C(65535); |
4323 | 0 | Value |= op; |
4324 | 0 | break; |
4325 | 0 | } |
4326 | 0 | case SystemZ::BRAS: { |
4327 | | // op: R1 |
4328 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4329 | 0 | op &= UINT64_C(15); |
4330 | 0 | op <<= 20; |
4331 | 0 | Value |= op; |
4332 | | // op: RI2 |
4333 | 0 | op = getPC16DBLTLSEncoding(MI, 1, Fixups, STI); |
4334 | 0 | op &= UINT64_C(65535); |
4335 | 0 | Value |= op; |
4336 | 0 | break; |
4337 | 0 | } |
4338 | 0 | case SystemZ::BAL: |
4339 | 0 | case SystemZ::BAS: |
4340 | 0 | case SystemZ::C: |
4341 | 0 | case SystemZ::CD: |
4342 | 0 | case SystemZ::CE: |
4343 | 0 | case SystemZ::CH: |
4344 | 0 | case SystemZ::CL: |
4345 | 0 | case SystemZ::CVD: |
4346 | 0 | case SystemZ::EX: |
4347 | 0 | case SystemZ::L: |
4348 | 0 | case SystemZ::LA: |
4349 | 0 | case SystemZ::LAE: |
4350 | 0 | case SystemZ::LD: |
4351 | 0 | case SystemZ::LE: |
4352 | 0 | case SystemZ::LH: |
4353 | 0 | case SystemZ::LRA: |
4354 | 0 | case SystemZ::ST: |
4355 | 0 | case SystemZ::STC: |
4356 | 0 | case SystemZ::STD: |
4357 | 0 | case SystemZ::STE: |
4358 | 0 | case SystemZ::STH: { |
4359 | | // op: R1 |
4360 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4361 | 0 | op &= UINT64_C(15); |
4362 | 0 | op <<= 20; |
4363 | 0 | Value |= op; |
4364 | | // op: X2 |
4365 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4366 | 0 | op &= UINT64_C(15); |
4367 | 0 | op <<= 16; |
4368 | 0 | Value |= op; |
4369 | | // op: B2 |
4370 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4371 | 0 | op &= UINT64_C(15); |
4372 | 0 | op <<= 12; |
4373 | 0 | Value |= op; |
4374 | | // op: D2 |
4375 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
4376 | 0 | op &= UINT64_C(4095); |
4377 | 0 | Value |= op; |
4378 | 0 | break; |
4379 | 0 | } |
4380 | 0 | case SystemZ::A: |
4381 | 0 | case SystemZ::AD: |
4382 | 0 | case SystemZ::AE: |
4383 | 0 | case SystemZ::AH: |
4384 | 0 | case SystemZ::AL: |
4385 | 0 | case SystemZ::AU: |
4386 | 0 | case SystemZ::AW: |
4387 | 0 | case SystemZ::BCT: |
4388 | 0 | case SystemZ::CVB: |
4389 | 0 | case SystemZ::D: |
4390 | 0 | case SystemZ::DD: |
4391 | 0 | case SystemZ::DE: |
4392 | 0 | case SystemZ::IC: |
4393 | 0 | case SystemZ::IC32: |
4394 | 0 | case SystemZ::M: |
4395 | 0 | case SystemZ::MD: |
4396 | 0 | case SystemZ::MDE: |
4397 | 0 | case SystemZ::ME: |
4398 | 0 | case SystemZ::MH: |
4399 | 0 | case SystemZ::MS: |
4400 | 0 | case SystemZ::MXD: |
4401 | 0 | case SystemZ::N: |
4402 | 0 | case SystemZ::O: |
4403 | 0 | case SystemZ::S: |
4404 | 0 | case SystemZ::SD: |
4405 | 0 | case SystemZ::SE: |
4406 | 0 | case SystemZ::SH: |
4407 | 0 | case SystemZ::SL: |
4408 | 0 | case SystemZ::SU: |
4409 | 0 | case SystemZ::SW: |
4410 | 0 | case SystemZ::X: { |
4411 | | // op: R1 |
4412 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4413 | 0 | op &= UINT64_C(15); |
4414 | 0 | op <<= 20; |
4415 | 0 | Value |= op; |
4416 | | // op: X2 |
4417 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4418 | 0 | op &= UINT64_C(15); |
4419 | 0 | op <<= 16; |
4420 | 0 | Value |= op; |
4421 | | // op: B2 |
4422 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4423 | 0 | op &= UINT64_C(15); |
4424 | 0 | op <<= 12; |
4425 | 0 | Value |= op; |
4426 | | // op: D2 |
4427 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4428 | 0 | op &= UINT64_C(4095); |
4429 | 0 | Value |= op; |
4430 | 0 | break; |
4431 | 0 | } |
4432 | 0 | case SystemZ::CLGTAsmE: |
4433 | 0 | case SystemZ::CLGTAsmH: |
4434 | 0 | case SystemZ::CLGTAsmHE: |
4435 | 0 | case SystemZ::CLGTAsmL: |
4436 | 0 | case SystemZ::CLGTAsmLE: |
4437 | 0 | case SystemZ::CLGTAsmLH: |
4438 | 0 | case SystemZ::CLGTAsmNE: |
4439 | 0 | case SystemZ::CLGTAsmNH: |
4440 | 0 | case SystemZ::CLGTAsmNHE: |
4441 | 0 | case SystemZ::CLGTAsmNL: |
4442 | 0 | case SystemZ::CLGTAsmNLE: |
4443 | 0 | case SystemZ::CLGTAsmNLH: |
4444 | 0 | case SystemZ::CLTAsmE: |
4445 | 0 | case SystemZ::CLTAsmH: |
4446 | 0 | case SystemZ::CLTAsmHE: |
4447 | 0 | case SystemZ::CLTAsmL: |
4448 | 0 | case SystemZ::CLTAsmLE: |
4449 | 0 | case SystemZ::CLTAsmLH: |
4450 | 0 | case SystemZ::CLTAsmNE: |
4451 | 0 | case SystemZ::CLTAsmNH: |
4452 | 0 | case SystemZ::CLTAsmNHE: |
4453 | 0 | case SystemZ::CLTAsmNL: |
4454 | 0 | case SystemZ::CLTAsmNLE: |
4455 | 0 | case SystemZ::CLTAsmNLH: |
4456 | 0 | case SystemZ::STOCAsmE: |
4457 | 0 | case SystemZ::STOCAsmH: |
4458 | 0 | case SystemZ::STOCAsmHE: |
4459 | 0 | case SystemZ::STOCAsmL: |
4460 | 0 | case SystemZ::STOCAsmLE: |
4461 | 0 | case SystemZ::STOCAsmLH: |
4462 | 0 | case SystemZ::STOCAsmM: |
4463 | 0 | case SystemZ::STOCAsmNE: |
4464 | 0 | case SystemZ::STOCAsmNH: |
4465 | 0 | case SystemZ::STOCAsmNHE: |
4466 | 0 | case SystemZ::STOCAsmNL: |
4467 | 0 | case SystemZ::STOCAsmNLE: |
4468 | 0 | case SystemZ::STOCAsmNLH: |
4469 | 0 | case SystemZ::STOCAsmNM: |
4470 | 0 | case SystemZ::STOCAsmNO: |
4471 | 0 | case SystemZ::STOCAsmNP: |
4472 | 0 | case SystemZ::STOCAsmNZ: |
4473 | 0 | case SystemZ::STOCAsmO: |
4474 | 0 | case SystemZ::STOCAsmP: |
4475 | 0 | case SystemZ::STOCAsmZ: |
4476 | 0 | case SystemZ::STOCFHAsmE: |
4477 | 0 | case SystemZ::STOCFHAsmH: |
4478 | 0 | case SystemZ::STOCFHAsmHE: |
4479 | 0 | case SystemZ::STOCFHAsmL: |
4480 | 0 | case SystemZ::STOCFHAsmLE: |
4481 | 0 | case SystemZ::STOCFHAsmLH: |
4482 | 0 | case SystemZ::STOCFHAsmM: |
4483 | 0 | case SystemZ::STOCFHAsmNE: |
4484 | 0 | case SystemZ::STOCFHAsmNH: |
4485 | 0 | case SystemZ::STOCFHAsmNHE: |
4486 | 0 | case SystemZ::STOCFHAsmNL: |
4487 | 0 | case SystemZ::STOCFHAsmNLE: |
4488 | 0 | case SystemZ::STOCFHAsmNLH: |
4489 | 0 | case SystemZ::STOCFHAsmNM: |
4490 | 0 | case SystemZ::STOCFHAsmNO: |
4491 | 0 | case SystemZ::STOCFHAsmNP: |
4492 | 0 | case SystemZ::STOCFHAsmNZ: |
4493 | 0 | case SystemZ::STOCFHAsmO: |
4494 | 0 | case SystemZ::STOCFHAsmP: |
4495 | 0 | case SystemZ::STOCFHAsmZ: |
4496 | 0 | case SystemZ::STOCGAsmE: |
4497 | 0 | case SystemZ::STOCGAsmH: |
4498 | 0 | case SystemZ::STOCGAsmHE: |
4499 | 0 | case SystemZ::STOCGAsmL: |
4500 | 0 | case SystemZ::STOCGAsmLE: |
4501 | 0 | case SystemZ::STOCGAsmLH: |
4502 | 0 | case SystemZ::STOCGAsmM: |
4503 | 0 | case SystemZ::STOCGAsmNE: |
4504 | 0 | case SystemZ::STOCGAsmNH: |
4505 | 0 | case SystemZ::STOCGAsmNHE: |
4506 | 0 | case SystemZ::STOCGAsmNL: |
4507 | 0 | case SystemZ::STOCGAsmNLE: |
4508 | 0 | case SystemZ::STOCGAsmNLH: |
4509 | 0 | case SystemZ::STOCGAsmNM: |
4510 | 0 | case SystemZ::STOCGAsmNO: |
4511 | 0 | case SystemZ::STOCGAsmNP: |
4512 | 0 | case SystemZ::STOCGAsmNZ: |
4513 | 0 | case SystemZ::STOCGAsmO: |
4514 | 0 | case SystemZ::STOCGAsmP: |
4515 | 0 | case SystemZ::STOCGAsmZ: { |
4516 | | // op: R1 |
4517 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4518 | 0 | op &= UINT64_C(15); |
4519 | 0 | op <<= 36; |
4520 | 0 | Value |= op; |
4521 | | // op: B2 |
4522 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4523 | 0 | op &= UINT64_C(15); |
4524 | 0 | op <<= 28; |
4525 | 0 | Value |= op; |
4526 | | // op: D2 |
4527 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
4528 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
4529 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
4530 | 0 | break; |
4531 | 0 | } |
4532 | 0 | case SystemZ::PLO: { |
4533 | | // op: R1 |
4534 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4535 | 0 | op &= UINT64_C(15); |
4536 | 0 | op <<= 36; |
4537 | 0 | Value |= op; |
4538 | | // op: B2 |
4539 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4540 | 0 | op &= UINT64_C(15); |
4541 | 0 | op <<= 28; |
4542 | 0 | Value |= op; |
4543 | | // op: D2 |
4544 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
4545 | 0 | op &= UINT64_C(4095); |
4546 | 0 | op <<= 16; |
4547 | 0 | Value |= op; |
4548 | | // op: R3 |
4549 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4550 | 0 | op &= UINT64_C(15); |
4551 | 0 | op <<= 32; |
4552 | 0 | Value |= op; |
4553 | | // op: B4 |
4554 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4555 | 0 | op &= UINT64_C(15); |
4556 | 0 | op <<= 12; |
4557 | 0 | Value |= op; |
4558 | | // op: D4 |
4559 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 5, Fixups, STI); |
4560 | 0 | op &= UINT64_C(4095); |
4561 | 0 | Value |= op; |
4562 | 0 | break; |
4563 | 0 | } |
4564 | 0 | case SystemZ::LOCAsmE: |
4565 | 0 | case SystemZ::LOCAsmH: |
4566 | 0 | case SystemZ::LOCAsmHE: |
4567 | 0 | case SystemZ::LOCAsmL: |
4568 | 0 | case SystemZ::LOCAsmLE: |
4569 | 0 | case SystemZ::LOCAsmLH: |
4570 | 0 | case SystemZ::LOCAsmM: |
4571 | 0 | case SystemZ::LOCAsmNE: |
4572 | 0 | case SystemZ::LOCAsmNH: |
4573 | 0 | case SystemZ::LOCAsmNHE: |
4574 | 0 | case SystemZ::LOCAsmNL: |
4575 | 0 | case SystemZ::LOCAsmNLE: |
4576 | 0 | case SystemZ::LOCAsmNLH: |
4577 | 0 | case SystemZ::LOCAsmNM: |
4578 | 0 | case SystemZ::LOCAsmNO: |
4579 | 0 | case SystemZ::LOCAsmNP: |
4580 | 0 | case SystemZ::LOCAsmNZ: |
4581 | 0 | case SystemZ::LOCAsmO: |
4582 | 0 | case SystemZ::LOCAsmP: |
4583 | 0 | case SystemZ::LOCAsmZ: |
4584 | 0 | case SystemZ::LOCFHAsmE: |
4585 | 0 | case SystemZ::LOCFHAsmH: |
4586 | 0 | case SystemZ::LOCFHAsmHE: |
4587 | 0 | case SystemZ::LOCFHAsmL: |
4588 | 0 | case SystemZ::LOCFHAsmLE: |
4589 | 0 | case SystemZ::LOCFHAsmLH: |
4590 | 0 | case SystemZ::LOCFHAsmM: |
4591 | 0 | case SystemZ::LOCFHAsmNE: |
4592 | 0 | case SystemZ::LOCFHAsmNH: |
4593 | 0 | case SystemZ::LOCFHAsmNHE: |
4594 | 0 | case SystemZ::LOCFHAsmNL: |
4595 | 0 | case SystemZ::LOCFHAsmNLE: |
4596 | 0 | case SystemZ::LOCFHAsmNLH: |
4597 | 0 | case SystemZ::LOCFHAsmNM: |
4598 | 0 | case SystemZ::LOCFHAsmNO: |
4599 | 0 | case SystemZ::LOCFHAsmNP: |
4600 | 0 | case SystemZ::LOCFHAsmNZ: |
4601 | 0 | case SystemZ::LOCFHAsmO: |
4602 | 0 | case SystemZ::LOCFHAsmP: |
4603 | 0 | case SystemZ::LOCFHAsmZ: |
4604 | 0 | case SystemZ::LOCGAsmE: |
4605 | 0 | case SystemZ::LOCGAsmH: |
4606 | 0 | case SystemZ::LOCGAsmHE: |
4607 | 0 | case SystemZ::LOCGAsmL: |
4608 | 0 | case SystemZ::LOCGAsmLE: |
4609 | 0 | case SystemZ::LOCGAsmLH: |
4610 | 0 | case SystemZ::LOCGAsmM: |
4611 | 0 | case SystemZ::LOCGAsmNE: |
4612 | 0 | case SystemZ::LOCGAsmNH: |
4613 | 0 | case SystemZ::LOCGAsmNHE: |
4614 | 0 | case SystemZ::LOCGAsmNL: |
4615 | 0 | case SystemZ::LOCGAsmNLE: |
4616 | 0 | case SystemZ::LOCGAsmNLH: |
4617 | 0 | case SystemZ::LOCGAsmNM: |
4618 | 0 | case SystemZ::LOCGAsmNO: |
4619 | 0 | case SystemZ::LOCGAsmNP: |
4620 | 0 | case SystemZ::LOCGAsmNZ: |
4621 | 0 | case SystemZ::LOCGAsmO: |
4622 | 0 | case SystemZ::LOCGAsmP: |
4623 | 0 | case SystemZ::LOCGAsmZ: { |
4624 | | // op: R1 |
4625 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4626 | 0 | op &= UINT64_C(15); |
4627 | 0 | op <<= 36; |
4628 | 0 | Value |= op; |
4629 | | // op: B2 |
4630 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4631 | 0 | op &= UINT64_C(15); |
4632 | 0 | op <<= 28; |
4633 | 0 | Value |= op; |
4634 | | // op: D2 |
4635 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
4636 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
4637 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
4638 | 0 | break; |
4639 | 0 | } |
4640 | 0 | case SystemZ::LMD: { |
4641 | | // op: R1 |
4642 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4643 | 0 | op &= UINT64_C(15); |
4644 | 0 | op <<= 36; |
4645 | 0 | Value |= op; |
4646 | | // op: B2 |
4647 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4648 | 0 | op &= UINT64_C(15); |
4649 | 0 | op <<= 28; |
4650 | 0 | Value |= op; |
4651 | | // op: D2 |
4652 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4653 | 0 | op &= UINT64_C(4095); |
4654 | 0 | op <<= 16; |
4655 | 0 | Value |= op; |
4656 | | // op: R3 |
4657 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4658 | 0 | op &= UINT64_C(15); |
4659 | 0 | op <<= 32; |
4660 | 0 | Value |= op; |
4661 | | // op: B4 |
4662 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4663 | 0 | op &= UINT64_C(15); |
4664 | 0 | op <<= 12; |
4665 | 0 | Value |= op; |
4666 | | // op: D4 |
4667 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 5, Fixups, STI); |
4668 | 0 | op &= UINT64_C(4095); |
4669 | 0 | Value |= op; |
4670 | 0 | break; |
4671 | 0 | } |
4672 | 0 | case SystemZ::VLGVB: |
4673 | 0 | case SystemZ::VLGVF: |
4674 | 0 | case SystemZ::VLGVG: |
4675 | 0 | case SystemZ::VLGVH: { |
4676 | | // op: R1 |
4677 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4678 | 0 | op &= UINT64_C(15); |
4679 | 0 | op <<= 36; |
4680 | 0 | Value |= op; |
4681 | | // op: B2 |
4682 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4683 | 0 | op &= UINT64_C(15); |
4684 | 0 | op <<= 28; |
4685 | 0 | Value |= op; |
4686 | | // op: D2 |
4687 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4688 | 0 | op &= UINT64_C(4095); |
4689 | 0 | op <<= 16; |
4690 | 0 | Value |= op; |
4691 | | // op: V3 |
4692 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4693 | 0 | Value |= (op & UINT64_C(15)) << 32; |
4694 | 0 | Value |= (op & UINT64_C(16)) << 6; |
4695 | 0 | break; |
4696 | 0 | } |
4697 | 0 | case SystemZ::VLGV: { |
4698 | | // op: R1 |
4699 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4700 | 0 | op &= UINT64_C(15); |
4701 | 0 | op <<= 36; |
4702 | 0 | Value |= op; |
4703 | | // op: B2 |
4704 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4705 | 0 | op &= UINT64_C(15); |
4706 | 0 | op <<= 28; |
4707 | 0 | Value |= op; |
4708 | | // op: D2 |
4709 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4710 | 0 | op &= UINT64_C(4095); |
4711 | 0 | op <<= 16; |
4712 | 0 | Value |= op; |
4713 | | // op: V3 |
4714 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4715 | 0 | Value |= (op & UINT64_C(15)) << 32; |
4716 | 0 | Value |= (op & UINT64_C(16)) << 6; |
4717 | | // op: M4 |
4718 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
4719 | 0 | op &= UINT64_C(15); |
4720 | 0 | op <<= 12; |
4721 | 0 | Value |= op; |
4722 | 0 | break; |
4723 | 0 | } |
4724 | 0 | case SystemZ::CGITAsmE: |
4725 | 0 | case SystemZ::CGITAsmH: |
4726 | 0 | case SystemZ::CGITAsmHE: |
4727 | 0 | case SystemZ::CGITAsmL: |
4728 | 0 | case SystemZ::CGITAsmLE: |
4729 | 0 | case SystemZ::CGITAsmLH: |
4730 | 0 | case SystemZ::CGITAsmNE: |
4731 | 0 | case SystemZ::CGITAsmNH: |
4732 | 0 | case SystemZ::CGITAsmNHE: |
4733 | 0 | case SystemZ::CGITAsmNL: |
4734 | 0 | case SystemZ::CGITAsmNLE: |
4735 | 0 | case SystemZ::CGITAsmNLH: |
4736 | 0 | case SystemZ::CITAsmE: |
4737 | 0 | case SystemZ::CITAsmH: |
4738 | 0 | case SystemZ::CITAsmHE: |
4739 | 0 | case SystemZ::CITAsmL: |
4740 | 0 | case SystemZ::CITAsmLE: |
4741 | 0 | case SystemZ::CITAsmLH: |
4742 | 0 | case SystemZ::CITAsmNE: |
4743 | 0 | case SystemZ::CITAsmNH: |
4744 | 0 | case SystemZ::CITAsmNHE: |
4745 | 0 | case SystemZ::CITAsmNL: |
4746 | 0 | case SystemZ::CITAsmNLE: |
4747 | 0 | case SystemZ::CITAsmNLH: { |
4748 | | // op: R1 |
4749 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4750 | 0 | op &= UINT64_C(15); |
4751 | 0 | op <<= 36; |
4752 | 0 | Value |= op; |
4753 | | // op: I2 |
4754 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 1, Fixups, STI); |
4755 | 0 | op &= UINT64_C(65535); |
4756 | 0 | op <<= 16; |
4757 | 0 | Value |= op; |
4758 | 0 | break; |
4759 | 0 | } |
4760 | 0 | case SystemZ::CGITAsm: |
4761 | 0 | case SystemZ::CITAsm: { |
4762 | | // op: R1 |
4763 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4764 | 0 | op &= UINT64_C(15); |
4765 | 0 | op <<= 36; |
4766 | 0 | Value |= op; |
4767 | | // op: I2 |
4768 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 1, Fixups, STI); |
4769 | 0 | op &= UINT64_C(65535); |
4770 | 0 | op <<= 16; |
4771 | 0 | Value |= op; |
4772 | | // op: M3 |
4773 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
4774 | 0 | op &= UINT64_C(15); |
4775 | 0 | op <<= 12; |
4776 | 0 | Value |= op; |
4777 | 0 | break; |
4778 | 0 | } |
4779 | 0 | case SystemZ::CGIT: |
4780 | 0 | case SystemZ::CIT: { |
4781 | | // op: R1 |
4782 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4783 | 0 | op &= UINT64_C(15); |
4784 | 0 | op <<= 36; |
4785 | 0 | Value |= op; |
4786 | | // op: I2 |
4787 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 1, Fixups, STI); |
4788 | 0 | op &= UINT64_C(65535); |
4789 | 0 | op <<= 16; |
4790 | 0 | Value |= op; |
4791 | | // op: M3 |
4792 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4793 | 0 | op &= UINT64_C(15); |
4794 | 0 | op <<= 12; |
4795 | 0 | Value |= op; |
4796 | 0 | break; |
4797 | 0 | } |
4798 | 0 | case SystemZ::LOCGHIAsmE: |
4799 | 0 | case SystemZ::LOCGHIAsmH: |
4800 | 0 | case SystemZ::LOCGHIAsmHE: |
4801 | 0 | case SystemZ::LOCGHIAsmL: |
4802 | 0 | case SystemZ::LOCGHIAsmLE: |
4803 | 0 | case SystemZ::LOCGHIAsmLH: |
4804 | 0 | case SystemZ::LOCGHIAsmM: |
4805 | 0 | case SystemZ::LOCGHIAsmNE: |
4806 | 0 | case SystemZ::LOCGHIAsmNH: |
4807 | 0 | case SystemZ::LOCGHIAsmNHE: |
4808 | 0 | case SystemZ::LOCGHIAsmNL: |
4809 | 0 | case SystemZ::LOCGHIAsmNLE: |
4810 | 0 | case SystemZ::LOCGHIAsmNLH: |
4811 | 0 | case SystemZ::LOCGHIAsmNM: |
4812 | 0 | case SystemZ::LOCGHIAsmNO: |
4813 | 0 | case SystemZ::LOCGHIAsmNP: |
4814 | 0 | case SystemZ::LOCGHIAsmNZ: |
4815 | 0 | case SystemZ::LOCGHIAsmO: |
4816 | 0 | case SystemZ::LOCGHIAsmP: |
4817 | 0 | case SystemZ::LOCGHIAsmZ: |
4818 | 0 | case SystemZ::LOCHHIAsmE: |
4819 | 0 | case SystemZ::LOCHHIAsmH: |
4820 | 0 | case SystemZ::LOCHHIAsmHE: |
4821 | 0 | case SystemZ::LOCHHIAsmL: |
4822 | 0 | case SystemZ::LOCHHIAsmLE: |
4823 | 0 | case SystemZ::LOCHHIAsmLH: |
4824 | 0 | case SystemZ::LOCHHIAsmM: |
4825 | 0 | case SystemZ::LOCHHIAsmNE: |
4826 | 0 | case SystemZ::LOCHHIAsmNH: |
4827 | 0 | case SystemZ::LOCHHIAsmNHE: |
4828 | 0 | case SystemZ::LOCHHIAsmNL: |
4829 | 0 | case SystemZ::LOCHHIAsmNLE: |
4830 | 0 | case SystemZ::LOCHHIAsmNLH: |
4831 | 0 | case SystemZ::LOCHHIAsmNM: |
4832 | 0 | case SystemZ::LOCHHIAsmNO: |
4833 | 0 | case SystemZ::LOCHHIAsmNP: |
4834 | 0 | case SystemZ::LOCHHIAsmNZ: |
4835 | 0 | case SystemZ::LOCHHIAsmO: |
4836 | 0 | case SystemZ::LOCHHIAsmP: |
4837 | 0 | case SystemZ::LOCHHIAsmZ: |
4838 | 0 | case SystemZ::LOCHIAsmE: |
4839 | 0 | case SystemZ::LOCHIAsmH: |
4840 | 0 | case SystemZ::LOCHIAsmHE: |
4841 | 0 | case SystemZ::LOCHIAsmL: |
4842 | 0 | case SystemZ::LOCHIAsmLE: |
4843 | 0 | case SystemZ::LOCHIAsmLH: |
4844 | 0 | case SystemZ::LOCHIAsmM: |
4845 | 0 | case SystemZ::LOCHIAsmNE: |
4846 | 0 | case SystemZ::LOCHIAsmNH: |
4847 | 0 | case SystemZ::LOCHIAsmNHE: |
4848 | 0 | case SystemZ::LOCHIAsmNL: |
4849 | 0 | case SystemZ::LOCHIAsmNLE: |
4850 | 0 | case SystemZ::LOCHIAsmNLH: |
4851 | 0 | case SystemZ::LOCHIAsmNM: |
4852 | 0 | case SystemZ::LOCHIAsmNO: |
4853 | 0 | case SystemZ::LOCHIAsmNP: |
4854 | 0 | case SystemZ::LOCHIAsmNZ: |
4855 | 0 | case SystemZ::LOCHIAsmO: |
4856 | 0 | case SystemZ::LOCHIAsmP: |
4857 | 0 | case SystemZ::LOCHIAsmZ: { |
4858 | | // op: R1 |
4859 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4860 | 0 | op &= UINT64_C(15); |
4861 | 0 | op <<= 36; |
4862 | 0 | Value |= op; |
4863 | | // op: I2 |
4864 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
4865 | 0 | op &= UINT64_C(65535); |
4866 | 0 | op <<= 16; |
4867 | 0 | Value |= op; |
4868 | 0 | break; |
4869 | 0 | } |
4870 | 0 | case SystemZ::CFI: |
4871 | 0 | case SystemZ::CGFI: |
4872 | 0 | case SystemZ::CIH: |
4873 | 0 | case SystemZ::LGFI: { |
4874 | | // op: R1 |
4875 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4876 | 0 | op &= UINT64_C(15); |
4877 | 0 | op <<= 36; |
4878 | 0 | Value |= op; |
4879 | | // op: I2 |
4880 | 0 | op = getImmOpValue<SystemZ::FK_390_S32Imm>(MI, 1, Fixups, STI); |
4881 | 0 | op &= UINT64_C(4294967295); |
4882 | 0 | Value |= op; |
4883 | 0 | break; |
4884 | 0 | } |
4885 | 0 | case SystemZ::AFI: |
4886 | 0 | case SystemZ::AGFI: |
4887 | 0 | case SystemZ::AIH: |
4888 | 0 | case SystemZ::ALSIH: |
4889 | 0 | case SystemZ::ALSIHN: |
4890 | 0 | case SystemZ::MSFI: |
4891 | 0 | case SystemZ::MSGFI: { |
4892 | | // op: R1 |
4893 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4894 | 0 | op &= UINT64_C(15); |
4895 | 0 | op <<= 36; |
4896 | 0 | Value |= op; |
4897 | | // op: I2 |
4898 | 0 | op = getImmOpValue<SystemZ::FK_390_S32Imm>(MI, 2, Fixups, STI); |
4899 | 0 | op &= UINT64_C(4294967295); |
4900 | 0 | Value |= op; |
4901 | 0 | break; |
4902 | 0 | } |
4903 | 0 | case SystemZ::CGIBAsmE: |
4904 | 0 | case SystemZ::CGIBAsmH: |
4905 | 0 | case SystemZ::CGIBAsmHE: |
4906 | 0 | case SystemZ::CGIBAsmL: |
4907 | 0 | case SystemZ::CGIBAsmLE: |
4908 | 0 | case SystemZ::CGIBAsmLH: |
4909 | 0 | case SystemZ::CGIBAsmNE: |
4910 | 0 | case SystemZ::CGIBAsmNH: |
4911 | 0 | case SystemZ::CGIBAsmNHE: |
4912 | 0 | case SystemZ::CGIBAsmNL: |
4913 | 0 | case SystemZ::CGIBAsmNLE: |
4914 | 0 | case SystemZ::CGIBAsmNLH: |
4915 | 0 | case SystemZ::CIBAsmE: |
4916 | 0 | case SystemZ::CIBAsmH: |
4917 | 0 | case SystemZ::CIBAsmHE: |
4918 | 0 | case SystemZ::CIBAsmL: |
4919 | 0 | case SystemZ::CIBAsmLE: |
4920 | 0 | case SystemZ::CIBAsmLH: |
4921 | 0 | case SystemZ::CIBAsmNE: |
4922 | 0 | case SystemZ::CIBAsmNH: |
4923 | 0 | case SystemZ::CIBAsmNHE: |
4924 | 0 | case SystemZ::CIBAsmNL: |
4925 | 0 | case SystemZ::CIBAsmNLE: |
4926 | 0 | case SystemZ::CIBAsmNLH: { |
4927 | | // op: R1 |
4928 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4929 | 0 | op &= UINT64_C(15); |
4930 | 0 | op <<= 36; |
4931 | 0 | Value |= op; |
4932 | | // op: I2 |
4933 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 1, Fixups, STI); |
4934 | 0 | op &= UINT64_C(255); |
4935 | 0 | op <<= 8; |
4936 | 0 | Value |= op; |
4937 | | // op: B4 |
4938 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4939 | 0 | op &= UINT64_C(15); |
4940 | 0 | op <<= 28; |
4941 | 0 | Value |= op; |
4942 | | // op: D4 |
4943 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
4944 | 0 | op &= UINT64_C(4095); |
4945 | 0 | op <<= 16; |
4946 | 0 | Value |= op; |
4947 | 0 | break; |
4948 | 0 | } |
4949 | 0 | case SystemZ::CGIBAsm: |
4950 | 0 | case SystemZ::CIBAsm: { |
4951 | | // op: R1 |
4952 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4953 | 0 | op &= UINT64_C(15); |
4954 | 0 | op <<= 36; |
4955 | 0 | Value |= op; |
4956 | | // op: I2 |
4957 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 1, Fixups, STI); |
4958 | 0 | op &= UINT64_C(255); |
4959 | 0 | op <<= 8; |
4960 | 0 | Value |= op; |
4961 | | // op: M3 |
4962 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
4963 | 0 | op &= UINT64_C(15); |
4964 | 0 | op <<= 32; |
4965 | 0 | Value |= op; |
4966 | | // op: B4 |
4967 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4968 | 0 | op &= UINT64_C(15); |
4969 | 0 | op <<= 28; |
4970 | 0 | Value |= op; |
4971 | | // op: D4 |
4972 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
4973 | 0 | op &= UINT64_C(4095); |
4974 | 0 | op <<= 16; |
4975 | 0 | Value |= op; |
4976 | 0 | break; |
4977 | 0 | } |
4978 | 0 | case SystemZ::CGIJAsm: |
4979 | 0 | case SystemZ::CIJAsm: { |
4980 | | // op: R1 |
4981 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4982 | 0 | op &= UINT64_C(15); |
4983 | 0 | op <<= 36; |
4984 | 0 | Value |= op; |
4985 | | // op: I2 |
4986 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 1, Fixups, STI); |
4987 | 0 | op &= UINT64_C(255); |
4988 | 0 | op <<= 8; |
4989 | 0 | Value |= op; |
4990 | | // op: M3 |
4991 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
4992 | 0 | op &= UINT64_C(15); |
4993 | 0 | op <<= 32; |
4994 | 0 | Value |= op; |
4995 | | // op: RI4 |
4996 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
4997 | 0 | op &= UINT64_C(65535); |
4998 | 0 | op <<= 16; |
4999 | 0 | Value |= op; |
5000 | 0 | break; |
5001 | 0 | } |
5002 | 0 | case SystemZ::CGIB: |
5003 | 0 | case SystemZ::CIB: { |
5004 | | // op: R1 |
5005 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5006 | 0 | op &= UINT64_C(15); |
5007 | 0 | op <<= 36; |
5008 | 0 | Value |= op; |
5009 | | // op: I2 |
5010 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 1, Fixups, STI); |
5011 | 0 | op &= UINT64_C(255); |
5012 | 0 | op <<= 8; |
5013 | 0 | Value |= op; |
5014 | | // op: M3 |
5015 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5016 | 0 | op &= UINT64_C(15); |
5017 | 0 | op <<= 32; |
5018 | 0 | Value |= op; |
5019 | | // op: B4 |
5020 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5021 | 0 | op &= UINT64_C(15); |
5022 | 0 | op <<= 28; |
5023 | 0 | Value |= op; |
5024 | | // op: D4 |
5025 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
5026 | 0 | op &= UINT64_C(4095); |
5027 | 0 | op <<= 16; |
5028 | 0 | Value |= op; |
5029 | 0 | break; |
5030 | 0 | } |
5031 | 0 | case SystemZ::CGIJ: |
5032 | 0 | case SystemZ::CIJ: { |
5033 | | // op: R1 |
5034 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5035 | 0 | op &= UINT64_C(15); |
5036 | 0 | op <<= 36; |
5037 | 0 | Value |= op; |
5038 | | // op: I2 |
5039 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 1, Fixups, STI); |
5040 | 0 | op &= UINT64_C(255); |
5041 | 0 | op <<= 8; |
5042 | 0 | Value |= op; |
5043 | | // op: M3 |
5044 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5045 | 0 | op &= UINT64_C(15); |
5046 | 0 | op <<= 32; |
5047 | 0 | Value |= op; |
5048 | | // op: RI4 |
5049 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
5050 | 0 | op &= UINT64_C(65535); |
5051 | 0 | op <<= 16; |
5052 | 0 | Value |= op; |
5053 | 0 | break; |
5054 | 0 | } |
5055 | 0 | case SystemZ::CGIJAsmE: |
5056 | 0 | case SystemZ::CGIJAsmH: |
5057 | 0 | case SystemZ::CGIJAsmHE: |
5058 | 0 | case SystemZ::CGIJAsmL: |
5059 | 0 | case SystemZ::CGIJAsmLE: |
5060 | 0 | case SystemZ::CGIJAsmLH: |
5061 | 0 | case SystemZ::CGIJAsmNE: |
5062 | 0 | case SystemZ::CGIJAsmNH: |
5063 | 0 | case SystemZ::CGIJAsmNHE: |
5064 | 0 | case SystemZ::CGIJAsmNL: |
5065 | 0 | case SystemZ::CGIJAsmNLE: |
5066 | 0 | case SystemZ::CGIJAsmNLH: |
5067 | 0 | case SystemZ::CIJAsmE: |
5068 | 0 | case SystemZ::CIJAsmH: |
5069 | 0 | case SystemZ::CIJAsmHE: |
5070 | 0 | case SystemZ::CIJAsmL: |
5071 | 0 | case SystemZ::CIJAsmLE: |
5072 | 0 | case SystemZ::CIJAsmLH: |
5073 | 0 | case SystemZ::CIJAsmNE: |
5074 | 0 | case SystemZ::CIJAsmNH: |
5075 | 0 | case SystemZ::CIJAsmNHE: |
5076 | 0 | case SystemZ::CIJAsmNL: |
5077 | 0 | case SystemZ::CIJAsmNLE: |
5078 | 0 | case SystemZ::CIJAsmNLH: { |
5079 | | // op: R1 |
5080 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5081 | 0 | op &= UINT64_C(15); |
5082 | 0 | op <<= 36; |
5083 | 0 | Value |= op; |
5084 | | // op: I2 |
5085 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 1, Fixups, STI); |
5086 | 0 | op &= UINT64_C(255); |
5087 | 0 | op <<= 8; |
5088 | 0 | Value |= op; |
5089 | | // op: RI4 |
5090 | 0 | op = getPC16DBLEncoding(MI, 2, Fixups, STI); |
5091 | 0 | op &= UINT64_C(65535); |
5092 | 0 | op <<= 16; |
5093 | 0 | Value |= op; |
5094 | 0 | break; |
5095 | 0 | } |
5096 | 0 | case SystemZ::CLFITAsmE: |
5097 | 0 | case SystemZ::CLFITAsmH: |
5098 | 0 | case SystemZ::CLFITAsmHE: |
5099 | 0 | case SystemZ::CLFITAsmL: |
5100 | 0 | case SystemZ::CLFITAsmLE: |
5101 | 0 | case SystemZ::CLFITAsmLH: |
5102 | 0 | case SystemZ::CLFITAsmNE: |
5103 | 0 | case SystemZ::CLFITAsmNH: |
5104 | 0 | case SystemZ::CLFITAsmNHE: |
5105 | 0 | case SystemZ::CLFITAsmNL: |
5106 | 0 | case SystemZ::CLFITAsmNLE: |
5107 | 0 | case SystemZ::CLFITAsmNLH: |
5108 | 0 | case SystemZ::CLGITAsmE: |
5109 | 0 | case SystemZ::CLGITAsmH: |
5110 | 0 | case SystemZ::CLGITAsmHE: |
5111 | 0 | case SystemZ::CLGITAsmL: |
5112 | 0 | case SystemZ::CLGITAsmLE: |
5113 | 0 | case SystemZ::CLGITAsmLH: |
5114 | 0 | case SystemZ::CLGITAsmNE: |
5115 | 0 | case SystemZ::CLGITAsmNH: |
5116 | 0 | case SystemZ::CLGITAsmNHE: |
5117 | 0 | case SystemZ::CLGITAsmNL: |
5118 | 0 | case SystemZ::CLGITAsmNLE: |
5119 | 0 | case SystemZ::CLGITAsmNLH: { |
5120 | | // op: R1 |
5121 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5122 | 0 | op &= UINT64_C(15); |
5123 | 0 | op <<= 36; |
5124 | 0 | Value |= op; |
5125 | | // op: I2 |
5126 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 1, Fixups, STI); |
5127 | 0 | op &= UINT64_C(65535); |
5128 | 0 | op <<= 16; |
5129 | 0 | Value |= op; |
5130 | 0 | break; |
5131 | 0 | } |
5132 | 0 | case SystemZ::CLFITAsm: |
5133 | 0 | case SystemZ::CLGITAsm: { |
5134 | | // op: R1 |
5135 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5136 | 0 | op &= UINT64_C(15); |
5137 | 0 | op <<= 36; |
5138 | 0 | Value |= op; |
5139 | | // op: I2 |
5140 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 1, Fixups, STI); |
5141 | 0 | op &= UINT64_C(65535); |
5142 | 0 | op <<= 16; |
5143 | 0 | Value |= op; |
5144 | | // op: M3 |
5145 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
5146 | 0 | op &= UINT64_C(15); |
5147 | 0 | op <<= 12; |
5148 | 0 | Value |= op; |
5149 | 0 | break; |
5150 | 0 | } |
5151 | 0 | case SystemZ::CLFIT: |
5152 | 0 | case SystemZ::CLGIT: { |
5153 | | // op: R1 |
5154 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5155 | 0 | op &= UINT64_C(15); |
5156 | 0 | op <<= 36; |
5157 | 0 | Value |= op; |
5158 | | // op: I2 |
5159 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 1, Fixups, STI); |
5160 | 0 | op &= UINT64_C(65535); |
5161 | 0 | op <<= 16; |
5162 | 0 | Value |= op; |
5163 | | // op: M3 |
5164 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5165 | 0 | op &= UINT64_C(15); |
5166 | 0 | op <<= 12; |
5167 | 0 | Value |= op; |
5168 | 0 | break; |
5169 | 0 | } |
5170 | 0 | case SystemZ::CLFI: |
5171 | 0 | case SystemZ::CLGFI: |
5172 | 0 | case SystemZ::CLIH: |
5173 | 0 | case SystemZ::IIHF: |
5174 | 0 | case SystemZ::IILF: |
5175 | 0 | case SystemZ::LLIHF: |
5176 | 0 | case SystemZ::LLILF: { |
5177 | | // op: R1 |
5178 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5179 | 0 | op &= UINT64_C(15); |
5180 | 0 | op <<= 36; |
5181 | 0 | Value |= op; |
5182 | | // op: I2 |
5183 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 1, Fixups, STI); |
5184 | 0 | op &= UINT64_C(4294967295); |
5185 | 0 | Value |= op; |
5186 | 0 | break; |
5187 | 0 | } |
5188 | 0 | case SystemZ::ALFI: |
5189 | 0 | case SystemZ::ALGFI: |
5190 | 0 | case SystemZ::NIHF: |
5191 | 0 | case SystemZ::NILF: |
5192 | 0 | case SystemZ::OIHF: |
5193 | 0 | case SystemZ::OILF: |
5194 | 0 | case SystemZ::SLFI: |
5195 | 0 | case SystemZ::SLGFI: |
5196 | 0 | case SystemZ::XIHF: |
5197 | 0 | case SystemZ::XILF: { |
5198 | | // op: R1 |
5199 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5200 | 0 | op &= UINT64_C(15); |
5201 | 0 | op <<= 36; |
5202 | 0 | Value |= op; |
5203 | | // op: I2 |
5204 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 2, Fixups, STI); |
5205 | 0 | op &= UINT64_C(4294967295); |
5206 | 0 | Value |= op; |
5207 | 0 | break; |
5208 | 0 | } |
5209 | 0 | case SystemZ::CLGIBAsmE: |
5210 | 0 | case SystemZ::CLGIBAsmH: |
5211 | 0 | case SystemZ::CLGIBAsmHE: |
5212 | 0 | case SystemZ::CLGIBAsmL: |
5213 | 0 | case SystemZ::CLGIBAsmLE: |
5214 | 0 | case SystemZ::CLGIBAsmLH: |
5215 | 0 | case SystemZ::CLGIBAsmNE: |
5216 | 0 | case SystemZ::CLGIBAsmNH: |
5217 | 0 | case SystemZ::CLGIBAsmNHE: |
5218 | 0 | case SystemZ::CLGIBAsmNL: |
5219 | 0 | case SystemZ::CLGIBAsmNLE: |
5220 | 0 | case SystemZ::CLGIBAsmNLH: |
5221 | 0 | case SystemZ::CLIBAsmE: |
5222 | 0 | case SystemZ::CLIBAsmH: |
5223 | 0 | case SystemZ::CLIBAsmHE: |
5224 | 0 | case SystemZ::CLIBAsmL: |
5225 | 0 | case SystemZ::CLIBAsmLE: |
5226 | 0 | case SystemZ::CLIBAsmLH: |
5227 | 0 | case SystemZ::CLIBAsmNE: |
5228 | 0 | case SystemZ::CLIBAsmNH: |
5229 | 0 | case SystemZ::CLIBAsmNHE: |
5230 | 0 | case SystemZ::CLIBAsmNL: |
5231 | 0 | case SystemZ::CLIBAsmNLE: |
5232 | 0 | case SystemZ::CLIBAsmNLH: { |
5233 | | // op: R1 |
5234 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5235 | 0 | op &= UINT64_C(15); |
5236 | 0 | op <<= 36; |
5237 | 0 | Value |= op; |
5238 | | // op: I2 |
5239 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
5240 | 0 | op &= UINT64_C(255); |
5241 | 0 | op <<= 8; |
5242 | 0 | Value |= op; |
5243 | | // op: B4 |
5244 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5245 | 0 | op &= UINT64_C(15); |
5246 | 0 | op <<= 28; |
5247 | 0 | Value |= op; |
5248 | | // op: D4 |
5249 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
5250 | 0 | op &= UINT64_C(4095); |
5251 | 0 | op <<= 16; |
5252 | 0 | Value |= op; |
5253 | 0 | break; |
5254 | 0 | } |
5255 | 0 | case SystemZ::CLGIBAsm: |
5256 | 0 | case SystemZ::CLIBAsm: { |
5257 | | // op: R1 |
5258 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5259 | 0 | op &= UINT64_C(15); |
5260 | 0 | op <<= 36; |
5261 | 0 | Value |= op; |
5262 | | // op: I2 |
5263 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
5264 | 0 | op &= UINT64_C(255); |
5265 | 0 | op <<= 8; |
5266 | 0 | Value |= op; |
5267 | | // op: M3 |
5268 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
5269 | 0 | op &= UINT64_C(15); |
5270 | 0 | op <<= 32; |
5271 | 0 | Value |= op; |
5272 | | // op: B4 |
5273 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5274 | 0 | op &= UINT64_C(15); |
5275 | 0 | op <<= 28; |
5276 | 0 | Value |= op; |
5277 | | // op: D4 |
5278 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
5279 | 0 | op &= UINT64_C(4095); |
5280 | 0 | op <<= 16; |
5281 | 0 | Value |= op; |
5282 | 0 | break; |
5283 | 0 | } |
5284 | 0 | case SystemZ::CLGIJAsm: |
5285 | 0 | case SystemZ::CLIJAsm: { |
5286 | | // op: R1 |
5287 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5288 | 0 | op &= UINT64_C(15); |
5289 | 0 | op <<= 36; |
5290 | 0 | Value |= op; |
5291 | | // op: I2 |
5292 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
5293 | 0 | op &= UINT64_C(255); |
5294 | 0 | op <<= 8; |
5295 | 0 | Value |= op; |
5296 | | // op: M3 |
5297 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
5298 | 0 | op &= UINT64_C(15); |
5299 | 0 | op <<= 32; |
5300 | 0 | Value |= op; |
5301 | | // op: RI4 |
5302 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
5303 | 0 | op &= UINT64_C(65535); |
5304 | 0 | op <<= 16; |
5305 | 0 | Value |= op; |
5306 | 0 | break; |
5307 | 0 | } |
5308 | 0 | case SystemZ::CLGIB: |
5309 | 0 | case SystemZ::CLIB: { |
5310 | | // op: R1 |
5311 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5312 | 0 | op &= UINT64_C(15); |
5313 | 0 | op <<= 36; |
5314 | 0 | Value |= op; |
5315 | | // op: I2 |
5316 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
5317 | 0 | op &= UINT64_C(255); |
5318 | 0 | op <<= 8; |
5319 | 0 | Value |= op; |
5320 | | // op: M3 |
5321 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5322 | 0 | op &= UINT64_C(15); |
5323 | 0 | op <<= 32; |
5324 | 0 | Value |= op; |
5325 | | // op: B4 |
5326 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5327 | 0 | op &= UINT64_C(15); |
5328 | 0 | op <<= 28; |
5329 | 0 | Value |= op; |
5330 | | // op: D4 |
5331 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
5332 | 0 | op &= UINT64_C(4095); |
5333 | 0 | op <<= 16; |
5334 | 0 | Value |= op; |
5335 | 0 | break; |
5336 | 0 | } |
5337 | 0 | case SystemZ::CLGIJ: |
5338 | 0 | case SystemZ::CLIJ: { |
5339 | | // op: R1 |
5340 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5341 | 0 | op &= UINT64_C(15); |
5342 | 0 | op <<= 36; |
5343 | 0 | Value |= op; |
5344 | | // op: I2 |
5345 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
5346 | 0 | op &= UINT64_C(255); |
5347 | 0 | op <<= 8; |
5348 | 0 | Value |= op; |
5349 | | // op: M3 |
5350 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5351 | 0 | op &= UINT64_C(15); |
5352 | 0 | op <<= 32; |
5353 | 0 | Value |= op; |
5354 | | // op: RI4 |
5355 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
5356 | 0 | op &= UINT64_C(65535); |
5357 | 0 | op <<= 16; |
5358 | 0 | Value |= op; |
5359 | 0 | break; |
5360 | 0 | } |
5361 | 0 | case SystemZ::CLGIJAsmE: |
5362 | 0 | case SystemZ::CLGIJAsmH: |
5363 | 0 | case SystemZ::CLGIJAsmHE: |
5364 | 0 | case SystemZ::CLGIJAsmL: |
5365 | 0 | case SystemZ::CLGIJAsmLE: |
5366 | 0 | case SystemZ::CLGIJAsmLH: |
5367 | 0 | case SystemZ::CLGIJAsmNE: |
5368 | 0 | case SystemZ::CLGIJAsmNH: |
5369 | 0 | case SystemZ::CLGIJAsmNHE: |
5370 | 0 | case SystemZ::CLGIJAsmNL: |
5371 | 0 | case SystemZ::CLGIJAsmNLE: |
5372 | 0 | case SystemZ::CLGIJAsmNLH: |
5373 | 0 | case SystemZ::CLIJAsmE: |
5374 | 0 | case SystemZ::CLIJAsmH: |
5375 | 0 | case SystemZ::CLIJAsmHE: |
5376 | 0 | case SystemZ::CLIJAsmL: |
5377 | 0 | case SystemZ::CLIJAsmLE: |
5378 | 0 | case SystemZ::CLIJAsmLH: |
5379 | 0 | case SystemZ::CLIJAsmNE: |
5380 | 0 | case SystemZ::CLIJAsmNH: |
5381 | 0 | case SystemZ::CLIJAsmNHE: |
5382 | 0 | case SystemZ::CLIJAsmNL: |
5383 | 0 | case SystemZ::CLIJAsmNLE: |
5384 | 0 | case SystemZ::CLIJAsmNLH: { |
5385 | | // op: R1 |
5386 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5387 | 0 | op &= UINT64_C(15); |
5388 | 0 | op <<= 36; |
5389 | 0 | Value |= op; |
5390 | | // op: I2 |
5391 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
5392 | 0 | op &= UINT64_C(255); |
5393 | 0 | op <<= 8; |
5394 | 0 | Value |= op; |
5395 | | // op: RI4 |
5396 | 0 | op = getPC16DBLEncoding(MI, 2, Fixups, STI); |
5397 | 0 | op &= UINT64_C(65535); |
5398 | 0 | op <<= 16; |
5399 | 0 | Value |= op; |
5400 | 0 | break; |
5401 | 0 | } |
5402 | 0 | case SystemZ::CLMH: |
5403 | 0 | case SystemZ::CLMY: |
5404 | 0 | case SystemZ::STCMH: |
5405 | 0 | case SystemZ::STCMY: { |
5406 | | // op: R1 |
5407 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5408 | 0 | op &= UINT64_C(15); |
5409 | 0 | op <<= 36; |
5410 | 0 | Value |= op; |
5411 | | // op: M3 |
5412 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 1, Fixups, STI); |
5413 | 0 | op &= UINT64_C(15); |
5414 | 0 | op <<= 32; |
5415 | 0 | Value |= op; |
5416 | | // op: B2 |
5417 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5418 | 0 | op &= UINT64_C(15); |
5419 | 0 | op <<= 28; |
5420 | 0 | Value |= op; |
5421 | | // op: D2 |
5422 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
5423 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5424 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5425 | 0 | break; |
5426 | 0 | } |
5427 | 0 | case SystemZ::ICMH: |
5428 | 0 | case SystemZ::ICMY: { |
5429 | | // op: R1 |
5430 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5431 | 0 | op &= UINT64_C(15); |
5432 | 0 | op <<= 36; |
5433 | 0 | Value |= op; |
5434 | | // op: M3 |
5435 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
5436 | 0 | op &= UINT64_C(15); |
5437 | 0 | op <<= 32; |
5438 | 0 | Value |= op; |
5439 | | // op: B2 |
5440 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5441 | 0 | op &= UINT64_C(15); |
5442 | 0 | op <<= 28; |
5443 | 0 | Value |= op; |
5444 | | // op: D2 |
5445 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 4, Fixups, STI); |
5446 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5447 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5448 | 0 | break; |
5449 | 0 | } |
5450 | 0 | case SystemZ::CLGTAsm: |
5451 | 0 | case SystemZ::CLTAsm: |
5452 | 0 | case SystemZ::STOCAsm: |
5453 | 0 | case SystemZ::STOCFHAsm: |
5454 | 0 | case SystemZ::STOCGAsm: { |
5455 | | // op: R1 |
5456 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5457 | 0 | op &= UINT64_C(15); |
5458 | 0 | op <<= 36; |
5459 | 0 | Value |= op; |
5460 | | // op: M3 |
5461 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
5462 | 0 | op &= UINT64_C(15); |
5463 | 0 | op <<= 32; |
5464 | 0 | Value |= op; |
5465 | | // op: B2 |
5466 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5467 | 0 | op &= UINT64_C(15); |
5468 | 0 | op <<= 28; |
5469 | 0 | Value |= op; |
5470 | | // op: D2 |
5471 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
5472 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5473 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5474 | 0 | break; |
5475 | 0 | } |
5476 | 0 | case SystemZ::LOCGHIAsm: |
5477 | 0 | case SystemZ::LOCHHIAsm: |
5478 | 0 | case SystemZ::LOCHIAsm: { |
5479 | | // op: R1 |
5480 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5481 | 0 | op &= UINT64_C(15); |
5482 | 0 | op <<= 36; |
5483 | 0 | Value |= op; |
5484 | | // op: M3 |
5485 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
5486 | 0 | op &= UINT64_C(15); |
5487 | 0 | op <<= 32; |
5488 | 0 | Value |= op; |
5489 | | // op: I2 |
5490 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
5491 | 0 | op &= UINT64_C(65535); |
5492 | 0 | op <<= 16; |
5493 | 0 | Value |= op; |
5494 | 0 | break; |
5495 | 0 | } |
5496 | 0 | case SystemZ::LOCAsm: |
5497 | 0 | case SystemZ::LOCFHAsm: |
5498 | 0 | case SystemZ::LOCGAsm: { |
5499 | | // op: R1 |
5500 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5501 | 0 | op &= UINT64_C(15); |
5502 | 0 | op <<= 36; |
5503 | 0 | Value |= op; |
5504 | | // op: M3 |
5505 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
5506 | 0 | op &= UINT64_C(15); |
5507 | 0 | op <<= 32; |
5508 | 0 | Value |= op; |
5509 | | // op: B2 |
5510 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5511 | 0 | op &= UINT64_C(15); |
5512 | 0 | op <<= 28; |
5513 | 0 | Value |= op; |
5514 | | // op: D2 |
5515 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
5516 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5517 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5518 | 0 | break; |
5519 | 0 | } |
5520 | 0 | case SystemZ::CLGT: |
5521 | 0 | case SystemZ::CLT: { |
5522 | | // op: R1 |
5523 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5524 | 0 | op &= UINT64_C(15); |
5525 | 0 | op <<= 36; |
5526 | 0 | Value |= op; |
5527 | | // op: M3 |
5528 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5529 | 0 | op &= UINT64_C(15); |
5530 | 0 | op <<= 32; |
5531 | 0 | Value |= op; |
5532 | | // op: B2 |
5533 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5534 | 0 | op &= UINT64_C(15); |
5535 | 0 | op <<= 28; |
5536 | 0 | Value |= op; |
5537 | | // op: D2 |
5538 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
5539 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5540 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5541 | 0 | break; |
5542 | 0 | } |
5543 | 0 | case SystemZ::STOC: |
5544 | 0 | case SystemZ::STOCFH: |
5545 | 0 | case SystemZ::STOCG: { |
5546 | | // op: R1 |
5547 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5548 | 0 | op &= UINT64_C(15); |
5549 | 0 | op <<= 36; |
5550 | 0 | Value |= op; |
5551 | | // op: M3 |
5552 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5553 | 0 | op &= UINT64_C(15); |
5554 | 0 | op <<= 32; |
5555 | 0 | Value |= op; |
5556 | | // op: B2 |
5557 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5558 | 0 | op &= UINT64_C(15); |
5559 | 0 | op <<= 28; |
5560 | 0 | Value |= op; |
5561 | | // op: D2 |
5562 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
5563 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5564 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5565 | 0 | break; |
5566 | 0 | } |
5567 | 0 | case SystemZ::LOCGHI: |
5568 | 0 | case SystemZ::LOCHHI: |
5569 | 0 | case SystemZ::LOCHI: { |
5570 | | // op: R1 |
5571 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5572 | 0 | op &= UINT64_C(15); |
5573 | 0 | op <<= 36; |
5574 | 0 | Value |= op; |
5575 | | // op: M3 |
5576 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5577 | 0 | op &= UINT64_C(15); |
5578 | 0 | op <<= 32; |
5579 | 0 | Value |= op; |
5580 | | // op: I2 |
5581 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
5582 | 0 | op &= UINT64_C(65535); |
5583 | 0 | op <<= 16; |
5584 | 0 | Value |= op; |
5585 | 0 | break; |
5586 | 0 | } |
5587 | 0 | case SystemZ::LOC: |
5588 | 0 | case SystemZ::LOCFH: |
5589 | 0 | case SystemZ::LOCG: { |
5590 | | // op: R1 |
5591 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5592 | 0 | op &= UINT64_C(15); |
5593 | 0 | op <<= 36; |
5594 | 0 | Value |= op; |
5595 | | // op: M3 |
5596 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
5597 | 0 | op &= UINT64_C(15); |
5598 | 0 | op <<= 32; |
5599 | 0 | Value |= op; |
5600 | | // op: B2 |
5601 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5602 | 0 | op &= UINT64_C(15); |
5603 | 0 | op <<= 28; |
5604 | 0 | Value |= op; |
5605 | | // op: D2 |
5606 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
5607 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5608 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5609 | 0 | break; |
5610 | 0 | } |
5611 | 0 | case SystemZ::CGRBAsmE: |
5612 | 0 | case SystemZ::CGRBAsmH: |
5613 | 0 | case SystemZ::CGRBAsmHE: |
5614 | 0 | case SystemZ::CGRBAsmL: |
5615 | 0 | case SystemZ::CGRBAsmLE: |
5616 | 0 | case SystemZ::CGRBAsmLH: |
5617 | 0 | case SystemZ::CGRBAsmNE: |
5618 | 0 | case SystemZ::CGRBAsmNH: |
5619 | 0 | case SystemZ::CGRBAsmNHE: |
5620 | 0 | case SystemZ::CGRBAsmNL: |
5621 | 0 | case SystemZ::CGRBAsmNLE: |
5622 | 0 | case SystemZ::CGRBAsmNLH: |
5623 | 0 | case SystemZ::CLGRBAsmE: |
5624 | 0 | case SystemZ::CLGRBAsmH: |
5625 | 0 | case SystemZ::CLGRBAsmHE: |
5626 | 0 | case SystemZ::CLGRBAsmL: |
5627 | 0 | case SystemZ::CLGRBAsmLE: |
5628 | 0 | case SystemZ::CLGRBAsmLH: |
5629 | 0 | case SystemZ::CLGRBAsmNE: |
5630 | 0 | case SystemZ::CLGRBAsmNH: |
5631 | 0 | case SystemZ::CLGRBAsmNHE: |
5632 | 0 | case SystemZ::CLGRBAsmNL: |
5633 | 0 | case SystemZ::CLGRBAsmNLE: |
5634 | 0 | case SystemZ::CLGRBAsmNLH: |
5635 | 0 | case SystemZ::CLRBAsmE: |
5636 | 0 | case SystemZ::CLRBAsmH: |
5637 | 0 | case SystemZ::CLRBAsmHE: |
5638 | 0 | case SystemZ::CLRBAsmL: |
5639 | 0 | case SystemZ::CLRBAsmLE: |
5640 | 0 | case SystemZ::CLRBAsmLH: |
5641 | 0 | case SystemZ::CLRBAsmNE: |
5642 | 0 | case SystemZ::CLRBAsmNH: |
5643 | 0 | case SystemZ::CLRBAsmNHE: |
5644 | 0 | case SystemZ::CLRBAsmNL: |
5645 | 0 | case SystemZ::CLRBAsmNLE: |
5646 | 0 | case SystemZ::CLRBAsmNLH: |
5647 | 0 | case SystemZ::CRBAsmE: |
5648 | 0 | case SystemZ::CRBAsmH: |
5649 | 0 | case SystemZ::CRBAsmHE: |
5650 | 0 | case SystemZ::CRBAsmL: |
5651 | 0 | case SystemZ::CRBAsmLE: |
5652 | 0 | case SystemZ::CRBAsmLH: |
5653 | 0 | case SystemZ::CRBAsmNE: |
5654 | 0 | case SystemZ::CRBAsmNH: |
5655 | 0 | case SystemZ::CRBAsmNHE: |
5656 | 0 | case SystemZ::CRBAsmNL: |
5657 | 0 | case SystemZ::CRBAsmNLE: |
5658 | 0 | case SystemZ::CRBAsmNLH: { |
5659 | | // op: R1 |
5660 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5661 | 0 | op &= UINT64_C(15); |
5662 | 0 | op <<= 36; |
5663 | 0 | Value |= op; |
5664 | | // op: R2 |
5665 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5666 | 0 | op &= UINT64_C(15); |
5667 | 0 | op <<= 32; |
5668 | 0 | Value |= op; |
5669 | | // op: B4 |
5670 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5671 | 0 | op &= UINT64_C(15); |
5672 | 0 | op <<= 28; |
5673 | 0 | Value |= op; |
5674 | | // op: D4 |
5675 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
5676 | 0 | op &= UINT64_C(4095); |
5677 | 0 | op <<= 16; |
5678 | 0 | Value |= op; |
5679 | 0 | break; |
5680 | 0 | } |
5681 | 0 | case SystemZ::CGRBAsm: |
5682 | 0 | case SystemZ::CLGRBAsm: |
5683 | 0 | case SystemZ::CLRBAsm: |
5684 | 0 | case SystemZ::CRBAsm: { |
5685 | | // op: R1 |
5686 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5687 | 0 | op &= UINT64_C(15); |
5688 | 0 | op <<= 36; |
5689 | 0 | Value |= op; |
5690 | | // op: R2 |
5691 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5692 | 0 | op &= UINT64_C(15); |
5693 | 0 | op <<= 32; |
5694 | 0 | Value |= op; |
5695 | | // op: M3 |
5696 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
5697 | 0 | op &= UINT64_C(15); |
5698 | 0 | op <<= 12; |
5699 | 0 | Value |= op; |
5700 | | // op: B4 |
5701 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5702 | 0 | op &= UINT64_C(15); |
5703 | 0 | op <<= 28; |
5704 | 0 | Value |= op; |
5705 | | // op: D4 |
5706 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
5707 | 0 | op &= UINT64_C(4095); |
5708 | 0 | op <<= 16; |
5709 | 0 | Value |= op; |
5710 | 0 | break; |
5711 | 0 | } |
5712 | 0 | case SystemZ::CGRJAsm: |
5713 | 0 | case SystemZ::CLGRJAsm: |
5714 | 0 | case SystemZ::CLRJAsm: |
5715 | 0 | case SystemZ::CRJAsm: { |
5716 | | // op: R1 |
5717 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5718 | 0 | op &= UINT64_C(15); |
5719 | 0 | op <<= 36; |
5720 | 0 | Value |= op; |
5721 | | // op: R2 |
5722 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5723 | 0 | op &= UINT64_C(15); |
5724 | 0 | op <<= 32; |
5725 | 0 | Value |= op; |
5726 | | // op: M3 |
5727 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
5728 | 0 | op &= UINT64_C(15); |
5729 | 0 | op <<= 12; |
5730 | 0 | Value |= op; |
5731 | | // op: RI4 |
5732 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
5733 | 0 | op &= UINT64_C(65535); |
5734 | 0 | op <<= 16; |
5735 | 0 | Value |= op; |
5736 | 0 | break; |
5737 | 0 | } |
5738 | 0 | case SystemZ::CGRB: |
5739 | 0 | case SystemZ::CLGRB: |
5740 | 0 | case SystemZ::CLRB: |
5741 | 0 | case SystemZ::CRB: { |
5742 | | // op: R1 |
5743 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5744 | 0 | op &= UINT64_C(15); |
5745 | 0 | op <<= 36; |
5746 | 0 | Value |= op; |
5747 | | // op: R2 |
5748 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5749 | 0 | op &= UINT64_C(15); |
5750 | 0 | op <<= 32; |
5751 | 0 | Value |= op; |
5752 | | // op: M3 |
5753 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5754 | 0 | op &= UINT64_C(15); |
5755 | 0 | op <<= 12; |
5756 | 0 | Value |= op; |
5757 | | // op: B4 |
5758 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5759 | 0 | op &= UINT64_C(15); |
5760 | 0 | op <<= 28; |
5761 | 0 | Value |= op; |
5762 | | // op: D4 |
5763 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
5764 | 0 | op &= UINT64_C(4095); |
5765 | 0 | op <<= 16; |
5766 | 0 | Value |= op; |
5767 | 0 | break; |
5768 | 0 | } |
5769 | 0 | case SystemZ::CGRJ: |
5770 | 0 | case SystemZ::CLGRJ: |
5771 | 0 | case SystemZ::CLRJ: |
5772 | 0 | case SystemZ::CRJ: { |
5773 | | // op: R1 |
5774 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5775 | 0 | op &= UINT64_C(15); |
5776 | 0 | op <<= 36; |
5777 | 0 | Value |= op; |
5778 | | // op: R2 |
5779 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5780 | 0 | op &= UINT64_C(15); |
5781 | 0 | op <<= 32; |
5782 | 0 | Value |= op; |
5783 | | // op: M3 |
5784 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5785 | 0 | op &= UINT64_C(15); |
5786 | 0 | op <<= 12; |
5787 | 0 | Value |= op; |
5788 | | // op: RI4 |
5789 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
5790 | 0 | op &= UINT64_C(65535); |
5791 | 0 | op <<= 16; |
5792 | 0 | Value |= op; |
5793 | 0 | break; |
5794 | 0 | } |
5795 | 0 | case SystemZ::CGRJAsmE: |
5796 | 0 | case SystemZ::CGRJAsmH: |
5797 | 0 | case SystemZ::CGRJAsmHE: |
5798 | 0 | case SystemZ::CGRJAsmL: |
5799 | 0 | case SystemZ::CGRJAsmLE: |
5800 | 0 | case SystemZ::CGRJAsmLH: |
5801 | 0 | case SystemZ::CGRJAsmNE: |
5802 | 0 | case SystemZ::CGRJAsmNH: |
5803 | 0 | case SystemZ::CGRJAsmNHE: |
5804 | 0 | case SystemZ::CGRJAsmNL: |
5805 | 0 | case SystemZ::CGRJAsmNLE: |
5806 | 0 | case SystemZ::CGRJAsmNLH: |
5807 | 0 | case SystemZ::CLGRJAsmE: |
5808 | 0 | case SystemZ::CLGRJAsmH: |
5809 | 0 | case SystemZ::CLGRJAsmHE: |
5810 | 0 | case SystemZ::CLGRJAsmL: |
5811 | 0 | case SystemZ::CLGRJAsmLE: |
5812 | 0 | case SystemZ::CLGRJAsmLH: |
5813 | 0 | case SystemZ::CLGRJAsmNE: |
5814 | 0 | case SystemZ::CLGRJAsmNH: |
5815 | 0 | case SystemZ::CLGRJAsmNHE: |
5816 | 0 | case SystemZ::CLGRJAsmNL: |
5817 | 0 | case SystemZ::CLGRJAsmNLE: |
5818 | 0 | case SystemZ::CLGRJAsmNLH: |
5819 | 0 | case SystemZ::CLRJAsmE: |
5820 | 0 | case SystemZ::CLRJAsmH: |
5821 | 0 | case SystemZ::CLRJAsmHE: |
5822 | 0 | case SystemZ::CLRJAsmL: |
5823 | 0 | case SystemZ::CLRJAsmLE: |
5824 | 0 | case SystemZ::CLRJAsmLH: |
5825 | 0 | case SystemZ::CLRJAsmNE: |
5826 | 0 | case SystemZ::CLRJAsmNH: |
5827 | 0 | case SystemZ::CLRJAsmNHE: |
5828 | 0 | case SystemZ::CLRJAsmNL: |
5829 | 0 | case SystemZ::CLRJAsmNLE: |
5830 | 0 | case SystemZ::CLRJAsmNLH: |
5831 | 0 | case SystemZ::CRJAsmE: |
5832 | 0 | case SystemZ::CRJAsmH: |
5833 | 0 | case SystemZ::CRJAsmHE: |
5834 | 0 | case SystemZ::CRJAsmL: |
5835 | 0 | case SystemZ::CRJAsmLE: |
5836 | 0 | case SystemZ::CRJAsmLH: |
5837 | 0 | case SystemZ::CRJAsmNE: |
5838 | 0 | case SystemZ::CRJAsmNH: |
5839 | 0 | case SystemZ::CRJAsmNHE: |
5840 | 0 | case SystemZ::CRJAsmNL: |
5841 | 0 | case SystemZ::CRJAsmNLE: |
5842 | 0 | case SystemZ::CRJAsmNLH: { |
5843 | | // op: R1 |
5844 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5845 | 0 | op &= UINT64_C(15); |
5846 | 0 | op <<= 36; |
5847 | 0 | Value |= op; |
5848 | | // op: R2 |
5849 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5850 | 0 | op &= UINT64_C(15); |
5851 | 0 | op <<= 32; |
5852 | 0 | Value |= op; |
5853 | | // op: RI4 |
5854 | 0 | op = getPC16DBLEncoding(MI, 2, Fixups, STI); |
5855 | 0 | op &= UINT64_C(65535); |
5856 | 0 | op <<= 16; |
5857 | 0 | Value |= op; |
5858 | 0 | break; |
5859 | 0 | } |
5860 | 0 | case SystemZ::RISBG: |
5861 | 0 | case SystemZ::RISBG32: |
5862 | 0 | case SystemZ::RISBGN: |
5863 | 0 | case SystemZ::RISBHG: |
5864 | 0 | case SystemZ::RISBLG: |
5865 | 0 | case SystemZ::RNSBG: |
5866 | 0 | case SystemZ::ROSBG: |
5867 | 0 | case SystemZ::RXSBG: { |
5868 | | // op: R1 |
5869 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5870 | 0 | op &= UINT64_C(15); |
5871 | 0 | op <<= 36; |
5872 | 0 | Value |= op; |
5873 | | // op: R2 |
5874 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5875 | 0 | op &= UINT64_C(15); |
5876 | 0 | op <<= 32; |
5877 | 0 | Value |= op; |
5878 | | // op: I3 |
5879 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
5880 | 0 | op &= UINT64_C(255); |
5881 | 0 | op <<= 24; |
5882 | 0 | Value |= op; |
5883 | | // op: I4 |
5884 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 4, Fixups, STI); |
5885 | 0 | op &= UINT64_C(255); |
5886 | 0 | op <<= 16; |
5887 | 0 | Value |= op; |
5888 | | // op: I5 |
5889 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 5, Fixups, STI); |
5890 | 0 | op &= UINT64_C(255); |
5891 | 0 | op <<= 8; |
5892 | 0 | Value |= op; |
5893 | 0 | break; |
5894 | 0 | } |
5895 | 0 | case SystemZ::ECAG: |
5896 | 0 | case SystemZ::LAA: |
5897 | 0 | case SystemZ::LAAG: |
5898 | 0 | case SystemZ::LAAL: |
5899 | 0 | case SystemZ::LAALG: |
5900 | 0 | case SystemZ::LAMY: |
5901 | 0 | case SystemZ::LAN: |
5902 | 0 | case SystemZ::LANG: |
5903 | 0 | case SystemZ::LAO: |
5904 | 0 | case SystemZ::LAOG: |
5905 | 0 | case SystemZ::LAX: |
5906 | 0 | case SystemZ::LAXG: |
5907 | 0 | case SystemZ::LCTLG: |
5908 | 0 | case SystemZ::LMG: |
5909 | 0 | case SystemZ::LMH: |
5910 | 0 | case SystemZ::LMY: |
5911 | 0 | case SystemZ::RLL: |
5912 | 0 | case SystemZ::RLLG: |
5913 | 0 | case SystemZ::SLAG: |
5914 | 0 | case SystemZ::SLAK: |
5915 | 0 | case SystemZ::SLLG: |
5916 | 0 | case SystemZ::SLLK: |
5917 | 0 | case SystemZ::SRAG: |
5918 | 0 | case SystemZ::SRAK: |
5919 | 0 | case SystemZ::SRLG: |
5920 | 0 | case SystemZ::SRLK: |
5921 | 0 | case SystemZ::STAMY: |
5922 | 0 | case SystemZ::STCTG: |
5923 | 0 | case SystemZ::STMG: |
5924 | 0 | case SystemZ::STMH: |
5925 | 0 | case SystemZ::STMY: |
5926 | 0 | case SystemZ::TRACG: { |
5927 | | // op: R1 |
5928 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5929 | 0 | op &= UINT64_C(15); |
5930 | 0 | op <<= 36; |
5931 | 0 | Value |= op; |
5932 | | // op: R3 |
5933 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5934 | 0 | op &= UINT64_C(15); |
5935 | 0 | op <<= 32; |
5936 | 0 | Value |= op; |
5937 | | // op: B2 |
5938 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5939 | 0 | op &= UINT64_C(15); |
5940 | 0 | op <<= 28; |
5941 | 0 | Value |= op; |
5942 | | // op: D2 |
5943 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
5944 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5945 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5946 | 0 | break; |
5947 | 0 | } |
5948 | 0 | case SystemZ::CLCLU: |
5949 | 0 | case SystemZ::MVCLU: { |
5950 | | // op: R1 |
5951 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5952 | 0 | op &= UINT64_C(15); |
5953 | 0 | op <<= 36; |
5954 | 0 | Value |= op; |
5955 | | // op: R3 |
5956 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5957 | 0 | op &= UINT64_C(15); |
5958 | 0 | op <<= 32; |
5959 | 0 | Value |= op; |
5960 | | // op: B2 |
5961 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5962 | 0 | op &= UINT64_C(15); |
5963 | 0 | op <<= 28; |
5964 | 0 | Value |= op; |
5965 | | // op: D2 |
5966 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 5, Fixups, STI); |
5967 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
5968 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
5969 | 0 | break; |
5970 | 0 | } |
5971 | 0 | case SystemZ::AGHIK: |
5972 | 0 | case SystemZ::AHIK: |
5973 | 0 | case SystemZ::ALGHSIK: |
5974 | 0 | case SystemZ::ALHSIK: { |
5975 | | // op: R1 |
5976 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5977 | 0 | op &= UINT64_C(15); |
5978 | 0 | op <<= 36; |
5979 | 0 | Value |= op; |
5980 | | // op: R3 |
5981 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5982 | 0 | op &= UINT64_C(15); |
5983 | 0 | op <<= 32; |
5984 | 0 | Value |= op; |
5985 | | // op: I2 |
5986 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
5987 | 0 | op &= UINT64_C(65535); |
5988 | 0 | op <<= 16; |
5989 | 0 | Value |= op; |
5990 | 0 | break; |
5991 | 0 | } |
5992 | 0 | case SystemZ::BXHG: |
5993 | 0 | case SystemZ::BXLEG: |
5994 | 0 | case SystemZ::CDSG: |
5995 | 0 | case SystemZ::CDSY: |
5996 | 0 | case SystemZ::CSG: |
5997 | 0 | case SystemZ::CSY: { |
5998 | | // op: R1 |
5999 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6000 | 0 | op &= UINT64_C(15); |
6001 | 0 | op <<= 36; |
6002 | 0 | Value |= op; |
6003 | | // op: R3 |
6004 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6005 | 0 | op &= UINT64_C(15); |
6006 | 0 | op <<= 32; |
6007 | 0 | Value |= op; |
6008 | | // op: B2 |
6009 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6010 | 0 | op &= UINT64_C(15); |
6011 | 0 | op <<= 28; |
6012 | 0 | Value |= op; |
6013 | | // op: D2 |
6014 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 4, Fixups, STI); |
6015 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
6016 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
6017 | 0 | break; |
6018 | 0 | } |
6019 | 0 | case SystemZ::BRXHG: |
6020 | 0 | case SystemZ::BRXLG: { |
6021 | | // op: R1 |
6022 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6023 | 0 | op &= UINT64_C(15); |
6024 | 0 | op <<= 36; |
6025 | 0 | Value |= op; |
6026 | | // op: R3 |
6027 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6028 | 0 | op &= UINT64_C(15); |
6029 | 0 | op <<= 32; |
6030 | 0 | Value |= op; |
6031 | | // op: RI2 |
6032 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
6033 | 0 | op &= UINT64_C(65535); |
6034 | 0 | op <<= 16; |
6035 | 0 | Value |= op; |
6036 | 0 | break; |
6037 | 0 | } |
6038 | 0 | case SystemZ::CGFRL: |
6039 | 0 | case SystemZ::CGHRL: |
6040 | 0 | case SystemZ::CGRL: |
6041 | 0 | case SystemZ::CHRL: |
6042 | 0 | case SystemZ::CLGFRL: |
6043 | 0 | case SystemZ::CLGHRL: |
6044 | 0 | case SystemZ::CLGRL: |
6045 | 0 | case SystemZ::CLHRL: |
6046 | 0 | case SystemZ::CLRL: |
6047 | 0 | case SystemZ::CRL: |
6048 | 0 | case SystemZ::EXRL: |
6049 | 0 | case SystemZ::LARL: |
6050 | 0 | case SystemZ::LGFRL: |
6051 | 0 | case SystemZ::LGHRL: |
6052 | 0 | case SystemZ::LGRL: |
6053 | 0 | case SystemZ::LHRL: |
6054 | 0 | case SystemZ::LLGFRL: |
6055 | 0 | case SystemZ::LLGHRL: |
6056 | 0 | case SystemZ::LLHRL: |
6057 | 0 | case SystemZ::LRL: |
6058 | 0 | case SystemZ::STGRL: |
6059 | 0 | case SystemZ::STHRL: |
6060 | 0 | case SystemZ::STRL: { |
6061 | | // op: R1 |
6062 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6063 | 0 | op &= UINT64_C(15); |
6064 | 0 | op <<= 36; |
6065 | 0 | Value |= op; |
6066 | | // op: RI2 |
6067 | 0 | op = getPC32DBLEncoding(MI, 1, Fixups, STI); |
6068 | 0 | op &= UINT64_C(4294967295); |
6069 | 0 | Value |= op; |
6070 | 0 | break; |
6071 | 0 | } |
6072 | 0 | case SystemZ::BRCTH: { |
6073 | | // op: R1 |
6074 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6075 | 0 | op &= UINT64_C(15); |
6076 | 0 | op <<= 36; |
6077 | 0 | Value |= op; |
6078 | | // op: RI2 |
6079 | 0 | op = getPC32DBLEncoding(MI, 2, Fixups, STI); |
6080 | 0 | op &= UINT64_C(4294967295); |
6081 | 0 | Value |= op; |
6082 | 0 | break; |
6083 | 0 | } |
6084 | 0 | case SystemZ::BRASL: { |
6085 | | // op: R1 |
6086 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6087 | 0 | op &= UINT64_C(15); |
6088 | 0 | op <<= 36; |
6089 | 0 | Value |= op; |
6090 | | // op: RI2 |
6091 | 0 | op = getPC32DBLTLSEncoding(MI, 1, Fixups, STI); |
6092 | 0 | op &= UINT64_C(4294967295); |
6093 | 0 | Value |= op; |
6094 | 0 | break; |
6095 | 0 | } |
6096 | 0 | case SystemZ::VCVB: |
6097 | 0 | case SystemZ::VCVBG: { |
6098 | | // op: R1 |
6099 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6100 | 0 | op &= UINT64_C(15); |
6101 | 0 | op <<= 36; |
6102 | 0 | Value |= op; |
6103 | | // op: V2 |
6104 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6105 | 0 | Value |= (op & UINT64_C(15)) << 32; |
6106 | 0 | Value |= (op & UINT64_C(16)) << 6; |
6107 | | // op: M3 |
6108 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
6109 | 0 | op &= UINT64_C(15); |
6110 | 0 | op <<= 20; |
6111 | 0 | Value |= op; |
6112 | 0 | break; |
6113 | 0 | } |
6114 | 0 | case SystemZ::VCVBGOpt: |
6115 | 0 | case SystemZ::VCVBOpt: { |
6116 | | // op: R1 |
6117 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6118 | 0 | op &= UINT64_C(15); |
6119 | 0 | op <<= 36; |
6120 | 0 | Value |= op; |
6121 | | // op: V2 |
6122 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6123 | 0 | Value |= (op & UINT64_C(15)) << 32; |
6124 | 0 | Value |= (op & UINT64_C(16)) << 6; |
6125 | | // op: M3 |
6126 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
6127 | 0 | op &= UINT64_C(15); |
6128 | 0 | op <<= 20; |
6129 | 0 | Value |= op; |
6130 | | // op: M4 |
6131 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
6132 | 0 | op &= UINT64_C(15); |
6133 | 0 | op <<= 16; |
6134 | 0 | Value |= op; |
6135 | 0 | break; |
6136 | 0 | } |
6137 | 0 | case SystemZ::CG: |
6138 | 0 | case SystemZ::CGF: |
6139 | 0 | case SystemZ::CGH: |
6140 | 0 | case SystemZ::CHF: |
6141 | 0 | case SystemZ::CHY: |
6142 | 0 | case SystemZ::CLG: |
6143 | 0 | case SystemZ::CLGF: |
6144 | 0 | case SystemZ::CLHF: |
6145 | 0 | case SystemZ::CLY: |
6146 | 0 | case SystemZ::CVDG: |
6147 | 0 | case SystemZ::CVDY: |
6148 | 0 | case SystemZ::CY: |
6149 | 0 | case SystemZ::LAEY: |
6150 | 0 | case SystemZ::LAT: |
6151 | 0 | case SystemZ::LAY: |
6152 | 0 | case SystemZ::LB: |
6153 | 0 | case SystemZ::LBH: |
6154 | 0 | case SystemZ::LDY: |
6155 | 0 | case SystemZ::LEY: |
6156 | 0 | case SystemZ::LFH: |
6157 | 0 | case SystemZ::LFHAT: |
6158 | 0 | case SystemZ::LG: |
6159 | 0 | case SystemZ::LGAT: |
6160 | 0 | case SystemZ::LGB: |
6161 | 0 | case SystemZ::LGF: |
6162 | 0 | case SystemZ::LGG: |
6163 | 0 | case SystemZ::LGH: |
6164 | 0 | case SystemZ::LGSC: |
6165 | 0 | case SystemZ::LHH: |
6166 | 0 | case SystemZ::LHY: |
6167 | 0 | case SystemZ::LLC: |
6168 | 0 | case SystemZ::LLCH: |
6169 | 0 | case SystemZ::LLGC: |
6170 | 0 | case SystemZ::LLGF: |
6171 | 0 | case SystemZ::LLGFAT: |
6172 | 0 | case SystemZ::LLGFSG: |
6173 | 0 | case SystemZ::LLGH: |
6174 | 0 | case SystemZ::LLGT: |
6175 | 0 | case SystemZ::LLGTAT: |
6176 | 0 | case SystemZ::LLH: |
6177 | 0 | case SystemZ::LLHH: |
6178 | 0 | case SystemZ::LLZRGF: |
6179 | 0 | case SystemZ::LPQ: |
6180 | 0 | case SystemZ::LRAG: |
6181 | 0 | case SystemZ::LRAY: |
6182 | 0 | case SystemZ::LRV: |
6183 | 0 | case SystemZ::LRVG: |
6184 | 0 | case SystemZ::LRVH: |
6185 | 0 | case SystemZ::LT: |
6186 | 0 | case SystemZ::LTG: |
6187 | 0 | case SystemZ::LTGF: |
6188 | 0 | case SystemZ::LY: |
6189 | 0 | case SystemZ::LZRF: |
6190 | 0 | case SystemZ::LZRG: |
6191 | 0 | case SystemZ::NTSTG: |
6192 | 0 | case SystemZ::STCH: |
6193 | 0 | case SystemZ::STCY: |
6194 | 0 | case SystemZ::STDY: |
6195 | 0 | case SystemZ::STEY: |
6196 | 0 | case SystemZ::STFH: |
6197 | 0 | case SystemZ::STG: |
6198 | 0 | case SystemZ::STGSC: |
6199 | 0 | case SystemZ::STHH: |
6200 | 0 | case SystemZ::STHY: |
6201 | 0 | case SystemZ::STPQ: |
6202 | 0 | case SystemZ::STRV: |
6203 | 0 | case SystemZ::STRVG: |
6204 | 0 | case SystemZ::STRVH: |
6205 | 0 | case SystemZ::STY: { |
6206 | | // op: R1 |
6207 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6208 | 0 | op &= UINT64_C(15); |
6209 | 0 | op <<= 36; |
6210 | 0 | Value |= op; |
6211 | | // op: X2 |
6212 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6213 | 0 | op &= UINT64_C(15); |
6214 | 0 | op <<= 32; |
6215 | 0 | Value |= op; |
6216 | | // op: B2 |
6217 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6218 | 0 | op &= UINT64_C(15); |
6219 | 0 | op <<= 28; |
6220 | 0 | Value |= op; |
6221 | | // op: D2 |
6222 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 2, Fixups, STI); |
6223 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
6224 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
6225 | 0 | break; |
6226 | 0 | } |
6227 | 0 | case SystemZ::CDB: |
6228 | 0 | case SystemZ::CEB: |
6229 | 0 | case SystemZ::KDB: |
6230 | 0 | case SystemZ::KEB: |
6231 | 0 | case SystemZ::LDE: |
6232 | 0 | case SystemZ::LDE32: |
6233 | 0 | case SystemZ::LDEB: |
6234 | 0 | case SystemZ::LXD: |
6235 | 0 | case SystemZ::LXDB: |
6236 | 0 | case SystemZ::LXE: |
6237 | 0 | case SystemZ::LXEB: |
6238 | 0 | case SystemZ::SQD: |
6239 | 0 | case SystemZ::SQDB: |
6240 | 0 | case SystemZ::SQE: |
6241 | 0 | case SystemZ::SQEB: |
6242 | 0 | case SystemZ::TCDB: |
6243 | 0 | case SystemZ::TCEB: |
6244 | 0 | case SystemZ::TCXB: |
6245 | 0 | case SystemZ::TDCDT: |
6246 | 0 | case SystemZ::TDCET: |
6247 | 0 | case SystemZ::TDCXT: |
6248 | 0 | case SystemZ::TDGDT: |
6249 | 0 | case SystemZ::TDGET: |
6250 | 0 | case SystemZ::TDGXT: { |
6251 | | // op: R1 |
6252 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6253 | 0 | op &= UINT64_C(15); |
6254 | 0 | op <<= 36; |
6255 | 0 | Value |= op; |
6256 | | // op: X2 |
6257 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6258 | 0 | op &= UINT64_C(15); |
6259 | 0 | op <<= 32; |
6260 | 0 | Value |= op; |
6261 | | // op: B2 |
6262 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6263 | 0 | op &= UINT64_C(15); |
6264 | 0 | op <<= 28; |
6265 | 0 | Value |= op; |
6266 | | // op: D2 |
6267 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
6268 | 0 | op &= UINT64_C(4095); |
6269 | 0 | op <<= 16; |
6270 | 0 | Value |= op; |
6271 | 0 | break; |
6272 | 0 | } |
6273 | 0 | case SystemZ::LCBB: { |
6274 | | // op: R1 |
6275 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6276 | 0 | op &= UINT64_C(15); |
6277 | 0 | op <<= 36; |
6278 | 0 | Value |= op; |
6279 | | // op: X2 |
6280 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6281 | 0 | op &= UINT64_C(15); |
6282 | 0 | op <<= 32; |
6283 | 0 | Value |= op; |
6284 | | // op: B2 |
6285 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6286 | 0 | op &= UINT64_C(15); |
6287 | 0 | op <<= 28; |
6288 | 0 | Value |= op; |
6289 | | // op: D2 |
6290 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
6291 | 0 | op &= UINT64_C(4095); |
6292 | 0 | op <<= 16; |
6293 | 0 | Value |= op; |
6294 | | // op: M3 |
6295 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
6296 | 0 | op &= UINT64_C(15); |
6297 | 0 | op <<= 12; |
6298 | 0 | Value |= op; |
6299 | 0 | break; |
6300 | 0 | } |
6301 | 0 | case SystemZ::AG: |
6302 | 0 | case SystemZ::AGF: |
6303 | 0 | case SystemZ::AGH: |
6304 | 0 | case SystemZ::AHY: |
6305 | 0 | case SystemZ::ALC: |
6306 | 0 | case SystemZ::ALCG: |
6307 | 0 | case SystemZ::ALG: |
6308 | 0 | case SystemZ::ALGF: |
6309 | 0 | case SystemZ::ALY: |
6310 | 0 | case SystemZ::AY: |
6311 | 0 | case SystemZ::BCTG: |
6312 | 0 | case SystemZ::CVBG: |
6313 | 0 | case SystemZ::CVBY: |
6314 | 0 | case SystemZ::DL: |
6315 | 0 | case SystemZ::DLG: |
6316 | 0 | case SystemZ::DSG: |
6317 | 0 | case SystemZ::DSGF: |
6318 | 0 | case SystemZ::IC32Y: |
6319 | 0 | case SystemZ::ICY: |
6320 | 0 | case SystemZ::MFY: |
6321 | 0 | case SystemZ::MG: |
6322 | 0 | case SystemZ::MGH: |
6323 | 0 | case SystemZ::MHY: |
6324 | 0 | case SystemZ::ML: |
6325 | 0 | case SystemZ::MLG: |
6326 | 0 | case SystemZ::MSC: |
6327 | 0 | case SystemZ::MSG: |
6328 | 0 | case SystemZ::MSGC: |
6329 | 0 | case SystemZ::MSGF: |
6330 | 0 | case SystemZ::MSY: |
6331 | 0 | case SystemZ::NG: |
6332 | 0 | case SystemZ::NY: |
6333 | 0 | case SystemZ::OG: |
6334 | 0 | case SystemZ::OY: |
6335 | 0 | case SystemZ::SG: |
6336 | 0 | case SystemZ::SGF: |
6337 | 0 | case SystemZ::SGH: |
6338 | 0 | case SystemZ::SHY: |
6339 | 0 | case SystemZ::SLB: |
6340 | 0 | case SystemZ::SLBG: |
6341 | 0 | case SystemZ::SLG: |
6342 | 0 | case SystemZ::SLGF: |
6343 | 0 | case SystemZ::SLY: |
6344 | 0 | case SystemZ::SY: |
6345 | 0 | case SystemZ::XG: |
6346 | 0 | case SystemZ::XY: { |
6347 | | // op: R1 |
6348 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6349 | 0 | op &= UINT64_C(15); |
6350 | 0 | op <<= 36; |
6351 | 0 | Value |= op; |
6352 | | // op: X2 |
6353 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6354 | 0 | op &= UINT64_C(15); |
6355 | 0 | op <<= 32; |
6356 | 0 | Value |= op; |
6357 | | // op: B2 |
6358 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6359 | 0 | op &= UINT64_C(15); |
6360 | 0 | op <<= 28; |
6361 | 0 | Value |= op; |
6362 | | // op: D2 |
6363 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
6364 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
6365 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
6366 | 0 | break; |
6367 | 0 | } |
6368 | 0 | case SystemZ::ADB: |
6369 | 0 | case SystemZ::AEB: |
6370 | 0 | case SystemZ::DDB: |
6371 | 0 | case SystemZ::DEB: |
6372 | 0 | case SystemZ::MDB: |
6373 | 0 | case SystemZ::MDEB: |
6374 | 0 | case SystemZ::MEE: |
6375 | 0 | case SystemZ::MEEB: |
6376 | 0 | case SystemZ::MXDB: |
6377 | 0 | case SystemZ::SDB: |
6378 | 0 | case SystemZ::SEB: { |
6379 | | // op: R1 |
6380 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6381 | 0 | op &= UINT64_C(15); |
6382 | 0 | op <<= 36; |
6383 | 0 | Value |= op; |
6384 | | // op: X2 |
6385 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6386 | 0 | op &= UINT64_C(15); |
6387 | 0 | op <<= 32; |
6388 | 0 | Value |= op; |
6389 | | // op: B2 |
6390 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6391 | 0 | op &= UINT64_C(15); |
6392 | 0 | op <<= 28; |
6393 | 0 | Value |= op; |
6394 | | // op: D2 |
6395 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
6396 | 0 | op &= UINT64_C(4095); |
6397 | 0 | op <<= 16; |
6398 | 0 | Value |= op; |
6399 | 0 | break; |
6400 | 0 | } |
6401 | 0 | case SystemZ::EFPC: |
6402 | 0 | case SystemZ::EPAIR: |
6403 | 0 | case SystemZ::EPAR: |
6404 | 0 | case SystemZ::ESAIR: |
6405 | 0 | case SystemZ::ESAR: |
6406 | 0 | case SystemZ::ESEA: |
6407 | 0 | case SystemZ::ETND: |
6408 | 0 | case SystemZ::IAC: |
6409 | 0 | case SystemZ::IPM: |
6410 | 0 | case SystemZ::LZDR: |
6411 | 0 | case SystemZ::LZER: |
6412 | 0 | case SystemZ::LZXR: |
6413 | 0 | case SystemZ::MSTA: |
6414 | 0 | case SystemZ::PTF: |
6415 | 0 | case SystemZ::SFASR: |
6416 | 0 | case SystemZ::SFPC: |
6417 | 0 | case SystemZ::SPM: |
6418 | 0 | case SystemZ::SSAIR: |
6419 | 0 | case SystemZ::SSAR: { |
6420 | | // op: R1 |
6421 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6422 | 0 | op &= UINT64_C(15); |
6423 | 0 | op <<= 4; |
6424 | 0 | Value |= op; |
6425 | 0 | break; |
6426 | 0 | } |
6427 | 0 | case SystemZ::BAKR: |
6428 | 0 | case SystemZ::BALR: |
6429 | 0 | case SystemZ::BASR: |
6430 | 0 | case SystemZ::BASSM: |
6431 | 0 | case SystemZ::BSA: |
6432 | 0 | case SystemZ::BSG: |
6433 | 0 | case SystemZ::BSM: |
6434 | 0 | case SystemZ::CDBR: |
6435 | 0 | case SystemZ::CDFBR: |
6436 | 0 | case SystemZ::CDFR: |
6437 | 0 | case SystemZ::CDGBR: |
6438 | 0 | case SystemZ::CDGR: |
6439 | 0 | case SystemZ::CDGTR: |
6440 | 0 | case SystemZ::CDR: |
6441 | 0 | case SystemZ::CDSTR: |
6442 | 0 | case SystemZ::CDTR: |
6443 | 0 | case SystemZ::CDUTR: |
6444 | 0 | case SystemZ::CEBR: |
6445 | 0 | case SystemZ::CEDTR: |
6446 | 0 | case SystemZ::CEFBR: |
6447 | 0 | case SystemZ::CEFR: |
6448 | 0 | case SystemZ::CEGBR: |
6449 | 0 | case SystemZ::CEGR: |
6450 | 0 | case SystemZ::CER: |
6451 | 0 | case SystemZ::CEXTR: |
6452 | 0 | case SystemZ::CGFR: |
6453 | 0 | case SystemZ::CGR: |
6454 | 0 | case SystemZ::CGRTAsmE: |
6455 | 0 | case SystemZ::CGRTAsmH: |
6456 | 0 | case SystemZ::CGRTAsmHE: |
6457 | 0 | case SystemZ::CGRTAsmL: |
6458 | 0 | case SystemZ::CGRTAsmLE: |
6459 | 0 | case SystemZ::CGRTAsmLH: |
6460 | 0 | case SystemZ::CGRTAsmNE: |
6461 | 0 | case SystemZ::CGRTAsmNH: |
6462 | 0 | case SystemZ::CGRTAsmNHE: |
6463 | 0 | case SystemZ::CGRTAsmNL: |
6464 | 0 | case SystemZ::CGRTAsmNLE: |
6465 | 0 | case SystemZ::CGRTAsmNLH: |
6466 | 0 | case SystemZ::CHHR: |
6467 | 0 | case SystemZ::CHLR: |
6468 | 0 | case SystemZ::CKSM: |
6469 | 0 | case SystemZ::CLCL: |
6470 | 0 | case SystemZ::CLGFR: |
6471 | 0 | case SystemZ::CLGR: |
6472 | 0 | case SystemZ::CLGRTAsmE: |
6473 | 0 | case SystemZ::CLGRTAsmH: |
6474 | 0 | case SystemZ::CLGRTAsmHE: |
6475 | 0 | case SystemZ::CLGRTAsmL: |
6476 | 0 | case SystemZ::CLGRTAsmLE: |
6477 | 0 | case SystemZ::CLGRTAsmLH: |
6478 | 0 | case SystemZ::CLGRTAsmNE: |
6479 | 0 | case SystemZ::CLGRTAsmNH: |
6480 | 0 | case SystemZ::CLGRTAsmNHE: |
6481 | 0 | case SystemZ::CLGRTAsmNL: |
6482 | 0 | case SystemZ::CLGRTAsmNLE: |
6483 | 0 | case SystemZ::CLGRTAsmNLH: |
6484 | 0 | case SystemZ::CLHHR: |
6485 | 0 | case SystemZ::CLHLR: |
6486 | 0 | case SystemZ::CLR: |
6487 | 0 | case SystemZ::CLRTAsmE: |
6488 | 0 | case SystemZ::CLRTAsmH: |
6489 | 0 | case SystemZ::CLRTAsmHE: |
6490 | 0 | case SystemZ::CLRTAsmL: |
6491 | 0 | case SystemZ::CLRTAsmLE: |
6492 | 0 | case SystemZ::CLRTAsmLH: |
6493 | 0 | case SystemZ::CLRTAsmNE: |
6494 | 0 | case SystemZ::CLRTAsmNH: |
6495 | 0 | case SystemZ::CLRTAsmNHE: |
6496 | 0 | case SystemZ::CLRTAsmNL: |
6497 | 0 | case SystemZ::CLRTAsmNLE: |
6498 | 0 | case SystemZ::CLRTAsmNLH: |
6499 | 0 | case SystemZ::CLST: |
6500 | 0 | case SystemZ::CMPSC: |
6501 | 0 | case SystemZ::CPYA: |
6502 | 0 | case SystemZ::CR: |
6503 | 0 | case SystemZ::CRTAsmE: |
6504 | 0 | case SystemZ::CRTAsmH: |
6505 | 0 | case SystemZ::CRTAsmHE: |
6506 | 0 | case SystemZ::CRTAsmL: |
6507 | 0 | case SystemZ::CRTAsmLE: |
6508 | 0 | case SystemZ::CRTAsmLH: |
6509 | 0 | case SystemZ::CRTAsmNE: |
6510 | 0 | case SystemZ::CRTAsmNH: |
6511 | 0 | case SystemZ::CRTAsmNHE: |
6512 | 0 | case SystemZ::CRTAsmNL: |
6513 | 0 | case SystemZ::CRTAsmNLE: |
6514 | 0 | case SystemZ::CRTAsmNLH: |
6515 | 0 | case SystemZ::CU12Opt: |
6516 | 0 | case SystemZ::CU14Opt: |
6517 | 0 | case SystemZ::CU21Opt: |
6518 | 0 | case SystemZ::CU24Opt: |
6519 | 0 | case SystemZ::CU41: |
6520 | 0 | case SystemZ::CU42: |
6521 | 0 | case SystemZ::CUDTR: |
6522 | 0 | case SystemZ::CUSE: |
6523 | 0 | case SystemZ::CUTFUOpt: |
6524 | 0 | case SystemZ::CUUTFOpt: |
6525 | 0 | case SystemZ::CUXTR: |
6526 | 0 | case SystemZ::CXBR: |
6527 | 0 | case SystemZ::CXFBR: |
6528 | 0 | case SystemZ::CXFR: |
6529 | 0 | case SystemZ::CXGBR: |
6530 | 0 | case SystemZ::CXGR: |
6531 | 0 | case SystemZ::CXGTR: |
6532 | 0 | case SystemZ::CXR: |
6533 | 0 | case SystemZ::CXSTR: |
6534 | 0 | case SystemZ::CXTR: |
6535 | 0 | case SystemZ::CXUTR: |
6536 | 0 | case SystemZ::EAR: |
6537 | 0 | case SystemZ::ECCTR: |
6538 | 0 | case SystemZ::ECPGA: |
6539 | 0 | case SystemZ::EEDTR: |
6540 | 0 | case SystemZ::EEXTR: |
6541 | 0 | case SystemZ::EPCTR: |
6542 | 0 | case SystemZ::EPSW: |
6543 | 0 | case SystemZ::EREG: |
6544 | 0 | case SystemZ::EREGG: |
6545 | 0 | case SystemZ::ESDTR: |
6546 | 0 | case SystemZ::ESTA: |
6547 | 0 | case SystemZ::ESXTR: |
6548 | 0 | case SystemZ::FIDR: |
6549 | 0 | case SystemZ::FIER: |
6550 | 0 | case SystemZ::FIXR: |
6551 | 0 | case SystemZ::FLOGR: |
6552 | 0 | case SystemZ::HDR: |
6553 | 0 | case SystemZ::HER: |
6554 | 0 | case SystemZ::IPTEOptOpt: |
6555 | 0 | case SystemZ::IRBM: |
6556 | 0 | case SystemZ::KDBR: |
6557 | 0 | case SystemZ::KDTR: |
6558 | 0 | case SystemZ::KEBR: |
6559 | 0 | case SystemZ::KM: |
6560 | 0 | case SystemZ::KMC: |
6561 | 0 | case SystemZ::KMF: |
6562 | 0 | case SystemZ::KMO: |
6563 | 0 | case SystemZ::KXBR: |
6564 | 0 | case SystemZ::KXTR: |
6565 | 0 | case SystemZ::LBR: |
6566 | 0 | case SystemZ::LCDBR: |
6567 | 0 | case SystemZ::LCDFR: |
6568 | 0 | case SystemZ::LCDFR_32: |
6569 | 0 | case SystemZ::LCDR: |
6570 | 0 | case SystemZ::LCEBR: |
6571 | 0 | case SystemZ::LCER: |
6572 | 0 | case SystemZ::LCGFR: |
6573 | 0 | case SystemZ::LCGR: |
6574 | 0 | case SystemZ::LCR: |
6575 | 0 | case SystemZ::LCXBR: |
6576 | 0 | case SystemZ::LCXR: |
6577 | 0 | case SystemZ::LDEBR: |
6578 | 0 | case SystemZ::LDER: |
6579 | 0 | case SystemZ::LDGR: |
6580 | 0 | case SystemZ::LDR: |
6581 | 0 | case SystemZ::LDR32: |
6582 | 0 | case SystemZ::LDXBR: |
6583 | 0 | case SystemZ::LDXR: |
6584 | 0 | case SystemZ::LEDBR: |
6585 | 0 | case SystemZ::LEDR: |
6586 | 0 | case SystemZ::LER: |
6587 | 0 | case SystemZ::LEXBR: |
6588 | 0 | case SystemZ::LEXR: |
6589 | 0 | case SystemZ::LGBR: |
6590 | 0 | case SystemZ::LGDR: |
6591 | 0 | case SystemZ::LGFR: |
6592 | 0 | case SystemZ::LGHR: |
6593 | 0 | case SystemZ::LGR: |
6594 | 0 | case SystemZ::LHR: |
6595 | 0 | case SystemZ::LLCR: |
6596 | 0 | case SystemZ::LLGCR: |
6597 | 0 | case SystemZ::LLGFR: |
6598 | 0 | case SystemZ::LLGHR: |
6599 | 0 | case SystemZ::LLGTR: |
6600 | 0 | case SystemZ::LLHR: |
6601 | 0 | case SystemZ::LNDBR: |
6602 | 0 | case SystemZ::LNDFR: |
6603 | 0 | case SystemZ::LNDFR_32: |
6604 | 0 | case SystemZ::LNDR: |
6605 | 0 | case SystemZ::LNEBR: |
6606 | 0 | case SystemZ::LNER: |
6607 | 0 | case SystemZ::LNGFR: |
6608 | 0 | case SystemZ::LNGR: |
6609 | 0 | case SystemZ::LNR: |
6610 | 0 | case SystemZ::LNXBR: |
6611 | 0 | case SystemZ::LNXR: |
6612 | 0 | case SystemZ::LPDBR: |
6613 | 0 | case SystemZ::LPDFR: |
6614 | 0 | case SystemZ::LPDFR_32: |
6615 | 0 | case SystemZ::LPDR: |
6616 | 0 | case SystemZ::LPEBR: |
6617 | 0 | case SystemZ::LPER: |
6618 | 0 | case SystemZ::LPGFR: |
6619 | 0 | case SystemZ::LPGR: |
6620 | 0 | case SystemZ::LPR: |
6621 | 0 | case SystemZ::LPXBR: |
6622 | 0 | case SystemZ::LPXR: |
6623 | 0 | case SystemZ::LR: |
6624 | 0 | case SystemZ::LRDR: |
6625 | 0 | case SystemZ::LRER: |
6626 | 0 | case SystemZ::LRVGR: |
6627 | 0 | case SystemZ::LRVR: |
6628 | 0 | case SystemZ::LTDBR: |
6629 | 0 | case SystemZ::LTDR: |
6630 | 0 | case SystemZ::LTDTR: |
6631 | 0 | case SystemZ::LTEBR: |
6632 | 0 | case SystemZ::LTER: |
6633 | 0 | case SystemZ::LTGFR: |
6634 | 0 | case SystemZ::LTGR: |
6635 | 0 | case SystemZ::LTR: |
6636 | 0 | case SystemZ::LTXBR: |
6637 | 0 | case SystemZ::LTXR: |
6638 | 0 | case SystemZ::LTXTR: |
6639 | 0 | case SystemZ::LURA: |
6640 | 0 | case SystemZ::LURAG: |
6641 | 0 | case SystemZ::LXDBR: |
6642 | 0 | case SystemZ::LXDR: |
6643 | 0 | case SystemZ::LXEBR: |
6644 | 0 | case SystemZ::LXER: |
6645 | 0 | case SystemZ::LXR: |
6646 | 0 | case SystemZ::MVCL: |
6647 | 0 | case SystemZ::MVPG: |
6648 | 0 | case SystemZ::MVST: |
6649 | 0 | case SystemZ::PGIN: |
6650 | 0 | case SystemZ::PGOUT: |
6651 | 0 | case SystemZ::POPCNT: |
6652 | 0 | case SystemZ::PPNO: |
6653 | 0 | case SystemZ::PRNO: |
6654 | 0 | case SystemZ::PT: |
6655 | 0 | case SystemZ::PTI: |
6656 | 0 | case SystemZ::RRBE: |
6657 | 0 | case SystemZ::RRBM: |
6658 | 0 | case SystemZ::SAR: |
6659 | 0 | case SystemZ::SCCTR: |
6660 | 0 | case SystemZ::SORTL: |
6661 | 0 | case SystemZ::SPCTR: |
6662 | 0 | case SystemZ::SQDBR: |
6663 | 0 | case SystemZ::SQDR: |
6664 | 0 | case SystemZ::SQEBR: |
6665 | 0 | case SystemZ::SQER: |
6666 | 0 | case SystemZ::SQXBR: |
6667 | 0 | case SystemZ::SQXR: |
6668 | 0 | case SystemZ::SRST: |
6669 | 0 | case SystemZ::SRSTU: |
6670 | 0 | case SystemZ::SSKEOpt: |
6671 | 0 | case SystemZ::STURA: |
6672 | 0 | case SystemZ::STURG: |
6673 | 0 | case SystemZ::TAR: |
6674 | 0 | case SystemZ::TB: |
6675 | 0 | case SystemZ::THDER: |
6676 | 0 | case SystemZ::THDR: |
6677 | 0 | case SystemZ::TRE: |
6678 | 0 | case SystemZ::TROOOpt: |
6679 | 0 | case SystemZ::TROTOpt: |
6680 | 0 | case SystemZ::TRTOOpt: |
6681 | 0 | case SystemZ::TRTTOpt: { |
6682 | | // op: R1 |
6683 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6684 | 0 | op &= UINT64_C(15); |
6685 | 0 | op <<= 4; |
6686 | 0 | Value |= op; |
6687 | | // op: R2 |
6688 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6689 | 0 | op &= UINT64_C(15); |
6690 | 0 | Value |= op; |
6691 | 0 | break; |
6692 | 0 | } |
6693 | 0 | case SystemZ::CGRTAsm: |
6694 | 0 | case SystemZ::CLGRTAsm: |
6695 | 0 | case SystemZ::CLRTAsm: |
6696 | 0 | case SystemZ::CRTAsm: |
6697 | 0 | case SystemZ::POPCNTOpt: |
6698 | 0 | case SystemZ::PPA: |
6699 | 0 | case SystemZ::SSKE: { |
6700 | | // op: R1 |
6701 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6702 | 0 | op &= UINT64_C(15); |
6703 | 0 | op <<= 4; |
6704 | 0 | Value |= op; |
6705 | | // op: R2 |
6706 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6707 | 0 | op &= UINT64_C(15); |
6708 | 0 | Value |= op; |
6709 | | // op: M3 |
6710 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
6711 | 0 | op &= UINT64_C(15); |
6712 | 0 | op <<= 12; |
6713 | 0 | Value |= op; |
6714 | 0 | break; |
6715 | 0 | } |
6716 | 0 | case SystemZ::CU12: |
6717 | 0 | case SystemZ::CU14: |
6718 | 0 | case SystemZ::CU21: |
6719 | 0 | case SystemZ::CU24: |
6720 | 0 | case SystemZ::CUTFU: |
6721 | 0 | case SystemZ::CUUTF: |
6722 | 0 | case SystemZ::TROO: |
6723 | 0 | case SystemZ::TROT: |
6724 | 0 | case SystemZ::TRTO: |
6725 | 0 | case SystemZ::TRTT: { |
6726 | | // op: R1 |
6727 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6728 | 0 | op &= UINT64_C(15); |
6729 | 0 | op <<= 4; |
6730 | 0 | Value |= op; |
6731 | | // op: R2 |
6732 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6733 | 0 | op &= UINT64_C(15); |
6734 | 0 | Value |= op; |
6735 | | // op: M3 |
6736 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
6737 | 0 | op &= UINT64_C(15); |
6738 | 0 | op <<= 12; |
6739 | 0 | Value |= op; |
6740 | 0 | break; |
6741 | 0 | } |
6742 | 0 | case SystemZ::CGRT: |
6743 | 0 | case SystemZ::CLGRT: |
6744 | 0 | case SystemZ::CLRT: |
6745 | 0 | case SystemZ::CRT: { |
6746 | | // op: R1 |
6747 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6748 | 0 | op &= UINT64_C(15); |
6749 | 0 | op <<= 4; |
6750 | 0 | Value |= op; |
6751 | | // op: R2 |
6752 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6753 | 0 | op &= UINT64_C(15); |
6754 | 0 | Value |= op; |
6755 | | // op: M3 |
6756 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6757 | 0 | op &= UINT64_C(15); |
6758 | 0 | op <<= 12; |
6759 | 0 | Value |= op; |
6760 | 0 | break; |
6761 | 0 | } |
6762 | 0 | case SystemZ::CSDTR: |
6763 | 0 | case SystemZ::CSXTR: |
6764 | 0 | case SystemZ::LDETR: |
6765 | 0 | case SystemZ::LXDTR: { |
6766 | | // op: R1 |
6767 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6768 | 0 | op &= UINT64_C(15); |
6769 | 0 | op <<= 4; |
6770 | 0 | Value |= op; |
6771 | | // op: R2 |
6772 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6773 | 0 | op &= UINT64_C(15); |
6774 | 0 | Value |= op; |
6775 | | // op: M4 |
6776 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
6777 | 0 | op &= UINT64_C(15); |
6778 | 0 | op <<= 8; |
6779 | 0 | Value |= op; |
6780 | 0 | break; |
6781 | 0 | } |
6782 | 0 | case SystemZ::ADTR: |
6783 | 0 | case SystemZ::AGRK: |
6784 | 0 | case SystemZ::AHHHR: |
6785 | 0 | case SystemZ::AHHLR: |
6786 | 0 | case SystemZ::ALGRK: |
6787 | 0 | case SystemZ::ALHHHR: |
6788 | 0 | case SystemZ::ALHHLR: |
6789 | 0 | case SystemZ::ALRK: |
6790 | 0 | case SystemZ::ARK: |
6791 | 0 | case SystemZ::AXTR: |
6792 | 0 | case SystemZ::CPSDRdd: |
6793 | 0 | case SystemZ::CPSDRds: |
6794 | 0 | case SystemZ::CPSDRsd: |
6795 | 0 | case SystemZ::CPSDRss: |
6796 | 0 | case SystemZ::CRDTEOpt: |
6797 | 0 | case SystemZ::DDTR: |
6798 | 0 | case SystemZ::DXTR: |
6799 | 0 | case SystemZ::IDTEOpt: |
6800 | 0 | case SystemZ::IEDTR: |
6801 | 0 | case SystemZ::IEXTR: |
6802 | 0 | case SystemZ::IPTEOpt: |
6803 | 0 | case SystemZ::KMA: |
6804 | 0 | case SystemZ::KMCTR: |
6805 | 0 | case SystemZ::MDTR: |
6806 | 0 | case SystemZ::MGRK: |
6807 | 0 | case SystemZ::MSGRKC: |
6808 | 0 | case SystemZ::MSRKC: |
6809 | 0 | case SystemZ::MXTR: |
6810 | 0 | case SystemZ::NCGRK: |
6811 | 0 | case SystemZ::NCRK: |
6812 | 0 | case SystemZ::NGRK: |
6813 | 0 | case SystemZ::NNGRK: |
6814 | 0 | case SystemZ::NNRK: |
6815 | 0 | case SystemZ::NOGRK: |
6816 | 0 | case SystemZ::NORK: |
6817 | 0 | case SystemZ::NRK: |
6818 | 0 | case SystemZ::NXGRK: |
6819 | 0 | case SystemZ::NXRK: |
6820 | 0 | case SystemZ::OCGRK: |
6821 | 0 | case SystemZ::OCRK: |
6822 | 0 | case SystemZ::OGRK: |
6823 | 0 | case SystemZ::ORK: |
6824 | 0 | case SystemZ::RDPOpt: |
6825 | 0 | case SystemZ::SDTR: |
6826 | 0 | case SystemZ::SGRK: |
6827 | 0 | case SystemZ::SHHHR: |
6828 | 0 | case SystemZ::SHHLR: |
6829 | 0 | case SystemZ::SLGRK: |
6830 | 0 | case SystemZ::SLHHHR: |
6831 | 0 | case SystemZ::SLHHLR: |
6832 | 0 | case SystemZ::SLRK: |
6833 | 0 | case SystemZ::SRK: |
6834 | 0 | case SystemZ::SXTR: |
6835 | 0 | case SystemZ::XGRK: |
6836 | 0 | case SystemZ::XRK: { |
6837 | | // op: R1 |
6838 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6839 | 0 | op &= UINT64_C(15); |
6840 | 0 | op <<= 4; |
6841 | 0 | Value |= op; |
6842 | | // op: R2 |
6843 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6844 | 0 | op &= UINT64_C(15); |
6845 | 0 | Value |= op; |
6846 | | // op: R3 |
6847 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6848 | 0 | op &= UINT64_C(15); |
6849 | 0 | op <<= 12; |
6850 | 0 | Value |= op; |
6851 | 0 | break; |
6852 | 0 | } |
6853 | 0 | case SystemZ::ADTRA: |
6854 | 0 | case SystemZ::AXTRA: |
6855 | 0 | case SystemZ::CRDTE: |
6856 | 0 | case SystemZ::DDTRA: |
6857 | 0 | case SystemZ::DXTRA: |
6858 | 0 | case SystemZ::IDTE: |
6859 | 0 | case SystemZ::IPTE: |
6860 | 0 | case SystemZ::MDTRA: |
6861 | 0 | case SystemZ::MXTRA: |
6862 | 0 | case SystemZ::RDP: |
6863 | 0 | case SystemZ::SDTRA: |
6864 | 0 | case SystemZ::SXTRA: { |
6865 | | // op: R1 |
6866 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6867 | 0 | op &= UINT64_C(15); |
6868 | 0 | op <<= 4; |
6869 | 0 | Value |= op; |
6870 | | // op: R2 |
6871 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6872 | 0 | op &= UINT64_C(15); |
6873 | 0 | Value |= op; |
6874 | | // op: R3 |
6875 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6876 | 0 | op &= UINT64_C(15); |
6877 | 0 | op <<= 12; |
6878 | 0 | Value |= op; |
6879 | | // op: M4 |
6880 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
6881 | 0 | op &= UINT64_C(15); |
6882 | 0 | op <<= 8; |
6883 | 0 | Value |= op; |
6884 | 0 | break; |
6885 | 0 | } |
6886 | 0 | case SystemZ::DFLTCC: { |
6887 | | // op: R1 |
6888 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6889 | 0 | op &= UINT64_C(15); |
6890 | 0 | op <<= 4; |
6891 | 0 | Value |= op; |
6892 | | // op: R2 |
6893 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6894 | 0 | op &= UINT64_C(15); |
6895 | 0 | Value |= op; |
6896 | | // op: R3 |
6897 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6898 | 0 | op &= UINT64_C(15); |
6899 | 0 | op <<= 12; |
6900 | 0 | Value |= op; |
6901 | 0 | break; |
6902 | 0 | } |
6903 | 0 | case SystemZ::ADBR: |
6904 | 0 | case SystemZ::ADR: |
6905 | 0 | case SystemZ::AEBR: |
6906 | 0 | case SystemZ::AER: |
6907 | 0 | case SystemZ::AGFR: |
6908 | 0 | case SystemZ::AGR: |
6909 | 0 | case SystemZ::ALCGR: |
6910 | 0 | case SystemZ::ALCR: |
6911 | 0 | case SystemZ::ALGFR: |
6912 | 0 | case SystemZ::ALGR: |
6913 | 0 | case SystemZ::ALR: |
6914 | 0 | case SystemZ::AR: |
6915 | 0 | case SystemZ::AUR: |
6916 | 0 | case SystemZ::AWR: |
6917 | 0 | case SystemZ::AXBR: |
6918 | 0 | case SystemZ::AXR: |
6919 | 0 | case SystemZ::BCTGR: |
6920 | 0 | case SystemZ::BCTR: |
6921 | 0 | case SystemZ::CSP: |
6922 | 0 | case SystemZ::CSPG: |
6923 | 0 | case SystemZ::DDBR: |
6924 | 0 | case SystemZ::DDR: |
6925 | 0 | case SystemZ::DEBR: |
6926 | 0 | case SystemZ::DER: |
6927 | 0 | case SystemZ::DLGR: |
6928 | 0 | case SystemZ::DLR: |
6929 | 0 | case SystemZ::DR: |
6930 | 0 | case SystemZ::DSGFR: |
6931 | 0 | case SystemZ::DSGR: |
6932 | 0 | case SystemZ::DXBR: |
6933 | 0 | case SystemZ::DXR: |
6934 | 0 | case SystemZ::ISKE: |
6935 | 0 | case SystemZ::IVSK: |
6936 | 0 | case SystemZ::LOCFHRAsmE: |
6937 | 0 | case SystemZ::LOCFHRAsmH: |
6938 | 0 | case SystemZ::LOCFHRAsmHE: |
6939 | 0 | case SystemZ::LOCFHRAsmL: |
6940 | 0 | case SystemZ::LOCFHRAsmLE: |
6941 | 0 | case SystemZ::LOCFHRAsmLH: |
6942 | 0 | case SystemZ::LOCFHRAsmM: |
6943 | 0 | case SystemZ::LOCFHRAsmNE: |
6944 | 0 | case SystemZ::LOCFHRAsmNH: |
6945 | 0 | case SystemZ::LOCFHRAsmNHE: |
6946 | 0 | case SystemZ::LOCFHRAsmNL: |
6947 | 0 | case SystemZ::LOCFHRAsmNLE: |
6948 | 0 | case SystemZ::LOCFHRAsmNLH: |
6949 | 0 | case SystemZ::LOCFHRAsmNM: |
6950 | 0 | case SystemZ::LOCFHRAsmNO: |
6951 | 0 | case SystemZ::LOCFHRAsmNP: |
6952 | 0 | case SystemZ::LOCFHRAsmNZ: |
6953 | 0 | case SystemZ::LOCFHRAsmO: |
6954 | 0 | case SystemZ::LOCFHRAsmP: |
6955 | 0 | case SystemZ::LOCFHRAsmZ: |
6956 | 0 | case SystemZ::LOCGRAsmE: |
6957 | 0 | case SystemZ::LOCGRAsmH: |
6958 | 0 | case SystemZ::LOCGRAsmHE: |
6959 | 0 | case SystemZ::LOCGRAsmL: |
6960 | 0 | case SystemZ::LOCGRAsmLE: |
6961 | 0 | case SystemZ::LOCGRAsmLH: |
6962 | 0 | case SystemZ::LOCGRAsmM: |
6963 | 0 | case SystemZ::LOCGRAsmNE: |
6964 | 0 | case SystemZ::LOCGRAsmNH: |
6965 | 0 | case SystemZ::LOCGRAsmNHE: |
6966 | 0 | case SystemZ::LOCGRAsmNL: |
6967 | 0 | case SystemZ::LOCGRAsmNLE: |
6968 | 0 | case SystemZ::LOCGRAsmNLH: |
6969 | 0 | case SystemZ::LOCGRAsmNM: |
6970 | 0 | case SystemZ::LOCGRAsmNO: |
6971 | 0 | case SystemZ::LOCGRAsmNP: |
6972 | 0 | case SystemZ::LOCGRAsmNZ: |
6973 | 0 | case SystemZ::LOCGRAsmO: |
6974 | 0 | case SystemZ::LOCGRAsmP: |
6975 | 0 | case SystemZ::LOCGRAsmZ: |
6976 | 0 | case SystemZ::LOCRAsmE: |
6977 | 0 | case SystemZ::LOCRAsmH: |
6978 | 0 | case SystemZ::LOCRAsmHE: |
6979 | 0 | case SystemZ::LOCRAsmL: |
6980 | 0 | case SystemZ::LOCRAsmLE: |
6981 | 0 | case SystemZ::LOCRAsmLH: |
6982 | 0 | case SystemZ::LOCRAsmM: |
6983 | 0 | case SystemZ::LOCRAsmNE: |
6984 | 0 | case SystemZ::LOCRAsmNH: |
6985 | 0 | case SystemZ::LOCRAsmNHE: |
6986 | 0 | case SystemZ::LOCRAsmNL: |
6987 | 0 | case SystemZ::LOCRAsmNLE: |
6988 | 0 | case SystemZ::LOCRAsmNLH: |
6989 | 0 | case SystemZ::LOCRAsmNM: |
6990 | 0 | case SystemZ::LOCRAsmNO: |
6991 | 0 | case SystemZ::LOCRAsmNP: |
6992 | 0 | case SystemZ::LOCRAsmNZ: |
6993 | 0 | case SystemZ::LOCRAsmO: |
6994 | 0 | case SystemZ::LOCRAsmP: |
6995 | 0 | case SystemZ::LOCRAsmZ: |
6996 | 0 | case SystemZ::MDBR: |
6997 | 0 | case SystemZ::MDEBR: |
6998 | 0 | case SystemZ::MDER: |
6999 | 0 | case SystemZ::MDR: |
7000 | 0 | case SystemZ::MEEBR: |
7001 | 0 | case SystemZ::MEER: |
7002 | 0 | case SystemZ::MER: |
7003 | 0 | case SystemZ::MLGR: |
7004 | 0 | case SystemZ::MLR: |
7005 | 0 | case SystemZ::MR: |
7006 | 0 | case SystemZ::MSGFR: |
7007 | 0 | case SystemZ::MSGR: |
7008 | 0 | case SystemZ::MSR: |
7009 | 0 | case SystemZ::MXBR: |
7010 | 0 | case SystemZ::MXDBR: |
7011 | 0 | case SystemZ::MXDR: |
7012 | 0 | case SystemZ::MXR: |
7013 | 0 | case SystemZ::NGR: |
7014 | 0 | case SystemZ::NR: |
7015 | 0 | case SystemZ::OGR: |
7016 | 0 | case SystemZ::OR: |
7017 | 0 | case SystemZ::SDBR: |
7018 | 0 | case SystemZ::SDR: |
7019 | 0 | case SystemZ::SEBR: |
7020 | 0 | case SystemZ::SER: |
7021 | 0 | case SystemZ::SGFR: |
7022 | 0 | case SystemZ::SGR: |
7023 | 0 | case SystemZ::SLBGR: |
7024 | 0 | case SystemZ::SLBR: |
7025 | 0 | case SystemZ::SLGFR: |
7026 | 0 | case SystemZ::SLGR: |
7027 | 0 | case SystemZ::SLR: |
7028 | 0 | case SystemZ::SR: |
7029 | 0 | case SystemZ::SUR: |
7030 | 0 | case SystemZ::SWR: |
7031 | 0 | case SystemZ::SXBR: |
7032 | 0 | case SystemZ::SXR: |
7033 | 0 | case SystemZ::XGR: |
7034 | 0 | case SystemZ::XR: { |
7035 | | // op: R1 |
7036 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7037 | 0 | op &= UINT64_C(15); |
7038 | 0 | op <<= 4; |
7039 | 0 | Value |= op; |
7040 | | // op: R2 |
7041 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7042 | 0 | op &= UINT64_C(15); |
7043 | 0 | Value |= op; |
7044 | 0 | break; |
7045 | 0 | } |
7046 | 0 | case SystemZ::CFDBR: |
7047 | 0 | case SystemZ::CFDR: |
7048 | 0 | case SystemZ::CFEBR: |
7049 | 0 | case SystemZ::CFER: |
7050 | 0 | case SystemZ::CFXBR: |
7051 | 0 | case SystemZ::CFXR: |
7052 | 0 | case SystemZ::CGDBR: |
7053 | 0 | case SystemZ::CGDR: |
7054 | 0 | case SystemZ::CGDTR: |
7055 | 0 | case SystemZ::CGEBR: |
7056 | 0 | case SystemZ::CGER: |
7057 | 0 | case SystemZ::CGXBR: |
7058 | 0 | case SystemZ::CGXR: |
7059 | 0 | case SystemZ::CGXTR: |
7060 | 0 | case SystemZ::FIDBR: |
7061 | 0 | case SystemZ::FIEBR: |
7062 | 0 | case SystemZ::FIXBR: |
7063 | 0 | case SystemZ::TBDR: |
7064 | 0 | case SystemZ::TBEDR: { |
7065 | | // op: R1 |
7066 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7067 | 0 | op &= UINT64_C(15); |
7068 | 0 | op <<= 4; |
7069 | 0 | Value |= op; |
7070 | | // op: R2 |
7071 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7072 | 0 | op &= UINT64_C(15); |
7073 | 0 | Value |= op; |
7074 | | // op: M3 |
7075 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 1, Fixups, STI); |
7076 | 0 | op &= UINT64_C(15); |
7077 | 0 | op <<= 12; |
7078 | 0 | Value |= op; |
7079 | 0 | break; |
7080 | 0 | } |
7081 | 0 | case SystemZ::CDFBRA: |
7082 | 0 | case SystemZ::CDFTR: |
7083 | 0 | case SystemZ::CDGBRA: |
7084 | 0 | case SystemZ::CDGTRA: |
7085 | 0 | case SystemZ::CDLFBR: |
7086 | 0 | case SystemZ::CDLFTR: |
7087 | 0 | case SystemZ::CDLGBR: |
7088 | 0 | case SystemZ::CDLGTR: |
7089 | 0 | case SystemZ::CEFBRA: |
7090 | 0 | case SystemZ::CEGBRA: |
7091 | 0 | case SystemZ::CELFBR: |
7092 | 0 | case SystemZ::CELGBR: |
7093 | 0 | case SystemZ::CFDBRA: |
7094 | 0 | case SystemZ::CFDTR: |
7095 | 0 | case SystemZ::CFEBRA: |
7096 | 0 | case SystemZ::CFXBRA: |
7097 | 0 | case SystemZ::CFXTR: |
7098 | 0 | case SystemZ::CGDBRA: |
7099 | 0 | case SystemZ::CGDTRA: |
7100 | 0 | case SystemZ::CGEBRA: |
7101 | 0 | case SystemZ::CGXBRA: |
7102 | 0 | case SystemZ::CGXTRA: |
7103 | 0 | case SystemZ::CLFDBR: |
7104 | 0 | case SystemZ::CLFDTR: |
7105 | 0 | case SystemZ::CLFEBR: |
7106 | 0 | case SystemZ::CLFXBR: |
7107 | 0 | case SystemZ::CLFXTR: |
7108 | 0 | case SystemZ::CLGDBR: |
7109 | 0 | case SystemZ::CLGDTR: |
7110 | 0 | case SystemZ::CLGEBR: |
7111 | 0 | case SystemZ::CLGXBR: |
7112 | 0 | case SystemZ::CLGXTR: |
7113 | 0 | case SystemZ::CXFBRA: |
7114 | 0 | case SystemZ::CXFTR: |
7115 | 0 | case SystemZ::CXGBRA: |
7116 | 0 | case SystemZ::CXGTRA: |
7117 | 0 | case SystemZ::CXLFBR: |
7118 | 0 | case SystemZ::CXLFTR: |
7119 | 0 | case SystemZ::CXLGBR: |
7120 | 0 | case SystemZ::CXLGTR: |
7121 | 0 | case SystemZ::FIDBRA: |
7122 | 0 | case SystemZ::FIDTR: |
7123 | 0 | case SystemZ::FIEBRA: |
7124 | 0 | case SystemZ::FIXBRA: |
7125 | 0 | case SystemZ::FIXTR: |
7126 | 0 | case SystemZ::LDXBRA: |
7127 | 0 | case SystemZ::LDXTR: |
7128 | 0 | case SystemZ::LEDBRA: |
7129 | 0 | case SystemZ::LEDTR: |
7130 | 0 | case SystemZ::LEXBRA: { |
7131 | | // op: R1 |
7132 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7133 | 0 | op &= UINT64_C(15); |
7134 | 0 | op <<= 4; |
7135 | 0 | Value |= op; |
7136 | | // op: R2 |
7137 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7138 | 0 | op &= UINT64_C(15); |
7139 | 0 | Value |= op; |
7140 | | // op: M3 |
7141 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 1, Fixups, STI); |
7142 | 0 | op &= UINT64_C(15); |
7143 | 0 | op <<= 12; |
7144 | 0 | Value |= op; |
7145 | | // op: M4 |
7146 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
7147 | 0 | op &= UINT64_C(15); |
7148 | 0 | op <<= 8; |
7149 | 0 | Value |= op; |
7150 | 0 | break; |
7151 | 0 | } |
7152 | 0 | case SystemZ::LOCFHRAsm: |
7153 | 0 | case SystemZ::LOCGRAsm: |
7154 | 0 | case SystemZ::LOCRAsm: { |
7155 | | // op: R1 |
7156 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7157 | 0 | op &= UINT64_C(15); |
7158 | 0 | op <<= 4; |
7159 | 0 | Value |= op; |
7160 | | // op: R2 |
7161 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7162 | 0 | op &= UINT64_C(15); |
7163 | 0 | Value |= op; |
7164 | | // op: M3 |
7165 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
7166 | 0 | op &= UINT64_C(15); |
7167 | 0 | op <<= 12; |
7168 | 0 | Value |= op; |
7169 | 0 | break; |
7170 | 0 | } |
7171 | 0 | case SystemZ::LOCFHR: |
7172 | 0 | case SystemZ::LOCGR: |
7173 | 0 | case SystemZ::LOCR: { |
7174 | | // op: R1 |
7175 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7176 | 0 | op &= UINT64_C(15); |
7177 | 0 | op <<= 4; |
7178 | 0 | Value |= op; |
7179 | | // op: R2 |
7180 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7181 | 0 | op &= UINT64_C(15); |
7182 | 0 | Value |= op; |
7183 | | // op: M3 |
7184 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7185 | 0 | op &= UINT64_C(15); |
7186 | 0 | op <<= 12; |
7187 | 0 | Value |= op; |
7188 | 0 | break; |
7189 | 0 | } |
7190 | 0 | case SystemZ::SELFHRAsmE: |
7191 | 0 | case SystemZ::SELFHRAsmH: |
7192 | 0 | case SystemZ::SELFHRAsmHE: |
7193 | 0 | case SystemZ::SELFHRAsmL: |
7194 | 0 | case SystemZ::SELFHRAsmLE: |
7195 | 0 | case SystemZ::SELFHRAsmLH: |
7196 | 0 | case SystemZ::SELFHRAsmM: |
7197 | 0 | case SystemZ::SELFHRAsmNE: |
7198 | 0 | case SystemZ::SELFHRAsmNH: |
7199 | 0 | case SystemZ::SELFHRAsmNHE: |
7200 | 0 | case SystemZ::SELFHRAsmNL: |
7201 | 0 | case SystemZ::SELFHRAsmNLE: |
7202 | 0 | case SystemZ::SELFHRAsmNLH: |
7203 | 0 | case SystemZ::SELFHRAsmNM: |
7204 | 0 | case SystemZ::SELFHRAsmNO: |
7205 | 0 | case SystemZ::SELFHRAsmNP: |
7206 | 0 | case SystemZ::SELFHRAsmNZ: |
7207 | 0 | case SystemZ::SELFHRAsmO: |
7208 | 0 | case SystemZ::SELFHRAsmP: |
7209 | 0 | case SystemZ::SELFHRAsmZ: |
7210 | 0 | case SystemZ::SELGRAsmE: |
7211 | 0 | case SystemZ::SELGRAsmH: |
7212 | 0 | case SystemZ::SELGRAsmHE: |
7213 | 0 | case SystemZ::SELGRAsmL: |
7214 | 0 | case SystemZ::SELGRAsmLE: |
7215 | 0 | case SystemZ::SELGRAsmLH: |
7216 | 0 | case SystemZ::SELGRAsmM: |
7217 | 0 | case SystemZ::SELGRAsmNE: |
7218 | 0 | case SystemZ::SELGRAsmNH: |
7219 | 0 | case SystemZ::SELGRAsmNHE: |
7220 | 0 | case SystemZ::SELGRAsmNL: |
7221 | 0 | case SystemZ::SELGRAsmNLE: |
7222 | 0 | case SystemZ::SELGRAsmNLH: |
7223 | 0 | case SystemZ::SELGRAsmNM: |
7224 | 0 | case SystemZ::SELGRAsmNO: |
7225 | 0 | case SystemZ::SELGRAsmNP: |
7226 | 0 | case SystemZ::SELGRAsmNZ: |
7227 | 0 | case SystemZ::SELGRAsmO: |
7228 | 0 | case SystemZ::SELGRAsmP: |
7229 | 0 | case SystemZ::SELGRAsmZ: |
7230 | 0 | case SystemZ::SELRAsmE: |
7231 | 0 | case SystemZ::SELRAsmH: |
7232 | 0 | case SystemZ::SELRAsmHE: |
7233 | 0 | case SystemZ::SELRAsmL: |
7234 | 0 | case SystemZ::SELRAsmLE: |
7235 | 0 | case SystemZ::SELRAsmLH: |
7236 | 0 | case SystemZ::SELRAsmM: |
7237 | 0 | case SystemZ::SELRAsmNE: |
7238 | 0 | case SystemZ::SELRAsmNH: |
7239 | 0 | case SystemZ::SELRAsmNHE: |
7240 | 0 | case SystemZ::SELRAsmNL: |
7241 | 0 | case SystemZ::SELRAsmNLE: |
7242 | 0 | case SystemZ::SELRAsmNLH: |
7243 | 0 | case SystemZ::SELRAsmNM: |
7244 | 0 | case SystemZ::SELRAsmNO: |
7245 | 0 | case SystemZ::SELRAsmNP: |
7246 | 0 | case SystemZ::SELRAsmNZ: |
7247 | 0 | case SystemZ::SELRAsmO: |
7248 | 0 | case SystemZ::SELRAsmP: |
7249 | 0 | case SystemZ::SELRAsmZ: { |
7250 | | // op: R1 |
7251 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7252 | 0 | op &= UINT64_C(15); |
7253 | 0 | op <<= 4; |
7254 | 0 | Value |= op; |
7255 | | // op: R2 |
7256 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7257 | 0 | op &= UINT64_C(15); |
7258 | 0 | Value |= op; |
7259 | | // op: R3 |
7260 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7261 | 0 | op &= UINT64_C(15); |
7262 | 0 | op <<= 12; |
7263 | 0 | Value |= op; |
7264 | 0 | break; |
7265 | 0 | } |
7266 | 0 | case SystemZ::SELFHRAsm: |
7267 | 0 | case SystemZ::SELGRAsm: |
7268 | 0 | case SystemZ::SELRAsm: { |
7269 | | // op: R1 |
7270 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7271 | 0 | op &= UINT64_C(15); |
7272 | 0 | op <<= 4; |
7273 | 0 | Value |= op; |
7274 | | // op: R2 |
7275 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7276 | 0 | op &= UINT64_C(15); |
7277 | 0 | Value |= op; |
7278 | | // op: R3 |
7279 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7280 | 0 | op &= UINT64_C(15); |
7281 | 0 | op <<= 12; |
7282 | 0 | Value |= op; |
7283 | | // op: M4 |
7284 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
7285 | 0 | op &= UINT64_C(15); |
7286 | 0 | op <<= 8; |
7287 | 0 | Value |= op; |
7288 | 0 | break; |
7289 | 0 | } |
7290 | 0 | case SystemZ::SELFHR: |
7291 | 0 | case SystemZ::SELGR: |
7292 | 0 | case SystemZ::SELR: { |
7293 | | // op: R1 |
7294 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7295 | 0 | op &= UINT64_C(15); |
7296 | 0 | op <<= 4; |
7297 | 0 | Value |= op; |
7298 | | // op: R2 |
7299 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7300 | 0 | op &= UINT64_C(15); |
7301 | 0 | Value |= op; |
7302 | | // op: R3 |
7303 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7304 | 0 | op &= UINT64_C(15); |
7305 | 0 | op <<= 12; |
7306 | 0 | Value |= op; |
7307 | | // op: M4 |
7308 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7309 | 0 | op &= UINT64_C(15); |
7310 | 0 | op <<= 8; |
7311 | 0 | Value |= op; |
7312 | 0 | break; |
7313 | 0 | } |
7314 | 0 | case SystemZ::DIDBR: |
7315 | 0 | case SystemZ::DIEBR: |
7316 | 0 | case SystemZ::LPTEA: |
7317 | 0 | case SystemZ::QADTR: |
7318 | 0 | case SystemZ::QAXTR: |
7319 | 0 | case SystemZ::RRDTR: |
7320 | 0 | case SystemZ::RRXTR: { |
7321 | | // op: R1 |
7322 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7323 | 0 | op &= UINT64_C(15); |
7324 | 0 | op <<= 4; |
7325 | 0 | Value |= op; |
7326 | | // op: R2 |
7327 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7328 | 0 | op &= UINT64_C(15); |
7329 | 0 | Value |= op; |
7330 | | // op: R3 |
7331 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7332 | 0 | op &= UINT64_C(15); |
7333 | 0 | op <<= 12; |
7334 | 0 | Value |= op; |
7335 | | // op: M4 |
7336 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
7337 | 0 | op &= UINT64_C(15); |
7338 | 0 | op <<= 8; |
7339 | 0 | Value |= op; |
7340 | 0 | break; |
7341 | 0 | } |
7342 | 0 | case SystemZ::InsnRXF: { |
7343 | | // op: R1 |
7344 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7345 | 0 | op &= UINT64_C(15); |
7346 | 0 | op <<= 12; |
7347 | 0 | Value |= op; |
7348 | | // op: R3 |
7349 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7350 | 0 | op &= UINT64_C(15); |
7351 | 0 | op <<= 36; |
7352 | 0 | Value |= op; |
7353 | | // op: X2 |
7354 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
7355 | 0 | op &= UINT64_C(15); |
7356 | 0 | op <<= 32; |
7357 | 0 | Value |= op; |
7358 | | // op: B2 |
7359 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7360 | 0 | op &= UINT64_C(15); |
7361 | 0 | op <<= 28; |
7362 | 0 | Value |= op; |
7363 | | // op: D2 |
7364 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
7365 | 0 | op &= UINT64_C(4095); |
7366 | 0 | op <<= 16; |
7367 | 0 | Value |= op; |
7368 | | // op: enc |
7369 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7370 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7371 | 0 | Value |= (op & UINT64_C(255)); |
7372 | 0 | break; |
7373 | 0 | } |
7374 | 0 | case SystemZ::InsnRI: { |
7375 | | // op: R1 |
7376 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7377 | 0 | op &= UINT64_C(15); |
7378 | 0 | op <<= 20; |
7379 | 0 | Value |= op; |
7380 | | // op: I2 |
7381 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
7382 | 0 | op &= UINT64_C(65535); |
7383 | 0 | Value |= op; |
7384 | | // op: enc |
7385 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
7386 | 0 | Value |= (op & UINT64_C(4278190080)); |
7387 | 0 | Value |= (op & UINT64_C(983040)); |
7388 | 0 | break; |
7389 | 0 | } |
7390 | 0 | case SystemZ::InsnRS: { |
7391 | | // op: R1 |
7392 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7393 | 0 | op &= UINT64_C(15); |
7394 | 0 | op <<= 20; |
7395 | 0 | Value |= op; |
7396 | | // op: R3 |
7397 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7398 | 0 | op &= UINT64_C(15); |
7399 | 0 | op <<= 16; |
7400 | 0 | Value |= op; |
7401 | | // op: B2 |
7402 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7403 | 0 | op &= UINT64_C(15); |
7404 | 0 | op <<= 12; |
7405 | 0 | Value |= op; |
7406 | | // op: D2 |
7407 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
7408 | 0 | op &= UINT64_C(4095); |
7409 | 0 | Value |= op; |
7410 | | // op: enc |
7411 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
7412 | 0 | op &= UINT64_C(4278190080); |
7413 | 0 | Value |= op; |
7414 | 0 | break; |
7415 | 0 | } |
7416 | 0 | case SystemZ::InsnRSI: { |
7417 | | // op: R1 |
7418 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7419 | 0 | op &= UINT64_C(15); |
7420 | 0 | op <<= 20; |
7421 | 0 | Value |= op; |
7422 | | // op: R3 |
7423 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7424 | 0 | op &= UINT64_C(15); |
7425 | 0 | op <<= 16; |
7426 | 0 | Value |= op; |
7427 | | // op: RI2 |
7428 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
7429 | 0 | op &= UINT64_C(65535); |
7430 | 0 | Value |= op; |
7431 | | // op: enc |
7432 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7433 | 0 | op &= UINT64_C(4278190080); |
7434 | 0 | Value |= op; |
7435 | 0 | break; |
7436 | 0 | } |
7437 | 0 | case SystemZ::InsnRX: { |
7438 | | // op: R1 |
7439 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7440 | 0 | op &= UINT64_C(15); |
7441 | 0 | op <<= 20; |
7442 | 0 | Value |= op; |
7443 | | // op: X2 |
7444 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7445 | 0 | op &= UINT64_C(15); |
7446 | 0 | op <<= 16; |
7447 | 0 | Value |= op; |
7448 | | // op: B2 |
7449 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7450 | 0 | op &= UINT64_C(15); |
7451 | 0 | op <<= 12; |
7452 | 0 | Value |= op; |
7453 | | // op: D2 |
7454 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
7455 | 0 | op &= UINT64_C(4095); |
7456 | 0 | Value |= op; |
7457 | | // op: enc |
7458 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
7459 | 0 | op &= UINT64_C(4278190080); |
7460 | 0 | Value |= op; |
7461 | 0 | break; |
7462 | 0 | } |
7463 | 0 | case SystemZ::InsnVRS: { |
7464 | | // op: R1 |
7465 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7466 | 0 | op &= UINT64_C(15); |
7467 | 0 | op <<= 36; |
7468 | 0 | Value |= op; |
7469 | | // op: B2 |
7470 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7471 | 0 | op &= UINT64_C(15); |
7472 | 0 | op <<= 28; |
7473 | 0 | Value |= op; |
7474 | | // op: D2 |
7475 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
7476 | 0 | op &= UINT64_C(4095); |
7477 | 0 | op <<= 16; |
7478 | 0 | Value |= op; |
7479 | | // op: V3 |
7480 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7481 | 0 | Value |= (op & UINT64_C(15)) << 32; |
7482 | 0 | Value |= (op & UINT64_C(16)) << 6; |
7483 | | // op: M4 |
7484 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
7485 | 0 | op &= UINT64_C(15); |
7486 | 0 | op <<= 12; |
7487 | 0 | Value |= op; |
7488 | | // op: enc |
7489 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7490 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7491 | 0 | Value |= (op & UINT64_C(255)); |
7492 | 0 | break; |
7493 | 0 | } |
7494 | 0 | case SystemZ::InsnRIS: { |
7495 | | // op: R1 |
7496 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7497 | 0 | op &= UINT64_C(15); |
7498 | 0 | op <<= 36; |
7499 | 0 | Value |= op; |
7500 | | // op: I2 |
7501 | 0 | op = getImmOpValue<SystemZ::FK_390_S8Imm>(MI, 2, Fixups, STI); |
7502 | 0 | op &= UINT64_C(255); |
7503 | 0 | op <<= 8; |
7504 | 0 | Value |= op; |
7505 | | // op: M3 |
7506 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
7507 | 0 | op &= UINT64_C(15); |
7508 | 0 | op <<= 32; |
7509 | 0 | Value |= op; |
7510 | | // op: B4 |
7511 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7512 | 0 | op &= UINT64_C(15); |
7513 | 0 | op <<= 28; |
7514 | 0 | Value |= op; |
7515 | | // op: D4 |
7516 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 5, Fixups, STI); |
7517 | 0 | op &= UINT64_C(4095); |
7518 | 0 | op <<= 16; |
7519 | 0 | Value |= op; |
7520 | | // op: enc |
7521 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7522 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7523 | 0 | Value |= (op & UINT64_C(255)); |
7524 | 0 | break; |
7525 | 0 | } |
7526 | 0 | case SystemZ::InsnRILU: { |
7527 | | // op: R1 |
7528 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7529 | 0 | op &= UINT64_C(15); |
7530 | 0 | op <<= 36; |
7531 | 0 | Value |= op; |
7532 | | // op: I2 |
7533 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 2, Fixups, STI); |
7534 | 0 | op &= UINT64_C(4294967295); |
7535 | 0 | Value |= op; |
7536 | | // op: enc |
7537 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7538 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7539 | 0 | Value |= (op & UINT64_C(64424509440)); |
7540 | 0 | break; |
7541 | 0 | } |
7542 | 0 | case SystemZ::InsnRIL: { |
7543 | | // op: R1 |
7544 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7545 | 0 | op &= UINT64_C(15); |
7546 | 0 | op <<= 36; |
7547 | 0 | Value |= op; |
7548 | | // op: I2 |
7549 | 0 | op = getPC32DBLEncoding(MI, 2, Fixups, STI); |
7550 | 0 | op &= UINT64_C(4294967295); |
7551 | 0 | Value |= op; |
7552 | | // op: enc |
7553 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7554 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7555 | 0 | Value |= (op & UINT64_C(64424509440)); |
7556 | 0 | break; |
7557 | 0 | } |
7558 | 0 | case SystemZ::InsnRRS: { |
7559 | | // op: R1 |
7560 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7561 | 0 | op &= UINT64_C(15); |
7562 | 0 | op <<= 36; |
7563 | 0 | Value |= op; |
7564 | | // op: R2 |
7565 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7566 | 0 | op &= UINT64_C(15); |
7567 | 0 | op <<= 32; |
7568 | 0 | Value |= op; |
7569 | | // op: M3 |
7570 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
7571 | 0 | op &= UINT64_C(15); |
7572 | 0 | op <<= 12; |
7573 | 0 | Value |= op; |
7574 | | // op: B4 |
7575 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7576 | 0 | op &= UINT64_C(15); |
7577 | 0 | op <<= 28; |
7578 | 0 | Value |= op; |
7579 | | // op: D4 |
7580 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 5, Fixups, STI); |
7581 | 0 | op &= UINT64_C(4095); |
7582 | 0 | op <<= 16; |
7583 | 0 | Value |= op; |
7584 | | // op: enc |
7585 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7586 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7587 | 0 | Value |= (op & UINT64_C(255)); |
7588 | 0 | break; |
7589 | 0 | } |
7590 | 0 | case SystemZ::InsnRSY: { |
7591 | | // op: R1 |
7592 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7593 | 0 | op &= UINT64_C(15); |
7594 | 0 | op <<= 36; |
7595 | 0 | Value |= op; |
7596 | | // op: R3 |
7597 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7598 | 0 | op &= UINT64_C(15); |
7599 | 0 | op <<= 32; |
7600 | 0 | Value |= op; |
7601 | | // op: B2 |
7602 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7603 | 0 | op &= UINT64_C(15); |
7604 | 0 | op <<= 28; |
7605 | 0 | Value |= op; |
7606 | | // op: D2 |
7607 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 4, Fixups, STI); |
7608 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
7609 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
7610 | | // op: enc |
7611 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7612 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7613 | 0 | Value |= (op & UINT64_C(255)); |
7614 | 0 | break; |
7615 | 0 | } |
7616 | 0 | case SystemZ::InsnRSE: { |
7617 | | // op: R1 |
7618 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7619 | 0 | op &= UINT64_C(15); |
7620 | 0 | op <<= 36; |
7621 | 0 | Value |= op; |
7622 | | // op: R3 |
7623 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7624 | 0 | op &= UINT64_C(15); |
7625 | 0 | op <<= 32; |
7626 | 0 | Value |= op; |
7627 | | // op: B2 |
7628 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7629 | 0 | op &= UINT64_C(15); |
7630 | 0 | op <<= 28; |
7631 | 0 | Value |= op; |
7632 | | // op: D2 |
7633 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
7634 | 0 | op &= UINT64_C(4095); |
7635 | 0 | op <<= 16; |
7636 | 0 | Value |= op; |
7637 | | // op: enc |
7638 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7639 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7640 | 0 | Value |= (op & UINT64_C(255)); |
7641 | 0 | break; |
7642 | 0 | } |
7643 | 0 | case SystemZ::InsnRIE: { |
7644 | | // op: R1 |
7645 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7646 | 0 | op &= UINT64_C(15); |
7647 | 0 | op <<= 36; |
7648 | 0 | Value |= op; |
7649 | | // op: R3 |
7650 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7651 | 0 | op &= UINT64_C(15); |
7652 | 0 | op <<= 32; |
7653 | 0 | Value |= op; |
7654 | | // op: I2 |
7655 | 0 | op = getPC16DBLEncoding(MI, 3, Fixups, STI); |
7656 | 0 | op &= UINT64_C(65535); |
7657 | 0 | op <<= 16; |
7658 | 0 | Value |= op; |
7659 | | // op: enc |
7660 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7661 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7662 | 0 | Value |= (op & UINT64_C(255)); |
7663 | 0 | break; |
7664 | 0 | } |
7665 | 0 | case SystemZ::InsnRXY: { |
7666 | | // op: R1 |
7667 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7668 | 0 | op &= UINT64_C(15); |
7669 | 0 | op <<= 36; |
7670 | 0 | Value |= op; |
7671 | | // op: X2 |
7672 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7673 | 0 | op &= UINT64_C(15); |
7674 | 0 | op <<= 32; |
7675 | 0 | Value |= op; |
7676 | | // op: B2 |
7677 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7678 | 0 | op &= UINT64_C(15); |
7679 | 0 | op <<= 28; |
7680 | 0 | Value |= op; |
7681 | | // op: D2 |
7682 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 3, Fixups, STI); |
7683 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
7684 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
7685 | | // op: enc |
7686 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7687 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7688 | 0 | Value |= (op & UINT64_C(255)); |
7689 | 0 | break; |
7690 | 0 | } |
7691 | 0 | case SystemZ::InsnRXE: { |
7692 | | // op: R1 |
7693 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7694 | 0 | op &= UINT64_C(15); |
7695 | 0 | op <<= 36; |
7696 | 0 | Value |= op; |
7697 | | // op: X2 |
7698 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7699 | 0 | op &= UINT64_C(15); |
7700 | 0 | op <<= 32; |
7701 | 0 | Value |= op; |
7702 | | // op: B2 |
7703 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7704 | 0 | op &= UINT64_C(15); |
7705 | 0 | op <<= 28; |
7706 | 0 | Value |= op; |
7707 | | // op: D2 |
7708 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
7709 | 0 | op &= UINT64_C(4095); |
7710 | 0 | op <<= 16; |
7711 | 0 | Value |= op; |
7712 | | // op: enc |
7713 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7714 | 0 | Value |= (op & UINT64_C(280375465082880)); |
7715 | 0 | Value |= (op & UINT64_C(255)); |
7716 | 0 | break; |
7717 | 0 | } |
7718 | 0 | case SystemZ::KDSA: |
7719 | 0 | case SystemZ::KIMD: |
7720 | 0 | case SystemZ::KLMD: |
7721 | 0 | case SystemZ::KMAC: |
7722 | 0 | case SystemZ::PFMF: |
7723 | 0 | case SystemZ::TRTEOpt: |
7724 | 0 | case SystemZ::TRTREOpt: { |
7725 | | // op: R1 |
7726 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7727 | 0 | op &= UINT64_C(15); |
7728 | 0 | op <<= 4; |
7729 | 0 | Value |= op; |
7730 | | // op: R2 |
7731 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7732 | 0 | op &= UINT64_C(15); |
7733 | 0 | Value |= op; |
7734 | 0 | break; |
7735 | 0 | } |
7736 | 0 | case SystemZ::TRTE: |
7737 | 0 | case SystemZ::TRTRE: { |
7738 | | // op: R1 |
7739 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7740 | 0 | op &= UINT64_C(15); |
7741 | 0 | op <<= 4; |
7742 | 0 | Value |= op; |
7743 | | // op: R2 |
7744 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7745 | 0 | op &= UINT64_C(15); |
7746 | 0 | Value |= op; |
7747 | | // op: M3 |
7748 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
7749 | 0 | op &= UINT64_C(15); |
7750 | 0 | op <<= 12; |
7751 | 0 | Value |= op; |
7752 | 0 | break; |
7753 | 0 | } |
7754 | 0 | case SystemZ::BCR: { |
7755 | | // op: R1 |
7756 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7757 | 0 | op &= UINT64_C(15); |
7758 | 0 | op <<= 4; |
7759 | 0 | Value |= op; |
7760 | | // op: R2 |
7761 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7762 | 0 | op &= UINT64_C(15); |
7763 | 0 | Value |= op; |
7764 | 0 | break; |
7765 | 0 | } |
7766 | 0 | case SystemZ::InsnRRF: { |
7767 | | // op: R1 |
7768 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7769 | 0 | op &= UINT64_C(15); |
7770 | 0 | op <<= 4; |
7771 | 0 | Value |= op; |
7772 | | // op: R2 |
7773 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7774 | 0 | op &= UINT64_C(15); |
7775 | 0 | Value |= op; |
7776 | | // op: R3 |
7777 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7778 | 0 | op &= UINT64_C(15); |
7779 | 0 | op <<= 12; |
7780 | 0 | Value |= op; |
7781 | | // op: M4 |
7782 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
7783 | 0 | op &= UINT64_C(15); |
7784 | 0 | op <<= 8; |
7785 | 0 | Value |= op; |
7786 | | // op: enc |
7787 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
7788 | 0 | op &= UINT64_C(4294901760); |
7789 | 0 | Value |= op; |
7790 | 0 | break; |
7791 | 0 | } |
7792 | 0 | case SystemZ::InsnRR: { |
7793 | | // op: R1 |
7794 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7795 | 0 | op &= UINT64_C(15); |
7796 | 0 | op <<= 4; |
7797 | 0 | Value |= op; |
7798 | | // op: R2 |
7799 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7800 | 0 | op &= UINT64_C(15); |
7801 | 0 | Value |= op; |
7802 | | // op: enc |
7803 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 0, Fixups, STI); |
7804 | 0 | op &= UINT64_C(65280); |
7805 | 0 | Value |= op; |
7806 | 0 | break; |
7807 | 0 | } |
7808 | 0 | case SystemZ::InsnRRE: { |
7809 | | // op: R1 |
7810 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7811 | 0 | op &= UINT64_C(15); |
7812 | 0 | op <<= 4; |
7813 | 0 | Value |= op; |
7814 | | // op: R2 |
7815 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7816 | 0 | op &= UINT64_C(15); |
7817 | 0 | Value |= op; |
7818 | | // op: enc |
7819 | 0 | op = getImmOpValue<SystemZ::FK_390_U32Imm>(MI, 0, Fixups, STI); |
7820 | 0 | op &= UINT64_C(4294901760); |
7821 | 0 | Value |= op; |
7822 | 0 | break; |
7823 | 0 | } |
7824 | 0 | case SystemZ::MVCK: |
7825 | 0 | case SystemZ::MVCP: |
7826 | 0 | case SystemZ::MVCS: { |
7827 | | // op: R1 |
7828 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7829 | 0 | op &= UINT64_C(15); |
7830 | 0 | op <<= 36; |
7831 | 0 | Value |= op; |
7832 | | // op: B1 |
7833 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7834 | 0 | op &= UINT64_C(15); |
7835 | 0 | op <<= 28; |
7836 | 0 | Value |= op; |
7837 | | // op: D1 |
7838 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
7839 | 0 | op &= UINT64_C(4095); |
7840 | 0 | op <<= 16; |
7841 | 0 | Value |= op; |
7842 | | // op: B2 |
7843 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7844 | 0 | op &= UINT64_C(15); |
7845 | 0 | op <<= 12; |
7846 | 0 | Value |= op; |
7847 | | // op: D2 |
7848 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
7849 | 0 | op &= UINT64_C(4095); |
7850 | 0 | Value |= op; |
7851 | | // op: R3 |
7852 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
7853 | 0 | op &= UINT64_C(15); |
7854 | 0 | op <<= 32; |
7855 | 0 | Value |= op; |
7856 | 0 | break; |
7857 | 0 | } |
7858 | 0 | case SystemZ::InsnSS: { |
7859 | | // op: R1 |
7860 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7861 | 0 | op &= UINT64_C(15); |
7862 | 0 | op <<= 36; |
7863 | 0 | Value |= op; |
7864 | | // op: B1 |
7865 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7866 | 0 | op &= UINT64_C(15); |
7867 | 0 | op <<= 28; |
7868 | 0 | Value |= op; |
7869 | | // op: D1 |
7870 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
7871 | 0 | op &= UINT64_C(4095); |
7872 | 0 | op <<= 16; |
7873 | 0 | Value |= op; |
7874 | | // op: B2 |
7875 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7876 | 0 | op &= UINT64_C(15); |
7877 | 0 | op <<= 12; |
7878 | 0 | Value |= op; |
7879 | | // op: D2 |
7880 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 5, Fixups, STI); |
7881 | 0 | op &= UINT64_C(4095); |
7882 | 0 | Value |= op; |
7883 | | // op: R3 |
7884 | 0 | op = getMachineOpValue(MI, MI.getOperand(6), Fixups, STI); |
7885 | 0 | op &= UINT64_C(15); |
7886 | 0 | op <<= 32; |
7887 | 0 | Value |= op; |
7888 | | // op: enc |
7889 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
7890 | 0 | op &= UINT64_C(280375465082880); |
7891 | 0 | Value |= op; |
7892 | 0 | break; |
7893 | 0 | } |
7894 | 0 | case SystemZ::BR: |
7895 | 0 | case SystemZ::BRAsmE: |
7896 | 0 | case SystemZ::BRAsmH: |
7897 | 0 | case SystemZ::BRAsmHE: |
7898 | 0 | case SystemZ::BRAsmL: |
7899 | 0 | case SystemZ::BRAsmLE: |
7900 | 0 | case SystemZ::BRAsmLH: |
7901 | 0 | case SystemZ::BRAsmM: |
7902 | 0 | case SystemZ::BRAsmNE: |
7903 | 0 | case SystemZ::BRAsmNH: |
7904 | 0 | case SystemZ::BRAsmNHE: |
7905 | 0 | case SystemZ::BRAsmNL: |
7906 | 0 | case SystemZ::BRAsmNLE: |
7907 | 0 | case SystemZ::BRAsmNLH: |
7908 | 0 | case SystemZ::BRAsmNM: |
7909 | 0 | case SystemZ::BRAsmNO: |
7910 | 0 | case SystemZ::BRAsmNP: |
7911 | 0 | case SystemZ::BRAsmNZ: |
7912 | 0 | case SystemZ::BRAsmO: |
7913 | 0 | case SystemZ::BRAsmP: |
7914 | 0 | case SystemZ::BRAsmZ: { |
7915 | | // op: R2 |
7916 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7917 | 0 | op &= UINT64_C(15); |
7918 | 0 | Value |= op; |
7919 | 0 | break; |
7920 | 0 | } |
7921 | 0 | case SystemZ::J: |
7922 | 0 | case SystemZ::JAsmE: |
7923 | 0 | case SystemZ::JAsmH: |
7924 | 0 | case SystemZ::JAsmHE: |
7925 | 0 | case SystemZ::JAsmL: |
7926 | 0 | case SystemZ::JAsmLE: |
7927 | 0 | case SystemZ::JAsmLH: |
7928 | 0 | case SystemZ::JAsmM: |
7929 | 0 | case SystemZ::JAsmNE: |
7930 | 0 | case SystemZ::JAsmNH: |
7931 | 0 | case SystemZ::JAsmNHE: |
7932 | 0 | case SystemZ::JAsmNL: |
7933 | 0 | case SystemZ::JAsmNLE: |
7934 | 0 | case SystemZ::JAsmNLH: |
7935 | 0 | case SystemZ::JAsmNM: |
7936 | 0 | case SystemZ::JAsmNO: |
7937 | 0 | case SystemZ::JAsmNP: |
7938 | 0 | case SystemZ::JAsmNZ: |
7939 | 0 | case SystemZ::JAsmO: |
7940 | 0 | case SystemZ::JAsmP: |
7941 | 0 | case SystemZ::JAsmZ: { |
7942 | | // op: RI2 |
7943 | 0 | op = getPC16DBLEncoding(MI, 0, Fixups, STI); |
7944 | 0 | op &= UINT64_C(65535); |
7945 | 0 | Value |= op; |
7946 | 0 | break; |
7947 | 0 | } |
7948 | 0 | case SystemZ::JG: |
7949 | 0 | case SystemZ::JGAsmE: |
7950 | 0 | case SystemZ::JGAsmH: |
7951 | 0 | case SystemZ::JGAsmHE: |
7952 | 0 | case SystemZ::JGAsmL: |
7953 | 0 | case SystemZ::JGAsmLE: |
7954 | 0 | case SystemZ::JGAsmLH: |
7955 | 0 | case SystemZ::JGAsmM: |
7956 | 0 | case SystemZ::JGAsmNE: |
7957 | 0 | case SystemZ::JGAsmNH: |
7958 | 0 | case SystemZ::JGAsmNHE: |
7959 | 0 | case SystemZ::JGAsmNL: |
7960 | 0 | case SystemZ::JGAsmNLE: |
7961 | 0 | case SystemZ::JGAsmNLH: |
7962 | 0 | case SystemZ::JGAsmNM: |
7963 | 0 | case SystemZ::JGAsmNO: |
7964 | 0 | case SystemZ::JGAsmNP: |
7965 | 0 | case SystemZ::JGAsmNZ: |
7966 | 0 | case SystemZ::JGAsmO: |
7967 | 0 | case SystemZ::JGAsmP: |
7968 | 0 | case SystemZ::JGAsmZ: { |
7969 | | // op: RI2 |
7970 | 0 | op = getPC32DBLEncoding(MI, 0, Fixups, STI); |
7971 | 0 | op &= UINT64_C(4294967295); |
7972 | 0 | Value |= op; |
7973 | 0 | break; |
7974 | 0 | } |
7975 | 0 | case SystemZ::VLRL: |
7976 | 0 | case SystemZ::VPKZ: |
7977 | 0 | case SystemZ::VSTRL: |
7978 | 0 | case SystemZ::VUPKZ: { |
7979 | | // op: V1 |
7980 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7981 | 0 | Value |= (op & UINT64_C(15)) << 12; |
7982 | 0 | Value |= (op & UINT64_C(16)) << 4; |
7983 | | // op: B2 |
7984 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7985 | 0 | op &= UINT64_C(15); |
7986 | 0 | op <<= 28; |
7987 | 0 | Value |= op; |
7988 | | // op: D2 |
7989 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
7990 | 0 | op &= UINT64_C(4095); |
7991 | 0 | op <<= 16; |
7992 | 0 | Value |= op; |
7993 | | // op: I3 |
7994 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
7995 | 0 | op &= UINT64_C(255); |
7996 | 0 | op <<= 32; |
7997 | 0 | Value |= op; |
7998 | 0 | break; |
7999 | 0 | } |
8000 | 0 | case SystemZ::VLRLR: |
8001 | 0 | case SystemZ::VSTRLR: { |
8002 | | // op: V1 |
8003 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8004 | 0 | Value |= (op & UINT64_C(15)) << 12; |
8005 | 0 | Value |= (op & UINT64_C(16)) << 4; |
8006 | | // op: B2 |
8007 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8008 | 0 | op &= UINT64_C(15); |
8009 | 0 | op <<= 28; |
8010 | 0 | Value |= op; |
8011 | | // op: D2 |
8012 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
8013 | 0 | op &= UINT64_C(4095); |
8014 | 0 | op <<= 16; |
8015 | 0 | Value |= op; |
8016 | | // op: R3 |
8017 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8018 | 0 | op &= UINT64_C(15); |
8019 | 0 | op <<= 32; |
8020 | 0 | Value |= op; |
8021 | 0 | break; |
8022 | 0 | } |
8023 | 0 | case SystemZ::VTP: { |
8024 | | // op: V1 |
8025 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8026 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8027 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8028 | 0 | break; |
8029 | 0 | } |
8030 | 0 | case SystemZ::VCP: { |
8031 | | // op: V1 |
8032 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8033 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8034 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8035 | | // op: V2 |
8036 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8037 | 0 | Value |= (op & UINT64_C(15)) << 28; |
8038 | 0 | Value |= (op & UINT64_C(16)) << 5; |
8039 | | // op: M3 |
8040 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8041 | 0 | op &= UINT64_C(15); |
8042 | 0 | op <<= 20; |
8043 | 0 | Value |= op; |
8044 | 0 | break; |
8045 | 0 | } |
8046 | 0 | case SystemZ::VONE: |
8047 | 0 | case SystemZ::VZERO: { |
8048 | | // op: V1 |
8049 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8050 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8051 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8052 | 0 | break; |
8053 | 0 | } |
8054 | 0 | case SystemZ::VLL: |
8055 | 0 | case SystemZ::VSTL: { |
8056 | | // op: V1 |
8057 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8058 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8059 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8060 | | // op: B2 |
8061 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8062 | 0 | op &= UINT64_C(15); |
8063 | 0 | op <<= 28; |
8064 | 0 | Value |= op; |
8065 | | // op: D2 |
8066 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
8067 | 0 | op &= UINT64_C(4095); |
8068 | 0 | op <<= 16; |
8069 | 0 | Value |= op; |
8070 | | // op: R3 |
8071 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8072 | 0 | op &= UINT64_C(15); |
8073 | 0 | op <<= 32; |
8074 | 0 | Value |= op; |
8075 | 0 | break; |
8076 | 0 | } |
8077 | 0 | case SystemZ::VERLLB: |
8078 | 0 | case SystemZ::VERLLF: |
8079 | 0 | case SystemZ::VERLLG: |
8080 | 0 | case SystemZ::VERLLH: |
8081 | 0 | case SystemZ::VESLB: |
8082 | 0 | case SystemZ::VESLF: |
8083 | 0 | case SystemZ::VESLG: |
8084 | 0 | case SystemZ::VESLH: |
8085 | 0 | case SystemZ::VESRAB: |
8086 | 0 | case SystemZ::VESRAF: |
8087 | 0 | case SystemZ::VESRAG: |
8088 | 0 | case SystemZ::VESRAH: |
8089 | 0 | case SystemZ::VESRLB: |
8090 | 0 | case SystemZ::VESRLF: |
8091 | 0 | case SystemZ::VESRLG: |
8092 | 0 | case SystemZ::VESRLH: |
8093 | 0 | case SystemZ::VLM: |
8094 | 0 | case SystemZ::VSTM: { |
8095 | | // op: V1 |
8096 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8097 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8098 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8099 | | // op: B2 |
8100 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8101 | 0 | op &= UINT64_C(15); |
8102 | 0 | op <<= 28; |
8103 | 0 | Value |= op; |
8104 | | // op: D2 |
8105 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
8106 | 0 | op &= UINT64_C(4095); |
8107 | 0 | op <<= 16; |
8108 | 0 | Value |= op; |
8109 | | // op: V3 |
8110 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8111 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8112 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8113 | 0 | break; |
8114 | 0 | } |
8115 | 0 | case SystemZ::VERLL: |
8116 | 0 | case SystemZ::VESL: |
8117 | 0 | case SystemZ::VESRA: |
8118 | 0 | case SystemZ::VESRL: |
8119 | 0 | case SystemZ::VLMAlign: |
8120 | 0 | case SystemZ::VSTMAlign: { |
8121 | | // op: V1 |
8122 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8123 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8124 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8125 | | // op: B2 |
8126 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8127 | 0 | op &= UINT64_C(15); |
8128 | 0 | op <<= 28; |
8129 | 0 | Value |= op; |
8130 | | // op: D2 |
8131 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
8132 | 0 | op &= UINT64_C(4095); |
8133 | 0 | op <<= 16; |
8134 | 0 | Value |= op; |
8135 | | // op: V3 |
8136 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8137 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8138 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8139 | | // op: M4 |
8140 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
8141 | 0 | op &= UINT64_C(15); |
8142 | 0 | op <<= 12; |
8143 | 0 | Value |= op; |
8144 | 0 | break; |
8145 | 0 | } |
8146 | 0 | case SystemZ::VLVGB: |
8147 | 0 | case SystemZ::VLVGF: |
8148 | 0 | case SystemZ::VLVGG: |
8149 | 0 | case SystemZ::VLVGH: { |
8150 | | // op: V1 |
8151 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8152 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8153 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8154 | | // op: B2 |
8155 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
8156 | 0 | op &= UINT64_C(15); |
8157 | 0 | op <<= 28; |
8158 | 0 | Value |= op; |
8159 | | // op: D2 |
8160 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
8161 | 0 | op &= UINT64_C(4095); |
8162 | 0 | op <<= 16; |
8163 | 0 | Value |= op; |
8164 | | // op: R3 |
8165 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8166 | 0 | op &= UINT64_C(15); |
8167 | 0 | op <<= 32; |
8168 | 0 | Value |= op; |
8169 | 0 | break; |
8170 | 0 | } |
8171 | 0 | case SystemZ::VLVG: { |
8172 | | // op: V1 |
8173 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8174 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8175 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8176 | | // op: B2 |
8177 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
8178 | 0 | op &= UINT64_C(15); |
8179 | 0 | op <<= 28; |
8180 | 0 | Value |= op; |
8181 | | // op: D2 |
8182 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 4, Fixups, STI); |
8183 | 0 | op &= UINT64_C(4095); |
8184 | 0 | op <<= 16; |
8185 | 0 | Value |= op; |
8186 | | // op: R3 |
8187 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8188 | 0 | op &= UINT64_C(15); |
8189 | 0 | op <<= 32; |
8190 | 0 | Value |= op; |
8191 | | // op: M4 |
8192 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
8193 | 0 | op &= UINT64_C(15); |
8194 | 0 | op <<= 12; |
8195 | 0 | Value |= op; |
8196 | 0 | break; |
8197 | 0 | } |
8198 | 0 | case SystemZ::VREPIB: |
8199 | 0 | case SystemZ::VREPIF: |
8200 | 0 | case SystemZ::VREPIG: |
8201 | 0 | case SystemZ::VREPIH: { |
8202 | | // op: V1 |
8203 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8204 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8205 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8206 | | // op: I2 |
8207 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 1, Fixups, STI); |
8208 | 0 | op &= UINT64_C(65535); |
8209 | 0 | op <<= 16; |
8210 | 0 | Value |= op; |
8211 | 0 | break; |
8212 | 0 | } |
8213 | 0 | case SystemZ::VREPI: { |
8214 | | // op: V1 |
8215 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8216 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8217 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8218 | | // op: I2 |
8219 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 1, Fixups, STI); |
8220 | 0 | op &= UINT64_C(65535); |
8221 | 0 | op <<= 16; |
8222 | 0 | Value |= op; |
8223 | | // op: M3 |
8224 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8225 | 0 | op &= UINT64_C(15); |
8226 | 0 | op <<= 12; |
8227 | 0 | Value |= op; |
8228 | 0 | break; |
8229 | 0 | } |
8230 | 0 | case SystemZ::VLEIG: { |
8231 | | // op: V1 |
8232 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8233 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8234 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8235 | | // op: I2 |
8236 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
8237 | 0 | op &= UINT64_C(65535); |
8238 | 0 | op <<= 16; |
8239 | 0 | Value |= op; |
8240 | | // op: M3 |
8241 | 0 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, 3, Fixups, STI); |
8242 | 0 | op &= UINT64_C(15); |
8243 | 0 | op <<= 12; |
8244 | 0 | Value |= op; |
8245 | 0 | break; |
8246 | 0 | } |
8247 | 0 | case SystemZ::VLEIF: { |
8248 | | // op: V1 |
8249 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8250 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8251 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8252 | | // op: I2 |
8253 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
8254 | 0 | op &= UINT64_C(65535); |
8255 | 0 | op <<= 16; |
8256 | 0 | Value |= op; |
8257 | | // op: M3 |
8258 | 0 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, 3, Fixups, STI); |
8259 | 0 | op &= UINT64_C(15); |
8260 | 0 | op <<= 12; |
8261 | 0 | Value |= op; |
8262 | 0 | break; |
8263 | 0 | } |
8264 | 0 | case SystemZ::VLEIH: { |
8265 | | // op: V1 |
8266 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8267 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8268 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8269 | | // op: I2 |
8270 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
8271 | 0 | op &= UINT64_C(65535); |
8272 | 0 | op <<= 16; |
8273 | 0 | Value |= op; |
8274 | | // op: M3 |
8275 | 0 | op = getImmOpValue<SystemZ::FK_390_U3Imm>(MI, 3, Fixups, STI); |
8276 | 0 | op &= UINT64_C(15); |
8277 | 0 | op <<= 12; |
8278 | 0 | Value |= op; |
8279 | 0 | break; |
8280 | 0 | } |
8281 | 0 | case SystemZ::VLEIB: { |
8282 | | // op: V1 |
8283 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8284 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8285 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8286 | | // op: I2 |
8287 | 0 | op = getImmOpValue<SystemZ::FK_390_S16Imm>(MI, 2, Fixups, STI); |
8288 | 0 | op &= UINT64_C(65535); |
8289 | 0 | op <<= 16; |
8290 | 0 | Value |= op; |
8291 | | // op: M3 |
8292 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8293 | 0 | op &= UINT64_C(15); |
8294 | 0 | op <<= 12; |
8295 | 0 | Value |= op; |
8296 | 0 | break; |
8297 | 0 | } |
8298 | 0 | case SystemZ::VGBM: { |
8299 | | // op: V1 |
8300 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8301 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8302 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8303 | | // op: I2 |
8304 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 1, Fixups, STI); |
8305 | 0 | op &= UINT64_C(65535); |
8306 | 0 | op <<= 16; |
8307 | 0 | Value |= op; |
8308 | 0 | break; |
8309 | 0 | } |
8310 | 0 | case SystemZ::VLIP: { |
8311 | | // op: V1 |
8312 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8313 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8314 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8315 | | // op: I2 |
8316 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 1, Fixups, STI); |
8317 | 0 | op &= UINT64_C(65535); |
8318 | 0 | op <<= 16; |
8319 | 0 | Value |= op; |
8320 | | // op: I3 |
8321 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8322 | 0 | op &= UINT64_C(15); |
8323 | 0 | op <<= 12; |
8324 | 0 | Value |= op; |
8325 | 0 | break; |
8326 | 0 | } |
8327 | 0 | case SystemZ::VGMB: |
8328 | 0 | case SystemZ::VGMF: |
8329 | 0 | case SystemZ::VGMG: |
8330 | 0 | case SystemZ::VGMH: { |
8331 | | // op: V1 |
8332 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8333 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8334 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8335 | | // op: I2 |
8336 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
8337 | 0 | op &= UINT64_C(255); |
8338 | 0 | op <<= 24; |
8339 | 0 | Value |= op; |
8340 | | // op: I3 |
8341 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
8342 | 0 | op &= UINT64_C(255); |
8343 | 0 | op <<= 16; |
8344 | 0 | Value |= op; |
8345 | 0 | break; |
8346 | 0 | } |
8347 | 0 | case SystemZ::VGM: { |
8348 | | // op: V1 |
8349 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8350 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8351 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8352 | | // op: I2 |
8353 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 1, Fixups, STI); |
8354 | 0 | op &= UINT64_C(255); |
8355 | 0 | op <<= 24; |
8356 | 0 | Value |= op; |
8357 | | // op: I3 |
8358 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
8359 | 0 | op &= UINT64_C(255); |
8360 | 0 | op <<= 16; |
8361 | 0 | Value |= op; |
8362 | | // op: M4 |
8363 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8364 | 0 | op &= UINT64_C(15); |
8365 | 0 | op <<= 12; |
8366 | 0 | Value |= op; |
8367 | 0 | break; |
8368 | 0 | } |
8369 | 0 | case SystemZ::VCVD: |
8370 | 0 | case SystemZ::VCVDG: { |
8371 | | // op: V1 |
8372 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8373 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8374 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8375 | | // op: R2 |
8376 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8377 | 0 | op &= UINT64_C(15); |
8378 | 0 | op <<= 32; |
8379 | 0 | Value |= op; |
8380 | | // op: I3 |
8381 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
8382 | 0 | op &= UINT64_C(255); |
8383 | 0 | op <<= 12; |
8384 | 0 | Value |= op; |
8385 | | // op: M4 |
8386 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8387 | 0 | op &= UINT64_C(15); |
8388 | 0 | op <<= 20; |
8389 | 0 | Value |= op; |
8390 | 0 | break; |
8391 | 0 | } |
8392 | 0 | case SystemZ::VLVGP: { |
8393 | | // op: V1 |
8394 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8395 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8396 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8397 | | // op: R2 |
8398 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8399 | 0 | op &= UINT64_C(15); |
8400 | 0 | op <<= 32; |
8401 | 0 | Value |= op; |
8402 | | // op: R3 |
8403 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
8404 | 0 | op &= UINT64_C(15); |
8405 | 0 | op <<= 28; |
8406 | 0 | Value |= op; |
8407 | 0 | break; |
8408 | 0 | } |
8409 | 0 | case SystemZ::VCLZB: |
8410 | 0 | case SystemZ::VCLZF: |
8411 | 0 | case SystemZ::VCLZG: |
8412 | 0 | case SystemZ::VCLZH: |
8413 | 0 | case SystemZ::VCTZB: |
8414 | 0 | case SystemZ::VCTZF: |
8415 | 0 | case SystemZ::VCTZG: |
8416 | 0 | case SystemZ::VCTZH: |
8417 | 0 | case SystemZ::VECB: |
8418 | 0 | case SystemZ::VECF: |
8419 | 0 | case SystemZ::VECG: |
8420 | 0 | case SystemZ::VECH: |
8421 | 0 | case SystemZ::VECLB: |
8422 | 0 | case SystemZ::VECLF: |
8423 | 0 | case SystemZ::VECLG: |
8424 | 0 | case SystemZ::VECLH: |
8425 | 0 | case SystemZ::VFLCDB: |
8426 | 0 | case SystemZ::VFLCSB: |
8427 | 0 | case SystemZ::VFLLS: |
8428 | 0 | case SystemZ::VFLNDB: |
8429 | 0 | case SystemZ::VFLNSB: |
8430 | 0 | case SystemZ::VFLPDB: |
8431 | 0 | case SystemZ::VFLPSB: |
8432 | 0 | case SystemZ::VFSQDB: |
8433 | 0 | case SystemZ::VFSQSB: |
8434 | 0 | case SystemZ::VISTRBS: |
8435 | 0 | case SystemZ::VISTRFS: |
8436 | 0 | case SystemZ::VISTRHS: |
8437 | 0 | case SystemZ::VLCB: |
8438 | 0 | case SystemZ::VLCF: |
8439 | 0 | case SystemZ::VLCG: |
8440 | 0 | case SystemZ::VLCH: |
8441 | 0 | case SystemZ::VLDEB: |
8442 | 0 | case SystemZ::VLPB: |
8443 | 0 | case SystemZ::VLPF: |
8444 | 0 | case SystemZ::VLPG: |
8445 | 0 | case SystemZ::VLPH: |
8446 | 0 | case SystemZ::VLR: |
8447 | 0 | case SystemZ::VPOPCTB: |
8448 | 0 | case SystemZ::VPOPCTF: |
8449 | 0 | case SystemZ::VPOPCTG: |
8450 | 0 | case SystemZ::VPOPCTH: |
8451 | 0 | case SystemZ::VSEGB: |
8452 | 0 | case SystemZ::VSEGF: |
8453 | 0 | case SystemZ::VSEGH: |
8454 | 0 | case SystemZ::VTM: |
8455 | 0 | case SystemZ::VUPHB: |
8456 | 0 | case SystemZ::VUPHF: |
8457 | 0 | case SystemZ::VUPHH: |
8458 | 0 | case SystemZ::VUPLB: |
8459 | 0 | case SystemZ::VUPLF: |
8460 | 0 | case SystemZ::VUPLHB: |
8461 | 0 | case SystemZ::VUPLHF: |
8462 | 0 | case SystemZ::VUPLHH: |
8463 | 0 | case SystemZ::VUPLHW: |
8464 | 0 | case SystemZ::VUPLLB: |
8465 | 0 | case SystemZ::VUPLLF: |
8466 | 0 | case SystemZ::VUPLLH: |
8467 | 0 | case SystemZ::WFCDB: |
8468 | 0 | case SystemZ::WFCSB: |
8469 | 0 | case SystemZ::WFCXB: |
8470 | 0 | case SystemZ::WFKDB: |
8471 | 0 | case SystemZ::WFKSB: |
8472 | 0 | case SystemZ::WFKXB: |
8473 | 0 | case SystemZ::WFLCDB: |
8474 | 0 | case SystemZ::WFLCSB: |
8475 | 0 | case SystemZ::WFLCXB: |
8476 | 0 | case SystemZ::WFLLD: |
8477 | 0 | case SystemZ::WFLLS: |
8478 | 0 | case SystemZ::WFLNDB: |
8479 | 0 | case SystemZ::WFLNSB: |
8480 | 0 | case SystemZ::WFLNXB: |
8481 | 0 | case SystemZ::WFLPDB: |
8482 | 0 | case SystemZ::WFLPSB: |
8483 | 0 | case SystemZ::WFLPXB: |
8484 | 0 | case SystemZ::WFSQDB: |
8485 | 0 | case SystemZ::WFSQSB: |
8486 | 0 | case SystemZ::WFSQXB: |
8487 | 0 | case SystemZ::WLDEB: { |
8488 | | // op: V1 |
8489 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8490 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8491 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8492 | | // op: V2 |
8493 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8494 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8495 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8496 | 0 | break; |
8497 | 0 | } |
8498 | 0 | case SystemZ::VFTCIDB: |
8499 | 0 | case SystemZ::VFTCISB: |
8500 | 0 | case SystemZ::WFTCIDB: |
8501 | 0 | case SystemZ::WFTCISB: |
8502 | 0 | case SystemZ::WFTCIXB: { |
8503 | | // op: V1 |
8504 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8505 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8506 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8507 | | // op: V2 |
8508 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8509 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8510 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8511 | | // op: I3 |
8512 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
8513 | 0 | op &= UINT64_C(4095); |
8514 | 0 | op <<= 20; |
8515 | 0 | Value |= op; |
8516 | 0 | break; |
8517 | 0 | } |
8518 | 0 | case SystemZ::VFTCI: { |
8519 | | // op: V1 |
8520 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8521 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8522 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8523 | | // op: V2 |
8524 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8525 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8526 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8527 | | // op: I3 |
8528 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
8529 | 0 | op &= UINT64_C(4095); |
8530 | 0 | op <<= 20; |
8531 | 0 | Value |= op; |
8532 | | // op: M4 |
8533 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8534 | 0 | op &= UINT64_C(15); |
8535 | 0 | op <<= 12; |
8536 | 0 | Value |= op; |
8537 | | // op: M5 |
8538 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
8539 | 0 | op &= UINT64_C(15); |
8540 | 0 | op <<= 16; |
8541 | 0 | Value |= op; |
8542 | 0 | break; |
8543 | 0 | } |
8544 | 0 | case SystemZ::VPSOP: |
8545 | 0 | case SystemZ::VSRP: { |
8546 | | // op: V1 |
8547 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8548 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8549 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8550 | | // op: V2 |
8551 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8552 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8553 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8554 | | // op: I3 |
8555 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 2, Fixups, STI); |
8556 | 0 | op &= UINT64_C(255); |
8557 | 0 | op <<= 12; |
8558 | 0 | Value |= op; |
8559 | | // op: I4 |
8560 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
8561 | 0 | op &= UINT64_C(255); |
8562 | 0 | op <<= 24; |
8563 | 0 | Value |= op; |
8564 | | // op: M5 |
8565 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
8566 | 0 | op &= UINT64_C(15); |
8567 | 0 | op <<= 20; |
8568 | 0 | Value |= op; |
8569 | 0 | break; |
8570 | 0 | } |
8571 | 0 | case SystemZ::VCLZ: |
8572 | 0 | case SystemZ::VCTZ: |
8573 | 0 | case SystemZ::VEC: |
8574 | 0 | case SystemZ::VECL: |
8575 | 0 | case SystemZ::VLC: |
8576 | 0 | case SystemZ::VLP: |
8577 | 0 | case SystemZ::VPOPCT: |
8578 | 0 | case SystemZ::VSEG: |
8579 | 0 | case SystemZ::VUPH: |
8580 | 0 | case SystemZ::VUPL: |
8581 | 0 | case SystemZ::VUPLH: |
8582 | 0 | case SystemZ::VUPLL: { |
8583 | | // op: V1 |
8584 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8585 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8586 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8587 | | // op: V2 |
8588 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8589 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8590 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8591 | | // op: M3 |
8592 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8593 | 0 | op &= UINT64_C(15); |
8594 | 0 | op <<= 12; |
8595 | 0 | Value |= op; |
8596 | 0 | break; |
8597 | 0 | } |
8598 | 0 | case SystemZ::VCFN: |
8599 | 0 | case SystemZ::VCLFNH: |
8600 | 0 | case SystemZ::VCLFNL: |
8601 | 0 | case SystemZ::VCNF: |
8602 | 0 | case SystemZ::VFLL: |
8603 | 0 | case SystemZ::VFSQ: |
8604 | 0 | case SystemZ::VLDE: |
8605 | 0 | case SystemZ::WFC: |
8606 | 0 | case SystemZ::WFK: { |
8607 | | // op: V1 |
8608 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8609 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8610 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8611 | | // op: V2 |
8612 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8613 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8614 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8615 | | // op: M3 |
8616 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8617 | 0 | op &= UINT64_C(15); |
8618 | 0 | op <<= 12; |
8619 | 0 | Value |= op; |
8620 | | // op: M4 |
8621 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8622 | 0 | op &= UINT64_C(15); |
8623 | 0 | op <<= 16; |
8624 | 0 | Value |= op; |
8625 | 0 | break; |
8626 | 0 | } |
8627 | 0 | case SystemZ::VCDG: |
8628 | 0 | case SystemZ::VCDLG: |
8629 | 0 | case SystemZ::VCFPL: |
8630 | 0 | case SystemZ::VCFPS: |
8631 | 0 | case SystemZ::VCGD: |
8632 | 0 | case SystemZ::VCLFP: |
8633 | 0 | case SystemZ::VCLGD: |
8634 | 0 | case SystemZ::VCSFP: |
8635 | 0 | case SystemZ::VFI: |
8636 | 0 | case SystemZ::VFLR: |
8637 | 0 | case SystemZ::VFPSO: |
8638 | 0 | case SystemZ::VLED: { |
8639 | | // op: V1 |
8640 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8641 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8642 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8643 | | // op: V2 |
8644 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8645 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8646 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8647 | | // op: M3 |
8648 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8649 | 0 | op &= UINT64_C(15); |
8650 | 0 | op <<= 12; |
8651 | 0 | Value |= op; |
8652 | | // op: M4 |
8653 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8654 | 0 | op &= UINT64_C(15); |
8655 | 0 | op <<= 16; |
8656 | 0 | Value |= op; |
8657 | | // op: M5 |
8658 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
8659 | 0 | op &= UINT64_C(15); |
8660 | 0 | op <<= 20; |
8661 | 0 | Value |= op; |
8662 | 0 | break; |
8663 | 0 | } |
8664 | 0 | case SystemZ::VISTR: { |
8665 | | // op: V1 |
8666 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8667 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8668 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8669 | | // op: V2 |
8670 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8671 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8672 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8673 | | // op: M3 |
8674 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8675 | 0 | op &= UINT64_C(15); |
8676 | 0 | op <<= 12; |
8677 | 0 | Value |= op; |
8678 | | // op: M5 |
8679 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8680 | 0 | op &= UINT64_C(15); |
8681 | 0 | op <<= 20; |
8682 | 0 | Value |= op; |
8683 | 0 | break; |
8684 | 0 | } |
8685 | 0 | case SystemZ::VCLZDP: |
8686 | 0 | case SystemZ::VUPKZH: |
8687 | 0 | case SystemZ::VUPKZL: { |
8688 | | // op: V1 |
8689 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8690 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8691 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8692 | | // op: V2 |
8693 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8694 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8695 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8696 | | // op: M3 |
8697 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8698 | 0 | op &= UINT64_C(15); |
8699 | 0 | op <<= 20; |
8700 | 0 | Value |= op; |
8701 | 0 | break; |
8702 | 0 | } |
8703 | 0 | case SystemZ::VCDGB: |
8704 | 0 | case SystemZ::VCDLGB: |
8705 | 0 | case SystemZ::VCEFB: |
8706 | 0 | case SystemZ::VCELFB: |
8707 | 0 | case SystemZ::VCFEB: |
8708 | 0 | case SystemZ::VCGDB: |
8709 | 0 | case SystemZ::VCLFEB: |
8710 | 0 | case SystemZ::VCLGDB: |
8711 | 0 | case SystemZ::VFIDB: |
8712 | 0 | case SystemZ::VFISB: |
8713 | 0 | case SystemZ::VFLRD: |
8714 | 0 | case SystemZ::VLEDB: { |
8715 | | // op: V1 |
8716 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8717 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8718 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8719 | | // op: V2 |
8720 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8721 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8722 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8723 | | // op: M4 |
8724 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8725 | 0 | op &= UINT64_C(15); |
8726 | 0 | op <<= 16; |
8727 | 0 | Value |= op; |
8728 | | // op: M5 |
8729 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8730 | 0 | op &= UINT64_C(15); |
8731 | 0 | op <<= 20; |
8732 | 0 | Value |= op; |
8733 | 0 | break; |
8734 | 0 | } |
8735 | 0 | case SystemZ::WCDGB: |
8736 | 0 | case SystemZ::WCDLGB: |
8737 | 0 | case SystemZ::WCEFB: |
8738 | 0 | case SystemZ::WCELFB: |
8739 | 0 | case SystemZ::WCFEB: |
8740 | 0 | case SystemZ::WCGDB: |
8741 | 0 | case SystemZ::WCLFEB: |
8742 | 0 | case SystemZ::WCLGDB: |
8743 | 0 | case SystemZ::WFIDB: |
8744 | 0 | case SystemZ::WFISB: |
8745 | 0 | case SystemZ::WFIXB: |
8746 | 0 | case SystemZ::WFLRD: |
8747 | 0 | case SystemZ::WFLRX: |
8748 | 0 | case SystemZ::WLEDB: { |
8749 | | // op: V1 |
8750 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8751 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8752 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8753 | | // op: V2 |
8754 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8755 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8756 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8757 | | // op: M4 |
8758 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8759 | 0 | op &= UINT64_C(7); |
8760 | 0 | op <<= 16; |
8761 | 0 | Value |= op; |
8762 | | // op: M5 |
8763 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
8764 | 0 | op &= UINT64_C(15); |
8765 | 0 | op <<= 20; |
8766 | 0 | Value |= op; |
8767 | 0 | break; |
8768 | 0 | } |
8769 | 0 | case SystemZ::VFPSODB: |
8770 | 0 | case SystemZ::VFPSOSB: |
8771 | 0 | case SystemZ::VISTRB: |
8772 | 0 | case SystemZ::VISTRF: |
8773 | 0 | case SystemZ::VISTRH: |
8774 | 0 | case SystemZ::WFPSODB: |
8775 | 0 | case SystemZ::WFPSOSB: |
8776 | 0 | case SystemZ::WFPSOXB: { |
8777 | | // op: V1 |
8778 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
8779 | 0 | Value |= (op & UINT64_C(15)) << 36; |
8780 | 0 | Value |= (op & UINT64_C(16)) << 7; |
8781 | | // op: V2 |
8782 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
8783 | 0 | Value |= (op & UINT64_C(15)) << 32; |
8784 | 0 | Value |= (op & UINT64_C(16)) << 6; |
8785 | | // op: M5 |
8786 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 2, Fixups, STI); |
8787 | 0 | op &= UINT64_C(15); |
8788 | 0 | op <<= 20; |
8789 | 0 | Value |= op; |
8790 | 0 | break; |
8791 | 0 | } |
8792 | 0 | case SystemZ::VAB: |
8793 | 0 | case SystemZ::VACCB: |
8794 | 0 | case SystemZ::VACCF: |
8795 | 0 | case SystemZ::VACCG: |
8796 | 0 | case SystemZ::VACCH: |
8797 | 0 | case SystemZ::VACCQ: |
8798 | 0 | case SystemZ::VAF: |
8799 | 0 | case SystemZ::VAG: |
8800 | 0 | case SystemZ::VAH: |
8801 | 0 | case SystemZ::VAQ: |
8802 | 0 | case SystemZ::VAVGB: |
8803 | 0 | case SystemZ::VAVGF: |
8804 | 0 | case SystemZ::VAVGG: |
8805 | 0 | case SystemZ::VAVGH: |
8806 | 0 | case SystemZ::VAVGLB: |
8807 | 0 | case SystemZ::VAVGLF: |
8808 | 0 | case SystemZ::VAVGLG: |
8809 | 0 | case SystemZ::VAVGLH: |
8810 | 0 | case SystemZ::VBPERM: |
8811 | 0 | case SystemZ::VCEQB: |
8812 | 0 | case SystemZ::VCEQBS: |
8813 | 0 | case SystemZ::VCEQF: |
8814 | 0 | case SystemZ::VCEQFS: |
8815 | 0 | case SystemZ::VCEQG: |
8816 | 0 | case SystemZ::VCEQGS: |
8817 | 0 | case SystemZ::VCEQH: |
8818 | 0 | case SystemZ::VCEQHS: |
8819 | 0 | case SystemZ::VCHB: |
8820 | 0 | case SystemZ::VCHBS: |
8821 | 0 | case SystemZ::VCHF: |
8822 | 0 | case SystemZ::VCHFS: |
8823 | 0 | case SystemZ::VCHG: |
8824 | 0 | case SystemZ::VCHGS: |
8825 | 0 | case SystemZ::VCHH: |
8826 | 0 | case SystemZ::VCHHS: |
8827 | 0 | case SystemZ::VCHLB: |
8828 | 0 | case SystemZ::VCHLBS: |
8829 | 0 | case SystemZ::VCHLF: |
8830 | 0 | case SystemZ::VCHLFS: |
8831 | 0 | case SystemZ::VCHLG: |
8832 | 0 | case SystemZ::VCHLGS: |
8833 | 0 | case SystemZ::VCHLH: |
8834 | 0 | case SystemZ::VCHLHS: |
8835 | 0 | case SystemZ::VCKSM: |
8836 | 0 | case SystemZ::VERLLVB: |
8837 | 0 | case SystemZ::VERLLVF: |
8838 | 0 | case SystemZ::VERLLVG: |
8839 | 0 | case SystemZ::VERLLVH: |
8840 | 0 | case SystemZ::VESLVB: |
8841 | 0 | case SystemZ::VESLVF: |
8842 | 0 | case SystemZ::VESLVG: |
8843 | 0 | case SystemZ::VESLVH: |
8844 | 0 | case SystemZ::VESRAVB: |
8845 | 0 | case SystemZ::VESRAVF: |
8846 | 0 | case SystemZ::VESRAVG: |
8847 | 0 | case SystemZ::VESRAVH: |
8848 | 0 | case SystemZ::VESRLVB: |
8849 | 0 | case SystemZ::VESRLVF: |
8850 | 0 | case SystemZ::VESRLVG: |
8851 | 0 | case SystemZ::VESRLVH: |
8852 | 0 | case SystemZ::VFADB: |
8853 | 0 | case SystemZ::VFASB: |
8854 | 0 | case SystemZ::VFCEDB: |
8855 | 0 | case SystemZ::VFCEDBS: |
8856 | 0 | case SystemZ::VFCESB: |
8857 | 0 | case SystemZ::VFCESBS: |
8858 | 0 | case SystemZ::VFCHDB: |
8859 | 0 | case SystemZ::VFCHDBS: |
8860 | 0 | case SystemZ::VFCHEDB: |
8861 | 0 | case SystemZ::VFCHEDBS: |
8862 | 0 | case SystemZ::VFCHESB: |
8863 | 0 | case SystemZ::VFCHESBS: |
8864 | 0 | case SystemZ::VFCHSB: |
8865 | 0 | case SystemZ::VFCHSBS: |
8866 | 0 | case SystemZ::VFDDB: |
8867 | 0 | case SystemZ::VFDSB: |
8868 | 0 | case SystemZ::VFEEBS: |
8869 | 0 | case SystemZ::VFEEFS: |
8870 | 0 | case SystemZ::VFEEHS: |
8871 | 0 | case SystemZ::VFEEZB: |
8872 | 0 | case SystemZ::VFEEZBS: |
8873 | 0 | case SystemZ::VFEEZF: |
8874 | 0 | case SystemZ::VFEEZFS: |
8875 | 0 | case SystemZ::VFEEZH: |
8876 | 0 | case SystemZ::VFEEZHS: |
8877 | 0 | case SystemZ::VFENEBS: |
8878 | 0 | case SystemZ::VFENEFS: |
8879 | 0 | case SystemZ::VFENEHS: |
8880 | 0 | case SystemZ::VFENEZB: |
8881 | 0 | case SystemZ::VFENEZBS: |
8882 | 0 | case SystemZ::VFENEZF: |
8883 | 0 | case SystemZ::VFENEZFS: |
8884 | 0 | case SystemZ::VFENEZH: |
8885 | 0 | case SystemZ::VFENEZHS: |
8886 | 0 | case SystemZ::VFKEDB: |
8887 | 0 | case SystemZ::VFKEDBS: |
8888 | 0 | case SystemZ::VFKESB: |
8889 | 0 | case SystemZ::VFKESBS: |
8890 | 0 | case SystemZ::VFKHDB: |
8891 | 0 | case SystemZ::VFKHDBS: |
8892 | 0 | case SystemZ::VFKHEDB: |
8893 | 0 | case SystemZ::VFKHEDBS: |
8894 | 0 | case SystemZ::VFKHESB: |
8895 | 0 | case SystemZ::VFKHESBS: |
8896 | 0 | case SystemZ::VFKHSB: |
8897 | 0 | case SystemZ::VFKHSBS: |
8898 | 0 | case SystemZ::VFMDB: |
8899 | 0 | case SystemZ::VFMSB: |
8900 | 0 | case SystemZ::VFSDB: |
8901 | 0 | case SystemZ::VFSSB: |
8902 | 0 | case SystemZ::VGFMB: |
8903 | 0 | case SystemZ::VGFMF: |
8904 | 0 | case SystemZ::VGFMG: |
8905 | 0 | case SystemZ::VGFMH: |
8906 | 0 | case SystemZ::VMEB: |
8907 | 0 | case SystemZ::VMEF: |
8908 | 0 | case SystemZ::VMEH: |
8909 | 0 | case SystemZ::VMHB: |
8910 | 0 | case SystemZ::VMHF: |
8911 | 0 | case SystemZ::VMHH: |
8912 | 0 | case SystemZ::VMLB: |
8913 | 0 | case SystemZ::VMLEB: |
8914 | 0 | case SystemZ::VMLEF: |
8915 | 0 | case SystemZ::VMLEH: |
8916 | 0 | case SystemZ::VMLF: |
8917 | 0 | case SystemZ::VMLHB: |
8918 | 0 | case SystemZ::VMLHF: |
8919 | 0 | case SystemZ::VMLHH: |
8920 | 0 | case SystemZ::VMLHW: |
8921 | 0 | case SystemZ::VMLOB: |
8922 | 0 | case SystemZ::VMLOF: |
8923 | 0 | case SystemZ::VMLOH: |
8924 | 0 | case SystemZ::VMNB: |
8925 | 0 | case SystemZ::VMNF: |
8926 | 0 | case SystemZ::VMNG: |
8927 | 0 | case SystemZ::VMNH: |
8928 | 0 | case SystemZ::VMNLB: |
8929 | 0 | case SystemZ::VMNLF: |
8930 | 0 | case SystemZ::VMNLG: |
8931 | 0 | case SystemZ::VMNLH: |
8932 | 0 | case SystemZ::VMOB: |
8933 | 0 | case SystemZ::VMOF: |
8934 | 0 | case SystemZ::VMOH: |
8935 | 0 | case SystemZ::VMRHB: |
8936 | 0 | case SystemZ::VMRHF: |
8937 | 0 | case SystemZ::VMRHG: |
8938 | 0 | case SystemZ::VMRHH: |
8939 | 0 | case SystemZ::VMRLB: |
8940 | 0 | case SystemZ::VMRLF: |
8941 | 0 | case SystemZ::VMRLG: |
8942 | 0 | case SystemZ::VMRLH: |
8943 | 0 | case SystemZ::VMXB: |
8944 | 0 | case SystemZ::VMXF: |
8945 | 0 | case SystemZ::VMXG: |
8946 | 0 | case SystemZ::VMXH: |
8947 | 0 | case SystemZ::VMXLB: |
8948 | 0 | case SystemZ::VMXLF: |
8949 | 0 | case SystemZ::VMXLG: |
8950 | 0 | case SystemZ::VMXLH: |
8951 | 0 | case SystemZ::VN: |
8952 | 0 | case SystemZ::VNC: |
8953 | 0 | case SystemZ::VNN: |
8954 | 0 | case SystemZ::VNO: |
8955 | 0 | case SystemZ::VNX: |
8956 | 0 | case SystemZ::VO: |
8957 | 0 | case SystemZ::VOC: |
8958 | 0 | case SystemZ::VPKF: |
8959 | 0 | case SystemZ::VPKG: |
8960 | 0 | case SystemZ::VPKH: |
8961 | 0 | case SystemZ::VPKLSF: |
8962 | 0 | case SystemZ::VPKLSFS: |
8963 | 0 | case SystemZ::VPKLSG: |
8964 | 0 | case SystemZ::VPKLSGS: |
8965 | 0 | case SystemZ::VPKLSH: |
8966 | 0 | case SystemZ::VPKLSHS: |
8967 | 0 | case SystemZ::VPKSF: |
8968 | 0 | case SystemZ::VPKSFS: |
8969 | 0 | case SystemZ::VPKSG: |
8970 | 0 | case SystemZ::VPKSGS: |
8971 | 0 | case SystemZ::VPKSH: |
8972 | 0 | case SystemZ::VPKSHS: |
8973 | 0 | case SystemZ::VSB: |
8974 | 0 | case SystemZ::VSCBIB: |
8975 | 0 | case SystemZ::VSCBIF: |
8976 | 0 | case SystemZ::VSCBIG: |
8977 | 0 | case SystemZ::VSCBIH: |
8978 | 0 | case SystemZ::VSCBIQ: |
8979 | 0 | case SystemZ::VSCSHP: |
8980 | 0 | case SystemZ::VSF: |
8981 | 0 | case SystemZ::VSG: |
8982 | 0 | case SystemZ::VSH: |
8983 | 0 | case SystemZ::VSL: |
8984 | 0 | case SystemZ::VSLB: |
8985 | 0 | case SystemZ::VSQ: |
8986 | 0 | case SystemZ::VSRA: |
8987 | 0 | case SystemZ::VSRAB: |
8988 | 0 | case SystemZ::VSRL: |
8989 | 0 | case SystemZ::VSRLB: |
8990 | 0 | case SystemZ::VSUMB: |
8991 | 0 | case SystemZ::VSUMGF: |
8992 | 0 | case SystemZ::VSUMGH: |
8993 | 0 | case SystemZ::VSUMH: |
8994 | 0 | case SystemZ::VSUMQF: |
8995 | 0 | case SystemZ::VSUMQG: |
8996 | 0 | case SystemZ::VX: |
8997 | 0 | case SystemZ::WFADB: |
8998 | 0 | case SystemZ::WFASB: |
8999 | 0 | case SystemZ::WFAXB: |
9000 | 0 | case SystemZ::WFCEDB: |
9001 | 0 | case SystemZ::WFCEDBS: |
9002 | 0 | case SystemZ::WFCESB: |
9003 | 0 | case SystemZ::WFCESBS: |
9004 | 0 | case SystemZ::WFCEXB: |
9005 | 0 | case SystemZ::WFCEXBS: |
9006 | 0 | case SystemZ::WFCHDB: |
9007 | 0 | case SystemZ::WFCHDBS: |
9008 | 0 | case SystemZ::WFCHEDB: |
9009 | 0 | case SystemZ::WFCHEDBS: |
9010 | 0 | case SystemZ::WFCHESB: |
9011 | 0 | case SystemZ::WFCHESBS: |
9012 | 0 | case SystemZ::WFCHEXB: |
9013 | 0 | case SystemZ::WFCHEXBS: |
9014 | 0 | case SystemZ::WFCHSB: |
9015 | 0 | case SystemZ::WFCHSBS: |
9016 | 0 | case SystemZ::WFCHXB: |
9017 | 0 | case SystemZ::WFCHXBS: |
9018 | 0 | case SystemZ::WFDDB: |
9019 | 0 | case SystemZ::WFDSB: |
9020 | 0 | case SystemZ::WFDXB: |
9021 | 0 | case SystemZ::WFKEDB: |
9022 | 0 | case SystemZ::WFKEDBS: |
9023 | 0 | case SystemZ::WFKESB: |
9024 | 0 | case SystemZ::WFKESBS: |
9025 | 0 | case SystemZ::WFKEXB: |
9026 | 0 | case SystemZ::WFKEXBS: |
9027 | 0 | case SystemZ::WFKHDB: |
9028 | 0 | case SystemZ::WFKHDBS: |
9029 | 0 | case SystemZ::WFKHEDB: |
9030 | 0 | case SystemZ::WFKHEDBS: |
9031 | 0 | case SystemZ::WFKHESB: |
9032 | 0 | case SystemZ::WFKHESBS: |
9033 | 0 | case SystemZ::WFKHEXB: |
9034 | 0 | case SystemZ::WFKHEXBS: |
9035 | 0 | case SystemZ::WFKHSB: |
9036 | 0 | case SystemZ::WFKHSBS: |
9037 | 0 | case SystemZ::WFKHXB: |
9038 | 0 | case SystemZ::WFKHXBS: |
9039 | 0 | case SystemZ::WFMDB: |
9040 | 0 | case SystemZ::WFMSB: |
9041 | 0 | case SystemZ::WFMXB: |
9042 | 0 | case SystemZ::WFSDB: |
9043 | 0 | case SystemZ::WFSSB: |
9044 | 0 | case SystemZ::WFSXB: { |
9045 | | // op: V1 |
9046 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9047 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9048 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9049 | | // op: V2 |
9050 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9051 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9052 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9053 | | // op: V3 |
9054 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9055 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9056 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9057 | 0 | break; |
9058 | 0 | } |
9059 | 0 | case SystemZ::VAP: |
9060 | 0 | case SystemZ::VDP: |
9061 | 0 | case SystemZ::VMP: |
9062 | 0 | case SystemZ::VMSP: |
9063 | 0 | case SystemZ::VPKZR: |
9064 | 0 | case SystemZ::VRP: |
9065 | 0 | case SystemZ::VSDP: |
9066 | 0 | case SystemZ::VSP: |
9067 | 0 | case SystemZ::VSRPR: { |
9068 | | // op: V1 |
9069 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9070 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9071 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9072 | | // op: V2 |
9073 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9074 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9075 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9076 | | // op: V3 |
9077 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9078 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9079 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9080 | | // op: I4 |
9081 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
9082 | 0 | op &= UINT64_C(255); |
9083 | 0 | op <<= 12; |
9084 | 0 | Value |= op; |
9085 | | // op: M5 |
9086 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9087 | 0 | op &= UINT64_C(15); |
9088 | 0 | op <<= 20; |
9089 | 0 | Value |= op; |
9090 | 0 | break; |
9091 | 0 | } |
9092 | 0 | case SystemZ::VSLD: |
9093 | 0 | case SystemZ::VSLDB: |
9094 | 0 | case SystemZ::VSRD: { |
9095 | | // op: V1 |
9096 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9097 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9098 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9099 | | // op: V2 |
9100 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9101 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9102 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9103 | | // op: V3 |
9104 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9105 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9106 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9107 | | // op: I4 |
9108 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 3, Fixups, STI); |
9109 | 0 | op &= UINT64_C(255); |
9110 | 0 | op <<= 16; |
9111 | 0 | Value |= op; |
9112 | 0 | break; |
9113 | 0 | } |
9114 | 0 | case SystemZ::VA: |
9115 | 0 | case SystemZ::VACC: |
9116 | 0 | case SystemZ::VAVG: |
9117 | 0 | case SystemZ::VAVGL: |
9118 | 0 | case SystemZ::VERLLV: |
9119 | 0 | case SystemZ::VESLV: |
9120 | 0 | case SystemZ::VESRAV: |
9121 | 0 | case SystemZ::VESRLV: |
9122 | 0 | case SystemZ::VGFM: |
9123 | 0 | case SystemZ::VME: |
9124 | 0 | case SystemZ::VMH: |
9125 | 0 | case SystemZ::VML: |
9126 | 0 | case SystemZ::VMLE: |
9127 | 0 | case SystemZ::VMLH: |
9128 | 0 | case SystemZ::VMLO: |
9129 | 0 | case SystemZ::VMN: |
9130 | 0 | case SystemZ::VMNL: |
9131 | 0 | case SystemZ::VMO: |
9132 | 0 | case SystemZ::VMRH: |
9133 | 0 | case SystemZ::VMRL: |
9134 | 0 | case SystemZ::VMX: |
9135 | 0 | case SystemZ::VMXL: |
9136 | 0 | case SystemZ::VPDI: |
9137 | 0 | case SystemZ::VPK: |
9138 | 0 | case SystemZ::VS: |
9139 | 0 | case SystemZ::VSCBI: |
9140 | 0 | case SystemZ::VSUM: |
9141 | 0 | case SystemZ::VSUMG: |
9142 | 0 | case SystemZ::VSUMQ: { |
9143 | | // op: V1 |
9144 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9145 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9146 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9147 | | // op: V2 |
9148 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9149 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9150 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9151 | | // op: V3 |
9152 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9153 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9154 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9155 | | // op: M4 |
9156 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9157 | 0 | op &= UINT64_C(15); |
9158 | 0 | op <<= 12; |
9159 | 0 | Value |= op; |
9160 | 0 | break; |
9161 | 0 | } |
9162 | 0 | case SystemZ::VCRNF: |
9163 | 0 | case SystemZ::VFA: |
9164 | 0 | case SystemZ::VFD: |
9165 | 0 | case SystemZ::VFM: |
9166 | 0 | case SystemZ::VFS: { |
9167 | | // op: V1 |
9168 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9169 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9170 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9171 | | // op: V2 |
9172 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9173 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9174 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9175 | | // op: V3 |
9176 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9177 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9178 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9179 | | // op: M4 |
9180 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9181 | 0 | op &= UINT64_C(15); |
9182 | 0 | op <<= 12; |
9183 | 0 | Value |= op; |
9184 | | // op: M5 |
9185 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9186 | 0 | op &= UINT64_C(15); |
9187 | 0 | op <<= 16; |
9188 | 0 | Value |= op; |
9189 | 0 | break; |
9190 | 0 | } |
9191 | 0 | case SystemZ::VFCE: |
9192 | 0 | case SystemZ::VFCH: |
9193 | 0 | case SystemZ::VFCHE: |
9194 | 0 | case SystemZ::VFMAX: |
9195 | 0 | case SystemZ::VFMIN: { |
9196 | | // op: V1 |
9197 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9198 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9199 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9200 | | // op: V2 |
9201 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9202 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9203 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9204 | | // op: V3 |
9205 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9206 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9207 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9208 | | // op: M4 |
9209 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9210 | 0 | op &= UINT64_C(15); |
9211 | 0 | op <<= 12; |
9212 | 0 | Value |= op; |
9213 | | // op: M5 |
9214 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9215 | 0 | op &= UINT64_C(15); |
9216 | 0 | op <<= 16; |
9217 | 0 | Value |= op; |
9218 | | // op: M6 |
9219 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
9220 | 0 | op &= UINT64_C(15); |
9221 | 0 | op <<= 20; |
9222 | 0 | Value |= op; |
9223 | 0 | break; |
9224 | 0 | } |
9225 | 0 | case SystemZ::VCEQ: |
9226 | 0 | case SystemZ::VCH: |
9227 | 0 | case SystemZ::VCHL: |
9228 | 0 | case SystemZ::VFAE: |
9229 | 0 | case SystemZ::VFEE: |
9230 | 0 | case SystemZ::VFENE: |
9231 | 0 | case SystemZ::VPKLS: |
9232 | 0 | case SystemZ::VPKS: |
9233 | 0 | case SystemZ::VSCHP: { |
9234 | | // op: V1 |
9235 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9236 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9237 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9238 | | // op: V2 |
9239 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9240 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9241 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9242 | | // op: V3 |
9243 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9244 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9245 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9246 | | // op: M4 |
9247 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9248 | 0 | op &= UINT64_C(15); |
9249 | 0 | op <<= 12; |
9250 | 0 | Value |= op; |
9251 | | // op: M5 |
9252 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9253 | 0 | op &= UINT64_C(15); |
9254 | 0 | op <<= 20; |
9255 | 0 | Value |= op; |
9256 | 0 | break; |
9257 | 0 | } |
9258 | 0 | case SystemZ::VCSPH: { |
9259 | | // op: V1 |
9260 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9261 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9262 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9263 | | // op: V2 |
9264 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9265 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9266 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9267 | | // op: V3 |
9268 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9269 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9270 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9271 | | // op: M4 |
9272 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9273 | 0 | op &= UINT64_C(15); |
9274 | 0 | op <<= 20; |
9275 | 0 | Value |= op; |
9276 | 0 | break; |
9277 | 0 | } |
9278 | 0 | case SystemZ::VFAEZB: |
9279 | 0 | case SystemZ::VFAEZF: |
9280 | 0 | case SystemZ::VFAEZH: { |
9281 | | // op: V1 |
9282 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9283 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9284 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9285 | | // op: V2 |
9286 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9287 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9288 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9289 | | // op: V3 |
9290 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9291 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9292 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9293 | | // op: M5 |
9294 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9295 | 0 | Value |= (op & UINT64_C(12)) << 20; |
9296 | 0 | Value |= (op & UINT64_C(1)) << 20; |
9297 | 0 | break; |
9298 | 0 | } |
9299 | 0 | case SystemZ::VFAEZBS: |
9300 | 0 | case SystemZ::VFAEZFS: |
9301 | 0 | case SystemZ::VFAEZHS: { |
9302 | | // op: V1 |
9303 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9304 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9305 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9306 | | // op: V2 |
9307 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9308 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9309 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9310 | | // op: V3 |
9311 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9312 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9313 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9314 | | // op: M5 |
9315 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9316 | 0 | op &= UINT64_C(12); |
9317 | 0 | op <<= 20; |
9318 | 0 | Value |= op; |
9319 | 0 | break; |
9320 | 0 | } |
9321 | 0 | case SystemZ::VFAEBS: |
9322 | 0 | case SystemZ::VFAEFS: |
9323 | 0 | case SystemZ::VFAEHS: { |
9324 | | // op: V1 |
9325 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9326 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9327 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9328 | | // op: V2 |
9329 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9330 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9331 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9332 | | // op: V3 |
9333 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9334 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9335 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9336 | | // op: M5 |
9337 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9338 | 0 | op &= UINT64_C(14); |
9339 | 0 | op <<= 20; |
9340 | 0 | Value |= op; |
9341 | 0 | break; |
9342 | 0 | } |
9343 | 0 | case SystemZ::VFAEB: |
9344 | 0 | case SystemZ::VFAEF: |
9345 | 0 | case SystemZ::VFAEH: |
9346 | 0 | case SystemZ::VFEEB: |
9347 | 0 | case SystemZ::VFEEF: |
9348 | 0 | case SystemZ::VFEEH: |
9349 | 0 | case SystemZ::VFENEB: |
9350 | 0 | case SystemZ::VFENEF: |
9351 | 0 | case SystemZ::VFENEH: |
9352 | 0 | case SystemZ::VSCHDP: |
9353 | 0 | case SystemZ::VSCHSP: |
9354 | 0 | case SystemZ::VSCHXP: { |
9355 | | // op: V1 |
9356 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9357 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9358 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9359 | | // op: V2 |
9360 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9361 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9362 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9363 | | // op: V3 |
9364 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9365 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9366 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9367 | | // op: M5 |
9368 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9369 | 0 | op &= UINT64_C(15); |
9370 | 0 | op <<= 20; |
9371 | 0 | Value |= op; |
9372 | 0 | break; |
9373 | 0 | } |
9374 | 0 | case SystemZ::VFMAXDB: |
9375 | 0 | case SystemZ::VFMAXSB: |
9376 | 0 | case SystemZ::VFMINDB: |
9377 | 0 | case SystemZ::VFMINSB: |
9378 | 0 | case SystemZ::WFMAXDB: |
9379 | 0 | case SystemZ::WFMAXSB: |
9380 | 0 | case SystemZ::WFMAXXB: |
9381 | 0 | case SystemZ::WFMINDB: |
9382 | 0 | case SystemZ::WFMINSB: |
9383 | 0 | case SystemZ::WFMINXB: { |
9384 | | // op: V1 |
9385 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9386 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9387 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9388 | | // op: V2 |
9389 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9390 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9391 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9392 | | // op: V3 |
9393 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9394 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9395 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9396 | | // op: M6 |
9397 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9398 | 0 | op &= UINT64_C(15); |
9399 | 0 | op <<= 20; |
9400 | 0 | Value |= op; |
9401 | 0 | break; |
9402 | 0 | } |
9403 | 0 | case SystemZ::VACCCQ: |
9404 | 0 | case SystemZ::VACQ: |
9405 | 0 | case SystemZ::VFMADB: |
9406 | 0 | case SystemZ::VFMASB: |
9407 | 0 | case SystemZ::VFMSDB: |
9408 | 0 | case SystemZ::VFMSSB: |
9409 | 0 | case SystemZ::VFNMADB: |
9410 | 0 | case SystemZ::VFNMASB: |
9411 | 0 | case SystemZ::VFNMSDB: |
9412 | 0 | case SystemZ::VFNMSSB: |
9413 | 0 | case SystemZ::VGFMAB: |
9414 | 0 | case SystemZ::VGFMAF: |
9415 | 0 | case SystemZ::VGFMAG: |
9416 | 0 | case SystemZ::VGFMAH: |
9417 | 0 | case SystemZ::VMAEB: |
9418 | 0 | case SystemZ::VMAEF: |
9419 | 0 | case SystemZ::VMAEH: |
9420 | 0 | case SystemZ::VMAHB: |
9421 | 0 | case SystemZ::VMAHF: |
9422 | 0 | case SystemZ::VMAHH: |
9423 | 0 | case SystemZ::VMALB: |
9424 | 0 | case SystemZ::VMALEB: |
9425 | 0 | case SystemZ::VMALEF: |
9426 | 0 | case SystemZ::VMALEH: |
9427 | 0 | case SystemZ::VMALF: |
9428 | 0 | case SystemZ::VMALHB: |
9429 | 0 | case SystemZ::VMALHF: |
9430 | 0 | case SystemZ::VMALHH: |
9431 | 0 | case SystemZ::VMALHW: |
9432 | 0 | case SystemZ::VMALOB: |
9433 | 0 | case SystemZ::VMALOF: |
9434 | 0 | case SystemZ::VMALOH: |
9435 | 0 | case SystemZ::VMAOB: |
9436 | 0 | case SystemZ::VMAOF: |
9437 | 0 | case SystemZ::VMAOH: |
9438 | 0 | case SystemZ::VPERM: |
9439 | 0 | case SystemZ::VSBCBIQ: |
9440 | 0 | case SystemZ::VSBIQ: |
9441 | 0 | case SystemZ::VSEL: |
9442 | 0 | case SystemZ::VSTRSZB: |
9443 | 0 | case SystemZ::VSTRSZF: |
9444 | 0 | case SystemZ::VSTRSZH: |
9445 | 0 | case SystemZ::WFMADB: |
9446 | 0 | case SystemZ::WFMASB: |
9447 | 0 | case SystemZ::WFMAXB: |
9448 | 0 | case SystemZ::WFMSDB: |
9449 | 0 | case SystemZ::WFMSSB: |
9450 | 0 | case SystemZ::WFMSXB: |
9451 | 0 | case SystemZ::WFNMADB: |
9452 | 0 | case SystemZ::WFNMASB: |
9453 | 0 | case SystemZ::WFNMAXB: |
9454 | 0 | case SystemZ::WFNMSDB: |
9455 | 0 | case SystemZ::WFNMSSB: |
9456 | 0 | case SystemZ::WFNMSXB: { |
9457 | | // op: V1 |
9458 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9459 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9460 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9461 | | // op: V2 |
9462 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9463 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9464 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9465 | | // op: V3 |
9466 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9467 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9468 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9469 | | // op: V4 |
9470 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9471 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9472 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9473 | 0 | break; |
9474 | 0 | } |
9475 | 0 | case SystemZ::VFMA: |
9476 | 0 | case SystemZ::VFMS: |
9477 | 0 | case SystemZ::VFNMA: |
9478 | 0 | case SystemZ::VFNMS: { |
9479 | | // op: V1 |
9480 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9481 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9482 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9483 | | // op: V2 |
9484 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9485 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9486 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9487 | | // op: V3 |
9488 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9489 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9490 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9491 | | // op: V4 |
9492 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9493 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9494 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9495 | | // op: M5 |
9496 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9497 | 0 | op &= UINT64_C(15); |
9498 | 0 | op <<= 16; |
9499 | 0 | Value |= op; |
9500 | | // op: M6 |
9501 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
9502 | 0 | op &= UINT64_C(15); |
9503 | 0 | op <<= 24; |
9504 | 0 | Value |= op; |
9505 | 0 | break; |
9506 | 0 | } |
9507 | 0 | case SystemZ::VAC: |
9508 | 0 | case SystemZ::VACCC: |
9509 | 0 | case SystemZ::VGFMA: |
9510 | 0 | case SystemZ::VMAE: |
9511 | 0 | case SystemZ::VMAH: |
9512 | 0 | case SystemZ::VMAL: |
9513 | 0 | case SystemZ::VMALE: |
9514 | 0 | case SystemZ::VMALH: |
9515 | 0 | case SystemZ::VMALO: |
9516 | 0 | case SystemZ::VMAO: |
9517 | 0 | case SystemZ::VSBCBI: |
9518 | 0 | case SystemZ::VSBI: { |
9519 | | // op: V1 |
9520 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9521 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9522 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9523 | | // op: V2 |
9524 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9525 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9526 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9527 | | // op: V3 |
9528 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9529 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9530 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9531 | | // op: V4 |
9532 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9533 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9534 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9535 | | // op: M5 |
9536 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9537 | 0 | op &= UINT64_C(15); |
9538 | 0 | op <<= 24; |
9539 | 0 | Value |= op; |
9540 | 0 | break; |
9541 | 0 | } |
9542 | 0 | case SystemZ::VMSL: |
9543 | 0 | case SystemZ::VSTRC: |
9544 | 0 | case SystemZ::VSTRS: { |
9545 | | // op: V1 |
9546 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9547 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9548 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9549 | | // op: V2 |
9550 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9551 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9552 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9553 | | // op: V3 |
9554 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9555 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9556 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9557 | | // op: V4 |
9558 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9559 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9560 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9561 | | // op: M5 |
9562 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9563 | 0 | op &= UINT64_C(15); |
9564 | 0 | op <<= 24; |
9565 | 0 | Value |= op; |
9566 | | // op: M6 |
9567 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
9568 | 0 | op &= UINT64_C(15); |
9569 | 0 | op <<= 20; |
9570 | 0 | Value |= op; |
9571 | 0 | break; |
9572 | 0 | } |
9573 | 0 | case SystemZ::VSTRCZB: |
9574 | 0 | case SystemZ::VSTRCZF: |
9575 | 0 | case SystemZ::VSTRCZH: { |
9576 | | // op: V1 |
9577 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9578 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9579 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9580 | | // op: V2 |
9581 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9582 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9583 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9584 | | // op: V3 |
9585 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9586 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9587 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9588 | | // op: V4 |
9589 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9590 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9591 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9592 | | // op: M6 |
9593 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9594 | 0 | Value |= (op & UINT64_C(12)) << 20; |
9595 | 0 | Value |= (op & UINT64_C(1)) << 20; |
9596 | 0 | break; |
9597 | 0 | } |
9598 | 0 | case SystemZ::VSTRCZBS: |
9599 | 0 | case SystemZ::VSTRCZFS: |
9600 | 0 | case SystemZ::VSTRCZHS: { |
9601 | | // op: V1 |
9602 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9603 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9604 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9605 | | // op: V2 |
9606 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9607 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9608 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9609 | | // op: V3 |
9610 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9611 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9612 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9613 | | // op: V4 |
9614 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9615 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9616 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9617 | | // op: M6 |
9618 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9619 | 0 | op &= UINT64_C(12); |
9620 | 0 | op <<= 20; |
9621 | 0 | Value |= op; |
9622 | 0 | break; |
9623 | 0 | } |
9624 | 0 | case SystemZ::VSTRCBS: |
9625 | 0 | case SystemZ::VSTRCFS: |
9626 | 0 | case SystemZ::VSTRCHS: { |
9627 | | // op: V1 |
9628 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9629 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9630 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9631 | | // op: V2 |
9632 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9633 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9634 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9635 | | // op: V3 |
9636 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9637 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9638 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9639 | | // op: V4 |
9640 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9641 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9642 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9643 | | // op: M6 |
9644 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9645 | 0 | op &= UINT64_C(14); |
9646 | 0 | op <<= 20; |
9647 | 0 | Value |= op; |
9648 | 0 | break; |
9649 | 0 | } |
9650 | 0 | case SystemZ::VMSLG: |
9651 | 0 | case SystemZ::VSTRCB: |
9652 | 0 | case SystemZ::VSTRCF: |
9653 | 0 | case SystemZ::VSTRCH: |
9654 | 0 | case SystemZ::VSTRSB: |
9655 | 0 | case SystemZ::VSTRSF: |
9656 | 0 | case SystemZ::VSTRSH: { |
9657 | | // op: V1 |
9658 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9659 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9660 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9661 | | // op: V2 |
9662 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9663 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9664 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9665 | | // op: V3 |
9666 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9667 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9668 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9669 | | // op: V4 |
9670 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9671 | 0 | Value |= (op & UINT64_C(15)) << 12; |
9672 | 0 | Value |= (op & UINT64_C(16)) << 4; |
9673 | | // op: M6 |
9674 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
9675 | 0 | op &= UINT64_C(15); |
9676 | 0 | op <<= 20; |
9677 | 0 | Value |= op; |
9678 | 0 | break; |
9679 | 0 | } |
9680 | 0 | case SystemZ::VERIMB: |
9681 | 0 | case SystemZ::VERIMF: |
9682 | 0 | case SystemZ::VERIMG: |
9683 | 0 | case SystemZ::VERIMH: { |
9684 | | // op: V1 |
9685 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9686 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9687 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9688 | | // op: V2 |
9689 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9690 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9691 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9692 | | // op: V3 |
9693 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9694 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9695 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9696 | | // op: I4 |
9697 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 4, Fixups, STI); |
9698 | 0 | op &= UINT64_C(255); |
9699 | 0 | op <<= 16; |
9700 | 0 | Value |= op; |
9701 | 0 | break; |
9702 | 0 | } |
9703 | 0 | case SystemZ::VERIM: { |
9704 | | // op: V1 |
9705 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9706 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9707 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9708 | | // op: V2 |
9709 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9710 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9711 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9712 | | // op: V3 |
9713 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9714 | 0 | Value |= (op & UINT64_C(15)) << 28; |
9715 | 0 | Value |= (op & UINT64_C(16)) << 5; |
9716 | | // op: I4 |
9717 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 4, Fixups, STI); |
9718 | 0 | op &= UINT64_C(255); |
9719 | 0 | op <<= 16; |
9720 | 0 | Value |= op; |
9721 | | // op: M5 |
9722 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
9723 | 0 | op &= UINT64_C(15); |
9724 | 0 | op <<= 12; |
9725 | 0 | Value |= op; |
9726 | 0 | break; |
9727 | 0 | } |
9728 | 0 | case SystemZ::VSCEG: { |
9729 | | // op: V1 |
9730 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9731 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9732 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9733 | | // op: V2 |
9734 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9735 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9736 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9737 | | // op: B2 |
9738 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9739 | 0 | op &= UINT64_C(15); |
9740 | 0 | op <<= 28; |
9741 | 0 | Value |= op; |
9742 | | // op: D2 |
9743 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
9744 | 0 | op &= UINT64_C(4095); |
9745 | 0 | op <<= 16; |
9746 | 0 | Value |= op; |
9747 | | // op: M3 |
9748 | 0 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, 4, Fixups, STI); |
9749 | 0 | op &= UINT64_C(15); |
9750 | 0 | op <<= 12; |
9751 | 0 | Value |= op; |
9752 | 0 | break; |
9753 | 0 | } |
9754 | 0 | case SystemZ::VSCEF: { |
9755 | | // op: V1 |
9756 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9757 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9758 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9759 | | // op: V2 |
9760 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9761 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9762 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9763 | | // op: B2 |
9764 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9765 | 0 | op &= UINT64_C(15); |
9766 | 0 | op <<= 28; |
9767 | 0 | Value |= op; |
9768 | | // op: D2 |
9769 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
9770 | 0 | op &= UINT64_C(4095); |
9771 | 0 | op <<= 16; |
9772 | 0 | Value |= op; |
9773 | | // op: M3 |
9774 | 0 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, 4, Fixups, STI); |
9775 | 0 | op &= UINT64_C(15); |
9776 | 0 | op <<= 12; |
9777 | 0 | Value |= op; |
9778 | 0 | break; |
9779 | 0 | } |
9780 | 0 | case SystemZ::VGEG: { |
9781 | | // op: V1 |
9782 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9783 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9784 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9785 | | // op: V2 |
9786 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
9787 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9788 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9789 | | // op: B2 |
9790 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9791 | 0 | op &= UINT64_C(15); |
9792 | 0 | op <<= 28; |
9793 | 0 | Value |= op; |
9794 | | // op: D2 |
9795 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
9796 | 0 | op &= UINT64_C(4095); |
9797 | 0 | op <<= 16; |
9798 | 0 | Value |= op; |
9799 | | // op: M3 |
9800 | 0 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, 5, Fixups, STI); |
9801 | 0 | op &= UINT64_C(15); |
9802 | 0 | op <<= 12; |
9803 | 0 | Value |= op; |
9804 | 0 | break; |
9805 | 0 | } |
9806 | 0 | case SystemZ::VGEF: { |
9807 | | // op: V1 |
9808 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9809 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9810 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9811 | | // op: V2 |
9812 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
9813 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9814 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9815 | | // op: B2 |
9816 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
9817 | 0 | op &= UINT64_C(15); |
9818 | 0 | op <<= 28; |
9819 | 0 | Value |= op; |
9820 | | // op: D2 |
9821 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
9822 | 0 | op &= UINT64_C(4095); |
9823 | 0 | op <<= 16; |
9824 | 0 | Value |= op; |
9825 | | // op: M3 |
9826 | 0 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, 5, Fixups, STI); |
9827 | 0 | op &= UINT64_C(15); |
9828 | 0 | op <<= 12; |
9829 | 0 | Value |= op; |
9830 | 0 | break; |
9831 | 0 | } |
9832 | 0 | case SystemZ::VREPB: |
9833 | 0 | case SystemZ::VREPF: |
9834 | 0 | case SystemZ::VREPG: |
9835 | 0 | case SystemZ::VREPH: { |
9836 | | // op: V1 |
9837 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9838 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9839 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9840 | | // op: V3 |
9841 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9842 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9843 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9844 | | // op: I2 |
9845 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 2, Fixups, STI); |
9846 | 0 | op &= UINT64_C(65535); |
9847 | 0 | op <<= 16; |
9848 | 0 | Value |= op; |
9849 | 0 | break; |
9850 | 0 | } |
9851 | 0 | case SystemZ::VREP: { |
9852 | | // op: V1 |
9853 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9854 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9855 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9856 | | // op: V3 |
9857 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9858 | 0 | Value |= (op & UINT64_C(15)) << 32; |
9859 | 0 | Value |= (op & UINT64_C(16)) << 6; |
9860 | | // op: I2 |
9861 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 2, Fixups, STI); |
9862 | 0 | op &= UINT64_C(65535); |
9863 | 0 | op <<= 16; |
9864 | 0 | Value |= op; |
9865 | | // op: M4 |
9866 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 3, Fixups, STI); |
9867 | 0 | op &= UINT64_C(15); |
9868 | 0 | op <<= 12; |
9869 | 0 | Value |= op; |
9870 | 0 | break; |
9871 | 0 | } |
9872 | 0 | case SystemZ::VL: |
9873 | 0 | case SystemZ::VLBRF: |
9874 | 0 | case SystemZ::VLBRG: |
9875 | 0 | case SystemZ::VLBRH: |
9876 | 0 | case SystemZ::VLBRQ: |
9877 | 0 | case SystemZ::VLBRREPF: |
9878 | 0 | case SystemZ::VLBRREPG: |
9879 | 0 | case SystemZ::VLBRREPH: |
9880 | 0 | case SystemZ::VLERF: |
9881 | 0 | case SystemZ::VLERG: |
9882 | 0 | case SystemZ::VLERH: |
9883 | 0 | case SystemZ::VLLEBRZE: |
9884 | 0 | case SystemZ::VLLEBRZF: |
9885 | 0 | case SystemZ::VLLEBRZG: |
9886 | 0 | case SystemZ::VLLEBRZH: |
9887 | 0 | case SystemZ::VLLEZB: |
9888 | 0 | case SystemZ::VLLEZF: |
9889 | 0 | case SystemZ::VLLEZG: |
9890 | 0 | case SystemZ::VLLEZH: |
9891 | 0 | case SystemZ::VLLEZLF: |
9892 | 0 | case SystemZ::VLREPB: |
9893 | 0 | case SystemZ::VLREPF: |
9894 | 0 | case SystemZ::VLREPG: |
9895 | 0 | case SystemZ::VLREPH: |
9896 | 0 | case SystemZ::VST: |
9897 | 0 | case SystemZ::VSTBRF: |
9898 | 0 | case SystemZ::VSTBRG: |
9899 | 0 | case SystemZ::VSTBRH: |
9900 | 0 | case SystemZ::VSTBRQ: |
9901 | 0 | case SystemZ::VSTERF: |
9902 | 0 | case SystemZ::VSTERG: |
9903 | 0 | case SystemZ::VSTERH: { |
9904 | | // op: V1 |
9905 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9906 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9907 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9908 | | // op: X2 |
9909 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9910 | 0 | op &= UINT64_C(15); |
9911 | 0 | op <<= 32; |
9912 | 0 | Value |= op; |
9913 | | // op: B2 |
9914 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9915 | 0 | op &= UINT64_C(15); |
9916 | 0 | op <<= 28; |
9917 | 0 | Value |= op; |
9918 | | // op: D2 |
9919 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
9920 | 0 | op &= UINT64_C(4095); |
9921 | 0 | op <<= 16; |
9922 | 0 | Value |= op; |
9923 | 0 | break; |
9924 | 0 | } |
9925 | 0 | case SystemZ::VSTEBRG: |
9926 | 0 | case SystemZ::VSTEG: { |
9927 | | // op: V1 |
9928 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9929 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9930 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9931 | | // op: X2 |
9932 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9933 | 0 | op &= UINT64_C(15); |
9934 | 0 | op <<= 32; |
9935 | 0 | Value |= op; |
9936 | | // op: B2 |
9937 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9938 | 0 | op &= UINT64_C(15); |
9939 | 0 | op <<= 28; |
9940 | 0 | Value |= op; |
9941 | | // op: D2 |
9942 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
9943 | 0 | op &= UINT64_C(4095); |
9944 | 0 | op <<= 16; |
9945 | 0 | Value |= op; |
9946 | | // op: M3 |
9947 | 0 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, 4, Fixups, STI); |
9948 | 0 | op &= UINT64_C(15); |
9949 | 0 | op <<= 12; |
9950 | 0 | Value |= op; |
9951 | 0 | break; |
9952 | 0 | } |
9953 | 0 | case SystemZ::VSTEBRF: |
9954 | 0 | case SystemZ::VSTEF: { |
9955 | | // op: V1 |
9956 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9957 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9958 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9959 | | // op: X2 |
9960 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9961 | 0 | op &= UINT64_C(15); |
9962 | 0 | op <<= 32; |
9963 | 0 | Value |= op; |
9964 | | // op: B2 |
9965 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9966 | 0 | op &= UINT64_C(15); |
9967 | 0 | op <<= 28; |
9968 | 0 | Value |= op; |
9969 | | // op: D2 |
9970 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
9971 | 0 | op &= UINT64_C(4095); |
9972 | 0 | op <<= 16; |
9973 | 0 | Value |= op; |
9974 | | // op: M3 |
9975 | 0 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, 4, Fixups, STI); |
9976 | 0 | op &= UINT64_C(15); |
9977 | 0 | op <<= 12; |
9978 | 0 | Value |= op; |
9979 | 0 | break; |
9980 | 0 | } |
9981 | 0 | case SystemZ::VSTEBRH: |
9982 | 0 | case SystemZ::VSTEH: { |
9983 | | // op: V1 |
9984 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
9985 | 0 | Value |= (op & UINT64_C(15)) << 36; |
9986 | 0 | Value |= (op & UINT64_C(16)) << 7; |
9987 | | // op: X2 |
9988 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
9989 | 0 | op &= UINT64_C(15); |
9990 | 0 | op <<= 32; |
9991 | 0 | Value |= op; |
9992 | | // op: B2 |
9993 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
9994 | 0 | op &= UINT64_C(15); |
9995 | 0 | op <<= 28; |
9996 | 0 | Value |= op; |
9997 | | // op: D2 |
9998 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
9999 | 0 | op &= UINT64_C(4095); |
10000 | 0 | op <<= 16; |
10001 | 0 | Value |= op; |
10002 | | // op: M3 |
10003 | 0 | op = getImmOpValue<SystemZ::FK_390_U3Imm>(MI, 4, Fixups, STI); |
10004 | 0 | op &= UINT64_C(15); |
10005 | 0 | op <<= 12; |
10006 | 0 | Value |= op; |
10007 | 0 | break; |
10008 | 0 | } |
10009 | 0 | case SystemZ::VLAlign: |
10010 | 0 | case SystemZ::VLBB: |
10011 | 0 | case SystemZ::VLBR: |
10012 | 0 | case SystemZ::VLBRREP: |
10013 | 0 | case SystemZ::VLER: |
10014 | 0 | case SystemZ::VLLEBRZ: |
10015 | 0 | case SystemZ::VLLEZ: |
10016 | 0 | case SystemZ::VLREP: |
10017 | 0 | case SystemZ::VSTAlign: |
10018 | 0 | case SystemZ::VSTBR: |
10019 | 0 | case SystemZ::VSTEB: |
10020 | 0 | case SystemZ::VSTER: { |
10021 | | // op: V1 |
10022 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10023 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10024 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10025 | | // op: X2 |
10026 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
10027 | 0 | op &= UINT64_C(15); |
10028 | 0 | op <<= 32; |
10029 | 0 | Value |= op; |
10030 | | // op: B2 |
10031 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
10032 | 0 | op &= UINT64_C(15); |
10033 | 0 | op <<= 28; |
10034 | 0 | Value |= op; |
10035 | | // op: D2 |
10036 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 2, Fixups, STI); |
10037 | 0 | op &= UINT64_C(4095); |
10038 | 0 | op <<= 16; |
10039 | 0 | Value |= op; |
10040 | | // op: M3 |
10041 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
10042 | 0 | op &= UINT64_C(15); |
10043 | 0 | op <<= 12; |
10044 | 0 | Value |= op; |
10045 | 0 | break; |
10046 | 0 | } |
10047 | 0 | case SystemZ::VLEBRG: |
10048 | 0 | case SystemZ::VLEG: { |
10049 | | // op: V1 |
10050 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10051 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10052 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10053 | | // op: X2 |
10054 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
10055 | 0 | op &= UINT64_C(15); |
10056 | 0 | op <<= 32; |
10057 | 0 | Value |= op; |
10058 | | // op: B2 |
10059 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10060 | 0 | op &= UINT64_C(15); |
10061 | 0 | op <<= 28; |
10062 | 0 | Value |= op; |
10063 | | // op: D2 |
10064 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10065 | 0 | op &= UINT64_C(4095); |
10066 | 0 | op <<= 16; |
10067 | 0 | Value |= op; |
10068 | | // op: M3 |
10069 | 0 | op = getImmOpValue<SystemZ::FK_390_U1Imm>(MI, 5, Fixups, STI); |
10070 | 0 | op &= UINT64_C(15); |
10071 | 0 | op <<= 12; |
10072 | 0 | Value |= op; |
10073 | 0 | break; |
10074 | 0 | } |
10075 | 0 | case SystemZ::VLEBRF: |
10076 | 0 | case SystemZ::VLEF: { |
10077 | | // op: V1 |
10078 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10079 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10080 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10081 | | // op: X2 |
10082 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
10083 | 0 | op &= UINT64_C(15); |
10084 | 0 | op <<= 32; |
10085 | 0 | Value |= op; |
10086 | | // op: B2 |
10087 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10088 | 0 | op &= UINT64_C(15); |
10089 | 0 | op <<= 28; |
10090 | 0 | Value |= op; |
10091 | | // op: D2 |
10092 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10093 | 0 | op &= UINT64_C(4095); |
10094 | 0 | op <<= 16; |
10095 | 0 | Value |= op; |
10096 | | // op: M3 |
10097 | 0 | op = getImmOpValue<SystemZ::FK_390_U2Imm>(MI, 5, Fixups, STI); |
10098 | 0 | op &= UINT64_C(15); |
10099 | 0 | op <<= 12; |
10100 | 0 | Value |= op; |
10101 | 0 | break; |
10102 | 0 | } |
10103 | 0 | case SystemZ::VLEBRH: |
10104 | 0 | case SystemZ::VLEH: { |
10105 | | // op: V1 |
10106 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10107 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10108 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10109 | | // op: X2 |
10110 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
10111 | 0 | op &= UINT64_C(15); |
10112 | 0 | op <<= 32; |
10113 | 0 | Value |= op; |
10114 | | // op: B2 |
10115 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10116 | 0 | op &= UINT64_C(15); |
10117 | 0 | op <<= 28; |
10118 | 0 | Value |= op; |
10119 | | // op: D2 |
10120 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10121 | 0 | op &= UINT64_C(4095); |
10122 | 0 | op <<= 16; |
10123 | 0 | Value |= op; |
10124 | | // op: M3 |
10125 | 0 | op = getImmOpValue<SystemZ::FK_390_U3Imm>(MI, 5, Fixups, STI); |
10126 | 0 | op &= UINT64_C(15); |
10127 | 0 | op <<= 12; |
10128 | 0 | Value |= op; |
10129 | 0 | break; |
10130 | 0 | } |
10131 | 0 | case SystemZ::VLEB: { |
10132 | | // op: V1 |
10133 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10134 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10135 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10136 | | // op: X2 |
10137 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
10138 | 0 | op &= UINT64_C(15); |
10139 | 0 | op <<= 32; |
10140 | 0 | Value |= op; |
10141 | | // op: B2 |
10142 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10143 | 0 | op &= UINT64_C(15); |
10144 | 0 | op <<= 28; |
10145 | 0 | Value |= op; |
10146 | | // op: D2 |
10147 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10148 | 0 | op &= UINT64_C(4095); |
10149 | 0 | op <<= 16; |
10150 | 0 | Value |= op; |
10151 | | // op: M3 |
10152 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
10153 | 0 | op &= UINT64_C(15); |
10154 | 0 | op <<= 12; |
10155 | 0 | Value |= op; |
10156 | 0 | break; |
10157 | 0 | } |
10158 | 0 | case SystemZ::InsnVSI: { |
10159 | | // op: V1 |
10160 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
10161 | 0 | Value |= (op & UINT64_C(15)) << 12; |
10162 | 0 | Value |= (op & UINT64_C(16)) << 4; |
10163 | | // op: B2 |
10164 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10165 | 0 | op &= UINT64_C(15); |
10166 | 0 | op <<= 28; |
10167 | 0 | Value |= op; |
10168 | | // op: D2 |
10169 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10170 | 0 | op &= UINT64_C(4095); |
10171 | 0 | op <<= 16; |
10172 | 0 | Value |= op; |
10173 | | // op: I3 |
10174 | 0 | op = getImmOpValue<SystemZ::FK_390_U8Imm>(MI, 4, Fixups, STI); |
10175 | 0 | op &= UINT64_C(255); |
10176 | 0 | op <<= 32; |
10177 | 0 | Value |= op; |
10178 | | // op: enc |
10179 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
10180 | 0 | Value |= (op & UINT64_C(280375465082880)); |
10181 | 0 | Value |= (op & UINT64_C(255)); |
10182 | 0 | break; |
10183 | 0 | } |
10184 | 0 | case SystemZ::InsnVRI: { |
10185 | | // op: V1 |
10186 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
10187 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10188 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10189 | | // op: V2 |
10190 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10191 | 0 | Value |= (op & UINT64_C(15)) << 32; |
10192 | 0 | Value |= (op & UINT64_C(16)) << 6; |
10193 | | // op: I3 |
10194 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10195 | 0 | op &= UINT64_C(4095); |
10196 | 0 | op <<= 20; |
10197 | 0 | Value |= op; |
10198 | | // op: M4 |
10199 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
10200 | 0 | op &= UINT64_C(15); |
10201 | 0 | op <<= 12; |
10202 | 0 | Value |= op; |
10203 | | // op: M5 |
10204 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
10205 | 0 | op &= UINT64_C(15); |
10206 | 0 | op <<= 16; |
10207 | 0 | Value |= op; |
10208 | | // op: enc |
10209 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
10210 | 0 | Value |= (op & UINT64_C(280375465082880)); |
10211 | 0 | Value |= (op & UINT64_C(255)); |
10212 | 0 | break; |
10213 | 0 | } |
10214 | 0 | case SystemZ::InsnVRR: { |
10215 | | // op: V1 |
10216 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
10217 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10218 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10219 | | // op: V2 |
10220 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10221 | 0 | Value |= (op & UINT64_C(15)) << 32; |
10222 | 0 | Value |= (op & UINT64_C(16)) << 6; |
10223 | | // op: V3 |
10224 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
10225 | 0 | Value |= (op & UINT64_C(15)) << 28; |
10226 | 0 | Value |= (op & UINT64_C(16)) << 5; |
10227 | | // op: M4 |
10228 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 4, Fixups, STI); |
10229 | 0 | op &= UINT64_C(15); |
10230 | 0 | op <<= 12; |
10231 | 0 | Value |= op; |
10232 | | // op: M5 |
10233 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
10234 | 0 | op &= UINT64_C(15); |
10235 | 0 | op <<= 16; |
10236 | 0 | Value |= op; |
10237 | | // op: M6 |
10238 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 6, Fixups, STI); |
10239 | 0 | op &= UINT64_C(15); |
10240 | 0 | op <<= 20; |
10241 | 0 | Value |= op; |
10242 | | // op: enc |
10243 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
10244 | 0 | Value |= (op & UINT64_C(280375465082880)); |
10245 | 0 | Value |= (op & UINT64_C(255)); |
10246 | 0 | break; |
10247 | 0 | } |
10248 | 0 | case SystemZ::InsnVRV: { |
10249 | | // op: V1 |
10250 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
10251 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10252 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10253 | | // op: V2 |
10254 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
10255 | 0 | Value |= (op & UINT64_C(15)) << 32; |
10256 | 0 | Value |= (op & UINT64_C(16)) << 6; |
10257 | | // op: B2 |
10258 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10259 | 0 | op &= UINT64_C(15); |
10260 | 0 | op <<= 28; |
10261 | 0 | Value |= op; |
10262 | | // op: D2 |
10263 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10264 | 0 | op &= UINT64_C(4095); |
10265 | 0 | op <<= 16; |
10266 | 0 | Value |= op; |
10267 | | // op: M3 |
10268 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
10269 | 0 | op &= UINT64_C(15); |
10270 | 0 | op <<= 12; |
10271 | 0 | Value |= op; |
10272 | | // op: enc |
10273 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
10274 | 0 | Value |= (op & UINT64_C(280375465082880)); |
10275 | 0 | Value |= (op & UINT64_C(255)); |
10276 | 0 | break; |
10277 | 0 | } |
10278 | 0 | case SystemZ::InsnVRX: { |
10279 | | // op: V1 |
10280 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
10281 | 0 | Value |= (op & UINT64_C(15)) << 36; |
10282 | 0 | Value |= (op & UINT64_C(16)) << 7; |
10283 | | // op: X2 |
10284 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
10285 | 0 | op &= UINT64_C(15); |
10286 | 0 | op <<= 32; |
10287 | 0 | Value |= op; |
10288 | | // op: B2 |
10289 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10290 | 0 | op &= UINT64_C(15); |
10291 | 0 | op <<= 28; |
10292 | 0 | Value |= op; |
10293 | | // op: D2 |
10294 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 3, Fixups, STI); |
10295 | 0 | op &= UINT64_C(4095); |
10296 | 0 | op <<= 16; |
10297 | 0 | Value |= op; |
10298 | | // op: M3 |
10299 | 0 | op = getImmOpValue<SystemZ::FK_390_U4Imm>(MI, 5, Fixups, STI); |
10300 | 0 | op &= UINT64_C(15); |
10301 | 0 | op <<= 12; |
10302 | 0 | Value |= op; |
10303 | | // op: enc |
10304 | 0 | op = getImmOpValue<SystemZ::FK_390_U48Imm>(MI, 0, Fixups, STI); |
10305 | 0 | Value |= (op & UINT64_C(280375465082880)); |
10306 | 0 | Value |= (op & UINT64_C(255)); |
10307 | 0 | break; |
10308 | 0 | } |
10309 | 0 | case SystemZ::B: |
10310 | 0 | case SystemZ::BAsmE: |
10311 | 0 | case SystemZ::BAsmH: |
10312 | 0 | case SystemZ::BAsmHE: |
10313 | 0 | case SystemZ::BAsmL: |
10314 | 0 | case SystemZ::BAsmLE: |
10315 | 0 | case SystemZ::BAsmLH: |
10316 | 0 | case SystemZ::BAsmM: |
10317 | 0 | case SystemZ::BAsmNE: |
10318 | 0 | case SystemZ::BAsmNH: |
10319 | 0 | case SystemZ::BAsmNHE: |
10320 | 0 | case SystemZ::BAsmNL: |
10321 | 0 | case SystemZ::BAsmNLE: |
10322 | 0 | case SystemZ::BAsmNLH: |
10323 | 0 | case SystemZ::BAsmNM: |
10324 | 0 | case SystemZ::BAsmNO: |
10325 | 0 | case SystemZ::BAsmNP: |
10326 | 0 | case SystemZ::BAsmNZ: |
10327 | 0 | case SystemZ::BAsmO: |
10328 | 0 | case SystemZ::BAsmP: |
10329 | 0 | case SystemZ::BAsmZ: { |
10330 | | // op: X2 |
10331 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10332 | 0 | op &= UINT64_C(15); |
10333 | 0 | op <<= 16; |
10334 | 0 | Value |= op; |
10335 | | // op: B2 |
10336 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10337 | 0 | op &= UINT64_C(15); |
10338 | 0 | op <<= 12; |
10339 | 0 | Value |= op; |
10340 | | // op: D2 |
10341 | 0 | op = getImmOpValue<SystemZ::FK_390_U12Imm>(MI, 1, Fixups, STI); |
10342 | 0 | op &= UINT64_C(4095); |
10343 | 0 | Value |= op; |
10344 | 0 | break; |
10345 | 0 | } |
10346 | 0 | case SystemZ::BI: |
10347 | 0 | case SystemZ::BIAsmE: |
10348 | 0 | case SystemZ::BIAsmH: |
10349 | 0 | case SystemZ::BIAsmHE: |
10350 | 0 | case SystemZ::BIAsmL: |
10351 | 0 | case SystemZ::BIAsmLE: |
10352 | 0 | case SystemZ::BIAsmLH: |
10353 | 0 | case SystemZ::BIAsmM: |
10354 | 0 | case SystemZ::BIAsmNE: |
10355 | 0 | case SystemZ::BIAsmNH: |
10356 | 0 | case SystemZ::BIAsmNHE: |
10357 | 0 | case SystemZ::BIAsmNL: |
10358 | 0 | case SystemZ::BIAsmNLE: |
10359 | 0 | case SystemZ::BIAsmNLH: |
10360 | 0 | case SystemZ::BIAsmNM: |
10361 | 0 | case SystemZ::BIAsmNO: |
10362 | 0 | case SystemZ::BIAsmNP: |
10363 | 0 | case SystemZ::BIAsmNZ: |
10364 | 0 | case SystemZ::BIAsmO: |
10365 | 0 | case SystemZ::BIAsmP: |
10366 | 0 | case SystemZ::BIAsmZ: { |
10367 | | // op: X2 |
10368 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
10369 | 0 | op &= UINT64_C(15); |
10370 | 0 | op <<= 32; |
10371 | 0 | Value |= op; |
10372 | | // op: B2 |
10373 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
10374 | 0 | op &= UINT64_C(15); |
10375 | 0 | op <<= 28; |
10376 | 0 | Value |= op; |
10377 | | // op: D2 |
10378 | 0 | op = getImmOpValue<SystemZ::FK_390_S20Imm>(MI, 1, Fixups, STI); |
10379 | 0 | Value |= (op & UINT64_C(4095)) << 16; |
10380 | 0 | Value |= (op & UINT64_C(1044480)) >> 4; |
10381 | 0 | break; |
10382 | 0 | } |
10383 | 0 | case SystemZ::InsnE: { |
10384 | | // op: enc |
10385 | 0 | op = getImmOpValue<SystemZ::FK_390_U16Imm>(MI, 0, Fixups, STI); |
10386 | 0 | op &= UINT64_C(65535); |
10387 | 0 | Value |= op; |
10388 | 0 | break; |
10389 | 0 | } |
10390 | 0 | default: |
10391 | 0 | std::string msg; |
10392 | 0 | raw_string_ostream Msg(msg); |
10393 | 0 | Msg << "Not supported instr: " << MI; |
10394 | 0 | report_fatal_error(Msg.str().c_str()); |
10395 | 0 | } |
10396 | 0 | return Value; |
10397 | 0 | } |
10398 | | |
10399 | | #ifdef GET_OPERAND_BIT_OFFSET |
10400 | | #undef GET_OPERAND_BIT_OFFSET |
10401 | | |
10402 | | uint32_t SystemZMCCodeEmitter::getOperandBitOffset(const MCInst &MI, |
10403 | | unsigned OpNum, |
10404 | 0 | const MCSubtargetInfo &STI) const { |
10405 | 0 | switch (MI.getOpcode()) { |
10406 | 0 | case SystemZ::CSCH: |
10407 | 0 | case SystemZ::HSCH: |
10408 | 0 | case SystemZ::IPK: |
10409 | 0 | case SystemZ::NNPA: |
10410 | 0 | case SystemZ::NOP_bare: |
10411 | 0 | case SystemZ::PALB: |
10412 | 0 | case SystemZ::PCC: |
10413 | 0 | case SystemZ::PCKMO: |
10414 | 0 | case SystemZ::PFPO: |
10415 | 0 | case SystemZ::PR: |
10416 | 0 | case SystemZ::PTFF: |
10417 | 0 | case SystemZ::PTLB: |
10418 | 0 | case SystemZ::RCHP: |
10419 | 0 | case SystemZ::RSCH: |
10420 | 0 | case SystemZ::SAL: |
10421 | 0 | case SystemZ::SAM24: |
10422 | 0 | case SystemZ::SAM31: |
10423 | 0 | case SystemZ::SAM64: |
10424 | 0 | case SystemZ::SCHM: |
10425 | 0 | case SystemZ::SCKPF: |
10426 | 0 | case SystemZ::TAM: |
10427 | 0 | case SystemZ::TEND: |
10428 | 0 | case SystemZ::TRAP2: |
10429 | 0 | case SystemZ::UPT: |
10430 | 0 | case SystemZ::XSCH: { |
10431 | 0 | break; |
10432 | 0 | } |
10433 | 0 | case SystemZ::CLI: |
10434 | 0 | case SystemZ::MC: |
10435 | 0 | case SystemZ::MVI: |
10436 | 0 | case SystemZ::NI: |
10437 | 0 | case SystemZ::OI: |
10438 | 0 | case SystemZ::STNSM: |
10439 | 0 | case SystemZ::STOSM: |
10440 | 0 | case SystemZ::TM: |
10441 | 0 | case SystemZ::XI: { |
10442 | 0 | switch (OpNum) { |
10443 | 0 | case 0: |
10444 | | // op: B1 |
10445 | 0 | return 12; |
10446 | 0 | case 1: |
10447 | | // op: D1 |
10448 | 0 | return 0; |
10449 | 0 | case 2: |
10450 | | // op: I2 |
10451 | 0 | return 16; |
10452 | 0 | } |
10453 | 0 | break; |
10454 | 0 | } |
10455 | 0 | case SystemZ::PKA: |
10456 | 0 | case SystemZ::PKU: { |
10457 | 0 | switch (OpNum) { |
10458 | 0 | case 0: |
10459 | | // op: B1 |
10460 | 0 | return 28; |
10461 | 0 | case 1: |
10462 | | // op: D1 |
10463 | 0 | return 16; |
10464 | 0 | case 2: |
10465 | | // op: B2 |
10466 | 0 | return 12; |
10467 | 0 | case 3: |
10468 | | // op: D2 |
10469 | 0 | return 0; |
10470 | 0 | case 4: |
10471 | | // op: L2 |
10472 | 0 | return 32; |
10473 | 0 | } |
10474 | 0 | break; |
10475 | 0 | } |
10476 | 0 | case SystemZ::CSST: |
10477 | 0 | case SystemZ::ECTG: |
10478 | 0 | case SystemZ::MVCOS: { |
10479 | 0 | switch (OpNum) { |
10480 | 0 | case 0: |
10481 | | // op: B1 |
10482 | 0 | return 28; |
10483 | 0 | case 1: |
10484 | | // op: D1 |
10485 | 0 | return 16; |
10486 | 0 | case 2: |
10487 | | // op: B2 |
10488 | 0 | return 12; |
10489 | 0 | case 3: |
10490 | | // op: D2 |
10491 | 0 | return 0; |
10492 | 0 | case 4: |
10493 | | // op: R3 |
10494 | 0 | return 36; |
10495 | 0 | } |
10496 | 0 | break; |
10497 | 0 | } |
10498 | 0 | case SystemZ::LASP: |
10499 | 0 | case SystemZ::MVCDK: |
10500 | 0 | case SystemZ::MVCRL: |
10501 | 0 | case SystemZ::MVCSK: |
10502 | 0 | case SystemZ::STRAG: |
10503 | 0 | case SystemZ::TPROT: { |
10504 | 0 | switch (OpNum) { |
10505 | 0 | case 0: |
10506 | | // op: B1 |
10507 | 0 | return 28; |
10508 | 0 | case 1: |
10509 | | // op: D1 |
10510 | 0 | return 16; |
10511 | 0 | case 2: |
10512 | | // op: B2 |
10513 | 0 | return 12; |
10514 | 0 | case 3: |
10515 | | // op: D2 |
10516 | 0 | return 0; |
10517 | 0 | } |
10518 | 0 | break; |
10519 | 0 | } |
10520 | 0 | case SystemZ::CGHSI: |
10521 | 0 | case SystemZ::CHHSI: |
10522 | 0 | case SystemZ::CHSI: |
10523 | 0 | case SystemZ::CLFHSI: |
10524 | 0 | case SystemZ::CLGHSI: |
10525 | 0 | case SystemZ::CLHHSI: |
10526 | 0 | case SystemZ::MVGHI: |
10527 | 0 | case SystemZ::MVHHI: |
10528 | 0 | case SystemZ::MVHI: |
10529 | 0 | case SystemZ::TBEGIN: |
10530 | 0 | case SystemZ::TBEGINC: { |
10531 | 0 | switch (OpNum) { |
10532 | 0 | case 0: |
10533 | | // op: B1 |
10534 | 0 | return 28; |
10535 | 0 | case 1: |
10536 | | // op: D1 |
10537 | 0 | return 16; |
10538 | 0 | case 2: |
10539 | | // op: I2 |
10540 | 0 | return 0; |
10541 | 0 | } |
10542 | 0 | break; |
10543 | 0 | } |
10544 | 0 | case SystemZ::CLC: |
10545 | 0 | case SystemZ::ED: |
10546 | 0 | case SystemZ::EDMK: |
10547 | 0 | case SystemZ::MVC: |
10548 | 0 | case SystemZ::MVCIN: |
10549 | 0 | case SystemZ::MVN: |
10550 | 0 | case SystemZ::MVZ: |
10551 | 0 | case SystemZ::NC: |
10552 | 0 | case SystemZ::OC: |
10553 | 0 | case SystemZ::TR: |
10554 | 0 | case SystemZ::TRT: |
10555 | 0 | case SystemZ::TRTR: |
10556 | 0 | case SystemZ::UNPKA: |
10557 | 0 | case SystemZ::UNPKU: |
10558 | 0 | case SystemZ::XC: { |
10559 | 0 | switch (OpNum) { |
10560 | 0 | case 0: |
10561 | | // op: B1 |
10562 | 0 | return 28; |
10563 | 0 | case 1: |
10564 | | // op: D1 |
10565 | 0 | return 16; |
10566 | 0 | case 2: |
10567 | | // op: L1 |
10568 | 0 | return 32; |
10569 | 0 | case 3: |
10570 | | // op: B2 |
10571 | 0 | return 12; |
10572 | 0 | case 4: |
10573 | | // op: D2 |
10574 | 0 | return 0; |
10575 | 0 | } |
10576 | 0 | break; |
10577 | 0 | } |
10578 | 0 | case SystemZ::SRP: { |
10579 | 0 | switch (OpNum) { |
10580 | 0 | case 0: |
10581 | | // op: B1 |
10582 | 0 | return 28; |
10583 | 0 | case 1: |
10584 | | // op: D1 |
10585 | 0 | return 16; |
10586 | 0 | case 2: |
10587 | | // op: L1 |
10588 | 0 | return 36; |
10589 | 0 | case 3: |
10590 | | // op: B2 |
10591 | 0 | return 12; |
10592 | 0 | case 4: |
10593 | | // op: D2 |
10594 | 0 | return 0; |
10595 | 0 | case 5: |
10596 | | // op: I3 |
10597 | 0 | return 32; |
10598 | 0 | } |
10599 | 0 | break; |
10600 | 0 | } |
10601 | 0 | case SystemZ::AP: |
10602 | 0 | case SystemZ::CP: |
10603 | 0 | case SystemZ::DP: |
10604 | 0 | case SystemZ::MP: |
10605 | 0 | case SystemZ::MVO: |
10606 | 0 | case SystemZ::PACK: |
10607 | 0 | case SystemZ::SP: |
10608 | 0 | case SystemZ::UNPK: |
10609 | 0 | case SystemZ::ZAP: { |
10610 | 0 | switch (OpNum) { |
10611 | 0 | case 0: |
10612 | | // op: B1 |
10613 | 0 | return 28; |
10614 | 0 | case 1: |
10615 | | // op: D1 |
10616 | 0 | return 16; |
10617 | 0 | case 2: |
10618 | | // op: L1 |
10619 | 0 | return 36; |
10620 | 0 | case 3: |
10621 | | // op: B2 |
10622 | 0 | return 12; |
10623 | 0 | case 4: |
10624 | | // op: D2 |
10625 | 0 | return 0; |
10626 | 0 | case 5: |
10627 | | // op: L2 |
10628 | 0 | return 32; |
10629 | 0 | } |
10630 | 0 | break; |
10631 | 0 | } |
10632 | 0 | case SystemZ::TP: { |
10633 | 0 | switch (OpNum) { |
10634 | 0 | case 0: |
10635 | | // op: B1 |
10636 | 0 | return 28; |
10637 | 0 | case 1: |
10638 | | // op: D1 |
10639 | 0 | return 16; |
10640 | 0 | case 2: |
10641 | | // op: L1 |
10642 | 0 | return 36; |
10643 | 0 | } |
10644 | 0 | break; |
10645 | 0 | } |
10646 | 0 | case SystemZ::AGSI: |
10647 | 0 | case SystemZ::ALGSI: |
10648 | 0 | case SystemZ::ALSI: |
10649 | 0 | case SystemZ::ASI: |
10650 | 0 | case SystemZ::CLIY: |
10651 | 0 | case SystemZ::MVIY: |
10652 | 0 | case SystemZ::NIY: |
10653 | 0 | case SystemZ::OIY: |
10654 | 0 | case SystemZ::TMY: |
10655 | 0 | case SystemZ::XIY: { |
10656 | 0 | switch (OpNum) { |
10657 | 0 | case 0: |
10658 | | // op: B1 |
10659 | 0 | return 28; |
10660 | 0 | case 1: |
10661 | | // op: D1 |
10662 | 0 | return 8; |
10663 | 0 | case 2: |
10664 | | // op: I2 |
10665 | 0 | return 32; |
10666 | 0 | } |
10667 | 0 | break; |
10668 | 0 | } |
10669 | 0 | case SystemZ::LPSWEY: { |
10670 | 0 | switch (OpNum) { |
10671 | 0 | case 0: |
10672 | | // op: B1 |
10673 | 0 | return 28; |
10674 | 0 | case 1: |
10675 | | // op: D1 |
10676 | 0 | return 8; |
10677 | 0 | } |
10678 | 0 | break; |
10679 | 0 | } |
10680 | 0 | case SystemZ::CFC: |
10681 | 0 | case SystemZ::LBEAR: |
10682 | 0 | case SystemZ::LCCTL: |
10683 | 0 | case SystemZ::LFAS: |
10684 | 0 | case SystemZ::LFPC: |
10685 | 0 | case SystemZ::LPCTL: |
10686 | 0 | case SystemZ::LPP: |
10687 | 0 | case SystemZ::LPSW: |
10688 | 0 | case SystemZ::LPSWE: |
10689 | 0 | case SystemZ::LSCTL: |
10690 | 0 | case SystemZ::MSCH: |
10691 | 0 | case SystemZ::PC: |
10692 | 0 | case SystemZ::QCTRI: |
10693 | 0 | case SystemZ::QPACI: |
10694 | 0 | case SystemZ::QSI: |
10695 | 0 | case SystemZ::RP: |
10696 | 0 | case SystemZ::SAC: |
10697 | 0 | case SystemZ::SACF: |
10698 | 0 | case SystemZ::SCK: |
10699 | 0 | case SystemZ::SCKC: |
10700 | 0 | case SystemZ::SIE: |
10701 | 0 | case SystemZ::SIGA: |
10702 | 0 | case SystemZ::SPKA: |
10703 | 0 | case SystemZ::SPT: |
10704 | 0 | case SystemZ::SPX: |
10705 | 0 | case SystemZ::SRNM: |
10706 | 0 | case SystemZ::SRNMB: |
10707 | 0 | case SystemZ::SRNMT: |
10708 | 0 | case SystemZ::SSCH: |
10709 | 0 | case SystemZ::SSM: |
10710 | 0 | case SystemZ::STAP: |
10711 | 0 | case SystemZ::STBEAR: |
10712 | 0 | case SystemZ::STCK: |
10713 | 0 | case SystemZ::STCKC: |
10714 | 0 | case SystemZ::STCKE: |
10715 | 0 | case SystemZ::STCKF: |
10716 | 0 | case SystemZ::STCPS: |
10717 | 0 | case SystemZ::STCRW: |
10718 | 0 | case SystemZ::STFL: |
10719 | 0 | case SystemZ::STFLE: |
10720 | 0 | case SystemZ::STFPC: |
10721 | 0 | case SystemZ::STIDP: |
10722 | 0 | case SystemZ::STPT: |
10723 | 0 | case SystemZ::STPX: |
10724 | 0 | case SystemZ::STSCH: |
10725 | 0 | case SystemZ::STSI: |
10726 | 0 | case SystemZ::TABORT: |
10727 | 0 | case SystemZ::TPI: |
10728 | 0 | case SystemZ::TRAP4: |
10729 | 0 | case SystemZ::TS: |
10730 | 0 | case SystemZ::TSCH: { |
10731 | 0 | switch (OpNum) { |
10732 | 0 | case 0: |
10733 | | // op: B2 |
10734 | 0 | return 12; |
10735 | 0 | case 1: |
10736 | | // op: D2 |
10737 | 0 | return 0; |
10738 | 0 | } |
10739 | 0 | break; |
10740 | 0 | } |
10741 | 0 | case SystemZ::SVC: { |
10742 | 0 | switch (OpNum) { |
10743 | 0 | case 0: |
10744 | | // op: I1 |
10745 | 0 | return 0; |
10746 | 0 | } |
10747 | 0 | break; |
10748 | 0 | } |
10749 | 0 | case SystemZ::NIAI: { |
10750 | 0 | switch (OpNum) { |
10751 | 0 | case 0: |
10752 | | // op: I1 |
10753 | 0 | return 4; |
10754 | 0 | case 1: |
10755 | | // op: I2 |
10756 | 0 | return 0; |
10757 | 0 | } |
10758 | 0 | break; |
10759 | 0 | } |
10760 | 0 | case SystemZ::BRCAsm: { |
10761 | 0 | switch (OpNum) { |
10762 | 0 | case 0: |
10763 | | // op: M1 |
10764 | 0 | return 20; |
10765 | 0 | case 1: |
10766 | | // op: RI2 |
10767 | 0 | return 0; |
10768 | 0 | } |
10769 | 0 | break; |
10770 | 0 | } |
10771 | 0 | case SystemZ::BCAsm: { |
10772 | 0 | switch (OpNum) { |
10773 | 0 | case 0: |
10774 | | // op: M1 |
10775 | 0 | return 20; |
10776 | 0 | case 3: |
10777 | | // op: X2 |
10778 | 0 | return 16; |
10779 | 0 | case 1: |
10780 | | // op: B2 |
10781 | 0 | return 12; |
10782 | 0 | case 2: |
10783 | | // op: D2 |
10784 | 0 | return 0; |
10785 | 0 | } |
10786 | 0 | break; |
10787 | 0 | } |
10788 | 0 | case SystemZ::BPP: { |
10789 | 0 | switch (OpNum) { |
10790 | 0 | case 0: |
10791 | | // op: M1 |
10792 | 0 | return 36; |
10793 | 0 | case 1: |
10794 | | // op: RI2 |
10795 | 0 | return 0; |
10796 | 0 | case 2: |
10797 | | // op: B3 |
10798 | 0 | return 28; |
10799 | 0 | case 3: |
10800 | | // op: D3 |
10801 | 0 | return 16; |
10802 | 0 | } |
10803 | 0 | break; |
10804 | 0 | } |
10805 | 0 | case SystemZ::BRCLAsm: |
10806 | 0 | case SystemZ::PFDRL: { |
10807 | 0 | switch (OpNum) { |
10808 | 0 | case 0: |
10809 | | // op: M1 |
10810 | 0 | return 36; |
10811 | 0 | case 1: |
10812 | | // op: RI2 |
10813 | 0 | return 0; |
10814 | 0 | } |
10815 | 0 | break; |
10816 | 0 | } |
10817 | 0 | case SystemZ::BPRP: { |
10818 | 0 | switch (OpNum) { |
10819 | 0 | case 0: |
10820 | | // op: M1 |
10821 | 0 | return 36; |
10822 | 0 | case 1: |
10823 | | // op: RI2 |
10824 | 0 | return 24; |
10825 | 0 | case 2: |
10826 | | // op: RI3 |
10827 | 0 | return 0; |
10828 | 0 | } |
10829 | 0 | break; |
10830 | 0 | } |
10831 | 0 | case SystemZ::BICAsm: |
10832 | 0 | case SystemZ::PFD: { |
10833 | 0 | switch (OpNum) { |
10834 | 0 | case 0: |
10835 | | // op: M1 |
10836 | 0 | return 36; |
10837 | 0 | case 3: |
10838 | | // op: X2 |
10839 | 0 | return 32; |
10840 | 0 | case 1: |
10841 | | // op: B2 |
10842 | 0 | return 28; |
10843 | 0 | case 2: |
10844 | | // op: D2 |
10845 | 0 | return 8; |
10846 | 0 | } |
10847 | 0 | break; |
10848 | 0 | } |
10849 | 0 | case SystemZ::CDPT: |
10850 | 0 | case SystemZ::CDZT: |
10851 | 0 | case SystemZ::CPDT: |
10852 | 0 | case SystemZ::CPXT: |
10853 | 0 | case SystemZ::CXPT: |
10854 | 0 | case SystemZ::CXZT: |
10855 | 0 | case SystemZ::CZDT: |
10856 | 0 | case SystemZ::CZXT: { |
10857 | 0 | switch (OpNum) { |
10858 | 0 | case 0: |
10859 | | // op: R1 |
10860 | 0 | return 12; |
10861 | 0 | case 1: |
10862 | | // op: B2 |
10863 | 0 | return 28; |
10864 | 0 | case 2: |
10865 | | // op: D2 |
10866 | 0 | return 16; |
10867 | 0 | case 3: |
10868 | | // op: L2 |
10869 | 0 | return 32; |
10870 | 0 | case 4: |
10871 | | // op: M3 |
10872 | 0 | return 8; |
10873 | 0 | } |
10874 | 0 | break; |
10875 | 0 | } |
10876 | 0 | case SystemZ::MY: |
10877 | 0 | case SystemZ::MYH: |
10878 | 0 | case SystemZ::MYL: |
10879 | 0 | case SystemZ::SLDT: |
10880 | 0 | case SystemZ::SLXT: |
10881 | 0 | case SystemZ::SRDT: |
10882 | 0 | case SystemZ::SRXT: { |
10883 | 0 | switch (OpNum) { |
10884 | 0 | case 0: |
10885 | | // op: R1 |
10886 | 0 | return 12; |
10887 | 0 | case 1: |
10888 | | // op: R3 |
10889 | 0 | return 36; |
10890 | 0 | case 4: |
10891 | | // op: X2 |
10892 | 0 | return 32; |
10893 | 0 | case 2: |
10894 | | // op: B2 |
10895 | 0 | return 28; |
10896 | 0 | case 3: |
10897 | | // op: D2 |
10898 | 0 | return 16; |
10899 | 0 | } |
10900 | 0 | break; |
10901 | 0 | } |
10902 | 0 | case SystemZ::MYHR: |
10903 | 0 | case SystemZ::MYLR: |
10904 | 0 | case SystemZ::MYR: { |
10905 | 0 | switch (OpNum) { |
10906 | 0 | case 0: |
10907 | | // op: R1 |
10908 | 0 | return 12; |
10909 | 0 | case 1: |
10910 | | // op: R3 |
10911 | 0 | return 4; |
10912 | 0 | case 2: |
10913 | | // op: R2 |
10914 | 0 | return 0; |
10915 | 0 | } |
10916 | 0 | break; |
10917 | 0 | } |
10918 | 0 | case SystemZ::MAD: |
10919 | 0 | case SystemZ::MADB: |
10920 | 0 | case SystemZ::MAE: |
10921 | 0 | case SystemZ::MAEB: |
10922 | 0 | case SystemZ::MAY: |
10923 | 0 | case SystemZ::MAYH: |
10924 | 0 | case SystemZ::MAYL: |
10925 | 0 | case SystemZ::MSD: |
10926 | 0 | case SystemZ::MSDB: |
10927 | 0 | case SystemZ::MSE: |
10928 | 0 | case SystemZ::MSEB: { |
10929 | 0 | switch (OpNum) { |
10930 | 0 | case 0: |
10931 | | // op: R1 |
10932 | 0 | return 12; |
10933 | 0 | case 2: |
10934 | | // op: R3 |
10935 | 0 | return 36; |
10936 | 0 | case 5: |
10937 | | // op: X2 |
10938 | 0 | return 32; |
10939 | 0 | case 3: |
10940 | | // op: B2 |
10941 | 0 | return 28; |
10942 | 0 | case 4: |
10943 | | // op: D2 |
10944 | 0 | return 16; |
10945 | 0 | } |
10946 | 0 | break; |
10947 | 0 | } |
10948 | 0 | case SystemZ::MADBR: |
10949 | 0 | case SystemZ::MADR: |
10950 | 0 | case SystemZ::MAEBR: |
10951 | 0 | case SystemZ::MAER: |
10952 | 0 | case SystemZ::MAYHR: |
10953 | 0 | case SystemZ::MAYLR: |
10954 | 0 | case SystemZ::MAYR: |
10955 | 0 | case SystemZ::MSDBR: |
10956 | 0 | case SystemZ::MSDR: |
10957 | 0 | case SystemZ::MSEBR: |
10958 | 0 | case SystemZ::MSER: { |
10959 | 0 | switch (OpNum) { |
10960 | 0 | case 0: |
10961 | | // op: R1 |
10962 | 0 | return 12; |
10963 | 0 | case 2: |
10964 | | // op: R3 |
10965 | 0 | return 4; |
10966 | 0 | case 3: |
10967 | | // op: R2 |
10968 | 0 | return 0; |
10969 | 0 | } |
10970 | 0 | break; |
10971 | 0 | } |
10972 | 0 | case SystemZ::CGHI: |
10973 | 0 | case SystemZ::CHI: |
10974 | 0 | case SystemZ::LGHI: |
10975 | 0 | case SystemZ::LHI: |
10976 | 0 | case SystemZ::LLIHH: |
10977 | 0 | case SystemZ::LLIHL: |
10978 | 0 | case SystemZ::LLILH: |
10979 | 0 | case SystemZ::LLILL: |
10980 | 0 | case SystemZ::TMHH: |
10981 | 0 | case SystemZ::TMHL: |
10982 | 0 | case SystemZ::TMLH: |
10983 | 0 | case SystemZ::TMLL: { |
10984 | 0 | switch (OpNum) { |
10985 | 0 | case 0: |
10986 | | // op: R1 |
10987 | 0 | return 20; |
10988 | 0 | case 1: |
10989 | | // op: I2 |
10990 | 0 | return 0; |
10991 | 0 | } |
10992 | 0 | break; |
10993 | 0 | } |
10994 | 0 | case SystemZ::CLM: |
10995 | 0 | case SystemZ::STCM: { |
10996 | 0 | switch (OpNum) { |
10997 | 0 | case 0: |
10998 | | // op: R1 |
10999 | 0 | return 20; |
11000 | 0 | case 1: |
11001 | | // op: M3 |
11002 | 0 | return 16; |
11003 | 0 | case 2: |
11004 | | // op: B2 |
11005 | 0 | return 12; |
11006 | 0 | case 3: |
11007 | | // op: D2 |
11008 | 0 | return 0; |
11009 | 0 | } |
11010 | 0 | break; |
11011 | 0 | } |
11012 | 0 | case SystemZ::DIAG: |
11013 | 0 | case SystemZ::LAM: |
11014 | 0 | case SystemZ::LCTL: |
11015 | 0 | case SystemZ::LM: |
11016 | 0 | case SystemZ::SIGP: |
11017 | 0 | case SystemZ::STAM: |
11018 | 0 | case SystemZ::STCTL: |
11019 | 0 | case SystemZ::STM: |
11020 | 0 | case SystemZ::TRACE: { |
11021 | 0 | switch (OpNum) { |
11022 | 0 | case 0: |
11023 | | // op: R1 |
11024 | 0 | return 20; |
11025 | 0 | case 1: |
11026 | | // op: R3 |
11027 | 0 | return 16; |
11028 | 0 | case 2: |
11029 | | // op: B2 |
11030 | 0 | return 12; |
11031 | 0 | case 3: |
11032 | | // op: D2 |
11033 | 0 | return 0; |
11034 | 0 | } |
11035 | 0 | break; |
11036 | 0 | } |
11037 | 0 | case SystemZ::CLCLE: |
11038 | 0 | case SystemZ::MVCLE: { |
11039 | 0 | switch (OpNum) { |
11040 | 0 | case 0: |
11041 | | // op: R1 |
11042 | 0 | return 20; |
11043 | 0 | case 1: |
11044 | | // op: R3 |
11045 | 0 | return 16; |
11046 | 0 | case 4: |
11047 | | // op: B2 |
11048 | 0 | return 12; |
11049 | 0 | case 5: |
11050 | | // op: D2 |
11051 | 0 | return 0; |
11052 | 0 | } |
11053 | 0 | break; |
11054 | 0 | } |
11055 | 0 | case SystemZ::BRAS: { |
11056 | 0 | switch (OpNum) { |
11057 | 0 | case 0: |
11058 | | // op: R1 |
11059 | 0 | return 20; |
11060 | 0 | case 1: |
11061 | | // op: RI2 |
11062 | 0 | return 0; |
11063 | 0 | } |
11064 | 0 | break; |
11065 | 0 | } |
11066 | 0 | case SystemZ::SLA: |
11067 | 0 | case SystemZ::SLDA: |
11068 | 0 | case SystemZ::SLDL: |
11069 | 0 | case SystemZ::SLL: |
11070 | 0 | case SystemZ::SRA: |
11071 | 0 | case SystemZ::SRDA: |
11072 | 0 | case SystemZ::SRDL: |
11073 | 0 | case SystemZ::SRL: { |
11074 | 0 | switch (OpNum) { |
11075 | 0 | case 0: |
11076 | | // op: R1 |
11077 | 0 | return 20; |
11078 | 0 | case 2: |
11079 | | // op: B2 |
11080 | 0 | return 12; |
11081 | 0 | case 3: |
11082 | | // op: D2 |
11083 | 0 | return 0; |
11084 | 0 | } |
11085 | 0 | break; |
11086 | 0 | } |
11087 | 0 | case SystemZ::AGHI: |
11088 | 0 | case SystemZ::AHI: |
11089 | 0 | case SystemZ::IIHH: |
11090 | 0 | case SystemZ::IIHL: |
11091 | 0 | case SystemZ::IILH: |
11092 | 0 | case SystemZ::IILL: |
11093 | 0 | case SystemZ::MGHI: |
11094 | 0 | case SystemZ::MHI: |
11095 | 0 | case SystemZ::NIHH: |
11096 | 0 | case SystemZ::NIHL: |
11097 | 0 | case SystemZ::NILH: |
11098 | 0 | case SystemZ::NILL: |
11099 | 0 | case SystemZ::OIHH: |
11100 | 0 | case SystemZ::OIHL: |
11101 | 0 | case SystemZ::OILH: |
11102 | 0 | case SystemZ::OILL: { |
11103 | 0 | switch (OpNum) { |
11104 | 0 | case 0: |
11105 | | // op: R1 |
11106 | 0 | return 20; |
11107 | 0 | case 2: |
11108 | | // op: I2 |
11109 | 0 | return 0; |
11110 | 0 | } |
11111 | 0 | break; |
11112 | 0 | } |
11113 | 0 | case SystemZ::ICM: { |
11114 | 0 | switch (OpNum) { |
11115 | 0 | case 0: |
11116 | | // op: R1 |
11117 | 0 | return 20; |
11118 | 0 | case 2: |
11119 | | // op: M3 |
11120 | 0 | return 16; |
11121 | 0 | case 3: |
11122 | | // op: B2 |
11123 | 0 | return 12; |
11124 | 0 | case 4: |
11125 | | // op: D2 |
11126 | 0 | return 0; |
11127 | 0 | } |
11128 | 0 | break; |
11129 | 0 | } |
11130 | 0 | case SystemZ::BXH: |
11131 | 0 | case SystemZ::BXLE: |
11132 | 0 | case SystemZ::CDS: |
11133 | 0 | case SystemZ::CS: { |
11134 | 0 | switch (OpNum) { |
11135 | 0 | case 0: |
11136 | | // op: R1 |
11137 | 0 | return 20; |
11138 | 0 | case 2: |
11139 | | // op: R3 |
11140 | 0 | return 16; |
11141 | 0 | case 3: |
11142 | | // op: B2 |
11143 | 0 | return 12; |
11144 | 0 | case 4: |
11145 | | // op: D2 |
11146 | 0 | return 0; |
11147 | 0 | } |
11148 | 0 | break; |
11149 | 0 | } |
11150 | 0 | case SystemZ::BRXH: |
11151 | 0 | case SystemZ::BRXLE: { |
11152 | 0 | switch (OpNum) { |
11153 | 0 | case 0: |
11154 | | // op: R1 |
11155 | 0 | return 20; |
11156 | 0 | case 2: |
11157 | | // op: R3 |
11158 | 0 | return 16; |
11159 | 0 | case 3: |
11160 | | // op: RI2 |
11161 | 0 | return 0; |
11162 | 0 | } |
11163 | 0 | break; |
11164 | 0 | } |
11165 | 0 | case SystemZ::BRCT: |
11166 | 0 | case SystemZ::BRCTG: { |
11167 | 0 | switch (OpNum) { |
11168 | 0 | case 0: |
11169 | | // op: R1 |
11170 | 0 | return 20; |
11171 | 0 | case 2: |
11172 | | // op: RI2 |
11173 | 0 | return 0; |
11174 | 0 | } |
11175 | 0 | break; |
11176 | 0 | } |
11177 | 0 | case SystemZ::BAL: |
11178 | 0 | case SystemZ::BAS: |
11179 | 0 | case SystemZ::C: |
11180 | 0 | case SystemZ::CD: |
11181 | 0 | case SystemZ::CE: |
11182 | 0 | case SystemZ::CH: |
11183 | 0 | case SystemZ::CL: |
11184 | 0 | case SystemZ::CVD: |
11185 | 0 | case SystemZ::EX: |
11186 | 0 | case SystemZ::L: |
11187 | 0 | case SystemZ::LA: |
11188 | 0 | case SystemZ::LAE: |
11189 | 0 | case SystemZ::LD: |
11190 | 0 | case SystemZ::LE: |
11191 | 0 | case SystemZ::LH: |
11192 | 0 | case SystemZ::LRA: |
11193 | 0 | case SystemZ::ST: |
11194 | 0 | case SystemZ::STC: |
11195 | 0 | case SystemZ::STD: |
11196 | 0 | case SystemZ::STE: |
11197 | 0 | case SystemZ::STH: { |
11198 | 0 | switch (OpNum) { |
11199 | 0 | case 0: |
11200 | | // op: R1 |
11201 | 0 | return 20; |
11202 | 0 | case 3: |
11203 | | // op: X2 |
11204 | 0 | return 16; |
11205 | 0 | case 1: |
11206 | | // op: B2 |
11207 | 0 | return 12; |
11208 | 0 | case 2: |
11209 | | // op: D2 |
11210 | 0 | return 0; |
11211 | 0 | } |
11212 | 0 | break; |
11213 | 0 | } |
11214 | 0 | case SystemZ::A: |
11215 | 0 | case SystemZ::AD: |
11216 | 0 | case SystemZ::AE: |
11217 | 0 | case SystemZ::AH: |
11218 | 0 | case SystemZ::AL: |
11219 | 0 | case SystemZ::AU: |
11220 | 0 | case SystemZ::AW: |
11221 | 0 | case SystemZ::BCT: |
11222 | 0 | case SystemZ::CVB: |
11223 | 0 | case SystemZ::D: |
11224 | 0 | case SystemZ::DD: |
11225 | 0 | case SystemZ::DE: |
11226 | 0 | case SystemZ::IC: |
11227 | 0 | case SystemZ::IC32: |
11228 | 0 | case SystemZ::M: |
11229 | 0 | case SystemZ::MD: |
11230 | 0 | case SystemZ::MDE: |
11231 | 0 | case SystemZ::ME: |
11232 | 0 | case SystemZ::MH: |
11233 | 0 | case SystemZ::MS: |
11234 | 0 | case SystemZ::MXD: |
11235 | 0 | case SystemZ::N: |
11236 | 0 | case SystemZ::O: |
11237 | 0 | case SystemZ::S: |
11238 | 0 | case SystemZ::SD: |
11239 | 0 | case SystemZ::SE: |
11240 | 0 | case SystemZ::SH: |
11241 | 0 | case SystemZ::SL: |
11242 | 0 | case SystemZ::SU: |
11243 | 0 | case SystemZ::SW: |
11244 | 0 | case SystemZ::X: { |
11245 | 0 | switch (OpNum) { |
11246 | 0 | case 0: |
11247 | | // op: R1 |
11248 | 0 | return 20; |
11249 | 0 | case 4: |
11250 | | // op: X2 |
11251 | 0 | return 16; |
11252 | 0 | case 2: |
11253 | | // op: B2 |
11254 | 0 | return 12; |
11255 | 0 | case 3: |
11256 | | // op: D2 |
11257 | 0 | return 0; |
11258 | 0 | } |
11259 | 0 | break; |
11260 | 0 | } |
11261 | 0 | case SystemZ::PLO: { |
11262 | 0 | switch (OpNum) { |
11263 | 0 | case 0: |
11264 | | // op: R1 |
11265 | 0 | return 36; |
11266 | 0 | case 1: |
11267 | | // op: B2 |
11268 | 0 | return 28; |
11269 | 0 | case 2: |
11270 | | // op: D2 |
11271 | 0 | return 16; |
11272 | 0 | case 3: |
11273 | | // op: R3 |
11274 | 0 | return 32; |
11275 | 0 | case 4: |
11276 | | // op: B4 |
11277 | 0 | return 12; |
11278 | 0 | case 5: |
11279 | | // op: D4 |
11280 | 0 | return 0; |
11281 | 0 | } |
11282 | 0 | break; |
11283 | 0 | } |
11284 | 0 | case SystemZ::CLGTAsmE: |
11285 | 0 | case SystemZ::CLGTAsmH: |
11286 | 0 | case SystemZ::CLGTAsmHE: |
11287 | 0 | case SystemZ::CLGTAsmL: |
11288 | 0 | case SystemZ::CLGTAsmLE: |
11289 | 0 | case SystemZ::CLGTAsmLH: |
11290 | 0 | case SystemZ::CLGTAsmNE: |
11291 | 0 | case SystemZ::CLGTAsmNH: |
11292 | 0 | case SystemZ::CLGTAsmNHE: |
11293 | 0 | case SystemZ::CLGTAsmNL: |
11294 | 0 | case SystemZ::CLGTAsmNLE: |
11295 | 0 | case SystemZ::CLGTAsmNLH: |
11296 | 0 | case SystemZ::CLTAsmE: |
11297 | 0 | case SystemZ::CLTAsmH: |
11298 | 0 | case SystemZ::CLTAsmHE: |
11299 | 0 | case SystemZ::CLTAsmL: |
11300 | 0 | case SystemZ::CLTAsmLE: |
11301 | 0 | case SystemZ::CLTAsmLH: |
11302 | 0 | case SystemZ::CLTAsmNE: |
11303 | 0 | case SystemZ::CLTAsmNH: |
11304 | 0 | case SystemZ::CLTAsmNHE: |
11305 | 0 | case SystemZ::CLTAsmNL: |
11306 | 0 | case SystemZ::CLTAsmNLE: |
11307 | 0 | case SystemZ::CLTAsmNLH: |
11308 | 0 | case SystemZ::STOCAsmE: |
11309 | 0 | case SystemZ::STOCAsmH: |
11310 | 0 | case SystemZ::STOCAsmHE: |
11311 | 0 | case SystemZ::STOCAsmL: |
11312 | 0 | case SystemZ::STOCAsmLE: |
11313 | 0 | case SystemZ::STOCAsmLH: |
11314 | 0 | case SystemZ::STOCAsmM: |
11315 | 0 | case SystemZ::STOCAsmNE: |
11316 | 0 | case SystemZ::STOCAsmNH: |
11317 | 0 | case SystemZ::STOCAsmNHE: |
11318 | 0 | case SystemZ::STOCAsmNL: |
11319 | 0 | case SystemZ::STOCAsmNLE: |
11320 | 0 | case SystemZ::STOCAsmNLH: |
11321 | 0 | case SystemZ::STOCAsmNM: |
11322 | 0 | case SystemZ::STOCAsmNO: |
11323 | 0 | case SystemZ::STOCAsmNP: |
11324 | 0 | case SystemZ::STOCAsmNZ: |
11325 | 0 | case SystemZ::STOCAsmO: |
11326 | 0 | case SystemZ::STOCAsmP: |
11327 | 0 | case SystemZ::STOCAsmZ: |
11328 | 0 | case SystemZ::STOCFHAsmE: |
11329 | 0 | case SystemZ::STOCFHAsmH: |
11330 | 0 | case SystemZ::STOCFHAsmHE: |
11331 | 0 | case SystemZ::STOCFHAsmL: |
11332 | 0 | case SystemZ::STOCFHAsmLE: |
11333 | 0 | case SystemZ::STOCFHAsmLH: |
11334 | 0 | case SystemZ::STOCFHAsmM: |
11335 | 0 | case SystemZ::STOCFHAsmNE: |
11336 | 0 | case SystemZ::STOCFHAsmNH: |
11337 | 0 | case SystemZ::STOCFHAsmNHE: |
11338 | 0 | case SystemZ::STOCFHAsmNL: |
11339 | 0 | case SystemZ::STOCFHAsmNLE: |
11340 | 0 | case SystemZ::STOCFHAsmNLH: |
11341 | 0 | case SystemZ::STOCFHAsmNM: |
11342 | 0 | case SystemZ::STOCFHAsmNO: |
11343 | 0 | case SystemZ::STOCFHAsmNP: |
11344 | 0 | case SystemZ::STOCFHAsmNZ: |
11345 | 0 | case SystemZ::STOCFHAsmO: |
11346 | 0 | case SystemZ::STOCFHAsmP: |
11347 | 0 | case SystemZ::STOCFHAsmZ: |
11348 | 0 | case SystemZ::STOCGAsmE: |
11349 | 0 | case SystemZ::STOCGAsmH: |
11350 | 0 | case SystemZ::STOCGAsmHE: |
11351 | 0 | case SystemZ::STOCGAsmL: |
11352 | 0 | case SystemZ::STOCGAsmLE: |
11353 | 0 | case SystemZ::STOCGAsmLH: |
11354 | 0 | case SystemZ::STOCGAsmM: |
11355 | 0 | case SystemZ::STOCGAsmNE: |
11356 | 0 | case SystemZ::STOCGAsmNH: |
11357 | 0 | case SystemZ::STOCGAsmNHE: |
11358 | 0 | case SystemZ::STOCGAsmNL: |
11359 | 0 | case SystemZ::STOCGAsmNLE: |
11360 | 0 | case SystemZ::STOCGAsmNLH: |
11361 | 0 | case SystemZ::STOCGAsmNM: |
11362 | 0 | case SystemZ::STOCGAsmNO: |
11363 | 0 | case SystemZ::STOCGAsmNP: |
11364 | 0 | case SystemZ::STOCGAsmNZ: |
11365 | 0 | case SystemZ::STOCGAsmO: |
11366 | 0 | case SystemZ::STOCGAsmP: |
11367 | 0 | case SystemZ::STOCGAsmZ: { |
11368 | 0 | switch (OpNum) { |
11369 | 0 | case 0: |
11370 | | // op: R1 |
11371 | 0 | return 36; |
11372 | 0 | case 1: |
11373 | | // op: B2 |
11374 | 0 | return 28; |
11375 | 0 | case 2: |
11376 | | // op: D2 |
11377 | 0 | return 8; |
11378 | 0 | } |
11379 | 0 | break; |
11380 | 0 | } |
11381 | 0 | case SystemZ::CFI: |
11382 | 0 | case SystemZ::CGFI: |
11383 | 0 | case SystemZ::CIH: |
11384 | 0 | case SystemZ::CLFI: |
11385 | 0 | case SystemZ::CLGFI: |
11386 | 0 | case SystemZ::CLIH: |
11387 | 0 | case SystemZ::IIHF: |
11388 | 0 | case SystemZ::IILF: |
11389 | 0 | case SystemZ::LGFI: |
11390 | 0 | case SystemZ::LLIHF: |
11391 | 0 | case SystemZ::LLILF: { |
11392 | 0 | switch (OpNum) { |
11393 | 0 | case 0: |
11394 | | // op: R1 |
11395 | 0 | return 36; |
11396 | 0 | case 1: |
11397 | | // op: I2 |
11398 | 0 | return 0; |
11399 | 0 | } |
11400 | 0 | break; |
11401 | 0 | } |
11402 | 0 | case SystemZ::CGIT: |
11403 | 0 | case SystemZ::CGITAsm: |
11404 | 0 | case SystemZ::CIT: |
11405 | 0 | case SystemZ::CITAsm: |
11406 | 0 | case SystemZ::CLFIT: |
11407 | 0 | case SystemZ::CLFITAsm: |
11408 | 0 | case SystemZ::CLGIT: |
11409 | 0 | case SystemZ::CLGITAsm: { |
11410 | 0 | switch (OpNum) { |
11411 | 0 | case 0: |
11412 | | // op: R1 |
11413 | 0 | return 36; |
11414 | 0 | case 1: |
11415 | | // op: I2 |
11416 | 0 | return 16; |
11417 | 0 | case 2: |
11418 | | // op: M3 |
11419 | 0 | return 12; |
11420 | 0 | } |
11421 | 0 | break; |
11422 | 0 | } |
11423 | 0 | case SystemZ::CGITAsmE: |
11424 | 0 | case SystemZ::CGITAsmH: |
11425 | 0 | case SystemZ::CGITAsmHE: |
11426 | 0 | case SystemZ::CGITAsmL: |
11427 | 0 | case SystemZ::CGITAsmLE: |
11428 | 0 | case SystemZ::CGITAsmLH: |
11429 | 0 | case SystemZ::CGITAsmNE: |
11430 | 0 | case SystemZ::CGITAsmNH: |
11431 | 0 | case SystemZ::CGITAsmNHE: |
11432 | 0 | case SystemZ::CGITAsmNL: |
11433 | 0 | case SystemZ::CGITAsmNLE: |
11434 | 0 | case SystemZ::CGITAsmNLH: |
11435 | 0 | case SystemZ::CITAsmE: |
11436 | 0 | case SystemZ::CITAsmH: |
11437 | 0 | case SystemZ::CITAsmHE: |
11438 | 0 | case SystemZ::CITAsmL: |
11439 | 0 | case SystemZ::CITAsmLE: |
11440 | 0 | case SystemZ::CITAsmLH: |
11441 | 0 | case SystemZ::CITAsmNE: |
11442 | 0 | case SystemZ::CITAsmNH: |
11443 | 0 | case SystemZ::CITAsmNHE: |
11444 | 0 | case SystemZ::CITAsmNL: |
11445 | 0 | case SystemZ::CITAsmNLE: |
11446 | 0 | case SystemZ::CITAsmNLH: |
11447 | 0 | case SystemZ::CLFITAsmE: |
11448 | 0 | case SystemZ::CLFITAsmH: |
11449 | 0 | case SystemZ::CLFITAsmHE: |
11450 | 0 | case SystemZ::CLFITAsmL: |
11451 | 0 | case SystemZ::CLFITAsmLE: |
11452 | 0 | case SystemZ::CLFITAsmLH: |
11453 | 0 | case SystemZ::CLFITAsmNE: |
11454 | 0 | case SystemZ::CLFITAsmNH: |
11455 | 0 | case SystemZ::CLFITAsmNHE: |
11456 | 0 | case SystemZ::CLFITAsmNL: |
11457 | 0 | case SystemZ::CLFITAsmNLE: |
11458 | 0 | case SystemZ::CLFITAsmNLH: |
11459 | 0 | case SystemZ::CLGITAsmE: |
11460 | 0 | case SystemZ::CLGITAsmH: |
11461 | 0 | case SystemZ::CLGITAsmHE: |
11462 | 0 | case SystemZ::CLGITAsmL: |
11463 | 0 | case SystemZ::CLGITAsmLE: |
11464 | 0 | case SystemZ::CLGITAsmLH: |
11465 | 0 | case SystemZ::CLGITAsmNE: |
11466 | 0 | case SystemZ::CLGITAsmNH: |
11467 | 0 | case SystemZ::CLGITAsmNHE: |
11468 | 0 | case SystemZ::CLGITAsmNL: |
11469 | 0 | case SystemZ::CLGITAsmNLE: |
11470 | 0 | case SystemZ::CLGITAsmNLH: { |
11471 | 0 | switch (OpNum) { |
11472 | 0 | case 0: |
11473 | | // op: R1 |
11474 | 0 | return 36; |
11475 | 0 | case 1: |
11476 | | // op: I2 |
11477 | 0 | return 16; |
11478 | 0 | } |
11479 | 0 | break; |
11480 | 0 | } |
11481 | 0 | case SystemZ::CGIBAsmE: |
11482 | 0 | case SystemZ::CGIBAsmH: |
11483 | 0 | case SystemZ::CGIBAsmHE: |
11484 | 0 | case SystemZ::CGIBAsmL: |
11485 | 0 | case SystemZ::CGIBAsmLE: |
11486 | 0 | case SystemZ::CGIBAsmLH: |
11487 | 0 | case SystemZ::CGIBAsmNE: |
11488 | 0 | case SystemZ::CGIBAsmNH: |
11489 | 0 | case SystemZ::CGIBAsmNHE: |
11490 | 0 | case SystemZ::CGIBAsmNL: |
11491 | 0 | case SystemZ::CGIBAsmNLE: |
11492 | 0 | case SystemZ::CGIBAsmNLH: |
11493 | 0 | case SystemZ::CIBAsmE: |
11494 | 0 | case SystemZ::CIBAsmH: |
11495 | 0 | case SystemZ::CIBAsmHE: |
11496 | 0 | case SystemZ::CIBAsmL: |
11497 | 0 | case SystemZ::CIBAsmLE: |
11498 | 0 | case SystemZ::CIBAsmLH: |
11499 | 0 | case SystemZ::CIBAsmNE: |
11500 | 0 | case SystemZ::CIBAsmNH: |
11501 | 0 | case SystemZ::CIBAsmNHE: |
11502 | 0 | case SystemZ::CIBAsmNL: |
11503 | 0 | case SystemZ::CIBAsmNLE: |
11504 | 0 | case SystemZ::CIBAsmNLH: |
11505 | 0 | case SystemZ::CLGIBAsmE: |
11506 | 0 | case SystemZ::CLGIBAsmH: |
11507 | 0 | case SystemZ::CLGIBAsmHE: |
11508 | 0 | case SystemZ::CLGIBAsmL: |
11509 | 0 | case SystemZ::CLGIBAsmLE: |
11510 | 0 | case SystemZ::CLGIBAsmLH: |
11511 | 0 | case SystemZ::CLGIBAsmNE: |
11512 | 0 | case SystemZ::CLGIBAsmNH: |
11513 | 0 | case SystemZ::CLGIBAsmNHE: |
11514 | 0 | case SystemZ::CLGIBAsmNL: |
11515 | 0 | case SystemZ::CLGIBAsmNLE: |
11516 | 0 | case SystemZ::CLGIBAsmNLH: |
11517 | 0 | case SystemZ::CLIBAsmE: |
11518 | 0 | case SystemZ::CLIBAsmH: |
11519 | 0 | case SystemZ::CLIBAsmHE: |
11520 | 0 | case SystemZ::CLIBAsmL: |
11521 | 0 | case SystemZ::CLIBAsmLE: |
11522 | 0 | case SystemZ::CLIBAsmLH: |
11523 | 0 | case SystemZ::CLIBAsmNE: |
11524 | 0 | case SystemZ::CLIBAsmNH: |
11525 | 0 | case SystemZ::CLIBAsmNHE: |
11526 | 0 | case SystemZ::CLIBAsmNL: |
11527 | 0 | case SystemZ::CLIBAsmNLE: |
11528 | 0 | case SystemZ::CLIBAsmNLH: { |
11529 | 0 | switch (OpNum) { |
11530 | 0 | case 0: |
11531 | | // op: R1 |
11532 | 0 | return 36; |
11533 | 0 | case 1: |
11534 | | // op: I2 |
11535 | 0 | return 8; |
11536 | 0 | case 2: |
11537 | | // op: B4 |
11538 | 0 | return 28; |
11539 | 0 | case 3: |
11540 | | // op: D4 |
11541 | 0 | return 16; |
11542 | 0 | } |
11543 | 0 | break; |
11544 | 0 | } |
11545 | 0 | case SystemZ::CGIB: |
11546 | 0 | case SystemZ::CGIBAsm: |
11547 | 0 | case SystemZ::CIB: |
11548 | 0 | case SystemZ::CIBAsm: |
11549 | 0 | case SystemZ::CLGIB: |
11550 | 0 | case SystemZ::CLGIBAsm: |
11551 | 0 | case SystemZ::CLIB: |
11552 | 0 | case SystemZ::CLIBAsm: { |
11553 | 0 | switch (OpNum) { |
11554 | 0 | case 0: |
11555 | | // op: R1 |
11556 | 0 | return 36; |
11557 | 0 | case 1: |
11558 | | // op: I2 |
11559 | 0 | return 8; |
11560 | 0 | case 2: |
11561 | | // op: M3 |
11562 | 0 | return 32; |
11563 | 0 | case 3: |
11564 | | // op: B4 |
11565 | 0 | return 28; |
11566 | 0 | case 4: |
11567 | | // op: D4 |
11568 | 0 | return 16; |
11569 | 0 | } |
11570 | 0 | break; |
11571 | 0 | } |
11572 | 0 | case SystemZ::CGIJ: |
11573 | 0 | case SystemZ::CGIJAsm: |
11574 | 0 | case SystemZ::CIJ: |
11575 | 0 | case SystemZ::CIJAsm: |
11576 | 0 | case SystemZ::CLGIJ: |
11577 | 0 | case SystemZ::CLGIJAsm: |
11578 | 0 | case SystemZ::CLIJ: |
11579 | 0 | case SystemZ::CLIJAsm: { |
11580 | 0 | switch (OpNum) { |
11581 | 0 | case 0: |
11582 | | // op: R1 |
11583 | 0 | return 36; |
11584 | 0 | case 1: |
11585 | | // op: I2 |
11586 | 0 | return 8; |
11587 | 0 | case 2: |
11588 | | // op: M3 |
11589 | 0 | return 32; |
11590 | 0 | case 3: |
11591 | | // op: RI4 |
11592 | 0 | return 16; |
11593 | 0 | } |
11594 | 0 | break; |
11595 | 0 | } |
11596 | 0 | case SystemZ::CGIJAsmE: |
11597 | 0 | case SystemZ::CGIJAsmH: |
11598 | 0 | case SystemZ::CGIJAsmHE: |
11599 | 0 | case SystemZ::CGIJAsmL: |
11600 | 0 | case SystemZ::CGIJAsmLE: |
11601 | 0 | case SystemZ::CGIJAsmLH: |
11602 | 0 | case SystemZ::CGIJAsmNE: |
11603 | 0 | case SystemZ::CGIJAsmNH: |
11604 | 0 | case SystemZ::CGIJAsmNHE: |
11605 | 0 | case SystemZ::CGIJAsmNL: |
11606 | 0 | case SystemZ::CGIJAsmNLE: |
11607 | 0 | case SystemZ::CGIJAsmNLH: |
11608 | 0 | case SystemZ::CIJAsmE: |
11609 | 0 | case SystemZ::CIJAsmH: |
11610 | 0 | case SystemZ::CIJAsmHE: |
11611 | 0 | case SystemZ::CIJAsmL: |
11612 | 0 | case SystemZ::CIJAsmLE: |
11613 | 0 | case SystemZ::CIJAsmLH: |
11614 | 0 | case SystemZ::CIJAsmNE: |
11615 | 0 | case SystemZ::CIJAsmNH: |
11616 | 0 | case SystemZ::CIJAsmNHE: |
11617 | 0 | case SystemZ::CIJAsmNL: |
11618 | 0 | case SystemZ::CIJAsmNLE: |
11619 | 0 | case SystemZ::CIJAsmNLH: |
11620 | 0 | case SystemZ::CLGIJAsmE: |
11621 | 0 | case SystemZ::CLGIJAsmH: |
11622 | 0 | case SystemZ::CLGIJAsmHE: |
11623 | 0 | case SystemZ::CLGIJAsmL: |
11624 | 0 | case SystemZ::CLGIJAsmLE: |
11625 | 0 | case SystemZ::CLGIJAsmLH: |
11626 | 0 | case SystemZ::CLGIJAsmNE: |
11627 | 0 | case SystemZ::CLGIJAsmNH: |
11628 | 0 | case SystemZ::CLGIJAsmNHE: |
11629 | 0 | case SystemZ::CLGIJAsmNL: |
11630 | 0 | case SystemZ::CLGIJAsmNLE: |
11631 | 0 | case SystemZ::CLGIJAsmNLH: |
11632 | 0 | case SystemZ::CLIJAsmE: |
11633 | 0 | case SystemZ::CLIJAsmH: |
11634 | 0 | case SystemZ::CLIJAsmHE: |
11635 | 0 | case SystemZ::CLIJAsmL: |
11636 | 0 | case SystemZ::CLIJAsmLE: |
11637 | 0 | case SystemZ::CLIJAsmLH: |
11638 | 0 | case SystemZ::CLIJAsmNE: |
11639 | 0 | case SystemZ::CLIJAsmNH: |
11640 | 0 | case SystemZ::CLIJAsmNHE: |
11641 | 0 | case SystemZ::CLIJAsmNL: |
11642 | 0 | case SystemZ::CLIJAsmNLE: |
11643 | 0 | case SystemZ::CLIJAsmNLH: { |
11644 | 0 | switch (OpNum) { |
11645 | 0 | case 0: |
11646 | | // op: R1 |
11647 | 0 | return 36; |
11648 | 0 | case 1: |
11649 | | // op: I2 |
11650 | 0 | return 8; |
11651 | 0 | case 2: |
11652 | | // op: RI4 |
11653 | 0 | return 16; |
11654 | 0 | } |
11655 | 0 | break; |
11656 | 0 | } |
11657 | 0 | case SystemZ::CLMH: |
11658 | 0 | case SystemZ::CLMY: |
11659 | 0 | case SystemZ::STCMH: |
11660 | 0 | case SystemZ::STCMY: { |
11661 | 0 | switch (OpNum) { |
11662 | 0 | case 0: |
11663 | | // op: R1 |
11664 | 0 | return 36; |
11665 | 0 | case 1: |
11666 | | // op: M3 |
11667 | 0 | return 32; |
11668 | 0 | case 2: |
11669 | | // op: B2 |
11670 | 0 | return 28; |
11671 | 0 | case 3: |
11672 | | // op: D2 |
11673 | 0 | return 8; |
11674 | 0 | } |
11675 | 0 | break; |
11676 | 0 | } |
11677 | 0 | case SystemZ::CGRBAsmE: |
11678 | 0 | case SystemZ::CGRBAsmH: |
11679 | 0 | case SystemZ::CGRBAsmHE: |
11680 | 0 | case SystemZ::CGRBAsmL: |
11681 | 0 | case SystemZ::CGRBAsmLE: |
11682 | 0 | case SystemZ::CGRBAsmLH: |
11683 | 0 | case SystemZ::CGRBAsmNE: |
11684 | 0 | case SystemZ::CGRBAsmNH: |
11685 | 0 | case SystemZ::CGRBAsmNHE: |
11686 | 0 | case SystemZ::CGRBAsmNL: |
11687 | 0 | case SystemZ::CGRBAsmNLE: |
11688 | 0 | case SystemZ::CGRBAsmNLH: |
11689 | 0 | case SystemZ::CLGRBAsmE: |
11690 | 0 | case SystemZ::CLGRBAsmH: |
11691 | 0 | case SystemZ::CLGRBAsmHE: |
11692 | 0 | case SystemZ::CLGRBAsmL: |
11693 | 0 | case SystemZ::CLGRBAsmLE: |
11694 | 0 | case SystemZ::CLGRBAsmLH: |
11695 | 0 | case SystemZ::CLGRBAsmNE: |
11696 | 0 | case SystemZ::CLGRBAsmNH: |
11697 | 0 | case SystemZ::CLGRBAsmNHE: |
11698 | 0 | case SystemZ::CLGRBAsmNL: |
11699 | 0 | case SystemZ::CLGRBAsmNLE: |
11700 | 0 | case SystemZ::CLGRBAsmNLH: |
11701 | 0 | case SystemZ::CLRBAsmE: |
11702 | 0 | case SystemZ::CLRBAsmH: |
11703 | 0 | case SystemZ::CLRBAsmHE: |
11704 | 0 | case SystemZ::CLRBAsmL: |
11705 | 0 | case SystemZ::CLRBAsmLE: |
11706 | 0 | case SystemZ::CLRBAsmLH: |
11707 | 0 | case SystemZ::CLRBAsmNE: |
11708 | 0 | case SystemZ::CLRBAsmNH: |
11709 | 0 | case SystemZ::CLRBAsmNHE: |
11710 | 0 | case SystemZ::CLRBAsmNL: |
11711 | 0 | case SystemZ::CLRBAsmNLE: |
11712 | 0 | case SystemZ::CLRBAsmNLH: |
11713 | 0 | case SystemZ::CRBAsmE: |
11714 | 0 | case SystemZ::CRBAsmH: |
11715 | 0 | case SystemZ::CRBAsmHE: |
11716 | 0 | case SystemZ::CRBAsmL: |
11717 | 0 | case SystemZ::CRBAsmLE: |
11718 | 0 | case SystemZ::CRBAsmLH: |
11719 | 0 | case SystemZ::CRBAsmNE: |
11720 | 0 | case SystemZ::CRBAsmNH: |
11721 | 0 | case SystemZ::CRBAsmNHE: |
11722 | 0 | case SystemZ::CRBAsmNL: |
11723 | 0 | case SystemZ::CRBAsmNLE: |
11724 | 0 | case SystemZ::CRBAsmNLH: { |
11725 | 0 | switch (OpNum) { |
11726 | 0 | case 0: |
11727 | | // op: R1 |
11728 | 0 | return 36; |
11729 | 0 | case 1: |
11730 | | // op: R2 |
11731 | 0 | return 32; |
11732 | 0 | case 2: |
11733 | | // op: B4 |
11734 | 0 | return 28; |
11735 | 0 | case 3: |
11736 | | // op: D4 |
11737 | 0 | return 16; |
11738 | 0 | } |
11739 | 0 | break; |
11740 | 0 | } |
11741 | 0 | case SystemZ::CGRB: |
11742 | 0 | case SystemZ::CGRBAsm: |
11743 | 0 | case SystemZ::CLGRB: |
11744 | 0 | case SystemZ::CLGRBAsm: |
11745 | 0 | case SystemZ::CLRB: |
11746 | 0 | case SystemZ::CLRBAsm: |
11747 | 0 | case SystemZ::CRB: |
11748 | 0 | case SystemZ::CRBAsm: { |
11749 | 0 | switch (OpNum) { |
11750 | 0 | case 0: |
11751 | | // op: R1 |
11752 | 0 | return 36; |
11753 | 0 | case 1: |
11754 | | // op: R2 |
11755 | 0 | return 32; |
11756 | 0 | case 2: |
11757 | | // op: M3 |
11758 | 0 | return 12; |
11759 | 0 | case 3: |
11760 | | // op: B4 |
11761 | 0 | return 28; |
11762 | 0 | case 4: |
11763 | | // op: D4 |
11764 | 0 | return 16; |
11765 | 0 | } |
11766 | 0 | break; |
11767 | 0 | } |
11768 | 0 | case SystemZ::CGRJ: |
11769 | 0 | case SystemZ::CGRJAsm: |
11770 | 0 | case SystemZ::CLGRJ: |
11771 | 0 | case SystemZ::CLGRJAsm: |
11772 | 0 | case SystemZ::CLRJ: |
11773 | 0 | case SystemZ::CLRJAsm: |
11774 | 0 | case SystemZ::CRJ: |
11775 | 0 | case SystemZ::CRJAsm: { |
11776 | 0 | switch (OpNum) { |
11777 | 0 | case 0: |
11778 | | // op: R1 |
11779 | 0 | return 36; |
11780 | 0 | case 1: |
11781 | | // op: R2 |
11782 | 0 | return 32; |
11783 | 0 | case 2: |
11784 | | // op: M3 |
11785 | 0 | return 12; |
11786 | 0 | case 3: |
11787 | | // op: RI4 |
11788 | 0 | return 16; |
11789 | 0 | } |
11790 | 0 | break; |
11791 | 0 | } |
11792 | 0 | case SystemZ::CGRJAsmE: |
11793 | 0 | case SystemZ::CGRJAsmH: |
11794 | 0 | case SystemZ::CGRJAsmHE: |
11795 | 0 | case SystemZ::CGRJAsmL: |
11796 | 0 | case SystemZ::CGRJAsmLE: |
11797 | 0 | case SystemZ::CGRJAsmLH: |
11798 | 0 | case SystemZ::CGRJAsmNE: |
11799 | 0 | case SystemZ::CGRJAsmNH: |
11800 | 0 | case SystemZ::CGRJAsmNHE: |
11801 | 0 | case SystemZ::CGRJAsmNL: |
11802 | 0 | case SystemZ::CGRJAsmNLE: |
11803 | 0 | case SystemZ::CGRJAsmNLH: |
11804 | 0 | case SystemZ::CLGRJAsmE: |
11805 | 0 | case SystemZ::CLGRJAsmH: |
11806 | 0 | case SystemZ::CLGRJAsmHE: |
11807 | 0 | case SystemZ::CLGRJAsmL: |
11808 | 0 | case SystemZ::CLGRJAsmLE: |
11809 | 0 | case SystemZ::CLGRJAsmLH: |
11810 | 0 | case SystemZ::CLGRJAsmNE: |
11811 | 0 | case SystemZ::CLGRJAsmNH: |
11812 | 0 | case SystemZ::CLGRJAsmNHE: |
11813 | 0 | case SystemZ::CLGRJAsmNL: |
11814 | 0 | case SystemZ::CLGRJAsmNLE: |
11815 | 0 | case SystemZ::CLGRJAsmNLH: |
11816 | 0 | case SystemZ::CLRJAsmE: |
11817 | 0 | case SystemZ::CLRJAsmH: |
11818 | 0 | case SystemZ::CLRJAsmHE: |
11819 | 0 | case SystemZ::CLRJAsmL: |
11820 | 0 | case SystemZ::CLRJAsmLE: |
11821 | 0 | case SystemZ::CLRJAsmLH: |
11822 | 0 | case SystemZ::CLRJAsmNE: |
11823 | 0 | case SystemZ::CLRJAsmNH: |
11824 | 0 | case SystemZ::CLRJAsmNHE: |
11825 | 0 | case SystemZ::CLRJAsmNL: |
11826 | 0 | case SystemZ::CLRJAsmNLE: |
11827 | 0 | case SystemZ::CLRJAsmNLH: |
11828 | 0 | case SystemZ::CRJAsmE: |
11829 | 0 | case SystemZ::CRJAsmH: |
11830 | 0 | case SystemZ::CRJAsmHE: |
11831 | 0 | case SystemZ::CRJAsmL: |
11832 | 0 | case SystemZ::CRJAsmLE: |
11833 | 0 | case SystemZ::CRJAsmLH: |
11834 | 0 | case SystemZ::CRJAsmNE: |
11835 | 0 | case SystemZ::CRJAsmNH: |
11836 | 0 | case SystemZ::CRJAsmNHE: |
11837 | 0 | case SystemZ::CRJAsmNL: |
11838 | 0 | case SystemZ::CRJAsmNLE: |
11839 | 0 | case SystemZ::CRJAsmNLH: { |
11840 | 0 | switch (OpNum) { |
11841 | 0 | case 0: |
11842 | | // op: R1 |
11843 | 0 | return 36; |
11844 | 0 | case 1: |
11845 | | // op: R2 |
11846 | 0 | return 32; |
11847 | 0 | case 2: |
11848 | | // op: RI4 |
11849 | 0 | return 16; |
11850 | 0 | } |
11851 | 0 | break; |
11852 | 0 | } |
11853 | 0 | case SystemZ::ECAG: |
11854 | 0 | case SystemZ::LAA: |
11855 | 0 | case SystemZ::LAAG: |
11856 | 0 | case SystemZ::LAAL: |
11857 | 0 | case SystemZ::LAALG: |
11858 | 0 | case SystemZ::LAMY: |
11859 | 0 | case SystemZ::LAN: |
11860 | 0 | case SystemZ::LANG: |
11861 | 0 | case SystemZ::LAO: |
11862 | 0 | case SystemZ::LAOG: |
11863 | 0 | case SystemZ::LAX: |
11864 | 0 | case SystemZ::LAXG: |
11865 | 0 | case SystemZ::LCTLG: |
11866 | 0 | case SystemZ::LMG: |
11867 | 0 | case SystemZ::LMH: |
11868 | 0 | case SystemZ::LMY: |
11869 | 0 | case SystemZ::RLL: |
11870 | 0 | case SystemZ::RLLG: |
11871 | 0 | case SystemZ::SLAG: |
11872 | 0 | case SystemZ::SLAK: |
11873 | 0 | case SystemZ::SLLG: |
11874 | 0 | case SystemZ::SLLK: |
11875 | 0 | case SystemZ::SRAG: |
11876 | 0 | case SystemZ::SRAK: |
11877 | 0 | case SystemZ::SRLG: |
11878 | 0 | case SystemZ::SRLK: |
11879 | 0 | case SystemZ::STAMY: |
11880 | 0 | case SystemZ::STCTG: |
11881 | 0 | case SystemZ::STMG: |
11882 | 0 | case SystemZ::STMH: |
11883 | 0 | case SystemZ::STMY: |
11884 | 0 | case SystemZ::TRACG: { |
11885 | 0 | switch (OpNum) { |
11886 | 0 | case 0: |
11887 | | // op: R1 |
11888 | 0 | return 36; |
11889 | 0 | case 1: |
11890 | | // op: R3 |
11891 | 0 | return 32; |
11892 | 0 | case 2: |
11893 | | // op: B2 |
11894 | 0 | return 28; |
11895 | 0 | case 3: |
11896 | | // op: D2 |
11897 | 0 | return 8; |
11898 | 0 | } |
11899 | 0 | break; |
11900 | 0 | } |
11901 | 0 | case SystemZ::AGHIK: |
11902 | 0 | case SystemZ::AHIK: |
11903 | 0 | case SystemZ::ALGHSIK: |
11904 | 0 | case SystemZ::ALHSIK: { |
11905 | 0 | switch (OpNum) { |
11906 | 0 | case 0: |
11907 | | // op: R1 |
11908 | 0 | return 36; |
11909 | 0 | case 1: |
11910 | | // op: R3 |
11911 | 0 | return 32; |
11912 | 0 | case 2: |
11913 | | // op: I2 |
11914 | 0 | return 16; |
11915 | 0 | } |
11916 | 0 | break; |
11917 | 0 | } |
11918 | 0 | case SystemZ::CLCLU: |
11919 | 0 | case SystemZ::MVCLU: { |
11920 | 0 | switch (OpNum) { |
11921 | 0 | case 0: |
11922 | | // op: R1 |
11923 | 0 | return 36; |
11924 | 0 | case 1: |
11925 | | // op: R3 |
11926 | 0 | return 32; |
11927 | 0 | case 4: |
11928 | | // op: B2 |
11929 | 0 | return 28; |
11930 | 0 | case 5: |
11931 | | // op: D2 |
11932 | 0 | return 8; |
11933 | 0 | } |
11934 | 0 | break; |
11935 | 0 | } |
11936 | 0 | case SystemZ::BRASL: |
11937 | 0 | case SystemZ::CGFRL: |
11938 | 0 | case SystemZ::CGHRL: |
11939 | 0 | case SystemZ::CGRL: |
11940 | 0 | case SystemZ::CHRL: |
11941 | 0 | case SystemZ::CLGFRL: |
11942 | 0 | case SystemZ::CLGHRL: |
11943 | 0 | case SystemZ::CLGRL: |
11944 | 0 | case SystemZ::CLHRL: |
11945 | 0 | case SystemZ::CLRL: |
11946 | 0 | case SystemZ::CRL: |
11947 | 0 | case SystemZ::EXRL: |
11948 | 0 | case SystemZ::LARL: |
11949 | 0 | case SystemZ::LGFRL: |
11950 | 0 | case SystemZ::LGHRL: |
11951 | 0 | case SystemZ::LGRL: |
11952 | 0 | case SystemZ::LHRL: |
11953 | 0 | case SystemZ::LLGFRL: |
11954 | 0 | case SystemZ::LLGHRL: |
11955 | 0 | case SystemZ::LLHRL: |
11956 | 0 | case SystemZ::LRL: |
11957 | 0 | case SystemZ::STGRL: |
11958 | 0 | case SystemZ::STHRL: |
11959 | 0 | case SystemZ::STRL: { |
11960 | 0 | switch (OpNum) { |
11961 | 0 | case 0: |
11962 | | // op: R1 |
11963 | 0 | return 36; |
11964 | 0 | case 1: |
11965 | | // op: RI2 |
11966 | 0 | return 0; |
11967 | 0 | } |
11968 | 0 | break; |
11969 | 0 | } |
11970 | 0 | case SystemZ::VCVBGOpt: |
11971 | 0 | case SystemZ::VCVBOpt: { |
11972 | 0 | switch (OpNum) { |
11973 | 0 | case 0: |
11974 | | // op: R1 |
11975 | 0 | return 36; |
11976 | 0 | case 1: |
11977 | | // op: V2 |
11978 | 0 | return 10; |
11979 | 0 | case 2: |
11980 | | // op: M3 |
11981 | 0 | return 20; |
11982 | 0 | case 3: |
11983 | | // op: M4 |
11984 | 0 | return 16; |
11985 | 0 | } |
11986 | 0 | break; |
11987 | 0 | } |
11988 | 0 | case SystemZ::VCVB: |
11989 | 0 | case SystemZ::VCVBG: { |
11990 | 0 | switch (OpNum) { |
11991 | 0 | case 0: |
11992 | | // op: R1 |
11993 | 0 | return 36; |
11994 | 0 | case 1: |
11995 | | // op: V2 |
11996 | 0 | return 10; |
11997 | 0 | case 2: |
11998 | | // op: M3 |
11999 | 0 | return 20; |
12000 | 0 | } |
12001 | 0 | break; |
12002 | 0 | } |
12003 | 0 | case SystemZ::LMD: { |
12004 | 0 | switch (OpNum) { |
12005 | 0 | case 0: |
12006 | | // op: R1 |
12007 | 0 | return 36; |
12008 | 0 | case 2: |
12009 | | // op: B2 |
12010 | 0 | return 28; |
12011 | 0 | case 3: |
12012 | | // op: D2 |
12013 | 0 | return 16; |
12014 | 0 | case 1: |
12015 | | // op: R3 |
12016 | 0 | return 32; |
12017 | 0 | case 4: |
12018 | | // op: B4 |
12019 | 0 | return 12; |
12020 | 0 | case 5: |
12021 | | // op: D4 |
12022 | 0 | return 0; |
12023 | 0 | } |
12024 | 0 | break; |
12025 | 0 | } |
12026 | 0 | case SystemZ::VLGV: { |
12027 | 0 | switch (OpNum) { |
12028 | 0 | case 0: |
12029 | | // op: R1 |
12030 | 0 | return 36; |
12031 | 0 | case 2: |
12032 | | // op: B2 |
12033 | 0 | return 28; |
12034 | 0 | case 3: |
12035 | | // op: D2 |
12036 | 0 | return 16; |
12037 | 0 | case 1: |
12038 | | // op: V3 |
12039 | 0 | return 10; |
12040 | 0 | case 4: |
12041 | | // op: M4 |
12042 | 0 | return 12; |
12043 | 0 | } |
12044 | 0 | break; |
12045 | 0 | } |
12046 | 0 | case SystemZ::VLGVB: |
12047 | 0 | case SystemZ::VLGVF: |
12048 | 0 | case SystemZ::VLGVG: |
12049 | 0 | case SystemZ::VLGVH: { |
12050 | 0 | switch (OpNum) { |
12051 | 0 | case 0: |
12052 | | // op: R1 |
12053 | 0 | return 36; |
12054 | 0 | case 2: |
12055 | | // op: B2 |
12056 | 0 | return 28; |
12057 | 0 | case 3: |
12058 | | // op: D2 |
12059 | 0 | return 16; |
12060 | 0 | case 1: |
12061 | | // op: V3 |
12062 | 0 | return 10; |
12063 | 0 | } |
12064 | 0 | break; |
12065 | 0 | } |
12066 | 0 | case SystemZ::LOCAsmE: |
12067 | 0 | case SystemZ::LOCAsmH: |
12068 | 0 | case SystemZ::LOCAsmHE: |
12069 | 0 | case SystemZ::LOCAsmL: |
12070 | 0 | case SystemZ::LOCAsmLE: |
12071 | 0 | case SystemZ::LOCAsmLH: |
12072 | 0 | case SystemZ::LOCAsmM: |
12073 | 0 | case SystemZ::LOCAsmNE: |
12074 | 0 | case SystemZ::LOCAsmNH: |
12075 | 0 | case SystemZ::LOCAsmNHE: |
12076 | 0 | case SystemZ::LOCAsmNL: |
12077 | 0 | case SystemZ::LOCAsmNLE: |
12078 | 0 | case SystemZ::LOCAsmNLH: |
12079 | 0 | case SystemZ::LOCAsmNM: |
12080 | 0 | case SystemZ::LOCAsmNO: |
12081 | 0 | case SystemZ::LOCAsmNP: |
12082 | 0 | case SystemZ::LOCAsmNZ: |
12083 | 0 | case SystemZ::LOCAsmO: |
12084 | 0 | case SystemZ::LOCAsmP: |
12085 | 0 | case SystemZ::LOCAsmZ: |
12086 | 0 | case SystemZ::LOCFHAsmE: |
12087 | 0 | case SystemZ::LOCFHAsmH: |
12088 | 0 | case SystemZ::LOCFHAsmHE: |
12089 | 0 | case SystemZ::LOCFHAsmL: |
12090 | 0 | case SystemZ::LOCFHAsmLE: |
12091 | 0 | case SystemZ::LOCFHAsmLH: |
12092 | 0 | case SystemZ::LOCFHAsmM: |
12093 | 0 | case SystemZ::LOCFHAsmNE: |
12094 | 0 | case SystemZ::LOCFHAsmNH: |
12095 | 0 | case SystemZ::LOCFHAsmNHE: |
12096 | 0 | case SystemZ::LOCFHAsmNL: |
12097 | 0 | case SystemZ::LOCFHAsmNLE: |
12098 | 0 | case SystemZ::LOCFHAsmNLH: |
12099 | 0 | case SystemZ::LOCFHAsmNM: |
12100 | 0 | case SystemZ::LOCFHAsmNO: |
12101 | 0 | case SystemZ::LOCFHAsmNP: |
12102 | 0 | case SystemZ::LOCFHAsmNZ: |
12103 | 0 | case SystemZ::LOCFHAsmO: |
12104 | 0 | case SystemZ::LOCFHAsmP: |
12105 | 0 | case SystemZ::LOCFHAsmZ: |
12106 | 0 | case SystemZ::LOCGAsmE: |
12107 | 0 | case SystemZ::LOCGAsmH: |
12108 | 0 | case SystemZ::LOCGAsmHE: |
12109 | 0 | case SystemZ::LOCGAsmL: |
12110 | 0 | case SystemZ::LOCGAsmLE: |
12111 | 0 | case SystemZ::LOCGAsmLH: |
12112 | 0 | case SystemZ::LOCGAsmM: |
12113 | 0 | case SystemZ::LOCGAsmNE: |
12114 | 0 | case SystemZ::LOCGAsmNH: |
12115 | 0 | case SystemZ::LOCGAsmNHE: |
12116 | 0 | case SystemZ::LOCGAsmNL: |
12117 | 0 | case SystemZ::LOCGAsmNLE: |
12118 | 0 | case SystemZ::LOCGAsmNLH: |
12119 | 0 | case SystemZ::LOCGAsmNM: |
12120 | 0 | case SystemZ::LOCGAsmNO: |
12121 | 0 | case SystemZ::LOCGAsmNP: |
12122 | 0 | case SystemZ::LOCGAsmNZ: |
12123 | 0 | case SystemZ::LOCGAsmO: |
12124 | 0 | case SystemZ::LOCGAsmP: |
12125 | 0 | case SystemZ::LOCGAsmZ: { |
12126 | 0 | switch (OpNum) { |
12127 | 0 | case 0: |
12128 | | // op: R1 |
12129 | 0 | return 36; |
12130 | 0 | case 2: |
12131 | | // op: B2 |
12132 | 0 | return 28; |
12133 | 0 | case 3: |
12134 | | // op: D2 |
12135 | 0 | return 8; |
12136 | 0 | } |
12137 | 0 | break; |
12138 | 0 | } |
12139 | 0 | case SystemZ::AFI: |
12140 | 0 | case SystemZ::AGFI: |
12141 | 0 | case SystemZ::AIH: |
12142 | 0 | case SystemZ::ALFI: |
12143 | 0 | case SystemZ::ALGFI: |
12144 | 0 | case SystemZ::ALSIH: |
12145 | 0 | case SystemZ::ALSIHN: |
12146 | 0 | case SystemZ::MSFI: |
12147 | 0 | case SystemZ::MSGFI: |
12148 | 0 | case SystemZ::NIHF: |
12149 | 0 | case SystemZ::NILF: |
12150 | 0 | case SystemZ::OIHF: |
12151 | 0 | case SystemZ::OILF: |
12152 | 0 | case SystemZ::SLFI: |
12153 | 0 | case SystemZ::SLGFI: |
12154 | 0 | case SystemZ::XIHF: |
12155 | 0 | case SystemZ::XILF: { |
12156 | 0 | switch (OpNum) { |
12157 | 0 | case 0: |
12158 | | // op: R1 |
12159 | 0 | return 36; |
12160 | 0 | case 2: |
12161 | | // op: I2 |
12162 | 0 | return 0; |
12163 | 0 | } |
12164 | 0 | break; |
12165 | 0 | } |
12166 | 0 | case SystemZ::LOCGHIAsmE: |
12167 | 0 | case SystemZ::LOCGHIAsmH: |
12168 | 0 | case SystemZ::LOCGHIAsmHE: |
12169 | 0 | case SystemZ::LOCGHIAsmL: |
12170 | 0 | case SystemZ::LOCGHIAsmLE: |
12171 | 0 | case SystemZ::LOCGHIAsmLH: |
12172 | 0 | case SystemZ::LOCGHIAsmM: |
12173 | 0 | case SystemZ::LOCGHIAsmNE: |
12174 | 0 | case SystemZ::LOCGHIAsmNH: |
12175 | 0 | case SystemZ::LOCGHIAsmNHE: |
12176 | 0 | case SystemZ::LOCGHIAsmNL: |
12177 | 0 | case SystemZ::LOCGHIAsmNLE: |
12178 | 0 | case SystemZ::LOCGHIAsmNLH: |
12179 | 0 | case SystemZ::LOCGHIAsmNM: |
12180 | 0 | case SystemZ::LOCGHIAsmNO: |
12181 | 0 | case SystemZ::LOCGHIAsmNP: |
12182 | 0 | case SystemZ::LOCGHIAsmNZ: |
12183 | 0 | case SystemZ::LOCGHIAsmO: |
12184 | 0 | case SystemZ::LOCGHIAsmP: |
12185 | 0 | case SystemZ::LOCGHIAsmZ: |
12186 | 0 | case SystemZ::LOCHHIAsmE: |
12187 | 0 | case SystemZ::LOCHHIAsmH: |
12188 | 0 | case SystemZ::LOCHHIAsmHE: |
12189 | 0 | case SystemZ::LOCHHIAsmL: |
12190 | 0 | case SystemZ::LOCHHIAsmLE: |
12191 | 0 | case SystemZ::LOCHHIAsmLH: |
12192 | 0 | case SystemZ::LOCHHIAsmM: |
12193 | 0 | case SystemZ::LOCHHIAsmNE: |
12194 | 0 | case SystemZ::LOCHHIAsmNH: |
12195 | 0 | case SystemZ::LOCHHIAsmNHE: |
12196 | 0 | case SystemZ::LOCHHIAsmNL: |
12197 | 0 | case SystemZ::LOCHHIAsmNLE: |
12198 | 0 | case SystemZ::LOCHHIAsmNLH: |
12199 | 0 | case SystemZ::LOCHHIAsmNM: |
12200 | 0 | case SystemZ::LOCHHIAsmNO: |
12201 | 0 | case SystemZ::LOCHHIAsmNP: |
12202 | 0 | case SystemZ::LOCHHIAsmNZ: |
12203 | 0 | case SystemZ::LOCHHIAsmO: |
12204 | 0 | case SystemZ::LOCHHIAsmP: |
12205 | 0 | case SystemZ::LOCHHIAsmZ: |
12206 | 0 | case SystemZ::LOCHIAsmE: |
12207 | 0 | case SystemZ::LOCHIAsmH: |
12208 | 0 | case SystemZ::LOCHIAsmHE: |
12209 | 0 | case SystemZ::LOCHIAsmL: |
12210 | 0 | case SystemZ::LOCHIAsmLE: |
12211 | 0 | case SystemZ::LOCHIAsmLH: |
12212 | 0 | case SystemZ::LOCHIAsmM: |
12213 | 0 | case SystemZ::LOCHIAsmNE: |
12214 | 0 | case SystemZ::LOCHIAsmNH: |
12215 | 0 | case SystemZ::LOCHIAsmNHE: |
12216 | 0 | case SystemZ::LOCHIAsmNL: |
12217 | 0 | case SystemZ::LOCHIAsmNLE: |
12218 | 0 | case SystemZ::LOCHIAsmNLH: |
12219 | 0 | case SystemZ::LOCHIAsmNM: |
12220 | 0 | case SystemZ::LOCHIAsmNO: |
12221 | 0 | case SystemZ::LOCHIAsmNP: |
12222 | 0 | case SystemZ::LOCHIAsmNZ: |
12223 | 0 | case SystemZ::LOCHIAsmO: |
12224 | 0 | case SystemZ::LOCHIAsmP: |
12225 | 0 | case SystemZ::LOCHIAsmZ: { |
12226 | 0 | switch (OpNum) { |
12227 | 0 | case 0: |
12228 | | // op: R1 |
12229 | 0 | return 36; |
12230 | 0 | case 2: |
12231 | | // op: I2 |
12232 | 0 | return 16; |
12233 | 0 | } |
12234 | 0 | break; |
12235 | 0 | } |
12236 | 0 | case SystemZ::ICMH: |
12237 | 0 | case SystemZ::ICMY: { |
12238 | 0 | switch (OpNum) { |
12239 | 0 | case 0: |
12240 | | // op: R1 |
12241 | 0 | return 36; |
12242 | 0 | case 2: |
12243 | | // op: M3 |
12244 | 0 | return 32; |
12245 | 0 | case 3: |
12246 | | // op: B2 |
12247 | 0 | return 28; |
12248 | 0 | case 4: |
12249 | | // op: D2 |
12250 | 0 | return 8; |
12251 | 0 | } |
12252 | 0 | break; |
12253 | 0 | } |
12254 | 0 | case SystemZ::RISBG: |
12255 | 0 | case SystemZ::RISBG32: |
12256 | 0 | case SystemZ::RISBGN: |
12257 | 0 | case SystemZ::RISBHG: |
12258 | 0 | case SystemZ::RISBLG: |
12259 | 0 | case SystemZ::RNSBG: |
12260 | 0 | case SystemZ::ROSBG: |
12261 | 0 | case SystemZ::RXSBG: { |
12262 | 0 | switch (OpNum) { |
12263 | 0 | case 0: |
12264 | | // op: R1 |
12265 | 0 | return 36; |
12266 | 0 | case 2: |
12267 | | // op: R2 |
12268 | 0 | return 32; |
12269 | 0 | case 3: |
12270 | | // op: I3 |
12271 | 0 | return 24; |
12272 | 0 | case 4: |
12273 | | // op: I4 |
12274 | 0 | return 16; |
12275 | 0 | case 5: |
12276 | | // op: I5 |
12277 | 0 | return 8; |
12278 | 0 | } |
12279 | 0 | break; |
12280 | 0 | } |
12281 | 0 | case SystemZ::BXHG: |
12282 | 0 | case SystemZ::BXLEG: |
12283 | 0 | case SystemZ::CDSG: |
12284 | 0 | case SystemZ::CDSY: |
12285 | 0 | case SystemZ::CSG: |
12286 | 0 | case SystemZ::CSY: { |
12287 | 0 | switch (OpNum) { |
12288 | 0 | case 0: |
12289 | | // op: R1 |
12290 | 0 | return 36; |
12291 | 0 | case 2: |
12292 | | // op: R3 |
12293 | 0 | return 32; |
12294 | 0 | case 3: |
12295 | | // op: B2 |
12296 | 0 | return 28; |
12297 | 0 | case 4: |
12298 | | // op: D2 |
12299 | 0 | return 8; |
12300 | 0 | } |
12301 | 0 | break; |
12302 | 0 | } |
12303 | 0 | case SystemZ::BRXHG: |
12304 | 0 | case SystemZ::BRXLG: { |
12305 | 0 | switch (OpNum) { |
12306 | 0 | case 0: |
12307 | | // op: R1 |
12308 | 0 | return 36; |
12309 | 0 | case 2: |
12310 | | // op: R3 |
12311 | 0 | return 32; |
12312 | 0 | case 3: |
12313 | | // op: RI2 |
12314 | 0 | return 16; |
12315 | 0 | } |
12316 | 0 | break; |
12317 | 0 | } |
12318 | 0 | case SystemZ::BRCTH: { |
12319 | 0 | switch (OpNum) { |
12320 | 0 | case 0: |
12321 | | // op: R1 |
12322 | 0 | return 36; |
12323 | 0 | case 2: |
12324 | | // op: RI2 |
12325 | 0 | return 0; |
12326 | 0 | } |
12327 | 0 | break; |
12328 | 0 | } |
12329 | 0 | case SystemZ::CLGT: |
12330 | 0 | case SystemZ::CLGTAsm: |
12331 | 0 | case SystemZ::CLT: |
12332 | 0 | case SystemZ::CLTAsm: |
12333 | 0 | case SystemZ::STOCAsm: |
12334 | 0 | case SystemZ::STOCFHAsm: |
12335 | 0 | case SystemZ::STOCGAsm: { |
12336 | 0 | switch (OpNum) { |
12337 | 0 | case 0: |
12338 | | // op: R1 |
12339 | 0 | return 36; |
12340 | 0 | case 3: |
12341 | | // op: M3 |
12342 | 0 | return 32; |
12343 | 0 | case 1: |
12344 | | // op: B2 |
12345 | 0 | return 28; |
12346 | 0 | case 2: |
12347 | | // op: D2 |
12348 | 0 | return 8; |
12349 | 0 | } |
12350 | 0 | break; |
12351 | 0 | } |
12352 | 0 | case SystemZ::LOCGHIAsm: |
12353 | 0 | case SystemZ::LOCHHIAsm: |
12354 | 0 | case SystemZ::LOCHIAsm: { |
12355 | 0 | switch (OpNum) { |
12356 | 0 | case 0: |
12357 | | // op: R1 |
12358 | 0 | return 36; |
12359 | 0 | case 3: |
12360 | | // op: M3 |
12361 | 0 | return 32; |
12362 | 0 | case 2: |
12363 | | // op: I2 |
12364 | 0 | return 16; |
12365 | 0 | } |
12366 | 0 | break; |
12367 | 0 | } |
12368 | 0 | case SystemZ::LCBB: { |
12369 | 0 | switch (OpNum) { |
12370 | 0 | case 0: |
12371 | | // op: R1 |
12372 | 0 | return 36; |
12373 | 0 | case 3: |
12374 | | // op: X2 |
12375 | 0 | return 32; |
12376 | 0 | case 1: |
12377 | | // op: B2 |
12378 | 0 | return 28; |
12379 | 0 | case 2: |
12380 | | // op: D2 |
12381 | 0 | return 16; |
12382 | 0 | case 4: |
12383 | | // op: M3 |
12384 | 0 | return 12; |
12385 | 0 | } |
12386 | 0 | break; |
12387 | 0 | } |
12388 | 0 | case SystemZ::CDB: |
12389 | 0 | case SystemZ::CEB: |
12390 | 0 | case SystemZ::KDB: |
12391 | 0 | case SystemZ::KEB: |
12392 | 0 | case SystemZ::LDE: |
12393 | 0 | case SystemZ::LDE32: |
12394 | 0 | case SystemZ::LDEB: |
12395 | 0 | case SystemZ::LXD: |
12396 | 0 | case SystemZ::LXDB: |
12397 | 0 | case SystemZ::LXE: |
12398 | 0 | case SystemZ::LXEB: |
12399 | 0 | case SystemZ::SQD: |
12400 | 0 | case SystemZ::SQDB: |
12401 | 0 | case SystemZ::SQE: |
12402 | 0 | case SystemZ::SQEB: |
12403 | 0 | case SystemZ::TCDB: |
12404 | 0 | case SystemZ::TCEB: |
12405 | 0 | case SystemZ::TCXB: |
12406 | 0 | case SystemZ::TDCDT: |
12407 | 0 | case SystemZ::TDCET: |
12408 | 0 | case SystemZ::TDCXT: |
12409 | 0 | case SystemZ::TDGDT: |
12410 | 0 | case SystemZ::TDGET: |
12411 | 0 | case SystemZ::TDGXT: { |
12412 | 0 | switch (OpNum) { |
12413 | 0 | case 0: |
12414 | | // op: R1 |
12415 | 0 | return 36; |
12416 | 0 | case 3: |
12417 | | // op: X2 |
12418 | 0 | return 32; |
12419 | 0 | case 1: |
12420 | | // op: B2 |
12421 | 0 | return 28; |
12422 | 0 | case 2: |
12423 | | // op: D2 |
12424 | 0 | return 16; |
12425 | 0 | } |
12426 | 0 | break; |
12427 | 0 | } |
12428 | 0 | case SystemZ::CG: |
12429 | 0 | case SystemZ::CGF: |
12430 | 0 | case SystemZ::CGH: |
12431 | 0 | case SystemZ::CHF: |
12432 | 0 | case SystemZ::CHY: |
12433 | 0 | case SystemZ::CLG: |
12434 | 0 | case SystemZ::CLGF: |
12435 | 0 | case SystemZ::CLHF: |
12436 | 0 | case SystemZ::CLY: |
12437 | 0 | case SystemZ::CVDG: |
12438 | 0 | case SystemZ::CVDY: |
12439 | 0 | case SystemZ::CY: |
12440 | 0 | case SystemZ::LAEY: |
12441 | 0 | case SystemZ::LAT: |
12442 | 0 | case SystemZ::LAY: |
12443 | 0 | case SystemZ::LB: |
12444 | 0 | case SystemZ::LBH: |
12445 | 0 | case SystemZ::LDY: |
12446 | 0 | case SystemZ::LEY: |
12447 | 0 | case SystemZ::LFH: |
12448 | 0 | case SystemZ::LFHAT: |
12449 | 0 | case SystemZ::LG: |
12450 | 0 | case SystemZ::LGAT: |
12451 | 0 | case SystemZ::LGB: |
12452 | 0 | case SystemZ::LGF: |
12453 | 0 | case SystemZ::LGG: |
12454 | 0 | case SystemZ::LGH: |
12455 | 0 | case SystemZ::LGSC: |
12456 | 0 | case SystemZ::LHH: |
12457 | 0 | case SystemZ::LHY: |
12458 | 0 | case SystemZ::LLC: |
12459 | 0 | case SystemZ::LLCH: |
12460 | 0 | case SystemZ::LLGC: |
12461 | 0 | case SystemZ::LLGF: |
12462 | 0 | case SystemZ::LLGFAT: |
12463 | 0 | case SystemZ::LLGFSG: |
12464 | 0 | case SystemZ::LLGH: |
12465 | 0 | case SystemZ::LLGT: |
12466 | 0 | case SystemZ::LLGTAT: |
12467 | 0 | case SystemZ::LLH: |
12468 | 0 | case SystemZ::LLHH: |
12469 | 0 | case SystemZ::LLZRGF: |
12470 | 0 | case SystemZ::LPQ: |
12471 | 0 | case SystemZ::LRAG: |
12472 | 0 | case SystemZ::LRAY: |
12473 | 0 | case SystemZ::LRV: |
12474 | 0 | case SystemZ::LRVG: |
12475 | 0 | case SystemZ::LRVH: |
12476 | 0 | case SystemZ::LT: |
12477 | 0 | case SystemZ::LTG: |
12478 | 0 | case SystemZ::LTGF: |
12479 | 0 | case SystemZ::LY: |
12480 | 0 | case SystemZ::LZRF: |
12481 | 0 | case SystemZ::LZRG: |
12482 | 0 | case SystemZ::NTSTG: |
12483 | 0 | case SystemZ::STCH: |
12484 | 0 | case SystemZ::STCY: |
12485 | 0 | case SystemZ::STDY: |
12486 | 0 | case SystemZ::STEY: |
12487 | 0 | case SystemZ::STFH: |
12488 | 0 | case SystemZ::STG: |
12489 | 0 | case SystemZ::STGSC: |
12490 | 0 | case SystemZ::STHH: |
12491 | 0 | case SystemZ::STHY: |
12492 | 0 | case SystemZ::STPQ: |
12493 | 0 | case SystemZ::STRV: |
12494 | 0 | case SystemZ::STRVG: |
12495 | 0 | case SystemZ::STRVH: |
12496 | 0 | case SystemZ::STY: { |
12497 | 0 | switch (OpNum) { |
12498 | 0 | case 0: |
12499 | | // op: R1 |
12500 | 0 | return 36; |
12501 | 0 | case 3: |
12502 | | // op: X2 |
12503 | 0 | return 32; |
12504 | 0 | case 1: |
12505 | | // op: B2 |
12506 | 0 | return 28; |
12507 | 0 | case 2: |
12508 | | // op: D2 |
12509 | 0 | return 8; |
12510 | 0 | } |
12511 | 0 | break; |
12512 | 0 | } |
12513 | 0 | case SystemZ::STOC: |
12514 | 0 | case SystemZ::STOCFH: |
12515 | 0 | case SystemZ::STOCG: { |
12516 | 0 | switch (OpNum) { |
12517 | 0 | case 0: |
12518 | | // op: R1 |
12519 | 0 | return 36; |
12520 | 0 | case 4: |
12521 | | // op: M3 |
12522 | 0 | return 32; |
12523 | 0 | case 1: |
12524 | | // op: B2 |
12525 | 0 | return 28; |
12526 | 0 | case 2: |
12527 | | // op: D2 |
12528 | 0 | return 8; |
12529 | 0 | } |
12530 | 0 | break; |
12531 | 0 | } |
12532 | 0 | case SystemZ::LOCAsm: |
12533 | 0 | case SystemZ::LOCFHAsm: |
12534 | 0 | case SystemZ::LOCGAsm: { |
12535 | 0 | switch (OpNum) { |
12536 | 0 | case 0: |
12537 | | // op: R1 |
12538 | 0 | return 36; |
12539 | 0 | case 4: |
12540 | | // op: M3 |
12541 | 0 | return 32; |
12542 | 0 | case 2: |
12543 | | // op: B2 |
12544 | 0 | return 28; |
12545 | 0 | case 3: |
12546 | | // op: D2 |
12547 | 0 | return 8; |
12548 | 0 | } |
12549 | 0 | break; |
12550 | 0 | } |
12551 | 0 | case SystemZ::LOCGHI: |
12552 | 0 | case SystemZ::LOCHHI: |
12553 | 0 | case SystemZ::LOCHI: { |
12554 | 0 | switch (OpNum) { |
12555 | 0 | case 0: |
12556 | | // op: R1 |
12557 | 0 | return 36; |
12558 | 0 | case 4: |
12559 | | // op: M3 |
12560 | 0 | return 32; |
12561 | 0 | case 2: |
12562 | | // op: I2 |
12563 | 0 | return 16; |
12564 | 0 | } |
12565 | 0 | break; |
12566 | 0 | } |
12567 | 0 | case SystemZ::ADB: |
12568 | 0 | case SystemZ::AEB: |
12569 | 0 | case SystemZ::DDB: |
12570 | 0 | case SystemZ::DEB: |
12571 | 0 | case SystemZ::MDB: |
12572 | 0 | case SystemZ::MDEB: |
12573 | 0 | case SystemZ::MEE: |
12574 | 0 | case SystemZ::MEEB: |
12575 | 0 | case SystemZ::MXDB: |
12576 | 0 | case SystemZ::SDB: |
12577 | 0 | case SystemZ::SEB: { |
12578 | 0 | switch (OpNum) { |
12579 | 0 | case 0: |
12580 | | // op: R1 |
12581 | 0 | return 36; |
12582 | 0 | case 4: |
12583 | | // op: X2 |
12584 | 0 | return 32; |
12585 | 0 | case 2: |
12586 | | // op: B2 |
12587 | 0 | return 28; |
12588 | 0 | case 3: |
12589 | | // op: D2 |
12590 | 0 | return 16; |
12591 | 0 | } |
12592 | 0 | break; |
12593 | 0 | } |
12594 | 0 | case SystemZ::AG: |
12595 | 0 | case SystemZ::AGF: |
12596 | 0 | case SystemZ::AGH: |
12597 | 0 | case SystemZ::AHY: |
12598 | 0 | case SystemZ::ALC: |
12599 | 0 | case SystemZ::ALCG: |
12600 | 0 | case SystemZ::ALG: |
12601 | 0 | case SystemZ::ALGF: |
12602 | 0 | case SystemZ::ALY: |
12603 | 0 | case SystemZ::AY: |
12604 | 0 | case SystemZ::BCTG: |
12605 | 0 | case SystemZ::CVBG: |
12606 | 0 | case SystemZ::CVBY: |
12607 | 0 | case SystemZ::DL: |
12608 | 0 | case SystemZ::DLG: |
12609 | 0 | case SystemZ::DSG: |
12610 | 0 | case SystemZ::DSGF: |
12611 | 0 | case SystemZ::IC32Y: |
12612 | 0 | case SystemZ::ICY: |
12613 | 0 | case SystemZ::MFY: |
12614 | 0 | case SystemZ::MG: |
12615 | 0 | case SystemZ::MGH: |
12616 | 0 | case SystemZ::MHY: |
12617 | 0 | case SystemZ::ML: |
12618 | 0 | case SystemZ::MLG: |
12619 | 0 | case SystemZ::MSC: |
12620 | 0 | case SystemZ::MSG: |
12621 | 0 | case SystemZ::MSGC: |
12622 | 0 | case SystemZ::MSGF: |
12623 | 0 | case SystemZ::MSY: |
12624 | 0 | case SystemZ::NG: |
12625 | 0 | case SystemZ::NY: |
12626 | 0 | case SystemZ::OG: |
12627 | 0 | case SystemZ::OY: |
12628 | 0 | case SystemZ::SG: |
12629 | 0 | case SystemZ::SGF: |
12630 | 0 | case SystemZ::SGH: |
12631 | 0 | case SystemZ::SHY: |
12632 | 0 | case SystemZ::SLB: |
12633 | 0 | case SystemZ::SLBG: |
12634 | 0 | case SystemZ::SLG: |
12635 | 0 | case SystemZ::SLGF: |
12636 | 0 | case SystemZ::SLY: |
12637 | 0 | case SystemZ::SY: |
12638 | 0 | case SystemZ::XG: |
12639 | 0 | case SystemZ::XY: { |
12640 | 0 | switch (OpNum) { |
12641 | 0 | case 0: |
12642 | | // op: R1 |
12643 | 0 | return 36; |
12644 | 0 | case 4: |
12645 | | // op: X2 |
12646 | 0 | return 32; |
12647 | 0 | case 2: |
12648 | | // op: B2 |
12649 | 0 | return 28; |
12650 | 0 | case 3: |
12651 | | // op: D2 |
12652 | 0 | return 8; |
12653 | 0 | } |
12654 | 0 | break; |
12655 | 0 | } |
12656 | 0 | case SystemZ::LOC: |
12657 | 0 | case SystemZ::LOCFH: |
12658 | 0 | case SystemZ::LOCG: { |
12659 | 0 | switch (OpNum) { |
12660 | 0 | case 0: |
12661 | | // op: R1 |
12662 | 0 | return 36; |
12663 | 0 | case 5: |
12664 | | // op: M3 |
12665 | 0 | return 32; |
12666 | 0 | case 2: |
12667 | | // op: B2 |
12668 | 0 | return 28; |
12669 | 0 | case 3: |
12670 | | // op: D2 |
12671 | 0 | return 8; |
12672 | 0 | } |
12673 | 0 | break; |
12674 | 0 | } |
12675 | 0 | case SystemZ::CGRT: |
12676 | 0 | case SystemZ::CGRTAsm: |
12677 | 0 | case SystemZ::CLGRT: |
12678 | 0 | case SystemZ::CLGRTAsm: |
12679 | 0 | case SystemZ::CLRT: |
12680 | 0 | case SystemZ::CLRTAsm: |
12681 | 0 | case SystemZ::CRT: |
12682 | 0 | case SystemZ::CRTAsm: |
12683 | 0 | case SystemZ::POPCNTOpt: |
12684 | 0 | case SystemZ::PPA: |
12685 | 0 | case SystemZ::SSKE: { |
12686 | 0 | switch (OpNum) { |
12687 | 0 | case 0: |
12688 | | // op: R1 |
12689 | 0 | return 4; |
12690 | 0 | case 1: |
12691 | | // op: R2 |
12692 | 0 | return 0; |
12693 | 0 | case 2: |
12694 | | // op: M3 |
12695 | 0 | return 12; |
12696 | 0 | } |
12697 | 0 | break; |
12698 | 0 | } |
12699 | 0 | case SystemZ::CSDTR: |
12700 | 0 | case SystemZ::CSXTR: |
12701 | 0 | case SystemZ::LDETR: |
12702 | 0 | case SystemZ::LXDTR: { |
12703 | 0 | switch (OpNum) { |
12704 | 0 | case 0: |
12705 | | // op: R1 |
12706 | 0 | return 4; |
12707 | 0 | case 1: |
12708 | | // op: R2 |
12709 | 0 | return 0; |
12710 | 0 | case 2: |
12711 | | // op: M4 |
12712 | 0 | return 8; |
12713 | 0 | } |
12714 | 0 | break; |
12715 | 0 | } |
12716 | 0 | case SystemZ::ADTRA: |
12717 | 0 | case SystemZ::AXTRA: |
12718 | 0 | case SystemZ::CRDTE: |
12719 | 0 | case SystemZ::DDTRA: |
12720 | 0 | case SystemZ::DXTRA: |
12721 | 0 | case SystemZ::IDTE: |
12722 | 0 | case SystemZ::IPTE: |
12723 | 0 | case SystemZ::MDTRA: |
12724 | 0 | case SystemZ::MXTRA: |
12725 | 0 | case SystemZ::RDP: |
12726 | 0 | case SystemZ::SDTRA: |
12727 | 0 | case SystemZ::SXTRA: { |
12728 | 0 | switch (OpNum) { |
12729 | 0 | case 0: |
12730 | | // op: R1 |
12731 | 0 | return 4; |
12732 | 0 | case 1: |
12733 | | // op: R2 |
12734 | 0 | return 0; |
12735 | 0 | case 2: |
12736 | | // op: R3 |
12737 | 0 | return 12; |
12738 | 0 | case 3: |
12739 | | // op: M4 |
12740 | 0 | return 8; |
12741 | 0 | } |
12742 | 0 | break; |
12743 | 0 | } |
12744 | 0 | case SystemZ::ADTR: |
12745 | 0 | case SystemZ::AGRK: |
12746 | 0 | case SystemZ::AHHHR: |
12747 | 0 | case SystemZ::AHHLR: |
12748 | 0 | case SystemZ::ALGRK: |
12749 | 0 | case SystemZ::ALHHHR: |
12750 | 0 | case SystemZ::ALHHLR: |
12751 | 0 | case SystemZ::ALRK: |
12752 | 0 | case SystemZ::ARK: |
12753 | 0 | case SystemZ::AXTR: |
12754 | 0 | case SystemZ::CPSDRdd: |
12755 | 0 | case SystemZ::CPSDRds: |
12756 | 0 | case SystemZ::CPSDRsd: |
12757 | 0 | case SystemZ::CPSDRss: |
12758 | 0 | case SystemZ::CRDTEOpt: |
12759 | 0 | case SystemZ::DDTR: |
12760 | 0 | case SystemZ::DXTR: |
12761 | 0 | case SystemZ::IDTEOpt: |
12762 | 0 | case SystemZ::IEDTR: |
12763 | 0 | case SystemZ::IEXTR: |
12764 | 0 | case SystemZ::IPTEOpt: |
12765 | 0 | case SystemZ::KMA: |
12766 | 0 | case SystemZ::KMCTR: |
12767 | 0 | case SystemZ::MDTR: |
12768 | 0 | case SystemZ::MGRK: |
12769 | 0 | case SystemZ::MSGRKC: |
12770 | 0 | case SystemZ::MSRKC: |
12771 | 0 | case SystemZ::MXTR: |
12772 | 0 | case SystemZ::NCGRK: |
12773 | 0 | case SystemZ::NCRK: |
12774 | 0 | case SystemZ::NGRK: |
12775 | 0 | case SystemZ::NNGRK: |
12776 | 0 | case SystemZ::NNRK: |
12777 | 0 | case SystemZ::NOGRK: |
12778 | 0 | case SystemZ::NORK: |
12779 | 0 | case SystemZ::NRK: |
12780 | 0 | case SystemZ::NXGRK: |
12781 | 0 | case SystemZ::NXRK: |
12782 | 0 | case SystemZ::OCGRK: |
12783 | 0 | case SystemZ::OCRK: |
12784 | 0 | case SystemZ::OGRK: |
12785 | 0 | case SystemZ::ORK: |
12786 | 0 | case SystemZ::RDPOpt: |
12787 | 0 | case SystemZ::SDTR: |
12788 | 0 | case SystemZ::SGRK: |
12789 | 0 | case SystemZ::SHHHR: |
12790 | 0 | case SystemZ::SHHLR: |
12791 | 0 | case SystemZ::SLGRK: |
12792 | 0 | case SystemZ::SLHHHR: |
12793 | 0 | case SystemZ::SLHHLR: |
12794 | 0 | case SystemZ::SLRK: |
12795 | 0 | case SystemZ::SRK: |
12796 | 0 | case SystemZ::SXTR: |
12797 | 0 | case SystemZ::XGRK: |
12798 | 0 | case SystemZ::XRK: { |
12799 | 0 | switch (OpNum) { |
12800 | 0 | case 0: |
12801 | | // op: R1 |
12802 | 0 | return 4; |
12803 | 0 | case 1: |
12804 | | // op: R2 |
12805 | 0 | return 0; |
12806 | 0 | case 2: |
12807 | | // op: R3 |
12808 | 0 | return 12; |
12809 | 0 | } |
12810 | 0 | break; |
12811 | 0 | } |
12812 | 0 | case SystemZ::CU12: |
12813 | 0 | case SystemZ::CU14: |
12814 | 0 | case SystemZ::CU21: |
12815 | 0 | case SystemZ::CU24: |
12816 | 0 | case SystemZ::CUTFU: |
12817 | 0 | case SystemZ::CUUTF: |
12818 | 0 | case SystemZ::TROO: |
12819 | 0 | case SystemZ::TROT: |
12820 | 0 | case SystemZ::TRTO: |
12821 | 0 | case SystemZ::TRTT: { |
12822 | 0 | switch (OpNum) { |
12823 | 0 | case 0: |
12824 | | // op: R1 |
12825 | 0 | return 4; |
12826 | 0 | case 1: |
12827 | | // op: R2 |
12828 | 0 | return 0; |
12829 | 0 | case 4: |
12830 | | // op: M3 |
12831 | 0 | return 12; |
12832 | 0 | } |
12833 | 0 | break; |
12834 | 0 | } |
12835 | 0 | case SystemZ::DFLTCC: { |
12836 | 0 | switch (OpNum) { |
12837 | 0 | case 0: |
12838 | | // op: R1 |
12839 | 0 | return 4; |
12840 | 0 | case 1: |
12841 | | // op: R2 |
12842 | 0 | return 0; |
12843 | 0 | case 4: |
12844 | | // op: R3 |
12845 | 0 | return 12; |
12846 | 0 | } |
12847 | 0 | break; |
12848 | 0 | } |
12849 | 0 | case SystemZ::BAKR: |
12850 | 0 | case SystemZ::BALR: |
12851 | 0 | case SystemZ::BASR: |
12852 | 0 | case SystemZ::BASSM: |
12853 | 0 | case SystemZ::BCRAsm: |
12854 | 0 | case SystemZ::BSA: |
12855 | 0 | case SystemZ::BSG: |
12856 | 0 | case SystemZ::BSM: |
12857 | 0 | case SystemZ::CDBR: |
12858 | 0 | case SystemZ::CDFBR: |
12859 | 0 | case SystemZ::CDFR: |
12860 | 0 | case SystemZ::CDGBR: |
12861 | 0 | case SystemZ::CDGR: |
12862 | 0 | case SystemZ::CDGTR: |
12863 | 0 | case SystemZ::CDR: |
12864 | 0 | case SystemZ::CDSTR: |
12865 | 0 | case SystemZ::CDTR: |
12866 | 0 | case SystemZ::CDUTR: |
12867 | 0 | case SystemZ::CEBR: |
12868 | 0 | case SystemZ::CEDTR: |
12869 | 0 | case SystemZ::CEFBR: |
12870 | 0 | case SystemZ::CEFR: |
12871 | 0 | case SystemZ::CEGBR: |
12872 | 0 | case SystemZ::CEGR: |
12873 | 0 | case SystemZ::CER: |
12874 | 0 | case SystemZ::CEXTR: |
12875 | 0 | case SystemZ::CGFR: |
12876 | 0 | case SystemZ::CGR: |
12877 | 0 | case SystemZ::CGRTAsmE: |
12878 | 0 | case SystemZ::CGRTAsmH: |
12879 | 0 | case SystemZ::CGRTAsmHE: |
12880 | 0 | case SystemZ::CGRTAsmL: |
12881 | 0 | case SystemZ::CGRTAsmLE: |
12882 | 0 | case SystemZ::CGRTAsmLH: |
12883 | 0 | case SystemZ::CGRTAsmNE: |
12884 | 0 | case SystemZ::CGRTAsmNH: |
12885 | 0 | case SystemZ::CGRTAsmNHE: |
12886 | 0 | case SystemZ::CGRTAsmNL: |
12887 | 0 | case SystemZ::CGRTAsmNLE: |
12888 | 0 | case SystemZ::CGRTAsmNLH: |
12889 | 0 | case SystemZ::CHHR: |
12890 | 0 | case SystemZ::CHLR: |
12891 | 0 | case SystemZ::CKSM: |
12892 | 0 | case SystemZ::CLCL: |
12893 | 0 | case SystemZ::CLGFR: |
12894 | 0 | case SystemZ::CLGR: |
12895 | 0 | case SystemZ::CLGRTAsmE: |
12896 | 0 | case SystemZ::CLGRTAsmH: |
12897 | 0 | case SystemZ::CLGRTAsmHE: |
12898 | 0 | case SystemZ::CLGRTAsmL: |
12899 | 0 | case SystemZ::CLGRTAsmLE: |
12900 | 0 | case SystemZ::CLGRTAsmLH: |
12901 | 0 | case SystemZ::CLGRTAsmNE: |
12902 | 0 | case SystemZ::CLGRTAsmNH: |
12903 | 0 | case SystemZ::CLGRTAsmNHE: |
12904 | 0 | case SystemZ::CLGRTAsmNL: |
12905 | 0 | case SystemZ::CLGRTAsmNLE: |
12906 | 0 | case SystemZ::CLGRTAsmNLH: |
12907 | 0 | case SystemZ::CLHHR: |
12908 | 0 | case SystemZ::CLHLR: |
12909 | 0 | case SystemZ::CLR: |
12910 | 0 | case SystemZ::CLRTAsmE: |
12911 | 0 | case SystemZ::CLRTAsmH: |
12912 | 0 | case SystemZ::CLRTAsmHE: |
12913 | 0 | case SystemZ::CLRTAsmL: |
12914 | 0 | case SystemZ::CLRTAsmLE: |
12915 | 0 | case SystemZ::CLRTAsmLH: |
12916 | 0 | case SystemZ::CLRTAsmNE: |
12917 | 0 | case SystemZ::CLRTAsmNH: |
12918 | 0 | case SystemZ::CLRTAsmNHE: |
12919 | 0 | case SystemZ::CLRTAsmNL: |
12920 | 0 | case SystemZ::CLRTAsmNLE: |
12921 | 0 | case SystemZ::CLRTAsmNLH: |
12922 | 0 | case SystemZ::CLST: |
12923 | 0 | case SystemZ::CMPSC: |
12924 | 0 | case SystemZ::CPYA: |
12925 | 0 | case SystemZ::CR: |
12926 | 0 | case SystemZ::CRTAsmE: |
12927 | 0 | case SystemZ::CRTAsmH: |
12928 | 0 | case SystemZ::CRTAsmHE: |
12929 | 0 | case SystemZ::CRTAsmL: |
12930 | 0 | case SystemZ::CRTAsmLE: |
12931 | 0 | case SystemZ::CRTAsmLH: |
12932 | 0 | case SystemZ::CRTAsmNE: |
12933 | 0 | case SystemZ::CRTAsmNH: |
12934 | 0 | case SystemZ::CRTAsmNHE: |
12935 | 0 | case SystemZ::CRTAsmNL: |
12936 | 0 | case SystemZ::CRTAsmNLE: |
12937 | 0 | case SystemZ::CRTAsmNLH: |
12938 | 0 | case SystemZ::CU12Opt: |
12939 | 0 | case SystemZ::CU14Opt: |
12940 | 0 | case SystemZ::CU21Opt: |
12941 | 0 | case SystemZ::CU24Opt: |
12942 | 0 | case SystemZ::CU41: |
12943 | 0 | case SystemZ::CU42: |
12944 | 0 | case SystemZ::CUDTR: |
12945 | 0 | case SystemZ::CUSE: |
12946 | 0 | case SystemZ::CUTFUOpt: |
12947 | 0 | case SystemZ::CUUTFOpt: |
12948 | 0 | case SystemZ::CUXTR: |
12949 | 0 | case SystemZ::CXBR: |
12950 | 0 | case SystemZ::CXFBR: |
12951 | 0 | case SystemZ::CXFR: |
12952 | 0 | case SystemZ::CXGBR: |
12953 | 0 | case SystemZ::CXGR: |
12954 | 0 | case SystemZ::CXGTR: |
12955 | 0 | case SystemZ::CXR: |
12956 | 0 | case SystemZ::CXSTR: |
12957 | 0 | case SystemZ::CXTR: |
12958 | 0 | case SystemZ::CXUTR: |
12959 | 0 | case SystemZ::EAR: |
12960 | 0 | case SystemZ::ECCTR: |
12961 | 0 | case SystemZ::ECPGA: |
12962 | 0 | case SystemZ::EEDTR: |
12963 | 0 | case SystemZ::EEXTR: |
12964 | 0 | case SystemZ::EPCTR: |
12965 | 0 | case SystemZ::EPSW: |
12966 | 0 | case SystemZ::EREG: |
12967 | 0 | case SystemZ::EREGG: |
12968 | 0 | case SystemZ::ESDTR: |
12969 | 0 | case SystemZ::ESTA: |
12970 | 0 | case SystemZ::ESXTR: |
12971 | 0 | case SystemZ::FIDR: |
12972 | 0 | case SystemZ::FIER: |
12973 | 0 | case SystemZ::FIXR: |
12974 | 0 | case SystemZ::FLOGR: |
12975 | 0 | case SystemZ::HDR: |
12976 | 0 | case SystemZ::HER: |
12977 | 0 | case SystemZ::IPTEOptOpt: |
12978 | 0 | case SystemZ::IRBM: |
12979 | 0 | case SystemZ::KDBR: |
12980 | 0 | case SystemZ::KDTR: |
12981 | 0 | case SystemZ::KEBR: |
12982 | 0 | case SystemZ::KM: |
12983 | 0 | case SystemZ::KMC: |
12984 | 0 | case SystemZ::KMF: |
12985 | 0 | case SystemZ::KMO: |
12986 | 0 | case SystemZ::KXBR: |
12987 | 0 | case SystemZ::KXTR: |
12988 | 0 | case SystemZ::LBR: |
12989 | 0 | case SystemZ::LCDBR: |
12990 | 0 | case SystemZ::LCDFR: |
12991 | 0 | case SystemZ::LCDFR_32: |
12992 | 0 | case SystemZ::LCDR: |
12993 | 0 | case SystemZ::LCEBR: |
12994 | 0 | case SystemZ::LCER: |
12995 | 0 | case SystemZ::LCGFR: |
12996 | 0 | case SystemZ::LCGR: |
12997 | 0 | case SystemZ::LCR: |
12998 | 0 | case SystemZ::LCXBR: |
12999 | 0 | case SystemZ::LCXR: |
13000 | 0 | case SystemZ::LDEBR: |
13001 | 0 | case SystemZ::LDER: |
13002 | 0 | case SystemZ::LDGR: |
13003 | 0 | case SystemZ::LDR: |
13004 | 0 | case SystemZ::LDR32: |
13005 | 0 | case SystemZ::LDXBR: |
13006 | 0 | case SystemZ::LDXR: |
13007 | 0 | case SystemZ::LEDBR: |
13008 | 0 | case SystemZ::LEDR: |
13009 | 0 | case SystemZ::LER: |
13010 | 0 | case SystemZ::LEXBR: |
13011 | 0 | case SystemZ::LEXR: |
13012 | 0 | case SystemZ::LGBR: |
13013 | 0 | case SystemZ::LGDR: |
13014 | 0 | case SystemZ::LGFR: |
13015 | 0 | case SystemZ::LGHR: |
13016 | 0 | case SystemZ::LGR: |
13017 | 0 | case SystemZ::LHR: |
13018 | 0 | case SystemZ::LLCR: |
13019 | 0 | case SystemZ::LLGCR: |
13020 | 0 | case SystemZ::LLGFR: |
13021 | 0 | case SystemZ::LLGHR: |
13022 | 0 | case SystemZ::LLGTR: |
13023 | 0 | case SystemZ::LLHR: |
13024 | 0 | case SystemZ::LNDBR: |
13025 | 0 | case SystemZ::LNDFR: |
13026 | 0 | case SystemZ::LNDFR_32: |
13027 | 0 | case SystemZ::LNDR: |
13028 | 0 | case SystemZ::LNEBR: |
13029 | 0 | case SystemZ::LNER: |
13030 | 0 | case SystemZ::LNGFR: |
13031 | 0 | case SystemZ::LNGR: |
13032 | 0 | case SystemZ::LNR: |
13033 | 0 | case SystemZ::LNXBR: |
13034 | 0 | case SystemZ::LNXR: |
13035 | 0 | case SystemZ::LPDBR: |
13036 | 0 | case SystemZ::LPDFR: |
13037 | 0 | case SystemZ::LPDFR_32: |
13038 | 0 | case SystemZ::LPDR: |
13039 | 0 | case SystemZ::LPEBR: |
13040 | 0 | case SystemZ::LPER: |
13041 | 0 | case SystemZ::LPGFR: |
13042 | 0 | case SystemZ::LPGR: |
13043 | 0 | case SystemZ::LPR: |
13044 | 0 | case SystemZ::LPXBR: |
13045 | 0 | case SystemZ::LPXR: |
13046 | 0 | case SystemZ::LR: |
13047 | 0 | case SystemZ::LRDR: |
13048 | 0 | case SystemZ::LRER: |
13049 | 0 | case SystemZ::LRVGR: |
13050 | 0 | case SystemZ::LRVR: |
13051 | 0 | case SystemZ::LTDBR: |
13052 | 0 | case SystemZ::LTDR: |
13053 | 0 | case SystemZ::LTDTR: |
13054 | 0 | case SystemZ::LTEBR: |
13055 | 0 | case SystemZ::LTER: |
13056 | 0 | case SystemZ::LTGFR: |
13057 | 0 | case SystemZ::LTGR: |
13058 | 0 | case SystemZ::LTR: |
13059 | 0 | case SystemZ::LTXBR: |
13060 | 0 | case SystemZ::LTXR: |
13061 | 0 | case SystemZ::LTXTR: |
13062 | 0 | case SystemZ::LURA: |
13063 | 0 | case SystemZ::LURAG: |
13064 | 0 | case SystemZ::LXDBR: |
13065 | 0 | case SystemZ::LXDR: |
13066 | 0 | case SystemZ::LXEBR: |
13067 | 0 | case SystemZ::LXER: |
13068 | 0 | case SystemZ::LXR: |
13069 | 0 | case SystemZ::MVCL: |
13070 | 0 | case SystemZ::MVPG: |
13071 | 0 | case SystemZ::MVST: |
13072 | 0 | case SystemZ::PGIN: |
13073 | 0 | case SystemZ::PGOUT: |
13074 | 0 | case SystemZ::POPCNT: |
13075 | 0 | case SystemZ::PPNO: |
13076 | 0 | case SystemZ::PRNO: |
13077 | 0 | case SystemZ::PT: |
13078 | 0 | case SystemZ::PTI: |
13079 | 0 | case SystemZ::RRBE: |
13080 | 0 | case SystemZ::RRBM: |
13081 | 0 | case SystemZ::SAR: |
13082 | 0 | case SystemZ::SCCTR: |
13083 | 0 | case SystemZ::SORTL: |
13084 | 0 | case SystemZ::SPCTR: |
13085 | 0 | case SystemZ::SQDBR: |
13086 | 0 | case SystemZ::SQDR: |
13087 | 0 | case SystemZ::SQEBR: |
13088 | 0 | case SystemZ::SQER: |
13089 | 0 | case SystemZ::SQXBR: |
13090 | 0 | case SystemZ::SQXR: |
13091 | 0 | case SystemZ::SRST: |
13092 | 0 | case SystemZ::SRSTU: |
13093 | 0 | case SystemZ::SSKEOpt: |
13094 | 0 | case SystemZ::STURA: |
13095 | 0 | case SystemZ::STURG: |
13096 | 0 | case SystemZ::TAR: |
13097 | 0 | case SystemZ::TB: |
13098 | 0 | case SystemZ::THDER: |
13099 | 0 | case SystemZ::THDR: |
13100 | 0 | case SystemZ::TRE: |
13101 | 0 | case SystemZ::TROOOpt: |
13102 | 0 | case SystemZ::TROTOpt: |
13103 | 0 | case SystemZ::TRTOOpt: |
13104 | 0 | case SystemZ::TRTTOpt: { |
13105 | 0 | switch (OpNum) { |
13106 | 0 | case 0: |
13107 | | // op: R1 |
13108 | 0 | return 4; |
13109 | 0 | case 1: |
13110 | | // op: R2 |
13111 | 0 | return 0; |
13112 | 0 | } |
13113 | 0 | break; |
13114 | 0 | } |
13115 | 0 | case SystemZ::CDFBRA: |
13116 | 0 | case SystemZ::CDFTR: |
13117 | 0 | case SystemZ::CDGBRA: |
13118 | 0 | case SystemZ::CDGTRA: |
13119 | 0 | case SystemZ::CDLFBR: |
13120 | 0 | case SystemZ::CDLFTR: |
13121 | 0 | case SystemZ::CDLGBR: |
13122 | 0 | case SystemZ::CDLGTR: |
13123 | 0 | case SystemZ::CEFBRA: |
13124 | 0 | case SystemZ::CEGBRA: |
13125 | 0 | case SystemZ::CELFBR: |
13126 | 0 | case SystemZ::CELGBR: |
13127 | 0 | case SystemZ::CFDBRA: |
13128 | 0 | case SystemZ::CFDTR: |
13129 | 0 | case SystemZ::CFEBRA: |
13130 | 0 | case SystemZ::CFXBRA: |
13131 | 0 | case SystemZ::CFXTR: |
13132 | 0 | case SystemZ::CGDBRA: |
13133 | 0 | case SystemZ::CGDTRA: |
13134 | 0 | case SystemZ::CGEBRA: |
13135 | 0 | case SystemZ::CGXBRA: |
13136 | 0 | case SystemZ::CGXTRA: |
13137 | 0 | case SystemZ::CLFDBR: |
13138 | 0 | case SystemZ::CLFDTR: |
13139 | 0 | case SystemZ::CLFEBR: |
13140 | 0 | case SystemZ::CLFXBR: |
13141 | 0 | case SystemZ::CLFXTR: |
13142 | 0 | case SystemZ::CLGDBR: |
13143 | 0 | case SystemZ::CLGDTR: |
13144 | 0 | case SystemZ::CLGEBR: |
13145 | 0 | case SystemZ::CLGXBR: |
13146 | 0 | case SystemZ::CLGXTR: |
13147 | 0 | case SystemZ::CXFBRA: |
13148 | 0 | case SystemZ::CXFTR: |
13149 | 0 | case SystemZ::CXGBRA: |
13150 | 0 | case SystemZ::CXGTRA: |
13151 | 0 | case SystemZ::CXLFBR: |
13152 | 0 | case SystemZ::CXLFTR: |
13153 | 0 | case SystemZ::CXLGBR: |
13154 | 0 | case SystemZ::CXLGTR: |
13155 | 0 | case SystemZ::FIDBRA: |
13156 | 0 | case SystemZ::FIDTR: |
13157 | 0 | case SystemZ::FIEBRA: |
13158 | 0 | case SystemZ::FIXBRA: |
13159 | 0 | case SystemZ::FIXTR: |
13160 | 0 | case SystemZ::LDXBRA: |
13161 | 0 | case SystemZ::LDXTR: |
13162 | 0 | case SystemZ::LEDBRA: |
13163 | 0 | case SystemZ::LEDTR: |
13164 | 0 | case SystemZ::LEXBRA: { |
13165 | 0 | switch (OpNum) { |
13166 | 0 | case 0: |
13167 | | // op: R1 |
13168 | 0 | return 4; |
13169 | 0 | case 2: |
13170 | | // op: R2 |
13171 | 0 | return 0; |
13172 | 0 | case 1: |
13173 | | // op: M3 |
13174 | 0 | return 12; |
13175 | 0 | case 3: |
13176 | | // op: M4 |
13177 | 0 | return 8; |
13178 | 0 | } |
13179 | 0 | break; |
13180 | 0 | } |
13181 | 0 | case SystemZ::CFDBR: |
13182 | 0 | case SystemZ::CFDR: |
13183 | 0 | case SystemZ::CFEBR: |
13184 | 0 | case SystemZ::CFER: |
13185 | 0 | case SystemZ::CFXBR: |
13186 | 0 | case SystemZ::CFXR: |
13187 | 0 | case SystemZ::CGDBR: |
13188 | 0 | case SystemZ::CGDR: |
13189 | 0 | case SystemZ::CGDTR: |
13190 | 0 | case SystemZ::CGEBR: |
13191 | 0 | case SystemZ::CGER: |
13192 | 0 | case SystemZ::CGXBR: |
13193 | 0 | case SystemZ::CGXR: |
13194 | 0 | case SystemZ::CGXTR: |
13195 | 0 | case SystemZ::FIDBR: |
13196 | 0 | case SystemZ::FIEBR: |
13197 | 0 | case SystemZ::FIXBR: |
13198 | 0 | case SystemZ::TBDR: |
13199 | 0 | case SystemZ::TBEDR: { |
13200 | 0 | switch (OpNum) { |
13201 | 0 | case 0: |
13202 | | // op: R1 |
13203 | 0 | return 4; |
13204 | 0 | case 2: |
13205 | | // op: R2 |
13206 | 0 | return 0; |
13207 | 0 | case 1: |
13208 | | // op: M3 |
13209 | 0 | return 12; |
13210 | 0 | } |
13211 | 0 | break; |
13212 | 0 | } |
13213 | 0 | case SystemZ::SELFHRAsm: |
13214 | 0 | case SystemZ::SELGRAsm: |
13215 | 0 | case SystemZ::SELRAsm: { |
13216 | 0 | switch (OpNum) { |
13217 | 0 | case 0: |
13218 | | // op: R1 |
13219 | 0 | return 4; |
13220 | 0 | case 2: |
13221 | | // op: R2 |
13222 | 0 | return 0; |
13223 | 0 | case 1: |
13224 | | // op: R3 |
13225 | 0 | return 12; |
13226 | 0 | case 3: |
13227 | | // op: M4 |
13228 | 0 | return 8; |
13229 | 0 | } |
13230 | 0 | break; |
13231 | 0 | } |
13232 | 0 | case SystemZ::SELFHR: |
13233 | 0 | case SystemZ::SELGR: |
13234 | 0 | case SystemZ::SELR: { |
13235 | 0 | switch (OpNum) { |
13236 | 0 | case 0: |
13237 | | // op: R1 |
13238 | 0 | return 4; |
13239 | 0 | case 2: |
13240 | | // op: R2 |
13241 | 0 | return 0; |
13242 | 0 | case 1: |
13243 | | // op: R3 |
13244 | 0 | return 12; |
13245 | 0 | case 4: |
13246 | | // op: M4 |
13247 | 0 | return 8; |
13248 | 0 | } |
13249 | 0 | break; |
13250 | 0 | } |
13251 | 0 | case SystemZ::SELFHRAsmE: |
13252 | 0 | case SystemZ::SELFHRAsmH: |
13253 | 0 | case SystemZ::SELFHRAsmHE: |
13254 | 0 | case SystemZ::SELFHRAsmL: |
13255 | 0 | case SystemZ::SELFHRAsmLE: |
13256 | 0 | case SystemZ::SELFHRAsmLH: |
13257 | 0 | case SystemZ::SELFHRAsmM: |
13258 | 0 | case SystemZ::SELFHRAsmNE: |
13259 | 0 | case SystemZ::SELFHRAsmNH: |
13260 | 0 | case SystemZ::SELFHRAsmNHE: |
13261 | 0 | case SystemZ::SELFHRAsmNL: |
13262 | 0 | case SystemZ::SELFHRAsmNLE: |
13263 | 0 | case SystemZ::SELFHRAsmNLH: |
13264 | 0 | case SystemZ::SELFHRAsmNM: |
13265 | 0 | case SystemZ::SELFHRAsmNO: |
13266 | 0 | case SystemZ::SELFHRAsmNP: |
13267 | 0 | case SystemZ::SELFHRAsmNZ: |
13268 | 0 | case SystemZ::SELFHRAsmO: |
13269 | 0 | case SystemZ::SELFHRAsmP: |
13270 | 0 | case SystemZ::SELFHRAsmZ: |
13271 | 0 | case SystemZ::SELGRAsmE: |
13272 | 0 | case SystemZ::SELGRAsmH: |
13273 | 0 | case SystemZ::SELGRAsmHE: |
13274 | 0 | case SystemZ::SELGRAsmL: |
13275 | 0 | case SystemZ::SELGRAsmLE: |
13276 | 0 | case SystemZ::SELGRAsmLH: |
13277 | 0 | case SystemZ::SELGRAsmM: |
13278 | 0 | case SystemZ::SELGRAsmNE: |
13279 | 0 | case SystemZ::SELGRAsmNH: |
13280 | 0 | case SystemZ::SELGRAsmNHE: |
13281 | 0 | case SystemZ::SELGRAsmNL: |
13282 | 0 | case SystemZ::SELGRAsmNLE: |
13283 | 0 | case SystemZ::SELGRAsmNLH: |
13284 | 0 | case SystemZ::SELGRAsmNM: |
13285 | 0 | case SystemZ::SELGRAsmNO: |
13286 | 0 | case SystemZ::SELGRAsmNP: |
13287 | 0 | case SystemZ::SELGRAsmNZ: |
13288 | 0 | case SystemZ::SELGRAsmO: |
13289 | 0 | case SystemZ::SELGRAsmP: |
13290 | 0 | case SystemZ::SELGRAsmZ: |
13291 | 0 | case SystemZ::SELRAsmE: |
13292 | 0 | case SystemZ::SELRAsmH: |
13293 | 0 | case SystemZ::SELRAsmHE: |
13294 | 0 | case SystemZ::SELRAsmL: |
13295 | 0 | case SystemZ::SELRAsmLE: |
13296 | 0 | case SystemZ::SELRAsmLH: |
13297 | 0 | case SystemZ::SELRAsmM: |
13298 | 0 | case SystemZ::SELRAsmNE: |
13299 | 0 | case SystemZ::SELRAsmNH: |
13300 | 0 | case SystemZ::SELRAsmNHE: |
13301 | 0 | case SystemZ::SELRAsmNL: |
13302 | 0 | case SystemZ::SELRAsmNLE: |
13303 | 0 | case SystemZ::SELRAsmNLH: |
13304 | 0 | case SystemZ::SELRAsmNM: |
13305 | 0 | case SystemZ::SELRAsmNO: |
13306 | 0 | case SystemZ::SELRAsmNP: |
13307 | 0 | case SystemZ::SELRAsmNZ: |
13308 | 0 | case SystemZ::SELRAsmO: |
13309 | 0 | case SystemZ::SELRAsmP: |
13310 | 0 | case SystemZ::SELRAsmZ: { |
13311 | 0 | switch (OpNum) { |
13312 | 0 | case 0: |
13313 | | // op: R1 |
13314 | 0 | return 4; |
13315 | 0 | case 2: |
13316 | | // op: R2 |
13317 | 0 | return 0; |
13318 | 0 | case 1: |
13319 | | // op: R3 |
13320 | 0 | return 12; |
13321 | 0 | } |
13322 | 0 | break; |
13323 | 0 | } |
13324 | 0 | case SystemZ::LOCFHRAsm: |
13325 | 0 | case SystemZ::LOCGRAsm: |
13326 | 0 | case SystemZ::LOCRAsm: { |
13327 | 0 | switch (OpNum) { |
13328 | 0 | case 0: |
13329 | | // op: R1 |
13330 | 0 | return 4; |
13331 | 0 | case 2: |
13332 | | // op: R2 |
13333 | 0 | return 0; |
13334 | 0 | case 3: |
13335 | | // op: M3 |
13336 | 0 | return 12; |
13337 | 0 | } |
13338 | 0 | break; |
13339 | 0 | } |
13340 | 0 | case SystemZ::LOCFHR: |
13341 | 0 | case SystemZ::LOCGR: |
13342 | 0 | case SystemZ::LOCR: { |
13343 | 0 | switch (OpNum) { |
13344 | 0 | case 0: |
13345 | | // op: R1 |
13346 | 0 | return 4; |
13347 | 0 | case 2: |
13348 | | // op: R2 |
13349 | 0 | return 0; |
13350 | 0 | case 4: |
13351 | | // op: M3 |
13352 | 0 | return 12; |
13353 | 0 | } |
13354 | 0 | break; |
13355 | 0 | } |
13356 | 0 | case SystemZ::ADBR: |
13357 | 0 | case SystemZ::ADR: |
13358 | 0 | case SystemZ::AEBR: |
13359 | 0 | case SystemZ::AER: |
13360 | 0 | case SystemZ::AGFR: |
13361 | 0 | case SystemZ::AGR: |
13362 | 0 | case SystemZ::ALCGR: |
13363 | 0 | case SystemZ::ALCR: |
13364 | 0 | case SystemZ::ALGFR: |
13365 | 0 | case SystemZ::ALGR: |
13366 | 0 | case SystemZ::ALR: |
13367 | 0 | case SystemZ::AR: |
13368 | 0 | case SystemZ::AUR: |
13369 | 0 | case SystemZ::AWR: |
13370 | 0 | case SystemZ::AXBR: |
13371 | 0 | case SystemZ::AXR: |
13372 | 0 | case SystemZ::BCTGR: |
13373 | 0 | case SystemZ::BCTR: |
13374 | 0 | case SystemZ::CSP: |
13375 | 0 | case SystemZ::CSPG: |
13376 | 0 | case SystemZ::DDBR: |
13377 | 0 | case SystemZ::DDR: |
13378 | 0 | case SystemZ::DEBR: |
13379 | 0 | case SystemZ::DER: |
13380 | 0 | case SystemZ::DLGR: |
13381 | 0 | case SystemZ::DLR: |
13382 | 0 | case SystemZ::DR: |
13383 | 0 | case SystemZ::DSGFR: |
13384 | 0 | case SystemZ::DSGR: |
13385 | 0 | case SystemZ::DXBR: |
13386 | 0 | case SystemZ::DXR: |
13387 | 0 | case SystemZ::ISKE: |
13388 | 0 | case SystemZ::IVSK: |
13389 | 0 | case SystemZ::LOCFHRAsmE: |
13390 | 0 | case SystemZ::LOCFHRAsmH: |
13391 | 0 | case SystemZ::LOCFHRAsmHE: |
13392 | 0 | case SystemZ::LOCFHRAsmL: |
13393 | 0 | case SystemZ::LOCFHRAsmLE: |
13394 | 0 | case SystemZ::LOCFHRAsmLH: |
13395 | 0 | case SystemZ::LOCFHRAsmM: |
13396 | 0 | case SystemZ::LOCFHRAsmNE: |
13397 | 0 | case SystemZ::LOCFHRAsmNH: |
13398 | 0 | case SystemZ::LOCFHRAsmNHE: |
13399 | 0 | case SystemZ::LOCFHRAsmNL: |
13400 | 0 | case SystemZ::LOCFHRAsmNLE: |
13401 | 0 | case SystemZ::LOCFHRAsmNLH: |
13402 | 0 | case SystemZ::LOCFHRAsmNM: |
13403 | 0 | case SystemZ::LOCFHRAsmNO: |
13404 | 0 | case SystemZ::LOCFHRAsmNP: |
13405 | 0 | case SystemZ::LOCFHRAsmNZ: |
13406 | 0 | case SystemZ::LOCFHRAsmO: |
13407 | 0 | case SystemZ::LOCFHRAsmP: |
13408 | 0 | case SystemZ::LOCFHRAsmZ: |
13409 | 0 | case SystemZ::LOCGRAsmE: |
13410 | 0 | case SystemZ::LOCGRAsmH: |
13411 | 0 | case SystemZ::LOCGRAsmHE: |
13412 | 0 | case SystemZ::LOCGRAsmL: |
13413 | 0 | case SystemZ::LOCGRAsmLE: |
13414 | 0 | case SystemZ::LOCGRAsmLH: |
13415 | 0 | case SystemZ::LOCGRAsmM: |
13416 | 0 | case SystemZ::LOCGRAsmNE: |
13417 | 0 | case SystemZ::LOCGRAsmNH: |
13418 | 0 | case SystemZ::LOCGRAsmNHE: |
13419 | 0 | case SystemZ::LOCGRAsmNL: |
13420 | 0 | case SystemZ::LOCGRAsmNLE: |
13421 | 0 | case SystemZ::LOCGRAsmNLH: |
13422 | 0 | case SystemZ::LOCGRAsmNM: |
13423 | 0 | case SystemZ::LOCGRAsmNO: |
13424 | 0 | case SystemZ::LOCGRAsmNP: |
13425 | 0 | case SystemZ::LOCGRAsmNZ: |
13426 | 0 | case SystemZ::LOCGRAsmO: |
13427 | 0 | case SystemZ::LOCGRAsmP: |
13428 | 0 | case SystemZ::LOCGRAsmZ: |
13429 | 0 | case SystemZ::LOCRAsmE: |
13430 | 0 | case SystemZ::LOCRAsmH: |
13431 | 0 | case SystemZ::LOCRAsmHE: |
13432 | 0 | case SystemZ::LOCRAsmL: |
13433 | 0 | case SystemZ::LOCRAsmLE: |
13434 | 0 | case SystemZ::LOCRAsmLH: |
13435 | 0 | case SystemZ::LOCRAsmM: |
13436 | 0 | case SystemZ::LOCRAsmNE: |
13437 | 0 | case SystemZ::LOCRAsmNH: |
13438 | 0 | case SystemZ::LOCRAsmNHE: |
13439 | 0 | case SystemZ::LOCRAsmNL: |
13440 | 0 | case SystemZ::LOCRAsmNLE: |
13441 | 0 | case SystemZ::LOCRAsmNLH: |
13442 | 0 | case SystemZ::LOCRAsmNM: |
13443 | 0 | case SystemZ::LOCRAsmNO: |
13444 | 0 | case SystemZ::LOCRAsmNP: |
13445 | 0 | case SystemZ::LOCRAsmNZ: |
13446 | 0 | case SystemZ::LOCRAsmO: |
13447 | 0 | case SystemZ::LOCRAsmP: |
13448 | 0 | case SystemZ::LOCRAsmZ: |
13449 | 0 | case SystemZ::MDBR: |
13450 | 0 | case SystemZ::MDEBR: |
13451 | 0 | case SystemZ::MDER: |
13452 | 0 | case SystemZ::MDR: |
13453 | 0 | case SystemZ::MEEBR: |
13454 | 0 | case SystemZ::MEER: |
13455 | 0 | case SystemZ::MER: |
13456 | 0 | case SystemZ::MLGR: |
13457 | 0 | case SystemZ::MLR: |
13458 | 0 | case SystemZ::MR: |
13459 | 0 | case SystemZ::MSGFR: |
13460 | 0 | case SystemZ::MSGR: |
13461 | 0 | case SystemZ::MSR: |
13462 | 0 | case SystemZ::MXBR: |
13463 | 0 | case SystemZ::MXDBR: |
13464 | 0 | case SystemZ::MXDR: |
13465 | 0 | case SystemZ::MXR: |
13466 | 0 | case SystemZ::NGR: |
13467 | 0 | case SystemZ::NR: |
13468 | 0 | case SystemZ::OGR: |
13469 | 0 | case SystemZ::OR: |
13470 | 0 | case SystemZ::SDBR: |
13471 | 0 | case SystemZ::SDR: |
13472 | 0 | case SystemZ::SEBR: |
13473 | 0 | case SystemZ::SER: |
13474 | 0 | case SystemZ::SGFR: |
13475 | 0 | case SystemZ::SGR: |
13476 | 0 | case SystemZ::SLBGR: |
13477 | 0 | case SystemZ::SLBR: |
13478 | 0 | case SystemZ::SLGFR: |
13479 | 0 | case SystemZ::SLGR: |
13480 | 0 | case SystemZ::SLR: |
13481 | 0 | case SystemZ::SR: |
13482 | 0 | case SystemZ::SUR: |
13483 | 0 | case SystemZ::SWR: |
13484 | 0 | case SystemZ::SXBR: |
13485 | 0 | case SystemZ::SXR: |
13486 | 0 | case SystemZ::XGR: |
13487 | 0 | case SystemZ::XR: { |
13488 | 0 | switch (OpNum) { |
13489 | 0 | case 0: |
13490 | | // op: R1 |
13491 | 0 | return 4; |
13492 | 0 | case 2: |
13493 | | // op: R2 |
13494 | 0 | return 0; |
13495 | 0 | } |
13496 | 0 | break; |
13497 | 0 | } |
13498 | 0 | case SystemZ::DIDBR: |
13499 | 0 | case SystemZ::DIEBR: |
13500 | 0 | case SystemZ::LPTEA: |
13501 | 0 | case SystemZ::QADTR: |
13502 | 0 | case SystemZ::QAXTR: |
13503 | 0 | case SystemZ::RRDTR: |
13504 | 0 | case SystemZ::RRXTR: { |
13505 | 0 | switch (OpNum) { |
13506 | 0 | case 0: |
13507 | | // op: R1 |
13508 | 0 | return 4; |
13509 | 0 | case 3: |
13510 | | // op: R2 |
13511 | 0 | return 0; |
13512 | 0 | case 1: |
13513 | | // op: R3 |
13514 | 0 | return 12; |
13515 | 0 | case 4: |
13516 | | // op: M4 |
13517 | 0 | return 8; |
13518 | 0 | } |
13519 | 0 | break; |
13520 | 0 | } |
13521 | 0 | case SystemZ::EFPC: |
13522 | 0 | case SystemZ::EPAIR: |
13523 | 0 | case SystemZ::EPAR: |
13524 | 0 | case SystemZ::ESAIR: |
13525 | 0 | case SystemZ::ESAR: |
13526 | 0 | case SystemZ::ESEA: |
13527 | 0 | case SystemZ::ETND: |
13528 | 0 | case SystemZ::IAC: |
13529 | 0 | case SystemZ::IPM: |
13530 | 0 | case SystemZ::LZDR: |
13531 | 0 | case SystemZ::LZER: |
13532 | 0 | case SystemZ::LZXR: |
13533 | 0 | case SystemZ::MSTA: |
13534 | 0 | case SystemZ::PTF: |
13535 | 0 | case SystemZ::SFASR: |
13536 | 0 | case SystemZ::SFPC: |
13537 | 0 | case SystemZ::SPM: |
13538 | 0 | case SystemZ::SSAIR: |
13539 | 0 | case SystemZ::SSAR: { |
13540 | 0 | switch (OpNum) { |
13541 | 0 | case 0: |
13542 | | // op: R1 |
13543 | 0 | return 4; |
13544 | 0 | } |
13545 | 0 | break; |
13546 | 0 | } |
13547 | 0 | case SystemZ::BR: |
13548 | 0 | case SystemZ::BRAsmE: |
13549 | 0 | case SystemZ::BRAsmH: |
13550 | 0 | case SystemZ::BRAsmHE: |
13551 | 0 | case SystemZ::BRAsmL: |
13552 | 0 | case SystemZ::BRAsmLE: |
13553 | 0 | case SystemZ::BRAsmLH: |
13554 | 0 | case SystemZ::BRAsmM: |
13555 | 0 | case SystemZ::BRAsmNE: |
13556 | 0 | case SystemZ::BRAsmNH: |
13557 | 0 | case SystemZ::BRAsmNHE: |
13558 | 0 | case SystemZ::BRAsmNL: |
13559 | 0 | case SystemZ::BRAsmNLE: |
13560 | 0 | case SystemZ::BRAsmNLH: |
13561 | 0 | case SystemZ::BRAsmNM: |
13562 | 0 | case SystemZ::BRAsmNO: |
13563 | 0 | case SystemZ::BRAsmNP: |
13564 | 0 | case SystemZ::BRAsmNZ: |
13565 | 0 | case SystemZ::BRAsmO: |
13566 | 0 | case SystemZ::BRAsmP: |
13567 | 0 | case SystemZ::BRAsmZ: { |
13568 | 0 | switch (OpNum) { |
13569 | 0 | case 0: |
13570 | | // op: R2 |
13571 | 0 | return 0; |
13572 | 0 | } |
13573 | 0 | break; |
13574 | 0 | } |
13575 | 0 | case SystemZ::J: |
13576 | 0 | case SystemZ::JAsmE: |
13577 | 0 | case SystemZ::JAsmH: |
13578 | 0 | case SystemZ::JAsmHE: |
13579 | 0 | case SystemZ::JAsmL: |
13580 | 0 | case SystemZ::JAsmLE: |
13581 | 0 | case SystemZ::JAsmLH: |
13582 | 0 | case SystemZ::JAsmM: |
13583 | 0 | case SystemZ::JAsmNE: |
13584 | 0 | case SystemZ::JAsmNH: |
13585 | 0 | case SystemZ::JAsmNHE: |
13586 | 0 | case SystemZ::JAsmNL: |
13587 | 0 | case SystemZ::JAsmNLE: |
13588 | 0 | case SystemZ::JAsmNLH: |
13589 | 0 | case SystemZ::JAsmNM: |
13590 | 0 | case SystemZ::JAsmNO: |
13591 | 0 | case SystemZ::JAsmNP: |
13592 | 0 | case SystemZ::JAsmNZ: |
13593 | 0 | case SystemZ::JAsmO: |
13594 | 0 | case SystemZ::JAsmP: |
13595 | 0 | case SystemZ::JAsmZ: |
13596 | 0 | case SystemZ::JG: |
13597 | 0 | case SystemZ::JGAsmE: |
13598 | 0 | case SystemZ::JGAsmH: |
13599 | 0 | case SystemZ::JGAsmHE: |
13600 | 0 | case SystemZ::JGAsmL: |
13601 | 0 | case SystemZ::JGAsmLE: |
13602 | 0 | case SystemZ::JGAsmLH: |
13603 | 0 | case SystemZ::JGAsmM: |
13604 | 0 | case SystemZ::JGAsmNE: |
13605 | 0 | case SystemZ::JGAsmNH: |
13606 | 0 | case SystemZ::JGAsmNHE: |
13607 | 0 | case SystemZ::JGAsmNL: |
13608 | 0 | case SystemZ::JGAsmNLE: |
13609 | 0 | case SystemZ::JGAsmNLH: |
13610 | 0 | case SystemZ::JGAsmNM: |
13611 | 0 | case SystemZ::JGAsmNO: |
13612 | 0 | case SystemZ::JGAsmNP: |
13613 | 0 | case SystemZ::JGAsmNZ: |
13614 | 0 | case SystemZ::JGAsmO: |
13615 | 0 | case SystemZ::JGAsmP: |
13616 | 0 | case SystemZ::JGAsmZ: { |
13617 | 0 | switch (OpNum) { |
13618 | 0 | case 0: |
13619 | | // op: RI2 |
13620 | 0 | return 0; |
13621 | 0 | } |
13622 | 0 | break; |
13623 | 0 | } |
13624 | 0 | case SystemZ::VCP: { |
13625 | 0 | switch (OpNum) { |
13626 | 0 | case 0: |
13627 | | // op: V1 |
13628 | 0 | return 10; |
13629 | 0 | case 1: |
13630 | | // op: V2 |
13631 | 0 | return 9; |
13632 | 0 | case 2: |
13633 | | // op: M3 |
13634 | 0 | return 20; |
13635 | 0 | } |
13636 | 0 | break; |
13637 | 0 | } |
13638 | 0 | case SystemZ::VTP: { |
13639 | 0 | switch (OpNum) { |
13640 | 0 | case 0: |
13641 | | // op: V1 |
13642 | 0 | return 10; |
13643 | 0 | } |
13644 | 0 | break; |
13645 | 0 | } |
13646 | 0 | case SystemZ::VLIP: { |
13647 | 0 | switch (OpNum) { |
13648 | 0 | case 0: |
13649 | | // op: V1 |
13650 | 0 | return 11; |
13651 | 0 | case 1: |
13652 | | // op: I2 |
13653 | 0 | return 16; |
13654 | 0 | case 2: |
13655 | | // op: I3 |
13656 | 0 | return 12; |
13657 | 0 | } |
13658 | 0 | break; |
13659 | 0 | } |
13660 | 0 | case SystemZ::VREPI: { |
13661 | 0 | switch (OpNum) { |
13662 | 0 | case 0: |
13663 | | // op: V1 |
13664 | 0 | return 11; |
13665 | 0 | case 1: |
13666 | | // op: I2 |
13667 | 0 | return 16; |
13668 | 0 | case 2: |
13669 | | // op: M3 |
13670 | 0 | return 12; |
13671 | 0 | } |
13672 | 0 | break; |
13673 | 0 | } |
13674 | 0 | case SystemZ::VGBM: |
13675 | 0 | case SystemZ::VREPIB: |
13676 | 0 | case SystemZ::VREPIF: |
13677 | 0 | case SystemZ::VREPIG: |
13678 | 0 | case SystemZ::VREPIH: { |
13679 | 0 | switch (OpNum) { |
13680 | 0 | case 0: |
13681 | | // op: V1 |
13682 | 0 | return 11; |
13683 | 0 | case 1: |
13684 | | // op: I2 |
13685 | 0 | return 16; |
13686 | 0 | } |
13687 | 0 | break; |
13688 | 0 | } |
13689 | 0 | case SystemZ::VGM: { |
13690 | 0 | switch (OpNum) { |
13691 | 0 | case 0: |
13692 | | // op: V1 |
13693 | 0 | return 11; |
13694 | 0 | case 1: |
13695 | | // op: I2 |
13696 | 0 | return 24; |
13697 | 0 | case 2: |
13698 | | // op: I3 |
13699 | 0 | return 16; |
13700 | 0 | case 3: |
13701 | | // op: M4 |
13702 | 0 | return 12; |
13703 | 0 | } |
13704 | 0 | break; |
13705 | 0 | } |
13706 | 0 | case SystemZ::VGMB: |
13707 | 0 | case SystemZ::VGMF: |
13708 | 0 | case SystemZ::VGMG: |
13709 | 0 | case SystemZ::VGMH: { |
13710 | 0 | switch (OpNum) { |
13711 | 0 | case 0: |
13712 | | // op: V1 |
13713 | 0 | return 11; |
13714 | 0 | case 1: |
13715 | | // op: I2 |
13716 | 0 | return 24; |
13717 | 0 | case 2: |
13718 | | // op: I3 |
13719 | 0 | return 16; |
13720 | 0 | } |
13721 | 0 | break; |
13722 | 0 | } |
13723 | 0 | case SystemZ::VCVD: |
13724 | 0 | case SystemZ::VCVDG: { |
13725 | 0 | switch (OpNum) { |
13726 | 0 | case 0: |
13727 | | // op: V1 |
13728 | 0 | return 11; |
13729 | 0 | case 1: |
13730 | | // op: R2 |
13731 | 0 | return 32; |
13732 | 0 | case 2: |
13733 | | // op: I3 |
13734 | 0 | return 12; |
13735 | 0 | case 3: |
13736 | | // op: M4 |
13737 | 0 | return 20; |
13738 | 0 | } |
13739 | 0 | break; |
13740 | 0 | } |
13741 | 0 | case SystemZ::VLVGP: { |
13742 | 0 | switch (OpNum) { |
13743 | 0 | case 0: |
13744 | | // op: V1 |
13745 | 0 | return 11; |
13746 | 0 | case 1: |
13747 | | // op: R2 |
13748 | 0 | return 32; |
13749 | 0 | case 2: |
13750 | | // op: R3 |
13751 | 0 | return 28; |
13752 | 0 | } |
13753 | 0 | break; |
13754 | 0 | } |
13755 | 0 | case SystemZ::VPSOP: |
13756 | 0 | case SystemZ::VSRP: { |
13757 | 0 | switch (OpNum) { |
13758 | 0 | case 0: |
13759 | | // op: V1 |
13760 | 0 | return 11; |
13761 | 0 | case 1: |
13762 | | // op: V2 |
13763 | 0 | return 10; |
13764 | 0 | case 2: |
13765 | | // op: I3 |
13766 | 0 | return 12; |
13767 | 0 | case 3: |
13768 | | // op: I4 |
13769 | 0 | return 24; |
13770 | 0 | case 4: |
13771 | | // op: M5 |
13772 | 0 | return 20; |
13773 | 0 | } |
13774 | 0 | break; |
13775 | 0 | } |
13776 | 0 | case SystemZ::VFTCI: { |
13777 | 0 | switch (OpNum) { |
13778 | 0 | case 0: |
13779 | | // op: V1 |
13780 | 0 | return 11; |
13781 | 0 | case 1: |
13782 | | // op: V2 |
13783 | 0 | return 10; |
13784 | 0 | case 2: |
13785 | | // op: I3 |
13786 | 0 | return 20; |
13787 | 0 | case 3: |
13788 | | // op: M4 |
13789 | 0 | return 12; |
13790 | 0 | case 4: |
13791 | | // op: M5 |
13792 | 0 | return 16; |
13793 | 0 | } |
13794 | 0 | break; |
13795 | 0 | } |
13796 | 0 | case SystemZ::VFTCIDB: |
13797 | 0 | case SystemZ::VFTCISB: |
13798 | 0 | case SystemZ::WFTCIDB: |
13799 | 0 | case SystemZ::WFTCISB: |
13800 | 0 | case SystemZ::WFTCIXB: { |
13801 | 0 | switch (OpNum) { |
13802 | 0 | case 0: |
13803 | | // op: V1 |
13804 | 0 | return 11; |
13805 | 0 | case 1: |
13806 | | // op: V2 |
13807 | 0 | return 10; |
13808 | 0 | case 2: |
13809 | | // op: I3 |
13810 | 0 | return 20; |
13811 | 0 | } |
13812 | 0 | break; |
13813 | 0 | } |
13814 | 0 | case SystemZ::VCDG: |
13815 | 0 | case SystemZ::VCDLG: |
13816 | 0 | case SystemZ::VCFPL: |
13817 | 0 | case SystemZ::VCFPS: |
13818 | 0 | case SystemZ::VCGD: |
13819 | 0 | case SystemZ::VCLFP: |
13820 | 0 | case SystemZ::VCLGD: |
13821 | 0 | case SystemZ::VCSFP: |
13822 | 0 | case SystemZ::VFI: |
13823 | 0 | case SystemZ::VFLR: |
13824 | 0 | case SystemZ::VFPSO: |
13825 | 0 | case SystemZ::VLED: { |
13826 | 0 | switch (OpNum) { |
13827 | 0 | case 0: |
13828 | | // op: V1 |
13829 | 0 | return 11; |
13830 | 0 | case 1: |
13831 | | // op: V2 |
13832 | 0 | return 10; |
13833 | 0 | case 2: |
13834 | | // op: M3 |
13835 | 0 | return 12; |
13836 | 0 | case 3: |
13837 | | // op: M4 |
13838 | 0 | return 16; |
13839 | 0 | case 4: |
13840 | | // op: M5 |
13841 | 0 | return 20; |
13842 | 0 | } |
13843 | 0 | break; |
13844 | 0 | } |
13845 | 0 | case SystemZ::VCFN: |
13846 | 0 | case SystemZ::VCLFNH: |
13847 | 0 | case SystemZ::VCLFNL: |
13848 | 0 | case SystemZ::VCNF: |
13849 | 0 | case SystemZ::VFLL: |
13850 | 0 | case SystemZ::VFSQ: |
13851 | 0 | case SystemZ::VLDE: |
13852 | 0 | case SystemZ::WFC: |
13853 | 0 | case SystemZ::WFK: { |
13854 | 0 | switch (OpNum) { |
13855 | 0 | case 0: |
13856 | | // op: V1 |
13857 | 0 | return 11; |
13858 | 0 | case 1: |
13859 | | // op: V2 |
13860 | 0 | return 10; |
13861 | 0 | case 2: |
13862 | | // op: M3 |
13863 | 0 | return 12; |
13864 | 0 | case 3: |
13865 | | // op: M4 |
13866 | 0 | return 16; |
13867 | 0 | } |
13868 | 0 | break; |
13869 | 0 | } |
13870 | 0 | case SystemZ::VISTR: { |
13871 | 0 | switch (OpNum) { |
13872 | 0 | case 0: |
13873 | | // op: V1 |
13874 | 0 | return 11; |
13875 | 0 | case 1: |
13876 | | // op: V2 |
13877 | 0 | return 10; |
13878 | 0 | case 2: |
13879 | | // op: M3 |
13880 | 0 | return 12; |
13881 | 0 | case 3: |
13882 | | // op: M5 |
13883 | 0 | return 20; |
13884 | 0 | } |
13885 | 0 | break; |
13886 | 0 | } |
13887 | 0 | case SystemZ::VCLZ: |
13888 | 0 | case SystemZ::VCTZ: |
13889 | 0 | case SystemZ::VEC: |
13890 | 0 | case SystemZ::VECL: |
13891 | 0 | case SystemZ::VLC: |
13892 | 0 | case SystemZ::VLP: |
13893 | 0 | case SystemZ::VPOPCT: |
13894 | 0 | case SystemZ::VSEG: |
13895 | 0 | case SystemZ::VUPH: |
13896 | 0 | case SystemZ::VUPL: |
13897 | 0 | case SystemZ::VUPLH: |
13898 | 0 | case SystemZ::VUPLL: { |
13899 | 0 | switch (OpNum) { |
13900 | 0 | case 0: |
13901 | | // op: V1 |
13902 | 0 | return 11; |
13903 | 0 | case 1: |
13904 | | // op: V2 |
13905 | 0 | return 10; |
13906 | 0 | case 2: |
13907 | | // op: M3 |
13908 | 0 | return 12; |
13909 | 0 | } |
13910 | 0 | break; |
13911 | 0 | } |
13912 | 0 | case SystemZ::VCLZDP: |
13913 | 0 | case SystemZ::VUPKZH: |
13914 | 0 | case SystemZ::VUPKZL: { |
13915 | 0 | switch (OpNum) { |
13916 | 0 | case 0: |
13917 | | // op: V1 |
13918 | 0 | return 11; |
13919 | 0 | case 1: |
13920 | | // op: V2 |
13921 | 0 | return 10; |
13922 | 0 | case 2: |
13923 | | // op: M3 |
13924 | 0 | return 20; |
13925 | 0 | } |
13926 | 0 | break; |
13927 | 0 | } |
13928 | 0 | case SystemZ::VCDGB: |
13929 | 0 | case SystemZ::VCDLGB: |
13930 | 0 | case SystemZ::VCEFB: |
13931 | 0 | case SystemZ::VCELFB: |
13932 | 0 | case SystemZ::VCFEB: |
13933 | 0 | case SystemZ::VCGDB: |
13934 | 0 | case SystemZ::VCLFEB: |
13935 | 0 | case SystemZ::VCLGDB: |
13936 | 0 | case SystemZ::VFIDB: |
13937 | 0 | case SystemZ::VFISB: |
13938 | 0 | case SystemZ::VFLRD: |
13939 | 0 | case SystemZ::VLEDB: |
13940 | 0 | case SystemZ::WCDGB: |
13941 | 0 | case SystemZ::WCDLGB: |
13942 | 0 | case SystemZ::WCEFB: |
13943 | 0 | case SystemZ::WCELFB: |
13944 | 0 | case SystemZ::WCFEB: |
13945 | 0 | case SystemZ::WCGDB: |
13946 | 0 | case SystemZ::WCLFEB: |
13947 | 0 | case SystemZ::WCLGDB: |
13948 | 0 | case SystemZ::WFIDB: |
13949 | 0 | case SystemZ::WFISB: |
13950 | 0 | case SystemZ::WFIXB: |
13951 | 0 | case SystemZ::WFLRD: |
13952 | 0 | case SystemZ::WFLRX: |
13953 | 0 | case SystemZ::WLEDB: { |
13954 | 0 | switch (OpNum) { |
13955 | 0 | case 0: |
13956 | | // op: V1 |
13957 | 0 | return 11; |
13958 | 0 | case 1: |
13959 | | // op: V2 |
13960 | 0 | return 10; |
13961 | 0 | case 2: |
13962 | | // op: M4 |
13963 | 0 | return 16; |
13964 | 0 | case 3: |
13965 | | // op: M5 |
13966 | 0 | return 20; |
13967 | 0 | } |
13968 | 0 | break; |
13969 | 0 | } |
13970 | 0 | case SystemZ::VFPSODB: |
13971 | 0 | case SystemZ::VFPSOSB: |
13972 | 0 | case SystemZ::VISTRB: |
13973 | 0 | case SystemZ::VISTRF: |
13974 | 0 | case SystemZ::VISTRH: |
13975 | 0 | case SystemZ::WFPSODB: |
13976 | 0 | case SystemZ::WFPSOSB: |
13977 | 0 | case SystemZ::WFPSOXB: { |
13978 | 0 | switch (OpNum) { |
13979 | 0 | case 0: |
13980 | | // op: V1 |
13981 | 0 | return 11; |
13982 | 0 | case 1: |
13983 | | // op: V2 |
13984 | 0 | return 10; |
13985 | 0 | case 2: |
13986 | | // op: M5 |
13987 | 0 | return 20; |
13988 | 0 | } |
13989 | 0 | break; |
13990 | 0 | } |
13991 | 0 | case SystemZ::VAP: |
13992 | 0 | case SystemZ::VDP: |
13993 | 0 | case SystemZ::VMP: |
13994 | 0 | case SystemZ::VMSP: |
13995 | 0 | case SystemZ::VPKZR: |
13996 | 0 | case SystemZ::VRP: |
13997 | 0 | case SystemZ::VSDP: |
13998 | 0 | case SystemZ::VSP: |
13999 | 0 | case SystemZ::VSRPR: { |
14000 | 0 | switch (OpNum) { |
14001 | 0 | case 0: |
14002 | | // op: V1 |
14003 | 0 | return 11; |
14004 | 0 | case 1: |
14005 | | // op: V2 |
14006 | 0 | return 10; |
14007 | 0 | case 2: |
14008 | | // op: V3 |
14009 | 0 | return 9; |
14010 | 0 | case 3: |
14011 | | // op: I4 |
14012 | 0 | return 12; |
14013 | 0 | case 4: |
14014 | | // op: M5 |
14015 | 0 | return 20; |
14016 | 0 | } |
14017 | 0 | break; |
14018 | 0 | } |
14019 | 0 | case SystemZ::VSLD: |
14020 | 0 | case SystemZ::VSLDB: |
14021 | 0 | case SystemZ::VSRD: { |
14022 | 0 | switch (OpNum) { |
14023 | 0 | case 0: |
14024 | | // op: V1 |
14025 | 0 | return 11; |
14026 | 0 | case 1: |
14027 | | // op: V2 |
14028 | 0 | return 10; |
14029 | 0 | case 2: |
14030 | | // op: V3 |
14031 | 0 | return 9; |
14032 | 0 | case 3: |
14033 | | // op: I4 |
14034 | 0 | return 16; |
14035 | 0 | } |
14036 | 0 | break; |
14037 | 0 | } |
14038 | 0 | case SystemZ::VFCE: |
14039 | 0 | case SystemZ::VFCH: |
14040 | 0 | case SystemZ::VFCHE: |
14041 | 0 | case SystemZ::VFMAX: |
14042 | 0 | case SystemZ::VFMIN: { |
14043 | 0 | switch (OpNum) { |
14044 | 0 | case 0: |
14045 | | // op: V1 |
14046 | 0 | return 11; |
14047 | 0 | case 1: |
14048 | | // op: V2 |
14049 | 0 | return 10; |
14050 | 0 | case 2: |
14051 | | // op: V3 |
14052 | 0 | return 9; |
14053 | 0 | case 3: |
14054 | | // op: M4 |
14055 | 0 | return 12; |
14056 | 0 | case 4: |
14057 | | // op: M5 |
14058 | 0 | return 16; |
14059 | 0 | case 5: |
14060 | | // op: M6 |
14061 | 0 | return 20; |
14062 | 0 | } |
14063 | 0 | break; |
14064 | 0 | } |
14065 | 0 | case SystemZ::VCRNF: |
14066 | 0 | case SystemZ::VFA: |
14067 | 0 | case SystemZ::VFD: |
14068 | 0 | case SystemZ::VFM: |
14069 | 0 | case SystemZ::VFS: { |
14070 | 0 | switch (OpNum) { |
14071 | 0 | case 0: |
14072 | | // op: V1 |
14073 | 0 | return 11; |
14074 | 0 | case 1: |
14075 | | // op: V2 |
14076 | 0 | return 10; |
14077 | 0 | case 2: |
14078 | | // op: V3 |
14079 | 0 | return 9; |
14080 | 0 | case 3: |
14081 | | // op: M4 |
14082 | 0 | return 12; |
14083 | 0 | case 4: |
14084 | | // op: M5 |
14085 | 0 | return 16; |
14086 | 0 | } |
14087 | 0 | break; |
14088 | 0 | } |
14089 | 0 | case SystemZ::VCEQ: |
14090 | 0 | case SystemZ::VCH: |
14091 | 0 | case SystemZ::VCHL: |
14092 | 0 | case SystemZ::VFAE: |
14093 | 0 | case SystemZ::VFEE: |
14094 | 0 | case SystemZ::VFENE: |
14095 | 0 | case SystemZ::VPKLS: |
14096 | 0 | case SystemZ::VPKS: |
14097 | 0 | case SystemZ::VSCHP: { |
14098 | 0 | switch (OpNum) { |
14099 | 0 | case 0: |
14100 | | // op: V1 |
14101 | 0 | return 11; |
14102 | 0 | case 1: |
14103 | | // op: V2 |
14104 | 0 | return 10; |
14105 | 0 | case 2: |
14106 | | // op: V3 |
14107 | 0 | return 9; |
14108 | 0 | case 3: |
14109 | | // op: M4 |
14110 | 0 | return 12; |
14111 | 0 | case 4: |
14112 | | // op: M5 |
14113 | 0 | return 20; |
14114 | 0 | } |
14115 | 0 | break; |
14116 | 0 | } |
14117 | 0 | case SystemZ::VA: |
14118 | 0 | case SystemZ::VACC: |
14119 | 0 | case SystemZ::VAVG: |
14120 | 0 | case SystemZ::VAVGL: |
14121 | 0 | case SystemZ::VERLLV: |
14122 | 0 | case SystemZ::VESLV: |
14123 | 0 | case SystemZ::VESRAV: |
14124 | 0 | case SystemZ::VESRLV: |
14125 | 0 | case SystemZ::VGFM: |
14126 | 0 | case SystemZ::VME: |
14127 | 0 | case SystemZ::VMH: |
14128 | 0 | case SystemZ::VML: |
14129 | 0 | case SystemZ::VMLE: |
14130 | 0 | case SystemZ::VMLH: |
14131 | 0 | case SystemZ::VMLO: |
14132 | 0 | case SystemZ::VMN: |
14133 | 0 | case SystemZ::VMNL: |
14134 | 0 | case SystemZ::VMO: |
14135 | 0 | case SystemZ::VMRH: |
14136 | 0 | case SystemZ::VMRL: |
14137 | 0 | case SystemZ::VMX: |
14138 | 0 | case SystemZ::VMXL: |
14139 | 0 | case SystemZ::VPDI: |
14140 | 0 | case SystemZ::VPK: |
14141 | 0 | case SystemZ::VS: |
14142 | 0 | case SystemZ::VSCBI: |
14143 | 0 | case SystemZ::VSUM: |
14144 | 0 | case SystemZ::VSUMG: |
14145 | 0 | case SystemZ::VSUMQ: { |
14146 | 0 | switch (OpNum) { |
14147 | 0 | case 0: |
14148 | | // op: V1 |
14149 | 0 | return 11; |
14150 | 0 | case 1: |
14151 | | // op: V2 |
14152 | 0 | return 10; |
14153 | 0 | case 2: |
14154 | | // op: V3 |
14155 | 0 | return 9; |
14156 | 0 | case 3: |
14157 | | // op: M4 |
14158 | 0 | return 12; |
14159 | 0 | } |
14160 | 0 | break; |
14161 | 0 | } |
14162 | 0 | case SystemZ::VCSPH: { |
14163 | 0 | switch (OpNum) { |
14164 | 0 | case 0: |
14165 | | // op: V1 |
14166 | 0 | return 11; |
14167 | 0 | case 1: |
14168 | | // op: V2 |
14169 | 0 | return 10; |
14170 | 0 | case 2: |
14171 | | // op: V3 |
14172 | 0 | return 9; |
14173 | 0 | case 3: |
14174 | | // op: M4 |
14175 | 0 | return 20; |
14176 | 0 | } |
14177 | 0 | break; |
14178 | 0 | } |
14179 | 0 | case SystemZ::VFAEB: |
14180 | 0 | case SystemZ::VFAEF: |
14181 | 0 | case SystemZ::VFAEH: |
14182 | 0 | case SystemZ::VFAEZB: |
14183 | 0 | case SystemZ::VFAEZF: |
14184 | 0 | case SystemZ::VFAEZH: |
14185 | 0 | case SystemZ::VFEEB: |
14186 | 0 | case SystemZ::VFEEF: |
14187 | 0 | case SystemZ::VFEEH: |
14188 | 0 | case SystemZ::VFENEB: |
14189 | 0 | case SystemZ::VFENEF: |
14190 | 0 | case SystemZ::VFENEH: |
14191 | 0 | case SystemZ::VSCHDP: |
14192 | 0 | case SystemZ::VSCHSP: |
14193 | 0 | case SystemZ::VSCHXP: { |
14194 | 0 | switch (OpNum) { |
14195 | 0 | case 0: |
14196 | | // op: V1 |
14197 | 0 | return 11; |
14198 | 0 | case 1: |
14199 | | // op: V2 |
14200 | 0 | return 10; |
14201 | 0 | case 2: |
14202 | | // op: V3 |
14203 | 0 | return 9; |
14204 | 0 | case 3: |
14205 | | // op: M5 |
14206 | 0 | return 20; |
14207 | 0 | } |
14208 | 0 | break; |
14209 | 0 | } |
14210 | 0 | case SystemZ::VFAEBS: |
14211 | 0 | case SystemZ::VFAEFS: |
14212 | 0 | case SystemZ::VFAEHS: { |
14213 | 0 | switch (OpNum) { |
14214 | 0 | case 0: |
14215 | | // op: V1 |
14216 | 0 | return 11; |
14217 | 0 | case 1: |
14218 | | // op: V2 |
14219 | 0 | return 10; |
14220 | 0 | case 2: |
14221 | | // op: V3 |
14222 | 0 | return 9; |
14223 | 0 | case 3: |
14224 | | // op: M5 |
14225 | 0 | return 21; |
14226 | 0 | } |
14227 | 0 | break; |
14228 | 0 | } |
14229 | 0 | case SystemZ::VFAEZBS: |
14230 | 0 | case SystemZ::VFAEZFS: |
14231 | 0 | case SystemZ::VFAEZHS: { |
14232 | 0 | switch (OpNum) { |
14233 | 0 | case 0: |
14234 | | // op: V1 |
14235 | 0 | return 11; |
14236 | 0 | case 1: |
14237 | | // op: V2 |
14238 | 0 | return 10; |
14239 | 0 | case 2: |
14240 | | // op: V3 |
14241 | 0 | return 9; |
14242 | 0 | case 3: |
14243 | | // op: M5 |
14244 | 0 | return 22; |
14245 | 0 | } |
14246 | 0 | break; |
14247 | 0 | } |
14248 | 0 | case SystemZ::VFMAXDB: |
14249 | 0 | case SystemZ::VFMAXSB: |
14250 | 0 | case SystemZ::VFMINDB: |
14251 | 0 | case SystemZ::VFMINSB: |
14252 | 0 | case SystemZ::WFMAXDB: |
14253 | 0 | case SystemZ::WFMAXSB: |
14254 | 0 | case SystemZ::WFMAXXB: |
14255 | 0 | case SystemZ::WFMINDB: |
14256 | 0 | case SystemZ::WFMINSB: |
14257 | 0 | case SystemZ::WFMINXB: { |
14258 | 0 | switch (OpNum) { |
14259 | 0 | case 0: |
14260 | | // op: V1 |
14261 | 0 | return 11; |
14262 | 0 | case 1: |
14263 | | // op: V2 |
14264 | 0 | return 10; |
14265 | 0 | case 2: |
14266 | | // op: V3 |
14267 | 0 | return 9; |
14268 | 0 | case 3: |
14269 | | // op: M6 |
14270 | 0 | return 20; |
14271 | 0 | } |
14272 | 0 | break; |
14273 | 0 | } |
14274 | 0 | case SystemZ::VFMA: |
14275 | 0 | case SystemZ::VFMS: |
14276 | 0 | case SystemZ::VFNMA: |
14277 | 0 | case SystemZ::VFNMS: { |
14278 | 0 | switch (OpNum) { |
14279 | 0 | case 0: |
14280 | | // op: V1 |
14281 | 0 | return 11; |
14282 | 0 | case 1: |
14283 | | // op: V2 |
14284 | 0 | return 10; |
14285 | 0 | case 2: |
14286 | | // op: V3 |
14287 | 0 | return 9; |
14288 | 0 | case 3: |
14289 | | // op: V4 |
14290 | 0 | return 8; |
14291 | 0 | case 4: |
14292 | | // op: M5 |
14293 | 0 | return 16; |
14294 | 0 | case 5: |
14295 | | // op: M6 |
14296 | 0 | return 24; |
14297 | 0 | } |
14298 | 0 | break; |
14299 | 0 | } |
14300 | 0 | case SystemZ::VMSL: |
14301 | 0 | case SystemZ::VSTRC: |
14302 | 0 | case SystemZ::VSTRS: { |
14303 | 0 | switch (OpNum) { |
14304 | 0 | case 0: |
14305 | | // op: V1 |
14306 | 0 | return 11; |
14307 | 0 | case 1: |
14308 | | // op: V2 |
14309 | 0 | return 10; |
14310 | 0 | case 2: |
14311 | | // op: V3 |
14312 | 0 | return 9; |
14313 | 0 | case 3: |
14314 | | // op: V4 |
14315 | 0 | return 8; |
14316 | 0 | case 4: |
14317 | | // op: M5 |
14318 | 0 | return 24; |
14319 | 0 | case 5: |
14320 | | // op: M6 |
14321 | 0 | return 20; |
14322 | 0 | } |
14323 | 0 | break; |
14324 | 0 | } |
14325 | 0 | case SystemZ::VAC: |
14326 | 0 | case SystemZ::VACCC: |
14327 | 0 | case SystemZ::VGFMA: |
14328 | 0 | case SystemZ::VMAE: |
14329 | 0 | case SystemZ::VMAH: |
14330 | 0 | case SystemZ::VMAL: |
14331 | 0 | case SystemZ::VMALE: |
14332 | 0 | case SystemZ::VMALH: |
14333 | 0 | case SystemZ::VMALO: |
14334 | 0 | case SystemZ::VMAO: |
14335 | 0 | case SystemZ::VSBCBI: |
14336 | 0 | case SystemZ::VSBI: { |
14337 | 0 | switch (OpNum) { |
14338 | 0 | case 0: |
14339 | | // op: V1 |
14340 | 0 | return 11; |
14341 | 0 | case 1: |
14342 | | // op: V2 |
14343 | 0 | return 10; |
14344 | 0 | case 2: |
14345 | | // op: V3 |
14346 | 0 | return 9; |
14347 | 0 | case 3: |
14348 | | // op: V4 |
14349 | 0 | return 8; |
14350 | 0 | case 4: |
14351 | | // op: M5 |
14352 | 0 | return 24; |
14353 | 0 | } |
14354 | 0 | break; |
14355 | 0 | } |
14356 | 0 | case SystemZ::VMSLG: |
14357 | 0 | case SystemZ::VSTRCB: |
14358 | 0 | case SystemZ::VSTRCF: |
14359 | 0 | case SystemZ::VSTRCH: |
14360 | 0 | case SystemZ::VSTRCZB: |
14361 | 0 | case SystemZ::VSTRCZF: |
14362 | 0 | case SystemZ::VSTRCZH: |
14363 | 0 | case SystemZ::VSTRSB: |
14364 | 0 | case SystemZ::VSTRSF: |
14365 | 0 | case SystemZ::VSTRSH: { |
14366 | 0 | switch (OpNum) { |
14367 | 0 | case 0: |
14368 | | // op: V1 |
14369 | 0 | return 11; |
14370 | 0 | case 1: |
14371 | | // op: V2 |
14372 | 0 | return 10; |
14373 | 0 | case 2: |
14374 | | // op: V3 |
14375 | 0 | return 9; |
14376 | 0 | case 3: |
14377 | | // op: V4 |
14378 | 0 | return 8; |
14379 | 0 | case 4: |
14380 | | // op: M6 |
14381 | 0 | return 20; |
14382 | 0 | } |
14383 | 0 | break; |
14384 | 0 | } |
14385 | 0 | case SystemZ::VSTRCBS: |
14386 | 0 | case SystemZ::VSTRCFS: |
14387 | 0 | case SystemZ::VSTRCHS: { |
14388 | 0 | switch (OpNum) { |
14389 | 0 | case 0: |
14390 | | // op: V1 |
14391 | 0 | return 11; |
14392 | 0 | case 1: |
14393 | | // op: V2 |
14394 | 0 | return 10; |
14395 | 0 | case 2: |
14396 | | // op: V3 |
14397 | 0 | return 9; |
14398 | 0 | case 3: |
14399 | | // op: V4 |
14400 | 0 | return 8; |
14401 | 0 | case 4: |
14402 | | // op: M6 |
14403 | 0 | return 21; |
14404 | 0 | } |
14405 | 0 | break; |
14406 | 0 | } |
14407 | 0 | case SystemZ::VSTRCZBS: |
14408 | 0 | case SystemZ::VSTRCZFS: |
14409 | 0 | case SystemZ::VSTRCZHS: { |
14410 | 0 | switch (OpNum) { |
14411 | 0 | case 0: |
14412 | | // op: V1 |
14413 | 0 | return 11; |
14414 | 0 | case 1: |
14415 | | // op: V2 |
14416 | 0 | return 10; |
14417 | 0 | case 2: |
14418 | | // op: V3 |
14419 | 0 | return 9; |
14420 | 0 | case 3: |
14421 | | // op: V4 |
14422 | 0 | return 8; |
14423 | 0 | case 4: |
14424 | | // op: M6 |
14425 | 0 | return 22; |
14426 | 0 | } |
14427 | 0 | break; |
14428 | 0 | } |
14429 | 0 | case SystemZ::VACCCQ: |
14430 | 0 | case SystemZ::VACQ: |
14431 | 0 | case SystemZ::VFMADB: |
14432 | 0 | case SystemZ::VFMASB: |
14433 | 0 | case SystemZ::VFMSDB: |
14434 | 0 | case SystemZ::VFMSSB: |
14435 | 0 | case SystemZ::VFNMADB: |
14436 | 0 | case SystemZ::VFNMASB: |
14437 | 0 | case SystemZ::VFNMSDB: |
14438 | 0 | case SystemZ::VFNMSSB: |
14439 | 0 | case SystemZ::VGFMAB: |
14440 | 0 | case SystemZ::VGFMAF: |
14441 | 0 | case SystemZ::VGFMAG: |
14442 | 0 | case SystemZ::VGFMAH: |
14443 | 0 | case SystemZ::VMAEB: |
14444 | 0 | case SystemZ::VMAEF: |
14445 | 0 | case SystemZ::VMAEH: |
14446 | 0 | case SystemZ::VMAHB: |
14447 | 0 | case SystemZ::VMAHF: |
14448 | 0 | case SystemZ::VMAHH: |
14449 | 0 | case SystemZ::VMALB: |
14450 | 0 | case SystemZ::VMALEB: |
14451 | 0 | case SystemZ::VMALEF: |
14452 | 0 | case SystemZ::VMALEH: |
14453 | 0 | case SystemZ::VMALF: |
14454 | 0 | case SystemZ::VMALHB: |
14455 | 0 | case SystemZ::VMALHF: |
14456 | 0 | case SystemZ::VMALHH: |
14457 | 0 | case SystemZ::VMALHW: |
14458 | 0 | case SystemZ::VMALOB: |
14459 | 0 | case SystemZ::VMALOF: |
14460 | 0 | case SystemZ::VMALOH: |
14461 | 0 | case SystemZ::VMAOB: |
14462 | 0 | case SystemZ::VMAOF: |
14463 | 0 | case SystemZ::VMAOH: |
14464 | 0 | case SystemZ::VPERM: |
14465 | 0 | case SystemZ::VSBCBIQ: |
14466 | 0 | case SystemZ::VSBIQ: |
14467 | 0 | case SystemZ::VSEL: |
14468 | 0 | case SystemZ::VSTRSZB: |
14469 | 0 | case SystemZ::VSTRSZF: |
14470 | 0 | case SystemZ::VSTRSZH: |
14471 | 0 | case SystemZ::WFMADB: |
14472 | 0 | case SystemZ::WFMASB: |
14473 | 0 | case SystemZ::WFMAXB: |
14474 | 0 | case SystemZ::WFMSDB: |
14475 | 0 | case SystemZ::WFMSSB: |
14476 | 0 | case SystemZ::WFMSXB: |
14477 | 0 | case SystemZ::WFNMADB: |
14478 | 0 | case SystemZ::WFNMASB: |
14479 | 0 | case SystemZ::WFNMAXB: |
14480 | 0 | case SystemZ::WFNMSDB: |
14481 | 0 | case SystemZ::WFNMSSB: |
14482 | 0 | case SystemZ::WFNMSXB: { |
14483 | 0 | switch (OpNum) { |
14484 | 0 | case 0: |
14485 | | // op: V1 |
14486 | 0 | return 11; |
14487 | 0 | case 1: |
14488 | | // op: V2 |
14489 | 0 | return 10; |
14490 | 0 | case 2: |
14491 | | // op: V3 |
14492 | 0 | return 9; |
14493 | 0 | case 3: |
14494 | | // op: V4 |
14495 | 0 | return 8; |
14496 | 0 | } |
14497 | 0 | break; |
14498 | 0 | } |
14499 | 0 | case SystemZ::VAB: |
14500 | 0 | case SystemZ::VACCB: |
14501 | 0 | case SystemZ::VACCF: |
14502 | 0 | case SystemZ::VACCG: |
14503 | 0 | case SystemZ::VACCH: |
14504 | 0 | case SystemZ::VACCQ: |
14505 | 0 | case SystemZ::VAF: |
14506 | 0 | case SystemZ::VAG: |
14507 | 0 | case SystemZ::VAH: |
14508 | 0 | case SystemZ::VAQ: |
14509 | 0 | case SystemZ::VAVGB: |
14510 | 0 | case SystemZ::VAVGF: |
14511 | 0 | case SystemZ::VAVGG: |
14512 | 0 | case SystemZ::VAVGH: |
14513 | 0 | case SystemZ::VAVGLB: |
14514 | 0 | case SystemZ::VAVGLF: |
14515 | 0 | case SystemZ::VAVGLG: |
14516 | 0 | case SystemZ::VAVGLH: |
14517 | 0 | case SystemZ::VBPERM: |
14518 | 0 | case SystemZ::VCEQB: |
14519 | 0 | case SystemZ::VCEQBS: |
14520 | 0 | case SystemZ::VCEQF: |
14521 | 0 | case SystemZ::VCEQFS: |
14522 | 0 | case SystemZ::VCEQG: |
14523 | 0 | case SystemZ::VCEQGS: |
14524 | 0 | case SystemZ::VCEQH: |
14525 | 0 | case SystemZ::VCEQHS: |
14526 | 0 | case SystemZ::VCHB: |
14527 | 0 | case SystemZ::VCHBS: |
14528 | 0 | case SystemZ::VCHF: |
14529 | 0 | case SystemZ::VCHFS: |
14530 | 0 | case SystemZ::VCHG: |
14531 | 0 | case SystemZ::VCHGS: |
14532 | 0 | case SystemZ::VCHH: |
14533 | 0 | case SystemZ::VCHHS: |
14534 | 0 | case SystemZ::VCHLB: |
14535 | 0 | case SystemZ::VCHLBS: |
14536 | 0 | case SystemZ::VCHLF: |
14537 | 0 | case SystemZ::VCHLFS: |
14538 | 0 | case SystemZ::VCHLG: |
14539 | 0 | case SystemZ::VCHLGS: |
14540 | 0 | case SystemZ::VCHLH: |
14541 | 0 | case SystemZ::VCHLHS: |
14542 | 0 | case SystemZ::VCKSM: |
14543 | 0 | case SystemZ::VERLLVB: |
14544 | 0 | case SystemZ::VERLLVF: |
14545 | 0 | case SystemZ::VERLLVG: |
14546 | 0 | case SystemZ::VERLLVH: |
14547 | 0 | case SystemZ::VESLVB: |
14548 | 0 | case SystemZ::VESLVF: |
14549 | 0 | case SystemZ::VESLVG: |
14550 | 0 | case SystemZ::VESLVH: |
14551 | 0 | case SystemZ::VESRAVB: |
14552 | 0 | case SystemZ::VESRAVF: |
14553 | 0 | case SystemZ::VESRAVG: |
14554 | 0 | case SystemZ::VESRAVH: |
14555 | 0 | case SystemZ::VESRLVB: |
14556 | 0 | case SystemZ::VESRLVF: |
14557 | 0 | case SystemZ::VESRLVG: |
14558 | 0 | case SystemZ::VESRLVH: |
14559 | 0 | case SystemZ::VFADB: |
14560 | 0 | case SystemZ::VFASB: |
14561 | 0 | case SystemZ::VFCEDB: |
14562 | 0 | case SystemZ::VFCEDBS: |
14563 | 0 | case SystemZ::VFCESB: |
14564 | 0 | case SystemZ::VFCESBS: |
14565 | 0 | case SystemZ::VFCHDB: |
14566 | 0 | case SystemZ::VFCHDBS: |
14567 | 0 | case SystemZ::VFCHEDB: |
14568 | 0 | case SystemZ::VFCHEDBS: |
14569 | 0 | case SystemZ::VFCHESB: |
14570 | 0 | case SystemZ::VFCHESBS: |
14571 | 0 | case SystemZ::VFCHSB: |
14572 | 0 | case SystemZ::VFCHSBS: |
14573 | 0 | case SystemZ::VFDDB: |
14574 | 0 | case SystemZ::VFDSB: |
14575 | 0 | case SystemZ::VFEEBS: |
14576 | 0 | case SystemZ::VFEEFS: |
14577 | 0 | case SystemZ::VFEEHS: |
14578 | 0 | case SystemZ::VFEEZB: |
14579 | 0 | case SystemZ::VFEEZBS: |
14580 | 0 | case SystemZ::VFEEZF: |
14581 | 0 | case SystemZ::VFEEZFS: |
14582 | 0 | case SystemZ::VFEEZH: |
14583 | 0 | case SystemZ::VFEEZHS: |
14584 | 0 | case SystemZ::VFENEBS: |
14585 | 0 | case SystemZ::VFENEFS: |
14586 | 0 | case SystemZ::VFENEHS: |
14587 | 0 | case SystemZ::VFENEZB: |
14588 | 0 | case SystemZ::VFENEZBS: |
14589 | 0 | case SystemZ::VFENEZF: |
14590 | 0 | case SystemZ::VFENEZFS: |
14591 | 0 | case SystemZ::VFENEZH: |
14592 | 0 | case SystemZ::VFENEZHS: |
14593 | 0 | case SystemZ::VFKEDB: |
14594 | 0 | case SystemZ::VFKEDBS: |
14595 | 0 | case SystemZ::VFKESB: |
14596 | 0 | case SystemZ::VFKESBS: |
14597 | 0 | case SystemZ::VFKHDB: |
14598 | 0 | case SystemZ::VFKHDBS: |
14599 | 0 | case SystemZ::VFKHEDB: |
14600 | 0 | case SystemZ::VFKHEDBS: |
14601 | 0 | case SystemZ::VFKHESB: |
14602 | 0 | case SystemZ::VFKHESBS: |
14603 | 0 | case SystemZ::VFKHSB: |
14604 | 0 | case SystemZ::VFKHSBS: |
14605 | 0 | case SystemZ::VFMDB: |
14606 | 0 | case SystemZ::VFMSB: |
14607 | 0 | case SystemZ::VFSDB: |
14608 | 0 | case SystemZ::VFSSB: |
14609 | 0 | case SystemZ::VGFMB: |
14610 | 0 | case SystemZ::VGFMF: |
14611 | 0 | case SystemZ::VGFMG: |
14612 | 0 | case SystemZ::VGFMH: |
14613 | 0 | case SystemZ::VMEB: |
14614 | 0 | case SystemZ::VMEF: |
14615 | 0 | case SystemZ::VMEH: |
14616 | 0 | case SystemZ::VMHB: |
14617 | 0 | case SystemZ::VMHF: |
14618 | 0 | case SystemZ::VMHH: |
14619 | 0 | case SystemZ::VMLB: |
14620 | 0 | case SystemZ::VMLEB: |
14621 | 0 | case SystemZ::VMLEF: |
14622 | 0 | case SystemZ::VMLEH: |
14623 | 0 | case SystemZ::VMLF: |
14624 | 0 | case SystemZ::VMLHB: |
14625 | 0 | case SystemZ::VMLHF: |
14626 | 0 | case SystemZ::VMLHH: |
14627 | 0 | case SystemZ::VMLHW: |
14628 | 0 | case SystemZ::VMLOB: |
14629 | 0 | case SystemZ::VMLOF: |
14630 | 0 | case SystemZ::VMLOH: |
14631 | 0 | case SystemZ::VMNB: |
14632 | 0 | case SystemZ::VMNF: |
14633 | 0 | case SystemZ::VMNG: |
14634 | 0 | case SystemZ::VMNH: |
14635 | 0 | case SystemZ::VMNLB: |
14636 | 0 | case SystemZ::VMNLF: |
14637 | 0 | case SystemZ::VMNLG: |
14638 | 0 | case SystemZ::VMNLH: |
14639 | 0 | case SystemZ::VMOB: |
14640 | 0 | case SystemZ::VMOF: |
14641 | 0 | case SystemZ::VMOH: |
14642 | 0 | case SystemZ::VMRHB: |
14643 | 0 | case SystemZ::VMRHF: |
14644 | 0 | case SystemZ::VMRHG: |
14645 | 0 | case SystemZ::VMRHH: |
14646 | 0 | case SystemZ::VMRLB: |
14647 | 0 | case SystemZ::VMRLF: |
14648 | 0 | case SystemZ::VMRLG: |
14649 | 0 | case SystemZ::VMRLH: |
14650 | 0 | case SystemZ::VMXB: |
14651 | 0 | case SystemZ::VMXF: |
14652 | 0 | case SystemZ::VMXG: |
14653 | 0 | case SystemZ::VMXH: |
14654 | 0 | case SystemZ::VMXLB: |
14655 | 0 | case SystemZ::VMXLF: |
14656 | 0 | case SystemZ::VMXLG: |
14657 | 0 | case SystemZ::VMXLH: |
14658 | 0 | case SystemZ::VN: |
14659 | 0 | case SystemZ::VNC: |
14660 | 0 | case SystemZ::VNN: |
14661 | 0 | case SystemZ::VNO: |
14662 | 0 | case SystemZ::VNX: |
14663 | 0 | case SystemZ::VO: |
14664 | 0 | case SystemZ::VOC: |
14665 | 0 | case SystemZ::VPKF: |
14666 | 0 | case SystemZ::VPKG: |
14667 | 0 | case SystemZ::VPKH: |
14668 | 0 | case SystemZ::VPKLSF: |
14669 | 0 | case SystemZ::VPKLSFS: |
14670 | 0 | case SystemZ::VPKLSG: |
14671 | 0 | case SystemZ::VPKLSGS: |
14672 | 0 | case SystemZ::VPKLSH: |
14673 | 0 | case SystemZ::VPKLSHS: |
14674 | 0 | case SystemZ::VPKSF: |
14675 | 0 | case SystemZ::VPKSFS: |
14676 | 0 | case SystemZ::VPKSG: |
14677 | 0 | case SystemZ::VPKSGS: |
14678 | 0 | case SystemZ::VPKSH: |
14679 | 0 | case SystemZ::VPKSHS: |
14680 | 0 | case SystemZ::VSB: |
14681 | 0 | case SystemZ::VSCBIB: |
14682 | 0 | case SystemZ::VSCBIF: |
14683 | 0 | case SystemZ::VSCBIG: |
14684 | 0 | case SystemZ::VSCBIH: |
14685 | 0 | case SystemZ::VSCBIQ: |
14686 | 0 | case SystemZ::VSCSHP: |
14687 | 0 | case SystemZ::VSF: |
14688 | 0 | case SystemZ::VSG: |
14689 | 0 | case SystemZ::VSH: |
14690 | 0 | case SystemZ::VSL: |
14691 | 0 | case SystemZ::VSLB: |
14692 | 0 | case SystemZ::VSQ: |
14693 | 0 | case SystemZ::VSRA: |
14694 | 0 | case SystemZ::VSRAB: |
14695 | 0 | case SystemZ::VSRL: |
14696 | 0 | case SystemZ::VSRLB: |
14697 | 0 | case SystemZ::VSUMB: |
14698 | 0 | case SystemZ::VSUMGF: |
14699 | 0 | case SystemZ::VSUMGH: |
14700 | 0 | case SystemZ::VSUMH: |
14701 | 0 | case SystemZ::VSUMQF: |
14702 | 0 | case SystemZ::VSUMQG: |
14703 | 0 | case SystemZ::VX: |
14704 | 0 | case SystemZ::WFADB: |
14705 | 0 | case SystemZ::WFASB: |
14706 | 0 | case SystemZ::WFAXB: |
14707 | 0 | case SystemZ::WFCEDB: |
14708 | 0 | case SystemZ::WFCEDBS: |
14709 | 0 | case SystemZ::WFCESB: |
14710 | 0 | case SystemZ::WFCESBS: |
14711 | 0 | case SystemZ::WFCEXB: |
14712 | 0 | case SystemZ::WFCEXBS: |
14713 | 0 | case SystemZ::WFCHDB: |
14714 | 0 | case SystemZ::WFCHDBS: |
14715 | 0 | case SystemZ::WFCHEDB: |
14716 | 0 | case SystemZ::WFCHEDBS: |
14717 | 0 | case SystemZ::WFCHESB: |
14718 | 0 | case SystemZ::WFCHESBS: |
14719 | 0 | case SystemZ::WFCHEXB: |
14720 | 0 | case SystemZ::WFCHEXBS: |
14721 | 0 | case SystemZ::WFCHSB: |
14722 | 0 | case SystemZ::WFCHSBS: |
14723 | 0 | case SystemZ::WFCHXB: |
14724 | 0 | case SystemZ::WFCHXBS: |
14725 | 0 | case SystemZ::WFDDB: |
14726 | 0 | case SystemZ::WFDSB: |
14727 | 0 | case SystemZ::WFDXB: |
14728 | 0 | case SystemZ::WFKEDB: |
14729 | 0 | case SystemZ::WFKEDBS: |
14730 | 0 | case SystemZ::WFKESB: |
14731 | 0 | case SystemZ::WFKESBS: |
14732 | 0 | case SystemZ::WFKEXB: |
14733 | 0 | case SystemZ::WFKEXBS: |
14734 | 0 | case SystemZ::WFKHDB: |
14735 | 0 | case SystemZ::WFKHDBS: |
14736 | 0 | case SystemZ::WFKHEDB: |
14737 | 0 | case SystemZ::WFKHEDBS: |
14738 | 0 | case SystemZ::WFKHESB: |
14739 | 0 | case SystemZ::WFKHESBS: |
14740 | 0 | case SystemZ::WFKHEXB: |
14741 | 0 | case SystemZ::WFKHEXBS: |
14742 | 0 | case SystemZ::WFKHSB: |
14743 | 0 | case SystemZ::WFKHSBS: |
14744 | 0 | case SystemZ::WFKHXB: |
14745 | 0 | case SystemZ::WFKHXBS: |
14746 | 0 | case SystemZ::WFMDB: |
14747 | 0 | case SystemZ::WFMSB: |
14748 | 0 | case SystemZ::WFMXB: |
14749 | 0 | case SystemZ::WFSDB: |
14750 | 0 | case SystemZ::WFSSB: |
14751 | 0 | case SystemZ::WFSXB: { |
14752 | 0 | switch (OpNum) { |
14753 | 0 | case 0: |
14754 | | // op: V1 |
14755 | 0 | return 11; |
14756 | 0 | case 1: |
14757 | | // op: V2 |
14758 | 0 | return 10; |
14759 | 0 | case 2: |
14760 | | // op: V3 |
14761 | 0 | return 9; |
14762 | 0 | } |
14763 | 0 | break; |
14764 | 0 | } |
14765 | 0 | case SystemZ::VCLZB: |
14766 | 0 | case SystemZ::VCLZF: |
14767 | 0 | case SystemZ::VCLZG: |
14768 | 0 | case SystemZ::VCLZH: |
14769 | 0 | case SystemZ::VCTZB: |
14770 | 0 | case SystemZ::VCTZF: |
14771 | 0 | case SystemZ::VCTZG: |
14772 | 0 | case SystemZ::VCTZH: |
14773 | 0 | case SystemZ::VECB: |
14774 | 0 | case SystemZ::VECF: |
14775 | 0 | case SystemZ::VECG: |
14776 | 0 | case SystemZ::VECH: |
14777 | 0 | case SystemZ::VECLB: |
14778 | 0 | case SystemZ::VECLF: |
14779 | 0 | case SystemZ::VECLG: |
14780 | 0 | case SystemZ::VECLH: |
14781 | 0 | case SystemZ::VFLCDB: |
14782 | 0 | case SystemZ::VFLCSB: |
14783 | 0 | case SystemZ::VFLLS: |
14784 | 0 | case SystemZ::VFLNDB: |
14785 | 0 | case SystemZ::VFLNSB: |
14786 | 0 | case SystemZ::VFLPDB: |
14787 | 0 | case SystemZ::VFLPSB: |
14788 | 0 | case SystemZ::VFSQDB: |
14789 | 0 | case SystemZ::VFSQSB: |
14790 | 0 | case SystemZ::VISTRBS: |
14791 | 0 | case SystemZ::VISTRFS: |
14792 | 0 | case SystemZ::VISTRHS: |
14793 | 0 | case SystemZ::VLCB: |
14794 | 0 | case SystemZ::VLCF: |
14795 | 0 | case SystemZ::VLCG: |
14796 | 0 | case SystemZ::VLCH: |
14797 | 0 | case SystemZ::VLDEB: |
14798 | 0 | case SystemZ::VLPB: |
14799 | 0 | case SystemZ::VLPF: |
14800 | 0 | case SystemZ::VLPG: |
14801 | 0 | case SystemZ::VLPH: |
14802 | 0 | case SystemZ::VLR: |
14803 | 0 | case SystemZ::VPOPCTB: |
14804 | 0 | case SystemZ::VPOPCTF: |
14805 | 0 | case SystemZ::VPOPCTG: |
14806 | 0 | case SystemZ::VPOPCTH: |
14807 | 0 | case SystemZ::VSEGB: |
14808 | 0 | case SystemZ::VSEGF: |
14809 | 0 | case SystemZ::VSEGH: |
14810 | 0 | case SystemZ::VTM: |
14811 | 0 | case SystemZ::VUPHB: |
14812 | 0 | case SystemZ::VUPHF: |
14813 | 0 | case SystemZ::VUPHH: |
14814 | 0 | case SystemZ::VUPLB: |
14815 | 0 | case SystemZ::VUPLF: |
14816 | 0 | case SystemZ::VUPLHB: |
14817 | 0 | case SystemZ::VUPLHF: |
14818 | 0 | case SystemZ::VUPLHH: |
14819 | 0 | case SystemZ::VUPLHW: |
14820 | 0 | case SystemZ::VUPLLB: |
14821 | 0 | case SystemZ::VUPLLF: |
14822 | 0 | case SystemZ::VUPLLH: |
14823 | 0 | case SystemZ::WFCDB: |
14824 | 0 | case SystemZ::WFCSB: |
14825 | 0 | case SystemZ::WFCXB: |
14826 | 0 | case SystemZ::WFKDB: |
14827 | 0 | case SystemZ::WFKSB: |
14828 | 0 | case SystemZ::WFKXB: |
14829 | 0 | case SystemZ::WFLCDB: |
14830 | 0 | case SystemZ::WFLCSB: |
14831 | 0 | case SystemZ::WFLCXB: |
14832 | 0 | case SystemZ::WFLLD: |
14833 | 0 | case SystemZ::WFLLS: |
14834 | 0 | case SystemZ::WFLNDB: |
14835 | 0 | case SystemZ::WFLNSB: |
14836 | 0 | case SystemZ::WFLNXB: |
14837 | 0 | case SystemZ::WFLPDB: |
14838 | 0 | case SystemZ::WFLPSB: |
14839 | 0 | case SystemZ::WFLPXB: |
14840 | 0 | case SystemZ::WFSQDB: |
14841 | 0 | case SystemZ::WFSQSB: |
14842 | 0 | case SystemZ::WFSQXB: |
14843 | 0 | case SystemZ::WLDEB: { |
14844 | 0 | switch (OpNum) { |
14845 | 0 | case 0: |
14846 | | // op: V1 |
14847 | 0 | return 11; |
14848 | 0 | case 1: |
14849 | | // op: V2 |
14850 | 0 | return 10; |
14851 | 0 | } |
14852 | 0 | break; |
14853 | 0 | } |
14854 | 0 | case SystemZ::VREP: { |
14855 | 0 | switch (OpNum) { |
14856 | 0 | case 0: |
14857 | | // op: V1 |
14858 | 0 | return 11; |
14859 | 0 | case 1: |
14860 | | // op: V3 |
14861 | 0 | return 10; |
14862 | 0 | case 2: |
14863 | | // op: I2 |
14864 | 0 | return 16; |
14865 | 0 | case 3: |
14866 | | // op: M4 |
14867 | 0 | return 12; |
14868 | 0 | } |
14869 | 0 | break; |
14870 | 0 | } |
14871 | 0 | case SystemZ::VREPB: |
14872 | 0 | case SystemZ::VREPF: |
14873 | 0 | case SystemZ::VREPG: |
14874 | 0 | case SystemZ::VREPH: { |
14875 | 0 | switch (OpNum) { |
14876 | 0 | case 0: |
14877 | | // op: V1 |
14878 | 0 | return 11; |
14879 | 0 | case 1: |
14880 | | // op: V3 |
14881 | 0 | return 10; |
14882 | 0 | case 2: |
14883 | | // op: I2 |
14884 | 0 | return 16; |
14885 | 0 | } |
14886 | 0 | break; |
14887 | 0 | } |
14888 | 0 | case SystemZ::VLL: |
14889 | 0 | case SystemZ::VSTL: { |
14890 | 0 | switch (OpNum) { |
14891 | 0 | case 0: |
14892 | | // op: V1 |
14893 | 0 | return 11; |
14894 | 0 | case 2: |
14895 | | // op: B2 |
14896 | 0 | return 28; |
14897 | 0 | case 3: |
14898 | | // op: D2 |
14899 | 0 | return 16; |
14900 | 0 | case 1: |
14901 | | // op: R3 |
14902 | 0 | return 32; |
14903 | 0 | } |
14904 | 0 | break; |
14905 | 0 | } |
14906 | 0 | case SystemZ::VERLL: |
14907 | 0 | case SystemZ::VESL: |
14908 | 0 | case SystemZ::VESRA: |
14909 | 0 | case SystemZ::VESRL: |
14910 | 0 | case SystemZ::VLMAlign: |
14911 | 0 | case SystemZ::VSTMAlign: { |
14912 | 0 | switch (OpNum) { |
14913 | 0 | case 0: |
14914 | | // op: V1 |
14915 | 0 | return 11; |
14916 | 0 | case 2: |
14917 | | // op: B2 |
14918 | 0 | return 28; |
14919 | 0 | case 3: |
14920 | | // op: D2 |
14921 | 0 | return 16; |
14922 | 0 | case 1: |
14923 | | // op: V3 |
14924 | 0 | return 10; |
14925 | 0 | case 4: |
14926 | | // op: M4 |
14927 | 0 | return 12; |
14928 | 0 | } |
14929 | 0 | break; |
14930 | 0 | } |
14931 | 0 | case SystemZ::VERLLB: |
14932 | 0 | case SystemZ::VERLLF: |
14933 | 0 | case SystemZ::VERLLG: |
14934 | 0 | case SystemZ::VERLLH: |
14935 | 0 | case SystemZ::VESLB: |
14936 | 0 | case SystemZ::VESLF: |
14937 | 0 | case SystemZ::VESLG: |
14938 | 0 | case SystemZ::VESLH: |
14939 | 0 | case SystemZ::VESRAB: |
14940 | 0 | case SystemZ::VESRAF: |
14941 | 0 | case SystemZ::VESRAG: |
14942 | 0 | case SystemZ::VESRAH: |
14943 | 0 | case SystemZ::VESRLB: |
14944 | 0 | case SystemZ::VESRLF: |
14945 | 0 | case SystemZ::VESRLG: |
14946 | 0 | case SystemZ::VESRLH: |
14947 | 0 | case SystemZ::VLM: |
14948 | 0 | case SystemZ::VSTM: { |
14949 | 0 | switch (OpNum) { |
14950 | 0 | case 0: |
14951 | | // op: V1 |
14952 | 0 | return 11; |
14953 | 0 | case 2: |
14954 | | // op: B2 |
14955 | 0 | return 28; |
14956 | 0 | case 3: |
14957 | | // op: D2 |
14958 | 0 | return 16; |
14959 | 0 | case 1: |
14960 | | // op: V3 |
14961 | 0 | return 10; |
14962 | 0 | } |
14963 | 0 | break; |
14964 | 0 | } |
14965 | 0 | case SystemZ::VLEIB: |
14966 | 0 | case SystemZ::VLEIF: |
14967 | 0 | case SystemZ::VLEIG: |
14968 | 0 | case SystemZ::VLEIH: { |
14969 | 0 | switch (OpNum) { |
14970 | 0 | case 0: |
14971 | | // op: V1 |
14972 | 0 | return 11; |
14973 | 0 | case 2: |
14974 | | // op: I2 |
14975 | 0 | return 16; |
14976 | 0 | case 3: |
14977 | | // op: M3 |
14978 | 0 | return 12; |
14979 | 0 | } |
14980 | 0 | break; |
14981 | 0 | } |
14982 | 0 | case SystemZ::VERIM: { |
14983 | 0 | switch (OpNum) { |
14984 | 0 | case 0: |
14985 | | // op: V1 |
14986 | 0 | return 11; |
14987 | 0 | case 2: |
14988 | | // op: V2 |
14989 | 0 | return 10; |
14990 | 0 | case 3: |
14991 | | // op: V3 |
14992 | 0 | return 9; |
14993 | 0 | case 4: |
14994 | | // op: I4 |
14995 | 0 | return 16; |
14996 | 0 | case 5: |
14997 | | // op: M5 |
14998 | 0 | return 12; |
14999 | 0 | } |
15000 | 0 | break; |
15001 | 0 | } |
15002 | 0 | case SystemZ::VERIMB: |
15003 | 0 | case SystemZ::VERIMF: |
15004 | 0 | case SystemZ::VERIMG: |
15005 | 0 | case SystemZ::VERIMH: { |
15006 | 0 | switch (OpNum) { |
15007 | 0 | case 0: |
15008 | | // op: V1 |
15009 | 0 | return 11; |
15010 | 0 | case 2: |
15011 | | // op: V2 |
15012 | 0 | return 10; |
15013 | 0 | case 3: |
15014 | | // op: V3 |
15015 | 0 | return 9; |
15016 | 0 | case 4: |
15017 | | // op: I4 |
15018 | 0 | return 16; |
15019 | 0 | } |
15020 | 0 | break; |
15021 | 0 | } |
15022 | 0 | case SystemZ::VLVG: { |
15023 | 0 | switch (OpNum) { |
15024 | 0 | case 0: |
15025 | | // op: V1 |
15026 | 0 | return 11; |
15027 | 0 | case 3: |
15028 | | // op: B2 |
15029 | 0 | return 28; |
15030 | 0 | case 4: |
15031 | | // op: D2 |
15032 | 0 | return 16; |
15033 | 0 | case 2: |
15034 | | // op: R3 |
15035 | 0 | return 32; |
15036 | 0 | case 5: |
15037 | | // op: M4 |
15038 | 0 | return 12; |
15039 | 0 | } |
15040 | 0 | break; |
15041 | 0 | } |
15042 | 0 | case SystemZ::VLVGB: |
15043 | 0 | case SystemZ::VLVGF: |
15044 | 0 | case SystemZ::VLVGG: |
15045 | 0 | case SystemZ::VLVGH: { |
15046 | 0 | switch (OpNum) { |
15047 | 0 | case 0: |
15048 | | // op: V1 |
15049 | 0 | return 11; |
15050 | 0 | case 3: |
15051 | | // op: B2 |
15052 | 0 | return 28; |
15053 | 0 | case 4: |
15054 | | // op: D2 |
15055 | 0 | return 16; |
15056 | 0 | case 2: |
15057 | | // op: R3 |
15058 | 0 | return 32; |
15059 | 0 | } |
15060 | 0 | break; |
15061 | 0 | } |
15062 | 0 | case SystemZ::VSCEF: |
15063 | 0 | case SystemZ::VSCEG: { |
15064 | 0 | switch (OpNum) { |
15065 | 0 | case 0: |
15066 | | // op: V1 |
15067 | 0 | return 11; |
15068 | 0 | case 3: |
15069 | | // op: V2 |
15070 | 0 | return 10; |
15071 | 0 | case 1: |
15072 | | // op: B2 |
15073 | 0 | return 28; |
15074 | 0 | case 2: |
15075 | | // op: D2 |
15076 | 0 | return 16; |
15077 | 0 | case 4: |
15078 | | // op: M3 |
15079 | 0 | return 12; |
15080 | 0 | } |
15081 | 0 | break; |
15082 | 0 | } |
15083 | 0 | case SystemZ::VLAlign: |
15084 | 0 | case SystemZ::VLBB: |
15085 | 0 | case SystemZ::VLBR: |
15086 | 0 | case SystemZ::VLBRREP: |
15087 | 0 | case SystemZ::VLER: |
15088 | 0 | case SystemZ::VLLEBRZ: |
15089 | 0 | case SystemZ::VLLEZ: |
15090 | 0 | case SystemZ::VLREP: |
15091 | 0 | case SystemZ::VSTAlign: |
15092 | 0 | case SystemZ::VSTBR: |
15093 | 0 | case SystemZ::VSTEB: |
15094 | 0 | case SystemZ::VSTEBRF: |
15095 | 0 | case SystemZ::VSTEBRG: |
15096 | 0 | case SystemZ::VSTEBRH: |
15097 | 0 | case SystemZ::VSTEF: |
15098 | 0 | case SystemZ::VSTEG: |
15099 | 0 | case SystemZ::VSTEH: |
15100 | 0 | case SystemZ::VSTER: { |
15101 | 0 | switch (OpNum) { |
15102 | 0 | case 0: |
15103 | | // op: V1 |
15104 | 0 | return 11; |
15105 | 0 | case 3: |
15106 | | // op: X2 |
15107 | 0 | return 32; |
15108 | 0 | case 1: |
15109 | | // op: B2 |
15110 | 0 | return 28; |
15111 | 0 | case 2: |
15112 | | // op: D2 |
15113 | 0 | return 16; |
15114 | 0 | case 4: |
15115 | | // op: M3 |
15116 | 0 | return 12; |
15117 | 0 | } |
15118 | 0 | break; |
15119 | 0 | } |
15120 | 0 | case SystemZ::VL: |
15121 | 0 | case SystemZ::VLBRF: |
15122 | 0 | case SystemZ::VLBRG: |
15123 | 0 | case SystemZ::VLBRH: |
15124 | 0 | case SystemZ::VLBRQ: |
15125 | 0 | case SystemZ::VLBRREPF: |
15126 | 0 | case SystemZ::VLBRREPG: |
15127 | 0 | case SystemZ::VLBRREPH: |
15128 | 0 | case SystemZ::VLERF: |
15129 | 0 | case SystemZ::VLERG: |
15130 | 0 | case SystemZ::VLERH: |
15131 | 0 | case SystemZ::VLLEBRZE: |
15132 | 0 | case SystemZ::VLLEBRZF: |
15133 | 0 | case SystemZ::VLLEBRZG: |
15134 | 0 | case SystemZ::VLLEBRZH: |
15135 | 0 | case SystemZ::VLLEZB: |
15136 | 0 | case SystemZ::VLLEZF: |
15137 | 0 | case SystemZ::VLLEZG: |
15138 | 0 | case SystemZ::VLLEZH: |
15139 | 0 | case SystemZ::VLLEZLF: |
15140 | 0 | case SystemZ::VLREPB: |
15141 | 0 | case SystemZ::VLREPF: |
15142 | 0 | case SystemZ::VLREPG: |
15143 | 0 | case SystemZ::VLREPH: |
15144 | 0 | case SystemZ::VST: |
15145 | 0 | case SystemZ::VSTBRF: |
15146 | 0 | case SystemZ::VSTBRG: |
15147 | 0 | case SystemZ::VSTBRH: |
15148 | 0 | case SystemZ::VSTBRQ: |
15149 | 0 | case SystemZ::VSTERF: |
15150 | 0 | case SystemZ::VSTERG: |
15151 | 0 | case SystemZ::VSTERH: { |
15152 | 0 | switch (OpNum) { |
15153 | 0 | case 0: |
15154 | | // op: V1 |
15155 | 0 | return 11; |
15156 | 0 | case 3: |
15157 | | // op: X2 |
15158 | 0 | return 32; |
15159 | 0 | case 1: |
15160 | | // op: B2 |
15161 | 0 | return 28; |
15162 | 0 | case 2: |
15163 | | // op: D2 |
15164 | 0 | return 16; |
15165 | 0 | } |
15166 | 0 | break; |
15167 | 0 | } |
15168 | 0 | case SystemZ::VGEF: |
15169 | 0 | case SystemZ::VGEG: { |
15170 | 0 | switch (OpNum) { |
15171 | 0 | case 0: |
15172 | | // op: V1 |
15173 | 0 | return 11; |
15174 | 0 | case 4: |
15175 | | // op: V2 |
15176 | 0 | return 10; |
15177 | 0 | case 2: |
15178 | | // op: B2 |
15179 | 0 | return 28; |
15180 | 0 | case 3: |
15181 | | // op: D2 |
15182 | 0 | return 16; |
15183 | 0 | case 5: |
15184 | | // op: M3 |
15185 | 0 | return 12; |
15186 | 0 | } |
15187 | 0 | break; |
15188 | 0 | } |
15189 | 0 | case SystemZ::VLEB: |
15190 | 0 | case SystemZ::VLEBRF: |
15191 | 0 | case SystemZ::VLEBRG: |
15192 | 0 | case SystemZ::VLEBRH: |
15193 | 0 | case SystemZ::VLEF: |
15194 | 0 | case SystemZ::VLEG: |
15195 | 0 | case SystemZ::VLEH: { |
15196 | 0 | switch (OpNum) { |
15197 | 0 | case 0: |
15198 | | // op: V1 |
15199 | 0 | return 11; |
15200 | 0 | case 4: |
15201 | | // op: X2 |
15202 | 0 | return 32; |
15203 | 0 | case 2: |
15204 | | // op: B2 |
15205 | 0 | return 28; |
15206 | 0 | case 3: |
15207 | | // op: D2 |
15208 | 0 | return 16; |
15209 | 0 | case 5: |
15210 | | // op: M3 |
15211 | 0 | return 12; |
15212 | 0 | } |
15213 | 0 | break; |
15214 | 0 | } |
15215 | 0 | case SystemZ::VONE: |
15216 | 0 | case SystemZ::VZERO: { |
15217 | 0 | switch (OpNum) { |
15218 | 0 | case 0: |
15219 | | // op: V1 |
15220 | 0 | return 11; |
15221 | 0 | } |
15222 | 0 | break; |
15223 | 0 | } |
15224 | 0 | case SystemZ::VLRL: |
15225 | 0 | case SystemZ::VPKZ: |
15226 | 0 | case SystemZ::VSTRL: |
15227 | 0 | case SystemZ::VUPKZ: { |
15228 | 0 | switch (OpNum) { |
15229 | 0 | case 0: |
15230 | | // op: V1 |
15231 | 0 | return 8; |
15232 | 0 | case 1: |
15233 | | // op: B2 |
15234 | 0 | return 28; |
15235 | 0 | case 2: |
15236 | | // op: D2 |
15237 | 0 | return 16; |
15238 | 0 | case 3: |
15239 | | // op: I3 |
15240 | 0 | return 32; |
15241 | 0 | } |
15242 | 0 | break; |
15243 | 0 | } |
15244 | 0 | case SystemZ::VLRLR: |
15245 | 0 | case SystemZ::VSTRLR: { |
15246 | 0 | switch (OpNum) { |
15247 | 0 | case 0: |
15248 | | // op: V1 |
15249 | 0 | return 8; |
15250 | 0 | case 2: |
15251 | | // op: B2 |
15252 | 0 | return 28; |
15253 | 0 | case 3: |
15254 | | // op: D2 |
15255 | 0 | return 16; |
15256 | 0 | case 1: |
15257 | | // op: R3 |
15258 | 0 | return 32; |
15259 | 0 | } |
15260 | 0 | break; |
15261 | 0 | } |
15262 | 0 | case SystemZ::InsnE: { |
15263 | 0 | switch (OpNum) { |
15264 | 0 | case 0: |
15265 | | // op: enc |
15266 | 0 | return 0; |
15267 | 0 | } |
15268 | 0 | break; |
15269 | 0 | } |
15270 | 0 | case SystemZ::InsnSI: { |
15271 | 0 | switch (OpNum) { |
15272 | 0 | case 1: |
15273 | | // op: B1 |
15274 | 0 | return 12; |
15275 | 0 | case 2: |
15276 | | // op: D1 |
15277 | 0 | return 0; |
15278 | 0 | case 3: |
15279 | | // op: I2 |
15280 | 0 | return 16; |
15281 | 0 | case 0: |
15282 | | // op: enc |
15283 | 0 | return 24; |
15284 | 0 | } |
15285 | 0 | break; |
15286 | 0 | } |
15287 | 0 | case SystemZ::LPD: |
15288 | 0 | case SystemZ::LPDG: { |
15289 | 0 | switch (OpNum) { |
15290 | 0 | case 1: |
15291 | | // op: B1 |
15292 | 0 | return 28; |
15293 | 0 | case 2: |
15294 | | // op: D1 |
15295 | 0 | return 16; |
15296 | 0 | case 3: |
15297 | | // op: B2 |
15298 | 0 | return 12; |
15299 | 0 | case 4: |
15300 | | // op: D2 |
15301 | 0 | return 0; |
15302 | 0 | case 0: |
15303 | | // op: R3 |
15304 | 0 | return 36; |
15305 | 0 | } |
15306 | 0 | break; |
15307 | 0 | } |
15308 | 0 | case SystemZ::InsnSSE: { |
15309 | 0 | switch (OpNum) { |
15310 | 0 | case 1: |
15311 | | // op: B1 |
15312 | 0 | return 28; |
15313 | 0 | case 2: |
15314 | | // op: D1 |
15315 | 0 | return 16; |
15316 | 0 | case 3: |
15317 | | // op: B2 |
15318 | 0 | return 12; |
15319 | 0 | case 4: |
15320 | | // op: D2 |
15321 | 0 | return 0; |
15322 | 0 | case 0: |
15323 | | // op: enc |
15324 | 0 | return 32; |
15325 | 0 | } |
15326 | 0 | break; |
15327 | 0 | } |
15328 | 0 | case SystemZ::InsnSSF: { |
15329 | 0 | switch (OpNum) { |
15330 | 0 | case 1: |
15331 | | // op: B1 |
15332 | 0 | return 28; |
15333 | 0 | case 2: |
15334 | | // op: D1 |
15335 | 0 | return 16; |
15336 | 0 | case 3: |
15337 | | // op: B2 |
15338 | 0 | return 12; |
15339 | 0 | case 4: |
15340 | | // op: D2 |
15341 | 0 | return 0; |
15342 | 0 | case 5: |
15343 | | // op: R3 |
15344 | 0 | return 36; |
15345 | 0 | case 0: |
15346 | | // op: enc |
15347 | 0 | return 32; |
15348 | 0 | } |
15349 | 0 | break; |
15350 | 0 | } |
15351 | 0 | case SystemZ::InsnSIL: { |
15352 | 0 | switch (OpNum) { |
15353 | 0 | case 1: |
15354 | | // op: B1 |
15355 | 0 | return 28; |
15356 | 0 | case 2: |
15357 | | // op: D1 |
15358 | 0 | return 16; |
15359 | 0 | case 3: |
15360 | | // op: I2 |
15361 | 0 | return 0; |
15362 | 0 | case 0: |
15363 | | // op: enc |
15364 | 0 | return 32; |
15365 | 0 | } |
15366 | 0 | break; |
15367 | 0 | } |
15368 | 0 | case SystemZ::InsnSIY: { |
15369 | 0 | switch (OpNum) { |
15370 | 0 | case 1: |
15371 | | // op: B1 |
15372 | 0 | return 28; |
15373 | 0 | case 2: |
15374 | | // op: D1 |
15375 | 0 | return 8; |
15376 | 0 | case 3: |
15377 | | // op: I2 |
15378 | 0 | return 32; |
15379 | 0 | case 0: |
15380 | | // op: enc |
15381 | 0 | return 0; |
15382 | 0 | } |
15383 | 0 | break; |
15384 | 0 | } |
15385 | 0 | case SystemZ::InsnS: { |
15386 | 0 | switch (OpNum) { |
15387 | 0 | case 1: |
15388 | | // op: B2 |
15389 | 0 | return 12; |
15390 | 0 | case 2: |
15391 | | // op: D2 |
15392 | 0 | return 0; |
15393 | 0 | case 0: |
15394 | | // op: enc |
15395 | 0 | return 16; |
15396 | 0 | } |
15397 | 0 | break; |
15398 | 0 | } |
15399 | 0 | case SystemZ::BRC: { |
15400 | 0 | switch (OpNum) { |
15401 | 0 | case 1: |
15402 | | // op: M1 |
15403 | 0 | return 20; |
15404 | 0 | case 2: |
15405 | | // op: RI2 |
15406 | 0 | return 0; |
15407 | 0 | } |
15408 | 0 | break; |
15409 | 0 | } |
15410 | 0 | case SystemZ::BC: { |
15411 | 0 | switch (OpNum) { |
15412 | 0 | case 1: |
15413 | | // op: M1 |
15414 | 0 | return 20; |
15415 | 0 | case 4: |
15416 | | // op: X2 |
15417 | 0 | return 16; |
15418 | 0 | case 2: |
15419 | | // op: B2 |
15420 | 0 | return 12; |
15421 | 0 | case 3: |
15422 | | // op: D2 |
15423 | 0 | return 0; |
15424 | 0 | } |
15425 | 0 | break; |
15426 | 0 | } |
15427 | 0 | case SystemZ::BRCL: { |
15428 | 0 | switch (OpNum) { |
15429 | 0 | case 1: |
15430 | | // op: M1 |
15431 | 0 | return 36; |
15432 | 0 | case 2: |
15433 | | // op: RI2 |
15434 | 0 | return 0; |
15435 | 0 | } |
15436 | 0 | break; |
15437 | 0 | } |
15438 | 0 | case SystemZ::BIC: { |
15439 | 0 | switch (OpNum) { |
15440 | 0 | case 1: |
15441 | | // op: M1 |
15442 | 0 | return 36; |
15443 | 0 | case 4: |
15444 | | // op: X2 |
15445 | 0 | return 32; |
15446 | 0 | case 2: |
15447 | | // op: B2 |
15448 | 0 | return 28; |
15449 | 0 | case 3: |
15450 | | // op: D2 |
15451 | 0 | return 8; |
15452 | 0 | } |
15453 | 0 | break; |
15454 | 0 | } |
15455 | 0 | case SystemZ::InsnRXF: { |
15456 | 0 | switch (OpNum) { |
15457 | 0 | case 1: |
15458 | | // op: R1 |
15459 | 0 | return 12; |
15460 | 0 | case 2: |
15461 | | // op: R3 |
15462 | 0 | return 36; |
15463 | 0 | case 5: |
15464 | | // op: X2 |
15465 | 0 | return 32; |
15466 | 0 | case 3: |
15467 | | // op: B2 |
15468 | 0 | return 28; |
15469 | 0 | case 4: |
15470 | | // op: D2 |
15471 | 0 | return 16; |
15472 | 0 | case 0: |
15473 | | // op: enc |
15474 | 0 | return 0; |
15475 | 0 | } |
15476 | 0 | break; |
15477 | 0 | } |
15478 | 0 | case SystemZ::InsnRI: { |
15479 | 0 | switch (OpNum) { |
15480 | 0 | case 1: |
15481 | | // op: R1 |
15482 | 0 | return 20; |
15483 | 0 | case 2: |
15484 | | // op: I2 |
15485 | 0 | return 0; |
15486 | 0 | case 0: |
15487 | | // op: enc |
15488 | 0 | return 16; |
15489 | 0 | } |
15490 | 0 | break; |
15491 | 0 | } |
15492 | 0 | case SystemZ::InsnRS: { |
15493 | 0 | switch (OpNum) { |
15494 | 0 | case 1: |
15495 | | // op: R1 |
15496 | 0 | return 20; |
15497 | 0 | case 2: |
15498 | | // op: R3 |
15499 | 0 | return 16; |
15500 | 0 | case 3: |
15501 | | // op: B2 |
15502 | 0 | return 12; |
15503 | 0 | case 4: |
15504 | | // op: D2 |
15505 | 0 | return 0; |
15506 | 0 | case 0: |
15507 | | // op: enc |
15508 | 0 | return 24; |
15509 | 0 | } |
15510 | 0 | break; |
15511 | 0 | } |
15512 | 0 | case SystemZ::InsnRSI: { |
15513 | 0 | switch (OpNum) { |
15514 | 0 | case 1: |
15515 | | // op: R1 |
15516 | 0 | return 20; |
15517 | 0 | case 2: |
15518 | | // op: R3 |
15519 | 0 | return 16; |
15520 | 0 | case 3: |
15521 | | // op: RI2 |
15522 | 0 | return 0; |
15523 | 0 | case 0: |
15524 | | // op: enc |
15525 | 0 | return 24; |
15526 | 0 | } |
15527 | 0 | break; |
15528 | 0 | } |
15529 | 0 | case SystemZ::InsnRX: { |
15530 | 0 | switch (OpNum) { |
15531 | 0 | case 1: |
15532 | | // op: R1 |
15533 | 0 | return 20; |
15534 | 0 | case 4: |
15535 | | // op: X2 |
15536 | 0 | return 16; |
15537 | 0 | case 2: |
15538 | | // op: B2 |
15539 | 0 | return 12; |
15540 | 0 | case 3: |
15541 | | // op: D2 |
15542 | 0 | return 0; |
15543 | 0 | case 0: |
15544 | | // op: enc |
15545 | 0 | return 24; |
15546 | 0 | } |
15547 | 0 | break; |
15548 | 0 | } |
15549 | 0 | case SystemZ::InsnRIL: |
15550 | 0 | case SystemZ::InsnRILU: { |
15551 | 0 | switch (OpNum) { |
15552 | 0 | case 1: |
15553 | | // op: R1 |
15554 | 0 | return 36; |
15555 | 0 | case 2: |
15556 | | // op: I2 |
15557 | 0 | return 0; |
15558 | 0 | case 0: |
15559 | | // op: enc |
15560 | 0 | return 32; |
15561 | 0 | } |
15562 | 0 | break; |
15563 | 0 | } |
15564 | 0 | case SystemZ::InsnRIS: { |
15565 | 0 | switch (OpNum) { |
15566 | 0 | case 1: |
15567 | | // op: R1 |
15568 | 0 | return 36; |
15569 | 0 | case 2: |
15570 | | // op: I2 |
15571 | 0 | return 8; |
15572 | 0 | case 3: |
15573 | | // op: M3 |
15574 | 0 | return 32; |
15575 | 0 | case 4: |
15576 | | // op: B4 |
15577 | 0 | return 28; |
15578 | 0 | case 5: |
15579 | | // op: D4 |
15580 | 0 | return 16; |
15581 | 0 | case 0: |
15582 | | // op: enc |
15583 | 0 | return 0; |
15584 | 0 | } |
15585 | 0 | break; |
15586 | 0 | } |
15587 | 0 | case SystemZ::InsnRRS: { |
15588 | 0 | switch (OpNum) { |
15589 | 0 | case 1: |
15590 | | // op: R1 |
15591 | 0 | return 36; |
15592 | 0 | case 2: |
15593 | | // op: R2 |
15594 | 0 | return 32; |
15595 | 0 | case 3: |
15596 | | // op: M3 |
15597 | 0 | return 12; |
15598 | 0 | case 4: |
15599 | | // op: B4 |
15600 | 0 | return 28; |
15601 | 0 | case 5: |
15602 | | // op: D4 |
15603 | 0 | return 16; |
15604 | 0 | case 0: |
15605 | | // op: enc |
15606 | 0 | return 0; |
15607 | 0 | } |
15608 | 0 | break; |
15609 | 0 | } |
15610 | 0 | case SystemZ::InsnRSE: { |
15611 | 0 | switch (OpNum) { |
15612 | 0 | case 1: |
15613 | | // op: R1 |
15614 | 0 | return 36; |
15615 | 0 | case 2: |
15616 | | // op: R3 |
15617 | 0 | return 32; |
15618 | 0 | case 3: |
15619 | | // op: B2 |
15620 | 0 | return 28; |
15621 | 0 | case 4: |
15622 | | // op: D2 |
15623 | 0 | return 16; |
15624 | 0 | case 0: |
15625 | | // op: enc |
15626 | 0 | return 0; |
15627 | 0 | } |
15628 | 0 | break; |
15629 | 0 | } |
15630 | 0 | case SystemZ::InsnRSY: { |
15631 | 0 | switch (OpNum) { |
15632 | 0 | case 1: |
15633 | | // op: R1 |
15634 | 0 | return 36; |
15635 | 0 | case 2: |
15636 | | // op: R3 |
15637 | 0 | return 32; |
15638 | 0 | case 3: |
15639 | | // op: B2 |
15640 | 0 | return 28; |
15641 | 0 | case 4: |
15642 | | // op: D2 |
15643 | 0 | return 8; |
15644 | 0 | case 0: |
15645 | | // op: enc |
15646 | 0 | return 0; |
15647 | 0 | } |
15648 | 0 | break; |
15649 | 0 | } |
15650 | 0 | case SystemZ::InsnRIE: { |
15651 | 0 | switch (OpNum) { |
15652 | 0 | case 1: |
15653 | | // op: R1 |
15654 | 0 | return 36; |
15655 | 0 | case 2: |
15656 | | // op: R3 |
15657 | 0 | return 32; |
15658 | 0 | case 3: |
15659 | | // op: I2 |
15660 | 0 | return 16; |
15661 | 0 | case 0: |
15662 | | // op: enc |
15663 | 0 | return 0; |
15664 | 0 | } |
15665 | 0 | break; |
15666 | 0 | } |
15667 | 0 | case SystemZ::InsnVRS: { |
15668 | 0 | switch (OpNum) { |
15669 | 0 | case 1: |
15670 | | // op: R1 |
15671 | 0 | return 36; |
15672 | 0 | case 3: |
15673 | | // op: B2 |
15674 | 0 | return 28; |
15675 | 0 | case 4: |
15676 | | // op: D2 |
15677 | 0 | return 16; |
15678 | 0 | case 2: |
15679 | | // op: V3 |
15680 | 0 | return 10; |
15681 | 0 | case 5: |
15682 | | // op: M4 |
15683 | 0 | return 12; |
15684 | 0 | case 0: |
15685 | | // op: enc |
15686 | 0 | return 0; |
15687 | 0 | } |
15688 | 0 | break; |
15689 | 0 | } |
15690 | 0 | case SystemZ::InsnRXE: { |
15691 | 0 | switch (OpNum) { |
15692 | 0 | case 1: |
15693 | | // op: R1 |
15694 | 0 | return 36; |
15695 | 0 | case 4: |
15696 | | // op: X2 |
15697 | 0 | return 32; |
15698 | 0 | case 2: |
15699 | | // op: B2 |
15700 | 0 | return 28; |
15701 | 0 | case 3: |
15702 | | // op: D2 |
15703 | 0 | return 16; |
15704 | 0 | case 0: |
15705 | | // op: enc |
15706 | 0 | return 0; |
15707 | 0 | } |
15708 | 0 | break; |
15709 | 0 | } |
15710 | 0 | case SystemZ::InsnRXY: { |
15711 | 0 | switch (OpNum) { |
15712 | 0 | case 1: |
15713 | | // op: R1 |
15714 | 0 | return 36; |
15715 | 0 | case 4: |
15716 | | // op: X2 |
15717 | 0 | return 32; |
15718 | 0 | case 2: |
15719 | | // op: B2 |
15720 | 0 | return 28; |
15721 | 0 | case 3: |
15722 | | // op: D2 |
15723 | 0 | return 8; |
15724 | 0 | case 0: |
15725 | | // op: enc |
15726 | 0 | return 0; |
15727 | 0 | } |
15728 | 0 | break; |
15729 | 0 | } |
15730 | 0 | case SystemZ::TRTE: |
15731 | 0 | case SystemZ::TRTRE: { |
15732 | 0 | switch (OpNum) { |
15733 | 0 | case 1: |
15734 | | // op: R1 |
15735 | 0 | return 4; |
15736 | 0 | case 0: |
15737 | | // op: R2 |
15738 | 0 | return 0; |
15739 | 0 | case 3: |
15740 | | // op: M3 |
15741 | 0 | return 12; |
15742 | 0 | } |
15743 | 0 | break; |
15744 | 0 | } |
15745 | 0 | case SystemZ::KDSA: |
15746 | 0 | case SystemZ::KIMD: |
15747 | 0 | case SystemZ::KLMD: |
15748 | 0 | case SystemZ::KMAC: |
15749 | 0 | case SystemZ::PFMF: |
15750 | 0 | case SystemZ::TRTEOpt: |
15751 | 0 | case SystemZ::TRTREOpt: { |
15752 | 0 | switch (OpNum) { |
15753 | 0 | case 1: |
15754 | | // op: R1 |
15755 | 0 | return 4; |
15756 | 0 | case 0: |
15757 | | // op: R2 |
15758 | 0 | return 0; |
15759 | 0 | } |
15760 | 0 | break; |
15761 | 0 | } |
15762 | 0 | case SystemZ::InsnRRE: { |
15763 | 0 | switch (OpNum) { |
15764 | 0 | case 1: |
15765 | | // op: R1 |
15766 | 0 | return 4; |
15767 | 0 | case 2: |
15768 | | // op: R2 |
15769 | 0 | return 0; |
15770 | 0 | case 0: |
15771 | | // op: enc |
15772 | 0 | return 16; |
15773 | 0 | } |
15774 | 0 | break; |
15775 | 0 | } |
15776 | 0 | case SystemZ::InsnRR: { |
15777 | 0 | switch (OpNum) { |
15778 | 0 | case 1: |
15779 | | // op: R1 |
15780 | 0 | return 4; |
15781 | 0 | case 2: |
15782 | | // op: R2 |
15783 | 0 | return 0; |
15784 | 0 | case 0: |
15785 | | // op: enc |
15786 | 0 | return 8; |
15787 | 0 | } |
15788 | 0 | break; |
15789 | 0 | } |
15790 | 0 | case SystemZ::InsnRRF: { |
15791 | 0 | switch (OpNum) { |
15792 | 0 | case 1: |
15793 | | // op: R1 |
15794 | 0 | return 4; |
15795 | 0 | case 2: |
15796 | | // op: R2 |
15797 | 0 | return 0; |
15798 | 0 | case 3: |
15799 | | // op: R3 |
15800 | 0 | return 12; |
15801 | 0 | case 4: |
15802 | | // op: M4 |
15803 | 0 | return 8; |
15804 | 0 | case 0: |
15805 | | // op: enc |
15806 | 0 | return 16; |
15807 | 0 | } |
15808 | 0 | break; |
15809 | 0 | } |
15810 | 0 | case SystemZ::BCR: { |
15811 | 0 | switch (OpNum) { |
15812 | 0 | case 1: |
15813 | | // op: R1 |
15814 | 0 | return 4; |
15815 | 0 | case 2: |
15816 | | // op: R2 |
15817 | 0 | return 0; |
15818 | 0 | } |
15819 | 0 | break; |
15820 | 0 | } |
15821 | 0 | case SystemZ::InsnVRI: { |
15822 | 0 | switch (OpNum) { |
15823 | 0 | case 1: |
15824 | | // op: V1 |
15825 | 0 | return 11; |
15826 | 0 | case 2: |
15827 | | // op: V2 |
15828 | 0 | return 10; |
15829 | 0 | case 3: |
15830 | | // op: I3 |
15831 | 0 | return 20; |
15832 | 0 | case 4: |
15833 | | // op: M4 |
15834 | 0 | return 12; |
15835 | 0 | case 5: |
15836 | | // op: M5 |
15837 | 0 | return 16; |
15838 | 0 | case 0: |
15839 | | // op: enc |
15840 | 0 | return 0; |
15841 | 0 | } |
15842 | 0 | break; |
15843 | 0 | } |
15844 | 0 | case SystemZ::InsnVRR: { |
15845 | 0 | switch (OpNum) { |
15846 | 0 | case 1: |
15847 | | // op: V1 |
15848 | 0 | return 11; |
15849 | 0 | case 2: |
15850 | | // op: V2 |
15851 | 0 | return 10; |
15852 | 0 | case 3: |
15853 | | // op: V3 |
15854 | 0 | return 9; |
15855 | 0 | case 4: |
15856 | | // op: M4 |
15857 | 0 | return 12; |
15858 | 0 | case 5: |
15859 | | // op: M5 |
15860 | 0 | return 16; |
15861 | 0 | case 6: |
15862 | | // op: M6 |
15863 | 0 | return 20; |
15864 | 0 | case 0: |
15865 | | // op: enc |
15866 | 0 | return 0; |
15867 | 0 | } |
15868 | 0 | break; |
15869 | 0 | } |
15870 | 0 | case SystemZ::InsnVRV: { |
15871 | 0 | switch (OpNum) { |
15872 | 0 | case 1: |
15873 | | // op: V1 |
15874 | 0 | return 11; |
15875 | 0 | case 4: |
15876 | | // op: V2 |
15877 | 0 | return 10; |
15878 | 0 | case 2: |
15879 | | // op: B2 |
15880 | 0 | return 28; |
15881 | 0 | case 3: |
15882 | | // op: D2 |
15883 | 0 | return 16; |
15884 | 0 | case 5: |
15885 | | // op: M3 |
15886 | 0 | return 12; |
15887 | 0 | case 0: |
15888 | | // op: enc |
15889 | 0 | return 0; |
15890 | 0 | } |
15891 | 0 | break; |
15892 | 0 | } |
15893 | 0 | case SystemZ::InsnVRX: { |
15894 | 0 | switch (OpNum) { |
15895 | 0 | case 1: |
15896 | | // op: V1 |
15897 | 0 | return 11; |
15898 | 0 | case 4: |
15899 | | // op: X2 |
15900 | 0 | return 32; |
15901 | 0 | case 2: |
15902 | | // op: B2 |
15903 | 0 | return 28; |
15904 | 0 | case 3: |
15905 | | // op: D2 |
15906 | 0 | return 16; |
15907 | 0 | case 5: |
15908 | | // op: M3 |
15909 | 0 | return 12; |
15910 | 0 | case 0: |
15911 | | // op: enc |
15912 | 0 | return 0; |
15913 | 0 | } |
15914 | 0 | break; |
15915 | 0 | } |
15916 | 0 | case SystemZ::InsnVSI: { |
15917 | 0 | switch (OpNum) { |
15918 | 0 | case 1: |
15919 | | // op: V1 |
15920 | 0 | return 8; |
15921 | 0 | case 2: |
15922 | | // op: B2 |
15923 | 0 | return 28; |
15924 | 0 | case 3: |
15925 | | // op: D2 |
15926 | 0 | return 16; |
15927 | 0 | case 4: |
15928 | | // op: I3 |
15929 | 0 | return 32; |
15930 | 0 | case 0: |
15931 | | // op: enc |
15932 | 0 | return 0; |
15933 | 0 | } |
15934 | 0 | break; |
15935 | 0 | } |
15936 | 0 | case SystemZ::MVCK: |
15937 | 0 | case SystemZ::MVCP: |
15938 | 0 | case SystemZ::MVCS: { |
15939 | 0 | switch (OpNum) { |
15940 | 0 | case 2: |
15941 | | // op: R1 |
15942 | 0 | return 36; |
15943 | 0 | case 0: |
15944 | | // op: B1 |
15945 | 0 | return 28; |
15946 | 0 | case 1: |
15947 | | // op: D1 |
15948 | 0 | return 16; |
15949 | 0 | case 3: |
15950 | | // op: B2 |
15951 | 0 | return 12; |
15952 | 0 | case 4: |
15953 | | // op: D2 |
15954 | 0 | return 0; |
15955 | 0 | case 5: |
15956 | | // op: R3 |
15957 | 0 | return 32; |
15958 | 0 | } |
15959 | 0 | break; |
15960 | 0 | } |
15961 | 0 | case SystemZ::B: |
15962 | 0 | case SystemZ::BAsmE: |
15963 | 0 | case SystemZ::BAsmH: |
15964 | 0 | case SystemZ::BAsmHE: |
15965 | 0 | case SystemZ::BAsmL: |
15966 | 0 | case SystemZ::BAsmLE: |
15967 | 0 | case SystemZ::BAsmLH: |
15968 | 0 | case SystemZ::BAsmM: |
15969 | 0 | case SystemZ::BAsmNE: |
15970 | 0 | case SystemZ::BAsmNH: |
15971 | 0 | case SystemZ::BAsmNHE: |
15972 | 0 | case SystemZ::BAsmNL: |
15973 | 0 | case SystemZ::BAsmNLE: |
15974 | 0 | case SystemZ::BAsmNLH: |
15975 | 0 | case SystemZ::BAsmNM: |
15976 | 0 | case SystemZ::BAsmNO: |
15977 | 0 | case SystemZ::BAsmNP: |
15978 | 0 | case SystemZ::BAsmNZ: |
15979 | 0 | case SystemZ::BAsmO: |
15980 | 0 | case SystemZ::BAsmP: |
15981 | 0 | case SystemZ::BAsmZ: { |
15982 | 0 | switch (OpNum) { |
15983 | 0 | case 2: |
15984 | | // op: X2 |
15985 | 0 | return 16; |
15986 | 0 | case 0: |
15987 | | // op: B2 |
15988 | 0 | return 12; |
15989 | 0 | case 1: |
15990 | | // op: D2 |
15991 | 0 | return 0; |
15992 | 0 | } |
15993 | 0 | break; |
15994 | 0 | } |
15995 | 0 | case SystemZ::BI: |
15996 | 0 | case SystemZ::BIAsmE: |
15997 | 0 | case SystemZ::BIAsmH: |
15998 | 0 | case SystemZ::BIAsmHE: |
15999 | 0 | case SystemZ::BIAsmL: |
16000 | 0 | case SystemZ::BIAsmLE: |
16001 | 0 | case SystemZ::BIAsmLH: |
16002 | 0 | case SystemZ::BIAsmM: |
16003 | 0 | case SystemZ::BIAsmNE: |
16004 | 0 | case SystemZ::BIAsmNH: |
16005 | 0 | case SystemZ::BIAsmNHE: |
16006 | 0 | case SystemZ::BIAsmNL: |
16007 | 0 | case SystemZ::BIAsmNLE: |
16008 | 0 | case SystemZ::BIAsmNLH: |
16009 | 0 | case SystemZ::BIAsmNM: |
16010 | 0 | case SystemZ::BIAsmNO: |
16011 | 0 | case SystemZ::BIAsmNP: |
16012 | 0 | case SystemZ::BIAsmNZ: |
16013 | 0 | case SystemZ::BIAsmO: |
16014 | 0 | case SystemZ::BIAsmP: |
16015 | 0 | case SystemZ::BIAsmZ: { |
16016 | 0 | switch (OpNum) { |
16017 | 0 | case 2: |
16018 | | // op: X2 |
16019 | 0 | return 32; |
16020 | 0 | case 0: |
16021 | | // op: B2 |
16022 | 0 | return 28; |
16023 | 0 | case 1: |
16024 | | // op: D2 |
16025 | 0 | return 8; |
16026 | 0 | } |
16027 | 0 | break; |
16028 | 0 | } |
16029 | 0 | case SystemZ::InsnSS: { |
16030 | 0 | switch (OpNum) { |
16031 | 0 | case 3: |
16032 | | // op: R1 |
16033 | 0 | return 36; |
16034 | 0 | case 1: |
16035 | | // op: B1 |
16036 | 0 | return 28; |
16037 | 0 | case 2: |
16038 | | // op: D1 |
16039 | 0 | return 16; |
16040 | 0 | case 4: |
16041 | | // op: B2 |
16042 | 0 | return 12; |
16043 | 0 | case 5: |
16044 | | // op: D2 |
16045 | 0 | return 0; |
16046 | 0 | case 6: |
16047 | | // op: R3 |
16048 | 0 | return 32; |
16049 | 0 | case 0: |
16050 | | // op: enc |
16051 | 0 | return 40; |
16052 | 0 | } |
16053 | 0 | break; |
16054 | 0 | } |
16055 | 0 | } |
16056 | 0 | std::string msg; |
16057 | 0 | raw_string_ostream Msg(msg); |
16058 | 0 | Msg << "Not supported instr[opcode]: " << MI << "[" << OpNum << "]"; |
16059 | 0 | report_fatal_error(Msg.str().c_str()); |
16060 | 0 | } |
16061 | | |
16062 | | #endif // GET_OPERAND_BIT_OFFSET |
16063 | | |