/src/build/lib/Target/VE/VEGenAsmMatcher.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Assembly Matcher Source Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* From: VE.td *| |
7 | | |* *| |
8 | | \*===----------------------------------------------------------------------===*/ |
9 | | |
10 | | |
11 | | #ifdef GET_ASSEMBLER_HEADER |
12 | | #undef GET_ASSEMBLER_HEADER |
13 | | // This should be included into the middle of the declaration of |
14 | | // your subclasses implementation of MCTargetAsmParser. |
15 | | FeatureBitset ComputeAvailableFeatures(const FeatureBitset &FB) const; |
16 | | void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
17 | | const OperandVector &Operands); |
18 | | void convertToMapAndConstraints(unsigned Kind, |
19 | | const OperandVector &Operands) override; |
20 | | unsigned MatchInstructionImpl(const OperandVector &Operands, |
21 | | MCInst &Inst, |
22 | | uint64_t &ErrorInfo, |
23 | | FeatureBitset &MissingFeatures, |
24 | | bool matchingInlineAsm, |
25 | | unsigned VariantID = 0); |
26 | | unsigned MatchInstructionImpl(const OperandVector &Operands, |
27 | | MCInst &Inst, |
28 | | uint64_t &ErrorInfo, |
29 | | bool matchingInlineAsm, |
30 | 0 | unsigned VariantID = 0) { |
31 | 0 | FeatureBitset MissingFeatures; |
32 | 0 | return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, |
33 | 0 | matchingInlineAsm, VariantID); |
34 | 0 | } |
35 | | |
36 | | ParseStatus MatchOperandParserImpl( |
37 | | OperandVector &Operands, |
38 | | StringRef Mnemonic, |
39 | | bool ParseForAllFeatures = false); |
40 | | ParseStatus tryCustomParseOperand( |
41 | | OperandVector &Operands, |
42 | | unsigned MCK); |
43 | | |
44 | | #endif // GET_ASSEMBLER_HEADER |
45 | | |
46 | | |
47 | | #ifdef GET_OPERAND_DIAGNOSTIC_TYPES |
48 | | #undef GET_OPERAND_DIAGNOSTIC_TYPES |
49 | | |
50 | | #endif // GET_OPERAND_DIAGNOSTIC_TYPES |
51 | | |
52 | | |
53 | | #ifdef GET_REGISTER_MATCHER |
54 | | #undef GET_REGISTER_MATCHER |
55 | | |
56 | | // Bits for subtarget features that participate in instruction matching. |
57 | | enum SubtargetFeatureBits : uint8_t { |
58 | | }; |
59 | | |
60 | 0 | static unsigned MatchRegisterName(StringRef Name) { |
61 | 0 | switch (Name.size()) { |
62 | 0 | default: break; |
63 | 0 | case 2: // 32 strings to match. |
64 | 0 | switch (Name[0]) { |
65 | 0 | default: break; |
66 | 0 | case 'i': // 1 string to match. |
67 | 0 | if (Name[1] != 'c') |
68 | 0 | break; |
69 | 0 | return 1; // "ic" |
70 | 0 | case 'q': // 10 strings to match. |
71 | 0 | switch (Name[1]) { |
72 | 0 | default: break; |
73 | 0 | case '0': // 1 string to match. |
74 | 0 | return 27; // "q0" |
75 | 0 | case '1': // 1 string to match. |
76 | 0 | return 28; // "q1" |
77 | 0 | case '2': // 1 string to match. |
78 | 0 | return 29; // "q2" |
79 | 0 | case '3': // 1 string to match. |
80 | 0 | return 30; // "q3" |
81 | 0 | case '4': // 1 string to match. |
82 | 0 | return 31; // "q4" |
83 | 0 | case '5': // 1 string to match. |
84 | 0 | return 32; // "q5" |
85 | 0 | case '6': // 1 string to match. |
86 | 0 | return 33; // "q6" |
87 | 0 | case '7': // 1 string to match. |
88 | 0 | return 34; // "q7" |
89 | 0 | case '8': // 1 string to match. |
90 | 0 | return 35; // "q8" |
91 | 0 | case '9': // 1 string to match. |
92 | 0 | return 36; // "q9" |
93 | 0 | } |
94 | 0 | break; |
95 | 0 | case 's': // 10 strings to match. |
96 | 0 | switch (Name[1]) { |
97 | 0 | default: break; |
98 | 0 | case '0': // 1 string to match. |
99 | 0 | return 187; // "s0" |
100 | 0 | case '1': // 1 string to match. |
101 | 0 | return 188; // "s1" |
102 | 0 | case '2': // 1 string to match. |
103 | 0 | return 189; // "s2" |
104 | 0 | case '3': // 1 string to match. |
105 | 0 | return 190; // "s3" |
106 | 0 | case '4': // 1 string to match. |
107 | 0 | return 191; // "s4" |
108 | 0 | case '5': // 1 string to match. |
109 | 0 | return 192; // "s5" |
110 | 0 | case '6': // 1 string to match. |
111 | 0 | return 193; // "s6" |
112 | 0 | case '7': // 1 string to match. |
113 | 0 | return 194; // "s7" |
114 | 0 | case '8': // 1 string to match. |
115 | 0 | return 195; // "s8" |
116 | 0 | case '9': // 1 string to match. |
117 | 0 | return 196; // "s9" |
118 | 0 | } |
119 | 0 | break; |
120 | 0 | case 'v': // 11 strings to match. |
121 | 0 | switch (Name[1]) { |
122 | 0 | default: break; |
123 | 0 | case '0': // 1 string to match. |
124 | 0 | return 251; // "v0" |
125 | 0 | case '1': // 1 string to match. |
126 | 0 | return 252; // "v1" |
127 | 0 | case '2': // 1 string to match. |
128 | 0 | return 253; // "v2" |
129 | 0 | case '3': // 1 string to match. |
130 | 0 | return 254; // "v3" |
131 | 0 | case '4': // 1 string to match. |
132 | 0 | return 255; // "v4" |
133 | 0 | case '5': // 1 string to match. |
134 | 0 | return 256; // "v5" |
135 | 0 | case '6': // 1 string to match. |
136 | 0 | return 257; // "v6" |
137 | 0 | case '7': // 1 string to match. |
138 | 0 | return 258; // "v7" |
139 | 0 | case '8': // 1 string to match. |
140 | 0 | return 259; // "v8" |
141 | 0 | case '9': // 1 string to match. |
142 | 0 | return 260; // "v9" |
143 | 0 | case 'l': // 1 string to match. |
144 | 0 | return 7; // "vl" |
145 | 0 | } |
146 | 0 | break; |
147 | 0 | } |
148 | 0 | break; |
149 | 0 | case 3: // 164 strings to match. |
150 | 0 | switch (Name[0]) { |
151 | 0 | default: break; |
152 | 0 | case 'p': // 1 string to match. |
153 | 0 | if (memcmp(Name.data()+1, "sw", 2) != 0) |
154 | 0 | break; |
155 | 0 | return 3; // "psw" |
156 | 0 | case 'q': // 22 strings to match. |
157 | 0 | switch (Name[1]) { |
158 | 0 | default: break; |
159 | 0 | case '1': // 10 strings to match. |
160 | 0 | switch (Name[2]) { |
161 | 0 | default: break; |
162 | 0 | case '0': // 1 string to match. |
163 | 0 | return 37; // "q10" |
164 | 0 | case '1': // 1 string to match. |
165 | 0 | return 38; // "q11" |
166 | 0 | case '2': // 1 string to match. |
167 | 0 | return 39; // "q12" |
168 | 0 | case '3': // 1 string to match. |
169 | 0 | return 40; // "q13" |
170 | 0 | case '4': // 1 string to match. |
171 | 0 | return 41; // "q14" |
172 | 0 | case '5': // 1 string to match. |
173 | 0 | return 42; // "q15" |
174 | 0 | case '6': // 1 string to match. |
175 | 0 | return 43; // "q16" |
176 | 0 | case '7': // 1 string to match. |
177 | 0 | return 44; // "q17" |
178 | 0 | case '8': // 1 string to match. |
179 | 0 | return 45; // "q18" |
180 | 0 | case '9': // 1 string to match. |
181 | 0 | return 46; // "q19" |
182 | 0 | } |
183 | 0 | break; |
184 | 0 | case '2': // 10 strings to match. |
185 | 0 | switch (Name[2]) { |
186 | 0 | default: break; |
187 | 0 | case '0': // 1 string to match. |
188 | 0 | return 47; // "q20" |
189 | 0 | case '1': // 1 string to match. |
190 | 0 | return 48; // "q21" |
191 | 0 | case '2': // 1 string to match. |
192 | 0 | return 49; // "q22" |
193 | 0 | case '3': // 1 string to match. |
194 | 0 | return 50; // "q23" |
195 | 0 | case '4': // 1 string to match. |
196 | 0 | return 51; // "q24" |
197 | 0 | case '5': // 1 string to match. |
198 | 0 | return 52; // "q25" |
199 | 0 | case '6': // 1 string to match. |
200 | 0 | return 53; // "q26" |
201 | 0 | case '7': // 1 string to match. |
202 | 0 | return 54; // "q27" |
203 | 0 | case '8': // 1 string to match. |
204 | 0 | return 55; // "q28" |
205 | 0 | case '9': // 1 string to match. |
206 | 0 | return 56; // "q29" |
207 | 0 | } |
208 | 0 | break; |
209 | 0 | case '3': // 2 strings to match. |
210 | 0 | switch (Name[2]) { |
211 | 0 | default: break; |
212 | 0 | case '0': // 1 string to match. |
213 | 0 | return 57; // "q30" |
214 | 0 | case '1': // 1 string to match. |
215 | 0 | return 58; // "q31" |
216 | 0 | } |
217 | 0 | break; |
218 | 0 | } |
219 | 0 | break; |
220 | 0 | case 's': // 75 strings to match. |
221 | 0 | switch (Name[1]) { |
222 | 0 | default: break; |
223 | 0 | case '1': // 10 strings to match. |
224 | 0 | switch (Name[2]) { |
225 | 0 | default: break; |
226 | 0 | case '0': // 1 string to match. |
227 | 0 | return 197; // "s10" |
228 | 0 | case '1': // 1 string to match. |
229 | 0 | return 198; // "s11" |
230 | 0 | case '2': // 1 string to match. |
231 | 0 | return 199; // "s12" |
232 | 0 | case '3': // 1 string to match. |
233 | 0 | return 200; // "s13" |
234 | 0 | case '4': // 1 string to match. |
235 | 0 | return 201; // "s14" |
236 | 0 | case '5': // 1 string to match. |
237 | 0 | return 202; // "s15" |
238 | 0 | case '6': // 1 string to match. |
239 | 0 | return 203; // "s16" |
240 | 0 | case '7': // 1 string to match. |
241 | 0 | return 204; // "s17" |
242 | 0 | case '8': // 1 string to match. |
243 | 0 | return 205; // "s18" |
244 | 0 | case '9': // 1 string to match. |
245 | 0 | return 206; // "s19" |
246 | 0 | } |
247 | 0 | break; |
248 | 0 | case '2': // 10 strings to match. |
249 | 0 | switch (Name[2]) { |
250 | 0 | default: break; |
251 | 0 | case '0': // 1 string to match. |
252 | 0 | return 207; // "s20" |
253 | 0 | case '1': // 1 string to match. |
254 | 0 | return 208; // "s21" |
255 | 0 | case '2': // 1 string to match. |
256 | 0 | return 209; // "s22" |
257 | 0 | case '3': // 1 string to match. |
258 | 0 | return 210; // "s23" |
259 | 0 | case '4': // 1 string to match. |
260 | 0 | return 211; // "s24" |
261 | 0 | case '5': // 1 string to match. |
262 | 0 | return 212; // "s25" |
263 | 0 | case '6': // 1 string to match. |
264 | 0 | return 213; // "s26" |
265 | 0 | case '7': // 1 string to match. |
266 | 0 | return 214; // "s27" |
267 | 0 | case '8': // 1 string to match. |
268 | 0 | return 215; // "s28" |
269 | 0 | case '9': // 1 string to match. |
270 | 0 | return 216; // "s29" |
271 | 0 | } |
272 | 0 | break; |
273 | 0 | case '3': // 10 strings to match. |
274 | 0 | switch (Name[2]) { |
275 | 0 | default: break; |
276 | 0 | case '0': // 1 string to match. |
277 | 0 | return 217; // "s30" |
278 | 0 | case '1': // 1 string to match. |
279 | 0 | return 218; // "s31" |
280 | 0 | case '2': // 1 string to match. |
281 | 0 | return 219; // "s32" |
282 | 0 | case '3': // 1 string to match. |
283 | 0 | return 220; // "s33" |
284 | 0 | case '4': // 1 string to match. |
285 | 0 | return 221; // "s34" |
286 | 0 | case '5': // 1 string to match. |
287 | 0 | return 222; // "s35" |
288 | 0 | case '6': // 1 string to match. |
289 | 0 | return 223; // "s36" |
290 | 0 | case '7': // 1 string to match. |
291 | 0 | return 224; // "s37" |
292 | 0 | case '8': // 1 string to match. |
293 | 0 | return 225; // "s38" |
294 | 0 | case '9': // 1 string to match. |
295 | 0 | return 226; // "s39" |
296 | 0 | } |
297 | 0 | break; |
298 | 0 | case '4': // 10 strings to match. |
299 | 0 | switch (Name[2]) { |
300 | 0 | default: break; |
301 | 0 | case '0': // 1 string to match. |
302 | 0 | return 227; // "s40" |
303 | 0 | case '1': // 1 string to match. |
304 | 0 | return 228; // "s41" |
305 | 0 | case '2': // 1 string to match. |
306 | 0 | return 229; // "s42" |
307 | 0 | case '3': // 1 string to match. |
308 | 0 | return 230; // "s43" |
309 | 0 | case '4': // 1 string to match. |
310 | 0 | return 231; // "s44" |
311 | 0 | case '5': // 1 string to match. |
312 | 0 | return 232; // "s45" |
313 | 0 | case '6': // 1 string to match. |
314 | 0 | return 233; // "s46" |
315 | 0 | case '7': // 1 string to match. |
316 | 0 | return 234; // "s47" |
317 | 0 | case '8': // 1 string to match. |
318 | 0 | return 235; // "s48" |
319 | 0 | case '9': // 1 string to match. |
320 | 0 | return 236; // "s49" |
321 | 0 | } |
322 | 0 | break; |
323 | 0 | case '5': // 10 strings to match. |
324 | 0 | switch (Name[2]) { |
325 | 0 | default: break; |
326 | 0 | case '0': // 1 string to match. |
327 | 0 | return 237; // "s50" |
328 | 0 | case '1': // 1 string to match. |
329 | 0 | return 238; // "s51" |
330 | 0 | case '2': // 1 string to match. |
331 | 0 | return 239; // "s52" |
332 | 0 | case '3': // 1 string to match. |
333 | 0 | return 240; // "s53" |
334 | 0 | case '4': // 1 string to match. |
335 | 0 | return 241; // "s54" |
336 | 0 | case '5': // 1 string to match. |
337 | 0 | return 242; // "s55" |
338 | 0 | case '6': // 1 string to match. |
339 | 0 | return 243; // "s56" |
340 | 0 | case '7': // 1 string to match. |
341 | 0 | return 244; // "s57" |
342 | 0 | case '8': // 1 string to match. |
343 | 0 | return 245; // "s58" |
344 | 0 | case '9': // 1 string to match. |
345 | 0 | return 246; // "s59" |
346 | 0 | } |
347 | 0 | break; |
348 | 0 | case '6': // 4 strings to match. |
349 | 0 | switch (Name[2]) { |
350 | 0 | default: break; |
351 | 0 | case '0': // 1 string to match. |
352 | 0 | return 247; // "s60" |
353 | 0 | case '1': // 1 string to match. |
354 | 0 | return 248; // "s61" |
355 | 0 | case '2': // 1 string to match. |
356 | 0 | return 249; // "s62" |
357 | 0 | case '3': // 1 string to match. |
358 | 0 | return 250; // "s63" |
359 | 0 | } |
360 | 0 | break; |
361 | 0 | case 'a': // 1 string to match. |
362 | 0 | if (Name[2] != 'r') |
363 | 0 | break; |
364 | 0 | return 4; // "sar" |
365 | 0 | case 'f': // 10 strings to match. |
366 | 0 | switch (Name[2]) { |
367 | 0 | default: break; |
368 | 0 | case '0': // 1 string to match. |
369 | 0 | return 59; // "sf0" |
370 | 0 | case '1': // 1 string to match. |
371 | 0 | return 60; // "sf1" |
372 | 0 | case '2': // 1 string to match. |
373 | 0 | return 61; // "sf2" |
374 | 0 | case '3': // 1 string to match. |
375 | 0 | return 62; // "sf3" |
376 | 0 | case '4': // 1 string to match. |
377 | 0 | return 63; // "sf4" |
378 | 0 | case '5': // 1 string to match. |
379 | 0 | return 64; // "sf5" |
380 | 0 | case '6': // 1 string to match. |
381 | 0 | return 65; // "sf6" |
382 | 0 | case '7': // 1 string to match. |
383 | 0 | return 66; // "sf7" |
384 | 0 | case '8': // 1 string to match. |
385 | 0 | return 67; // "sf8" |
386 | 0 | case '9': // 1 string to match. |
387 | 0 | return 68; // "sf9" |
388 | 0 | } |
389 | 0 | break; |
390 | 0 | case 'w': // 10 strings to match. |
391 | 0 | switch (Name[2]) { |
392 | 0 | default: break; |
393 | 0 | case '0': // 1 string to match. |
394 | 0 | return 123; // "sw0" |
395 | 0 | case '1': // 1 string to match. |
396 | 0 | return 124; // "sw1" |
397 | 0 | case '2': // 1 string to match. |
398 | 0 | return 125; // "sw2" |
399 | 0 | case '3': // 1 string to match. |
400 | 0 | return 126; // "sw3" |
401 | 0 | case '4': // 1 string to match. |
402 | 0 | return 127; // "sw4" |
403 | 0 | case '5': // 1 string to match. |
404 | 0 | return 128; // "sw5" |
405 | 0 | case '6': // 1 string to match. |
406 | 0 | return 129; // "sw6" |
407 | 0 | case '7': // 1 string to match. |
408 | 0 | return 130; // "sw7" |
409 | 0 | case '8': // 1 string to match. |
410 | 0 | return 131; // "sw8" |
411 | 0 | case '9': // 1 string to match. |
412 | 0 | return 132; // "sw9" |
413 | 0 | } |
414 | 0 | break; |
415 | 0 | } |
416 | 0 | break; |
417 | 0 | case 'v': // 66 strings to match. |
418 | 0 | switch (Name[1]) { |
419 | 0 | default: break; |
420 | 0 | case '1': // 10 strings to match. |
421 | 0 | switch (Name[2]) { |
422 | 0 | default: break; |
423 | 0 | case '0': // 1 string to match. |
424 | 0 | return 261; // "v10" |
425 | 0 | case '1': // 1 string to match. |
426 | 0 | return 262; // "v11" |
427 | 0 | case '2': // 1 string to match. |
428 | 0 | return 263; // "v12" |
429 | 0 | case '3': // 1 string to match. |
430 | 0 | return 264; // "v13" |
431 | 0 | case '4': // 1 string to match. |
432 | 0 | return 265; // "v14" |
433 | 0 | case '5': // 1 string to match. |
434 | 0 | return 266; // "v15" |
435 | 0 | case '6': // 1 string to match. |
436 | 0 | return 267; // "v16" |
437 | 0 | case '7': // 1 string to match. |
438 | 0 | return 268; // "v17" |
439 | 0 | case '8': // 1 string to match. |
440 | 0 | return 269; // "v18" |
441 | 0 | case '9': // 1 string to match. |
442 | 0 | return 270; // "v19" |
443 | 0 | } |
444 | 0 | break; |
445 | 0 | case '2': // 10 strings to match. |
446 | 0 | switch (Name[2]) { |
447 | 0 | default: break; |
448 | 0 | case '0': // 1 string to match. |
449 | 0 | return 271; // "v20" |
450 | 0 | case '1': // 1 string to match. |
451 | 0 | return 272; // "v21" |
452 | 0 | case '2': // 1 string to match. |
453 | 0 | return 273; // "v22" |
454 | 0 | case '3': // 1 string to match. |
455 | 0 | return 274; // "v23" |
456 | 0 | case '4': // 1 string to match. |
457 | 0 | return 275; // "v24" |
458 | 0 | case '5': // 1 string to match. |
459 | 0 | return 276; // "v25" |
460 | 0 | case '6': // 1 string to match. |
461 | 0 | return 277; // "v26" |
462 | 0 | case '7': // 1 string to match. |
463 | 0 | return 278; // "v27" |
464 | 0 | case '8': // 1 string to match. |
465 | 0 | return 279; // "v28" |
466 | 0 | case '9': // 1 string to match. |
467 | 0 | return 280; // "v29" |
468 | 0 | } |
469 | 0 | break; |
470 | 0 | case '3': // 10 strings to match. |
471 | 0 | switch (Name[2]) { |
472 | 0 | default: break; |
473 | 0 | case '0': // 1 string to match. |
474 | 0 | return 281; // "v30" |
475 | 0 | case '1': // 1 string to match. |
476 | 0 | return 282; // "v31" |
477 | 0 | case '2': // 1 string to match. |
478 | 0 | return 283; // "v32" |
479 | 0 | case '3': // 1 string to match. |
480 | 0 | return 284; // "v33" |
481 | 0 | case '4': // 1 string to match. |
482 | 0 | return 285; // "v34" |
483 | 0 | case '5': // 1 string to match. |
484 | 0 | return 286; // "v35" |
485 | 0 | case '6': // 1 string to match. |
486 | 0 | return 287; // "v36" |
487 | 0 | case '7': // 1 string to match. |
488 | 0 | return 288; // "v37" |
489 | 0 | case '8': // 1 string to match. |
490 | 0 | return 289; // "v38" |
491 | 0 | case '9': // 1 string to match. |
492 | 0 | return 290; // "v39" |
493 | 0 | } |
494 | 0 | break; |
495 | 0 | case '4': // 10 strings to match. |
496 | 0 | switch (Name[2]) { |
497 | 0 | default: break; |
498 | 0 | case '0': // 1 string to match. |
499 | 0 | return 291; // "v40" |
500 | 0 | case '1': // 1 string to match. |
501 | 0 | return 292; // "v41" |
502 | 0 | case '2': // 1 string to match. |
503 | 0 | return 293; // "v42" |
504 | 0 | case '3': // 1 string to match. |
505 | 0 | return 294; // "v43" |
506 | 0 | case '4': // 1 string to match. |
507 | 0 | return 295; // "v44" |
508 | 0 | case '5': // 1 string to match. |
509 | 0 | return 296; // "v45" |
510 | 0 | case '6': // 1 string to match. |
511 | 0 | return 297; // "v46" |
512 | 0 | case '7': // 1 string to match. |
513 | 0 | return 298; // "v47" |
514 | 0 | case '8': // 1 string to match. |
515 | 0 | return 299; // "v48" |
516 | 0 | case '9': // 1 string to match. |
517 | 0 | return 300; // "v49" |
518 | 0 | } |
519 | 0 | break; |
520 | 0 | case '5': // 10 strings to match. |
521 | 0 | switch (Name[2]) { |
522 | 0 | default: break; |
523 | 0 | case '0': // 1 string to match. |
524 | 0 | return 301; // "v50" |
525 | 0 | case '1': // 1 string to match. |
526 | 0 | return 302; // "v51" |
527 | 0 | case '2': // 1 string to match. |
528 | 0 | return 303; // "v52" |
529 | 0 | case '3': // 1 string to match. |
530 | 0 | return 304; // "v53" |
531 | 0 | case '4': // 1 string to match. |
532 | 0 | return 305; // "v54" |
533 | 0 | case '5': // 1 string to match. |
534 | 0 | return 306; // "v55" |
535 | 0 | case '6': // 1 string to match. |
536 | 0 | return 307; // "v56" |
537 | 0 | case '7': // 1 string to match. |
538 | 0 | return 308; // "v57" |
539 | 0 | case '8': // 1 string to match. |
540 | 0 | return 309; // "v58" |
541 | 0 | case '9': // 1 string to match. |
542 | 0 | return 310; // "v59" |
543 | 0 | } |
544 | 0 | break; |
545 | 0 | case '6': // 4 strings to match. |
546 | 0 | switch (Name[2]) { |
547 | 0 | default: break; |
548 | 0 | case '0': // 1 string to match. |
549 | 0 | return 311; // "v60" |
550 | 0 | case '1': // 1 string to match. |
551 | 0 | return 312; // "v61" |
552 | 0 | case '2': // 1 string to match. |
553 | 0 | return 313; // "v62" |
554 | 0 | case '3': // 1 string to match. |
555 | 0 | return 314; // "v63" |
556 | 0 | } |
557 | 0 | break; |
558 | 0 | case 'i': // 1 string to match. |
559 | 0 | if (Name[2] != 'x') |
560 | 0 | break; |
561 | 0 | return 6; // "vix" |
562 | 0 | case 'm': // 11 strings to match. |
563 | 0 | switch (Name[2]) { |
564 | 0 | default: break; |
565 | 0 | case '0': // 2 strings to match. |
566 | 0 | return 315; // "vm0" |
567 | 0 | case '1': // 1 string to match. |
568 | 0 | return 316; // "vm1" |
569 | 0 | case '2': // 1 string to match. |
570 | 0 | return 317; // "vm2" |
571 | 0 | case '3': // 1 string to match. |
572 | 0 | return 318; // "vm3" |
573 | 0 | case '4': // 1 string to match. |
574 | 0 | return 319; // "vm4" |
575 | 0 | case '5': // 1 string to match. |
576 | 0 | return 320; // "vm5" |
577 | 0 | case '6': // 1 string to match. |
578 | 0 | return 321; // "vm6" |
579 | 0 | case '7': // 1 string to match. |
580 | 0 | return 322; // "vm7" |
581 | 0 | case '8': // 1 string to match. |
582 | 0 | return 323; // "vm8" |
583 | 0 | case '9': // 1 string to match. |
584 | 0 | return 324; // "vm9" |
585 | 0 | } |
586 | 0 | break; |
587 | 0 | } |
588 | 0 | break; |
589 | 0 | } |
590 | 0 | break; |
591 | 0 | case 4: // 132 strings to match. |
592 | 0 | switch (Name[0]) { |
593 | 0 | default: break; |
594 | 0 | case 'p': // 11 strings to match. |
595 | 0 | if (Name[1] != 'm') |
596 | 0 | break; |
597 | 0 | switch (Name[2]) { |
598 | 0 | default: break; |
599 | 0 | case 'c': // 10 strings to match. |
600 | 0 | switch (Name[3]) { |
601 | 0 | default: break; |
602 | 0 | case '0': // 1 string to match. |
603 | 0 | return 8; // "pmc0" |
604 | 0 | case '1': // 1 string to match. |
605 | 0 | return 9; // "pmc1" |
606 | 0 | case '2': // 1 string to match. |
607 | 0 | return 10; // "pmc2" |
608 | 0 | case '3': // 1 string to match. |
609 | 0 | return 11; // "pmc3" |
610 | 0 | case '4': // 1 string to match. |
611 | 0 | return 12; // "pmc4" |
612 | 0 | case '5': // 1 string to match. |
613 | 0 | return 13; // "pmc5" |
614 | 0 | case '6': // 1 string to match. |
615 | 0 | return 14; // "pmc6" |
616 | 0 | case '7': // 1 string to match. |
617 | 0 | return 15; // "pmc7" |
618 | 0 | case '8': // 1 string to match. |
619 | 0 | return 16; // "pmc8" |
620 | 0 | case '9': // 1 string to match. |
621 | 0 | return 17; // "pmc9" |
622 | 0 | } |
623 | 0 | break; |
624 | 0 | case 'm': // 1 string to match. |
625 | 0 | if (Name[3] != 'r') |
626 | 0 | break; |
627 | 0 | return 2; // "pmmr" |
628 | 0 | } |
629 | 0 | break; |
630 | 0 | case 's': // 108 strings to match. |
631 | 0 | switch (Name[1]) { |
632 | 0 | default: break; |
633 | 0 | case 'f': // 54 strings to match. |
634 | 0 | switch (Name[2]) { |
635 | 0 | default: break; |
636 | 0 | case '1': // 10 strings to match. |
637 | 0 | switch (Name[3]) { |
638 | 0 | default: break; |
639 | 0 | case '0': // 1 string to match. |
640 | 0 | return 69; // "sf10" |
641 | 0 | case '1': // 1 string to match. |
642 | 0 | return 70; // "sf11" |
643 | 0 | case '2': // 1 string to match. |
644 | 0 | return 71; // "sf12" |
645 | 0 | case '3': // 1 string to match. |
646 | 0 | return 72; // "sf13" |
647 | 0 | case '4': // 1 string to match. |
648 | 0 | return 73; // "sf14" |
649 | 0 | case '5': // 1 string to match. |
650 | 0 | return 74; // "sf15" |
651 | 0 | case '6': // 1 string to match. |
652 | 0 | return 75; // "sf16" |
653 | 0 | case '7': // 1 string to match. |
654 | 0 | return 76; // "sf17" |
655 | 0 | case '8': // 1 string to match. |
656 | 0 | return 77; // "sf18" |
657 | 0 | case '9': // 1 string to match. |
658 | 0 | return 78; // "sf19" |
659 | 0 | } |
660 | 0 | break; |
661 | 0 | case '2': // 10 strings to match. |
662 | 0 | switch (Name[3]) { |
663 | 0 | default: break; |
664 | 0 | case '0': // 1 string to match. |
665 | 0 | return 79; // "sf20" |
666 | 0 | case '1': // 1 string to match. |
667 | 0 | return 80; // "sf21" |
668 | 0 | case '2': // 1 string to match. |
669 | 0 | return 81; // "sf22" |
670 | 0 | case '3': // 1 string to match. |
671 | 0 | return 82; // "sf23" |
672 | 0 | case '4': // 1 string to match. |
673 | 0 | return 83; // "sf24" |
674 | 0 | case '5': // 1 string to match. |
675 | 0 | return 84; // "sf25" |
676 | 0 | case '6': // 1 string to match. |
677 | 0 | return 85; // "sf26" |
678 | 0 | case '7': // 1 string to match. |
679 | 0 | return 86; // "sf27" |
680 | 0 | case '8': // 1 string to match. |
681 | 0 | return 87; // "sf28" |
682 | 0 | case '9': // 1 string to match. |
683 | 0 | return 88; // "sf29" |
684 | 0 | } |
685 | 0 | break; |
686 | 0 | case '3': // 10 strings to match. |
687 | 0 | switch (Name[3]) { |
688 | 0 | default: break; |
689 | 0 | case '0': // 1 string to match. |
690 | 0 | return 89; // "sf30" |
691 | 0 | case '1': // 1 string to match. |
692 | 0 | return 90; // "sf31" |
693 | 0 | case '2': // 1 string to match. |
694 | 0 | return 91; // "sf32" |
695 | 0 | case '3': // 1 string to match. |
696 | 0 | return 92; // "sf33" |
697 | 0 | case '4': // 1 string to match. |
698 | 0 | return 93; // "sf34" |
699 | 0 | case '5': // 1 string to match. |
700 | 0 | return 94; // "sf35" |
701 | 0 | case '6': // 1 string to match. |
702 | 0 | return 95; // "sf36" |
703 | 0 | case '7': // 1 string to match. |
704 | 0 | return 96; // "sf37" |
705 | 0 | case '8': // 1 string to match. |
706 | 0 | return 97; // "sf38" |
707 | 0 | case '9': // 1 string to match. |
708 | 0 | return 98; // "sf39" |
709 | 0 | } |
710 | 0 | break; |
711 | 0 | case '4': // 10 strings to match. |
712 | 0 | switch (Name[3]) { |
713 | 0 | default: break; |
714 | 0 | case '0': // 1 string to match. |
715 | 0 | return 99; // "sf40" |
716 | 0 | case '1': // 1 string to match. |
717 | 0 | return 100; // "sf41" |
718 | 0 | case '2': // 1 string to match. |
719 | 0 | return 101; // "sf42" |
720 | 0 | case '3': // 1 string to match. |
721 | 0 | return 102; // "sf43" |
722 | 0 | case '4': // 1 string to match. |
723 | 0 | return 103; // "sf44" |
724 | 0 | case '5': // 1 string to match. |
725 | 0 | return 104; // "sf45" |
726 | 0 | case '6': // 1 string to match. |
727 | 0 | return 105; // "sf46" |
728 | 0 | case '7': // 1 string to match. |
729 | 0 | return 106; // "sf47" |
730 | 0 | case '8': // 1 string to match. |
731 | 0 | return 107; // "sf48" |
732 | 0 | case '9': // 1 string to match. |
733 | 0 | return 108; // "sf49" |
734 | 0 | } |
735 | 0 | break; |
736 | 0 | case '5': // 10 strings to match. |
737 | 0 | switch (Name[3]) { |
738 | 0 | default: break; |
739 | 0 | case '0': // 1 string to match. |
740 | 0 | return 109; // "sf50" |
741 | 0 | case '1': // 1 string to match. |
742 | 0 | return 110; // "sf51" |
743 | 0 | case '2': // 1 string to match. |
744 | 0 | return 111; // "sf52" |
745 | 0 | case '3': // 1 string to match. |
746 | 0 | return 112; // "sf53" |
747 | 0 | case '4': // 1 string to match. |
748 | 0 | return 113; // "sf54" |
749 | 0 | case '5': // 1 string to match. |
750 | 0 | return 114; // "sf55" |
751 | 0 | case '6': // 1 string to match. |
752 | 0 | return 115; // "sf56" |
753 | 0 | case '7': // 1 string to match. |
754 | 0 | return 116; // "sf57" |
755 | 0 | case '8': // 1 string to match. |
756 | 0 | return 117; // "sf58" |
757 | 0 | case '9': // 1 string to match. |
758 | 0 | return 118; // "sf59" |
759 | 0 | } |
760 | 0 | break; |
761 | 0 | case '6': // 4 strings to match. |
762 | 0 | switch (Name[3]) { |
763 | 0 | default: break; |
764 | 0 | case '0': // 1 string to match. |
765 | 0 | return 119; // "sf60" |
766 | 0 | case '1': // 1 string to match. |
767 | 0 | return 120; // "sf61" |
768 | 0 | case '2': // 1 string to match. |
769 | 0 | return 121; // "sf62" |
770 | 0 | case '3': // 1 string to match. |
771 | 0 | return 122; // "sf63" |
772 | 0 | } |
773 | 0 | break; |
774 | 0 | } |
775 | 0 | break; |
776 | 0 | case 'w': // 54 strings to match. |
777 | 0 | switch (Name[2]) { |
778 | 0 | default: break; |
779 | 0 | case '1': // 10 strings to match. |
780 | 0 | switch (Name[3]) { |
781 | 0 | default: break; |
782 | 0 | case '0': // 1 string to match. |
783 | 0 | return 133; // "sw10" |
784 | 0 | case '1': // 1 string to match. |
785 | 0 | return 134; // "sw11" |
786 | 0 | case '2': // 1 string to match. |
787 | 0 | return 135; // "sw12" |
788 | 0 | case '3': // 1 string to match. |
789 | 0 | return 136; // "sw13" |
790 | 0 | case '4': // 1 string to match. |
791 | 0 | return 137; // "sw14" |
792 | 0 | case '5': // 1 string to match. |
793 | 0 | return 138; // "sw15" |
794 | 0 | case '6': // 1 string to match. |
795 | 0 | return 139; // "sw16" |
796 | 0 | case '7': // 1 string to match. |
797 | 0 | return 140; // "sw17" |
798 | 0 | case '8': // 1 string to match. |
799 | 0 | return 141; // "sw18" |
800 | 0 | case '9': // 1 string to match. |
801 | 0 | return 142; // "sw19" |
802 | 0 | } |
803 | 0 | break; |
804 | 0 | case '2': // 10 strings to match. |
805 | 0 | switch (Name[3]) { |
806 | 0 | default: break; |
807 | 0 | case '0': // 1 string to match. |
808 | 0 | return 143; // "sw20" |
809 | 0 | case '1': // 1 string to match. |
810 | 0 | return 144; // "sw21" |
811 | 0 | case '2': // 1 string to match. |
812 | 0 | return 145; // "sw22" |
813 | 0 | case '3': // 1 string to match. |
814 | 0 | return 146; // "sw23" |
815 | 0 | case '4': // 1 string to match. |
816 | 0 | return 147; // "sw24" |
817 | 0 | case '5': // 1 string to match. |
818 | 0 | return 148; // "sw25" |
819 | 0 | case '6': // 1 string to match. |
820 | 0 | return 149; // "sw26" |
821 | 0 | case '7': // 1 string to match. |
822 | 0 | return 150; // "sw27" |
823 | 0 | case '8': // 1 string to match. |
824 | 0 | return 151; // "sw28" |
825 | 0 | case '9': // 1 string to match. |
826 | 0 | return 152; // "sw29" |
827 | 0 | } |
828 | 0 | break; |
829 | 0 | case '3': // 10 strings to match. |
830 | 0 | switch (Name[3]) { |
831 | 0 | default: break; |
832 | 0 | case '0': // 1 string to match. |
833 | 0 | return 153; // "sw30" |
834 | 0 | case '1': // 1 string to match. |
835 | 0 | return 154; // "sw31" |
836 | 0 | case '2': // 1 string to match. |
837 | 0 | return 155; // "sw32" |
838 | 0 | case '3': // 1 string to match. |
839 | 0 | return 156; // "sw33" |
840 | 0 | case '4': // 1 string to match. |
841 | 0 | return 157; // "sw34" |
842 | 0 | case '5': // 1 string to match. |
843 | 0 | return 158; // "sw35" |
844 | 0 | case '6': // 1 string to match. |
845 | 0 | return 159; // "sw36" |
846 | 0 | case '7': // 1 string to match. |
847 | 0 | return 160; // "sw37" |
848 | 0 | case '8': // 1 string to match. |
849 | 0 | return 161; // "sw38" |
850 | 0 | case '9': // 1 string to match. |
851 | 0 | return 162; // "sw39" |
852 | 0 | } |
853 | 0 | break; |
854 | 0 | case '4': // 10 strings to match. |
855 | 0 | switch (Name[3]) { |
856 | 0 | default: break; |
857 | 0 | case '0': // 1 string to match. |
858 | 0 | return 163; // "sw40" |
859 | 0 | case '1': // 1 string to match. |
860 | 0 | return 164; // "sw41" |
861 | 0 | case '2': // 1 string to match. |
862 | 0 | return 165; // "sw42" |
863 | 0 | case '3': // 1 string to match. |
864 | 0 | return 166; // "sw43" |
865 | 0 | case '4': // 1 string to match. |
866 | 0 | return 167; // "sw44" |
867 | 0 | case '5': // 1 string to match. |
868 | 0 | return 168; // "sw45" |
869 | 0 | case '6': // 1 string to match. |
870 | 0 | return 169; // "sw46" |
871 | 0 | case '7': // 1 string to match. |
872 | 0 | return 170; // "sw47" |
873 | 0 | case '8': // 1 string to match. |
874 | 0 | return 171; // "sw48" |
875 | 0 | case '9': // 1 string to match. |
876 | 0 | return 172; // "sw49" |
877 | 0 | } |
878 | 0 | break; |
879 | 0 | case '5': // 10 strings to match. |
880 | 0 | switch (Name[3]) { |
881 | 0 | default: break; |
882 | 0 | case '0': // 1 string to match. |
883 | 0 | return 173; // "sw50" |
884 | 0 | case '1': // 1 string to match. |
885 | 0 | return 174; // "sw51" |
886 | 0 | case '2': // 1 string to match. |
887 | 0 | return 175; // "sw52" |
888 | 0 | case '3': // 1 string to match. |
889 | 0 | return 176; // "sw53" |
890 | 0 | case '4': // 1 string to match. |
891 | 0 | return 177; // "sw54" |
892 | 0 | case '5': // 1 string to match. |
893 | 0 | return 178; // "sw55" |
894 | 0 | case '6': // 1 string to match. |
895 | 0 | return 179; // "sw56" |
896 | 0 | case '7': // 1 string to match. |
897 | 0 | return 180; // "sw57" |
898 | 0 | case '8': // 1 string to match. |
899 | 0 | return 181; // "sw58" |
900 | 0 | case '9': // 1 string to match. |
901 | 0 | return 182; // "sw59" |
902 | 0 | } |
903 | 0 | break; |
904 | 0 | case '6': // 4 strings to match. |
905 | 0 | switch (Name[3]) { |
906 | 0 | default: break; |
907 | 0 | case '0': // 1 string to match. |
908 | 0 | return 183; // "sw60" |
909 | 0 | case '1': // 1 string to match. |
910 | 0 | return 184; // "sw61" |
911 | 0 | case '2': // 1 string to match. |
912 | 0 | return 185; // "sw62" |
913 | 0 | case '3': // 1 string to match. |
914 | 0 | return 186; // "sw63" |
915 | 0 | } |
916 | 0 | break; |
917 | 0 | } |
918 | 0 | break; |
919 | 0 | } |
920 | 0 | break; |
921 | 0 | case 'v': // 13 strings to match. |
922 | 0 | if (Name[1] != 'm') |
923 | 0 | break; |
924 | 0 | switch (Name[2]) { |
925 | 0 | default: break; |
926 | 0 | case '1': // 6 strings to match. |
927 | 0 | switch (Name[3]) { |
928 | 0 | default: break; |
929 | 0 | case '0': // 1 string to match. |
930 | 0 | return 325; // "vm10" |
931 | 0 | case '1': // 1 string to match. |
932 | 0 | return 326; // "vm11" |
933 | 0 | case '2': // 1 string to match. |
934 | 0 | return 327; // "vm12" |
935 | 0 | case '3': // 1 string to match. |
936 | 0 | return 328; // "vm13" |
937 | 0 | case '4': // 1 string to match. |
938 | 0 | return 329; // "vm14" |
939 | 0 | case '5': // 1 string to match. |
940 | 0 | return 330; // "vm15" |
941 | 0 | } |
942 | 0 | break; |
943 | 0 | case 'p': // 7 strings to match. |
944 | 0 | switch (Name[3]) { |
945 | 0 | default: break; |
946 | 0 | case '1': // 1 string to match. |
947 | 0 | return 332; // "vmp1" |
948 | 0 | case '2': // 1 string to match. |
949 | 0 | return 333; // "vmp2" |
950 | 0 | case '3': // 1 string to match. |
951 | 0 | return 334; // "vmp3" |
952 | 0 | case '4': // 1 string to match. |
953 | 0 | return 335; // "vmp4" |
954 | 0 | case '5': // 1 string to match. |
955 | 0 | return 336; // "vmp5" |
956 | 0 | case '6': // 1 string to match. |
957 | 0 | return 337; // "vmp6" |
958 | 0 | case '7': // 1 string to match. |
959 | 0 | return 338; // "vmp7" |
960 | 0 | } |
961 | 0 | break; |
962 | 0 | } |
963 | 0 | break; |
964 | 0 | } |
965 | 0 | break; |
966 | 0 | case 5: // 10 strings to match. |
967 | 0 | switch (Name[0]) { |
968 | 0 | default: break; |
969 | 0 | case 'p': // 9 strings to match. |
970 | 0 | if (memcmp(Name.data()+1, "mc", 2) != 0) |
971 | 0 | break; |
972 | 0 | switch (Name[3]) { |
973 | 0 | default: break; |
974 | 0 | case '1': // 5 strings to match. |
975 | 0 | switch (Name[4]) { |
976 | 0 | default: break; |
977 | 0 | case '0': // 1 string to match. |
978 | 0 | return 18; // "pmc10" |
979 | 0 | case '1': // 1 string to match. |
980 | 0 | return 19; // "pmc11" |
981 | 0 | case '2': // 1 string to match. |
982 | 0 | return 20; // "pmc12" |
983 | 0 | case '3': // 1 string to match. |
984 | 0 | return 21; // "pmc13" |
985 | 0 | case '4': // 1 string to match. |
986 | 0 | return 22; // "pmc14" |
987 | 0 | } |
988 | 0 | break; |
989 | 0 | case 'r': // 4 strings to match. |
990 | 0 | switch (Name[4]) { |
991 | 0 | default: break; |
992 | 0 | case '0': // 1 string to match. |
993 | 0 | return 23; // "pmcr0" |
994 | 0 | case '1': // 1 string to match. |
995 | 0 | return 24; // "pmcr1" |
996 | 0 | case '2': // 1 string to match. |
997 | 0 | return 25; // "pmcr2" |
998 | 0 | case '3': // 1 string to match. |
999 | 0 | return 26; // "pmcr3" |
1000 | 0 | } |
1001 | 0 | break; |
1002 | 0 | } |
1003 | 0 | break; |
1004 | 0 | case 'u': // 1 string to match. |
1005 | 0 | if (memcmp(Name.data()+1, "srcc", 4) != 0) |
1006 | 0 | break; |
1007 | 0 | return 5; // "usrcc" |
1008 | 0 | } |
1009 | 0 | break; |
1010 | 0 | } |
1011 | 0 | return 0; |
1012 | 0 | } |
1013 | | |
1014 | 0 | static unsigned MatchRegisterAltName(StringRef Name) { |
1015 | 0 | switch (Name.size()) { |
1016 | 0 | default: break; |
1017 | 0 | case 2: // 50 strings to match. |
1018 | 0 | switch (Name[0]) { |
1019 | 0 | default: break; |
1020 | 0 | case 'f': // 1 string to match. |
1021 | 0 | if (Name[1] != 'p') |
1022 | 0 | break; |
1023 | 0 | return 196; // "fp" |
1024 | 0 | case 'l': // 1 string to match. |
1025 | 0 | if (Name[1] != 'r') |
1026 | 0 | break; |
1027 | 0 | return 197; // "lr" |
1028 | 0 | case 's': // 37 strings to match. |
1029 | 0 | switch (Name[1]) { |
1030 | 0 | default: break; |
1031 | 0 | case '0': // 4 strings to match. |
1032 | 0 | return 27; // "s0" |
1033 | 0 | case '1': // 3 strings to match. |
1034 | 0 | return 60; // "s1" |
1035 | 0 | case '2': // 4 strings to match. |
1036 | 0 | return 28; // "s2" |
1037 | 0 | case '3': // 3 strings to match. |
1038 | 0 | return 62; // "s3" |
1039 | 0 | case '4': // 4 strings to match. |
1040 | 0 | return 29; // "s4" |
1041 | 0 | case '5': // 3 strings to match. |
1042 | 0 | return 64; // "s5" |
1043 | 0 | case '6': // 4 strings to match. |
1044 | 0 | return 30; // "s6" |
1045 | 0 | case '7': // 3 strings to match. |
1046 | 0 | return 66; // "s7" |
1047 | 0 | case '8': // 4 strings to match. |
1048 | 0 | return 31; // "s8" |
1049 | 0 | case '9': // 3 strings to match. |
1050 | 0 | return 68; // "s9" |
1051 | 0 | case 'l': // 1 string to match. |
1052 | 0 | return 195; // "sl" |
1053 | 0 | case 'p': // 1 string to match. |
1054 | 0 | return 198; // "sp" |
1055 | 0 | } |
1056 | 0 | break; |
1057 | 0 | case 't': // 1 string to match. |
1058 | 0 | if (Name[1] != 'p') |
1059 | 0 | break; |
1060 | 0 | return 201; // "tp" |
1061 | 0 | case 'v': // 10 strings to match. |
1062 | 0 | switch (Name[1]) { |
1063 | 0 | default: break; |
1064 | 0 | case '0': // 1 string to match. |
1065 | 0 | return 251; // "v0" |
1066 | 0 | case '1': // 1 string to match. |
1067 | 0 | return 252; // "v1" |
1068 | 0 | case '2': // 1 string to match. |
1069 | 0 | return 253; // "v2" |
1070 | 0 | case '3': // 1 string to match. |
1071 | 0 | return 254; // "v3" |
1072 | 0 | case '4': // 1 string to match. |
1073 | 0 | return 255; // "v4" |
1074 | 0 | case '5': // 1 string to match. |
1075 | 0 | return 256; // "v5" |
1076 | 0 | case '6': // 1 string to match. |
1077 | 0 | return 257; // "v6" |
1078 | 0 | case '7': // 1 string to match. |
1079 | 0 | return 258; // "v7" |
1080 | 0 | case '8': // 1 string to match. |
1081 | 0 | return 259; // "v8" |
1082 | 0 | case '9': // 1 string to match. |
1083 | 0 | return 260; // "v9" |
1084 | 0 | } |
1085 | 0 | break; |
1086 | 0 | } |
1087 | 0 | break; |
1088 | 0 | case 3: // 261 strings to match. |
1089 | 0 | switch (Name[0]) { |
1090 | 0 | default: break; |
1091 | 0 | case 'g': // 1 string to match. |
1092 | 0 | if (memcmp(Name.data()+1, "ot", 2) != 0) |
1093 | 0 | break; |
1094 | 0 | return 202; // "got" |
1095 | 0 | case 'p': // 1 string to match. |
1096 | 0 | if (memcmp(Name.data()+1, "lt", 2) != 0) |
1097 | 0 | break; |
1098 | 0 | return 203; // "plt" |
1099 | 0 | case 's': // 189 strings to match. |
1100 | 0 | switch (Name[1]) { |
1101 | 0 | default: break; |
1102 | 0 | case '1': // 35 strings to match. |
1103 | 0 | switch (Name[2]) { |
1104 | 0 | default: break; |
1105 | 0 | case '0': // 4 strings to match. |
1106 | 0 | return 32; // "s10" |
1107 | 0 | case '1': // 3 strings to match. |
1108 | 0 | return 70; // "s11" |
1109 | 0 | case '2': // 4 strings to match. |
1110 | 0 | return 33; // "s12" |
1111 | 0 | case '3': // 3 strings to match. |
1112 | 0 | return 72; // "s13" |
1113 | 0 | case '4': // 4 strings to match. |
1114 | 0 | return 34; // "s14" |
1115 | 0 | case '5': // 3 strings to match. |
1116 | 0 | return 74; // "s15" |
1117 | 0 | case '6': // 4 strings to match. |
1118 | 0 | return 35; // "s16" |
1119 | 0 | case '7': // 3 strings to match. |
1120 | 0 | return 76; // "s17" |
1121 | 0 | case '8': // 4 strings to match. |
1122 | 0 | return 36; // "s18" |
1123 | 0 | case '9': // 3 strings to match. |
1124 | 0 | return 78; // "s19" |
1125 | 0 | } |
1126 | 0 | break; |
1127 | 0 | case '2': // 35 strings to match. |
1128 | 0 | switch (Name[2]) { |
1129 | 0 | default: break; |
1130 | 0 | case '0': // 4 strings to match. |
1131 | 0 | return 37; // "s20" |
1132 | 0 | case '1': // 3 strings to match. |
1133 | 0 | return 80; // "s21" |
1134 | 0 | case '2': // 4 strings to match. |
1135 | 0 | return 38; // "s22" |
1136 | 0 | case '3': // 3 strings to match. |
1137 | 0 | return 82; // "s23" |
1138 | 0 | case '4': // 4 strings to match. |
1139 | 0 | return 39; // "s24" |
1140 | 0 | case '5': // 3 strings to match. |
1141 | 0 | return 84; // "s25" |
1142 | 0 | case '6': // 4 strings to match. |
1143 | 0 | return 40; // "s26" |
1144 | 0 | case '7': // 3 strings to match. |
1145 | 0 | return 86; // "s27" |
1146 | 0 | case '8': // 4 strings to match. |
1147 | 0 | return 41; // "s28" |
1148 | 0 | case '9': // 3 strings to match. |
1149 | 0 | return 88; // "s29" |
1150 | 0 | } |
1151 | 0 | break; |
1152 | 0 | case '3': // 35 strings to match. |
1153 | 0 | switch (Name[2]) { |
1154 | 0 | default: break; |
1155 | 0 | case '0': // 4 strings to match. |
1156 | 0 | return 42; // "s30" |
1157 | 0 | case '1': // 3 strings to match. |
1158 | 0 | return 90; // "s31" |
1159 | 0 | case '2': // 4 strings to match. |
1160 | 0 | return 43; // "s32" |
1161 | 0 | case '3': // 3 strings to match. |
1162 | 0 | return 92; // "s33" |
1163 | 0 | case '4': // 4 strings to match. |
1164 | 0 | return 44; // "s34" |
1165 | 0 | case '5': // 3 strings to match. |
1166 | 0 | return 94; // "s35" |
1167 | 0 | case '6': // 4 strings to match. |
1168 | 0 | return 45; // "s36" |
1169 | 0 | case '7': // 3 strings to match. |
1170 | 0 | return 96; // "s37" |
1171 | 0 | case '8': // 4 strings to match. |
1172 | 0 | return 46; // "s38" |
1173 | 0 | case '9': // 3 strings to match. |
1174 | 0 | return 98; // "s39" |
1175 | 0 | } |
1176 | 0 | break; |
1177 | 0 | case '4': // 35 strings to match. |
1178 | 0 | switch (Name[2]) { |
1179 | 0 | default: break; |
1180 | 0 | case '0': // 4 strings to match. |
1181 | 0 | return 47; // "s40" |
1182 | 0 | case '1': // 3 strings to match. |
1183 | 0 | return 100; // "s41" |
1184 | 0 | case '2': // 4 strings to match. |
1185 | 0 | return 48; // "s42" |
1186 | 0 | case '3': // 3 strings to match. |
1187 | 0 | return 102; // "s43" |
1188 | 0 | case '4': // 4 strings to match. |
1189 | 0 | return 49; // "s44" |
1190 | 0 | case '5': // 3 strings to match. |
1191 | 0 | return 104; // "s45" |
1192 | 0 | case '6': // 4 strings to match. |
1193 | 0 | return 50; // "s46" |
1194 | 0 | case '7': // 3 strings to match. |
1195 | 0 | return 106; // "s47" |
1196 | 0 | case '8': // 4 strings to match. |
1197 | 0 | return 51; // "s48" |
1198 | 0 | case '9': // 3 strings to match. |
1199 | 0 | return 108; // "s49" |
1200 | 0 | } |
1201 | 0 | break; |
1202 | 0 | case '5': // 35 strings to match. |
1203 | 0 | switch (Name[2]) { |
1204 | 0 | default: break; |
1205 | 0 | case '0': // 4 strings to match. |
1206 | 0 | return 52; // "s50" |
1207 | 0 | case '1': // 3 strings to match. |
1208 | 0 | return 110; // "s51" |
1209 | 0 | case '2': // 4 strings to match. |
1210 | 0 | return 53; // "s52" |
1211 | 0 | case '3': // 3 strings to match. |
1212 | 0 | return 112; // "s53" |
1213 | 0 | case '4': // 4 strings to match. |
1214 | 0 | return 54; // "s54" |
1215 | 0 | case '5': // 3 strings to match. |
1216 | 0 | return 114; // "s55" |
1217 | 0 | case '6': // 4 strings to match. |
1218 | 0 | return 55; // "s56" |
1219 | 0 | case '7': // 3 strings to match. |
1220 | 0 | return 116; // "s57" |
1221 | 0 | case '8': // 4 strings to match. |
1222 | 0 | return 56; // "s58" |
1223 | 0 | case '9': // 3 strings to match. |
1224 | 0 | return 118; // "s59" |
1225 | 0 | } |
1226 | 0 | break; |
1227 | 0 | case '6': // 14 strings to match. |
1228 | 0 | switch (Name[2]) { |
1229 | 0 | default: break; |
1230 | 0 | case '0': // 4 strings to match. |
1231 | 0 | return 57; // "s60" |
1232 | 0 | case '1': // 3 strings to match. |
1233 | 0 | return 120; // "s61" |
1234 | 0 | case '2': // 4 strings to match. |
1235 | 0 | return 58; // "s62" |
1236 | 0 | case '3': // 3 strings to match. |
1237 | 0 | return 122; // "s63" |
1238 | 0 | } |
1239 | 0 | break; |
1240 | 0 | } |
1241 | 0 | break; |
1242 | 0 | case 'v': // 70 strings to match. |
1243 | 0 | switch (Name[1]) { |
1244 | 0 | default: break; |
1245 | 0 | case '1': // 10 strings to match. |
1246 | 0 | switch (Name[2]) { |
1247 | 0 | default: break; |
1248 | 0 | case '0': // 1 string to match. |
1249 | 0 | return 261; // "v10" |
1250 | 0 | case '1': // 1 string to match. |
1251 | 0 | return 262; // "v11" |
1252 | 0 | case '2': // 1 string to match. |
1253 | 0 | return 263; // "v12" |
1254 | 0 | case '3': // 1 string to match. |
1255 | 0 | return 264; // "v13" |
1256 | 0 | case '4': // 1 string to match. |
1257 | 0 | return 265; // "v14" |
1258 | 0 | case '5': // 1 string to match. |
1259 | 0 | return 266; // "v15" |
1260 | 0 | case '6': // 1 string to match. |
1261 | 0 | return 267; // "v16" |
1262 | 0 | case '7': // 1 string to match. |
1263 | 0 | return 268; // "v17" |
1264 | 0 | case '8': // 1 string to match. |
1265 | 0 | return 269; // "v18" |
1266 | 0 | case '9': // 1 string to match. |
1267 | 0 | return 270; // "v19" |
1268 | 0 | } |
1269 | 0 | break; |
1270 | 0 | case '2': // 10 strings to match. |
1271 | 0 | switch (Name[2]) { |
1272 | 0 | default: break; |
1273 | 0 | case '0': // 1 string to match. |
1274 | 0 | return 271; // "v20" |
1275 | 0 | case '1': // 1 string to match. |
1276 | 0 | return 272; // "v21" |
1277 | 0 | case '2': // 1 string to match. |
1278 | 0 | return 273; // "v22" |
1279 | 0 | case '3': // 1 string to match. |
1280 | 0 | return 274; // "v23" |
1281 | 0 | case '4': // 1 string to match. |
1282 | 0 | return 275; // "v24" |
1283 | 0 | case '5': // 1 string to match. |
1284 | 0 | return 276; // "v25" |
1285 | 0 | case '6': // 1 string to match. |
1286 | 0 | return 277; // "v26" |
1287 | 0 | case '7': // 1 string to match. |
1288 | 0 | return 278; // "v27" |
1289 | 0 | case '8': // 1 string to match. |
1290 | 0 | return 279; // "v28" |
1291 | 0 | case '9': // 1 string to match. |
1292 | 0 | return 280; // "v29" |
1293 | 0 | } |
1294 | 0 | break; |
1295 | 0 | case '3': // 10 strings to match. |
1296 | 0 | switch (Name[2]) { |
1297 | 0 | default: break; |
1298 | 0 | case '0': // 1 string to match. |
1299 | 0 | return 281; // "v30" |
1300 | 0 | case '1': // 1 string to match. |
1301 | 0 | return 282; // "v31" |
1302 | 0 | case '2': // 1 string to match. |
1303 | 0 | return 283; // "v32" |
1304 | 0 | case '3': // 1 string to match. |
1305 | 0 | return 284; // "v33" |
1306 | 0 | case '4': // 1 string to match. |
1307 | 0 | return 285; // "v34" |
1308 | 0 | case '5': // 1 string to match. |
1309 | 0 | return 286; // "v35" |
1310 | 0 | case '6': // 1 string to match. |
1311 | 0 | return 287; // "v36" |
1312 | 0 | case '7': // 1 string to match. |
1313 | 0 | return 288; // "v37" |
1314 | 0 | case '8': // 1 string to match. |
1315 | 0 | return 289; // "v38" |
1316 | 0 | case '9': // 1 string to match. |
1317 | 0 | return 290; // "v39" |
1318 | 0 | } |
1319 | 0 | break; |
1320 | 0 | case '4': // 10 strings to match. |
1321 | 0 | switch (Name[2]) { |
1322 | 0 | default: break; |
1323 | 0 | case '0': // 1 string to match. |
1324 | 0 | return 291; // "v40" |
1325 | 0 | case '1': // 1 string to match. |
1326 | 0 | return 292; // "v41" |
1327 | 0 | case '2': // 1 string to match. |
1328 | 0 | return 293; // "v42" |
1329 | 0 | case '3': // 1 string to match. |
1330 | 0 | return 294; // "v43" |
1331 | 0 | case '4': // 1 string to match. |
1332 | 0 | return 295; // "v44" |
1333 | 0 | case '5': // 1 string to match. |
1334 | 0 | return 296; // "v45" |
1335 | 0 | case '6': // 1 string to match. |
1336 | 0 | return 297; // "v46" |
1337 | 0 | case '7': // 1 string to match. |
1338 | 0 | return 298; // "v47" |
1339 | 0 | case '8': // 1 string to match. |
1340 | 0 | return 299; // "v48" |
1341 | 0 | case '9': // 1 string to match. |
1342 | 0 | return 300; // "v49" |
1343 | 0 | } |
1344 | 0 | break; |
1345 | 0 | case '5': // 10 strings to match. |
1346 | 0 | switch (Name[2]) { |
1347 | 0 | default: break; |
1348 | 0 | case '0': // 1 string to match. |
1349 | 0 | return 301; // "v50" |
1350 | 0 | case '1': // 1 string to match. |
1351 | 0 | return 302; // "v51" |
1352 | 0 | case '2': // 1 string to match. |
1353 | 0 | return 303; // "v52" |
1354 | 0 | case '3': // 1 string to match. |
1355 | 0 | return 304; // "v53" |
1356 | 0 | case '4': // 1 string to match. |
1357 | 0 | return 305; // "v54" |
1358 | 0 | case '5': // 1 string to match. |
1359 | 0 | return 306; // "v55" |
1360 | 0 | case '6': // 1 string to match. |
1361 | 0 | return 307; // "v56" |
1362 | 0 | case '7': // 1 string to match. |
1363 | 0 | return 308; // "v57" |
1364 | 0 | case '8': // 1 string to match. |
1365 | 0 | return 309; // "v58" |
1366 | 0 | case '9': // 1 string to match. |
1367 | 0 | return 310; // "v59" |
1368 | 0 | } |
1369 | 0 | break; |
1370 | 0 | case '6': // 4 strings to match. |
1371 | 0 | switch (Name[2]) { |
1372 | 0 | default: break; |
1373 | 0 | case '0': // 1 string to match. |
1374 | 0 | return 311; // "v60" |
1375 | 0 | case '1': // 1 string to match. |
1376 | 0 | return 312; // "v61" |
1377 | 0 | case '2': // 1 string to match. |
1378 | 0 | return 313; // "v62" |
1379 | 0 | case '3': // 1 string to match. |
1380 | 0 | return 314; // "v63" |
1381 | 0 | } |
1382 | 0 | break; |
1383 | 0 | case 'i': // 1 string to match. |
1384 | 0 | if (Name[2] != 'x') |
1385 | 0 | break; |
1386 | 0 | return 6; // "vix" |
1387 | 0 | case 'm': // 15 strings to match. |
1388 | 0 | switch (Name[2]) { |
1389 | 0 | default: break; |
1390 | 0 | case '0': // 2 strings to match. |
1391 | 0 | return 315; // "vm0" |
1392 | 0 | case '1': // 1 string to match. |
1393 | 0 | return 316; // "vm1" |
1394 | 0 | case '2': // 2 strings to match. |
1395 | 0 | return 317; // "vm2" |
1396 | 0 | case '3': // 1 string to match. |
1397 | 0 | return 318; // "vm3" |
1398 | 0 | case '4': // 2 strings to match. |
1399 | 0 | return 319; // "vm4" |
1400 | 0 | case '5': // 1 string to match. |
1401 | 0 | return 320; // "vm5" |
1402 | 0 | case '6': // 2 strings to match. |
1403 | 0 | return 321; // "vm6" |
1404 | 0 | case '7': // 1 string to match. |
1405 | 0 | return 322; // "vm7" |
1406 | 0 | case '8': // 2 strings to match. |
1407 | 0 | return 323; // "vm8" |
1408 | 0 | case '9': // 1 string to match. |
1409 | 0 | return 324; // "vm9" |
1410 | 0 | } |
1411 | 0 | break; |
1412 | 0 | } |
1413 | 0 | break; |
1414 | 0 | } |
1415 | 0 | break; |
1416 | 0 | case 4: // 9 strings to match. |
1417 | 0 | if (memcmp(Name.data()+0, "vm1", 3) != 0) |
1418 | 0 | break; |
1419 | 0 | switch (Name[3]) { |
1420 | 0 | default: break; |
1421 | 0 | case '0': // 2 strings to match. |
1422 | 0 | return 325; // "vm10" |
1423 | 0 | case '1': // 1 string to match. |
1424 | 0 | return 326; // "vm11" |
1425 | 0 | case '2': // 2 strings to match. |
1426 | 0 | return 327; // "vm12" |
1427 | 0 | case '3': // 1 string to match. |
1428 | 0 | return 328; // "vm13" |
1429 | 0 | case '4': // 2 strings to match. |
1430 | 0 | return 329; // "vm14" |
1431 | 0 | case '5': // 1 string to match. |
1432 | 0 | return 330; // "vm15" |
1433 | 0 | } |
1434 | 0 | break; |
1435 | 0 | } |
1436 | 0 | return 0; |
1437 | 0 | } |
1438 | | |
1439 | | #endif // GET_REGISTER_MATCHER |
1440 | | |
1441 | | |
1442 | | #ifdef GET_SUBTARGET_FEATURE_NAME |
1443 | | #undef GET_SUBTARGET_FEATURE_NAME |
1444 | | |
1445 | | // User-level names for subtarget features that participate in |
1446 | | // instruction matching. |
1447 | | static const char *getSubtargetFeatureName(uint64_t Val) { |
1448 | | return "(unknown)"; |
1449 | | } |
1450 | | |
1451 | | #endif // GET_SUBTARGET_FEATURE_NAME |
1452 | | |
1453 | | |
1454 | | #ifdef GET_MATCHER_IMPLEMENTATION |
1455 | | #undef GET_MATCHER_IMPLEMENTATION |
1456 | | |
1457 | 0 | static void applyMnemonicAliases(StringRef &Mnemonic, const FeatureBitset &Features, unsigned VariantID) { |
1458 | 0 | switch (VariantID) { |
1459 | 0 | case 0: |
1460 | 0 | switch (Mnemonic.size()) { |
1461 | 0 | default: break; |
1462 | 0 | case 4: // 1 string to match. |
1463 | 0 | if (memcmp(Mnemonic.data()+0, "vgtl", 4) != 0) |
1464 | 0 | break; |
1465 | 0 | Mnemonic = "vgtl.zx"; // "vgtl" |
1466 | 0 | return; |
1467 | 0 | case 6: // 12 strings to match. |
1468 | 0 | switch (Mnemonic[0]) { |
1469 | 0 | default: break; |
1470 | 0 | case 'c': // 4 strings to match. |
1471 | 0 | if (memcmp(Mnemonic.data()+1, "mov.", 4) != 0) |
1472 | 0 | break; |
1473 | 0 | switch (Mnemonic[5]) { |
1474 | 0 | default: break; |
1475 | 0 | case 'd': // 1 string to match. |
1476 | 0 | Mnemonic = "cmov.d.at"; // "cmov.d" |
1477 | 0 | return; |
1478 | 0 | case 'l': // 1 string to match. |
1479 | 0 | Mnemonic = "cmov.l.at"; // "cmov.l" |
1480 | 0 | return; |
1481 | 0 | case 's': // 1 string to match. |
1482 | 0 | Mnemonic = "cmov.s.at"; // "cmov.s" |
1483 | 0 | return; |
1484 | 0 | case 'w': // 1 string to match. |
1485 | 0 | Mnemonic = "cmov.w.at"; // "cmov.w" |
1486 | 0 | return; |
1487 | 0 | } |
1488 | 0 | break; |
1489 | 0 | case 'v': // 8 strings to match. |
1490 | 0 | switch (Mnemonic[1]) { |
1491 | 0 | default: break; |
1492 | 0 | case 'f': // 4 strings to match. |
1493 | 0 | if (memcmp(Mnemonic.data()+2, "mk.", 3) != 0) |
1494 | 0 | break; |
1495 | 0 | switch (Mnemonic[5]) { |
1496 | 0 | default: break; |
1497 | 0 | case 'd': // 1 string to match. |
1498 | 0 | Mnemonic = "vfmk.d.at"; // "vfmk.d" |
1499 | 0 | return; |
1500 | 0 | case 'l': // 1 string to match. |
1501 | 0 | Mnemonic = "vfmk.l.at"; // "vfmk.l" |
1502 | 0 | return; |
1503 | 0 | case 's': // 1 string to match. |
1504 | 0 | Mnemonic = "pvfmk.s.up.at"; // "vfmk.s" |
1505 | 0 | return; |
1506 | 0 | case 'w': // 1 string to match. |
1507 | 0 | Mnemonic = "vfmk.w.at"; // "vfmk.w" |
1508 | 0 | return; |
1509 | 0 | } |
1510 | 0 | break; |
1511 | 0 | case 'm': // 1 string to match. |
1512 | 0 | if (memcmp(Mnemonic.data()+2, "rg.l", 4) != 0) |
1513 | 0 | break; |
1514 | 0 | Mnemonic = "vmrg"; // "vmrg.l" |
1515 | 0 | return; |
1516 | 0 | case 'r': // 1 string to match. |
1517 | 0 | if (memcmp(Mnemonic.data()+2, "cp.s", 4) != 0) |
1518 | 0 | break; |
1519 | 0 | Mnemonic = "pvrcp.up"; // "vrcp.s" |
1520 | 0 | return; |
1521 | 0 | case 's': // 2 strings to match. |
1522 | 0 | switch (Mnemonic[2]) { |
1523 | 0 | default: break; |
1524 | 0 | case 'l': // 1 string to match. |
1525 | 0 | if (memcmp(Mnemonic.data()+3, "a.w", 3) != 0) |
1526 | 0 | break; |
1527 | 0 | Mnemonic = "pvsla.lo"; // "vsla.w" |
1528 | 0 | return; |
1529 | 0 | case 'r': // 1 string to match. |
1530 | 0 | if (memcmp(Mnemonic.data()+3, "a.w", 3) != 0) |
1531 | 0 | break; |
1532 | 0 | Mnemonic = "pvsra.lo"; // "vsra.w" |
1533 | 0 | return; |
1534 | 0 | } |
1535 | 0 | break; |
1536 | 0 | } |
1537 | 0 | break; |
1538 | 0 | } |
1539 | 0 | break; |
1540 | 0 | case 7: // 19 strings to match. |
1541 | 0 | if (Mnemonic[0] != 'v') |
1542 | 0 | break; |
1543 | 0 | switch (Mnemonic[1]) { |
1544 | 0 | default: break; |
1545 | 0 | case 'a': // 2 strings to match. |
1546 | 0 | if (memcmp(Mnemonic.data()+2, "dd", 2) != 0) |
1547 | 0 | break; |
1548 | 0 | switch (Mnemonic[4]) { |
1549 | 0 | default: break; |
1550 | 0 | case 's': // 1 string to match. |
1551 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
1552 | 0 | break; |
1553 | 0 | Mnemonic = "pvadds.lo"; // "vadds.w" |
1554 | 0 | return; |
1555 | 0 | case 'u': // 1 string to match. |
1556 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
1557 | 0 | break; |
1558 | 0 | Mnemonic = "pvaddu.lo"; // "vaddu.w" |
1559 | 0 | return; |
1560 | 0 | } |
1561 | 0 | break; |
1562 | 0 | case 'c': // 2 strings to match. |
1563 | 0 | if (memcmp(Mnemonic.data()+2, "mp", 2) != 0) |
1564 | 0 | break; |
1565 | 0 | switch (Mnemonic[4]) { |
1566 | 0 | default: break; |
1567 | 0 | case 's': // 1 string to match. |
1568 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
1569 | 0 | break; |
1570 | 0 | Mnemonic = "pvcmps.lo"; // "vcmps.w" |
1571 | 0 | return; |
1572 | 0 | case 'u': // 1 string to match. |
1573 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
1574 | 0 | break; |
1575 | 0 | Mnemonic = "pvcmpu.lo"; // "vcmpu.w" |
1576 | 0 | return; |
1577 | 0 | } |
1578 | 0 | break; |
1579 | 0 | case 'd': // 1 string to match. |
1580 | 0 | if (memcmp(Mnemonic.data()+2, "ivs.w", 5) != 0) |
1581 | 0 | break; |
1582 | 0 | Mnemonic = "vdivs.w.zx"; // "vdivs.w" |
1583 | 0 | return; |
1584 | 0 | case 'f': // 8 strings to match. |
1585 | 0 | switch (Mnemonic[2]) { |
1586 | 0 | default: break; |
1587 | 0 | case 'a': // 1 string to match. |
1588 | 0 | if (memcmp(Mnemonic.data()+3, "dd.s", 4) != 0) |
1589 | 0 | break; |
1590 | 0 | Mnemonic = "pvfadd.up"; // "vfadd.s" |
1591 | 0 | return; |
1592 | 0 | case 'c': // 1 string to match. |
1593 | 0 | if (memcmp(Mnemonic.data()+3, "mp.s", 4) != 0) |
1594 | 0 | break; |
1595 | 0 | Mnemonic = "pvfcmp.up"; // "vfcmp.s" |
1596 | 0 | return; |
1597 | 0 | case 'm': // 5 strings to match. |
1598 | 0 | switch (Mnemonic[3]) { |
1599 | 0 | default: break; |
1600 | 0 | case 'a': // 2 strings to match. |
1601 | 0 | switch (Mnemonic[4]) { |
1602 | 0 | default: break; |
1603 | 0 | case 'd': // 1 string to match. |
1604 | 0 | if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) |
1605 | 0 | break; |
1606 | 0 | Mnemonic = "pvfmad.up"; // "vfmad.s" |
1607 | 0 | return; |
1608 | 0 | case 'x': // 1 string to match. |
1609 | 0 | if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) |
1610 | 0 | break; |
1611 | 0 | Mnemonic = "pvfmax.up"; // "vfmax.s" |
1612 | 0 | return; |
1613 | 0 | } |
1614 | 0 | break; |
1615 | 0 | case 'i': // 1 string to match. |
1616 | 0 | if (memcmp(Mnemonic.data()+4, "n.s", 3) != 0) |
1617 | 0 | break; |
1618 | 0 | Mnemonic = "pvfmin.up"; // "vfmin.s" |
1619 | 0 | return; |
1620 | 0 | case 's': // 1 string to match. |
1621 | 0 | if (memcmp(Mnemonic.data()+4, "b.s", 3) != 0) |
1622 | 0 | break; |
1623 | 0 | Mnemonic = "pvfmsb.up"; // "vfmsb.s" |
1624 | 0 | return; |
1625 | 0 | case 'u': // 1 string to match. |
1626 | 0 | if (memcmp(Mnemonic.data()+4, "l.s", 3) != 0) |
1627 | 0 | break; |
1628 | 0 | Mnemonic = "pvfmul.up"; // "vfmul.s" |
1629 | 0 | return; |
1630 | 0 | } |
1631 | 0 | break; |
1632 | 0 | case 's': // 1 string to match. |
1633 | 0 | if (memcmp(Mnemonic.data()+3, "ub.s", 4) != 0) |
1634 | 0 | break; |
1635 | 0 | Mnemonic = "pvfsub.up"; // "vfsub.s" |
1636 | 0 | return; |
1637 | 0 | } |
1638 | 0 | break; |
1639 | 0 | case 'g': // 1 string to match. |
1640 | 0 | if (memcmp(Mnemonic.data()+2, "tl.nc", 5) != 0) |
1641 | 0 | break; |
1642 | 0 | Mnemonic = "vgtl.zx.nc"; // "vgtl.nc" |
1643 | 0 | return; |
1644 | 0 | case 'm': // 3 strings to match. |
1645 | 0 | switch (Mnemonic[2]) { |
1646 | 0 | default: break; |
1647 | 0 | case 'a': // 1 string to match. |
1648 | 0 | if (memcmp(Mnemonic.data()+3, "xs.w", 4) != 0) |
1649 | 0 | break; |
1650 | 0 | Mnemonic = "pvmaxs.lo"; // "vmaxs.w" |
1651 | 0 | return; |
1652 | 0 | case 'i': // 1 string to match. |
1653 | 0 | if (memcmp(Mnemonic.data()+3, "ns.w", 4) != 0) |
1654 | 0 | break; |
1655 | 0 | Mnemonic = "pvmins.lo"; // "vmins.w" |
1656 | 0 | return; |
1657 | 0 | case 'u': // 1 string to match. |
1658 | 0 | if (memcmp(Mnemonic.data()+3, "ls.w", 4) != 0) |
1659 | 0 | break; |
1660 | 0 | Mnemonic = "vmuls.w.zx"; // "vmuls.w" |
1661 | 0 | return; |
1662 | 0 | } |
1663 | 0 | break; |
1664 | 0 | case 's': // 2 strings to match. |
1665 | 0 | if (memcmp(Mnemonic.data()+2, "ub", 2) != 0) |
1666 | 0 | break; |
1667 | 0 | switch (Mnemonic[4]) { |
1668 | 0 | default: break; |
1669 | 0 | case 's': // 1 string to match. |
1670 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
1671 | 0 | break; |
1672 | 0 | Mnemonic = "pvsubs.lo"; // "vsubs.w" |
1673 | 0 | return; |
1674 | 0 | case 'u': // 1 string to match. |
1675 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
1676 | 0 | break; |
1677 | 0 | Mnemonic = "pvsubu.lo"; // "vsubu.w" |
1678 | 0 | return; |
1679 | 0 | } |
1680 | 0 | break; |
1681 | 0 | } |
1682 | 0 | break; |
1683 | 0 | case 8: // 3 strings to match. |
1684 | 0 | if (Mnemonic[0] != 'v') |
1685 | 0 | break; |
1686 | 0 | switch (Mnemonic[1]) { |
1687 | 0 | default: break; |
1688 | 0 | case 'f': // 2 strings to match. |
1689 | 0 | if (memcmp(Mnemonic.data()+2, "nm", 2) != 0) |
1690 | 0 | break; |
1691 | 0 | switch (Mnemonic[4]) { |
1692 | 0 | default: break; |
1693 | 0 | case 'a': // 1 string to match. |
1694 | 0 | if (memcmp(Mnemonic.data()+5, "d.s", 3) != 0) |
1695 | 0 | break; |
1696 | 0 | Mnemonic = "pvfnmad.up"; // "vfnmad.s" |
1697 | 0 | return; |
1698 | 0 | case 's': // 1 string to match. |
1699 | 0 | if (memcmp(Mnemonic.data()+5, "b.s", 3) != 0) |
1700 | 0 | break; |
1701 | 0 | Mnemonic = "pvfnmsb.up"; // "vfnmsb.s" |
1702 | 0 | return; |
1703 | 0 | } |
1704 | 0 | break; |
1705 | 0 | case 'r': // 1 string to match. |
1706 | 0 | if (memcmp(Mnemonic.data()+2, "sqrt.s", 6) != 0) |
1707 | 0 | break; |
1708 | 0 | Mnemonic = "pvrsqrt.up"; // "vrsqrt.s" |
1709 | 0 | return; |
1710 | 0 | } |
1711 | 0 | break; |
1712 | 0 | case 9: // 10 strings to match. |
1713 | 0 | if (Mnemonic[0] != 'v') |
1714 | 0 | break; |
1715 | 0 | switch (Mnemonic[1]) { |
1716 | 0 | default: break; |
1717 | 0 | case 'f': // 8 strings to match. |
1718 | 0 | if (memcmp(Mnemonic.data()+2, "mk.s.", 5) != 0) |
1719 | 0 | break; |
1720 | 0 | switch (Mnemonic[7]) { |
1721 | 0 | default: break; |
1722 | 0 | case 'a': // 2 strings to match. |
1723 | 0 | switch (Mnemonic[8]) { |
1724 | 0 | default: break; |
1725 | 0 | case 'f': // 1 string to match. |
1726 | 0 | Mnemonic = "pvfmk.s.up.af"; // "vfmk.s.af" |
1727 | 0 | return; |
1728 | 0 | case 't': // 1 string to match. |
1729 | 0 | Mnemonic = "pvfmk.s.up.at"; // "vfmk.s.at" |
1730 | 0 | return; |
1731 | 0 | } |
1732 | 0 | break; |
1733 | 0 | case 'e': // 1 string to match. |
1734 | 0 | if (Mnemonic[8] != 'q') |
1735 | 0 | break; |
1736 | 0 | Mnemonic = "pvfmk.s.up.eq"; // "vfmk.s.eq" |
1737 | 0 | return; |
1738 | 0 | case 'g': // 2 strings to match. |
1739 | 0 | switch (Mnemonic[8]) { |
1740 | 0 | default: break; |
1741 | 0 | case 'e': // 1 string to match. |
1742 | 0 | Mnemonic = "pvfmk.s.up.ge"; // "vfmk.s.ge" |
1743 | 0 | return; |
1744 | 0 | case 't': // 1 string to match. |
1745 | 0 | Mnemonic = "pvfmk.s.up.gt"; // "vfmk.s.gt" |
1746 | 0 | return; |
1747 | 0 | } |
1748 | 0 | break; |
1749 | 0 | case 'l': // 2 strings to match. |
1750 | 0 | switch (Mnemonic[8]) { |
1751 | 0 | default: break; |
1752 | 0 | case 'e': // 1 string to match. |
1753 | 0 | Mnemonic = "pvfmk.s.up.le"; // "vfmk.s.le" |
1754 | 0 | return; |
1755 | 0 | case 't': // 1 string to match. |
1756 | 0 | Mnemonic = "pvfmk.s.up.lt"; // "vfmk.s.lt" |
1757 | 0 | return; |
1758 | 0 | } |
1759 | 0 | break; |
1760 | 0 | case 'n': // 1 string to match. |
1761 | 0 | if (Mnemonic[8] != 'e') |
1762 | 0 | break; |
1763 | 0 | Mnemonic = "pvfmk.s.up.ne"; // "vfmk.s.ne" |
1764 | 0 | return; |
1765 | 0 | } |
1766 | 0 | break; |
1767 | 0 | case 's': // 2 strings to match. |
1768 | 0 | switch (Mnemonic[2]) { |
1769 | 0 | default: break; |
1770 | 0 | case 'l': // 1 string to match. |
1771 | 0 | if (memcmp(Mnemonic.data()+3, "a.w.zx", 6) != 0) |
1772 | 0 | break; |
1773 | 0 | Mnemonic = "pvsla.lo"; // "vsla.w.zx" |
1774 | 0 | return; |
1775 | 0 | case 'r': // 1 string to match. |
1776 | 0 | if (memcmp(Mnemonic.data()+3, "a.w.zx", 6) != 0) |
1777 | 0 | break; |
1778 | 0 | Mnemonic = "pvsra.lo"; // "vsra.w.zx" |
1779 | 0 | return; |
1780 | 0 | } |
1781 | 0 | break; |
1782 | 0 | } |
1783 | 0 | break; |
1784 | 0 | case 10: // 11 strings to match. |
1785 | 0 | switch (Mnemonic[0]) { |
1786 | 0 | default: break; |
1787 | 0 | case 'p': // 4 strings to match. |
1788 | 0 | if (memcmp(Mnemonic.data()+1, "vfmk.", 5) != 0) |
1789 | 0 | break; |
1790 | 0 | switch (Mnemonic[6]) { |
1791 | 0 | default: break; |
1792 | 0 | case 's': // 2 strings to match. |
1793 | 0 | if (Mnemonic[7] != '.') |
1794 | 0 | break; |
1795 | 0 | switch (Mnemonic[8]) { |
1796 | 0 | default: break; |
1797 | 0 | case 'l': // 1 string to match. |
1798 | 0 | if (Mnemonic[9] != 'o') |
1799 | 0 | break; |
1800 | 0 | Mnemonic = "pvfmk.s.lo.at"; // "pvfmk.s.lo" |
1801 | 0 | return; |
1802 | 0 | case 'u': // 1 string to match. |
1803 | 0 | if (Mnemonic[9] != 'p') |
1804 | 0 | break; |
1805 | 0 | Mnemonic = "pvfmk.s.up.at"; // "pvfmk.s.up" |
1806 | 0 | return; |
1807 | 0 | } |
1808 | 0 | break; |
1809 | 0 | case 'w': // 2 strings to match. |
1810 | 0 | if (Mnemonic[7] != '.') |
1811 | 0 | break; |
1812 | 0 | switch (Mnemonic[8]) { |
1813 | 0 | default: break; |
1814 | 0 | case 'l': // 1 string to match. |
1815 | 0 | if (Mnemonic[9] != 'o') |
1816 | 0 | break; |
1817 | 0 | Mnemonic = "vfmk.w.at"; // "pvfmk.w.lo" |
1818 | 0 | return; |
1819 | 0 | case 'u': // 1 string to match. |
1820 | 0 | if (Mnemonic[9] != 'p') |
1821 | 0 | break; |
1822 | 0 | Mnemonic = "pvfmk.w.up.at"; // "pvfmk.w.up" |
1823 | 0 | return; |
1824 | 0 | } |
1825 | 0 | break; |
1826 | 0 | } |
1827 | 0 | break; |
1828 | 0 | case 'v': // 7 strings to match. |
1829 | 0 | switch (Mnemonic[1]) { |
1830 | 0 | default: break; |
1831 | 0 | case 'a': // 1 string to match. |
1832 | 0 | if (memcmp(Mnemonic.data()+2, "dds.w.zx", 8) != 0) |
1833 | 0 | break; |
1834 | 0 | Mnemonic = "pvadds.lo"; // "vadds.w.zx" |
1835 | 0 | return; |
1836 | 0 | case 'c': // 1 string to match. |
1837 | 0 | if (memcmp(Mnemonic.data()+2, "mps.w.zx", 8) != 0) |
1838 | 0 | break; |
1839 | 0 | Mnemonic = "pvcmps.lo"; // "vcmps.w.zx" |
1840 | 0 | return; |
1841 | 0 | case 'f': // 2 strings to match. |
1842 | 0 | if (memcmp(Mnemonic.data()+2, "mk.s.n", 6) != 0) |
1843 | 0 | break; |
1844 | 0 | switch (Mnemonic[8]) { |
1845 | 0 | default: break; |
1846 | 0 | case 'a': // 1 string to match. |
1847 | 0 | if (Mnemonic[9] != 'n') |
1848 | 0 | break; |
1849 | 0 | Mnemonic = "pvfmk.s.up.nan"; // "vfmk.s.nan" |
1850 | 0 | return; |
1851 | 0 | case 'u': // 1 string to match. |
1852 | 0 | if (Mnemonic[9] != 'm') |
1853 | 0 | break; |
1854 | 0 | Mnemonic = "pvfmk.s.up.num"; // "vfmk.s.num" |
1855 | 0 | return; |
1856 | 0 | } |
1857 | 0 | break; |
1858 | 0 | case 'm': // 2 strings to match. |
1859 | 0 | switch (Mnemonic[2]) { |
1860 | 0 | default: break; |
1861 | 0 | case 'a': // 1 string to match. |
1862 | 0 | if (memcmp(Mnemonic.data()+3, "xs.w.zx", 7) != 0) |
1863 | 0 | break; |
1864 | 0 | Mnemonic = "pvmaxs.lo"; // "vmaxs.w.zx" |
1865 | 0 | return; |
1866 | 0 | case 'i': // 1 string to match. |
1867 | 0 | if (memcmp(Mnemonic.data()+3, "ns.w.zx", 7) != 0) |
1868 | 0 | break; |
1869 | 0 | Mnemonic = "pvmins.lo"; // "vmins.w.zx" |
1870 | 0 | return; |
1871 | 0 | } |
1872 | 0 | break; |
1873 | 0 | case 's': // 1 string to match. |
1874 | 0 | if (memcmp(Mnemonic.data()+2, "ubs.w.zx", 8) != 0) |
1875 | 0 | break; |
1876 | 0 | Mnemonic = "pvsubs.lo"; // "vsubs.w.zx" |
1877 | 0 | return; |
1878 | 0 | } |
1879 | 0 | break; |
1880 | 0 | } |
1881 | 0 | break; |
1882 | 0 | case 11: // 4 strings to match. |
1883 | 0 | if (memcmp(Mnemonic.data()+0, "pvs", 3) != 0) |
1884 | 0 | break; |
1885 | 0 | switch (Mnemonic[3]) { |
1886 | 0 | default: break; |
1887 | 0 | case 'l': // 2 strings to match. |
1888 | 0 | if (memcmp(Mnemonic.data()+4, "a.lo.", 5) != 0) |
1889 | 0 | break; |
1890 | 0 | switch (Mnemonic[9]) { |
1891 | 0 | default: break; |
1892 | 0 | case 's': // 1 string to match. |
1893 | 0 | if (Mnemonic[10] != 'x') |
1894 | 0 | break; |
1895 | 0 | Mnemonic = "vsla.w.sx"; // "pvsla.lo.sx" |
1896 | 0 | return; |
1897 | 0 | case 'z': // 1 string to match. |
1898 | 0 | if (Mnemonic[10] != 'x') |
1899 | 0 | break; |
1900 | 0 | Mnemonic = "pvsla.lo"; // "pvsla.lo.zx" |
1901 | 0 | return; |
1902 | 0 | } |
1903 | 0 | break; |
1904 | 0 | case 'r': // 2 strings to match. |
1905 | 0 | if (memcmp(Mnemonic.data()+4, "a.lo.", 5) != 0) |
1906 | 0 | break; |
1907 | 0 | switch (Mnemonic[9]) { |
1908 | 0 | default: break; |
1909 | 0 | case 's': // 1 string to match. |
1910 | 0 | if (Mnemonic[10] != 'x') |
1911 | 0 | break; |
1912 | 0 | Mnemonic = "vsra.w.sx"; // "pvsra.lo.sx" |
1913 | 0 | return; |
1914 | 0 | case 'z': // 1 string to match. |
1915 | 0 | if (Mnemonic[10] != 'x') |
1916 | 0 | break; |
1917 | 0 | Mnemonic = "pvsra.lo"; // "pvsra.lo.zx" |
1918 | 0 | return; |
1919 | 0 | } |
1920 | 0 | break; |
1921 | 0 | } |
1922 | 0 | break; |
1923 | 0 | case 12: // 17 strings to match. |
1924 | 0 | switch (Mnemonic[0]) { |
1925 | 0 | default: break; |
1926 | 0 | case 'p': // 10 strings to match. |
1927 | 0 | if (Mnemonic[1] != 'v') |
1928 | 0 | break; |
1929 | 0 | switch (Mnemonic[2]) { |
1930 | 0 | default: break; |
1931 | 0 | case 'a': // 2 strings to match. |
1932 | 0 | if (memcmp(Mnemonic.data()+3, "dds.lo.", 7) != 0) |
1933 | 0 | break; |
1934 | 0 | switch (Mnemonic[10]) { |
1935 | 0 | default: break; |
1936 | 0 | case 's': // 1 string to match. |
1937 | 0 | if (Mnemonic[11] != 'x') |
1938 | 0 | break; |
1939 | 0 | Mnemonic = "vadds.w.sx"; // "pvadds.lo.sx" |
1940 | 0 | return; |
1941 | 0 | case 'z': // 1 string to match. |
1942 | 0 | if (Mnemonic[11] != 'x') |
1943 | 0 | break; |
1944 | 0 | Mnemonic = "pvadds.lo"; // "pvadds.lo.zx" |
1945 | 0 | return; |
1946 | 0 | } |
1947 | 0 | break; |
1948 | 0 | case 'c': // 2 strings to match. |
1949 | 0 | if (memcmp(Mnemonic.data()+3, "mps.lo.", 7) != 0) |
1950 | 0 | break; |
1951 | 0 | switch (Mnemonic[10]) { |
1952 | 0 | default: break; |
1953 | 0 | case 's': // 1 string to match. |
1954 | 0 | if (Mnemonic[11] != 'x') |
1955 | 0 | break; |
1956 | 0 | Mnemonic = "vcmps.w.sx"; // "pvcmps.lo.sx" |
1957 | 0 | return; |
1958 | 0 | case 'z': // 1 string to match. |
1959 | 0 | if (Mnemonic[11] != 'x') |
1960 | 0 | break; |
1961 | 0 | Mnemonic = "pvcmps.lo"; // "pvcmps.lo.zx" |
1962 | 0 | return; |
1963 | 0 | } |
1964 | 0 | break; |
1965 | 0 | case 'm': // 4 strings to match. |
1966 | 0 | switch (Mnemonic[3]) { |
1967 | 0 | default: break; |
1968 | 0 | case 'a': // 2 strings to match. |
1969 | 0 | if (memcmp(Mnemonic.data()+4, "xs.lo.", 6) != 0) |
1970 | 0 | break; |
1971 | 0 | switch (Mnemonic[10]) { |
1972 | 0 | default: break; |
1973 | 0 | case 's': // 1 string to match. |
1974 | 0 | if (Mnemonic[11] != 'x') |
1975 | 0 | break; |
1976 | 0 | Mnemonic = "vmaxs.w.sx"; // "pvmaxs.lo.sx" |
1977 | 0 | return; |
1978 | 0 | case 'z': // 1 string to match. |
1979 | 0 | if (Mnemonic[11] != 'x') |
1980 | 0 | break; |
1981 | 0 | Mnemonic = "pvmaxs.lo"; // "pvmaxs.lo.zx" |
1982 | 0 | return; |
1983 | 0 | } |
1984 | 0 | break; |
1985 | 0 | case 'i': // 2 strings to match. |
1986 | 0 | if (memcmp(Mnemonic.data()+4, "ns.lo.", 6) != 0) |
1987 | 0 | break; |
1988 | 0 | switch (Mnemonic[10]) { |
1989 | 0 | default: break; |
1990 | 0 | case 's': // 1 string to match. |
1991 | 0 | if (Mnemonic[11] != 'x') |
1992 | 0 | break; |
1993 | 0 | Mnemonic = "vmins.w.sx"; // "pvmins.lo.sx" |
1994 | 0 | return; |
1995 | 0 | case 'z': // 1 string to match. |
1996 | 0 | if (Mnemonic[11] != 'x') |
1997 | 0 | break; |
1998 | 0 | Mnemonic = "pvmins.lo"; // "pvmins.lo.zx" |
1999 | 0 | return; |
2000 | 0 | } |
2001 | 0 | break; |
2002 | 0 | } |
2003 | 0 | break; |
2004 | 0 | case 's': // 2 strings to match. |
2005 | 0 | if (memcmp(Mnemonic.data()+3, "ubs.lo.", 7) != 0) |
2006 | 0 | break; |
2007 | 0 | switch (Mnemonic[10]) { |
2008 | 0 | default: break; |
2009 | 0 | case 's': // 1 string to match. |
2010 | 0 | if (Mnemonic[11] != 'x') |
2011 | 0 | break; |
2012 | 0 | Mnemonic = "vsubs.w.sx"; // "pvsubs.lo.sx" |
2013 | 0 | return; |
2014 | 0 | case 'z': // 1 string to match. |
2015 | 0 | if (Mnemonic[11] != 'x') |
2016 | 0 | break; |
2017 | 0 | Mnemonic = "pvsubs.lo"; // "pvsubs.lo.zx" |
2018 | 0 | return; |
2019 | 0 | } |
2020 | 0 | break; |
2021 | 0 | } |
2022 | 0 | break; |
2023 | 0 | case 'v': // 7 strings to match. |
2024 | 0 | switch (Mnemonic[1]) { |
2025 | 0 | default: break; |
2026 | 0 | case 'f': // 6 strings to match. |
2027 | 0 | if (memcmp(Mnemonic.data()+2, "mk.s.", 5) != 0) |
2028 | 0 | break; |
2029 | 0 | switch (Mnemonic[7]) { |
2030 | 0 | default: break; |
2031 | 0 | case 'e': // 1 string to match. |
2032 | 0 | if (memcmp(Mnemonic.data()+8, "qnan", 4) != 0) |
2033 | 0 | break; |
2034 | 0 | Mnemonic = "pvfmk.s.up.eqnan"; // "vfmk.s.eqnan" |
2035 | 0 | return; |
2036 | 0 | case 'g': // 2 strings to match. |
2037 | 0 | switch (Mnemonic[8]) { |
2038 | 0 | default: break; |
2039 | 0 | case 'e': // 1 string to match. |
2040 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2041 | 0 | break; |
2042 | 0 | Mnemonic = "pvfmk.s.up.genan"; // "vfmk.s.genan" |
2043 | 0 | return; |
2044 | 0 | case 't': // 1 string to match. |
2045 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2046 | 0 | break; |
2047 | 0 | Mnemonic = "pvfmk.s.up.gtnan"; // "vfmk.s.gtnan" |
2048 | 0 | return; |
2049 | 0 | } |
2050 | 0 | break; |
2051 | 0 | case 'l': // 2 strings to match. |
2052 | 0 | switch (Mnemonic[8]) { |
2053 | 0 | default: break; |
2054 | 0 | case 'e': // 1 string to match. |
2055 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2056 | 0 | break; |
2057 | 0 | Mnemonic = "pvfmk.s.up.lenan"; // "vfmk.s.lenan" |
2058 | 0 | return; |
2059 | 0 | case 't': // 1 string to match. |
2060 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2061 | 0 | break; |
2062 | 0 | Mnemonic = "pvfmk.s.up.ltnan"; // "vfmk.s.ltnan" |
2063 | 0 | return; |
2064 | 0 | } |
2065 | 0 | break; |
2066 | 0 | case 'n': // 1 string to match. |
2067 | 0 | if (memcmp(Mnemonic.data()+8, "enan", 4) != 0) |
2068 | 0 | break; |
2069 | 0 | Mnemonic = "pvfmk.s.up.nenan"; // "vfmk.s.nenan" |
2070 | 0 | return; |
2071 | 0 | } |
2072 | 0 | break; |
2073 | 0 | case 'r': // 1 string to match. |
2074 | 0 | if (memcmp(Mnemonic.data()+2, "sqrt.s.nex", 10) != 0) |
2075 | 0 | break; |
2076 | 0 | Mnemonic = "pvrsqrt.up.nex"; // "vrsqrt.s.nex" |
2077 | 0 | return; |
2078 | 0 | } |
2079 | 0 | break; |
2080 | 0 | } |
2081 | 0 | break; |
2082 | 0 | case 13: // 8 strings to match. |
2083 | 0 | if (memcmp(Mnemonic.data()+0, "pvfmk.w.lo.", 11) != 0) |
2084 | 0 | break; |
2085 | 0 | switch (Mnemonic[11]) { |
2086 | 0 | default: break; |
2087 | 0 | case 'a': // 2 strings to match. |
2088 | 0 | switch (Mnemonic[12]) { |
2089 | 0 | default: break; |
2090 | 0 | case 'f': // 1 string to match. |
2091 | 0 | Mnemonic = "vfmk.w.af"; // "pvfmk.w.lo.af" |
2092 | 0 | return; |
2093 | 0 | case 't': // 1 string to match. |
2094 | 0 | Mnemonic = "vfmk.w.at"; // "pvfmk.w.lo.at" |
2095 | 0 | return; |
2096 | 0 | } |
2097 | 0 | break; |
2098 | 0 | case 'e': // 1 string to match. |
2099 | 0 | if (Mnemonic[12] != 'q') |
2100 | 0 | break; |
2101 | 0 | Mnemonic = "vfmk.w.eq"; // "pvfmk.w.lo.eq" |
2102 | 0 | return; |
2103 | 0 | case 'g': // 2 strings to match. |
2104 | 0 | switch (Mnemonic[12]) { |
2105 | 0 | default: break; |
2106 | 0 | case 'e': // 1 string to match. |
2107 | 0 | Mnemonic = "vfmk.w.ge"; // "pvfmk.w.lo.ge" |
2108 | 0 | return; |
2109 | 0 | case 't': // 1 string to match. |
2110 | 0 | Mnemonic = "vfmk.w.gt"; // "pvfmk.w.lo.gt" |
2111 | 0 | return; |
2112 | 0 | } |
2113 | 0 | break; |
2114 | 0 | case 'l': // 2 strings to match. |
2115 | 0 | switch (Mnemonic[12]) { |
2116 | 0 | default: break; |
2117 | 0 | case 'e': // 1 string to match. |
2118 | 0 | Mnemonic = "vfmk.w.le"; // "pvfmk.w.lo.le" |
2119 | 0 | return; |
2120 | 0 | case 't': // 1 string to match. |
2121 | 0 | Mnemonic = "vfmk.w.lt"; // "pvfmk.w.lo.lt" |
2122 | 0 | return; |
2123 | 0 | } |
2124 | 0 | break; |
2125 | 0 | case 'n': // 1 string to match. |
2126 | 0 | if (Mnemonic[12] != 'e') |
2127 | 0 | break; |
2128 | 0 | Mnemonic = "vfmk.w.ne"; // "pvfmk.w.lo.ne" |
2129 | 0 | return; |
2130 | 0 | } |
2131 | 0 | break; |
2132 | 0 | } |
2133 | 0 | break; |
2134 | 0 | } |
2135 | 0 | switch (Mnemonic.size()) { |
2136 | 0 | default: break; |
2137 | 0 | case 4: // 1 string to match. |
2138 | 0 | if (memcmp(Mnemonic.data()+0, "vgtl", 4) != 0) |
2139 | 0 | break; |
2140 | 0 | Mnemonic = "vgtl.zx"; // "vgtl" |
2141 | 0 | return; |
2142 | 0 | case 6: // 12 strings to match. |
2143 | 0 | switch (Mnemonic[0]) { |
2144 | 0 | default: break; |
2145 | 0 | case 'c': // 4 strings to match. |
2146 | 0 | if (memcmp(Mnemonic.data()+1, "mov.", 4) != 0) |
2147 | 0 | break; |
2148 | 0 | switch (Mnemonic[5]) { |
2149 | 0 | default: break; |
2150 | 0 | case 'd': // 1 string to match. |
2151 | 0 | Mnemonic = "cmov.d.at"; // "cmov.d" |
2152 | 0 | return; |
2153 | 0 | case 'l': // 1 string to match. |
2154 | 0 | Mnemonic = "cmov.l.at"; // "cmov.l" |
2155 | 0 | return; |
2156 | 0 | case 's': // 1 string to match. |
2157 | 0 | Mnemonic = "cmov.s.at"; // "cmov.s" |
2158 | 0 | return; |
2159 | 0 | case 'w': // 1 string to match. |
2160 | 0 | Mnemonic = "cmov.w.at"; // "cmov.w" |
2161 | 0 | return; |
2162 | 0 | } |
2163 | 0 | break; |
2164 | 0 | case 'v': // 8 strings to match. |
2165 | 0 | switch (Mnemonic[1]) { |
2166 | 0 | default: break; |
2167 | 0 | case 'f': // 4 strings to match. |
2168 | 0 | if (memcmp(Mnemonic.data()+2, "mk.", 3) != 0) |
2169 | 0 | break; |
2170 | 0 | switch (Mnemonic[5]) { |
2171 | 0 | default: break; |
2172 | 0 | case 'd': // 1 string to match. |
2173 | 0 | Mnemonic = "vfmk.d.at"; // "vfmk.d" |
2174 | 0 | return; |
2175 | 0 | case 'l': // 1 string to match. |
2176 | 0 | Mnemonic = "vfmk.l.at"; // "vfmk.l" |
2177 | 0 | return; |
2178 | 0 | case 's': // 1 string to match. |
2179 | 0 | Mnemonic = "pvfmk.s.up.at"; // "vfmk.s" |
2180 | 0 | return; |
2181 | 0 | case 'w': // 1 string to match. |
2182 | 0 | Mnemonic = "vfmk.w.at"; // "vfmk.w" |
2183 | 0 | return; |
2184 | 0 | } |
2185 | 0 | break; |
2186 | 0 | case 'm': // 1 string to match. |
2187 | 0 | if (memcmp(Mnemonic.data()+2, "rg.l", 4) != 0) |
2188 | 0 | break; |
2189 | 0 | Mnemonic = "vmrg"; // "vmrg.l" |
2190 | 0 | return; |
2191 | 0 | case 'r': // 1 string to match. |
2192 | 0 | if (memcmp(Mnemonic.data()+2, "cp.s", 4) != 0) |
2193 | 0 | break; |
2194 | 0 | Mnemonic = "pvrcp.up"; // "vrcp.s" |
2195 | 0 | return; |
2196 | 0 | case 's': // 2 strings to match. |
2197 | 0 | switch (Mnemonic[2]) { |
2198 | 0 | default: break; |
2199 | 0 | case 'l': // 1 string to match. |
2200 | 0 | if (memcmp(Mnemonic.data()+3, "a.w", 3) != 0) |
2201 | 0 | break; |
2202 | 0 | Mnemonic = "pvsla.lo"; // "vsla.w" |
2203 | 0 | return; |
2204 | 0 | case 'r': // 1 string to match. |
2205 | 0 | if (memcmp(Mnemonic.data()+3, "a.w", 3) != 0) |
2206 | 0 | break; |
2207 | 0 | Mnemonic = "pvsra.lo"; // "vsra.w" |
2208 | 0 | return; |
2209 | 0 | } |
2210 | 0 | break; |
2211 | 0 | } |
2212 | 0 | break; |
2213 | 0 | } |
2214 | 0 | break; |
2215 | 0 | case 7: // 19 strings to match. |
2216 | 0 | if (Mnemonic[0] != 'v') |
2217 | 0 | break; |
2218 | 0 | switch (Mnemonic[1]) { |
2219 | 0 | default: break; |
2220 | 0 | case 'a': // 2 strings to match. |
2221 | 0 | if (memcmp(Mnemonic.data()+2, "dd", 2) != 0) |
2222 | 0 | break; |
2223 | 0 | switch (Mnemonic[4]) { |
2224 | 0 | default: break; |
2225 | 0 | case 's': // 1 string to match. |
2226 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
2227 | 0 | break; |
2228 | 0 | Mnemonic = "pvadds.lo"; // "vadds.w" |
2229 | 0 | return; |
2230 | 0 | case 'u': // 1 string to match. |
2231 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
2232 | 0 | break; |
2233 | 0 | Mnemonic = "pvaddu.lo"; // "vaddu.w" |
2234 | 0 | return; |
2235 | 0 | } |
2236 | 0 | break; |
2237 | 0 | case 'c': // 2 strings to match. |
2238 | 0 | if (memcmp(Mnemonic.data()+2, "mp", 2) != 0) |
2239 | 0 | break; |
2240 | 0 | switch (Mnemonic[4]) { |
2241 | 0 | default: break; |
2242 | 0 | case 's': // 1 string to match. |
2243 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
2244 | 0 | break; |
2245 | 0 | Mnemonic = "pvcmps.lo"; // "vcmps.w" |
2246 | 0 | return; |
2247 | 0 | case 'u': // 1 string to match. |
2248 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
2249 | 0 | break; |
2250 | 0 | Mnemonic = "pvcmpu.lo"; // "vcmpu.w" |
2251 | 0 | return; |
2252 | 0 | } |
2253 | 0 | break; |
2254 | 0 | case 'd': // 1 string to match. |
2255 | 0 | if (memcmp(Mnemonic.data()+2, "ivs.w", 5) != 0) |
2256 | 0 | break; |
2257 | 0 | Mnemonic = "vdivs.w.zx"; // "vdivs.w" |
2258 | 0 | return; |
2259 | 0 | case 'f': // 8 strings to match. |
2260 | 0 | switch (Mnemonic[2]) { |
2261 | 0 | default: break; |
2262 | 0 | case 'a': // 1 string to match. |
2263 | 0 | if (memcmp(Mnemonic.data()+3, "dd.s", 4) != 0) |
2264 | 0 | break; |
2265 | 0 | Mnemonic = "pvfadd.up"; // "vfadd.s" |
2266 | 0 | return; |
2267 | 0 | case 'c': // 1 string to match. |
2268 | 0 | if (memcmp(Mnemonic.data()+3, "mp.s", 4) != 0) |
2269 | 0 | break; |
2270 | 0 | Mnemonic = "pvfcmp.up"; // "vfcmp.s" |
2271 | 0 | return; |
2272 | 0 | case 'm': // 5 strings to match. |
2273 | 0 | switch (Mnemonic[3]) { |
2274 | 0 | default: break; |
2275 | 0 | case 'a': // 2 strings to match. |
2276 | 0 | switch (Mnemonic[4]) { |
2277 | 0 | default: break; |
2278 | 0 | case 'd': // 1 string to match. |
2279 | 0 | if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) |
2280 | 0 | break; |
2281 | 0 | Mnemonic = "pvfmad.up"; // "vfmad.s" |
2282 | 0 | return; |
2283 | 0 | case 'x': // 1 string to match. |
2284 | 0 | if (memcmp(Mnemonic.data()+5, ".s", 2) != 0) |
2285 | 0 | break; |
2286 | 0 | Mnemonic = "pvfmax.up"; // "vfmax.s" |
2287 | 0 | return; |
2288 | 0 | } |
2289 | 0 | break; |
2290 | 0 | case 'i': // 1 string to match. |
2291 | 0 | if (memcmp(Mnemonic.data()+4, "n.s", 3) != 0) |
2292 | 0 | break; |
2293 | 0 | Mnemonic = "pvfmin.up"; // "vfmin.s" |
2294 | 0 | return; |
2295 | 0 | case 's': // 1 string to match. |
2296 | 0 | if (memcmp(Mnemonic.data()+4, "b.s", 3) != 0) |
2297 | 0 | break; |
2298 | 0 | Mnemonic = "pvfmsb.up"; // "vfmsb.s" |
2299 | 0 | return; |
2300 | 0 | case 'u': // 1 string to match. |
2301 | 0 | if (memcmp(Mnemonic.data()+4, "l.s", 3) != 0) |
2302 | 0 | break; |
2303 | 0 | Mnemonic = "pvfmul.up"; // "vfmul.s" |
2304 | 0 | return; |
2305 | 0 | } |
2306 | 0 | break; |
2307 | 0 | case 's': // 1 string to match. |
2308 | 0 | if (memcmp(Mnemonic.data()+3, "ub.s", 4) != 0) |
2309 | 0 | break; |
2310 | 0 | Mnemonic = "pvfsub.up"; // "vfsub.s" |
2311 | 0 | return; |
2312 | 0 | } |
2313 | 0 | break; |
2314 | 0 | case 'g': // 1 string to match. |
2315 | 0 | if (memcmp(Mnemonic.data()+2, "tl.nc", 5) != 0) |
2316 | 0 | break; |
2317 | 0 | Mnemonic = "vgtl.zx.nc"; // "vgtl.nc" |
2318 | 0 | return; |
2319 | 0 | case 'm': // 3 strings to match. |
2320 | 0 | switch (Mnemonic[2]) { |
2321 | 0 | default: break; |
2322 | 0 | case 'a': // 1 string to match. |
2323 | 0 | if (memcmp(Mnemonic.data()+3, "xs.w", 4) != 0) |
2324 | 0 | break; |
2325 | 0 | Mnemonic = "pvmaxs.lo"; // "vmaxs.w" |
2326 | 0 | return; |
2327 | 0 | case 'i': // 1 string to match. |
2328 | 0 | if (memcmp(Mnemonic.data()+3, "ns.w", 4) != 0) |
2329 | 0 | break; |
2330 | 0 | Mnemonic = "pvmins.lo"; // "vmins.w" |
2331 | 0 | return; |
2332 | 0 | case 'u': // 1 string to match. |
2333 | 0 | if (memcmp(Mnemonic.data()+3, "ls.w", 4) != 0) |
2334 | 0 | break; |
2335 | 0 | Mnemonic = "vmuls.w.zx"; // "vmuls.w" |
2336 | 0 | return; |
2337 | 0 | } |
2338 | 0 | break; |
2339 | 0 | case 's': // 2 strings to match. |
2340 | 0 | if (memcmp(Mnemonic.data()+2, "ub", 2) != 0) |
2341 | 0 | break; |
2342 | 0 | switch (Mnemonic[4]) { |
2343 | 0 | default: break; |
2344 | 0 | case 's': // 1 string to match. |
2345 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
2346 | 0 | break; |
2347 | 0 | Mnemonic = "pvsubs.lo"; // "vsubs.w" |
2348 | 0 | return; |
2349 | 0 | case 'u': // 1 string to match. |
2350 | 0 | if (memcmp(Mnemonic.data()+5, ".w", 2) != 0) |
2351 | 0 | break; |
2352 | 0 | Mnemonic = "pvsubu.lo"; // "vsubu.w" |
2353 | 0 | return; |
2354 | 0 | } |
2355 | 0 | break; |
2356 | 0 | } |
2357 | 0 | break; |
2358 | 0 | case 8: // 3 strings to match. |
2359 | 0 | if (Mnemonic[0] != 'v') |
2360 | 0 | break; |
2361 | 0 | switch (Mnemonic[1]) { |
2362 | 0 | default: break; |
2363 | 0 | case 'f': // 2 strings to match. |
2364 | 0 | if (memcmp(Mnemonic.data()+2, "nm", 2) != 0) |
2365 | 0 | break; |
2366 | 0 | switch (Mnemonic[4]) { |
2367 | 0 | default: break; |
2368 | 0 | case 'a': // 1 string to match. |
2369 | 0 | if (memcmp(Mnemonic.data()+5, "d.s", 3) != 0) |
2370 | 0 | break; |
2371 | 0 | Mnemonic = "pvfnmad.up"; // "vfnmad.s" |
2372 | 0 | return; |
2373 | 0 | case 's': // 1 string to match. |
2374 | 0 | if (memcmp(Mnemonic.data()+5, "b.s", 3) != 0) |
2375 | 0 | break; |
2376 | 0 | Mnemonic = "pvfnmsb.up"; // "vfnmsb.s" |
2377 | 0 | return; |
2378 | 0 | } |
2379 | 0 | break; |
2380 | 0 | case 'r': // 1 string to match. |
2381 | 0 | if (memcmp(Mnemonic.data()+2, "sqrt.s", 6) != 0) |
2382 | 0 | break; |
2383 | 0 | Mnemonic = "pvrsqrt.up"; // "vrsqrt.s" |
2384 | 0 | return; |
2385 | 0 | } |
2386 | 0 | break; |
2387 | 0 | case 9: // 10 strings to match. |
2388 | 0 | if (Mnemonic[0] != 'v') |
2389 | 0 | break; |
2390 | 0 | switch (Mnemonic[1]) { |
2391 | 0 | default: break; |
2392 | 0 | case 'f': // 8 strings to match. |
2393 | 0 | if (memcmp(Mnemonic.data()+2, "mk.s.", 5) != 0) |
2394 | 0 | break; |
2395 | 0 | switch (Mnemonic[7]) { |
2396 | 0 | default: break; |
2397 | 0 | case 'a': // 2 strings to match. |
2398 | 0 | switch (Mnemonic[8]) { |
2399 | 0 | default: break; |
2400 | 0 | case 'f': // 1 string to match. |
2401 | 0 | Mnemonic = "pvfmk.s.up.af"; // "vfmk.s.af" |
2402 | 0 | return; |
2403 | 0 | case 't': // 1 string to match. |
2404 | 0 | Mnemonic = "pvfmk.s.up.at"; // "vfmk.s.at" |
2405 | 0 | return; |
2406 | 0 | } |
2407 | 0 | break; |
2408 | 0 | case 'e': // 1 string to match. |
2409 | 0 | if (Mnemonic[8] != 'q') |
2410 | 0 | break; |
2411 | 0 | Mnemonic = "pvfmk.s.up.eq"; // "vfmk.s.eq" |
2412 | 0 | return; |
2413 | 0 | case 'g': // 2 strings to match. |
2414 | 0 | switch (Mnemonic[8]) { |
2415 | 0 | default: break; |
2416 | 0 | case 'e': // 1 string to match. |
2417 | 0 | Mnemonic = "pvfmk.s.up.ge"; // "vfmk.s.ge" |
2418 | 0 | return; |
2419 | 0 | case 't': // 1 string to match. |
2420 | 0 | Mnemonic = "pvfmk.s.up.gt"; // "vfmk.s.gt" |
2421 | 0 | return; |
2422 | 0 | } |
2423 | 0 | break; |
2424 | 0 | case 'l': // 2 strings to match. |
2425 | 0 | switch (Mnemonic[8]) { |
2426 | 0 | default: break; |
2427 | 0 | case 'e': // 1 string to match. |
2428 | 0 | Mnemonic = "pvfmk.s.up.le"; // "vfmk.s.le" |
2429 | 0 | return; |
2430 | 0 | case 't': // 1 string to match. |
2431 | 0 | Mnemonic = "pvfmk.s.up.lt"; // "vfmk.s.lt" |
2432 | 0 | return; |
2433 | 0 | } |
2434 | 0 | break; |
2435 | 0 | case 'n': // 1 string to match. |
2436 | 0 | if (Mnemonic[8] != 'e') |
2437 | 0 | break; |
2438 | 0 | Mnemonic = "pvfmk.s.up.ne"; // "vfmk.s.ne" |
2439 | 0 | return; |
2440 | 0 | } |
2441 | 0 | break; |
2442 | 0 | case 's': // 2 strings to match. |
2443 | 0 | switch (Mnemonic[2]) { |
2444 | 0 | default: break; |
2445 | 0 | case 'l': // 1 string to match. |
2446 | 0 | if (memcmp(Mnemonic.data()+3, "a.w.zx", 6) != 0) |
2447 | 0 | break; |
2448 | 0 | Mnemonic = "pvsla.lo"; // "vsla.w.zx" |
2449 | 0 | return; |
2450 | 0 | case 'r': // 1 string to match. |
2451 | 0 | if (memcmp(Mnemonic.data()+3, "a.w.zx", 6) != 0) |
2452 | 0 | break; |
2453 | 0 | Mnemonic = "pvsra.lo"; // "vsra.w.zx" |
2454 | 0 | return; |
2455 | 0 | } |
2456 | 0 | break; |
2457 | 0 | } |
2458 | 0 | break; |
2459 | 0 | case 10: // 11 strings to match. |
2460 | 0 | switch (Mnemonic[0]) { |
2461 | 0 | default: break; |
2462 | 0 | case 'p': // 4 strings to match. |
2463 | 0 | if (memcmp(Mnemonic.data()+1, "vfmk.", 5) != 0) |
2464 | 0 | break; |
2465 | 0 | switch (Mnemonic[6]) { |
2466 | 0 | default: break; |
2467 | 0 | case 's': // 2 strings to match. |
2468 | 0 | if (Mnemonic[7] != '.') |
2469 | 0 | break; |
2470 | 0 | switch (Mnemonic[8]) { |
2471 | 0 | default: break; |
2472 | 0 | case 'l': // 1 string to match. |
2473 | 0 | if (Mnemonic[9] != 'o') |
2474 | 0 | break; |
2475 | 0 | Mnemonic = "pvfmk.s.lo.at"; // "pvfmk.s.lo" |
2476 | 0 | return; |
2477 | 0 | case 'u': // 1 string to match. |
2478 | 0 | if (Mnemonic[9] != 'p') |
2479 | 0 | break; |
2480 | 0 | Mnemonic = "pvfmk.s.up.at"; // "pvfmk.s.up" |
2481 | 0 | return; |
2482 | 0 | } |
2483 | 0 | break; |
2484 | 0 | case 'w': // 2 strings to match. |
2485 | 0 | if (Mnemonic[7] != '.') |
2486 | 0 | break; |
2487 | 0 | switch (Mnemonic[8]) { |
2488 | 0 | default: break; |
2489 | 0 | case 'l': // 1 string to match. |
2490 | 0 | if (Mnemonic[9] != 'o') |
2491 | 0 | break; |
2492 | 0 | Mnemonic = "vfmk.w.at"; // "pvfmk.w.lo" |
2493 | 0 | return; |
2494 | 0 | case 'u': // 1 string to match. |
2495 | 0 | if (Mnemonic[9] != 'p') |
2496 | 0 | break; |
2497 | 0 | Mnemonic = "pvfmk.w.up.at"; // "pvfmk.w.up" |
2498 | 0 | return; |
2499 | 0 | } |
2500 | 0 | break; |
2501 | 0 | } |
2502 | 0 | break; |
2503 | 0 | case 'v': // 7 strings to match. |
2504 | 0 | switch (Mnemonic[1]) { |
2505 | 0 | default: break; |
2506 | 0 | case 'a': // 1 string to match. |
2507 | 0 | if (memcmp(Mnemonic.data()+2, "dds.w.zx", 8) != 0) |
2508 | 0 | break; |
2509 | 0 | Mnemonic = "pvadds.lo"; // "vadds.w.zx" |
2510 | 0 | return; |
2511 | 0 | case 'c': // 1 string to match. |
2512 | 0 | if (memcmp(Mnemonic.data()+2, "mps.w.zx", 8) != 0) |
2513 | 0 | break; |
2514 | 0 | Mnemonic = "pvcmps.lo"; // "vcmps.w.zx" |
2515 | 0 | return; |
2516 | 0 | case 'f': // 2 strings to match. |
2517 | 0 | if (memcmp(Mnemonic.data()+2, "mk.s.n", 6) != 0) |
2518 | 0 | break; |
2519 | 0 | switch (Mnemonic[8]) { |
2520 | 0 | default: break; |
2521 | 0 | case 'a': // 1 string to match. |
2522 | 0 | if (Mnemonic[9] != 'n') |
2523 | 0 | break; |
2524 | 0 | Mnemonic = "pvfmk.s.up.nan"; // "vfmk.s.nan" |
2525 | 0 | return; |
2526 | 0 | case 'u': // 1 string to match. |
2527 | 0 | if (Mnemonic[9] != 'm') |
2528 | 0 | break; |
2529 | 0 | Mnemonic = "pvfmk.s.up.num"; // "vfmk.s.num" |
2530 | 0 | return; |
2531 | 0 | } |
2532 | 0 | break; |
2533 | 0 | case 'm': // 2 strings to match. |
2534 | 0 | switch (Mnemonic[2]) { |
2535 | 0 | default: break; |
2536 | 0 | case 'a': // 1 string to match. |
2537 | 0 | if (memcmp(Mnemonic.data()+3, "xs.w.zx", 7) != 0) |
2538 | 0 | break; |
2539 | 0 | Mnemonic = "pvmaxs.lo"; // "vmaxs.w.zx" |
2540 | 0 | return; |
2541 | 0 | case 'i': // 1 string to match. |
2542 | 0 | if (memcmp(Mnemonic.data()+3, "ns.w.zx", 7) != 0) |
2543 | 0 | break; |
2544 | 0 | Mnemonic = "pvmins.lo"; // "vmins.w.zx" |
2545 | 0 | return; |
2546 | 0 | } |
2547 | 0 | break; |
2548 | 0 | case 's': // 1 string to match. |
2549 | 0 | if (memcmp(Mnemonic.data()+2, "ubs.w.zx", 8) != 0) |
2550 | 0 | break; |
2551 | 0 | Mnemonic = "pvsubs.lo"; // "vsubs.w.zx" |
2552 | 0 | return; |
2553 | 0 | } |
2554 | 0 | break; |
2555 | 0 | } |
2556 | 0 | break; |
2557 | 0 | case 11: // 4 strings to match. |
2558 | 0 | if (memcmp(Mnemonic.data()+0, "pvs", 3) != 0) |
2559 | 0 | break; |
2560 | 0 | switch (Mnemonic[3]) { |
2561 | 0 | default: break; |
2562 | 0 | case 'l': // 2 strings to match. |
2563 | 0 | if (memcmp(Mnemonic.data()+4, "a.lo.", 5) != 0) |
2564 | 0 | break; |
2565 | 0 | switch (Mnemonic[9]) { |
2566 | 0 | default: break; |
2567 | 0 | case 's': // 1 string to match. |
2568 | 0 | if (Mnemonic[10] != 'x') |
2569 | 0 | break; |
2570 | 0 | Mnemonic = "vsla.w.sx"; // "pvsla.lo.sx" |
2571 | 0 | return; |
2572 | 0 | case 'z': // 1 string to match. |
2573 | 0 | if (Mnemonic[10] != 'x') |
2574 | 0 | break; |
2575 | 0 | Mnemonic = "pvsla.lo"; // "pvsla.lo.zx" |
2576 | 0 | return; |
2577 | 0 | } |
2578 | 0 | break; |
2579 | 0 | case 'r': // 2 strings to match. |
2580 | 0 | if (memcmp(Mnemonic.data()+4, "a.lo.", 5) != 0) |
2581 | 0 | break; |
2582 | 0 | switch (Mnemonic[9]) { |
2583 | 0 | default: break; |
2584 | 0 | case 's': // 1 string to match. |
2585 | 0 | if (Mnemonic[10] != 'x') |
2586 | 0 | break; |
2587 | 0 | Mnemonic = "vsra.w.sx"; // "pvsra.lo.sx" |
2588 | 0 | return; |
2589 | 0 | case 'z': // 1 string to match. |
2590 | 0 | if (Mnemonic[10] != 'x') |
2591 | 0 | break; |
2592 | 0 | Mnemonic = "pvsra.lo"; // "pvsra.lo.zx" |
2593 | 0 | return; |
2594 | 0 | } |
2595 | 0 | break; |
2596 | 0 | } |
2597 | 0 | break; |
2598 | 0 | case 12: // 17 strings to match. |
2599 | 0 | switch (Mnemonic[0]) { |
2600 | 0 | default: break; |
2601 | 0 | case 'p': // 10 strings to match. |
2602 | 0 | if (Mnemonic[1] != 'v') |
2603 | 0 | break; |
2604 | 0 | switch (Mnemonic[2]) { |
2605 | 0 | default: break; |
2606 | 0 | case 'a': // 2 strings to match. |
2607 | 0 | if (memcmp(Mnemonic.data()+3, "dds.lo.", 7) != 0) |
2608 | 0 | break; |
2609 | 0 | switch (Mnemonic[10]) { |
2610 | 0 | default: break; |
2611 | 0 | case 's': // 1 string to match. |
2612 | 0 | if (Mnemonic[11] != 'x') |
2613 | 0 | break; |
2614 | 0 | Mnemonic = "vadds.w.sx"; // "pvadds.lo.sx" |
2615 | 0 | return; |
2616 | 0 | case 'z': // 1 string to match. |
2617 | 0 | if (Mnemonic[11] != 'x') |
2618 | 0 | break; |
2619 | 0 | Mnemonic = "pvadds.lo"; // "pvadds.lo.zx" |
2620 | 0 | return; |
2621 | 0 | } |
2622 | 0 | break; |
2623 | 0 | case 'c': // 2 strings to match. |
2624 | 0 | if (memcmp(Mnemonic.data()+3, "mps.lo.", 7) != 0) |
2625 | 0 | break; |
2626 | 0 | switch (Mnemonic[10]) { |
2627 | 0 | default: break; |
2628 | 0 | case 's': // 1 string to match. |
2629 | 0 | if (Mnemonic[11] != 'x') |
2630 | 0 | break; |
2631 | 0 | Mnemonic = "vcmps.w.sx"; // "pvcmps.lo.sx" |
2632 | 0 | return; |
2633 | 0 | case 'z': // 1 string to match. |
2634 | 0 | if (Mnemonic[11] != 'x') |
2635 | 0 | break; |
2636 | 0 | Mnemonic = "pvcmps.lo"; // "pvcmps.lo.zx" |
2637 | 0 | return; |
2638 | 0 | } |
2639 | 0 | break; |
2640 | 0 | case 'm': // 4 strings to match. |
2641 | 0 | switch (Mnemonic[3]) { |
2642 | 0 | default: break; |
2643 | 0 | case 'a': // 2 strings to match. |
2644 | 0 | if (memcmp(Mnemonic.data()+4, "xs.lo.", 6) != 0) |
2645 | 0 | break; |
2646 | 0 | switch (Mnemonic[10]) { |
2647 | 0 | default: break; |
2648 | 0 | case 's': // 1 string to match. |
2649 | 0 | if (Mnemonic[11] != 'x') |
2650 | 0 | break; |
2651 | 0 | Mnemonic = "vmaxs.w.sx"; // "pvmaxs.lo.sx" |
2652 | 0 | return; |
2653 | 0 | case 'z': // 1 string to match. |
2654 | 0 | if (Mnemonic[11] != 'x') |
2655 | 0 | break; |
2656 | 0 | Mnemonic = "pvmaxs.lo"; // "pvmaxs.lo.zx" |
2657 | 0 | return; |
2658 | 0 | } |
2659 | 0 | break; |
2660 | 0 | case 'i': // 2 strings to match. |
2661 | 0 | if (memcmp(Mnemonic.data()+4, "ns.lo.", 6) != 0) |
2662 | 0 | break; |
2663 | 0 | switch (Mnemonic[10]) { |
2664 | 0 | default: break; |
2665 | 0 | case 's': // 1 string to match. |
2666 | 0 | if (Mnemonic[11] != 'x') |
2667 | 0 | break; |
2668 | 0 | Mnemonic = "vmins.w.sx"; // "pvmins.lo.sx" |
2669 | 0 | return; |
2670 | 0 | case 'z': // 1 string to match. |
2671 | 0 | if (Mnemonic[11] != 'x') |
2672 | 0 | break; |
2673 | 0 | Mnemonic = "pvmins.lo"; // "pvmins.lo.zx" |
2674 | 0 | return; |
2675 | 0 | } |
2676 | 0 | break; |
2677 | 0 | } |
2678 | 0 | break; |
2679 | 0 | case 's': // 2 strings to match. |
2680 | 0 | if (memcmp(Mnemonic.data()+3, "ubs.lo.", 7) != 0) |
2681 | 0 | break; |
2682 | 0 | switch (Mnemonic[10]) { |
2683 | 0 | default: break; |
2684 | 0 | case 's': // 1 string to match. |
2685 | 0 | if (Mnemonic[11] != 'x') |
2686 | 0 | break; |
2687 | 0 | Mnemonic = "vsubs.w.sx"; // "pvsubs.lo.sx" |
2688 | 0 | return; |
2689 | 0 | case 'z': // 1 string to match. |
2690 | 0 | if (Mnemonic[11] != 'x') |
2691 | 0 | break; |
2692 | 0 | Mnemonic = "pvsubs.lo"; // "pvsubs.lo.zx" |
2693 | 0 | return; |
2694 | 0 | } |
2695 | 0 | break; |
2696 | 0 | } |
2697 | 0 | break; |
2698 | 0 | case 'v': // 7 strings to match. |
2699 | 0 | switch (Mnemonic[1]) { |
2700 | 0 | default: break; |
2701 | 0 | case 'f': // 6 strings to match. |
2702 | 0 | if (memcmp(Mnemonic.data()+2, "mk.s.", 5) != 0) |
2703 | 0 | break; |
2704 | 0 | switch (Mnemonic[7]) { |
2705 | 0 | default: break; |
2706 | 0 | case 'e': // 1 string to match. |
2707 | 0 | if (memcmp(Mnemonic.data()+8, "qnan", 4) != 0) |
2708 | 0 | break; |
2709 | 0 | Mnemonic = "pvfmk.s.up.eqnan"; // "vfmk.s.eqnan" |
2710 | 0 | return; |
2711 | 0 | case 'g': // 2 strings to match. |
2712 | 0 | switch (Mnemonic[8]) { |
2713 | 0 | default: break; |
2714 | 0 | case 'e': // 1 string to match. |
2715 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2716 | 0 | break; |
2717 | 0 | Mnemonic = "pvfmk.s.up.genan"; // "vfmk.s.genan" |
2718 | 0 | return; |
2719 | 0 | case 't': // 1 string to match. |
2720 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2721 | 0 | break; |
2722 | 0 | Mnemonic = "pvfmk.s.up.gtnan"; // "vfmk.s.gtnan" |
2723 | 0 | return; |
2724 | 0 | } |
2725 | 0 | break; |
2726 | 0 | case 'l': // 2 strings to match. |
2727 | 0 | switch (Mnemonic[8]) { |
2728 | 0 | default: break; |
2729 | 0 | case 'e': // 1 string to match. |
2730 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2731 | 0 | break; |
2732 | 0 | Mnemonic = "pvfmk.s.up.lenan"; // "vfmk.s.lenan" |
2733 | 0 | return; |
2734 | 0 | case 't': // 1 string to match. |
2735 | 0 | if (memcmp(Mnemonic.data()+9, "nan", 3) != 0) |
2736 | 0 | break; |
2737 | 0 | Mnemonic = "pvfmk.s.up.ltnan"; // "vfmk.s.ltnan" |
2738 | 0 | return; |
2739 | 0 | } |
2740 | 0 | break; |
2741 | 0 | case 'n': // 1 string to match. |
2742 | 0 | if (memcmp(Mnemonic.data()+8, "enan", 4) != 0) |
2743 | 0 | break; |
2744 | 0 | Mnemonic = "pvfmk.s.up.nenan"; // "vfmk.s.nenan" |
2745 | 0 | return; |
2746 | 0 | } |
2747 | 0 | break; |
2748 | 0 | case 'r': // 1 string to match. |
2749 | 0 | if (memcmp(Mnemonic.data()+2, "sqrt.s.nex", 10) != 0) |
2750 | 0 | break; |
2751 | 0 | Mnemonic = "pvrsqrt.up.nex"; // "vrsqrt.s.nex" |
2752 | 0 | return; |
2753 | 0 | } |
2754 | 0 | break; |
2755 | 0 | } |
2756 | 0 | break; |
2757 | 0 | case 13: // 8 strings to match. |
2758 | 0 | if (memcmp(Mnemonic.data()+0, "pvfmk.w.lo.", 11) != 0) |
2759 | 0 | break; |
2760 | 0 | switch (Mnemonic[11]) { |
2761 | 0 | default: break; |
2762 | 0 | case 'a': // 2 strings to match. |
2763 | 0 | switch (Mnemonic[12]) { |
2764 | 0 | default: break; |
2765 | 0 | case 'f': // 1 string to match. |
2766 | 0 | Mnemonic = "vfmk.w.af"; // "pvfmk.w.lo.af" |
2767 | 0 | return; |
2768 | 0 | case 't': // 1 string to match. |
2769 | 0 | Mnemonic = "vfmk.w.at"; // "pvfmk.w.lo.at" |
2770 | 0 | return; |
2771 | 0 | } |
2772 | 0 | break; |
2773 | 0 | case 'e': // 1 string to match. |
2774 | 0 | if (Mnemonic[12] != 'q') |
2775 | 0 | break; |
2776 | 0 | Mnemonic = "vfmk.w.eq"; // "pvfmk.w.lo.eq" |
2777 | 0 | return; |
2778 | 0 | case 'g': // 2 strings to match. |
2779 | 0 | switch (Mnemonic[12]) { |
2780 | 0 | default: break; |
2781 | 0 | case 'e': // 1 string to match. |
2782 | 0 | Mnemonic = "vfmk.w.ge"; // "pvfmk.w.lo.ge" |
2783 | 0 | return; |
2784 | 0 | case 't': // 1 string to match. |
2785 | 0 | Mnemonic = "vfmk.w.gt"; // "pvfmk.w.lo.gt" |
2786 | 0 | return; |
2787 | 0 | } |
2788 | 0 | break; |
2789 | 0 | case 'l': // 2 strings to match. |
2790 | 0 | switch (Mnemonic[12]) { |
2791 | 0 | default: break; |
2792 | 0 | case 'e': // 1 string to match. |
2793 | 0 | Mnemonic = "vfmk.w.le"; // "pvfmk.w.lo.le" |
2794 | 0 | return; |
2795 | 0 | case 't': // 1 string to match. |
2796 | 0 | Mnemonic = "vfmk.w.lt"; // "pvfmk.w.lo.lt" |
2797 | 0 | return; |
2798 | 0 | } |
2799 | 0 | break; |
2800 | 0 | case 'n': // 1 string to match. |
2801 | 0 | if (Mnemonic[12] != 'e') |
2802 | 0 | break; |
2803 | 0 | Mnemonic = "vfmk.w.ne"; // "pvfmk.w.lo.ne" |
2804 | 0 | return; |
2805 | 0 | } |
2806 | 0 | break; |
2807 | 0 | } |
2808 | 0 | } |
2809 | | |
2810 | | enum { |
2811 | | Tie0_1_1, |
2812 | | }; |
2813 | | |
2814 | | static const uint8_t TiedAsmOperandTable[][3] = { |
2815 | | /* Tie0_1_1 */ { 0, 1, 1 }, |
2816 | | }; |
2817 | | |
2818 | | namespace { |
2819 | | enum OperatorConversionKind { |
2820 | | CVT_Done, |
2821 | | CVT_Reg, |
2822 | | CVT_Tied, |
2823 | | CVT_95_Reg, |
2824 | | CVT_95_addMImmOperands, |
2825 | | CVT_95_addSImm7Operands, |
2826 | | CVT_95_addMEMriOperands, |
2827 | | CVT_95_addUImm0to2Operands, |
2828 | | CVT_95_addMEMziOperands, |
2829 | | CVT_95_addCCOpOperands, |
2830 | | CVT_95_addImmOperands, |
2831 | | CVT_95_addZeroOperands, |
2832 | | CVT_95_addMEMriiOperands, |
2833 | | CVT_95_addMEMrriOperands, |
2834 | | CVT_95_addMEMziiOperands, |
2835 | | CVT_95_addMEMzriOperands, |
2836 | | CVT_95_addUImm1Operands, |
2837 | | CVT_95_addRDOpOperands, |
2838 | | CVT_95_addUImm3Operands, |
2839 | | CVT_95_addUImm2Operands, |
2840 | | CVT_95_addUImm6Operands, |
2841 | | CVT_95_addUImm7Operands, |
2842 | | CVT_95_addUImm4Operands, |
2843 | | CVT_NUM_CONVERTERS |
2844 | | }; |
2845 | | |
2846 | | enum InstructionConversionKind { |
2847 | | Convert__Reg1_0__Reg1_1__Reg1_2, |
2848 | | Convert__Reg1_0__Reg1_1__MImm1_2, |
2849 | | Convert__Reg1_0__Reg1_2__SImm71_1, |
2850 | | Convert__Reg1_0__SImm71_1__MImm1_2, |
2851 | | Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, |
2852 | | Convert__Reg1_0__MEMri2_1__UImm0to21_2__Tie0_1_1, |
2853 | | Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, |
2854 | | Convert__Reg1_0__MEMzi2_1__UImm0to21_2__Tie0_1_1, |
2855 | | Convert__CCOp1_0__Reg1_2__MEMri2_3, |
2856 | | Convert__CCOp1_0__Reg1_2__MEMzi2_3, |
2857 | | Convert__CCOp1_0__SImm71_2__MEMri2_3, |
2858 | | Convert__CCOp1_0__SImm71_2__MEMzi2_3, |
2859 | | Convert__MEMri2_0, |
2860 | | Convert__MEMzi2_0, |
2861 | | Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, |
2862 | | Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, |
2863 | | Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, |
2864 | | Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, |
2865 | | Convert__Imm1_0, |
2866 | | Convert__Reg1_0__Reg1_1, |
2867 | | Convert__Reg1_0__MImm1_1, |
2868 | | Convert__Reg1_0__MEMrii3_1, |
2869 | | Convert__Reg1_0__MEMrri3_1, |
2870 | | Convert__Reg1_0__MEMzii3_1, |
2871 | | Convert__Reg1_0__MEMzri3_1, |
2872 | | Convert__Reg1_0__Reg1_1__UImm11_2, |
2873 | | Convert__Reg1_0__MImm1_1__UImm11_2, |
2874 | | Convert__Reg1_0__MEMri2_1__SImm71_2__Tie0_1_1, |
2875 | | Convert__Reg1_0__MEMzi2_1__SImm71_2__Tie0_1_1, |
2876 | | Convert__Reg1_1__CCOp1_0__Reg1_3__Reg1_2__Tie0_1_1, |
2877 | | Convert__Reg1_1__CCOp1_0__SImm71_3__Reg1_2__Tie0_1_1, |
2878 | | Convert__Reg1_1__CCOp1_0__Reg1_3__MImm1_2__Tie0_1_1, |
2879 | | Convert__Reg1_1__CCOp1_0__SImm71_3__MImm1_2__Tie0_1_1, |
2880 | | Convert__Reg1_0__SImm71_1__Reg1_2, |
2881 | | Convert__Reg1_0__SImm71_1, |
2882 | | Convert__Reg1_1__RDOp1_0__Reg1_2, |
2883 | | Convert__Reg1_1__RDOp1_0__SImm71_2, |
2884 | | Convert__UImm31_0, |
2885 | | Convert_NoOperands, |
2886 | | Convert__UImm21_0, |
2887 | | Convert__Reg1_0__Reg1_1__UImm31_2, |
2888 | | Convert__Reg1_0__SImm71_1__UImm31_2, |
2889 | | Convert__Reg1_0__Reg1_1__Zero1_2, |
2890 | | Convert__Reg1_0__SImm71_1__Zero1_2, |
2891 | | Convert__Reg1_0, |
2892 | | Convert__UImm61_0, |
2893 | | Convert__Reg1_0__MEMri2_1, |
2894 | | Convert__Reg1_0__MEMzi2_1, |
2895 | | Convert__Reg1_0__Reg1_2__Reg1_4, |
2896 | | Convert__Reg1_0__Reg1_2__MImm1_4, |
2897 | | Convert__Reg1_0__UImm71_2__Reg1_4, |
2898 | | Convert__Reg1_0__UImm71_2__MImm1_4, |
2899 | | Convert__SImm71_0, |
2900 | | Convert__Reg1_0__UImm21_1__Reg1_2, |
2901 | | Convert__Reg1_0__UImm21_1__MImm1_2, |
2902 | | Convert__Reg1_0__Reg1_1__Reg1_3, |
2903 | | Convert__Reg1_0__Reg1_1__UImm71_3, |
2904 | | Convert__Reg1_0__Reg1_1__Reg1_2__Tie0_1_1, |
2905 | | Convert__Reg1_0__Reg1_1__MImm1_2__Tie0_1_1, |
2906 | | Convert__Reg1_0__SImm71_1__Reg1_2__Tie0_1_1, |
2907 | | Convert__Reg1_0__SImm71_1__MImm1_2__Tie0_1_1, |
2908 | | Convert__MEMrii3_0, |
2909 | | Convert__MEMrri3_0, |
2910 | | Convert__MEMzii3_0, |
2911 | | Convert__MEMzri3_0, |
2912 | | Convert__Reg1_0__Zero1_1, |
2913 | | Convert__SImm71_0__Reg1_1, |
2914 | | Convert__SImm71_0__Zero1_1, |
2915 | | Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, |
2916 | | Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, |
2917 | | Convert__Reg1_0__MImm1_1__Reg1_2, |
2918 | | Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, |
2919 | | Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, |
2920 | | Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, |
2921 | | Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, |
2922 | | Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, |
2923 | | Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, |
2924 | | Convert__Reg1_1__CCOp1_0__Reg1_2, |
2925 | | Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, |
2926 | | Convert__Reg1_0__Reg1_1__UImm71_2, |
2927 | | Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, |
2928 | | Convert__Reg1_1__Reg1_2__Reg1_0, |
2929 | | Convert__Reg1_1__Zero1_2__Reg1_0, |
2930 | | Convert__SImm71_1__Reg1_2__Reg1_0, |
2931 | | Convert__SImm71_1__Zero1_2__Reg1_0, |
2932 | | Convert__MEMri2_1__Reg1_0, |
2933 | | Convert__MEMzi2_1__Reg1_0, |
2934 | | Convert__Reg1_0__MImm1_1__UImm71_2, |
2935 | | Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, |
2936 | | Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm71_2, |
2937 | | Convert__Reg1_0__Tie0_1_1__MImm1_1__Reg1_2, |
2938 | | Convert__Reg1_0__Tie0_1_1__MImm1_1__UImm71_2, |
2939 | | Convert__Reg1_0__Reg1_1__Tie0_1_1__Reg1_2, |
2940 | | Convert__Reg1_0__Reg1_1__Tie0_1_1__UImm71_2, |
2941 | | Convert__Reg1_0__MImm1_1__Tie0_1_1__Reg1_2, |
2942 | | Convert__Reg1_0__MImm1_1__Tie0_1_1__UImm71_2, |
2943 | | Convert__MEMrii3_1__Reg1_0, |
2944 | | Convert__MEMrri3_1__Reg1_0, |
2945 | | Convert__MEMzii3_1__Reg1_0, |
2946 | | Convert__MEMzri3_1__Reg1_0, |
2947 | | Convert__Reg1_0__Reg1_1__UImm21_2, |
2948 | | Convert__Reg1_0__MEMri2_1__UImm71_2__Tie0_1_1, |
2949 | | Convert__Reg1_0__MEMzi2_1__UImm71_2__Tie0_1_1, |
2950 | | Convert__Reg1_0__MEMri2_1__UImm11_2__Tie0_1_1, |
2951 | | Convert__Reg1_0__MEMzi2_1__UImm11_2__Tie0_1_1, |
2952 | | Convert__Reg1_0__Reg1_1__Zero1_2__Tie0_1_1, |
2953 | | Convert__Reg1_0__SImm71_1__Zero1_2__Tie0_1_1, |
2954 | | Convert__Reg1_0__Reg1_1__SImm71_2, |
2955 | | Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, |
2956 | | Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, |
2957 | | Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, |
2958 | | Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, |
2959 | | Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, |
2960 | | Convert__Reg1_0__UImm71_1__Reg1_2, |
2961 | | Convert__Reg1_0__UImm71_1__Reg1_2__Reg1_3, |
2962 | | Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, |
2963 | | Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, |
2964 | | Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, |
2965 | | Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, |
2966 | | Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, |
2967 | | Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, |
2968 | | Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, |
2969 | | Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, |
2970 | | Convert__Reg1_0__Reg1_1__Reg1_2__MImm1_3, |
2971 | | Convert__Reg1_0__Reg1_1__UImm31_2__Reg1_3, |
2972 | | Convert__Reg1_0__Reg1_1__UImm31_2__MImm1_3, |
2973 | | Convert__Reg1_0__Reg1_1__Reg1_2__MImm1_3__Reg1_4, |
2974 | | Convert__Reg1_0__Reg1_1__UImm31_2__Reg1_3__Reg1_4, |
2975 | | Convert__Reg1_0__Reg1_1__UImm31_2__MImm1_3__Reg1_4, |
2976 | | Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3, |
2977 | | Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5, |
2978 | | Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5, |
2979 | | Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5__Reg1_6, |
2980 | | Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5__Reg1_6, |
2981 | | Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, |
2982 | | Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, |
2983 | | Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, |
2984 | | Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, |
2985 | | CVT_NUM_SIGNATURES |
2986 | | }; |
2987 | | |
2988 | | } // end anonymous namespace |
2989 | | |
2990 | | static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { |
2991 | | // Convert__Reg1_0__Reg1_1__Reg1_2 |
2992 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
2993 | | // Convert__Reg1_0__Reg1_1__MImm1_2 |
2994 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMImmOperands, 3, CVT_Done }, |
2995 | | // Convert__Reg1_0__Reg1_2__SImm71_1 |
2996 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addSImm7Operands, 2, CVT_Done }, |
2997 | | // Convert__Reg1_0__SImm71_1__MImm1_2 |
2998 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_addMImmOperands, 3, CVT_Done }, |
2999 | | // Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1 |
3000 | | { CVT_95_Reg, 1, CVT_95_addMEMriOperands, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3001 | | // Convert__Reg1_0__MEMri2_1__UImm0to21_2__Tie0_1_1 |
3002 | | { CVT_95_Reg, 1, CVT_95_addMEMriOperands, 2, CVT_95_addUImm0to2Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3003 | | // Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1 |
3004 | | { CVT_95_Reg, 1, CVT_95_addMEMziOperands, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3005 | | // Convert__Reg1_0__MEMzi2_1__UImm0to21_2__Tie0_1_1 |
3006 | | { CVT_95_Reg, 1, CVT_95_addMEMziOperands, 2, CVT_95_addUImm0to2Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3007 | | // Convert__CCOp1_0__Reg1_2__MEMri2_3 |
3008 | | { CVT_95_addCCOpOperands, 1, CVT_95_Reg, 3, CVT_95_addMEMriOperands, 4, CVT_Done }, |
3009 | | // Convert__CCOp1_0__Reg1_2__MEMzi2_3 |
3010 | | { CVT_95_addCCOpOperands, 1, CVT_95_Reg, 3, CVT_95_addMEMziOperands, 4, CVT_Done }, |
3011 | | // Convert__CCOp1_0__SImm71_2__MEMri2_3 |
3012 | | { CVT_95_addCCOpOperands, 1, CVT_95_addSImm7Operands, 3, CVT_95_addMEMriOperands, 4, CVT_Done }, |
3013 | | // Convert__CCOp1_0__SImm71_2__MEMzi2_3 |
3014 | | { CVT_95_addCCOpOperands, 1, CVT_95_addSImm7Operands, 3, CVT_95_addMEMziOperands, 4, CVT_Done }, |
3015 | | // Convert__MEMri2_0 |
3016 | | { CVT_95_addMEMriOperands, 1, CVT_Done }, |
3017 | | // Convert__MEMzi2_0 |
3018 | | { CVT_95_addMEMziOperands, 1, CVT_Done }, |
3019 | | // Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4 |
3020 | | { CVT_95_addCCOpOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
3021 | | // Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4 |
3022 | | { CVT_95_addCCOpOperands, 1, CVT_95_Reg, 3, CVT_95_addZeroOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
3023 | | // Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4 |
3024 | | { CVT_95_addCCOpOperands, 1, CVT_95_addSImm7Operands, 3, CVT_95_Reg, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
3025 | | // Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4 |
3026 | | { CVT_95_addCCOpOperands, 1, CVT_95_addSImm7Operands, 3, CVT_95_addZeroOperands, 4, CVT_95_addImmOperands, 5, CVT_Done }, |
3027 | | // Convert__Imm1_0 |
3028 | | { CVT_95_addImmOperands, 1, CVT_Done }, |
3029 | | // Convert__Reg1_0__Reg1_1 |
3030 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, |
3031 | | // Convert__Reg1_0__MImm1_1 |
3032 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_Done }, |
3033 | | // Convert__Reg1_0__MEMrii3_1 |
3034 | | { CVT_95_Reg, 1, CVT_95_addMEMriiOperands, 2, CVT_Done }, |
3035 | | // Convert__Reg1_0__MEMrri3_1 |
3036 | | { CVT_95_Reg, 1, CVT_95_addMEMrriOperands, 2, CVT_Done }, |
3037 | | // Convert__Reg1_0__MEMzii3_1 |
3038 | | { CVT_95_Reg, 1, CVT_95_addMEMziiOperands, 2, CVT_Done }, |
3039 | | // Convert__Reg1_0__MEMzri3_1 |
3040 | | { CVT_95_Reg, 1, CVT_95_addMEMzriOperands, 2, CVT_Done }, |
3041 | | // Convert__Reg1_0__Reg1_1__UImm11_2 |
3042 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm1Operands, 3, CVT_Done }, |
3043 | | // Convert__Reg1_0__MImm1_1__UImm11_2 |
3044 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_95_addUImm1Operands, 3, CVT_Done }, |
3045 | | // Convert__Reg1_0__MEMri2_1__SImm71_2__Tie0_1_1 |
3046 | | { CVT_95_Reg, 1, CVT_95_addMEMriOperands, 2, CVT_95_addSImm7Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3047 | | // Convert__Reg1_0__MEMzi2_1__SImm71_2__Tie0_1_1 |
3048 | | { CVT_95_Reg, 1, CVT_95_addMEMziOperands, 2, CVT_95_addSImm7Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3049 | | // Convert__Reg1_1__CCOp1_0__Reg1_3__Reg1_2__Tie0_1_1 |
3050 | | { CVT_95_Reg, 2, CVT_95_addCCOpOperands, 1, CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3051 | | // Convert__Reg1_1__CCOp1_0__SImm71_3__Reg1_2__Tie0_1_1 |
3052 | | { CVT_95_Reg, 2, CVT_95_addCCOpOperands, 1, CVT_95_addSImm7Operands, 4, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3053 | | // Convert__Reg1_1__CCOp1_0__Reg1_3__MImm1_2__Tie0_1_1 |
3054 | | { CVT_95_Reg, 2, CVT_95_addCCOpOperands, 1, CVT_95_Reg, 4, CVT_95_addMImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3055 | | // Convert__Reg1_1__CCOp1_0__SImm71_3__MImm1_2__Tie0_1_1 |
3056 | | { CVT_95_Reg, 2, CVT_95_addCCOpOperands, 1, CVT_95_addSImm7Operands, 4, CVT_95_addMImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3057 | | // Convert__Reg1_0__SImm71_1__Reg1_2 |
3058 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_Reg, 3, CVT_Done }, |
3059 | | // Convert__Reg1_0__SImm71_1 |
3060 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_Done }, |
3061 | | // Convert__Reg1_1__RDOp1_0__Reg1_2 |
3062 | | { CVT_95_Reg, 2, CVT_95_addRDOpOperands, 1, CVT_95_Reg, 3, CVT_Done }, |
3063 | | // Convert__Reg1_1__RDOp1_0__SImm71_2 |
3064 | | { CVT_95_Reg, 2, CVT_95_addRDOpOperands, 1, CVT_95_addSImm7Operands, 3, CVT_Done }, |
3065 | | // Convert__UImm31_0 |
3066 | | { CVT_95_addUImm3Operands, 1, CVT_Done }, |
3067 | | // Convert_NoOperands |
3068 | | { CVT_Done }, |
3069 | | // Convert__UImm21_0 |
3070 | | { CVT_95_addUImm2Operands, 1, CVT_Done }, |
3071 | | // Convert__Reg1_0__Reg1_1__UImm31_2 |
3072 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm3Operands, 3, CVT_Done }, |
3073 | | // Convert__Reg1_0__SImm71_1__UImm31_2 |
3074 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_addUImm3Operands, 3, CVT_Done }, |
3075 | | // Convert__Reg1_0__Reg1_1__Zero1_2 |
3076 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addZeroOperands, 3, CVT_Done }, |
3077 | | // Convert__Reg1_0__SImm71_1__Zero1_2 |
3078 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_addZeroOperands, 3, CVT_Done }, |
3079 | | // Convert__Reg1_0 |
3080 | | { CVT_95_Reg, 1, CVT_Done }, |
3081 | | // Convert__UImm61_0 |
3082 | | { CVT_95_addUImm6Operands, 1, CVT_Done }, |
3083 | | // Convert__Reg1_0__MEMri2_1 |
3084 | | { CVT_95_Reg, 1, CVT_95_addMEMriOperands, 2, CVT_Done }, |
3085 | | // Convert__Reg1_0__MEMzi2_1 |
3086 | | { CVT_95_Reg, 1, CVT_95_addMEMziOperands, 2, CVT_Done }, |
3087 | | // Convert__Reg1_0__Reg1_2__Reg1_4 |
3088 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_Done }, |
3089 | | // Convert__Reg1_0__Reg1_2__MImm1_4 |
3090 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_addMImmOperands, 5, CVT_Done }, |
3091 | | // Convert__Reg1_0__UImm71_2__Reg1_4 |
3092 | | { CVT_95_Reg, 1, CVT_95_addUImm7Operands, 3, CVT_95_Reg, 5, CVT_Done }, |
3093 | | // Convert__Reg1_0__UImm71_2__MImm1_4 |
3094 | | { CVT_95_Reg, 1, CVT_95_addUImm7Operands, 3, CVT_95_addMImmOperands, 5, CVT_Done }, |
3095 | | // Convert__SImm71_0 |
3096 | | { CVT_95_addSImm7Operands, 1, CVT_Done }, |
3097 | | // Convert__Reg1_0__UImm21_1__Reg1_2 |
3098 | | { CVT_95_Reg, 1, CVT_95_addUImm2Operands, 2, CVT_95_Reg, 3, CVT_Done }, |
3099 | | // Convert__Reg1_0__UImm21_1__MImm1_2 |
3100 | | { CVT_95_Reg, 1, CVT_95_addUImm2Operands, 2, CVT_95_addMImmOperands, 3, CVT_Done }, |
3101 | | // Convert__Reg1_0__Reg1_1__Reg1_3 |
3102 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Done }, |
3103 | | // Convert__Reg1_0__Reg1_1__UImm71_3 |
3104 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm7Operands, 4, CVT_Done }, |
3105 | | // Convert__Reg1_0__Reg1_1__Reg1_2__Tie0_1_1 |
3106 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3107 | | // Convert__Reg1_0__Reg1_1__MImm1_2__Tie0_1_1 |
3108 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addMImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3109 | | // Convert__Reg1_0__SImm71_1__Reg1_2__Tie0_1_1 |
3110 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_Reg, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3111 | | // Convert__Reg1_0__SImm71_1__MImm1_2__Tie0_1_1 |
3112 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_addMImmOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3113 | | // Convert__MEMrii3_0 |
3114 | | { CVT_95_addMEMriiOperands, 1, CVT_Done }, |
3115 | | // Convert__MEMrri3_0 |
3116 | | { CVT_95_addMEMrriOperands, 1, CVT_Done }, |
3117 | | // Convert__MEMzii3_0 |
3118 | | { CVT_95_addMEMziiOperands, 1, CVT_Done }, |
3119 | | // Convert__MEMzri3_0 |
3120 | | { CVT_95_addMEMzriOperands, 1, CVT_Done }, |
3121 | | // Convert__Reg1_0__Zero1_1 |
3122 | | { CVT_95_Reg, 1, CVT_95_addZeroOperands, 2, CVT_Done }, |
3123 | | // Convert__SImm71_0__Reg1_1 |
3124 | | { CVT_95_addSImm7Operands, 1, CVT_95_Reg, 2, CVT_Done }, |
3125 | | // Convert__SImm71_0__Zero1_1 |
3126 | | { CVT_95_addSImm7Operands, 1, CVT_95_addZeroOperands, 2, CVT_Done }, |
3127 | | // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3 |
3128 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, |
3129 | | // Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3 |
3130 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, |
3131 | | // Convert__Reg1_0__MImm1_1__Reg1_2 |
3132 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_95_Reg, 3, CVT_Done }, |
3133 | | // Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3 |
3134 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, |
3135 | | // Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3 |
3136 | | { CVT_95_Reg, 2, CVT_95_addRDOpOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, |
3137 | | // Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3 |
3138 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_Reg, 4, CVT_Done }, |
3139 | | // Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4 |
3140 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Done }, |
3141 | | // Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4 |
3142 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Done }, |
3143 | | // Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4 |
3144 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Done }, |
3145 | | // Convert__Reg1_1__CCOp1_0__Reg1_2 |
3146 | | { CVT_95_Reg, 2, CVT_95_addCCOpOperands, 1, CVT_95_Reg, 3, CVT_Done }, |
3147 | | // Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3 |
3148 | | { CVT_95_Reg, 2, CVT_95_addCCOpOperands, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, |
3149 | | // Convert__Reg1_0__Reg1_1__UImm71_2 |
3150 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm7Operands, 3, CVT_Done }, |
3151 | | // Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3 |
3152 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm7Operands, 3, CVT_95_Reg, 4, CVT_Done }, |
3153 | | // Convert__Reg1_1__Reg1_2__Reg1_0 |
3154 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Done }, |
3155 | | // Convert__Reg1_1__Zero1_2__Reg1_0 |
3156 | | { CVT_95_Reg, 2, CVT_95_addZeroOperands, 3, CVT_95_Reg, 1, CVT_Done }, |
3157 | | // Convert__SImm71_1__Reg1_2__Reg1_0 |
3158 | | { CVT_95_addSImm7Operands, 2, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_Done }, |
3159 | | // Convert__SImm71_1__Zero1_2__Reg1_0 |
3160 | | { CVT_95_addSImm7Operands, 2, CVT_95_addZeroOperands, 3, CVT_95_Reg, 1, CVT_Done }, |
3161 | | // Convert__MEMri2_1__Reg1_0 |
3162 | | { CVT_95_addMEMriOperands, 2, CVT_95_Reg, 1, CVT_Done }, |
3163 | | // Convert__MEMzi2_1__Reg1_0 |
3164 | | { CVT_95_addMEMziOperands, 2, CVT_95_Reg, 1, CVT_Done }, |
3165 | | // Convert__Reg1_0__MImm1_1__UImm71_2 |
3166 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_95_addUImm7Operands, 3, CVT_Done }, |
3167 | | // Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2 |
3168 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, |
3169 | | // Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm71_2 |
3170 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_95_addUImm7Operands, 3, CVT_Done }, |
3171 | | // Convert__Reg1_0__Tie0_1_1__MImm1_1__Reg1_2 |
3172 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMImmOperands, 2, CVT_95_Reg, 3, CVT_Done }, |
3173 | | // Convert__Reg1_0__Tie0_1_1__MImm1_1__UImm71_2 |
3174 | | { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addMImmOperands, 2, CVT_95_addUImm7Operands, 3, CVT_Done }, |
3175 | | // Convert__Reg1_0__Reg1_1__Tie0_1_1__Reg1_2 |
3176 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done }, |
3177 | | // Convert__Reg1_0__Reg1_1__Tie0_1_1__UImm71_2 |
3178 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, Tie0_1_1, CVT_95_addUImm7Operands, 3, CVT_Done }, |
3179 | | // Convert__Reg1_0__MImm1_1__Tie0_1_1__Reg1_2 |
3180 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_Reg, 3, CVT_Done }, |
3181 | | // Convert__Reg1_0__MImm1_1__Tie0_1_1__UImm71_2 |
3182 | | { CVT_95_Reg, 1, CVT_95_addMImmOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addUImm7Operands, 3, CVT_Done }, |
3183 | | // Convert__MEMrii3_1__Reg1_0 |
3184 | | { CVT_95_addMEMriiOperands, 2, CVT_95_Reg, 1, CVT_Done }, |
3185 | | // Convert__MEMrri3_1__Reg1_0 |
3186 | | { CVT_95_addMEMrriOperands, 2, CVT_95_Reg, 1, CVT_Done }, |
3187 | | // Convert__MEMzii3_1__Reg1_0 |
3188 | | { CVT_95_addMEMziiOperands, 2, CVT_95_Reg, 1, CVT_Done }, |
3189 | | // Convert__MEMzri3_1__Reg1_0 |
3190 | | { CVT_95_addMEMzriOperands, 2, CVT_95_Reg, 1, CVT_Done }, |
3191 | | // Convert__Reg1_0__Reg1_1__UImm21_2 |
3192 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm2Operands, 3, CVT_Done }, |
3193 | | // Convert__Reg1_0__MEMri2_1__UImm71_2__Tie0_1_1 |
3194 | | { CVT_95_Reg, 1, CVT_95_addMEMriOperands, 2, CVT_95_addUImm7Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3195 | | // Convert__Reg1_0__MEMzi2_1__UImm71_2__Tie0_1_1 |
3196 | | { CVT_95_Reg, 1, CVT_95_addMEMziOperands, 2, CVT_95_addUImm7Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3197 | | // Convert__Reg1_0__MEMri2_1__UImm11_2__Tie0_1_1 |
3198 | | { CVT_95_Reg, 1, CVT_95_addMEMriOperands, 2, CVT_95_addUImm1Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3199 | | // Convert__Reg1_0__MEMzi2_1__UImm11_2__Tie0_1_1 |
3200 | | { CVT_95_Reg, 1, CVT_95_addMEMziOperands, 2, CVT_95_addUImm1Operands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3201 | | // Convert__Reg1_0__Reg1_1__Zero1_2__Tie0_1_1 |
3202 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addZeroOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3203 | | // Convert__Reg1_0__SImm71_1__Zero1_2__Tie0_1_1 |
3204 | | { CVT_95_Reg, 1, CVT_95_addSImm7Operands, 2, CVT_95_addZeroOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, |
3205 | | // Convert__Reg1_0__Reg1_1__SImm71_2 |
3206 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_Done }, |
3207 | | // Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3 |
3208 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addSImm7Operands, 4, CVT_Done }, |
3209 | | // Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3 |
3210 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addZeroOperands, 4, CVT_Done }, |
3211 | | // Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3 |
3212 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_addZeroOperands, 4, CVT_Done }, |
3213 | | // Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4 |
3214 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addZeroOperands, 4, CVT_95_Reg, 5, CVT_Done }, |
3215 | | // Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4 |
3216 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_addZeroOperands, 4, CVT_95_Reg, 5, CVT_Done }, |
3217 | | // Convert__Reg1_0__UImm71_1__Reg1_2 |
3218 | | { CVT_95_Reg, 1, CVT_95_addUImm7Operands, 2, CVT_95_Reg, 3, CVT_Done }, |
3219 | | // Convert__Reg1_0__UImm71_1__Reg1_2__Reg1_3 |
3220 | | { CVT_95_Reg, 1, CVT_95_addUImm7Operands, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_Done }, |
3221 | | // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0 |
3222 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done }, |
3223 | | // Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0 |
3224 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addZeroOperands, 4, CVT_95_Reg, 1, CVT_Done }, |
3225 | | // Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0 |
3226 | | { CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_Done }, |
3227 | | // Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0 |
3228 | | { CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_addZeroOperands, 4, CVT_95_Reg, 1, CVT_Done }, |
3229 | | // Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4 |
3230 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_Done }, |
3231 | | // Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4 |
3232 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addZeroOperands, 4, CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_Done }, |
3233 | | // Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4 |
3234 | | { CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_Reg, 4, CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_Done }, |
3235 | | // Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4 |
3236 | | { CVT_95_Reg, 2, CVT_95_addSImm7Operands, 3, CVT_95_addZeroOperands, 4, CVT_95_Reg, 1, CVT_95_Reg, 5, CVT_Done }, |
3237 | | // Convert__Reg1_0__Reg1_1__Reg1_2__MImm1_3 |
3238 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMImmOperands, 4, CVT_Done }, |
3239 | | // Convert__Reg1_0__Reg1_1__UImm31_2__Reg1_3 |
3240 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm3Operands, 3, CVT_95_Reg, 4, CVT_Done }, |
3241 | | // Convert__Reg1_0__Reg1_1__UImm31_2__MImm1_3 |
3242 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm3Operands, 3, CVT_95_addMImmOperands, 4, CVT_Done }, |
3243 | | // Convert__Reg1_0__Reg1_1__Reg1_2__MImm1_3__Reg1_4 |
3244 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addMImmOperands, 4, CVT_95_Reg, 5, CVT_Done }, |
3245 | | // Convert__Reg1_0__Reg1_1__UImm31_2__Reg1_3__Reg1_4 |
3246 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm3Operands, 3, CVT_95_Reg, 4, CVT_95_Reg, 5, CVT_Done }, |
3247 | | // Convert__Reg1_0__Reg1_1__UImm31_2__MImm1_3__Reg1_4 |
3248 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addUImm3Operands, 3, CVT_95_addMImmOperands, 4, CVT_95_Reg, 5, CVT_Done }, |
3249 | | // Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3 |
3250 | | { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_addUImm4Operands, 4, CVT_Done }, |
3251 | | // Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5 |
3252 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_Done }, |
3253 | | // Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5 |
3254 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addUImm7Operands, 6, CVT_Done }, |
3255 | | // Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5__Reg1_6 |
3256 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_Reg, 6, CVT_95_Reg, 7, CVT_Done }, |
3257 | | // Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5__Reg1_6 |
3258 | | { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_95_Reg, 4, CVT_95_addUImm7Operands, 6, CVT_95_Reg, 7, CVT_Done }, |
3259 | | // Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3 |
3260 | | { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done }, |
3261 | | // Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3 |
3262 | | { CVT_95_Reg, 2, CVT_95_addZeroOperands, 3, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done }, |
3263 | | // Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3 |
3264 | | { CVT_95_addSImm7Operands, 2, CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done }, |
3265 | | // Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3 |
3266 | | { CVT_95_addSImm7Operands, 2, CVT_95_addZeroOperands, 3, CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_Done }, |
3267 | | }; |
3268 | | |
3269 | | void VEAsmParser:: |
3270 | | convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, |
3271 | 0 | const OperandVector &Operands) { |
3272 | 0 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
3273 | 0 | const uint8_t *Converter = ConversionTable[Kind]; |
3274 | 0 | unsigned OpIdx; |
3275 | 0 | Inst.setOpcode(Opcode); |
3276 | 0 | for (const uint8_t *p = Converter; *p; p += 2) { |
3277 | 0 | OpIdx = *(p + 1); |
3278 | 0 | switch (*p) { |
3279 | 0 | default: llvm_unreachable("invalid conversion entry!"); |
3280 | 0 | case CVT_Reg: |
3281 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
3282 | 0 | break; |
3283 | 0 | case CVT_Tied: { |
3284 | 0 | assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - |
3285 | 0 | std::begin(TiedAsmOperandTable)) && |
3286 | 0 | "Tied operand not found"); |
3287 | 0 | unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; |
3288 | 0 | if (TiedResOpnd != (uint8_t)-1) |
3289 | 0 | Inst.addOperand(Inst.getOperand(TiedResOpnd)); |
3290 | 0 | break; |
3291 | 0 | } |
3292 | 0 | case CVT_95_Reg: |
3293 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addRegOperands(Inst, 1); |
3294 | 0 | break; |
3295 | 0 | case CVT_95_addMImmOperands: |
3296 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMImmOperands(Inst, 1); |
3297 | 0 | break; |
3298 | 0 | case CVT_95_addSImm7Operands: |
3299 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addSImm7Operands(Inst, 1); |
3300 | 0 | break; |
3301 | 0 | case CVT_95_addMEMriOperands: |
3302 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMEMriOperands(Inst, 2); |
3303 | 0 | break; |
3304 | 0 | case CVT_95_addUImm0to2Operands: |
3305 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm0to2Operands(Inst, 1); |
3306 | 0 | break; |
3307 | 0 | case CVT_95_addMEMziOperands: |
3308 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMEMziOperands(Inst, 2); |
3309 | 0 | break; |
3310 | 0 | case CVT_95_addCCOpOperands: |
3311 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addCCOpOperands(Inst, 1); |
3312 | 0 | break; |
3313 | 0 | case CVT_95_addImmOperands: |
3314 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addImmOperands(Inst, 1); |
3315 | 0 | break; |
3316 | 0 | case CVT_95_addZeroOperands: |
3317 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addZeroOperands(Inst, 1); |
3318 | 0 | break; |
3319 | 0 | case CVT_95_addMEMriiOperands: |
3320 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMEMriiOperands(Inst, 3); |
3321 | 0 | break; |
3322 | 0 | case CVT_95_addMEMrriOperands: |
3323 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMEMrriOperands(Inst, 3); |
3324 | 0 | break; |
3325 | 0 | case CVT_95_addMEMziiOperands: |
3326 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMEMziiOperands(Inst, 3); |
3327 | 0 | break; |
3328 | 0 | case CVT_95_addMEMzriOperands: |
3329 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addMEMzriOperands(Inst, 3); |
3330 | 0 | break; |
3331 | 0 | case CVT_95_addUImm1Operands: |
3332 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm1Operands(Inst, 1); |
3333 | 0 | break; |
3334 | 0 | case CVT_95_addRDOpOperands: |
3335 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addRDOpOperands(Inst, 1); |
3336 | 0 | break; |
3337 | 0 | case CVT_95_addUImm3Operands: |
3338 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm3Operands(Inst, 1); |
3339 | 0 | break; |
3340 | 0 | case CVT_95_addUImm2Operands: |
3341 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm2Operands(Inst, 1); |
3342 | 0 | break; |
3343 | 0 | case CVT_95_addUImm6Operands: |
3344 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm6Operands(Inst, 1); |
3345 | 0 | break; |
3346 | 0 | case CVT_95_addUImm7Operands: |
3347 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm7Operands(Inst, 1); |
3348 | 0 | break; |
3349 | 0 | case CVT_95_addUImm4Operands: |
3350 | 0 | static_cast<VEOperand &>(*Operands[OpIdx]).addUImm4Operands(Inst, 1); |
3351 | 0 | break; |
3352 | 0 | } |
3353 | 0 | } |
3354 | 0 | } |
3355 | | |
3356 | | void VEAsmParser:: |
3357 | | convertToMapAndConstraints(unsigned Kind, |
3358 | 0 | const OperandVector &Operands) { |
3359 | 0 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
3360 | 0 | unsigned NumMCOperands = 0; |
3361 | 0 | const uint8_t *Converter = ConversionTable[Kind]; |
3362 | 0 | for (const uint8_t *p = Converter; *p; p += 2) { |
3363 | 0 | switch (*p) { |
3364 | 0 | default: llvm_unreachable("invalid conversion entry!"); |
3365 | 0 | case CVT_Reg: |
3366 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3367 | 0 | Operands[*(p + 1)]->setConstraint("r"); |
3368 | 0 | ++NumMCOperands; |
3369 | 0 | break; |
3370 | 0 | case CVT_Tied: |
3371 | 0 | ++NumMCOperands; |
3372 | 0 | break; |
3373 | 0 | case CVT_95_Reg: |
3374 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3375 | 0 | Operands[*(p + 1)]->setConstraint("r"); |
3376 | 0 | NumMCOperands += 1; |
3377 | 0 | break; |
3378 | 0 | case CVT_95_addMImmOperands: |
3379 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3380 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3381 | 0 | NumMCOperands += 1; |
3382 | 0 | break; |
3383 | 0 | case CVT_95_addSImm7Operands: |
3384 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3385 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3386 | 0 | NumMCOperands += 1; |
3387 | 0 | break; |
3388 | 0 | case CVT_95_addMEMriOperands: |
3389 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3390 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3391 | 0 | NumMCOperands += 2; |
3392 | 0 | break; |
3393 | 0 | case CVT_95_addUImm0to2Operands: |
3394 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3395 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3396 | 0 | NumMCOperands += 1; |
3397 | 0 | break; |
3398 | 0 | case CVT_95_addMEMziOperands: |
3399 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3400 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3401 | 0 | NumMCOperands += 2; |
3402 | 0 | break; |
3403 | 0 | case CVT_95_addCCOpOperands: |
3404 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3405 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3406 | 0 | NumMCOperands += 1; |
3407 | 0 | break; |
3408 | 0 | case CVT_95_addImmOperands: |
3409 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3410 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3411 | 0 | NumMCOperands += 1; |
3412 | 0 | break; |
3413 | 0 | case CVT_95_addZeroOperands: |
3414 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3415 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3416 | 0 | NumMCOperands += 1; |
3417 | 0 | break; |
3418 | 0 | case CVT_95_addMEMriiOperands: |
3419 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3420 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3421 | 0 | NumMCOperands += 3; |
3422 | 0 | break; |
3423 | 0 | case CVT_95_addMEMrriOperands: |
3424 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3425 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3426 | 0 | NumMCOperands += 3; |
3427 | 0 | break; |
3428 | 0 | case CVT_95_addMEMziiOperands: |
3429 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3430 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3431 | 0 | NumMCOperands += 3; |
3432 | 0 | break; |
3433 | 0 | case CVT_95_addMEMzriOperands: |
3434 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3435 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3436 | 0 | NumMCOperands += 3; |
3437 | 0 | break; |
3438 | 0 | case CVT_95_addUImm1Operands: |
3439 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3440 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3441 | 0 | NumMCOperands += 1; |
3442 | 0 | break; |
3443 | 0 | case CVT_95_addRDOpOperands: |
3444 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3445 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3446 | 0 | NumMCOperands += 1; |
3447 | 0 | break; |
3448 | 0 | case CVT_95_addUImm3Operands: |
3449 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3450 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3451 | 0 | NumMCOperands += 1; |
3452 | 0 | break; |
3453 | 0 | case CVT_95_addUImm2Operands: |
3454 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3455 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3456 | 0 | NumMCOperands += 1; |
3457 | 0 | break; |
3458 | 0 | case CVT_95_addUImm6Operands: |
3459 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3460 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3461 | 0 | NumMCOperands += 1; |
3462 | 0 | break; |
3463 | 0 | case CVT_95_addUImm7Operands: |
3464 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3465 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3466 | 0 | NumMCOperands += 1; |
3467 | 0 | break; |
3468 | 0 | case CVT_95_addUImm4Operands: |
3469 | 0 | Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); |
3470 | 0 | Operands[*(p + 1)]->setConstraint("m"); |
3471 | 0 | NumMCOperands += 1; |
3472 | 0 | break; |
3473 | 0 | } |
3474 | 0 | } |
3475 | 0 | } |
3476 | | |
3477 | | namespace { |
3478 | | |
3479 | | /// MatchClassKind - The kinds of classes which participate in |
3480 | | /// instruction matching. |
3481 | | enum MatchClassKind { |
3482 | | InvalidMatchClass = 0, |
3483 | | OptionalMatchClass = 1, |
3484 | | MCK__40_, // '(' |
3485 | | MCK__41_, // ')' |
3486 | | MCK__DOT_d, // '.d' |
3487 | | MCK__DOT_d_DOT_nt, // '.d.nt' |
3488 | | MCK__DOT_d_DOT_t, // '.d.t' |
3489 | | MCK__DOT_l, // '.l' |
3490 | | MCK__DOT_l_DOT_nt, // '.l.nt' |
3491 | | MCK__DOT_l_DOT_t, // '.l.t' |
3492 | | MCK__DOT_s, // '.s' |
3493 | | MCK__DOT_s_DOT_nt, // '.s.nt' |
3494 | | MCK__DOT_s_DOT_t, // '.s.t' |
3495 | | MCK__DOT_w, // '.w' |
3496 | | MCK__DOT_w_DOT_nt, // '.w.nt' |
3497 | | MCK__DOT_w_DOT_t, // '.w.t' |
3498 | | MCK_LAST_TOKEN = MCK__DOT_w_DOT_t, |
3499 | | MCK_VLS, // register class 'VLS' |
3500 | | MCK_Reg9, // derived register class |
3501 | | MCK_VM512, // register class 'VM512' |
3502 | | MCK_VM, // register class 'VM' |
3503 | | MCK_MISC, // register class 'MISC' |
3504 | | MCK_F128, // register class 'F128' |
3505 | | MCK_F32, // register class 'F32' |
3506 | | MCK_I32, // register class 'I32' |
3507 | | MCK_I64, // register class 'I64' |
3508 | | MCK_V64, // register class 'V64' |
3509 | | MCK_LAST_REGISTER = MCK_V64, |
3510 | | MCK_CCOp, // user defined class 'CCOpAsmOperand' |
3511 | | MCK_Imm, // user defined class 'ImmAsmOperand' |
3512 | | MCK_MImm, // user defined class 'MImmAsmOperand' |
3513 | | MCK_RDOp, // user defined class 'RDOpAsmOperand' |
3514 | | MCK_SImm7, // user defined class 'SImm7AsmOperand' |
3515 | | MCK_UImm0to2, // user defined class 'UImm0to2AsmOperand' |
3516 | | MCK_UImm1, // user defined class 'UImm1AsmOperand' |
3517 | | MCK_UImm2, // user defined class 'UImm2AsmOperand' |
3518 | | MCK_UImm3, // user defined class 'UImm3AsmOperand' |
3519 | | MCK_UImm4, // user defined class 'UImm4AsmOperand' |
3520 | | MCK_UImm6, // user defined class 'UImm6AsmOperand' |
3521 | | MCK_UImm7, // user defined class 'UImm7AsmOperand' |
3522 | | MCK_MEMri, // user defined class 'VEMEMriAsmOperand' |
3523 | | MCK_MEMrii, // user defined class 'VEMEMriiAsmOperand' |
3524 | | MCK_MEMrri, // user defined class 'VEMEMrriAsmOperand' |
3525 | | MCK_MEMzi, // user defined class 'VEMEMziAsmOperand' |
3526 | | MCK_MEMzii, // user defined class 'VEMEMziiAsmOperand' |
3527 | | MCK_MEMzri, // user defined class 'VEMEMzriAsmOperand' |
3528 | | MCK_Zero, // user defined class 'ZeroAsmOperand' |
3529 | | NumMatchClassKinds |
3530 | | }; |
3531 | | |
3532 | | } // end anonymous namespace |
3533 | | |
3534 | 0 | static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { |
3535 | 0 | return MCTargetAsmParser::Match_InvalidOperand; |
3536 | 0 | } |
3537 | | |
3538 | 0 | static MatchClassKind matchTokenString(StringRef Name) { |
3539 | 0 | switch (Name.size()) { |
3540 | 0 | default: break; |
3541 | 0 | case 1: // 2 strings to match. |
3542 | 0 | switch (Name[0]) { |
3543 | 0 | default: break; |
3544 | 0 | case '(': // 1 string to match. |
3545 | 0 | return MCK__40_; // "(" |
3546 | 0 | case ')': // 1 string to match. |
3547 | 0 | return MCK__41_; // ")" |
3548 | 0 | } |
3549 | 0 | break; |
3550 | 0 | case 2: // 4 strings to match. |
3551 | 0 | if (Name[0] != '.') |
3552 | 0 | break; |
3553 | 0 | switch (Name[1]) { |
3554 | 0 | default: break; |
3555 | 0 | case 'd': // 1 string to match. |
3556 | 0 | return MCK__DOT_d; // ".d" |
3557 | 0 | case 'l': // 1 string to match. |
3558 | 0 | return MCK__DOT_l; // ".l" |
3559 | 0 | case 's': // 1 string to match. |
3560 | 0 | return MCK__DOT_s; // ".s" |
3561 | 0 | case 'w': // 1 string to match. |
3562 | 0 | return MCK__DOT_w; // ".w" |
3563 | 0 | } |
3564 | 0 | break; |
3565 | 0 | case 4: // 4 strings to match. |
3566 | 0 | if (Name[0] != '.') |
3567 | 0 | break; |
3568 | 0 | switch (Name[1]) { |
3569 | 0 | default: break; |
3570 | 0 | case 'd': // 1 string to match. |
3571 | 0 | if (memcmp(Name.data()+2, ".t", 2) != 0) |
3572 | 0 | break; |
3573 | 0 | return MCK__DOT_d_DOT_t; // ".d.t" |
3574 | 0 | case 'l': // 1 string to match. |
3575 | 0 | if (memcmp(Name.data()+2, ".t", 2) != 0) |
3576 | 0 | break; |
3577 | 0 | return MCK__DOT_l_DOT_t; // ".l.t" |
3578 | 0 | case 's': // 1 string to match. |
3579 | 0 | if (memcmp(Name.data()+2, ".t", 2) != 0) |
3580 | 0 | break; |
3581 | 0 | return MCK__DOT_s_DOT_t; // ".s.t" |
3582 | 0 | case 'w': // 1 string to match. |
3583 | 0 | if (memcmp(Name.data()+2, ".t", 2) != 0) |
3584 | 0 | break; |
3585 | 0 | return MCK__DOT_w_DOT_t; // ".w.t" |
3586 | 0 | } |
3587 | 0 | break; |
3588 | 0 | case 5: // 4 strings to match. |
3589 | 0 | if (Name[0] != '.') |
3590 | 0 | break; |
3591 | 0 | switch (Name[1]) { |
3592 | 0 | default: break; |
3593 | 0 | case 'd': // 1 string to match. |
3594 | 0 | if (memcmp(Name.data()+2, ".nt", 3) != 0) |
3595 | 0 | break; |
3596 | 0 | return MCK__DOT_d_DOT_nt; // ".d.nt" |
3597 | 0 | case 'l': // 1 string to match. |
3598 | 0 | if (memcmp(Name.data()+2, ".nt", 3) != 0) |
3599 | 0 | break; |
3600 | 0 | return MCK__DOT_l_DOT_nt; // ".l.nt" |
3601 | 0 | case 's': // 1 string to match. |
3602 | 0 | if (memcmp(Name.data()+2, ".nt", 3) != 0) |
3603 | 0 | break; |
3604 | 0 | return MCK__DOT_s_DOT_nt; // ".s.nt" |
3605 | 0 | case 'w': // 1 string to match. |
3606 | 0 | if (memcmp(Name.data()+2, ".nt", 3) != 0) |
3607 | 0 | break; |
3608 | 0 | return MCK__DOT_w_DOT_nt; // ".w.nt" |
3609 | 0 | } |
3610 | 0 | break; |
3611 | 0 | } |
3612 | 0 | return InvalidMatchClass; |
3613 | 0 | } |
3614 | | |
3615 | | /// isSubclass - Compute whether \p A is a subclass of \p B. |
3616 | 0 | static bool isSubclass(MatchClassKind A, MatchClassKind B) { |
3617 | 0 | if (A == B) |
3618 | 0 | return true; |
3619 | | |
3620 | 0 | switch (A) { |
3621 | 0 | default: |
3622 | 0 | return false; |
3623 | | |
3624 | 0 | case MCK_Reg9: |
3625 | 0 | return B == MCK_VM512; |
3626 | 0 | } |
3627 | 0 | } |
3628 | | |
3629 | 0 | static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { |
3630 | 0 | VEOperand &Operand = (VEOperand &)GOp; |
3631 | 0 | if (Kind == InvalidMatchClass) |
3632 | 0 | return MCTargetAsmParser::Match_InvalidOperand; |
3633 | | |
3634 | 0 | if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) |
3635 | 0 | return isSubclass(matchTokenString(Operand.getToken()), Kind) ? |
3636 | 0 | MCTargetAsmParser::Match_Success : |
3637 | 0 | MCTargetAsmParser::Match_InvalidOperand; |
3638 | | |
3639 | 0 | switch (Kind) { |
3640 | 0 | default: break; |
3641 | | // 'CCOp' class |
3642 | 0 | case MCK_CCOp: { |
3643 | 0 | DiagnosticPredicate DP(Operand.isCCOp()); |
3644 | 0 | if (DP.isMatch()) |
3645 | 0 | return MCTargetAsmParser::Match_Success; |
3646 | 0 | break; |
3647 | 0 | } |
3648 | | // 'Imm' class |
3649 | 0 | case MCK_Imm: { |
3650 | 0 | DiagnosticPredicate DP(Operand.isImm()); |
3651 | 0 | if (DP.isMatch()) |
3652 | 0 | return MCTargetAsmParser::Match_Success; |
3653 | 0 | break; |
3654 | 0 | } |
3655 | | // 'MImm' class |
3656 | 0 | case MCK_MImm: { |
3657 | 0 | DiagnosticPredicate DP(Operand.isMImm()); |
3658 | 0 | if (DP.isMatch()) |
3659 | 0 | return MCTargetAsmParser::Match_Success; |
3660 | 0 | break; |
3661 | 0 | } |
3662 | | // 'RDOp' class |
3663 | 0 | case MCK_RDOp: { |
3664 | 0 | DiagnosticPredicate DP(Operand.isRDOp()); |
3665 | 0 | if (DP.isMatch()) |
3666 | 0 | return MCTargetAsmParser::Match_Success; |
3667 | 0 | break; |
3668 | 0 | } |
3669 | | // 'SImm7' class |
3670 | 0 | case MCK_SImm7: { |
3671 | 0 | DiagnosticPredicate DP(Operand.isSImm7()); |
3672 | 0 | if (DP.isMatch()) |
3673 | 0 | return MCTargetAsmParser::Match_Success; |
3674 | 0 | break; |
3675 | 0 | } |
3676 | | // 'UImm0to2' class |
3677 | 0 | case MCK_UImm0to2: { |
3678 | 0 | DiagnosticPredicate DP(Operand.isUImm0to2()); |
3679 | 0 | if (DP.isMatch()) |
3680 | 0 | return MCTargetAsmParser::Match_Success; |
3681 | 0 | break; |
3682 | 0 | } |
3683 | | // 'UImm1' class |
3684 | 0 | case MCK_UImm1: { |
3685 | 0 | DiagnosticPredicate DP(Operand.isUImm1()); |
3686 | 0 | if (DP.isMatch()) |
3687 | 0 | return MCTargetAsmParser::Match_Success; |
3688 | 0 | break; |
3689 | 0 | } |
3690 | | // 'UImm2' class |
3691 | 0 | case MCK_UImm2: { |
3692 | 0 | DiagnosticPredicate DP(Operand.isUImm2()); |
3693 | 0 | if (DP.isMatch()) |
3694 | 0 | return MCTargetAsmParser::Match_Success; |
3695 | 0 | break; |
3696 | 0 | } |
3697 | | // 'UImm3' class |
3698 | 0 | case MCK_UImm3: { |
3699 | 0 | DiagnosticPredicate DP(Operand.isUImm3()); |
3700 | 0 | if (DP.isMatch()) |
3701 | 0 | return MCTargetAsmParser::Match_Success; |
3702 | 0 | break; |
3703 | 0 | } |
3704 | | // 'UImm4' class |
3705 | 0 | case MCK_UImm4: { |
3706 | 0 | DiagnosticPredicate DP(Operand.isUImm4()); |
3707 | 0 | if (DP.isMatch()) |
3708 | 0 | return MCTargetAsmParser::Match_Success; |
3709 | 0 | break; |
3710 | 0 | } |
3711 | | // 'UImm6' class |
3712 | 0 | case MCK_UImm6: { |
3713 | 0 | DiagnosticPredicate DP(Operand.isUImm6()); |
3714 | 0 | if (DP.isMatch()) |
3715 | 0 | return MCTargetAsmParser::Match_Success; |
3716 | 0 | break; |
3717 | 0 | } |
3718 | | // 'UImm7' class |
3719 | 0 | case MCK_UImm7: { |
3720 | 0 | DiagnosticPredicate DP(Operand.isUImm7()); |
3721 | 0 | if (DP.isMatch()) |
3722 | 0 | return MCTargetAsmParser::Match_Success; |
3723 | 0 | break; |
3724 | 0 | } |
3725 | | // 'MEMri' class |
3726 | 0 | case MCK_MEMri: { |
3727 | 0 | DiagnosticPredicate DP(Operand.isMEMri()); |
3728 | 0 | if (DP.isMatch()) |
3729 | 0 | return MCTargetAsmParser::Match_Success; |
3730 | 0 | break; |
3731 | 0 | } |
3732 | | // 'MEMrii' class |
3733 | 0 | case MCK_MEMrii: { |
3734 | 0 | DiagnosticPredicate DP(Operand.isMEMrii()); |
3735 | 0 | if (DP.isMatch()) |
3736 | 0 | return MCTargetAsmParser::Match_Success; |
3737 | 0 | break; |
3738 | 0 | } |
3739 | | // 'MEMrri' class |
3740 | 0 | case MCK_MEMrri: { |
3741 | 0 | DiagnosticPredicate DP(Operand.isMEMrri()); |
3742 | 0 | if (DP.isMatch()) |
3743 | 0 | return MCTargetAsmParser::Match_Success; |
3744 | 0 | break; |
3745 | 0 | } |
3746 | | // 'MEMzi' class |
3747 | 0 | case MCK_MEMzi: { |
3748 | 0 | DiagnosticPredicate DP(Operand.isMEMzi()); |
3749 | 0 | if (DP.isMatch()) |
3750 | 0 | return MCTargetAsmParser::Match_Success; |
3751 | 0 | break; |
3752 | 0 | } |
3753 | | // 'MEMzii' class |
3754 | 0 | case MCK_MEMzii: { |
3755 | 0 | DiagnosticPredicate DP(Operand.isMEMzii()); |
3756 | 0 | if (DP.isMatch()) |
3757 | 0 | return MCTargetAsmParser::Match_Success; |
3758 | 0 | break; |
3759 | 0 | } |
3760 | | // 'MEMzri' class |
3761 | 0 | case MCK_MEMzri: { |
3762 | 0 | DiagnosticPredicate DP(Operand.isMEMzri()); |
3763 | 0 | if (DP.isMatch()) |
3764 | 0 | return MCTargetAsmParser::Match_Success; |
3765 | 0 | break; |
3766 | 0 | } |
3767 | | // 'Zero' class |
3768 | 0 | case MCK_Zero: { |
3769 | 0 | DiagnosticPredicate DP(Operand.isZero()); |
3770 | 0 | if (DP.isMatch()) |
3771 | 0 | return MCTargetAsmParser::Match_Success; |
3772 | 0 | break; |
3773 | 0 | } |
3774 | 0 | } // end switch (Kind) |
3775 | | |
3776 | 0 | if (Operand.isReg()) { |
3777 | 0 | MatchClassKind OpKind; |
3778 | 0 | switch (Operand.getReg()) { |
3779 | 0 | default: OpKind = InvalidMatchClass; break; |
3780 | 0 | case VE::USRCC: OpKind = MCK_MISC; break; |
3781 | 0 | case VE::PSW: OpKind = MCK_MISC; break; |
3782 | 0 | case VE::SAR: OpKind = MCK_MISC; break; |
3783 | 0 | case VE::PMMR: OpKind = MCK_MISC; break; |
3784 | 0 | case VE::PMCR0: OpKind = MCK_MISC; break; |
3785 | 0 | case VE::PMCR1: OpKind = MCK_MISC; break; |
3786 | 0 | case VE::PMCR2: OpKind = MCK_MISC; break; |
3787 | 0 | case VE::PMCR3: OpKind = MCK_MISC; break; |
3788 | 0 | case VE::PMC0: OpKind = MCK_MISC; break; |
3789 | 0 | case VE::PMC1: OpKind = MCK_MISC; break; |
3790 | 0 | case VE::PMC2: OpKind = MCK_MISC; break; |
3791 | 0 | case VE::PMC3: OpKind = MCK_MISC; break; |
3792 | 0 | case VE::PMC4: OpKind = MCK_MISC; break; |
3793 | 0 | case VE::PMC5: OpKind = MCK_MISC; break; |
3794 | 0 | case VE::PMC6: OpKind = MCK_MISC; break; |
3795 | 0 | case VE::PMC7: OpKind = MCK_MISC; break; |
3796 | 0 | case VE::PMC8: OpKind = MCK_MISC; break; |
3797 | 0 | case VE::PMC9: OpKind = MCK_MISC; break; |
3798 | 0 | case VE::PMC10: OpKind = MCK_MISC; break; |
3799 | 0 | case VE::PMC11: OpKind = MCK_MISC; break; |
3800 | 0 | case VE::PMC12: OpKind = MCK_MISC; break; |
3801 | 0 | case VE::PMC13: OpKind = MCK_MISC; break; |
3802 | 0 | case VE::PMC14: OpKind = MCK_MISC; break; |
3803 | 0 | case VE::VL: OpKind = MCK_VLS; break; |
3804 | 0 | case VE::SW0: OpKind = MCK_I32; break; |
3805 | 0 | case VE::SW1: OpKind = MCK_I32; break; |
3806 | 0 | case VE::SW2: OpKind = MCK_I32; break; |
3807 | 0 | case VE::SW3: OpKind = MCK_I32; break; |
3808 | 0 | case VE::SW4: OpKind = MCK_I32; break; |
3809 | 0 | case VE::SW5: OpKind = MCK_I32; break; |
3810 | 0 | case VE::SW6: OpKind = MCK_I32; break; |
3811 | 0 | case VE::SW7: OpKind = MCK_I32; break; |
3812 | 0 | case VE::SW8: OpKind = MCK_I32; break; |
3813 | 0 | case VE::SW9: OpKind = MCK_I32; break; |
3814 | 0 | case VE::SW10: OpKind = MCK_I32; break; |
3815 | 0 | case VE::SW11: OpKind = MCK_I32; break; |
3816 | 0 | case VE::SW12: OpKind = MCK_I32; break; |
3817 | 0 | case VE::SW13: OpKind = MCK_I32; break; |
3818 | 0 | case VE::SW14: OpKind = MCK_I32; break; |
3819 | 0 | case VE::SW15: OpKind = MCK_I32; break; |
3820 | 0 | case VE::SW16: OpKind = MCK_I32; break; |
3821 | 0 | case VE::SW17: OpKind = MCK_I32; break; |
3822 | 0 | case VE::SW18: OpKind = MCK_I32; break; |
3823 | 0 | case VE::SW19: OpKind = MCK_I32; break; |
3824 | 0 | case VE::SW20: OpKind = MCK_I32; break; |
3825 | 0 | case VE::SW21: OpKind = MCK_I32; break; |
3826 | 0 | case VE::SW22: OpKind = MCK_I32; break; |
3827 | 0 | case VE::SW23: OpKind = MCK_I32; break; |
3828 | 0 | case VE::SW24: OpKind = MCK_I32; break; |
3829 | 0 | case VE::SW25: OpKind = MCK_I32; break; |
3830 | 0 | case VE::SW26: OpKind = MCK_I32; break; |
3831 | 0 | case VE::SW27: OpKind = MCK_I32; break; |
3832 | 0 | case VE::SW28: OpKind = MCK_I32; break; |
3833 | 0 | case VE::SW29: OpKind = MCK_I32; break; |
3834 | 0 | case VE::SW30: OpKind = MCK_I32; break; |
3835 | 0 | case VE::SW31: OpKind = MCK_I32; break; |
3836 | 0 | case VE::SW32: OpKind = MCK_I32; break; |
3837 | 0 | case VE::SW33: OpKind = MCK_I32; break; |
3838 | 0 | case VE::SW34: OpKind = MCK_I32; break; |
3839 | 0 | case VE::SW35: OpKind = MCK_I32; break; |
3840 | 0 | case VE::SW36: OpKind = MCK_I32; break; |
3841 | 0 | case VE::SW37: OpKind = MCK_I32; break; |
3842 | 0 | case VE::SW38: OpKind = MCK_I32; break; |
3843 | 0 | case VE::SW39: OpKind = MCK_I32; break; |
3844 | 0 | case VE::SW40: OpKind = MCK_I32; break; |
3845 | 0 | case VE::SW41: OpKind = MCK_I32; break; |
3846 | 0 | case VE::SW42: OpKind = MCK_I32; break; |
3847 | 0 | case VE::SW43: OpKind = MCK_I32; break; |
3848 | 0 | case VE::SW44: OpKind = MCK_I32; break; |
3849 | 0 | case VE::SW45: OpKind = MCK_I32; break; |
3850 | 0 | case VE::SW46: OpKind = MCK_I32; break; |
3851 | 0 | case VE::SW47: OpKind = MCK_I32; break; |
3852 | 0 | case VE::SW48: OpKind = MCK_I32; break; |
3853 | 0 | case VE::SW49: OpKind = MCK_I32; break; |
3854 | 0 | case VE::SW50: OpKind = MCK_I32; break; |
3855 | 0 | case VE::SW51: OpKind = MCK_I32; break; |
3856 | 0 | case VE::SW52: OpKind = MCK_I32; break; |
3857 | 0 | case VE::SW53: OpKind = MCK_I32; break; |
3858 | 0 | case VE::SW54: OpKind = MCK_I32; break; |
3859 | 0 | case VE::SW55: OpKind = MCK_I32; break; |
3860 | 0 | case VE::SW56: OpKind = MCK_I32; break; |
3861 | 0 | case VE::SW57: OpKind = MCK_I32; break; |
3862 | 0 | case VE::SW58: OpKind = MCK_I32; break; |
3863 | 0 | case VE::SW59: OpKind = MCK_I32; break; |
3864 | 0 | case VE::SW60: OpKind = MCK_I32; break; |
3865 | 0 | case VE::SW61: OpKind = MCK_I32; break; |
3866 | 0 | case VE::SW62: OpKind = MCK_I32; break; |
3867 | 0 | case VE::SW63: OpKind = MCK_I32; break; |
3868 | 0 | case VE::SF0: OpKind = MCK_F32; break; |
3869 | 0 | case VE::SF1: OpKind = MCK_F32; break; |
3870 | 0 | case VE::SF2: OpKind = MCK_F32; break; |
3871 | 0 | case VE::SF3: OpKind = MCK_F32; break; |
3872 | 0 | case VE::SF4: OpKind = MCK_F32; break; |
3873 | 0 | case VE::SF5: OpKind = MCK_F32; break; |
3874 | 0 | case VE::SF6: OpKind = MCK_F32; break; |
3875 | 0 | case VE::SF7: OpKind = MCK_F32; break; |
3876 | 0 | case VE::SF8: OpKind = MCK_F32; break; |
3877 | 0 | case VE::SF9: OpKind = MCK_F32; break; |
3878 | 0 | case VE::SF10: OpKind = MCK_F32; break; |
3879 | 0 | case VE::SF11: OpKind = MCK_F32; break; |
3880 | 0 | case VE::SF12: OpKind = MCK_F32; break; |
3881 | 0 | case VE::SF13: OpKind = MCK_F32; break; |
3882 | 0 | case VE::SF14: OpKind = MCK_F32; break; |
3883 | 0 | case VE::SF15: OpKind = MCK_F32; break; |
3884 | 0 | case VE::SF16: OpKind = MCK_F32; break; |
3885 | 0 | case VE::SF17: OpKind = MCK_F32; break; |
3886 | 0 | case VE::SF18: OpKind = MCK_F32; break; |
3887 | 0 | case VE::SF19: OpKind = MCK_F32; break; |
3888 | 0 | case VE::SF20: OpKind = MCK_F32; break; |
3889 | 0 | case VE::SF21: OpKind = MCK_F32; break; |
3890 | 0 | case VE::SF22: OpKind = MCK_F32; break; |
3891 | 0 | case VE::SF23: OpKind = MCK_F32; break; |
3892 | 0 | case VE::SF24: OpKind = MCK_F32; break; |
3893 | 0 | case VE::SF25: OpKind = MCK_F32; break; |
3894 | 0 | case VE::SF26: OpKind = MCK_F32; break; |
3895 | 0 | case VE::SF27: OpKind = MCK_F32; break; |
3896 | 0 | case VE::SF28: OpKind = MCK_F32; break; |
3897 | 0 | case VE::SF29: OpKind = MCK_F32; break; |
3898 | 0 | case VE::SF30: OpKind = MCK_F32; break; |
3899 | 0 | case VE::SF31: OpKind = MCK_F32; break; |
3900 | 0 | case VE::SF32: OpKind = MCK_F32; break; |
3901 | 0 | case VE::SF33: OpKind = MCK_F32; break; |
3902 | 0 | case VE::SF34: OpKind = MCK_F32; break; |
3903 | 0 | case VE::SF35: OpKind = MCK_F32; break; |
3904 | 0 | case VE::SF36: OpKind = MCK_F32; break; |
3905 | 0 | case VE::SF37: OpKind = MCK_F32; break; |
3906 | 0 | case VE::SF38: OpKind = MCK_F32; break; |
3907 | 0 | case VE::SF39: OpKind = MCK_F32; break; |
3908 | 0 | case VE::SF40: OpKind = MCK_F32; break; |
3909 | 0 | case VE::SF41: OpKind = MCK_F32; break; |
3910 | 0 | case VE::SF42: OpKind = MCK_F32; break; |
3911 | 0 | case VE::SF43: OpKind = MCK_F32; break; |
3912 | 0 | case VE::SF44: OpKind = MCK_F32; break; |
3913 | 0 | case VE::SF45: OpKind = MCK_F32; break; |
3914 | 0 | case VE::SF46: OpKind = MCK_F32; break; |
3915 | 0 | case VE::SF47: OpKind = MCK_F32; break; |
3916 | 0 | case VE::SF48: OpKind = MCK_F32; break; |
3917 | 0 | case VE::SF49: OpKind = MCK_F32; break; |
3918 | 0 | case VE::SF50: OpKind = MCK_F32; break; |
3919 | 0 | case VE::SF51: OpKind = MCK_F32; break; |
3920 | 0 | case VE::SF52: OpKind = MCK_F32; break; |
3921 | 0 | case VE::SF53: OpKind = MCK_F32; break; |
3922 | 0 | case VE::SF54: OpKind = MCK_F32; break; |
3923 | 0 | case VE::SF55: OpKind = MCK_F32; break; |
3924 | 0 | case VE::SF56: OpKind = MCK_F32; break; |
3925 | 0 | case VE::SF57: OpKind = MCK_F32; break; |
3926 | 0 | case VE::SF58: OpKind = MCK_F32; break; |
3927 | 0 | case VE::SF59: OpKind = MCK_F32; break; |
3928 | 0 | case VE::SF60: OpKind = MCK_F32; break; |
3929 | 0 | case VE::SF61: OpKind = MCK_F32; break; |
3930 | 0 | case VE::SF62: OpKind = MCK_F32; break; |
3931 | 0 | case VE::SF63: OpKind = MCK_F32; break; |
3932 | 0 | case VE::SX8: OpKind = MCK_I64; break; |
3933 | 0 | case VE::SX9: OpKind = MCK_I64; break; |
3934 | 0 | case VE::SX10: OpKind = MCK_I64; break; |
3935 | 0 | case VE::SX11: OpKind = MCK_I64; break; |
3936 | 0 | case VE::SX14: OpKind = MCK_I64; break; |
3937 | 0 | case VE::SX15: OpKind = MCK_I64; break; |
3938 | 0 | case VE::SX16: OpKind = MCK_I64; break; |
3939 | 0 | case VE::SX0: OpKind = MCK_I64; break; |
3940 | 0 | case VE::SX1: OpKind = MCK_I64; break; |
3941 | 0 | case VE::SX2: OpKind = MCK_I64; break; |
3942 | 0 | case VE::SX3: OpKind = MCK_I64; break; |
3943 | 0 | case VE::SX4: OpKind = MCK_I64; break; |
3944 | 0 | case VE::SX5: OpKind = MCK_I64; break; |
3945 | 0 | case VE::SX6: OpKind = MCK_I64; break; |
3946 | 0 | case VE::SX7: OpKind = MCK_I64; break; |
3947 | 0 | case VE::SX12: OpKind = MCK_I64; break; |
3948 | 0 | case VE::SX13: OpKind = MCK_I64; break; |
3949 | 0 | case VE::SX17: OpKind = MCK_I64; break; |
3950 | 0 | case VE::SX18: OpKind = MCK_I64; break; |
3951 | 0 | case VE::SX19: OpKind = MCK_I64; break; |
3952 | 0 | case VE::SX20: OpKind = MCK_I64; break; |
3953 | 0 | case VE::SX21: OpKind = MCK_I64; break; |
3954 | 0 | case VE::SX22: OpKind = MCK_I64; break; |
3955 | 0 | case VE::SX23: OpKind = MCK_I64; break; |
3956 | 0 | case VE::SX24: OpKind = MCK_I64; break; |
3957 | 0 | case VE::SX25: OpKind = MCK_I64; break; |
3958 | 0 | case VE::SX26: OpKind = MCK_I64; break; |
3959 | 0 | case VE::SX27: OpKind = MCK_I64; break; |
3960 | 0 | case VE::SX28: OpKind = MCK_I64; break; |
3961 | 0 | case VE::SX29: OpKind = MCK_I64; break; |
3962 | 0 | case VE::SX30: OpKind = MCK_I64; break; |
3963 | 0 | case VE::SX31: OpKind = MCK_I64; break; |
3964 | 0 | case VE::SX32: OpKind = MCK_I64; break; |
3965 | 0 | case VE::SX33: OpKind = MCK_I64; break; |
3966 | 0 | case VE::SX34: OpKind = MCK_I64; break; |
3967 | 0 | case VE::SX35: OpKind = MCK_I64; break; |
3968 | 0 | case VE::SX36: OpKind = MCK_I64; break; |
3969 | 0 | case VE::SX37: OpKind = MCK_I64; break; |
3970 | 0 | case VE::SX38: OpKind = MCK_I64; break; |
3971 | 0 | case VE::SX39: OpKind = MCK_I64; break; |
3972 | 0 | case VE::SX40: OpKind = MCK_I64; break; |
3973 | 0 | case VE::SX41: OpKind = MCK_I64; break; |
3974 | 0 | case VE::SX42: OpKind = MCK_I64; break; |
3975 | 0 | case VE::SX43: OpKind = MCK_I64; break; |
3976 | 0 | case VE::SX44: OpKind = MCK_I64; break; |
3977 | 0 | case VE::SX45: OpKind = MCK_I64; break; |
3978 | 0 | case VE::SX46: OpKind = MCK_I64; break; |
3979 | 0 | case VE::SX47: OpKind = MCK_I64; break; |
3980 | 0 | case VE::SX48: OpKind = MCK_I64; break; |
3981 | 0 | case VE::SX49: OpKind = MCK_I64; break; |
3982 | 0 | case VE::SX50: OpKind = MCK_I64; break; |
3983 | 0 | case VE::SX51: OpKind = MCK_I64; break; |
3984 | 0 | case VE::SX52: OpKind = MCK_I64; break; |
3985 | 0 | case VE::SX53: OpKind = MCK_I64; break; |
3986 | 0 | case VE::SX54: OpKind = MCK_I64; break; |
3987 | 0 | case VE::SX55: OpKind = MCK_I64; break; |
3988 | 0 | case VE::SX56: OpKind = MCK_I64; break; |
3989 | 0 | case VE::SX57: OpKind = MCK_I64; break; |
3990 | 0 | case VE::SX58: OpKind = MCK_I64; break; |
3991 | 0 | case VE::SX59: OpKind = MCK_I64; break; |
3992 | 0 | case VE::SX60: OpKind = MCK_I64; break; |
3993 | 0 | case VE::SX61: OpKind = MCK_I64; break; |
3994 | 0 | case VE::SX62: OpKind = MCK_I64; break; |
3995 | 0 | case VE::SX63: OpKind = MCK_I64; break; |
3996 | 0 | case VE::Q0: OpKind = MCK_F128; break; |
3997 | 0 | case VE::Q1: OpKind = MCK_F128; break; |
3998 | 0 | case VE::Q2: OpKind = MCK_F128; break; |
3999 | 0 | case VE::Q3: OpKind = MCK_F128; break; |
4000 | 0 | case VE::Q4: OpKind = MCK_F128; break; |
4001 | 0 | case VE::Q5: OpKind = MCK_F128; break; |
4002 | 0 | case VE::Q6: OpKind = MCK_F128; break; |
4003 | 0 | case VE::Q7: OpKind = MCK_F128; break; |
4004 | 0 | case VE::Q8: OpKind = MCK_F128; break; |
4005 | 0 | case VE::Q9: OpKind = MCK_F128; break; |
4006 | 0 | case VE::Q10: OpKind = MCK_F128; break; |
4007 | 0 | case VE::Q11: OpKind = MCK_F128; break; |
4008 | 0 | case VE::Q12: OpKind = MCK_F128; break; |
4009 | 0 | case VE::Q13: OpKind = MCK_F128; break; |
4010 | 0 | case VE::Q14: OpKind = MCK_F128; break; |
4011 | 0 | case VE::Q15: OpKind = MCK_F128; break; |
4012 | 0 | case VE::Q16: OpKind = MCK_F128; break; |
4013 | 0 | case VE::Q17: OpKind = MCK_F128; break; |
4014 | 0 | case VE::Q18: OpKind = MCK_F128; break; |
4015 | 0 | case VE::Q19: OpKind = MCK_F128; break; |
4016 | 0 | case VE::Q20: OpKind = MCK_F128; break; |
4017 | 0 | case VE::Q21: OpKind = MCK_F128; break; |
4018 | 0 | case VE::Q22: OpKind = MCK_F128; break; |
4019 | 0 | case VE::Q23: OpKind = MCK_F128; break; |
4020 | 0 | case VE::Q24: OpKind = MCK_F128; break; |
4021 | 0 | case VE::Q25: OpKind = MCK_F128; break; |
4022 | 0 | case VE::Q26: OpKind = MCK_F128; break; |
4023 | 0 | case VE::Q27: OpKind = MCK_F128; break; |
4024 | 0 | case VE::Q28: OpKind = MCK_F128; break; |
4025 | 0 | case VE::Q29: OpKind = MCK_F128; break; |
4026 | 0 | case VE::Q30: OpKind = MCK_F128; break; |
4027 | 0 | case VE::Q31: OpKind = MCK_F128; break; |
4028 | 0 | case VE::V0: OpKind = MCK_V64; break; |
4029 | 0 | case VE::V1: OpKind = MCK_V64; break; |
4030 | 0 | case VE::V2: OpKind = MCK_V64; break; |
4031 | 0 | case VE::V3: OpKind = MCK_V64; break; |
4032 | 0 | case VE::V4: OpKind = MCK_V64; break; |
4033 | 0 | case VE::V5: OpKind = MCK_V64; break; |
4034 | 0 | case VE::V6: OpKind = MCK_V64; break; |
4035 | 0 | case VE::V7: OpKind = MCK_V64; break; |
4036 | 0 | case VE::V8: OpKind = MCK_V64; break; |
4037 | 0 | case VE::V9: OpKind = MCK_V64; break; |
4038 | 0 | case VE::V10: OpKind = MCK_V64; break; |
4039 | 0 | case VE::V11: OpKind = MCK_V64; break; |
4040 | 0 | case VE::V12: OpKind = MCK_V64; break; |
4041 | 0 | case VE::V13: OpKind = MCK_V64; break; |
4042 | 0 | case VE::V14: OpKind = MCK_V64; break; |
4043 | 0 | case VE::V15: OpKind = MCK_V64; break; |
4044 | 0 | case VE::V16: OpKind = MCK_V64; break; |
4045 | 0 | case VE::V17: OpKind = MCK_V64; break; |
4046 | 0 | case VE::V18: OpKind = MCK_V64; break; |
4047 | 0 | case VE::V19: OpKind = MCK_V64; break; |
4048 | 0 | case VE::V20: OpKind = MCK_V64; break; |
4049 | 0 | case VE::V21: OpKind = MCK_V64; break; |
4050 | 0 | case VE::V22: OpKind = MCK_V64; break; |
4051 | 0 | case VE::V23: OpKind = MCK_V64; break; |
4052 | 0 | case VE::V24: OpKind = MCK_V64; break; |
4053 | 0 | case VE::V25: OpKind = MCK_V64; break; |
4054 | 0 | case VE::V26: OpKind = MCK_V64; break; |
4055 | 0 | case VE::V27: OpKind = MCK_V64; break; |
4056 | 0 | case VE::V28: OpKind = MCK_V64; break; |
4057 | 0 | case VE::V29: OpKind = MCK_V64; break; |
4058 | 0 | case VE::V30: OpKind = MCK_V64; break; |
4059 | 0 | case VE::V31: OpKind = MCK_V64; break; |
4060 | 0 | case VE::V32: OpKind = MCK_V64; break; |
4061 | 0 | case VE::V33: OpKind = MCK_V64; break; |
4062 | 0 | case VE::V34: OpKind = MCK_V64; break; |
4063 | 0 | case VE::V35: OpKind = MCK_V64; break; |
4064 | 0 | case VE::V36: OpKind = MCK_V64; break; |
4065 | 0 | case VE::V37: OpKind = MCK_V64; break; |
4066 | 0 | case VE::V38: OpKind = MCK_V64; break; |
4067 | 0 | case VE::V39: OpKind = MCK_V64; break; |
4068 | 0 | case VE::V40: OpKind = MCK_V64; break; |
4069 | 0 | case VE::V41: OpKind = MCK_V64; break; |
4070 | 0 | case VE::V42: OpKind = MCK_V64; break; |
4071 | 0 | case VE::V43: OpKind = MCK_V64; break; |
4072 | 0 | case VE::V44: OpKind = MCK_V64; break; |
4073 | 0 | case VE::V45: OpKind = MCK_V64; break; |
4074 | 0 | case VE::V46: OpKind = MCK_V64; break; |
4075 | 0 | case VE::V47: OpKind = MCK_V64; break; |
4076 | 0 | case VE::V48: OpKind = MCK_V64; break; |
4077 | 0 | case VE::V49: OpKind = MCK_V64; break; |
4078 | 0 | case VE::V50: OpKind = MCK_V64; break; |
4079 | 0 | case VE::V51: OpKind = MCK_V64; break; |
4080 | 0 | case VE::V52: OpKind = MCK_V64; break; |
4081 | 0 | case VE::V53: OpKind = MCK_V64; break; |
4082 | 0 | case VE::V54: OpKind = MCK_V64; break; |
4083 | 0 | case VE::V55: OpKind = MCK_V64; break; |
4084 | 0 | case VE::V56: OpKind = MCK_V64; break; |
4085 | 0 | case VE::V57: OpKind = MCK_V64; break; |
4086 | 0 | case VE::V58: OpKind = MCK_V64; break; |
4087 | 0 | case VE::V59: OpKind = MCK_V64; break; |
4088 | 0 | case VE::V60: OpKind = MCK_V64; break; |
4089 | 0 | case VE::V61: OpKind = MCK_V64; break; |
4090 | 0 | case VE::V62: OpKind = MCK_V64; break; |
4091 | 0 | case VE::V63: OpKind = MCK_V64; break; |
4092 | 0 | case VE::VIX: OpKind = MCK_V64; break; |
4093 | 0 | case VE::VM0: OpKind = MCK_VM; break; |
4094 | 0 | case VE::VM1: OpKind = MCK_VM; break; |
4095 | 0 | case VE::VM2: OpKind = MCK_VM; break; |
4096 | 0 | case VE::VM3: OpKind = MCK_VM; break; |
4097 | 0 | case VE::VM4: OpKind = MCK_VM; break; |
4098 | 0 | case VE::VM5: OpKind = MCK_VM; break; |
4099 | 0 | case VE::VM6: OpKind = MCK_VM; break; |
4100 | 0 | case VE::VM7: OpKind = MCK_VM; break; |
4101 | 0 | case VE::VM8: OpKind = MCK_VM; break; |
4102 | 0 | case VE::VM9: OpKind = MCK_VM; break; |
4103 | 0 | case VE::VM10: OpKind = MCK_VM; break; |
4104 | 0 | case VE::VM11: OpKind = MCK_VM; break; |
4105 | 0 | case VE::VM12: OpKind = MCK_VM; break; |
4106 | 0 | case VE::VM13: OpKind = MCK_VM; break; |
4107 | 0 | case VE::VM14: OpKind = MCK_VM; break; |
4108 | 0 | case VE::VM15: OpKind = MCK_VM; break; |
4109 | 0 | case VE::VMP0: OpKind = MCK_VM512; break; |
4110 | 0 | case VE::VMP1: OpKind = MCK_Reg9; break; |
4111 | 0 | case VE::VMP2: OpKind = MCK_Reg9; break; |
4112 | 0 | case VE::VMP3: OpKind = MCK_Reg9; break; |
4113 | 0 | case VE::VMP4: OpKind = MCK_Reg9; break; |
4114 | 0 | case VE::VMP5: OpKind = MCK_Reg9; break; |
4115 | 0 | case VE::VMP6: OpKind = MCK_Reg9; break; |
4116 | 0 | case VE::VMP7: OpKind = MCK_Reg9; break; |
4117 | 0 | } |
4118 | 0 | return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : |
4119 | 0 | getDiagKindFromRegisterClass(Kind); |
4120 | 0 | } |
4121 | | |
4122 | 0 | if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) |
4123 | 0 | return getDiagKindFromRegisterClass(Kind); |
4124 | | |
4125 | 0 | return MCTargetAsmParser::Match_InvalidOperand; |
4126 | 0 | } |
4127 | | |
4128 | | #ifndef NDEBUG |
4129 | 0 | const char *getMatchClassName(MatchClassKind Kind) { |
4130 | 0 | switch (Kind) { |
4131 | 0 | case InvalidMatchClass: return "InvalidMatchClass"; |
4132 | 0 | case OptionalMatchClass: return "OptionalMatchClass"; |
4133 | 0 | case MCK__40_: return "MCK__40_"; |
4134 | 0 | case MCK__41_: return "MCK__41_"; |
4135 | 0 | case MCK__DOT_d: return "MCK__DOT_d"; |
4136 | 0 | case MCK__DOT_d_DOT_nt: return "MCK__DOT_d_DOT_nt"; |
4137 | 0 | case MCK__DOT_d_DOT_t: return "MCK__DOT_d_DOT_t"; |
4138 | 0 | case MCK__DOT_l: return "MCK__DOT_l"; |
4139 | 0 | case MCK__DOT_l_DOT_nt: return "MCK__DOT_l_DOT_nt"; |
4140 | 0 | case MCK__DOT_l_DOT_t: return "MCK__DOT_l_DOT_t"; |
4141 | 0 | case MCK__DOT_s: return "MCK__DOT_s"; |
4142 | 0 | case MCK__DOT_s_DOT_nt: return "MCK__DOT_s_DOT_nt"; |
4143 | 0 | case MCK__DOT_s_DOT_t: return "MCK__DOT_s_DOT_t"; |
4144 | 0 | case MCK__DOT_w: return "MCK__DOT_w"; |
4145 | 0 | case MCK__DOT_w_DOT_nt: return "MCK__DOT_w_DOT_nt"; |
4146 | 0 | case MCK__DOT_w_DOT_t: return "MCK__DOT_w_DOT_t"; |
4147 | 0 | case MCK_VLS: return "MCK_VLS"; |
4148 | 0 | case MCK_Reg9: return "MCK_Reg9"; |
4149 | 0 | case MCK_VM512: return "MCK_VM512"; |
4150 | 0 | case MCK_VM: return "MCK_VM"; |
4151 | 0 | case MCK_MISC: return "MCK_MISC"; |
4152 | 0 | case MCK_F128: return "MCK_F128"; |
4153 | 0 | case MCK_F32: return "MCK_F32"; |
4154 | 0 | case MCK_I32: return "MCK_I32"; |
4155 | 0 | case MCK_I64: return "MCK_I64"; |
4156 | 0 | case MCK_V64: return "MCK_V64"; |
4157 | 0 | case MCK_CCOp: return "MCK_CCOp"; |
4158 | 0 | case MCK_Imm: return "MCK_Imm"; |
4159 | 0 | case MCK_MImm: return "MCK_MImm"; |
4160 | 0 | case MCK_RDOp: return "MCK_RDOp"; |
4161 | 0 | case MCK_SImm7: return "MCK_SImm7"; |
4162 | 0 | case MCK_UImm0to2: return "MCK_UImm0to2"; |
4163 | 0 | case MCK_UImm1: return "MCK_UImm1"; |
4164 | 0 | case MCK_UImm2: return "MCK_UImm2"; |
4165 | 0 | case MCK_UImm3: return "MCK_UImm3"; |
4166 | 0 | case MCK_UImm4: return "MCK_UImm4"; |
4167 | 0 | case MCK_UImm6: return "MCK_UImm6"; |
4168 | 0 | case MCK_UImm7: return "MCK_UImm7"; |
4169 | 0 | case MCK_MEMri: return "MCK_MEMri"; |
4170 | 0 | case MCK_MEMrii: return "MCK_MEMrii"; |
4171 | 0 | case MCK_MEMrri: return "MCK_MEMrri"; |
4172 | 0 | case MCK_MEMzi: return "MCK_MEMzi"; |
4173 | 0 | case MCK_MEMzii: return "MCK_MEMzii"; |
4174 | 0 | case MCK_MEMzri: return "MCK_MEMzri"; |
4175 | 0 | case MCK_Zero: return "MCK_Zero"; |
4176 | 0 | case NumMatchClassKinds: return "NumMatchClassKinds"; |
4177 | 0 | } |
4178 | 0 | llvm_unreachable("unhandled MatchClassKind!"); |
4179 | 0 | } |
4180 | | |
4181 | | #endif // NDEBUG |
4182 | | FeatureBitset VEAsmParser:: |
4183 | 0 | ComputeAvailableFeatures(const FeatureBitset &FB) const { |
4184 | 0 | FeatureBitset Features; |
4185 | 0 | return Features; |
4186 | 0 | } |
4187 | | |
4188 | | static bool checkAsmTiedOperandConstraints(const VEAsmParser&AsmParser, |
4189 | | unsigned Kind, |
4190 | | const OperandVector &Operands, |
4191 | 0 | uint64_t &ErrorInfo) { |
4192 | 0 | assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); |
4193 | 0 | const uint8_t *Converter = ConversionTable[Kind]; |
4194 | 0 | for (const uint8_t *p = Converter; *p; p += 2) { |
4195 | 0 | switch (*p) { |
4196 | 0 | case CVT_Tied: { |
4197 | 0 | unsigned OpIdx = *(p + 1); |
4198 | 0 | assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - |
4199 | 0 | std::begin(TiedAsmOperandTable)) && |
4200 | 0 | "Tied operand not found"); |
4201 | 0 | unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; |
4202 | 0 | unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; |
4203 | 0 | if (OpndNum1 != OpndNum2) { |
4204 | 0 | auto &SrcOp1 = Operands[OpndNum1]; |
4205 | 0 | auto &SrcOp2 = Operands[OpndNum2]; |
4206 | 0 | if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) { |
4207 | 0 | ErrorInfo = OpndNum2; |
4208 | 0 | return false; |
4209 | 0 | } |
4210 | 0 | } |
4211 | 0 | break; |
4212 | 0 | } |
4213 | 0 | default: |
4214 | 0 | break; |
4215 | 0 | } |
4216 | 0 | } |
4217 | 0 | return true; |
4218 | 0 | } |
4219 | | |
4220 | | static const char MnemonicTable[] = |
4221 | | "\006adds.l\tadds.w.sx\tadds.w.zx\006addu.l\006addu.w\003and\004andm\005" |
4222 | | "atmam\001b\003b.d\006b.d.nt\005b.d.t\003b.l\006b.l.nt\005b.l.t\003b.s\006" |
4223 | | "b.s.nt\005b.s.t\003b.w\006b.w.nt\005b.w.t\005baf.d\010baf.d.nt\007baf.d" |
4224 | | ".t\005baf.l\010baf.l.nt\007baf.l.t\005baf.s\010baf.s.nt\007baf.s.t\005b" |
4225 | | "af.w\010baf.w.nt\007baf.w.t\002br\004br.d\007br.d.nt\006br.d.t\004br.l\007" |
4226 | | "br.l.nt\006br.l.t\004br.s\007br.s.nt\006br.s.t\004br.w\007br.w.nt\006br" |
4227 | | ".w.t\006braf.d\tbraf.d.nt\010braf.d.t\006braf.l\tbraf.l.nt\010braf.l.t\006" |
4228 | | "braf.s\tbraf.s.nt\010braf.s.t\006braf.w\tbraf.w.nt\010braf.w.t\003brv\004" |
4229 | | "bsic\004bswp\005cas.l\005cas.w\007cmov.d.\007cmov.l.\007cmov.s.\007cmov" |
4230 | | ".w.\006cmps.l\tcmps.w.sx\tcmps.w.zx\006cmpu.l\006cmpu.w\007cvt.d.l\007c" |
4231 | | "vt.d.q\007cvt.d.s\007cvt.d.w\007cvt.l.d\007cvt.q.d\007cvt.q.s\007cvt.s." |
4232 | | "d\007cvt.s.q\007cvt.s.w\ncvt.w.d.sx\ncvt.w.d.zx\ncvt.w.s.sx\ncvt.w.s.zx" |
4233 | | "\006divs.l\tdivs.w.sx\tdivs.w.zx\006divu.l\006divu.w\003dld\007dldl.sx\007" |
4234 | | "dldl.zx\004dldu\003eqv\004eqvm\006fadd.d\006fadd.q\006fadd.s\006fcmp.d\006" |
4235 | | "fcmp.q\006fcmp.s\006fdiv.d\006fdiv.s\006fencec\006fencei\006fencem\005f" |
4236 | | "idcr\006fmax.d\006fmax.s\006fmin.d\006fmin.s\006fmul.d\006fmul.q\006fmu" |
4237 | | "l.s\006fsub.d\006fsub.q\006fsub.s\003lcr\002ld\007ld1b.sx\007ld1b.zx\007" |
4238 | | "ld2b.sx\007ld2b.zx\006ldl.sx\006ldl.zx\003ldu\003ldz\003lea\006lea.sl\003" |
4239 | | "lfr\005lhm.b\005lhm.h\005lhm.l\005lhm.w\003lpm\003lsv\004lvix\003lvl\003" |
4240 | | "lvm\003lvs\004lzvm\006maxs.l\tmaxs.w.sx\tmaxs.w.zx\006mins.l\tmins.w.sx" |
4241 | | "\tmins.w.zx\004monc\010monc.hdb\003mrg\006muls.l\010muls.l.w\tmuls.w.sx" |
4242 | | "\tmuls.w.zx\006mulu.l\006mulu.w\004negm\003nnd\004nndm\003nop\002or\003" |
4243 | | "orm\004pcnt\004pcvm\004pfch\005pfchv\010pfchv.nc\006pvadds\tpvadds.lo\t" |
4244 | | "pvadds.up\006pvaddu\tpvaddu.lo\tpvaddu.up\005pvand\010pvand.lo\010pvand" |
4245 | | ".up\005pvbrd\005pvbrv\010pvbrv.lo\010pvbrv.up\006pvcmps\tpvcmps.lo\tpvc" |
4246 | | "mps.up\006pvcmpu\tpvcmpu.lo\tpvcmpu.up\tpvcvt.s.w\014pvcvt.s.w.lo\014pv" |
4247 | | "cvt.s.w.up\tpvcvt.w.s\014pvcvt.w.s.lo\014pvcvt.w.s.up\005pveqv\010pveqv" |
4248 | | ".lo\010pveqv.up\006pvfadd\tpvfadd.lo\tpvfadd.up\006pvfcmp\tpvfcmp.lo\tp" |
4249 | | "vfcmp.up\006pvfmad\tpvfmad.lo\tpvfmad.up\006pvfmax\tpvfmax.lo\tpvfmax.u" |
4250 | | "p\006pvfmin\tpvfmin.lo\tpvfmin.up\013pvfmk.s.lo.\015pvfmk.s.lo.af\015pv" |
4251 | | "fmk.s.lo.at\013pvfmk.s.up.\015pvfmk.s.up.af\015pvfmk.s.up.at\013pvfmk.w" |
4252 | | ".up.\015pvfmk.w.up.af\015pvfmk.w.up.at\006pvfmsb\tpvfmsb.lo\tpvfmsb.up\006" |
4253 | | "pvfmul\tpvfmul.lo\tpvfmul.up\007pvfnmad\npvfnmad.lo\npvfnmad.up\007pvfn" |
4254 | | "msb\npvfnmsb.lo\npvfnmsb.up\006pvfsub\tpvfsub.lo\tpvfsub.up\005pvldz\010" |
4255 | | "pvldz.lo\010pvldz.up\006pvmaxs\tpvmaxs.lo\tpvmaxs.up\006pvmins\tpvmins." |
4256 | | "lo\tpvmins.up\004pvor\007pvor.lo\007pvor.up\006pvpcnt\tpvpcnt.lo\tpvpcn" |
4257 | | "t.up\005pvrcp\010pvrcp.lo\010pvrcp.up\007pvrsqrt\npvrsqrt.lo\016pvrsqrt" |
4258 | | ".lo.nex\013pvrsqrt.nex\npvrsqrt.up\016pvrsqrt.up.nex\005pvseq\010pvseq." |
4259 | | "lo\010pvseq.up\005pvsla\010pvsla.lo\010pvsla.up\005pvsll\010pvsll.lo\010" |
4260 | | "pvsll.up\005pvsra\010pvsra.lo\010pvsra.up\005pvsrl\010pvsrl.lo\010pvsrl" |
4261 | | ".up\006pvsubs\tpvsubs.lo\tpvsubs.up\006pvsubu\tpvsubu.lo\tpvsubu.up\005" |
4262 | | "pvxor\010pvxor.lo\010pvxor.up\003scr\003sfr\005shm.b\005shm.h\005shm.l\005" |
4263 | | "shm.w\003sic\005sla.l\010sla.w.sx\010sla.w.zx\003sld\003sll\004smir\004" |
4264 | | "smvl\003spm\005sra.l\010sra.w.sx\010sra.w.zx\003srd\003srl\002st\004st1" |
4265 | | "b\004st2b\003stl\003stu\006subs.l\tsubs.w.sx\tsubs.w.zx\006subu.l\006su" |
4266 | | "bu.w\003svl\003svm\004svob\004tovm\007ts1am.l\007ts1am.w\005ts2am\005ts" |
4267 | | "3am\004tscr\007vadds.l\nvadds.w.sx\007vaddu.l\004vand\004vbrd\005vbrdl\005" |
4268 | | "vbrdu\004vbrv\007vcmps.l\nvcmps.w.sx\007vcmpu.l\003vcp\010vcvt.d.l\010v" |
4269 | | "cvt.d.s\010vcvt.d.w\010vcvt.l.d\010vcvt.s.d\010vcvt.s.w\013vcvt.w.d.sx\013" |
4270 | | "vcvt.w.d.zx\013vcvt.w.s.sx\013vcvt.w.s.zx\007vdivs.l\nvdivs.w.sx\nvdivs" |
4271 | | ".w.zx\007vdivu.l\007vdivu.w\004veqv\003vex\007vfadd.d\007vfcmp.d\007vfd" |
4272 | | "iv.d\007vfdiv.s\006vfia.d\006vfia.s\007vfiam.d\007vfiam.s\006vfim.d\006" |
4273 | | "vfim.s\007vfima.d\007vfima.s\007vfims.d\007vfims.s\006vfis.d\006vfis.s\007" |
4274 | | "vfism.d\007vfism.s\007vfmad.d\007vfmax.d\007vfmin.d\007vfmk.d.\tvfmk.d." |
4275 | | "af\tvfmk.d.at\007vfmk.l.\tvfmk.l.af\tvfmk.l.at\007vfmk.w.\tvfmk.w.af\tv" |
4276 | | "fmk.w.at\007vfmsb.d\007vfmul.d\010vfnmad.d\010vfnmsb.d\014vfrmax.d.fst\014" |
4277 | | "vfrmax.d.lst\014vfrmax.s.fst\014vfrmax.s.lst\014vfrmin.d.fst\014vfrmin." |
4278 | | "d.lst\014vfrmin.s.fst\014vfrmin.s.lst\010vfsqrt.d\010vfsqrt.s\007vfsub." |
4279 | | "d\007vfsum.d\007vfsum.s\003vgt\006vgt.nc\007vgtl.sx\nvgtl.sx.nc\007vgtl" |
4280 | | ".zx\nvgtl.zx.nc\004vgtu\007vgtu.nc\003vld\006vld.nc\005vld2d\010vld2d.n" |
4281 | | "c\007vldl.sx\nvldl.sx.nc\007vldl.zx\nvldl.zx.nc\tvldl2d.sx\014vldl2d.sx" |
4282 | | ".nc\tvldl2d.zx\014vldl2d.zx.nc\004vldu\007vldu.nc\006vldu2d\tvldu2d.nc\004" |
4283 | | "vldz\007vmaxs.l\nvmaxs.w.sx\007vmins.l\nvmins.w.sx\004vmrg\006vmrg.w\007" |
4284 | | "vmuls.l\tvmuls.l.w\nvmuls.w.sx\nvmuls.w.zx\007vmulu.l\007vmulu.w\003vmv" |
4285 | | "\003vor\005vpcnt\005vrand\006vrcp.d\014vrmaxs.l.fst\014vrmaxs.l.lst\017" |
4286 | | "vrmaxs.w.fst.sx\017vrmaxs.w.fst.zx\017vrmaxs.w.lst.sx\017vrmaxs.w.lst.z" |
4287 | | "x\014vrmins.l.fst\014vrmins.l.lst\017vrmins.w.fst.sx\017vrmins.w.fst.zx" |
4288 | | "\017vrmins.w.lst.sx\017vrmins.w.lst.zx\004vror\010vrsqrt.d\014vrsqrt.d." |
4289 | | "nex\005vrxor\003vsc\006vsc.nc\tvsc.nc.ot\006vsc.ot\004vscl\007vscl.nc\n" |
4290 | | "vscl.nc.ot\007vscl.ot\004vscu\007vscu.nc\nvscu.nc.ot\007vscu.ot\004vseq" |
4291 | | "\004vsfa\004vshf\006vsla.l\tvsla.w.sx\004vsld\004vsll\006vsra.l\tvsra.w" |
4292 | | ".sx\004vsrd\004vsrl\003vst\006vst.nc\tvst.nc.ot\006vst.ot\005vst2d\010v" |
4293 | | "st2d.nc\013vst2d.nc.ot\010vst2d.ot\004vstl\007vstl.nc\nvstl.nc.ot\007vs" |
4294 | | "tl.ot\006vstl2d\tvstl2d.nc\014vstl2d.nc.ot\tvstl2d.ot\004vstu\007vstu.n" |
4295 | | "c\nvstu.nc.ot\007vstu.ot\006vstu2d\tvstu2d.nc\014vstu2d.nc.ot\tvstu2d.o" |
4296 | | "t\007vsubs.l\nvsubs.w.sx\007vsubu.l\006vsum.l\tvsum.w.sx\tvsum.w.zx\004" |
4297 | | "vxor\003xor\004xorm"; |
4298 | | |
4299 | | // Feature bitsets. |
4300 | | enum : uint8_t { |
4301 | | AMFBS_None, |
4302 | | }; |
4303 | | |
4304 | | static constexpr FeatureBitset FeatureBitsets[] = { |
4305 | | {}, // AMFBS_None |
4306 | | }; |
4307 | | |
4308 | | namespace { |
4309 | | struct MatchEntry { |
4310 | | uint16_t Mnemonic; |
4311 | | uint16_t Opcode; |
4312 | | uint8_t ConvertFn; |
4313 | | uint8_t RequiredFeaturesIdx; |
4314 | | uint8_t Classes[7]; |
4315 | 0 | StringRef getMnemonic() const { |
4316 | 0 | return StringRef(MnemonicTable + Mnemonic + 1, |
4317 | 0 | MnemonicTable[Mnemonic]); |
4318 | 0 | } |
4319 | | }; |
4320 | | |
4321 | | // Predicate for searching for an opcode. |
4322 | | struct LessOpcode { |
4323 | 0 | bool operator()(const MatchEntry &LHS, StringRef RHS) { |
4324 | 0 | return LHS.getMnemonic() < RHS; |
4325 | 0 | } |
4326 | 0 | bool operator()(StringRef LHS, const MatchEntry &RHS) { |
4327 | 0 | return LHS < RHS.getMnemonic(); |
4328 | 0 | } |
4329 | 0 | bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { |
4330 | 0 | return LHS.getMnemonic() < RHS.getMnemonic(); |
4331 | 0 | } |
4332 | | }; |
4333 | | } // end anonymous namespace |
4334 | | |
4335 | | static const MatchEntry MatchTable0[] = { |
4336 | | { 0 /* adds.l */, VE::ADDSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4337 | | { 0 /* adds.l */, VE::ADDSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4338 | | { 0 /* adds.l */, VE::ADDSLri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4339 | | { 0 /* adds.l */, VE::ADDSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4340 | | { 7 /* adds.w.sx */, VE::ADDSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4341 | | { 7 /* adds.w.sx */, VE::ADDSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4342 | | { 7 /* adds.w.sx */, VE::ADDSWSXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4343 | | { 7 /* adds.w.sx */, VE::ADDSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4344 | | { 17 /* adds.w.zx */, VE::ADDSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4345 | | { 17 /* adds.w.zx */, VE::ADDSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4346 | | { 17 /* adds.w.zx */, VE::ADDSWZXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4347 | | { 17 /* adds.w.zx */, VE::ADDSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4348 | | { 27 /* addu.l */, VE::ADDULrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4349 | | { 27 /* addu.l */, VE::ADDULrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4350 | | { 27 /* addu.l */, VE::ADDULri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4351 | | { 27 /* addu.l */, VE::ADDULim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4352 | | { 34 /* addu.w */, VE::ADDUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4353 | | { 34 /* addu.w */, VE::ADDUWrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4354 | | { 34 /* addu.w */, VE::ADDUWri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4355 | | { 34 /* addu.w */, VE::ADDUWim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4356 | | { 41 /* and */, VE::ANDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4357 | | { 41 /* and */, VE::ANDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4358 | | { 41 /* and */, VE::ANDri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4359 | | { 41 /* and */, VE::ANDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4360 | | { 45 /* andm */, VE::ANDMmm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_VM, MCK_VM }, }, |
4361 | | { 50 /* atmam */, VE::ATMAMrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_I64 }, }, |
4362 | | { 50 /* atmam */, VE::ATMAMrii, Convert__Reg1_0__MEMri2_1__UImm0to21_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_UImm0to2 }, }, |
4363 | | { 50 /* atmam */, VE::ATMAMzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_I64 }, }, |
4364 | | { 50 /* atmam */, VE::ATMAMzii, Convert__Reg1_0__MEMzi2_1__UImm0to21_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_UImm0to2 }, }, |
4365 | | { 56 /* b */, VE::BCFDrri, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_I64, MCK_MEMri }, }, |
4366 | | { 56 /* b */, VE::BCFDrzi, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_I64, MCK_MEMzi }, }, |
4367 | | { 56 /* b */, VE::BCFDiri, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_SImm7, MCK_MEMri }, }, |
4368 | | { 56 /* b */, VE::BCFDizi, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_SImm7, MCK_MEMzi }, }, |
4369 | | { 56 /* b */, VE::BCFDrri_nt, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_I64, MCK_MEMri }, }, |
4370 | | { 56 /* b */, VE::BCFDrzi_nt, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_I64, MCK_MEMzi }, }, |
4371 | | { 56 /* b */, VE::BCFDiri_nt, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_SImm7, MCK_MEMri }, }, |
4372 | | { 56 /* b */, VE::BCFDizi_nt, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_SImm7, MCK_MEMzi }, }, |
4373 | | { 56 /* b */, VE::BCFDrri_t, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_I64, MCK_MEMri }, }, |
4374 | | { 56 /* b */, VE::BCFDrzi_t, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_I64, MCK_MEMzi }, }, |
4375 | | { 56 /* b */, VE::BCFDiri_t, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_SImm7, MCK_MEMri }, }, |
4376 | | { 56 /* b */, VE::BCFDizi_t, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_SImm7, MCK_MEMzi }, }, |
4377 | | { 56 /* b */, VE::BCFLrri, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_I64, MCK_MEMri }, }, |
4378 | | { 56 /* b */, VE::BCFLrzi, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_I64, MCK_MEMzi }, }, |
4379 | | { 56 /* b */, VE::BCFLiri, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_SImm7, MCK_MEMri }, }, |
4380 | | { 56 /* b */, VE::BCFLizi, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_SImm7, MCK_MEMzi }, }, |
4381 | | { 56 /* b */, VE::BCFLrri_nt, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_I64, MCK_MEMri }, }, |
4382 | | { 56 /* b */, VE::BCFLrzi_nt, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_I64, MCK_MEMzi }, }, |
4383 | | { 56 /* b */, VE::BCFLiri_nt, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_SImm7, MCK_MEMri }, }, |
4384 | | { 56 /* b */, VE::BCFLizi_nt, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_SImm7, MCK_MEMzi }, }, |
4385 | | { 56 /* b */, VE::BCFLrri_t, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_I64, MCK_MEMri }, }, |
4386 | | { 56 /* b */, VE::BCFLrzi_t, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_I64, MCK_MEMzi }, }, |
4387 | | { 56 /* b */, VE::BCFLiri_t, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_SImm7, MCK_MEMri }, }, |
4388 | | { 56 /* b */, VE::BCFLizi_t, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_SImm7, MCK_MEMzi }, }, |
4389 | | { 56 /* b */, VE::BCFSrri, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_F32, MCK_MEMri }, }, |
4390 | | { 56 /* b */, VE::BCFSrzi, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_F32, MCK_MEMzi }, }, |
4391 | | { 56 /* b */, VE::BCFSiri, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_SImm7, MCK_MEMri }, }, |
4392 | | { 56 /* b */, VE::BCFSizi, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_SImm7, MCK_MEMzi }, }, |
4393 | | { 56 /* b */, VE::BCFSrri_nt, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_F32, MCK_MEMri }, }, |
4394 | | { 56 /* b */, VE::BCFSrzi_nt, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_F32, MCK_MEMzi }, }, |
4395 | | { 56 /* b */, VE::BCFSiri_nt, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_SImm7, MCK_MEMri }, }, |
4396 | | { 56 /* b */, VE::BCFSizi_nt, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_SImm7, MCK_MEMzi }, }, |
4397 | | { 56 /* b */, VE::BCFSrri_t, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_F32, MCK_MEMri }, }, |
4398 | | { 56 /* b */, VE::BCFSrzi_t, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_F32, MCK_MEMzi }, }, |
4399 | | { 56 /* b */, VE::BCFSiri_t, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_SImm7, MCK_MEMri }, }, |
4400 | | { 56 /* b */, VE::BCFSizi_t, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_SImm7, MCK_MEMzi }, }, |
4401 | | { 56 /* b */, VE::BCFWrri, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_I32, MCK_MEMri }, }, |
4402 | | { 56 /* b */, VE::BCFWrzi, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_I32, MCK_MEMzi }, }, |
4403 | | { 56 /* b */, VE::BCFWiri, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_SImm7, MCK_MEMri }, }, |
4404 | | { 56 /* b */, VE::BCFWizi, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_SImm7, MCK_MEMzi }, }, |
4405 | | { 56 /* b */, VE::BCFWrri_nt, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_I32, MCK_MEMri }, }, |
4406 | | { 56 /* b */, VE::BCFWrzi_nt, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_I32, MCK_MEMzi }, }, |
4407 | | { 56 /* b */, VE::BCFWiri_nt, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_SImm7, MCK_MEMri }, }, |
4408 | | { 56 /* b */, VE::BCFWizi_nt, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_SImm7, MCK_MEMzi }, }, |
4409 | | { 56 /* b */, VE::BCFWrri_t, Convert__CCOp1_0__Reg1_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_I32, MCK_MEMri }, }, |
4410 | | { 56 /* b */, VE::BCFWrzi_t, Convert__CCOp1_0__Reg1_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_I32, MCK_MEMzi }, }, |
4411 | | { 56 /* b */, VE::BCFWiri_t, Convert__CCOp1_0__SImm71_2__MEMri2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_SImm7, MCK_MEMri }, }, |
4412 | | { 56 /* b */, VE::BCFWizi_t, Convert__CCOp1_0__SImm71_2__MEMzi2_3, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_SImm7, MCK_MEMzi }, }, |
4413 | | { 58 /* b.d */, VE::BCFDari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4414 | | { 58 /* b.d */, VE::BCFDazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4415 | | { 62 /* b.d.nt */, VE::BCFDari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4416 | | { 62 /* b.d.nt */, VE::BCFDazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4417 | | { 69 /* b.d.t */, VE::BCFDari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4418 | | { 69 /* b.d.t */, VE::BCFDazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4419 | | { 75 /* b.l */, VE::BCFLari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4420 | | { 75 /* b.l */, VE::BCFLazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4421 | | { 79 /* b.l.nt */, VE::BCFLari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4422 | | { 79 /* b.l.nt */, VE::BCFLazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4423 | | { 86 /* b.l.t */, VE::BCFLari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4424 | | { 86 /* b.l.t */, VE::BCFLazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4425 | | { 92 /* b.s */, VE::BCFSari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4426 | | { 92 /* b.s */, VE::BCFSazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4427 | | { 96 /* b.s.nt */, VE::BCFSari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4428 | | { 96 /* b.s.nt */, VE::BCFSazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4429 | | { 103 /* b.s.t */, VE::BCFSari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4430 | | { 103 /* b.s.t */, VE::BCFSazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4431 | | { 109 /* b.w */, VE::BCFWari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4432 | | { 109 /* b.w */, VE::BCFWazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4433 | | { 113 /* b.w.nt */, VE::BCFWari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4434 | | { 113 /* b.w.nt */, VE::BCFWazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4435 | | { 120 /* b.w.t */, VE::BCFWari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4436 | | { 120 /* b.w.t */, VE::BCFWazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4437 | | { 126 /* baf.d */, VE::BCFDnari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4438 | | { 126 /* baf.d */, VE::BCFDnazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4439 | | { 132 /* baf.d.nt */, VE::BCFDnari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4440 | | { 132 /* baf.d.nt */, VE::BCFDnazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4441 | | { 141 /* baf.d.t */, VE::BCFDnari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4442 | | { 141 /* baf.d.t */, VE::BCFDnazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4443 | | { 149 /* baf.l */, VE::BCFLnari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4444 | | { 149 /* baf.l */, VE::BCFLnazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4445 | | { 155 /* baf.l.nt */, VE::BCFLnari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4446 | | { 155 /* baf.l.nt */, VE::BCFLnazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4447 | | { 164 /* baf.l.t */, VE::BCFLnari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4448 | | { 164 /* baf.l.t */, VE::BCFLnazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4449 | | { 172 /* baf.s */, VE::BCFSnari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4450 | | { 172 /* baf.s */, VE::BCFSnazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4451 | | { 178 /* baf.s.nt */, VE::BCFSnari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4452 | | { 178 /* baf.s.nt */, VE::BCFSnazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4453 | | { 187 /* baf.s.t */, VE::BCFSnari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4454 | | { 187 /* baf.s.t */, VE::BCFSnazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4455 | | { 195 /* baf.w */, VE::BCFWnari, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4456 | | { 195 /* baf.w */, VE::BCFWnazi, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4457 | | { 201 /* baf.w.nt */, VE::BCFWnari_nt, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4458 | | { 201 /* baf.w.nt */, VE::BCFWnazi_nt, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4459 | | { 210 /* baf.w.t */, VE::BCFWnari_t, Convert__MEMri2_0, AMFBS_None, { MCK_MEMri }, }, |
4460 | | { 210 /* baf.w.t */, VE::BCFWnazi_t, Convert__MEMzi2_0, AMFBS_None, { MCK_MEMzi }, }, |
4461 | | { 218 /* br */, VE::BRCFDrr, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_I64, MCK_I64, MCK_Imm }, }, |
4462 | | { 218 /* br */, VE::BRCFDrz, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_I64, MCK_Zero, MCK_Imm }, }, |
4463 | | { 218 /* br */, VE::BRCFDir, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_SImm7, MCK_I64, MCK_Imm }, }, |
4464 | | { 218 /* br */, VE::BRCFDiz, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4465 | | { 218 /* br */, VE::BRCFDrr_nt, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_I64, MCK_I64, MCK_Imm }, }, |
4466 | | { 218 /* br */, VE::BRCFDrz_nt, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_I64, MCK_Zero, MCK_Imm }, }, |
4467 | | { 218 /* br */, VE::BRCFDir_nt, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_SImm7, MCK_I64, MCK_Imm }, }, |
4468 | | { 218 /* br */, VE::BRCFDiz_nt, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_nt, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4469 | | { 218 /* br */, VE::BRCFDrr_t, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_I64, MCK_I64, MCK_Imm }, }, |
4470 | | { 218 /* br */, VE::BRCFDrz_t, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_I64, MCK_Zero, MCK_Imm }, }, |
4471 | | { 218 /* br */, VE::BRCFDir_t, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_SImm7, MCK_I64, MCK_Imm }, }, |
4472 | | { 218 /* br */, VE::BRCFDiz_t, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_d_DOT_t, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4473 | | { 218 /* br */, VE::BRCFLrr, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_I64, MCK_I64, MCK_Imm }, }, |
4474 | | { 218 /* br */, VE::BRCFLrz, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_I64, MCK_Zero, MCK_Imm }, }, |
4475 | | { 218 /* br */, VE::BRCFLir, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_SImm7, MCK_I64, MCK_Imm }, }, |
4476 | | { 218 /* br */, VE::BRCFLiz, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4477 | | { 218 /* br */, VE::BRCFLrr_nt, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_I64, MCK_I64, MCK_Imm }, }, |
4478 | | { 218 /* br */, VE::BRCFLrz_nt, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_I64, MCK_Zero, MCK_Imm }, }, |
4479 | | { 218 /* br */, VE::BRCFLir_nt, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_SImm7, MCK_I64, MCK_Imm }, }, |
4480 | | { 218 /* br */, VE::BRCFLiz_nt, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_nt, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4481 | | { 218 /* br */, VE::BRCFLrr_t, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_I64, MCK_I64, MCK_Imm }, }, |
4482 | | { 218 /* br */, VE::BRCFLrz_t, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_I64, MCK_Zero, MCK_Imm }, }, |
4483 | | { 218 /* br */, VE::BRCFLir_t, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_SImm7, MCK_I64, MCK_Imm }, }, |
4484 | | { 218 /* br */, VE::BRCFLiz_t, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_l_DOT_t, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4485 | | { 218 /* br */, VE::BRCFSrr, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_F32, MCK_F32, MCK_Imm }, }, |
4486 | | { 218 /* br */, VE::BRCFSrz, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_F32, MCK_Zero, MCK_Imm }, }, |
4487 | | { 218 /* br */, VE::BRCFSir, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_SImm7, MCK_F32, MCK_Imm }, }, |
4488 | | { 218 /* br */, VE::BRCFSiz, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4489 | | { 218 /* br */, VE::BRCFSrr_nt, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_F32, MCK_F32, MCK_Imm }, }, |
4490 | | { 218 /* br */, VE::BRCFSrz_nt, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_F32, MCK_Zero, MCK_Imm }, }, |
4491 | | { 218 /* br */, VE::BRCFSir_nt, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_SImm7, MCK_F32, MCK_Imm }, }, |
4492 | | { 218 /* br */, VE::BRCFSiz_nt, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_nt, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4493 | | { 218 /* br */, VE::BRCFSrr_t, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_F32, MCK_F32, MCK_Imm }, }, |
4494 | | { 218 /* br */, VE::BRCFSrz_t, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_F32, MCK_Zero, MCK_Imm }, }, |
4495 | | { 218 /* br */, VE::BRCFSir_t, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_SImm7, MCK_F32, MCK_Imm }, }, |
4496 | | { 218 /* br */, VE::BRCFSiz_t, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_s_DOT_t, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4497 | | { 218 /* br */, VE::BRCFWrr, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_I32, MCK_I32, MCK_Imm }, }, |
4498 | | { 218 /* br */, VE::BRCFWrz, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_I32, MCK_Zero, MCK_Imm }, }, |
4499 | | { 218 /* br */, VE::BRCFWir, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_SImm7, MCK_I32, MCK_Imm }, }, |
4500 | | { 218 /* br */, VE::BRCFWiz, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4501 | | { 218 /* br */, VE::BRCFWrr_nt, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_I32, MCK_I32, MCK_Imm }, }, |
4502 | | { 218 /* br */, VE::BRCFWrz_nt, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_I32, MCK_Zero, MCK_Imm }, }, |
4503 | | { 218 /* br */, VE::BRCFWir_nt, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_SImm7, MCK_I32, MCK_Imm }, }, |
4504 | | { 218 /* br */, VE::BRCFWiz_nt, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_nt, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4505 | | { 218 /* br */, VE::BRCFWrr_t, Convert__CCOp1_0__Reg1_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_I32, MCK_I32, MCK_Imm }, }, |
4506 | | { 218 /* br */, VE::BRCFWrz_t, Convert__CCOp1_0__Reg1_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_I32, MCK_Zero, MCK_Imm }, }, |
4507 | | { 218 /* br */, VE::BRCFWir_t, Convert__CCOp1_0__SImm71_2__Reg1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_SImm7, MCK_I32, MCK_Imm }, }, |
4508 | | { 218 /* br */, VE::BRCFWiz_t, Convert__CCOp1_0__SImm71_2__Zero1_3__Imm1_4, AMFBS_None, { MCK_CCOp, MCK__DOT_w_DOT_t, MCK_SImm7, MCK_Zero, MCK_Imm }, }, |
4509 | | { 221 /* br.d */, VE::BRCFDa, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4510 | | { 226 /* br.d.nt */, VE::BRCFDa_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4511 | | { 234 /* br.d.t */, VE::BRCFDa_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4512 | | { 241 /* br.l */, VE::BRCFLa, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4513 | | { 246 /* br.l.nt */, VE::BRCFLa_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4514 | | { 254 /* br.l.t */, VE::BRCFLa_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4515 | | { 261 /* br.s */, VE::BRCFSa, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4516 | | { 266 /* br.s.nt */, VE::BRCFSa_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4517 | | { 274 /* br.s.t */, VE::BRCFSa_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4518 | | { 281 /* br.w */, VE::BRCFWa, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4519 | | { 286 /* br.w.nt */, VE::BRCFWa_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4520 | | { 294 /* br.w.t */, VE::BRCFWa_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4521 | | { 301 /* braf.d */, VE::BRCFDna, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4522 | | { 308 /* braf.d.nt */, VE::BRCFDna_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4523 | | { 318 /* braf.d.t */, VE::BRCFDna_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4524 | | { 327 /* braf.l */, VE::BRCFLna, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4525 | | { 334 /* braf.l.nt */, VE::BRCFLna_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4526 | | { 344 /* braf.l.t */, VE::BRCFLna_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4527 | | { 353 /* braf.s */, VE::BRCFSna, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4528 | | { 360 /* braf.s.nt */, VE::BRCFSna_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4529 | | { 370 /* braf.s.t */, VE::BRCFSna_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4530 | | { 379 /* braf.w */, VE::BRCFWna, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4531 | | { 386 /* braf.w.nt */, VE::BRCFWna_nt, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4532 | | { 396 /* braf.w.t */, VE::BRCFWna_t, Convert__Imm1_0, AMFBS_None, { MCK_Imm }, }, |
4533 | | { 405 /* brv */, VE::BRVr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I64 }, }, |
4534 | | { 405 /* brv */, VE::BRVm, Convert__Reg1_0__MImm1_1, AMFBS_None, { MCK_I64, MCK_MImm }, }, |
4535 | | { 409 /* bsic */, VE::BSICrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I64, MCK_MEMrii }, }, |
4536 | | { 409 /* bsic */, VE::BSICrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I64, MCK_MEMrri }, }, |
4537 | | { 409 /* bsic */, VE::BSICzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I64, MCK_MEMzii }, }, |
4538 | | { 409 /* bsic */, VE::BSICzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I64, MCK_MEMzri }, }, |
4539 | | { 414 /* bswp */, VE::BSWPri, Convert__Reg1_0__Reg1_1__UImm11_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm1 }, }, |
4540 | | { 414 /* bswp */, VE::BSWPmi, Convert__Reg1_0__MImm1_1__UImm11_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm1 }, }, |
4541 | | { 419 /* cas.l */, VE::CASLrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_I64 }, }, |
4542 | | { 419 /* cas.l */, VE::CASLrii, Convert__Reg1_0__MEMri2_1__SImm71_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_SImm7 }, }, |
4543 | | { 419 /* cas.l */, VE::CASLzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_I64 }, }, |
4544 | | { 419 /* cas.l */, VE::CASLzii, Convert__Reg1_0__MEMzi2_1__SImm71_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_SImm7 }, }, |
4545 | | { 425 /* cas.w */, VE::CASWrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMri, MCK_I32 }, }, |
4546 | | { 425 /* cas.w */, VE::CASWrii, Convert__Reg1_0__MEMri2_1__SImm71_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMri, MCK_SImm7 }, }, |
4547 | | { 425 /* cas.w */, VE::CASWzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMzi, MCK_I32 }, }, |
4548 | | { 425 /* cas.w */, VE::CASWzii, Convert__Reg1_0__MEMzi2_1__SImm71_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMzi, MCK_SImm7 }, }, |
4549 | | { 431 /* cmov.d. */, VE::CMOVDrr, Convert__Reg1_1__CCOp1_0__Reg1_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_I64 }, }, |
4550 | | { 431 /* cmov.d. */, VE::CMOVDir, Convert__Reg1_1__CCOp1_0__SImm71_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_SImm7 }, }, |
4551 | | { 431 /* cmov.d. */, VE::CMOVDrm, Convert__Reg1_1__CCOp1_0__Reg1_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_I64 }, }, |
4552 | | { 431 /* cmov.d. */, VE::CMOVDim, Convert__Reg1_1__CCOp1_0__SImm71_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_SImm7 }, }, |
4553 | | { 439 /* cmov.l. */, VE::CMOVLrr, Convert__Reg1_1__CCOp1_0__Reg1_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_I64 }, }, |
4554 | | { 439 /* cmov.l. */, VE::CMOVLir, Convert__Reg1_1__CCOp1_0__SImm71_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_SImm7 }, }, |
4555 | | { 439 /* cmov.l. */, VE::CMOVLrm, Convert__Reg1_1__CCOp1_0__Reg1_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_I64 }, }, |
4556 | | { 439 /* cmov.l. */, VE::CMOVLim, Convert__Reg1_1__CCOp1_0__SImm71_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_SImm7 }, }, |
4557 | | { 447 /* cmov.s. */, VE::CMOVSrr, Convert__Reg1_1__CCOp1_0__Reg1_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_F32 }, }, |
4558 | | { 447 /* cmov.s. */, VE::CMOVSir, Convert__Reg1_1__CCOp1_0__SImm71_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_SImm7 }, }, |
4559 | | { 447 /* cmov.s. */, VE::CMOVSrm, Convert__Reg1_1__CCOp1_0__Reg1_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_F32 }, }, |
4560 | | { 447 /* cmov.s. */, VE::CMOVSim, Convert__Reg1_1__CCOp1_0__SImm71_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_SImm7 }, }, |
4561 | | { 455 /* cmov.w. */, VE::CMOVWrr, Convert__Reg1_1__CCOp1_0__Reg1_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_I32 }, }, |
4562 | | { 455 /* cmov.w. */, VE::CMOVWir, Convert__Reg1_1__CCOp1_0__SImm71_3__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_I64, MCK_SImm7 }, }, |
4563 | | { 455 /* cmov.w. */, VE::CMOVWrm, Convert__Reg1_1__CCOp1_0__Reg1_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_I32 }, }, |
4564 | | { 455 /* cmov.w. */, VE::CMOVWim, Convert__Reg1_1__CCOp1_0__SImm71_3__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_CCOp, MCK_I64, MCK_MImm, MCK_SImm7 }, }, |
4565 | | { 463 /* cmps.l */, VE::CMPSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4566 | | { 463 /* cmps.l */, VE::CMPSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4567 | | { 463 /* cmps.l */, VE::CMPSLir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4568 | | { 463 /* cmps.l */, VE::CMPSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4569 | | { 470 /* cmps.w.sx */, VE::CMPSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4570 | | { 470 /* cmps.w.sx */, VE::CMPSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4571 | | { 470 /* cmps.w.sx */, VE::CMPSWSXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4572 | | { 470 /* cmps.w.sx */, VE::CMPSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4573 | | { 480 /* cmps.w.zx */, VE::CMPSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4574 | | { 480 /* cmps.w.zx */, VE::CMPSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4575 | | { 480 /* cmps.w.zx */, VE::CMPSWZXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4576 | | { 480 /* cmps.w.zx */, VE::CMPSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4577 | | { 490 /* cmpu.l */, VE::CMPULrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4578 | | { 490 /* cmpu.l */, VE::CMPULrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4579 | | { 490 /* cmpu.l */, VE::CMPULir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4580 | | { 490 /* cmpu.l */, VE::CMPULim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4581 | | { 497 /* cmpu.w */, VE::CMPUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4582 | | { 497 /* cmpu.w */, VE::CMPUWrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4583 | | { 497 /* cmpu.w */, VE::CMPUWir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4584 | | { 497 /* cmpu.w */, VE::CMPUWim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4585 | | { 504 /* cvt.d.l */, VE::CVTDLr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I64 }, }, |
4586 | | { 504 /* cvt.d.l */, VE::CVTDLi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7 }, }, |
4587 | | { 512 /* cvt.d.q */, VE::CVTDQr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_F128 }, }, |
4588 | | { 512 /* cvt.d.q */, VE::CVTDQi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7 }, }, |
4589 | | { 520 /* cvt.d.s */, VE::CVTDSr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_F32 }, }, |
4590 | | { 520 /* cvt.d.s */, VE::CVTDSi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7 }, }, |
4591 | | { 528 /* cvt.d.w */, VE::CVTDWr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I32 }, }, |
4592 | | { 528 /* cvt.d.w */, VE::CVTDWi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7 }, }, |
4593 | | { 536 /* cvt.l.d */, VE::CVTLDr, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_I64, MCK_I64 }, }, |
4594 | | { 536 /* cvt.l.d */, VE::CVTLDi, Convert__Reg1_1__RDOp1_0__SImm71_2, AMFBS_None, { MCK_RDOp, MCK_I64, MCK_SImm7 }, }, |
4595 | | { 544 /* cvt.q.d */, VE::CVTQDr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_F128, MCK_I64 }, }, |
4596 | | { 544 /* cvt.q.d */, VE::CVTQDi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_F128, MCK_SImm7 }, }, |
4597 | | { 552 /* cvt.q.s */, VE::CVTQSr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_F128, MCK_F32 }, }, |
4598 | | { 552 /* cvt.q.s */, VE::CVTQSi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_F128, MCK_SImm7 }, }, |
4599 | | { 560 /* cvt.s.d */, VE::CVTSDr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_F32, MCK_I64 }, }, |
4600 | | { 560 /* cvt.s.d */, VE::CVTSDi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_F32, MCK_SImm7 }, }, |
4601 | | { 568 /* cvt.s.q */, VE::CVTSQr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_F32, MCK_F128 }, }, |
4602 | | { 568 /* cvt.s.q */, VE::CVTSQi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_F32, MCK_SImm7 }, }, |
4603 | | { 576 /* cvt.s.w */, VE::CVTSWr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_F32, MCK_I32 }, }, |
4604 | | { 576 /* cvt.s.w */, VE::CVTSWi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_F32, MCK_SImm7 }, }, |
4605 | | { 584 /* cvt.w.d.sx */, VE::CVTWDSXr, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_I64 }, }, |
4606 | | { 584 /* cvt.w.d.sx */, VE::CVTWDSXi, Convert__Reg1_1__RDOp1_0__SImm71_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_SImm7 }, }, |
4607 | | { 595 /* cvt.w.d.zx */, VE::CVTWDZXr, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_I64 }, }, |
4608 | | { 595 /* cvt.w.d.zx */, VE::CVTWDZXi, Convert__Reg1_1__RDOp1_0__SImm71_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_SImm7 }, }, |
4609 | | { 606 /* cvt.w.s.sx */, VE::CVTWSSXr, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_F32 }, }, |
4610 | | { 606 /* cvt.w.s.sx */, VE::CVTWSSXi, Convert__Reg1_1__RDOp1_0__SImm71_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_SImm7 }, }, |
4611 | | { 617 /* cvt.w.s.zx */, VE::CVTWSZXr, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_F32 }, }, |
4612 | | { 617 /* cvt.w.s.zx */, VE::CVTWSZXi, Convert__Reg1_1__RDOp1_0__SImm71_2, AMFBS_None, { MCK_RDOp, MCK_I32, MCK_SImm7 }, }, |
4613 | | { 628 /* divs.l */, VE::DIVSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4614 | | { 628 /* divs.l */, VE::DIVSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4615 | | { 628 /* divs.l */, VE::DIVSLir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4616 | | { 628 /* divs.l */, VE::DIVSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4617 | | { 635 /* divs.w.sx */, VE::DIVSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4618 | | { 635 /* divs.w.sx */, VE::DIVSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4619 | | { 635 /* divs.w.sx */, VE::DIVSWSXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4620 | | { 635 /* divs.w.sx */, VE::DIVSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4621 | | { 645 /* divs.w.zx */, VE::DIVSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4622 | | { 645 /* divs.w.zx */, VE::DIVSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4623 | | { 645 /* divs.w.zx */, VE::DIVSWZXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4624 | | { 645 /* divs.w.zx */, VE::DIVSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4625 | | { 655 /* divu.l */, VE::DIVULrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4626 | | { 655 /* divu.l */, VE::DIVULrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4627 | | { 655 /* divu.l */, VE::DIVULir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4628 | | { 655 /* divu.l */, VE::DIVULim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4629 | | { 662 /* divu.w */, VE::DIVUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4630 | | { 662 /* divu.w */, VE::DIVUWrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4631 | | { 662 /* divu.w */, VE::DIVUWir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4632 | | { 662 /* divu.w */, VE::DIVUWim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4633 | | { 669 /* dld */, VE::DLDrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I64, MCK_MEMrii }, }, |
4634 | | { 669 /* dld */, VE::DLDrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I64, MCK_MEMrri }, }, |
4635 | | { 669 /* dld */, VE::DLDzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I64, MCK_MEMzii }, }, |
4636 | | { 669 /* dld */, VE::DLDzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I64, MCK_MEMzri }, }, |
4637 | | { 673 /* dldl.sx */, VE::DLDLSXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4638 | | { 673 /* dldl.sx */, VE::DLDLSXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4639 | | { 673 /* dldl.sx */, VE::DLDLSXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4640 | | { 673 /* dldl.sx */, VE::DLDLSXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4641 | | { 681 /* dldl.zx */, VE::DLDLZXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4642 | | { 681 /* dldl.zx */, VE::DLDLZXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4643 | | { 681 /* dldl.zx */, VE::DLDLZXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4644 | | { 681 /* dldl.zx */, VE::DLDLZXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4645 | | { 689 /* dldu */, VE::DLDUrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_F32, MCK_MEMrii }, }, |
4646 | | { 689 /* dldu */, VE::DLDUrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_F32, MCK_MEMrri }, }, |
4647 | | { 689 /* dldu */, VE::DLDUzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_F32, MCK_MEMzii }, }, |
4648 | | { 689 /* dldu */, VE::DLDUzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_F32, MCK_MEMzri }, }, |
4649 | | { 694 /* eqv */, VE::EQVrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4650 | | { 694 /* eqv */, VE::EQVrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4651 | | { 694 /* eqv */, VE::EQVri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4652 | | { 694 /* eqv */, VE::EQVim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4653 | | { 698 /* eqvm */, VE::EQVMmm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_VM, MCK_VM }, }, |
4654 | | { 703 /* fadd.d */, VE::FADDDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4655 | | { 703 /* fadd.d */, VE::FADDDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4656 | | { 703 /* fadd.d */, VE::FADDDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4657 | | { 703 /* fadd.d */, VE::FADDDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4658 | | { 710 /* fadd.q */, VE::FADDQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F128, MCK_F128, MCK_F128 }, }, |
4659 | | { 710 /* fadd.q */, VE::FADDQrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F128, MCK_F128, MCK_MImm }, }, |
4660 | | { 710 /* fadd.q */, VE::FADDQir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F128, MCK_SImm7, MCK_F128 }, }, |
4661 | | { 710 /* fadd.q */, VE::FADDQim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F128, MCK_SImm7, MCK_MImm }, }, |
4662 | | { 717 /* fadd.s */, VE::FADDSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4663 | | { 717 /* fadd.s */, VE::FADDSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4664 | | { 717 /* fadd.s */, VE::FADDSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4665 | | { 717 /* fadd.s */, VE::FADDSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4666 | | { 724 /* fcmp.d */, VE::FCMPDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4667 | | { 724 /* fcmp.d */, VE::FCMPDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4668 | | { 724 /* fcmp.d */, VE::FCMPDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4669 | | { 724 /* fcmp.d */, VE::FCMPDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4670 | | { 731 /* fcmp.q */, VE::FCMPQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_F128, MCK_F128 }, }, |
4671 | | { 731 /* fcmp.q */, VE::FCMPQrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_F128, MCK_MImm }, }, |
4672 | | { 731 /* fcmp.q */, VE::FCMPQir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_F128 }, }, |
4673 | | { 731 /* fcmp.q */, VE::FCMPQim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4674 | | { 738 /* fcmp.s */, VE::FCMPSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4675 | | { 738 /* fcmp.s */, VE::FCMPSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4676 | | { 738 /* fcmp.s */, VE::FCMPSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4677 | | { 738 /* fcmp.s */, VE::FCMPSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4678 | | { 745 /* fdiv.d */, VE::FDIVDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4679 | | { 745 /* fdiv.d */, VE::FDIVDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4680 | | { 745 /* fdiv.d */, VE::FDIVDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4681 | | { 745 /* fdiv.d */, VE::FDIVDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4682 | | { 752 /* fdiv.s */, VE::FDIVSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4683 | | { 752 /* fdiv.s */, VE::FDIVSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4684 | | { 752 /* fdiv.s */, VE::FDIVSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4685 | | { 752 /* fdiv.s */, VE::FDIVSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4686 | | { 759 /* fencec */, VE::FENCEC, Convert__UImm31_0, AMFBS_None, { MCK_UImm3 }, }, |
4687 | | { 766 /* fencei */, VE::FENCEI, Convert_NoOperands, AMFBS_None, { }, }, |
4688 | | { 773 /* fencem */, VE::FENCEM, Convert__UImm21_0, AMFBS_None, { MCK_UImm2 }, }, |
4689 | | { 780 /* fidcr */, VE::FIDCRri, Convert__Reg1_0__Reg1_1__UImm31_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm3 }, }, |
4690 | | { 780 /* fidcr */, VE::FIDCRii, Convert__Reg1_0__SImm71_1__UImm31_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_UImm3 }, }, |
4691 | | { 786 /* fmax.d */, VE::FMAXDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4692 | | { 786 /* fmax.d */, VE::FMAXDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4693 | | { 786 /* fmax.d */, VE::FMAXDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4694 | | { 786 /* fmax.d */, VE::FMAXDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4695 | | { 793 /* fmax.s */, VE::FMAXSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4696 | | { 793 /* fmax.s */, VE::FMAXSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4697 | | { 793 /* fmax.s */, VE::FMAXSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4698 | | { 793 /* fmax.s */, VE::FMAXSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4699 | | { 800 /* fmin.d */, VE::FMINDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4700 | | { 800 /* fmin.d */, VE::FMINDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4701 | | { 800 /* fmin.d */, VE::FMINDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4702 | | { 800 /* fmin.d */, VE::FMINDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4703 | | { 807 /* fmin.s */, VE::FMINSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4704 | | { 807 /* fmin.s */, VE::FMINSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4705 | | { 807 /* fmin.s */, VE::FMINSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4706 | | { 807 /* fmin.s */, VE::FMINSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4707 | | { 814 /* fmul.d */, VE::FMULDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4708 | | { 814 /* fmul.d */, VE::FMULDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4709 | | { 814 /* fmul.d */, VE::FMULDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4710 | | { 814 /* fmul.d */, VE::FMULDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4711 | | { 821 /* fmul.q */, VE::FMULQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F128, MCK_F128, MCK_F128 }, }, |
4712 | | { 821 /* fmul.q */, VE::FMULQrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F128, MCK_F128, MCK_MImm }, }, |
4713 | | { 821 /* fmul.q */, VE::FMULQir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F128, MCK_SImm7, MCK_F128 }, }, |
4714 | | { 821 /* fmul.q */, VE::FMULQim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F128, MCK_SImm7, MCK_MImm }, }, |
4715 | | { 828 /* fmul.s */, VE::FMULSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4716 | | { 828 /* fmul.s */, VE::FMULSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4717 | | { 828 /* fmul.s */, VE::FMULSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4718 | | { 828 /* fmul.s */, VE::FMULSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4719 | | { 835 /* fsub.d */, VE::FSUBDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4720 | | { 835 /* fsub.d */, VE::FSUBDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4721 | | { 835 /* fsub.d */, VE::FSUBDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4722 | | { 835 /* fsub.d */, VE::FSUBDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4723 | | { 842 /* fsub.q */, VE::FSUBQrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F128, MCK_F128, MCK_F128 }, }, |
4724 | | { 842 /* fsub.q */, VE::FSUBQrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F128, MCK_F128, MCK_MImm }, }, |
4725 | | { 842 /* fsub.q */, VE::FSUBQir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F128, MCK_SImm7, MCK_F128 }, }, |
4726 | | { 842 /* fsub.q */, VE::FSUBQim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F128, MCK_SImm7, MCK_MImm }, }, |
4727 | | { 849 /* fsub.s */, VE::FSUBSrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_F32 }, }, |
4728 | | { 849 /* fsub.s */, VE::FSUBSrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_F32, MCK_MImm }, }, |
4729 | | { 849 /* fsub.s */, VE::FSUBSir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_F32 }, }, |
4730 | | { 849 /* fsub.s */, VE::FSUBSim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_F32, MCK_SImm7, MCK_MImm }, }, |
4731 | | { 856 /* lcr */, VE::LCRrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4732 | | { 856 /* lcr */, VE::LCRrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_Zero }, }, |
4733 | | { 856 /* lcr */, VE::LCRir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4734 | | { 856 /* lcr */, VE::LCRiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_Zero }, }, |
4735 | | { 860 /* ld */, VE::LDrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I64, MCK_MEMrii }, }, |
4736 | | { 860 /* ld */, VE::LDrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I64, MCK_MEMrri }, }, |
4737 | | { 860 /* ld */, VE::LDzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I64, MCK_MEMzii }, }, |
4738 | | { 860 /* ld */, VE::LDzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I64, MCK_MEMzri }, }, |
4739 | | { 863 /* ld1b.sx */, VE::LD1BSXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4740 | | { 863 /* ld1b.sx */, VE::LD1BSXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4741 | | { 863 /* ld1b.sx */, VE::LD1BSXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4742 | | { 863 /* ld1b.sx */, VE::LD1BSXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4743 | | { 871 /* ld1b.zx */, VE::LD1BZXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4744 | | { 871 /* ld1b.zx */, VE::LD1BZXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4745 | | { 871 /* ld1b.zx */, VE::LD1BZXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4746 | | { 871 /* ld1b.zx */, VE::LD1BZXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4747 | | { 879 /* ld2b.sx */, VE::LD2BSXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4748 | | { 879 /* ld2b.sx */, VE::LD2BSXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4749 | | { 879 /* ld2b.sx */, VE::LD2BSXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4750 | | { 879 /* ld2b.sx */, VE::LD2BSXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4751 | | { 887 /* ld2b.zx */, VE::LD2BZXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4752 | | { 887 /* ld2b.zx */, VE::LD2BZXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4753 | | { 887 /* ld2b.zx */, VE::LD2BZXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4754 | | { 887 /* ld2b.zx */, VE::LD2BZXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4755 | | { 895 /* ldl.sx */, VE::LDLSXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4756 | | { 895 /* ldl.sx */, VE::LDLSXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4757 | | { 895 /* ldl.sx */, VE::LDLSXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4758 | | { 895 /* ldl.sx */, VE::LDLSXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4759 | | { 902 /* ldl.zx */, VE::LDLZXrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
4760 | | { 902 /* ldl.zx */, VE::LDLZXrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
4761 | | { 902 /* ldl.zx */, VE::LDLZXzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
4762 | | { 902 /* ldl.zx */, VE::LDLZXzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
4763 | | { 909 /* ldu */, VE::LDUrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_F32, MCK_MEMrii }, }, |
4764 | | { 909 /* ldu */, VE::LDUrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_F32, MCK_MEMrri }, }, |
4765 | | { 909 /* ldu */, VE::LDUzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_F32, MCK_MEMzii }, }, |
4766 | | { 909 /* ldu */, VE::LDUzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_F32, MCK_MEMzri }, }, |
4767 | | { 913 /* ldz */, VE::LDZr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I64 }, }, |
4768 | | { 913 /* ldz */, VE::LDZm, Convert__Reg1_0__MImm1_1, AMFBS_None, { MCK_I64, MCK_MImm }, }, |
4769 | | { 917 /* lea */, VE::LEArii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I64, MCK_MEMrii }, }, |
4770 | | { 917 /* lea */, VE::LEArri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I64, MCK_MEMrri }, }, |
4771 | | { 917 /* lea */, VE::LEAzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I64, MCK_MEMzii }, }, |
4772 | | { 917 /* lea */, VE::LEAzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I64, MCK_MEMzri }, }, |
4773 | | { 921 /* lea.sl */, VE::LEASLrii, Convert__Reg1_0__MEMrii3_1, AMFBS_None, { MCK_I64, MCK_MEMrii }, }, |
4774 | | { 921 /* lea.sl */, VE::LEASLrri, Convert__Reg1_0__MEMrri3_1, AMFBS_None, { MCK_I64, MCK_MEMrri }, }, |
4775 | | { 921 /* lea.sl */, VE::LEASLzii, Convert__Reg1_0__MEMzii3_1, AMFBS_None, { MCK_I64, MCK_MEMzii }, }, |
4776 | | { 921 /* lea.sl */, VE::LEASLzri, Convert__Reg1_0__MEMzri3_1, AMFBS_None, { MCK_I64, MCK_MEMzri }, }, |
4777 | | { 928 /* lfr */, VE::LFRr, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
4778 | | { 928 /* lfr */, VE::LFRi, Convert__UImm61_0, AMFBS_None, { MCK_UImm6 }, }, |
4779 | | { 932 /* lhm.b */, VE::LHMBri, Convert__Reg1_0__MEMri2_1, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
4780 | | { 932 /* lhm.b */, VE::LHMBzi, Convert__Reg1_0__MEMzi2_1, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
4781 | | { 938 /* lhm.h */, VE::LHMHri, Convert__Reg1_0__MEMri2_1, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
4782 | | { 938 /* lhm.h */, VE::LHMHzi, Convert__Reg1_0__MEMzi2_1, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
4783 | | { 944 /* lhm.l */, VE::LHMLri, Convert__Reg1_0__MEMri2_1, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
4784 | | { 944 /* lhm.l */, VE::LHMLzi, Convert__Reg1_0__MEMzi2_1, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
4785 | | { 950 /* lhm.w */, VE::LHMWri, Convert__Reg1_0__MEMri2_1, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
4786 | | { 950 /* lhm.w */, VE::LHMWzi, Convert__Reg1_0__MEMzi2_1, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
4787 | | { 956 /* lpm */, VE::LPM, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
4788 | | { 960 /* lsv */, VE::LSVrr, Convert__Reg1_0__Reg1_2__Reg1_4, AMFBS_None, { MCK_V64, MCK__40_, MCK_I64, MCK__41_, MCK_I64 }, }, |
4789 | | { 960 /* lsv */, VE::LSVrm, Convert__Reg1_0__Reg1_2__MImm1_4, AMFBS_None, { MCK_V64, MCK__40_, MCK_I64, MCK__41_, MCK_MImm }, }, |
4790 | | { 960 /* lsv */, VE::LSVir, Convert__Reg1_0__UImm71_2__Reg1_4, AMFBS_None, { MCK_V64, MCK__40_, MCK_UImm7, MCK__41_, MCK_I64 }, }, |
4791 | | { 960 /* lsv */, VE::LSVim, Convert__Reg1_0__UImm71_2__MImm1_4, AMFBS_None, { MCK_V64, MCK__40_, MCK_UImm7, MCK__41_, MCK_MImm }, }, |
4792 | | { 964 /* lvix */, VE::LVIXr, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
4793 | | { 964 /* lvix */, VE::LVIXi, Convert__UImm61_0, AMFBS_None, { MCK_UImm6 }, }, |
4794 | | { 969 /* lvl */, VE::LVLr, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
4795 | | { 969 /* lvl */, VE::LVLi, Convert__SImm71_0, AMFBS_None, { MCK_SImm7 }, }, |
4796 | | { 973 /* lvm */, VE::LVMrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_I64, MCK_I64 }, }, |
4797 | | { 973 /* lvm */, VE::LVMrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_VM, MCK_I64, MCK_MImm }, }, |
4798 | | { 973 /* lvm */, VE::LVMir, Convert__Reg1_0__UImm21_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_UImm2, MCK_I64 }, }, |
4799 | | { 973 /* lvm */, VE::LVMim, Convert__Reg1_0__UImm21_1__MImm1_2, AMFBS_None, { MCK_VM, MCK_UImm2, MCK_MImm }, }, |
4800 | | { 977 /* lvs */, VE::LVSvr, Convert__Reg1_0__Reg1_1__Reg1_3, AMFBS_None, { MCK_I64, MCK_V64, MCK__40_, MCK_I64, MCK__41_ }, }, |
4801 | | { 977 /* lvs */, VE::LVSvi, Convert__Reg1_0__Reg1_1__UImm71_3, AMFBS_None, { MCK_I64, MCK_V64, MCK__40_, MCK_UImm7, MCK__41_ }, }, |
4802 | | { 981 /* lzvm */, VE::LZVMm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_VM }, }, |
4803 | | { 986 /* maxs.l */, VE::MAXSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4804 | | { 986 /* maxs.l */, VE::MAXSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4805 | | { 986 /* maxs.l */, VE::MAXSLri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4806 | | { 986 /* maxs.l */, VE::MAXSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4807 | | { 993 /* maxs.w.sx */, VE::MAXSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4808 | | { 993 /* maxs.w.sx */, VE::MAXSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4809 | | { 993 /* maxs.w.sx */, VE::MAXSWSXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4810 | | { 993 /* maxs.w.sx */, VE::MAXSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4811 | | { 1003 /* maxs.w.zx */, VE::MAXSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4812 | | { 1003 /* maxs.w.zx */, VE::MAXSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4813 | | { 1003 /* maxs.w.zx */, VE::MAXSWZXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4814 | | { 1003 /* maxs.w.zx */, VE::MAXSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4815 | | { 1013 /* mins.l */, VE::MINSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4816 | | { 1013 /* mins.l */, VE::MINSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4817 | | { 1013 /* mins.l */, VE::MINSLri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4818 | | { 1013 /* mins.l */, VE::MINSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4819 | | { 1020 /* mins.w.sx */, VE::MINSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4820 | | { 1020 /* mins.w.sx */, VE::MINSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4821 | | { 1020 /* mins.w.sx */, VE::MINSWSXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4822 | | { 1020 /* mins.w.sx */, VE::MINSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4823 | | { 1030 /* mins.w.zx */, VE::MINSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4824 | | { 1030 /* mins.w.zx */, VE::MINSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4825 | | { 1030 /* mins.w.zx */, VE::MINSWZXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4826 | | { 1030 /* mins.w.zx */, VE::MINSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4827 | | { 1040 /* monc */, VE::MONC, Convert_NoOperands, AMFBS_None, { }, }, |
4828 | | { 1045 /* monc.hdb */, VE::MONCHDB, Convert_NoOperands, AMFBS_None, { }, }, |
4829 | | { 1054 /* mrg */, VE::MRGrr, Convert__Reg1_0__Reg1_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4830 | | { 1054 /* mrg */, VE::MRGrm, Convert__Reg1_0__Reg1_1__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4831 | | { 1054 /* mrg */, VE::MRGir, Convert__Reg1_0__SImm71_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4832 | | { 1054 /* mrg */, VE::MRGim, Convert__Reg1_0__SImm71_1__MImm1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4833 | | { 1058 /* muls.l */, VE::MULSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4834 | | { 1058 /* muls.l */, VE::MULSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4835 | | { 1058 /* muls.l */, VE::MULSLri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4836 | | { 1058 /* muls.l */, VE::MULSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4837 | | { 1065 /* muls.l.w */, VE::MULSLWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I32, MCK_I32 }, }, |
4838 | | { 1065 /* muls.l.w */, VE::MULSLWrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I32, MCK_MImm }, }, |
4839 | | { 1065 /* muls.l.w */, VE::MULSLWri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I32 }, }, |
4840 | | { 1065 /* muls.l.w */, VE::MULSLWim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4841 | | { 1074 /* muls.w.sx */, VE::MULSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4842 | | { 1074 /* muls.w.sx */, VE::MULSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4843 | | { 1074 /* muls.w.sx */, VE::MULSWSXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4844 | | { 1074 /* muls.w.sx */, VE::MULSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4845 | | { 1084 /* muls.w.zx */, VE::MULSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4846 | | { 1084 /* muls.w.zx */, VE::MULSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4847 | | { 1084 /* muls.w.zx */, VE::MULSWZXri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4848 | | { 1084 /* muls.w.zx */, VE::MULSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4849 | | { 1094 /* mulu.l */, VE::MULULrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4850 | | { 1094 /* mulu.l */, VE::MULULrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4851 | | { 1094 /* mulu.l */, VE::MULULri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4852 | | { 1094 /* mulu.l */, VE::MULULim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4853 | | { 1101 /* mulu.w */, VE::MULUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
4854 | | { 1101 /* mulu.w */, VE::MULUWrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
4855 | | { 1101 /* mulu.w */, VE::MULUWri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
4856 | | { 1101 /* mulu.w */, VE::MULUWim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
4857 | | { 1108 /* negm */, VE::NEGMm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
4858 | | { 1113 /* nnd */, VE::NNDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4859 | | { 1113 /* nnd */, VE::NNDrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4860 | | { 1113 /* nnd */, VE::NNDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4861 | | { 1113 /* nnd */, VE::NNDim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4862 | | { 1117 /* nndm */, VE::NNDMmm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_VM, MCK_VM }, }, |
4863 | | { 1122 /* nop */, VE::NOP, Convert_NoOperands, AMFBS_None, { }, }, |
4864 | | { 1126 /* or */, VE::ORrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
4865 | | { 1126 /* or */, VE::ORrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
4866 | | { 1126 /* or */, VE::ORri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
4867 | | { 1126 /* or */, VE::ORim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
4868 | | { 1129 /* orm */, VE::ORMmm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_VM, MCK_VM }, }, |
4869 | | { 1133 /* pcnt */, VE::PCNTr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I64 }, }, |
4870 | | { 1133 /* pcnt */, VE::PCNTm, Convert__Reg1_0__MImm1_1, AMFBS_None, { MCK_I64, MCK_MImm }, }, |
4871 | | { 1138 /* pcvm */, VE::PCVMm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_VM }, }, |
4872 | | { 1143 /* pfch */, VE::PFCHrii, Convert__MEMrii3_0, AMFBS_None, { MCK_MEMrii }, }, |
4873 | | { 1143 /* pfch */, VE::PFCHrri, Convert__MEMrri3_0, AMFBS_None, { MCK_MEMrri }, }, |
4874 | | { 1143 /* pfch */, VE::PFCHzii, Convert__MEMzii3_0, AMFBS_None, { MCK_MEMzii }, }, |
4875 | | { 1143 /* pfch */, VE::PFCHzri, Convert__MEMzri3_0, AMFBS_None, { MCK_MEMzri }, }, |
4876 | | { 1148 /* pfchv */, VE::PFCHVrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I64 }, }, |
4877 | | { 1148 /* pfchv */, VE::PFCHVrz, Convert__Reg1_0__Zero1_1, AMFBS_None, { MCK_I64, MCK_Zero }, }, |
4878 | | { 1148 /* pfchv */, VE::PFCHVir, Convert__SImm71_0__Reg1_1, AMFBS_None, { MCK_SImm7, MCK_I64 }, }, |
4879 | | { 1148 /* pfchv */, VE::PFCHViz, Convert__SImm71_0__Zero1_1, AMFBS_None, { MCK_SImm7, MCK_Zero }, }, |
4880 | | { 1154 /* pfchv.nc */, VE::PFCHVNCrr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_I64 }, }, |
4881 | | { 1154 /* pfchv.nc */, VE::PFCHVNCrz, Convert__Reg1_0__Zero1_1, AMFBS_None, { MCK_I64, MCK_Zero }, }, |
4882 | | { 1154 /* pfchv.nc */, VE::PFCHVNCir, Convert__SImm71_0__Reg1_1, AMFBS_None, { MCK_SImm7, MCK_I64 }, }, |
4883 | | { 1154 /* pfchv.nc */, VE::PFCHVNCiz, Convert__SImm71_0__Zero1_1, AMFBS_None, { MCK_SImm7, MCK_Zero }, }, |
4884 | | { 1163 /* pvadds */, VE::PVADDSrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4885 | | { 1163 /* pvadds */, VE::PVADDSvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4886 | | { 1163 /* pvadds */, VE::PVADDSiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4887 | | { 1163 /* pvadds */, VE::PVADDSrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
4888 | | { 1163 /* pvadds */, VE::PVADDSvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
4889 | | { 1163 /* pvadds */, VE::PVADDSivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
4890 | | { 1170 /* pvadds.lo */, VE::PVADDSLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
4891 | | { 1170 /* pvadds.lo */, VE::PVADDSLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4892 | | { 1170 /* pvadds.lo */, VE::PVADDSLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4893 | | { 1170 /* pvadds.lo */, VE::PVADDSLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
4894 | | { 1170 /* pvadds.lo */, VE::PVADDSLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4895 | | { 1170 /* pvadds.lo */, VE::PVADDSLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4896 | | { 1180 /* pvadds.up */, VE::PVADDSUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4897 | | { 1180 /* pvadds.up */, VE::PVADDSUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4898 | | { 1180 /* pvadds.up */, VE::PVADDSUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4899 | | { 1180 /* pvadds.up */, VE::PVADDSUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
4900 | | { 1180 /* pvadds.up */, VE::PVADDSUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4901 | | { 1180 /* pvadds.up */, VE::PVADDSUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4902 | | { 1190 /* pvaddu */, VE::PVADDUrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4903 | | { 1190 /* pvaddu */, VE::PVADDUvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4904 | | { 1190 /* pvaddu */, VE::PVADDUiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4905 | | { 1190 /* pvaddu */, VE::PVADDUrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
4906 | | { 1190 /* pvaddu */, VE::PVADDUvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
4907 | | { 1190 /* pvaddu */, VE::PVADDUivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
4908 | | { 1197 /* pvaddu.lo */, VE::PVADDULOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
4909 | | { 1197 /* pvaddu.lo */, VE::PVADDULOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4910 | | { 1197 /* pvaddu.lo */, VE::PVADDULOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4911 | | { 1197 /* pvaddu.lo */, VE::PVADDULOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
4912 | | { 1197 /* pvaddu.lo */, VE::PVADDULOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4913 | | { 1197 /* pvaddu.lo */, VE::PVADDULOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4914 | | { 1207 /* pvaddu.up */, VE::PVADDUUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4915 | | { 1207 /* pvaddu.up */, VE::PVADDUUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4916 | | { 1207 /* pvaddu.up */, VE::PVADDUUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4917 | | { 1207 /* pvaddu.up */, VE::PVADDUUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
4918 | | { 1207 /* pvaddu.up */, VE::PVADDUUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4919 | | { 1207 /* pvaddu.up */, VE::PVADDUUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4920 | | { 1217 /* pvand */, VE::PVANDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4921 | | { 1217 /* pvand */, VE::PVANDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4922 | | { 1217 /* pvand */, VE::PVANDmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
4923 | | { 1217 /* pvand */, VE::PVANDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
4924 | | { 1217 /* pvand */, VE::PVANDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
4925 | | { 1217 /* pvand */, VE::PVANDmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM512 }, }, |
4926 | | { 1223 /* pvand.lo */, VE::PVANDLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
4927 | | { 1223 /* pvand.lo */, VE::PVANDLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4928 | | { 1223 /* pvand.lo */, VE::PVANDLOmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
4929 | | { 1223 /* pvand.lo */, VE::PVANDLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
4930 | | { 1223 /* pvand.lo */, VE::PVANDLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4931 | | { 1223 /* pvand.lo */, VE::PVANDLOmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
4932 | | { 1232 /* pvand.up */, VE::PVANDUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
4933 | | { 1232 /* pvand.up */, VE::PVANDUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4934 | | { 1232 /* pvand.up */, VE::PVANDUPmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
4935 | | { 1232 /* pvand.up */, VE::PVANDUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
4936 | | { 1232 /* pvand.up */, VE::PVANDUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4937 | | { 1232 /* pvand.up */, VE::PVANDUPmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
4938 | | { 1241 /* pvbrd */, VE::PVBRDr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_I64 }, }, |
4939 | | { 1241 /* pvbrd */, VE::PVBRDi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_V64, MCK_SImm7 }, }, |
4940 | | { 1241 /* pvbrd */, VE::PVBRDrm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_VM512 }, }, |
4941 | | { 1241 /* pvbrd */, VE::PVBRDim, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_VM512 }, }, |
4942 | | { 1247 /* pvbrv */, VE::PVBRVv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
4943 | | { 1247 /* pvbrv */, VE::PVBRVvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
4944 | | { 1253 /* pvbrv.lo */, VE::PVBRVLOv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
4945 | | { 1253 /* pvbrv.lo */, VE::PVBRVLOvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
4946 | | { 1262 /* pvbrv.up */, VE::PVBRVUPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
4947 | | { 1262 /* pvbrv.up */, VE::PVBRVUPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
4948 | | { 1271 /* pvcmps */, VE::PVCMPSrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4949 | | { 1271 /* pvcmps */, VE::PVCMPSvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4950 | | { 1271 /* pvcmps */, VE::PVCMPSiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4951 | | { 1271 /* pvcmps */, VE::PVCMPSrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
4952 | | { 1271 /* pvcmps */, VE::PVCMPSvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
4953 | | { 1271 /* pvcmps */, VE::PVCMPSivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
4954 | | { 1278 /* pvcmps.lo */, VE::PVCMPSLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
4955 | | { 1278 /* pvcmps.lo */, VE::PVCMPSLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4956 | | { 1278 /* pvcmps.lo */, VE::PVCMPSLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4957 | | { 1278 /* pvcmps.lo */, VE::PVCMPSLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
4958 | | { 1278 /* pvcmps.lo */, VE::PVCMPSLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4959 | | { 1278 /* pvcmps.lo */, VE::PVCMPSLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4960 | | { 1288 /* pvcmps.up */, VE::PVCMPSUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4961 | | { 1288 /* pvcmps.up */, VE::PVCMPSUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4962 | | { 1288 /* pvcmps.up */, VE::PVCMPSUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4963 | | { 1288 /* pvcmps.up */, VE::PVCMPSUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
4964 | | { 1288 /* pvcmps.up */, VE::PVCMPSUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4965 | | { 1288 /* pvcmps.up */, VE::PVCMPSUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4966 | | { 1298 /* pvcmpu */, VE::PVCMPUrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4967 | | { 1298 /* pvcmpu */, VE::PVCMPUvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4968 | | { 1298 /* pvcmpu */, VE::PVCMPUiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4969 | | { 1298 /* pvcmpu */, VE::PVCMPUrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
4970 | | { 1298 /* pvcmpu */, VE::PVCMPUvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
4971 | | { 1298 /* pvcmpu */, VE::PVCMPUivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
4972 | | { 1305 /* pvcmpu.lo */, VE::PVCMPULOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
4973 | | { 1305 /* pvcmpu.lo */, VE::PVCMPULOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4974 | | { 1305 /* pvcmpu.lo */, VE::PVCMPULOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4975 | | { 1305 /* pvcmpu.lo */, VE::PVCMPULOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
4976 | | { 1305 /* pvcmpu.lo */, VE::PVCMPULOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4977 | | { 1305 /* pvcmpu.lo */, VE::PVCMPULOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4978 | | { 1315 /* pvcmpu.up */, VE::PVCMPUUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4979 | | { 1315 /* pvcmpu.up */, VE::PVCMPUUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4980 | | { 1315 /* pvcmpu.up */, VE::PVCMPUUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
4981 | | { 1315 /* pvcmpu.up */, VE::PVCMPUUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
4982 | | { 1315 /* pvcmpu.up */, VE::PVCMPUUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
4983 | | { 1315 /* pvcmpu.up */, VE::PVCMPUUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
4984 | | { 1325 /* pvcvt.s.w */, VE::PVCVTSWv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
4985 | | { 1325 /* pvcvt.s.w */, VE::PVCVTSWvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
4986 | | { 1335 /* pvcvt.s.w.lo */, VE::PVCVTSWLOv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
4987 | | { 1335 /* pvcvt.s.w.lo */, VE::PVCVTSWLOvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
4988 | | { 1348 /* pvcvt.s.w.up */, VE::PVCVTSWUPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
4989 | | { 1348 /* pvcvt.s.w.up */, VE::PVCVTSWUPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
4990 | | { 1361 /* pvcvt.w.s */, VE::PVCVTWSv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
4991 | | { 1361 /* pvcvt.w.s */, VE::PVCVTWSvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM512 }, }, |
4992 | | { 1371 /* pvcvt.w.s.lo */, VE::PVCVTWSLOv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
4993 | | { 1371 /* pvcvt.w.s.lo */, VE::PVCVTWSLOvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
4994 | | { 1384 /* pvcvt.w.s.up */, VE::PVCVTWSUPv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
4995 | | { 1384 /* pvcvt.w.s.up */, VE::PVCVTWSUPvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
4996 | | { 1397 /* pveqv */, VE::PVEQVrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
4997 | | { 1397 /* pveqv */, VE::PVEQVvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
4998 | | { 1397 /* pveqv */, VE::PVEQVmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
4999 | | { 1397 /* pveqv */, VE::PVEQVrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5000 | | { 1397 /* pveqv */, VE::PVEQVvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5001 | | { 1397 /* pveqv */, VE::PVEQVmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM512 }, }, |
5002 | | { 1403 /* pveqv.lo */, VE::PVEQVLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5003 | | { 1403 /* pveqv.lo */, VE::PVEQVLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5004 | | { 1403 /* pveqv.lo */, VE::PVEQVLOmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5005 | | { 1403 /* pveqv.lo */, VE::PVEQVLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5006 | | { 1403 /* pveqv.lo */, VE::PVEQVLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5007 | | { 1403 /* pveqv.lo */, VE::PVEQVLOmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5008 | | { 1412 /* pveqv.up */, VE::PVEQVUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5009 | | { 1412 /* pveqv.up */, VE::PVEQVUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5010 | | { 1412 /* pveqv.up */, VE::PVEQVUPmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5011 | | { 1412 /* pveqv.up */, VE::PVEQVUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5012 | | { 1412 /* pveqv.up */, VE::PVEQVUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5013 | | { 1412 /* pveqv.up */, VE::PVEQVUPmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5014 | | { 1421 /* pvfadd */, VE::PVFADDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5015 | | { 1421 /* pvfadd */, VE::PVFADDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5016 | | { 1421 /* pvfadd */, VE::PVFADDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5017 | | { 1421 /* pvfadd */, VE::PVFADDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5018 | | { 1421 /* pvfadd */, VE::PVFADDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5019 | | { 1421 /* pvfadd */, VE::PVFADDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5020 | | { 1428 /* pvfadd.lo */, VE::PVFADDLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5021 | | { 1428 /* pvfadd.lo */, VE::PVFADDLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5022 | | { 1428 /* pvfadd.lo */, VE::PVFADDLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5023 | | { 1428 /* pvfadd.lo */, VE::PVFADDLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5024 | | { 1428 /* pvfadd.lo */, VE::PVFADDLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5025 | | { 1428 /* pvfadd.lo */, VE::PVFADDLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5026 | | { 1438 /* pvfadd.up */, VE::PVFADDUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5027 | | { 1438 /* pvfadd.up */, VE::PVFADDUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5028 | | { 1438 /* pvfadd.up */, VE::PVFADDUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5029 | | { 1438 /* pvfadd.up */, VE::PVFADDUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5030 | | { 1438 /* pvfadd.up */, VE::PVFADDUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5031 | | { 1438 /* pvfadd.up */, VE::PVFADDUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5032 | | { 1448 /* pvfcmp */, VE::PVFCMPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5033 | | { 1448 /* pvfcmp */, VE::PVFCMPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5034 | | { 1448 /* pvfcmp */, VE::PVFCMPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5035 | | { 1448 /* pvfcmp */, VE::PVFCMPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5036 | | { 1448 /* pvfcmp */, VE::PVFCMPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5037 | | { 1448 /* pvfcmp */, VE::PVFCMPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5038 | | { 1455 /* pvfcmp.lo */, VE::PVFCMPLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5039 | | { 1455 /* pvfcmp.lo */, VE::PVFCMPLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5040 | | { 1455 /* pvfcmp.lo */, VE::PVFCMPLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5041 | | { 1455 /* pvfcmp.lo */, VE::PVFCMPLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5042 | | { 1455 /* pvfcmp.lo */, VE::PVFCMPLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5043 | | { 1455 /* pvfcmp.lo */, VE::PVFCMPLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5044 | | { 1465 /* pvfcmp.up */, VE::PVFCMPUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5045 | | { 1465 /* pvfcmp.up */, VE::PVFCMPUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5046 | | { 1465 /* pvfcmp.up */, VE::PVFCMPUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5047 | | { 1465 /* pvfcmp.up */, VE::PVFCMPUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5048 | | { 1465 /* pvfcmp.up */, VE::PVFCMPUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5049 | | { 1465 /* pvfcmp.up */, VE::PVFCMPUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5050 | | { 1475 /* pvfmad */, VE::PVFMADrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5051 | | { 1475 /* pvfmad */, VE::PVFMADvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5052 | | { 1475 /* pvfmad */, VE::PVFMADvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5053 | | { 1475 /* pvfmad */, VE::PVFMADviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5054 | | { 1475 /* pvfmad */, VE::PVFMADivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5055 | | { 1475 /* pvfmad */, VE::PVFMADrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5056 | | { 1475 /* pvfmad */, VE::PVFMADvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5057 | | { 1475 /* pvfmad */, VE::PVFMADvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5058 | | { 1475 /* pvfmad */, VE::PVFMADvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5059 | | { 1475 /* pvfmad */, VE::PVFMADivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5060 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5061 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5062 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5063 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5064 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5065 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5066 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5067 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5068 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5069 | | { 1482 /* pvfmad.lo */, VE::PVFMADLOivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5070 | | { 1492 /* pvfmad.up */, VE::PVFMADUPrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64 }, }, |
5071 | | { 1492 /* pvfmad.up */, VE::PVFMADUPvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64 }, }, |
5072 | | { 1492 /* pvfmad.up */, VE::PVFMADUPvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5073 | | { 1492 /* pvfmad.up */, VE::PVFMADUPviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5074 | | { 1492 /* pvfmad.up */, VE::PVFMADUPivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5075 | | { 1492 /* pvfmad.up */, VE::PVFMADUPrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64, MCK_VM }, }, |
5076 | | { 1492 /* pvfmad.up */, VE::PVFMADUPvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5077 | | { 1492 /* pvfmad.up */, VE::PVFMADUPvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5078 | | { 1492 /* pvfmad.up */, VE::PVFMADUPvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5079 | | { 1492 /* pvfmad.up */, VE::PVFMADUPivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5080 | | { 1502 /* pvfmax */, VE::PVFMAXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5081 | | { 1502 /* pvfmax */, VE::PVFMAXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5082 | | { 1502 /* pvfmax */, VE::PVFMAXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5083 | | { 1502 /* pvfmax */, VE::PVFMAXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5084 | | { 1502 /* pvfmax */, VE::PVFMAXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5085 | | { 1502 /* pvfmax */, VE::PVFMAXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5086 | | { 1509 /* pvfmax.lo */, VE::PVFMAXLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5087 | | { 1509 /* pvfmax.lo */, VE::PVFMAXLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5088 | | { 1509 /* pvfmax.lo */, VE::PVFMAXLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5089 | | { 1509 /* pvfmax.lo */, VE::PVFMAXLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5090 | | { 1509 /* pvfmax.lo */, VE::PVFMAXLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5091 | | { 1509 /* pvfmax.lo */, VE::PVFMAXLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5092 | | { 1519 /* pvfmax.up */, VE::PVFMAXUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5093 | | { 1519 /* pvfmax.up */, VE::PVFMAXUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5094 | | { 1519 /* pvfmax.up */, VE::PVFMAXUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5095 | | { 1519 /* pvfmax.up */, VE::PVFMAXUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5096 | | { 1519 /* pvfmax.up */, VE::PVFMAXUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5097 | | { 1519 /* pvfmax.up */, VE::PVFMAXUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5098 | | { 1529 /* pvfmin */, VE::PVFMINrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5099 | | { 1529 /* pvfmin */, VE::PVFMINvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5100 | | { 1529 /* pvfmin */, VE::PVFMINiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5101 | | { 1529 /* pvfmin */, VE::PVFMINrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5102 | | { 1529 /* pvfmin */, VE::PVFMINvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5103 | | { 1529 /* pvfmin */, VE::PVFMINivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5104 | | { 1536 /* pvfmin.lo */, VE::PVFMINLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5105 | | { 1536 /* pvfmin.lo */, VE::PVFMINLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5106 | | { 1536 /* pvfmin.lo */, VE::PVFMINLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5107 | | { 1536 /* pvfmin.lo */, VE::PVFMINLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5108 | | { 1536 /* pvfmin.lo */, VE::PVFMINLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5109 | | { 1536 /* pvfmin.lo */, VE::PVFMINLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5110 | | { 1546 /* pvfmin.up */, VE::PVFMINUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5111 | | { 1546 /* pvfmin.up */, VE::PVFMINUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5112 | | { 1546 /* pvfmin.up */, VE::PVFMINUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5113 | | { 1546 /* pvfmin.up */, VE::PVFMINUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5114 | | { 1546 /* pvfmin.up */, VE::PVFMINUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5115 | | { 1546 /* pvfmin.up */, VE::PVFMINUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5116 | | { 1556 /* pvfmk.s.lo. */, VE::PVFMKSLOv, Convert__Reg1_1__CCOp1_0__Reg1_2, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64 }, }, |
5117 | | { 1556 /* pvfmk.s.lo. */, VE::PVFMKSLOvm, Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64, MCK_VM }, }, |
5118 | | { 1568 /* pvfmk.s.lo.af */, VE::PVFMKSLOna, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5119 | | { 1568 /* pvfmk.s.lo.af */, VE::PVFMKSLOnam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5120 | | { 1582 /* pvfmk.s.lo.at */, VE::PVFMKSLOa, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5121 | | { 1582 /* pvfmk.s.lo.at */, VE::PVFMKSLOam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5122 | | { 1596 /* pvfmk.s.up. */, VE::PVFMKSUPv, Convert__Reg1_1__CCOp1_0__Reg1_2, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64 }, }, |
5123 | | { 1596 /* pvfmk.s.up. */, VE::PVFMKSUPvm, Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64, MCK_VM }, }, |
5124 | | { 1608 /* pvfmk.s.up.af */, VE::PVFMKSUPna, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5125 | | { 1608 /* pvfmk.s.up.af */, VE::PVFMKSUPnam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5126 | | { 1622 /* pvfmk.s.up.at */, VE::PVFMKSUPa, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5127 | | { 1622 /* pvfmk.s.up.at */, VE::PVFMKSUPam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5128 | | { 1636 /* pvfmk.w.up. */, VE::PVFMKWUPv, Convert__Reg1_1__CCOp1_0__Reg1_2, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64 }, }, |
5129 | | { 1636 /* pvfmk.w.up. */, VE::PVFMKWUPvm, Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64, MCK_VM }, }, |
5130 | | { 1648 /* pvfmk.w.up.af */, VE::PVFMKWUPna, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5131 | | { 1648 /* pvfmk.w.up.af */, VE::PVFMKWUPnam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5132 | | { 1662 /* pvfmk.w.up.at */, VE::PVFMKWUPa, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5133 | | { 1662 /* pvfmk.w.up.at */, VE::PVFMKWUPam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5134 | | { 1676 /* pvfmsb */, VE::PVFMSBrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5135 | | { 1676 /* pvfmsb */, VE::PVFMSBvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5136 | | { 1676 /* pvfmsb */, VE::PVFMSBvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5137 | | { 1676 /* pvfmsb */, VE::PVFMSBviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5138 | | { 1676 /* pvfmsb */, VE::PVFMSBivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5139 | | { 1676 /* pvfmsb */, VE::PVFMSBrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5140 | | { 1676 /* pvfmsb */, VE::PVFMSBvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5141 | | { 1676 /* pvfmsb */, VE::PVFMSBvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5142 | | { 1676 /* pvfmsb */, VE::PVFMSBvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5143 | | { 1676 /* pvfmsb */, VE::PVFMSBivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5144 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5145 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5146 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5147 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5148 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5149 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5150 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5151 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5152 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5153 | | { 1683 /* pvfmsb.lo */, VE::PVFMSBLOivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5154 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64 }, }, |
5155 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64 }, }, |
5156 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5157 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5158 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5159 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64, MCK_VM }, }, |
5160 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5161 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5162 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5163 | | { 1693 /* pvfmsb.up */, VE::PVFMSBUPivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5164 | | { 1703 /* pvfmul */, VE::PVFMULrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5165 | | { 1703 /* pvfmul */, VE::PVFMULvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5166 | | { 1703 /* pvfmul */, VE::PVFMULiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5167 | | { 1703 /* pvfmul */, VE::PVFMULrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5168 | | { 1703 /* pvfmul */, VE::PVFMULvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5169 | | { 1703 /* pvfmul */, VE::PVFMULivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5170 | | { 1710 /* pvfmul.lo */, VE::PVFMULLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5171 | | { 1710 /* pvfmul.lo */, VE::PVFMULLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5172 | | { 1710 /* pvfmul.lo */, VE::PVFMULLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5173 | | { 1710 /* pvfmul.lo */, VE::PVFMULLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5174 | | { 1710 /* pvfmul.lo */, VE::PVFMULLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5175 | | { 1710 /* pvfmul.lo */, VE::PVFMULLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5176 | | { 1720 /* pvfmul.up */, VE::PVFMULUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5177 | | { 1720 /* pvfmul.up */, VE::PVFMULUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5178 | | { 1720 /* pvfmul.up */, VE::PVFMULUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5179 | | { 1720 /* pvfmul.up */, VE::PVFMULUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5180 | | { 1720 /* pvfmul.up */, VE::PVFMULUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5181 | | { 1720 /* pvfmul.up */, VE::PVFMULUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5182 | | { 1730 /* pvfnmad */, VE::PVFNMADrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5183 | | { 1730 /* pvfnmad */, VE::PVFNMADvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5184 | | { 1730 /* pvfnmad */, VE::PVFNMADvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5185 | | { 1730 /* pvfnmad */, VE::PVFNMADviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5186 | | { 1730 /* pvfnmad */, VE::PVFNMADivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5187 | | { 1730 /* pvfnmad */, VE::PVFNMADrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5188 | | { 1730 /* pvfnmad */, VE::PVFNMADvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5189 | | { 1730 /* pvfnmad */, VE::PVFNMADvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5190 | | { 1730 /* pvfnmad */, VE::PVFNMADvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5191 | | { 1730 /* pvfnmad */, VE::PVFNMADivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5192 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5193 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5194 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5195 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5196 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5197 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5198 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5199 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5200 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5201 | | { 1738 /* pvfnmad.lo */, VE::PVFNMADLOivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5202 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64 }, }, |
5203 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64 }, }, |
5204 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5205 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5206 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5207 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64, MCK_VM }, }, |
5208 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5209 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5210 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5211 | | { 1749 /* pvfnmad.up */, VE::PVFNMADUPivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5212 | | { 1760 /* pvfnmsb */, VE::PVFNMSBrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5213 | | { 1760 /* pvfnmsb */, VE::PVFNMSBvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5214 | | { 1760 /* pvfnmsb */, VE::PVFNMSBvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5215 | | { 1760 /* pvfnmsb */, VE::PVFNMSBviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5216 | | { 1760 /* pvfnmsb */, VE::PVFNMSBivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5217 | | { 1760 /* pvfnmsb */, VE::PVFNMSBrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5218 | | { 1760 /* pvfnmsb */, VE::PVFNMSBvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5219 | | { 1760 /* pvfnmsb */, VE::PVFNMSBvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5220 | | { 1760 /* pvfnmsb */, VE::PVFNMSBvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5221 | | { 1760 /* pvfnmsb */, VE::PVFNMSBivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5222 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5223 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5224 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5225 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5226 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5227 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5228 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5229 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5230 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5231 | | { 1768 /* pvfnmsb.lo */, VE::PVFNMSBLOivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5232 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64 }, }, |
5233 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64 }, }, |
5234 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5235 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5236 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5237 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_V64, MCK_VM }, }, |
5238 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5239 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5240 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5241 | | { 1779 /* pvfnmsb.up */, VE::PVFNMSBUPivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5242 | | { 1790 /* pvfsub */, VE::PVFSUBrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5243 | | { 1790 /* pvfsub */, VE::PVFSUBvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5244 | | { 1790 /* pvfsub */, VE::PVFSUBiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5245 | | { 1790 /* pvfsub */, VE::PVFSUBrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5246 | | { 1790 /* pvfsub */, VE::PVFSUBvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5247 | | { 1790 /* pvfsub */, VE::PVFSUBivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5248 | | { 1797 /* pvfsub.lo */, VE::PVFSUBLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5249 | | { 1797 /* pvfsub.lo */, VE::PVFSUBLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5250 | | { 1797 /* pvfsub.lo */, VE::PVFSUBLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5251 | | { 1797 /* pvfsub.lo */, VE::PVFSUBLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5252 | | { 1797 /* pvfsub.lo */, VE::PVFSUBLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5253 | | { 1797 /* pvfsub.lo */, VE::PVFSUBLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5254 | | { 1807 /* pvfsub.up */, VE::PVFSUBUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5255 | | { 1807 /* pvfsub.up */, VE::PVFSUBUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5256 | | { 1807 /* pvfsub.up */, VE::PVFSUBUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5257 | | { 1807 /* pvfsub.up */, VE::PVFSUBUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5258 | | { 1807 /* pvfsub.up */, VE::PVFSUBUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5259 | | { 1807 /* pvfsub.up */, VE::PVFSUBUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5260 | | { 1817 /* pvldz */, VE::PVLDZv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5261 | | { 1817 /* pvldz */, VE::PVLDZvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
5262 | | { 1823 /* pvldz.lo */, VE::PVLDZLOv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5263 | | { 1823 /* pvldz.lo */, VE::PVLDZLOvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5264 | | { 1832 /* pvldz.up */, VE::PVLDZUPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5265 | | { 1832 /* pvldz.up */, VE::PVLDZUPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5266 | | { 1841 /* pvmaxs */, VE::PVMAXSrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5267 | | { 1841 /* pvmaxs */, VE::PVMAXSvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5268 | | { 1841 /* pvmaxs */, VE::PVMAXSiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5269 | | { 1841 /* pvmaxs */, VE::PVMAXSrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5270 | | { 1841 /* pvmaxs */, VE::PVMAXSvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5271 | | { 1841 /* pvmaxs */, VE::PVMAXSivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5272 | | { 1848 /* pvmaxs.lo */, VE::PVMAXSLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5273 | | { 1848 /* pvmaxs.lo */, VE::PVMAXSLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5274 | | { 1848 /* pvmaxs.lo */, VE::PVMAXSLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5275 | | { 1848 /* pvmaxs.lo */, VE::PVMAXSLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5276 | | { 1848 /* pvmaxs.lo */, VE::PVMAXSLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5277 | | { 1848 /* pvmaxs.lo */, VE::PVMAXSLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5278 | | { 1858 /* pvmaxs.up */, VE::PVMAXSUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5279 | | { 1858 /* pvmaxs.up */, VE::PVMAXSUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5280 | | { 1858 /* pvmaxs.up */, VE::PVMAXSUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5281 | | { 1858 /* pvmaxs.up */, VE::PVMAXSUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5282 | | { 1858 /* pvmaxs.up */, VE::PVMAXSUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5283 | | { 1858 /* pvmaxs.up */, VE::PVMAXSUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5284 | | { 1868 /* pvmins */, VE::PVMINSrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5285 | | { 1868 /* pvmins */, VE::PVMINSvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5286 | | { 1868 /* pvmins */, VE::PVMINSiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5287 | | { 1868 /* pvmins */, VE::PVMINSrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5288 | | { 1868 /* pvmins */, VE::PVMINSvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5289 | | { 1868 /* pvmins */, VE::PVMINSivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5290 | | { 1875 /* pvmins.lo */, VE::PVMINSLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5291 | | { 1875 /* pvmins.lo */, VE::PVMINSLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5292 | | { 1875 /* pvmins.lo */, VE::PVMINSLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5293 | | { 1875 /* pvmins.lo */, VE::PVMINSLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5294 | | { 1875 /* pvmins.lo */, VE::PVMINSLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5295 | | { 1875 /* pvmins.lo */, VE::PVMINSLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5296 | | { 1885 /* pvmins.up */, VE::PVMINSUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5297 | | { 1885 /* pvmins.up */, VE::PVMINSUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5298 | | { 1885 /* pvmins.up */, VE::PVMINSUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5299 | | { 1885 /* pvmins.up */, VE::PVMINSUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5300 | | { 1885 /* pvmins.up */, VE::PVMINSUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5301 | | { 1885 /* pvmins.up */, VE::PVMINSUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5302 | | { 1895 /* pvor */, VE::PVORrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5303 | | { 1895 /* pvor */, VE::PVORvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5304 | | { 1895 /* pvor */, VE::PVORmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5305 | | { 1895 /* pvor */, VE::PVORrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5306 | | { 1895 /* pvor */, VE::PVORvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5307 | | { 1895 /* pvor */, VE::PVORmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM512 }, }, |
5308 | | { 1900 /* pvor.lo */, VE::PVORLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5309 | | { 1900 /* pvor.lo */, VE::PVORLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5310 | | { 1900 /* pvor.lo */, VE::PVORLOmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5311 | | { 1900 /* pvor.lo */, VE::PVORLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5312 | | { 1900 /* pvor.lo */, VE::PVORLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5313 | | { 1900 /* pvor.lo */, VE::PVORLOmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5314 | | { 1908 /* pvor.up */, VE::PVORUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5315 | | { 1908 /* pvor.up */, VE::PVORUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5316 | | { 1908 /* pvor.up */, VE::PVORUPmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5317 | | { 1908 /* pvor.up */, VE::PVORUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5318 | | { 1908 /* pvor.up */, VE::PVORUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5319 | | { 1908 /* pvor.up */, VE::PVORUPmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5320 | | { 1916 /* pvpcnt */, VE::PVPCNTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5321 | | { 1916 /* pvpcnt */, VE::PVPCNTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
5322 | | { 1923 /* pvpcnt.lo */, VE::PVPCNTLOv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5323 | | { 1923 /* pvpcnt.lo */, VE::PVPCNTLOvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5324 | | { 1933 /* pvpcnt.up */, VE::PVPCNTUPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5325 | | { 1933 /* pvpcnt.up */, VE::PVPCNTUPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5326 | | { 1943 /* pvrcp */, VE::PVRCPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5327 | | { 1943 /* pvrcp */, VE::PVRCPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
5328 | | { 1949 /* pvrcp.lo */, VE::PVRCPLOv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5329 | | { 1949 /* pvrcp.lo */, VE::PVRCPLOvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5330 | | { 1958 /* pvrcp.up */, VE::PVRCPUPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5331 | | { 1958 /* pvrcp.up */, VE::PVRCPUPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5332 | | { 1967 /* pvrsqrt */, VE::PVRSQRTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5333 | | { 1967 /* pvrsqrt */, VE::PVRSQRTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
5334 | | { 1975 /* pvrsqrt.lo */, VE::PVRSQRTLOv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5335 | | { 1975 /* pvrsqrt.lo */, VE::PVRSQRTLOvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5336 | | { 1986 /* pvrsqrt.lo.nex */, VE::PVRSQRTLONEXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5337 | | { 1986 /* pvrsqrt.lo.nex */, VE::PVRSQRTLONEXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5338 | | { 2001 /* pvrsqrt.nex */, VE::PVRSQRTNEXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5339 | | { 2001 /* pvrsqrt.nex */, VE::PVRSQRTNEXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM512 }, }, |
5340 | | { 2013 /* pvrsqrt.up */, VE::PVRSQRTUPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5341 | | { 2013 /* pvrsqrt.up */, VE::PVRSQRTUPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5342 | | { 2024 /* pvrsqrt.up.nex */, VE::PVRSQRTUPNEXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5343 | | { 2024 /* pvrsqrt.up.nex */, VE::PVRSQRTUPNEXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5344 | | { 2039 /* pvseq */, VE::PVSEQ, Convert__Reg1_0, AMFBS_None, { MCK_V64 }, }, |
5345 | | { 2039 /* pvseq */, VE::PVSEQm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_VM512 }, }, |
5346 | | { 2045 /* pvseq.lo */, VE::PVSEQLO, Convert__Reg1_0, AMFBS_None, { MCK_V64 }, }, |
5347 | | { 2045 /* pvseq.lo */, VE::PVSEQLOm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_VM }, }, |
5348 | | { 2054 /* pvseq.up */, VE::PVSEQUP, Convert__Reg1_0, AMFBS_None, { MCK_V64 }, }, |
5349 | | { 2054 /* pvseq.up */, VE::PVSEQUPm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_VM }, }, |
5350 | | { 2063 /* pvsla */, VE::PVSLAvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5351 | | { 2063 /* pvsla */, VE::PVSLAvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5352 | | { 2063 /* pvsla */, VE::PVSLAvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5353 | | { 2063 /* pvsla */, VE::PVSLAvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM512 }, }, |
5354 | | { 2063 /* pvsla */, VE::PVSLAvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5355 | | { 2063 /* pvsla */, VE::PVSLAvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM512 }, }, |
5356 | | { 2069 /* pvsla.lo */, VE::PVSLALOvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5357 | | { 2069 /* pvsla.lo */, VE::PVSLALOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5358 | | { 2069 /* pvsla.lo */, VE::PVSLALOvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5359 | | { 2069 /* pvsla.lo */, VE::PVSLALOvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5360 | | { 2069 /* pvsla.lo */, VE::PVSLALOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5361 | | { 2069 /* pvsla.lo */, VE::PVSLALOvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5362 | | { 2078 /* pvsla.up */, VE::PVSLAUPvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5363 | | { 2078 /* pvsla.up */, VE::PVSLAUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5364 | | { 2078 /* pvsla.up */, VE::PVSLAUPvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5365 | | { 2078 /* pvsla.up */, VE::PVSLAUPvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_VM }, }, |
5366 | | { 2078 /* pvsla.up */, VE::PVSLAUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5367 | | { 2078 /* pvsla.up */, VE::PVSLAUPvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5368 | | { 2087 /* pvsll */, VE::PVSLLvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5369 | | { 2087 /* pvsll */, VE::PVSLLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5370 | | { 2087 /* pvsll */, VE::PVSLLvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5371 | | { 2087 /* pvsll */, VE::PVSLLvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM512 }, }, |
5372 | | { 2087 /* pvsll */, VE::PVSLLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5373 | | { 2087 /* pvsll */, VE::PVSLLvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM512 }, }, |
5374 | | { 2093 /* pvsll.lo */, VE::PVSLLLOvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5375 | | { 2093 /* pvsll.lo */, VE::PVSLLLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5376 | | { 2093 /* pvsll.lo */, VE::PVSLLLOvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5377 | | { 2093 /* pvsll.lo */, VE::PVSLLLOvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5378 | | { 2093 /* pvsll.lo */, VE::PVSLLLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5379 | | { 2093 /* pvsll.lo */, VE::PVSLLLOvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5380 | | { 2102 /* pvsll.up */, VE::PVSLLUPvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5381 | | { 2102 /* pvsll.up */, VE::PVSLLUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5382 | | { 2102 /* pvsll.up */, VE::PVSLLUPvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5383 | | { 2102 /* pvsll.up */, VE::PVSLLUPvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_VM }, }, |
5384 | | { 2102 /* pvsll.up */, VE::PVSLLUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5385 | | { 2102 /* pvsll.up */, VE::PVSLLUPvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5386 | | { 2111 /* pvsra */, VE::PVSRAvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5387 | | { 2111 /* pvsra */, VE::PVSRAvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5388 | | { 2111 /* pvsra */, VE::PVSRAvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5389 | | { 2111 /* pvsra */, VE::PVSRAvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM512 }, }, |
5390 | | { 2111 /* pvsra */, VE::PVSRAvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5391 | | { 2111 /* pvsra */, VE::PVSRAvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM512 }, }, |
5392 | | { 2117 /* pvsra.lo */, VE::PVSRALOvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5393 | | { 2117 /* pvsra.lo */, VE::PVSRALOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5394 | | { 2117 /* pvsra.lo */, VE::PVSRALOvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5395 | | { 2117 /* pvsra.lo */, VE::PVSRALOvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5396 | | { 2117 /* pvsra.lo */, VE::PVSRALOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5397 | | { 2117 /* pvsra.lo */, VE::PVSRALOvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5398 | | { 2126 /* pvsra.up */, VE::PVSRAUPvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5399 | | { 2126 /* pvsra.up */, VE::PVSRAUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5400 | | { 2126 /* pvsra.up */, VE::PVSRAUPvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5401 | | { 2126 /* pvsra.up */, VE::PVSRAUPvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_VM }, }, |
5402 | | { 2126 /* pvsra.up */, VE::PVSRAUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5403 | | { 2126 /* pvsra.up */, VE::PVSRAUPvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5404 | | { 2135 /* pvsrl */, VE::PVSRLvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5405 | | { 2135 /* pvsrl */, VE::PVSRLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5406 | | { 2135 /* pvsrl */, VE::PVSRLvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5407 | | { 2135 /* pvsrl */, VE::PVSRLvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM512 }, }, |
5408 | | { 2135 /* pvsrl */, VE::PVSRLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5409 | | { 2135 /* pvsrl */, VE::PVSRLvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM512 }, }, |
5410 | | { 2141 /* pvsrl.lo */, VE::PVSRLLOvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5411 | | { 2141 /* pvsrl.lo */, VE::PVSRLLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5412 | | { 2141 /* pvsrl.lo */, VE::PVSRLLOvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5413 | | { 2141 /* pvsrl.lo */, VE::PVSRLLOvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5414 | | { 2141 /* pvsrl.lo */, VE::PVSRLLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5415 | | { 2141 /* pvsrl.lo */, VE::PVSRLLOvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5416 | | { 2150 /* pvsrl.up */, VE::PVSRLUPvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5417 | | { 2150 /* pvsrl.up */, VE::PVSRLUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5418 | | { 2150 /* pvsrl.up */, VE::PVSRLUPvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
5419 | | { 2150 /* pvsrl.up */, VE::PVSRLUPvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_VM }, }, |
5420 | | { 2150 /* pvsrl.up */, VE::PVSRLUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5421 | | { 2150 /* pvsrl.up */, VE::PVSRLUPvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
5422 | | { 2159 /* pvsubs */, VE::PVSUBSrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5423 | | { 2159 /* pvsubs */, VE::PVSUBSvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5424 | | { 2159 /* pvsubs */, VE::PVSUBSiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5425 | | { 2159 /* pvsubs */, VE::PVSUBSrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5426 | | { 2159 /* pvsubs */, VE::PVSUBSvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5427 | | { 2159 /* pvsubs */, VE::PVSUBSivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5428 | | { 2166 /* pvsubs.lo */, VE::PVSUBSLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5429 | | { 2166 /* pvsubs.lo */, VE::PVSUBSLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5430 | | { 2166 /* pvsubs.lo */, VE::PVSUBSLOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5431 | | { 2166 /* pvsubs.lo */, VE::PVSUBSLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5432 | | { 2166 /* pvsubs.lo */, VE::PVSUBSLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5433 | | { 2166 /* pvsubs.lo */, VE::PVSUBSLOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5434 | | { 2176 /* pvsubs.up */, VE::PVSUBSUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5435 | | { 2176 /* pvsubs.up */, VE::PVSUBSUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5436 | | { 2176 /* pvsubs.up */, VE::PVSUBSUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5437 | | { 2176 /* pvsubs.up */, VE::PVSUBSUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5438 | | { 2176 /* pvsubs.up */, VE::PVSUBSUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5439 | | { 2176 /* pvsubs.up */, VE::PVSUBSUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5440 | | { 2186 /* pvsubu */, VE::PVSUBUrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5441 | | { 2186 /* pvsubu */, VE::PVSUBUvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5442 | | { 2186 /* pvsubu */, VE::PVSUBUiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5443 | | { 2186 /* pvsubu */, VE::PVSUBUrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5444 | | { 2186 /* pvsubu */, VE::PVSUBUvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5445 | | { 2186 /* pvsubu */, VE::PVSUBUivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
5446 | | { 2193 /* pvsubu.lo */, VE::PVSUBULOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5447 | | { 2193 /* pvsubu.lo */, VE::PVSUBULOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5448 | | { 2193 /* pvsubu.lo */, VE::PVSUBULOiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5449 | | { 2193 /* pvsubu.lo */, VE::PVSUBULOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5450 | | { 2193 /* pvsubu.lo */, VE::PVSUBULOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5451 | | { 2193 /* pvsubu.lo */, VE::PVSUBULOivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5452 | | { 2203 /* pvsubu.up */, VE::PVSUBUUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5453 | | { 2203 /* pvsubu.up */, VE::PVSUBUUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5454 | | { 2203 /* pvsubu.up */, VE::PVSUBUUPiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5455 | | { 2203 /* pvsubu.up */, VE::PVSUBUUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5456 | | { 2203 /* pvsubu.up */, VE::PVSUBUUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5457 | | { 2203 /* pvsubu.up */, VE::PVSUBUUPivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5458 | | { 2213 /* pvxor */, VE::PVXORrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5459 | | { 2213 /* pvxor */, VE::PVXORvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5460 | | { 2213 /* pvxor */, VE::PVXORmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5461 | | { 2213 /* pvxor */, VE::PVXORrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
5462 | | { 2213 /* pvxor */, VE::PVXORvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
5463 | | { 2213 /* pvxor */, VE::PVXORmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM512 }, }, |
5464 | | { 2219 /* pvxor.lo */, VE::PVXORLOrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5465 | | { 2219 /* pvxor.lo */, VE::PVXORLOvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5466 | | { 2219 /* pvxor.lo */, VE::PVXORLOmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5467 | | { 2219 /* pvxor.lo */, VE::PVXORLOrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5468 | | { 2219 /* pvxor.lo */, VE::PVXORLOvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5469 | | { 2219 /* pvxor.lo */, VE::PVXORLOmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5470 | | { 2228 /* pvxor.up */, VE::PVXORUPrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5471 | | { 2228 /* pvxor.up */, VE::PVXORUPvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5472 | | { 2228 /* pvxor.up */, VE::PVXORUPmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5473 | | { 2228 /* pvxor.up */, VE::PVXORUPrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5474 | | { 2228 /* pvxor.up */, VE::PVXORUPvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5475 | | { 2228 /* pvxor.up */, VE::PVXORUPmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5476 | | { 2237 /* scr */, VE::SCRrrr, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
5477 | | { 2237 /* scr */, VE::SCRrzr, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_I64, MCK_I64, MCK_Zero }, }, |
5478 | | { 2237 /* scr */, VE::SCRirr, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5479 | | { 2237 /* scr */, VE::SCRizr, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5480 | | { 2241 /* sfr */, VE::SFR, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
5481 | | { 2245 /* shm.b */, VE::SHMBri, Convert__MEMri2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
5482 | | { 2245 /* shm.b */, VE::SHMBzi, Convert__MEMzi2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
5483 | | { 2251 /* shm.h */, VE::SHMHri, Convert__MEMri2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
5484 | | { 2251 /* shm.h */, VE::SHMHzi, Convert__MEMzi2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
5485 | | { 2257 /* shm.l */, VE::SHMLri, Convert__MEMri2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
5486 | | { 2257 /* shm.l */, VE::SHMLzi, Convert__MEMzi2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
5487 | | { 2263 /* shm.w */, VE::SHMWri, Convert__MEMri2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMri }, }, |
5488 | | { 2263 /* shm.w */, VE::SHMWzi, Convert__MEMzi2_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMzi }, }, |
5489 | | { 2269 /* sic */, VE::SIC, Convert__Reg1_0, AMFBS_None, { MCK_I32 }, }, |
5490 | | { 2273 /* sla.l */, VE::SLALrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I32 }, }, |
5491 | | { 2273 /* sla.l */, VE::SLALri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm7 }, }, |
5492 | | { 2273 /* sla.l */, VE::SLALmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_I32 }, }, |
5493 | | { 2273 /* sla.l */, VE::SLALmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm7 }, }, |
5494 | | { 2279 /* sla.w.sx */, VE::SLAWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5495 | | { 2279 /* sla.w.sx */, VE::SLAWSXri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_UImm7 }, }, |
5496 | | { 2279 /* sla.w.sx */, VE::SLAWSXmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_I32 }, }, |
5497 | | { 2279 /* sla.w.sx */, VE::SLAWSXmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_UImm7 }, }, |
5498 | | { 2288 /* sla.w.zx */, VE::SLAWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5499 | | { 2288 /* sla.w.zx */, VE::SLAWZXri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_UImm7 }, }, |
5500 | | { 2288 /* sla.w.zx */, VE::SLAWZXmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_I32 }, }, |
5501 | | { 2288 /* sla.w.zx */, VE::SLAWZXmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_UImm7 }, }, |
5502 | | { 2297 /* sld */, VE::SLDrrr, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I32 }, }, |
5503 | | { 2297 /* sld */, VE::SLDrri, Convert__Reg1_0__Tie0_1_1__Reg1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm7 }, }, |
5504 | | { 2297 /* sld */, VE::SLDrmr, Convert__Reg1_0__Tie0_1_1__MImm1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_I32 }, }, |
5505 | | { 2297 /* sld */, VE::SLDrmi, Convert__Reg1_0__Tie0_1_1__MImm1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm7 }, }, |
5506 | | { 2301 /* sll */, VE::SLLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I32 }, }, |
5507 | | { 2301 /* sll */, VE::SLLri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm7 }, }, |
5508 | | { 2301 /* sll */, VE::SLLmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_I32 }, }, |
5509 | | { 2301 /* sll */, VE::SLLmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm7 }, }, |
5510 | | { 2305 /* smir */, VE::SMIR, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_MISC }, }, |
5511 | | { 2310 /* smvl */, VE::SMVL, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
5512 | | { 2315 /* spm */, VE::SPM, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
5513 | | { 2319 /* sra.l */, VE::SRALrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I32 }, }, |
5514 | | { 2319 /* sra.l */, VE::SRALri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm7 }, }, |
5515 | | { 2319 /* sra.l */, VE::SRALmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_I32 }, }, |
5516 | | { 2319 /* sra.l */, VE::SRALmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm7 }, }, |
5517 | | { 2325 /* sra.w.sx */, VE::SRAWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5518 | | { 2325 /* sra.w.sx */, VE::SRAWSXri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_UImm7 }, }, |
5519 | | { 2325 /* sra.w.sx */, VE::SRAWSXmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_I32 }, }, |
5520 | | { 2325 /* sra.w.sx */, VE::SRAWSXmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_UImm7 }, }, |
5521 | | { 2334 /* sra.w.zx */, VE::SRAWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5522 | | { 2334 /* sra.w.zx */, VE::SRAWZXri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_UImm7 }, }, |
5523 | | { 2334 /* sra.w.zx */, VE::SRAWZXmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_I32 }, }, |
5524 | | { 2334 /* sra.w.zx */, VE::SRAWZXmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I32, MCK_MImm, MCK_UImm7 }, }, |
5525 | | { 2343 /* srd */, VE::SRDrrr, Convert__Reg1_0__Reg1_1__Tie0_1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I32 }, }, |
5526 | | { 2343 /* srd */, VE::SRDrri, Convert__Reg1_0__Reg1_1__Tie0_1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm7 }, }, |
5527 | | { 2343 /* srd */, VE::SRDmrr, Convert__Reg1_0__MImm1_1__Tie0_1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_I32 }, }, |
5528 | | { 2343 /* srd */, VE::SRDmri, Convert__Reg1_0__MImm1_1__Tie0_1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm7 }, }, |
5529 | | { 2347 /* srl */, VE::SRLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I32 }, }, |
5530 | | { 2347 /* srl */, VE::SRLri, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_UImm7 }, }, |
5531 | | { 2347 /* srl */, VE::SRLmr, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_I32 }, }, |
5532 | | { 2347 /* srl */, VE::SRLmi, Convert__Reg1_0__MImm1_1__UImm71_2, AMFBS_None, { MCK_I64, MCK_MImm, MCK_UImm7 }, }, |
5533 | | { 2351 /* st */, VE::STrii, Convert__MEMrii3_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMrii }, }, |
5534 | | { 2351 /* st */, VE::STrri, Convert__MEMrri3_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMrri }, }, |
5535 | | { 2351 /* st */, VE::STzii, Convert__MEMzii3_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMzii }, }, |
5536 | | { 2351 /* st */, VE::STzri, Convert__MEMzri3_1__Reg1_0, AMFBS_None, { MCK_I64, MCK_MEMzri }, }, |
5537 | | { 2354 /* st1b */, VE::ST1Brii, Convert__MEMrii3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
5538 | | { 2354 /* st1b */, VE::ST1Brri, Convert__MEMrri3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
5539 | | { 2354 /* st1b */, VE::ST1Bzii, Convert__MEMzii3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
5540 | | { 2354 /* st1b */, VE::ST1Bzri, Convert__MEMzri3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
5541 | | { 2359 /* st2b */, VE::ST2Brii, Convert__MEMrii3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
5542 | | { 2359 /* st2b */, VE::ST2Brri, Convert__MEMrri3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
5543 | | { 2359 /* st2b */, VE::ST2Bzii, Convert__MEMzii3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
5544 | | { 2359 /* st2b */, VE::ST2Bzri, Convert__MEMzri3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
5545 | | { 2364 /* stl */, VE::STLrii, Convert__MEMrii3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMrii }, }, |
5546 | | { 2364 /* stl */, VE::STLrri, Convert__MEMrri3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMrri }, }, |
5547 | | { 2364 /* stl */, VE::STLzii, Convert__MEMzii3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMzii }, }, |
5548 | | { 2364 /* stl */, VE::STLzri, Convert__MEMzri3_1__Reg1_0, AMFBS_None, { MCK_I32, MCK_MEMzri }, }, |
5549 | | { 2368 /* stu */, VE::STUrii, Convert__MEMrii3_1__Reg1_0, AMFBS_None, { MCK_F32, MCK_MEMrii }, }, |
5550 | | { 2368 /* stu */, VE::STUrri, Convert__MEMrri3_1__Reg1_0, AMFBS_None, { MCK_F32, MCK_MEMrri }, }, |
5551 | | { 2368 /* stu */, VE::STUzii, Convert__MEMzii3_1__Reg1_0, AMFBS_None, { MCK_F32, MCK_MEMzii }, }, |
5552 | | { 2368 /* stu */, VE::STUzri, Convert__MEMzri3_1__Reg1_0, AMFBS_None, { MCK_F32, MCK_MEMzri }, }, |
5553 | | { 2372 /* subs.l */, VE::SUBSLrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
5554 | | { 2372 /* subs.l */, VE::SUBSLrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
5555 | | { 2372 /* subs.l */, VE::SUBSLir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5556 | | { 2372 /* subs.l */, VE::SUBSLim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
5557 | | { 2379 /* subs.w.sx */, VE::SUBSWSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5558 | | { 2379 /* subs.w.sx */, VE::SUBSWSXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
5559 | | { 2379 /* subs.w.sx */, VE::SUBSWSXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
5560 | | { 2379 /* subs.w.sx */, VE::SUBSWSXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
5561 | | { 2389 /* subs.w.zx */, VE::SUBSWZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5562 | | { 2389 /* subs.w.zx */, VE::SUBSWZXrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
5563 | | { 2389 /* subs.w.zx */, VE::SUBSWZXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
5564 | | { 2389 /* subs.w.zx */, VE::SUBSWZXim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
5565 | | { 2399 /* subu.l */, VE::SUBULrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
5566 | | { 2399 /* subu.l */, VE::SUBULrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
5567 | | { 2399 /* subu.l */, VE::SUBULir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5568 | | { 2399 /* subu.l */, VE::SUBULim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
5569 | | { 2406 /* subu.w */, VE::SUBUWrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_I32 }, }, |
5570 | | { 2406 /* subu.w */, VE::SUBUWrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_I32, MCK_MImm }, }, |
5571 | | { 2406 /* subu.w */, VE::SUBUWir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_I32 }, }, |
5572 | | { 2406 /* subu.w */, VE::SUBUWim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I32, MCK_SImm7, MCK_MImm }, }, |
5573 | | { 2413 /* svl */, VE::SVL, Convert__Reg1_0, AMFBS_None, { MCK_I64 }, }, |
5574 | | { 2417 /* svm */, VE::SVMmr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_VM, MCK_I64 }, }, |
5575 | | { 2417 /* svm */, VE::SVMmi, Convert__Reg1_0__Reg1_1__UImm21_2, AMFBS_None, { MCK_I64, MCK_VM, MCK_UImm2 }, }, |
5576 | | { 2421 /* svob */, VE::SVOB, Convert_NoOperands, AMFBS_None, { }, }, |
5577 | | { 2426 /* tovm */, VE::TOVMm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_I64, MCK_VM }, }, |
5578 | | { 2431 /* ts1am.l */, VE::TS1AMLrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_I64 }, }, |
5579 | | { 2431 /* ts1am.l */, VE::TS1AMLrii, Convert__Reg1_0__MEMri2_1__UImm71_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_UImm7 }, }, |
5580 | | { 2431 /* ts1am.l */, VE::TS1AMLzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_I64 }, }, |
5581 | | { 2431 /* ts1am.l */, VE::TS1AMLzii, Convert__Reg1_0__MEMzi2_1__UImm71_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_UImm7 }, }, |
5582 | | { 2439 /* ts1am.w */, VE::TS1AMWrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMri, MCK_I32 }, }, |
5583 | | { 2439 /* ts1am.w */, VE::TS1AMWrii, Convert__Reg1_0__MEMri2_1__UImm71_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMri, MCK_UImm7 }, }, |
5584 | | { 2439 /* ts1am.w */, VE::TS1AMWzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMzi, MCK_I32 }, }, |
5585 | | { 2439 /* ts1am.w */, VE::TS1AMWzii, Convert__Reg1_0__MEMzi2_1__UImm71_2__Tie0_1_1, AMFBS_None, { MCK_I32, MCK_MEMzi, MCK_UImm7 }, }, |
5586 | | { 2447 /* ts2am */, VE::TS2AMrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_I64 }, }, |
5587 | | { 2447 /* ts2am */, VE::TS2AMrii, Convert__Reg1_0__MEMri2_1__UImm71_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_UImm7 }, }, |
5588 | | { 2447 /* ts2am */, VE::TS2AMzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_I64 }, }, |
5589 | | { 2447 /* ts2am */, VE::TS2AMzii, Convert__Reg1_0__MEMzi2_1__UImm71_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_UImm7 }, }, |
5590 | | { 2453 /* ts3am */, VE::TS3AMrir, Convert__Reg1_0__MEMri2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_I64 }, }, |
5591 | | { 2453 /* ts3am */, VE::TS3AMrii, Convert__Reg1_0__MEMri2_1__UImm11_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMri, MCK_UImm1 }, }, |
5592 | | { 2453 /* ts3am */, VE::TS3AMzir, Convert__Reg1_0__MEMzi2_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_I64 }, }, |
5593 | | { 2453 /* ts3am */, VE::TS3AMzii, Convert__Reg1_0__MEMzi2_1__UImm11_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_MEMzi, MCK_UImm1 }, }, |
5594 | | { 2459 /* tscr */, VE::TSCRrrr, Convert__Reg1_0__Reg1_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
5595 | | { 2459 /* tscr */, VE::TSCRrzr, Convert__Reg1_0__Reg1_1__Zero1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_I64, MCK_Zero }, }, |
5596 | | { 2459 /* tscr */, VE::TSCRirr, Convert__Reg1_0__SImm71_1__Reg1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5597 | | { 2459 /* tscr */, VE::TSCRizr, Convert__Reg1_0__SImm71_1__Zero1_2__Tie0_1_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5598 | | { 2464 /* vadds.l */, VE::VADDSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5599 | | { 2464 /* vadds.l */, VE::VADDSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5600 | | { 2464 /* vadds.l */, VE::VADDSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5601 | | { 2464 /* vadds.l */, VE::VADDSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5602 | | { 2464 /* vadds.l */, VE::VADDSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5603 | | { 2464 /* vadds.l */, VE::VADDSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5604 | | { 2472 /* vadds.w.sx */, VE::VADDSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5605 | | { 2472 /* vadds.w.sx */, VE::VADDSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5606 | | { 2472 /* vadds.w.sx */, VE::VADDSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5607 | | { 2472 /* vadds.w.sx */, VE::VADDSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5608 | | { 2472 /* vadds.w.sx */, VE::VADDSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5609 | | { 2472 /* vadds.w.sx */, VE::VADDSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5610 | | { 2483 /* vaddu.l */, VE::VADDULrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5611 | | { 2483 /* vaddu.l */, VE::VADDULvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5612 | | { 2483 /* vaddu.l */, VE::VADDULiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5613 | | { 2483 /* vaddu.l */, VE::VADDULrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5614 | | { 2483 /* vaddu.l */, VE::VADDULvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5615 | | { 2483 /* vaddu.l */, VE::VADDULivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5616 | | { 2491 /* vand */, VE::VANDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5617 | | { 2491 /* vand */, VE::VANDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5618 | | { 2491 /* vand */, VE::VANDmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5619 | | { 2491 /* vand */, VE::VANDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5620 | | { 2491 /* vand */, VE::VANDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5621 | | { 2491 /* vand */, VE::VANDmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5622 | | { 2496 /* vbrd */, VE::VBRDr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_I64 }, }, |
5623 | | { 2496 /* vbrd */, VE::VBRDi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_V64, MCK_SImm7 }, }, |
5624 | | { 2496 /* vbrd */, VE::VBRDrm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_VM }, }, |
5625 | | { 2496 /* vbrd */, VE::VBRDim, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_VM }, }, |
5626 | | { 2501 /* vbrdl */, VE::VBRDLr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_I32 }, }, |
5627 | | { 2501 /* vbrdl */, VE::VBRDLi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_V64, MCK_SImm7 }, }, |
5628 | | { 2501 /* vbrdl */, VE::VBRDLrm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_VM }, }, |
5629 | | { 2501 /* vbrdl */, VE::VBRDLim, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_VM }, }, |
5630 | | { 2507 /* vbrdu */, VE::VBRDUr, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_F32 }, }, |
5631 | | { 2507 /* vbrdu */, VE::VBRDUi, Convert__Reg1_0__SImm71_1, AMFBS_None, { MCK_V64, MCK_SImm7 }, }, |
5632 | | { 2507 /* vbrdu */, VE::VBRDUrm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_VM }, }, |
5633 | | { 2507 /* vbrdu */, VE::VBRDUim, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_VM }, }, |
5634 | | { 2513 /* vbrv */, VE::VBRVv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5635 | | { 2513 /* vbrv */, VE::VBRVvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5636 | | { 2518 /* vcmps.l */, VE::VCMPSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5637 | | { 2518 /* vcmps.l */, VE::VCMPSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5638 | | { 2518 /* vcmps.l */, VE::VCMPSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5639 | | { 2518 /* vcmps.l */, VE::VCMPSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5640 | | { 2518 /* vcmps.l */, VE::VCMPSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5641 | | { 2518 /* vcmps.l */, VE::VCMPSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5642 | | { 2526 /* vcmps.w.sx */, VE::VCMPSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5643 | | { 2526 /* vcmps.w.sx */, VE::VCMPSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5644 | | { 2526 /* vcmps.w.sx */, VE::VCMPSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5645 | | { 2526 /* vcmps.w.sx */, VE::VCMPSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5646 | | { 2526 /* vcmps.w.sx */, VE::VCMPSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5647 | | { 2526 /* vcmps.w.sx */, VE::VCMPSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5648 | | { 2537 /* vcmpu.l */, VE::VCMPULrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5649 | | { 2537 /* vcmpu.l */, VE::VCMPULvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5650 | | { 2537 /* vcmpu.l */, VE::VCMPULiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5651 | | { 2537 /* vcmpu.l */, VE::VCMPULrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5652 | | { 2537 /* vcmpu.l */, VE::VCMPULvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5653 | | { 2537 /* vcmpu.l */, VE::VCMPULivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5654 | | { 2545 /* vcp */, VE::VCPv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5655 | | { 2545 /* vcp */, VE::VCPvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5656 | | { 2549 /* vcvt.d.l */, VE::VCVTDLv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5657 | | { 2549 /* vcvt.d.l */, VE::VCVTDLvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5658 | | { 2558 /* vcvt.d.s */, VE::VCVTDSv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5659 | | { 2558 /* vcvt.d.s */, VE::VCVTDSvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5660 | | { 2567 /* vcvt.d.w */, VE::VCVTDWv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5661 | | { 2567 /* vcvt.d.w */, VE::VCVTDWvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5662 | | { 2576 /* vcvt.l.d */, VE::VCVTLDv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
5663 | | { 2576 /* vcvt.l.d */, VE::VCVTLDvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
5664 | | { 2585 /* vcvt.s.d */, VE::VCVTSDv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5665 | | { 2585 /* vcvt.s.d */, VE::VCVTSDvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5666 | | { 2594 /* vcvt.s.w */, VE::VCVTSWv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5667 | | { 2594 /* vcvt.s.w */, VE::VCVTSWvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5668 | | { 2603 /* vcvt.w.d.sx */, VE::VCVTWDSXv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
5669 | | { 2603 /* vcvt.w.d.sx */, VE::VCVTWDSXvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
5670 | | { 2615 /* vcvt.w.d.zx */, VE::VCVTWDZXv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
5671 | | { 2615 /* vcvt.w.d.zx */, VE::VCVTWDZXvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
5672 | | { 2627 /* vcvt.w.s.sx */, VE::VCVTWSSXv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
5673 | | { 2627 /* vcvt.w.s.sx */, VE::VCVTWSSXvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
5674 | | { 2639 /* vcvt.w.s.zx */, VE::VCVTWSZXv, Convert__Reg1_1__RDOp1_0__Reg1_2, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64 }, }, |
5675 | | { 2639 /* vcvt.w.s.zx */, VE::VCVTWSZXvm, Convert__Reg1_1__RDOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_RDOp, MCK_V64, MCK_V64, MCK_VM }, }, |
5676 | | { 2651 /* vdivs.l */, VE::VDIVSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5677 | | { 2651 /* vdivs.l */, VE::VDIVSLvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5678 | | { 2651 /* vdivs.l */, VE::VDIVSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5679 | | { 2651 /* vdivs.l */, VE::VDIVSLvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5680 | | { 2651 /* vdivs.l */, VE::VDIVSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5681 | | { 2651 /* vdivs.l */, VE::VDIVSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5682 | | { 2651 /* vdivs.l */, VE::VDIVSLvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
5683 | | { 2651 /* vdivs.l */, VE::VDIVSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5684 | | { 2651 /* vdivs.l */, VE::VDIVSLvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5685 | | { 2651 /* vdivs.l */, VE::VDIVSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5686 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5687 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5688 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5689 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5690 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5691 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5692 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5693 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5694 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5695 | | { 2659 /* vdivs.w.sx */, VE::VDIVSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5696 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5697 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5698 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5699 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5700 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5701 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5702 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5703 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5704 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5705 | | { 2670 /* vdivs.w.zx */, VE::VDIVSWZXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5706 | | { 2681 /* vdivu.l */, VE::VDIVULrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5707 | | { 2681 /* vdivu.l */, VE::VDIVULvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5708 | | { 2681 /* vdivu.l */, VE::VDIVULvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5709 | | { 2681 /* vdivu.l */, VE::VDIVULvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5710 | | { 2681 /* vdivu.l */, VE::VDIVULiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5711 | | { 2681 /* vdivu.l */, VE::VDIVULrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5712 | | { 2681 /* vdivu.l */, VE::VDIVULvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
5713 | | { 2681 /* vdivu.l */, VE::VDIVULvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5714 | | { 2681 /* vdivu.l */, VE::VDIVULvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5715 | | { 2681 /* vdivu.l */, VE::VDIVULivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5716 | | { 2689 /* vdivu.w */, VE::VDIVUWrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
5717 | | { 2689 /* vdivu.w */, VE::VDIVUWvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
5718 | | { 2689 /* vdivu.w */, VE::VDIVUWvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5719 | | { 2689 /* vdivu.w */, VE::VDIVUWvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5720 | | { 2689 /* vdivu.w */, VE::VDIVUWiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5721 | | { 2689 /* vdivu.w */, VE::VDIVUWrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
5722 | | { 2689 /* vdivu.w */, VE::VDIVUWvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
5723 | | { 2689 /* vdivu.w */, VE::VDIVUWvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5724 | | { 2689 /* vdivu.w */, VE::VDIVUWvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5725 | | { 2689 /* vdivu.w */, VE::VDIVUWivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5726 | | { 2697 /* veqv */, VE::VEQVrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5727 | | { 2697 /* veqv */, VE::VEQVvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5728 | | { 2697 /* veqv */, VE::VEQVmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
5729 | | { 2697 /* veqv */, VE::VEQVrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5730 | | { 2697 /* veqv */, VE::VEQVvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5731 | | { 2697 /* veqv */, VE::VEQVmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
5732 | | { 2702 /* vex */, VE::VEXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5733 | | { 2702 /* vex */, VE::VEXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5734 | | { 2706 /* vfadd.d */, VE::VFADDDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5735 | | { 2706 /* vfadd.d */, VE::VFADDDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5736 | | { 2706 /* vfadd.d */, VE::VFADDDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5737 | | { 2706 /* vfadd.d */, VE::VFADDDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5738 | | { 2706 /* vfadd.d */, VE::VFADDDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5739 | | { 2706 /* vfadd.d */, VE::VFADDDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5740 | | { 2714 /* vfcmp.d */, VE::VFCMPDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5741 | | { 2714 /* vfcmp.d */, VE::VFCMPDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5742 | | { 2714 /* vfcmp.d */, VE::VFCMPDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5743 | | { 2714 /* vfcmp.d */, VE::VFCMPDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5744 | | { 2714 /* vfcmp.d */, VE::VFCMPDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5745 | | { 2714 /* vfcmp.d */, VE::VFCMPDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5746 | | { 2722 /* vfdiv.d */, VE::VFDIVDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5747 | | { 2722 /* vfdiv.d */, VE::VFDIVDvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5748 | | { 2722 /* vfdiv.d */, VE::VFDIVDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5749 | | { 2722 /* vfdiv.d */, VE::VFDIVDvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5750 | | { 2722 /* vfdiv.d */, VE::VFDIVDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5751 | | { 2722 /* vfdiv.d */, VE::VFDIVDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5752 | | { 2722 /* vfdiv.d */, VE::VFDIVDvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
5753 | | { 2722 /* vfdiv.d */, VE::VFDIVDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5754 | | { 2722 /* vfdiv.d */, VE::VFDIVDvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5755 | | { 2722 /* vfdiv.d */, VE::VFDIVDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5756 | | { 2730 /* vfdiv.s */, VE::VFDIVSrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64 }, }, |
5757 | | { 2730 /* vfdiv.s */, VE::VFDIVSvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5758 | | { 2730 /* vfdiv.s */, VE::VFDIVSvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5759 | | { 2730 /* vfdiv.s */, VE::VFDIVSvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5760 | | { 2730 /* vfdiv.s */, VE::VFDIVSiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5761 | | { 2730 /* vfdiv.s */, VE::VFDIVSrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_F32, MCK_V64, MCK_VM }, }, |
5762 | | { 2730 /* vfdiv.s */, VE::VFDIVSvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32, MCK_VM }, }, |
5763 | | { 2730 /* vfdiv.s */, VE::VFDIVSvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5764 | | { 2730 /* vfdiv.s */, VE::VFDIVSvim, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_VM }, }, |
5765 | | { 2730 /* vfdiv.s */, VE::VFDIVSivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5766 | | { 2738 /* vfia.d */, VE::VFIADvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5767 | | { 2738 /* vfia.d */, VE::VFIADvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5768 | | { 2745 /* vfia.s */, VE::VFIASvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5769 | | { 2745 /* vfia.s */, VE::VFIASvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5770 | | { 2752 /* vfiam.d */, VE::VFIAMDvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_I64 }, }, |
5771 | | { 2752 /* vfiam.d */, VE::VFIAMDvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5772 | | { 2760 /* vfiam.s */, VE::VFIAMSvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_F32 }, }, |
5773 | | { 2760 /* vfiam.s */, VE::VFIAMSvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5774 | | { 2768 /* vfim.d */, VE::VFIMDvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5775 | | { 2768 /* vfim.d */, VE::VFIMDvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5776 | | { 2775 /* vfim.s */, VE::VFIMSvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5777 | | { 2775 /* vfim.s */, VE::VFIMSvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5778 | | { 2782 /* vfima.d */, VE::VFIMADvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_I64 }, }, |
5779 | | { 2782 /* vfima.d */, VE::VFIMADvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5780 | | { 2790 /* vfima.s */, VE::VFIMASvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_F32 }, }, |
5781 | | { 2790 /* vfima.s */, VE::VFIMASvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5782 | | { 2798 /* vfims.d */, VE::VFIMSDvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_I64 }, }, |
5783 | | { 2798 /* vfims.d */, VE::VFIMSDvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5784 | | { 2806 /* vfims.s */, VE::VFIMSSvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_F32 }, }, |
5785 | | { 2806 /* vfims.s */, VE::VFIMSSvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5786 | | { 2814 /* vfis.d */, VE::VFISDvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
5787 | | { 2814 /* vfis.d */, VE::VFISDvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5788 | | { 2821 /* vfis.s */, VE::VFISSvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_F32 }, }, |
5789 | | { 2821 /* vfis.s */, VE::VFISSvi, Convert__Reg1_0__Reg1_1__SImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5790 | | { 2828 /* vfism.d */, VE::VFISMDvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_I64 }, }, |
5791 | | { 2828 /* vfism.d */, VE::VFISMDvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5792 | | { 2836 /* vfism.s */, VE::VFISMSvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_F32 }, }, |
5793 | | { 2836 /* vfism.s */, VE::VFISMSvvi, Convert__Reg1_0__Reg1_1__Reg1_2__SImm71_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_SImm7 }, }, |
5794 | | { 2844 /* vfmad.d */, VE::VFMADDrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5795 | | { 2844 /* vfmad.d */, VE::VFMADDvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5796 | | { 2844 /* vfmad.d */, VE::VFMADDvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5797 | | { 2844 /* vfmad.d */, VE::VFMADDviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5798 | | { 2844 /* vfmad.d */, VE::VFMADDivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5799 | | { 2844 /* vfmad.d */, VE::VFMADDrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5800 | | { 2844 /* vfmad.d */, VE::VFMADDvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5801 | | { 2844 /* vfmad.d */, VE::VFMADDvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5802 | | { 2844 /* vfmad.d */, VE::VFMADDvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5803 | | { 2844 /* vfmad.d */, VE::VFMADDivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5804 | | { 2852 /* vfmax.d */, VE::VFMAXDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5805 | | { 2852 /* vfmax.d */, VE::VFMAXDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5806 | | { 2852 /* vfmax.d */, VE::VFMAXDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5807 | | { 2852 /* vfmax.d */, VE::VFMAXDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5808 | | { 2852 /* vfmax.d */, VE::VFMAXDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5809 | | { 2852 /* vfmax.d */, VE::VFMAXDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5810 | | { 2860 /* vfmin.d */, VE::VFMINDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5811 | | { 2860 /* vfmin.d */, VE::VFMINDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5812 | | { 2860 /* vfmin.d */, VE::VFMINDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5813 | | { 2860 /* vfmin.d */, VE::VFMINDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5814 | | { 2860 /* vfmin.d */, VE::VFMINDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5815 | | { 2860 /* vfmin.d */, VE::VFMINDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5816 | | { 2868 /* vfmk.d. */, VE::VFMKDv, Convert__Reg1_1__CCOp1_0__Reg1_2, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64 }, }, |
5817 | | { 2868 /* vfmk.d. */, VE::VFMKDvm, Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64, MCK_VM }, }, |
5818 | | { 2876 /* vfmk.d.af */, VE::VFMKDna, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5819 | | { 2876 /* vfmk.d.af */, VE::VFMKDnam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5820 | | { 2886 /* vfmk.d.at */, VE::VFMKDa, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5821 | | { 2886 /* vfmk.d.at */, VE::VFMKDam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5822 | | { 2896 /* vfmk.l. */, VE::VFMKLv, Convert__Reg1_1__CCOp1_0__Reg1_2, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64 }, }, |
5823 | | { 2896 /* vfmk.l. */, VE::VFMKLvm, Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64, MCK_VM }, }, |
5824 | | { 2904 /* vfmk.l.af */, VE::VFMKLna, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5825 | | { 2904 /* vfmk.l.af */, VE::VFMKLnam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5826 | | { 2914 /* vfmk.l.at */, VE::VFMKLa, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5827 | | { 2914 /* vfmk.l.at */, VE::VFMKLam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5828 | | { 2924 /* vfmk.w. */, VE::VFMKWv, Convert__Reg1_1__CCOp1_0__Reg1_2, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64 }, }, |
5829 | | { 2924 /* vfmk.w. */, VE::VFMKWvm, Convert__Reg1_1__CCOp1_0__Reg1_2__Reg1_3, AMFBS_None, { MCK_CCOp, MCK_VM, MCK_V64, MCK_VM }, }, |
5830 | | { 2932 /* vfmk.w.af */, VE::VFMKWna, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5831 | | { 2932 /* vfmk.w.af */, VE::VFMKWnam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5832 | | { 2942 /* vfmk.w.at */, VE::VFMKWa, Convert__Reg1_0, AMFBS_None, { MCK_VM }, }, |
5833 | | { 2942 /* vfmk.w.at */, VE::VFMKWam, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_VM, MCK_VM }, }, |
5834 | | { 2952 /* vfmsb.d */, VE::VFMSBDrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5835 | | { 2952 /* vfmsb.d */, VE::VFMSBDvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5836 | | { 2952 /* vfmsb.d */, VE::VFMSBDvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5837 | | { 2952 /* vfmsb.d */, VE::VFMSBDviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5838 | | { 2952 /* vfmsb.d */, VE::VFMSBDivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5839 | | { 2952 /* vfmsb.d */, VE::VFMSBDrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5840 | | { 2952 /* vfmsb.d */, VE::VFMSBDvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5841 | | { 2952 /* vfmsb.d */, VE::VFMSBDvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5842 | | { 2952 /* vfmsb.d */, VE::VFMSBDvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5843 | | { 2952 /* vfmsb.d */, VE::VFMSBDivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5844 | | { 2960 /* vfmul.d */, VE::VFMULDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5845 | | { 2960 /* vfmul.d */, VE::VFMULDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5846 | | { 2960 /* vfmul.d */, VE::VFMULDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5847 | | { 2960 /* vfmul.d */, VE::VFMULDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5848 | | { 2960 /* vfmul.d */, VE::VFMULDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5849 | | { 2960 /* vfmul.d */, VE::VFMULDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5850 | | { 2968 /* vfnmad.d */, VE::VFNMADDrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5851 | | { 2968 /* vfnmad.d */, VE::VFNMADDvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5852 | | { 2968 /* vfnmad.d */, VE::VFNMADDvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5853 | | { 2968 /* vfnmad.d */, VE::VFNMADDviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5854 | | { 2968 /* vfnmad.d */, VE::VFNMADDivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5855 | | { 2968 /* vfnmad.d */, VE::VFNMADDrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5856 | | { 2968 /* vfnmad.d */, VE::VFNMADDvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5857 | | { 2968 /* vfnmad.d */, VE::VFNMADDvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5858 | | { 2968 /* vfnmad.d */, VE::VFNMADDvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5859 | | { 2968 /* vfnmad.d */, VE::VFNMADDivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5860 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDrvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64 }, }, |
5861 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDvrv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64 }, }, |
5862 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDvvv, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64 }, }, |
5863 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDviv, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5864 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDivv, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64 }, }, |
5865 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDrvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_V64, MCK_VM }, }, |
5866 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDvrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5867 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDvvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5868 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDvivm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5869 | | { 2977 /* vfnmsb.d */, VE::VFNMSBDivvm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_V64, MCK_VM }, }, |
5870 | | { 2986 /* vfrmax.d.fst */, VE::VFRMAXDFSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5871 | | { 2986 /* vfrmax.d.fst */, VE::VFRMAXDFSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5872 | | { 2999 /* vfrmax.d.lst */, VE::VFRMAXDLSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5873 | | { 2999 /* vfrmax.d.lst */, VE::VFRMAXDLSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5874 | | { 3012 /* vfrmax.s.fst */, VE::VFRMAXSFSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5875 | | { 3012 /* vfrmax.s.fst */, VE::VFRMAXSFSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5876 | | { 3025 /* vfrmax.s.lst */, VE::VFRMAXSLSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5877 | | { 3025 /* vfrmax.s.lst */, VE::VFRMAXSLSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5878 | | { 3038 /* vfrmin.d.fst */, VE::VFRMINDFSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5879 | | { 3038 /* vfrmin.d.fst */, VE::VFRMINDFSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5880 | | { 3051 /* vfrmin.d.lst */, VE::VFRMINDLSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5881 | | { 3051 /* vfrmin.d.lst */, VE::VFRMINDLSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5882 | | { 3064 /* vfrmin.s.fst */, VE::VFRMINSFSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5883 | | { 3064 /* vfrmin.s.fst */, VE::VFRMINSFSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5884 | | { 3077 /* vfrmin.s.lst */, VE::VFRMINSLSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5885 | | { 3077 /* vfrmin.s.lst */, VE::VFRMINSLSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5886 | | { 3090 /* vfsqrt.d */, VE::VFSQRTDv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5887 | | { 3090 /* vfsqrt.d */, VE::VFSQRTDvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5888 | | { 3099 /* vfsqrt.s */, VE::VFSQRTSv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5889 | | { 3099 /* vfsqrt.s */, VE::VFSQRTSvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5890 | | { 3108 /* vfsub.d */, VE::VFSUBDrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
5891 | | { 3108 /* vfsub.d */, VE::VFSUBDvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
5892 | | { 3108 /* vfsub.d */, VE::VFSUBDiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
5893 | | { 3108 /* vfsub.d */, VE::VFSUBDrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
5894 | | { 3108 /* vfsub.d */, VE::VFSUBDvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
5895 | | { 3108 /* vfsub.d */, VE::VFSUBDivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
5896 | | { 3116 /* vfsum.d */, VE::VFSUMDv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5897 | | { 3116 /* vfsum.d */, VE::VFSUMDvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5898 | | { 3124 /* vfsum.s */, VE::VFSUMSv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
5899 | | { 3124 /* vfsum.s */, VE::VFSUMSvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
5900 | | { 3132 /* vgt */, VE::VGTsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5901 | | { 3132 /* vgt */, VE::VGTsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5902 | | { 3132 /* vgt */, VE::VGTsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5903 | | { 3132 /* vgt */, VE::VGTsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5904 | | { 3132 /* vgt */, VE::VGTvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
5905 | | { 3132 /* vgt */, VE::VGTvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
5906 | | { 3132 /* vgt */, VE::VGTvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
5907 | | { 3132 /* vgt */, VE::VGTviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
5908 | | { 3132 /* vgt */, VE::VGTsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
5909 | | { 3132 /* vgt */, VE::VGTsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5910 | | { 3132 /* vgt */, VE::VGTsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5911 | | { 3132 /* vgt */, VE::VGTsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5912 | | { 3132 /* vgt */, VE::VGTvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
5913 | | { 3132 /* vgt */, VE::VGTvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5914 | | { 3132 /* vgt */, VE::VGTvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5915 | | { 3132 /* vgt */, VE::VGTvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5916 | | { 3136 /* vgt.nc */, VE::VGTNCsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5917 | | { 3136 /* vgt.nc */, VE::VGTNCsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5918 | | { 3136 /* vgt.nc */, VE::VGTNCsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5919 | | { 3136 /* vgt.nc */, VE::VGTNCsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5920 | | { 3136 /* vgt.nc */, VE::VGTNCvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
5921 | | { 3136 /* vgt.nc */, VE::VGTNCvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
5922 | | { 3136 /* vgt.nc */, VE::VGTNCvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
5923 | | { 3136 /* vgt.nc */, VE::VGTNCviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
5924 | | { 3136 /* vgt.nc */, VE::VGTNCsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
5925 | | { 3136 /* vgt.nc */, VE::VGTNCsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5926 | | { 3136 /* vgt.nc */, VE::VGTNCsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5927 | | { 3136 /* vgt.nc */, VE::VGTNCsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5928 | | { 3136 /* vgt.nc */, VE::VGTNCvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
5929 | | { 3136 /* vgt.nc */, VE::VGTNCvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5930 | | { 3136 /* vgt.nc */, VE::VGTNCvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5931 | | { 3136 /* vgt.nc */, VE::VGTNCvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5932 | | { 3143 /* vgtl.sx */, VE::VGTLSXsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5933 | | { 3143 /* vgtl.sx */, VE::VGTLSXsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5934 | | { 3143 /* vgtl.sx */, VE::VGTLSXsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5935 | | { 3143 /* vgtl.sx */, VE::VGTLSXsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5936 | | { 3143 /* vgtl.sx */, VE::VGTLSXvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
5937 | | { 3143 /* vgtl.sx */, VE::VGTLSXvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
5938 | | { 3143 /* vgtl.sx */, VE::VGTLSXvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
5939 | | { 3143 /* vgtl.sx */, VE::VGTLSXviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
5940 | | { 3143 /* vgtl.sx */, VE::VGTLSXsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
5941 | | { 3143 /* vgtl.sx */, VE::VGTLSXsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5942 | | { 3143 /* vgtl.sx */, VE::VGTLSXsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5943 | | { 3143 /* vgtl.sx */, VE::VGTLSXsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5944 | | { 3143 /* vgtl.sx */, VE::VGTLSXvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
5945 | | { 3143 /* vgtl.sx */, VE::VGTLSXvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5946 | | { 3143 /* vgtl.sx */, VE::VGTLSXvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5947 | | { 3143 /* vgtl.sx */, VE::VGTLSXvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5948 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5949 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5950 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5951 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5952 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
5953 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
5954 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
5955 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
5956 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
5957 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5958 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5959 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5960 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
5961 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5962 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5963 | | { 3151 /* vgtl.sx.nc */, VE::VGTLSXNCvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5964 | | { 3162 /* vgtl.zx */, VE::VGTLZXsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5965 | | { 3162 /* vgtl.zx */, VE::VGTLZXsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5966 | | { 3162 /* vgtl.zx */, VE::VGTLZXsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5967 | | { 3162 /* vgtl.zx */, VE::VGTLZXsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5968 | | { 3162 /* vgtl.zx */, VE::VGTLZXvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
5969 | | { 3162 /* vgtl.zx */, VE::VGTLZXvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
5970 | | { 3162 /* vgtl.zx */, VE::VGTLZXvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
5971 | | { 3162 /* vgtl.zx */, VE::VGTLZXviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
5972 | | { 3162 /* vgtl.zx */, VE::VGTLZXsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
5973 | | { 3162 /* vgtl.zx */, VE::VGTLZXsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5974 | | { 3162 /* vgtl.zx */, VE::VGTLZXsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5975 | | { 3162 /* vgtl.zx */, VE::VGTLZXsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5976 | | { 3162 /* vgtl.zx */, VE::VGTLZXvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
5977 | | { 3162 /* vgtl.zx */, VE::VGTLZXvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5978 | | { 3162 /* vgtl.zx */, VE::VGTLZXvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5979 | | { 3162 /* vgtl.zx */, VE::VGTLZXvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5980 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5981 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5982 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5983 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
5984 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
5985 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
5986 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
5987 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
5988 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
5989 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5990 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5991 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5992 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
5993 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
5994 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
5995 | | { 3170 /* vgtl.zx.nc */, VE::VGTLZXNCvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
5996 | | { 3181 /* vgtu */, VE::VGTUsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
5997 | | { 3181 /* vgtu */, VE::VGTUsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
5998 | | { 3181 /* vgtu */, VE::VGTUsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
5999 | | { 3181 /* vgtu */, VE::VGTUsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6000 | | { 3181 /* vgtu */, VE::VGTUvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6001 | | { 3181 /* vgtu */, VE::VGTUvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6002 | | { 3181 /* vgtu */, VE::VGTUvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6003 | | { 3181 /* vgtu */, VE::VGTUviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6004 | | { 3181 /* vgtu */, VE::VGTUsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6005 | | { 3181 /* vgtu */, VE::VGTUsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6006 | | { 3181 /* vgtu */, VE::VGTUsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6007 | | { 3181 /* vgtu */, VE::VGTUsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6008 | | { 3181 /* vgtu */, VE::VGTUvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6009 | | { 3181 /* vgtu */, VE::VGTUvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6010 | | { 3181 /* vgtu */, VE::VGTUvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6011 | | { 3181 /* vgtu */, VE::VGTUvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6012 | | { 3186 /* vgtu.nc */, VE::VGTUNCsrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6013 | | { 3186 /* vgtu.nc */, VE::VGTUNCsrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6014 | | { 3186 /* vgtu.nc */, VE::VGTUNCsir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6015 | | { 3186 /* vgtu.nc */, VE::VGTUNCsiz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6016 | | { 3186 /* vgtu.nc */, VE::VGTUNCvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6017 | | { 3186 /* vgtu.nc */, VE::VGTUNCvrz, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6018 | | { 3186 /* vgtu.nc */, VE::VGTUNCvir, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6019 | | { 3186 /* vgtu.nc */, VE::VGTUNCviz, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6020 | | { 3186 /* vgtu.nc */, VE::VGTUNCsrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6021 | | { 3186 /* vgtu.nc */, VE::VGTUNCsrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6022 | | { 3186 /* vgtu.nc */, VE::VGTUNCsirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6023 | | { 3186 /* vgtu.nc */, VE::VGTUNCsizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6024 | | { 3186 /* vgtu.nc */, VE::VGTUNCvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6025 | | { 3186 /* vgtu.nc */, VE::VGTUNCvrzm, Convert__Reg1_0__Reg1_1__Reg1_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6026 | | { 3186 /* vgtu.nc */, VE::VGTUNCvirm, Convert__Reg1_0__Reg1_1__SImm71_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6027 | | { 3186 /* vgtu.nc */, VE::VGTUNCvizm, Convert__Reg1_0__Reg1_1__SImm71_2__Zero1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6028 | | { 3194 /* vld */, VE::VLDrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6029 | | { 3194 /* vld */, VE::VLDrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6030 | | { 3194 /* vld */, VE::VLDir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6031 | | { 3194 /* vld */, VE::VLDiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6032 | | { 3198 /* vld.nc */, VE::VLDNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6033 | | { 3198 /* vld.nc */, VE::VLDNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6034 | | { 3198 /* vld.nc */, VE::VLDNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6035 | | { 3198 /* vld.nc */, VE::VLDNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6036 | | { 3205 /* vld2d */, VE::VLD2Drr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6037 | | { 3205 /* vld2d */, VE::VLD2Drz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6038 | | { 3205 /* vld2d */, VE::VLD2Dir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6039 | | { 3205 /* vld2d */, VE::VLD2Diz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6040 | | { 3211 /* vld2d.nc */, VE::VLD2DNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6041 | | { 3211 /* vld2d.nc */, VE::VLD2DNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6042 | | { 3211 /* vld2d.nc */, VE::VLD2DNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6043 | | { 3211 /* vld2d.nc */, VE::VLD2DNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6044 | | { 3220 /* vldl.sx */, VE::VLDLSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6045 | | { 3220 /* vldl.sx */, VE::VLDLSXrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6046 | | { 3220 /* vldl.sx */, VE::VLDLSXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6047 | | { 3220 /* vldl.sx */, VE::VLDLSXiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6048 | | { 3228 /* vldl.sx.nc */, VE::VLDLSXNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6049 | | { 3228 /* vldl.sx.nc */, VE::VLDLSXNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6050 | | { 3228 /* vldl.sx.nc */, VE::VLDLSXNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6051 | | { 3228 /* vldl.sx.nc */, VE::VLDLSXNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6052 | | { 3239 /* vldl.zx */, VE::VLDLZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6053 | | { 3239 /* vldl.zx */, VE::VLDLZXrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6054 | | { 3239 /* vldl.zx */, VE::VLDLZXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6055 | | { 3239 /* vldl.zx */, VE::VLDLZXiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6056 | | { 3247 /* vldl.zx.nc */, VE::VLDLZXNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6057 | | { 3247 /* vldl.zx.nc */, VE::VLDLZXNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6058 | | { 3247 /* vldl.zx.nc */, VE::VLDLZXNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6059 | | { 3247 /* vldl.zx.nc */, VE::VLDLZXNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6060 | | { 3258 /* vldl2d.sx */, VE::VLDL2DSXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6061 | | { 3258 /* vldl2d.sx */, VE::VLDL2DSXrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6062 | | { 3258 /* vldl2d.sx */, VE::VLDL2DSXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6063 | | { 3258 /* vldl2d.sx */, VE::VLDL2DSXiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6064 | | { 3268 /* vldl2d.sx.nc */, VE::VLDL2DSXNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6065 | | { 3268 /* vldl2d.sx.nc */, VE::VLDL2DSXNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6066 | | { 3268 /* vldl2d.sx.nc */, VE::VLDL2DSXNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6067 | | { 3268 /* vldl2d.sx.nc */, VE::VLDL2DSXNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6068 | | { 3281 /* vldl2d.zx */, VE::VLDL2DZXrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6069 | | { 3281 /* vldl2d.zx */, VE::VLDL2DZXrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6070 | | { 3281 /* vldl2d.zx */, VE::VLDL2DZXir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6071 | | { 3281 /* vldl2d.zx */, VE::VLDL2DZXiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6072 | | { 3291 /* vldl2d.zx.nc */, VE::VLDL2DZXNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6073 | | { 3291 /* vldl2d.zx.nc */, VE::VLDL2DZXNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6074 | | { 3291 /* vldl2d.zx.nc */, VE::VLDL2DZXNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6075 | | { 3291 /* vldl2d.zx.nc */, VE::VLDL2DZXNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6076 | | { 3304 /* vldu */, VE::VLDUrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6077 | | { 3304 /* vldu */, VE::VLDUrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6078 | | { 3304 /* vldu */, VE::VLDUir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6079 | | { 3304 /* vldu */, VE::VLDUiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6080 | | { 3309 /* vldu.nc */, VE::VLDUNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6081 | | { 3309 /* vldu.nc */, VE::VLDUNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6082 | | { 3309 /* vldu.nc */, VE::VLDUNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6083 | | { 3309 /* vldu.nc */, VE::VLDUNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6084 | | { 3317 /* vldu2d */, VE::VLDU2Drr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6085 | | { 3317 /* vldu2d */, VE::VLDU2Drz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6086 | | { 3317 /* vldu2d */, VE::VLDU2Dir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6087 | | { 3317 /* vldu2d */, VE::VLDU2Diz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6088 | | { 3324 /* vldu2d.nc */, VE::VLDU2DNCrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6089 | | { 3324 /* vldu2d.nc */, VE::VLDU2DNCrz, Convert__Reg1_0__Reg1_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6090 | | { 3324 /* vldu2d.nc */, VE::VLDU2DNCir, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6091 | | { 3324 /* vldu2d.nc */, VE::VLDU2DNCiz, Convert__Reg1_0__SImm71_1__Zero1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6092 | | { 3334 /* vldz */, VE::VLDZv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6093 | | { 3334 /* vldz */, VE::VLDZvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6094 | | { 3339 /* vmaxs.l */, VE::VMAXSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6095 | | { 3339 /* vmaxs.l */, VE::VMAXSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6096 | | { 3339 /* vmaxs.l */, VE::VMAXSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6097 | | { 3339 /* vmaxs.l */, VE::VMAXSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6098 | | { 3339 /* vmaxs.l */, VE::VMAXSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6099 | | { 3339 /* vmaxs.l */, VE::VMAXSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6100 | | { 3347 /* vmaxs.w.sx */, VE::VMAXSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6101 | | { 3347 /* vmaxs.w.sx */, VE::VMAXSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6102 | | { 3347 /* vmaxs.w.sx */, VE::VMAXSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6103 | | { 3347 /* vmaxs.w.sx */, VE::VMAXSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6104 | | { 3347 /* vmaxs.w.sx */, VE::VMAXSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6105 | | { 3347 /* vmaxs.w.sx */, VE::VMAXSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6106 | | { 3358 /* vmins.l */, VE::VMINSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6107 | | { 3358 /* vmins.l */, VE::VMINSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6108 | | { 3358 /* vmins.l */, VE::VMINSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6109 | | { 3358 /* vmins.l */, VE::VMINSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6110 | | { 3358 /* vmins.l */, VE::VMINSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6111 | | { 3358 /* vmins.l */, VE::VMINSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6112 | | { 3366 /* vmins.w.sx */, VE::VMINSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6113 | | { 3366 /* vmins.w.sx */, VE::VMINSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6114 | | { 3366 /* vmins.w.sx */, VE::VMINSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6115 | | { 3366 /* vmins.w.sx */, VE::VMINSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6116 | | { 3366 /* vmins.w.sx */, VE::VMINSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6117 | | { 3366 /* vmins.w.sx */, VE::VMINSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6118 | | { 3377 /* vmrg */, VE::VMRGrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6119 | | { 3377 /* vmrg */, VE::VMRGvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6120 | | { 3377 /* vmrg */, VE::VMRGiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6121 | | { 3377 /* vmrg */, VE::VMRGrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6122 | | { 3377 /* vmrg */, VE::VMRGvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6123 | | { 3377 /* vmrg */, VE::VMRGivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6124 | | { 3382 /* vmrg.w */, VE::VMRGWrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6125 | | { 3382 /* vmrg.w */, VE::VMRGWvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6126 | | { 3382 /* vmrg.w */, VE::VMRGWiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6127 | | { 3382 /* vmrg.w */, VE::VMRGWrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM512 }, }, |
6128 | | { 3382 /* vmrg.w */, VE::VMRGWvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM512 }, }, |
6129 | | { 3382 /* vmrg.w */, VE::VMRGWivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM512 }, }, |
6130 | | { 3389 /* vmuls.l */, VE::VMULSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6131 | | { 3389 /* vmuls.l */, VE::VMULSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6132 | | { 3389 /* vmuls.l */, VE::VMULSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6133 | | { 3389 /* vmuls.l */, VE::VMULSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6134 | | { 3389 /* vmuls.l */, VE::VMULSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6135 | | { 3389 /* vmuls.l */, VE::VMULSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6136 | | { 3397 /* vmuls.l.w */, VE::VMULSLWrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6137 | | { 3397 /* vmuls.l.w */, VE::VMULSLWvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6138 | | { 3397 /* vmuls.l.w */, VE::VMULSLWiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6139 | | { 3397 /* vmuls.l.w */, VE::VMULSLWrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6140 | | { 3397 /* vmuls.l.w */, VE::VMULSLWvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6141 | | { 3397 /* vmuls.l.w */, VE::VMULSLWivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6142 | | { 3407 /* vmuls.w.sx */, VE::VMULSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6143 | | { 3407 /* vmuls.w.sx */, VE::VMULSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6144 | | { 3407 /* vmuls.w.sx */, VE::VMULSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6145 | | { 3407 /* vmuls.w.sx */, VE::VMULSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6146 | | { 3407 /* vmuls.w.sx */, VE::VMULSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6147 | | { 3407 /* vmuls.w.sx */, VE::VMULSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6148 | | { 3418 /* vmuls.w.zx */, VE::VMULSWZXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6149 | | { 3418 /* vmuls.w.zx */, VE::VMULSWZXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6150 | | { 3418 /* vmuls.w.zx */, VE::VMULSWZXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6151 | | { 3418 /* vmuls.w.zx */, VE::VMULSWZXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6152 | | { 3418 /* vmuls.w.zx */, VE::VMULSWZXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6153 | | { 3418 /* vmuls.w.zx */, VE::VMULSWZXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6154 | | { 3429 /* vmulu.l */, VE::VMULULrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6155 | | { 3429 /* vmulu.l */, VE::VMULULvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6156 | | { 3429 /* vmulu.l */, VE::VMULULiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6157 | | { 3429 /* vmulu.l */, VE::VMULULrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6158 | | { 3429 /* vmulu.l */, VE::VMULULvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6159 | | { 3429 /* vmulu.l */, VE::VMULULivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6160 | | { 3437 /* vmulu.w */, VE::VMULUWrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6161 | | { 3437 /* vmulu.w */, VE::VMULUWvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6162 | | { 3437 /* vmulu.w */, VE::VMULUWiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6163 | | { 3437 /* vmulu.w */, VE::VMULUWrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6164 | | { 3437 /* vmulu.w */, VE::VMULUWvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6165 | | { 3437 /* vmulu.w */, VE::VMULUWivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6166 | | { 3445 /* vmv */, VE::VMVrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6167 | | { 3445 /* vmv */, VE::VMViv, Convert__Reg1_0__UImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_UImm7, MCK_V64 }, }, |
6168 | | { 3445 /* vmv */, VE::VMVrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6169 | | { 3445 /* vmv */, VE::VMVivm, Convert__Reg1_0__UImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_UImm7, MCK_V64, MCK_VM }, }, |
6170 | | { 3449 /* vor */, VE::VORrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6171 | | { 3449 /* vor */, VE::VORvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6172 | | { 3449 /* vor */, VE::VORmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
6173 | | { 3449 /* vor */, VE::VORrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6174 | | { 3449 /* vor */, VE::VORvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6175 | | { 3449 /* vor */, VE::VORmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
6176 | | { 3453 /* vpcnt */, VE::VPCNTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6177 | | { 3453 /* vpcnt */, VE::VPCNTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6178 | | { 3459 /* vrand */, VE::VRANDv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6179 | | { 3459 /* vrand */, VE::VRANDvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6180 | | { 3465 /* vrcp.d */, VE::VRCPDv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6181 | | { 3465 /* vrcp.d */, VE::VRCPDvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6182 | | { 3472 /* vrmaxs.l.fst */, VE::VRMAXSLFSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6183 | | { 3472 /* vrmaxs.l.fst */, VE::VRMAXSLFSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6184 | | { 3485 /* vrmaxs.l.lst */, VE::VRMAXSLLSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6185 | | { 3485 /* vrmaxs.l.lst */, VE::VRMAXSLLSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6186 | | { 3498 /* vrmaxs.w.fst.sx */, VE::VRMAXSWFSTSXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6187 | | { 3498 /* vrmaxs.w.fst.sx */, VE::VRMAXSWFSTSXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6188 | | { 3514 /* vrmaxs.w.fst.zx */, VE::VRMAXSWFSTZXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6189 | | { 3514 /* vrmaxs.w.fst.zx */, VE::VRMAXSWFSTZXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6190 | | { 3530 /* vrmaxs.w.lst.sx */, VE::VRMAXSWLSTSXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6191 | | { 3530 /* vrmaxs.w.lst.sx */, VE::VRMAXSWLSTSXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6192 | | { 3546 /* vrmaxs.w.lst.zx */, VE::VRMAXSWLSTZXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6193 | | { 3546 /* vrmaxs.w.lst.zx */, VE::VRMAXSWLSTZXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6194 | | { 3562 /* vrmins.l.fst */, VE::VRMINSLFSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6195 | | { 3562 /* vrmins.l.fst */, VE::VRMINSLFSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6196 | | { 3575 /* vrmins.l.lst */, VE::VRMINSLLSTv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6197 | | { 3575 /* vrmins.l.lst */, VE::VRMINSLLSTvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6198 | | { 3588 /* vrmins.w.fst.sx */, VE::VRMINSWFSTSXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6199 | | { 3588 /* vrmins.w.fst.sx */, VE::VRMINSWFSTSXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6200 | | { 3604 /* vrmins.w.fst.zx */, VE::VRMINSWFSTZXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6201 | | { 3604 /* vrmins.w.fst.zx */, VE::VRMINSWFSTZXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6202 | | { 3620 /* vrmins.w.lst.sx */, VE::VRMINSWLSTSXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6203 | | { 3620 /* vrmins.w.lst.sx */, VE::VRMINSWLSTSXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6204 | | { 3636 /* vrmins.w.lst.zx */, VE::VRMINSWLSTZXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6205 | | { 3636 /* vrmins.w.lst.zx */, VE::VRMINSWLSTZXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6206 | | { 3652 /* vror */, VE::VRORv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6207 | | { 3652 /* vror */, VE::VRORvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6208 | | { 3657 /* vrsqrt.d */, VE::VRSQRTDv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6209 | | { 3657 /* vrsqrt.d */, VE::VRSQRTDvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6210 | | { 3666 /* vrsqrt.d.nex */, VE::VRSQRTDNEXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6211 | | { 3666 /* vrsqrt.d.nex */, VE::VRSQRTDNEXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6212 | | { 3679 /* vrxor */, VE::VRXORv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6213 | | { 3679 /* vrxor */, VE::VRXORvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6214 | | { 3685 /* vsc */, VE::VSCsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6215 | | { 3685 /* vsc */, VE::VSCsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6216 | | { 3685 /* vsc */, VE::VSCsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6217 | | { 3685 /* vsc */, VE::VSCsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6218 | | { 3685 /* vsc */, VE::VSCvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6219 | | { 3685 /* vsc */, VE::VSCvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6220 | | { 3685 /* vsc */, VE::VSCvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6221 | | { 3685 /* vsc */, VE::VSCvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6222 | | { 3685 /* vsc */, VE::VSCsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6223 | | { 3685 /* vsc */, VE::VSCsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6224 | | { 3685 /* vsc */, VE::VSCsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6225 | | { 3685 /* vsc */, VE::VSCsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6226 | | { 3685 /* vsc */, VE::VSCvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6227 | | { 3685 /* vsc */, VE::VSCvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6228 | | { 3685 /* vsc */, VE::VSCvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6229 | | { 3685 /* vsc */, VE::VSCvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6230 | | { 3689 /* vsc.nc */, VE::VSCNCsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6231 | | { 3689 /* vsc.nc */, VE::VSCNCsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6232 | | { 3689 /* vsc.nc */, VE::VSCNCsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6233 | | { 3689 /* vsc.nc */, VE::VSCNCsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6234 | | { 3689 /* vsc.nc */, VE::VSCNCvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6235 | | { 3689 /* vsc.nc */, VE::VSCNCvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6236 | | { 3689 /* vsc.nc */, VE::VSCNCvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6237 | | { 3689 /* vsc.nc */, VE::VSCNCvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6238 | | { 3689 /* vsc.nc */, VE::VSCNCsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6239 | | { 3689 /* vsc.nc */, VE::VSCNCsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6240 | | { 3689 /* vsc.nc */, VE::VSCNCsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6241 | | { 3689 /* vsc.nc */, VE::VSCNCsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6242 | | { 3689 /* vsc.nc */, VE::VSCNCvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6243 | | { 3689 /* vsc.nc */, VE::VSCNCvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6244 | | { 3689 /* vsc.nc */, VE::VSCNCvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6245 | | { 3689 /* vsc.nc */, VE::VSCNCvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6246 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6247 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6248 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6249 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6250 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6251 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6252 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6253 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6254 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6255 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6256 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6257 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6258 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6259 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6260 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6261 | | { 3696 /* vsc.nc.ot */, VE::VSCNCOTvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6262 | | { 3706 /* vsc.ot */, VE::VSCOTsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6263 | | { 3706 /* vsc.ot */, VE::VSCOTsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6264 | | { 3706 /* vsc.ot */, VE::VSCOTsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6265 | | { 3706 /* vsc.ot */, VE::VSCOTsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6266 | | { 3706 /* vsc.ot */, VE::VSCOTvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6267 | | { 3706 /* vsc.ot */, VE::VSCOTvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6268 | | { 3706 /* vsc.ot */, VE::VSCOTvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6269 | | { 3706 /* vsc.ot */, VE::VSCOTvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6270 | | { 3706 /* vsc.ot */, VE::VSCOTsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6271 | | { 3706 /* vsc.ot */, VE::VSCOTsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6272 | | { 3706 /* vsc.ot */, VE::VSCOTsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6273 | | { 3706 /* vsc.ot */, VE::VSCOTsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6274 | | { 3706 /* vsc.ot */, VE::VSCOTvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6275 | | { 3706 /* vsc.ot */, VE::VSCOTvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6276 | | { 3706 /* vsc.ot */, VE::VSCOTvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6277 | | { 3706 /* vsc.ot */, VE::VSCOTvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6278 | | { 3713 /* vscl */, VE::VSCLsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6279 | | { 3713 /* vscl */, VE::VSCLsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6280 | | { 3713 /* vscl */, VE::VSCLsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6281 | | { 3713 /* vscl */, VE::VSCLsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6282 | | { 3713 /* vscl */, VE::VSCLvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6283 | | { 3713 /* vscl */, VE::VSCLvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6284 | | { 3713 /* vscl */, VE::VSCLvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6285 | | { 3713 /* vscl */, VE::VSCLvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6286 | | { 3713 /* vscl */, VE::VSCLsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6287 | | { 3713 /* vscl */, VE::VSCLsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6288 | | { 3713 /* vscl */, VE::VSCLsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6289 | | { 3713 /* vscl */, VE::VSCLsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6290 | | { 3713 /* vscl */, VE::VSCLvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6291 | | { 3713 /* vscl */, VE::VSCLvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6292 | | { 3713 /* vscl */, VE::VSCLvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6293 | | { 3713 /* vscl */, VE::VSCLvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6294 | | { 3718 /* vscl.nc */, VE::VSCLNCsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6295 | | { 3718 /* vscl.nc */, VE::VSCLNCsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6296 | | { 3718 /* vscl.nc */, VE::VSCLNCsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6297 | | { 3718 /* vscl.nc */, VE::VSCLNCsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6298 | | { 3718 /* vscl.nc */, VE::VSCLNCvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6299 | | { 3718 /* vscl.nc */, VE::VSCLNCvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6300 | | { 3718 /* vscl.nc */, VE::VSCLNCvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6301 | | { 3718 /* vscl.nc */, VE::VSCLNCvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6302 | | { 3718 /* vscl.nc */, VE::VSCLNCsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6303 | | { 3718 /* vscl.nc */, VE::VSCLNCsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6304 | | { 3718 /* vscl.nc */, VE::VSCLNCsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6305 | | { 3718 /* vscl.nc */, VE::VSCLNCsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6306 | | { 3718 /* vscl.nc */, VE::VSCLNCvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6307 | | { 3718 /* vscl.nc */, VE::VSCLNCvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6308 | | { 3718 /* vscl.nc */, VE::VSCLNCvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6309 | | { 3718 /* vscl.nc */, VE::VSCLNCvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6310 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6311 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6312 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6313 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6314 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6315 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6316 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6317 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6318 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6319 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6320 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6321 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6322 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6323 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6324 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6325 | | { 3726 /* vscl.nc.ot */, VE::VSCLNCOTvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6326 | | { 3737 /* vscl.ot */, VE::VSCLOTsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6327 | | { 3737 /* vscl.ot */, VE::VSCLOTsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6328 | | { 3737 /* vscl.ot */, VE::VSCLOTsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6329 | | { 3737 /* vscl.ot */, VE::VSCLOTsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6330 | | { 3737 /* vscl.ot */, VE::VSCLOTvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6331 | | { 3737 /* vscl.ot */, VE::VSCLOTvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6332 | | { 3737 /* vscl.ot */, VE::VSCLOTvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6333 | | { 3737 /* vscl.ot */, VE::VSCLOTvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6334 | | { 3737 /* vscl.ot */, VE::VSCLOTsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6335 | | { 3737 /* vscl.ot */, VE::VSCLOTsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6336 | | { 3737 /* vscl.ot */, VE::VSCLOTsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6337 | | { 3737 /* vscl.ot */, VE::VSCLOTsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6338 | | { 3737 /* vscl.ot */, VE::VSCLOTvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6339 | | { 3737 /* vscl.ot */, VE::VSCLOTvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6340 | | { 3737 /* vscl.ot */, VE::VSCLOTvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6341 | | { 3737 /* vscl.ot */, VE::VSCLOTvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6342 | | { 3745 /* vscu */, VE::VSCUsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6343 | | { 3745 /* vscu */, VE::VSCUsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6344 | | { 3745 /* vscu */, VE::VSCUsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6345 | | { 3745 /* vscu */, VE::VSCUsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6346 | | { 3745 /* vscu */, VE::VSCUvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6347 | | { 3745 /* vscu */, VE::VSCUvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6348 | | { 3745 /* vscu */, VE::VSCUvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6349 | | { 3745 /* vscu */, VE::VSCUvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6350 | | { 3745 /* vscu */, VE::VSCUsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6351 | | { 3745 /* vscu */, VE::VSCUsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6352 | | { 3745 /* vscu */, VE::VSCUsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6353 | | { 3745 /* vscu */, VE::VSCUsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6354 | | { 3745 /* vscu */, VE::VSCUvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6355 | | { 3745 /* vscu */, VE::VSCUvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6356 | | { 3745 /* vscu */, VE::VSCUvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6357 | | { 3745 /* vscu */, VE::VSCUvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6358 | | { 3750 /* vscu.nc */, VE::VSCUNCsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6359 | | { 3750 /* vscu.nc */, VE::VSCUNCsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6360 | | { 3750 /* vscu.nc */, VE::VSCUNCsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6361 | | { 3750 /* vscu.nc */, VE::VSCUNCsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6362 | | { 3750 /* vscu.nc */, VE::VSCUNCvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6363 | | { 3750 /* vscu.nc */, VE::VSCUNCvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6364 | | { 3750 /* vscu.nc */, VE::VSCUNCvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6365 | | { 3750 /* vscu.nc */, VE::VSCUNCvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6366 | | { 3750 /* vscu.nc */, VE::VSCUNCsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6367 | | { 3750 /* vscu.nc */, VE::VSCUNCsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6368 | | { 3750 /* vscu.nc */, VE::VSCUNCsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6369 | | { 3750 /* vscu.nc */, VE::VSCUNCsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6370 | | { 3750 /* vscu.nc */, VE::VSCUNCvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6371 | | { 3750 /* vscu.nc */, VE::VSCUNCvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6372 | | { 3750 /* vscu.nc */, VE::VSCUNCvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6373 | | { 3750 /* vscu.nc */, VE::VSCUNCvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6374 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6375 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6376 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6377 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6378 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6379 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6380 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6381 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6382 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6383 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6384 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6385 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6386 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6387 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6388 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6389 | | { 3758 /* vscu.nc.ot */, VE::VSCUNCOTvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6390 | | { 3769 /* vscu.ot */, VE::VSCUOTsrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64 }, }, |
6391 | | { 3769 /* vscu.ot */, VE::VSCUOTsrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero }, }, |
6392 | | { 3769 /* vscu.ot */, VE::VSCUOTsirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6393 | | { 3769 /* vscu.ot */, VE::VSCUOTsizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero }, }, |
6394 | | { 3769 /* vscu.ot */, VE::VSCUOTvrrv, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6395 | | { 3769 /* vscu.ot */, VE::VSCUOTvrzv, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero }, }, |
6396 | | { 3769 /* vscu.ot */, VE::VSCUOTvirv, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6397 | | { 3769 /* vscu.ot */, VE::VSCUOTvizv, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6398 | | { 3769 /* vscu.ot */, VE::VSCUOTsrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_I64, MCK_VM }, }, |
6399 | | { 3769 /* vscu.ot */, VE::VSCUOTsrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6400 | | { 3769 /* vscu.ot */, VE::VSCUOTsirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6401 | | { 3769 /* vscu.ot */, VE::VSCUOTsizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_I64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6402 | | { 3769 /* vscu.ot */, VE::VSCUOTvrrvm, Convert__Reg1_1__Reg1_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6403 | | { 3769 /* vscu.ot */, VE::VSCUOTvrzvm, Convert__Reg1_1__Reg1_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6404 | | { 3769 /* vscu.ot */, VE::VSCUOTvirvm, Convert__Reg1_1__SImm71_2__Reg1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6405 | | { 3769 /* vscu.ot */, VE::VSCUOTvizvm, Convert__Reg1_1__SImm71_2__Zero1_3__Reg1_0__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6406 | | { 3777 /* vseq */, VE::VSEQ, Convert__Reg1_0, AMFBS_None, { MCK_V64 }, }, |
6407 | | { 3777 /* vseq */, VE::VSEQm, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_VM }, }, |
6408 | | { 3782 /* vsfa */, VE::VSFAvrr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64 }, }, |
6409 | | { 3782 /* vsfa */, VE::VSFAvrm, Convert__Reg1_0__Reg1_1__Reg1_2__MImm1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_MImm }, }, |
6410 | | { 3782 /* vsfa */, VE::VSFAvir, Convert__Reg1_0__Reg1_1__UImm31_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm3, MCK_I64 }, }, |
6411 | | { 3782 /* vsfa */, VE::VSFAvim, Convert__Reg1_0__Reg1_1__UImm31_2__MImm1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm3, MCK_MImm }, }, |
6412 | | { 3782 /* vsfa */, VE::VSFAvrrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6413 | | { 3782 /* vsfa */, VE::VSFAvrmm, Convert__Reg1_0__Reg1_1__Reg1_2__MImm1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_MImm, MCK_VM }, }, |
6414 | | { 3782 /* vsfa */, VE::VSFAvirm, Convert__Reg1_0__Reg1_1__UImm31_2__Reg1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm3, MCK_I64, MCK_VM }, }, |
6415 | | { 3782 /* vsfa */, VE::VSFAvimm, Convert__Reg1_0__Reg1_1__UImm31_2__MImm1_3__Reg1_4, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm3, MCK_MImm, MCK_VM }, }, |
6416 | | { 3787 /* vshf */, VE::VSHFvvr, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_I64 }, }, |
6417 | | { 3787 /* vshf */, VE::VSHFvvi, Convert__Reg1_0__Reg1_1__Reg1_2__UImm41_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_UImm4 }, }, |
6418 | | { 3792 /* vsla.l */, VE::VSLALvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
6419 | | { 3792 /* vsla.l */, VE::VSLALvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6420 | | { 3792 /* vsla.l */, VE::VSLALvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
6421 | | { 3792 /* vsla.l */, VE::VSLALvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
6422 | | { 3792 /* vsla.l */, VE::VSLALvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6423 | | { 3792 /* vsla.l */, VE::VSLALvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
6424 | | { 3799 /* vsla.w.sx */, VE::VSLAWSXvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
6425 | | { 3799 /* vsla.w.sx */, VE::VSLAWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6426 | | { 3799 /* vsla.w.sx */, VE::VSLAWSXvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
6427 | | { 3799 /* vsla.w.sx */, VE::VSLAWSXvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
6428 | | { 3799 /* vsla.w.sx */, VE::VSLAWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6429 | | { 3799 /* vsla.w.sx */, VE::VSLAWSXvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
6430 | | { 3809 /* vsld */, VE::VSLDvvr, Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_I64 }, }, |
6431 | | { 3809 /* vsld */, VE::VSLDvvi, Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_UImm7 }, }, |
6432 | | { 3809 /* vsld */, VE::VSLDvvrm, Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5__Reg1_6, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_I64, MCK_VM }, }, |
6433 | | { 3809 /* vsld */, VE::VSLDvvim, Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5__Reg1_6, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_UImm7, MCK_VM }, }, |
6434 | | { 3814 /* vsll */, VE::VSLLvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
6435 | | { 3814 /* vsll */, VE::VSLLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6436 | | { 3814 /* vsll */, VE::VSLLvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
6437 | | { 3814 /* vsll */, VE::VSLLvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
6438 | | { 3814 /* vsll */, VE::VSLLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6439 | | { 3814 /* vsll */, VE::VSLLvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
6440 | | { 3819 /* vsra.l */, VE::VSRALvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
6441 | | { 3819 /* vsra.l */, VE::VSRALvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6442 | | { 3819 /* vsra.l */, VE::VSRALvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
6443 | | { 3819 /* vsra.l */, VE::VSRALvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
6444 | | { 3819 /* vsra.l */, VE::VSRALvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6445 | | { 3819 /* vsra.l */, VE::VSRALvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
6446 | | { 3826 /* vsra.w.sx */, VE::VSRAWSXvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32 }, }, |
6447 | | { 3826 /* vsra.w.sx */, VE::VSRAWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6448 | | { 3826 /* vsra.w.sx */, VE::VSRAWSXvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
6449 | | { 3826 /* vsra.w.sx */, VE::VSRAWSXvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I32, MCK_VM }, }, |
6450 | | { 3826 /* vsra.w.sx */, VE::VSRAWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6451 | | { 3826 /* vsra.w.sx */, VE::VSRAWSXvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
6452 | | { 3836 /* vsrd */, VE::VSRDvvr, Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_I64 }, }, |
6453 | | { 3836 /* vsrd */, VE::VSRDvvi, Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_UImm7 }, }, |
6454 | | { 3836 /* vsrd */, VE::VSRDvvrm, Convert__Reg1_0__Reg1_2__Reg1_3__Reg1_5__Reg1_6, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_I64, MCK_VM }, }, |
6455 | | { 3836 /* vsrd */, VE::VSRDvvim, Convert__Reg1_0__Reg1_2__Reg1_3__UImm71_5__Reg1_6, AMFBS_None, { MCK_V64, MCK__40_, MCK_V64, MCK_V64, MCK__41_, MCK_UImm7, MCK_VM }, }, |
6456 | | { 3841 /* vsrl */, VE::VSRLvr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64 }, }, |
6457 | | { 3841 /* vsrl */, VE::VSRLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6458 | | { 3841 /* vsrl */, VE::VSRLvi, Convert__Reg1_0__Reg1_1__UImm71_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7 }, }, |
6459 | | { 3841 /* vsrl */, VE::VSRLvrm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_I64, MCK_VM }, }, |
6460 | | { 3841 /* vsrl */, VE::VSRLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6461 | | { 3841 /* vsrl */, VE::VSRLvim, Convert__Reg1_0__Reg1_1__UImm71_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_UImm7, MCK_VM }, }, |
6462 | | { 3846 /* vst */, VE::VSTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6463 | | { 3846 /* vst */, VE::VSTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6464 | | { 3846 /* vst */, VE::VSTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6465 | | { 3846 /* vst */, VE::VSTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6466 | | { 3846 /* vst */, VE::VSTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6467 | | { 3846 /* vst */, VE::VSTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6468 | | { 3846 /* vst */, VE::VSTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6469 | | { 3846 /* vst */, VE::VSTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6470 | | { 3850 /* vst.nc */, VE::VSTNCrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6471 | | { 3850 /* vst.nc */, VE::VSTNCrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6472 | | { 3850 /* vst.nc */, VE::VSTNCirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6473 | | { 3850 /* vst.nc */, VE::VSTNCizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6474 | | { 3850 /* vst.nc */, VE::VSTNCrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6475 | | { 3850 /* vst.nc */, VE::VSTNCrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6476 | | { 3850 /* vst.nc */, VE::VSTNCirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6477 | | { 3850 /* vst.nc */, VE::VSTNCizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6478 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6479 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6480 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6481 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6482 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6483 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6484 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6485 | | { 3857 /* vst.nc.ot */, VE::VSTNCOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6486 | | { 3867 /* vst.ot */, VE::VSTOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6487 | | { 3867 /* vst.ot */, VE::VSTOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6488 | | { 3867 /* vst.ot */, VE::VSTOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6489 | | { 3867 /* vst.ot */, VE::VSTOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6490 | | { 3867 /* vst.ot */, VE::VSTOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6491 | | { 3867 /* vst.ot */, VE::VSTOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6492 | | { 3867 /* vst.ot */, VE::VSTOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6493 | | { 3867 /* vst.ot */, VE::VSTOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6494 | | { 3874 /* vst2d */, VE::VST2Drrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6495 | | { 3874 /* vst2d */, VE::VST2Drzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6496 | | { 3874 /* vst2d */, VE::VST2Dirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6497 | | { 3874 /* vst2d */, VE::VST2Dizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6498 | | { 3874 /* vst2d */, VE::VST2Drrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6499 | | { 3874 /* vst2d */, VE::VST2Drzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6500 | | { 3874 /* vst2d */, VE::VST2Dirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6501 | | { 3874 /* vst2d */, VE::VST2Dizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6502 | | { 3880 /* vst2d.nc */, VE::VST2DNCrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6503 | | { 3880 /* vst2d.nc */, VE::VST2DNCrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6504 | | { 3880 /* vst2d.nc */, VE::VST2DNCirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6505 | | { 3880 /* vst2d.nc */, VE::VST2DNCizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6506 | | { 3880 /* vst2d.nc */, VE::VST2DNCrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6507 | | { 3880 /* vst2d.nc */, VE::VST2DNCrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6508 | | { 3880 /* vst2d.nc */, VE::VST2DNCirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6509 | | { 3880 /* vst2d.nc */, VE::VST2DNCizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6510 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6511 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6512 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6513 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6514 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6515 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6516 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6517 | | { 3889 /* vst2d.nc.ot */, VE::VST2DNCOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6518 | | { 3901 /* vst2d.ot */, VE::VST2DOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6519 | | { 3901 /* vst2d.ot */, VE::VST2DOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6520 | | { 3901 /* vst2d.ot */, VE::VST2DOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6521 | | { 3901 /* vst2d.ot */, VE::VST2DOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6522 | | { 3901 /* vst2d.ot */, VE::VST2DOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6523 | | { 3901 /* vst2d.ot */, VE::VST2DOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6524 | | { 3901 /* vst2d.ot */, VE::VST2DOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6525 | | { 3901 /* vst2d.ot */, VE::VST2DOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6526 | | { 3910 /* vstl */, VE::VSTLrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6527 | | { 3910 /* vstl */, VE::VSTLrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6528 | | { 3910 /* vstl */, VE::VSTLirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6529 | | { 3910 /* vstl */, VE::VSTLizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6530 | | { 3910 /* vstl */, VE::VSTLrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6531 | | { 3910 /* vstl */, VE::VSTLrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6532 | | { 3910 /* vstl */, VE::VSTLirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6533 | | { 3910 /* vstl */, VE::VSTLizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6534 | | { 3915 /* vstl.nc */, VE::VSTLNCrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6535 | | { 3915 /* vstl.nc */, VE::VSTLNCrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6536 | | { 3915 /* vstl.nc */, VE::VSTLNCirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6537 | | { 3915 /* vstl.nc */, VE::VSTLNCizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6538 | | { 3915 /* vstl.nc */, VE::VSTLNCrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6539 | | { 3915 /* vstl.nc */, VE::VSTLNCrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6540 | | { 3915 /* vstl.nc */, VE::VSTLNCirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6541 | | { 3915 /* vstl.nc */, VE::VSTLNCizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6542 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6543 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6544 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6545 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6546 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6547 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6548 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6549 | | { 3923 /* vstl.nc.ot */, VE::VSTLNCOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6550 | | { 3934 /* vstl.ot */, VE::VSTLOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6551 | | { 3934 /* vstl.ot */, VE::VSTLOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6552 | | { 3934 /* vstl.ot */, VE::VSTLOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6553 | | { 3934 /* vstl.ot */, VE::VSTLOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6554 | | { 3934 /* vstl.ot */, VE::VSTLOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6555 | | { 3934 /* vstl.ot */, VE::VSTLOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6556 | | { 3934 /* vstl.ot */, VE::VSTLOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6557 | | { 3934 /* vstl.ot */, VE::VSTLOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6558 | | { 3942 /* vstl2d */, VE::VSTL2Drrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6559 | | { 3942 /* vstl2d */, VE::VSTL2Drzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6560 | | { 3942 /* vstl2d */, VE::VSTL2Dirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6561 | | { 3942 /* vstl2d */, VE::VSTL2Dizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6562 | | { 3942 /* vstl2d */, VE::VSTL2Drrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6563 | | { 3942 /* vstl2d */, VE::VSTL2Drzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6564 | | { 3942 /* vstl2d */, VE::VSTL2Dirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6565 | | { 3942 /* vstl2d */, VE::VSTL2Dizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6566 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6567 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6568 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6569 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6570 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6571 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6572 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6573 | | { 3949 /* vstl2d.nc */, VE::VSTL2DNCizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6574 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6575 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6576 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6577 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6578 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6579 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6580 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6581 | | { 3959 /* vstl2d.nc.ot */, VE::VSTL2DNCOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6582 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6583 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6584 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6585 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6586 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6587 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6588 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6589 | | { 3972 /* vstl2d.ot */, VE::VSTL2DOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6590 | | { 3982 /* vstu */, VE::VSTUrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6591 | | { 3982 /* vstu */, VE::VSTUrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6592 | | { 3982 /* vstu */, VE::VSTUirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6593 | | { 3982 /* vstu */, VE::VSTUizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6594 | | { 3982 /* vstu */, VE::VSTUrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6595 | | { 3982 /* vstu */, VE::VSTUrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6596 | | { 3982 /* vstu */, VE::VSTUirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6597 | | { 3982 /* vstu */, VE::VSTUizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6598 | | { 3987 /* vstu.nc */, VE::VSTUNCrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6599 | | { 3987 /* vstu.nc */, VE::VSTUNCrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6600 | | { 3987 /* vstu.nc */, VE::VSTUNCirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6601 | | { 3987 /* vstu.nc */, VE::VSTUNCizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6602 | | { 3987 /* vstu.nc */, VE::VSTUNCrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6603 | | { 3987 /* vstu.nc */, VE::VSTUNCrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6604 | | { 3987 /* vstu.nc */, VE::VSTUNCirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6605 | | { 3987 /* vstu.nc */, VE::VSTUNCizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6606 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6607 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6608 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6609 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6610 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6611 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6612 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6613 | | { 3995 /* vstu.nc.ot */, VE::VSTUNCOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6614 | | { 4006 /* vstu.ot */, VE::VSTUOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6615 | | { 4006 /* vstu.ot */, VE::VSTUOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6616 | | { 4006 /* vstu.ot */, VE::VSTUOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6617 | | { 4006 /* vstu.ot */, VE::VSTUOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6618 | | { 4006 /* vstu.ot */, VE::VSTUOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6619 | | { 4006 /* vstu.ot */, VE::VSTUOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6620 | | { 4006 /* vstu.ot */, VE::VSTUOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6621 | | { 4006 /* vstu.ot */, VE::VSTUOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6622 | | { 4014 /* vstu2d */, VE::VSTU2Drrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6623 | | { 4014 /* vstu2d */, VE::VSTU2Drzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6624 | | { 4014 /* vstu2d */, VE::VSTU2Dirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6625 | | { 4014 /* vstu2d */, VE::VSTU2Dizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6626 | | { 4014 /* vstu2d */, VE::VSTU2Drrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6627 | | { 4014 /* vstu2d */, VE::VSTU2Drzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6628 | | { 4014 /* vstu2d */, VE::VSTU2Dirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6629 | | { 4014 /* vstu2d */, VE::VSTU2Dizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6630 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6631 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6632 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6633 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6634 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6635 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6636 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6637 | | { 4021 /* vstu2d.nc */, VE::VSTU2DNCizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6638 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6639 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6640 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6641 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6642 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6643 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6644 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6645 | | { 4031 /* vstu2d.nc.ot */, VE::VSTU2DNCOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6646 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTrrv, Convert__Reg1_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64 }, }, |
6647 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTrzv, Convert__Reg1_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero }, }, |
6648 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTirv, Convert__SImm71_1__Reg1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64 }, }, |
6649 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTizv, Convert__SImm71_1__Zero1_2__Reg1_0, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero }, }, |
6650 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTrrvm, Convert__Reg1_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_I64, MCK_VM }, }, |
6651 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTrzvm, Convert__Reg1_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_Zero, MCK_VM }, }, |
6652 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTirvm, Convert__SImm71_1__Reg1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_I64, MCK_VM }, }, |
6653 | | { 4044 /* vstu2d.ot */, VE::VSTU2DOTizvm, Convert__SImm71_1__Zero1_2__Reg1_0__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_Zero, MCK_VM }, }, |
6654 | | { 4054 /* vsubs.l */, VE::VSUBSLrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6655 | | { 4054 /* vsubs.l */, VE::VSUBSLvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6656 | | { 4054 /* vsubs.l */, VE::VSUBSLiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6657 | | { 4054 /* vsubs.l */, VE::VSUBSLrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6658 | | { 4054 /* vsubs.l */, VE::VSUBSLvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6659 | | { 4054 /* vsubs.l */, VE::VSUBSLivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6660 | | { 4062 /* vsubs.w.sx */, VE::VSUBSWSXrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64 }, }, |
6661 | | { 4062 /* vsubs.w.sx */, VE::VSUBSWSXvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6662 | | { 4062 /* vsubs.w.sx */, VE::VSUBSWSXiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6663 | | { 4062 /* vsubs.w.sx */, VE::VSUBSWSXrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I32, MCK_V64, MCK_VM }, }, |
6664 | | { 4062 /* vsubs.w.sx */, VE::VSUBSWSXvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6665 | | { 4062 /* vsubs.w.sx */, VE::VSUBSWSXivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6666 | | { 4073 /* vsubu.l */, VE::VSUBULrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6667 | | { 4073 /* vsubu.l */, VE::VSUBULvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6668 | | { 4073 /* vsubu.l */, VE::VSUBULiv, Convert__Reg1_0__SImm71_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64 }, }, |
6669 | | { 4073 /* vsubu.l */, VE::VSUBULrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6670 | | { 4073 /* vsubu.l */, VE::VSUBULvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6671 | | { 4073 /* vsubu.l */, VE::VSUBULivm, Convert__Reg1_0__SImm71_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_SImm7, MCK_V64, MCK_VM }, }, |
6672 | | { 4081 /* vsum.l */, VE::VSUMLv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6673 | | { 4081 /* vsum.l */, VE::VSUMLvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6674 | | { 4088 /* vsum.w.sx */, VE::VSUMWSXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6675 | | { 4088 /* vsum.w.sx */, VE::VSUMWSXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6676 | | { 4098 /* vsum.w.zx */, VE::VSUMWZXv, Convert__Reg1_0__Reg1_1, AMFBS_None, { MCK_V64, MCK_V64 }, }, |
6677 | | { 4098 /* vsum.w.zx */, VE::VSUMWZXvm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_VM }, }, |
6678 | | { 4108 /* vxor */, VE::VXORrv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64 }, }, |
6679 | | { 4108 /* vxor */, VE::VXORvv, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64 }, }, |
6680 | | { 4108 /* vxor */, VE::VXORmv, Convert__Reg1_0__MImm1_1__Reg1_2, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64 }, }, |
6681 | | { 4108 /* vxor */, VE::VXORrvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_I64, MCK_V64, MCK_VM }, }, |
6682 | | { 4108 /* vxor */, VE::VXORvvm, Convert__Reg1_0__Reg1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_V64, MCK_V64, MCK_VM }, }, |
6683 | | { 4108 /* vxor */, VE::VXORmvm, Convert__Reg1_0__MImm1_1__Reg1_2__Reg1_3, AMFBS_None, { MCK_V64, MCK_MImm, MCK_V64, MCK_VM }, }, |
6684 | | { 4113 /* xor */, VE::XORrr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_I64 }, }, |
6685 | | { 4113 /* xor */, VE::XORrm, Convert__Reg1_0__Reg1_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_I64, MCK_MImm }, }, |
6686 | | { 4113 /* xor */, VE::XORri, Convert__Reg1_0__Reg1_2__SImm71_1, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_I64 }, }, |
6687 | | { 4113 /* xor */, VE::XORim, Convert__Reg1_0__SImm71_1__MImm1_2, AMFBS_None, { MCK_I64, MCK_SImm7, MCK_MImm }, }, |
6688 | | { 4117 /* xorm */, VE::XORMmm, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_VM, MCK_VM, MCK_VM }, }, |
6689 | | }; |
6690 | | |
6691 | | #include "llvm/Support/Debug.h" |
6692 | | #include "llvm/Support/Format.h" |
6693 | | |
6694 | | unsigned VEAsmParser:: |
6695 | | MatchInstructionImpl(const OperandVector &Operands, |
6696 | | MCInst &Inst, |
6697 | | uint64_t &ErrorInfo, |
6698 | | FeatureBitset &MissingFeatures, |
6699 | 0 | bool matchingInlineAsm, unsigned VariantID) { |
6700 | | // Eliminate obvious mismatches. |
6701 | 0 | if (Operands.size() > 8) { |
6702 | 0 | ErrorInfo = 8; |
6703 | 0 | return Match_InvalidOperand; |
6704 | 0 | } |
6705 | | |
6706 | | // Get the current feature set. |
6707 | 0 | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); |
6708 | | |
6709 | | // Get the instruction mnemonic, which is the first token. |
6710 | 0 | StringRef Mnemonic = ((VEOperand &)*Operands[0]).getToken(); |
6711 | | |
6712 | | // Process all MnemonicAliases to remap the mnemonic. |
6713 | 0 | applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); |
6714 | | |
6715 | | // Some state to try to produce better error messages. |
6716 | 0 | bool HadMatchOtherThanFeatures = false; |
6717 | 0 | bool HadMatchOtherThanPredicate = false; |
6718 | 0 | unsigned RetCode = Match_InvalidOperand; |
6719 | 0 | MissingFeatures.set(); |
6720 | | // Set ErrorInfo to the operand that mismatches if it is |
6721 | | // wrong for all instances of the instruction. |
6722 | 0 | ErrorInfo = ~0ULL; |
6723 | | // Find the appropriate table for this asm variant. |
6724 | 0 | const MatchEntry *Start, *End; |
6725 | 0 | switch (VariantID) { |
6726 | 0 | default: llvm_unreachable("invalid variant!"); |
6727 | 0 | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
6728 | 0 | } |
6729 | | // Search the table. |
6730 | 0 | auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); |
6731 | |
|
6732 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << |
6733 | 0 | std::distance(MnemonicRange.first, MnemonicRange.second) << |
6734 | 0 | " encodings with mnemonic '" << Mnemonic << "'\n"); |
6735 | | |
6736 | | // Return a more specific error code if no mnemonics match. |
6737 | 0 | if (MnemonicRange.first == MnemonicRange.second) |
6738 | 0 | return Match_MnemonicFail; |
6739 | | |
6740 | 0 | for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; |
6741 | 0 | it != ie; ++it) { |
6742 | 0 | const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; |
6743 | 0 | bool HasRequiredFeatures = |
6744 | 0 | (AvailableFeatures & RequiredFeatures) == RequiredFeatures; |
6745 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " |
6746 | 0 | << MII.getName(it->Opcode) << "\n"); |
6747 | | // equal_range guarantees that instruction mnemonic matches. |
6748 | 0 | assert(Mnemonic == it->getMnemonic()); |
6749 | 0 | bool OperandsValid = true; |
6750 | 0 | for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 7; ++FormalIdx) { |
6751 | 0 | auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); |
6752 | 0 | DEBUG_WITH_TYPE("asm-matcher", |
6753 | 0 | dbgs() << " Matching formal operand class " << getMatchClassName(Formal) |
6754 | 0 | << " against actual operand at index " << ActualIdx); |
6755 | 0 | if (ActualIdx < Operands.size()) |
6756 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; |
6757 | 0 | Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); |
6758 | 0 | else |
6759 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); |
6760 | 0 | if (ActualIdx >= Operands.size()) { |
6761 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range\n"); |
6762 | 0 | if (Formal == InvalidMatchClass) { |
6763 | 0 | break; |
6764 | 0 | } |
6765 | 0 | if (isSubclass(Formal, OptionalMatchClass)) { |
6766 | 0 | continue; |
6767 | 0 | } |
6768 | 0 | OperandsValid = false; |
6769 | 0 | ErrorInfo = ActualIdx; |
6770 | 0 | break; |
6771 | 0 | } |
6772 | 0 | MCParsedAsmOperand &Actual = *Operands[ActualIdx]; |
6773 | 0 | unsigned Diag = validateOperandClass(Actual, Formal); |
6774 | 0 | if (Diag == Match_Success) { |
6775 | 0 | DEBUG_WITH_TYPE("asm-matcher", |
6776 | 0 | dbgs() << "match success using generic matcher\n"); |
6777 | 0 | ++ActualIdx; |
6778 | 0 | continue; |
6779 | 0 | } |
6780 | | // If the generic handler indicates an invalid operand |
6781 | | // failure, check for a special case. |
6782 | 0 | if (Diag != Match_Success) { |
6783 | 0 | unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); |
6784 | 0 | if (TargetDiag == Match_Success) { |
6785 | 0 | DEBUG_WITH_TYPE("asm-matcher", |
6786 | 0 | dbgs() << "match success using target matcher\n"); |
6787 | 0 | ++ActualIdx; |
6788 | 0 | continue; |
6789 | 0 | } |
6790 | | // If the target matcher returned a specific error code use |
6791 | | // that, else use the one from the generic matcher. |
6792 | 0 | if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) |
6793 | 0 | Diag = TargetDiag; |
6794 | 0 | } |
6795 | | // If current formal operand wasn't matched and it is optional |
6796 | | // then try to match next formal operand |
6797 | 0 | if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { |
6798 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); |
6799 | 0 | continue; |
6800 | 0 | } |
6801 | | // If this operand is broken for all of the instances of this |
6802 | | // mnemonic, keep track of it so we can report loc info. |
6803 | | // If we already had a match that only failed due to a |
6804 | | // target predicate, that diagnostic is preferred. |
6805 | 0 | if (!HadMatchOtherThanPredicate && |
6806 | 0 | (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { |
6807 | 0 | if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand)) |
6808 | 0 | RetCode = Diag; |
6809 | 0 | ErrorInfo = ActualIdx; |
6810 | 0 | } |
6811 | | // Otherwise, just reject this instance of the mnemonic. |
6812 | 0 | OperandsValid = false; |
6813 | 0 | break; |
6814 | 0 | } |
6815 | |
|
6816 | 0 | if (!OperandsValid) { |
6817 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " |
6818 | 0 | "operand mismatches, ignoring " |
6819 | 0 | "this opcode\n"); |
6820 | 0 | continue; |
6821 | 0 | } |
6822 | 0 | if (!HasRequiredFeatures) { |
6823 | 0 | HadMatchOtherThanFeatures = true; |
6824 | 0 | FeatureBitset NewMissingFeatures = RequiredFeatures & ~AvailableFeatures; |
6825 | 0 | DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features:"; |
6826 | 0 | for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I) |
6827 | 0 | if (NewMissingFeatures[I]) |
6828 | 0 | dbgs() << ' ' << I; |
6829 | 0 | dbgs() << "\n"); |
6830 | 0 | if (NewMissingFeatures.count() <= |
6831 | 0 | MissingFeatures.count()) |
6832 | 0 | MissingFeatures = NewMissingFeatures; |
6833 | 0 | continue; |
6834 | 0 | } |
6835 | | |
6836 | 0 | Inst.clear(); |
6837 | |
|
6838 | 0 | Inst.setOpcode(it->Opcode); |
6839 | | // We have a potential match but have not rendered the operands. |
6840 | | // Check the target predicate to handle any context sensitive |
6841 | | // constraints. |
6842 | | // For example, Ties that are referenced multiple times must be |
6843 | | // checked here to ensure the input is the same for each match |
6844 | | // constraints. If we leave it any later the ties will have been |
6845 | | // canonicalized |
6846 | 0 | unsigned MatchResult; |
6847 | 0 | if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { |
6848 | 0 | Inst.clear(); |
6849 | 0 | DEBUG_WITH_TYPE( |
6850 | 0 | "asm-matcher", |
6851 | 0 | dbgs() << "Early target match predicate failed with diag code " |
6852 | 0 | << MatchResult << "\n"); |
6853 | 0 | RetCode = MatchResult; |
6854 | 0 | HadMatchOtherThanPredicate = true; |
6855 | 0 | continue; |
6856 | 0 | } |
6857 | | |
6858 | 0 | if (matchingInlineAsm) { |
6859 | 0 | convertToMapAndConstraints(it->ConvertFn, Operands); |
6860 | 0 | if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) |
6861 | 0 | return Match_InvalidTiedOperand; |
6862 | | |
6863 | 0 | return Match_Success; |
6864 | 0 | } |
6865 | | |
6866 | | // We have selected a definite instruction, convert the parsed |
6867 | | // operands into the appropriate MCInst. |
6868 | 0 | convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); |
6869 | | |
6870 | | // We have a potential match. Check the target predicate to |
6871 | | // handle any context sensitive constraints. |
6872 | 0 | if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { |
6873 | 0 | DEBUG_WITH_TYPE("asm-matcher", |
6874 | 0 | dbgs() << "Target match predicate failed with diag code " |
6875 | 0 | << MatchResult << "\n"); |
6876 | 0 | Inst.clear(); |
6877 | 0 | RetCode = MatchResult; |
6878 | 0 | HadMatchOtherThanPredicate = true; |
6879 | 0 | continue; |
6880 | 0 | } |
6881 | | |
6882 | 0 | if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) |
6883 | 0 | return Match_InvalidTiedOperand; |
6884 | | |
6885 | 0 | DEBUG_WITH_TYPE( |
6886 | 0 | "asm-matcher", |
6887 | 0 | dbgs() << "Opcode result: complete match, selecting this opcode\n"); |
6888 | 0 | return Match_Success; |
6889 | 0 | } |
6890 | | |
6891 | | // Okay, we had no match. Try to return a useful error code. |
6892 | 0 | if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) |
6893 | 0 | return RetCode; |
6894 | | |
6895 | 0 | ErrorInfo = 0; |
6896 | 0 | return Match_MissingFeature; |
6897 | 0 | } |
6898 | | |
6899 | | namespace { |
6900 | | struct OperandMatchEntry { |
6901 | | uint16_t Mnemonic; |
6902 | | uint8_t OperandMask; |
6903 | | uint8_t Class; |
6904 | | uint8_t RequiredFeaturesIdx; |
6905 | | |
6906 | 0 | StringRef getMnemonic() const { |
6907 | 0 | return StringRef(MnemonicTable + Mnemonic + 1, |
6908 | 0 | MnemonicTable[Mnemonic]); |
6909 | 0 | } |
6910 | | }; |
6911 | | |
6912 | | // Predicate for searching for an opcode. |
6913 | | struct LessOpcodeOperand { |
6914 | 0 | bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { |
6915 | 0 | return LHS.getMnemonic() < RHS; |
6916 | 0 | } |
6917 | 0 | bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { |
6918 | 0 | return LHS < RHS.getMnemonic(); |
6919 | 0 | } |
6920 | 0 | bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { |
6921 | 0 | return LHS.getMnemonic() < RHS.getMnemonic(); |
6922 | 0 | } |
6923 | | }; |
6924 | | } // end anonymous namespace |
6925 | | |
6926 | | static const OperandMatchEntry OperandMatchTable[408] = { |
6927 | | /* Operand List Mnemonic, Mask, Operand Class, Features */ |
6928 | | { 0 /* adds.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6929 | | { 0 /* adds.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6930 | | { 7 /* adds.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6931 | | { 7 /* adds.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6932 | | { 17 /* adds.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6933 | | { 17 /* adds.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6934 | | { 27 /* addu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6935 | | { 27 /* addu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6936 | | { 34 /* addu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6937 | | { 34 /* addu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6938 | | { 41 /* and */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6939 | | { 41 /* and */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
6940 | | { 50 /* atmam */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
6941 | | { 50 /* atmam */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
6942 | | { 50 /* atmam */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
6943 | | { 50 /* atmam */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
6944 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6945 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6946 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6947 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6948 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6949 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6950 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6951 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6952 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6953 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6954 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6955 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6956 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6957 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6958 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6959 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6960 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6961 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6962 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6963 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6964 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6965 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6966 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6967 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6968 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6969 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6970 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6971 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6972 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6973 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6974 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6975 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6976 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6977 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6978 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6979 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6980 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6981 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6982 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6983 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6984 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6985 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6986 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6987 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6988 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6989 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6990 | | { 56 /* b */, 8 /* 3 */, MCK_MEMri, AMFBS_None }, |
6991 | | { 56 /* b */, 8 /* 3 */, MCK_MEMzi, AMFBS_None }, |
6992 | | { 58 /* b.d */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
6993 | | { 58 /* b.d */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
6994 | | { 62 /* b.d.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
6995 | | { 62 /* b.d.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
6996 | | { 69 /* b.d.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
6997 | | { 69 /* b.d.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
6998 | | { 75 /* b.l */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
6999 | | { 75 /* b.l */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7000 | | { 79 /* b.l.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7001 | | { 79 /* b.l.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7002 | | { 86 /* b.l.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7003 | | { 86 /* b.l.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7004 | | { 92 /* b.s */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7005 | | { 92 /* b.s */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7006 | | { 96 /* b.s.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7007 | | { 96 /* b.s.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7008 | | { 103 /* b.s.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7009 | | { 103 /* b.s.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7010 | | { 109 /* b.w */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7011 | | { 109 /* b.w */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7012 | | { 113 /* b.w.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7013 | | { 113 /* b.w.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7014 | | { 120 /* b.w.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7015 | | { 120 /* b.w.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7016 | | { 126 /* baf.d */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7017 | | { 126 /* baf.d */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7018 | | { 132 /* baf.d.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7019 | | { 132 /* baf.d.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7020 | | { 141 /* baf.d.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7021 | | { 141 /* baf.d.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7022 | | { 149 /* baf.l */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7023 | | { 149 /* baf.l */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7024 | | { 155 /* baf.l.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7025 | | { 155 /* baf.l.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7026 | | { 164 /* baf.l.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7027 | | { 164 /* baf.l.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7028 | | { 172 /* baf.s */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7029 | | { 172 /* baf.s */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7030 | | { 178 /* baf.s.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7031 | | { 178 /* baf.s.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7032 | | { 187 /* baf.s.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7033 | | { 187 /* baf.s.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7034 | | { 195 /* baf.w */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7035 | | { 195 /* baf.w */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7036 | | { 201 /* baf.w.nt */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7037 | | { 201 /* baf.w.nt */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7038 | | { 210 /* baf.w.t */, 1 /* 0 */, MCK_MEMri, AMFBS_None }, |
7039 | | { 210 /* baf.w.t */, 1 /* 0 */, MCK_MEMzi, AMFBS_None }, |
7040 | | { 405 /* brv */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7041 | | { 409 /* bsic */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7042 | | { 409 /* bsic */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7043 | | { 409 /* bsic */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7044 | | { 409 /* bsic */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7045 | | { 414 /* bswp */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7046 | | { 419 /* cas.l */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7047 | | { 419 /* cas.l */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7048 | | { 419 /* cas.l */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7049 | | { 419 /* cas.l */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7050 | | { 425 /* cas.w */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7051 | | { 425 /* cas.w */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7052 | | { 425 /* cas.w */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7053 | | { 425 /* cas.w */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7054 | | { 431 /* cmov.d. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7055 | | { 431 /* cmov.d. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7056 | | { 439 /* cmov.l. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7057 | | { 439 /* cmov.l. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7058 | | { 447 /* cmov.s. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7059 | | { 447 /* cmov.s. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7060 | | { 455 /* cmov.w. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7061 | | { 455 /* cmov.w. */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7062 | | { 463 /* cmps.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7063 | | { 463 /* cmps.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7064 | | { 470 /* cmps.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7065 | | { 470 /* cmps.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7066 | | { 480 /* cmps.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7067 | | { 480 /* cmps.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7068 | | { 490 /* cmpu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7069 | | { 490 /* cmpu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7070 | | { 497 /* cmpu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7071 | | { 497 /* cmpu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7072 | | { 628 /* divs.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7073 | | { 628 /* divs.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7074 | | { 635 /* divs.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7075 | | { 635 /* divs.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7076 | | { 645 /* divs.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7077 | | { 645 /* divs.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7078 | | { 655 /* divu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7079 | | { 655 /* divu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7080 | | { 662 /* divu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7081 | | { 662 /* divu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7082 | | { 669 /* dld */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7083 | | { 669 /* dld */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7084 | | { 669 /* dld */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7085 | | { 669 /* dld */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7086 | | { 673 /* dldl.sx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7087 | | { 673 /* dldl.sx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7088 | | { 673 /* dldl.sx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7089 | | { 673 /* dldl.sx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7090 | | { 681 /* dldl.zx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7091 | | { 681 /* dldl.zx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7092 | | { 681 /* dldl.zx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7093 | | { 681 /* dldl.zx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7094 | | { 689 /* dldu */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7095 | | { 689 /* dldu */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7096 | | { 689 /* dldu */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7097 | | { 689 /* dldu */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7098 | | { 694 /* eqv */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7099 | | { 694 /* eqv */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7100 | | { 703 /* fadd.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7101 | | { 703 /* fadd.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7102 | | { 710 /* fadd.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7103 | | { 710 /* fadd.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7104 | | { 717 /* fadd.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7105 | | { 717 /* fadd.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7106 | | { 724 /* fcmp.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7107 | | { 724 /* fcmp.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7108 | | { 731 /* fcmp.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7109 | | { 731 /* fcmp.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7110 | | { 738 /* fcmp.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7111 | | { 738 /* fcmp.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7112 | | { 745 /* fdiv.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7113 | | { 745 /* fdiv.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7114 | | { 752 /* fdiv.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7115 | | { 752 /* fdiv.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7116 | | { 786 /* fmax.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7117 | | { 786 /* fmax.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7118 | | { 793 /* fmax.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7119 | | { 793 /* fmax.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7120 | | { 800 /* fmin.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7121 | | { 800 /* fmin.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7122 | | { 807 /* fmin.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7123 | | { 807 /* fmin.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7124 | | { 814 /* fmul.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7125 | | { 814 /* fmul.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7126 | | { 821 /* fmul.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7127 | | { 821 /* fmul.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7128 | | { 828 /* fmul.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7129 | | { 828 /* fmul.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7130 | | { 835 /* fsub.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7131 | | { 835 /* fsub.d */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7132 | | { 842 /* fsub.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7133 | | { 842 /* fsub.q */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7134 | | { 849 /* fsub.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7135 | | { 849 /* fsub.s */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7136 | | { 860 /* ld */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7137 | | { 860 /* ld */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7138 | | { 860 /* ld */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7139 | | { 860 /* ld */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7140 | | { 863 /* ld1b.sx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7141 | | { 863 /* ld1b.sx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7142 | | { 863 /* ld1b.sx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7143 | | { 863 /* ld1b.sx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7144 | | { 871 /* ld1b.zx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7145 | | { 871 /* ld1b.zx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7146 | | { 871 /* ld1b.zx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7147 | | { 871 /* ld1b.zx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7148 | | { 879 /* ld2b.sx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7149 | | { 879 /* ld2b.sx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7150 | | { 879 /* ld2b.sx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7151 | | { 879 /* ld2b.sx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7152 | | { 887 /* ld2b.zx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7153 | | { 887 /* ld2b.zx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7154 | | { 887 /* ld2b.zx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7155 | | { 887 /* ld2b.zx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7156 | | { 895 /* ldl.sx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7157 | | { 895 /* ldl.sx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7158 | | { 895 /* ldl.sx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7159 | | { 895 /* ldl.sx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7160 | | { 902 /* ldl.zx */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7161 | | { 902 /* ldl.zx */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7162 | | { 902 /* ldl.zx */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7163 | | { 902 /* ldl.zx */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7164 | | { 909 /* ldu */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7165 | | { 909 /* ldu */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7166 | | { 909 /* ldu */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7167 | | { 909 /* ldu */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7168 | | { 913 /* ldz */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7169 | | { 917 /* lea */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7170 | | { 917 /* lea */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7171 | | { 917 /* lea */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7172 | | { 917 /* lea */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7173 | | { 921 /* lea.sl */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7174 | | { 921 /* lea.sl */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7175 | | { 921 /* lea.sl */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7176 | | { 921 /* lea.sl */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7177 | | { 932 /* lhm.b */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7178 | | { 932 /* lhm.b */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7179 | | { 938 /* lhm.h */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7180 | | { 938 /* lhm.h */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7181 | | { 944 /* lhm.l */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7182 | | { 944 /* lhm.l */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7183 | | { 950 /* lhm.w */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7184 | | { 950 /* lhm.w */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7185 | | { 960 /* lsv */, 16 /* 4 */, MCK_MImm, AMFBS_None }, |
7186 | | { 960 /* lsv */, 16 /* 4 */, MCK_MImm, AMFBS_None }, |
7187 | | { 973 /* lvm */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7188 | | { 973 /* lvm */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7189 | | { 986 /* maxs.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7190 | | { 986 /* maxs.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7191 | | { 993 /* maxs.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7192 | | { 993 /* maxs.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7193 | | { 1003 /* maxs.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7194 | | { 1003 /* maxs.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7195 | | { 1013 /* mins.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7196 | | { 1013 /* mins.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7197 | | { 1020 /* mins.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7198 | | { 1020 /* mins.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7199 | | { 1030 /* mins.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7200 | | { 1030 /* mins.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7201 | | { 1054 /* mrg */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7202 | | { 1054 /* mrg */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7203 | | { 1058 /* muls.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7204 | | { 1058 /* muls.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7205 | | { 1065 /* muls.l.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7206 | | { 1065 /* muls.l.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7207 | | { 1074 /* muls.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7208 | | { 1074 /* muls.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7209 | | { 1084 /* muls.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7210 | | { 1084 /* muls.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7211 | | { 1094 /* mulu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7212 | | { 1094 /* mulu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7213 | | { 1101 /* mulu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7214 | | { 1101 /* mulu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7215 | | { 1113 /* nnd */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7216 | | { 1113 /* nnd */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7217 | | { 1126 /* or */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7218 | | { 1126 /* or */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7219 | | { 1133 /* pcnt */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7220 | | { 1143 /* pfch */, 1 /* 0 */, MCK_MEMrii, AMFBS_None }, |
7221 | | { 1143 /* pfch */, 1 /* 0 */, MCK_MEMrri, AMFBS_None }, |
7222 | | { 1143 /* pfch */, 1 /* 0 */, MCK_MEMzii, AMFBS_None }, |
7223 | | { 1143 /* pfch */, 1 /* 0 */, MCK_MEMzri, AMFBS_None }, |
7224 | | { 1217 /* pvand */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7225 | | { 1217 /* pvand */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7226 | | { 1223 /* pvand.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7227 | | { 1223 /* pvand.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7228 | | { 1232 /* pvand.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7229 | | { 1232 /* pvand.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7230 | | { 1397 /* pveqv */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7231 | | { 1397 /* pveqv */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7232 | | { 1403 /* pveqv.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7233 | | { 1403 /* pveqv.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7234 | | { 1412 /* pveqv.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7235 | | { 1412 /* pveqv.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7236 | | { 1895 /* pvor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7237 | | { 1895 /* pvor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7238 | | { 1900 /* pvor.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7239 | | { 1900 /* pvor.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7240 | | { 1908 /* pvor.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7241 | | { 1908 /* pvor.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7242 | | { 2213 /* pvxor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7243 | | { 2213 /* pvxor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7244 | | { 2219 /* pvxor.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7245 | | { 2219 /* pvxor.lo */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7246 | | { 2228 /* pvxor.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7247 | | { 2228 /* pvxor.up */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7248 | | { 2245 /* shm.b */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7249 | | { 2245 /* shm.b */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7250 | | { 2251 /* shm.h */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7251 | | { 2251 /* shm.h */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7252 | | { 2257 /* shm.l */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7253 | | { 2257 /* shm.l */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7254 | | { 2263 /* shm.w */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7255 | | { 2263 /* shm.w */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7256 | | { 2273 /* sla.l */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7257 | | { 2273 /* sla.l */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7258 | | { 2279 /* sla.w.sx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7259 | | { 2279 /* sla.w.sx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7260 | | { 2288 /* sla.w.zx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7261 | | { 2288 /* sla.w.zx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7262 | | { 2297 /* sld */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7263 | | { 2297 /* sld */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7264 | | { 2301 /* sll */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7265 | | { 2301 /* sll */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7266 | | { 2319 /* sra.l */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7267 | | { 2319 /* sra.l */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7268 | | { 2325 /* sra.w.sx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7269 | | { 2325 /* sra.w.sx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7270 | | { 2334 /* sra.w.zx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7271 | | { 2334 /* sra.w.zx */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7272 | | { 2343 /* srd */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7273 | | { 2343 /* srd */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7274 | | { 2347 /* srl */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7275 | | { 2347 /* srl */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7276 | | { 2351 /* st */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7277 | | { 2351 /* st */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7278 | | { 2351 /* st */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7279 | | { 2351 /* st */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7280 | | { 2354 /* st1b */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7281 | | { 2354 /* st1b */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7282 | | { 2354 /* st1b */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7283 | | { 2354 /* st1b */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7284 | | { 2359 /* st2b */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7285 | | { 2359 /* st2b */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7286 | | { 2359 /* st2b */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7287 | | { 2359 /* st2b */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7288 | | { 2364 /* stl */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7289 | | { 2364 /* stl */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7290 | | { 2364 /* stl */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7291 | | { 2364 /* stl */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7292 | | { 2368 /* stu */, 2 /* 1 */, MCK_MEMrii, AMFBS_None }, |
7293 | | { 2368 /* stu */, 2 /* 1 */, MCK_MEMrri, AMFBS_None }, |
7294 | | { 2368 /* stu */, 2 /* 1 */, MCK_MEMzii, AMFBS_None }, |
7295 | | { 2368 /* stu */, 2 /* 1 */, MCK_MEMzri, AMFBS_None }, |
7296 | | { 2372 /* subs.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7297 | | { 2372 /* subs.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7298 | | { 2379 /* subs.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7299 | | { 2379 /* subs.w.sx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7300 | | { 2389 /* subs.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7301 | | { 2389 /* subs.w.zx */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7302 | | { 2399 /* subu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7303 | | { 2399 /* subu.l */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7304 | | { 2406 /* subu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7305 | | { 2406 /* subu.w */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7306 | | { 2431 /* ts1am.l */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7307 | | { 2431 /* ts1am.l */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7308 | | { 2431 /* ts1am.l */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7309 | | { 2431 /* ts1am.l */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7310 | | { 2439 /* ts1am.w */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7311 | | { 2439 /* ts1am.w */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7312 | | { 2439 /* ts1am.w */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7313 | | { 2439 /* ts1am.w */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7314 | | { 2447 /* ts2am */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7315 | | { 2447 /* ts2am */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7316 | | { 2447 /* ts2am */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7317 | | { 2447 /* ts2am */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7318 | | { 2453 /* ts3am */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7319 | | { 2453 /* ts3am */, 2 /* 1 */, MCK_MEMri, AMFBS_None }, |
7320 | | { 2453 /* ts3am */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7321 | | { 2453 /* ts3am */, 2 /* 1 */, MCK_MEMzi, AMFBS_None }, |
7322 | | { 2491 /* vand */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7323 | | { 2491 /* vand */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7324 | | { 2697 /* veqv */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7325 | | { 2697 /* veqv */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7326 | | { 3449 /* vor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7327 | | { 3449 /* vor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7328 | | { 3782 /* vsfa */, 8 /* 3 */, MCK_MImm, AMFBS_None }, |
7329 | | { 3782 /* vsfa */, 8 /* 3 */, MCK_MImm, AMFBS_None }, |
7330 | | { 3782 /* vsfa */, 8 /* 3 */, MCK_MImm, AMFBS_None }, |
7331 | | { 3782 /* vsfa */, 8 /* 3 */, MCK_MImm, AMFBS_None }, |
7332 | | { 4108 /* vxor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7333 | | { 4108 /* vxor */, 2 /* 1 */, MCK_MImm, AMFBS_None }, |
7334 | | { 4113 /* xor */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7335 | | { 4113 /* xor */, 4 /* 2 */, MCK_MImm, AMFBS_None }, |
7336 | | }; |
7337 | | |
7338 | | ParseStatus VEAsmParser:: |
7339 | | tryCustomParseOperand(OperandVector &Operands, |
7340 | 0 | unsigned MCK) { |
7341 | |
|
7342 | 0 | switch(MCK) { |
7343 | 0 | case MCK_MImm: |
7344 | 0 | return parseMImmOperand(Operands); |
7345 | 0 | case MCK_MEMri: |
7346 | 0 | return parseMEMAsOperand(Operands); |
7347 | 0 | case MCK_MEMrii: |
7348 | 0 | return parseMEMOperand(Operands); |
7349 | 0 | case MCK_MEMrri: |
7350 | 0 | return parseMEMOperand(Operands); |
7351 | 0 | case MCK_MEMzi: |
7352 | 0 | return parseMEMAsOperand(Operands); |
7353 | 0 | case MCK_MEMzii: |
7354 | 0 | return parseMEMOperand(Operands); |
7355 | 0 | case MCK_MEMzri: |
7356 | 0 | return parseMEMOperand(Operands); |
7357 | 0 | default: |
7358 | 0 | return ParseStatus::NoMatch; |
7359 | 0 | } |
7360 | 0 | return ParseStatus::NoMatch; |
7361 | 0 | } |
7362 | | |
7363 | | ParseStatus VEAsmParser:: |
7364 | | MatchOperandParserImpl(OperandVector &Operands, |
7365 | | StringRef Mnemonic, |
7366 | 0 | bool ParseForAllFeatures) { |
7367 | | // Get the current feature set. |
7368 | 0 | const FeatureBitset &AvailableFeatures = getAvailableFeatures(); |
7369 | | |
7370 | | // Get the next operand index. |
7371 | 0 | unsigned NextOpNum = Operands.size() - 1; |
7372 | | // Search the table. |
7373 | 0 | auto MnemonicRange = |
7374 | 0 | std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), |
7375 | 0 | Mnemonic, LessOpcodeOperand()); |
7376 | |
|
7377 | 0 | if (MnemonicRange.first == MnemonicRange.second) |
7378 | 0 | return ParseStatus::NoMatch; |
7379 | | |
7380 | 0 | for (const OperandMatchEntry *it = MnemonicRange.first, |
7381 | 0 | *ie = MnemonicRange.second; it != ie; ++it) { |
7382 | | // equal_range guarantees that instruction mnemonic matches. |
7383 | 0 | assert(Mnemonic == it->getMnemonic()); |
7384 | | |
7385 | | // check if the available features match |
7386 | 0 | const FeatureBitset &RequiredFeatures = FeatureBitsets[it->RequiredFeaturesIdx]; |
7387 | 0 | if (!ParseForAllFeatures && (AvailableFeatures & RequiredFeatures) != RequiredFeatures) |
7388 | 0 | continue; |
7389 | | |
7390 | | // check if the operand in question has a custom parser. |
7391 | 0 | if (!(it->OperandMask & (1 << NextOpNum))) |
7392 | 0 | continue; |
7393 | | |
7394 | | // call custom parse method to handle the operand |
7395 | 0 | ParseStatus Result = tryCustomParseOperand(Operands, it->Class); |
7396 | 0 | if (!Result.isNoMatch()) |
7397 | 0 | return Result; |
7398 | 0 | } |
7399 | | |
7400 | | // Okay, we had no match. |
7401 | 0 | return ParseStatus::NoMatch; |
7402 | 0 | } |
7403 | | |
7404 | | #endif // GET_MATCHER_IMPLEMENTATION |
7405 | | |
7406 | | |
7407 | | #ifdef GET_MNEMONIC_SPELL_CHECKER |
7408 | | #undef GET_MNEMONIC_SPELL_CHECKER |
7409 | | |
7410 | | static std::string VEMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, unsigned VariantID) { |
7411 | | const unsigned MaxEditDist = 2; |
7412 | | std::vector<StringRef> Candidates; |
7413 | | StringRef Prev = ""; |
7414 | | |
7415 | | // Find the appropriate table for this asm variant. |
7416 | | const MatchEntry *Start, *End; |
7417 | | switch (VariantID) { |
7418 | | default: llvm_unreachable("invalid variant!"); |
7419 | | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
7420 | | } |
7421 | | |
7422 | | for (auto I = Start; I < End; I++) { |
7423 | | // Ignore unsupported instructions. |
7424 | | const FeatureBitset &RequiredFeatures = FeatureBitsets[I->RequiredFeaturesIdx]; |
7425 | | if ((FBS & RequiredFeatures) != RequiredFeatures) |
7426 | | continue; |
7427 | | |
7428 | | StringRef T = I->getMnemonic(); |
7429 | | // Avoid recomputing the edit distance for the same string. |
7430 | | if (T.equals(Prev)) |
7431 | | continue; |
7432 | | |
7433 | | Prev = T; |
7434 | | unsigned Dist = S.edit_distance(T, false, MaxEditDist); |
7435 | | if (Dist <= MaxEditDist) |
7436 | | Candidates.push_back(T); |
7437 | | } |
7438 | | |
7439 | | if (Candidates.empty()) |
7440 | | return ""; |
7441 | | |
7442 | | std::string Res = ", did you mean: "; |
7443 | | unsigned i = 0; |
7444 | | for (; i < Candidates.size() - 1; i++) |
7445 | | Res += Candidates[i].str() + ", "; |
7446 | | return Res + Candidates[i].str() + "?"; |
7447 | | } |
7448 | | |
7449 | | #endif // GET_MNEMONIC_SPELL_CHECKER |
7450 | | |
7451 | | |
7452 | | #ifdef GET_MNEMONIC_CHECKER |
7453 | | #undef GET_MNEMONIC_CHECKER |
7454 | | |
7455 | | static bool VECheckMnemonic(StringRef Mnemonic, |
7456 | | const FeatureBitset &AvailableFeatures, |
7457 | | unsigned VariantID) { |
7458 | | // Process all MnemonicAliases to remap the mnemonic. |
7459 | | applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID); |
7460 | | |
7461 | | // Find the appropriate table for this asm variant. |
7462 | | const MatchEntry *Start, *End; |
7463 | | switch (VariantID) { |
7464 | | default: llvm_unreachable("invalid variant!"); |
7465 | | case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; |
7466 | | } |
7467 | | |
7468 | | // Search the table. |
7469 | | auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); |
7470 | | |
7471 | | if (MnemonicRange.first == MnemonicRange.second) |
7472 | | return false; |
7473 | | |
7474 | | for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; |
7475 | | it != ie; ++it) { |
7476 | | const FeatureBitset &RequiredFeatures = |
7477 | | FeatureBitsets[it->RequiredFeaturesIdx]; |
7478 | | if ((AvailableFeatures & RequiredFeatures) == RequiredFeatures) |
7479 | | return true; |
7480 | | } |
7481 | | return false; |
7482 | | } |
7483 | | |
7484 | | #endif // GET_MNEMONIC_CHECKER |
7485 | | |