/src/build/lib/Target/VE/VEGenCallingConv.inc

Source (jump to first uncovered line)
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Calling Convention Implementation Fragment                                 *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

#ifndef GET_CC_REGISTER_LISTS

static bool CC_VE2(unsigned ValNo, MVT ValVT,
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
                   ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_VE_C(unsigned ValNo, MVT ValVT,
                    MVT LocVT, CCValAssign::LocInfo LocInfo,
                    ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State);
static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State);


static bool CC_VE2(unsigned ValNo, MVT ValVT,
                   MVT LocVT, CCValAssign::LocInfo LocInfo,
                   ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::f32) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::f128) {
    int64_t Offset1 = State.AllocateStack(16, Align(16));
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
    return false;
  }

  int64_t Offset2 = State.AllocateStack(
    State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), Align(8));
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
  return false;

  return true; // CC didn't match.
}


static bool CC_VE_C(unsigned ValNo, MVT ValVT,
                    MVT LocVT, CCValAssign::LocInfo LocInfo,
                    ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::f32) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64) {
    static const MCPhysReg RegList1[] = {
      VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
    };
    if (unsigned Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f128) {
    static const MCPhysReg RegList2[] = {
      VE::Q0, VE::Q1, VE::Q2, VE::Q3
    };
    static const MCPhysReg RegList3[] = {
      VE::SX0, VE::SX1, VE::SX3, VE::SX5
    };
    if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (!CC_VE_C_Stack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
    return false;

  return true; // CC didn't match.
}


static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::f128) {
    static const MCPhysReg ShadowRegList1[] = {
      VE::SX7
    };
    int64_t Offset2 = State.AllocateStack(16, Align(16), ShadowRegList1);
    State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
    return false;
  }

  int64_t Offset3 = State.AllocateStack(
    State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), Align(8));
  State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
  return false;

  return true; // CC didn't match.
}


static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::v256i32 ||
      LocVT == MVT::v256f32 ||
      LocVT == MVT::v256i64 ||
      LocVT == MVT::v256f64) {
    static const MCPhysReg RegList1[] = {
      VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
    };
    if (unsigned Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v512i32 ||
      LocVT == MVT::v512f32) {
    static const MCPhysReg RegList2[] = {
      VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
    };
    if (unsigned Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v256i1) {
    static const MCPhysReg RegList3[] = {
      VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
    };
    if (unsigned Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v512i1) {
    static const MCPhysReg RegList4[] = {
      VE::VMP1, VE::VMP2, VE::VMP3
    };
    static const MCPhysReg RegList5[] = {
      VE::VM1, VE::VM3, VE::VM5
    };
    if (unsigned Reg = State.AllocateReg(RegList4, RegList5)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (!CC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
    return false;

  return true; // CC didn't match.
}


static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
                       MVT LocVT, CCValAssign::LocInfo LocInfo,
                       ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::i1 ||
      LocVT == MVT::i8 ||
      LocVT == MVT::i16 ||
      LocVT == MVT::i32) {
    LocVT = MVT::i64;
    if (ArgFlags.isSExt())
      LocInfo = CCValAssign::SExt;
    else if (ArgFlags.isZExt())
      LocInfo = CCValAssign::ZExt;
    else
      LocInfo = CCValAssign::AExt;
  }

  if (LocVT == MVT::f32) {
    LocVT = MVT::i64;
    LocInfo = CCValAssign::BCvt;
  }

  if (LocVT == MVT::i64 ||
      LocVT == MVT::f64) {
    static const MCPhysReg RegList1[] = {
      VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
    };
    if (unsigned Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::f128) {
    static const MCPhysReg RegList2[] = {
      VE::Q0, VE::Q1, VE::Q2, VE::Q3
    };
    static const MCPhysReg RegList3[] = {
      VE::SX0, VE::SX1, VE::SX3, VE::SX5
    };
    if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  return true; // CC didn't match.
}


static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
                          MVT LocVT, CCValAssign::LocInfo LocInfo,
                          ISD::ArgFlagsTy ArgFlags, CCState &State) {

  if (LocVT == MVT::v256i32 ||
      LocVT == MVT::v256f32 ||
      LocVT == MVT::v256i64 ||
      LocVT == MVT::v256f64) {
    static const MCPhysReg RegList1[] = {
      VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
    };
    if (unsigned Reg = State.AllocateReg(RegList1)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v512i32 ||
      LocVT == MVT::v512f32) {
    static const MCPhysReg RegList2[] = {
      VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
    };
    if (unsigned Reg = State.AllocateReg(RegList2)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v256i1) {
    static const MCPhysReg RegList3[] = {
      VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
    };
    if (unsigned Reg = State.AllocateReg(RegList3)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (LocVT == MVT::v512i1) {
    static const MCPhysReg RegList4[] = {
      VE::VMP1, VE::VMP2, VE::VMP3
    };
    static const MCPhysReg RegList5[] = {
      VE::VM1, VE::VM3, VE::VM5
    };
    if (unsigned Reg = State.AllocateReg(RegList4, RegList5)) {
      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
      return false;
    }
  }

  if (!RetCC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
    return false;

  return true; // CC didn't match.
}

#else

const MCRegister CC_VE2_ArgRegs[] = { 0 };
const MCRegister CC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
const MCRegister CC_VE_C_Stack_ArgRegs[] = { 0 };
const MCRegister CC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
const MCRegister RetCC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
const MCRegister RetCC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };

#endif // CC_REGISTER_LIST

Coverage Report

Created: 2024-01-17 10:31

Line	Count	Source (jump to first uncovered line)
1		/===- TableGen'erated file -------------------------------------- C++ --===\
2		\|* *\|
3		\|* Calling Convention Implementation Fragment *\|
4		\|* *\|
5		\|* Automatically generated file, do not edit! *\|
6		\|* *\|
7		\===----------------------------------------------------------------------===/
8
9		#ifndef GET_CC_REGISTER_LISTS
10
11		static bool CC_VE2(unsigned ValNo, MVT ValVT,
12		MVT LocVT, CCValAssign::LocInfo LocInfo,
13		ISD::ArgFlagsTy ArgFlags, CCState &State);
14		static bool CC_VE_C(unsigned ValNo, MVT ValVT,
15		MVT LocVT, CCValAssign::LocInfo LocInfo,
16		ISD::ArgFlagsTy ArgFlags, CCState &State);
17		static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
18		MVT LocVT, CCValAssign::LocInfo LocInfo,
19		ISD::ArgFlagsTy ArgFlags, CCState &State);
20		static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
21		MVT LocVT, CCValAssign::LocInfo LocInfo,
22		ISD::ArgFlagsTy ArgFlags, CCState &State);
23		static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
24		MVT LocVT, CCValAssign::LocInfo LocInfo,
25		ISD::ArgFlagsTy ArgFlags, CCState &State);
26		static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
27		MVT LocVT, CCValAssign::LocInfo LocInfo,
28		ISD::ArgFlagsTy ArgFlags, CCState &State);
29
30
31		static bool CC_VE2(unsigned ValNo, MVT ValVT,
32		MVT LocVT, CCValAssign::LocInfo LocInfo,
33	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
34
35	0	if (LocVT == MVT::i1 \|\|
36	0	LocVT == MVT::i8 \|\|
37	0	LocVT == MVT::i16 \|\|
38	0	LocVT == MVT::i32) {
39	0	LocVT = MVT::i64;
40	0	if (ArgFlags.isSExt())
41	0	LocInfo = CCValAssign::SExt;
42	0	else if (ArgFlags.isZExt())
43	0	LocInfo = CCValAssign::ZExt;
44	0	else
45	0	LocInfo = CCValAssign::AExt;
46	0	}
47
48	0	if (LocVT == MVT::f32) {
49	0	LocVT = MVT::i64;
50	0	LocInfo = CCValAssign::BCvt;
51	0	}
52
53	0	if (LocVT == MVT::f128) {
54	0	int64_t Offset1 = State.AllocateStack(16, Align(16));
55	0	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo));
56	0	return false;
57	0	}
58
59	0	int64_t Offset2 = State.AllocateStack(
60	0	State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), Align(8));
61	0	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
62	0	return false;
63
64	0	return true; // CC didn't match.
65	0	}
66
67
68		static bool CC_VE_C(unsigned ValNo, MVT ValVT,
69		MVT LocVT, CCValAssign::LocInfo LocInfo,
70	8.29k	ISD::ArgFlagsTy ArgFlags, CCState &State) {
71
72	8.29k	if (LocVT == MVT::i1 \|\|
73	8.29k	LocVT == MVT::i8 \|\|
74	8.29k	LocVT == MVT::i16 \|\|
75	8.29k	LocVT == MVT::i32) {
76	4.24k	LocVT = MVT::i64;
77	4.24k	if (ArgFlags.isSExt())
78	0	LocInfo = CCValAssign::SExt;
79	4.24k	else if (ArgFlags.isZExt())
80	0	LocInfo = CCValAssign::ZExt;
81	4.24k	else
82	4.24k	LocInfo = CCValAssign::AExt;
83	4.24k	}
84
85	8.29k	if (LocVT == MVT::f32) {
86	857	LocVT = MVT::i64;
87	857	LocInfo = CCValAssign::BCvt;
88	857	}
89
90	8.29k	if (LocVT == MVT::i64 \|\|
91	8.29k	LocVT == MVT::f64) {
92	8.29k	static const MCPhysReg RegList1[] = {
93	8.29k	VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
94	8.29k	};
95	8.29k	if (unsigned Reg = State.AllocateReg(RegList1)) {
96	8.29k	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
97	8.29k	return false;
98	8.29k	}
99	8.29k	}
100
101	0	if (LocVT == MVT::f128) {
102	0	static const MCPhysReg RegList2[] = {
103	0	VE::Q0, VE::Q1, VE::Q2, VE::Q3
104	0	};
105	0	static const MCPhysReg RegList3[] = {
106	0	VE::SX0, VE::SX1, VE::SX3, VE::SX5
107	0	};
108	0	if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
109	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
110	0	return false;
111	0	}
112	0	}
113
114	0	if (!CC_VE_C_Stack(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
115	0	return false;
116
117	0	return true; // CC didn't match.
118	0	}
119
120
121		static bool CC_VE_C_Stack(unsigned ValNo, MVT ValVT,
122		MVT LocVT, CCValAssign::LocInfo LocInfo,
123	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
124
125	0	if (LocVT == MVT::f128) {
126	0	static const MCPhysReg ShadowRegList1[] = {
127	0	VE::SX7
128	0	};
129	0	int64_t Offset2 = State.AllocateStack(16, Align(16), ShadowRegList1);
130	0	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo));
131	0	return false;
132	0	}
133
134	0	int64_t Offset3 = State.AllocateStack(
135	0	State.getMachineFunction().getDataLayout().getTypeAllocSize(EVT(LocVT).getTypeForEVT(State.getContext())), Align(8));
136	0	State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo));
137	0	return false;
138
139	0	return true; // CC didn't match.
140	0	}
141
142
143		static bool CC_VE_Fast(unsigned ValNo, MVT ValVT,
144		MVT LocVT, CCValAssign::LocInfo LocInfo,
145	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
146
147	0	if (LocVT == MVT::v256i32 \|\|
148	0	LocVT == MVT::v256f32 \|\|
149	0	LocVT == MVT::v256i64 \|\|
150	0	LocVT == MVT::v256f64) {
151	0	static const MCPhysReg RegList1[] = {
152	0	VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
153	0	};
154	0	if (unsigned Reg = State.AllocateReg(RegList1)) {
155	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
156	0	return false;
157	0	}
158	0	}
159
160	0	if (LocVT == MVT::v512i32 \|\|
161	0	LocVT == MVT::v512f32) {
162	0	static const MCPhysReg RegList2[] = {
163	0	VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
164	0	};
165	0	if (unsigned Reg = State.AllocateReg(RegList2)) {
166	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
167	0	return false;
168	0	}
169	0	}
170
171	0	if (LocVT == MVT::v256i1) {
172	0	static const MCPhysReg RegList3[] = {
173	0	VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
174	0	};
175	0	if (unsigned Reg = State.AllocateReg(RegList3)) {
176	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
177	0	return false;
178	0	}
179	0	}
180
181	0	if (LocVT == MVT::v512i1) {
182	0	static const MCPhysReg RegList4[] = {
183	0	VE::VMP1, VE::VMP2, VE::VMP3
184	0	};
185	0	static const MCPhysReg RegList5[] = {
186	0	VE::VM1, VE::VM3, VE::VM5
187	0	};
188	0	if (unsigned Reg = State.AllocateReg(RegList4, RegList5)) {
189	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
190	0	return false;
191	0	}
192	0	}
193
194	0	if (!CC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
195	0	return false;
196
197	0	return true; // CC didn't match.
198	0	}
199
200
201		static bool RetCC_VE_C(unsigned ValNo, MVT ValVT,
202		MVT LocVT, CCValAssign::LocInfo LocInfo,
203	6.81k	ISD::ArgFlagsTy ArgFlags, CCState &State) {
204
205	6.81k	if (LocVT == MVT::i1 \|\|
206	6.81k	LocVT == MVT::i8 \|\|
207	6.81k	LocVT == MVT::i16 \|\|
208	6.81k	LocVT == MVT::i32) {
209	2.09k	LocVT = MVT::i64;
210	2.09k	if (ArgFlags.isSExt())
211	0	LocInfo = CCValAssign::SExt;
212	2.09k	else if (ArgFlags.isZExt())
213	0	LocInfo = CCValAssign::ZExt;
214	2.09k	else
215	2.09k	LocInfo = CCValAssign::AExt;
216	2.09k	}
217
218	6.81k	if (LocVT == MVT::f32) {
219	1.37k	LocVT = MVT::i64;
220	1.37k	LocInfo = CCValAssign::BCvt;
221	1.37k	}
222
223	6.81k	if (LocVT == MVT::i64 \|\|
224	6.81k	LocVT == MVT::f64) {
225	6.81k	static const MCPhysReg RegList1[] = {
226	6.81k	VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7
227	6.81k	};
228	6.81k	if (unsigned Reg = State.AllocateReg(RegList1)) {
229	6.81k	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
230	6.81k	return false;
231	6.81k	}
232	6.81k	}
233
234	0	if (LocVT == MVT::f128) {
235	0	static const MCPhysReg RegList2[] = {
236	0	VE::Q0, VE::Q1, VE::Q2, VE::Q3
237	0	};
238	0	static const MCPhysReg RegList3[] = {
239	0	VE::SX0, VE::SX1, VE::SX3, VE::SX5
240	0	};
241	0	if (unsigned Reg = State.AllocateReg(RegList2, RegList3)) {
242	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
243	0	return false;
244	0	}
245	0	}
246
247	0	return true; // CC didn't match.
248	0	}
249
250
251		static bool RetCC_VE_Fast(unsigned ValNo, MVT ValVT,
252		MVT LocVT, CCValAssign::LocInfo LocInfo,
253	0	ISD::ArgFlagsTy ArgFlags, CCState &State) {
254
255	0	if (LocVT == MVT::v256i32 \|\|
256	0	LocVT == MVT::v256f32 \|\|
257	0	LocVT == MVT::v256i64 \|\|
258	0	LocVT == MVT::v256f64) {
259	0	static const MCPhysReg RegList1[] = {
260	0	VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
261	0	};
262	0	if (unsigned Reg = State.AllocateReg(RegList1)) {
263	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
264	0	return false;
265	0	}
266	0	}
267
268	0	if (LocVT == MVT::v512i32 \|\|
269	0	LocVT == MVT::v512f32) {
270	0	static const MCPhysReg RegList2[] = {
271	0	VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7
272	0	};
273	0	if (unsigned Reg = State.AllocateReg(RegList2)) {
274	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
275	0	return false;
276	0	}
277	0	}
278
279	0	if (LocVT == MVT::v256i1) {
280	0	static const MCPhysReg RegList3[] = {
281	0	VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7
282	0	};
283	0	if (unsigned Reg = State.AllocateReg(RegList3)) {
284	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
285	0	return false;
286	0	}
287	0	}
288
289	0	if (LocVT == MVT::v512i1) {
290	0	static const MCPhysReg RegList4[] = {
291	0	VE::VMP1, VE::VMP2, VE::VMP3
292	0	};
293	0	static const MCPhysReg RegList5[] = {
294	0	VE::VM1, VE::VM3, VE::VM5
295	0	};
296	0	if (unsigned Reg = State.AllocateReg(RegList4, RegList5)) {
297	0	State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
298	0	return false;
299	0	}
300	0	}
301
302	0	if (!RetCC_VE_C(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State))
303	0	return false;
304
305	0	return true; // CC didn't match.
306	0	}
307
308		#else
309
310		const MCRegister CC_VE2_ArgRegs[] = { 0 };
311		const MCRegister CC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
312		const MCRegister CC_VE_C_Stack_ArgRegs[] = { 0 };
313		const MCRegister CC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
314		const MCRegister RetCC_VE_C_ArgRegs[] = { VE::SX0, VE::SX1, VE::SX2, VE::SX3, VE::SX4, VE::SX5, VE::SX6, VE::SX7 };
315		const MCRegister RetCC_VE_Fast_ArgRegs[] = { VE::V0, VE::V1, VE::V2, VE::V3, VE::V4, VE::V5, VE::V6, VE::V7, VE::VM1, VE::VM2, VE::VM3, VE::VM4, VE::VM5, VE::VM6, VE::VM7 };
316
317		#endif // CC_REGISTER_LIST